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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2008-10-03 06:52:33 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-10-03 06:52:33 -0400
commit56f68556d7bbb51dd158c74deb09c783345bfbbd (patch)
tree536e6e3c7063b1eee927194dda257602bd3dc66f /arch
parentfd9470ce3ac6fb54d6026e4b1cdab0936e34805e (diff)
parent7c8ad9828e793573877fd60868bb5d2f1e3b64da (diff)
Merge unstable branch 'omap-rmk'
Merge branch 'omap-rmk' into omap-all
Diffstat (limited to 'arch')
-rw-r--r--arch/alpha/kernel/osf_sys.c19
-rw-r--r--arch/arm/Kconfig5
-rw-r--r--arch/arm/configs/ams_delta_defconfig1314
-rw-r--r--arch/arm/configs/n770_defconfig1421
-rw-r--r--arch/arm/configs/omap_2430sdp_defconfig1304
-rw-r--r--arch/arm/configs/omap_apollon_2420_defconfig962
-rw-r--r--arch/arm/configs/omap_generic_1510_defconfig1172
-rw-r--r--arch/arm/configs/omap_generic_1610_defconfig1178
-rw-r--r--arch/arm/configs/omap_generic_1710_defconfig1088
-rw-r--r--arch/arm/configs/omap_generic_2420_defconfig655
-rw-r--r--arch/arm/configs/omap_h2_1610_defconfig509
-rw-r--r--arch/arm/configs/omap_h4_2420_defconfig1120
-rw-r--r--arch/arm/configs/omap_innovator_1510_defconfig1253
-rw-r--r--arch/arm/configs/omap_innovator_1610_defconfig839
-rw-r--r--arch/arm/configs/omap_osk_5912_defconfig169
-rw-r--r--arch/arm/configs/omap_perseus2_730_defconfig928
-rw-r--r--arch/arm/configs/orion5x_defconfig146
-rw-r--r--arch/arm/configs/palmte_defconfig761
-rw-r--r--arch/arm/configs/palmtt_defconfig844
-rw-r--r--arch/arm/configs/palmz71_defconfig891
-rw-r--r--arch/arm/configs/sx1_defconfig1118
-rw-r--r--arch/arm/include/asm/byteorder.h25
-rw-r--r--arch/arm/lib/sha1.S2
-rw-r--r--arch/arm/mach-footbridge/time.c18
-rw-r--r--arch/arm/mach-omap1/clock.c10
-rw-r--r--arch/arm/mach-omap1/clock.h6
-rw-r--r--arch/arm/mach-omap1/mcbsp.c16
-rw-r--r--arch/arm/mach-omap1/serial.c12
-rw-r--r--arch/arm/mach-omap2/board-2430sdp.c2
-rw-r--r--arch/arm/mach-omap2/clock.c18
-rw-r--r--arch/arm/mach-omap2/cm.h2
-rw-r--r--arch/arm/mach-omap2/gpmc.c6
-rw-r--r--arch/arm/mach-omap2/id.c6
-rw-r--r--arch/arm/mach-omap2/irq.c4
-rw-r--r--arch/arm/mach-omap2/mcbsp.c8
-rw-r--r--arch/arm/mach-omap2/prm.h2
-rw-r--r--arch/arm/mach-omap2/serial.c16
-rw-r--r--arch/arm/mach-orion5x/common.h1
-rw-r--r--arch/arm/mach-orion5x/dns323-setup.c6
-rw-r--r--arch/arm/mach-orion5x/kurobox_pro-setup.c4
-rw-r--r--arch/arm/mach-orion5x/pci.c13
-rw-r--r--arch/arm/mach-orion5x/ts209-setup.c9
-rw-r--r--arch/arm/mach-orion5x/ts409-setup.c9
-rw-r--r--arch/arm/mach-pxa/corgi.c2
-rw-r--r--arch/arm/mach-pxa/poodle.c2
-rw-r--r--arch/arm/mach-pxa/spitz.c2
-rw-r--r--arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h10
-rw-r--r--arch/arm/mach-s3c2410/nor-simtec.c3
-rw-r--r--arch/arm/mach-s3c2412/mach-jive.c2
-rw-r--r--arch/arm/plat-mxc/clock.c1
-rw-r--r--arch/arm/plat-omap/Makefile2
-rw-r--r--arch/arm/plat-omap/common.c36
-rw-r--r--arch/arm/plat-omap/dma.c8
-rw-r--r--arch/arm/plat-omap/dmtimer.c2
-rw-r--r--arch/arm/plat-omap/gpio.c72
-rw-r--r--arch/arm/plat-omap/include/mach/control.h6
-rw-r--r--arch/arm/plat-omap/include/mach/fpga.h12
-rw-r--r--arch/arm/plat-omap/include/mach/gpio.h2
-rw-r--r--arch/arm/plat-omap/include/mach/hardware.h2
-rw-r--r--arch/arm/plat-omap/include/mach/io.h56
-rw-r--r--arch/arm/plat-omap/include/mach/mcbsp.h5
-rw-r--r--arch/arm/plat-omap/include/mach/pm.h4
-rw-r--r--arch/arm/plat-omap/include/mach/sdrc.h6
-rw-r--r--arch/arm/plat-omap/include/mach/serial.h12
-rw-r--r--arch/arm/plat-omap/io.c83
-rw-r--r--arch/arm/plat-omap/mcbsp.c47
-rw-r--r--arch/arm/plat-s3c24xx/gpiolib.c12
-rw-r--r--arch/arm/plat-s3c24xx/pwm-clock.c6
-rw-r--r--arch/arm/plat-s3c24xx/pwm.c5
-rw-r--r--arch/blackfin/Kconfig1
-rw-r--r--arch/blackfin/Makefile26
-rw-r--r--arch/blackfin/include/asm/.gitignore1
-rw-r--r--arch/blackfin/include/asm/Kbuild3
-rw-r--r--arch/blackfin/include/asm/a.out.h19
-rw-r--r--arch/blackfin/include/asm/atomic.h144
-rw-r--r--arch/blackfin/include/asm/auxvec.h4
-rw-r--r--arch/blackfin/include/asm/bfin-global.h117
-rw-r--r--arch/blackfin/include/asm/bfin5xx_spi.h137
-rw-r--r--arch/blackfin/include/asm/bfin_simple_timer.h13
-rw-r--r--arch/blackfin/include/asm/bfin_sport.h175
-rw-r--r--arch/blackfin/include/asm/bitops.h218
-rw-r--r--arch/blackfin/include/asm/blackfin.h92
-rw-r--r--arch/blackfin/include/asm/bug.h17
-rw-r--r--arch/blackfin/include/asm/bugs.h16
-rw-r--r--arch/blackfin/include/asm/byteorder.h48
-rw-r--r--arch/blackfin/include/asm/cache.h29
-rw-r--r--arch/blackfin/include/asm/cacheflush.h90
-rw-r--r--arch/blackfin/include/asm/cdef_LPBlackfin.h328
-rw-r--r--arch/blackfin/include/asm/checksum.h100
-rw-r--r--arch/blackfin/include/asm/clocks.h70
-rw-r--r--arch/blackfin/include/asm/context.S355
-rw-r--r--arch/blackfin/include/asm/cplb-mpu.h61
-rw-r--r--arch/blackfin/include/asm/cplb.h110
-rw-r--r--arch/blackfin/include/asm/cplbinit.h95
-rw-r--r--arch/blackfin/include/asm/cpumask.h6
-rw-r--r--arch/blackfin/include/asm/cputime.h6
-rw-r--r--arch/blackfin/include/asm/current.h23
-rw-r--r--arch/blackfin/include/asm/def_LPBlackfin.h712
-rw-r--r--arch/blackfin/include/asm/delay.h62
-rw-r--r--arch/blackfin/include/asm/device.h7
-rw-r--r--arch/blackfin/include/asm/div64.h1
-rw-r--r--arch/blackfin/include/asm/dma-mapping.h83
-rw-r--r--arch/blackfin/include/asm/dma.h205
-rw-r--r--arch/blackfin/include/asm/dpmc.h57
-rw-r--r--arch/blackfin/include/asm/early_printk.h28
-rw-r--r--arch/blackfin/include/asm/elf.h127
-rw-r--r--arch/blackfin/include/asm/emergency-restart.h6
-rw-r--r--arch/blackfin/include/asm/entry.h61
-rw-r--r--arch/blackfin/include/asm/errno.h6
-rw-r--r--arch/blackfin/include/asm/fb.h12
-rw-r--r--arch/blackfin/include/asm/fcntl.h13
-rw-r--r--arch/blackfin/include/asm/fixed_code.h46
-rw-r--r--arch/blackfin/include/asm/flat.h58
-rw-r--r--arch/blackfin/include/asm/futex.h6
-rw-r--r--arch/blackfin/include/asm/gpio.h456
-rw-r--r--arch/blackfin/include/asm/gptimers.h191
-rw-r--r--arch/blackfin/include/asm/hardirq.h45
-rw-r--r--arch/blackfin/include/asm/hw_irq.h6
-rw-r--r--arch/blackfin/include/asm/io.h212
-rw-r--r--arch/blackfin/include/asm/ioctl.h1
-rw-r--r--arch/blackfin/include/asm/ioctls.h87
-rw-r--r--arch/blackfin/include/asm/ipcbuf.h30
-rw-r--r--arch/blackfin/include/asm/irq.h72
-rw-r--r--arch/blackfin/include/asm/irq_handler.h33
-rw-r--r--arch/blackfin/include/asm/irq_regs.h1
-rw-r--r--arch/blackfin/include/asm/kdebug.h1
-rw-r--r--arch/blackfin/include/asm/kgdb.h184
-rw-r--r--arch/blackfin/include/asm/kmap_types.h21
-rw-r--r--arch/blackfin/include/asm/l1layout.h31
-rw-r--r--arch/blackfin/include/asm/linkage.h7
-rw-r--r--arch/blackfin/include/asm/local.h6
-rw-r--r--arch/blackfin/include/asm/mem_map.h12
-rw-r--r--arch/blackfin/include/asm/mman.h43
-rw-r--r--arch/blackfin/include/asm/mmu.h32
-rw-r--r--arch/blackfin/include/asm/mmu_context.h183
-rw-r--r--arch/blackfin/include/asm/module.h20
-rw-r--r--arch/blackfin/include/asm/msgbuf.h31
-rw-r--r--arch/blackfin/include/asm/mutex.h9
-rw-r--r--arch/blackfin/include/asm/nand.h47
-rw-r--r--arch/blackfin/include/asm/page.h88
-rw-r--r--arch/blackfin/include/asm/page_offset.h6
-rw-r--r--arch/blackfin/include/asm/param.h22
-rw-r--r--arch/blackfin/include/asm/pci.h148
-rw-r--r--arch/blackfin/include/asm/percpu.h6
-rw-r--r--arch/blackfin/include/asm/pgalloc.h8
-rw-r--r--arch/blackfin/include/asm/pgtable.h96
-rw-r--r--arch/blackfin/include/asm/poll.h24
-rw-r--r--arch/blackfin/include/asm/portmux.h1188
-rw-r--r--arch/blackfin/include/asm/posix_types.h61
-rw-r--r--arch/blackfin/include/asm/processor.h158
-rw-r--r--arch/blackfin/include/asm/ptrace.h168
-rw-r--r--arch/blackfin/include/asm/reboot.h20
-rw-r--r--arch/blackfin/include/asm/resource.h6
-rw-r--r--arch/blackfin/include/asm/scatterlist.h28
-rw-r--r--arch/blackfin/include/asm/sections.h7
-rw-r--r--arch/blackfin/include/asm/segment.h7
-rw-r--r--arch/blackfin/include/asm/sembuf.h25
-rw-r--r--arch/blackfin/include/asm/serial.h5
-rw-r--r--arch/blackfin/include/asm/setup.h17
-rw-r--r--arch/blackfin/include/asm/shmbuf.h42
-rw-r--r--arch/blackfin/include/asm/shmparam.h6
-rw-r--r--arch/blackfin/include/asm/sigcontext.h55
-rw-r--r--arch/blackfin/include/asm/siginfo.h35
-rw-r--r--arch/blackfin/include/asm/signal.h160
-rw-r--r--arch/blackfin/include/asm/socket.h56
-rw-r--r--arch/blackfin/include/asm/sockios.h13
-rw-r--r--arch/blackfin/include/asm/spinlock.h6
-rw-r--r--arch/blackfin/include/asm/stat.h63
-rw-r--r--arch/blackfin/include/asm/statfs.h6
-rw-r--r--arch/blackfin/include/asm/string.h137
-rw-r--r--arch/blackfin/include/asm/system.h221
-rw-r--r--arch/blackfin/include/asm/termbits.h198
-rw-r--r--arch/blackfin/include/asm/termios.h94
-rw-r--r--arch/blackfin/include/asm/thread_info.h135
-rw-r--r--arch/blackfin/include/asm/time.h40
-rw-r--r--arch/blackfin/include/asm/timex.h23
-rw-r--r--arch/blackfin/include/asm/tlb.h16
-rw-r--r--arch/blackfin/include/asm/tlbflush.h56
-rw-r--r--arch/blackfin/include/asm/topology.h6
-rw-r--r--arch/blackfin/include/asm/trace.h94
-rw-r--r--arch/blackfin/include/asm/traps.h131
-rw-r--r--arch/blackfin/include/asm/types.h36
-rw-r--r--arch/blackfin/include/asm/uaccess.h271
-rw-r--r--arch/blackfin/include/asm/ucontext.h17
-rw-r--r--arch/blackfin/include/asm/unaligned.h11
-rw-r--r--arch/blackfin/include/asm/unistd.h438
-rw-r--r--arch/blackfin/include/asm/user.h89
-rw-r--r--arch/blackfin/kernel/entry.S2
-rw-r--r--arch/blackfin/mach-bf527/head.S4
-rw-r--r--arch/blackfin/mach-bf527/include/mach/anomaly.h104
-rw-r--r--arch/blackfin/mach-bf527/include/mach/bf527.h127
-rw-r--r--arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h195
-rw-r--r--arch/blackfin/mach-bf527/include/mach/bfin_sir.h142
-rw-r--r--arch/blackfin/mach-bf527/include/mach/blackfin.h93
-rw-r--r--arch/blackfin/mach-bf527/include/mach/cdefBF522.h46
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-rw-r--r--arch/blackfin/mach-bf527/include/mach/cdefBF527.h626
-rw-r--r--arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h1204
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-rw-r--r--arch/blackfin/mach-bf527/include/mach/defBF525.h713
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-rw-r--r--arch/blackfin/mach-bf527/include/mach/dma.h62
-rw-r--r--arch/blackfin/mach-bf527/include/mach/irq.h259
-rw-r--r--arch/blackfin/mach-bf527/include/mach/mem_init.h310
-rw-r--r--arch/blackfin/mach-bf527/include/mach/mem_map.h102
-rw-r--r--arch/blackfin/mach-bf527/include/mach/portmux.h207
-rw-r--r--arch/blackfin/mach-bf533/head.S4
-rw-r--r--arch/blackfin/mach-bf533/include/mach/anomaly.h272
-rw-r--r--arch/blackfin/mach-bf533/include/mach/bf533.h161
-rw-r--r--arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h164
-rw-r--r--arch/blackfin/mach-bf533/include/mach/bfin_sir.h125
-rw-r--r--arch/blackfin/mach-bf533/include/mach/blackfin.h60
-rw-r--r--arch/blackfin/mach-bf533/include/mach/cdefBF532.h767
-rw-r--r--arch/blackfin/mach-bf533/include/mach/defBF532.h1266
-rw-r--r--arch/blackfin/mach-bf533/include/mach/dma.h54
-rw-r--r--arch/blackfin/mach-bf533/include/mach/irq.h173
-rw-r--r--arch/blackfin/mach-bf533/include/mach/mem_init.h297
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-rw-r--r--arch/blackfin/mach-bf533/include/mach/portmux.h67
-rw-r--r--arch/blackfin/mach-bf537/boards/stamp.c27
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-rw-r--r--arch/blackfin/mach-bf537/include/mach/bfin_sir.h142
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-rw-r--r--arch/ia64/include/asm/io.h10
-rw-r--r--arch/ia64/kernel/smpboot.c1
-rw-r--r--arch/m68k/atari/atakeyb.c9
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-rw-r--r--arch/mips/kernel/setup.c42
-rw-r--r--arch/mips/pci/pci-ip27.c1
-rw-r--r--arch/mips/rb532/devices.c16
-rw-r--r--arch/mips/txx9/generic/setup.c3
-rw-r--r--arch/parisc/hpux/fs.c30
-rw-r--r--arch/powerpc/boot/dts/mpc8641_hpcn.dts2
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-rw-r--r--arch/powerpc/boot/dts/tqm8548.dts3
-rwxr-xr-xarch/powerpc/boot/wrapper2
-rw-r--r--arch/powerpc/configs/83xx/asp8347_defconfig (renamed from arch/powerpc/configs/asp8347_defconfig)312
-rw-r--r--arch/powerpc/configs/83xx/mpc8313_rdb_defconfig188
-rw-r--r--arch/powerpc/configs/83xx/mpc8315_rdb_defconfig188
-rw-r--r--arch/powerpc/configs/83xx/mpc832x_mds_defconfig172
-rw-r--r--arch/powerpc/configs/83xx/mpc832x_rdb_defconfig176
-rw-r--r--arch/powerpc/configs/83xx/mpc834x_itx_defconfig175
-rw-r--r--arch/powerpc/configs/83xx/mpc834x_itxgp_defconfig172
-rw-r--r--arch/powerpc/configs/83xx/mpc834x_mds_defconfig168
-rw-r--r--arch/powerpc/configs/83xx/mpc836x_mds_defconfig172
-rw-r--r--arch/powerpc/configs/83xx/mpc836x_rdk_defconfig183
-rw-r--r--arch/powerpc/configs/83xx/mpc837x_mds_defconfig351
-rw-r--r--arch/powerpc/configs/83xx/mpc837x_rdb_defconfig340
-rw-r--r--arch/powerpc/configs/83xx/sbc834x_defconfig239
-rw-r--r--arch/powerpc/configs/85xx/ksi8560_defconfig95
-rw-r--r--arch/powerpc/configs/85xx/mpc8536_ds_defconfig (renamed from arch/powerpc/configs/mpc8536_ds_defconfig)167
-rw-r--r--arch/powerpc/configs/85xx/mpc8540_ads_defconfig71
-rw-r--r--arch/powerpc/configs/85xx/mpc8544_ds_defconfig178
-rw-r--r--arch/powerpc/configs/85xx/mpc8560_ads_defconfig98
-rw-r--r--arch/powerpc/configs/85xx/mpc8568mds_defconfig121
-rw-r--r--arch/powerpc/configs/85xx/mpc8572_ds_defconfig177
-rw-r--r--arch/powerpc/configs/85xx/mpc85xx_cds_defconfig85
-rw-r--r--arch/powerpc/configs/85xx/sbc8548_defconfig63
-rw-r--r--arch/powerpc/configs/85xx/sbc8560_defconfig69
-rw-r--r--arch/powerpc/configs/85xx/stx_gp3_defconfig163
-rw-r--r--arch/powerpc/configs/85xx/tqm8540_defconfig112
-rw-r--r--arch/powerpc/configs/85xx/tqm8541_defconfig139
-rw-r--r--arch/powerpc/configs/85xx/tqm8548_defconfig129
-rw-r--r--arch/powerpc/configs/85xx/tqm8555_defconfig139
-rw-r--r--arch/powerpc/configs/85xx/tqm8560_defconfig139
-rw-r--r--arch/powerpc/configs/adder875_defconfig55
-rw-r--r--arch/powerpc/configs/c2k_defconfig245
-rw-r--r--arch/powerpc/configs/chrp32_defconfig141
-rw-r--r--arch/powerpc/configs/ep8248e_defconfig198
-rw-r--r--arch/powerpc/configs/ep88xc_defconfig57
-rw-r--r--arch/powerpc/configs/g5_defconfig227
-rw-r--r--arch/powerpc/configs/iseries_defconfig87
-rw-r--r--arch/powerpc/configs/linkstation_defconfig133
-rw-r--r--arch/powerpc/configs/maple_defconfig381
-rw-r--r--arch/powerpc/configs/mpc7448_hpc2_defconfig72
-rw-r--r--arch/powerpc/configs/mpc8272_ads_defconfig132
-rw-r--r--arch/powerpc/configs/mpc83xx_defconfig389
-rw-r--r--arch/powerpc/configs/mpc85xx_defconfig207
-rw-r--r--arch/powerpc/configs/mpc8610_hpcd_defconfig165
-rw-r--r--arch/powerpc/configs/mpc8641_hpcn_defconfig215
-rw-r--r--arch/powerpc/configs/mpc866_ads_defconfig61
-rw-r--r--arch/powerpc/configs/mpc885_ads_defconfig57
-rw-r--r--arch/powerpc/configs/pmac32_defconfig241
-rw-r--r--arch/powerpc/configs/ppc64_defconfig237
-rw-r--r--arch/powerpc/configs/ppc6xx_defconfig144
-rw-r--r--arch/powerpc/configs/pq2fads_defconfig147
-rw-r--r--arch/powerpc/configs/prpmc2800_defconfig125
-rw-r--r--arch/powerpc/configs/ps3_defconfig153
-rw-r--r--arch/powerpc/configs/pseries_defconfig172
-rw-r--r--arch/powerpc/configs/sbc8641d_defconfig173
-rw-r--r--arch/powerpc/configs/storcenter_defconfig113
-rw-r--r--arch/powerpc/include/asm/cpm2.h5
-rw-r--r--arch/powerpc/platforms/ps3/htab.c269
-rw-r--r--arch/powerpc/platforms/ps3/setup.c1
-rw-r--r--arch/powerpc/platforms/ps3/spu.c18
-rw-r--r--arch/powerpc/platforms/pseries/setup.c1
-rw-r--r--arch/powerpc/sysdev/cpm_common.c37
-rw-r--r--arch/powerpc/sysdev/qe_lib/ucc_fast.c4
-rw-r--r--arch/powerpc/sysdev/qe_lib/ucc_slow.c8
-rw-r--r--arch/s390/kernel/vmlinux.lds.S2
-rw-r--r--arch/sparc/Makefile8
-rw-r--r--arch/sparc/boot/Makefile6
-rw-r--r--arch/sparc/include/asm/smp_32.h25
-rw-r--r--arch/sparc/kernel/of_device.c19
-rw-r--r--arch/sparc/kernel/sun4d_smp.c16
-rw-r--r--arch/sparc/kernel/sun4m_smp.c12
-rw-r--r--arch/sparc64/Kconfig1
-rw-r--r--arch/sparc64/kernel/of_device.c20
-rw-r--r--arch/sparc64/mm/init.c2
-rw-r--r--arch/x86/configs/i386_defconfig303
-rw-r--r--arch/x86/configs/x86_64_defconfig258
-rw-r--r--arch/x86/kernel/cpuid.c15
-rw-r--r--arch/x86/kernel/msr.c38
-rw-r--r--arch/x86/kernel/tsc.c235
-rw-r--r--arch/x86/lib/msr-on-cpu.c22
-rw-r--r--arch/x86/pci/i386.c87
383 files changed, 80550 insertions, 3872 deletions
diff --git a/arch/alpha/kernel/osf_sys.c b/arch/alpha/kernel/osf_sys.c
index 6e943135f0e0..8509dad31204 100644
--- a/arch/alpha/kernel/osf_sys.c
+++ b/arch/alpha/kernel/osf_sys.c
@@ -121,24 +121,29 @@ osf_filldir(void *__buf, const char *name, int namlen, loff_t offset,
121 if (reclen > buf->count) 121 if (reclen > buf->count)
122 return -EINVAL; 122 return -EINVAL;
123 d_ino = ino; 123 d_ino = ino;
124 if (sizeof(d_ino) < sizeof(ino) && d_ino != ino) 124 if (sizeof(d_ino) < sizeof(ino) && d_ino != ino) {
125 buf->error = -EOVERFLOW;
125 return -EOVERFLOW; 126 return -EOVERFLOW;
127 }
126 if (buf->basep) { 128 if (buf->basep) {
127 if (put_user(offset, buf->basep)) 129 if (put_user(offset, buf->basep))
128 return -EFAULT; 130 goto Efault;
129 buf->basep = NULL; 131 buf->basep = NULL;
130 } 132 }
131 dirent = buf->dirent; 133 dirent = buf->dirent;
132 put_user(d_ino, &dirent->d_ino); 134 if (put_user(d_ino, &dirent->d_ino) ||
133 put_user(namlen, &dirent->d_namlen); 135 put_user(namlen, &dirent->d_namlen) ||
134 put_user(reclen, &dirent->d_reclen); 136 put_user(reclen, &dirent->d_reclen) ||
135 if (copy_to_user(dirent->d_name, name, namlen) || 137 copy_to_user(dirent->d_name, name, namlen) ||
136 put_user(0, dirent->d_name + namlen)) 138 put_user(0, dirent->d_name + namlen))
137 return -EFAULT; 139 goto Efault;
138 dirent = (void __user *)dirent + reclen; 140 dirent = (void __user *)dirent + reclen;
139 buf->dirent = dirent; 141 buf->dirent = dirent;
140 buf->count -= reclen; 142 buf->count -= reclen;
141 return 0; 143 return 0;
144Efault:
145 buf->error = -EFAULT;
146 return -EFAULT;
142} 147}
143 148
144asmlinkage int 149asmlinkage int
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 4b8acd2851f4..70dba1668907 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -810,6 +810,11 @@ config OABI_COMPAT
810 UNPREDICTABLE (in fact it can be predicted that it won't work 810 UNPREDICTABLE (in fact it can be predicted that it won't work
811 at all). If in doubt say Y. 811 at all). If in doubt say Y.
812 812
813config ARCH_FLATMEM_HAS_HOLES
814 bool
815 default y
816 depends on FLATMEM
817
813config ARCH_DISCONTIGMEM_ENABLE 818config ARCH_DISCONTIGMEM_ENABLE
814 bool 819 bool
815 default (ARCH_LH7A40X && !LH7A40X_CONTIGMEM) 820 default (ARCH_LH7A40X && !LH7A40X_CONTIGMEM)
diff --git a/arch/arm/configs/ams_delta_defconfig b/arch/arm/configs/ams_delta_defconfig
new file mode 100644
index 000000000000..2c4aa11f0b0d
--- /dev/null
+++ b/arch/arm/configs/ams_delta_defconfig
@@ -0,0 +1,1314 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.22-rc1-omap1
4# Thu Jun 7 04:28:32 2007
5#
6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8CONFIG_GENERIC_GPIO=y
9CONFIG_GENERIC_TIME=y
10CONFIG_GENERIC_CLOCKEVENTS=y
11CONFIG_MMU=y
12# CONFIG_NO_IOPORT is not set
13CONFIG_GENERIC_HARDIRQS=y
14CONFIG_STACKTRACE_SUPPORT=y
15CONFIG_LOCKDEP_SUPPORT=y
16CONFIG_TRACE_IRQFLAGS_SUPPORT=y
17CONFIG_HARDIRQS_SW_RESEND=y
18CONFIG_GENERIC_IRQ_PROBE=y
19CONFIG_RWSEM_GENERIC_SPINLOCK=y
20# CONFIG_ARCH_HAS_ILOG2_U32 is not set
21# CONFIG_ARCH_HAS_ILOG2_U64 is not set
22CONFIG_GENERIC_HWEIGHT=y
23CONFIG_GENERIC_CALIBRATE_DELAY=y
24CONFIG_ZONE_DMA=y
25CONFIG_VECTORS_BASE=0xffff0000
26CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
27
28#
29# Code maturity level options
30#
31CONFIG_EXPERIMENTAL=y
32CONFIG_BROKEN_ON_SMP=y
33CONFIG_LOCK_KERNEL=y
34CONFIG_INIT_ENV_ARG_LIMIT=32
35
36#
37# General setup
38#
39CONFIG_LOCALVERSION=""
40CONFIG_LOCALVERSION_AUTO=y
41# CONFIG_SWAP is not set
42CONFIG_SYSVIPC=y
43# CONFIG_IPC_NS is not set
44CONFIG_SYSVIPC_SYSCTL=y
45# CONFIG_POSIX_MQUEUE is not set
46# CONFIG_BSD_PROCESS_ACCT is not set
47# CONFIG_TASKSTATS is not set
48# CONFIG_UTS_NS is not set
49# CONFIG_AUDIT is not set
50# CONFIG_IKCONFIG is not set
51CONFIG_LOG_BUF_SHIFT=14
52CONFIG_SYSFS_DEPRECATED=y
53# CONFIG_RELAY is not set
54CONFIG_BLK_DEV_INITRD=y
55CONFIG_INITRAMFS_SOURCE=""
56CONFIG_CC_OPTIMIZE_FOR_SIZE=y
57CONFIG_SYSCTL=y
58# CONFIG_EMBEDDED is not set
59CONFIG_UID16=y
60CONFIG_SYSCTL_SYSCALL=y
61CONFIG_KALLSYMS=y
62# CONFIG_KALLSYMS_ALL is not set
63# CONFIG_KALLSYMS_EXTRA_PASS is not set
64CONFIG_HOTPLUG=y
65CONFIG_PRINTK=y
66CONFIG_BUG=y
67CONFIG_ELF_CORE=y
68CONFIG_BASE_FULL=y
69CONFIG_FUTEX=y
70CONFIG_ANON_INODES=y
71CONFIG_EPOLL=y
72CONFIG_SIGNALFD=y
73CONFIG_TIMERFD=y
74CONFIG_EVENTFD=y
75CONFIG_SHMEM=y
76CONFIG_VM_EVENT_COUNTERS=y
77CONFIG_SLAB=y
78# CONFIG_SLUB is not set
79# CONFIG_SLOB is not set
80CONFIG_RT_MUTEXES=y
81# CONFIG_TINY_SHMEM is not set
82CONFIG_BASE_SMALL=0
83
84#
85# Loadable module support
86#
87CONFIG_MODULES=y
88CONFIG_MODULE_UNLOAD=y
89CONFIG_MODULE_FORCE_UNLOAD=y
90# CONFIG_MODVERSIONS is not set
91# CONFIG_MODULE_SRCVERSION_ALL is not set
92CONFIG_KMOD=y
93
94#
95# Block layer
96#
97CONFIG_BLOCK=y
98# CONFIG_LBD is not set
99# CONFIG_BLK_DEV_IO_TRACE is not set
100# CONFIG_LSF is not set
101
102#
103# IO Schedulers
104#
105CONFIG_IOSCHED_NOOP=y
106CONFIG_IOSCHED_AS=y
107CONFIG_IOSCHED_DEADLINE=y
108CONFIG_IOSCHED_CFQ=y
109CONFIG_DEFAULT_AS=y
110# CONFIG_DEFAULT_DEADLINE is not set
111# CONFIG_DEFAULT_CFQ is not set
112# CONFIG_DEFAULT_NOOP is not set
113CONFIG_DEFAULT_IOSCHED="anticipatory"
114
115#
116# System Type
117#
118# CONFIG_ARCH_AAEC2000 is not set
119# CONFIG_ARCH_INTEGRATOR is not set
120# CONFIG_ARCH_REALVIEW is not set
121# CONFIG_ARCH_VERSATILE is not set
122# CONFIG_ARCH_AT91 is not set
123# CONFIG_ARCH_CLPS7500 is not set
124# CONFIG_ARCH_CLPS711X is not set
125# CONFIG_ARCH_CO285 is not set
126# CONFIG_ARCH_EBSA110 is not set
127# CONFIG_ARCH_EP93XX is not set
128# CONFIG_ARCH_FOOTBRIDGE is not set
129# CONFIG_ARCH_NETX is not set
130# CONFIG_ARCH_H720X is not set
131# CONFIG_ARCH_IMX is not set
132# CONFIG_ARCH_IOP13XX is not set
133# CONFIG_ARCH_IOP32X is not set
134# CONFIG_ARCH_IOP33X is not set
135# CONFIG_ARCH_IXP23XX is not set
136# CONFIG_ARCH_IXP2000 is not set
137# CONFIG_ARCH_IXP4XX is not set
138# CONFIG_ARCH_L7200 is not set
139# CONFIG_ARCH_KS8695 is not set
140# CONFIG_ARCH_NS9XXX is not set
141# CONFIG_ARCH_PNX4008 is not set
142# CONFIG_ARCH_PXA is not set
143# CONFIG_ARCH_RPC is not set
144# CONFIG_ARCH_SA1100 is not set
145# CONFIG_ARCH_S3C2410 is not set
146# CONFIG_ARCH_SHARK is not set
147# CONFIG_ARCH_LH7A40X is not set
148# CONFIG_ARCH_DAVINCI is not set
149CONFIG_ARCH_OMAP=y
150
151#
152# TI OMAP Implementations
153#
154CONFIG_ARCH_OMAP1=y
155# CONFIG_ARCH_OMAP2 is not set
156
157#
158# OMAP Feature Selections
159#
160# CONFIG_OMAP_RESET_CLOCKS is not set
161# CONFIG_OMAP_BOOT_TAG is not set
162# CONFIG_OMAP_GPIO_SWITCH is not set
163CONFIG_OMAP_MUX=y
164# CONFIG_OMAP_MUX_DEBUG is not set
165CONFIG_OMAP_MUX_WARNINGS=y
166CONFIG_OMAP_MCBSP=y
167CONFIG_OMAP_MMU_FWK=y
168CONFIG_OMAP_MBOX_FWK=m
169CONFIG_OMAP_MPU_TIMER=y
170# CONFIG_OMAP_32K_TIMER is not set
171CONFIG_OMAP_LL_DEBUG_UART1=y
172# CONFIG_OMAP_LL_DEBUG_UART2 is not set
173# CONFIG_OMAP_LL_DEBUG_UART3 is not set
174# CONFIG_OMAP_LL_DEBUG_LCD is not set
175CONFIG_OMAP_SERIAL_WAKE=y
176CONFIG_OMAP_DSP=m
177# CONFIG_OMAP_DSP_MBCMD_VERBOSE is not set
178# CONFIG_OMAP_DSP_TASK_MULTIOPEN is not set
179# CONFIG_OMAP_DSP_FBEXPORT is not set
180
181#
182# OMAP Core Type
183#
184# CONFIG_ARCH_OMAP730 is not set
185CONFIG_ARCH_OMAP15XX=y
186# CONFIG_ARCH_OMAP16XX is not set
187
188#
189# OMAP Board Type
190#
191# CONFIG_MACH_OMAP_INNOVATOR is not set
192# CONFIG_MACH_VOICEBLUE is not set
193# CONFIG_MACH_OMAP_PALMTE is not set
194# CONFIG_MACH_OMAP_PALMZ71 is not set
195# CONFIG_MACH_OMAP_PALMTT is not set
196# CONFIG_MACH_SX1 is not set
197CONFIG_MACH_AMS_DELTA=y
198# CONFIG_MACH_OMAP_GENERIC is not set
199
200#
201# OMAP CPU Speed
202#
203# CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER is not set
204# CONFIG_OMAP_ARM_168MHZ is not set
205CONFIG_OMAP_ARM_150MHZ=y
206# CONFIG_OMAP_ARM_120MHZ is not set
207# CONFIG_OMAP_ARM_60MHZ is not set
208# CONFIG_OMAP_ARM_30MHZ is not set
209
210#
211# Processor Type
212#
213CONFIG_CPU_32=y
214CONFIG_CPU_ARM925T=y
215CONFIG_CPU_32v4T=y
216CONFIG_CPU_ABRT_EV4T=y
217CONFIG_CPU_CACHE_V4WT=y
218CONFIG_CPU_CACHE_VIVT=y
219CONFIG_CPU_COPY_V4WB=y
220CONFIG_CPU_TLB_V4WBI=y
221CONFIG_CPU_CP15=y
222CONFIG_CPU_CP15_MMU=y
223
224#
225# Processor Features
226#
227# CONFIG_ARM_THUMB is not set
228# CONFIG_CPU_ICACHE_DISABLE is not set
229# CONFIG_CPU_DCACHE_DISABLE is not set
230CONFIG_CPU_DCACHE_WRITETHROUGH=y
231# CONFIG_OUTER_CACHE is not set
232
233#
234# Bus support
235#
236# CONFIG_ARCH_SUPPORTS_MSI is not set
237
238#
239# PCCARD (PCMCIA/CardBus) support
240#
241# CONFIG_PCCARD is not set
242
243#
244# Kernel Features
245#
246# CONFIG_TICK_ONESHOT is not set
247# CONFIG_NO_HZ is not set
248# CONFIG_HIGH_RES_TIMERS is not set
249CONFIG_PREEMPT=y
250CONFIG_HZ=100
251# CONFIG_AEABI is not set
252# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
253CONFIG_SELECT_MEMORY_MODEL=y
254CONFIG_FLATMEM_MANUAL=y
255# CONFIG_DISCONTIGMEM_MANUAL is not set
256# CONFIG_SPARSEMEM_MANUAL is not set
257CONFIG_FLATMEM=y
258CONFIG_FLAT_NODE_MEM_MAP=y
259# CONFIG_SPARSEMEM_STATIC is not set
260CONFIG_SPLIT_PTLOCK_CPUS=4096
261# CONFIG_RESOURCES_64BIT is not set
262CONFIG_ZONE_DMA_FLAG=1
263# CONFIG_LEDS is not set
264CONFIG_ALIGNMENT_TRAP=y
265
266#
267# Boot options
268#
269CONFIG_ZBOOT_ROM_TEXT=0x0
270CONFIG_ZBOOT_ROM_BSS=0x0
271CONFIG_CMDLINE="mem=32M console=ttyS0,115200n8 root=/dev/ram0 initrd=0x11c00000,4M"
272# CONFIG_XIP_KERNEL is not set
273# CONFIG_KEXEC is not set
274
275#
276# CPU Frequency scaling
277#
278# CONFIG_CPU_FREQ is not set
279
280#
281# Floating point emulation
282#
283
284#
285# At least one emulation must be selected
286#
287CONFIG_FPE_NWFPE=y
288# CONFIG_FPE_NWFPE_XP is not set
289# CONFIG_FPE_FASTFPE is not set
290
291#
292# Userspace binary formats
293#
294CONFIG_BINFMT_ELF=y
295# CONFIG_BINFMT_AOUT is not set
296# CONFIG_BINFMT_MISC is not set
297# CONFIG_ARTHUR is not set
298
299#
300# Power management options
301#
302# CONFIG_PM is not set
303
304#
305# Networking
306#
307CONFIG_NET=y
308
309#
310# Networking options
311#
312CONFIG_PACKET=y
313# CONFIG_PACKET_MMAP is not set
314CONFIG_UNIX=y
315CONFIG_XFRM=y
316# CONFIG_XFRM_USER is not set
317# CONFIG_XFRM_SUB_POLICY is not set
318# CONFIG_XFRM_MIGRATE is not set
319# CONFIG_NET_KEY is not set
320CONFIG_INET=y
321CONFIG_IP_MULTICAST=y
322# CONFIG_IP_ADVANCED_ROUTER is not set
323CONFIG_IP_FIB_HASH=y
324# CONFIG_IP_PNP is not set
325# CONFIG_NET_IPIP is not set
326# CONFIG_NET_IPGRE is not set
327# CONFIG_IP_MROUTE is not set
328# CONFIG_ARPD is not set
329# CONFIG_SYN_COOKIES is not set
330# CONFIG_INET_AH is not set
331# CONFIG_INET_ESP is not set
332# CONFIG_INET_IPCOMP is not set
333# CONFIG_INET_XFRM_TUNNEL is not set
334CONFIG_INET_TUNNEL=y
335CONFIG_INET_XFRM_MODE_TRANSPORT=y
336CONFIG_INET_XFRM_MODE_TUNNEL=y
337CONFIG_INET_XFRM_MODE_BEET=y
338CONFIG_INET_DIAG=y
339CONFIG_INET_TCP_DIAG=y
340# CONFIG_TCP_CONG_ADVANCED is not set
341CONFIG_TCP_CONG_CUBIC=y
342CONFIG_DEFAULT_TCP_CONG="cubic"
343# CONFIG_TCP_MD5SIG is not set
344CONFIG_IPV6=y
345# CONFIG_IPV6_PRIVACY is not set
346# CONFIG_IPV6_ROUTER_PREF is not set
347# CONFIG_IPV6_OPTIMISTIC_DAD is not set
348# CONFIG_INET6_AH is not set
349# CONFIG_INET6_ESP is not set
350# CONFIG_INET6_IPCOMP is not set
351# CONFIG_IPV6_MIP6 is not set
352# CONFIG_INET6_XFRM_TUNNEL is not set
353# CONFIG_INET6_TUNNEL is not set
354CONFIG_INET6_XFRM_MODE_TRANSPORT=y
355CONFIG_INET6_XFRM_MODE_TUNNEL=y
356CONFIG_INET6_XFRM_MODE_BEET=y
357# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
358CONFIG_IPV6_SIT=y
359# CONFIG_IPV6_TUNNEL is not set
360# CONFIG_IPV6_MULTIPLE_TABLES is not set
361# CONFIG_NETWORK_SECMARK is not set
362# CONFIG_NETFILTER is not set
363
364#
365# DCCP Configuration (EXPERIMENTAL)
366#
367# CONFIG_IP_DCCP is not set
368
369#
370# SCTP Configuration (EXPERIMENTAL)
371#
372# CONFIG_IP_SCTP is not set
373
374#
375# TIPC Configuration (EXPERIMENTAL)
376#
377# CONFIG_TIPC is not set
378# CONFIG_ATM is not set
379# CONFIG_BRIDGE is not set
380# CONFIG_VLAN_8021Q is not set
381# CONFIG_DECNET is not set
382# CONFIG_LLC2 is not set
383# CONFIG_IPX is not set
384# CONFIG_ATALK is not set
385# CONFIG_X25 is not set
386# CONFIG_LAPB is not set
387# CONFIG_ECONET is not set
388# CONFIG_WAN_ROUTER is not set
389
390#
391# QoS and/or fair queueing
392#
393# CONFIG_NET_SCHED is not set
394
395#
396# Network testing
397#
398# CONFIG_NET_PKTGEN is not set
399# CONFIG_HAMRADIO is not set
400# CONFIG_IRDA is not set
401# CONFIG_BT is not set
402# CONFIG_AF_RXRPC is not set
403
404#
405# Wireless
406#
407# CONFIG_CFG80211 is not set
408# CONFIG_WIRELESS_EXT is not set
409# CONFIG_MAC80211 is not set
410# CONFIG_IEEE80211 is not set
411# CONFIG_RFKILL is not set
412
413#
414# Device Drivers
415#
416
417#
418# Generic Driver Options
419#
420CONFIG_STANDALONE=y
421CONFIG_PREVENT_FIRMWARE_BUILD=y
422# CONFIG_FW_LOADER is not set
423# CONFIG_DEBUG_DRIVER is not set
424# CONFIG_DEBUG_DEVRES is not set
425# CONFIG_SYS_HYPERVISOR is not set
426
427#
428# Connector - unified userspace <-> kernelspace linker
429#
430# CONFIG_CONNECTOR is not set
431CONFIG_MTD=y
432# CONFIG_MTD_DEBUG is not set
433# CONFIG_MTD_CONCAT is not set
434CONFIG_MTD_PARTITIONS=y
435# CONFIG_MTD_REDBOOT_PARTS is not set
436# CONFIG_MTD_CMDLINE_PARTS is not set
437# CONFIG_MTD_AFS_PARTS is not set
438
439#
440# User Modules And Translation Layers
441#
442CONFIG_MTD_CHAR=y
443CONFIG_MTD_BLKDEVS=y
444CONFIG_MTD_BLOCK=y
445# CONFIG_FTL is not set
446# CONFIG_NFTL is not set
447# CONFIG_INFTL is not set
448# CONFIG_RFD_FTL is not set
449# CONFIG_SSFDC is not set
450
451#
452# RAM/ROM/Flash chip drivers
453#
454# CONFIG_MTD_CFI is not set
455# CONFIG_MTD_JEDECPROBE is not set
456CONFIG_MTD_MAP_BANK_WIDTH_1=y
457CONFIG_MTD_MAP_BANK_WIDTH_2=y
458CONFIG_MTD_MAP_BANK_WIDTH_4=y
459# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
460# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
461# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
462CONFIG_MTD_CFI_I1=y
463CONFIG_MTD_CFI_I2=y
464# CONFIG_MTD_CFI_I4 is not set
465# CONFIG_MTD_CFI_I8 is not set
466# CONFIG_MTD_RAM is not set
467# CONFIG_MTD_ROM is not set
468# CONFIG_MTD_ABSENT is not set
469
470#
471# Mapping drivers for chip access
472#
473# CONFIG_MTD_COMPLEX_MAPPINGS is not set
474# CONFIG_MTD_PLATRAM is not set
475
476#
477# Self-contained MTD device drivers
478#
479# CONFIG_MTD_SLRAM is not set
480# CONFIG_MTD_PHRAM is not set
481# CONFIG_MTD_MTDRAM is not set
482# CONFIG_MTD_BLOCK2MTD is not set
483
484#
485# Disk-On-Chip Device Drivers
486#
487# CONFIG_MTD_DOC2000 is not set
488# CONFIG_MTD_DOC2001 is not set
489# CONFIG_MTD_DOC2001PLUS is not set
490CONFIG_MTD_NAND=y
491# CONFIG_MTD_NAND_VERIFY_WRITE is not set
492# CONFIG_MTD_NAND_ECC_SMC is not set
493# CONFIG_MTD_NAND_MUSEUM_IDS is not set
494CONFIG_MTD_NAND_AMS_DELTA=y
495CONFIG_MTD_NAND_IDS=y
496# CONFIG_MTD_NAND_DISKONCHIP is not set
497# CONFIG_MTD_NAND_NANDSIM is not set
498# CONFIG_MTD_NAND_PLATFORM is not set
499# CONFIG_MTD_ONENAND is not set
500
501#
502# UBI - Unsorted block images
503#
504# CONFIG_MTD_UBI is not set
505
506#
507# Parallel port support
508#
509# CONFIG_PARPORT is not set
510
511#
512# Plug and Play support
513#
514# CONFIG_PNPACPI is not set
515
516#
517# Block devices
518#
519# CONFIG_BLK_DEV_COW_COMMON is not set
520CONFIG_BLK_DEV_LOOP=y
521# CONFIG_BLK_DEV_CRYPTOLOOP is not set
522# CONFIG_BLK_DEV_NBD is not set
523# CONFIG_BLK_DEV_UB is not set
524CONFIG_BLK_DEV_RAM=y
525CONFIG_BLK_DEV_RAM_COUNT=16
526CONFIG_BLK_DEV_RAM_SIZE=8192
527CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
528# CONFIG_CDROM_PKTCDVD is not set
529# CONFIG_ATA_OVER_ETH is not set
530
531#
532# SCSI device support
533#
534# CONFIG_RAID_ATTRS is not set
535CONFIG_SCSI=y
536# CONFIG_SCSI_TGT is not set
537# CONFIG_SCSI_NETLINK is not set
538CONFIG_SCSI_PROC_FS=y
539
540#
541# SCSI support type (disk, tape, CD-ROM)
542#
543CONFIG_BLK_DEV_SD=y
544# CONFIG_CHR_DEV_ST is not set
545# CONFIG_CHR_DEV_OSST is not set
546# CONFIG_BLK_DEV_SR is not set
547# CONFIG_CHR_DEV_SG is not set
548# CONFIG_CHR_DEV_SCH is not set
549
550#
551# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
552#
553# CONFIG_SCSI_MULTI_LUN is not set
554# CONFIG_SCSI_CONSTANTS is not set
555# CONFIG_SCSI_LOGGING is not set
556# CONFIG_SCSI_SCAN_ASYNC is not set
557CONFIG_SCSI_WAIT_SCAN=m
558
559#
560# SCSI Transports
561#
562# CONFIG_SCSI_SPI_ATTRS is not set
563# CONFIG_SCSI_FC_ATTRS is not set
564# CONFIG_SCSI_ISCSI_ATTRS is not set
565# CONFIG_SCSI_SAS_ATTRS is not set
566# CONFIG_SCSI_SAS_LIBSAS is not set
567
568#
569# SCSI low-level drivers
570#
571# CONFIG_ISCSI_TCP is not set
572# CONFIG_SCSI_DEBUG is not set
573# CONFIG_SCSI_ESP_CORE is not set
574# CONFIG_ATA is not set
575
576#
577# Multi-device support (RAID and LVM)
578#
579# CONFIG_MD is not set
580
581#
582# Network device support
583#
584CONFIG_NETDEVICES=y
585# CONFIG_DUMMY is not set
586# CONFIG_BONDING is not set
587# CONFIG_EQUALIZER is not set
588# CONFIG_TUN is not set
589# CONFIG_PHYLIB is not set
590
591#
592# Ethernet (10 or 100Mbit)
593#
594CONFIG_NET_ETHERNET=y
595CONFIG_MII=y
596# CONFIG_SMC91X is not set
597# CONFIG_DM9000 is not set
598CONFIG_NETDEV_1000=y
599CONFIG_NETDEV_10000=y
600
601#
602# Token Ring devices
603#
604
605#
606# Wireless LAN
607#
608# CONFIG_WLAN_PRE80211 is not set
609# CONFIG_WLAN_80211 is not set
610
611#
612# USB Network Adapters
613#
614CONFIG_USB_CATC=y
615CONFIG_USB_KAWETH=y
616CONFIG_USB_PEGASUS=y
617CONFIG_USB_RTL8150=y
618CONFIG_USB_USBNET_MII=y
619CONFIG_USB_USBNET=y
620CONFIG_USB_NET_AX8817X=y
621CONFIG_USB_NET_CDCETHER=y
622# CONFIG_USB_NET_DM9601 is not set
623# CONFIG_USB_NET_GL620A is not set
624CONFIG_USB_NET_NET1080=y
625# CONFIG_USB_NET_PLUSB is not set
626# CONFIG_USB_NET_MCS7830 is not set
627# CONFIG_USB_NET_RNDIS_HOST is not set
628CONFIG_USB_NET_CDC_SUBSET=y
629# CONFIG_USB_ALI_M5632 is not set
630# CONFIG_USB_AN2720 is not set
631CONFIG_USB_BELKIN=y
632CONFIG_USB_ARMLINUX=y
633# CONFIG_USB_EPSON2888 is not set
634# CONFIG_USB_KC2190 is not set
635CONFIG_USB_NET_ZAURUS=y
636# CONFIG_WAN is not set
637CONFIG_PPP=y
638CONFIG_PPP_MULTILINK=y
639# CONFIG_PPP_FILTER is not set
640# CONFIG_PPP_ASYNC is not set
641# CONFIG_PPP_SYNC_TTY is not set
642# CONFIG_PPP_DEFLATE is not set
643# CONFIG_PPP_BSDCOMP is not set
644# CONFIG_PPP_MPPE is not set
645# CONFIG_PPPOE is not set
646# CONFIG_SLIP is not set
647CONFIG_SLHC=y
648# CONFIG_SHAPER is not set
649# CONFIG_NETCONSOLE is not set
650# CONFIG_NETPOLL is not set
651# CONFIG_NET_POLL_CONTROLLER is not set
652
653#
654# ISDN subsystem
655#
656# CONFIG_ISDN is not set
657
658#
659# Input device support
660#
661CONFIG_INPUT=y
662# CONFIG_INPUT_FF_MEMLESS is not set
663
664#
665# Userland interfaces
666#
667CONFIG_INPUT_MOUSEDEV=y
668CONFIG_INPUT_MOUSEDEV_PSAUX=y
669CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
670CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
671# CONFIG_INPUT_JOYDEV is not set
672# CONFIG_INPUT_TSDEV is not set
673# CONFIG_INPUT_EVDEV is not set
674# CONFIG_INPUT_EVBUG is not set
675
676#
677# Input Device Drivers
678#
679CONFIG_INPUT_KEYBOARD=y
680CONFIG_KEYBOARD_ATKBD=y
681# CONFIG_KEYBOARD_SUNKBD is not set
682# CONFIG_KEYBOARD_LKKBD is not set
683# CONFIG_KEYBOARD_XTKBD is not set
684# CONFIG_KEYBOARD_NEWTON is not set
685# CONFIG_KEYBOARD_STOWAWAY is not set
686CONFIG_KEYBOARD_OMAP=y
687# CONFIG_KEYBOARD_GPIO is not set
688# CONFIG_INPUT_MOUSE is not set
689# CONFIG_INPUT_JOYSTICK is not set
690# CONFIG_INPUT_TABLET is not set
691# CONFIG_INPUT_TOUCHSCREEN is not set
692# CONFIG_INPUT_MISC is not set
693
694#
695# Hardware I/O ports
696#
697CONFIG_SERIO=y
698CONFIG_SERIO_SERPORT=y
699CONFIG_SERIO_LIBPS2=y
700# CONFIG_SERIO_RAW is not set
701# CONFIG_GAMEPORT is not set
702
703#
704# Character devices
705#
706CONFIG_VT=y
707CONFIG_VT_CONSOLE=y
708CONFIG_HW_CONSOLE=y
709# CONFIG_VT_HW_CONSOLE_BINDING is not set
710# CONFIG_SERIAL_NONSTANDARD is not set
711
712#
713# Serial drivers
714#
715CONFIG_SERIAL_8250=y
716CONFIG_SERIAL_8250_CONSOLE=y
717CONFIG_SERIAL_8250_NR_UARTS=4
718CONFIG_SERIAL_8250_RUNTIME_UARTS=4
719# CONFIG_SERIAL_8250_EXTENDED is not set
720
721#
722# Non-8250 serial port support
723#
724CONFIG_SERIAL_CORE=y
725CONFIG_SERIAL_CORE_CONSOLE=y
726CONFIG_UNIX98_PTYS=y
727# CONFIG_LEGACY_PTYS is not set
728
729#
730# IPMI
731#
732# CONFIG_IPMI_HANDLER is not set
733# CONFIG_WATCHDOG is not set
734CONFIG_HW_RANDOM=y
735# CONFIG_NVRAM is not set
736# CONFIG_R3964 is not set
737# CONFIG_RAW_DRIVER is not set
738
739#
740# TPM devices
741#
742# CONFIG_TCG_TPM is not set
743CONFIG_I2C=y
744CONFIG_I2C_BOARDINFO=y
745CONFIG_I2C_CHARDEV=y
746
747#
748# I2C Algorithms
749#
750CONFIG_I2C_ALGOBIT=y
751# CONFIG_I2C_ALGOPCF is not set
752# CONFIG_I2C_ALGOPCA is not set
753
754#
755# I2C Hardware Bus support
756#
757# CONFIG_I2C_GPIO is not set
758# CONFIG_I2C_OCORES is not set
759CONFIG_I2C_OMAP=y
760# CONFIG_I2C_PARPORT_LIGHT is not set
761# CONFIG_I2C_SIMTEC is not set
762# CONFIG_I2C_STUB is not set
763# CONFIG_I2C_TINY_USB is not set
764
765#
766# Miscellaneous I2C Chip support
767#
768# CONFIG_SENSORS_DS1337 is not set
769# CONFIG_SENSORS_DS1374 is not set
770# CONFIG_SENSORS_EEPROM is not set
771# CONFIG_SENSORS_PCF8574 is not set
772# CONFIG_SENSORS_PCA9539 is not set
773# CONFIG_SENSORS_PCF8591 is not set
774# CONFIG_TPS65010 is not set
775# CONFIG_SENSORS_TLV320AIC23 is not set
776# CONFIG_SENSORS_MAX6875 is not set
777# CONFIG_I2C_DEBUG_CORE is not set
778# CONFIG_I2C_DEBUG_ALGO is not set
779# CONFIG_I2C_DEBUG_BUS is not set
780# CONFIG_I2C_DEBUG_CHIP is not set
781
782#
783# SPI support
784#
785# CONFIG_SPI is not set
786# CONFIG_SPI_MASTER is not set
787
788#
789# Dallas's 1-wire bus
790#
791# CONFIG_W1 is not set
792# CONFIG_HWMON is not set
793
794#
795# Misc devices
796#
797# CONFIG_BLINK is not set
798
799#
800# Multifunction device drivers
801#
802# CONFIG_MFD_SM501 is not set
803
804#
805# LED devices
806#
807CONFIG_NEW_LEDS=y
808CONFIG_LEDS_CLASS=y
809
810#
811# LED drivers
812#
813CONFIG_LEDS_AMS_DELTA=y
814# CONFIG_LEDS_OMAP_DEBUG is not set
815# CONFIG_LEDS_OMAP is not set
816
817#
818# LED Triggers
819#
820CONFIG_LEDS_TRIGGERS=y
821CONFIG_LEDS_TRIGGER_TIMER=y
822CONFIG_LEDS_TRIGGER_HEARTBEAT=y
823
824#
825# Multimedia devices
826#
827# CONFIG_VIDEO_DEV is not set
828# CONFIG_DVB_CORE is not set
829CONFIG_DAB=y
830# CONFIG_USB_DABUSB is not set
831
832#
833# Graphics support
834#
835# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
836
837#
838# Display device support
839#
840# CONFIG_DISPLAY_SUPPORT is not set
841# CONFIG_VGASTATE is not set
842CONFIG_FB=y
843CONFIG_FIRMWARE_EDID=y
844# CONFIG_FB_DDC is not set
845# CONFIG_FB_CFB_FILLRECT is not set
846# CONFIG_FB_CFB_COPYAREA is not set
847# CONFIG_FB_CFB_IMAGEBLIT is not set
848# CONFIG_FB_SYS_FILLRECT is not set
849# CONFIG_FB_SYS_COPYAREA is not set
850# CONFIG_FB_SYS_IMAGEBLIT is not set
851# CONFIG_FB_SYS_FOPS is not set
852CONFIG_FB_DEFERRED_IO=y
853# CONFIG_FB_SVGALIB is not set
854# CONFIG_FB_MACMODES is not set
855# CONFIG_FB_BACKLIGHT is not set
856# CONFIG_FB_MODE_HELPERS is not set
857# CONFIG_FB_TILEBLITTING is not set
858
859#
860# Frame buffer hardware drivers
861#
862# CONFIG_FB_S1D13XXX is not set
863CONFIG_FB_OMAP=y
864# CONFIG_FB_OMAP_LCDC_EXTERNAL is not set
865# CONFIG_FB_OMAP_LCD_MIPID is not set
866# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set
867CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=2
868# CONFIG_FB_OMAP_DMA_TUNE is not set
869# CONFIG_FB_VIRTUAL is not set
870
871#
872# Console display driver support
873#
874# CONFIG_VGA_CONSOLE is not set
875CONFIG_DUMMY_CONSOLE=y
876CONFIG_FRAMEBUFFER_CONSOLE=y
877# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
878CONFIG_FONTS=y
879# CONFIG_FONT_8x8 is not set
880# CONFIG_FONT_8x16 is not set
881CONFIG_FONT_6x11=y
882# CONFIG_FONT_7x14 is not set
883# CONFIG_FONT_PEARL_8x8 is not set
884# CONFIG_FONT_ACORN_8x8 is not set
885# CONFIG_FONT_MINI_4x6 is not set
886# CONFIG_FONT_CLEAN_4x6 is not set
887# CONFIG_FONT_CLEAN_5x8 is not set
888# CONFIG_FONT_SUN8x16 is not set
889# CONFIG_FONT_SUN12x22 is not set
890# CONFIG_FONT_10x18 is not set
891CONFIG_LOGO=y
892# CONFIG_LOGO_LINUX_MONO is not set
893# CONFIG_LOGO_LINUX_VGA16 is not set
894CONFIG_LOGO_LINUX_CLUT224=y
895
896#
897# Sound
898#
899# CONFIG_SOUND is not set
900
901#
902# HID Devices
903#
904CONFIG_HID=y
905# CONFIG_HID_DEBUG is not set
906
907#
908# USB Input Devices
909#
910CONFIG_USB_HID=y
911# CONFIG_USB_HIDINPUT_POWERBOOK is not set
912# CONFIG_HID_FF is not set
913# CONFIG_USB_HIDDEV is not set
914
915#
916# USB support
917#
918CONFIG_USB_ARCH_HAS_HCD=y
919CONFIG_USB_ARCH_HAS_OHCI=y
920# CONFIG_USB_ARCH_HAS_EHCI is not set
921CONFIG_USB=y
922# CONFIG_USB_DEBUG is not set
923
924#
925# Miscellaneous USB options
926#
927CONFIG_USB_DEVICEFS=y
928# CONFIG_USB_DEVICE_CLASS is not set
929# CONFIG_USB_DYNAMIC_MINORS is not set
930# CONFIG_USB_OTG is not set
931
932#
933# USB Host Controller Drivers
934#
935# CONFIG_USB_ISP116X_HCD is not set
936CONFIG_USB_OHCI_HCD=y
937# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
938# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
939CONFIG_USB_OHCI_LITTLE_ENDIAN=y
940# CONFIG_USB_SL811_HCD is not set
941# CONFIG_USB_MUSB_HDRC is not set
942
943#
944# USB Device Class drivers
945#
946# CONFIG_USB_ACM is not set
947# CONFIG_USB_PRINTER is not set
948
949#
950# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
951#
952
953#
954# may also be needed; see USB_STORAGE Help for more information
955#
956CONFIG_USB_STORAGE=y
957# CONFIG_USB_STORAGE_DEBUG is not set
958# CONFIG_USB_STORAGE_DATAFAB is not set
959# CONFIG_USB_STORAGE_FREECOM is not set
960# CONFIG_USB_STORAGE_DPCM is not set
961# CONFIG_USB_STORAGE_USBAT is not set
962# CONFIG_USB_STORAGE_SDDR09 is not set
963# CONFIG_USB_STORAGE_SDDR55 is not set
964# CONFIG_USB_STORAGE_JUMPSHOT is not set
965# CONFIG_USB_STORAGE_ALAUDA is not set
966# CONFIG_USB_STORAGE_KARMA is not set
967# CONFIG_USB_LIBUSUAL is not set
968
969#
970# USB Imaging devices
971#
972# CONFIG_USB_MDC800 is not set
973# CONFIG_USB_MICROTEK is not set
974CONFIG_USB_MON=y
975
976#
977# USB port drivers
978#
979
980#
981# USB Serial Converter support
982#
983# CONFIG_USB_SERIAL is not set
984
985#
986# USB Miscellaneous drivers
987#
988# CONFIG_USB_EMI62 is not set
989# CONFIG_USB_EMI26 is not set
990# CONFIG_USB_ADUTUX is not set
991# CONFIG_USB_AUERSWALD is not set
992# CONFIG_USB_RIO500 is not set
993# CONFIG_USB_LEGOTOWER is not set
994# CONFIG_USB_LCD is not set
995# CONFIG_USB_BERRY_CHARGE is not set
996# CONFIG_USB_LED is not set
997# CONFIG_USB_CYPRESS_CY7C63 is not set
998# CONFIG_USB_CYTHERM is not set
999# CONFIG_USB_PHIDGET is not set
1000# CONFIG_USB_IDMOUSE is not set
1001# CONFIG_USB_FTDI_ELAN is not set
1002# CONFIG_USB_APPLEDISPLAY is not set
1003# CONFIG_USB_LD is not set
1004# CONFIG_USB_TRANCEVIBRATOR is not set
1005# CONFIG_USB_IOWARRIOR is not set
1006# CONFIG_USB_TEST is not set
1007
1008#
1009# USB DSL modem support
1010#
1011
1012#
1013# USB Gadget Support
1014#
1015# CONFIG_USB_GADGET is not set
1016# CONFIG_MMC is not set
1017
1018#
1019# Real Time Clock
1020#
1021CONFIG_RTC_LIB=y
1022CONFIG_RTC_CLASS=y
1023CONFIG_RTC_HCTOSYS=y
1024CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
1025# CONFIG_RTC_DEBUG is not set
1026
1027#
1028# RTC interfaces
1029#
1030CONFIG_RTC_INTF_SYSFS=y
1031CONFIG_RTC_INTF_PROC=y
1032CONFIG_RTC_INTF_DEV=y
1033# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
1034# CONFIG_RTC_DRV_TEST is not set
1035
1036#
1037# I2C RTC drivers
1038#
1039# CONFIG_RTC_DRV_DS1307 is not set
1040# CONFIG_RTC_DRV_DS1672 is not set
1041# CONFIG_RTC_DRV_MAX6900 is not set
1042# CONFIG_RTC_DRV_RS5C372 is not set
1043# CONFIG_RTC_DRV_ISL1208 is not set
1044# CONFIG_RTC_DRV_X1205 is not set
1045# CONFIG_RTC_DRV_PCF8563 is not set
1046# CONFIG_RTC_DRV_PCF8583 is not set
1047
1048#
1049# SPI RTC drivers
1050#
1051
1052#
1053# Platform RTC drivers
1054#
1055# CONFIG_RTC_DRV_CMOS is not set
1056# CONFIG_RTC_DRV_DS1553 is not set
1057# CONFIG_RTC_DRV_DS1742 is not set
1058# CONFIG_RTC_DRV_M48T86 is not set
1059# CONFIG_RTC_DRV_V3020 is not set
1060
1061#
1062# on-CPU RTC drivers
1063#
1064CONFIG_RTC_DRV_OMAP=y
1065
1066#
1067# CBUS support
1068#
1069# CONFIG_CBUS is not set
1070
1071#
1072# File systems
1073#
1074CONFIG_EXT2_FS=y
1075# CONFIG_EXT2_FS_XATTR is not set
1076# CONFIG_EXT2_FS_XIP is not set
1077CONFIG_EXT3_FS=y
1078CONFIG_EXT3_FS_XATTR=y
1079# CONFIG_EXT3_FS_POSIX_ACL is not set
1080# CONFIG_EXT3_FS_SECURITY is not set
1081# CONFIG_EXT4DEV_FS is not set
1082CONFIG_JBD=y
1083# CONFIG_JBD_DEBUG is not set
1084CONFIG_FS_MBCACHE=y
1085# CONFIG_REISERFS_FS is not set
1086# CONFIG_JFS_FS is not set
1087# CONFIG_FS_POSIX_ACL is not set
1088# CONFIG_XFS_FS is not set
1089# CONFIG_GFS2_FS is not set
1090# CONFIG_OCFS2_FS is not set
1091# CONFIG_MINIX_FS is not set
1092# CONFIG_ROMFS_FS is not set
1093CONFIG_INOTIFY=y
1094CONFIG_INOTIFY_USER=y
1095# CONFIG_QUOTA is not set
1096CONFIG_DNOTIFY=y
1097CONFIG_AUTOFS_FS=y
1098CONFIG_AUTOFS4_FS=y
1099# CONFIG_FUSE_FS is not set
1100
1101#
1102# CD-ROM/DVD Filesystems
1103#
1104# CONFIG_ISO9660_FS is not set
1105# CONFIG_UDF_FS is not set
1106
1107#
1108# DOS/FAT/NT Filesystems
1109#
1110CONFIG_FAT_FS=y
1111CONFIG_MSDOS_FS=y
1112CONFIG_VFAT_FS=y
1113CONFIG_FAT_DEFAULT_CODEPAGE=437
1114CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
1115# CONFIG_NTFS_FS is not set
1116
1117#
1118# Pseudo filesystems
1119#
1120CONFIG_PROC_FS=y
1121CONFIG_PROC_SYSCTL=y
1122CONFIG_SYSFS=y
1123CONFIG_TMPFS=y
1124# CONFIG_TMPFS_POSIX_ACL is not set
1125# CONFIG_HUGETLB_PAGE is not set
1126CONFIG_RAMFS=y
1127# CONFIG_CONFIGFS_FS is not set
1128
1129#
1130# Miscellaneous filesystems
1131#
1132# CONFIG_ADFS_FS is not set
1133# CONFIG_AFFS_FS is not set
1134# CONFIG_HFS_FS is not set
1135# CONFIG_HFSPLUS_FS is not set
1136# CONFIG_BEFS_FS is not set
1137# CONFIG_BFS_FS is not set
1138# CONFIG_EFS_FS is not set
1139CONFIG_JFFS2_FS=y
1140CONFIG_JFFS2_FS_DEBUG=0
1141CONFIG_JFFS2_FS_WRITEBUFFER=y
1142CONFIG_JFFS2_SUMMARY=y
1143# CONFIG_JFFS2_FS_XATTR is not set
1144# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
1145CONFIG_JFFS2_ZLIB=y
1146CONFIG_JFFS2_RTIME=y
1147# CONFIG_JFFS2_RUBIN is not set
1148# CONFIG_CRAMFS is not set
1149# CONFIG_VXFS_FS is not set
1150# CONFIG_HPFS_FS is not set
1151# CONFIG_QNX4FS_FS is not set
1152# CONFIG_SYSV_FS is not set
1153# CONFIG_UFS_FS is not set
1154
1155#
1156# Network File Systems
1157#
1158CONFIG_NFS_FS=y
1159# CONFIG_NFS_V3 is not set
1160# CONFIG_NFS_V4 is not set
1161# CONFIG_NFS_DIRECTIO is not set
1162# CONFIG_NFSD is not set
1163CONFIG_LOCKD=y
1164CONFIG_NFS_COMMON=y
1165CONFIG_SUNRPC=y
1166# CONFIG_SUNRPC_BIND34 is not set
1167# CONFIG_RPCSEC_GSS_KRB5 is not set
1168# CONFIG_RPCSEC_GSS_SPKM3 is not set
1169# CONFIG_SMB_FS is not set
1170# CONFIG_CIFS is not set
1171# CONFIG_NCP_FS is not set
1172# CONFIG_CODA_FS is not set
1173# CONFIG_AFS_FS is not set
1174# CONFIG_9P_FS is not set
1175
1176#
1177# Partition Types
1178#
1179CONFIG_PARTITION_ADVANCED=y
1180# CONFIG_ACORN_PARTITION is not set
1181# CONFIG_OSF_PARTITION is not set
1182# CONFIG_AMIGA_PARTITION is not set
1183# CONFIG_ATARI_PARTITION is not set
1184# CONFIG_MAC_PARTITION is not set
1185CONFIG_MSDOS_PARTITION=y
1186# CONFIG_BSD_DISKLABEL is not set
1187# CONFIG_MINIX_SUBPARTITION is not set
1188# CONFIG_SOLARIS_X86_PARTITION is not set
1189# CONFIG_UNIXWARE_DISKLABEL is not set
1190# CONFIG_LDM_PARTITION is not set
1191# CONFIG_SGI_PARTITION is not set
1192# CONFIG_ULTRIX_PARTITION is not set
1193# CONFIG_SUN_PARTITION is not set
1194# CONFIG_KARMA_PARTITION is not set
1195# CONFIG_EFI_PARTITION is not set
1196# CONFIG_SYSV68_PARTITION is not set
1197
1198#
1199# Native Language Support
1200#
1201CONFIG_NLS=y
1202CONFIG_NLS_DEFAULT="iso8859-1"
1203CONFIG_NLS_CODEPAGE_437=y
1204# CONFIG_NLS_CODEPAGE_737 is not set
1205# CONFIG_NLS_CODEPAGE_775 is not set
1206CONFIG_NLS_CODEPAGE_850=y
1207CONFIG_NLS_CODEPAGE_852=y
1208# CONFIG_NLS_CODEPAGE_855 is not set
1209# CONFIG_NLS_CODEPAGE_857 is not set
1210# CONFIG_NLS_CODEPAGE_860 is not set
1211# CONFIG_NLS_CODEPAGE_861 is not set
1212# CONFIG_NLS_CODEPAGE_862 is not set
1213# CONFIG_NLS_CODEPAGE_863 is not set
1214# CONFIG_NLS_CODEPAGE_864 is not set
1215# CONFIG_NLS_CODEPAGE_865 is not set
1216# CONFIG_NLS_CODEPAGE_866 is not set
1217# CONFIG_NLS_CODEPAGE_869 is not set
1218# CONFIG_NLS_CODEPAGE_936 is not set
1219# CONFIG_NLS_CODEPAGE_950 is not set
1220# CONFIG_NLS_CODEPAGE_932 is not set
1221# CONFIG_NLS_CODEPAGE_949 is not set
1222# CONFIG_NLS_CODEPAGE_874 is not set
1223# CONFIG_NLS_ISO8859_8 is not set
1224# CONFIG_NLS_CODEPAGE_1250 is not set
1225# CONFIG_NLS_CODEPAGE_1251 is not set
1226# CONFIG_NLS_ASCII is not set
1227CONFIG_NLS_ISO8859_1=y
1228CONFIG_NLS_ISO8859_2=y
1229# CONFIG_NLS_ISO8859_3 is not set
1230# CONFIG_NLS_ISO8859_4 is not set
1231# CONFIG_NLS_ISO8859_5 is not set
1232# CONFIG_NLS_ISO8859_6 is not set
1233# CONFIG_NLS_ISO8859_7 is not set
1234# CONFIG_NLS_ISO8859_9 is not set
1235# CONFIG_NLS_ISO8859_13 is not set
1236# CONFIG_NLS_ISO8859_14 is not set
1237# CONFIG_NLS_ISO8859_15 is not set
1238# CONFIG_NLS_KOI8_R is not set
1239# CONFIG_NLS_KOI8_U is not set
1240# CONFIG_NLS_UTF8 is not set
1241
1242#
1243# Distributed Lock Manager
1244#
1245# CONFIG_DLM is not set
1246
1247#
1248# Profiling support
1249#
1250# CONFIG_PROFILING is not set
1251
1252#
1253# Kernel hacking
1254#
1255# CONFIG_PRINTK_TIME is not set
1256CONFIG_ENABLE_MUST_CHECK=y
1257CONFIG_MAGIC_SYSRQ=y
1258# CONFIG_UNUSED_SYMBOLS is not set
1259# CONFIG_DEBUG_FS is not set
1260# CONFIG_HEADERS_CHECK is not set
1261CONFIG_DEBUG_KERNEL=y
1262# CONFIG_DEBUG_SHIRQ is not set
1263CONFIG_DETECT_SOFTLOCKUP=y
1264# CONFIG_SCHEDSTATS is not set
1265# CONFIG_TIMER_STATS is not set
1266# CONFIG_DEBUG_SLAB is not set
1267CONFIG_DEBUG_PREEMPT=y
1268# CONFIG_DEBUG_RT_MUTEXES is not set
1269# CONFIG_RT_MUTEX_TESTER is not set
1270# CONFIG_DEBUG_SPINLOCK is not set
1271# CONFIG_DEBUG_MUTEXES is not set
1272# CONFIG_DEBUG_LOCK_ALLOC is not set
1273# CONFIG_PROVE_LOCKING is not set
1274# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1275# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1276# CONFIG_DEBUG_KOBJECT is not set
1277CONFIG_DEBUG_BUGVERBOSE=y
1278# CONFIG_DEBUG_INFO is not set
1279# CONFIG_DEBUG_VM is not set
1280# CONFIG_DEBUG_LIST is not set
1281CONFIG_FRAME_POINTER=y
1282CONFIG_FORCED_INLINING=y
1283# CONFIG_RCU_TORTURE_TEST is not set
1284# CONFIG_FAULT_INJECTION is not set
1285# CONFIG_DEBUG_USER is not set
1286# CONFIG_DEBUG_ERRORS is not set
1287# CONFIG_DEBUG_LL is not set
1288
1289#
1290# Security options
1291#
1292# CONFIG_KEYS is not set
1293# CONFIG_SECURITY is not set
1294
1295#
1296# Cryptographic options
1297#
1298# CONFIG_CRYPTO is not set
1299
1300#
1301# Library routines
1302#
1303CONFIG_BITREVERSE=y
1304# CONFIG_CRC_CCITT is not set
1305# CONFIG_CRC16 is not set
1306# CONFIG_CRC_ITU_T is not set
1307CONFIG_CRC32=y
1308# CONFIG_LIBCRC32C is not set
1309CONFIG_ZLIB_INFLATE=y
1310CONFIG_ZLIB_DEFLATE=y
1311CONFIG_PLIST=y
1312CONFIG_HAS_IOMEM=y
1313CONFIG_HAS_IOPORT=y
1314CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/n770_defconfig b/arch/arm/configs/n770_defconfig
new file mode 100644
index 000000000000..568ef1770d5f
--- /dev/null
+++ b/arch/arm/configs/n770_defconfig
@@ -0,0 +1,1421 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.24-rc8-omap1
4# Fri Jan 18 10:21:06 2008
5#
6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8CONFIG_GENERIC_GPIO=y
9CONFIG_GENERIC_TIME=y
10CONFIG_GENERIC_CLOCKEVENTS=y
11CONFIG_MMU=y
12# CONFIG_NO_IOPORT is not set
13CONFIG_GENERIC_HARDIRQS=y
14CONFIG_STACKTRACE_SUPPORT=y
15CONFIG_LOCKDEP_SUPPORT=y
16CONFIG_TRACE_IRQFLAGS_SUPPORT=y
17CONFIG_HARDIRQS_SW_RESEND=y
18CONFIG_GENERIC_IRQ_PROBE=y
19CONFIG_RWSEM_GENERIC_SPINLOCK=y
20# CONFIG_ARCH_HAS_ILOG2_U32 is not set
21# CONFIG_ARCH_HAS_ILOG2_U64 is not set
22CONFIG_GENERIC_HWEIGHT=y
23CONFIG_GENERIC_CALIBRATE_DELAY=y
24CONFIG_ZONE_DMA=y
25CONFIG_VECTORS_BASE=0xffff0000
26CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
27
28#
29# General setup
30#
31CONFIG_EXPERIMENTAL=y
32CONFIG_BROKEN_ON_SMP=y
33CONFIG_INIT_ENV_ARG_LIMIT=32
34CONFIG_LOCALVERSION=""
35CONFIG_LOCALVERSION_AUTO=y
36CONFIG_SWAP=y
37CONFIG_SYSVIPC=y
38CONFIG_SYSVIPC_SYSCTL=y
39CONFIG_POSIX_MQUEUE=y
40# CONFIG_BSD_PROCESS_ACCT is not set
41# CONFIG_TASKSTATS is not set
42# CONFIG_USER_NS is not set
43# CONFIG_PID_NS is not set
44# CONFIG_AUDIT is not set
45# CONFIG_IKCONFIG is not set
46CONFIG_LOG_BUF_SHIFT=14
47# CONFIG_CGROUPS is not set
48CONFIG_FAIR_GROUP_SCHED=y
49CONFIG_FAIR_USER_SCHED=y
50# CONFIG_FAIR_CGROUP_SCHED is not set
51CONFIG_SYSFS_DEPRECATED=y
52# CONFIG_RELAY is not set
53# CONFIG_BLK_DEV_INITRD is not set
54CONFIG_CC_OPTIMIZE_FOR_SIZE=y
55CONFIG_SYSCTL=y
56# CONFIG_EMBEDDED is not set
57CONFIG_UID16=y
58CONFIG_SYSCTL_SYSCALL=y
59CONFIG_KALLSYMS=y
60# CONFIG_KALLSYMS_ALL is not set
61# CONFIG_KALLSYMS_EXTRA_PASS is not set
62CONFIG_HOTPLUG=y
63CONFIG_PRINTK=y
64CONFIG_BUG=y
65CONFIG_ELF_CORE=y
66CONFIG_BASE_FULL=y
67CONFIG_FUTEX=y
68CONFIG_ANON_INODES=y
69CONFIG_EPOLL=y
70CONFIG_SIGNALFD=y
71CONFIG_EVENTFD=y
72CONFIG_SHMEM=y
73CONFIG_VM_EVENT_COUNTERS=y
74CONFIG_SLAB=y
75# CONFIG_SLUB is not set
76# CONFIG_SLOB is not set
77CONFIG_SLABINFO=y
78CONFIG_RT_MUTEXES=y
79# CONFIG_TINY_SHMEM is not set
80CONFIG_BASE_SMALL=0
81CONFIG_MODULES=y
82CONFIG_MODULE_UNLOAD=y
83# CONFIG_MODULE_FORCE_UNLOAD is not set
84# CONFIG_MODVERSIONS is not set
85# CONFIG_MODULE_SRCVERSION_ALL is not set
86# CONFIG_KMOD is not set
87CONFIG_BLOCK=y
88# CONFIG_LBD is not set
89# CONFIG_BLK_DEV_IO_TRACE is not set
90# CONFIG_LSF is not set
91# CONFIG_BLK_DEV_BSG is not set
92
93#
94# IO Schedulers
95#
96CONFIG_IOSCHED_NOOP=y
97# CONFIG_IOSCHED_AS is not set
98# CONFIG_IOSCHED_DEADLINE is not set
99CONFIG_IOSCHED_CFQ=y
100# CONFIG_DEFAULT_AS is not set
101# CONFIG_DEFAULT_DEADLINE is not set
102CONFIG_DEFAULT_CFQ=y
103# CONFIG_DEFAULT_NOOP is not set
104CONFIG_DEFAULT_IOSCHED="cfq"
105
106#
107# System Type
108#
109# CONFIG_ARCH_AAEC2000 is not set
110# CONFIG_ARCH_INTEGRATOR is not set
111# CONFIG_ARCH_REALVIEW is not set
112# CONFIG_ARCH_VERSATILE is not set
113# CONFIG_ARCH_AT91 is not set
114# CONFIG_ARCH_CLPS7500 is not set
115# CONFIG_ARCH_CLPS711X is not set
116# CONFIG_ARCH_CO285 is not set
117# CONFIG_ARCH_EBSA110 is not set
118# CONFIG_ARCH_EP93XX is not set
119# CONFIG_ARCH_FOOTBRIDGE is not set
120# CONFIG_ARCH_NETX is not set
121# CONFIG_ARCH_H720X is not set
122# CONFIG_ARCH_IMX is not set
123# CONFIG_ARCH_IOP13XX is not set
124# CONFIG_ARCH_IOP32X is not set
125# CONFIG_ARCH_IOP33X is not set
126# CONFIG_ARCH_IXP23XX is not set
127# CONFIG_ARCH_IXP2000 is not set
128# CONFIG_ARCH_IXP4XX is not set
129# CONFIG_ARCH_L7200 is not set
130# CONFIG_ARCH_KS8695 is not set
131# CONFIG_ARCH_NS9XXX is not set
132# CONFIG_ARCH_MXC is not set
133# CONFIG_ARCH_PNX4008 is not set
134# CONFIG_ARCH_PXA is not set
135# CONFIG_ARCH_RPC is not set
136# CONFIG_ARCH_SA1100 is not set
137# CONFIG_ARCH_S3C2410 is not set
138# CONFIG_ARCH_SHARK is not set
139# CONFIG_ARCH_LH7A40X is not set
140# CONFIG_ARCH_DAVINCI is not set
141CONFIG_ARCH_OMAP=y
142
143#
144# TI OMAP Implementations
145#
146CONFIG_ARCH_OMAP_OTG=y
147CONFIG_ARCH_OMAP1=y
148# CONFIG_ARCH_OMAP2 is not set
149# CONFIG_ARCH_OMAP3 is not set
150
151#
152# OMAP Feature Selections
153#
154CONFIG_OMAP_DEBUG_SRAM_PATCH=y
155CONFIG_OMAP_RESET_CLOCKS=y
156CONFIG_OMAP_BOOT_TAG=y
157CONFIG_OMAP_BOOT_REASON=y
158CONFIG_OMAP_COMPONENT_VERSION=y
159CONFIG_OMAP_GPIO_SWITCH=y
160# CONFIG_OMAP_MUX is not set
161CONFIG_OMAP_STI=y
162CONFIG_OMAP_STI_CONSOLE=y
163CONFIG_OMAP_MCBSP=y
164CONFIG_OMAP_MMU_FWK=y
165CONFIG_OMAP_MBOX_FWK=y
166# CONFIG_OMAP_MPU_TIMER is not set
167CONFIG_OMAP_32K_TIMER=y
168CONFIG_OMAP_32K_TIMER_HZ=128
169CONFIG_OMAP_DM_TIMER=y
170CONFIG_OMAP_LL_DEBUG_UART1=y
171# CONFIG_OMAP_LL_DEBUG_UART2 is not set
172# CONFIG_OMAP_LL_DEBUG_UART3 is not set
173
174#
175# OMAP Core Type
176#
177# CONFIG_ARCH_OMAP730 is not set
178# CONFIG_ARCH_OMAP15XX is not set
179CONFIG_ARCH_OMAP16XX=y
180
181#
182# OMAP Board Type
183#
184# CONFIG_MACH_OMAP_INNOVATOR is not set
185# CONFIG_MACH_OMAP_H2 is not set
186# CONFIG_MACH_OMAP_H3 is not set
187# CONFIG_MACH_OMAP_OSK is not set
188CONFIG_MACH_NOKIA770=y
189# CONFIG_MACH_OMAP_GENERIC is not set
190
191#
192# OMAP CPU Speed
193#
194CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER=y
195CONFIG_OMAP_ARM_216MHZ=y
196# CONFIG_OMAP_ARM_192MHZ is not set
197# CONFIG_OMAP_ARM_168MHZ is not set
198# CONFIG_OMAP_ARM_120MHZ is not set
199# CONFIG_OMAP_ARM_60MHZ is not set
200# CONFIG_OMAP_ARM_30MHZ is not set
201
202#
203# Boot options
204#
205
206#
207# Power management
208#
209
210#
211# Processor Type
212#
213CONFIG_CPU_32=y
214CONFIG_CPU_ARM926T=y
215CONFIG_CPU_32v5=y
216CONFIG_CPU_ABRT_EV5TJ=y
217CONFIG_CPU_PABRT_NOIFAR=y
218CONFIG_CPU_CACHE_VIVT=y
219CONFIG_CPU_COPY_V4WB=y
220CONFIG_CPU_TLB_V4WBI=y
221CONFIG_CPU_CP15=y
222CONFIG_CPU_CP15_MMU=y
223
224#
225# Processor Features
226#
227CONFIG_ARM_THUMB=y
228# CONFIG_CPU_ICACHE_DISABLE is not set
229# CONFIG_CPU_DCACHE_DISABLE is not set
230# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
231# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
232# CONFIG_OUTER_CACHE is not set
233
234#
235# Bus support
236#
237# CONFIG_PCI_SYSCALL is not set
238# CONFIG_ARCH_SUPPORTS_MSI is not set
239# CONFIG_PCCARD is not set
240
241#
242# Kernel Features
243#
244# CONFIG_TICK_ONESHOT is not set
245# CONFIG_NO_HZ is not set
246# CONFIG_HIGH_RES_TIMERS is not set
247CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
248# CONFIG_PREEMPT is not set
249CONFIG_HZ=128
250# CONFIG_AEABI is not set
251# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
252CONFIG_SELECT_MEMORY_MODEL=y
253CONFIG_FLATMEM_MANUAL=y
254# CONFIG_DISCONTIGMEM_MANUAL is not set
255# CONFIG_SPARSEMEM_MANUAL is not set
256CONFIG_FLATMEM=y
257CONFIG_FLAT_NODE_MEM_MAP=y
258# CONFIG_SPARSEMEM_STATIC is not set
259# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
260CONFIG_SPLIT_PTLOCK_CPUS=4096
261# CONFIG_RESOURCES_64BIT is not set
262CONFIG_ZONE_DMA_FLAG=1
263CONFIG_BOUNCE=y
264CONFIG_VIRT_TO_BUS=y
265# CONFIG_LEDS is not set
266CONFIG_ALIGNMENT_TRAP=y
267
268#
269# Boot options
270#
271CONFIG_ZBOOT_ROM_TEXT=0x0
272CONFIG_ZBOOT_ROM_BSS=0x0
273CONFIG_CMDLINE="root=1f03 rootfstype=jffs2 time"
274# CONFIG_XIP_KERNEL is not set
275# CONFIG_KEXEC is not set
276
277#
278# CPU Frequency scaling
279#
280# CONFIG_CPU_FREQ is not set
281
282#
283# Floating point emulation
284#
285
286#
287# At least one emulation must be selected
288#
289CONFIG_FPE_NWFPE=y
290# CONFIG_FPE_NWFPE_XP is not set
291# CONFIG_FPE_FASTFPE is not set
292# CONFIG_VFP is not set
293
294#
295# Userspace binary formats
296#
297CONFIG_BINFMT_ELF=y
298# CONFIG_BINFMT_AOUT is not set
299# CONFIG_BINFMT_MISC is not set
300# CONFIG_ARTHUR is not set
301
302#
303# Power management options
304#
305CONFIG_PM=y
306# CONFIG_PM_LEGACY is not set
307# CONFIG_PM_DEBUG is not set
308CONFIG_PM_SLEEP=y
309CONFIG_SUSPEND_UP_POSSIBLE=y
310CONFIG_SUSPEND=y
311# CONFIG_APM_EMULATION is not set
312
313#
314# Networking
315#
316CONFIG_NET=y
317
318#
319# Networking options
320#
321CONFIG_PACKET=y
322# CONFIG_PACKET_MMAP is not set
323CONFIG_UNIX=y
324CONFIG_XFRM=y
325# CONFIG_XFRM_USER is not set
326# CONFIG_XFRM_SUB_POLICY is not set
327# CONFIG_XFRM_MIGRATE is not set
328# CONFIG_NET_KEY is not set
329CONFIG_INET=y
330CONFIG_IP_MULTICAST=y
331# CONFIG_IP_ADVANCED_ROUTER is not set
332CONFIG_IP_FIB_HASH=y
333CONFIG_IP_PNP=y
334CONFIG_IP_PNP_DHCP=y
335CONFIG_IP_PNP_BOOTP=y
336# CONFIG_IP_PNP_RARP is not set
337# CONFIG_NET_IPIP is not set
338# CONFIG_NET_IPGRE is not set
339# CONFIG_IP_MROUTE is not set
340# CONFIG_ARPD is not set
341# CONFIG_SYN_COOKIES is not set
342# CONFIG_INET_AH is not set
343# CONFIG_INET_ESP is not set
344# CONFIG_INET_IPCOMP is not set
345# CONFIG_INET_XFRM_TUNNEL is not set
346# CONFIG_INET_TUNNEL is not set
347CONFIG_INET_XFRM_MODE_TRANSPORT=y
348CONFIG_INET_XFRM_MODE_TUNNEL=y
349CONFIG_INET_XFRM_MODE_BEET=y
350# CONFIG_INET_LRO is not set
351# CONFIG_INET_DIAG is not set
352# CONFIG_TCP_CONG_ADVANCED is not set
353CONFIG_TCP_CONG_CUBIC=y
354CONFIG_DEFAULT_TCP_CONG="cubic"
355# CONFIG_TCP_MD5SIG is not set
356# CONFIG_IP_VS is not set
357# CONFIG_IPV6 is not set
358# CONFIG_INET6_XFRM_TUNNEL is not set
359# CONFIG_INET6_TUNNEL is not set
360# CONFIG_NETLABEL is not set
361# CONFIG_NETWORK_SECMARK is not set
362CONFIG_NETFILTER=y
363# CONFIG_NETFILTER_DEBUG is not set
364
365#
366# Core Netfilter Configuration
367#
368CONFIG_NETFILTER_NETLINK=y
369# CONFIG_NETFILTER_NETLINK_QUEUE is not set
370# CONFIG_NETFILTER_NETLINK_LOG is not set
371# CONFIG_NF_CONNTRACK_ENABLED is not set
372# CONFIG_NF_CONNTRACK is not set
373# CONFIG_NETFILTER_XTABLES is not set
374
375#
376# IP: Netfilter Configuration
377#
378# CONFIG_IP_NF_QUEUE is not set
379# CONFIG_IP_NF_IPTABLES is not set
380# CONFIG_IP_NF_ARPTABLES is not set
381# CONFIG_IP_DCCP is not set
382# CONFIG_IP_SCTP is not set
383# CONFIG_TIPC is not set
384# CONFIG_ATM is not set
385# CONFIG_BRIDGE is not set
386# CONFIG_VLAN_8021Q is not set
387# CONFIG_DECNET is not set
388# CONFIG_LLC2 is not set
389# CONFIG_IPX is not set
390# CONFIG_ATALK is not set
391# CONFIG_X25 is not set
392# CONFIG_LAPB is not set
393# CONFIG_ECONET is not set
394# CONFIG_WAN_ROUTER is not set
395# CONFIG_NET_SCHED is not set
396
397#
398# Network testing
399#
400# CONFIG_NET_PKTGEN is not set
401# CONFIG_HAMRADIO is not set
402# CONFIG_IRDA is not set
403CONFIG_BT=y
404CONFIG_BT_L2CAP=y
405CONFIG_BT_SCO=y
406CONFIG_BT_RFCOMM=y
407CONFIG_BT_RFCOMM_TTY=y
408CONFIG_BT_BNEP=y
409# CONFIG_BT_BNEP_MC_FILTER is not set
410# CONFIG_BT_BNEP_PROTO_FILTER is not set
411CONFIG_BT_HIDP=y
412
413#
414# Bluetooth device drivers
415#
416# CONFIG_BT_HCIUSB is not set
417# CONFIG_BT_HCIBTUSB is not set
418# CONFIG_BT_HCIBTSDIO is not set
419# CONFIG_BT_HCIUART is not set
420# CONFIG_BT_HCIBCM203X is not set
421# CONFIG_BT_HCIBPA10X is not set
422# CONFIG_BT_HCIBFUSB is not set
423CONFIG_BT_HCIBRF6150=y
424# CONFIG_BT_HCIH4P is not set
425# CONFIG_BT_HCIVHCI is not set
426# CONFIG_AF_RXRPC is not set
427
428#
429# Wireless
430#
431# CONFIG_CFG80211 is not set
432# CONFIG_WIRELESS_EXT is not set
433# CONFIG_MAC80211 is not set
434# CONFIG_IEEE80211 is not set
435# CONFIG_RFKILL is not set
436# CONFIG_NET_9P is not set
437
438#
439# Device Drivers
440#
441
442#
443# Generic Driver Options
444#
445CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
446CONFIG_STANDALONE=y
447CONFIG_PREVENT_FIRMWARE_BUILD=y
448CONFIG_FW_LOADER=y
449# CONFIG_DEBUG_DRIVER is not set
450# CONFIG_DEBUG_DEVRES is not set
451# CONFIG_SYS_HYPERVISOR is not set
452CONFIG_CONNECTOR=y
453# CONFIG_PROC_EVENTS is not set
454CONFIG_MTD=y
455# CONFIG_MTD_DEBUG is not set
456# CONFIG_MTD_CONCAT is not set
457CONFIG_MTD_PARTITIONS=y
458# CONFIG_MTD_REDBOOT_PARTS is not set
459CONFIG_MTD_CMDLINE_PARTS=y
460# CONFIG_MTD_AFS_PARTS is not set
461
462#
463# User Modules And Translation Layers
464#
465CONFIG_MTD_CHAR=y
466CONFIG_MTD_BLKDEVS=y
467CONFIG_MTD_BLOCK=y
468# CONFIG_FTL is not set
469# CONFIG_NFTL is not set
470# CONFIG_INFTL is not set
471# CONFIG_RFD_FTL is not set
472# CONFIG_SSFDC is not set
473# CONFIG_MTD_OOPS is not set
474
475#
476# RAM/ROM/Flash chip drivers
477#
478# CONFIG_MTD_CFI is not set
479# CONFIG_MTD_JEDECPROBE is not set
480CONFIG_MTD_MAP_BANK_WIDTH_1=y
481CONFIG_MTD_MAP_BANK_WIDTH_2=y
482CONFIG_MTD_MAP_BANK_WIDTH_4=y
483# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
484# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
485# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
486CONFIG_MTD_CFI_I1=y
487CONFIG_MTD_CFI_I2=y
488# CONFIG_MTD_CFI_I4 is not set
489# CONFIG_MTD_CFI_I8 is not set
490# CONFIG_MTD_RAM is not set
491# CONFIG_MTD_ROM is not set
492# CONFIG_MTD_ABSENT is not set
493
494#
495# Mapping drivers for chip access
496#
497# CONFIG_MTD_COMPLEX_MAPPINGS is not set
498# CONFIG_MTD_PLATRAM is not set
499
500#
501# Self-contained MTD device drivers
502#
503# CONFIG_MTD_DATAFLASH is not set
504# CONFIG_MTD_M25P80 is not set
505# CONFIG_MTD_SLRAM is not set
506# CONFIG_MTD_PHRAM is not set
507# CONFIG_MTD_MTDRAM is not set
508# CONFIG_MTD_BLOCK2MTD is not set
509
510#
511# Disk-On-Chip Device Drivers
512#
513# CONFIG_MTD_DOC2000 is not set
514# CONFIG_MTD_DOC2001 is not set
515# CONFIG_MTD_DOC2001PLUS is not set
516CONFIG_MTD_NAND=y
517# CONFIG_MTD_NAND_VERIFY_WRITE is not set
518# CONFIG_MTD_NAND_ECC_SMC is not set
519# CONFIG_MTD_NAND_MUSEUM_IDS is not set
520CONFIG_MTD_NAND_OMAP_HW=y
521CONFIG_MTD_NAND_IDS=y
522# CONFIG_MTD_NAND_DISKONCHIP is not set
523# CONFIG_MTD_NAND_NANDSIM is not set
524# CONFIG_MTD_NAND_PLATFORM is not set
525# CONFIG_MTD_ALAUDA is not set
526# CONFIG_MTD_ONENAND is not set
527
528#
529# UBI - Unsorted block images
530#
531# CONFIG_MTD_UBI is not set
532# CONFIG_PARPORT is not set
533CONFIG_BLK_DEV=y
534# CONFIG_BLK_DEV_COW_COMMON is not set
535CONFIG_BLK_DEV_LOOP=y
536# CONFIG_BLK_DEV_CRYPTOLOOP is not set
537# CONFIG_BLK_DEV_NBD is not set
538# CONFIG_BLK_DEV_UB is not set
539# CONFIG_BLK_DEV_RAM is not set
540# CONFIG_CDROM_PKTCDVD is not set
541# CONFIG_ATA_OVER_ETH is not set
542CONFIG_MISC_DEVICES=y
543# CONFIG_EEPROM_93CX6 is not set
544
545#
546# SCSI device support
547#
548# CONFIG_RAID_ATTRS is not set
549CONFIG_SCSI=y
550CONFIG_SCSI_DMA=y
551# CONFIG_SCSI_TGT is not set
552# CONFIG_SCSI_NETLINK is not set
553# CONFIG_SCSI_PROC_FS is not set
554
555#
556# SCSI support type (disk, tape, CD-ROM)
557#
558CONFIG_BLK_DEV_SD=y
559# CONFIG_CHR_DEV_ST is not set
560# CONFIG_CHR_DEV_OSST is not set
561# CONFIG_BLK_DEV_SR is not set
562# CONFIG_CHR_DEV_SG is not set
563# CONFIG_CHR_DEV_SCH is not set
564
565#
566# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
567#
568# CONFIG_SCSI_MULTI_LUN is not set
569# CONFIG_SCSI_CONSTANTS is not set
570# CONFIG_SCSI_LOGGING is not set
571# CONFIG_SCSI_SCAN_ASYNC is not set
572CONFIG_SCSI_WAIT_SCAN=m
573
574#
575# SCSI Transports
576#
577# CONFIG_SCSI_SPI_ATTRS is not set
578# CONFIG_SCSI_FC_ATTRS is not set
579# CONFIG_SCSI_ISCSI_ATTRS is not set
580# CONFIG_SCSI_SAS_LIBSAS is not set
581# CONFIG_SCSI_SRP_ATTRS is not set
582CONFIG_SCSI_LOWLEVEL=y
583# CONFIG_ISCSI_TCP is not set
584# CONFIG_SCSI_DEBUG is not set
585# CONFIG_ATA is not set
586# CONFIG_MD is not set
587CONFIG_NETDEVICES=y
588# CONFIG_NETDEVICES_MULTIQUEUE is not set
589# CONFIG_DUMMY is not set
590# CONFIG_BONDING is not set
591# CONFIG_MACVLAN is not set
592# CONFIG_EQUALIZER is not set
593CONFIG_TUN=y
594# CONFIG_VETH is not set
595# CONFIG_PHYLIB is not set
596CONFIG_NET_ETHERNET=y
597CONFIG_MII=y
598# CONFIG_AX88796 is not set
599# CONFIG_SMC91X is not set
600# CONFIG_DM9000 is not set
601# CONFIG_IBM_NEW_EMAC_ZMII is not set
602# CONFIG_IBM_NEW_EMAC_RGMII is not set
603# CONFIG_IBM_NEW_EMAC_TAH is not set
604# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
605# CONFIG_B44 is not set
606CONFIG_NETDEV_1000=y
607CONFIG_NETDEV_10000=y
608
609#
610# Wireless LAN
611#
612# CONFIG_WLAN_PRE80211 is not set
613# CONFIG_WLAN_80211 is not set
614
615#
616# USB Network Adapters
617#
618# CONFIG_USB_CATC is not set
619# CONFIG_USB_KAWETH is not set
620# CONFIG_USB_PEGASUS is not set
621# CONFIG_USB_RTL8150 is not set
622CONFIG_USB_USBNET=y
623# CONFIG_USB_NET_AX8817X is not set
624CONFIG_USB_NET_CDCETHER=y
625# CONFIG_USB_NET_DM9601 is not set
626# CONFIG_USB_NET_GL620A is not set
627CONFIG_USB_NET_NET1080=y
628# CONFIG_USB_NET_PLUSB is not set
629# CONFIG_USB_NET_MCS7830 is not set
630# CONFIG_USB_NET_RNDIS_HOST is not set
631# CONFIG_USB_NET_CDC_SUBSET is not set
632CONFIG_USB_NET_ZAURUS=y
633# CONFIG_WAN is not set
634CONFIG_PPP=y
635# CONFIG_PPP_MULTILINK is not set
636CONFIG_PPP_FILTER=y
637CONFIG_PPP_ASYNC=y
638# CONFIG_PPP_SYNC_TTY is not set
639CONFIG_PPP_DEFLATE=y
640CONFIG_PPP_BSDCOMP=y
641# CONFIG_PPP_MPPE is not set
642# CONFIG_PPPOE is not set
643# CONFIG_PPPOL2TP is not set
644# CONFIG_SLIP is not set
645CONFIG_SLHC=y
646# CONFIG_SHAPER is not set
647# CONFIG_NETCONSOLE is not set
648# CONFIG_NETPOLL is not set
649# CONFIG_NET_POLL_CONTROLLER is not set
650# CONFIG_ISDN is not set
651
652#
653# Input device support
654#
655CONFIG_INPUT=y
656# CONFIG_INPUT_FF_MEMLESS is not set
657# CONFIG_INPUT_POLLDEV is not set
658
659#
660# Userland interfaces
661#
662CONFIG_INPUT_MOUSEDEV=y
663# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
664CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
665CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
666# CONFIG_INPUT_JOYDEV is not set
667CONFIG_INPUT_EVDEV=y
668# CONFIG_INPUT_EVBUG is not set
669
670#
671# Input Device Drivers
672#
673CONFIG_INPUT_KEYBOARD=y
674# CONFIG_KEYBOARD_ATKBD is not set
675# CONFIG_KEYBOARD_SUNKBD is not set
676# CONFIG_KEYBOARD_LKKBD is not set
677# CONFIG_KEYBOARD_XTKBD is not set
678# CONFIG_KEYBOARD_NEWTON is not set
679# CONFIG_KEYBOARD_STOWAWAY is not set
680CONFIG_KEYBOARD_OMAP=y
681# CONFIG_KEYBOARD_GPIO is not set
682# CONFIG_INPUT_MOUSE is not set
683# CONFIG_INPUT_JOYSTICK is not set
684# CONFIG_INPUT_TABLET is not set
685CONFIG_INPUT_TOUCHSCREEN=y
686CONFIG_TOUCHSCREEN_ADS7846=y
687# CONFIG_TOUCHSCREEN_FUJITSU is not set
688# CONFIG_TOUCHSCREEN_GUNZE is not set
689# CONFIG_TOUCHSCREEN_ELO is not set
690# CONFIG_TOUCHSCREEN_MTOUCH is not set
691# CONFIG_TOUCHSCREEN_MK712 is not set
692# CONFIG_TOUCHSCREEN_PENMOUNT is not set
693# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
694# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
695# CONFIG_TOUCHSCREEN_UCB1400 is not set
696# CONFIG_TOUCHSCREEN_TSC2102 is not set
697# CONFIG_TOUCHSCREEN_TSC210X is not set
698# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
699# CONFIG_INPUT_MISC is not set
700
701#
702# Hardware I/O ports
703#
704CONFIG_SERIO=y
705CONFIG_SERIO_SERPORT=y
706# CONFIG_SERIO_RAW is not set
707# CONFIG_GAMEPORT is not set
708
709#
710# Character devices
711#
712CONFIG_VT=y
713CONFIG_VT_CONSOLE=y
714CONFIG_HW_CONSOLE=y
715# CONFIG_VT_HW_CONSOLE_BINDING is not set
716# CONFIG_SERIAL_NONSTANDARD is not set
717
718#
719# Serial drivers
720#
721CONFIG_SERIAL_8250=y
722CONFIG_SERIAL_8250_CONSOLE=y
723CONFIG_SERIAL_8250_NR_UARTS=4
724CONFIG_SERIAL_8250_RUNTIME_UARTS=4
725# CONFIG_SERIAL_8250_EXTENDED is not set
726
727#
728# Non-8250 serial port support
729#
730CONFIG_SERIAL_CORE=y
731CONFIG_SERIAL_CORE_CONSOLE=y
732CONFIG_UNIX98_PTYS=y
733# CONFIG_LEGACY_PTYS is not set
734# CONFIG_IPMI_HANDLER is not set
735CONFIG_HW_RANDOM=m
736CONFIG_HW_RANDOM_OMAP=m
737# CONFIG_NVRAM is not set
738# CONFIG_R3964 is not set
739# CONFIG_RAW_DRIVER is not set
740# CONFIG_TCG_TPM is not set
741CONFIG_I2C=y
742CONFIG_I2C_BOARDINFO=y
743# CONFIG_I2C_CHARDEV is not set
744
745#
746# I2C Algorithms
747#
748# CONFIG_I2C_ALGOBIT is not set
749# CONFIG_I2C_ALGOPCF is not set
750# CONFIG_I2C_ALGOPCA is not set
751
752#
753# I2C Hardware Bus support
754#
755# CONFIG_I2C_GPIO is not set
756# CONFIG_I2C_OCORES is not set
757CONFIG_I2C_OMAP=y
758# CONFIG_I2C_PARPORT_LIGHT is not set
759# CONFIG_I2C_SIMTEC is not set
760# CONFIG_I2C_TAOS_EVM is not set
761# CONFIG_I2C_STUB is not set
762# CONFIG_I2C_TINY_USB is not set
763
764#
765# Miscellaneous I2C Chip support
766#
767# CONFIG_SENSORS_DS1337 is not set
768# CONFIG_SENSORS_DS1374 is not set
769# CONFIG_DS1682 is not set
770# CONFIG_SENSORS_EEPROM is not set
771# CONFIG_SENSORS_PCF8574 is not set
772# CONFIG_SENSORS_PCA9539 is not set
773# CONFIG_SENSORS_PCF8591 is not set
774# CONFIG_ISP1301_OMAP is not set
775# CONFIG_TPS65010 is not set
776CONFIG_SENSORS_TLV320AIC23=y
777# CONFIG_GPIOEXPANDER_OMAP is not set
778# CONFIG_SENSORS_MAX6875 is not set
779# CONFIG_SENSORS_TSL2550 is not set
780# CONFIG_I2C_DEBUG_CORE is not set
781# CONFIG_I2C_DEBUG_ALGO is not set
782# CONFIG_I2C_DEBUG_BUS is not set
783# CONFIG_I2C_DEBUG_CHIP is not set
784
785#
786# SPI support
787#
788CONFIG_SPI=y
789# CONFIG_SPI_DEBUG is not set
790CONFIG_SPI_MASTER=y
791
792#
793# SPI Master Controller Drivers
794#
795CONFIG_SPI_BITBANG=y
796CONFIG_SPI_OMAP_UWIRE=y
797
798#
799# SPI Protocol Masters
800#
801# CONFIG_SPI_AT25 is not set
802# CONFIG_SPI_TSC2101 is not set
803# CONFIG_SPI_TSC2102 is not set
804# CONFIG_SPI_TSC210X is not set
805# CONFIG_SPI_TSC2301 is not set
806# CONFIG_SPI_SPIDEV is not set
807# CONFIG_SPI_TLE62X0 is not set
808# CONFIG_W1 is not set
809# CONFIG_POWER_SUPPLY is not set
810# CONFIG_HWMON is not set
811CONFIG_WATCHDOG=y
812CONFIG_WATCHDOG_NOWAYOUT=y
813
814#
815# Watchdog Device Drivers
816#
817# CONFIG_SOFT_WATCHDOG is not set
818CONFIG_OMAP_WATCHDOG=y
819
820#
821# USB-based Watchdog Cards
822#
823# CONFIG_USBPCWATCHDOG is not set
824
825#
826# Sonics Silicon Backplane
827#
828CONFIG_SSB_POSSIBLE=y
829# CONFIG_SSB is not set
830
831#
832# Multifunction device drivers
833#
834# CONFIG_MFD_SM501 is not set
835
836#
837# Multimedia devices
838#
839# CONFIG_VIDEO_DEV is not set
840# CONFIG_DVB_CORE is not set
841CONFIG_DAB=y
842# CONFIG_USB_DABUSB is not set
843
844#
845# Graphics support
846#
847# CONFIG_VGASTATE is not set
848# CONFIG_VIDEO_OUTPUT_CONTROL is not set
849CONFIG_FB=y
850# CONFIG_FIRMWARE_EDID is not set
851# CONFIG_FB_DDC is not set
852CONFIG_FB_CFB_FILLRECT=y
853CONFIG_FB_CFB_COPYAREA=y
854CONFIG_FB_CFB_IMAGEBLIT=y
855# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
856# CONFIG_FB_SYS_FILLRECT is not set
857# CONFIG_FB_SYS_COPYAREA is not set
858# CONFIG_FB_SYS_IMAGEBLIT is not set
859# CONFIG_FB_SYS_FOPS is not set
860CONFIG_FB_DEFERRED_IO=y
861# CONFIG_FB_SVGALIB is not set
862# CONFIG_FB_MACMODES is not set
863# CONFIG_FB_BACKLIGHT is not set
864# CONFIG_FB_MODE_HELPERS is not set
865# CONFIG_FB_TILEBLITTING is not set
866
867#
868# Frame buffer hardware drivers
869#
870# CONFIG_FB_UVESA is not set
871# CONFIG_FB_S1D13XXX is not set
872# CONFIG_FB_VIRTUAL is not set
873CONFIG_FB_OMAP=y
874CONFIG_FB_OMAP_LCDC_EXTERNAL=y
875CONFIG_FB_OMAP_LCDC_HWA742=y
876# CONFIG_FB_OMAP_LCDC_BLIZZARD is not set
877CONFIG_FB_OMAP_MANUAL_UPDATE=y
878# CONFIG_FB_OMAP_LCD_MIPID is not set
879# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set
880CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=2
881# CONFIG_FB_OMAP_DMA_TUNE is not set
882# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
883
884#
885# Display device support
886#
887# CONFIG_DISPLAY_SUPPORT is not set
888
889#
890# Console display driver support
891#
892# CONFIG_VGA_CONSOLE is not set
893CONFIG_DUMMY_CONSOLE=y
894# CONFIG_FRAMEBUFFER_CONSOLE is not set
895# CONFIG_LOGO is not set
896
897#
898# Sound
899#
900CONFIG_SOUND=y
901
902#
903# Advanced Linux Sound Architecture
904#
905CONFIG_SND=y
906CONFIG_SND_TIMER=y
907CONFIG_SND_PCM=y
908CONFIG_SND_HWDEP=y
909CONFIG_SND_RAWMIDI=y
910# CONFIG_SND_SEQUENCER is not set
911# CONFIG_SND_MIXER_OSS is not set
912# CONFIG_SND_PCM_OSS is not set
913# CONFIG_SND_DYNAMIC_MINORS is not set
914# CONFIG_SND_SUPPORT_OLD_API is not set
915CONFIG_SND_VERBOSE_PROCFS=y
916# CONFIG_SND_VERBOSE_PRINTK is not set
917# CONFIG_SND_DEBUG is not set
918
919#
920# Generic devices
921#
922CONFIG_SND_DUMMY=y
923# CONFIG_SND_MTPAV is not set
924# CONFIG_SND_SERIAL_U16550 is not set
925# CONFIG_SND_MPU401 is not set
926
927#
928# ALSA ARM devices
929#
930CONFIG_SND_OMAP_AIC23=y
931# CONFIG_SND_OMAP_TSC2101 is not set
932# CONFIG_SND_SX1 is not set
933# CONFIG_SND_OMAP_TSC2102 is not set
934# CONFIG_SND_OMAP24XX_EAC is not set
935
936#
937# SPI devices
938#
939
940#
941# USB devices
942#
943CONFIG_SND_USB_AUDIO=y
944# CONFIG_SND_USB_CAIAQ is not set
945
946#
947# System on Chip audio support
948#
949# CONFIG_SND_SOC is not set
950
951#
952# SoC Audio support for SuperH
953#
954
955#
956# Open Sound System
957#
958# CONFIG_SOUND_PRIME is not set
959CONFIG_HID_SUPPORT=y
960CONFIG_HID=y
961CONFIG_HID_DEBUG=y
962# CONFIG_HIDRAW is not set
963
964#
965# USB Input Devices
966#
967CONFIG_USB_HID=y
968# CONFIG_USB_HIDINPUT_POWERBOOK is not set
969# CONFIG_HID_FF is not set
970# CONFIG_USB_HIDDEV is not set
971CONFIG_USB_SUPPORT=y
972CONFIG_USB_ARCH_HAS_HCD=y
973CONFIG_USB_ARCH_HAS_OHCI=y
974# CONFIG_USB_ARCH_HAS_EHCI is not set
975CONFIG_USB=y
976# CONFIG_USB_DEBUG is not set
977
978#
979# Miscellaneous USB options
980#
981CONFIG_USB_DEVICEFS=y
982CONFIG_USB_DEVICE_CLASS=y
983# CONFIG_USB_DYNAMIC_MINORS is not set
984CONFIG_USB_SUSPEND=y
985# CONFIG_USB_PERSIST is not set
986CONFIG_USB_OTG=y
987# CONFIG_USB_OTG_WHITELIST is not set
988# CONFIG_USB_OTG_BLACKLIST_HUB is not set
989
990#
991# USB Host Controller Drivers
992#
993# CONFIG_USB_ISP116X_HCD is not set
994CONFIG_USB_OHCI_HCD=y
995# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
996# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
997CONFIG_USB_OHCI_LITTLE_ENDIAN=y
998# CONFIG_USB_SL811_HCD is not set
999# CONFIG_USB_R8A66597_HCD is not set
1000# CONFIG_USB_MUSB_HDRC is not set
1001# CONFIG_USB_GADGET_MUSB_HDRC is not set
1002
1003#
1004# USB Device Class drivers
1005#
1006# CONFIG_USB_ACM is not set
1007# CONFIG_USB_PRINTER is not set
1008
1009#
1010# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
1011#
1012
1013#
1014# may also be needed; see USB_STORAGE Help for more information
1015#
1016CONFIG_USB_STORAGE=y
1017# CONFIG_USB_STORAGE_DEBUG is not set
1018# CONFIG_USB_STORAGE_DATAFAB is not set
1019# CONFIG_USB_STORAGE_FREECOM is not set
1020# CONFIG_USB_STORAGE_ISD200 is not set
1021# CONFIG_USB_STORAGE_DPCM is not set
1022# CONFIG_USB_STORAGE_USBAT is not set
1023# CONFIG_USB_STORAGE_SDDR09 is not set
1024# CONFIG_USB_STORAGE_SDDR55 is not set
1025# CONFIG_USB_STORAGE_JUMPSHOT is not set
1026# CONFIG_USB_STORAGE_ALAUDA is not set
1027# CONFIG_USB_STORAGE_KARMA is not set
1028# CONFIG_USB_LIBUSUAL is not set
1029
1030#
1031# USB Imaging devices
1032#
1033# CONFIG_USB_MDC800 is not set
1034# CONFIG_USB_MICROTEK is not set
1035# CONFIG_USB_MON is not set
1036
1037#
1038# USB port drivers
1039#
1040
1041#
1042# USB Serial Converter support
1043#
1044CONFIG_USB_SERIAL=y
1045CONFIG_USB_SERIAL_CONSOLE=y
1046# CONFIG_USB_SERIAL_GENERIC is not set
1047# CONFIG_USB_SERIAL_AIRCABLE is not set
1048# CONFIG_USB_SERIAL_AIRPRIME is not set
1049# CONFIG_USB_SERIAL_ARK3116 is not set
1050# CONFIG_USB_SERIAL_BELKIN is not set
1051# CONFIG_USB_SERIAL_CH341 is not set
1052# CONFIG_USB_SERIAL_WHITEHEAT is not set
1053# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
1054# CONFIG_USB_SERIAL_CP2101 is not set
1055# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
1056# CONFIG_USB_SERIAL_EMPEG is not set
1057# CONFIG_USB_SERIAL_FTDI_SIO is not set
1058# CONFIG_USB_SERIAL_FUNSOFT is not set
1059# CONFIG_USB_SERIAL_VISOR is not set
1060# CONFIG_USB_SERIAL_IPAQ is not set
1061# CONFIG_USB_SERIAL_IR is not set
1062# CONFIG_USB_SERIAL_EDGEPORT is not set
1063# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
1064# CONFIG_USB_SERIAL_GARMIN is not set
1065# CONFIG_USB_SERIAL_IPW is not set
1066# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
1067# CONFIG_USB_SERIAL_KEYSPAN is not set
1068# CONFIG_USB_SERIAL_KLSI is not set
1069# CONFIG_USB_SERIAL_KOBIL_SCT is not set
1070# CONFIG_USB_SERIAL_MCT_U232 is not set
1071# CONFIG_USB_SERIAL_MOS7720 is not set
1072# CONFIG_USB_SERIAL_MOS7840 is not set
1073# CONFIG_USB_SERIAL_NAVMAN is not set
1074CONFIG_USB_SERIAL_PL2303=y
1075# CONFIG_USB_SERIAL_OTI6858 is not set
1076# CONFIG_USB_SERIAL_HP4X is not set
1077# CONFIG_USB_SERIAL_SAFE is not set
1078# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
1079# CONFIG_USB_SERIAL_TI is not set
1080# CONFIG_USB_SERIAL_CYBERJACK is not set
1081# CONFIG_USB_SERIAL_XIRCOM is not set
1082# CONFIG_USB_SERIAL_OPTION is not set
1083# CONFIG_USB_SERIAL_OMNINET is not set
1084# CONFIG_USB_SERIAL_DEBUG is not set
1085
1086#
1087# USB Miscellaneous drivers
1088#
1089# CONFIG_USB_EMI62 is not set
1090# CONFIG_USB_EMI26 is not set
1091# CONFIG_USB_ADUTUX is not set
1092# CONFIG_USB_AUERSWALD is not set
1093# CONFIG_USB_RIO500 is not set
1094# CONFIG_USB_LEGOTOWER is not set
1095# CONFIG_USB_LCD is not set
1096# CONFIG_USB_BERRY_CHARGE is not set
1097# CONFIG_USB_LED is not set
1098# CONFIG_USB_CYPRESS_CY7C63 is not set
1099# CONFIG_USB_CYTHERM is not set
1100# CONFIG_USB_PHIDGET is not set
1101# CONFIG_USB_IDMOUSE is not set
1102# CONFIG_USB_FTDI_ELAN is not set
1103# CONFIG_USB_APPLEDISPLAY is not set
1104# CONFIG_USB_LD is not set
1105# CONFIG_USB_TRANCEVIBRATOR is not set
1106# CONFIG_USB_IOWARRIOR is not set
1107# CONFIG_USB_TEST is not set
1108
1109#
1110# USB DSL modem support
1111#
1112
1113#
1114# USB Gadget Support
1115#
1116CONFIG_USB_GADGET=y
1117# CONFIG_USB_GADGET_DEBUG is not set
1118# CONFIG_USB_GADGET_DEBUG_FILES is not set
1119CONFIG_USB_GADGET_SELECTED=y
1120# CONFIG_USB_GADGET_AMD5536UDC is not set
1121# CONFIG_USB_GADGET_ATMEL_USBA is not set
1122# CONFIG_USB_GADGET_FSL_USB2 is not set
1123# CONFIG_USB_GADGET_NET2280 is not set
1124# CONFIG_USB_GADGET_PXA2XX is not set
1125# CONFIG_USB_GADGET_M66592 is not set
1126# CONFIG_USB_GADGET_GOKU is not set
1127# CONFIG_USB_GADGET_LH7A40X is not set
1128CONFIG_USB_GADGET_OMAP=y
1129CONFIG_USB_OMAP=y
1130# CONFIG_USB_GADGET_S3C2410 is not set
1131# CONFIG_USB_GADGET_AT91 is not set
1132# CONFIG_USB_GADGET_DUMMY_HCD is not set
1133# CONFIG_USB_GADGET_DUALSPEED is not set
1134# CONFIG_USB_ZERO is not set
1135CONFIG_USB_ETH=m
1136CONFIG_USB_ETH_RNDIS=y
1137# CONFIG_USB_GADGETFS is not set
1138CONFIG_USB_FILE_STORAGE=m
1139CONFIG_USB_FILE_STORAGE_TEST=y
1140# CONFIG_USB_G_SERIAL is not set
1141# CONFIG_USB_MIDI_GADGET is not set
1142CONFIG_MMC=y
1143# CONFIG_MMC_DEBUG is not set
1144# CONFIG_MMC_UNSAFE_RESUME is not set
1145
1146#
1147# MMC/SD Card Drivers
1148#
1149CONFIG_MMC_BLOCK=y
1150CONFIG_MMC_BLOCK_BOUNCE=y
1151# CONFIG_SDIO_UART is not set
1152
1153#
1154# MMC/SD Host Controller Drivers
1155#
1156CONFIG_MMC_OMAP=y
1157# CONFIG_MMC_SPI is not set
1158# CONFIG_NEW_LEDS is not set
1159CONFIG_RTC_LIB=y
1160# CONFIG_RTC_CLASS is not set
1161
1162#
1163# CBUS support
1164#
1165CONFIG_CBUS=y
1166CONFIG_CBUS_TAHVO=y
1167CONFIG_CBUS_TAHVO_USER=y
1168CONFIG_CBUS_TAHVO_USB=y
1169# CONFIG_CBUS_TAHVO_USB_HOST_BY_DEFAULT is not set
1170CONFIG_CBUS_RETU=y
1171CONFIG_CBUS_RETU_USER=y
1172CONFIG_CBUS_RETU_POWERBUTTON=y
1173CONFIG_CBUS_RETU_RTC=y
1174CONFIG_CBUS_RETU_WDT=y
1175# CONFIG_CBUS_RETU_HEADSET is not set
1176CONFIG_OMAP_DSP=y
1177# CONFIG_OMAP_DSP_MBCMD_VERBOSE is not set
1178CONFIG_OMAP_DSP_FBEXPORT=y
1179
1180#
1181# File systems
1182#
1183CONFIG_EXT2_FS=y
1184# CONFIG_EXT2_FS_XATTR is not set
1185# CONFIG_EXT2_FS_XIP is not set
1186CONFIG_EXT3_FS=y
1187CONFIG_EXT3_FS_XATTR=y
1188# CONFIG_EXT3_FS_POSIX_ACL is not set
1189# CONFIG_EXT3_FS_SECURITY is not set
1190# CONFIG_EXT4DEV_FS is not set
1191CONFIG_JBD=y
1192CONFIG_FS_MBCACHE=y
1193# CONFIG_REISERFS_FS is not set
1194# CONFIG_JFS_FS is not set
1195# CONFIG_FS_POSIX_ACL is not set
1196# CONFIG_XFS_FS is not set
1197# CONFIG_GFS2_FS is not set
1198# CONFIG_OCFS2_FS is not set
1199# CONFIG_MINIX_FS is not set
1200# CONFIG_ROMFS_FS is not set
1201# CONFIG_INOTIFY is not set
1202# CONFIG_QUOTA is not set
1203CONFIG_DNOTIFY=y
1204# CONFIG_AUTOFS_FS is not set
1205# CONFIG_AUTOFS4_FS is not set
1206# CONFIG_FUSE_FS is not set
1207
1208#
1209# CD-ROM/DVD Filesystems
1210#
1211# CONFIG_ISO9660_FS is not set
1212# CONFIG_UDF_FS is not set
1213
1214#
1215# DOS/FAT/NT Filesystems
1216#
1217CONFIG_FAT_FS=y
1218CONFIG_MSDOS_FS=y
1219CONFIG_VFAT_FS=y
1220CONFIG_FAT_DEFAULT_CODEPAGE=437
1221CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
1222# CONFIG_NTFS_FS is not set
1223
1224#
1225# Pseudo filesystems
1226#
1227CONFIG_PROC_FS=y
1228CONFIG_PROC_SYSCTL=y
1229CONFIG_SYSFS=y
1230CONFIG_TMPFS=y
1231# CONFIG_TMPFS_POSIX_ACL is not set
1232# CONFIG_HUGETLB_PAGE is not set
1233# CONFIG_CONFIGFS_FS is not set
1234
1235#
1236# Miscellaneous filesystems
1237#
1238# CONFIG_ADFS_FS is not set
1239# CONFIG_AFFS_FS is not set
1240# CONFIG_HFS_FS is not set
1241# CONFIG_HFSPLUS_FS is not set
1242# CONFIG_BEFS_FS is not set
1243# CONFIG_BFS_FS is not set
1244# CONFIG_EFS_FS is not set
1245CONFIG_JFFS2_FS=y
1246CONFIG_JFFS2_FS_DEBUG=0
1247CONFIG_JFFS2_FS_WRITEBUFFER=y
1248# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
1249CONFIG_JFFS2_SUMMARY=y
1250# CONFIG_JFFS2_FS_XATTR is not set
1251CONFIG_JFFS2_COMPRESSION_OPTIONS=y
1252CONFIG_JFFS2_ZLIB=y
1253# CONFIG_JFFS2_LZO is not set
1254CONFIG_JFFS2_RTIME=y
1255# CONFIG_JFFS2_RUBIN is not set
1256# CONFIG_JFFS2_CMODE_NONE is not set
1257CONFIG_JFFS2_CMODE_PRIORITY=y
1258# CONFIG_JFFS2_CMODE_SIZE is not set
1259# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
1260# CONFIG_CRAMFS is not set
1261# CONFIG_VXFS_FS is not set
1262# CONFIG_HPFS_FS is not set
1263# CONFIG_QNX4FS_FS is not set
1264# CONFIG_SYSV_FS is not set
1265# CONFIG_UFS_FS is not set
1266CONFIG_NETWORK_FILESYSTEMS=y
1267CONFIG_NFS_FS=y
1268CONFIG_NFS_V3=y
1269# CONFIG_NFS_V3_ACL is not set
1270# CONFIG_NFS_V4 is not set
1271# CONFIG_NFS_DIRECTIO is not set
1272# CONFIG_NFSD is not set
1273# CONFIG_ROOT_NFS is not set
1274CONFIG_LOCKD=y
1275CONFIG_LOCKD_V4=y
1276CONFIG_NFS_COMMON=y
1277CONFIG_SUNRPC=y
1278# CONFIG_SUNRPC_BIND34 is not set
1279# CONFIG_RPCSEC_GSS_KRB5 is not set
1280# CONFIG_RPCSEC_GSS_SPKM3 is not set
1281# CONFIG_SMB_FS is not set
1282# CONFIG_CIFS is not set
1283# CONFIG_NCP_FS is not set
1284# CONFIG_CODA_FS is not set
1285# CONFIG_AFS_FS is not set
1286
1287#
1288# Partition Types
1289#
1290CONFIG_PARTITION_ADVANCED=y
1291# CONFIG_ACORN_PARTITION is not set
1292# CONFIG_OSF_PARTITION is not set
1293# CONFIG_AMIGA_PARTITION is not set
1294# CONFIG_ATARI_PARTITION is not set
1295# CONFIG_MAC_PARTITION is not set
1296CONFIG_MSDOS_PARTITION=y
1297# CONFIG_BSD_DISKLABEL is not set
1298# CONFIG_MINIX_SUBPARTITION is not set
1299# CONFIG_SOLARIS_X86_PARTITION is not set
1300# CONFIG_UNIXWARE_DISKLABEL is not set
1301# CONFIG_LDM_PARTITION is not set
1302# CONFIG_SGI_PARTITION is not set
1303# CONFIG_ULTRIX_PARTITION is not set
1304# CONFIG_SUN_PARTITION is not set
1305# CONFIG_KARMA_PARTITION is not set
1306# CONFIG_EFI_PARTITION is not set
1307# CONFIG_SYSV68_PARTITION is not set
1308CONFIG_NLS=y
1309CONFIG_NLS_DEFAULT="iso8859-1"
1310CONFIG_NLS_CODEPAGE_437=y
1311# CONFIG_NLS_CODEPAGE_737 is not set
1312# CONFIG_NLS_CODEPAGE_775 is not set
1313# CONFIG_NLS_CODEPAGE_850 is not set
1314CONFIG_NLS_CODEPAGE_852=y
1315# CONFIG_NLS_CODEPAGE_855 is not set
1316# CONFIG_NLS_CODEPAGE_857 is not set
1317# CONFIG_NLS_CODEPAGE_860 is not set
1318# CONFIG_NLS_CODEPAGE_861 is not set
1319# CONFIG_NLS_CODEPAGE_862 is not set
1320# CONFIG_NLS_CODEPAGE_863 is not set
1321# CONFIG_NLS_CODEPAGE_864 is not set
1322# CONFIG_NLS_CODEPAGE_865 is not set
1323# CONFIG_NLS_CODEPAGE_866 is not set
1324# CONFIG_NLS_CODEPAGE_869 is not set
1325# CONFIG_NLS_CODEPAGE_936 is not set
1326# CONFIG_NLS_CODEPAGE_950 is not set
1327# CONFIG_NLS_CODEPAGE_932 is not set
1328# CONFIG_NLS_CODEPAGE_949 is not set
1329# CONFIG_NLS_CODEPAGE_874 is not set
1330# CONFIG_NLS_ISO8859_8 is not set
1331# CONFIG_NLS_CODEPAGE_1250 is not set
1332# CONFIG_NLS_CODEPAGE_1251 is not set
1333# CONFIG_NLS_ASCII is not set
1334CONFIG_NLS_ISO8859_1=y
1335# CONFIG_NLS_ISO8859_2 is not set
1336# CONFIG_NLS_ISO8859_3 is not set
1337# CONFIG_NLS_ISO8859_4 is not set
1338# CONFIG_NLS_ISO8859_5 is not set
1339# CONFIG_NLS_ISO8859_6 is not set
1340# CONFIG_NLS_ISO8859_7 is not set
1341# CONFIG_NLS_ISO8859_9 is not set
1342# CONFIG_NLS_ISO8859_13 is not set
1343# CONFIG_NLS_ISO8859_14 is not set
1344CONFIG_NLS_ISO8859_15=y
1345# CONFIG_NLS_KOI8_R is not set
1346# CONFIG_NLS_KOI8_U is not set
1347CONFIG_NLS_UTF8=y
1348# CONFIG_DLM is not set
1349CONFIG_INSTRUMENTATION=y
1350# CONFIG_PROFILING is not set
1351# CONFIG_MARKERS is not set
1352
1353#
1354# Kernel hacking
1355#
1356# CONFIG_PRINTK_TIME is not set
1357CONFIG_ENABLE_WARN_DEPRECATED=y
1358CONFIG_ENABLE_MUST_CHECK=y
1359CONFIG_MAGIC_SYSRQ=y
1360# CONFIG_UNUSED_SYMBOLS is not set
1361# CONFIG_DEBUG_FS is not set
1362# CONFIG_HEADERS_CHECK is not set
1363CONFIG_DEBUG_KERNEL=y
1364# CONFIG_DEBUG_SHIRQ is not set
1365CONFIG_DETECT_SOFTLOCKUP=y
1366CONFIG_SCHED_DEBUG=y
1367# CONFIG_SCHEDSTATS is not set
1368# CONFIG_TIMER_STATS is not set
1369# CONFIG_DEBUG_SLAB is not set
1370# CONFIG_DEBUG_RT_MUTEXES is not set
1371# CONFIG_RT_MUTEX_TESTER is not set
1372# CONFIG_DEBUG_SPINLOCK is not set
1373CONFIG_DEBUG_MUTEXES=y
1374# CONFIG_DEBUG_LOCK_ALLOC is not set
1375# CONFIG_PROVE_LOCKING is not set
1376# CONFIG_LOCK_STAT is not set
1377# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1378# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1379# CONFIG_DEBUG_KOBJECT is not set
1380CONFIG_DEBUG_BUGVERBOSE=y
1381# CONFIG_DEBUG_INFO is not set
1382# CONFIG_DEBUG_VM is not set
1383# CONFIG_DEBUG_LIST is not set
1384# CONFIG_DEBUG_SG is not set
1385CONFIG_FRAME_POINTER=y
1386CONFIG_FORCED_INLINING=y
1387# CONFIG_BOOT_PRINTK_DELAY is not set
1388# CONFIG_RCU_TORTURE_TEST is not set
1389# CONFIG_FAULT_INJECTION is not set
1390# CONFIG_SAMPLES is not set
1391# CONFIG_DEBUG_USER is not set
1392CONFIG_DEBUG_ERRORS=y
1393# CONFIG_DEBUG_LL is not set
1394
1395#
1396# Security options
1397#
1398# CONFIG_KEYS is not set
1399CONFIG_SECURITY=y
1400# CONFIG_SECURITY_NETWORK is not set
1401# CONFIG_SECURITY_CAPABILITIES is not set
1402# CONFIG_SECURITY_ROOTPLUG is not set
1403# CONFIG_SECURITY_LOWMEM is not set
1404# CONFIG_CRYPTO is not set
1405
1406#
1407# Library routines
1408#
1409CONFIG_BITREVERSE=y
1410CONFIG_CRC_CCITT=y
1411# CONFIG_CRC16 is not set
1412# CONFIG_CRC_ITU_T is not set
1413CONFIG_CRC32=y
1414# CONFIG_CRC7 is not set
1415# CONFIG_LIBCRC32C is not set
1416CONFIG_ZLIB_INFLATE=y
1417CONFIG_ZLIB_DEFLATE=y
1418CONFIG_PLIST=y
1419CONFIG_HAS_IOMEM=y
1420CONFIG_HAS_IOPORT=y
1421CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/omap_2430sdp_defconfig b/arch/arm/configs/omap_2430sdp_defconfig
new file mode 100644
index 000000000000..b0617c0da2a1
--- /dev/null
+++ b/arch/arm/configs/omap_2430sdp_defconfig
@@ -0,0 +1,1304 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.23-rc6-omap1
4# Tue Sep 18 11:47:37 2007
5#
6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8CONFIG_GENERIC_GPIO=y
9CONFIG_GENERIC_TIME=y
10CONFIG_GENERIC_CLOCKEVENTS=y
11CONFIG_MMU=y
12# CONFIG_NO_IOPORT is not set
13CONFIG_GENERIC_HARDIRQS=y
14CONFIG_STACKTRACE_SUPPORT=y
15CONFIG_LOCKDEP_SUPPORT=y
16CONFIG_TRACE_IRQFLAGS_SUPPORT=y
17CONFIG_HARDIRQS_SW_RESEND=y
18CONFIG_GENERIC_IRQ_PROBE=y
19CONFIG_RWSEM_GENERIC_SPINLOCK=y
20# CONFIG_ARCH_HAS_ILOG2_U32 is not set
21# CONFIG_ARCH_HAS_ILOG2_U64 is not set
22CONFIG_GENERIC_HWEIGHT=y
23CONFIG_GENERIC_CALIBRATE_DELAY=y
24CONFIG_ZONE_DMA=y
25CONFIG_VECTORS_BASE=0xffff0000
26CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
27
28#
29# General setup
30#
31CONFIG_EXPERIMENTAL=y
32CONFIG_BROKEN_ON_SMP=y
33CONFIG_LOCK_KERNEL=y
34CONFIG_INIT_ENV_ARG_LIMIT=32
35CONFIG_LOCALVERSION=""
36CONFIG_LOCALVERSION_AUTO=y
37CONFIG_SWAP=y
38CONFIG_SYSVIPC=y
39CONFIG_SYSVIPC_SYSCTL=y
40# CONFIG_POSIX_MQUEUE is not set
41CONFIG_BSD_PROCESS_ACCT=y
42# CONFIG_BSD_PROCESS_ACCT_V3 is not set
43# CONFIG_TASKSTATS is not set
44# CONFIG_USER_NS is not set
45# CONFIG_AUDIT is not set
46# CONFIG_IKCONFIG is not set
47CONFIG_LOG_BUF_SHIFT=14
48CONFIG_SYSFS_DEPRECATED=y
49# CONFIG_RELAY is not set
50CONFIG_BLK_DEV_INITRD=y
51CONFIG_INITRAMFS_SOURCE=""
52CONFIG_CC_OPTIMIZE_FOR_SIZE=y
53CONFIG_SYSCTL=y
54CONFIG_EMBEDDED=y
55CONFIG_UID16=y
56# CONFIG_SYSCTL_SYSCALL is not set
57CONFIG_KALLSYMS=y
58# CONFIG_KALLSYMS_ALL is not set
59CONFIG_KALLSYMS_EXTRA_PASS=y
60CONFIG_HOTPLUG=y
61CONFIG_PRINTK=y
62CONFIG_BUG=y
63CONFIG_ELF_CORE=y
64CONFIG_BASE_FULL=y
65CONFIG_FUTEX=y
66CONFIG_ANON_INODES=y
67CONFIG_EPOLL=y
68CONFIG_SIGNALFD=y
69CONFIG_TIMERFD=y
70CONFIG_EVENTFD=y
71CONFIG_SHMEM=y
72CONFIG_VM_EVENT_COUNTERS=y
73CONFIG_SLAB=y
74# CONFIG_SLUB is not set
75# CONFIG_SLOB is not set
76CONFIG_RT_MUTEXES=y
77# CONFIG_TINY_SHMEM is not set
78CONFIG_BASE_SMALL=0
79CONFIG_MODULES=y
80CONFIG_MODULE_UNLOAD=y
81# CONFIG_MODULE_FORCE_UNLOAD is not set
82CONFIG_MODVERSIONS=y
83CONFIG_MODULE_SRCVERSION_ALL=y
84CONFIG_KMOD=y
85CONFIG_BLOCK=y
86# CONFIG_LBD is not set
87# CONFIG_BLK_DEV_IO_TRACE is not set
88# CONFIG_LSF is not set
89# CONFIG_BLK_DEV_BSG is not set
90
91#
92# IO Schedulers
93#
94CONFIG_IOSCHED_NOOP=y
95CONFIG_IOSCHED_AS=y
96CONFIG_IOSCHED_DEADLINE=y
97CONFIG_IOSCHED_CFQ=y
98CONFIG_DEFAULT_AS=y
99# CONFIG_DEFAULT_DEADLINE is not set
100# CONFIG_DEFAULT_CFQ is not set
101# CONFIG_DEFAULT_NOOP is not set
102CONFIG_DEFAULT_IOSCHED="anticipatory"
103
104#
105# System Type
106#
107# CONFIG_ARCH_AAEC2000 is not set
108# CONFIG_ARCH_INTEGRATOR is not set
109# CONFIG_ARCH_REALVIEW is not set
110# CONFIG_ARCH_VERSATILE is not set
111# CONFIG_ARCH_AT91 is not set
112# CONFIG_ARCH_CLPS7500 is not set
113# CONFIG_ARCH_CLPS711X is not set
114# CONFIG_ARCH_CO285 is not set
115# CONFIG_ARCH_EBSA110 is not set
116# CONFIG_ARCH_EP93XX is not set
117# CONFIG_ARCH_FOOTBRIDGE is not set
118# CONFIG_ARCH_NETX is not set
119# CONFIG_ARCH_H720X is not set
120# CONFIG_ARCH_IMX is not set
121# CONFIG_ARCH_IOP13XX is not set
122# CONFIG_ARCH_IOP32X is not set
123# CONFIG_ARCH_IOP33X is not set
124# CONFIG_ARCH_IXP23XX is not set
125# CONFIG_ARCH_IXP2000 is not set
126# CONFIG_ARCH_IXP4XX is not set
127# CONFIG_ARCH_L7200 is not set
128# CONFIG_ARCH_KS8695 is not set
129# CONFIG_ARCH_NS9XXX is not set
130# CONFIG_ARCH_MXC is not set
131# CONFIG_ARCH_PNX4008 is not set
132# CONFIG_ARCH_PXA is not set
133# CONFIG_ARCH_RPC is not set
134# CONFIG_ARCH_SA1100 is not set
135# CONFIG_ARCH_S3C2410 is not set
136# CONFIG_ARCH_SHARK is not set
137# CONFIG_ARCH_LH7A40X is not set
138# CONFIG_ARCH_DAVINCI is not set
139CONFIG_ARCH_OMAP=y
140
141#
142# TI OMAP Implementations
143#
144# CONFIG_ARCH_OMAP1 is not set
145CONFIG_ARCH_OMAP2=y
146# CONFIG_ARCH_OMAP3 is not set
147
148#
149# OMAP Feature Selections
150#
151# CONFIG_OMAP_RESET_CLOCKS is not set
152CONFIG_OMAP_BOOT_TAG=y
153# CONFIG_OMAP_BOOT_REASON is not set
154# CONFIG_OMAP_COMPONENT_VERSION is not set
155# CONFIG_OMAP_GPIO_SWITCH is not set
156CONFIG_OMAP_MUX=y
157# CONFIG_OMAP_MUX_DEBUG is not set
158# CONFIG_OMAP_MUX_WARNINGS is not set
159# CONFIG_OMAP_STI is not set
160CONFIG_OMAP_MCBSP=y
161# CONFIG_OMAP_MMU_FWK is not set
162# CONFIG_OMAP_MBOX_FWK is not set
163CONFIG_OMAP_MPU_TIMER=y
164# CONFIG_OMAP_32K_TIMER is not set
165CONFIG_OMAP_DM_TIMER=y
166CONFIG_OMAP_LL_DEBUG_UART1=y
167# CONFIG_OMAP_LL_DEBUG_UART2 is not set
168# CONFIG_OMAP_LL_DEBUG_UART3 is not set
169CONFIG_OMAP_SERIAL_WAKE=y
170# CONFIG_OMAP_DSP is not set
171# CONFIG_MACH_OMAP_GENERIC is not set
172
173#
174# OMAP Core Type
175#
176CONFIG_ARCH_OMAP24XX=y
177# CONFIG_ARCH_OMAP2420 is not set
178CONFIG_ARCH_OMAP2430=y
179
180#
181# OMAP Board Type
182#
183# CONFIG_MACH_NOKIA_N800 is not set
184# CONFIG_MACH_OMAP_H4 is not set
185# CONFIG_MACH_OMAP_APOLLON is not set
186# CONFIG_MACH_OMAP_APOLLON_PLUS is not set
187CONFIG_MACH_OMAP_2430SDP=y
188
189#
190# Boot options
191#
192
193#
194# Power management
195#
196
197#
198# Processor Type
199#
200CONFIG_CPU_32=y
201CONFIG_CPU_V6=y
202# CONFIG_CPU_32v6K is not set
203CONFIG_CPU_32v6=y
204CONFIG_CPU_ABRT_EV6=y
205CONFIG_CPU_PABRT_NOIFAR=y
206CONFIG_CPU_CACHE_V6=y
207CONFIG_CPU_CACHE_VIPT=y
208CONFIG_CPU_COPY_V6=y
209CONFIG_CPU_TLB_V6=y
210CONFIG_CPU_HAS_ASID=y
211CONFIG_CPU_CP15=y
212CONFIG_CPU_CP15_MMU=y
213
214#
215# Processor Features
216#
217CONFIG_ARM_THUMB=y
218# CONFIG_CPU_ICACHE_DISABLE is not set
219# CONFIG_CPU_DCACHE_DISABLE is not set
220# CONFIG_CPU_BPREDICT_DISABLE is not set
221# CONFIG_OUTER_CACHE is not set
222
223#
224# Bus support
225#
226# CONFIG_PCI_SYSCALL is not set
227# CONFIG_ARCH_SUPPORTS_MSI is not set
228
229#
230# PCCARD (PCMCIA/CardBus) support
231#
232# CONFIG_PCCARD is not set
233
234#
235# Kernel Features
236#
237# CONFIG_TICK_ONESHOT is not set
238# CONFIG_NO_HZ is not set
239# CONFIG_HIGH_RES_TIMERS is not set
240CONFIG_PREEMPT=y
241CONFIG_HZ=100
242CONFIG_AEABI=y
243CONFIG_OABI_COMPAT=y
244# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
245CONFIG_SELECT_MEMORY_MODEL=y
246CONFIG_FLATMEM_MANUAL=y
247# CONFIG_DISCONTIGMEM_MANUAL is not set
248# CONFIG_SPARSEMEM_MANUAL is not set
249CONFIG_FLATMEM=y
250CONFIG_FLAT_NODE_MEM_MAP=y
251# CONFIG_SPARSEMEM_STATIC is not set
252CONFIG_SPLIT_PTLOCK_CPUS=4
253# CONFIG_RESOURCES_64BIT is not set
254CONFIG_ZONE_DMA_FLAG=1
255CONFIG_BOUNCE=y
256CONFIG_VIRT_TO_BUS=y
257# CONFIG_LEDS is not set
258CONFIG_ALIGNMENT_TRAP=y
259
260#
261# Boot options
262#
263CONFIG_ZBOOT_ROM_TEXT=0x0
264CONFIG_ZBOOT_ROM_BSS=0x0
265CONFIG_CMDLINE="root=/dev/ram0 rw console=ttyS0,115200n8 initrd=0x80600000,8M ramdisk_size=8192"
266# CONFIG_XIP_KERNEL is not set
267# CONFIG_KEXEC is not set
268
269#
270# CPU Frequency scaling
271#
272# CONFIG_CPU_FREQ is not set
273
274#
275# Floating point emulation
276#
277
278#
279# At least one emulation must be selected
280#
281CONFIG_FPE_NWFPE=y
282# CONFIG_FPE_NWFPE_XP is not set
283# CONFIG_FPE_FASTFPE is not set
284# CONFIG_VFP is not set
285
286#
287# Userspace binary formats
288#
289CONFIG_BINFMT_ELF=y
290# CONFIG_BINFMT_AOUT is not set
291CONFIG_BINFMT_MISC=y
292
293#
294# Power management options
295#
296CONFIG_PM=y
297# CONFIG_PM_LEGACY is not set
298# CONFIG_PM_DEBUG is not set
299CONFIG_PM_SLEEP=y
300CONFIG_SUSPEND_UP_POSSIBLE=y
301CONFIG_SUSPEND=y
302# CONFIG_APM_EMULATION is not set
303
304#
305# Networking
306#
307CONFIG_NET=y
308
309#
310# Networking options
311#
312CONFIG_PACKET=y
313# CONFIG_PACKET_MMAP is not set
314CONFIG_UNIX=y
315CONFIG_XFRM=y
316# CONFIG_XFRM_USER is not set
317# CONFIG_XFRM_SUB_POLICY is not set
318# CONFIG_XFRM_MIGRATE is not set
319CONFIG_NET_KEY=y
320# CONFIG_NET_KEY_MIGRATE is not set
321CONFIG_INET=y
322# CONFIG_IP_MULTICAST is not set
323# CONFIG_IP_ADVANCED_ROUTER is not set
324CONFIG_IP_FIB_HASH=y
325CONFIG_IP_PNP=y
326CONFIG_IP_PNP_DHCP=y
327# CONFIG_IP_PNP_BOOTP is not set
328# CONFIG_IP_PNP_RARP is not set
329# CONFIG_NET_IPIP is not set
330# CONFIG_NET_IPGRE is not set
331# CONFIG_ARPD is not set
332# CONFIG_SYN_COOKIES is not set
333# CONFIG_INET_AH is not set
334# CONFIG_INET_ESP is not set
335# CONFIG_INET_IPCOMP is not set
336# CONFIG_INET_XFRM_TUNNEL is not set
337# CONFIG_INET_TUNNEL is not set
338CONFIG_INET_XFRM_MODE_TRANSPORT=y
339CONFIG_INET_XFRM_MODE_TUNNEL=y
340CONFIG_INET_XFRM_MODE_BEET=y
341CONFIG_INET_DIAG=y
342CONFIG_INET_TCP_DIAG=y
343# CONFIG_TCP_CONG_ADVANCED is not set
344CONFIG_TCP_CONG_CUBIC=y
345CONFIG_DEFAULT_TCP_CONG="cubic"
346# CONFIG_TCP_MD5SIG is not set
347# CONFIG_IPV6 is not set
348# CONFIG_INET6_XFRM_TUNNEL is not set
349# CONFIG_INET6_TUNNEL is not set
350# CONFIG_NETWORK_SECMARK is not set
351# CONFIG_NETFILTER is not set
352# CONFIG_IP_DCCP is not set
353# CONFIG_IP_SCTP is not set
354# CONFIG_TIPC is not set
355# CONFIG_ATM is not set
356# CONFIG_BRIDGE is not set
357# CONFIG_VLAN_8021Q is not set
358# CONFIG_DECNET is not set
359# CONFIG_LLC2 is not set
360# CONFIG_IPX is not set
361# CONFIG_ATALK is not set
362# CONFIG_X25 is not set
363# CONFIG_LAPB is not set
364# CONFIG_ECONET is not set
365# CONFIG_WAN_ROUTER is not set
366
367#
368# QoS and/or fair queueing
369#
370# CONFIG_NET_SCHED is not set
371
372#
373# Network testing
374#
375# CONFIG_NET_PKTGEN is not set
376# CONFIG_HAMRADIO is not set
377# CONFIG_IRDA is not set
378# CONFIG_BT is not set
379# CONFIG_AF_RXRPC is not set
380
381#
382# Wireless
383#
384# CONFIG_CFG80211 is not set
385# CONFIG_WIRELESS_EXT is not set
386# CONFIG_MAC80211 is not set
387# CONFIG_IEEE80211 is not set
388# CONFIG_RFKILL is not set
389# CONFIG_NET_9P is not set
390
391#
392# Device Drivers
393#
394
395#
396# Generic Driver Options
397#
398CONFIG_STANDALONE=y
399CONFIG_PREVENT_FIRMWARE_BUILD=y
400# CONFIG_FW_LOADER is not set
401# CONFIG_DEBUG_DRIVER is not set
402# CONFIG_DEBUG_DEVRES is not set
403# CONFIG_SYS_HYPERVISOR is not set
404# CONFIG_CONNECTOR is not set
405CONFIG_MTD=y
406# CONFIG_MTD_DEBUG is not set
407CONFIG_MTD_CONCAT=y
408CONFIG_MTD_PARTITIONS=y
409# CONFIG_MTD_REDBOOT_PARTS is not set
410CONFIG_MTD_CMDLINE_PARTS=y
411# CONFIG_MTD_AFS_PARTS is not set
412
413#
414# User Modules And Translation Layers
415#
416CONFIG_MTD_CHAR=y
417CONFIG_MTD_BLKDEVS=y
418CONFIG_MTD_BLOCK=y
419# CONFIG_FTL is not set
420# CONFIG_NFTL is not set
421# CONFIG_INFTL is not set
422# CONFIG_RFD_FTL is not set
423# CONFIG_SSFDC is not set
424
425#
426# RAM/ROM/Flash chip drivers
427#
428CONFIG_MTD_CFI=y
429# CONFIG_MTD_JEDECPROBE is not set
430CONFIG_MTD_GEN_PROBE=y
431# CONFIG_MTD_CFI_ADV_OPTIONS is not set
432CONFIG_MTD_MAP_BANK_WIDTH_1=y
433CONFIG_MTD_MAP_BANK_WIDTH_2=y
434CONFIG_MTD_MAP_BANK_WIDTH_4=y
435# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
436# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
437# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
438CONFIG_MTD_CFI_I1=y
439CONFIG_MTD_CFI_I2=y
440# CONFIG_MTD_CFI_I4 is not set
441# CONFIG_MTD_CFI_I8 is not set
442CONFIG_MTD_CFI_INTELEXT=y
443# CONFIG_MTD_CFI_AMDSTD is not set
444# CONFIG_MTD_CFI_STAA is not set
445CONFIG_MTD_CFI_UTIL=y
446# CONFIG_MTD_RAM is not set
447# CONFIG_MTD_ROM is not set
448# CONFIG_MTD_ABSENT is not set
449
450#
451# Mapping drivers for chip access
452#
453# CONFIG_MTD_COMPLEX_MAPPINGS is not set
454# CONFIG_MTD_PHYSMAP is not set
455# CONFIG_MTD_ARM_INTEGRATOR is not set
456CONFIG_MTD_OMAP_NOR=y
457# CONFIG_MTD_PLATRAM is not set
458
459#
460# Self-contained MTD device drivers
461#
462# CONFIG_MTD_DATAFLASH is not set
463# CONFIG_MTD_M25P80 is not set
464# CONFIG_MTD_SLRAM is not set
465# CONFIG_MTD_PHRAM is not set
466# CONFIG_MTD_MTDRAM is not set
467# CONFIG_MTD_BLOCK2MTD is not set
468
469#
470# Disk-On-Chip Device Drivers
471#
472# CONFIG_MTD_DOC2000 is not set
473# CONFIG_MTD_DOC2001 is not set
474# CONFIG_MTD_DOC2001PLUS is not set
475# CONFIG_MTD_NAND is not set
476CONFIG_MTD_ONENAND=y
477CONFIG_MTD_ONENAND_VERIFY_WRITE=y
478# CONFIG_MTD_ONENAND_GENERIC is not set
479CONFIG_MTD_ONENAND_OMAP2=y
480# CONFIG_MTD_ONENAND_OTP is not set
481
482#
483# UBI - Unsorted block images
484#
485# CONFIG_MTD_UBI is not set
486# CONFIG_PARPORT is not set
487CONFIG_BLK_DEV=y
488# CONFIG_BLK_DEV_COW_COMMON is not set
489CONFIG_BLK_DEV_LOOP=y
490# CONFIG_BLK_DEV_CRYPTOLOOP is not set
491# CONFIG_BLK_DEV_NBD is not set
492# CONFIG_BLK_DEV_UB is not set
493CONFIG_BLK_DEV_RAM=y
494CONFIG_BLK_DEV_RAM_COUNT=16
495CONFIG_BLK_DEV_RAM_SIZE=16384
496CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
497# CONFIG_CDROM_PKTCDVD is not set
498# CONFIG_ATA_OVER_ETH is not set
499
500#
501# SCSI device support
502#
503# CONFIG_RAID_ATTRS is not set
504CONFIG_SCSI=m
505CONFIG_SCSI_DMA=y
506# CONFIG_SCSI_TGT is not set
507# CONFIG_SCSI_NETLINK is not set
508CONFIG_SCSI_PROC_FS=y
509
510#
511# SCSI support type (disk, tape, CD-ROM)
512#
513CONFIG_BLK_DEV_SD=m
514# CONFIG_CHR_DEV_ST is not set
515# CONFIG_CHR_DEV_OSST is not set
516# CONFIG_BLK_DEV_SR is not set
517CONFIG_CHR_DEV_SG=m
518# CONFIG_CHR_DEV_SCH is not set
519
520#
521# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
522#
523# CONFIG_SCSI_MULTI_LUN is not set
524# CONFIG_SCSI_CONSTANTS is not set
525# CONFIG_SCSI_LOGGING is not set
526# CONFIG_SCSI_SCAN_ASYNC is not set
527CONFIG_SCSI_WAIT_SCAN=m
528
529#
530# SCSI Transports
531#
532# CONFIG_SCSI_SPI_ATTRS is not set
533# CONFIG_SCSI_FC_ATTRS is not set
534# CONFIG_SCSI_ISCSI_ATTRS is not set
535# CONFIG_SCSI_SAS_LIBSAS is not set
536CONFIG_SCSI_LOWLEVEL=y
537# CONFIG_ISCSI_TCP is not set
538# CONFIG_SCSI_DEBUG is not set
539# CONFIG_ATA is not set
540# CONFIG_MD is not set
541CONFIG_NETDEVICES=y
542# CONFIG_NETDEVICES_MULTIQUEUE is not set
543# CONFIG_DUMMY is not set
544# CONFIG_BONDING is not set
545# CONFIG_MACVLAN is not set
546# CONFIG_EQUALIZER is not set
547# CONFIG_TUN is not set
548# CONFIG_PHYLIB is not set
549CONFIG_NET_ETHERNET=y
550CONFIG_MII=y
551# CONFIG_AX88796 is not set
552CONFIG_SMC91X=y
553# CONFIG_DM9000 is not set
554CONFIG_NETDEV_1000=y
555CONFIG_NETDEV_10000=y
556
557#
558# Wireless LAN
559#
560# CONFIG_WLAN_PRE80211 is not set
561# CONFIG_WLAN_80211 is not set
562
563#
564# USB Network Adapters
565#
566# CONFIG_USB_CATC is not set
567# CONFIG_USB_KAWETH is not set
568# CONFIG_USB_PEGASUS is not set
569# CONFIG_USB_RTL8150 is not set
570# CONFIG_USB_USBNET_MII is not set
571# CONFIG_USB_USBNET is not set
572# CONFIG_WAN is not set
573# CONFIG_PPP is not set
574# CONFIG_SLIP is not set
575# CONFIG_SHAPER is not set
576# CONFIG_NETCONSOLE is not set
577# CONFIG_NETPOLL is not set
578# CONFIG_NET_POLL_CONTROLLER is not set
579# CONFIG_ISDN is not set
580
581#
582# Input device support
583#
584CONFIG_INPUT=y
585# CONFIG_INPUT_FF_MEMLESS is not set
586# CONFIG_INPUT_POLLDEV is not set
587
588#
589# Userland interfaces
590#
591# CONFIG_INPUT_MOUSEDEV is not set
592# CONFIG_INPUT_JOYDEV is not set
593# CONFIG_INPUT_TSDEV is not set
594CONFIG_INPUT_EVDEV=y
595# CONFIG_INPUT_EVBUG is not set
596
597#
598# Input Device Drivers
599#
600CONFIG_INPUT_KEYBOARD=y
601# CONFIG_KEYBOARD_ATKBD is not set
602# CONFIG_KEYBOARD_SUNKBD is not set
603# CONFIG_KEYBOARD_LKKBD is not set
604# CONFIG_KEYBOARD_XTKBD is not set
605# CONFIG_KEYBOARD_NEWTON is not set
606# CONFIG_KEYBOARD_STOWAWAY is not set
607# CONFIG_KEYBOARD_OMAP is not set
608CONFIG_KEYBOARD_TWL4030=y
609# CONFIG_KEYBOARD_GPIO is not set
610# CONFIG_INPUT_MOUSE is not set
611# CONFIG_INPUT_JOYSTICK is not set
612# CONFIG_INPUT_TABLET is not set
613CONFIG_INPUT_TOUCHSCREEN=y
614CONFIG_TOUCHSCREEN_ADS7846=y
615# CONFIG_TOUCHSCREEN_FUJITSU is not set
616# CONFIG_TOUCHSCREEN_GUNZE is not set
617# CONFIG_TOUCHSCREEN_ELO is not set
618# CONFIG_TOUCHSCREEN_MTOUCH is not set
619# CONFIG_TOUCHSCREEN_MK712 is not set
620# CONFIG_TOUCHSCREEN_PENMOUNT is not set
621# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
622# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
623# CONFIG_TOUCHSCREEN_UCB1400 is not set
624# CONFIG_TOUCHSCREEN_TSC2102 is not set
625# CONFIG_TOUCHSCREEN_TSC210X is not set
626# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
627# CONFIG_INPUT_MISC is not set
628
629#
630# Hardware I/O ports
631#
632# CONFIG_SERIO is not set
633# CONFIG_GAMEPORT is not set
634
635#
636# Character devices
637#
638CONFIG_VT=y
639CONFIG_VT_CONSOLE=y
640CONFIG_HW_CONSOLE=y
641# CONFIG_VT_HW_CONSOLE_BINDING is not set
642# CONFIG_SERIAL_NONSTANDARD is not set
643
644#
645# Serial drivers
646#
647CONFIG_SERIAL_8250=y
648CONFIG_SERIAL_8250_CONSOLE=y
649CONFIG_SERIAL_8250_NR_UARTS=32
650CONFIG_SERIAL_8250_RUNTIME_UARTS=4
651CONFIG_SERIAL_8250_EXTENDED=y
652CONFIG_SERIAL_8250_MANY_PORTS=y
653CONFIG_SERIAL_8250_SHARE_IRQ=y
654CONFIG_SERIAL_8250_DETECT_IRQ=y
655CONFIG_SERIAL_8250_RSA=y
656
657#
658# Non-8250 serial port support
659#
660CONFIG_SERIAL_CORE=y
661CONFIG_SERIAL_CORE_CONSOLE=y
662CONFIG_UNIX98_PTYS=y
663# CONFIG_LEGACY_PTYS is not set
664# CONFIG_IPMI_HANDLER is not set
665CONFIG_WATCHDOG=y
666CONFIG_WATCHDOG_NOWAYOUT=y
667
668#
669# Watchdog Device Drivers
670#
671# CONFIG_SOFT_WATCHDOG is not set
672CONFIG_OMAP_WATCHDOG=y
673
674#
675# USB-based Watchdog Cards
676#
677# CONFIG_USBPCWATCHDOG is not set
678CONFIG_HW_RANDOM=y
679CONFIG_HW_RANDOM_OMAP=y
680# CONFIG_NVRAM is not set
681# CONFIG_R3964 is not set
682# CONFIG_RAW_DRIVER is not set
683# CONFIG_TCG_TPM is not set
684CONFIG_I2C=y
685CONFIG_I2C_BOARDINFO=y
686CONFIG_I2C_CHARDEV=y
687
688#
689# I2C Algorithms
690#
691# CONFIG_I2C_ALGOBIT is not set
692# CONFIG_I2C_ALGOPCF is not set
693# CONFIG_I2C_ALGOPCA is not set
694
695#
696# I2C Hardware Bus support
697#
698# CONFIG_I2C_GPIO is not set
699# CONFIG_I2C_OCORES is not set
700CONFIG_I2C_OMAP=y
701# CONFIG_I2C_PARPORT_LIGHT is not set
702# CONFIG_I2C_SIMTEC is not set
703# CONFIG_I2C_TAOS_EVM is not set
704# CONFIG_I2C_STUB is not set
705# CONFIG_I2C_TINY_USB is not set
706
707#
708# Miscellaneous I2C Chip support
709#
710# CONFIG_SENSORS_DS1337 is not set
711# CONFIG_SENSORS_DS1374 is not set
712# CONFIG_DS1682 is not set
713# CONFIG_SENSORS_EEPROM is not set
714# CONFIG_SENSORS_PCF8574 is not set
715# CONFIG_SENSORS_PCA9539 is not set
716# CONFIG_SENSORS_PCF8591 is not set
717# CONFIG_TPS65010 is not set
718# CONFIG_SENSORS_TLV320AIC23 is not set
719# CONFIG_GPIOEXPANDER_OMAP is not set
720CONFIG_TWL4030_CORE=y
721CONFIG_TWL4030_GPIO=y
722# CONFIG_SENSORS_MAX6875 is not set
723# CONFIG_SENSORS_TSL2550 is not set
724# CONFIG_MENELAUS is not set
725# CONFIG_I2C_DEBUG_CORE is not set
726# CONFIG_I2C_DEBUG_ALGO is not set
727# CONFIG_I2C_DEBUG_BUS is not set
728# CONFIG_I2C_DEBUG_CHIP is not set
729
730#
731# SPI support
732#
733CONFIG_SPI=y
734# CONFIG_SPI_DEBUG is not set
735CONFIG_SPI_MASTER=y
736
737#
738# SPI Master Controller Drivers
739#
740# CONFIG_SPI_BITBANG is not set
741# CONFIG_SPI_OMAP24XX is not set
742
743#
744# SPI Protocol Masters
745#
746# CONFIG_SPI_AT25 is not set
747# CONFIG_SPI_TSC2101 is not set
748# CONFIG_SPI_TSC2102 is not set
749# CONFIG_SPI_TSC210X is not set
750# CONFIG_SPI_TSC2301 is not set
751# CONFIG_SPI_SPIDEV is not set
752# CONFIG_SPI_TLE62X0 is not set
753# CONFIG_W1 is not set
754# CONFIG_HWMON is not set
755CONFIG_MISC_DEVICES=y
756# CONFIG_EEPROM_93CX6 is not set
757
758#
759# Multifunction device drivers
760#
761# CONFIG_MFD_SM501 is not set
762# CONFIG_NEW_LEDS is not set
763
764#
765# Multimedia devices
766#
767# CONFIG_VIDEO_DEV is not set
768# CONFIG_DVB_CORE is not set
769CONFIG_DAB=y
770# CONFIG_USB_DABUSB is not set
771
772#
773# Graphics support
774#
775# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
776
777#
778# Display device support
779#
780# CONFIG_DISPLAY_SUPPORT is not set
781# CONFIG_VGASTATE is not set
782CONFIG_VIDEO_OUTPUT_CONTROL=m
783CONFIG_FB=y
784CONFIG_FIRMWARE_EDID=y
785# CONFIG_FB_DDC is not set
786# CONFIG_FB_CFB_FILLRECT is not set
787# CONFIG_FB_CFB_COPYAREA is not set
788# CONFIG_FB_CFB_IMAGEBLIT is not set
789# CONFIG_FB_SYS_FILLRECT is not set
790# CONFIG_FB_SYS_COPYAREA is not set
791# CONFIG_FB_SYS_IMAGEBLIT is not set
792# CONFIG_FB_SYS_FOPS is not set
793CONFIG_FB_DEFERRED_IO=y
794# CONFIG_FB_SVGALIB is not set
795# CONFIG_FB_MACMODES is not set
796# CONFIG_FB_BACKLIGHT is not set
797# CONFIG_FB_MODE_HELPERS is not set
798# CONFIG_FB_TILEBLITTING is not set
799
800#
801# Frame buffer hardware drivers
802#
803# CONFIG_FB_S1D13XXX is not set
804CONFIG_FB_OMAP=y
805# CONFIG_FB_OMAP_LCDC_EXTERNAL is not set
806# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set
807CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=2
808# CONFIG_FB_VIRTUAL is not set
809
810#
811# Console display driver support
812#
813# CONFIG_VGA_CONSOLE is not set
814CONFIG_DUMMY_CONSOLE=y
815CONFIG_FRAMEBUFFER_CONSOLE=y
816# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
817# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
818# CONFIG_FONTS is not set
819CONFIG_FONT_8x8=y
820CONFIG_FONT_8x16=y
821CONFIG_LOGO=y
822# CONFIG_LOGO_LINUX_MONO is not set
823# CONFIG_LOGO_LINUX_VGA16 is not set
824CONFIG_LOGO_LINUX_CLUT224=y
825
826#
827# Sound
828#
829# CONFIG_SOUND is not set
830CONFIG_HID_SUPPORT=y
831CONFIG_HID=y
832# CONFIG_HID_DEBUG is not set
833
834#
835# USB Input Devices
836#
837CONFIG_USB_HID=m
838# CONFIG_USB_HIDINPUT_POWERBOOK is not set
839# CONFIG_HID_FF is not set
840# CONFIG_USB_HIDDEV is not set
841
842#
843# USB HID Boot Protocol drivers
844#
845# CONFIG_USB_KBD is not set
846# CONFIG_USB_MOUSE is not set
847CONFIG_USB_SUPPORT=y
848CONFIG_USB_ARCH_HAS_HCD=y
849CONFIG_USB_ARCH_HAS_OHCI=y
850# CONFIG_USB_ARCH_HAS_EHCI is not set
851CONFIG_USB=m
852# CONFIG_USB_DEBUG is not set
853
854#
855# Miscellaneous USB options
856#
857# CONFIG_USB_DEVICEFS is not set
858# CONFIG_USB_DEVICE_CLASS is not set
859# CONFIG_USB_DYNAMIC_MINORS is not set
860CONFIG_USB_SUSPEND=y
861# CONFIG_USB_PERSIST is not set
862CONFIG_USB_OTG=y
863CONFIG_USB_OTG_WHITELIST=y
864# CONFIG_USB_OTG_BLACKLIST_HUB is not set
865
866#
867# USB Host Controller Drivers
868#
869# CONFIG_USB_ISP116X_HCD is not set
870# CONFIG_USB_OHCI_HCD is not set
871# CONFIG_USB_SL811_HCD is not set
872# CONFIG_USB_R8A66597_HCD is not set
873CONFIG_USB_MUSB_HDRC=m
874CONFIG_USB_MUSB_SOC=y
875
876#
877# OMAP 243x high speed USB support
878#
879# CONFIG_USB_MUSB_HOST is not set
880# CONFIG_USB_MUSB_PERIPHERAL is not set
881CONFIG_USB_MUSB_OTG=y
882CONFIG_USB_GADGET_MUSB_HDRC=y
883CONFIG_USB_MUSB_HDRC_HCD=y
884# CONFIG_MUSB_PIO_ONLY is not set
885CONFIG_USB_INVENTRA_DMA=y
886# CONFIG_USB_TI_CPPI_DMA is not set
887CONFIG_USB_MUSB_LOGLEVEL=0
888
889#
890# USB Device Class drivers
891#
892# CONFIG_USB_ACM is not set
893# CONFIG_USB_PRINTER is not set
894
895#
896# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
897#
898
899#
900# may also be needed; see USB_STORAGE Help for more information
901#
902CONFIG_USB_STORAGE=m
903# CONFIG_USB_STORAGE_DEBUG is not set
904# CONFIG_USB_STORAGE_DATAFAB is not set
905# CONFIG_USB_STORAGE_FREECOM is not set
906# CONFIG_USB_STORAGE_DPCM is not set
907# CONFIG_USB_STORAGE_USBAT is not set
908# CONFIG_USB_STORAGE_SDDR09 is not set
909# CONFIG_USB_STORAGE_SDDR55 is not set
910# CONFIG_USB_STORAGE_JUMPSHOT is not set
911# CONFIG_USB_STORAGE_ALAUDA is not set
912# CONFIG_USB_STORAGE_KARMA is not set
913# CONFIG_USB_LIBUSUAL is not set
914
915#
916# USB Imaging devices
917#
918# CONFIG_USB_MDC800 is not set
919# CONFIG_USB_MICROTEK is not set
920CONFIG_USB_MON=y
921
922#
923# USB port drivers
924#
925
926#
927# USB Serial Converter support
928#
929# CONFIG_USB_SERIAL is not set
930
931#
932# USB Miscellaneous drivers
933#
934# CONFIG_USB_EMI62 is not set
935# CONFIG_USB_EMI26 is not set
936# CONFIG_USB_ADUTUX is not set
937# CONFIG_USB_AUERSWALD is not set
938# CONFIG_USB_RIO500 is not set
939# CONFIG_USB_LEGOTOWER is not set
940# CONFIG_USB_LCD is not set
941# CONFIG_USB_BERRY_CHARGE is not set
942# CONFIG_USB_LED is not set
943# CONFIG_USB_CYPRESS_CY7C63 is not set
944# CONFIG_USB_CYTHERM is not set
945# CONFIG_USB_PHIDGET is not set
946# CONFIG_USB_IDMOUSE is not set
947# CONFIG_USB_FTDI_ELAN is not set
948# CONFIG_USB_APPLEDISPLAY is not set
949# CONFIG_USB_LD is not set
950# CONFIG_USB_TRANCEVIBRATOR is not set
951# CONFIG_USB_IOWARRIOR is not set
952
953#
954# USB DSL modem support
955#
956
957#
958# USB Gadget Support
959#
960CONFIG_USB_GADGET=m
961# CONFIG_USB_GADGET_DEBUG is not set
962CONFIG_USB_GADGET_DEBUG_FILES=y
963CONFIG_USB_GADGET_SELECTED=y
964# CONFIG_USB_GADGET_AMD5536UDC is not set
965# CONFIG_USB_GADGET_FSL_USB2 is not set
966# CONFIG_USB_GADGET_NET2280 is not set
967# CONFIG_USB_GADGET_PXA2XX is not set
968# CONFIG_USB_GADGET_M66592 is not set
969# CONFIG_USB_GADGET_GOKU is not set
970# CONFIG_USB_GADGET_LH7A40X is not set
971# CONFIG_USB_GADGET_OMAP is not set
972# CONFIG_USB_GADGET_S3C2410 is not set
973# CONFIG_USB_GADGET_AT91 is not set
974# CONFIG_USB_GADGET_DUMMY_HCD is not set
975CONFIG_USB_GADGET_DUALSPEED=y
976CONFIG_USB_ZERO=m
977# CONFIG_USB_ZERO_HNPTEST is not set
978CONFIG_USB_ETH=m
979CONFIG_USB_ETH_RNDIS=y
980CONFIG_USB_GADGETFS=m
981CONFIG_USB_FILE_STORAGE=m
982# CONFIG_USB_FILE_STORAGE_TEST is not set
983CONFIG_USB_G_SERIAL=m
984# CONFIG_USB_MIDI_GADGET is not set
985CONFIG_MMC=y
986# CONFIG_MMC_DEBUG is not set
987# CONFIG_MMC_UNSAFE_RESUME is not set
988
989#
990# MMC/SD Card Drivers
991#
992CONFIG_MMC_BLOCK=y
993CONFIG_MMC_BLOCK_BOUNCE=y
994
995#
996# MMC/SD Host Controller Drivers
997#
998CONFIG_MMC_OMAP_HS=y
999CONFIG_RTC_LIB=y
1000# CONFIG_RTC_CLASS is not set
1001
1002#
1003# DMA Engine support
1004#
1005# CONFIG_DMA_ENGINE is not set
1006
1007#
1008# DMA Clients
1009#
1010
1011#
1012# DMA Devices
1013#
1014
1015#
1016# CBUS support
1017#
1018# CONFIG_CBUS is not set
1019
1020#
1021# File systems
1022#
1023CONFIG_EXT2_FS=y
1024# CONFIG_EXT2_FS_XATTR is not set
1025# CONFIG_EXT2_FS_XIP is not set
1026CONFIG_EXT3_FS=y
1027# CONFIG_EXT3_FS_XATTR is not set
1028# CONFIG_EXT4DEV_FS is not set
1029CONFIG_JBD=y
1030# CONFIG_JBD_DEBUG is not set
1031# CONFIG_REISERFS_FS is not set
1032# CONFIG_JFS_FS is not set
1033# CONFIG_FS_POSIX_ACL is not set
1034# CONFIG_XFS_FS is not set
1035# CONFIG_GFS2_FS is not set
1036# CONFIG_OCFS2_FS is not set
1037# CONFIG_MINIX_FS is not set
1038# CONFIG_ROMFS_FS is not set
1039CONFIG_INOTIFY=y
1040CONFIG_INOTIFY_USER=y
1041CONFIG_QUOTA=y
1042# CONFIG_QFMT_V1 is not set
1043CONFIG_QFMT_V2=y
1044CONFIG_QUOTACTL=y
1045CONFIG_DNOTIFY=y
1046# CONFIG_AUTOFS_FS is not set
1047# CONFIG_AUTOFS4_FS is not set
1048# CONFIG_FUSE_FS is not set
1049
1050#
1051# CD-ROM/DVD Filesystems
1052#
1053# CONFIG_ISO9660_FS is not set
1054# CONFIG_UDF_FS is not set
1055
1056#
1057# DOS/FAT/NT Filesystems
1058#
1059CONFIG_FAT_FS=y
1060CONFIG_MSDOS_FS=y
1061CONFIG_VFAT_FS=y
1062CONFIG_FAT_DEFAULT_CODEPAGE=437
1063CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
1064# CONFIG_NTFS_FS is not set
1065
1066#
1067# Pseudo filesystems
1068#
1069CONFIG_PROC_FS=y
1070CONFIG_PROC_SYSCTL=y
1071CONFIG_SYSFS=y
1072CONFIG_TMPFS=y
1073# CONFIG_TMPFS_POSIX_ACL is not set
1074# CONFIG_HUGETLB_PAGE is not set
1075CONFIG_RAMFS=y
1076# CONFIG_CONFIGFS_FS is not set
1077
1078#
1079# Miscellaneous filesystems
1080#
1081# CONFIG_ADFS_FS is not set
1082# CONFIG_AFFS_FS is not set
1083# CONFIG_HFS_FS is not set
1084# CONFIG_HFSPLUS_FS is not set
1085# CONFIG_BEFS_FS is not set
1086# CONFIG_BFS_FS is not set
1087# CONFIG_EFS_FS is not set
1088CONFIG_JFFS2_FS=y
1089CONFIG_JFFS2_FS_DEBUG=0
1090CONFIG_JFFS2_FS_WRITEBUFFER=y
1091# CONFIG_JFFS2_SUMMARY is not set
1092# CONFIG_JFFS2_FS_XATTR is not set
1093CONFIG_JFFS2_COMPRESSION_OPTIONS=y
1094CONFIG_JFFS2_ZLIB=y
1095CONFIG_JFFS2_RTIME=y
1096# CONFIG_JFFS2_RUBIN is not set
1097# CONFIG_JFFS2_CMODE_NONE is not set
1098CONFIG_JFFS2_CMODE_PRIORITY=y
1099# CONFIG_JFFS2_CMODE_SIZE is not set
1100# CONFIG_CRAMFS is not set
1101# CONFIG_VXFS_FS is not set
1102# CONFIG_HPFS_FS is not set
1103# CONFIG_QNX4FS_FS is not set
1104# CONFIG_SYSV_FS is not set
1105# CONFIG_UFS_FS is not set
1106
1107#
1108# Network File Systems
1109#
1110CONFIG_NFS_FS=y
1111CONFIG_NFS_V3=y
1112# CONFIG_NFS_V3_ACL is not set
1113# CONFIG_NFS_V4 is not set
1114# CONFIG_NFS_DIRECTIO is not set
1115# CONFIG_NFSD is not set
1116CONFIG_ROOT_NFS=y
1117CONFIG_LOCKD=y
1118CONFIG_LOCKD_V4=y
1119CONFIG_NFS_COMMON=y
1120CONFIG_SUNRPC=y
1121# CONFIG_SUNRPC_BIND34 is not set
1122# CONFIG_RPCSEC_GSS_KRB5 is not set
1123# CONFIG_RPCSEC_GSS_SPKM3 is not set
1124# CONFIG_SMB_FS is not set
1125# CONFIG_CIFS is not set
1126# CONFIG_NCP_FS is not set
1127# CONFIG_CODA_FS is not set
1128# CONFIG_AFS_FS is not set
1129
1130#
1131# Partition Types
1132#
1133CONFIG_PARTITION_ADVANCED=y
1134# CONFIG_ACORN_PARTITION is not set
1135# CONFIG_OSF_PARTITION is not set
1136# CONFIG_AMIGA_PARTITION is not set
1137# CONFIG_ATARI_PARTITION is not set
1138# CONFIG_MAC_PARTITION is not set
1139CONFIG_MSDOS_PARTITION=y
1140# CONFIG_BSD_DISKLABEL is not set
1141# CONFIG_MINIX_SUBPARTITION is not set
1142# CONFIG_SOLARIS_X86_PARTITION is not set
1143# CONFIG_UNIXWARE_DISKLABEL is not set
1144# CONFIG_LDM_PARTITION is not set
1145# CONFIG_SGI_PARTITION is not set
1146# CONFIG_ULTRIX_PARTITION is not set
1147# CONFIG_SUN_PARTITION is not set
1148# CONFIG_KARMA_PARTITION is not set
1149# CONFIG_EFI_PARTITION is not set
1150# CONFIG_SYSV68_PARTITION is not set
1151
1152#
1153# Native Language Support
1154#
1155CONFIG_NLS=y
1156CONFIG_NLS_DEFAULT="iso8859-1"
1157CONFIG_NLS_CODEPAGE_437=y
1158# CONFIG_NLS_CODEPAGE_737 is not set
1159# CONFIG_NLS_CODEPAGE_775 is not set
1160# CONFIG_NLS_CODEPAGE_850 is not set
1161# CONFIG_NLS_CODEPAGE_852 is not set
1162# CONFIG_NLS_CODEPAGE_855 is not set
1163# CONFIG_NLS_CODEPAGE_857 is not set
1164# CONFIG_NLS_CODEPAGE_860 is not set
1165# CONFIG_NLS_CODEPAGE_861 is not set
1166# CONFIG_NLS_CODEPAGE_862 is not set
1167# CONFIG_NLS_CODEPAGE_863 is not set
1168# CONFIG_NLS_CODEPAGE_864 is not set
1169# CONFIG_NLS_CODEPAGE_865 is not set
1170# CONFIG_NLS_CODEPAGE_866 is not set
1171# CONFIG_NLS_CODEPAGE_869 is not set
1172# CONFIG_NLS_CODEPAGE_936 is not set
1173# CONFIG_NLS_CODEPAGE_950 is not set
1174# CONFIG_NLS_CODEPAGE_932 is not set
1175# CONFIG_NLS_CODEPAGE_949 is not set
1176# CONFIG_NLS_CODEPAGE_874 is not set
1177# CONFIG_NLS_ISO8859_8 is not set
1178# CONFIG_NLS_CODEPAGE_1250 is not set
1179# CONFIG_NLS_CODEPAGE_1251 is not set
1180# CONFIG_NLS_ASCII is not set
1181# CONFIG_NLS_ISO8859_1 is not set
1182# CONFIG_NLS_ISO8859_2 is not set
1183# CONFIG_NLS_ISO8859_3 is not set
1184# CONFIG_NLS_ISO8859_4 is not set
1185# CONFIG_NLS_ISO8859_5 is not set
1186# CONFIG_NLS_ISO8859_6 is not set
1187# CONFIG_NLS_ISO8859_7 is not set
1188# CONFIG_NLS_ISO8859_9 is not set
1189# CONFIG_NLS_ISO8859_13 is not set
1190# CONFIG_NLS_ISO8859_14 is not set
1191# CONFIG_NLS_ISO8859_15 is not set
1192# CONFIG_NLS_KOI8_R is not set
1193# CONFIG_NLS_KOI8_U is not set
1194# CONFIG_NLS_UTF8 is not set
1195
1196#
1197# Distributed Lock Manager
1198#
1199# CONFIG_DLM is not set
1200
1201#
1202# Profiling support
1203#
1204# CONFIG_PROFILING is not set
1205
1206#
1207# Kernel hacking
1208#
1209# CONFIG_PRINTK_TIME is not set
1210CONFIG_ENABLE_MUST_CHECK=y
1211CONFIG_MAGIC_SYSRQ=y
1212# CONFIG_UNUSED_SYMBOLS is not set
1213# CONFIG_DEBUG_FS is not set
1214# CONFIG_HEADERS_CHECK is not set
1215CONFIG_DEBUG_KERNEL=y
1216# CONFIG_DEBUG_SHIRQ is not set
1217CONFIG_DETECT_SOFTLOCKUP=y
1218CONFIG_SCHED_DEBUG=y
1219# CONFIG_SCHEDSTATS is not set
1220CONFIG_TIMER_STATS=y
1221# CONFIG_DEBUG_SLAB is not set
1222CONFIG_DEBUG_PREEMPT=y
1223# CONFIG_DEBUG_RT_MUTEXES is not set
1224# CONFIG_RT_MUTEX_TESTER is not set
1225# CONFIG_DEBUG_SPINLOCK is not set
1226CONFIG_DEBUG_MUTEXES=y
1227# CONFIG_DEBUG_LOCK_ALLOC is not set
1228# CONFIG_PROVE_LOCKING is not set
1229# CONFIG_LOCK_STAT is not set
1230# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1231# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1232# CONFIG_DEBUG_KOBJECT is not set
1233# CONFIG_DEBUG_BUGVERBOSE is not set
1234# CONFIG_DEBUG_INFO is not set
1235# CONFIG_DEBUG_VM is not set
1236# CONFIG_DEBUG_LIST is not set
1237CONFIG_FRAME_POINTER=y
1238CONFIG_FORCED_INLINING=y
1239# CONFIG_RCU_TORTURE_TEST is not set
1240# CONFIG_FAULT_INJECTION is not set
1241# CONFIG_DEBUG_USER is not set
1242# CONFIG_DEBUG_ERRORS is not set
1243# CONFIG_DEBUG_LL is not set
1244
1245#
1246# Security options
1247#
1248# CONFIG_KEYS is not set
1249# CONFIG_SECURITY is not set
1250CONFIG_CRYPTO=y
1251CONFIG_CRYPTO_ALGAPI=y
1252CONFIG_CRYPTO_BLKCIPHER=y
1253CONFIG_CRYPTO_MANAGER=y
1254# CONFIG_CRYPTO_HMAC is not set
1255# CONFIG_CRYPTO_XCBC is not set
1256# CONFIG_CRYPTO_NULL is not set
1257# CONFIG_CRYPTO_MD4 is not set
1258CONFIG_CRYPTO_MD5=y
1259# CONFIG_CRYPTO_SHA1 is not set
1260# CONFIG_CRYPTO_SHA256 is not set
1261# CONFIG_CRYPTO_SHA512 is not set
1262# CONFIG_CRYPTO_WP512 is not set
1263# CONFIG_CRYPTO_TGR192 is not set
1264# CONFIG_CRYPTO_GF128MUL is not set
1265CONFIG_CRYPTO_ECB=m
1266CONFIG_CRYPTO_CBC=y
1267CONFIG_CRYPTO_PCBC=m
1268# CONFIG_CRYPTO_LRW is not set
1269# CONFIG_CRYPTO_CRYPTD is not set
1270CONFIG_CRYPTO_DES=y
1271# CONFIG_CRYPTO_FCRYPT is not set
1272# CONFIG_CRYPTO_BLOWFISH is not set
1273# CONFIG_CRYPTO_TWOFISH is not set
1274# CONFIG_CRYPTO_SERPENT is not set
1275# CONFIG_CRYPTO_AES is not set
1276# CONFIG_CRYPTO_CAST5 is not set
1277# CONFIG_CRYPTO_CAST6 is not set
1278# CONFIG_CRYPTO_TEA is not set
1279# CONFIG_CRYPTO_ARC4 is not set
1280# CONFIG_CRYPTO_KHAZAD is not set
1281# CONFIG_CRYPTO_ANUBIS is not set
1282# CONFIG_CRYPTO_DEFLATE is not set
1283# CONFIG_CRYPTO_MICHAEL_MIC is not set
1284# CONFIG_CRYPTO_CRC32C is not set
1285# CONFIG_CRYPTO_CAMELLIA is not set
1286# CONFIG_CRYPTO_TEST is not set
1287CONFIG_CRYPTO_HW=y
1288
1289#
1290# Library routines
1291#
1292CONFIG_BITREVERSE=y
1293CONFIG_CRC_CCITT=y
1294# CONFIG_CRC16 is not set
1295# CONFIG_CRC_ITU_T is not set
1296CONFIG_CRC32=y
1297# CONFIG_CRC7 is not set
1298CONFIG_LIBCRC32C=y
1299CONFIG_ZLIB_INFLATE=y
1300CONFIG_ZLIB_DEFLATE=y
1301CONFIG_PLIST=y
1302CONFIG_HAS_IOMEM=y
1303CONFIG_HAS_IOPORT=y
1304CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/omap_apollon_2420_defconfig b/arch/arm/configs/omap_apollon_2420_defconfig
new file mode 100644
index 000000000000..bb39dfc72d69
--- /dev/null
+++ b/arch/arm/configs/omap_apollon_2420_defconfig
@@ -0,0 +1,962 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.23-rc6-omap1
4# Tue Sep 18 12:07:29 2007
5#
6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8CONFIG_GENERIC_GPIO=y
9CONFIG_GENERIC_TIME=y
10CONFIG_GENERIC_CLOCKEVENTS=y
11CONFIG_MMU=y
12# CONFIG_NO_IOPORT is not set
13CONFIG_GENERIC_HARDIRQS=y
14CONFIG_STACKTRACE_SUPPORT=y
15CONFIG_LOCKDEP_SUPPORT=y
16CONFIG_TRACE_IRQFLAGS_SUPPORT=y
17CONFIG_HARDIRQS_SW_RESEND=y
18CONFIG_GENERIC_IRQ_PROBE=y
19CONFIG_RWSEM_GENERIC_SPINLOCK=y
20# CONFIG_ARCH_HAS_ILOG2_U32 is not set
21# CONFIG_ARCH_HAS_ILOG2_U64 is not set
22CONFIG_GENERIC_HWEIGHT=y
23CONFIG_GENERIC_CALIBRATE_DELAY=y
24CONFIG_ZONE_DMA=y
25CONFIG_VECTORS_BASE=0xffff0000
26CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
27
28#
29# General setup
30#
31CONFIG_EXPERIMENTAL=y
32CONFIG_BROKEN_ON_SMP=y
33CONFIG_LOCK_KERNEL=y
34CONFIG_INIT_ENV_ARG_LIMIT=32
35CONFIG_LOCALVERSION=""
36# CONFIG_LOCALVERSION_AUTO is not set
37CONFIG_SWAP=y
38CONFIG_SYSVIPC=y
39CONFIG_SYSVIPC_SYSCTL=y
40# CONFIG_POSIX_MQUEUE is not set
41CONFIG_BSD_PROCESS_ACCT=y
42# CONFIG_BSD_PROCESS_ACCT_V3 is not set
43# CONFIG_TASKSTATS is not set
44# CONFIG_USER_NS is not set
45# CONFIG_AUDIT is not set
46# CONFIG_IKCONFIG is not set
47CONFIG_LOG_BUF_SHIFT=14
48CONFIG_SYSFS_DEPRECATED=y
49# CONFIG_RELAY is not set
50# CONFIG_BLK_DEV_INITRD is not set
51CONFIG_CC_OPTIMIZE_FOR_SIZE=y
52CONFIG_SYSCTL=y
53# CONFIG_EMBEDDED is not set
54CONFIG_UID16=y
55CONFIG_SYSCTL_SYSCALL=y
56CONFIG_KALLSYMS=y
57# CONFIG_KALLSYMS_ALL is not set
58CONFIG_KALLSYMS_EXTRA_PASS=y
59CONFIG_HOTPLUG=y
60CONFIG_PRINTK=y
61CONFIG_BUG=y
62CONFIG_ELF_CORE=y
63CONFIG_BASE_FULL=y
64CONFIG_FUTEX=y
65CONFIG_ANON_INODES=y
66CONFIG_EPOLL=y
67CONFIG_SIGNALFD=y
68CONFIG_TIMERFD=y
69CONFIG_EVENTFD=y
70CONFIG_SHMEM=y
71CONFIG_VM_EVENT_COUNTERS=y
72CONFIG_SLAB=y
73# CONFIG_SLUB is not set
74# CONFIG_SLOB is not set
75CONFIG_RT_MUTEXES=y
76# CONFIG_TINY_SHMEM is not set
77CONFIG_BASE_SMALL=0
78CONFIG_MODULES=y
79CONFIG_MODULE_UNLOAD=y
80# CONFIG_MODULE_FORCE_UNLOAD is not set
81# CONFIG_MODVERSIONS is not set
82# CONFIG_MODULE_SRCVERSION_ALL is not set
83CONFIG_KMOD=y
84CONFIG_BLOCK=y
85# CONFIG_LBD is not set
86# CONFIG_BLK_DEV_IO_TRACE is not set
87# CONFIG_LSF is not set
88# CONFIG_BLK_DEV_BSG is not set
89
90#
91# IO Schedulers
92#
93CONFIG_IOSCHED_NOOP=y
94CONFIG_IOSCHED_AS=y
95CONFIG_IOSCHED_DEADLINE=y
96CONFIG_IOSCHED_CFQ=y
97# CONFIG_DEFAULT_AS is not set
98# CONFIG_DEFAULT_DEADLINE is not set
99CONFIG_DEFAULT_CFQ=y
100# CONFIG_DEFAULT_NOOP is not set
101CONFIG_DEFAULT_IOSCHED="cfq"
102
103#
104# System Type
105#
106# CONFIG_ARCH_AAEC2000 is not set
107# CONFIG_ARCH_INTEGRATOR is not set
108# CONFIG_ARCH_REALVIEW is not set
109# CONFIG_ARCH_VERSATILE is not set
110# CONFIG_ARCH_AT91 is not set
111# CONFIG_ARCH_CLPS7500 is not set
112# CONFIG_ARCH_CLPS711X is not set
113# CONFIG_ARCH_CO285 is not set
114# CONFIG_ARCH_EBSA110 is not set
115# CONFIG_ARCH_EP93XX is not set
116# CONFIG_ARCH_FOOTBRIDGE is not set
117# CONFIG_ARCH_NETX is not set
118# CONFIG_ARCH_H720X is not set
119# CONFIG_ARCH_IMX is not set
120# CONFIG_ARCH_IOP13XX is not set
121# CONFIG_ARCH_IOP32X is not set
122# CONFIG_ARCH_IOP33X is not set
123# CONFIG_ARCH_IXP23XX is not set
124# CONFIG_ARCH_IXP2000 is not set
125# CONFIG_ARCH_IXP4XX is not set
126# CONFIG_ARCH_L7200 is not set
127# CONFIG_ARCH_KS8695 is not set
128# CONFIG_ARCH_NS9XXX is not set
129# CONFIG_ARCH_MXC is not set
130# CONFIG_ARCH_PNX4008 is not set
131# CONFIG_ARCH_PXA is not set
132# CONFIG_ARCH_RPC is not set
133# CONFIG_ARCH_SA1100 is not set
134# CONFIG_ARCH_S3C2410 is not set
135# CONFIG_ARCH_SHARK is not set
136# CONFIG_ARCH_LH7A40X is not set
137# CONFIG_ARCH_DAVINCI is not set
138CONFIG_ARCH_OMAP=y
139
140#
141# TI OMAP Implementations
142#
143CONFIG_ARCH_OMAP_OTG=y
144# CONFIG_ARCH_OMAP1 is not set
145CONFIG_ARCH_OMAP2=y
146# CONFIG_ARCH_OMAP3 is not set
147
148#
149# OMAP Feature Selections
150#
151# CONFIG_OMAP_RESET_CLOCKS is not set
152# CONFIG_OMAP_BOOT_TAG is not set
153# CONFIG_OMAP_GPIO_SWITCH is not set
154CONFIG_OMAP_MUX=y
155# CONFIG_OMAP_MUX_DEBUG is not set
156CONFIG_OMAP_MUX_WARNINGS=y
157# CONFIG_OMAP_STI is not set
158# CONFIG_OMAP_MCBSP is not set
159# CONFIG_OMAP_MMU_FWK is not set
160# CONFIG_OMAP_MBOX_FWK is not set
161# CONFIG_OMAP_MPU_TIMER is not set
162CONFIG_OMAP_32K_TIMER=y
163CONFIG_OMAP_32K_TIMER_HZ=128
164CONFIG_OMAP_DM_TIMER=y
165CONFIG_OMAP_LL_DEBUG_UART1=y
166# CONFIG_OMAP_LL_DEBUG_UART2 is not set
167# CONFIG_OMAP_LL_DEBUG_UART3 is not set
168CONFIG_OMAP_SERIAL_WAKE=y
169# CONFIG_OMAP_DSP is not set
170# CONFIG_MACH_OMAP_GENERIC is not set
171
172#
173# OMAP Core Type
174#
175CONFIG_ARCH_OMAP24XX=y
176CONFIG_ARCH_OMAP2420=y
177# CONFIG_ARCH_OMAP2430 is not set
178
179#
180# OMAP Board Type
181#
182# CONFIG_MACH_NOKIA_N800 is not set
183# CONFIG_MACH_OMAP_H4 is not set
184CONFIG_MACH_OMAP_APOLLON=y
185# CONFIG_MACH_OMAP_APOLLON_PLUS is not set
186# CONFIG_MACH_OMAP_2430SDP is not set
187
188#
189# Boot options
190#
191
192#
193# Power management
194#
195
196#
197# Processor Type
198#
199CONFIG_CPU_32=y
200CONFIG_CPU_V6=y
201# CONFIG_CPU_32v6K is not set
202CONFIG_CPU_32v6=y
203CONFIG_CPU_ABRT_EV6=y
204CONFIG_CPU_PABRT_NOIFAR=y
205CONFIG_CPU_CACHE_V6=y
206CONFIG_CPU_CACHE_VIPT=y
207CONFIG_CPU_COPY_V6=y
208CONFIG_CPU_TLB_V6=y
209CONFIG_CPU_HAS_ASID=y
210CONFIG_CPU_CP15=y
211CONFIG_CPU_CP15_MMU=y
212
213#
214# Processor Features
215#
216# CONFIG_ARM_THUMB is not set
217# CONFIG_CPU_ICACHE_DISABLE is not set
218# CONFIG_CPU_DCACHE_DISABLE is not set
219# CONFIG_CPU_BPREDICT_DISABLE is not set
220# CONFIG_OUTER_CACHE is not set
221
222#
223# Bus support
224#
225# CONFIG_PCI_SYSCALL is not set
226# CONFIG_ARCH_SUPPORTS_MSI is not set
227
228#
229# PCCARD (PCMCIA/CardBus) support
230#
231# CONFIG_PCCARD is not set
232
233#
234# Kernel Features
235#
236# CONFIG_TICK_ONESHOT is not set
237# CONFIG_NO_HZ is not set
238# CONFIG_HIGH_RES_TIMERS is not set
239CONFIG_PREEMPT=y
240CONFIG_HZ=128
241# CONFIG_AEABI is not set
242# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
243CONFIG_SELECT_MEMORY_MODEL=y
244CONFIG_FLATMEM_MANUAL=y
245# CONFIG_DISCONTIGMEM_MANUAL is not set
246# CONFIG_SPARSEMEM_MANUAL is not set
247CONFIG_FLATMEM=y
248CONFIG_FLAT_NODE_MEM_MAP=y
249# CONFIG_SPARSEMEM_STATIC is not set
250CONFIG_SPLIT_PTLOCK_CPUS=4
251# CONFIG_RESOURCES_64BIT is not set
252CONFIG_ZONE_DMA_FLAG=1
253CONFIG_BOUNCE=y
254CONFIG_VIRT_TO_BUS=y
255# CONFIG_LEDS is not set
256CONFIG_ALIGNMENT_TRAP=y
257
258#
259# Boot options
260#
261CONFIG_ZBOOT_ROM_TEXT=0x0
262CONFIG_ZBOOT_ROM_BSS=0x0
263CONFIG_CMDLINE="root=/dev/ram0 rw mem=128M console=ttyS0,115200n8 initrd=0x80600000,8M ramdisk_size=8192"
264# CONFIG_XIP_KERNEL is not set
265# CONFIG_KEXEC is not set
266
267#
268# CPU Frequency scaling
269#
270# CONFIG_CPU_FREQ is not set
271
272#
273# Floating point emulation
274#
275
276#
277# At least one emulation must be selected
278#
279# CONFIG_FPE_NWFPE is not set
280# CONFIG_FPE_FASTFPE is not set
281CONFIG_VFP=y
282
283#
284# Userspace binary formats
285#
286CONFIG_BINFMT_ELF=y
287# CONFIG_BINFMT_AOUT is not set
288# CONFIG_BINFMT_MISC is not set
289# CONFIG_ARTHUR is not set
290
291#
292# Power management options
293#
294# CONFIG_PM is not set
295CONFIG_SUSPEND_UP_POSSIBLE=y
296
297#
298# Networking
299#
300CONFIG_NET=y
301
302#
303# Networking options
304#
305CONFIG_PACKET=y
306# CONFIG_PACKET_MMAP is not set
307CONFIG_UNIX=y
308CONFIG_XFRM=y
309# CONFIG_XFRM_USER is not set
310# CONFIG_XFRM_SUB_POLICY is not set
311# CONFIG_XFRM_MIGRATE is not set
312# CONFIG_NET_KEY is not set
313CONFIG_INET=y
314# CONFIG_IP_MULTICAST is not set
315# CONFIG_IP_ADVANCED_ROUTER is not set
316CONFIG_IP_FIB_HASH=y
317CONFIG_IP_PNP=y
318CONFIG_IP_PNP_DHCP=y
319CONFIG_IP_PNP_BOOTP=y
320# CONFIG_IP_PNP_RARP is not set
321# CONFIG_NET_IPIP is not set
322# CONFIG_NET_IPGRE is not set
323# CONFIG_ARPD is not set
324# CONFIG_SYN_COOKIES is not set
325# CONFIG_INET_AH is not set
326# CONFIG_INET_ESP is not set
327# CONFIG_INET_IPCOMP is not set
328# CONFIG_INET_XFRM_TUNNEL is not set
329# CONFIG_INET_TUNNEL is not set
330CONFIG_INET_XFRM_MODE_TRANSPORT=y
331CONFIG_INET_XFRM_MODE_TUNNEL=y
332CONFIG_INET_XFRM_MODE_BEET=y
333CONFIG_INET_DIAG=y
334CONFIG_INET_TCP_DIAG=y
335# CONFIG_TCP_CONG_ADVANCED is not set
336CONFIG_TCP_CONG_CUBIC=y
337CONFIG_DEFAULT_TCP_CONG="cubic"
338# CONFIG_TCP_MD5SIG is not set
339# CONFIG_IPV6 is not set
340# CONFIG_INET6_XFRM_TUNNEL is not set
341# CONFIG_INET6_TUNNEL is not set
342# CONFIG_NETWORK_SECMARK is not set
343# CONFIG_NETFILTER is not set
344# CONFIG_IP_DCCP is not set
345# CONFIG_IP_SCTP is not set
346# CONFIG_TIPC is not set
347# CONFIG_ATM is not set
348# CONFIG_BRIDGE is not set
349# CONFIG_VLAN_8021Q is not set
350# CONFIG_DECNET is not set
351# CONFIG_LLC2 is not set
352# CONFIG_IPX is not set
353# CONFIG_ATALK is not set
354# CONFIG_X25 is not set
355# CONFIG_LAPB is not set
356# CONFIG_ECONET is not set
357# CONFIG_WAN_ROUTER is not set
358
359#
360# QoS and/or fair queueing
361#
362# CONFIG_NET_SCHED is not set
363
364#
365# Network testing
366#
367# CONFIG_NET_PKTGEN is not set
368# CONFIG_HAMRADIO is not set
369# CONFIG_IRDA is not set
370# CONFIG_BT is not set
371# CONFIG_AF_RXRPC is not set
372
373#
374# Wireless
375#
376# CONFIG_CFG80211 is not set
377# CONFIG_WIRELESS_EXT is not set
378# CONFIG_MAC80211 is not set
379# CONFIG_IEEE80211 is not set
380# CONFIG_RFKILL is not set
381# CONFIG_NET_9P is not set
382
383#
384# Device Drivers
385#
386
387#
388# Generic Driver Options
389#
390CONFIG_STANDALONE=y
391CONFIG_PREVENT_FIRMWARE_BUILD=y
392# CONFIG_FW_LOADER is not set
393# CONFIG_DEBUG_DRIVER is not set
394# CONFIG_DEBUG_DEVRES is not set
395# CONFIG_SYS_HYPERVISOR is not set
396# CONFIG_CONNECTOR is not set
397CONFIG_MTD=y
398# CONFIG_MTD_DEBUG is not set
399CONFIG_MTD_CONCAT=y
400CONFIG_MTD_PARTITIONS=y
401# CONFIG_MTD_REDBOOT_PARTS is not set
402CONFIG_MTD_CMDLINE_PARTS=y
403# CONFIG_MTD_AFS_PARTS is not set
404
405#
406# User Modules And Translation Layers
407#
408CONFIG_MTD_CHAR=y
409CONFIG_MTD_BLKDEVS=y
410CONFIG_MTD_BLOCK=y
411# CONFIG_FTL is not set
412# CONFIG_NFTL is not set
413# CONFIG_INFTL is not set
414# CONFIG_RFD_FTL is not set
415# CONFIG_SSFDC is not set
416
417#
418# RAM/ROM/Flash chip drivers
419#
420# CONFIG_MTD_CFI is not set
421# CONFIG_MTD_JEDECPROBE is not set
422CONFIG_MTD_MAP_BANK_WIDTH_1=y
423CONFIG_MTD_MAP_BANK_WIDTH_2=y
424CONFIG_MTD_MAP_BANK_WIDTH_4=y
425# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
426# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
427# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
428CONFIG_MTD_CFI_I1=y
429CONFIG_MTD_CFI_I2=y
430# CONFIG_MTD_CFI_I4 is not set
431# CONFIG_MTD_CFI_I8 is not set
432# CONFIG_MTD_RAM is not set
433# CONFIG_MTD_ROM is not set
434# CONFIG_MTD_ABSENT is not set
435
436#
437# Mapping drivers for chip access
438#
439# CONFIG_MTD_COMPLEX_MAPPINGS is not set
440# CONFIG_MTD_PLATRAM is not set
441
442#
443# Self-contained MTD device drivers
444#
445# CONFIG_MTD_DATAFLASH is not set
446# CONFIG_MTD_M25P80 is not set
447# CONFIG_MTD_SLRAM is not set
448# CONFIG_MTD_PHRAM is not set
449# CONFIG_MTD_MTDRAM is not set
450# CONFIG_MTD_BLOCK2MTD is not set
451
452#
453# Disk-On-Chip Device Drivers
454#
455# CONFIG_MTD_DOC2000 is not set
456# CONFIG_MTD_DOC2001 is not set
457# CONFIG_MTD_DOC2001PLUS is not set
458# CONFIG_MTD_NAND is not set
459CONFIG_MTD_ONENAND=y
460# CONFIG_MTD_ONENAND_VERIFY_WRITE is not set
461CONFIG_MTD_ONENAND_GENERIC=y
462# CONFIG_MTD_ONENAND_OMAP2 is not set
463# CONFIG_MTD_ONENAND_OTP is not set
464
465#
466# UBI - Unsorted block images
467#
468# CONFIG_MTD_UBI is not set
469# CONFIG_PARPORT is not set
470CONFIG_BLK_DEV=y
471# CONFIG_BLK_DEV_COW_COMMON is not set
472CONFIG_BLK_DEV_LOOP=y
473# CONFIG_BLK_DEV_CRYPTOLOOP is not set
474# CONFIG_BLK_DEV_NBD is not set
475# CONFIG_BLK_DEV_RAM is not set
476# CONFIG_CDROM_PKTCDVD is not set
477# CONFIG_ATA_OVER_ETH is not set
478
479#
480# SCSI device support
481#
482# CONFIG_RAID_ATTRS is not set
483# CONFIG_SCSI is not set
484# CONFIG_SCSI_DMA is not set
485# CONFIG_SCSI_NETLINK is not set
486# CONFIG_ATA is not set
487# CONFIG_MD is not set
488CONFIG_NETDEVICES=y
489# CONFIG_NETDEVICES_MULTIQUEUE is not set
490# CONFIG_DUMMY is not set
491# CONFIG_BONDING is not set
492# CONFIG_MACVLAN is not set
493# CONFIG_EQUALIZER is not set
494# CONFIG_TUN is not set
495# CONFIG_PHYLIB is not set
496CONFIG_NET_ETHERNET=y
497CONFIG_MII=y
498# CONFIG_AX88796 is not set
499CONFIG_SMC91X=y
500# CONFIG_DM9000 is not set
501CONFIG_NETDEV_1000=y
502CONFIG_NETDEV_10000=y
503
504#
505# Wireless LAN
506#
507# CONFIG_WLAN_PRE80211 is not set
508# CONFIG_WLAN_80211 is not set
509# CONFIG_WAN is not set
510# CONFIG_PPP is not set
511# CONFIG_SLIP is not set
512# CONFIG_SHAPER is not set
513# CONFIG_NETCONSOLE is not set
514# CONFIG_NETPOLL is not set
515# CONFIG_NET_POLL_CONTROLLER is not set
516# CONFIG_ISDN is not set
517
518#
519# Input device support
520#
521CONFIG_INPUT=y
522# CONFIG_INPUT_FF_MEMLESS is not set
523# CONFIG_INPUT_POLLDEV is not set
524
525#
526# Userland interfaces
527#
528CONFIG_INPUT_MOUSEDEV=y
529# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
530CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
531CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
532# CONFIG_INPUT_JOYDEV is not set
533# CONFIG_INPUT_TSDEV is not set
534# CONFIG_INPUT_EVDEV is not set
535# CONFIG_INPUT_EVBUG is not set
536
537#
538# Input Device Drivers
539#
540# CONFIG_INPUT_KEYBOARD is not set
541# CONFIG_INPUT_MOUSE is not set
542# CONFIG_INPUT_JOYSTICK is not set
543# CONFIG_INPUT_TABLET is not set
544# CONFIG_INPUT_TOUCHSCREEN is not set
545# CONFIG_INPUT_MISC is not set
546
547#
548# Hardware I/O ports
549#
550# CONFIG_SERIO is not set
551# CONFIG_GAMEPORT is not set
552
553#
554# Character devices
555#
556CONFIG_VT=y
557CONFIG_VT_CONSOLE=y
558CONFIG_HW_CONSOLE=y
559# CONFIG_VT_HW_CONSOLE_BINDING is not set
560# CONFIG_SERIAL_NONSTANDARD is not set
561
562#
563# Serial drivers
564#
565CONFIG_SERIAL_8250=y
566CONFIG_SERIAL_8250_CONSOLE=y
567CONFIG_SERIAL_8250_NR_UARTS=32
568CONFIG_SERIAL_8250_RUNTIME_UARTS=4
569CONFIG_SERIAL_8250_EXTENDED=y
570CONFIG_SERIAL_8250_MANY_PORTS=y
571CONFIG_SERIAL_8250_SHARE_IRQ=y
572CONFIG_SERIAL_8250_DETECT_IRQ=y
573CONFIG_SERIAL_8250_RSA=y
574
575#
576# Non-8250 serial port support
577#
578CONFIG_SERIAL_CORE=y
579CONFIG_SERIAL_CORE_CONSOLE=y
580CONFIG_UNIX98_PTYS=y
581# CONFIG_LEGACY_PTYS is not set
582# CONFIG_IPMI_HANDLER is not set
583CONFIG_WATCHDOG=y
584# CONFIG_WATCHDOG_NOWAYOUT is not set
585
586#
587# Watchdog Device Drivers
588#
589# CONFIG_SOFT_WATCHDOG is not set
590CONFIG_OMAP_WATCHDOG=y
591CONFIG_HW_RANDOM=y
592CONFIG_HW_RANDOM_OMAP=y
593# CONFIG_NVRAM is not set
594# CONFIG_R3964 is not set
595# CONFIG_RAW_DRIVER is not set
596# CONFIG_TCG_TPM is not set
597# CONFIG_I2C is not set
598
599#
600# SPI support
601#
602CONFIG_SPI=y
603# CONFIG_SPI_DEBUG is not set
604CONFIG_SPI_MASTER=y
605
606#
607# SPI Master Controller Drivers
608#
609# CONFIG_SPI_BITBANG is not set
610CONFIG_SPI_OMAP24XX=y
611
612#
613# SPI Protocol Masters
614#
615# CONFIG_SPI_AT25 is not set
616# CONFIG_SPI_TSC2101 is not set
617# CONFIG_SPI_TSC2102 is not set
618# CONFIG_SPI_TSC210X is not set
619# CONFIG_SPI_TSC2301 is not set
620# CONFIG_SPI_SPIDEV is not set
621# CONFIG_SPI_TLE62X0 is not set
622# CONFIG_W1 is not set
623# CONFIG_HWMON is not set
624CONFIG_MISC_DEVICES=y
625# CONFIG_EEPROM_93CX6 is not set
626
627#
628# Multifunction device drivers
629#
630# CONFIG_MFD_SM501 is not set
631# CONFIG_NEW_LEDS is not set
632
633#
634# Multimedia devices
635#
636# CONFIG_VIDEO_DEV is not set
637# CONFIG_DVB_CORE is not set
638CONFIG_DAB=y
639
640#
641# Graphics support
642#
643# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
644
645#
646# Display device support
647#
648# CONFIG_DISPLAY_SUPPORT is not set
649# CONFIG_VGASTATE is not set
650CONFIG_VIDEO_OUTPUT_CONTROL=m
651CONFIG_FB=y
652CONFIG_FIRMWARE_EDID=y
653# CONFIG_FB_DDC is not set
654# CONFIG_FB_CFB_FILLRECT is not set
655# CONFIG_FB_CFB_COPYAREA is not set
656# CONFIG_FB_CFB_IMAGEBLIT is not set
657# CONFIG_FB_SYS_FILLRECT is not set
658# CONFIG_FB_SYS_COPYAREA is not set
659# CONFIG_FB_SYS_IMAGEBLIT is not set
660# CONFIG_FB_SYS_FOPS is not set
661CONFIG_FB_DEFERRED_IO=y
662# CONFIG_FB_SVGALIB is not set
663# CONFIG_FB_MACMODES is not set
664# CONFIG_FB_BACKLIGHT is not set
665# CONFIG_FB_MODE_HELPERS is not set
666# CONFIG_FB_TILEBLITTING is not set
667
668#
669# Frame buffer hardware drivers
670#
671# CONFIG_FB_S1D13XXX is not set
672CONFIG_FB_OMAP=y
673# CONFIG_FB_OMAP_LCDC_EXTERNAL is not set
674# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set
675CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=2
676# CONFIG_FB_VIRTUAL is not set
677
678#
679# Console display driver support
680#
681# CONFIG_VGA_CONSOLE is not set
682CONFIG_DUMMY_CONSOLE=y
683CONFIG_FRAMEBUFFER_CONSOLE=y
684# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
685# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
686CONFIG_FONTS=y
687CONFIG_FONT_8x8=y
688CONFIG_FONT_8x16=y
689# CONFIG_FONT_6x11 is not set
690# CONFIG_FONT_7x14 is not set
691# CONFIG_FONT_PEARL_8x8 is not set
692# CONFIG_FONT_ACORN_8x8 is not set
693# CONFIG_FONT_MINI_4x6 is not set
694# CONFIG_FONT_SUN8x16 is not set
695# CONFIG_FONT_SUN12x22 is not set
696# CONFIG_FONT_10x18 is not set
697CONFIG_LOGO=y
698# CONFIG_LOGO_LINUX_MONO is not set
699# CONFIG_LOGO_LINUX_VGA16 is not set
700CONFIG_LOGO_LINUX_CLUT224=y
701
702#
703# Sound
704#
705# CONFIG_SOUND is not set
706CONFIG_HID_SUPPORT=y
707# CONFIG_HID is not set
708CONFIG_USB_SUPPORT=y
709CONFIG_USB_ARCH_HAS_HCD=y
710CONFIG_USB_ARCH_HAS_OHCI=y
711# CONFIG_USB_ARCH_HAS_EHCI is not set
712# CONFIG_USB is not set
713# CONFIG_USB_MUSB_HDRC is not set
714# CONFIG_USB_GADGET_MUSB_HDRC is not set
715
716#
717# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
718#
719
720#
721# USB Gadget Support
722#
723CONFIG_USB_GADGET=y
724# CONFIG_USB_GADGET_DEBUG is not set
725# CONFIG_USB_GADGET_DEBUG_FILES is not set
726CONFIG_USB_GADGET_SELECTED=y
727# CONFIG_USB_GADGET_AMD5536UDC is not set
728# CONFIG_USB_GADGET_FSL_USB2 is not set
729# CONFIG_USB_GADGET_NET2280 is not set
730# CONFIG_USB_GADGET_PXA2XX is not set
731# CONFIG_USB_GADGET_M66592 is not set
732# CONFIG_USB_GADGET_GOKU is not set
733# CONFIG_USB_GADGET_LH7A40X is not set
734CONFIG_USB_GADGET_OMAP=y
735CONFIG_USB_OMAP=y
736# CONFIG_USB_GADGET_S3C2410 is not set
737# CONFIG_USB_GADGET_AT91 is not set
738# CONFIG_USB_GADGET_DUMMY_HCD is not set
739# CONFIG_USB_GADGET_DUALSPEED is not set
740# CONFIG_USB_ZERO is not set
741CONFIG_USB_ETH=m
742CONFIG_USB_ETH_RNDIS=y
743# CONFIG_USB_GADGETFS is not set
744CONFIG_USB_FILE_STORAGE=m
745# CONFIG_USB_FILE_STORAGE_TEST is not set
746# CONFIG_USB_G_SERIAL is not set
747# CONFIG_USB_MIDI_GADGET is not set
748CONFIG_MMC=y
749# CONFIG_MMC_DEBUG is not set
750# CONFIG_MMC_UNSAFE_RESUME is not set
751
752#
753# MMC/SD Card Drivers
754#
755CONFIG_MMC_BLOCK=y
756CONFIG_MMC_BLOCK_BOUNCE=y
757
758#
759# MMC/SD Host Controller Drivers
760#
761CONFIG_MMC_OMAP=y
762CONFIG_RTC_LIB=y
763# CONFIG_RTC_CLASS is not set
764
765#
766# DMA Engine support
767#
768# CONFIG_DMA_ENGINE is not set
769
770#
771# DMA Clients
772#
773
774#
775# DMA Devices
776#
777
778#
779# CBUS support
780#
781# CONFIG_CBUS is not set
782
783#
784# File systems
785#
786CONFIG_EXT2_FS=y
787# CONFIG_EXT2_FS_XATTR is not set
788# CONFIG_EXT2_FS_XIP is not set
789# CONFIG_EXT3_FS is not set
790# CONFIG_EXT4DEV_FS is not set
791# CONFIG_REISERFS_FS is not set
792# CONFIG_JFS_FS is not set
793# CONFIG_FS_POSIX_ACL is not set
794# CONFIG_XFS_FS is not set
795# CONFIG_GFS2_FS is not set
796# CONFIG_OCFS2_FS is not set
797# CONFIG_MINIX_FS is not set
798# CONFIG_ROMFS_FS is not set
799# CONFIG_INOTIFY is not set
800# CONFIG_QUOTA is not set
801CONFIG_DNOTIFY=y
802# CONFIG_AUTOFS_FS is not set
803CONFIG_AUTOFS4_FS=y
804# CONFIG_FUSE_FS is not set
805
806#
807# CD-ROM/DVD Filesystems
808#
809# CONFIG_ISO9660_FS is not set
810# CONFIG_UDF_FS is not set
811
812#
813# DOS/FAT/NT Filesystems
814#
815# CONFIG_MSDOS_FS is not set
816# CONFIG_VFAT_FS is not set
817# CONFIG_NTFS_FS is not set
818
819#
820# Pseudo filesystems
821#
822CONFIG_PROC_FS=y
823CONFIG_PROC_SYSCTL=y
824CONFIG_SYSFS=y
825CONFIG_TMPFS=y
826# CONFIG_TMPFS_POSIX_ACL is not set
827# CONFIG_HUGETLB_PAGE is not set
828CONFIG_RAMFS=y
829# CONFIG_CONFIGFS_FS is not set
830
831#
832# Miscellaneous filesystems
833#
834# CONFIG_ADFS_FS is not set
835# CONFIG_AFFS_FS is not set
836# CONFIG_HFS_FS is not set
837# CONFIG_HFSPLUS_FS is not set
838# CONFIG_BEFS_FS is not set
839# CONFIG_BFS_FS is not set
840# CONFIG_EFS_FS is not set
841CONFIG_JFFS2_FS=y
842CONFIG_JFFS2_FS_DEBUG=0
843CONFIG_JFFS2_FS_WRITEBUFFER=y
844# CONFIG_JFFS2_SUMMARY is not set
845# CONFIG_JFFS2_FS_XATTR is not set
846# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
847CONFIG_JFFS2_ZLIB=y
848CONFIG_JFFS2_RTIME=y
849# CONFIG_JFFS2_RUBIN is not set
850CONFIG_CRAMFS=y
851# CONFIG_VXFS_FS is not set
852# CONFIG_HPFS_FS is not set
853# CONFIG_QNX4FS_FS is not set
854# CONFIG_SYSV_FS is not set
855# CONFIG_UFS_FS is not set
856
857#
858# Network File Systems
859#
860CONFIG_NFS_FS=y
861CONFIG_NFS_V3=y
862# CONFIG_NFS_V3_ACL is not set
863# CONFIG_NFS_V4 is not set
864# CONFIG_NFS_DIRECTIO is not set
865# CONFIG_NFSD is not set
866CONFIG_ROOT_NFS=y
867CONFIG_LOCKD=y
868CONFIG_LOCKD_V4=y
869CONFIG_NFS_COMMON=y
870CONFIG_SUNRPC=y
871# CONFIG_SUNRPC_BIND34 is not set
872# CONFIG_RPCSEC_GSS_KRB5 is not set
873# CONFIG_RPCSEC_GSS_SPKM3 is not set
874# CONFIG_SMB_FS is not set
875# CONFIG_CIFS is not set
876# CONFIG_NCP_FS is not set
877# CONFIG_CODA_FS is not set
878# CONFIG_AFS_FS is not set
879
880#
881# Partition Types
882#
883# CONFIG_PARTITION_ADVANCED is not set
884CONFIG_MSDOS_PARTITION=y
885
886#
887# Native Language Support
888#
889# CONFIG_NLS is not set
890
891#
892# Distributed Lock Manager
893#
894# CONFIG_DLM is not set
895
896#
897# Profiling support
898#
899# CONFIG_PROFILING is not set
900
901#
902# Kernel hacking
903#
904# CONFIG_PRINTK_TIME is not set
905CONFIG_ENABLE_MUST_CHECK=y
906# CONFIG_MAGIC_SYSRQ is not set
907# CONFIG_UNUSED_SYMBOLS is not set
908# CONFIG_DEBUG_FS is not set
909# CONFIG_HEADERS_CHECK is not set
910CONFIG_DEBUG_KERNEL=y
911# CONFIG_DEBUG_SHIRQ is not set
912CONFIG_DETECT_SOFTLOCKUP=y
913CONFIG_SCHED_DEBUG=y
914# CONFIG_SCHEDSTATS is not set
915# CONFIG_TIMER_STATS is not set
916# CONFIG_DEBUG_SLAB is not set
917CONFIG_DEBUG_PREEMPT=y
918# CONFIG_DEBUG_RT_MUTEXES is not set
919# CONFIG_RT_MUTEX_TESTER is not set
920CONFIG_DEBUG_SPINLOCK=y
921CONFIG_DEBUG_MUTEXES=y
922# CONFIG_DEBUG_LOCK_ALLOC is not set
923# CONFIG_PROVE_LOCKING is not set
924# CONFIG_LOCK_STAT is not set
925CONFIG_DEBUG_SPINLOCK_SLEEP=y
926# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
927# CONFIG_DEBUG_KOBJECT is not set
928CONFIG_DEBUG_BUGVERBOSE=y
929# CONFIG_DEBUG_INFO is not set
930# CONFIG_DEBUG_VM is not set
931# CONFIG_DEBUG_LIST is not set
932CONFIG_FRAME_POINTER=y
933CONFIG_FORCED_INLINING=y
934# CONFIG_RCU_TORTURE_TEST is not set
935# CONFIG_FAULT_INJECTION is not set
936# CONFIG_DEBUG_USER is not set
937# CONFIG_DEBUG_ERRORS is not set
938# CONFIG_DEBUG_LL is not set
939
940#
941# Security options
942#
943# CONFIG_KEYS is not set
944# CONFIG_SECURITY is not set
945# CONFIG_CRYPTO is not set
946
947#
948# Library routines
949#
950CONFIG_BITREVERSE=y
951CONFIG_CRC_CCITT=y
952# CONFIG_CRC16 is not set
953# CONFIG_CRC_ITU_T is not set
954CONFIG_CRC32=y
955# CONFIG_CRC7 is not set
956CONFIG_LIBCRC32C=y
957CONFIG_ZLIB_INFLATE=y
958CONFIG_ZLIB_DEFLATE=y
959CONFIG_PLIST=y
960CONFIG_HAS_IOMEM=y
961CONFIG_HAS_IOPORT=y
962CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/omap_generic_1510_defconfig b/arch/arm/configs/omap_generic_1510_defconfig
new file mode 100644
index 000000000000..4b1c252f2091
--- /dev/null
+++ b/arch/arm/configs/omap_generic_1510_defconfig
@@ -0,0 +1,1172 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.23-rc6-omap1
4# Tue Sep 18 12:20:19 2007
5#
6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8CONFIG_GENERIC_GPIO=y
9CONFIG_GENERIC_TIME=y
10CONFIG_GENERIC_CLOCKEVENTS=y
11CONFIG_MMU=y
12# CONFIG_NO_IOPORT is not set
13CONFIG_GENERIC_HARDIRQS=y
14CONFIG_STACKTRACE_SUPPORT=y
15CONFIG_LOCKDEP_SUPPORT=y
16CONFIG_TRACE_IRQFLAGS_SUPPORT=y
17CONFIG_HARDIRQS_SW_RESEND=y
18CONFIG_GENERIC_IRQ_PROBE=y
19CONFIG_RWSEM_GENERIC_SPINLOCK=y
20# CONFIG_ARCH_HAS_ILOG2_U32 is not set
21# CONFIG_ARCH_HAS_ILOG2_U64 is not set
22CONFIG_GENERIC_HWEIGHT=y
23CONFIG_GENERIC_CALIBRATE_DELAY=y
24CONFIG_ZONE_DMA=y
25CONFIG_VECTORS_BASE=0xffff0000
26CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
27
28#
29# General setup
30#
31CONFIG_EXPERIMENTAL=y
32CONFIG_BROKEN_ON_SMP=y
33CONFIG_LOCK_KERNEL=y
34CONFIG_INIT_ENV_ARG_LIMIT=32
35CONFIG_LOCALVERSION=""
36CONFIG_LOCALVERSION_AUTO=y
37CONFIG_SWAP=y
38CONFIG_SYSVIPC=y
39CONFIG_SYSVIPC_SYSCTL=y
40# CONFIG_POSIX_MQUEUE is not set
41# CONFIG_BSD_PROCESS_ACCT is not set
42# CONFIG_TASKSTATS is not set
43# CONFIG_USER_NS is not set
44# CONFIG_AUDIT is not set
45# CONFIG_IKCONFIG is not set
46CONFIG_LOG_BUF_SHIFT=14
47CONFIG_SYSFS_DEPRECATED=y
48# CONFIG_RELAY is not set
49CONFIG_BLK_DEV_INITRD=y
50CONFIG_INITRAMFS_SOURCE=""
51CONFIG_CC_OPTIMIZE_FOR_SIZE=y
52CONFIG_SYSCTL=y
53# CONFIG_EMBEDDED is not set
54CONFIG_UID16=y
55CONFIG_SYSCTL_SYSCALL=y
56CONFIG_KALLSYMS=y
57# CONFIG_KALLSYMS_ALL is not set
58# CONFIG_KALLSYMS_EXTRA_PASS is not set
59CONFIG_HOTPLUG=y
60CONFIG_PRINTK=y
61CONFIG_BUG=y
62CONFIG_ELF_CORE=y
63CONFIG_BASE_FULL=y
64CONFIG_FUTEX=y
65CONFIG_ANON_INODES=y
66CONFIG_EPOLL=y
67CONFIG_SIGNALFD=y
68CONFIG_TIMERFD=y
69CONFIG_EVENTFD=y
70CONFIG_SHMEM=y
71CONFIG_VM_EVENT_COUNTERS=y
72CONFIG_SLAB=y
73# CONFIG_SLUB is not set
74# CONFIG_SLOB is not set
75CONFIG_RT_MUTEXES=y
76# CONFIG_TINY_SHMEM is not set
77CONFIG_BASE_SMALL=0
78CONFIG_MODULES=y
79CONFIG_MODULE_UNLOAD=y
80CONFIG_MODULE_FORCE_UNLOAD=y
81# CONFIG_MODVERSIONS is not set
82# CONFIG_MODULE_SRCVERSION_ALL is not set
83CONFIG_KMOD=y
84CONFIG_BLOCK=y
85# CONFIG_LBD is not set
86# CONFIG_BLK_DEV_IO_TRACE is not set
87# CONFIG_LSF is not set
88# CONFIG_BLK_DEV_BSG is not set
89
90#
91# IO Schedulers
92#
93CONFIG_IOSCHED_NOOP=y
94CONFIG_IOSCHED_AS=y
95CONFIG_IOSCHED_DEADLINE=y
96CONFIG_IOSCHED_CFQ=y
97# CONFIG_DEFAULT_AS is not set
98# CONFIG_DEFAULT_DEADLINE is not set
99CONFIG_DEFAULT_CFQ=y
100# CONFIG_DEFAULT_NOOP is not set
101CONFIG_DEFAULT_IOSCHED="cfq"
102
103#
104# System Type
105#
106# CONFIG_ARCH_AAEC2000 is not set
107# CONFIG_ARCH_INTEGRATOR is not set
108# CONFIG_ARCH_REALVIEW is not set
109# CONFIG_ARCH_VERSATILE is not set
110# CONFIG_ARCH_AT91 is not set
111# CONFIG_ARCH_CLPS7500 is not set
112# CONFIG_ARCH_CLPS711X is not set
113# CONFIG_ARCH_CO285 is not set
114# CONFIG_ARCH_EBSA110 is not set
115# CONFIG_ARCH_EP93XX is not set
116# CONFIG_ARCH_FOOTBRIDGE is not set
117# CONFIG_ARCH_NETX is not set
118# CONFIG_ARCH_H720X is not set
119# CONFIG_ARCH_IMX is not set
120# CONFIG_ARCH_IOP13XX is not set
121# CONFIG_ARCH_IOP32X is not set
122# CONFIG_ARCH_IOP33X is not set
123# CONFIG_ARCH_IXP23XX is not set
124# CONFIG_ARCH_IXP2000 is not set
125# CONFIG_ARCH_IXP4XX is not set
126# CONFIG_ARCH_L7200 is not set
127# CONFIG_ARCH_KS8695 is not set
128# CONFIG_ARCH_NS9XXX is not set
129# CONFIG_ARCH_MXC is not set
130# CONFIG_ARCH_PNX4008 is not set
131# CONFIG_ARCH_PXA is not set
132# CONFIG_ARCH_RPC is not set
133# CONFIG_ARCH_SA1100 is not set
134# CONFIG_ARCH_S3C2410 is not set
135# CONFIG_ARCH_SHARK is not set
136# CONFIG_ARCH_LH7A40X is not set
137# CONFIG_ARCH_DAVINCI is not set
138CONFIG_ARCH_OMAP=y
139
140#
141# TI OMAP Implementations
142#
143CONFIG_ARCH_OMAP1=y
144# CONFIG_ARCH_OMAP2 is not set
145# CONFIG_ARCH_OMAP3 is not set
146
147#
148# OMAP Feature Selections
149#
150# CONFIG_OMAP_RESET_CLOCKS is not set
151# CONFIG_OMAP_BOOT_TAG is not set
152# CONFIG_OMAP_GPIO_SWITCH is not set
153CONFIG_OMAP_MUX=y
154# CONFIG_OMAP_MUX_DEBUG is not set
155CONFIG_OMAP_MUX_WARNINGS=y
156CONFIG_OMAP_MCBSP=y
157# CONFIG_OMAP_MMU_FWK is not set
158# CONFIG_OMAP_MBOX_FWK is not set
159CONFIG_OMAP_MPU_TIMER=y
160# CONFIG_OMAP_32K_TIMER is not set
161CONFIG_OMAP_LL_DEBUG_UART1=y
162# CONFIG_OMAP_LL_DEBUG_UART2 is not set
163# CONFIG_OMAP_LL_DEBUG_UART3 is not set
164CONFIG_OMAP_SERIAL_WAKE=y
165# CONFIG_OMAP_DSP is not set
166
167#
168# OMAP Core Type
169#
170# CONFIG_ARCH_OMAP730 is not set
171CONFIG_ARCH_OMAP15XX=y
172# CONFIG_ARCH_OMAP16XX is not set
173
174#
175# OMAP Board Type
176#
177# CONFIG_MACH_OMAP_INNOVATOR is not set
178# CONFIG_MACH_VOICEBLUE is not set
179# CONFIG_MACH_OMAP_PALMTE is not set
180# CONFIG_MACH_OMAP_PALMZ71 is not set
181# CONFIG_MACH_OMAP_PALMTT is not set
182# CONFIG_MACH_SX1 is not set
183# CONFIG_MACH_AMS_DELTA is not set
184CONFIG_MACH_OMAP_GENERIC=y
185
186#
187# OMAP CPU Speed
188#
189# CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER is not set
190CONFIG_OMAP_ARM_168MHZ=y
191# CONFIG_OMAP_ARM_150MHZ is not set
192# CONFIG_OMAP_ARM_120MHZ is not set
193# CONFIG_OMAP_ARM_60MHZ is not set
194# CONFIG_OMAP_ARM_30MHZ is not set
195# CONFIG_MACH_OMAP_APOLLON_PLUS is not set
196
197#
198# Boot options
199#
200
201#
202# Power management
203#
204
205#
206# Processor Type
207#
208CONFIG_CPU_32=y
209CONFIG_CPU_ARM925T=y
210CONFIG_CPU_32v4T=y
211CONFIG_CPU_ABRT_EV4T=y
212CONFIG_CPU_PABRT_NOIFAR=y
213CONFIG_CPU_CACHE_V4WT=y
214CONFIG_CPU_CACHE_VIVT=y
215CONFIG_CPU_COPY_V4WB=y
216CONFIG_CPU_TLB_V4WBI=y
217CONFIG_CPU_CP15=y
218CONFIG_CPU_CP15_MMU=y
219
220#
221# Processor Features
222#
223# CONFIG_ARM_THUMB is not set
224# CONFIG_CPU_ICACHE_DISABLE is not set
225# CONFIG_CPU_DCACHE_DISABLE is not set
226CONFIG_CPU_DCACHE_WRITETHROUGH=y
227# CONFIG_OUTER_CACHE is not set
228
229#
230# Bus support
231#
232# CONFIG_PCI_SYSCALL is not set
233# CONFIG_ARCH_SUPPORTS_MSI is not set
234
235#
236# PCCARD (PCMCIA/CardBus) support
237#
238# CONFIG_PCCARD is not set
239
240#
241# Kernel Features
242#
243# CONFIG_TICK_ONESHOT is not set
244# CONFIG_NO_HZ is not set
245# CONFIG_HIGH_RES_TIMERS is not set
246CONFIG_PREEMPT=y
247CONFIG_HZ=100
248# CONFIG_AEABI is not set
249# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
250CONFIG_SELECT_MEMORY_MODEL=y
251CONFIG_FLATMEM_MANUAL=y
252# CONFIG_DISCONTIGMEM_MANUAL is not set
253# CONFIG_SPARSEMEM_MANUAL is not set
254CONFIG_FLATMEM=y
255CONFIG_FLAT_NODE_MEM_MAP=y
256# CONFIG_SPARSEMEM_STATIC is not set
257CONFIG_SPLIT_PTLOCK_CPUS=4096
258# CONFIG_RESOURCES_64BIT is not set
259CONFIG_ZONE_DMA_FLAG=1
260CONFIG_BOUNCE=y
261CONFIG_VIRT_TO_BUS=y
262# CONFIG_LEDS is not set
263CONFIG_ALIGNMENT_TRAP=y
264
265#
266# Boot options
267#
268CONFIG_ZBOOT_ROM_TEXT=0x0
269CONFIG_ZBOOT_ROM_BSS=0x0
270CONFIG_CMDLINE="mem=64M console=ttyS2,115200 root=0803 ro init=/bin/sh"
271# CONFIG_XIP_KERNEL is not set
272# CONFIG_KEXEC is not set
273
274#
275# CPU Frequency scaling
276#
277# CONFIG_CPU_FREQ is not set
278
279#
280# Floating point emulation
281#
282
283#
284# At least one emulation must be selected
285#
286CONFIG_FPE_NWFPE=y
287# CONFIG_FPE_NWFPE_XP is not set
288# CONFIG_FPE_FASTFPE is not set
289
290#
291# Userspace binary formats
292#
293CONFIG_BINFMT_ELF=y
294# CONFIG_BINFMT_AOUT is not set
295# CONFIG_BINFMT_MISC is not set
296# CONFIG_ARTHUR is not set
297
298#
299# Power management options
300#
301CONFIG_PM=y
302# CONFIG_PM_LEGACY is not set
303# CONFIG_PM_DEBUG is not set
304CONFIG_PM_SLEEP=y
305CONFIG_SUSPEND_UP_POSSIBLE=y
306CONFIG_SUSPEND=y
307# CONFIG_APM_EMULATION is not set
308
309#
310# Networking
311#
312CONFIG_NET=y
313
314#
315# Networking options
316#
317CONFIG_PACKET=y
318# CONFIG_PACKET_MMAP is not set
319CONFIG_UNIX=y
320CONFIG_XFRM=y
321# CONFIG_XFRM_USER is not set
322# CONFIG_XFRM_SUB_POLICY is not set
323# CONFIG_XFRM_MIGRATE is not set
324# CONFIG_NET_KEY is not set
325CONFIG_INET=y
326CONFIG_IP_MULTICAST=y
327# CONFIG_IP_ADVANCED_ROUTER is not set
328CONFIG_IP_FIB_HASH=y
329CONFIG_IP_PNP=y
330CONFIG_IP_PNP_DHCP=y
331CONFIG_IP_PNP_BOOTP=y
332# CONFIG_IP_PNP_RARP is not set
333# CONFIG_NET_IPIP is not set
334# CONFIG_NET_IPGRE is not set
335# CONFIG_IP_MROUTE is not set
336# CONFIG_ARPD is not set
337# CONFIG_SYN_COOKIES is not set
338# CONFIG_INET_AH is not set
339# CONFIG_INET_ESP is not set
340# CONFIG_INET_IPCOMP is not set
341# CONFIG_INET_XFRM_TUNNEL is not set
342# CONFIG_INET_TUNNEL is not set
343CONFIG_INET_XFRM_MODE_TRANSPORT=y
344CONFIG_INET_XFRM_MODE_TUNNEL=y
345CONFIG_INET_XFRM_MODE_BEET=y
346CONFIG_INET_DIAG=y
347CONFIG_INET_TCP_DIAG=y
348# CONFIG_TCP_CONG_ADVANCED is not set
349CONFIG_TCP_CONG_CUBIC=y
350CONFIG_DEFAULT_TCP_CONG="cubic"
351# CONFIG_TCP_MD5SIG is not set
352# CONFIG_IPV6 is not set
353# CONFIG_INET6_XFRM_TUNNEL is not set
354# CONFIG_INET6_TUNNEL is not set
355# CONFIG_NETWORK_SECMARK is not set
356# CONFIG_NETFILTER is not set
357# CONFIG_IP_DCCP is not set
358# CONFIG_IP_SCTP is not set
359# CONFIG_TIPC is not set
360# CONFIG_ATM is not set
361# CONFIG_BRIDGE is not set
362# CONFIG_VLAN_8021Q is not set
363# CONFIG_DECNET is not set
364# CONFIG_LLC2 is not set
365# CONFIG_IPX is not set
366# CONFIG_ATALK is not set
367# CONFIG_X25 is not set
368# CONFIG_LAPB is not set
369# CONFIG_ECONET is not set
370# CONFIG_WAN_ROUTER is not set
371
372#
373# QoS and/or fair queueing
374#
375# CONFIG_NET_SCHED is not set
376
377#
378# Network testing
379#
380# CONFIG_NET_PKTGEN is not set
381# CONFIG_HAMRADIO is not set
382# CONFIG_IRDA is not set
383# CONFIG_BT is not set
384# CONFIG_AF_RXRPC is not set
385
386#
387# Wireless
388#
389# CONFIG_CFG80211 is not set
390# CONFIG_WIRELESS_EXT is not set
391# CONFIG_MAC80211 is not set
392# CONFIG_IEEE80211 is not set
393# CONFIG_RFKILL is not set
394# CONFIG_NET_9P is not set
395
396#
397# Device Drivers
398#
399
400#
401# Generic Driver Options
402#
403CONFIG_STANDALONE=y
404CONFIG_PREVENT_FIRMWARE_BUILD=y
405# CONFIG_FW_LOADER is not set
406# CONFIG_DEBUG_DRIVER is not set
407# CONFIG_DEBUG_DEVRES is not set
408# CONFIG_SYS_HYPERVISOR is not set
409# CONFIG_CONNECTOR is not set
410# CONFIG_MTD is not set
411# CONFIG_PARPORT is not set
412CONFIG_BLK_DEV=y
413# CONFIG_BLK_DEV_COW_COMMON is not set
414CONFIG_BLK_DEV_LOOP=y
415# CONFIG_BLK_DEV_CRYPTOLOOP is not set
416# CONFIG_BLK_DEV_NBD is not set
417# CONFIG_BLK_DEV_UB is not set
418CONFIG_BLK_DEV_RAM=y
419CONFIG_BLK_DEV_RAM_COUNT=16
420CONFIG_BLK_DEV_RAM_SIZE=8192
421CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
422# CONFIG_CDROM_PKTCDVD is not set
423# CONFIG_ATA_OVER_ETH is not set
424
425#
426# SCSI device support
427#
428# CONFIG_RAID_ATTRS is not set
429CONFIG_SCSI=y
430CONFIG_SCSI_DMA=y
431# CONFIG_SCSI_TGT is not set
432# CONFIG_SCSI_NETLINK is not set
433CONFIG_SCSI_PROC_FS=y
434
435#
436# SCSI support type (disk, tape, CD-ROM)
437#
438CONFIG_BLK_DEV_SD=y
439# CONFIG_CHR_DEV_ST is not set
440# CONFIG_CHR_DEV_OSST is not set
441CONFIG_BLK_DEV_SR=y
442# CONFIG_BLK_DEV_SR_VENDOR is not set
443CONFIG_CHR_DEV_SG=y
444# CONFIG_CHR_DEV_SCH is not set
445
446#
447# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
448#
449CONFIG_SCSI_MULTI_LUN=y
450# CONFIG_SCSI_CONSTANTS is not set
451# CONFIG_SCSI_LOGGING is not set
452# CONFIG_SCSI_SCAN_ASYNC is not set
453CONFIG_SCSI_WAIT_SCAN=m
454
455#
456# SCSI Transports
457#
458# CONFIG_SCSI_SPI_ATTRS is not set
459# CONFIG_SCSI_FC_ATTRS is not set
460# CONFIG_SCSI_ISCSI_ATTRS is not set
461# CONFIG_SCSI_SAS_LIBSAS is not set
462CONFIG_SCSI_LOWLEVEL=y
463# CONFIG_ISCSI_TCP is not set
464# CONFIG_SCSI_DEBUG is not set
465# CONFIG_ATA is not set
466# CONFIG_MD is not set
467CONFIG_NETDEVICES=y
468# CONFIG_NETDEVICES_MULTIQUEUE is not set
469# CONFIG_DUMMY is not set
470# CONFIG_BONDING is not set
471# CONFIG_MACVLAN is not set
472# CONFIG_EQUALIZER is not set
473# CONFIG_TUN is not set
474# CONFIG_PHYLIB is not set
475CONFIG_NET_ETHERNET=y
476CONFIG_MII=y
477# CONFIG_AX88796 is not set
478# CONFIG_SMC91X is not set
479# CONFIG_DM9000 is not set
480CONFIG_NETDEV_1000=y
481CONFIG_NETDEV_10000=y
482
483#
484# Wireless LAN
485#
486# CONFIG_WLAN_PRE80211 is not set
487# CONFIG_WLAN_80211 is not set
488
489#
490# USB Network Adapters
491#
492# CONFIG_USB_CATC is not set
493# CONFIG_USB_KAWETH is not set
494# CONFIG_USB_PEGASUS is not set
495CONFIG_USB_RTL8150=y
496CONFIG_USB_USBNET_MII=y
497CONFIG_USB_USBNET=y
498CONFIG_USB_NET_AX8817X=y
499CONFIG_USB_NET_CDCETHER=y
500# CONFIG_USB_NET_DM9601 is not set
501# CONFIG_USB_NET_GL620A is not set
502CONFIG_USB_NET_NET1080=y
503# CONFIG_USB_NET_PLUSB is not set
504# CONFIG_USB_NET_MCS7830 is not set
505# CONFIG_USB_NET_RNDIS_HOST is not set
506CONFIG_USB_NET_CDC_SUBSET=y
507# CONFIG_USB_ALI_M5632 is not set
508CONFIG_USB_AN2720=y
509CONFIG_USB_BELKIN=y
510CONFIG_USB_ARMLINUX=y
511CONFIG_USB_EPSON2888=y
512# CONFIG_USB_KC2190 is not set
513CONFIG_USB_NET_ZAURUS=y
514# CONFIG_WAN is not set
515CONFIG_PPP=y
516CONFIG_PPP_MULTILINK=y
517# CONFIG_PPP_FILTER is not set
518# CONFIG_PPP_ASYNC is not set
519# CONFIG_PPP_SYNC_TTY is not set
520# CONFIG_PPP_DEFLATE is not set
521# CONFIG_PPP_BSDCOMP is not set
522# CONFIG_PPP_MPPE is not set
523# CONFIG_PPPOE is not set
524# CONFIG_PPPOL2TP is not set
525# CONFIG_SLIP is not set
526CONFIG_SLHC=y
527# CONFIG_SHAPER is not set
528# CONFIG_NETCONSOLE is not set
529# CONFIG_NETPOLL is not set
530# CONFIG_NET_POLL_CONTROLLER is not set
531# CONFIG_ISDN is not set
532
533#
534# Input device support
535#
536CONFIG_INPUT=y
537# CONFIG_INPUT_FF_MEMLESS is not set
538# CONFIG_INPUT_POLLDEV is not set
539
540#
541# Userland interfaces
542#
543CONFIG_INPUT_MOUSEDEV=y
544CONFIG_INPUT_MOUSEDEV_PSAUX=y
545CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
546CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
547# CONFIG_INPUT_JOYDEV is not set
548# CONFIG_INPUT_TSDEV is not set
549# CONFIG_INPUT_EVDEV is not set
550# CONFIG_INPUT_EVBUG is not set
551
552#
553# Input Device Drivers
554#
555CONFIG_INPUT_KEYBOARD=y
556CONFIG_KEYBOARD_ATKBD=y
557# CONFIG_KEYBOARD_SUNKBD is not set
558# CONFIG_KEYBOARD_LKKBD is not set
559# CONFIG_KEYBOARD_XTKBD is not set
560# CONFIG_KEYBOARD_NEWTON is not set
561# CONFIG_KEYBOARD_STOWAWAY is not set
562CONFIG_KEYBOARD_OMAP=y
563# CONFIG_KEYBOARD_GPIO is not set
564# CONFIG_INPUT_MOUSE is not set
565# CONFIG_INPUT_JOYSTICK is not set
566# CONFIG_INPUT_TABLET is not set
567# CONFIG_INPUT_TOUCHSCREEN is not set
568# CONFIG_INPUT_MISC is not set
569
570#
571# Hardware I/O ports
572#
573CONFIG_SERIO=y
574CONFIG_SERIO_SERPORT=y
575CONFIG_SERIO_LIBPS2=y
576# CONFIG_SERIO_RAW is not set
577# CONFIG_GAMEPORT is not set
578
579#
580# Character devices
581#
582CONFIG_VT=y
583CONFIG_VT_CONSOLE=y
584CONFIG_HW_CONSOLE=y
585# CONFIG_VT_HW_CONSOLE_BINDING is not set
586# CONFIG_SERIAL_NONSTANDARD is not set
587
588#
589# Serial drivers
590#
591CONFIG_SERIAL_8250=y
592CONFIG_SERIAL_8250_CONSOLE=y
593CONFIG_SERIAL_8250_NR_UARTS=4
594CONFIG_SERIAL_8250_RUNTIME_UARTS=4
595# CONFIG_SERIAL_8250_EXTENDED is not set
596
597#
598# Non-8250 serial port support
599#
600CONFIG_SERIAL_CORE=y
601CONFIG_SERIAL_CORE_CONSOLE=y
602CONFIG_UNIX98_PTYS=y
603# CONFIG_LEGACY_PTYS is not set
604# CONFIG_IPMI_HANDLER is not set
605# CONFIG_WATCHDOG is not set
606CONFIG_HW_RANDOM=m
607# CONFIG_NVRAM is not set
608# CONFIG_R3964 is not set
609# CONFIG_RAW_DRIVER is not set
610# CONFIG_TCG_TPM is not set
611CONFIG_I2C=y
612CONFIG_I2C_BOARDINFO=y
613CONFIG_I2C_CHARDEV=y
614
615#
616# I2C Algorithms
617#
618CONFIG_I2C_ALGOBIT=y
619# CONFIG_I2C_ALGOPCF is not set
620# CONFIG_I2C_ALGOPCA is not set
621
622#
623# I2C Hardware Bus support
624#
625# CONFIG_I2C_GPIO is not set
626# CONFIG_I2C_OCORES is not set
627# CONFIG_I2C_OMAP is not set
628# CONFIG_I2C_PARPORT_LIGHT is not set
629# CONFIG_I2C_SIMTEC is not set
630# CONFIG_I2C_TAOS_EVM is not set
631# CONFIG_I2C_STUB is not set
632# CONFIG_I2C_TINY_USB is not set
633
634#
635# Miscellaneous I2C Chip support
636#
637# CONFIG_SENSORS_DS1337 is not set
638# CONFIG_SENSORS_DS1374 is not set
639# CONFIG_DS1682 is not set
640# CONFIG_SENSORS_EEPROM is not set
641# CONFIG_SENSORS_PCF8574 is not set
642# CONFIG_SENSORS_PCA9539 is not set
643# CONFIG_SENSORS_PCF8591 is not set
644# CONFIG_TPS65010 is not set
645# CONFIG_SENSORS_MAX6875 is not set
646# CONFIG_SENSORS_TSL2550 is not set
647# CONFIG_I2C_DEBUG_CORE is not set
648# CONFIG_I2C_DEBUG_ALGO is not set
649# CONFIG_I2C_DEBUG_BUS is not set
650# CONFIG_I2C_DEBUG_CHIP is not set
651
652#
653# SPI support
654#
655# CONFIG_SPI is not set
656# CONFIG_SPI_MASTER is not set
657# CONFIG_W1 is not set
658CONFIG_HWMON=y
659# CONFIG_HWMON_VID is not set
660# CONFIG_SENSORS_ABITUGURU is not set
661# CONFIG_SENSORS_ABITUGURU3 is not set
662# CONFIG_SENSORS_AD7418 is not set
663# CONFIG_SENSORS_ADM1021 is not set
664# CONFIG_SENSORS_ADM1025 is not set
665# CONFIG_SENSORS_ADM1026 is not set
666# CONFIG_SENSORS_ADM1029 is not set
667# CONFIG_SENSORS_ADM1031 is not set
668# CONFIG_SENSORS_ADM9240 is not set
669# CONFIG_SENSORS_ASB100 is not set
670# CONFIG_SENSORS_ATXP1 is not set
671# CONFIG_SENSORS_DS1621 is not set
672# CONFIG_SENSORS_F71805F is not set
673# CONFIG_SENSORS_FSCHER is not set
674# CONFIG_SENSORS_FSCPOS is not set
675# CONFIG_SENSORS_GL518SM is not set
676# CONFIG_SENSORS_GL520SM is not set
677# CONFIG_SENSORS_IT87 is not set
678# CONFIG_SENSORS_LM63 is not set
679# CONFIG_SENSORS_LM75 is not set
680# CONFIG_SENSORS_LM77 is not set
681# CONFIG_SENSORS_LM78 is not set
682# CONFIG_SENSORS_LM80 is not set
683# CONFIG_SENSORS_LM83 is not set
684# CONFIG_SENSORS_LM85 is not set
685# CONFIG_SENSORS_LM87 is not set
686# CONFIG_SENSORS_LM90 is not set
687# CONFIG_SENSORS_LM92 is not set
688# CONFIG_SENSORS_LM93 is not set
689# CONFIG_SENSORS_MAX1619 is not set
690# CONFIG_SENSORS_MAX6650 is not set
691# CONFIG_SENSORS_PC87360 is not set
692# CONFIG_SENSORS_PC87427 is not set
693# CONFIG_SENSORS_DME1737 is not set
694# CONFIG_SENSORS_SMSC47M1 is not set
695# CONFIG_SENSORS_SMSC47M192 is not set
696# CONFIG_SENSORS_SMSC47B397 is not set
697# CONFIG_SENSORS_THMC50 is not set
698# CONFIG_SENSORS_VT1211 is not set
699# CONFIG_SENSORS_W83781D is not set
700# CONFIG_SENSORS_W83791D is not set
701# CONFIG_SENSORS_W83792D is not set
702# CONFIG_SENSORS_W83793 is not set
703# CONFIG_SENSORS_W83L785TS is not set
704# CONFIG_SENSORS_W83627HF is not set
705# CONFIG_SENSORS_W83627EHF is not set
706# CONFIG_HWMON_DEBUG_CHIP is not set
707CONFIG_MISC_DEVICES=y
708# CONFIG_EEPROM_93CX6 is not set
709
710#
711# Multifunction device drivers
712#
713# CONFIG_MFD_SM501 is not set
714# CONFIG_NEW_LEDS is not set
715
716#
717# Multimedia devices
718#
719# CONFIG_VIDEO_DEV is not set
720# CONFIG_DVB_CORE is not set
721CONFIG_DAB=y
722# CONFIG_USB_DABUSB is not set
723
724#
725# Graphics support
726#
727# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
728
729#
730# Display device support
731#
732# CONFIG_DISPLAY_SUPPORT is not set
733# CONFIG_VGASTATE is not set
734CONFIG_VIDEO_OUTPUT_CONTROL=m
735# CONFIG_FB is not set
736
737#
738# Console display driver support
739#
740# CONFIG_VGA_CONSOLE is not set
741CONFIG_DUMMY_CONSOLE=y
742
743#
744# Sound
745#
746# CONFIG_SOUND is not set
747CONFIG_HID_SUPPORT=y
748CONFIG_HID=y
749# CONFIG_HID_DEBUG is not set
750
751#
752# USB Input Devices
753#
754CONFIG_USB_HID=y
755# CONFIG_USB_HIDINPUT_POWERBOOK is not set
756# CONFIG_HID_FF is not set
757# CONFIG_USB_HIDDEV is not set
758CONFIG_USB_SUPPORT=y
759CONFIG_USB_ARCH_HAS_HCD=y
760CONFIG_USB_ARCH_HAS_OHCI=y
761# CONFIG_USB_ARCH_HAS_EHCI is not set
762CONFIG_USB=y
763CONFIG_USB_DEBUG=y
764
765#
766# Miscellaneous USB options
767#
768CONFIG_USB_DEVICEFS=y
769# CONFIG_USB_DEVICE_CLASS is not set
770# CONFIG_USB_DYNAMIC_MINORS is not set
771# CONFIG_USB_SUSPEND is not set
772# CONFIG_USB_PERSIST is not set
773# CONFIG_USB_OTG is not set
774
775#
776# USB Host Controller Drivers
777#
778# CONFIG_USB_ISP116X_HCD is not set
779CONFIG_USB_OHCI_HCD=y
780# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
781# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
782CONFIG_USB_OHCI_LITTLE_ENDIAN=y
783# CONFIG_USB_SL811_HCD is not set
784# CONFIG_USB_R8A66597_HCD is not set
785# CONFIG_USB_MUSB_HDRC is not set
786
787#
788# USB Device Class drivers
789#
790# CONFIG_USB_ACM is not set
791# CONFIG_USB_PRINTER is not set
792
793#
794# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
795#
796
797#
798# may also be needed; see USB_STORAGE Help for more information
799#
800CONFIG_USB_STORAGE=y
801# CONFIG_USB_STORAGE_DEBUG is not set
802CONFIG_USB_STORAGE_DATAFAB=y
803CONFIG_USB_STORAGE_FREECOM=y
804CONFIG_USB_STORAGE_DPCM=y
805# CONFIG_USB_STORAGE_USBAT is not set
806CONFIG_USB_STORAGE_SDDR09=y
807CONFIG_USB_STORAGE_SDDR55=y
808CONFIG_USB_STORAGE_JUMPSHOT=y
809# CONFIG_USB_STORAGE_ALAUDA is not set
810# CONFIG_USB_STORAGE_KARMA is not set
811# CONFIG_USB_LIBUSUAL is not set
812
813#
814# USB Imaging devices
815#
816# CONFIG_USB_MDC800 is not set
817# CONFIG_USB_MICROTEK is not set
818CONFIG_USB_MON=y
819
820#
821# USB port drivers
822#
823
824#
825# USB Serial Converter support
826#
827# CONFIG_USB_SERIAL is not set
828
829#
830# USB Miscellaneous drivers
831#
832# CONFIG_USB_EMI62 is not set
833# CONFIG_USB_EMI26 is not set
834# CONFIG_USB_ADUTUX is not set
835# CONFIG_USB_AUERSWALD is not set
836# CONFIG_USB_RIO500 is not set
837# CONFIG_USB_LEGOTOWER is not set
838# CONFIG_USB_LCD is not set
839# CONFIG_USB_BERRY_CHARGE is not set
840# CONFIG_USB_LED is not set
841# CONFIG_USB_CYPRESS_CY7C63 is not set
842# CONFIG_USB_CYTHERM is not set
843# CONFIG_USB_PHIDGET is not set
844# CONFIG_USB_IDMOUSE is not set
845# CONFIG_USB_FTDI_ELAN is not set
846# CONFIG_USB_APPLEDISPLAY is not set
847# CONFIG_USB_LD is not set
848# CONFIG_USB_TRANCEVIBRATOR is not set
849# CONFIG_USB_IOWARRIOR is not set
850# CONFIG_USB_TEST is not set
851
852#
853# USB DSL modem support
854#
855
856#
857# USB Gadget Support
858#
859# CONFIG_USB_GADGET is not set
860CONFIG_MMC=y
861# CONFIG_MMC_DEBUG is not set
862# CONFIG_MMC_UNSAFE_RESUME is not set
863
864#
865# MMC/SD Card Drivers
866#
867CONFIG_MMC_BLOCK=y
868CONFIG_MMC_BLOCK_BOUNCE=y
869
870#
871# MMC/SD Host Controller Drivers
872#
873CONFIG_MMC_OMAP=y
874CONFIG_RTC_LIB=y
875CONFIG_RTC_CLASS=y
876CONFIG_RTC_HCTOSYS=y
877CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
878# CONFIG_RTC_DEBUG is not set
879
880#
881# RTC interfaces
882#
883CONFIG_RTC_INTF_SYSFS=y
884CONFIG_RTC_INTF_PROC=y
885CONFIG_RTC_INTF_DEV=y
886# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
887# CONFIG_RTC_DRV_TEST is not set
888
889#
890# I2C RTC drivers
891#
892# CONFIG_RTC_DRV_DS1307 is not set
893# CONFIG_RTC_DRV_DS1672 is not set
894# CONFIG_RTC_DRV_MAX6900 is not set
895# CONFIG_RTC_DRV_RS5C372 is not set
896# CONFIG_RTC_DRV_ISL1208 is not set
897# CONFIG_RTC_DRV_X1205 is not set
898# CONFIG_RTC_DRV_PCF8563 is not set
899# CONFIG_RTC_DRV_PCF8583 is not set
900# CONFIG_RTC_DRV_M41T80 is not set
901
902#
903# SPI RTC drivers
904#
905
906#
907# Platform RTC drivers
908#
909# CONFIG_RTC_DRV_CMOS is not set
910# CONFIG_RTC_DRV_DS1553 is not set
911# CONFIG_RTC_DRV_STK17TA8 is not set
912# CONFIG_RTC_DRV_DS1742 is not set
913# CONFIG_RTC_DRV_M48T86 is not set
914# CONFIG_RTC_DRV_M48T59 is not set
915# CONFIG_RTC_DRV_V3020 is not set
916
917#
918# on-CPU RTC drivers
919#
920CONFIG_RTC_DRV_OMAP=y
921
922#
923# DMA Engine support
924#
925# CONFIG_DMA_ENGINE is not set
926
927#
928# DMA Clients
929#
930
931#
932# DMA Devices
933#
934
935#
936# CBUS support
937#
938# CONFIG_CBUS is not set
939
940#
941# File systems
942#
943CONFIG_EXT2_FS=y
944# CONFIG_EXT2_FS_XATTR is not set
945# CONFIG_EXT2_FS_XIP is not set
946CONFIG_EXT3_FS=y
947CONFIG_EXT3_FS_XATTR=y
948# CONFIG_EXT3_FS_POSIX_ACL is not set
949# CONFIG_EXT3_FS_SECURITY is not set
950# CONFIG_EXT4DEV_FS is not set
951CONFIG_JBD=y
952# CONFIG_JBD_DEBUG is not set
953CONFIG_FS_MBCACHE=y
954# CONFIG_REISERFS_FS is not set
955# CONFIG_JFS_FS is not set
956# CONFIG_FS_POSIX_ACL is not set
957# CONFIG_XFS_FS is not set
958# CONFIG_GFS2_FS is not set
959# CONFIG_OCFS2_FS is not set
960# CONFIG_MINIX_FS is not set
961# CONFIG_ROMFS_FS is not set
962CONFIG_INOTIFY=y
963CONFIG_INOTIFY_USER=y
964# CONFIG_QUOTA is not set
965CONFIG_DNOTIFY=y
966CONFIG_AUTOFS_FS=y
967CONFIG_AUTOFS4_FS=y
968# CONFIG_FUSE_FS is not set
969
970#
971# CD-ROM/DVD Filesystems
972#
973CONFIG_ISO9660_FS=y
974CONFIG_JOLIET=y
975# CONFIG_ZISOFS is not set
976# CONFIG_UDF_FS is not set
977
978#
979# DOS/FAT/NT Filesystems
980#
981CONFIG_FAT_FS=m
982CONFIG_MSDOS_FS=m
983CONFIG_VFAT_FS=m
984CONFIG_FAT_DEFAULT_CODEPAGE=437
985CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
986# CONFIG_NTFS_FS is not set
987
988#
989# Pseudo filesystems
990#
991CONFIG_PROC_FS=y
992CONFIG_PROC_SYSCTL=y
993CONFIG_SYSFS=y
994# CONFIG_TMPFS is not set
995# CONFIG_HUGETLB_PAGE is not set
996CONFIG_RAMFS=y
997# CONFIG_CONFIGFS_FS is not set
998
999#
1000# Miscellaneous filesystems
1001#
1002# CONFIG_ADFS_FS is not set
1003# CONFIG_AFFS_FS is not set
1004# CONFIG_HFS_FS is not set
1005# CONFIG_HFSPLUS_FS is not set
1006# CONFIG_BEFS_FS is not set
1007# CONFIG_BFS_FS is not set
1008# CONFIG_EFS_FS is not set
1009# CONFIG_CRAMFS is not set
1010# CONFIG_VXFS_FS is not set
1011# CONFIG_HPFS_FS is not set
1012# CONFIG_QNX4FS_FS is not set
1013# CONFIG_SYSV_FS is not set
1014# CONFIG_UFS_FS is not set
1015
1016#
1017# Network File Systems
1018#
1019CONFIG_NFS_FS=y
1020# CONFIG_NFS_V3 is not set
1021# CONFIG_NFS_V4 is not set
1022# CONFIG_NFS_DIRECTIO is not set
1023# CONFIG_NFSD is not set
1024# CONFIG_ROOT_NFS is not set
1025CONFIG_LOCKD=y
1026CONFIG_NFS_COMMON=y
1027CONFIG_SUNRPC=y
1028# CONFIG_SUNRPC_BIND34 is not set
1029# CONFIG_RPCSEC_GSS_KRB5 is not set
1030# CONFIG_RPCSEC_GSS_SPKM3 is not set
1031# CONFIG_SMB_FS is not set
1032# CONFIG_CIFS is not set
1033# CONFIG_NCP_FS is not set
1034# CONFIG_CODA_FS is not set
1035# CONFIG_AFS_FS is not set
1036
1037#
1038# Partition Types
1039#
1040CONFIG_PARTITION_ADVANCED=y
1041# CONFIG_ACORN_PARTITION is not set
1042# CONFIG_OSF_PARTITION is not set
1043# CONFIG_AMIGA_PARTITION is not set
1044# CONFIG_ATARI_PARTITION is not set
1045# CONFIG_MAC_PARTITION is not set
1046CONFIG_MSDOS_PARTITION=y
1047# CONFIG_BSD_DISKLABEL is not set
1048# CONFIG_MINIX_SUBPARTITION is not set
1049# CONFIG_SOLARIS_X86_PARTITION is not set
1050# CONFIG_UNIXWARE_DISKLABEL is not set
1051# CONFIG_LDM_PARTITION is not set
1052# CONFIG_SGI_PARTITION is not set
1053# CONFIG_ULTRIX_PARTITION is not set
1054# CONFIG_SUN_PARTITION is not set
1055# CONFIG_KARMA_PARTITION is not set
1056# CONFIG_EFI_PARTITION is not set
1057# CONFIG_SYSV68_PARTITION is not set
1058
1059#
1060# Native Language Support
1061#
1062CONFIG_NLS=y
1063CONFIG_NLS_DEFAULT="iso8859-1"
1064# CONFIG_NLS_CODEPAGE_437 is not set
1065# CONFIG_NLS_CODEPAGE_737 is not set
1066# CONFIG_NLS_CODEPAGE_775 is not set
1067# CONFIG_NLS_CODEPAGE_850 is not set
1068# CONFIG_NLS_CODEPAGE_852 is not set
1069# CONFIG_NLS_CODEPAGE_855 is not set
1070# CONFIG_NLS_CODEPAGE_857 is not set
1071# CONFIG_NLS_CODEPAGE_860 is not set
1072# CONFIG_NLS_CODEPAGE_861 is not set
1073# CONFIG_NLS_CODEPAGE_862 is not set
1074# CONFIG_NLS_CODEPAGE_863 is not set
1075# CONFIG_NLS_CODEPAGE_864 is not set
1076# CONFIG_NLS_CODEPAGE_865 is not set
1077# CONFIG_NLS_CODEPAGE_866 is not set
1078# CONFIG_NLS_CODEPAGE_869 is not set
1079# CONFIG_NLS_CODEPAGE_936 is not set
1080# CONFIG_NLS_CODEPAGE_950 is not set
1081# CONFIG_NLS_CODEPAGE_932 is not set
1082# CONFIG_NLS_CODEPAGE_949 is not set
1083# CONFIG_NLS_CODEPAGE_874 is not set
1084# CONFIG_NLS_ISO8859_8 is not set
1085# CONFIG_NLS_CODEPAGE_1250 is not set
1086# CONFIG_NLS_CODEPAGE_1251 is not set
1087# CONFIG_NLS_ASCII is not set
1088# CONFIG_NLS_ISO8859_1 is not set
1089# CONFIG_NLS_ISO8859_2 is not set
1090# CONFIG_NLS_ISO8859_3 is not set
1091# CONFIG_NLS_ISO8859_4 is not set
1092# CONFIG_NLS_ISO8859_5 is not set
1093# CONFIG_NLS_ISO8859_6 is not set
1094# CONFIG_NLS_ISO8859_7 is not set
1095# CONFIG_NLS_ISO8859_9 is not set
1096# CONFIG_NLS_ISO8859_13 is not set
1097# CONFIG_NLS_ISO8859_14 is not set
1098# CONFIG_NLS_ISO8859_15 is not set
1099# CONFIG_NLS_KOI8_R is not set
1100# CONFIG_NLS_KOI8_U is not set
1101# CONFIG_NLS_UTF8 is not set
1102
1103#
1104# Distributed Lock Manager
1105#
1106# CONFIG_DLM is not set
1107
1108#
1109# Profiling support
1110#
1111# CONFIG_PROFILING is not set
1112
1113#
1114# Kernel hacking
1115#
1116# CONFIG_PRINTK_TIME is not set
1117CONFIG_ENABLE_MUST_CHECK=y
1118CONFIG_MAGIC_SYSRQ=y
1119# CONFIG_UNUSED_SYMBOLS is not set
1120# CONFIG_DEBUG_FS is not set
1121# CONFIG_HEADERS_CHECK is not set
1122CONFIG_DEBUG_KERNEL=y
1123# CONFIG_DEBUG_SHIRQ is not set
1124CONFIG_DETECT_SOFTLOCKUP=y
1125CONFIG_SCHED_DEBUG=y
1126# CONFIG_SCHEDSTATS is not set
1127# CONFIG_TIMER_STATS is not set
1128# CONFIG_DEBUG_SLAB is not set
1129CONFIG_DEBUG_PREEMPT=y
1130# CONFIG_DEBUG_RT_MUTEXES is not set
1131# CONFIG_RT_MUTEX_TESTER is not set
1132# CONFIG_DEBUG_SPINLOCK is not set
1133# CONFIG_DEBUG_MUTEXES is not set
1134# CONFIG_DEBUG_LOCK_ALLOC is not set
1135# CONFIG_PROVE_LOCKING is not set
1136# CONFIG_LOCK_STAT is not set
1137# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1138# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1139# CONFIG_DEBUG_KOBJECT is not set
1140CONFIG_DEBUG_BUGVERBOSE=y
1141# CONFIG_DEBUG_INFO is not set
1142# CONFIG_DEBUG_VM is not set
1143# CONFIG_DEBUG_LIST is not set
1144CONFIG_FRAME_POINTER=y
1145CONFIG_FORCED_INLINING=y
1146# CONFIG_RCU_TORTURE_TEST is not set
1147# CONFIG_FAULT_INJECTION is not set
1148# CONFIG_DEBUG_USER is not set
1149# CONFIG_DEBUG_ERRORS is not set
1150# CONFIG_DEBUG_LL is not set
1151
1152#
1153# Security options
1154#
1155# CONFIG_KEYS is not set
1156# CONFIG_SECURITY is not set
1157# CONFIG_CRYPTO is not set
1158
1159#
1160# Library routines
1161#
1162CONFIG_BITREVERSE=y
1163# CONFIG_CRC_CCITT is not set
1164# CONFIG_CRC16 is not set
1165# CONFIG_CRC_ITU_T is not set
1166CONFIG_CRC32=y
1167# CONFIG_CRC7 is not set
1168# CONFIG_LIBCRC32C is not set
1169CONFIG_PLIST=y
1170CONFIG_HAS_IOMEM=y
1171CONFIG_HAS_IOPORT=y
1172CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/omap_generic_1610_defconfig b/arch/arm/configs/omap_generic_1610_defconfig
new file mode 100644
index 000000000000..fc66f019d56c
--- /dev/null
+++ b/arch/arm/configs/omap_generic_1610_defconfig
@@ -0,0 +1,1178 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.23-rc6-omap1
4# Tue Sep 18 13:01:27 2007
5#
6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8CONFIG_GENERIC_GPIO=y
9CONFIG_GENERIC_TIME=y
10CONFIG_GENERIC_CLOCKEVENTS=y
11CONFIG_MMU=y
12# CONFIG_NO_IOPORT is not set
13CONFIG_GENERIC_HARDIRQS=y
14CONFIG_STACKTRACE_SUPPORT=y
15CONFIG_LOCKDEP_SUPPORT=y
16CONFIG_TRACE_IRQFLAGS_SUPPORT=y
17CONFIG_HARDIRQS_SW_RESEND=y
18CONFIG_GENERIC_IRQ_PROBE=y
19CONFIG_RWSEM_GENERIC_SPINLOCK=y
20# CONFIG_ARCH_HAS_ILOG2_U32 is not set
21# CONFIG_ARCH_HAS_ILOG2_U64 is not set
22CONFIG_GENERIC_HWEIGHT=y
23CONFIG_GENERIC_CALIBRATE_DELAY=y
24CONFIG_ZONE_DMA=y
25CONFIG_VECTORS_BASE=0xffff0000
26CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
27
28#
29# General setup
30#
31CONFIG_EXPERIMENTAL=y
32CONFIG_BROKEN_ON_SMP=y
33CONFIG_LOCK_KERNEL=y
34CONFIG_INIT_ENV_ARG_LIMIT=32
35CONFIG_LOCALVERSION=""
36CONFIG_LOCALVERSION_AUTO=y
37CONFIG_SWAP=y
38CONFIG_SYSVIPC=y
39CONFIG_SYSVIPC_SYSCTL=y
40# CONFIG_POSIX_MQUEUE is not set
41# CONFIG_BSD_PROCESS_ACCT is not set
42# CONFIG_TASKSTATS is not set
43# CONFIG_USER_NS is not set
44# CONFIG_AUDIT is not set
45# CONFIG_IKCONFIG is not set
46CONFIG_LOG_BUF_SHIFT=14
47CONFIG_SYSFS_DEPRECATED=y
48# CONFIG_RELAY is not set
49CONFIG_BLK_DEV_INITRD=y
50CONFIG_INITRAMFS_SOURCE=""
51CONFIG_CC_OPTIMIZE_FOR_SIZE=y
52CONFIG_SYSCTL=y
53# CONFIG_EMBEDDED is not set
54CONFIG_UID16=y
55CONFIG_SYSCTL_SYSCALL=y
56CONFIG_KALLSYMS=y
57# CONFIG_KALLSYMS_ALL is not set
58# CONFIG_KALLSYMS_EXTRA_PASS is not set
59CONFIG_HOTPLUG=y
60CONFIG_PRINTK=y
61CONFIG_BUG=y
62CONFIG_ELF_CORE=y
63CONFIG_BASE_FULL=y
64CONFIG_FUTEX=y
65CONFIG_ANON_INODES=y
66CONFIG_EPOLL=y
67CONFIG_SIGNALFD=y
68CONFIG_TIMERFD=y
69CONFIG_EVENTFD=y
70CONFIG_SHMEM=y
71CONFIG_VM_EVENT_COUNTERS=y
72CONFIG_SLAB=y
73# CONFIG_SLUB is not set
74# CONFIG_SLOB is not set
75CONFIG_RT_MUTEXES=y
76# CONFIG_TINY_SHMEM is not set
77CONFIG_BASE_SMALL=0
78CONFIG_MODULES=y
79CONFIG_MODULE_UNLOAD=y
80CONFIG_MODULE_FORCE_UNLOAD=y
81# CONFIG_MODVERSIONS is not set
82# CONFIG_MODULE_SRCVERSION_ALL is not set
83CONFIG_KMOD=y
84CONFIG_BLOCK=y
85# CONFIG_LBD is not set
86# CONFIG_BLK_DEV_IO_TRACE is not set
87# CONFIG_LSF is not set
88# CONFIG_BLK_DEV_BSG is not set
89
90#
91# IO Schedulers
92#
93CONFIG_IOSCHED_NOOP=y
94CONFIG_IOSCHED_AS=y
95CONFIG_IOSCHED_DEADLINE=y
96CONFIG_IOSCHED_CFQ=y
97# CONFIG_DEFAULT_AS is not set
98# CONFIG_DEFAULT_DEADLINE is not set
99CONFIG_DEFAULT_CFQ=y
100# CONFIG_DEFAULT_NOOP is not set
101CONFIG_DEFAULT_IOSCHED="cfq"
102
103#
104# System Type
105#
106# CONFIG_ARCH_AAEC2000 is not set
107# CONFIG_ARCH_INTEGRATOR is not set
108# CONFIG_ARCH_REALVIEW is not set
109# CONFIG_ARCH_VERSATILE is not set
110# CONFIG_ARCH_AT91 is not set
111# CONFIG_ARCH_CLPS7500 is not set
112# CONFIG_ARCH_CLPS711X is not set
113# CONFIG_ARCH_CO285 is not set
114# CONFIG_ARCH_EBSA110 is not set
115# CONFIG_ARCH_EP93XX is not set
116# CONFIG_ARCH_FOOTBRIDGE is not set
117# CONFIG_ARCH_NETX is not set
118# CONFIG_ARCH_H720X is not set
119# CONFIG_ARCH_IMX is not set
120# CONFIG_ARCH_IOP13XX is not set
121# CONFIG_ARCH_IOP32X is not set
122# CONFIG_ARCH_IOP33X is not set
123# CONFIG_ARCH_IXP23XX is not set
124# CONFIG_ARCH_IXP2000 is not set
125# CONFIG_ARCH_IXP4XX is not set
126# CONFIG_ARCH_L7200 is not set
127# CONFIG_ARCH_KS8695 is not set
128# CONFIG_ARCH_NS9XXX is not set
129# CONFIG_ARCH_MXC is not set
130# CONFIG_ARCH_PNX4008 is not set
131# CONFIG_ARCH_PXA is not set
132# CONFIG_ARCH_RPC is not set
133# CONFIG_ARCH_SA1100 is not set
134# CONFIG_ARCH_S3C2410 is not set
135# CONFIG_ARCH_SHARK is not set
136# CONFIG_ARCH_LH7A40X is not set
137# CONFIG_ARCH_DAVINCI is not set
138CONFIG_ARCH_OMAP=y
139
140#
141# TI OMAP Implementations
142#
143CONFIG_ARCH_OMAP_OTG=y
144CONFIG_ARCH_OMAP1=y
145# CONFIG_ARCH_OMAP2 is not set
146# CONFIG_ARCH_OMAP3 is not set
147
148#
149# OMAP Feature Selections
150#
151# CONFIG_OMAP_RESET_CLOCKS is not set
152# CONFIG_OMAP_BOOT_TAG is not set
153# CONFIG_OMAP_GPIO_SWITCH is not set
154CONFIG_OMAP_MUX=y
155# CONFIG_OMAP_MUX_DEBUG is not set
156CONFIG_OMAP_MUX_WARNINGS=y
157# CONFIG_OMAP_STI is not set
158CONFIG_OMAP_MCBSP=y
159# CONFIG_OMAP_MMU_FWK is not set
160# CONFIG_OMAP_MBOX_FWK is not set
161CONFIG_OMAP_MPU_TIMER=y
162# CONFIG_OMAP_32K_TIMER is not set
163# CONFIG_OMAP_DM_TIMER is not set
164CONFIG_OMAP_LL_DEBUG_UART1=y
165# CONFIG_OMAP_LL_DEBUG_UART2 is not set
166# CONFIG_OMAP_LL_DEBUG_UART3 is not set
167CONFIG_OMAP_SERIAL_WAKE=y
168# CONFIG_OMAP_DSP is not set
169
170#
171# OMAP Core Type
172#
173# CONFIG_ARCH_OMAP730 is not set
174# CONFIG_ARCH_OMAP15XX is not set
175CONFIG_ARCH_OMAP16XX=y
176
177#
178# OMAP Board Type
179#
180# CONFIG_MACH_OMAP_INNOVATOR is not set
181# CONFIG_MACH_OMAP_H2 is not set
182# CONFIG_MACH_OMAP_H3 is not set
183# CONFIG_MACH_OMAP_OSK is not set
184# CONFIG_MACH_NOKIA770 is not set
185CONFIG_MACH_OMAP_GENERIC=y
186
187#
188# OMAP CPU Speed
189#
190# CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER is not set
191# CONFIG_OMAP_ARM_216MHZ is not set
192CONFIG_OMAP_ARM_192MHZ=y
193# CONFIG_OMAP_ARM_168MHZ is not set
194# CONFIG_OMAP_ARM_120MHZ is not set
195# CONFIG_OMAP_ARM_60MHZ is not set
196# CONFIG_OMAP_ARM_30MHZ is not set
197# CONFIG_MACH_OMAP_APOLLON_PLUS is not set
198
199#
200# Boot options
201#
202
203#
204# Power management
205#
206
207#
208# Processor Type
209#
210CONFIG_CPU_32=y
211CONFIG_CPU_ARM926T=y
212CONFIG_CPU_32v5=y
213CONFIG_CPU_ABRT_EV5TJ=y
214CONFIG_CPU_PABRT_NOIFAR=y
215CONFIG_CPU_CACHE_VIVT=y
216CONFIG_CPU_COPY_V4WB=y
217CONFIG_CPU_TLB_V4WBI=y
218CONFIG_CPU_CP15=y
219CONFIG_CPU_CP15_MMU=y
220
221#
222# Processor Features
223#
224# CONFIG_ARM_THUMB is not set
225# CONFIG_CPU_ICACHE_DISABLE is not set
226# CONFIG_CPU_DCACHE_DISABLE is not set
227# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
228# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
229# CONFIG_OUTER_CACHE is not set
230
231#
232# Bus support
233#
234# CONFIG_PCI_SYSCALL is not set
235# CONFIG_ARCH_SUPPORTS_MSI is not set
236
237#
238# PCCARD (PCMCIA/CardBus) support
239#
240# CONFIG_PCCARD is not set
241
242#
243# Kernel Features
244#
245# CONFIG_TICK_ONESHOT is not set
246# CONFIG_NO_HZ is not set
247# CONFIG_HIGH_RES_TIMERS is not set
248CONFIG_PREEMPT=y
249CONFIG_HZ=100
250# CONFIG_AEABI is not set
251# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
252CONFIG_SELECT_MEMORY_MODEL=y
253CONFIG_FLATMEM_MANUAL=y
254# CONFIG_DISCONTIGMEM_MANUAL is not set
255# CONFIG_SPARSEMEM_MANUAL is not set
256CONFIG_FLATMEM=y
257CONFIG_FLAT_NODE_MEM_MAP=y
258# CONFIG_SPARSEMEM_STATIC is not set
259CONFIG_SPLIT_PTLOCK_CPUS=4096
260# CONFIG_RESOURCES_64BIT is not set
261CONFIG_ZONE_DMA_FLAG=1
262CONFIG_BOUNCE=y
263CONFIG_VIRT_TO_BUS=y
264# CONFIG_LEDS is not set
265CONFIG_ALIGNMENT_TRAP=y
266
267#
268# Boot options
269#
270CONFIG_ZBOOT_ROM_TEXT=0x0
271CONFIG_ZBOOT_ROM_BSS=0x0
272CONFIG_CMDLINE="mem=64M console=ttyS2,115200 root=0803 ro init=/bin/sh"
273# CONFIG_XIP_KERNEL is not set
274# CONFIG_KEXEC is not set
275
276#
277# CPU Frequency scaling
278#
279# CONFIG_CPU_FREQ is not set
280
281#
282# Floating point emulation
283#
284
285#
286# At least one emulation must be selected
287#
288CONFIG_FPE_NWFPE=y
289# CONFIG_FPE_NWFPE_XP is not set
290# CONFIG_FPE_FASTFPE is not set
291# CONFIG_VFP is not set
292
293#
294# Userspace binary formats
295#
296CONFIG_BINFMT_ELF=y
297# CONFIG_BINFMT_AOUT is not set
298# CONFIG_BINFMT_MISC is not set
299# CONFIG_ARTHUR is not set
300
301#
302# Power management options
303#
304CONFIG_PM=y
305# CONFIG_PM_LEGACY is not set
306# CONFIG_PM_DEBUG is not set
307CONFIG_PM_SLEEP=y
308CONFIG_SUSPEND_UP_POSSIBLE=y
309CONFIG_SUSPEND=y
310# CONFIG_APM_EMULATION is not set
311
312#
313# Networking
314#
315CONFIG_NET=y
316
317#
318# Networking options
319#
320CONFIG_PACKET=y
321# CONFIG_PACKET_MMAP is not set
322CONFIG_UNIX=y
323CONFIG_XFRM=y
324# CONFIG_XFRM_USER is not set
325# CONFIG_XFRM_SUB_POLICY is not set
326# CONFIG_XFRM_MIGRATE is not set
327# CONFIG_NET_KEY is not set
328CONFIG_INET=y
329CONFIG_IP_MULTICAST=y
330# CONFIG_IP_ADVANCED_ROUTER is not set
331CONFIG_IP_FIB_HASH=y
332CONFIG_IP_PNP=y
333CONFIG_IP_PNP_DHCP=y
334CONFIG_IP_PNP_BOOTP=y
335# CONFIG_IP_PNP_RARP is not set
336# CONFIG_NET_IPIP is not set
337# CONFIG_NET_IPGRE is not set
338# CONFIG_IP_MROUTE is not set
339# CONFIG_ARPD is not set
340# CONFIG_SYN_COOKIES is not set
341# CONFIG_INET_AH is not set
342# CONFIG_INET_ESP is not set
343# CONFIG_INET_IPCOMP is not set
344# CONFIG_INET_XFRM_TUNNEL is not set
345# CONFIG_INET_TUNNEL is not set
346CONFIG_INET_XFRM_MODE_TRANSPORT=y
347CONFIG_INET_XFRM_MODE_TUNNEL=y
348CONFIG_INET_XFRM_MODE_BEET=y
349CONFIG_INET_DIAG=y
350CONFIG_INET_TCP_DIAG=y
351# CONFIG_TCP_CONG_ADVANCED is not set
352CONFIG_TCP_CONG_CUBIC=y
353CONFIG_DEFAULT_TCP_CONG="cubic"
354# CONFIG_TCP_MD5SIG is not set
355# CONFIG_IPV6 is not set
356# CONFIG_INET6_XFRM_TUNNEL is not set
357# CONFIG_INET6_TUNNEL is not set
358# CONFIG_NETWORK_SECMARK is not set
359# CONFIG_NETFILTER is not set
360# CONFIG_IP_DCCP is not set
361# CONFIG_IP_SCTP is not set
362# CONFIG_TIPC is not set
363# CONFIG_ATM is not set
364# CONFIG_BRIDGE is not set
365# CONFIG_VLAN_8021Q is not set
366# CONFIG_DECNET is not set
367# CONFIG_LLC2 is not set
368# CONFIG_IPX is not set
369# CONFIG_ATALK is not set
370# CONFIG_X25 is not set
371# CONFIG_LAPB is not set
372# CONFIG_ECONET is not set
373# CONFIG_WAN_ROUTER is not set
374
375#
376# QoS and/or fair queueing
377#
378# CONFIG_NET_SCHED is not set
379
380#
381# Network testing
382#
383# CONFIG_NET_PKTGEN is not set
384# CONFIG_HAMRADIO is not set
385# CONFIG_IRDA is not set
386# CONFIG_BT is not set
387# CONFIG_AF_RXRPC is not set
388
389#
390# Wireless
391#
392# CONFIG_CFG80211 is not set
393# CONFIG_WIRELESS_EXT is not set
394# CONFIG_MAC80211 is not set
395# CONFIG_IEEE80211 is not set
396# CONFIG_RFKILL is not set
397# CONFIG_NET_9P is not set
398
399#
400# Device Drivers
401#
402
403#
404# Generic Driver Options
405#
406CONFIG_STANDALONE=y
407CONFIG_PREVENT_FIRMWARE_BUILD=y
408# CONFIG_FW_LOADER is not set
409# CONFIG_DEBUG_DRIVER is not set
410# CONFIG_DEBUG_DEVRES is not set
411# CONFIG_SYS_HYPERVISOR is not set
412# CONFIG_CONNECTOR is not set
413# CONFIG_MTD is not set
414# CONFIG_PARPORT is not set
415CONFIG_BLK_DEV=y
416# CONFIG_BLK_DEV_COW_COMMON is not set
417CONFIG_BLK_DEV_LOOP=y
418# CONFIG_BLK_DEV_CRYPTOLOOP is not set
419# CONFIG_BLK_DEV_NBD is not set
420# CONFIG_BLK_DEV_UB is not set
421CONFIG_BLK_DEV_RAM=y
422CONFIG_BLK_DEV_RAM_COUNT=16
423CONFIG_BLK_DEV_RAM_SIZE=8192
424CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
425# CONFIG_CDROM_PKTCDVD is not set
426# CONFIG_ATA_OVER_ETH is not set
427
428#
429# SCSI device support
430#
431# CONFIG_RAID_ATTRS is not set
432CONFIG_SCSI=y
433CONFIG_SCSI_DMA=y
434# CONFIG_SCSI_TGT is not set
435# CONFIG_SCSI_NETLINK is not set
436CONFIG_SCSI_PROC_FS=y
437
438#
439# SCSI support type (disk, tape, CD-ROM)
440#
441CONFIG_BLK_DEV_SD=y
442# CONFIG_CHR_DEV_ST is not set
443# CONFIG_CHR_DEV_OSST is not set
444CONFIG_BLK_DEV_SR=y
445# CONFIG_BLK_DEV_SR_VENDOR is not set
446CONFIG_CHR_DEV_SG=y
447# CONFIG_CHR_DEV_SCH is not set
448
449#
450# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
451#
452CONFIG_SCSI_MULTI_LUN=y
453# CONFIG_SCSI_CONSTANTS is not set
454# CONFIG_SCSI_LOGGING is not set
455# CONFIG_SCSI_SCAN_ASYNC is not set
456CONFIG_SCSI_WAIT_SCAN=m
457
458#
459# SCSI Transports
460#
461# CONFIG_SCSI_SPI_ATTRS is not set
462# CONFIG_SCSI_FC_ATTRS is not set
463# CONFIG_SCSI_ISCSI_ATTRS is not set
464# CONFIG_SCSI_SAS_LIBSAS is not set
465CONFIG_SCSI_LOWLEVEL=y
466# CONFIG_ISCSI_TCP is not set
467# CONFIG_SCSI_DEBUG is not set
468# CONFIG_ATA is not set
469# CONFIG_MD is not set
470CONFIG_NETDEVICES=y
471# CONFIG_NETDEVICES_MULTIQUEUE is not set
472# CONFIG_DUMMY is not set
473# CONFIG_BONDING is not set
474# CONFIG_MACVLAN is not set
475# CONFIG_EQUALIZER is not set
476# CONFIG_TUN is not set
477# CONFIG_PHYLIB is not set
478CONFIG_NET_ETHERNET=y
479CONFIG_MII=y
480# CONFIG_AX88796 is not set
481# CONFIG_SMC91X is not set
482# CONFIG_DM9000 is not set
483CONFIG_NETDEV_1000=y
484CONFIG_NETDEV_10000=y
485
486#
487# Wireless LAN
488#
489# CONFIG_WLAN_PRE80211 is not set
490# CONFIG_WLAN_80211 is not set
491
492#
493# USB Network Adapters
494#
495# CONFIG_USB_CATC is not set
496# CONFIG_USB_KAWETH is not set
497# CONFIG_USB_PEGASUS is not set
498CONFIG_USB_RTL8150=y
499CONFIG_USB_USBNET_MII=y
500CONFIG_USB_USBNET=y
501CONFIG_USB_NET_AX8817X=y
502CONFIG_USB_NET_CDCETHER=y
503# CONFIG_USB_NET_DM9601 is not set
504# CONFIG_USB_NET_GL620A is not set
505CONFIG_USB_NET_NET1080=y
506# CONFIG_USB_NET_PLUSB is not set
507# CONFIG_USB_NET_MCS7830 is not set
508# CONFIG_USB_NET_RNDIS_HOST is not set
509CONFIG_USB_NET_CDC_SUBSET=y
510CONFIG_USB_ALI_M5632=y
511CONFIG_USB_AN2720=y
512CONFIG_USB_BELKIN=y
513CONFIG_USB_ARMLINUX=y
514CONFIG_USB_EPSON2888=y
515# CONFIG_USB_KC2190 is not set
516CONFIG_USB_NET_ZAURUS=y
517# CONFIG_WAN is not set
518CONFIG_PPP=y
519CONFIG_PPP_MULTILINK=y
520# CONFIG_PPP_FILTER is not set
521# CONFIG_PPP_ASYNC is not set
522# CONFIG_PPP_SYNC_TTY is not set
523# CONFIG_PPP_DEFLATE is not set
524# CONFIG_PPP_BSDCOMP is not set
525# CONFIG_PPP_MPPE is not set
526# CONFIG_PPPOE is not set
527# CONFIG_PPPOL2TP is not set
528# CONFIG_SLIP is not set
529CONFIG_SLHC=y
530# CONFIG_SHAPER is not set
531# CONFIG_NETCONSOLE is not set
532# CONFIG_NETPOLL is not set
533# CONFIG_NET_POLL_CONTROLLER is not set
534# CONFIG_ISDN is not set
535
536#
537# Input device support
538#
539CONFIG_INPUT=y
540# CONFIG_INPUT_FF_MEMLESS is not set
541# CONFIG_INPUT_POLLDEV is not set
542
543#
544# Userland interfaces
545#
546CONFIG_INPUT_MOUSEDEV=y
547CONFIG_INPUT_MOUSEDEV_PSAUX=y
548CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
549CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
550# CONFIG_INPUT_JOYDEV is not set
551# CONFIG_INPUT_TSDEV is not set
552# CONFIG_INPUT_EVDEV is not set
553# CONFIG_INPUT_EVBUG is not set
554
555#
556# Input Device Drivers
557#
558CONFIG_INPUT_KEYBOARD=y
559CONFIG_KEYBOARD_ATKBD=y
560# CONFIG_KEYBOARD_SUNKBD is not set
561# CONFIG_KEYBOARD_LKKBD is not set
562# CONFIG_KEYBOARD_XTKBD is not set
563# CONFIG_KEYBOARD_NEWTON is not set
564# CONFIG_KEYBOARD_STOWAWAY is not set
565CONFIG_KEYBOARD_OMAP=y
566# CONFIG_KEYBOARD_GPIO is not set
567# CONFIG_INPUT_MOUSE is not set
568# CONFIG_INPUT_JOYSTICK is not set
569# CONFIG_INPUT_TABLET is not set
570# CONFIG_INPUT_TOUCHSCREEN is not set
571# CONFIG_INPUT_MISC is not set
572
573#
574# Hardware I/O ports
575#
576CONFIG_SERIO=y
577CONFIG_SERIO_SERPORT=y
578CONFIG_SERIO_LIBPS2=y
579# CONFIG_SERIO_RAW is not set
580# CONFIG_GAMEPORT is not set
581
582#
583# Character devices
584#
585CONFIG_VT=y
586CONFIG_VT_CONSOLE=y
587CONFIG_HW_CONSOLE=y
588# CONFIG_VT_HW_CONSOLE_BINDING is not set
589# CONFIG_SERIAL_NONSTANDARD is not set
590
591#
592# Serial drivers
593#
594CONFIG_SERIAL_8250=y
595CONFIG_SERIAL_8250_CONSOLE=y
596CONFIG_SERIAL_8250_NR_UARTS=4
597CONFIG_SERIAL_8250_RUNTIME_UARTS=4
598# CONFIG_SERIAL_8250_EXTENDED is not set
599
600#
601# Non-8250 serial port support
602#
603CONFIG_SERIAL_CORE=y
604CONFIG_SERIAL_CORE_CONSOLE=y
605CONFIG_UNIX98_PTYS=y
606# CONFIG_LEGACY_PTYS is not set
607# CONFIG_IPMI_HANDLER is not set
608# CONFIG_WATCHDOG is not set
609CONFIG_HW_RANDOM=m
610CONFIG_HW_RANDOM_OMAP=m
611# CONFIG_NVRAM is not set
612# CONFIG_R3964 is not set
613# CONFIG_RAW_DRIVER is not set
614# CONFIG_TCG_TPM is not set
615CONFIG_I2C=y
616CONFIG_I2C_BOARDINFO=y
617CONFIG_I2C_CHARDEV=y
618
619#
620# I2C Algorithms
621#
622CONFIG_I2C_ALGOBIT=y
623# CONFIG_I2C_ALGOPCF is not set
624# CONFIG_I2C_ALGOPCA is not set
625
626#
627# I2C Hardware Bus support
628#
629# CONFIG_I2C_GPIO is not set
630# CONFIG_I2C_OCORES is not set
631# CONFIG_I2C_OMAP is not set
632# CONFIG_I2C_PARPORT_LIGHT is not set
633# CONFIG_I2C_SIMTEC is not set
634# CONFIG_I2C_TAOS_EVM is not set
635# CONFIG_I2C_STUB is not set
636# CONFIG_I2C_TINY_USB is not set
637
638#
639# Miscellaneous I2C Chip support
640#
641# CONFIG_SENSORS_DS1337 is not set
642# CONFIG_SENSORS_DS1374 is not set
643# CONFIG_DS1682 is not set
644# CONFIG_SENSORS_EEPROM is not set
645# CONFIG_SENSORS_PCF8574 is not set
646# CONFIG_SENSORS_PCA9539 is not set
647# CONFIG_SENSORS_PCF8591 is not set
648# CONFIG_ISP1301_OMAP is not set
649# CONFIG_TPS65010 is not set
650# CONFIG_GPIOEXPANDER_OMAP is not set
651# CONFIG_SENSORS_MAX6875 is not set
652# CONFIG_SENSORS_TSL2550 is not set
653# CONFIG_I2C_DEBUG_CORE is not set
654# CONFIG_I2C_DEBUG_ALGO is not set
655# CONFIG_I2C_DEBUG_BUS is not set
656# CONFIG_I2C_DEBUG_CHIP is not set
657
658#
659# SPI support
660#
661# CONFIG_SPI is not set
662# CONFIG_SPI_MASTER is not set
663# CONFIG_W1 is not set
664CONFIG_HWMON=y
665# CONFIG_HWMON_VID is not set
666# CONFIG_SENSORS_ABITUGURU is not set
667# CONFIG_SENSORS_ABITUGURU3 is not set
668# CONFIG_SENSORS_AD7418 is not set
669# CONFIG_SENSORS_ADM1021 is not set
670# CONFIG_SENSORS_ADM1025 is not set
671# CONFIG_SENSORS_ADM1026 is not set
672# CONFIG_SENSORS_ADM1029 is not set
673# CONFIG_SENSORS_ADM1031 is not set
674# CONFIG_SENSORS_ADM9240 is not set
675# CONFIG_SENSORS_ASB100 is not set
676# CONFIG_SENSORS_ATXP1 is not set
677# CONFIG_SENSORS_DS1621 is not set
678# CONFIG_SENSORS_F71805F is not set
679# CONFIG_SENSORS_FSCHER is not set
680# CONFIG_SENSORS_FSCPOS is not set
681# CONFIG_SENSORS_GL518SM is not set
682# CONFIG_SENSORS_GL520SM is not set
683# CONFIG_SENSORS_IT87 is not set
684# CONFIG_SENSORS_LM63 is not set
685# CONFIG_SENSORS_LM75 is not set
686# CONFIG_SENSORS_LM77 is not set
687# CONFIG_SENSORS_LM78 is not set
688# CONFIG_SENSORS_LM80 is not set
689# CONFIG_SENSORS_LM83 is not set
690# CONFIG_SENSORS_LM85 is not set
691# CONFIG_SENSORS_LM87 is not set
692# CONFIG_SENSORS_LM90 is not set
693# CONFIG_SENSORS_LM92 is not set
694# CONFIG_SENSORS_LM93 is not set
695# CONFIG_SENSORS_MAX1619 is not set
696# CONFIG_SENSORS_MAX6650 is not set
697# CONFIG_SENSORS_PC87360 is not set
698# CONFIG_SENSORS_PC87427 is not set
699# CONFIG_SENSORS_DME1737 is not set
700# CONFIG_SENSORS_SMSC47M1 is not set
701# CONFIG_SENSORS_SMSC47M192 is not set
702# CONFIG_SENSORS_SMSC47B397 is not set
703# CONFIG_SENSORS_THMC50 is not set
704# CONFIG_SENSORS_VT1211 is not set
705# CONFIG_SENSORS_W83781D is not set
706# CONFIG_SENSORS_W83791D is not set
707# CONFIG_SENSORS_W83792D is not set
708# CONFIG_SENSORS_W83793 is not set
709# CONFIG_SENSORS_W83L785TS is not set
710# CONFIG_SENSORS_W83627HF is not set
711# CONFIG_SENSORS_W83627EHF is not set
712# CONFIG_HWMON_DEBUG_CHIP is not set
713CONFIG_MISC_DEVICES=y
714# CONFIG_EEPROM_93CX6 is not set
715
716#
717# Multifunction device drivers
718#
719# CONFIG_MFD_SM501 is not set
720# CONFIG_NEW_LEDS is not set
721
722#
723# Multimedia devices
724#
725# CONFIG_VIDEO_DEV is not set
726# CONFIG_DVB_CORE is not set
727CONFIG_DAB=y
728# CONFIG_USB_DABUSB is not set
729
730#
731# Graphics support
732#
733# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
734
735#
736# Display device support
737#
738# CONFIG_DISPLAY_SUPPORT is not set
739# CONFIG_VGASTATE is not set
740CONFIG_VIDEO_OUTPUT_CONTROL=m
741# CONFIG_FB is not set
742
743#
744# Console display driver support
745#
746# CONFIG_VGA_CONSOLE is not set
747CONFIG_DUMMY_CONSOLE=y
748
749#
750# Sound
751#
752# CONFIG_SOUND is not set
753CONFIG_HID_SUPPORT=y
754CONFIG_HID=y
755# CONFIG_HID_DEBUG is not set
756
757#
758# USB Input Devices
759#
760CONFIG_USB_HID=y
761# CONFIG_USB_HIDINPUT_POWERBOOK is not set
762# CONFIG_HID_FF is not set
763# CONFIG_USB_HIDDEV is not set
764CONFIG_USB_SUPPORT=y
765CONFIG_USB_ARCH_HAS_HCD=y
766CONFIG_USB_ARCH_HAS_OHCI=y
767# CONFIG_USB_ARCH_HAS_EHCI is not set
768CONFIG_USB=y
769CONFIG_USB_DEBUG=y
770
771#
772# Miscellaneous USB options
773#
774CONFIG_USB_DEVICEFS=y
775# CONFIG_USB_DEVICE_CLASS is not set
776# CONFIG_USB_DYNAMIC_MINORS is not set
777# CONFIG_USB_SUSPEND is not set
778# CONFIG_USB_PERSIST is not set
779# CONFIG_USB_OTG is not set
780
781#
782# USB Host Controller Drivers
783#
784# CONFIG_USB_ISP116X_HCD is not set
785CONFIG_USB_OHCI_HCD=y
786# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
787# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
788CONFIG_USB_OHCI_LITTLE_ENDIAN=y
789# CONFIG_USB_SL811_HCD is not set
790# CONFIG_USB_R8A66597_HCD is not set
791# CONFIG_USB_MUSB_HDRC is not set
792
793#
794# USB Device Class drivers
795#
796# CONFIG_USB_ACM is not set
797# CONFIG_USB_PRINTER is not set
798
799#
800# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
801#
802
803#
804# may also be needed; see USB_STORAGE Help for more information
805#
806CONFIG_USB_STORAGE=y
807# CONFIG_USB_STORAGE_DEBUG is not set
808CONFIG_USB_STORAGE_DATAFAB=y
809CONFIG_USB_STORAGE_FREECOM=y
810CONFIG_USB_STORAGE_DPCM=y
811# CONFIG_USB_STORAGE_USBAT is not set
812CONFIG_USB_STORAGE_SDDR09=y
813CONFIG_USB_STORAGE_SDDR55=y
814CONFIG_USB_STORAGE_JUMPSHOT=y
815# CONFIG_USB_STORAGE_ALAUDA is not set
816# CONFIG_USB_STORAGE_KARMA is not set
817# CONFIG_USB_LIBUSUAL is not set
818
819#
820# USB Imaging devices
821#
822# CONFIG_USB_MDC800 is not set
823# CONFIG_USB_MICROTEK is not set
824CONFIG_USB_MON=y
825
826#
827# USB port drivers
828#
829
830#
831# USB Serial Converter support
832#
833# CONFIG_USB_SERIAL is not set
834
835#
836# USB Miscellaneous drivers
837#
838# CONFIG_USB_EMI62 is not set
839# CONFIG_USB_EMI26 is not set
840# CONFIG_USB_ADUTUX is not set
841# CONFIG_USB_AUERSWALD is not set
842# CONFIG_USB_RIO500 is not set
843# CONFIG_USB_LEGOTOWER is not set
844# CONFIG_USB_LCD is not set
845# CONFIG_USB_BERRY_CHARGE is not set
846# CONFIG_USB_LED is not set
847# CONFIG_USB_CYPRESS_CY7C63 is not set
848# CONFIG_USB_CYTHERM is not set
849# CONFIG_USB_PHIDGET is not set
850# CONFIG_USB_IDMOUSE is not set
851# CONFIG_USB_FTDI_ELAN is not set
852# CONFIG_USB_APPLEDISPLAY is not set
853# CONFIG_USB_LD is not set
854# CONFIG_USB_TRANCEVIBRATOR is not set
855# CONFIG_USB_IOWARRIOR is not set
856# CONFIG_USB_TEST is not set
857
858#
859# USB DSL modem support
860#
861
862#
863# USB Gadget Support
864#
865# CONFIG_USB_GADGET is not set
866CONFIG_MMC=y
867# CONFIG_MMC_DEBUG is not set
868# CONFIG_MMC_UNSAFE_RESUME is not set
869
870#
871# MMC/SD Card Drivers
872#
873CONFIG_MMC_BLOCK=y
874CONFIG_MMC_BLOCK_BOUNCE=y
875
876#
877# MMC/SD Host Controller Drivers
878#
879CONFIG_MMC_OMAP=y
880CONFIG_RTC_LIB=y
881CONFIG_RTC_CLASS=y
882CONFIG_RTC_HCTOSYS=y
883CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
884# CONFIG_RTC_DEBUG is not set
885
886#
887# RTC interfaces
888#
889CONFIG_RTC_INTF_SYSFS=y
890CONFIG_RTC_INTF_PROC=y
891CONFIG_RTC_INTF_DEV=y
892# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
893# CONFIG_RTC_DRV_TEST is not set
894
895#
896# I2C RTC drivers
897#
898# CONFIG_RTC_DRV_DS1307 is not set
899# CONFIG_RTC_DRV_DS1672 is not set
900# CONFIG_RTC_DRV_MAX6900 is not set
901# CONFIG_RTC_DRV_RS5C372 is not set
902# CONFIG_RTC_DRV_ISL1208 is not set
903# CONFIG_RTC_DRV_X1205 is not set
904# CONFIG_RTC_DRV_PCF8563 is not set
905# CONFIG_RTC_DRV_PCF8583 is not set
906# CONFIG_RTC_DRV_M41T80 is not set
907
908#
909# SPI RTC drivers
910#
911
912#
913# Platform RTC drivers
914#
915# CONFIG_RTC_DRV_CMOS is not set
916# CONFIG_RTC_DRV_DS1553 is not set
917# CONFIG_RTC_DRV_STK17TA8 is not set
918# CONFIG_RTC_DRV_DS1742 is not set
919# CONFIG_RTC_DRV_M48T86 is not set
920# CONFIG_RTC_DRV_M48T59 is not set
921# CONFIG_RTC_DRV_V3020 is not set
922
923#
924# on-CPU RTC drivers
925#
926CONFIG_RTC_DRV_OMAP=y
927
928#
929# DMA Engine support
930#
931# CONFIG_DMA_ENGINE is not set
932
933#
934# DMA Clients
935#
936
937#
938# DMA Devices
939#
940
941#
942# CBUS support
943#
944# CONFIG_CBUS is not set
945
946#
947# File systems
948#
949CONFIG_EXT2_FS=y
950# CONFIG_EXT2_FS_XATTR is not set
951# CONFIG_EXT2_FS_XIP is not set
952CONFIG_EXT3_FS=y
953CONFIG_EXT3_FS_XATTR=y
954# CONFIG_EXT3_FS_POSIX_ACL is not set
955# CONFIG_EXT3_FS_SECURITY is not set
956# CONFIG_EXT4DEV_FS is not set
957CONFIG_JBD=y
958# CONFIG_JBD_DEBUG is not set
959CONFIG_FS_MBCACHE=y
960# CONFIG_REISERFS_FS is not set
961# CONFIG_JFS_FS is not set
962# CONFIG_FS_POSIX_ACL is not set
963# CONFIG_XFS_FS is not set
964# CONFIG_GFS2_FS is not set
965# CONFIG_OCFS2_FS is not set
966# CONFIG_MINIX_FS is not set
967# CONFIG_ROMFS_FS is not set
968CONFIG_INOTIFY=y
969CONFIG_INOTIFY_USER=y
970# CONFIG_QUOTA is not set
971CONFIG_DNOTIFY=y
972CONFIG_AUTOFS_FS=y
973CONFIG_AUTOFS4_FS=y
974# CONFIG_FUSE_FS is not set
975
976#
977# CD-ROM/DVD Filesystems
978#
979CONFIG_ISO9660_FS=y
980CONFIG_JOLIET=y
981# CONFIG_ZISOFS is not set
982# CONFIG_UDF_FS is not set
983
984#
985# DOS/FAT/NT Filesystems
986#
987CONFIG_FAT_FS=m
988CONFIG_MSDOS_FS=m
989CONFIG_VFAT_FS=m
990CONFIG_FAT_DEFAULT_CODEPAGE=437
991CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
992# CONFIG_NTFS_FS is not set
993
994#
995# Pseudo filesystems
996#
997CONFIG_PROC_FS=y
998CONFIG_PROC_SYSCTL=y
999CONFIG_SYSFS=y
1000# CONFIG_TMPFS is not set
1001# CONFIG_HUGETLB_PAGE is not set
1002CONFIG_RAMFS=y
1003# CONFIG_CONFIGFS_FS is not set
1004
1005#
1006# Miscellaneous filesystems
1007#
1008# CONFIG_ADFS_FS is not set
1009# CONFIG_AFFS_FS is not set
1010# CONFIG_HFS_FS is not set
1011# CONFIG_HFSPLUS_FS is not set
1012# CONFIG_BEFS_FS is not set
1013# CONFIG_BFS_FS is not set
1014# CONFIG_EFS_FS is not set
1015# CONFIG_CRAMFS is not set
1016# CONFIG_VXFS_FS is not set
1017# CONFIG_HPFS_FS is not set
1018# CONFIG_QNX4FS_FS is not set
1019# CONFIG_SYSV_FS is not set
1020# CONFIG_UFS_FS is not set
1021
1022#
1023# Network File Systems
1024#
1025CONFIG_NFS_FS=y
1026# CONFIG_NFS_V3 is not set
1027# CONFIG_NFS_V4 is not set
1028# CONFIG_NFS_DIRECTIO is not set
1029# CONFIG_NFSD is not set
1030# CONFIG_ROOT_NFS is not set
1031CONFIG_LOCKD=y
1032CONFIG_NFS_COMMON=y
1033CONFIG_SUNRPC=y
1034# CONFIG_SUNRPC_BIND34 is not set
1035# CONFIG_RPCSEC_GSS_KRB5 is not set
1036# CONFIG_RPCSEC_GSS_SPKM3 is not set
1037# CONFIG_SMB_FS is not set
1038# CONFIG_CIFS is not set
1039# CONFIG_NCP_FS is not set
1040# CONFIG_CODA_FS is not set
1041# CONFIG_AFS_FS is not set
1042
1043#
1044# Partition Types
1045#
1046CONFIG_PARTITION_ADVANCED=y
1047# CONFIG_ACORN_PARTITION is not set
1048# CONFIG_OSF_PARTITION is not set
1049# CONFIG_AMIGA_PARTITION is not set
1050# CONFIG_ATARI_PARTITION is not set
1051# CONFIG_MAC_PARTITION is not set
1052CONFIG_MSDOS_PARTITION=y
1053# CONFIG_BSD_DISKLABEL is not set
1054# CONFIG_MINIX_SUBPARTITION is not set
1055# CONFIG_SOLARIS_X86_PARTITION is not set
1056# CONFIG_UNIXWARE_DISKLABEL is not set
1057# CONFIG_LDM_PARTITION is not set
1058# CONFIG_SGI_PARTITION is not set
1059# CONFIG_ULTRIX_PARTITION is not set
1060# CONFIG_SUN_PARTITION is not set
1061# CONFIG_KARMA_PARTITION is not set
1062# CONFIG_EFI_PARTITION is not set
1063# CONFIG_SYSV68_PARTITION is not set
1064
1065#
1066# Native Language Support
1067#
1068CONFIG_NLS=y
1069CONFIG_NLS_DEFAULT="iso8859-1"
1070# CONFIG_NLS_CODEPAGE_437 is not set
1071# CONFIG_NLS_CODEPAGE_737 is not set
1072# CONFIG_NLS_CODEPAGE_775 is not set
1073# CONFIG_NLS_CODEPAGE_850 is not set
1074# CONFIG_NLS_CODEPAGE_852 is not set
1075# CONFIG_NLS_CODEPAGE_855 is not set
1076# CONFIG_NLS_CODEPAGE_857 is not set
1077# CONFIG_NLS_CODEPAGE_860 is not set
1078# CONFIG_NLS_CODEPAGE_861 is not set
1079# CONFIG_NLS_CODEPAGE_862 is not set
1080# CONFIG_NLS_CODEPAGE_863 is not set
1081# CONFIG_NLS_CODEPAGE_864 is not set
1082# CONFIG_NLS_CODEPAGE_865 is not set
1083# CONFIG_NLS_CODEPAGE_866 is not set
1084# CONFIG_NLS_CODEPAGE_869 is not set
1085# CONFIG_NLS_CODEPAGE_936 is not set
1086# CONFIG_NLS_CODEPAGE_950 is not set
1087# CONFIG_NLS_CODEPAGE_932 is not set
1088# CONFIG_NLS_CODEPAGE_949 is not set
1089# CONFIG_NLS_CODEPAGE_874 is not set
1090# CONFIG_NLS_ISO8859_8 is not set
1091# CONFIG_NLS_CODEPAGE_1250 is not set
1092# CONFIG_NLS_CODEPAGE_1251 is not set
1093# CONFIG_NLS_ASCII is not set
1094# CONFIG_NLS_ISO8859_1 is not set
1095# CONFIG_NLS_ISO8859_2 is not set
1096# CONFIG_NLS_ISO8859_3 is not set
1097# CONFIG_NLS_ISO8859_4 is not set
1098# CONFIG_NLS_ISO8859_5 is not set
1099# CONFIG_NLS_ISO8859_6 is not set
1100# CONFIG_NLS_ISO8859_7 is not set
1101# CONFIG_NLS_ISO8859_9 is not set
1102# CONFIG_NLS_ISO8859_13 is not set
1103# CONFIG_NLS_ISO8859_14 is not set
1104# CONFIG_NLS_ISO8859_15 is not set
1105# CONFIG_NLS_KOI8_R is not set
1106# CONFIG_NLS_KOI8_U is not set
1107# CONFIG_NLS_UTF8 is not set
1108
1109#
1110# Distributed Lock Manager
1111#
1112# CONFIG_DLM is not set
1113
1114#
1115# Profiling support
1116#
1117# CONFIG_PROFILING is not set
1118
1119#
1120# Kernel hacking
1121#
1122# CONFIG_PRINTK_TIME is not set
1123CONFIG_ENABLE_MUST_CHECK=y
1124CONFIG_MAGIC_SYSRQ=y
1125# CONFIG_UNUSED_SYMBOLS is not set
1126# CONFIG_DEBUG_FS is not set
1127# CONFIG_HEADERS_CHECK is not set
1128CONFIG_DEBUG_KERNEL=y
1129# CONFIG_DEBUG_SHIRQ is not set
1130CONFIG_DETECT_SOFTLOCKUP=y
1131CONFIG_SCHED_DEBUG=y
1132# CONFIG_SCHEDSTATS is not set
1133# CONFIG_TIMER_STATS is not set
1134# CONFIG_DEBUG_SLAB is not set
1135CONFIG_DEBUG_PREEMPT=y
1136# CONFIG_DEBUG_RT_MUTEXES is not set
1137# CONFIG_RT_MUTEX_TESTER is not set
1138# CONFIG_DEBUG_SPINLOCK is not set
1139# CONFIG_DEBUG_MUTEXES is not set
1140# CONFIG_DEBUG_LOCK_ALLOC is not set
1141# CONFIG_PROVE_LOCKING is not set
1142# CONFIG_LOCK_STAT is not set
1143# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1144# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1145# CONFIG_DEBUG_KOBJECT is not set
1146CONFIG_DEBUG_BUGVERBOSE=y
1147# CONFIG_DEBUG_INFO is not set
1148# CONFIG_DEBUG_VM is not set
1149# CONFIG_DEBUG_LIST is not set
1150CONFIG_FRAME_POINTER=y
1151CONFIG_FORCED_INLINING=y
1152# CONFIG_RCU_TORTURE_TEST is not set
1153# CONFIG_FAULT_INJECTION is not set
1154# CONFIG_DEBUG_USER is not set
1155# CONFIG_DEBUG_ERRORS is not set
1156# CONFIG_DEBUG_LL is not set
1157
1158#
1159# Security options
1160#
1161# CONFIG_KEYS is not set
1162# CONFIG_SECURITY is not set
1163# CONFIG_CRYPTO is not set
1164
1165#
1166# Library routines
1167#
1168CONFIG_BITREVERSE=y
1169# CONFIG_CRC_CCITT is not set
1170# CONFIG_CRC16 is not set
1171# CONFIG_CRC_ITU_T is not set
1172CONFIG_CRC32=y
1173# CONFIG_CRC7 is not set
1174# CONFIG_LIBCRC32C is not set
1175CONFIG_PLIST=y
1176CONFIG_HAS_IOMEM=y
1177CONFIG_HAS_IOPORT=y
1178CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/omap_generic_1710_defconfig b/arch/arm/configs/omap_generic_1710_defconfig
new file mode 100644
index 000000000000..0a00a708a4fc
--- /dev/null
+++ b/arch/arm/configs/omap_generic_1710_defconfig
@@ -0,0 +1,1088 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.23-rc6-omap1
4# Tue Sep 18 13:02:08 2007
5#
6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8CONFIG_GENERIC_GPIO=y
9CONFIG_GENERIC_TIME=y
10CONFIG_GENERIC_CLOCKEVENTS=y
11CONFIG_MMU=y
12# CONFIG_NO_IOPORT is not set
13CONFIG_GENERIC_HARDIRQS=y
14CONFIG_STACKTRACE_SUPPORT=y
15CONFIG_LOCKDEP_SUPPORT=y
16CONFIG_TRACE_IRQFLAGS_SUPPORT=y
17CONFIG_HARDIRQS_SW_RESEND=y
18CONFIG_GENERIC_IRQ_PROBE=y
19CONFIG_RWSEM_GENERIC_SPINLOCK=y
20# CONFIG_ARCH_HAS_ILOG2_U32 is not set
21# CONFIG_ARCH_HAS_ILOG2_U64 is not set
22CONFIG_GENERIC_HWEIGHT=y
23CONFIG_GENERIC_CALIBRATE_DELAY=y
24CONFIG_ZONE_DMA=y
25CONFIG_VECTORS_BASE=0xffff0000
26CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
27
28#
29# General setup
30#
31CONFIG_EXPERIMENTAL=y
32CONFIG_BROKEN_ON_SMP=y
33CONFIG_INIT_ENV_ARG_LIMIT=32
34CONFIG_LOCALVERSION=""
35CONFIG_LOCALVERSION_AUTO=y
36CONFIG_SWAP=y
37CONFIG_SYSVIPC=y
38CONFIG_SYSVIPC_SYSCTL=y
39# CONFIG_POSIX_MQUEUE is not set
40# CONFIG_BSD_PROCESS_ACCT is not set
41# CONFIG_TASKSTATS is not set
42# CONFIG_USER_NS is not set
43# CONFIG_AUDIT is not set
44# CONFIG_IKCONFIG is not set
45CONFIG_LOG_BUF_SHIFT=14
46CONFIG_SYSFS_DEPRECATED=y
47# CONFIG_RELAY is not set
48CONFIG_BLK_DEV_INITRD=y
49CONFIG_INITRAMFS_SOURCE=""
50CONFIG_CC_OPTIMIZE_FOR_SIZE=y
51CONFIG_SYSCTL=y
52# CONFIG_EMBEDDED is not set
53CONFIG_UID16=y
54CONFIG_SYSCTL_SYSCALL=y
55CONFIG_KALLSYMS=y
56# CONFIG_KALLSYMS_ALL is not set
57# CONFIG_KALLSYMS_EXTRA_PASS is not set
58CONFIG_HOTPLUG=y
59CONFIG_PRINTK=y
60CONFIG_BUG=y
61CONFIG_ELF_CORE=y
62CONFIG_BASE_FULL=y
63CONFIG_FUTEX=y
64CONFIG_ANON_INODES=y
65CONFIG_EPOLL=y
66CONFIG_SIGNALFD=y
67CONFIG_TIMERFD=y
68CONFIG_EVENTFD=y
69CONFIG_SHMEM=y
70CONFIG_VM_EVENT_COUNTERS=y
71CONFIG_SLUB_DEBUG=y
72# CONFIG_SLAB is not set
73CONFIG_SLUB=y
74# CONFIG_SLOB is not set
75CONFIG_RT_MUTEXES=y
76# CONFIG_TINY_SHMEM is not set
77CONFIG_BASE_SMALL=0
78# CONFIG_MODULES is not set
79CONFIG_BLOCK=y
80# CONFIG_LBD is not set
81# CONFIG_BLK_DEV_IO_TRACE is not set
82# CONFIG_LSF is not set
83# CONFIG_BLK_DEV_BSG is not set
84
85#
86# IO Schedulers
87#
88CONFIG_IOSCHED_NOOP=y
89CONFIG_IOSCHED_AS=y
90CONFIG_IOSCHED_DEADLINE=y
91CONFIG_IOSCHED_CFQ=y
92# CONFIG_DEFAULT_AS is not set
93# CONFIG_DEFAULT_DEADLINE is not set
94CONFIG_DEFAULT_CFQ=y
95# CONFIG_DEFAULT_NOOP is not set
96CONFIG_DEFAULT_IOSCHED="cfq"
97
98#
99# System Type
100#
101# CONFIG_ARCH_AAEC2000 is not set
102# CONFIG_ARCH_INTEGRATOR is not set
103# CONFIG_ARCH_REALVIEW is not set
104# CONFIG_ARCH_VERSATILE is not set
105# CONFIG_ARCH_AT91 is not set
106# CONFIG_ARCH_CLPS7500 is not set
107# CONFIG_ARCH_CLPS711X is not set
108# CONFIG_ARCH_CO285 is not set
109# CONFIG_ARCH_EBSA110 is not set
110# CONFIG_ARCH_EP93XX is not set
111# CONFIG_ARCH_FOOTBRIDGE is not set
112# CONFIG_ARCH_NETX is not set
113# CONFIG_ARCH_H720X is not set
114# CONFIG_ARCH_IMX is not set
115# CONFIG_ARCH_IOP13XX is not set
116# CONFIG_ARCH_IOP32X is not set
117# CONFIG_ARCH_IOP33X is not set
118# CONFIG_ARCH_IXP23XX is not set
119# CONFIG_ARCH_IXP2000 is not set
120# CONFIG_ARCH_IXP4XX is not set
121# CONFIG_ARCH_L7200 is not set
122# CONFIG_ARCH_KS8695 is not set
123# CONFIG_ARCH_NS9XXX is not set
124# CONFIG_ARCH_MXC is not set
125# CONFIG_ARCH_PNX4008 is not set
126# CONFIG_ARCH_PXA is not set
127# CONFIG_ARCH_RPC is not set
128# CONFIG_ARCH_SA1100 is not set
129# CONFIG_ARCH_S3C2410 is not set
130# CONFIG_ARCH_SHARK is not set
131# CONFIG_ARCH_LH7A40X is not set
132# CONFIG_ARCH_DAVINCI is not set
133CONFIG_ARCH_OMAP=y
134
135#
136# TI OMAP Implementations
137#
138CONFIG_ARCH_OMAP_OTG=y
139CONFIG_ARCH_OMAP1=y
140# CONFIG_ARCH_OMAP2 is not set
141# CONFIG_ARCH_OMAP3 is not set
142
143#
144# OMAP Feature Selections
145#
146# CONFIG_OMAP_RESET_CLOCKS is not set
147CONFIG_OMAP_BOOT_TAG=y
148# CONFIG_OMAP_BOOT_REASON is not set
149# CONFIG_OMAP_COMPONENT_VERSION is not set
150# CONFIG_OMAP_GPIO_SWITCH is not set
151# CONFIG_OMAP_MUX is not set
152# CONFIG_OMAP_STI is not set
153CONFIG_OMAP_MCBSP=y
154# CONFIG_OMAP_MMU_FWK is not set
155# CONFIG_OMAP_MBOX_FWK is not set
156CONFIG_OMAP_MPU_TIMER=y
157# CONFIG_OMAP_32K_TIMER is not set
158# CONFIG_OMAP_DM_TIMER is not set
159# CONFIG_OMAP_LL_DEBUG_UART1 is not set
160# CONFIG_OMAP_LL_DEBUG_UART2 is not set
161CONFIG_OMAP_LL_DEBUG_UART3=y
162# CONFIG_OMAP_DSP is not set
163
164#
165# OMAP Core Type
166#
167# CONFIG_ARCH_OMAP730 is not set
168# CONFIG_ARCH_OMAP15XX is not set
169CONFIG_ARCH_OMAP16XX=y
170
171#
172# OMAP Board Type
173#
174# CONFIG_MACH_OMAP_INNOVATOR is not set
175# CONFIG_MACH_OMAP_H2 is not set
176# CONFIG_MACH_OMAP_H3 is not set
177# CONFIG_MACH_OMAP_OSK is not set
178# CONFIG_MACH_NOKIA770 is not set
179CONFIG_MACH_OMAP_GENERIC=y
180
181#
182# OMAP CPU Speed
183#
184# CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER is not set
185# CONFIG_OMAP_ARM_216MHZ is not set
186CONFIG_OMAP_ARM_192MHZ=y
187# CONFIG_OMAP_ARM_168MHZ is not set
188# CONFIG_OMAP_ARM_120MHZ is not set
189# CONFIG_OMAP_ARM_60MHZ is not set
190# CONFIG_OMAP_ARM_30MHZ is not set
191# CONFIG_MACH_OMAP_APOLLON_PLUS is not set
192
193#
194# Boot options
195#
196
197#
198# Power management
199#
200
201#
202# Processor Type
203#
204CONFIG_CPU_32=y
205CONFIG_CPU_ARM926T=y
206CONFIG_CPU_32v5=y
207CONFIG_CPU_ABRT_EV5TJ=y
208CONFIG_CPU_PABRT_NOIFAR=y
209CONFIG_CPU_CACHE_VIVT=y
210CONFIG_CPU_COPY_V4WB=y
211CONFIG_CPU_TLB_V4WBI=y
212CONFIG_CPU_CP15=y
213CONFIG_CPU_CP15_MMU=y
214
215#
216# Processor Features
217#
218# CONFIG_ARM_THUMB is not set
219# CONFIG_CPU_ICACHE_DISABLE is not set
220# CONFIG_CPU_DCACHE_DISABLE is not set
221# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
222# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
223# CONFIG_OUTER_CACHE is not set
224
225#
226# Bus support
227#
228# CONFIG_PCI_SYSCALL is not set
229# CONFIG_ARCH_SUPPORTS_MSI is not set
230
231#
232# PCCARD (PCMCIA/CardBus) support
233#
234# CONFIG_PCCARD is not set
235
236#
237# Kernel Features
238#
239# CONFIG_TICK_ONESHOT is not set
240# CONFIG_NO_HZ is not set
241# CONFIG_HIGH_RES_TIMERS is not set
242# CONFIG_PREEMPT is not set
243CONFIG_HZ=100
244# CONFIG_AEABI is not set
245# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
246CONFIG_SELECT_MEMORY_MODEL=y
247CONFIG_FLATMEM_MANUAL=y
248# CONFIG_DISCONTIGMEM_MANUAL is not set
249# CONFIG_SPARSEMEM_MANUAL is not set
250CONFIG_FLATMEM=y
251CONFIG_FLAT_NODE_MEM_MAP=y
252# CONFIG_SPARSEMEM_STATIC is not set
253CONFIG_SPLIT_PTLOCK_CPUS=4096
254# CONFIG_RESOURCES_64BIT is not set
255CONFIG_ZONE_DMA_FLAG=1
256CONFIG_BOUNCE=y
257CONFIG_VIRT_TO_BUS=y
258# CONFIG_LEDS is not set
259CONFIG_ALIGNMENT_TRAP=y
260
261#
262# Boot options
263#
264CONFIG_ZBOOT_ROM_TEXT=0x0
265CONFIG_ZBOOT_ROM_BSS=0x0
266CONFIG_CMDLINE="mem=64M console=tty0 console=ttyS2,115200 root=0801"
267# CONFIG_XIP_KERNEL is not set
268# CONFIG_KEXEC is not set
269
270#
271# CPU Frequency scaling
272#
273# CONFIG_CPU_FREQ is not set
274
275#
276# Floating point emulation
277#
278
279#
280# At least one emulation must be selected
281#
282CONFIG_FPE_NWFPE=y
283# CONFIG_FPE_NWFPE_XP is not set
284# CONFIG_FPE_FASTFPE is not set
285# CONFIG_VFP is not set
286
287#
288# Userspace binary formats
289#
290CONFIG_BINFMT_ELF=y
291# CONFIG_BINFMT_AOUT is not set
292# CONFIG_BINFMT_MISC is not set
293CONFIG_ARTHUR=y
294
295#
296# Power management options
297#
298CONFIG_PM=y
299# CONFIG_PM_LEGACY is not set
300# CONFIG_PM_DEBUG is not set
301CONFIG_PM_SLEEP=y
302CONFIG_SUSPEND_UP_POSSIBLE=y
303CONFIG_SUSPEND=y
304# CONFIG_APM_EMULATION is not set
305
306#
307# Networking
308#
309CONFIG_NET=y
310
311#
312# Networking options
313#
314CONFIG_PACKET=y
315# CONFIG_PACKET_MMAP is not set
316CONFIG_UNIX=y
317CONFIG_XFRM=y
318# CONFIG_XFRM_USER is not set
319# CONFIG_XFRM_SUB_POLICY is not set
320# CONFIG_XFRM_MIGRATE is not set
321# CONFIG_NET_KEY is not set
322CONFIG_INET=y
323CONFIG_IP_MULTICAST=y
324# CONFIG_IP_ADVANCED_ROUTER is not set
325CONFIG_IP_FIB_HASH=y
326CONFIG_IP_PNP=y
327CONFIG_IP_PNP_DHCP=y
328CONFIG_IP_PNP_BOOTP=y
329# CONFIG_IP_PNP_RARP is not set
330# CONFIG_NET_IPIP is not set
331# CONFIG_NET_IPGRE is not set
332# CONFIG_IP_MROUTE is not set
333# CONFIG_ARPD is not set
334# CONFIG_SYN_COOKIES is not set
335# CONFIG_INET_AH is not set
336# CONFIG_INET_ESP is not set
337# CONFIG_INET_IPCOMP is not set
338# CONFIG_INET_XFRM_TUNNEL is not set
339# CONFIG_INET_TUNNEL is not set
340CONFIG_INET_XFRM_MODE_TRANSPORT=y
341CONFIG_INET_XFRM_MODE_TUNNEL=y
342CONFIG_INET_XFRM_MODE_BEET=y
343CONFIG_INET_DIAG=y
344CONFIG_INET_TCP_DIAG=y
345# CONFIG_TCP_CONG_ADVANCED is not set
346CONFIG_TCP_CONG_CUBIC=y
347CONFIG_DEFAULT_TCP_CONG="cubic"
348# CONFIG_TCP_MD5SIG is not set
349# CONFIG_IPV6 is not set
350# CONFIG_INET6_XFRM_TUNNEL is not set
351# CONFIG_INET6_TUNNEL is not set
352# CONFIG_NETLABEL is not set
353# CONFIG_NETWORK_SECMARK is not set
354# CONFIG_NETFILTER is not set
355# CONFIG_IP_DCCP is not set
356# CONFIG_IP_SCTP is not set
357# CONFIG_TIPC is not set
358# CONFIG_ATM is not set
359# CONFIG_BRIDGE is not set
360# CONFIG_VLAN_8021Q is not set
361# CONFIG_DECNET is not set
362# CONFIG_LLC2 is not set
363# CONFIG_IPX is not set
364# CONFIG_ATALK is not set
365# CONFIG_X25 is not set
366# CONFIG_LAPB is not set
367# CONFIG_ECONET is not set
368# CONFIG_WAN_ROUTER is not set
369
370#
371# QoS and/or fair queueing
372#
373# CONFIG_NET_SCHED is not set
374
375#
376# Network testing
377#
378# CONFIG_NET_PKTGEN is not set
379# CONFIG_HAMRADIO is not set
380# CONFIG_IRDA is not set
381# CONFIG_BT is not set
382# CONFIG_AF_RXRPC is not set
383
384#
385# Wireless
386#
387# CONFIG_CFG80211 is not set
388# CONFIG_WIRELESS_EXT is not set
389# CONFIG_MAC80211 is not set
390# CONFIG_IEEE80211 is not set
391# CONFIG_RFKILL is not set
392# CONFIG_NET_9P is not set
393
394#
395# Device Drivers
396#
397
398#
399# Generic Driver Options
400#
401CONFIG_STANDALONE=y
402CONFIG_PREVENT_FIRMWARE_BUILD=y
403# CONFIG_FW_LOADER is not set
404# CONFIG_DEBUG_DRIVER is not set
405# CONFIG_DEBUG_DEVRES is not set
406# CONFIG_SYS_HYPERVISOR is not set
407# CONFIG_CONNECTOR is not set
408# CONFIG_MTD is not set
409# CONFIG_PARPORT is not set
410CONFIG_BLK_DEV=y
411# CONFIG_BLK_DEV_COW_COMMON is not set
412CONFIG_BLK_DEV_LOOP=y
413# CONFIG_BLK_DEV_CRYPTOLOOP is not set
414# CONFIG_BLK_DEV_NBD is not set
415# CONFIG_BLK_DEV_UB is not set
416CONFIG_BLK_DEV_RAM=y
417CONFIG_BLK_DEV_RAM_COUNT=16
418CONFIG_BLK_DEV_RAM_SIZE=8192
419CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
420# CONFIG_CDROM_PKTCDVD is not set
421# CONFIG_ATA_OVER_ETH is not set
422
423#
424# SCSI device support
425#
426# CONFIG_RAID_ATTRS is not set
427CONFIG_SCSI=y
428CONFIG_SCSI_DMA=y
429# CONFIG_SCSI_TGT is not set
430# CONFIG_SCSI_NETLINK is not set
431CONFIG_SCSI_PROC_FS=y
432
433#
434# SCSI support type (disk, tape, CD-ROM)
435#
436CONFIG_BLK_DEV_SD=y
437# CONFIG_CHR_DEV_ST is not set
438# CONFIG_CHR_DEV_OSST is not set
439# CONFIG_BLK_DEV_SR is not set
440# CONFIG_CHR_DEV_SG is not set
441# CONFIG_CHR_DEV_SCH is not set
442
443#
444# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
445#
446# CONFIG_SCSI_MULTI_LUN is not set
447# CONFIG_SCSI_CONSTANTS is not set
448# CONFIG_SCSI_LOGGING is not set
449# CONFIG_SCSI_SCAN_ASYNC is not set
450
451#
452# SCSI Transports
453#
454# CONFIG_SCSI_SPI_ATTRS is not set
455# CONFIG_SCSI_FC_ATTRS is not set
456# CONFIG_SCSI_ISCSI_ATTRS is not set
457# CONFIG_SCSI_SAS_LIBSAS is not set
458CONFIG_SCSI_LOWLEVEL=y
459# CONFIG_ISCSI_TCP is not set
460# CONFIG_SCSI_DEBUG is not set
461# CONFIG_ATA is not set
462# CONFIG_MD is not set
463CONFIG_NETDEVICES=y
464# CONFIG_NETDEVICES_MULTIQUEUE is not set
465# CONFIG_DUMMY is not set
466# CONFIG_BONDING is not set
467# CONFIG_MACVLAN is not set
468# CONFIG_EQUALIZER is not set
469# CONFIG_TUN is not set
470# CONFIG_PHYLIB is not set
471CONFIG_NET_ETHERNET=y
472CONFIG_MII=y
473# CONFIG_AX88796 is not set
474# CONFIG_SMC91X is not set
475# CONFIG_DM9000 is not set
476CONFIG_NETDEV_1000=y
477CONFIG_NETDEV_10000=y
478
479#
480# Wireless LAN
481#
482# CONFIG_WLAN_PRE80211 is not set
483# CONFIG_WLAN_80211 is not set
484
485#
486# USB Network Adapters
487#
488# CONFIG_USB_CATC is not set
489# CONFIG_USB_KAWETH is not set
490# CONFIG_USB_PEGASUS is not set
491# CONFIG_USB_RTL8150 is not set
492CONFIG_USB_USBNET_MII=y
493CONFIG_USB_USBNET=y
494CONFIG_USB_NET_AX8817X=y
495CONFIG_USB_NET_CDCETHER=y
496# CONFIG_USB_NET_DM9601 is not set
497# CONFIG_USB_NET_GL620A is not set
498CONFIG_USB_NET_NET1080=y
499# CONFIG_USB_NET_PLUSB is not set
500# CONFIG_USB_NET_MCS7830 is not set
501# CONFIG_USB_NET_RNDIS_HOST is not set
502CONFIG_USB_NET_CDC_SUBSET=y
503CONFIG_USB_ALI_M5632=y
504# CONFIG_USB_AN2720 is not set
505# CONFIG_USB_BELKIN is not set
506# CONFIG_USB_ARMLINUX is not set
507# CONFIG_USB_EPSON2888 is not set
508# CONFIG_USB_KC2190 is not set
509CONFIG_USB_NET_ZAURUS=y
510# CONFIG_WAN is not set
511CONFIG_PPP=y
512# CONFIG_PPP_MULTILINK is not set
513# CONFIG_PPP_FILTER is not set
514# CONFIG_PPP_ASYNC is not set
515# CONFIG_PPP_SYNC_TTY is not set
516# CONFIG_PPP_DEFLATE is not set
517# CONFIG_PPP_BSDCOMP is not set
518# CONFIG_PPP_MPPE is not set
519# CONFIG_PPPOE is not set
520# CONFIG_PPPOL2TP is not set
521# CONFIG_SLIP is not set
522CONFIG_SLHC=y
523# CONFIG_SHAPER is not set
524# CONFIG_NETCONSOLE is not set
525# CONFIG_NETPOLL is not set
526# CONFIG_NET_POLL_CONTROLLER is not set
527# CONFIG_ISDN is not set
528
529#
530# Input device support
531#
532CONFIG_INPUT=y
533# CONFIG_INPUT_FF_MEMLESS is not set
534# CONFIG_INPUT_POLLDEV is not set
535
536#
537# Userland interfaces
538#
539CONFIG_INPUT_MOUSEDEV=y
540CONFIG_INPUT_MOUSEDEV_PSAUX=y
541CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
542CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
543# CONFIG_INPUT_JOYDEV is not set
544# CONFIG_INPUT_TSDEV is not set
545CONFIG_INPUT_EVDEV=y
546# CONFIG_INPUT_EVBUG is not set
547
548#
549# Input Device Drivers
550#
551CONFIG_INPUT_KEYBOARD=y
552CONFIG_KEYBOARD_ATKBD=y
553# CONFIG_KEYBOARD_SUNKBD is not set
554# CONFIG_KEYBOARD_LKKBD is not set
555# CONFIG_KEYBOARD_XTKBD is not set
556# CONFIG_KEYBOARD_NEWTON is not set
557# CONFIG_KEYBOARD_STOWAWAY is not set
558CONFIG_KEYBOARD_OMAP=y
559# CONFIG_KEYBOARD_GPIO is not set
560# CONFIG_INPUT_MOUSE is not set
561# CONFIG_INPUT_JOYSTICK is not set
562# CONFIG_INPUT_TABLET is not set
563# CONFIG_INPUT_TOUCHSCREEN is not set
564# CONFIG_INPUT_MISC is not set
565
566#
567# Hardware I/O ports
568#
569CONFIG_SERIO=y
570CONFIG_SERIO_SERPORT=y
571CONFIG_SERIO_LIBPS2=y
572# CONFIG_SERIO_RAW is not set
573# CONFIG_GAMEPORT is not set
574
575#
576# Character devices
577#
578CONFIG_VT=y
579CONFIG_VT_CONSOLE=y
580CONFIG_HW_CONSOLE=y
581# CONFIG_VT_HW_CONSOLE_BINDING is not set
582# CONFIG_SERIAL_NONSTANDARD is not set
583
584#
585# Serial drivers
586#
587CONFIG_SERIAL_8250=y
588CONFIG_SERIAL_8250_CONSOLE=y
589CONFIG_SERIAL_8250_NR_UARTS=4
590CONFIG_SERIAL_8250_RUNTIME_UARTS=4
591# CONFIG_SERIAL_8250_EXTENDED is not set
592
593#
594# Non-8250 serial port support
595#
596CONFIG_SERIAL_CORE=y
597CONFIG_SERIAL_CORE_CONSOLE=y
598CONFIG_UNIX98_PTYS=y
599CONFIG_LEGACY_PTYS=y
600CONFIG_LEGACY_PTY_COUNT=256
601# CONFIG_IPMI_HANDLER is not set
602# CONFIG_WATCHDOG is not set
603CONFIG_HW_RANDOM=y
604CONFIG_HW_RANDOM_OMAP=y
605# CONFIG_NVRAM is not set
606# CONFIG_R3964 is not set
607# CONFIG_RAW_DRIVER is not set
608# CONFIG_TCG_TPM is not set
609# CONFIG_I2C is not set
610
611#
612# SPI support
613#
614# CONFIG_SPI is not set
615# CONFIG_SPI_MASTER is not set
616# CONFIG_W1 is not set
617CONFIG_HWMON=y
618# CONFIG_HWMON_VID is not set
619# CONFIG_SENSORS_ABITUGURU is not set
620# CONFIG_SENSORS_ABITUGURU3 is not set
621# CONFIG_SENSORS_F71805F is not set
622# CONFIG_SENSORS_IT87 is not set
623# CONFIG_SENSORS_PC87360 is not set
624# CONFIG_SENSORS_PC87427 is not set
625# CONFIG_SENSORS_SMSC47M1 is not set
626# CONFIG_SENSORS_SMSC47B397 is not set
627# CONFIG_SENSORS_VT1211 is not set
628# CONFIG_SENSORS_W83627HF is not set
629# CONFIG_SENSORS_W83627EHF is not set
630# CONFIG_HWMON_DEBUG_CHIP is not set
631CONFIG_MISC_DEVICES=y
632# CONFIG_EEPROM_93CX6 is not set
633
634#
635# Multifunction device drivers
636#
637# CONFIG_MFD_SM501 is not set
638# CONFIG_NEW_LEDS is not set
639
640#
641# Multimedia devices
642#
643# CONFIG_VIDEO_DEV is not set
644# CONFIG_DVB_CORE is not set
645CONFIG_DAB=y
646# CONFIG_USB_DABUSB is not set
647
648#
649# Graphics support
650#
651# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
652
653#
654# Display device support
655#
656# CONFIG_DISPLAY_SUPPORT is not set
657# CONFIG_VGASTATE is not set
658CONFIG_VIDEO_OUTPUT_CONTROL=y
659# CONFIG_FB is not set
660
661#
662# Console display driver support
663#
664# CONFIG_VGA_CONSOLE is not set
665CONFIG_DUMMY_CONSOLE=y
666
667#
668# Sound
669#
670# CONFIG_SOUND is not set
671CONFIG_HID_SUPPORT=y
672CONFIG_HID=y
673CONFIG_HID_DEBUG=y
674
675#
676# USB Input Devices
677#
678CONFIG_USB_HID=y
679# CONFIG_USB_HIDINPUT_POWERBOOK is not set
680# CONFIG_HID_FF is not set
681# CONFIG_USB_HIDDEV is not set
682CONFIG_USB_SUPPORT=y
683CONFIG_USB_ARCH_HAS_HCD=y
684CONFIG_USB_ARCH_HAS_OHCI=y
685# CONFIG_USB_ARCH_HAS_EHCI is not set
686CONFIG_USB=y
687CONFIG_USB_DEBUG=y
688
689#
690# Miscellaneous USB options
691#
692CONFIG_USB_DEVICEFS=y
693CONFIG_USB_DEVICE_CLASS=y
694# CONFIG_USB_DYNAMIC_MINORS is not set
695# CONFIG_USB_SUSPEND is not set
696# CONFIG_USB_PERSIST is not set
697# CONFIG_USB_OTG is not set
698
699#
700# USB Host Controller Drivers
701#
702# CONFIG_USB_ISP116X_HCD is not set
703CONFIG_USB_OHCI_HCD=y
704# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
705# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
706CONFIG_USB_OHCI_LITTLE_ENDIAN=y
707# CONFIG_USB_SL811_HCD is not set
708# CONFIG_USB_R8A66597_HCD is not set
709# CONFIG_USB_MUSB_HDRC is not set
710
711#
712# USB Device Class drivers
713#
714# CONFIG_USB_ACM is not set
715# CONFIG_USB_PRINTER is not set
716
717#
718# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
719#
720
721#
722# may also be needed; see USB_STORAGE Help for more information
723#
724CONFIG_USB_STORAGE=y
725# CONFIG_USB_STORAGE_DEBUG is not set
726# CONFIG_USB_STORAGE_DATAFAB is not set
727# CONFIG_USB_STORAGE_FREECOM is not set
728# CONFIG_USB_STORAGE_DPCM is not set
729# CONFIG_USB_STORAGE_USBAT is not set
730# CONFIG_USB_STORAGE_SDDR09 is not set
731# CONFIG_USB_STORAGE_SDDR55 is not set
732# CONFIG_USB_STORAGE_JUMPSHOT is not set
733# CONFIG_USB_STORAGE_ALAUDA is not set
734# CONFIG_USB_STORAGE_KARMA is not set
735# CONFIG_USB_LIBUSUAL is not set
736
737#
738# USB Imaging devices
739#
740# CONFIG_USB_MDC800 is not set
741# CONFIG_USB_MICROTEK is not set
742CONFIG_USB_MON=y
743
744#
745# USB port drivers
746#
747
748#
749# USB Serial Converter support
750#
751# CONFIG_USB_SERIAL is not set
752
753#
754# USB Miscellaneous drivers
755#
756# CONFIG_USB_EMI62 is not set
757# CONFIG_USB_EMI26 is not set
758# CONFIG_USB_ADUTUX is not set
759# CONFIG_USB_AUERSWALD is not set
760# CONFIG_USB_RIO500 is not set
761# CONFIG_USB_LEGOTOWER is not set
762# CONFIG_USB_LCD is not set
763# CONFIG_USB_BERRY_CHARGE is not set
764# CONFIG_USB_LED is not set
765# CONFIG_USB_CYPRESS_CY7C63 is not set
766# CONFIG_USB_CYTHERM is not set
767# CONFIG_USB_PHIDGET is not set
768# CONFIG_USB_IDMOUSE is not set
769# CONFIG_USB_FTDI_ELAN is not set
770# CONFIG_USB_APPLEDISPLAY is not set
771# CONFIG_USB_LD is not set
772# CONFIG_USB_TRANCEVIBRATOR is not set
773# CONFIG_USB_IOWARRIOR is not set
774# CONFIG_USB_TEST is not set
775
776#
777# USB DSL modem support
778#
779
780#
781# USB Gadget Support
782#
783# CONFIG_USB_GADGET is not set
784CONFIG_MMC=y
785# CONFIG_MMC_DEBUG is not set
786# CONFIG_MMC_UNSAFE_RESUME is not set
787
788#
789# MMC/SD Card Drivers
790#
791CONFIG_MMC_BLOCK=y
792CONFIG_MMC_BLOCK_BOUNCE=y
793
794#
795# MMC/SD Host Controller Drivers
796#
797CONFIG_MMC_OMAP=y
798CONFIG_RTC_LIB=y
799# CONFIG_RTC_CLASS is not set
800
801#
802# DMA Engine support
803#
804# CONFIG_DMA_ENGINE is not set
805
806#
807# DMA Clients
808#
809
810#
811# DMA Devices
812#
813
814#
815# CBUS support
816#
817# CONFIG_CBUS is not set
818
819#
820# File systems
821#
822CONFIG_EXT2_FS=y
823# CONFIG_EXT2_FS_XATTR is not set
824# CONFIG_EXT2_FS_XIP is not set
825CONFIG_EXT3_FS=y
826CONFIG_EXT3_FS_XATTR=y
827# CONFIG_EXT3_FS_POSIX_ACL is not set
828# CONFIG_EXT3_FS_SECURITY is not set
829# CONFIG_EXT4DEV_FS is not set
830CONFIG_JBD=y
831# CONFIG_JBD_DEBUG is not set
832CONFIG_FS_MBCACHE=y
833# CONFIG_REISERFS_FS is not set
834# CONFIG_JFS_FS is not set
835# CONFIG_FS_POSIX_ACL is not set
836# CONFIG_XFS_FS is not set
837# CONFIG_GFS2_FS is not set
838# CONFIG_OCFS2_FS is not set
839# CONFIG_MINIX_FS is not set
840# CONFIG_ROMFS_FS is not set
841CONFIG_INOTIFY=y
842CONFIG_INOTIFY_USER=y
843# CONFIG_QUOTA is not set
844CONFIG_DNOTIFY=y
845# CONFIG_AUTOFS_FS is not set
846# CONFIG_AUTOFS4_FS is not set
847# CONFIG_FUSE_FS is not set
848
849#
850# CD-ROM/DVD Filesystems
851#
852# CONFIG_ISO9660_FS is not set
853# CONFIG_UDF_FS is not set
854
855#
856# DOS/FAT/NT Filesystems
857#
858# CONFIG_MSDOS_FS is not set
859# CONFIG_VFAT_FS is not set
860# CONFIG_NTFS_FS is not set
861
862#
863# Pseudo filesystems
864#
865CONFIG_PROC_FS=y
866CONFIG_PROC_SYSCTL=y
867CONFIG_SYSFS=y
868CONFIG_TMPFS=y
869# CONFIG_TMPFS_POSIX_ACL is not set
870# CONFIG_HUGETLB_PAGE is not set
871CONFIG_RAMFS=y
872# CONFIG_CONFIGFS_FS is not set
873
874#
875# Miscellaneous filesystems
876#
877# CONFIG_ADFS_FS is not set
878# CONFIG_AFFS_FS is not set
879# CONFIG_HFS_FS is not set
880# CONFIG_HFSPLUS_FS is not set
881# CONFIG_BEFS_FS is not set
882# CONFIG_BFS_FS is not set
883# CONFIG_EFS_FS is not set
884# CONFIG_CRAMFS is not set
885# CONFIG_VXFS_FS is not set
886# CONFIG_HPFS_FS is not set
887# CONFIG_QNX4FS_FS is not set
888# CONFIG_SYSV_FS is not set
889# CONFIG_UFS_FS is not set
890
891#
892# Network File Systems
893#
894CONFIG_NFS_FS=y
895CONFIG_NFS_V3=y
896# CONFIG_NFS_V3_ACL is not set
897CONFIG_NFS_V4=y
898# CONFIG_NFS_DIRECTIO is not set
899# CONFIG_NFSD is not set
900# CONFIG_ROOT_NFS is not set
901CONFIG_LOCKD=y
902CONFIG_LOCKD_V4=y
903CONFIG_NFS_COMMON=y
904CONFIG_SUNRPC=y
905CONFIG_SUNRPC_GSS=y
906# CONFIG_SUNRPC_BIND34 is not set
907CONFIG_RPCSEC_GSS_KRB5=y
908# CONFIG_RPCSEC_GSS_SPKM3 is not set
909# CONFIG_SMB_FS is not set
910# CONFIG_CIFS is not set
911# CONFIG_NCP_FS is not set
912# CONFIG_CODA_FS is not set
913# CONFIG_AFS_FS is not set
914
915#
916# Partition Types
917#
918CONFIG_PARTITION_ADVANCED=y
919# CONFIG_ACORN_PARTITION is not set
920# CONFIG_OSF_PARTITION is not set
921# CONFIG_AMIGA_PARTITION is not set
922# CONFIG_ATARI_PARTITION is not set
923# CONFIG_MAC_PARTITION is not set
924CONFIG_MSDOS_PARTITION=y
925# CONFIG_BSD_DISKLABEL is not set
926# CONFIG_MINIX_SUBPARTITION is not set
927# CONFIG_SOLARIS_X86_PARTITION is not set
928# CONFIG_UNIXWARE_DISKLABEL is not set
929# CONFIG_LDM_PARTITION is not set
930# CONFIG_SGI_PARTITION is not set
931# CONFIG_ULTRIX_PARTITION is not set
932# CONFIG_SUN_PARTITION is not set
933# CONFIG_KARMA_PARTITION is not set
934# CONFIG_EFI_PARTITION is not set
935# CONFIG_SYSV68_PARTITION is not set
936
937#
938# Native Language Support
939#
940CONFIG_NLS=y
941CONFIG_NLS_DEFAULT="iso8859-1"
942CONFIG_NLS_CODEPAGE_437=y
943# CONFIG_NLS_CODEPAGE_737 is not set
944# CONFIG_NLS_CODEPAGE_775 is not set
945# CONFIG_NLS_CODEPAGE_850 is not set
946CONFIG_NLS_CODEPAGE_852=y
947# CONFIG_NLS_CODEPAGE_855 is not set
948# CONFIG_NLS_CODEPAGE_857 is not set
949# CONFIG_NLS_CODEPAGE_860 is not set
950# CONFIG_NLS_CODEPAGE_861 is not set
951# CONFIG_NLS_CODEPAGE_862 is not set
952# CONFIG_NLS_CODEPAGE_863 is not set
953# CONFIG_NLS_CODEPAGE_864 is not set
954# CONFIG_NLS_CODEPAGE_865 is not set
955# CONFIG_NLS_CODEPAGE_866 is not set
956# CONFIG_NLS_CODEPAGE_869 is not set
957# CONFIG_NLS_CODEPAGE_936 is not set
958# CONFIG_NLS_CODEPAGE_950 is not set
959# CONFIG_NLS_CODEPAGE_932 is not set
960# CONFIG_NLS_CODEPAGE_949 is not set
961# CONFIG_NLS_CODEPAGE_874 is not set
962# CONFIG_NLS_ISO8859_8 is not set
963# CONFIG_NLS_CODEPAGE_1250 is not set
964# CONFIG_NLS_CODEPAGE_1251 is not set
965# CONFIG_NLS_ASCII is not set
966CONFIG_NLS_ISO8859_1=y
967# CONFIG_NLS_ISO8859_2 is not set
968# CONFIG_NLS_ISO8859_3 is not set
969# CONFIG_NLS_ISO8859_4 is not set
970# CONFIG_NLS_ISO8859_5 is not set
971# CONFIG_NLS_ISO8859_6 is not set
972# CONFIG_NLS_ISO8859_7 is not set
973# CONFIG_NLS_ISO8859_9 is not set
974# CONFIG_NLS_ISO8859_13 is not set
975# CONFIG_NLS_ISO8859_14 is not set
976CONFIG_NLS_ISO8859_15=y
977# CONFIG_NLS_KOI8_R is not set
978# CONFIG_NLS_KOI8_U is not set
979# CONFIG_NLS_UTF8 is not set
980
981#
982# Distributed Lock Manager
983#
984# CONFIG_DLM is not set
985
986#
987# Profiling support
988#
989# CONFIG_PROFILING is not set
990
991#
992# Kernel hacking
993#
994# CONFIG_PRINTK_TIME is not set
995CONFIG_ENABLE_MUST_CHECK=y
996CONFIG_MAGIC_SYSRQ=y
997# CONFIG_UNUSED_SYMBOLS is not set
998# CONFIG_DEBUG_FS is not set
999# CONFIG_HEADERS_CHECK is not set
1000CONFIG_DEBUG_KERNEL=y
1001# CONFIG_DEBUG_SHIRQ is not set
1002CONFIG_DETECT_SOFTLOCKUP=y
1003CONFIG_SCHED_DEBUG=y
1004# CONFIG_SCHEDSTATS is not set
1005# CONFIG_TIMER_STATS is not set
1006# CONFIG_SLUB_DEBUG_ON is not set
1007# CONFIG_DEBUG_RT_MUTEXES is not set
1008# CONFIG_RT_MUTEX_TESTER is not set
1009CONFIG_DEBUG_SPINLOCK=y
1010# CONFIG_DEBUG_MUTEXES is not set
1011# CONFIG_DEBUG_LOCK_ALLOC is not set
1012# CONFIG_PROVE_LOCKING is not set
1013# CONFIG_LOCK_STAT is not set
1014# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1015# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1016# CONFIG_DEBUG_KOBJECT is not set
1017CONFIG_DEBUG_BUGVERBOSE=y
1018# CONFIG_DEBUG_INFO is not set
1019# CONFIG_DEBUG_VM is not set
1020# CONFIG_DEBUG_LIST is not set
1021CONFIG_FRAME_POINTER=y
1022CONFIG_FORCED_INLINING=y
1023# CONFIG_FAULT_INJECTION is not set
1024# CONFIG_DEBUG_USER is not set
1025CONFIG_DEBUG_ERRORS=y
1026# CONFIG_DEBUG_LL is not set
1027
1028#
1029# Security options
1030#
1031# CONFIG_KEYS is not set
1032CONFIG_SECURITY=y
1033# CONFIG_SECURITY_NETWORK is not set
1034CONFIG_SECURITY_CAPABILITIES=y
1035# CONFIG_SECURITY_ROOTPLUG is not set
1036# CONFIG_SECURITY_LOWMEM is not set
1037CONFIG_CRYPTO=y
1038CONFIG_CRYPTO_ALGAPI=y
1039CONFIG_CRYPTO_BLKCIPHER=y
1040CONFIG_CRYPTO_MANAGER=y
1041# CONFIG_CRYPTO_HMAC is not set
1042# CONFIG_CRYPTO_XCBC is not set
1043# CONFIG_CRYPTO_NULL is not set
1044# CONFIG_CRYPTO_MD4 is not set
1045CONFIG_CRYPTO_MD5=y
1046# CONFIG_CRYPTO_SHA1 is not set
1047# CONFIG_CRYPTO_SHA256 is not set
1048# CONFIG_CRYPTO_SHA512 is not set
1049# CONFIG_CRYPTO_WP512 is not set
1050# CONFIG_CRYPTO_TGR192 is not set
1051# CONFIG_CRYPTO_GF128MUL is not set
1052CONFIG_CRYPTO_ECB=y
1053CONFIG_CRYPTO_CBC=y
1054CONFIG_CRYPTO_PCBC=y
1055# CONFIG_CRYPTO_LRW is not set
1056# CONFIG_CRYPTO_CRYPTD is not set
1057CONFIG_CRYPTO_DES=y
1058# CONFIG_CRYPTO_FCRYPT is not set
1059# CONFIG_CRYPTO_BLOWFISH is not set
1060# CONFIG_CRYPTO_TWOFISH is not set
1061# CONFIG_CRYPTO_SERPENT is not set
1062# CONFIG_CRYPTO_AES is not set
1063# CONFIG_CRYPTO_CAST5 is not set
1064# CONFIG_CRYPTO_CAST6 is not set
1065# CONFIG_CRYPTO_TEA is not set
1066# CONFIG_CRYPTO_ARC4 is not set
1067# CONFIG_CRYPTO_KHAZAD is not set
1068# CONFIG_CRYPTO_ANUBIS is not set
1069# CONFIG_CRYPTO_DEFLATE is not set
1070# CONFIG_CRYPTO_MICHAEL_MIC is not set
1071# CONFIG_CRYPTO_CRC32C is not set
1072# CONFIG_CRYPTO_CAMELLIA is not set
1073CONFIG_CRYPTO_HW=y
1074
1075#
1076# Library routines
1077#
1078CONFIG_BITREVERSE=y
1079# CONFIG_CRC_CCITT is not set
1080# CONFIG_CRC16 is not set
1081# CONFIG_CRC_ITU_T is not set
1082CONFIG_CRC32=y
1083# CONFIG_CRC7 is not set
1084# CONFIG_LIBCRC32C is not set
1085CONFIG_PLIST=y
1086CONFIG_HAS_IOMEM=y
1087CONFIG_HAS_IOPORT=y
1088CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/omap_generic_2420_defconfig b/arch/arm/configs/omap_generic_2420_defconfig
new file mode 100644
index 000000000000..cf4073b47aaa
--- /dev/null
+++ b/arch/arm/configs/omap_generic_2420_defconfig
@@ -0,0 +1,655 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.23-rc6-omap1
4# Tue Sep 18 11:44:48 2007
5#
6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8CONFIG_GENERIC_GPIO=y
9CONFIG_GENERIC_TIME=y
10CONFIG_GENERIC_CLOCKEVENTS=y
11CONFIG_MMU=y
12# CONFIG_NO_IOPORT is not set
13CONFIG_GENERIC_HARDIRQS=y
14CONFIG_STACKTRACE_SUPPORT=y
15CONFIG_LOCKDEP_SUPPORT=y
16CONFIG_TRACE_IRQFLAGS_SUPPORT=y
17CONFIG_HARDIRQS_SW_RESEND=y
18CONFIG_GENERIC_IRQ_PROBE=y
19CONFIG_RWSEM_GENERIC_SPINLOCK=y
20# CONFIG_ARCH_HAS_ILOG2_U32 is not set
21# CONFIG_ARCH_HAS_ILOG2_U64 is not set
22CONFIG_GENERIC_HWEIGHT=y
23CONFIG_GENERIC_CALIBRATE_DELAY=y
24CONFIG_ZONE_DMA=y
25CONFIG_VECTORS_BASE=0xffff0000
26CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
27
28#
29# General setup
30#
31CONFIG_EXPERIMENTAL=y
32CONFIG_BROKEN_ON_SMP=y
33CONFIG_INIT_ENV_ARG_LIMIT=32
34CONFIG_LOCALVERSION=""
35CONFIG_LOCALVERSION_AUTO=y
36CONFIG_SWAP=y
37CONFIG_SYSVIPC=y
38CONFIG_SYSVIPC_SYSCTL=y
39# CONFIG_BSD_PROCESS_ACCT is not set
40# CONFIG_USER_NS is not set
41# CONFIG_IKCONFIG is not set
42CONFIG_LOG_BUF_SHIFT=14
43CONFIG_SYSFS_DEPRECATED=y
44# CONFIG_RELAY is not set
45CONFIG_BLK_DEV_INITRD=y
46CONFIG_INITRAMFS_SOURCE=""
47CONFIG_CC_OPTIMIZE_FOR_SIZE=y
48CONFIG_SYSCTL=y
49# CONFIG_EMBEDDED is not set
50CONFIG_UID16=y
51CONFIG_SYSCTL_SYSCALL=y
52CONFIG_KALLSYMS=y
53# CONFIG_KALLSYMS_ALL is not set
54# CONFIG_KALLSYMS_EXTRA_PASS is not set
55CONFIG_HOTPLUG=y
56CONFIG_PRINTK=y
57CONFIG_BUG=y
58CONFIG_ELF_CORE=y
59CONFIG_BASE_FULL=y
60CONFIG_FUTEX=y
61CONFIG_ANON_INODES=y
62CONFIG_EPOLL=y
63CONFIG_SIGNALFD=y
64CONFIG_TIMERFD=y
65CONFIG_EVENTFD=y
66CONFIG_SHMEM=y
67CONFIG_VM_EVENT_COUNTERS=y
68CONFIG_SLUB_DEBUG=y
69# CONFIG_SLAB is not set
70CONFIG_SLUB=y
71# CONFIG_SLOB is not set
72CONFIG_RT_MUTEXES=y
73# CONFIG_TINY_SHMEM is not set
74CONFIG_BASE_SMALL=0
75CONFIG_MODULES=y
76CONFIG_MODULE_UNLOAD=y
77# CONFIG_MODULE_FORCE_UNLOAD is not set
78# CONFIG_MODVERSIONS is not set
79# CONFIG_MODULE_SRCVERSION_ALL is not set
80# CONFIG_KMOD is not set
81CONFIG_BLOCK=y
82# CONFIG_LBD is not set
83# CONFIG_BLK_DEV_IO_TRACE is not set
84# CONFIG_LSF is not set
85# CONFIG_BLK_DEV_BSG is not set
86
87#
88# IO Schedulers
89#
90CONFIG_IOSCHED_NOOP=y
91CONFIG_IOSCHED_AS=y
92CONFIG_IOSCHED_DEADLINE=y
93CONFIG_IOSCHED_CFQ=y
94# CONFIG_DEFAULT_AS is not set
95# CONFIG_DEFAULT_DEADLINE is not set
96CONFIG_DEFAULT_CFQ=y
97# CONFIG_DEFAULT_NOOP is not set
98CONFIG_DEFAULT_IOSCHED="cfq"
99
100#
101# System Type
102#
103# CONFIG_ARCH_AAEC2000 is not set
104# CONFIG_ARCH_INTEGRATOR is not set
105# CONFIG_ARCH_REALVIEW is not set
106# CONFIG_ARCH_VERSATILE is not set
107# CONFIG_ARCH_AT91 is not set
108# CONFIG_ARCH_CLPS7500 is not set
109# CONFIG_ARCH_CLPS711X is not set
110# CONFIG_ARCH_CO285 is not set
111# CONFIG_ARCH_EBSA110 is not set
112# CONFIG_ARCH_EP93XX is not set
113# CONFIG_ARCH_FOOTBRIDGE is not set
114# CONFIG_ARCH_NETX is not set
115# CONFIG_ARCH_H720X is not set
116# CONFIG_ARCH_IMX is not set
117# CONFIG_ARCH_IOP13XX is not set
118# CONFIG_ARCH_IOP32X is not set
119# CONFIG_ARCH_IOP33X is not set
120# CONFIG_ARCH_IXP23XX is not set
121# CONFIG_ARCH_IXP2000 is not set
122# CONFIG_ARCH_IXP4XX is not set
123# CONFIG_ARCH_L7200 is not set
124# CONFIG_ARCH_KS8695 is not set
125# CONFIG_ARCH_NS9XXX is not set
126# CONFIG_ARCH_MXC is not set
127# CONFIG_ARCH_PNX4008 is not set
128# CONFIG_ARCH_PXA is not set
129# CONFIG_ARCH_RPC is not set
130# CONFIG_ARCH_SA1100 is not set
131# CONFIG_ARCH_S3C2410 is not set
132# CONFIG_ARCH_SHARK is not set
133# CONFIG_ARCH_LH7A40X is not set
134# CONFIG_ARCH_DAVINCI is not set
135CONFIG_ARCH_OMAP=y
136
137#
138# TI OMAP Implementations
139#
140CONFIG_ARCH_OMAP_OTG=y
141# CONFIG_ARCH_OMAP1 is not set
142CONFIG_ARCH_OMAP2=y
143# CONFIG_ARCH_OMAP3 is not set
144
145#
146# OMAP Feature Selections
147#
148# CONFIG_OMAP_RESET_CLOCKS is not set
149CONFIG_OMAP_BOOT_TAG=y
150# CONFIG_OMAP_BOOT_REASON is not set
151# CONFIG_OMAP_COMPONENT_VERSION is not set
152# CONFIG_OMAP_GPIO_SWITCH is not set
153# CONFIG_OMAP_MUX is not set
154# CONFIG_OMAP_STI is not set
155CONFIG_OMAP_MCBSP=y
156# CONFIG_OMAP_MMU_FWK is not set
157# CONFIG_OMAP_MBOX_FWK is not set
158CONFIG_OMAP_MPU_TIMER=y
159# CONFIG_OMAP_32K_TIMER is not set
160CONFIG_OMAP_DM_TIMER=y
161# CONFIG_OMAP_LL_DEBUG_UART1 is not set
162# CONFIG_OMAP_LL_DEBUG_UART2 is not set
163CONFIG_OMAP_LL_DEBUG_UART3=y
164# CONFIG_OMAP_DSP is not set
165CONFIG_MACH_OMAP_GENERIC=y
166
167#
168# OMAP Core Type
169#
170CONFIG_ARCH_OMAP24XX=y
171CONFIG_ARCH_OMAP2420=y
172# CONFIG_ARCH_OMAP2430 is not set
173
174#
175# OMAP Board Type
176#
177# CONFIG_MACH_NOKIA_N800 is not set
178# CONFIG_MACH_OMAP_H4 is not set
179# CONFIG_MACH_OMAP_APOLLON is not set
180# CONFIG_MACH_OMAP_APOLLON_PLUS is not set
181# CONFIG_MACH_OMAP_2430SDP is not set
182
183#
184# Boot options
185#
186
187#
188# Power management
189#
190
191#
192# Processor Type
193#
194CONFIG_CPU_32=y
195CONFIG_CPU_V6=y
196# CONFIG_CPU_32v6K is not set
197CONFIG_CPU_32v6=y
198CONFIG_CPU_ABRT_EV6=y
199CONFIG_CPU_PABRT_NOIFAR=y
200CONFIG_CPU_CACHE_V6=y
201CONFIG_CPU_CACHE_VIPT=y
202CONFIG_CPU_COPY_V6=y
203CONFIG_CPU_TLB_V6=y
204CONFIG_CPU_HAS_ASID=y
205CONFIG_CPU_CP15=y
206CONFIG_CPU_CP15_MMU=y
207
208#
209# Processor Features
210#
211CONFIG_ARM_THUMB=y
212# CONFIG_CPU_ICACHE_DISABLE is not set
213# CONFIG_CPU_DCACHE_DISABLE is not set
214# CONFIG_CPU_BPREDICT_DISABLE is not set
215# CONFIG_OUTER_CACHE is not set
216
217#
218# Bus support
219#
220# CONFIG_PCI_SYSCALL is not set
221# CONFIG_ARCH_SUPPORTS_MSI is not set
222
223#
224# PCCARD (PCMCIA/CardBus) support
225#
226# CONFIG_PCCARD is not set
227
228#
229# Kernel Features
230#
231# CONFIG_TICK_ONESHOT is not set
232# CONFIG_NO_HZ is not set
233# CONFIG_HIGH_RES_TIMERS is not set
234# CONFIG_PREEMPT is not set
235CONFIG_HZ=100
236# CONFIG_AEABI is not set
237# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
238CONFIG_SELECT_MEMORY_MODEL=y
239CONFIG_FLATMEM_MANUAL=y
240# CONFIG_DISCONTIGMEM_MANUAL is not set
241# CONFIG_SPARSEMEM_MANUAL is not set
242CONFIG_FLATMEM=y
243CONFIG_FLAT_NODE_MEM_MAP=y
244# CONFIG_SPARSEMEM_STATIC is not set
245CONFIG_SPLIT_PTLOCK_CPUS=4
246# CONFIG_RESOURCES_64BIT is not set
247CONFIG_ZONE_DMA_FLAG=1
248CONFIG_BOUNCE=y
249CONFIG_VIRT_TO_BUS=y
250CONFIG_LEDS=y
251CONFIG_ALIGNMENT_TRAP=y
252
253#
254# Boot options
255#
256CONFIG_ZBOOT_ROM_TEXT=0x10C08000
257CONFIG_ZBOOT_ROM_BSS=0x10200000
258# CONFIG_ZBOOT_ROM is not set
259CONFIG_CMDLINE=""
260# CONFIG_XIP_KERNEL is not set
261# CONFIG_KEXEC is not set
262
263#
264# CPU Frequency scaling
265#
266# CONFIG_CPU_FREQ is not set
267
268#
269# Floating point emulation
270#
271
272#
273# At least one emulation must be selected
274#
275CONFIG_FPE_NWFPE=y
276# CONFIG_FPE_NWFPE_XP is not set
277# CONFIG_FPE_FASTFPE is not set
278# CONFIG_VFP is not set
279
280#
281# Userspace binary formats
282#
283CONFIG_BINFMT_ELF=y
284# CONFIG_BINFMT_AOUT is not set
285# CONFIG_BINFMT_MISC is not set
286# CONFIG_ARTHUR is not set
287
288#
289# Power management options
290#
291# CONFIG_PM is not set
292CONFIG_SUSPEND_UP_POSSIBLE=y
293
294#
295# Networking
296#
297# CONFIG_NET is not set
298
299#
300# Device Drivers
301#
302
303#
304# Generic Driver Options
305#
306CONFIG_STANDALONE=y
307CONFIG_PREVENT_FIRMWARE_BUILD=y
308CONFIG_FW_LOADER=y
309# CONFIG_DEBUG_DRIVER is not set
310# CONFIG_DEBUG_DEVRES is not set
311# CONFIG_SYS_HYPERVISOR is not set
312# CONFIG_MTD is not set
313# CONFIG_PARPORT is not set
314CONFIG_BLK_DEV=y
315# CONFIG_BLK_DEV_COW_COMMON is not set
316# CONFIG_BLK_DEV_LOOP is not set
317CONFIG_BLK_DEV_RAM=y
318CONFIG_BLK_DEV_RAM_COUNT=16
319CONFIG_BLK_DEV_RAM_SIZE=4096
320CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
321# CONFIG_CDROM_PKTCDVD is not set
322
323#
324# SCSI device support
325#
326# CONFIG_RAID_ATTRS is not set
327# CONFIG_SCSI is not set
328# CONFIG_SCSI_DMA is not set
329# CONFIG_SCSI_NETLINK is not set
330# CONFIG_ATA is not set
331# CONFIG_MD is not set
332
333#
334# Input device support
335#
336CONFIG_INPUT=y
337# CONFIG_INPUT_FF_MEMLESS is not set
338# CONFIG_INPUT_POLLDEV is not set
339
340#
341# Userland interfaces
342#
343CONFIG_INPUT_MOUSEDEV=y
344CONFIG_INPUT_MOUSEDEV_PSAUX=y
345CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
346CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
347# CONFIG_INPUT_JOYDEV is not set
348# CONFIG_INPUT_TSDEV is not set
349CONFIG_INPUT_EVDEV=y
350# CONFIG_INPUT_EVBUG is not set
351
352#
353# Input Device Drivers
354#
355# CONFIG_INPUT_KEYBOARD is not set
356# CONFIG_INPUT_MOUSE is not set
357# CONFIG_INPUT_JOYSTICK is not set
358# CONFIG_INPUT_TABLET is not set
359# CONFIG_INPUT_TOUCHSCREEN is not set
360# CONFIG_INPUT_MISC is not set
361
362#
363# Hardware I/O ports
364#
365CONFIG_SERIO=y
366CONFIG_SERIO_SERPORT=y
367# CONFIG_SERIO_RAW is not set
368# CONFIG_GAMEPORT is not set
369
370#
371# Character devices
372#
373CONFIG_VT=y
374CONFIG_VT_CONSOLE=y
375CONFIG_HW_CONSOLE=y
376# CONFIG_VT_HW_CONSOLE_BINDING is not set
377# CONFIG_SERIAL_NONSTANDARD is not set
378
379#
380# Serial drivers
381#
382CONFIG_SERIAL_8250=y
383CONFIG_SERIAL_8250_CONSOLE=y
384CONFIG_SERIAL_8250_NR_UARTS=4
385CONFIG_SERIAL_8250_RUNTIME_UARTS=4
386# CONFIG_SERIAL_8250_EXTENDED is not set
387
388#
389# Non-8250 serial port support
390#
391CONFIG_SERIAL_CORE=y
392CONFIG_SERIAL_CORE_CONSOLE=y
393CONFIG_UNIX98_PTYS=y
394# CONFIG_LEGACY_PTYS is not set
395# CONFIG_IPMI_HANDLER is not set
396CONFIG_WATCHDOG=y
397CONFIG_WATCHDOG_NOWAYOUT=y
398
399#
400# Watchdog Device Drivers
401#
402# CONFIG_SOFT_WATCHDOG is not set
403# CONFIG_OMAP_WATCHDOG is not set
404CONFIG_HW_RANDOM=m
405CONFIG_HW_RANDOM_OMAP=m
406# CONFIG_NVRAM is not set
407# CONFIG_R3964 is not set
408# CONFIG_RAW_DRIVER is not set
409# CONFIG_TCG_TPM is not set
410# CONFIG_I2C is not set
411
412#
413# SPI support
414#
415# CONFIG_SPI is not set
416# CONFIG_SPI_MASTER is not set
417# CONFIG_W1 is not set
418CONFIG_HWMON=y
419# CONFIG_HWMON_VID is not set
420# CONFIG_SENSORS_ABITUGURU is not set
421# CONFIG_SENSORS_ABITUGURU3 is not set
422# CONFIG_SENSORS_F71805F is not set
423# CONFIG_SENSORS_IT87 is not set
424# CONFIG_SENSORS_PC87360 is not set
425# CONFIG_SENSORS_PC87427 is not set
426# CONFIG_SENSORS_SMSC47M1 is not set
427# CONFIG_SENSORS_SMSC47B397 is not set
428# CONFIG_SENSORS_VT1211 is not set
429# CONFIG_SENSORS_W83627HF is not set
430# CONFIG_SENSORS_W83627EHF is not set
431# CONFIG_HWMON_DEBUG_CHIP is not set
432CONFIG_MISC_DEVICES=y
433# CONFIG_EEPROM_93CX6 is not set
434
435#
436# Multifunction device drivers
437#
438# CONFIG_MFD_SM501 is not set
439# CONFIG_NEW_LEDS is not set
440
441#
442# Multimedia devices
443#
444# CONFIG_VIDEO_DEV is not set
445CONFIG_DAB=y
446
447#
448# Graphics support
449#
450# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
451
452#
453# Display device support
454#
455# CONFIG_DISPLAY_SUPPORT is not set
456# CONFIG_VGASTATE is not set
457CONFIG_VIDEO_OUTPUT_CONTROL=m
458# CONFIG_FB is not set
459
460#
461# Console display driver support
462#
463# CONFIG_VGA_CONSOLE is not set
464CONFIG_DUMMY_CONSOLE=y
465
466#
467# Sound
468#
469# CONFIG_SOUND is not set
470CONFIG_HID_SUPPORT=y
471CONFIG_HID=y
472CONFIG_HID_DEBUG=y
473CONFIG_USB_SUPPORT=y
474CONFIG_USB_ARCH_HAS_HCD=y
475CONFIG_USB_ARCH_HAS_OHCI=y
476# CONFIG_USB_ARCH_HAS_EHCI is not set
477# CONFIG_USB is not set
478
479#
480# Enable Host or Gadget support to see Inventra options
481#
482
483#
484# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
485#
486
487#
488# USB Gadget Support
489#
490# CONFIG_USB_GADGET is not set
491# CONFIG_MMC is not set
492CONFIG_RTC_LIB=y
493# CONFIG_RTC_CLASS is not set
494
495#
496# DMA Engine support
497#
498# CONFIG_DMA_ENGINE is not set
499
500#
501# DMA Clients
502#
503
504#
505# DMA Devices
506#
507
508#
509# CBUS support
510#
511# CONFIG_CBUS is not set
512
513#
514# File systems
515#
516CONFIG_EXT2_FS=y
517CONFIG_EXT2_FS_XATTR=y
518# CONFIG_EXT2_FS_POSIX_ACL is not set
519# CONFIG_EXT2_FS_SECURITY is not set
520# CONFIG_EXT2_FS_XIP is not set
521# CONFIG_EXT3_FS is not set
522# CONFIG_EXT4DEV_FS is not set
523CONFIG_FS_MBCACHE=y
524# CONFIG_REISERFS_FS is not set
525# CONFIG_JFS_FS is not set
526# CONFIG_FS_POSIX_ACL is not set
527# CONFIG_XFS_FS is not set
528# CONFIG_GFS2_FS is not set
529# CONFIG_MINIX_FS is not set
530CONFIG_ROMFS_FS=y
531CONFIG_INOTIFY=y
532CONFIG_INOTIFY_USER=y
533# CONFIG_QUOTA is not set
534CONFIG_DNOTIFY=y
535# CONFIG_AUTOFS_FS is not set
536# CONFIG_AUTOFS4_FS is not set
537# CONFIG_FUSE_FS is not set
538
539#
540# CD-ROM/DVD Filesystems
541#
542# CONFIG_ISO9660_FS is not set
543# CONFIG_UDF_FS is not set
544
545#
546# DOS/FAT/NT Filesystems
547#
548# CONFIG_MSDOS_FS is not set
549# CONFIG_VFAT_FS is not set
550# CONFIG_NTFS_FS is not set
551
552#
553# Pseudo filesystems
554#
555CONFIG_PROC_FS=y
556CONFIG_PROC_SYSCTL=y
557CONFIG_SYSFS=y
558# CONFIG_TMPFS is not set
559# CONFIG_HUGETLB_PAGE is not set
560CONFIG_RAMFS=y
561# CONFIG_CONFIGFS_FS is not set
562
563#
564# Miscellaneous filesystems
565#
566# CONFIG_ADFS_FS is not set
567# CONFIG_AFFS_FS is not set
568# CONFIG_HFS_FS is not set
569# CONFIG_HFSPLUS_FS is not set
570# CONFIG_BEFS_FS is not set
571# CONFIG_BFS_FS is not set
572# CONFIG_EFS_FS is not set
573# CONFIG_CRAMFS is not set
574# CONFIG_VXFS_FS is not set
575# CONFIG_HPFS_FS is not set
576# CONFIG_QNX4FS_FS is not set
577# CONFIG_SYSV_FS is not set
578# CONFIG_UFS_FS is not set
579
580#
581# Partition Types
582#
583# CONFIG_PARTITION_ADVANCED is not set
584CONFIG_MSDOS_PARTITION=y
585
586#
587# Native Language Support
588#
589# CONFIG_NLS is not set
590
591#
592# Profiling support
593#
594# CONFIG_PROFILING is not set
595
596#
597# Kernel hacking
598#
599# CONFIG_PRINTK_TIME is not set
600CONFIG_ENABLE_MUST_CHECK=y
601# CONFIG_MAGIC_SYSRQ is not set
602# CONFIG_UNUSED_SYMBOLS is not set
603# CONFIG_DEBUG_FS is not set
604# CONFIG_HEADERS_CHECK is not set
605CONFIG_DEBUG_KERNEL=y
606# CONFIG_DEBUG_SHIRQ is not set
607CONFIG_DETECT_SOFTLOCKUP=y
608CONFIG_SCHED_DEBUG=y
609# CONFIG_SCHEDSTATS is not set
610# CONFIG_TIMER_STATS is not set
611# CONFIG_SLUB_DEBUG_ON is not set
612# CONFIG_DEBUG_RT_MUTEXES is not set
613# CONFIG_RT_MUTEX_TESTER is not set
614# CONFIG_DEBUG_SPINLOCK is not set
615# CONFIG_DEBUG_MUTEXES is not set
616# CONFIG_DEBUG_LOCK_ALLOC is not set
617# CONFIG_PROVE_LOCKING is not set
618# CONFIG_LOCK_STAT is not set
619# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
620# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
621# CONFIG_DEBUG_KOBJECT is not set
622CONFIG_DEBUG_BUGVERBOSE=y
623CONFIG_DEBUG_INFO=y
624# CONFIG_DEBUG_VM is not set
625# CONFIG_DEBUG_LIST is not set
626CONFIG_FRAME_POINTER=y
627CONFIG_FORCED_INLINING=y
628# CONFIG_RCU_TORTURE_TEST is not set
629# CONFIG_FAULT_INJECTION is not set
630CONFIG_DEBUG_USER=y
631CONFIG_DEBUG_ERRORS=y
632CONFIG_DEBUG_LL=y
633# CONFIG_DEBUG_ICEDCC is not set
634
635#
636# Security options
637#
638# CONFIG_KEYS is not set
639# CONFIG_SECURITY is not set
640# CONFIG_CRYPTO is not set
641
642#
643# Library routines
644#
645CONFIG_BITREVERSE=y
646CONFIG_CRC_CCITT=y
647# CONFIG_CRC16 is not set
648# CONFIG_CRC_ITU_T is not set
649CONFIG_CRC32=y
650# CONFIG_CRC7 is not set
651# CONFIG_LIBCRC32C is not set
652CONFIG_PLIST=y
653CONFIG_HAS_IOMEM=y
654CONFIG_HAS_IOPORT=y
655CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/omap_h2_1610_defconfig b/arch/arm/configs/omap_h2_1610_defconfig
index 323c1deeb953..c03507202f3c 100644
--- a/arch/arm/configs/omap_h2_1610_defconfig
+++ b/arch/arm/configs/omap_h2_1610_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.25-rc3 3# Linux kernel version: 2.6.25-rc2-omap1
4# Mon Mar 3 03:39:48 2008 4# Wed Feb 20 17:12:36 2008
5# 5#
6CONFIG_ARM=y 6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y 7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
@@ -31,7 +31,6 @@ CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
31# 31#
32CONFIG_EXPERIMENTAL=y 32CONFIG_EXPERIMENTAL=y
33CONFIG_BROKEN_ON_SMP=y 33CONFIG_BROKEN_ON_SMP=y
34CONFIG_LOCK_KERNEL=y
35CONFIG_INIT_ENV_ARG_LIMIT=32 34CONFIG_INIT_ENV_ARG_LIMIT=32
36CONFIG_LOCALVERSION="" 35CONFIG_LOCALVERSION=""
37CONFIG_LOCALVERSION_AUTO=y 36CONFIG_LOCALVERSION_AUTO=y
@@ -50,7 +49,7 @@ CONFIG_FAIR_GROUP_SCHED=y
50# CONFIG_RT_GROUP_SCHED is not set 49# CONFIG_RT_GROUP_SCHED is not set
51CONFIG_USER_SCHED=y 50CONFIG_USER_SCHED=y
52# CONFIG_CGROUP_SCHED is not set 51# CONFIG_CGROUP_SCHED is not set
53# CONFIG_SYSFS_DEPRECATED is not set 52CONFIG_SYSFS_DEPRECATED=y
54# CONFIG_RELAY is not set 53# CONFIG_RELAY is not set
55CONFIG_NAMESPACES=y 54CONFIG_NAMESPACES=y
56# CONFIG_UTS_NS is not set 55# CONFIG_UTS_NS is not set
@@ -65,6 +64,7 @@ CONFIG_SYSCTL=y
65CONFIG_UID16=y 64CONFIG_UID16=y
66CONFIG_SYSCTL_SYSCALL=y 65CONFIG_SYSCTL_SYSCALL=y
67CONFIG_KALLSYMS=y 66CONFIG_KALLSYMS=y
67# CONFIG_KALLSYMS_ALL is not set
68# CONFIG_KALLSYMS_EXTRA_PASS is not set 68# CONFIG_KALLSYMS_EXTRA_PASS is not set
69CONFIG_HOTPLUG=y 69CONFIG_HOTPLUG=y
70CONFIG_PRINTK=y 70CONFIG_PRINTK=y
@@ -165,20 +165,28 @@ CONFIG_ARCH_OMAP=y
165CONFIG_ARCH_OMAP_OTG=y 165CONFIG_ARCH_OMAP_OTG=y
166CONFIG_ARCH_OMAP1=y 166CONFIG_ARCH_OMAP1=y
167# CONFIG_ARCH_OMAP2 is not set 167# CONFIG_ARCH_OMAP2 is not set
168# CONFIG_ARCH_OMAP3 is not set
168 169
169# 170#
170# OMAP Feature Selections 171# OMAP Feature Selections
171# 172#
173CONFIG_OMAP_DEBUG_SRAM_PATCH=y
172# CONFIG_OMAP_RESET_CLOCKS is not set 174# CONFIG_OMAP_RESET_CLOCKS is not set
175CONFIG_OMAP_BOOT_TAG=y
176# CONFIG_OMAP_BOOT_REASON is not set
177# CONFIG_OMAP_COMPONENT_VERSION is not set
178CONFIG_OMAP_GPIO_SWITCH=y
173CONFIG_OMAP_MUX=y 179CONFIG_OMAP_MUX=y
174# CONFIG_OMAP_MUX_DEBUG is not set 180CONFIG_OMAP_MUX_DEBUG=y
175CONFIG_OMAP_MUX_WARNINGS=y 181CONFIG_OMAP_MUX_WARNINGS=y
182# CONFIG_OMAP_STI is not set
176CONFIG_OMAP_MCBSP=y 183CONFIG_OMAP_MCBSP=y
177# CONFIG_OMAP_MMU_FWK is not set 184# CONFIG_OMAP_MMU_FWK is not set
185# CONFIG_OMAP_MBOX_FWK is not set
178# CONFIG_OMAP_MPU_TIMER is not set 186# CONFIG_OMAP_MPU_TIMER is not set
179CONFIG_OMAP_32K_TIMER=y 187CONFIG_OMAP_32K_TIMER=y
180CONFIG_OMAP_32K_TIMER_HZ=128 188CONFIG_OMAP_32K_TIMER_HZ=128
181# CONFIG_OMAP_DM_TIMER is not set 189CONFIG_OMAP_DM_TIMER=y
182CONFIG_OMAP_LL_DEBUG_UART1=y 190CONFIG_OMAP_LL_DEBUG_UART1=y
183# CONFIG_OMAP_LL_DEBUG_UART2 is not set 191# CONFIG_OMAP_LL_DEBUG_UART2 is not set
184# CONFIG_OMAP_LL_DEBUG_UART3 is not set 192# CONFIG_OMAP_LL_DEBUG_UART3 is not set
@@ -206,10 +214,10 @@ CONFIG_MACH_OMAP_H2=y
206# 214#
207# CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER is not set 215# CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER is not set
208# CONFIG_OMAP_ARM_216MHZ is not set 216# CONFIG_OMAP_ARM_216MHZ is not set
209CONFIG_OMAP_ARM_192MHZ=y 217# CONFIG_OMAP_ARM_192MHZ is not set
210# CONFIG_OMAP_ARM_168MHZ is not set 218# CONFIG_OMAP_ARM_168MHZ is not set
211# CONFIG_OMAP_ARM_120MHZ is not set 219# CONFIG_OMAP_ARM_120MHZ is not set
212# CONFIG_OMAP_ARM_60MHZ is not set 220CONFIG_OMAP_ARM_60MHZ=y
213# CONFIG_OMAP_ARM_30MHZ is not set 221# CONFIG_OMAP_ARM_30MHZ is not set
214 222
215# 223#
@@ -227,6 +235,7 @@ CONFIG_CPU_32=y
227CONFIG_CPU_ARM926T=y 235CONFIG_CPU_ARM926T=y
228CONFIG_CPU_32v5=y 236CONFIG_CPU_32v5=y
229CONFIG_CPU_ABRT_EV5TJ=y 237CONFIG_CPU_ABRT_EV5TJ=y
238CONFIG_CPU_PABRT_NOIFAR=y
230CONFIG_CPU_CACHE_VIVT=y 239CONFIG_CPU_CACHE_VIVT=y
231CONFIG_CPU_COPY_V4WB=y 240CONFIG_CPU_COPY_V4WB=y
232CONFIG_CPU_TLB_V4WBI=y 241CONFIG_CPU_TLB_V4WBI=y
@@ -257,10 +266,9 @@ CONFIG_TICK_ONESHOT=y
257CONFIG_NO_HZ=y 266CONFIG_NO_HZ=y
258CONFIG_HIGH_RES_TIMERS=y 267CONFIG_HIGH_RES_TIMERS=y
259CONFIG_GENERIC_CLOCKEVENTS_BUILD=y 268CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
260CONFIG_PREEMPT=y 269# CONFIG_PREEMPT is not set
261CONFIG_HZ=128 270CONFIG_HZ=128
262CONFIG_AEABI=y 271# CONFIG_AEABI is not set
263CONFIG_OABI_COMPAT=y
264# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set 272# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
265CONFIG_SELECT_MEMORY_MODEL=y 273CONFIG_SELECT_MEMORY_MODEL=y
266CONFIG_FLATMEM_MANUAL=y 274CONFIG_FLATMEM_MANUAL=y
@@ -275,7 +283,8 @@ CONFIG_SPLIT_PTLOCK_CPUS=4096
275CONFIG_ZONE_DMA_FLAG=1 283CONFIG_ZONE_DMA_FLAG=1
276CONFIG_BOUNCE=y 284CONFIG_BOUNCE=y
277CONFIG_VIRT_TO_BUS=y 285CONFIG_VIRT_TO_BUS=y
278# CONFIG_LEDS is not set 286CONFIG_LEDS=y
287# CONFIG_LEDS_CPU is not set
279CONFIG_ALIGNMENT_TRAP=y 288CONFIG_ALIGNMENT_TRAP=y
280 289
281# 290#
@@ -283,7 +292,7 @@ CONFIG_ALIGNMENT_TRAP=y
283# 292#
284CONFIG_ZBOOT_ROM_TEXT=0x0 293CONFIG_ZBOOT_ROM_TEXT=0x0
285CONFIG_ZBOOT_ROM_BSS=0x0 294CONFIG_ZBOOT_ROM_BSS=0x0
286CONFIG_CMDLINE="mem=32M console=ttyS0,115200n8 root=0801 ro init=/bin/sh" 295CONFIG_CMDLINE="mem=32M console=ttyS0,115200n8 root=/dev/ram0 rw initrd=0x10600000,8M ramdisk_size=8192"
287# CONFIG_XIP_KERNEL is not set 296# CONFIG_XIP_KERNEL is not set
288# CONFIG_KEXEC is not set 297# CONFIG_KEXEC is not set
289# CONFIG_ATAGS_PROC is not set 298# CONFIG_ATAGS_PROC is not set
@@ -291,20 +300,7 @@ CONFIG_CMDLINE="mem=32M console=ttyS0,115200n8 root=0801 ro init=/bin/sh"
291# 300#
292# CPU Frequency scaling 301# CPU Frequency scaling
293# 302#
294CONFIG_CPU_FREQ=y 303# CONFIG_CPU_FREQ is not set
295CONFIG_CPU_FREQ_TABLE=y
296# CONFIG_CPU_FREQ_DEBUG is not set
297CONFIG_CPU_FREQ_STAT=y
298# CONFIG_CPU_FREQ_STAT_DETAILS is not set
299# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
300CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
301# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
302# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
303# CONFIG_CPU_FREQ_GOV_PERFORMANCE is not set
304# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
305CONFIG_CPU_FREQ_GOV_USERSPACE=y
306# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
307# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
308 304
309# 305#
310# Floating point emulation 306# Floating point emulation
@@ -322,8 +318,9 @@ CONFIG_FPE_NWFPE=y
322# Userspace binary formats 318# Userspace binary formats
323# 319#
324CONFIG_BINFMT_ELF=y 320CONFIG_BINFMT_ELF=y
325CONFIG_BINFMT_AOUT=y 321# CONFIG_BINFMT_AOUT is not set
326# CONFIG_BINFMT_MISC is not set 322# CONFIG_BINFMT_MISC is not set
323# CONFIG_ARTHUR is not set
327 324
328# 325#
329# Power management options 326# Power management options
@@ -433,21 +430,102 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
433CONFIG_STANDALONE=y 430CONFIG_STANDALONE=y
434CONFIG_PREVENT_FIRMWARE_BUILD=y 431CONFIG_PREVENT_FIRMWARE_BUILD=y
435# CONFIG_FW_LOADER is not set 432# CONFIG_FW_LOADER is not set
433CONFIG_DEBUG_DRIVER=y
434# CONFIG_DEBUG_DEVRES is not set
436# CONFIG_SYS_HYPERVISOR is not set 435# CONFIG_SYS_HYPERVISOR is not set
437# CONFIG_CONNECTOR is not set 436# CONFIG_CONNECTOR is not set
438# CONFIG_MTD is not set 437CONFIG_MTD=y
438CONFIG_MTD_DEBUG=y
439CONFIG_MTD_DEBUG_VERBOSE=3
440# CONFIG_MTD_CONCAT is not set
441CONFIG_MTD_PARTITIONS=y
442# CONFIG_MTD_REDBOOT_PARTS is not set
443CONFIG_MTD_CMDLINE_PARTS=y
444# CONFIG_MTD_AFS_PARTS is not set
445
446#
447# User Modules And Translation Layers
448#
449CONFIG_MTD_CHAR=y
450CONFIG_MTD_BLKDEVS=y
451CONFIG_MTD_BLOCK=y
452# CONFIG_FTL is not set
453# CONFIG_NFTL is not set
454# CONFIG_INFTL is not set
455# CONFIG_RFD_FTL is not set
456# CONFIG_SSFDC is not set
457# CONFIG_MTD_OOPS is not set
458
459#
460# RAM/ROM/Flash chip drivers
461#
462CONFIG_MTD_CFI=y
463# CONFIG_MTD_JEDECPROBE is not set
464CONFIG_MTD_GEN_PROBE=y
465# CONFIG_MTD_CFI_ADV_OPTIONS is not set
466CONFIG_MTD_MAP_BANK_WIDTH_1=y
467CONFIG_MTD_MAP_BANK_WIDTH_2=y
468CONFIG_MTD_MAP_BANK_WIDTH_4=y
469# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
470# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
471# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
472CONFIG_MTD_CFI_I1=y
473CONFIG_MTD_CFI_I2=y
474# CONFIG_MTD_CFI_I4 is not set
475# CONFIG_MTD_CFI_I8 is not set
476CONFIG_MTD_CFI_INTELEXT=y
477# CONFIG_MTD_CFI_AMDSTD is not set
478# CONFIG_MTD_CFI_STAA is not set
479CONFIG_MTD_CFI_UTIL=y
480# CONFIG_MTD_RAM is not set
481# CONFIG_MTD_ROM is not set
482# CONFIG_MTD_ABSENT is not set
483
484#
485# Mapping drivers for chip access
486#
487# CONFIG_MTD_COMPLEX_MAPPINGS is not set
488# CONFIG_MTD_PHYSMAP is not set
489# CONFIG_MTD_ARM_INTEGRATOR is not set
490# CONFIG_MTD_OMAP_NOR is not set
491# CONFIG_MTD_PLATRAM is not set
492
493#
494# Self-contained MTD device drivers
495#
496# CONFIG_MTD_DATAFLASH is not set
497# CONFIG_MTD_M25P80 is not set
498# CONFIG_MTD_SLRAM is not set
499# CONFIG_MTD_PHRAM is not set
500# CONFIG_MTD_MTDRAM is not set
501# CONFIG_MTD_BLOCK2MTD is not set
502
503#
504# Disk-On-Chip Device Drivers
505#
506# CONFIG_MTD_DOC2000 is not set
507# CONFIG_MTD_DOC2001 is not set
508# CONFIG_MTD_DOC2001PLUS is not set
509# CONFIG_MTD_NAND is not set
510# CONFIG_MTD_ONENAND is not set
511
512#
513# UBI - Unsorted block images
514#
515# CONFIG_MTD_UBI is not set
439# CONFIG_PARPORT is not set 516# CONFIG_PARPORT is not set
440CONFIG_BLK_DEV=y 517CONFIG_BLK_DEV=y
441# CONFIG_BLK_DEV_COW_COMMON is not set 518# CONFIG_BLK_DEV_COW_COMMON is not set
442CONFIG_BLK_DEV_LOOP=y 519CONFIG_BLK_DEV_LOOP=y
443# CONFIG_BLK_DEV_CRYPTOLOOP is not set 520# CONFIG_BLK_DEV_CRYPTOLOOP is not set
444# CONFIG_BLK_DEV_NBD is not set 521# CONFIG_BLK_DEV_NBD is not set
522# CONFIG_BLK_DEV_UB is not set
445CONFIG_BLK_DEV_RAM=y 523CONFIG_BLK_DEV_RAM=y
446CONFIG_BLK_DEV_RAM_COUNT=16 524CONFIG_BLK_DEV_RAM_COUNT=16
447CONFIG_BLK_DEV_RAM_SIZE=8192 525CONFIG_BLK_DEV_RAM_SIZE=8192
448# CONFIG_BLK_DEV_XIP is not set 526# CONFIG_BLK_DEV_XIP is not set
449# CONFIG_CDROM_PKTCDVD is not set 527# CONFIG_CDROM_PKTCDVD is not set
450CONFIG_ATA_OVER_ETH=m 528# CONFIG_ATA_OVER_ETH is not set
451CONFIG_MISC_DEVICES=y 529CONFIG_MISC_DEVICES=y
452# CONFIG_EEPROM_93CX6 is not set 530# CONFIG_EEPROM_93CX6 is not set
453# CONFIG_ENCLOSURE_SERVICES is not set 531# CONFIG_ENCLOSURE_SERVICES is not set
@@ -457,42 +535,9 @@ CONFIG_MISC_DEVICES=y
457# SCSI device support 535# SCSI device support
458# 536#
459# CONFIG_RAID_ATTRS is not set 537# CONFIG_RAID_ATTRS is not set
460CONFIG_SCSI=y 538# CONFIG_SCSI is not set
461CONFIG_SCSI_DMA=y 539# CONFIG_SCSI_DMA is not set
462# CONFIG_SCSI_TGT is not set
463# CONFIG_SCSI_NETLINK is not set 540# CONFIG_SCSI_NETLINK is not set
464CONFIG_SCSI_PROC_FS=y
465
466#
467# SCSI support type (disk, tape, CD-ROM)
468#
469# CONFIG_BLK_DEV_SD is not set
470# CONFIG_CHR_DEV_ST is not set
471# CONFIG_CHR_DEV_OSST is not set
472# CONFIG_BLK_DEV_SR is not set
473# CONFIG_CHR_DEV_SG is not set
474# CONFIG_CHR_DEV_SCH is not set
475
476#
477# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
478#
479# CONFIG_SCSI_MULTI_LUN is not set
480# CONFIG_SCSI_CONSTANTS is not set
481# CONFIG_SCSI_LOGGING is not set
482# CONFIG_SCSI_SCAN_ASYNC is not set
483CONFIG_SCSI_WAIT_SCAN=m
484
485#
486# SCSI Transports
487#
488# CONFIG_SCSI_SPI_ATTRS is not set
489# CONFIG_SCSI_FC_ATTRS is not set
490# CONFIG_SCSI_ISCSI_ATTRS is not set
491# CONFIG_SCSI_SAS_LIBSAS is not set
492# CONFIG_SCSI_SRP_ATTRS is not set
493CONFIG_SCSI_LOWLEVEL=y
494# CONFIG_ISCSI_TCP is not set
495# CONFIG_SCSI_DEBUG is not set
496# CONFIG_ATA is not set 541# CONFIG_ATA is not set
497# CONFIG_MD is not set 542# CONFIG_MD is not set
498CONFIG_NETDEVICES=y 543CONFIG_NETDEVICES=y
@@ -509,6 +554,7 @@ CONFIG_MII=y
509# CONFIG_AX88796 is not set 554# CONFIG_AX88796 is not set
510CONFIG_SMC91X=y 555CONFIG_SMC91X=y
511# CONFIG_DM9000 is not set 556# CONFIG_DM9000 is not set
557# CONFIG_ENC28J60 is not set
512# CONFIG_IBM_NEW_EMAC_ZMII is not set 558# CONFIG_IBM_NEW_EMAC_ZMII is not set
513# CONFIG_IBM_NEW_EMAC_RGMII is not set 559# CONFIG_IBM_NEW_EMAC_RGMII is not set
514# CONFIG_IBM_NEW_EMAC_TAH is not set 560# CONFIG_IBM_NEW_EMAC_TAH is not set
@@ -523,6 +569,15 @@ CONFIG_NETDEV_10000=y
523# 569#
524# CONFIG_WLAN_PRE80211 is not set 570# CONFIG_WLAN_PRE80211 is not set
525# CONFIG_WLAN_80211 is not set 571# CONFIG_WLAN_80211 is not set
572
573#
574# USB Network Adapters
575#
576# CONFIG_USB_CATC is not set
577# CONFIG_USB_KAWETH is not set
578# CONFIG_USB_PEGASUS is not set
579# CONFIG_USB_RTL8150 is not set
580# CONFIG_USB_USBNET is not set
526# CONFIG_WAN is not set 581# CONFIG_WAN is not set
527CONFIG_PPP=y 582CONFIG_PPP=y
528# CONFIG_PPP_MULTILINK is not set 583# CONFIG_PPP_MULTILINK is not set
@@ -612,7 +667,8 @@ CONFIG_SERIAL_CORE_CONSOLE=y
612CONFIG_UNIX98_PTYS=y 667CONFIG_UNIX98_PTYS=y
613# CONFIG_LEGACY_PTYS is not set 668# CONFIG_LEGACY_PTYS is not set
614# CONFIG_IPMI_HANDLER is not set 669# CONFIG_IPMI_HANDLER is not set
615# CONFIG_HW_RANDOM is not set 670CONFIG_HW_RANDOM=m
671CONFIG_HW_RANDOM_OMAP=m
616# CONFIG_NVRAM is not set 672# CONFIG_NVRAM is not set
617# CONFIG_R3964 is not set 673# CONFIG_R3964 is not set
618# CONFIG_RAW_DRIVER is not set 674# CONFIG_RAW_DRIVER is not set
@@ -638,6 +694,7 @@ CONFIG_I2C_OMAP=y
638# CONFIG_I2C_SIMTEC is not set 694# CONFIG_I2C_SIMTEC is not set
639# CONFIG_I2C_TAOS_EVM is not set 695# CONFIG_I2C_TAOS_EVM is not set
640# CONFIG_I2C_STUB is not set 696# CONFIG_I2C_STUB is not set
697# CONFIG_I2C_TINY_USB is not set
641 698
642# 699#
643# Miscellaneous I2C Chip support 700# Miscellaneous I2C Chip support
@@ -647,8 +704,10 @@ CONFIG_I2C_OMAP=y
647# CONFIG_SENSORS_PCF8574 is not set 704# CONFIG_SENSORS_PCF8574 is not set
648# CONFIG_PCF8575 is not set 705# CONFIG_PCF8575 is not set
649# CONFIG_SENSORS_PCF8591 is not set 706# CONFIG_SENSORS_PCF8591 is not set
650# CONFIG_ISP1301_OMAP is not set 707CONFIG_ISP1301_OMAP=y
651CONFIG_TPS65010=y 708CONFIG_TPS65010=y
709# CONFIG_SENSORS_TLV320AIC23 is not set
710# CONFIG_GPIOEXPANDER_OMAP is not set
652# CONFIG_SENSORS_MAX6875 is not set 711# CONFIG_SENSORS_MAX6875 is not set
653# CONFIG_SENSORS_TSL2550 is not set 712# CONFIG_SENSORS_TSL2550 is not set
654# CONFIG_I2C_DEBUG_CORE is not set 713# CONFIG_I2C_DEBUG_CORE is not set
@@ -659,8 +718,26 @@ CONFIG_TPS65010=y
659# 718#
660# SPI support 719# SPI support
661# 720#
662# CONFIG_SPI is not set 721CONFIG_SPI=y
663# CONFIG_SPI_MASTER is not set 722# CONFIG_SPI_DEBUG is not set
723CONFIG_SPI_MASTER=y
724
725#
726# SPI Master Controller Drivers
727#
728CONFIG_SPI_BITBANG=y
729CONFIG_SPI_OMAP_UWIRE=y
730
731#
732# SPI Protocol Masters
733#
734# CONFIG_SPI_AT25 is not set
735CONFIG_SPI_TSC2101=y
736# CONFIG_SPI_TSC2102 is not set
737# CONFIG_SPI_TSC210X is not set
738# CONFIG_SPI_TSC2301 is not set
739# CONFIG_SPI_SPIDEV is not set
740# CONFIG_SPI_TLE62X0 is not set
664# CONFIG_W1 is not set 741# CONFIG_W1 is not set
665# CONFIG_POWER_SUPPLY is not set 742# CONFIG_POWER_SUPPLY is not set
666CONFIG_HWMON=y 743CONFIG_HWMON=y
@@ -673,7 +750,6 @@ CONFIG_HWMON=y
673# CONFIG_SENSORS_ADM1031 is not set 750# CONFIG_SENSORS_ADM1031 is not set
674# CONFIG_SENSORS_ADM9240 is not set 751# CONFIG_SENSORS_ADM9240 is not set
675# CONFIG_SENSORS_ADT7470 is not set 752# CONFIG_SENSORS_ADT7470 is not set
676# CONFIG_SENSORS_ADT7473 is not set
677# CONFIG_SENSORS_ATXP1 is not set 753# CONFIG_SENSORS_ATXP1 is not set
678# CONFIG_SENSORS_DS1621 is not set 754# CONFIG_SENSORS_DS1621 is not set
679# CONFIG_SENSORS_F71805F is not set 755# CONFIG_SENSORS_F71805F is not set
@@ -683,6 +759,7 @@ CONFIG_HWMON=y
683# CONFIG_SENSORS_GL520SM is not set 759# CONFIG_SENSORS_GL520SM is not set
684# CONFIG_SENSORS_IT87 is not set 760# CONFIG_SENSORS_IT87 is not set
685# CONFIG_SENSORS_LM63 is not set 761# CONFIG_SENSORS_LM63 is not set
762# CONFIG_SENSORS_LM70 is not set
686# CONFIG_SENSORS_LM75 is not set 763# CONFIG_SENSORS_LM75 is not set
687# CONFIG_SENSORS_LM77 is not set 764# CONFIG_SENSORS_LM77 is not set
688# CONFIG_SENSORS_LM78 is not set 765# CONFIG_SENSORS_LM78 is not set
@@ -712,6 +789,7 @@ CONFIG_HWMON=y
712# CONFIG_SENSORS_W83L786NG is not set 789# CONFIG_SENSORS_W83L786NG is not set
713# CONFIG_SENSORS_W83627HF is not set 790# CONFIG_SENSORS_W83627HF is not set
714# CONFIG_SENSORS_W83627EHF is not set 791# CONFIG_SENSORS_W83627EHF is not set
792# CONFIG_SENSORS_TSC210X is not set
715# CONFIG_HWMON_DEBUG_CHIP is not set 793# CONFIG_HWMON_DEBUG_CHIP is not set
716CONFIG_WATCHDOG=y 794CONFIG_WATCHDOG=y
717CONFIG_WATCHDOG_NOWAYOUT=y 795CONFIG_WATCHDOG_NOWAYOUT=y
@@ -723,6 +801,11 @@ CONFIG_WATCHDOG_NOWAYOUT=y
723# CONFIG_OMAP_WATCHDOG is not set 801# CONFIG_OMAP_WATCHDOG is not set
724 802
725# 803#
804# USB-based Watchdog Cards
805#
806# CONFIG_USBPCWATCHDOG is not set
807
808#
726# Sonics Silicon Backplane 809# Sonics Silicon Backplane
727# 810#
728CONFIG_SSB_POSSIBLE=y 811CONFIG_SSB_POSSIBLE=y
@@ -740,6 +823,7 @@ CONFIG_SSB_POSSIBLE=y
740# CONFIG_VIDEO_DEV is not set 823# CONFIG_VIDEO_DEV is not set
741# CONFIG_DVB_CORE is not set 824# CONFIG_DVB_CORE is not set
742CONFIG_DAB=y 825CONFIG_DAB=y
826# CONFIG_USB_DABUSB is not set
743 827
744# 828#
745# Graphics support 829# Graphics support
@@ -749,9 +833,9 @@ CONFIG_VIDEO_OUTPUT_CONTROL=m
749CONFIG_FB=y 833CONFIG_FB=y
750CONFIG_FIRMWARE_EDID=y 834CONFIG_FIRMWARE_EDID=y
751# CONFIG_FB_DDC is not set 835# CONFIG_FB_DDC is not set
752# CONFIG_FB_CFB_FILLRECT is not set 836CONFIG_FB_CFB_FILLRECT=y
753# CONFIG_FB_CFB_COPYAREA is not set 837CONFIG_FB_CFB_COPYAREA=y
754# CONFIG_FB_CFB_IMAGEBLIT is not set 838CONFIG_FB_CFB_IMAGEBLIT=y
755# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set 839# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
756# CONFIG_FB_SYS_FILLRECT is not set 840# CONFIG_FB_SYS_FILLRECT is not set
757# CONFIG_FB_SYS_COPYAREA is not set 841# CONFIG_FB_SYS_COPYAREA is not set
@@ -769,7 +853,11 @@ CONFIG_FB_MODE_HELPERS=y
769# 853#
770# CONFIG_FB_S1D13XXX is not set 854# CONFIG_FB_S1D13XXX is not set
771# CONFIG_FB_VIRTUAL is not set 855# CONFIG_FB_VIRTUAL is not set
772# CONFIG_FB_OMAP is not set 856CONFIG_FB_OMAP=y
857# CONFIG_FB_OMAP_LCDC_EXTERNAL is not set
858# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set
859CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=2
860# CONFIG_FB_OMAP_DMA_TUNE is not set
773# CONFIG_BACKLIGHT_LCD_SUPPORT is not set 861# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
774 862
775# 863#
@@ -785,17 +873,9 @@ CONFIG_DUMMY_CONSOLE=y
785CONFIG_FRAMEBUFFER_CONSOLE=y 873CONFIG_FRAMEBUFFER_CONSOLE=y
786# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set 874# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
787# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set 875# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
788CONFIG_FONTS=y 876# CONFIG_FONTS is not set
789CONFIG_FONT_8x8=y 877CONFIG_FONT_8x8=y
790CONFIG_FONT_8x16=y 878CONFIG_FONT_8x16=y
791# CONFIG_FONT_6x11 is not set
792# CONFIG_FONT_7x14 is not set
793# CONFIG_FONT_PEARL_8x8 is not set
794# CONFIG_FONT_ACORN_8x8 is not set
795# CONFIG_FONT_MINI_4x6 is not set
796# CONFIG_FONT_SUN8x16 is not set
797# CONFIG_FONT_SUN12x22 is not set
798# CONFIG_FONT_10x18 is not set
799CONFIG_LOGO=y 879CONFIG_LOGO=y
800# CONFIG_LOGO_LINUX_MONO is not set 880# CONFIG_LOGO_LINUX_MONO is not set
801# CONFIG_LOGO_LINUX_VGA16 is not set 881# CONFIG_LOGO_LINUX_VGA16 is not set
@@ -804,37 +884,204 @@ CONFIG_LOGO_LINUX_CLUT224=y
804# 884#
805# Sound 885# Sound
806# 886#
807CONFIG_SOUND=y 887# CONFIG_SOUND is not set
888CONFIG_HID_SUPPORT=y
889CONFIG_HID=y
890# CONFIG_HID_DEBUG is not set
891# CONFIG_HIDRAW is not set
808 892
809# 893#
810# Advanced Linux Sound Architecture 894# USB Input Devices
811# 895#
812# CONFIG_SND is not set 896# CONFIG_USB_HID is not set
813 897
814# 898#
815# Open Sound System 899# USB HID Boot Protocol drivers
816# 900#
817CONFIG_SOUND_PRIME=y 901# CONFIG_USB_KBD is not set
818# CONFIG_SOUND_MSNDCLAS is not set 902# CONFIG_USB_MOUSE is not set
819# CONFIG_SOUND_MSNDPIN is not set
820CONFIG_HID_SUPPORT=y
821CONFIG_HID=y
822CONFIG_HID_DEBUG=y
823# CONFIG_HIDRAW is not set
824CONFIG_USB_SUPPORT=y 903CONFIG_USB_SUPPORT=y
825CONFIG_USB_ARCH_HAS_HCD=y 904CONFIG_USB_ARCH_HAS_HCD=y
826CONFIG_USB_ARCH_HAS_OHCI=y 905CONFIG_USB_ARCH_HAS_OHCI=y
827# CONFIG_USB_ARCH_HAS_EHCI is not set 906# CONFIG_USB_ARCH_HAS_EHCI is not set
828# CONFIG_USB is not set 907CONFIG_USB=y
908# CONFIG_USB_DEBUG is not set
909# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
910
911#
912# Miscellaneous USB options
913#
914CONFIG_USB_DEVICEFS=y
915# CONFIG_USB_DEVICE_CLASS is not set
916# CONFIG_USB_DYNAMIC_MINORS is not set
917CONFIG_USB_SUSPEND=y
918# CONFIG_USB_PERSIST is not set
919CONFIG_USB_OTG=y
920CONFIG_USB_OTG_WHITELIST=y
921# CONFIG_USB_OTG_BLACKLIST_HUB is not set
922
923#
924# USB Host Controller Drivers
925#
926# CONFIG_USB_ISP116X_HCD is not set
927CONFIG_USB_OHCI_HCD=y
928# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
929# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
930CONFIG_USB_OHCI_LITTLE_ENDIAN=y
931# CONFIG_USB_SL811_HCD is not set
932# CONFIG_USB_R8A66597_HCD is not set
933# CONFIG_USB_MUSB_HDRC is not set
934# CONFIG_USB_GADGET_MUSB_HDRC is not set
935
936#
937# USB Device Class drivers
938#
939# CONFIG_USB_ACM is not set
940# CONFIG_USB_PRINTER is not set
829 941
830# 942#
831# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 943# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
832# 944#
833# CONFIG_USB_GADGET is not set 945
834# CONFIG_MMC is not set 946#
947# may also be needed; see USB_STORAGE Help for more information
948#
949# CONFIG_USB_LIBUSUAL is not set
950
951#
952# USB Imaging devices
953#
954# CONFIG_USB_MDC800 is not set
955CONFIG_USB_MON=y
956
957#
958# USB port drivers
959#
960# CONFIG_USB_SERIAL is not set
961
962#
963# USB Miscellaneous drivers
964#
965# CONFIG_USB_EMI62 is not set
966# CONFIG_USB_EMI26 is not set
967# CONFIG_USB_ADUTUX is not set
968# CONFIG_USB_AUERSWALD is not set
969# CONFIG_USB_RIO500 is not set
970# CONFIG_USB_LEGOTOWER is not set
971# CONFIG_USB_LCD is not set
972# CONFIG_USB_BERRY_CHARGE is not set
973# CONFIG_USB_LED is not set
974# CONFIG_USB_CYPRESS_CY7C63 is not set
975# CONFIG_USB_CYTHERM is not set
976# CONFIG_USB_PHIDGET is not set
977# CONFIG_USB_IDMOUSE is not set
978# CONFIG_USB_FTDI_ELAN is not set
979# CONFIG_USB_APPLEDISPLAY is not set
980# CONFIG_USB_LD is not set
981# CONFIG_USB_TRANCEVIBRATOR is not set
982# CONFIG_USB_IOWARRIOR is not set
983CONFIG_USB_TEST=y
984CONFIG_USB_GADGET=y
985# CONFIG_USB_GADGET_DEBUG is not set
986# CONFIG_USB_GADGET_DEBUG_FILES is not set
987CONFIG_USB_GADGET_SELECTED=y
988# CONFIG_USB_GADGET_AMD5536UDC is not set
989# CONFIG_USB_GADGET_ATMEL_USBA is not set
990# CONFIG_USB_GADGET_FSL_USB2 is not set
991# CONFIG_USB_GADGET_NET2280 is not set
992# CONFIG_USB_GADGET_PXA2XX is not set
993# CONFIG_USB_GADGET_M66592 is not set
994# CONFIG_USB_GADGET_GOKU is not set
995# CONFIG_USB_GADGET_LH7A40X is not set
996CONFIG_USB_GADGET_OMAP=y
997CONFIG_USB_OMAP=y
998# CONFIG_USB_GADGET_S3C2410 is not set
999# CONFIG_USB_GADGET_AT91 is not set
1000# CONFIG_USB_GADGET_DUMMY_HCD is not set
1001# CONFIG_USB_GADGET_DUALSPEED is not set
1002# CONFIG_USB_ZERO is not set
1003CONFIG_USB_ETH=y
1004CONFIG_USB_ETH_RNDIS=y
1005# CONFIG_USB_GADGETFS is not set
1006# CONFIG_USB_FILE_STORAGE is not set
1007# CONFIG_USB_G_SERIAL is not set
1008# CONFIG_USB_MIDI_GADGET is not set
1009# CONFIG_USB_G_PRINTER is not set
1010CONFIG_MMC=y
1011# CONFIG_MMC_DEBUG is not set
1012# CONFIG_MMC_UNSAFE_RESUME is not set
1013
1014#
1015# MMC/SD Card Drivers
1016#
1017CONFIG_MMC_BLOCK=y
1018CONFIG_MMC_BLOCK_BOUNCE=y
1019# CONFIG_SDIO_UART is not set
1020
1021#
1022# MMC/SD Host Controller Drivers
1023#
1024CONFIG_MMC_OMAP=y
1025# CONFIG_MMC_SPI is not set
835# CONFIG_NEW_LEDS is not set 1026# CONFIG_NEW_LEDS is not set
836CONFIG_RTC_LIB=y 1027CONFIG_RTC_LIB=y
837# CONFIG_RTC_CLASS is not set 1028CONFIG_RTC_CLASS=y
1029CONFIG_RTC_HCTOSYS=y
1030CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
1031# CONFIG_RTC_DEBUG is not set
1032
1033#
1034# RTC interfaces
1035#
1036CONFIG_RTC_INTF_SYSFS=y
1037CONFIG_RTC_INTF_PROC=y
1038CONFIG_RTC_INTF_DEV=y
1039# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
1040# CONFIG_RTC_DRV_TEST is not set
1041
1042#
1043# I2C RTC drivers
1044#
1045# CONFIG_RTC_DRV_DS1307 is not set
1046# CONFIG_RTC_DRV_DS1374 is not set
1047# CONFIG_RTC_DRV_DS1672 is not set
1048# CONFIG_RTC_DRV_MAX6900 is not set
1049# CONFIG_RTC_DRV_RS5C372 is not set
1050# CONFIG_RTC_DRV_ISL1208 is not set
1051# CONFIG_RTC_DRV_X1205 is not set
1052# CONFIG_RTC_DRV_PCF8563 is not set
1053# CONFIG_RTC_DRV_PCF8583 is not set
1054# CONFIG_RTC_DRV_M41T80 is not set
1055
1056#
1057# SPI RTC drivers
1058#
1059# CONFIG_RTC_DRV_MAX6902 is not set
1060# CONFIG_RTC_DRV_R9701 is not set
1061# CONFIG_RTC_DRV_RS5C348 is not set
1062
1063#
1064# Platform RTC drivers
1065#
1066# CONFIG_RTC_DRV_CMOS is not set
1067# CONFIG_RTC_DRV_DS1511 is not set
1068# CONFIG_RTC_DRV_DS1553 is not set
1069# CONFIG_RTC_DRV_DS1742 is not set
1070# CONFIG_RTC_DRV_STK17TA8 is not set
1071# CONFIG_RTC_DRV_M48T86 is not set
1072# CONFIG_RTC_DRV_M48T59 is not set
1073# CONFIG_RTC_DRV_V3020 is not set
1074
1075#
1076# on-CPU RTC drivers
1077#
1078CONFIG_RTC_DRV_OMAP=y
1079
1080#
1081# CBUS support
1082#
1083# CONFIG_CBUS is not set
1084# CONFIG_OMAP_DSP is not set
838 1085
839# 1086#
840# File systems 1087# File systems
@@ -894,6 +1141,17 @@ CONFIG_SYSFS=y
894# CONFIG_BEFS_FS is not set 1141# CONFIG_BEFS_FS is not set
895# CONFIG_BFS_FS is not set 1142# CONFIG_BFS_FS is not set
896# CONFIG_EFS_FS is not set 1143# CONFIG_EFS_FS is not set
1144CONFIG_JFFS2_FS=y
1145CONFIG_JFFS2_FS_DEBUG=0
1146CONFIG_JFFS2_FS_WRITEBUFFER=y
1147# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
1148# CONFIG_JFFS2_SUMMARY is not set
1149# CONFIG_JFFS2_FS_XATTR is not set
1150# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
1151CONFIG_JFFS2_ZLIB=y
1152# CONFIG_JFFS2_LZO is not set
1153CONFIG_JFFS2_RTIME=y
1154# CONFIG_JFFS2_RUBIN is not set
897CONFIG_CRAMFS=y 1155CONFIG_CRAMFS=y
898# CONFIG_VXFS_FS is not set 1156# CONFIG_VXFS_FS is not set
899# CONFIG_MINIX_FS is not set 1157# CONFIG_MINIX_FS is not set
@@ -904,19 +1162,16 @@ CONFIG_ROMFS_FS=y
904# CONFIG_UFS_FS is not set 1162# CONFIG_UFS_FS is not set
905CONFIG_NETWORK_FILESYSTEMS=y 1163CONFIG_NETWORK_FILESYSTEMS=y
906CONFIG_NFS_FS=y 1164CONFIG_NFS_FS=y
907CONFIG_NFS_V3=y 1165# CONFIG_NFS_V3 is not set
908# CONFIG_NFS_V3_ACL is not set 1166# CONFIG_NFS_V4 is not set
909CONFIG_NFS_V4=y
910# CONFIG_NFS_DIRECTIO is not set 1167# CONFIG_NFS_DIRECTIO is not set
911# CONFIG_NFSD is not set 1168# CONFIG_NFSD is not set
912CONFIG_ROOT_NFS=y 1169CONFIG_ROOT_NFS=y
913CONFIG_LOCKD=y 1170CONFIG_LOCKD=y
914CONFIG_LOCKD_V4=y
915CONFIG_NFS_COMMON=y 1171CONFIG_NFS_COMMON=y
916CONFIG_SUNRPC=y 1172CONFIG_SUNRPC=y
917CONFIG_SUNRPC_GSS=y
918# CONFIG_SUNRPC_BIND34 is not set 1173# CONFIG_SUNRPC_BIND34 is not set
919CONFIG_RPCSEC_GSS_KRB5=y 1174# CONFIG_RPCSEC_GSS_KRB5 is not set
920# CONFIG_RPCSEC_GSS_SPKM3 is not set 1175# CONFIG_RPCSEC_GSS_SPKM3 is not set
921# CONFIG_SMB_FS is not set 1176# CONFIG_SMB_FS is not set
922# CONFIG_CIFS is not set 1177# CONFIG_CIFS is not set
@@ -981,11 +1236,38 @@ CONFIG_ENABLE_MUST_CHECK=y
981# CONFIG_UNUSED_SYMBOLS is not set 1236# CONFIG_UNUSED_SYMBOLS is not set
982# CONFIG_DEBUG_FS is not set 1237# CONFIG_DEBUG_FS is not set
983# CONFIG_HEADERS_CHECK is not set 1238# CONFIG_HEADERS_CHECK is not set
984# CONFIG_DEBUG_KERNEL is not set 1239CONFIG_DEBUG_KERNEL=y
1240# CONFIG_DEBUG_SHIRQ is not set
1241CONFIG_DETECT_SOFTLOCKUP=y
1242CONFIG_SCHED_DEBUG=y
1243# CONFIG_SCHEDSTATS is not set
1244# CONFIG_TIMER_STATS is not set
1245# CONFIG_DEBUG_SLAB is not set
1246# CONFIG_DEBUG_RT_MUTEXES is not set
1247# CONFIG_RT_MUTEX_TESTER is not set
1248# CONFIG_DEBUG_SPINLOCK is not set
1249# CONFIG_DEBUG_MUTEXES is not set
1250# CONFIG_DEBUG_LOCK_ALLOC is not set
1251# CONFIG_PROVE_LOCKING is not set
1252# CONFIG_LOCK_STAT is not set
1253# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1254# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1255# CONFIG_DEBUG_KOBJECT is not set
985CONFIG_DEBUG_BUGVERBOSE=y 1256CONFIG_DEBUG_BUGVERBOSE=y
1257CONFIG_DEBUG_INFO=y
1258# CONFIG_DEBUG_VM is not set
1259# CONFIG_DEBUG_LIST is not set
1260# CONFIG_DEBUG_SG is not set
986CONFIG_FRAME_POINTER=y 1261CONFIG_FRAME_POINTER=y
1262# CONFIG_BOOT_PRINTK_DELAY is not set
1263# CONFIG_RCU_TORTURE_TEST is not set
1264# CONFIG_BACKTRACE_SELF_TEST is not set
1265# CONFIG_FAULT_INJECTION is not set
987# CONFIG_SAMPLES is not set 1266# CONFIG_SAMPLES is not set
988# CONFIG_DEBUG_USER is not set 1267CONFIG_DEBUG_USER=y
1268CONFIG_DEBUG_ERRORS=y
1269# CONFIG_DEBUG_STACK_USAGE is not set
1270# CONFIG_DEBUG_LL is not set
989 1271
990# 1272#
991# Security options 1273# Security options
@@ -994,31 +1276,29 @@ CONFIG_FRAME_POINTER=y
994# CONFIG_SECURITY is not set 1276# CONFIG_SECURITY is not set
995# CONFIG_SECURITY_FILE_CAPABILITIES is not set 1277# CONFIG_SECURITY_FILE_CAPABILITIES is not set
996CONFIG_CRYPTO=y 1278CONFIG_CRYPTO=y
997CONFIG_CRYPTO_ALGAPI=y
998CONFIG_CRYPTO_BLKCIPHER=y
999# CONFIG_CRYPTO_SEQIV is not set 1279# CONFIG_CRYPTO_SEQIV is not set
1000CONFIG_CRYPTO_MANAGER=y 1280# CONFIG_CRYPTO_MANAGER is not set
1001# CONFIG_CRYPTO_HMAC is not set 1281# CONFIG_CRYPTO_HMAC is not set
1002# CONFIG_CRYPTO_XCBC is not set 1282# CONFIG_CRYPTO_XCBC is not set
1003# CONFIG_CRYPTO_NULL is not set 1283# CONFIG_CRYPTO_NULL is not set
1004# CONFIG_CRYPTO_MD4 is not set 1284# CONFIG_CRYPTO_MD4 is not set
1005CONFIG_CRYPTO_MD5=y 1285# CONFIG_CRYPTO_MD5 is not set
1006# CONFIG_CRYPTO_SHA1 is not set 1286# CONFIG_CRYPTO_SHA1 is not set
1007# CONFIG_CRYPTO_SHA256 is not set 1287# CONFIG_CRYPTO_SHA256 is not set
1008# CONFIG_CRYPTO_SHA512 is not set 1288# CONFIG_CRYPTO_SHA512 is not set
1009# CONFIG_CRYPTO_WP512 is not set 1289# CONFIG_CRYPTO_WP512 is not set
1010# CONFIG_CRYPTO_TGR192 is not set 1290# CONFIG_CRYPTO_TGR192 is not set
1011# CONFIG_CRYPTO_GF128MUL is not set 1291# CONFIG_CRYPTO_GF128MUL is not set
1012CONFIG_CRYPTO_ECB=m 1292# CONFIG_CRYPTO_ECB is not set
1013CONFIG_CRYPTO_CBC=y 1293# CONFIG_CRYPTO_CBC is not set
1014CONFIG_CRYPTO_PCBC=m 1294# CONFIG_CRYPTO_PCBC is not set
1015# CONFIG_CRYPTO_LRW is not set 1295# CONFIG_CRYPTO_LRW is not set
1016# CONFIG_CRYPTO_XTS is not set 1296# CONFIG_CRYPTO_XTS is not set
1017# CONFIG_CRYPTO_CTR is not set 1297# CONFIG_CRYPTO_CTR is not set
1018# CONFIG_CRYPTO_GCM is not set 1298# CONFIG_CRYPTO_GCM is not set
1019# CONFIG_CRYPTO_CCM is not set 1299# CONFIG_CRYPTO_CCM is not set
1020# CONFIG_CRYPTO_CRYPTD is not set 1300# CONFIG_CRYPTO_CRYPTD is not set
1021CONFIG_CRYPTO_DES=y 1301# CONFIG_CRYPTO_DES is not set
1022# CONFIG_CRYPTO_FCRYPT is not set 1302# CONFIG_CRYPTO_FCRYPT is not set
1023# CONFIG_CRYPTO_BLOWFISH is not set 1303# CONFIG_CRYPTO_BLOWFISH is not set
1024# CONFIG_CRYPTO_TWOFISH is not set 1304# CONFIG_CRYPTO_TWOFISH is not set
@@ -1052,6 +1332,7 @@ CONFIG_CRC32=y
1052# CONFIG_CRC7 is not set 1332# CONFIG_CRC7 is not set
1053# CONFIG_LIBCRC32C is not set 1333# CONFIG_LIBCRC32C is not set
1054CONFIG_ZLIB_INFLATE=y 1334CONFIG_ZLIB_INFLATE=y
1335CONFIG_ZLIB_DEFLATE=y
1055CONFIG_PLIST=y 1336CONFIG_PLIST=y
1056CONFIG_HAS_IOMEM=y 1337CONFIG_HAS_IOMEM=y
1057CONFIG_HAS_IOPORT=y 1338CONFIG_HAS_IOPORT=y
diff --git a/arch/arm/configs/omap_h4_2420_defconfig b/arch/arm/configs/omap_h4_2420_defconfig
new file mode 100644
index 000000000000..5bc89185a64f
--- /dev/null
+++ b/arch/arm/configs/omap_h4_2420_defconfig
@@ -0,0 +1,1120 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.23-rc6-omap1
4# Tue Sep 18 11:44:58 2007
5#
6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8CONFIG_GENERIC_GPIO=y
9CONFIG_GENERIC_TIME=y
10CONFIG_GENERIC_CLOCKEVENTS=y
11CONFIG_MMU=y
12# CONFIG_NO_IOPORT is not set
13CONFIG_GENERIC_HARDIRQS=y
14CONFIG_STACKTRACE_SUPPORT=y
15CONFIG_LOCKDEP_SUPPORT=y
16CONFIG_TRACE_IRQFLAGS_SUPPORT=y
17CONFIG_HARDIRQS_SW_RESEND=y
18CONFIG_GENERIC_IRQ_PROBE=y
19CONFIG_RWSEM_GENERIC_SPINLOCK=y
20# CONFIG_ARCH_HAS_ILOG2_U32 is not set
21# CONFIG_ARCH_HAS_ILOG2_U64 is not set
22CONFIG_GENERIC_HWEIGHT=y
23CONFIG_GENERIC_CALIBRATE_DELAY=y
24CONFIG_ZONE_DMA=y
25CONFIG_VECTORS_BASE=0xffff0000
26CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
27
28#
29# General setup
30#
31CONFIG_EXPERIMENTAL=y
32CONFIG_BROKEN_ON_SMP=y
33CONFIG_INIT_ENV_ARG_LIMIT=32
34CONFIG_LOCALVERSION=""
35CONFIG_LOCALVERSION_AUTO=y
36CONFIG_SWAP=y
37CONFIG_SYSVIPC=y
38CONFIG_SYSVIPC_SYSCTL=y
39# CONFIG_POSIX_MQUEUE is not set
40CONFIG_BSD_PROCESS_ACCT=y
41# CONFIG_BSD_PROCESS_ACCT_V3 is not set
42# CONFIG_TASKSTATS is not set
43# CONFIG_USER_NS is not set
44# CONFIG_AUDIT is not set
45# CONFIG_IKCONFIG is not set
46CONFIG_LOG_BUF_SHIFT=14
47CONFIG_SYSFS_DEPRECATED=y
48# CONFIG_RELAY is not set
49CONFIG_BLK_DEV_INITRD=y
50CONFIG_INITRAMFS_SOURCE=""
51CONFIG_CC_OPTIMIZE_FOR_SIZE=y
52CONFIG_SYSCTL=y
53CONFIG_EMBEDDED=y
54CONFIG_UID16=y
55CONFIG_SYSCTL_SYSCALL=y
56CONFIG_KALLSYMS=y
57# CONFIG_KALLSYMS_ALL is not set
58CONFIG_KALLSYMS_EXTRA_PASS=y
59CONFIG_HOTPLUG=y
60CONFIG_PRINTK=y
61CONFIG_BUG=y
62CONFIG_ELF_CORE=y
63CONFIG_BASE_FULL=y
64CONFIG_FUTEX=y
65CONFIG_ANON_INODES=y
66CONFIG_EPOLL=y
67CONFIG_SIGNALFD=y
68CONFIG_TIMERFD=y
69CONFIG_EVENTFD=y
70CONFIG_SHMEM=y
71CONFIG_VM_EVENT_COUNTERS=y
72CONFIG_SLAB=y
73# CONFIG_SLUB is not set
74# CONFIG_SLOB is not set
75CONFIG_RT_MUTEXES=y
76# CONFIG_TINY_SHMEM is not set
77CONFIG_BASE_SMALL=0
78CONFIG_MODULES=y
79CONFIG_MODULE_UNLOAD=y
80# CONFIG_MODULE_FORCE_UNLOAD is not set
81CONFIG_MODVERSIONS=y
82CONFIG_MODULE_SRCVERSION_ALL=y
83CONFIG_KMOD=y
84CONFIG_BLOCK=y
85# CONFIG_LBD is not set
86# CONFIG_BLK_DEV_IO_TRACE is not set
87# CONFIG_LSF is not set
88# CONFIG_BLK_DEV_BSG is not set
89
90#
91# IO Schedulers
92#
93CONFIG_IOSCHED_NOOP=y
94CONFIG_IOSCHED_AS=y
95CONFIG_IOSCHED_DEADLINE=y
96CONFIG_IOSCHED_CFQ=y
97CONFIG_DEFAULT_AS=y
98# CONFIG_DEFAULT_DEADLINE is not set
99# CONFIG_DEFAULT_CFQ is not set
100# CONFIG_DEFAULT_NOOP is not set
101CONFIG_DEFAULT_IOSCHED="anticipatory"
102
103#
104# System Type
105#
106# CONFIG_ARCH_AAEC2000 is not set
107# CONFIG_ARCH_INTEGRATOR is not set
108# CONFIG_ARCH_REALVIEW is not set
109# CONFIG_ARCH_VERSATILE is not set
110# CONFIG_ARCH_AT91 is not set
111# CONFIG_ARCH_CLPS7500 is not set
112# CONFIG_ARCH_CLPS711X is not set
113# CONFIG_ARCH_CO285 is not set
114# CONFIG_ARCH_EBSA110 is not set
115# CONFIG_ARCH_EP93XX is not set
116# CONFIG_ARCH_FOOTBRIDGE is not set
117# CONFIG_ARCH_NETX is not set
118# CONFIG_ARCH_H720X is not set
119# CONFIG_ARCH_IMX is not set
120# CONFIG_ARCH_IOP13XX is not set
121# CONFIG_ARCH_IOP32X is not set
122# CONFIG_ARCH_IOP33X is not set
123# CONFIG_ARCH_IXP23XX is not set
124# CONFIG_ARCH_IXP2000 is not set
125# CONFIG_ARCH_IXP4XX is not set
126# CONFIG_ARCH_L7200 is not set
127# CONFIG_ARCH_KS8695 is not set
128# CONFIG_ARCH_NS9XXX is not set
129# CONFIG_ARCH_MXC is not set
130# CONFIG_ARCH_PNX4008 is not set
131# CONFIG_ARCH_PXA is not set
132# CONFIG_ARCH_RPC is not set
133# CONFIG_ARCH_SA1100 is not set
134# CONFIG_ARCH_S3C2410 is not set
135# CONFIG_ARCH_SHARK is not set
136# CONFIG_ARCH_LH7A40X is not set
137# CONFIG_ARCH_DAVINCI is not set
138CONFIG_ARCH_OMAP=y
139
140#
141# TI OMAP Implementations
142#
143CONFIG_ARCH_OMAP_OTG=y
144# CONFIG_ARCH_OMAP1 is not set
145CONFIG_ARCH_OMAP2=y
146# CONFIG_ARCH_OMAP3 is not set
147
148#
149# OMAP Feature Selections
150#
151CONFIG_OMAP_DEBUG_DEVICES=y
152# CONFIG_OMAP_RESET_CLOCKS is not set
153CONFIG_OMAP_BOOT_TAG=y
154# CONFIG_OMAP_BOOT_REASON is not set
155# CONFIG_OMAP_COMPONENT_VERSION is not set
156# CONFIG_OMAP_GPIO_SWITCH is not set
157CONFIG_OMAP_MUX=y
158CONFIG_OMAP_MUX_DEBUG=y
159CONFIG_OMAP_MUX_WARNINGS=y
160# CONFIG_OMAP_STI is not set
161CONFIG_OMAP_MCBSP=y
162# CONFIG_OMAP_MMU_FWK is not set
163# CONFIG_OMAP_MBOX_FWK is not set
164CONFIG_OMAP_MPU_TIMER=y
165# CONFIG_OMAP_32K_TIMER is not set
166CONFIG_OMAP_DM_TIMER=y
167CONFIG_OMAP_LL_DEBUG_UART1=y
168# CONFIG_OMAP_LL_DEBUG_UART2 is not set
169# CONFIG_OMAP_LL_DEBUG_UART3 is not set
170CONFIG_OMAP_SERIAL_WAKE=y
171# CONFIG_OMAP_DSP is not set
172# CONFIG_MACH_OMAP_GENERIC is not set
173
174#
175# OMAP Core Type
176#
177CONFIG_ARCH_OMAP24XX=y
178CONFIG_ARCH_OMAP2420=y
179# CONFIG_ARCH_OMAP2430 is not set
180
181#
182# OMAP Board Type
183#
184# CONFIG_MACH_NOKIA_N800 is not set
185CONFIG_MACH_OMAP_H4=y
186# CONFIG_MACH_OMAP_H4_TUSB is not set
187# CONFIG_MACH_OMAP_H4_OTG is not set
188# CONFIG_MACH_OMAP2_H4_USB1 is not set
189# CONFIG_MACH_OMAP_APOLLON is not set
190# CONFIG_MACH_OMAP_APOLLON_PLUS is not set
191# CONFIG_MACH_OMAP_2430SDP is not set
192
193#
194# Boot options
195#
196
197#
198# Power management
199#
200
201#
202# Processor Type
203#
204CONFIG_CPU_32=y
205CONFIG_CPU_V6=y
206# CONFIG_CPU_32v6K is not set
207CONFIG_CPU_32v6=y
208CONFIG_CPU_ABRT_EV6=y
209CONFIG_CPU_PABRT_NOIFAR=y
210CONFIG_CPU_CACHE_V6=y
211CONFIG_CPU_CACHE_VIPT=y
212CONFIG_CPU_COPY_V6=y
213CONFIG_CPU_TLB_V6=y
214CONFIG_CPU_HAS_ASID=y
215CONFIG_CPU_CP15=y
216CONFIG_CPU_CP15_MMU=y
217
218#
219# Processor Features
220#
221CONFIG_ARM_THUMB=y
222# CONFIG_CPU_ICACHE_DISABLE is not set
223# CONFIG_CPU_DCACHE_DISABLE is not set
224# CONFIG_CPU_BPREDICT_DISABLE is not set
225# CONFIG_OUTER_CACHE is not set
226
227#
228# Bus support
229#
230# CONFIG_PCI_SYSCALL is not set
231# CONFIG_ARCH_SUPPORTS_MSI is not set
232
233#
234# PCCARD (PCMCIA/CardBus) support
235#
236# CONFIG_PCCARD is not set
237
238#
239# Kernel Features
240#
241# CONFIG_TICK_ONESHOT is not set
242# CONFIG_NO_HZ is not set
243# CONFIG_HIGH_RES_TIMERS is not set
244# CONFIG_PREEMPT is not set
245CONFIG_HZ=100
246CONFIG_AEABI=y
247CONFIG_OABI_COMPAT=y
248# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
249CONFIG_SELECT_MEMORY_MODEL=y
250CONFIG_FLATMEM_MANUAL=y
251# CONFIG_DISCONTIGMEM_MANUAL is not set
252# CONFIG_SPARSEMEM_MANUAL is not set
253CONFIG_FLATMEM=y
254CONFIG_FLAT_NODE_MEM_MAP=y
255# CONFIG_SPARSEMEM_STATIC is not set
256CONFIG_SPLIT_PTLOCK_CPUS=4
257# CONFIG_RESOURCES_64BIT is not set
258CONFIG_ZONE_DMA_FLAG=1
259CONFIG_BOUNCE=y
260CONFIG_VIRT_TO_BUS=y
261# CONFIG_LEDS is not set
262CONFIG_ALIGNMENT_TRAP=y
263
264#
265# Boot options
266#
267CONFIG_ZBOOT_ROM_TEXT=0x0
268CONFIG_ZBOOT_ROM_BSS=0x0
269CONFIG_CMDLINE="root=/dev/ram0 rw console=ttyS0,115200n8 initrd=0x80600000,8M ramdisk_size=8192"
270# CONFIG_XIP_KERNEL is not set
271# CONFIG_KEXEC is not set
272
273#
274# CPU Frequency scaling
275#
276# CONFIG_CPU_FREQ is not set
277
278#
279# Floating point emulation
280#
281
282#
283# At least one emulation must be selected
284#
285CONFIG_FPE_NWFPE=y
286# CONFIG_FPE_NWFPE_XP is not set
287# CONFIG_FPE_FASTFPE is not set
288# CONFIG_VFP is not set
289
290#
291# Userspace binary formats
292#
293CONFIG_BINFMT_ELF=y
294# CONFIG_BINFMT_AOUT is not set
295CONFIG_BINFMT_MISC=y
296
297#
298# Power management options
299#
300# CONFIG_PM is not set
301CONFIG_SUSPEND_UP_POSSIBLE=y
302
303#
304# Networking
305#
306CONFIG_NET=y
307
308#
309# Networking options
310#
311CONFIG_PACKET=y
312# CONFIG_PACKET_MMAP is not set
313CONFIG_UNIX=y
314CONFIG_XFRM=y
315# CONFIG_XFRM_USER is not set
316# CONFIG_XFRM_SUB_POLICY is not set
317# CONFIG_XFRM_MIGRATE is not set
318CONFIG_NET_KEY=y
319# CONFIG_NET_KEY_MIGRATE is not set
320CONFIG_INET=y
321# CONFIG_IP_MULTICAST is not set
322# CONFIG_IP_ADVANCED_ROUTER is not set
323CONFIG_IP_FIB_HASH=y
324CONFIG_IP_PNP=y
325CONFIG_IP_PNP_DHCP=y
326# CONFIG_IP_PNP_BOOTP is not set
327# CONFIG_IP_PNP_RARP is not set
328# CONFIG_NET_IPIP is not set
329# CONFIG_NET_IPGRE is not set
330# CONFIG_ARPD is not set
331# CONFIG_SYN_COOKIES is not set
332# CONFIG_INET_AH is not set
333# CONFIG_INET_ESP is not set
334# CONFIG_INET_IPCOMP is not set
335# CONFIG_INET_XFRM_TUNNEL is not set
336# CONFIG_INET_TUNNEL is not set
337CONFIG_INET_XFRM_MODE_TRANSPORT=y
338CONFIG_INET_XFRM_MODE_TUNNEL=y
339CONFIG_INET_XFRM_MODE_BEET=y
340CONFIG_INET_DIAG=y
341CONFIG_INET_TCP_DIAG=y
342# CONFIG_TCP_CONG_ADVANCED is not set
343CONFIG_TCP_CONG_CUBIC=y
344CONFIG_DEFAULT_TCP_CONG="cubic"
345# CONFIG_TCP_MD5SIG is not set
346# CONFIG_IPV6 is not set
347# CONFIG_INET6_XFRM_TUNNEL is not set
348# CONFIG_INET6_TUNNEL is not set
349# CONFIG_NETWORK_SECMARK is not set
350# CONFIG_NETFILTER is not set
351# CONFIG_IP_DCCP is not set
352# CONFIG_IP_SCTP is not set
353# CONFIG_TIPC is not set
354# CONFIG_ATM is not set
355# CONFIG_BRIDGE is not set
356# CONFIG_VLAN_8021Q is not set
357# CONFIG_DECNET is not set
358# CONFIG_LLC2 is not set
359# CONFIG_IPX is not set
360# CONFIG_ATALK is not set
361# CONFIG_X25 is not set
362# CONFIG_LAPB is not set
363# CONFIG_ECONET is not set
364# CONFIG_WAN_ROUTER is not set
365
366#
367# QoS and/or fair queueing
368#
369# CONFIG_NET_SCHED is not set
370
371#
372# Network testing
373#
374# CONFIG_NET_PKTGEN is not set
375# CONFIG_HAMRADIO is not set
376CONFIG_IRDA=y
377
378#
379# IrDA protocols
380#
381CONFIG_IRLAN=y
382CONFIG_IRCOMM=y
383# CONFIG_IRDA_ULTRA is not set
384
385#
386# IrDA options
387#
388# CONFIG_IRDA_CACHE_LAST_LSAP is not set
389# CONFIG_IRDA_FAST_RR is not set
390# CONFIG_IRDA_DEBUG is not set
391
392#
393# Infrared-port device drivers
394#
395
396#
397# SIR device drivers
398#
399# CONFIG_IRTTY_SIR is not set
400
401#
402# Dongle support
403#
404
405#
406# Old SIR device drivers
407#
408# CONFIG_IRPORT_SIR is not set
409
410#
411# Old Serial dongle support
412#
413
414#
415# FIR device drivers
416#
417CONFIG_OMAP_IR=y
418# CONFIG_BT is not set
419# CONFIG_AF_RXRPC is not set
420
421#
422# Wireless
423#
424# CONFIG_CFG80211 is not set
425# CONFIG_WIRELESS_EXT is not set
426# CONFIG_MAC80211 is not set
427# CONFIG_IEEE80211 is not set
428# CONFIG_RFKILL is not set
429# CONFIG_NET_9P is not set
430
431#
432# Device Drivers
433#
434
435#
436# Generic Driver Options
437#
438CONFIG_STANDALONE=y
439CONFIG_PREVENT_FIRMWARE_BUILD=y
440# CONFIG_FW_LOADER is not set
441# CONFIG_DEBUG_DRIVER is not set
442# CONFIG_DEBUG_DEVRES is not set
443# CONFIG_SYS_HYPERVISOR is not set
444# CONFIG_CONNECTOR is not set
445CONFIG_MTD=y
446# CONFIG_MTD_DEBUG is not set
447CONFIG_MTD_CONCAT=y
448CONFIG_MTD_PARTITIONS=y
449# CONFIG_MTD_REDBOOT_PARTS is not set
450CONFIG_MTD_CMDLINE_PARTS=y
451# CONFIG_MTD_AFS_PARTS is not set
452
453#
454# User Modules And Translation Layers
455#
456CONFIG_MTD_CHAR=y
457CONFIG_MTD_BLKDEVS=y
458CONFIG_MTD_BLOCK=y
459# CONFIG_FTL is not set
460# CONFIG_NFTL is not set
461# CONFIG_INFTL is not set
462# CONFIG_RFD_FTL is not set
463# CONFIG_SSFDC is not set
464
465#
466# RAM/ROM/Flash chip drivers
467#
468CONFIG_MTD_CFI=y
469# CONFIG_MTD_JEDECPROBE is not set
470CONFIG_MTD_GEN_PROBE=y
471# CONFIG_MTD_CFI_ADV_OPTIONS is not set
472CONFIG_MTD_MAP_BANK_WIDTH_1=y
473CONFIG_MTD_MAP_BANK_WIDTH_2=y
474CONFIG_MTD_MAP_BANK_WIDTH_4=y
475# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
476# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
477# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
478CONFIG_MTD_CFI_I1=y
479CONFIG_MTD_CFI_I2=y
480# CONFIG_MTD_CFI_I4 is not set
481# CONFIG_MTD_CFI_I8 is not set
482CONFIG_MTD_CFI_INTELEXT=y
483# CONFIG_MTD_CFI_AMDSTD is not set
484# CONFIG_MTD_CFI_STAA is not set
485CONFIG_MTD_CFI_UTIL=y
486# CONFIG_MTD_RAM is not set
487# CONFIG_MTD_ROM is not set
488# CONFIG_MTD_ABSENT is not set
489
490#
491# Mapping drivers for chip access
492#
493# CONFIG_MTD_COMPLEX_MAPPINGS is not set
494# CONFIG_MTD_PHYSMAP is not set
495# CONFIG_MTD_ARM_INTEGRATOR is not set
496CONFIG_MTD_OMAP_NOR=y
497# CONFIG_MTD_PLATRAM is not set
498
499#
500# Self-contained MTD device drivers
501#
502# CONFIG_MTD_SLRAM is not set
503# CONFIG_MTD_PHRAM is not set
504# CONFIG_MTD_MTDRAM is not set
505# CONFIG_MTD_BLOCK2MTD is not set
506
507#
508# Disk-On-Chip Device Drivers
509#
510# CONFIG_MTD_DOC2000 is not set
511# CONFIG_MTD_DOC2001 is not set
512# CONFIG_MTD_DOC2001PLUS is not set
513# CONFIG_MTD_NAND is not set
514# CONFIG_MTD_ONENAND is not set
515
516#
517# UBI - Unsorted block images
518#
519# CONFIG_MTD_UBI is not set
520# CONFIG_PARPORT is not set
521CONFIG_BLK_DEV=y
522# CONFIG_BLK_DEV_COW_COMMON is not set
523CONFIG_BLK_DEV_LOOP=y
524# CONFIG_BLK_DEV_CRYPTOLOOP is not set
525# CONFIG_BLK_DEV_NBD is not set
526CONFIG_BLK_DEV_RAM=y
527CONFIG_BLK_DEV_RAM_COUNT=16
528CONFIG_BLK_DEV_RAM_SIZE=16384
529CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
530# CONFIG_CDROM_PKTCDVD is not set
531# CONFIG_ATA_OVER_ETH is not set
532
533#
534# SCSI device support
535#
536# CONFIG_RAID_ATTRS is not set
537# CONFIG_SCSI is not set
538# CONFIG_SCSI_DMA is not set
539# CONFIG_SCSI_NETLINK is not set
540# CONFIG_ATA is not set
541# CONFIG_MD is not set
542CONFIG_NETDEVICES=y
543# CONFIG_NETDEVICES_MULTIQUEUE is not set
544# CONFIG_DUMMY is not set
545# CONFIG_BONDING is not set
546# CONFIG_MACVLAN is not set
547# CONFIG_EQUALIZER is not set
548# CONFIG_TUN is not set
549# CONFIG_PHYLIB is not set
550CONFIG_NET_ETHERNET=y
551CONFIG_MII=y
552# CONFIG_AX88796 is not set
553CONFIG_SMC91X=y
554# CONFIG_DM9000 is not set
555CONFIG_NETDEV_1000=y
556CONFIG_NETDEV_10000=y
557
558#
559# Wireless LAN
560#
561# CONFIG_WLAN_PRE80211 is not set
562# CONFIG_WLAN_80211 is not set
563# CONFIG_WAN is not set
564# CONFIG_PPP is not set
565# CONFIG_SLIP is not set
566# CONFIG_SHAPER is not set
567# CONFIG_NETCONSOLE is not set
568# CONFIG_NETPOLL is not set
569# CONFIG_NET_POLL_CONTROLLER is not set
570# CONFIG_ISDN is not set
571
572#
573# Input device support
574#
575CONFIG_INPUT=y
576# CONFIG_INPUT_FF_MEMLESS is not set
577# CONFIG_INPUT_POLLDEV is not set
578
579#
580# Userland interfaces
581#
582# CONFIG_INPUT_MOUSEDEV is not set
583# CONFIG_INPUT_JOYDEV is not set
584# CONFIG_INPUT_TSDEV is not set
585CONFIG_INPUT_EVDEV=y
586# CONFIG_INPUT_EVBUG is not set
587
588#
589# Input Device Drivers
590#
591CONFIG_INPUT_KEYBOARD=y
592# CONFIG_KEYBOARD_ATKBD is not set
593# CONFIG_KEYBOARD_SUNKBD is not set
594# CONFIG_KEYBOARD_LKKBD is not set
595# CONFIG_KEYBOARD_XTKBD is not set
596# CONFIG_KEYBOARD_NEWTON is not set
597# CONFIG_KEYBOARD_STOWAWAY is not set
598CONFIG_KEYBOARD_OMAP=y
599# CONFIG_KEYBOARD_GPIO is not set
600# CONFIG_INPUT_MOUSE is not set
601# CONFIG_INPUT_JOYSTICK is not set
602# CONFIG_INPUT_TABLET is not set
603# CONFIG_INPUT_TOUCHSCREEN is not set
604# CONFIG_INPUT_MISC is not set
605
606#
607# Hardware I/O ports
608#
609# CONFIG_SERIO is not set
610# CONFIG_GAMEPORT is not set
611
612#
613# Character devices
614#
615CONFIG_VT=y
616CONFIG_VT_CONSOLE=y
617CONFIG_HW_CONSOLE=y
618# CONFIG_VT_HW_CONSOLE_BINDING is not set
619# CONFIG_SERIAL_NONSTANDARD is not set
620
621#
622# Serial drivers
623#
624CONFIG_SERIAL_8250=y
625CONFIG_SERIAL_8250_CONSOLE=y
626CONFIG_SERIAL_8250_NR_UARTS=32
627CONFIG_SERIAL_8250_RUNTIME_UARTS=4
628CONFIG_SERIAL_8250_EXTENDED=y
629CONFIG_SERIAL_8250_MANY_PORTS=y
630CONFIG_SERIAL_8250_SHARE_IRQ=y
631CONFIG_SERIAL_8250_DETECT_IRQ=y
632CONFIG_SERIAL_8250_RSA=y
633
634#
635# Non-8250 serial port support
636#
637CONFIG_SERIAL_CORE=y
638CONFIG_SERIAL_CORE_CONSOLE=y
639CONFIG_UNIX98_PTYS=y
640# CONFIG_LEGACY_PTYS is not set
641# CONFIG_IPMI_HANDLER is not set
642CONFIG_WATCHDOG=y
643CONFIG_WATCHDOG_NOWAYOUT=y
644
645#
646# Watchdog Device Drivers
647#
648# CONFIG_SOFT_WATCHDOG is not set
649CONFIG_OMAP_WATCHDOG=y
650CONFIG_HW_RANDOM=m
651CONFIG_HW_RANDOM_OMAP=m
652# CONFIG_NVRAM is not set
653# CONFIG_R3964 is not set
654# CONFIG_RAW_DRIVER is not set
655# CONFIG_TCG_TPM is not set
656CONFIG_I2C=y
657CONFIG_I2C_BOARDINFO=y
658# CONFIG_I2C_CHARDEV is not set
659
660#
661# I2C Algorithms
662#
663# CONFIG_I2C_ALGOBIT is not set
664# CONFIG_I2C_ALGOPCF is not set
665# CONFIG_I2C_ALGOPCA is not set
666
667#
668# I2C Hardware Bus support
669#
670# CONFIG_I2C_GPIO is not set
671# CONFIG_I2C_OCORES is not set
672CONFIG_I2C_OMAP=y
673# CONFIG_I2C_PARPORT_LIGHT is not set
674# CONFIG_I2C_SIMTEC is not set
675# CONFIG_I2C_TAOS_EVM is not set
676# CONFIG_I2C_STUB is not set
677
678#
679# Miscellaneous I2C Chip support
680#
681# CONFIG_SENSORS_DS1337 is not set
682# CONFIG_SENSORS_DS1374 is not set
683# CONFIG_DS1682 is not set
684# CONFIG_SENSORS_EEPROM is not set
685# CONFIG_SENSORS_PCF8574 is not set
686# CONFIG_SENSORS_PCA9539 is not set
687# CONFIG_SENSORS_PCF8591 is not set
688# CONFIG_ISP1301_OMAP is not set
689# CONFIG_TPS65010 is not set
690# CONFIG_SENSORS_TLV320AIC23 is not set
691CONFIG_GPIOEXPANDER_OMAP=y
692# CONFIG_TWL4030_CORE is not set
693# CONFIG_SENSORS_MAX6875 is not set
694# CONFIG_SENSORS_TSL2550 is not set
695CONFIG_MENELAUS=y
696# CONFIG_I2C_DEBUG_CORE is not set
697# CONFIG_I2C_DEBUG_ALGO is not set
698# CONFIG_I2C_DEBUG_BUS is not set
699# CONFIG_I2C_DEBUG_CHIP is not set
700
701#
702# SPI support
703#
704# CONFIG_SPI is not set
705# CONFIG_SPI_MASTER is not set
706# CONFIG_W1 is not set
707# CONFIG_HWMON is not set
708CONFIG_MISC_DEVICES=y
709# CONFIG_EEPROM_93CX6 is not set
710
711#
712# Multifunction device drivers
713#
714# CONFIG_MFD_SM501 is not set
715# CONFIG_NEW_LEDS is not set
716
717#
718# Multimedia devices
719#
720# CONFIG_VIDEO_DEV is not set
721# CONFIG_DVB_CORE is not set
722CONFIG_DAB=y
723
724#
725# Graphics support
726#
727# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
728
729#
730# Display device support
731#
732# CONFIG_DISPLAY_SUPPORT is not set
733# CONFIG_VGASTATE is not set
734CONFIG_VIDEO_OUTPUT_CONTROL=m
735CONFIG_FB=y
736CONFIG_FIRMWARE_EDID=y
737# CONFIG_FB_DDC is not set
738# CONFIG_FB_CFB_FILLRECT is not set
739# CONFIG_FB_CFB_COPYAREA is not set
740# CONFIG_FB_CFB_IMAGEBLIT is not set
741# CONFIG_FB_SYS_FILLRECT is not set
742# CONFIG_FB_SYS_COPYAREA is not set
743# CONFIG_FB_SYS_IMAGEBLIT is not set
744# CONFIG_FB_SYS_FOPS is not set
745CONFIG_FB_DEFERRED_IO=y
746# CONFIG_FB_SVGALIB is not set
747# CONFIG_FB_MACMODES is not set
748# CONFIG_FB_BACKLIGHT is not set
749# CONFIG_FB_MODE_HELPERS is not set
750# CONFIG_FB_TILEBLITTING is not set
751
752#
753# Frame buffer hardware drivers
754#
755# CONFIG_FB_S1D13XXX is not set
756CONFIG_FB_OMAP=y
757# CONFIG_FB_OMAP_LCDC_EXTERNAL is not set
758# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set
759CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=2
760# CONFIG_FB_VIRTUAL is not set
761
762#
763# Console display driver support
764#
765# CONFIG_VGA_CONSOLE is not set
766CONFIG_DUMMY_CONSOLE=y
767CONFIG_FRAMEBUFFER_CONSOLE=y
768# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
769# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
770# CONFIG_FONTS is not set
771CONFIG_FONT_8x8=y
772CONFIG_FONT_8x16=y
773CONFIG_LOGO=y
774# CONFIG_LOGO_LINUX_MONO is not set
775# CONFIG_LOGO_LINUX_VGA16 is not set
776CONFIG_LOGO_LINUX_CLUT224=y
777
778#
779# Sound
780#
781# CONFIG_SOUND is not set
782CONFIG_HID_SUPPORT=y
783CONFIG_HID=y
784# CONFIG_HID_DEBUG is not set
785CONFIG_USB_SUPPORT=y
786CONFIG_USB_ARCH_HAS_HCD=y
787CONFIG_USB_ARCH_HAS_OHCI=y
788# CONFIG_USB_ARCH_HAS_EHCI is not set
789# CONFIG_USB is not set
790
791#
792# Enable Host or Gadget support to see Inventra options
793#
794
795#
796# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
797#
798
799#
800# USB Gadget Support
801#
802# CONFIG_USB_GADGET is not set
803CONFIG_MMC=y
804# CONFIG_MMC_DEBUG is not set
805# CONFIG_MMC_UNSAFE_RESUME is not set
806
807#
808# MMC/SD Card Drivers
809#
810CONFIG_MMC_BLOCK=y
811CONFIG_MMC_BLOCK_BOUNCE=y
812
813#
814# MMC/SD Host Controller Drivers
815#
816CONFIG_MMC_OMAP=y
817CONFIG_RTC_LIB=y
818# CONFIG_RTC_CLASS is not set
819
820#
821# DMA Engine support
822#
823# CONFIG_DMA_ENGINE is not set
824
825#
826# DMA Clients
827#
828
829#
830# DMA Devices
831#
832
833#
834# CBUS support
835#
836# CONFIG_CBUS is not set
837
838#
839# File systems
840#
841CONFIG_EXT2_FS=y
842# CONFIG_EXT2_FS_XATTR is not set
843# CONFIG_EXT2_FS_XIP is not set
844CONFIG_EXT3_FS=y
845# CONFIG_EXT3_FS_XATTR is not set
846# CONFIG_EXT4DEV_FS is not set
847CONFIG_JBD=y
848# CONFIG_JBD_DEBUG is not set
849# CONFIG_REISERFS_FS is not set
850# CONFIG_JFS_FS is not set
851# CONFIG_FS_POSIX_ACL is not set
852# CONFIG_XFS_FS is not set
853# CONFIG_GFS2_FS is not set
854# CONFIG_OCFS2_FS is not set
855# CONFIG_MINIX_FS is not set
856# CONFIG_ROMFS_FS is not set
857CONFIG_INOTIFY=y
858CONFIG_INOTIFY_USER=y
859CONFIG_QUOTA=y
860# CONFIG_QFMT_V1 is not set
861CONFIG_QFMT_V2=y
862CONFIG_QUOTACTL=y
863CONFIG_DNOTIFY=y
864# CONFIG_AUTOFS_FS is not set
865# CONFIG_AUTOFS4_FS is not set
866# CONFIG_FUSE_FS is not set
867
868#
869# CD-ROM/DVD Filesystems
870#
871# CONFIG_ISO9660_FS is not set
872# CONFIG_UDF_FS is not set
873
874#
875# DOS/FAT/NT Filesystems
876#
877CONFIG_FAT_FS=y
878CONFIG_MSDOS_FS=y
879CONFIG_VFAT_FS=y
880CONFIG_FAT_DEFAULT_CODEPAGE=437
881CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
882# CONFIG_NTFS_FS is not set
883
884#
885# Pseudo filesystems
886#
887CONFIG_PROC_FS=y
888CONFIG_PROC_SYSCTL=y
889CONFIG_SYSFS=y
890CONFIG_TMPFS=y
891# CONFIG_TMPFS_POSIX_ACL is not set
892# CONFIG_HUGETLB_PAGE is not set
893CONFIG_RAMFS=y
894# CONFIG_CONFIGFS_FS is not set
895
896#
897# Miscellaneous filesystems
898#
899# CONFIG_ADFS_FS is not set
900# CONFIG_AFFS_FS is not set
901# CONFIG_HFS_FS is not set
902# CONFIG_HFSPLUS_FS is not set
903# CONFIG_BEFS_FS is not set
904# CONFIG_BFS_FS is not set
905# CONFIG_EFS_FS is not set
906CONFIG_JFFS2_FS=y
907CONFIG_JFFS2_FS_DEBUG=0
908CONFIG_JFFS2_FS_WRITEBUFFER=y
909# CONFIG_JFFS2_SUMMARY is not set
910# CONFIG_JFFS2_FS_XATTR is not set
911# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
912CONFIG_JFFS2_ZLIB=y
913CONFIG_JFFS2_RTIME=y
914# CONFIG_JFFS2_RUBIN is not set
915# CONFIG_CRAMFS is not set
916# CONFIG_VXFS_FS is not set
917# CONFIG_HPFS_FS is not set
918# CONFIG_QNX4FS_FS is not set
919# CONFIG_SYSV_FS is not set
920# CONFIG_UFS_FS is not set
921
922#
923# Network File Systems
924#
925CONFIG_NFS_FS=y
926CONFIG_NFS_V3=y
927# CONFIG_NFS_V3_ACL is not set
928CONFIG_NFS_V4=y
929# CONFIG_NFS_DIRECTIO is not set
930# CONFIG_NFSD is not set
931CONFIG_ROOT_NFS=y
932CONFIG_LOCKD=y
933CONFIG_LOCKD_V4=y
934CONFIG_NFS_COMMON=y
935CONFIG_SUNRPC=y
936CONFIG_SUNRPC_GSS=y
937# CONFIG_SUNRPC_BIND34 is not set
938CONFIG_RPCSEC_GSS_KRB5=y
939# CONFIG_RPCSEC_GSS_SPKM3 is not set
940# CONFIG_SMB_FS is not set
941# CONFIG_CIFS is not set
942# CONFIG_NCP_FS is not set
943# CONFIG_CODA_FS is not set
944# CONFIG_AFS_FS is not set
945
946#
947# Partition Types
948#
949CONFIG_PARTITION_ADVANCED=y
950# CONFIG_ACORN_PARTITION is not set
951# CONFIG_OSF_PARTITION is not set
952# CONFIG_AMIGA_PARTITION is not set
953# CONFIG_ATARI_PARTITION is not set
954# CONFIG_MAC_PARTITION is not set
955CONFIG_MSDOS_PARTITION=y
956# CONFIG_BSD_DISKLABEL is not set
957# CONFIG_MINIX_SUBPARTITION is not set
958# CONFIG_SOLARIS_X86_PARTITION is not set
959# CONFIG_UNIXWARE_DISKLABEL is not set
960# CONFIG_LDM_PARTITION is not set
961# CONFIG_SGI_PARTITION is not set
962# CONFIG_ULTRIX_PARTITION is not set
963# CONFIG_SUN_PARTITION is not set
964# CONFIG_KARMA_PARTITION is not set
965# CONFIG_EFI_PARTITION is not set
966# CONFIG_SYSV68_PARTITION is not set
967
968#
969# Native Language Support
970#
971CONFIG_NLS=y
972CONFIG_NLS_DEFAULT="iso8859-1"
973CONFIG_NLS_CODEPAGE_437=y
974# CONFIG_NLS_CODEPAGE_737 is not set
975# CONFIG_NLS_CODEPAGE_775 is not set
976# CONFIG_NLS_CODEPAGE_850 is not set
977# CONFIG_NLS_CODEPAGE_852 is not set
978# CONFIG_NLS_CODEPAGE_855 is not set
979# CONFIG_NLS_CODEPAGE_857 is not set
980# CONFIG_NLS_CODEPAGE_860 is not set
981# CONFIG_NLS_CODEPAGE_861 is not set
982# CONFIG_NLS_CODEPAGE_862 is not set
983# CONFIG_NLS_CODEPAGE_863 is not set
984# CONFIG_NLS_CODEPAGE_864 is not set
985# CONFIG_NLS_CODEPAGE_865 is not set
986# CONFIG_NLS_CODEPAGE_866 is not set
987# CONFIG_NLS_CODEPAGE_869 is not set
988# CONFIG_NLS_CODEPAGE_936 is not set
989# CONFIG_NLS_CODEPAGE_950 is not set
990# CONFIG_NLS_CODEPAGE_932 is not set
991# CONFIG_NLS_CODEPAGE_949 is not set
992# CONFIG_NLS_CODEPAGE_874 is not set
993# CONFIG_NLS_ISO8859_8 is not set
994# CONFIG_NLS_CODEPAGE_1250 is not set
995# CONFIG_NLS_CODEPAGE_1251 is not set
996# CONFIG_NLS_ASCII is not set
997# CONFIG_NLS_ISO8859_1 is not set
998# CONFIG_NLS_ISO8859_2 is not set
999# CONFIG_NLS_ISO8859_3 is not set
1000# CONFIG_NLS_ISO8859_4 is not set
1001# CONFIG_NLS_ISO8859_5 is not set
1002# CONFIG_NLS_ISO8859_6 is not set
1003# CONFIG_NLS_ISO8859_7 is not set
1004# CONFIG_NLS_ISO8859_9 is not set
1005# CONFIG_NLS_ISO8859_13 is not set
1006# CONFIG_NLS_ISO8859_14 is not set
1007# CONFIG_NLS_ISO8859_15 is not set
1008# CONFIG_NLS_KOI8_R is not set
1009# CONFIG_NLS_KOI8_U is not set
1010# CONFIG_NLS_UTF8 is not set
1011
1012#
1013# Distributed Lock Manager
1014#
1015# CONFIG_DLM is not set
1016
1017#
1018# Profiling support
1019#
1020# CONFIG_PROFILING is not set
1021
1022#
1023# Kernel hacking
1024#
1025# CONFIG_PRINTK_TIME is not set
1026CONFIG_ENABLE_MUST_CHECK=y
1027CONFIG_MAGIC_SYSRQ=y
1028# CONFIG_UNUSED_SYMBOLS is not set
1029# CONFIG_DEBUG_FS is not set
1030# CONFIG_HEADERS_CHECK is not set
1031CONFIG_DEBUG_KERNEL=y
1032# CONFIG_DEBUG_SHIRQ is not set
1033CONFIG_DETECT_SOFTLOCKUP=y
1034CONFIG_SCHED_DEBUG=y
1035# CONFIG_SCHEDSTATS is not set
1036# CONFIG_TIMER_STATS is not set
1037# CONFIG_DEBUG_SLAB is not set
1038# CONFIG_DEBUG_RT_MUTEXES is not set
1039# CONFIG_RT_MUTEX_TESTER is not set
1040# CONFIG_DEBUG_SPINLOCK is not set
1041CONFIG_DEBUG_MUTEXES=y
1042# CONFIG_DEBUG_LOCK_ALLOC is not set
1043# CONFIG_PROVE_LOCKING is not set
1044# CONFIG_LOCK_STAT is not set
1045# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1046# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1047# CONFIG_DEBUG_KOBJECT is not set
1048# CONFIG_DEBUG_BUGVERBOSE is not set
1049# CONFIG_DEBUG_INFO is not set
1050# CONFIG_DEBUG_VM is not set
1051# CONFIG_DEBUG_LIST is not set
1052CONFIG_FRAME_POINTER=y
1053CONFIG_FORCED_INLINING=y
1054# CONFIG_RCU_TORTURE_TEST is not set
1055# CONFIG_FAULT_INJECTION is not set
1056# CONFIG_DEBUG_USER is not set
1057# CONFIG_DEBUG_ERRORS is not set
1058CONFIG_DEBUG_LL=y
1059# CONFIG_DEBUG_ICEDCC is not set
1060
1061#
1062# Security options
1063#
1064# CONFIG_KEYS is not set
1065# CONFIG_SECURITY is not set
1066CONFIG_CRYPTO=y
1067CONFIG_CRYPTO_ALGAPI=y
1068CONFIG_CRYPTO_BLKCIPHER=y
1069CONFIG_CRYPTO_MANAGER=y
1070# CONFIG_CRYPTO_HMAC is not set
1071# CONFIG_CRYPTO_XCBC is not set
1072# CONFIG_CRYPTO_NULL is not set
1073# CONFIG_CRYPTO_MD4 is not set
1074CONFIG_CRYPTO_MD5=y
1075# CONFIG_CRYPTO_SHA1 is not set
1076# CONFIG_CRYPTO_SHA256 is not set
1077# CONFIG_CRYPTO_SHA512 is not set
1078# CONFIG_CRYPTO_WP512 is not set
1079# CONFIG_CRYPTO_TGR192 is not set
1080# CONFIG_CRYPTO_GF128MUL is not set
1081CONFIG_CRYPTO_ECB=m
1082CONFIG_CRYPTO_CBC=y
1083CONFIG_CRYPTO_PCBC=m
1084# CONFIG_CRYPTO_LRW is not set
1085# CONFIG_CRYPTO_CRYPTD is not set
1086CONFIG_CRYPTO_DES=y
1087# CONFIG_CRYPTO_FCRYPT is not set
1088# CONFIG_CRYPTO_BLOWFISH is not set
1089# CONFIG_CRYPTO_TWOFISH is not set
1090# CONFIG_CRYPTO_SERPENT is not set
1091# CONFIG_CRYPTO_AES is not set
1092# CONFIG_CRYPTO_CAST5 is not set
1093# CONFIG_CRYPTO_CAST6 is not set
1094# CONFIG_CRYPTO_TEA is not set
1095# CONFIG_CRYPTO_ARC4 is not set
1096# CONFIG_CRYPTO_KHAZAD is not set
1097# CONFIG_CRYPTO_ANUBIS is not set
1098# CONFIG_CRYPTO_DEFLATE is not set
1099# CONFIG_CRYPTO_MICHAEL_MIC is not set
1100# CONFIG_CRYPTO_CRC32C is not set
1101# CONFIG_CRYPTO_CAMELLIA is not set
1102# CONFIG_CRYPTO_TEST is not set
1103CONFIG_CRYPTO_HW=y
1104
1105#
1106# Library routines
1107#
1108CONFIG_BITREVERSE=y
1109CONFIG_CRC_CCITT=y
1110# CONFIG_CRC16 is not set
1111# CONFIG_CRC_ITU_T is not set
1112CONFIG_CRC32=y
1113# CONFIG_CRC7 is not set
1114CONFIG_LIBCRC32C=y
1115CONFIG_ZLIB_INFLATE=y
1116CONFIG_ZLIB_DEFLATE=y
1117CONFIG_PLIST=y
1118CONFIG_HAS_IOMEM=y
1119CONFIG_HAS_IOPORT=y
1120CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/omap_innovator_1510_defconfig b/arch/arm/configs/omap_innovator_1510_defconfig
new file mode 100644
index 000000000000..55b2611bd90a
--- /dev/null
+++ b/arch/arm/configs/omap_innovator_1510_defconfig
@@ -0,0 +1,1253 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.23-rc6-omap1
4# Tue Sep 18 11:45:02 2007
5#
6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8CONFIG_GENERIC_GPIO=y
9CONFIG_GENERIC_TIME=y
10CONFIG_GENERIC_CLOCKEVENTS=y
11CONFIG_MMU=y
12# CONFIG_NO_IOPORT is not set
13CONFIG_GENERIC_HARDIRQS=y
14CONFIG_STACKTRACE_SUPPORT=y
15CONFIG_LOCKDEP_SUPPORT=y
16CONFIG_TRACE_IRQFLAGS_SUPPORT=y
17CONFIG_HARDIRQS_SW_RESEND=y
18CONFIG_GENERIC_IRQ_PROBE=y
19CONFIG_RWSEM_GENERIC_SPINLOCK=y
20# CONFIG_ARCH_HAS_ILOG2_U32 is not set
21# CONFIG_ARCH_HAS_ILOG2_U64 is not set
22CONFIG_GENERIC_HWEIGHT=y
23CONFIG_GENERIC_CALIBRATE_DELAY=y
24CONFIG_ZONE_DMA=y
25CONFIG_VECTORS_BASE=0xffff0000
26CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
27
28#
29# General setup
30#
31CONFIG_EXPERIMENTAL=y
32CONFIG_BROKEN_ON_SMP=y
33CONFIG_LOCK_KERNEL=y
34CONFIG_INIT_ENV_ARG_LIMIT=32
35CONFIG_LOCALVERSION=""
36CONFIG_LOCALVERSION_AUTO=y
37CONFIG_SWAP=y
38CONFIG_SYSVIPC=y
39CONFIG_SYSVIPC_SYSCTL=y
40# CONFIG_POSIX_MQUEUE is not set
41# CONFIG_BSD_PROCESS_ACCT is not set
42# CONFIG_TASKSTATS is not set
43# CONFIG_USER_NS is not set
44# CONFIG_AUDIT is not set
45# CONFIG_IKCONFIG is not set
46CONFIG_LOG_BUF_SHIFT=14
47CONFIG_SYSFS_DEPRECATED=y
48# CONFIG_RELAY is not set
49CONFIG_BLK_DEV_INITRD=y
50CONFIG_INITRAMFS_SOURCE=""
51CONFIG_CC_OPTIMIZE_FOR_SIZE=y
52CONFIG_SYSCTL=y
53# CONFIG_EMBEDDED is not set
54CONFIG_UID16=y
55CONFIG_SYSCTL_SYSCALL=y
56CONFIG_KALLSYMS=y
57# CONFIG_KALLSYMS_ALL is not set
58# CONFIG_KALLSYMS_EXTRA_PASS is not set
59CONFIG_HOTPLUG=y
60CONFIG_PRINTK=y
61CONFIG_BUG=y
62CONFIG_ELF_CORE=y
63CONFIG_BASE_FULL=y
64CONFIG_FUTEX=y
65CONFIG_ANON_INODES=y
66CONFIG_EPOLL=y
67CONFIG_SIGNALFD=y
68CONFIG_TIMERFD=y
69CONFIG_EVENTFD=y
70CONFIG_SHMEM=y
71CONFIG_VM_EVENT_COUNTERS=y
72CONFIG_SLAB=y
73# CONFIG_SLUB is not set
74# CONFIG_SLOB is not set
75CONFIG_RT_MUTEXES=y
76# CONFIG_TINY_SHMEM is not set
77CONFIG_BASE_SMALL=0
78CONFIG_MODULES=y
79CONFIG_MODULE_UNLOAD=y
80# CONFIG_MODULE_FORCE_UNLOAD is not set
81# CONFIG_MODVERSIONS is not set
82# CONFIG_MODULE_SRCVERSION_ALL is not set
83CONFIG_KMOD=y
84CONFIG_BLOCK=y
85# CONFIG_LBD is not set
86# CONFIG_BLK_DEV_IO_TRACE is not set
87# CONFIG_LSF is not set
88# CONFIG_BLK_DEV_BSG is not set
89
90#
91# IO Schedulers
92#
93CONFIG_IOSCHED_NOOP=y
94CONFIG_IOSCHED_AS=y
95CONFIG_IOSCHED_DEADLINE=y
96CONFIG_IOSCHED_CFQ=y
97# CONFIG_DEFAULT_AS is not set
98# CONFIG_DEFAULT_DEADLINE is not set
99CONFIG_DEFAULT_CFQ=y
100# CONFIG_DEFAULT_NOOP is not set
101CONFIG_DEFAULT_IOSCHED="cfq"
102
103#
104# System Type
105#
106# CONFIG_ARCH_AAEC2000 is not set
107# CONFIG_ARCH_INTEGRATOR is not set
108# CONFIG_ARCH_REALVIEW is not set
109# CONFIG_ARCH_VERSATILE is not set
110# CONFIG_ARCH_AT91 is not set
111# CONFIG_ARCH_CLPS7500 is not set
112# CONFIG_ARCH_CLPS711X is not set
113# CONFIG_ARCH_CO285 is not set
114# CONFIG_ARCH_EBSA110 is not set
115# CONFIG_ARCH_EP93XX is not set
116# CONFIG_ARCH_FOOTBRIDGE is not set
117# CONFIG_ARCH_NETX is not set
118# CONFIG_ARCH_H720X is not set
119# CONFIG_ARCH_IMX is not set
120# CONFIG_ARCH_IOP13XX is not set
121# CONFIG_ARCH_IOP32X is not set
122# CONFIG_ARCH_IOP33X is not set
123# CONFIG_ARCH_IXP23XX is not set
124# CONFIG_ARCH_IXP2000 is not set
125# CONFIG_ARCH_IXP4XX is not set
126# CONFIG_ARCH_L7200 is not set
127# CONFIG_ARCH_KS8695 is not set
128# CONFIG_ARCH_NS9XXX is not set
129# CONFIG_ARCH_MXC is not set
130# CONFIG_ARCH_PNX4008 is not set
131# CONFIG_ARCH_PXA is not set
132# CONFIG_ARCH_RPC is not set
133# CONFIG_ARCH_SA1100 is not set
134# CONFIG_ARCH_S3C2410 is not set
135# CONFIG_ARCH_SHARK is not set
136# CONFIG_ARCH_LH7A40X is not set
137# CONFIG_ARCH_DAVINCI is not set
138CONFIG_ARCH_OMAP=y
139
140#
141# TI OMAP Implementations
142#
143CONFIG_ARCH_OMAP1=y
144# CONFIG_ARCH_OMAP2 is not set
145# CONFIG_ARCH_OMAP3 is not set
146
147#
148# OMAP Feature Selections
149#
150# CONFIG_OMAP_RESET_CLOCKS is not set
151# CONFIG_OMAP_BOOT_TAG is not set
152# CONFIG_OMAP_GPIO_SWITCH is not set
153CONFIG_OMAP_MUX=y
154# CONFIG_OMAP_MUX_DEBUG is not set
155CONFIG_OMAP_MUX_WARNINGS=y
156CONFIG_OMAP_MCBSP=y
157# CONFIG_OMAP_MMU_FWK is not set
158# CONFIG_OMAP_MBOX_FWK is not set
159CONFIG_OMAP_MPU_TIMER=y
160# CONFIG_OMAP_32K_TIMER is not set
161CONFIG_OMAP_LL_DEBUG_UART1=y
162# CONFIG_OMAP_LL_DEBUG_UART2 is not set
163# CONFIG_OMAP_LL_DEBUG_UART3 is not set
164CONFIG_OMAP_SERIAL_WAKE=y
165# CONFIG_OMAP_DSP is not set
166
167#
168# OMAP Core Type
169#
170# CONFIG_ARCH_OMAP730 is not set
171CONFIG_ARCH_OMAP15XX=y
172# CONFIG_ARCH_OMAP16XX is not set
173
174#
175# OMAP Board Type
176#
177CONFIG_MACH_OMAP_INNOVATOR=y
178# CONFIG_MACH_VOICEBLUE is not set
179# CONFIG_MACH_OMAP_PALMTE is not set
180# CONFIG_MACH_OMAP_PALMZ71 is not set
181# CONFIG_MACH_OMAP_PALMTT is not set
182# CONFIG_MACH_SX1 is not set
183# CONFIG_MACH_AMS_DELTA is not set
184# CONFIG_MACH_OMAP_GENERIC is not set
185
186#
187# OMAP CPU Speed
188#
189# CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER is not set
190CONFIG_OMAP_ARM_168MHZ=y
191# CONFIG_OMAP_ARM_150MHZ is not set
192# CONFIG_OMAP_ARM_120MHZ is not set
193# CONFIG_OMAP_ARM_60MHZ is not set
194# CONFIG_OMAP_ARM_30MHZ is not set
195# CONFIG_MACH_OMAP_APOLLON_PLUS is not set
196
197#
198# Boot options
199#
200
201#
202# Power management
203#
204
205#
206# Processor Type
207#
208CONFIG_CPU_32=y
209CONFIG_CPU_ARM925T=y
210CONFIG_CPU_32v4T=y
211CONFIG_CPU_ABRT_EV4T=y
212CONFIG_CPU_PABRT_NOIFAR=y
213CONFIG_CPU_CACHE_V4WT=y
214CONFIG_CPU_CACHE_VIVT=y
215CONFIG_CPU_COPY_V4WB=y
216CONFIG_CPU_TLB_V4WBI=y
217CONFIG_CPU_CP15=y
218CONFIG_CPU_CP15_MMU=y
219
220#
221# Processor Features
222#
223CONFIG_ARM_THUMB=y
224# CONFIG_CPU_ICACHE_DISABLE is not set
225# CONFIG_CPU_DCACHE_DISABLE is not set
226CONFIG_CPU_DCACHE_WRITETHROUGH=y
227# CONFIG_OUTER_CACHE is not set
228
229#
230# Bus support
231#
232# CONFIG_PCI_SYSCALL is not set
233# CONFIG_ARCH_SUPPORTS_MSI is not set
234
235#
236# PCCARD (PCMCIA/CardBus) support
237#
238# CONFIG_PCCARD is not set
239
240#
241# Kernel Features
242#
243# CONFIG_TICK_ONESHOT is not set
244# CONFIG_NO_HZ is not set
245# CONFIG_HIGH_RES_TIMERS is not set
246CONFIG_PREEMPT=y
247CONFIG_HZ=100
248# CONFIG_AEABI is not set
249# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
250CONFIG_SELECT_MEMORY_MODEL=y
251CONFIG_FLATMEM_MANUAL=y
252# CONFIG_DISCONTIGMEM_MANUAL is not set
253# CONFIG_SPARSEMEM_MANUAL is not set
254CONFIG_FLATMEM=y
255CONFIG_FLAT_NODE_MEM_MAP=y
256# CONFIG_SPARSEMEM_STATIC is not set
257CONFIG_SPLIT_PTLOCK_CPUS=4096
258# CONFIG_RESOURCES_64BIT is not set
259CONFIG_ZONE_DMA_FLAG=1
260CONFIG_BOUNCE=y
261CONFIG_VIRT_TO_BUS=y
262CONFIG_LEDS=y
263CONFIG_ALIGNMENT_TRAP=y
264
265#
266# Boot options
267#
268CONFIG_ZBOOT_ROM_TEXT=0x0
269CONFIG_ZBOOT_ROM_BSS=0x0
270CONFIG_CMDLINE="console=ttyS0,115200n8 root=/dev/nfs ip=bootp noinitrd"
271# CONFIG_XIP_KERNEL is not set
272# CONFIG_KEXEC is not set
273
274#
275# CPU Frequency scaling
276#
277# CONFIG_CPU_FREQ is not set
278
279#
280# Floating point emulation
281#
282
283#
284# At least one emulation must be selected
285#
286CONFIG_FPE_NWFPE=y
287# CONFIG_FPE_NWFPE_XP is not set
288# CONFIG_FPE_FASTFPE is not set
289
290#
291# Userspace binary formats
292#
293CONFIG_BINFMT_ELF=y
294# CONFIG_BINFMT_AOUT is not set
295# CONFIG_BINFMT_MISC is not set
296# CONFIG_ARTHUR is not set
297
298#
299# Power management options
300#
301CONFIG_PM=y
302# CONFIG_PM_LEGACY is not set
303# CONFIG_PM_DEBUG is not set
304CONFIG_PM_SLEEP=y
305CONFIG_SUSPEND_UP_POSSIBLE=y
306CONFIG_SUSPEND=y
307# CONFIG_APM_EMULATION is not set
308
309#
310# Networking
311#
312CONFIG_NET=y
313
314#
315# Networking options
316#
317CONFIG_PACKET=y
318# CONFIG_PACKET_MMAP is not set
319CONFIG_UNIX=y
320CONFIG_XFRM=y
321# CONFIG_XFRM_USER is not set
322# CONFIG_XFRM_SUB_POLICY is not set
323# CONFIG_XFRM_MIGRATE is not set
324# CONFIG_NET_KEY is not set
325CONFIG_INET=y
326CONFIG_IP_MULTICAST=y
327# CONFIG_IP_ADVANCED_ROUTER is not set
328CONFIG_IP_FIB_HASH=y
329CONFIG_IP_PNP=y
330CONFIG_IP_PNP_DHCP=y
331CONFIG_IP_PNP_BOOTP=y
332# CONFIG_IP_PNP_RARP is not set
333# CONFIG_NET_IPIP is not set
334# CONFIG_NET_IPGRE is not set
335# CONFIG_IP_MROUTE is not set
336# CONFIG_ARPD is not set
337# CONFIG_SYN_COOKIES is not set
338# CONFIG_INET_AH is not set
339# CONFIG_INET_ESP is not set
340# CONFIG_INET_IPCOMP is not set
341# CONFIG_INET_XFRM_TUNNEL is not set
342# CONFIG_INET_TUNNEL is not set
343CONFIG_INET_XFRM_MODE_TRANSPORT=y
344CONFIG_INET_XFRM_MODE_TUNNEL=y
345CONFIG_INET_XFRM_MODE_BEET=y
346CONFIG_INET_DIAG=y
347CONFIG_INET_TCP_DIAG=y
348# CONFIG_TCP_CONG_ADVANCED is not set
349CONFIG_TCP_CONG_CUBIC=y
350CONFIG_DEFAULT_TCP_CONG="cubic"
351# CONFIG_TCP_MD5SIG is not set
352# CONFIG_IPV6 is not set
353# CONFIG_INET6_XFRM_TUNNEL is not set
354# CONFIG_INET6_TUNNEL is not set
355# CONFIG_NETWORK_SECMARK is not set
356# CONFIG_NETFILTER is not set
357# CONFIG_IP_DCCP is not set
358# CONFIG_IP_SCTP is not set
359# CONFIG_TIPC is not set
360# CONFIG_ATM is not set
361# CONFIG_BRIDGE is not set
362# CONFIG_VLAN_8021Q is not set
363# CONFIG_DECNET is not set
364# CONFIG_LLC2 is not set
365# CONFIG_IPX is not set
366# CONFIG_ATALK is not set
367# CONFIG_X25 is not set
368# CONFIG_LAPB is not set
369# CONFIG_ECONET is not set
370# CONFIG_WAN_ROUTER is not set
371
372#
373# QoS and/or fair queueing
374#
375# CONFIG_NET_SCHED is not set
376
377#
378# Network testing
379#
380# CONFIG_NET_PKTGEN is not set
381# CONFIG_HAMRADIO is not set
382# CONFIG_IRDA is not set
383# CONFIG_BT is not set
384# CONFIG_AF_RXRPC is not set
385
386#
387# Wireless
388#
389# CONFIG_CFG80211 is not set
390# CONFIG_WIRELESS_EXT is not set
391# CONFIG_MAC80211 is not set
392# CONFIG_IEEE80211 is not set
393# CONFIG_RFKILL is not set
394# CONFIG_NET_9P is not set
395
396#
397# Device Drivers
398#
399
400#
401# Generic Driver Options
402#
403CONFIG_STANDALONE=y
404CONFIG_PREVENT_FIRMWARE_BUILD=y
405# CONFIG_FW_LOADER is not set
406# CONFIG_DEBUG_DRIVER is not set
407# CONFIG_DEBUG_DEVRES is not set
408# CONFIG_SYS_HYPERVISOR is not set
409# CONFIG_CONNECTOR is not set
410# CONFIG_MTD is not set
411# CONFIG_PARPORT is not set
412CONFIG_BLK_DEV=y
413# CONFIG_BLK_DEV_COW_COMMON is not set
414CONFIG_BLK_DEV_LOOP=y
415# CONFIG_BLK_DEV_CRYPTOLOOP is not set
416# CONFIG_BLK_DEV_NBD is not set
417# CONFIG_BLK_DEV_UB is not set
418CONFIG_BLK_DEV_RAM=y
419CONFIG_BLK_DEV_RAM_COUNT=16
420CONFIG_BLK_DEV_RAM_SIZE=8192
421CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
422# CONFIG_CDROM_PKTCDVD is not set
423# CONFIG_ATA_OVER_ETH is not set
424
425#
426# SCSI device support
427#
428# CONFIG_RAID_ATTRS is not set
429CONFIG_SCSI=y
430CONFIG_SCSI_DMA=y
431# CONFIG_SCSI_TGT is not set
432# CONFIG_SCSI_NETLINK is not set
433CONFIG_SCSI_PROC_FS=y
434
435#
436# SCSI support type (disk, tape, CD-ROM)
437#
438CONFIG_BLK_DEV_SD=y
439CONFIG_CHR_DEV_ST=y
440# CONFIG_CHR_DEV_OSST is not set
441CONFIG_BLK_DEV_SR=y
442# CONFIG_BLK_DEV_SR_VENDOR is not set
443CONFIG_CHR_DEV_SG=y
444# CONFIG_CHR_DEV_SCH is not set
445
446#
447# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
448#
449CONFIG_SCSI_MULTI_LUN=y
450# CONFIG_SCSI_CONSTANTS is not set
451# CONFIG_SCSI_LOGGING is not set
452# CONFIG_SCSI_SCAN_ASYNC is not set
453CONFIG_SCSI_WAIT_SCAN=m
454
455#
456# SCSI Transports
457#
458# CONFIG_SCSI_SPI_ATTRS is not set
459# CONFIG_SCSI_FC_ATTRS is not set
460# CONFIG_SCSI_ISCSI_ATTRS is not set
461# CONFIG_SCSI_SAS_LIBSAS is not set
462CONFIG_SCSI_LOWLEVEL=y
463# CONFIG_ISCSI_TCP is not set
464# CONFIG_SCSI_DEBUG is not set
465# CONFIG_ATA is not set
466# CONFIG_MD is not set
467CONFIG_NETDEVICES=y
468# CONFIG_NETDEVICES_MULTIQUEUE is not set
469# CONFIG_DUMMY is not set
470# CONFIG_BONDING is not set
471# CONFIG_MACVLAN is not set
472# CONFIG_EQUALIZER is not set
473# CONFIG_TUN is not set
474# CONFIG_PHYLIB is not set
475CONFIG_NET_ETHERNET=y
476CONFIG_MII=y
477# CONFIG_AX88796 is not set
478CONFIG_SMC91X=y
479# CONFIG_DM9000 is not set
480CONFIG_NETDEV_1000=y
481CONFIG_NETDEV_10000=y
482
483#
484# Wireless LAN
485#
486# CONFIG_WLAN_PRE80211 is not set
487# CONFIG_WLAN_80211 is not set
488
489#
490# USB Network Adapters
491#
492# CONFIG_USB_CATC is not set
493# CONFIG_USB_KAWETH is not set
494# CONFIG_USB_PEGASUS is not set
495CONFIG_USB_RTL8150=y
496CONFIG_USB_USBNET_MII=y
497CONFIG_USB_USBNET=y
498CONFIG_USB_NET_AX8817X=y
499CONFIG_USB_NET_CDCETHER=y
500# CONFIG_USB_NET_DM9601 is not set
501# CONFIG_USB_NET_GL620A is not set
502CONFIG_USB_NET_NET1080=y
503# CONFIG_USB_NET_PLUSB is not set
504# CONFIG_USB_NET_MCS7830 is not set
505# CONFIG_USB_NET_RNDIS_HOST is not set
506# CONFIG_USB_NET_CDC_SUBSET is not set
507CONFIG_USB_NET_ZAURUS=y
508# CONFIG_WAN is not set
509CONFIG_PPP=y
510CONFIG_PPP_MULTILINK=y
511# CONFIG_PPP_FILTER is not set
512CONFIG_PPP_ASYNC=y
513# CONFIG_PPP_SYNC_TTY is not set
514CONFIG_PPP_DEFLATE=y
515CONFIG_PPP_BSDCOMP=y
516# CONFIG_PPP_MPPE is not set
517# CONFIG_PPPOE is not set
518# CONFIG_PPPOL2TP is not set
519# CONFIG_SLIP is not set
520CONFIG_SLHC=y
521# CONFIG_SHAPER is not set
522# CONFIG_NETCONSOLE is not set
523# CONFIG_NETPOLL is not set
524# CONFIG_NET_POLL_CONTROLLER is not set
525# CONFIG_ISDN is not set
526
527#
528# Input device support
529#
530CONFIG_INPUT=y
531# CONFIG_INPUT_FF_MEMLESS is not set
532# CONFIG_INPUT_POLLDEV is not set
533
534#
535# Userland interfaces
536#
537CONFIG_INPUT_MOUSEDEV=y
538CONFIG_INPUT_MOUSEDEV_PSAUX=y
539CONFIG_INPUT_MOUSEDEV_SCREEN_X=240
540CONFIG_INPUT_MOUSEDEV_SCREEN_Y=320
541# CONFIG_INPUT_JOYDEV is not set
542# CONFIG_INPUT_TSDEV is not set
543# CONFIG_INPUT_EVDEV is not set
544# CONFIG_INPUT_EVBUG is not set
545
546#
547# Input Device Drivers
548#
549CONFIG_INPUT_KEYBOARD=y
550# CONFIG_KEYBOARD_ATKBD is not set
551# CONFIG_KEYBOARD_SUNKBD is not set
552# CONFIG_KEYBOARD_LKKBD is not set
553# CONFIG_KEYBOARD_XTKBD is not set
554# CONFIG_KEYBOARD_NEWTON is not set
555# CONFIG_KEYBOARD_STOWAWAY is not set
556CONFIG_KEYBOARD_OMAP=y
557CONFIG_OMAP_PS2=m
558# CONFIG_KEYBOARD_GPIO is not set
559# CONFIG_INPUT_MOUSE is not set
560# CONFIG_INPUT_JOYSTICK is not set
561# CONFIG_INPUT_TABLET is not set
562# CONFIG_INPUT_TOUCHSCREEN is not set
563# CONFIG_INPUT_MISC is not set
564
565#
566# Hardware I/O ports
567#
568CONFIG_SERIO=y
569CONFIG_SERIO_SERPORT=y
570# CONFIG_SERIO_RAW is not set
571# CONFIG_GAMEPORT is not set
572
573#
574# Character devices
575#
576CONFIG_VT=y
577CONFIG_VT_CONSOLE=y
578CONFIG_HW_CONSOLE=y
579# CONFIG_VT_HW_CONSOLE_BINDING is not set
580# CONFIG_SERIAL_NONSTANDARD is not set
581
582#
583# Serial drivers
584#
585CONFIG_SERIAL_8250=y
586CONFIG_SERIAL_8250_CONSOLE=y
587CONFIG_SERIAL_8250_NR_UARTS=4
588CONFIG_SERIAL_8250_RUNTIME_UARTS=4
589# CONFIG_SERIAL_8250_EXTENDED is not set
590
591#
592# Non-8250 serial port support
593#
594CONFIG_SERIAL_CORE=y
595CONFIG_SERIAL_CORE_CONSOLE=y
596CONFIG_UNIX98_PTYS=y
597# CONFIG_LEGACY_PTYS is not set
598# CONFIG_IPMI_HANDLER is not set
599# CONFIG_WATCHDOG is not set
600CONFIG_HW_RANDOM=m
601# CONFIG_NVRAM is not set
602# CONFIG_R3964 is not set
603# CONFIG_RAW_DRIVER is not set
604# CONFIG_TCG_TPM is not set
605CONFIG_I2C=y
606CONFIG_I2C_BOARDINFO=y
607# CONFIG_I2C_CHARDEV is not set
608
609#
610# I2C Algorithms
611#
612# CONFIG_I2C_ALGOBIT is not set
613# CONFIG_I2C_ALGOPCF is not set
614# CONFIG_I2C_ALGOPCA is not set
615
616#
617# I2C Hardware Bus support
618#
619# CONFIG_I2C_GPIO is not set
620# CONFIG_I2C_OCORES is not set
621# CONFIG_I2C_OMAP is not set
622# CONFIG_I2C_PARPORT_LIGHT is not set
623# CONFIG_I2C_SIMTEC is not set
624# CONFIG_I2C_TAOS_EVM is not set
625# CONFIG_I2C_STUB is not set
626# CONFIG_I2C_TINY_USB is not set
627
628#
629# Miscellaneous I2C Chip support
630#
631# CONFIG_SENSORS_DS1337 is not set
632# CONFIG_SENSORS_DS1374 is not set
633# CONFIG_DS1682 is not set
634# CONFIG_SENSORS_EEPROM is not set
635# CONFIG_SENSORS_PCF8574 is not set
636# CONFIG_SENSORS_PCA9539 is not set
637# CONFIG_SENSORS_PCF8591 is not set
638# CONFIG_TPS65010 is not set
639# CONFIG_SENSORS_MAX6875 is not set
640# CONFIG_SENSORS_TSL2550 is not set
641# CONFIG_I2C_DEBUG_CORE is not set
642# CONFIG_I2C_DEBUG_ALGO is not set
643# CONFIG_I2C_DEBUG_BUS is not set
644# CONFIG_I2C_DEBUG_CHIP is not set
645
646#
647# SPI support
648#
649# CONFIG_SPI is not set
650# CONFIG_SPI_MASTER is not set
651# CONFIG_W1 is not set
652CONFIG_HWMON=y
653# CONFIG_HWMON_VID is not set
654# CONFIG_SENSORS_ABITUGURU is not set
655# CONFIG_SENSORS_ABITUGURU3 is not set
656# CONFIG_SENSORS_AD7418 is not set
657# CONFIG_SENSORS_ADM1021 is not set
658# CONFIG_SENSORS_ADM1025 is not set
659# CONFIG_SENSORS_ADM1026 is not set
660# CONFIG_SENSORS_ADM1029 is not set
661# CONFIG_SENSORS_ADM1031 is not set
662# CONFIG_SENSORS_ADM9240 is not set
663# CONFIG_SENSORS_ASB100 is not set
664# CONFIG_SENSORS_ATXP1 is not set
665# CONFIG_SENSORS_DS1621 is not set
666# CONFIG_SENSORS_F71805F is not set
667# CONFIG_SENSORS_FSCHER is not set
668# CONFIG_SENSORS_FSCPOS is not set
669# CONFIG_SENSORS_GL518SM is not set
670# CONFIG_SENSORS_GL520SM is not set
671# CONFIG_SENSORS_IT87 is not set
672# CONFIG_SENSORS_LM63 is not set
673# CONFIG_SENSORS_LM75 is not set
674# CONFIG_SENSORS_LM77 is not set
675# CONFIG_SENSORS_LM78 is not set
676# CONFIG_SENSORS_LM80 is not set
677# CONFIG_SENSORS_LM83 is not set
678# CONFIG_SENSORS_LM85 is not set
679# CONFIG_SENSORS_LM87 is not set
680# CONFIG_SENSORS_LM90 is not set
681# CONFIG_SENSORS_LM92 is not set
682# CONFIG_SENSORS_LM93 is not set
683# CONFIG_SENSORS_MAX1619 is not set
684# CONFIG_SENSORS_MAX6650 is not set
685# CONFIG_SENSORS_PC87360 is not set
686# CONFIG_SENSORS_PC87427 is not set
687# CONFIG_SENSORS_DME1737 is not set
688# CONFIG_SENSORS_SMSC47M1 is not set
689# CONFIG_SENSORS_SMSC47M192 is not set
690# CONFIG_SENSORS_SMSC47B397 is not set
691# CONFIG_SENSORS_THMC50 is not set
692# CONFIG_SENSORS_VT1211 is not set
693# CONFIG_SENSORS_W83781D is not set
694# CONFIG_SENSORS_W83791D is not set
695# CONFIG_SENSORS_W83792D is not set
696# CONFIG_SENSORS_W83793 is not set
697# CONFIG_SENSORS_W83L785TS is not set
698# CONFIG_SENSORS_W83627HF is not set
699# CONFIG_SENSORS_W83627EHF is not set
700# CONFIG_HWMON_DEBUG_CHIP is not set
701CONFIG_MISC_DEVICES=y
702# CONFIG_EEPROM_93CX6 is not set
703
704#
705# Multifunction device drivers
706#
707# CONFIG_MFD_SM501 is not set
708# CONFIG_NEW_LEDS is not set
709
710#
711# Multimedia devices
712#
713# CONFIG_VIDEO_DEV is not set
714# CONFIG_DVB_CORE is not set
715CONFIG_DAB=y
716# CONFIG_USB_DABUSB is not set
717
718#
719# Graphics support
720#
721# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
722
723#
724# Display device support
725#
726# CONFIG_DISPLAY_SUPPORT is not set
727# CONFIG_VGASTATE is not set
728CONFIG_VIDEO_OUTPUT_CONTROL=m
729CONFIG_FB=y
730# CONFIG_FIRMWARE_EDID is not set
731# CONFIG_FB_DDC is not set
732# CONFIG_FB_CFB_FILLRECT is not set
733# CONFIG_FB_CFB_COPYAREA is not set
734# CONFIG_FB_CFB_IMAGEBLIT is not set
735# CONFIG_FB_SYS_FILLRECT is not set
736# CONFIG_FB_SYS_COPYAREA is not set
737# CONFIG_FB_SYS_IMAGEBLIT is not set
738# CONFIG_FB_SYS_FOPS is not set
739CONFIG_FB_DEFERRED_IO=y
740# CONFIG_FB_SVGALIB is not set
741# CONFIG_FB_MACMODES is not set
742# CONFIG_FB_BACKLIGHT is not set
743# CONFIG_FB_MODE_HELPERS is not set
744# CONFIG_FB_TILEBLITTING is not set
745
746#
747# Frame buffer hardware drivers
748#
749# CONFIG_FB_S1D13XXX is not set
750CONFIG_FB_OMAP=y
751# CONFIG_FB_OMAP_LCDC_EXTERNAL is not set
752# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set
753CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=2
754# CONFIG_FB_OMAP_DMA_TUNE is not set
755# CONFIG_FB_VIRTUAL is not set
756
757#
758# Console display driver support
759#
760# CONFIG_VGA_CONSOLE is not set
761CONFIG_DUMMY_CONSOLE=y
762CONFIG_FRAMEBUFFER_CONSOLE=y
763# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
764# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
765CONFIG_FONTS=y
766CONFIG_FONT_8x8=y
767CONFIG_FONT_8x16=y
768# CONFIG_FONT_6x11 is not set
769# CONFIG_FONT_7x14 is not set
770# CONFIG_FONT_PEARL_8x8 is not set
771# CONFIG_FONT_ACORN_8x8 is not set
772# CONFIG_FONT_MINI_4x6 is not set
773# CONFIG_FONT_SUN8x16 is not set
774# CONFIG_FONT_SUN12x22 is not set
775# CONFIG_FONT_10x18 is not set
776CONFIG_LOGO=y
777CONFIG_LOGO_LINUX_MONO=y
778CONFIG_LOGO_LINUX_VGA16=y
779CONFIG_LOGO_LINUX_CLUT224=y
780
781#
782# Sound
783#
784# CONFIG_SOUND is not set
785CONFIG_HID_SUPPORT=y
786CONFIG_HID=y
787# CONFIG_HID_DEBUG is not set
788
789#
790# USB Input Devices
791#
792CONFIG_USB_HID=y
793# CONFIG_USB_HIDINPUT_POWERBOOK is not set
794# CONFIG_HID_FF is not set
795# CONFIG_USB_HIDDEV is not set
796CONFIG_USB_SUPPORT=y
797CONFIG_USB_ARCH_HAS_HCD=y
798CONFIG_USB_ARCH_HAS_OHCI=y
799# CONFIG_USB_ARCH_HAS_EHCI is not set
800CONFIG_USB=y
801CONFIG_USB_DEBUG=y
802
803#
804# Miscellaneous USB options
805#
806CONFIG_USB_DEVICEFS=y
807# CONFIG_USB_DEVICE_CLASS is not set
808# CONFIG_USB_DYNAMIC_MINORS is not set
809CONFIG_USB_SUSPEND=y
810# CONFIG_USB_PERSIST is not set
811# CONFIG_USB_OTG is not set
812
813#
814# USB Host Controller Drivers
815#
816# CONFIG_USB_ISP116X_HCD is not set
817CONFIG_USB_OHCI_HCD=y
818# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
819# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
820CONFIG_USB_OHCI_LITTLE_ENDIAN=y
821# CONFIG_USB_SL811_HCD is not set
822# CONFIG_USB_R8A66597_HCD is not set
823# CONFIG_USB_MUSB_HDRC is not set
824
825#
826# USB Device Class drivers
827#
828# CONFIG_USB_ACM is not set
829# CONFIG_USB_PRINTER is not set
830
831#
832# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
833#
834
835#
836# may also be needed; see USB_STORAGE Help for more information
837#
838CONFIG_USB_STORAGE=y
839# CONFIG_USB_STORAGE_DEBUG is not set
840CONFIG_USB_STORAGE_DATAFAB=y
841CONFIG_USB_STORAGE_FREECOM=y
842CONFIG_USB_STORAGE_DPCM=y
843# CONFIG_USB_STORAGE_USBAT is not set
844CONFIG_USB_STORAGE_SDDR09=y
845CONFIG_USB_STORAGE_SDDR55=y
846CONFIG_USB_STORAGE_JUMPSHOT=y
847# CONFIG_USB_STORAGE_ALAUDA is not set
848# CONFIG_USB_STORAGE_KARMA is not set
849# CONFIG_USB_LIBUSUAL is not set
850
851#
852# USB Imaging devices
853#
854# CONFIG_USB_MDC800 is not set
855# CONFIG_USB_MICROTEK is not set
856CONFIG_USB_MON=y
857
858#
859# USB port drivers
860#
861
862#
863# USB Serial Converter support
864#
865# CONFIG_USB_SERIAL is not set
866
867#
868# USB Miscellaneous drivers
869#
870# CONFIG_USB_EMI62 is not set
871# CONFIG_USB_EMI26 is not set
872# CONFIG_USB_ADUTUX is not set
873# CONFIG_USB_AUERSWALD is not set
874# CONFIG_USB_RIO500 is not set
875# CONFIG_USB_LEGOTOWER is not set
876# CONFIG_USB_LCD is not set
877# CONFIG_USB_BERRY_CHARGE is not set
878# CONFIG_USB_LED is not set
879# CONFIG_USB_CYPRESS_CY7C63 is not set
880# CONFIG_USB_CYTHERM is not set
881# CONFIG_USB_PHIDGET is not set
882# CONFIG_USB_IDMOUSE is not set
883# CONFIG_USB_FTDI_ELAN is not set
884# CONFIG_USB_APPLEDISPLAY is not set
885# CONFIG_USB_LD is not set
886# CONFIG_USB_TRANCEVIBRATOR is not set
887# CONFIG_USB_IOWARRIOR is not set
888# CONFIG_USB_TEST is not set
889
890#
891# USB DSL modem support
892#
893
894#
895# USB Gadget Support
896#
897# CONFIG_USB_GADGET is not set
898CONFIG_MMC=y
899# CONFIG_MMC_DEBUG is not set
900# CONFIG_MMC_UNSAFE_RESUME is not set
901
902#
903# MMC/SD Card Drivers
904#
905CONFIG_MMC_BLOCK=y
906CONFIG_MMC_BLOCK_BOUNCE=y
907
908#
909# MMC/SD Host Controller Drivers
910#
911CONFIG_MMC_OMAP=y
912CONFIG_RTC_LIB=y
913CONFIG_RTC_CLASS=y
914CONFIG_RTC_HCTOSYS=y
915CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
916# CONFIG_RTC_DEBUG is not set
917
918#
919# RTC interfaces
920#
921CONFIG_RTC_INTF_SYSFS=y
922CONFIG_RTC_INTF_PROC=y
923CONFIG_RTC_INTF_DEV=y
924# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
925# CONFIG_RTC_DRV_TEST is not set
926
927#
928# I2C RTC drivers
929#
930# CONFIG_RTC_DRV_DS1307 is not set
931# CONFIG_RTC_DRV_DS1672 is not set
932# CONFIG_RTC_DRV_MAX6900 is not set
933# CONFIG_RTC_DRV_RS5C372 is not set
934# CONFIG_RTC_DRV_ISL1208 is not set
935# CONFIG_RTC_DRV_X1205 is not set
936# CONFIG_RTC_DRV_PCF8563 is not set
937# CONFIG_RTC_DRV_PCF8583 is not set
938# CONFIG_RTC_DRV_M41T80 is not set
939
940#
941# SPI RTC drivers
942#
943
944#
945# Platform RTC drivers
946#
947# CONFIG_RTC_DRV_CMOS is not set
948# CONFIG_RTC_DRV_DS1553 is not set
949# CONFIG_RTC_DRV_STK17TA8 is not set
950# CONFIG_RTC_DRV_DS1742 is not set
951# CONFIG_RTC_DRV_M48T86 is not set
952# CONFIG_RTC_DRV_M48T59 is not set
953# CONFIG_RTC_DRV_V3020 is not set
954
955#
956# on-CPU RTC drivers
957#
958CONFIG_RTC_DRV_OMAP=y
959
960#
961# DMA Engine support
962#
963# CONFIG_DMA_ENGINE is not set
964
965#
966# DMA Clients
967#
968
969#
970# DMA Devices
971#
972
973#
974# CBUS support
975#
976# CONFIG_CBUS is not set
977
978#
979# File systems
980#
981CONFIG_EXT2_FS=y
982# CONFIG_EXT2_FS_XATTR is not set
983# CONFIG_EXT2_FS_XIP is not set
984CONFIG_EXT3_FS=y
985CONFIG_EXT3_FS_XATTR=y
986# CONFIG_EXT3_FS_POSIX_ACL is not set
987# CONFIG_EXT3_FS_SECURITY is not set
988# CONFIG_EXT4DEV_FS is not set
989CONFIG_JBD=y
990# CONFIG_JBD_DEBUG is not set
991CONFIG_FS_MBCACHE=y
992# CONFIG_REISERFS_FS is not set
993# CONFIG_JFS_FS is not set
994# CONFIG_FS_POSIX_ACL is not set
995# CONFIG_XFS_FS is not set
996# CONFIG_GFS2_FS is not set
997# CONFIG_OCFS2_FS is not set
998# CONFIG_MINIX_FS is not set
999# CONFIG_ROMFS_FS is not set
1000CONFIG_INOTIFY=y
1001CONFIG_INOTIFY_USER=y
1002# CONFIG_QUOTA is not set
1003CONFIG_DNOTIFY=y
1004CONFIG_AUTOFS_FS=y
1005CONFIG_AUTOFS4_FS=y
1006# CONFIG_FUSE_FS is not set
1007
1008#
1009# CD-ROM/DVD Filesystems
1010#
1011CONFIG_ISO9660_FS=y
1012CONFIG_JOLIET=y
1013# CONFIG_ZISOFS is not set
1014# CONFIG_UDF_FS is not set
1015
1016#
1017# DOS/FAT/NT Filesystems
1018#
1019CONFIG_FAT_FS=m
1020CONFIG_MSDOS_FS=m
1021CONFIG_VFAT_FS=m
1022CONFIG_FAT_DEFAULT_CODEPAGE=437
1023CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
1024# CONFIG_NTFS_FS is not set
1025
1026#
1027# Pseudo filesystems
1028#
1029CONFIG_PROC_FS=y
1030CONFIG_PROC_SYSCTL=y
1031CONFIG_SYSFS=y
1032CONFIG_TMPFS=y
1033# CONFIG_TMPFS_POSIX_ACL is not set
1034# CONFIG_HUGETLB_PAGE is not set
1035CONFIG_RAMFS=y
1036# CONFIG_CONFIGFS_FS is not set
1037
1038#
1039# Miscellaneous filesystems
1040#
1041# CONFIG_ADFS_FS is not set
1042# CONFIG_AFFS_FS is not set
1043# CONFIG_HFS_FS is not set
1044# CONFIG_HFSPLUS_FS is not set
1045# CONFIG_BEFS_FS is not set
1046# CONFIG_BFS_FS is not set
1047# CONFIG_EFS_FS is not set
1048# CONFIG_CRAMFS is not set
1049# CONFIG_VXFS_FS is not set
1050# CONFIG_HPFS_FS is not set
1051# CONFIG_QNX4FS_FS is not set
1052# CONFIG_SYSV_FS is not set
1053# CONFIG_UFS_FS is not set
1054
1055#
1056# Network File Systems
1057#
1058CONFIG_NFS_FS=y
1059CONFIG_NFS_V3=y
1060# CONFIG_NFS_V3_ACL is not set
1061CONFIG_NFS_V4=y
1062# CONFIG_NFS_DIRECTIO is not set
1063# CONFIG_NFSD is not set
1064CONFIG_ROOT_NFS=y
1065CONFIG_LOCKD=y
1066CONFIG_LOCKD_V4=y
1067CONFIG_NFS_COMMON=y
1068CONFIG_SUNRPC=y
1069CONFIG_SUNRPC_GSS=y
1070# CONFIG_SUNRPC_BIND34 is not set
1071CONFIG_RPCSEC_GSS_KRB5=y
1072# CONFIG_RPCSEC_GSS_SPKM3 is not set
1073# CONFIG_SMB_FS is not set
1074# CONFIG_CIFS is not set
1075# CONFIG_NCP_FS is not set
1076# CONFIG_CODA_FS is not set
1077# CONFIG_AFS_FS is not set
1078
1079#
1080# Partition Types
1081#
1082CONFIG_PARTITION_ADVANCED=y
1083# CONFIG_ACORN_PARTITION is not set
1084# CONFIG_OSF_PARTITION is not set
1085# CONFIG_AMIGA_PARTITION is not set
1086# CONFIG_ATARI_PARTITION is not set
1087# CONFIG_MAC_PARTITION is not set
1088CONFIG_MSDOS_PARTITION=y
1089# CONFIG_BSD_DISKLABEL is not set
1090# CONFIG_MINIX_SUBPARTITION is not set
1091# CONFIG_SOLARIS_X86_PARTITION is not set
1092# CONFIG_UNIXWARE_DISKLABEL is not set
1093# CONFIG_LDM_PARTITION is not set
1094# CONFIG_SGI_PARTITION is not set
1095# CONFIG_ULTRIX_PARTITION is not set
1096# CONFIG_SUN_PARTITION is not set
1097# CONFIG_KARMA_PARTITION is not set
1098# CONFIG_EFI_PARTITION is not set
1099# CONFIG_SYSV68_PARTITION is not set
1100
1101#
1102# Native Language Support
1103#
1104CONFIG_NLS=y
1105CONFIG_NLS_DEFAULT="iso8859-1"
1106# CONFIG_NLS_CODEPAGE_437 is not set
1107# CONFIG_NLS_CODEPAGE_737 is not set
1108# CONFIG_NLS_CODEPAGE_775 is not set
1109# CONFIG_NLS_CODEPAGE_850 is not set
1110# CONFIG_NLS_CODEPAGE_852 is not set
1111# CONFIG_NLS_CODEPAGE_855 is not set
1112# CONFIG_NLS_CODEPAGE_857 is not set
1113# CONFIG_NLS_CODEPAGE_860 is not set
1114# CONFIG_NLS_CODEPAGE_861 is not set
1115# CONFIG_NLS_CODEPAGE_862 is not set
1116# CONFIG_NLS_CODEPAGE_863 is not set
1117# CONFIG_NLS_CODEPAGE_864 is not set
1118# CONFIG_NLS_CODEPAGE_865 is not set
1119# CONFIG_NLS_CODEPAGE_866 is not set
1120# CONFIG_NLS_CODEPAGE_869 is not set
1121# CONFIG_NLS_CODEPAGE_936 is not set
1122# CONFIG_NLS_CODEPAGE_950 is not set
1123# CONFIG_NLS_CODEPAGE_932 is not set
1124# CONFIG_NLS_CODEPAGE_949 is not set
1125# CONFIG_NLS_CODEPAGE_874 is not set
1126# CONFIG_NLS_ISO8859_8 is not set
1127# CONFIG_NLS_CODEPAGE_1250 is not set
1128# CONFIG_NLS_CODEPAGE_1251 is not set
1129# CONFIG_NLS_ASCII is not set
1130# CONFIG_NLS_ISO8859_1 is not set
1131# CONFIG_NLS_ISO8859_2 is not set
1132# CONFIG_NLS_ISO8859_3 is not set
1133# CONFIG_NLS_ISO8859_4 is not set
1134# CONFIG_NLS_ISO8859_5 is not set
1135# CONFIG_NLS_ISO8859_6 is not set
1136# CONFIG_NLS_ISO8859_7 is not set
1137# CONFIG_NLS_ISO8859_9 is not set
1138# CONFIG_NLS_ISO8859_13 is not set
1139# CONFIG_NLS_ISO8859_14 is not set
1140# CONFIG_NLS_ISO8859_15 is not set
1141# CONFIG_NLS_KOI8_R is not set
1142# CONFIG_NLS_KOI8_U is not set
1143# CONFIG_NLS_UTF8 is not set
1144
1145#
1146# Distributed Lock Manager
1147#
1148# CONFIG_DLM is not set
1149
1150#
1151# Profiling support
1152#
1153# CONFIG_PROFILING is not set
1154
1155#
1156# Kernel hacking
1157#
1158# CONFIG_PRINTK_TIME is not set
1159CONFIG_ENABLE_MUST_CHECK=y
1160CONFIG_MAGIC_SYSRQ=y
1161# CONFIG_UNUSED_SYMBOLS is not set
1162# CONFIG_DEBUG_FS is not set
1163# CONFIG_HEADERS_CHECK is not set
1164CONFIG_DEBUG_KERNEL=y
1165# CONFIG_DEBUG_SHIRQ is not set
1166CONFIG_DETECT_SOFTLOCKUP=y
1167CONFIG_SCHED_DEBUG=y
1168# CONFIG_SCHEDSTATS is not set
1169# CONFIG_TIMER_STATS is not set
1170# CONFIG_DEBUG_SLAB is not set
1171CONFIG_DEBUG_PREEMPT=y
1172# CONFIG_DEBUG_RT_MUTEXES is not set
1173# CONFIG_RT_MUTEX_TESTER is not set
1174# CONFIG_DEBUG_SPINLOCK is not set
1175# CONFIG_DEBUG_MUTEXES is not set
1176# CONFIG_DEBUG_LOCK_ALLOC is not set
1177# CONFIG_PROVE_LOCKING is not set
1178# CONFIG_LOCK_STAT is not set
1179# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1180# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1181# CONFIG_DEBUG_KOBJECT is not set
1182CONFIG_DEBUG_BUGVERBOSE=y
1183# CONFIG_DEBUG_INFO is not set
1184# CONFIG_DEBUG_VM is not set
1185# CONFIG_DEBUG_LIST is not set
1186CONFIG_FRAME_POINTER=y
1187CONFIG_FORCED_INLINING=y
1188# CONFIG_RCU_TORTURE_TEST is not set
1189# CONFIG_FAULT_INJECTION is not set
1190# CONFIG_DEBUG_USER is not set
1191# CONFIG_DEBUG_ERRORS is not set
1192# CONFIG_DEBUG_LL is not set
1193
1194#
1195# Security options
1196#
1197# CONFIG_KEYS is not set
1198# CONFIG_SECURITY is not set
1199CONFIG_CRYPTO=y
1200CONFIG_CRYPTO_ALGAPI=y
1201CONFIG_CRYPTO_BLKCIPHER=y
1202CONFIG_CRYPTO_MANAGER=y
1203# CONFIG_CRYPTO_HMAC is not set
1204# CONFIG_CRYPTO_XCBC is not set
1205# CONFIG_CRYPTO_NULL is not set
1206# CONFIG_CRYPTO_MD4 is not set
1207CONFIG_CRYPTO_MD5=y
1208# CONFIG_CRYPTO_SHA1 is not set
1209# CONFIG_CRYPTO_SHA256 is not set
1210# CONFIG_CRYPTO_SHA512 is not set
1211# CONFIG_CRYPTO_WP512 is not set
1212# CONFIG_CRYPTO_TGR192 is not set
1213# CONFIG_CRYPTO_GF128MUL is not set
1214CONFIG_CRYPTO_ECB=m
1215CONFIG_CRYPTO_CBC=y
1216CONFIG_CRYPTO_PCBC=m
1217# CONFIG_CRYPTO_LRW is not set
1218# CONFIG_CRYPTO_CRYPTD is not set
1219CONFIG_CRYPTO_DES=y
1220# CONFIG_CRYPTO_FCRYPT is not set
1221# CONFIG_CRYPTO_BLOWFISH is not set
1222# CONFIG_CRYPTO_TWOFISH is not set
1223# CONFIG_CRYPTO_SERPENT is not set
1224# CONFIG_CRYPTO_AES is not set
1225# CONFIG_CRYPTO_CAST5 is not set
1226# CONFIG_CRYPTO_CAST6 is not set
1227# CONFIG_CRYPTO_TEA is not set
1228# CONFIG_CRYPTO_ARC4 is not set
1229# CONFIG_CRYPTO_KHAZAD is not set
1230# CONFIG_CRYPTO_ANUBIS is not set
1231# CONFIG_CRYPTO_DEFLATE is not set
1232# CONFIG_CRYPTO_MICHAEL_MIC is not set
1233# CONFIG_CRYPTO_CRC32C is not set
1234# CONFIG_CRYPTO_CAMELLIA is not set
1235# CONFIG_CRYPTO_TEST is not set
1236CONFIG_CRYPTO_HW=y
1237
1238#
1239# Library routines
1240#
1241CONFIG_BITREVERSE=y
1242CONFIG_CRC_CCITT=y
1243# CONFIG_CRC16 is not set
1244# CONFIG_CRC_ITU_T is not set
1245CONFIG_CRC32=y
1246# CONFIG_CRC7 is not set
1247# CONFIG_LIBCRC32C is not set
1248CONFIG_ZLIB_INFLATE=y
1249CONFIG_ZLIB_DEFLATE=y
1250CONFIG_PLIST=y
1251CONFIG_HAS_IOMEM=y
1252CONFIG_HAS_IOPORT=y
1253CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/omap_innovator_1610_defconfig b/arch/arm/configs/omap_innovator_1610_defconfig
new file mode 100644
index 000000000000..95d9f2be53e0
--- /dev/null
+++ b/arch/arm/configs/omap_innovator_1610_defconfig
@@ -0,0 +1,839 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.23-rc6-omap1
4# Tue Sep 18 11:45:05 2007
5#
6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8CONFIG_GENERIC_GPIO=y
9CONFIG_GENERIC_TIME=y
10CONFIG_GENERIC_CLOCKEVENTS=y
11CONFIG_MMU=y
12# CONFIG_NO_IOPORT is not set
13CONFIG_GENERIC_HARDIRQS=y
14CONFIG_STACKTRACE_SUPPORT=y
15CONFIG_LOCKDEP_SUPPORT=y
16CONFIG_TRACE_IRQFLAGS_SUPPORT=y
17CONFIG_HARDIRQS_SW_RESEND=y
18CONFIG_GENERIC_IRQ_PROBE=y
19CONFIG_RWSEM_GENERIC_SPINLOCK=y
20# CONFIG_ARCH_HAS_ILOG2_U32 is not set
21# CONFIG_ARCH_HAS_ILOG2_U64 is not set
22CONFIG_GENERIC_HWEIGHT=y
23CONFIG_GENERIC_CALIBRATE_DELAY=y
24CONFIG_ZONE_DMA=y
25CONFIG_VECTORS_BASE=0xffff0000
26CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
27
28#
29# General setup
30#
31CONFIG_EXPERIMENTAL=y
32CONFIG_BROKEN_ON_SMP=y
33CONFIG_INIT_ENV_ARG_LIMIT=32
34CONFIG_LOCALVERSION=""
35CONFIG_LOCALVERSION_AUTO=y
36CONFIG_SWAP=y
37CONFIG_SYSVIPC=y
38CONFIG_SYSVIPC_SYSCTL=y
39# CONFIG_POSIX_MQUEUE is not set
40# CONFIG_BSD_PROCESS_ACCT is not set
41# CONFIG_TASKSTATS is not set
42# CONFIG_USER_NS is not set
43# CONFIG_AUDIT is not set
44# CONFIG_IKCONFIG is not set
45CONFIG_LOG_BUF_SHIFT=14
46CONFIG_SYSFS_DEPRECATED=y
47# CONFIG_RELAY is not set
48CONFIG_BLK_DEV_INITRD=y
49CONFIG_INITRAMFS_SOURCE=""
50CONFIG_CC_OPTIMIZE_FOR_SIZE=y
51CONFIG_SYSCTL=y
52# CONFIG_EMBEDDED is not set
53CONFIG_UID16=y
54CONFIG_SYSCTL_SYSCALL=y
55CONFIG_KALLSYMS=y
56# CONFIG_KALLSYMS_EXTRA_PASS is not set
57CONFIG_HOTPLUG=y
58CONFIG_PRINTK=y
59CONFIG_BUG=y
60CONFIG_ELF_CORE=y
61CONFIG_BASE_FULL=y
62CONFIG_FUTEX=y
63CONFIG_ANON_INODES=y
64CONFIG_EPOLL=y
65CONFIG_SIGNALFD=y
66CONFIG_TIMERFD=y
67CONFIG_EVENTFD=y
68CONFIG_SHMEM=y
69CONFIG_VM_EVENT_COUNTERS=y
70CONFIG_SLUB_DEBUG=y
71# CONFIG_SLAB is not set
72CONFIG_SLUB=y
73# CONFIG_SLOB is not set
74CONFIG_RT_MUTEXES=y
75# CONFIG_TINY_SHMEM is not set
76CONFIG_BASE_SMALL=0
77CONFIG_MODULES=y
78CONFIG_MODULE_UNLOAD=y
79# CONFIG_MODULE_FORCE_UNLOAD is not set
80# CONFIG_MODVERSIONS is not set
81# CONFIG_MODULE_SRCVERSION_ALL is not set
82CONFIG_KMOD=y
83CONFIG_BLOCK=y
84# CONFIG_LBD is not set
85# CONFIG_BLK_DEV_IO_TRACE is not set
86# CONFIG_LSF is not set
87# CONFIG_BLK_DEV_BSG is not set
88
89#
90# IO Schedulers
91#
92CONFIG_IOSCHED_NOOP=y
93CONFIG_IOSCHED_AS=y
94CONFIG_IOSCHED_DEADLINE=y
95CONFIG_IOSCHED_CFQ=y
96# CONFIG_DEFAULT_AS is not set
97# CONFIG_DEFAULT_DEADLINE is not set
98CONFIG_DEFAULT_CFQ=y
99# CONFIG_DEFAULT_NOOP is not set
100CONFIG_DEFAULT_IOSCHED="cfq"
101
102#
103# System Type
104#
105# CONFIG_ARCH_AAEC2000 is not set
106# CONFIG_ARCH_INTEGRATOR is not set
107# CONFIG_ARCH_REALVIEW is not set
108# CONFIG_ARCH_VERSATILE is not set
109# CONFIG_ARCH_AT91 is not set
110# CONFIG_ARCH_CLPS7500 is not set
111# CONFIG_ARCH_CLPS711X is not set
112# CONFIG_ARCH_CO285 is not set
113# CONFIG_ARCH_EBSA110 is not set
114# CONFIG_ARCH_EP93XX is not set
115# CONFIG_ARCH_FOOTBRIDGE is not set
116# CONFIG_ARCH_NETX is not set
117# CONFIG_ARCH_H720X is not set
118# CONFIG_ARCH_IMX is not set
119# CONFIG_ARCH_IOP13XX is not set
120# CONFIG_ARCH_IOP32X is not set
121# CONFIG_ARCH_IOP33X is not set
122# CONFIG_ARCH_IXP23XX is not set
123# CONFIG_ARCH_IXP2000 is not set
124# CONFIG_ARCH_IXP4XX is not set
125# CONFIG_ARCH_L7200 is not set
126# CONFIG_ARCH_KS8695 is not set
127# CONFIG_ARCH_NS9XXX is not set
128# CONFIG_ARCH_MXC is not set
129# CONFIG_ARCH_PNX4008 is not set
130# CONFIG_ARCH_PXA is not set
131# CONFIG_ARCH_RPC is not set
132# CONFIG_ARCH_SA1100 is not set
133# CONFIG_ARCH_S3C2410 is not set
134# CONFIG_ARCH_SHARK is not set
135# CONFIG_ARCH_LH7A40X is not set
136# CONFIG_ARCH_DAVINCI is not set
137CONFIG_ARCH_OMAP=y
138
139#
140# TI OMAP Implementations
141#
142CONFIG_ARCH_OMAP_OTG=y
143CONFIG_ARCH_OMAP1=y
144# CONFIG_ARCH_OMAP2 is not set
145# CONFIG_ARCH_OMAP3 is not set
146
147#
148# OMAP Feature Selections
149#
150# CONFIG_OMAP_RESET_CLOCKS is not set
151# CONFIG_OMAP_BOOT_TAG is not set
152# CONFIG_OMAP_GPIO_SWITCH is not set
153CONFIG_OMAP_MUX=y
154# CONFIG_OMAP_MUX_DEBUG is not set
155CONFIG_OMAP_MUX_WARNINGS=y
156# CONFIG_OMAP_STI is not set
157CONFIG_OMAP_MCBSP=y
158# CONFIG_OMAP_MMU_FWK is not set
159# CONFIG_OMAP_MBOX_FWK is not set
160CONFIG_OMAP_MPU_TIMER=y
161# CONFIG_OMAP_32K_TIMER is not set
162# CONFIG_OMAP_DM_TIMER is not set
163CONFIG_OMAP_LL_DEBUG_UART1=y
164# CONFIG_OMAP_LL_DEBUG_UART2 is not set
165# CONFIG_OMAP_LL_DEBUG_UART3 is not set
166CONFIG_OMAP_SERIAL_WAKE=y
167# CONFIG_OMAP_DSP is not set
168
169#
170# OMAP Core Type
171#
172# CONFIG_ARCH_OMAP730 is not set
173# CONFIG_ARCH_OMAP15XX is not set
174CONFIG_ARCH_OMAP16XX=y
175
176#
177# OMAP Board Type
178#
179CONFIG_MACH_OMAP_INNOVATOR=y
180# CONFIG_MACH_OMAP_H2 is not set
181# CONFIG_MACH_OMAP_H3 is not set
182# CONFIG_MACH_OMAP_OSK is not set
183# CONFIG_MACH_NOKIA770 is not set
184# CONFIG_MACH_OMAP_GENERIC is not set
185
186#
187# OMAP CPU Speed
188#
189# CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER is not set
190# CONFIG_OMAP_ARM_216MHZ is not set
191CONFIG_OMAP_ARM_192MHZ=y
192# CONFIG_OMAP_ARM_168MHZ is not set
193# CONFIG_OMAP_ARM_120MHZ is not set
194# CONFIG_OMAP_ARM_60MHZ is not set
195# CONFIG_OMAP_ARM_30MHZ is not set
196# CONFIG_MACH_OMAP_APOLLON_PLUS is not set
197
198#
199# Boot options
200#
201
202#
203# Power management
204#
205
206#
207# Processor Type
208#
209CONFIG_CPU_32=y
210CONFIG_CPU_ARM926T=y
211CONFIG_CPU_32v5=y
212CONFIG_CPU_ABRT_EV5TJ=y
213CONFIG_CPU_PABRT_NOIFAR=y
214CONFIG_CPU_CACHE_VIVT=y
215CONFIG_CPU_COPY_V4WB=y
216CONFIG_CPU_TLB_V4WBI=y
217CONFIG_CPU_CP15=y
218CONFIG_CPU_CP15_MMU=y
219
220#
221# Processor Features
222#
223# CONFIG_ARM_THUMB is not set
224# CONFIG_CPU_ICACHE_DISABLE is not set
225# CONFIG_CPU_DCACHE_DISABLE is not set
226CONFIG_CPU_DCACHE_WRITETHROUGH=y
227# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
228# CONFIG_OUTER_CACHE is not set
229
230#
231# Bus support
232#
233# CONFIG_PCI_SYSCALL is not set
234# CONFIG_ARCH_SUPPORTS_MSI is not set
235
236#
237# PCCARD (PCMCIA/CardBus) support
238#
239# CONFIG_PCCARD is not set
240
241#
242# Kernel Features
243#
244# CONFIG_TICK_ONESHOT is not set
245# CONFIG_NO_HZ is not set
246# CONFIG_HIGH_RES_TIMERS is not set
247# CONFIG_PREEMPT is not set
248CONFIG_HZ=100
249# CONFIG_AEABI is not set
250# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
251CONFIG_SELECT_MEMORY_MODEL=y
252CONFIG_FLATMEM_MANUAL=y
253# CONFIG_DISCONTIGMEM_MANUAL is not set
254# CONFIG_SPARSEMEM_MANUAL is not set
255CONFIG_FLATMEM=y
256CONFIG_FLAT_NODE_MEM_MAP=y
257# CONFIG_SPARSEMEM_STATIC is not set
258CONFIG_SPLIT_PTLOCK_CPUS=4096
259# CONFIG_RESOURCES_64BIT is not set
260CONFIG_ZONE_DMA_FLAG=1
261CONFIG_BOUNCE=y
262CONFIG_VIRT_TO_BUS=y
263# CONFIG_LEDS is not set
264CONFIG_ALIGNMENT_TRAP=y
265
266#
267# Boot options
268#
269CONFIG_ZBOOT_ROM_TEXT=0x0
270CONFIG_ZBOOT_ROM_BSS=0x0
271CONFIG_CMDLINE="mem=32M console=tty0 console=ttyS0,115200 initrd=0x10200000,8M root=/dev/ram0 rw"
272# CONFIG_XIP_KERNEL is not set
273# CONFIG_KEXEC is not set
274
275#
276# CPU Frequency scaling
277#
278# CONFIG_CPU_FREQ is not set
279
280#
281# Floating point emulation
282#
283
284#
285# At least one emulation must be selected
286#
287CONFIG_FPE_NWFPE=y
288# CONFIG_FPE_NWFPE_XP is not set
289# CONFIG_FPE_FASTFPE is not set
290# CONFIG_VFP is not set
291
292#
293# Userspace binary formats
294#
295CONFIG_BINFMT_ELF=y
296# CONFIG_BINFMT_AOUT is not set
297# CONFIG_BINFMT_MISC is not set
298# CONFIG_ARTHUR is not set
299
300#
301# Power management options
302#
303# CONFIG_PM is not set
304CONFIG_SUSPEND_UP_POSSIBLE=y
305
306#
307# Networking
308#
309CONFIG_NET=y
310
311#
312# Networking options
313#
314CONFIG_PACKET=m
315# CONFIG_PACKET_MMAP is not set
316CONFIG_UNIX=y
317CONFIG_XFRM=y
318# CONFIG_XFRM_USER is not set
319# CONFIG_XFRM_SUB_POLICY is not set
320# CONFIG_XFRM_MIGRATE is not set
321# CONFIG_NET_KEY is not set
322CONFIG_INET=y
323CONFIG_IP_MULTICAST=y
324# CONFIG_IP_ADVANCED_ROUTER is not set
325CONFIG_IP_FIB_HASH=y
326CONFIG_IP_PNP=y
327CONFIG_IP_PNP_DHCP=y
328CONFIG_IP_PNP_BOOTP=y
329# CONFIG_IP_PNP_RARP is not set
330# CONFIG_NET_IPIP is not set
331# CONFIG_NET_IPGRE is not set
332# CONFIG_IP_MROUTE is not set
333# CONFIG_ARPD is not set
334# CONFIG_SYN_COOKIES is not set
335# CONFIG_INET_AH is not set
336# CONFIG_INET_ESP is not set
337# CONFIG_INET_IPCOMP is not set
338# CONFIG_INET_XFRM_TUNNEL is not set
339# CONFIG_INET_TUNNEL is not set
340CONFIG_INET_XFRM_MODE_TRANSPORT=y
341CONFIG_INET_XFRM_MODE_TUNNEL=y
342CONFIG_INET_XFRM_MODE_BEET=y
343CONFIG_INET_DIAG=y
344CONFIG_INET_TCP_DIAG=y
345# CONFIG_TCP_CONG_ADVANCED is not set
346CONFIG_TCP_CONG_CUBIC=y
347CONFIG_DEFAULT_TCP_CONG="cubic"
348# CONFIG_TCP_MD5SIG is not set
349# CONFIG_IPV6 is not set
350# CONFIG_INET6_XFRM_TUNNEL is not set
351# CONFIG_INET6_TUNNEL is not set
352# CONFIG_NETWORK_SECMARK is not set
353# CONFIG_NETFILTER is not set
354# CONFIG_IP_DCCP is not set
355# CONFIG_IP_SCTP is not set
356# CONFIG_TIPC is not set
357# CONFIG_ATM is not set
358# CONFIG_BRIDGE is not set
359# CONFIG_VLAN_8021Q is not set
360# CONFIG_DECNET is not set
361# CONFIG_LLC2 is not set
362# CONFIG_IPX is not set
363# CONFIG_ATALK is not set
364# CONFIG_X25 is not set
365# CONFIG_LAPB is not set
366# CONFIG_ECONET is not set
367# CONFIG_WAN_ROUTER is not set
368
369#
370# QoS and/or fair queueing
371#
372# CONFIG_NET_SCHED is not set
373
374#
375# Network testing
376#
377# CONFIG_NET_PKTGEN is not set
378# CONFIG_HAMRADIO is not set
379# CONFIG_IRDA is not set
380# CONFIG_BT is not set
381# CONFIG_AF_RXRPC is not set
382
383#
384# Wireless
385#
386# CONFIG_CFG80211 is not set
387# CONFIG_WIRELESS_EXT is not set
388# CONFIG_MAC80211 is not set
389# CONFIG_IEEE80211 is not set
390# CONFIG_RFKILL is not set
391# CONFIG_NET_9P is not set
392
393#
394# Device Drivers
395#
396
397#
398# Generic Driver Options
399#
400CONFIG_STANDALONE=y
401CONFIG_PREVENT_FIRMWARE_BUILD=y
402# CONFIG_FW_LOADER is not set
403# CONFIG_SYS_HYPERVISOR is not set
404# CONFIG_CONNECTOR is not set
405# CONFIG_MTD is not set
406# CONFIG_PARPORT is not set
407CONFIG_BLK_DEV=y
408# CONFIG_BLK_DEV_COW_COMMON is not set
409CONFIG_BLK_DEV_LOOP=y
410# CONFIG_BLK_DEV_CRYPTOLOOP is not set
411# CONFIG_BLK_DEV_NBD is not set
412CONFIG_BLK_DEV_RAM=y
413CONFIG_BLK_DEV_RAM_COUNT=16
414CONFIG_BLK_DEV_RAM_SIZE=8192
415CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
416# CONFIG_CDROM_PKTCDVD is not set
417# CONFIG_ATA_OVER_ETH is not set
418
419#
420# SCSI device support
421#
422# CONFIG_RAID_ATTRS is not set
423# CONFIG_SCSI is not set
424# CONFIG_SCSI_DMA is not set
425# CONFIG_SCSI_NETLINK is not set
426# CONFIG_ATA is not set
427# CONFIG_MD is not set
428CONFIG_NETDEVICES=y
429# CONFIG_NETDEVICES_MULTIQUEUE is not set
430# CONFIG_DUMMY is not set
431# CONFIG_BONDING is not set
432# CONFIG_MACVLAN is not set
433# CONFIG_EQUALIZER is not set
434# CONFIG_TUN is not set
435# CONFIG_PHYLIB is not set
436CONFIG_NET_ETHERNET=y
437CONFIG_MII=y
438# CONFIG_AX88796 is not set
439CONFIG_SMC91X=y
440# CONFIG_DM9000 is not set
441CONFIG_NETDEV_1000=y
442CONFIG_NETDEV_10000=y
443
444#
445# Wireless LAN
446#
447# CONFIG_WLAN_PRE80211 is not set
448# CONFIG_WLAN_80211 is not set
449# CONFIG_WAN is not set
450CONFIG_PPP=y
451CONFIG_PPP_MULTILINK=y
452# CONFIG_PPP_FILTER is not set
453# CONFIG_PPP_ASYNC is not set
454# CONFIG_PPP_SYNC_TTY is not set
455# CONFIG_PPP_DEFLATE is not set
456# CONFIG_PPP_BSDCOMP is not set
457# CONFIG_PPP_MPPE is not set
458# CONFIG_PPPOE is not set
459# CONFIG_PPPOL2TP is not set
460# CONFIG_SLIP is not set
461CONFIG_SLHC=y
462# CONFIG_SHAPER is not set
463# CONFIG_NETCONSOLE is not set
464# CONFIG_NETPOLL is not set
465# CONFIG_NET_POLL_CONTROLLER is not set
466# CONFIG_ISDN is not set
467
468#
469# Input device support
470#
471CONFIG_INPUT=y
472# CONFIG_INPUT_FF_MEMLESS is not set
473# CONFIG_INPUT_POLLDEV is not set
474
475#
476# Userland interfaces
477#
478CONFIG_INPUT_MOUSEDEV=y
479CONFIG_INPUT_MOUSEDEV_PSAUX=y
480CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
481CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
482# CONFIG_INPUT_JOYDEV is not set
483# CONFIG_INPUT_TSDEV is not set
484# CONFIG_INPUT_EVDEV is not set
485# CONFIG_INPUT_EVBUG is not set
486
487#
488# Input Device Drivers
489#
490CONFIG_INPUT_KEYBOARD=y
491# CONFIG_KEYBOARD_ATKBD is not set
492# CONFIG_KEYBOARD_SUNKBD is not set
493# CONFIG_KEYBOARD_LKKBD is not set
494# CONFIG_KEYBOARD_XTKBD is not set
495# CONFIG_KEYBOARD_NEWTON is not set
496# CONFIG_KEYBOARD_STOWAWAY is not set
497CONFIG_KEYBOARD_OMAP=y
498# CONFIG_KEYBOARD_GPIO is not set
499# CONFIG_INPUT_MOUSE is not set
500# CONFIG_INPUT_JOYSTICK is not set
501# CONFIG_INPUT_TABLET is not set
502# CONFIG_INPUT_TOUCHSCREEN is not set
503# CONFIG_INPUT_MISC is not set
504
505#
506# Hardware I/O ports
507#
508CONFIG_SERIO=y
509CONFIG_SERIO_SERPORT=y
510# CONFIG_SERIO_RAW is not set
511# CONFIG_GAMEPORT is not set
512
513#
514# Character devices
515#
516CONFIG_VT=y
517CONFIG_VT_CONSOLE=y
518CONFIG_HW_CONSOLE=y
519# CONFIG_VT_HW_CONSOLE_BINDING is not set
520# CONFIG_SERIAL_NONSTANDARD is not set
521
522#
523# Serial drivers
524#
525CONFIG_SERIAL_8250=y
526CONFIG_SERIAL_8250_CONSOLE=y
527CONFIG_SERIAL_8250_NR_UARTS=4
528CONFIG_SERIAL_8250_RUNTIME_UARTS=4
529# CONFIG_SERIAL_8250_EXTENDED is not set
530
531#
532# Non-8250 serial port support
533#
534CONFIG_SERIAL_CORE=y
535CONFIG_SERIAL_CORE_CONSOLE=y
536CONFIG_UNIX98_PTYS=y
537CONFIG_LEGACY_PTYS=y
538CONFIG_LEGACY_PTY_COUNT=256
539# CONFIG_IPMI_HANDLER is not set
540# CONFIG_WATCHDOG is not set
541CONFIG_HW_RANDOM=m
542CONFIG_HW_RANDOM_OMAP=m
543# CONFIG_NVRAM is not set
544# CONFIG_R3964 is not set
545# CONFIG_RAW_DRIVER is not set
546# CONFIG_TCG_TPM is not set
547# CONFIG_I2C is not set
548
549#
550# SPI support
551#
552# CONFIG_SPI is not set
553# CONFIG_SPI_MASTER is not set
554# CONFIG_W1 is not set
555CONFIG_HWMON=y
556# CONFIG_HWMON_VID is not set
557# CONFIG_SENSORS_ABITUGURU is not set
558# CONFIG_SENSORS_ABITUGURU3 is not set
559# CONFIG_SENSORS_F71805F is not set
560# CONFIG_SENSORS_IT87 is not set
561# CONFIG_SENSORS_PC87360 is not set
562# CONFIG_SENSORS_PC87427 is not set
563# CONFIG_SENSORS_SMSC47M1 is not set
564# CONFIG_SENSORS_SMSC47B397 is not set
565# CONFIG_SENSORS_VT1211 is not set
566# CONFIG_SENSORS_W83627HF is not set
567# CONFIG_SENSORS_W83627EHF is not set
568# CONFIG_HWMON_DEBUG_CHIP is not set
569CONFIG_MISC_DEVICES=y
570# CONFIG_EEPROM_93CX6 is not set
571
572#
573# Multifunction device drivers
574#
575# CONFIG_MFD_SM501 is not set
576# CONFIG_NEW_LEDS is not set
577
578#
579# Multimedia devices
580#
581# CONFIG_VIDEO_DEV is not set
582# CONFIG_DVB_CORE is not set
583CONFIG_DAB=y
584
585#
586# Graphics support
587#
588# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
589
590#
591# Display device support
592#
593# CONFIG_DISPLAY_SUPPORT is not set
594# CONFIG_VGASTATE is not set
595CONFIG_VIDEO_OUTPUT_CONTROL=m
596CONFIG_FB=y
597# CONFIG_FIRMWARE_EDID is not set
598# CONFIG_FB_DDC is not set
599# CONFIG_FB_CFB_FILLRECT is not set
600# CONFIG_FB_CFB_COPYAREA is not set
601# CONFIG_FB_CFB_IMAGEBLIT is not set
602# CONFIG_FB_SYS_FILLRECT is not set
603# CONFIG_FB_SYS_COPYAREA is not set
604# CONFIG_FB_SYS_IMAGEBLIT is not set
605# CONFIG_FB_SYS_FOPS is not set
606CONFIG_FB_DEFERRED_IO=y
607# CONFIG_FB_SVGALIB is not set
608# CONFIG_FB_MACMODES is not set
609# CONFIG_FB_BACKLIGHT is not set
610CONFIG_FB_MODE_HELPERS=y
611# CONFIG_FB_TILEBLITTING is not set
612
613#
614# Frame buffer hardware drivers
615#
616# CONFIG_FB_S1D13XXX is not set
617CONFIG_FB_OMAP=y
618# CONFIG_FB_OMAP_LCDC_EXTERNAL is not set
619# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set
620CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=2
621# CONFIG_FB_OMAP_DMA_TUNE is not set
622# CONFIG_FB_VIRTUAL is not set
623
624#
625# Console display driver support
626#
627# CONFIG_VGA_CONSOLE is not set
628CONFIG_DUMMY_CONSOLE=y
629CONFIG_FRAMEBUFFER_CONSOLE=y
630# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
631# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
632CONFIG_FONTS=y
633CONFIG_FONT_8x8=y
634CONFIG_FONT_8x16=y
635# CONFIG_FONT_6x11 is not set
636# CONFIG_FONT_7x14 is not set
637# CONFIG_FONT_PEARL_8x8 is not set
638# CONFIG_FONT_ACORN_8x8 is not set
639# CONFIG_FONT_MINI_4x6 is not set
640# CONFIG_FONT_SUN8x16 is not set
641# CONFIG_FONT_SUN12x22 is not set
642# CONFIG_FONT_10x18 is not set
643CONFIG_LOGO=y
644CONFIG_LOGO_LINUX_MONO=y
645CONFIG_LOGO_LINUX_VGA16=y
646CONFIG_LOGO_LINUX_CLUT224=y
647
648#
649# Sound
650#
651# CONFIG_SOUND is not set
652CONFIG_HID_SUPPORT=y
653CONFIG_HID=y
654CONFIG_HID_DEBUG=y
655CONFIG_USB_SUPPORT=y
656CONFIG_USB_ARCH_HAS_HCD=y
657CONFIG_USB_ARCH_HAS_OHCI=y
658# CONFIG_USB_ARCH_HAS_EHCI is not set
659# CONFIG_USB is not set
660
661#
662# Enable Host or Gadget support to see Inventra options
663#
664
665#
666# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
667#
668
669#
670# USB Gadget Support
671#
672# CONFIG_USB_GADGET is not set
673# CONFIG_MMC is not set
674CONFIG_RTC_LIB=y
675# CONFIG_RTC_CLASS is not set
676
677#
678# DMA Engine support
679#
680# CONFIG_DMA_ENGINE is not set
681
682#
683# DMA Clients
684#
685
686#
687# DMA Devices
688#
689
690#
691# CBUS support
692#
693# CONFIG_CBUS is not set
694
695#
696# File systems
697#
698CONFIG_EXT2_FS=y
699# CONFIG_EXT2_FS_XATTR is not set
700# CONFIG_EXT2_FS_XIP is not set
701# CONFIG_EXT3_FS is not set
702# CONFIG_EXT4DEV_FS is not set
703# CONFIG_REISERFS_FS is not set
704# CONFIG_JFS_FS is not set
705# CONFIG_FS_POSIX_ACL is not set
706# CONFIG_XFS_FS is not set
707# CONFIG_GFS2_FS is not set
708# CONFIG_OCFS2_FS is not set
709# CONFIG_MINIX_FS is not set
710# CONFIG_ROMFS_FS is not set
711CONFIG_INOTIFY=y
712CONFIG_INOTIFY_USER=y
713# CONFIG_QUOTA is not set
714CONFIG_DNOTIFY=y
715CONFIG_AUTOFS_FS=y
716CONFIG_AUTOFS4_FS=y
717# CONFIG_FUSE_FS is not set
718
719#
720# CD-ROM/DVD Filesystems
721#
722# CONFIG_ISO9660_FS is not set
723# CONFIG_UDF_FS is not set
724
725#
726# DOS/FAT/NT Filesystems
727#
728# CONFIG_MSDOS_FS is not set
729# CONFIG_VFAT_FS is not set
730# CONFIG_NTFS_FS is not set
731
732#
733# Pseudo filesystems
734#
735CONFIG_PROC_FS=y
736CONFIG_PROC_SYSCTL=y
737CONFIG_SYSFS=y
738# CONFIG_TMPFS is not set
739# CONFIG_HUGETLB_PAGE is not set
740CONFIG_RAMFS=y
741# CONFIG_CONFIGFS_FS is not set
742
743#
744# Miscellaneous filesystems
745#
746# CONFIG_ADFS_FS is not set
747# CONFIG_AFFS_FS is not set
748# CONFIG_HFS_FS is not set
749# CONFIG_HFSPLUS_FS is not set
750# CONFIG_BEFS_FS is not set
751# CONFIG_BFS_FS is not set
752# CONFIG_EFS_FS is not set
753# CONFIG_CRAMFS is not set
754# CONFIG_VXFS_FS is not set
755# CONFIG_HPFS_FS is not set
756# CONFIG_QNX4FS_FS is not set
757# CONFIG_SYSV_FS is not set
758# CONFIG_UFS_FS is not set
759
760#
761# Network File Systems
762#
763CONFIG_NFS_FS=y
764CONFIG_NFS_V3=y
765# CONFIG_NFS_V3_ACL is not set
766# CONFIG_NFS_V4 is not set
767# CONFIG_NFS_DIRECTIO is not set
768# CONFIG_NFSD is not set
769# CONFIG_ROOT_NFS is not set
770CONFIG_LOCKD=y
771CONFIG_LOCKD_V4=y
772CONFIG_NFS_COMMON=y
773CONFIG_SUNRPC=y
774# CONFIG_SUNRPC_BIND34 is not set
775# CONFIG_RPCSEC_GSS_KRB5 is not set
776# CONFIG_RPCSEC_GSS_SPKM3 is not set
777# CONFIG_SMB_FS is not set
778# CONFIG_CIFS is not set
779# CONFIG_NCP_FS is not set
780# CONFIG_CODA_FS is not set
781# CONFIG_AFS_FS is not set
782
783#
784# Partition Types
785#
786# CONFIG_PARTITION_ADVANCED is not set
787CONFIG_MSDOS_PARTITION=y
788
789#
790# Native Language Support
791#
792# CONFIG_NLS is not set
793
794#
795# Distributed Lock Manager
796#
797# CONFIG_DLM is not set
798
799#
800# Profiling support
801#
802# CONFIG_PROFILING is not set
803
804#
805# Kernel hacking
806#
807# CONFIG_PRINTK_TIME is not set
808CONFIG_ENABLE_MUST_CHECK=y
809# CONFIG_MAGIC_SYSRQ is not set
810# CONFIG_UNUSED_SYMBOLS is not set
811# CONFIG_DEBUG_FS is not set
812# CONFIG_HEADERS_CHECK is not set
813# CONFIG_DEBUG_KERNEL is not set
814# CONFIG_SLUB_DEBUG_ON is not set
815CONFIG_DEBUG_BUGVERBOSE=y
816CONFIG_FRAME_POINTER=y
817# CONFIG_DEBUG_USER is not set
818
819#
820# Security options
821#
822# CONFIG_KEYS is not set
823# CONFIG_SECURITY is not set
824# CONFIG_CRYPTO is not set
825
826#
827# Library routines
828#
829CONFIG_BITREVERSE=y
830# CONFIG_CRC_CCITT is not set
831# CONFIG_CRC16 is not set
832# CONFIG_CRC_ITU_T is not set
833CONFIG_CRC32=y
834# CONFIG_CRC7 is not set
835# CONFIG_LIBCRC32C is not set
836CONFIG_PLIST=y
837CONFIG_HAS_IOMEM=y
838CONFIG_HAS_IOPORT=y
839CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/omap_osk_5912_defconfig b/arch/arm/configs/omap_osk_5912_defconfig
index d4ca5e6e4ffa..b68e0144cab5 100644
--- a/arch/arm/configs/omap_osk_5912_defconfig
+++ b/arch/arm/configs/omap_osk_5912_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.25-rc3 3# Linux kernel version: 2.6.24-rc3-omap1
4# Mon Mar 3 03:35:17 2008 4# Fri Nov 23 12:24:12 2007
5# 5#
6CONFIG_ARM=y 6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y 7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
@@ -21,7 +21,6 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
21# CONFIG_ARCH_HAS_ILOG2_U64 is not set 21# CONFIG_ARCH_HAS_ILOG2_U64 is not set
22CONFIG_GENERIC_HWEIGHT=y 22CONFIG_GENERIC_HWEIGHT=y
23CONFIG_GENERIC_CALIBRATE_DELAY=y 23CONFIG_GENERIC_CALIBRATE_DELAY=y
24CONFIG_ARCH_SUPPORTS_AOUT=y
25CONFIG_ZONE_DMA=y 24CONFIG_ZONE_DMA=y
26CONFIG_VECTORS_BASE=0xffff0000 25CONFIG_VECTORS_BASE=0xffff0000
27CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 26CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
@@ -40,22 +39,17 @@ CONFIG_SYSVIPC_SYSCTL=y
40# CONFIG_POSIX_MQUEUE is not set 39# CONFIG_POSIX_MQUEUE is not set
41# CONFIG_BSD_PROCESS_ACCT is not set 40# CONFIG_BSD_PROCESS_ACCT is not set
42# CONFIG_TASKSTATS is not set 41# CONFIG_TASKSTATS is not set
42# CONFIG_USER_NS is not set
43# CONFIG_PID_NS is not set
43# CONFIG_AUDIT is not set 44# CONFIG_AUDIT is not set
44# CONFIG_IKCONFIG is not set 45# CONFIG_IKCONFIG is not set
45CONFIG_LOG_BUF_SHIFT=14 46CONFIG_LOG_BUF_SHIFT=14
46# CONFIG_CGROUPS is not set 47# CONFIG_CGROUPS is not set
47CONFIG_GROUP_SCHED=y
48CONFIG_FAIR_GROUP_SCHED=y 48CONFIG_FAIR_GROUP_SCHED=y
49# CONFIG_RT_GROUP_SCHED is not set 49CONFIG_FAIR_USER_SCHED=y
50CONFIG_USER_SCHED=y 50# CONFIG_FAIR_CGROUP_SCHED is not set
51# CONFIG_CGROUP_SCHED is not set 51CONFIG_SYSFS_DEPRECATED=y
52# CONFIG_SYSFS_DEPRECATED is not set
53# CONFIG_RELAY is not set 52# CONFIG_RELAY is not set
54CONFIG_NAMESPACES=y
55# CONFIG_UTS_NS is not set
56# CONFIG_IPC_NS is not set
57# CONFIG_USER_NS is not set
58# CONFIG_PID_NS is not set
59CONFIG_BLK_DEV_INITRD=y 53CONFIG_BLK_DEV_INITRD=y
60CONFIG_INITRAMFS_SOURCE="" 54CONFIG_INITRAMFS_SOURCE=""
61CONFIG_CC_OPTIMIZE_FOR_SIZE=y 55CONFIG_CC_OPTIMIZE_FOR_SIZE=y
@@ -69,26 +63,18 @@ CONFIG_HOTPLUG=y
69CONFIG_PRINTK=y 63CONFIG_PRINTK=y
70CONFIG_BUG=y 64CONFIG_BUG=y
71CONFIG_ELF_CORE=y 65CONFIG_ELF_CORE=y
72CONFIG_COMPAT_BRK=y
73CONFIG_BASE_FULL=y 66CONFIG_BASE_FULL=y
74CONFIG_FUTEX=y 67CONFIG_FUTEX=y
75CONFIG_ANON_INODES=y 68CONFIG_ANON_INODES=y
76CONFIG_EPOLL=y 69CONFIG_EPOLL=y
77CONFIG_SIGNALFD=y 70CONFIG_SIGNALFD=y
78CONFIG_TIMERFD=y
79CONFIG_EVENTFD=y 71CONFIG_EVENTFD=y
80CONFIG_SHMEM=y 72CONFIG_SHMEM=y
81CONFIG_VM_EVENT_COUNTERS=y 73CONFIG_VM_EVENT_COUNTERS=y
82CONFIG_SLAB=y 74CONFIG_SLUB_DEBUG=y
83# CONFIG_SLUB is not set 75# CONFIG_SLAB is not set
76CONFIG_SLUB=y
84# CONFIG_SLOB is not set 77# CONFIG_SLOB is not set
85# CONFIG_PROFILING is not set
86# CONFIG_MARKERS is not set
87CONFIG_HAVE_OPROFILE=y
88# CONFIG_KPROBES is not set
89CONFIG_HAVE_KPROBES=y
90CONFIG_PROC_PAGE_MONITOR=y
91CONFIG_SLABINFO=y
92CONFIG_RT_MUTEXES=y 78CONFIG_RT_MUTEXES=y
93# CONFIG_TINY_SHMEM is not set 79# CONFIG_TINY_SHMEM is not set
94CONFIG_BASE_SMALL=0 80CONFIG_BASE_SMALL=0
@@ -116,8 +102,6 @@ CONFIG_IOSCHED_CFQ=y
116CONFIG_DEFAULT_CFQ=y 102CONFIG_DEFAULT_CFQ=y
117# CONFIG_DEFAULT_NOOP is not set 103# CONFIG_DEFAULT_NOOP is not set
118CONFIG_DEFAULT_IOSCHED="cfq" 104CONFIG_DEFAULT_IOSCHED="cfq"
119CONFIG_CLASSIC_RCU=y
120# CONFIG_PREEMPT_RCU is not set
121 105
122# 106#
123# System Type 107# System Type
@@ -146,7 +130,6 @@ CONFIG_CLASSIC_RCU=y
146# CONFIG_ARCH_KS8695 is not set 130# CONFIG_ARCH_KS8695 is not set
147# CONFIG_ARCH_NS9XXX is not set 131# CONFIG_ARCH_NS9XXX is not set
148# CONFIG_ARCH_MXC is not set 132# CONFIG_ARCH_MXC is not set
149# CONFIG_ARCH_ORION is not set
150# CONFIG_ARCH_PNX4008 is not set 133# CONFIG_ARCH_PNX4008 is not set
151# CONFIG_ARCH_PXA is not set 134# CONFIG_ARCH_PXA is not set
152# CONFIG_ARCH_RPC is not set 135# CONFIG_ARCH_RPC is not set
@@ -156,7 +139,6 @@ CONFIG_CLASSIC_RCU=y
156# CONFIG_ARCH_LH7A40X is not set 139# CONFIG_ARCH_LH7A40X is not set
157# CONFIG_ARCH_DAVINCI is not set 140# CONFIG_ARCH_DAVINCI is not set
158CONFIG_ARCH_OMAP=y 141CONFIG_ARCH_OMAP=y
159# CONFIG_ARCH_MSM7X00A is not set
160 142
161# 143#
162# TI OMAP Implementations 144# TI OMAP Implementations
@@ -164,16 +146,22 @@ CONFIG_ARCH_OMAP=y
164CONFIG_ARCH_OMAP_OTG=y 146CONFIG_ARCH_OMAP_OTG=y
165CONFIG_ARCH_OMAP1=y 147CONFIG_ARCH_OMAP1=y
166# CONFIG_ARCH_OMAP2 is not set 148# CONFIG_ARCH_OMAP2 is not set
149# CONFIG_ARCH_OMAP3 is not set
167 150
168# 151#
169# OMAP Feature Selections 152# OMAP Feature Selections
170# 153#
154CONFIG_OMAP_DEBUG_SRAM_PATCH=y
171CONFIG_OMAP_RESET_CLOCKS=y 155CONFIG_OMAP_RESET_CLOCKS=y
156# CONFIG_OMAP_BOOT_TAG is not set
157# CONFIG_OMAP_GPIO_SWITCH is not set
172CONFIG_OMAP_MUX=y 158CONFIG_OMAP_MUX=y
173# CONFIG_OMAP_MUX_DEBUG is not set 159# CONFIG_OMAP_MUX_DEBUG is not set
174CONFIG_OMAP_MUX_WARNINGS=y 160CONFIG_OMAP_MUX_WARNINGS=y
161# CONFIG_OMAP_STI is not set
175CONFIG_OMAP_MCBSP=y 162CONFIG_OMAP_MCBSP=y
176# CONFIG_OMAP_MMU_FWK is not set 163# CONFIG_OMAP_MMU_FWK is not set
164# CONFIG_OMAP_MBOX_FWK is not set
177# CONFIG_OMAP_MPU_TIMER is not set 165# CONFIG_OMAP_MPU_TIMER is not set
178CONFIG_OMAP_32K_TIMER=y 166CONFIG_OMAP_32K_TIMER=y
179CONFIG_OMAP_32K_TIMER_HZ=128 167CONFIG_OMAP_32K_TIMER_HZ=128
@@ -182,6 +170,7 @@ CONFIG_OMAP_LL_DEBUG_UART1=y
182# CONFIG_OMAP_LL_DEBUG_UART2 is not set 170# CONFIG_OMAP_LL_DEBUG_UART2 is not set
183# CONFIG_OMAP_LL_DEBUG_UART3 is not set 171# CONFIG_OMAP_LL_DEBUG_UART3 is not set
184CONFIG_OMAP_SERIAL_WAKE=y 172CONFIG_OMAP_SERIAL_WAKE=y
173# CONFIG_OMAP_DSP is not set
185 174
186# 175#
187# OMAP Core Type 176# OMAP Core Type
@@ -193,13 +182,13 @@ CONFIG_ARCH_OMAP16XX=y
193# 182#
194# OMAP Board Type 183# OMAP Board Type
195# 184#
196CONFIG_MACH_OMAP_INNOVATOR=y 185# CONFIG_MACH_OMAP_INNOVATOR is not set
197CONFIG_MACH_OMAP_H2=y 186# CONFIG_MACH_OMAP_H2 is not set
198CONFIG_MACH_OMAP_H3=y 187# CONFIG_MACH_OMAP_H3 is not set
199CONFIG_MACH_OMAP_OSK=y 188CONFIG_MACH_OMAP_OSK=y
200# CONFIG_OMAP_OSK_MISTRAL is not set 189# CONFIG_OMAP_OSK_MISTRAL is not set
201CONFIG_MACH_NOKIA770=y 190# CONFIG_MACH_NOKIA770 is not set
202CONFIG_MACH_OMAP_GENERIC=y 191# CONFIG_MACH_OMAP_GENERIC is not set
203 192
204# 193#
205# OMAP CPU Speed 194# OMAP CPU Speed
@@ -227,6 +216,7 @@ CONFIG_CPU_32=y
227CONFIG_CPU_ARM926T=y 216CONFIG_CPU_ARM926T=y
228CONFIG_CPU_32v5=y 217CONFIG_CPU_32v5=y
229CONFIG_CPU_ABRT_EV5TJ=y 218CONFIG_CPU_ABRT_EV5TJ=y
219CONFIG_CPU_PABRT_NOIFAR=y
230CONFIG_CPU_CACHE_VIVT=y 220CONFIG_CPU_CACHE_VIVT=y
231CONFIG_CPU_COPY_V4WB=y 221CONFIG_CPU_COPY_V4WB=y
232CONFIG_CPU_TLB_V4WBI=y 222CONFIG_CPU_TLB_V4WBI=y
@@ -264,12 +254,11 @@ CONFIG_OMAP_CF=y
264# 254#
265CONFIG_TICK_ONESHOT=y 255CONFIG_TICK_ONESHOT=y
266CONFIG_NO_HZ=y 256CONFIG_NO_HZ=y
267CONFIG_HIGH_RES_TIMERS=y 257# CONFIG_HIGH_RES_TIMERS is not set
268CONFIG_GENERIC_CLOCKEVENTS_BUILD=y 258CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
269# CONFIG_PREEMPT is not set 259# CONFIG_PREEMPT is not set
270CONFIG_HZ=128 260CONFIG_HZ=128
271CONFIG_AEABI=y 261# CONFIG_AEABI is not set
272CONFIG_OABI_COMPAT=y
273# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set 262# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
274CONFIG_SELECT_MEMORY_MODEL=y 263CONFIG_SELECT_MEMORY_MODEL=y
275CONFIG_FLATMEM_MANUAL=y 264CONFIG_FLATMEM_MANUAL=y
@@ -295,7 +284,6 @@ CONFIG_ZBOOT_ROM_BSS=0x0
295CONFIG_CMDLINE="mem=32M console=ttyS0,115200 initrd=0x10400000,8M root=/dev/ram0 rw" 284CONFIG_CMDLINE="mem=32M console=ttyS0,115200 initrd=0x10400000,8M root=/dev/ram0 rw"
296# CONFIG_XIP_KERNEL is not set 285# CONFIG_XIP_KERNEL is not set
297# CONFIG_KEXEC is not set 286# CONFIG_KEXEC is not set
298# CONFIG_ATAGS_PROC is not set
299 287
300# 288#
301# CPU Frequency scaling 289# CPU Frequency scaling
@@ -320,6 +308,7 @@ CONFIG_FPE_NWFPE=y
320CONFIG_BINFMT_ELF=y 308CONFIG_BINFMT_ELF=y
321# CONFIG_BINFMT_AOUT is not set 309# CONFIG_BINFMT_AOUT is not set
322# CONFIG_BINFMT_MISC is not set 310# CONFIG_BINFMT_MISC is not set
311# CONFIG_ARTHUR is not set
323 312
324# 313#
325# Power management options 314# Power management options
@@ -328,10 +317,9 @@ CONFIG_PM=y
328# CONFIG_PM_LEGACY is not set 317# CONFIG_PM_LEGACY is not set
329# CONFIG_PM_DEBUG is not set 318# CONFIG_PM_DEBUG is not set
330CONFIG_PM_SLEEP=y 319CONFIG_PM_SLEEP=y
320CONFIG_SUSPEND_UP_POSSIBLE=y
331CONFIG_SUSPEND=y 321CONFIG_SUSPEND=y
332CONFIG_SUSPEND_FREEZER=y
333# CONFIG_APM_EMULATION is not set 322# CONFIG_APM_EMULATION is not set
334CONFIG_ARCH_SUSPEND_POSSIBLE=y
335 323
336# 324#
337# Networking 325# Networking
@@ -348,7 +336,6 @@ CONFIG_XFRM=y
348# CONFIG_XFRM_USER is not set 336# CONFIG_XFRM_USER is not set
349# CONFIG_XFRM_SUB_POLICY is not set 337# CONFIG_XFRM_SUB_POLICY is not set
350# CONFIG_XFRM_MIGRATE is not set 338# CONFIG_XFRM_MIGRATE is not set
351# CONFIG_XFRM_STATISTICS is not set
352# CONFIG_NET_KEY is not set 339# CONFIG_NET_KEY is not set
353CONFIG_INET=y 340CONFIG_INET=y
354CONFIG_IP_MULTICAST=y 341CONFIG_IP_MULTICAST=y
@@ -404,7 +391,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
404# 391#
405# CONFIG_NET_PKTGEN is not set 392# CONFIG_NET_PKTGEN is not set
406# CONFIG_HAMRADIO is not set 393# CONFIG_HAMRADIO is not set
407# CONFIG_CAN is not set
408# CONFIG_IRDA is not set 394# CONFIG_IRDA is not set
409# CONFIG_BT is not set 395# CONFIG_BT is not set
410# CONFIG_AF_RXRPC is not set 396# CONFIG_AF_RXRPC is not set
@@ -517,13 +503,11 @@ CONFIG_BLK_DEV_LOOP=y
517CONFIG_BLK_DEV_RAM=y 503CONFIG_BLK_DEV_RAM=y
518CONFIG_BLK_DEV_RAM_COUNT=16 504CONFIG_BLK_DEV_RAM_COUNT=16
519CONFIG_BLK_DEV_RAM_SIZE=8192 505CONFIG_BLK_DEV_RAM_SIZE=8192
520# CONFIG_BLK_DEV_XIP is not set 506CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
521# CONFIG_CDROM_PKTCDVD is not set 507# CONFIG_CDROM_PKTCDVD is not set
522# CONFIG_ATA_OVER_ETH is not set 508# CONFIG_ATA_OVER_ETH is not set
523CONFIG_MISC_DEVICES=y 509CONFIG_MISC_DEVICES=y
524# CONFIG_EEPROM_93CX6 is not set 510# CONFIG_EEPROM_93CX6 is not set
525# CONFIG_ENCLOSURE_SERVICES is not set
526CONFIG_HAVE_IDE=y
527CONFIG_IDE=m 511CONFIG_IDE=m
528CONFIG_BLK_DEV_IDE=m 512CONFIG_BLK_DEV_IDE=m
529 513
@@ -545,6 +529,7 @@ CONFIG_IDE_PROC_FS=y
545# 529#
546# CONFIG_IDE_GENERIC is not set 530# CONFIG_IDE_GENERIC is not set
547# CONFIG_BLK_DEV_PLATFORM is not set 531# CONFIG_BLK_DEV_PLATFORM is not set
532# CONFIG_IDE_ARM is not set
548# CONFIG_BLK_DEV_IDEDMA is not set 533# CONFIG_BLK_DEV_IDEDMA is not set
549CONFIG_IDE_ARCH_OBSOLETE_INIT=y 534CONFIG_IDE_ARCH_OBSOLETE_INIT=y
550# CONFIG_BLK_DEV_HD is not set 535# CONFIG_BLK_DEV_HD is not set
@@ -578,7 +563,6 @@ CONFIG_SMC91X=y
578# CONFIG_IBM_NEW_EMAC_EMAC4 is not set 563# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
579# CONFIG_B44 is not set 564# CONFIG_B44 is not set
580CONFIG_NETDEV_1000=y 565CONFIG_NETDEV_1000=y
581# CONFIG_E1000E_ENABLED is not set
582CONFIG_NETDEV_10000=y 566CONFIG_NETDEV_10000=y
583 567
584# 568#
@@ -600,6 +584,7 @@ CONFIG_PPP_MULTILINK=y
600# CONFIG_PPPOL2TP is not set 584# CONFIG_PPPOL2TP is not set
601# CONFIG_SLIP is not set 585# CONFIG_SLIP is not set
602CONFIG_SLHC=y 586CONFIG_SLHC=y
587# CONFIG_SHAPER is not set
603# CONFIG_NETCONSOLE is not set 588# CONFIG_NETCONSOLE is not set
604# CONFIG_NETPOLL is not set 589# CONFIG_NETPOLL is not set
605# CONFIG_NET_POLL_CONTROLLER is not set 590# CONFIG_NET_POLL_CONTROLLER is not set
@@ -696,7 +681,6 @@ CONFIG_HW_RANDOM_OMAP=m
696# CONFIG_SYNCLINK_CS is not set 681# CONFIG_SYNCLINK_CS is not set
697# CONFIG_CARDMAN_4000 is not set 682# CONFIG_CARDMAN_4000 is not set
698# CONFIG_CARDMAN_4040 is not set 683# CONFIG_CARDMAN_4040 is not set
699# CONFIG_IPWIRELESS is not set
700# CONFIG_RAW_DRIVER is not set 684# CONFIG_RAW_DRIVER is not set
701# CONFIG_TCG_TPM is not set 685# CONFIG_TCG_TPM is not set
702CONFIG_I2C=y 686CONFIG_I2C=y
@@ -724,13 +708,17 @@ CONFIG_I2C_OMAP=y
724# 708#
725# Miscellaneous I2C Chip support 709# Miscellaneous I2C Chip support
726# 710#
711# CONFIG_SENSORS_DS1337 is not set
712# CONFIG_SENSORS_DS1374 is not set
727# CONFIG_DS1682 is not set 713# CONFIG_DS1682 is not set
728# CONFIG_SENSORS_EEPROM is not set 714# CONFIG_SENSORS_EEPROM is not set
729# CONFIG_SENSORS_PCF8574 is not set 715# CONFIG_SENSORS_PCF8574 is not set
730# CONFIG_PCF8575 is not set 716# CONFIG_SENSORS_PCA9539 is not set
731# CONFIG_SENSORS_PCF8591 is not set 717# CONFIG_SENSORS_PCF8591 is not set
732# CONFIG_ISP1301_OMAP is not set 718# CONFIG_ISP1301_OMAP is not set
733CONFIG_TPS65010=y 719CONFIG_TPS65010=y
720# CONFIG_SENSORS_TLV320AIC23 is not set
721# CONFIG_GPIOEXPANDER_OMAP is not set
734# CONFIG_SENSORS_MAX6875 is not set 722# CONFIG_SENSORS_MAX6875 is not set
735# CONFIG_SENSORS_TSL2550 is not set 723# CONFIG_SENSORS_TSL2550 is not set
736# CONFIG_I2C_DEBUG_CORE is not set 724# CONFIG_I2C_DEBUG_CORE is not set
@@ -755,7 +743,6 @@ CONFIG_HWMON=y
755# CONFIG_SENSORS_ADM1031 is not set 743# CONFIG_SENSORS_ADM1031 is not set
756# CONFIG_SENSORS_ADM9240 is not set 744# CONFIG_SENSORS_ADM9240 is not set
757# CONFIG_SENSORS_ADT7470 is not set 745# CONFIG_SENSORS_ADT7470 is not set
758# CONFIG_SENSORS_ADT7473 is not set
759# CONFIG_SENSORS_ATXP1 is not set 746# CONFIG_SENSORS_ATXP1 is not set
760# CONFIG_SENSORS_DS1621 is not set 747# CONFIG_SENSORS_DS1621 is not set
761# CONFIG_SENSORS_F71805F is not set 748# CONFIG_SENSORS_F71805F is not set
@@ -783,7 +770,6 @@ CONFIG_HWMON=y
783# CONFIG_SENSORS_SMSC47M1 is not set 770# CONFIG_SENSORS_SMSC47M1 is not set
784# CONFIG_SENSORS_SMSC47M192 is not set 771# CONFIG_SENSORS_SMSC47M192 is not set
785# CONFIG_SENSORS_SMSC47B397 is not set 772# CONFIG_SENSORS_SMSC47B397 is not set
786# CONFIG_SENSORS_ADS7828 is not set
787# CONFIG_SENSORS_THMC50 is not set 773# CONFIG_SENSORS_THMC50 is not set
788# CONFIG_SENSORS_VT1211 is not set 774# CONFIG_SENSORS_VT1211 is not set
789# CONFIG_SENSORS_W83781D is not set 775# CONFIG_SENSORS_W83781D is not set
@@ -791,7 +777,6 @@ CONFIG_HWMON=y
791# CONFIG_SENSORS_W83792D is not set 777# CONFIG_SENSORS_W83792D is not set
792# CONFIG_SENSORS_W83793 is not set 778# CONFIG_SENSORS_W83793 is not set
793# CONFIG_SENSORS_W83L785TS is not set 779# CONFIG_SENSORS_W83L785TS is not set
794# CONFIG_SENSORS_W83L786NG is not set
795# CONFIG_SENSORS_W83627HF is not set 780# CONFIG_SENSORS_W83627HF is not set
796# CONFIG_SENSORS_W83627EHF is not set 781# CONFIG_SENSORS_W83627EHF is not set
797# CONFIG_HWMON_DEBUG_CHIP is not set 782# CONFIG_HWMON_DEBUG_CHIP is not set
@@ -807,7 +792,6 @@ CONFIG_SSB_POSSIBLE=y
807# Multifunction device drivers 792# Multifunction device drivers
808# 793#
809# CONFIG_MFD_SM501 is not set 794# CONFIG_MFD_SM501 is not set
810# CONFIG_MFD_ASIC3 is not set
811 795
812# 796#
813# Multimedia devices 797# Multimedia devices
@@ -822,11 +806,11 @@ CONFIG_DAB=y
822# CONFIG_VGASTATE is not set 806# CONFIG_VGASTATE is not set
823CONFIG_VIDEO_OUTPUT_CONTROL=m 807CONFIG_VIDEO_OUTPUT_CONTROL=m
824CONFIG_FB=y 808CONFIG_FB=y
825CONFIG_FIRMWARE_EDID=y 809# CONFIG_FIRMWARE_EDID is not set
826# CONFIG_FB_DDC is not set 810# CONFIG_FB_DDC is not set
827# CONFIG_FB_CFB_FILLRECT is not set 811CONFIG_FB_CFB_FILLRECT=y
828# CONFIG_FB_CFB_COPYAREA is not set 812CONFIG_FB_CFB_COPYAREA=y
829# CONFIG_FB_CFB_IMAGEBLIT is not set 813CONFIG_FB_CFB_IMAGEBLIT=y
830# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set 814# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
831# CONFIG_FB_SYS_FILLRECT is not set 815# CONFIG_FB_SYS_FILLRECT is not set
832# CONFIG_FB_SYS_COPYAREA is not set 816# CONFIG_FB_SYS_COPYAREA is not set
@@ -844,7 +828,11 @@ CONFIG_FB_MODE_HELPERS=y
844# 828#
845# CONFIG_FB_S1D13XXX is not set 829# CONFIG_FB_S1D13XXX is not set
846# CONFIG_FB_VIRTUAL is not set 830# CONFIG_FB_VIRTUAL is not set
847# CONFIG_FB_OMAP is not set 831CONFIG_FB_OMAP=y
832# CONFIG_FB_OMAP_LCDC_EXTERNAL is not set
833# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set
834CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=2
835# CONFIG_FB_OMAP_DMA_TUNE is not set
848# CONFIG_BACKLIGHT_LCD_SUPPORT is not set 836# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
849 837
850# 838#
@@ -891,8 +879,16 @@ CONFIG_USB_ARCH_HAS_OHCI=y
891# CONFIG_USB is not set 879# CONFIG_USB is not set
892 880
893# 881#
882# Enable Host or Gadget support to see Inventra options
883#
884
885#
894# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 886# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
895# 887#
888
889#
890# USB Gadget Support
891#
896# CONFIG_USB_GADGET is not set 892# CONFIG_USB_GADGET is not set
897# CONFIG_MMC is not set 893# CONFIG_MMC is not set
898# CONFIG_NEW_LEDS is not set 894# CONFIG_NEW_LEDS is not set
@@ -900,6 +896,11 @@ CONFIG_RTC_LIB=y
900# CONFIG_RTC_CLASS is not set 896# CONFIG_RTC_CLASS is not set
901 897
902# 898#
899# CBUS support
900#
901# CONFIG_CBUS is not set
902
903#
903# File systems 904# File systems
904# 905#
905CONFIG_EXT2_FS=y 906CONFIG_EXT2_FS=y
@@ -913,10 +914,12 @@ CONFIG_EXT2_FS=y
913# CONFIG_XFS_FS is not set 914# CONFIG_XFS_FS is not set
914# CONFIG_GFS2_FS is not set 915# CONFIG_GFS2_FS is not set
915# CONFIG_OCFS2_FS is not set 916# CONFIG_OCFS2_FS is not set
916CONFIG_DNOTIFY=y 917# CONFIG_MINIX_FS is not set
918# CONFIG_ROMFS_FS is not set
917CONFIG_INOTIFY=y 919CONFIG_INOTIFY=y
918CONFIG_INOTIFY_USER=y 920CONFIG_INOTIFY_USER=y
919# CONFIG_QUOTA is not set 921# CONFIG_QUOTA is not set
922CONFIG_DNOTIFY=y
920CONFIG_AUTOFS_FS=y 923CONFIG_AUTOFS_FS=y
921CONFIG_AUTOFS4_FS=y 924CONFIG_AUTOFS4_FS=y
922# CONFIG_FUSE_FS is not set 925# CONFIG_FUSE_FS is not set
@@ -970,10 +973,8 @@ CONFIG_JFFS2_RTIME=y
970# CONFIG_JFFS2_RUBIN is not set 973# CONFIG_JFFS2_RUBIN is not set
971# CONFIG_CRAMFS is not set 974# CONFIG_CRAMFS is not set
972# CONFIG_VXFS_FS is not set 975# CONFIG_VXFS_FS is not set
973# CONFIG_MINIX_FS is not set
974# CONFIG_HPFS_FS is not set 976# CONFIG_HPFS_FS is not set
975# CONFIG_QNX4FS_FS is not set 977# CONFIG_QNX4FS_FS is not set
976# CONFIG_ROMFS_FS is not set
977# CONFIG_SYSV_FS is not set 978# CONFIG_SYSV_FS is not set
978# CONFIG_UFS_FS is not set 979# CONFIG_UFS_FS is not set
979CONFIG_NETWORK_FILESYSTEMS=y 980CONFIG_NETWORK_FILESYSTEMS=y
@@ -1043,6 +1044,9 @@ CONFIG_NLS_ISO8859_1=m
1043# CONFIG_NLS_KOI8_U is not set 1044# CONFIG_NLS_KOI8_U is not set
1044# CONFIG_NLS_UTF8 is not set 1045# CONFIG_NLS_UTF8 is not set
1045# CONFIG_DLM is not set 1046# CONFIG_DLM is not set
1047CONFIG_INSTRUMENTATION=y
1048# CONFIG_PROFILING is not set
1049# CONFIG_MARKERS is not set
1046 1050
1047# 1051#
1048# Kernel hacking 1052# Kernel hacking
@@ -1055,6 +1059,7 @@ CONFIG_ENABLE_MUST_CHECK=y
1055# CONFIG_DEBUG_FS is not set 1059# CONFIG_DEBUG_FS is not set
1056# CONFIG_HEADERS_CHECK is not set 1060# CONFIG_HEADERS_CHECK is not set
1057# CONFIG_DEBUG_KERNEL is not set 1061# CONFIG_DEBUG_KERNEL is not set
1062# CONFIG_SLUB_DEBUG_ON is not set
1058CONFIG_DEBUG_BUGVERBOSE=y 1063CONFIG_DEBUG_BUGVERBOSE=y
1059CONFIG_FRAME_POINTER=y 1064CONFIG_FRAME_POINTER=y
1060# CONFIG_SAMPLES is not set 1065# CONFIG_SAMPLES is not set
@@ -1066,51 +1071,7 @@ CONFIG_FRAME_POINTER=y
1066# CONFIG_KEYS is not set 1071# CONFIG_KEYS is not set
1067# CONFIG_SECURITY is not set 1072# CONFIG_SECURITY is not set
1068# CONFIG_SECURITY_FILE_CAPABILITIES is not set 1073# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1069CONFIG_CRYPTO=y 1074# CONFIG_CRYPTO is not set
1070# CONFIG_CRYPTO_SEQIV is not set
1071# CONFIG_CRYPTO_MANAGER is not set
1072# CONFIG_CRYPTO_HMAC is not set
1073# CONFIG_CRYPTO_XCBC is not set
1074# CONFIG_CRYPTO_NULL is not set
1075# CONFIG_CRYPTO_MD4 is not set
1076# CONFIG_CRYPTO_MD5 is not set
1077# CONFIG_CRYPTO_SHA1 is not set
1078# CONFIG_CRYPTO_SHA256 is not set
1079# CONFIG_CRYPTO_SHA512 is not set
1080# CONFIG_CRYPTO_WP512 is not set
1081# CONFIG_CRYPTO_TGR192 is not set
1082# CONFIG_CRYPTO_GF128MUL is not set
1083# CONFIG_CRYPTO_ECB is not set
1084# CONFIG_CRYPTO_CBC is not set
1085# CONFIG_CRYPTO_PCBC is not set
1086# CONFIG_CRYPTO_LRW is not set
1087# CONFIG_CRYPTO_XTS is not set
1088# CONFIG_CRYPTO_CTR is not set
1089# CONFIG_CRYPTO_GCM is not set
1090# CONFIG_CRYPTO_CCM is not set
1091# CONFIG_CRYPTO_CRYPTD is not set
1092# CONFIG_CRYPTO_DES is not set
1093# CONFIG_CRYPTO_FCRYPT is not set
1094# CONFIG_CRYPTO_BLOWFISH is not set
1095# CONFIG_CRYPTO_TWOFISH is not set
1096# CONFIG_CRYPTO_SERPENT is not set
1097# CONFIG_CRYPTO_AES is not set
1098# CONFIG_CRYPTO_CAST5 is not set
1099# CONFIG_CRYPTO_CAST6 is not set
1100# CONFIG_CRYPTO_TEA is not set
1101# CONFIG_CRYPTO_ARC4 is not set
1102# CONFIG_CRYPTO_KHAZAD is not set
1103# CONFIG_CRYPTO_ANUBIS is not set
1104# CONFIG_CRYPTO_SEED is not set
1105# CONFIG_CRYPTO_SALSA20 is not set
1106# CONFIG_CRYPTO_DEFLATE is not set
1107# CONFIG_CRYPTO_MICHAEL_MIC is not set
1108# CONFIG_CRYPTO_CRC32C is not set
1109# CONFIG_CRYPTO_CAMELLIA is not set
1110# CONFIG_CRYPTO_TEST is not set
1111# CONFIG_CRYPTO_AUTHENC is not set
1112# CONFIG_CRYPTO_LZO is not set
1113CONFIG_CRYPTO_HW=y
1114 1075
1115# 1076#
1116# Library routines 1077# Library routines
diff --git a/arch/arm/configs/omap_perseus2_730_defconfig b/arch/arm/configs/omap_perseus2_730_defconfig
new file mode 100644
index 000000000000..b94800c0e000
--- /dev/null
+++ b/arch/arm/configs/omap_perseus2_730_defconfig
@@ -0,0 +1,928 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.23-rc6-omap1
4# Tue Sep 18 11:45:12 2007
5#
6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8CONFIG_GENERIC_GPIO=y
9CONFIG_GENERIC_TIME=y
10CONFIG_GENERIC_CLOCKEVENTS=y
11CONFIG_MMU=y
12# CONFIG_NO_IOPORT is not set
13CONFIG_GENERIC_HARDIRQS=y
14CONFIG_STACKTRACE_SUPPORT=y
15CONFIG_LOCKDEP_SUPPORT=y
16CONFIG_TRACE_IRQFLAGS_SUPPORT=y
17CONFIG_HARDIRQS_SW_RESEND=y
18CONFIG_GENERIC_IRQ_PROBE=y
19CONFIG_RWSEM_GENERIC_SPINLOCK=y
20# CONFIG_ARCH_HAS_ILOG2_U32 is not set
21# CONFIG_ARCH_HAS_ILOG2_U64 is not set
22CONFIG_GENERIC_HWEIGHT=y
23CONFIG_GENERIC_CALIBRATE_DELAY=y
24CONFIG_ZONE_DMA=y
25CONFIG_VECTORS_BASE=0xffff0000
26CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
27
28#
29# General setup
30#
31CONFIG_EXPERIMENTAL=y
32CONFIG_BROKEN_ON_SMP=y
33CONFIG_LOCK_KERNEL=y
34CONFIG_INIT_ENV_ARG_LIMIT=32
35CONFIG_LOCALVERSION=""
36CONFIG_LOCALVERSION_AUTO=y
37CONFIG_SWAP=y
38CONFIG_SYSVIPC=y
39CONFIG_SYSVIPC_SYSCTL=y
40# CONFIG_POSIX_MQUEUE is not set
41# CONFIG_BSD_PROCESS_ACCT is not set
42# CONFIG_TASKSTATS is not set
43# CONFIG_USER_NS is not set
44# CONFIG_AUDIT is not set
45# CONFIG_IKCONFIG is not set
46CONFIG_LOG_BUF_SHIFT=14
47CONFIG_SYSFS_DEPRECATED=y
48# CONFIG_RELAY is not set
49CONFIG_BLK_DEV_INITRD=y
50CONFIG_INITRAMFS_SOURCE=""
51CONFIG_CC_OPTIMIZE_FOR_SIZE=y
52CONFIG_SYSCTL=y
53# CONFIG_EMBEDDED is not set
54CONFIG_UID16=y
55CONFIG_SYSCTL_SYSCALL=y
56CONFIG_KALLSYMS=y
57# CONFIG_KALLSYMS_EXTRA_PASS is not set
58CONFIG_HOTPLUG=y
59CONFIG_PRINTK=y
60CONFIG_BUG=y
61CONFIG_ELF_CORE=y
62CONFIG_BASE_FULL=y
63CONFIG_FUTEX=y
64CONFIG_ANON_INODES=y
65CONFIG_EPOLL=y
66CONFIG_SIGNALFD=y
67CONFIG_TIMERFD=y
68CONFIG_EVENTFD=y
69CONFIG_SHMEM=y
70CONFIG_VM_EVENT_COUNTERS=y
71CONFIG_SLAB=y
72# CONFIG_SLUB is not set
73# CONFIG_SLOB is not set
74CONFIG_RT_MUTEXES=y
75# CONFIG_TINY_SHMEM is not set
76CONFIG_BASE_SMALL=0
77CONFIG_MODULES=y
78CONFIG_MODULE_UNLOAD=y
79# CONFIG_MODULE_FORCE_UNLOAD is not set
80# CONFIG_MODVERSIONS is not set
81# CONFIG_MODULE_SRCVERSION_ALL is not set
82CONFIG_KMOD=y
83CONFIG_BLOCK=y
84# CONFIG_LBD is not set
85# CONFIG_BLK_DEV_IO_TRACE is not set
86# CONFIG_LSF is not set
87# CONFIG_BLK_DEV_BSG is not set
88
89#
90# IO Schedulers
91#
92CONFIG_IOSCHED_NOOP=y
93CONFIG_IOSCHED_AS=y
94CONFIG_IOSCHED_DEADLINE=y
95CONFIG_IOSCHED_CFQ=y
96# CONFIG_DEFAULT_AS is not set
97# CONFIG_DEFAULT_DEADLINE is not set
98CONFIG_DEFAULT_CFQ=y
99# CONFIG_DEFAULT_NOOP is not set
100CONFIG_DEFAULT_IOSCHED="cfq"
101
102#
103# System Type
104#
105# CONFIG_ARCH_AAEC2000 is not set
106# CONFIG_ARCH_INTEGRATOR is not set
107# CONFIG_ARCH_REALVIEW is not set
108# CONFIG_ARCH_VERSATILE is not set
109# CONFIG_ARCH_AT91 is not set
110# CONFIG_ARCH_CLPS7500 is not set
111# CONFIG_ARCH_CLPS711X is not set
112# CONFIG_ARCH_CO285 is not set
113# CONFIG_ARCH_EBSA110 is not set
114# CONFIG_ARCH_EP93XX is not set
115# CONFIG_ARCH_FOOTBRIDGE is not set
116# CONFIG_ARCH_NETX is not set
117# CONFIG_ARCH_H720X is not set
118# CONFIG_ARCH_IMX is not set
119# CONFIG_ARCH_IOP13XX is not set
120# CONFIG_ARCH_IOP32X is not set
121# CONFIG_ARCH_IOP33X is not set
122# CONFIG_ARCH_IXP23XX is not set
123# CONFIG_ARCH_IXP2000 is not set
124# CONFIG_ARCH_IXP4XX is not set
125# CONFIG_ARCH_L7200 is not set
126# CONFIG_ARCH_KS8695 is not set
127# CONFIG_ARCH_NS9XXX is not set
128# CONFIG_ARCH_MXC is not set
129# CONFIG_ARCH_PNX4008 is not set
130# CONFIG_ARCH_PXA is not set
131# CONFIG_ARCH_RPC is not set
132# CONFIG_ARCH_SA1100 is not set
133# CONFIG_ARCH_S3C2410 is not set
134# CONFIG_ARCH_SHARK is not set
135# CONFIG_ARCH_LH7A40X is not set
136# CONFIG_ARCH_DAVINCI is not set
137CONFIG_ARCH_OMAP=y
138
139#
140# TI OMAP Implementations
141#
142CONFIG_ARCH_OMAP_OTG=y
143CONFIG_ARCH_OMAP1=y
144# CONFIG_ARCH_OMAP2 is not set
145# CONFIG_ARCH_OMAP3 is not set
146
147#
148# OMAP Feature Selections
149#
150# CONFIG_OMAP_RESET_CLOCKS is not set
151# CONFIG_OMAP_BOOT_TAG is not set
152# CONFIG_OMAP_GPIO_SWITCH is not set
153CONFIG_OMAP_MUX=y
154# CONFIG_OMAP_MUX_DEBUG is not set
155CONFIG_OMAP_MUX_WARNINGS=y
156CONFIG_OMAP_MCBSP=y
157# CONFIG_OMAP_MMU_FWK is not set
158# CONFIG_OMAP_MBOX_FWK is not set
159CONFIG_OMAP_MPU_TIMER=y
160# CONFIG_OMAP_32K_TIMER is not set
161CONFIG_OMAP_LL_DEBUG_UART1=y
162# CONFIG_OMAP_LL_DEBUG_UART2 is not set
163# CONFIG_OMAP_LL_DEBUG_UART3 is not set
164CONFIG_OMAP_SERIAL_WAKE=y
165
166#
167# OMAP Core Type
168#
169CONFIG_ARCH_OMAP730=y
170# CONFIG_ARCH_OMAP15XX is not set
171# CONFIG_ARCH_OMAP16XX is not set
172
173#
174# OMAP Board Type
175#
176CONFIG_MACH_OMAP_PERSEUS2=y
177# CONFIG_MACH_OMAP_FSAMPLE is not set
178
179#
180# OMAP CPU Speed
181#
182# CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER is not set
183# CONFIG_OMAP_ARM_195MHZ is not set
184CONFIG_OMAP_ARM_182MHZ=y
185# CONFIG_OMAP_ARM_168MHZ is not set
186# CONFIG_OMAP_ARM_120MHZ is not set
187# CONFIG_OMAP_ARM_60MHZ is not set
188# CONFIG_OMAP_ARM_30MHZ is not set
189# CONFIG_MACH_OMAP_APOLLON_PLUS is not set
190
191#
192# Boot options
193#
194
195#
196# Power management
197#
198
199#
200# Processor Type
201#
202CONFIG_CPU_32=y
203CONFIG_CPU_ARM926T=y
204CONFIG_CPU_32v5=y
205CONFIG_CPU_ABRT_EV5TJ=y
206CONFIG_CPU_PABRT_NOIFAR=y
207CONFIG_CPU_CACHE_VIVT=y
208CONFIG_CPU_COPY_V4WB=y
209CONFIG_CPU_TLB_V4WBI=y
210CONFIG_CPU_CP15=y
211CONFIG_CPU_CP15_MMU=y
212
213#
214# Processor Features
215#
216# CONFIG_ARM_THUMB is not set
217# CONFIG_CPU_ICACHE_DISABLE is not set
218# CONFIG_CPU_DCACHE_DISABLE is not set
219# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
220# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
221# CONFIG_OUTER_CACHE is not set
222
223#
224# Bus support
225#
226# CONFIG_PCI_SYSCALL is not set
227# CONFIG_ARCH_SUPPORTS_MSI is not set
228
229#
230# PCCARD (PCMCIA/CardBus) support
231#
232# CONFIG_PCCARD is not set
233
234#
235# Kernel Features
236#
237# CONFIG_TICK_ONESHOT is not set
238# CONFIG_NO_HZ is not set
239# CONFIG_HIGH_RES_TIMERS is not set
240CONFIG_PREEMPT=y
241CONFIG_HZ=100
242# CONFIG_AEABI is not set
243# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
244CONFIG_SELECT_MEMORY_MODEL=y
245CONFIG_FLATMEM_MANUAL=y
246# CONFIG_DISCONTIGMEM_MANUAL is not set
247# CONFIG_SPARSEMEM_MANUAL is not set
248CONFIG_FLATMEM=y
249CONFIG_FLAT_NODE_MEM_MAP=y
250# CONFIG_SPARSEMEM_STATIC is not set
251CONFIG_SPLIT_PTLOCK_CPUS=4096
252# CONFIG_RESOURCES_64BIT is not set
253CONFIG_ZONE_DMA_FLAG=1
254CONFIG_BOUNCE=y
255CONFIG_VIRT_TO_BUS=y
256CONFIG_LEDS=y
257CONFIG_LEDS_CPU=y
258CONFIG_ALIGNMENT_TRAP=y
259
260#
261# Boot options
262#
263CONFIG_ZBOOT_ROM_TEXT=0x0
264CONFIG_ZBOOT_ROM_BSS=0x0
265CONFIG_CMDLINE="mem=32M console=ttyS0,115200 ip=dhcp"
266# CONFIG_XIP_KERNEL is not set
267# CONFIG_KEXEC is not set
268
269#
270# CPU Frequency scaling
271#
272# CONFIG_CPU_FREQ is not set
273
274#
275# Floating point emulation
276#
277
278#
279# At least one emulation must be selected
280#
281CONFIG_FPE_NWFPE=y
282# CONFIG_FPE_NWFPE_XP is not set
283# CONFIG_FPE_FASTFPE is not set
284# CONFIG_VFP is not set
285
286#
287# Userspace binary formats
288#
289CONFIG_BINFMT_ELF=y
290# CONFIG_BINFMT_AOUT is not set
291# CONFIG_BINFMT_MISC is not set
292# CONFIG_ARTHUR is not set
293
294#
295# Power management options
296#
297CONFIG_PM=y
298# CONFIG_PM_LEGACY is not set
299# CONFIG_PM_DEBUG is not set
300CONFIG_PM_SLEEP=y
301CONFIG_SUSPEND_UP_POSSIBLE=y
302CONFIG_SUSPEND=y
303# CONFIG_APM_EMULATION is not set
304
305#
306# Networking
307#
308CONFIG_NET=y
309
310#
311# Networking options
312#
313CONFIG_PACKET=y
314# CONFIG_PACKET_MMAP is not set
315CONFIG_UNIX=y
316CONFIG_XFRM=y
317# CONFIG_XFRM_USER is not set
318# CONFIG_XFRM_SUB_POLICY is not set
319# CONFIG_XFRM_MIGRATE is not set
320# CONFIG_NET_KEY is not set
321CONFIG_INET=y
322CONFIG_IP_MULTICAST=y
323# CONFIG_IP_ADVANCED_ROUTER is not set
324CONFIG_IP_FIB_HASH=y
325CONFIG_IP_PNP=y
326CONFIG_IP_PNP_DHCP=y
327CONFIG_IP_PNP_BOOTP=y
328# CONFIG_IP_PNP_RARP is not set
329# CONFIG_NET_IPIP is not set
330# CONFIG_NET_IPGRE is not set
331# CONFIG_IP_MROUTE is not set
332# CONFIG_ARPD is not set
333# CONFIG_SYN_COOKIES is not set
334# CONFIG_INET_AH is not set
335# CONFIG_INET_ESP is not set
336# CONFIG_INET_IPCOMP is not set
337# CONFIG_INET_XFRM_TUNNEL is not set
338# CONFIG_INET_TUNNEL is not set
339CONFIG_INET_XFRM_MODE_TRANSPORT=y
340CONFIG_INET_XFRM_MODE_TUNNEL=y
341CONFIG_INET_XFRM_MODE_BEET=y
342CONFIG_INET_DIAG=y
343CONFIG_INET_TCP_DIAG=y
344# CONFIG_TCP_CONG_ADVANCED is not set
345CONFIG_TCP_CONG_CUBIC=y
346CONFIG_DEFAULT_TCP_CONG="cubic"
347# CONFIG_TCP_MD5SIG is not set
348# CONFIG_IPV6 is not set
349# CONFIG_INET6_XFRM_TUNNEL is not set
350# CONFIG_INET6_TUNNEL is not set
351# CONFIG_NETWORK_SECMARK is not set
352# CONFIG_NETFILTER is not set
353# CONFIG_IP_DCCP is not set
354# CONFIG_IP_SCTP is not set
355# CONFIG_TIPC is not set
356# CONFIG_ATM is not set
357# CONFIG_BRIDGE is not set
358# CONFIG_VLAN_8021Q is not set
359# CONFIG_DECNET is not set
360# CONFIG_LLC2 is not set
361# CONFIG_IPX is not set
362# CONFIG_ATALK is not set
363# CONFIG_X25 is not set
364# CONFIG_LAPB is not set
365# CONFIG_ECONET is not set
366# CONFIG_WAN_ROUTER is not set
367
368#
369# QoS and/or fair queueing
370#
371# CONFIG_NET_SCHED is not set
372
373#
374# Network testing
375#
376# CONFIG_NET_PKTGEN is not set
377# CONFIG_HAMRADIO is not set
378# CONFIG_IRDA is not set
379# CONFIG_BT is not set
380# CONFIG_AF_RXRPC is not set
381
382#
383# Wireless
384#
385# CONFIG_CFG80211 is not set
386# CONFIG_WIRELESS_EXT is not set
387# CONFIG_MAC80211 is not set
388# CONFIG_IEEE80211 is not set
389# CONFIG_RFKILL is not set
390# CONFIG_NET_9P is not set
391
392#
393# Device Drivers
394#
395
396#
397# Generic Driver Options
398#
399CONFIG_STANDALONE=y
400CONFIG_PREVENT_FIRMWARE_BUILD=y
401# CONFIG_FW_LOADER is not set
402# CONFIG_SYS_HYPERVISOR is not set
403# CONFIG_CONNECTOR is not set
404CONFIG_MTD=y
405# CONFIG_MTD_DEBUG is not set
406# CONFIG_MTD_CONCAT is not set
407CONFIG_MTD_PARTITIONS=y
408# CONFIG_MTD_REDBOOT_PARTS is not set
409CONFIG_MTD_CMDLINE_PARTS=y
410# CONFIG_MTD_AFS_PARTS is not set
411
412#
413# User Modules And Translation Layers
414#
415CONFIG_MTD_CHAR=y
416CONFIG_MTD_BLKDEVS=y
417CONFIG_MTD_BLOCK=y
418# CONFIG_FTL is not set
419# CONFIG_NFTL is not set
420# CONFIG_INFTL is not set
421# CONFIG_RFD_FTL is not set
422# CONFIG_SSFDC is not set
423
424#
425# RAM/ROM/Flash chip drivers
426#
427CONFIG_MTD_CFI=y
428# CONFIG_MTD_JEDECPROBE is not set
429CONFIG_MTD_GEN_PROBE=y
430# CONFIG_MTD_CFI_ADV_OPTIONS is not set
431CONFIG_MTD_MAP_BANK_WIDTH_1=y
432CONFIG_MTD_MAP_BANK_WIDTH_2=y
433CONFIG_MTD_MAP_BANK_WIDTH_4=y
434# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
435# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
436# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
437CONFIG_MTD_CFI_I1=y
438CONFIG_MTD_CFI_I2=y
439# CONFIG_MTD_CFI_I4 is not set
440# CONFIG_MTD_CFI_I8 is not set
441CONFIG_MTD_CFI_INTELEXT=y
442# CONFIG_MTD_CFI_AMDSTD is not set
443# CONFIG_MTD_CFI_STAA is not set
444CONFIG_MTD_CFI_UTIL=y
445# CONFIG_MTD_RAM is not set
446# CONFIG_MTD_ROM is not set
447# CONFIG_MTD_ABSENT is not set
448
449#
450# Mapping drivers for chip access
451#
452# CONFIG_MTD_COMPLEX_MAPPINGS is not set
453# CONFIG_MTD_PHYSMAP is not set
454# CONFIG_MTD_ARM_INTEGRATOR is not set
455CONFIG_MTD_OMAP_NOR=y
456# CONFIG_MTD_PLATRAM is not set
457
458#
459# Self-contained MTD device drivers
460#
461# CONFIG_MTD_SLRAM is not set
462# CONFIG_MTD_PHRAM is not set
463# CONFIG_MTD_MTDRAM is not set
464# CONFIG_MTD_BLOCK2MTD is not set
465
466#
467# Disk-On-Chip Device Drivers
468#
469# CONFIG_MTD_DOC2000 is not set
470# CONFIG_MTD_DOC2001 is not set
471# CONFIG_MTD_DOC2001PLUS is not set
472CONFIG_MTD_NAND=y
473# CONFIG_MTD_NAND_VERIFY_WRITE is not set
474# CONFIG_MTD_NAND_ECC_SMC is not set
475# CONFIG_MTD_NAND_MUSEUM_IDS is not set
476CONFIG_MTD_NAND_OMAP=y
477CONFIG_MTD_NAND_IDS=y
478# CONFIG_MTD_NAND_DISKONCHIP is not set
479# CONFIG_MTD_NAND_NANDSIM is not set
480# CONFIG_MTD_NAND_PLATFORM is not set
481# CONFIG_MTD_ONENAND is not set
482
483#
484# UBI - Unsorted block images
485#
486# CONFIG_MTD_UBI is not set
487# CONFIG_PARPORT is not set
488CONFIG_BLK_DEV=y
489# CONFIG_BLK_DEV_COW_COMMON is not set
490CONFIG_BLK_DEV_LOOP=y
491# CONFIG_BLK_DEV_CRYPTOLOOP is not set
492# CONFIG_BLK_DEV_NBD is not set
493CONFIG_BLK_DEV_RAM=y
494CONFIG_BLK_DEV_RAM_COUNT=16
495CONFIG_BLK_DEV_RAM_SIZE=8192
496CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
497# CONFIG_CDROM_PKTCDVD is not set
498# CONFIG_ATA_OVER_ETH is not set
499
500#
501# SCSI device support
502#
503# CONFIG_RAID_ATTRS is not set
504# CONFIG_SCSI is not set
505# CONFIG_SCSI_DMA is not set
506# CONFIG_SCSI_NETLINK is not set
507# CONFIG_ATA is not set
508# CONFIG_MD is not set
509CONFIG_NETDEVICES=y
510# CONFIG_NETDEVICES_MULTIQUEUE is not set
511# CONFIG_DUMMY is not set
512# CONFIG_BONDING is not set
513# CONFIG_MACVLAN is not set
514# CONFIG_EQUALIZER is not set
515# CONFIG_TUN is not set
516# CONFIG_PHYLIB is not set
517CONFIG_NET_ETHERNET=y
518CONFIG_MII=y
519# CONFIG_AX88796 is not set
520CONFIG_SMC91X=y
521# CONFIG_DM9000 is not set
522CONFIG_NETDEV_1000=y
523CONFIG_NETDEV_10000=y
524
525#
526# Wireless LAN
527#
528# CONFIG_WLAN_PRE80211 is not set
529# CONFIG_WLAN_80211 is not set
530# CONFIG_WAN is not set
531# CONFIG_PPP is not set
532# CONFIG_SLIP is not set
533# CONFIG_SHAPER is not set
534# CONFIG_NETCONSOLE is not set
535# CONFIG_NETPOLL is not set
536# CONFIG_NET_POLL_CONTROLLER is not set
537# CONFIG_ISDN is not set
538
539#
540# Input device support
541#
542CONFIG_INPUT=y
543# CONFIG_INPUT_FF_MEMLESS is not set
544# CONFIG_INPUT_POLLDEV is not set
545
546#
547# Userland interfaces
548#
549CONFIG_INPUT_MOUSEDEV=y
550CONFIG_INPUT_MOUSEDEV_PSAUX=y
551CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
552CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
553# CONFIG_INPUT_JOYDEV is not set
554# CONFIG_INPUT_TSDEV is not set
555# CONFIG_INPUT_EVDEV is not set
556# CONFIG_INPUT_EVBUG is not set
557
558#
559# Input Device Drivers
560#
561CONFIG_INPUT_KEYBOARD=y
562# CONFIG_KEYBOARD_ATKBD is not set
563# CONFIG_KEYBOARD_SUNKBD is not set
564# CONFIG_KEYBOARD_LKKBD is not set
565# CONFIG_KEYBOARD_XTKBD is not set
566# CONFIG_KEYBOARD_NEWTON is not set
567# CONFIG_KEYBOARD_STOWAWAY is not set
568CONFIG_KEYBOARD_OMAP=y
569# CONFIG_KEYBOARD_GPIO is not set
570# CONFIG_INPUT_MOUSE is not set
571# CONFIG_INPUT_JOYSTICK is not set
572# CONFIG_INPUT_TABLET is not set
573# CONFIG_INPUT_TOUCHSCREEN is not set
574# CONFIG_INPUT_MISC is not set
575
576#
577# Hardware I/O ports
578#
579CONFIG_SERIO=y
580CONFIG_SERIO_SERPORT=y
581# CONFIG_SERIO_RAW is not set
582# CONFIG_GAMEPORT is not set
583
584#
585# Character devices
586#
587CONFIG_VT=y
588CONFIG_VT_CONSOLE=y
589CONFIG_HW_CONSOLE=y
590# CONFIG_VT_HW_CONSOLE_BINDING is not set
591# CONFIG_SERIAL_NONSTANDARD is not set
592
593#
594# Serial drivers
595#
596CONFIG_SERIAL_8250=y
597CONFIG_SERIAL_8250_CONSOLE=y
598CONFIG_SERIAL_8250_NR_UARTS=4
599CONFIG_SERIAL_8250_RUNTIME_UARTS=4
600# CONFIG_SERIAL_8250_EXTENDED is not set
601
602#
603# Non-8250 serial port support
604#
605CONFIG_SERIAL_CORE=y
606CONFIG_SERIAL_CORE_CONSOLE=y
607CONFIG_UNIX98_PTYS=y
608# CONFIG_LEGACY_PTYS is not set
609# CONFIG_IPMI_HANDLER is not set
610# CONFIG_WATCHDOG is not set
611CONFIG_HW_RANDOM=m
612# CONFIG_NVRAM is not set
613# CONFIG_R3964 is not set
614# CONFIG_RAW_DRIVER is not set
615# CONFIG_TCG_TPM is not set
616# CONFIG_I2C is not set
617
618#
619# SPI support
620#
621# CONFIG_SPI is not set
622# CONFIG_SPI_MASTER is not set
623# CONFIG_W1 is not set
624CONFIG_HWMON=y
625# CONFIG_HWMON_VID is not set
626# CONFIG_SENSORS_ABITUGURU is not set
627# CONFIG_SENSORS_ABITUGURU3 is not set
628# CONFIG_SENSORS_F71805F is not set
629# CONFIG_SENSORS_IT87 is not set
630# CONFIG_SENSORS_PC87360 is not set
631# CONFIG_SENSORS_PC87427 is not set
632# CONFIG_SENSORS_SMSC47M1 is not set
633# CONFIG_SENSORS_SMSC47B397 is not set
634# CONFIG_SENSORS_VT1211 is not set
635# CONFIG_SENSORS_W83627HF is not set
636# CONFIG_SENSORS_W83627EHF is not set
637# CONFIG_HWMON_DEBUG_CHIP is not set
638CONFIG_MISC_DEVICES=y
639# CONFIG_EEPROM_93CX6 is not set
640
641#
642# Multifunction device drivers
643#
644# CONFIG_MFD_SM501 is not set
645# CONFIG_NEW_LEDS is not set
646
647#
648# Multimedia devices
649#
650# CONFIG_VIDEO_DEV is not set
651# CONFIG_DVB_CORE is not set
652CONFIG_DAB=y
653
654#
655# Graphics support
656#
657# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
658
659#
660# Display device support
661#
662# CONFIG_DISPLAY_SUPPORT is not set
663# CONFIG_VGASTATE is not set
664CONFIG_VIDEO_OUTPUT_CONTROL=m
665CONFIG_FB=y
666# CONFIG_FIRMWARE_EDID is not set
667# CONFIG_FB_DDC is not set
668# CONFIG_FB_CFB_FILLRECT is not set
669# CONFIG_FB_CFB_COPYAREA is not set
670# CONFIG_FB_CFB_IMAGEBLIT is not set
671CONFIG_FB_SYS_FILLRECT=y
672CONFIG_FB_SYS_COPYAREA=y
673CONFIG_FB_SYS_IMAGEBLIT=y
674CONFIG_FB_SYS_FOPS=y
675CONFIG_FB_DEFERRED_IO=y
676# CONFIG_FB_SVGALIB is not set
677# CONFIG_FB_MACMODES is not set
678# CONFIG_FB_BACKLIGHT is not set
679CONFIG_FB_MODE_HELPERS=y
680# CONFIG_FB_TILEBLITTING is not set
681
682#
683# Frame buffer hardware drivers
684#
685# CONFIG_FB_S1D13XXX is not set
686# CONFIG_FB_OMAP is not set
687CONFIG_FB_VIRTUAL=y
688
689#
690# Console display driver support
691#
692# CONFIG_VGA_CONSOLE is not set
693CONFIG_DUMMY_CONSOLE=y
694# CONFIG_FRAMEBUFFER_CONSOLE is not set
695# CONFIG_LOGO is not set
696
697#
698# Sound
699#
700# CONFIG_SOUND is not set
701CONFIG_HID_SUPPORT=y
702CONFIG_HID=y
703# CONFIG_HID_DEBUG is not set
704CONFIG_USB_SUPPORT=y
705CONFIG_USB_ARCH_HAS_HCD=y
706CONFIG_USB_ARCH_HAS_OHCI=y
707# CONFIG_USB_ARCH_HAS_EHCI is not set
708# CONFIG_USB is not set
709
710#
711# Enable Host or Gadget support to see Inventra options
712#
713
714#
715# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
716#
717
718#
719# USB Gadget Support
720#
721# CONFIG_USB_GADGET is not set
722# CONFIG_MMC is not set
723CONFIG_RTC_LIB=y
724CONFIG_RTC_CLASS=y
725CONFIG_RTC_HCTOSYS=y
726CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
727# CONFIG_RTC_DEBUG is not set
728
729#
730# RTC interfaces
731#
732CONFIG_RTC_INTF_SYSFS=y
733CONFIG_RTC_INTF_PROC=y
734CONFIG_RTC_INTF_DEV=y
735# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
736# CONFIG_RTC_DRV_TEST is not set
737
738#
739# SPI RTC drivers
740#
741
742#
743# Platform RTC drivers
744#
745# CONFIG_RTC_DRV_CMOS is not set
746# CONFIG_RTC_DRV_DS1553 is not set
747# CONFIG_RTC_DRV_STK17TA8 is not set
748# CONFIG_RTC_DRV_DS1742 is not set
749# CONFIG_RTC_DRV_M48T86 is not set
750# CONFIG_RTC_DRV_M48T59 is not set
751# CONFIG_RTC_DRV_V3020 is not set
752
753#
754# on-CPU RTC drivers
755#
756CONFIG_RTC_DRV_OMAP=y
757
758#
759# DMA Engine support
760#
761# CONFIG_DMA_ENGINE is not set
762
763#
764# DMA Clients
765#
766
767#
768# DMA Devices
769#
770
771#
772# CBUS support
773#
774# CONFIG_CBUS is not set
775
776#
777# File systems
778#
779CONFIG_EXT2_FS=y
780# CONFIG_EXT2_FS_XATTR is not set
781# CONFIG_EXT2_FS_XIP is not set
782# CONFIG_EXT3_FS is not set
783# CONFIG_EXT4DEV_FS is not set
784# CONFIG_REISERFS_FS is not set
785# CONFIG_JFS_FS is not set
786# CONFIG_FS_POSIX_ACL is not set
787# CONFIG_XFS_FS is not set
788# CONFIG_GFS2_FS is not set
789# CONFIG_OCFS2_FS is not set
790# CONFIG_MINIX_FS is not set
791# CONFIG_ROMFS_FS is not set
792CONFIG_INOTIFY=y
793CONFIG_INOTIFY_USER=y
794# CONFIG_QUOTA is not set
795CONFIG_DNOTIFY=y
796# CONFIG_AUTOFS_FS is not set
797# CONFIG_AUTOFS4_FS is not set
798# CONFIG_FUSE_FS is not set
799
800#
801# CD-ROM/DVD Filesystems
802#
803# CONFIG_ISO9660_FS is not set
804# CONFIG_UDF_FS is not set
805
806#
807# DOS/FAT/NT Filesystems
808#
809# CONFIG_MSDOS_FS is not set
810# CONFIG_VFAT_FS is not set
811# CONFIG_NTFS_FS is not set
812
813#
814# Pseudo filesystems
815#
816CONFIG_PROC_FS=y
817CONFIG_PROC_SYSCTL=y
818CONFIG_SYSFS=y
819# CONFIG_TMPFS is not set
820# CONFIG_HUGETLB_PAGE is not set
821CONFIG_RAMFS=y
822# CONFIG_CONFIGFS_FS is not set
823
824#
825# Miscellaneous filesystems
826#
827# CONFIG_ADFS_FS is not set
828# CONFIG_AFFS_FS is not set
829# CONFIG_HFS_FS is not set
830# CONFIG_HFSPLUS_FS is not set
831# CONFIG_BEFS_FS is not set
832# CONFIG_BFS_FS is not set
833# CONFIG_EFS_FS is not set
834CONFIG_JFFS2_FS=y
835CONFIG_JFFS2_FS_DEBUG=0
836CONFIG_JFFS2_FS_WRITEBUFFER=y
837# CONFIG_JFFS2_SUMMARY is not set
838# CONFIG_JFFS2_FS_XATTR is not set
839# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
840CONFIG_JFFS2_ZLIB=y
841CONFIG_JFFS2_RTIME=y
842# CONFIG_JFFS2_RUBIN is not set
843# CONFIG_CRAMFS is not set
844# CONFIG_VXFS_FS is not set
845# CONFIG_HPFS_FS is not set
846# CONFIG_QNX4FS_FS is not set
847# CONFIG_SYSV_FS is not set
848# CONFIG_UFS_FS is not set
849
850#
851# Network File Systems
852#
853CONFIG_NFS_FS=y
854# CONFIG_NFS_V3 is not set
855# CONFIG_NFS_V4 is not set
856# CONFIG_NFS_DIRECTIO is not set
857# CONFIG_NFSD is not set
858CONFIG_ROOT_NFS=y
859CONFIG_LOCKD=y
860CONFIG_NFS_COMMON=y
861CONFIG_SUNRPC=y
862# CONFIG_SUNRPC_BIND34 is not set
863# CONFIG_RPCSEC_GSS_KRB5 is not set
864# CONFIG_RPCSEC_GSS_SPKM3 is not set
865# CONFIG_SMB_FS is not set
866# CONFIG_CIFS is not set
867# CONFIG_NCP_FS is not set
868# CONFIG_CODA_FS is not set
869# CONFIG_AFS_FS is not set
870
871#
872# Partition Types
873#
874# CONFIG_PARTITION_ADVANCED is not set
875CONFIG_MSDOS_PARTITION=y
876
877#
878# Native Language Support
879#
880# CONFIG_NLS is not set
881
882#
883# Distributed Lock Manager
884#
885# CONFIG_DLM is not set
886
887#
888# Profiling support
889#
890# CONFIG_PROFILING is not set
891
892#
893# Kernel hacking
894#
895# CONFIG_PRINTK_TIME is not set
896CONFIG_ENABLE_MUST_CHECK=y
897# CONFIG_MAGIC_SYSRQ is not set
898# CONFIG_UNUSED_SYMBOLS is not set
899# CONFIG_DEBUG_FS is not set
900# CONFIG_HEADERS_CHECK is not set
901# CONFIG_DEBUG_KERNEL is not set
902CONFIG_DEBUG_BUGVERBOSE=y
903CONFIG_FRAME_POINTER=y
904# CONFIG_DEBUG_USER is not set
905
906#
907# Security options
908#
909# CONFIG_KEYS is not set
910# CONFIG_SECURITY is not set
911# CONFIG_CRYPTO is not set
912
913#
914# Library routines
915#
916CONFIG_BITREVERSE=y
917# CONFIG_CRC_CCITT is not set
918# CONFIG_CRC16 is not set
919# CONFIG_CRC_ITU_T is not set
920CONFIG_CRC32=y
921# CONFIG_CRC7 is not set
922# CONFIG_LIBCRC32C is not set
923CONFIG_ZLIB_INFLATE=y
924CONFIG_ZLIB_DEFLATE=y
925CONFIG_PLIST=y
926CONFIG_HAS_IOMEM=y
927CONFIG_HAS_IOPORT=y
928CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/orion5x_defconfig b/arch/arm/configs/orion5x_defconfig
index 1464ffe71717..4017d83c9d2d 100644
--- a/arch/arm/configs/orion5x_defconfig
+++ b/arch/arm/configs/orion5x_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc4 3# Linux kernel version: 2.6.27-rc4
4# Mon Jun 2 23:54:48 2008 4# Fri Aug 22 12:38:51 2008
5# 5#
6CONFIG_ARM=y 6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y 7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
@@ -12,6 +12,7 @@ CONFIG_MMU=y
12# CONFIG_NO_IOPORT is not set 12# CONFIG_NO_IOPORT is not set
13CONFIG_GENERIC_HARDIRQS=y 13CONFIG_GENERIC_HARDIRQS=y
14CONFIG_STACKTRACE_SUPPORT=y 14CONFIG_STACKTRACE_SUPPORT=y
15CONFIG_HAVE_LATENCYTOP_SUPPORT=y
15CONFIG_LOCKDEP_SUPPORT=y 16CONFIG_LOCKDEP_SUPPORT=y
16CONFIG_TRACE_IRQFLAGS_SUPPORT=y 17CONFIG_TRACE_IRQFLAGS_SUPPORT=y
17CONFIG_HARDIRQS_SW_RESEND=y 18CONFIG_HARDIRQS_SW_RESEND=y
@@ -23,6 +24,7 @@ CONFIG_GENERIC_HWEIGHT=y
23CONFIG_GENERIC_CALIBRATE_DELAY=y 24CONFIG_GENERIC_CALIBRATE_DELAY=y
24CONFIG_ARCH_SUPPORTS_AOUT=y 25CONFIG_ARCH_SUPPORTS_AOUT=y
25CONFIG_ZONE_DMA=y 26CONFIG_ZONE_DMA=y
27CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
26CONFIG_VECTORS_BASE=0xffff0000 28CONFIG_VECTORS_BASE=0xffff0000
27CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 29CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
28 30
@@ -56,7 +58,6 @@ CONFIG_SYSCTL=y
56CONFIG_EMBEDDED=y 58CONFIG_EMBEDDED=y
57CONFIG_UID16=y 59CONFIG_UID16=y
58CONFIG_SYSCTL_SYSCALL=y 60CONFIG_SYSCTL_SYSCALL=y
59CONFIG_SYSCTL_SYSCALL_CHECK=y
60CONFIG_KALLSYMS=y 61CONFIG_KALLSYMS=y
61CONFIG_KALLSYMS_ALL=y 62CONFIG_KALLSYMS_ALL=y
62# CONFIG_KALLSYMS_EXTRA_PASS is not set 63# CONFIG_KALLSYMS_EXTRA_PASS is not set
@@ -83,11 +84,17 @@ CONFIG_PROFILING=y
83CONFIG_OPROFILE=y 84CONFIG_OPROFILE=y
84CONFIG_HAVE_OPROFILE=y 85CONFIG_HAVE_OPROFILE=y
85CONFIG_KPROBES=y 86CONFIG_KPROBES=y
87# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
86CONFIG_KRETPROBES=y 88CONFIG_KRETPROBES=y
89# CONFIG_HAVE_IOREMAP_PROT is not set
87CONFIG_HAVE_KPROBES=y 90CONFIG_HAVE_KPROBES=y
88CONFIG_HAVE_KRETPROBES=y 91CONFIG_HAVE_KRETPROBES=y
92# CONFIG_HAVE_ARCH_TRACEHOOK is not set
89# CONFIG_HAVE_DMA_ATTRS is not set 93# CONFIG_HAVE_DMA_ATTRS is not set
94# CONFIG_USE_GENERIC_SMP_HELPERS is not set
95# CONFIG_HAVE_CLK is not set
90CONFIG_PROC_PAGE_MONITOR=y 96CONFIG_PROC_PAGE_MONITOR=y
97CONFIG_HAVE_GENERIC_DMA_COHERENT=y
91CONFIG_RT_MUTEXES=y 98CONFIG_RT_MUTEXES=y
92# CONFIG_TINY_SHMEM is not set 99# CONFIG_TINY_SHMEM is not set
93CONFIG_BASE_SMALL=0 100CONFIG_BASE_SMALL=0
@@ -97,12 +104,13 @@ CONFIG_MODULE_UNLOAD=y
97# CONFIG_MODULE_FORCE_UNLOAD is not set 104# CONFIG_MODULE_FORCE_UNLOAD is not set
98# CONFIG_MODVERSIONS is not set 105# CONFIG_MODVERSIONS is not set
99# CONFIG_MODULE_SRCVERSION_ALL is not set 106# CONFIG_MODULE_SRCVERSION_ALL is not set
100# CONFIG_KMOD is not set 107CONFIG_KMOD=y
101CONFIG_BLOCK=y 108CONFIG_BLOCK=y
102# CONFIG_LBD is not set 109# CONFIG_LBD is not set
103# CONFIG_BLK_DEV_IO_TRACE is not set 110# CONFIG_BLK_DEV_IO_TRACE is not set
104# CONFIG_LSF is not set 111# CONFIG_LSF is not set
105# CONFIG_BLK_DEV_BSG is not set 112# CONFIG_BLK_DEV_BSG is not set
113# CONFIG_BLK_DEV_INTEGRITY is not set
106 114
107# 115#
108# IO Schedulers 116# IO Schedulers
@@ -128,7 +136,6 @@ CONFIG_CLASSIC_RCU=y
128# CONFIG_ARCH_AT91 is not set 136# CONFIG_ARCH_AT91 is not set
129# CONFIG_ARCH_CLPS7500 is not set 137# CONFIG_ARCH_CLPS7500 is not set
130# CONFIG_ARCH_CLPS711X is not set 138# CONFIG_ARCH_CLPS711X is not set
131# CONFIG_ARCH_CO285 is not set
132# CONFIG_ARCH_EBSA110 is not set 139# CONFIG_ARCH_EBSA110 is not set
133# CONFIG_ARCH_EP93XX is not set 140# CONFIG_ARCH_EP93XX is not set
134# CONFIG_ARCH_FOOTBRIDGE is not set 141# CONFIG_ARCH_FOOTBRIDGE is not set
@@ -142,8 +149,11 @@ CONFIG_CLASSIC_RCU=y
142# CONFIG_ARCH_IXP2000 is not set 149# CONFIG_ARCH_IXP2000 is not set
143# CONFIG_ARCH_IXP4XX is not set 150# CONFIG_ARCH_IXP4XX is not set
144# CONFIG_ARCH_L7200 is not set 151# CONFIG_ARCH_L7200 is not set
152# CONFIG_ARCH_KIRKWOOD is not set
145# CONFIG_ARCH_KS8695 is not set 153# CONFIG_ARCH_KS8695 is not set
146# CONFIG_ARCH_NS9XXX is not set 154# CONFIG_ARCH_NS9XXX is not set
155# CONFIG_ARCH_LOKI is not set
156# CONFIG_ARCH_MV78XX0 is not set
147# CONFIG_ARCH_MXC is not set 157# CONFIG_ARCH_MXC is not set
148CONFIG_ARCH_ORION5X=y 158CONFIG_ARCH_ORION5X=y
149# CONFIG_ARCH_PNX4008 is not set 159# CONFIG_ARCH_PNX4008 is not set
@@ -195,7 +205,7 @@ CONFIG_CPU_ABRT_EV5T=y
195CONFIG_CPU_PABRT_NOIFAR=y 205CONFIG_CPU_PABRT_NOIFAR=y
196CONFIG_CPU_CACHE_VIVT=y 206CONFIG_CPU_CACHE_VIVT=y
197CONFIG_CPU_COPY_FEROCEON=y 207CONFIG_CPU_COPY_FEROCEON=y
198CONFIG_CPU_TLB_V4WBI=y 208CONFIG_CPU_TLB_FEROCEON=y
199CONFIG_CPU_CP15=y 209CONFIG_CPU_CP15=y
200CONFIG_CPU_CP15_MMU=y 210CONFIG_CPU_CP15_MMU=y
201 211
@@ -280,10 +290,6 @@ CONFIG_BINFMT_ELF=y
280# 290#
281# CONFIG_PM is not set 291# CONFIG_PM is not set
282CONFIG_ARCH_SUSPEND_POSSIBLE=y 292CONFIG_ARCH_SUSPEND_POSSIBLE=y
283
284#
285# Networking
286#
287CONFIG_NET=y 293CONFIG_NET=y
288 294
289# 295#
@@ -361,6 +367,7 @@ CONFIG_NET_PKTGEN=m
361# 367#
362# CONFIG_CFG80211 is not set 368# CONFIG_CFG80211 is not set
363CONFIG_WIRELESS_EXT=y 369CONFIG_WIRELESS_EXT=y
370CONFIG_WIRELESS_EXT_SYSFS=y
364# CONFIG_MAC80211 is not set 371# CONFIG_MAC80211 is not set
365# CONFIG_IEEE80211 is not set 372# CONFIG_IEEE80211 is not set
366# CONFIG_RFKILL is not set 373# CONFIG_RFKILL is not set
@@ -377,6 +384,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
377CONFIG_STANDALONE=y 384CONFIG_STANDALONE=y
378CONFIG_PREVENT_FIRMWARE_BUILD=y 385CONFIG_PREVENT_FIRMWARE_BUILD=y
379CONFIG_FW_LOADER=y 386CONFIG_FW_LOADER=y
387# CONFIG_FIRMWARE_IN_KERNEL is not set
388CONFIG_EXTRA_FIRMWARE=""
380# CONFIG_DEBUG_DRIVER is not set 389# CONFIG_DEBUG_DRIVER is not set
381# CONFIG_DEBUG_DEVRES is not set 390# CONFIG_DEBUG_DEVRES is not set
382# CONFIG_SYS_HYPERVISOR is not set 391# CONFIG_SYS_HYPERVISOR is not set
@@ -499,6 +508,7 @@ CONFIG_MISC_DEVICES=y
499# CONFIG_SGI_IOC4 is not set 508# CONFIG_SGI_IOC4 is not set
500# CONFIG_TIFM_CORE is not set 509# CONFIG_TIFM_CORE is not set
501# CONFIG_ENCLOSURE_SERVICES is not set 510# CONFIG_ENCLOSURE_SERVICES is not set
511# CONFIG_HP_ILO is not set
502CONFIG_HAVE_IDE=y 512CONFIG_HAVE_IDE=y
503# CONFIG_IDE is not set 513# CONFIG_IDE is not set
504 514
@@ -575,6 +585,7 @@ CONFIG_SCSI_LOWLEVEL=y
575# CONFIG_SCSI_NSP32 is not set 585# CONFIG_SCSI_NSP32 is not set
576# CONFIG_SCSI_DEBUG is not set 586# CONFIG_SCSI_DEBUG is not set
577# CONFIG_SCSI_SRP is not set 587# CONFIG_SCSI_SRP is not set
588# CONFIG_SCSI_DH is not set
578CONFIG_ATA=y 589CONFIG_ATA=y
579# CONFIG_ATA_NONSTANDARD is not set 590# CONFIG_ATA_NONSTANDARD is not set
580CONFIG_SATA_PMP=y 591CONFIG_SATA_PMP=y
@@ -641,11 +652,14 @@ CONFIG_SATA_MV=y
641# 652#
642# IEEE 1394 (FireWire) support 653# IEEE 1394 (FireWire) support
643# 654#
655
656#
657# Enable only one of the two stacks, unless you know what you are doing
658#
644# CONFIG_FIREWIRE is not set 659# CONFIG_FIREWIRE is not set
645# CONFIG_IEEE1394 is not set 660# CONFIG_IEEE1394 is not set
646# CONFIG_I2O is not set 661# CONFIG_I2O is not set
647CONFIG_NETDEVICES=y 662CONFIG_NETDEVICES=y
648# CONFIG_NETDEVICES_MULTIQUEUE is not set
649# CONFIG_DUMMY is not set 663# CONFIG_DUMMY is not set
650# CONFIG_BONDING is not set 664# CONFIG_BONDING is not set
651# CONFIG_MACVLAN is not set 665# CONFIG_MACVLAN is not set
@@ -694,7 +708,6 @@ CONFIG_NETDEV_1000=y
694# CONFIG_DL2K is not set 708# CONFIG_DL2K is not set
695# CONFIG_E1000 is not set 709# CONFIG_E1000 is not set
696# CONFIG_E1000E is not set 710# CONFIG_E1000E is not set
697# CONFIG_E1000E_ENABLED is not set
698# CONFIG_IP1000 is not set 711# CONFIG_IP1000 is not set
699# CONFIG_IGB is not set 712# CONFIG_IGB is not set
700# CONFIG_NS83820 is not set 713# CONFIG_NS83820 is not set
@@ -710,6 +723,7 @@ CONFIG_NETDEV_1000=y
710CONFIG_MV643XX_ETH=y 723CONFIG_MV643XX_ETH=y
711# CONFIG_QLA3XXX is not set 724# CONFIG_QLA3XXX is not set
712# CONFIG_ATL1 is not set 725# CONFIG_ATL1 is not set
726# CONFIG_ATL1E is not set
713# CONFIG_NETDEV_10000 is not set 727# CONFIG_NETDEV_10000 is not set
714# CONFIG_TR is not set 728# CONFIG_TR is not set
715 729
@@ -815,44 +829,65 @@ CONFIG_DEVPORT=y
815CONFIG_I2C=y 829CONFIG_I2C=y
816CONFIG_I2C_BOARDINFO=y 830CONFIG_I2C_BOARDINFO=y
817CONFIG_I2C_CHARDEV=y 831CONFIG_I2C_CHARDEV=y
832CONFIG_I2C_HELPER_AUTO=y
818 833
819# 834#
820# I2C Hardware Bus support 835# I2C Hardware Bus support
821# 836#
837
838#
839# PC SMBus host controller drivers
840#
822# CONFIG_I2C_ALI1535 is not set 841# CONFIG_I2C_ALI1535 is not set
823# CONFIG_I2C_ALI1563 is not set 842# CONFIG_I2C_ALI1563 is not set
824# CONFIG_I2C_ALI15X3 is not set 843# CONFIG_I2C_ALI15X3 is not set
825# CONFIG_I2C_AMD756 is not set 844# CONFIG_I2C_AMD756 is not set
826# CONFIG_I2C_AMD8111 is not set 845# CONFIG_I2C_AMD8111 is not set
827# CONFIG_I2C_GPIO is not set
828# CONFIG_I2C_I801 is not set 846# CONFIG_I2C_I801 is not set
829# CONFIG_I2C_I810 is not set 847# CONFIG_I2C_ISCH is not set
830# CONFIG_I2C_PIIX4 is not set 848# CONFIG_I2C_PIIX4 is not set
831# CONFIG_I2C_NFORCE2 is not set 849# CONFIG_I2C_NFORCE2 is not set
832# CONFIG_I2C_OCORES is not set
833# CONFIG_I2C_PARPORT_LIGHT is not set
834# CONFIG_I2C_PROSAVAGE is not set
835# CONFIG_I2C_SAVAGE4 is not set
836# CONFIG_I2C_SIMTEC is not set
837# CONFIG_I2C_SIS5595 is not set 850# CONFIG_I2C_SIS5595 is not set
838# CONFIG_I2C_SIS630 is not set 851# CONFIG_I2C_SIS630 is not set
839# CONFIG_I2C_SIS96X is not set 852# CONFIG_I2C_SIS96X is not set
840# CONFIG_I2C_TAOS_EVM is not set
841# CONFIG_I2C_STUB is not set
842# CONFIG_I2C_TINY_USB is not set
843# CONFIG_I2C_VIA is not set 853# CONFIG_I2C_VIA is not set
844# CONFIG_I2C_VIAPRO is not set 854# CONFIG_I2C_VIAPRO is not set
855
856#
857# I2C system bus drivers (mostly embedded / system-on-chip)
858#
859# CONFIG_I2C_GPIO is not set
860CONFIG_I2C_MV64XXX=y
861# CONFIG_I2C_OCORES is not set
862# CONFIG_I2C_SIMTEC is not set
863
864#
865# External I2C/SMBus adapter drivers
866#
867# CONFIG_I2C_PARPORT_LIGHT is not set
868# CONFIG_I2C_TAOS_EVM is not set
869# CONFIG_I2C_TINY_USB is not set
870
871#
872# Graphics adapter I2C/DDC channel drivers
873#
845# CONFIG_I2C_VOODOO3 is not set 874# CONFIG_I2C_VOODOO3 is not set
875
876#
877# Other I2C/SMBus bus drivers
878#
846# CONFIG_I2C_PCA_PLATFORM is not set 879# CONFIG_I2C_PCA_PLATFORM is not set
847CONFIG_I2C_MV64XXX=y 880# CONFIG_I2C_STUB is not set
848 881
849# 882#
850# Miscellaneous I2C Chip support 883# Miscellaneous I2C Chip support
851# 884#
852# CONFIG_DS1682 is not set 885# CONFIG_DS1682 is not set
886# CONFIG_AT24 is not set
853# CONFIG_SENSORS_EEPROM is not set 887# CONFIG_SENSORS_EEPROM is not set
854# CONFIG_SENSORS_PCF8574 is not set 888# CONFIG_SENSORS_PCF8574 is not set
855# CONFIG_PCF8575 is not set 889# CONFIG_PCF8575 is not set
890# CONFIG_SENSORS_PCA9539 is not set
856# CONFIG_SENSORS_PCF8591 is not set 891# CONFIG_SENSORS_PCF8591 is not set
857# CONFIG_SENSORS_MAX6875 is not set 892# CONFIG_SENSORS_MAX6875 is not set
858# CONFIG_SENSORS_TSL2550 is not set 893# CONFIG_SENSORS_TSL2550 is not set
@@ -865,6 +900,7 @@ CONFIG_I2C_MV64XXX=y
865# CONFIG_POWER_SUPPLY is not set 900# CONFIG_POWER_SUPPLY is not set
866CONFIG_HWMON=y 901CONFIG_HWMON=y
867# CONFIG_HWMON_VID is not set 902# CONFIG_HWMON_VID is not set
903# CONFIG_SENSORS_AD7414 is not set
868# CONFIG_SENSORS_AD7418 is not set 904# CONFIG_SENSORS_AD7418 is not set
869# CONFIG_SENSORS_ADM1021 is not set 905# CONFIG_SENSORS_ADM1021 is not set
870# CONFIG_SENSORS_ADM1025 is not set 906# CONFIG_SENSORS_ADM1025 is not set
@@ -884,7 +920,7 @@ CONFIG_HWMON=y
884# CONFIG_SENSORS_GL520SM is not set 920# CONFIG_SENSORS_GL520SM is not set
885# CONFIG_SENSORS_IT87 is not set 921# CONFIG_SENSORS_IT87 is not set
886# CONFIG_SENSORS_LM63 is not set 922# CONFIG_SENSORS_LM63 is not set
887# CONFIG_SENSORS_LM75 is not set 923CONFIG_SENSORS_LM75=y
888# CONFIG_SENSORS_LM77 is not set 924# CONFIG_SENSORS_LM77 is not set
889# CONFIG_SENSORS_LM78 is not set 925# CONFIG_SENSORS_LM78 is not set
890# CONFIG_SENSORS_LM80 is not set 926# CONFIG_SENSORS_LM80 is not set
@@ -928,9 +964,12 @@ CONFIG_SSB_POSSIBLE=y
928# 964#
929# Multifunction device drivers 965# Multifunction device drivers
930# 966#
967# CONFIG_MFD_CORE is not set
931# CONFIG_MFD_SM501 is not set 968# CONFIG_MFD_SM501 is not set
932# CONFIG_MFD_ASIC3 is not set
933# CONFIG_HTC_PASIC3 is not set 969# CONFIG_HTC_PASIC3 is not set
970# CONFIG_MFD_TMIO is not set
971# CONFIG_MFD_T7L66XB is not set
972# CONFIG_MFD_TC6387XB is not set
934 973
935# 974#
936# Multimedia devices 975# Multimedia devices
@@ -961,10 +1000,6 @@ CONFIG_SSB_POSSIBLE=y
961# Display device support 1000# Display device support
962# 1001#
963# CONFIG_DISPLAY_SUPPORT is not set 1002# CONFIG_DISPLAY_SUPPORT is not set
964
965#
966# Sound
967#
968# CONFIG_SOUND is not set 1003# CONFIG_SOUND is not set
969CONFIG_HID_SUPPORT=y 1004CONFIG_HID_SUPPORT=y
970CONFIG_HID=y 1005CONFIG_HID=y
@@ -995,6 +1030,7 @@ CONFIG_USB_DEVICE_CLASS=y
995# CONFIG_USB_OTG is not set 1030# CONFIG_USB_OTG is not set
996# CONFIG_USB_OTG_WHITELIST is not set 1031# CONFIG_USB_OTG_WHITELIST is not set
997# CONFIG_USB_OTG_BLACKLIST_HUB is not set 1032# CONFIG_USB_OTG_BLACKLIST_HUB is not set
1033# CONFIG_USB_MON is not set
998 1034
999# 1035#
1000# USB Host Controller Drivers 1036# USB Host Controller Drivers
@@ -1037,6 +1073,7 @@ CONFIG_USB_STORAGE_JUMPSHOT=y
1037# CONFIG_USB_STORAGE_ALAUDA is not set 1073# CONFIG_USB_STORAGE_ALAUDA is not set
1038# CONFIG_USB_STORAGE_ONETOUCH is not set 1074# CONFIG_USB_STORAGE_ONETOUCH is not set
1039# CONFIG_USB_STORAGE_KARMA is not set 1075# CONFIG_USB_STORAGE_KARMA is not set
1076# CONFIG_USB_STORAGE_SIERRA is not set
1040# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set 1077# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
1041# CONFIG_USB_LIBUSUAL is not set 1078# CONFIG_USB_LIBUSUAL is not set
1042 1079
@@ -1045,7 +1082,6 @@ CONFIG_USB_STORAGE_JUMPSHOT=y
1045# 1082#
1046# CONFIG_USB_MDC800 is not set 1083# CONFIG_USB_MDC800 is not set
1047# CONFIG_USB_MICROTEK is not set 1084# CONFIG_USB_MICROTEK is not set
1048# CONFIG_USB_MON is not set
1049 1085
1050# 1086#
1051# USB port drivers 1087# USB port drivers
@@ -1058,7 +1094,6 @@ CONFIG_USB_STORAGE_JUMPSHOT=y
1058# CONFIG_USB_EMI62 is not set 1094# CONFIG_USB_EMI62 is not set
1059# CONFIG_USB_EMI26 is not set 1095# CONFIG_USB_EMI26 is not set
1060# CONFIG_USB_ADUTUX is not set 1096# CONFIG_USB_ADUTUX is not set
1061# CONFIG_USB_AUERSWALD is not set
1062# CONFIG_USB_RIO500 is not set 1097# CONFIG_USB_RIO500 is not set
1063# CONFIG_USB_LEGOTOWER is not set 1098# CONFIG_USB_LEGOTOWER is not set
1064# CONFIG_USB_LCD is not set 1099# CONFIG_USB_LCD is not set
@@ -1084,7 +1119,9 @@ CONFIG_LEDS_CLASS=y
1084# 1119#
1085# LED drivers 1120# LED drivers
1086# 1121#
1122# CONFIG_LEDS_PCA9532 is not set
1087CONFIG_LEDS_GPIO=y 1123CONFIG_LEDS_GPIO=y
1124# CONFIG_LEDS_PCA955X is not set
1088 1125
1089# 1126#
1090# LED Triggers 1127# LED Triggers
@@ -1123,6 +1160,7 @@ CONFIG_RTC_DRV_PCF8563=y
1123CONFIG_RTC_DRV_M41T80=y 1160CONFIG_RTC_DRV_M41T80=y
1124# CONFIG_RTC_DRV_M41T80_WDT is not set 1161# CONFIG_RTC_DRV_M41T80_WDT is not set
1125CONFIG_RTC_DRV_S35390A=y 1162CONFIG_RTC_DRV_S35390A=y
1163# CONFIG_RTC_DRV_FM3130 is not set
1126 1164
1127# 1165#
1128# SPI RTC drivers 1166# SPI RTC drivers
@@ -1143,6 +1181,27 @@ CONFIG_RTC_DRV_S35390A=y
1143# 1181#
1144# on-CPU RTC drivers 1182# on-CPU RTC drivers
1145# 1183#
1184CONFIG_DMADEVICES=y
1185
1186#
1187# DMA Devices
1188#
1189CONFIG_MV_XOR=y
1190CONFIG_DMA_ENGINE=y
1191
1192#
1193# DMA Clients
1194#
1195# CONFIG_NET_DMA is not set
1196# CONFIG_DMATEST is not set
1197
1198#
1199# Voltage and Current regulators
1200#
1201# CONFIG_REGULATOR is not set
1202# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
1203# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
1204# CONFIG_REGULATOR_BQ24022 is not set
1146# CONFIG_UIO is not set 1205# CONFIG_UIO is not set
1147 1206
1148# 1207#
@@ -1222,6 +1281,7 @@ CONFIG_JFFS2_RTIME=y
1222CONFIG_CRAMFS=y 1281CONFIG_CRAMFS=y
1223# CONFIG_VXFS_FS is not set 1282# CONFIG_VXFS_FS is not set
1224# CONFIG_MINIX_FS is not set 1283# CONFIG_MINIX_FS is not set
1284# CONFIG_OMFS_FS is not set
1225# CONFIG_HPFS_FS is not set 1285# CONFIG_HPFS_FS is not set
1226# CONFIG_QNX4FS_FS is not set 1286# CONFIG_QNX4FS_FS is not set
1227# CONFIG_ROMFS_FS is not set 1287# CONFIG_ROMFS_FS is not set
@@ -1232,13 +1292,12 @@ CONFIG_NFS_FS=y
1232CONFIG_NFS_V3=y 1292CONFIG_NFS_V3=y
1233# CONFIG_NFS_V3_ACL is not set 1293# CONFIG_NFS_V3_ACL is not set
1234# CONFIG_NFS_V4 is not set 1294# CONFIG_NFS_V4 is not set
1235# CONFIG_NFSD is not set
1236CONFIG_ROOT_NFS=y 1295CONFIG_ROOT_NFS=y
1296# CONFIG_NFSD is not set
1237CONFIG_LOCKD=y 1297CONFIG_LOCKD=y
1238CONFIG_LOCKD_V4=y 1298CONFIG_LOCKD_V4=y
1239CONFIG_NFS_COMMON=y 1299CONFIG_NFS_COMMON=y
1240CONFIG_SUNRPC=y 1300CONFIG_SUNRPC=y
1241# CONFIG_SUNRPC_BIND34 is not set
1242# CONFIG_RPCSEC_GSS_KRB5 is not set 1301# CONFIG_RPCSEC_GSS_KRB5 is not set
1243# CONFIG_RPCSEC_GSS_SPKM3 is not set 1302# CONFIG_RPCSEC_GSS_SPKM3 is not set
1244# CONFIG_SMB_FS is not set 1303# CONFIG_SMB_FS is not set
@@ -1324,6 +1383,8 @@ CONFIG_MAGIC_SYSRQ=y
1324CONFIG_DEBUG_KERNEL=y 1383CONFIG_DEBUG_KERNEL=y
1325# CONFIG_DEBUG_SHIRQ is not set 1384# CONFIG_DEBUG_SHIRQ is not set
1326CONFIG_DETECT_SOFTLOCKUP=y 1385CONFIG_DETECT_SOFTLOCKUP=y
1386# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
1387CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
1327CONFIG_SCHED_DEBUG=y 1388CONFIG_SCHED_DEBUG=y
1328CONFIG_SCHEDSTATS=y 1389CONFIG_SCHEDSTATS=y
1329# CONFIG_TIMER_STATS is not set 1390# CONFIG_TIMER_STATS is not set
@@ -1338,11 +1399,13 @@ CONFIG_DEBUG_PREEMPT=y
1338# CONFIG_LOCK_STAT is not set 1399# CONFIG_LOCK_STAT is not set
1339# CONFIG_DEBUG_SPINLOCK_SLEEP is not set 1400# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1340# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set 1401# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1402CONFIG_STACKTRACE=y
1341# CONFIG_DEBUG_KOBJECT is not set 1403# CONFIG_DEBUG_KOBJECT is not set
1342# CONFIG_DEBUG_BUGVERBOSE is not set 1404# CONFIG_DEBUG_BUGVERBOSE is not set
1343CONFIG_DEBUG_INFO=y 1405CONFIG_DEBUG_INFO=y
1344# CONFIG_DEBUG_VM is not set 1406# CONFIG_DEBUG_VM is not set
1345# CONFIG_DEBUG_WRITECOUNT is not set 1407# CONFIG_DEBUG_WRITECOUNT is not set
1408# CONFIG_DEBUG_MEMORY_INIT is not set
1346# CONFIG_DEBUG_LIST is not set 1409# CONFIG_DEBUG_LIST is not set
1347# CONFIG_DEBUG_SG is not set 1410# CONFIG_DEBUG_SG is not set
1348CONFIG_FRAME_POINTER=y 1411CONFIG_FRAME_POINTER=y
@@ -1352,7 +1415,18 @@ CONFIG_FRAME_POINTER=y
1352# CONFIG_BACKTRACE_SELF_TEST is not set 1415# CONFIG_BACKTRACE_SELF_TEST is not set
1353# CONFIG_LKDTM is not set 1416# CONFIG_LKDTM is not set
1354# CONFIG_FAULT_INJECTION is not set 1417# CONFIG_FAULT_INJECTION is not set
1418CONFIG_LATENCYTOP=y
1419CONFIG_SYSCTL_SYSCALL_CHECK=y
1420CONFIG_HAVE_FTRACE=y
1421CONFIG_HAVE_DYNAMIC_FTRACE=y
1422# CONFIG_FTRACE is not set
1423# CONFIG_IRQSOFF_TRACER is not set
1424# CONFIG_PREEMPT_TRACER is not set
1425# CONFIG_SCHED_TRACER is not set
1426# CONFIG_CONTEXT_SWITCH_TRACER is not set
1355# CONFIG_SAMPLES is not set 1427# CONFIG_SAMPLES is not set
1428CONFIG_HAVE_ARCH_KGDB=y
1429# CONFIG_KGDB is not set
1356CONFIG_DEBUG_USER=y 1430CONFIG_DEBUG_USER=y
1357CONFIG_DEBUG_ERRORS=y 1431CONFIG_DEBUG_ERRORS=y
1358# CONFIG_DEBUG_STACK_USAGE is not set 1432# CONFIG_DEBUG_STACK_USAGE is not set
@@ -1365,6 +1439,7 @@ CONFIG_DEBUG_LL=y
1365# CONFIG_KEYS is not set 1439# CONFIG_KEYS is not set
1366# CONFIG_SECURITY is not set 1440# CONFIG_SECURITY is not set
1367# CONFIG_SECURITY_FILE_CAPABILITIES is not set 1441# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1442CONFIG_ASYNC_CORE=y
1368CONFIG_CRYPTO=y 1443CONFIG_CRYPTO=y
1369 1444
1370# 1445#
@@ -1410,6 +1485,10 @@ CONFIG_CRYPTO_PCBC=m
1410# CONFIG_CRYPTO_MD4 is not set 1485# CONFIG_CRYPTO_MD4 is not set
1411# CONFIG_CRYPTO_MD5 is not set 1486# CONFIG_CRYPTO_MD5 is not set
1412# CONFIG_CRYPTO_MICHAEL_MIC is not set 1487# CONFIG_CRYPTO_MICHAEL_MIC is not set
1488# CONFIG_CRYPTO_RMD128 is not set
1489# CONFIG_CRYPTO_RMD160 is not set
1490# CONFIG_CRYPTO_RMD256 is not set
1491# CONFIG_CRYPTO_RMD320 is not set
1413# CONFIG_CRYPTO_SHA1 is not set 1492# CONFIG_CRYPTO_SHA1 is not set
1414# CONFIG_CRYPTO_SHA256 is not set 1493# CONFIG_CRYPTO_SHA256 is not set
1415# CONFIG_CRYPTO_SHA512 is not set 1494# CONFIG_CRYPTO_SHA512 is not set
@@ -1451,6 +1530,7 @@ CONFIG_BITREVERSE=y
1451# CONFIG_GENERIC_FIND_NEXT_BIT is not set 1530# CONFIG_GENERIC_FIND_NEXT_BIT is not set
1452# CONFIG_CRC_CCITT is not set 1531# CONFIG_CRC_CCITT is not set
1453# CONFIG_CRC16 is not set 1532# CONFIG_CRC16 is not set
1533CONFIG_CRC_T10DIF=y
1454CONFIG_CRC_ITU_T=m 1534CONFIG_CRC_ITU_T=m
1455CONFIG_CRC32=y 1535CONFIG_CRC32=y
1456# CONFIG_CRC7 is not set 1536# CONFIG_CRC7 is not set
diff --git a/arch/arm/configs/palmte_defconfig b/arch/arm/configs/palmte_defconfig
new file mode 100644
index 000000000000..40fc6a778e00
--- /dev/null
+++ b/arch/arm/configs/palmte_defconfig
@@ -0,0 +1,761 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.22-rc1-omap1
4# Sat May 19 11:04:27 2007
5#
6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8CONFIG_GENERIC_GPIO=y
9CONFIG_GENERIC_TIME=y
10CONFIG_GENERIC_CLOCKEVENTS=y
11CONFIG_MMU=y
12# CONFIG_NO_IOPORT is not set
13CONFIG_GENERIC_HARDIRQS=y
14CONFIG_STACKTRACE_SUPPORT=y
15CONFIG_LOCKDEP_SUPPORT=y
16CONFIG_TRACE_IRQFLAGS_SUPPORT=y
17CONFIG_HARDIRQS_SW_RESEND=y
18CONFIG_GENERIC_IRQ_PROBE=y
19CONFIG_RWSEM_GENERIC_SPINLOCK=y
20# CONFIG_ARCH_HAS_ILOG2_U32 is not set
21# CONFIG_ARCH_HAS_ILOG2_U64 is not set
22CONFIG_GENERIC_HWEIGHT=y
23CONFIG_GENERIC_CALIBRATE_DELAY=y
24CONFIG_ZONE_DMA=y
25CONFIG_VECTORS_BASE=0xffff0000
26CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
27
28#
29# Code maturity level options
30#
31CONFIG_EXPERIMENTAL=y
32CONFIG_BROKEN_ON_SMP=y
33CONFIG_INIT_ENV_ARG_LIMIT=32
34
35#
36# General setup
37#
38CONFIG_LOCALVERSION=""
39CONFIG_LOCALVERSION_AUTO=y
40# CONFIG_SWAP is not set
41CONFIG_SYSVIPC=y
42# CONFIG_IPC_NS is not set
43CONFIG_SYSVIPC_SYSCTL=y
44CONFIG_BSD_PROCESS_ACCT=y
45# CONFIG_BSD_PROCESS_ACCT_V3 is not set
46# CONFIG_UTS_NS is not set
47# CONFIG_IKCONFIG is not set
48CONFIG_LOG_BUF_SHIFT=14
49CONFIG_SYSFS_DEPRECATED=y
50# CONFIG_RELAY is not set
51# CONFIG_BLK_DEV_INITRD is not set
52CONFIG_CC_OPTIMIZE_FOR_SIZE=y
53CONFIG_SYSCTL=y
54# CONFIG_EMBEDDED is not set
55CONFIG_UID16=y
56CONFIG_SYSCTL_SYSCALL=y
57CONFIG_KALLSYMS=y
58# CONFIG_KALLSYMS_EXTRA_PASS is not set
59CONFIG_HOTPLUG=y
60CONFIG_PRINTK=y
61CONFIG_BUG=y
62CONFIG_ELF_CORE=y
63CONFIG_BASE_FULL=y
64CONFIG_FUTEX=y
65CONFIG_ANON_INODES=y
66CONFIG_EPOLL=y
67CONFIG_SIGNALFD=y
68CONFIG_TIMERFD=y
69CONFIG_EVENTFD=y
70CONFIG_SHMEM=y
71CONFIG_VM_EVENT_COUNTERS=y
72CONFIG_SLAB=y
73# CONFIG_SLUB is not set
74# CONFIG_SLOB is not set
75CONFIG_RT_MUTEXES=y
76# CONFIG_TINY_SHMEM is not set
77CONFIG_BASE_SMALL=0
78
79#
80# Loadable module support
81#
82# CONFIG_MODULES is not set
83
84#
85# Block layer
86#
87CONFIG_BLOCK=y
88# CONFIG_LBD is not set
89# CONFIG_BLK_DEV_IO_TRACE is not set
90# CONFIG_LSF is not set
91
92#
93# IO Schedulers
94#
95CONFIG_IOSCHED_NOOP=y
96CONFIG_IOSCHED_AS=y
97# CONFIG_IOSCHED_DEADLINE is not set
98# CONFIG_IOSCHED_CFQ is not set
99CONFIG_DEFAULT_AS=y
100# CONFIG_DEFAULT_DEADLINE is not set
101# CONFIG_DEFAULT_CFQ is not set
102# CONFIG_DEFAULT_NOOP is not set
103CONFIG_DEFAULT_IOSCHED="anticipatory"
104
105#
106# System Type
107#
108# CONFIG_ARCH_AAEC2000 is not set
109# CONFIG_ARCH_INTEGRATOR is not set
110# CONFIG_ARCH_REALVIEW is not set
111# CONFIG_ARCH_VERSATILE is not set
112# CONFIG_ARCH_AT91 is not set
113# CONFIG_ARCH_CLPS7500 is not set
114# CONFIG_ARCH_CLPS711X is not set
115# CONFIG_ARCH_CO285 is not set
116# CONFIG_ARCH_EBSA110 is not set
117# CONFIG_ARCH_EP93XX is not set
118# CONFIG_ARCH_FOOTBRIDGE is not set
119# CONFIG_ARCH_NETX is not set
120# CONFIG_ARCH_H720X is not set
121# CONFIG_ARCH_IMX is not set
122# CONFIG_ARCH_IOP13XX is not set
123# CONFIG_ARCH_IOP32X is not set
124# CONFIG_ARCH_IOP33X is not set
125# CONFIG_ARCH_IXP23XX is not set
126# CONFIG_ARCH_IXP2000 is not set
127# CONFIG_ARCH_IXP4XX is not set
128# CONFIG_ARCH_L7200 is not set
129# CONFIG_ARCH_KS8695 is not set
130# CONFIG_ARCH_NS9XXX is not set
131# CONFIG_ARCH_PNX4008 is not set
132# CONFIG_ARCH_PXA is not set
133# CONFIG_ARCH_RPC is not set
134# CONFIG_ARCH_SA1100 is not set
135# CONFIG_ARCH_S3C2410 is not set
136# CONFIG_ARCH_SHARK is not set
137# CONFIG_ARCH_LH7A40X is not set
138# CONFIG_ARCH_DAVINCI is not set
139CONFIG_ARCH_OMAP=y
140
141#
142# TI OMAP Implementations
143#
144CONFIG_ARCH_OMAP1=y
145# CONFIG_ARCH_OMAP2 is not set
146
147#
148# OMAP Feature Selections
149#
150# CONFIG_OMAP_RESET_CLOCKS is not set
151# CONFIG_OMAP_BOOT_TAG is not set
152CONFIG_OMAP_GPIO_SWITCH=y
153CONFIG_OMAP_MUX=y
154# CONFIG_OMAP_MUX_DEBUG is not set
155CONFIG_OMAP_MUX_WARNINGS=y
156CONFIG_OMAP_MCBSP=y
157# CONFIG_OMAP_MMU_FWK is not set
158# CONFIG_OMAP_MBOX_FWK is not set
159CONFIG_OMAP_MPU_TIMER=y
160# CONFIG_OMAP_32K_TIMER is not set
161CONFIG_OMAP_LL_DEBUG_UART1=y
162# CONFIG_OMAP_LL_DEBUG_UART2 is not set
163# CONFIG_OMAP_LL_DEBUG_UART3 is not set
164CONFIG_OMAP_SERIAL_WAKE=y
165# CONFIG_OMAP_DSP is not set
166
167#
168# OMAP Core Type
169#
170# CONFIG_ARCH_OMAP730 is not set
171CONFIG_ARCH_OMAP15XX=y
172# CONFIG_ARCH_OMAP16XX is not set
173
174#
175# OMAP Board Type
176#
177# CONFIG_MACH_OMAP_INNOVATOR is not set
178# CONFIG_MACH_VOICEBLUE is not set
179CONFIG_MACH_OMAP_PALMTE=y
180# CONFIG_MACH_OMAP_PALMZ71 is not set
181# CONFIG_MACH_OMAP_PALMTT is not set
182# CONFIG_MACH_SX1 is not set
183# CONFIG_MACH_AMS_DELTA is not set
184# CONFIG_MACH_OMAP_GENERIC is not set
185
186#
187# OMAP CPU Speed
188#
189CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER=y
190# CONFIG_OMAP_ARM_168MHZ is not set
191# CONFIG_OMAP_ARM_150MHZ is not set
192# CONFIG_OMAP_ARM_120MHZ is not set
193# CONFIG_OMAP_ARM_60MHZ is not set
194# CONFIG_OMAP_ARM_30MHZ is not set
195
196#
197# Processor Type
198#
199CONFIG_CPU_32=y
200CONFIG_CPU_ARM925T=y
201CONFIG_CPU_32v4T=y
202CONFIG_CPU_ABRT_EV4T=y
203CONFIG_CPU_CACHE_V4WT=y
204CONFIG_CPU_CACHE_VIVT=y
205CONFIG_CPU_COPY_V4WB=y
206CONFIG_CPU_TLB_V4WBI=y
207CONFIG_CPU_CP15=y
208CONFIG_CPU_CP15_MMU=y
209
210#
211# Processor Features
212#
213# CONFIG_ARM_THUMB is not set
214# CONFIG_CPU_ICACHE_DISABLE is not set
215# CONFIG_CPU_DCACHE_DISABLE is not set
216# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
217# CONFIG_OUTER_CACHE is not set
218
219#
220# Bus support
221#
222# CONFIG_ARCH_SUPPORTS_MSI is not set
223
224#
225# PCCARD (PCMCIA/CardBus) support
226#
227# CONFIG_PCCARD is not set
228
229#
230# Kernel Features
231#
232# CONFIG_TICK_ONESHOT is not set
233# CONFIG_NO_HZ is not set
234# CONFIG_HIGH_RES_TIMERS is not set
235# CONFIG_PREEMPT is not set
236CONFIG_HZ=100
237# CONFIG_AEABI is not set
238# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
239CONFIG_SELECT_MEMORY_MODEL=y
240CONFIG_FLATMEM_MANUAL=y
241# CONFIG_DISCONTIGMEM_MANUAL is not set
242# CONFIG_SPARSEMEM_MANUAL is not set
243CONFIG_FLATMEM=y
244CONFIG_FLAT_NODE_MEM_MAP=y
245# CONFIG_SPARSEMEM_STATIC is not set
246CONFIG_SPLIT_PTLOCK_CPUS=4096
247# CONFIG_RESOURCES_64BIT is not set
248CONFIG_ZONE_DMA_FLAG=1
249# CONFIG_LEDS is not set
250CONFIG_ALIGNMENT_TRAP=y
251
252#
253# Boot options
254#
255CONFIG_ZBOOT_ROM_TEXT=0x0
256CONFIG_ZBOOT_ROM_BSS=0x0
257CONFIG_CMDLINE=""
258# CONFIG_XIP_KERNEL is not set
259# CONFIG_KEXEC is not set
260
261#
262# CPU Frequency scaling
263#
264# CONFIG_CPU_FREQ is not set
265
266#
267# Floating point emulation
268#
269
270#
271# At least one emulation must be selected
272#
273CONFIG_FPE_NWFPE=y
274# CONFIG_FPE_NWFPE_XP is not set
275# CONFIG_FPE_FASTFPE is not set
276
277#
278# Userspace binary formats
279#
280CONFIG_BINFMT_ELF=y
281# CONFIG_BINFMT_AOUT is not set
282# CONFIG_BINFMT_MISC is not set
283# CONFIG_ARTHUR is not set
284
285#
286# Power management options
287#
288# CONFIG_PM is not set
289
290#
291# Networking
292#
293# CONFIG_NET is not set
294
295#
296# Device Drivers
297#
298
299#
300# Generic Driver Options
301#
302# CONFIG_STANDALONE is not set
303# CONFIG_PREVENT_FIRMWARE_BUILD is not set
304# CONFIG_FW_LOADER is not set
305# CONFIG_SYS_HYPERVISOR is not set
306
307#
308# Connector - unified userspace <-> kernelspace linker
309#
310# CONFIG_MTD is not set
311
312#
313# Parallel port support
314#
315# CONFIG_PARPORT is not set
316
317#
318# Plug and Play support
319#
320# CONFIG_PNPACPI is not set
321
322#
323# Block devices
324#
325# CONFIG_BLK_DEV_COW_COMMON is not set
326# CONFIG_BLK_DEV_LOOP is not set
327# CONFIG_BLK_DEV_RAM is not set
328# CONFIG_CDROM_PKTCDVD is not set
329
330#
331# SCSI device support
332#
333# CONFIG_RAID_ATTRS is not set
334# CONFIG_SCSI is not set
335# CONFIG_SCSI_NETLINK is not set
336# CONFIG_ATA is not set
337
338#
339# Multi-device support (RAID and LVM)
340#
341# CONFIG_MD is not set
342
343#
344# ISDN subsystem
345#
346
347#
348# Input device support
349#
350CONFIG_INPUT=y
351# CONFIG_INPUT_FF_MEMLESS is not set
352
353#
354# Userland interfaces
355#
356CONFIG_INPUT_MOUSEDEV=y
357# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
358CONFIG_INPUT_MOUSEDEV_SCREEN_X=320
359CONFIG_INPUT_MOUSEDEV_SCREEN_Y=320
360# CONFIG_INPUT_JOYDEV is not set
361# CONFIG_INPUT_TSDEV is not set
362# CONFIG_INPUT_EVDEV is not set
363# CONFIG_INPUT_EVBUG is not set
364
365#
366# Input Device Drivers
367#
368# CONFIG_INPUT_KEYBOARD is not set
369# CONFIG_INPUT_MOUSE is not set
370# CONFIG_INPUT_JOYSTICK is not set
371# CONFIG_INPUT_TABLET is not set
372# CONFIG_INPUT_TOUCHSCREEN is not set
373# CONFIG_INPUT_MISC is not set
374
375#
376# Hardware I/O ports
377#
378# CONFIG_SERIO is not set
379# CONFIG_GAMEPORT is not set
380
381#
382# Character devices
383#
384CONFIG_VT=y
385CONFIG_VT_CONSOLE=y
386CONFIG_HW_CONSOLE=y
387# CONFIG_VT_HW_CONSOLE_BINDING is not set
388# CONFIG_SERIAL_NONSTANDARD is not set
389
390#
391# Serial drivers
392#
393# CONFIG_SERIAL_8250 is not set
394
395#
396# Non-8250 serial port support
397#
398CONFIG_UNIX98_PTYS=y
399# CONFIG_LEGACY_PTYS is not set
400
401#
402# IPMI
403#
404# CONFIG_IPMI_HANDLER is not set
405# CONFIG_WATCHDOG is not set
406CONFIG_HW_RANDOM=y
407# CONFIG_NVRAM is not set
408CONFIG_OMAP_RTC=y
409# CONFIG_R3964 is not set
410# CONFIG_RAW_DRIVER is not set
411
412#
413# TPM devices
414#
415# CONFIG_TCG_TPM is not set
416# CONFIG_I2C is not set
417
418#
419# SPI support
420#
421# CONFIG_SPI is not set
422# CONFIG_SPI_MASTER is not set
423
424#
425# Dallas's 1-wire bus
426#
427# CONFIG_W1 is not set
428# CONFIG_HWMON is not set
429
430#
431# Misc devices
432#
433# CONFIG_BLINK is not set
434
435#
436# Multifunction device drivers
437#
438# CONFIG_MFD_SM501 is not set
439
440#
441# LED devices
442#
443# CONFIG_NEW_LEDS is not set
444
445#
446# LED drivers
447#
448
449#
450# LED Triggers
451#
452
453#
454# Multimedia devices
455#
456# CONFIG_VIDEO_DEV is not set
457CONFIG_DAB=y
458
459#
460# Graphics support
461#
462# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
463
464#
465# Display device support
466#
467# CONFIG_DISPLAY_SUPPORT is not set
468# CONFIG_VGASTATE is not set
469CONFIG_FB=y
470# CONFIG_FIRMWARE_EDID is not set
471# CONFIG_FB_DDC is not set
472# CONFIG_FB_CFB_FILLRECT is not set
473# CONFIG_FB_CFB_COPYAREA is not set
474# CONFIG_FB_CFB_IMAGEBLIT is not set
475# CONFIG_FB_SYS_FILLRECT is not set
476# CONFIG_FB_SYS_COPYAREA is not set
477# CONFIG_FB_SYS_IMAGEBLIT is not set
478# CONFIG_FB_SYS_FOPS is not set
479CONFIG_FB_DEFERRED_IO=y
480# CONFIG_FB_SVGALIB is not set
481# CONFIG_FB_MACMODES is not set
482# CONFIG_FB_BACKLIGHT is not set
483# CONFIG_FB_MODE_HELPERS is not set
484# CONFIG_FB_TILEBLITTING is not set
485
486#
487# Frame buffer hardware drivers
488#
489# CONFIG_FB_S1D13XXX is not set
490CONFIG_FB_OMAP=y
491# CONFIG_FB_OMAP_LCDC_EXTERNAL is not set
492# CONFIG_FB_OMAP_LCD_MIPID is not set
493# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set
494CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=2
495# CONFIG_FB_OMAP_DMA_TUNE is not set
496# CONFIG_FB_VIRTUAL is not set
497
498#
499# Console display driver support
500#
501# CONFIG_VGA_CONSOLE is not set
502CONFIG_DUMMY_CONSOLE=y
503CONFIG_FRAMEBUFFER_CONSOLE=y
504# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
505# CONFIG_FONTS is not set
506CONFIG_FONT_8x8=y
507CONFIG_FONT_8x16=y
508CONFIG_LOGO=y
509# CONFIG_LOGO_LINUX_MONO is not set
510# CONFIG_LOGO_LINUX_VGA16 is not set
511CONFIG_LOGO_LINUX_CLUT224=y
512
513#
514# Sound
515#
516# CONFIG_SOUND is not set
517
518#
519# HID Devices
520#
521CONFIG_HID=y
522# CONFIG_HID_DEBUG is not set
523
524#
525# USB support
526#
527CONFIG_USB_ARCH_HAS_HCD=y
528CONFIG_USB_ARCH_HAS_OHCI=y
529# CONFIG_USB_ARCH_HAS_EHCI is not set
530# CONFIG_USB is not set
531# CONFIG_USB_MUSB_HDRC is not set
532# CONFIG_USB_GADGET_MUSB_HDRC is not set
533
534#
535# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
536#
537
538#
539# USB Gadget Support
540#
541CONFIG_USB_GADGET=y
542# CONFIG_USB_GADGET_DEBUG_FILES is not set
543CONFIG_USB_GADGET_SELECTED=y
544# CONFIG_USB_GADGET_FSL_USB2 is not set
545# CONFIG_USB_GADGET_NET2280 is not set
546# CONFIG_USB_GADGET_PXA2XX is not set
547# CONFIG_USB_GADGET_GOKU is not set
548# CONFIG_USB_GADGET_LH7A40X is not set
549CONFIG_USB_GADGET_OMAP=y
550CONFIG_USB_OMAP=y
551# CONFIG_USB_GADGET_AT91 is not set
552# CONFIG_USB_GADGET_DUMMY_HCD is not set
553# CONFIG_USB_GADGET_DUALSPEED is not set
554CONFIG_USB_ZERO=y
555# CONFIG_USB_ETH is not set
556# CONFIG_USB_GADGETFS is not set
557# CONFIG_USB_FILE_STORAGE is not set
558# CONFIG_USB_G_SERIAL is not set
559# CONFIG_USB_MIDI_GADGET is not set
560CONFIG_MMC=y
561# CONFIG_MMC_DEBUG is not set
562# CONFIG_MMC_UNSAFE_RESUME is not set
563
564#
565# MMC/SD Card Drivers
566#
567CONFIG_MMC_BLOCK=y
568
569#
570# MMC/SD Host Controller Drivers
571#
572CONFIG_MMC_OMAP=y
573
574#
575# Real Time Clock
576#
577CONFIG_RTC_LIB=y
578# CONFIG_RTC_CLASS is not set
579
580#
581# CBUS support
582#
583# CONFIG_CBUS is not set
584
585#
586# File systems
587#
588CONFIG_EXT2_FS=y
589# CONFIG_EXT2_FS_XATTR is not set
590# CONFIG_EXT2_FS_XIP is not set
591# CONFIG_EXT3_FS is not set
592# CONFIG_EXT4DEV_FS is not set
593# CONFIG_REISERFS_FS is not set
594# CONFIG_JFS_FS is not set
595# CONFIG_FS_POSIX_ACL is not set
596# CONFIG_XFS_FS is not set
597# CONFIG_GFS2_FS is not set
598# CONFIG_MINIX_FS is not set
599# CONFIG_ROMFS_FS is not set
600# CONFIG_INOTIFY is not set
601# CONFIG_QUOTA is not set
602CONFIG_DNOTIFY=y
603# CONFIG_AUTOFS_FS is not set
604# CONFIG_AUTOFS4_FS is not set
605# CONFIG_FUSE_FS is not set
606
607#
608# CD-ROM/DVD Filesystems
609#
610# CONFIG_ISO9660_FS is not set
611# CONFIG_UDF_FS is not set
612
613#
614# DOS/FAT/NT Filesystems
615#
616CONFIG_FAT_FS=y
617CONFIG_MSDOS_FS=y
618CONFIG_VFAT_FS=y
619CONFIG_FAT_DEFAULT_CODEPAGE=850
620CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
621# CONFIG_NTFS_FS is not set
622
623#
624# Pseudo filesystems
625#
626CONFIG_PROC_FS=y
627CONFIG_PROC_SYSCTL=y
628CONFIG_SYSFS=y
629CONFIG_TMPFS=y
630# CONFIG_TMPFS_POSIX_ACL is not set
631# CONFIG_HUGETLB_PAGE is not set
632CONFIG_RAMFS=y
633# CONFIG_CONFIGFS_FS is not set
634
635#
636# Miscellaneous filesystems
637#
638# CONFIG_ADFS_FS is not set
639# CONFIG_AFFS_FS is not set
640# CONFIG_HFS_FS is not set
641# CONFIG_HFSPLUS_FS is not set
642# CONFIG_BEFS_FS is not set
643# CONFIG_BFS_FS is not set
644# CONFIG_EFS_FS is not set
645CONFIG_CRAMFS=y
646# CONFIG_VXFS_FS is not set
647# CONFIG_HPFS_FS is not set
648# CONFIG_QNX4FS_FS is not set
649# CONFIG_SYSV_FS is not set
650# CONFIG_UFS_FS is not set
651
652#
653# Partition Types
654#
655CONFIG_PARTITION_ADVANCED=y
656# CONFIG_ACORN_PARTITION is not set
657# CONFIG_OSF_PARTITION is not set
658# CONFIG_AMIGA_PARTITION is not set
659# CONFIG_ATARI_PARTITION is not set
660# CONFIG_MAC_PARTITION is not set
661CONFIG_MSDOS_PARTITION=y
662# CONFIG_BSD_DISKLABEL is not set
663# CONFIG_MINIX_SUBPARTITION is not set
664# CONFIG_SOLARIS_X86_PARTITION is not set
665# CONFIG_UNIXWARE_DISKLABEL is not set
666# CONFIG_LDM_PARTITION is not set
667# CONFIG_SGI_PARTITION is not set
668# CONFIG_ULTRIX_PARTITION is not set
669# CONFIG_SUN_PARTITION is not set
670# CONFIG_KARMA_PARTITION is not set
671# CONFIG_EFI_PARTITION is not set
672# CONFIG_SYSV68_PARTITION is not set
673
674#
675# Native Language Support
676#
677CONFIG_NLS=y
678CONFIG_NLS_DEFAULT="iso8859-1"
679# CONFIG_NLS_CODEPAGE_437 is not set
680# CONFIG_NLS_CODEPAGE_737 is not set
681# CONFIG_NLS_CODEPAGE_775 is not set
682CONFIG_NLS_CODEPAGE_850=y
683# CONFIG_NLS_CODEPAGE_852 is not set
684# CONFIG_NLS_CODEPAGE_855 is not set
685# CONFIG_NLS_CODEPAGE_857 is not set
686# CONFIG_NLS_CODEPAGE_860 is not set
687# CONFIG_NLS_CODEPAGE_861 is not set
688# CONFIG_NLS_CODEPAGE_862 is not set
689# CONFIG_NLS_CODEPAGE_863 is not set
690# CONFIG_NLS_CODEPAGE_864 is not set
691# CONFIG_NLS_CODEPAGE_865 is not set
692# CONFIG_NLS_CODEPAGE_866 is not set
693# CONFIG_NLS_CODEPAGE_869 is not set
694# CONFIG_NLS_CODEPAGE_936 is not set
695# CONFIG_NLS_CODEPAGE_950 is not set
696# CONFIG_NLS_CODEPAGE_932 is not set
697# CONFIG_NLS_CODEPAGE_949 is not set
698# CONFIG_NLS_CODEPAGE_874 is not set
699# CONFIG_NLS_ISO8859_8 is not set
700# CONFIG_NLS_CODEPAGE_1250 is not set
701# CONFIG_NLS_CODEPAGE_1251 is not set
702# CONFIG_NLS_ASCII is not set
703CONFIG_NLS_ISO8859_1=y
704# CONFIG_NLS_ISO8859_2 is not set
705# CONFIG_NLS_ISO8859_3 is not set
706# CONFIG_NLS_ISO8859_4 is not set
707# CONFIG_NLS_ISO8859_5 is not set
708# CONFIG_NLS_ISO8859_6 is not set
709# CONFIG_NLS_ISO8859_7 is not set
710# CONFIG_NLS_ISO8859_9 is not set
711# CONFIG_NLS_ISO8859_13 is not set
712# CONFIG_NLS_ISO8859_14 is not set
713# CONFIG_NLS_ISO8859_15 is not set
714# CONFIG_NLS_KOI8_R is not set
715# CONFIG_NLS_KOI8_U is not set
716# CONFIG_NLS_UTF8 is not set
717
718#
719# Profiling support
720#
721# CONFIG_PROFILING is not set
722
723#
724# Kernel hacking
725#
726# CONFIG_PRINTK_TIME is not set
727CONFIG_ENABLE_MUST_CHECK=y
728# CONFIG_MAGIC_SYSRQ is not set
729# CONFIG_UNUSED_SYMBOLS is not set
730# CONFIG_DEBUG_FS is not set
731# CONFIG_HEADERS_CHECK is not set
732# CONFIG_DEBUG_KERNEL is not set
733CONFIG_DEBUG_BUGVERBOSE=y
734CONFIG_FRAME_POINTER=y
735# CONFIG_DEBUG_USER is not set
736
737#
738# Security options
739#
740# CONFIG_KEYS is not set
741# CONFIG_SECURITY is not set
742
743#
744# Cryptographic options
745#
746# CONFIG_CRYPTO is not set
747
748#
749# Library routines
750#
751CONFIG_BITREVERSE=y
752CONFIG_CRC_CCITT=y
753# CONFIG_CRC16 is not set
754# CONFIG_CRC_ITU_T is not set
755CONFIG_CRC32=y
756# CONFIG_LIBCRC32C is not set
757CONFIG_ZLIB_INFLATE=y
758CONFIG_PLIST=y
759CONFIG_HAS_IOMEM=y
760CONFIG_HAS_IOPORT=y
761CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/palmtt_defconfig b/arch/arm/configs/palmtt_defconfig
new file mode 100644
index 000000000000..e54ced41217e
--- /dev/null
+++ b/arch/arm/configs/palmtt_defconfig
@@ -0,0 +1,844 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.19-rc3-omap1
4# Sun Oct 29 00:36:12 2006
5#
6CONFIG_ARM=y
7# CONFIG_GENERIC_TIME is not set
8CONFIG_MMU=y
9CONFIG_GENERIC_HARDIRQS=y
10CONFIG_TRACE_IRQFLAGS_SUPPORT=y
11CONFIG_HARDIRQS_SW_RESEND=y
12CONFIG_GENERIC_IRQ_PROBE=y
13CONFIG_RWSEM_GENERIC_SPINLOCK=y
14CONFIG_GENERIC_HWEIGHT=y
15CONFIG_GENERIC_CALIBRATE_DELAY=y
16CONFIG_VECTORS_BASE=0xffff0000
17CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
18
19#
20# Code maturity level options
21#
22CONFIG_EXPERIMENTAL=y
23CONFIG_BROKEN_ON_SMP=y
24CONFIG_INIT_ENV_ARG_LIMIT=32
25
26#
27# General setup
28#
29CONFIG_LOCALVERSION=""
30CONFIG_LOCALVERSION_AUTO=y
31CONFIG_SWAP=y
32CONFIG_SYSVIPC=y
33# CONFIG_IPC_NS is not set
34# CONFIG_POSIX_MQUEUE is not set
35CONFIG_BSD_PROCESS_ACCT=y
36# CONFIG_BSD_PROCESS_ACCT_V3 is not set
37# CONFIG_TASKSTATS is not set
38# CONFIG_UTS_NS is not set
39# CONFIG_AUDIT is not set
40# CONFIG_IKCONFIG is not set
41# CONFIG_RELAY is not set
42CONFIG_INITRAMFS_SOURCE=""
43CONFIG_CC_OPTIMIZE_FOR_SIZE=y
44CONFIG_SYSCTL=y
45# CONFIG_EMBEDDED is not set
46CONFIG_UID16=y
47# CONFIG_SYSCTL_SYSCALL is not set
48CONFIG_KALLSYMS=y
49# CONFIG_KALLSYMS_EXTRA_PASS is not set
50CONFIG_HOTPLUG=y
51CONFIG_PRINTK=y
52CONFIG_BUG=y
53CONFIG_ELF_CORE=y
54CONFIG_BASE_FULL=y
55CONFIG_FUTEX=y
56CONFIG_EPOLL=y
57CONFIG_SHMEM=y
58CONFIG_SLAB=y
59CONFIG_VM_EVENT_COUNTERS=y
60CONFIG_RT_MUTEXES=y
61# CONFIG_TINY_SHMEM is not set
62CONFIG_BASE_SMALL=0
63# CONFIG_SLOB is not set
64
65#
66# Loadable module support
67#
68# CONFIG_MODULES is not set
69
70#
71# Block layer
72#
73CONFIG_BLOCK=y
74# CONFIG_BLK_DEV_IO_TRACE is not set
75
76#
77# IO Schedulers
78#
79CONFIG_IOSCHED_NOOP=y
80# CONFIG_IOSCHED_AS is not set
81# CONFIG_IOSCHED_DEADLINE is not set
82# CONFIG_IOSCHED_CFQ is not set
83# CONFIG_DEFAULT_AS is not set
84# CONFIG_DEFAULT_DEADLINE is not set
85# CONFIG_DEFAULT_CFQ is not set
86CONFIG_DEFAULT_NOOP=y
87CONFIG_DEFAULT_IOSCHED="noop"
88
89#
90# System Type
91#
92# CONFIG_ARCH_AAEC2000 is not set
93# CONFIG_ARCH_INTEGRATOR is not set
94# CONFIG_ARCH_REALVIEW is not set
95# CONFIG_ARCH_VERSATILE is not set
96# CONFIG_ARCH_AT91 is not set
97# CONFIG_ARCH_CLPS7500 is not set
98# CONFIG_ARCH_CLPS711X is not set
99# CONFIG_ARCH_CO285 is not set
100# CONFIG_ARCH_EBSA110 is not set
101# CONFIG_ARCH_EP93XX is not set
102# CONFIG_ARCH_FOOTBRIDGE is not set
103# CONFIG_ARCH_NETX is not set
104# CONFIG_ARCH_H720X is not set
105# CONFIG_ARCH_IMX is not set
106# CONFIG_ARCH_IOP32X is not set
107# CONFIG_ARCH_IOP33X is not set
108# CONFIG_ARCH_IXP4XX is not set
109# CONFIG_ARCH_IXP2000 is not set
110# CONFIG_ARCH_IXP23XX is not set
111# CONFIG_ARCH_L7200 is not set
112# CONFIG_ARCH_PNX4008 is not set
113# CONFIG_ARCH_PXA is not set
114# CONFIG_ARCH_RPC is not set
115# CONFIG_ARCH_SA1100 is not set
116# CONFIG_ARCH_S3C2410 is not set
117# CONFIG_ARCH_SHARK is not set
118# CONFIG_ARCH_LH7A40X is not set
119CONFIG_ARCH_OMAP=y
120
121#
122# TI OMAP Implementations
123#
124CONFIG_ARCH_OMAP1=y
125# CONFIG_ARCH_OMAP2 is not set
126
127#
128# OMAP Feature Selections
129#
130# CONFIG_OMAP_RESET_CLOCKS is not set
131# CONFIG_OMAP_BOOT_TAG is not set
132# CONFIG_OMAP_GPIO_SWITCH is not set
133CONFIG_OMAP_MUX=y
134# CONFIG_OMAP_MUX_DEBUG is not set
135CONFIG_OMAP_MUX_WARNINGS=y
136CONFIG_OMAP_MCBSP=y
137CONFIG_OMAP_MPU_TIMER=y
138# CONFIG_OMAP_32K_TIMER is not set
139# CONFIG_OMAP_LL_DEBUG_UART1 is not set
140CONFIG_OMAP_LL_DEBUG_UART2=y
141# CONFIG_OMAP_LL_DEBUG_UART3 is not set
142CONFIG_OMAP_SERIAL_WAKE=y
143CONFIG_OMAP_DSP=y
144# CONFIG_OMAP_DSP_MBCMD_VERBOSE is not set
145# CONFIG_OMAP_DSP_TASK_MULTIOPEN is not set
146CONFIG_OMAP_DSP_FBEXPORT=y
147
148#
149# OMAP Core Type
150#
151# CONFIG_ARCH_OMAP730 is not set
152CONFIG_ARCH_OMAP15XX=y
153# CONFIG_ARCH_OMAP16XX is not set
154
155#
156# OMAP Board Type
157#
158# CONFIG_MACH_OMAP_INNOVATOR is not set
159# CONFIG_MACH_VOICEBLUE is not set
160# CONFIG_MACH_OMAP_PALMTE is not set
161# CONFIG_MACH_OMAP_PALMZ71 is not set
162CONFIG_MACH_OMAP_PALMTT=y
163# CONFIG_MACH_AMS_DELTA is not set
164# CONFIG_MACH_OMAP_GENERIC is not set
165
166#
167# OMAP CPU Speed
168#
169CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER=y
170# CONFIG_OMAP_ARM_168MHZ is not set
171# CONFIG_OMAP_ARM_150MHZ is not set
172# CONFIG_OMAP_ARM_120MHZ is not set
173# CONFIG_OMAP_ARM_60MHZ is not set
174# CONFIG_OMAP_ARM_30MHZ is not set
175
176#
177# Processor Type
178#
179CONFIG_CPU_32=y
180CONFIG_CPU_ARM925T=y
181CONFIG_CPU_32v4T=y
182CONFIG_CPU_ABRT_EV4T=y
183CONFIG_CPU_CACHE_V4WT=y
184CONFIG_CPU_CACHE_VIVT=y
185CONFIG_CPU_COPY_V4WB=y
186CONFIG_CPU_TLB_V4WBI=y
187CONFIG_CPU_CP15=y
188CONFIG_CPU_CP15_MMU=y
189
190#
191# Processor Features
192#
193CONFIG_ARM_THUMB=y
194# CONFIG_CPU_ICACHE_DISABLE is not set
195# CONFIG_CPU_DCACHE_DISABLE is not set
196# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
197
198#
199# Bus support
200#
201
202#
203# PCCARD (PCMCIA/CardBus) support
204#
205# CONFIG_PCCARD is not set
206
207#
208# Kernel Features
209#
210# CONFIG_PREEMPT is not set
211# CONFIG_NO_IDLE_HZ is not set
212CONFIG_HZ=100
213# CONFIG_AEABI is not set
214# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
215CONFIG_SELECT_MEMORY_MODEL=y
216CONFIG_FLATMEM_MANUAL=y
217# CONFIG_DISCONTIGMEM_MANUAL is not set
218# CONFIG_SPARSEMEM_MANUAL is not set
219CONFIG_FLATMEM=y
220CONFIG_FLAT_NODE_MEM_MAP=y
221# CONFIG_SPARSEMEM_STATIC is not set
222CONFIG_SPLIT_PTLOCK_CPUS=4096
223# CONFIG_RESOURCES_64BIT is not set
224# CONFIG_LEDS is not set
225CONFIG_ALIGNMENT_TRAP=y
226
227#
228# Boot options
229#
230CONFIG_ZBOOT_ROM_TEXT=0x0
231CONFIG_ZBOOT_ROM_BSS=0x0
232CONFIG_CMDLINE="root=/dev/mmcblk0p2 rw init=/init"
233# CONFIG_XIP_KERNEL is not set
234
235#
236# CPU Frequency scaling
237#
238# CONFIG_CPU_FREQ is not set
239
240#
241# Floating point emulation
242#
243
244#
245# At least one emulation must be selected
246#
247CONFIG_FPE_NWFPE=y
248# CONFIG_FPE_NWFPE_XP is not set
249# CONFIG_FPE_FASTFPE is not set
250
251#
252# Userspace binary formats
253#
254CONFIG_BINFMT_ELF=y
255# CONFIG_BINFMT_AOUT is not set
256# CONFIG_BINFMT_MISC is not set
257# CONFIG_ARTHUR is not set
258
259#
260# Power management options
261#
262# CONFIG_PM is not set
263# CONFIG_APM is not set
264
265#
266# Networking
267#
268CONFIG_NET=y
269
270#
271# Networking options
272#
273# CONFIG_NETDEBUG is not set
274CONFIG_PACKET=y
275# CONFIG_PACKET_MMAP is not set
276CONFIG_UNIX=y
277CONFIG_XFRM=y
278# CONFIG_XFRM_USER is not set
279# CONFIG_XFRM_SUB_POLICY is not set
280CONFIG_NET_KEY=y
281CONFIG_INET=y
282# CONFIG_IP_MULTICAST is not set
283# CONFIG_IP_ADVANCED_ROUTER is not set
284CONFIG_IP_FIB_HASH=y
285# CONFIG_IP_PNP is not set
286# CONFIG_NET_IPIP is not set
287# CONFIG_NET_IPGRE is not set
288# CONFIG_ARPD is not set
289# CONFIG_SYN_COOKIES is not set
290# CONFIG_INET_AH is not set
291# CONFIG_INET_ESP is not set
292# CONFIG_INET_IPCOMP is not set
293# CONFIG_INET_XFRM_TUNNEL is not set
294# CONFIG_INET_TUNNEL is not set
295# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
296# CONFIG_INET_XFRM_MODE_TUNNEL is not set
297# CONFIG_INET_XFRM_MODE_BEET is not set
298# CONFIG_INET_DIAG is not set
299# CONFIG_TCP_CONG_ADVANCED is not set
300CONFIG_TCP_CONG_CUBIC=y
301CONFIG_DEFAULT_TCP_CONG="cubic"
302# CONFIG_IPV6 is not set
303# CONFIG_INET6_XFRM_TUNNEL is not set
304# CONFIG_INET6_TUNNEL is not set
305# CONFIG_NETWORK_SECMARK is not set
306# CONFIG_NETFILTER is not set
307
308#
309# DCCP Configuration (EXPERIMENTAL)
310#
311# CONFIG_IP_DCCP is not set
312
313#
314# SCTP Configuration (EXPERIMENTAL)
315#
316# CONFIG_IP_SCTP is not set
317
318#
319# TIPC Configuration (EXPERIMENTAL)
320#
321# CONFIG_TIPC is not set
322# CONFIG_ATM is not set
323# CONFIG_BRIDGE is not set
324# CONFIG_VLAN_8021Q is not set
325# CONFIG_DECNET is not set
326# CONFIG_LLC2 is not set
327# CONFIG_IPX is not set
328# CONFIG_ATALK is not set
329# CONFIG_X25 is not set
330# CONFIG_LAPB is not set
331# CONFIG_ECONET is not set
332# CONFIG_WAN_ROUTER is not set
333
334#
335# QoS and/or fair queueing
336#
337# CONFIG_NET_SCHED is not set
338
339#
340# Network testing
341#
342# CONFIG_NET_PKTGEN is not set
343# CONFIG_HAMRADIO is not set
344# CONFIG_IRDA is not set
345# CONFIG_BT is not set
346# CONFIG_IEEE80211 is not set
347
348#
349# Device Drivers
350#
351
352#
353# Generic Driver Options
354#
355CONFIG_STANDALONE=y
356CONFIG_PREVENT_FIRMWARE_BUILD=y
357# CONFIG_FW_LOADER is not set
358# CONFIG_SYS_HYPERVISOR is not set
359
360#
361# Connector - unified userspace <-> kernelspace linker
362#
363# CONFIG_CONNECTOR is not set
364
365#
366# Memory Technology Devices (MTD)
367#
368# CONFIG_MTD is not set
369
370#
371# Parallel port support
372#
373# CONFIG_PARPORT is not set
374
375#
376# Plug and Play support
377#
378
379#
380# Block devices
381#
382# CONFIG_BLK_DEV_COW_COMMON is not set
383# CONFIG_BLK_DEV_LOOP is not set
384# CONFIG_BLK_DEV_NBD is not set
385# CONFIG_BLK_DEV_RAM is not set
386# CONFIG_BLK_DEV_INITRD is not set
387# CONFIG_CDROM_PKTCDVD is not set
388# CONFIG_ATA_OVER_ETH is not set
389
390#
391# SCSI device support
392#
393# CONFIG_RAID_ATTRS is not set
394# CONFIG_SCSI is not set
395# CONFIG_SCSI_NETLINK is not set
396
397#
398# Multi-device support (RAID and LVM)
399#
400# CONFIG_MD is not set
401
402#
403# Fusion MPT device support
404#
405# CONFIG_FUSION is not set
406
407#
408# IEEE 1394 (FireWire) support
409#
410
411#
412# I2O device support
413#
414
415#
416# Network device support
417#
418# CONFIG_NETDEVICES is not set
419# CONFIG_NETPOLL is not set
420# CONFIG_NET_POLL_CONTROLLER is not set
421
422#
423# ISDN subsystem
424#
425# CONFIG_ISDN is not set
426
427#
428# Input device support
429#
430CONFIG_INPUT=y
431# CONFIG_INPUT_FF_MEMLESS is not set
432
433#
434# Userland interfaces
435#
436CONFIG_INPUT_MOUSEDEV=y
437CONFIG_INPUT_MOUSEDEV_PSAUX=y
438CONFIG_INPUT_MOUSEDEV_SCREEN_X=320
439CONFIG_INPUT_MOUSEDEV_SCREEN_Y=320
440# CONFIG_INPUT_JOYDEV is not set
441CONFIG_INPUT_TSDEV=y
442CONFIG_INPUT_TSDEV_SCREEN_X=320
443CONFIG_INPUT_TSDEV_SCREEN_Y=320
444CONFIG_INPUT_EVDEV=y
445# CONFIG_INPUT_EVBUG is not set
446
447#
448# Input Device Drivers
449#
450# CONFIG_INPUT_KEYBOARD is not set
451# CONFIG_INPUT_MOUSE is not set
452# CONFIG_INPUT_JOYSTICK is not set
453CONFIG_INPUT_TOUCHSCREEN=y
454CONFIG_TOUCHSCREEN_ADS7846=y
455# CONFIG_TOUCHSCREEN_GUNZE is not set
456# CONFIG_TOUCHSCREEN_ELO is not set
457# CONFIG_TOUCHSCREEN_MTOUCH is not set
458# CONFIG_TOUCHSCREEN_MK712 is not set
459# CONFIG_TOUCHSCREEN_PENMOUNT is not set
460# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
461# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
462# CONFIG_TOUCHSCREEN_TSC2102 is not set
463# CONFIG_INPUT_MISC is not set
464
465#
466# Hardware I/O ports
467#
468# CONFIG_SERIO is not set
469# CONFIG_GAMEPORT is not set
470
471#
472# Character devices
473#
474CONFIG_VT=y
475CONFIG_VT_CONSOLE=y
476CONFIG_HW_CONSOLE=y
477# CONFIG_VT_HW_CONSOLE_BINDING is not set
478# CONFIG_SERIAL_NONSTANDARD is not set
479
480#
481# Serial drivers
482#
483# CONFIG_SERIAL_8250 is not set
484
485#
486# Non-8250 serial port support
487#
488CONFIG_UNIX98_PTYS=y
489CONFIG_LEGACY_PTYS=y
490CONFIG_LEGACY_PTY_COUNT=256
491
492#
493# IPMI
494#
495# CONFIG_IPMI_HANDLER is not set
496
497#
498# Watchdog Cards
499#
500# CONFIG_WATCHDOG is not set
501CONFIG_HW_RANDOM=y
502# CONFIG_NVRAM is not set
503# CONFIG_OMAP_RTC is not set
504# CONFIG_DTLK is not set
505# CONFIG_R3964 is not set
506
507#
508# Ftape, the floppy tape device driver
509#
510# CONFIG_RAW_DRIVER is not set
511
512#
513# TPM devices
514#
515# CONFIG_TCG_TPM is not set
516
517#
518# I2C support
519#
520# CONFIG_I2C is not set
521
522#
523# SPI support
524#
525CONFIG_SPI=y
526CONFIG_SPI_MASTER=y
527
528#
529# SPI Master Controller Drivers
530#
531CONFIG_SPI_BITBANG=y
532CONFIG_SPI_OMAP_UWIRE=y
533
534#
535# SPI Protocol Masters
536#
537# CONFIG_TSC2102 is not set
538
539#
540# Dallas's 1-wire bus
541#
542# CONFIG_W1 is not set
543
544#
545# Hardware Monitoring support
546#
547CONFIG_HWMON=y
548# CONFIG_HWMON_VID is not set
549# CONFIG_SENSORS_ABITUGURU is not set
550# CONFIG_SENSORS_F71805F is not set
551# CONFIG_SENSORS_LM70 is not set
552# CONFIG_SENSORS_VT1211 is not set
553# CONFIG_HWMON_DEBUG_CHIP is not set
554
555#
556# Misc devices
557#
558# CONFIG_SGI_IOC4 is not set
559# CONFIG_TIFM_CORE is not set
560
561#
562# LED devices
563#
564CONFIG_NEW_LEDS=y
565CONFIG_LEDS_CLASS=y
566
567#
568# LED drivers
569#
570CONFIG_LEDS_OMAP=y
571
572#
573# LED Triggers
574#
575CONFIG_LEDS_TRIGGERS=y
576CONFIG_LEDS_TRIGGER_TIMER=y
577CONFIG_LEDS_TRIGGER_HEARTBEAT=y
578
579#
580# Multimedia devices
581#
582# CONFIG_VIDEO_DEV is not set
583
584#
585# Digital Video Broadcasting Devices
586#
587# CONFIG_DVB is not set
588
589#
590# Graphics support
591#
592CONFIG_FIRMWARE_EDID=y
593CONFIG_FB=y
594# CONFIG_FB_CFB_FILLRECT is not set
595# CONFIG_FB_CFB_COPYAREA is not set
596# CONFIG_FB_CFB_IMAGEBLIT is not set
597# CONFIG_FB_MACMODES is not set
598# CONFIG_FB_BACKLIGHT is not set
599# CONFIG_FB_MODE_HELPERS is not set
600# CONFIG_FB_TILEBLITTING is not set
601# CONFIG_FB_S1D13XXX is not set
602# CONFIG_FB_VIRTUAL is not set
603CONFIG_FB_OMAP=y
604# CONFIG_FB_OMAP_LCDC_EXTERNAL is not set
605# CONFIG_FB_OMAP_LCD_MIPID is not set
606# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set
607CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=2
608# CONFIG_FB_OMAP_DMA_TUNE is not set
609
610#
611# Console display driver support
612#
613# CONFIG_VGA_CONSOLE is not set
614CONFIG_DUMMY_CONSOLE=y
615CONFIG_FRAMEBUFFER_CONSOLE=y
616# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
617# CONFIG_FONTS is not set
618CONFIG_FONT_8x8=y
619CONFIG_FONT_8x16=y
620
621#
622# Logo configuration
623#
624# CONFIG_LOGO is not set
625CONFIG_BACKLIGHT_LCD_SUPPORT=y
626CONFIG_BACKLIGHT_CLASS_DEVICE=y
627CONFIG_BACKLIGHT_DEVICE=y
628CONFIG_LCD_CLASS_DEVICE=y
629CONFIG_LCD_DEVICE=y
630CONFIG_BACKLIGHT_OMAP=y
631
632#
633# Sound
634#
635# CONFIG_SOUND is not set
636
637#
638# USB support
639#
640CONFIG_USB_ARCH_HAS_HCD=y
641CONFIG_USB_ARCH_HAS_OHCI=y
642# CONFIG_USB_ARCH_HAS_EHCI is not set
643# CONFIG_USB is not set
644
645#
646# Enable Host or Gadget support to see Inventra options
647#
648
649#
650# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
651#
652
653#
654# USB Gadget Support
655#
656# CONFIG_USB_GADGET is not set
657
658#
659# MMC/SD Card support
660#
661# CONFIG_MMC is not set
662
663#
664# Real Time Clock
665#
666CONFIG_RTC_LIB=y
667CONFIG_RTC_CLASS=y
668CONFIG_RTC_HCTOSYS=y
669CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
670# CONFIG_RTC_DEBUG is not set
671
672#
673# RTC interfaces
674#
675CONFIG_RTC_INTF_SYSFS=y
676CONFIG_RTC_INTF_PROC=y
677CONFIG_RTC_INTF_DEV=y
678# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
679
680#
681# RTC drivers
682#
683# CONFIG_RTC_DRV_DS1553 is not set
684# CONFIG_RTC_DRV_DS1742 is not set
685CONFIG_RTC_DRV_OMAP=y
686# CONFIG_RTC_DRV_RS5C348 is not set
687# CONFIG_RTC_DRV_M48T86 is not set
688# CONFIG_RTC_DRV_TEST is not set
689# CONFIG_RTC_DRV_MAX6902 is not set
690# CONFIG_RTC_DRV_V3020 is not set
691
692#
693# Synchronous Serial Interfaces (SSI)
694#
695# CONFIG_OMAP_UWIRE is not set
696# CONFIG_OMAP_TSC2101 is not set
697
698#
699# CBUS support
700#
701# CONFIG_CBUS is not set
702
703#
704# File systems
705#
706CONFIG_EXT2_FS=y
707# CONFIG_EXT2_FS_XATTR is not set
708# CONFIG_EXT2_FS_XIP is not set
709# CONFIG_EXT3_FS is not set
710# CONFIG_EXT4DEV_FS is not set
711# CONFIG_REISERFS_FS is not set
712# CONFIG_JFS_FS is not set
713# CONFIG_FS_POSIX_ACL is not set
714# CONFIG_XFS_FS is not set
715# CONFIG_GFS2_FS is not set
716# CONFIG_OCFS2_FS is not set
717# CONFIG_MINIX_FS is not set
718# CONFIG_ROMFS_FS is not set
719# CONFIG_INOTIFY is not set
720# CONFIG_QUOTA is not set
721CONFIG_DNOTIFY=y
722# CONFIG_AUTOFS_FS is not set
723# CONFIG_AUTOFS4_FS is not set
724# CONFIG_FUSE_FS is not set
725
726#
727# CD-ROM/DVD Filesystems
728#
729# CONFIG_ISO9660_FS is not set
730# CONFIG_UDF_FS is not set
731
732#
733# DOS/FAT/NT Filesystems
734#
735# CONFIG_MSDOS_FS is not set
736# CONFIG_VFAT_FS is not set
737# CONFIG_NTFS_FS is not set
738
739#
740# Pseudo filesystems
741#
742CONFIG_PROC_FS=y
743CONFIG_PROC_SYSCTL=y
744CONFIG_SYSFS=y
745# CONFIG_TMPFS is not set
746# CONFIG_HUGETLB_PAGE is not set
747CONFIG_RAMFS=y
748# CONFIG_CONFIGFS_FS is not set
749
750#
751# Miscellaneous filesystems
752#
753# CONFIG_ADFS_FS is not set
754# CONFIG_AFFS_FS is not set
755# CONFIG_HFS_FS is not set
756# CONFIG_HFSPLUS_FS is not set
757# CONFIG_BEFS_FS is not set
758# CONFIG_BFS_FS is not set
759# CONFIG_EFS_FS is not set
760# CONFIG_CRAMFS is not set
761# CONFIG_VXFS_FS is not set
762# CONFIG_HPFS_FS is not set
763# CONFIG_QNX4FS_FS is not set
764# CONFIG_SYSV_FS is not set
765# CONFIG_UFS_FS is not set
766
767#
768# Network File Systems
769#
770# CONFIG_NFS_FS is not set
771# CONFIG_NFSD is not set
772# CONFIG_SMB_FS is not set
773# CONFIG_CIFS is not set
774# CONFIG_NCP_FS is not set
775# CONFIG_CODA_FS is not set
776# CONFIG_AFS_FS is not set
777# CONFIG_9P_FS is not set
778
779#
780# Partition Types
781#
782CONFIG_PARTITION_ADVANCED=y
783# CONFIG_ACORN_PARTITION is not set
784# CONFIG_OSF_PARTITION is not set
785# CONFIG_AMIGA_PARTITION is not set
786# CONFIG_ATARI_PARTITION is not set
787# CONFIG_MAC_PARTITION is not set
788CONFIG_MSDOS_PARTITION=y
789# CONFIG_BSD_DISKLABEL is not set
790# CONFIG_MINIX_SUBPARTITION is not set
791# CONFIG_SOLARIS_X86_PARTITION is not set
792# CONFIG_UNIXWARE_DISKLABEL is not set
793# CONFIG_LDM_PARTITION is not set
794# CONFIG_SGI_PARTITION is not set
795# CONFIG_ULTRIX_PARTITION is not set
796# CONFIG_SUN_PARTITION is not set
797# CONFIG_KARMA_PARTITION is not set
798# CONFIG_EFI_PARTITION is not set
799
800#
801# Native Language Support
802#
803# CONFIG_NLS is not set
804
805#
806# Profiling support
807#
808# CONFIG_PROFILING is not set
809
810#
811# Kernel hacking
812#
813# CONFIG_PRINTK_TIME is not set
814# CONFIG_ENABLE_MUST_CHECK is not set
815# CONFIG_MAGIC_SYSRQ is not set
816# CONFIG_UNUSED_SYMBOLS is not set
817# CONFIG_DEBUG_KERNEL is not set
818CONFIG_LOG_BUF_SHIFT=14
819CONFIG_DEBUG_BUGVERBOSE=y
820# CONFIG_DEBUG_FS is not set
821CONFIG_FRAME_POINTER=y
822# CONFIG_UNWIND_INFO is not set
823# CONFIG_HEADERS_CHECK is not set
824# CONFIG_DEBUG_USER is not set
825
826#
827# Security options
828#
829# CONFIG_KEYS is not set
830# CONFIG_SECURITY is not set
831
832#
833# Cryptographic options
834#
835# CONFIG_CRYPTO is not set
836
837#
838# Library routines
839#
840CONFIG_CRC_CCITT=y
841CONFIG_CRC16=y
842CONFIG_CRC32=y
843CONFIG_LIBCRC32C=y
844CONFIG_PLIST=y
diff --git a/arch/arm/configs/palmz71_defconfig b/arch/arm/configs/palmz71_defconfig
new file mode 100644
index 000000000000..6361922e71c1
--- /dev/null
+++ b/arch/arm/configs/palmz71_defconfig
@@ -0,0 +1,891 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.22-rc1-omap1
4# Thu Jun 7 05:13:00 2007
5#
6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8CONFIG_GENERIC_GPIO=y
9CONFIG_GENERIC_TIME=y
10CONFIG_GENERIC_CLOCKEVENTS=y
11CONFIG_MMU=y
12# CONFIG_NO_IOPORT is not set
13CONFIG_GENERIC_HARDIRQS=y
14CONFIG_STACKTRACE_SUPPORT=y
15CONFIG_LOCKDEP_SUPPORT=y
16CONFIG_TRACE_IRQFLAGS_SUPPORT=y
17CONFIG_HARDIRQS_SW_RESEND=y
18CONFIG_GENERIC_IRQ_PROBE=y
19CONFIG_RWSEM_GENERIC_SPINLOCK=y
20# CONFIG_ARCH_HAS_ILOG2_U32 is not set
21# CONFIG_ARCH_HAS_ILOG2_U64 is not set
22CONFIG_GENERIC_HWEIGHT=y
23CONFIG_GENERIC_CALIBRATE_DELAY=y
24CONFIG_ZONE_DMA=y
25CONFIG_VECTORS_BASE=0xffff0000
26CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
27
28#
29# Code maturity level options
30#
31CONFIG_EXPERIMENTAL=y
32CONFIG_BROKEN_ON_SMP=y
33CONFIG_INIT_ENV_ARG_LIMIT=32
34
35#
36# General setup
37#
38CONFIG_LOCALVERSION="-z71"
39CONFIG_LOCALVERSION_AUTO=y
40CONFIG_SWAP=y
41CONFIG_SYSVIPC=y
42# CONFIG_IPC_NS is not set
43CONFIG_SYSVIPC_SYSCTL=y
44# CONFIG_POSIX_MQUEUE is not set
45CONFIG_BSD_PROCESS_ACCT=y
46# CONFIG_BSD_PROCESS_ACCT_V3 is not set
47# CONFIG_TASKSTATS is not set
48# CONFIG_UTS_NS is not set
49# CONFIG_AUDIT is not set
50# CONFIG_IKCONFIG is not set
51CONFIG_LOG_BUF_SHIFT=14
52CONFIG_SYSFS_DEPRECATED=y
53# CONFIG_RELAY is not set
54# CONFIG_BLK_DEV_INITRD is not set
55CONFIG_CC_OPTIMIZE_FOR_SIZE=y
56CONFIG_SYSCTL=y
57# CONFIG_EMBEDDED is not set
58CONFIG_UID16=y
59CONFIG_SYSCTL_SYSCALL=y
60CONFIG_KALLSYMS=y
61# CONFIG_KALLSYMS_EXTRA_PASS is not set
62CONFIG_HOTPLUG=y
63CONFIG_PRINTK=y
64CONFIG_BUG=y
65CONFIG_ELF_CORE=y
66CONFIG_BASE_FULL=y
67CONFIG_FUTEX=y
68CONFIG_ANON_INODES=y
69CONFIG_EPOLL=y
70CONFIG_SIGNALFD=y
71CONFIG_TIMERFD=y
72CONFIG_EVENTFD=y
73CONFIG_SHMEM=y
74CONFIG_VM_EVENT_COUNTERS=y
75CONFIG_SLAB=y
76# CONFIG_SLUB is not set
77# CONFIG_SLOB is not set
78CONFIG_RT_MUTEXES=y
79# CONFIG_TINY_SHMEM is not set
80CONFIG_BASE_SMALL=0
81
82#
83# Loadable module support
84#
85# CONFIG_MODULES is not set
86
87#
88# Block layer
89#
90CONFIG_BLOCK=y
91# CONFIG_LBD is not set
92# CONFIG_BLK_DEV_IO_TRACE is not set
93# CONFIG_LSF is not set
94
95#
96# IO Schedulers
97#
98CONFIG_IOSCHED_NOOP=y
99# CONFIG_IOSCHED_AS is not set
100# CONFIG_IOSCHED_DEADLINE is not set
101# CONFIG_IOSCHED_CFQ is not set
102# CONFIG_DEFAULT_AS is not set
103# CONFIG_DEFAULT_DEADLINE is not set
104# CONFIG_DEFAULT_CFQ is not set
105CONFIG_DEFAULT_NOOP=y
106CONFIG_DEFAULT_IOSCHED="noop"
107
108#
109# System Type
110#
111# CONFIG_ARCH_AAEC2000 is not set
112# CONFIG_ARCH_INTEGRATOR is not set
113# CONFIG_ARCH_REALVIEW is not set
114# CONFIG_ARCH_VERSATILE is not set
115# CONFIG_ARCH_AT91 is not set
116# CONFIG_ARCH_CLPS7500 is not set
117# CONFIG_ARCH_CLPS711X is not set
118# CONFIG_ARCH_CO285 is not set
119# CONFIG_ARCH_EBSA110 is not set
120# CONFIG_ARCH_EP93XX is not set
121# CONFIG_ARCH_FOOTBRIDGE is not set
122# CONFIG_ARCH_NETX is not set
123# CONFIG_ARCH_H720X is not set
124# CONFIG_ARCH_IMX is not set
125# CONFIG_ARCH_IOP13XX is not set
126# CONFIG_ARCH_IOP32X is not set
127# CONFIG_ARCH_IOP33X is not set
128# CONFIG_ARCH_IXP23XX is not set
129# CONFIG_ARCH_IXP2000 is not set
130# CONFIG_ARCH_IXP4XX is not set
131# CONFIG_ARCH_L7200 is not set
132# CONFIG_ARCH_KS8695 is not set
133# CONFIG_ARCH_NS9XXX is not set
134# CONFIG_ARCH_PNX4008 is not set
135# CONFIG_ARCH_PXA is not set
136# CONFIG_ARCH_RPC is not set
137# CONFIG_ARCH_SA1100 is not set
138# CONFIG_ARCH_S3C2410 is not set
139# CONFIG_ARCH_SHARK is not set
140# CONFIG_ARCH_LH7A40X is not set
141# CONFIG_ARCH_DAVINCI is not set
142CONFIG_ARCH_OMAP=y
143
144#
145# TI OMAP Implementations
146#
147CONFIG_ARCH_OMAP1=y
148# CONFIG_ARCH_OMAP2 is not set
149
150#
151# OMAP Feature Selections
152#
153# CONFIG_OMAP_RESET_CLOCKS is not set
154# CONFIG_OMAP_BOOT_TAG is not set
155# CONFIG_OMAP_GPIO_SWITCH is not set
156CONFIG_OMAP_MUX=y
157# CONFIG_OMAP_MUX_DEBUG is not set
158CONFIG_OMAP_MUX_WARNINGS=y
159CONFIG_OMAP_MCBSP=y
160# CONFIG_OMAP_MMU_FWK is not set
161# CONFIG_OMAP_MBOX_FWK is not set
162CONFIG_OMAP_MPU_TIMER=y
163# CONFIG_OMAP_32K_TIMER is not set
164CONFIG_OMAP_LL_DEBUG_UART1=y
165# CONFIG_OMAP_LL_DEBUG_UART2 is not set
166# CONFIG_OMAP_LL_DEBUG_UART3 is not set
167# CONFIG_OMAP_LL_DEBUG_LCD is not set
168CONFIG_OMAP_SERIAL_WAKE=y
169# CONFIG_OMAP_DSP is not set
170
171#
172# OMAP Core Type
173#
174# CONFIG_ARCH_OMAP730 is not set
175CONFIG_ARCH_OMAP15XX=y
176# CONFIG_ARCH_OMAP16XX is not set
177
178#
179# OMAP Board Type
180#
181# CONFIG_MACH_OMAP_INNOVATOR is not set
182# CONFIG_MACH_VOICEBLUE is not set
183# CONFIG_MACH_OMAP_PALMTE is not set
184CONFIG_MACH_OMAP_PALMZ71=y
185# CONFIG_MACH_OMAP_PALMTT is not set
186# CONFIG_MACH_SX1 is not set
187# CONFIG_MACH_AMS_DELTA is not set
188# CONFIG_MACH_OMAP_GENERIC is not set
189
190#
191# OMAP CPU Speed
192#
193CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER=y
194# CONFIG_OMAP_ARM_168MHZ is not set
195# CONFIG_OMAP_ARM_150MHZ is not set
196# CONFIG_OMAP_ARM_120MHZ is not set
197# CONFIG_OMAP_ARM_60MHZ is not set
198# CONFIG_OMAP_ARM_30MHZ is not set
199
200#
201# Processor Type
202#
203CONFIG_CPU_32=y
204CONFIG_CPU_ARM925T=y
205CONFIG_CPU_32v4T=y
206CONFIG_CPU_ABRT_EV4T=y
207CONFIG_CPU_CACHE_V4WT=y
208CONFIG_CPU_CACHE_VIVT=y
209CONFIG_CPU_COPY_V4WB=y
210CONFIG_CPU_TLB_V4WBI=y
211CONFIG_CPU_CP15=y
212CONFIG_CPU_CP15_MMU=y
213
214#
215# Processor Features
216#
217# CONFIG_ARM_THUMB is not set
218# CONFIG_CPU_ICACHE_DISABLE is not set
219# CONFIG_CPU_DCACHE_DISABLE is not set
220# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
221# CONFIG_OUTER_CACHE is not set
222
223#
224# Bus support
225#
226# CONFIG_ARCH_SUPPORTS_MSI is not set
227
228#
229# PCCARD (PCMCIA/CardBus) support
230#
231# CONFIG_PCCARD is not set
232
233#
234# Kernel Features
235#
236# CONFIG_TICK_ONESHOT is not set
237# CONFIG_NO_HZ is not set
238# CONFIG_HIGH_RES_TIMERS is not set
239# CONFIG_PREEMPT is not set
240CONFIG_HZ=100
241# CONFIG_AEABI is not set
242# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
243CONFIG_SELECT_MEMORY_MODEL=y
244CONFIG_FLATMEM_MANUAL=y
245# CONFIG_DISCONTIGMEM_MANUAL is not set
246# CONFIG_SPARSEMEM_MANUAL is not set
247CONFIG_FLATMEM=y
248CONFIG_FLAT_NODE_MEM_MAP=y
249# CONFIG_SPARSEMEM_STATIC is not set
250CONFIG_SPLIT_PTLOCK_CPUS=4096
251# CONFIG_RESOURCES_64BIT is not set
252CONFIG_ZONE_DMA_FLAG=1
253# CONFIG_LEDS is not set
254CONFIG_ALIGNMENT_TRAP=y
255
256#
257# Boot options
258#
259CONFIG_ZBOOT_ROM_TEXT=0x0
260CONFIG_ZBOOT_ROM_BSS=0x0
261CONFIG_CMDLINE=""
262# CONFIG_XIP_KERNEL is not set
263# CONFIG_KEXEC is not set
264
265#
266# CPU Frequency scaling
267#
268# CONFIG_CPU_FREQ is not set
269
270#
271# Floating point emulation
272#
273
274#
275# At least one emulation must be selected
276#
277CONFIG_FPE_NWFPE=y
278# CONFIG_FPE_NWFPE_XP is not set
279# CONFIG_FPE_FASTFPE is not set
280
281#
282# Userspace binary formats
283#
284CONFIG_BINFMT_ELF=y
285# CONFIG_BINFMT_AOUT is not set
286# CONFIG_BINFMT_MISC is not set
287# CONFIG_ARTHUR is not set
288
289#
290# Power management options
291#
292# CONFIG_PM is not set
293
294#
295# Networking
296#
297CONFIG_NET=y
298
299#
300# Networking options
301#
302CONFIG_PACKET=y
303# CONFIG_PACKET_MMAP is not set
304CONFIG_UNIX=y
305CONFIG_XFRM=y
306# CONFIG_XFRM_USER is not set
307# CONFIG_XFRM_SUB_POLICY is not set
308# CONFIG_XFRM_MIGRATE is not set
309CONFIG_NET_KEY=y
310# CONFIG_NET_KEY_MIGRATE is not set
311CONFIG_INET=y
312# CONFIG_IP_MULTICAST is not set
313# CONFIG_IP_ADVANCED_ROUTER is not set
314CONFIG_IP_FIB_HASH=y
315# CONFIG_IP_PNP is not set
316# CONFIG_NET_IPIP is not set
317# CONFIG_NET_IPGRE is not set
318# CONFIG_ARPD is not set
319# CONFIG_SYN_COOKIES is not set
320# CONFIG_INET_AH is not set
321# CONFIG_INET_ESP is not set
322# CONFIG_INET_IPCOMP is not set
323# CONFIG_INET_XFRM_TUNNEL is not set
324# CONFIG_INET_TUNNEL is not set
325# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
326# CONFIG_INET_XFRM_MODE_TUNNEL is not set
327CONFIG_INET_XFRM_MODE_BEET=y
328# CONFIG_INET_DIAG is not set
329# CONFIG_TCP_CONG_ADVANCED is not set
330CONFIG_TCP_CONG_CUBIC=y
331CONFIG_DEFAULT_TCP_CONG="cubic"
332# CONFIG_TCP_MD5SIG is not set
333# CONFIG_IPV6 is not set
334# CONFIG_INET6_XFRM_TUNNEL is not set
335# CONFIG_INET6_TUNNEL is not set
336# CONFIG_NETWORK_SECMARK is not set
337# CONFIG_NETFILTER is not set
338
339#
340# DCCP Configuration (EXPERIMENTAL)
341#
342# CONFIG_IP_DCCP is not set
343
344#
345# SCTP Configuration (EXPERIMENTAL)
346#
347# CONFIG_IP_SCTP is not set
348
349#
350# TIPC Configuration (EXPERIMENTAL)
351#
352# CONFIG_TIPC is not set
353# CONFIG_ATM is not set
354# CONFIG_BRIDGE is not set
355# CONFIG_VLAN_8021Q is not set
356# CONFIG_DECNET is not set
357# CONFIG_LLC2 is not set
358# CONFIG_IPX is not set
359# CONFIG_ATALK is not set
360# CONFIG_X25 is not set
361# CONFIG_LAPB is not set
362# CONFIG_ECONET is not set
363# CONFIG_WAN_ROUTER is not set
364
365#
366# QoS and/or fair queueing
367#
368# CONFIG_NET_SCHED is not set
369
370#
371# Network testing
372#
373# CONFIG_NET_PKTGEN is not set
374# CONFIG_HAMRADIO is not set
375# CONFIG_IRDA is not set
376# CONFIG_BT is not set
377# CONFIG_AF_RXRPC is not set
378
379#
380# Wireless
381#
382# CONFIG_CFG80211 is not set
383# CONFIG_WIRELESS_EXT is not set
384# CONFIG_MAC80211 is not set
385# CONFIG_IEEE80211 is not set
386# CONFIG_RFKILL is not set
387
388#
389# Device Drivers
390#
391
392#
393# Generic Driver Options
394#
395CONFIG_STANDALONE=y
396CONFIG_PREVENT_FIRMWARE_BUILD=y
397# CONFIG_FW_LOADER is not set
398# CONFIG_SYS_HYPERVISOR is not set
399
400#
401# Connector - unified userspace <-> kernelspace linker
402#
403# CONFIG_CONNECTOR is not set
404# CONFIG_MTD is not set
405
406#
407# Parallel port support
408#
409# CONFIG_PARPORT is not set
410
411#
412# Plug and Play support
413#
414# CONFIG_PNPACPI is not set
415
416#
417# Block devices
418#
419# CONFIG_BLK_DEV_COW_COMMON is not set
420# CONFIG_BLK_DEV_LOOP is not set
421# CONFIG_BLK_DEV_NBD is not set
422# CONFIG_BLK_DEV_RAM is not set
423# CONFIG_CDROM_PKTCDVD is not set
424# CONFIG_ATA_OVER_ETH is not set
425
426#
427# SCSI device support
428#
429# CONFIG_RAID_ATTRS is not set
430# CONFIG_SCSI is not set
431# CONFIG_SCSI_NETLINK is not set
432# CONFIG_ATA is not set
433
434#
435# Multi-device support (RAID and LVM)
436#
437# CONFIG_MD is not set
438
439#
440# Network device support
441#
442# CONFIG_NETDEVICES is not set
443# CONFIG_NETPOLL is not set
444# CONFIG_NET_POLL_CONTROLLER is not set
445
446#
447# ISDN subsystem
448#
449# CONFIG_ISDN is not set
450
451#
452# Input device support
453#
454CONFIG_INPUT=y
455# CONFIG_INPUT_FF_MEMLESS is not set
456
457#
458# Userland interfaces
459#
460CONFIG_INPUT_MOUSEDEV=y
461CONFIG_INPUT_MOUSEDEV_PSAUX=y
462CONFIG_INPUT_MOUSEDEV_SCREEN_X=320
463CONFIG_INPUT_MOUSEDEV_SCREEN_Y=320
464# CONFIG_INPUT_JOYDEV is not set
465CONFIG_INPUT_TSDEV=y
466CONFIG_INPUT_TSDEV_SCREEN_X=320
467CONFIG_INPUT_TSDEV_SCREEN_Y=320
468# CONFIG_INPUT_EVDEV is not set
469# CONFIG_INPUT_EVBUG is not set
470
471#
472# Input Device Drivers
473#
474# CONFIG_INPUT_KEYBOARD is not set
475# CONFIG_INPUT_MOUSE is not set
476# CONFIG_INPUT_JOYSTICK is not set
477# CONFIG_INPUT_TABLET is not set
478CONFIG_INPUT_TOUCHSCREEN=y
479CONFIG_TOUCHSCREEN_ADS7846=y
480# CONFIG_TOUCHSCREEN_GUNZE is not set
481# CONFIG_TOUCHSCREEN_ELO is not set
482# CONFIG_TOUCHSCREEN_MTOUCH is not set
483# CONFIG_TOUCHSCREEN_MK712 is not set
484# CONFIG_TOUCHSCREEN_PENMOUNT is not set
485# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
486# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
487# CONFIG_TOUCHSCREEN_UCB1400 is not set
488# CONFIG_TOUCHSCREEN_TSC210X is not set
489# CONFIG_TOUCHSCREEN_TSC2046 is not set
490# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
491# CONFIG_INPUT_MISC is not set
492
493#
494# Hardware I/O ports
495#
496# CONFIG_SERIO is not set
497# CONFIG_GAMEPORT is not set
498
499#
500# Character devices
501#
502CONFIG_VT=y
503CONFIG_VT_CONSOLE=y
504CONFIG_HW_CONSOLE=y
505# CONFIG_VT_HW_CONSOLE_BINDING is not set
506# CONFIG_SERIAL_NONSTANDARD is not set
507
508#
509# Serial drivers
510#
511CONFIG_SERIAL_8250=y
512CONFIG_SERIAL_8250_CONSOLE=y
513CONFIG_SERIAL_8250_NR_UARTS=4
514CONFIG_SERIAL_8250_RUNTIME_UARTS=4
515# CONFIG_SERIAL_8250_EXTENDED is not set
516
517#
518# Non-8250 serial port support
519#
520CONFIG_SERIAL_CORE=y
521CONFIG_SERIAL_CORE_CONSOLE=y
522CONFIG_UNIX98_PTYS=y
523CONFIG_LEGACY_PTYS=y
524CONFIG_LEGACY_PTY_COUNT=16
525
526#
527# IPMI
528#
529# CONFIG_IPMI_HANDLER is not set
530# CONFIG_WATCHDOG is not set
531CONFIG_HW_RANDOM=y
532# CONFIG_NVRAM is not set
533# CONFIG_R3964 is not set
534# CONFIG_RAW_DRIVER is not set
535
536#
537# TPM devices
538#
539# CONFIG_TCG_TPM is not set
540# CONFIG_I2C is not set
541
542#
543# SPI support
544#
545CONFIG_SPI=y
546CONFIG_SPI_MASTER=y
547
548#
549# SPI Master Controller Drivers
550#
551CONFIG_SPI_BITBANG=y
552CONFIG_SPI_OMAP_UWIRE=y
553
554#
555# SPI Protocol Masters
556#
557# CONFIG_SPI_AT25 is not set
558# CONFIG_SPI_TSC2101 is not set
559# CONFIG_SPI_TSC2102 is not set
560# CONFIG_SPI_TSC210X is not set
561# CONFIG_SPI_TSC2301 is not set
562# CONFIG_SPI_SPIDEV is not set
563
564#
565# Dallas's 1-wire bus
566#
567# CONFIG_W1 is not set
568CONFIG_HWMON=y
569# CONFIG_HWMON_VID is not set
570# CONFIG_SENSORS_ABITUGURU is not set
571# CONFIG_SENSORS_F71805F is not set
572# CONFIG_SENSORS_LM70 is not set
573# CONFIG_SENSORS_PC87427 is not set
574# CONFIG_SENSORS_SMSC47M1 is not set
575# CONFIG_SENSORS_SMSC47B397 is not set
576# CONFIG_SENSORS_VT1211 is not set
577# CONFIG_SENSORS_W83627HF is not set
578# CONFIG_SENSORS_TSC210X is not set
579# CONFIG_HWMON_DEBUG_CHIP is not set
580
581#
582# Misc devices
583#
584# CONFIG_BLINK is not set
585
586#
587# Multifunction device drivers
588#
589# CONFIG_MFD_SM501 is not set
590
591#
592# LED devices
593#
594# CONFIG_NEW_LEDS is not set
595
596#
597# LED drivers
598#
599
600#
601# LED Triggers
602#
603
604#
605# Multimedia devices
606#
607# CONFIG_VIDEO_DEV is not set
608# CONFIG_DVB_CORE is not set
609CONFIG_DAB=y
610
611#
612# Graphics support
613#
614CONFIG_BACKLIGHT_LCD_SUPPORT=y
615CONFIG_BACKLIGHT_CLASS_DEVICE=y
616CONFIG_LCD_CLASS_DEVICE=y
617CONFIG_BACKLIGHT_OMAP=y
618
619#
620# Display device support
621#
622# CONFIG_DISPLAY_SUPPORT is not set
623# CONFIG_VGASTATE is not set
624CONFIG_FB=y
625CONFIG_FIRMWARE_EDID=y
626# CONFIG_FB_DDC is not set
627# CONFIG_FB_CFB_FILLRECT is not set
628# CONFIG_FB_CFB_COPYAREA is not set
629# CONFIG_FB_CFB_IMAGEBLIT is not set
630# CONFIG_FB_SYS_FILLRECT is not set
631# CONFIG_FB_SYS_COPYAREA is not set
632# CONFIG_FB_SYS_IMAGEBLIT is not set
633# CONFIG_FB_SYS_FOPS is not set
634CONFIG_FB_DEFERRED_IO=y
635# CONFIG_FB_SVGALIB is not set
636# CONFIG_FB_MACMODES is not set
637# CONFIG_FB_BACKLIGHT is not set
638# CONFIG_FB_MODE_HELPERS is not set
639# CONFIG_FB_TILEBLITTING is not set
640
641#
642# Frame buffer hardware drivers
643#
644# CONFIG_FB_S1D13XXX is not set
645CONFIG_FB_OMAP=y
646# CONFIG_FB_OMAP_LCDC_EXTERNAL is not set
647# CONFIG_FB_OMAP_LCD_MIPID is not set
648# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set
649CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=2
650# CONFIG_FB_OMAP_DMA_TUNE is not set
651# CONFIG_FB_VIRTUAL is not set
652
653#
654# Console display driver support
655#
656# CONFIG_VGA_CONSOLE is not set
657CONFIG_DUMMY_CONSOLE=y
658CONFIG_FRAMEBUFFER_CONSOLE=y
659# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
660# CONFIG_FONTS is not set
661CONFIG_FONT_8x8=y
662CONFIG_FONT_8x16=y
663# CONFIG_LOGO is not set
664
665#
666# Sound
667#
668# CONFIG_SOUND is not set
669
670#
671# HID Devices
672#
673CONFIG_HID=y
674# CONFIG_HID_DEBUG is not set
675
676#
677# USB support
678#
679CONFIG_USB_ARCH_HAS_HCD=y
680CONFIG_USB_ARCH_HAS_OHCI=y
681# CONFIG_USB_ARCH_HAS_EHCI is not set
682# CONFIG_USB is not set
683
684#
685# Enable Host or Gadget support to see Inventra options
686#
687
688#
689# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
690#
691
692#
693# USB Gadget Support
694#
695# CONFIG_USB_GADGET is not set
696CONFIG_MMC=y
697# CONFIG_MMC_DEBUG is not set
698# CONFIG_MMC_UNSAFE_RESUME is not set
699
700#
701# MMC/SD Card Drivers
702#
703CONFIG_MMC_BLOCK=y
704
705#
706# MMC/SD Host Controller Drivers
707#
708CONFIG_MMC_OMAP=y
709
710#
711# Real Time Clock
712#
713CONFIG_RTC_LIB=y
714CONFIG_RTC_CLASS=y
715CONFIG_RTC_HCTOSYS=y
716CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
717# CONFIG_RTC_DEBUG is not set
718
719#
720# RTC interfaces
721#
722CONFIG_RTC_INTF_SYSFS=y
723CONFIG_RTC_INTF_PROC=y
724CONFIG_RTC_INTF_DEV=y
725# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
726# CONFIG_RTC_DRV_TEST is not set
727
728#
729# I2C RTC drivers
730#
731
732#
733# SPI RTC drivers
734#
735# CONFIG_RTC_DRV_RS5C348 is not set
736# CONFIG_RTC_DRV_MAX6902 is not set
737
738#
739# Platform RTC drivers
740#
741# CONFIG_RTC_DRV_CMOS is not set
742# CONFIG_RTC_DRV_DS1553 is not set
743# CONFIG_RTC_DRV_DS1742 is not set
744# CONFIG_RTC_DRV_M48T86 is not set
745# CONFIG_RTC_DRV_V3020 is not set
746
747#
748# on-CPU RTC drivers
749#
750CONFIG_RTC_DRV_OMAP=y
751
752#
753# CBUS support
754#
755# CONFIG_CBUS is not set
756
757#
758# File systems
759#
760CONFIG_EXT2_FS=y
761# CONFIG_EXT2_FS_XATTR is not set
762# CONFIG_EXT2_FS_XIP is not set
763# CONFIG_EXT3_FS is not set
764# CONFIG_EXT4DEV_FS is not set
765# CONFIG_REISERFS_FS is not set
766# CONFIG_JFS_FS is not set
767# CONFIG_FS_POSIX_ACL is not set
768# CONFIG_XFS_FS is not set
769# CONFIG_GFS2_FS is not set
770# CONFIG_OCFS2_FS is not set
771# CONFIG_MINIX_FS is not set
772# CONFIG_ROMFS_FS is not set
773# CONFIG_INOTIFY is not set
774# CONFIG_QUOTA is not set
775CONFIG_DNOTIFY=y
776# CONFIG_AUTOFS_FS is not set
777# CONFIG_AUTOFS4_FS is not set
778# CONFIG_FUSE_FS is not set
779
780#
781# CD-ROM/DVD Filesystems
782#
783# CONFIG_ISO9660_FS is not set
784# CONFIG_UDF_FS is not set
785
786#
787# DOS/FAT/NT Filesystems
788#
789# CONFIG_MSDOS_FS is not set
790# CONFIG_VFAT_FS is not set
791# CONFIG_NTFS_FS is not set
792
793#
794# Pseudo filesystems
795#
796CONFIG_PROC_FS=y
797CONFIG_PROC_SYSCTL=y
798CONFIG_SYSFS=y
799# CONFIG_TMPFS is not set
800# CONFIG_HUGETLB_PAGE is not set
801CONFIG_RAMFS=y
802# CONFIG_CONFIGFS_FS is not set
803
804#
805# Miscellaneous filesystems
806#
807# CONFIG_ADFS_FS is not set
808# CONFIG_AFFS_FS is not set
809# CONFIG_HFS_FS is not set
810# CONFIG_HFSPLUS_FS is not set
811# CONFIG_BEFS_FS is not set
812# CONFIG_BFS_FS is not set
813# CONFIG_EFS_FS is not set
814# CONFIG_CRAMFS is not set
815# CONFIG_VXFS_FS is not set
816# CONFIG_HPFS_FS is not set
817# CONFIG_QNX4FS_FS is not set
818# CONFIG_SYSV_FS is not set
819# CONFIG_UFS_FS is not set
820
821#
822# Network File Systems
823#
824# CONFIG_NFS_FS is not set
825# CONFIG_NFSD is not set
826# CONFIG_SMB_FS is not set
827# CONFIG_CIFS is not set
828# CONFIG_NCP_FS is not set
829# CONFIG_CODA_FS is not set
830# CONFIG_AFS_FS is not set
831# CONFIG_9P_FS is not set
832
833#
834# Partition Types
835#
836# CONFIG_PARTITION_ADVANCED is not set
837CONFIG_MSDOS_PARTITION=y
838
839#
840# Native Language Support
841#
842# CONFIG_NLS is not set
843
844#
845# Distributed Lock Manager
846#
847# CONFIG_DLM is not set
848
849#
850# Profiling support
851#
852# CONFIG_PROFILING is not set
853
854#
855# Kernel hacking
856#
857# CONFIG_PRINTK_TIME is not set
858CONFIG_ENABLE_MUST_CHECK=y
859# CONFIG_MAGIC_SYSRQ is not set
860# CONFIG_UNUSED_SYMBOLS is not set
861# CONFIG_DEBUG_FS is not set
862# CONFIG_HEADERS_CHECK is not set
863# CONFIG_DEBUG_KERNEL is not set
864CONFIG_DEBUG_BUGVERBOSE=y
865CONFIG_FRAME_POINTER=y
866# CONFIG_DEBUG_USER is not set
867
868#
869# Security options
870#
871# CONFIG_KEYS is not set
872# CONFIG_SECURITY is not set
873
874#
875# Cryptographic options
876#
877# CONFIG_CRYPTO is not set
878
879#
880# Library routines
881#
882CONFIG_BITREVERSE=y
883CONFIG_CRC_CCITT=y
884CONFIG_CRC16=y
885# CONFIG_CRC_ITU_T is not set
886CONFIG_CRC32=y
887CONFIG_LIBCRC32C=y
888CONFIG_PLIST=y
889CONFIG_HAS_IOMEM=y
890CONFIG_HAS_IOPORT=y
891CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/sx1_defconfig b/arch/arm/configs/sx1_defconfig
new file mode 100644
index 000000000000..853dcdd9f2e0
--- /dev/null
+++ b/arch/arm/configs/sx1_defconfig
@@ -0,0 +1,1118 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.22-rc1-omap1
4# Thu Jun 7 05:16:10 2007
5#
6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8CONFIG_GENERIC_GPIO=y
9CONFIG_GENERIC_TIME=y
10CONFIG_GENERIC_CLOCKEVENTS=y
11CONFIG_MMU=y
12# CONFIG_NO_IOPORT is not set
13CONFIG_GENERIC_HARDIRQS=y
14CONFIG_STACKTRACE_SUPPORT=y
15CONFIG_LOCKDEP_SUPPORT=y
16CONFIG_TRACE_IRQFLAGS_SUPPORT=y
17CONFIG_HARDIRQS_SW_RESEND=y
18CONFIG_GENERIC_IRQ_PROBE=y
19CONFIG_RWSEM_GENERIC_SPINLOCK=y
20# CONFIG_ARCH_HAS_ILOG2_U32 is not set
21# CONFIG_ARCH_HAS_ILOG2_U64 is not set
22CONFIG_GENERIC_HWEIGHT=y
23CONFIG_GENERIC_CALIBRATE_DELAY=y
24CONFIG_ZONE_DMA=y
25CONFIG_VECTORS_BASE=0xffff0000
26CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
27
28#
29# Code maturity level options
30#
31CONFIG_EXPERIMENTAL=y
32CONFIG_BROKEN_ON_SMP=y
33CONFIG_LOCK_KERNEL=y
34CONFIG_INIT_ENV_ARG_LIMIT=32
35
36#
37# General setup
38#
39CONFIG_LOCALVERSION=""
40CONFIG_LOCALVERSION_AUTO=y
41CONFIG_SWAP=y
42CONFIG_SYSVIPC=y
43# CONFIG_IPC_NS is not set
44CONFIG_SYSVIPC_SYSCTL=y
45CONFIG_POSIX_MQUEUE=y
46# CONFIG_BSD_PROCESS_ACCT is not set
47# CONFIG_TASKSTATS is not set
48# CONFIG_UTS_NS is not set
49# CONFIG_AUDIT is not set
50CONFIG_IKCONFIG=y
51# CONFIG_IKCONFIG_PROC is not set
52CONFIG_LOG_BUF_SHIFT=14
53CONFIG_SYSFS_DEPRECATED=y
54# CONFIG_RELAY is not set
55# CONFIG_BLK_DEV_INITRD is not set
56CONFIG_CC_OPTIMIZE_FOR_SIZE=y
57CONFIG_SYSCTL=y
58CONFIG_EMBEDDED=y
59CONFIG_UID16=y
60CONFIG_SYSCTL_SYSCALL=y
61# CONFIG_KALLSYMS is not set
62CONFIG_HOTPLUG=y
63CONFIG_PRINTK=y
64CONFIG_BUG=y
65# CONFIG_ELF_CORE is not set
66# CONFIG_BASE_FULL is not set
67CONFIG_FUTEX=y
68CONFIG_ANON_INODES=y
69CONFIG_EPOLL=y
70CONFIG_SIGNALFD=y
71CONFIG_TIMERFD=y
72CONFIG_EVENTFD=y
73# CONFIG_SHMEM is not set
74# CONFIG_VM_EVENT_COUNTERS is not set
75# CONFIG_SLAB is not set
76# CONFIG_SLUB is not set
77CONFIG_SLOB=y
78CONFIG_RT_MUTEXES=y
79CONFIG_TINY_SHMEM=y
80CONFIG_BASE_SMALL=1
81
82#
83# Loadable module support
84#
85CONFIG_MODULES=y
86CONFIG_MODULE_UNLOAD=y
87# CONFIG_MODULE_FORCE_UNLOAD is not set
88# CONFIG_MODVERSIONS is not set
89# CONFIG_MODULE_SRCVERSION_ALL is not set
90CONFIG_KMOD=y
91
92#
93# Block layer
94#
95CONFIG_BLOCK=y
96# CONFIG_LBD is not set
97# CONFIG_BLK_DEV_IO_TRACE is not set
98# CONFIG_LSF is not set
99
100#
101# IO Schedulers
102#
103CONFIG_IOSCHED_NOOP=y
104# CONFIG_IOSCHED_AS is not set
105CONFIG_IOSCHED_DEADLINE=y
106# CONFIG_IOSCHED_CFQ is not set
107# CONFIG_DEFAULT_AS is not set
108CONFIG_DEFAULT_DEADLINE=y
109# CONFIG_DEFAULT_CFQ is not set
110# CONFIG_DEFAULT_NOOP is not set
111CONFIG_DEFAULT_IOSCHED="deadline"
112
113#
114# System Type
115#
116# CONFIG_ARCH_AAEC2000 is not set
117# CONFIG_ARCH_INTEGRATOR is not set
118# CONFIG_ARCH_REALVIEW is not set
119# CONFIG_ARCH_VERSATILE is not set
120# CONFIG_ARCH_AT91 is not set
121# CONFIG_ARCH_CLPS7500 is not set
122# CONFIG_ARCH_CLPS711X is not set
123# CONFIG_ARCH_CO285 is not set
124# CONFIG_ARCH_EBSA110 is not set
125# CONFIG_ARCH_EP93XX is not set
126# CONFIG_ARCH_FOOTBRIDGE is not set
127# CONFIG_ARCH_NETX is not set
128# CONFIG_ARCH_H720X is not set
129# CONFIG_ARCH_IMX is not set
130# CONFIG_ARCH_IOP13XX is not set
131# CONFIG_ARCH_IOP32X is not set
132# CONFIG_ARCH_IOP33X is not set
133# CONFIG_ARCH_IXP23XX is not set
134# CONFIG_ARCH_IXP2000 is not set
135# CONFIG_ARCH_IXP4XX is not set
136# CONFIG_ARCH_L7200 is not set
137# CONFIG_ARCH_KS8695 is not set
138# CONFIG_ARCH_NS9XXX is not set
139# CONFIG_ARCH_PNX4008 is not set
140# CONFIG_ARCH_PXA is not set
141# CONFIG_ARCH_RPC is not set
142# CONFIG_ARCH_SA1100 is not set
143# CONFIG_ARCH_S3C2410 is not set
144# CONFIG_ARCH_SHARK is not set
145# CONFIG_ARCH_LH7A40X is not set
146# CONFIG_ARCH_DAVINCI is not set
147CONFIG_ARCH_OMAP=y
148
149#
150# TI OMAP Implementations
151#
152CONFIG_ARCH_OMAP1=y
153# CONFIG_ARCH_OMAP2 is not set
154
155#
156# OMAP Feature Selections
157#
158# CONFIG_OMAP_RESET_CLOCKS is not set
159CONFIG_OMAP_BOOT_TAG=y
160# CONFIG_OMAP_BOOT_REASON is not set
161# CONFIG_OMAP_COMPONENT_VERSION is not set
162CONFIG_OMAP_GPIO_SWITCH=y
163CONFIG_OMAP_MUX=y
164# CONFIG_OMAP_MUX_DEBUG is not set
165CONFIG_OMAP_MUX_WARNINGS=y
166CONFIG_OMAP_MCBSP=y
167CONFIG_OMAP_MMU_FWK=y
168CONFIG_OMAP_MBOX_FWK=y
169CONFIG_OMAP_MPU_TIMER=y
170# CONFIG_OMAP_32K_TIMER is not set
171# CONFIG_OMAP_LL_DEBUG_UART1 is not set
172# CONFIG_OMAP_LL_DEBUG_UART2 is not set
173CONFIG_OMAP_LL_DEBUG_UART3=y
174# CONFIG_OMAP_LL_DEBUG_LCD is not set
175CONFIG_OMAP_SERIAL_WAKE=y
176CONFIG_OMAP_DSP=y
177# CONFIG_OMAP_DSP_MBCMD_VERBOSE is not set
178# CONFIG_OMAP_DSP_TASK_MULTIOPEN is not set
179# CONFIG_OMAP_DSP_FBEXPORT is not set
180
181#
182# OMAP Core Type
183#
184# CONFIG_ARCH_OMAP730 is not set
185CONFIG_ARCH_OMAP15XX=y
186# CONFIG_ARCH_OMAP16XX is not set
187
188#
189# OMAP Board Type
190#
191# CONFIG_MACH_OMAP_INNOVATOR is not set
192# CONFIG_MACH_VOICEBLUE is not set
193# CONFIG_MACH_OMAP_PALMTE is not set
194# CONFIG_MACH_OMAP_PALMZ71 is not set
195# CONFIG_MACH_OMAP_PALMTT is not set
196CONFIG_MACH_SX1=y
197# CONFIG_MACH_AMS_DELTA is not set
198# CONFIG_MACH_OMAP_GENERIC is not set
199
200#
201# OMAP CPU Speed
202#
203# CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER is not set
204CONFIG_OMAP_ARM_168MHZ=y
205# CONFIG_OMAP_ARM_150MHZ is not set
206# CONFIG_OMAP_ARM_120MHZ is not set
207# CONFIG_OMAP_ARM_60MHZ is not set
208# CONFIG_OMAP_ARM_30MHZ is not set
209
210#
211# Processor Type
212#
213CONFIG_CPU_32=y
214CONFIG_CPU_ARM925T=y
215CONFIG_CPU_32v4T=y
216CONFIG_CPU_ABRT_EV4T=y
217CONFIG_CPU_CACHE_V4WT=y
218CONFIG_CPU_CACHE_VIVT=y
219CONFIG_CPU_COPY_V4WB=y
220CONFIG_CPU_TLB_V4WBI=y
221CONFIG_CPU_CP15=y
222CONFIG_CPU_CP15_MMU=y
223
224#
225# Processor Features
226#
227CONFIG_ARM_THUMB=y
228# CONFIG_CPU_ICACHE_DISABLE is not set
229# CONFIG_CPU_DCACHE_DISABLE is not set
230# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
231# CONFIG_OUTER_CACHE is not set
232
233#
234# Bus support
235#
236# CONFIG_ARCH_SUPPORTS_MSI is not set
237
238#
239# PCCARD (PCMCIA/CardBus) support
240#
241# CONFIG_PCCARD is not set
242
243#
244# Kernel Features
245#
246# CONFIG_TICK_ONESHOT is not set
247# CONFIG_NO_HZ is not set
248# CONFIG_HIGH_RES_TIMERS is not set
249CONFIG_PREEMPT=y
250CONFIG_HZ=100
251# CONFIG_AEABI is not set
252# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
253CONFIG_SELECT_MEMORY_MODEL=y
254CONFIG_FLATMEM_MANUAL=y
255# CONFIG_DISCONTIGMEM_MANUAL is not set
256# CONFIG_SPARSEMEM_MANUAL is not set
257CONFIG_FLATMEM=y
258CONFIG_FLAT_NODE_MEM_MAP=y
259# CONFIG_SPARSEMEM_STATIC is not set
260CONFIG_SPLIT_PTLOCK_CPUS=4096
261# CONFIG_RESOURCES_64BIT is not set
262CONFIG_ZONE_DMA_FLAG=1
263# CONFIG_LEDS is not set
264CONFIG_ALIGNMENT_TRAP=y
265
266#
267# Boot options
268#
269CONFIG_ZBOOT_ROM_TEXT=0x0
270CONFIG_ZBOOT_ROM_BSS=0x0
271CONFIG_CMDLINE=""
272# CONFIG_XIP_KERNEL is not set
273# CONFIG_KEXEC is not set
274
275#
276# CPU Frequency scaling
277#
278# CONFIG_CPU_FREQ is not set
279
280#
281# Floating point emulation
282#
283
284#
285# At least one emulation must be selected
286#
287CONFIG_FPE_NWFPE=y
288# CONFIG_FPE_NWFPE_XP is not set
289# CONFIG_FPE_FASTFPE is not set
290
291#
292# Userspace binary formats
293#
294CONFIG_BINFMT_ELF=y
295# CONFIG_BINFMT_AOUT is not set
296CONFIG_BINFMT_MISC=y
297# CONFIG_ARTHUR is not set
298
299#
300# Power management options
301#
302# CONFIG_PM is not set
303
304#
305# Networking
306#
307CONFIG_NET=y
308
309#
310# Networking options
311#
312CONFIG_PACKET=y
313CONFIG_PACKET_MMAP=y
314CONFIG_UNIX=y
315# CONFIG_NET_KEY is not set
316CONFIG_INET=y
317# CONFIG_IP_MULTICAST is not set
318# CONFIG_IP_ADVANCED_ROUTER is not set
319CONFIG_IP_FIB_HASH=y
320CONFIG_IP_PNP=y
321# CONFIG_IP_PNP_DHCP is not set
322# CONFIG_IP_PNP_BOOTP is not set
323# CONFIG_IP_PNP_RARP is not set
324# CONFIG_NET_IPIP is not set
325# CONFIG_NET_IPGRE is not set
326# CONFIG_ARPD is not set
327# CONFIG_SYN_COOKIES is not set
328# CONFIG_INET_AH is not set
329# CONFIG_INET_ESP is not set
330# CONFIG_INET_IPCOMP is not set
331# CONFIG_INET_XFRM_TUNNEL is not set
332# CONFIG_INET_TUNNEL is not set
333# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
334# CONFIG_INET_XFRM_MODE_TUNNEL is not set
335# CONFIG_INET_XFRM_MODE_BEET is not set
336# CONFIG_INET_DIAG is not set
337# CONFIG_TCP_CONG_ADVANCED is not set
338CONFIG_TCP_CONG_CUBIC=y
339CONFIG_DEFAULT_TCP_CONG="cubic"
340# CONFIG_TCP_MD5SIG is not set
341# CONFIG_IPV6 is not set
342# CONFIG_INET6_XFRM_TUNNEL is not set
343# CONFIG_INET6_TUNNEL is not set
344# CONFIG_NETWORK_SECMARK is not set
345# CONFIG_NETFILTER is not set
346
347#
348# DCCP Configuration (EXPERIMENTAL)
349#
350# CONFIG_IP_DCCP is not set
351
352#
353# SCTP Configuration (EXPERIMENTAL)
354#
355# CONFIG_IP_SCTP is not set
356
357#
358# TIPC Configuration (EXPERIMENTAL)
359#
360# CONFIG_TIPC is not set
361# CONFIG_ATM is not set
362# CONFIG_BRIDGE is not set
363# CONFIG_VLAN_8021Q is not set
364# CONFIG_DECNET is not set
365# CONFIG_LLC2 is not set
366# CONFIG_IPX is not set
367# CONFIG_ATALK is not set
368# CONFIG_X25 is not set
369# CONFIG_LAPB is not set
370# CONFIG_ECONET is not set
371# CONFIG_WAN_ROUTER is not set
372
373#
374# QoS and/or fair queueing
375#
376# CONFIG_NET_SCHED is not set
377
378#
379# Network testing
380#
381# CONFIG_NET_PKTGEN is not set
382# CONFIG_HAMRADIO is not set
383# CONFIG_IRDA is not set
384# CONFIG_BT is not set
385# CONFIG_AF_RXRPC is not set
386
387#
388# Wireless
389#
390# CONFIG_CFG80211 is not set
391# CONFIG_WIRELESS_EXT is not set
392# CONFIG_MAC80211 is not set
393# CONFIG_IEEE80211 is not set
394# CONFIG_RFKILL is not set
395
396#
397# Device Drivers
398#
399
400#
401# Generic Driver Options
402#
403CONFIG_STANDALONE=y
404CONFIG_PREVENT_FIRMWARE_BUILD=y
405# CONFIG_FW_LOADER is not set
406# CONFIG_DEBUG_DRIVER is not set
407# CONFIG_DEBUG_DEVRES is not set
408# CONFIG_SYS_HYPERVISOR is not set
409
410#
411# Connector - unified userspace <-> kernelspace linker
412#
413CONFIG_CONNECTOR=y
414# CONFIG_PROC_EVENTS is not set
415# CONFIG_MTD is not set
416
417#
418# Parallel port support
419#
420# CONFIG_PARPORT is not set
421
422#
423# Plug and Play support
424#
425# CONFIG_PNPACPI is not set
426
427#
428# Block devices
429#
430# CONFIG_BLK_DEV_COW_COMMON is not set
431CONFIG_BLK_DEV_LOOP=m
432# CONFIG_BLK_DEV_CRYPTOLOOP is not set
433# CONFIG_BLK_DEV_NBD is not set
434CONFIG_BLK_DEV_RAM=m
435CONFIG_BLK_DEV_RAM_COUNT=2
436CONFIG_BLK_DEV_RAM_SIZE=4096
437CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
438# CONFIG_CDROM_PKTCDVD is not set
439# CONFIG_ATA_OVER_ETH is not set
440
441#
442# SCSI device support
443#
444# CONFIG_RAID_ATTRS is not set
445# CONFIG_SCSI is not set
446# CONFIG_SCSI_NETLINK is not set
447# CONFIG_ATA is not set
448
449#
450# Multi-device support (RAID and LVM)
451#
452# CONFIG_MD is not set
453
454#
455# Network device support
456#
457CONFIG_NETDEVICES=y
458# CONFIG_DUMMY is not set
459# CONFIG_BONDING is not set
460# CONFIG_EQUALIZER is not set
461# CONFIG_TUN is not set
462CONFIG_PHYLIB=y
463
464#
465# MII PHY device drivers
466#
467# CONFIG_MARVELL_PHY is not set
468# CONFIG_DAVICOM_PHY is not set
469# CONFIG_QSEMI_PHY is not set
470# CONFIG_LXT_PHY is not set
471# CONFIG_CICADA_PHY is not set
472# CONFIG_VITESSE_PHY is not set
473# CONFIG_SMSC_PHY is not set
474# CONFIG_BROADCOM_PHY is not set
475# CONFIG_FIXED_PHY is not set
476
477#
478# Ethernet (10 or 100Mbit)
479#
480CONFIG_NET_ETHERNET=y
481CONFIG_MII=y
482# CONFIG_SMC91X is not set
483# CONFIG_DM9000 is not set
484CONFIG_NETDEV_1000=y
485CONFIG_NETDEV_10000=y
486
487#
488# Token Ring devices
489#
490
491#
492# Wireless LAN
493#
494# CONFIG_WLAN_PRE80211 is not set
495# CONFIG_WLAN_80211 is not set
496# CONFIG_WAN is not set
497# CONFIG_PPP is not set
498# CONFIG_SLIP is not set
499# CONFIG_SHAPER is not set
500# CONFIG_NETCONSOLE is not set
501# CONFIG_NETPOLL is not set
502# CONFIG_NET_POLL_CONTROLLER is not set
503
504#
505# ISDN subsystem
506#
507# CONFIG_ISDN is not set
508
509#
510# Input device support
511#
512CONFIG_INPUT=y
513# CONFIG_INPUT_FF_MEMLESS is not set
514
515#
516# Userland interfaces
517#
518# CONFIG_INPUT_MOUSEDEV is not set
519# CONFIG_INPUT_JOYDEV is not set
520# CONFIG_INPUT_TSDEV is not set
521CONFIG_INPUT_EVDEV=y
522# CONFIG_INPUT_EVBUG is not set
523
524#
525# Input Device Drivers
526#
527CONFIG_INPUT_KEYBOARD=y
528# CONFIG_KEYBOARD_ATKBD is not set
529# CONFIG_KEYBOARD_SUNKBD is not set
530# CONFIG_KEYBOARD_LKKBD is not set
531# CONFIG_KEYBOARD_XTKBD is not set
532# CONFIG_KEYBOARD_NEWTON is not set
533# CONFIG_KEYBOARD_STOWAWAY is not set
534CONFIG_KEYBOARD_OMAP=y
535# CONFIG_KEYBOARD_GPIO is not set
536# CONFIG_INPUT_MOUSE is not set
537# CONFIG_INPUT_JOYSTICK is not set
538# CONFIG_INPUT_TABLET is not set
539# CONFIG_INPUT_TOUCHSCREEN is not set
540# CONFIG_INPUT_MISC is not set
541
542#
543# Hardware I/O ports
544#
545# CONFIG_SERIO is not set
546# CONFIG_GAMEPORT is not set
547
548#
549# Character devices
550#
551CONFIG_VT=y
552CONFIG_VT_CONSOLE=y
553CONFIG_HW_CONSOLE=y
554# CONFIG_VT_HW_CONSOLE_BINDING is not set
555# CONFIG_SERIAL_NONSTANDARD is not set
556
557#
558# Serial drivers
559#
560CONFIG_SERIAL_8250=y
561# CONFIG_SERIAL_8250_CONSOLE is not set
562CONFIG_SERIAL_8250_NR_UARTS=3
563CONFIG_SERIAL_8250_RUNTIME_UARTS=3
564# CONFIG_SERIAL_8250_EXTENDED is not set
565
566#
567# Non-8250 serial port support
568#
569CONFIG_SERIAL_CORE=y
570CONFIG_UNIX98_PTYS=y
571# CONFIG_LEGACY_PTYS is not set
572
573#
574# IPMI
575#
576# CONFIG_IPMI_HANDLER is not set
577# CONFIG_WATCHDOG is not set
578# CONFIG_HW_RANDOM is not set
579# CONFIG_NVRAM is not set
580# CONFIG_R3964 is not set
581# CONFIG_RAW_DRIVER is not set
582
583#
584# TPM devices
585#
586# CONFIG_TCG_TPM is not set
587CONFIG_I2C=y
588CONFIG_I2C_BOARDINFO=y
589CONFIG_I2C_CHARDEV=y
590
591#
592# I2C Algorithms
593#
594# CONFIG_I2C_ALGOBIT is not set
595# CONFIG_I2C_ALGOPCF is not set
596# CONFIG_I2C_ALGOPCA is not set
597
598#
599# I2C Hardware Bus support
600#
601# CONFIG_I2C_GPIO is not set
602# CONFIG_I2C_OCORES is not set
603CONFIG_I2C_OMAP=y
604# CONFIG_I2C_PARPORT_LIGHT is not set
605# CONFIG_I2C_SIMTEC is not set
606# CONFIG_I2C_STUB is not set
607
608#
609# Miscellaneous I2C Chip support
610#
611# CONFIG_SENSORS_DS1337 is not set
612# CONFIG_SENSORS_DS1374 is not set
613# CONFIG_SENSORS_EEPROM is not set
614# CONFIG_SENSORS_PCF8574 is not set
615# CONFIG_SENSORS_PCA9539 is not set
616# CONFIG_SENSORS_PCF8591 is not set
617# CONFIG_TPS65010 is not set
618# CONFIG_SENSORS_TLV320AIC23 is not set
619# CONFIG_SENSORS_MAX6875 is not set
620# CONFIG_I2C_DEBUG_CORE is not set
621# CONFIG_I2C_DEBUG_ALGO is not set
622# CONFIG_I2C_DEBUG_BUS is not set
623# CONFIG_I2C_DEBUG_CHIP is not set
624
625#
626# SPI support
627#
628# CONFIG_SPI is not set
629# CONFIG_SPI_MASTER is not set
630
631#
632# Dallas's 1-wire bus
633#
634# CONFIG_W1 is not set
635# CONFIG_HWMON is not set
636
637#
638# Misc devices
639#
640# CONFIG_BLINK is not set
641
642#
643# Multifunction device drivers
644#
645# CONFIG_MFD_SM501 is not set
646
647#
648# LED devices
649#
650# CONFIG_NEW_LEDS is not set
651
652#
653# LED drivers
654#
655
656#
657# LED Triggers
658#
659
660#
661# Multimedia devices
662#
663# CONFIG_VIDEO_DEV is not set
664# CONFIG_DVB_CORE is not set
665CONFIG_DAB=y
666
667#
668# Graphics support
669#
670# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
671
672#
673# Display device support
674#
675# CONFIG_DISPLAY_SUPPORT is not set
676# CONFIG_VGASTATE is not set
677CONFIG_FB=y
678# CONFIG_FIRMWARE_EDID is not set
679# CONFIG_FB_DDC is not set
680# CONFIG_FB_CFB_FILLRECT is not set
681# CONFIG_FB_CFB_COPYAREA is not set
682# CONFIG_FB_CFB_IMAGEBLIT is not set
683# CONFIG_FB_SYS_FILLRECT is not set
684# CONFIG_FB_SYS_COPYAREA is not set
685# CONFIG_FB_SYS_IMAGEBLIT is not set
686# CONFIG_FB_SYS_FOPS is not set
687CONFIG_FB_DEFERRED_IO=y
688# CONFIG_FB_SVGALIB is not set
689# CONFIG_FB_MACMODES is not set
690# CONFIG_FB_BACKLIGHT is not set
691# CONFIG_FB_MODE_HELPERS is not set
692# CONFIG_FB_TILEBLITTING is not set
693
694#
695# Frame buffer hardware drivers
696#
697# CONFIG_FB_S1D13XXX is not set
698CONFIG_FB_OMAP=y
699# CONFIG_FB_OMAP_LCDC_EXTERNAL is not set
700# CONFIG_FB_OMAP_LCD_MIPID is not set
701CONFIG_FB_OMAP_BOOTLOADER_INIT=y
702CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=2
703# CONFIG_FB_OMAP_DMA_TUNE is not set
704# CONFIG_FB_VIRTUAL is not set
705
706#
707# Console display driver support
708#
709# CONFIG_VGA_CONSOLE is not set
710CONFIG_DUMMY_CONSOLE=y
711CONFIG_FRAMEBUFFER_CONSOLE=y
712# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
713CONFIG_FONTS=y
714# CONFIG_FONT_8x8 is not set
715# CONFIG_FONT_8x16 is not set
716# CONFIG_FONT_6x11 is not set
717# CONFIG_FONT_7x14 is not set
718# CONFIG_FONT_PEARL_8x8 is not set
719# CONFIG_FONT_ACORN_8x8 is not set
720CONFIG_FONT_MINI_4x6=y
721# CONFIG_FONT_CLEAN_4x6 is not set
722# CONFIG_FONT_CLEAN_5x8 is not set
723# CONFIG_FONT_SUN8x16 is not set
724# CONFIG_FONT_SUN12x22 is not set
725# CONFIG_FONT_10x18 is not set
726CONFIG_LOGO=y
727# CONFIG_LOGO_LINUX_MONO is not set
728# CONFIG_LOGO_LINUX_VGA16 is not set
729CONFIG_LOGO_LINUX_CLUT224=y
730
731#
732# Sound
733#
734CONFIG_SOUND=y
735
736#
737# Advanced Linux Sound Architecture
738#
739CONFIG_SND=y
740CONFIG_SND_TIMER=y
741CONFIG_SND_PCM=y
742# CONFIG_SND_SEQUENCER is not set
743CONFIG_SND_OSSEMUL=y
744CONFIG_SND_MIXER_OSS=y
745CONFIG_SND_PCM_OSS=y
746CONFIG_SND_PCM_OSS_PLUGINS=y
747# CONFIG_SND_DYNAMIC_MINORS is not set
748# CONFIG_SND_SUPPORT_OLD_API is not set
749# CONFIG_SND_VERBOSE_PROCFS is not set
750# CONFIG_SND_VERBOSE_PRINTK is not set
751# CONFIG_SND_DEBUG is not set
752
753#
754# Generic devices
755#
756# CONFIG_SND_DUMMY is not set
757# CONFIG_SND_MTPAV is not set
758# CONFIG_SND_SERIAL_U16550 is not set
759# CONFIG_SND_MPU401 is not set
760
761#
762# ALSA ARM devices
763#
764# CONFIG_SND_OMAP_AIC23 is not set
765# CONFIG_SND_OMAP_TSC2101 is not set
766CONFIG_SND_SX1=y
767# CONFIG_SND_OMAP_TSC2102 is not set
768# CONFIG_SND_OMAP24XX_EAC is not set
769
770#
771# System on Chip audio support
772#
773# CONFIG_SND_SOC is not set
774
775#
776# Open Sound System
777#
778# CONFIG_SOUND_PRIME is not set
779
780#
781# HID Devices
782#
783CONFIG_HID=y
784# CONFIG_HID_DEBUG is not set
785
786#
787# USB support
788#
789CONFIG_USB_ARCH_HAS_HCD=y
790CONFIG_USB_ARCH_HAS_OHCI=y
791# CONFIG_USB_ARCH_HAS_EHCI is not set
792# CONFIG_USB is not set
793# CONFIG_USB_MUSB_HDRC is not set
794# CONFIG_USB_GADGET_MUSB_HDRC is not set
795
796#
797# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
798#
799
800#
801# USB Gadget Support
802#
803CONFIG_USB_GADGET=y
804# CONFIG_USB_GADGET_DEBUG_FILES is not set
805CONFIG_USB_GADGET_SELECTED=y
806# CONFIG_USB_GADGET_FSL_USB2 is not set
807# CONFIG_USB_GADGET_NET2280 is not set
808# CONFIG_USB_GADGET_PXA2XX is not set
809# CONFIG_USB_GADGET_GOKU is not set
810# CONFIG_USB_GADGET_LH7A40X is not set
811CONFIG_USB_GADGET_OMAP=y
812CONFIG_USB_OMAP=y
813# CONFIG_USB_GADGET_AT91 is not set
814# CONFIG_USB_GADGET_DUMMY_HCD is not set
815# CONFIG_USB_GADGET_DUALSPEED is not set
816# CONFIG_USB_ZERO is not set
817CONFIG_USB_ETH=y
818CONFIG_USB_ETH_RNDIS=y
819# CONFIG_USB_GADGETFS is not set
820# CONFIG_USB_FILE_STORAGE is not set
821# CONFIG_USB_G_SERIAL is not set
822# CONFIG_USB_MIDI_GADGET is not set
823CONFIG_MMC=y
824# CONFIG_MMC_DEBUG is not set
825# CONFIG_MMC_UNSAFE_RESUME is not set
826
827#
828# MMC/SD Card Drivers
829#
830CONFIG_MMC_BLOCK=y
831
832#
833# MMC/SD Host Controller Drivers
834#
835CONFIG_MMC_OMAP=y
836
837#
838# Real Time Clock
839#
840CONFIG_RTC_LIB=y
841CONFIG_RTC_CLASS=y
842CONFIG_RTC_HCTOSYS=y
843CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
844# CONFIG_RTC_DEBUG is not set
845
846#
847# RTC interfaces
848#
849CONFIG_RTC_INTF_SYSFS=y
850CONFIG_RTC_INTF_PROC=y
851CONFIG_RTC_INTF_DEV=y
852# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
853# CONFIG_RTC_DRV_TEST is not set
854
855#
856# I2C RTC drivers
857#
858# CONFIG_RTC_DRV_DS1307 is not set
859# CONFIG_RTC_DRV_DS1672 is not set
860# CONFIG_RTC_DRV_MAX6900 is not set
861# CONFIG_RTC_DRV_RS5C372 is not set
862# CONFIG_RTC_DRV_ISL1208 is not set
863# CONFIG_RTC_DRV_X1205 is not set
864# CONFIG_RTC_DRV_PCF8563 is not set
865# CONFIG_RTC_DRV_PCF8583 is not set
866
867#
868# SPI RTC drivers
869#
870
871#
872# Platform RTC drivers
873#
874# CONFIG_RTC_DRV_CMOS is not set
875# CONFIG_RTC_DRV_DS1553 is not set
876# CONFIG_RTC_DRV_DS1742 is not set
877# CONFIG_RTC_DRV_M48T86 is not set
878# CONFIG_RTC_DRV_V3020 is not set
879
880#
881# on-CPU RTC drivers
882#
883CONFIG_RTC_DRV_OMAP=y
884
885#
886# CBUS support
887#
888# CONFIG_CBUS is not set
889
890#
891# File systems
892#
893CONFIG_EXT2_FS=y
894# CONFIG_EXT2_FS_XATTR is not set
895# CONFIG_EXT2_FS_XIP is not set
896# CONFIG_EXT3_FS is not set
897# CONFIG_EXT4DEV_FS is not set
898# CONFIG_REISERFS_FS is not set
899# CONFIG_JFS_FS is not set
900# CONFIG_FS_POSIX_ACL is not set
901# CONFIG_XFS_FS is not set
902# CONFIG_GFS2_FS is not set
903# CONFIG_OCFS2_FS is not set
904# CONFIG_MINIX_FS is not set
905# CONFIG_ROMFS_FS is not set
906CONFIG_INOTIFY=y
907CONFIG_INOTIFY_USER=y
908# CONFIG_QUOTA is not set
909# CONFIG_DNOTIFY is not set
910# CONFIG_AUTOFS_FS is not set
911# CONFIG_AUTOFS4_FS is not set
912# CONFIG_FUSE_FS is not set
913
914#
915# CD-ROM/DVD Filesystems
916#
917# CONFIG_ISO9660_FS is not set
918# CONFIG_UDF_FS is not set
919
920#
921# DOS/FAT/NT Filesystems
922#
923CONFIG_FAT_FS=y
924CONFIG_MSDOS_FS=y
925CONFIG_VFAT_FS=y
926CONFIG_FAT_DEFAULT_CODEPAGE=866
927CONFIG_FAT_DEFAULT_IOCHARSET="koi8-r"
928# CONFIG_NTFS_FS is not set
929
930#
931# Pseudo filesystems
932#
933CONFIG_PROC_FS=y
934CONFIG_PROC_SYSCTL=y
935CONFIG_SYSFS=y
936CONFIG_TMPFS=y
937# CONFIG_TMPFS_POSIX_ACL is not set
938# CONFIG_HUGETLB_PAGE is not set
939CONFIG_RAMFS=y
940# CONFIG_CONFIGFS_FS is not set
941
942#
943# Miscellaneous filesystems
944#
945# CONFIG_ADFS_FS is not set
946# CONFIG_AFFS_FS is not set
947# CONFIG_HFS_FS is not set
948# CONFIG_HFSPLUS_FS is not set
949# CONFIG_BEFS_FS is not set
950# CONFIG_BFS_FS is not set
951# CONFIG_EFS_FS is not set
952CONFIG_CRAMFS=y
953# CONFIG_VXFS_FS is not set
954# CONFIG_HPFS_FS is not set
955# CONFIG_QNX4FS_FS is not set
956# CONFIG_SYSV_FS is not set
957# CONFIG_UFS_FS is not set
958
959#
960# Network File Systems
961#
962CONFIG_NFS_FS=y
963# CONFIG_NFS_V3 is not set
964# CONFIG_NFS_V4 is not set
965# CONFIG_NFS_DIRECTIO is not set
966# CONFIG_NFSD is not set
967CONFIG_ROOT_NFS=y
968CONFIG_LOCKD=y
969CONFIG_NFS_COMMON=y
970CONFIG_SUNRPC=y
971# CONFIG_SUNRPC_BIND34 is not set
972# CONFIG_RPCSEC_GSS_KRB5 is not set
973# CONFIG_RPCSEC_GSS_SPKM3 is not set
974# CONFIG_SMB_FS is not set
975# CONFIG_CIFS is not set
976# CONFIG_NCP_FS is not set
977# CONFIG_CODA_FS is not set
978# CONFIG_AFS_FS is not set
979# CONFIG_9P_FS is not set
980
981#
982# Partition Types
983#
984CONFIG_PARTITION_ADVANCED=y
985# CONFIG_ACORN_PARTITION is not set
986# CONFIG_OSF_PARTITION is not set
987# CONFIG_AMIGA_PARTITION is not set
988# CONFIG_ATARI_PARTITION is not set
989# CONFIG_MAC_PARTITION is not set
990CONFIG_MSDOS_PARTITION=y
991# CONFIG_BSD_DISKLABEL is not set
992# CONFIG_MINIX_SUBPARTITION is not set
993# CONFIG_SOLARIS_X86_PARTITION is not set
994# CONFIG_UNIXWARE_DISKLABEL is not set
995# CONFIG_LDM_PARTITION is not set
996# CONFIG_SGI_PARTITION is not set
997# CONFIG_ULTRIX_PARTITION is not set
998# CONFIG_SUN_PARTITION is not set
999# CONFIG_KARMA_PARTITION is not set
1000# CONFIG_EFI_PARTITION is not set
1001# CONFIG_SYSV68_PARTITION is not set
1002
1003#
1004# Native Language Support
1005#
1006CONFIG_NLS=y
1007CONFIG_NLS_DEFAULT="iso8859-1"
1008CONFIG_NLS_CODEPAGE_437=y
1009# CONFIG_NLS_CODEPAGE_737 is not set
1010# CONFIG_NLS_CODEPAGE_775 is not set
1011# CONFIG_NLS_CODEPAGE_850 is not set
1012# CONFIG_NLS_CODEPAGE_852 is not set
1013# CONFIG_NLS_CODEPAGE_855 is not set
1014# CONFIG_NLS_CODEPAGE_857 is not set
1015# CONFIG_NLS_CODEPAGE_860 is not set
1016# CONFIG_NLS_CODEPAGE_861 is not set
1017# CONFIG_NLS_CODEPAGE_862 is not set
1018# CONFIG_NLS_CODEPAGE_863 is not set
1019# CONFIG_NLS_CODEPAGE_864 is not set
1020# CONFIG_NLS_CODEPAGE_865 is not set
1021CONFIG_NLS_CODEPAGE_866=y
1022# CONFIG_NLS_CODEPAGE_869 is not set
1023# CONFIG_NLS_CODEPAGE_936 is not set
1024# CONFIG_NLS_CODEPAGE_950 is not set
1025# CONFIG_NLS_CODEPAGE_932 is not set
1026# CONFIG_NLS_CODEPAGE_949 is not set
1027# CONFIG_NLS_CODEPAGE_874 is not set
1028# CONFIG_NLS_ISO8859_8 is not set
1029# CONFIG_NLS_CODEPAGE_1250 is not set
1030CONFIG_NLS_CODEPAGE_1251=y
1031# CONFIG_NLS_ASCII is not set
1032CONFIG_NLS_ISO8859_1=y
1033# CONFIG_NLS_ISO8859_2 is not set
1034# CONFIG_NLS_ISO8859_3 is not set
1035# CONFIG_NLS_ISO8859_4 is not set
1036CONFIG_NLS_ISO8859_5=y
1037# CONFIG_NLS_ISO8859_6 is not set
1038# CONFIG_NLS_ISO8859_7 is not set
1039# CONFIG_NLS_ISO8859_9 is not set
1040# CONFIG_NLS_ISO8859_13 is not set
1041# CONFIG_NLS_ISO8859_14 is not set
1042# CONFIG_NLS_ISO8859_15 is not set
1043CONFIG_NLS_KOI8_R=y
1044# CONFIG_NLS_KOI8_U is not set
1045CONFIG_NLS_UTF8=y
1046
1047#
1048# Distributed Lock Manager
1049#
1050# CONFIG_DLM is not set
1051
1052#
1053# Profiling support
1054#
1055CONFIG_PROFILING=y
1056CONFIG_OPROFILE=y
1057
1058#
1059# Kernel hacking
1060#
1061# CONFIG_PRINTK_TIME is not set
1062# CONFIG_ENABLE_MUST_CHECK is not set
1063# CONFIG_MAGIC_SYSRQ is not set
1064# CONFIG_UNUSED_SYMBOLS is not set
1065# CONFIG_DEBUG_FS is not set
1066# CONFIG_HEADERS_CHECK is not set
1067CONFIG_DEBUG_KERNEL=y
1068# CONFIG_DEBUG_SHIRQ is not set
1069# CONFIG_DETECT_SOFTLOCKUP is not set
1070# CONFIG_SCHEDSTATS is not set
1071# CONFIG_TIMER_STATS is not set
1072CONFIG_DEBUG_PREEMPT=y
1073# CONFIG_DEBUG_RT_MUTEXES is not set
1074# CONFIG_RT_MUTEX_TESTER is not set
1075# CONFIG_DEBUG_SPINLOCK is not set
1076# CONFIG_DEBUG_MUTEXES is not set
1077# CONFIG_DEBUG_LOCK_ALLOC is not set
1078# CONFIG_PROVE_LOCKING is not set
1079# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1080# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1081# CONFIG_DEBUG_KOBJECT is not set
1082# CONFIG_DEBUG_BUGVERBOSE is not set
1083# CONFIG_DEBUG_INFO is not set
1084# CONFIG_DEBUG_VM is not set
1085# CONFIG_DEBUG_LIST is not set
1086CONFIG_FRAME_POINTER=y
1087CONFIG_FORCED_INLINING=y
1088# CONFIG_RCU_TORTURE_TEST is not set
1089# CONFIG_FAULT_INJECTION is not set
1090# CONFIG_DEBUG_USER is not set
1091# CONFIG_DEBUG_ERRORS is not set
1092# CONFIG_DEBUG_LL is not set
1093
1094#
1095# Security options
1096#
1097# CONFIG_KEYS is not set
1098# CONFIG_SECURITY is not set
1099
1100#
1101# Cryptographic options
1102#
1103# CONFIG_CRYPTO is not set
1104
1105#
1106# Library routines
1107#
1108CONFIG_BITREVERSE=y
1109CONFIG_CRC_CCITT=y
1110CONFIG_CRC16=y
1111# CONFIG_CRC_ITU_T is not set
1112CONFIG_CRC32=y
1113CONFIG_LIBCRC32C=y
1114CONFIG_ZLIB_INFLATE=y
1115CONFIG_PLIST=y
1116CONFIG_HAS_IOMEM=y
1117CONFIG_HAS_IOPORT=y
1118CONFIG_HAS_DMA=y
diff --git a/arch/arm/include/asm/byteorder.h b/arch/arm/include/asm/byteorder.h
index 4fbfb22f65a0..d04a7a2bc2e9 100644
--- a/arch/arm/include/asm/byteorder.h
+++ b/arch/arm/include/asm/byteorder.h
@@ -18,7 +18,15 @@
18#include <linux/compiler.h> 18#include <linux/compiler.h>
19#include <asm/types.h> 19#include <asm/types.h>
20 20
21static inline __attribute_const__ __u32 ___arch__swab32(__u32 x) 21#ifdef __ARMEB__
22# define __BIG_ENDIAN
23#else
24# define __LITTLE_ENDIAN
25#endif
26
27#define __SWAB_64_THRU_32__
28
29static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
22{ 30{
23 __u32 t; 31 __u32 t;
24 32
@@ -40,19 +48,8 @@ static inline __attribute_const__ __u32 ___arch__swab32(__u32 x)
40 48
41 return x; 49 return x;
42} 50}
51#define __arch_swab32 __arch_swab32
43 52
44#define __arch__swab32(x) ___arch__swab32(x) 53#include <linux/byteorder.h>
45
46#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
47# define __BYTEORDER_HAS_U64__
48# define __SWAB_64_THRU_32__
49#endif
50
51#ifdef __ARMEB__
52#include <linux/byteorder/big_endian.h>
53#else
54#include <linux/byteorder/little_endian.h>
55#endif
56 54
57#endif 55#endif
58
diff --git a/arch/arm/lib/sha1.S b/arch/arm/lib/sha1.S
index ff6ece487ffc..67c2bf4774b7 100644
--- a/arch/arm/lib/sha1.S
+++ b/arch/arm/lib/sha1.S
@@ -29,7 +29,7 @@ ENTRY(sha_transform)
29 stmfd sp!, {r4 - r8, lr} 29 stmfd sp!, {r4 - r8, lr}
30 30
31 @ for (i = 0; i < 16; i++) 31 @ for (i = 0; i < 16; i++)
32 @ W[i] = be32_to_cpu(in[i]); */ 32 @ W[i] = be32_to_cpu(in[i]);
33 33
34#ifdef __ARMEB__ 34#ifdef __ARMEB__
35 mov r4, r0 35 mov r4, r0
diff --git a/arch/arm/mach-footbridge/time.c b/arch/arm/mach-footbridge/time.c
index fd9a7c11d62d..004819ea85c8 100644
--- a/arch/arm/mach-footbridge/time.c
+++ b/arch/arm/mach-footbridge/time.c
@@ -49,12 +49,12 @@ static unsigned long __init get_isa_cmos_time(void)
49 } while (sec != CMOS_READ(RTC_SECONDS)); 49 } while (sec != CMOS_READ(RTC_SECONDS));
50 50
51 if (!(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) || RTC_ALWAYS_BCD) { 51 if (!(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
52 BCD_TO_BIN(sec); 52 sec = bcd2bin(sec);
53 BCD_TO_BIN(min); 53 min = bcd2bin(min);
54 BCD_TO_BIN(hour); 54 hour = bcd2bin(hour);
55 BCD_TO_BIN(day); 55 day = bcd2bin(day);
56 BCD_TO_BIN(mon); 56 mon = bcd2bin(mon);
57 BCD_TO_BIN(year); 57 year = bcd2bin(year);
58 } 58 }
59 if ((year += 1900) < 1970) 59 if ((year += 1900) < 1970)
60 year += 100; 60 year += 100;
@@ -76,7 +76,7 @@ static int set_isa_cmos_time(void)
76 76
77 cmos_minutes = CMOS_READ(RTC_MINUTES); 77 cmos_minutes = CMOS_READ(RTC_MINUTES);
78 if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) 78 if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD)
79 BCD_TO_BIN(cmos_minutes); 79 cmos_minutes = bcd2bin(cmos_minutes);
80 80
81 /* 81 /*
82 * since we're only adjusting minutes and seconds, 82 * since we're only adjusting minutes and seconds,
@@ -92,8 +92,8 @@ static int set_isa_cmos_time(void)
92 92
93 if (abs(real_minutes - cmos_minutes) < 30) { 93 if (abs(real_minutes - cmos_minutes) < 30) {
94 if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) { 94 if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
95 BIN_TO_BCD(real_seconds); 95 real_seconds = bin2bcd(real_seconds);
96 BIN_TO_BCD(real_minutes); 96 real_minutes = bin2bcd(real_minutes);
97 } 97 }
98 CMOS_WRITE(real_seconds,RTC_SECONDS); 98 CMOS_WRITE(real_seconds,RTC_SECONDS);
99 CMOS_WRITE(real_minutes,RTC_MINUTES); 99 CMOS_WRITE(real_minutes,RTC_MINUTES);
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
index 5965cf09f8c4..90ae0ef37d66 100644
--- a/arch/arm/mach-omap1/clock.c
+++ b/arch/arm/mach-omap1/clock.c
@@ -201,7 +201,7 @@ static int calc_dsor_exp(struct clk *clk, unsigned long rate)
201 return -EINVAL; 201 return -EINVAL;
202 202
203 parent = clk->parent; 203 parent = clk->parent;
204 if (unlikely(parent == 0)) 204 if (unlikely(parent == NULL))
205 return -EIO; 205 return -EIO;
206 206
207 realrate = parent->rate; 207 realrate = parent->rate;
@@ -499,7 +499,7 @@ static int omap1_clk_enable_generic(struct clk *clk)
499 if (clk->flags & ALWAYS_ENABLED) 499 if (clk->flags & ALWAYS_ENABLED)
500 return 0; 500 return 0;
501 501
502 if (unlikely(clk->enable_reg == 0)) { 502 if (unlikely(clk->enable_reg == NULL)) {
503 printk(KERN_ERR "clock.c: Enable for %s without enable code\n", 503 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
504 clk->name); 504 clk->name);
505 return -EINVAL; 505 return -EINVAL;
@@ -535,7 +535,7 @@ static void omap1_clk_disable_generic(struct clk *clk)
535 __u16 regval16; 535 __u16 regval16;
536 __u32 regval32; 536 __u32 regval32;
537 537
538 if (clk->enable_reg == 0) 538 if (clk->enable_reg == NULL)
539 return; 539 return;
540 540
541 if (clk->flags & ENABLE_REG_32BIT) { 541 if (clk->flags & ENABLE_REG_32BIT) {
@@ -577,7 +577,7 @@ static long omap1_clk_round_rate(struct clk *clk, unsigned long rate)
577 return clk->parent->rate / (1 << dsor_exp); 577 return clk->parent->rate / (1 << dsor_exp);
578 } 578 }
579 579
580 if(clk->round_rate != 0) 580 if (clk->round_rate != NULL)
581 return clk->round_rate(clk, rate); 581 return clk->round_rate(clk, rate);
582 582
583 return clk->rate; 583 return clk->rate;
@@ -625,7 +625,7 @@ static void __init omap1_clk_disable_unused(struct clk *clk)
625 625
626 /* Clocks in the DSP domain need api_ck. Just assume bootloader 626 /* Clocks in the DSP domain need api_ck. Just assume bootloader
627 * has not enabled any DSP clocks */ 627 * has not enabled any DSP clocks */
628 if ((u32)clk->enable_reg == DSP_IDLECT2) { 628 if (clk->enable_reg == DSP_IDLECT2) {
629 printk(KERN_INFO "Skipping reset check for DSP domain " 629 printk(KERN_INFO "Skipping reset check for DSP domain "
630 "clock \"%s\"\n", clk->name); 630 "clock \"%s\"\n", clk->name);
631 return; 631 return;
diff --git a/arch/arm/mach-omap1/clock.h b/arch/arm/mach-omap1/clock.h
index 6eadf72828d8..5635b511ab6f 100644
--- a/arch/arm/mach-omap1/clock.h
+++ b/arch/arm/mach-omap1/clock.h
@@ -324,7 +324,7 @@ static struct clk dspper_ck = {
324 .parent = &ck_dpll1, 324 .parent = &ck_dpll1,
325 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 325 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
326 RATE_CKCTL | VIRTUAL_IO_ADDRESS, 326 RATE_CKCTL | VIRTUAL_IO_ADDRESS,
327 .enable_reg = (void __iomem *)DSP_IDLECT2, 327 .enable_reg = DSP_IDLECT2,
328 .enable_bit = EN_PERCK, 328 .enable_bit = EN_PERCK,
329 .rate_offset = CKCTL_PERDIV_OFFSET, 329 .rate_offset = CKCTL_PERDIV_OFFSET,
330 .recalc = &omap1_ckctl_recalc_dsp_domain, 330 .recalc = &omap1_ckctl_recalc_dsp_domain,
@@ -338,7 +338,7 @@ static struct clk dspxor_ck = {
338 .parent = &ck_ref, 338 .parent = &ck_ref,
339 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 339 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
340 VIRTUAL_IO_ADDRESS, 340 VIRTUAL_IO_ADDRESS,
341 .enable_reg = (void __iomem *)DSP_IDLECT2, 341 .enable_reg = DSP_IDLECT2,
342 .enable_bit = EN_XORPCK, 342 .enable_bit = EN_XORPCK,
343 .recalc = &followparent_recalc, 343 .recalc = &followparent_recalc,
344 .enable = &omap1_clk_enable_dsp_domain, 344 .enable = &omap1_clk_enable_dsp_domain,
@@ -350,7 +350,7 @@ static struct clk dsptim_ck = {
350 .parent = &ck_ref, 350 .parent = &ck_ref,
351 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 351 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
352 VIRTUAL_IO_ADDRESS, 352 VIRTUAL_IO_ADDRESS,
353 .enable_reg = (void __iomem *)DSP_IDLECT2, 353 .enable_reg = DSP_IDLECT2,
354 .enable_bit = EN_DSPTIMCK, 354 .enable_bit = EN_DSPTIMCK,
355 .recalc = &followparent_recalc, 355 .recalc = &followparent_recalc,
356 .enable = &omap1_clk_enable_dsp_domain, 356 .enable = &omap1_clk_enable_dsp_domain,
diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c
index 826010d5d014..afb5789f94f9 100644
--- a/arch/arm/mach-omap1/mcbsp.c
+++ b/arch/arm/mach-omap1/mcbsp.c
@@ -159,7 +159,7 @@ static struct omap_mcbsp_ops omap1_mcbsp_ops = {
159#ifdef CONFIG_ARCH_OMAP730 159#ifdef CONFIG_ARCH_OMAP730
160static struct omap_mcbsp_platform_data omap730_mcbsp_pdata[] = { 160static struct omap_mcbsp_platform_data omap730_mcbsp_pdata[] = {
161 { 161 {
162 .virt_base = io_p2v(OMAP730_MCBSP1_BASE), 162 .phys_base = OMAP730_MCBSP1_BASE,
163 .dma_rx_sync = OMAP_DMA_MCBSP1_RX, 163 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
164 .dma_tx_sync = OMAP_DMA_MCBSP1_TX, 164 .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
165 .rx_irq = INT_730_McBSP1RX, 165 .rx_irq = INT_730_McBSP1RX,
@@ -167,7 +167,7 @@ static struct omap_mcbsp_platform_data omap730_mcbsp_pdata[] = {
167 .ops = &omap1_mcbsp_ops, 167 .ops = &omap1_mcbsp_ops,
168 }, 168 },
169 { 169 {
170 .virt_base = io_p2v(OMAP730_MCBSP2_BASE), 170 .phys_base = OMAP730_MCBSP2_BASE,
171 .dma_rx_sync = OMAP_DMA_MCBSP3_RX, 171 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
172 .dma_tx_sync = OMAP_DMA_MCBSP3_TX, 172 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
173 .rx_irq = INT_730_McBSP2RX, 173 .rx_irq = INT_730_McBSP2RX,
@@ -184,7 +184,7 @@ static struct omap_mcbsp_platform_data omap730_mcbsp_pdata[] = {
184#ifdef CONFIG_ARCH_OMAP15XX 184#ifdef CONFIG_ARCH_OMAP15XX
185static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = { 185static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = {
186 { 186 {
187 .virt_base = OMAP1510_MCBSP1_BASE, 187 .phys_base = OMAP1510_MCBSP1_BASE,
188 .dma_rx_sync = OMAP_DMA_MCBSP1_RX, 188 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
189 .dma_tx_sync = OMAP_DMA_MCBSP1_TX, 189 .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
190 .rx_irq = INT_McBSP1RX, 190 .rx_irq = INT_McBSP1RX,
@@ -193,7 +193,7 @@ static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = {
193 .clk_name = "mcbsp_clk", 193 .clk_name = "mcbsp_clk",
194 }, 194 },
195 { 195 {
196 .virt_base = io_p2v(OMAP1510_MCBSP2_BASE), 196 .phys_base = OMAP1510_MCBSP2_BASE,
197 .dma_rx_sync = OMAP_DMA_MCBSP2_RX, 197 .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
198 .dma_tx_sync = OMAP_DMA_MCBSP2_TX, 198 .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
199 .rx_irq = INT_1510_SPI_RX, 199 .rx_irq = INT_1510_SPI_RX,
@@ -201,7 +201,7 @@ static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = {
201 .ops = &omap1_mcbsp_ops, 201 .ops = &omap1_mcbsp_ops,
202 }, 202 },
203 { 203 {
204 .virt_base = OMAP1510_MCBSP3_BASE, 204 .phys_base = OMAP1510_MCBSP3_BASE,
205 .dma_rx_sync = OMAP_DMA_MCBSP3_RX, 205 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
206 .dma_tx_sync = OMAP_DMA_MCBSP3_TX, 206 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
207 .rx_irq = INT_McBSP3RX, 207 .rx_irq = INT_McBSP3RX,
@@ -219,7 +219,7 @@ static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = {
219#ifdef CONFIG_ARCH_OMAP16XX 219#ifdef CONFIG_ARCH_OMAP16XX
220static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = { 220static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = {
221 { 221 {
222 .virt_base = OMAP1610_MCBSP1_BASE, 222 .phys_base = OMAP1610_MCBSP1_BASE,
223 .dma_rx_sync = OMAP_DMA_MCBSP1_RX, 223 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
224 .dma_tx_sync = OMAP_DMA_MCBSP1_TX, 224 .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
225 .rx_irq = INT_McBSP1RX, 225 .rx_irq = INT_McBSP1RX,
@@ -228,7 +228,7 @@ static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = {
228 .clk_name = "mcbsp_clk", 228 .clk_name = "mcbsp_clk",
229 }, 229 },
230 { 230 {
231 .virt_base = io_p2v(OMAP1610_MCBSP2_BASE), 231 .phys_base = OMAP1610_MCBSP2_BASE,
232 .dma_rx_sync = OMAP_DMA_MCBSP2_RX, 232 .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
233 .dma_tx_sync = OMAP_DMA_MCBSP2_TX, 233 .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
234 .rx_irq = INT_1610_McBSP2_RX, 234 .rx_irq = INT_1610_McBSP2_RX,
@@ -236,7 +236,7 @@ static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = {
236 .ops = &omap1_mcbsp_ops, 236 .ops = &omap1_mcbsp_ops,
237 }, 237 },
238 { 238 {
239 .virt_base = OMAP1610_MCBSP3_BASE, 239 .phys_base = OMAP1610_MCBSP3_BASE,
240 .dma_rx_sync = OMAP_DMA_MCBSP3_RX, 240 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
241 .dma_tx_sync = OMAP_DMA_MCBSP3_TX, 241 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
242 .rx_irq = INT_McBSP3RX, 242 .rx_irq = INT_McBSP3RX,
diff --git a/arch/arm/mach-omap1/serial.c b/arch/arm/mach-omap1/serial.c
index 0e25a996bb4c..4965986b4ad5 100644
--- a/arch/arm/mach-omap1/serial.c
+++ b/arch/arm/mach-omap1/serial.c
@@ -67,8 +67,8 @@ static void __init omap_serial_reset(struct plat_serial8250_port *p)
67 67
68static struct plat_serial8250_port serial_platform_data[] = { 68static struct plat_serial8250_port serial_platform_data[] = {
69 { 69 {
70 .membase = (char*)IO_ADDRESS(OMAP_UART1_BASE), 70 .membase = IO_ADDRESS(OMAP_UART1_BASE),
71 .mapbase = (unsigned long)OMAP_UART1_BASE, 71 .mapbase = OMAP_UART1_BASE,
72 .irq = INT_UART1, 72 .irq = INT_UART1,
73 .flags = UPF_BOOT_AUTOCONF, 73 .flags = UPF_BOOT_AUTOCONF,
74 .iotype = UPIO_MEM, 74 .iotype = UPIO_MEM,
@@ -76,8 +76,8 @@ static struct plat_serial8250_port serial_platform_data[] = {
76 .uartclk = OMAP16XX_BASE_BAUD * 16, 76 .uartclk = OMAP16XX_BASE_BAUD * 16,
77 }, 77 },
78 { 78 {
79 .membase = (char*)IO_ADDRESS(OMAP_UART2_BASE), 79 .membase = IO_ADDRESS(OMAP_UART2_BASE),
80 .mapbase = (unsigned long)OMAP_UART2_BASE, 80 .mapbase = OMAP_UART2_BASE,
81 .irq = INT_UART2, 81 .irq = INT_UART2,
82 .flags = UPF_BOOT_AUTOCONF, 82 .flags = UPF_BOOT_AUTOCONF,
83 .iotype = UPIO_MEM, 83 .iotype = UPIO_MEM,
@@ -85,8 +85,8 @@ static struct plat_serial8250_port serial_platform_data[] = {
85 .uartclk = OMAP16XX_BASE_BAUD * 16, 85 .uartclk = OMAP16XX_BASE_BAUD * 16,
86 }, 86 },
87 { 87 {
88 .membase = (char*)IO_ADDRESS(OMAP_UART3_BASE), 88 .membase = IO_ADDRESS(OMAP_UART3_BASE),
89 .mapbase = (unsigned long)OMAP_UART3_BASE, 89 .mapbase = OMAP_UART3_BASE,
90 .irq = INT_UART3, 90 .irq = INT_UART3,
91 .flags = UPF_BOOT_AUTOCONF, 91 .flags = UPF_BOOT_AUTOCONF,
92 .iotype = UPIO_MEM, 92 .iotype = UPIO_MEM,
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index d4d6385cad7c..b72ca13b3acb 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -103,7 +103,7 @@ static struct resource sdp2430_smc91x_resources[] = {
103 [1] = { 103 [1] = {
104 .start = OMAP_GPIO_IRQ(OMAP24XX_ETHR_GPIO_IRQ), 104 .start = OMAP_GPIO_IRQ(OMAP24XX_ETHR_GPIO_IRQ),
105 .end = OMAP_GPIO_IRQ(OMAP24XX_ETHR_GPIO_IRQ), 105 .end = OMAP_GPIO_IRQ(OMAP24XX_ETHR_GPIO_IRQ),
106 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, 106 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
107 }, 107 },
108}; 108};
109 109
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index aa9b37370d44..57c4405cceda 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -278,7 +278,7 @@ int _omap2_clk_enable(struct clk *clk)
278 if (clk->enable) 278 if (clk->enable)
279 return clk->enable(clk); 279 return clk->enable(clk);
280 280
281 if (unlikely(clk->enable_reg == 0)) { 281 if (unlikely(clk->enable_reg == NULL)) {
282 printk(KERN_ERR "clock.c: Enable for %s without enable code\n", 282 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
283 clk->name); 283 clk->name);
284 return 0; /* REVISIT: -EINVAL */ 284 return 0; /* REVISIT: -EINVAL */
@@ -310,7 +310,7 @@ void _omap2_clk_disable(struct clk *clk)
310 return; 310 return;
311 } 311 }
312 312
313 if (clk->enable_reg == 0) { 313 if (clk->enable_reg == NULL) {
314 /* 314 /*
315 * 'Independent' here refers to a clock which is not 315 * 'Independent' here refers to a clock which is not
316 * controlled by its parent. 316 * controlled by its parent.
@@ -515,7 +515,7 @@ long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
515/* Given a clock and a rate apply a clock specific rounding function */ 515/* Given a clock and a rate apply a clock specific rounding function */
516long omap2_clk_round_rate(struct clk *clk, unsigned long rate) 516long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
517{ 517{
518 if (clk->round_rate != 0) 518 if (clk->round_rate != NULL)
519 return clk->round_rate(clk, rate); 519 return clk->round_rate(clk, rate);
520 520
521 if (clk->flags & RATE_FIXED) 521 if (clk->flags & RATE_FIXED)
@@ -604,7 +604,7 @@ u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
604 */ 604 */
605void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask) 605void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask)
606{ 606{
607 if (unlikely((clk->clksel_reg == 0) || (clk->clksel_mask == 0))) 607 if (unlikely((clk->clksel_reg == NULL) || (clk->clksel_mask == NULL)))
608 return NULL; 608 return NULL;
609 609
610 *field_mask = clk->clksel_mask; 610 *field_mask = clk->clksel_mask;
@@ -624,7 +624,7 @@ u32 omap2_clksel_get_divisor(struct clk *clk)
624 void __iomem *div_addr; 624 void __iomem *div_addr;
625 625
626 div_addr = omap2_get_clksel(clk, &field_mask); 626 div_addr = omap2_get_clksel(clk, &field_mask);
627 if (div_addr == 0) 627 if (div_addr == NULL)
628 return 0; 628 return 0;
629 629
630 field_val = __raw_readl(div_addr) & field_mask; 630 field_val = __raw_readl(div_addr) & field_mask;
@@ -643,7 +643,7 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
643 return -EINVAL; 643 return -EINVAL;
644 644
645 div_addr = omap2_get_clksel(clk, &field_mask); 645 div_addr = omap2_get_clksel(clk, &field_mask);
646 if (div_addr == 0) 646 if (div_addr == NULL)
647 return -EINVAL; 647 return -EINVAL;
648 648
649 field_val = omap2_divisor_to_clksel(clk, new_div); 649 field_val = omap2_divisor_to_clksel(clk, new_div);
@@ -681,7 +681,7 @@ int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
681 return -EINVAL; 681 return -EINVAL;
682 682
683 /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */ 683 /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
684 if (clk->set_rate != 0) 684 if (clk->set_rate != NULL)
685 ret = clk->set_rate(clk, rate); 685 ret = clk->set_rate(clk, rate);
686 686
687 if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES))) 687 if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
@@ -702,7 +702,7 @@ static u32 omap2_clksel_get_src_field(void __iomem **src_addr,
702 const struct clksel_rate *clkr; 702 const struct clksel_rate *clkr;
703 703
704 *parent_div = 0; 704 *parent_div = 0;
705 *src_addr = 0; 705 *src_addr = NULL;
706 706
707 clks = omap2_get_clksel_by_parent(clk, src_clk); 707 clks = omap2_get_clksel_by_parent(clk, src_clk);
708 if (clks == NULL) 708 if (clks == NULL)
@@ -743,7 +743,7 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
743 743
744 field_val = omap2_clksel_get_src_field(&src_addr, new_parent, 744 field_val = omap2_clksel_get_src_field(&src_addr, new_parent,
745 &field_mask, clk, &parent_div); 745 &field_mask, clk, &parent_div);
746 if (src_addr == 0) 746 if (src_addr == NULL)
747 return -EINVAL; 747 return -EINVAL;
748 748
749 if (clk->usecount > 0) 749 if (clk->usecount > 0)
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h
index 87a44c715aa4..65fdf78c91e1 100644
--- a/arch/arm/mach-omap2/cm.h
+++ b/arch/arm/mach-omap2/cm.h
@@ -18,7 +18,7 @@
18 18
19#ifndef __ASSEMBLER__ 19#ifndef __ASSEMBLER__
20#define OMAP_CM_REGADDR(module, reg) \ 20#define OMAP_CM_REGADDR(module, reg) \
21 (void __iomem *)IO_ADDRESS(OMAP2_CM_BASE + (module) + (reg)) 21 IO_ADDRESS(OMAP2_CM_BASE + (module) + (reg))
22#else 22#else
23#define OMAP2420_CM_REGADDR(module, reg) \ 23#define OMAP2420_CM_REGADDR(module, reg) \
24 IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg)) 24 IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index f51d69bc457d..9b4e58ee2ca2 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -64,10 +64,8 @@ static struct resource gpmc_cs_mem[GPMC_CS_NUM];
64static DEFINE_SPINLOCK(gpmc_mem_lock); 64static DEFINE_SPINLOCK(gpmc_mem_lock);
65static unsigned gpmc_cs_map; 65static unsigned gpmc_cs_map;
66 66
67static void __iomem *gpmc_base = 67static void __iomem *gpmc_base = IO_ADDRESS(GPMC_BASE);
68 (void __iomem *) IO_ADDRESS(GPMC_BASE); 68static void __iomem *gpmc_cs_base = IO_ADDRESS(GPMC_BASE) + GPMC_CS0;
69static void __iomem *gpmc_cs_base =
70 (void __iomem *) IO_ADDRESS(GPMC_BASE) + GPMC_CS0;
71 69
72static struct clk *gpmc_fck; 70static struct clk *gpmc_fck;
73 71
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index a5d4526ac4d6..e53ebe7d58be 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -21,11 +21,11 @@
21#include <mach/cpu.h> 21#include <mach/cpu.h>
22 22
23#if defined(CONFIG_ARCH_OMAP2420) 23#if defined(CONFIG_ARCH_OMAP2420)
24#define TAP_BASE io_p2v(0x48014000) 24#define TAP_BASE IO_ADDRESS(0x48014000)
25#elif defined(CONFIG_ARCH_OMAP2430) 25#elif defined(CONFIG_ARCH_OMAP2430)
26#define TAP_BASE io_p2v(0x4900A000) 26#define TAP_BASE IO_ADDRESS(0x4900A000)
27#elif defined(CONFIG_ARCH_OMAP34XX) 27#elif defined(CONFIG_ARCH_OMAP34XX)
28#define TAP_BASE io_p2v(0x4830A000) 28#define TAP_BASE IO_ADDRESS(0x4830A000)
29#endif 29#endif
30 30
31#define OMAP_TAP_IDCODE 0x0204 31#define OMAP_TAP_IDCODE 0x0204
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 9ef15b31d8fc..742bd0070e63 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -32,7 +32,7 @@
32 * for each bank.. when in doubt, consult the TRM. 32 * for each bank.. when in doubt, consult the TRM.
33 */ 33 */
34static struct omap_irq_bank { 34static struct omap_irq_bank {
35 unsigned long base_reg; 35 void __iomem *base_reg;
36 unsigned int nr_irqs; 36 unsigned int nr_irqs;
37} __attribute__ ((aligned(4))) irq_banks[] = { 37} __attribute__ ((aligned(4))) irq_banks[] = {
38 { 38 {
@@ -94,7 +94,7 @@ static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
94 unsigned long tmp; 94 unsigned long tmp;
95 95
96 tmp = __raw_readl(bank->base_reg + INTC_REVISION) & 0xff; 96 tmp = __raw_readl(bank->base_reg + INTC_REVISION) & 0xff;
97 printk(KERN_INFO "IRQ: Found an INTC at 0x%08lx " 97 printk(KERN_INFO "IRQ: Found an INTC at 0x%p "
98 "(revision %ld.%ld) with %d interrupts\n", 98 "(revision %ld.%ld) with %d interrupts\n",
99 bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs); 99 bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
100 100
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index 27eb6e3ca926..709db03b9999 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -134,7 +134,7 @@ static struct omap_mcbsp_ops omap2_mcbsp_ops = {
134#ifdef CONFIG_ARCH_OMAP24XX 134#ifdef CONFIG_ARCH_OMAP24XX
135static struct omap_mcbsp_platform_data omap24xx_mcbsp_pdata[] = { 135static struct omap_mcbsp_platform_data omap24xx_mcbsp_pdata[] = {
136 { 136 {
137 .virt_base = IO_ADDRESS(OMAP24XX_MCBSP1_BASE), 137 .phys_base = OMAP24XX_MCBSP1_BASE,
138 .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX, 138 .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
139 .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, 139 .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
140 .rx_irq = INT_24XX_MCBSP1_IRQ_RX, 140 .rx_irq = INT_24XX_MCBSP1_IRQ_RX,
@@ -143,7 +143,7 @@ static struct omap_mcbsp_platform_data omap24xx_mcbsp_pdata[] = {
143 .clk_name = "mcbsp_clk", 143 .clk_name = "mcbsp_clk",
144 }, 144 },
145 { 145 {
146 .virt_base = IO_ADDRESS(OMAP24XX_MCBSP2_BASE), 146 .phys_base = OMAP24XX_MCBSP2_BASE,
147 .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX, 147 .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
148 .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, 148 .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
149 .rx_irq = INT_24XX_MCBSP2_IRQ_RX, 149 .rx_irq = INT_24XX_MCBSP2_IRQ_RX,
@@ -161,7 +161,7 @@ static struct omap_mcbsp_platform_data omap24xx_mcbsp_pdata[] = {
161#ifdef CONFIG_ARCH_OMAP34XX 161#ifdef CONFIG_ARCH_OMAP34XX
162static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { 162static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
163 { 163 {
164 .virt_base = IO_ADDRESS(OMAP34XX_MCBSP1_BASE), 164 .phys_base = OMAP34XX_MCBSP1_BASE,
165 .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX, 165 .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
166 .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, 166 .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
167 .rx_irq = INT_24XX_MCBSP1_IRQ_RX, 167 .rx_irq = INT_24XX_MCBSP1_IRQ_RX,
@@ -170,7 +170,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
170 .clk_name = "mcbsp_clk", 170 .clk_name = "mcbsp_clk",
171 }, 171 },
172 { 172 {
173 .virt_base = IO_ADDRESS(OMAP34XX_MCBSP2_BASE), 173 .phys_base = OMAP34XX_MCBSP2_BASE,
174 .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX, 174 .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
175 .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, 175 .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
176 .rx_irq = INT_24XX_MCBSP2_IRQ_RX, 176 .rx_irq = INT_24XX_MCBSP2_IRQ_RX,
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index eb9982fb21d5..e4dc4b17881d 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -18,7 +18,7 @@
18 18
19#ifndef __ASSEMBLER__ 19#ifndef __ASSEMBLER__
20#define OMAP_PRM_REGADDR(module, reg) \ 20#define OMAP_PRM_REGADDR(module, reg) \
21 (void __iomem *)IO_ADDRESS(OMAP2_PRM_BASE + (module) + (reg)) 21 IO_ADDRESS(OMAP2_PRM_BASE + (module) + (reg))
22#else 22#else
23#define OMAP2420_PRM_REGADDR(module, reg) \ 23#define OMAP2420_PRM_REGADDR(module, reg) \
24 IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg)) 24 IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index adc8a26a8fb0..69651cf08305 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -32,24 +32,24 @@ static struct clk * uart3_fck = NULL;
32 32
33static struct plat_serial8250_port serial_platform_data[] = { 33static struct plat_serial8250_port serial_platform_data[] = {
34 { 34 {
35 .membase = (char *)IO_ADDRESS(OMAP_UART1_BASE), 35 .membase = IO_ADDRESS(OMAP_UART1_BASE),
36 .mapbase = (unsigned long)OMAP_UART1_BASE, 36 .mapbase = OMAP_UART1_BASE,
37 .irq = 72, 37 .irq = 72,
38 .flags = UPF_BOOT_AUTOCONF, 38 .flags = UPF_BOOT_AUTOCONF,
39 .iotype = UPIO_MEM, 39 .iotype = UPIO_MEM,
40 .regshift = 2, 40 .regshift = 2,
41 .uartclk = OMAP16XX_BASE_BAUD * 16, 41 .uartclk = OMAP16XX_BASE_BAUD * 16,
42 }, { 42 }, {
43 .membase = (char *)IO_ADDRESS(OMAP_UART2_BASE), 43 .membase = IO_ADDRESS(OMAP_UART2_BASE),
44 .mapbase = (unsigned long)OMAP_UART2_BASE, 44 .mapbase = OMAP_UART2_BASE,
45 .irq = 73, 45 .irq = 73,
46 .flags = UPF_BOOT_AUTOCONF, 46 .flags = UPF_BOOT_AUTOCONF,
47 .iotype = UPIO_MEM, 47 .iotype = UPIO_MEM,
48 .regshift = 2, 48 .regshift = 2,
49 .uartclk = OMAP16XX_BASE_BAUD * 16, 49 .uartclk = OMAP16XX_BASE_BAUD * 16,
50 }, { 50 }, {
51 .membase = (char *)IO_ADDRESS(OMAP_UART3_BASE), 51 .membase = IO_ADDRESS(OMAP_UART3_BASE),
52 .mapbase = (unsigned long)OMAP_UART3_BASE, 52 .mapbase = OMAP_UART3_BASE,
53 .irq = 74, 53 .irq = 74,
54 .flags = UPF_BOOT_AUTOCONF, 54 .flags = UPF_BOOT_AUTOCONF,
55 .iotype = UPIO_MEM, 55 .iotype = UPIO_MEM,
@@ -71,7 +71,7 @@ static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
71 int value) 71 int value)
72{ 72{
73 offset <<= p->regshift; 73 offset <<= p->regshift;
74 __raw_writeb(value, (unsigned long)(p->membase + offset)); 74 __raw_writeb(value, p->membase + offset);
75} 75}
76 76
77/* 77/*
@@ -108,7 +108,7 @@ void __init omap_serial_init()
108 struct plat_serial8250_port *p = serial_platform_data + i; 108 struct plat_serial8250_port *p = serial_platform_data + i;
109 109
110 if (!(info->enabled_uarts & (1 << i))) { 110 if (!(info->enabled_uarts & (1 << i))) {
111 p->membase = 0; 111 p->membase = NULL;
112 p->mapbase = 0; 112 p->mapbase = 0;
113 continue; 113 continue;
114 } 114 }
diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h
index e75bd7004b94..0bd195551a27 100644
--- a/arch/arm/mach-orion5x/common.h
+++ b/arch/arm/mach-orion5x/common.h
@@ -41,6 +41,7 @@ struct pci_bus;
41struct pci_sys_data; 41struct pci_sys_data;
42 42
43void orion5x_pcie_id(u32 *dev, u32 *rev); 43void orion5x_pcie_id(u32 *dev, u32 *rev);
44void orion5x_pci_disable(void);
44void orion5x_pci_set_cardbus_mode(void); 45void orion5x_pci_set_cardbus_mode(void);
45int orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys); 46int orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys);
46struct pci_bus *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys); 47struct pci_bus *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys);
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index 1a1d84b80a65..b38c65ccfb15 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -245,12 +245,8 @@ static struct orion5x_mpp_mode dns323_mpp_modes[] __initdata = {
245static struct i2c_board_info __initdata dns323_i2c_devices[] = { 245static struct i2c_board_info __initdata dns323_i2c_devices[] = {
246 { 246 {
247 I2C_BOARD_INFO("g760a", 0x3e), 247 I2C_BOARD_INFO("g760a", 0x3e),
248#if 0
249 /* this entry requires the new-style driver model lm75 driver,
250 * for the meantime "insmod lm75.ko force_lm75=0,0x48" is needed */
251 }, { 248 }, {
252 I2C_BOARD_INFO("g751", 0x48), 249 I2C_BOARD_INFO("lm75", 0x48),
253#endif
254 }, { 250 }, {
255 I2C_BOARD_INFO("m41t80", 0x68), 251 I2C_BOARD_INFO("m41t80", 0x68),
256 }, 252 },
diff --git a/arch/arm/mach-orion5x/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c
index cb72f1bb9cb7..e321ec331839 100644
--- a/arch/arm/mach-orion5x/kurobox_pro-setup.c
+++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c
@@ -146,8 +146,10 @@ static struct hw_pci kurobox_pro_pci __initdata = {
146 146
147static int __init kurobox_pro_pci_init(void) 147static int __init kurobox_pro_pci_init(void)
148{ 148{
149 if (machine_is_kurobox_pro()) 149 if (machine_is_kurobox_pro()) {
150 orion5x_pci_disable();
150 pci_common_init(&kurobox_pro_pci); 151 pci_common_init(&kurobox_pro_pci);
152 }
151 153
152 return 0; 154 return 0;
153} 155}
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
index fbceecc4b7ec..a7b7d77b1b09 100644
--- a/arch/arm/mach-orion5x/pci.c
+++ b/arch/arm/mach-orion5x/pci.c
@@ -541,6 +541,13 @@ static void __devinit rc_pci_fixup(struct pci_dev *dev)
541} 541}
542DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup); 542DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
543 543
544static int orion5x_pci_disabled __initdata;
545
546void __init orion5x_pci_disable(void)
547{
548 orion5x_pci_disabled = 1;
549}
550
544void __init orion5x_pci_set_cardbus_mode(void) 551void __init orion5x_pci_set_cardbus_mode(void)
545{ 552{
546 orion5x_pci_cardbus_mode = 1; 553 orion5x_pci_cardbus_mode = 1;
@@ -553,7 +560,7 @@ int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys)
553 if (nr == 0) { 560 if (nr == 0) {
554 orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr); 561 orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr);
555 ret = pcie_setup(sys); 562 ret = pcie_setup(sys);
556 } else if (nr == 1) { 563 } else if (nr == 1 && !orion5x_pci_disabled) {
557 orion5x_pci_set_bus_nr(sys->busnr); 564 orion5x_pci_set_bus_nr(sys->busnr);
558 ret = pci_setup(sys); 565 ret = pci_setup(sys);
559 } 566 }
@@ -567,7 +574,7 @@ struct pci_bus __init *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys
567 574
568 if (nr == 0) { 575 if (nr == 0) {
569 bus = pci_scan_bus(sys->busnr, &pcie_ops, sys); 576 bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
570 } else if (nr == 1) { 577 } else if (nr == 1 && !orion5x_pci_disabled) {
571 bus = pci_scan_bus(sys->busnr, &pci_ops, sys); 578 bus = pci_scan_bus(sys->busnr, &pci_ops, sys);
572 } else { 579 } else {
573 bus = NULL; 580 bus = NULL;
@@ -584,7 +591,7 @@ int __init orion5x_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
584 /* 591 /*
585 * PCIe endpoint? 592 * PCIe endpoint?
586 */ 593 */
587 if (bus < orion5x_pci_local_bus_nr()) 594 if (orion5x_pci_disabled || bus < orion5x_pci_local_bus_nr())
588 return IRQ_ORION5X_PCIE0_INT; 595 return IRQ_ORION5X_PCIE0_INT;
589 596
590 return -1; 597 return -1;
diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c
index dd657163cd8d..9d6890514199 100644
--- a/arch/arm/mach-orion5x/ts209-setup.c
+++ b/arch/arm/mach-orion5x/ts209-setup.c
@@ -287,6 +287,10 @@ static void __init qnap_ts209_init(void)
287 /* 287 /*
288 * Configure peripherals. 288 * Configure peripherals.
289 */ 289 */
290 orion5x_setup_dev_boot_win(QNAP_TS209_NOR_BOOT_BASE,
291 QNAP_TS209_NOR_BOOT_SIZE);
292 platform_device_register(&qnap_ts209_nor_flash);
293
290 orion5x_ehci0_init(); 294 orion5x_ehci0_init();
291 orion5x_ehci1_init(); 295 orion5x_ehci1_init();
292 qnap_tsx09_find_mac_addr(QNAP_TS209_NOR_BOOT_BASE + 296 qnap_tsx09_find_mac_addr(QNAP_TS209_NOR_BOOT_BASE +
@@ -296,12 +300,9 @@ static void __init qnap_ts209_init(void)
296 orion5x_i2c_init(); 300 orion5x_i2c_init();
297 orion5x_sata_init(&qnap_ts209_sata_data); 301 orion5x_sata_init(&qnap_ts209_sata_data);
298 orion5x_uart0_init(); 302 orion5x_uart0_init();
303 orion5x_uart1_init();
299 orion5x_xor_init(); 304 orion5x_xor_init();
300 305
301 orion5x_setup_dev_boot_win(QNAP_TS209_NOR_BOOT_BASE,
302 QNAP_TS209_NOR_BOOT_SIZE);
303 platform_device_register(&qnap_ts209_nor_flash);
304
305 platform_device_register(&qnap_ts209_button_device); 306 platform_device_register(&qnap_ts209_button_device);
306 307
307 /* Get RTC IRQ and register the chip */ 308 /* Get RTC IRQ and register the chip */
diff --git a/arch/arm/mach-orion5x/ts409-setup.c b/arch/arm/mach-orion5x/ts409-setup.c
index b27d2b762081..d85588ac7ef8 100644
--- a/arch/arm/mach-orion5x/ts409-setup.c
+++ b/arch/arm/mach-orion5x/ts409-setup.c
@@ -278,6 +278,10 @@ static void __init qnap_ts409_init(void)
278 /* 278 /*
279 * Configure peripherals. 279 * Configure peripherals.
280 */ 280 */
281 orion5x_setup_dev_boot_win(QNAP_TS409_NOR_BOOT_BASE,
282 QNAP_TS409_NOR_BOOT_SIZE);
283 platform_device_register(&qnap_ts409_nor_flash);
284
281 orion5x_ehci0_init(); 285 orion5x_ehci0_init();
282 qnap_tsx09_find_mac_addr(QNAP_TS409_NOR_BOOT_BASE + 286 qnap_tsx09_find_mac_addr(QNAP_TS409_NOR_BOOT_BASE +
283 qnap_ts409_partitions[5].offset, 287 qnap_ts409_partitions[5].offset,
@@ -285,10 +289,7 @@ static void __init qnap_ts409_init(void)
285 orion5x_eth_init(&qnap_tsx09_eth_data); 289 orion5x_eth_init(&qnap_tsx09_eth_data);
286 orion5x_i2c_init(); 290 orion5x_i2c_init();
287 orion5x_uart0_init(); 291 orion5x_uart0_init();
288 292 orion5x_uart1_init();
289 orion5x_setup_dev_boot_win(QNAP_TS409_NOR_BOOT_BASE,
290 QNAP_TS409_NOR_BOOT_SIZE);
291 platform_device_register(&qnap_ts409_nor_flash);
292 293
293 platform_device_register(&qnap_ts409_button_device); 294 platform_device_register(&qnap_ts409_button_device);
294 295
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index 123a950db466..e703a8d209e2 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -38,6 +38,7 @@
38#include <mach/pxa-regs.h> 38#include <mach/pxa-regs.h>
39#include <mach/pxa2xx-regs.h> 39#include <mach/pxa2xx-regs.h>
40#include <mach/pxa2xx-gpio.h> 40#include <mach/pxa2xx-gpio.h>
41#include <mach/i2c.h>
41#include <mach/irda.h> 42#include <mach/irda.h>
42#include <mach/mmc.h> 43#include <mach/mmc.h>
43#include <mach/udc.h> 44#include <mach/udc.h>
@@ -532,6 +533,7 @@ static void __init corgi_init(void)
532 pxa_set_udc_info(&udc_info); 533 pxa_set_udc_info(&udc_info);
533 pxa_set_mci_info(&corgi_mci_platform_data); 534 pxa_set_mci_info(&corgi_mci_platform_data);
534 pxa_set_ficp_info(&corgi_ficp_platform_data); 535 pxa_set_ficp_info(&corgi_ficp_platform_data);
536 pxa_set_i2c_info(NULL);
535 537
536 platform_scoop_config = &corgi_pcmcia_config; 538 platform_scoop_config = &corgi_pcmcia_config;
537 539
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index 055ec63d768c..3f5f484549b3 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -36,6 +36,7 @@
36#include <mach/pxa2xx-gpio.h> 36#include <mach/pxa2xx-gpio.h>
37#include <mach/mmc.h> 37#include <mach/mmc.h>
38#include <mach/udc.h> 38#include <mach/udc.h>
39#include <mach/i2c.h>
39#include <mach/irda.h> 40#include <mach/irda.h>
40#include <mach/poodle.h> 41#include <mach/poodle.h>
41#include <mach/pxafb.h> 42#include <mach/pxafb.h>
@@ -387,6 +388,7 @@ static void __init poodle_init(void)
387 pxa_set_udc_info(&udc_info); 388 pxa_set_udc_info(&udc_info);
388 pxa_set_mci_info(&poodle_mci_platform_data); 389 pxa_set_mci_info(&poodle_mci_platform_data);
389 pxa_set_ficp_info(&poodle_ficp_platform_data); 390 pxa_set_ficp_info(&poodle_ficp_platform_data);
391 pxa_set_i2c_info(NULL);
390 392
391 platform_scoop_config = &poodle_pcmcia_config; 393 platform_scoop_config = &poodle_pcmcia_config;
392 394
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index cd39005c98ff..b569f3b4cf3a 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -40,6 +40,7 @@
40#include <mach/pxa2xx-gpio.h> 40#include <mach/pxa2xx-gpio.h>
41#include <mach/pxa27x-udc.h> 41#include <mach/pxa27x-udc.h>
42#include <mach/reset.h> 42#include <mach/reset.h>
43#include <mach/i2c.h>
43#include <mach/irda.h> 44#include <mach/irda.h>
44#include <mach/mmc.h> 45#include <mach/mmc.h>
45#include <mach/ohci.h> 46#include <mach/ohci.h>
@@ -574,6 +575,7 @@ static void __init common_init(void)
574 pxa_set_ficp_info(&spitz_ficp_platform_data); 575 pxa_set_ficp_info(&spitz_ficp_platform_data);
575 set_pxa_fb_parent(&spitzssp_device.dev); 576 set_pxa_fb_parent(&spitzssp_device.dev);
576 set_pxa_fb_info(&spitz_pxafb_info); 577 set_pxa_fb_info(&spitz_pxafb_info);
578 pxa_set_i2c_info(NULL);
577} 579}
578 580
579#if defined(CONFIG_MACH_SPITZ) || defined(CONFIG_MACH_BORZOI) 581#if defined(CONFIG_MACH_SPITZ) || defined(CONFIG_MACH_BORZOI)
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h b/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h
index 7dd458363a51..6026d091a2fe 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h
@@ -48,11 +48,11 @@
48#define S3C2443_CLKSRC_I2S_EPLLREF3 (3<<14) 48#define S3C2443_CLKSRC_I2S_EPLLREF3 (3<<14)
49#define S3C2443_CLKSRC_I2S_MASK (3<<14) 49#define S3C2443_CLKSRC_I2S_MASK (3<<14)
50 50
51#define S3C2443_CLKSRC_EPLLREF_XTAL (2<<8) 51#define S3C2443_CLKSRC_EPLLREF_XTAL (2<<7)
52#define S3C2443_CLKSRC_EPLLREF_EXTCLK (3<<8) 52#define S3C2443_CLKSRC_EPLLREF_EXTCLK (3<<7)
53#define S3C2443_CLKSRC_EPLLREF_MPLLREF (0<<8) 53#define S3C2443_CLKSRC_EPLLREF_MPLLREF (0<<7)
54#define S3C2443_CLKSRC_EPLLREF_MPLLREF2 (1<<8) 54#define S3C2443_CLKSRC_EPLLREF_MPLLREF2 (1<<7)
55#define S3C2443_CLKSRC_EPLLREF_MASK (3<<8) 55#define S3C2443_CLKSRC_EPLLREF_MASK (3<<7)
56 56
57#define S3C2443_CLKSRC_ESYSCLK_EPLL (1<<6) 57#define S3C2443_CLKSRC_ESYSCLK_EPLL (1<<6)
58#define S3C2443_CLKSRC_MSYSCLK_MPLL (1<<4) 58#define S3C2443_CLKSRC_MSYSCLK_MPLL (1<<4)
diff --git a/arch/arm/mach-s3c2410/nor-simtec.c b/arch/arm/mach-s3c2410/nor-simtec.c
index b2ae237042a5..598d130633dc 100644
--- a/arch/arm/mach-s3c2410/nor-simtec.c
+++ b/arch/arm/mach-s3c2410/nor-simtec.c
@@ -30,6 +30,7 @@
30#include <mach/bast-map.h> 30#include <mach/bast-map.h>
31#include <mach/bast-cpld.h> 31#include <mach/bast-cpld.h>
32 32
33#include "nor-simtec.h"
33 34
34static void simtec_nor_vpp(struct map_info *map, int vpp) 35static void simtec_nor_vpp(struct map_info *map, int vpp)
35{ 36{
@@ -50,7 +51,7 @@ static void simtec_nor_vpp(struct map_info *map, int vpp)
50 local_irq_restore(flags); 51 local_irq_restore(flags);
51} 52}
52 53
53struct physmap_flash_data simtec_nor_pdata = { 54static struct physmap_flash_data simtec_nor_pdata = {
54 .width = 2, 55 .width = 2,
55 .set_vpp = simtec_nor_vpp, 56 .set_vpp = simtec_nor_vpp,
56 .nr_parts = 0, 57 .nr_parts = 0,
diff --git a/arch/arm/mach-s3c2412/mach-jive.c b/arch/arm/mach-s3c2412/mach-jive.c
index 4c061d29463c..ad980a1690c2 100644
--- a/arch/arm/mach-s3c2412/mach-jive.c
+++ b/arch/arm/mach-s3c2412/mach-jive.c
@@ -395,7 +395,7 @@ static void jive_lcd_spi_chipselect(struct s3c2410_spigpio_info *spi, int cs)
395} 395}
396 396
397static struct s3c2410_spigpio_info jive_lcd_spi = { 397static struct s3c2410_spigpio_info jive_lcd_spi = {
398 .bus_num = 0, 398 .bus_num = 1,
399 .pin_clk = S3C2410_GPG8, 399 .pin_clk = S3C2410_GPG8,
400 .pin_mosi = S3C2410_GPB8, 400 .pin_mosi = S3C2410_GPB8,
401 .chip_select = jive_lcd_spi_chipselect, 401 .chip_select = jive_lcd_spi_chipselect,
diff --git a/arch/arm/plat-mxc/clock.c b/arch/arm/plat-mxc/clock.c
index 2f8627218839..0a38f0b396eb 100644
--- a/arch/arm/plat-mxc/clock.c
+++ b/arch/arm/plat-mxc/clock.c
@@ -37,7 +37,6 @@
37#include <linux/proc_fs.h> 37#include <linux/proc_fs.h>
38#include <linux/semaphore.h> 38#include <linux/semaphore.h>
39#include <linux/string.h> 39#include <linux/string.h>
40#include <linux/version.h>
41 40
42#include <mach/clock.h> 41#include <mach/clock.h>
43 42
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index 2c4051cc79a1..deaff58878a2 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -4,7 +4,7 @@
4 4
5# Common support 5# Common support
6obj-y := common.o sram.o clock.o devices.o dma.o mux.o gpio.o \ 6obj-y := common.o sram.o clock.o devices.o dma.o mux.o gpio.o \
7 usb.o fb.o 7 usb.o fb.o io.o
8obj-m := 8obj-m :=
9obj-n := 9obj-n :=
10obj- := 10obj- :=
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index f4dff423ae7c..20e8db5fe32a 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -258,12 +258,12 @@ static void __init __omap2_set_globals(void)
258#if defined(CONFIG_ARCH_OMAP2420) 258#if defined(CONFIG_ARCH_OMAP2420)
259 259
260static struct omap_globals omap242x_globals = { 260static struct omap_globals omap242x_globals = {
261 .tap = (__force void __iomem *)OMAP2_IO_ADDRESS(0x48014000), 261 .tap = OMAP2_IO_ADDRESS(0x48014000),
262 .sdrc = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_SDRC_BASE), 262 .sdrc = OMAP2_IO_ADDRESS(OMAP2420_SDRC_BASE),
263 .sms = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_SMS_BASE), 263 .sms = OMAP2_IO_ADDRESS(OMAP2420_SMS_BASE),
264 .ctrl = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_CTRL_BASE), 264 .ctrl = OMAP2_IO_ADDRESS(OMAP2420_CTRL_BASE),
265 .prm = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_PRM_BASE), 265 .prm = OMAP2_IO_ADDRESS(OMAP2420_PRM_BASE),
266 .cm = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_CM_BASE), 266 .cm = OMAP2_IO_ADDRESS(OMAP2420_CM_BASE),
267}; 267};
268 268
269void __init omap2_set_globals_242x(void) 269void __init omap2_set_globals_242x(void)
@@ -276,12 +276,12 @@ void __init omap2_set_globals_242x(void)
276#if defined(CONFIG_ARCH_OMAP2430) 276#if defined(CONFIG_ARCH_OMAP2430)
277 277
278static struct omap_globals omap243x_globals = { 278static struct omap_globals omap243x_globals = {
279 .tap = (__force void __iomem *)OMAP2_IO_ADDRESS(0x4900a000), 279 .tap = OMAP2_IO_ADDRESS(0x4900a000),
280 .sdrc = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP243X_SDRC_BASE), 280 .sdrc = OMAP2_IO_ADDRESS(OMAP243X_SDRC_BASE),
281 .sms = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP243X_SMS_BASE), 281 .sms = OMAP2_IO_ADDRESS(OMAP243X_SMS_BASE),
282 .ctrl = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP243X_CTRL_BASE), 282 .ctrl = OMAP2_IO_ADDRESS(OMAP243X_CTRL_BASE),
283 .prm = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2430_PRM_BASE), 283 .prm = OMAP2_IO_ADDRESS(OMAP2430_PRM_BASE),
284 .cm = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2430_CM_BASE), 284 .cm = OMAP2_IO_ADDRESS(OMAP2430_CM_BASE),
285}; 285};
286 286
287void __init omap2_set_globals_243x(void) 287void __init omap2_set_globals_243x(void)
@@ -294,12 +294,12 @@ void __init omap2_set_globals_243x(void)
294#if defined(CONFIG_ARCH_OMAP3430) 294#if defined(CONFIG_ARCH_OMAP3430)
295 295
296static struct omap_globals omap343x_globals = { 296static struct omap_globals omap343x_globals = {
297 .tap = (__force void __iomem *)OMAP2_IO_ADDRESS(0x4830A000), 297 .tap = OMAP2_IO_ADDRESS(0x4830A000),
298 .sdrc = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP343X_SDRC_BASE), 298 .sdrc = OMAP2_IO_ADDRESS(OMAP343X_SDRC_BASE),
299 .sms = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP343X_SMS_BASE), 299 .sms = OMAP2_IO_ADDRESS(OMAP343X_SMS_BASE),
300 .ctrl = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP343X_CTRL_BASE), 300 .ctrl = OMAP2_IO_ADDRESS(OMAP343X_CTRL_BASE),
301 .prm = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP3430_PRM_BASE), 301 .prm = OMAP2_IO_ADDRESS(OMAP3430_PRM_BASE),
302 .cm = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP3430_CM_BASE), 302 .cm = OMAP2_IO_ADDRESS(OMAP3430_CM_BASE),
303}; 303};
304 304
305void __init omap2_set_globals_343x(void) 305void __init omap2_set_globals_343x(void)
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index a63b644ad305..50f8b4ad9a09 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -1233,7 +1233,7 @@ int omap_request_dma_chain(int dev_id, const char *dev_name,
1233 /* request and reserve DMA channels for the chain */ 1233 /* request and reserve DMA channels for the chain */
1234 for (i = 0; i < no_of_chans; i++) { 1234 for (i = 0; i < no_of_chans; i++) {
1235 err = omap_request_dma(dev_id, dev_name, 1235 err = omap_request_dma(dev_id, dev_name,
1236 callback, 0, &channels[i]); 1236 callback, NULL, &channels[i]);
1237 if (err < 0) { 1237 if (err < 0) {
1238 int j; 1238 int j;
1239 for (j = 0; j < i; j++) 1239 for (j = 0; j < i; j++)
@@ -2297,13 +2297,13 @@ static int __init omap_init_dma(void)
2297 int ch, r; 2297 int ch, r;
2298 2298
2299 if (cpu_class_is_omap1()) { 2299 if (cpu_class_is_omap1()) {
2300 omap_dma_base = (void __iomem *)IO_ADDRESS(OMAP1_DMA_BASE); 2300 omap_dma_base = IO_ADDRESS(OMAP1_DMA_BASE);
2301 dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT; 2301 dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
2302 } else if (cpu_is_omap24xx()) { 2302 } else if (cpu_is_omap24xx()) {
2303 omap_dma_base = (void __iomem *)IO_ADDRESS(OMAP24XX_DMA4_BASE); 2303 omap_dma_base = IO_ADDRESS(OMAP24XX_DMA4_BASE);
2304 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT; 2304 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2305 } else if (cpu_is_omap34xx()) { 2305 } else if (cpu_is_omap34xx()) {
2306 omap_dma_base = (void __iomem *)IO_ADDRESS(OMAP34XX_DMA4_BASE); 2306 omap_dma_base = IO_ADDRESS(OMAP34XX_DMA4_BASE);
2307 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT; 2307 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2308 } else { 2308 } else {
2309 pr_err("DMA init failed for unsupported omap\n"); 2309 pr_err("DMA init failed for unsupported omap\n");
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 743a4abcd85d..df61ad247dc2 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -693,7 +693,7 @@ int __init omap_dm_timer_init(void)
693 693
694 for (i = 0; i < dm_timer_count; i++) { 694 for (i = 0; i < dm_timer_count; i++) {
695 timer = &dm_timers[i]; 695 timer = &dm_timers[i];
696 timer->io_base = (void __iomem *)io_p2v(timer->phys_base); 696 timer->io_base = IO_ADDRESS(timer->phys_base);
697#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) 697#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
698 if (cpu_class_is_omap2()) { 698 if (cpu_class_is_omap2()) {
699 char clk_name[16]; 699 char clk_name[16];
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 3e76ee2bc731..5de70d650922 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -29,7 +29,7 @@
29/* 29/*
30 * OMAP1510 GPIO registers 30 * OMAP1510 GPIO registers
31 */ 31 */
32#define OMAP1510_GPIO_BASE (void __iomem *)0xfffce000 32#define OMAP1510_GPIO_BASE IO_ADDRESS(0xfffce000)
33#define OMAP1510_GPIO_DATA_INPUT 0x00 33#define OMAP1510_GPIO_DATA_INPUT 0x00
34#define OMAP1510_GPIO_DATA_OUTPUT 0x04 34#define OMAP1510_GPIO_DATA_OUTPUT 0x04
35#define OMAP1510_GPIO_DIR_CONTROL 0x08 35#define OMAP1510_GPIO_DIR_CONTROL 0x08
@@ -43,10 +43,10 @@
43/* 43/*
44 * OMAP1610 specific GPIO registers 44 * OMAP1610 specific GPIO registers
45 */ 45 */
46#define OMAP1610_GPIO1_BASE (void __iomem *)0xfffbe400 46#define OMAP1610_GPIO1_BASE IO_ADDRESS(0xfffbe400)
47#define OMAP1610_GPIO2_BASE (void __iomem *)0xfffbec00 47#define OMAP1610_GPIO2_BASE IO_ADDRESS(0xfffbec00)
48#define OMAP1610_GPIO3_BASE (void __iomem *)0xfffbb400 48#define OMAP1610_GPIO3_BASE IO_ADDRESS(0xfffbb400)
49#define OMAP1610_GPIO4_BASE (void __iomem *)0xfffbbc00 49#define OMAP1610_GPIO4_BASE IO_ADDRESS(0xfffbbc00)
50#define OMAP1610_GPIO_REVISION 0x0000 50#define OMAP1610_GPIO_REVISION 0x0000
51#define OMAP1610_GPIO_SYSCONFIG 0x0010 51#define OMAP1610_GPIO_SYSCONFIG 0x0010
52#define OMAP1610_GPIO_SYSSTATUS 0x0014 52#define OMAP1610_GPIO_SYSSTATUS 0x0014
@@ -68,12 +68,12 @@
68/* 68/*
69 * OMAP730 specific GPIO registers 69 * OMAP730 specific GPIO registers
70 */ 70 */
71#define OMAP730_GPIO1_BASE (void __iomem *)0xfffbc000 71#define OMAP730_GPIO1_BASE IO_ADDRESS(0xfffbc000)
72#define OMAP730_GPIO2_BASE (void __iomem *)0xfffbc800 72#define OMAP730_GPIO2_BASE IO_ADDRESS(0xfffbc800)
73#define OMAP730_GPIO3_BASE (void __iomem *)0xfffbd000 73#define OMAP730_GPIO3_BASE IO_ADDRESS(0xfffbd000)
74#define OMAP730_GPIO4_BASE (void __iomem *)0xfffbd800 74#define OMAP730_GPIO4_BASE IO_ADDRESS(0xfffbd800)
75#define OMAP730_GPIO5_BASE (void __iomem *)0xfffbe000 75#define OMAP730_GPIO5_BASE IO_ADDRESS(0xfffbe000)
76#define OMAP730_GPIO6_BASE (void __iomem *)0xfffbe800 76#define OMAP730_GPIO6_BASE IO_ADDRESS(0xfffbe800)
77#define OMAP730_GPIO_DATA_INPUT 0x00 77#define OMAP730_GPIO_DATA_INPUT 0x00
78#define OMAP730_GPIO_DATA_OUTPUT 0x04 78#define OMAP730_GPIO_DATA_OUTPUT 0x04
79#define OMAP730_GPIO_DIR_CONTROL 0x08 79#define OMAP730_GPIO_DIR_CONTROL 0x08
@@ -84,16 +84,16 @@
84/* 84/*
85 * omap24xx specific GPIO registers 85 * omap24xx specific GPIO registers
86 */ 86 */
87#define OMAP242X_GPIO1_BASE (void __iomem *)0x48018000 87#define OMAP242X_GPIO1_BASE IO_ADDRESS(0x48018000)
88#define OMAP242X_GPIO2_BASE (void __iomem *)0x4801a000 88#define OMAP242X_GPIO2_BASE IO_ADDRESS(0x4801a000)
89#define OMAP242X_GPIO3_BASE (void __iomem *)0x4801c000 89#define OMAP242X_GPIO3_BASE IO_ADDRESS(0x4801c000)
90#define OMAP242X_GPIO4_BASE (void __iomem *)0x4801e000 90#define OMAP242X_GPIO4_BASE IO_ADDRESS(0x4801e000)
91 91
92#define OMAP243X_GPIO1_BASE (void __iomem *)0x4900C000 92#define OMAP243X_GPIO1_BASE IO_ADDRESS(0x4900C000)
93#define OMAP243X_GPIO2_BASE (void __iomem *)0x4900E000 93#define OMAP243X_GPIO2_BASE IO_ADDRESS(0x4900E000)
94#define OMAP243X_GPIO3_BASE (void __iomem *)0x49010000 94#define OMAP243X_GPIO3_BASE IO_ADDRESS(0x49010000)
95#define OMAP243X_GPIO4_BASE (void __iomem *)0x49012000 95#define OMAP243X_GPIO4_BASE IO_ADDRESS(0x49012000)
96#define OMAP243X_GPIO5_BASE (void __iomem *)0x480B6000 96#define OMAP243X_GPIO5_BASE IO_ADDRESS(0x480B6000)
97 97
98#define OMAP24XX_GPIO_REVISION 0x0000 98#define OMAP24XX_GPIO_REVISION 0x0000
99#define OMAP24XX_GPIO_SYSCONFIG 0x0010 99#define OMAP24XX_GPIO_SYSCONFIG 0x0010
@@ -123,13 +123,14 @@
123 * omap34xx specific GPIO registers 123 * omap34xx specific GPIO registers
124 */ 124 */
125 125
126#define OMAP34XX_GPIO1_BASE (void __iomem *)0x48310000 126#define OMAP34XX_GPIO1_BASE IO_ADDRESS(0x48310000)
127#define OMAP34XX_GPIO2_BASE (void __iomem *)0x49050000 127#define OMAP34XX_GPIO2_BASE IO_ADDRESS(0x49050000)
128#define OMAP34XX_GPIO3_BASE (void __iomem *)0x49052000 128#define OMAP34XX_GPIO3_BASE IO_ADDRESS(0x49052000)
129#define OMAP34XX_GPIO4_BASE (void __iomem *)0x49054000 129#define OMAP34XX_GPIO4_BASE IO_ADDRESS(0x49054000)
130#define OMAP34XX_GPIO5_BASE (void __iomem *)0x49056000 130#define OMAP34XX_GPIO5_BASE IO_ADDRESS(0x49056000)
131#define OMAP34XX_GPIO6_BASE (void __iomem *)0x49058000 131#define OMAP34XX_GPIO6_BASE IO_ADDRESS(0x49058000)
132 132
133#define OMAP_MPUIO_VBASE IO_ADDRESS(OMAP_MPUIO_BASE)
133 134
134struct gpio_bank { 135struct gpio_bank {
135 void __iomem *base; 136 void __iomem *base;
@@ -161,7 +162,7 @@ struct gpio_bank {
161 162
162#ifdef CONFIG_ARCH_OMAP16XX 163#ifdef CONFIG_ARCH_OMAP16XX
163static struct gpio_bank gpio_bank_1610[5] = { 164static struct gpio_bank gpio_bank_1610[5] = {
164 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO}, 165 { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
165 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 }, 166 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
166 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 }, 167 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
167 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 }, 168 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
@@ -171,14 +172,14 @@ static struct gpio_bank gpio_bank_1610[5] = {
171 172
172#ifdef CONFIG_ARCH_OMAP15XX 173#ifdef CONFIG_ARCH_OMAP15XX
173static struct gpio_bank gpio_bank_1510[2] = { 174static struct gpio_bank gpio_bank_1510[2] = {
174 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO }, 175 { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
175 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 } 176 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
176}; 177};
177#endif 178#endif
178 179
179#ifdef CONFIG_ARCH_OMAP730 180#ifdef CONFIG_ARCH_OMAP730
180static struct gpio_bank gpio_bank_730[7] = { 181static struct gpio_bank gpio_bank_730[7] = {
181 { OMAP_MPUIO_BASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO }, 182 { OMAP_MPUIO_VBASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
182 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 }, 183 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
183 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 }, 184 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
184 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 }, 185 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
@@ -1393,7 +1394,7 @@ static int __init _omap_gpio_init(void)
1393 1394
1394 gpio_bank_count = 5; 1395 gpio_bank_count = 5;
1395 gpio_bank = gpio_bank_1610; 1396 gpio_bank = gpio_bank_1610;
1396 rev = omap_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION); 1397 rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1397 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n", 1398 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1398 (rev >> 4) & 0x0f, rev & 0x0f); 1399 (rev >> 4) & 0x0f, rev & 0x0f);
1399 } 1400 }
@@ -1412,7 +1413,7 @@ static int __init _omap_gpio_init(void)
1412 1413
1413 gpio_bank_count = 4; 1414 gpio_bank_count = 4;
1414 gpio_bank = gpio_bank_242x; 1415 gpio_bank = gpio_bank_242x;
1415 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION); 1416 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1416 printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n", 1417 printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n",
1417 (rev >> 4) & 0x0f, rev & 0x0f); 1418 (rev >> 4) & 0x0f, rev & 0x0f);
1418 } 1419 }
@@ -1421,7 +1422,7 @@ static int __init _omap_gpio_init(void)
1421 1422
1422 gpio_bank_count = 5; 1423 gpio_bank_count = 5;
1423 gpio_bank = gpio_bank_243x; 1424 gpio_bank = gpio_bank_243x;
1424 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION); 1425 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1425 printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n", 1426 printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
1426 (rev >> 4) & 0x0f, rev & 0x0f); 1427 (rev >> 4) & 0x0f, rev & 0x0f);
1427 } 1428 }
@@ -1432,7 +1433,7 @@ static int __init _omap_gpio_init(void)
1432 1433
1433 gpio_bank_count = OMAP34XX_NR_GPIOS; 1434 gpio_bank_count = OMAP34XX_NR_GPIOS;
1434 gpio_bank = gpio_bank_34xx; 1435 gpio_bank = gpio_bank_34xx;
1435 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION); 1436 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1436 printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n", 1437 printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n",
1437 (rev >> 4) & 0x0f, rev & 0x0f); 1438 (rev >> 4) & 0x0f, rev & 0x0f);
1438 } 1439 }
@@ -1441,10 +1442,9 @@ static int __init _omap_gpio_init(void)
1441 int j, gpio_count = 16; 1442 int j, gpio_count = 16;
1442 1443
1443 bank = &gpio_bank[i]; 1444 bank = &gpio_bank[i];
1444 bank->base = IO_ADDRESS(bank->base);
1445 spin_lock_init(&bank->lock); 1445 spin_lock_init(&bank->lock);
1446 if (bank_is_mpuio(bank)) 1446 if (bank_is_mpuio(bank))
1447 omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT); 1447 __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT);
1448 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) { 1448 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1449 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK); 1449 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1450 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS); 1450 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
@@ -1488,7 +1488,7 @@ static int __init _omap_gpio_init(void)
1488 bank->chip.set = gpio_set; 1488 bank->chip.set = gpio_set;
1489 if (bank_is_mpuio(bank)) { 1489 if (bank_is_mpuio(bank)) {
1490 bank->chip.label = "mpuio"; 1490 bank->chip.label = "mpuio";
1491#ifdef CONFIG_ARCH_OMAP1 1491#ifdef CONFIG_ARCH_OMAP16XX
1492 bank->chip.dev = &omap_mpuio_device.dev; 1492 bank->chip.dev = &omap_mpuio_device.dev;
1493#endif 1493#endif
1494 bank->chip.base = OMAP_MPUIO(0); 1494 bank->chip.base = OMAP_MPUIO(0);
diff --git a/arch/arm/plat-omap/include/mach/control.h b/arch/arm/plat-omap/include/mach/control.h
index e3fd62d9a995..ee378d254cbd 100644
--- a/arch/arm/plat-omap/include/mach/control.h
+++ b/arch/arm/plat-omap/include/mach/control.h
@@ -19,11 +19,11 @@
19#include <mach/io.h> 19#include <mach/io.h>
20 20
21#define OMAP242X_CTRL_REGADDR(reg) \ 21#define OMAP242X_CTRL_REGADDR(reg) \
22 (void __iomem *)IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) 22 IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
23#define OMAP243X_CTRL_REGADDR(reg) \ 23#define OMAP243X_CTRL_REGADDR(reg) \
24 (void __iomem *)IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) 24 IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
25#define OMAP343X_CTRL_REGADDR(reg) \ 25#define OMAP343X_CTRL_REGADDR(reg) \
26 (void __iomem *)IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) 26 IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
27 27
28/* 28/*
29 * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for 29 * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for
diff --git a/arch/arm/plat-omap/include/mach/fpga.h b/arch/arm/plat-omap/include/mach/fpga.h
index c92e4b42b289..f1864a652f7a 100644
--- a/arch/arm/plat-omap/include/mach/fpga.h
+++ b/arch/arm/plat-omap/include/mach/fpga.h
@@ -34,9 +34,9 @@ extern void omap1510_fpga_init_irq(void);
34 * --------------------------------------------------------------------------- 34 * ---------------------------------------------------------------------------
35 */ 35 */
36/* maps in the FPGA registers and the ETHR registers */ 36/* maps in the FPGA registers and the ETHR registers */
37#define H2P2_DBG_FPGA_BASE 0xE8000000 /* VA */ 37#define H2P2_DBG_FPGA_BASE IOMEM(0xE8000000) /* VA */
38#define H2P2_DBG_FPGA_SIZE SZ_4K /* SIZE */ 38#define H2P2_DBG_FPGA_SIZE SZ_4K /* SIZE */
39#define H2P2_DBG_FPGA_START 0x04000000 /* PA */ 39#define H2P2_DBG_FPGA_START 0x04000000 /* PA */
40 40
41#define H2P2_DBG_FPGA_ETHR_START (H2P2_DBG_FPGA_START + 0x300) 41#define H2P2_DBG_FPGA_ETHR_START (H2P2_DBG_FPGA_START + 0x300)
42#define H2P2_DBG_FPGA_FPGA_REV (H2P2_DBG_FPGA_BASE + 0x10) /* FPGA Revision */ 42#define H2P2_DBG_FPGA_FPGA_REV (H2P2_DBG_FPGA_BASE + 0x10) /* FPGA Revision */
@@ -85,9 +85,9 @@ struct h2p2_dbg_fpga {
85 * OMAP-1510 FPGA 85 * OMAP-1510 FPGA
86 * --------------------------------------------------------------------------- 86 * ---------------------------------------------------------------------------
87 */ 87 */
88#define OMAP1510_FPGA_BASE 0xE8000000 /* Virtual */ 88#define OMAP1510_FPGA_BASE IOMEM(0xE8000000) /* VA */
89#define OMAP1510_FPGA_SIZE SZ_4K 89#define OMAP1510_FPGA_SIZE SZ_4K
90#define OMAP1510_FPGA_START 0x08000000 /* Physical */ 90#define OMAP1510_FPGA_START 0x08000000 /* PA */
91 91
92/* Revision */ 92/* Revision */
93#define OMAP1510_FPGA_REV_LOW (OMAP1510_FPGA_BASE + 0x0) 93#define OMAP1510_FPGA_REV_LOW (OMAP1510_FPGA_BASE + 0x0)
diff --git a/arch/arm/plat-omap/include/mach/gpio.h b/arch/arm/plat-omap/include/mach/gpio.h
index 94ce2780e8ee..4cb818da672c 100644
--- a/arch/arm/plat-omap/include/mach/gpio.h
+++ b/arch/arm/plat-omap/include/mach/gpio.h
@@ -29,7 +29,7 @@
29#include <mach/irqs.h> 29#include <mach/irqs.h>
30#include <asm/io.h> 30#include <asm/io.h>
31 31
32#define OMAP_MPUIO_BASE (void __iomem *)0xfffb5000 32#define OMAP_MPUIO_BASE 0xfffb5000
33 33
34#ifdef CONFIG_ARCH_OMAP730 34#ifdef CONFIG_ARCH_OMAP730
35#define OMAP_MPUIO_INPUT_LATCH 0x00 35#define OMAP_MPUIO_INPUT_LATCH 0x00
diff --git a/arch/arm/plat-omap/include/mach/hardware.h b/arch/arm/plat-omap/include/mach/hardware.h
index 07f5d7f21528..abb01e471c4c 100644
--- a/arch/arm/plat-omap/include/mach/hardware.h
+++ b/arch/arm/plat-omap/include/mach/hardware.h
@@ -89,7 +89,7 @@
89#define DPLL_CTL (0xfffecf00) 89#define DPLL_CTL (0xfffecf00)
90 90
91/* DSP clock control. Must use __raw_readw() and __raw_writew() with these */ 91/* DSP clock control. Must use __raw_readw() and __raw_writew() with these */
92#define DSP_CONFIG_REG_BASE (0xe1008000) 92#define DSP_CONFIG_REG_BASE IOMEM(0xe1008000)
93#define DSP_CKCTL (DSP_CONFIG_REG_BASE + 0x0) 93#define DSP_CKCTL (DSP_CONFIG_REG_BASE + 0x0)
94#define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4) 94#define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4)
95#define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8) 95#define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8)
diff --git a/arch/arm/plat-omap/include/mach/io.h b/arch/arm/plat-omap/include/mach/io.h
index 2a30b7d88cde..dd0cf069431d 100644
--- a/arch/arm/plat-omap/include/mach/io.h
+++ b/arch/arm/plat-omap/include/mach/io.h
@@ -55,14 +55,13 @@
55 55
56#if defined(CONFIG_ARCH_OMAP1) 56#if defined(CONFIG_ARCH_OMAP1)
57 57
58#define IO_PHYS 0xFFFB0000 58#define IO_PHYS 0xFFFB0000
59#define IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */ 59#define IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */
60#define IO_SIZE 0x40000 60#define IO_SIZE 0x40000
61#define IO_VIRT (IO_PHYS - IO_OFFSET) 61#define IO_VIRT (IO_PHYS - IO_OFFSET)
62#define IO_ADDRESS(pa) ((pa) - IO_OFFSET) 62#define __IO_ADDRESS(pa) ((pa) - IO_OFFSET)
63#define OMAP1_IO_ADDRESS(pa) ((pa) - IO_OFFSET) 63#define __OMAP1_IO_ADDRESS(pa) ((pa) - IO_OFFSET)
64#define io_p2v(pa) ((pa) - IO_OFFSET) 64#define io_v2p(va) ((va) + IO_OFFSET)
65#define io_v2p(va) ((va) + IO_OFFSET)
66 65
67#elif defined(CONFIG_ARCH_OMAP2) 66#elif defined(CONFIG_ARCH_OMAP2)
68 67
@@ -90,11 +89,10 @@
90 89
91#endif 90#endif
92 91
93#define IO_OFFSET 0x90000000 92#define IO_OFFSET 0x90000000
94#define IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */ 93#define __IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */
95#define OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */ 94#define __OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */
96#define io_p2v(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */ 95#define io_v2p(va) ((va) - IO_OFFSET) /* Works for L3 and L4 */
97#define io_v2p(va) ((va) - IO_OFFSET) /* Works for L3 and L4 */
98 96
99/* DSP */ 97/* DSP */
100#define DSP_MEM_24XX_PHYS OMAP2420_DSP_MEM_BASE /* 0x58000000 */ 98#define DSP_MEM_24XX_PHYS OMAP2420_DSP_MEM_BASE /* 0x58000000 */
@@ -149,9 +147,8 @@
149 147
150 148
151#define IO_OFFSET 0x90000000 149#define IO_OFFSET 0x90000000
152#define IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */ 150#define __IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */
153#define OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */ 151#define __OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */
154#define io_p2v(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */
155#define io_v2p(va) ((va) - IO_OFFSET)/* Works for L3 and L4 */ 152#define io_v2p(va) ((va) - IO_OFFSET)/* Works for L3 and L4 */
156 153
157/* DSP */ 154/* DSP */
@@ -167,7 +164,14 @@
167 164
168#endif 165#endif
169 166
170#ifndef __ASSEMBLER__ 167#define IO_ADDRESS(pa) IOMEM(__IO_ADDRESS(pa))
168#define OMAP1_IO_ADDRESS(pa) IOMEM(__OMAP1_IO_ADDRESS(pa))
169#define OMAP2_IO_ADDRESS(pa) IOMEM(__OMAP2_IO_ADDRESS(pa))
170
171#ifdef __ASSEMBLER__
172#define IOMEM(x) x
173#else
174#define IOMEM(x) ((void __force __iomem *)(x))
171 175
172/* 176/*
173 * Functions to access the OMAP IO region 177 * Functions to access the OMAP IO region
@@ -178,13 +182,13 @@
178 * - DO NOT use hardcoded virtual addresses to allow changing the 182 * - DO NOT use hardcoded virtual addresses to allow changing the
179 * IO address space again if needed 183 * IO address space again if needed
180 */ 184 */
181#define omap_readb(a) (*(volatile unsigned char *)IO_ADDRESS(a)) 185#define omap_readb(a) __raw_readb(IO_ADDRESS(a))
182#define omap_readw(a) (*(volatile unsigned short *)IO_ADDRESS(a)) 186#define omap_readw(a) __raw_readw(IO_ADDRESS(a))
183#define omap_readl(a) (*(volatile unsigned int *)IO_ADDRESS(a)) 187#define omap_readl(a) __raw_readl(IO_ADDRESS(a))
184 188
185#define omap_writeb(v,a) (*(volatile unsigned char *)IO_ADDRESS(a) = (v)) 189#define omap_writeb(v,a) __raw_writeb(v, IO_ADDRESS(a))
186#define omap_writew(v,a) (*(volatile unsigned short *)IO_ADDRESS(a) = (v)) 190#define omap_writew(v,a) __raw_writew(v, IO_ADDRESS(a))
187#define omap_writel(v,a) (*(volatile unsigned int *)IO_ADDRESS(a) = (v)) 191#define omap_writel(v,a) __raw_writel(v, IO_ADDRESS(a))
188 192
189extern void omap1_map_common_io(void); 193extern void omap1_map_common_io(void);
190extern void omap1_init_common_hw(void); 194extern void omap1_init_common_hw(void);
@@ -192,6 +196,12 @@ extern void omap1_init_common_hw(void);
192extern void omap2_map_common_io(void); 196extern void omap2_map_common_io(void);
193extern void omap2_init_common_hw(void); 197extern void omap2_init_common_hw(void);
194 198
199#define __arch_ioremap(p,s,t) omap_ioremap(p,s,t)
200#define __arch_iounmap(v) omap_iounmap(v)
201
202void __iomem *omap_ioremap(unsigned long phys, size_t size, unsigned int type);
203void omap_iounmap(volatile void __iomem *addr);
204
195#endif 205#endif
196 206
197#endif 207#endif
diff --git a/arch/arm/plat-omap/include/mach/mcbsp.h b/arch/arm/plat-omap/include/mach/mcbsp.h
index 6eb44a92871d..a3074f2fb7ce 100644
--- a/arch/arm/plat-omap/include/mach/mcbsp.h
+++ b/arch/arm/plat-omap/include/mach/mcbsp.h
@@ -315,7 +315,7 @@ struct omap_mcbsp_ops {
315}; 315};
316 316
317struct omap_mcbsp_platform_data { 317struct omap_mcbsp_platform_data {
318 u32 virt_base; 318 unsigned long phys_base;
319 u8 dma_rx_sync, dma_tx_sync; 319 u8 dma_rx_sync, dma_tx_sync;
320 u16 rx_irq, tx_irq; 320 u16 rx_irq, tx_irq;
321 struct omap_mcbsp_ops *ops; 321 struct omap_mcbsp_ops *ops;
@@ -324,7 +324,8 @@ struct omap_mcbsp_platform_data {
324 324
325struct omap_mcbsp { 325struct omap_mcbsp {
326 struct device *dev; 326 struct device *dev;
327 u32 io_base; 327 unsigned long phys_base;
328 void __iomem *io_base;
328 u8 id; 329 u8 id;
329 u8 free; 330 u8 free;
330 omap_mcbsp_word_length rx_word_length; 331 omap_mcbsp_word_length rx_word_length;
diff --git a/arch/arm/plat-omap/include/mach/pm.h b/arch/arm/plat-omap/include/mach/pm.h
index bfa09325a5ff..6063e9681de2 100644
--- a/arch/arm/plat-omap/include/mach/pm.h
+++ b/arch/arm/plat-omap/include/mach/pm.h
@@ -39,11 +39,11 @@
39 * Register and offset definitions to be used in PM assembler code 39 * Register and offset definitions to be used in PM assembler code
40 * ---------------------------------------------------------------------------- 40 * ----------------------------------------------------------------------------
41 */ 41 */
42#define CLKGEN_REG_ASM_BASE io_p2v(0xfffece00) 42#define CLKGEN_REG_ASM_BASE IO_ADDRESS(0xfffece00)
43#define ARM_IDLECT1_ASM_OFFSET 0x04 43#define ARM_IDLECT1_ASM_OFFSET 0x04
44#define ARM_IDLECT2_ASM_OFFSET 0x08 44#define ARM_IDLECT2_ASM_OFFSET 0x08
45 45
46#define TCMIF_ASM_BASE io_p2v(0xfffecc00) 46#define TCMIF_ASM_BASE IO_ADDRESS(0xfffecc00)
47#define EMIFS_CONFIG_ASM_OFFSET 0x0c 47#define EMIFS_CONFIG_ASM_OFFSET 0x0c
48#define EMIFF_SDRAM_CONFIG_ASM_OFFSET 0x20 48#define EMIFF_SDRAM_CONFIG_ASM_OFFSET 0x20
49 49
diff --git a/arch/arm/plat-omap/include/mach/sdrc.h b/arch/arm/plat-omap/include/mach/sdrc.h
index 787b7acec546..d908eb527c8d 100644
--- a/arch/arm/plat-omap/include/mach/sdrc.h
+++ b/arch/arm/plat-omap/include/mach/sdrc.h
@@ -63,9 +63,9 @@
63 */ 63 */
64 64
65 65
66#define OMAP242X_SMS_REGADDR(reg) (void __iomem *)IO_ADDRESS(OMAP2420_SMS_BASE + reg) 66#define OMAP242X_SMS_REGADDR(reg) IO_ADDRESS(OMAP2420_SMS_BASE + reg)
67#define OMAP243X_SMS_REGADDR(reg) (void __iomem *)IO_ADDRESS(OMAP243X_SMS_BASE + reg) 67#define OMAP243X_SMS_REGADDR(reg) IO_ADDRESS(OMAP243X_SMS_BASE + reg)
68#define OMAP343X_SMS_REGADDR(reg) (void __iomem *)IO_ADDRESS(OMAP343X_SMS_BASE + reg) 68#define OMAP343X_SMS_REGADDR(reg) IO_ADDRESS(OMAP343X_SMS_BASE + reg)
69 69
70/* SMS register offsets - read/write with sms_{read,write}_reg() */ 70/* SMS register offsets - read/write with sms_{read,write}_reg() */
71 71
diff --git a/arch/arm/plat-omap/include/mach/serial.h b/arch/arm/plat-omap/include/mach/serial.h
index cc6bfa51ccb5..515b89bee966 100644
--- a/arch/arm/plat-omap/include/mach/serial.h
+++ b/arch/arm/plat-omap/include/mach/serial.h
@@ -26,12 +26,12 @@
26#define OMAP1510_BASE_BAUD (12000000/16) 26#define OMAP1510_BASE_BAUD (12000000/16)
27#define OMAP16XX_BASE_BAUD (48000000/16) 27#define OMAP16XX_BASE_BAUD (48000000/16)
28 28
29#define is_omap_port(p) ({int __ret = 0; \ 29#define is_omap_port(pt) ({int __ret = 0; \
30 if (p == IO_ADDRESS(OMAP_UART1_BASE) || \ 30 if ((pt)->port.mapbase == OMAP_UART1_BASE || \
31 p == IO_ADDRESS(OMAP_UART2_BASE) || \ 31 (pt)->port.mapbase == OMAP_UART2_BASE || \
32 p == IO_ADDRESS(OMAP_UART3_BASE)) \ 32 (pt)->port.mapbase == OMAP_UART3_BASE) \
33 __ret = 1; \ 33 __ret = 1; \
34 __ret; \ 34 __ret; \
35 }) 35 })
36 36
37#endif 37#endif
diff --git a/arch/arm/plat-omap/io.c b/arch/arm/plat-omap/io.c
new file mode 100644
index 000000000000..0253c456ed5b
--- /dev/null
+++ b/arch/arm/plat-omap/io.c
@@ -0,0 +1,83 @@
1#include <linux/module.h>
2#include <linux/io.h>
3#include <linux/mm.h>
4
5#include <mach/omap730.h>
6#include <mach/omap1510.h>
7#include <mach/omap16xx.h>
8#include <mach/omap24xx.h>
9#include <mach/omap34xx.h>
10
11#define BETWEEN(p,st,sz) ((p) >= (st) && (p) < ((st) + (sz)))
12#define XLATE(p,pst,vst) ((void __iomem *)((p) - (pst) + (vst)))
13
14/*
15 * Intercept ioremap() requests for addresses in our fixed mapping regions.
16 */
17void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type)
18{
19#ifdef CONFIG_ARCH_OMAP1
20 if (cpu_class_is_omap1()) {
21 if (BETWEEN(p, IO_PHYS, IO_SIZE))
22 return XLATE(p, IO_PHYS, IO_VIRT);
23 }
24 if (cpu_is_omap730()) {
25 if (BETWEEN(p, OMAP730_DSP_BASE, OMAP730_DSP_SIZE))
26 return XLATE(p, OMAP730_DSP_BASE, OMAP730_DSP_START);
27
28 if (BETWEEN(p, OMAP730_DSPREG_BASE, OMAP730_DSPREG_SIZE))
29 return XLATE(p, OMAP730_DSPREG_BASE,
30 OMAP730_DSPREG_START);
31 }
32 if (cpu_is_omap15xx()) {
33 if (BETWEEN(p, OMAP1510_DSP_BASE, OMAP1510_DSP_SIZE))
34 return XLATE(p, OMAP1510_DSP_BASE, OMAP1510_DSP_START);
35
36 if (BETWEEN(p, OMAP1510_DSPREG_BASE, OMAP1510_DSPREG_SIZE))
37 return XLATE(p, OMAP1510_DSPREG_BASE,
38 OMAP1510_DSPREG_START);
39 }
40 if (cpu_is_omap16xx()) {
41 if (BETWEEN(p, OMAP16XX_DSP_BASE, OMAP16XX_DSP_SIZE))
42 return XLATE(p, OMAP16XX_DSP_BASE, OMAP16XX_DSP_START);
43
44 if (BETWEEN(p, OMAP16XX_DSPREG_BASE, OMAP16XX_DSPREG_SIZE))
45 return XLATE(p, OMAP16XX_DSPREG_BASE,
46 OMAP16XX_DSPREG_START);
47 }
48#endif
49#ifdef CONFIG_ARCH_OMAP2
50 if (cpu_class_is_omap2()) {
51 if (BETWEEN(p, L3_24XX_PHYS, L3_24XX_SIZE))
52 return XLATE(p, L3_24XX_PHYS, L3_24XX_VIRT);
53 if (BETWEEN(p, L4_24XX_PHYS, L4_24XX_SIZE))
54 return XLATE(p, L4_24XX_PHYS, L4_24XX_VIRT);
55 if (BETWEEN(p, DSP_MEM_24XX_PHYS, DSP_MEM_24XX_SIZE))
56 return XLATE(p, DSP_MEM_24XX_PHYS, DSP_MEM_24XX_VIRT);
57 if (BETWEEN(p, DSP_IPI_24XX_PHYS, DSP_IPI_24XX_SIZE))
58 return XLATE(p, DSP_IPI_24XX_PHYS, DSP_IPI_24XX_SIZE);
59 if (BETWEEN(p, DSP_MMU_24XX_PHYS, DSP_MMU_24XX_SIZE))
60 return XLATE(p, DSP_MMU_24XX_PHYS, DSP_MMU_24XX_VIRT);
61 }
62#ifdef CONFIG_ARCH_OMAP2430
63 if (cpu_is_omap2430()) {
64 if (BETWEEN(p, L4_WK_243X_PHYS, L4_WK_243X_SIZE))
65 return XLATE(L4_WK_243X_PHYS, L4_WK_243X_VIRT);
66 if (BETWEEN(p, OMAP243X_GPMC_PHYS, OMAP243X_GPMC_SIZE))
67 return XLATE(OMAP243X_GPMC_PHYS, OMAP243X_GPMC_VIRT);
68 }
69#endif
70#endif
71
72 return __arm_ioremap(p, size, type);
73}
74EXPORT_SYMBOL(omap_ioremap);
75
76void omap_iounmap(volatile void __iomem *addr)
77{
78 unsigned long virt = (unsigned long)addr;
79
80 if (virt >= VMALLOC_START && virt < VMALLOC_END)
81 __iounmap(addr);
82}
83EXPORT_SYMBOL(omap_iounmap);
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index d0844050f2d2..e63990fd923f 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -126,7 +126,7 @@ static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
126 */ 126 */
127void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config) 127void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
128{ 128{
129 u32 io_base; 129 void __iomem *io_base;
130 130
131 if (!omap_mcbsp_check_valid_id(id)) { 131 if (!omap_mcbsp_check_valid_id(id)) {
132 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); 132 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
@@ -134,8 +134,8 @@ void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
134 } 134 }
135 135
136 io_base = mcbsp[id].io_base; 136 io_base = mcbsp[id].io_base;
137 dev_dbg(mcbsp[id].dev, "Configuring McBSP%d io_base: 0x%8x\n", 137 dev_dbg(mcbsp[id].dev, "Configuring McBSP%d phys_base: 0x%08lx\n",
138 mcbsp[id].id, io_base); 138 mcbsp[id].id, mcbsp[id].phys_base);
139 139
140 /* We write the given config */ 140 /* We write the given config */
141 OMAP_MCBSP_WRITE(io_base, SPCR2, config->spcr2); 141 OMAP_MCBSP_WRITE(io_base, SPCR2, config->spcr2);
@@ -273,7 +273,7 @@ EXPORT_SYMBOL(omap_mcbsp_free);
273 */ 273 */
274void omap_mcbsp_start(unsigned int id) 274void omap_mcbsp_start(unsigned int id)
275{ 275{
276 u32 io_base; 276 void __iomem *io_base;
277 u16 w; 277 u16 w;
278 278
279 if (!omap_mcbsp_check_valid_id(id)) { 279 if (!omap_mcbsp_check_valid_id(id)) {
@@ -310,7 +310,7 @@ EXPORT_SYMBOL(omap_mcbsp_start);
310 310
311void omap_mcbsp_stop(unsigned int id) 311void omap_mcbsp_stop(unsigned int id)
312{ 312{
313 u32 io_base; 313 void __iomem *io_base;
314 u16 w; 314 u16 w;
315 315
316 if (!omap_mcbsp_check_valid_id(id)) { 316 if (!omap_mcbsp_check_valid_id(id)) {
@@ -337,7 +337,7 @@ EXPORT_SYMBOL(omap_mcbsp_stop);
337/* polled mcbsp i/o operations */ 337/* polled mcbsp i/o operations */
338int omap_mcbsp_pollwrite(unsigned int id, u16 buf) 338int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
339{ 339{
340 u32 base; 340 void __iomem *base;
341 341
342 if (!omap_mcbsp_check_valid_id(id)) { 342 if (!omap_mcbsp_check_valid_id(id)) {
343 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); 343 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
@@ -379,7 +379,7 @@ EXPORT_SYMBOL(omap_mcbsp_pollwrite);
379 379
380int omap_mcbsp_pollread(unsigned int id, u16 *buf) 380int omap_mcbsp_pollread(unsigned int id, u16 *buf)
381{ 381{
382 u32 base; 382 void __iomem *base;
383 383
384 if (!omap_mcbsp_check_valid_id(id)) { 384 if (!omap_mcbsp_check_valid_id(id)) {
385 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); 385 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
@@ -424,7 +424,7 @@ EXPORT_SYMBOL(omap_mcbsp_pollread);
424 */ 424 */
425void omap_mcbsp_xmit_word(unsigned int id, u32 word) 425void omap_mcbsp_xmit_word(unsigned int id, u32 word)
426{ 426{
427 u32 io_base; 427 void __iomem *io_base;
428 omap_mcbsp_word_length word_length; 428 omap_mcbsp_word_length word_length;
429 429
430 if (!omap_mcbsp_check_valid_id(id)) { 430 if (!omap_mcbsp_check_valid_id(id)) {
@@ -445,7 +445,7 @@ EXPORT_SYMBOL(omap_mcbsp_xmit_word);
445 445
446u32 omap_mcbsp_recv_word(unsigned int id) 446u32 omap_mcbsp_recv_word(unsigned int id)
447{ 447{
448 u32 io_base; 448 void __iomem *io_base;
449 u16 word_lsb, word_msb = 0; 449 u16 word_lsb, word_msb = 0;
450 omap_mcbsp_word_length word_length; 450 omap_mcbsp_word_length word_length;
451 451
@@ -469,7 +469,7 @@ EXPORT_SYMBOL(omap_mcbsp_recv_word);
469 469
470int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word) 470int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
471{ 471{
472 u32 io_base; 472 void __iomem *io_base;
473 omap_mcbsp_word_length tx_word_length; 473 omap_mcbsp_word_length tx_word_length;
474 omap_mcbsp_word_length rx_word_length; 474 omap_mcbsp_word_length rx_word_length;
475 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0; 475 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
@@ -534,7 +534,8 @@ EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
534 534
535int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word) 535int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
536{ 536{
537 u32 io_base, clock_word = 0; 537 u32 clock_word = 0;
538 void __iomem *io_base;
538 omap_mcbsp_word_length tx_word_length; 539 omap_mcbsp_word_length tx_word_length;
539 omap_mcbsp_word_length rx_word_length; 540 omap_mcbsp_word_length rx_word_length;
540 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0; 541 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
@@ -651,7 +652,7 @@ int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer,
651 omap_set_dma_dest_params(mcbsp[id].dma_tx_lch, 652 omap_set_dma_dest_params(mcbsp[id].dma_tx_lch,
652 src_port, 653 src_port,
653 OMAP_DMA_AMODE_CONSTANT, 654 OMAP_DMA_AMODE_CONSTANT,
654 mcbsp[id].io_base + OMAP_MCBSP_REG_DXR1, 655 mcbsp[id].phys_base + OMAP_MCBSP_REG_DXR1,
655 0, 0); 656 0, 0);
656 657
657 omap_set_dma_src_params(mcbsp[id].dma_tx_lch, 658 omap_set_dma_src_params(mcbsp[id].dma_tx_lch,
@@ -712,7 +713,7 @@ int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer,
712 omap_set_dma_src_params(mcbsp[id].dma_rx_lch, 713 omap_set_dma_src_params(mcbsp[id].dma_rx_lch,
713 src_port, 714 src_port,
714 OMAP_DMA_AMODE_CONSTANT, 715 OMAP_DMA_AMODE_CONSTANT,
715 mcbsp[id].io_base + OMAP_MCBSP_REG_DRR1, 716 mcbsp[id].phys_base + OMAP_MCBSP_REG_DRR1,
716 0, 0); 717 0, 0);
717 718
718 omap_set_dma_dest_params(mcbsp[id].dma_rx_lch, 719 omap_set_dma_dest_params(mcbsp[id].dma_rx_lch,
@@ -830,7 +831,13 @@ static int __init omap_mcbsp_probe(struct platform_device *pdev)
830 mcbsp[id].dma_tx_lch = -1; 831 mcbsp[id].dma_tx_lch = -1;
831 mcbsp[id].dma_rx_lch = -1; 832 mcbsp[id].dma_rx_lch = -1;
832 833
833 mcbsp[id].io_base = pdata->virt_base; 834 mcbsp[id].phys_base = pdata->phys_base;
835 mcbsp[id].io_base = ioremap(pdata->phys_base, SZ_4K);
836 if (!mcbsp[id].io_base) {
837 ret = -ENOMEM;
838 goto err_ioremap;
839 }
840
834 /* Default I/O is IRQ based */ 841 /* Default I/O is IRQ based */
835 mcbsp[id].io_type = OMAP_MCBSP_IRQ_IO; 842 mcbsp[id].io_type = OMAP_MCBSP_IRQ_IO;
836 mcbsp[id].tx_irq = pdata->tx_irq; 843 mcbsp[id].tx_irq = pdata->tx_irq;
@@ -841,18 +848,22 @@ static int __init omap_mcbsp_probe(struct platform_device *pdev)
841 if (pdata->clk_name) 848 if (pdata->clk_name)
842 mcbsp[id].clk = clk_get(&pdev->dev, pdata->clk_name); 849 mcbsp[id].clk = clk_get(&pdev->dev, pdata->clk_name);
843 if (IS_ERR(mcbsp[id].clk)) { 850 if (IS_ERR(mcbsp[id].clk)) {
844 mcbsp[id].free = 0;
845 dev_err(&pdev->dev, 851 dev_err(&pdev->dev,
846 "Invalid clock configuration for McBSP%d.\n", 852 "Invalid clock configuration for McBSP%d.\n",
847 mcbsp[id].id); 853 mcbsp[id].id);
848 ret = -EINVAL; 854 ret = PTR_ERR(mcbsp[id].clk);
849 goto exit; 855 goto err_clk;
850 } 856 }
851 857
852 mcbsp[id].pdata = pdata; 858 mcbsp[id].pdata = pdata;
853 mcbsp[id].dev = &pdev->dev; 859 mcbsp[id].dev = &pdev->dev;
854 platform_set_drvdata(pdev, &mcbsp[id]); 860 platform_set_drvdata(pdev, &mcbsp[id]);
861 return 0;
855 862
863err_clk:
864 iounmap(mcbsp[id].io_base);
865err_ioremap:
866 mcbsp[id].free = 0;
856exit: 867exit:
857 return ret; 868 return ret;
858} 869}
@@ -871,6 +882,8 @@ static int omap_mcbsp_remove(struct platform_device *pdev)
871 clk_disable(mcbsp->clk); 882 clk_disable(mcbsp->clk);
872 clk_put(mcbsp->clk); 883 clk_put(mcbsp->clk);
873 884
885 iounmap(mcbsp->io_base);
886
874 mcbsp->clk = NULL; 887 mcbsp->clk = NULL;
875 mcbsp->free = 0; 888 mcbsp->free = 0;
876 mcbsp->dev = NULL; 889 mcbsp->dev = NULL;
diff --git a/arch/arm/plat-s3c24xx/gpiolib.c b/arch/arm/plat-s3c24xx/gpiolib.c
index 849f8469714a..3caec6bad3eb 100644
--- a/arch/arm/plat-s3c24xx/gpiolib.c
+++ b/arch/arm/plat-s3c24xx/gpiolib.c
@@ -39,7 +39,7 @@ static inline struct s3c24xx_gpio_chip *to_s3c_chip(struct gpio_chip *gpc)
39 * drivers themsevles. 39 * drivers themsevles.
40 */ 40 */
41 41
42int s3c24xx_gpiolib_input(struct gpio_chip *chip, unsigned offset) 42static int s3c24xx_gpiolib_input(struct gpio_chip *chip, unsigned offset)
43{ 43{
44 struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip); 44 struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip);
45 void __iomem *base = ourchip->base; 45 void __iomem *base = ourchip->base;
@@ -58,7 +58,7 @@ int s3c24xx_gpiolib_input(struct gpio_chip *chip, unsigned offset)
58 return 0; 58 return 0;
59} 59}
60 60
61int s3c24xx_gpiolib_output(struct gpio_chip *chip, 61static int s3c24xx_gpiolib_output(struct gpio_chip *chip,
62 unsigned offset, int value) 62 unsigned offset, int value)
63{ 63{
64 struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip); 64 struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip);
@@ -86,7 +86,8 @@ int s3c24xx_gpiolib_output(struct gpio_chip *chip,
86 return 0; 86 return 0;
87} 87}
88 88
89void s3c24xx_gpiolib_set(struct gpio_chip *chip, unsigned offset, int value) 89static void s3c24xx_gpiolib_set(struct gpio_chip *chip,
90 unsigned offset, int value)
90{ 91{
91 struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip); 92 struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip);
92 void __iomem *base = ourchip->base; 93 void __iomem *base = ourchip->base;
@@ -104,7 +105,7 @@ void s3c24xx_gpiolib_set(struct gpio_chip *chip, unsigned offset, int value)
104 local_irq_restore(flags); 105 local_irq_restore(flags);
105} 106}
106 107
107int s3c24xx_gpiolib_get(struct gpio_chip *chip, unsigned offset) 108static int s3c24xx_gpiolib_get(struct gpio_chip *chip, unsigned offset)
108{ 109{
109 struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip); 110 struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip);
110 unsigned long val; 111 unsigned long val;
@@ -150,8 +151,7 @@ static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
150 return 0; 151 return 0;
151} 152}
152 153
153 154static struct s3c24xx_gpio_chip gpios[] = {
154struct s3c24xx_gpio_chip gpios[] = {
155 [0] = { 155 [0] = {
156 .base = S3C24XX_GPIO_BASE(S3C2410_GPA0), 156 .base = S3C24XX_GPIO_BASE(S3C2410_GPA0),
157 .chip = { 157 .chip = {
diff --git a/arch/arm/plat-s3c24xx/pwm-clock.c b/arch/arm/plat-s3c24xx/pwm-clock.c
index ccfdc9d7ae4b..306cc9c6f9ef 100644
--- a/arch/arm/plat-s3c24xx/pwm-clock.c
+++ b/arch/arm/plat-s3c24xx/pwm-clock.c
@@ -89,7 +89,7 @@ static unsigned long clk_pwm_scaler_getrate(struct clk *clk)
89 89
90/* TODO - add set rate calls. */ 90/* TODO - add set rate calls. */
91 91
92struct clk clk_timer_scaler[] = { 92static struct clk clk_timer_scaler[] = {
93 [0] = { 93 [0] = {
94 .name = "pwm-scaler0", 94 .name = "pwm-scaler0",
95 .id = -1, 95 .id = -1,
@@ -102,7 +102,7 @@ struct clk clk_timer_scaler[] = {
102 }, 102 },
103}; 103};
104 104
105struct clk clk_timer_tclk[] = { 105static struct clk clk_timer_tclk[] = {
106 [0] = { 106 [0] = {
107 .name = "pwm-tclk0", 107 .name = "pwm-tclk0",
108 .id = -1, 108 .id = -1,
@@ -232,7 +232,7 @@ static int clk_pwm_tdiv_set_rate(struct clk *clk, unsigned long rate)
232 return 0; 232 return 0;
233} 233}
234 234
235struct pwm_tdiv_clk clk_timer_tdiv[] = { 235static struct pwm_tdiv_clk clk_timer_tdiv[] = {
236 [0] = { 236 [0] = {
237 .clk = { 237 .clk = {
238 .name = "pwm-tdiv", 238 .name = "pwm-tdiv",
diff --git a/arch/arm/plat-s3c24xx/pwm.c b/arch/arm/plat-s3c24xx/pwm.c
index 18c4bdc49a05..7a92c938542a 100644
--- a/arch/arm/plat-s3c24xx/pwm.c
+++ b/arch/arm/plat-s3c24xx/pwm.c
@@ -19,6 +19,7 @@
19#include <linux/io.h> 19#include <linux/io.h>
20#include <linux/pwm.h> 20#include <linux/pwm.h>
21 21
22#include <asm/plat-s3c24xx/devs.h>
22#include <asm/plat-s3c/regs-timer.h> 23#include <asm/plat-s3c/regs-timer.h>
23 24
24struct pwm_device { 25struct pwm_device {
@@ -38,7 +39,7 @@ struct pwm_device {
38 unsigned char pwm_id; 39 unsigned char pwm_id;
39}; 40};
40 41
41#define pwm_dbg(_pwm, msg...) dev_info(&(_pwm)->pdev->dev, msg) 42#define pwm_dbg(_pwm, msg...) dev_dbg(&(_pwm)->pdev->dev, msg)
42 43
43static struct clk *clk_scaler[2]; 44static struct clk *clk_scaler[2];
44 45
@@ -168,7 +169,7 @@ void pwm_disable(struct pwm_device *pwm)
168 169
169EXPORT_SYMBOL(pwm_disable); 170EXPORT_SYMBOL(pwm_disable);
170 171
171unsigned long pwm_calc_tin(struct pwm_device *pwm, unsigned long freq) 172static unsigned long pwm_calc_tin(struct pwm_device *pwm, unsigned long freq)
172{ 173{
173 unsigned long tin_parent_rate; 174 unsigned long tin_parent_rate;
174 unsigned int div; 175 unsigned int div;
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index f64d25973a37..4154ff1101fa 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -855,6 +855,7 @@ menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
855 855
856config PCI 856config PCI
857 bool "PCI support" 857 bool "PCI support"
858 depends on BROKEN
858 help 859 help
859 Support for PCI bus. 860 Support for PCI bus.
860 861
diff --git a/arch/blackfin/Makefile b/arch/blackfin/Makefile
index 9564731ad3a8..eac0533d6e4f 100644
--- a/arch/blackfin/Makefile
+++ b/arch/blackfin/Makefile
@@ -98,36 +98,20 @@ libs-y += arch/$(ARCH)/lib/
98 98
99drivers-$(CONFIG_OPROFILE) += arch/$(ARCH)/oprofile/ 99drivers-$(CONFIG_OPROFILE) += arch/$(ARCH)/oprofile/
100 100
101machdirs := $(patsubst %,arch/blackfin/mach-%/, $(machine-y))
101 102
103KBUILD_CFLAGS += -Iarch/$(ARCH)/include/
104KBUILD_CFLAGS += -Iarch/$(ARCH)/mach-$(MACHINE)/include
102 105
103# Update machine arch symlinks if something which affects 106KBUILD_CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs))
104# them changed. We use .mach to indicate when they were updated
105# last, otherwise make uses the target directory mtime.
106
107 show_mach_symlink = :
108 quiet_show_mach_symlink = echo ' SYMLINK include/asm-$(ARCH)/mach-$(MACHINE) -> include/asm-$(ARCH)/mach'
109silent_show_mach_symlink = :
110include/asm-blackfin/.mach: $(wildcard include/config/arch/*.h) include/config/auto.conf
111 @$($(quiet)show_mach_symlink)
112ifneq ($(KBUILD_SRC),)
113 $(Q)mkdir -p include/asm-$(ARCH)
114 $(Q)ln -fsn $(srctree)/include/asm-$(ARCH)/mach-$(MACHINE) include/asm-$(ARCH)/mach
115else
116 $(Q)ln -fsn mach-$(MACHINE) include/asm-$(ARCH)/mach
117endif
118 @touch $@
119 107
120CLEAN_FILES += \ 108CLEAN_FILES += \
121 include/asm-$(ARCH)/asm-offsets.h \ 109 arch/$(ARCH)/include/asm/asm-offsets.h \
122 arch/$(ARCH)/kernel/asm-offsets.s \ 110 arch/$(ARCH)/kernel/asm-offsets.s \
123 include/asm-$(ARCH)/mach \
124 include/asm-$(ARCH)/.mach
125 111
126archprepare: include/asm-blackfin/.mach
127archclean: 112archclean:
128 $(Q)$(MAKE) $(clean)=$(boot) 113 $(Q)$(MAKE) $(clean)=$(boot)
129 114
130
131INSTALL_PATH ?= /tftpboot 115INSTALL_PATH ?= /tftpboot
132boot := arch/$(ARCH)/boot 116boot := arch/$(ARCH)/boot
133BOOT_TARGETS = vmImage 117BOOT_TARGETS = vmImage
diff --git a/arch/blackfin/include/asm/.gitignore b/arch/blackfin/include/asm/.gitignore
new file mode 100644
index 000000000000..7858564a4466
--- /dev/null
+++ b/arch/blackfin/include/asm/.gitignore
@@ -0,0 +1 @@
+mach
diff --git a/arch/blackfin/include/asm/Kbuild b/arch/blackfin/include/asm/Kbuild
new file mode 100644
index 000000000000..606ecfdcc962
--- /dev/null
+++ b/arch/blackfin/include/asm/Kbuild
@@ -0,0 +1,3 @@
1include include/asm-generic/Kbuild.asm
2
3unifdef-y += fixed_code.h
diff --git a/arch/blackfin/include/asm/a.out.h b/arch/blackfin/include/asm/a.out.h
new file mode 100644
index 000000000000..6c3d652ebd33
--- /dev/null
+++ b/arch/blackfin/include/asm/a.out.h
@@ -0,0 +1,19 @@
1#ifndef __BFIN_A_OUT_H__
2#define __BFIN_A_OUT_H__
3
4struct exec {
5 unsigned long a_info; /* Use macros N_MAGIC, etc for access */
6 unsigned a_text; /* length of text, in bytes */
7 unsigned a_data; /* length of data, in bytes */
8 unsigned a_bss; /* length of uninitialized data area for file, in bytes */
9 unsigned a_syms; /* length of symbol table data in file, in bytes */
10 unsigned a_entry; /* start address */
11 unsigned a_trsize; /* length of relocation info for text, in bytes */
12 unsigned a_drsize; /* length of relocation info for data, in bytes */
13};
14
15#define N_TRSIZE(a) ((a).a_trsize)
16#define N_DRSIZE(a) ((a).a_drsize)
17#define N_SYMSIZE(a) ((a).a_syms)
18
19#endif /* __BFIN_A_OUT_H__ */
diff --git a/arch/blackfin/include/asm/atomic.h b/arch/blackfin/include/asm/atomic.h
new file mode 100644
index 000000000000..7cf508718605
--- /dev/null
+++ b/arch/blackfin/include/asm/atomic.h
@@ -0,0 +1,144 @@
1#ifndef __ARCH_BLACKFIN_ATOMIC__
2#define __ARCH_BLACKFIN_ATOMIC__
3
4#include <asm/system.h> /* local_irq_XXX() */
5
6/*
7 * Atomic operations that C can't guarantee us. Useful for
8 * resource counting etc..
9 *
10 * Generally we do not concern about SMP BFIN systems, so we don't have
11 * to deal with that.
12 *
13 * Tony Kou (tonyko@lineo.ca) Lineo Inc. 2001
14 */
15
16typedef struct {
17 int counter;
18} atomic_t;
19#define ATOMIC_INIT(i) { (i) }
20
21#define atomic_read(v) ((v)->counter)
22#define atomic_set(v, i) (((v)->counter) = i)
23
24static __inline__ void atomic_add(int i, atomic_t * v)
25{
26 long flags;
27
28 local_irq_save(flags);
29 v->counter += i;
30 local_irq_restore(flags);
31}
32
33static __inline__ void atomic_sub(int i, atomic_t * v)
34{
35 long flags;
36
37 local_irq_save(flags);
38 v->counter -= i;
39 local_irq_restore(flags);
40
41}
42
43static inline int atomic_add_return(int i, atomic_t * v)
44{
45 int __temp = 0;
46 long flags;
47
48 local_irq_save(flags);
49 v->counter += i;
50 __temp = v->counter;
51 local_irq_restore(flags);
52
53
54 return __temp;
55}
56
57#define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0)
58static inline int atomic_sub_return(int i, atomic_t * v)
59{
60 int __temp = 0;
61 long flags;
62
63 local_irq_save(flags);
64 v->counter -= i;
65 __temp = v->counter;
66 local_irq_restore(flags);
67
68 return __temp;
69}
70
71static __inline__ void atomic_inc(volatile atomic_t * v)
72{
73 long flags;
74
75 local_irq_save(flags);
76 v->counter++;
77 local_irq_restore(flags);
78}
79
80#define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
81#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
82
83#define atomic_add_unless(v, a, u) \
84({ \
85 int c, old; \
86 c = atomic_read(v); \
87 while (c != (u) && (old = atomic_cmpxchg((v), c, c + (a))) != c) \
88 c = old; \
89 c != (u); \
90})
91#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
92
93static __inline__ void atomic_dec(volatile atomic_t * v)
94{
95 long flags;
96
97 local_irq_save(flags);
98 v->counter--;
99 local_irq_restore(flags);
100}
101
102static __inline__ void atomic_clear_mask(unsigned int mask, atomic_t * v)
103{
104 long flags;
105
106 local_irq_save(flags);
107 v->counter &= ~mask;
108 local_irq_restore(flags);
109}
110
111static __inline__ void atomic_set_mask(unsigned int mask, atomic_t * v)
112{
113 long flags;
114
115 local_irq_save(flags);
116 v->counter |= mask;
117 local_irq_restore(flags);
118}
119
120/* Atomic operations are already serializing */
121#define smp_mb__before_atomic_dec() barrier()
122#define smp_mb__after_atomic_dec() barrier()
123#define smp_mb__before_atomic_inc() barrier()
124#define smp_mb__after_atomic_inc() barrier()
125
126#define atomic_dec_return(v) atomic_sub_return(1,(v))
127#define atomic_inc_return(v) atomic_add_return(1,(v))
128
129/*
130 * atomic_inc_and_test - increment and test
131 * @v: pointer of type atomic_t
132 *
133 * Atomically increments @v by 1
134 * and returns true if the result is zero, or false for all
135 * other cases.
136 */
137#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
138
139#define atomic_sub_and_test(i,v) (atomic_sub_return((i), (v)) == 0)
140#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0)
141
142#include <asm-generic/atomic.h>
143
144#endif /* __ARCH_BLACKFIN_ATOMIC __ */
diff --git a/arch/blackfin/include/asm/auxvec.h b/arch/blackfin/include/asm/auxvec.h
new file mode 100644
index 000000000000..215506cd87b7
--- /dev/null
+++ b/arch/blackfin/include/asm/auxvec.h
@@ -0,0 +1,4 @@
1#ifndef __ASMBFIN_AUXVEC_H
2#define __ASMBFIN_AUXVEC_H
3
4#endif
diff --git a/arch/blackfin/include/asm/bfin-global.h b/arch/blackfin/include/asm/bfin-global.h
new file mode 100644
index 000000000000..7ba70de66f2b
--- /dev/null
+++ b/arch/blackfin/include/asm/bfin-global.h
@@ -0,0 +1,117 @@
1/*
2 * File: include/asm-blackfin/bfin-global.h
3 * Based on:
4 * Author: *
5 * Created:
6 * Description: Global extern defines for blackfin
7 *
8 * Modified:
9 * Copyright 2004-2006 Analog Devices Inc.
10 *
11 * Bugs: Enter bugs at http://blackfin.uclinux.org/
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, see the file COPYING, or write
25 * to the Free Software Foundation, Inc.,
26 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
27 */
28
29#ifndef _BFIN_GLOBAL_H_
30#define _BFIN_GLOBAL_H_
31
32#ifndef __ASSEMBLY__
33
34#include <asm-generic/sections.h>
35#include <asm/ptrace.h>
36#include <asm/user.h>
37#include <linux/linkage.h>
38#include <linux/types.h>
39
40#if defined(CONFIG_DMA_UNCACHED_4M)
41# define DMA_UNCACHED_REGION (4 * 1024 * 1024)
42#elif defined(CONFIG_DMA_UNCACHED_2M)
43# define DMA_UNCACHED_REGION (2 * 1024 * 1024)
44#elif defined(CONFIG_DMA_UNCACHED_1M)
45# define DMA_UNCACHED_REGION (1024 * 1024)
46#else
47# define DMA_UNCACHED_REGION (0)
48#endif
49
50extern unsigned long get_cclk(void);
51extern unsigned long get_sclk(void);
52extern unsigned long sclk_to_usecs(unsigned long sclk);
53extern unsigned long usecs_to_sclk(unsigned long usecs);
54
55extern void dump_bfin_process(struct pt_regs *regs);
56extern void dump_bfin_mem(struct pt_regs *regs);
57extern void dump_bfin_trace_buffer(void);
58
59/* init functions only */
60extern int init_arch_irq(void);
61extern void bfin_icache_init(void);
62extern void bfin_dcache_init(void);
63extern void init_exception_vectors(void);
64extern void program_IAR(void);
65
66extern void bfin_reset(void);
67extern asmlinkage void lower_to_irq14(void);
68extern asmlinkage void bfin_return_from_exception(void);
69extern asmlinkage void evt14_softirq(void);
70extern asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs);
71extern int bfin_internal_set_wake(unsigned int irq, unsigned int state);
72
73extern void *l1_data_A_sram_alloc(size_t);
74extern void *l1_data_B_sram_alloc(size_t);
75extern void *l1_inst_sram_alloc(size_t);
76extern void *l1_data_sram_alloc(size_t);
77extern void *l1_data_sram_zalloc(size_t);
78extern void *l2_sram_alloc(size_t);
79extern void *l2_sram_zalloc(size_t);
80extern int l1_data_A_sram_free(const void*);
81extern int l1_data_B_sram_free(const void*);
82extern int l1_inst_sram_free(const void*);
83extern int l1_data_sram_free(const void*);
84extern int l2_sram_free(const void *);
85extern int sram_free(const void*);
86
87#define L1_INST_SRAM 0x00000001
88#define L1_DATA_A_SRAM 0x00000002
89#define L1_DATA_B_SRAM 0x00000004
90#define L1_DATA_SRAM 0x00000006
91#define L2_SRAM 0x00000008
92extern void *sram_alloc_with_lsl(size_t, unsigned long);
93extern int sram_free_with_lsl(const void*);
94
95extern const char bfin_board_name[];
96
97extern unsigned long bfin_sic_iwr[];
98extern unsigned vr_wakeup;
99extern u16 _bfin_swrst; /* shadow for Software Reset Register (SWRST) */
100extern unsigned long _ramstart, _ramend, _rambase;
101extern unsigned long memory_start, memory_end, physical_mem_end;
102extern char _stext_l1[], _etext_l1[], _sdata_l1[], _edata_l1[], _sbss_l1[],
103 _ebss_l1[], _l1_lma_start[], _sdata_b_l1[], _ebss_b_l1[],
104 _stext_l2[], _etext_l2[], _sdata_l2[], _edata_l2[], _sbss_l2[],
105 _ebss_l2[], _l2_lma_start[];
106
107/* only used when CONFIG_MTD_UCLINUX */
108extern unsigned long memory_mtd_start, memory_mtd_end, mtd_size;
109
110#ifdef CONFIG_BFIN_ICACHE_LOCK
111extern void cache_grab_lock(int way);
112extern void cache_lock(int way);
113#endif
114
115#endif
116
117#endif /* _BLACKFIN_H_ */
diff --git a/arch/blackfin/include/asm/bfin5xx_spi.h b/arch/blackfin/include/asm/bfin5xx_spi.h
new file mode 100644
index 000000000000..9fa19158e38d
--- /dev/null
+++ b/arch/blackfin/include/asm/bfin5xx_spi.h
@@ -0,0 +1,137 @@
1/************************************************************
2
3* Copyright (C) 2006-2008, Analog Devices. All Rights Reserved
4*
5* FILE bfin5xx_spi.h
6* PROGRAMMER(S): Luke Yang (Analog Devices Inc.)
7*
8*
9* DATE OF CREATION: March. 10th 2006
10*
11* SYNOPSIS:
12*
13* DESCRIPTION: header file for SPI controller driver for Blackfin5xx.
14**************************************************************
15
16* MODIFICATION HISTORY:
17* March 10, 2006 bfin5xx_spi.h Created. (Luke Yang)
18
19************************************************************/
20
21#ifndef _SPI_CHANNEL_H_
22#define _SPI_CHANNEL_H_
23
24#define SPI_READ 0
25#define SPI_WRITE 1
26
27#define SPI_CTRL_OFF 0x0
28#define SPI_FLAG_OFF 0x4
29#define SPI_STAT_OFF 0x8
30#define SPI_TXBUFF_OFF 0xc
31#define SPI_RXBUFF_OFF 0x10
32#define SPI_BAUD_OFF 0x14
33#define SPI_SHAW_OFF 0x18
34
35
36#define BIT_CTL_ENABLE 0x4000
37#define BIT_CTL_OPENDRAIN 0x2000
38#define BIT_CTL_MASTER 0x1000
39#define BIT_CTL_POLAR 0x0800
40#define BIT_CTL_PHASE 0x0400
41#define BIT_CTL_BITORDER 0x0200
42#define BIT_CTL_WORDSIZE 0x0100
43#define BIT_CTL_MISOENABLE 0x0020
44#define BIT_CTL_RXMOD 0x0000
45#define BIT_CTL_TXMOD 0x0001
46#define BIT_CTL_TIMOD_DMA_TX 0x0003
47#define BIT_CTL_TIMOD_DMA_RX 0x0002
48#define BIT_CTL_SENDOPT 0x0004
49#define BIT_CTL_TIMOD 0x0003
50
51#define BIT_STAT_SPIF 0x0001
52#define BIT_STAT_MODF 0x0002
53#define BIT_STAT_TXE 0x0004
54#define BIT_STAT_TXS 0x0008
55#define BIT_STAT_RBSY 0x0010
56#define BIT_STAT_RXS 0x0020
57#define BIT_STAT_TXCOL 0x0040
58#define BIT_STAT_CLR 0xFFFF
59
60#define BIT_STU_SENDOVER 0x0001
61#define BIT_STU_RECVFULL 0x0020
62
63#define CFG_SPI_ENABLE 1
64#define CFG_SPI_DISABLE 0
65
66#define CFG_SPI_OUTENABLE 1
67#define CFG_SPI_OUTDISABLE 0
68
69#define CFG_SPI_ACTLOW 1
70#define CFG_SPI_ACTHIGH 0
71
72#define CFG_SPI_PHASESTART 1
73#define CFG_SPI_PHASEMID 0
74
75#define CFG_SPI_MASTER 1
76#define CFG_SPI_SLAVE 0
77
78#define CFG_SPI_SENELAST 0
79#define CFG_SPI_SENDZERO 1
80
81#define CFG_SPI_RCVFLUSH 1
82#define CFG_SPI_RCVDISCARD 0
83
84#define CFG_SPI_LSBFIRST 1
85#define CFG_SPI_MSBFIRST 0
86
87#define CFG_SPI_WORDSIZE16 1
88#define CFG_SPI_WORDSIZE8 0
89
90#define CFG_SPI_MISOENABLE 1
91#define CFG_SPI_MISODISABLE 0
92
93#define CFG_SPI_READ 0x00
94#define CFG_SPI_WRITE 0x01
95#define CFG_SPI_DMAREAD 0x02
96#define CFG_SPI_DMAWRITE 0x03
97
98#define CFG_SPI_CSCLEARALL 0
99#define CFG_SPI_CHIPSEL1 1
100#define CFG_SPI_CHIPSEL2 2
101#define CFG_SPI_CHIPSEL3 3
102#define CFG_SPI_CHIPSEL4 4
103#define CFG_SPI_CHIPSEL5 5
104#define CFG_SPI_CHIPSEL6 6
105#define CFG_SPI_CHIPSEL7 7
106
107#define CFG_SPI_CS1VALUE 1
108#define CFG_SPI_CS2VALUE 2
109#define CFG_SPI_CS3VALUE 3
110#define CFG_SPI_CS4VALUE 4
111#define CFG_SPI_CS5VALUE 5
112#define CFG_SPI_CS6VALUE 6
113#define CFG_SPI_CS7VALUE 7
114
115#define CMD_SPI_SET_BAUDRATE 2
116#define CMD_SPI_GET_SYSTEMCLOCK 25
117#define CMD_SPI_SET_WRITECONTINUOUS 26
118
119/* device.platform_data for SSP controller devices */
120struct bfin5xx_spi_master {
121 u16 num_chipselect;
122 u8 enable_dma;
123 u16 pin_req[4];
124};
125
126/* spi_board_info.controller_data for SPI slave devices,
127 * copied to spi_device.platform_data ... mostly for dma tuning
128 */
129struct bfin5xx_spi_chip {
130 u16 ctl_reg;
131 u8 enable_dma;
132 u8 bits_per_word;
133 u8 cs_change_per_word;
134 u16 cs_chg_udelay; /* Some devices require 16-bit delays */
135};
136
137#endif /* _SPI_CHANNEL_H_ */
diff --git a/arch/blackfin/include/asm/bfin_simple_timer.h b/arch/blackfin/include/asm/bfin_simple_timer.h
new file mode 100644
index 000000000000..fccbb595464a
--- /dev/null
+++ b/arch/blackfin/include/asm/bfin_simple_timer.h
@@ -0,0 +1,13 @@
1#ifndef _bfin_simple_timer_h_
2#define _bfin_simple_timer_h_
3
4#include <linux/ioctl.h>
5
6#define BFIN_SIMPLE_TIMER_IOCTL_MAGIC 't'
7
8#define BFIN_SIMPLE_TIMER_SET_PERIOD _IO (BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 2)
9#define BFIN_SIMPLE_TIMER_START _IO (BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 6)
10#define BFIN_SIMPLE_TIMER_STOP _IO (BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 8)
11#define BFIN_SIMPLE_TIMER_READ _IO (BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 10)
12
13#endif
diff --git a/arch/blackfin/include/asm/bfin_sport.h b/arch/blackfin/include/asm/bfin_sport.h
new file mode 100644
index 000000000000..c76ed8def302
--- /dev/null
+++ b/arch/blackfin/include/asm/bfin_sport.h
@@ -0,0 +1,175 @@
1/*
2 * File: include/asm-blackfin/bfin_sport.h
3 * Based on:
4 * Author: Roy Huang (roy.huang@analog.com)
5 *
6 * Created: Thu Aug. 24 2006
7 * Description:
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#ifndef __BFIN_SPORT_H__
31#define __BFIN_SPORT_H__
32
33#define SPORT_MAJOR 237
34#define SPORT_NR_DEVS 2
35
36/* Sport mode: it can be set to TDM, i2s or others */
37#define NORM_MODE 0x0
38#define TDM_MODE 0x1
39#define I2S_MODE 0x2
40
41/* Data format, normal, a-law or u-law */
42#define NORM_FORMAT 0x0
43#define ALAW_FORMAT 0x2
44#define ULAW_FORMAT 0x3
45struct sport_register;
46
47/* Function driver which use sport must initialize the structure */
48struct sport_config {
49 /*TDM (multichannels), I2S or other mode */
50 unsigned int mode:3;
51
52 /* if TDM mode is selected, channels must be set */
53 int channels; /* Must be in 8 units */
54 unsigned int frame_delay:4; /* Delay between frame sync pulse and first bit */
55
56 /* I2S mode */
57 unsigned int right_first:1; /* Right stereo channel first */
58
59 /* In mormal mode, the following item need to be set */
60 unsigned int lsb_first:1; /* order of transmit or receive data */
61 unsigned int fsync:1; /* Frame sync required */
62 unsigned int data_indep:1; /* data independent frame sync generated */
63 unsigned int act_low:1; /* Active low TFS */
64 unsigned int late_fsync:1; /* Late frame sync */
65 unsigned int tckfe:1;
66 unsigned int sec_en:1; /* Secondary side enabled */
67
68 /* Choose clock source */
69 unsigned int int_clk:1; /* Internal or external clock */
70
71 /* If external clock is used, the following fields are ignored */
72 int serial_clk;
73 int fsync_clk;
74
75 unsigned int data_format:2; /*Normal, u-law or a-law */
76
77 int word_len; /* How length of the word in bits, 3-32 bits */
78 int dma_enabled;
79};
80
81struct sport_register {
82 unsigned short tcr1;
83 unsigned short reserved0;
84 unsigned short tcr2;
85 unsigned short reserved1;
86 unsigned short tclkdiv;
87 unsigned short reserved2;
88 unsigned short tfsdiv;
89 unsigned short reserved3;
90 unsigned long tx;
91 unsigned long reserved_l0;
92 unsigned long rx;
93 unsigned long reserved_l1;
94 unsigned short rcr1;
95 unsigned short reserved4;
96 unsigned short rcr2;
97 unsigned short reserved5;
98 unsigned short rclkdiv;
99 unsigned short reserved6;
100 unsigned short rfsdiv;
101 unsigned short reserved7;
102 unsigned short stat;
103 unsigned short reserved8;
104 unsigned short chnl;
105 unsigned short reserved9;
106 unsigned short mcmc1;
107 unsigned short reserved10;
108 unsigned short mcmc2;
109 unsigned short reserved11;
110 unsigned long mtcs0;
111 unsigned long mtcs1;
112 unsigned long mtcs2;
113 unsigned long mtcs3;
114 unsigned long mrcs0;
115 unsigned long mrcs1;
116 unsigned long mrcs2;
117 unsigned long mrcs3;
118};
119
120#define SPORT_IOC_MAGIC 'P'
121#define SPORT_IOC_CONFIG _IOWR('P', 0x01, struct sport_config)
122
123/* Test purpose */
124#define ENABLE_AD73311 _IOWR('P', 0x02, int)
125
126struct sport_dev {
127 struct cdev cdev; /* Char device structure */
128
129 int sport_num;
130
131 int dma_rx_chan;
132 int dma_tx_chan;
133
134 int rx_irq;
135 unsigned char *rx_buf; /* Buffer store the received data */
136 int rx_len; /* How many bytes will be received */
137 int rx_received; /* How many bytes has been received */
138
139 int tx_irq;
140 const unsigned char *tx_buf;
141 int tx_len;
142 int tx_sent;
143
144 int sport_err_irq;
145
146 struct mutex mutex; /* mutual exclusion semaphore */
147 struct task_struct *task;
148
149 wait_queue_head_t waitq;
150 int wait_con;
151 struct sport_register *regs;
152 struct sport_config config;
153};
154
155#define SPORT_TCR1 0
156#define SPORT_TCR2 1
157#define SPORT_TCLKDIV 2
158#define SPORT_TFSDIV 3
159#define SPORT_RCR1 8
160#define SPORT_RCR2 9
161#define SPORT_RCLKDIV 10
162#define SPORT_RFSDIV 11
163#define SPORT_CHANNEL 13
164#define SPORT_MCMC1 14
165#define SPORT_MCMC2 15
166#define SPORT_MTCS0 16
167#define SPORT_MTCS1 17
168#define SPORT_MTCS2 18
169#define SPORT_MTCS3 19
170#define SPORT_MRCS0 20
171#define SPORT_MRCS1 21
172#define SPORT_MRCS2 22
173#define SPORT_MRCS3 23
174
175#endif /*__BFIN_SPORT_H__*/
diff --git a/arch/blackfin/include/asm/bitops.h b/arch/blackfin/include/asm/bitops.h
new file mode 100644
index 000000000000..b39a175c79c1
--- /dev/null
+++ b/arch/blackfin/include/asm/bitops.h
@@ -0,0 +1,218 @@
1#ifndef _BLACKFIN_BITOPS_H
2#define _BLACKFIN_BITOPS_H
3
4/*
5 * Copyright 1992, Linus Torvalds.
6 */
7
8#include <linux/compiler.h>
9#include <asm/byteorder.h> /* swab32 */
10#include <asm/system.h> /* save_flags */
11
12#ifdef __KERNEL__
13
14#ifndef _LINUX_BITOPS_H
15#error only <linux/bitops.h> can be included directly
16#endif
17
18#include <asm-generic/bitops/ffs.h>
19#include <asm-generic/bitops/__ffs.h>
20#include <asm-generic/bitops/sched.h>
21#include <asm-generic/bitops/ffz.h>
22
23static __inline__ void set_bit(int nr, volatile unsigned long *addr)
24{
25 int *a = (int *)addr;
26 int mask;
27 unsigned long flags;
28
29 a += nr >> 5;
30 mask = 1 << (nr & 0x1f);
31 local_irq_save(flags);
32 *a |= mask;
33 local_irq_restore(flags);
34}
35
36static __inline__ void __set_bit(int nr, volatile unsigned long *addr)
37{
38 int *a = (int *)addr;
39 int mask;
40
41 a += nr >> 5;
42 mask = 1 << (nr & 0x1f);
43 *a |= mask;
44}
45
46/*
47 * clear_bit() doesn't provide any barrier for the compiler.
48 */
49#define smp_mb__before_clear_bit() barrier()
50#define smp_mb__after_clear_bit() barrier()
51
52static __inline__ void clear_bit(int nr, volatile unsigned long *addr)
53{
54 int *a = (int *)addr;
55 int mask;
56 unsigned long flags;
57 a += nr >> 5;
58 mask = 1 << (nr & 0x1f);
59 local_irq_save(flags);
60 *a &= ~mask;
61 local_irq_restore(flags);
62}
63
64static __inline__ void __clear_bit(int nr, volatile unsigned long *addr)
65{
66 int *a = (int *)addr;
67 int mask;
68
69 a += nr >> 5;
70 mask = 1 << (nr & 0x1f);
71 *a &= ~mask;
72}
73
74static __inline__ void change_bit(int nr, volatile unsigned long *addr)
75{
76 int mask, flags;
77 unsigned long *ADDR = (unsigned long *)addr;
78
79 ADDR += nr >> 5;
80 mask = 1 << (nr & 31);
81 local_irq_save(flags);
82 *ADDR ^= mask;
83 local_irq_restore(flags);
84}
85
86static __inline__ void __change_bit(int nr, volatile unsigned long *addr)
87{
88 int mask;
89 unsigned long *ADDR = (unsigned long *)addr;
90
91 ADDR += nr >> 5;
92 mask = 1 << (nr & 31);
93 *ADDR ^= mask;
94}
95
96static __inline__ int test_and_set_bit(int nr, void *addr)
97{
98 int mask, retval;
99 volatile unsigned int *a = (volatile unsigned int *)addr;
100 unsigned long flags;
101
102 a += nr >> 5;
103 mask = 1 << (nr & 0x1f);
104 local_irq_save(flags);
105 retval = (mask & *a) != 0;
106 *a |= mask;
107 local_irq_restore(flags);
108
109 return retval;
110}
111
112static __inline__ int __test_and_set_bit(int nr, volatile unsigned long *addr)
113{
114 int mask, retval;
115 volatile unsigned int *a = (volatile unsigned int *)addr;
116
117 a += nr >> 5;
118 mask = 1 << (nr & 0x1f);
119 retval = (mask & *a) != 0;
120 *a |= mask;
121 return retval;
122}
123
124static __inline__ int test_and_clear_bit(int nr, volatile unsigned long *addr)
125{
126 int mask, retval;
127 volatile unsigned int *a = (volatile unsigned int *)addr;
128 unsigned long flags;
129
130 a += nr >> 5;
131 mask = 1 << (nr & 0x1f);
132 local_irq_save(flags);
133 retval = (mask & *a) != 0;
134 *a &= ~mask;
135 local_irq_restore(flags);
136
137 return retval;
138}
139
140static __inline__ int __test_and_clear_bit(int nr, volatile unsigned long *addr)
141{
142 int mask, retval;
143 volatile unsigned int *a = (volatile unsigned int *)addr;
144
145 a += nr >> 5;
146 mask = 1 << (nr & 0x1f);
147 retval = (mask & *a) != 0;
148 *a &= ~mask;
149 return retval;
150}
151
152static __inline__ int test_and_change_bit(int nr, volatile unsigned long *addr)
153{
154 int mask, retval;
155 volatile unsigned int *a = (volatile unsigned int *)addr;
156 unsigned long flags;
157
158 a += nr >> 5;
159 mask = 1 << (nr & 0x1f);
160 local_irq_save(flags);
161 retval = (mask & *a) != 0;
162 *a ^= mask;
163 local_irq_restore(flags);
164 return retval;
165}
166
167static __inline__ int __test_and_change_bit(int nr,
168 volatile unsigned long *addr)
169{
170 int mask, retval;
171 volatile unsigned int *a = (volatile unsigned int *)addr;
172
173 a += nr >> 5;
174 mask = 1 << (nr & 0x1f);
175 retval = (mask & *a) != 0;
176 *a ^= mask;
177 return retval;
178}
179
180/*
181 * This routine doesn't need to be atomic.
182 */
183static __inline__ int __constant_test_bit(int nr, const void *addr)
184{
185 return ((1UL << (nr & 31)) &
186 (((const volatile unsigned int *)addr)[nr >> 5])) != 0;
187}
188
189static __inline__ int __test_bit(int nr, const void *addr)
190{
191 int *a = (int *)addr;
192 int mask;
193
194 a += nr >> 5;
195 mask = 1 << (nr & 0x1f);
196 return ((mask & *a) != 0);
197}
198
199#define test_bit(nr,addr) \
200(__builtin_constant_p(nr) ? \
201 __constant_test_bit((nr),(addr)) : \
202 __test_bit((nr),(addr)))
203
204#include <asm-generic/bitops/find.h>
205#include <asm-generic/bitops/hweight.h>
206#include <asm-generic/bitops/lock.h>
207
208#include <asm-generic/bitops/ext2-atomic.h>
209#include <asm-generic/bitops/ext2-non-atomic.h>
210
211#include <asm-generic/bitops/minix.h>
212
213#endif /* __KERNEL__ */
214
215#include <asm-generic/bitops/fls.h>
216#include <asm-generic/bitops/fls64.h>
217
218#endif /* _BLACKFIN_BITOPS_H */
diff --git a/arch/blackfin/include/asm/blackfin.h b/arch/blackfin/include/asm/blackfin.h
new file mode 100644
index 000000000000..8749b0e321ab
--- /dev/null
+++ b/arch/blackfin/include/asm/blackfin.h
@@ -0,0 +1,92 @@
1/*
2 * Common header file for blackfin family of processors.
3 *
4 */
5
6#ifndef _BLACKFIN_H_
7#define _BLACKFIN_H_
8
9#define LO(con32) ((con32) & 0xFFFF)
10#define lo(con32) ((con32) & 0xFFFF)
11#define HI(con32) (((con32) >> 16) & 0xFFFF)
12#define hi(con32) (((con32) >> 16) & 0xFFFF)
13
14#include <mach/anomaly.h>
15
16#ifndef __ASSEMBLY__
17
18/* SSYNC implementation for C file */
19static inline void SSYNC(void)
20{
21 int _tmp;
22 if (ANOMALY_05000312)
23 __asm__ __volatile__(
24 "cli %0;"
25 "nop;"
26 "nop;"
27 "ssync;"
28 "sti %0;"
29 : "=d" (_tmp)
30 );
31 else if (ANOMALY_05000244)
32 __asm__ __volatile__(
33 "nop;"
34 "nop;"
35 "nop;"
36 "ssync;"
37 );
38 else
39 __asm__ __volatile__("ssync;");
40}
41
42/* CSYNC implementation for C file */
43static inline void CSYNC(void)
44{
45 int _tmp;
46 if (ANOMALY_05000312)
47 __asm__ __volatile__(
48 "cli %0;"
49 "nop;"
50 "nop;"
51 "csync;"
52 "sti %0;"
53 : "=d" (_tmp)
54 );
55 else if (ANOMALY_05000244)
56 __asm__ __volatile__(
57 "nop;"
58 "nop;"
59 "nop;"
60 "csync;"
61 );
62 else
63 __asm__ __volatile__("csync;");
64}
65
66#else /* __ASSEMBLY__ */
67
68/* SSYNC & CSYNC implementations for assembly files */
69
70#define ssync(x) SSYNC(x)
71#define csync(x) CSYNC(x)
72
73#if ANOMALY_05000312
74#define SSYNC(scratch) cli scratch; nop; nop; SSYNC; sti scratch;
75#define CSYNC(scratch) cli scratch; nop; nop; CSYNC; sti scratch;
76
77#elif ANOMALY_05000244
78#define SSYNC(scratch) nop; nop; nop; SSYNC;
79#define CSYNC(scratch) nop; nop; nop; CSYNC;
80
81#else
82#define SSYNC(scratch) SSYNC;
83#define CSYNC(scratch) CSYNC;
84
85#endif /* ANOMALY_05000312 & ANOMALY_05000244 handling */
86
87#endif /* __ASSEMBLY__ */
88
89#include <mach/blackfin.h>
90#include <asm/bfin-global.h>
91
92#endif /* _BLACKFIN_H_ */
diff --git a/arch/blackfin/include/asm/bug.h b/arch/blackfin/include/asm/bug.h
new file mode 100644
index 000000000000..6d3e11b1fc57
--- /dev/null
+++ b/arch/blackfin/include/asm/bug.h
@@ -0,0 +1,17 @@
1#ifndef _BLACKFIN_BUG_H
2#define _BLACKFIN_BUG_H
3
4#ifdef CONFIG_BUG
5#define HAVE_ARCH_BUG
6
7#define BUG() do { \
8 dump_bfin_trace_buffer(); \
9 printk(KERN_EMERG "BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __func__); \
10 panic("BUG!"); \
11} while (0)
12
13#endif
14
15#include <asm-generic/bug.h>
16
17#endif
diff --git a/arch/blackfin/include/asm/bugs.h b/arch/blackfin/include/asm/bugs.h
new file mode 100644
index 000000000000..9093c9c1fb81
--- /dev/null
+++ b/arch/blackfin/include/asm/bugs.h
@@ -0,0 +1,16 @@
1/*
2 * include/asm-blackfin/bugs.h
3 *
4 * Copyright (C) 1994 Linus Torvalds
5 */
6
7/*
8 * This is included by init/main.c to check for architecture-dependent bugs.
9 *
10 * Needs:
11 * void check_bugs(void);
12 */
13
14static void check_bugs(void)
15{
16}
diff --git a/arch/blackfin/include/asm/byteorder.h b/arch/blackfin/include/asm/byteorder.h
new file mode 100644
index 000000000000..6a673d42da18
--- /dev/null
+++ b/arch/blackfin/include/asm/byteorder.h
@@ -0,0 +1,48 @@
1#ifndef _BLACKFIN_BYTEORDER_H
2#define _BLACKFIN_BYTEORDER_H
3
4#include <asm/types.h>
5#include <linux/compiler.h>
6
7#ifdef __GNUC__
8
9static __inline__ __attribute_const__ __u32 ___arch__swahb32(__u32 xx)
10{
11 __u32 tmp;
12 __asm__("%1 = %0 >> 8 (V);\n\t"
13 "%0 = %0 << 8 (V);\n\t"
14 "%0 = %0 | %1;\n\t"
15 : "+d"(xx), "=&d"(tmp));
16 return xx;
17}
18
19static __inline__ __attribute_const__ __u32 ___arch__swahw32(__u32 xx)
20{
21 __u32 rv;
22 __asm__("%0 = PACK(%1.L, %1.H);\n\t": "=d"(rv): "d"(xx));
23 return rv;
24}
25
26#define __arch__swahb32(x) ___arch__swahb32(x)
27#define __arch__swahw32(x) ___arch__swahw32(x)
28#define __arch__swab32(x) ___arch__swahb32(___arch__swahw32(x))
29
30static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 xx)
31{
32 __u32 xw = xx;
33 __asm__("%0 <<= 8;\n %0.L = %0.L + %0.H (NS);\n": "+d"(xw));
34 return (__u16)xw;
35}
36
37#define __arch__swab16(x) ___arch__swab16(x)
38
39#endif
40
41#if defined(__GNUC__) && !defined(__STRICT_ANSI__) || defined(__KERNEL__)
42# define __BYTEORDER_HAS_U64__
43# define __SWAB_64_THRU_32__
44#endif
45
46#include <linux/byteorder/little_endian.h>
47
48#endif /* _BLACKFIN_BYTEORDER_H */
diff --git a/arch/blackfin/include/asm/cache.h b/arch/blackfin/include/asm/cache.h
new file mode 100644
index 000000000000..023d72133b5a
--- /dev/null
+++ b/arch/blackfin/include/asm/cache.h
@@ -0,0 +1,29 @@
1/*
2 * include/asm-blackfin/cache.h
3 */
4#ifndef __ARCH_BLACKFIN_CACHE_H
5#define __ARCH_BLACKFIN_CACHE_H
6
7/*
8 * Bytes per L1 cache line
9 * Blackfin loads 32 bytes for cache
10 */
11#define L1_CACHE_SHIFT 5
12#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
13#define SMP_CACHE_BYTES L1_CACHE_BYTES
14
15/*
16 * Put cacheline_aliged data to L1 data memory
17 */
18#ifdef CONFIG_CACHELINE_ALIGNED_L1
19#define __cacheline_aligned \
20 __attribute__((__aligned__(L1_CACHE_BYTES), \
21 __section__(".data_l1.cacheline_aligned")))
22#endif
23
24/*
25 * largest L1 which this arch supports
26 */
27#define L1_CACHE_SHIFT_MAX 5
28
29#endif
diff --git a/arch/blackfin/include/asm/cacheflush.h b/arch/blackfin/include/asm/cacheflush.h
new file mode 100644
index 000000000000..d81a77545a04
--- /dev/null
+++ b/arch/blackfin/include/asm/cacheflush.h
@@ -0,0 +1,90 @@
1/*
2 * File: include/asm-blackfin/cacheflush.h
3 * Based on: include/asm-m68knommu/cacheflush.h
4 * Author: LG Soft India
5 * Copyright (C) 2004 Analog Devices Inc.
6 * Created: Tue Sep 21 2004
7 * Description: Blackfin low-level cache routines adapted from the i386
8 * and PPC versions by Greg Ungerer (gerg@snapgear.com)
9 *
10 * Modified:
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2, or (at your option)
17 * any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; see the file COPYING.
26 * If not, write to the Free Software Foundation,
27 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
28 */
29
30#ifndef _BLACKFIN_CACHEFLUSH_H
31#define _BLACKFIN_CACHEFLUSH_H
32
33#include <asm/cplb.h>
34
35extern void blackfin_icache_dcache_flush_range(unsigned int, unsigned int);
36extern void blackfin_icache_flush_range(unsigned int, unsigned int);
37extern void blackfin_dcache_flush_range(unsigned int, unsigned int);
38extern void blackfin_dcache_invalidate_range(unsigned int, unsigned int);
39extern void blackfin_dflush_page(void *);
40
41#define flush_dcache_mmap_lock(mapping) do { } while (0)
42#define flush_dcache_mmap_unlock(mapping) do { } while (0)
43#define flush_cache_mm(mm) do { } while (0)
44#define flush_cache_range(vma, start, end) do { } while (0)
45#define flush_cache_page(vma, vmaddr) do { } while (0)
46#define flush_cache_vmap(start, end) do { } while (0)
47#define flush_cache_vunmap(start, end) do { } while (0)
48
49static inline void flush_icache_range(unsigned start, unsigned end)
50{
51#if defined(CONFIG_BFIN_DCACHE) && defined(CONFIG_BFIN_ICACHE)
52
53# if defined(CONFIG_BFIN_WT)
54 blackfin_icache_flush_range((start), (end));
55# else
56 blackfin_icache_dcache_flush_range((start), (end));
57# endif
58
59#else
60
61# if defined(CONFIG_BFIN_ICACHE)
62 blackfin_icache_flush_range((start), (end));
63# endif
64# if defined(CONFIG_BFIN_DCACHE)
65 blackfin_dcache_flush_range((start), (end));
66# endif
67
68#endif
69}
70
71#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
72do { memcpy(dst, src, len); \
73 flush_icache_range ((unsigned) (dst), (unsigned) (dst) + (len)); \
74} while (0)
75#define copy_from_user_page(vma, page, vaddr, dst, src, len) memcpy(dst, src, len)
76
77#if defined(CONFIG_BFIN_DCACHE)
78# define invalidate_dcache_range(start,end) blackfin_dcache_invalidate_range((start), (end))
79#else
80# define invalidate_dcache_range(start,end) do { } while (0)
81#endif
82#if defined(CONFIG_BFIN_DCACHE) && defined(CONFIG_BFIN_WB)
83# define flush_dcache_range(start,end) blackfin_dcache_flush_range((start), (end))
84# define flush_dcache_page(page) blackfin_dflush_page(page_address(page))
85#else
86# define flush_dcache_range(start,end) do { } while (0)
87# define flush_dcache_page(page) do { } while (0)
88#endif
89
90#endif /* _BLACKFIN_ICACHEFLUSH_H */
diff --git a/arch/blackfin/include/asm/cdef_LPBlackfin.h b/arch/blackfin/include/asm/cdef_LPBlackfin.h
new file mode 100644
index 000000000000..35f841bce57d
--- /dev/null
+++ b/arch/blackfin/include/asm/cdef_LPBlackfin.h
@@ -0,0 +1,328 @@
1 /*
2 * File: include/asm-blackfin/mach-common/cdef_LPBlackfin.h
3 * Based on:
4 * Author: unknown
5 * COPYRIGHT 2005 Analog Devices
6 * Created: ?
7 * Description:
8 *
9 * Modified:
10 *
11 * Bugs: Enter bugs at http://blackfin.uclinux.org/
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2, or (at your option)
16 * any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; see the file COPYING.
25 * If not, write to the Free Software Foundation,
26 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 */
28
29#ifndef _CDEF_LPBLACKFIN_H
30#define _CDEF_LPBLACKFIN_H
31
32/*#if !defined(__ADSPLPBLACKFIN__)
33#warning cdef_LPBlackfin.h should only be included for 532 compatible chips.
34#endif
35*/
36#include <asm/def_LPBlackfin.h>
37
38/*Cache & SRAM Memory*/
39#define bfin_read_SRAM_BASE_ADDRESS() bfin_read32(SRAM_BASE_ADDRESS)
40#define bfin_write_SRAM_BASE_ADDRESS(val) bfin_write32(SRAM_BASE_ADDRESS,val)
41#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL)
42#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL,val)
43#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS)
44#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS,val)
45#define bfin_read_DCPLB_FAULT_ADDR() bfin_read32(DCPLB_FAULT_ADDR)
46#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_write32(DCPLB_FAULT_ADDR,val)
47/*
48#define MMR_TIMEOUT 0xFFE00010
49*/
50#define bfin_read_DCPLB_ADDR0() bfin_read32(DCPLB_ADDR0)
51#define bfin_write_DCPLB_ADDR0(val) bfin_write32(DCPLB_ADDR0,val)
52#define bfin_read_DCPLB_ADDR1() bfin_read32(DCPLB_ADDR1)
53#define bfin_write_DCPLB_ADDR1(val) bfin_write32(DCPLB_ADDR1,val)
54#define bfin_read_DCPLB_ADDR2() bfin_read32(DCPLB_ADDR2)
55#define bfin_write_DCPLB_ADDR2(val) bfin_write32(DCPLB_ADDR2,val)
56#define bfin_read_DCPLB_ADDR3() bfin_read32(DCPLB_ADDR3)
57#define bfin_write_DCPLB_ADDR3(val) bfin_write32(DCPLB_ADDR3,val)
58#define bfin_read_DCPLB_ADDR4() bfin_read32(DCPLB_ADDR4)
59#define bfin_write_DCPLB_ADDR4(val) bfin_write32(DCPLB_ADDR4,val)
60#define bfin_read_DCPLB_ADDR5() bfin_read32(DCPLB_ADDR5)
61#define bfin_write_DCPLB_ADDR5(val) bfin_write32(DCPLB_ADDR5,val)
62#define bfin_read_DCPLB_ADDR6() bfin_read32(DCPLB_ADDR6)
63#define bfin_write_DCPLB_ADDR6(val) bfin_write32(DCPLB_ADDR6,val)
64#define bfin_read_DCPLB_ADDR7() bfin_read32(DCPLB_ADDR7)
65#define bfin_write_DCPLB_ADDR7(val) bfin_write32(DCPLB_ADDR7,val)
66#define bfin_read_DCPLB_ADDR8() bfin_read32(DCPLB_ADDR8)
67#define bfin_write_DCPLB_ADDR8(val) bfin_write32(DCPLB_ADDR8,val)
68#define bfin_read_DCPLB_ADDR9() bfin_read32(DCPLB_ADDR9)
69#define bfin_write_DCPLB_ADDR9(val) bfin_write32(DCPLB_ADDR9,val)
70#define bfin_read_DCPLB_ADDR10() bfin_read32(DCPLB_ADDR10)
71#define bfin_write_DCPLB_ADDR10(val) bfin_write32(DCPLB_ADDR10,val)
72#define bfin_read_DCPLB_ADDR11() bfin_read32(DCPLB_ADDR11)
73#define bfin_write_DCPLB_ADDR11(val) bfin_write32(DCPLB_ADDR11,val)
74#define bfin_read_DCPLB_ADDR12() bfin_read32(DCPLB_ADDR12)
75#define bfin_write_DCPLB_ADDR12(val) bfin_write32(DCPLB_ADDR12,val)
76#define bfin_read_DCPLB_ADDR13() bfin_read32(DCPLB_ADDR13)
77#define bfin_write_DCPLB_ADDR13(val) bfin_write32(DCPLB_ADDR13,val)
78#define bfin_read_DCPLB_ADDR14() bfin_read32(DCPLB_ADDR14)
79#define bfin_write_DCPLB_ADDR14(val) bfin_write32(DCPLB_ADDR14,val)
80#define bfin_read_DCPLB_ADDR15() bfin_read32(DCPLB_ADDR15)
81#define bfin_write_DCPLB_ADDR15(val) bfin_write32(DCPLB_ADDR15,val)
82#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0)
83#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0,val)
84#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1)
85#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1,val)
86#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2)
87#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2,val)
88#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3)
89#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3,val)
90#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4)
91#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4,val)
92#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5)
93#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5,val)
94#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6)
95#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6,val)
96#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7)
97#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7,val)
98#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8)
99#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8,val)
100#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9)
101#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9,val)
102#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10)
103#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10,val)
104#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11)
105#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11,val)
106#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12)
107#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12,val)
108#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13)
109#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13,val)
110#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14)
111#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14,val)
112#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15)
113#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15,val)
114#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND)
115#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND,val)
116/*
117#define DTEST_INDEX 0xFFE00304
118*/
119#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0)
120#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0,val)
121#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1)
122#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1,val)
123/*
124#define DTEST_DATA2 0xFFE00408
125#define DTEST_DATA3 0xFFE0040C
126*/
127#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL)
128#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL,val)
129#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS)
130#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS,val)
131#define bfin_read_ICPLB_FAULT_ADDR() bfin_read32(ICPLB_FAULT_ADDR)
132#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_write32(ICPLB_FAULT_ADDR,val)
133#define bfin_read_ICPLB_ADDR0() bfin_read32(ICPLB_ADDR0)
134#define bfin_write_ICPLB_ADDR0(val) bfin_write32(ICPLB_ADDR0,val)
135#define bfin_read_ICPLB_ADDR1() bfin_read32(ICPLB_ADDR1)
136#define bfin_write_ICPLB_ADDR1(val) bfin_write32(ICPLB_ADDR1,val)
137#define bfin_read_ICPLB_ADDR2() bfin_read32(ICPLB_ADDR2)
138#define bfin_write_ICPLB_ADDR2(val) bfin_write32(ICPLB_ADDR2,val)
139#define bfin_read_ICPLB_ADDR3() bfin_read32(ICPLB_ADDR3)
140#define bfin_write_ICPLB_ADDR3(val) bfin_write32(ICPLB_ADDR3,val)
141#define bfin_read_ICPLB_ADDR4() bfin_read32(ICPLB_ADDR4)
142#define bfin_write_ICPLB_ADDR4(val) bfin_write32(ICPLB_ADDR4,val)
143#define bfin_read_ICPLB_ADDR5() bfin_read32(ICPLB_ADDR5)
144#define bfin_write_ICPLB_ADDR5(val) bfin_write32(ICPLB_ADDR5,val)
145#define bfin_read_ICPLB_ADDR6() bfin_read32(ICPLB_ADDR6)
146#define bfin_write_ICPLB_ADDR6(val) bfin_write32(ICPLB_ADDR6,val)
147#define bfin_read_ICPLB_ADDR7() bfin_read32(ICPLB_ADDR7)
148#define bfin_write_ICPLB_ADDR7(val) bfin_write32(ICPLB_ADDR7,val)
149#define bfin_read_ICPLB_ADDR8() bfin_read32(ICPLB_ADDR8)
150#define bfin_write_ICPLB_ADDR8(val) bfin_write32(ICPLB_ADDR8,val)
151#define bfin_read_ICPLB_ADDR9() bfin_read32(ICPLB_ADDR9)
152#define bfin_write_ICPLB_ADDR9(val) bfin_write32(ICPLB_ADDR9,val)
153#define bfin_read_ICPLB_ADDR10() bfin_read32(ICPLB_ADDR10)
154#define bfin_write_ICPLB_ADDR10(val) bfin_write32(ICPLB_ADDR10,val)
155#define bfin_read_ICPLB_ADDR11() bfin_read32(ICPLB_ADDR11)
156#define bfin_write_ICPLB_ADDR11(val) bfin_write32(ICPLB_ADDR11,val)
157#define bfin_read_ICPLB_ADDR12() bfin_read32(ICPLB_ADDR12)
158#define bfin_write_ICPLB_ADDR12(val) bfin_write32(ICPLB_ADDR12,val)
159#define bfin_read_ICPLB_ADDR13() bfin_read32(ICPLB_ADDR13)
160#define bfin_write_ICPLB_ADDR13(val) bfin_write32(ICPLB_ADDR13,val)
161#define bfin_read_ICPLB_ADDR14() bfin_read32(ICPLB_ADDR14)
162#define bfin_write_ICPLB_ADDR14(val) bfin_write32(ICPLB_ADDR14,val)
163#define bfin_read_ICPLB_ADDR15() bfin_read32(ICPLB_ADDR15)
164#define bfin_write_ICPLB_ADDR15(val) bfin_write32(ICPLB_ADDR15,val)
165#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0)
166#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0,val)
167#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1)
168#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1,val)
169#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2)
170#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2,val)
171#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3)
172#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3,val)
173#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4)
174#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4,val)
175#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5)
176#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5,val)
177#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6)
178#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6,val)
179#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7)
180#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7,val)
181#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8)
182#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8,val)
183#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9)
184#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9,val)
185#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10)
186#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10,val)
187#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11)
188#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11,val)
189#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12)
190#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12,val)
191#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13)
192#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13,val)
193#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14)
194#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14,val)
195#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15)
196#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15,val)
197#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND)
198#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND,val)
199#if 0
200#define ITEST_INDEX 0xFFE01304 /* Instruction Test Index Register */
201#endif
202#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0)
203#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0,val)
204#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1)
205#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1,val)
206
207/* Event/Interrupt Registers*/
208
209#define bfin_read_EVT0() bfin_read32(EVT0)
210#define bfin_write_EVT0(val) bfin_write32(EVT0,val)
211#define bfin_read_EVT1() bfin_read32(EVT1)
212#define bfin_write_EVT1(val) bfin_write32(EVT1,val)
213#define bfin_read_EVT2() bfin_read32(EVT2)
214#define bfin_write_EVT2(val) bfin_write32(EVT2,val)
215#define bfin_read_EVT3() bfin_read32(EVT3)
216#define bfin_write_EVT3(val) bfin_write32(EVT3,val)
217#define bfin_read_EVT4() bfin_read32(EVT4)
218#define bfin_write_EVT4(val) bfin_write32(EVT4,val)
219#define bfin_read_EVT5() bfin_read32(EVT5)
220#define bfin_write_EVT5(val) bfin_write32(EVT5,val)
221#define bfin_read_EVT6() bfin_read32(EVT6)
222#define bfin_write_EVT6(val) bfin_write32(EVT6,val)
223#define bfin_read_EVT7() bfin_read32(EVT7)
224#define bfin_write_EVT7(val) bfin_write32(EVT7,val)
225#define bfin_read_EVT8() bfin_read32(EVT8)
226#define bfin_write_EVT8(val) bfin_write32(EVT8,val)
227#define bfin_read_EVT9() bfin_read32(EVT9)
228#define bfin_write_EVT9(val) bfin_write32(EVT9,val)
229#define bfin_read_EVT10() bfin_read32(EVT10)
230#define bfin_write_EVT10(val) bfin_write32(EVT10,val)
231#define bfin_read_EVT11() bfin_read32(EVT11)
232#define bfin_write_EVT11(val) bfin_write32(EVT11,val)
233#define bfin_read_EVT12() bfin_read32(EVT12)
234#define bfin_write_EVT12(val) bfin_write32(EVT12,val)
235#define bfin_read_EVT13() bfin_read32(EVT13)
236#define bfin_write_EVT13(val) bfin_write32(EVT13,val)
237#define bfin_read_EVT14() bfin_read32(EVT14)
238#define bfin_write_EVT14(val) bfin_write32(EVT14,val)
239#define bfin_read_EVT15() bfin_read32(EVT15)
240#define bfin_write_EVT15(val) bfin_write32(EVT15,val)
241#define bfin_read_IMASK() bfin_read32(IMASK)
242#define bfin_write_IMASK(val) bfin_write32(IMASK,val)
243#define bfin_read_IPEND() bfin_read32(IPEND)
244#define bfin_write_IPEND(val) bfin_write32(IPEND,val)
245#define bfin_read_ILAT() bfin_read32(ILAT)
246#define bfin_write_ILAT(val) bfin_write32(ILAT,val)
247
248/*Core Timer Registers*/
249#define bfin_read_TCNTL() bfin_read32(TCNTL)
250#define bfin_write_TCNTL(val) bfin_write32(TCNTL,val)
251#define bfin_read_TPERIOD() bfin_read32(TPERIOD)
252#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD,val)
253#define bfin_read_TSCALE() bfin_read32(TSCALE)
254#define bfin_write_TSCALE(val) bfin_write32(TSCALE,val)
255#define bfin_read_TCOUNT() bfin_read32(TCOUNT)
256#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT,val)
257
258/*Debug/MP/Emulation Registers*/
259#define bfin_read_DSPID() bfin_read32(DSPID)
260#define bfin_write_DSPID(val) bfin_write32(DSPID,val)
261#define bfin_read_DBGCTL() bfin_read32(DBGCTL)
262#define bfin_write_DBGCTL(val) bfin_write32(DBGCTL,val)
263#define bfin_read_DBGSTAT() bfin_read32(DBGSTAT)
264#define bfin_write_DBGSTAT(val) bfin_write32(DBGSTAT,val)
265#define bfin_read_EMUDAT() bfin_read32(EMUDAT)
266#define bfin_write_EMUDAT(val) bfin_write32(EMUDAT,val)
267
268/*Trace Buffer Registers*/
269#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL)
270#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL,val)
271#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT)
272#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT,val)
273#define bfin_read_TBUF() bfin_read32(TBUF)
274#define bfin_write_TBUF(val) bfin_write32(TBUF,val)
275
276/*Watch Point Control Registers*/
277#define bfin_read_WPIACTL() bfin_read32(WPIACTL)
278#define bfin_write_WPIACTL(val) bfin_write32(WPIACTL,val)
279#define bfin_read_WPIA0() bfin_read32(WPIA0)
280#define bfin_write_WPIA0(val) bfin_write32(WPIA0,val)
281#define bfin_read_WPIA1() bfin_read32(WPIA1)
282#define bfin_write_WPIA1(val) bfin_write32(WPIA1,val)
283#define bfin_read_WPIA2() bfin_read32(WPIA2)
284#define bfin_write_WPIA2(val) bfin_write32(WPIA2,val)
285#define bfin_read_WPIA3() bfin_read32(WPIA3)
286#define bfin_write_WPIA3(val) bfin_write32(WPIA3,val)
287#define bfin_read_WPIA4() bfin_read32(WPIA4)
288#define bfin_write_WPIA4(val) bfin_write32(WPIA4,val)
289#define bfin_read_WPIA5() bfin_read32(WPIA5)
290#define bfin_write_WPIA5(val) bfin_write32(WPIA5,val)
291#define bfin_read_WPIACNT0() bfin_read32(WPIACNT0)
292#define bfin_write_WPIACNT0(val) bfin_write32(WPIACNT0,val)
293#define bfin_read_WPIACNT1() bfin_read32(WPIACNT1)
294#define bfin_write_WPIACNT1(val) bfin_write32(WPIACNT1,val)
295#define bfin_read_WPIACNT2() bfin_read32(WPIACNT2)
296#define bfin_write_WPIACNT2(val) bfin_write32(WPIACNT2,val)
297#define bfin_read_WPIACNT3() bfin_read32(WPIACNT3)
298#define bfin_write_WPIACNT3(val) bfin_write32(WPIACNT3,val)
299#define bfin_read_WPIACNT4() bfin_read32(WPIACNT4)
300#define bfin_write_WPIACNT4(val) bfin_write32(WPIACNT4,val)
301#define bfin_read_WPIACNT5() bfin_read32(WPIACNT5)
302#define bfin_write_WPIACNT5(val) bfin_write32(WPIACNT5,val)
303#define bfin_read_WPDACTL() bfin_read32(WPDACTL)
304#define bfin_write_WPDACTL(val) bfin_write32(WPDACTL,val)
305#define bfin_read_WPDA0() bfin_read32(WPDA0)
306#define bfin_write_WPDA0(val) bfin_write32(WPDA0,val)
307#define bfin_read_WPDA1() bfin_read32(WPDA1)
308#define bfin_write_WPDA1(val) bfin_write32(WPDA1,val)
309#define bfin_read_WPDACNT0() bfin_read32(WPDACNT0)
310#define bfin_write_WPDACNT0(val) bfin_write32(WPDACNT0,val)
311#define bfin_read_WPDACNT1() bfin_read32(WPDACNT1)
312#define bfin_write_WPDACNT1(val) bfin_write32(WPDACNT1,val)
313#define bfin_read_WPSTAT() bfin_read32(WPSTAT)
314#define bfin_write_WPSTAT(val) bfin_write32(WPSTAT,val)
315
316/*Performance Monitor Registers*/
317#define bfin_read_PFCTL() bfin_read32(PFCTL)
318#define bfin_write_PFCTL(val) bfin_write32(PFCTL,val)
319#define bfin_read_PFCNTR0() bfin_read32(PFCNTR0)
320#define bfin_write_PFCNTR0(val) bfin_write32(PFCNTR0,val)
321#define bfin_read_PFCNTR1() bfin_read32(PFCNTR1)
322#define bfin_write_PFCNTR1(val) bfin_write32(PFCNTR1,val)
323
324/*
325#define IPRIO 0xFFE02110
326*/
327
328#endif /* _CDEF_LPBLACKFIN_H */
diff --git a/arch/blackfin/include/asm/checksum.h b/arch/blackfin/include/asm/checksum.h
new file mode 100644
index 000000000000..6f6af2b8e9e0
--- /dev/null
+++ b/arch/blackfin/include/asm/checksum.h
@@ -0,0 +1,100 @@
1#ifndef _BFIN_CHECKSUM_H
2#define _BFIN_CHECKSUM_H
3
4/*
5 * MODIFIED FOR BFIN April 30, 2001 akbar.hussain@lineo.com
6 *
7 * computes the checksum of a memory block at buff, length len,
8 * and adds in "sum" (32-bit)
9 *
10 * returns a 32-bit number suitable for feeding into itself
11 * or csum_tcpudp_magic
12 *
13 * this function must be called with even lengths, except
14 * for the last fragment, which may be odd
15 *
16 * it's best to have buff aligned on a 32-bit boundary
17 */
18__wsum csum_partial(const void *buff, int len, __wsum sum);
19
20/*
21 * the same as csum_partial, but copies from src while it
22 * checksums
23 *
24 * here even more important to align src and dst on a 32-bit (or even
25 * better 64-bit) boundary
26 */
27
28__wsum csum_partial_copy(const void *src, void *dst,
29 int len, __wsum sum);
30
31/*
32 * the same as csum_partial_copy, but copies from user space.
33 *
34 * here even more important to align src and dst on a 32-bit (or even
35 * better 64-bit) boundary
36 */
37
38extern __wsum csum_partial_copy_from_user(const void __user *src, void *dst,
39 int len, __wsum sum, int *csum_err);
40
41#define csum_partial_copy_nocheck(src, dst, len, sum) \
42 csum_partial_copy((src), (dst), (len), (sum))
43
44__sum16 ip_fast_csum(unsigned char *iph, unsigned int ihl);
45
46/*
47 * Fold a partial checksum
48 */
49
50static inline __sum16 csum_fold(__wsum sum)
51{
52 while (sum >> 16)
53 sum = (sum & 0xffff) + (sum >> 16);
54 return ((~(sum << 16)) >> 16);
55}
56
57/*
58 * computes the checksum of the TCP/UDP pseudo-header
59 * returns a 16-bit checksum, already complemented
60 */
61
62static inline __wsum
63csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len,
64 unsigned short proto, __wsum sum)
65{
66
67 __asm__ ("%0 = %0 + %1;\n\t"
68 "CC = AC0;\n\t"
69 "if !CC jump 4;\n\t"
70 "%0 = %0 + %4;\n\t"
71 "%0 = %0 + %2;\n\t"
72 "CC = AC0;\n\t"
73 "if !CC jump 4;\n\t"
74 "%0 = %0 + %4;\n\t"
75 "%0 = %0 + %3;\n\t"
76 "CC = AC0;\n\t"
77 "if !CC jump 4;\n\t"
78 "%0 = %0 + %4;\n\t"
79 "NOP;\n\t"
80 : "=d" (sum)
81 : "d" (daddr), "d" (saddr), "d" ((ntohs(len)<<16)+proto*256), "d" (1), "0"(sum));
82
83 return (sum);
84}
85
86static inline __sum16
87csum_tcpudp_magic(__be32 saddr, __be32 daddr, unsigned short len,
88 unsigned short proto, __wsum sum)
89{
90 return csum_fold(csum_tcpudp_nofold(saddr, daddr, len, proto, sum));
91}
92
93/*
94 * this routine is used for miscellaneous IP-like checksums, mainly
95 * in icmp.c
96 */
97
98extern __sum16 ip_compute_csum(const void *buff, int len);
99
100#endif /* _BFIN_CHECKSUM_H */
diff --git a/arch/blackfin/include/asm/clocks.h b/arch/blackfin/include/asm/clocks.h
new file mode 100644
index 000000000000..033bba92d61c
--- /dev/null
+++ b/arch/blackfin/include/asm/clocks.h
@@ -0,0 +1,70 @@
1/*
2 * File: include/asm-blackfin/mach-common/clocks.h
3 * Based on: include/asm-blackfin/mach-bf537/bf537.h
4 * Author: Robin Getz <rgetz@blackfin.uclinux.org>
5 *
6 * Created: 25Jul07
7 * Description: Common Clock definitions for various kernel files
8 *
9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#ifndef _BFIN_CLOCKS_H
31#define _BFIN_CLOCKS_H
32
33#ifdef CONFIG_CCLK_DIV_1
34# define CONFIG_CCLK_ACT_DIV CCLK_DIV1
35# define CONFIG_CCLK_DIV 1
36#endif
37
38#ifdef CONFIG_CCLK_DIV_2
39# define CONFIG_CCLK_ACT_DIV CCLK_DIV2
40# define CONFIG_CCLK_DIV 2
41#endif
42
43#ifdef CONFIG_CCLK_DIV_4
44# define CONFIG_CCLK_ACT_DIV CCLK_DIV4
45# define CONFIG_CCLK_DIV 4
46#endif
47
48#ifdef CONFIG_CCLK_DIV_8
49# define CONFIG_CCLK_ACT_DIV CCLK_DIV8
50# define CONFIG_CCLK_DIV 8
51#endif
52
53#ifndef CONFIG_PLL_BYPASS
54# ifndef CONFIG_CLKIN_HALF
55# define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)
56# else
57# define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2)
58# endif
59
60# define CONFIG_CCLK_HZ (CONFIG_VCO_HZ/CONFIG_CCLK_DIV)
61# define CONFIG_SCLK_HZ (CONFIG_VCO_HZ/CONFIG_SCLK_DIV)
62
63#else
64# define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ)
65# define CONFIG_CCLK_HZ (CONFIG_CLKIN_HZ)
66# define CONFIG_SCLK_HZ (CONFIG_CLKIN_HZ)
67# define CONFIG_VCO_MULT 0
68#endif
69
70#endif
diff --git a/arch/blackfin/include/asm/context.S b/arch/blackfin/include/asm/context.S
new file mode 100644
index 000000000000..c0e630edfb9a
--- /dev/null
+++ b/arch/blackfin/include/asm/context.S
@@ -0,0 +1,355 @@
1/*
2 * File: arch/blackfin/kernel/context.S
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30/*
31 * NOTE! The single-stepping code assumes that all interrupt handlers
32 * start by saving SYSCFG on the stack with their first instruction.
33 */
34
35/*
36 * Code to save processor context.
37 * We even save the register which are preserved by a function call
38 * - r4, r5, r6, r7, p3, p4, p5
39 */
40.macro save_context_with_interrupts
41 [--sp] = SYSCFG;
42
43 [--sp] = P0; /*orig_p0*/
44 [--sp] = R0; /*orig_r0*/
45
46 [--sp] = ( R7:0, P5:0 );
47 [--sp] = fp;
48 [--sp] = usp;
49
50 [--sp] = i0;
51 [--sp] = i1;
52 [--sp] = i2;
53 [--sp] = i3;
54
55 [--sp] = m0;
56 [--sp] = m1;
57 [--sp] = m2;
58 [--sp] = m3;
59
60 [--sp] = l0;
61 [--sp] = l1;
62 [--sp] = l2;
63 [--sp] = l3;
64
65 [--sp] = b0;
66 [--sp] = b1;
67 [--sp] = b2;
68 [--sp] = b3;
69 [--sp] = a0.x;
70 [--sp] = a0.w;
71 [--sp] = a1.x;
72 [--sp] = a1.w;
73
74 [--sp] = LC0;
75 [--sp] = LC1;
76 [--sp] = LT0;
77 [--sp] = LT1;
78 [--sp] = LB0;
79 [--sp] = LB1;
80
81 [--sp] = ASTAT;
82
83 [--sp] = r0; /* Skip reserved */
84 [--sp] = RETS;
85 r0 = RETI;
86 [--sp] = r0;
87 [--sp] = RETX;
88 [--sp] = RETN;
89 [--sp] = RETE;
90 [--sp] = SEQSTAT;
91 [--sp] = r0; /* Skip IPEND as well. */
92 /* Switch to other method of keeping interrupts disabled. */
93#ifdef CONFIG_DEBUG_HWERR
94 r0 = 0x3f;
95 sti r0;
96#else
97 cli r0;
98#endif
99 [--sp] = RETI; /*orig_pc*/
100 /* Clear all L registers. */
101 r0 = 0 (x);
102 l0 = r0;
103 l1 = r0;
104 l2 = r0;
105 l3 = r0;
106.endm
107
108.macro save_context_syscall
109 [--sp] = SYSCFG;
110
111 [--sp] = P0; /*orig_p0*/
112 [--sp] = R0; /*orig_r0*/
113 [--sp] = ( R7:0, P5:0 );
114 [--sp] = fp;
115 [--sp] = usp;
116
117 [--sp] = i0;
118 [--sp] = i1;
119 [--sp] = i2;
120 [--sp] = i3;
121
122 [--sp] = m0;
123 [--sp] = m1;
124 [--sp] = m2;
125 [--sp] = m3;
126
127 [--sp] = l0;
128 [--sp] = l1;
129 [--sp] = l2;
130 [--sp] = l3;
131
132 [--sp] = b0;
133 [--sp] = b1;
134 [--sp] = b2;
135 [--sp] = b3;
136 [--sp] = a0.x;
137 [--sp] = a0.w;
138 [--sp] = a1.x;
139 [--sp] = a1.w;
140
141 [--sp] = LC0;
142 [--sp] = LC1;
143 [--sp] = LT0;
144 [--sp] = LT1;
145 [--sp] = LB0;
146 [--sp] = LB1;
147
148 [--sp] = ASTAT;
149
150 [--sp] = r0; /* Skip reserved */
151 [--sp] = RETS;
152 r0 = RETI;
153 [--sp] = r0;
154 [--sp] = RETX;
155 [--sp] = RETN;
156 [--sp] = RETE;
157 [--sp] = SEQSTAT;
158 [--sp] = r0; /* Skip IPEND as well. */
159 [--sp] = RETI; /*orig_pc*/
160 /* Clear all L registers. */
161 r0 = 0 (x);
162 l0 = r0;
163 l1 = r0;
164 l2 = r0;
165 l3 = r0;
166.endm
167
168.macro save_context_no_interrupts
169 [--sp] = SYSCFG;
170 [--sp] = P0; /* orig_p0 */
171 [--sp] = R0; /* orig_r0 */
172 [--sp] = ( R7:0, P5:0 );
173 [--sp] = fp;
174 [--sp] = usp;
175
176 [--sp] = i0;
177 [--sp] = i1;
178 [--sp] = i2;
179 [--sp] = i3;
180
181 [--sp] = m0;
182 [--sp] = m1;
183 [--sp] = m2;
184 [--sp] = m3;
185
186 [--sp] = l0;
187 [--sp] = l1;
188 [--sp] = l2;
189 [--sp] = l3;
190
191 [--sp] = b0;
192 [--sp] = b1;
193 [--sp] = b2;
194 [--sp] = b3;
195 [--sp] = a0.x;
196 [--sp] = a0.w;
197 [--sp] = a1.x;
198 [--sp] = a1.w;
199
200 [--sp] = LC0;
201 [--sp] = LC1;
202 [--sp] = LT0;
203 [--sp] = LT1;
204 [--sp] = LB0;
205 [--sp] = LB1;
206
207 [--sp] = ASTAT;
208
209#ifdef CONFIG_KGDB
210 fp = 0(Z);
211 r1 = sp;
212 r1 += 60;
213 r1 += 60;
214 r1 += 60;
215 [--sp] = r1;
216#else
217 [--sp] = r0; /* Skip reserved */
218#endif
219 [--sp] = RETS;
220 r0 = RETI;
221 [--sp] = r0;
222 [--sp] = RETX;
223 [--sp] = RETN;
224 [--sp] = RETE;
225 [--sp] = SEQSTAT;
226#ifdef CONFIG_KGDB
227 r1.l = lo(IPEND);
228 r1.h = hi(IPEND);
229 [--sp] = r1;
230#else
231 [--sp] = r0; /* Skip IPEND as well. */
232#endif
233 [--sp] = r0; /*orig_pc*/
234 /* Clear all L registers. */
235 r0 = 0 (x);
236 l0 = r0;
237 l1 = r0;
238 l2 = r0;
239 l3 = r0;
240.endm
241
242.macro restore_context_no_interrupts
243 sp += 4; /* Skip orig_pc */
244 sp += 4; /* Skip IPEND */
245 SEQSTAT = [sp++];
246 RETE = [sp++];
247 RETN = [sp++];
248 RETX = [sp++];
249 r0 = [sp++];
250 RETI = r0; /* Restore RETI indirectly when in exception */
251 RETS = [sp++];
252
253 sp += 4; /* Skip Reserved */
254
255 ASTAT = [sp++];
256
257 LB1 = [sp++];
258 LB0 = [sp++];
259 LT1 = [sp++];
260 LT0 = [sp++];
261 LC1 = [sp++];
262 LC0 = [sp++];
263
264 a1.w = [sp++];
265 a1.x = [sp++];
266 a0.w = [sp++];
267 a0.x = [sp++];
268 b3 = [sp++];
269 b2 = [sp++];
270 b1 = [sp++];
271 b0 = [sp++];
272
273 l3 = [sp++];
274 l2 = [sp++];
275 l1 = [sp++];
276 l0 = [sp++];
277
278 m3 = [sp++];
279 m2 = [sp++];
280 m1 = [sp++];
281 m0 = [sp++];
282
283 i3 = [sp++];
284 i2 = [sp++];
285 i1 = [sp++];
286 i0 = [sp++];
287
288 sp += 4;
289 fp = [sp++];
290
291 ( R7 : 0, P5 : 0) = [ SP ++ ];
292 sp += 8; /* Skip orig_r0/orig_p0 */
293 SYSCFG = [sp++];
294.endm
295
296.macro restore_context_with_interrupts
297 sp += 4; /* Skip orig_pc */
298 sp += 4; /* Skip IPEND */
299 SEQSTAT = [sp++];
300 RETE = [sp++];
301 RETN = [sp++];
302 RETX = [sp++];
303 RETI = [sp++];
304 RETS = [sp++];
305
306 p0.h = _irq_flags;
307 p0.l = _irq_flags;
308 r0 = [p0];
309 sti r0;
310
311 sp += 4; /* Skip Reserved */
312
313 ASTAT = [sp++];
314
315 LB1 = [sp++];
316 LB0 = [sp++];
317 LT1 = [sp++];
318 LT0 = [sp++];
319 LC1 = [sp++];
320 LC0 = [sp++];
321
322 a1.w = [sp++];
323 a1.x = [sp++];
324 a0.w = [sp++];
325 a0.x = [sp++];
326 b3 = [sp++];
327 b2 = [sp++];
328 b1 = [sp++];
329 b0 = [sp++];
330
331 l3 = [sp++];
332 l2 = [sp++];
333 l1 = [sp++];
334 l0 = [sp++];
335
336 m3 = [sp++];
337 m2 = [sp++];
338 m1 = [sp++];
339 m0 = [sp++];
340
341 i3 = [sp++];
342 i2 = [sp++];
343 i1 = [sp++];
344 i0 = [sp++];
345
346 sp += 4;
347 fp = [sp++];
348
349 ( R7 : 0, P5 : 0) = [ SP ++ ];
350 sp += 8; /* Skip orig_r0/orig_p0 */
351 csync;
352 SYSCFG = [sp++];
353 csync;
354.endm
355
diff --git a/arch/blackfin/include/asm/cplb-mpu.h b/arch/blackfin/include/asm/cplb-mpu.h
new file mode 100644
index 000000000000..75c67b99d607
--- /dev/null
+++ b/arch/blackfin/include/asm/cplb-mpu.h
@@ -0,0 +1,61 @@
1/*
2 * File: include/asm-blackfin/cplbinit.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29#ifndef __ASM_BFIN_CPLB_MPU_H
30#define __ASM_BFIN_CPLB_MPU_H
31
32struct cplb_entry {
33 unsigned long data, addr;
34};
35
36struct mem_region {
37 unsigned long start, end;
38 unsigned long dcplb_data;
39 unsigned long icplb_data;
40};
41
42extern struct cplb_entry dcplb_tbl[MAX_CPLBS];
43extern struct cplb_entry icplb_tbl[MAX_CPLBS];
44extern int first_switched_icplb;
45extern int first_mask_dcplb;
46extern int first_switched_dcplb;
47
48extern int nr_dcplb_miss, nr_icplb_miss, nr_icplb_supv_miss, nr_dcplb_prot;
49extern int nr_cplb_flush;
50
51extern int page_mask_order;
52extern int page_mask_nelts;
53
54extern unsigned long *current_rwx_mask;
55
56extern void flush_switched_cplbs(void);
57extern void set_mask_dcplbs(unsigned long *);
58
59extern void __noreturn panic_cplb_error(int seqstat, struct pt_regs *);
60
61#endif /* __ASM_BFIN_CPLB_MPU_H */
diff --git a/arch/blackfin/include/asm/cplb.h b/arch/blackfin/include/asm/cplb.h
new file mode 100644
index 000000000000..05d6f05fb748
--- /dev/null
+++ b/arch/blackfin/include/asm/cplb.h
@@ -0,0 +1,110 @@
1/*
2 * File: include/asm-blackfin/cplb.h
3 * Based on: include/asm-blackfin/mach-bf537/bf537.h
4 * Author: Robin Getz <rgetz@blackfin.uclinux.org>
5 *
6 * Created: 2000
7 * Description: Common CPLB definitions for CPLB init
8 *
9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#ifndef _CPLB_H
31#define _CPLB_H
32
33#include <asm/blackfin.h>
34#include <mach/anomaly.h>
35
36#define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
37#define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK)
38#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
39#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID)
40
41/*Use the menuconfig cache policy here - CONFIG_BFIN_WT/CONFIG_BFIN_WB*/
42
43#if ANOMALY_05000158
44#define ANOMALY_05000158_WORKAROUND 0x200
45#else
46#define ANOMALY_05000158_WORKAROUND 0x0
47#endif
48
49#define CPLB_COMMON (CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
50
51#ifdef CONFIG_BFIN_WB /*Write Back Policy */
52#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_COMMON)
53#else /*Write Through */
54#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON)
55#endif
56
57#define L1_DMEMORY (CPLB_LOCK | CPLB_COMMON)
58#define L2_MEMORY (CPLB_COMMON)
59#define SDRAM_DNON_CHBL (CPLB_COMMON)
60#define SDRAM_EBIU (CPLB_COMMON)
61#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
62
63#define SIZE_1K 0x00000400 /* 1K */
64#define SIZE_4K 0x00001000 /* 4K */
65#define SIZE_1M 0x00100000 /* 1M */
66#define SIZE_4M 0x00400000 /* 4M */
67
68#ifdef CONFIG_MPU
69#define MAX_CPLBS 16
70#else
71#define MAX_CPLBS (16 * 2)
72#endif
73
74#define ASYNC_MEMORY_CPLB_COVERAGE ((ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \
75 ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE) / SIZE_4M)
76
77#define CPLB_ENABLE_ICACHE_P 0
78#define CPLB_ENABLE_DCACHE_P 1
79#define CPLB_ENABLE_DCACHE2_P 2
80#define CPLB_ENABLE_CPLBS_P 3 /* Deprecated! */
81#define CPLB_ENABLE_ICPLBS_P 4
82#define CPLB_ENABLE_DCPLBS_P 5
83
84#define CPLB_ENABLE_ICACHE (1<<CPLB_ENABLE_ICACHE_P)
85#define CPLB_ENABLE_DCACHE (1<<CPLB_ENABLE_DCACHE_P)
86#define CPLB_ENABLE_DCACHE2 (1<<CPLB_ENABLE_DCACHE2_P)
87#define CPLB_ENABLE_CPLBS (1<<CPLB_ENABLE_CPLBS_P)
88#define CPLB_ENABLE_ICPLBS (1<<CPLB_ENABLE_ICPLBS_P)
89#define CPLB_ENABLE_DCPLBS (1<<CPLB_ENABLE_DCPLBS_P)
90#define CPLB_ENABLE_ANY_CPLBS CPLB_ENABLE_CPLBS | \
91 CPLB_ENABLE_ICPLBS | \
92 CPLB_ENABLE_DCPLBS
93
94#define CPLB_RELOADED 0x0000
95#define CPLB_NO_UNLOCKED 0x0001
96#define CPLB_NO_ADDR_MATCH 0x0002
97#define CPLB_PROT_VIOL 0x0003
98#define CPLB_UNKNOWN_ERR 0x0004
99
100#define CPLB_DEF_CACHE CPLB_L1_CHBL | CPLB_WT
101#define CPLB_CACHE_ENABLED CPLB_L1_CHBL | CPLB_DIRTY
102
103#define CPLB_I_PAGE_MGMT CPLB_LOCK | CPLB_VALID
104#define CPLB_D_PAGE_MGMT CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID
105#define CPLB_DNOCACHE CPLB_ALL_ACCESS | CPLB_VALID
106#define CPLB_DDOCACHE CPLB_DNOCACHE | CPLB_DEF_CACHE
107#define CPLB_INOCACHE CPLB_USER_RD | CPLB_VALID
108#define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL
109
110#endif /* _CPLB_H */
diff --git a/arch/blackfin/include/asm/cplbinit.h b/arch/blackfin/include/asm/cplbinit.h
new file mode 100644
index 000000000000..0eb1c1b685a7
--- /dev/null
+++ b/arch/blackfin/include/asm/cplbinit.h
@@ -0,0 +1,95 @@
1/*
2 * File: include/asm-blackfin/cplbinit.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#ifndef __ASM_CPLBINIT_H__
31#define __ASM_CPLBINIT_H__
32
33#include <asm/blackfin.h>
34#include <asm/cplb.h>
35
36#ifdef CONFIG_MPU
37
38#include <asm/cplb-mpu.h>
39
40#else
41
42#define INITIAL_T 0x1
43#define SWITCH_T 0x2
44#define I_CPLB 0x4
45#define D_CPLB 0x8
46
47#define IN_KERNEL 1
48
49enum
50{ZERO_P, L1I_MEM, L1D_MEM, SDRAM_KERN , SDRAM_RAM_MTD, SDRAM_DMAZ, RES_MEM, ASYNC_MEM, L2_MEM};
51
52struct cplb_desc {
53 u32 start; /* start address */
54 u32 end; /* end address */
55 u32 psize; /* prefered size if any otherwise 1MB or 4MB*/
56 u16 attr;/* attributes */
57 u16 i_conf;/* I-CPLB DATA */
58 u16 d_conf;/* D-CPLB DATA */
59 u16 valid;/* valid */
60 const s8 name[30];/* name */
61};
62
63struct cplb_tab {
64 u_long *tab;
65 u16 pos;
66 u16 size;
67};
68
69extern u_long icplb_table[];
70extern u_long dcplb_table[];
71
72/* Till here we are discussing about the static memory management model.
73 * However, the operating envoronments commonly define more CPLB
74 * descriptors to cover the entire addressable memory than will fit into
75 * the available on-chip 16 CPLB MMRs. When this happens, the below table
76 * will be used which will hold all the potentially required CPLB descriptors
77 *
78 * This is how Page descriptor Table is implemented in uClinux/Blackfin.
79 */
80
81extern u_long ipdt_table[];
82extern u_long dpdt_table[];
83#ifdef CONFIG_CPLB_INFO
84extern u_long ipdt_swapcount_table[];
85extern u_long dpdt_swapcount_table[];
86#endif
87
88#endif /* CONFIG_MPU */
89
90extern unsigned long reserved_mem_dcache_on;
91extern unsigned long reserved_mem_icache_on;
92
93extern void generate_cpl_tables(void);
94
95#endif
diff --git a/arch/blackfin/include/asm/cpumask.h b/arch/blackfin/include/asm/cpumask.h
new file mode 100644
index 000000000000..b20a8e9012cb
--- /dev/null
+++ b/arch/blackfin/include/asm/cpumask.h
@@ -0,0 +1,6 @@
1#ifndef _ASM_BLACKFIN_CPUMASK_H
2#define _ASM_BLACKFIN_CPUMASK_H
3
4#include <asm-generic/cpumask.h>
5
6#endif /* _ASM_BLACKFIN_CPUMASK_H */
diff --git a/arch/blackfin/include/asm/cputime.h b/arch/blackfin/include/asm/cputime.h
new file mode 100644
index 000000000000..2b19705f9885
--- /dev/null
+++ b/arch/blackfin/include/asm/cputime.h
@@ -0,0 +1,6 @@
1#ifndef __BLACKFIN_CPUTIME_H
2#define __BLACKFIN_CPUTIME_H
3
4#include <asm-generic/cputime.h>
5
6#endif /* __BLACKFIN_CPUTIME_H */
diff --git a/arch/blackfin/include/asm/current.h b/arch/blackfin/include/asm/current.h
new file mode 100644
index 000000000000..31918d29122c
--- /dev/null
+++ b/arch/blackfin/include/asm/current.h
@@ -0,0 +1,23 @@
1#ifndef _BLACKFIN_CURRENT_H
2#define _BLACKFIN_CURRENT_H
3/*
4 * current.h
5 * (C) Copyright 2000, Lineo, David McCullough <davidm@lineo.com>
6 *
7 * rather than dedicate a register (as the m68k source does), we
8 * just keep a global, we should probably just change it all to be
9 * current and lose _current_task.
10 */
11#include <linux/thread_info.h>
12
13struct task_struct;
14
15static inline struct task_struct *get_current(void) __attribute__ ((__const__));
16static inline struct task_struct *get_current(void)
17{
18 return (current_thread_info()->task);
19}
20
21#define current (get_current())
22
23#endif /* _BLACKFIN_CURRENT_H */
diff --git a/arch/blackfin/include/asm/def_LPBlackfin.h b/arch/blackfin/include/asm/def_LPBlackfin.h
new file mode 100644
index 000000000000..6341eebff3dc
--- /dev/null
+++ b/arch/blackfin/include/asm/def_LPBlackfin.h
@@ -0,0 +1,712 @@
1 /*
2 * File: include/asm-blackfin/mach-common/def_LPBlackfin.h
3 * Based on:
4 * Author: unknown
5 * COPYRIGHT 2005 Analog Devices
6 * Created: ?
7 * Description:
8 *
9 * Modified:
10 *
11 * Bugs: Enter bugs at http://blackfin.uclinux.org/
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2, or (at your option)
16 * any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; see the file COPYING.
25 * If not, write to the Free Software Foundation,
26 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 */
28
29/* LP Blackfin CORE REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532/33 */
30
31#ifndef _DEF_LPBLACKFIN_H
32#define _DEF_LPBLACKFIN_H
33
34#include <mach/anomaly.h>
35
36#define MK_BMSK_(x) (1<<x)
37
38#ifndef __ASSEMBLY__
39
40#include <linux/types.h>
41
42#if ANOMALY_05000198
43# define NOP_PAD_ANOMALY_05000198 "nop;"
44#else
45# define NOP_PAD_ANOMALY_05000198
46#endif
47
48#define bfin_read8(addr) ({ \
49 uint32_t __v; \
50 __asm__ __volatile__( \
51 NOP_PAD_ANOMALY_05000198 \
52 "%0 = b[%1] (z);" \
53 : "=d" (__v) \
54 : "a" (addr) \
55 ); \
56 __v; })
57
58#define bfin_read16(addr) ({ \
59 uint32_t __v; \
60 __asm__ __volatile__( \
61 NOP_PAD_ANOMALY_05000198 \
62 "%0 = w[%1] (z);" \
63 : "=d" (__v) \
64 : "a" (addr) \
65 ); \
66 __v; })
67
68#define bfin_read32(addr) ({ \
69 uint32_t __v; \
70 __asm__ __volatile__( \
71 NOP_PAD_ANOMALY_05000198 \
72 "%0 = [%1];" \
73 : "=d" (__v) \
74 : "a" (addr) \
75 ); \
76 __v; })
77
78#define bfin_write8(addr, val) \
79 __asm__ __volatile__( \
80 NOP_PAD_ANOMALY_05000198 \
81 "b[%0] = %1;" \
82 : \
83 : "a" (addr), "d" ((uint8_t)(val)) \
84 : "memory" \
85 )
86
87#define bfin_write16(addr, val) \
88 __asm__ __volatile__( \
89 NOP_PAD_ANOMALY_05000198 \
90 "w[%0] = %1;" \
91 : \
92 : "a" (addr), "d" ((uint16_t)(val)) \
93 : "memory" \
94 )
95
96#define bfin_write32(addr, val) \
97 __asm__ __volatile__( \
98 NOP_PAD_ANOMALY_05000198 \
99 "[%0] = %1;" \
100 : \
101 : "a" (addr), "d" (val) \
102 : "memory" \
103 )
104
105#endif /* __ASSEMBLY__ */
106
107/**************************************************
108 * System Register Bits
109 **************************************************/
110
111/**************************************************
112 * ASTAT register
113 **************************************************/
114
115/* definitions of ASTAT bit positions*/
116
117/*Result of last ALU0 or shifter operation is zero*/
118#define ASTAT_AZ_P 0x00000000
119/*Result of last ALU0 or shifter operation is negative*/
120#define ASTAT_AN_P 0x00000001
121/*Condition Code, used for holding comparison results*/
122#define ASTAT_CC_P 0x00000005
123/*Quotient Bit*/
124#define ASTAT_AQ_P 0x00000006
125/*Rounding mode, set for biased, clear for unbiased*/
126#define ASTAT_RND_MOD_P 0x00000008
127/*Result of last ALU0 operation generated a carry*/
128#define ASTAT_AC0_P 0x0000000C
129/*Result of last ALU0 operation generated a carry*/
130#define ASTAT_AC0_COPY_P 0x00000002
131/*Result of last ALU1 operation generated a carry*/
132#define ASTAT_AC1_P 0x0000000D
133/*Result of last ALU0 or MAC0 operation overflowed, sticky for MAC*/
134#define ASTAT_AV0_P 0x00000010
135/*Sticky version of ASTAT_AV0 */
136#define ASTAT_AV0S_P 0x00000011
137/*Result of last MAC1 operation overflowed, sticky for MAC*/
138#define ASTAT_AV1_P 0x00000012
139/*Sticky version of ASTAT_AV1 */
140#define ASTAT_AV1S_P 0x00000013
141/*Result of last ALU0 or MAC0 operation overflowed*/
142#define ASTAT_V_P 0x00000018
143/*Result of last ALU0 or MAC0 operation overflowed*/
144#define ASTAT_V_COPY_P 0x00000003
145/*Sticky version of ASTAT_V*/
146#define ASTAT_VS_P 0x00000019
147
148/* Masks */
149
150/*Result of last ALU0 or shifter operation is zero*/
151#define ASTAT_AZ MK_BMSK_(ASTAT_AZ_P)
152/*Result of last ALU0 or shifter operation is negative*/
153#define ASTAT_AN MK_BMSK_(ASTAT_AN_P)
154/*Result of last ALU0 operation generated a carry*/
155#define ASTAT_AC0 MK_BMSK_(ASTAT_AC0_P)
156/*Result of last ALU0 operation generated a carry*/
157#define ASTAT_AC0_COPY MK_BMSK_(ASTAT_AC0_COPY_P)
158/*Result of last ALU0 operation generated a carry*/
159#define ASTAT_AC1 MK_BMSK_(ASTAT_AC1_P)
160/*Result of last ALU0 or MAC0 operation overflowed, sticky for MAC*/
161#define ASTAT_AV0 MK_BMSK_(ASTAT_AV0_P)
162/*Result of last MAC1 operation overflowed, sticky for MAC*/
163#define ASTAT_AV1 MK_BMSK_(ASTAT_AV1_P)
164/*Condition Code, used for holding comparison results*/
165#define ASTAT_CC MK_BMSK_(ASTAT_CC_P)
166/*Quotient Bit*/
167#define ASTAT_AQ MK_BMSK_(ASTAT_AQ_P)
168/*Rounding mode, set for biased, clear for unbiased*/
169#define ASTAT_RND_MOD MK_BMSK_(ASTAT_RND_MOD_P)
170/*Overflow Bit*/
171#define ASTAT_V MK_BMSK_(ASTAT_V_P)
172/*Overflow Bit*/
173#define ASTAT_V_COPY MK_BMSK_(ASTAT_V_COPY_P)
174
175/**************************************************
176 * SEQSTAT register
177 **************************************************/
178
179/* Bit Positions */
180#define SEQSTAT_EXCAUSE0_P 0x00000000 /* Last exception cause bit 0 */
181#define SEQSTAT_EXCAUSE1_P 0x00000001 /* Last exception cause bit 1 */
182#define SEQSTAT_EXCAUSE2_P 0x00000002 /* Last exception cause bit 2 */
183#define SEQSTAT_EXCAUSE3_P 0x00000003 /* Last exception cause bit 3 */
184#define SEQSTAT_EXCAUSE4_P 0x00000004 /* Last exception cause bit 4 */
185#define SEQSTAT_EXCAUSE5_P 0x00000005 /* Last exception cause bit 5 */
186#define SEQSTAT_IDLE_REQ_P 0x0000000C /* Pending idle mode request,
187 * set by IDLE instruction.
188 */
189#define SEQSTAT_SFTRESET_P 0x0000000D /* Indicates whether the last
190 * reset was a software reset
191 * (=1)
192 */
193#define SEQSTAT_HWERRCAUSE0_P 0x0000000E /* Last hw error cause bit 0 */
194#define SEQSTAT_HWERRCAUSE1_P 0x0000000F /* Last hw error cause bit 1 */
195#define SEQSTAT_HWERRCAUSE2_P 0x00000010 /* Last hw error cause bit 2 */
196#define SEQSTAT_HWERRCAUSE3_P 0x00000011 /* Last hw error cause bit 3 */
197#define SEQSTAT_HWERRCAUSE4_P 0x00000012 /* Last hw error cause bit 4 */
198/* Masks */
199/* Exception cause */
200#define SEQSTAT_EXCAUSE (MK_BMSK_(SEQSTAT_EXCAUSE0_P) | \
201 MK_BMSK_(SEQSTAT_EXCAUSE1_P) | \
202 MK_BMSK_(SEQSTAT_EXCAUSE2_P) | \
203 MK_BMSK_(SEQSTAT_EXCAUSE3_P) | \
204 MK_BMSK_(SEQSTAT_EXCAUSE4_P) | \
205 MK_BMSK_(SEQSTAT_EXCAUSE5_P) | \
206 0)
207
208/* Indicates whether the last reset was a software reset (=1) */
209#define SEQSTAT_SFTRESET (MK_BMSK_(SEQSTAT_SFTRESET_P))
210
211/* Last hw error cause */
212#define SEQSTAT_HWERRCAUSE (MK_BMSK_(SEQSTAT_HWERRCAUSE0_P) | \
213 MK_BMSK_(SEQSTAT_HWERRCAUSE1_P) | \
214 MK_BMSK_(SEQSTAT_HWERRCAUSE2_P) | \
215 MK_BMSK_(SEQSTAT_HWERRCAUSE3_P) | \
216 MK_BMSK_(SEQSTAT_HWERRCAUSE4_P) | \
217 0)
218
219/* Translate bits to something useful */
220
221/* Last hw error cause */
222#define SEQSTAT_HWERRCAUSE_SHIFT (14)
223#define SEQSTAT_HWERRCAUSE_SYSTEM_MMR (0x02 << SEQSTAT_HWERRCAUSE_SHIFT)
224#define SEQSTAT_HWERRCAUSE_EXTERN_ADDR (0x03 << SEQSTAT_HWERRCAUSE_SHIFT)
225#define SEQSTAT_HWERRCAUSE_PERF_FLOW (0x12 << SEQSTAT_HWERRCAUSE_SHIFT)
226#define SEQSTAT_HWERRCAUSE_RAISE_5 (0x18 << SEQSTAT_HWERRCAUSE_SHIFT)
227
228/**************************************************
229 * SYSCFG register
230 **************************************************/
231
232/* Bit Positions */
233#define SYSCFG_SSSTEP_P 0x00000000 /* Supervisor single step, when
234 * set it forces an exception
235 * for each instruction executed
236 */
237#define SYSCFG_CCEN_P 0x00000001 /* Enable cycle counter (=1) */
238#define SYSCFG_SNEN_P 0x00000002 /* Self nesting Interrupt Enable */
239
240/* Masks */
241
242/* Supervisor single step, when set it forces an exception for each
243 *instruction executed
244 */
245#define SYSCFG_SSSTEP MK_BMSK_(SYSCFG_SSSTEP_P )
246/* Enable cycle counter (=1) */
247#define SYSCFG_CCEN MK_BMSK_(SYSCFG_CCEN_P )
248/* Self Nesting Interrupt Enable */
249#define SYSCFG_SNEN MK_BMSK_(SYSCFG_SNEN_P)
250/* Backward-compatibility for typos in prior releases */
251#define SYSCFG_SSSSTEP SYSCFG_SSSTEP
252#define SYSCFG_CCCEN SYSCFG_CCEN
253
254/****************************************************
255 * Core MMR Register Map
256 ****************************************************/
257
258/* Data Cache & SRAM Memory (0xFFE00000 - 0xFFE00404) */
259
260#define SRAM_BASE_ADDRESS 0xFFE00000 /* SRAM Base Address Register */
261#define DMEM_CONTROL 0xFFE00004 /* Data memory control */
262#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside
263 * Buffer Status
264 */
265#define DCPLB_FAULT_STATUS 0xFFE00008 /* "" (older define) */
266#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside
267 * Buffer Fault Address
268 */
269#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside
270 * Buffer 0
271 */
272#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside
273 * Buffer 1
274 */
275#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside
276 * Buffer 2
277 */
278#define DCPLB_ADDR3 0xFFE0010C /* Data Cacheability Protection
279 * Lookaside Buffer 3
280 */
281#define DCPLB_ADDR4 0xFFE00110 /* Data Cacheability Protection
282 * Lookaside Buffer 4
283 */
284#define DCPLB_ADDR5 0xFFE00114 /* Data Cacheability Protection
285 * Lookaside Buffer 5
286 */
287#define DCPLB_ADDR6 0xFFE00118 /* Data Cacheability Protection
288 * Lookaside Buffer 6
289 */
290#define DCPLB_ADDR7 0xFFE0011C /* Data Cacheability Protection
291 * Lookaside Buffer 7
292 */
293#define DCPLB_ADDR8 0xFFE00120 /* Data Cacheability Protection
294 * Lookaside Buffer 8
295 */
296#define DCPLB_ADDR9 0xFFE00124 /* Data Cacheability Protection
297 * Lookaside Buffer 9
298 */
299#define DCPLB_ADDR10 0xFFE00128 /* Data Cacheability Protection
300 * Lookaside Buffer 10
301 */
302#define DCPLB_ADDR11 0xFFE0012C /* Data Cacheability Protection
303 * Lookaside Buffer 11
304 */
305#define DCPLB_ADDR12 0xFFE00130 /* Data Cacheability Protection
306 * Lookaside Buffer 12
307 */
308#define DCPLB_ADDR13 0xFFE00134 /* Data Cacheability Protection
309 * Lookaside Buffer 13
310 */
311#define DCPLB_ADDR14 0xFFE00138 /* Data Cacheability Protection
312 * Lookaside Buffer 14
313 */
314#define DCPLB_ADDR15 0xFFE0013C /* Data Cacheability Protection
315 * Lookaside Buffer 15
316 */
317#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */
318#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */
319#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */
320#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */
321#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */
322#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */
323#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */
324#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */
325#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */
326#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */
327#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */
328#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */
329#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */
330#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */
331#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */
332#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */
333#define DCPLB_DATA16 0xFFE00240 /* Extra Dummy entry */
334
335#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */
336#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */
337#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */
338
339/* Instruction Cache & SRAM Memory (0xFFE01004 - 0xFFE01404) */
340
341#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */
342#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache miss status */
343#define CODE_FAULT_STATUS 0xFFE01008 /* "" (older define) */
344#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache miss address */
345#define CODE_FAULT_ADDR 0xFFE0100C /* "" (older define) */
346#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability
347 * Protection Lookaside Buffer 0
348 */
349#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability
350 * Protection Lookaside Buffer 1
351 */
352#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability
353 * Protection Lookaside Buffer 2
354 */
355#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability
356 * Protection Lookaside Buffer 3
357 */
358#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability
359 * Protection Lookaside Buffer 4
360 */
361#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability
362 * Protection Lookaside Buffer 5
363 */
364#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability
365 * Protection Lookaside Buffer 6
366 */
367#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability
368 * Protection Lookaside Buffer 7
369 */
370#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability
371 * Protection Lookaside Buffer 8
372 */
373#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability
374 * Protection Lookaside Buffer 9
375 */
376#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability
377 * Protection Lookaside Buffer 10
378 */
379#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability
380 * Protection Lookaside Buffer 11
381 */
382#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability
383 * Protection Lookaside Buffer 12
384 */
385#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability
386 * Protection Lookaside Buffer 13
387 */
388#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability
389 * Protection Lookaside Buffer 14
390 */
391#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability
392 * Protection Lookaside Buffer 15
393 */
394#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */
395#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */
396#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */
397#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */
398#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */
399#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */
400#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */
401#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */
402#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */
403#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */
404#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */
405#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */
406#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */
407#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */
408#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */
409#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */
410#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */
411#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */
412#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */
413
414/* Event/Interrupt Controller Registers (0xFFE02000 - 0xFFE02110) */
415
416#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */
417#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */
418#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */
419#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */
420#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */
421#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */
422#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */
423#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */
424#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */
425#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */
426#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */
427#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */
428#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */
429#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */
430#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */
431#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */
432#define IMASK 0xFFE02104 /* Interrupt Mask Register */
433#define IPEND 0xFFE02108 /* Interrupt Pending Register */
434#define ILAT 0xFFE0210C /* Interrupt Latch Register */
435#define IPRIO 0xFFE02110 /* Core Interrupt Priority Register */
436
437/* Core Timer Registers (0xFFE03000 - 0xFFE0300C) */
438
439#define TCNTL 0xFFE03000 /* Core Timer Control Register */
440#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
441#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
442#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
443
444/* Debug/MP/Emulation Registers (0xFFE05000 - 0xFFE05008) */
445#define DSPID 0xFFE05000 /* DSP Processor ID Register for
446 * MP implementations
447 */
448
449#define DBGSTAT 0xFFE05008 /* Debug Status Register */
450
451/* Trace Buffer Registers (0xFFE06000 - 0xFFE06100) */
452
453#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
454#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
455#define TBUF 0xFFE06100 /* Trace Buffer */
456
457/* Watchpoint Control Registers (0xFFE07000 - 0xFFE07200) */
458
459/* Watchpoint Instruction Address Control Register */
460#define WPIACTL 0xFFE07000
461/* Watchpoint Instruction Address Register 0 */
462#define WPIA0 0xFFE07040
463/* Watchpoint Instruction Address Register 1 */
464#define WPIA1 0xFFE07044
465/* Watchpoint Instruction Address Register 2 */
466#define WPIA2 0xFFE07048
467/* Watchpoint Instruction Address Register 3 */
468#define WPIA3 0xFFE0704C
469/* Watchpoint Instruction Address Register 4 */
470#define WPIA4 0xFFE07050
471/* Watchpoint Instruction Address Register 5 */
472#define WPIA5 0xFFE07054
473/* Watchpoint Instruction Address Count Register 0 */
474#define WPIACNT0 0xFFE07080
475/* Watchpoint Instruction Address Count Register 1 */
476#define WPIACNT1 0xFFE07084
477/* Watchpoint Instruction Address Count Register 2 */
478#define WPIACNT2 0xFFE07088
479/* Watchpoint Instruction Address Count Register 3 */
480#define WPIACNT3 0xFFE0708C
481/* Watchpoint Instruction Address Count Register 4 */
482#define WPIACNT4 0xFFE07090
483/* Watchpoint Instruction Address Count Register 5 */
484#define WPIACNT5 0xFFE07094
485/* Watchpoint Data Address Control Register */
486#define WPDACTL 0xFFE07100
487/* Watchpoint Data Address Register 0 */
488#define WPDA0 0xFFE07140
489/* Watchpoint Data Address Register 1 */
490#define WPDA1 0xFFE07144
491/* Watchpoint Data Address Count Value Register 0 */
492#define WPDACNT0 0xFFE07180
493/* Watchpoint Data Address Count Value Register 1 */
494#define WPDACNT1 0xFFE07184
495/* Watchpoint Status Register */
496#define WPSTAT 0xFFE07200
497
498/* Performance Monitor Registers (0xFFE08000 - 0xFFE08104) */
499
500/* Performance Monitor Control Register */
501#define PFCTL 0xFFE08000
502/* Performance Monitor Counter Register 0 */
503#define PFCNTR0 0xFFE08100
504/* Performance Monitor Counter Register 1 */
505#define PFCNTR1 0xFFE08104
506
507/****************************************************
508 * Core MMR Register Bits
509 ****************************************************/
510
511/**************************************************
512 * EVT registers (ILAT, IMASK, and IPEND).
513 **************************************************/
514
515/* Bit Positions */
516#define EVT_EMU_P 0x00000000 /* Emulator interrupt bit position */
517#define EVT_RST_P 0x00000001 /* Reset interrupt bit position */
518#define EVT_NMI_P 0x00000002 /* Non Maskable interrupt bit position */
519#define EVT_EVX_P 0x00000003 /* Exception bit position */
520#define EVT_IRPTEN_P 0x00000004 /* Global interrupt enable bit position */
521#define EVT_IVHW_P 0x00000005 /* Hardware Error interrupt bit position */
522#define EVT_IVTMR_P 0x00000006 /* Timer interrupt bit position */
523#define EVT_IVG7_P 0x00000007 /* IVG7 interrupt bit position */
524#define EVT_IVG8_P 0x00000008 /* IVG8 interrupt bit position */
525#define EVT_IVG9_P 0x00000009 /* IVG9 interrupt bit position */
526#define EVT_IVG10_P 0x0000000a /* IVG10 interrupt bit position */
527#define EVT_IVG11_P 0x0000000b /* IVG11 interrupt bit position */
528#define EVT_IVG12_P 0x0000000c /* IVG12 interrupt bit position */
529#define EVT_IVG13_P 0x0000000d /* IVG13 interrupt bit position */
530#define EVT_IVG14_P 0x0000000e /* IVG14 interrupt bit position */
531#define EVT_IVG15_P 0x0000000f /* IVG15 interrupt bit position */
532
533/* Masks */
534#define EVT_EMU MK_BMSK_(EVT_EMU_P ) /* Emulator interrupt mask */
535#define EVT_RST MK_BMSK_(EVT_RST_P ) /* Reset interrupt mask */
536#define EVT_NMI MK_BMSK_(EVT_NMI_P ) /* Non Maskable interrupt mask */
537#define EVT_EVX MK_BMSK_(EVT_EVX_P ) /* Exception mask */
538#define EVT_IRPTEN MK_BMSK_(EVT_IRPTEN_P) /* Global interrupt enable mask */
539#define EVT_IVHW MK_BMSK_(EVT_IVHW_P ) /* Hardware Error interrupt mask */
540#define EVT_IVTMR MK_BMSK_(EVT_IVTMR_P ) /* Timer interrupt mask */
541#define EVT_IVG7 MK_BMSK_(EVT_IVG7_P ) /* IVG7 interrupt mask */
542#define EVT_IVG8 MK_BMSK_(EVT_IVG8_P ) /* IVG8 interrupt mask */
543#define EVT_IVG9 MK_BMSK_(EVT_IVG9_P ) /* IVG9 interrupt mask */
544#define EVT_IVG10 MK_BMSK_(EVT_IVG10_P ) /* IVG10 interrupt mask */
545#define EVT_IVG11 MK_BMSK_(EVT_IVG11_P ) /* IVG11 interrupt mask */
546#define EVT_IVG12 MK_BMSK_(EVT_IVG12_P ) /* IVG12 interrupt mask */
547#define EVT_IVG13 MK_BMSK_(EVT_IVG13_P ) /* IVG13 interrupt mask */
548#define EVT_IVG14 MK_BMSK_(EVT_IVG14_P ) /* IVG14 interrupt mask */
549#define EVT_IVG15 MK_BMSK_(EVT_IVG15_P ) /* IVG15 interrupt mask */
550
551/**************************************************
552 * DMEM_CONTROL Register
553 **************************************************/
554/* Bit Positions */
555#define ENDM_P 0x00 /* (doesn't really exist) Enable
556 *Data Memory L1
557 */
558#define DMCTL_ENDM_P ENDM_P /* "" (older define) */
559
560#define ENDCPLB_P 0x01 /* Enable DCPLBS */
561#define DMCTL_ENDCPLB_P ENDCPLB_P /* "" (older define) */
562#define DMC0_P 0x02 /* L1 Data Memory Configure bit 0 */
563#define DMCTL_DMC0_P DMC0_P /* "" (older define) */
564#define DMC1_P 0x03 /* L1 Data Memory Configure bit 1 */
565#define DMCTL_DMC1_P DMC1_P /* "" (older define) */
566#define DCBS_P 0x04 /* L1 Data Cache Bank Select */
567#define PORT_PREF0_P 0x12 /* DAG0 Port Preference */
568#define PORT_PREF1_P 0x13 /* DAG1 Port Preference */
569
570/* Masks */
571#define ENDM 0x00000001 /* (doesn't really exist) Enable
572 * Data Memory L1
573 */
574#define ENDCPLB 0x00000002 /* Enable DCPLB */
575#define ASRAM_BSRAM 0x00000000
576#define ACACHE_BSRAM 0x00000008
577#define ACACHE_BCACHE 0x0000000C
578#define DCBS 0x00000010 /* L1 Data Cache Bank Select */
579#define PORT_PREF0 0x00001000 /* DAG0 Port Preference */
580#define PORT_PREF1 0x00002000 /* DAG1 Port Preference */
581
582/* IMEM_CONTROL Register */
583/* Bit Positions */
584#define ENIM_P 0x00 /* Enable L1 Code Memory */
585#define IMCTL_ENIM_P 0x00 /* "" (older define) */
586#define ENICPLB_P 0x01 /* Enable ICPLB */
587#define IMCTL_ENICPLB_P 0x01 /* "" (older define) */
588#define IMC_P 0x02 /* Enable */
589#define IMCTL_IMC_P 0x02 /* Configure L1 code memory as
590 * cache (0=SRAM)
591 */
592#define ILOC0_P 0x03 /* Lock Way 0 */
593#define ILOC1_P 0x04 /* Lock Way 1 */
594#define ILOC2_P 0x05 /* Lock Way 2 */
595#define ILOC3_P 0x06 /* Lock Way 3 */
596#define LRUPRIORST_P 0x0D /* Least Recently Used Replacement
597 * Priority
598 */
599/* Masks */
600#define ENIM 0x00000001 /* Enable L1 Code Memory */
601#define ENICPLB 0x00000002 /* Enable ICPLB */
602#define IMC 0x00000004 /* Configure L1 code memory as
603 * cache (0=SRAM)
604 */
605#define ILOC0 0x00000008 /* Lock Way 0 */
606#define ILOC1 0x00000010 /* Lock Way 1 */
607#define ILOC2 0x00000020 /* Lock Way 2 */
608#define ILOC3 0x00000040 /* Lock Way 3 */
609#define LRUPRIORST 0x00002000 /* Least Recently Used Replacement
610 * Priority
611 */
612
613/* TCNTL Masks */
614#define TMPWR 0x00000001 /* Timer Low Power Control,
615 * 0=low power mode, 1=active state
616 */
617#define TMREN 0x00000002 /* Timer enable, 0=disable, 1=enable */
618#define TAUTORLD 0x00000004 /* Timer auto reload */
619#define TINT 0x00000008 /* Timer generated interrupt 0=no
620 * interrupt has been generated,
621 * 1=interrupt has been generated
622 * (sticky)
623 */
624
625/* DCPLB_DATA and ICPLB_DATA Registers */
626/* Bit Positions */
627#define CPLB_VALID_P 0x00000000 /* 0=invalid entry, 1=valid entry */
628#define CPLB_LOCK_P 0x00000001 /* 0=entry may be replaced, 1=entry
629 * locked
630 */
631#define CPLB_USER_RD_P 0x00000002 /* 0=no read access, 1=read access
632 * allowed (user mode)
633 */
634/* Masks */
635#define CPLB_VALID 0x00000001 /* 0=invalid entry, 1=valid entry */
636#define CPLB_LOCK 0x00000002 /* 0=entry may be replaced, 1=entry
637 * locked
638 */
639#define CPLB_USER_RD 0x00000004 /* 0=no read access, 1=read access
640 * allowed (user mode)
641 */
642
643#define PAGE_SIZE_1KB 0x00000000 /* 1 KB page size */
644#define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */
645#define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */
646#define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */
647#define CPLB_L1SRAM 0x00000020 /* 0=SRAM mapped in L1, 0=SRAM not
648 * mapped to L1
649 */
650#define CPLB_PORTPRIO 0x00000200 /* 0=low priority port, 1= high
651 * priority port
652 */
653#define CPLB_L1_CHBL 0x00001000 /* 0=non-cacheable in L1, 1=cacheable
654 * in L1
655 */
656/* ICPLB_DATA only */
657#define CPLB_LRUPRIO 0x00000100 /* 0=can be replaced by any line,
658 * 1=priority for non-replacement
659 */
660/* DCPLB_DATA only */
661#define CPLB_USER_WR 0x00000008 /* 0=no write access, 0=write
662 * access allowed (user mode)
663 */
664#define CPLB_SUPV_WR 0x00000010 /* 0=no write access, 0=write
665 * access allowed (supervisor mode)
666 */
667#define CPLB_DIRTY 0x00000080 /* 1=dirty, 0=clean */
668#define CPLB_L1_AOW 0x00008000 /* 0=do not allocate cache lines on
669 * write-through writes,
670 * 1= allocate cache lines on
671 * write-through writes.
672 */
673#define CPLB_WT 0x00004000 /* 0=write-back, 1=write-through */
674
675#define CPLB_ALL_ACCESS CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR
676
677/* TBUFCTL Masks */
678#define TBUFPWR 0x0001
679#define TBUFEN 0x0002
680#define TBUFOVF 0x0004
681#define TBUFCMPLP_SINGLE 0x0008
682#define TBUFCMPLP_DOUBLE 0x0010
683#define TBUFCMPLP (TBUFCMPLP_SINGLE | TBUFCMPLP_DOUBLE)
684
685/* TBUFSTAT Masks */
686#define TBUFCNT 0x001F
687
688/* ITEST_COMMAND and DTEST_COMMAND Registers */
689/* Masks */
690#define TEST_READ 0x00000000 /* Read Access */
691#define TEST_WRITE 0x00000002 /* Write Access */
692#define TEST_TAG 0x00000000 /* Access TAG */
693#define TEST_DATA 0x00000004 /* Access DATA */
694#define TEST_DW0 0x00000000 /* Select Double Word 0 */
695#define TEST_DW1 0x00000008 /* Select Double Word 1 */
696#define TEST_DW2 0x00000010 /* Select Double Word 2 */
697#define TEST_DW3 0x00000018 /* Select Double Word 3 */
698#define TEST_MB0 0x00000000 /* Select Mini-Bank 0 */
699#define TEST_MB1 0x00010000 /* Select Mini-Bank 1 */
700#define TEST_MB2 0x00020000 /* Select Mini-Bank 2 */
701#define TEST_MB3 0x00030000 /* Select Mini-Bank 3 */
702#define TEST_SET(x) ((x << 5) & 0x03E0) /* Set Index 0->31 */
703#define TEST_WAY0 0x00000000 /* Access Way0 */
704#define TEST_WAY1 0x04000000 /* Access Way1 */
705/* ITEST_COMMAND only */
706#define TEST_WAY2 0x08000000 /* Access Way2 */
707#define TEST_WAY3 0x0C000000 /* Access Way3 */
708/* DTEST_COMMAND only */
709#define TEST_BNKSELA 0x00000000 /* Access SuperBank A */
710#define TEST_BNKSELB 0x00800000 /* Access SuperBank B */
711
712#endif /* _DEF_LPBLACKFIN_H */
diff --git a/arch/blackfin/include/asm/delay.h b/arch/blackfin/include/asm/delay.h
new file mode 100644
index 000000000000..0889c3abb593
--- /dev/null
+++ b/arch/blackfin/include/asm/delay.h
@@ -0,0 +1,62 @@
1/*
2 * delay.h - delay functions
3 *
4 * Copyright (c) 2004-2007 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef __ASM_DELAY_H__
10#define __ASM_DELAY_H__
11
12#include <mach/anomaly.h>
13
14static inline void __delay(unsigned long loops)
15{
16 if (ANOMALY_05000312) {
17 /* Interrupted loads to loop registers -> bad */
18 unsigned long tmp;
19 __asm__ __volatile__(
20 "[--SP] = LC0;"
21 "[--SP] = LT0;"
22 "[--SP] = LB0;"
23 "LSETUP (1f,1f) LC0 = %1;"
24 "1: NOP;"
25 /* We take advantage of the fact that LC0 is 0 at
26 * the end of the loop. Otherwise we'd need some
27 * NOPs after the CLI here.
28 */
29 "CLI %0;"
30 "LB0 = [SP++];"
31 "LT0 = [SP++];"
32 "LC0 = [SP++];"
33 "STI %0;"
34 : "=d" (tmp)
35 : "a" (loops)
36 );
37 } else
38 __asm__ __volatile__ (
39 "LSETUP(1f, 1f) LC0 = %0;"
40 "1: NOP;"
41 :
42 : "a" (loops)
43 : "LT0", "LB0", "LC0"
44 );
45}
46
47#include <linux/param.h> /* needed for HZ */
48
49/*
50 * Use only for very small delays ( < 1 msec). Should probably use a
51 * lookup table, really, as the multiplications take much too long with
52 * short delays. This is a "reasonable" implementation, though (and the
53 * first constant multiplications gets optimized away if the delay is
54 * a constant)
55 */
56static inline void udelay(unsigned long usecs)
57{
58 extern unsigned long loops_per_jiffy;
59 __delay(usecs * loops_per_jiffy / (1000000 / HZ));
60}
61
62#endif
diff --git a/arch/blackfin/include/asm/device.h b/arch/blackfin/include/asm/device.h
new file mode 100644
index 000000000000..d8f9872b0e2d
--- /dev/null
+++ b/arch/blackfin/include/asm/device.h
@@ -0,0 +1,7 @@
1/*
2 * Arch specific extensions to struct device
3 *
4 * This file is released under the GPLv2
5 */
6#include <asm-generic/device.h>
7
diff --git a/arch/blackfin/include/asm/div64.h b/arch/blackfin/include/asm/div64.h
new file mode 100644
index 000000000000..6cd978cefb28
--- /dev/null
+++ b/arch/blackfin/include/asm/div64.h
@@ -0,0 +1 @@
#include <asm-generic/div64.h>
diff --git a/arch/blackfin/include/asm/dma-mapping.h b/arch/blackfin/include/asm/dma-mapping.h
new file mode 100644
index 000000000000..1a13c2fc3667
--- /dev/null
+++ b/arch/blackfin/include/asm/dma-mapping.h
@@ -0,0 +1,83 @@
1#ifndef _BLACKFIN_DMA_MAPPING_H
2#define _BLACKFIN_DMA_MAPPING_H
3
4#include <asm/scatterlist.h>
5
6void dma_alloc_init(unsigned long start, unsigned long end);
7void *dma_alloc_coherent(struct device *dev, size_t size,
8 dma_addr_t *dma_handle, gfp_t gfp);
9void dma_free_coherent(struct device *dev, size_t size, void *vaddr,
10 dma_addr_t dma_handle);
11
12/*
13 * Now for the API extensions over the pci_ one
14 */
15#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
16#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
17
18#define dma_mapping_error
19
20/*
21 * Map a single buffer of the indicated size for DMA in streaming mode.
22 * The 32-bit bus address to use is returned.
23 *
24 * Once the device is given the dma address, the device owns this memory
25 * until either pci_unmap_single or pci_dma_sync_single is performed.
26 */
27extern dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size,
28 enum dma_data_direction direction);
29
30static inline dma_addr_t
31dma_map_page(struct device *dev, struct page *page,
32 unsigned long offset, size_t size,
33 enum dma_data_direction dir)
34{
35 return dma_map_single(dev, page_address(page) + offset, size, dir);
36}
37
38/*
39 * Unmap a single streaming mode DMA translation. The dma_addr and size
40 * must match what was provided for in a previous pci_map_single call. All
41 * other usages are undefined.
42 *
43 * After this call, reads by the cpu to the buffer are guarenteed to see
44 * whatever the device wrote there.
45 */
46extern void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
47 enum dma_data_direction direction);
48
49static inline void
50dma_unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
51 enum dma_data_direction dir)
52{
53 dma_unmap_single(dev, dma_addr, size, dir);
54}
55
56/*
57 * Map a set of buffers described by scatterlist in streaming
58 * mode for DMA. This is the scather-gather version of the
59 * above pci_map_single interface. Here the scatter gather list
60 * elements are each tagged with the appropriate dma address
61 * and length. They are obtained via sg_dma_{address,length}(SG).
62 *
63 * NOTE: An implementation may be able to use a smaller number of
64 * DMA address/length pairs than there are SG table elements.
65 * (for example via virtual mapping capabilities)
66 * The routine returns the number of addr/length pairs actually
67 * used, at most nents.
68 *
69 * Device ownership issues as mentioned above for pci_map_single are
70 * the same here.
71 */
72extern int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
73 enum dma_data_direction direction);
74
75/*
76 * Unmap a set of streaming mode DMA translations.
77 * Again, cpu read rules concerning calls here are the same as for
78 * pci_unmap_single() above.
79 */
80extern void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
81 int nhwentries, enum dma_data_direction direction);
82
83#endif /* _BLACKFIN_DMA_MAPPING_H */
diff --git a/arch/blackfin/include/asm/dma.h b/arch/blackfin/include/asm/dma.h
new file mode 100644
index 000000000000..6509733bb0f6
--- /dev/null
+++ b/arch/blackfin/include/asm/dma.h
@@ -0,0 +1,205 @@
1/*
2 * File: include/asm-blackfin/simple_bf533_dma.h
3 * Based on: none - original work
4 * Author: LG Soft India
5 * Copyright (C) 2004-2005 Analog Devices Inc.
6 * Created: Tue Sep 21 2004
7 * Description: This file contains the major Data structures and constants
8 * used for DMA Implementation in BF533
9 * Modified:
10 *
11 * Bugs: Enter bugs at http://blackfin.uclinux.org/
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2, or (at your option)
16 * any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; see the file COPYING.
25 * If not, write to the Free Software Foundation,
26 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 */
28
29#ifndef _BLACKFIN_DMA_H_
30#define _BLACKFIN_DMA_H_
31
32#include <asm/io.h>
33#include <linux/slab.h>
34#include <asm/irq.h>
35#include <asm/signal.h>
36
37#include <linux/kernel.h>
38#include <mach/dma.h>
39#include <linux/mm.h>
40#include <linux/interrupt.h>
41#include <asm/blackfin.h>
42
43#define MAX_DMA_ADDRESS PAGE_OFFSET
44
45/*****************************************************************************
46* Generic DMA Declarations
47*
48****************************************************************************/
49enum dma_chan_status {
50 DMA_CHANNEL_FREE,
51 DMA_CHANNEL_REQUESTED,
52 DMA_CHANNEL_ENABLED,
53};
54
55/*-------------------------
56 * config reg bits value
57 *-------------------------*/
58#define DATA_SIZE_8 0
59#define DATA_SIZE_16 1
60#define DATA_SIZE_32 2
61
62#define DMA_FLOW_STOP 0
63#define DMA_FLOW_AUTO 1
64#define DMA_FLOW_ARRAY 4
65#define DMA_FLOW_SMALL 6
66#define DMA_FLOW_LARGE 7
67
68#define DIMENSION_LINEAR 0
69#define DIMENSION_2D 1
70
71#define DIR_READ 0
72#define DIR_WRITE 1
73
74#define INTR_DISABLE 0
75#define INTR_ON_BUF 2
76#define INTR_ON_ROW 3
77
78#define DMA_NOSYNC_KEEP_DMA_BUF 0
79#define DMA_SYNC_RESTART 1
80
81struct dmasg {
82 unsigned long next_desc_addr;
83 unsigned long start_addr;
84 unsigned short cfg;
85 unsigned short x_count;
86 short x_modify;
87 unsigned short y_count;
88 short y_modify;
89} __attribute__((packed));
90
91struct dma_register {
92 unsigned long next_desc_ptr; /* DMA Next Descriptor Pointer register */
93 unsigned long start_addr; /* DMA Start address register */
94
95 unsigned short cfg; /* DMA Configuration register */
96 unsigned short dummy1; /* DMA Configuration register */
97
98 unsigned long reserved;
99
100 unsigned short x_count; /* DMA x_count register */
101 unsigned short dummy2;
102
103 short x_modify; /* DMA x_modify register */
104 unsigned short dummy3;
105
106 unsigned short y_count; /* DMA y_count register */
107 unsigned short dummy4;
108
109 short y_modify; /* DMA y_modify register */
110 unsigned short dummy5;
111
112 unsigned long curr_desc_ptr; /* DMA Current Descriptor Pointer
113 register */
114 unsigned long curr_addr_ptr; /* DMA Current Address Pointer
115 register */
116 unsigned short irq_status; /* DMA irq status register */
117 unsigned short dummy6;
118
119 unsigned short peripheral_map; /* DMA peripheral map register */
120 unsigned short dummy7;
121
122 unsigned short curr_x_count; /* DMA Current x-count register */
123 unsigned short dummy8;
124
125 unsigned long reserved2;
126
127 unsigned short curr_y_count; /* DMA Current y-count register */
128 unsigned short dummy9;
129
130 unsigned long reserved3;
131
132};
133
134typedef irqreturn_t(*dma_interrupt_t) (int irq, void *dev_id);
135
136struct dma_channel {
137 struct mutex dmalock;
138 char *device_id;
139 enum dma_chan_status chan_status;
140 struct dma_register *regs;
141 struct dmasg *sg; /* large mode descriptor */
142 unsigned int ctrl_num; /* controller number */
143 dma_interrupt_t irq_callback;
144 void *data;
145 unsigned int dma_enable_flag;
146 unsigned int loopback_flag;
147#ifdef CONFIG_PM
148 unsigned short saved_peripheral_map;
149#endif
150};
151
152#ifdef CONFIG_PM
153int blackfin_dma_suspend(void);
154void blackfin_dma_resume(void);
155#endif
156
157/*******************************************************************************
158* DMA API's
159*******************************************************************************/
160/* functions to set register mode */
161void set_dma_start_addr(unsigned int channel, unsigned long addr);
162void set_dma_next_desc_addr(unsigned int channel, unsigned long addr);
163void set_dma_curr_desc_addr(unsigned int channel, unsigned long addr);
164void set_dma_x_count(unsigned int channel, unsigned short x_count);
165void set_dma_x_modify(unsigned int channel, short x_modify);
166void set_dma_y_count(unsigned int channel, unsigned short y_count);
167void set_dma_y_modify(unsigned int channel, short y_modify);
168void set_dma_config(unsigned int channel, unsigned short config);
169unsigned short set_bfin_dma_config(char direction, char flow_mode,
170 char intr_mode, char dma_mode, char width,
171 char syncmode);
172void set_dma_curr_addr(unsigned int channel, unsigned long addr);
173
174/* get curr status for polling */
175unsigned short get_dma_curr_irqstat(unsigned int channel);
176unsigned short get_dma_curr_xcount(unsigned int channel);
177unsigned short get_dma_curr_ycount(unsigned int channel);
178unsigned long get_dma_next_desc_ptr(unsigned int channel);
179unsigned long get_dma_curr_desc_ptr(unsigned int channel);
180unsigned long get_dma_curr_addr(unsigned int channel);
181
182/* set large DMA mode descriptor */
183void set_dma_sg(unsigned int channel, struct dmasg *sg, int nr_sg);
184
185/* check if current channel is in use */
186int dma_channel_active(unsigned int channel);
187
188/* common functions must be called in any mode */
189void free_dma(unsigned int channel);
190int dma_channel_active(unsigned int channel); /* check if a channel is in use */
191void disable_dma(unsigned int channel);
192void enable_dma(unsigned int channel);
193int request_dma(unsigned int channel, char *device_id);
194int set_dma_callback(unsigned int channel, dma_interrupt_t callback,
195 void *data);
196void dma_disable_irq(unsigned int channel);
197void dma_enable_irq(unsigned int channel);
198void clear_dma_irqstat(unsigned int channel);
199void *dma_memcpy(void *dest, const void *src, size_t count);
200void *safe_dma_memcpy(void *dest, const void *src, size_t count);
201
202extern int channel2irq(unsigned int channel);
203extern struct dma_register *dma_io_base_addr[MAX_BLACKFIN_DMA_CHANNEL];
204
205#endif
diff --git a/arch/blackfin/include/asm/dpmc.h b/arch/blackfin/include/asm/dpmc.h
new file mode 100644
index 000000000000..96e8208f929a
--- /dev/null
+++ b/arch/blackfin/include/asm/dpmc.h
@@ -0,0 +1,57 @@
1/*
2 * include/asm-blackfin/dpmc.h - Miscellaneous IOCTL commands for Dynamic Power
3 * Management Controller Driver.
4 * Copyright (C) 2004-2008 Analog Device Inc.
5 *
6 */
7#ifndef _BLACKFIN_DPMC_H_
8#define _BLACKFIN_DPMC_H_
9
10#ifdef __KERNEL__
11#ifndef __ASSEMBLY__
12
13void sleep_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
14void hibernate_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
15void sleep_deeper(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
16void do_hibernate(int wakeup);
17void set_dram_srfs(void);
18void unset_dram_srfs(void);
19
20#define VRPAIR(vlev, freq) (((vlev) << 16) | ((freq) >> 16))
21
22struct bfin_dpmc_platform_data {
23 const unsigned int *tuple_tab;
24 unsigned short tabsize;
25 unsigned short vr_settling_time; /* in us */
26};
27
28#else
29
30#define PM_PUSH(x) \
31 R0 = [P0 + (x - SRAM_BASE_ADDRESS)];\
32 [--SP] = R0;\
33
34#define PM_POP(x) \
35 R0 = [SP++];\
36 [P0 + (x - SRAM_BASE_ADDRESS)] = R0;\
37
38#define PM_SYS_PUSH(x) \
39 R0 = [P0 + (x - PLL_CTL)];\
40 [--SP] = R0;\
41
42#define PM_SYS_POP(x) \
43 R0 = [SP++];\
44 [P0 + (x - PLL_CTL)] = R0;\
45
46#define PM_SYS_PUSH16(x) \
47 R0 = w[P0 + (x - PLL_CTL)];\
48 [--SP] = R0;\
49
50#define PM_SYS_POP16(x) \
51 R0 = [SP++];\
52 w[P0 + (x - PLL_CTL)] = R0;\
53
54#endif
55#endif /* __KERNEL__ */
56
57#endif /*_BLACKFIN_DPMC_H_*/
diff --git a/arch/blackfin/include/asm/early_printk.h b/arch/blackfin/include/asm/early_printk.h
new file mode 100644
index 000000000000..110f1c1f845c
--- /dev/null
+++ b/arch/blackfin/include/asm/early_printk.h
@@ -0,0 +1,28 @@
1/*
2 * File: include/asm-blackfin/early_printk.h
3 * Author: Robin Getz <rgetz@blackfin.uclinux.org
4 *
5 * Created: 14Aug2007
6 * Description: function prototpyes for early printk
7 *
8 * Modified:
9 * Copyright 2004-2007 Analog Devices Inc.
10 *
11 * Bugs: Enter bugs at http://blackfin.uclinux.org/
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 */
23
24#ifdef CONFIG_EARLY_PRINTK
25extern int setup_early_printk(char *);
26#else
27#define setup_early_printk(fmt) do { } while (0)
28#endif /* CONFIG_EARLY_PRINTK */
diff --git a/arch/blackfin/include/asm/elf.h b/arch/blackfin/include/asm/elf.h
new file mode 100644
index 000000000000..67a03a8a353e
--- /dev/null
+++ b/arch/blackfin/include/asm/elf.h
@@ -0,0 +1,127 @@
1/* Changes made by LG Soft Oct 2004*/
2
3#ifndef __ASMBFIN_ELF_H
4#define __ASMBFIN_ELF_H
5
6/*
7 * ELF register definitions..
8 */
9
10#include <asm/ptrace.h>
11#include <asm/user.h>
12
13/* Processor specific flags for the ELF header e_flags field. */
14#define EF_BFIN_PIC 0x00000001 /* -fpic */
15#define EF_BFIN_FDPIC 0x00000002 /* -mfdpic */
16#define EF_BFIN_CODE_IN_L1 0x00000010 /* --code-in-l1 */
17#define EF_BFIN_DATA_IN_L1 0x00000020 /* --data-in-l1 */
18#define EF_BFIN_CODE_IN_L2 0x00000040 /* --code-in-l2 */
19#define EF_BFIN_DATA_IN_L2 0x00000080 /* --data-in-l2 */
20
21typedef unsigned long elf_greg_t;
22
23#define ELF_NGREG (sizeof(struct user_regs_struct) / sizeof(elf_greg_t))
24typedef elf_greg_t elf_gregset_t[ELF_NGREG];
25
26typedef struct user_bfinfp_struct elf_fpregset_t;
27/*
28 * This is used to ensure we don't load something for the wrong architecture.
29 */
30#define elf_check_arch(x) ((x)->e_machine == EM_BLACKFIN)
31
32#define elf_check_fdpic(x) ((x)->e_flags & EF_BFIN_FDPIC /* && !((x)->e_flags & EF_FRV_NON_PIC_RELOCS) */)
33#define elf_check_const_displacement(x) ((x)->e_flags & EF_BFIN_PIC)
34
35/* EM_BLACKFIN defined in linux/elf.h */
36
37/*
38 * These are used to set parameters in the core dumps.
39 */
40#define ELF_CLASS ELFCLASS32
41#define ELF_DATA ELFDATA2LSB
42#define ELF_ARCH EM_BLACKFIN
43
44#define ELF_PLAT_INIT(_r) _r->p1 = 0
45
46#define ELF_FDPIC_PLAT_INIT(_regs, _exec_map_addr, _interp_map_addr, _dynamic_addr) \
47do { \
48 _regs->r7 = 0; \
49 _regs->p0 = _exec_map_addr; \
50 _regs->p1 = _interp_map_addr; \
51 _regs->p2 = _dynamic_addr; \
52} while(0)
53
54#define USE_ELF_CORE_DUMP
55#define ELF_FDPIC_CORE_EFLAGS EF_BFIN_FDPIC
56#define ELF_EXEC_PAGESIZE 4096
57
58#define R_unused0 0 /* relocation type 0 is not defined */
59#define R_pcrel5m2 1 /*LSETUP part a */
60#define R_unused1 2 /* relocation type 2 is not defined */
61#define R_pcrel10 3 /* type 3, if cc jump <target> */
62#define R_pcrel12_jump 4 /* type 4, jump <target> */
63#define R_rimm16 5 /* type 0x5, rN = <target> */
64#define R_luimm16 6 /* # 0x6, preg.l=<target> Load imm 16 to lower half */
65#define R_huimm16 7 /* # 0x7, preg.h=<target> Load imm 16 to upper half */
66#define R_pcrel12_jump_s 8 /* # 0x8 jump.s <target> */
67#define R_pcrel24_jump_x 9 /* # 0x9 jump.x <target> */
68#define R_pcrel24 10 /* # 0xa call <target> , not expandable */
69#define R_unusedb 11 /* # 0xb not generated */
70#define R_unusedc 12 /* # 0xc not used */
71#define R_pcrel24_jump_l 13 /*0xd jump.l <target> */
72#define R_pcrel24_call_x 14 /* 0xE, call.x <target> if <target> is above 24 bit limit call through P1 */
73#define R_var_eq_symb 15 /* 0xf, linker should treat it same as 0x12 */
74#define R_byte_data 16 /* 0x10, .byte var = symbol */
75#define R_byte2_data 17 /* 0x11, .byte2 var = symbol */
76#define R_byte4_data 18 /* 0x12, .byte4 var = symbol and .var var=symbol */
77#define R_pcrel11 19 /* 0x13, lsetup part b */
78#define R_unused14 20 /* 0x14, undefined */
79#define R_unused15 21 /* not generated by VDSP 3.5 */
80
81/* arithmetic relocations */
82#define R_push 0xE0
83#define R_const 0xE1
84#define R_add 0xE2
85#define R_sub 0xE3
86#define R_mult 0xE4
87#define R_div 0xE5
88#define R_mod 0xE6
89#define R_lshift 0xE7
90#define R_rshift 0xE8
91#define R_and 0xE9
92#define R_or 0xEA
93#define R_xor 0xEB
94#define R_land 0xEC
95#define R_lor 0xED
96#define R_len 0xEE
97#define R_neg 0xEF
98#define R_comp 0xF0
99#define R_page 0xF1
100#define R_hwpage 0xF2
101#define R_addr 0xF3
102
103/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
104 use of this is to invoke "./ld.so someprog" to test out a new version of
105 the loader. We need to make sure that it is out of the way of the program
106 that it will "exec", and that there is sufficient room for the brk. */
107
108#define ELF_ET_DYN_BASE 0xD0000000UL
109
110#define ELF_CORE_COPY_REGS(pr_reg, regs) \
111 memcpy((char *) &pr_reg, (char *)regs, \
112 sizeof(struct pt_regs));
113
114/* This yields a mask that user programs can use to figure out what
115 instruction set this cpu supports. */
116
117#define ELF_HWCAP (0)
118
119/* This yields a string that ld.so will use to load implementation
120 specific libraries for optimization. This is more specific in
121 intent than poking at uname or /proc/cpuinfo. */
122
123#define ELF_PLATFORM (NULL)
124
125#define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX)
126
127#endif
diff --git a/arch/blackfin/include/asm/emergency-restart.h b/arch/blackfin/include/asm/emergency-restart.h
new file mode 100644
index 000000000000..27f6c785d103
--- /dev/null
+++ b/arch/blackfin/include/asm/emergency-restart.h
@@ -0,0 +1,6 @@
1#ifndef _ASM_EMERGENCY_RESTART_H
2#define _ASM_EMERGENCY_RESTART_H
3
4#include <asm-generic/emergency-restart.h>
5
6#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/arch/blackfin/include/asm/entry.h b/arch/blackfin/include/asm/entry.h
new file mode 100644
index 000000000000..c4f721e0d00d
--- /dev/null
+++ b/arch/blackfin/include/asm/entry.h
@@ -0,0 +1,61 @@
1#ifndef __BFIN_ENTRY_H
2#define __BFIN_ENTRY_H
3
4#include <asm/setup.h>
5#include <asm/page.h>
6
7#ifdef __ASSEMBLY__
8
9#define LFLUSH_I_AND_D 0x00000808
10#define LSIGTRAP 5
11
12/* process bits for task_struct.flags */
13#define PF_TRACESYS_OFF 3
14#define PF_TRACESYS_BIT 5
15#define PF_PTRACED_OFF 3
16#define PF_PTRACED_BIT 4
17#define PF_DTRACE_OFF 1
18#define PF_DTRACE_BIT 5
19
20/*
21 * NOTE! The single-stepping code assumes that all interrupt handlers
22 * start by saving SYSCFG on the stack with their first instruction.
23 */
24
25/* This one is used for exceptions, emulation, and NMI. It doesn't push
26 RETI and doesn't do cli. */
27#define SAVE_ALL_SYS save_context_no_interrupts
28/* This is used for all normal interrupts. It saves a minimum of registers
29 to the stack, loads the IRQ number, and jumps to common code. */
30#define INTERRUPT_ENTRY(N) \
31 [--sp] = SYSCFG; \
32 \
33 [--sp] = P0; /*orig_p0*/ \
34 [--sp] = R0; /*orig_r0*/ \
35 [--sp] = (R7:0,P5:0); \
36 R0 = (N); \
37 jump __common_int_entry;
38
39/* For timer interrupts, we need to save IPEND, since the user_mode
40 macro accesses it to determine where to account time. */
41#define TIMER_INTERRUPT_ENTRY(N) \
42 [--sp] = SYSCFG; \
43 \
44 [--sp] = P0; /*orig_p0*/ \
45 [--sp] = R0; /*orig_r0*/ \
46 [--sp] = (R7:0,P5:0); \
47 p0.l = lo(IPEND); \
48 p0.h = hi(IPEND); \
49 r1 = [p0]; \
50 R0 = (N); \
51 jump __common_int_entry;
52
53/* This one pushes RETI without using CLI. Interrupts are enabled. */
54#define SAVE_CONTEXT_SYSCALL save_context_syscall
55#define SAVE_CONTEXT save_context_with_interrupts
56
57#define RESTORE_ALL_SYS restore_context_no_interrupts
58#define RESTORE_CONTEXT restore_context_with_interrupts
59
60#endif /* __ASSEMBLY__ */
61#endif /* __BFIN_ENTRY_H */
diff --git a/arch/blackfin/include/asm/errno.h b/arch/blackfin/include/asm/errno.h
new file mode 100644
index 000000000000..164e4f39bb57
--- /dev/null
+++ b/arch/blackfin/include/asm/errno.h
@@ -0,0 +1,6 @@
1#ifndef _BFIN_ERRNO_H
2#define _BFIN_ERRNO_H
3
4#include<asm-generic/errno.h>
5
6#endif /* _BFIN_ERRNO_H */
diff --git a/arch/blackfin/include/asm/fb.h b/arch/blackfin/include/asm/fb.h
new file mode 100644
index 000000000000..c7df38030992
--- /dev/null
+++ b/arch/blackfin/include/asm/fb.h
@@ -0,0 +1,12 @@
1#ifndef _ASM_FB_H_
2#define _ASM_FB_H_
3#include <linux/fb.h>
4
5#define fb_pgprotect(...) do {} while (0)
6
7static inline int fb_is_primary_device(struct fb_info *info)
8{
9 return 0;
10}
11
12#endif /* _ASM_FB_H_ */
diff --git a/arch/blackfin/include/asm/fcntl.h b/arch/blackfin/include/asm/fcntl.h
new file mode 100644
index 000000000000..9c4037127857
--- /dev/null
+++ b/arch/blackfin/include/asm/fcntl.h
@@ -0,0 +1,13 @@
1#ifndef _BFIN_FCNTL_H
2#define _BFIN_FCNTL_H
3
4/* open/fcntl - O_SYNC is only implemented on blocks devices and on files
5 located on an ext2 file system */
6#define O_DIRECTORY 040000 /* must be a directory */
7#define O_NOFOLLOW 0100000 /* don't follow links */
8#define O_DIRECT 0200000 /* direct disk access hint - currently ignored */
9#define O_LARGEFILE 0400000
10
11#include <asm-generic/fcntl.h>
12
13#endif
diff --git a/arch/blackfin/include/asm/fixed_code.h b/arch/blackfin/include/asm/fixed_code.h
new file mode 100644
index 000000000000..32c4d495d847
--- /dev/null
+++ b/arch/blackfin/include/asm/fixed_code.h
@@ -0,0 +1,46 @@
1/* This file defines the fixed addresses where userspace programs can find
2 atomic code sequences. */
3
4#ifndef __BFIN_ASM_FIXED_CODE_H__
5#define __BFIN_ASM_FIXED_CODE_H__
6
7#ifdef __KERNEL__
8#ifndef __ASSEMBLY__
9#include <linux/linkage.h>
10#include <linux/ptrace.h>
11extern asmlinkage void finish_atomic_sections(struct pt_regs *regs);
12extern char fixed_code_start;
13extern char fixed_code_end;
14extern int atomic_xchg32(void);
15extern int atomic_cas32(void);
16extern int atomic_add32(void);
17extern int atomic_sub32(void);
18extern int atomic_ior32(void);
19extern int atomic_and32(void);
20extern int atomic_xor32(void);
21extern void safe_user_instruction(void);
22extern void sigreturn_stub(void);
23#endif
24#endif
25
26#define FIXED_CODE_START 0x400
27
28#define SIGRETURN_STUB 0x400
29
30#define ATOMIC_SEQS_START 0x410
31
32#define ATOMIC_XCHG32 0x410
33#define ATOMIC_CAS32 0x420
34#define ATOMIC_ADD32 0x430
35#define ATOMIC_SUB32 0x440
36#define ATOMIC_IOR32 0x450
37#define ATOMIC_AND32 0x460
38#define ATOMIC_XOR32 0x470
39
40#define ATOMIC_SEQS_END 0x480
41
42#define SAFE_USER_INSTRUCTION 0x480
43
44#define FIXED_CODE_END 0x490
45
46#endif
diff --git a/arch/blackfin/include/asm/flat.h b/arch/blackfin/include/asm/flat.h
new file mode 100644
index 000000000000..e70074e05f4e
--- /dev/null
+++ b/arch/blackfin/include/asm/flat.h
@@ -0,0 +1,58 @@
1/*
2 * include/asm-blackfin/flat.h -- uClinux flat-format executables
3 *
4 * Copyright (C) 2003,
5 *
6 */
7
8#ifndef __BLACKFIN_FLAT_H__
9#define __BLACKFIN_FLAT_H__
10
11#include <asm/unaligned.h>
12
13#define flat_stack_align(sp) /* nothing needed */
14#define flat_argvp_envp_on_stack() 0
15#define flat_old_ram_flag(flags) (flags)
16
17extern unsigned long bfin_get_addr_from_rp (unsigned long *ptr,
18 unsigned long relval,
19 unsigned long flags,
20 unsigned long *persistent);
21
22extern void bfin_put_addr_at_rp(unsigned long *ptr, unsigned long addr,
23 unsigned long relval);
24
25/* The amount by which a relocation can exceed the program image limits
26 without being regarded as an error. */
27
28#define flat_reloc_valid(reloc, size) ((reloc) <= (size))
29
30#define flat_get_addr_from_rp(rp, relval, flags, persistent) \
31 bfin_get_addr_from_rp(rp, relval, flags, persistent)
32#define flat_put_addr_at_rp(rp, val, relval) \
33 bfin_put_addr_at_rp(rp, val, relval)
34
35/* Convert a relocation entry into an address. */
36static inline unsigned long
37flat_get_relocate_addr (unsigned long relval)
38{
39 return relval & 0x03ffffff; /* Mask out top 6 bits */
40}
41
42static inline int flat_set_persistent(unsigned long relval,
43 unsigned long *persistent)
44{
45 int type = (relval >> 26) & 7;
46 if (type == 3) {
47 *persistent = relval << 16;
48 return 1;
49 }
50 return 0;
51}
52
53static inline int flat_addr_absolute(unsigned long relval)
54{
55 return (relval & (1 << 29)) != 0;
56}
57
58#endif /* __BLACKFIN_FLAT_H__ */
diff --git a/arch/blackfin/include/asm/futex.h b/arch/blackfin/include/asm/futex.h
new file mode 100644
index 000000000000..6a332a9f099c
--- /dev/null
+++ b/arch/blackfin/include/asm/futex.h
@@ -0,0 +1,6 @@
1#ifndef _ASM_FUTEX_H
2#define _ASM_FUTEX_H
3
4#include <asm-generic/futex.h>
5
6#endif
diff --git a/arch/blackfin/include/asm/gpio.h b/arch/blackfin/include/asm/gpio.h
new file mode 100644
index 000000000000..ad33ac271fd9
--- /dev/null
+++ b/arch/blackfin/include/asm/gpio.h
@@ -0,0 +1,456 @@
1/*
2 * File: arch/blackfin/kernel/bfin_gpio.h
3 * Based on:
4 * Author: Michael Hennerich (hennerich@blackfin.uclinux.org)
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2004-2008 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30/*
31* Number BF537/6/4 BF561 BF533/2/1
32* BF527/5/2
33*
34* GPIO_0 PF0 PF0 PF0
35* GPIO_1 PF1 PF1 PF1
36* GPIO_2 PF2 PF2 PF2
37* GPIO_3 PF3 PF3 PF3
38* GPIO_4 PF4 PF4 PF4
39* GPIO_5 PF5 PF5 PF5
40* GPIO_6 PF6 PF6 PF6
41* GPIO_7 PF7 PF7 PF7
42* GPIO_8 PF8 PF8 PF8
43* GPIO_9 PF9 PF9 PF9
44* GPIO_10 PF10 PF10 PF10
45* GPIO_11 PF11 PF11 PF11
46* GPIO_12 PF12 PF12 PF12
47* GPIO_13 PF13 PF13 PF13
48* GPIO_14 PF14 PF14 PF14
49* GPIO_15 PF15 PF15 PF15
50* GPIO_16 PG0 PF16
51* GPIO_17 PG1 PF17
52* GPIO_18 PG2 PF18
53* GPIO_19 PG3 PF19
54* GPIO_20 PG4 PF20
55* GPIO_21 PG5 PF21
56* GPIO_22 PG6 PF22
57* GPIO_23 PG7 PF23
58* GPIO_24 PG8 PF24
59* GPIO_25 PG9 PF25
60* GPIO_26 PG10 PF26
61* GPIO_27 PG11 PF27
62* GPIO_28 PG12 PF28
63* GPIO_29 PG13 PF29
64* GPIO_30 PG14 PF30
65* GPIO_31 PG15 PF31
66* GPIO_32 PH0 PF32
67* GPIO_33 PH1 PF33
68* GPIO_34 PH2 PF34
69* GPIO_35 PH3 PF35
70* GPIO_36 PH4 PF36
71* GPIO_37 PH5 PF37
72* GPIO_38 PH6 PF38
73* GPIO_39 PH7 PF39
74* GPIO_40 PH8 PF40
75* GPIO_41 PH9 PF41
76* GPIO_42 PH10 PF42
77* GPIO_43 PH11 PF43
78* GPIO_44 PH12 PF44
79* GPIO_45 PH13 PF45
80* GPIO_46 PH14 PF46
81* GPIO_47 PH15 PF47
82*/
83
84#ifndef __ARCH_BLACKFIN_GPIO_H__
85#define __ARCH_BLACKFIN_GPIO_H__
86
87#define gpio_bank(x) ((x) >> 4)
88#define gpio_bit(x) (1<<((x) & 0xF))
89#define gpio_sub_n(x) ((x) & 0xF)
90
91#define GPIO_BANKSIZE 16
92
93#define GPIO_0 0
94#define GPIO_1 1
95#define GPIO_2 2
96#define GPIO_3 3
97#define GPIO_4 4
98#define GPIO_5 5
99#define GPIO_6 6
100#define GPIO_7 7
101#define GPIO_8 8
102#define GPIO_9 9
103#define GPIO_10 10
104#define GPIO_11 11
105#define GPIO_12 12
106#define GPIO_13 13
107#define GPIO_14 14
108#define GPIO_15 15
109#define GPIO_16 16
110#define GPIO_17 17
111#define GPIO_18 18
112#define GPIO_19 19
113#define GPIO_20 20
114#define GPIO_21 21
115#define GPIO_22 22
116#define GPIO_23 23
117#define GPIO_24 24
118#define GPIO_25 25
119#define GPIO_26 26
120#define GPIO_27 27
121#define GPIO_28 28
122#define GPIO_29 29
123#define GPIO_30 30
124#define GPIO_31 31
125#define GPIO_32 32
126#define GPIO_33 33
127#define GPIO_34 34
128#define GPIO_35 35
129#define GPIO_36 36
130#define GPIO_37 37
131#define GPIO_38 38
132#define GPIO_39 39
133#define GPIO_40 40
134#define GPIO_41 41
135#define GPIO_42 42
136#define GPIO_43 43
137#define GPIO_44 44
138#define GPIO_45 45
139#define GPIO_46 46
140#define GPIO_47 47
141
142
143#define PERIPHERAL_USAGE 1
144#define GPIO_USAGE 0
145
146#ifdef BF533_FAMILY
147#define MAX_BLACKFIN_GPIOS 16
148
149#define GPIO_PF0 0
150#define GPIO_PF1 1
151#define GPIO_PF2 2
152#define GPIO_PF3 3
153#define GPIO_PF4 4
154#define GPIO_PF5 5
155#define GPIO_PF6 6
156#define GPIO_PF7 7
157#define GPIO_PF8 8
158#define GPIO_PF9 9
159#define GPIO_PF10 10
160#define GPIO_PF11 11
161#define GPIO_PF12 12
162#define GPIO_PF13 13
163#define GPIO_PF14 14
164#define GPIO_PF15 15
165
166#endif
167
168#if defined(BF527_FAMILY) || defined(BF537_FAMILY)
169#define MAX_BLACKFIN_GPIOS 48
170
171#define GPIO_PF0 0
172#define GPIO_PF1 1
173#define GPIO_PF2 2
174#define GPIO_PF3 3
175#define GPIO_PF4 4
176#define GPIO_PF5 5
177#define GPIO_PF6 6
178#define GPIO_PF7 7
179#define GPIO_PF8 8
180#define GPIO_PF9 9
181#define GPIO_PF10 10
182#define GPIO_PF11 11
183#define GPIO_PF12 12
184#define GPIO_PF13 13
185#define GPIO_PF14 14
186#define GPIO_PF15 15
187#define GPIO_PG0 16
188#define GPIO_PG1 17
189#define GPIO_PG2 18
190#define GPIO_PG3 19
191#define GPIO_PG4 20
192#define GPIO_PG5 21
193#define GPIO_PG6 22
194#define GPIO_PG7 23
195#define GPIO_PG8 24
196#define GPIO_PG9 25
197#define GPIO_PG10 26
198#define GPIO_PG11 27
199#define GPIO_PG12 28
200#define GPIO_PG13 29
201#define GPIO_PG14 30
202#define GPIO_PG15 31
203#define GPIO_PH0 32
204#define GPIO_PH1 33
205#define GPIO_PH2 34
206#define GPIO_PH3 35
207#define GPIO_PH4 36
208#define GPIO_PH5 37
209#define GPIO_PH6 38
210#define GPIO_PH7 39
211#define GPIO_PH8 40
212#define GPIO_PH9 41
213#define GPIO_PH10 42
214#define GPIO_PH11 43
215#define GPIO_PH12 44
216#define GPIO_PH13 45
217#define GPIO_PH14 46
218#define GPIO_PH15 47
219
220#define PORT_F GPIO_PF0
221#define PORT_G GPIO_PG0
222#define PORT_H GPIO_PH0
223
224#endif
225
226#ifdef BF548_FAMILY
227#include <mach/gpio.h>
228#endif
229
230#ifdef BF561_FAMILY
231#define MAX_BLACKFIN_GPIOS 48
232
233#define GPIO_PF0 0
234#define GPIO_PF1 1
235#define GPIO_PF2 2
236#define GPIO_PF3 3
237#define GPIO_PF4 4
238#define GPIO_PF5 5
239#define GPIO_PF6 6
240#define GPIO_PF7 7
241#define GPIO_PF8 8
242#define GPIO_PF9 9
243#define GPIO_PF10 10
244#define GPIO_PF11 11
245#define GPIO_PF12 12
246#define GPIO_PF13 13
247#define GPIO_PF14 14
248#define GPIO_PF15 15
249#define GPIO_PF16 16
250#define GPIO_PF17 17
251#define GPIO_PF18 18
252#define GPIO_PF19 19
253#define GPIO_PF20 20
254#define GPIO_PF21 21
255#define GPIO_PF22 22
256#define GPIO_PF23 23
257#define GPIO_PF24 24
258#define GPIO_PF25 25
259#define GPIO_PF26 26
260#define GPIO_PF27 27
261#define GPIO_PF28 28
262#define GPIO_PF29 29
263#define GPIO_PF30 30
264#define GPIO_PF31 31
265#define GPIO_PF32 32
266#define GPIO_PF33 33
267#define GPIO_PF34 34
268#define GPIO_PF35 35
269#define GPIO_PF36 36
270#define GPIO_PF37 37
271#define GPIO_PF38 38
272#define GPIO_PF39 39
273#define GPIO_PF40 40
274#define GPIO_PF41 41
275#define GPIO_PF42 42
276#define GPIO_PF43 43
277#define GPIO_PF44 44
278#define GPIO_PF45 45
279#define GPIO_PF46 46
280#define GPIO_PF47 47
281
282#define PORT_FIO0 GPIO_0
283#define PORT_FIO1 GPIO_16
284#define PORT_FIO2 GPIO_32
285#endif
286
287#ifndef __ASSEMBLY__
288
289/***********************************************************
290*
291* FUNCTIONS: Blackfin General Purpose Ports Access Functions
292*
293* INPUTS/OUTPUTS:
294* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
295*
296*
297* DESCRIPTION: These functions abstract direct register access
298* to Blackfin processor General Purpose
299* Ports Regsiters
300*
301* CAUTION: These functions do not belong to the GPIO Driver API
302*************************************************************
303* MODIFICATION HISTORY :
304**************************************************************/
305
306#ifndef BF548_FAMILY
307void set_gpio_dir(unsigned, unsigned short);
308void set_gpio_inen(unsigned, unsigned short);
309void set_gpio_polar(unsigned, unsigned short);
310void set_gpio_edge(unsigned, unsigned short);
311void set_gpio_both(unsigned, unsigned short);
312void set_gpio_data(unsigned, unsigned short);
313void set_gpio_maska(unsigned, unsigned short);
314void set_gpio_maskb(unsigned, unsigned short);
315void set_gpio_toggle(unsigned);
316void set_gpiop_dir(unsigned, unsigned short);
317void set_gpiop_inen(unsigned, unsigned short);
318void set_gpiop_polar(unsigned, unsigned short);
319void set_gpiop_edge(unsigned, unsigned short);
320void set_gpiop_both(unsigned, unsigned short);
321void set_gpiop_data(unsigned, unsigned short);
322void set_gpiop_maska(unsigned, unsigned short);
323void set_gpiop_maskb(unsigned, unsigned short);
324unsigned short get_gpio_dir(unsigned);
325unsigned short get_gpio_inen(unsigned);
326unsigned short get_gpio_polar(unsigned);
327unsigned short get_gpio_edge(unsigned);
328unsigned short get_gpio_both(unsigned);
329unsigned short get_gpio_maska(unsigned);
330unsigned short get_gpio_maskb(unsigned);
331unsigned short get_gpio_data(unsigned);
332unsigned short get_gpiop_dir(unsigned);
333unsigned short get_gpiop_inen(unsigned);
334unsigned short get_gpiop_polar(unsigned);
335unsigned short get_gpiop_edge(unsigned);
336unsigned short get_gpiop_both(unsigned);
337unsigned short get_gpiop_maska(unsigned);
338unsigned short get_gpiop_maskb(unsigned);
339unsigned short get_gpiop_data(unsigned);
340
341struct gpio_port_t {
342 unsigned short data;
343 unsigned short dummy1;
344 unsigned short data_clear;
345 unsigned short dummy2;
346 unsigned short data_set;
347 unsigned short dummy3;
348 unsigned short toggle;
349 unsigned short dummy4;
350 unsigned short maska;
351 unsigned short dummy5;
352 unsigned short maska_clear;
353 unsigned short dummy6;
354 unsigned short maska_set;
355 unsigned short dummy7;
356 unsigned short maska_toggle;
357 unsigned short dummy8;
358 unsigned short maskb;
359 unsigned short dummy9;
360 unsigned short maskb_clear;
361 unsigned short dummy10;
362 unsigned short maskb_set;
363 unsigned short dummy11;
364 unsigned short maskb_toggle;
365 unsigned short dummy12;
366 unsigned short dir;
367 unsigned short dummy13;
368 unsigned short polar;
369 unsigned short dummy14;
370 unsigned short edge;
371 unsigned short dummy15;
372 unsigned short both;
373 unsigned short dummy16;
374 unsigned short inen;
375};
376#endif
377
378#ifdef CONFIG_PM
379
380unsigned int bfin_pm_standby_setup(void);
381void bfin_pm_standby_restore(void);
382
383void bfin_gpio_pm_hibernate_restore(void);
384void bfin_gpio_pm_hibernate_suspend(void);
385
386#ifndef CONFIG_BF54x
387#define PM_WAKE_RISING 0x1
388#define PM_WAKE_FALLING 0x2
389#define PM_WAKE_HIGH 0x4
390#define PM_WAKE_LOW 0x8
391#define PM_WAKE_BOTH_EDGES (PM_WAKE_RISING | PM_WAKE_FALLING)
392#define PM_WAKE_IGNORE 0xF0
393
394int gpio_pm_wakeup_request(unsigned gpio, unsigned char type);
395void gpio_pm_wakeup_free(unsigned gpio);
396
397struct gpio_port_s {
398 unsigned short data;
399 unsigned short maska;
400 unsigned short maskb;
401 unsigned short dir;
402 unsigned short polar;
403 unsigned short edge;
404 unsigned short both;
405 unsigned short inen;
406
407 unsigned short fer;
408 unsigned short reserved;
409 unsigned short mux;
410};
411#endif /*CONFIG_BF54x*/
412#endif /*CONFIG_PM*/
413/***********************************************************
414*
415* FUNCTIONS: Blackfin GPIO Driver
416*
417* INPUTS/OUTPUTS:
418* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
419*
420*
421* DESCRIPTION: Blackfin GPIO Driver API
422*
423* CAUTION:
424*************************************************************
425* MODIFICATION HISTORY :
426**************************************************************/
427
428int gpio_request(unsigned, const char *);
429void gpio_free(unsigned);
430
431void gpio_set_value(unsigned gpio, int arg);
432int gpio_get_value(unsigned gpio);
433
434#ifndef BF548_FAMILY
435#define gpio_set_value(gpio, value) set_gpio_data(gpio, value)
436#endif
437
438int gpio_direction_input(unsigned gpio);
439int gpio_direction_output(unsigned gpio, int value);
440
441#include <asm-generic/gpio.h> /* cansleep wrappers */
442#include <asm/irq.h>
443
444static inline int gpio_to_irq(unsigned gpio)
445{
446 return (gpio + GPIO_IRQ_BASE);
447}
448
449static inline int irq_to_gpio(unsigned irq)
450{
451 return (irq - GPIO_IRQ_BASE);
452}
453
454#endif /* __ASSEMBLY__ */
455
456#endif /* __ARCH_BLACKFIN_GPIO_H__ */
diff --git a/arch/blackfin/include/asm/gptimers.h b/arch/blackfin/include/asm/gptimers.h
new file mode 100644
index 000000000000..0520d2aac8f3
--- /dev/null
+++ b/arch/blackfin/include/asm/gptimers.h
@@ -0,0 +1,191 @@
1/*
2 * gptimers.h - Blackfin General Purpose Timer structs/defines/prototypes
3 *
4 * Copyright (c) 2005-2008 Analog Devices Inc.
5 * Copyright (C) 2005 John DeHority
6 * Copyright (C) 2006 Hella Aglaia GmbH (awe@aglaia-gmbh.de)
7 *
8 * Licensed under the GPL-2.
9 */
10
11#ifndef _BLACKFIN_TIMERS_H_
12#define _BLACKFIN_TIMERS_H_
13
14#include <linux/types.h>
15#include <asm/blackfin.h>
16
17/*
18 * BF537/BF527: 8 timers:
19 */
20#if defined(BF527_FAMILY) || defined(BF537_FAMILY)
21# define MAX_BLACKFIN_GPTIMERS 8
22# define TIMER0_GROUP_REG TIMER_ENABLE
23#endif
24/*
25 * BF54x: 11 timers (BF542: 8 timers):
26 */
27#if defined(BF548_FAMILY)
28# ifdef CONFIG_BF542
29# define MAX_BLACKFIN_GPTIMERS 8
30# else
31# define MAX_BLACKFIN_GPTIMERS 11
32# define TIMER8_GROUP_REG TIMER_ENABLE1
33# endif
34# define TIMER0_GROUP_REG TIMER_ENABLE0
35#endif
36/*
37 * BF561: 12 timers:
38 */
39#if defined(CONFIG_BF561)
40# define MAX_BLACKFIN_GPTIMERS 12
41# define TIMER0_GROUP_REG TMRS8_ENABLE
42# define TIMER8_GROUP_REG TMRS4_ENABLE
43#endif
44/*
45 * All others: 3 timers:
46 */
47#if !defined(MAX_BLACKFIN_GPTIMERS)
48# define MAX_BLACKFIN_GPTIMERS 3
49# define TIMER0_GROUP_REG TIMER_ENABLE
50#endif
51
52#define BLACKFIN_GPTIMER_IDMASK ((1UL << MAX_BLACKFIN_GPTIMERS) - 1)
53#define BFIN_TIMER_OCTET(x) ((x) >> 3)
54
55/* used in masks for timer_enable() and timer_disable() */
56#define TIMER0bit 0x0001 /* 0001b */
57#define TIMER1bit 0x0002 /* 0010b */
58#define TIMER2bit 0x0004 /* 0100b */
59#define TIMER3bit 0x0008
60#define TIMER4bit 0x0010
61#define TIMER5bit 0x0020
62#define TIMER6bit 0x0040
63#define TIMER7bit 0x0080
64#define TIMER8bit 0x0100
65#define TIMER9bit 0x0200
66#define TIMER10bit 0x0400
67#define TIMER11bit 0x0800
68
69#define TIMER0_id 0
70#define TIMER1_id 1
71#define TIMER2_id 2
72#define TIMER3_id 3
73#define TIMER4_id 4
74#define TIMER5_id 5
75#define TIMER6_id 6
76#define TIMER7_id 7
77#define TIMER8_id 8
78#define TIMER9_id 9
79#define TIMER10_id 10
80#define TIMER11_id 11
81
82/* associated timers for ppi framesync: */
83
84#if defined(CONFIG_BF561)
85# define FS0_1_TIMER_ID TIMER8_id
86# define FS0_2_TIMER_ID TIMER9_id
87# define FS1_1_TIMER_ID TIMER10_id
88# define FS1_2_TIMER_ID TIMER11_id
89# define FS0_1_TIMER_BIT TIMER8bit
90# define FS0_2_TIMER_BIT TIMER9bit
91# define FS1_1_TIMER_BIT TIMER10bit
92# define FS1_2_TIMER_BIT TIMER11bit
93# undef FS1_TIMER_ID
94# undef FS2_TIMER_ID
95# undef FS1_TIMER_BIT
96# undef FS2_TIMER_BIT
97#else
98# define FS1_TIMER_ID TIMER0_id
99# define FS2_TIMER_ID TIMER1_id
100# define FS1_TIMER_BIT TIMER0bit
101# define FS2_TIMER_BIT TIMER1bit
102#endif
103
104/*
105 * Timer Configuration Register Bits
106 */
107#define TIMER_ERR 0xC000
108#define TIMER_ERR_OVFL 0x4000
109#define TIMER_ERR_PROG_PER 0x8000
110#define TIMER_ERR_PROG_PW 0xC000
111#define TIMER_EMU_RUN 0x0200
112#define TIMER_TOGGLE_HI 0x0100
113#define TIMER_CLK_SEL 0x0080
114#define TIMER_OUT_DIS 0x0040
115#define TIMER_TIN_SEL 0x0020
116#define TIMER_IRQ_ENA 0x0010
117#define TIMER_PERIOD_CNT 0x0008
118#define TIMER_PULSE_HI 0x0004
119#define TIMER_MODE 0x0003
120#define TIMER_MODE_PWM 0x0001
121#define TIMER_MODE_WDTH 0x0002
122#define TIMER_MODE_EXT_CLK 0x0003
123
124/*
125 * Timer Status Register Bits
126 */
127#define TIMER_STATUS_TIMIL0 0x0001
128#define TIMER_STATUS_TIMIL1 0x0002
129#define TIMER_STATUS_TIMIL2 0x0004
130#define TIMER_STATUS_TIMIL3 0x00000008
131#define TIMER_STATUS_TIMIL4 0x00010000
132#define TIMER_STATUS_TIMIL5 0x00020000
133#define TIMER_STATUS_TIMIL6 0x00040000
134#define TIMER_STATUS_TIMIL7 0x00080000
135#define TIMER_STATUS_TIMIL8 0x0001
136#define TIMER_STATUS_TIMIL9 0x0002
137#define TIMER_STATUS_TIMIL10 0x0004
138#define TIMER_STATUS_TIMIL11 0x0008
139
140#define TIMER_STATUS_TOVF0 0x0010 /* timer 0 overflow error */
141#define TIMER_STATUS_TOVF1 0x0020
142#define TIMER_STATUS_TOVF2 0x0040
143#define TIMER_STATUS_TOVF3 0x00000080
144#define TIMER_STATUS_TOVF4 0x00100000
145#define TIMER_STATUS_TOVF5 0x00200000
146#define TIMER_STATUS_TOVF6 0x00400000
147#define TIMER_STATUS_TOVF7 0x00800000
148#define TIMER_STATUS_TOVF8 0x0010
149#define TIMER_STATUS_TOVF9 0x0020
150#define TIMER_STATUS_TOVF10 0x0040
151#define TIMER_STATUS_TOVF11 0x0080
152
153/*
154 * Timer Slave Enable Status : write 1 to clear
155 */
156#define TIMER_STATUS_TRUN0 0x1000
157#define TIMER_STATUS_TRUN1 0x2000
158#define TIMER_STATUS_TRUN2 0x4000
159#define TIMER_STATUS_TRUN3 0x00008000
160#define TIMER_STATUS_TRUN4 0x10000000
161#define TIMER_STATUS_TRUN5 0x20000000
162#define TIMER_STATUS_TRUN6 0x40000000
163#define TIMER_STATUS_TRUN7 0x80000000
164#define TIMER_STATUS_TRUN 0xF000F000
165#define TIMER_STATUS_TRUN8 0x1000
166#define TIMER_STATUS_TRUN9 0x2000
167#define TIMER_STATUS_TRUN10 0x4000
168#define TIMER_STATUS_TRUN11 0x8000
169
170/* The actual gptimer API */
171
172void set_gptimer_pwidth (int timer_id, uint32_t width);
173uint32_t get_gptimer_pwidth (int timer_id);
174void set_gptimer_period (int timer_id, uint32_t period);
175uint32_t get_gptimer_period (int timer_id);
176uint32_t get_gptimer_count (int timer_id);
177uint16_t get_gptimer_intr (int timer_id);
178void clear_gptimer_intr (int timer_id);
179uint16_t get_gptimer_over (int timer_id);
180void clear_gptimer_over (int timer_id);
181void set_gptimer_config (int timer_id, uint16_t config);
182uint16_t get_gptimer_config (int timer_id);
183void set_gptimer_pulse_hi (int timer_id);
184void clear_gptimer_pulse_hi(int timer_id);
185void enable_gptimers (uint16_t mask);
186void disable_gptimers (uint16_t mask);
187uint16_t get_enabled_gptimers (void);
188uint32_t get_gptimer_status (int group);
189void set_gptimer_status (int group, uint32_t value);
190
191#endif
diff --git a/arch/blackfin/include/asm/hardirq.h b/arch/blackfin/include/asm/hardirq.h
new file mode 100644
index 000000000000..b6b19f1b9dab
--- /dev/null
+++ b/arch/blackfin/include/asm/hardirq.h
@@ -0,0 +1,45 @@
1#ifndef __BFIN_HARDIRQ_H
2#define __BFIN_HARDIRQ_H
3
4#include <linux/cache.h>
5#include <linux/threads.h>
6#include <asm/irq.h>
7
8typedef struct {
9 unsigned int __softirq_pending;
10 unsigned int __syscall_count;
11 struct task_struct *__ksoftirqd_task;
12} ____cacheline_aligned irq_cpustat_t;
13
14#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */
15
16/*
17 * We put the hardirq and softirq counter into the preemption
18 * counter. The bitmask has the following meaning:
19 *
20 * - bits 0-7 are the preemption count (max preemption depth: 256)
21 * - bits 8-15 are the softirq count (max # of softirqs: 256)
22 * - bits 16-23 are the hardirq count (max # of hardirqs: 256)
23 *
24 * - ( bit 26 is the PREEMPT_ACTIVE flag. )
25 *
26 * PREEMPT_MASK: 0x000000ff
27 * HARDIRQ_MASK: 0x0000ff00
28 * SOFTIRQ_MASK: 0x00ff0000
29 */
30
31#if NR_IRQS > 256
32#define HARDIRQ_BITS 9
33#else
34#define HARDIRQ_BITS 8
35#endif
36
37#ifdef NR_IRQS
38# if (1 << HARDIRQ_BITS) < NR_IRQS
39# error HARDIRQ_BITS is too low!
40# endif
41#endif
42
43#define __ARCH_IRQ_EXIT_IRQS_DISABLED 1
44
45#endif
diff --git a/arch/blackfin/include/asm/hw_irq.h b/arch/blackfin/include/asm/hw_irq.h
new file mode 100644
index 000000000000..5b51eaec012c
--- /dev/null
+++ b/arch/blackfin/include/asm/hw_irq.h
@@ -0,0 +1,6 @@
1#ifndef __ASM_BFIN_HW_IRQ_H
2#define __ASM_BFIN_HW_IRQ_H
3
4/* Dummy include. */
5
6#endif
diff --git a/arch/blackfin/include/asm/io.h b/arch/blackfin/include/asm/io.h
new file mode 100644
index 000000000000..cbbf7ffdbbff
--- /dev/null
+++ b/arch/blackfin/include/asm/io.h
@@ -0,0 +1,212 @@
1#ifndef _BFIN_IO_H
2#define _BFIN_IO_H
3
4#ifdef __KERNEL__
5
6#ifndef __ASSEMBLY__
7#include <linux/types.h>
8#endif
9#include <linux/compiler.h>
10
11/*
12 * These are for ISA/PCI shared memory _only_ and should never be used
13 * on any other type of memory, including Zorro memory. They are meant to
14 * access the bus in the bus byte order which is little-endian!.
15 *
16 * readX/writeX() are used to access memory mapped devices. On some
17 * architectures the memory mapped IO stuff needs to be accessed
18 * differently. On the bfin architecture, we just read/write the
19 * memory location directly.
20 */
21#ifndef __ASSEMBLY__
22
23static inline unsigned char readb(const volatile void __iomem *addr)
24{
25 unsigned int val;
26 int tmp;
27
28 __asm__ __volatile__ ("cli %1;\n\t"
29 "NOP; NOP; SSYNC;\n\t"
30 "%0 = b [%2] (z);\n\t"
31 "sti %1;\n\t"
32 : "=d"(val), "=d"(tmp): "a"(addr)
33 );
34
35 return (unsigned char) val;
36}
37
38static inline unsigned short readw(const volatile void __iomem *addr)
39{
40 unsigned int val;
41 int tmp;
42
43 __asm__ __volatile__ ("cli %1;\n\t"
44 "NOP; NOP; SSYNC;\n\t"
45 "%0 = w [%2] (z);\n\t"
46 "sti %1;\n\t"
47 : "=d"(val), "=d"(tmp): "a"(addr)
48 );
49
50 return (unsigned short) val;
51}
52
53static inline unsigned int readl(const volatile void __iomem *addr)
54{
55 unsigned int val;
56 int tmp;
57
58 __asm__ __volatile__ ("cli %1;\n\t"
59 "NOP; NOP; SSYNC;\n\t"
60 "%0 = [%2];\n\t"
61 "sti %1;\n\t"
62 : "=d"(val), "=d"(tmp): "a"(addr)
63 );
64 return val;
65}
66
67#endif /* __ASSEMBLY__ */
68
69#define writeb(b,addr) (void)((*(volatile unsigned char *) (addr)) = (b))
70#define writew(b,addr) (void)((*(volatile unsigned short *) (addr)) = (b))
71#define writel(b,addr) (void)((*(volatile unsigned int *) (addr)) = (b))
72
73#define __raw_readb readb
74#define __raw_readw readw
75#define __raw_readl readl
76#define __raw_writeb writeb
77#define __raw_writew writew
78#define __raw_writel writel
79#define memset_io(a,b,c) memset((void *)(a),(b),(c))
80#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c))
81#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
82
83#define inb(addr) readb(addr)
84#define inw(addr) readw(addr)
85#define inl(addr) readl(addr)
86#define outb(x,addr) ((void) writeb(x,addr))
87#define outw(x,addr) ((void) writew(x,addr))
88#define outl(x,addr) ((void) writel(x,addr))
89
90#define inb_p(addr) inb(addr)
91#define inw_p(addr) inw(addr)
92#define inl_p(addr) inl(addr)
93#define outb_p(x,addr) outb(x,addr)
94#define outw_p(x,addr) outw(x,addr)
95#define outl_p(x,addr) outl(x,addr)
96
97#define ioread8_rep(a,d,c) insb(a,d,c)
98#define ioread16_rep(a,d,c) insw(a,d,c)
99#define ioread32_rep(a,d,c) insl(a,d,c)
100#define iowrite8_rep(a,s,c) outsb(a,s,c)
101#define iowrite16_rep(a,s,c) outsw(a,s,c)
102#define iowrite32_rep(a,s,c) outsl(a,s,c)
103
104#define ioread8(X) readb(X)
105#define ioread16(X) readw(X)
106#define ioread32(X) readl(X)
107#define iowrite8(val,X) writeb(val,X)
108#define iowrite16(val,X) writew(val,X)
109#define iowrite32(val,X) writel(val,X)
110
111#define IO_SPACE_LIMIT 0xffffffff
112
113/* Values for nocacheflag and cmode */
114#define IOMAP_NOCACHE_SER 1
115
116#ifndef __ASSEMBLY__
117
118extern void outsb(unsigned long port, const void *addr, unsigned long count);
119extern void outsw(unsigned long port, const void *addr, unsigned long count);
120extern void outsw_8(unsigned long port, const void *addr, unsigned long count);
121extern void outsl(unsigned long port, const void *addr, unsigned long count);
122
123extern void insb(unsigned long port, void *addr, unsigned long count);
124extern void insw(unsigned long port, void *addr, unsigned long count);
125extern void insw_8(unsigned long port, void *addr, unsigned long count);
126extern void insl(unsigned long port, void *addr, unsigned long count);
127extern void insl_16(unsigned long port, void *addr, unsigned long count);
128
129extern void dma_outsb(unsigned long port, const void *addr, unsigned short count);
130extern void dma_outsw(unsigned long port, const void *addr, unsigned short count);
131extern void dma_outsl(unsigned long port, const void *addr, unsigned short count);
132
133extern void dma_insb(unsigned long port, void *addr, unsigned short count);
134extern void dma_insw(unsigned long port, void *addr, unsigned short count);
135extern void dma_insl(unsigned long port, void *addr, unsigned short count);
136
137/*
138 * Map some physical address range into the kernel address space.
139 */
140static inline void __iomem *__ioremap(unsigned long physaddr, unsigned long size,
141 int cacheflag)
142{
143 return (void __iomem *)physaddr;
144}
145
146/*
147 * Unmap a ioremap()ed region again
148 */
149static inline void iounmap(void *addr)
150{
151}
152
153/*
154 * __iounmap unmaps nearly everything, so be careful
155 * it doesn't free currently pointer/page tables anymore but it
156 * wans't used anyway and might be added later.
157 */
158static inline void __iounmap(void *addr, unsigned long size)
159{
160}
161
162/*
163 * Set new cache mode for some kernel address space.
164 * The caller must push data for that range itself, if such data may already
165 * be in the cache.
166 */
167static inline void kernel_set_cachemode(void *addr, unsigned long size,
168 int cmode)
169{
170}
171
172static inline void __iomem *ioremap(unsigned long physaddr, unsigned long size)
173{
174 return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
175}
176static inline void __iomem *ioremap_nocache(unsigned long physaddr,
177 unsigned long size)
178{
179 return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
180}
181
182extern void blkfin_inv_cache_all(void);
183
184#endif
185
186#define ioport_map(port, nr) ((void __iomem*)(port))
187#define ioport_unmap(addr)
188
189/* Pages to physical address... */
190#define page_to_phys(page) ((page - mem_map) << PAGE_SHIFT)
191#define page_to_bus(page) ((page - mem_map) << PAGE_SHIFT)
192
193#define phys_to_virt(vaddr) ((void *) (vaddr))
194#define virt_to_phys(vaddr) ((unsigned long) (vaddr))
195
196#define virt_to_bus virt_to_phys
197#define bus_to_virt phys_to_virt
198
199/*
200 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
201 * access
202 */
203#define xlate_dev_mem_ptr(p) __va(p)
204
205/*
206 * Convert a virtual cached pointer to an uncached pointer
207 */
208#define xlate_dev_kmem_ptr(p) p
209
210#endif /* __KERNEL__ */
211
212#endif /* _BFIN_IO_H */
diff --git a/arch/blackfin/include/asm/ioctl.h b/arch/blackfin/include/asm/ioctl.h
new file mode 100644
index 000000000000..b279fe06dfe5
--- /dev/null
+++ b/arch/blackfin/include/asm/ioctl.h
@@ -0,0 +1 @@
#include <asm-generic/ioctl.h>
diff --git a/arch/blackfin/include/asm/ioctls.h b/arch/blackfin/include/asm/ioctls.h
new file mode 100644
index 000000000000..895e3173165d
--- /dev/null
+++ b/arch/blackfin/include/asm/ioctls.h
@@ -0,0 +1,87 @@
1#ifndef __ARCH_BFIN_IOCTLS_H__
2#define __ARCH_BFIN_IOCTLS_H__
3
4#include <asm/ioctl.h>
5
6/* 0x54 is just a magic number to make these relatively unique ('T') */
7
8#define TCGETS 0x5401
9#define TCSETS 0x5402
10#define TCSETSW 0x5403
11#define TCSETSF 0x5404
12#define TCGETA 0x5405
13#define TCSETA 0x5406
14#define TCSETAW 0x5407
15#define TCSETAF 0x5408
16#define TCSBRK 0x5409
17#define TCXONC 0x540A
18#define TCFLSH 0x540B
19#define TIOCEXCL 0x540C
20#define TIOCNXCL 0x540D
21#define TIOCSCTTY 0x540E
22#define TIOCGPGRP 0x540F
23#define TIOCSPGRP 0x5410
24#define TIOCOUTQ 0x5411
25#define TIOCSTI 0x5412
26#define TIOCGWINSZ 0x5413
27#define TIOCSWINSZ 0x5414
28#define TIOCMGET 0x5415
29#define TIOCMBIS 0x5416
30#define TIOCMBIC 0x5417
31#define TIOCMSET 0x5418
32#define TIOCGSOFTCAR 0x5419
33#define TIOCSSOFTCAR 0x541A
34#define FIONREAD 0x541B
35#define TIOCINQ FIONREAD
36#define TIOCLINUX 0x541C
37#define TIOCCONS 0x541D
38#define TIOCGSERIAL 0x541E
39#define TIOCSSERIAL 0x541F
40#define TIOCPKT 0x5420
41#define FIONBIO 0x5421
42#define TIOCNOTTY 0x5422
43#define TIOCSETD 0x5423
44#define TIOCGETD 0x5424
45#define TCSBRKP 0x5425 /* Needed for POSIX tcsendbreak() */
46#define TIOCTTYGSTRUCT 0x5426 /* For debugging only */
47#define TIOCSBRK 0x5427 /* BSD compatibility */
48#define TIOCCBRK 0x5428 /* BSD compatibility */
49#define TIOCGSID 0x5429 /* Return the session ID of FD */
50#define TCGETS2 _IOR('T', 0x2A, struct termios2)
51#define TCSETS2 _IOW('T', 0x2B, struct termios2)
52#define TCSETSW2 _IOW('T', 0x2C, struct termios2)
53#define TCSETSF2 _IOW('T', 0x2D, struct termios2)
54/* Get Pty Number (of pty-mux device) */
55#define TIOCGPTN _IOR('T', 0x30, unsigned int)
56#define TIOCSPTLCK _IOW('T', 0x31, int) /* Lock/unlock Pty */
57
58#define FIONCLEX 0x5450 /* these numbers need to be adjusted. */
59#define FIOCLEX 0x5451
60#define FIOASYNC 0x5452
61#define TIOCSERCONFIG 0x5453
62#define TIOCSERGWILD 0x5454
63#define TIOCSERSWILD 0x5455
64#define TIOCGLCKTRMIOS 0x5456
65#define TIOCSLCKTRMIOS 0x5457
66#define TIOCSERGSTRUCT 0x5458 /* For debugging only */
67#define TIOCSERGETLSR 0x5459 /* Get line status register */
68#define TIOCSERGETMULTI 0x545A /* Get multiport config */
69#define TIOCSERSETMULTI 0x545B /* Set multiport config */
70
71#define TIOCMIWAIT 0x545C /* wait for a change on serial input line(s) */
72#define TIOCGICOUNT 0x545D /* read serial port inline interrupt counts */
73
74#define FIOQSIZE 0x545E
75
76/* Used for packet mode */
77#define TIOCPKT_DATA 0
78#define TIOCPKT_FLUSHREAD 1
79#define TIOCPKT_FLUSHWRITE 2
80#define TIOCPKT_STOP 4
81#define TIOCPKT_START 8
82#define TIOCPKT_NOSTOP 16
83#define TIOCPKT_DOSTOP 32
84
85#define TIOCSER_TEMT 0x01 /* Transmitter physically empty */
86
87#endif /* __ARCH_BFIN_IOCTLS_H__ */
diff --git a/arch/blackfin/include/asm/ipcbuf.h b/arch/blackfin/include/asm/ipcbuf.h
new file mode 100644
index 000000000000..8f0899cdf4d2
--- /dev/null
+++ b/arch/blackfin/include/asm/ipcbuf.h
@@ -0,0 +1,30 @@
1/* Changes origined from m68k version. Lineo Inc. May 2001 */
2
3#ifndef __BFIN_IPCBUF_H__
4#define __BFIN_IPCBUF_H__
5
6/*
7 * The user_ipc_perm structure for m68k architecture.
8 * Note extra padding because this structure is passed back and forth
9 * between kernel and user space.
10 *
11 * Pad space is left for:
12 * - 32-bit mode_t and seq
13 * - 2 miscellaneous 32-bit values
14 */
15
16struct ipc64_perm {
17 __kernel_key_t key;
18 __kernel_uid32_t uid;
19 __kernel_gid32_t gid;
20 __kernel_uid32_t cuid;
21 __kernel_gid32_t cgid;
22 __kernel_mode_t mode;
23 unsigned short __pad1;
24 unsigned short seq;
25 unsigned short __pad2;
26 unsigned long __unused1;
27 unsigned long __unused2;
28};
29
30#endif /* __BFIN_IPCBUF_H__ */
diff --git a/arch/blackfin/include/asm/irq.h b/arch/blackfin/include/asm/irq.h
new file mode 100644
index 000000000000..89f59e18af93
--- /dev/null
+++ b/arch/blackfin/include/asm/irq.h
@@ -0,0 +1,72 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file COPYING in the main directory of this archive
4 * for more details.
5 *
6 * Changed by HuTao Apr18, 2003
7 *
8 * Copyright was missing when I got the code so took from MIPS arch ...MaTed---
9 * Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle
10 * Copyright (C) 1995, 96, 97, 98, 99, 2000, 2001 by Ralf Baechle
11 *
12 * Adapted for BlackFin (ADI) by Ted Ma <mated@sympatico.ca>
13 * Copyright (c) 2002 Arcturus Networks Inc. (www.arcturusnetworks.com)
14 * Copyright (c) 2002 Lineo, Inc. <mattw@lineo.com>
15 */
16
17#ifndef _BFIN_IRQ_H_
18#define _BFIN_IRQ_H_
19
20#include <mach/irq.h>
21#include <asm/ptrace.h>
22
23/*******************************************************************************
24 ***** INTRODUCTION ***********
25 * On the Blackfin, the interrupt structure allows remmapping of the hardware
26 * levels.
27 * - I'm going to assume that the H/W level is going to stay at the default
28 * settings. If someone wants to go through and abstart this out, feel free
29 * to mod the interrupt numbering scheme.
30 * - I'm abstracting the interrupts so that uClinux does not know anything
31 * about the H/W levels. If you want to change the H/W AND keep the abstracted
32 * levels that uClinux sees, you should be able to do most of it here.
33 * - I've left the "abstract" numbering sparce in case someone wants to pull the
34 * interrupts apart (just the TX/RX for the various devices)
35 *******************************************************************************/
36
37/* SYS_IRQS and NR_IRQS are defined in <mach-bf5xx/irq.h>*/
38
39/*
40 * Machine specific interrupt sources.
41 *
42 * Adding an interrupt service routine for a source with this bit
43 * set indicates a special machine specific interrupt source.
44 * The machine specific files define these sources.
45 *
46 * The IRQ_MACHSPEC bit is now gone - the only thing it did was to
47 * introduce unnecessary overhead.
48 *
49 * All interrupt handling is actually machine specific so it is better
50 * to use function pointers, as used by the Sparc port, and select the
51 * interrupt handling functions when initializing the kernel. This way
52 * we save some unnecessary overhead at run-time.
53 * 01/11/97 - Jes
54 */
55
56extern void ack_bad_irq(unsigned int irq);
57
58static __inline__ int irq_canonicalize(int irq)
59{
60 return irq;
61}
62
63/* count of spurious interrupts */
64/* extern volatile unsigned int num_spurious; */
65
66#ifndef NO_IRQ
67#define NO_IRQ ((unsigned int)(-1))
68#endif
69
70#define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
71
72#endif /* _BFIN_IRQ_H_ */
diff --git a/arch/blackfin/include/asm/irq_handler.h b/arch/blackfin/include/asm/irq_handler.h
new file mode 100644
index 000000000000..139b5208f9d8
--- /dev/null
+++ b/arch/blackfin/include/asm/irq_handler.h
@@ -0,0 +1,33 @@
1#ifndef _IRQ_HANDLER_H
2#define _IRQ_HANDLER_H
3
4#include <linux/types.h>
5#include <linux/linkage.h>
6
7/* BASE LEVEL interrupt handler routines */
8asmlinkage void evt_exception(void);
9asmlinkage void trap(void);
10asmlinkage void evt_ivhw(void);
11asmlinkage void evt_timer(void);
12asmlinkage void evt_nmi(void);
13asmlinkage void evt_evt7(void);
14asmlinkage void evt_evt8(void);
15asmlinkage void evt_evt9(void);
16asmlinkage void evt_evt10(void);
17asmlinkage void evt_evt11(void);
18asmlinkage void evt_evt12(void);
19asmlinkage void evt_evt13(void);
20asmlinkage void evt_soft_int1(void);
21asmlinkage void evt_system_call(void);
22asmlinkage void init_exception_buff(void);
23asmlinkage void trap_c(struct pt_regs *fp);
24asmlinkage void ex_replaceable(void);
25asmlinkage void early_trap(void);
26
27extern void *ex_table[];
28extern void return_from_exception(void);
29
30extern int bfin_request_exception(unsigned int exception, void (*handler)(void));
31extern int bfin_free_exception(unsigned int exception, void (*handler)(void));
32
33#endif
diff --git a/arch/blackfin/include/asm/irq_regs.h b/arch/blackfin/include/asm/irq_regs.h
new file mode 100644
index 000000000000..3dd9c0b70270
--- /dev/null
+++ b/arch/blackfin/include/asm/irq_regs.h
@@ -0,0 +1 @@
#include <asm-generic/irq_regs.h>
diff --git a/arch/blackfin/include/asm/kdebug.h b/arch/blackfin/include/asm/kdebug.h
new file mode 100644
index 000000000000..6ece1b037665
--- /dev/null
+++ b/arch/blackfin/include/asm/kdebug.h
@@ -0,0 +1 @@
#include <asm-generic/kdebug.h>
diff --git a/arch/blackfin/include/asm/kgdb.h b/arch/blackfin/include/asm/kgdb.h
new file mode 100644
index 000000000000..0f73847fd6bc
--- /dev/null
+++ b/arch/blackfin/include/asm/kgdb.h
@@ -0,0 +1,184 @@
1/*
2 * File: include/asm-blackfin/kgdb.h
3 * Based on:
4 * Author: Sonic Zhang
5 *
6 * Created:
7 * Description:
8 *
9 * Rev: $Id: kgdb_bfin_linux-2.6.x.patch 4934 2007-02-13 09:32:11Z sonicz $
10 *
11 * Modified:
12 * Copyright 2005-2006 Analog Devices Inc.
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, see the file COPYING, or write
28 * to the Free Software Foundation, Inc.,
29 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
30 */
31
32#ifndef __ASM_BLACKFIN_KGDB_H__
33#define __ASM_BLACKFIN_KGDB_H__
34
35#include <linux/ptrace.h>
36
37/* gdb locks */
38#define KGDB_MAX_NO_CPUS 8
39
40/************************************************************************/
41/* BUFMAX defines the maximum number of characters in inbound/outbound buffers*/
42/* at least NUMREGBYTES*2 are needed for register packets */
43/* Longer buffer is needed to list all threads */
44#define BUFMAX 2048
45
46/*
47 * Note that this register image is different from
48 * the register image that Linux produces at interrupt time.
49 *
50 * Linux's register image is defined by struct pt_regs in ptrace.h.
51 */
52enum regnames {
53 /* Core Registers */
54 BFIN_R0 = 0,
55 BFIN_R1,
56 BFIN_R2,
57 BFIN_R3,
58 BFIN_R4,
59 BFIN_R5,
60 BFIN_R6,
61 BFIN_R7,
62 BFIN_P0,
63 BFIN_P1,
64 BFIN_P2,
65 BFIN_P3,
66 BFIN_P4,
67 BFIN_P5,
68 BFIN_SP,
69 BFIN_FP,
70 BFIN_I0,
71 BFIN_I1,
72 BFIN_I2,
73 BFIN_I3,
74 BFIN_M0,
75 BFIN_M1,
76 BFIN_M2,
77 BFIN_M3,
78 BFIN_B0,
79 BFIN_B1,
80 BFIN_B2,
81 BFIN_B3,
82 BFIN_L0,
83 BFIN_L1,
84 BFIN_L2,
85 BFIN_L3,
86 BFIN_A0_DOT_X,
87 BFIN_A0_DOT_W,
88 BFIN_A1_DOT_X,
89 BFIN_A1_DOT_W,
90 BFIN_ASTAT,
91 BFIN_RETS,
92 BFIN_LC0,
93 BFIN_LT0,
94 BFIN_LB0,
95 BFIN_LC1,
96 BFIN_LT1,
97 BFIN_LB1,
98 BFIN_CYCLES,
99 BFIN_CYCLES2,
100 BFIN_USP,
101 BFIN_SEQSTAT,
102 BFIN_SYSCFG,
103 BFIN_RETI,
104 BFIN_RETX,
105 BFIN_RETN,
106 BFIN_RETE,
107
108 /* Pseudo Registers */
109 BFIN_PC,
110 BFIN_CC,
111 BFIN_EXTRA1, /* Address of .text section. */
112 BFIN_EXTRA2, /* Address of .data section. */
113 BFIN_EXTRA3, /* Address of .bss section. */
114 BFIN_FDPIC_EXEC,
115 BFIN_FDPIC_INTERP,
116
117 /* MMRs */
118 BFIN_IPEND,
119
120 /* LAST ENTRY SHOULD NOT BE CHANGED. */
121 BFIN_NUM_REGS /* The number of all registers. */
122};
123
124/* Number of bytes of registers. */
125#define NUMREGBYTES BFIN_NUM_REGS*4
126
127#define BREAKPOINT() asm(" EXCPT 2;");
128#define BREAK_INSTR_SIZE 2
129#define HW_BREAKPOINT_NUM 6
130
131/* Instruction watchpoint address control register bits mask */
132#define WPPWR 0x1
133#define WPIREN01 0x2
134#define WPIRINV01 0x4
135#define WPIAEN0 0x8
136#define WPIAEN1 0x10
137#define WPICNTEN0 0x20
138#define WPICNTEN1 0x40
139#define EMUSW0 0x80
140#define EMUSW1 0x100
141#define WPIREN23 0x200
142#define WPIRINV23 0x400
143#define WPIAEN2 0x800
144#define WPIAEN3 0x1000
145#define WPICNTEN2 0x2000
146#define WPICNTEN3 0x4000
147#define EMUSW2 0x8000
148#define EMUSW3 0x10000
149#define WPIREN45 0x20000
150#define WPIRINV45 0x40000
151#define WPIAEN4 0x80000
152#define WPIAEN5 0x100000
153#define WPICNTEN4 0x200000
154#define WPICNTEN5 0x400000
155#define EMUSW4 0x800000
156#define EMUSW5 0x1000000
157#define WPAND 0x2000000
158
159/* Data watchpoint address control register bits mask */
160#define WPDREN01 0x1
161#define WPDRINV01 0x2
162#define WPDAEN0 0x4
163#define WPDAEN1 0x8
164#define WPDCNTEN0 0x10
165#define WPDCNTEN1 0x20
166#define WPDSRC0 0xc0
167#define WPDACC0 0x300
168#define WPDSRC1 0xc00
169#define WPDACC1 0x3000
170
171/* Watchpoint status register bits mask */
172#define STATIA0 0x1
173#define STATIA1 0x2
174#define STATIA2 0x4
175#define STATIA3 0x8
176#define STATIA4 0x10
177#define STATIA5 0x20
178#define STATDA0 0x40
179#define STATDA1 0x80
180
181extern void kgdb_print(const char *fmt, ...);
182extern void init_kgdb_uart(void);
183
184#endif
diff --git a/arch/blackfin/include/asm/kmap_types.h b/arch/blackfin/include/asm/kmap_types.h
new file mode 100644
index 000000000000..e215f7104974
--- /dev/null
+++ b/arch/blackfin/include/asm/kmap_types.h
@@ -0,0 +1,21 @@
1#ifndef _ASM_KMAP_TYPES_H
2#define _ASM_KMAP_TYPES_H
3
4enum km_type {
5 KM_BOUNCE_READ,
6 KM_SKB_SUNRPC_DATA,
7 KM_SKB_DATA_SOFTIRQ,
8 KM_USER0,
9 KM_USER1,
10 KM_BIO_SRC_IRQ,
11 KM_BIO_DST_IRQ,
12 KM_PTE0,
13 KM_PTE1,
14 KM_IRQ0,
15 KM_IRQ1,
16 KM_SOFTIRQ0,
17 KM_SOFTIRQ1,
18 KM_TYPE_NR
19};
20
21#endif
diff --git a/arch/blackfin/include/asm/l1layout.h b/arch/blackfin/include/asm/l1layout.h
new file mode 100644
index 000000000000..c13ded777828
--- /dev/null
+++ b/arch/blackfin/include/asm/l1layout.h
@@ -0,0 +1,31 @@
1/*
2 * l1layout.h
3 * Defines a layout of L1 scratchpad memory that userspace can rely on.
4 */
5
6#ifndef _L1LAYOUT_H_
7#define _L1LAYOUT_H_
8
9#include <asm/blackfin.h>
10
11#ifndef __ASSEMBLY__
12
13/* Data that is "mapped" into the process VM at the start of the L1 scratch
14 memory, so that each process can access it at a fixed address. Used for
15 stack checking. */
16struct l1_scratch_task_info
17{
18 /* Points to the start of the stack. */
19 void *stack_start;
20 /* Not updated by the kernel; a user process can modify this to
21 keep track of the lowest address of the stack pointer during its
22 runtime. */
23 void *lowest_sp;
24};
25
26/* A pointer to the structure in memory. */
27#define L1_SCRATCH_TASK_INFO ((struct l1_scratch_task_info *)L1_SCRATCH_START)
28
29#endif
30
31#endif
diff --git a/arch/blackfin/include/asm/linkage.h b/arch/blackfin/include/asm/linkage.h
new file mode 100644
index 000000000000..5a822bb790f7
--- /dev/null
+++ b/arch/blackfin/include/asm/linkage.h
@@ -0,0 +1,7 @@
1#ifndef __ASM_LINKAGE_H
2#define __ASM_LINKAGE_H
3
4#define __ALIGN .align 4
5#define __ALIGN_STR ".align 4"
6
7#endif
diff --git a/arch/blackfin/include/asm/local.h b/arch/blackfin/include/asm/local.h
new file mode 100644
index 000000000000..75afffbc6421
--- /dev/null
+++ b/arch/blackfin/include/asm/local.h
@@ -0,0 +1,6 @@
1#ifndef __BLACKFIN_LOCAL_H
2#define __BLACKFIN_LOCAL_H
3
4#include <asm-generic/local.h>
5
6#endif /* __BLACKFIN_LOCAL_H */
diff --git a/arch/blackfin/include/asm/mem_map.h b/arch/blackfin/include/asm/mem_map.h
new file mode 100644
index 000000000000..88d04a707708
--- /dev/null
+++ b/arch/blackfin/include/asm/mem_map.h
@@ -0,0 +1,12 @@
1/*
2 * mem_map.h
3 * Common header file for blackfin family of processors.
4 *
5 */
6
7#ifndef _MEM_MAP_H_
8#define _MEM_MAP_H_
9
10#include <mach/mem_map.h>
11
12#endif /* _MEM_MAP_H_ */
diff --git a/arch/blackfin/include/asm/mman.h b/arch/blackfin/include/asm/mman.h
new file mode 100644
index 000000000000..b58f5ad3f024
--- /dev/null
+++ b/arch/blackfin/include/asm/mman.h
@@ -0,0 +1,43 @@
1#ifndef __BFIN_MMAN_H__
2#define __BFIN_MMAN_H__
3
4#define PROT_READ 0x1 /* page can be read */
5#define PROT_WRITE 0x2 /* page can be written */
6#define PROT_EXEC 0x4 /* page can be executed */
7#define PROT_SEM 0x8 /* page may be used for atomic ops */
8#define PROT_NONE 0x0 /* page can not be accessed */
9#define PROT_GROWSDOWN 0x01000000 /* mprotect flag: extend change to start of growsdown vma */
10#define PROT_GROWSUP 0x02000000 /* mprotect flag: extend change to end of growsup vma */
11
12#define MAP_SHARED 0x01 /* Share changes */
13#define MAP_PRIVATE 0x02 /* Changes are private */
14#define MAP_TYPE 0x0f /* Mask for type of mapping */
15#define MAP_FIXED 0x10 /* Interpret addr exactly */
16#define MAP_ANONYMOUS 0x20 /* don't use a file */
17
18#define MAP_GROWSDOWN 0x0100 /* stack-like segment */
19#define MAP_DENYWRITE 0x0800 /* ETXTBSY */
20#define MAP_EXECUTABLE 0x1000 /* mark it as an executable */
21#define MAP_LOCKED 0x2000 /* pages are locked */
22#define MAP_NORESERVE 0x4000 /* don't check for reservations */
23#define MAP_POPULATE 0x8000 /* populate (prefault) pagetables */
24#define MAP_NONBLOCK 0x10000 /* do not block on IO */
25
26#define MS_ASYNC 1 /* sync memory asynchronously */
27#define MS_INVALIDATE 2 /* invalidate the caches */
28#define MS_SYNC 4 /* synchronous memory sync */
29
30#define MCL_CURRENT 1 /* lock all current mappings */
31#define MCL_FUTURE 2 /* lock all future mappings */
32
33#define MADV_NORMAL 0x0 /* default page-in behavior */
34#define MADV_RANDOM 0x1 /* page-in minimum required */
35#define MADV_SEQUENTIAL 0x2 /* read-ahead aggressively */
36#define MADV_WILLNEED 0x3 /* pre-fault pages */
37#define MADV_DONTNEED 0x4 /* discard these pages */
38
39/* compatibility flags */
40#define MAP_ANON MAP_ANONYMOUS
41#define MAP_FILE 0
42
43#endif /* __BFIN_MMAN_H__ */
diff --git a/arch/blackfin/include/asm/mmu.h b/arch/blackfin/include/asm/mmu.h
new file mode 100644
index 000000000000..757e43906ed4
--- /dev/null
+++ b/arch/blackfin/include/asm/mmu.h
@@ -0,0 +1,32 @@
1#ifndef __MMU_H
2#define __MMU_H
3
4/* Copyright (C) 2002, David McCullough <davidm@snapgear.com> */
5
6struct sram_list_struct {
7 struct sram_list_struct *next;
8 void *addr;
9 size_t length;
10};
11
12typedef struct {
13 struct vm_list_struct *vmlist;
14 unsigned long end_brk;
15 unsigned long stack_start;
16
17 /* Points to the location in SDRAM where the L1 stack is normally
18 saved, or NULL if the stack is always in SDRAM. */
19 void *l1_stack_save;
20
21 struct sram_list_struct *sram_list;
22
23#ifdef CONFIG_BINFMT_ELF_FDPIC
24 unsigned long exec_fdpic_loadmap;
25 unsigned long interp_fdpic_loadmap;
26#endif
27#ifdef CONFIG_MPU
28 unsigned long *page_rwx_mask;
29#endif
30} mm_context_t;
31
32#endif
diff --git a/arch/blackfin/include/asm/mmu_context.h b/arch/blackfin/include/asm/mmu_context.h
new file mode 100644
index 000000000000..8529552a981f
--- /dev/null
+++ b/arch/blackfin/include/asm/mmu_context.h
@@ -0,0 +1,183 @@
1/*
2 * File: include/asm-blackfin/mmu_context.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#ifndef __BLACKFIN_MMU_CONTEXT_H__
31#define __BLACKFIN_MMU_CONTEXT_H__
32
33#include <linux/gfp.h>
34#include <linux/sched.h>
35#include <asm/setup.h>
36#include <asm/page.h>
37#include <asm/pgalloc.h>
38#include <asm/cplbinit.h>
39
40extern void *current_l1_stack_save;
41extern int nr_l1stack_tasks;
42extern void *l1_stack_base;
43extern unsigned long l1_stack_len;
44
45extern int l1sram_free(const void*);
46extern void *l1sram_alloc_max(void*);
47
48static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
49{
50}
51
52/* Called when creating a new context during fork() or execve(). */
53static inline int
54init_new_context(struct task_struct *tsk, struct mm_struct *mm)
55{
56#ifdef CONFIG_MPU
57 unsigned long p = __get_free_pages(GFP_KERNEL, page_mask_order);
58 mm->context.page_rwx_mask = (unsigned long *)p;
59 memset(mm->context.page_rwx_mask, 0,
60 page_mask_nelts * 3 * sizeof(long));
61#endif
62 return 0;
63}
64
65static inline void free_l1stack(void)
66{
67 nr_l1stack_tasks--;
68 if (nr_l1stack_tasks == 0)
69 l1sram_free(l1_stack_base);
70}
71static inline void destroy_context(struct mm_struct *mm)
72{
73 struct sram_list_struct *tmp;
74
75 if (current_l1_stack_save == mm->context.l1_stack_save)
76 current_l1_stack_save = NULL;
77 if (mm->context.l1_stack_save)
78 free_l1stack();
79
80 while ((tmp = mm->context.sram_list)) {
81 mm->context.sram_list = tmp->next;
82 sram_free(tmp->addr);
83 kfree(tmp);
84 }
85#ifdef CONFIG_MPU
86 if (current_rwx_mask == mm->context.page_rwx_mask)
87 current_rwx_mask = NULL;
88 free_pages((unsigned long)mm->context.page_rwx_mask, page_mask_order);
89#endif
90}
91
92static inline unsigned long
93alloc_l1stack(unsigned long length, unsigned long *stack_base)
94{
95 if (nr_l1stack_tasks == 0) {
96 l1_stack_base = l1sram_alloc_max(&l1_stack_len);
97 if (!l1_stack_base)
98 return 0;
99 }
100
101 if (l1_stack_len < length) {
102 if (nr_l1stack_tasks == 0)
103 l1sram_free(l1_stack_base);
104 return 0;
105 }
106 *stack_base = (unsigned long)l1_stack_base;
107 nr_l1stack_tasks++;
108 return l1_stack_len;
109}
110
111static inline int
112activate_l1stack(struct mm_struct *mm, unsigned long sp_base)
113{
114 if (current_l1_stack_save)
115 memcpy(current_l1_stack_save, l1_stack_base, l1_stack_len);
116 mm->context.l1_stack_save = current_l1_stack_save = (void*)sp_base;
117 memcpy(l1_stack_base, current_l1_stack_save, l1_stack_len);
118 return 1;
119}
120
121#define deactivate_mm(tsk,mm) do { } while (0)
122
123#define activate_mm(prev, next) switch_mm(prev, next, NULL)
124
125static inline void switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm,
126 struct task_struct *tsk)
127{
128 if (prev_mm == next_mm)
129 return;
130#ifdef CONFIG_MPU
131 if (prev_mm->context.page_rwx_mask == current_rwx_mask) {
132 flush_switched_cplbs();
133 set_mask_dcplbs(next_mm->context.page_rwx_mask);
134 }
135#endif
136
137 /* L1 stack switching. */
138 if (!next_mm->context.l1_stack_save)
139 return;
140 if (next_mm->context.l1_stack_save == current_l1_stack_save)
141 return;
142 if (current_l1_stack_save) {
143 memcpy(current_l1_stack_save, l1_stack_base, l1_stack_len);
144 }
145 current_l1_stack_save = next_mm->context.l1_stack_save;
146 memcpy(l1_stack_base, current_l1_stack_save, l1_stack_len);
147}
148
149#ifdef CONFIG_MPU
150static inline void protect_page(struct mm_struct *mm, unsigned long addr,
151 unsigned long flags)
152{
153 unsigned long *mask = mm->context.page_rwx_mask;
154 unsigned long page = addr >> 12;
155 unsigned long idx = page >> 5;
156 unsigned long bit = 1 << (page & 31);
157
158 if (flags & VM_MAYREAD)
159 mask[idx] |= bit;
160 else
161 mask[idx] &= ~bit;
162 mask += page_mask_nelts;
163 if (flags & VM_MAYWRITE)
164 mask[idx] |= bit;
165 else
166 mask[idx] &= ~bit;
167 mask += page_mask_nelts;
168 if (flags & VM_MAYEXEC)
169 mask[idx] |= bit;
170 else
171 mask[idx] &= ~bit;
172}
173
174static inline void update_protections(struct mm_struct *mm)
175{
176 if (mm->context.page_rwx_mask == current_rwx_mask) {
177 flush_switched_cplbs();
178 set_mask_dcplbs(mm->context.page_rwx_mask);
179 }
180}
181#endif
182
183#endif
diff --git a/arch/blackfin/include/asm/module.h b/arch/blackfin/include/asm/module.h
new file mode 100644
index 000000000000..e3128df139d6
--- /dev/null
+++ b/arch/blackfin/include/asm/module.h
@@ -0,0 +1,20 @@
1#ifndef _ASM_BFIN_MODULE_H
2#define _ASM_BFIN_MODULE_H
3
4#define MODULE_SYMBOL_PREFIX "_"
5
6#define Elf_Shdr Elf32_Shdr
7#define Elf_Sym Elf32_Sym
8#define Elf_Ehdr Elf32_Ehdr
9
10struct mod_arch_specific {
11 Elf_Shdr *text_l1;
12 Elf_Shdr *data_a_l1;
13 Elf_Shdr *bss_a_l1;
14 Elf_Shdr *data_b_l1;
15 Elf_Shdr *bss_b_l1;
16 Elf_Shdr *text_l2;
17 Elf_Shdr *data_l2;
18 Elf_Shdr *bss_l2;
19};
20#endif /* _ASM_BFIN_MODULE_H */
diff --git a/arch/blackfin/include/asm/msgbuf.h b/arch/blackfin/include/asm/msgbuf.h
new file mode 100644
index 000000000000..6fcbe8cd801d
--- /dev/null
+++ b/arch/blackfin/include/asm/msgbuf.h
@@ -0,0 +1,31 @@
1#ifndef _BFIN_MSGBUF_H
2#define _BFIN_MSGBUF_H
3
4/*
5 * The msqid64_ds structure for bfin architecture.
6 * Note extra padding because this structure is passed back and forth
7 * between kernel and user space.
8 *
9 * Pad space is left for:
10 * - 64-bit time_t to solve y2038 problem
11 * - 2 miscellaneous 32-bit values
12 */
13
14struct msqid64_ds {
15 struct ipc64_perm msg_perm;
16 __kernel_time_t msg_stime; /* last msgsnd time */
17 unsigned long __unused1;
18 __kernel_time_t msg_rtime; /* last msgrcv time */
19 unsigned long __unused2;
20 __kernel_time_t msg_ctime; /* last change time */
21 unsigned long __unused3;
22 unsigned long msg_cbytes; /* current number of bytes on queue */
23 unsigned long msg_qnum; /* number of messages in queue */
24 unsigned long msg_qbytes; /* max number of bytes on queue */
25 __kernel_pid_t msg_lspid; /* pid of last msgsnd */
26 __kernel_pid_t msg_lrpid; /* last receive pid */
27 unsigned long __unused4;
28 unsigned long __unused5;
29};
30
31#endif /* _BFIN_MSGBUF_H */
diff --git a/arch/blackfin/include/asm/mutex.h b/arch/blackfin/include/asm/mutex.h
new file mode 100644
index 000000000000..458c1f7fbc18
--- /dev/null
+++ b/arch/blackfin/include/asm/mutex.h
@@ -0,0 +1,9 @@
1/*
2 * Pull in the generic implementation for the mutex fastpath.
3 *
4 * TODO: implement optimized primitives instead, or leave the generic
5 * implementation in place, or pick the atomic_xchg() based generic
6 * implementation. (see asm-generic/mutex-xchg.h for details)
7 */
8
9#include <asm-generic/mutex-dec.h>
diff --git a/arch/blackfin/include/asm/nand.h b/arch/blackfin/include/asm/nand.h
new file mode 100644
index 000000000000..afbaafa793f1
--- /dev/null
+++ b/arch/blackfin/include/asm/nand.h
@@ -0,0 +1,47 @@
1/* linux/include/asm-blackfin/nand.h
2 *
3 * Copyright (c) 2007 Analog Devices, Inc.
4 * Bryan Wu <bryan.wu@analog.com>
5 *
6 * BF5XX - NAND flash controller platfrom_device info
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13/* struct bf5xx_nand_platform
14 *
15 * define a interface between platfrom board specific code and
16 * bf54x NFC driver.
17 *
18 * nr_partitions = number of partitions pointed to be partitoons (or zero)
19 * partitions = mtd partition list
20 */
21
22#define NFC_PG_SIZE_256 0
23#define NFC_PG_SIZE_512 1
24#define NFC_PG_SIZE_OFFSET 9
25
26#define NFC_NWIDTH_8 0
27#define NFC_NWIDTH_16 1
28#define NFC_NWIDTH_OFFSET 8
29
30#define NFC_RDDLY_OFFSET 4
31#define NFC_WRDLY_OFFSET 0
32
33#define NFC_STAT_NBUSY 1
34
35struct bf5xx_nand_platform {
36 /* NAND chip information */
37 unsigned short page_size;
38 unsigned short data_width;
39
40 /* RD/WR strobe delay timing information, all times in SCLK cycles */
41 unsigned short rd_dly;
42 unsigned short wr_dly;
43
44 /* NAND MTD partition information */
45 int nr_partitions;
46 struct mtd_partition *partitions;
47};
diff --git a/arch/blackfin/include/asm/page.h b/arch/blackfin/include/asm/page.h
new file mode 100644
index 000000000000..344f6a8c1f22
--- /dev/null
+++ b/arch/blackfin/include/asm/page.h
@@ -0,0 +1,88 @@
1#ifndef _BLACKFIN_PAGE_H
2#define _BLACKFIN_PAGE_H
3
4/* PAGE_SHIFT determines the page size */
5
6#define PAGE_SHIFT 12
7#ifdef __ASSEMBLY__
8#define PAGE_SIZE (1 << PAGE_SHIFT)
9#else
10#define PAGE_SIZE (1UL << PAGE_SHIFT)
11#endif
12#define PAGE_MASK (~(PAGE_SIZE-1))
13
14#include <asm/setup.h>
15
16#ifndef __ASSEMBLY__
17
18#define get_user_page(vaddr) __get_free_page(GFP_KERNEL)
19#define free_user_page(page, addr) free_page(addr)
20
21#define clear_page(page) memset((page), 0, PAGE_SIZE)
22#define copy_page(to,from) memcpy((to), (from), PAGE_SIZE)
23
24#define clear_user_page(page, vaddr,pg) clear_page(page)
25#define copy_user_page(to, from, vaddr,pg) copy_page(to, from)
26
27/*
28 * These are used to make use of C type-checking..
29 */
30typedef struct {
31 unsigned long pte;
32} pte_t;
33typedef struct {
34 unsigned long pmd[16];
35} pmd_t;
36typedef struct {
37 unsigned long pgd;
38} pgd_t;
39typedef struct {
40 unsigned long pgprot;
41} pgprot_t;
42typedef struct page *pgtable_t;
43
44#define pte_val(x) ((x).pte)
45#define pmd_val(x) ((&x)->pmd[0])
46#define pgd_val(x) ((x).pgd)
47#define pgprot_val(x) ((x).pgprot)
48
49#define __pte(x) ((pte_t) { (x) } )
50#define __pmd(x) ((pmd_t) { (x) } )
51#define __pgd(x) ((pgd_t) { (x) } )
52#define __pgprot(x) ((pgprot_t) { (x) } )
53
54extern unsigned long memory_start;
55extern unsigned long memory_end;
56
57#endif /* !__ASSEMBLY__ */
58
59#include <asm/page_offset.h>
60#include <asm/io.h>
61
62#define PAGE_OFFSET (PAGE_OFFSET_RAW)
63
64#ifndef __ASSEMBLY__
65
66#define __pa(vaddr) virt_to_phys((void *)(vaddr))
67#define __va(paddr) phys_to_virt((unsigned long)(paddr))
68
69#define MAP_NR(addr) (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT)
70
71#define virt_to_pfn(kaddr) (__pa(kaddr) >> PAGE_SHIFT)
72#define pfn_to_virt(pfn) __va((pfn) << PAGE_SHIFT)
73#define virt_to_page(addr) (mem_map + (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT))
74#define page_to_virt(page) ((((page) - mem_map) << PAGE_SHIFT) + PAGE_OFFSET)
75#define VALID_PAGE(page) ((page - mem_map) < max_mapnr)
76
77#define pfn_to_page(pfn) virt_to_page(pfn_to_virt(pfn))
78#define page_to_pfn(page) virt_to_pfn(page_to_virt(page))
79#define pfn_valid(pfn) ((pfn) < max_mapnr)
80
81#define virt_addr_valid(kaddr) (((void *)(kaddr) >= (void *)PAGE_OFFSET) && \
82 ((void *)(kaddr) < (void *)memory_end))
83
84#include <asm-generic/page.h>
85
86#endif /* __ASSEMBLY__ */
87
88#endif /* _BLACKFIN_PAGE_H */
diff --git a/arch/blackfin/include/asm/page_offset.h b/arch/blackfin/include/asm/page_offset.h
new file mode 100644
index 000000000000..cbaff24b4b25
--- /dev/null
+++ b/arch/blackfin/include/asm/page_offset.h
@@ -0,0 +1,6 @@
1
2/* This handles the memory map.. */
3
4#ifdef CONFIG_BLACKFIN
5#define PAGE_OFFSET_RAW 0x00000000
6#endif
diff --git a/arch/blackfin/include/asm/param.h b/arch/blackfin/include/asm/param.h
new file mode 100644
index 000000000000..41564a6347f8
--- /dev/null
+++ b/arch/blackfin/include/asm/param.h
@@ -0,0 +1,22 @@
1#ifndef _BLACKFIN_PARAM_H
2#define _BLACKFIN_PARAM_H
3
4#ifdef __KERNEL__
5#define HZ CONFIG_HZ
6#define USER_HZ 100
7#define CLOCKS_PER_SEC (USER_HZ)
8#endif
9
10#ifndef HZ
11#define HZ 100
12#endif
13
14#define EXEC_PAGESIZE 4096
15
16#ifndef NOGROUP
17#define NOGROUP (-1)
18#endif
19
20#define MAXHOSTNAMELEN 64 /* max length of hostname */
21
22#endif /* _BLACKFIN_PARAM_H */
diff --git a/arch/blackfin/include/asm/pci.h b/arch/blackfin/include/asm/pci.h
new file mode 100644
index 000000000000..61277358c865
--- /dev/null
+++ b/arch/blackfin/include/asm/pci.h
@@ -0,0 +1,148 @@
1/* Changed from asm-m68k version, Lineo Inc. May 2001 */
2
3#ifndef _ASM_BFIN_PCI_H
4#define _ASM_BFIN_PCI_H
5
6#include <asm/scatterlist.h>
7
8/*
9 *
10 * Written by Wout Klaren.
11 */
12
13/* Added by Chang Junxiao */
14#define PCIBIOS_MIN_IO 0x00001000
15#define PCIBIOS_MIN_MEM 0x10000000
16
17#define PCI_DMA_BUS_IS_PHYS (1)
18struct pci_ops;
19
20/*
21 * Structure with hardware dependent information and functions of the
22 * PCI bus.
23 */
24struct pci_bus_info {
25
26 /*
27 * Resources of the PCI bus.
28 */
29 struct resource mem_space;
30 struct resource io_space;
31
32 /*
33 * System dependent functions.
34 */
35 struct pci_ops *bfin_pci_ops;
36 void (*fixup) (int pci_modify);
37 void (*conf_device) (unsigned char bus, unsigned char device_fn);
38};
39
40#define pcibios_assign_all_busses() 0
41static inline void pcibios_set_master(struct pci_dev *dev)
42{
43
44 /* No special bus mastering setup handling */
45}
46static inline void pcibios_penalize_isa_irq(int irq)
47{
48
49 /* We don't do dynamic PCI IRQ allocation */
50}
51static inline dma_addr_t pci_map_single(struct pci_dev *hwdev, void *ptr,
52 size_t size, int direction)
53{
54 if (direction == PCI_DMA_NONE)
55 BUG();
56
57 /* return virt_to_bus(ptr); */
58 return (dma_addr_t) ptr;
59}
60
61/* Unmap a single streaming mode DMA translation. The dma_addr and size
62 * must match what was provided for in a previous pci_map_single call. All
63 * other usages are undefined.
64 *
65 * After this call, reads by the cpu to the buffer are guarenteed to see
66 * whatever the device wrote there.
67 */
68static inline void pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr,
69 size_t size, int direction)
70{
71 if (direction == PCI_DMA_NONE)
72 BUG();
73
74 /* Nothing to do */
75}
76
77/* Map a set of buffers described by scatterlist in streaming
78 * mode for DMA. This is the scather-gather version of the
79 * above pci_map_single interface. Here the scatter gather list
80 * elements are each tagged with the appropriate dma address
81 * and length. They are obtained via sg_dma_{address,length}(SG).
82 *
83 * NOTE: An implementation may be able to use a smaller number of
84 * DMA address/length pairs than there are SG table elements.
85 * (for example via virtual mapping capabilities)
86 * The routine returns the number of addr/length pairs actually
87 * used, at most nents.
88 *
89 * Device ownership issues as mentioned above for pci_map_single are
90 * the same here.
91 */
92static inline int pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg,
93 int nents, int direction)
94{
95 if (direction == PCI_DMA_NONE)
96 BUG();
97 return nents;
98}
99
100/* Unmap a set of streaming mode DMA translations.
101 * Again, cpu read rules concerning calls here are the same as for
102 * pci_unmap_single() above.
103 */
104static inline void pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg,
105 int nents, int direction)
106{
107 if (direction == PCI_DMA_NONE)
108 BUG();
109
110 /* Nothing to do */
111}
112
113/* Make physical memory consistent for a single
114 * streaming mode DMA translation after a transfer.
115 *
116 * If you perform a pci_map_single() but wish to interrogate the
117 * buffer using the cpu, yet do not wish to teardown the PCI dma
118 * mapping, you must call this function before doing so. At the
119 * next point you give the PCI dma address back to the card, the
120 * device again owns the buffer.
121 */
122static inline void pci_dma_sync_single(struct pci_dev *hwdev,
123 dma_addr_t dma_handle, size_t size,
124 int direction)
125{
126 if (direction == PCI_DMA_NONE)
127 BUG();
128
129 /* Nothing to do */
130}
131
132/* Make physical memory consistent for a set of streaming
133 * mode DMA translations after a transfer.
134 *
135 * The same as pci_dma_sync_single but for a scatter-gather list,
136 * same rules and usage.
137 */
138static inline void pci_dma_sync_sg(struct pci_dev *hwdev,
139 struct scatterlist *sg, int nelems,
140 int direction)
141{
142 if (direction == PCI_DMA_NONE)
143 BUG();
144
145 /* Nothing to do */
146}
147
148#endif /* _ASM_BFIN_PCI_H */
diff --git a/arch/blackfin/include/asm/percpu.h b/arch/blackfin/include/asm/percpu.h
new file mode 100644
index 000000000000..78dd61f6b39f
--- /dev/null
+++ b/arch/blackfin/include/asm/percpu.h
@@ -0,0 +1,6 @@
1#ifndef __ARCH_BLACKFIN_PERCPU__
2#define __ARCH_BLACKFIN_PERCPU__
3
4#include <asm-generic/percpu.h>
5
6#endif /* __ARCH_BLACKFIN_PERCPU__ */
diff --git a/arch/blackfin/include/asm/pgalloc.h b/arch/blackfin/include/asm/pgalloc.h
new file mode 100644
index 000000000000..c686e0542fd0
--- /dev/null
+++ b/arch/blackfin/include/asm/pgalloc.h
@@ -0,0 +1,8 @@
1#ifndef _BLACKFIN_PGALLOC_H
2#define _BLACKFIN_PGALLOC_H
3
4#include <asm/setup.h>
5
6#define check_pgt_cache() do { } while (0)
7
8#endif /* _BLACKFIN_PGALLOC_H */
diff --git a/arch/blackfin/include/asm/pgtable.h b/arch/blackfin/include/asm/pgtable.h
new file mode 100644
index 000000000000..f11684e4ade7
--- /dev/null
+++ b/arch/blackfin/include/asm/pgtable.h
@@ -0,0 +1,96 @@
1#ifndef _BLACKFIN_PGTABLE_H
2#define _BLACKFIN_PGTABLE_H
3
4#include <asm-generic/4level-fixup.h>
5
6#include <asm/page.h>
7#include <asm/def_LPBlackfin.h>
8
9typedef pte_t *pte_addr_t;
10/*
11* Trivial page table functions.
12*/
13#define pgd_present(pgd) (1)
14#define pgd_none(pgd) (0)
15#define pgd_bad(pgd) (0)
16#define pgd_clear(pgdp)
17#define kern_addr_valid(addr) (1)
18
19#define pmd_offset(a, b) ((void *)0)
20#define pmd_none(x) (!pmd_val(x))
21#define pmd_present(x) (pmd_val(x))
22#define pmd_clear(xp) do { set_pmd(xp, __pmd(0)); } while (0)
23#define pmd_bad(x) (pmd_val(x) & ~PAGE_MASK)
24
25#define kern_addr_valid(addr) (1)
26
27#define PAGE_NONE __pgprot(0) /* these mean nothing to NO_MM */
28#define PAGE_SHARED __pgprot(0) /* these mean nothing to NO_MM */
29#define PAGE_COPY __pgprot(0) /* these mean nothing to NO_MM */
30#define PAGE_READONLY __pgprot(0) /* these mean nothing to NO_MM */
31#define PAGE_KERNEL __pgprot(0) /* these mean nothing to NO_MM */
32
33extern void paging_init(void);
34
35#define __swp_type(x) (0)
36#define __swp_offset(x) (0)
37#define __swp_entry(typ,off) ((swp_entry_t) { ((typ) | ((off) << 7)) })
38#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
39#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
40
41static inline int pte_file(pte_t pte)
42{
43 return 0;
44}
45
46#define set_pte(pteptr, pteval) (*(pteptr) = pteval)
47#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval)
48
49/*
50 * Page assess control based on Blackfin CPLB management
51 */
52#define _PAGE_RD (CPLB_USER_RD)
53#define _PAGE_WR (CPLB_USER_WR)
54#define _PAGE_USER (CPLB_USER_RD | CPLB_USER_WR)
55#define _PAGE_ACCESSED CPLB_ALL_ACCESS
56#define _PAGE_DIRTY (CPLB_DIRTY)
57
58#define PTE_BIT_FUNC(fn, op) \
59 static inline pte_t pte_##fn(pte_t _pte) { _pte.pte op; return _pte; }
60
61PTE_BIT_FUNC(rdprotect, &= ~_PAGE_RD);
62PTE_BIT_FUNC(mkread, |= _PAGE_RD);
63PTE_BIT_FUNC(wrprotect, &= ~_PAGE_WR);
64PTE_BIT_FUNC(mkwrite, |= _PAGE_WR);
65PTE_BIT_FUNC(exprotect, &= ~_PAGE_USER);
66PTE_BIT_FUNC(mkexec, |= _PAGE_USER);
67PTE_BIT_FUNC(mkclean, &= ~_PAGE_DIRTY);
68PTE_BIT_FUNC(mkdirty, |= _PAGE_DIRTY);
69PTE_BIT_FUNC(mkold, &= ~_PAGE_ACCESSED);
70PTE_BIT_FUNC(mkyoung, |= _PAGE_ACCESSED);
71
72/*
73 * ZERO_PAGE is a global shared page that is always zero: used
74 * for zero-mapped memory areas etc..
75 */
76#define ZERO_PAGE(vaddr) (virt_to_page(0))
77
78extern unsigned int kobjsize(const void *objp);
79
80#define swapper_pg_dir ((pgd_t *) 0)
81/*
82 * No page table caches to initialise.
83 */
84#define pgtable_cache_init() do { } while (0)
85#define io_remap_pfn_range remap_pfn_range
86
87/*
88 * All 32bit addresses are effectively valid for vmalloc...
89 * Sort of meaningless for non-VM targets.
90 */
91#define VMALLOC_START 0
92#define VMALLOC_END 0xffffffff
93
94#include <asm-generic/pgtable.h>
95
96#endif /* _BLACKFIN_PGTABLE_H */
diff --git a/arch/blackfin/include/asm/poll.h b/arch/blackfin/include/asm/poll.h
new file mode 100644
index 000000000000..94cc2636e0e2
--- /dev/null
+++ b/arch/blackfin/include/asm/poll.h
@@ -0,0 +1,24 @@
1#ifndef __BFIN_POLL_H
2#define __BFIN_POLL_H
3
4#define POLLIN 1
5#define POLLPRI 2
6#define POLLOUT 4
7#define POLLERR 8
8#define POLLHUP 16
9#define POLLNVAL 32
10#define POLLRDNORM 64
11#define POLLWRNORM POLLOUT
12#define POLLRDBAND 128
13#define POLLWRBAND 256
14#define POLLMSG 0x0400
15#define POLLREMOVE 0x1000
16#define POLLRDHUP 0x2000
17
18struct pollfd {
19 int fd;
20 short events;
21 short revents;
22};
23
24#endif /* __BFIN_POLL_H */
diff --git a/arch/blackfin/include/asm/portmux.h b/arch/blackfin/include/asm/portmux.h
new file mode 100644
index 000000000000..88eb5c07cc24
--- /dev/null
+++ b/arch/blackfin/include/asm/portmux.h
@@ -0,0 +1,1188 @@
1/*
2 * Common header file for blackfin family of processors.
3 *
4 */
5
6#ifndef _PORTMUX_H_
7#define _PORTMUX_H_
8
9#define P_IDENT(x) ((x) & 0x1FF)
10#define P_FUNCT(x) (((x) & 0x3) << 9)
11#define P_FUNCT2MUX(x) (((x) >> 9) & 0x3)
12#define P_DEFINED 0x8000
13#define P_UNDEF 0x4000
14#define P_MAYSHARE 0x2000
15#define P_DONTCARE 0x1000
16
17
18int peripheral_request(unsigned short per, const char *label);
19void peripheral_free(unsigned short per);
20int peripheral_request_list(const unsigned short per[], const char *label);
21void peripheral_free_list(const unsigned short per[]);
22
23#include <asm/gpio.h>
24#include <mach/portmux.h>
25
26#ifndef P_SPORT2_TFS
27#define P_SPORT2_TFS P_UNDEF
28#endif
29
30#ifndef P_SPORT2_DTSEC
31#define P_SPORT2_DTSEC P_UNDEF
32#endif
33
34#ifndef P_SPORT2_DTPRI
35#define P_SPORT2_DTPRI P_UNDEF
36#endif
37
38#ifndef P_SPORT2_TSCLK
39#define P_SPORT2_TSCLK P_UNDEF
40#endif
41
42#ifndef P_SPORT2_RFS
43#define P_SPORT2_RFS P_UNDEF
44#endif
45
46#ifndef P_SPORT2_DRSEC
47#define P_SPORT2_DRSEC P_UNDEF
48#endif
49
50#ifndef P_SPORT2_DRPRI
51#define P_SPORT2_DRPRI P_UNDEF
52#endif
53
54#ifndef P_SPORT2_RSCLK
55#define P_SPORT2_RSCLK P_UNDEF
56#endif
57
58#ifndef P_SPORT3_TFS
59#define P_SPORT3_TFS P_UNDEF
60#endif
61
62#ifndef P_SPORT3_DTSEC
63#define P_SPORT3_DTSEC P_UNDEF
64#endif
65
66#ifndef P_SPORT3_DTPRI
67#define P_SPORT3_DTPRI P_UNDEF
68#endif
69
70#ifndef P_SPORT3_TSCLK
71#define P_SPORT3_TSCLK P_UNDEF
72#endif
73
74#ifndef P_SPORT3_RFS
75#define P_SPORT3_RFS P_UNDEF
76#endif
77
78#ifndef P_SPORT3_DRSEC
79#define P_SPORT3_DRSEC P_UNDEF
80#endif
81
82#ifndef P_SPORT3_DRPRI
83#define P_SPORT3_DRPRI P_UNDEF
84#endif
85
86#ifndef P_SPORT3_RSCLK
87#define P_SPORT3_RSCLK P_UNDEF
88#endif
89
90#ifndef P_TMR4
91#define P_TMR4 P_UNDEF
92#endif
93
94#ifndef P_TMR5
95#define P_TMR5 P_UNDEF
96#endif
97
98#ifndef P_TMR6
99#define P_TMR6 P_UNDEF
100#endif
101
102#ifndef P_TMR7
103#define P_TMR7 P_UNDEF
104#endif
105
106#ifndef P_TWI1_SCL
107#define P_TWI1_SCL P_UNDEF
108#endif
109
110#ifndef P_TWI1_SDA
111#define P_TWI1_SDA P_UNDEF
112#endif
113
114#ifndef P_UART3_RTS
115#define P_UART3_RTS P_UNDEF
116#endif
117
118#ifndef P_UART3_CTS
119#define P_UART3_CTS P_UNDEF
120#endif
121
122#ifndef P_UART2_TX
123#define P_UART2_TX P_UNDEF
124#endif
125
126#ifndef P_UART2_RX
127#define P_UART2_RX P_UNDEF
128#endif
129
130#ifndef P_UART3_TX
131#define P_UART3_TX P_UNDEF
132#endif
133
134#ifndef P_UART3_RX
135#define P_UART3_RX P_UNDEF
136#endif
137
138#ifndef P_SPI2_SS
139#define P_SPI2_SS P_UNDEF
140#endif
141
142#ifndef P_SPI2_SSEL1
143#define P_SPI2_SSEL1 P_UNDEF
144#endif
145
146#ifndef P_SPI2_SSEL2
147#define P_SPI2_SSEL2 P_UNDEF
148#endif
149
150#ifndef P_SPI2_SSEL3
151#define P_SPI2_SSEL3 P_UNDEF
152#endif
153
154#ifndef P_SPI2_SSEL4
155#define P_SPI2_SSEL4 P_UNDEF
156#endif
157
158#ifndef P_SPI2_SSEL5
159#define P_SPI2_SSEL5 P_UNDEF
160#endif
161
162#ifndef P_SPI2_SSEL6
163#define P_SPI2_SSEL6 P_UNDEF
164#endif
165
166#ifndef P_SPI2_SSEL7
167#define P_SPI2_SSEL7 P_UNDEF
168#endif
169
170#ifndef P_SPI2_SCK
171#define P_SPI2_SCK P_UNDEF
172#endif
173
174#ifndef P_SPI2_MOSI
175#define P_SPI2_MOSI P_UNDEF
176#endif
177
178#ifndef P_SPI2_MISO
179#define P_SPI2_MISO P_UNDEF
180#endif
181
182#ifndef P_TMR0
183#define P_TMR0 P_UNDEF
184#endif
185
186#ifndef P_TMR1
187#define P_TMR1 P_UNDEF
188#endif
189
190#ifndef P_TMR2
191#define P_TMR2 P_UNDEF
192#endif
193
194#ifndef P_TMR3
195#define P_TMR3 P_UNDEF
196#endif
197
198#ifndef P_SPORT0_TFS
199#define P_SPORT0_TFS P_UNDEF
200#endif
201
202#ifndef P_SPORT0_DTSEC
203#define P_SPORT0_DTSEC P_UNDEF
204#endif
205
206#ifndef P_SPORT0_DTPRI
207#define P_SPORT0_DTPRI P_UNDEF
208#endif
209
210#ifndef P_SPORT0_TSCLK
211#define P_SPORT0_TSCLK P_UNDEF
212#endif
213
214#ifndef P_SPORT0_RFS
215#define P_SPORT0_RFS P_UNDEF
216#endif
217
218#ifndef P_SPORT0_DRSEC
219#define P_SPORT0_DRSEC P_UNDEF
220#endif
221
222#ifndef P_SPORT0_DRPRI
223#define P_SPORT0_DRPRI P_UNDEF
224#endif
225
226#ifndef P_SPORT0_RSCLK
227#define P_SPORT0_RSCLK P_UNDEF
228#endif
229
230#ifndef P_SD_D0
231#define P_SD_D0 P_UNDEF
232#endif
233
234#ifndef P_SD_D1
235#define P_SD_D1 P_UNDEF
236#endif
237
238#ifndef P_SD_D2
239#define P_SD_D2 P_UNDEF
240#endif
241
242#ifndef P_SD_D3
243#define P_SD_D3 P_UNDEF
244#endif
245
246#ifndef P_SD_CLK
247#define P_SD_CLK P_UNDEF
248#endif
249
250#ifndef P_SD_CMD
251#define P_SD_CMD P_UNDEF
252#endif
253
254#ifndef P_MMCLK
255#define P_MMCLK P_UNDEF
256#endif
257
258#ifndef P_MBCLK
259#define P_MBCLK P_UNDEF
260#endif
261
262#ifndef P_PPI1_D0
263#define P_PPI1_D0 P_UNDEF
264#endif
265
266#ifndef P_PPI1_D1
267#define P_PPI1_D1 P_UNDEF
268#endif
269
270#ifndef P_PPI1_D2
271#define P_PPI1_D2 P_UNDEF
272#endif
273
274#ifndef P_PPI1_D3
275#define P_PPI1_D3 P_UNDEF
276#endif
277
278#ifndef P_PPI1_D4
279#define P_PPI1_D4 P_UNDEF
280#endif
281
282#ifndef P_PPI1_D5
283#define P_PPI1_D5 P_UNDEF
284#endif
285
286#ifndef P_PPI1_D6
287#define P_PPI1_D6 P_UNDEF
288#endif
289
290#ifndef P_PPI1_D7
291#define P_PPI1_D7 P_UNDEF
292#endif
293
294#ifndef P_PPI1_D8
295#define P_PPI1_D8 P_UNDEF
296#endif
297
298#ifndef P_PPI1_D9
299#define P_PPI1_D9 P_UNDEF
300#endif
301
302#ifndef P_PPI1_D10
303#define P_PPI1_D10 P_UNDEF
304#endif
305
306#ifndef P_PPI1_D11
307#define P_PPI1_D11 P_UNDEF
308#endif
309
310#ifndef P_PPI1_D12
311#define P_PPI1_D12 P_UNDEF
312#endif
313
314#ifndef P_PPI1_D13
315#define P_PPI1_D13 P_UNDEF
316#endif
317
318#ifndef P_PPI1_D14
319#define P_PPI1_D14 P_UNDEF
320#endif
321
322#ifndef P_PPI1_D15
323#define P_PPI1_D15 P_UNDEF
324#endif
325
326#ifndef P_HOST_D8
327#define P_HOST_D8 P_UNDEF
328#endif
329
330#ifndef P_HOST_D9
331#define P_HOST_D9 P_UNDEF
332#endif
333
334#ifndef P_HOST_D10
335#define P_HOST_D10 P_UNDEF
336#endif
337
338#ifndef P_HOST_D11
339#define P_HOST_D11 P_UNDEF
340#endif
341
342#ifndef P_HOST_D12
343#define P_HOST_D12 P_UNDEF
344#endif
345
346#ifndef P_HOST_D13
347#define P_HOST_D13 P_UNDEF
348#endif
349
350#ifndef P_HOST_D14
351#define P_HOST_D14 P_UNDEF
352#endif
353
354#ifndef P_HOST_D15
355#define P_HOST_D15 P_UNDEF
356#endif
357
358#ifndef P_HOST_D0
359#define P_HOST_D0 P_UNDEF
360#endif
361
362#ifndef P_HOST_D1
363#define P_HOST_D1 P_UNDEF
364#endif
365
366#ifndef P_HOST_D2
367#define P_HOST_D2 P_UNDEF
368#endif
369
370#ifndef P_HOST_D3
371#define P_HOST_D3 P_UNDEF
372#endif
373
374#ifndef P_HOST_D4
375#define P_HOST_D4 P_UNDEF
376#endif
377
378#ifndef P_HOST_D5
379#define P_HOST_D5 P_UNDEF
380#endif
381
382#ifndef P_HOST_D6
383#define P_HOST_D6 P_UNDEF
384#endif
385
386#ifndef P_HOST_D7
387#define P_HOST_D7 P_UNDEF
388#endif
389
390#ifndef P_SPORT1_TFS
391#define P_SPORT1_TFS P_UNDEF
392#endif
393
394#ifndef P_SPORT1_DTSEC
395#define P_SPORT1_DTSEC P_UNDEF
396#endif
397
398#ifndef P_SPORT1_DTPRI
399#define P_SPORT1_DTPRI P_UNDEF
400#endif
401
402#ifndef P_SPORT1_TSCLK
403#define P_SPORT1_TSCLK P_UNDEF
404#endif
405
406#ifndef P_SPORT1_RFS
407#define P_SPORT1_RFS P_UNDEF
408#endif
409
410#ifndef P_SPORT1_DRSEC
411#define P_SPORT1_DRSEC P_UNDEF
412#endif
413
414#ifndef P_SPORT1_DRPRI
415#define P_SPORT1_DRPRI P_UNDEF
416#endif
417
418#ifndef P_SPORT1_RSCLK
419#define P_SPORT1_RSCLK P_UNDEF
420#endif
421
422#ifndef P_PPI2_D0
423#define P_PPI2_D0 P_UNDEF
424#endif
425
426#ifndef P_PPI2_D1
427#define P_PPI2_D1 P_UNDEF
428#endif
429
430#ifndef P_PPI2_D2
431#define P_PPI2_D2 P_UNDEF
432#endif
433
434#ifndef P_PPI2_D3
435#define P_PPI2_D3 P_UNDEF
436#endif
437
438#ifndef P_PPI2_D4
439#define P_PPI2_D4 P_UNDEF
440#endif
441
442#ifndef P_PPI2_D5
443#define P_PPI2_D5 P_UNDEF
444#endif
445
446#ifndef P_PPI2_D6
447#define P_PPI2_D6 P_UNDEF
448#endif
449
450#ifndef P_PPI2_D7
451#define P_PPI2_D7 P_UNDEF
452#endif
453
454#ifndef P_PPI0_D18
455#define P_PPI0_D18 P_UNDEF
456#endif
457
458#ifndef P_PPI0_D19
459#define P_PPI0_D19 P_UNDEF
460#endif
461
462#ifndef P_PPI0_D20
463#define P_PPI0_D20 P_UNDEF
464#endif
465
466#ifndef P_PPI0_D21
467#define P_PPI0_D21 P_UNDEF
468#endif
469
470#ifndef P_PPI0_D22
471#define P_PPI0_D22 P_UNDEF
472#endif
473
474#ifndef P_PPI0_D23
475#define P_PPI0_D23 P_UNDEF
476#endif
477
478#ifndef P_KEY_ROW0
479#define P_KEY_ROW0 P_UNDEF
480#endif
481
482#ifndef P_KEY_ROW1
483#define P_KEY_ROW1 P_UNDEF
484#endif
485
486#ifndef P_KEY_ROW2
487#define P_KEY_ROW2 P_UNDEF
488#endif
489
490#ifndef P_KEY_ROW3
491#define P_KEY_ROW3 P_UNDEF
492#endif
493
494#ifndef P_KEY_COL0
495#define P_KEY_COL0 P_UNDEF
496#endif
497
498#ifndef P_KEY_COL1
499#define P_KEY_COL1 P_UNDEF
500#endif
501
502#ifndef P_KEY_COL2
503#define P_KEY_COL2 P_UNDEF
504#endif
505
506#ifndef P_KEY_COL3
507#define P_KEY_COL3 P_UNDEF
508#endif
509
510#ifndef P_SPI0_SCK
511#define P_SPI0_SCK P_UNDEF
512#endif
513
514#ifndef P_SPI0_MISO
515#define P_SPI0_MISO P_UNDEF
516#endif
517
518#ifndef P_SPI0_MOSI
519#define P_SPI0_MOSI P_UNDEF
520#endif
521
522#ifndef P_SPI0_SS
523#define P_SPI0_SS P_UNDEF
524#endif
525
526#ifndef P_SPI0_SSEL1
527#define P_SPI0_SSEL1 P_UNDEF
528#endif
529
530#ifndef P_SPI0_SSEL2
531#define P_SPI0_SSEL2 P_UNDEF
532#endif
533
534#ifndef P_SPI0_SSEL3
535#define P_SPI0_SSEL3 P_UNDEF
536#endif
537
538#ifndef P_SPI0_SSEL4
539#define P_SPI0_SSEL4 P_UNDEF
540#endif
541
542#ifndef P_SPI0_SSEL5
543#define P_SPI0_SSEL5 P_UNDEF
544#endif
545
546#ifndef P_SPI0_SSEL6
547#define P_SPI0_SSEL6 P_UNDEF
548#endif
549
550#ifndef P_SPI0_SSEL7
551#define P_SPI0_SSEL7 P_UNDEF
552#endif
553
554#ifndef P_UART0_TX
555#define P_UART0_TX P_UNDEF
556#endif
557
558#ifndef P_UART0_RX
559#define P_UART0_RX P_UNDEF
560#endif
561
562#ifndef P_UART1_RTS
563#define P_UART1_RTS P_UNDEF
564#endif
565
566#ifndef P_UART1_CTS
567#define P_UART1_CTS P_UNDEF
568#endif
569
570#ifndef P_PPI1_CLK
571#define P_PPI1_CLK P_UNDEF
572#endif
573
574#ifndef P_PPI1_FS1
575#define P_PPI1_FS1 P_UNDEF
576#endif
577
578#ifndef P_PPI1_FS2
579#define P_PPI1_FS2 P_UNDEF
580#endif
581
582#ifndef P_TWI0_SCL
583#define P_TWI0_SCL P_UNDEF
584#endif
585
586#ifndef P_TWI0_SDA
587#define P_TWI0_SDA P_UNDEF
588#endif
589
590#ifndef P_KEY_COL7
591#define P_KEY_COL7 P_UNDEF
592#endif
593
594#ifndef P_KEY_ROW6
595#define P_KEY_ROW6 P_UNDEF
596#endif
597
598#ifndef P_KEY_COL6
599#define P_KEY_COL6 P_UNDEF
600#endif
601
602#ifndef P_KEY_ROW5
603#define P_KEY_ROW5 P_UNDEF
604#endif
605
606#ifndef P_KEY_COL5
607#define P_KEY_COL5 P_UNDEF
608#endif
609
610#ifndef P_KEY_ROW4
611#define P_KEY_ROW4 P_UNDEF
612#endif
613
614#ifndef P_KEY_COL4
615#define P_KEY_COL4 P_UNDEF
616#endif
617
618#ifndef P_KEY_ROW7
619#define P_KEY_ROW7 P_UNDEF
620#endif
621
622#ifndef P_PPI0_D0
623#define P_PPI0_D0 P_UNDEF
624#endif
625
626#ifndef P_PPI0_D1
627#define P_PPI0_D1 P_UNDEF
628#endif
629
630#ifndef P_PPI0_D2
631#define P_PPI0_D2 P_UNDEF
632#endif
633
634#ifndef P_PPI0_D3
635#define P_PPI0_D3 P_UNDEF
636#endif
637
638#ifndef P_PPI0_D4
639#define P_PPI0_D4 P_UNDEF
640#endif
641
642#ifndef P_PPI0_D5
643#define P_PPI0_D5 P_UNDEF
644#endif
645
646#ifndef P_PPI0_D6
647#define P_PPI0_D6 P_UNDEF
648#endif
649
650#ifndef P_PPI0_D7
651#define P_PPI0_D7 P_UNDEF
652#endif
653
654#ifndef P_PPI0_D8
655#define P_PPI0_D8 P_UNDEF
656#endif
657
658#ifndef P_PPI0_D9
659#define P_PPI0_D9 P_UNDEF
660#endif
661
662#ifndef P_PPI0_D10
663#define P_PPI0_D10 P_UNDEF
664#endif
665
666#ifndef P_PPI0_D11
667#define P_PPI0_D11 P_UNDEF
668#endif
669
670#ifndef P_PPI0_D12
671#define P_PPI0_D12 P_UNDEF
672#endif
673
674#ifndef P_PPI0_D13
675#define P_PPI0_D13 P_UNDEF
676#endif
677
678#ifndef P_PPI0_D14
679#define P_PPI0_D14 P_UNDEF
680#endif
681
682#ifndef P_PPI0_D15
683#define P_PPI0_D15 P_UNDEF
684#endif
685
686#ifndef P_ATAPI_D0A
687#define P_ATAPI_D0A P_UNDEF
688#endif
689
690#ifndef P_ATAPI_D1A
691#define P_ATAPI_D1A P_UNDEF
692#endif
693
694#ifndef P_ATAPI_D2A
695#define P_ATAPI_D2A P_UNDEF
696#endif
697
698#ifndef P_ATAPI_D3A
699#define P_ATAPI_D3A P_UNDEF
700#endif
701
702#ifndef P_ATAPI_D4A
703#define P_ATAPI_D4A P_UNDEF
704#endif
705
706#ifndef P_ATAPI_D5A
707#define P_ATAPI_D5A P_UNDEF
708#endif
709
710#ifndef P_ATAPI_D6A
711#define P_ATAPI_D6A P_UNDEF
712#endif
713
714#ifndef P_ATAPI_D7A
715#define P_ATAPI_D7A P_UNDEF
716#endif
717
718#ifndef P_ATAPI_D8A
719#define P_ATAPI_D8A P_UNDEF
720#endif
721
722#ifndef P_ATAPI_D9A
723#define P_ATAPI_D9A P_UNDEF
724#endif
725
726#ifndef P_ATAPI_D10A
727#define P_ATAPI_D10A P_UNDEF
728#endif
729
730#ifndef P_ATAPI_D11A
731#define P_ATAPI_D11A P_UNDEF
732#endif
733
734#ifndef P_ATAPI_D12A
735#define P_ATAPI_D12A P_UNDEF
736#endif
737
738#ifndef P_ATAPI_D13A
739#define P_ATAPI_D13A P_UNDEF
740#endif
741
742#ifndef P_ATAPI_D14A
743#define P_ATAPI_D14A P_UNDEF
744#endif
745
746#ifndef P_ATAPI_D15A
747#define P_ATAPI_D15A P_UNDEF
748#endif
749
750#ifndef P_PPI0_CLK
751#define P_PPI0_CLK P_UNDEF
752#endif
753
754#ifndef P_PPI0_FS1
755#define P_PPI0_FS1 P_UNDEF
756#endif
757
758#ifndef P_PPI0_FS2
759#define P_PPI0_FS2 P_UNDEF
760#endif
761
762#ifndef P_PPI0_D16
763#define P_PPI0_D16 P_UNDEF
764#endif
765
766#ifndef P_PPI0_D17
767#define P_PPI0_D17 P_UNDEF
768#endif
769
770#ifndef P_SPI1_SSEL1
771#define P_SPI1_SSEL1 P_UNDEF
772#endif
773
774#ifndef P_SPI1_SSEL2
775#define P_SPI1_SSEL2 P_UNDEF
776#endif
777
778#ifndef P_SPI1_SSEL3
779#define P_SPI1_SSEL3 P_UNDEF
780#endif
781
782
783#ifndef P_SPI1_SSEL4
784#define P_SPI1_SSEL4 P_UNDEF
785#endif
786
787#ifndef P_SPI1_SSEL5
788#define P_SPI1_SSEL5 P_UNDEF
789#endif
790
791#ifndef P_SPI1_SSEL6
792#define P_SPI1_SSEL6 P_UNDEF
793#endif
794
795#ifndef P_SPI1_SSEL7
796#define P_SPI1_SSEL7 P_UNDEF
797#endif
798
799#ifndef P_SPI1_SCK
800#define P_SPI1_SCK P_UNDEF
801#endif
802
803#ifndef P_SPI1_MISO
804#define P_SPI1_MISO P_UNDEF
805#endif
806
807#ifndef P_SPI1_MOSI
808#define P_SPI1_MOSI P_UNDEF
809#endif
810
811#ifndef P_SPI1_SS
812#define P_SPI1_SS P_UNDEF
813#endif
814
815#ifndef P_CAN0_TX
816#define P_CAN0_TX P_UNDEF
817#endif
818
819#ifndef P_CAN0_RX
820#define P_CAN0_RX P_UNDEF
821#endif
822
823#ifndef P_CAN1_TX
824#define P_CAN1_TX P_UNDEF
825#endif
826
827#ifndef P_CAN1_RX
828#define P_CAN1_RX P_UNDEF
829#endif
830
831#ifndef P_ATAPI_A0A
832#define P_ATAPI_A0A P_UNDEF
833#endif
834
835#ifndef P_ATAPI_A1A
836#define P_ATAPI_A1A P_UNDEF
837#endif
838
839#ifndef P_ATAPI_A2A
840#define P_ATAPI_A2A P_UNDEF
841#endif
842
843#ifndef P_HOST_CE
844#define P_HOST_CE P_UNDEF
845#endif
846
847#ifndef P_HOST_RD
848#define P_HOST_RD P_UNDEF
849#endif
850
851#ifndef P_HOST_WR
852#define P_HOST_WR P_UNDEF
853#endif
854
855#ifndef P_MTXONB
856#define P_MTXONB P_UNDEF
857#endif
858
859#ifndef P_PPI2_FS2
860#define P_PPI2_FS2 P_UNDEF
861#endif
862
863#ifndef P_PPI2_FS1
864#define P_PPI2_FS1 P_UNDEF
865#endif
866
867#ifndef P_PPI2_CLK
868#define P_PPI2_CLK P_UNDEF
869#endif
870
871#ifndef P_CNT_CZM
872#define P_CNT_CZM P_UNDEF
873#endif
874
875#ifndef P_UART1_TX
876#define P_UART1_TX P_UNDEF
877#endif
878
879#ifndef P_UART1_RX
880#define P_UART1_RX P_UNDEF
881#endif
882
883#ifndef P_ATAPI_RESET
884#define P_ATAPI_RESET P_UNDEF
885#endif
886
887#ifndef P_HOST_ADDR
888#define P_HOST_ADDR P_UNDEF
889#endif
890
891#ifndef P_HOST_ACK
892#define P_HOST_ACK P_UNDEF
893#endif
894
895#ifndef P_MTX
896#define P_MTX P_UNDEF
897#endif
898
899#ifndef P_MRX
900#define P_MRX P_UNDEF
901#endif
902
903#ifndef P_MRXONB
904#define P_MRXONB P_UNDEF
905#endif
906
907#ifndef P_A4
908#define P_A4 P_UNDEF
909#endif
910
911#ifndef P_A5
912#define P_A5 P_UNDEF
913#endif
914
915#ifndef P_A6
916#define P_A6 P_UNDEF
917#endif
918
919#ifndef P_A7
920#define P_A7 P_UNDEF
921#endif
922
923#ifndef P_A8
924#define P_A8 P_UNDEF
925#endif
926
927#ifndef P_A9
928#define P_A9 P_UNDEF
929#endif
930
931#ifndef P_PPI1_FS3
932#define P_PPI1_FS3 P_UNDEF
933#endif
934
935#ifndef P_PPI2_FS3
936#define P_PPI2_FS3 P_UNDEF
937#endif
938
939#ifndef P_TMR8
940#define P_TMR8 P_UNDEF
941#endif
942
943#ifndef P_TMR9
944#define P_TMR9 P_UNDEF
945#endif
946
947#ifndef P_TMR10
948#define P_TMR10 P_UNDEF
949#endif
950#ifndef P_TMR11
951#define P_TMR11 P_UNDEF
952#endif
953
954#ifndef P_DMAR0
955#define P_DMAR0 P_UNDEF
956#endif
957
958#ifndef P_DMAR1
959#define P_DMAR1 P_UNDEF
960#endif
961
962#ifndef P_PPI0_FS3
963#define P_PPI0_FS3 P_UNDEF
964#endif
965
966#ifndef P_CNT_CDG
967#define P_CNT_CDG P_UNDEF
968#endif
969
970#ifndef P_CNT_CUD
971#define P_CNT_CUD P_UNDEF
972#endif
973
974#ifndef P_A10
975#define P_A10 P_UNDEF
976#endif
977
978#ifndef P_A11
979#define P_A11 P_UNDEF
980#endif
981
982#ifndef P_A12
983#define P_A12 P_UNDEF
984#endif
985
986#ifndef P_A13
987#define P_A13 P_UNDEF
988#endif
989
990#ifndef P_A14
991#define P_A14 P_UNDEF
992#endif
993
994#ifndef P_A15
995#define P_A15 P_UNDEF
996#endif
997
998#ifndef P_A16
999#define P_A16 P_UNDEF
1000#endif
1001
1002#ifndef P_A17
1003#define P_A17 P_UNDEF
1004#endif
1005
1006#ifndef P_A18
1007#define P_A18 P_UNDEF
1008#endif
1009
1010#ifndef P_A19
1011#define P_A19 P_UNDEF
1012#endif
1013
1014#ifndef P_A20
1015#define P_A20 P_UNDEF
1016#endif
1017
1018#ifndef P_A21
1019#define P_A21 P_UNDEF
1020#endif
1021
1022#ifndef P_A22
1023#define P_A22 P_UNDEF
1024#endif
1025
1026#ifndef P_A23
1027#define P_A23 P_UNDEF
1028#endif
1029
1030#ifndef P_A24
1031#define P_A24 P_UNDEF
1032#endif
1033
1034#ifndef P_A25
1035#define P_A25 P_UNDEF
1036#endif
1037
1038#ifndef P_NOR_CLK
1039#define P_NOR_CLK P_UNDEF
1040#endif
1041
1042#ifndef P_TMRCLK
1043#define P_TMRCLK P_UNDEF
1044#endif
1045
1046#ifndef P_AMC_ARDY_NOR_WAIT
1047#define P_AMC_ARDY_NOR_WAIT P_UNDEF
1048#endif
1049
1050#ifndef P_NAND_CE
1051#define P_NAND_CE P_UNDEF
1052#endif
1053
1054#ifndef P_NAND_RB
1055#define P_NAND_RB P_UNDEF
1056#endif
1057
1058#ifndef P_ATAPI_DIOR
1059#define P_ATAPI_DIOR P_UNDEF
1060#endif
1061
1062#ifndef P_ATAPI_DIOW
1063#define P_ATAPI_DIOW P_UNDEF
1064#endif
1065
1066#ifndef P_ATAPI_CS0
1067#define P_ATAPI_CS0 P_UNDEF
1068#endif
1069
1070#ifndef P_ATAPI_CS1
1071#define P_ATAPI_CS1 P_UNDEF
1072#endif
1073
1074#ifndef P_ATAPI_DMACK
1075#define P_ATAPI_DMACK P_UNDEF
1076#endif
1077
1078#ifndef P_ATAPI_DMARQ
1079#define P_ATAPI_DMARQ P_UNDEF
1080#endif
1081
1082#ifndef P_ATAPI_INTRQ
1083#define P_ATAPI_INTRQ P_UNDEF
1084#endif
1085
1086#ifndef P_ATAPI_IORDY
1087#define P_ATAPI_IORDY P_UNDEF
1088#endif
1089
1090#ifndef P_AMC_BR
1091#define P_AMC_BR P_UNDEF
1092#endif
1093
1094#ifndef P_AMC_BG
1095#define P_AMC_BG P_UNDEF
1096#endif
1097
1098#ifndef P_AMC_BGH
1099#define P_AMC_BGH P_UNDEF
1100#endif
1101
1102/* EMAC */
1103
1104#ifndef P_MII0_ETxD0
1105#define P_MII0_ETxD0 P_UNDEF
1106#endif
1107
1108#ifndef P_MII0_ETxD1
1109#define P_MII0_ETxD1 P_UNDEF
1110#endif
1111
1112#ifndef P_MII0_ETxD2
1113#define P_MII0_ETxD2 P_UNDEF
1114#endif
1115
1116#ifndef P_MII0_ETxD3
1117#define P_MII0_ETxD3 P_UNDEF
1118#endif
1119
1120#ifndef P_MII0_ETxEN
1121#define P_MII0_ETxEN P_UNDEF
1122#endif
1123
1124#ifndef P_MII0_TxCLK
1125#define P_MII0_TxCLK P_UNDEF
1126#endif
1127
1128#ifndef P_MII0_PHYINT
1129#define P_MII0_PHYINT P_UNDEF
1130#endif
1131
1132#ifndef P_MII0_COL
1133#define P_MII0_COL P_UNDEF
1134#endif
1135
1136#ifndef P_MII0_ERxD0
1137#define P_MII0_ERxD0 P_UNDEF
1138#endif
1139
1140#ifndef P_MII0_ERxD1
1141#define P_MII0_ERxD1 P_UNDEF
1142#endif
1143
1144#ifndef P_MII0_ERxD2
1145#define P_MII0_ERxD2 P_UNDEF
1146#endif
1147
1148#ifndef P_MII0_ERxD3
1149#define P_MII0_ERxD3 P_UNDEF
1150#endif
1151
1152#ifndef P_MII0_ERxDV
1153#define P_MII0_ERxDV P_UNDEF
1154#endif
1155
1156#ifndef P_MII0_ERxCLK
1157#define P_MII0_ERxCLK P_UNDEF
1158#endif
1159
1160#ifndef P_MII0_ERxER
1161#define P_MII0_ERxER P_UNDEF
1162#endif
1163
1164#ifndef P_MII0_CRS
1165#define P_MII0_CRS P_UNDEF
1166#endif
1167
1168#ifndef P_RMII0_REF_CLK
1169#define P_RMII0_REF_CLK P_UNDEF
1170#endif
1171
1172#ifndef P_RMII0_MDINT
1173#define P_RMII0_MDINT P_UNDEF
1174#endif
1175
1176#ifndef P_RMII0_CRS_DV
1177#define P_RMII0_CRS_DV P_UNDEF
1178#endif
1179
1180#ifndef P_MDC
1181#define P_MDC P_UNDEF
1182#endif
1183
1184#ifndef P_MDIO
1185#define P_MDIO P_UNDEF
1186#endif
1187
1188#endif /* _PORTMUX_H_ */
diff --git a/arch/blackfin/include/asm/posix_types.h b/arch/blackfin/include/asm/posix_types.h
new file mode 100644
index 000000000000..23aa1f8c1bd1
--- /dev/null
+++ b/arch/blackfin/include/asm/posix_types.h
@@ -0,0 +1,61 @@
1#ifndef __ARCH_BFIN_POSIX_TYPES_H
2#define __ARCH_BFIN_POSIX_TYPES_H
3
4/*
5 * This file is generally used by user-level software, so you need to
6 * be a little careful about namespace pollution etc. Also, we cannot
7 * assume GCC is being used.
8 */
9
10typedef unsigned long __kernel_ino_t;
11typedef unsigned short __kernel_mode_t;
12typedef unsigned short __kernel_nlink_t;
13typedef long __kernel_off_t;
14typedef int __kernel_pid_t;
15typedef unsigned int __kernel_ipc_pid_t;
16typedef unsigned int __kernel_uid_t;
17typedef unsigned int __kernel_gid_t;
18typedef unsigned long __kernel_size_t;
19typedef long __kernel_ssize_t;
20typedef int __kernel_ptrdiff_t;
21typedef long __kernel_time_t;
22typedef long __kernel_suseconds_t;
23typedef long __kernel_clock_t;
24typedef int __kernel_timer_t;
25typedef int __kernel_clockid_t;
26typedef int __kernel_daddr_t;
27typedef char *__kernel_caddr_t;
28typedef unsigned short __kernel_uid16_t;
29typedef unsigned short __kernel_gid16_t;
30typedef unsigned int __kernel_uid32_t;
31typedef unsigned int __kernel_gid32_t;
32
33typedef unsigned short __kernel_old_uid_t;
34typedef unsigned short __kernel_old_gid_t;
35typedef unsigned short __kernel_old_dev_t;
36
37#ifdef __GNUC__
38typedef long long __kernel_loff_t;
39#endif
40
41typedef struct {
42 int val[2];
43} __kernel_fsid_t;
44
45#if defined(__KERNEL__)
46
47#undef __FD_SET
48#define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d))
49
50#undef __FD_CLR
51#define __FD_CLR(d, set) ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d))
52
53#undef __FD_ISSET
54#define __FD_ISSET(d, set) ((set)->fds_bits[__FDELT(d)] & __FDMASK(d))
55
56#undef __FD_ZERO
57#define __FD_ZERO(fdsetp) (memset (fdsetp, 0, sizeof(*(fd_set *)fdsetp)))
58
59#endif /* defined(__KERNEL__) */
60
61#endif
diff --git a/arch/blackfin/include/asm/processor.h b/arch/blackfin/include/asm/processor.h
new file mode 100644
index 000000000000..6f3995b119d8
--- /dev/null
+++ b/arch/blackfin/include/asm/processor.h
@@ -0,0 +1,158 @@
1#ifndef __ASM_BFIN_PROCESSOR_H
2#define __ASM_BFIN_PROCESSOR_H
3
4/*
5 * Default implementation of macro that returns current
6 * instruction pointer ("program counter").
7 */
8#define current_text_addr() ({ __label__ _l; _l: &&_l;})
9
10#include <asm/blackfin.h>
11#include <asm/segment.h>
12#include <linux/compiler.h>
13
14static inline unsigned long rdusp(void)
15{
16 unsigned long usp;
17
18 __asm__ __volatile__("%0 = usp;\n\t":"=da"(usp));
19 return usp;
20}
21
22static inline void wrusp(unsigned long usp)
23{
24 __asm__ __volatile__("usp = %0;\n\t"::"da"(usp));
25}
26
27/*
28 * User space process size: 1st byte beyond user address space.
29 * Fairly meaningless on nommu. Parts of user programs can be scattered
30 * in a lot of places, so just disable this by setting it to 0xFFFFFFFF.
31 */
32#define TASK_SIZE 0xFFFFFFFF
33
34#ifdef __KERNEL__
35#define STACK_TOP TASK_SIZE
36#endif
37
38#define TASK_UNMAPPED_BASE 0
39
40struct thread_struct {
41 unsigned long ksp; /* kernel stack pointer */
42 unsigned long usp; /* user stack pointer */
43 unsigned short seqstat; /* saved status register */
44 unsigned long esp0; /* points to SR of stack frame pt_regs */
45 unsigned long pc; /* instruction pointer */
46 void * debuggerinfo;
47};
48
49#define INIT_THREAD { \
50 sizeof(init_stack) + (unsigned long) init_stack, 0, \
51 PS_S, 0, 0 \
52}
53
54/*
55 * Do necessary setup to start up a newly executed thread.
56 *
57 * pass the data segment into user programs if it exists,
58 * it can't hurt anything as far as I can tell
59 */
60#define start_thread(_regs, _pc, _usp) \
61do { \
62 set_fs(USER_DS); \
63 (_regs)->pc = (_pc); \
64 if (current->mm) \
65 (_regs)->p5 = current->mm->start_data; \
66 task_thread_info(current)->l1_task_info.stack_start \
67 = (void *)current->mm->context.stack_start; \
68 task_thread_info(current)->l1_task_info.lowest_sp = (void *)(_usp); \
69 memcpy(L1_SCRATCH_TASK_INFO, &task_thread_info(current)->l1_task_info, \
70 sizeof(*L1_SCRATCH_TASK_INFO)); \
71 wrusp(_usp); \
72} while(0)
73
74/* Forward declaration, a strange C thing */
75struct task_struct;
76
77/* Free all resources held by a thread. */
78static inline void release_thread(struct task_struct *dead_task)
79{
80}
81
82#define prepare_to_copy(tsk) do { } while (0)
83
84extern int kernel_thread(int (*fn) (void *), void *arg, unsigned long flags);
85
86/*
87 * Free current thread data structures etc..
88 */
89static inline void exit_thread(void)
90{
91}
92
93/*
94 * Return saved PC of a blocked thread.
95 */
96#define thread_saved_pc(tsk) (tsk->thread.pc)
97
98unsigned long get_wchan(struct task_struct *p);
99
100#define KSTK_EIP(tsk) \
101 ({ \
102 unsigned long eip = 0; \
103 if ((tsk)->thread.esp0 > PAGE_SIZE && \
104 MAP_NR((tsk)->thread.esp0) < max_mapnr) \
105 eip = ((struct pt_regs *) (tsk)->thread.esp0)->pc; \
106 eip; })
107#define KSTK_ESP(tsk) ((tsk) == current ? rdusp() : (tsk)->thread.usp)
108
109#define cpu_relax() barrier()
110
111/* Get the Silicon Revision of the chip */
112static inline uint32_t __pure bfin_revid(void)
113{
114 /* stored in the upper 4 bits */
115 uint32_t revid = bfin_read_CHIPID() >> 28;
116
117#ifdef CONFIG_BF52x
118 /* ANOMALY_05000357
119 * Incorrect Revision Number in DSPID Register
120 */
121 if (revid == 0)
122 switch (bfin_read16(_BOOTROM_GET_DXE_ADDRESS_TWI)) {
123 case 0x0010:
124 revid = 0;
125 break;
126 case 0x2796:
127 revid = 1;
128 break;
129 default:
130 revid = 0xFFFF;
131 break;
132 }
133#endif
134 return revid;
135}
136
137static inline uint32_t __pure bfin_compiled_revid(void)
138{
139#if defined(CONFIG_BF_REV_0_0)
140 return 0;
141#elif defined(CONFIG_BF_REV_0_1)
142 return 1;
143#elif defined(CONFIG_BF_REV_0_2)
144 return 2;
145#elif defined(CONFIG_BF_REV_0_3)
146 return 3;
147#elif defined(CONFIG_BF_REV_0_4)
148 return 4;
149#elif defined(CONFIG_BF_REV_0_5)
150 return 5;
151#elif defined(CONFIG_BF_REV_ANY)
152 return 0xffff;
153#else
154 return -1;
155#endif
156}
157
158#endif
diff --git a/arch/blackfin/include/asm/ptrace.h b/arch/blackfin/include/asm/ptrace.h
new file mode 100644
index 000000000000..a45a80e54adc
--- /dev/null
+++ b/arch/blackfin/include/asm/ptrace.h
@@ -0,0 +1,168 @@
1#ifndef _BFIN_PTRACE_H
2#define _BFIN_PTRACE_H
3
4/*
5 * GCC defines register number like this:
6 * -----------------------------
7 * 0 - 7 are data registers R0-R7
8 * 8 - 15 are address registers P0-P7
9 * 16 - 31 dsp registers I/B/L0 -- I/B/L3 & M0--M3
10 * 32 - 33 A registers A0 & A1
11 * 34 - status register
12 * -----------------------------
13 *
14 * We follows above, except:
15 * 32-33 --- Low 32-bit of A0&1
16 * 34-35 --- High 8-bit of A0&1
17 */
18
19#ifndef __ASSEMBLY__
20
21/* this struct defines the way the registers are stored on the
22 stack during a system call. */
23
24struct pt_regs {
25 long orig_pc;
26 long ipend;
27 long seqstat;
28 long rete;
29 long retn;
30 long retx;
31 long pc; /* PC == RETI */
32 long rets;
33 long reserved; /* Used as scratch during system calls */
34 long astat;
35 long lb1;
36 long lb0;
37 long lt1;
38 long lt0;
39 long lc1;
40 long lc0;
41 long a1w;
42 long a1x;
43 long a0w;
44 long a0x;
45 long b3;
46 long b2;
47 long b1;
48 long b0;
49 long l3;
50 long l2;
51 long l1;
52 long l0;
53 long m3;
54 long m2;
55 long m1;
56 long m0;
57 long i3;
58 long i2;
59 long i1;
60 long i0;
61 long usp;
62 long fp;
63 long p5;
64 long p4;
65 long p3;
66 long p2;
67 long p1;
68 long p0;
69 long r7;
70 long r6;
71 long r5;
72 long r4;
73 long r3;
74 long r2;
75 long r1;
76 long r0;
77 long orig_r0;
78 long orig_p0;
79 long syscfg;
80};
81
82/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
83#define PTRACE_GETREGS 12
84#define PTRACE_SETREGS 13 /* ptrace signal */
85
86#define PTRACE_GETFDPIC 31
87#define PTRACE_GETFDPIC_EXEC 0
88#define PTRACE_GETFDPIC_INTERP 1
89
90#define PS_S (0x0002)
91
92#ifdef __KERNEL__
93
94/* user_mode returns true if only one bit is set in IPEND, other than the
95 master interrupt enable. */
96#define user_mode(regs) (!(((regs)->ipend & ~0x10) & (((regs)->ipend & ~0x10) - 1)))
97#define instruction_pointer(regs) ((regs)->pc)
98#define profile_pc(regs) instruction_pointer(regs)
99extern void show_regs(struct pt_regs *);
100
101#endif /* __KERNEL__ */
102
103#endif /* __ASSEMBLY__ */
104
105/*
106 * Offsets used by 'ptrace' system call interface.
107 */
108
109#define PT_R0 204
110#define PT_R1 200
111#define PT_R2 196
112#define PT_R3 192
113#define PT_R4 188
114#define PT_R5 184
115#define PT_R6 180
116#define PT_R7 176
117#define PT_P0 172
118#define PT_P1 168
119#define PT_P2 164
120#define PT_P3 160
121#define PT_P4 156
122#define PT_P5 152
123#define PT_FP 148
124#define PT_USP 144
125#define PT_I0 140
126#define PT_I1 136
127#define PT_I2 132
128#define PT_I3 128
129#define PT_M0 124
130#define PT_M1 120
131#define PT_M2 116
132#define PT_M3 112
133#define PT_L0 108
134#define PT_L1 104
135#define PT_L2 100
136#define PT_L3 96
137#define PT_B0 92
138#define PT_B1 88
139#define PT_B2 84
140#define PT_B3 80
141#define PT_A0X 76
142#define PT_A0W 72
143#define PT_A1X 68
144#define PT_A1W 64
145#define PT_LC0 60
146#define PT_LC1 56
147#define PT_LT0 52
148#define PT_LT1 48
149#define PT_LB0 44
150#define PT_LB1 40
151#define PT_ASTAT 36
152#define PT_RESERVED 32
153#define PT_RETS 28
154#define PT_PC 24
155#define PT_RETX 20
156#define PT_RETN 16
157#define PT_RETE 12
158#define PT_SEQSTAT 8
159#define PT_IPEND 4
160
161#define PT_SYSCFG 216
162#define PT_TEXT_ADDR 220
163#define PT_TEXT_END_ADDR 224
164#define PT_DATA_ADDR 228
165#define PT_FDPIC_EXEC 232
166#define PT_FDPIC_INTERP 236
167
168#endif /* _BFIN_PTRACE_H */
diff --git a/arch/blackfin/include/asm/reboot.h b/arch/blackfin/include/asm/reboot.h
new file mode 100644
index 000000000000..6d448b5f5985
--- /dev/null
+++ b/arch/blackfin/include/asm/reboot.h
@@ -0,0 +1,20 @@
1/*
2 * include/asm-blackfin/reboot.h - shutdown/reboot header
3 *
4 * Copyright 2004-2007 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef __ASM_REBOOT_H__
10#define __ASM_REBOOT_H__
11
12/* optional board specific hooks */
13extern void native_machine_restart(char *cmd);
14extern void native_machine_halt(void);
15extern void native_machine_power_off(void);
16
17/* common reboot workarounds */
18extern void bfin_gpio_reset_spi0_ssel1(void);
19
20#endif
diff --git a/arch/blackfin/include/asm/resource.h b/arch/blackfin/include/asm/resource.h
new file mode 100644
index 000000000000..091355ab3495
--- /dev/null
+++ b/arch/blackfin/include/asm/resource.h
@@ -0,0 +1,6 @@
1#ifndef _BFIN_RESOURCE_H
2#define _BFIN_RESOURCE_H
3
4#include <asm-generic/resource.h>
5
6#endif /* _BFIN_RESOURCE_H */
diff --git a/arch/blackfin/include/asm/scatterlist.h b/arch/blackfin/include/asm/scatterlist.h
new file mode 100644
index 000000000000..04f448711cd0
--- /dev/null
+++ b/arch/blackfin/include/asm/scatterlist.h
@@ -0,0 +1,28 @@
1#ifndef _BLACKFIN_SCATTERLIST_H
2#define _BLACKFIN_SCATTERLIST_H
3
4#include <linux/mm.h>
5
6struct scatterlist {
7#ifdef CONFIG_DEBUG_SG
8 unsigned long sg_magic;
9#endif
10 unsigned long page_link;
11 unsigned int offset;
12 dma_addr_t dma_address;
13 unsigned int length;
14};
15
16/*
17 * These macros should be used after a pci_map_sg call has been done
18 * to get bus addresses of each of the SG entries and their lengths.
19 * You should only work with the number of sg entries pci_map_sg
20 * returns, or alternatively stop on the first sg_dma_len(sg) which
21 * is 0.
22 */
23#define sg_dma_address(sg) ((sg)->dma_address)
24#define sg_dma_len(sg) ((sg)->length)
25
26#define ISA_DMA_THRESHOLD (0xffffffff)
27
28#endif /* !(_BLACKFIN_SCATTERLIST_H) */
diff --git a/arch/blackfin/include/asm/sections.h b/arch/blackfin/include/asm/sections.h
new file mode 100644
index 000000000000..1443c3353a8c
--- /dev/null
+++ b/arch/blackfin/include/asm/sections.h
@@ -0,0 +1,7 @@
1#ifndef _BLACKFIN_SECTIONS_H
2#define _BLACKFIN_SECTIONS_H
3
4/* nothing to see, move along */
5#include <asm-generic/sections.h>
6
7#endif
diff --git a/arch/blackfin/include/asm/segment.h b/arch/blackfin/include/asm/segment.h
new file mode 100644
index 000000000000..02cfd09b5a99
--- /dev/null
+++ b/arch/blackfin/include/asm/segment.h
@@ -0,0 +1,7 @@
1#ifndef _BFIN_SEGMENT_H
2#define _BFIN_SEGMENT_H
3
4#define KERNEL_DS (0x5)
5#define USER_DS (0x1)
6
7#endif /* _BFIN_SEGMENT_H */
diff --git a/arch/blackfin/include/asm/sembuf.h b/arch/blackfin/include/asm/sembuf.h
new file mode 100644
index 000000000000..18deb5c7fa5d
--- /dev/null
+++ b/arch/blackfin/include/asm/sembuf.h
@@ -0,0 +1,25 @@
1#ifndef _BFIN_SEMBUF_H
2#define _BFIN_SEMBUF_H
3
4/*
5 * The semid64_ds structure for bfin architecture.
6 * Note extra padding because this structure is passed back and forth
7 * between kernel and user space.
8 *
9 * Pad space is left for:
10 * - 64-bit time_t to solve y2038 problem
11 * - 2 miscellaneous 32-bit values
12 */
13
14struct semid64_ds {
15 struct ipc64_perm sem_perm; /* permissions .. see ipc.h */
16 __kernel_time_t sem_otime; /* last semop time */
17 unsigned long __unused1;
18 __kernel_time_t sem_ctime; /* last change time */
19 unsigned long __unused2;
20 unsigned long sem_nsems; /* no. of semaphores in array */
21 unsigned long __unused3;
22 unsigned long __unused4;
23};
24
25#endif /* _BFIN_SEMBUF_H */
diff --git a/arch/blackfin/include/asm/serial.h b/arch/blackfin/include/asm/serial.h
new file mode 100644
index 000000000000..994dd869558c
--- /dev/null
+++ b/arch/blackfin/include/asm/serial.h
@@ -0,0 +1,5 @@
1/*
2 * include/asm-blackfin/serial.h
3 */
4
5#define SERIAL_EXTRA_IRQ_FLAGS IRQF_TRIGGER_HIGH
diff --git a/arch/blackfin/include/asm/setup.h b/arch/blackfin/include/asm/setup.h
new file mode 100644
index 000000000000..01c8c6cbe6fc
--- /dev/null
+++ b/arch/blackfin/include/asm/setup.h
@@ -0,0 +1,17 @@
1/*
2** asm/setup.h -- Definition of the Linux/bfin setup information
3**
4** This file is subject to the terms and conditions of the GNU General Public
5** License. See the file COPYING in the main directory of this archive
6** for more details.
7**
8** Copyright Lineo, Inc 2001 Tony Kou
9**
10*/
11
12#ifndef _BFIN_SETUP_H
13#define _BFIN_SETUP_H
14
15#define COMMAND_LINE_SIZE 512
16
17#endif /* _BFIN_SETUP_H */
diff --git a/arch/blackfin/include/asm/shmbuf.h b/arch/blackfin/include/asm/shmbuf.h
new file mode 100644
index 000000000000..612436303e89
--- /dev/null
+++ b/arch/blackfin/include/asm/shmbuf.h
@@ -0,0 +1,42 @@
1#ifndef _BFIN_SHMBUF_H
2#define _BFIN_SHMBUF_H
3
4/*
5 * The shmid64_ds structure for bfin architecture.
6 * Note extra padding because this structure is passed back and forth
7 * between kernel and user space.
8 *
9 * Pad space is left for:
10 * - 64-bit time_t to solve y2038 problem
11 * - 2 miscellaneous 32-bit values
12 */
13
14struct shmid64_ds {
15 struct ipc64_perm shm_perm; /* operation perms */
16 size_t shm_segsz; /* size of segment (bytes) */
17 __kernel_time_t shm_atime; /* last attach time */
18 unsigned long __unused1;
19 __kernel_time_t shm_dtime; /* last detach time */
20 unsigned long __unused2;
21 __kernel_time_t shm_ctime; /* last change time */
22 unsigned long __unused3;
23 __kernel_pid_t shm_cpid; /* pid of creator */
24 __kernel_pid_t shm_lpid; /* pid of last operator */
25 unsigned long shm_nattch; /* no. of current attaches */
26 unsigned long __unused4;
27 unsigned long __unused5;
28};
29
30struct shminfo64 {
31 unsigned long shmmax;
32 unsigned long shmmin;
33 unsigned long shmmni;
34 unsigned long shmseg;
35 unsigned long shmall;
36 unsigned long __unused1;
37 unsigned long __unused2;
38 unsigned long __unused3;
39 unsigned long __unused4;
40};
41
42#endif /* _BFIN_SHMBUF_H */
diff --git a/arch/blackfin/include/asm/shmparam.h b/arch/blackfin/include/asm/shmparam.h
new file mode 100644
index 000000000000..3c03906b7664
--- /dev/null
+++ b/arch/blackfin/include/asm/shmparam.h
@@ -0,0 +1,6 @@
1#ifndef _BFIN_SHMPARAM_H
2#define _BFIN_SHMPARAM_H
3
4#define SHMLBA PAGE_SIZE /* attach addr a multiple of this */
5
6#endif /* _BFIN_SHMPARAM_H */
diff --git a/arch/blackfin/include/asm/sigcontext.h b/arch/blackfin/include/asm/sigcontext.h
new file mode 100644
index 000000000000..ce00b03c2775
--- /dev/null
+++ b/arch/blackfin/include/asm/sigcontext.h
@@ -0,0 +1,55 @@
1#ifndef _ASM_BLACKFIN_SIGCONTEXT_H
2#define _ASM_BLACKFIN_SIGCONTEXT_H
3
4/* Add new entries at the end of the structure only. */
5struct sigcontext {
6 unsigned long sc_r0;
7 unsigned long sc_r1;
8 unsigned long sc_r2;
9 unsigned long sc_r3;
10 unsigned long sc_r4;
11 unsigned long sc_r5;
12 unsigned long sc_r6;
13 unsigned long sc_r7;
14 unsigned long sc_p0;
15 unsigned long sc_p1;
16 unsigned long sc_p2;
17 unsigned long sc_p3;
18 unsigned long sc_p4;
19 unsigned long sc_p5;
20 unsigned long sc_usp;
21 unsigned long sc_a0w;
22 unsigned long sc_a1w;
23 unsigned long sc_a0x;
24 unsigned long sc_a1x;
25 unsigned long sc_astat;
26 unsigned long sc_rets;
27 unsigned long sc_pc;
28 unsigned long sc_retx;
29 unsigned long sc_fp;
30 unsigned long sc_i0;
31 unsigned long sc_i1;
32 unsigned long sc_i2;
33 unsigned long sc_i3;
34 unsigned long sc_m0;
35 unsigned long sc_m1;
36 unsigned long sc_m2;
37 unsigned long sc_m3;
38 unsigned long sc_l0;
39 unsigned long sc_l1;
40 unsigned long sc_l2;
41 unsigned long sc_l3;
42 unsigned long sc_b0;
43 unsigned long sc_b1;
44 unsigned long sc_b2;
45 unsigned long sc_b3;
46 unsigned long sc_lc0;
47 unsigned long sc_lc1;
48 unsigned long sc_lt0;
49 unsigned long sc_lt1;
50 unsigned long sc_lb0;
51 unsigned long sc_lb1;
52 unsigned long sc_seqstat;
53};
54
55#endif
diff --git a/arch/blackfin/include/asm/siginfo.h b/arch/blackfin/include/asm/siginfo.h
new file mode 100644
index 000000000000..eca4565cea37
--- /dev/null
+++ b/arch/blackfin/include/asm/siginfo.h
@@ -0,0 +1,35 @@
1#ifndef _BFIN_SIGINFO_H
2#define _BFIN_SIGINFO_H
3
4#include <linux/types.h>
5#include <asm-generic/siginfo.h>
6
7#define UID16_SIGINFO_COMPAT_NEEDED
8
9#define si_uid16 _sifields._kill._uid
10
11#define ILL_ILLPARAOP (__SI_FAULT|2) /* illegal opcode combine ********** */
12#define ILL_ILLEXCPT (__SI_FAULT|4) /* unrecoverable exception ********** */
13#define ILL_CPLB_VI (__SI_FAULT|9) /* D/I CPLB protect violation ******** */
14#define ILL_CPLB_MISS (__SI_FAULT|10) /* D/I CPLB miss ******** */
15#define ILL_CPLB_MULHIT (__SI_FAULT|11) /* D/I CPLB multiple hit ******** */
16
17/*
18 * SIGBUS si_codes
19 */
20#define BUS_OPFETCH (__SI_FAULT|4) /* error from instruction fetch ******** */
21
22/*
23 * SIGTRAP si_codes
24 */
25#define TRAP_STEP (__SI_FAULT|1) /* single-step breakpoint************* */
26#define TRAP_TRACEFLOW (__SI_FAULT|2) /* trace buffer overflow ************* */
27#define TRAP_WATCHPT (__SI_FAULT|3) /* watchpoint match ************* */
28#define TRAP_ILLTRAP (__SI_FAULT|4) /* illegal trap ************* */
29
30/*
31 * SIGSEGV si_codes
32 */
33#define SEGV_STACKFLOW (__SI_FAULT|3) /* stack overflow */
34
35#endif
diff --git a/arch/blackfin/include/asm/signal.h b/arch/blackfin/include/asm/signal.h
new file mode 100644
index 000000000000..87951d251458
--- /dev/null
+++ b/arch/blackfin/include/asm/signal.h
@@ -0,0 +1,160 @@
1#ifndef _BLACKFIN_SIGNAL_H
2#define _BLACKFIN_SIGNAL_H
3
4#include <linux/types.h>
5
6/* Avoid too many header ordering problems. */
7struct siginfo;
8
9#ifdef __KERNEL__
10/* Most things should be clean enough to redefine this at will, if care
11 is taken to make libc match. */
12
13#define _NSIG 64
14#define _NSIG_BPW 32
15#define _NSIG_WORDS (_NSIG / _NSIG_BPW)
16
17typedef unsigned long old_sigset_t; /* at least 32 bits */
18
19typedef struct {
20 unsigned long sig[_NSIG_WORDS];
21} sigset_t;
22
23#else
24/* Here we must cater to libcs that poke about in kernel headers. */
25
26#define NSIG 32
27typedef unsigned long sigset_t;
28
29#endif /* __KERNEL__ */
30
31#define SIGHUP 1
32#define SIGINT 2
33#define SIGQUIT 3
34#define SIGILL 4
35#define SIGTRAP 5
36#define SIGABRT 6
37#define SIGIOT 6
38#define SIGBUS 7
39#define SIGFPE 8
40#define SIGKILL 9
41#define SIGUSR1 10
42#define SIGSEGV 11
43#define SIGUSR2 12
44#define SIGPIPE 13
45#define SIGALRM 14
46#define SIGTERM 15
47#define SIGSTKFLT 16
48#define SIGCHLD 17
49#define SIGCONT 18
50#define SIGSTOP 19
51#define SIGTSTP 20
52#define SIGTTIN 21
53#define SIGTTOU 22
54#define SIGURG 23
55#define SIGXCPU 24
56#define SIGXFSZ 25
57#define SIGVTALRM 26
58#define SIGPROF 27
59#define SIGWINCH 28
60#define SIGIO 29
61#define SIGPOLL SIGIO
62/*
63#define SIGLOST 29
64*/
65#define SIGPWR 30
66#define SIGSYS 31
67#define SIGUNUSED 31
68
69/* These should not be considered constants from userland. */
70#define SIGRTMIN 32
71#define SIGRTMAX _NSIG
72
73/*
74 * SA_FLAGS values:
75 *
76 * SA_ONSTACK indicates that a registered stack_t will be used.
77 * SA_INTERRUPT is a no-op, but left due to historical reasons. Use the
78 * SA_RESTART flag to get restarting signals (which were the default long ago)
79 * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
80 * SA_RESETHAND clears the handler when the signal is delivered.
81 * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies.
82 * SA_NODEFER prevents the current signal from being masked in the handler.
83 *
84 * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
85 * Unix names RESETHAND and NODEFER respectively.
86 */
87#define SA_NOCLDSTOP 0x00000001
88#define SA_NOCLDWAIT 0x00000002 /* not supported yet */
89#define SA_SIGINFO 0x00000004
90#define SA_ONSTACK 0x08000000
91#define SA_RESTART 0x10000000
92#define SA_NODEFER 0x40000000
93#define SA_RESETHAND 0x80000000
94
95#define SA_NOMASK SA_NODEFER
96#define SA_ONESHOT SA_RESETHAND
97
98/*
99 * sigaltstack controls
100 */
101#define SS_ONSTACK 1
102#define SS_DISABLE 2
103
104#define MINSIGSTKSZ 2048
105#define SIGSTKSZ 8192
106
107#include <asm-generic/signal.h>
108
109#ifdef __KERNEL__
110struct old_sigaction {
111 __sighandler_t sa_handler;
112 old_sigset_t sa_mask;
113 unsigned long sa_flags;
114 void (*sa_restorer) (void);
115};
116
117struct sigaction {
118 __sighandler_t sa_handler;
119 unsigned long sa_flags;
120 void (*sa_restorer) (void);
121 sigset_t sa_mask; /* mask last for extensibility */
122};
123
124struct k_sigaction {
125 struct sigaction sa;
126};
127#else
128/* Here we must cater to libcs that poke about in kernel headers. */
129
130struct sigaction {
131 union {
132 __sighandler_t _sa_handler;
133 void (*_sa_sigaction) (int, struct siginfo *, void *);
134 } _u;
135 sigset_t sa_mask;
136 unsigned long sa_flags;
137 void (*sa_restorer) (void);
138};
139
140#define sa_handler _u._sa_handler
141#define sa_sigaction _u._sa_sigaction
142
143#endif /* __KERNEL__ */
144
145typedef struct sigaltstack {
146 void __user *ss_sp;
147 int ss_flags;
148 size_t ss_size;
149} stack_t;
150
151#ifdef __KERNEL__
152
153#include <asm/sigcontext.h>
154#undef __HAVE_ARCH_SIG_BITOPS
155
156#define ptrace_signal_deliver(regs, cookie) do { } while (0)
157
158#endif /* __KERNEL__ */
159
160#endif /* _BLACKFIN_SIGNAL_H */
diff --git a/arch/blackfin/include/asm/socket.h b/arch/blackfin/include/asm/socket.h
new file mode 100644
index 000000000000..2ca702e44d47
--- /dev/null
+++ b/arch/blackfin/include/asm/socket.h
@@ -0,0 +1,56 @@
1#ifndef _ASM_SOCKET_H
2#define _ASM_SOCKET_H
3
4#include <asm/sockios.h>
5
6/* For setsockoptions(2) */
7#define SOL_SOCKET 1
8
9#define SO_DEBUG 1
10#define SO_REUSEADDR 2
11#define SO_TYPE 3
12#define SO_ERROR 4
13#define SO_DONTROUTE 5
14#define SO_BROADCAST 6
15#define SO_SNDBUF 7
16#define SO_RCVBUF 8
17#define SO_SNDBUFFORCE 32
18#define SO_RCVBUFFORCE 33
19#define SO_KEEPALIVE 9
20#define SO_OOBINLINE 10
21#define SO_NO_CHECK 11
22#define SO_PRIORITY 12
23#define SO_LINGER 13
24#define SO_BSDCOMPAT 14
25/* To add :#define SO_REUSEPORT 15 */
26#define SO_PASSCRED 16
27#define SO_PEERCRED 17
28#define SO_RCVLOWAT 18
29#define SO_SNDLOWAT 19
30#define SO_RCVTIMEO 20
31#define SO_SNDTIMEO 21
32
33/* Security levels - as per NRL IPv6 - don't actually do anything */
34#define SO_SECURITY_AUTHENTICATION 22
35#define SO_SECURITY_ENCRYPTION_TRANSPORT 23
36#define SO_SECURITY_ENCRYPTION_NETWORK 24
37
38#define SO_BINDTODEVICE 25
39
40/* Socket filtering */
41#define SO_ATTACH_FILTER 26
42#define SO_DETACH_FILTER 27
43
44#define SO_PEERNAME 28
45#define SO_TIMESTAMP 29
46#define SCM_TIMESTAMP SO_TIMESTAMP
47
48#define SO_ACCEPTCONN 30
49#define SO_PEERSEC 31
50#define SO_PASSSEC 34
51#define SO_TIMESTAMPNS 35
52#define SCM_TIMESTAMPNS SO_TIMESTAMPNS
53
54#define SO_MARK 36
55
56#endif /* _ASM_SOCKET_H */
diff --git a/arch/blackfin/include/asm/sockios.h b/arch/blackfin/include/asm/sockios.h
new file mode 100644
index 000000000000..426b89bfaa8b
--- /dev/null
+++ b/arch/blackfin/include/asm/sockios.h
@@ -0,0 +1,13 @@
1#ifndef __ARCH_BFIN_SOCKIOS__
2#define __ARCH_BFIN_SOCKIOS__
3
4/* Socket-level I/O control calls. */
5#define FIOSETOWN 0x8901
6#define SIOCSPGRP 0x8902
7#define FIOGETOWN 0x8903
8#define SIOCGPGRP 0x8904
9#define SIOCATMARK 0x8905
10#define SIOCGSTAMP 0x8906 /* Get stamp (timeval) */
11#define SIOCGSTAMPNS 0x8907 /* Get stamp (timespec) */
12
13#endif /* __ARCH_BFIN_SOCKIOS__ */
diff --git a/arch/blackfin/include/asm/spinlock.h b/arch/blackfin/include/asm/spinlock.h
new file mode 100644
index 000000000000..64e908a50646
--- /dev/null
+++ b/arch/blackfin/include/asm/spinlock.h
@@ -0,0 +1,6 @@
1#ifndef __BFIN_SPINLOCK_H
2#define __BFIN_SPINLOCK_H
3
4#error blackfin architecture does not support SMP spin lock yet
5
6#endif
diff --git a/arch/blackfin/include/asm/stat.h b/arch/blackfin/include/asm/stat.h
new file mode 100644
index 000000000000..d2b6f11ec231
--- /dev/null
+++ b/arch/blackfin/include/asm/stat.h
@@ -0,0 +1,63 @@
1#ifndef _BFIN_STAT_H
2#define _BFIN_STAT_H
3
4struct stat {
5 unsigned short st_dev;
6 unsigned short __pad1;
7 unsigned long st_ino;
8 unsigned short st_mode;
9 unsigned short st_nlink;
10 unsigned short st_uid;
11 unsigned short st_gid;
12 unsigned short st_rdev;
13 unsigned short __pad2;
14 unsigned long st_size;
15 unsigned long st_blksize;
16 unsigned long st_blocks;
17 unsigned long st_atime;
18 unsigned long __unused1;
19 unsigned long st_mtime;
20 unsigned long __unused2;
21 unsigned long st_ctime;
22 unsigned long __unused3;
23 unsigned long __unused4;
24 unsigned long __unused5;
25};
26
27/* This matches struct stat64 in glibc2.1, hence the absolutely
28 * insane amounts of padding around dev_t's.
29 */
30struct stat64 {
31 unsigned long long st_dev;
32 unsigned char __pad1[4];
33
34#define STAT64_HAS_BROKEN_ST_INO 1
35 unsigned long __st_ino;
36
37 unsigned int st_mode;
38 unsigned int st_nlink;
39
40 unsigned long st_uid;
41 unsigned long st_gid;
42
43 unsigned long long st_rdev;
44 unsigned char __pad2[4];
45
46 long long st_size;
47 unsigned long st_blksize;
48
49 long long st_blocks; /* Number 512-byte blocks allocated. */
50
51 unsigned long st_atime;
52 unsigned long st_atime_nsec;
53
54 unsigned long st_mtime;
55 unsigned long st_mtime_nsec;
56
57 unsigned long st_ctime;
58 unsigned long st_ctime_nsec;
59
60 unsigned long long st_ino;
61};
62
63#endif /* _BFIN_STAT_H */
diff --git a/arch/blackfin/include/asm/statfs.h b/arch/blackfin/include/asm/statfs.h
new file mode 100644
index 000000000000..350672091ba3
--- /dev/null
+++ b/arch/blackfin/include/asm/statfs.h
@@ -0,0 +1,6 @@
1#ifndef _BFIN_STATFS_H
2#define _BFIN_STATFS_H
3
4#include <asm-generic/statfs.h>
5
6#endif /* _BFIN_STATFS_H */
diff --git a/arch/blackfin/include/asm/string.h b/arch/blackfin/include/asm/string.h
new file mode 100644
index 000000000000..321f4d96e4ae
--- /dev/null
+++ b/arch/blackfin/include/asm/string.h
@@ -0,0 +1,137 @@
1#ifndef _BLACKFIN_STRING_H_
2#define _BLACKFIN_STRING_H_
3
4#include <linux/types.h>
5
6#ifdef __KERNEL__ /* only set these up for kernel code */
7
8#define __HAVE_ARCH_STRCPY
9extern inline char *strcpy(char *dest, const char *src)
10{
11 char *xdest = dest;
12 char temp = 0;
13
14 __asm__ __volatile__ (
15 "1:"
16 "%2 = B [%1++] (Z);"
17 "B [%0++] = %2;"
18 "CC = %2;"
19 "if cc jump 1b (bp);"
20 : "+&a" (dest), "+&a" (src), "=&d" (temp)
21 :
22 : "memory", "CC");
23
24 return xdest;
25}
26
27#define __HAVE_ARCH_STRNCPY
28extern inline char *strncpy(char *dest, const char *src, size_t n)
29{
30 char *xdest = dest;
31 char temp = 0;
32
33 if (n == 0)
34 return xdest;
35
36 __asm__ __volatile__ (
37 "1:"
38 "%3 = B [%1++] (Z);"
39 "B [%0++] = %3;"
40 "CC = %3;"
41 "if ! cc jump 2f;"
42 "%2 += -1;"
43 "CC = %2 == 0;"
44 "if ! cc jump 1b (bp);"
45 "jump 4f;"
46 "2:"
47 /* if src is shorter than n, we need to null pad bytes now */
48 "%3 = 0;"
49 "3:"
50 "%2 += -1;"
51 "CC = %2 == 0;"
52 "if cc jump 4f;"
53 "B [%0++] = %3;"
54 "jump 3b;"
55 "4:"
56 : "+&a" (dest), "+&a" (src), "+&da" (n), "=&d" (temp)
57 :
58 : "memory", "CC");
59
60 return xdest;
61}
62
63#define __HAVE_ARCH_STRCMP
64extern inline int strcmp(const char *cs, const char *ct)
65{
66 /* need to use int's here so the char's in the assembly don't get
67 * sign extended incorrectly when we don't want them to be
68 */
69 int __res1, __res2;
70
71 __asm__ __volatile__ (
72 "1:"
73 "%2 = B[%0++] (Z);" /* get *cs */
74 "%3 = B[%1++] (Z);" /* get *ct */
75 "CC = %2 == %3;" /* compare a byte */
76 "if ! cc jump 2f;" /* not equal, break out */
77 "CC = %2;" /* at end of cs? */
78 "if cc jump 1b (bp);" /* no, keep going */
79 "jump.s 3f;" /* strings are equal */
80 "2:"
81 "%2 = %2 - %3;" /* *cs - *ct */
82 "3:"
83 : "+&a" (cs), "+&a" (ct), "=&d" (__res1), "=&d" (__res2)
84 :
85 : "memory", "CC");
86
87 return __res1;
88}
89
90#define __HAVE_ARCH_STRNCMP
91extern inline int strncmp(const char *cs, const char *ct, size_t count)
92{
93 /* need to use int's here so the char's in the assembly don't get
94 * sign extended incorrectly when we don't want them to be
95 */
96 int __res1, __res2;
97
98 if (!count)
99 return 0;
100
101 __asm__ __volatile__ (
102 "1:"
103 "%3 = B[%0++] (Z);" /* get *cs */
104 "%4 = B[%1++] (Z);" /* get *ct */
105 "CC = %3 == %4;" /* compare a byte */
106 "if ! cc jump 3f;" /* not equal, break out */
107 "CC = %3;" /* at end of cs? */
108 "if ! cc jump 4f;" /* yes, all done */
109 "%2 += -1;" /* no, adjust count */
110 "CC = %2 == 0;"
111 "if ! cc jump 1b;" /* more to do, keep going */
112 "2:"
113 "%3 = 0;" /* strings are equal */
114 "jump.s 4f;"
115 "3:"
116 "%3 = %3 - %4;" /* *cs - *ct */
117 "4:"
118 : "+&a" (cs), "+&a" (ct), "+&da" (count), "=&d" (__res1), "=&d" (__res2)
119 :
120 : "memory", "CC");
121
122 return __res1;
123}
124
125#define __HAVE_ARCH_MEMSET
126extern void *memset(void *s, int c, size_t count);
127#define __HAVE_ARCH_MEMCPY
128extern void *memcpy(void *d, const void *s, size_t count);
129#define __HAVE_ARCH_MEMCMP
130extern int memcmp(const void *, const void *, __kernel_size_t);
131#define __HAVE_ARCH_MEMCHR
132extern void *memchr(const void *s, int c, size_t n);
133#define __HAVE_ARCH_MEMMOVE
134extern void *memmove(void *dest, const void *src, size_t count);
135
136#endif /*__KERNEL__*/
137#endif /* _BLACKFIN_STRING_H_ */
diff --git a/arch/blackfin/include/asm/system.h b/arch/blackfin/include/asm/system.h
new file mode 100644
index 000000000000..8f1627d8bf09
--- /dev/null
+++ b/arch/blackfin/include/asm/system.h
@@ -0,0 +1,221 @@
1/*
2 * File: include/asm/system.h
3 * Based on:
4 * Author: Tony Kou (tonyko@lineo.ca)
5 * Copyright (c) 2002 Arcturus Networks Inc.
6 * (www.arcturusnetworks.com)
7 * Copyright (c) 2003 Metrowerks (www.metrowerks.com)
8 * Copyright (c) 2004 Analog Device Inc.
9 * Created: 25Jan2001 - Tony Kou
10 * Description: system.h include file
11 *
12 * Modified: 22Sep2006 - Robin Getz
13 * - move include blackfin.h down, so I can get access to
14 * irq functions in other include files.
15 *
16 * Bugs: Enter bugs at http://blackfin.uclinux.org/
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2, or (at your option)
21 * any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; see the file COPYING.
30 * If not, write to the Free Software Foundation,
31 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
32 */
33
34#ifndef _BLACKFIN_SYSTEM_H
35#define _BLACKFIN_SYSTEM_H
36
37#include <linux/linkage.h>
38#include <linux/compiler.h>
39#include <mach/anomaly.h>
40
41/*
42 * Interrupt configuring macros.
43 */
44
45extern unsigned long irq_flags;
46
47#define local_irq_enable() \
48 __asm__ __volatile__( \
49 "sti %0;" \
50 : \
51 : "d" (irq_flags) \
52 )
53
54#define local_irq_disable() \
55 do { \
56 int __tmp_dummy; \
57 __asm__ __volatile__( \
58 "cli %0;" \
59 : "=d" (__tmp_dummy) \
60 ); \
61 } while (0)
62
63#if ANOMALY_05000244 && defined(CONFIG_BFIN_ICACHE)
64# define NOP_PAD_ANOMALY_05000244 "nop; nop;"
65#else
66# define NOP_PAD_ANOMALY_05000244
67#endif
68
69#define idle_with_irq_disabled() \
70 __asm__ __volatile__( \
71 NOP_PAD_ANOMALY_05000244 \
72 ".align 8;" \
73 "sti %0;" \
74 "idle;" \
75 : \
76 : "d" (irq_flags) \
77 )
78
79#ifdef CONFIG_DEBUG_HWERR
80# define __save_and_cli(x) \
81 __asm__ __volatile__( \
82 "cli %0;" \
83 "sti %1;" \
84 : "=&d" (x) \
85 : "d" (0x3F) \
86 )
87#else
88# define __save_and_cli(x) \
89 __asm__ __volatile__( \
90 "cli %0;" \
91 : "=&d" (x) \
92 )
93#endif
94
95#define local_save_flags(x) \
96 __asm__ __volatile__( \
97 "cli %0;" \
98 "sti %0;" \
99 : "=d" (x) \
100 )
101
102#ifdef CONFIG_DEBUG_HWERR
103#define irqs_enabled_from_flags(x) (((x) & ~0x3f) != 0)
104#else
105#define irqs_enabled_from_flags(x) ((x) != 0x1f)
106#endif
107
108#define local_irq_restore(x) \
109 do { \
110 if (irqs_enabled_from_flags(x)) \
111 local_irq_enable(); \
112 } while (0)
113
114/* For spinlocks etc */
115#define local_irq_save(x) __save_and_cli(x)
116
117#define irqs_disabled() \
118({ \
119 unsigned long flags; \
120 local_save_flags(flags); \
121 !irqs_enabled_from_flags(flags); \
122})
123
124/*
125 * Force strict CPU ordering.
126 */
127#define nop() asm volatile ("nop;\n\t"::)
128#define mb() asm volatile ("" : : :"memory")
129#define rmb() asm volatile ("" : : :"memory")
130#define wmb() asm volatile ("" : : :"memory")
131#define set_mb(var, value) do { (void) xchg(&var, value); } while (0)
132
133#define read_barrier_depends() do { } while(0)
134
135#ifdef CONFIG_SMP
136#define smp_mb() mb()
137#define smp_rmb() rmb()
138#define smp_wmb() wmb()
139#define smp_read_barrier_depends() read_barrier_depends()
140#else
141#define smp_mb() barrier()
142#define smp_rmb() barrier()
143#define smp_wmb() barrier()
144#define smp_read_barrier_depends() do { } while(0)
145#endif
146
147#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
148
149struct __xchg_dummy {
150 unsigned long a[100];
151};
152#define __xg(x) ((volatile struct __xchg_dummy *)(x))
153
154static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
155 int size)
156{
157 unsigned long tmp = 0;
158 unsigned long flags = 0;
159
160 local_irq_save(flags);
161
162 switch (size) {
163 case 1:
164 __asm__ __volatile__
165 ("%0 = b%2 (z);\n\t"
166 "b%2 = %1;\n\t"
167 : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
168 break;
169 case 2:
170 __asm__ __volatile__
171 ("%0 = w%2 (z);\n\t"
172 "w%2 = %1;\n\t"
173 : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
174 break;
175 case 4:
176 __asm__ __volatile__
177 ("%0 = %2;\n\t"
178 "%2 = %1;\n\t"
179 : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
180 break;
181 }
182 local_irq_restore(flags);
183 return tmp;
184}
185
186#include <asm-generic/cmpxchg-local.h>
187
188/*
189 * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
190 * them available.
191 */
192#define cmpxchg_local(ptr, o, n) \
193 ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
194 (unsigned long)(n), sizeof(*(ptr))))
195#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
196
197#ifndef CONFIG_SMP
198#include <asm-generic/cmpxchg.h>
199#endif
200
201#define prepare_to_switch() do { } while(0)
202
203/*
204 * switch_to(n) should switch tasks to task ptr, first checking that
205 * ptr isn't the current task, in which case it does nothing.
206 */
207
208#include <asm/blackfin.h>
209
210asmlinkage struct task_struct *resume(struct task_struct *prev, struct task_struct *next);
211
212#define switch_to(prev,next,last) \
213do { \
214 memcpy (&task_thread_info(prev)->l1_task_info, L1_SCRATCH_TASK_INFO, \
215 sizeof *L1_SCRATCH_TASK_INFO); \
216 memcpy (L1_SCRATCH_TASK_INFO, &task_thread_info(next)->l1_task_info, \
217 sizeof *L1_SCRATCH_TASK_INFO); \
218 (last) = resume (prev, next); \
219} while (0)
220
221#endif /* _BLACKFIN_SYSTEM_H */
diff --git a/arch/blackfin/include/asm/termbits.h b/arch/blackfin/include/asm/termbits.h
new file mode 100644
index 000000000000..f37feb7cf895
--- /dev/null
+++ b/arch/blackfin/include/asm/termbits.h
@@ -0,0 +1,198 @@
1#ifndef __ARCH_BFIN_TERMBITS_H__
2#define __ARCH_BFIN_TERMBITS_H__
3
4#include <linux/posix_types.h>
5
6typedef unsigned char cc_t;
7typedef unsigned int speed_t;
8typedef unsigned int tcflag_t;
9
10#define NCCS 19
11struct termios {
12 tcflag_t c_iflag; /* input mode flags */
13 tcflag_t c_oflag; /* output mode flags */
14 tcflag_t c_cflag; /* control mode flags */
15 tcflag_t c_lflag; /* local mode flags */
16 cc_t c_line; /* line discipline */
17 cc_t c_cc[NCCS]; /* control characters */
18};
19
20struct termios2 {
21 tcflag_t c_iflag; /* input mode flags */
22 tcflag_t c_oflag; /* output mode flags */
23 tcflag_t c_cflag; /* control mode flags */
24 tcflag_t c_lflag; /* local mode flags */
25 cc_t c_line; /* line discipline */
26 cc_t c_cc[NCCS]; /* control characters */
27 speed_t c_ispeed; /* input speed */
28 speed_t c_ospeed; /* output speed */
29};
30
31struct ktermios {
32 tcflag_t c_iflag; /* input mode flags */
33 tcflag_t c_oflag; /* output mode flags */
34 tcflag_t c_cflag; /* control mode flags */
35 tcflag_t c_lflag; /* local mode flags */
36 cc_t c_line; /* line discipline */
37 cc_t c_cc[NCCS]; /* control characters */
38 speed_t c_ispeed; /* input speed */
39 speed_t c_ospeed; /* output speed */
40};
41
42/* c_cc characters */
43#define VINTR 0
44#define VQUIT 1
45#define VERASE 2
46#define VKILL 3
47#define VEOF 4
48#define VTIME 5
49#define VMIN 6
50#define VSWTC 7
51#define VSTART 8
52#define VSTOP 9
53#define VSUSP 10
54#define VEOL 11
55#define VREPRINT 12
56#define VDISCARD 13
57#define VWERASE 14
58#define VLNEXT 15
59#define VEOL2 16
60
61/* c_iflag bits */
62#define IGNBRK 0000001
63#define BRKINT 0000002
64#define IGNPAR 0000004
65#define PARMRK 0000010
66#define INPCK 0000020
67#define ISTRIP 0000040
68#define INLCR 0000100
69#define IGNCR 0000200
70#define ICRNL 0000400
71#define IUCLC 0001000
72#define IXON 0002000
73#define IXANY 0004000
74#define IXOFF 0010000
75#define IMAXBEL 0020000
76#define IUTF8 0040000
77
78/* c_oflag bits */
79#define OPOST 0000001
80#define OLCUC 0000002
81#define ONLCR 0000004
82#define OCRNL 0000010
83#define ONOCR 0000020
84#define ONLRET 0000040
85#define OFILL 0000100
86#define OFDEL 0000200
87#define NLDLY 0000400
88#define NL0 0000000
89#define NL1 0000400
90#define CRDLY 0003000
91#define CR0 0000000
92#define CR1 0001000
93#define CR2 0002000
94#define CR3 0003000
95#define TABDLY 0014000
96#define TAB0 0000000
97#define TAB1 0004000
98#define TAB2 0010000
99#define TAB3 0014000
100#define XTABS 0014000
101#define BSDLY 0020000
102#define BS0 0000000
103#define BS1 0020000
104#define VTDLY 0040000
105#define VT0 0000000
106#define VT1 0040000
107#define FFDLY 0100000
108#define FF0 0000000
109#define FF1 0100000
110
111/* c_cflag bit meaning */
112#define CBAUD 0010017
113#define B0 0000000 /* hang up */
114#define B50 0000001
115#define B75 0000002
116#define B110 0000003
117#define B134 0000004
118#define B150 0000005
119#define B200 0000006
120#define B300 0000007
121#define B600 0000010
122#define B1200 0000011
123#define B1800 0000012
124#define B2400 0000013
125#define B4800 0000014
126#define B9600 0000015
127#define B19200 0000016
128#define B38400 0000017
129#define EXTA B19200
130#define EXTB B38400
131#define CSIZE 0000060
132#define CS5 0000000
133#define CS6 0000020
134#define CS7 0000040
135#define CS8 0000060
136#define CSTOPB 0000100
137#define CREAD 0000200
138#define PARENB 0000400
139#define PARODD 0001000
140#define HUPCL 0002000
141#define CLOCAL 0004000
142#define CBAUDEX 0010000
143#define BOTHER 0010000
144#define B57600 0010001
145#define B115200 0010002
146#define B230400 0010003
147#define B460800 0010004
148#define B500000 0010005
149#define B576000 0010006
150#define B921600 0010007
151#define B1000000 0010010
152#define B1152000 0010011
153#define B1500000 0010012
154#define B2000000 0010013
155#define B2500000 0010014
156#define B3000000 0010015
157#define B3500000 0010016
158#define B4000000 0010017
159#define CIBAUD 002003600000 /* input baud rate */
160#define CMSPAR 010000000000 /* mark or space (stick) parity */
161#define CRTSCTS 020000000000 /* flow control */
162
163#define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */
164
165/* c_lflag bits */
166#define ISIG 0000001
167#define ICANON 0000002
168#define XCASE 0000004
169#define ECHO 0000010
170#define ECHOE 0000020
171#define ECHOK 0000040
172#define ECHONL 0000100
173#define NOFLSH 0000200
174#define TOSTOP 0000400
175#define ECHOCTL 0001000
176#define ECHOPRT 0002000
177#define ECHOKE 0004000
178#define FLUSHO 0010000
179#define PENDIN 0040000
180#define IEXTEN 0100000
181
182/* tcflow() and TCXONC use these */
183#define TCOOFF 0
184#define TCOON 1
185#define TCIOFF 2
186#define TCION 3
187
188/* tcflush() and TCFLSH use these */
189#define TCIFLUSH 0
190#define TCOFLUSH 1
191#define TCIOFLUSH 2
192
193/* tcsetattr uses these */
194#define TCSANOW 0
195#define TCSADRAIN 1
196#define TCSAFLUSH 2
197
198#endif /* __ARCH_BFIN_TERMBITS_H__ */
diff --git a/arch/blackfin/include/asm/termios.h b/arch/blackfin/include/asm/termios.h
new file mode 100644
index 000000000000..d50d063c605a
--- /dev/null
+++ b/arch/blackfin/include/asm/termios.h
@@ -0,0 +1,94 @@
1#ifndef __BFIN_TERMIOS_H__
2#define __BFIN_TERMIOS_H__
3
4#include <asm/termbits.h>
5#include <asm/ioctls.h>
6
7struct winsize {
8 unsigned short ws_row;
9 unsigned short ws_col;
10 unsigned short ws_xpixel;
11 unsigned short ws_ypixel;
12};
13
14#define NCC 8
15struct termio {
16 unsigned short c_iflag; /* input mode flags */
17 unsigned short c_oflag; /* output mode flags */
18 unsigned short c_cflag; /* control mode flags */
19 unsigned short c_lflag; /* local mode flags */
20 unsigned char c_line; /* line discipline */
21 unsigned char c_cc[NCC]; /* control characters */
22};
23
24/* modem lines */
25#define TIOCM_LE 0x001
26#define TIOCM_DTR 0x002
27#define TIOCM_RTS 0x004
28#define TIOCM_ST 0x008
29#define TIOCM_SR 0x010
30#define TIOCM_CTS 0x020
31#define TIOCM_CAR 0x040
32#define TIOCM_RNG 0x080
33#define TIOCM_DSR 0x100
34#define TIOCM_CD TIOCM_CAR
35#define TIOCM_RI TIOCM_RNG
36#define TIOCM_OUT1 0x2000
37#define TIOCM_OUT2 0x4000
38#define TIOCM_LOOP 0x8000
39
40/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
41
42#ifdef __KERNEL__
43
44/* intr=^C quit=^\ erase=del kill=^U
45 eof=^D vtime=\0 vmin=\1 sxtc=\0
46 start=^Q stop=^S susp=^Z eol=\0
47 reprint=^R discard=^U werase=^W lnext=^V
48 eol2=\0
49*/
50#define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0"
51
52/*
53 * Translate a "termio" structure into a "termios". Ugh.
54 */
55#define SET_LOW_TERMIOS_BITS(termios, termio, x) { \
56 unsigned short __tmp; \
57 get_user(__tmp,&(termio)->x); \
58 *(unsigned short *) &(termios)->x = __tmp; \
59}
60
61#define user_termio_to_kernel_termios(termios, termio) \
62({ \
63 SET_LOW_TERMIOS_BITS(termios, termio, c_iflag); \
64 SET_LOW_TERMIOS_BITS(termios, termio, c_oflag); \
65 SET_LOW_TERMIOS_BITS(termios, termio, c_cflag); \
66 SET_LOW_TERMIOS_BITS(termios, termio, c_lflag); \
67 copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \
68})
69
70/*
71 * Translate a "termios" structure into a "termio". Ugh.
72 */
73#define kernel_termios_to_user_termio(termio, termios) \
74({ \
75 put_user((termios)->c_iflag, &(termio)->c_iflag); \
76 put_user((termios)->c_oflag, &(termio)->c_oflag); \
77 put_user((termios)->c_cflag, &(termio)->c_cflag); \
78 put_user((termios)->c_lflag, &(termio)->c_lflag); \
79 put_user((termios)->c_line, &(termio)->c_line); \
80 copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \
81})
82
83#define user_termios_to_kernel_termios(k, u) \
84 copy_from_user(k, u, sizeof(struct termios2))
85#define kernel_termios_to_user_termios(u, k) \
86 copy_to_user(u, k, sizeof(struct termios2))
87#define user_termios_to_kernel_termios_1(k, u) \
88 copy_from_user(k, u, sizeof(struct termios))
89#define kernel_termios_to_user_termios_1(u, k) \
90 copy_to_user(u, k, sizeof(struct termios))
91
92#endif /* __KERNEL__ */
93
94#endif /* __BFIN_TERMIOS_H__ */
diff --git a/arch/blackfin/include/asm/thread_info.h b/arch/blackfin/include/asm/thread_info.h
new file mode 100644
index 000000000000..642769329d12
--- /dev/null
+++ b/arch/blackfin/include/asm/thread_info.h
@@ -0,0 +1,135 @@
1/*
2 * File: include/asm-blackfin/thread_info.h
3 * Based on: include/asm-m68knommu/thread_info.h
4 * Author: LG Soft India
5 * Copyright (C) 2004-2005 Analog Devices Inc.
6 * Created: Tue Sep 21 2004
7 * Description: Blackfin low-level thread information
8 * Modified:
9 * Bugs: Enter bugs at http://blackfin.uclinux.org/
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING.
23 * If not, write to the Free Software Foundation,
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
25 */
26
27#ifndef _ASM_THREAD_INFO_H
28#define _ASM_THREAD_INFO_H
29
30#include <asm/page.h>
31#include <asm/entry.h>
32#include <asm/l1layout.h>
33#include <linux/compiler.h>
34
35#ifdef __KERNEL__
36
37/* Thread Align Mask to reach to the top of the stack
38 * for any process
39 */
40#define ALIGN_PAGE_MASK 0xffffe000
41
42/*
43 * Size of kernel stack for each process. This must be a power of 2...
44 */
45#define THREAD_SIZE_ORDER 1
46#define THREAD_SIZE 8192 /* 2 pages */
47
48#ifndef __ASSEMBLY__
49
50typedef unsigned long mm_segment_t;
51
52/*
53 * low level task data.
54 * If you change this, change the TI_* offsets below to match.
55 */
56
57struct thread_info {
58 struct task_struct *task; /* main task structure */
59 struct exec_domain *exec_domain; /* execution domain */
60 unsigned long flags; /* low level flags */
61 int cpu; /* cpu we're on */
62 int preempt_count; /* 0 => preemptable, <0 => BUG */
63 mm_segment_t addr_limit; /* address limit */
64 struct restart_block restart_block;
65 struct l1_scratch_task_info l1_task_info;
66};
67
68/*
69 * macros/functions for gaining access to the thread information structure
70 */
71#define INIT_THREAD_INFO(tsk) \
72{ \
73 .task = &tsk, \
74 .exec_domain = &default_exec_domain, \
75 .flags = 0, \
76 .cpu = 0, \
77 .preempt_count = 1, \
78 .restart_block = { \
79 .fn = do_no_restart_syscall, \
80 }, \
81}
82#define init_thread_info (init_thread_union.thread_info)
83#define init_stack (init_thread_union.stack)
84
85/* Given a task stack pointer, you can find its corresponding
86 * thread_info structure just by masking it to the THREAD_SIZE
87 * boundary (currently 8K as you can see above).
88 */
89__attribute_const__
90static inline struct thread_info *current_thread_info(void)
91{
92 struct thread_info *ti;
93 __asm__("%0 = sp;": "=&d"(ti):
94 );
95 return (struct thread_info *)((long)ti & ~((long)THREAD_SIZE-1));
96}
97
98#endif /* __ASSEMBLY__ */
99
100/*
101 * Offsets in thread_info structure, used in assembly code
102 */
103#define TI_TASK 0
104#define TI_EXECDOMAIN 4
105#define TI_FLAGS 8
106#define TI_CPU 12
107#define TI_PREEMPT 16
108
109#define PREEMPT_ACTIVE 0x4000000
110
111/*
112 * thread information flag bit numbers
113 */
114#define TIF_SYSCALL_TRACE 0 /* syscall trace active */
115#define TIF_SIGPENDING 1 /* signal pending */
116#define TIF_NEED_RESCHED 2 /* rescheduling necessary */
117#define TIF_POLLING_NRFLAG 3 /* true if poll_idle() is polling
118 TIF_NEED_RESCHED */
119#define TIF_MEMDIE 4
120#define TIF_RESTORE_SIGMASK 5 /* restore signal mask in do_signal() */
121#define TIF_FREEZE 6 /* is freezing for suspend */
122
123/* as above, but as bit values */
124#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
125#define _TIF_SIGPENDING (1<<TIF_SIGPENDING)
126#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED)
127#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG)
128#define _TIF_RESTORE_SIGMASK (1<<TIF_RESTORE_SIGMASK)
129#define _TIF_FREEZE (1<<TIF_FREEZE)
130
131#define _TIF_WORK_MASK 0x0000FFFE /* work to do on interrupt/exception return */
132
133#endif /* __KERNEL__ */
134
135#endif /* _ASM_THREAD_INFO_H */
diff --git a/arch/blackfin/include/asm/time.h b/arch/blackfin/include/asm/time.h
new file mode 100644
index 000000000000..ddc43ce38533
--- /dev/null
+++ b/arch/blackfin/include/asm/time.h
@@ -0,0 +1,40 @@
1/*
2 * asm-blackfin/time.h:
3 *
4 * Copyright 2004-2008 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef _ASM_BLACKFIN_TIME_H
10#define _ASM_BLACKFIN_TIME_H
11
12/*
13 * The way that the Blackfin core timer works is:
14 * - CCLK is divided by a programmable 8-bit pre-scaler (TSCALE)
15 * - Every time TSCALE ticks, a 32bit is counted down (TCOUNT)
16 *
17 * If you take the fastest clock (1ns, or 1GHz to make the math work easier)
18 * 10ms is 10,000,000 clock ticks, which fits easy into a 32-bit counter
19 * (32 bit counter is 4,294,967,296ns or 4.2 seconds) so, we don't need
20 * to use TSCALE, and program it to zero (which is pass CCLK through).
21 * If you feel like using it, try to keep HZ * TIMESCALE to some
22 * value that divides easy (like power of 2).
23 */
24
25#ifndef CONFIG_CPU_FREQ
26#define TIME_SCALE 1
27#define __bfin_cycles_off (0)
28#define __bfin_cycles_mod (0)
29#else
30/*
31 * Blackfin CPU frequency scaling supports max Core Clock 1, 1/2 and 1/4 .
32 * Whenever we change the Core Clock frequency changes we immediately
33 * adjust the Core Timer Presale Register. This way we don't lose time.
34 */
35#define TIME_SCALE 4
36extern unsigned long long __bfin_cycles_off;
37extern unsigned int __bfin_cycles_mod;
38#endif
39
40#endif
diff --git a/arch/blackfin/include/asm/timex.h b/arch/blackfin/include/asm/timex.h
new file mode 100644
index 000000000000..22b0806161bb
--- /dev/null
+++ b/arch/blackfin/include/asm/timex.h
@@ -0,0 +1,23 @@
1/*
2 * asm-blackfin/timex.h: cpu cycles!
3 *
4 * Copyright 2004-2008 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef _ASM_BLACKFIN_TIMEX_H
10#define _ASM_BLACKFIN_TIMEX_H
11
12#define CLOCK_TICK_RATE 1000000 /* Underlying HZ */
13
14typedef unsigned long long cycles_t;
15
16static inline cycles_t get_cycles(void)
17{
18 unsigned long tmp, tmp2;
19 __asm__("%0 = cycles; %1 = cycles2;" : "=d"(tmp), "=d"(tmp2));
20 return tmp | ((cycles_t)tmp2 << 32);
21}
22
23#endif
diff --git a/arch/blackfin/include/asm/tlb.h b/arch/blackfin/include/asm/tlb.h
new file mode 100644
index 000000000000..89a12ee916d8
--- /dev/null
+++ b/arch/blackfin/include/asm/tlb.h
@@ -0,0 +1,16 @@
1#ifndef _BLACKFIN_TLB_H
2#define _BLACKFIN_TLB_H
3
4#define tlb_start_vma(tlb, vma) do { } while (0)
5#define tlb_end_vma(tlb, vma) do { } while (0)
6#define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0)
7
8/*
9 * .. because we flush the whole mm when it
10 * fills up.
11 */
12#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
13
14#include <asm-generic/tlb.h>
15
16#endif /* _BLACKFIN_TLB_H */
diff --git a/arch/blackfin/include/asm/tlbflush.h b/arch/blackfin/include/asm/tlbflush.h
new file mode 100644
index 000000000000..277b400924b8
--- /dev/null
+++ b/arch/blackfin/include/asm/tlbflush.h
@@ -0,0 +1,56 @@
1#ifndef _BLACKFIN_TLBFLUSH_H
2#define _BLACKFIN_TLBFLUSH_H
3
4/*
5 * Copyright (C) 2000 Lineo, David McCullough <davidm@uclinux.org>
6 * Copyright (C) 2000-2002, Greg Ungerer <gerg@snapgear.com>
7 */
8
9#include <asm/setup.h>
10
11/*
12 * flush all user-space atc entries.
13 */
14static inline void __flush_tlb(void)
15{
16 BUG();
17}
18
19static inline void __flush_tlb_one(unsigned long addr)
20{
21 BUG();
22}
23
24#define flush_tlb() __flush_tlb()
25
26/*
27 * flush all atc entries (both kernel and user-space entries).
28 */
29static inline void flush_tlb_all(void)
30{
31 BUG();
32}
33
34static inline void flush_tlb_mm(struct mm_struct *mm)
35{
36 BUG();
37}
38
39static inline void flush_tlb_page(struct vm_area_struct *vma,
40 unsigned long addr)
41{
42 BUG();
43}
44
45static inline void flush_tlb_range(struct mm_struct *mm,
46 unsigned long start, unsigned long end)
47{
48 BUG();
49}
50
51static inline void flush_tlb_kernel_page(unsigned long addr)
52{
53 BUG();
54}
55
56#endif
diff --git a/arch/blackfin/include/asm/topology.h b/arch/blackfin/include/asm/topology.h
new file mode 100644
index 000000000000..acee23987897
--- /dev/null
+++ b/arch/blackfin/include/asm/topology.h
@@ -0,0 +1,6 @@
1#ifndef _ASM_BLACKFIN_TOPOLOGY_H
2#define _ASM_BLACKFIN_TOPOLOGY_H
3
4#include <asm-generic/topology.h>
5
6#endif /* _ASM_BLACKFIN_TOPOLOGY_H */
diff --git a/arch/blackfin/include/asm/trace.h b/arch/blackfin/include/asm/trace.h
new file mode 100644
index 000000000000..312b596b9731
--- /dev/null
+++ b/arch/blackfin/include/asm/trace.h
@@ -0,0 +1,94 @@
1/*
2 * Common header file for blackfin family of processors.
3 *
4 */
5
6#ifndef _BLACKFIN_TRACE_
7#define _BLACKFIN_TRACE_
8
9/* Normally, we use ON, but you can't turn on software expansion until
10 * interrupts subsystem is ready
11 */
12
13#define BFIN_TRACE_INIT ((CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION << 4) | 0x03)
14#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
15#define BFIN_TRACE_ON (BFIN_TRACE_INIT | (CONFIG_DEBUG_BFIN_HWTRACE_EXPAND << 2))
16#else
17#define BFIN_TRACE_ON (BFIN_TRACE_INIT)
18#endif
19
20#ifndef __ASSEMBLY__
21extern unsigned long trace_buff_offset;
22extern unsigned long software_trace_buff[];
23
24/* Trace Macros for C files */
25
26#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
27
28#define trace_buffer_save(x) \
29 do { \
30 (x) = bfin_read_TBUFCTL(); \
31 bfin_write_TBUFCTL((x) & ~TBUFEN); \
32 } while (0)
33
34#define trace_buffer_restore(x) \
35 do { \
36 bfin_write_TBUFCTL((x)); \
37 } while (0)
38#else /* DEBUG_BFIN_HWTRACE_ON */
39
40#define trace_buffer_save(x)
41#define trace_buffer_restore(x)
42#endif /* CONFIG_DEBUG_BFIN_HWTRACE_ON */
43
44#else
45/* Trace Macros for Assembly files */
46
47#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
48
49#define trace_buffer_stop(preg, dreg) \
50 preg.L = LO(TBUFCTL); \
51 preg.H = HI(TBUFCTL); \
52 dreg = 0x1; \
53 [preg] = dreg;
54
55#define trace_buffer_init(preg, dreg) \
56 preg.L = LO(TBUFCTL); \
57 preg.H = HI(TBUFCTL); \
58 dreg = BFIN_TRACE_INIT; \
59 [preg] = dreg;
60
61#define trace_buffer_save(preg, dreg) \
62 preg.L = LO(TBUFCTL); \
63 preg.H = HI(TBUFCTL); \
64 dreg = [preg]; \
65 [--sp] = dreg; \
66 dreg = 0x1; \
67 [preg] = dreg;
68
69#define trace_buffer_restore(preg, dreg) \
70 preg.L = LO(TBUFCTL); \
71 preg.H = HI(TBUFCTL); \
72 dreg = [sp++]; \
73 [preg] = dreg;
74
75#else /* CONFIG_DEBUG_BFIN_HWTRACE_ON */
76
77#define trace_buffer_stop(preg, dreg)
78#define trace_buffer_init(preg, dreg)
79#define trace_buffer_save(preg, dreg)
80#define trace_buffer_restore(preg, dreg)
81
82#endif /* CONFIG_DEBUG_BFIN_HWTRACE_ON */
83
84#ifdef CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE
85# define DEBUG_HWTRACE_SAVE(preg, dreg) trace_buffer_save(preg, dreg)
86# define DEBUG_HWTRACE_RESTORE(preg, dreg) trace_buffer_restore(preg, dreg)
87#else
88# define DEBUG_HWTRACE_SAVE(preg, dreg)
89# define DEBUG_HWTRACE_RESTORE(preg, dreg)
90#endif
91
92#endif /* __ASSEMBLY__ */
93
94#endif /* _BLACKFIN_TRACE_ */
diff --git a/arch/blackfin/include/asm/traps.h b/arch/blackfin/include/asm/traps.h
new file mode 100644
index 000000000000..f0e5f940d9ca
--- /dev/null
+++ b/arch/blackfin/include/asm/traps.h
@@ -0,0 +1,131 @@
1/*
2 * linux/include/asm/traps.h
3 *
4 * Copyright (C) 1993 Hamish Macdonald
5 *
6 * Lineo, Inc Jul 2001 Tony Kou
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file COPYING in the main directory of this archive
10 * for more details.
11 */
12
13#ifndef _BFIN_TRAPS_H
14#define _BFIN_TRAPS_H
15
16#define VEC_SYS (0)
17#define VEC_EXCPT01 (1)
18#define VEC_EXCPT02 (2)
19#define VEC_EXCPT03 (3)
20#define VEC_EXCPT04 (4)
21#define VEC_EXCPT05 (5)
22#define VEC_EXCPT06 (6)
23#define VEC_EXCPT07 (7)
24#define VEC_EXCPT08 (8)
25#define VEC_EXCPT09 (9)
26#define VEC_EXCPT10 (10)
27#define VEC_EXCPT11 (11)
28#define VEC_EXCPT12 (12)
29#define VEC_EXCPT13 (13)
30#define VEC_EXCPT14 (14)
31#define VEC_EXCPT15 (15)
32#define VEC_STEP (16)
33#define VEC_OVFLOW (17)
34#define VEC_UNDEF_I (33)
35#define VEC_ILGAL_I (34)
36#define VEC_CPLB_VL (35)
37#define VEC_MISALI_D (36)
38#define VEC_UNCOV (37)
39#define VEC_CPLB_M (38)
40#define VEC_CPLB_MHIT (39)
41#define VEC_WATCH (40)
42#define VEC_ISTRU_VL (41) /*ADSP-BF535 only (MH) */
43#define VEC_MISALI_I (42)
44#define VEC_CPLB_I_VL (43)
45#define VEC_CPLB_I_M (44)
46#define VEC_CPLB_I_MHIT (45)
47#define VEC_ILL_RES (46) /* including unvalid supervisor mode insn */
48/* The hardware reserves (63) for future use - we use it to tell our
49 * normal exception handling code we have a hardware error
50 */
51#define VEC_HWERR (63)
52
53#ifndef __ASSEMBLY__
54
55#define HWC_x2(level) \
56 "System MMR Error\n" \
57 level " - An error occurred due to an invalid access to an System MMR location\n" \
58 level " Possible reason: a 32-bit register is accessed with a 16-bit instruction\n" \
59 level " or a 16-bit register is accessed with a 32-bit instruction.\n"
60#define HWC_x3(level) \
61 "External Memory Addressing Error\n"
62#define HWC_x12(level) \
63 "Performance Monitor Overflow\n"
64#define HWC_x18(level) \
65 "RAISE 5 instruction\n" \
66 level " Software issued a RAISE 5 instruction to invoke the Hardware\n"
67#define HWC_default(level) \
68 "Reserved\n"
69#define EXC_0x03(level) \
70 "Application stack overflow\n" \
71 level " - Please increase the stack size of the application using elf2flt -s option,\n" \
72 level " and/or reduce the stack use of the application.\n"
73#define EXC_0x10(level) \
74 "Single step\n" \
75 level " - When the processor is in single step mode, every instruction\n" \
76 level " generates an exception. Primarily used for debugging.\n"
77#define EXC_0x11(level) \
78 "Exception caused by a trace buffer full condition\n" \
79 level " - The processor takes this exception when the trace\n" \
80 level " buffer overflows (only when enabled by the Trace Unit Control register).\n"
81#define EXC_0x21(level) \
82 "Undefined instruction\n" \
83 level " - May be used to emulate instructions that are not defined for\n" \
84 level " a particular processor implementation.\n"
85#define EXC_0x22(level) \
86 "Illegal instruction combination\n" \
87 level " - See section for multi-issue rules in the ADSP-BF53x Blackfin\n" \
88 level " Processor Instruction Set Reference.\n"
89#define EXC_0x23(level) \
90 "Data access CPLB protection violation\n" \
91 level " - Attempted read or write to Supervisor resource,\n" \
92 level " or illegal data memory access. \n"
93#define EXC_0x24(level) \
94 "Data access misaligned address violation\n" \
95 level " - Attempted misaligned data memory or data cache access.\n"
96#define EXC_0x25(level) \
97 "Unrecoverable event\n" \
98 level " - For example, an exception generated while processing a previous exception.\n"
99#define EXC_0x26(level) \
100 "Data access CPLB miss\n" \
101 level " - Used by the MMU to signal a CPLB miss on a data access.\n"
102#define EXC_0x27(level) \
103 "Data access multiple CPLB hits\n" \
104 level " - More than one CPLB entry matches data fetch address.\n"
105#define EXC_0x28(level) \
106 "Program Sequencer Exception caused by an emulation watchpoint match\n" \
107 level " - There is a watchpoint match, and one of the EMUSW\n" \
108 level " bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n"
109#define EXC_0x2A(level) \
110 "Instruction fetch misaligned address violation\n" \
111 level " - Attempted misaligned instruction cache fetch. On a misaligned instruction fetch\n" \
112 level " exception, the return address provided in RETX is the destination address which is\n" \
113 level " misaligned, rather than the address of the offending instruction.\n"
114#define EXC_0x2B(level) \
115 "CPLB protection violation\n" \
116 level " - Illegal instruction fetch access (memory protection violation).\n"
117#define EXC_0x2C(level) \
118 "Instruction fetch CPLB miss\n" \
119 level " - CPLB miss on an instruction fetch.\n"
120#define EXC_0x2D(level) \
121 "Instruction fetch multiple CPLB hits\n" \
122 level " - More than one CPLB entry matches instruction fetch address.\n"
123#define EXC_0x2E(level) \
124 "Illegal use of supervisor resource\n" \
125 level " - Attempted to use a Supervisor register or instruction from User mode.\n" \
126 level " Supervisor resources are registers and instructions that are reserved\n" \
127 level " for Supervisor use: Supervisor only registers, all MMRs, and Supervisor\n" \
128 level " only instructions.\n"
129
130#endif /* __ASSEMBLY__ */
131#endif /* _BFIN_TRAPS_H */
diff --git a/arch/blackfin/include/asm/types.h b/arch/blackfin/include/asm/types.h
new file mode 100644
index 000000000000..8441cbc2bf9e
--- /dev/null
+++ b/arch/blackfin/include/asm/types.h
@@ -0,0 +1,36 @@
1#ifndef _BFIN_TYPES_H
2#define _BFIN_TYPES_H
3
4/*
5 * This file is never included by application software unless
6 * explicitly requested (e.g., via linux/types.h) in which case the
7 * application is Linux specific so (user-) name space pollution is
8 * not a major issue. However, for interoperability, libraries still
9 * need to be careful to avoid a name clashes.
10 */
11#include <asm-generic/int-ll64.h>
12
13#ifndef __ASSEMBLY__
14
15typedef unsigned short umode_t;
16
17#endif /* __ASSEMBLY__ */
18/*
19 * These aren't exported outside the kernel to avoid name space clashes
20 */
21#ifdef __KERNEL__
22
23#define BITS_PER_LONG 32
24
25#ifndef __ASSEMBLY__
26
27/* Dma addresses are 32-bits wide. */
28
29typedef u32 dma_addr_t;
30typedef u64 dma64_addr_t;
31
32#endif /* __ASSEMBLY__ */
33
34#endif /* __KERNEL__ */
35
36#endif /* _BFIN_TYPES_H */
diff --git a/arch/blackfin/include/asm/uaccess.h b/arch/blackfin/include/asm/uaccess.h
new file mode 100644
index 000000000000..d928b8099056
--- /dev/null
+++ b/arch/blackfin/include/asm/uaccess.h
@@ -0,0 +1,271 @@
1/* Changes made by Lineo Inc. May 2001
2 *
3 * Based on: include/asm-m68knommu/uaccess.h
4 */
5
6#ifndef __BLACKFIN_UACCESS_H
7#define __BLACKFIN_UACCESS_H
8
9/*
10 * User space memory access functions
11 */
12#include <linux/sched.h>
13#include <linux/mm.h>
14#include <linux/string.h>
15
16#include <asm/segment.h>
17#ifdef CONFIG_ACCESS_CHECK
18# include <asm/bfin-global.h>
19#endif
20
21#define get_ds() (KERNEL_DS)
22#define get_fs() (current_thread_info()->addr_limit)
23
24static inline void set_fs(mm_segment_t fs)
25{
26 current_thread_info()->addr_limit = fs;
27}
28
29#define segment_eq(a,b) ((a) == (b))
30
31#define VERIFY_READ 0
32#define VERIFY_WRITE 1
33
34#define access_ok(type, addr, size) _access_ok((unsigned long)(addr), (size))
35
36static inline int is_in_rom(unsigned long addr)
37{
38 /*
39 * What we are really trying to do is determine if addr is
40 * in an allocated kernel memory region. If not then assume
41 * we cannot free it or otherwise de-allocate it. Ideally
42 * we could restrict this to really being in a ROM or flash,
43 * but that would need to be done on a board by board basis,
44 * not globally.
45 */
46 if ((addr < _ramstart) || (addr >= _ramend))
47 return (1);
48
49 /* Default case, not in ROM */
50 return (0);
51}
52
53/*
54 * The fs value determines whether argument validity checking should be
55 * performed or not. If get_fs() == USER_DS, checking is performed, with
56 * get_fs() == KERNEL_DS, checking is bypassed.
57 */
58
59#ifndef CONFIG_ACCESS_CHECK
60static inline int _access_ok(unsigned long addr, unsigned long size) { return 1; }
61#else
62#ifdef CONFIG_ACCESS_OK_L1
63extern int _access_ok(unsigned long addr, unsigned long size)__attribute__((l1_text));
64#else
65extern int _access_ok(unsigned long addr, unsigned long size);
66#endif
67#endif
68
69/*
70 * The exception table consists of pairs of addresses: the first is the
71 * address of an instruction that is allowed to fault, and the second is
72 * the address at which the program should continue. No registers are
73 * modified, so it is entirely up to the continuation code to figure out
74 * what to do.
75 *
76 * All the routines below use bits of fixup code that are out of line
77 * with the main instruction path. This means when everything is well,
78 * we don't even have to jump over them. Further, they do not intrude
79 * on our cache or tlb entries.
80 */
81
82struct exception_table_entry {
83 unsigned long insn, fixup;
84};
85
86/* Returns 0 if exception not found and fixup otherwise. */
87extern unsigned long search_exception_table(unsigned long);
88
89/*
90 * These are the main single-value transfer routines. They automatically
91 * use the right size if we just have the right pointer type.
92 */
93
94#define put_user(x,p) \
95 ({ \
96 int _err = 0; \
97 typeof(*(p)) _x = (x); \
98 typeof(*(p)) *_p = (p); \
99 if (!access_ok(VERIFY_WRITE, _p, sizeof(*(_p)))) {\
100 _err = -EFAULT; \
101 } \
102 else { \
103 switch (sizeof (*(_p))) { \
104 case 1: \
105 __put_user_asm(_x, _p, B); \
106 break; \
107 case 2: \
108 __put_user_asm(_x, _p, W); \
109 break; \
110 case 4: \
111 __put_user_asm(_x, _p, ); \
112 break; \
113 case 8: { \
114 long _xl, _xh; \
115 _xl = ((long *)&_x)[0]; \
116 _xh = ((long *)&_x)[1]; \
117 __put_user_asm(_xl, ((long *)_p)+0, ); \
118 __put_user_asm(_xh, ((long *)_p)+1, ); \
119 } break; \
120 default: \
121 _err = __put_user_bad(); \
122 break; \
123 } \
124 } \
125 _err; \
126 })
127
128#define __put_user(x,p) put_user(x,p)
129static inline int bad_user_access_length(void)
130{
131 panic("bad_user_access_length");
132 return -1;
133}
134
135#define __put_user_bad() (printk(KERN_INFO "put_user_bad %s:%d %s\n",\
136 __FILE__, __LINE__, __func__),\
137 bad_user_access_length(), (-EFAULT))
138
139/*
140 * Tell gcc we read from memory instead of writing: this is because
141 * we do not write to any memory gcc knows about, so there are no
142 * aliasing issues.
143 */
144
145#define __ptr(x) ((unsigned long *)(x))
146
147#define __put_user_asm(x,p,bhw) \
148 __asm__ (#bhw"[%1] = %0;\n\t" \
149 : /* no outputs */ \
150 :"d" (x),"a" (__ptr(p)) : "memory")
151
152#define get_user(x,p) \
153 ({ \
154 int _err = 0; \
155 typeof(*(p)) *_p = (p); \
156 if (!access_ok(VERIFY_READ, _p, sizeof(*(_p)))) { \
157 _err = -EFAULT; \
158 } \
159 else { \
160 switch (sizeof(*(_p))) { \
161 case 1: \
162 __get_user_asm(x, _p, B,(Z)); \
163 break; \
164 case 2: \
165 __get_user_asm(x, _p, W,(Z)); \
166 break; \
167 case 4: \
168 __get_user_asm(x, _p, , ); \
169 break; \
170 case 8: { \
171 unsigned long _xl, _xh; \
172 __get_user_asm(_xl, ((unsigned long *)_p)+0, , ); \
173 __get_user_asm(_xh, ((unsigned long *)_p)+1, , ); \
174 ((unsigned long *)&x)[0] = _xl; \
175 ((unsigned long *)&x)[1] = _xh; \
176 } break; \
177 default: \
178 x = 0; \
179 printk(KERN_INFO "get_user_bad: %s:%d %s\n", \
180 __FILE__, __LINE__, __func__); \
181 _err = __get_user_bad(); \
182 break; \
183 } \
184 } \
185 _err; \
186 })
187
188#define __get_user(x,p) get_user(x,p)
189
190#define __get_user_bad() (bad_user_access_length(), (-EFAULT))
191
192#define __get_user_asm(x,p,bhw,option) \
193 { \
194 unsigned long _tmp; \
195 __asm__ ("%0 =" #bhw "[%1]"#option";\n\t" \
196 : "=d" (_tmp) \
197 : "a" (__ptr(p))); \
198 (x) = (__typeof__(*(p))) _tmp; \
199 }
200
201#define __copy_from_user(to, from, n) copy_from_user(to, from, n)
202#define __copy_to_user(to, from, n) copy_to_user(to, from, n)
203#define __copy_to_user_inatomic __copy_to_user
204#define __copy_from_user_inatomic __copy_from_user
205
206#define copy_to_user_ret(to,from,n,retval) ({ if (copy_to_user(to,from,n))\
207 return retval; })
208
209#define copy_from_user_ret(to,from,n,retval) ({ if (copy_from_user(to,from,n))\
210 return retval; })
211
212static inline long copy_from_user(void *to,
213 const void __user * from, unsigned long n)
214{
215 if (access_ok(VERIFY_READ, from, n))
216 memcpy(to, from, n);
217 else
218 return n;
219 return 0;
220}
221
222static inline long copy_to_user(void *to,
223 const void __user * from, unsigned long n)
224{
225 if (access_ok(VERIFY_WRITE, to, n))
226 memcpy(to, from, n);
227 else
228 return n;
229 return 0;
230}
231
232/*
233 * Copy a null terminated string from userspace.
234 */
235
236static inline long strncpy_from_user(char *dst,
237 const char *src, long count)
238{
239 char *tmp;
240 if (!access_ok(VERIFY_READ, src, 1))
241 return -EFAULT;
242 strncpy(dst, src, count);
243 for (tmp = dst; *tmp && count > 0; tmp++, count--) ;
244 return (tmp - dst);
245}
246
247/*
248 * Return the size of a string (including the ending 0)
249 *
250 * Return 0 on exception, a value greater than N if too long
251 */
252static inline long strnlen_user(const char *src, long n)
253{
254 return (strlen(src) + 1);
255}
256
257#define strlen_user(str) strnlen_user(str, 32767)
258
259/*
260 * Zero Userspace
261 */
262
263static inline unsigned long __clear_user(void *to, unsigned long n)
264{
265 memset(to, 0, n);
266 return 0;
267}
268
269#define clear_user(to, n) __clear_user(to, n)
270
271#endif /* _BLACKFIN_UACCESS_H */
diff --git a/arch/blackfin/include/asm/ucontext.h b/arch/blackfin/include/asm/ucontext.h
new file mode 100644
index 000000000000..4a4e3856beba
--- /dev/null
+++ b/arch/blackfin/include/asm/ucontext.h
@@ -0,0 +1,17 @@
1/** Changes made by Tony Kou Lineo Inc. May 2001
2 *
3 * Based on: include/m68knommu/ucontext.h
4 */
5
6#ifndef _BLACKFIN_UCONTEXT_H
7#define _BLACKFIN_UCONTEXT_H
8
9struct ucontext {
10 unsigned long uc_flags; /* the others are necessary */
11 struct ucontext *uc_link;
12 stack_t uc_stack;
13 struct sigcontext uc_mcontext;
14 sigset_t uc_sigmask; /* mask last for extensibility */
15};
16
17#endif /* _BLACKFIN_UCONTEXT_H */
diff --git a/arch/blackfin/include/asm/unaligned.h b/arch/blackfin/include/asm/unaligned.h
new file mode 100644
index 000000000000..fd8a1d634945
--- /dev/null
+++ b/arch/blackfin/include/asm/unaligned.h
@@ -0,0 +1,11 @@
1#ifndef _ASM_BLACKFIN_UNALIGNED_H
2#define _ASM_BLACKFIN_UNALIGNED_H
3
4#include <linux/unaligned/le_struct.h>
5#include <linux/unaligned/be_byteshift.h>
6#include <linux/unaligned/generic.h>
7
8#define get_unaligned __get_unaligned_le
9#define put_unaligned __put_unaligned_le
10
11#endif /* _ASM_BLACKFIN_UNALIGNED_H */
diff --git a/arch/blackfin/include/asm/unistd.h b/arch/blackfin/include/asm/unistd.h
new file mode 100644
index 000000000000..1e57b636e0bc
--- /dev/null
+++ b/arch/blackfin/include/asm/unistd.h
@@ -0,0 +1,438 @@
1#ifndef __ASM_BFIN_UNISTD_H
2#define __ASM_BFIN_UNISTD_H
3/*
4 * This file contains the system call numbers.
5 */
6#define __NR_restart_syscall 0
7#define __NR_exit 1
8#define __NR_fork 2
9#define __NR_read 3
10#define __NR_write 4
11#define __NR_open 5
12#define __NR_close 6
13 /* 7 __NR_waitpid obsolete */
14#define __NR_creat 8
15#define __NR_link 9
16#define __NR_unlink 10
17#define __NR_execve 11
18#define __NR_chdir 12
19#define __NR_time 13
20#define __NR_mknod 14
21#define __NR_chmod 15
22#define __NR_chown 16
23 /* 17 __NR_break obsolete */
24 /* 18 __NR_oldstat obsolete */
25#define __NR_lseek 19
26#define __NR_getpid 20
27#define __NR_mount 21
28 /* 22 __NR_umount obsolete */
29#define __NR_setuid 23
30#define __NR_getuid 24
31#define __NR_stime 25
32#define __NR_ptrace 26
33#define __NR_alarm 27
34 /* 28 __NR_oldfstat obsolete */
35#define __NR_pause 29
36 /* 30 __NR_utime obsolete */
37 /* 31 __NR_stty obsolete */
38 /* 32 __NR_gtty obsolete */
39#define __NR_access 33
40#define __NR_nice 34
41 /* 35 __NR_ftime obsolete */
42#define __NR_sync 36
43#define __NR_kill 37
44#define __NR_rename 38
45#define __NR_mkdir 39
46#define __NR_rmdir 40
47#define __NR_dup 41
48#define __NR_pipe 42
49#define __NR_times 43
50 /* 44 __NR_prof obsolete */
51#define __NR_brk 45
52#define __NR_setgid 46
53#define __NR_getgid 47
54 /* 48 __NR_signal obsolete */
55#define __NR_geteuid 49
56#define __NR_getegid 50
57#define __NR_acct 51
58#define __NR_umount2 52
59 /* 53 __NR_lock obsolete */
60#define __NR_ioctl 54
61#define __NR_fcntl 55
62 /* 56 __NR_mpx obsolete */
63#define __NR_setpgid 57
64 /* 58 __NR_ulimit obsolete */
65 /* 59 __NR_oldolduname obsolete */
66#define __NR_umask 60
67#define __NR_chroot 61
68#define __NR_ustat 62
69#define __NR_dup2 63
70#define __NR_getppid 64
71#define __NR_getpgrp 65
72#define __NR_setsid 66
73 /* 67 __NR_sigaction obsolete */
74#define __NR_sgetmask 68
75#define __NR_ssetmask 69
76#define __NR_setreuid 70
77#define __NR_setregid 71
78 /* 72 __NR_sigsuspend obsolete */
79 /* 73 __NR_sigpending obsolete */
80#define __NR_sethostname 74
81#define __NR_setrlimit 75
82 /* 76 __NR_old_getrlimit obsolete */
83#define __NR_getrusage 77
84#define __NR_gettimeofday 78
85#define __NR_settimeofday 79
86#define __NR_getgroups 80
87#define __NR_setgroups 81
88 /* 82 __NR_select obsolete */
89#define __NR_symlink 83
90 /* 84 __NR_oldlstat obsolete */
91#define __NR_readlink 85
92 /* 86 __NR_uselib obsolete */
93 /* 87 __NR_swapon obsolete */
94#define __NR_reboot 88
95 /* 89 __NR_readdir obsolete */
96 /* 90 __NR_mmap obsolete */
97#define __NR_munmap 91
98#define __NR_truncate 92
99#define __NR_ftruncate 93
100#define __NR_fchmod 94
101#define __NR_fchown 95
102#define __NR_getpriority 96
103#define __NR_setpriority 97
104 /* 98 __NR_profil obsolete */
105#define __NR_statfs 99
106#define __NR_fstatfs 100
107 /* 101 __NR_ioperm */
108 /* 102 __NR_socketcall obsolete */
109#define __NR_syslog 103
110#define __NR_setitimer 104
111#define __NR_getitimer 105
112#define __NR_stat 106
113#define __NR_lstat 107
114#define __NR_fstat 108
115 /* 109 __NR_olduname obsolete */
116 /* 110 __NR_iopl obsolete */
117#define __NR_vhangup 111
118 /* 112 __NR_idle obsolete */
119 /* 113 __NR_vm86old */
120#define __NR_wait4 114
121 /* 115 __NR_swapoff obsolete */
122#define __NR_sysinfo 116
123 /* 117 __NR_ipc oboslete */
124#define __NR_fsync 118
125 /* 119 __NR_sigreturn obsolete */
126#define __NR_clone 120
127#define __NR_setdomainname 121
128#define __NR_uname 122
129 /* 123 __NR_modify_ldt obsolete */
130#define __NR_adjtimex 124
131#define __NR_mprotect 125
132 /* 126 __NR_sigprocmask obsolete */
133 /* 127 __NR_create_module obsolete */
134#define __NR_init_module 128
135#define __NR_delete_module 129
136 /* 130 __NR_get_kernel_syms obsolete */
137#define __NR_quotactl 131
138#define __NR_getpgid 132
139#define __NR_fchdir 133
140#define __NR_bdflush 134
141 /* 135 was sysfs */
142#define __NR_personality 136
143 /* 137 __NR_afs_syscall */
144#define __NR_setfsuid 138
145#define __NR_setfsgid 139
146#define __NR__llseek 140
147#define __NR_getdents 141
148 /* 142 __NR__newselect obsolete */
149#define __NR_flock 143
150 /* 144 __NR_msync obsolete */
151#define __NR_readv 145
152#define __NR_writev 146
153#define __NR_getsid 147
154#define __NR_fdatasync 148
155#define __NR__sysctl 149
156 /* 150 __NR_mlock */
157 /* 151 __NR_munlock */
158 /* 152 __NR_mlockall */
159 /* 153 __NR_munlockall */
160#define __NR_sched_setparam 154
161#define __NR_sched_getparam 155
162#define __NR_sched_setscheduler 156
163#define __NR_sched_getscheduler 157
164#define __NR_sched_yield 158
165#define __NR_sched_get_priority_max 159
166#define __NR_sched_get_priority_min 160
167#define __NR_sched_rr_get_interval 161
168#define __NR_nanosleep 162
169#define __NR_mremap 163
170#define __NR_setresuid 164
171#define __NR_getresuid 165
172 /* 166 __NR_vm86 */
173 /* 167 __NR_query_module */
174 /* 168 __NR_poll */
175#define __NR_nfsservctl 169
176#define __NR_setresgid 170
177#define __NR_getresgid 171
178#define __NR_prctl 172
179#define __NR_rt_sigreturn 173
180#define __NR_rt_sigaction 174
181#define __NR_rt_sigprocmask 175
182#define __NR_rt_sigpending 176
183#define __NR_rt_sigtimedwait 177
184#define __NR_rt_sigqueueinfo 178
185#define __NR_rt_sigsuspend 179
186#define __NR_pread 180
187#define __NR_pwrite 181
188#define __NR_lchown 182
189#define __NR_getcwd 183
190#define __NR_capget 184
191#define __NR_capset 185
192#define __NR_sigaltstack 186
193#define __NR_sendfile 187
194 /* 188 __NR_getpmsg */
195 /* 189 __NR_putpmsg */
196#define __NR_vfork 190
197#define __NR_getrlimit 191
198#define __NR_mmap2 192
199#define __NR_truncate64 193
200#define __NR_ftruncate64 194
201#define __NR_stat64 195
202#define __NR_lstat64 196
203#define __NR_fstat64 197
204#define __NR_chown32 198
205#define __NR_getuid32 199
206#define __NR_getgid32 200
207#define __NR_geteuid32 201
208#define __NR_getegid32 202
209#define __NR_setreuid32 203
210#define __NR_setregid32 204
211#define __NR_getgroups32 205
212#define __NR_setgroups32 206
213#define __NR_fchown32 207
214#define __NR_setresuid32 208
215#define __NR_getresuid32 209
216#define __NR_setresgid32 210
217#define __NR_getresgid32 211
218#define __NR_lchown32 212
219#define __NR_setuid32 213
220#define __NR_setgid32 214
221#define __NR_setfsuid32 215
222#define __NR_setfsgid32 216
223#define __NR_pivot_root 217
224 /* 218 __NR_mincore */
225 /* 219 __NR_madvise */
226#define __NR_getdents64 220
227#define __NR_fcntl64 221
228 /* 222 reserved for TUX */
229 /* 223 reserved for TUX */
230#define __NR_gettid 224
231#define __NR_readahead 225
232#define __NR_setxattr 226
233#define __NR_lsetxattr 227
234#define __NR_fsetxattr 228
235#define __NR_getxattr 229
236#define __NR_lgetxattr 230
237#define __NR_fgetxattr 231
238#define __NR_listxattr 232
239#define __NR_llistxattr 233
240#define __NR_flistxattr 234
241#define __NR_removexattr 235
242#define __NR_lremovexattr 236
243#define __NR_fremovexattr 237
244#define __NR_tkill 238
245#define __NR_sendfile64 239
246#define __NR_futex 240
247#define __NR_sched_setaffinity 241
248#define __NR_sched_getaffinity 242
249 /* 243 __NR_set_thread_area */
250 /* 244 __NR_get_thread_area */
251#define __NR_io_setup 245
252#define __NR_io_destroy 246
253#define __NR_io_getevents 247
254#define __NR_io_submit 248
255#define __NR_io_cancel 249
256 /* 250 __NR_alloc_hugepages */
257 /* 251 __NR_free_hugepages */
258#define __NR_exit_group 252
259#define __NR_lookup_dcookie 253
260#define __NR_bfin_spinlock 254
261
262#define __NR_epoll_create 255
263#define __NR_epoll_ctl 256
264#define __NR_epoll_wait 257
265 /* 258 __NR_remap_file_pages */
266#define __NR_set_tid_address 259
267#define __NR_timer_create 260
268#define __NR_timer_settime 261
269#define __NR_timer_gettime 262
270#define __NR_timer_getoverrun 263
271#define __NR_timer_delete 264
272#define __NR_clock_settime 265
273#define __NR_clock_gettime 266
274#define __NR_clock_getres 267
275#define __NR_clock_nanosleep 268
276#define __NR_statfs64 269
277#define __NR_fstatfs64 270
278#define __NR_tgkill 271
279#define __NR_utimes 272
280#define __NR_fadvise64_64 273
281 /* 274 __NR_vserver */
282 /* 275 __NR_mbind */
283 /* 276 __NR_get_mempolicy */
284 /* 277 __NR_set_mempolicy */
285#define __NR_mq_open 278
286#define __NR_mq_unlink 279
287#define __NR_mq_timedsend 280
288#define __NR_mq_timedreceive 281
289#define __NR_mq_notify 282
290#define __NR_mq_getsetattr 283
291#define __NR_kexec_load 284
292#define __NR_waitid 285
293#define __NR_add_key 286
294#define __NR_request_key 287
295#define __NR_keyctl 288
296#define __NR_ioprio_set 289
297#define __NR_ioprio_get 290
298#define __NR_inotify_init 291
299#define __NR_inotify_add_watch 292
300#define __NR_inotify_rm_watch 293
301 /* 294 __NR_migrate_pages */
302#define __NR_openat 295
303#define __NR_mkdirat 296
304#define __NR_mknodat 297
305#define __NR_fchownat 298
306#define __NR_futimesat 299
307#define __NR_fstatat64 300
308#define __NR_unlinkat 301
309#define __NR_renameat 302
310#define __NR_linkat 303
311#define __NR_symlinkat 304
312#define __NR_readlinkat 305
313#define __NR_fchmodat 306
314#define __NR_faccessat 307
315#define __NR_pselect6 308
316#define __NR_ppoll 309
317#define __NR_unshare 310
318
319/* Blackfin private syscalls */
320#define __NR_sram_alloc 311
321#define __NR_sram_free 312
322#define __NR_dma_memcpy 313
323
324/* socket syscalls */
325#define __NR_accept 314
326#define __NR_bind 315
327#define __NR_connect 316
328#define __NR_getpeername 317
329#define __NR_getsockname 318
330#define __NR_getsockopt 319
331#define __NR_listen 320
332#define __NR_recv 321
333#define __NR_recvfrom 322
334#define __NR_recvmsg 323
335#define __NR_send 324
336#define __NR_sendmsg 325
337#define __NR_sendto 326
338#define __NR_setsockopt 327
339#define __NR_shutdown 328
340#define __NR_socket 329
341#define __NR_socketpair 330
342
343/* sysv ipc syscalls */
344#define __NR_semctl 331
345#define __NR_semget 332
346#define __NR_semop 333
347#define __NR_msgctl 334
348#define __NR_msgget 335
349#define __NR_msgrcv 336
350#define __NR_msgsnd 337
351#define __NR_shmat 338
352#define __NR_shmctl 339
353#define __NR_shmdt 340
354#define __NR_shmget 341
355
356#define __NR_splice 342
357#define __NR_sync_file_range 343
358#define __NR_tee 344
359#define __NR_vmsplice 345
360
361#define __NR_epoll_pwait 346
362#define __NR_utimensat 347
363#define __NR_signalfd 348
364#define __NR_timerfd_create 349
365#define __NR_eventfd 350
366#define __NR_pread64 351
367#define __NR_pwrite64 352
368#define __NR_fadvise64 353
369#define __NR_set_robust_list 354
370#define __NR_get_robust_list 355
371#define __NR_fallocate 356
372#define __NR_semtimedop 357
373#define __NR_timerfd_settime 358
374#define __NR_timerfd_gettime 359
375#define __NR_signalfd4 360
376#define __NR_eventfd2 361
377#define __NR_epoll_create1 362
378#define __NR_dup3 363
379#define __NR_pipe2 364
380#define __NR_inotify_init1 365
381
382#define __NR_syscall 366
383#define NR_syscalls __NR_syscall
384
385/* Old optional stuff no one actually uses */
386#define __IGNORE_sysfs
387#define __IGNORE_uselib
388
389/* Implement the newer interfaces */
390#define __IGNORE_mmap
391#define __IGNORE_poll
392#define __IGNORE_select
393#define __IGNORE_utime
394
395/* Not relevant on no-mmu */
396#define __IGNORE_swapon
397#define __IGNORE_swapoff
398#define __IGNORE_msync
399#define __IGNORE_mlock
400#define __IGNORE_munlock
401#define __IGNORE_mlockall
402#define __IGNORE_munlockall
403#define __IGNORE_mincore
404#define __IGNORE_madvise
405#define __IGNORE_remap_file_pages
406#define __IGNORE_mbind
407#define __IGNORE_get_mempolicy
408#define __IGNORE_set_mempolicy
409#define __IGNORE_migrate_pages
410#define __IGNORE_move_pages
411#define __IGNORE_getcpu
412
413#ifdef __KERNEL__
414#define __ARCH_WANT_IPC_PARSE_VERSION
415#define __ARCH_WANT_STAT64
416#define __ARCH_WANT_SYS_ALARM
417#define __ARCH_WANT_SYS_GETHOSTNAME
418#define __ARCH_WANT_SYS_PAUSE
419#define __ARCH_WANT_SYS_SGETMASK
420#define __ARCH_WANT_SYS_TIME
421#define __ARCH_WANT_SYS_FADVISE64
422#define __ARCH_WANT_SYS_GETPGRP
423#define __ARCH_WANT_SYS_LLSEEK
424#define __ARCH_WANT_SYS_NICE
425#define __ARCH_WANT_SYS_RT_SIGACTION
426#define __ARCH_WANT_SYS_RT_SIGSUSPEND
427
428/*
429 * "Conditional" syscalls
430 *
431 * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
432 * but it doesn't work on all toolchains, so we just do it by hand
433 */
434#define cond_syscall(x) asm(".weak\t_" #x "\n\t.set\t_" #x ",_sys_ni_syscall");
435
436#endif /* __KERNEL__ */
437
438#endif /* __ASM_BFIN_UNISTD_H */
diff --git a/arch/blackfin/include/asm/user.h b/arch/blackfin/include/asm/user.h
new file mode 100644
index 000000000000..afe6a0e1f7ce
--- /dev/null
+++ b/arch/blackfin/include/asm/user.h
@@ -0,0 +1,89 @@
1#ifndef _BFIN_USER_H
2#define _BFIN_USER_H
3
4/* Changes by Tony Kou Lineo, Inc. July, 2001
5 *
6 * Based include/asm-m68knommu/user.h
7 *
8 */
9
10/* Core file format: The core file is written in such a way that gdb
11 can understand it and provide useful information to the user (under
12 linux we use the 'trad-core' bfd). There are quite a number of
13 obstacles to being able to view the contents of the floating point
14 registers, and until these are solved you will not be able to view the
15 contents of them. Actually, you can read in the core file and look at
16 the contents of the user struct to find out what the floating point
17 registers contain.
18 The actual file contents are as follows:
19 UPAGE: 1 page consisting of a user struct that tells gdb what is present
20 in the file. Directly after this is a copy of the task_struct, which
21 is currently not used by gdb, but it may come in useful at some point.
22 All of the registers are stored as part of the upage. The upage should
23 always be only one page.
24 DATA: The data area is stored. We use current->end_text to
25 current->brk to pick up all of the user variables, plus any memory
26 that may have been malloced. No attempt is made to determine if a page
27 is demand-zero or if a page is totally unused, we just cover the entire
28 range. All of the addresses are rounded in such a way that an integral
29 number of pages is written.
30 STACK: We need the stack information in order to get a meaningful
31 backtrace. We need to write the data from (esp) to
32 current->start_stack, so we round each of these off in order to be able
33 to write an integer number of pages.
34 The minimum core file size is 3 pages, or 12288 bytes.
35*/
36struct user_bfinfp_struct {
37};
38
39/* This is the old layout of "struct pt_regs" as of Linux 1.x, and
40 is still the layout used by user (the new pt_regs doesn't have
41 all registers). */
42struct user_regs_struct {
43 long r0, r1, r2, r3, r4, r5, r6, r7;
44 long p0, p1, p2, p3, p4, p5, usp, fp;
45 long i0, i1, i2, i3;
46 long l0, l1, l2, l3;
47 long b0, b1, b2, b3;
48 long m0, m1, m2, m3;
49 long a0w, a1w;
50 long a0x, a1x;
51 unsigned long rets;
52 unsigned long astat;
53 unsigned long pc;
54 unsigned long orig_p0;
55};
56
57/* When the kernel dumps core, it starts by dumping the user struct -
58 this will be used by gdb to figure out where the data and stack segments
59 are within the file, and what virtual addresses to use. */
60
61struct user {
62/* We start with the registers, to mimic the way that "memory" is returned
63 from the ptrace(3,...) function. */
64
65 struct user_regs_struct regs; /* Where the registers are actually stored */
66
67/* The rest of this junk is to help gdb figure out what goes where */
68 unsigned long int u_tsize; /* Text segment size (pages). */
69 unsigned long int u_dsize; /* Data segment size (pages). */
70 unsigned long int u_ssize; /* Stack segment size (pages). */
71 unsigned long start_code; /* Starting virtual address of text. */
72 unsigned long start_stack; /* Starting virtual address of stack area.
73 This is actually the bottom of the stack,
74 the top of the stack is always found in the
75 esp register. */
76 long int signal; /* Signal that caused the core dump. */
77 int reserved; /* No longer used */
78 unsigned long u_ar0;
79 /* Used by gdb to help find the values for */
80 /* the registers. */
81 unsigned long magic; /* To uniquely identify a core file */
82 char u_comm[32]; /* User command that was responsible */
83};
84#define NBPG PAGE_SIZE
85#define UPAGES 1
86#define HOST_TEXT_START_ADDR (u.start_code)
87#define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG)
88
89#endif
diff --git a/arch/blackfin/kernel/entry.S b/arch/blackfin/kernel/entry.S
index 31bd9bf3efae..faea88ebb2ef 100644
--- a/arch/blackfin/kernel/entry.S
+++ b/arch/blackfin/kernel/entry.S
@@ -32,7 +32,7 @@
32#include <asm/errno.h> 32#include <asm/errno.h>
33#include <asm/asm-offsets.h> 33#include <asm/asm-offsets.h>
34 34
35#include <asm/mach-common/context.S> 35#include <asm/context.S>
36 36
37#ifdef CONFIG_EXCPT_IRQ_SYSC_L1 37#ifdef CONFIG_EXCPT_IRQ_SYSC_L1
38.section .l1.text 38.section .l1.text
diff --git a/arch/blackfin/mach-bf527/head.S b/arch/blackfin/mach-bf527/head.S
index c3334cc5bcb7..28c486191209 100644
--- a/arch/blackfin/mach-bf527/head.S
+++ b/arch/blackfin/mach-bf527/head.S
@@ -31,8 +31,8 @@
31#include <linux/init.h> 31#include <linux/init.h>
32#include <asm/blackfin.h> 32#include <asm/blackfin.h>
33#ifdef CONFIG_BFIN_KERNEL_CLOCK 33#ifdef CONFIG_BFIN_KERNEL_CLOCK
34#include <asm/mach-common/clocks.h> 34#include <asm/clocks.h>
35#include <asm/mach/mem_init.h> 35#include <mach/mem_init.h>
36#endif 36#endif
37 37
38.section .l1.text 38.section .l1.text
diff --git a/arch/blackfin/mach-bf527/include/mach/anomaly.h b/arch/blackfin/mach-bf527/include/mach/anomaly.h
new file mode 100644
index 000000000000..b7b166f4f064
--- /dev/null
+++ b/arch/blackfin/mach-bf527/include/mach/anomaly.h
@@ -0,0 +1,104 @@
1/*
2 * File: include/asm-blackfin/mach-bf527/anomaly.h
3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
4 *
5 * Copyright (C) 2004-2008 Analog Devices Inc.
6 * Licensed under the GPL-2 or later.
7 */
8
9/* This file shoule be up to date with:
10 * - Revision C, 01/25/2008; ADSP-BF527 Blackfin Processor Anomaly List
11 */
12
13#ifndef _MACH_ANOMALY_H_
14#define _MACH_ANOMALY_H_
15
16/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
17#define ANOMALY_05000074 (1)
18/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
19#define ANOMALY_05000119 (1)
20/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
21#define ANOMALY_05000122 (1)
22/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
23#define ANOMALY_05000245 (1)
24/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
25#define ANOMALY_05000265 (1)
26/* New Feature: EMAC TX DMA Word Alignment */
27#define ANOMALY_05000285 (1)
28/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
29#define ANOMALY_05000312 (1)
30/* Incorrect Access of OTP_STATUS During otp_write() Function */
31#define ANOMALY_05000328 (1)
32/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
33#define ANOMALY_05000337 (1)
34/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
35#define ANOMALY_05000341 (1)
36/* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */
37#define ANOMALY_05000342 (1)
38/* USB Calibration Value Is Not Initialized */
39#define ANOMALY_05000346 (1)
40/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
41#define ANOMALY_05000347 (1)
42/* Security Features Are Not Functional */
43#define ANOMALY_05000348 (__SILICON_REVISION__ < 1)
44/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
45#define ANOMALY_05000355 (1)
46/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
47#define ANOMALY_05000357 (1)
48/* Incorrect Revision Number in DSPID Register */
49#define ANOMALY_05000364 (__SILICON_REVISION__ > 0)
50/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
51#define ANOMALY_05000366 (1)
52/* New Feature: Higher Default CCLK Rate */
53#define ANOMALY_05000368 (1)
54/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
55#define ANOMALY_05000371 (1)
56/* Authentication Fails To Initiate */
57#define ANOMALY_05000376 (__SILICON_REVISION__ > 0)
58/* Data Read From L3 Memory by USB DMA May be Corrupted */
59#define ANOMALY_05000380 (1)
60/* USB Full-speed Mode not Fully Tested */
61#define ANOMALY_05000381 (1)
62/* New Feature: Boot from OTP Memory */
63#define ANOMALY_05000385 (1)
64/* New Feature: bfrom_SysControl() Routine */
65#define ANOMALY_05000386 (1)
66/* New Feature: Programmable Preboot Settings */
67#define ANOMALY_05000387 (1)
68/* Reset Vector Must Not Be in SDRAM Memory Space */
69#define ANOMALY_05000389 (1)
70/* New Feature: pTempCurrent Added to ADI_BOOT_DATA Structure */
71#define ANOMALY_05000392 (1)
72/* New Feature: dTempByteCount Value Increased in ADI_BOOT_DATA Structure */
73#define ANOMALY_05000393 (1)
74/* New Feature: Log Buffer Functionality */
75#define ANOMALY_05000394 (1)
76/* New Feature: Hook Routine Functionality */
77#define ANOMALY_05000395 (1)
78/* New Feature: Header Indirect Bit */
79#define ANOMALY_05000396 (1)
80/* New Feature: BK_ONES, BK_ZEROS, and BK_DATECODE Constants */
81#define ANOMALY_05000397 (1)
82/* New Feature: SWRESET, DFRESET and WDRESET Bits Added to SYSCR Register */
83#define ANOMALY_05000398 (1)
84/* New Feature: BCODE_NOBOOT Added to BCODE Field of SYSCR Register */
85#define ANOMALY_05000399 (1)
86/* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */
87#define ANOMALY_05000401 (1)
88
89/* Anomalies that don't exist on this proc */
90#define ANOMALY_05000125 (0)
91#define ANOMALY_05000158 (0)
92#define ANOMALY_05000183 (0)
93#define ANOMALY_05000198 (0)
94#define ANOMALY_05000230 (0)
95#define ANOMALY_05000244 (0)
96#define ANOMALY_05000261 (0)
97#define ANOMALY_05000263 (0)
98#define ANOMALY_05000266 (0)
99#define ANOMALY_05000273 (0)
100#define ANOMALY_05000311 (0)
101#define ANOMALY_05000323 (0)
102#define ANOMALY_05000363 (0)
103
104#endif
diff --git a/arch/blackfin/mach-bf527/include/mach/bf527.h b/arch/blackfin/mach-bf527/include/mach/bf527.h
new file mode 100644
index 000000000000..056eb4b9cd25
--- /dev/null
+++ b/arch/blackfin/mach-bf527/include/mach/bf527.h
@@ -0,0 +1,127 @@
1/*
2 * File: include/asm-blackfin/mach-bf527/bf527.h
3 * Based on: include/asm-blackfin/mach-bf537/bf537.h
4 * Author: Michael Hennerich (michael.hennerich@analog.com)
5 *
6 * Created:
7 * Description: SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF527
8 *
9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#ifndef __MACH_BF527_H__
31#define __MACH_BF527_H__
32
33#define SUPPORTED_REVID 2
34
35#define OFFSET_(x) ((x) & 0x0000FFFF)
36
37/*some misc defines*/
38#define IMASK_IVG15 0x8000
39#define IMASK_IVG14 0x4000
40#define IMASK_IVG13 0x2000
41#define IMASK_IVG12 0x1000
42
43#define IMASK_IVG11 0x0800
44#define IMASK_IVG10 0x0400
45#define IMASK_IVG9 0x0200
46#define IMASK_IVG8 0x0100
47
48#define IMASK_IVG7 0x0080
49#define IMASK_IVGTMR 0x0040
50#define IMASK_IVGHW 0x0020
51
52/***************************/
53
54#define BFIN_DSUBBANKS 4
55#define BFIN_DWAYS 2
56#define BFIN_DLINES 64
57#define BFIN_ISUBBANKS 4
58#define BFIN_IWAYS 4
59#define BFIN_ILINES 32
60
61#define WAY0_L 0x1
62#define WAY1_L 0x2
63#define WAY01_L 0x3
64#define WAY2_L 0x4
65#define WAY02_L 0x5
66#define WAY12_L 0x6
67#define WAY012_L 0x7
68
69#define WAY3_L 0x8
70#define WAY03_L 0x9
71#define WAY13_L 0xA
72#define WAY013_L 0xB
73
74#define WAY32_L 0xC
75#define WAY320_L 0xD
76#define WAY321_L 0xE
77#define WAYALL_L 0xF
78
79#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
80
81/********************************* EBIU Settings ************************************/
82#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
83#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
84
85#ifdef CONFIG_C_AMBEN_ALL
86#define V_AMBEN AMBEN_ALL
87#endif
88#ifdef CONFIG_C_AMBEN
89#define V_AMBEN 0x0
90#endif
91#ifdef CONFIG_C_AMBEN_B0
92#define V_AMBEN AMBEN_B0
93#endif
94#ifdef CONFIG_C_AMBEN_B0_B1
95#define V_AMBEN AMBEN_B0_B1
96#endif
97#ifdef CONFIG_C_AMBEN_B0_B1_B2
98#define V_AMBEN AMBEN_B0_B1_B2
99#endif
100#ifdef CONFIG_C_AMCKEN
101#define V_AMCKEN AMCKEN
102#else
103#define V_AMCKEN 0x0
104#endif
105#ifdef CONFIG_C_CDPRIO
106#define V_CDPRIO 0x100
107#else
108#define V_CDPRIO 0x0
109#endif
110
111#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
112
113#ifdef CONFIG_BF527
114#define CPU "BF527"
115#endif
116#ifdef CONFIG_BF525
117#define CPU "BF525"
118#endif
119#ifdef CONFIG_BF522
120#define CPU "BF522"
121#endif
122#ifndef CPU
123#define CPU "UNKNOWN"
124#define CPUID 0x0
125#endif
126
127#endif /* __MACH_BF527_H__ */
diff --git a/arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h
new file mode 100644
index 000000000000..2526b6ed6faa
--- /dev/null
+++ b/arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h
@@ -0,0 +1,195 @@
1/*
2 * file: include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
3 * based on:
4 * author:
5 *
6 * created:
7 * description:
8 * blackfin serial driver head file
9 * rev:
10 *
11 * modified:
12 *
13 *
14 * bugs: enter bugs at http://blackfin.uclinux.org/
15 *
16 * this program is free software; you can redistribute it and/or modify
17 * it under the terms of the gnu general public license as published by
18 * the free software foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * this program is distributed in the hope that it will be useful,
22 * but without any warranty; without even the implied warranty of
23 * merchantability or fitness for a particular purpose. see the
24 * gnu general public license for more details.
25 *
26 * you should have received a copy of the gnu general public license
27 * along with this program; see the file copying.
28 * if not, write to the free software foundation,
29 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
30 */
31
32#include <linux/serial.h>
33#include <asm/dma.h>
34#include <asm/portmux.h>
35
36#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
37#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
38#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
39#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
40#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
41#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
42#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
43
44#define UART_PUT_CHAR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_THR), v)
45#define UART_PUT_DLL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLL), v)
46#define UART_PUT_IER(uart, v) bfin_write16(((uart)->port.membase + OFFSET_IER), v)
47#define UART_SET_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
48#define UART_CLEAR_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
49#define UART_PUT_DLH(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLH), v)
50#define UART_PUT_LCR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_LCR), v)
51#define UART_PUT_GCTL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_GCTL), v)
52
53#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
54#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
55
56#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
57#define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1)
58#define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0)
59#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
60#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
61
62#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
63# define CONFIG_SERIAL_BFIN_CTSRTS
64
65# ifndef CONFIG_UART0_CTS_PIN
66# define CONFIG_UART0_CTS_PIN -1
67# endif
68
69# ifndef CONFIG_UART0_RTS_PIN
70# define CONFIG_UART0_RTS_PIN -1
71# endif
72
73# ifndef CONFIG_UART1_CTS_PIN
74# define CONFIG_UART1_CTS_PIN -1
75# endif
76
77# ifndef CONFIG_UART1_RTS_PIN
78# define CONFIG_UART1_RTS_PIN -1
79# endif
80#endif
81/*
82 * The pin configuration is different from schematic
83 */
84struct bfin_serial_port {
85 struct uart_port port;
86 unsigned int old_status;
87 unsigned int lsr;
88#ifdef CONFIG_SERIAL_BFIN_DMA
89 int tx_done;
90 int tx_count;
91 struct circ_buf rx_dma_buf;
92 struct timer_list rx_dma_timer;
93 int rx_dma_nrows;
94 unsigned int tx_dma_channel;
95 unsigned int rx_dma_channel;
96 struct work_struct tx_dma_workqueue;
97#endif
98#ifdef CONFIG_SERIAL_BFIN_CTSRTS
99 struct timer_list cts_timer;
100 int cts_pin;
101 int rts_pin;
102#endif
103};
104
105/* The hardware clears the LSR bits upon read, so we need to cache
106 * some of the more fun bits in software so they don't get lost
107 * when checking the LSR in other code paths (TX).
108 */
109static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
110{
111 unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
112 uart->lsr |= (lsr & (BI|FE|PE|OE));
113 return lsr | uart->lsr;
114}
115
116static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
117{
118 uart->lsr = 0;
119 bfin_write16(uart->port.membase + OFFSET_LSR, -1);
120}
121
122struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
123struct bfin_serial_res {
124 unsigned long uart_base_addr;
125 int uart_irq;
126#ifdef CONFIG_SERIAL_BFIN_DMA
127 unsigned int uart_tx_dma_channel;
128 unsigned int uart_rx_dma_channel;
129#endif
130#ifdef CONFIG_SERIAL_BFIN_CTSRTS
131 int uart_cts_pin;
132 int uart_rts_pin;
133#endif
134};
135
136struct bfin_serial_res bfin_serial_resource[] = {
137#ifdef CONFIG_SERIAL_BFIN_UART0
138 {
139 0xFFC00400,
140 IRQ_UART0_RX,
141#ifdef CONFIG_SERIAL_BFIN_DMA
142 CH_UART0_TX,
143 CH_UART0_RX,
144#endif
145#ifdef CONFIG_BFIN_UART0_CTSRTS
146 CONFIG_UART0_CTS_PIN,
147 CONFIG_UART0_RTS_PIN,
148#endif
149 },
150#endif
151#ifdef CONFIG_SERIAL_BFIN_UART1
152 {
153 0xFFC02000,
154 IRQ_UART1_RX,
155#ifdef CONFIG_SERIAL_BFIN_DMA
156 CH_UART1_TX,
157 CH_UART1_RX,
158#endif
159#ifdef CONFIG_BFIN_UART1_CTSRTS
160 CONFIG_UART1_CTS_PIN,
161 CONFIG_UART1_RTS_PIN,
162#endif
163 },
164#endif
165};
166
167int nr_ports = ARRAY_SIZE(bfin_serial_resource);
168
169#define DRIVER_NAME "bfin-uart"
170
171static void bfin_serial_hw_init(struct bfin_serial_port *uart)
172{
173
174#ifdef CONFIG_SERIAL_BFIN_UART0
175 peripheral_request(P_UART0_TX, DRIVER_NAME);
176 peripheral_request(P_UART0_RX, DRIVER_NAME);
177#endif
178
179#ifdef CONFIG_SERIAL_BFIN_UART1
180 peripheral_request(P_UART1_TX, DRIVER_NAME);
181 peripheral_request(P_UART1_RX, DRIVER_NAME);
182#endif
183
184#ifdef CONFIG_SERIAL_BFIN_CTSRTS
185 if (uart->cts_pin >= 0) {
186 gpio_request(uart->cts_pin, DRIVER_NAME);
187 gpio_direction_input(uart->cts_pin);
188 }
189
190 if (uart->rts_pin >= 0) {
191 gpio_request(uart->rts_pin, DRIVER_NAME);
192 gpio_direction_output(uart->rts_pin, 0);
193 }
194#endif
195}
diff --git a/arch/blackfin/mach-bf527/include/mach/bfin_sir.h b/arch/blackfin/mach-bf527/include/mach/bfin_sir.h
new file mode 100644
index 000000000000..cfd8ad4f1f2c
--- /dev/null
+++ b/arch/blackfin/mach-bf527/include/mach/bfin_sir.h
@@ -0,0 +1,142 @@
1/*
2 * Blackfin Infra-red Driver
3 *
4 * Copyright 2006-2008 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 *
10 */
11
12#include <linux/serial.h>
13#include <asm/dma.h>
14#include <asm/portmux.h>
15
16#define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR)
17#define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL)
18#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER)
19#define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH)
20#define SIR_UART_GET_IIR(port) bfin_read16((port)->membase + OFFSET_IIR)
21#define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR)
22#define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL)
23
24#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
25#define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v)
26#define SIR_UART_PUT_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER), v)
27#define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v)
28#define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v)
29#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
30
31#ifdef CONFIG_SIR_BFIN_DMA
32struct dma_rx_buf {
33 char *buf;
34 int head;
35 int tail;
36 };
37#endif /* CONFIG_SIR_BFIN_DMA */
38
39struct bfin_sir_port {
40 unsigned char __iomem *membase;
41 unsigned int irq;
42 unsigned int lsr;
43 unsigned long clk;
44 struct net_device *dev;
45#ifdef CONFIG_SIR_BFIN_DMA
46 int tx_done;
47 struct dma_rx_buf rx_dma_buf;
48 struct timer_list rx_dma_timer;
49 int rx_dma_nrows;
50#endif /* CONFIG_SIR_BFIN_DMA */
51 unsigned int tx_dma_channel;
52 unsigned int rx_dma_channel;
53};
54
55struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS];
56
57struct bfin_sir_port_res {
58 unsigned long base_addr;
59 int irq;
60 unsigned int rx_dma_channel;
61 unsigned int tx_dma_channel;
62};
63
64struct bfin_sir_port_res bfin_sir_port_resource[] = {
65#ifdef CONFIG_BFIN_SIR0
66 {
67 0xFFC00400,
68 IRQ_UART0_RX,
69 CH_UART0_RX,
70 CH_UART0_TX,
71 },
72#endif
73#ifdef CONFIG_BFIN_SIR1
74 {
75 0xFFC02000,
76 IRQ_UART1_RX,
77 CH_UART1_RX,
78 CH_UART1_TX,
79 },
80#endif
81};
82
83int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource);
84
85struct bfin_sir_self {
86 struct bfin_sir_port *sir_port;
87 spinlock_t lock;
88 unsigned int open;
89 int speed;
90 int newspeed;
91
92 struct sk_buff *txskb;
93 struct sk_buff *rxskb;
94 struct net_device_stats stats;
95 struct device *dev;
96 struct irlap_cb *irlap;
97 struct qos_info qos;
98
99 iobuff_t tx_buff;
100 iobuff_t rx_buff;
101
102 struct work_struct work;
103 int mtt;
104};
105
106static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port)
107{
108 unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR);
109 port->lsr |= (lsr & (BI|FE|PE|OE));
110 return lsr | port->lsr;
111}
112
113static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port)
114{
115 port->lsr = 0;
116 bfin_read16(port->membase + OFFSET_LSR);
117}
118
119#define DRIVER_NAME "bfin_sir"
120
121static int bfin_sir_hw_init(void)
122{
123 int ret = -ENODEV;
124#ifdef CONFIG_BFIN_SIR0
125 ret = peripheral_request(P_UART0_TX, DRIVER_NAME);
126 if (ret)
127 return ret;
128 ret = peripheral_request(P_UART0_RX, DRIVER_NAME);
129 if (ret)
130 return ret;
131#endif
132
133#ifdef CONFIG_BFIN_SIR1
134 ret = peripheral_request(P_UART1_TX, DRIVER_NAME);
135 if (ret)
136 return ret;
137 ret = peripheral_request(P_UART1_RX, DRIVER_NAME);
138 if (ret)
139 return ret;
140#endif
141 return ret;
142}
diff --git a/arch/blackfin/mach-bf527/include/mach/blackfin.h b/arch/blackfin/mach-bf527/include/mach/blackfin.h
new file mode 100644
index 000000000000..297821e2d79a
--- /dev/null
+++ b/arch/blackfin/mach-bf527/include/mach/blackfin.h
@@ -0,0 +1,93 @@
1/*
2 * File: include/asm-blackfin/mach-bf527/blackfin.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#ifndef _MACH_BLACKFIN_H_
33#define _MACH_BLACKFIN_H_
34
35#define BF527_FAMILY
36
37#include "bf527.h"
38#include "mem_map.h"
39#include "defBF522.h"
40#include "anomaly.h"
41
42#if defined(CONFIG_BF527) || defined(CONFIG_BF526)
43#include "defBF527.h"
44#endif
45
46#if defined(CONFIG_BF525) || defined(CONFIG_BF524)
47#include "defBF525.h"
48#endif
49
50#if !defined(__ASSEMBLY__)
51#include "cdefBF522.h"
52
53#if defined(CONFIG_BF527) || defined(CONFIG_BF526)
54#include "cdefBF527.h"
55#endif
56
57#if defined(CONFIG_BF525) || defined(CONFIG_BF524)
58#include "cdefBF525.h"
59#endif
60#endif
61
62/* UART_IIR Register */
63#define STATUS(x) ((x << 1) & 0x06)
64#define STATUS_P1 0x02
65#define STATUS_P0 0x01
66
67#define BFIN_UART_NR_PORTS 2
68
69#define OFFSET_THR 0x00 /* Transmit Holding register */
70#define OFFSET_RBR 0x00 /* Receive Buffer register */
71#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
72#define OFFSET_IER 0x04 /* Interrupt Enable Register */
73#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
74#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
75#define OFFSET_LCR 0x0C /* Line Control Register */
76#define OFFSET_MCR 0x10 /* Modem Control Register */
77#define OFFSET_LSR 0x14 /* Line Status Register */
78#define OFFSET_MSR 0x18 /* Modem Status Register */
79#define OFFSET_SCR 0x1C /* SCR Scratch Register */
80#define OFFSET_GCTL 0x24 /* Global Control Register */
81
82/* DPMC*/
83#define bfin_read_STOPCK_OFF() bfin_read_STOPCK()
84#define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val)
85#define STOPCK_OFF STOPCK
86
87/* PLL_DIV Masks */
88#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */
89#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */
90#define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */
91#define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */
92
93#endif
diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF522.h b/arch/blackfin/mach-bf527/include/mach/cdefBF522.h
new file mode 100644
index 000000000000..663c2bbdfd91
--- /dev/null
+++ b/arch/blackfin/mach-bf527/include/mach/cdefBF522.h
@@ -0,0 +1,46 @@
1/*
2 * File: include/asm-blackfin/mach-bf527/cdefbf522.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: system mmr register map
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#ifndef _CDEF_BF522_H
33#define _CDEF_BF522_H
34
35/* include all Core registers and bit definitions */
36#include "defBF522.h"
37
38/* include core specific register pointer definitions */
39#include <asm/cdef_LPBlackfin.h>
40
41/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF522 */
42
43/* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
44#include "cdefBF52x_base.h"
45
46#endif /* _CDEF_BF522_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF525.h b/arch/blackfin/mach-bf527/include/mach/cdefBF525.h
new file mode 100644
index 000000000000..00377eb59b75
--- /dev/null
+++ b/arch/blackfin/mach-bf527/include/mach/cdefBF525.h
@@ -0,0 +1,461 @@
1/*
2 * File: include/asm-blackfin/mach-bf527/cdefbf525.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: system mmr register map
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#ifndef _CDEF_BF525_H
33#define _CDEF_BF525_H
34
35/* include all Core registers and bit definitions */
36#include "defBF525.h"
37
38/* include core specific register pointer definitions */
39#include <asm/cdef_LPBlackfin.h>
40
41/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF525 */
42
43/* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
44#include "cdefBF52x_base.h"
45
46/* The following are the #defines needed by ADSP-BF525 that are not in the common header */
47
48/* USB Control Registers */
49
50#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
51#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
52#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
53#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
54#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
55#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
56#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
57#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
58#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
59#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
60#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
61#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
62#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
63#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
64#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
65#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
66#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
67#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
68#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
69#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
70#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
71#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
72#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
73#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
74#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
75#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
76
77/* USB Packet Control Registers */
78
79#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
80#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
81#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
82#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
83#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
84#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
85#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
86#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
87#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
88#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
89#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
90#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
91#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
92#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
93#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
94#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
95#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
96#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
97#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
98#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
99#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
100#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
101#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
102#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
103#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
104#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
105
106/* USB Endpoint FIFO Registers */
107
108#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
109#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
110#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
111#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
112#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
113#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
114#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
115#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
116#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
117#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
118#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
119#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
120#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
121#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
122#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
123#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
124
125/* USB OTG Control Registers */
126
127#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
128#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
129#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
130#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
131#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
132#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
133
134/* USB Phy Control Registers */
135
136#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
137#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
138#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
139#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
140#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
141#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
142#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
143#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
144#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
145#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
146
147/* (APHY_CNTRL is for ADI usage only) */
148
149#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
150#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
151
152/* (APHY_CALIB is for ADI usage only) */
153
154#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
155#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
156
157#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
158#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
159
160/* (PHY_TEST is for ADI usage only) */
161
162#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST)
163#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val)
164
165#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
166#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
167#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
168#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
169
170/* USB Endpoint 0 Control Registers */
171
172#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
173#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
174#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
175#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
176#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
177#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
178#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
179#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
180#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
181#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
182#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
183#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
184#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
185#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
186#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
187#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
188#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
189#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
190#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
191#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
192
193/* USB Endpoint 1 Control Registers */
194
195#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
196#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
197#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
198#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
199#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
200#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
201#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
202#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
203#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
204#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
205#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
206#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
207#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
208#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
209#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
210#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
211#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
212#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
213#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
214#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
215
216/* USB Endpoint 2 Control Registers */
217
218#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
219#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
220#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
221#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
222#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
223#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
224#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
225#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
226#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
227#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
228#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
229#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
230#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
231#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
232#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
233#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
234#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
235#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
236#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
237#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
238
239/* USB Endpoint 3 Control Registers */
240
241#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
242#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
243#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
244#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
245#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
246#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
247#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
248#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
249#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
250#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
251#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
252#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
253#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
254#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
255#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
256#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
257#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
258#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
259#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
260#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
261
262/* USB Endpoint 4 Control Registers */
263
264#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
265#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
266#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
267#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
268#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
269#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
270#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
271#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
272#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
273#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
274#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
275#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
276#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
277#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
278#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
279#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
280#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
281#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
282#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
283#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
284
285/* USB Endpoint 5 Control Registers */
286
287#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
288#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
289#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
290#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
291#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
292#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
293#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
294#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
295#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
296#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
297#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
298#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
299#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
300#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
301#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
302#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
303#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
304#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
305#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
306#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
307
308/* USB Endpoint 6 Control Registers */
309
310#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
311#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
312#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
313#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
314#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
315#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
316#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
317#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
318#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
319#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
320#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
321#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
322#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
323#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
324#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
325#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
326#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
327#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
328#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
329#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
330
331/* USB Endpoint 7 Control Registers */
332
333#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
334#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
335#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
336#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
337#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
338#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
339#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
340#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
341#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
342#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
343#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
344#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
345#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
346#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
347#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
348#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
349#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
350#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
351#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
352#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
353
354#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
355#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
356
357/* USB Channel 0 Config Registers */
358
359#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL)
360#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val)
361#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW)
362#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val)
363#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH)
364#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val)
365#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW)
366#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val)
367#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH)
368#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val)
369
370/* USB Channel 1 Config Registers */
371
372#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL)
373#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val)
374#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW)
375#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val)
376#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH)
377#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val)
378#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW)
379#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val)
380#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH)
381#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val)
382
383/* USB Channel 2 Config Registers */
384
385#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL)
386#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val)
387#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW)
388#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val)
389#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH)
390#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val)
391#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW)
392#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val)
393#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH)
394#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val)
395
396/* USB Channel 3 Config Registers */
397
398#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL)
399#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val)
400#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW)
401#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val)
402#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH)
403#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val)
404#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW)
405#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val)
406#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH)
407#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val)
408
409/* USB Channel 4 Config Registers */
410
411#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL)
412#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val)
413#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW)
414#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val)
415#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH)
416#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val)
417#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW)
418#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val)
419#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH)
420#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val)
421
422/* USB Channel 5 Config Registers */
423
424#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL)
425#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val)
426#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW)
427#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val)
428#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH)
429#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val)
430#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW)
431#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val)
432#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH)
433#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val)
434
435/* USB Channel 6 Config Registers */
436
437#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL)
438#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val)
439#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW)
440#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val)
441#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH)
442#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val)
443#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW)
444#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val)
445#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH)
446#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val)
447
448/* USB Channel 7 Config Registers */
449
450#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL)
451#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val)
452#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW)
453#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val)
454#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH)
455#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val)
456#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW)
457#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val)
458#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH)
459#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val)
460
461#endif /* _CDEF_BF525_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF527.h b/arch/blackfin/mach-bf527/include/mach/cdefBF527.h
new file mode 100644
index 000000000000..fca8db708119
--- /dev/null
+++ b/arch/blackfin/mach-bf527/include/mach/cdefBF527.h
@@ -0,0 +1,626 @@
1/*
2 * File: include/asm-blackfin/mach-bf527/cdefbf527.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: system mmr register map
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#ifndef _CDEF_BF527_H
33#define _CDEF_BF527_H
34
35/* include all Core registers and bit definitions */
36#include "defBF527.h"
37
38/* include core specific register pointer definitions */
39#include <asm/cdef_LPBlackfin.h>
40
41/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF527 */
42
43/* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
44#include "cdefBF52x_base.h"
45
46/* The following are the #defines needed by ADSP-BF527 that are not in the common header */
47
48/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
49
50#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE)
51#define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val)
52#define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO)
53#define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO, val)
54#define bfin_read_EMAC_ADDRHI() bfin_read32(EMAC_ADDRHI)
55#define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI, val)
56#define bfin_read_EMAC_HASHLO() bfin_read32(EMAC_HASHLO)
57#define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO, val)
58#define bfin_read_EMAC_HASHHI() bfin_read32(EMAC_HASHHI)
59#define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI, val)
60#define bfin_read_EMAC_STAADD() bfin_read32(EMAC_STAADD)
61#define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD, val)
62#define bfin_read_EMAC_STADAT() bfin_read32(EMAC_STADAT)
63#define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT, val)
64#define bfin_read_EMAC_FLC() bfin_read32(EMAC_FLC)
65#define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC, val)
66#define bfin_read_EMAC_VLAN1() bfin_read32(EMAC_VLAN1)
67#define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1, val)
68#define bfin_read_EMAC_VLAN2() bfin_read32(EMAC_VLAN2)
69#define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2, val)
70#define bfin_read_EMAC_WKUP_CTL() bfin_read32(EMAC_WKUP_CTL)
71#define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL, val)
72#define bfin_read_EMAC_WKUP_FFMSK0() bfin_read32(EMAC_WKUP_FFMSK0)
73#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val)
74#define bfin_read_EMAC_WKUP_FFMSK1() bfin_read32(EMAC_WKUP_FFMSK1)
75#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val)
76#define bfin_read_EMAC_WKUP_FFMSK2() bfin_read32(EMAC_WKUP_FFMSK2)
77#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val)
78#define bfin_read_EMAC_WKUP_FFMSK3() bfin_read32(EMAC_WKUP_FFMSK3)
79#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val)
80#define bfin_read_EMAC_WKUP_FFCMD() bfin_read32(EMAC_WKUP_FFCMD)
81#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val)
82#define bfin_read_EMAC_WKUP_FFOFF() bfin_read32(EMAC_WKUP_FFOFF)
83#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val)
84#define bfin_read_EMAC_WKUP_FFCRC0() bfin_read32(EMAC_WKUP_FFCRC0)
85#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val)
86#define bfin_read_EMAC_WKUP_FFCRC1() bfin_read32(EMAC_WKUP_FFCRC1)
87#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val)
88
89#define bfin_read_EMAC_SYSCTL() bfin_read32(EMAC_SYSCTL)
90#define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val)
91#define bfin_read_EMAC_SYSTAT() bfin_read32(EMAC_SYSTAT)
92#define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT, val)
93#define bfin_read_EMAC_RX_STAT() bfin_read32(EMAC_RX_STAT)
94#define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT, val)
95#define bfin_read_EMAC_RX_STKY() bfin_read32(EMAC_RX_STKY)
96#define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY, val)
97#define bfin_read_EMAC_RX_IRQE() bfin_read32(EMAC_RX_IRQE)
98#define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE, val)
99#define bfin_read_EMAC_TX_STAT() bfin_read32(EMAC_TX_STAT)
100#define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT, val)
101#define bfin_read_EMAC_TX_STKY() bfin_read32(EMAC_TX_STKY)
102#define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY, val)
103#define bfin_read_EMAC_TX_IRQE() bfin_read32(EMAC_TX_IRQE)
104#define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE, val)
105
106#define bfin_read_EMAC_MMC_CTL() bfin_read32(EMAC_MMC_CTL)
107#define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL, val)
108#define bfin_read_EMAC_MMC_RIRQS() bfin_read32(EMAC_MMC_RIRQS)
109#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val)
110#define bfin_read_EMAC_MMC_RIRQE() bfin_read32(EMAC_MMC_RIRQE)
111#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val)
112#define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS)
113#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val)
114#define bfin_read_EMAC_MMC_TIRQE() bfin_read32(EMAC_MMC_TIRQE)
115#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val)
116
117#define bfin_read_EMAC_RXC_OK() bfin_read32(EMAC_RXC_OK)
118#define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK, val)
119#define bfin_read_EMAC_RXC_FCS() bfin_read32(EMAC_RXC_FCS)
120#define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS, val)
121#define bfin_read_EMAC_RXC_ALIGN() bfin_read32(EMAC_RXC_ALIGN)
122#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val)
123#define bfin_read_EMAC_RXC_OCTET() bfin_read32(EMAC_RXC_OCTET)
124#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val)
125#define bfin_read_EMAC_RXC_DMAOVF() bfin_read32(EMAC_RXC_DMAOVF)
126#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val)
127#define bfin_read_EMAC_RXC_UNICST() bfin_read32(EMAC_RXC_UNICST)
128#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val)
129#define bfin_read_EMAC_RXC_MULTI() bfin_read32(EMAC_RXC_MULTI)
130#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val)
131#define bfin_read_EMAC_RXC_BROAD() bfin_read32(EMAC_RXC_BROAD)
132#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val)
133#define bfin_read_EMAC_RXC_LNERRI() bfin_read32(EMAC_RXC_LNERRI)
134#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val)
135#define bfin_read_EMAC_RXC_LNERRO() bfin_read32(EMAC_RXC_LNERRO)
136#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val)
137#define bfin_read_EMAC_RXC_LONG() bfin_read32(EMAC_RXC_LONG)
138#define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG, val)
139#define bfin_read_EMAC_RXC_MACCTL() bfin_read32(EMAC_RXC_MACCTL)
140#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val)
141#define bfin_read_EMAC_RXC_OPCODE() bfin_read32(EMAC_RXC_OPCODE)
142#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val)
143#define bfin_read_EMAC_RXC_PAUSE() bfin_read32(EMAC_RXC_PAUSE)
144#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val)
145#define bfin_read_EMAC_RXC_ALLFRM() bfin_read32(EMAC_RXC_ALLFRM)
146#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val)
147#define bfin_read_EMAC_RXC_ALLOCT() bfin_read32(EMAC_RXC_ALLOCT)
148#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val)
149#define bfin_read_EMAC_RXC_TYPED() bfin_read32(EMAC_RXC_TYPED)
150#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val)
151#define bfin_read_EMAC_RXC_SHORT() bfin_read32(EMAC_RXC_SHORT)
152#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val)
153#define bfin_read_EMAC_RXC_EQ64() bfin_read32(EMAC_RXC_EQ64)
154#define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64, val)
155#define bfin_read_EMAC_RXC_LT128() bfin_read32(EMAC_RXC_LT128)
156#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val)
157#define bfin_read_EMAC_RXC_LT256() bfin_read32(EMAC_RXC_LT256)
158#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val)
159#define bfin_read_EMAC_RXC_LT512() bfin_read32(EMAC_RXC_LT512)
160#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val)
161#define bfin_read_EMAC_RXC_LT1024() bfin_read32(EMAC_RXC_LT1024)
162#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val)
163#define bfin_read_EMAC_RXC_GE1024() bfin_read32(EMAC_RXC_GE1024)
164#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val)
165
166#define bfin_read_EMAC_TXC_OK() bfin_read32(EMAC_TXC_OK)
167#define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK, val)
168#define bfin_read_EMAC_TXC_1COL() bfin_read32(EMAC_TXC_1COL)
169#define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL, val)
170#define bfin_read_EMAC_TXC_GT1COL() bfin_read32(EMAC_TXC_GT1COL)
171#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val)
172#define bfin_read_EMAC_TXC_OCTET() bfin_read32(EMAC_TXC_OCTET)
173#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val)
174#define bfin_read_EMAC_TXC_DEFER() bfin_read32(EMAC_TXC_DEFER)
175#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val)
176#define bfin_read_EMAC_TXC_LATECL() bfin_read32(EMAC_TXC_LATECL)
177#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val)
178#define bfin_read_EMAC_TXC_XS_COL() bfin_read32(EMAC_TXC_XS_COL)
179#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val)
180#define bfin_read_EMAC_TXC_DMAUND() bfin_read32(EMAC_TXC_DMAUND)
181#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val)
182#define bfin_read_EMAC_TXC_CRSERR() bfin_read32(EMAC_TXC_CRSERR)
183#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val)
184#define bfin_read_EMAC_TXC_UNICST() bfin_read32(EMAC_TXC_UNICST)
185#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val)
186#define bfin_read_EMAC_TXC_MULTI() bfin_read32(EMAC_TXC_MULTI)
187#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val)
188#define bfin_read_EMAC_TXC_BROAD() bfin_read32(EMAC_TXC_BROAD)
189#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val)
190#define bfin_read_EMAC_TXC_XS_DFR() bfin_read32(EMAC_TXC_XS_DFR)
191#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val)
192#define bfin_read_EMAC_TXC_MACCTL() bfin_read32(EMAC_TXC_MACCTL)
193#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val)
194#define bfin_read_EMAC_TXC_ALLFRM() bfin_read32(EMAC_TXC_ALLFRM)
195#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val)
196#define bfin_read_EMAC_TXC_ALLOCT() bfin_read32(EMAC_TXC_ALLOCT)
197#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val)
198#define bfin_read_EMAC_TXC_EQ64() bfin_read32(EMAC_TXC_EQ64)
199#define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64, val)
200#define bfin_read_EMAC_TXC_LT128() bfin_read32(EMAC_TXC_LT128)
201#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val)
202#define bfin_read_EMAC_TXC_LT256() bfin_read32(EMAC_TXC_LT256)
203#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val)
204#define bfin_read_EMAC_TXC_LT512() bfin_read32(EMAC_TXC_LT512)
205#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val)
206#define bfin_read_EMAC_TXC_LT1024() bfin_read32(EMAC_TXC_LT1024)
207#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val)
208#define bfin_read_EMAC_TXC_GE1024() bfin_read32(EMAC_TXC_GE1024)
209#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val)
210#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT)
211#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val)
212
213/* USB Control Registers */
214
215#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
216#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
217#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
218#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
219#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
220#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
221#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
222#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
223#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
224#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
225#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
226#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
227#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
228#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
229#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
230#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
231#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
232#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
233#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
234#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
235#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
236#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
237#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
238#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
239#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
240#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
241
242/* USB Packet Control Registers */
243
244#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
245#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
246#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
247#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
248#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
249#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
250#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
251#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
252#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
253#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
254#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
255#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
256#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
257#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
258#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
259#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
260#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
261#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
262#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
263#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
264#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
265#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
266#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
267#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
268#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
269#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
270
271/* USB Endpoint FIFO Registers */
272
273#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
274#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
275#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
276#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
277#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
278#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
279#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
280#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
281#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
282#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
283#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
284#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
285#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
286#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
287#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
288#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
289
290/* USB OTG Control Registers */
291
292#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
293#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
294#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
295#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
296#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
297#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
298
299/* USB Phy Control Registers */
300
301#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
302#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
303#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
304#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
305#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
306#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
307#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
308#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
309#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
310#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
311
312/* (APHY_CNTRL is for ADI usage only) */
313
314#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
315#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
316
317/* (APHY_CALIB is for ADI usage only) */
318
319#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
320#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
321
322#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
323#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
324
325/* (PHY_TEST is for ADI usage only) */
326
327#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST)
328#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val)
329
330#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
331#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
332#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
333#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
334
335/* USB Endpoint 0 Control Registers */
336
337#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
338#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
339#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
340#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
341#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
342#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
343#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
344#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
345#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
346#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
347#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
348#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
349#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
350#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
351#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
352#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
353#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
354#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
355#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
356#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
357
358/* USB Endpoint 1 Control Registers */
359
360#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
361#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
362#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
363#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
364#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
365#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
366#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
367#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
368#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
369#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
370#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
371#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
372#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
373#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
374#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
375#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
376#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
377#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
378#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
379#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
380
381/* USB Endpoint 2 Control Registers */
382
383#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
384#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
385#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
386#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
387#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
388#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
389#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
390#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
391#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
392#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
393#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
394#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
395#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
396#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
397#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
398#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
399#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
400#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
401#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
402#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
403
404/* USB Endpoint 3 Control Registers */
405
406#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
407#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
408#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
409#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
410#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
411#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
412#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
413#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
414#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
415#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
416#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
417#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
418#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
419#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
420#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
421#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
422#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
423#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
424#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
425#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
426
427/* USB Endpoint 4 Control Registers */
428
429#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
430#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
431#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
432#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
433#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
434#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
435#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
436#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
437#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
438#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
439#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
440#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
441#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
442#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
443#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
444#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
445#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
446#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
447#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
448#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
449
450/* USB Endpoint 5 Control Registers */
451
452#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
453#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
454#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
455#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
456#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
457#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
458#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
459#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
460#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
461#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
462#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
463#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
464#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
465#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
466#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
467#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
468#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
469#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
470#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
471#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
472
473/* USB Endpoint 6 Control Registers */
474
475#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
476#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
477#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
478#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
479#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
480#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
481#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
482#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
483#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
484#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
485#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
486#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
487#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
488#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
489#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
490#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
491#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
492#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
493#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
494#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
495
496/* USB Endpoint 7 Control Registers */
497
498#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
499#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
500#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
501#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
502#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
503#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
504#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
505#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
506#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
507#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
508#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
509#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
510#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
511#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
512#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
513#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
514#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
515#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
516#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
517#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
518
519#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
520#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
521
522/* USB Channel 0 Config Registers */
523
524#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL)
525#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val)
526#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW)
527#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val)
528#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH)
529#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val)
530#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW)
531#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val)
532#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH)
533#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val)
534
535/* USB Channel 1 Config Registers */
536
537#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL)
538#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val)
539#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW)
540#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val)
541#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH)
542#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val)
543#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW)
544#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val)
545#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH)
546#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val)
547
548/* USB Channel 2 Config Registers */
549
550#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL)
551#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val)
552#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW)
553#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val)
554#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH)
555#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val)
556#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW)
557#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val)
558#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH)
559#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val)
560
561/* USB Channel 3 Config Registers */
562
563#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL)
564#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val)
565#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW)
566#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val)
567#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH)
568#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val)
569#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW)
570#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val)
571#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH)
572#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val)
573
574/* USB Channel 4 Config Registers */
575
576#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL)
577#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val)
578#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW)
579#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val)
580#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH)
581#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val)
582#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW)
583#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val)
584#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH)
585#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val)
586
587/* USB Channel 5 Config Registers */
588
589#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL)
590#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val)
591#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW)
592#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val)
593#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH)
594#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val)
595#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW)
596#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val)
597#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH)
598#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val)
599
600/* USB Channel 6 Config Registers */
601
602#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL)
603#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val)
604#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW)
605#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val)
606#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH)
607#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val)
608#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW)
609#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val)
610#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH)
611#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val)
612
613/* USB Channel 7 Config Registers */
614
615#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL)
616#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val)
617#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW)
618#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val)
619#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH)
620#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val)
621#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW)
622#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val)
623#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH)
624#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val)
625
626#endif /* _CDEF_BF527_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h b/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h
new file mode 100644
index 000000000000..9a814b9a12b9
--- /dev/null
+++ b/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h
@@ -0,0 +1,1204 @@
1/*
2 * File: include/asm-blackfin/mach-bf527/cdefBF52x_base.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _CDEF_BF52X_H
32#define _CDEF_BF52X_H
33
34#include <asm/system.h>
35#include <asm/blackfin.h>
36
37#include "defBF52x_base.h"
38
39/* Include core specific register pointer definitions */
40#include <asm/cdef_LPBlackfin.h>
41
42/* ==== begin from cdefBF534.h ==== */
43
44/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
45#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
46/* Writing to PLL_CTL initiates a PLL relock sequence. */
47static __inline__ void bfin_write_PLL_CTL(unsigned int val)
48{
49 unsigned long flags, iwr0, iwr1;
50
51 if (val == bfin_read_PLL_CTL())
52 return;
53
54 local_irq_save(flags);
55 /* Enable the PLL Wakeup bit in SIC IWR */
56 iwr0 = bfin_read32(SIC_IWR0);
57 iwr1 = bfin_read32(SIC_IWR1);
58 /* Only allow PPL Wakeup) */
59 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
60 bfin_write32(SIC_IWR1, 0);
61
62 bfin_write16(PLL_CTL, val);
63 SSYNC();
64 asm("IDLE;");
65
66 bfin_write32(SIC_IWR0, iwr0);
67 bfin_write32(SIC_IWR1, iwr1);
68 local_irq_restore(flags);
69}
70#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
71#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
72#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
73/* Writing to VR_CTL initiates a PLL relock sequence. */
74static __inline__ void bfin_write_VR_CTL(unsigned int val)
75{
76 unsigned long flags, iwr0, iwr1;
77
78 if (val == bfin_read_VR_CTL())
79 return;
80
81 local_irq_save(flags);
82 /* Enable the PLL Wakeup bit in SIC IWR */
83 iwr0 = bfin_read32(SIC_IWR0);
84 iwr1 = bfin_read32(SIC_IWR1);
85 /* Only allow PPL Wakeup) */
86 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
87 bfin_write32(SIC_IWR1, 0);
88
89 bfin_write16(VR_CTL, val);
90 SSYNC();
91 asm("IDLE;");
92
93 bfin_write32(SIC_IWR0, iwr0);
94 bfin_write32(SIC_IWR1, iwr1);
95 local_irq_restore(flags);
96}
97#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
98#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
99#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
100#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
101#define bfin_read_CHIPID() bfin_read32(CHIPID)
102#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
103
104
105/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
106#define bfin_read_SWRST() bfin_read16(SWRST)
107#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
108#define bfin_read_SYSCR() bfin_read16(SYSCR)
109#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
110
111#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT)
112#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val)
113#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
114#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
115#define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 6))
116#define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 6)), val)
117
118#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
119#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
120#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
121#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
122#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
123#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
124#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
125#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
126
127#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
128#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
129#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 6))
130#define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 6)), val)
131
132#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
133#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
134#define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + (x << 6))
135#define bfin_write_SIC_IWR(x, val) bfin_write32((SIC_IWR0 + (x << 6)), val)
136
137/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
138
139#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
140#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
141#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
142#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
143#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
144#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
145#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
146#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
147#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
148#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val)
149#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
150#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
151#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
152#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
153
154/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
155#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
156#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
157#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
158#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
159#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
160#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
161
162
163/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
164#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
165#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
166#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
167#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
168#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
169#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
170#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
171#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
172#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
173#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
174#define bfin_read_RTC_FAST() bfin_read16(RTC_FAST)
175#define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST, val)
176#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
177#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
178
179
180/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
181#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
182#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
183#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
184#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
185#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
186#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
187#define bfin_read_UART0_IER() bfin_read16(UART0_IER)
188#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val)
189#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
190#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
191#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR)
192#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val)
193#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
194#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
195#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
196#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
197#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
198#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
199#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
200#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val)
201#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
202#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
203#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
204#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
205
206
207/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
208#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL)
209#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL, val)
210#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG)
211#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG, val)
212#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT)
213#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT, val)
214#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR)
215#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR, val)
216#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR)
217#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR, val)
218#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD)
219#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD, val)
220#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW)
221#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW, val)
222
223
224/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
225#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
226#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
227#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
228#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
229#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
230#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
231#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
232#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
233
234#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
235#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
236#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
237#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
238#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
239#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
240#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
241#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
242
243#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
244#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
245#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
246#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
247#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
248#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
249#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
250#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
251
252#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
253#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
254#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
255#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
256#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
257#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
258#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
259#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
260
261#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
262#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
263#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
264#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
265#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
266#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
267#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
268#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
269
270#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
271#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
272#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
273#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
274#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
275#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
276#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
277#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
278
279#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
280#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
281#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
282#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
283#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
284#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
285#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
286#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
287
288#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
289#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
290#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
291#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
292#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
293#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
294#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
295#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
296
297#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
298#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val)
299#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE)
300#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val)
301#define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS)
302#define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS, val)
303
304
305/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
306#define bfin_read_PORTFIO() bfin_read16(PORTFIO)
307#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val)
308#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR)
309#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val)
310#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET)
311#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val)
312#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE)
313#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val)
314#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA)
315#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val)
316#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
317#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val)
318#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET)
319#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val)
320#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
321#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val)
322#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB)
323#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val)
324#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
325#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val)
326#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET)
327#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val)
328#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
329#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val)
330#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR)
331#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val)
332#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR)
333#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val)
334#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE)
335#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val)
336#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH)
337#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val)
338#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN)
339#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val)
340
341
342/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
343#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
344#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
345#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
346#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
347#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
348#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
349#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
350#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
351#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
352#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
353#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
354#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
355#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX32)
356#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX32, val)
357#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX32)
358#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX32, val)
359#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX16)
360#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX16, val)
361#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX16)
362#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX16, val)
363#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
364#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
365#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
366#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
367#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
368#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
369#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
370#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
371#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
372#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
373#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
374#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
375#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
376#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
377#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
378#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
379#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
380#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
381#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
382#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
383#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
384#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
385#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
386#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
387#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
388#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
389#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
390#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
391#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
392#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
393#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
394#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
395
396
397/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
398#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
399#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
400#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
401#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
402#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
403#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
404#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
405#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
406#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
407#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
408#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
409#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
410#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX32)
411#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX32, val)
412#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX32)
413#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX32, val)
414#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX16)
415#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX16, val)
416#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX16)
417#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX16, val)
418#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
419#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
420#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
421#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
422#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
423#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
424#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
425#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
426#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
427#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
428#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
429#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
430#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
431#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
432#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
433#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
434#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
435#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
436#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
437#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
438#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
439#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
440#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
441#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
442#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
443#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
444#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
445#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
446#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
447#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
448#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
449#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
450
451
452/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
453#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
454#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
455#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
456#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
457#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
458#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
459#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
460#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val)
461#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
462#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val)
463#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
464#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val)
465#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
466#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val)
467
468
469/* DMA Traffic Control Registers */
470#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER)
471#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER, val)
472#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT)
473#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT, val)
474
475/* Alternate deprecated register names (below) provided for backwards code compatibility */
476#define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER)
477#define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER, val)
478#define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT)
479#define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT, val)
480
481/* DMA Controller */
482#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
483#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
484#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
485#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val)
486#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
487#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val)
488#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
489#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
490#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
491#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
492#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
493#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
494#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
495#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
496#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
497#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val)
498#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
499#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val)
500#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
501#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
502#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
503#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
504#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
505#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
506#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
507#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
508
509#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
510#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
511#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
512#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val)
513#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
514#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val)
515#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
516#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
517#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
518#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
519#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
520#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
521#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
522#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
523#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
524#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val)
525#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
526#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val)
527#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
528#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
529#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
530#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
531#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
532#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
533#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
534#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
535
536#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
537#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
538#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
539#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val)
540#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
541#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val)
542#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
543#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
544#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
545#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
546#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
547#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
548#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
549#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
550#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
551#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val)
552#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
553#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val)
554#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
555#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
556#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
557#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
558#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
559#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
560#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
561#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
562
563#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
564#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
565#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
566#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val)
567#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
568#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val)
569#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
570#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
571#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
572#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
573#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
574#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
575#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
576#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
577#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
578#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val)
579#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
580#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val)
581#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
582#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
583#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
584#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
585#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
586#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
587#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
588#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
589
590#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
591#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
592#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
593#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val)
594#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
595#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val)
596#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
597#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
598#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
599#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
600#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
601#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
602#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
603#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
604#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
605#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val)
606#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
607#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val)
608#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
609#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
610#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
611#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
612#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
613#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
614#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
615#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
616
617#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
618#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
619#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
620#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val)
621#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
622#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val)
623#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
624#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
625#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
626#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
627#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
628#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
629#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
630#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
631#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
632#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val)
633#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
634#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val)
635#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
636#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
637#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
638#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
639#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
640#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
641#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
642#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
643
644#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
645#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
646#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
647#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
648#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
649#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val)
650#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
651#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
652#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
653#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
654#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
655#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
656#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
657#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
658#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
659#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val)
660#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
661#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val)
662#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
663#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
664#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
665#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
666#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
667#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
668#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
669#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
670
671#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
672#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
673#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
674#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val)
675#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
676#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val)
677#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
678#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
679#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
680#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
681#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
682#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
683#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
684#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
685#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
686#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val)
687#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
688#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val)
689#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
690#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
691#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
692#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
693#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
694#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
695#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
696#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
697
698#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
699#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
700#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR)
701#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val)
702#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR)
703#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val)
704#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
705#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
706#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
707#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
708#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
709#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
710#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
711#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
712#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR)
713#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val)
714#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR)
715#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val)
716#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
717#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
718#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
719#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
720#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
721#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
722#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
723#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
724
725#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
726#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
727#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR)
728#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val)
729#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR)
730#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val)
731#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
732#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
733#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
734#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
735#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
736#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
737#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
738#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
739#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR)
740#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val)
741#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR)
742#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val)
743#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
744#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
745#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
746#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
747#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
748#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
749#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
750#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
751
752#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
753#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
754#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR)
755#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val)
756#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR)
757#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val)
758#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
759#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
760#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
761#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
762#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
763#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
764#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
765#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
766#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR)
767#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val)
768#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR)
769#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val)
770#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
771#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
772#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
773#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
774#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
775#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
776#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
777#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
778
779#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
780#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
781#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR)
782#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val)
783#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR)
784#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val)
785#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
786#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
787#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
788#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
789#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
790#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
791#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
792#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
793#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR)
794#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val)
795#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR)
796#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val)
797#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
798#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
799#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
800#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
801#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
802#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
803#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
804#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
805
806#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
807#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
808#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
809#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
810#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
811#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val)
812#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
813#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
814#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
815#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
816#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
817#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
818#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
819#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
820#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
821#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
822#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
823#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val)
824#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
825#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
826#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
827#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
828#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
829#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
830#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
831#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
832
833#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
834#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
835#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
836#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
837#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
838#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val)
839#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
840#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
841#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
842#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
843#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
844#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
845#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
846#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
847#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
848#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
849#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
850#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val)
851#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
852#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
853#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
854#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
855#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
856#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
857#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
858#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
859
860#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
861#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
862#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
863#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
864#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
865#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val)
866#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
867#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
868#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
869#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
870#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
871#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
872#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
873#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
874#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
875#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
876#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
877#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val)
878#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
879#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
880#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
881#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
882#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
883#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
884#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
885#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
886
887#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
888#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
889#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
890#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
891#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
892#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val)
893#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
894#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
895#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
896#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
897#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
898#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
899#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
900#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
901#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
902#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
903#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
904#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val)
905#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
906#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
907#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
908#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
909#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
910#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
911#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
912#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
913
914
915/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
916#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
917#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val)
918#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
919#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val)
920#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
921#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val)
922#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
923#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val)
924#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
925#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val)
926
927
928/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
929
930/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
931#define bfin_read_PORTGIO() bfin_read16(PORTGIO)
932#define bfin_write_PORTGIO(val) bfin_write16(PORTGIO, val)
933#define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR)
934#define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR, val)
935#define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET)
936#define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET, val)
937#define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE)
938#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val)
939#define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA)
940#define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA, val)
941#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR)
942#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val)
943#define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET)
944#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val)
945#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE)
946#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val)
947#define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB)
948#define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB, val)
949#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR)
950#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val)
951#define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET)
952#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val)
953#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE)
954#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val)
955#define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR)
956#define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR, val)
957#define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR)
958#define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR, val)
959#define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE)
960#define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE, val)
961#define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH)
962#define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH, val)
963#define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN)
964#define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN, val)
965
966
967/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
968#define bfin_read_PORTHIO() bfin_read16(PORTHIO)
969#define bfin_write_PORTHIO(val) bfin_write16(PORTHIO, val)
970#define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR)
971#define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR, val)
972#define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET)
973#define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET, val)
974#define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE)
975#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val)
976#define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA)
977#define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA, val)
978#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR)
979#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val)
980#define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET)
981#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val)
982#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE)
983#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val)
984#define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB)
985#define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB, val)
986#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR)
987#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val)
988#define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET)
989#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val)
990#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE)
991#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val)
992#define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR)
993#define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR, val)
994#define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR)
995#define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR, val)
996#define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE)
997#define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE, val)
998#define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH)
999#define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH, val)
1000#define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN)
1001#define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN, val)
1002
1003
1004/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
1005#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
1006#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
1007#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
1008#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
1009#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
1010#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
1011#define bfin_read_UART1_IER() bfin_read16(UART1_IER)
1012#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val)
1013#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
1014#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
1015#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR)
1016#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val)
1017#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
1018#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
1019#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
1020#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
1021#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
1022#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
1023#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR)
1024#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val)
1025#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
1026#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
1027#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
1028#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
1029
1030/* Omit CAN register sets from the cdefBF534.h (CAN is not in the ADSP-BF52x processor) */
1031
1032/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
1033#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER)
1034#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val)
1035#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER)
1036#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val)
1037#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER)
1038#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val)
1039#define bfin_read_PORT_MUX() bfin_read16(PORT_MUX)
1040#define bfin_write_PORT_MUX(val) bfin_write16(PORT_MUX, val)
1041
1042
1043/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
1044#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
1045#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
1046#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
1047#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
1048#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
1049#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
1050#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
1051#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
1052#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
1053#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
1054#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
1055#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
1056#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
1057#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
1058
1059#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
1060#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
1061#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
1062#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
1063#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
1064#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
1065#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
1066#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
1067#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
1068#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
1069#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
1070#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
1071#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
1072#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
1073
1074/* ==== end from cdefBF534.h ==== */
1075
1076/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
1077
1078#define bfin_read_PORTF_MUX() bfin_read16(PORTF_MUX)
1079#define bfin_write_PORTF_MUX(val) bfin_write16(PORTF_MUX, val)
1080#define bfin_read_PORTG_MUX() bfin_read16(PORTG_MUX)
1081#define bfin_write_PORTG_MUX(val) bfin_write16(PORTG_MUX, val)
1082#define bfin_read_PORTH_MUX() bfin_read16(PORTH_MUX)
1083#define bfin_write_PORTH_MUX(val) bfin_write16(PORTH_MUX, val)
1084
1085#define bfin_read_PORTF_DRIVE() bfin_read16(PORTF_DRIVE)
1086#define bfin_write_PORTF_DRIVE(val) bfin_write16(PORTF_DRIVE, val)
1087#define bfin_read_PORTG_DRIVE() bfin_read16(PORTG_DRIVE)
1088#define bfin_write_PORTG_DRIVE(val) bfin_write16(PORTG_DRIVE, val)
1089#define bfin_read_PORTH_DRIVE() bfin_read16(PORTH_DRIVE)
1090#define bfin_write_PORTH_DRIVE(val) bfin_write16(PORTH_DRIVE, val)
1091#define bfin_read_PORTF_SLEW() bfin_read16(PORTF_SLEW)
1092#define bfin_write_PORTF_SLEW(val) bfin_write16(PORTF_SLEW, val)
1093#define bfin_read_PORTG_SLEW() bfin_read16(PORTG_SLEW)
1094#define bfin_write_PORTG_SLEW(val) bfin_write16(PORTG_SLEW, val)
1095#define bfin_read_PORTH_SLEW() bfin_read16(PORTH_SLEW)
1096#define bfin_write_PORTH_SLEW(val) bfin_write16(PORTH_SLEW, val)
1097#define bfin_read_PORTF_HYSTERISIS() bfin_read16(PORTF_HYSTERISIS)
1098#define bfin_write_PORTF_HYSTERISIS(val) bfin_write16(PORTF_HYSTERISIS, val)
1099#define bfin_read_PORTG_HYSTERISIS() bfin_read16(PORTG_HYSTERISIS)
1100#define bfin_write_PORTG_HYSTERISIS(val) bfin_write16(PORTG_HYSTERISIS, val)
1101#define bfin_read_PORTH_HYSTERISIS() bfin_read16(PORTH_HYSTERISIS)
1102#define bfin_write_PORTH_HYSTERISIS(val) bfin_write16(PORTH_HYSTERISIS, val)
1103#define bfin_read_MISCPORT_DRIVE() bfin_read16(MISCPORT_DRIVE)
1104#define bfin_write_MISCPORT_DRIVE(val) bfin_write16(MISCPORT_DRIVE, val)
1105#define bfin_read_MISCPORT_SLEW() bfin_read16(MISCPORT_SLEW)
1106#define bfin_write_MISCPORT_SLEW(val) bfin_write16(MISCPORT_SLEW, val)
1107#define bfin_read_MISCPORT_HYSTERISIS() bfin_read16(MISCPORT_HYSTERISIS)
1108#define bfin_write_MISCPORT_HYSTERISIS(val) bfin_write16(MISCPORT_HYSTERISIS, val)
1109
1110/* HOST Port Registers */
1111
1112#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
1113#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
1114#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
1115#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
1116#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
1117#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
1118
1119/* Counter Registers */
1120
1121#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG)
1122#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val)
1123#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK)
1124#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val)
1125#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS)
1126#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val)
1127#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND)
1128#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val)
1129#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE)
1130#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val)
1131#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER)
1132#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val)
1133#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX)
1134#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val)
1135#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
1136#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
1137
1138/* OTP/FUSE Registers */
1139
1140#define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL)
1141#define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val)
1142#define bfin_read_OTP_BEN() bfin_read16(OTP_BEN)
1143#define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val)
1144#define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS)
1145#define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val)
1146#define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING)
1147#define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val)
1148
1149/* Security Registers */
1150
1151#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT)
1152#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val)
1153#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL)
1154#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
1155#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS)
1156#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val)
1157
1158/* OTP Read/Write Data Buffer Registers */
1159
1160#define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0)
1161#define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val)
1162#define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1)
1163#define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val)
1164#define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2)
1165#define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val)
1166#define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3)
1167#define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val)
1168
1169/* NFC Registers */
1170
1171#define bfin_read_NFC_CTL() bfin_read16(NFC_CTL)
1172#define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val)
1173#define bfin_read_NFC_STAT() bfin_read16(NFC_STAT)
1174#define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val)
1175#define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT)
1176#define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val)
1177#define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK)
1178#define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val)
1179#define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0)
1180#define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val)
1181#define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1)
1182#define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val)
1183#define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2)
1184#define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val)
1185#define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3)
1186#define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val)
1187#define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT)
1188#define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val)
1189#define bfin_read_NFC_RST() bfin_read16(NFC_RST)
1190#define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val)
1191#define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL)
1192#define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val)
1193#define bfin_read_NFC_READ() bfin_read16(NFC_READ)
1194#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val)
1195#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR)
1196#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val)
1197#define bfin_read_NFC_CMD() bfin_read16(NFC_CMD)
1198#define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val)
1199#define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR)
1200#define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val)
1201#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD)
1202#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val)
1203
1204#endif /* _CDEF_BF52X_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF522.h b/arch/blackfin/mach-bf527/include/mach/defBF522.h
new file mode 100644
index 000000000000..0a8cdcdf0b49
--- /dev/null
+++ b/arch/blackfin/mach-bf527/include/mach/defBF522.h
@@ -0,0 +1,42 @@
1/*
2 * File: include/asm-blackfin/mach-bf527/defBF522.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _DEF_BF522_H
32#define _DEF_BF522_H
33
34/* Include all Core registers and bit definitions */
35#include <asm/def_LPBlackfin.h>
36
37/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF522 */
38
39/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
40#include "defBF52x_base.h"
41
42#endif /* _DEF_BF522_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF525.h b/arch/blackfin/mach-bf527/include/mach/defBF525.h
new file mode 100644
index 000000000000..5cd7576fef76
--- /dev/null
+++ b/arch/blackfin/mach-bf527/include/mach/defBF525.h
@@ -0,0 +1,713 @@
1/*
2 * File: include/asm-blackfin/mach-bf527/defBF525.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _DEF_BF525_H
32#define _DEF_BF525_H
33
34/* Include all Core registers and bit definitions */
35#include <asm/def_LPBlackfin.h>
36
37/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF525 */
38
39/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
40#include "defBF52x_base.h"
41
42/* The following are the #defines needed by ADSP-BF525 that are not in the common header */
43
44/* USB Control Registers */
45
46#define USB_FADDR 0xffc03800 /* Function address register */
47#define USB_POWER 0xffc03804 /* Power management register */
48#define USB_INTRTX 0xffc03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
49#define USB_INTRRX 0xffc0380c /* Interrupt register for Rx endpoints 1 to 7 */
50#define USB_INTRTXE 0xffc03810 /* Interrupt enable register for IntrTx */
51#define USB_INTRRXE 0xffc03814 /* Interrupt enable register for IntrRx */
52#define USB_INTRUSB 0xffc03818 /* Interrupt register for common USB interrupts */
53#define USB_INTRUSBE 0xffc0381c /* Interrupt enable register for IntrUSB */
54#define USB_FRAME 0xffc03820 /* USB frame number */
55#define USB_INDEX 0xffc03824 /* Index register for selecting the indexed endpoint registers */
56#define USB_TESTMODE 0xffc03828 /* Enabled USB 20 test modes */
57#define USB_GLOBINTR 0xffc0382c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
58#define USB_GLOBAL_CTL 0xffc03830 /* Global Clock Control for the core */
59
60/* USB Packet Control Registers */
61
62#define USB_TX_MAX_PACKET 0xffc03840 /* Maximum packet size for Host Tx endpoint */
63#define USB_CSR0 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
64#define USB_TXCSR 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
65#define USB_RX_MAX_PACKET 0xffc03848 /* Maximum packet size for Host Rx endpoint */
66#define USB_RXCSR 0xffc0384c /* Control Status register for Host Rx endpoint */
67#define USB_COUNT0 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
68#define USB_RXCOUNT 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
69#define USB_TXTYPE 0xffc03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
70#define USB_NAKLIMIT0 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
71#define USB_TXINTERVAL 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
72#define USB_RXTYPE 0xffc0385c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
73#define USB_RXINTERVAL 0xffc03860 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
74#define USB_TXCOUNT 0xffc03868 /* Number of bytes to be written to the selected endpoint Tx FIFO */
75
76/* USB Endpoint FIFO Registers */
77
78#define USB_EP0_FIFO 0xffc03880 /* Endpoint 0 FIFO */
79#define USB_EP1_FIFO 0xffc03888 /* Endpoint 1 FIFO */
80#define USB_EP2_FIFO 0xffc03890 /* Endpoint 2 FIFO */
81#define USB_EP3_FIFO 0xffc03898 /* Endpoint 3 FIFO */
82#define USB_EP4_FIFO 0xffc038a0 /* Endpoint 4 FIFO */
83#define USB_EP5_FIFO 0xffc038a8 /* Endpoint 5 FIFO */
84#define USB_EP6_FIFO 0xffc038b0 /* Endpoint 6 FIFO */
85#define USB_EP7_FIFO 0xffc038b8 /* Endpoint 7 FIFO */
86
87/* USB OTG Control Registers */
88
89#define USB_OTG_DEV_CTL 0xffc03900 /* OTG Device Control Register */
90#define USB_OTG_VBUS_IRQ 0xffc03904 /* OTG VBUS Control Interrupts */
91#define USB_OTG_VBUS_MASK 0xffc03908 /* VBUS Control Interrupt Enable */
92
93/* USB Phy Control Registers */
94
95#define USB_LINKINFO 0xffc03948 /* Enables programming of some PHY-side delays */
96#define USB_VPLEN 0xffc0394c /* Determines duration of VBUS pulse for VBUS charging */
97#define USB_HS_EOF1 0xffc03950 /* Time buffer for High-Speed transactions */
98#define USB_FS_EOF1 0xffc03954 /* Time buffer for Full-Speed transactions */
99#define USB_LS_EOF1 0xffc03958 /* Time buffer for Low-Speed transactions */
100
101/* (APHY_CNTRL is for ADI usage only) */
102
103#define USB_APHY_CNTRL 0xffc039e0 /* Register that increases visibility of Analog PHY */
104
105/* (APHY_CALIB is for ADI usage only) */
106
107#define USB_APHY_CALIB 0xffc039e4 /* Register used to set some calibration values */
108
109#define USB_APHY_CNTRL2 0xffc039e8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
110
111/* (PHY_TEST is for ADI usage only) */
112
113#define USB_PHY_TEST 0xffc039ec /* Used for reducing simulation time and simplifies FIFO testability */
114
115#define USB_PLLOSC_CTRL 0xffc039f0 /* Used to program different parameters for USB PLL and Oscillator */
116#define USB_SRP_CLKDIV 0xffc039f4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
117
118/* USB Endpoint 0 Control Registers */
119
120#define USB_EP_NI0_TXMAXP 0xffc03a00 /* Maximum packet size for Host Tx endpoint0 */
121#define USB_EP_NI0_TXCSR 0xffc03a04 /* Control Status register for endpoint 0 */
122#define USB_EP_NI0_RXMAXP 0xffc03a08 /* Maximum packet size for Host Rx endpoint0 */
123#define USB_EP_NI0_RXCSR 0xffc03a0c /* Control Status register for Host Rx endpoint0 */
124#define USB_EP_NI0_RXCOUNT 0xffc03a10 /* Number of bytes received in endpoint 0 FIFO */
125#define USB_EP_NI0_TXTYPE 0xffc03a14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
126#define USB_EP_NI0_TXINTERVAL 0xffc03a18 /* Sets the NAK response timeout on Endpoint 0 */
127#define USB_EP_NI0_RXTYPE 0xffc03a1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
128#define USB_EP_NI0_RXINTERVAL 0xffc03a20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
129#define USB_EP_NI0_TXCOUNT 0xffc03a28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
130
131/* USB Endpoint 1 Control Registers */
132
133#define USB_EP_NI1_TXMAXP 0xffc03a40 /* Maximum packet size for Host Tx endpoint1 */
134#define USB_EP_NI1_TXCSR 0xffc03a44 /* Control Status register for endpoint1 */
135#define USB_EP_NI1_RXMAXP 0xffc03a48 /* Maximum packet size for Host Rx endpoint1 */
136#define USB_EP_NI1_RXCSR 0xffc03a4c /* Control Status register for Host Rx endpoint1 */
137#define USB_EP_NI1_RXCOUNT 0xffc03a50 /* Number of bytes received in endpoint1 FIFO */
138#define USB_EP_NI1_TXTYPE 0xffc03a54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
139#define USB_EP_NI1_TXINTERVAL 0xffc03a58 /* Sets the NAK response timeout on Endpoint1 */
140#define USB_EP_NI1_RXTYPE 0xffc03a5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
141#define USB_EP_NI1_RXINTERVAL 0xffc03a60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
142#define USB_EP_NI1_TXCOUNT 0xffc03a68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
143
144/* USB Endpoint 2 Control Registers */
145
146#define USB_EP_NI2_TXMAXP 0xffc03a80 /* Maximum packet size for Host Tx endpoint2 */
147#define USB_EP_NI2_TXCSR 0xffc03a84 /* Control Status register for endpoint2 */
148#define USB_EP_NI2_RXMAXP 0xffc03a88 /* Maximum packet size for Host Rx endpoint2 */
149#define USB_EP_NI2_RXCSR 0xffc03a8c /* Control Status register for Host Rx endpoint2 */
150#define USB_EP_NI2_RXCOUNT 0xffc03a90 /* Number of bytes received in endpoint2 FIFO */
151#define USB_EP_NI2_TXTYPE 0xffc03a94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
152#define USB_EP_NI2_TXINTERVAL 0xffc03a98 /* Sets the NAK response timeout on Endpoint2 */
153#define USB_EP_NI2_RXTYPE 0xffc03a9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
154#define USB_EP_NI2_RXINTERVAL 0xffc03aa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
155#define USB_EP_NI2_TXCOUNT 0xffc03aa8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
156
157/* USB Endpoint 3 Control Registers */
158
159#define USB_EP_NI3_TXMAXP 0xffc03ac0 /* Maximum packet size for Host Tx endpoint3 */
160#define USB_EP_NI3_TXCSR 0xffc03ac4 /* Control Status register for endpoint3 */
161#define USB_EP_NI3_RXMAXP 0xffc03ac8 /* Maximum packet size for Host Rx endpoint3 */
162#define USB_EP_NI3_RXCSR 0xffc03acc /* Control Status register for Host Rx endpoint3 */
163#define USB_EP_NI3_RXCOUNT 0xffc03ad0 /* Number of bytes received in endpoint3 FIFO */
164#define USB_EP_NI3_TXTYPE 0xffc03ad4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
165#define USB_EP_NI3_TXINTERVAL 0xffc03ad8 /* Sets the NAK response timeout on Endpoint3 */
166#define USB_EP_NI3_RXTYPE 0xffc03adc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
167#define USB_EP_NI3_RXINTERVAL 0xffc03ae0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
168#define USB_EP_NI3_TXCOUNT 0xffc03ae8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
169
170/* USB Endpoint 4 Control Registers */
171
172#define USB_EP_NI4_TXMAXP 0xffc03b00 /* Maximum packet size for Host Tx endpoint4 */
173#define USB_EP_NI4_TXCSR 0xffc03b04 /* Control Status register for endpoint4 */
174#define USB_EP_NI4_RXMAXP 0xffc03b08 /* Maximum packet size for Host Rx endpoint4 */
175#define USB_EP_NI4_RXCSR 0xffc03b0c /* Control Status register for Host Rx endpoint4 */
176#define USB_EP_NI4_RXCOUNT 0xffc03b10 /* Number of bytes received in endpoint4 FIFO */
177#define USB_EP_NI4_TXTYPE 0xffc03b14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
178#define USB_EP_NI4_TXINTERVAL 0xffc03b18 /* Sets the NAK response timeout on Endpoint4 */
179#define USB_EP_NI4_RXTYPE 0xffc03b1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
180#define USB_EP_NI4_RXINTERVAL 0xffc03b20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
181#define USB_EP_NI4_TXCOUNT 0xffc03b28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
182
183/* USB Endpoint 5 Control Registers */
184
185#define USB_EP_NI5_TXMAXP 0xffc03b40 /* Maximum packet size for Host Tx endpoint5 */
186#define USB_EP_NI5_TXCSR 0xffc03b44 /* Control Status register for endpoint5 */
187#define USB_EP_NI5_RXMAXP 0xffc03b48 /* Maximum packet size for Host Rx endpoint5 */
188#define USB_EP_NI5_RXCSR 0xffc03b4c /* Control Status register for Host Rx endpoint5 */
189#define USB_EP_NI5_RXCOUNT 0xffc03b50 /* Number of bytes received in endpoint5 FIFO */
190#define USB_EP_NI5_TXTYPE 0xffc03b54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
191#define USB_EP_NI5_TXINTERVAL 0xffc03b58 /* Sets the NAK response timeout on Endpoint5 */
192#define USB_EP_NI5_RXTYPE 0xffc03b5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
193#define USB_EP_NI5_RXINTERVAL 0xffc03b60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
194#define USB_EP_NI5_TXCOUNT 0xffc03b68 /* Number of bytes to be written to the endpoint5 Tx FIFO */
195
196/* USB Endpoint 6 Control Registers */
197
198#define USB_EP_NI6_TXMAXP 0xffc03b80 /* Maximum packet size for Host Tx endpoint6 */
199#define USB_EP_NI6_TXCSR 0xffc03b84 /* Control Status register for endpoint6 */
200#define USB_EP_NI6_RXMAXP 0xffc03b88 /* Maximum packet size for Host Rx endpoint6 */
201#define USB_EP_NI6_RXCSR 0xffc03b8c /* Control Status register for Host Rx endpoint6 */
202#define USB_EP_NI6_RXCOUNT 0xffc03b90 /* Number of bytes received in endpoint6 FIFO */
203#define USB_EP_NI6_TXTYPE 0xffc03b94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
204#define USB_EP_NI6_TXINTERVAL 0xffc03b98 /* Sets the NAK response timeout on Endpoint6 */
205#define USB_EP_NI6_RXTYPE 0xffc03b9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
206#define USB_EP_NI6_RXINTERVAL 0xffc03ba0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
207#define USB_EP_NI6_TXCOUNT 0xffc03ba8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
208
209/* USB Endpoint 7 Control Registers */
210
211#define USB_EP_NI7_TXMAXP 0xffc03bc0 /* Maximum packet size for Host Tx endpoint7 */
212#define USB_EP_NI7_TXCSR 0xffc03bc4 /* Control Status register for endpoint7 */
213#define USB_EP_NI7_RXMAXP 0xffc03bc8 /* Maximum packet size for Host Rx endpoint7 */
214#define USB_EP_NI7_RXCSR 0xffc03bcc /* Control Status register for Host Rx endpoint7 */
215#define USB_EP_NI7_RXCOUNT 0xffc03bd0 /* Number of bytes received in endpoint7 FIFO */
216#define USB_EP_NI7_TXTYPE 0xffc03bd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
217#define USB_EP_NI7_TXINTERVAL 0xffc03bd8 /* Sets the NAK response timeout on Endpoint7 */
218#define USB_EP_NI7_RXTYPE 0xffc03bdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
219#define USB_EP_NI7_RXINTERVAL 0xffc03bf0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
220#define USB_EP_NI7_TXCOUNT 0xffc03bf8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
221
222#define USB_DMA_INTERRUPT 0xffc03c00 /* Indicates pending interrupts for the DMA channels */
223
224/* USB Channel 0 Config Registers */
225
226#define USB_DMA0CONTROL 0xffc03c04 /* DMA master channel 0 configuration */
227#define USB_DMA0ADDRLOW 0xffc03c08 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
228#define USB_DMA0ADDRHIGH 0xffc03c0c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
229#define USB_DMA0COUNTLOW 0xffc03c10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
230#define USB_DMA0COUNTHIGH 0xffc03c14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
231
232/* USB Channel 1 Config Registers */
233
234#define USB_DMA1CONTROL 0xffc03c24 /* DMA master channel 1 configuration */
235#define USB_DMA1ADDRLOW 0xffc03c28 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
236#define USB_DMA1ADDRHIGH 0xffc03c2c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
237#define USB_DMA1COUNTLOW 0xffc03c30 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
238#define USB_DMA1COUNTHIGH 0xffc03c34 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
239
240/* USB Channel 2 Config Registers */
241
242#define USB_DMA2CONTROL 0xffc03c44 /* DMA master channel 2 configuration */
243#define USB_DMA2ADDRLOW 0xffc03c48 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
244#define USB_DMA2ADDRHIGH 0xffc03c4c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
245#define USB_DMA2COUNTLOW 0xffc03c50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
246#define USB_DMA2COUNTHIGH 0xffc03c54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
247
248/* USB Channel 3 Config Registers */
249
250#define USB_DMA3CONTROL 0xffc03c64 /* DMA master channel 3 configuration */
251#define USB_DMA3ADDRLOW 0xffc03c68 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
252#define USB_DMA3ADDRHIGH 0xffc03c6c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
253#define USB_DMA3COUNTLOW 0xffc03c70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
254#define USB_DMA3COUNTHIGH 0xffc03c74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
255
256/* USB Channel 4 Config Registers */
257
258#define USB_DMA4CONTROL 0xffc03c84 /* DMA master channel 4 configuration */
259#define USB_DMA4ADDRLOW 0xffc03c88 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
260#define USB_DMA4ADDRHIGH 0xffc03c8c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
261#define USB_DMA4COUNTLOW 0xffc03c90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
262#define USB_DMA4COUNTHIGH 0xffc03c94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
263
264/* USB Channel 5 Config Registers */
265
266#define USB_DMA5CONTROL 0xffc03ca4 /* DMA master channel 5 configuration */
267#define USB_DMA5ADDRLOW 0xffc03ca8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
268#define USB_DMA5ADDRHIGH 0xffc03cac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
269#define USB_DMA5COUNTLOW 0xffc03cb0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
270#define USB_DMA5COUNTHIGH 0xffc03cb4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
271
272/* USB Channel 6 Config Registers */
273
274#define USB_DMA6CONTROL 0xffc03cc4 /* DMA master channel 6 configuration */
275#define USB_DMA6ADDRLOW 0xffc03cc8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
276#define USB_DMA6ADDRHIGH 0xffc03ccc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
277#define USB_DMA6COUNTLOW 0xffc03cd0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
278#define USB_DMA6COUNTHIGH 0xffc03cd4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
279
280/* USB Channel 7 Config Registers */
281
282#define USB_DMA7CONTROL 0xffc03ce4 /* DMA master channel 7 configuration */
283#define USB_DMA7ADDRLOW 0xffc03ce8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
284#define USB_DMA7ADDRHIGH 0xffc03cec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
285#define USB_DMA7COUNTLOW 0xffc03cf0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
286#define USB_DMA7COUNTHIGH 0xffc03cf4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
287
288/* Bit masks for USB_FADDR */
289
290#define FUNCTION_ADDRESS 0x7f /* Function address */
291
292/* Bit masks for USB_POWER */
293
294#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
295#define nENABLE_SUSPENDM 0x0
296#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
297#define nSUSPEND_MODE 0x0
298#define RESUME_MODE 0x4 /* DMA Mode */
299#define nRESUME_MODE 0x0
300#define RESET 0x8 /* Reset indicator */
301#define nRESET 0x0
302#define HS_MODE 0x10 /* High Speed mode indicator */
303#define nHS_MODE 0x0
304#define HS_ENABLE 0x20 /* high Speed Enable */
305#define nHS_ENABLE 0x0
306#define SOFT_CONN 0x40 /* Soft connect */
307#define nSOFT_CONN 0x0
308#define ISO_UPDATE 0x80 /* Isochronous update */
309#define nISO_UPDATE 0x0
310
311/* Bit masks for USB_INTRTX */
312
313#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
314#define nEP0_TX 0x0
315#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
316#define nEP1_TX 0x0
317#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
318#define nEP2_TX 0x0
319#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
320#define nEP3_TX 0x0
321#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
322#define nEP4_TX 0x0
323#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
324#define nEP5_TX 0x0
325#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
326#define nEP6_TX 0x0
327#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
328#define nEP7_TX 0x0
329
330/* Bit masks for USB_INTRRX */
331
332#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
333#define nEP1_RX 0x0
334#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
335#define nEP2_RX 0x0
336#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
337#define nEP3_RX 0x0
338#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
339#define nEP4_RX 0x0
340#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
341#define nEP5_RX 0x0
342#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
343#define nEP6_RX 0x0
344#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
345#define nEP7_RX 0x0
346
347/* Bit masks for USB_INTRTXE */
348
349#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
350#define nEP0_TX_E 0x0
351#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
352#define nEP1_TX_E 0x0
353#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
354#define nEP2_TX_E 0x0
355#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
356#define nEP3_TX_E 0x0
357#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
358#define nEP4_TX_E 0x0
359#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
360#define nEP5_TX_E 0x0
361#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
362#define nEP6_TX_E 0x0
363#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
364#define nEP7_TX_E 0x0
365
366/* Bit masks for USB_INTRRXE */
367
368#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
369#define nEP1_RX_E 0x0
370#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
371#define nEP2_RX_E 0x0
372#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
373#define nEP3_RX_E 0x0
374#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
375#define nEP4_RX_E 0x0
376#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
377#define nEP5_RX_E 0x0
378#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
379#define nEP6_RX_E 0x0
380#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
381#define nEP7_RX_E 0x0
382
383/* Bit masks for USB_INTRUSB */
384
385#define SUSPEND_B 0x1 /* Suspend indicator */
386#define nSUSPEND_B 0x0
387#define RESUME_B 0x2 /* Resume indicator */
388#define nRESUME_B 0x0
389#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
390#define nRESET_OR_BABLE_B 0x0
391#define SOF_B 0x8 /* Start of frame */
392#define nSOF_B 0x0
393#define CONN_B 0x10 /* Connection indicator */
394#define nCONN_B 0x0
395#define DISCON_B 0x20 /* Disconnect indicator */
396#define nDISCON_B 0x0
397#define SESSION_REQ_B 0x40 /* Session Request */
398#define nSESSION_REQ_B 0x0
399#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
400#define nVBUS_ERROR_B 0x0
401
402/* Bit masks for USB_INTRUSBE */
403
404#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
405#define nSUSPEND_BE 0x0
406#define RESUME_BE 0x2 /* Resume indicator int enable */
407#define nRESUME_BE 0x0
408#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
409#define nRESET_OR_BABLE_BE 0x0
410#define SOF_BE 0x8 /* Start of frame int enable */
411#define nSOF_BE 0x0
412#define CONN_BE 0x10 /* Connection indicator int enable */
413#define nCONN_BE 0x0
414#define DISCON_BE 0x20 /* Disconnect indicator int enable */
415#define nDISCON_BE 0x0
416#define SESSION_REQ_BE 0x40 /* Session Request int enable */
417#define nSESSION_REQ_BE 0x0
418#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
419#define nVBUS_ERROR_BE 0x0
420
421/* Bit masks for USB_FRAME */
422
423#define FRAME_NUMBER 0x7ff /* Frame number */
424
425/* Bit masks for USB_INDEX */
426
427#define SELECTED_ENDPOINT 0xf /* selected endpoint */
428
429/* Bit masks for USB_GLOBAL_CTL */
430
431#define GLOBAL_ENA 0x1 /* enables USB module */
432#define nGLOBAL_ENA 0x0
433#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
434#define nEP1_TX_ENA 0x0
435#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
436#define nEP2_TX_ENA 0x0
437#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
438#define nEP3_TX_ENA 0x0
439#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
440#define nEP4_TX_ENA 0x0
441#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
442#define nEP5_TX_ENA 0x0
443#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
444#define nEP6_TX_ENA 0x0
445#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
446#define nEP7_TX_ENA 0x0
447#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
448#define nEP1_RX_ENA 0x0
449#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
450#define nEP2_RX_ENA 0x0
451#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
452#define nEP3_RX_ENA 0x0
453#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
454#define nEP4_RX_ENA 0x0
455#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
456#define nEP5_RX_ENA 0x0
457#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
458#define nEP6_RX_ENA 0x0
459#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
460#define nEP7_RX_ENA 0x0
461
462/* Bit masks for USB_OTG_DEV_CTL */
463
464#define SESSION 0x1 /* session indicator */
465#define nSESSION 0x0
466#define HOST_REQ 0x2 /* Host negotiation request */
467#define nHOST_REQ 0x0
468#define HOST_MODE 0x4 /* indicates USBDRC is a host */
469#define nHOST_MODE 0x0
470#define VBUS0 0x8 /* Vbus level indicator[0] */
471#define nVBUS0 0x0
472#define VBUS1 0x10 /* Vbus level indicator[1] */
473#define nVBUS1 0x0
474#define LSDEV 0x20 /* Low-speed indicator */
475#define nLSDEV 0x0
476#define FSDEV 0x40 /* Full or High-speed indicator */
477#define nFSDEV 0x0
478#define B_DEVICE 0x80 /* A' or 'B' device indicator */
479#define nB_DEVICE 0x0
480
481/* Bit masks for USB_OTG_VBUS_IRQ */
482
483#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
484#define nDRIVE_VBUS_ON 0x0
485#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
486#define nDRIVE_VBUS_OFF 0x0
487#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
488#define nCHRG_VBUS_START 0x0
489#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
490#define nCHRG_VBUS_END 0x0
491#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
492#define nDISCHRG_VBUS_START 0x0
493#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
494#define nDISCHRG_VBUS_END 0x0
495
496/* Bit masks for USB_OTG_VBUS_MASK */
497
498#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
499#define nDRIVE_VBUS_ON_ENA 0x0
500#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
501#define nDRIVE_VBUS_OFF_ENA 0x0
502#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
503#define nCHRG_VBUS_START_ENA 0x0
504#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
505#define nCHRG_VBUS_END_ENA 0x0
506#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
507#define nDISCHRG_VBUS_START_ENA 0x0
508#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
509#define nDISCHRG_VBUS_END_ENA 0x0
510
511/* Bit masks for USB_CSR0 */
512
513#define RXPKTRDY 0x1 /* data packet receive indicator */
514#define nRXPKTRDY 0x0
515#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
516#define nTXPKTRDY 0x0
517#define STALL_SENT 0x4 /* STALL handshake sent */
518#define nSTALL_SENT 0x0
519#define DATAEND 0x8 /* Data end indicator */
520#define nDATAEND 0x0
521#define SETUPEND 0x10 /* Setup end */
522#define nSETUPEND 0x0
523#define SENDSTALL 0x20 /* Send STALL handshake */
524#define nSENDSTALL 0x0
525#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
526#define nSERVICED_RXPKTRDY 0x0
527#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
528#define nSERVICED_SETUPEND 0x0
529#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
530#define nFLUSHFIFO 0x0
531#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
532#define nSTALL_RECEIVED_H 0x0
533#define SETUPPKT_H 0x8 /* send Setup token host mode */
534#define nSETUPPKT_H 0x0
535#define ERROR_H 0x10 /* timeout error indicator host mode */
536#define nERROR_H 0x0
537#define REQPKT_H 0x20 /* Request an IN transaction host mode */
538#define nREQPKT_H 0x0
539#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
540#define nSTATUSPKT_H 0x0
541#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
542#define nNAK_TIMEOUT_H 0x0
543
544/* Bit masks for USB_COUNT0 */
545
546#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
547
548/* Bit masks for USB_NAKLIMIT0 */
549
550#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
551
552/* Bit masks for USB_TX_MAX_PACKET */
553
554#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
555
556/* Bit masks for USB_RX_MAX_PACKET */
557
558#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
559
560/* Bit masks for USB_TXCSR */
561
562#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
563#define nTXPKTRDY_T 0x0
564#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
565#define nFIFO_NOT_EMPTY_T 0x0
566#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
567#define nUNDERRUN_T 0x0
568#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
569#define nFLUSHFIFO_T 0x0
570#define STALL_SEND_T 0x10 /* issue a Stall handshake */
571#define nSTALL_SEND_T 0x0
572#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
573#define nSTALL_SENT_T 0x0
574#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
575#define nCLEAR_DATATOGGLE_T 0x0
576#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
577#define nINCOMPTX_T 0x0
578#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
579#define nDMAREQMODE_T 0x0
580#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
581#define nFORCE_DATATOGGLE_T 0x0
582#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
583#define nDMAREQ_ENA_T 0x0
584#define ISO_T 0x4000 /* enable Isochronous transfers */
585#define nISO_T 0x0
586#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
587#define nAUTOSET_T 0x0
588#define ERROR_TH 0x4 /* error condition host mode */
589#define nERROR_TH 0x0
590#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
591#define nSTALL_RECEIVED_TH 0x0
592#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
593#define nNAK_TIMEOUT_TH 0x0
594
595/* Bit masks for USB_TXCOUNT */
596
597#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
598
599/* Bit masks for USB_RXCSR */
600
601#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
602#define nRXPKTRDY_R 0x0
603#define FIFO_FULL_R 0x2 /* FIFO not empty */
604#define nFIFO_FULL_R 0x0
605#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
606#define nOVERRUN_R 0x0
607#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
608#define nDATAERROR_R 0x0
609#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
610#define nFLUSHFIFO_R 0x0
611#define STALL_SEND_R 0x20 /* issue a Stall handshake */
612#define nSTALL_SEND_R 0x0
613#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
614#define nSTALL_SENT_R 0x0
615#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
616#define nCLEAR_DATATOGGLE_R 0x0
617#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
618#define nINCOMPRX_R 0x0
619#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
620#define nDMAREQMODE_R 0x0
621#define DISNYET_R 0x1000 /* disable Nyet handshakes */
622#define nDISNYET_R 0x0
623#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
624#define nDMAREQ_ENA_R 0x0
625#define ISO_R 0x4000 /* enable Isochronous transfers */
626#define nISO_R 0x0
627#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
628#define nAUTOCLEAR_R 0x0
629#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
630#define nERROR_RH 0x0
631#define REQPKT_RH 0x20 /* request an IN transaction host mode */
632#define nREQPKT_RH 0x0
633#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
634#define nSTALL_RECEIVED_RH 0x0
635#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
636#define nINCOMPRX_RH 0x0
637#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
638#define nDMAREQMODE_RH 0x0
639#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
640#define nAUTOREQ_RH 0x0
641
642/* Bit masks for USB_RXCOUNT */
643
644#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
645
646/* Bit masks for USB_TXTYPE */
647
648#define TARGET_EP_NO_T 0xf /* EP number */
649#define PROTOCOL_T 0xc /* transfer type */
650
651/* Bit masks for USB_TXINTERVAL */
652
653#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
654
655/* Bit masks for USB_RXTYPE */
656
657#define TARGET_EP_NO_R 0xf /* EP number */
658#define PROTOCOL_R 0xc /* transfer type */
659
660/* Bit masks for USB_RXINTERVAL */
661
662#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
663
664/* Bit masks for USB_DMA_INTERRUPT */
665
666#define DMA0_INT 0x1 /* DMA0 pending interrupt */
667#define nDMA0_INT 0x0
668#define DMA1_INT 0x2 /* DMA1 pending interrupt */
669#define nDMA1_INT 0x0
670#define DMA2_INT 0x4 /* DMA2 pending interrupt */
671#define nDMA2_INT 0x0
672#define DMA3_INT 0x8 /* DMA3 pending interrupt */
673#define nDMA3_INT 0x0
674#define DMA4_INT 0x10 /* DMA4 pending interrupt */
675#define nDMA4_INT 0x0
676#define DMA5_INT 0x20 /* DMA5 pending interrupt */
677#define nDMA5_INT 0x0
678#define DMA6_INT 0x40 /* DMA6 pending interrupt */
679#define nDMA6_INT 0x0
680#define DMA7_INT 0x80 /* DMA7 pending interrupt */
681#define nDMA7_INT 0x0
682
683/* Bit masks for USB_DMAxCONTROL */
684
685#define DMA_ENA 0x1 /* DMA enable */
686#define nDMA_ENA 0x0
687#define DIRECTION 0x2 /* direction of DMA transfer */
688#define nDIRECTION 0x0
689#define MODE 0x4 /* DMA Bus error */
690#define nMODE 0x0
691#define INT_ENA 0x8 /* Interrupt enable */
692#define nINT_ENA 0x0
693#define EPNUM 0xf0 /* EP number */
694#define BUSERROR 0x100 /* DMA Bus error */
695#define nBUSERROR 0x0
696
697/* Bit masks for USB_DMAxADDRHIGH */
698
699#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
700
701/* Bit masks for USB_DMAxADDRLOW */
702
703#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
704
705/* Bit masks for USB_DMAxCOUNTHIGH */
706
707#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
708
709/* Bit masks for USB_DMAxCOUNTLOW */
710
711#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
712
713#endif /* _DEF_BF525_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF527.h b/arch/blackfin/mach-bf527/include/mach/defBF527.h
new file mode 100644
index 000000000000..f040f364afa3
--- /dev/null
+++ b/arch/blackfin/mach-bf527/include/mach/defBF527.h
@@ -0,0 +1,1090 @@
1/*
2 * File: include/asm-blackfin/mach-bf527/defBF527.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _DEF_BF527_H
32#define _DEF_BF527_H
33
34/* Include all Core registers and bit definitions */
35#include <asm/def_LPBlackfin.h>
36
37/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF527 */
38
39/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
40#include "defBF52x_base.h"
41
42/* The following are the #defines needed by ADSP-BF527 that are not in the common header */
43/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
44
45#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
46#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
47#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
48#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
49#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
50#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */
51#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */
52#define EMAC_FLC 0xFFC0301C /* Flow Control Register */
53#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */
54#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */
55#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */
56#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
57#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
58#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
59#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
60#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */
61#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
62#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
63#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
64
65#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */
66#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */
67#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */
68#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */
69#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */
70#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */
71#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */
72#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */
73
74#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */
75#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */
76#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */
77#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */
78#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */
79
80#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */
81#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */
82#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */
83#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */
84#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
85#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */
86#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */
87#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */
88#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */
89#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */
90#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */
91#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */
92#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */
93#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */
94#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */
95#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */
96#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */
97#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
98#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
99#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 < x < 128 */
100#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
101#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
102#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
103#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
104
105#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */
106#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */
107#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
108#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */
109#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
110#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */
111#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
112#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
113#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
114#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */
115#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */
116#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */
117#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */
118#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */
119#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */
120#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */
121#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
122#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 < x < 128 */
123#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
124#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
125#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
126#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
127#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */
128
129/* Listing for IEEE-Supported Count Registers */
130
131#define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */
132#define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */
133#define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */
134#define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */
135#define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */
136#define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */
137#define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */
138#define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */
139#define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */
140#define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */
141#define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */
142#define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */
143#define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */
144#define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */
145#define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */
146#define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */
147#define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */
148#define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */
149#define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */
150#define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 < x < 128 */
151#define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
152#define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
153#define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
154#define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */
155
156#define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */
157#define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */
158#define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */
159#define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */
160#define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */
161#define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */
162#define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */
163#define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */
164#define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */
165#define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */
166#define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */
167#define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */
168#define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */
169#define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */
170#define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */
171#define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */
172#define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */
173#define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 < x < 128 */
174#define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
175#define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */
176#define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
177#define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */
178#define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */
179
180/***********************************************************************************
181** System MMR Register Bits And Macros
182**
183** Disclaimer: All macros are intended to make C and Assembly code more readable.
184** Use these macros carefully, as any that do left shifts for field
185** depositing will result in the lower order bits being destroyed. Any
186** macro that shifts left to properly position the bit-field should be
187** used as part of an OR to initialize a register and NOT as a dynamic
188** modifier UNLESS the lower order bits are saved and ORed back in when
189** the macro is used.
190*************************************************************************************/
191
192/************************ ETHERNET 10/100 CONTROLLER MASKS ************************/
193
194/* EMAC_OPMODE Masks */
195
196#define RE 0x00000001 /* Receiver Enable */
197#define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */
198#define HU 0x00000010 /* Hash Filter Unicast Address */
199#define HM 0x00000020 /* Hash Filter Multicast Address */
200#define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */
201#define PR 0x00000080 /* Promiscuous Mode Enable */
202#define IFE 0x00000100 /* Inverse Filtering Enable */
203#define DBF 0x00000200 /* Disable Broadcast Frame Reception */
204#define PBF 0x00000400 /* Pass Bad Frames Enable */
205#define PSF 0x00000800 /* Pass Short Frames Enable */
206#define RAF 0x00001000 /* Receive-All Mode */
207#define TE 0x00010000 /* Transmitter Enable */
208#define DTXPAD 0x00020000 /* Disable Automatic TX Padding */
209#define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */
210#define DC 0x00080000 /* Deferral Check */
211#define BOLMT 0x00300000 /* Back-Off Limit */
212#define BOLMT_10 0x00000000 /* 10-bit range */
213#define BOLMT_8 0x00100000 /* 8-bit range */
214#define BOLMT_4 0x00200000 /* 4-bit range */
215#define BOLMT_1 0x00300000 /* 1-bit range */
216#define DRTY 0x00400000 /* Disable TX Retry On Collision */
217#define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */
218#define RMII 0x01000000 /* RMII/MII* Mode */
219#define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */
220#define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */
221#define LB 0x08000000 /* Internal Loopback Enable */
222#define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */
223
224/* EMAC_STAADD Masks */
225
226#define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */
227#define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */
228#define STADISPRE 0x00000004 /* Disable Preamble Generation */
229#define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */
230#define REGAD 0x000007C0 /* STA Register Address */
231#define PHYAD 0x0000F800 /* PHY Device Address */
232
233#define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */
234#define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */
235
236/* EMAC_STADAT Mask */
237
238#define STADATA 0x0000FFFF /* Station Management Data */
239
240/* EMAC_FLC Masks */
241
242#define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */
243#define FLCE 0x00000002 /* Flow Control Enable */
244#define PCF 0x00000004 /* Pass Control Frames */
245#define BKPRSEN 0x00000008 /* Enable Backpressure */
246#define FLCPAUSE 0xFFFF0000 /* Pause Time */
247
248#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */
249
250/* EMAC_WKUP_CTL Masks */
251
252#define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */
253#define MPKE 0x00000002 /* Magic Packet Enable */
254#define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */
255#define GUWKE 0x00000008 /* Global Unicast Wake Enable */
256#define MPKS 0x00000020 /* Magic Packet Received Status */
257#define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */
258
259/* EMAC_WKUP_FFCMD Masks */
260
261#define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */
262#define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */
263#define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */
264#define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */
265#define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */
266#define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */
267#define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */
268#define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */
269
270/* EMAC_WKUP_FFOFF Masks */
271
272#define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */
273#define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */
274#define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */
275#define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */
276
277#define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */
278#define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */
279#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */
280#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */
281/* Set ALL Offsets */
282#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
283
284/* EMAC_WKUP_FFCRC0 Masks */
285
286#define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */
287#define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */
288
289#define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */
290#define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */
291
292/* EMAC_WKUP_FFCRC1 Masks */
293
294#define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */
295#define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */
296
297#define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */
298#define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */
299
300/* EMAC_SYSCTL Masks */
301
302#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */
303#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */
304#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */
305#define TXDWA 0x00000010 /* Transmit Frame DMA Word Alignment (Odd/Even*) */
306#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
307
308#define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */
309
310/* EMAC_SYSTAT Masks */
311
312#define PHYINT 0x00000001 /* PHY_INT Interrupt Status */
313#define MMCINT 0x00000002 /* MMC Counter Interrupt Status */
314#define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */
315#define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */
316#define WAKEDET 0x00000010 /* Wake-Up Detected Status */
317#define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */
318#define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */
319#define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */
320
321/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
322
323#define RX_FRLEN 0x000007FF /* Frame Length In Bytes */
324#define RX_COMP 0x00001000 /* RX Frame Complete */
325#define RX_OK 0x00002000 /* RX Frame Received With No Errors */
326#define RX_LONG 0x00004000 /* RX Frame Too Long Error */
327#define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */
328#define RX_CRC 0x00010000 /* RX Frame CRC Error */
329#define RX_LEN 0x00020000 /* RX Frame Length Error */
330#define RX_FRAG 0x00040000 /* RX Frame Fragment Error */
331#define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */
332#define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */
333#define RX_PHY 0x00200000 /* RX Frame PHY Error */
334#define RX_LATE 0x00400000 /* RX Frame Late Collision Error */
335#define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */
336#define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */
337#define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */
338#define RX_CTL 0x04000000 /* RX Control Frame Indicator */
339#define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */
340#define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */
341#define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */
342#define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */
343#define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */
344
345/* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */
346
347#define TX_COMP 0x00000001 /* TX Frame Complete */
348#define TX_OK 0x00000002 /* TX Frame Sent With No Errors */
349#define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */
350#define TX_LATE 0x00000008 /* TX Frame Late Collision Error */
351#define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */
352#define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */
353#define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */
354#define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */
355#define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */
356#define TX_CCNT 0x00000F00 /* TX Frame Collision Count */
357#define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */
358#define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */
359#define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */
360#define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */
361#define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */
362
363/* EMAC_MMC_CTL Masks */
364#define RSTC 0x00000001 /* Reset All Counters */
365#define CROLL 0x00000002 /* Counter Roll-Over Enable */
366#define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */
367#define MMCE 0x00000008 /* Enable MMC Counter Operation */
368
369/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
370#define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */
371#define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */
372#define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */
373#define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */
374#define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */
375#define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */
376#define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */
377#define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */
378#define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */
379#define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */
380#define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */
381#define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */
382#define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */
383#define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */
384#define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */
385#define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */
386#define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */
387#define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */
388#define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */
389#define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */
390#define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */
391#define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */
392#define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */
393#define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */
394
395/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */
396
397#define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */
398#define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */
399#define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */
400#define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */
401#define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */
402#define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */
403#define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */
404#define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */
405#define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */
406#define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */
407#define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */
408#define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */
409#define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */
410#define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */
411#define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */
412#define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */
413#define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */
414#define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */
415#define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */
416#define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */
417#define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */
418#define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */
419#define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */
420
421/* USB Control Registers */
422
423#define USB_FADDR 0xffc03800 /* Function address register */
424#define USB_POWER 0xffc03804 /* Power management register */
425#define USB_INTRTX 0xffc03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
426#define USB_INTRRX 0xffc0380c /* Interrupt register for Rx endpoints 1 to 7 */
427#define USB_INTRTXE 0xffc03810 /* Interrupt enable register for IntrTx */
428#define USB_INTRRXE 0xffc03814 /* Interrupt enable register for IntrRx */
429#define USB_INTRUSB 0xffc03818 /* Interrupt register for common USB interrupts */
430#define USB_INTRUSBE 0xffc0381c /* Interrupt enable register for IntrUSB */
431#define USB_FRAME 0xffc03820 /* USB frame number */
432#define USB_INDEX 0xffc03824 /* Index register for selecting the indexed endpoint registers */
433#define USB_TESTMODE 0xffc03828 /* Enabled USB 20 test modes */
434#define USB_GLOBINTR 0xffc0382c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
435#define USB_GLOBAL_CTL 0xffc03830 /* Global Clock Control for the core */
436
437/* USB Packet Control Registers */
438
439#define USB_TX_MAX_PACKET 0xffc03840 /* Maximum packet size for Host Tx endpoint */
440#define USB_CSR0 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
441#define USB_TXCSR 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
442#define USB_RX_MAX_PACKET 0xffc03848 /* Maximum packet size for Host Rx endpoint */
443#define USB_RXCSR 0xffc0384c /* Control Status register for Host Rx endpoint */
444#define USB_COUNT0 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
445#define USB_RXCOUNT 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
446#define USB_TXTYPE 0xffc03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
447#define USB_NAKLIMIT0 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
448#define USB_TXINTERVAL 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
449#define USB_RXTYPE 0xffc0385c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
450#define USB_RXINTERVAL 0xffc03860 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
451#define USB_TXCOUNT 0xffc03868 /* Number of bytes to be written to the selected endpoint Tx FIFO */
452
453/* USB Endpoint FIFO Registers */
454
455#define USB_EP0_FIFO 0xffc03880 /* Endpoint 0 FIFO */
456#define USB_EP1_FIFO 0xffc03888 /* Endpoint 1 FIFO */
457#define USB_EP2_FIFO 0xffc03890 /* Endpoint 2 FIFO */
458#define USB_EP3_FIFO 0xffc03898 /* Endpoint 3 FIFO */
459#define USB_EP4_FIFO 0xffc038a0 /* Endpoint 4 FIFO */
460#define USB_EP5_FIFO 0xffc038a8 /* Endpoint 5 FIFO */
461#define USB_EP6_FIFO 0xffc038b0 /* Endpoint 6 FIFO */
462#define USB_EP7_FIFO 0xffc038b8 /* Endpoint 7 FIFO */
463
464/* USB OTG Control Registers */
465
466#define USB_OTG_DEV_CTL 0xffc03900 /* OTG Device Control Register */
467#define USB_OTG_VBUS_IRQ 0xffc03904 /* OTG VBUS Control Interrupts */
468#define USB_OTG_VBUS_MASK 0xffc03908 /* VBUS Control Interrupt Enable */
469
470/* USB Phy Control Registers */
471
472#define USB_LINKINFO 0xffc03948 /* Enables programming of some PHY-side delays */
473#define USB_VPLEN 0xffc0394c /* Determines duration of VBUS pulse for VBUS charging */
474#define USB_HS_EOF1 0xffc03950 /* Time buffer for High-Speed transactions */
475#define USB_FS_EOF1 0xffc03954 /* Time buffer for Full-Speed transactions */
476#define USB_LS_EOF1 0xffc03958 /* Time buffer for Low-Speed transactions */
477
478/* (APHY_CNTRL is for ADI usage only) */
479
480#define USB_APHY_CNTRL 0xffc039e0 /* Register that increases visibility of Analog PHY */
481
482/* (APHY_CALIB is for ADI usage only) */
483
484#define USB_APHY_CALIB 0xffc039e4 /* Register used to set some calibration values */
485
486#define USB_APHY_CNTRL2 0xffc039e8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
487
488/* (PHY_TEST is for ADI usage only) */
489
490#define USB_PHY_TEST 0xffc039ec /* Used for reducing simulation time and simplifies FIFO testability */
491
492#define USB_PLLOSC_CTRL 0xffc039f0 /* Used to program different parameters for USB PLL and Oscillator */
493#define USB_SRP_CLKDIV 0xffc039f4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
494
495/* USB Endpoint 0 Control Registers */
496
497#define USB_EP_NI0_TXMAXP 0xffc03a00 /* Maximum packet size for Host Tx endpoint0 */
498#define USB_EP_NI0_TXCSR 0xffc03a04 /* Control Status register for endpoint 0 */
499#define USB_EP_NI0_RXMAXP 0xffc03a08 /* Maximum packet size for Host Rx endpoint0 */
500#define USB_EP_NI0_RXCSR 0xffc03a0c /* Control Status register for Host Rx endpoint0 */
501#define USB_EP_NI0_RXCOUNT 0xffc03a10 /* Number of bytes received in endpoint 0 FIFO */
502#define USB_EP_NI0_TXTYPE 0xffc03a14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
503#define USB_EP_NI0_TXINTERVAL 0xffc03a18 /* Sets the NAK response timeout on Endpoint 0 */
504#define USB_EP_NI0_RXTYPE 0xffc03a1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
505#define USB_EP_NI0_RXINTERVAL 0xffc03a20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
506#define USB_EP_NI0_TXCOUNT 0xffc03a28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
507
508/* USB Endpoint 1 Control Registers */
509
510#define USB_EP_NI1_TXMAXP 0xffc03a40 /* Maximum packet size for Host Tx endpoint1 */
511#define USB_EP_NI1_TXCSR 0xffc03a44 /* Control Status register for endpoint1 */
512#define USB_EP_NI1_RXMAXP 0xffc03a48 /* Maximum packet size for Host Rx endpoint1 */
513#define USB_EP_NI1_RXCSR 0xffc03a4c /* Control Status register for Host Rx endpoint1 */
514#define USB_EP_NI1_RXCOUNT 0xffc03a50 /* Number of bytes received in endpoint1 FIFO */
515#define USB_EP_NI1_TXTYPE 0xffc03a54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
516#define USB_EP_NI1_TXINTERVAL 0xffc03a58 /* Sets the NAK response timeout on Endpoint1 */
517#define USB_EP_NI1_RXTYPE 0xffc03a5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
518#define USB_EP_NI1_RXINTERVAL 0xffc03a60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
519#define USB_EP_NI1_TXCOUNT 0xffc03a68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
520
521/* USB Endpoint 2 Control Registers */
522
523#define USB_EP_NI2_TXMAXP 0xffc03a80 /* Maximum packet size for Host Tx endpoint2 */
524#define USB_EP_NI2_TXCSR 0xffc03a84 /* Control Status register for endpoint2 */
525#define USB_EP_NI2_RXMAXP 0xffc03a88 /* Maximum packet size for Host Rx endpoint2 */
526#define USB_EP_NI2_RXCSR 0xffc03a8c /* Control Status register for Host Rx endpoint2 */
527#define USB_EP_NI2_RXCOUNT 0xffc03a90 /* Number of bytes received in endpoint2 FIFO */
528#define USB_EP_NI2_TXTYPE 0xffc03a94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
529#define USB_EP_NI2_TXINTERVAL 0xffc03a98 /* Sets the NAK response timeout on Endpoint2 */
530#define USB_EP_NI2_RXTYPE 0xffc03a9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
531#define USB_EP_NI2_RXINTERVAL 0xffc03aa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
532#define USB_EP_NI2_TXCOUNT 0xffc03aa8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
533
534/* USB Endpoint 3 Control Registers */
535
536#define USB_EP_NI3_TXMAXP 0xffc03ac0 /* Maximum packet size for Host Tx endpoint3 */
537#define USB_EP_NI3_TXCSR 0xffc03ac4 /* Control Status register for endpoint3 */
538#define USB_EP_NI3_RXMAXP 0xffc03ac8 /* Maximum packet size for Host Rx endpoint3 */
539#define USB_EP_NI3_RXCSR 0xffc03acc /* Control Status register for Host Rx endpoint3 */
540#define USB_EP_NI3_RXCOUNT 0xffc03ad0 /* Number of bytes received in endpoint3 FIFO */
541#define USB_EP_NI3_TXTYPE 0xffc03ad4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
542#define USB_EP_NI3_TXINTERVAL 0xffc03ad8 /* Sets the NAK response timeout on Endpoint3 */
543#define USB_EP_NI3_RXTYPE 0xffc03adc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
544#define USB_EP_NI3_RXINTERVAL 0xffc03ae0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
545#define USB_EP_NI3_TXCOUNT 0xffc03ae8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
546
547/* USB Endpoint 4 Control Registers */
548
549#define USB_EP_NI4_TXMAXP 0xffc03b00 /* Maximum packet size for Host Tx endpoint4 */
550#define USB_EP_NI4_TXCSR 0xffc03b04 /* Control Status register for endpoint4 */
551#define USB_EP_NI4_RXMAXP 0xffc03b08 /* Maximum packet size for Host Rx endpoint4 */
552#define USB_EP_NI4_RXCSR 0xffc03b0c /* Control Status register for Host Rx endpoint4 */
553#define USB_EP_NI4_RXCOUNT 0xffc03b10 /* Number of bytes received in endpoint4 FIFO */
554#define USB_EP_NI4_TXTYPE 0xffc03b14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
555#define USB_EP_NI4_TXINTERVAL 0xffc03b18 /* Sets the NAK response timeout on Endpoint4 */
556#define USB_EP_NI4_RXTYPE 0xffc03b1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
557#define USB_EP_NI4_RXINTERVAL 0xffc03b20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
558#define USB_EP_NI4_TXCOUNT 0xffc03b28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
559
560/* USB Endpoint 5 Control Registers */
561
562#define USB_EP_NI5_TXMAXP 0xffc03b40 /* Maximum packet size for Host Tx endpoint5 */
563#define USB_EP_NI5_TXCSR 0xffc03b44 /* Control Status register for endpoint5 */
564#define USB_EP_NI5_RXMAXP 0xffc03b48 /* Maximum packet size for Host Rx endpoint5 */
565#define USB_EP_NI5_RXCSR 0xffc03b4c /* Control Status register for Host Rx endpoint5 */
566#define USB_EP_NI5_RXCOUNT 0xffc03b50 /* Number of bytes received in endpoint5 FIFO */
567#define USB_EP_NI5_TXTYPE 0xffc03b54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
568#define USB_EP_NI5_TXINTERVAL 0xffc03b58 /* Sets the NAK response timeout on Endpoint5 */
569#define USB_EP_NI5_RXTYPE 0xffc03b5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
570#define USB_EP_NI5_RXINTERVAL 0xffc03b60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
571#define USB_EP_NI5_TXCOUNT 0xffc03b68 /* Number of bytes to be written to the endpoint5 Tx FIFO */
572
573/* USB Endpoint 6 Control Registers */
574
575#define USB_EP_NI6_TXMAXP 0xffc03b80 /* Maximum packet size for Host Tx endpoint6 */
576#define USB_EP_NI6_TXCSR 0xffc03b84 /* Control Status register for endpoint6 */
577#define USB_EP_NI6_RXMAXP 0xffc03b88 /* Maximum packet size for Host Rx endpoint6 */
578#define USB_EP_NI6_RXCSR 0xffc03b8c /* Control Status register for Host Rx endpoint6 */
579#define USB_EP_NI6_RXCOUNT 0xffc03b90 /* Number of bytes received in endpoint6 FIFO */
580#define USB_EP_NI6_TXTYPE 0xffc03b94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
581#define USB_EP_NI6_TXINTERVAL 0xffc03b98 /* Sets the NAK response timeout on Endpoint6 */
582#define USB_EP_NI6_RXTYPE 0xffc03b9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
583#define USB_EP_NI6_RXINTERVAL 0xffc03ba0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
584#define USB_EP_NI6_TXCOUNT 0xffc03ba8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
585
586/* USB Endpoint 7 Control Registers */
587
588#define USB_EP_NI7_TXMAXP 0xffc03bc0 /* Maximum packet size for Host Tx endpoint7 */
589#define USB_EP_NI7_TXCSR 0xffc03bc4 /* Control Status register for endpoint7 */
590#define USB_EP_NI7_RXMAXP 0xffc03bc8 /* Maximum packet size for Host Rx endpoint7 */
591#define USB_EP_NI7_RXCSR 0xffc03bcc /* Control Status register for Host Rx endpoint7 */
592#define USB_EP_NI7_RXCOUNT 0xffc03bd0 /* Number of bytes received in endpoint7 FIFO */
593#define USB_EP_NI7_TXTYPE 0xffc03bd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
594#define USB_EP_NI7_TXINTERVAL 0xffc03bd8 /* Sets the NAK response timeout on Endpoint7 */
595#define USB_EP_NI7_RXTYPE 0xffc03bdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
596#define USB_EP_NI7_RXINTERVAL 0xffc03bf0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
597#define USB_EP_NI7_TXCOUNT 0xffc03bf8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
598
599#define USB_DMA_INTERRUPT 0xffc03c00 /* Indicates pending interrupts for the DMA channels */
600
601/* USB Channel 0 Config Registers */
602
603#define USB_DMA0CONTROL 0xffc03c04 /* DMA master channel 0 configuration */
604#define USB_DMA0ADDRLOW 0xffc03c08 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
605#define USB_DMA0ADDRHIGH 0xffc03c0c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
606#define USB_DMA0COUNTLOW 0xffc03c10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
607#define USB_DMA0COUNTHIGH 0xffc03c14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
608
609/* USB Channel 1 Config Registers */
610
611#define USB_DMA1CONTROL 0xffc03c24 /* DMA master channel 1 configuration */
612#define USB_DMA1ADDRLOW 0xffc03c28 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
613#define USB_DMA1ADDRHIGH 0xffc03c2c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
614#define USB_DMA1COUNTLOW 0xffc03c30 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
615#define USB_DMA1COUNTHIGH 0xffc03c34 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
616
617/* USB Channel 2 Config Registers */
618
619#define USB_DMA2CONTROL 0xffc03c44 /* DMA master channel 2 configuration */
620#define USB_DMA2ADDRLOW 0xffc03c48 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
621#define USB_DMA2ADDRHIGH 0xffc03c4c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
622#define USB_DMA2COUNTLOW 0xffc03c50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
623#define USB_DMA2COUNTHIGH 0xffc03c54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
624
625/* USB Channel 3 Config Registers */
626
627#define USB_DMA3CONTROL 0xffc03c64 /* DMA master channel 3 configuration */
628#define USB_DMA3ADDRLOW 0xffc03c68 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
629#define USB_DMA3ADDRHIGH 0xffc03c6c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
630#define USB_DMA3COUNTLOW 0xffc03c70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
631#define USB_DMA3COUNTHIGH 0xffc03c74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
632
633/* USB Channel 4 Config Registers */
634
635#define USB_DMA4CONTROL 0xffc03c84 /* DMA master channel 4 configuration */
636#define USB_DMA4ADDRLOW 0xffc03c88 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
637#define USB_DMA4ADDRHIGH 0xffc03c8c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
638#define USB_DMA4COUNTLOW 0xffc03c90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
639#define USB_DMA4COUNTHIGH 0xffc03c94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
640
641/* USB Channel 5 Config Registers */
642
643#define USB_DMA5CONTROL 0xffc03ca4 /* DMA master channel 5 configuration */
644#define USB_DMA5ADDRLOW 0xffc03ca8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
645#define USB_DMA5ADDRHIGH 0xffc03cac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
646#define USB_DMA5COUNTLOW 0xffc03cb0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
647#define USB_DMA5COUNTHIGH 0xffc03cb4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
648
649/* USB Channel 6 Config Registers */
650
651#define USB_DMA6CONTROL 0xffc03cc4 /* DMA master channel 6 configuration */
652#define USB_DMA6ADDRLOW 0xffc03cc8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
653#define USB_DMA6ADDRHIGH 0xffc03ccc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
654#define USB_DMA6COUNTLOW 0xffc03cd0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
655#define USB_DMA6COUNTHIGH 0xffc03cd4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
656
657/* USB Channel 7 Config Registers */
658
659#define USB_DMA7CONTROL 0xffc03ce4 /* DMA master channel 7 configuration */
660#define USB_DMA7ADDRLOW 0xffc03ce8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
661#define USB_DMA7ADDRHIGH 0xffc03cec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
662#define USB_DMA7COUNTLOW 0xffc03cf0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
663#define USB_DMA7COUNTHIGH 0xffc03cf4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
664
665/* Bit masks for USB_FADDR */
666
667#define FUNCTION_ADDRESS 0x7f /* Function address */
668
669/* Bit masks for USB_POWER */
670
671#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
672#define nENABLE_SUSPENDM 0x0
673#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
674#define nSUSPEND_MODE 0x0
675#define RESUME_MODE 0x4 /* DMA Mode */
676#define nRESUME_MODE 0x0
677#define RESET 0x8 /* Reset indicator */
678#define nRESET 0x0
679#define HS_MODE 0x10 /* High Speed mode indicator */
680#define nHS_MODE 0x0
681#define HS_ENABLE 0x20 /* high Speed Enable */
682#define nHS_ENABLE 0x0
683#define SOFT_CONN 0x40 /* Soft connect */
684#define nSOFT_CONN 0x0
685#define ISO_UPDATE 0x80 /* Isochronous update */
686#define nISO_UPDATE 0x0
687
688/* Bit masks for USB_INTRTX */
689
690#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
691#define nEP0_TX 0x0
692#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
693#define nEP1_TX 0x0
694#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
695#define nEP2_TX 0x0
696#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
697#define nEP3_TX 0x0
698#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
699#define nEP4_TX 0x0
700#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
701#define nEP5_TX 0x0
702#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
703#define nEP6_TX 0x0
704#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
705#define nEP7_TX 0x0
706
707/* Bit masks for USB_INTRRX */
708
709#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
710#define nEP1_RX 0x0
711#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
712#define nEP2_RX 0x0
713#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
714#define nEP3_RX 0x0
715#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
716#define nEP4_RX 0x0
717#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
718#define nEP5_RX 0x0
719#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
720#define nEP6_RX 0x0
721#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
722#define nEP7_RX 0x0
723
724/* Bit masks for USB_INTRTXE */
725
726#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
727#define nEP0_TX_E 0x0
728#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
729#define nEP1_TX_E 0x0
730#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
731#define nEP2_TX_E 0x0
732#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
733#define nEP3_TX_E 0x0
734#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
735#define nEP4_TX_E 0x0
736#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
737#define nEP5_TX_E 0x0
738#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
739#define nEP6_TX_E 0x0
740#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
741#define nEP7_TX_E 0x0
742
743/* Bit masks for USB_INTRRXE */
744
745#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
746#define nEP1_RX_E 0x0
747#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
748#define nEP2_RX_E 0x0
749#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
750#define nEP3_RX_E 0x0
751#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
752#define nEP4_RX_E 0x0
753#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
754#define nEP5_RX_E 0x0
755#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
756#define nEP6_RX_E 0x0
757#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
758#define nEP7_RX_E 0x0
759
760/* Bit masks for USB_INTRUSB */
761
762#define SUSPEND_B 0x1 /* Suspend indicator */
763#define nSUSPEND_B 0x0
764#define RESUME_B 0x2 /* Resume indicator */
765#define nRESUME_B 0x0
766#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
767#define nRESET_OR_BABLE_B 0x0
768#define SOF_B 0x8 /* Start of frame */
769#define nSOF_B 0x0
770#define CONN_B 0x10 /* Connection indicator */
771#define nCONN_B 0x0
772#define DISCON_B 0x20 /* Disconnect indicator */
773#define nDISCON_B 0x0
774#define SESSION_REQ_B 0x40 /* Session Request */
775#define nSESSION_REQ_B 0x0
776#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
777#define nVBUS_ERROR_B 0x0
778
779/* Bit masks for USB_INTRUSBE */
780
781#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
782#define nSUSPEND_BE 0x0
783#define RESUME_BE 0x2 /* Resume indicator int enable */
784#define nRESUME_BE 0x0
785#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
786#define nRESET_OR_BABLE_BE 0x0
787#define SOF_BE 0x8 /* Start of frame int enable */
788#define nSOF_BE 0x0
789#define CONN_BE 0x10 /* Connection indicator int enable */
790#define nCONN_BE 0x0
791#define DISCON_BE 0x20 /* Disconnect indicator int enable */
792#define nDISCON_BE 0x0
793#define SESSION_REQ_BE 0x40 /* Session Request int enable */
794#define nSESSION_REQ_BE 0x0
795#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
796#define nVBUS_ERROR_BE 0x0
797
798/* Bit masks for USB_FRAME */
799
800#define FRAME_NUMBER 0x7ff /* Frame number */
801
802/* Bit masks for USB_INDEX */
803
804#define SELECTED_ENDPOINT 0xf /* selected endpoint */
805
806/* Bit masks for USB_GLOBAL_CTL */
807
808#define GLOBAL_ENA 0x1 /* enables USB module */
809#define nGLOBAL_ENA 0x0
810#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
811#define nEP1_TX_ENA 0x0
812#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
813#define nEP2_TX_ENA 0x0
814#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
815#define nEP3_TX_ENA 0x0
816#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
817#define nEP4_TX_ENA 0x0
818#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
819#define nEP5_TX_ENA 0x0
820#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
821#define nEP6_TX_ENA 0x0
822#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
823#define nEP7_TX_ENA 0x0
824#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
825#define nEP1_RX_ENA 0x0
826#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
827#define nEP2_RX_ENA 0x0
828#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
829#define nEP3_RX_ENA 0x0
830#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
831#define nEP4_RX_ENA 0x0
832#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
833#define nEP5_RX_ENA 0x0
834#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
835#define nEP6_RX_ENA 0x0
836#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
837#define nEP7_RX_ENA 0x0
838
839/* Bit masks for USB_OTG_DEV_CTL */
840
841#define SESSION 0x1 /* session indicator */
842#define nSESSION 0x0
843#define HOST_REQ 0x2 /* Host negotiation request */
844#define nHOST_REQ 0x0
845#define HOST_MODE 0x4 /* indicates USBDRC is a host */
846#define nHOST_MODE 0x0
847#define VBUS0 0x8 /* Vbus level indicator[0] */
848#define nVBUS0 0x0
849#define VBUS1 0x10 /* Vbus level indicator[1] */
850#define nVBUS1 0x0
851#define LSDEV 0x20 /* Low-speed indicator */
852#define nLSDEV 0x0
853#define FSDEV 0x40 /* Full or High-speed indicator */
854#define nFSDEV 0x0
855#define B_DEVICE 0x80 /* A' or 'B' device indicator */
856#define nB_DEVICE 0x0
857
858/* Bit masks for USB_OTG_VBUS_IRQ */
859
860#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
861#define nDRIVE_VBUS_ON 0x0
862#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
863#define nDRIVE_VBUS_OFF 0x0
864#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
865#define nCHRG_VBUS_START 0x0
866#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
867#define nCHRG_VBUS_END 0x0
868#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
869#define nDISCHRG_VBUS_START 0x0
870#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
871#define nDISCHRG_VBUS_END 0x0
872
873/* Bit masks for USB_OTG_VBUS_MASK */
874
875#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
876#define nDRIVE_VBUS_ON_ENA 0x0
877#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
878#define nDRIVE_VBUS_OFF_ENA 0x0
879#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
880#define nCHRG_VBUS_START_ENA 0x0
881#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
882#define nCHRG_VBUS_END_ENA 0x0
883#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
884#define nDISCHRG_VBUS_START_ENA 0x0
885#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
886#define nDISCHRG_VBUS_END_ENA 0x0
887
888/* Bit masks for USB_CSR0 */
889
890#define RXPKTRDY 0x1 /* data packet receive indicator */
891#define nRXPKTRDY 0x0
892#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
893#define nTXPKTRDY 0x0
894#define STALL_SENT 0x4 /* STALL handshake sent */
895#define nSTALL_SENT 0x0
896#define DATAEND 0x8 /* Data end indicator */
897#define nDATAEND 0x0
898#define SETUPEND 0x10 /* Setup end */
899#define nSETUPEND 0x0
900#define SENDSTALL 0x20 /* Send STALL handshake */
901#define nSENDSTALL 0x0
902#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
903#define nSERVICED_RXPKTRDY 0x0
904#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
905#define nSERVICED_SETUPEND 0x0
906#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
907#define nFLUSHFIFO 0x0
908#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
909#define nSTALL_RECEIVED_H 0x0
910#define SETUPPKT_H 0x8 /* send Setup token host mode */
911#define nSETUPPKT_H 0x0
912#define ERROR_H 0x10 /* timeout error indicator host mode */
913#define nERROR_H 0x0
914#define REQPKT_H 0x20 /* Request an IN transaction host mode */
915#define nREQPKT_H 0x0
916#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
917#define nSTATUSPKT_H 0x0
918#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
919#define nNAK_TIMEOUT_H 0x0
920
921/* Bit masks for USB_COUNT0 */
922
923#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
924
925/* Bit masks for USB_NAKLIMIT0 */
926
927#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
928
929/* Bit masks for USB_TX_MAX_PACKET */
930
931#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
932
933/* Bit masks for USB_RX_MAX_PACKET */
934
935#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
936
937/* Bit masks for USB_TXCSR */
938
939#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
940#define nTXPKTRDY_T 0x0
941#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
942#define nFIFO_NOT_EMPTY_T 0x0
943#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
944#define nUNDERRUN_T 0x0
945#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
946#define nFLUSHFIFO_T 0x0
947#define STALL_SEND_T 0x10 /* issue a Stall handshake */
948#define nSTALL_SEND_T 0x0
949#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
950#define nSTALL_SENT_T 0x0
951#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
952#define nCLEAR_DATATOGGLE_T 0x0
953#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
954#define nINCOMPTX_T 0x0
955#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
956#define nDMAREQMODE_T 0x0
957#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
958#define nFORCE_DATATOGGLE_T 0x0
959#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
960#define nDMAREQ_ENA_T 0x0
961#define ISO_T 0x4000 /* enable Isochronous transfers */
962#define nISO_T 0x0
963#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
964#define nAUTOSET_T 0x0
965#define ERROR_TH 0x4 /* error condition host mode */
966#define nERROR_TH 0x0
967#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
968#define nSTALL_RECEIVED_TH 0x0
969#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
970#define nNAK_TIMEOUT_TH 0x0
971
972/* Bit masks for USB_TXCOUNT */
973
974#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
975
976/* Bit masks for USB_RXCSR */
977
978#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
979#define nRXPKTRDY_R 0x0
980#define FIFO_FULL_R 0x2 /* FIFO not empty */
981#define nFIFO_FULL_R 0x0
982#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
983#define nOVERRUN_R 0x0
984#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
985#define nDATAERROR_R 0x0
986#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
987#define nFLUSHFIFO_R 0x0
988#define STALL_SEND_R 0x20 /* issue a Stall handshake */
989#define nSTALL_SEND_R 0x0
990#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
991#define nSTALL_SENT_R 0x0
992#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
993#define nCLEAR_DATATOGGLE_R 0x0
994#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
995#define nINCOMPRX_R 0x0
996#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
997#define nDMAREQMODE_R 0x0
998#define DISNYET_R 0x1000 /* disable Nyet handshakes */
999#define nDISNYET_R 0x0
1000#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
1001#define nDMAREQ_ENA_R 0x0
1002#define ISO_R 0x4000 /* enable Isochronous transfers */
1003#define nISO_R 0x0
1004#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
1005#define nAUTOCLEAR_R 0x0
1006#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
1007#define nERROR_RH 0x0
1008#define REQPKT_RH 0x20 /* request an IN transaction host mode */
1009#define nREQPKT_RH 0x0
1010#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
1011#define nSTALL_RECEIVED_RH 0x0
1012#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
1013#define nINCOMPRX_RH 0x0
1014#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
1015#define nDMAREQMODE_RH 0x0
1016#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
1017#define nAUTOREQ_RH 0x0
1018
1019/* Bit masks for USB_RXCOUNT */
1020
1021#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
1022
1023/* Bit masks for USB_TXTYPE */
1024
1025#define TARGET_EP_NO_T 0xf /* EP number */
1026#define PROTOCOL_T 0xc /* transfer type */
1027
1028/* Bit masks for USB_TXINTERVAL */
1029
1030#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
1031
1032/* Bit masks for USB_RXTYPE */
1033
1034#define TARGET_EP_NO_R 0xf /* EP number */
1035#define PROTOCOL_R 0xc /* transfer type */
1036
1037/* Bit masks for USB_RXINTERVAL */
1038
1039#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
1040
1041/* Bit masks for USB_DMA_INTERRUPT */
1042
1043#define DMA0_INT 0x1 /* DMA0 pending interrupt */
1044#define nDMA0_INT 0x0
1045#define DMA1_INT 0x2 /* DMA1 pending interrupt */
1046#define nDMA1_INT 0x0
1047#define DMA2_INT 0x4 /* DMA2 pending interrupt */
1048#define nDMA2_INT 0x0
1049#define DMA3_INT 0x8 /* DMA3 pending interrupt */
1050#define nDMA3_INT 0x0
1051#define DMA4_INT 0x10 /* DMA4 pending interrupt */
1052#define nDMA4_INT 0x0
1053#define DMA5_INT 0x20 /* DMA5 pending interrupt */
1054#define nDMA5_INT 0x0
1055#define DMA6_INT 0x40 /* DMA6 pending interrupt */
1056#define nDMA6_INT 0x0
1057#define DMA7_INT 0x80 /* DMA7 pending interrupt */
1058#define nDMA7_INT 0x0
1059
1060/* Bit masks for USB_DMAxCONTROL */
1061
1062#define DMA_ENA 0x1 /* DMA enable */
1063#define nDMA_ENA 0x0
1064#define DIRECTION 0x2 /* direction of DMA transfer */
1065#define nDIRECTION 0x0
1066#define MODE 0x4 /* DMA Bus error */
1067#define nMODE 0x0
1068#define INT_ENA 0x8 /* Interrupt enable */
1069#define nINT_ENA 0x0
1070#define EPNUM 0xf0 /* EP number */
1071#define BUSERROR 0x100 /* DMA Bus error */
1072#define nBUSERROR 0x0
1073
1074/* Bit masks for USB_DMAxADDRHIGH */
1075
1076#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
1077
1078/* Bit masks for USB_DMAxADDRLOW */
1079
1080#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
1081
1082/* Bit masks for USB_DMAxCOUNTHIGH */
1083
1084#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
1085
1086/* Bit masks for USB_DMAxCOUNTLOW */
1087
1088#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
1089
1090#endif /* _DEF_BF527_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
new file mode 100644
index 000000000000..6ac2ed7026eb
--- /dev/null
+++ b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
@@ -0,0 +1,2005 @@
1/*
2 * File: include/asm-blackfin/mach-bf527/defBF52x_base.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _DEF_BF52X_H
32#define _DEF_BF52X_H
33
34
35/* ************************************************************** */
36/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF52x */
37/* ************************************************************** */
38
39/* ==== begin from defBF534.h ==== */
40
41/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
42#define PLL_CTL 0xFFC00000 /* PLL Control Register */
43#define PLL_DIV 0xFFC00004 /* PLL Divide Register */
44#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */
45#define PLL_STAT 0xFFC0000C /* PLL Status Register */
46#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */
47#define CHIPID 0xFFC00014 /* Device ID Register */
48
49
50/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
51#define SWRST 0xFFC00100 /* Software Reset Register */
52#define SYSCR 0xFFC00104 /* System Configuration Register */
53#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
54
55#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */
56#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
57#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
58#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
59#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
60#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */
61#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */
62
63/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
64#define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */
65#define SIC_IAR4 0xFFC00150 /* Interrupt Assignment register4 */
66#define SIC_IAR5 0xFFC00154 /* Interrupt Assignment register5 */
67#define SIC_IAR6 0xFFC00158 /* Interrupt Assignment register6 */
68#define SIC_IAR7 0xFFC0015C /* Interrupt Assignment register7 */
69#define SIC_ISR1 0xFFC00160 /* Interrupt Statur register */
70#define SIC_IWR1 0xFFC00164 /* Interrupt Wakeup register */
71
72
73/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
74#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
75#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
76#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
77
78
79/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
80#define RTC_STAT 0xFFC00300 /* RTC Status Register */
81#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
82#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
83#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
84#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
85#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
86#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Alternate Macro */
87
88
89/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
90#define UART0_THR 0xFFC00400 /* Transmit Holding register */
91#define UART0_RBR 0xFFC00400 /* Receive Buffer register */
92#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
93#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */
94#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
95#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */
96#define UART0_LCR 0xFFC0040C /* Line Control Register */
97#define UART0_MCR 0xFFC00410 /* Modem Control Register */
98#define UART0_LSR 0xFFC00414 /* Line Status Register */
99#define UART0_MSR 0xFFC00418 /* Modem Status Register */
100#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */
101#define UART0_GCTL 0xFFC00424 /* Global Control Register */
102
103
104/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
105#define SPI0_REGBASE 0xFFC00500
106#define SPI_CTL 0xFFC00500 /* SPI Control Register */
107#define SPI_FLG 0xFFC00504 /* SPI Flag register */
108#define SPI_STAT 0xFFC00508 /* SPI Status register */
109#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
110#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
111#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
112#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
113
114
115/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
116#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
117#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
118#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
119#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
120
121#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
122#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
123#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
124#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
125
126#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
127#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
128#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
129#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
130
131#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */
132#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */
133#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */
134#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */
135
136#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */
137#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */
138#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */
139#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */
140
141#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */
142#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */
143#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */
144#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */
145
146#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */
147#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */
148#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */
149#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */
150
151#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */
152#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */
153#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */
154#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */
155
156#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */
157#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */
158#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */
159
160
161/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
162#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */
163#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */
164#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */
165#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */
166#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */
167#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */
168#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */
169#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */
170#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */
171#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */
172#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */
173#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */
174#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */
175#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */
176#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */
177#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */
178#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */
179
180
181/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
182#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
183#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
184#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
185#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
186#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
187#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
188#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
189#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
190#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
191#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
192#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
193#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
194#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
195#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
196#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
197#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
198#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
199#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
200#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
201#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
202#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
203#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
204
205
206/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
207#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
208#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
209#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
210#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
211#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
212#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
213#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
214#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
215#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
216#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
217#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
218#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
219#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
220#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
221#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
222#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
223#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
224#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
225#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
226#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
227#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
228#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
229
230
231/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
232#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
233#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
234#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
235#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
236#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
237#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
238#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
239
240
241/* DMA Traffic Control Registers */
242#define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
243#define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
244
245/* Alternate deprecated register names (below) provided for backwards code compatibility */
246#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
247#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
248
249/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
250#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
251#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
252#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
253#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
254#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
255#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
256#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
257#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
258#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
259#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
260#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
261#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
262#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
263
264#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
265#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
266#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
267#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
268#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
269#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
270#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
271#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
272#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
273#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
274#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
275#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
276#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
277
278#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
279#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
280#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
281#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
282#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
283#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
284#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
285#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
286#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
287#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
288#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
289#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
290#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
291
292#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
293#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
294#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
295#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
296#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
297#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
298#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
299#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
300#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
301#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
302#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
303#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
304#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
305
306#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
307#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
308#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
309#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
310#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
311#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
312#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
313#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
314#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
315#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
316#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
317#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
318#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
319
320#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
321#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
322#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
323#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
324#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
325#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
326#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
327#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
328#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
329#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
330#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
331#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
332#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
333
334#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
335#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
336#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
337#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
338#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
339#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
340#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
341#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
342#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
343#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
344#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
345#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
346#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
347
348#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
349#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
350#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
351#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
352#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
353#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
354#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
355#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
356#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
357#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
358#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
359#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
360#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
361
362#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
363#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */
364#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */
365#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */
366#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */
367#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */
368#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */
369#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
370#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */
371#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
372#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
373#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */
374#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
375
376#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
377#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */
378#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */
379#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */
380#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */
381#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */
382#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */
383#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
384#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */
385#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
386#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
387#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */
388#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
389
390#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
391#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */
392#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */
393#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */
394#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */
395#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */
396#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
397#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
398#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */
399#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
400#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
401#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
402#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
403
404#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
405#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */
406#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */
407#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */
408#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
409#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */
410#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
411#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
412#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */
413#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
414#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
415#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
416#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
417
418#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
419#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */
420#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */
421#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */
422#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */
423#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */
424#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */
425#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
426#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */
427#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
428#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */
429#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */
430#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */
431
432#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
433#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */
434#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */
435#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */
436#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */
437#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */
438#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */
439#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
440#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */
441#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */
442#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */
443#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */
444#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */
445
446#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
447#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */
448#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */
449#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */
450#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */
451#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */
452#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */
453#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
454#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */
455#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
456#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */
457#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */
458#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */
459
460#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
461#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */
462#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */
463#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */
464#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */
465#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */
466#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */
467#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
468#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */
469#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
470#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */
471#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */
472#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */
473
474
475/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
476#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
477#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
478#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
479#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
480#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
481
482
483/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
484#define TWI0_REGBASE 0xFFC01400
485#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
486#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */
487#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
488#define TWI_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
489#define TWI_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
490#define TWI_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
491#define TWI_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
492#define TWI_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
493#define TWI_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
494#define TWI_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
495#define TWI_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
496#define TWI_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
497#define TWI_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
498#define TWI_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
499#define TWI_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
500#define TWI_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
501
502
503/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
504#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */
505#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */
506#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */
507#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */
508#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */
509#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */
510#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */
511#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */
512#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */
513#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */
514#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */
515#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */
516#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */
517#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */
518#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */
519#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */
520#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */
521
522
523/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
524#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */
525#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */
526#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */
527#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */
528#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */
529#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */
530#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */
531#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */
532#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */
533#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */
534#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */
535#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */
536#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */
537#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */
538#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */
539#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */
540#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */
541
542
543/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
544#define UART1_THR 0xFFC02000 /* Transmit Holding register */
545#define UART1_RBR 0xFFC02000 /* Receive Buffer register */
546#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */
547#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */
548#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */
549#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */
550#define UART1_LCR 0xFFC0200C /* Line Control Register */
551#define UART1_MCR 0xFFC02010 /* Modem Control Register */
552#define UART1_LSR 0xFFC02014 /* Line Status Register */
553#define UART1_MSR 0xFFC02018 /* Modem Status Register */
554#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */
555#define UART1_GCTL 0xFFC02024 /* Global Control Register */
556
557
558/* Omit CAN register sets from the defBF534.h (CAN is not in the ADSP-BF52x processor) */
559
560/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
561#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */
562#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */
563#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */
564#define BFIN_PORT_MUX 0xFFC0320C /* Port Multiplexer Control Register */
565
566
567/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
568#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */
569#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */
570#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */
571#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshhold Register */
572#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
573#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */
574#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */
575
576#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */
577#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */
578#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */
579#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshhold Register */
580#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
581#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */
582#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */
583
584/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
585#define PORTF_MUX 0xFFC03210 /* Port F mux control */
586#define PORTG_MUX 0xFFC03214 /* Port G mux control */
587#define PORTH_MUX 0xFFC03218 /* Port H mux control */
588#define PORTF_DRIVE 0xFFC03220 /* Port F drive strength control */
589#define PORTG_DRIVE 0xFFC03224 /* Port G drive strength control */
590#define PORTH_DRIVE 0xFFC03228 /* Port H drive strength control */
591#define PORTF_SLEW 0xFFC03230 /* Port F slew control */
592#define PORTG_SLEW 0xFFC03234 /* Port G slew control */
593#define PORTH_SLEW 0xFFC03238 /* Port H slew control */
594#define PORTF_HYSTERISIS 0xFFC03240 /* Port F Schmitt trigger control */
595#define PORTG_HYSTERISIS 0xFFC03244 /* Port G Schmitt trigger control */
596#define PORTH_HYSTERISIS 0xFFC03248 /* Port H Schmitt trigger control */
597#define MISCPORT_DRIVE 0xFFC03280 /* Misc Port drive strength control */
598#define MISCPORT_SLEW 0xFFC03284 /* Misc Port slew control */
599#define MISCPORT_HYSTERISIS 0xFFC03288 /* Misc Port Schmitt trigger control */
600
601
602/***********************************************************************************
603** System MMR Register Bits And Macros
604**
605** Disclaimer: All macros are intended to make C and Assembly code more readable.
606** Use these macros carefully, as any that do left shifts for field
607** depositing will result in the lower order bits being destroyed. Any
608** macro that shifts left to properly position the bit-field should be
609** used as part of an OR to initialize a register and NOT as a dynamic
610** modifier UNLESS the lower order bits are saved and ORed back in when
611** the macro is used.
612*************************************************************************************/
613/*
614** ********************* PLL AND RESET MASKS ****************************************/
615/* PLL_CTL Masks */
616#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
617#define PLL_OFF 0x0002 /* PLL Not Powered */
618#define STOPCK 0x0008 /* Core Clock Off */
619#define PDWN 0x0020 /* Enter Deep Sleep Mode */
620#define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */
621#define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */
622#define BYPASS 0x0100 /* Bypass the PLL */
623#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */
624/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */
625#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
626
627/* PLL_DIV Masks */
628#define SSEL 0x000F /* System Select */
629#define CSEL 0x0030 /* Core Select */
630#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
631#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
632#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
633#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
634/* PLL_DIV Macros */
635#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
636
637/* VR_CTL Masks */
638#define FREQ 0x3000 /* Switching Oscillator Frequency For Regulator */
639#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
640
641#define VLEV 0x00F0 /* Internal Voltage Level */
642#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
643#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
644#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
645#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
646#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
647#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
648#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
649#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
650#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */
651#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
652
653#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
654#define USBWE 0x0200 /* Enable USB Wakeup From Hibernate */
655#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */
656#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */
657#define PHYCLKOE CLKBUFOE /* Alternative legacy name for the above */
658#define SCKELOW 0x8000 /* Enable Drive CKE Low During Reset */
659
660/* PLL_STAT Masks */
661#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
662#define FULL_ON 0x0002 /* Processor In Full On Mode */
663#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
664#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
665
666/* CHIPID Masks */
667#define CHIPID_VERSION 0xF0000000
668#define CHIPID_FAMILY 0x0FFFF000
669#define CHIPID_MANUFACTURE 0x00000FFE
670
671/* SWRST Masks */
672#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
673#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
674#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
675#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
676#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
677
678/* SYSCR Masks */
679#define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */
680#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
681
682
683/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
684/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */
685
686#if 0
687#define IRQ_PLL_WAKEUP 0x00000001 /* PLL Wakeup Interrupt */
688
689#define IRQ_ERROR1 0x00000002 /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */
690#define IRQ_ERROR2 0x00000004 /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */
691#define IRQ_RTC 0x00000008 /* Real Time Clock Interrupt */
692#define IRQ_DMA0 0x00000010 /* DMA Channel 0 (PPI) Interrupt */
693#define IRQ_DMA3 0x00000020 /* DMA Channel 3 (SPORT0 RX) Interrupt */
694#define IRQ_DMA4 0x00000040 /* DMA Channel 4 (SPORT0 TX) Interrupt */
695#define IRQ_DMA5 0x00000080 /* DMA Channel 5 (SPORT1 RX) Interrupt */
696
697#define IRQ_DMA6 0x00000100 /* DMA Channel 6 (SPORT1 TX) Interrupt */
698#define IRQ_TWI 0x00000200 /* TWI Interrupt */
699#define IRQ_DMA7 0x00000400 /* DMA Channel 7 (SPI) Interrupt */
700#define IRQ_DMA8 0x00000800 /* DMA Channel 8 (UART0 RX) Interrupt */
701#define IRQ_DMA9 0x00001000 /* DMA Channel 9 (UART0 TX) Interrupt */
702#define IRQ_DMA10 0x00002000 /* DMA Channel 10 (UART1 RX) Interrupt */
703#define IRQ_DMA11 0x00004000 /* DMA Channel 11 (UART1 TX) Interrupt */
704#define IRQ_CAN_RX 0x00008000 /* CAN Receive Interrupt */
705
706#define IRQ_CAN_TX 0x00010000 /* CAN Transmit Interrupt */
707#define IRQ_DMA1 0x00020000 /* DMA Channel 1 (Ethernet RX) Interrupt */
708#define IRQ_PFA_PORTH 0x00020000 /* PF Port H (PF47:32) Interrupt A */
709#define IRQ_DMA2 0x00040000 /* DMA Channel 2 (Ethernet TX) Interrupt */
710#define IRQ_PFB_PORTH 0x00040000 /* PF Port H (PF47:32) Interrupt B */
711#define IRQ_TIMER0 0x00080000 /* Timer 0 Interrupt */
712#define IRQ_TIMER1 0x00100000 /* Timer 1 Interrupt */
713#define IRQ_TIMER2 0x00200000 /* Timer 2 Interrupt */
714#define IRQ_TIMER3 0x00400000 /* Timer 3 Interrupt */
715#define IRQ_TIMER4 0x00800000 /* Timer 4 Interrupt */
716
717#define IRQ_TIMER5 0x01000000 /* Timer 5 Interrupt */
718#define IRQ_TIMER6 0x02000000 /* Timer 6 Interrupt */
719#define IRQ_TIMER7 0x04000000 /* Timer 7 Interrupt */
720#define IRQ_PFA_PORTFG 0x08000000 /* PF Ports F&G (PF31:0) Interrupt A */
721#define IRQ_PFB_PORTF 0x80000000 /* PF Port F (PF15:0) Interrupt B */
722#define IRQ_DMA12 0x20000000 /* DMA Channels 12 (MDMA1 Source) RX Interrupt */
723#define IRQ_DMA13 0x20000000 /* DMA Channels 13 (MDMA1 Destination) TX Interrupt */
724#define IRQ_DMA14 0x40000000 /* DMA Channels 14 (MDMA0 Source) RX Interrupt */
725#define IRQ_DMA15 0x40000000 /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */
726#define IRQ_WDOG 0x80000000 /* Software Watchdog Timer Interrupt */
727#define IRQ_PFB_PORTG 0x10000000 /* PF Port G (PF31:16) Interrupt B */
728#endif
729
730/* SIC_IAR0 Macros */
731#define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */
732#define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
733#define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
734#define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */
735#define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
736#define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
737#define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
738#define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
739
740/* SIC_IAR1 Macros */
741#define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */
742#define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
743#define P10_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #10 assigned IVG #x */
744#define P11_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #11 assigned IVG #x */
745#define P12_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #12 assigned IVG #x */
746#define P13_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #13 assigned IVG #x */
747#define P14_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #14 assigned IVG #x */
748#define P15_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
749
750/* SIC_IAR2 Macros */
751#define P16_IVG(x) (((x)&0xF)-7) /* Peripheral #16 assigned IVG #x */
752#define P17_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #17 assigned IVG #x */
753#define P18_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #18 assigned IVG #x */
754#define P19_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #19 assigned IVG #x */
755#define P20_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #20 assigned IVG #x */
756#define P21_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #21 assigned IVG #x */
757#define P22_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #22 assigned IVG #x */
758#define P23_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #23 assigned IVG #x */
759
760/* SIC_IAR3 Macros */
761#define P24_IVG(x) (((x)&0xF)-7) /* Peripheral #24 assigned IVG #x */
762#define P25_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #25 assigned IVG #x */
763#define P26_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #26 assigned IVG #x */
764#define P27_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #27 assigned IVG #x */
765#define P28_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #28 assigned IVG #x */
766#define P29_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #29 assigned IVG #x */
767#define P30_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #30 assigned IVG #x */
768#define P31_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #31 assigned IVG #x */
769
770
771/* SIC_IMASK Masks */
772#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
773#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
774#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
775#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
776
777/* SIC_IWR Masks */
778#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
779#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
780#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
781#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
782
783
784/* ********* WATCHDOG TIMER MASKS ******************** */
785
786/* Watchdog Timer WDOG_CTL Register Masks */
787
788#define WDEV(x) (((x)<<1) & 0x0006) /* event generated on roll over */
789#define WDEV_RESET 0x0000 /* generate reset event on roll over */
790#define WDEV_NMI 0x0002 /* generate NMI event on roll over */
791#define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */
792#define WDEV_NONE 0x0006 /* no event on roll over */
793#define WDEN 0x0FF0 /* enable watchdog */
794#define WDDIS 0x0AD0 /* disable watchdog */
795#define WDRO 0x8000 /* watchdog rolled over latch */
796
797/* depreciated WDOG_CTL Register Masks for legacy code */
798
799
800#define ICTL WDEV
801#define ENABLE_RESET WDEV_RESET
802#define WDOG_RESET WDEV_RESET
803#define ENABLE_NMI WDEV_NMI
804#define WDOG_NMI WDEV_NMI
805#define ENABLE_GPI WDEV_GPI
806#define WDOG_GPI WDEV_GPI
807#define DISABLE_EVT WDEV_NONE
808#define WDOG_NONE WDEV_NONE
809
810#define TMR_EN WDEN
811#define TMR_DIS WDDIS
812#define TRO WDRO
813#define ICTL_P0 0x01
814 #define ICTL_P1 0x02
815#define TRO_P 0x0F
816
817
818
819/* *************** REAL TIME CLOCK MASKS **************************/
820/* RTC_STAT and RTC_ALARM Masks */
821#define RTC_SEC 0x0000003F /* Real-Time Clock Seconds */
822#define RTC_MIN 0x00000FC0 /* Real-Time Clock Minutes */
823#define RTC_HR 0x0001F000 /* Real-Time Clock Hours */
824#define RTC_DAY 0xFFFE0000 /* Real-Time Clock Days */
825
826/* RTC_ALARM Macro z=day y=hr x=min w=sec */
827#define SET_ALARM(z,y,x,w) ((((z)&0x7FFF)<<0x11)|(((y)&0x1F)<<0xC)|(((x)&0x3F)<<0x6)|((w)&0x3F))
828
829/* RTC_ICTL and RTC_ISTAT Masks */
830#define STOPWATCH 0x0001 /* Stopwatch Interrupt Enable */
831#define ALARM 0x0002 /* Alarm Interrupt Enable */
832#define SECOND 0x0004 /* Seconds (1 Hz) Interrupt Enable */
833#define MINUTE 0x0008 /* Minutes Interrupt Enable */
834#define HOUR 0x0010 /* Hours Interrupt Enable */
835#define DAY 0x0020 /* 24 Hours (Days) Interrupt Enable */
836#define DAY_ALARM 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */
837#define WRITE_PENDING 0x4000 /* Write Pending Status */
838#define WRITE_COMPLETE 0x8000 /* Write Complete Interrupt Enable */
839
840/* RTC_FAST / RTC_PREN Mask */
841#define PREN 0x0001 /* Enable Prescaler, RTC Runs @1 Hz */
842
843
844/* ************** UART CONTROLLER MASKS *************************/
845/* UARTx_LCR Masks */
846#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
847#define STB 0x04 /* Stop Bits */
848#define PEN 0x08 /* Parity Enable */
849#define EPS 0x10 /* Even Parity Select */
850#define STP 0x20 /* Stick Parity */
851#define SB 0x40 /* Set Break */
852#define DLAB 0x80 /* Divisor Latch Access */
853
854/* UARTx_MCR Mask */
855#define LOOP_ENA 0x10 /* Loopback Mode Enable */
856#define LOOP_ENA_P 0x04
857
858/* UARTx_LSR Masks */
859#define DR 0x01 /* Data Ready */
860#define OE 0x02 /* Overrun Error */
861#define PE 0x04 /* Parity Error */
862#define FE 0x08 /* Framing Error */
863#define BI 0x10 /* Break Interrupt */
864#define THRE 0x20 /* THR Empty */
865#define TEMT 0x40 /* TSR and UART_THR Empty */
866
867/* UARTx_IER Masks */
868#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
869#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
870#define ELSI 0x04 /* Enable RX Status Interrupt */
871
872/* UARTx_IIR Masks */
873#define NINT 0x01 /* Pending Interrupt */
874#define IIR_TX_READY 0x02 /* UART_THR empty */
875#define IIR_RX_READY 0x04 /* Receive data ready */
876#define IIR_LINE_CHANGE 0x06 /* Receive line status */
877#define IIR_STATUS 0x06 /* Highest Priority Pending Interrupt */
878
879/* UARTx_GCTL Masks */
880#define UCEN 0x01 /* Enable UARTx Clocks */
881#define IREN 0x02 /* Enable IrDA Mode */
882#define TPOLC 0x04 /* IrDA TX Polarity Change */
883#define RPOLC 0x08 /* IrDA RX Polarity Change */
884#define FPE 0x10 /* Force Parity Error On Transmit */
885#define FFE 0x20 /* Force Framing Error On Transmit */
886
887
888/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS ****************************/
889/* SPI_CTL Masks */
890#define TIMOD 0x0003 /* Transfer Initiate Mode */
891#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */
892#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */
893#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */
894#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */
895#define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last*) */
896#define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */
897#define PSSE 0x0010 /* Slave-Select Input Enable */
898#define EMISO 0x0020 /* Enable MISO As Output */
899#define SIZE 0x0100 /* Size of Words (16/8* Bits) */
900#define LSBF 0x0200 /* LSB First */
901#define CPHA 0x0400 /* Clock Phase */
902#define CPOL 0x0800 /* Clock Polarity */
903#define MSTR 0x1000 /* Master/Slave* */
904#define WOM 0x2000 /* Write Open Drain Master */
905#define SPE 0x4000 /* SPI Enable */
906
907/* SPI_FLG Masks */
908#define FLS1 0x0002 /* Enables SPI_FLOUT1 as SPI Slave-Select Output */
909#define FLS2 0x0004 /* Enables SPI_FLOUT2 as SPI Slave-Select Output */
910#define FLS3 0x0008 /* Enables SPI_FLOUT3 as SPI Slave-Select Output */
911#define FLS4 0x0010 /* Enables SPI_FLOUT4 as SPI Slave-Select Output */
912#define FLS5 0x0020 /* Enables SPI_FLOUT5 as SPI Slave-Select Output */
913#define FLS6 0x0040 /* Enables SPI_FLOUT6 as SPI Slave-Select Output */
914#define FLS7 0x0080 /* Enables SPI_FLOUT7 as SPI Slave-Select Output */
915#define FLG1 0xFDFF /* Activates SPI_FLOUT1 */
916#define FLG2 0xFBFF /* Activates SPI_FLOUT2 */
917#define FLG3 0xF7FF /* Activates SPI_FLOUT3 */
918#define FLG4 0xEFFF /* Activates SPI_FLOUT4 */
919#define FLG5 0xDFFF /* Activates SPI_FLOUT5 */
920#define FLG6 0xBFFF /* Activates SPI_FLOUT6 */
921#define FLG7 0x7FFF /* Activates SPI_FLOUT7 */
922
923/* SPI_STAT Masks */
924#define SPIF 0x0001 /* SPI Finished (Single-Word Transfer Complete) */
925#define MODF 0x0002 /* Mode Fault Error (Another Device Tried To Become Master) */
926#define TXE 0x0004 /* Transmission Error (Data Sent With No New Data In TDBR) */
927#define TXS 0x0008 /* SPI_TDBR Data Buffer Status (Full/Empty*) */
928#define RBSY 0x0010 /* Receive Error (Data Received With RDBR Full) */
929#define RXS 0x0020 /* SPI_RDBR Data Buffer Status (Full/Empty*) */
930#define TXCOL 0x0040 /* Transmit Collision Error (Corrupt Data May Have Been Sent) */
931
932
933/* **************** GENERAL PURPOSE TIMER MASKS **********************/
934/* TIMER_ENABLE Masks */
935#define TIMEN0 0x0001 /* Enable Timer 0 */
936#define TIMEN1 0x0002 /* Enable Timer 1 */
937#define TIMEN2 0x0004 /* Enable Timer 2 */
938#define TIMEN3 0x0008 /* Enable Timer 3 */
939#define TIMEN4 0x0010 /* Enable Timer 4 */
940#define TIMEN5 0x0020 /* Enable Timer 5 */
941#define TIMEN6 0x0040 /* Enable Timer 6 */
942#define TIMEN7 0x0080 /* Enable Timer 7 */
943
944/* TIMER_DISABLE Masks */
945#define TIMDIS0 TIMEN0 /* Disable Timer 0 */
946#define TIMDIS1 TIMEN1 /* Disable Timer 1 */
947#define TIMDIS2 TIMEN2 /* Disable Timer 2 */
948#define TIMDIS3 TIMEN3 /* Disable Timer 3 */
949#define TIMDIS4 TIMEN4 /* Disable Timer 4 */
950#define TIMDIS5 TIMEN5 /* Disable Timer 5 */
951#define TIMDIS6 TIMEN6 /* Disable Timer 6 */
952#define TIMDIS7 TIMEN7 /* Disable Timer 7 */
953
954/* TIMER_STATUS Masks */
955#define TIMIL0 0x00000001 /* Timer 0 Interrupt */
956#define TIMIL1 0x00000002 /* Timer 1 Interrupt */
957#define TIMIL2 0x00000004 /* Timer 2 Interrupt */
958#define TIMIL3 0x00000008 /* Timer 3 Interrupt */
959#define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */
960#define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */
961#define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */
962#define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */
963#define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */
964#define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */
965#define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */
966#define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */
967#define TIMIL4 0x00010000 /* Timer 4 Interrupt */
968#define TIMIL5 0x00020000 /* Timer 5 Interrupt */
969#define TIMIL6 0x00040000 /* Timer 6 Interrupt */
970#define TIMIL7 0x00080000 /* Timer 7 Interrupt */
971#define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */
972#define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */
973#define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */
974#define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */
975#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */
976#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */
977#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
978#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
979
980/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
981#define TOVL_ERR0 TOVF_ERR0
982#define TOVL_ERR1 TOVF_ERR1
983#define TOVL_ERR2 TOVF_ERR2
984#define TOVL_ERR3 TOVF_ERR3
985#define TOVL_ERR4 TOVF_ERR4
986#define TOVL_ERR5 TOVF_ERR5
987#define TOVL_ERR6 TOVF_ERR6
988#define TOVL_ERR7 TOVF_ERR7
989
990/* TIMERx_CONFIG Masks */
991#define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */
992#define WDTH_CAP 0x0002 /* Width Capture Input Mode */
993#define EXT_CLK 0x0003 /* External Clock Mode */
994#define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */
995#define PERIOD_CNT 0x0008 /* Period Count */
996#define IRQ_ENA 0x0010 /* Interrupt Request Enable */
997#define TIN_SEL 0x0020 /* Timer Input Select */
998#define OUT_DIS 0x0040 /* Output Pad Disable */
999#define CLK_SEL 0x0080 /* Timer Clock Select */
1000#define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */
1001#define EMU_RUN 0x0200 /* Emulation Behavior Select */
1002#define ERR_TYP 0xC000 /* Error Type */
1003
1004
1005/* ****************** GPIO PORTS F, G, H MASKS ***********************/
1006/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */
1007/* Port F Masks */
1008#define PF0 0x0001
1009#define PF1 0x0002
1010#define PF2 0x0004
1011#define PF3 0x0008
1012#define PF4 0x0010
1013#define PF5 0x0020
1014#define PF6 0x0040
1015#define PF7 0x0080
1016#define PF8 0x0100
1017#define PF9 0x0200
1018#define PF10 0x0400
1019#define PF11 0x0800
1020#define PF12 0x1000
1021#define PF13 0x2000
1022#define PF14 0x4000
1023#define PF15 0x8000
1024
1025/* Port G Masks */
1026#define PG0 0x0001
1027#define PG1 0x0002
1028#define PG2 0x0004
1029#define PG3 0x0008
1030#define PG4 0x0010
1031#define PG5 0x0020
1032#define PG6 0x0040
1033#define PG7 0x0080
1034#define PG8 0x0100
1035#define PG9 0x0200
1036#define PG10 0x0400
1037#define PG11 0x0800
1038#define PG12 0x1000
1039#define PG13 0x2000
1040#define PG14 0x4000
1041#define PG15 0x8000
1042
1043/* Port H Masks */
1044#define PH0 0x0001
1045#define PH1 0x0002
1046#define PH2 0x0004
1047#define PH3 0x0008
1048#define PH4 0x0010
1049#define PH5 0x0020
1050#define PH6 0x0040
1051#define PH7 0x0080
1052#define PH8 0x0100
1053#define PH9 0x0200
1054#define PH10 0x0400
1055#define PH11 0x0800
1056#define PH12 0x1000
1057#define PH13 0x2000
1058#define PH14 0x4000
1059#define PH15 0x8000
1060
1061
1062/* ******************* SERIAL PORT MASKS **************************************/
1063/* SPORTx_TCR1 Masks */
1064#define TSPEN 0x0001 /* Transmit Enable */
1065#define ITCLK 0x0002 /* Internal Transmit Clock Select */
1066#define DTYPE_NORM 0x0004 /* Data Format Normal */
1067#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
1068#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
1069#define TLSBIT 0x0010 /* Transmit Bit Order */
1070#define ITFS 0x0200 /* Internal Transmit Frame Sync Select */
1071#define TFSR 0x0400 /* Transmit Frame Sync Required Select */
1072#define DITFS 0x0800 /* Data-Independent Transmit Frame Sync Select */
1073#define LTFS 0x1000 /* Low Transmit Frame Sync Select */
1074#define LATFS 0x2000 /* Late Transmit Frame Sync Select */
1075#define TCKFE 0x4000 /* Clock Falling Edge Select */
1076
1077/* SPORTx_TCR2 Masks and Macro */
1078#define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
1079#define TXSE 0x0100 /* TX Secondary Enable */
1080#define TSFSE 0x0200 /* Transmit Stereo Frame Sync Enable */
1081#define TRFST 0x0400 /* Left/Right Order (1 = Right Channel 1st) */
1082
1083/* SPORTx_RCR1 Masks */
1084#define RSPEN 0x0001 /* Receive Enable */
1085#define IRCLK 0x0002 /* Internal Receive Clock Select */
1086#define DTYPE_NORM 0x0004 /* Data Format Normal */
1087#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
1088#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
1089#define RLSBIT 0x0010 /* Receive Bit Order */
1090#define IRFS 0x0200 /* Internal Receive Frame Sync Select */
1091#define RFSR 0x0400 /* Receive Frame Sync Required Select */
1092#define LRFS 0x1000 /* Low Receive Frame Sync Select */
1093#define LARFS 0x2000 /* Late Receive Frame Sync Select */
1094#define RCKFE 0x4000 /* Clock Falling Edge Select */
1095
1096/* SPORTx_RCR2 Masks */
1097#define SLEN(x) ((x)&0x1F) /* SPORT RX Word Length (2 - 31) */
1098#define RXSE 0x0100 /* RX Secondary Enable */
1099#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */
1100#define RRFST 0x0400 /* Right-First Data Order */
1101
1102/* SPORTx_STAT Masks */
1103#define RXNE 0x0001 /* Receive FIFO Not Empty Status */
1104#define RUVF 0x0002 /* Sticky Receive Underflow Status */
1105#define ROVF 0x0004 /* Sticky Receive Overflow Status */
1106#define TXF 0x0008 /* Transmit FIFO Full Status */
1107#define TUVF 0x0010 /* Sticky Transmit Underflow Status */
1108#define TOVF 0x0020 /* Sticky Transmit Overflow Status */
1109#define TXHRE 0x0040 /* Transmit Hold Register Empty */
1110
1111/* SPORTx_MCMC1 Macros */
1112#define SP_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
1113
1114/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits */
1115#define SP_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
1116
1117/* SPORTx_MCMC2 Masks */
1118#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
1119#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
1120#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
1121#define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */
1122#define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */
1123#define MCMEN 0x0010 /* Multichannel Frame Mode Enable */
1124#define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */
1125#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */
1126#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */
1127#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */
1128#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */
1129#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */
1130#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */
1131#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */
1132#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */
1133#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */
1134#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */
1135#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */
1136#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */
1137#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */
1138#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */
1139#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */
1140#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */
1141
1142
1143/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
1144/* EBIU_AMGCTL Masks */
1145#define AMCKEN 0x0001 /* Enable CLKOUT */
1146#define AMBEN_NONE 0x0000 /* All Banks Disabled */
1147#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */
1148#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */
1149#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */
1150#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */
1151
1152/* EBIU_AMBCTL0 Masks */
1153#define B0RDYEN 0x00000001 /* Bank 0 (B0) RDY Enable */
1154#define B0RDYPOL 0x00000002 /* B0 RDY Active High */
1155#define B0TT_1 0x00000004 /* B0 Transition Time (Read to Write) = 1 cycle */
1156#define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */
1157#define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */
1158#define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */
1159#define B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */
1160#define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */
1161#define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */
1162#define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */
1163#define B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */
1164#define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1165#define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1166#define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1167#define B0RAT_1 0x00000100 /* B0 Read Access Time = 1 cycle */
1168#define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */
1169#define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */
1170#define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */
1171#define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */
1172#define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */
1173#define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */
1174#define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */
1175#define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */
1176#define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */
1177#define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */
1178#define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */
1179#define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */
1180#define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */
1181#define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */
1182#define B0WAT_1 0x00001000 /* B0 Write Access Time = 1 cycle */
1183#define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */
1184#define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */
1185#define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */
1186#define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */
1187#define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */
1188#define B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */
1189#define B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */
1190#define B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */
1191#define B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */
1192#define B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */
1193#define B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */
1194#define B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */
1195#define B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */
1196#define B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */
1197
1198#define B1RDYEN 0x00010000 /* Bank 1 (B1) RDY Enable */
1199#define B1RDYPOL 0x00020000 /* B1 RDY Active High */
1200#define B1TT_1 0x00040000 /* B1 Transition Time (Read to Write) = 1 cycle */
1201#define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */
1202#define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */
1203#define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */
1204#define B1ST_1 0x00100000 /* B1 Setup Time (AOE to Read/Write) = 1 cycle */
1205#define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */
1206#define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */
1207#define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */
1208#define B1HT_1 0x00400000 /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */
1209#define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1210#define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1211#define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1212#define B1RAT_1 0x01000000 /* B1 Read Access Time = 1 cycle */
1213#define B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */
1214#define B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */
1215#define B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */
1216#define B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */
1217#define B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */
1218#define B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */
1219#define B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */
1220#define B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */
1221#define B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */
1222#define B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */
1223#define B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */
1224#define B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */
1225#define B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */
1226#define B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */
1227#define B1WAT_1 0x10000000 /* B1 Write Access Time = 1 cycle */
1228#define B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */
1229#define B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */
1230#define B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */
1231#define B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */
1232#define B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */
1233#define B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */
1234#define B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */
1235#define B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */
1236#define B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */
1237#define B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */
1238#define B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */
1239#define B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */
1240#define B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */
1241#define B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */
1242
1243/* EBIU_AMBCTL1 Masks */
1244#define B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */
1245#define B2RDYPOL 0x00000002 /* B2 RDY Active High */
1246#define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */
1247#define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */
1248#define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */
1249#define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */
1250#define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */
1251#define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */
1252#define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */
1253#define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */
1254#define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */
1255#define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1256#define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1257#define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1258#define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */
1259#define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */
1260#define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */
1261#define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */
1262#define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */
1263#define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */
1264#define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */
1265#define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */
1266#define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */
1267#define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */
1268#define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */
1269#define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */
1270#define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */
1271#define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */
1272#define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */
1273#define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */
1274#define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */
1275#define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */
1276#define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */
1277#define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */
1278#define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */
1279#define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */
1280#define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */
1281#define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */
1282#define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */
1283#define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */
1284#define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */
1285#define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */
1286#define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */
1287#define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */
1288
1289#define B3RDYEN 0x00010000 /* Bank 3 (B3) RDY Enable */
1290#define B3RDYPOL 0x00020000 /* B3 RDY Active High */
1291#define B3TT_1 0x00040000 /* B3 Transition Time (Read to Write) = 1 cycle */
1292#define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */
1293#define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */
1294#define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */
1295#define B3ST_1 0x00100000 /* B3 Setup Time (AOE to Read/Write) = 1 cycle */
1296#define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */
1297#define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */
1298#define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */
1299#define B3HT_1 0x00400000 /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */
1300#define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1301#define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1302#define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1303#define B3RAT_1 0x01000000 /* B3 Read Access Time = 1 cycle */
1304#define B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */
1305#define B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */
1306#define B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */
1307#define B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */
1308#define B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */
1309#define B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */
1310#define B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */
1311#define B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */
1312#define B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */
1313#define B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */
1314#define B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */
1315#define B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */
1316#define B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */
1317#define B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */
1318#define B3WAT_1 0x10000000 /* B3 Write Access Time = 1 cycle */
1319#define B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */
1320#define B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */
1321#define B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */
1322#define B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */
1323#define B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */
1324#define B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */
1325#define B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */
1326#define B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */
1327#define B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */
1328#define B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */
1329#define B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */
1330#define B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */
1331#define B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */
1332#define B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */
1333
1334
1335/* ********************** SDRAM CONTROLLER MASKS **********************************************/
1336/* EBIU_SDGCTL Masks */
1337#define SCTLE 0x00000001 /* Enable SDRAM Signals */
1338#define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */
1339#define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */
1340#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
1341#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
1342#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
1343#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
1344#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
1345#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
1346#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
1347#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
1348#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
1349#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
1350#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
1351#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
1352#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
1353#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
1354#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
1355#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
1356#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
1357#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
1358#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
1359#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
1360#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
1361#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
1362#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
1363#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
1364#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
1365#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
1366#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
1367#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
1368#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
1369#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
1370#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
1371#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
1372#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
1373#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
1374#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
1375#define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */
1376#define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */
1377#define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */
1378#define SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode */
1379#define EBUFE 0x02000000 /* Enable External Buffering Timing */
1380#define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */
1381#define EMREN 0x10000000 /* Extended Mode Register Enable */
1382#define TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */
1383#define CDDBG 0x40000000 /* Tristate SDRAM Controls During Bus Grant */
1384
1385/* EBIU_SDBCTL Masks */
1386#define EBE 0x0001 /* Enable SDRAM External Bank */
1387#define EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */
1388#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */
1389#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */
1390#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */
1391#define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */
1392#define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */
1393#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */
1394#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */
1395#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */
1396#define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */
1397
1398/* EBIU_SDSTAT Masks */
1399#define SDCI 0x0001 /* SDRAM Controller Idle */
1400#define SDSRA 0x0002 /* SDRAM Self-Refresh Active */
1401#define SDPUA 0x0004 /* SDRAM Power-Up Active */
1402#define SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */
1403#define SDEASE 0x0010 /* SDRAM EAB Sticky Error Status */
1404#define BGSTAT 0x0020 /* Bus Grant Status */
1405
1406
1407/* ************************** DMA CONTROLLER MASKS ********************************/
1408/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */
1409#define DMAEN 0x0001 /* DMA Channel Enable */
1410#define WNR 0x0002 /* Channel Direction (W/R*) */
1411#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */
1412#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */
1413#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */
1414#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */
1415#define RESTART 0x0020 /* DMA Buffer Clear */
1416#define DI_SEL 0x0040 /* Data Interrupt Timing Select */
1417#define DI_EN 0x0080 /* Data Interrupt Enable */
1418#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
1419#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
1420#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
1421#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
1422#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
1423#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
1424#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
1425#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
1426#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
1427#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
1428#define NDSIZE 0x0900 /* Next Descriptor Size */
1429#define DMAFLOW 0x7000 /* Flow Control */
1430#define DMAFLOW_STOP 0x0000 /* Stop Mode */
1431#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
1432#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
1433#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
1434#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
1435
1436/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
1437#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */
1438#define PMAP 0xF000 /* Peripheral Mapped To This Channel */
1439#define PMAP_PPI 0x0000 /* PPI Port DMA */
1440#define PMAP_EMACRX 0x1000 /* Ethernet Receive DMA */
1441#define PMAP_EMACTX 0x2000 /* Ethernet Transmit DMA */
1442#define PMAP_SPORT0RX 0x3000 /* SPORT0 Receive DMA */
1443#define PMAP_SPORT0TX 0x4000 /* SPORT0 Transmit DMA */
1444#define PMAP_SPORT1RX 0x5000 /* SPORT1 Receive DMA */
1445#define PMAP_SPORT1TX 0x6000 /* SPORT1 Transmit DMA */
1446#define PMAP_SPI 0x7000 /* SPI Port DMA */
1447#define PMAP_UART0RX 0x8000 /* UART0 Port Receive DMA */
1448#define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */
1449#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */
1450#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */
1451
1452/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
1453#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */
1454#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */
1455#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */
1456#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */
1457
1458
1459/* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
1460/* PPI_CONTROL Masks */
1461#define PORT_EN 0x0001 /* PPI Port Enable */
1462#define PORT_DIR 0x0002 /* PPI Port Direction */
1463#define XFR_TYPE 0x000C /* PPI Transfer Type */
1464#define PORT_CFG 0x0030 /* PPI Port Configuration */
1465#define FLD_SEL 0x0040 /* PPI Active Field Select */
1466#define PACK_EN 0x0080 /* PPI Packing Mode */
1467#define DMA32 0x0100 /* PPI 32-bit DMA Enable */
1468#define SKIP_EN 0x0200 /* PPI Skip Element Enable */
1469#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */
1470#define DLEN_8 0x0000 /* Data Length = 8 Bits */
1471#define DLEN_10 0x0800 /* Data Length = 10 Bits */
1472#define DLEN_11 0x1000 /* Data Length = 11 Bits */
1473#define DLEN_12 0x1800 /* Data Length = 12 Bits */
1474#define DLEN_13 0x2000 /* Data Length = 13 Bits */
1475#define DLEN_14 0x2800 /* Data Length = 14 Bits */
1476#define DLEN_15 0x3000 /* Data Length = 15 Bits */
1477#define DLEN_16 0x3800 /* Data Length = 16 Bits */
1478#define DLENGTH 0x3800 /* PPI Data Length */
1479#define POLC 0x4000 /* PPI Clock Polarity */
1480#define POLS 0x8000 /* PPI Frame Sync Polarity */
1481
1482/* PPI_STATUS Masks */
1483#define FLD 0x0400 /* Field Indicator */
1484#define FT_ERR 0x0800 /* Frame Track Error */
1485#define OVR 0x1000 /* FIFO Overflow Error */
1486#define UNDR 0x2000 /* FIFO Underrun Error */
1487#define ERR_DET 0x4000 /* Error Detected Indicator */
1488#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
1489
1490
1491/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/
1492/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
1493#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
1494#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
1495
1496/* TWI_PRESCALE Masks */
1497#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
1498#define TWI_ENA 0x0080 /* TWI Enable */
1499#define SCCB 0x0200 /* SCCB Compatibility Enable */
1500
1501/* TWI_SLAVE_CTRL Masks */
1502#define SEN 0x0001 /* Slave Enable */
1503#define SADD_LEN 0x0002 /* Slave Address Length */
1504#define STDVAL 0x0004 /* Slave Transmit Data Valid */
1505#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
1506#define GEN 0x0010 /* General Call Adrress Matching Enabled */
1507
1508/* TWI_SLAVE_STAT Masks */
1509#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
1510#define GCALL 0x0002 /* General Call Indicator */
1511
1512/* TWI_MASTER_CTRL Masks */
1513#define MEN 0x0001 /* Master Mode Enable */
1514#define MADD_LEN 0x0002 /* Master Address Length */
1515#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
1516#define FAST 0x0008 /* Use Fast Mode Timing Specs */
1517#define STOP 0x0010 /* Issue Stop Condition */
1518#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */
1519#define DCNT 0x3FC0 /* Data Bytes To Transfer */
1520#define SDAOVR 0x4000 /* Serial Data Override */
1521#define SCLOVR 0x8000 /* Serial Clock Override */
1522
1523/* TWI_MASTER_STAT Masks */
1524#define MPROG 0x0001 /* Master Transfer In Progress */
1525#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */
1526#define ANAK 0x0004 /* Address Not Acknowledged */
1527#define DNAK 0x0008 /* Data Not Acknowledged */
1528#define BUFRDERR 0x0010 /* Buffer Read Error */
1529#define BUFWRERR 0x0020 /* Buffer Write Error */
1530#define SDASEN 0x0040 /* Serial Data Sense */
1531#define SCLSEN 0x0080 /* Serial Clock Sense */
1532#define BUSBUSY 0x0100 /* Bus Busy Indicator */
1533
1534/* TWI_INT_SRC and TWI_INT_ENABLE Masks */
1535#define SINIT 0x0001 /* Slave Transfer Initiated */
1536#define SCOMP 0x0002 /* Slave Transfer Complete */
1537#define SERR 0x0004 /* Slave Transfer Error */
1538#define SOVF 0x0008 /* Slave Overflow */
1539#define MCOMP 0x0010 /* Master Transfer Complete */
1540#define MERR 0x0020 /* Master Transfer Error */
1541#define XMTSERV 0x0040 /* Transmit FIFO Service */
1542#define RCVSERV 0x0080 /* Receive FIFO Service */
1543
1544/* TWI_FIFO_CTRL Masks */
1545#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
1546#define RCVFLUSH 0x0002 /* Receive Buffer Flush */
1547#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */
1548#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */
1549
1550/* TWI_FIFO_STAT Masks */
1551#define XMTSTAT 0x0003 /* Transmit FIFO Status */
1552#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */
1553#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */
1554#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */
1555
1556#define RCVSTAT 0x000C /* Receive FIFO Status */
1557#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */
1558#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
1559#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
1560
1561
1562/* Omit CAN masks from defBF534.h */
1563
1564/* ******************* PIN CONTROL REGISTER MASKS ************************/
1565/* PORT_MUX Masks */
1566#define PJSE 0x0001 /* Port J SPI/SPORT Enable */
1567#define PJSE_SPORT 0x0000 /* Enable TFS0/DT0PRI */
1568#define PJSE_SPI 0x0001 /* Enable SPI_SSEL3:2 */
1569
1570#define PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */
1571#define PJCE_SPORT 0x0000 /* Enable DR0SEC/DT0SEC */
1572#define PJCE_CAN 0x0002 /* Enable CAN RX/TX */
1573#define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */
1574
1575#define PFDE 0x0008 /* Port F DMA Request Enable */
1576#define PFDE_UART 0x0000 /* Enable UART0 RX/TX */
1577#define PFDE_DMA 0x0008 /* Enable DMAR1:0 */
1578
1579#define PFTE 0x0010 /* Port F Timer Enable */
1580#define PFTE_UART 0x0000 /* Enable UART1 RX/TX */
1581#define PFTE_TIMER 0x0010 /* Enable TMR7:6 */
1582
1583#define PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */
1584#define PFS6E_TIMER 0x0000 /* Enable TMR5 */
1585#define PFS6E_SPI 0x0020 /* Enable SPI_SSEL6 */
1586
1587#define PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */
1588#define PFS5E_TIMER 0x0000 /* Enable TMR4 */
1589#define PFS5E_SPI 0x0040 /* Enable SPI_SSEL5 */
1590
1591#define PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */
1592#define PFS4E_TIMER 0x0000 /* Enable TMR3 */
1593#define PFS4E_SPI 0x0080 /* Enable SPI_SSEL4 */
1594
1595#define PFFE 0x0100 /* Port F PPI Frame Sync Enable */
1596#define PFFE_TIMER 0x0000 /* Enable TMR2 */
1597#define PFFE_PPI 0x0100 /* Enable PPI FS3 */
1598
1599#define PGSE 0x0200 /* Port G SPORT1 Secondary Enable */
1600#define PGSE_PPI 0x0000 /* Enable PPI D9:8 */
1601#define PGSE_SPORT 0x0200 /* Enable DR1SEC/DT1SEC */
1602
1603#define PGRE 0x0400 /* Port G SPORT1 Receive Enable */
1604#define PGRE_PPI 0x0000 /* Enable PPI D12:10 */
1605#define PGRE_SPORT 0x0400 /* Enable DR1PRI/RFS1/RSCLK1 */
1606
1607#define PGTE 0x0800 /* Port G SPORT1 Transmit Enable */
1608#define PGTE_PPI 0x0000 /* Enable PPI D15:13 */
1609#define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */
1610
1611
1612/* ****************** HANDSHAKE DMA (HDMA) MASKS *********************/
1613/* HDMAx_CTL Masks */
1614#define HMDMAEN 0x0001 /* Enable Handshake DMA 0/1 */
1615#define REP 0x0002 /* HDMA Request Polarity */
1616#define UTE 0x0004 /* Urgency Threshold Enable */
1617#define OIE 0x0010 /* Overflow Interrupt Enable */
1618#define BDIE 0x0020 /* Block Done Interrupt Enable */
1619#define MBDI 0x0040 /* Mask Block Done IRQ If Pending ECNT */
1620#define DRQ 0x0300 /* HDMA Request Type */
1621#define DRQ_NONE 0x0000 /* No Request */
1622#define DRQ_SINGLE 0x0100 /* Channels Request Single */
1623#define DRQ_MULTI 0x0200 /* Channels Request Multi (Default) */
1624#define DRQ_URGENT 0x0300 /* Channels Request Multi Urgent */
1625#define RBC 0x1000 /* Reload BCNT With IBCNT */
1626#define PS 0x2000 /* HDMA Pin Status */
1627#define OI 0x4000 /* Overflow Interrupt Generated */
1628#define BDI 0x8000 /* Block Done Interrupt Generated */
1629
1630/* entry addresses of the user-callable Boot ROM functions */
1631
1632#define _BOOTROM_RESET 0xEF000000
1633#define _BOOTROM_FINAL_INIT 0xEF000002
1634#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
1635#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
1636#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
1637#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
1638#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
1639#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
1640#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
1641
1642/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
1643#define PGDE_UART PFDE_UART
1644#define PGDE_DMA PFDE_DMA
1645#define CKELOW SCKELOW
1646
1647/* ==== end from defBF534.h ==== */
1648
1649/* HOST Port Registers */
1650
1651#define HOST_CONTROL 0xffc03400 /* HOST Control Register */
1652#define HOST_STATUS 0xffc03404 /* HOST Status Register */
1653#define HOST_TIMEOUT 0xffc03408 /* HOST Acknowledge Mode Timeout Register */
1654
1655/* Counter Registers */
1656
1657#define CNT_CONFIG 0xffc03500 /* Configuration Register */
1658#define CNT_IMASK 0xffc03504 /* Interrupt Mask Register */
1659#define CNT_STATUS 0xffc03508 /* Status Register */
1660#define CNT_COMMAND 0xffc0350c /* Command Register */
1661#define CNT_DEBOUNCE 0xffc03510 /* Debounce Register */
1662#define CNT_COUNTER 0xffc03514 /* Counter Register */
1663#define CNT_MAX 0xffc03518 /* Maximal Count Register */
1664#define CNT_MIN 0xffc0351c /* Minimal Count Register */
1665
1666/* OTP/FUSE Registers */
1667
1668#define OTP_CONTROL 0xffc03600 /* OTP/Fuse Control Register */
1669#define OTP_BEN 0xffc03604 /* OTP/Fuse Byte Enable */
1670#define OTP_STATUS 0xffc03608 /* OTP/Fuse Status */
1671#define OTP_TIMING 0xffc0360c /* OTP/Fuse Access Timing */
1672
1673/* Security Registers */
1674
1675#define SECURE_SYSSWT 0xffc03620 /* Secure System Switches */
1676#define SECURE_CONTROL 0xffc03624 /* Secure Control */
1677#define SECURE_STATUS 0xffc03628 /* Secure Status */
1678
1679/* OTP Read/Write Data Buffer Registers */
1680
1681#define OTP_DATA0 0xffc03680 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1682#define OTP_DATA1 0xffc03684 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1683#define OTP_DATA2 0xffc03688 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1684#define OTP_DATA3 0xffc0368c /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1685
1686/* NFC Registers */
1687
1688#define NFC_CTL 0xffc03700 /* NAND Control Register */
1689#define NFC_STAT 0xffc03704 /* NAND Status Register */
1690#define NFC_IRQSTAT 0xffc03708 /* NAND Interrupt Status Register */
1691#define NFC_IRQMASK 0xffc0370c /* NAND Interrupt Mask Register */
1692#define NFC_ECC0 0xffc03710 /* NAND ECC Register 0 */
1693#define NFC_ECC1 0xffc03714 /* NAND ECC Register 1 */
1694#define NFC_ECC2 0xffc03718 /* NAND ECC Register 2 */
1695#define NFC_ECC3 0xffc0371c /* NAND ECC Register 3 */
1696#define NFC_COUNT 0xffc03720 /* NAND ECC Count Register */
1697#define NFC_RST 0xffc03724 /* NAND ECC Reset Register */
1698#define NFC_PGCTL 0xffc03728 /* NAND Page Control Register */
1699#define NFC_READ 0xffc0372c /* NAND Read Data Register */
1700#define NFC_ADDR 0xffc03740 /* NAND Address Register */
1701#define NFC_CMD 0xffc03744 /* NAND Command Register */
1702#define NFC_DATA_WR 0xffc03748 /* NAND Data Write Register */
1703#define NFC_DATA_RD 0xffc0374c /* NAND Data Read Register */
1704
1705/* ********************************************************** */
1706/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
1707/* and MULTI BIT READ MACROS */
1708/* ********************************************************** */
1709
1710/* Bit masks for HOST_CONTROL */
1711
1712#define HOST_CNTR_HOST_EN 0x1 /* Host Enable */
1713#define HOST_CNTR_nHOST_EN 0x0
1714#define HOST_CNTR_HOST_END 0x2 /* Host Endianess */
1715#define HOST_CNTR_nHOST_END 0x0
1716#define HOST_CNTR_DATA_SIZE 0x4 /* Data Size */
1717#define HOST_CNTR_nDATA_SIZE 0x0
1718#define HOST_CNTR_HOST_RST 0x8 /* Host Reset */
1719#define HOST_CNTR_nHOST_RST 0x0
1720#define HOST_CNTR_HRDY_OVR 0x20 /* Host Ready Override */
1721#define HOST_CNTR_nHRDY_OVR 0x0
1722#define HOST_CNTR_INT_MODE 0x40 /* Interrupt Mode */
1723#define HOST_CNTR_nINT_MODE 0x0
1724#define HOST_CNTR_BT_EN 0x80 /* Bus Timeout Enable */
1725#define HOST_CNTR_ nBT_EN 0x0
1726#define HOST_CNTR_EHW 0x100 /* Enable Host Write */
1727#define HOST_CNTR_nEHW 0x0
1728#define HOST_CNTR_EHR 0x200 /* Enable Host Read */
1729#define HOST_CNTR_nEHR 0x0
1730#define HOST_CNTR_BDR 0x400 /* Burst DMA Requests */
1731#define HOST_CNTR_nBDR 0x0
1732
1733/* Bit masks for HOST_STATUS */
1734
1735#define HOST_STAT_READY 0x1 /* DMA Ready */
1736#define HOST_STAT_nREADY 0x0
1737#define HOST_STAT_FIFOFULL 0x2 /* FIFO Full */
1738#define HOST_STAT_nFIFOFULL 0x0
1739#define HOST_STAT_FIFOEMPTY 0x4 /* FIFO Empty */
1740#define HOST_STAT_nFIFOEMPTY 0x0
1741#define HOST_STAT_COMPLETE 0x8 /* DMA Complete */
1742#define HOST_STAT_nCOMPLETE 0x0
1743#define HOST_STAT_HSHK 0x10 /* Host Handshake */
1744#define HOST_STAT_nHSHK 0x0
1745#define HOST_STAT_TIMEOUT 0x20 /* Host Timeout */
1746#define HOST_STAT_nTIMEOUT 0x0
1747#define HOST_STAT_HIRQ 0x40 /* Host Interrupt Request */
1748#define HOST_STAT_nHIRQ 0x0
1749#define HOST_STAT_ALLOW_CNFG 0x80 /* Allow New Configuration */
1750#define HOST_STAT_nALLOW_CNFG 0x0
1751#define HOST_STAT_DMA_DIR 0x100 /* DMA Direction */
1752#define HOST_STAT_nDMA_DIR 0x0
1753#define HOST_STAT_BTE 0x200 /* Bus Timeout Enabled */
1754#define HOST_STAT_nBTE 0x0
1755#define HOST_STAT_HOSTRD_DONE 0x8000 /* Host Read Completion Interrupt */
1756#define HOST_STAT_nHOSTRD_DONE 0x0
1757
1758/* Bit masks for HOST_TIMEOUT */
1759
1760#define HOST_COUNT_TIMEOUT 0x7ff /* Host Timeout count */
1761
1762/* Bit masks for CNT_CONFIG */
1763
1764#define CNTE 0x1 /* Counter Enable */
1765#define nCNTE 0x0
1766#define DEBE 0x2 /* Debounce Enable */
1767#define nDEBE 0x0
1768#define CDGINV 0x10 /* CDG Pin Polarity Invert */
1769#define nCDGINV 0x0
1770#define CUDINV 0x20 /* CUD Pin Polarity Invert */
1771#define nCUDINV 0x0
1772#define CZMINV 0x40 /* CZM Pin Polarity Invert */
1773#define nCZMINV 0x0
1774#define CNTMODE 0x700 /* Counter Operating Mode */
1775#define ZMZC 0x800 /* CZM Zeroes Counter Enable */
1776#define nZMZC 0x0
1777#define BNDMODE 0x3000 /* Boundary register Mode */
1778#define INPDIS 0x8000 /* CUG and CDG Input Disable */
1779#define nINPDIS 0x0
1780
1781/* Bit masks for CNT_IMASK */
1782
1783#define ICIE 0x1 /* Illegal Gray/Binary Code Interrupt Enable */
1784#define nICIE 0x0
1785#define UCIE 0x2 /* Up count Interrupt Enable */
1786#define nUCIE 0x0
1787#define DCIE 0x4 /* Down count Interrupt Enable */
1788#define nDCIE 0x0
1789#define MINCIE 0x8 /* Min Count Interrupt Enable */
1790#define nMINCIE 0x0
1791#define MAXCIE 0x10 /* Max Count Interrupt Enable */
1792#define nMAXCIE 0x0
1793#define COV31IE 0x20 /* Bit 31 Overflow Interrupt Enable */
1794#define nCOV31IE 0x0
1795#define COV15IE 0x40 /* Bit 15 Overflow Interrupt Enable */
1796#define nCOV15IE 0x0
1797#define CZEROIE 0x80 /* Count to Zero Interrupt Enable */
1798#define nCZEROIE 0x0
1799#define CZMIE 0x100 /* CZM Pin Interrupt Enable */
1800#define nCZMIE 0x0
1801#define CZMEIE 0x200 /* CZM Error Interrupt Enable */
1802#define nCZMEIE 0x0
1803#define CZMZIE 0x400 /* CZM Zeroes Counter Interrupt Enable */
1804#define nCZMZIE 0x0
1805
1806/* Bit masks for CNT_STATUS */
1807
1808#define ICII 0x1 /* Illegal Gray/Binary Code Interrupt Identifier */
1809#define nICII 0x0
1810#define UCII 0x2 /* Up count Interrupt Identifier */
1811#define nUCII 0x0
1812#define DCII 0x4 /* Down count Interrupt Identifier */
1813#define nDCII 0x0
1814#define MINCII 0x8 /* Min Count Interrupt Identifier */
1815#define nMINCII 0x0
1816#define MAXCII 0x10 /* Max Count Interrupt Identifier */
1817#define nMAXCII 0x0
1818#define COV31II 0x20 /* Bit 31 Overflow Interrupt Identifier */
1819#define nCOV31II 0x0
1820#define COV15II 0x40 /* Bit 15 Overflow Interrupt Identifier */
1821#define nCOV15II 0x0
1822#define CZEROII 0x80 /* Count to Zero Interrupt Identifier */
1823#define nCZEROII 0x0
1824#define CZMII 0x100 /* CZM Pin Interrupt Identifier */
1825#define nCZMII 0x0
1826#define CZMEII 0x200 /* CZM Error Interrupt Identifier */
1827#define nCZMEII 0x0
1828#define CZMZII 0x400 /* CZM Zeroes Counter Interrupt Identifier */
1829#define nCZMZII 0x0
1830
1831/* Bit masks for CNT_COMMAND */
1832
1833#define W1LCNT 0xf /* Load Counter Register */
1834#define W1LMIN 0xf0 /* Load Min Register */
1835#define W1LMAX 0xf00 /* Load Max Register */
1836#define W1ZMONCE 0x1000 /* Enable CZM Clear Counter Once */
1837#define nW1ZMONCE 0x0
1838
1839/* Bit masks for CNT_DEBOUNCE */
1840
1841#define DPRESCALE 0xf /* Load Counter Register */
1842
1843/* Bit masks for OTP_CONTROL */
1844
1845#define FUSE_FADDR 0x1ff /* OTP/Fuse Address */
1846#define FIEN 0x800 /* OTP/Fuse Interrupt Enable */
1847#define nFIEN 0x0
1848#define FTESTDEC 0x1000 /* OTP/Fuse Test Decoder */
1849#define nFTESTDEC 0x0
1850#define FWRTEST 0x2000 /* OTP/Fuse Write Test */
1851#define nFWRTEST 0x0
1852#define FRDEN 0x4000 /* OTP/Fuse Read Enable */
1853#define nFRDEN 0x0
1854#define FWREN 0x8000 /* OTP/Fuse Write Enable */
1855#define nFWREN 0x0
1856
1857/* Bit masks for OTP_BEN */
1858
1859#define FBEN 0xffff /* OTP/Fuse Byte Enable */
1860
1861/* Bit masks for OTP_STATUS */
1862
1863#define FCOMP 0x1 /* OTP/Fuse Access Complete */
1864#define nFCOMP 0x0
1865#define FERROR 0x2 /* OTP/Fuse Access Error */
1866#define nFERROR 0x0
1867#define MMRGLOAD 0x10 /* Memory Mapped Register Gasket Load */
1868#define nMMRGLOAD 0x0
1869#define MMRGLOCK 0x20 /* Memory Mapped Register Gasket Lock */
1870#define nMMRGLOCK 0x0
1871#define FPGMEN 0x40 /* OTP/Fuse Program Enable */
1872#define nFPGMEN 0x0
1873
1874/* Bit masks for OTP_TIMING */
1875
1876#define USECDIV 0xff /* Micro Second Divider */
1877#define READACC 0x7f00 /* Read Access Time */
1878#define CPUMPRL 0x38000 /* Charge Pump Release Time */
1879#define CPUMPSU 0xc0000 /* Charge Pump Setup Time */
1880#define CPUMPHD 0xf00000 /* Charge Pump Hold Time */
1881#define PGMTIME 0xff000000 /* Program Time */
1882
1883/* Bit masks for SECURE_SYSSWT */
1884
1885#define EMUDABL 0x1 /* Emulation Disable. */
1886#define nEMUDABL 0x0
1887#define RSTDABL 0x2 /* Reset Disable */
1888#define nRSTDABL 0x0
1889#define L1IDABL 0x1c /* L1 Instruction Memory Disable. */
1890#define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */
1891#define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */
1892#define DMA0OVR 0x800 /* DMA0 Memory Access Override */
1893#define nDMA0OVR 0x0
1894#define DMA1OVR 0x1000 /* DMA1 Memory Access Override */
1895#define nDMA1OVR 0x0
1896#define EMUOVR 0x4000 /* Emulation Override */
1897#define nEMUOVR 0x0
1898#define OTPSEN 0x8000 /* OTP Secrets Enable. */
1899#define nOTPSEN 0x0
1900#define L2DABL 0x70000 /* L2 Memory Disable. */
1901
1902/* Bit masks for SECURE_CONTROL */
1903
1904#define SECURE0 0x1 /* SECURE 0 */
1905#define nSECURE0 0x0
1906#define SECURE1 0x2 /* SECURE 1 */
1907#define nSECURE1 0x0
1908#define SECURE2 0x4 /* SECURE 2 */
1909#define nSECURE2 0x0
1910#define SECURE3 0x8 /* SECURE 3 */
1911#define nSECURE3 0x0
1912
1913/* Bit masks for SECURE_STATUS */
1914
1915#define SECMODE 0x3 /* Secured Mode Control State */
1916#define NMI 0x4 /* Non Maskable Interrupt */
1917#define nNMI 0x0
1918#define AFVALID 0x8 /* Authentication Firmware Valid */
1919#define nAFVALID 0x0
1920#define AFEXIT 0x10 /* Authentication Firmware Exit */
1921#define nAFEXIT 0x0
1922#define SECSTAT 0xe0 /* Secure Status */
1923
1924/* Bit masks for NFC_CTL */
1925
1926#define WR_DLY 0xf /* Write Strobe Delay */
1927#define RD_DLY 0xf0 /* Read Strobe Delay */
1928#define NWIDTH 0x100 /* NAND Data Width */
1929#define nNWIDTH 0x0
1930#define PG_SIZE 0x200 /* Page Size */
1931#define nPG_SIZE 0x0
1932
1933/* Bit masks for NFC_STAT */
1934
1935#define NBUSY 0x1 /* Not Busy */
1936#define nNBUSY 0x0
1937#define WB_FULL 0x2 /* Write Buffer Full */
1938#define nWB_FULL 0x0
1939#define PG_WR_STAT 0x4 /* Page Write Pending */
1940#define nPG_WR_STAT 0x0
1941#define PG_RD_STAT 0x8 /* Page Read Pending */
1942#define nPG_RD_STAT 0x0
1943#define WB_EMPTY 0x10 /* Write Buffer Empty */
1944#define nWB_EMPTY 0x0
1945
1946/* Bit masks for NFC_IRQSTAT */
1947
1948#define NBUSYIRQ 0x1 /* Not Busy IRQ */
1949#define nNBUSYIRQ 0x0
1950#define WB_OVF 0x2 /* Write Buffer Overflow */
1951#define nWB_OVF 0x0
1952#define WB_EDGE 0x4 /* Write Buffer Edge Detect */
1953#define nWB_EDGE 0x0
1954#define RD_RDY 0x8 /* Read Data Ready */
1955#define nRD_RDY 0x0
1956#define WR_DONE 0x10 /* Page Write Done */
1957#define nWR_DONE 0x0
1958
1959/* Bit masks for NFC_IRQMASK */
1960
1961#define MASK_BUSYIRQ 0x1 /* Mask Not Busy IRQ */
1962#define nMASK_BUSYIRQ 0x0
1963#define MASK_WBOVF 0x2 /* Mask Write Buffer Overflow */
1964#define nMASK_WBOVF 0x0
1965#define MASK_WBEMPTY 0x4 /* Mask Write Buffer Empty */
1966#define nMASK_WBEMPTY 0x0
1967#define MASK_RDRDY 0x8 /* Mask Read Data Ready */
1968#define nMASK_RDRDY 0x0
1969#define MASK_WRDONE 0x10 /* Mask Write Done */
1970#define nMASK_WRDONE 0x0
1971
1972/* Bit masks for NFC_RST */
1973
1974#define ECC_RST 0x1 /* ECC (and NFC counters) Reset */
1975#define nECC_RST 0x0
1976
1977/* Bit masks for NFC_PGCTL */
1978
1979#define PG_RD_START 0x1 /* Page Read Start */
1980#define nPG_RD_START 0x0
1981#define PG_WR_START 0x2 /* Page Write Start */
1982#define nPG_WR_START 0x0
1983
1984/* Bit masks for NFC_ECC0 */
1985
1986#define ECC0 0x7ff /* Parity Calculation Result0 */
1987
1988/* Bit masks for NFC_ECC1 */
1989
1990#define ECC1 0x7ff /* Parity Calculation Result1 */
1991
1992/* Bit masks for NFC_ECC2 */
1993
1994#define ECC2 0x7ff /* Parity Calculation Result2 */
1995
1996/* Bit masks for NFC_ECC3 */
1997
1998#define ECC3 0x7ff /* Parity Calculation Result3 */
1999
2000/* Bit masks for NFC_COUNT */
2001
2002#define ECCCNT 0x3ff /* Transfer Count */
2003
2004
2005#endif /* _DEF_BF52X_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/dma.h b/arch/blackfin/mach-bf527/include/mach/dma.h
new file mode 100644
index 000000000000..49dd693223e8
--- /dev/null
+++ b/arch/blackfin/mach-bf527/include/mach/dma.h
@@ -0,0 +1,62 @@
1/*
2 * file: include/asm-blackfin/mach-bf527/dma.h
3 * based on: include/asm-blackfin/mach-bf537/dma.h
4 * author: Michael Hennerich (michael.hennerich@analog.com)
5 *
6 * created:
7 * description:
8 * system DMA map
9 * rev:
10 *
11 * modified:
12 *
13 *
14 * bugs: enter bugs at http://blackfin.uclinux.org/
15 *
16 * this program is free software; you can redistribute it and/or modify
17 * it under the terms of the gnu general public license as published by
18 * the free software foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * this program is distributed in the hope that it will be useful,
22 * but without any warranty; without even the implied warranty of
23 * merchantability or fitness for a particular purpose. see the
24 * gnu general public license for more details.
25 *
26 * you should have received a copy of the gnu general public license
27 * along with this program; see the file copying.
28 * if not, write to the free software foundation,
29 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
30 */
31
32#ifndef _MACH_DMA_H_
33#define _MACH_DMA_H_
34
35#define MAX_BLACKFIN_DMA_CHANNEL 16
36
37#define CH_PPI 0 /* PPI receive/transmit or NFC */
38#define CH_EMAC_RX 1 /* Ethernet MAC receive or HOSTDP */
39#define CH_EMAC_HOSTDP 1 /* Ethernet MAC receive or HOSTDP */
40#define CH_EMAC_TX 2 /* Ethernet MAC transmit or NFC */
41#define CH_SPORT0_RX 3 /* SPORT0 receive */
42#define CH_SPORT0_TX 4 /* SPORT0 transmit */
43#define CH_SPORT1_RX 5 /* SPORT1 receive */
44#define CH_SPORT1_TX 6 /* SPORT1 transmit */
45#define CH_SPI 7 /* SPI transmit/receive */
46#define CH_UART0_RX 8 /* UART0 receive */
47#define CH_UART0_TX 9 /* UART0 transmit */
48#define CH_UART1_RX 10 /* UART1 receive */
49#define CH_UART1_TX 11 /* UART1 transmit */
50
51#define CH_MEM_STREAM0_DEST 12 /* TX */
52#define CH_MEM_STREAM0_SRC 13 /* RX */
53#define CH_MEM_STREAM1_DEST 14 /* TX */
54#define CH_MEM_STREAM1_SRC 15 /* RX */
55
56#if defined(CONFIG_BF527_NAND_D_PORTF)
57#define CH_NFC CH_PPI /* PPI receive/transmit or NFC */
58#elif defined(CONFIG_BF527_NAND_D_PORTH)
59#define CH_NFC CH_EMAC_TX /* PPI receive/transmit or NFC */
60#endif
61
62#endif
diff --git a/arch/blackfin/mach-bf527/include/mach/irq.h b/arch/blackfin/mach-bf527/include/mach/irq.h
new file mode 100644
index 000000000000..4e2b3f2020e5
--- /dev/null
+++ b/arch/blackfin/mach-bf527/include/mach/irq.h
@@ -0,0 +1,259 @@
1/*
2 * file: include/asm-blackfin/mach-bf527/irq.h
3 * based on: include/asm-blackfin/mach-bf537/irq.h
4 * author: Michael Hennerich (michael.hennerich@analog.com)
5 *
6 * created:
7 * description:
8 * system mmr register map
9 * rev:
10 *
11 * modified:
12 *
13 *
14 * bugs: enter bugs at http://blackfin.uclinux.org/
15 *
16 * this program is free software; you can redistribute it and/or modify
17 * it under the terms of the gnu general public license as published by
18 * the free software foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * this program is distributed in the hope that it will be useful,
22 * but without any warranty; without even the implied warranty of
23 * merchantability or fitness for a particular purpose. see the
24 * gnu general public license for more details.
25 *
26 * you should have received a copy of the gnu general public license
27 * along with this program; see the file copying.
28 * if not, write to the free software foundation,
29 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
30 */
31
32#ifndef _BF527_IRQ_H_
33#define _BF527_IRQ_H_
34
35/*
36 * Interrupt source definitions
37 Event Source Core Event Name
38 Core Emulation **
39 Events (highest priority) EMU 0
40 Reset RST 1
41 NMI NMI 2
42 Exception EVX 3
43 Reserved -- 4
44 Hardware Error IVHW 5
45 Core Timer IVTMR 6 *
46
47 .....
48
49 Software Interrupt 1 IVG14 31
50 Software Interrupt 2 --
51 (lowest priority) IVG15 32 *
52*/
53
54#define NR_PERI_INTS (2 * 32)
55
56/* The ABSTRACT IRQ definitions */
57/** the first seven of the following are fixed, the rest you change if you need to **/
58#define IRQ_EMU 0 /* Emulation */
59#define IRQ_RST 1 /* reset */
60#define IRQ_NMI 2 /* Non Maskable */
61#define IRQ_EVX 3 /* Exception */
62#define IRQ_UNUSED 4 /* - unused interrupt */
63#define IRQ_HWERR 5 /* Hardware Error */
64#define IRQ_CORETMR 6 /* Core timer */
65
66#define BFIN_IRQ(x) ((x) + 7)
67
68#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
69#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */
70#define IRQ_DMAR0_BLK BFIN_IRQ(2) /* DMAR0 Block Interrupt */
71#define IRQ_DMAR1_BLK BFIN_IRQ(3) /* DMAR1 Block Interrupt */
72#define IRQ_DMAR0_OVR BFIN_IRQ(4) /* DMAR0 Overflow Error */
73#define IRQ_DMAR1_OVR BFIN_IRQ(5) /* DMAR1 Overflow Error */
74#define IRQ_PPI_ERROR BFIN_IRQ(6) /* PPI Error */
75#define IRQ_MAC_ERROR BFIN_IRQ(7) /* MAC Status */
76#define IRQ_SPORT0_ERROR BFIN_IRQ(8) /* SPORT0 Status */
77#define IRQ_SPORT1_ERROR BFIN_IRQ(9) /* SPORT1 Status */
78#define IRQ_UART0_ERROR BFIN_IRQ(12) /* UART0 Status */
79#define IRQ_UART1_ERROR BFIN_IRQ(13) /* UART1 Status */
80#define IRQ_RTC BFIN_IRQ(14) /* RTC */
81#define IRQ_PPI BFIN_IRQ(15) /* DMA Channel 0 (PPI/NAND) */
82#define IRQ_SPORT0_RX BFIN_IRQ(16) /* DMA 3 Channel (SPORT0 RX) */
83#define IRQ_SPORT0_TX BFIN_IRQ(17) /* DMA 4 Channel (SPORT0 TX) */
84#define IRQ_SPORT1_RX BFIN_IRQ(18) /* DMA 5 Channel (SPORT1 RX) */
85#define IRQ_SPORT1_TX BFIN_IRQ(19) /* DMA 6 Channel (SPORT1 TX) */
86#define IRQ_TWI BFIN_IRQ(20) /* TWI */
87#define IRQ_SPI BFIN_IRQ(21) /* DMA 7 Channel (SPI) */
88#define IRQ_UART0_RX BFIN_IRQ(22) /* DMA8 Channel (UART0 RX) */
89#define IRQ_UART0_TX BFIN_IRQ(23) /* DMA9 Channel (UART0 TX) */
90#define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */
91#define IRQ_UART1_TX BFIN_IRQ(25) /* DMA11 Channel (UART1 TX) */
92#define IRQ_OPTSEC BFIN_IRQ(26) /* OTPSEC Interrupt */
93#define IRQ_CNT BFIN_IRQ(27) /* GP Counter */
94#define IRQ_MAC_RX BFIN_IRQ(28) /* DMA1 Channel (MAC RX/HDMA) */
95#define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */
96#define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */
97#define IRQ_NFC BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */
98#define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */
99#define IRQ_TMR0 BFIN_IRQ(32) /* Timer 0 */
100#define IRQ_TMR1 BFIN_IRQ(33) /* Timer 1 */
101#define IRQ_TMR2 BFIN_IRQ(34) /* Timer 2 */
102#define IRQ_TMR3 BFIN_IRQ(35) /* Timer 3 */
103#define IRQ_TMR4 BFIN_IRQ(36) /* Timer 4 */
104#define IRQ_TMR5 BFIN_IRQ(37) /* Timer 5 */
105#define IRQ_TMR6 BFIN_IRQ(38) /* Timer 6 */
106#define IRQ_TMR7 BFIN_IRQ(39) /* Timer 7 */
107#define IRQ_PORTG_INTA BFIN_IRQ(40) /* Port G Interrupt A */
108#define IRQ_PORTG_INTB BFIN_IRQ(41) /* Port G Interrupt B */
109#define IRQ_MEM_DMA0 BFIN_IRQ(42) /* MDMA Stream 0 */
110#define IRQ_MEM_DMA1 BFIN_IRQ(43) /* MDMA Stream 1 */
111#define IRQ_WATCH BFIN_IRQ(44) /* Software Watchdog Timer */
112#define IRQ_PORTF_INTA BFIN_IRQ(45) /* Port F Interrupt A */
113#define IRQ_PORTF_INTB BFIN_IRQ(46) /* Port F Interrupt B */
114#define IRQ_SPI_ERROR BFIN_IRQ(47) /* SPI Status */
115#define IRQ_NFC_ERROR BFIN_IRQ(48) /* NAND Error */
116#define IRQ_HDMA_ERROR BFIN_IRQ(49) /* HDMA Error */
117#define IRQ_HDMA BFIN_IRQ(50) /* HDMA (TFI) */
118#define IRQ_USB_EINT BFIN_IRQ(51) /* USB_EINT Interrupt */
119#define IRQ_USB_INT0 BFIN_IRQ(52) /* USB_INT0 Interrupt */
120#define IRQ_USB_INT1 BFIN_IRQ(53) /* USB_INT1 Interrupt */
121#define IRQ_USB_INT2 BFIN_IRQ(54) /* USB_INT2 Interrupt */
122#define IRQ_USB_DMA BFIN_IRQ(55) /* USB_DMAINT Interrupt */
123
124#define SYS_IRQS BFIN_IRQ(63) /* 70 */
125
126#define IRQ_PF0 71
127#define IRQ_PF1 72
128#define IRQ_PF2 73
129#define IRQ_PF3 74
130#define IRQ_PF4 75
131#define IRQ_PF5 76
132#define IRQ_PF6 77
133#define IRQ_PF7 78
134#define IRQ_PF8 79
135#define IRQ_PF9 80
136#define IRQ_PF10 81
137#define IRQ_PF11 82
138#define IRQ_PF12 83
139#define IRQ_PF13 84
140#define IRQ_PF14 85
141#define IRQ_PF15 86
142
143#define IRQ_PG0 87
144#define IRQ_PG1 88
145#define IRQ_PG2 89
146#define IRQ_PG3 90
147#define IRQ_PG4 91
148#define IRQ_PG5 92
149#define IRQ_PG6 93
150#define IRQ_PG7 94
151#define IRQ_PG8 95
152#define IRQ_PG9 96
153#define IRQ_PG10 97
154#define IRQ_PG11 98
155#define IRQ_PG12 99
156#define IRQ_PG13 100
157#define IRQ_PG14 101
158#define IRQ_PG15 102
159
160#define IRQ_PH0 103
161#define IRQ_PH1 104
162#define IRQ_PH2 105
163#define IRQ_PH3 106
164#define IRQ_PH4 107
165#define IRQ_PH5 108
166#define IRQ_PH6 109
167#define IRQ_PH7 110
168#define IRQ_PH8 111
169#define IRQ_PH9 112
170#define IRQ_PH10 113
171#define IRQ_PH11 114
172#define IRQ_PH12 115
173#define IRQ_PH13 116
174#define IRQ_PH14 117
175#define IRQ_PH15 118
176
177#define GPIO_IRQ_BASE IRQ_PF0
178
179#define NR_IRQS (IRQ_PH15+1)
180
181#define IVG7 7
182#define IVG8 8
183#define IVG9 9
184#define IVG10 10
185#define IVG11 11
186#define IVG12 12
187#define IVG13 13
188#define IVG14 14
189#define IVG15 15
190
191/* IAR0 BIT FIELDS */
192#define IRQ_PLL_WAKEUP_POS 0
193#define IRQ_DMA0_ERROR_POS 4
194#define IRQ_DMAR0_BLK_POS 8
195#define IRQ_DMAR1_BLK_POS 12
196#define IRQ_DMAR0_OVR_POS 16
197#define IRQ_DMAR1_OVR_POS 20
198#define IRQ_PPI_ERROR_POS 24
199#define IRQ_MAC_ERROR_POS 28
200
201/* IAR1 BIT FIELDS */
202#define IRQ_SPORT0_ERROR_POS 0
203#define IRQ_SPORT1_ERROR_POS 4
204#define IRQ_UART0_ERROR_POS 16
205#define IRQ_UART1_ERROR_POS 20
206#define IRQ_RTC_POS 24
207#define IRQ_PPI_POS 28
208
209/* IAR2 BIT FIELDS */
210#define IRQ_SPORT0_RX_POS 0
211#define IRQ_SPORT0_TX_POS 4
212#define IRQ_SPORT1_RX_POS 8
213#define IRQ_SPORT1_TX_POS 12
214#define IRQ_TWI_POS 16
215#define IRQ_SPI_POS 20
216#define IRQ_UART0_RX_POS 24
217#define IRQ_UART0_TX_POS 28
218
219/* IAR3 BIT FIELDS */
220#define IRQ_UART1_RX_POS 0
221#define IRQ_UART1_TX_POS 4
222#define IRQ_OPTSEC_POS 8
223#define IRQ_CNT_POS 12
224#define IRQ_MAC_RX_POS 16
225#define IRQ_PORTH_INTA_POS 20
226#define IRQ_MAC_TX_POS 24
227#define IRQ_PORTH_INTB_POS 28
228
229/* IAR4 BIT FIELDS */
230#define IRQ_TMR0_POS 0
231#define IRQ_TMR1_POS 4
232#define IRQ_TMR2_POS 8
233#define IRQ_TMR3_POS 12
234#define IRQ_TMR4_POS 16
235#define IRQ_TMR5_POS 20
236#define IRQ_TMR6_POS 24
237#define IRQ_TMR7_POS 28
238
239/* IAR5 BIT FIELDS */
240#define IRQ_PORTG_INTA_POS 0
241#define IRQ_PORTG_INTB_POS 4
242#define IRQ_MEM_DMA0_POS 8
243#define IRQ_MEM_DMA1_POS 12
244#define IRQ_WATCH_POS 16
245#define IRQ_PORTF_INTA_POS 20
246#define IRQ_PORTF_INTB_POS 24
247#define IRQ_SPI_ERROR_POS 28
248
249/* IAR6 BIT FIELDS */
250#define IRQ_NFC_ERROR_POS 0
251#define IRQ_HDMA_ERROR_POS 4
252#define IRQ_HDMA_POS 8
253#define IRQ_USB_EINT_POS 12
254#define IRQ_USB_INT0_POS 16
255#define IRQ_USB_INT1_POS 20
256#define IRQ_USB_INT2_POS 24
257#define IRQ_USB_DMA_POS 28
258
259#endif /* _BF527_IRQ_H_ */
diff --git a/arch/blackfin/mach-bf527/include/mach/mem_init.h b/arch/blackfin/mach-bf527/include/mach/mem_init.h
new file mode 100644
index 000000000000..cbe03f4a5698
--- /dev/null
+++ b/arch/blackfin/mach-bf527/include/mach/mem_init.h
@@ -0,0 +1,310 @@
1/*
2 * File: include/asm-blackfin/mach-bf527/mem_init.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 * Copyright 2004-2007 Analog Devices Inc.
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || CONFIG_MEM_MT48LC16M8A2TG_75 || CONFIG_MEM_GENERIC_BOARD || CONFIG_MEM_MT48LC32M8A2_75 || CONFIG_MEM_MT48LC32M16A2TG_75)
33#if (CONFIG_SCLK_HZ > 119402985)
34#define SDRAM_tRP TRP_2
35#define SDRAM_tRP_num 2
36#define SDRAM_tRAS TRAS_7
37#define SDRAM_tRAS_num 7
38#define SDRAM_tRCD TRCD_2
39#define SDRAM_tWR TWR_2
40#endif
41#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
42#define SDRAM_tRP TRP_2
43#define SDRAM_tRP_num 2
44#define SDRAM_tRAS TRAS_6
45#define SDRAM_tRAS_num 6
46#define SDRAM_tRCD TRCD_2
47#define SDRAM_tWR TWR_2
48#endif
49#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
50#define SDRAM_tRP TRP_2
51#define SDRAM_tRP_num 2
52#define SDRAM_tRAS TRAS_5
53#define SDRAM_tRAS_num 5
54#define SDRAM_tRCD TRCD_2
55#define SDRAM_tWR TWR_2
56#endif
57#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
58#define SDRAM_tRP TRP_2
59#define SDRAM_tRP_num 2
60#define SDRAM_tRAS TRAS_4
61#define SDRAM_tRAS_num 4
62#define SDRAM_tRCD TRCD_2
63#define SDRAM_tWR TWR_2
64#endif
65#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
66#define SDRAM_tRP TRP_2
67#define SDRAM_tRP_num 2
68#define SDRAM_tRAS TRAS_3
69#define SDRAM_tRAS_num 3
70#define SDRAM_tRCD TRCD_2
71#define SDRAM_tWR TWR_2
72#endif
73#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
74#define SDRAM_tRP TRP_1
75#define SDRAM_tRP_num 1
76#define SDRAM_tRAS TRAS_4
77#define SDRAM_tRAS_num 3
78#define SDRAM_tRCD TRCD_1
79#define SDRAM_tWR TWR_2
80#endif
81#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
82#define SDRAM_tRP TRP_1
83#define SDRAM_tRP_num 1
84#define SDRAM_tRAS TRAS_3
85#define SDRAM_tRAS_num 3
86#define SDRAM_tRCD TRCD_1
87#define SDRAM_tWR TWR_2
88#endif
89#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
90#define SDRAM_tRP TRP_1
91#define SDRAM_tRP_num 1
92#define SDRAM_tRAS TRAS_2
93#define SDRAM_tRAS_num 2
94#define SDRAM_tRCD TRCD_1
95#define SDRAM_tWR TWR_2
96#endif
97#if (CONFIG_SCLK_HZ <= 29850746)
98#define SDRAM_tRP TRP_1
99#define SDRAM_tRP_num 1
100#define SDRAM_tRAS TRAS_1
101#define SDRAM_tRAS_num 1
102#define SDRAM_tRCD TRCD_1
103#define SDRAM_tWR TWR_2
104#endif
105#endif
106
107#if (CONFIG_MEM_MT48LC16M16A2TG_75)
108 /*SDRAM INFORMATION: */
109#define SDRAM_Tref 64 /* Refresh period in milliseconds */
110#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
111#define SDRAM_CL CL_3
112#endif
113
114#if (CONFIG_MEM_MT48LC16M8A2TG_75)
115 /*SDRAM INFORMATION: */
116#define SDRAM_Tref 64 /* Refresh period in milliseconds */
117#define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
118#define SDRAM_CL CL_3
119#endif
120
121#if (CONFIG_MEM_MT48LC32M8A2_75)
122 /*SDRAM INFORMATION: */
123#define SDRAM_Tref 64 /* Refresh period in milliseconds */
124#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
125#define SDRAM_CL CL_3
126#endif
127
128#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
129 /*SDRAM INFORMATION: */
130#define SDRAM_Tref 64 /* Refresh period in milliseconds */
131#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
132#define SDRAM_CL CL_3
133#endif
134
135#if (CONFIG_MEM_GENERIC_BOARD)
136 /*SDRAM INFORMATION: Modify this for your board */
137#define SDRAM_Tref 64 /* Refresh period in milliseconds */
138#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
139#define SDRAM_CL CL_3
140#endif
141
142#if (CONFIG_MEM_MT48LC32M16A2TG_75)
143 /*SDRAM INFORMATION: */
144#define SDRAM_Tref 64 /* Refresh period in milliseconds */
145#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
146#define SDRAM_CL CL_3
147#endif
148
149/* Equation from section 17 (p17-46) of BF533 HRM */
150#define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
151
152/* Enable SCLK Out */
153#define mem_SDGCTL (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
154
155#if defined CONFIG_CLKIN_HALF
156#define CLKIN_HALF 1
157#else
158#define CLKIN_HALF 0
159#endif
160
161#if defined CONFIG_PLL_BYPASS
162#define PLL_BYPASS 1
163#else
164#define PLL_BYPASS 0
165#endif
166
167/***************************************Currently Not Being Used *********************************/
168#define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
169#define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
170#define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ))
171#define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
172#define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
173
174#if (flash_EBIU_AMBCTL_TT > 3)
175#define flash_EBIU_AMBCTL0_TT B0TT_4
176#endif
177#if (flash_EBIU_AMBCTL_TT == 3)
178#define flash_EBIU_AMBCTL0_TT B0TT_3
179#endif
180#if (flash_EBIU_AMBCTL_TT == 2)
181#define flash_EBIU_AMBCTL0_TT B0TT_2
182#endif
183#if (flash_EBIU_AMBCTL_TT < 2)
184#define flash_EBIU_AMBCTL0_TT B0TT_1
185#endif
186
187#if (flash_EBIU_AMBCTL_ST > 3)
188#define flash_EBIU_AMBCTL0_ST B0ST_4
189#endif
190#if (flash_EBIU_AMBCTL_ST == 3)
191#define flash_EBIU_AMBCTL0_ST B0ST_3
192#endif
193#if (flash_EBIU_AMBCTL_ST == 2)
194#define flash_EBIU_AMBCTL0_ST B0ST_2
195#endif
196#if (flash_EBIU_AMBCTL_ST < 2)
197#define flash_EBIU_AMBCTL0_ST B0ST_1
198#endif
199
200#if (flash_EBIU_AMBCTL_HT > 2)
201#define flash_EBIU_AMBCTL0_HT B0HT_3
202#endif
203#if (flash_EBIU_AMBCTL_HT == 2)
204#define flash_EBIU_AMBCTL0_HT B0HT_2
205#endif
206#if (flash_EBIU_AMBCTL_HT == 1)
207#define flash_EBIU_AMBCTL0_HT B0HT_1
208#endif
209#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
210#define flash_EBIU_AMBCTL0_HT B0HT_0
211#endif
212#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
213#define flash_EBIU_AMBCTL0_HT B0HT_1
214#endif
215
216#if (flash_EBIU_AMBCTL_WAT > 14)
217#define flash_EBIU_AMBCTL0_WAT B0WAT_15
218#endif
219#if (flash_EBIU_AMBCTL_WAT == 14)
220#define flash_EBIU_AMBCTL0_WAT B0WAT_14
221#endif
222#if (flash_EBIU_AMBCTL_WAT == 13)
223#define flash_EBIU_AMBCTL0_WAT B0WAT_13
224#endif
225#if (flash_EBIU_AMBCTL_WAT == 12)
226#define flash_EBIU_AMBCTL0_WAT B0WAT_12
227#endif
228#if (flash_EBIU_AMBCTL_WAT == 11)
229#define flash_EBIU_AMBCTL0_WAT B0WAT_11
230#endif
231#if (flash_EBIU_AMBCTL_WAT == 10)
232#define flash_EBIU_AMBCTL0_WAT B0WAT_10
233#endif
234#if (flash_EBIU_AMBCTL_WAT == 9)
235#define flash_EBIU_AMBCTL0_WAT B0WAT_9
236#endif
237#if (flash_EBIU_AMBCTL_WAT == 8)
238#define flash_EBIU_AMBCTL0_WAT B0WAT_8
239#endif
240#if (flash_EBIU_AMBCTL_WAT == 7)
241#define flash_EBIU_AMBCTL0_WAT B0WAT_7
242#endif
243#if (flash_EBIU_AMBCTL_WAT == 6)
244#define flash_EBIU_AMBCTL0_WAT B0WAT_6
245#endif
246#if (flash_EBIU_AMBCTL_WAT == 5)
247#define flash_EBIU_AMBCTL0_WAT B0WAT_5
248#endif
249#if (flash_EBIU_AMBCTL_WAT == 4)
250#define flash_EBIU_AMBCTL0_WAT B0WAT_4
251#endif
252#if (flash_EBIU_AMBCTL_WAT == 3)
253#define flash_EBIU_AMBCTL0_WAT B0WAT_3
254#endif
255#if (flash_EBIU_AMBCTL_WAT == 2)
256#define flash_EBIU_AMBCTL0_WAT B0WAT_2
257#endif
258#if (flash_EBIU_AMBCTL_WAT == 1)
259#define flash_EBIU_AMBCTL0_WAT B0WAT_1
260#endif
261
262#if (flash_EBIU_AMBCTL_RAT > 14)
263#define flash_EBIU_AMBCTL0_RAT B0RAT_15
264#endif
265#if (flash_EBIU_AMBCTL_RAT == 14)
266#define flash_EBIU_AMBCTL0_RAT B0RAT_14
267#endif
268#if (flash_EBIU_AMBCTL_RAT == 13)
269#define flash_EBIU_AMBCTL0_RAT B0RAT_13
270#endif
271#if (flash_EBIU_AMBCTL_RAT == 12)
272#define flash_EBIU_AMBCTL0_RAT B0RAT_12
273#endif
274#if (flash_EBIU_AMBCTL_RAT == 11)
275#define flash_EBIU_AMBCTL0_RAT B0RAT_11
276#endif
277#if (flash_EBIU_AMBCTL_RAT == 10)
278#define flash_EBIU_AMBCTL0_RAT B0RAT_10
279#endif
280#if (flash_EBIU_AMBCTL_RAT == 9)
281#define flash_EBIU_AMBCTL0_RAT B0RAT_9
282#endif
283#if (flash_EBIU_AMBCTL_RAT == 8)
284#define flash_EBIU_AMBCTL0_RAT B0RAT_8
285#endif
286#if (flash_EBIU_AMBCTL_RAT == 7)
287#define flash_EBIU_AMBCTL0_RAT B0RAT_7
288#endif
289#if (flash_EBIU_AMBCTL_RAT == 6)
290#define flash_EBIU_AMBCTL0_RAT B0RAT_6
291#endif
292#if (flash_EBIU_AMBCTL_RAT == 5)
293#define flash_EBIU_AMBCTL0_RAT B0RAT_5
294#endif
295#if (flash_EBIU_AMBCTL_RAT == 4)
296#define flash_EBIU_AMBCTL0_RAT B0RAT_4
297#endif
298#if (flash_EBIU_AMBCTL_RAT == 3)
299#define flash_EBIU_AMBCTL0_RAT B0RAT_3
300#endif
301#if (flash_EBIU_AMBCTL_RAT == 2)
302#define flash_EBIU_AMBCTL0_RAT B0RAT_2
303#endif
304#if (flash_EBIU_AMBCTL_RAT == 1)
305#define flash_EBIU_AMBCTL0_RAT B0RAT_1
306#endif
307
308#define flash_EBIU_AMBCTL0 \
309 (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
310 flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
diff --git a/arch/blackfin/mach-bf527/include/mach/mem_map.h b/arch/blackfin/mach-bf527/include/mach/mem_map.h
new file mode 100644
index 000000000000..ef46dc991cd4
--- /dev/null
+++ b/arch/blackfin/mach-bf527/include/mach/mem_map.h
@@ -0,0 +1,102 @@
1/*
2 * file: include/asm-blackfin/mach-bf527/mem_map.h
3 * based on: include/asm-blackfin/mach-bf537/mem_map.h
4 * author: Michael Hennerich (michael.hennerich@analog.com)
5 *
6 * created:
7 * description:
8 * Memory MAP Common header file for blackfin BF527/5/2 of processors.
9 * rev:
10 *
11 * modified:
12 *
13 * bugs: enter bugs at http://blackfin.uclinux.org/
14 *
15 * this program is free software; you can redistribute it and/or modify
16 * it under the terms of the gnu general public license as published by
17 * the free software foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * this program is distributed in the hope that it will be useful,
21 * but without any warranty; without even the implied warranty of
22 * merchantability or fitness for a particular purpose. see the
23 * gnu general public license for more details.
24 *
25 * you should have received a copy of the gnu general public license
26 * along with this program; see the file copying.
27 * if not, write to the free software foundation,
28 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
29 */
30
31#ifndef _MEM_MAP_527_H_
32#define _MEM_MAP_527_H_
33
34#define COREMMR_BASE 0xFFE00000 /* Core MMRs */
35#define SYSMMR_BASE 0xFFC00000 /* System MMRs */
36
37/* Async Memory Banks */
38#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */
39#define ASYNC_BANK3_SIZE 0x00100000 /* 1M */
40#define ASYNC_BANK2_BASE 0x20200000 /* Async Bank 2 */
41#define ASYNC_BANK2_SIZE 0x00100000 /* 1M */
42#define ASYNC_BANK1_BASE 0x20100000 /* Async Bank 1 */
43#define ASYNC_BANK1_SIZE 0x00100000 /* 1M */
44#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
45#define ASYNC_BANK0_SIZE 0x00100000 /* 1M */
46
47/* Boot ROM Memory */
48
49#define BOOT_ROM_START 0xEF000000
50#define BOOT_ROM_LENGTH 0x8000
51
52/* Level 1 Memory */
53
54/* Memory Map for ADSP-BF527 ADSP-BF525 ADSP-BF522 processors */
55
56#ifdef CONFIG_BFIN_ICACHE
57#define BFIN_ICACHESIZE (16*1024)
58#else
59#define BFIN_ICACHESIZE (0*1024)
60#endif
61
62#define L1_CODE_START 0xFFA00000
63#define L1_DATA_A_START 0xFF800000
64#define L1_DATA_B_START 0xFF900000
65
66#define L1_CODE_LENGTH 0xC000
67
68#ifdef CONFIG_BFIN_DCACHE
69
70#ifdef CONFIG_BFIN_DCACHE_BANKA
71#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
72#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
73#define L1_DATA_B_LENGTH 0x8000
74#define BFIN_DCACHESIZE (16*1024)
75#define BFIN_DSUPBANKS 1
76#else
77#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
78#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
79#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
80#define BFIN_DCACHESIZE (32*1024)
81#define BFIN_DSUPBANKS 2
82#endif
83
84#else
85#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
86#define L1_DATA_A_LENGTH 0x8000
87#define L1_DATA_B_LENGTH 0x8000
88#define BFIN_DCACHESIZE (0*1024)
89#define BFIN_DSUPBANKS 0
90#endif /*CONFIG_BFIN_DCACHE */
91
92/* Level 2 Memory - none */
93
94#define L2_START 0
95#define L2_LENGTH 0
96
97/* Scratch Pad Memory */
98
99#define L1_SCRATCH_START 0xFFB00000
100#define L1_SCRATCH_LENGTH 0x1000
101
102#endif /* _MEM_MAP_527_H_ */
diff --git a/arch/blackfin/mach-bf527/include/mach/portmux.h b/arch/blackfin/mach-bf527/include/mach/portmux.h
new file mode 100644
index 000000000000..ae4d205bfcf5
--- /dev/null
+++ b/arch/blackfin/mach-bf527/include/mach/portmux.h
@@ -0,0 +1,207 @@
1#ifndef _MACH_PORTMUX_H_
2#define _MACH_PORTMUX_H_
3
4#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
5
6#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
7#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
8#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
9#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
10#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
11#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
12#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
13#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
14#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
15#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
16#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
17#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
18#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
19#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
20#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
21#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
22
23#if defined(CONFIG_BF527_SPORT0_PORTF)
24#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
25#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
26#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
27#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
28#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
29#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
30#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
31#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
32#elif defined(CONFIG_BF527_SPORT0_PORTG)
33#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
34#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
35#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
36#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
37#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
38#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
39#if defined(CONFIG_BF527_SPORT0_TSCLK_PG10)
40#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
41#elif defined(CONFIG_BF527_SPORT0_TSCLK_PG14)
42#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
43#endif
44#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
45#endif
46
47#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
48#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
49#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
50#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
51#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
52#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
53#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
54#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
55
56#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2))
57#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2))
58
59#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2))
60#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2))
61
62#if defined(CONFIG_BF527_UART1_PORTF)
63#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2))
64#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2))
65#elif defined(CONFIG_BF527_UART1_PORTG)
66#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
67#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
68#endif
69
70#define P_HWAIT (P_DONTCARE)
71
72#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
73#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
74#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2))
75#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2))
76#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2))
77#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
78#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
79#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
80#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
81#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
82#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
83/* #define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0)) */
84#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
85#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
86#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
87#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
88#define P_MDC (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
89#define P_RMII0_MDINT (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
90#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
91
92#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
93#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
94#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(2))
95
96#define P_HOST_WR (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(2))
97#define P_HOST_ACK (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2))
98#define P_HOST_ADDR (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2))
99#define P_HOST_RD (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2))
100#define P_HOST_CE (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2))
101
102#if defined(CONFIG_BF527_NAND_D_PORTF)
103#define P_NAND_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(2))
104#define P_NAND_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2))
105#define P_NAND_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2))
106#define P_NAND_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2))
107#define P_NAND_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2))
108#define P_NAND_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2))
109#define P_NAND_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2))
110#define P_NAND_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2))
111#elif defined(CONFIG_BF527_NAND_D_PORTH)
112#define P_NAND_D0 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
113#define P_NAND_D1 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
114#define P_NAND_D2 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
115#define P_NAND_D3 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
116#define P_NAND_D4 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
117#define P_NAND_D5 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
118#define P_NAND_D6 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
119#define P_NAND_D7 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
120#endif
121
122#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0))
123#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0))
124#define P_NAND_CE (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0))
125#define P_NAND_WE (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0))
126#define P_NAND_RE (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0))
127#define P_NAND_RB (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0))
128#define P_NAND_CLE (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(0))
129#define P_NAND_ALE (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(0))
130
131#define P_HOST_D0 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(2))
132#define P_HOST_D1 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(2))
133#define P_HOST_D2 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2))
134#define P_HOST_D3 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2))
135#define P_HOST_D4 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2))
136#define P_HOST_D5 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(2))
137#define P_HOST_D6 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(2))
138#define P_HOST_D7 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(2))
139#define P_HOST_D8 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(2))
140#define P_HOST_D9 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(2))
141#define P_HOST_D10 (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(2))
142#define P_HOST_D11 (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(2))
143#define P_HOST_D12 (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(2))
144#define P_HOST_D13 (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(2))
145#define P_HOST_D14 (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(2))
146#define P_HOST_D15 (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(2))
147
148#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1))
149#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(1))
150#define P_MII0_ETxD2 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(1))
151#define P_MII0_ETxD3 (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(1))
152#define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1))
153#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1))
154#define P_MII0_COL (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(1))
155#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
156#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(1))
157#define P_MII0_ERxD2 (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(1))
158#define P_MII0_ERxD3 (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(1))
159#define P_MII0_ERxDV (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(1))
160#define P_MII0_ERxCLK (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(1))
161#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1))
162#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
163#define P_RMII0_REF_CLK (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1))
164#define P_RMII0_CRS_DV (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
165#define P_MDIO (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1))
166
167#define P_TWI0_SCL (P_DONTCARE)
168#define P_TWI0_SDA (P_DONTCARE)
169#define P_PPI0_FS1 (P_DONTCARE)
170#define P_TMR0 (P_DONTCARE)
171#define P_TMRCLK (P_DONTCARE)
172#define P_PPI0_CLK (P_DONTCARE)
173
174#define P_MII0 {\
175 P_MII0_ETxD0, \
176 P_MII0_ETxD1, \
177 P_MII0_ETxD2, \
178 P_MII0_ETxD3, \
179 P_MII0_ETxEN, \
180 P_MII0_TxCLK, \
181 P_MII0_PHYINT, \
182 P_MII0_COL, \
183 P_MII0_ERxD0, \
184 P_MII0_ERxD1, \
185 P_MII0_ERxD2, \
186 P_MII0_ERxD3, \
187 P_MII0_ERxDV, \
188 P_MII0_ERxCLK, \
189 P_MII0_ERxER, \
190 P_MII0_CRS, \
191 P_MDC, \
192 P_MDIO, 0}
193
194#define P_RMII0 {\
195 P_MII0_ETxD0, \
196 P_MII0_ETxD1, \
197 P_MII0_ETxEN, \
198 P_MII0_ERxD0, \
199 P_MII0_ERxD1, \
200 P_MII0_ERxER, \
201 P_RMII0_REF_CLK, \
202 P_RMII0_MDINT, \
203 P_RMII0_CRS_DV, \
204 P_MDC, \
205 P_MDIO, 0}
206
207#endif /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/mach-bf533/head.S b/arch/blackfin/mach-bf533/head.S
index d59db86195b6..01b2b7ead5ab 100644
--- a/arch/blackfin/mach-bf533/head.S
+++ b/arch/blackfin/mach-bf533/head.S
@@ -31,8 +31,8 @@
31#include <linux/init.h> 31#include <linux/init.h>
32#include <asm/blackfin.h> 32#include <asm/blackfin.h>
33#ifdef CONFIG_BFIN_KERNEL_CLOCK 33#ifdef CONFIG_BFIN_KERNEL_CLOCK
34#include <asm/mach-common/clocks.h> 34#include <asm/clocks.h>
35#include <asm/mach/mem_init.h> 35#include <mach/mem_init.h>
36#endif 36#endif
37 37
38.section .l1.text 38.section .l1.text
diff --git a/arch/blackfin/mach-bf533/include/mach/anomaly.h b/arch/blackfin/mach-bf533/include/mach/anomaly.h
new file mode 100644
index 000000000000..8f7ea112fd3a
--- /dev/null
+++ b/arch/blackfin/mach-bf533/include/mach/anomaly.h
@@ -0,0 +1,272 @@
1/*
2 * File: include/asm-blackfin/mach-bf533/anomaly.h
3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
4 *
5 * Copyright (C) 2004-2008 Analog Devices Inc.
6 * Licensed under the GPL-2 or later.
7 */
8
9/* This file shoule be up to date with:
10 * - Revision C, 02/08/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
11 */
12
13#ifndef _MACH_ANOMALY_H_
14#define _MACH_ANOMALY_H_
15
16/* We do not support 0.1 or 0.2 silicon - sorry */
17#if __SILICON_REVISION__ < 3
18# error will not work on BF533 silicon version 0.0, 0.1, or 0.2
19#endif
20
21#if defined(__ADSPBF531__)
22# define ANOMALY_BF531 1
23#else
24# define ANOMALY_BF531 0
25#endif
26#if defined(__ADSPBF532__)
27# define ANOMALY_BF532 1
28#else
29# define ANOMALY_BF532 0
30#endif
31#if defined(__ADSPBF533__)
32# define ANOMALY_BF533 1
33#else
34# define ANOMALY_BF533 0
35#endif
36
37/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */
38#define ANOMALY_05000074 (1)
39/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */
40#define ANOMALY_05000099 (__SILICON_REVISION__ < 5)
41/* Watchpoint Status Register (WPSTAT) Bits Are Set on Every Corresponding Match */
42#define ANOMALY_05000105 (1)
43/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
44#define ANOMALY_05000119 (1)
45/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
46#define ANOMALY_05000122 (1)
47/* Instruction DMA Can Cause Data Cache Fills to Fail (Boot Implications) */
48#define ANOMALY_05000158 (__SILICON_REVISION__ < 5)
49/* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */
50#define ANOMALY_05000166 (1)
51/* Turning Serial Ports on with External Frame Syncs */
52#define ANOMALY_05000167 (1)
53/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
54#define ANOMALY_05000179 (__SILICON_REVISION__ < 5)
55/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
56#define ANOMALY_05000180 (1)
57/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */
58#define ANOMALY_05000183 (__SILICON_REVISION__ < 4)
59/* False Protection Exceptions */
60#define ANOMALY_05000189 (__SILICON_REVISION__ < 4)
61/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
62#define ANOMALY_05000193 (__SILICON_REVISION__ < 4)
63/* Restarting SPORT in Specific Modes May Cause Data Corruption */
64#define ANOMALY_05000194 (__SILICON_REVISION__ < 4)
65/* Failing MMR Accesses When Stalled by Preceding Memory Read */
66#define ANOMALY_05000198 (__SILICON_REVISION__ < 5)
67/* Current DMA Address Shows Wrong Value During Carry Fix */
68#define ANOMALY_05000199 (__SILICON_REVISION__ < 4)
69/* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */
70#define ANOMALY_05000200 (__SILICON_REVISION__ < 5)
71/* Receive Frame Sync Not Ignored During Active Frames in SPORT Multi-Channel Mode */
72#define ANOMALY_05000201 (__SILICON_REVISION__ < 4)
73/* Possible Infinite Stall with Specific Dual-DAG Situation */
74#define ANOMALY_05000202 (__SILICON_REVISION__ < 5)
75/* Specific Sequence That Can Cause DMA Error or DMA Stopping */
76#define ANOMALY_05000203 (__SILICON_REVISION__ < 4)
77/* Incorrect data read with write-through cache and allocate cache lines on reads only mode */
78#define ANOMALY_05000204 (__SILICON_REVISION__ < 4 && ANOMALY_BF533)
79/* Recovery from "Brown-Out" Condition */
80#define ANOMALY_05000207 (__SILICON_REVISION__ < 4)
81/* VSTAT Status Bit in PLL_STAT Register Is Not Functional */
82#define ANOMALY_05000208 (1)
83/* Speed Path in Computational Unit Affects Certain Instructions */
84#define ANOMALY_05000209 (__SILICON_REVISION__ < 4)
85/* UART TX Interrupt Masked Erroneously */
86#define ANOMALY_05000215 (__SILICON_REVISION__ < 5)
87/* NMI Event at Boot Time Results in Unpredictable State */
88#define ANOMALY_05000219 (1)
89/* Incorrect Pulse-Width of UART Start Bit */
90#define ANOMALY_05000225 (__SILICON_REVISION__ < 5)
91/* Scratchpad Memory Bank Reads May Return Incorrect Data */
92#define ANOMALY_05000227 (__SILICON_REVISION__ < 5)
93/* SPI Slave Boot Mode Modifies Registers from Reset Value */
94#define ANOMALY_05000229 (1)
95/* UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions */
96#define ANOMALY_05000230 (__SILICON_REVISION__ < 5)
97/* UART STB Bit Incorrectly Affects Receiver Setting */
98#define ANOMALY_05000231 (__SILICON_REVISION__ < 5)
99/* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */
100#define ANOMALY_05000233 (__SILICON_REVISION__ < 4)
101/* Incorrect Revision Number in DSPID Register */
102#define ANOMALY_05000234 (__SILICON_REVISION__ == 4)
103/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */
104#define ANOMALY_05000242 (__SILICON_REVISION__ < 4)
105/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
106#define ANOMALY_05000244 (__SILICON_REVISION__ < 5)
107/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
108#define ANOMALY_05000245 (1)
109/* Data CPLBs Should Prevent Spurious Hardware Errors */
110#define ANOMALY_05000246 (__SILICON_REVISION__ < 5)
111/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
112#define ANOMALY_05000250 (__SILICON_REVISION__ == 4)
113/* Maximum External Clock Speed for Timers */
114#define ANOMALY_05000253 (__SILICON_REVISION__ < 5)
115/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
116#define ANOMALY_05000254 (__SILICON_REVISION__ > 4)
117/* Entering Hibernate State with RTC Seconds Interrupt Not Functional */
118#define ANOMALY_05000255 (__SILICON_REVISION__ < 5)
119/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
120#define ANOMALY_05000257 (__SILICON_REVISION__ < 5)
121/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
122#define ANOMALY_05000258 (__SILICON_REVISION__ < 5)
123/* ICPLB_STATUS MMR Register May Be Corrupted */
124#define ANOMALY_05000260 (__SILICON_REVISION__ < 5)
125/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
126#define ANOMALY_05000261 (__SILICON_REVISION__ < 5)
127/* Stores To Data Cache May Be Lost */
128#define ANOMALY_05000262 (__SILICON_REVISION__ < 5)
129/* Hardware Loop Corrupted When Taking an ICPLB Exception */
130#define ANOMALY_05000263 (__SILICON_REVISION__ < 5)
131/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
132#define ANOMALY_05000264 (__SILICON_REVISION__ < 5)
133/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
134#define ANOMALY_05000265 (__SILICON_REVISION__ < 5)
135/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */
136#define ANOMALY_05000269 (__SILICON_REVISION__ < 5)
137/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
138#define ANOMALY_05000270 (__SILICON_REVISION__ < 5)
139/* Spontaneous Reset of Internal Voltage Regulator */
140#define ANOMALY_05000271 (__SILICON_REVISION__ < 4)
141/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
142#define ANOMALY_05000272 (1)
143/* Writes to Synchronous SDRAM Memory May Be Lost */
144#define ANOMALY_05000273 (1)
145/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
146#define ANOMALY_05000276 (1)
147/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
148#define ANOMALY_05000277 (1)
149/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
150#define ANOMALY_05000278 (1)
151/* False Hardware Error Exception When ISR Context Is Not Restored */
152#define ANOMALY_05000281 (1)
153/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
154#define ANOMALY_05000282 (1)
155/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */
156#define ANOMALY_05000283 (1)
157/* SPORTs May Receive Bad Data If FIFOs Fill Up */
158#define ANOMALY_05000288 (1)
159/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
160#define ANOMALY_05000301 (1)
161/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */
162#define ANOMALY_05000302 (__SILICON_REVISION__ < 5)
163/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */
164#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
165/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available On Older Silicon) */
166#define ANOMALY_05000306 (__SILICON_REVISION__ < 5)
167/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
168#define ANOMALY_05000310 (1)
169/* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */
170#define ANOMALY_05000311 (1)
171/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
172#define ANOMALY_05000312 (1)
173/* PPI Is Level-Sensitive on First Transfer */
174#define ANOMALY_05000313 (1)
175/* Killed System MMR Write Completes Erroneously On Next System MMR Access */
176#define ANOMALY_05000315 (1)
177/* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */
178#define ANOMALY_05000319 (ANOMALY_BF531 || ANOMALY_BF532)
179/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
180#define ANOMALY_05000357 (1)
181/* UART Break Signal Issues */
182#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
183/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
184#define ANOMALY_05000366 (1)
185/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
186#define ANOMALY_05000371 (1)
187/* PPI Does Not Start Properly In Specific Mode */
188#define ANOMALY_05000400 (__SILICON_REVISION__ >= 5)
189/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
190#define ANOMALY_05000402 (__SILICON_REVISION__ >= 5)
191/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
192#define ANOMALY_05000403 (1)
193
194
195/* These anomalies have been "phased" out of analog.com anomaly sheets and are
196 * here to show running on older silicon just isn't feasible.
197 */
198
199/* Watchpoints (Hardware Breakpoints) are not supported */
200#define ANOMALY_05000067 (__SILICON_REVISION__ < 3)
201/* Reserved bits in SYSCFG register not set at power on */
202#define ANOMALY_05000109 (__SILICON_REVISION__ < 3)
203/* Trace Buffers may record discontinuities into emulation mode and/or exception, NMI, reset handlers */
204#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
205/* DTEST_COMMAND initiated memory access may be incorrect if data cache or DMA is active */
206#define ANOMALY_05000123 (__SILICON_REVISION__ < 3)
207/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
208#define ANOMALY_05000124 (__SILICON_REVISION__ < 3)
209/* Erroneous exception when enabling cache */
210#define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
211/* SPI clock polarity and phase bits incorrect during booting */
212#define ANOMALY_05000126 (__SILICON_REVISION__ < 3)
213/* DMEM_CONTROL is not set on Reset */
214#define ANOMALY_05000137 (__SILICON_REVISION__ < 3)
215/* SPI boot will not complete if there is a zero fill block in the loader file */
216#define ANOMALY_05000138 (__SILICON_REVISION__ < 3)
217/* Allowing the SPORT RX FIFO to fill will cause an overflow */
218#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
219/* An Infinite Stall occurs with a particular sequence of consecutive dual dag events */
220#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
221/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
222#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
223/* A read from external memory may return a wrong value with data cache enabled */
224#define ANOMALY_05000143 (__SILICON_REVISION__ < 3)
225/* DMA and TESTSET conflict when both are accessing external memory */
226#define ANOMALY_05000144 (__SILICON_REVISION__ < 3)
227/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */
228#define ANOMALY_05000145 (__SILICON_REVISION__ < 3)
229/* MDMA may lose the first few words of a descriptor chain */
230#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
231/* The source MDMA descriptor may stop with a DMA Error */
232#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
233/* When booting from a 16-bit asynchronous memory device, the upper 8-bits of each word must be 0x00 */
234#define ANOMALY_05000148 (__SILICON_REVISION__ < 3)
235/* Frame Delay in SPORT Multichannel Mode */
236#define ANOMALY_05000153 (__SILICON_REVISION__ < 3)
237/* SPORT TFS signal is active in Multi-channel mode outside of valid channels */
238#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
239/* Timer1 can not be used for PWMOUT mode when a certain PPI mode is in use */
240#define ANOMALY_05000155 (__SILICON_REVISION__ < 3)
241/* A killed 32-bit System MMR write will lead to the next system MMR access thinking it should be 32-bit. */
242#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
243/* SPORT transmit data is not gated by external frame sync in certain conditions */
244#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
245/* SDRAM auto-refresh and subsequent Power Ups */
246#define ANOMALY_05000168 (__SILICON_REVISION__ < 3)
247/* DATA CPLB page miss can result in lost write-through cache data writes */
248#define ANOMALY_05000169 (__SILICON_REVISION__ < 3)
249/* DMA vs Core accesses to external memory */
250#define ANOMALY_05000173 (__SILICON_REVISION__ < 3)
251/* Cache Fill Buffer Data lost */
252#define ANOMALY_05000174 (__SILICON_REVISION__ < 3)
253/* Overlapping Sequencer and Memory Stalls */
254#define ANOMALY_05000175 (__SILICON_REVISION__ < 3)
255/* Multiplication of (-1) by (-1) followed by an accumulator saturation */
256#define ANOMALY_05000176 (__SILICON_REVISION__ < 3)
257/* Disabling the PPI resets the PPI configuration registers */
258#define ANOMALY_05000181 (__SILICON_REVISION__ < 3)
259/* PPI TX Mode with 2 External Frame Syncs */
260#define ANOMALY_05000185 (__SILICON_REVISION__ < 3)
261/* PPI does not invert the Driving PPICLK edge in Transmit Modes */
262#define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
263/* In PPI Transmit Modes with External Frame Syncs POLC */
264#define ANOMALY_05000192 (__SILICON_REVISION__ < 3)
265/* Internal Voltage Regulator may not start up */
266#define ANOMALY_05000206 (__SILICON_REVISION__ < 3)
267
268/* Anomalies that don't exist on this proc */
269#define ANOMALY_05000266 (0)
270#define ANOMALY_05000323 (0)
271
272#endif
diff --git a/arch/blackfin/mach-bf533/include/mach/bf533.h b/arch/blackfin/mach-bf533/include/mach/bf533.h
new file mode 100644
index 000000000000..12a416931991
--- /dev/null
+++ b/arch/blackfin/mach-bf533/include/mach/bf533.h
@@ -0,0 +1,161 @@
1/*
2 * File: include/asm-blackfin/mach-bf533/bf533.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#ifndef __MACH_BF533_H__
31#define __MACH_BF533_H__
32
33#define SUPPORTED_REVID 2
34
35#define OFFSET_(x) ((x) & 0x0000FFFF)
36
37/*some misc defines*/
38#define IMASK_IVG15 0x8000
39#define IMASK_IVG14 0x4000
40#define IMASK_IVG13 0x2000
41#define IMASK_IVG12 0x1000
42
43#define IMASK_IVG11 0x0800
44#define IMASK_IVG10 0x0400
45#define IMASK_IVG9 0x0200
46#define IMASK_IVG8 0x0100
47
48#define IMASK_IVG7 0x0080
49#define IMASK_IVGTMR 0x0040
50#define IMASK_IVGHW 0x0020
51
52/***************************/
53
54
55#define BFIN_DSUBBANKS 4
56#define BFIN_DWAYS 2
57#define BFIN_DLINES 64
58#define BFIN_ISUBBANKS 4
59#define BFIN_IWAYS 4
60#define BFIN_ILINES 32
61
62#define WAY0_L 0x1
63#define WAY1_L 0x2
64#define WAY01_L 0x3
65#define WAY2_L 0x4
66#define WAY02_L 0x5
67#define WAY12_L 0x6
68#define WAY012_L 0x7
69
70#define WAY3_L 0x8
71#define WAY03_L 0x9
72#define WAY13_L 0xA
73#define WAY013_L 0xB
74
75#define WAY32_L 0xC
76#define WAY320_L 0xD
77#define WAY321_L 0xE
78#define WAYALL_L 0xF
79
80#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
81
82/* IAR0 BIT FIELDS*/
83#define RTC_ERROR_BIT 0x0FFFFFFF
84#define UART_ERROR_BIT 0xF0FFFFFF
85#define SPORT1_ERROR_BIT 0xFF0FFFFF
86#define SPI_ERROR_BIT 0xFFF0FFFF
87#define SPORT0_ERROR_BIT 0xFFFF0FFF
88#define PPI_ERROR_BIT 0xFFFFF0FF
89#define DMA_ERROR_BIT 0xFFFFFF0F
90#define PLLWAKE_ERROR_BIT 0xFFFFFFFF
91
92/* IAR1 BIT FIELDS*/
93#define DMA7_UARTTX_BIT 0x0FFFFFFF
94#define DMA6_UARTRX_BIT 0xF0FFFFFF
95#define DMA5_SPI_BIT 0xFF0FFFFF
96#define DMA4_SPORT1TX_BIT 0xFFF0FFFF
97#define DMA3_SPORT1RX_BIT 0xFFFF0FFF
98#define DMA2_SPORT0TX_BIT 0xFFFFF0FF
99#define DMA1_SPORT0RX_BIT 0xFFFFFF0F
100#define DMA0_PPI_BIT 0xFFFFFFFF
101
102/* IAR2 BIT FIELDS*/
103#define WDTIMER_BIT 0x0FFFFFFF
104#define MEMDMA1_BIT 0xF0FFFFFF
105#define MEMDMA0_BIT 0xFF0FFFFF
106#define PFB_BIT 0xFFF0FFFF
107#define PFA_BIT 0xFFFF0FFF
108#define TIMER2_BIT 0xFFFFF0FF
109#define TIMER1_BIT 0xFFFFFF0F
110#define TIMER0_BIT 0xFFFFFFFF
111
112/********************************* EBIU Settings ************************************/
113#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
114#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
115
116#ifdef CONFIG_C_AMBEN_ALL
117#define V_AMBEN AMBEN_ALL
118#endif
119#ifdef CONFIG_C_AMBEN
120#define V_AMBEN 0x0
121#endif
122#ifdef CONFIG_C_AMBEN_B0
123#define V_AMBEN AMBEN_B0
124#endif
125#ifdef CONFIG_C_AMBEN_B0_B1
126#define V_AMBEN AMBEN_B0_B1
127#endif
128#ifdef CONFIG_C_AMBEN_B0_B1_B2
129#define V_AMBEN AMBEN_B0_B1_B2
130#endif
131#ifdef CONFIG_C_AMCKEN
132#define V_AMCKEN AMCKEN
133#else
134#define V_AMCKEN 0x0
135#endif
136#ifdef CONFIG_C_CDPRIO
137#define V_CDPRIO 0x100
138#else
139#define V_CDPRIO 0x0
140#endif
141
142#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
143
144#ifdef CONFIG_BF533
145#define CPU "BF533"
146#define CPUID 0x027a5000
147#endif
148#ifdef CONFIG_BF532
149#define CPU "BF532"
150#define CPUID 0x0275A000
151#endif
152#ifdef CONFIG_BF531
153#define CPU "BF531"
154#define CPUID 0x027a5000
155#endif
156#ifndef CPU
157#define CPU "UNKNOWN"
158#define CPUID 0x0
159#endif
160
161#endif /* __MACH_BF533_H__ */
diff --git a/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h
new file mode 100644
index 000000000000..ebf592b59aab
--- /dev/null
+++ b/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h
@@ -0,0 +1,164 @@
1/*
2 * file: include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
3 * based on:
4 * author:
5 *
6 * created:
7 * description:
8 * blackfin serial driver head file
9 * rev:
10 *
11 * modified:
12 *
13 *
14 * bugs: enter bugs at http://blackfin.uclinux.org/
15 *
16 * this program is free software; you can redistribute it and/or modify
17 * it under the terms of the gnu general public license as published by
18 * the free software foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * this program is distributed in the hope that it will be useful,
22 * but without any warranty; without even the implied warranty of
23 * merchantability or fitness for a particular purpose. see the
24 * gnu general public license for more details.
25 *
26 * you should have received a copy of the gnu general public license
27 * along with this program; see the file copying.
28 * if not, write to the free software foundation,
29 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
30 */
31
32#include <linux/serial.h>
33#include <asm/dma.h>
34#include <asm/portmux.h>
35
36#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
37#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
38#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
39#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
40#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
41#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
42#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
43
44#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
45#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
46#define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v)
47#define UART_SET_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
48#define UART_CLEAR_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
49#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
50#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
51#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
52
53#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
54#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
55
56#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
57#define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1)
58#define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0)
59#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
60#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
61
62#ifdef CONFIG_BFIN_UART0_CTSRTS
63# define CONFIG_SERIAL_BFIN_CTSRTS
64# ifndef CONFIG_UART0_CTS_PIN
65# define CONFIG_UART0_CTS_PIN -1
66# endif
67# ifndef CONFIG_UART0_RTS_PIN
68# define CONFIG_UART0_RTS_PIN -1
69# endif
70#endif
71
72struct bfin_serial_port {
73 struct uart_port port;
74 unsigned int old_status;
75 unsigned int lsr;
76#ifdef CONFIG_SERIAL_BFIN_DMA
77 int tx_done;
78 int tx_count;
79 struct circ_buf rx_dma_buf;
80 struct timer_list rx_dma_timer;
81 int rx_dma_nrows;
82 unsigned int tx_dma_channel;
83 unsigned int rx_dma_channel;
84 struct work_struct tx_dma_workqueue;
85#else
86# if ANOMALY_05000230
87 unsigned int anomaly_threshold;
88# endif
89#endif
90#ifdef CONFIG_SERIAL_BFIN_CTSRTS
91 struct timer_list cts_timer;
92 int cts_pin;
93 int rts_pin;
94#endif
95};
96
97/* The hardware clears the LSR bits upon read, so we need to cache
98 * some of the more fun bits in software so they don't get lost
99 * when checking the LSR in other code paths (TX).
100 */
101static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
102{
103 unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
104 uart->lsr |= (lsr & (BI|FE|PE|OE));
105 return lsr | uart->lsr;
106}
107
108static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
109{
110 uart->lsr = 0;
111 bfin_write16(uart->port.membase + OFFSET_LSR, -1);
112}
113
114struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
115struct bfin_serial_res {
116 unsigned long uart_base_addr;
117 int uart_irq;
118#ifdef CONFIG_SERIAL_BFIN_DMA
119 unsigned int uart_tx_dma_channel;
120 unsigned int uart_rx_dma_channel;
121#endif
122#ifdef CONFIG_SERIAL_BFIN_CTSRTS
123 int uart_cts_pin;
124 int uart_rts_pin;
125#endif
126};
127
128struct bfin_serial_res bfin_serial_resource[] = {
129 {
130 0xFFC00400,
131 IRQ_UART_RX,
132#ifdef CONFIG_SERIAL_BFIN_DMA
133 CH_UART_TX,
134 CH_UART_RX,
135#endif
136#ifdef CONFIG_BFIN_UART0_CTSRTS
137 CONFIG_UART0_CTS_PIN,
138 CONFIG_UART0_RTS_PIN,
139#endif
140 }
141};
142
143#define DRIVER_NAME "bfin-uart"
144
145int nr_ports = BFIN_UART_NR_PORTS;
146static void bfin_serial_hw_init(struct bfin_serial_port *uart)
147{
148
149#ifdef CONFIG_SERIAL_BFIN_UART0
150 peripheral_request(P_UART0_TX, DRIVER_NAME);
151 peripheral_request(P_UART0_RX, DRIVER_NAME);
152#endif
153
154#ifdef CONFIG_SERIAL_BFIN_CTSRTS
155 if (uart->cts_pin >= 0) {
156 gpio_request(uart->cts_pin, DRIVER_NAME);
157 gpio_direction_input(uart->cts_pin);
158 }
159 if (uart->rts_pin >= 0) {
160 gpio_request(uart->rts_pin, DRIVER_NAME);
161 gpio_direction_input(uart->rts_pin, 0);
162 }
163#endif
164}
diff --git a/arch/blackfin/mach-bf533/include/mach/bfin_sir.h b/arch/blackfin/mach-bf533/include/mach/bfin_sir.h
new file mode 100644
index 000000000000..9bb87e9e2e9b
--- /dev/null
+++ b/arch/blackfin/mach-bf533/include/mach/bfin_sir.h
@@ -0,0 +1,125 @@
1/*
2 * Blackfin Infra-red Driver
3 *
4 * Copyright 2006-2008 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 *
10 */
11
12#include <linux/serial.h>
13#include <asm/dma.h>
14#include <asm/portmux.h>
15
16#define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR)
17#define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL)
18#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER)
19#define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH)
20#define SIR_UART_GET_IIR(port) bfin_read16((port)->membase + OFFSET_IIR)
21#define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR)
22#define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL)
23
24#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
25#define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v)
26#define SIR_UART_PUT_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER), v)
27#define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v)
28#define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v)
29#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
30
31#ifdef CONFIG_SIR_BFIN_DMA
32struct dma_rx_buf {
33 char *buf;
34 int head;
35 int tail;
36 };
37#endif /* CONFIG_SIR_BFIN_DMA */
38
39struct bfin_sir_port {
40 unsigned char __iomem *membase;
41 unsigned int irq;
42 unsigned int lsr;
43 unsigned long clk;
44 struct net_device *dev;
45#ifdef CONFIG_SIR_BFIN_DMA
46 int tx_done;
47 struct dma_rx_buf rx_dma_buf;
48 struct timer_list rx_dma_timer;
49 int rx_dma_nrows;
50#endif /* CONFIG_SIR_BFIN_DMA */
51 unsigned int tx_dma_channel;
52 unsigned int rx_dma_channel;
53};
54
55struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS];
56
57struct bfin_sir_port_res {
58 unsigned long base_addr;
59 int irq;
60 unsigned int rx_dma_channel;
61 unsigned int tx_dma_channel;
62};
63
64struct bfin_sir_port_res bfin_sir_port_resource[] = {
65#ifdef CONFIG_BFIN_SIR0
66 {
67 0xFFC00400,
68 IRQ_UART_RX,
69 CH_UART_RX,
70 CH_UART_TX,
71 },
72#endif
73};
74
75int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource);
76
77struct bfin_sir_self {
78 struct bfin_sir_port *sir_port;
79 spinlock_t lock;
80 unsigned int open;
81 int speed;
82 int newspeed;
83
84 struct sk_buff *txskb;
85 struct sk_buff *rxskb;
86 struct net_device_stats stats;
87 struct device *dev;
88 struct irlap_cb *irlap;
89 struct qos_info qos;
90
91 iobuff_t tx_buff;
92 iobuff_t rx_buff;
93
94 struct work_struct work;
95 int mtt;
96};
97
98static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port)
99{
100 unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR);
101 port->lsr |= (lsr & (BI|FE|PE|OE));
102 return lsr | port->lsr;
103}
104
105static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port)
106{
107 port->lsr = 0;
108 bfin_read16(port->membase + OFFSET_LSR);
109}
110
111#define DRIVER_NAME "bfin_sir"
112
113static int bfin_sir_hw_init(void)
114{
115 int ret = -ENODEV;
116#ifdef CONFIG_BFIN_SIR0
117 ret = peripheral_request(P_UART0_TX, DRIVER_NAME);
118 if (ret)
119 return ret;
120 ret = peripheral_request(P_UART0_RX, DRIVER_NAME);
121 if (ret)
122 return ret;
123#endif
124 return ret;
125}
diff --git a/arch/blackfin/mach-bf533/include/mach/blackfin.h b/arch/blackfin/mach-bf533/include/mach/blackfin.h
new file mode 100644
index 000000000000..d80971b4e3aa
--- /dev/null
+++ b/arch/blackfin/mach-bf533/include/mach/blackfin.h
@@ -0,0 +1,60 @@
1/*
2 * File: include/asm-blackfin/mach-bf533/blackfin.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _MACH_BLACKFIN_H_
32#define _MACH_BLACKFIN_H_
33
34#define BF533_FAMILY
35
36#include "bf533.h"
37#include "mem_map.h"
38#include "defBF532.h"
39#include "anomaly.h"
40
41#if !defined(__ASSEMBLY__)
42#include "cdefBF532.h"
43#endif
44
45#define BFIN_UART_NR_PORTS 1
46
47#define OFFSET_THR 0x00 /* Transmit Holding register */
48#define OFFSET_RBR 0x00 /* Receive Buffer register */
49#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
50#define OFFSET_IER 0x04 /* Interrupt Enable Register */
51#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
52#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
53#define OFFSET_LCR 0x0C /* Line Control Register */
54#define OFFSET_MCR 0x10 /* Modem Control Register */
55#define OFFSET_LSR 0x14 /* Line Status Register */
56#define OFFSET_MSR 0x18 /* Modem Status Register */
57#define OFFSET_SCR 0x1C /* SCR Scratch Register */
58#define OFFSET_GCTL 0x24 /* Global Control Register */
59
60#endif /* _MACH_BLACKFIN_H_ */
diff --git a/arch/blackfin/mach-bf533/include/mach/cdefBF532.h b/arch/blackfin/mach-bf533/include/mach/cdefBF532.h
new file mode 100644
index 000000000000..3d8978a52c17
--- /dev/null
+++ b/arch/blackfin/mach-bf533/include/mach/cdefBF532.h
@@ -0,0 +1,767 @@
1/*
2 * File: include/asm-blackfin/mach-bf533/cdefBF532.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _CDEF_BF532_H
32#define _CDEF_BF532_H
33
34#include <asm/blackfin.h>
35
36/*include all Core registers and bit definitions*/
37#include "defBF532.h"
38
39/*include core specific register pointer definitions*/
40#include <asm/cdef_LPBlackfin.h>
41
42#include <asm/system.h>
43
44/* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */
45#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
46/* Writing to PLL_CTL initiates a PLL relock sequence. */
47static __inline__ void bfin_write_PLL_CTL(unsigned int val)
48{
49 unsigned long flags, iwr;
50
51 if (val == bfin_read_PLL_CTL())
52 return;
53
54 local_irq_save(flags);
55 /* Enable the PLL Wakeup bit in SIC IWR */
56 iwr = bfin_read32(SIC_IWR);
57 /* Only allow PPL Wakeup) */
58 bfin_write32(SIC_IWR, IWR_ENABLE(0));
59
60 bfin_write16(PLL_CTL, val);
61 SSYNC();
62 asm("IDLE;");
63
64 bfin_write32(SIC_IWR, iwr);
65 local_irq_restore(flags);
66}
67#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
68#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
69#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
70#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val)
71#define bfin_read_CHIPID() bfin_read32(CHIPID)
72#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
73#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
74#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
75/* Writing to VR_CTL initiates a PLL relock sequence. */
76static __inline__ void bfin_write_VR_CTL(unsigned int val)
77{
78 unsigned long flags, iwr;
79
80 if (val == bfin_read_VR_CTL())
81 return;
82
83 local_irq_save(flags);
84 /* Enable the PLL Wakeup bit in SIC IWR */
85 iwr = bfin_read32(SIC_IWR);
86 /* Only allow PPL Wakeup) */
87 bfin_write32(SIC_IWR, IWR_ENABLE(0));
88
89 bfin_write16(VR_CTL, val);
90 SSYNC();
91 asm("IDLE;");
92
93 bfin_write32(SIC_IWR, iwr);
94 local_irq_restore(flags);
95}
96
97/* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */
98#define bfin_read_SWRST() bfin_read16(SWRST)
99#define bfin_write_SWRST(val) bfin_write16(SWRST,val)
100#define bfin_read_SYSCR() bfin_read16(SYSCR)
101#define bfin_write_SYSCR(val) bfin_write16(SYSCR,val)
102#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
103#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val)
104#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
105#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1,val)
106#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
107#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2,val)
108#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
109#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3,val)
110#define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK)
111#define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK,val)
112#define bfin_read_SIC_ISR() bfin_read32(SIC_ISR)
113#define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR,val)
114#define bfin_read_SIC_IWR() bfin_read32(SIC_IWR)
115#define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR,val)
116
117/* Watchdog Timer (0xFFC0 1000-0xFFC0 13FF) */
118#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
119#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL,val)
120#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
121#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT,val)
122#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
123#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT,val)
124
125/* Real Time Clock (0xFFC0 1400-0xFFC0 17FF) */
126#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
127#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT,val)
128#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
129#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL,val)
130#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
131#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT,val)
132#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
133#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT,val)
134#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
135#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM,val)
136#define bfin_read_RTC_FAST() bfin_read16(RTC_FAST)
137#define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST,val)
138#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
139#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN,val)
140
141/* DMA Traffic controls */
142#define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER)
143#define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER,val)
144#define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT)
145#define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT,val)
146
147/* Alternate deprecated register names (below) provided for backwards code compatibility */
148#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER)
149#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER,val)
150#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT)
151#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT,val)
152
153/* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */
154#define bfin_read_FIO_DIR() bfin_read16(FIO_DIR)
155#define bfin_write_FIO_DIR(val) bfin_write16(FIO_DIR,val)
156#define bfin_read_FIO_MASKA_C() bfin_read16(FIO_MASKA_C)
157#define bfin_write_FIO_MASKA_C(val) bfin_write16(FIO_MASKA_C,val)
158#define bfin_read_FIO_MASKA_S() bfin_read16(FIO_MASKA_S)
159#define bfin_write_FIO_MASKA_S(val) bfin_write16(FIO_MASKA_S,val)
160#define bfin_read_FIO_MASKB_C() bfin_read16(FIO_MASKB_C)
161#define bfin_write_FIO_MASKB_C(val) bfin_write16(FIO_MASKB_C,val)
162#define bfin_read_FIO_MASKB_S() bfin_read16(FIO_MASKB_S)
163#define bfin_write_FIO_MASKB_S(val) bfin_write16(FIO_MASKB_S,val)
164#define bfin_read_FIO_POLAR() bfin_read16(FIO_POLAR)
165#define bfin_write_FIO_POLAR(val) bfin_write16(FIO_POLAR,val)
166#define bfin_read_FIO_EDGE() bfin_read16(FIO_EDGE)
167#define bfin_write_FIO_EDGE(val) bfin_write16(FIO_EDGE,val)
168#define bfin_read_FIO_BOTH() bfin_read16(FIO_BOTH)
169#define bfin_write_FIO_BOTH(val) bfin_write16(FIO_BOTH,val)
170#define bfin_read_FIO_INEN() bfin_read16(FIO_INEN)
171#define bfin_write_FIO_INEN(val) bfin_write16(FIO_INEN,val)
172#define bfin_read_FIO_MASKA_D() bfin_read16(FIO_MASKA_D)
173#define bfin_write_FIO_MASKA_D(val) bfin_write16(FIO_MASKA_D,val)
174#define bfin_read_FIO_MASKA_T() bfin_read16(FIO_MASKA_T)
175#define bfin_write_FIO_MASKA_T(val) bfin_write16(FIO_MASKA_T,val)
176#define bfin_read_FIO_MASKB_D() bfin_read16(FIO_MASKB_D)
177#define bfin_write_FIO_MASKB_D(val) bfin_write16(FIO_MASKB_D,val)
178#define bfin_read_FIO_MASKB_T() bfin_read16(FIO_MASKB_T)
179#define bfin_write_FIO_MASKB_T(val) bfin_write16(FIO_MASKB_T,val)
180
181
182#if ANOMALY_05000311
183#define BFIN_WRITE_FIO_FLAG(name) \
184static __inline__ void bfin_write_FIO_FLAG_ ## name (unsigned short val)\
185{\
186 unsigned long flags;\
187 local_irq_save(flags);\
188 bfin_write16(FIO_FLAG_ ## name,val);\
189 bfin_read_CHIPID();\
190 local_irq_restore(flags);\
191}
192BFIN_WRITE_FIO_FLAG(D)
193BFIN_WRITE_FIO_FLAG(C)
194BFIN_WRITE_FIO_FLAG(S)
195BFIN_WRITE_FIO_FLAG(T)
196
197#define BFIN_READ_FIO_FLAG(name) \
198static __inline__ unsigned short bfin_read_FIO_FLAG_ ## name (void)\
199{\
200 unsigned long flags;\
201 unsigned short ret;\
202 local_irq_save(flags);\
203 ret = bfin_read16(FIO_FLAG_ ## name);\
204 bfin_read_CHIPID();\
205 local_irq_restore(flags);\
206 return ret;\
207}
208BFIN_READ_FIO_FLAG(D)
209BFIN_READ_FIO_FLAG(C)
210BFIN_READ_FIO_FLAG(S)
211BFIN_READ_FIO_FLAG(T)
212
213#else
214#define bfin_write_FIO_FLAG_D(val) bfin_write16(FIO_FLAG_D,val)
215#define bfin_write_FIO_FLAG_C(val) bfin_write16(FIO_FLAG_C,val)
216#define bfin_write_FIO_FLAG_S(val) bfin_write16(FIO_FLAG_S,val)
217#define bfin_write_FIO_FLAG_T(val) bfin_write16(FIO_FLAG_T,val)
218#define bfin_read_FIO_FLAG_T() bfin_read16(FIO_FLAG_T)
219#define bfin_read_FIO_FLAG_C() bfin_read16(FIO_FLAG_C)
220#define bfin_read_FIO_FLAG_S() bfin_read16(FIO_FLAG_S)
221#define bfin_read_FIO_FLAG_D() bfin_read16(FIO_FLAG_D)
222#endif
223
224
225/* DMA Controller */
226#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
227#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG,val)
228#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
229#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR,val)
230#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
231#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR,val)
232#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
233#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT,val)
234#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
235#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT,val)
236#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
237#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY,val)
238#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
239#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY,val)
240#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
241#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR,val)
242#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
243#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR,val)
244#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
245#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT,val)
246#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
247#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT,val)
248#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
249#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS,val)
250#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
251#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP,val)
252
253#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
254#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG,val)
255#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
256#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR,val)
257#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
258#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR,val)
259#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
260#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT,val)
261#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
262#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT,val)
263#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
264#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY,val)
265#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
266#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY,val)
267#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
268#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR,val)
269#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
270#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR,val)
271#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
272#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT,val)
273#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
274#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT,val)
275#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
276#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS,val)
277#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
278#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP,val)
279
280#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
281#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG,val)
282#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
283#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR,val)
284#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
285#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR,val)
286#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
287#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT,val)
288#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
289#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT,val)
290#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
291#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY,val)
292#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
293#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY,val)
294#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
295#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR,val)
296#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
297#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR,val)
298#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
299#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT,val)
300#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
301#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT,val)
302#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
303#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS,val)
304#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
305#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP,val)
306
307#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
308#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG,val)
309#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
310#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR,val)
311#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
312#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR,val)
313#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
314#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT,val)
315#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
316#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT,val)
317#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
318#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY,val)
319#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
320#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY,val)
321#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
322#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR,val)
323#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
324#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR,val)
325#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
326#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT,val)
327#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
328#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT,val)
329#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
330#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS,val)
331#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
332#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP,val)
333
334#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
335#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG,val)
336#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
337#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR,val)
338#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
339#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR,val)
340#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
341#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT,val)
342#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
343#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT,val)
344#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
345#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY,val)
346#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
347#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY,val)
348#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
349#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR,val)
350#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
351#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR,val)
352#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
353#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT,val)
354#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
355#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT,val)
356#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
357#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS,val)
358#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
359#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP,val)
360
361#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
362#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG,val)
363#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
364#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR,val)
365#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
366#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR,val)
367#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
368#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT,val)
369#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
370#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT,val)
371#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
372#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY,val)
373#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
374#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY,val)
375#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
376#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR,val)
377#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
378#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR,val)
379#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
380#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT,val)
381#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
382#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT,val)
383#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
384#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS,val)
385#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
386#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP,val)
387
388#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
389#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG,val)
390#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
391#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR,val)
392#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
393#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR,val)
394#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
395#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT,val)
396#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
397#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT,val)
398#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
399#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY,val)
400#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
401#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY,val)
402#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
403#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR,val)
404#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
405#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR,val)
406#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
407#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT,val)
408#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
409#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT,val)
410#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
411#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS,val)
412#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
413#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP,val)
414
415#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
416#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG,val)
417#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
418#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR,val)
419#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
420#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR,val)
421#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
422#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT,val)
423#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
424#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT,val)
425#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
426#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY,val)
427#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
428#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY,val)
429#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
430#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR,val)
431#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
432#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR,val)
433#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
434#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT,val)
435#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
436#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT,val)
437#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
438#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS,val)
439#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
440#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP,val)
441
442#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
443#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG,val)
444#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
445#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR,val)
446#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
447#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR,val)
448#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
449#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT,val)
450#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
451#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT,val)
452#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
453#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY,val)
454#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
455#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY,val)
456#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
457#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR,val)
458#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
459#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR,val)
460#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
461#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT,val)
462#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
463#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT,val)
464#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
465#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS,val)
466#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
467#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP,val)
468
469#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
470#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG,val)
471#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
472#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR,val)
473#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
474#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR,val)
475#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
476#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT,val)
477#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
478#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT,val)
479#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
480#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY,val)
481#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
482#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY,val)
483#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
484#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR,val)
485#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
486#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR,val)
487#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
488#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT,val)
489#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
490#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT,val)
491#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
492#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS,val)
493#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
494#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP,val)
495
496#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
497#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG,val)
498#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
499#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR,val)
500#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
501#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR,val)
502#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
503#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT,val)
504#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
505#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT,val)
506#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
507#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY,val)
508#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
509#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY,val)
510#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
511#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR,val)
512#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
513#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR,val)
514#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
515#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT,val)
516#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
517#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT,val)
518#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
519#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS,val)
520#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
521#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP,val)
522
523#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
524#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG,val)
525#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
526#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR,val)
527#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
528#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR,val)
529#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
530#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT,val)
531#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
532#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT,val)
533#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
534#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY,val)
535#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
536#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY,val)
537#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
538#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR,val)
539#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
540#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR,val)
541#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
542#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT,val)
543#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
544#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT,val)
545#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
546#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS,val)
547#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
548#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP,val)
549
550/* Aysnchronous Memory Controller - External Bus Interface Unit (0xFFC0 3C00-0xFFC0 3FFF) */
551#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
552#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL,val)
553#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
554#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0,val)
555#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
556#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1,val)
557
558/* SDRAM Controller External Bus Interface Unit (0xFFC0 4C00-0xFFC0 4FFF) */
559#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
560#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL,val)
561#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
562#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC,val)
563#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
564#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val)
565#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
566#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL,val)
567
568/* UART Controller */
569#define bfin_read_UART_THR() bfin_read16(UART_THR)
570#define bfin_write_UART_THR(val) bfin_write16(UART_THR,val)
571#define bfin_read_UART_RBR() bfin_read16(UART_RBR)
572#define bfin_write_UART_RBR(val) bfin_write16(UART_RBR,val)
573#define bfin_read_UART_DLL() bfin_read16(UART_DLL)
574#define bfin_write_UART_DLL(val) bfin_write16(UART_DLL,val)
575#define bfin_read_UART_IER() bfin_read16(UART_IER)
576#define bfin_write_UART_IER(val) bfin_write16(UART_IER,val)
577#define bfin_read_UART_DLH() bfin_read16(UART_DLH)
578#define bfin_write_UART_DLH(val) bfin_write16(UART_DLH,val)
579#define bfin_read_UART_IIR() bfin_read16(UART_IIR)
580#define bfin_write_UART_IIR(val) bfin_write16(UART_IIR,val)
581#define bfin_read_UART_LCR() bfin_read16(UART_LCR)
582#define bfin_write_UART_LCR(val) bfin_write16(UART_LCR,val)
583#define bfin_read_UART_MCR() bfin_read16(UART_MCR)
584#define bfin_write_UART_MCR(val) bfin_write16(UART_MCR,val)
585#define bfin_read_UART_LSR() bfin_read16(UART_LSR)
586#define bfin_write_UART_LSR(val) bfin_write16(UART_LSR,val)
587/*
588#define UART_MSR
589*/
590#define bfin_read_UART_SCR() bfin_read16(UART_SCR)
591#define bfin_write_UART_SCR(val) bfin_write16(UART_SCR,val)
592#define bfin_read_UART_GCTL() bfin_read16(UART_GCTL)
593#define bfin_write_UART_GCTL(val) bfin_write16(UART_GCTL,val)
594
595/* SPI Controller */
596#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL)
597#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL,val)
598#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG)
599#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG,val)
600#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT)
601#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT,val)
602#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR)
603#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR,val)
604#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR)
605#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR,val)
606#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD)
607#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD,val)
608#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW)
609#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW,val)
610
611/* TIMER 0, 1, 2 Registers */
612#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
613#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG,val)
614#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
615#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER,val)
616#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
617#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD,val)
618#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
619#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH,val)
620
621#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
622#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG,val)
623#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
624#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER,val)
625#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
626#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD,val)
627#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
628#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH,val)
629
630#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
631#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG,val)
632#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
633#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER,val)
634#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
635#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD,val)
636#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
637#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH,val)
638
639#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
640#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE,val)
641#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE)
642#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE,val)
643#define bfin_read_TIMER_STATUS() bfin_read16(TIMER_STATUS)
644#define bfin_write_TIMER_STATUS(val) bfin_write16(TIMER_STATUS,val)
645
646/* SPORT0 Controller */
647#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
648#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1,val)
649#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
650#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2,val)
651#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
652#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV,val)
653#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
654#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV,val)
655#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
656#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX,val)
657#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
658#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX,val)
659#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX)
660#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX,val)
661#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX)
662#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX,val)
663#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX)
664#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX,val)
665#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX)
666#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX,val)
667#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
668#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1,val)
669#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
670#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2,val)
671#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
672#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV,val)
673#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
674#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV,val)
675#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
676#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT,val)
677#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
678#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL,val)
679#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
680#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1,val)
681#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
682#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2,val)
683#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
684#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0,val)
685#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
686#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1,val)
687#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
688#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2,val)
689#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
690#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3,val)
691#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
692#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0,val)
693#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
694#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1,val)
695#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
696#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2,val)
697#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
698#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3,val)
699
700/* SPORT1 Controller */
701#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
702#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1,val)
703#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
704#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2,val)
705#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
706#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV,val)
707#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
708#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV,val)
709#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
710#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX,val)
711#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
712#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX,val)
713#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX)
714#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX,val)
715#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX)
716#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX,val)
717#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX)
718#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX,val)
719#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX)
720#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX,val)
721#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
722#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1,val)
723#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
724#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2,val)
725#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
726#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV,val)
727#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
728#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV,val)
729#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
730#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT,val)
731#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
732#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL,val)
733#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
734#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1,val)
735#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
736#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2,val)
737#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
738#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0,val)
739#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
740#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1,val)
741#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
742#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2,val)
743#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
744#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3,val)
745#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
746#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0,val)
747#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
748#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1,val)
749#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
750#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2,val)
751#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
752#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3,val)
753
754/* Parallel Peripheral Interface (PPI) */
755#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
756#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL,val)
757#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
758#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS,val)
759#define bfin_clear_PPI_STATUS() bfin_read_PPI_STATUS()
760#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
761#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY,val)
762#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
763#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT,val)
764#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
765#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME,val)
766
767#endif /* _CDEF_BF532_H */
diff --git a/arch/blackfin/mach-bf533/include/mach/defBF532.h b/arch/blackfin/mach-bf533/include/mach/defBF532.h
new file mode 100644
index 000000000000..7f4633223e6d
--- /dev/null
+++ b/arch/blackfin/mach-bf533/include/mach/defBF532.h
@@ -0,0 +1,1266 @@
1/************************************************************************
2 *
3 * This file is subject to the terms and conditions of the GNU Public
4 * License. See the file "COPYING" in the main directory of this archive
5 * for more details.
6 *
7 * Non-GPL License also available as part of VisualDSP++
8 * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
9 *
10 * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
11 *
12 * This file under source code control, please send bugs or changes to:
13 * dsptools.support@analog.com
14 *
15 ************************************************************************/
16/*
17 * File: include/asm-blackfin/mach-bf533/defBF532.h
18 * Based on:
19 * Author:
20 *
21 * Created:
22 * Description:
23 *
24 * Rev:
25 *
26 * Modified:
27 *
28 * Bugs: Enter bugs at http://blackfin.uclinux.org/
29 *
30 * This program is free software; you can redistribute it and/or modify
31 * it under the terms of the GNU General Public License as published by
32 * the Free Software Foundation; either version 2, or (at your option)
33 * any later version.
34 *
35 * This program is distributed in the hope that it will be useful,
36 * but WITHOUT ANY WARRANTY; without even the implied warranty of
37 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
38 * GNU General Public License for more details.
39 *
40 * You should have received a copy of the GNU General Public License
41 * along with this program; see the file COPYING.
42 * If not, write to the Free Software Foundation,
43 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
44 */
45/* SYSTEM & MM REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532 */
46
47#ifndef _DEF_BF532_H
48#define _DEF_BF532_H
49
50/* include all Core registers and bit definitions */
51#include <asm/def_LPBlackfin.h>
52
53/*********************************************************************************** */
54/* System MMR Register Map */
55/*********************************************************************************** */
56/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
57
58#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */
59#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */
60#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */
61#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */
62#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
63#define CHIPID 0xFFC00014 /* Chip ID Register */
64
65/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
66#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */
67#define SYSCR 0xFFC00104 /* System Configuration registe */
68#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
69#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */
70#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
71#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
72#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
73#define SIC_ISR 0xFFC00120 /* Interrupt Status Register */
74#define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */
75
76/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
77#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
78#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
79#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
80
81/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
82#define RTC_STAT 0xFFC00300 /* RTC Status Register */
83#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
84#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
85#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
86#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
87#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
88#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register (alternate macro) */
89
90/* UART Controller (0xFFC00400 - 0xFFC004FF) */
91
92/*
93 * Because include/linux/serial_reg.h have defined UART_*,
94 * So we define blackfin uart regs to BFIN_UART_*.
95 */
96#define BFIN_UART_THR 0xFFC00400 /* Transmit Holding register */
97#define BFIN_UART_RBR 0xFFC00400 /* Receive Buffer register */
98#define BFIN_UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
99#define BFIN_UART_IER 0xFFC00404 /* Interrupt Enable Register */
100#define BFIN_UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
101#define BFIN_UART_IIR 0xFFC00408 /* Interrupt Identification Register */
102#define BFIN_UART_LCR 0xFFC0040C /* Line Control Register */
103#define BFIN_UART_MCR 0xFFC00410 /* Modem Control Register */
104#define BFIN_UART_LSR 0xFFC00414 /* Line Status Register */
105#if 0
106#define BFIN_UART_MSR 0xFFC00418 /* Modem Status Register (UNUSED in ADSP-BF532) */
107#endif
108#define BFIN_UART_SCR 0xFFC0041C /* SCR Scratch Register */
109#define BFIN_UART_GCTL 0xFFC00424 /* Global Control Register */
110
111/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
112#define SPI0_REGBASE 0xFFC00500
113#define SPI_CTL 0xFFC00500 /* SPI Control Register */
114#define SPI_FLG 0xFFC00504 /* SPI Flag register */
115#define SPI_STAT 0xFFC00508 /* SPI Status register */
116#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
117#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
118#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
119#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
120
121/* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */
122
123#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
124#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
125#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
126#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
127
128#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
129#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
130#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
131#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
132
133#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
134#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
135#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
136#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
137
138#define TIMER_ENABLE 0xFFC00640 /* Timer Enable Register */
139#define TIMER_DISABLE 0xFFC00644 /* Timer Disable Register */
140#define TIMER_STATUS 0xFFC00648 /* Timer Status Register */
141
142/* General Purpose IO (0xFFC00700 - 0xFFC007FF) */
143
144#define FIO_FLAG_D 0xFFC00700 /* Flag Mask to directly specify state of pins */
145#define FIO_FLAG_C 0xFFC00704 /* Peripheral Interrupt Flag Register (clear) */
146#define FIO_FLAG_S 0xFFC00708 /* Peripheral Interrupt Flag Register (set) */
147#define FIO_FLAG_T 0xFFC0070C /* Flag Mask to directly toggle state of pins */
148#define FIO_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Register (set directly) */
149#define FIO_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Register (clear) */
150#define FIO_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Register (set) */
151#define FIO_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Register (toggle) */
152#define FIO_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Register (set directly) */
153#define FIO_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Register (clear) */
154#define FIO_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Register (set) */
155#define FIO_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Register (toggle) */
156#define FIO_DIR 0xFFC00730 /* Peripheral Flag Direction Register */
157#define FIO_POLAR 0xFFC00734 /* Flag Source Polarity Register */
158#define FIO_EDGE 0xFFC00738 /* Flag Source Sensitivity Register */
159#define FIO_BOTH 0xFFC0073C /* Flag Set on BOTH Edges Register */
160#define FIO_INEN 0xFFC00740 /* Flag Input Enable Register */
161
162/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
163#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
164#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
165#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
166#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
167#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
168#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
169#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
170#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
171#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
172#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
173#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
174#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
175#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
176#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
177#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
178#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
179#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
180#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
181#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
182#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
183#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
184#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
185
186/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
187#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
188#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
189#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
190#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
191#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
192#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
193#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
194#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
195#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
196#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
197#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
198#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
199#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
200#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
201#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
202#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
203#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
204#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
205#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
206#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
207#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
208#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
209
210/* Asynchronous Memory Controller - External Bus Interface Unit */
211#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
212#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
213#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
214
215/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
216
217#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
218#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
219#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
220#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
221
222/* DMA Traffic controls */
223#define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
224#define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
225
226/* Alternate deprecated register names (below) provided for backwards code compatibility */
227#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
228#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
229
230/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
231#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
232#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
233#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
234#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
235#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
236#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
237#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
238#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
239#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
240#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
241#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
242#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
243#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
244
245#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
246#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
247#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
248#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
249#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
250#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
251#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
252#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
253#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
254#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
255#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
256#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
257#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
258
259#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
260#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
261#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
262#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
263#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
264#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
265#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
266#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
267#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
268#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
269#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
270#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
271#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
272
273#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
274#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
275#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
276#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
277#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
278#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
279#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
280#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
281#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
282#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
283#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
284#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
285#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
286
287#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
288#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
289#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
290#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
291#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
292#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
293#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
294#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
295#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
296#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
297#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
298#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
299#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
300
301#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
302#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
303#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
304#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
305#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
306#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
307#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
308#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
309#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
310#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
311#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
312#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
313#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
314
315#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
316#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
317#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
318#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
319#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
320#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
321#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
322#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
323#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
324#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
325#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
326#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
327#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
328
329#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
330#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
331#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
332#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
333#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
334#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
335#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
336#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
337#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
338#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
339#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
340#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
341#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
342
343#define MDMA_D1_CONFIG 0xFFC00E88 /* MemDMA Stream 1 Destination Configuration Register */
344#define MDMA_D1_NEXT_DESC_PTR 0xFFC00E80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
345#define MDMA_D1_START_ADDR 0xFFC00E84 /* MemDMA Stream 1 Destination Start Address Register */
346#define MDMA_D1_X_COUNT 0xFFC00E90 /* MemDMA Stream 1 Destination X Count Register */
347#define MDMA_D1_Y_COUNT 0xFFC00E98 /* MemDMA Stream 1 Destination Y Count Register */
348#define MDMA_D1_X_MODIFY 0xFFC00E94 /* MemDMA Stream 1 Destination X Modify Register */
349#define MDMA_D1_Y_MODIFY 0xFFC00E9C /* MemDMA Stream 1 Destination Y Modify Register */
350#define MDMA_D1_CURR_DESC_PTR 0xFFC00EA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
351#define MDMA_D1_CURR_ADDR 0xFFC00EA4 /* MemDMA Stream 1 Destination Current Address Register */
352#define MDMA_D1_CURR_X_COUNT 0xFFC00EB0 /* MemDMA Stream 1 Destination Current X Count Register */
353#define MDMA_D1_CURR_Y_COUNT 0xFFC00EB8 /* MemDMA Stream 1 Destination Current Y Count Register */
354#define MDMA_D1_IRQ_STATUS 0xFFC00EA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
355#define MDMA_D1_PERIPHERAL_MAP 0xFFC00EAC /* MemDMA Stream 1 Destination Peripheral Map Register */
356
357#define MDMA_S1_CONFIG 0xFFC00EC8 /* MemDMA Stream 1 Source Configuration Register */
358#define MDMA_S1_NEXT_DESC_PTR 0xFFC00EC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
359#define MDMA_S1_START_ADDR 0xFFC00EC4 /* MemDMA Stream 1 Source Start Address Register */
360#define MDMA_S1_X_COUNT 0xFFC00ED0 /* MemDMA Stream 1 Source X Count Register */
361#define MDMA_S1_Y_COUNT 0xFFC00ED8 /* MemDMA Stream 1 Source Y Count Register */
362#define MDMA_S1_X_MODIFY 0xFFC00ED4 /* MemDMA Stream 1 Source X Modify Register */
363#define MDMA_S1_Y_MODIFY 0xFFC00EDC /* MemDMA Stream 1 Source Y Modify Register */
364#define MDMA_S1_CURR_DESC_PTR 0xFFC00EE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
365#define MDMA_S1_CURR_ADDR 0xFFC00EE4 /* MemDMA Stream 1 Source Current Address Register */
366#define MDMA_S1_CURR_X_COUNT 0xFFC00EF0 /* MemDMA Stream 1 Source Current X Count Register */
367#define MDMA_S1_CURR_Y_COUNT 0xFFC00EF8 /* MemDMA Stream 1 Source Current Y Count Register */
368#define MDMA_S1_IRQ_STATUS 0xFFC00EE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
369#define MDMA_S1_PERIPHERAL_MAP 0xFFC00EEC /* MemDMA Stream 1 Source Peripheral Map Register */
370
371#define MDMA_D0_CONFIG 0xFFC00E08 /* MemDMA Stream 0 Destination Configuration Register */
372#define MDMA_D0_NEXT_DESC_PTR 0xFFC00E00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
373#define MDMA_D0_START_ADDR 0xFFC00E04 /* MemDMA Stream 0 Destination Start Address Register */
374#define MDMA_D0_X_COUNT 0xFFC00E10 /* MemDMA Stream 0 Destination X Count Register */
375#define MDMA_D0_Y_COUNT 0xFFC00E18 /* MemDMA Stream 0 Destination Y Count Register */
376#define MDMA_D0_X_MODIFY 0xFFC00E14 /* MemDMA Stream 0 Destination X Modify Register */
377#define MDMA_D0_Y_MODIFY 0xFFC00E1C /* MemDMA Stream 0 Destination Y Modify Register */
378#define MDMA_D0_CURR_DESC_PTR 0xFFC00E20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
379#define MDMA_D0_CURR_ADDR 0xFFC00E24 /* MemDMA Stream 0 Destination Current Address Register */
380#define MDMA_D0_CURR_X_COUNT 0xFFC00E30 /* MemDMA Stream 0 Destination Current X Count Register */
381#define MDMA_D0_CURR_Y_COUNT 0xFFC00E38 /* MemDMA Stream 0 Destination Current Y Count Register */
382#define MDMA_D0_IRQ_STATUS 0xFFC00E28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
383#define MDMA_D0_PERIPHERAL_MAP 0xFFC00E2C /* MemDMA Stream 0 Destination Peripheral Map Register */
384
385#define MDMA_S0_CONFIG 0xFFC00E48 /* MemDMA Stream 0 Source Configuration Register */
386#define MDMA_S0_NEXT_DESC_PTR 0xFFC00E40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
387#define MDMA_S0_START_ADDR 0xFFC00E44 /* MemDMA Stream 0 Source Start Address Register */
388#define MDMA_S0_X_COUNT 0xFFC00E50 /* MemDMA Stream 0 Source X Count Register */
389#define MDMA_S0_Y_COUNT 0xFFC00E58 /* MemDMA Stream 0 Source Y Count Register */
390#define MDMA_S0_X_MODIFY 0xFFC00E54 /* MemDMA Stream 0 Source X Modify Register */
391#define MDMA_S0_Y_MODIFY 0xFFC00E5C /* MemDMA Stream 0 Source Y Modify Register */
392#define MDMA_S0_CURR_DESC_PTR 0xFFC00E60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
393#define MDMA_S0_CURR_ADDR 0xFFC00E64 /* MemDMA Stream 0 Source Current Address Register */
394#define MDMA_S0_CURR_X_COUNT 0xFFC00E70 /* MemDMA Stream 0 Source Current X Count Register */
395#define MDMA_S0_CURR_Y_COUNT 0xFFC00E78 /* MemDMA Stream 0 Source Current Y Count Register */
396#define MDMA_S0_IRQ_STATUS 0xFFC00E68 /* MemDMA Stream 0 Source Interrupt/Status Register */
397#define MDMA_S0_PERIPHERAL_MAP 0xFFC00E6C /* MemDMA Stream 0 Source Peripheral Map Register */
398
399/* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */
400
401#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
402#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
403#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
404#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
405#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
406
407/*********************************************************************************** */
408/* System MMR Register Bits */
409/******************************************************************************* */
410
411/* ********************* PLL AND RESET MASKS ************************ */
412
413/* PLL_CTL Masks */
414#define PLL_CLKIN 0x0000 /* Pass CLKIN to PLL */
415#define PLL_CLKIN_DIV2 0x0001 /* Pass CLKIN/2 to PLL */
416#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
417#define PLL_OFF 0x0002 /* Shut off PLL clocks */
418#define STOPCK_OFF 0x0008 /* Core clock off */
419#define STOPCK 0x0008 /* Core Clock Off */
420#define PDWN 0x0020 /* Put the PLL in a Deep Sleep state */
421#if !defined(__ADSPBF538__)
422/* this file is included in defBF538.h but IN_DELAY/OUT_DELAY are different */
423# define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */
424# define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */
425#endif
426#define BYPASS 0x0100 /* Bypass the PLL */
427/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */
428#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
429
430/* PLL_DIV Masks */
431#define SSEL 0x000F /* System Select */
432#define CSEL 0x0030 /* Core Select */
433
434#define SCLK_DIV(x) (x) /* SCLK = VCO / x */
435
436#define CCLK_DIV1 0x00000000 /* CCLK = VCO / 1 */
437#define CCLK_DIV2 0x00000010 /* CCLK = VCO / 2 */
438#define CCLK_DIV4 0x00000020 /* CCLK = VCO / 4 */
439#define CCLK_DIV8 0x00000030 /* CCLK = VCO / 8 */
440/* PLL_DIV Macros */
441#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
442
443/* PLL_STAT Masks */
444#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
445#define FULL_ON 0x0002 /* Processor In Full On Mode */
446#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
447#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
448
449/* VR_CTL Masks */
450#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */
451#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
452#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
453#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
454#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
455
456#define GAIN 0x000C /* Voltage Level Gain */
457#define GAIN_5 0x0000 /* GAIN = 5 */
458#define GAIN_10 0x0004 /* GAIN = 10 */
459#define GAIN_20 0x0008 /* GAIN = 20 */
460#define GAIN_50 0x000C /* GAIN = 50 */
461
462#define VLEV 0x00F0 /* Internal Voltage Level */
463#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
464#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
465#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
466#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
467#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
468#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
469#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
470#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
471#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */
472#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
473
474#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
475#define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */
476
477/* CHIPID Masks */
478#define CHIPID_VERSION 0xF0000000
479#define CHIPID_FAMILY 0x0FFFF000
480#define CHIPID_MANUFACTURE 0x00000FFE
481
482/* SWRST Mask */
483#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
484#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
485#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
486#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
487#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
488
489/* SYSCR Masks */
490#define BMODE 0x0006 /* Boot Mode - Latched During HW Reset From Mode Pins */
491#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
492
493/* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
494
495 /* SIC_IAR0 Masks */
496
497#define P0_IVG(x) ((x)-7) /* Peripheral #0 assigned IVG #x */
498#define P1_IVG(x) ((x)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
499#define P2_IVG(x) ((x)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
500#define P3_IVG(x) ((x)-7) << 0xC /* Peripheral #3 assigned IVG #x */
501#define P4_IVG(x) ((x)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
502#define P5_IVG(x) ((x)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
503#define P6_IVG(x) ((x)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
504#define P7_IVG(x) ((x)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
505
506/* SIC_IAR1 Masks */
507
508#define P8_IVG(x) ((x)-7) /* Peripheral #8 assigned IVG #x */
509#define P9_IVG(x) ((x)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
510#define P10_IVG(x) ((x)-7) << 0x8 /* Peripheral #10 assigned IVG #x */
511#define P11_IVG(x) ((x)-7) << 0xC /* Peripheral #11 assigned IVG #x */
512#define P12_IVG(x) ((x)-7) << 0x10 /* Peripheral #12 assigned IVG #x */
513#define P13_IVG(x) ((x)-7) << 0x14 /* Peripheral #13 assigned IVG #x */
514#define P14_IVG(x) ((x)-7) << 0x18 /* Peripheral #14 assigned IVG #x */
515#define P15_IVG(x) ((x)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
516
517/* SIC_IAR2 Masks */
518#define P16_IVG(x) ((x)-7) /* Peripheral #16 assigned IVG #x */
519#define P17_IVG(x) ((x)-7) << 0x4 /* Peripheral #17 assigned IVG #x */
520#define P18_IVG(x) ((x)-7) << 0x8 /* Peripheral #18 assigned IVG #x */
521#define P19_IVG(x) ((x)-7) << 0xC /* Peripheral #19 assigned IVG #x */
522#define P20_IVG(x) ((x)-7) << 0x10 /* Peripheral #20 assigned IVG #x */
523#define P21_IVG(x) ((x)-7) << 0x14 /* Peripheral #21 assigned IVG #x */
524#define P22_IVG(x) ((x)-7) << 0x18 /* Peripheral #22 assigned IVG #x */
525#define P23_IVG(x) ((x)-7) << 0x1C /* Peripheral #23 assigned IVG #x */
526
527/* SIC_IMASK Masks */
528#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
529#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
530#define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */
531#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */
532
533/* SIC_IWR Masks */
534#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
535#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
536#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
537#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */
538
539/* ***************************** UART CONTROLLER MASKS ********************** */
540
541/* UART_LCR Register */
542
543#define DLAB 0x80
544#define SB 0x40
545#define STP 0x20
546#define EPS 0x10
547#define PEN 0x08
548#define STB 0x04
549#define WLS(x) ((x-5) & 0x03)
550
551#define DLAB_P 0x07
552#define SB_P 0x06
553#define STP_P 0x05
554#define EPS_P 0x04
555#define PEN_P 0x03
556#define STB_P 0x02
557#define WLS_P1 0x01
558#define WLS_P0 0x00
559
560/* UART_MCR Register */
561#define LOOP_ENA 0x10
562#define LOOP_ENA_P 0x04
563
564/* UART_LSR Register */
565#define TEMT 0x40
566#define THRE 0x20
567#define BI 0x10
568#define FE 0x08
569#define PE 0x04
570#define OE 0x02
571#define DR 0x01
572
573#define TEMP_P 0x06
574#define THRE_P 0x05
575#define BI_P 0x04
576#define FE_P 0x03
577#define PE_P 0x02
578#define OE_P 0x01
579#define DR_P 0x00
580
581/* UART_IER Register */
582#define ELSI 0x04
583#define ETBEI 0x02
584#define ERBFI 0x01
585
586#define ELSI_P 0x02
587#define ETBEI_P 0x01
588#define ERBFI_P 0x00
589
590/* UART_IIR Register */
591#define STATUS(x) ((x << 1) & 0x06)
592#define NINT 0x01
593#define STATUS_P1 0x02
594#define STATUS_P0 0x01
595#define NINT_P 0x00
596#define IIR_TX_READY 0x02 /* UART_THR empty */
597#define IIR_RX_READY 0x04 /* Receive data ready */
598#define IIR_LINE_CHANGE 0x06 /* Receive line status */
599#define IIR_STATUS 0x06
600
601/* UART_GCTL Register */
602#define FFE 0x20
603#define FPE 0x10
604#define RPOLC 0x08
605#define TPOLC 0x04
606#define IREN 0x02
607#define UCEN 0x01
608
609#define FFE_P 0x05
610#define FPE_P 0x04
611#define RPOLC_P 0x03
612#define TPOLC_P 0x02
613#define IREN_P 0x01
614#define UCEN_P 0x00
615
616/* ********** SERIAL PORT MASKS ********************** */
617
618/* SPORTx_TCR1 Masks */
619#define TSPEN 0x0001 /* TX enable */
620#define ITCLK 0x0002 /* Internal TX Clock Select */
621#define TDTYPE 0x000C /* TX Data Formatting Select */
622#define DTYPE_NORM 0x0000 /* Data Format Normal */
623#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
624#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
625#define TLSBIT 0x0010 /* TX Bit Order */
626#define ITFS 0x0200 /* Internal TX Frame Sync Select */
627#define TFSR 0x0400 /* TX Frame Sync Required Select */
628#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */
629#define LTFS 0x1000 /* Low TX Frame Sync Select */
630#define LATFS 0x2000 /* Late TX Frame Sync Select */
631#define TCKFE 0x4000 /* TX Clock Falling Edge Select */
632
633/* SPORTx_TCR2 Masks */
634#if defined(__ADSPBF531__) || defined(__ADSPBF532__) || \
635 defined(__ADSPBF533__)
636# define SLEN 0x001F /*TX Word Length */
637#else
638# define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
639#endif
640#define TXSE 0x0100 /*TX Secondary Enable */
641#define TSFSE 0x0200 /*TX Stereo Frame Sync Enable */
642#define TRFST 0x0400 /*TX Right-First Data Order */
643
644/* SPORTx_RCR1 Masks */
645#define RSPEN 0x0001 /* RX enable */
646#define IRCLK 0x0002 /* Internal RX Clock Select */
647#define RDTYPE 0x000C /* RX Data Formatting Select */
648#define DTYPE_NORM 0x0000 /* no companding */
649#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
650#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
651#define RLSBIT 0x0010 /* RX Bit Order */
652#define IRFS 0x0200 /* Internal RX Frame Sync Select */
653#define RFSR 0x0400 /* RX Frame Sync Required Select */
654#define LRFS 0x1000 /* Low RX Frame Sync Select */
655#define LARFS 0x2000 /* Late RX Frame Sync Select */
656#define RCKFE 0x4000 /* RX Clock Falling Edge Select */
657
658/* SPORTx_RCR2 Masks */
659/* SLEN defined above */
660#define RXSE 0x0100 /*RX Secondary Enable */
661#define RSFSE 0x0200 /*RX Stereo Frame Sync Enable */
662#define RRFST 0x0400 /*Right-First Data Order */
663
664/*SPORTx_STAT Masks */
665#define RXNE 0x0001 /*RX FIFO Not Empty Status */
666#define RUVF 0x0002 /*RX Underflow Status */
667#define ROVF 0x0004 /*RX Overflow Status */
668#define TXF 0x0008 /*TX FIFO Full Status */
669#define TUVF 0x0010 /*TX Underflow Status */
670#define TOVF 0x0020 /*TX Overflow Status */
671#define TXHRE 0x0040 /*TX Hold Register Empty */
672
673/*SPORTx_MCMC1 Masks */
674#define SP_WSIZE 0x0000F000 /*Multichannel Window Size Field */
675#define SP_WOFF 0x000003FF /*Multichannel Window Offset Field */
676/* SPORTx_MCMC1 Macros */
677#define SET_SP_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
678/* Only use SET_WSIZE Macro With Logic OR While Setting Lower Order Bits */
679#define SET_SP_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
680
681/*SPORTx_MCMC2 Masks */
682#define MCCRM 0x00000003 /*Multichannel Clock Recovery Mode */
683#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
684#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
685#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
686#define MCDTXPE 0x00000004 /*Multichannel DMA Transmit Packing */
687#define MCDRXPE 0x00000008 /*Multichannel DMA Receive Packing */
688#define MCMEN 0x00000010 /*Multichannel Frame Mode Enable */
689#define FSDR 0x00000080 /*Multichannel Frame Sync to Data Relationship */
690#define MFD 0x0000F000 /*Multichannel Frame Delay */
691#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */
692#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */
693#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */
694#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */
695#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */
696#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */
697#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */
698#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */
699#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */
700#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */
701#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */
702#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */
703#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */
704#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */
705#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */
706#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */
707
708/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */
709
710/* PPI_CONTROL Masks */
711#define PORT_EN 0x00000001 /* PPI Port Enable */
712#define PORT_DIR 0x00000002 /* PPI Port Direction */
713#define XFR_TYPE 0x0000000C /* PPI Transfer Type */
714#define PORT_CFG 0x00000030 /* PPI Port Configuration */
715#define FLD_SEL 0x00000040 /* PPI Active Field Select */
716#define PACK_EN 0x00000080 /* PPI Packing Mode */
717#define DMA32 0x00000100 /* PPI 32-bit DMA Enable */
718#define SKIP_EN 0x00000200 /* PPI Skip Element Enable */
719#define SKIP_EO 0x00000400 /* PPI Skip Even/Odd Elements */
720#define DLENGTH 0x00003800 /* PPI Data Length */
721#define DLEN_8 0x0000 /* Data Length = 8 Bits */
722#define DLEN_10 0x0800 /* Data Length = 10 Bits */
723#define DLEN_11 0x1000 /* Data Length = 11 Bits */
724#define DLEN_12 0x1800 /* Data Length = 12 Bits */
725#define DLEN_13 0x2000 /* Data Length = 13 Bits */
726#define DLEN_14 0x2800 /* Data Length = 14 Bits */
727#define DLEN_15 0x3000 /* Data Length = 15 Bits */
728#define DLEN_16 0x3800 /* Data Length = 16 Bits */
729#define DLEN(x) (((x-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */
730#define POL 0x0000C000 /* PPI Signal Polarities */
731#define POLC 0x4000 /* PPI Clock Polarity */
732#define POLS 0x8000 /* PPI Frame Sync Polarity */
733
734/* PPI_STATUS Masks */
735#define FLD 0x00000400 /* Field Indicator */
736#define FT_ERR 0x00000800 /* Frame Track Error */
737#define OVR 0x00001000 /* FIFO Overflow Error */
738#define UNDR 0x00002000 /* FIFO Underrun Error */
739#define ERR_DET 0x00004000 /* Error Detected Indicator */
740#define ERR_NCOR 0x00008000 /* Error Not Corrected Indicator */
741
742/* ********** DMA CONTROLLER MASKS *********************8 */
743
744/*DMAx_CONFIG, MDMA_yy_CONFIG Masks */
745#define DMAEN 0x00000001 /* Channel Enable */
746#define WNR 0x00000002 /* Channel Direction (W/R*) */
747#define WDSIZE_8 0x00000000 /* Word Size 8 bits */
748#define WDSIZE_16 0x00000004 /* Word Size 16 bits */
749#define WDSIZE_32 0x00000008 /* Word Size 32 bits */
750#define DMA2D 0x00000010 /* 2D/1D* Mode */
751#define RESTART 0x00000020 /* Restart */
752#define DI_SEL 0x00000040 /* Data Interrupt Select */
753#define DI_EN 0x00000080 /* Data Interrupt Enable */
754#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
755#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
756#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
757#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
758#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
759#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
760#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
761#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
762#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
763#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
764#define NDSIZE 0x00000900 /* Next Descriptor Size */
765#define DMAFLOW 0x00007000 /* Flow Control */
766#define DMAFLOW_STOP 0x0000 /* Stop Mode */
767#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
768#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
769#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
770#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
771
772#define DMAEN_P 0 /* Channel Enable */
773#define WNR_P 1 /* Channel Direction (W/R*) */
774#define DMA2D_P 4 /* 2D/1D* Mode */
775#define RESTART_P 5 /* Restart */
776#define DI_SEL_P 6 /* Data Interrupt Select */
777#define DI_EN_P 7 /* Data Interrupt Enable */
778
779/*DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
780
781#define DMA_DONE 0x00000001 /* DMA Done Indicator */
782#define DMA_ERR 0x00000002 /* DMA Error Indicator */
783#define DFETCH 0x00000004 /* Descriptor Fetch Indicator */
784#define DMA_RUN 0x00000008 /* DMA Running Indicator */
785
786#define DMA_DONE_P 0 /* DMA Done Indicator */
787#define DMA_ERR_P 1 /* DMA Error Indicator */
788#define DFETCH_P 2 /* Descriptor Fetch Indicator */
789#define DMA_RUN_P 3 /* DMA Running Indicator */
790
791/*DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
792
793#define CTYPE 0x00000040 /* DMA Channel Type Indicator */
794#define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */
795#define PCAP8 0x00000080 /* DMA 8-bit Operation Indicator */
796#define PCAP16 0x00000100 /* DMA 16-bit Operation Indicator */
797#define PCAP32 0x00000200 /* DMA 32-bit Operation Indicator */
798#define PCAPWR 0x00000400 /* DMA Write Operation Indicator */
799#define PCAPRD 0x00000800 /* DMA Read Operation Indicator */
800#define PMAP 0x00007000 /* DMA Peripheral Map Field */
801
802#define PMAP_PPI 0x0000 /* PMAP PPI Port DMA */
803#define PMAP_SPORT0RX 0x1000 /* PMAP SPORT0 Receive DMA */
804#define PMAP_SPORT0TX 0x2000 /* PMAP SPORT0 Transmit DMA */
805#define PMAP_SPORT1RX 0x3000 /* PMAP SPORT1 Receive DMA */
806#define PMAP_SPORT1TX 0x4000 /* PMAP SPORT1 Transmit DMA */
807#define PMAP_SPI 0x5000 /* PMAP SPI DMA */
808#define PMAP_UARTRX 0x6000 /* PMAP UART Receive DMA */
809#define PMAP_UARTTX 0x7000 /* PMAP UART Transmit DMA */
810
811/* ************* GENERAL PURPOSE TIMER MASKS ******************** */
812
813/* PWM Timer bit definitions */
814
815/* TIMER_ENABLE Register */
816#define TIMEN0 0x0001
817#define TIMEN1 0x0002
818#define TIMEN2 0x0004
819
820#define TIMEN0_P 0x00
821#define TIMEN1_P 0x01
822#define TIMEN2_P 0x02
823
824/* TIMER_DISABLE Register */
825#define TIMDIS0 0x0001
826#define TIMDIS1 0x0002
827#define TIMDIS2 0x0004
828
829#define TIMDIS0_P 0x00
830#define TIMDIS1_P 0x01
831#define TIMDIS2_P 0x02
832
833/* TIMER_STATUS Register */
834#define TIMIL0 0x0001
835#define TIMIL1 0x0002
836#define TIMIL2 0x0004
837#define TOVF_ERR0 0x0010 /* Timer 0 Counter Overflow */
838#define TOVF_ERR1 0x0020 /* Timer 1 Counter Overflow */
839#define TOVF_ERR2 0x0040 /* Timer 2 Counter Overflow */
840#define TRUN0 0x1000
841#define TRUN1 0x2000
842#define TRUN2 0x4000
843
844#define TIMIL0_P 0x00
845#define TIMIL1_P 0x01
846#define TIMIL2_P 0x02
847#define TOVF_ERR0_P 0x04
848#define TOVF_ERR1_P 0x05
849#define TOVF_ERR2_P 0x06
850#define TRUN0_P 0x0C
851#define TRUN1_P 0x0D
852#define TRUN2_P 0x0E
853
854/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
855#define TOVL_ERR0 TOVF_ERR0
856#define TOVL_ERR1 TOVF_ERR1
857#define TOVL_ERR2 TOVF_ERR2
858#define TOVL_ERR0_P TOVF_ERR0_P
859#define TOVL_ERR1_P TOVF_ERR1_P
860#define TOVL_ERR2_P TOVF_ERR2_P
861
862/* TIMERx_CONFIG Registers */
863#define PWM_OUT 0x0001
864#define WDTH_CAP 0x0002
865#define EXT_CLK 0x0003
866#define PULSE_HI 0x0004
867#define PERIOD_CNT 0x0008
868#define IRQ_ENA 0x0010
869#define TIN_SEL 0x0020
870#define OUT_DIS 0x0040
871#define CLK_SEL 0x0080
872#define TOGGLE_HI 0x0100
873#define EMU_RUN 0x0200
874#define ERR_TYP(x) ((x & 0x03) << 14)
875
876#define TMODE_P0 0x00
877#define TMODE_P1 0x01
878#define PULSE_HI_P 0x02
879#define PERIOD_CNT_P 0x03
880#define IRQ_ENA_P 0x04
881#define TIN_SEL_P 0x05
882#define OUT_DIS_P 0x06
883#define CLK_SEL_P 0x07
884#define TOGGLE_HI_P 0x08
885#define EMU_RUN_P 0x09
886#define ERR_TYP_P0 0x0E
887#define ERR_TYP_P1 0x0F
888
889/*/ ****************** PROGRAMMABLE FLAG MASKS ********************* */
890
891/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */
892#define PF0 0x0001
893#define PF1 0x0002
894#define PF2 0x0004
895#define PF3 0x0008
896#define PF4 0x0010
897#define PF5 0x0020
898#define PF6 0x0040
899#define PF7 0x0080
900#define PF8 0x0100
901#define PF9 0x0200
902#define PF10 0x0400
903#define PF11 0x0800
904#define PF12 0x1000
905#define PF13 0x2000
906#define PF14 0x4000
907#define PF15 0x8000
908
909/* General Purpose IO (0xFFC00700 - 0xFFC007FF) BIT POSITIONS */
910#define PF0_P 0
911#define PF1_P 1
912#define PF2_P 2
913#define PF3_P 3
914#define PF4_P 4
915#define PF5_P 5
916#define PF6_P 6
917#define PF7_P 7
918#define PF8_P 8
919#define PF9_P 9
920#define PF10_P 10
921#define PF11_P 11
922#define PF12_P 12
923#define PF13_P 13
924#define PF14_P 14
925#define PF15_P 15
926
927/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS **************** */
928
929/* SPI_CTL Masks */
930#define TIMOD 0x00000003 /* Transfer initiation mode and interrupt generation */
931#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */
932#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */
933#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */
934#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */
935#define SZ 0x00000004 /* Send Zero (=0) or last (=1) word when TDBR empty. */
936#define GM 0x00000008 /* When RDBR full, get more (=1) data or discard (=0) incoming Data */
937#define PSSE 0x00000010 /* Enable (=1) Slave-Select input for Master. */
938#define EMISO 0x00000020 /* Enable (=1) MISO pin as an output. */
939#define SIZE 0x00000100 /* Word length (0 => 8 bits, 1 => 16 bits) */
940#define LSBF 0x00000200 /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */
941#define CPHA 0x00000400 /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */
942#define CPOL 0x00000800 /* Clock polarity (0 => active-high, 1 => active-low) */
943#define MSTR 0x00001000 /* Configures SPI as master (=1) or slave (=0) */
944#define WOM 0x00002000 /* Open drain (=1) data output enable (for MOSI and MISO) */
945#define SPE 0x00004000 /* SPI module enable (=1), disable (=0) */
946
947/* SPI_FLG Masks */
948#define FLS1 0x00000002 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
949#define FLS2 0x00000004 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
950#define FLS3 0x00000008 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
951#define FLS4 0x00000010 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
952#define FLS5 0x00000020 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
953#define FLS6 0x00000040 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
954#define FLS7 0x00000080 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
955#define FLG1 0x00000200 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
956#define FLG2 0x00000400 /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
957#define FLG3 0x00000800 /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
958#define FLG4 0x00001000 /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
959#define FLG5 0x00002000 /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
960#define FLG6 0x00004000 /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
961#define FLG7 0x00008000 /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
962
963/* SPI_FLG Bit Positions */
964#define FLS1_P 0x00000001 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
965#define FLS2_P 0x00000002 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
966#define FLS3_P 0x00000003 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
967#define FLS4_P 0x00000004 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
968#define FLS5_P 0x00000005 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
969#define FLS6_P 0x00000006 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
970#define FLS7_P 0x00000007 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
971#define FLG1_P 0x00000009 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
972#define FLG2_P 0x0000000A /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
973#define FLG3_P 0x0000000B /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
974#define FLG4_P 0x0000000C /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
975#define FLG5_P 0x0000000D /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
976#define FLG6_P 0x0000000E /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
977#define FLG7_P 0x0000000F /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
978
979/* SPI_STAT Masks */
980#define SPIF 0x00000001 /* Set (=1) when SPI single-word transfer complete */
981#define MODF 0x00000002 /* Set (=1) in a master device when some other device tries to become master */
982#define TXE 0x00000004 /* Set (=1) when transmission occurs with no new data in SPI_TDBR */
983#define TXS 0x00000008 /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */
984#define RBSY 0x00000010 /* Set (=1) when data is received with RDBR full */
985#define RXS 0x00000020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */
986#define TXCOL 0x00000040 /* When set (=1), corrupt data may have been transmitted */
987
988/* SPIx_FLG Masks */
989#define FLG1E 0xFDFF /* Activates SPI_FLOUT1 */
990#define FLG2E 0xFBFF /* Activates SPI_FLOUT2 */
991#define FLG3E 0xF7FF /* Activates SPI_FLOUT3 */
992#define FLG4E 0xEFFF /* Activates SPI_FLOUT4 */
993#define FLG5E 0xDFFF /* Activates SPI_FLOUT5 */
994#define FLG6E 0xBFFF /* Activates SPI_FLOUT6 */
995#define FLG7E 0x7FFF /* Activates SPI_FLOUT7 */
996
997/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */
998
999/* AMGCTL Masks */
1000#define AMCKEN 0x00000001 /* Enable CLKOUT */
1001#define AMBEN_NONE 0x00000000 /* All Banks Disabled */
1002#define AMBEN_B0 0x00000002 /* Enable Asynchronous Memory Bank 0 only */
1003#define AMBEN_B0_B1 0x00000004 /* Enable Asynchronous Memory Banks 0 & 1 only */
1004#define AMBEN_B0_B1_B2 0x00000006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */
1005#define AMBEN_ALL 0x00000008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
1006
1007/* AMGCTL Bit Positions */
1008#define AMCKEN_P 0x00000000 /* Enable CLKOUT */
1009#define AMBEN_P0 0x00000001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
1010#define AMBEN_P1 0x00000002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */
1011#define AMBEN_P2 0x00000003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
1012
1013/* AMBCTL0 Masks */
1014#define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */
1015#define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */
1016#define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */
1017#define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */
1018#define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */
1019#define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */
1020#define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
1021#define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
1022#define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
1023#define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
1024#define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
1025#define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
1026#define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
1027#define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
1028#define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */
1029#define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */
1030#define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */
1031#define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */
1032#define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */
1033#define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */
1034#define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */
1035#define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */
1036#define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */
1037#define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */
1038#define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */
1039#define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */
1040#define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */
1041#define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */
1042#define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */
1043#define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */
1044#define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */
1045#define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */
1046#define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */
1047#define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */
1048#define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */
1049#define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */
1050#define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */
1051#define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */
1052#define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */
1053#define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */
1054#define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */
1055#define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */
1056#define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */
1057#define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */
1058#define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */
1059#define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */
1060#define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */
1061#define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */
1062#define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */
1063#define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */
1064#define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
1065#define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
1066#define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
1067#define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
1068#define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
1069#define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
1070#define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
1071#define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
1072#define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */
1073#define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */
1074#define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */
1075#define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */
1076#define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */
1077#define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */
1078#define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */
1079#define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */
1080#define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */
1081#define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */
1082#define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */
1083#define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */
1084#define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */
1085#define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */
1086#define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */
1087#define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */
1088#define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */
1089#define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */
1090#define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */
1091#define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */
1092#define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */
1093#define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */
1094#define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */
1095#define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */
1096#define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */
1097#define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */
1098#define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */
1099#define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */
1100#define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */
1101#define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */
1102
1103/* AMBCTL1 Masks */
1104#define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */
1105#define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */
1106#define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */
1107#define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */
1108#define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */
1109#define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */
1110#define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
1111#define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
1112#define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
1113#define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
1114#define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
1115#define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
1116#define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
1117#define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
1118#define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */
1119#define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */
1120#define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */
1121#define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */
1122#define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */
1123#define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */
1124#define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */
1125#define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */
1126#define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */
1127#define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */
1128#define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */
1129#define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */
1130#define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */
1131#define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */
1132#define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */
1133#define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */
1134#define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */
1135#define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */
1136#define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */
1137#define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */
1138#define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */
1139#define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */
1140#define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */
1141#define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */
1142#define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */
1143#define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */
1144#define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */
1145#define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */
1146#define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */
1147#define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */
1148#define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */
1149#define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */
1150#define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */
1151#define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */
1152#define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */
1153#define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */
1154#define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
1155#define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
1156#define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
1157#define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
1158#define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
1159#define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
1160#define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
1161#define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
1162#define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */
1163#define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */
1164#define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */
1165#define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */
1166#define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */
1167#define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */
1168#define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */
1169#define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */
1170#define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */
1171#define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */
1172#define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */
1173#define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */
1174#define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */
1175#define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */
1176#define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */
1177#define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */
1178#define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */
1179#define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */
1180#define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */
1181#define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */
1182#define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */
1183#define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */
1184#define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */
1185#define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */
1186#define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */
1187#define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */
1188#define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */
1189#define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */
1190#define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */
1191#define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */
1192
1193/* ********************** SDRAM CONTROLLER MASKS *************************** */
1194
1195/* SDGCTL Masks */
1196#define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
1197#define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */
1198#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */
1199#define PFE 0x00000010 /* Enable SDRAM prefetch */
1200#define PFP 0x00000020 /* Prefetch has priority over AMC requests */
1201#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
1202#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
1203#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
1204#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
1205#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
1206#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
1207#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
1208#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
1209#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
1210#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
1211#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
1212#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
1213#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
1214#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
1215#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
1216#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
1217#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
1218#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
1219#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
1220#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
1221#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
1222#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
1223#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
1224#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
1225#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
1226#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
1227#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
1228#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
1229#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
1230#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
1231#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
1232#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
1233#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
1234#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
1235#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
1236#define PUPSD 0x00200000 /*Power-up start delay */
1237#define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
1238#define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */
1239#define SRFS 0x01000000 /* Start SDRAM self-refresh mode */
1240#define EBUFE 0x02000000 /* Enable external buffering timing */
1241#define FBBRW 0x04000000 /* Fast back-to-back read write enable */
1242#define EMREN 0x10000000 /* Extended mode register enable */
1243#define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */
1244#define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */
1245
1246/* EBIU_SDBCTL Masks */
1247#define EBE 0x00000001 /* Enable SDRAM external bank */
1248#define EBSZ_16 0x00000000 /* SDRAM external bank size = 16MB */
1249#define EBSZ_32 0x00000002 /* SDRAM external bank size = 32MB */
1250#define EBSZ_64 0x00000004 /* SDRAM external bank size = 64MB */
1251#define EBSZ_128 0x00000006 /* SDRAM external bank size = 128MB */
1252#define EBCAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
1253#define EBCAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */
1254#define EBCAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */
1255#define EBCAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */
1256
1257/* EBIU_SDSTAT Masks */
1258#define SDCI 0x00000001 /* SDRAM controller is idle */
1259#define SDSRA 0x00000002 /* SDRAM SDRAM self refresh is active */
1260#define SDPUA 0x00000004 /* SDRAM power up active */
1261#define SDRS 0x00000008 /* SDRAM is in reset state */
1262#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */
1263#define BGSTAT 0x00000020 /* Bus granted */
1264
1265
1266#endif /* _DEF_BF532_H */
diff --git a/arch/blackfin/mach-bf533/include/mach/dma.h b/arch/blackfin/mach-bf533/include/mach/dma.h
new file mode 100644
index 000000000000..bd9d5e94307d
--- /dev/null
+++ b/arch/blackfin/mach-bf533/include/mach/dma.h
@@ -0,0 +1,54 @@
1/*****************************************************************************
2*
3* BF-533/2/1 Specific Declarations
4*
5****************************************************************************/
6/*
7 * File: include/asm-blackfin/mach-bf533/dma.h
8 * Based on:
9 * Author:
10 *
11 * Created:
12 * Description:
13 *
14 * Rev:
15 *
16 * Modified:
17 *
18 * Bugs: Enter bugs at http://blackfin.uclinux.org/
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING.
32 * If not, write to the Free Software Foundation,
33 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
34 */
35
36#ifndef _MACH_DMA_H_
37#define _MACH_DMA_H_
38
39#define MAX_BLACKFIN_DMA_CHANNEL 12
40
41#define CH_PPI 0
42#define CH_SPORT0_RX 1
43#define CH_SPORT0_TX 2
44#define CH_SPORT1_RX 3
45#define CH_SPORT1_TX 4
46#define CH_SPI 5
47#define CH_UART_RX 6
48#define CH_UART_TX 7
49#define CH_MEM_STREAM0_DEST 8 /* TX */
50#define CH_MEM_STREAM0_SRC 9 /* RX */
51#define CH_MEM_STREAM1_DEST 10 /* TX */
52#define CH_MEM_STREAM1_SRC 11 /* RX */
53
54#endif
diff --git a/arch/blackfin/mach-bf533/include/mach/irq.h b/arch/blackfin/mach-bf533/include/mach/irq.h
new file mode 100644
index 000000000000..5aa38e5da6b7
--- /dev/null
+++ b/arch/blackfin/mach-bf533/include/mach/irq.h
@@ -0,0 +1,173 @@
1/*
2 * File: include/asm-blackfin/mach-bf533/defBF532.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _BF533_IRQ_H_
32#define _BF533_IRQ_H_
33
34/*
35 * Interrupt source definitions
36 Event Source Core Event Name
37Core Emulation **
38 Events (highest priority) EMU 0
39 Reset RST 1
40 NMI NMI 2
41 Exception EVX 3
42 Reserved -- 4
43 Hardware Error IVHW 5
44 Core Timer IVTMR 6 *
45 PLL Wakeup Interrupt IVG7 7
46 DMA Error (generic) IVG7 8
47 PPI Error Interrupt IVG7 9
48 SPORT0 Error Interrupt IVG7 10
49 SPORT1 Error Interrupt IVG7 11
50 SPI Error Interrupt IVG7 12
51 UART Error Interrupt IVG7 13
52 RTC Interrupt IVG8 14
53 DMA0 Interrupt (PPI) IVG8 15
54 DMA1 (SPORT0 RX) IVG9 16
55 DMA2 (SPORT0 TX) IVG9 17
56 DMA3 (SPORT1 RX) IVG9 18
57 DMA4 (SPORT1 TX) IVG9 19
58 DMA5 (PPI) IVG10 20
59 DMA6 (UART RX) IVG10 21
60 DMA7 (UART TX) IVG10 22
61 Timer0 IVG11 23
62 Timer1 IVG11 24
63 Timer2 IVG11 25
64 PF Interrupt A IVG12 26
65 PF Interrupt B IVG12 27
66 DMA8/9 Interrupt IVG13 28
67 DMA10/11 Interrupt IVG13 29
68 Watchdog Timer IVG13 30
69
70 Softirq IVG14 31
71 System Call --
72 (lowest priority) IVG15 32 *
73 */
74#define SYS_IRQS 31
75#define NR_PERI_INTS 24
76
77/* The ABSTRACT IRQ definitions */
78/** the first seven of the following are fixed, the rest you change if you need to **/
79#define IRQ_EMU 0 /*Emulation */
80#define IRQ_RST 1 /*reset */
81#define IRQ_NMI 2 /*Non Maskable */
82#define IRQ_EVX 3 /*Exception */
83#define IRQ_UNUSED 4 /*- unused interrupt*/
84#define IRQ_HWERR 5 /*Hardware Error */
85#define IRQ_CORETMR 6 /*Core timer */
86
87#define IRQ_PLL_WAKEUP 7 /*PLL Wakeup Interrupt */
88#define IRQ_DMA_ERROR 8 /*DMA Error (general) */
89#define IRQ_PPI_ERROR 9 /*PPI Error Interrupt */
90#define IRQ_SPORT0_ERROR 10 /*SPORT0 Error Interrupt */
91#define IRQ_SPORT1_ERROR 11 /*SPORT1 Error Interrupt */
92#define IRQ_SPI_ERROR 12 /*SPI Error Interrupt */
93#define IRQ_UART_ERROR 13 /*UART Error Interrupt */
94#define IRQ_RTC 14 /*RTC Interrupt */
95#define IRQ_PPI 15 /*DMA0 Interrupt (PPI) */
96#define IRQ_SPORT0_RX 16 /*DMA1 Interrupt (SPORT0 RX) */
97#define IRQ_SPORT0_TX 17 /*DMA2 Interrupt (SPORT0 TX) */
98#define IRQ_SPORT1_RX 18 /*DMA3 Interrupt (SPORT1 RX) */
99#define IRQ_SPORT1_TX 19 /*DMA4 Interrupt (SPORT1 TX) */
100#define IRQ_SPI 20 /*DMA5 Interrupt (SPI) */
101#define IRQ_UART_RX 21 /*DMA6 Interrupt (UART RX) */
102#define IRQ_UART_TX 22 /*DMA7 Interrupt (UART TX) */
103#define IRQ_TMR0 23 /*Timer 0 */
104#define IRQ_TMR1 24 /*Timer 1 */
105#define IRQ_TMR2 25 /*Timer 2 */
106#define IRQ_PROG_INTA 26 /*Programmable Flags A (8) */
107#define IRQ_PROG_INTB 27 /*Programmable Flags B (8) */
108#define IRQ_MEM_DMA0 28 /*DMA8/9 Interrupt (Memory DMA Stream 0) */
109#define IRQ_MEM_DMA1 29 /*DMA10/11 Interrupt (Memory DMA Stream 1) */
110#define IRQ_WATCH 30 /*Watch Dog Timer */
111
112#define IRQ_PF0 33
113#define IRQ_PF1 34
114#define IRQ_PF2 35
115#define IRQ_PF3 36
116#define IRQ_PF4 37
117#define IRQ_PF5 38
118#define IRQ_PF6 39
119#define IRQ_PF7 40
120#define IRQ_PF8 41
121#define IRQ_PF9 42
122#define IRQ_PF10 43
123#define IRQ_PF11 44
124#define IRQ_PF12 45
125#define IRQ_PF13 46
126#define IRQ_PF14 47
127#define IRQ_PF15 48
128
129#define GPIO_IRQ_BASE IRQ_PF0
130
131#define NR_IRQS (IRQ_PF15+1)
132
133#define IVG7 7
134#define IVG8 8
135#define IVG9 9
136#define IVG10 10
137#define IVG11 11
138#define IVG12 12
139#define IVG13 13
140#define IVG14 14
141#define IVG15 15
142
143/* IAR0 BIT FIELDS*/
144#define RTC_ERROR_POS 28
145#define UART_ERROR_POS 24
146#define SPORT1_ERROR_POS 20
147#define SPI_ERROR_POS 16
148#define SPORT0_ERROR_POS 12
149#define PPI_ERROR_POS 8
150#define DMA_ERROR_POS 4
151#define PLLWAKE_ERROR_POS 0
152
153/* IAR1 BIT FIELDS*/
154#define DMA7_UARTTX_POS 28
155#define DMA6_UARTRX_POS 24
156#define DMA5_SPI_POS 20
157#define DMA4_SPORT1TX_POS 16
158#define DMA3_SPORT1RX_POS 12
159#define DMA2_SPORT0TX_POS 8
160#define DMA1_SPORT0RX_POS 4
161#define DMA0_PPI_POS 0
162
163/* IAR2 BIT FIELDS*/
164#define WDTIMER_POS 28
165#define MEMDMA1_POS 24
166#define MEMDMA0_POS 20
167#define PFB_POS 16
168#define PFA_POS 12
169#define TIMER2_POS 8
170#define TIMER1_POS 4
171#define TIMER0_POS 0
172
173#endif /* _BF533_IRQ_H_ */
diff --git a/arch/blackfin/mach-bf533/include/mach/mem_init.h b/arch/blackfin/mach-bf533/include/mach/mem_init.h
new file mode 100644
index 000000000000..ed2034bf10ec
--- /dev/null
+++ b/arch/blackfin/mach-bf533/include/mach/mem_init.h
@@ -0,0 +1,297 @@
1/*
2 * File: include/asm-blackfin/mach-bf533/mem_init.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 * Copyright 2004-2006 Analog Devices Inc.
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || \
33 CONFIG_MEM_MT48LC32M16A2TG_75 || CONFIG_MEM_GENERIC_BOARD)
34#if (CONFIG_SCLK_HZ > 119402985)
35#define SDRAM_tRP TRP_2
36#define SDRAM_tRP_num 2
37#define SDRAM_tRAS TRAS_7
38#define SDRAM_tRAS_num 7
39#define SDRAM_tRCD TRCD_2
40#define SDRAM_tWR TWR_2
41#endif
42#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
43#define SDRAM_tRP TRP_2
44#define SDRAM_tRP_num 2
45#define SDRAM_tRAS TRAS_6
46#define SDRAM_tRAS_num 6
47#define SDRAM_tRCD TRCD_2
48#define SDRAM_tWR TWR_2
49#endif
50#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
51#define SDRAM_tRP TRP_2
52#define SDRAM_tRP_num 2
53#define SDRAM_tRAS TRAS_5
54#define SDRAM_tRAS_num 5
55#define SDRAM_tRCD TRCD_2
56#define SDRAM_tWR TWR_2
57#endif
58#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
59#define SDRAM_tRP TRP_2
60#define SDRAM_tRP_num 2
61#define SDRAM_tRAS TRAS_4
62#define SDRAM_tRAS_num 4
63#define SDRAM_tRCD TRCD_2
64#define SDRAM_tWR TWR_2
65#endif
66#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
67#define SDRAM_tRP TRP_2
68#define SDRAM_tRP_num 2
69#define SDRAM_tRAS TRAS_3
70#define SDRAM_tRAS_num 3
71#define SDRAM_tRCD TRCD_2
72#define SDRAM_tWR TWR_2
73#endif
74#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
75#define SDRAM_tRP TRP_1
76#define SDRAM_tRP_num 1
77#define SDRAM_tRAS TRAS_4
78#define SDRAM_tRAS_num 3
79#define SDRAM_tRCD TRCD_1
80#define SDRAM_tWR TWR_2
81#endif
82#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
83#define SDRAM_tRP TRP_1
84#define SDRAM_tRP_num 1
85#define SDRAM_tRAS TRAS_3
86#define SDRAM_tRAS_num 3
87#define SDRAM_tRCD TRCD_1
88#define SDRAM_tWR TWR_2
89#endif
90#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
91#define SDRAM_tRP TRP_1
92#define SDRAM_tRP_num 1
93#define SDRAM_tRAS TRAS_2
94#define SDRAM_tRAS_num 2
95#define SDRAM_tRCD TRCD_1
96#define SDRAM_tWR TWR_2
97#endif
98#if (CONFIG_SCLK_HZ <= 29850746)
99#define SDRAM_tRP TRP_1
100#define SDRAM_tRP_num 1
101#define SDRAM_tRAS TRAS_1
102#define SDRAM_tRAS_num 1
103#define SDRAM_tRCD TRCD_1
104#define SDRAM_tWR TWR_2
105#endif
106#endif
107
108#if (CONFIG_MEM_MT48LC16M16A2TG_75)
109 /*SDRAM INFORMATION: */
110#define SDRAM_Tref 64 /* Refresh period in milliseconds */
111#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
112#define SDRAM_CL CL_3
113#endif
114
115#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
116 /*SDRAM INFORMATION: */
117#define SDRAM_Tref 64 /* Refresh period in milliseconds */
118#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
119#define SDRAM_CL CL_3
120#endif
121
122#if (CONFIG_MEM_MT48LC32M16A2TG_75)
123 /*SDRAM INFORMATION: */
124#define SDRAM_Tref 64 /* Refresh period in milliseconds */
125#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
126#define SDRAM_CL CL_3
127#endif
128
129#if (CONFIG_MEM_GENERIC_BOARD)
130 /*SDRAM INFORMATION: Modify this for your board */
131#define SDRAM_Tref 64 /* Refresh period in milliseconds */
132#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
133#define SDRAM_CL CL_3
134#endif
135
136/* Equation from section 17 (p17-46) of BF533 HRM */
137#define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
138
139/* Enable SCLK Out */
140#define mem_SDGCTL (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
141
142#if defined CONFIG_CLKIN_HALF
143#define CLKIN_HALF 1
144#else
145#define CLKIN_HALF 0
146#endif
147
148#if defined CONFIG_PLL_BYPASS
149#define PLL_BYPASS 1
150#else
151#define PLL_BYPASS 0
152#endif
153
154/***************************************Currently Not Being Used *********************************/
155#define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
156#define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
157#define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ))
158#define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
159#define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
160
161#if (flash_EBIU_AMBCTL_TT > 3)
162#define flash_EBIU_AMBCTL0_TT B0TT_4
163#endif
164#if (flash_EBIU_AMBCTL_TT == 3)
165#define flash_EBIU_AMBCTL0_TT B0TT_3
166#endif
167#if (flash_EBIU_AMBCTL_TT == 2)
168#define flash_EBIU_AMBCTL0_TT B0TT_2
169#endif
170#if (flash_EBIU_AMBCTL_TT < 2)
171#define flash_EBIU_AMBCTL0_TT B0TT_1
172#endif
173
174#if (flash_EBIU_AMBCTL_ST > 3)
175#define flash_EBIU_AMBCTL0_ST B0ST_4
176#endif
177#if (flash_EBIU_AMBCTL_ST == 3)
178#define flash_EBIU_AMBCTL0_ST B0ST_3
179#endif
180#if (flash_EBIU_AMBCTL_ST == 2)
181#define flash_EBIU_AMBCTL0_ST B0ST_2
182#endif
183#if (flash_EBIU_AMBCTL_ST < 2)
184#define flash_EBIU_AMBCTL0_ST B0ST_1
185#endif
186
187#if (flash_EBIU_AMBCTL_HT > 2)
188#define flash_EBIU_AMBCTL0_HT B0HT_3
189#endif
190#if (flash_EBIU_AMBCTL_HT == 2)
191#define flash_EBIU_AMBCTL0_HT B0HT_2
192#endif
193#if (flash_EBIU_AMBCTL_HT == 1)
194#define flash_EBIU_AMBCTL0_HT B0HT_1
195#endif
196#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
197#define flash_EBIU_AMBCTL0_HT B0HT_0
198#endif
199#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
200#define flash_EBIU_AMBCTL0_HT B0HT_1
201#endif
202
203#if (flash_EBIU_AMBCTL_WAT > 14)
204#define flash_EBIU_AMBCTL0_WAT B0WAT_15
205#endif
206#if (flash_EBIU_AMBCTL_WAT == 14)
207#define flash_EBIU_AMBCTL0_WAT B0WAT_14
208#endif
209#if (flash_EBIU_AMBCTL_WAT == 13)
210#define flash_EBIU_AMBCTL0_WAT B0WAT_13
211#endif
212#if (flash_EBIU_AMBCTL_WAT == 12)
213#define flash_EBIU_AMBCTL0_WAT B0WAT_12
214#endif
215#if (flash_EBIU_AMBCTL_WAT == 11)
216#define flash_EBIU_AMBCTL0_WAT B0WAT_11
217#endif
218#if (flash_EBIU_AMBCTL_WAT == 10)
219#define flash_EBIU_AMBCTL0_WAT B0WAT_10
220#endif
221#if (flash_EBIU_AMBCTL_WAT == 9)
222#define flash_EBIU_AMBCTL0_WAT B0WAT_9
223#endif
224#if (flash_EBIU_AMBCTL_WAT == 8)
225#define flash_EBIU_AMBCTL0_WAT B0WAT_8
226#endif
227#if (flash_EBIU_AMBCTL_WAT == 7)
228#define flash_EBIU_AMBCTL0_WAT B0WAT_7
229#endif
230#if (flash_EBIU_AMBCTL_WAT == 6)
231#define flash_EBIU_AMBCTL0_WAT B0WAT_6
232#endif
233#if (flash_EBIU_AMBCTL_WAT == 5)
234#define flash_EBIU_AMBCTL0_WAT B0WAT_5
235#endif
236#if (flash_EBIU_AMBCTL_WAT == 4)
237#define flash_EBIU_AMBCTL0_WAT B0WAT_4
238#endif
239#if (flash_EBIU_AMBCTL_WAT == 3)
240#define flash_EBIU_AMBCTL0_WAT B0WAT_3
241#endif
242#if (flash_EBIU_AMBCTL_WAT == 2)
243#define flash_EBIU_AMBCTL0_WAT B0WAT_2
244#endif
245#if (flash_EBIU_AMBCTL_WAT == 1)
246#define flash_EBIU_AMBCTL0_WAT B0WAT_1
247#endif
248
249#if (flash_EBIU_AMBCTL_RAT > 14)
250#define flash_EBIU_AMBCTL0_RAT B0RAT_15
251#endif
252#if (flash_EBIU_AMBCTL_RAT == 14)
253#define flash_EBIU_AMBCTL0_RAT B0RAT_14
254#endif
255#if (flash_EBIU_AMBCTL_RAT == 13)
256#define flash_EBIU_AMBCTL0_RAT B0RAT_13
257#endif
258#if (flash_EBIU_AMBCTL_RAT == 12)
259#define flash_EBIU_AMBCTL0_RAT B0RAT_12
260#endif
261#if (flash_EBIU_AMBCTL_RAT == 11)
262#define flash_EBIU_AMBCTL0_RAT B0RAT_11
263#endif
264#if (flash_EBIU_AMBCTL_RAT == 10)
265#define flash_EBIU_AMBCTL0_RAT B0RAT_10
266#endif
267#if (flash_EBIU_AMBCTL_RAT == 9)
268#define flash_EBIU_AMBCTL0_RAT B0RAT_9
269#endif
270#if (flash_EBIU_AMBCTL_RAT == 8)
271#define flash_EBIU_AMBCTL0_RAT B0RAT_8
272#endif
273#if (flash_EBIU_AMBCTL_RAT == 7)
274#define flash_EBIU_AMBCTL0_RAT B0RAT_7
275#endif
276#if (flash_EBIU_AMBCTL_RAT == 6)
277#define flash_EBIU_AMBCTL0_RAT B0RAT_6
278#endif
279#if (flash_EBIU_AMBCTL_RAT == 5)
280#define flash_EBIU_AMBCTL0_RAT B0RAT_5
281#endif
282#if (flash_EBIU_AMBCTL_RAT == 4)
283#define flash_EBIU_AMBCTL0_RAT B0RAT_4
284#endif
285#if (flash_EBIU_AMBCTL_RAT == 3)
286#define flash_EBIU_AMBCTL0_RAT B0RAT_3
287#endif
288#if (flash_EBIU_AMBCTL_RAT == 2)
289#define flash_EBIU_AMBCTL0_RAT B0RAT_2
290#endif
291#if (flash_EBIU_AMBCTL_RAT == 1)
292#define flash_EBIU_AMBCTL0_RAT B0RAT_1
293#endif
294
295#define flash_EBIU_AMBCTL0 \
296 (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
297 flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
diff --git a/arch/blackfin/mach-bf533/include/mach/mem_map.h b/arch/blackfin/mach-bf533/include/mach/mem_map.h
new file mode 100644
index 000000000000..581fc6eea789
--- /dev/null
+++ b/arch/blackfin/mach-bf533/include/mach/mem_map.h
@@ -0,0 +1,171 @@
1/*
2 * File: include/asm-blackfin/mach-bf533/mem_map.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _MEM_MAP_533_H_
32#define _MEM_MAP_533_H_
33
34#define COREMMR_BASE 0xFFE00000 /* Core MMRs */
35#define SYSMMR_BASE 0xFFC00000 /* System MMRs */
36
37/* Async Memory Banks */
38#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */
39#define ASYNC_BANK3_SIZE 0x00100000 /* 1M */
40#define ASYNC_BANK2_BASE 0x20200000 /* Async Bank 2 */
41#define ASYNC_BANK2_SIZE 0x00100000 /* 1M */
42#define ASYNC_BANK1_BASE 0x20100000 /* Async Bank 1 */
43#define ASYNC_BANK1_SIZE 0x00100000 /* 1M */
44#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
45#define ASYNC_BANK0_SIZE 0x00100000 /* 1M */
46
47/* Boot ROM Memory */
48
49#define BOOT_ROM_START 0xEF000000
50#define BOOT_ROM_LENGTH 0x400
51
52/* Level 1 Memory */
53
54#ifdef CONFIG_BFIN_ICACHE
55#define BFIN_ICACHESIZE (16*1024)
56#else
57#define BFIN_ICACHESIZE (0*1024)
58#endif
59
60/* Memory Map for ADSP-BF533 processors */
61
62#ifdef CONFIG_BF533
63#define L1_CODE_START 0xFFA00000
64#define L1_DATA_A_START 0xFF800000
65#define L1_DATA_B_START 0xFF900000
66
67#ifdef CONFIG_BFIN_ICACHE
68#define L1_CODE_LENGTH (0x14000 - 0x4000)
69#else
70#define L1_CODE_LENGTH 0x14000
71#endif
72
73#ifdef CONFIG_BFIN_DCACHE
74
75#ifdef CONFIG_BFIN_DCACHE_BANKA
76#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
77#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
78#define L1_DATA_B_LENGTH 0x8000
79#define BFIN_DCACHESIZE (16*1024)
80#define BFIN_DSUPBANKS 1
81#else
82#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
83#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
84#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
85#define BFIN_DCACHESIZE (32*1024)
86#define BFIN_DSUPBANKS 2
87#endif
88
89#else
90#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
91#define L1_DATA_A_LENGTH 0x8000
92#define L1_DATA_B_LENGTH 0x8000
93#define BFIN_DCACHESIZE (0*1024)
94#define BFIN_DSUPBANKS 0
95#endif /*CONFIG_BFIN_DCACHE*/
96#endif
97
98/* Memory Map for ADSP-BF532 processors */
99
100#ifdef CONFIG_BF532
101#define L1_CODE_START 0xFFA08000
102#define L1_DATA_A_START 0xFF804000
103#define L1_DATA_B_START 0xFF904000
104
105#ifdef CONFIG_BFIN_ICACHE
106#define L1_CODE_LENGTH (0xC000 - 0x4000)
107#else
108#define L1_CODE_LENGTH 0xC000
109#endif
110
111#ifdef CONFIG_BFIN_DCACHE
112
113#ifdef CONFIG_BFIN_DCACHE_BANKA
114#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
115#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
116#define L1_DATA_B_LENGTH 0x4000
117#define BFIN_DCACHESIZE (16*1024)
118#define BFIN_DSUPBANKS 1
119
120#else
121#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
122#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
123#define L1_DATA_B_LENGTH (0x4000 - 0x4000)
124#define BFIN_DCACHESIZE (32*1024)
125#define BFIN_DSUPBANKS 2
126#endif
127
128#else
129#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
130#define L1_DATA_A_LENGTH 0x4000
131#define L1_DATA_B_LENGTH 0x4000
132#define BFIN_DCACHESIZE (0*1024)
133#define BFIN_DSUPBANKS 0
134#endif /*CONFIG_BFIN_DCACHE*/
135#endif
136
137/* Memory Map for ADSP-BF531 processors */
138
139#ifdef CONFIG_BF531
140#define L1_CODE_START 0xFFA08000
141#define L1_DATA_A_START 0xFF804000
142#define L1_DATA_B_START 0xFF904000
143#define L1_CODE_LENGTH 0x4000
144#define L1_DATA_B_LENGTH 0x0000
145
146
147#ifdef CONFIG_BFIN_DCACHE
148#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
149#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
150#define BFIN_DCACHESIZE (16*1024)
151#define BFIN_DSUPBANKS 1
152#else
153#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
154#define L1_DATA_A_LENGTH 0x4000
155#define BFIN_DCACHESIZE (0*1024)
156#define BFIN_DSUPBANKS 0
157#endif
158
159#endif
160
161/* Level 2 Memory - none */
162
163#define L2_START 0
164#define L2_LENGTH 0
165
166/* Scratch Pad Memory */
167
168#define L1_SCRATCH_START 0xFFB00000
169#define L1_SCRATCH_LENGTH 0x1000
170
171#endif /* _MEM_MAP_533_H_ */
diff --git a/arch/blackfin/mach-bf533/include/mach/portmux.h b/arch/blackfin/mach-bf533/include/mach/portmux.h
new file mode 100644
index 000000000000..685a2651dcda
--- /dev/null
+++ b/arch/blackfin/mach-bf533/include/mach/portmux.h
@@ -0,0 +1,67 @@
1#ifndef _MACH_PORTMUX_H_
2#define _MACH_PORTMUX_H_
3
4#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
5
6#define P_PPI0_CLK (P_DONTCARE)
7#define P_PPI0_FS1 (P_DONTCARE)
8#define P_PPI0_FS2 (P_DONTCARE)
9#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PF3))
10#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF4))
11#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF5))
12#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF6))
13#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF7))
14#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF8))
15#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF9))
16#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF10))
17#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF11))
18#define P_PPI0_D0 (P_DONTCARE)
19#define P_PPI0_D1 (P_DONTCARE)
20#define P_PPI0_D2 (P_DONTCARE)
21#define P_PPI0_D3 (P_DONTCARE)
22#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF15))
23#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF14))
24#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF13))
25#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF12))
26
27#define P_SPORT1_TSCLK (P_DONTCARE)
28#define P_SPORT1_RSCLK (P_DONTCARE)
29#define P_SPORT0_TSCLK (P_DONTCARE)
30#define P_SPORT0_RSCLK (P_DONTCARE)
31#define P_UART0_RX (P_DONTCARE)
32#define P_UART0_TX (P_DONTCARE)
33#define P_SPORT1_DRSEC (P_DONTCARE)
34#define P_SPORT1_RFS (P_DONTCARE)
35#define P_SPORT1_DTPRI (P_DONTCARE)
36#define P_SPORT1_DTSEC (P_DONTCARE)
37#define P_SPORT1_TFS (P_DONTCARE)
38#define P_SPORT1_DRPRI (P_DONTCARE)
39#define P_SPORT0_DRSEC (P_DONTCARE)
40#define P_SPORT0_RFS (P_DONTCARE)
41#define P_SPORT0_DTPRI (P_DONTCARE)
42#define P_SPORT0_DTSEC (P_DONTCARE)
43#define P_SPORT0_TFS (P_DONTCARE)
44#define P_SPORT0_DRPRI (P_DONTCARE)
45
46#define P_SPI0_MOSI (P_DONTCARE)
47#define P_SPI0_MISO (P_DONTCARE)
48#define P_SPI0_SCK (P_DONTCARE)
49#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7))
50#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6))
51#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5))
52#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4))
53#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3))
54#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2))
55#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1))
56#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0))
57
58#define P_TMR2 (P_DONTCARE)
59#define P_TMR1 (P_DONTCARE)
60#define P_TMR0 (P_DONTCARE)
61#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF1))
62
63
64
65
66
67#endif /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c
index e93964fdb432..8482d22321f3 100644
--- a/arch/blackfin/mach-bf537/boards/stamp.c
+++ b/arch/blackfin/mach-bf537/boards/stamp.c
@@ -584,6 +584,30 @@ static struct bfin5xx_spi_chip spidev_chip_info = {
584 584
585#if defined(CONFIG_MTD_DATAFLASH) \ 585#if defined(CONFIG_MTD_DATAFLASH) \
586 || defined(CONFIG_MTD_DATAFLASH_MODULE) 586 || defined(CONFIG_MTD_DATAFLASH_MODULE)
587
588static struct mtd_partition bfin_spi_dataflash_partitions[] = {
589 {
590 .name = "bootloader(spi)",
591 .size = 0x00040000,
592 .offset = 0,
593 .mask_flags = MTD_CAP_ROM
594 }, {
595 .name = "linux kernel(spi)",
596 .size = 0xe0000,
597 .offset = MTDPART_OFS_APPEND,
598 }, {
599 .name = "file system(spi)",
600 .size = MTDPART_SIZ_FULL,
601 .offset = MTDPART_OFS_APPEND,
602 }
603};
604
605static struct flash_platform_data bfin_spi_dataflash_data = {
606 .name = "SPI Dataflash",
607 .parts = bfin_spi_dataflash_partitions,
608 .nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions),
609};
610
587/* DataFlash chip */ 611/* DataFlash chip */
588static struct bfin5xx_spi_chip data_flash_chip_info = { 612static struct bfin5xx_spi_chip data_flash_chip_info = {
589 .enable_dma = 0, /* use dma transfer with this chip*/ 613 .enable_dma = 0, /* use dma transfer with this chip*/
@@ -609,9 +633,10 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
609 || defined(CONFIG_MTD_DATAFLASH_MODULE) 633 || defined(CONFIG_MTD_DATAFLASH_MODULE)
610 { /* DataFlash chip */ 634 { /* DataFlash chip */
611 .modalias = "mtd_dataflash", 635 .modalias = "mtd_dataflash",
612 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ 636 .max_speed_hz = 33250000, /* max spi clock (SCK) speed in HZ */
613 .bus_num = 0, /* Framework bus number */ 637 .bus_num = 0, /* Framework bus number */
614 .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/ 638 .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
639 .platform_data = &bfin_spi_dataflash_data,
615 .controller_data = &data_flash_chip_info, 640 .controller_data = &data_flash_chip_info,
616 .mode = SPI_MODE_3, 641 .mode = SPI_MODE_3,
617 }, 642 },
diff --git a/arch/blackfin/mach-bf537/head.S b/arch/blackfin/mach-bf537/head.S
index 64e0287ab266..12eb5cc571d0 100644
--- a/arch/blackfin/mach-bf537/head.S
+++ b/arch/blackfin/mach-bf537/head.S
@@ -31,8 +31,8 @@
31#include <linux/init.h> 31#include <linux/init.h>
32#include <asm/blackfin.h> 32#include <asm/blackfin.h>
33#ifdef CONFIG_BFIN_KERNEL_CLOCK 33#ifdef CONFIG_BFIN_KERNEL_CLOCK
34#include <asm/mach-common/clocks.h> 34#include <asm/clocks.h>
35#include <asm/mach/mem_init.h> 35#include <mach/mem_init.h>
36#endif 36#endif
37 37
38.section .l1.text 38.section .l1.text
diff --git a/arch/blackfin/mach-bf537/include/mach/anomaly.h b/arch/blackfin/mach-bf537/include/mach/anomaly.h
new file mode 100644
index 000000000000..8460ab9c324f
--- /dev/null
+++ b/arch/blackfin/mach-bf537/include/mach/anomaly.h
@@ -0,0 +1,163 @@
1/*
2 * File: include/asm-blackfin/mach-bf537/anomaly.h
3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
4 *
5 * Copyright (C) 2004-2008 Analog Devices Inc.
6 * Licensed under the GPL-2 or later.
7 */
8
9/* This file shoule be up to date with:
10 * - Revision C, 02/08/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
11 */
12
13#ifndef _MACH_ANOMALY_H_
14#define _MACH_ANOMALY_H_
15
16/* We do not support 0.1 silicon - sorry */
17#if __SILICON_REVISION__ < 2
18# error will not work on BF537 silicon version 0.0 or 0.1
19#endif
20
21#if defined(__ADSPBF534__)
22# define ANOMALY_BF534 1
23#else
24# define ANOMALY_BF534 0
25#endif
26#if defined(__ADSPBF536__)
27# define ANOMALY_BF536 1
28#else
29# define ANOMALY_BF536 0
30#endif
31#if defined(__ADSPBF537__)
32# define ANOMALY_BF537 1
33#else
34# define ANOMALY_BF537 0
35#endif
36
37/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */
38#define ANOMALY_05000074 (1)
39/* DMA_RUN bit is not valid after a Peripheral Receive Channel DMA stops */
40#define ANOMALY_05000119 (1)
41/* Rx.H cannot be used to access 16-bit System MMR registers */
42#define ANOMALY_05000122 (1)
43/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */
44#define ANOMALY_05000157 (__SILICON_REVISION__ < 2)
45/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */
46#define ANOMALY_05000167 (1)
47/* PPI_DELAY not functional in PPI modes with 0 frame syncs */
48#define ANOMALY_05000180 (1)
49/* Instruction Cache Is Not Functional */
50#define ANOMALY_05000237 (__SILICON_REVISION__ < 2)
51/* If i-cache is on, CSYNC/SSYNC/IDLE around Change of Control causes failures */
52#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
53/* Spurious Hardware Error from an access in the shadow of a conditional branch */
54#define ANOMALY_05000245 (1)
55/* CLKIN Buffer Output Enable Reset Behavior Is Changed */
56#define ANOMALY_05000247 (1)
57/* Incorrect Bit-Shift of Data Word in Multichannel (TDM) mode in certain conditions */
58#define ANOMALY_05000250 (__SILICON_REVISION__ < 3)
59/* EMAC Tx DMA error after an early frame abort */
60#define ANOMALY_05000252 (__SILICON_REVISION__ < 3)
61/* Maximum external clock speed for Timers */
62#define ANOMALY_05000253 (__SILICON_REVISION__ < 3)
63/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT mode with external clock */
64#define ANOMALY_05000254 (__SILICON_REVISION__ > 2)
65/* Entering Hibernate Mode with RTC Seconds event interrupt not functional */
66#define ANOMALY_05000255 (__SILICON_REVISION__ < 3)
67/* EMAC MDIO input latched on wrong MDC edge */
68#define ANOMALY_05000256 (__SILICON_REVISION__ < 3)
69/* Interrupt/Exception during short hardware loop may cause bad instruction fetches */
70#define ANOMALY_05000257 (__SILICON_REVISION__ < 3)
71/* Instruction Cache is corrupted when bits 9 and 12 of the ICPLB Data registers differ */
72#define ANOMALY_05000258 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ == 1) || __SILICON_REVISION__ == 2)
73/* ICPLB_STATUS MMR register may be corrupted */
74#define ANOMALY_05000260 (__SILICON_REVISION__ == 2)
75/* DCPLB_FAULT_ADDR MMR register may be corrupted */
76#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
77/* Stores to data cache may be lost */
78#define ANOMALY_05000262 (__SILICON_REVISION__ < 3)
79/* Hardware loop corrupted when taking an ICPLB exception */
80#define ANOMALY_05000263 (__SILICON_REVISION__ == 2)
81/* CSYNC/SSYNC/IDLE causes infinite stall in second to last instruction in hardware loop */
82#define ANOMALY_05000264 (__SILICON_REVISION__ < 3)
83/* Sensitivity to noise with slow input edge rates on external SPORT TX and RX clocks */
84#define ANOMALY_05000265 (1)
85/* Memory DMA error when peripheral DMA is running with non-zero DEB_TRAFFIC_PERIOD */
86#define ANOMALY_05000268 (__SILICON_REVISION__ < 3)
87/* High I/O activity causes output voltage of internal voltage regulator (VDDint) to decrease */
88#define ANOMALY_05000270 (__SILICON_REVISION__ < 3)
89/* Certain data cache write through modes fail for VDDint <=0.9V */
90#define ANOMALY_05000272 (1)
91/* Writes to Synchronous SDRAM memory may be lost */
92#define ANOMALY_05000273 (__SILICON_REVISION__ < 3)
93/* Writes to an I/O data register one SCLK cycle after an edge is detected may clear interrupt */
94#define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
95/* Disabling Peripherals with DMA running may cause DMA system instability */
96#define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2))
97/* SPI Master boot mode does not work well with Atmel Data flash devices */
98#define ANOMALY_05000280 (1)
99/* False Hardware Error Exception when ISR context is not restored */
100#define ANOMALY_05000281 (__SILICON_REVISION__ < 3)
101/* Memory DMA corruption with 32-bit data and traffic control */
102#define ANOMALY_05000282 (__SILICON_REVISION__ < 3)
103/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */
104#define ANOMALY_05000283 (__SILICON_REVISION__ < 3)
105/* New Feature: EMAC TX DMA Word Alignment (Not Available On Older Silicon) */
106#define ANOMALY_05000285 (__SILICON_REVISION__ < 3)
107/* SPORTs may receive bad data if FIFOs fill up */
108#define ANOMALY_05000288 (__SILICON_REVISION__ < 3)
109/* Memory to memory DMA source/destination descriptors must be in same memory space */
110#define ANOMALY_05000301 (1)
111/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
112#define ANOMALY_05000304 (__SILICON_REVISION__ < 3)
113/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */
114#define ANOMALY_05000305 (__SILICON_REVISION__ < 3)
115/* SCKELOW Bit Does Not Maintain State Through Hibernate */
116#define ANOMALY_05000307 (__SILICON_REVISION__ < 3)
117/* Writing UART_THR while UART clock is disabled sends erroneous start bit */
118#define ANOMALY_05000309 (__SILICON_REVISION__ < 3)
119/* False hardware errors caused by fetches at the boundary of reserved memory */
120#define ANOMALY_05000310 (1)
121/* Errors when SSYNC, CSYNC, or loads to LT, LB and LC registers are interrupted */
122#define ANOMALY_05000312 (1)
123/* PPI is level sensitive on first transfer */
124#define ANOMALY_05000313 (1)
125/* Killed System MMR Write Completes Erroneously On Next System MMR Access */
126#define ANOMALY_05000315 (__SILICON_REVISION__ < 3)
127/* EMAC RMII mode: collisions occur in Full Duplex mode */
128#define ANOMALY_05000316 (__SILICON_REVISION__ < 3)
129/* EMAC RMII mode: TX frames in half duplex fail with status No Carrier */
130#define ANOMALY_05000321 (__SILICON_REVISION__ < 3)
131/* EMAC RMII mode at 10-Base-T speed: RX frames not received properly */
132#define ANOMALY_05000322 (1)
133/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
134#define ANOMALY_05000341 (__SILICON_REVISION__ >= 3)
135/* New Feature: UART Remains Enabled after UART Boot */
136#define ANOMALY_05000350 (__SILICON_REVISION__ >= 3)
137/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
138#define ANOMALY_05000355 (1)
139/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
140#define ANOMALY_05000357 (1)
141/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
142#define ANOMALY_05000359 (1)
143/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
144#define ANOMALY_05000366 (1)
145/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
146#define ANOMALY_05000371 (1)
147/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
148#define ANOMALY_05000402 (__SILICON_REVISION__ >= 5)
149/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
150#define ANOMALY_05000403 (1)
151
152/* Anomalies that don't exist on this proc */
153#define ANOMALY_05000125 (0)
154#define ANOMALY_05000158 (0)
155#define ANOMALY_05000183 (0)
156#define ANOMALY_05000198 (0)
157#define ANOMALY_05000230 (0)
158#define ANOMALY_05000266 (0)
159#define ANOMALY_05000311 (0)
160#define ANOMALY_05000323 (0)
161#define ANOMALY_05000363 (0)
162
163#endif
diff --git a/arch/blackfin/mach-bf537/include/mach/bf537.h b/arch/blackfin/mach-bf537/include/mach/bf537.h
new file mode 100644
index 000000000000..cfe2a221112e
--- /dev/null
+++ b/arch/blackfin/mach-bf537/include/mach/bf537.h
@@ -0,0 +1,141 @@
1/*
2 * File: include/asm-blackfin/mach-bf537/bf537.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF537
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#ifndef __MACH_BF537_H__
31#define __MACH_BF537_H__
32
33#define SUPPORTED_REVID 2
34
35/* Masks for generic ERROR IRQ demultiplexing used in int-priority-sc.c */
36
37#define SPI_ERR_MASK (TXCOL | RBSY | MODF | TXE) /* SPI_STAT */
38#define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF) /* SPORTx_STAT */
39#define PPI_ERR_MASK (0xFFFF & ~FLD) /* PPI_STATUS */
40#define EMAC_ERR_MASK (PHYINT | MMCINT | RXFSINT | TXFSINT | WAKEDET | RXDMAERR | TXDMAERR | STMDONE) /* EMAC_SYSTAT */
41#define UART_ERR_MASK_STAT1 (0x4) /* UARTx_IIR */
42#define UART_ERR_MASK_STAT0 (0x2) /* UARTx_IIR */
43#define CAN_ERR_MASK (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | RMLIF | UCEIF | EXTIF | ADIF) /* CAN_GIF */
44
45#define OFFSET_(x) ((x) & 0x0000FFFF)
46
47/*some misc defines*/
48#define IMASK_IVG15 0x8000
49#define IMASK_IVG14 0x4000
50#define IMASK_IVG13 0x2000
51#define IMASK_IVG12 0x1000
52
53#define IMASK_IVG11 0x0800
54#define IMASK_IVG10 0x0400
55#define IMASK_IVG9 0x0200
56#define IMASK_IVG8 0x0100
57
58#define IMASK_IVG7 0x0080
59#define IMASK_IVGTMR 0x0040
60#define IMASK_IVGHW 0x0020
61
62/***************************/
63
64
65#define BFIN_DSUBBANKS 4
66#define BFIN_DWAYS 2
67#define BFIN_DLINES 64
68#define BFIN_ISUBBANKS 4
69#define BFIN_IWAYS 4
70#define BFIN_ILINES 32
71
72#define WAY0_L 0x1
73#define WAY1_L 0x2
74#define WAY01_L 0x3
75#define WAY2_L 0x4
76#define WAY02_L 0x5
77#define WAY12_L 0x6
78#define WAY012_L 0x7
79
80#define WAY3_L 0x8
81#define WAY03_L 0x9
82#define WAY13_L 0xA
83#define WAY013_L 0xB
84
85#define WAY32_L 0xC
86#define WAY320_L 0xD
87#define WAY321_L 0xE
88#define WAYALL_L 0xF
89
90#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
91
92/********************************* EBIU Settings ************************************/
93#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
94#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
95
96#ifdef CONFIG_C_AMBEN_ALL
97#define V_AMBEN AMBEN_ALL
98#endif
99#ifdef CONFIG_C_AMBEN
100#define V_AMBEN 0x0
101#endif
102#ifdef CONFIG_C_AMBEN_B0
103#define V_AMBEN AMBEN_B0
104#endif
105#ifdef CONFIG_C_AMBEN_B0_B1
106#define V_AMBEN AMBEN_B0_B1
107#endif
108#ifdef CONFIG_C_AMBEN_B0_B1_B2
109#define V_AMBEN AMBEN_B0_B1_B2
110#endif
111#ifdef CONFIG_C_AMCKEN
112#define V_AMCKEN AMCKEN
113#else
114#define V_AMCKEN 0x0
115#endif
116#ifdef CONFIG_C_CDPRIO
117#define V_CDPRIO 0x100
118#else
119#define V_CDPRIO 0x0
120#endif
121
122#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
123
124#ifdef CONFIG_BF537
125#define CPU "BF537"
126#define CPUID 0x027c8000
127#endif
128#ifdef CONFIG_BF536
129#define CPU "BF536"
130#define CPUID 0x027c8000
131#endif
132#ifdef CONFIG_BF534
133#define CPU "BF534"
134#define CPUID 0x027c6000
135#endif
136#ifndef CPU
137#define CPU "UNKNOWN"
138#define CPUID 0x0
139#endif
140
141#endif /* __MACH_BF537_H__ */
diff --git a/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h
new file mode 100644
index 000000000000..1bf56ffa22f9
--- /dev/null
+++ b/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h
@@ -0,0 +1,195 @@
1/*
2 * file: include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
3 * based on:
4 * author:
5 *
6 * created:
7 * description:
8 * blackfin serial driver header files
9 * rev:
10 *
11 * modified:
12 *
13 *
14 * bugs: enter bugs at http://blackfin.uclinux.org/
15 *
16 * this program is free software; you can redistribute it and/or modify
17 * it under the terms of the gnu general public license as published by
18 * the free software foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * this program is distributed in the hope that it will be useful,
22 * but without any warranty; without even the implied warranty of
23 * merchantability or fitness for a particular purpose. see the
24 * gnu general public license for more details.
25 *
26 * you should have received a copy of the gnu general public license
27 * along with this program; see the file copying.
28 * if not, write to the free software foundation,
29 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
30 */
31
32#include <linux/serial.h>
33#include <asm/dma.h>
34#include <asm/portmux.h>
35
36#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
37#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
38#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
39#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
40#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
41#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
42#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
43
44#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
45#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
46#define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v)
47#define UART_SET_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
48#define UART_CLEAR_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
49#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
50#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
51#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
52
53#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
54#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
55
56#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
57#define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1)
58#define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0)
59#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
60#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
61
62#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
63# define CONFIG_SERIAL_BFIN_CTSRTS
64
65# ifndef CONFIG_UART0_CTS_PIN
66# define CONFIG_UART0_CTS_PIN -1
67# endif
68
69# ifndef CONFIG_UART0_RTS_PIN
70# define CONFIG_UART0_RTS_PIN -1
71# endif
72
73# ifndef CONFIG_UART1_CTS_PIN
74# define CONFIG_UART1_CTS_PIN -1
75# endif
76
77# ifndef CONFIG_UART1_RTS_PIN
78# define CONFIG_UART1_RTS_PIN -1
79# endif
80#endif
81/*
82 * The pin configuration is different from schematic
83 */
84struct bfin_serial_port {
85 struct uart_port port;
86 unsigned int old_status;
87 unsigned int lsr;
88#ifdef CONFIG_SERIAL_BFIN_DMA
89 int tx_done;
90 int tx_count;
91 struct circ_buf rx_dma_buf;
92 struct timer_list rx_dma_timer;
93 int rx_dma_nrows;
94 unsigned int tx_dma_channel;
95 unsigned int rx_dma_channel;
96 struct work_struct tx_dma_workqueue;
97#endif
98#ifdef CONFIG_SERIAL_BFIN_CTSRTS
99 struct timer_list cts_timer;
100 int cts_pin;
101 int rts_pin;
102#endif
103};
104
105/* The hardware clears the LSR bits upon read, so we need to cache
106 * some of the more fun bits in software so they don't get lost
107 * when checking the LSR in other code paths (TX).
108 */
109static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
110{
111 unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
112 uart->lsr |= (lsr & (BI|FE|PE|OE));
113 return lsr | uart->lsr;
114}
115
116static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
117{
118 uart->lsr = 0;
119 bfin_write16(uart->port.membase + OFFSET_LSR, -1);
120}
121
122struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
123struct bfin_serial_res {
124 unsigned long uart_base_addr;
125 int uart_irq;
126#ifdef CONFIG_SERIAL_BFIN_DMA
127 unsigned int uart_tx_dma_channel;
128 unsigned int uart_rx_dma_channel;
129#endif
130#ifdef CONFIG_SERIAL_BFIN_CTSRTS
131 int uart_cts_pin;
132 int uart_rts_pin;
133#endif
134};
135
136struct bfin_serial_res bfin_serial_resource[] = {
137#ifdef CONFIG_SERIAL_BFIN_UART0
138 {
139 0xFFC00400,
140 IRQ_UART0_RX,
141#ifdef CONFIG_SERIAL_BFIN_DMA
142 CH_UART0_TX,
143 CH_UART0_RX,
144#endif
145#ifdef CONFIG_BFIN_UART0_CTSRTS
146 CONFIG_UART0_CTS_PIN,
147 CONFIG_UART0_RTS_PIN,
148#endif
149 },
150#endif
151#ifdef CONFIG_SERIAL_BFIN_UART1
152 {
153 0xFFC02000,
154 IRQ_UART1_RX,
155#ifdef CONFIG_SERIAL_BFIN_DMA
156 CH_UART1_TX,
157 CH_UART1_RX,
158#endif
159#ifdef CONFIG_BFIN_UART1_CTSRTS
160 CONFIG_UART1_CTS_PIN,
161 CONFIG_UART1_RTS_PIN,
162#endif
163 },
164#endif
165};
166
167int nr_ports = ARRAY_SIZE(bfin_serial_resource);
168
169#define DRIVER_NAME "bfin-uart"
170
171static void bfin_serial_hw_init(struct bfin_serial_port *uart)
172{
173
174#ifdef CONFIG_SERIAL_BFIN_UART0
175 peripheral_request(P_UART0_TX, DRIVER_NAME);
176 peripheral_request(P_UART0_RX, DRIVER_NAME);
177#endif
178
179#ifdef CONFIG_SERIAL_BFIN_UART1
180 peripheral_request(P_UART1_TX, DRIVER_NAME);
181 peripheral_request(P_UART1_RX, DRIVER_NAME);
182#endif
183
184#ifdef CONFIG_SERIAL_BFIN_CTSRTS
185 if (uart->cts_pin >= 0) {
186 gpio_request(uart->cts_pin, DRIVER_NAME);
187 gpio_direction_input(uart->cts_pin);
188 }
189
190 if (uart->rts_pin >= 0) {
191 gpio_request(uart->rts_pin, DRIVER_NAME);
192 gpio_direction_output(uart->rts_pin, 0);
193 }
194#endif
195}
diff --git a/arch/blackfin/mach-bf537/include/mach/bfin_sir.h b/arch/blackfin/mach-bf537/include/mach/bfin_sir.h
new file mode 100644
index 000000000000..cfd8ad4f1f2c
--- /dev/null
+++ b/arch/blackfin/mach-bf537/include/mach/bfin_sir.h
@@ -0,0 +1,142 @@
1/*
2 * Blackfin Infra-red Driver
3 *
4 * Copyright 2006-2008 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 *
10 */
11
12#include <linux/serial.h>
13#include <asm/dma.h>
14#include <asm/portmux.h>
15
16#define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR)
17#define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL)
18#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER)
19#define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH)
20#define SIR_UART_GET_IIR(port) bfin_read16((port)->membase + OFFSET_IIR)
21#define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR)
22#define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL)
23
24#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
25#define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v)
26#define SIR_UART_PUT_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER), v)
27#define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v)
28#define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v)
29#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
30
31#ifdef CONFIG_SIR_BFIN_DMA
32struct dma_rx_buf {
33 char *buf;
34 int head;
35 int tail;
36 };
37#endif /* CONFIG_SIR_BFIN_DMA */
38
39struct bfin_sir_port {
40 unsigned char __iomem *membase;
41 unsigned int irq;
42 unsigned int lsr;
43 unsigned long clk;
44 struct net_device *dev;
45#ifdef CONFIG_SIR_BFIN_DMA
46 int tx_done;
47 struct dma_rx_buf rx_dma_buf;
48 struct timer_list rx_dma_timer;
49 int rx_dma_nrows;
50#endif /* CONFIG_SIR_BFIN_DMA */
51 unsigned int tx_dma_channel;
52 unsigned int rx_dma_channel;
53};
54
55struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS];
56
57struct bfin_sir_port_res {
58 unsigned long base_addr;
59 int irq;
60 unsigned int rx_dma_channel;
61 unsigned int tx_dma_channel;
62};
63
64struct bfin_sir_port_res bfin_sir_port_resource[] = {
65#ifdef CONFIG_BFIN_SIR0
66 {
67 0xFFC00400,
68 IRQ_UART0_RX,
69 CH_UART0_RX,
70 CH_UART0_TX,
71 },
72#endif
73#ifdef CONFIG_BFIN_SIR1
74 {
75 0xFFC02000,
76 IRQ_UART1_RX,
77 CH_UART1_RX,
78 CH_UART1_TX,
79 },
80#endif
81};
82
83int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource);
84
85struct bfin_sir_self {
86 struct bfin_sir_port *sir_port;
87 spinlock_t lock;
88 unsigned int open;
89 int speed;
90 int newspeed;
91
92 struct sk_buff *txskb;
93 struct sk_buff *rxskb;
94 struct net_device_stats stats;
95 struct device *dev;
96 struct irlap_cb *irlap;
97 struct qos_info qos;
98
99 iobuff_t tx_buff;
100 iobuff_t rx_buff;
101
102 struct work_struct work;
103 int mtt;
104};
105
106static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port)
107{
108 unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR);
109 port->lsr |= (lsr & (BI|FE|PE|OE));
110 return lsr | port->lsr;
111}
112
113static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port)
114{
115 port->lsr = 0;
116 bfin_read16(port->membase + OFFSET_LSR);
117}
118
119#define DRIVER_NAME "bfin_sir"
120
121static int bfin_sir_hw_init(void)
122{
123 int ret = -ENODEV;
124#ifdef CONFIG_BFIN_SIR0
125 ret = peripheral_request(P_UART0_TX, DRIVER_NAME);
126 if (ret)
127 return ret;
128 ret = peripheral_request(P_UART0_RX, DRIVER_NAME);
129 if (ret)
130 return ret;
131#endif
132
133#ifdef CONFIG_BFIN_SIR1
134 ret = peripheral_request(P_UART1_TX, DRIVER_NAME);
135 if (ret)
136 return ret;
137 ret = peripheral_request(P_UART1_RX, DRIVER_NAME);
138 if (ret)
139 return ret;
140#endif
141 return ret;
142}
diff --git a/arch/blackfin/mach-bf537/include/mach/blackfin.h b/arch/blackfin/mach-bf537/include/mach/blackfin.h
new file mode 100644
index 000000000000..cffc786b2a2b
--- /dev/null
+++ b/arch/blackfin/mach-bf537/include/mach/blackfin.h
@@ -0,0 +1,165 @@
1/*
2 * File: include/asm-blackfin/mach-bf537/blackfin.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#ifndef _MACH_BLACKFIN_H_
33#define _MACH_BLACKFIN_H_
34
35#define BF537_FAMILY
36
37#include "bf537.h"
38#include "mem_map.h"
39#include "defBF534.h"
40#include "anomaly.h"
41
42#if defined(CONFIG_BF537) || defined(CONFIG_BF536)
43#include "defBF537.h"
44#endif
45
46#if !defined(__ASSEMBLY__)
47#include "cdefBF534.h"
48
49/* UART 0*/
50#define bfin_read_UART_THR() bfin_read_UART0_THR()
51#define bfin_write_UART_THR(val) bfin_write_UART0_THR(val)
52#define bfin_read_UART_RBR() bfin_read_UART0_RBR()
53#define bfin_write_UART_RBR(val) bfin_write_UART0_RBR(val)
54#define bfin_read_UART_DLL() bfin_read_UART0_DLL()
55#define bfin_write_UART_DLL(val) bfin_write_UART0_DLL(val)
56#define bfin_read_UART_IER() bfin_read_UART0_IER()
57#define bfin_write_UART_IER(val) bfin_write_UART0_IER(val)
58#define bfin_read_UART_DLH() bfin_read_UART0_DLH()
59#define bfin_write_UART_DLH(val) bfin_write_UART0_DLH(val)
60#define bfin_read_UART_IIR() bfin_read_UART0_IIR()
61#define bfin_write_UART_IIR(val) bfin_write_UART0_IIR(val)
62#define bfin_read_UART_LCR() bfin_read_UART0_LCR()
63#define bfin_write_UART_LCR(val) bfin_write_UART0_LCR(val)
64#define bfin_read_UART_MCR() bfin_read_UART0_MCR()
65#define bfin_write_UART_MCR(val) bfin_write_UART0_MCR(val)
66#define bfin_read_UART_LSR() bfin_read_UART0_LSR()
67#define bfin_write_UART_LSR(val) bfin_write_UART0_LSR(val)
68#define bfin_read_UART_SCR() bfin_read_UART0_SCR()
69#define bfin_write_UART_SCR(val) bfin_write_UART0_SCR(val)
70#define bfin_read_UART_GCTL() bfin_read_UART0_GCTL()
71#define bfin_write_UART_GCTL(val) bfin_write_UART0_GCTL(val)
72
73#if defined(CONFIG_BF537) || defined(CONFIG_BF536)
74#include "cdefBF537.h"
75#endif
76#endif
77
78/* MAP used DEFINES from BF533 to BF537 - so we don't need to change them in the driver, kernel, etc. */
79
80/* UART_IIR Register */
81#define STATUS(x) ((x << 1) & 0x06)
82#define STATUS_P1 0x02
83#define STATUS_P0 0x01
84
85/* DMA Channnel */
86#define bfin_read_CH_UART_RX() bfin_read_CH_UART0_RX()
87#define bfin_write_CH_UART_RX(val) bfin_write_CH_UART0_RX(val)
88#define CH_UART_RX CH_UART0_RX
89#define bfin_read_CH_UART_TX() bfin_read_CH_UART0_TX()
90#define bfin_write_CH_UART_TX(val) bfin_write_CH_UART0_TX(val)
91#define CH_UART_TX CH_UART0_TX
92
93/* System Interrupt Controller */
94#define bfin_read_IRQ_UART_RX() bfin_read_IRQ_UART0_RX()
95#define bfin_write_IRQ_UART_RX(val) bfin_write_IRQ_UART0_RX(val)
96#define IRQ_UART_RX IRQ_UART0_RX
97#define bfin_read_IRQ_UART_TX() bfin_read_IRQ_UART0_TX()
98#define bfin_write_IRQ_UART_TX(val) bfin_write_IRQ_UART0_TX(val)
99#define IRQ_UART_TX IRQ_UART0_TX
100#define bfin_read_IRQ_UART_ERROR() bfin_read_IRQ_UART0_ERROR()
101#define bfin_write_IRQ_UART_ERROR(val) bfin_write_IRQ_UART0_ERROR(val)
102#define IRQ_UART_ERROR IRQ_UART0_ERROR
103
104/* MMR Registers*/
105#define bfin_read_UART_THR() bfin_read_UART0_THR()
106#define bfin_write_UART_THR(val) bfin_write_UART0_THR(val)
107#define BFIN_UART_THR UART0_THR
108#define bfin_read_UART_RBR() bfin_read_UART0_RBR()
109#define bfin_write_UART_RBR(val) bfin_write_UART0_RBR(val)
110#define BFIN_UART_RBR UART0_RBR
111#define bfin_read_UART_DLL() bfin_read_UART0_DLL()
112#define bfin_write_UART_DLL(val) bfin_write_UART0_DLL(val)
113#define BFIN_UART_DLL UART0_DLL
114#define bfin_read_UART_IER() bfin_read_UART0_IER()
115#define bfin_write_UART_IER(val) bfin_write_UART0_IER(val)
116#define BFIN_UART_IER UART0_IER
117#define bfin_read_UART_DLH() bfin_read_UART0_DLH()
118#define bfin_write_UART_DLH(val) bfin_write_UART0_DLH(val)
119#define BFIN_UART_DLH UART0_DLH
120#define bfin_read_UART_IIR() bfin_read_UART0_IIR()
121#define bfin_write_UART_IIR(val) bfin_write_UART0_IIR(val)
122#define BFIN_UART_IIR UART0_IIR
123#define bfin_read_UART_LCR() bfin_read_UART0_LCR()
124#define bfin_write_UART_LCR(val) bfin_write_UART0_LCR(val)
125#define BFIN_UART_LCR UART0_LCR
126#define bfin_read_UART_MCR() bfin_read_UART0_MCR()
127#define bfin_write_UART_MCR(val) bfin_write_UART0_MCR(val)
128#define BFIN_UART_MCR UART0_MCR
129#define bfin_read_UART_LSR() bfin_read_UART0_LSR()
130#define bfin_write_UART_LSR(val) bfin_write_UART0_LSR(val)
131#define BFIN_UART_LSR UART0_LSR
132#define bfin_read_UART_SCR() bfin_read_UART0_SCR()
133#define bfin_write_UART_SCR(val) bfin_write_UART0_SCR(val)
134#define BFIN_UART_SCR UART0_SCR
135#define bfin_read_UART_GCTL() bfin_read_UART0_GCTL()
136#define bfin_write_UART_GCTL(val) bfin_write_UART0_GCTL(val)
137#define BFIN_UART_GCTL UART0_GCTL
138
139#define BFIN_UART_NR_PORTS 2
140
141#define OFFSET_THR 0x00 /* Transmit Holding register */
142#define OFFSET_RBR 0x00 /* Receive Buffer register */
143#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
144#define OFFSET_IER 0x04 /* Interrupt Enable Register */
145#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
146#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
147#define OFFSET_LCR 0x0C /* Line Control Register */
148#define OFFSET_MCR 0x10 /* Modem Control Register */
149#define OFFSET_LSR 0x14 /* Line Status Register */
150#define OFFSET_MSR 0x18 /* Modem Status Register */
151#define OFFSET_SCR 0x1C /* SCR Scratch Register */
152#define OFFSET_GCTL 0x24 /* Global Control Register */
153
154/* DPMC*/
155#define bfin_read_STOPCK_OFF() bfin_read_STOPCK()
156#define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val)
157#define STOPCK_OFF STOPCK
158
159/* PLL_DIV Masks */
160#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */
161#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */
162#define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */
163#define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */
164
165#endif
diff --git a/arch/blackfin/mach-bf537/include/mach/cdefBF534.h b/arch/blackfin/mach-bf537/include/mach/cdefBF534.h
new file mode 100644
index 000000000000..88d491cd9f36
--- /dev/null
+++ b/arch/blackfin/mach-bf537/include/mach/cdefBF534.h
@@ -0,0 +1,1819 @@
1/*
2 * File: include/asm-blackfin/mach-bf537/cdefbf534.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: system mmr register map
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#ifndef _CDEF_BF534_H
33#define _CDEF_BF534_H
34
35#include <asm/blackfin.h>
36
37/* Include all Core registers and bit definitions */
38#include "defBF534.h"
39
40/* Include core specific register pointer definitions */
41#include <asm/cdef_LPBlackfin.h>
42
43#include <asm/system.h>
44
45/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
46#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
47/* Writing to PLL_CTL initiates a PLL relock sequence. */
48static __inline__ void bfin_write_PLL_CTL(unsigned int val)
49{
50 unsigned long flags, iwr;
51
52 if (val == bfin_read_PLL_CTL())
53 return;
54
55 local_irq_save(flags);
56 /* Enable the PLL Wakeup bit in SIC IWR */
57 iwr = bfin_read32(SIC_IWR);
58 /* Only allow PPL Wakeup) */
59 bfin_write32(SIC_IWR, IWR_ENABLE(0));
60
61 bfin_write16(PLL_CTL, val);
62 SSYNC();
63 asm("IDLE;");
64
65 bfin_write32(SIC_IWR, iwr);
66 local_irq_restore(flags);
67}
68#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
69#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
70#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
71/* Writing to VR_CTL initiates a PLL relock sequence. */
72static __inline__ void bfin_write_VR_CTL(unsigned int val)
73{
74 unsigned long flags, iwr;
75
76 if (val == bfin_read_VR_CTL())
77 return;
78
79 local_irq_save(flags);
80 /* Enable the PLL Wakeup bit in SIC IWR */
81 iwr = bfin_read32(SIC_IWR);
82 /* Only allow PPL Wakeup) */
83 bfin_write32(SIC_IWR, IWR_ENABLE(0));
84
85 bfin_write16(VR_CTL, val);
86 SSYNC();
87 asm("IDLE;");
88
89 bfin_write32(SIC_IWR, iwr);
90 local_irq_restore(flags);
91}
92#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
93#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
94#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
95#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val)
96#define bfin_read_CHIPID() bfin_read32(CHIPID)
97
98/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
99#define bfin_read_SWRST() bfin_read16(SWRST)
100#define bfin_write_SWRST(val) bfin_write16(SWRST,val)
101#define bfin_read_SYSCR() bfin_read16(SYSCR)
102#define bfin_write_SYSCR(val) bfin_write16(SYSCR,val)
103#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT)
104#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT,val)
105#define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK)
106#define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK,val)
107#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
108#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val)
109#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
110#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1,val)
111#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
112#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2,val)
113#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
114#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3,val)
115#define bfin_read_SIC_ISR() bfin_read32(SIC_ISR)
116#define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR,val)
117#define bfin_read_SIC_IWR() bfin_read32(SIC_IWR)
118#define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR,val)
119
120/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
121#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
122#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL,val)
123#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
124#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT,val)
125#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
126#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT,val)
127
128/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
129#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
130#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT,val)
131#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
132#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL,val)
133#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
134#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT,val)
135#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
136#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT,val)
137#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
138#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM,val)
139#define bfin_read_RTC_FAST() bfin_read16(RTC_FAST)
140#define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST,val)
141#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
142#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN,val)
143
144/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
145#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
146#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR,val)
147#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
148#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR,val)
149#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
150#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL,val)
151#define bfin_read_UART0_IER() bfin_read16(UART0_IER)
152#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER,val)
153#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
154#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH,val)
155#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR)
156#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR,val)
157#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
158#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR,val)
159#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
160#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR,val)
161#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
162#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR,val)
163#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
164#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR,val)
165#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
166#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR,val)
167#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
168#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL,val)
169
170/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
171#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL)
172#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL,val)
173#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG)
174#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG,val)
175#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT)
176#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT,val)
177#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR)
178#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR,val)
179#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR)
180#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR,val)
181#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD)
182#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD,val)
183#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW)
184#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW,val)
185
186/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
187#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
188#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG,val)
189#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
190#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER,val)
191#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
192#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD,val)
193#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
194#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH,val)
195
196#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
197#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG,val)
198#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
199#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER,val)
200#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
201#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD,val)
202#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
203#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH,val)
204
205#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
206#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG,val)
207#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
208#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER,val)
209#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
210#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD,val)
211#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
212#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH,val)
213
214#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
215#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG,val)
216#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
217#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER,val)
218#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
219#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD,val)
220#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
221#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH,val)
222
223#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
224#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG,val)
225#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
226#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER,val)
227#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
228#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD,val)
229#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
230#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH,val)
231
232#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
233#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG,val)
234#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
235#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER,val)
236#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
237#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD,val)
238#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
239#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH,val)
240
241#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
242#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG,val)
243#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
244#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER,val)
245#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
246#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD,val)
247#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
248#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH,val)
249
250#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
251#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG,val)
252#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
253#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER,val)
254#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
255#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD,val)
256#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
257#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH,val)
258
259#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
260#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE,val)
261#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE)
262#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE,val)
263#define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS)
264#define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS,val)
265
266/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
267#define bfin_read_PORTFIO() bfin_read16(PORTFIO)
268#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO,val)
269#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR)
270#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR,val)
271#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET)
272#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET,val)
273#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE)
274#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE,val)
275#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA)
276#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA,val)
277#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
278#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR,val)
279#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET)
280#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET,val)
281#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
282#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE,val)
283#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB)
284#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB,val)
285#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
286#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR,val)
287#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET)
288#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET,val)
289#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
290#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE,val)
291#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR)
292#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR,val)
293#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR)
294#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR,val)
295#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE)
296#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE,val)
297#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH)
298#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH,val)
299#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN)
300#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN,val)
301
302/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
303#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
304#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1,val)
305#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
306#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2,val)
307#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
308#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV,val)
309#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
310#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV,val)
311#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
312#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX,val)
313#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
314#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX,val)
315#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX)
316#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX,val)
317#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX)
318#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX,val)
319#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX)
320#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX,val)
321#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX)
322#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX,val)
323#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
324#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1,val)
325#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
326#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2,val)
327#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
328#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV,val)
329#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
330#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV,val)
331#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
332#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT,val)
333#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
334#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL,val)
335#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
336#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1,val)
337#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
338#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2,val)
339#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
340#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0,val)
341#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
342#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1,val)
343#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
344#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2,val)
345#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
346#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3,val)
347#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
348#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0,val)
349#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
350#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1,val)
351#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
352#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2,val)
353#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
354#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3,val)
355
356/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
357#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
358#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1,val)
359#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
360#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2,val)
361#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
362#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV,val)
363#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
364#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV,val)
365#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
366#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX,val)
367#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
368#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX,val)
369#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX)
370#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX,val)
371#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX)
372#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX,val)
373#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX)
374#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX,val)
375#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX)
376#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX,val)
377#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
378#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1,val)
379#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
380#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2,val)
381#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
382#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV,val)
383#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
384#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV,val)
385#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
386#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT,val)
387#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
388#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL,val)
389#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
390#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1,val)
391#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
392#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2,val)
393#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
394#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0,val)
395#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
396#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1,val)
397#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
398#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2,val)
399#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
400#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3,val)
401#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
402#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0,val)
403#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
404#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1,val)
405#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
406#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2,val)
407#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
408#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3,val)
409
410/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
411#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
412#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL,val)
413#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
414#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0,val)
415#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
416#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1,val)
417#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
418#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL,val)
419#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
420#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL,val)
421#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
422#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC,val)
423#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
424#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val)
425
426/* DMA Traffic Control Registers */
427#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER)
428#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER,val)
429#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT)
430#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT,val)
431
432/* Alternate deprecated register names (below) provided for backwards code compatibility */
433#define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER)
434#define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER,val)
435#define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT)
436#define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT,val)
437
438/* DMA Controller */
439#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
440#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG,val)
441#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
442#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR,val)
443#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
444#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR,val)
445#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
446#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT,val)
447#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
448#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT,val)
449#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
450#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY,val)
451#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
452#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY,val)
453#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
454#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR,val)
455#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
456#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR,val)
457#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
458#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT,val)
459#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
460#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT,val)
461#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
462#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS,val)
463#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
464#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP,val)
465
466#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
467#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG,val)
468#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
469#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR,val)
470#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
471#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR,val)
472#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
473#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT,val)
474#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
475#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT,val)
476#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
477#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY,val)
478#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
479#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY,val)
480#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
481#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR,val)
482#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
483#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR,val)
484#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
485#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT,val)
486#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
487#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT,val)
488#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
489#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS,val)
490#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
491#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP,val)
492
493#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
494#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG,val)
495#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
496#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR,val)
497#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
498#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR,val)
499#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
500#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT,val)
501#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
502#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT,val)
503#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
504#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY,val)
505#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
506#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY,val)
507#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
508#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR,val)
509#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
510#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR,val)
511#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
512#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT,val)
513#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
514#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT,val)
515#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
516#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS,val)
517#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
518#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP,val)
519
520#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
521#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG,val)
522#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
523#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR,val)
524#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
525#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR,val)
526#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
527#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT,val)
528#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
529#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT,val)
530#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
531#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY,val)
532#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
533#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY,val)
534#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
535#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR,val)
536#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
537#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR,val)
538#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
539#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT,val)
540#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
541#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT,val)
542#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
543#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS,val)
544#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
545#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP,val)
546
547#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
548#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG,val)
549#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
550#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR,val)
551#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
552#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR,val)
553#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
554#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT,val)
555#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
556#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT,val)
557#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
558#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY,val)
559#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
560#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY,val)
561#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
562#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR,val)
563#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
564#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR,val)
565#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
566#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT,val)
567#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
568#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT,val)
569#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
570#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS,val)
571#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
572#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP,val)
573
574#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
575#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG,val)
576#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
577#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR,val)
578#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
579#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR,val)
580#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
581#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT,val)
582#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
583#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT,val)
584#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
585#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY,val)
586#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
587#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY,val)
588#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
589#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR,val)
590#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
591#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR,val)
592#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
593#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT,val)
594#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
595#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT,val)
596#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
597#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS,val)
598#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
599#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP,val)
600
601#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
602#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG,val)
603#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
604#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR,val)
605#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
606#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR,val)
607#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
608#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT,val)
609#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
610#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT,val)
611#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
612#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY,val)
613#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
614#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY,val)
615#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
616#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR,val)
617#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
618#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR,val)
619#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
620#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT,val)
621#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
622#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT,val)
623#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
624#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS,val)
625#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
626#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP,val)
627
628#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
629#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG,val)
630#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
631#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR,val)
632#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
633#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR,val)
634#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
635#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT,val)
636#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
637#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT,val)
638#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
639#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY,val)
640#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
641#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY,val)
642#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
643#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR,val)
644#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
645#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR,val)
646#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
647#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT,val)
648#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
649#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT,val)
650#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
651#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS,val)
652#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
653#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP,val)
654
655#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
656#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG,val)
657#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR)
658#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR,val)
659#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR)
660#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR,val)
661#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
662#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT,val)
663#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
664#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT,val)
665#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
666#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY,val)
667#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
668#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY,val)
669#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR)
670#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR,val)
671#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR)
672#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR,val)
673#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
674#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT,val)
675#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
676#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT,val)
677#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
678#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS,val)
679#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
680#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP,val)
681
682#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
683#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG,val)
684#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR)
685#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR,val)
686#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR)
687#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR,val)
688#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
689#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT,val)
690#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
691#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT,val)
692#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
693#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY,val)
694#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
695#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY,val)
696#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR)
697#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR,val)
698#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR)
699#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR,val)
700#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
701#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT,val)
702#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
703#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT,val)
704#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
705#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS,val)
706#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
707#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP,val)
708
709#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
710#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG,val)
711#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR)
712#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR,val)
713#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR)
714#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR,val)
715#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
716#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT,val)
717#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
718#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT,val)
719#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
720#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY,val)
721#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
722#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY,val)
723#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR)
724#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR,val)
725#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR)
726#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR,val)
727#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
728#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT,val)
729#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
730#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT,val)
731#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
732#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS,val)
733#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
734#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP,val)
735
736#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
737#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG,val)
738#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR)
739#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR,val)
740#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR)
741#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR,val)
742#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
743#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT,val)
744#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
745#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT,val)
746#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
747#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY,val)
748#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
749#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY,val)
750#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR)
751#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR,val)
752#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR)
753#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR,val)
754#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
755#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT,val)
756#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
757#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT,val)
758#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
759#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS,val)
760#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
761#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP,val)
762
763#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
764#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG,val)
765#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
766#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR,val)
767#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
768#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR,val)
769#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
770#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT,val)
771#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
772#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT,val)
773#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
774#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY,val)
775#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
776#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY,val)
777#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
778#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR,val)
779#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
780#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR,val)
781#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
782#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT,val)
783#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
784#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT,val)
785#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
786#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS,val)
787#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
788#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP,val)
789
790#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
791#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG,val)
792#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
793#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR,val)
794#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
795#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR,val)
796#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
797#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT,val)
798#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
799#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT,val)
800#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
801#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY,val)
802#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
803#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY,val)
804#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
805#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR,val)
806#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
807#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR,val)
808#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
809#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT,val)
810#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
811#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT,val)
812#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
813#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS,val)
814#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
815#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP,val)
816
817#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
818#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG,val)
819#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
820#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR,val)
821#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
822#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR,val)
823#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
824#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT,val)
825#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
826#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT,val)
827#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
828#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY,val)
829#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
830#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY,val)
831#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
832#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR,val)
833#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
834#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR,val)
835#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
836#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT,val)
837#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
838#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT,val)
839#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
840#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS,val)
841#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
842#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP,val)
843
844#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
845#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG,val)
846#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
847#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR,val)
848#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
849#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR,val)
850#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
851#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT,val)
852#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
853#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT,val)
854#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
855#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY,val)
856#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
857#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY,val)
858#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
859#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR,val)
860#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
861#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR,val)
862#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
863#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT,val)
864#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
865#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT,val)
866#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
867#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS,val)
868#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
869#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP,val)
870
871/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
872#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
873#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL,val)
874#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
875#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS,val)
876#define bfin_clear_PPI_STATUS() bfin_write_PPI_STATUS(0xFFFF)
877#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
878#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY,val)
879#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
880#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT,val)
881#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
882#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME,val)
883
884/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
885
886/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
887#define bfin_read_PORTGIO() bfin_read16(PORTGIO)
888#define bfin_write_PORTGIO(val) bfin_write16(PORTGIO,val)
889#define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR)
890#define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR,val)
891#define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET)
892#define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET,val)
893#define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE)
894#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE,val)
895#define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA)
896#define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA,val)
897#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR)
898#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR,val)
899#define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET)
900#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET,val)
901#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE)
902#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE,val)
903#define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB)
904#define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB,val)
905#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR)
906#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR,val)
907#define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET)
908#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET,val)
909#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE)
910#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE,val)
911#define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR)
912#define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR,val)
913#define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR)
914#define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR,val)
915#define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE)
916#define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE,val)
917#define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH)
918#define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH,val)
919#define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN)
920#define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN,val)
921
922/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
923#define bfin_read_PORTHIO() bfin_read16(PORTHIO)
924#define bfin_write_PORTHIO(val) bfin_write16(PORTHIO,val)
925#define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR)
926#define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR,val)
927#define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET)
928#define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET,val)
929#define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE)
930#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE,val)
931#define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA)
932#define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA,val)
933#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR)
934#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR,val)
935#define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET)
936#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET,val)
937#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE)
938#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE,val)
939#define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB)
940#define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB,val)
941#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR)
942#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR,val)
943#define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET)
944#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET,val)
945#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE)
946#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE,val)
947#define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR)
948#define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR,val)
949#define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR)
950#define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR,val)
951#define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE)
952#define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE,val)
953#define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH)
954#define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH,val)
955#define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN)
956#define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN,val)
957
958/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
959#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
960#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR,val)
961#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
962#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR,val)
963#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
964#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL,val)
965#define bfin_read_UART1_IER() bfin_read16(UART1_IER)
966#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER,val)
967#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
968#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH,val)
969#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR)
970#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR,val)
971#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
972#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR,val)
973#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
974#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR,val)
975#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
976#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR,val)
977#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR)
978#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR,val)
979#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
980#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR,val)
981#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
982#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL,val)
983
984/* CAN Controller (0xFFC02A00 - 0xFFC02FFF) */
985/* For Mailboxes 0-15 */
986#define bfin_read_CAN_MC1() bfin_read16(CAN_MC1)
987#define bfin_write_CAN_MC1(val) bfin_write16(CAN_MC1,val)
988#define bfin_read_CAN_MD1() bfin_read16(CAN_MD1)
989#define bfin_write_CAN_MD1(val) bfin_write16(CAN_MD1,val)
990#define bfin_read_CAN_TRS1() bfin_read16(CAN_TRS1)
991#define bfin_write_CAN_TRS1(val) bfin_write16(CAN_TRS1,val)
992#define bfin_read_CAN_TRR1() bfin_read16(CAN_TRR1)
993#define bfin_write_CAN_TRR1(val) bfin_write16(CAN_TRR1,val)
994#define bfin_read_CAN_TA1() bfin_read16(CAN_TA1)
995#define bfin_write_CAN_TA1(val) bfin_write16(CAN_TA1,val)
996#define bfin_read_CAN_AA1() bfin_read16(CAN_AA1)
997#define bfin_write_CAN_AA1(val) bfin_write16(CAN_AA1,val)
998#define bfin_read_CAN_RMP1() bfin_read16(CAN_RMP1)
999#define bfin_write_CAN_RMP1(val) bfin_write16(CAN_RMP1,val)
1000#define bfin_read_CAN_RML1() bfin_read16(CAN_RML1)
1001#define bfin_write_CAN_RML1(val) bfin_write16(CAN_RML1,val)
1002#define bfin_read_CAN_MBTIF1() bfin_read16(CAN_MBTIF1)
1003#define bfin_write_CAN_MBTIF1(val) bfin_write16(CAN_MBTIF1,val)
1004#define bfin_read_CAN_MBRIF1() bfin_read16(CAN_MBRIF1)
1005#define bfin_write_CAN_MBRIF1(val) bfin_write16(CAN_MBRIF1,val)
1006#define bfin_read_CAN_MBIM1() bfin_read16(CAN_MBIM1)
1007#define bfin_write_CAN_MBIM1(val) bfin_write16(CAN_MBIM1,val)
1008#define bfin_read_CAN_RFH1() bfin_read16(CAN_RFH1)
1009#define bfin_write_CAN_RFH1(val) bfin_write16(CAN_RFH1,val)
1010#define bfin_read_CAN_OPSS1() bfin_read16(CAN_OPSS1)
1011#define bfin_write_CAN_OPSS1(val) bfin_write16(CAN_OPSS1,val)
1012
1013/* For Mailboxes 16-31 */
1014#define bfin_read_CAN_MC2() bfin_read16(CAN_MC2)
1015#define bfin_write_CAN_MC2(val) bfin_write16(CAN_MC2,val)
1016#define bfin_read_CAN_MD2() bfin_read16(CAN_MD2)
1017#define bfin_write_CAN_MD2(val) bfin_write16(CAN_MD2,val)
1018#define bfin_read_CAN_TRS2() bfin_read16(CAN_TRS2)
1019#define bfin_write_CAN_TRS2(val) bfin_write16(CAN_TRS2,val)
1020#define bfin_read_CAN_TRR2() bfin_read16(CAN_TRR2)
1021#define bfin_write_CAN_TRR2(val) bfin_write16(CAN_TRR2,val)
1022#define bfin_read_CAN_TA2() bfin_read16(CAN_TA2)
1023#define bfin_write_CAN_TA2(val) bfin_write16(CAN_TA2,val)
1024#define bfin_read_CAN_AA2() bfin_read16(CAN_AA2)
1025#define bfin_write_CAN_AA2(val) bfin_write16(CAN_AA2,val)
1026#define bfin_read_CAN_RMP2() bfin_read16(CAN_RMP2)
1027#define bfin_write_CAN_RMP2(val) bfin_write16(CAN_RMP2,val)
1028#define bfin_read_CAN_RML2() bfin_read16(CAN_RML2)
1029#define bfin_write_CAN_RML2(val) bfin_write16(CAN_RML2,val)
1030#define bfin_read_CAN_MBTIF2() bfin_read16(CAN_MBTIF2)
1031#define bfin_write_CAN_MBTIF2(val) bfin_write16(CAN_MBTIF2,val)
1032#define bfin_read_CAN_MBRIF2() bfin_read16(CAN_MBRIF2)
1033#define bfin_write_CAN_MBRIF2(val) bfin_write16(CAN_MBRIF2,val)
1034#define bfin_read_CAN_MBIM2() bfin_read16(CAN_MBIM2)
1035#define bfin_write_CAN_MBIM2(val) bfin_write16(CAN_MBIM2,val)
1036#define bfin_read_CAN_RFH2() bfin_read16(CAN_RFH2)
1037#define bfin_write_CAN_RFH2(val) bfin_write16(CAN_RFH2,val)
1038#define bfin_read_CAN_OPSS2() bfin_read16(CAN_OPSS2)
1039#define bfin_write_CAN_OPSS2(val) bfin_write16(CAN_OPSS2,val)
1040
1041#define bfin_read_CAN_CLOCK() bfin_read16(CAN_CLOCK)
1042#define bfin_write_CAN_CLOCK(val) bfin_write16(CAN_CLOCK,val)
1043#define bfin_read_CAN_TIMING() bfin_read16(CAN_TIMING)
1044#define bfin_write_CAN_TIMING(val) bfin_write16(CAN_TIMING,val)
1045#define bfin_read_CAN_DEBUG() bfin_read16(CAN_DEBUG)
1046#define bfin_write_CAN_DEBUG(val) bfin_write16(CAN_DEBUG,val)
1047#define bfin_read_CAN_STATUS() bfin_read16(CAN_STATUS)
1048#define bfin_write_CAN_STATUS(val) bfin_write16(CAN_STATUS,val)
1049#define bfin_read_CAN_CEC() bfin_read16(CAN_CEC)
1050#define bfin_write_CAN_CEC(val) bfin_write16(CAN_CEC,val)
1051#define bfin_read_CAN_GIS() bfin_read16(CAN_GIS)
1052#define bfin_write_CAN_GIS(val) bfin_write16(CAN_GIS,val)
1053#define bfin_read_CAN_GIM() bfin_read16(CAN_GIM)
1054#define bfin_write_CAN_GIM(val) bfin_write16(CAN_GIM,val)
1055#define bfin_read_CAN_GIF() bfin_read16(CAN_GIF)
1056#define bfin_write_CAN_GIF(val) bfin_write16(CAN_GIF,val)
1057#define bfin_read_CAN_CONTROL() bfin_read16(CAN_CONTROL)
1058#define bfin_write_CAN_CONTROL(val) bfin_write16(CAN_CONTROL,val)
1059#define bfin_read_CAN_INTR() bfin_read16(CAN_INTR)
1060#define bfin_write_CAN_INTR(val) bfin_write16(CAN_INTR,val)
1061#define bfin_read_CAN_SFCMVER() bfin_read16(CAN_SFCMVER)
1062#define bfin_write_CAN_SFCMVER(val) bfin_write16(CAN_SFCMVER,val)
1063#define bfin_read_CAN_MBTD() bfin_read16(CAN_MBTD)
1064#define bfin_write_CAN_MBTD(val) bfin_write16(CAN_MBTD,val)
1065#define bfin_read_CAN_EWR() bfin_read16(CAN_EWR)
1066#define bfin_write_CAN_EWR(val) bfin_write16(CAN_EWR,val)
1067#define bfin_read_CAN_ESR() bfin_read16(CAN_ESR)
1068#define bfin_write_CAN_ESR(val) bfin_write16(CAN_ESR,val)
1069#define bfin_read_CAN_UCREG() bfin_read16(CAN_UCREG)
1070#define bfin_write_CAN_UCREG(val) bfin_write16(CAN_UCREG,val)
1071#define bfin_read_CAN_UCCNT() bfin_read16(CAN_UCCNT)
1072#define bfin_write_CAN_UCCNT(val) bfin_write16(CAN_UCCNT,val)
1073#define bfin_read_CAN_UCRC() bfin_read16(CAN_UCRC)
1074#define bfin_write_CAN_UCRC(val) bfin_write16(CAN_UCRC,val)
1075#define bfin_read_CAN_UCCNF() bfin_read16(CAN_UCCNF)
1076#define bfin_write_CAN_UCCNF(val) bfin_write16(CAN_UCCNF,val)
1077
1078/* Mailbox Acceptance Masks */
1079#define bfin_read_CAN_AM00L() bfin_read16(CAN_AM00L)
1080#define bfin_write_CAN_AM00L(val) bfin_write16(CAN_AM00L,val)
1081#define bfin_read_CAN_AM00H() bfin_read16(CAN_AM00H)
1082#define bfin_write_CAN_AM00H(val) bfin_write16(CAN_AM00H,val)
1083#define bfin_read_CAN_AM01L() bfin_read16(CAN_AM01L)
1084#define bfin_write_CAN_AM01L(val) bfin_write16(CAN_AM01L,val)
1085#define bfin_read_CAN_AM01H() bfin_read16(CAN_AM01H)
1086#define bfin_write_CAN_AM01H(val) bfin_write16(CAN_AM01H,val)
1087#define bfin_read_CAN_AM02L() bfin_read16(CAN_AM02L)
1088#define bfin_write_CAN_AM02L(val) bfin_write16(CAN_AM02L,val)
1089#define bfin_read_CAN_AM02H() bfin_read16(CAN_AM02H)
1090#define bfin_write_CAN_AM02H(val) bfin_write16(CAN_AM02H,val)
1091#define bfin_read_CAN_AM03L() bfin_read16(CAN_AM03L)
1092#define bfin_write_CAN_AM03L(val) bfin_write16(CAN_AM03L,val)
1093#define bfin_read_CAN_AM03H() bfin_read16(CAN_AM03H)
1094#define bfin_write_CAN_AM03H(val) bfin_write16(CAN_AM03H,val)
1095#define bfin_read_CAN_AM04L() bfin_read16(CAN_AM04L)
1096#define bfin_write_CAN_AM04L(val) bfin_write16(CAN_AM04L,val)
1097#define bfin_read_CAN_AM04H() bfin_read16(CAN_AM04H)
1098#define bfin_write_CAN_AM04H(val) bfin_write16(CAN_AM04H,val)
1099#define bfin_read_CAN_AM05L() bfin_read16(CAN_AM05L)
1100#define bfin_write_CAN_AM05L(val) bfin_write16(CAN_AM05L,val)
1101#define bfin_read_CAN_AM05H() bfin_read16(CAN_AM05H)
1102#define bfin_write_CAN_AM05H(val) bfin_write16(CAN_AM05H,val)
1103#define bfin_read_CAN_AM06L() bfin_read16(CAN_AM06L)
1104#define bfin_write_CAN_AM06L(val) bfin_write16(CAN_AM06L,val)
1105#define bfin_read_CAN_AM06H() bfin_read16(CAN_AM06H)
1106#define bfin_write_CAN_AM06H(val) bfin_write16(CAN_AM06H,val)
1107#define bfin_read_CAN_AM07L() bfin_read16(CAN_AM07L)
1108#define bfin_write_CAN_AM07L(val) bfin_write16(CAN_AM07L,val)
1109#define bfin_read_CAN_AM07H() bfin_read16(CAN_AM07H)
1110#define bfin_write_CAN_AM07H(val) bfin_write16(CAN_AM07H,val)
1111#define bfin_read_CAN_AM08L() bfin_read16(CAN_AM08L)
1112#define bfin_write_CAN_AM08L(val) bfin_write16(CAN_AM08L,val)
1113#define bfin_read_CAN_AM08H() bfin_read16(CAN_AM08H)
1114#define bfin_write_CAN_AM08H(val) bfin_write16(CAN_AM08H,val)
1115#define bfin_read_CAN_AM09L() bfin_read16(CAN_AM09L)
1116#define bfin_write_CAN_AM09L(val) bfin_write16(CAN_AM09L,val)
1117#define bfin_read_CAN_AM09H() bfin_read16(CAN_AM09H)
1118#define bfin_write_CAN_AM09H(val) bfin_write16(CAN_AM09H,val)
1119#define bfin_read_CAN_AM10L() bfin_read16(CAN_AM10L)
1120#define bfin_write_CAN_AM10L(val) bfin_write16(CAN_AM10L,val)
1121#define bfin_read_CAN_AM10H() bfin_read16(CAN_AM10H)
1122#define bfin_write_CAN_AM10H(val) bfin_write16(CAN_AM10H,val)
1123#define bfin_read_CAN_AM11L() bfin_read16(CAN_AM11L)
1124#define bfin_write_CAN_AM11L(val) bfin_write16(CAN_AM11L,val)
1125#define bfin_read_CAN_AM11H() bfin_read16(CAN_AM11H)
1126#define bfin_write_CAN_AM11H(val) bfin_write16(CAN_AM11H,val)
1127#define bfin_read_CAN_AM12L() bfin_read16(CAN_AM12L)
1128#define bfin_write_CAN_AM12L(val) bfin_write16(CAN_AM12L,val)
1129#define bfin_read_CAN_AM12H() bfin_read16(CAN_AM12H)
1130#define bfin_write_CAN_AM12H(val) bfin_write16(CAN_AM12H,val)
1131#define bfin_read_CAN_AM13L() bfin_read16(CAN_AM13L)
1132#define bfin_write_CAN_AM13L(val) bfin_write16(CAN_AM13L,val)
1133#define bfin_read_CAN_AM13H() bfin_read16(CAN_AM13H)
1134#define bfin_write_CAN_AM13H(val) bfin_write16(CAN_AM13H,val)
1135#define bfin_read_CAN_AM14L() bfin_read16(CAN_AM14L)
1136#define bfin_write_CAN_AM14L(val) bfin_write16(CAN_AM14L,val)
1137#define bfin_read_CAN_AM14H() bfin_read16(CAN_AM14H)
1138#define bfin_write_CAN_AM14H(val) bfin_write16(CAN_AM14H,val)
1139#define bfin_read_CAN_AM15L() bfin_read16(CAN_AM15L)
1140#define bfin_write_CAN_AM15L(val) bfin_write16(CAN_AM15L,val)
1141#define bfin_read_CAN_AM15H() bfin_read16(CAN_AM15H)
1142#define bfin_write_CAN_AM15H(val) bfin_write16(CAN_AM15H,val)
1143
1144#define bfin_read_CAN_AM16L() bfin_read16(CAN_AM16L)
1145#define bfin_write_CAN_AM16L(val) bfin_write16(CAN_AM16L,val)
1146#define bfin_read_CAN_AM16H() bfin_read16(CAN_AM16H)
1147#define bfin_write_CAN_AM16H(val) bfin_write16(CAN_AM16H,val)
1148#define bfin_read_CAN_AM17L() bfin_read16(CAN_AM17L)
1149#define bfin_write_CAN_AM17L(val) bfin_write16(CAN_AM17L,val)
1150#define bfin_read_CAN_AM17H() bfin_read16(CAN_AM17H)
1151#define bfin_write_CAN_AM17H(val) bfin_write16(CAN_AM17H,val)
1152#define bfin_read_CAN_AM18L() bfin_read16(CAN_AM18L)
1153#define bfin_write_CAN_AM18L(val) bfin_write16(CAN_AM18L,val)
1154#define bfin_read_CAN_AM18H() bfin_read16(CAN_AM18H)
1155#define bfin_write_CAN_AM18H(val) bfin_write16(CAN_AM18H,val)
1156#define bfin_read_CAN_AM19L() bfin_read16(CAN_AM19L)
1157#define bfin_write_CAN_AM19L(val) bfin_write16(CAN_AM19L,val)
1158#define bfin_read_CAN_AM19H() bfin_read16(CAN_AM19H)
1159#define bfin_write_CAN_AM19H(val) bfin_write16(CAN_AM19H,val)
1160#define bfin_read_CAN_AM20L() bfin_read16(CAN_AM20L)
1161#define bfin_write_CAN_AM20L(val) bfin_write16(CAN_AM20L,val)
1162#define bfin_read_CAN_AM20H() bfin_read16(CAN_AM20H)
1163#define bfin_write_CAN_AM20H(val) bfin_write16(CAN_AM20H,val)
1164#define bfin_read_CAN_AM21L() bfin_read16(CAN_AM21L)
1165#define bfin_write_CAN_AM21L(val) bfin_write16(CAN_AM21L,val)
1166#define bfin_read_CAN_AM21H() bfin_read16(CAN_AM21H)
1167#define bfin_write_CAN_AM21H(val) bfin_write16(CAN_AM21H,val)
1168#define bfin_read_CAN_AM22L() bfin_read16(CAN_AM22L)
1169#define bfin_write_CAN_AM22L(val) bfin_write16(CAN_AM22L,val)
1170#define bfin_read_CAN_AM22H() bfin_read16(CAN_AM22H)
1171#define bfin_write_CAN_AM22H(val) bfin_write16(CAN_AM22H,val)
1172#define bfin_read_CAN_AM23L() bfin_read16(CAN_AM23L)
1173#define bfin_write_CAN_AM23L(val) bfin_write16(CAN_AM23L,val)
1174#define bfin_read_CAN_AM23H() bfin_read16(CAN_AM23H)
1175#define bfin_write_CAN_AM23H(val) bfin_write16(CAN_AM23H,val)
1176#define bfin_read_CAN_AM24L() bfin_read16(CAN_AM24L)
1177#define bfin_write_CAN_AM24L(val) bfin_write16(CAN_AM24L,val)
1178#define bfin_read_CAN_AM24H() bfin_read16(CAN_AM24H)
1179#define bfin_write_CAN_AM24H(val) bfin_write16(CAN_AM24H,val)
1180#define bfin_read_CAN_AM25L() bfin_read16(CAN_AM25L)
1181#define bfin_write_CAN_AM25L(val) bfin_write16(CAN_AM25L,val)
1182#define bfin_read_CAN_AM25H() bfin_read16(CAN_AM25H)
1183#define bfin_write_CAN_AM25H(val) bfin_write16(CAN_AM25H,val)
1184#define bfin_read_CAN_AM26L() bfin_read16(CAN_AM26L)
1185#define bfin_write_CAN_AM26L(val) bfin_write16(CAN_AM26L,val)
1186#define bfin_read_CAN_AM26H() bfin_read16(CAN_AM26H)
1187#define bfin_write_CAN_AM26H(val) bfin_write16(CAN_AM26H,val)
1188#define bfin_read_CAN_AM27L() bfin_read16(CAN_AM27L)
1189#define bfin_write_CAN_AM27L(val) bfin_write16(CAN_AM27L,val)
1190#define bfin_read_CAN_AM27H() bfin_read16(CAN_AM27H)
1191#define bfin_write_CAN_AM27H(val) bfin_write16(CAN_AM27H,val)
1192#define bfin_read_CAN_AM28L() bfin_read16(CAN_AM28L)
1193#define bfin_write_CAN_AM28L(val) bfin_write16(CAN_AM28L,val)
1194#define bfin_read_CAN_AM28H() bfin_read16(CAN_AM28H)
1195#define bfin_write_CAN_AM28H(val) bfin_write16(CAN_AM28H,val)
1196#define bfin_read_CAN_AM29L() bfin_read16(CAN_AM29L)
1197#define bfin_write_CAN_AM29L(val) bfin_write16(CAN_AM29L,val)
1198#define bfin_read_CAN_AM29H() bfin_read16(CAN_AM29H)
1199#define bfin_write_CAN_AM29H(val) bfin_write16(CAN_AM29H,val)
1200#define bfin_read_CAN_AM30L() bfin_read16(CAN_AM30L)
1201#define bfin_write_CAN_AM30L(val) bfin_write16(CAN_AM30L,val)
1202#define bfin_read_CAN_AM30H() bfin_read16(CAN_AM30H)
1203#define bfin_write_CAN_AM30H(val) bfin_write16(CAN_AM30H,val)
1204#define bfin_read_CAN_AM31L() bfin_read16(CAN_AM31L)
1205#define bfin_write_CAN_AM31L(val) bfin_write16(CAN_AM31L,val)
1206#define bfin_read_CAN_AM31H() bfin_read16(CAN_AM31H)
1207#define bfin_write_CAN_AM31H(val) bfin_write16(CAN_AM31H,val)
1208
1209/* CAN Acceptance Mask Area Macros */
1210#define bfin_read_CAN_AM_L(x)() bfin_read16(CAN_AM_L(x))
1211#define bfin_write_CAN_AM_L(x)(val) bfin_write16(CAN_AM_L(x),val)
1212#define bfin_read_CAN_AM_H(x)() bfin_read16(CAN_AM_H(x))
1213#define bfin_write_CAN_AM_H(x)(val) bfin_write16(CAN_AM_H(x),val)
1214
1215/* Mailbox Registers */
1216#define bfin_read_CAN_MB00_ID1() bfin_read16(CAN_MB00_ID1)
1217#define bfin_write_CAN_MB00_ID1(val) bfin_write16(CAN_MB00_ID1,val)
1218#define bfin_read_CAN_MB00_ID0() bfin_read16(CAN_MB00_ID0)
1219#define bfin_write_CAN_MB00_ID0(val) bfin_write16(CAN_MB00_ID0,val)
1220#define bfin_read_CAN_MB00_TIMESTAMP() bfin_read16(CAN_MB00_TIMESTAMP)
1221#define bfin_write_CAN_MB00_TIMESTAMP(val) bfin_write16(CAN_MB00_TIMESTAMP,val)
1222#define bfin_read_CAN_MB00_LENGTH() bfin_read16(CAN_MB00_LENGTH)
1223#define bfin_write_CAN_MB00_LENGTH(val) bfin_write16(CAN_MB00_LENGTH,val)
1224#define bfin_read_CAN_MB00_DATA3() bfin_read16(CAN_MB00_DATA3)
1225#define bfin_write_CAN_MB00_DATA3(val) bfin_write16(CAN_MB00_DATA3,val)
1226#define bfin_read_CAN_MB00_DATA2() bfin_read16(CAN_MB00_DATA2)
1227#define bfin_write_CAN_MB00_DATA2(val) bfin_write16(CAN_MB00_DATA2,val)
1228#define bfin_read_CAN_MB00_DATA1() bfin_read16(CAN_MB00_DATA1)
1229#define bfin_write_CAN_MB00_DATA1(val) bfin_write16(CAN_MB00_DATA1,val)
1230#define bfin_read_CAN_MB00_DATA0() bfin_read16(CAN_MB00_DATA0)
1231#define bfin_write_CAN_MB00_DATA0(val) bfin_write16(CAN_MB00_DATA0,val)
1232
1233#define bfin_read_CAN_MB01_ID1() bfin_read16(CAN_MB01_ID1)
1234#define bfin_write_CAN_MB01_ID1(val) bfin_write16(CAN_MB01_ID1,val)
1235#define bfin_read_CAN_MB01_ID0() bfin_read16(CAN_MB01_ID0)
1236#define bfin_write_CAN_MB01_ID0(val) bfin_write16(CAN_MB01_ID0,val)
1237#define bfin_read_CAN_MB01_TIMESTAMP() bfin_read16(CAN_MB01_TIMESTAMP)
1238#define bfin_write_CAN_MB01_TIMESTAMP(val) bfin_write16(CAN_MB01_TIMESTAMP,val)
1239#define bfin_read_CAN_MB01_LENGTH() bfin_read16(CAN_MB01_LENGTH)
1240#define bfin_write_CAN_MB01_LENGTH(val) bfin_write16(CAN_MB01_LENGTH,val)
1241#define bfin_read_CAN_MB01_DATA3() bfin_read16(CAN_MB01_DATA3)
1242#define bfin_write_CAN_MB01_DATA3(val) bfin_write16(CAN_MB01_DATA3,val)
1243#define bfin_read_CAN_MB01_DATA2() bfin_read16(CAN_MB01_DATA2)
1244#define bfin_write_CAN_MB01_DATA2(val) bfin_write16(CAN_MB01_DATA2,val)
1245#define bfin_read_CAN_MB01_DATA1() bfin_read16(CAN_MB01_DATA1)
1246#define bfin_write_CAN_MB01_DATA1(val) bfin_write16(CAN_MB01_DATA1,val)
1247#define bfin_read_CAN_MB01_DATA0() bfin_read16(CAN_MB01_DATA0)
1248#define bfin_write_CAN_MB01_DATA0(val) bfin_write16(CAN_MB01_DATA0,val)
1249
1250#define bfin_read_CAN_MB02_ID1() bfin_read16(CAN_MB02_ID1)
1251#define bfin_write_CAN_MB02_ID1(val) bfin_write16(CAN_MB02_ID1,val)
1252#define bfin_read_CAN_MB02_ID0() bfin_read16(CAN_MB02_ID0)
1253#define bfin_write_CAN_MB02_ID0(val) bfin_write16(CAN_MB02_ID0,val)
1254#define bfin_read_CAN_MB02_TIMESTAMP() bfin_read16(CAN_MB02_TIMESTAMP)
1255#define bfin_write_CAN_MB02_TIMESTAMP(val) bfin_write16(CAN_MB02_TIMESTAMP,val)
1256#define bfin_read_CAN_MB02_LENGTH() bfin_read16(CAN_MB02_LENGTH)
1257#define bfin_write_CAN_MB02_LENGTH(val) bfin_write16(CAN_MB02_LENGTH,val)
1258#define bfin_read_CAN_MB02_DATA3() bfin_read16(CAN_MB02_DATA3)
1259#define bfin_write_CAN_MB02_DATA3(val) bfin_write16(CAN_MB02_DATA3,val)
1260#define bfin_read_CAN_MB02_DATA2() bfin_read16(CAN_MB02_DATA2)
1261#define bfin_write_CAN_MB02_DATA2(val) bfin_write16(CAN_MB02_DATA2,val)
1262#define bfin_read_CAN_MB02_DATA1() bfin_read16(CAN_MB02_DATA1)
1263#define bfin_write_CAN_MB02_DATA1(val) bfin_write16(CAN_MB02_DATA1,val)
1264#define bfin_read_CAN_MB02_DATA0() bfin_read16(CAN_MB02_DATA0)
1265#define bfin_write_CAN_MB02_DATA0(val) bfin_write16(CAN_MB02_DATA0,val)
1266
1267#define bfin_read_CAN_MB03_ID1() bfin_read16(CAN_MB03_ID1)
1268#define bfin_write_CAN_MB03_ID1(val) bfin_write16(CAN_MB03_ID1,val)
1269#define bfin_read_CAN_MB03_ID0() bfin_read16(CAN_MB03_ID0)
1270#define bfin_write_CAN_MB03_ID0(val) bfin_write16(CAN_MB03_ID0,val)
1271#define bfin_read_CAN_MB03_TIMESTAMP() bfin_read16(CAN_MB03_TIMESTAMP)
1272#define bfin_write_CAN_MB03_TIMESTAMP(val) bfin_write16(CAN_MB03_TIMESTAMP,val)
1273#define bfin_read_CAN_MB03_LENGTH() bfin_read16(CAN_MB03_LENGTH)
1274#define bfin_write_CAN_MB03_LENGTH(val) bfin_write16(CAN_MB03_LENGTH,val)
1275#define bfin_read_CAN_MB03_DATA3() bfin_read16(CAN_MB03_DATA3)
1276#define bfin_write_CAN_MB03_DATA3(val) bfin_write16(CAN_MB03_DATA3,val)
1277#define bfin_read_CAN_MB03_DATA2() bfin_read16(CAN_MB03_DATA2)
1278#define bfin_write_CAN_MB03_DATA2(val) bfin_write16(CAN_MB03_DATA2,val)
1279#define bfin_read_CAN_MB03_DATA1() bfin_read16(CAN_MB03_DATA1)
1280#define bfin_write_CAN_MB03_DATA1(val) bfin_write16(CAN_MB03_DATA1,val)
1281#define bfin_read_CAN_MB03_DATA0() bfin_read16(CAN_MB03_DATA0)
1282#define bfin_write_CAN_MB03_DATA0(val) bfin_write16(CAN_MB03_DATA0,val)
1283
1284#define bfin_read_CAN_MB04_ID1() bfin_read16(CAN_MB04_ID1)
1285#define bfin_write_CAN_MB04_ID1(val) bfin_write16(CAN_MB04_ID1,val)
1286#define bfin_read_CAN_MB04_ID0() bfin_read16(CAN_MB04_ID0)
1287#define bfin_write_CAN_MB04_ID0(val) bfin_write16(CAN_MB04_ID0,val)
1288#define bfin_read_CAN_MB04_TIMESTAMP() bfin_read16(CAN_MB04_TIMESTAMP)
1289#define bfin_write_CAN_MB04_TIMESTAMP(val) bfin_write16(CAN_MB04_TIMESTAMP,val)
1290#define bfin_read_CAN_MB04_LENGTH() bfin_read16(CAN_MB04_LENGTH)
1291#define bfin_write_CAN_MB04_LENGTH(val) bfin_write16(CAN_MB04_LENGTH,val)
1292#define bfin_read_CAN_MB04_DATA3() bfin_read16(CAN_MB04_DATA3)
1293#define bfin_write_CAN_MB04_DATA3(val) bfin_write16(CAN_MB04_DATA3,val)
1294#define bfin_read_CAN_MB04_DATA2() bfin_read16(CAN_MB04_DATA2)
1295#define bfin_write_CAN_MB04_DATA2(val) bfin_write16(CAN_MB04_DATA2,val)
1296#define bfin_read_CAN_MB04_DATA1() bfin_read16(CAN_MB04_DATA1)
1297#define bfin_write_CAN_MB04_DATA1(val) bfin_write16(CAN_MB04_DATA1,val)
1298#define bfin_read_CAN_MB04_DATA0() bfin_read16(CAN_MB04_DATA0)
1299#define bfin_write_CAN_MB04_DATA0(val) bfin_write16(CAN_MB04_DATA0,val)
1300
1301#define bfin_read_CAN_MB05_ID1() bfin_read16(CAN_MB05_ID1)
1302#define bfin_write_CAN_MB05_ID1(val) bfin_write16(CAN_MB05_ID1,val)
1303#define bfin_read_CAN_MB05_ID0() bfin_read16(CAN_MB05_ID0)
1304#define bfin_write_CAN_MB05_ID0(val) bfin_write16(CAN_MB05_ID0,val)
1305#define bfin_read_CAN_MB05_TIMESTAMP() bfin_read16(CAN_MB05_TIMESTAMP)
1306#define bfin_write_CAN_MB05_TIMESTAMP(val) bfin_write16(CAN_MB05_TIMESTAMP,val)
1307#define bfin_read_CAN_MB05_LENGTH() bfin_read16(CAN_MB05_LENGTH)
1308#define bfin_write_CAN_MB05_LENGTH(val) bfin_write16(CAN_MB05_LENGTH,val)
1309#define bfin_read_CAN_MB05_DATA3() bfin_read16(CAN_MB05_DATA3)
1310#define bfin_write_CAN_MB05_DATA3(val) bfin_write16(CAN_MB05_DATA3,val)
1311#define bfin_read_CAN_MB05_DATA2() bfin_read16(CAN_MB05_DATA2)
1312#define bfin_write_CAN_MB05_DATA2(val) bfin_write16(CAN_MB05_DATA2,val)
1313#define bfin_read_CAN_MB05_DATA1() bfin_read16(CAN_MB05_DATA1)
1314#define bfin_write_CAN_MB05_DATA1(val) bfin_write16(CAN_MB05_DATA1,val)
1315#define bfin_read_CAN_MB05_DATA0() bfin_read16(CAN_MB05_DATA0)
1316#define bfin_write_CAN_MB05_DATA0(val) bfin_write16(CAN_MB05_DATA0,val)
1317
1318#define bfin_read_CAN_MB06_ID1() bfin_read16(CAN_MB06_ID1)
1319#define bfin_write_CAN_MB06_ID1(val) bfin_write16(CAN_MB06_ID1,val)
1320#define bfin_read_CAN_MB06_ID0() bfin_read16(CAN_MB06_ID0)
1321#define bfin_write_CAN_MB06_ID0(val) bfin_write16(CAN_MB06_ID0,val)
1322#define bfin_read_CAN_MB06_TIMESTAMP() bfin_read16(CAN_MB06_TIMESTAMP)
1323#define bfin_write_CAN_MB06_TIMESTAMP(val) bfin_write16(CAN_MB06_TIMESTAMP,val)
1324#define bfin_read_CAN_MB06_LENGTH() bfin_read16(CAN_MB06_LENGTH)
1325#define bfin_write_CAN_MB06_LENGTH(val) bfin_write16(CAN_MB06_LENGTH,val)
1326#define bfin_read_CAN_MB06_DATA3() bfin_read16(CAN_MB06_DATA3)
1327#define bfin_write_CAN_MB06_DATA3(val) bfin_write16(CAN_MB06_DATA3,val)
1328#define bfin_read_CAN_MB06_DATA2() bfin_read16(CAN_MB06_DATA2)
1329#define bfin_write_CAN_MB06_DATA2(val) bfin_write16(CAN_MB06_DATA2,val)
1330#define bfin_read_CAN_MB06_DATA1() bfin_read16(CAN_MB06_DATA1)
1331#define bfin_write_CAN_MB06_DATA1(val) bfin_write16(CAN_MB06_DATA1,val)
1332#define bfin_read_CAN_MB06_DATA0() bfin_read16(CAN_MB06_DATA0)
1333#define bfin_write_CAN_MB06_DATA0(val) bfin_write16(CAN_MB06_DATA0,val)
1334
1335#define bfin_read_CAN_MB07_ID1() bfin_read16(CAN_MB07_ID1)
1336#define bfin_write_CAN_MB07_ID1(val) bfin_write16(CAN_MB07_ID1,val)
1337#define bfin_read_CAN_MB07_ID0() bfin_read16(CAN_MB07_ID0)
1338#define bfin_write_CAN_MB07_ID0(val) bfin_write16(CAN_MB07_ID0,val)
1339#define bfin_read_CAN_MB07_TIMESTAMP() bfin_read16(CAN_MB07_TIMESTAMP)
1340#define bfin_write_CAN_MB07_TIMESTAMP(val) bfin_write16(CAN_MB07_TIMESTAMP,val)
1341#define bfin_read_CAN_MB07_LENGTH() bfin_read16(CAN_MB07_LENGTH)
1342#define bfin_write_CAN_MB07_LENGTH(val) bfin_write16(CAN_MB07_LENGTH,val)
1343#define bfin_read_CAN_MB07_DATA3() bfin_read16(CAN_MB07_DATA3)
1344#define bfin_write_CAN_MB07_DATA3(val) bfin_write16(CAN_MB07_DATA3,val)
1345#define bfin_read_CAN_MB07_DATA2() bfin_read16(CAN_MB07_DATA2)
1346#define bfin_write_CAN_MB07_DATA2(val) bfin_write16(CAN_MB07_DATA2,val)
1347#define bfin_read_CAN_MB07_DATA1() bfin_read16(CAN_MB07_DATA1)
1348#define bfin_write_CAN_MB07_DATA1(val) bfin_write16(CAN_MB07_DATA1,val)
1349#define bfin_read_CAN_MB07_DATA0() bfin_read16(CAN_MB07_DATA0)
1350#define bfin_write_CAN_MB07_DATA0(val) bfin_write16(CAN_MB07_DATA0,val)
1351
1352#define bfin_read_CAN_MB08_ID1() bfin_read16(CAN_MB08_ID1)
1353#define bfin_write_CAN_MB08_ID1(val) bfin_write16(CAN_MB08_ID1,val)
1354#define bfin_read_CAN_MB08_ID0() bfin_read16(CAN_MB08_ID0)
1355#define bfin_write_CAN_MB08_ID0(val) bfin_write16(CAN_MB08_ID0,val)
1356#define bfin_read_CAN_MB08_TIMESTAMP() bfin_read16(CAN_MB08_TIMESTAMP)
1357#define bfin_write_CAN_MB08_TIMESTAMP(val) bfin_write16(CAN_MB08_TIMESTAMP,val)
1358#define bfin_read_CAN_MB08_LENGTH() bfin_read16(CAN_MB08_LENGTH)
1359#define bfin_write_CAN_MB08_LENGTH(val) bfin_write16(CAN_MB08_LENGTH,val)
1360#define bfin_read_CAN_MB08_DATA3() bfin_read16(CAN_MB08_DATA3)
1361#define bfin_write_CAN_MB08_DATA3(val) bfin_write16(CAN_MB08_DATA3,val)
1362#define bfin_read_CAN_MB08_DATA2() bfin_read16(CAN_MB08_DATA2)
1363#define bfin_write_CAN_MB08_DATA2(val) bfin_write16(CAN_MB08_DATA2,val)
1364#define bfin_read_CAN_MB08_DATA1() bfin_read16(CAN_MB08_DATA1)
1365#define bfin_write_CAN_MB08_DATA1(val) bfin_write16(CAN_MB08_DATA1,val)
1366#define bfin_read_CAN_MB08_DATA0() bfin_read16(CAN_MB08_DATA0)
1367#define bfin_write_CAN_MB08_DATA0(val) bfin_write16(CAN_MB08_DATA0,val)
1368
1369#define bfin_read_CAN_MB09_ID1() bfin_read16(CAN_MB09_ID1)
1370#define bfin_write_CAN_MB09_ID1(val) bfin_write16(CAN_MB09_ID1,val)
1371#define bfin_read_CAN_MB09_ID0() bfin_read16(CAN_MB09_ID0)
1372#define bfin_write_CAN_MB09_ID0(val) bfin_write16(CAN_MB09_ID0,val)
1373#define bfin_read_CAN_MB09_TIMESTAMP() bfin_read16(CAN_MB09_TIMESTAMP)
1374#define bfin_write_CAN_MB09_TIMESTAMP(val) bfin_write16(CAN_MB09_TIMESTAMP,val)
1375#define bfin_read_CAN_MB09_LENGTH() bfin_read16(CAN_MB09_LENGTH)
1376#define bfin_write_CAN_MB09_LENGTH(val) bfin_write16(CAN_MB09_LENGTH,val)
1377#define bfin_read_CAN_MB09_DATA3() bfin_read16(CAN_MB09_DATA3)
1378#define bfin_write_CAN_MB09_DATA3(val) bfin_write16(CAN_MB09_DATA3,val)
1379#define bfin_read_CAN_MB09_DATA2() bfin_read16(CAN_MB09_DATA2)
1380#define bfin_write_CAN_MB09_DATA2(val) bfin_write16(CAN_MB09_DATA2,val)
1381#define bfin_read_CAN_MB09_DATA1() bfin_read16(CAN_MB09_DATA1)
1382#define bfin_write_CAN_MB09_DATA1(val) bfin_write16(CAN_MB09_DATA1,val)
1383#define bfin_read_CAN_MB09_DATA0() bfin_read16(CAN_MB09_DATA0)
1384#define bfin_write_CAN_MB09_DATA0(val) bfin_write16(CAN_MB09_DATA0,val)
1385
1386#define bfin_read_CAN_MB10_ID1() bfin_read16(CAN_MB10_ID1)
1387#define bfin_write_CAN_MB10_ID1(val) bfin_write16(CAN_MB10_ID1,val)
1388#define bfin_read_CAN_MB10_ID0() bfin_read16(CAN_MB10_ID0)
1389#define bfin_write_CAN_MB10_ID0(val) bfin_write16(CAN_MB10_ID0,val)
1390#define bfin_read_CAN_MB10_TIMESTAMP() bfin_read16(CAN_MB10_TIMESTAMP)
1391#define bfin_write_CAN_MB10_TIMESTAMP(val) bfin_write16(CAN_MB10_TIMESTAMP,val)
1392#define bfin_read_CAN_MB10_LENGTH() bfin_read16(CAN_MB10_LENGTH)
1393#define bfin_write_CAN_MB10_LENGTH(val) bfin_write16(CAN_MB10_LENGTH,val)
1394#define bfin_read_CAN_MB10_DATA3() bfin_read16(CAN_MB10_DATA3)
1395#define bfin_write_CAN_MB10_DATA3(val) bfin_write16(CAN_MB10_DATA3,val)
1396#define bfin_read_CAN_MB10_DATA2() bfin_read16(CAN_MB10_DATA2)
1397#define bfin_write_CAN_MB10_DATA2(val) bfin_write16(CAN_MB10_DATA2,val)
1398#define bfin_read_CAN_MB10_DATA1() bfin_read16(CAN_MB10_DATA1)
1399#define bfin_write_CAN_MB10_DATA1(val) bfin_write16(CAN_MB10_DATA1,val)
1400#define bfin_read_CAN_MB10_DATA0() bfin_read16(CAN_MB10_DATA0)
1401#define bfin_write_CAN_MB10_DATA0(val) bfin_write16(CAN_MB10_DATA0,val)
1402
1403#define bfin_read_CAN_MB11_ID1() bfin_read16(CAN_MB11_ID1)
1404#define bfin_write_CAN_MB11_ID1(val) bfin_write16(CAN_MB11_ID1,val)
1405#define bfin_read_CAN_MB11_ID0() bfin_read16(CAN_MB11_ID0)
1406#define bfin_write_CAN_MB11_ID0(val) bfin_write16(CAN_MB11_ID0,val)
1407#define bfin_read_CAN_MB11_TIMESTAMP() bfin_read16(CAN_MB11_TIMESTAMP)
1408#define bfin_write_CAN_MB11_TIMESTAMP(val) bfin_write16(CAN_MB11_TIMESTAMP,val)
1409#define bfin_read_CAN_MB11_LENGTH() bfin_read16(CAN_MB11_LENGTH)
1410#define bfin_write_CAN_MB11_LENGTH(val) bfin_write16(CAN_MB11_LENGTH,val)
1411#define bfin_read_CAN_MB11_DATA3() bfin_read16(CAN_MB11_DATA3)
1412#define bfin_write_CAN_MB11_DATA3(val) bfin_write16(CAN_MB11_DATA3,val)
1413#define bfin_read_CAN_MB11_DATA2() bfin_read16(CAN_MB11_DATA2)
1414#define bfin_write_CAN_MB11_DATA2(val) bfin_write16(CAN_MB11_DATA2,val)
1415#define bfin_read_CAN_MB11_DATA1() bfin_read16(CAN_MB11_DATA1)
1416#define bfin_write_CAN_MB11_DATA1(val) bfin_write16(CAN_MB11_DATA1,val)
1417#define bfin_read_CAN_MB11_DATA0() bfin_read16(CAN_MB11_DATA0)
1418#define bfin_write_CAN_MB11_DATA0(val) bfin_write16(CAN_MB11_DATA0,val)
1419
1420#define bfin_read_CAN_MB12_ID1() bfin_read16(CAN_MB12_ID1)
1421#define bfin_write_CAN_MB12_ID1(val) bfin_write16(CAN_MB12_ID1,val)
1422#define bfin_read_CAN_MB12_ID0() bfin_read16(CAN_MB12_ID0)
1423#define bfin_write_CAN_MB12_ID0(val) bfin_write16(CAN_MB12_ID0,val)
1424#define bfin_read_CAN_MB12_TIMESTAMP() bfin_read16(CAN_MB12_TIMESTAMP)
1425#define bfin_write_CAN_MB12_TIMESTAMP(val) bfin_write16(CAN_MB12_TIMESTAMP,val)
1426#define bfin_read_CAN_MB12_LENGTH() bfin_read16(CAN_MB12_LENGTH)
1427#define bfin_write_CAN_MB12_LENGTH(val) bfin_write16(CAN_MB12_LENGTH,val)
1428#define bfin_read_CAN_MB12_DATA3() bfin_read16(CAN_MB12_DATA3)
1429#define bfin_write_CAN_MB12_DATA3(val) bfin_write16(CAN_MB12_DATA3,val)
1430#define bfin_read_CAN_MB12_DATA2() bfin_read16(CAN_MB12_DATA2)
1431#define bfin_write_CAN_MB12_DATA2(val) bfin_write16(CAN_MB12_DATA2,val)
1432#define bfin_read_CAN_MB12_DATA1() bfin_read16(CAN_MB12_DATA1)
1433#define bfin_write_CAN_MB12_DATA1(val) bfin_write16(CAN_MB12_DATA1,val)
1434#define bfin_read_CAN_MB12_DATA0() bfin_read16(CAN_MB12_DATA0)
1435#define bfin_write_CAN_MB12_DATA0(val) bfin_write16(CAN_MB12_DATA0,val)
1436
1437#define bfin_read_CAN_MB13_ID1() bfin_read16(CAN_MB13_ID1)
1438#define bfin_write_CAN_MB13_ID1(val) bfin_write16(CAN_MB13_ID1,val)
1439#define bfin_read_CAN_MB13_ID0() bfin_read16(CAN_MB13_ID0)
1440#define bfin_write_CAN_MB13_ID0(val) bfin_write16(CAN_MB13_ID0,val)
1441#define bfin_read_CAN_MB13_TIMESTAMP() bfin_read16(CAN_MB13_TIMESTAMP)
1442#define bfin_write_CAN_MB13_TIMESTAMP(val) bfin_write16(CAN_MB13_TIMESTAMP,val)
1443#define bfin_read_CAN_MB13_LENGTH() bfin_read16(CAN_MB13_LENGTH)
1444#define bfin_write_CAN_MB13_LENGTH(val) bfin_write16(CAN_MB13_LENGTH,val)
1445#define bfin_read_CAN_MB13_DATA3() bfin_read16(CAN_MB13_DATA3)
1446#define bfin_write_CAN_MB13_DATA3(val) bfin_write16(CAN_MB13_DATA3,val)
1447#define bfin_read_CAN_MB13_DATA2() bfin_read16(CAN_MB13_DATA2)
1448#define bfin_write_CAN_MB13_DATA2(val) bfin_write16(CAN_MB13_DATA2,val)
1449#define bfin_read_CAN_MB13_DATA1() bfin_read16(CAN_MB13_DATA1)
1450#define bfin_write_CAN_MB13_DATA1(val) bfin_write16(CAN_MB13_DATA1,val)
1451#define bfin_read_CAN_MB13_DATA0() bfin_read16(CAN_MB13_DATA0)
1452#define bfin_write_CAN_MB13_DATA0(val) bfin_write16(CAN_MB13_DATA0,val)
1453
1454#define bfin_read_CAN_MB14_ID1() bfin_read16(CAN_MB14_ID1)
1455#define bfin_write_CAN_MB14_ID1(val) bfin_write16(CAN_MB14_ID1,val)
1456#define bfin_read_CAN_MB14_ID0() bfin_read16(CAN_MB14_ID0)
1457#define bfin_write_CAN_MB14_ID0(val) bfin_write16(CAN_MB14_ID0,val)
1458#define bfin_read_CAN_MB14_TIMESTAMP() bfin_read16(CAN_MB14_TIMESTAMP)
1459#define bfin_write_CAN_MB14_TIMESTAMP(val) bfin_write16(CAN_MB14_TIMESTAMP,val)
1460#define bfin_read_CAN_MB14_LENGTH() bfin_read16(CAN_MB14_LENGTH)
1461#define bfin_write_CAN_MB14_LENGTH(val) bfin_write16(CAN_MB14_LENGTH,val)
1462#define bfin_read_CAN_MB14_DATA3() bfin_read16(CAN_MB14_DATA3)
1463#define bfin_write_CAN_MB14_DATA3(val) bfin_write16(CAN_MB14_DATA3,val)
1464#define bfin_read_CAN_MB14_DATA2() bfin_read16(CAN_MB14_DATA2)
1465#define bfin_write_CAN_MB14_DATA2(val) bfin_write16(CAN_MB14_DATA2,val)
1466#define bfin_read_CAN_MB14_DATA1() bfin_read16(CAN_MB14_DATA1)
1467#define bfin_write_CAN_MB14_DATA1(val) bfin_write16(CAN_MB14_DATA1,val)
1468#define bfin_read_CAN_MB14_DATA0() bfin_read16(CAN_MB14_DATA0)
1469#define bfin_write_CAN_MB14_DATA0(val) bfin_write16(CAN_MB14_DATA0,val)
1470
1471#define bfin_read_CAN_MB15_ID1() bfin_read16(CAN_MB15_ID1)
1472#define bfin_write_CAN_MB15_ID1(val) bfin_write16(CAN_MB15_ID1,val)
1473#define bfin_read_CAN_MB15_ID0() bfin_read16(CAN_MB15_ID0)
1474#define bfin_write_CAN_MB15_ID0(val) bfin_write16(CAN_MB15_ID0,val)
1475#define bfin_read_CAN_MB15_TIMESTAMP() bfin_read16(CAN_MB15_TIMESTAMP)
1476#define bfin_write_CAN_MB15_TIMESTAMP(val) bfin_write16(CAN_MB15_TIMESTAMP,val)
1477#define bfin_read_CAN_MB15_LENGTH() bfin_read16(CAN_MB15_LENGTH)
1478#define bfin_write_CAN_MB15_LENGTH(val) bfin_write16(CAN_MB15_LENGTH,val)
1479#define bfin_read_CAN_MB15_DATA3() bfin_read16(CAN_MB15_DATA3)
1480#define bfin_write_CAN_MB15_DATA3(val) bfin_write16(CAN_MB15_DATA3,val)
1481#define bfin_read_CAN_MB15_DATA2() bfin_read16(CAN_MB15_DATA2)
1482#define bfin_write_CAN_MB15_DATA2(val) bfin_write16(CAN_MB15_DATA2,val)
1483#define bfin_read_CAN_MB15_DATA1() bfin_read16(CAN_MB15_DATA1)
1484#define bfin_write_CAN_MB15_DATA1(val) bfin_write16(CAN_MB15_DATA1,val)
1485#define bfin_read_CAN_MB15_DATA0() bfin_read16(CAN_MB15_DATA0)
1486#define bfin_write_CAN_MB15_DATA0(val) bfin_write16(CAN_MB15_DATA0,val)
1487
1488#define bfin_read_CAN_MB16_ID1() bfin_read16(CAN_MB16_ID1)
1489#define bfin_write_CAN_MB16_ID1(val) bfin_write16(CAN_MB16_ID1,val)
1490#define bfin_read_CAN_MB16_ID0() bfin_read16(CAN_MB16_ID0)
1491#define bfin_write_CAN_MB16_ID0(val) bfin_write16(CAN_MB16_ID0,val)
1492#define bfin_read_CAN_MB16_TIMESTAMP() bfin_read16(CAN_MB16_TIMESTAMP)
1493#define bfin_write_CAN_MB16_TIMESTAMP(val) bfin_write16(CAN_MB16_TIMESTAMP,val)
1494#define bfin_read_CAN_MB16_LENGTH() bfin_read16(CAN_MB16_LENGTH)
1495#define bfin_write_CAN_MB16_LENGTH(val) bfin_write16(CAN_MB16_LENGTH,val)
1496#define bfin_read_CAN_MB16_DATA3() bfin_read16(CAN_MB16_DATA3)
1497#define bfin_write_CAN_MB16_DATA3(val) bfin_write16(CAN_MB16_DATA3,val)
1498#define bfin_read_CAN_MB16_DATA2() bfin_read16(CAN_MB16_DATA2)
1499#define bfin_write_CAN_MB16_DATA2(val) bfin_write16(CAN_MB16_DATA2,val)
1500#define bfin_read_CAN_MB16_DATA1() bfin_read16(CAN_MB16_DATA1)
1501#define bfin_write_CAN_MB16_DATA1(val) bfin_write16(CAN_MB16_DATA1,val)
1502#define bfin_read_CAN_MB16_DATA0() bfin_read16(CAN_MB16_DATA0)
1503#define bfin_write_CAN_MB16_DATA0(val) bfin_write16(CAN_MB16_DATA0,val)
1504
1505#define bfin_read_CAN_MB17_ID1() bfin_read16(CAN_MB17_ID1)
1506#define bfin_write_CAN_MB17_ID1(val) bfin_write16(CAN_MB17_ID1,val)
1507#define bfin_read_CAN_MB17_ID0() bfin_read16(CAN_MB17_ID0)
1508#define bfin_write_CAN_MB17_ID0(val) bfin_write16(CAN_MB17_ID0,val)
1509#define bfin_read_CAN_MB17_TIMESTAMP() bfin_read16(CAN_MB17_TIMESTAMP)
1510#define bfin_write_CAN_MB17_TIMESTAMP(val) bfin_write16(CAN_MB17_TIMESTAMP,val)
1511#define bfin_read_CAN_MB17_LENGTH() bfin_read16(CAN_MB17_LENGTH)
1512#define bfin_write_CAN_MB17_LENGTH(val) bfin_write16(CAN_MB17_LENGTH,val)
1513#define bfin_read_CAN_MB17_DATA3() bfin_read16(CAN_MB17_DATA3)
1514#define bfin_write_CAN_MB17_DATA3(val) bfin_write16(CAN_MB17_DATA3,val)
1515#define bfin_read_CAN_MB17_DATA2() bfin_read16(CAN_MB17_DATA2)
1516#define bfin_write_CAN_MB17_DATA2(val) bfin_write16(CAN_MB17_DATA2,val)
1517#define bfin_read_CAN_MB17_DATA1() bfin_read16(CAN_MB17_DATA1)
1518#define bfin_write_CAN_MB17_DATA1(val) bfin_write16(CAN_MB17_DATA1,val)
1519#define bfin_read_CAN_MB17_DATA0() bfin_read16(CAN_MB17_DATA0)
1520#define bfin_write_CAN_MB17_DATA0(val) bfin_write16(CAN_MB17_DATA0,val)
1521
1522#define bfin_read_CAN_MB18_ID1() bfin_read16(CAN_MB18_ID1)
1523#define bfin_write_CAN_MB18_ID1(val) bfin_write16(CAN_MB18_ID1,val)
1524#define bfin_read_CAN_MB18_ID0() bfin_read16(CAN_MB18_ID0)
1525#define bfin_write_CAN_MB18_ID0(val) bfin_write16(CAN_MB18_ID0,val)
1526#define bfin_read_CAN_MB18_TIMESTAMP() bfin_read16(CAN_MB18_TIMESTAMP)
1527#define bfin_write_CAN_MB18_TIMESTAMP(val) bfin_write16(CAN_MB18_TIMESTAMP,val)
1528#define bfin_read_CAN_MB18_LENGTH() bfin_read16(CAN_MB18_LENGTH)
1529#define bfin_write_CAN_MB18_LENGTH(val) bfin_write16(CAN_MB18_LENGTH,val)
1530#define bfin_read_CAN_MB18_DATA3() bfin_read16(CAN_MB18_DATA3)
1531#define bfin_write_CAN_MB18_DATA3(val) bfin_write16(CAN_MB18_DATA3,val)
1532#define bfin_read_CAN_MB18_DATA2() bfin_read16(CAN_MB18_DATA2)
1533#define bfin_write_CAN_MB18_DATA2(val) bfin_write16(CAN_MB18_DATA2,val)
1534#define bfin_read_CAN_MB18_DATA1() bfin_read16(CAN_MB18_DATA1)
1535#define bfin_write_CAN_MB18_DATA1(val) bfin_write16(CAN_MB18_DATA1,val)
1536#define bfin_read_CAN_MB18_DATA0() bfin_read16(CAN_MB18_DATA0)
1537#define bfin_write_CAN_MB18_DATA0(val) bfin_write16(CAN_MB18_DATA0,val)
1538
1539#define bfin_read_CAN_MB19_ID1() bfin_read16(CAN_MB19_ID1)
1540#define bfin_write_CAN_MB19_ID1(val) bfin_write16(CAN_MB19_ID1,val)
1541#define bfin_read_CAN_MB19_ID0() bfin_read16(CAN_MB19_ID0)
1542#define bfin_write_CAN_MB19_ID0(val) bfin_write16(CAN_MB19_ID0,val)
1543#define bfin_read_CAN_MB19_TIMESTAMP() bfin_read16(CAN_MB19_TIMESTAMP)
1544#define bfin_write_CAN_MB19_TIMESTAMP(val) bfin_write16(CAN_MB19_TIMESTAMP,val)
1545#define bfin_read_CAN_MB19_LENGTH() bfin_read16(CAN_MB19_LENGTH)
1546#define bfin_write_CAN_MB19_LENGTH(val) bfin_write16(CAN_MB19_LENGTH,val)
1547#define bfin_read_CAN_MB19_DATA3() bfin_read16(CAN_MB19_DATA3)
1548#define bfin_write_CAN_MB19_DATA3(val) bfin_write16(CAN_MB19_DATA3,val)
1549#define bfin_read_CAN_MB19_DATA2() bfin_read16(CAN_MB19_DATA2)
1550#define bfin_write_CAN_MB19_DATA2(val) bfin_write16(CAN_MB19_DATA2,val)
1551#define bfin_read_CAN_MB19_DATA1() bfin_read16(CAN_MB19_DATA1)
1552#define bfin_write_CAN_MB19_DATA1(val) bfin_write16(CAN_MB19_DATA1,val)
1553#define bfin_read_CAN_MB19_DATA0() bfin_read16(CAN_MB19_DATA0)
1554#define bfin_write_CAN_MB19_DATA0(val) bfin_write16(CAN_MB19_DATA0,val)
1555
1556#define bfin_read_CAN_MB20_ID1() bfin_read16(CAN_MB20_ID1)
1557#define bfin_write_CAN_MB20_ID1(val) bfin_write16(CAN_MB20_ID1,val)
1558#define bfin_read_CAN_MB20_ID0() bfin_read16(CAN_MB20_ID0)
1559#define bfin_write_CAN_MB20_ID0(val) bfin_write16(CAN_MB20_ID0,val)
1560#define bfin_read_CAN_MB20_TIMESTAMP() bfin_read16(CAN_MB20_TIMESTAMP)
1561#define bfin_write_CAN_MB20_TIMESTAMP(val) bfin_write16(CAN_MB20_TIMESTAMP,val)
1562#define bfin_read_CAN_MB20_LENGTH() bfin_read16(CAN_MB20_LENGTH)
1563#define bfin_write_CAN_MB20_LENGTH(val) bfin_write16(CAN_MB20_LENGTH,val)
1564#define bfin_read_CAN_MB20_DATA3() bfin_read16(CAN_MB20_DATA3)
1565#define bfin_write_CAN_MB20_DATA3(val) bfin_write16(CAN_MB20_DATA3,val)
1566#define bfin_read_CAN_MB20_DATA2() bfin_read16(CAN_MB20_DATA2)
1567#define bfin_write_CAN_MB20_DATA2(val) bfin_write16(CAN_MB20_DATA2,val)
1568#define bfin_read_CAN_MB20_DATA1() bfin_read16(CAN_MB20_DATA1)
1569#define bfin_write_CAN_MB20_DATA1(val) bfin_write16(CAN_MB20_DATA1,val)
1570#define bfin_read_CAN_MB20_DATA0() bfin_read16(CAN_MB20_DATA0)
1571#define bfin_write_CAN_MB20_DATA0(val) bfin_write16(CAN_MB20_DATA0,val)
1572
1573#define bfin_read_CAN_MB21_ID1() bfin_read16(CAN_MB21_ID1)
1574#define bfin_write_CAN_MB21_ID1(val) bfin_write16(CAN_MB21_ID1,val)
1575#define bfin_read_CAN_MB21_ID0() bfin_read16(CAN_MB21_ID0)
1576#define bfin_write_CAN_MB21_ID0(val) bfin_write16(CAN_MB21_ID0,val)
1577#define bfin_read_CAN_MB21_TIMESTAMP() bfin_read16(CAN_MB21_TIMESTAMP)
1578#define bfin_write_CAN_MB21_TIMESTAMP(val) bfin_write16(CAN_MB21_TIMESTAMP,val)
1579#define bfin_read_CAN_MB21_LENGTH() bfin_read16(CAN_MB21_LENGTH)
1580#define bfin_write_CAN_MB21_LENGTH(val) bfin_write16(CAN_MB21_LENGTH,val)
1581#define bfin_read_CAN_MB21_DATA3() bfin_read16(CAN_MB21_DATA3)
1582#define bfin_write_CAN_MB21_DATA3(val) bfin_write16(CAN_MB21_DATA3,val)
1583#define bfin_read_CAN_MB21_DATA2() bfin_read16(CAN_MB21_DATA2)
1584#define bfin_write_CAN_MB21_DATA2(val) bfin_write16(CAN_MB21_DATA2,val)
1585#define bfin_read_CAN_MB21_DATA1() bfin_read16(CAN_MB21_DATA1)
1586#define bfin_write_CAN_MB21_DATA1(val) bfin_write16(CAN_MB21_DATA1,val)
1587#define bfin_read_CAN_MB21_DATA0() bfin_read16(CAN_MB21_DATA0)
1588#define bfin_write_CAN_MB21_DATA0(val) bfin_write16(CAN_MB21_DATA0,val)
1589
1590#define bfin_read_CAN_MB22_ID1() bfin_read16(CAN_MB22_ID1)
1591#define bfin_write_CAN_MB22_ID1(val) bfin_write16(CAN_MB22_ID1,val)
1592#define bfin_read_CAN_MB22_ID0() bfin_read16(CAN_MB22_ID0)
1593#define bfin_write_CAN_MB22_ID0(val) bfin_write16(CAN_MB22_ID0,val)
1594#define bfin_read_CAN_MB22_TIMESTAMP() bfin_read16(CAN_MB22_TIMESTAMP)
1595#define bfin_write_CAN_MB22_TIMESTAMP(val) bfin_write16(CAN_MB22_TIMESTAMP,val)
1596#define bfin_read_CAN_MB22_LENGTH() bfin_read16(CAN_MB22_LENGTH)
1597#define bfin_write_CAN_MB22_LENGTH(val) bfin_write16(CAN_MB22_LENGTH,val)
1598#define bfin_read_CAN_MB22_DATA3() bfin_read16(CAN_MB22_DATA3)
1599#define bfin_write_CAN_MB22_DATA3(val) bfin_write16(CAN_MB22_DATA3,val)
1600#define bfin_read_CAN_MB22_DATA2() bfin_read16(CAN_MB22_DATA2)
1601#define bfin_write_CAN_MB22_DATA2(val) bfin_write16(CAN_MB22_DATA2,val)
1602#define bfin_read_CAN_MB22_DATA1() bfin_read16(CAN_MB22_DATA1)
1603#define bfin_write_CAN_MB22_DATA1(val) bfin_write16(CAN_MB22_DATA1,val)
1604#define bfin_read_CAN_MB22_DATA0() bfin_read16(CAN_MB22_DATA0)
1605#define bfin_write_CAN_MB22_DATA0(val) bfin_write16(CAN_MB22_DATA0,val)
1606
1607#define bfin_read_CAN_MB23_ID1() bfin_read16(CAN_MB23_ID1)
1608#define bfin_write_CAN_MB23_ID1(val) bfin_write16(CAN_MB23_ID1,val)
1609#define bfin_read_CAN_MB23_ID0() bfin_read16(CAN_MB23_ID0)
1610#define bfin_write_CAN_MB23_ID0(val) bfin_write16(CAN_MB23_ID0,val)
1611#define bfin_read_CAN_MB23_TIMESTAMP() bfin_read16(CAN_MB23_TIMESTAMP)
1612#define bfin_write_CAN_MB23_TIMESTAMP(val) bfin_write16(CAN_MB23_TIMESTAMP,val)
1613#define bfin_read_CAN_MB23_LENGTH() bfin_read16(CAN_MB23_LENGTH)
1614#define bfin_write_CAN_MB23_LENGTH(val) bfin_write16(CAN_MB23_LENGTH,val)
1615#define bfin_read_CAN_MB23_DATA3() bfin_read16(CAN_MB23_DATA3)
1616#define bfin_write_CAN_MB23_DATA3(val) bfin_write16(CAN_MB23_DATA3,val)
1617#define bfin_read_CAN_MB23_DATA2() bfin_read16(CAN_MB23_DATA2)
1618#define bfin_write_CAN_MB23_DATA2(val) bfin_write16(CAN_MB23_DATA2,val)
1619#define bfin_read_CAN_MB23_DATA1() bfin_read16(CAN_MB23_DATA1)
1620#define bfin_write_CAN_MB23_DATA1(val) bfin_write16(CAN_MB23_DATA1,val)
1621#define bfin_read_CAN_MB23_DATA0() bfin_read16(CAN_MB23_DATA0)
1622#define bfin_write_CAN_MB23_DATA0(val) bfin_write16(CAN_MB23_DATA0,val)
1623
1624#define bfin_read_CAN_MB24_ID1() bfin_read16(CAN_MB24_ID1)
1625#define bfin_write_CAN_MB24_ID1(val) bfin_write16(CAN_MB24_ID1,val)
1626#define bfin_read_CAN_MB24_ID0() bfin_read16(CAN_MB24_ID0)
1627#define bfin_write_CAN_MB24_ID0(val) bfin_write16(CAN_MB24_ID0,val)
1628#define bfin_read_CAN_MB24_TIMESTAMP() bfin_read16(CAN_MB24_TIMESTAMP)
1629#define bfin_write_CAN_MB24_TIMESTAMP(val) bfin_write16(CAN_MB24_TIMESTAMP,val)
1630#define bfin_read_CAN_MB24_LENGTH() bfin_read16(CAN_MB24_LENGTH)
1631#define bfin_write_CAN_MB24_LENGTH(val) bfin_write16(CAN_MB24_LENGTH,val)
1632#define bfin_read_CAN_MB24_DATA3() bfin_read16(CAN_MB24_DATA3)
1633#define bfin_write_CAN_MB24_DATA3(val) bfin_write16(CAN_MB24_DATA3,val)
1634#define bfin_read_CAN_MB24_DATA2() bfin_read16(CAN_MB24_DATA2)
1635#define bfin_write_CAN_MB24_DATA2(val) bfin_write16(CAN_MB24_DATA2,val)
1636#define bfin_read_CAN_MB24_DATA1() bfin_read16(CAN_MB24_DATA1)
1637#define bfin_write_CAN_MB24_DATA1(val) bfin_write16(CAN_MB24_DATA1,val)
1638#define bfin_read_CAN_MB24_DATA0() bfin_read16(CAN_MB24_DATA0)
1639#define bfin_write_CAN_MB24_DATA0(val) bfin_write16(CAN_MB24_DATA0,val)
1640
1641#define bfin_read_CAN_MB25_ID1() bfin_read16(CAN_MB25_ID1)
1642#define bfin_write_CAN_MB25_ID1(val) bfin_write16(CAN_MB25_ID1,val)
1643#define bfin_read_CAN_MB25_ID0() bfin_read16(CAN_MB25_ID0)
1644#define bfin_write_CAN_MB25_ID0(val) bfin_write16(CAN_MB25_ID0,val)
1645#define bfin_read_CAN_MB25_TIMESTAMP() bfin_read16(CAN_MB25_TIMESTAMP)
1646#define bfin_write_CAN_MB25_TIMESTAMP(val) bfin_write16(CAN_MB25_TIMESTAMP,val)
1647#define bfin_read_CAN_MB25_LENGTH() bfin_read16(CAN_MB25_LENGTH)
1648#define bfin_write_CAN_MB25_LENGTH(val) bfin_write16(CAN_MB25_LENGTH,val)
1649#define bfin_read_CAN_MB25_DATA3() bfin_read16(CAN_MB25_DATA3)
1650#define bfin_write_CAN_MB25_DATA3(val) bfin_write16(CAN_MB25_DATA3,val)
1651#define bfin_read_CAN_MB25_DATA2() bfin_read16(CAN_MB25_DATA2)
1652#define bfin_write_CAN_MB25_DATA2(val) bfin_write16(CAN_MB25_DATA2,val)
1653#define bfin_read_CAN_MB25_DATA1() bfin_read16(CAN_MB25_DATA1)
1654#define bfin_write_CAN_MB25_DATA1(val) bfin_write16(CAN_MB25_DATA1,val)
1655#define bfin_read_CAN_MB25_DATA0() bfin_read16(CAN_MB25_DATA0)
1656#define bfin_write_CAN_MB25_DATA0(val) bfin_write16(CAN_MB25_DATA0,val)
1657
1658#define bfin_read_CAN_MB26_ID1() bfin_read16(CAN_MB26_ID1)
1659#define bfin_write_CAN_MB26_ID1(val) bfin_write16(CAN_MB26_ID1,val)
1660#define bfin_read_CAN_MB26_ID0() bfin_read16(CAN_MB26_ID0)
1661#define bfin_write_CAN_MB26_ID0(val) bfin_write16(CAN_MB26_ID0,val)
1662#define bfin_read_CAN_MB26_TIMESTAMP() bfin_read16(CAN_MB26_TIMESTAMP)
1663#define bfin_write_CAN_MB26_TIMESTAMP(val) bfin_write16(CAN_MB26_TIMESTAMP,val)
1664#define bfin_read_CAN_MB26_LENGTH() bfin_read16(CAN_MB26_LENGTH)
1665#define bfin_write_CAN_MB26_LENGTH(val) bfin_write16(CAN_MB26_LENGTH,val)
1666#define bfin_read_CAN_MB26_DATA3() bfin_read16(CAN_MB26_DATA3)
1667#define bfin_write_CAN_MB26_DATA3(val) bfin_write16(CAN_MB26_DATA3,val)
1668#define bfin_read_CAN_MB26_DATA2() bfin_read16(CAN_MB26_DATA2)
1669#define bfin_write_CAN_MB26_DATA2(val) bfin_write16(CAN_MB26_DATA2,val)
1670#define bfin_read_CAN_MB26_DATA1() bfin_read16(CAN_MB26_DATA1)
1671#define bfin_write_CAN_MB26_DATA1(val) bfin_write16(CAN_MB26_DATA1,val)
1672#define bfin_read_CAN_MB26_DATA0() bfin_read16(CAN_MB26_DATA0)
1673#define bfin_write_CAN_MB26_DATA0(val) bfin_write16(CAN_MB26_DATA0,val)
1674
1675#define bfin_read_CAN_MB27_ID1() bfin_read16(CAN_MB27_ID1)
1676#define bfin_write_CAN_MB27_ID1(val) bfin_write16(CAN_MB27_ID1,val)
1677#define bfin_read_CAN_MB27_ID0() bfin_read16(CAN_MB27_ID0)
1678#define bfin_write_CAN_MB27_ID0(val) bfin_write16(CAN_MB27_ID0,val)
1679#define bfin_read_CAN_MB27_TIMESTAMP() bfin_read16(CAN_MB27_TIMESTAMP)
1680#define bfin_write_CAN_MB27_TIMESTAMP(val) bfin_write16(CAN_MB27_TIMESTAMP,val)
1681#define bfin_read_CAN_MB27_LENGTH() bfin_read16(CAN_MB27_LENGTH)
1682#define bfin_write_CAN_MB27_LENGTH(val) bfin_write16(CAN_MB27_LENGTH,val)
1683#define bfin_read_CAN_MB27_DATA3() bfin_read16(CAN_MB27_DATA3)
1684#define bfin_write_CAN_MB27_DATA3(val) bfin_write16(CAN_MB27_DATA3,val)
1685#define bfin_read_CAN_MB27_DATA2() bfin_read16(CAN_MB27_DATA2)
1686#define bfin_write_CAN_MB27_DATA2(val) bfin_write16(CAN_MB27_DATA2,val)
1687#define bfin_read_CAN_MB27_DATA1() bfin_read16(CAN_MB27_DATA1)
1688#define bfin_write_CAN_MB27_DATA1(val) bfin_write16(CAN_MB27_DATA1,val)
1689#define bfin_read_CAN_MB27_DATA0() bfin_read16(CAN_MB27_DATA0)
1690#define bfin_write_CAN_MB27_DATA0(val) bfin_write16(CAN_MB27_DATA0,val)
1691
1692#define bfin_read_CAN_MB28_ID1() bfin_read16(CAN_MB28_ID1)
1693#define bfin_write_CAN_MB28_ID1(val) bfin_write16(CAN_MB28_ID1,val)
1694#define bfin_read_CAN_MB28_ID0() bfin_read16(CAN_MB28_ID0)
1695#define bfin_write_CAN_MB28_ID0(val) bfin_write16(CAN_MB28_ID0,val)
1696#define bfin_read_CAN_MB28_TIMESTAMP() bfin_read16(CAN_MB28_TIMESTAMP)
1697#define bfin_write_CAN_MB28_TIMESTAMP(val) bfin_write16(CAN_MB28_TIMESTAMP,val)
1698#define bfin_read_CAN_MB28_LENGTH() bfin_read16(CAN_MB28_LENGTH)
1699#define bfin_write_CAN_MB28_LENGTH(val) bfin_write16(CAN_MB28_LENGTH,val)
1700#define bfin_read_CAN_MB28_DATA3() bfin_read16(CAN_MB28_DATA3)
1701#define bfin_write_CAN_MB28_DATA3(val) bfin_write16(CAN_MB28_DATA3,val)
1702#define bfin_read_CAN_MB28_DATA2() bfin_read16(CAN_MB28_DATA2)
1703#define bfin_write_CAN_MB28_DATA2(val) bfin_write16(CAN_MB28_DATA2,val)
1704#define bfin_read_CAN_MB28_DATA1() bfin_read16(CAN_MB28_DATA1)
1705#define bfin_write_CAN_MB28_DATA1(val) bfin_write16(CAN_MB28_DATA1,val)
1706#define bfin_read_CAN_MB28_DATA0() bfin_read16(CAN_MB28_DATA0)
1707#define bfin_write_CAN_MB28_DATA0(val) bfin_write16(CAN_MB28_DATA0,val)
1708
1709#define bfin_read_CAN_MB29_ID1() bfin_read16(CAN_MB29_ID1)
1710#define bfin_write_CAN_MB29_ID1(val) bfin_write16(CAN_MB29_ID1,val)
1711#define bfin_read_CAN_MB29_ID0() bfin_read16(CAN_MB29_ID0)
1712#define bfin_write_CAN_MB29_ID0(val) bfin_write16(CAN_MB29_ID0,val)
1713#define bfin_read_CAN_MB29_TIMESTAMP() bfin_read16(CAN_MB29_TIMESTAMP)
1714#define bfin_write_CAN_MB29_TIMESTAMP(val) bfin_write16(CAN_MB29_TIMESTAMP,val)
1715#define bfin_read_CAN_MB29_LENGTH() bfin_read16(CAN_MB29_LENGTH)
1716#define bfin_write_CAN_MB29_LENGTH(val) bfin_write16(CAN_MB29_LENGTH,val)
1717#define bfin_read_CAN_MB29_DATA3() bfin_read16(CAN_MB29_DATA3)
1718#define bfin_write_CAN_MB29_DATA3(val) bfin_write16(CAN_MB29_DATA3,val)
1719#define bfin_read_CAN_MB29_DATA2() bfin_read16(CAN_MB29_DATA2)
1720#define bfin_write_CAN_MB29_DATA2(val) bfin_write16(CAN_MB29_DATA2,val)
1721#define bfin_read_CAN_MB29_DATA1() bfin_read16(CAN_MB29_DATA1)
1722#define bfin_write_CAN_MB29_DATA1(val) bfin_write16(CAN_MB29_DATA1,val)
1723#define bfin_read_CAN_MB29_DATA0() bfin_read16(CAN_MB29_DATA0)
1724#define bfin_write_CAN_MB29_DATA0(val) bfin_write16(CAN_MB29_DATA0,val)
1725
1726#define bfin_read_CAN_MB30_ID1() bfin_read16(CAN_MB30_ID1)
1727#define bfin_write_CAN_MB30_ID1(val) bfin_write16(CAN_MB30_ID1,val)
1728#define bfin_read_CAN_MB30_ID0() bfin_read16(CAN_MB30_ID0)
1729#define bfin_write_CAN_MB30_ID0(val) bfin_write16(CAN_MB30_ID0,val)
1730#define bfin_read_CAN_MB30_TIMESTAMP() bfin_read16(CAN_MB30_TIMESTAMP)
1731#define bfin_write_CAN_MB30_TIMESTAMP(val) bfin_write16(CAN_MB30_TIMESTAMP,val)
1732#define bfin_read_CAN_MB30_LENGTH() bfin_read16(CAN_MB30_LENGTH)
1733#define bfin_write_CAN_MB30_LENGTH(val) bfin_write16(CAN_MB30_LENGTH,val)
1734#define bfin_read_CAN_MB30_DATA3() bfin_read16(CAN_MB30_DATA3)
1735#define bfin_write_CAN_MB30_DATA3(val) bfin_write16(CAN_MB30_DATA3,val)
1736#define bfin_read_CAN_MB30_DATA2() bfin_read16(CAN_MB30_DATA2)
1737#define bfin_write_CAN_MB30_DATA2(val) bfin_write16(CAN_MB30_DATA2,val)
1738#define bfin_read_CAN_MB30_DATA1() bfin_read16(CAN_MB30_DATA1)
1739#define bfin_write_CAN_MB30_DATA1(val) bfin_write16(CAN_MB30_DATA1,val)
1740#define bfin_read_CAN_MB30_DATA0() bfin_read16(CAN_MB30_DATA0)
1741#define bfin_write_CAN_MB30_DATA0(val) bfin_write16(CAN_MB30_DATA0,val)
1742
1743#define bfin_read_CAN_MB31_ID1() bfin_read16(CAN_MB31_ID1)
1744#define bfin_write_CAN_MB31_ID1(val) bfin_write16(CAN_MB31_ID1,val)
1745#define bfin_read_CAN_MB31_ID0() bfin_read16(CAN_MB31_ID0)
1746#define bfin_write_CAN_MB31_ID0(val) bfin_write16(CAN_MB31_ID0,val)
1747#define bfin_read_CAN_MB31_TIMESTAMP() bfin_read16(CAN_MB31_TIMESTAMP)
1748#define bfin_write_CAN_MB31_TIMESTAMP(val) bfin_write16(CAN_MB31_TIMESTAMP,val)
1749#define bfin_read_CAN_MB31_LENGTH() bfin_read16(CAN_MB31_LENGTH)
1750#define bfin_write_CAN_MB31_LENGTH(val) bfin_write16(CAN_MB31_LENGTH,val)
1751#define bfin_read_CAN_MB31_DATA3() bfin_read16(CAN_MB31_DATA3)
1752#define bfin_write_CAN_MB31_DATA3(val) bfin_write16(CAN_MB31_DATA3,val)
1753#define bfin_read_CAN_MB31_DATA2() bfin_read16(CAN_MB31_DATA2)
1754#define bfin_write_CAN_MB31_DATA2(val) bfin_write16(CAN_MB31_DATA2,val)
1755#define bfin_read_CAN_MB31_DATA1() bfin_read16(CAN_MB31_DATA1)
1756#define bfin_write_CAN_MB31_DATA1(val) bfin_write16(CAN_MB31_DATA1,val)
1757#define bfin_read_CAN_MB31_DATA0() bfin_read16(CAN_MB31_DATA0)
1758#define bfin_write_CAN_MB31_DATA0(val) bfin_write16(CAN_MB31_DATA0,val)
1759
1760/* CAN Mailbox Area Macros */
1761#define bfin_read_CAN_MB_ID1(x)() bfin_read16(CAN_MB_ID1(x))
1762#define bfin_write_CAN_MB_ID1(x)(val) bfin_write16(CAN_MB_ID1(x),val)
1763#define bfin_read_CAN_MB_ID0(x)() bfin_read16(CAN_MB_ID0(x))
1764#define bfin_write_CAN_MB_ID0(x)(val) bfin_write16(CAN_MB_ID0(x),val)
1765#define bfin_read_CAN_MB_TIMESTAMP(x)() bfin_read16(CAN_MB_TIMESTAMP(x))
1766#define bfin_write_CAN_MB_TIMESTAMP(x)(val) bfin_write16(CAN_MB_TIMESTAMP(x),val)
1767#define bfin_read_CAN_MB_LENGTH(x)() bfin_read16(CAN_MB_LENGTH(x))
1768#define bfin_write_CAN_MB_LENGTH(x)(val) bfin_write16(CAN_MB_LENGTH(x),val)
1769#define bfin_read_CAN_MB_DATA3(x)() bfin_read16(CAN_MB_DATA3(x))
1770#define bfin_write_CAN_MB_DATA3(x)(val) bfin_write16(CAN_MB_DATA3(x),val)
1771#define bfin_read_CAN_MB_DATA2(x)() bfin_read16(CAN_MB_DATA2(x))
1772#define bfin_write_CAN_MB_DATA2(x)(val) bfin_write16(CAN_MB_DATA2(x),val)
1773#define bfin_read_CAN_MB_DATA1(x)() bfin_read16(CAN_MB_DATA1(x))
1774#define bfin_write_CAN_MB_DATA1(x)(val) bfin_write16(CAN_MB_DATA1(x),val)
1775#define bfin_read_CAN_MB_DATA0(x)() bfin_read16(CAN_MB_DATA0(x))
1776#define bfin_write_CAN_MB_DATA0(x)(val) bfin_write16(CAN_MB_DATA0(x),val)
1777
1778/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
1779#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER)
1780#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER,val)
1781#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER)
1782#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER,val)
1783#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER)
1784#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER,val)
1785#define bfin_read_PORT_MUX() bfin_read16(BFIN_PORT_MUX)
1786#define bfin_write_PORT_MUX(val) bfin_write16(BFIN_PORT_MUX,val)
1787
1788/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
1789#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
1790#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL,val)
1791#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
1792#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT,val)
1793#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
1794#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT,val)
1795#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
1796#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT,val)
1797#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
1798#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW,val)
1799#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
1800#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT,val)
1801#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
1802#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT,val)
1803
1804#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
1805#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL,val)
1806#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
1807#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT,val)
1808#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
1809#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT,val)
1810#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
1811#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT,val)
1812#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
1813#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW,val)
1814#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
1815#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT,val)
1816#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
1817#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT,val)
1818
1819#endif /* _CDEF_BF534_H */
diff --git a/arch/blackfin/mach-bf537/include/mach/cdefBF537.h b/arch/blackfin/mach-bf537/include/mach/cdefBF537.h
new file mode 100644
index 000000000000..b8fc949a991f
--- /dev/null
+++ b/arch/blackfin/mach-bf537/include/mach/cdefBF537.h
@@ -0,0 +1,206 @@
1/*
2 * File: include/asm-blackfin/mach-bf537/cdefBF537.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 * System MMR Register Map
9 * Rev:
10 *
11 * Modified:
12 *
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#ifndef _CDEF_BF537_H
33#define _CDEF_BF537_H
34
35/* Include MMRs Common to BF534 */
36#include "cdefBF534.h"
37
38/* Include all Core registers and bit definitions */
39#include "defBF537.h"
40
41/* Include Macro "Defines" For EMAC (Unique to BF536/BF537 */
42/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
43#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE)
44#define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE,val)
45#define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO)
46#define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO,val)
47#define bfin_read_EMAC_ADDRHI() bfin_read32(EMAC_ADDRHI)
48#define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI,val)
49#define bfin_read_EMAC_HASHLO() bfin_read32(EMAC_HASHLO)
50#define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO,val)
51#define bfin_read_EMAC_HASHHI() bfin_read32(EMAC_HASHHI)
52#define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI,val)
53#define bfin_read_EMAC_STAADD() bfin_read32(EMAC_STAADD)
54#define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD,val)
55#define bfin_read_EMAC_STADAT() bfin_read32(EMAC_STADAT)
56#define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT,val)
57#define bfin_read_EMAC_FLC() bfin_read32(EMAC_FLC)
58#define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC,val)
59#define bfin_read_EMAC_VLAN1() bfin_read32(EMAC_VLAN1)
60#define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1,val)
61#define bfin_read_EMAC_VLAN2() bfin_read32(EMAC_VLAN2)
62#define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2,val)
63#define bfin_read_EMAC_WKUP_CTL() bfin_read32(EMAC_WKUP_CTL)
64#define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL,val)
65#define bfin_read_EMAC_WKUP_FFMSK0() bfin_read32(EMAC_WKUP_FFMSK0)
66#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0,val)
67#define bfin_read_EMAC_WKUP_FFMSK1() bfin_read32(EMAC_WKUP_FFMSK1)
68#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1,val)
69#define bfin_read_EMAC_WKUP_FFMSK2() bfin_read32(EMAC_WKUP_FFMSK2)
70#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2,val)
71#define bfin_read_EMAC_WKUP_FFMSK3() bfin_read32(EMAC_WKUP_FFMSK3)
72#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3,val)
73#define bfin_read_EMAC_WKUP_FFCMD() bfin_read32(EMAC_WKUP_FFCMD)
74#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD,val)
75#define bfin_read_EMAC_WKUP_FFOFF() bfin_read32(EMAC_WKUP_FFOFF)
76#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF,val)
77#define bfin_read_EMAC_WKUP_FFCRC0() bfin_read32(EMAC_WKUP_FFCRC0)
78#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0,val)
79#define bfin_read_EMAC_WKUP_FFCRC1() bfin_read32(EMAC_WKUP_FFCRC1)
80#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1,val)
81
82#define bfin_read_EMAC_SYSCTL() bfin_read32(EMAC_SYSCTL)
83#define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL,val)
84#define bfin_read_EMAC_SYSTAT() bfin_read32(EMAC_SYSTAT)
85#define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT,val)
86#define bfin_read_EMAC_RX_STAT() bfin_read32(EMAC_RX_STAT)
87#define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT,val)
88#define bfin_read_EMAC_RX_STKY() bfin_read32(EMAC_RX_STKY)
89#define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY,val)
90#define bfin_read_EMAC_RX_IRQE() bfin_read32(EMAC_RX_IRQE)
91#define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE,val)
92#define bfin_read_EMAC_TX_STAT() bfin_read32(EMAC_TX_STAT)
93#define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT,val)
94#define bfin_read_EMAC_TX_STKY() bfin_read32(EMAC_TX_STKY)
95#define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY,val)
96#define bfin_read_EMAC_TX_IRQE() bfin_read32(EMAC_TX_IRQE)
97#define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE,val)
98
99#define bfin_read_EMAC_MMC_CTL() bfin_read32(EMAC_MMC_CTL)
100#define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL,val)
101#define bfin_read_EMAC_MMC_RIRQS() bfin_read32(EMAC_MMC_RIRQS)
102#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS,val)
103#define bfin_read_EMAC_MMC_RIRQE() bfin_read32(EMAC_MMC_RIRQE)
104#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE,val)
105#define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS)
106#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS,val)
107#define bfin_read_EMAC_MMC_TIRQE() bfin_read32(EMAC_MMC_TIRQE)
108#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE,val)
109
110#define bfin_read_EMAC_RXC_OK() bfin_read32(EMAC_RXC_OK)
111#define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK,val)
112#define bfin_read_EMAC_RXC_FCS() bfin_read32(EMAC_RXC_FCS)
113#define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS,val)
114#define bfin_read_EMAC_RXC_ALIGN() bfin_read32(EMAC_RXC_ALIGN)
115#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN,val)
116#define bfin_read_EMAC_RXC_OCTET() bfin_read32(EMAC_RXC_OCTET)
117#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET,val)
118#define bfin_read_EMAC_RXC_DMAOVF() bfin_read32(EMAC_RXC_DMAOVF)
119#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF,val)
120#define bfin_read_EMAC_RXC_UNICST() bfin_read32(EMAC_RXC_UNICST)
121#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST,val)
122#define bfin_read_EMAC_RXC_MULTI() bfin_read32(EMAC_RXC_MULTI)
123#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI,val)
124#define bfin_read_EMAC_RXC_BROAD() bfin_read32(EMAC_RXC_BROAD)
125#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD,val)
126#define bfin_read_EMAC_RXC_LNERRI() bfin_read32(EMAC_RXC_LNERRI)
127#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI,val)
128#define bfin_read_EMAC_RXC_LNERRO() bfin_read32(EMAC_RXC_LNERRO)
129#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO,val)
130#define bfin_read_EMAC_RXC_LONG() bfin_read32(EMAC_RXC_LONG)
131#define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG,val)
132#define bfin_read_EMAC_RXC_MACCTL() bfin_read32(EMAC_RXC_MACCTL)
133#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL,val)
134#define bfin_read_EMAC_RXC_OPCODE() bfin_read32(EMAC_RXC_OPCODE)
135#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE,val)
136#define bfin_read_EMAC_RXC_PAUSE() bfin_read32(EMAC_RXC_PAUSE)
137#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE,val)
138#define bfin_read_EMAC_RXC_ALLFRM() bfin_read32(EMAC_RXC_ALLFRM)
139#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM,val)
140#define bfin_read_EMAC_RXC_ALLOCT() bfin_read32(EMAC_RXC_ALLOCT)
141#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT,val)
142#define bfin_read_EMAC_RXC_TYPED() bfin_read32(EMAC_RXC_TYPED)
143#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED,val)
144#define bfin_read_EMAC_RXC_SHORT() bfin_read32(EMAC_RXC_SHORT)
145#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT,val)
146#define bfin_read_EMAC_RXC_EQ64() bfin_read32(EMAC_RXC_EQ64)
147#define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64,val)
148#define bfin_read_EMAC_RXC_LT128() bfin_read32(EMAC_RXC_LT128)
149#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128,val)
150#define bfin_read_EMAC_RXC_LT256() bfin_read32(EMAC_RXC_LT256)
151#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256,val)
152#define bfin_read_EMAC_RXC_LT512() bfin_read32(EMAC_RXC_LT512)
153#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512,val)
154#define bfin_read_EMAC_RXC_LT1024() bfin_read32(EMAC_RXC_LT1024)
155#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024,val)
156#define bfin_read_EMAC_RXC_GE1024() bfin_read32(EMAC_RXC_GE1024)
157#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024,val)
158
159#define bfin_read_EMAC_TXC_OK() bfin_read32(EMAC_TXC_OK)
160#define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK,val)
161#define bfin_read_EMAC_TXC_1COL() bfin_read32(EMAC_TXC_1COL)
162#define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL,val)
163#define bfin_read_EMAC_TXC_GT1COL() bfin_read32(EMAC_TXC_GT1COL)
164#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL,val)
165#define bfin_read_EMAC_TXC_OCTET() bfin_read32(EMAC_TXC_OCTET)
166#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET,val)
167#define bfin_read_EMAC_TXC_DEFER() bfin_read32(EMAC_TXC_DEFER)
168#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER,val)
169#define bfin_read_EMAC_TXC_LATECL() bfin_read32(EMAC_TXC_LATECL)
170#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL,val)
171#define bfin_read_EMAC_TXC_XS_COL() bfin_read32(EMAC_TXC_XS_COL)
172#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL,val)
173#define bfin_read_EMAC_TXC_DMAUND() bfin_read32(EMAC_TXC_DMAUND)
174#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND,val)
175#define bfin_read_EMAC_TXC_CRSERR() bfin_read32(EMAC_TXC_CRSERR)
176#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR,val)
177#define bfin_read_EMAC_TXC_UNICST() bfin_read32(EMAC_TXC_UNICST)
178#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST,val)
179#define bfin_read_EMAC_TXC_MULTI() bfin_read32(EMAC_TXC_MULTI)
180#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI,val)
181#define bfin_read_EMAC_TXC_BROAD() bfin_read32(EMAC_TXC_BROAD)
182#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD,val)
183#define bfin_read_EMAC_TXC_XS_DFR() bfin_read32(EMAC_TXC_XS_DFR)
184#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR,val)
185#define bfin_read_EMAC_TXC_MACCTL() bfin_read32(EMAC_TXC_MACCTL)
186#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL,val)
187#define bfin_read_EMAC_TXC_ALLFRM() bfin_read32(EMAC_TXC_ALLFRM)
188#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM,val)
189#define bfin_read_EMAC_TXC_ALLOCT() bfin_read32(EMAC_TXC_ALLOCT)
190#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT,val)
191#define bfin_read_EMAC_TXC_EQ64() bfin_read32(EMAC_TXC_EQ64)
192#define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64,val)
193#define bfin_read_EMAC_TXC_LT128() bfin_read32(EMAC_TXC_LT128)
194#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128,val)
195#define bfin_read_EMAC_TXC_LT256() bfin_read32(EMAC_TXC_LT256)
196#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256,val)
197#define bfin_read_EMAC_TXC_LT512() bfin_read32(EMAC_TXC_LT512)
198#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512,val)
199#define bfin_read_EMAC_TXC_LT1024() bfin_read32(EMAC_TXC_LT1024)
200#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024,val)
201#define bfin_read_EMAC_TXC_GE1024() bfin_read32(EMAC_TXC_GE1024)
202#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024,val)
203#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT)
204#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT,val)
205
206#endif /* _CDEF_BF537_H */
diff --git a/arch/blackfin/mach-bf537/include/mach/defBF534.h b/arch/blackfin/mach-bf537/include/mach/defBF534.h
new file mode 100644
index 000000000000..a3227f9003ff
--- /dev/null
+++ b/arch/blackfin/mach-bf537/include/mach/defBF534.h
@@ -0,0 +1,2527 @@
1/*
2 * File: include/asm-blackfin/mach-bf537/cdefBF537.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _DEF_BF534_H
32#define _DEF_BF534_H
33
34/* Include all Core registers and bit definitions */
35#include <asm/def_LPBlackfin.h>
36
37/************************************************************************************
38** System MMR Register Map
39*************************************************************************************/
40/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
41#define PLL_CTL 0xFFC00000 /* PLL Control Register */
42#define PLL_DIV 0xFFC00004 /* PLL Divide Register */
43#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */
44#define PLL_STAT 0xFFC0000C /* PLL Status Register */
45#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */
46#define CHIPID 0xFFC00014 /* Chip ID Register */
47
48/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
49#define SWRST 0xFFC00100 /* Software Reset Register */
50#define SYSCR 0xFFC00104 /* System Configuration Register */
51#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
52#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */
53#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
54#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
55#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
56#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
57#define SIC_ISR 0xFFC00120 /* Interrupt Status Register */
58#define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */
59
60/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
61#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
62#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
63#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
64
65/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
66#define RTC_STAT 0xFFC00300 /* RTC Status Register */
67#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
68#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
69#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
70#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
71#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
72#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Alternate Macro */
73
74/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
75#define UART0_THR 0xFFC00400 /* Transmit Holding register */
76#define UART0_RBR 0xFFC00400 /* Receive Buffer register */
77#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
78#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */
79#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
80#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */
81#define UART0_LCR 0xFFC0040C /* Line Control Register */
82#define UART0_MCR 0xFFC00410 /* Modem Control Register */
83#define UART0_LSR 0xFFC00414 /* Line Status Register */
84#define UART0_MSR 0xFFC00418 /* Modem Status Register */
85#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */
86#define UART0_GCTL 0xFFC00424 /* Global Control Register */
87
88/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
89#define SPI0_REGBASE 0xFFC00500
90#define SPI_CTL 0xFFC00500 /* SPI Control Register */
91#define SPI_FLG 0xFFC00504 /* SPI Flag register */
92#define SPI_STAT 0xFFC00508 /* SPI Status register */
93#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
94#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
95#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
96#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
97
98/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
99#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
100#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
101#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
102#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
103
104#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
105#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
106#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
107#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
108
109#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
110#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
111#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
112#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
113
114#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */
115#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */
116#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */
117#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */
118
119#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */
120#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */
121#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */
122#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */
123
124#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */
125#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */
126#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */
127#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */
128
129#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */
130#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */
131#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */
132#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */
133
134#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */
135#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */
136#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */
137#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */
138
139#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */
140#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */
141#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */
142
143/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
144#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */
145#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */
146#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */
147#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */
148#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */
149#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */
150#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */
151#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */
152#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */
153#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */
154#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */
155#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */
156#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */
157#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */
158#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */
159#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */
160#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */
161
162/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
163#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
164#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
165#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
166#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
167#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
168#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
169#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
170#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
171#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
172#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
173#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
174#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
175#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
176#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
177#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
178#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
179#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
180#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
181#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
182#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
183#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
184#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
185
186/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
187#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
188#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
189#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
190#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
191#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
192#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
193#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
194#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
195#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
196#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
197#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
198#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
199#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
200#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
201#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
202#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
203#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
204#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
205#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
206#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
207#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
208#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
209
210/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
211#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
212#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
213#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
214#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
215#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
216#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
217#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
218
219/* DMA Traffic Control Registers */
220#define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
221#define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
222
223/* Alternate deprecated register names (below) provided for backwards code compatibility */
224#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
225#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
226
227/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
228#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
229#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
230#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
231#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
232#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
233#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
234#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
235#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
236#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
237#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
238#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
239#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
240#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
241
242#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
243#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
244#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
245#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
246#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
247#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
248#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
249#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
250#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
251#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
252#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
253#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
254#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
255
256#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
257#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
258#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
259#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
260#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
261#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
262#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
263#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
264#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
265#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
266#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
267#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
268#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
269
270#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
271#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
272#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
273#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
274#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
275#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
276#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
277#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
278#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
279#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
280#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
281#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
282#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
283
284#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
285#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
286#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
287#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
288#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
289#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
290#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
291#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
292#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
293#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
294#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
295#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
296#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
297
298#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
299#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
300#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
301#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
302#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
303#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
304#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
305#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
306#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
307#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
308#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
309#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
310#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
311
312#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
313#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
314#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
315#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
316#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
317#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
318#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
319#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
320#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
321#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
322#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
323#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
324#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
325
326#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
327#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
328#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
329#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
330#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
331#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
332#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
333#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
334#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
335#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
336#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
337#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
338#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
339
340#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
341#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */
342#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */
343#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */
344#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */
345#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */
346#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */
347#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
348#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */
349#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
350#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
351#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */
352#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
353
354#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
355#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */
356#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */
357#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */
358#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */
359#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */
360#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */
361#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
362#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */
363#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
364#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
365#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */
366#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
367
368#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
369#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */
370#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */
371#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */
372#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */
373#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */
374#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
375#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
376#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */
377#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
378#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
379#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
380#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
381
382#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
383#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */
384#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */
385#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */
386#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
387#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */
388#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
389#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
390#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */
391#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
392#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
393#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
394#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
395
396#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
397#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */
398#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */
399#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */
400#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */
401#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */
402#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */
403#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
404#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */
405#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
406#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */
407#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */
408#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */
409
410#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
411#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */
412#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */
413#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */
414#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */
415#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */
416#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */
417#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
418#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */
419#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */
420#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */
421#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */
422#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */
423
424#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
425#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */
426#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */
427#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */
428#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */
429#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */
430#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */
431#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
432#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */
433#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
434#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */
435#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */
436#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */
437
438#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
439#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */
440#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */
441#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */
442#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */
443#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */
444#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */
445#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
446#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */
447#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
448#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */
449#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */
450#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */
451
452/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
453#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
454#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
455#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
456#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
457#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
458
459/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
460#define TWI0_REGBASE 0xFFC01400
461#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
462#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */
463#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
464#define TWI_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
465#define TWI_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
466#define TWI_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
467#define TWI_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
468#define TWI_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
469#define TWI_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
470#define TWI_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
471#define TWI_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
472#define TWI_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
473#define TWI_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
474#define TWI_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
475#define TWI_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
476#define TWI_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
477
478/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
479#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */
480#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */
481#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */
482#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */
483#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */
484#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */
485#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */
486#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */
487#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */
488#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */
489#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */
490#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */
491#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */
492#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */
493#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */
494#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */
495#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */
496
497/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
498#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */
499#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */
500#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */
501#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */
502#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */
503#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */
504#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */
505#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */
506#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */
507#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */
508#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */
509#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */
510#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */
511#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */
512#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */
513#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */
514#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */
515
516/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
517#define UART1_THR 0xFFC02000 /* Transmit Holding register */
518#define UART1_RBR 0xFFC02000 /* Receive Buffer register */
519#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */
520#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */
521#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */
522#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */
523#define UART1_LCR 0xFFC0200C /* Line Control Register */
524#define UART1_MCR 0xFFC02010 /* Modem Control Register */
525#define UART1_LSR 0xFFC02014 /* Line Status Register */
526#define UART1_MSR 0xFFC02018 /* Modem Status Register */
527#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */
528#define UART1_GCTL 0xFFC02024 /* Global Control Register */
529
530/* CAN Controller (0xFFC02A00 - 0xFFC02FFF) */
531/* For Mailboxes 0-15 */
532#define CAN_MC1 0xFFC02A00 /* Mailbox config reg 1 */
533#define CAN_MD1 0xFFC02A04 /* Mailbox direction reg 1 */
534#define CAN_TRS1 0xFFC02A08 /* Transmit Request Set reg 1 */
535#define CAN_TRR1 0xFFC02A0C /* Transmit Request Reset reg 1 */
536#define CAN_TA1 0xFFC02A10 /* Transmit Acknowledge reg 1 */
537#define CAN_AA1 0xFFC02A14 /* Transmit Abort Acknowledge reg 1 */
538#define CAN_RMP1 0xFFC02A18 /* Receive Message Pending reg 1 */
539#define CAN_RML1 0xFFC02A1C /* Receive Message Lost reg 1 */
540#define CAN_MBTIF1 0xFFC02A20 /* Mailbox Transmit Interrupt Flag reg 1 */
541#define CAN_MBRIF1 0xFFC02A24 /* Mailbox Receive Interrupt Flag reg 1 */
542#define CAN_MBIM1 0xFFC02A28 /* Mailbox Interrupt Mask reg 1 */
543#define CAN_RFH1 0xFFC02A2C /* Remote Frame Handling reg 1 */
544#define CAN_OPSS1 0xFFC02A30 /* Overwrite Protection Single Shot Xmit reg 1 */
545
546/* For Mailboxes 16-31 */
547#define CAN_MC2 0xFFC02A40 /* Mailbox config reg 2 */
548#define CAN_MD2 0xFFC02A44 /* Mailbox direction reg 2 */
549#define CAN_TRS2 0xFFC02A48 /* Transmit Request Set reg 2 */
550#define CAN_TRR2 0xFFC02A4C /* Transmit Request Reset reg 2 */
551#define CAN_TA2 0xFFC02A50 /* Transmit Acknowledge reg 2 */
552#define CAN_AA2 0xFFC02A54 /* Transmit Abort Acknowledge reg 2 */
553#define CAN_RMP2 0xFFC02A58 /* Receive Message Pending reg 2 */
554#define CAN_RML2 0xFFC02A5C /* Receive Message Lost reg 2 */
555#define CAN_MBTIF2 0xFFC02A60 /* Mailbox Transmit Interrupt Flag reg 2 */
556#define CAN_MBRIF2 0xFFC02A64 /* Mailbox Receive Interrupt Flag reg 2 */
557#define CAN_MBIM2 0xFFC02A68 /* Mailbox Interrupt Mask reg 2 */
558#define CAN_RFH2 0xFFC02A6C /* Remote Frame Handling reg 2 */
559#define CAN_OPSS2 0xFFC02A70 /* Overwrite Protection Single Shot Xmit reg 2 */
560
561/* CAN Configuration, Control, and Status Registers */
562#define CAN_CLOCK 0xFFC02A80 /* Bit Timing Configuration register 0 */
563#define CAN_TIMING 0xFFC02A84 /* Bit Timing Configuration register 1 */
564#define CAN_DEBUG 0xFFC02A88 /* Debug Register */
565#define CAN_STATUS 0xFFC02A8C /* Global Status Register */
566#define CAN_CEC 0xFFC02A90 /* Error Counter Register */
567#define CAN_GIS 0xFFC02A94 /* Global Interrupt Status Register */
568#define CAN_GIM 0xFFC02A98 /* Global Interrupt Mask Register */
569#define CAN_GIF 0xFFC02A9C /* Global Interrupt Flag Register */
570#define CAN_CONTROL 0xFFC02AA0 /* Master Control Register */
571#define CAN_INTR 0xFFC02AA4 /* Interrupt Pending Register */
572
573#define CAN_MBTD 0xFFC02AAC /* Mailbox Temporary Disable Feature */
574#define CAN_EWR 0xFFC02AB0 /* Programmable Warning Level */
575#define CAN_ESR 0xFFC02AB4 /* Error Status Register */
576#define CAN_UCREG 0xFFC02AC0 /* Universal Counter Register/Capture Register */
577#define CAN_UCCNT 0xFFC02AC4 /* Universal Counter */
578#define CAN_UCRC 0xFFC02AC8 /* Universal Counter Force Reload Register */
579#define CAN_UCCNF 0xFFC02ACC /* Universal Counter Configuration Register */
580
581/* Mailbox Acceptance Masks */
582#define CAN_AM00L 0xFFC02B00 /* Mailbox 0 Low Acceptance Mask */
583#define CAN_AM00H 0xFFC02B04 /* Mailbox 0 High Acceptance Mask */
584#define CAN_AM01L 0xFFC02B08 /* Mailbox 1 Low Acceptance Mask */
585#define CAN_AM01H 0xFFC02B0C /* Mailbox 1 High Acceptance Mask */
586#define CAN_AM02L 0xFFC02B10 /* Mailbox 2 Low Acceptance Mask */
587#define CAN_AM02H 0xFFC02B14 /* Mailbox 2 High Acceptance Mask */
588#define CAN_AM03L 0xFFC02B18 /* Mailbox 3 Low Acceptance Mask */
589#define CAN_AM03H 0xFFC02B1C /* Mailbox 3 High Acceptance Mask */
590#define CAN_AM04L 0xFFC02B20 /* Mailbox 4 Low Acceptance Mask */
591#define CAN_AM04H 0xFFC02B24 /* Mailbox 4 High Acceptance Mask */
592#define CAN_AM05L 0xFFC02B28 /* Mailbox 5 Low Acceptance Mask */
593#define CAN_AM05H 0xFFC02B2C /* Mailbox 5 High Acceptance Mask */
594#define CAN_AM06L 0xFFC02B30 /* Mailbox 6 Low Acceptance Mask */
595#define CAN_AM06H 0xFFC02B34 /* Mailbox 6 High Acceptance Mask */
596#define CAN_AM07L 0xFFC02B38 /* Mailbox 7 Low Acceptance Mask */
597#define CAN_AM07H 0xFFC02B3C /* Mailbox 7 High Acceptance Mask */
598#define CAN_AM08L 0xFFC02B40 /* Mailbox 8 Low Acceptance Mask */
599#define CAN_AM08H 0xFFC02B44 /* Mailbox 8 High Acceptance Mask */
600#define CAN_AM09L 0xFFC02B48 /* Mailbox 9 Low Acceptance Mask */
601#define CAN_AM09H 0xFFC02B4C /* Mailbox 9 High Acceptance Mask */
602#define CAN_AM10L 0xFFC02B50 /* Mailbox 10 Low Acceptance Mask */
603#define CAN_AM10H 0xFFC02B54 /* Mailbox 10 High Acceptance Mask */
604#define CAN_AM11L 0xFFC02B58 /* Mailbox 11 Low Acceptance Mask */
605#define CAN_AM11H 0xFFC02B5C /* Mailbox 11 High Acceptance Mask */
606#define CAN_AM12L 0xFFC02B60 /* Mailbox 12 Low Acceptance Mask */
607#define CAN_AM12H 0xFFC02B64 /* Mailbox 12 High Acceptance Mask */
608#define CAN_AM13L 0xFFC02B68 /* Mailbox 13 Low Acceptance Mask */
609#define CAN_AM13H 0xFFC02B6C /* Mailbox 13 High Acceptance Mask */
610#define CAN_AM14L 0xFFC02B70 /* Mailbox 14 Low Acceptance Mask */
611#define CAN_AM14H 0xFFC02B74 /* Mailbox 14 High Acceptance Mask */
612#define CAN_AM15L 0xFFC02B78 /* Mailbox 15 Low Acceptance Mask */
613#define CAN_AM15H 0xFFC02B7C /* Mailbox 15 High Acceptance Mask */
614
615#define CAN_AM16L 0xFFC02B80 /* Mailbox 16 Low Acceptance Mask */
616#define CAN_AM16H 0xFFC02B84 /* Mailbox 16 High Acceptance Mask */
617#define CAN_AM17L 0xFFC02B88 /* Mailbox 17 Low Acceptance Mask */
618#define CAN_AM17H 0xFFC02B8C /* Mailbox 17 High Acceptance Mask */
619#define CAN_AM18L 0xFFC02B90 /* Mailbox 18 Low Acceptance Mask */
620#define CAN_AM18H 0xFFC02B94 /* Mailbox 18 High Acceptance Mask */
621#define CAN_AM19L 0xFFC02B98 /* Mailbox 19 Low Acceptance Mask */
622#define CAN_AM19H 0xFFC02B9C /* Mailbox 19 High Acceptance Mask */
623#define CAN_AM20L 0xFFC02BA0 /* Mailbox 20 Low Acceptance Mask */
624#define CAN_AM20H 0xFFC02BA4 /* Mailbox 20 High Acceptance Mask */
625#define CAN_AM21L 0xFFC02BA8 /* Mailbox 21 Low Acceptance Mask */
626#define CAN_AM21H 0xFFC02BAC /* Mailbox 21 High Acceptance Mask */
627#define CAN_AM22L 0xFFC02BB0 /* Mailbox 22 Low Acceptance Mask */
628#define CAN_AM22H 0xFFC02BB4 /* Mailbox 22 High Acceptance Mask */
629#define CAN_AM23L 0xFFC02BB8 /* Mailbox 23 Low Acceptance Mask */
630#define CAN_AM23H 0xFFC02BBC /* Mailbox 23 High Acceptance Mask */
631#define CAN_AM24L 0xFFC02BC0 /* Mailbox 24 Low Acceptance Mask */
632#define CAN_AM24H 0xFFC02BC4 /* Mailbox 24 High Acceptance Mask */
633#define CAN_AM25L 0xFFC02BC8 /* Mailbox 25 Low Acceptance Mask */
634#define CAN_AM25H 0xFFC02BCC /* Mailbox 25 High Acceptance Mask */
635#define CAN_AM26L 0xFFC02BD0 /* Mailbox 26 Low Acceptance Mask */
636#define CAN_AM26H 0xFFC02BD4 /* Mailbox 26 High Acceptance Mask */
637#define CAN_AM27L 0xFFC02BD8 /* Mailbox 27 Low Acceptance Mask */
638#define CAN_AM27H 0xFFC02BDC /* Mailbox 27 High Acceptance Mask */
639#define CAN_AM28L 0xFFC02BE0 /* Mailbox 28 Low Acceptance Mask */
640#define CAN_AM28H 0xFFC02BE4 /* Mailbox 28 High Acceptance Mask */
641#define CAN_AM29L 0xFFC02BE8 /* Mailbox 29 Low Acceptance Mask */
642#define CAN_AM29H 0xFFC02BEC /* Mailbox 29 High Acceptance Mask */
643#define CAN_AM30L 0xFFC02BF0 /* Mailbox 30 Low Acceptance Mask */
644#define CAN_AM30H 0xFFC02BF4 /* Mailbox 30 High Acceptance Mask */
645#define CAN_AM31L 0xFFC02BF8 /* Mailbox 31 Low Acceptance Mask */
646#define CAN_AM31H 0xFFC02BFC /* Mailbox 31 High Acceptance Mask */
647
648/* CAN Acceptance Mask Macros */
649#define CAN_AM_L(x) (CAN_AM00L+((x)*0x8))
650#define CAN_AM_H(x) (CAN_AM00H+((x)*0x8))
651
652/* Mailbox Registers */
653#define CAN_MB00_DATA0 0xFFC02C00 /* Mailbox 0 Data Word 0 [15:0] Register */
654#define CAN_MB00_DATA1 0xFFC02C04 /* Mailbox 0 Data Word 1 [31:16] Register */
655#define CAN_MB00_DATA2 0xFFC02C08 /* Mailbox 0 Data Word 2 [47:32] Register */
656#define CAN_MB00_DATA3 0xFFC02C0C /* Mailbox 0 Data Word 3 [63:48] Register */
657#define CAN_MB00_LENGTH 0xFFC02C10 /* Mailbox 0 Data Length Code Register */
658#define CAN_MB00_TIMESTAMP 0xFFC02C14 /* Mailbox 0 Time Stamp Value Register */
659#define CAN_MB00_ID0 0xFFC02C18 /* Mailbox 0 Identifier Low Register */
660#define CAN_MB00_ID1 0xFFC02C1C /* Mailbox 0 Identifier High Register */
661
662#define CAN_MB01_DATA0 0xFFC02C20 /* Mailbox 1 Data Word 0 [15:0] Register */
663#define CAN_MB01_DATA1 0xFFC02C24 /* Mailbox 1 Data Word 1 [31:16] Register */
664#define CAN_MB01_DATA2 0xFFC02C28 /* Mailbox 1 Data Word 2 [47:32] Register */
665#define CAN_MB01_DATA3 0xFFC02C2C /* Mailbox 1 Data Word 3 [63:48] Register */
666#define CAN_MB01_LENGTH 0xFFC02C30 /* Mailbox 1 Data Length Code Register */
667#define CAN_MB01_TIMESTAMP 0xFFC02C34 /* Mailbox 1 Time Stamp Value Register */
668#define CAN_MB01_ID0 0xFFC02C38 /* Mailbox 1 Identifier Low Register */
669#define CAN_MB01_ID1 0xFFC02C3C /* Mailbox 1 Identifier High Register */
670
671#define CAN_MB02_DATA0 0xFFC02C40 /* Mailbox 2 Data Word 0 [15:0] Register */
672#define CAN_MB02_DATA1 0xFFC02C44 /* Mailbox 2 Data Word 1 [31:16] Register */
673#define CAN_MB02_DATA2 0xFFC02C48 /* Mailbox 2 Data Word 2 [47:32] Register */
674#define CAN_MB02_DATA3 0xFFC02C4C /* Mailbox 2 Data Word 3 [63:48] Register */
675#define CAN_MB02_LENGTH 0xFFC02C50 /* Mailbox 2 Data Length Code Register */
676#define CAN_MB02_TIMESTAMP 0xFFC02C54 /* Mailbox 2 Time Stamp Value Register */
677#define CAN_MB02_ID0 0xFFC02C58 /* Mailbox 2 Identifier Low Register */
678#define CAN_MB02_ID1 0xFFC02C5C /* Mailbox 2 Identifier High Register */
679
680#define CAN_MB03_DATA0 0xFFC02C60 /* Mailbox 3 Data Word 0 [15:0] Register */
681#define CAN_MB03_DATA1 0xFFC02C64 /* Mailbox 3 Data Word 1 [31:16] Register */
682#define CAN_MB03_DATA2 0xFFC02C68 /* Mailbox 3 Data Word 2 [47:32] Register */
683#define CAN_MB03_DATA3 0xFFC02C6C /* Mailbox 3 Data Word 3 [63:48] Register */
684#define CAN_MB03_LENGTH 0xFFC02C70 /* Mailbox 3 Data Length Code Register */
685#define CAN_MB03_TIMESTAMP 0xFFC02C74 /* Mailbox 3 Time Stamp Value Register */
686#define CAN_MB03_ID0 0xFFC02C78 /* Mailbox 3 Identifier Low Register */
687#define CAN_MB03_ID1 0xFFC02C7C /* Mailbox 3 Identifier High Register */
688
689#define CAN_MB04_DATA0 0xFFC02C80 /* Mailbox 4 Data Word 0 [15:0] Register */
690#define CAN_MB04_DATA1 0xFFC02C84 /* Mailbox 4 Data Word 1 [31:16] Register */
691#define CAN_MB04_DATA2 0xFFC02C88 /* Mailbox 4 Data Word 2 [47:32] Register */
692#define CAN_MB04_DATA3 0xFFC02C8C /* Mailbox 4 Data Word 3 [63:48] Register */
693#define CAN_MB04_LENGTH 0xFFC02C90 /* Mailbox 4 Data Length Code Register */
694#define CAN_MB04_TIMESTAMP 0xFFC02C94 /* Mailbox 4 Time Stamp Value Register */
695#define CAN_MB04_ID0 0xFFC02C98 /* Mailbox 4 Identifier Low Register */
696#define CAN_MB04_ID1 0xFFC02C9C /* Mailbox 4 Identifier High Register */
697
698#define CAN_MB05_DATA0 0xFFC02CA0 /* Mailbox 5 Data Word 0 [15:0] Register */
699#define CAN_MB05_DATA1 0xFFC02CA4 /* Mailbox 5 Data Word 1 [31:16] Register */
700#define CAN_MB05_DATA2 0xFFC02CA8 /* Mailbox 5 Data Word 2 [47:32] Register */
701#define CAN_MB05_DATA3 0xFFC02CAC /* Mailbox 5 Data Word 3 [63:48] Register */
702#define CAN_MB05_LENGTH 0xFFC02CB0 /* Mailbox 5 Data Length Code Register */
703#define CAN_MB05_TIMESTAMP 0xFFC02CB4 /* Mailbox 5 Time Stamp Value Register */
704#define CAN_MB05_ID0 0xFFC02CB8 /* Mailbox 5 Identifier Low Register */
705#define CAN_MB05_ID1 0xFFC02CBC /* Mailbox 5 Identifier High Register */
706
707#define CAN_MB06_DATA0 0xFFC02CC0 /* Mailbox 6 Data Word 0 [15:0] Register */
708#define CAN_MB06_DATA1 0xFFC02CC4 /* Mailbox 6 Data Word 1 [31:16] Register */
709#define CAN_MB06_DATA2 0xFFC02CC8 /* Mailbox 6 Data Word 2 [47:32] Register */
710#define CAN_MB06_DATA3 0xFFC02CCC /* Mailbox 6 Data Word 3 [63:48] Register */
711#define CAN_MB06_LENGTH 0xFFC02CD0 /* Mailbox 6 Data Length Code Register */
712#define CAN_MB06_TIMESTAMP 0xFFC02CD4 /* Mailbox 6 Time Stamp Value Register */
713#define CAN_MB06_ID0 0xFFC02CD8 /* Mailbox 6 Identifier Low Register */
714#define CAN_MB06_ID1 0xFFC02CDC /* Mailbox 6 Identifier High Register */
715
716#define CAN_MB07_DATA0 0xFFC02CE0 /* Mailbox 7 Data Word 0 [15:0] Register */
717#define CAN_MB07_DATA1 0xFFC02CE4 /* Mailbox 7 Data Word 1 [31:16] Register */
718#define CAN_MB07_DATA2 0xFFC02CE8 /* Mailbox 7 Data Word 2 [47:32] Register */
719#define CAN_MB07_DATA3 0xFFC02CEC /* Mailbox 7 Data Word 3 [63:48] Register */
720#define CAN_MB07_LENGTH 0xFFC02CF0 /* Mailbox 7 Data Length Code Register */
721#define CAN_MB07_TIMESTAMP 0xFFC02CF4 /* Mailbox 7 Time Stamp Value Register */
722#define CAN_MB07_ID0 0xFFC02CF8 /* Mailbox 7 Identifier Low Register */
723#define CAN_MB07_ID1 0xFFC02CFC /* Mailbox 7 Identifier High Register */
724
725#define CAN_MB08_DATA0 0xFFC02D00 /* Mailbox 8 Data Word 0 [15:0] Register */
726#define CAN_MB08_DATA1 0xFFC02D04 /* Mailbox 8 Data Word 1 [31:16] Register */
727#define CAN_MB08_DATA2 0xFFC02D08 /* Mailbox 8 Data Word 2 [47:32] Register */
728#define CAN_MB08_DATA3 0xFFC02D0C /* Mailbox 8 Data Word 3 [63:48] Register */
729#define CAN_MB08_LENGTH 0xFFC02D10 /* Mailbox 8 Data Length Code Register */
730#define CAN_MB08_TIMESTAMP 0xFFC02D14 /* Mailbox 8 Time Stamp Value Register */
731#define CAN_MB08_ID0 0xFFC02D18 /* Mailbox 8 Identifier Low Register */
732#define CAN_MB08_ID1 0xFFC02D1C /* Mailbox 8 Identifier High Register */
733
734#define CAN_MB09_DATA0 0xFFC02D20 /* Mailbox 9 Data Word 0 [15:0] Register */
735#define CAN_MB09_DATA1 0xFFC02D24 /* Mailbox 9 Data Word 1 [31:16] Register */
736#define CAN_MB09_DATA2 0xFFC02D28 /* Mailbox 9 Data Word 2 [47:32] Register */
737#define CAN_MB09_DATA3 0xFFC02D2C /* Mailbox 9 Data Word 3 [63:48] Register */
738#define CAN_MB09_LENGTH 0xFFC02D30 /* Mailbox 9 Data Length Code Register */
739#define CAN_MB09_TIMESTAMP 0xFFC02D34 /* Mailbox 9 Time Stamp Value Register */
740#define CAN_MB09_ID0 0xFFC02D38 /* Mailbox 9 Identifier Low Register */
741#define CAN_MB09_ID1 0xFFC02D3C /* Mailbox 9 Identifier High Register */
742
743#define CAN_MB10_DATA0 0xFFC02D40 /* Mailbox 10 Data Word 0 [15:0] Register */
744#define CAN_MB10_DATA1 0xFFC02D44 /* Mailbox 10 Data Word 1 [31:16] Register */
745#define CAN_MB10_DATA2 0xFFC02D48 /* Mailbox 10 Data Word 2 [47:32] Register */
746#define CAN_MB10_DATA3 0xFFC02D4C /* Mailbox 10 Data Word 3 [63:48] Register */
747#define CAN_MB10_LENGTH 0xFFC02D50 /* Mailbox 10 Data Length Code Register */
748#define CAN_MB10_TIMESTAMP 0xFFC02D54 /* Mailbox 10 Time Stamp Value Register */
749#define CAN_MB10_ID0 0xFFC02D58 /* Mailbox 10 Identifier Low Register */
750#define CAN_MB10_ID1 0xFFC02D5C /* Mailbox 10 Identifier High Register */
751
752#define CAN_MB11_DATA0 0xFFC02D60 /* Mailbox 11 Data Word 0 [15:0] Register */
753#define CAN_MB11_DATA1 0xFFC02D64 /* Mailbox 11 Data Word 1 [31:16] Register */
754#define CAN_MB11_DATA2 0xFFC02D68 /* Mailbox 11 Data Word 2 [47:32] Register */
755#define CAN_MB11_DATA3 0xFFC02D6C /* Mailbox 11 Data Word 3 [63:48] Register */
756#define CAN_MB11_LENGTH 0xFFC02D70 /* Mailbox 11 Data Length Code Register */
757#define CAN_MB11_TIMESTAMP 0xFFC02D74 /* Mailbox 11 Time Stamp Value Register */
758#define CAN_MB11_ID0 0xFFC02D78 /* Mailbox 11 Identifier Low Register */
759#define CAN_MB11_ID1 0xFFC02D7C /* Mailbox 11 Identifier High Register */
760
761#define CAN_MB12_DATA0 0xFFC02D80 /* Mailbox 12 Data Word 0 [15:0] Register */
762#define CAN_MB12_DATA1 0xFFC02D84 /* Mailbox 12 Data Word 1 [31:16] Register */
763#define CAN_MB12_DATA2 0xFFC02D88 /* Mailbox 12 Data Word 2 [47:32] Register */
764#define CAN_MB12_DATA3 0xFFC02D8C /* Mailbox 12 Data Word 3 [63:48] Register */
765#define CAN_MB12_LENGTH 0xFFC02D90 /* Mailbox 12 Data Length Code Register */
766#define CAN_MB12_TIMESTAMP 0xFFC02D94 /* Mailbox 12 Time Stamp Value Register */
767#define CAN_MB12_ID0 0xFFC02D98 /* Mailbox 12 Identifier Low Register */
768#define CAN_MB12_ID1 0xFFC02D9C /* Mailbox 12 Identifier High Register */
769
770#define CAN_MB13_DATA0 0xFFC02DA0 /* Mailbox 13 Data Word 0 [15:0] Register */
771#define CAN_MB13_DATA1 0xFFC02DA4 /* Mailbox 13 Data Word 1 [31:16] Register */
772#define CAN_MB13_DATA2 0xFFC02DA8 /* Mailbox 13 Data Word 2 [47:32] Register */
773#define CAN_MB13_DATA3 0xFFC02DAC /* Mailbox 13 Data Word 3 [63:48] Register */
774#define CAN_MB13_LENGTH 0xFFC02DB0 /* Mailbox 13 Data Length Code Register */
775#define CAN_MB13_TIMESTAMP 0xFFC02DB4 /* Mailbox 13 Time Stamp Value Register */
776#define CAN_MB13_ID0 0xFFC02DB8 /* Mailbox 13 Identifier Low Register */
777#define CAN_MB13_ID1 0xFFC02DBC /* Mailbox 13 Identifier High Register */
778
779#define CAN_MB14_DATA0 0xFFC02DC0 /* Mailbox 14 Data Word 0 [15:0] Register */
780#define CAN_MB14_DATA1 0xFFC02DC4 /* Mailbox 14 Data Word 1 [31:16] Register */
781#define CAN_MB14_DATA2 0xFFC02DC8 /* Mailbox 14 Data Word 2 [47:32] Register */
782#define CAN_MB14_DATA3 0xFFC02DCC /* Mailbox 14 Data Word 3 [63:48] Register */
783#define CAN_MB14_LENGTH 0xFFC02DD0 /* Mailbox 14 Data Length Code Register */
784#define CAN_MB14_TIMESTAMP 0xFFC02DD4 /* Mailbox 14 Time Stamp Value Register */
785#define CAN_MB14_ID0 0xFFC02DD8 /* Mailbox 14 Identifier Low Register */
786#define CAN_MB14_ID1 0xFFC02DDC /* Mailbox 14 Identifier High Register */
787
788#define CAN_MB15_DATA0 0xFFC02DE0 /* Mailbox 15 Data Word 0 [15:0] Register */
789#define CAN_MB15_DATA1 0xFFC02DE4 /* Mailbox 15 Data Word 1 [31:16] Register */
790#define CAN_MB15_DATA2 0xFFC02DE8 /* Mailbox 15 Data Word 2 [47:32] Register */
791#define CAN_MB15_DATA3 0xFFC02DEC /* Mailbox 15 Data Word 3 [63:48] Register */
792#define CAN_MB15_LENGTH 0xFFC02DF0 /* Mailbox 15 Data Length Code Register */
793#define CAN_MB15_TIMESTAMP 0xFFC02DF4 /* Mailbox 15 Time Stamp Value Register */
794#define CAN_MB15_ID0 0xFFC02DF8 /* Mailbox 15 Identifier Low Register */
795#define CAN_MB15_ID1 0xFFC02DFC /* Mailbox 15 Identifier High Register */
796
797#define CAN_MB16_DATA0 0xFFC02E00 /* Mailbox 16 Data Word 0 [15:0] Register */
798#define CAN_MB16_DATA1 0xFFC02E04 /* Mailbox 16 Data Word 1 [31:16] Register */
799#define CAN_MB16_DATA2 0xFFC02E08 /* Mailbox 16 Data Word 2 [47:32] Register */
800#define CAN_MB16_DATA3 0xFFC02E0C /* Mailbox 16 Data Word 3 [63:48] Register */
801#define CAN_MB16_LENGTH 0xFFC02E10 /* Mailbox 16 Data Length Code Register */
802#define CAN_MB16_TIMESTAMP 0xFFC02E14 /* Mailbox 16 Time Stamp Value Register */
803#define CAN_MB16_ID0 0xFFC02E18 /* Mailbox 16 Identifier Low Register */
804#define CAN_MB16_ID1 0xFFC02E1C /* Mailbox 16 Identifier High Register */
805
806#define CAN_MB17_DATA0 0xFFC02E20 /* Mailbox 17 Data Word 0 [15:0] Register */
807#define CAN_MB17_DATA1 0xFFC02E24 /* Mailbox 17 Data Word 1 [31:16] Register */
808#define CAN_MB17_DATA2 0xFFC02E28 /* Mailbox 17 Data Word 2 [47:32] Register */
809#define CAN_MB17_DATA3 0xFFC02E2C /* Mailbox 17 Data Word 3 [63:48] Register */
810#define CAN_MB17_LENGTH 0xFFC02E30 /* Mailbox 17 Data Length Code Register */
811#define CAN_MB17_TIMESTAMP 0xFFC02E34 /* Mailbox 17 Time Stamp Value Register */
812#define CAN_MB17_ID0 0xFFC02E38 /* Mailbox 17 Identifier Low Register */
813#define CAN_MB17_ID1 0xFFC02E3C /* Mailbox 17 Identifier High Register */
814
815#define CAN_MB18_DATA0 0xFFC02E40 /* Mailbox 18 Data Word 0 [15:0] Register */
816#define CAN_MB18_DATA1 0xFFC02E44 /* Mailbox 18 Data Word 1 [31:16] Register */
817#define CAN_MB18_DATA2 0xFFC02E48 /* Mailbox 18 Data Word 2 [47:32] Register */
818#define CAN_MB18_DATA3 0xFFC02E4C /* Mailbox 18 Data Word 3 [63:48] Register */
819#define CAN_MB18_LENGTH 0xFFC02E50 /* Mailbox 18 Data Length Code Register */
820#define CAN_MB18_TIMESTAMP 0xFFC02E54 /* Mailbox 18 Time Stamp Value Register */
821#define CAN_MB18_ID0 0xFFC02E58 /* Mailbox 18 Identifier Low Register */
822#define CAN_MB18_ID1 0xFFC02E5C /* Mailbox 18 Identifier High Register */
823
824#define CAN_MB19_DATA0 0xFFC02E60 /* Mailbox 19 Data Word 0 [15:0] Register */
825#define CAN_MB19_DATA1 0xFFC02E64 /* Mailbox 19 Data Word 1 [31:16] Register */
826#define CAN_MB19_DATA2 0xFFC02E68 /* Mailbox 19 Data Word 2 [47:32] Register */
827#define CAN_MB19_DATA3 0xFFC02E6C /* Mailbox 19 Data Word 3 [63:48] Register */
828#define CAN_MB19_LENGTH 0xFFC02E70 /* Mailbox 19 Data Length Code Register */
829#define CAN_MB19_TIMESTAMP 0xFFC02E74 /* Mailbox 19 Time Stamp Value Register */
830#define CAN_MB19_ID0 0xFFC02E78 /* Mailbox 19 Identifier Low Register */
831#define CAN_MB19_ID1 0xFFC02E7C /* Mailbox 19 Identifier High Register */
832
833#define CAN_MB20_DATA0 0xFFC02E80 /* Mailbox 20 Data Word 0 [15:0] Register */
834#define CAN_MB20_DATA1 0xFFC02E84 /* Mailbox 20 Data Word 1 [31:16] Register */
835#define CAN_MB20_DATA2 0xFFC02E88 /* Mailbox 20 Data Word 2 [47:32] Register */
836#define CAN_MB20_DATA3 0xFFC02E8C /* Mailbox 20 Data Word 3 [63:48] Register */
837#define CAN_MB20_LENGTH 0xFFC02E90 /* Mailbox 20 Data Length Code Register */
838#define CAN_MB20_TIMESTAMP 0xFFC02E94 /* Mailbox 20 Time Stamp Value Register */
839#define CAN_MB20_ID0 0xFFC02E98 /* Mailbox 20 Identifier Low Register */
840#define CAN_MB20_ID1 0xFFC02E9C /* Mailbox 20 Identifier High Register */
841
842#define CAN_MB21_DATA0 0xFFC02EA0 /* Mailbox 21 Data Word 0 [15:0] Register */
843#define CAN_MB21_DATA1 0xFFC02EA4 /* Mailbox 21 Data Word 1 [31:16] Register */
844#define CAN_MB21_DATA2 0xFFC02EA8 /* Mailbox 21 Data Word 2 [47:32] Register */
845#define CAN_MB21_DATA3 0xFFC02EAC /* Mailbox 21 Data Word 3 [63:48] Register */
846#define CAN_MB21_LENGTH 0xFFC02EB0 /* Mailbox 21 Data Length Code Register */
847#define CAN_MB21_TIMESTAMP 0xFFC02EB4 /* Mailbox 21 Time Stamp Value Register */
848#define CAN_MB21_ID0 0xFFC02EB8 /* Mailbox 21 Identifier Low Register */
849#define CAN_MB21_ID1 0xFFC02EBC /* Mailbox 21 Identifier High Register */
850
851#define CAN_MB22_DATA0 0xFFC02EC0 /* Mailbox 22 Data Word 0 [15:0] Register */
852#define CAN_MB22_DATA1 0xFFC02EC4 /* Mailbox 22 Data Word 1 [31:16] Register */
853#define CAN_MB22_DATA2 0xFFC02EC8 /* Mailbox 22 Data Word 2 [47:32] Register */
854#define CAN_MB22_DATA3 0xFFC02ECC /* Mailbox 22 Data Word 3 [63:48] Register */
855#define CAN_MB22_LENGTH 0xFFC02ED0 /* Mailbox 22 Data Length Code Register */
856#define CAN_MB22_TIMESTAMP 0xFFC02ED4 /* Mailbox 22 Time Stamp Value Register */
857#define CAN_MB22_ID0 0xFFC02ED8 /* Mailbox 22 Identifier Low Register */
858#define CAN_MB22_ID1 0xFFC02EDC /* Mailbox 22 Identifier High Register */
859
860#define CAN_MB23_DATA0 0xFFC02EE0 /* Mailbox 23 Data Word 0 [15:0] Register */
861#define CAN_MB23_DATA1 0xFFC02EE4 /* Mailbox 23 Data Word 1 [31:16] Register */
862#define CAN_MB23_DATA2 0xFFC02EE8 /* Mailbox 23 Data Word 2 [47:32] Register */
863#define CAN_MB23_DATA3 0xFFC02EEC /* Mailbox 23 Data Word 3 [63:48] Register */
864#define CAN_MB23_LENGTH 0xFFC02EF0 /* Mailbox 23 Data Length Code Register */
865#define CAN_MB23_TIMESTAMP 0xFFC02EF4 /* Mailbox 23 Time Stamp Value Register */
866#define CAN_MB23_ID0 0xFFC02EF8 /* Mailbox 23 Identifier Low Register */
867#define CAN_MB23_ID1 0xFFC02EFC /* Mailbox 23 Identifier High Register */
868
869#define CAN_MB24_DATA0 0xFFC02F00 /* Mailbox 24 Data Word 0 [15:0] Register */
870#define CAN_MB24_DATA1 0xFFC02F04 /* Mailbox 24 Data Word 1 [31:16] Register */
871#define CAN_MB24_DATA2 0xFFC02F08 /* Mailbox 24 Data Word 2 [47:32] Register */
872#define CAN_MB24_DATA3 0xFFC02F0C /* Mailbox 24 Data Word 3 [63:48] Register */
873#define CAN_MB24_LENGTH 0xFFC02F10 /* Mailbox 24 Data Length Code Register */
874#define CAN_MB24_TIMESTAMP 0xFFC02F14 /* Mailbox 24 Time Stamp Value Register */
875#define CAN_MB24_ID0 0xFFC02F18 /* Mailbox 24 Identifier Low Register */
876#define CAN_MB24_ID1 0xFFC02F1C /* Mailbox 24 Identifier High Register */
877
878#define CAN_MB25_DATA0 0xFFC02F20 /* Mailbox 25 Data Word 0 [15:0] Register */
879#define CAN_MB25_DATA1 0xFFC02F24 /* Mailbox 25 Data Word 1 [31:16] Register */
880#define CAN_MB25_DATA2 0xFFC02F28 /* Mailbox 25 Data Word 2 [47:32] Register */
881#define CAN_MB25_DATA3 0xFFC02F2C /* Mailbox 25 Data Word 3 [63:48] Register */
882#define CAN_MB25_LENGTH 0xFFC02F30 /* Mailbox 25 Data Length Code Register */
883#define CAN_MB25_TIMESTAMP 0xFFC02F34 /* Mailbox 25 Time Stamp Value Register */
884#define CAN_MB25_ID0 0xFFC02F38 /* Mailbox 25 Identifier Low Register */
885#define CAN_MB25_ID1 0xFFC02F3C /* Mailbox 25 Identifier High Register */
886
887#define CAN_MB26_DATA0 0xFFC02F40 /* Mailbox 26 Data Word 0 [15:0] Register */
888#define CAN_MB26_DATA1 0xFFC02F44 /* Mailbox 26 Data Word 1 [31:16] Register */
889#define CAN_MB26_DATA2 0xFFC02F48 /* Mailbox 26 Data Word 2 [47:32] Register */
890#define CAN_MB26_DATA3 0xFFC02F4C /* Mailbox 26 Data Word 3 [63:48] Register */
891#define CAN_MB26_LENGTH 0xFFC02F50 /* Mailbox 26 Data Length Code Register */
892#define CAN_MB26_TIMESTAMP 0xFFC02F54 /* Mailbox 26 Time Stamp Value Register */
893#define CAN_MB26_ID0 0xFFC02F58 /* Mailbox 26 Identifier Low Register */
894#define CAN_MB26_ID1 0xFFC02F5C /* Mailbox 26 Identifier High Register */
895
896#define CAN_MB27_DATA0 0xFFC02F60 /* Mailbox 27 Data Word 0 [15:0] Register */
897#define CAN_MB27_DATA1 0xFFC02F64 /* Mailbox 27 Data Word 1 [31:16] Register */
898#define CAN_MB27_DATA2 0xFFC02F68 /* Mailbox 27 Data Word 2 [47:32] Register */
899#define CAN_MB27_DATA3 0xFFC02F6C /* Mailbox 27 Data Word 3 [63:48] Register */
900#define CAN_MB27_LENGTH 0xFFC02F70 /* Mailbox 27 Data Length Code Register */
901#define CAN_MB27_TIMESTAMP 0xFFC02F74 /* Mailbox 27 Time Stamp Value Register */
902#define CAN_MB27_ID0 0xFFC02F78 /* Mailbox 27 Identifier Low Register */
903#define CAN_MB27_ID1 0xFFC02F7C /* Mailbox 27 Identifier High Register */
904
905#define CAN_MB28_DATA0 0xFFC02F80 /* Mailbox 28 Data Word 0 [15:0] Register */
906#define CAN_MB28_DATA1 0xFFC02F84 /* Mailbox 28 Data Word 1 [31:16] Register */
907#define CAN_MB28_DATA2 0xFFC02F88 /* Mailbox 28 Data Word 2 [47:32] Register */
908#define CAN_MB28_DATA3 0xFFC02F8C /* Mailbox 28 Data Word 3 [63:48] Register */
909#define CAN_MB28_LENGTH 0xFFC02F90 /* Mailbox 28 Data Length Code Register */
910#define CAN_MB28_TIMESTAMP 0xFFC02F94 /* Mailbox 28 Time Stamp Value Register */
911#define CAN_MB28_ID0 0xFFC02F98 /* Mailbox 28 Identifier Low Register */
912#define CAN_MB28_ID1 0xFFC02F9C /* Mailbox 28 Identifier High Register */
913
914#define CAN_MB29_DATA0 0xFFC02FA0 /* Mailbox 29 Data Word 0 [15:0] Register */
915#define CAN_MB29_DATA1 0xFFC02FA4 /* Mailbox 29 Data Word 1 [31:16] Register */
916#define CAN_MB29_DATA2 0xFFC02FA8 /* Mailbox 29 Data Word 2 [47:32] Register */
917#define CAN_MB29_DATA3 0xFFC02FAC /* Mailbox 29 Data Word 3 [63:48] Register */
918#define CAN_MB29_LENGTH 0xFFC02FB0 /* Mailbox 29 Data Length Code Register */
919#define CAN_MB29_TIMESTAMP 0xFFC02FB4 /* Mailbox 29 Time Stamp Value Register */
920#define CAN_MB29_ID0 0xFFC02FB8 /* Mailbox 29 Identifier Low Register */
921#define CAN_MB29_ID1 0xFFC02FBC /* Mailbox 29 Identifier High Register */
922
923#define CAN_MB30_DATA0 0xFFC02FC0 /* Mailbox 30 Data Word 0 [15:0] Register */
924#define CAN_MB30_DATA1 0xFFC02FC4 /* Mailbox 30 Data Word 1 [31:16] Register */
925#define CAN_MB30_DATA2 0xFFC02FC8 /* Mailbox 30 Data Word 2 [47:32] Register */
926#define CAN_MB30_DATA3 0xFFC02FCC /* Mailbox 30 Data Word 3 [63:48] Register */
927#define CAN_MB30_LENGTH 0xFFC02FD0 /* Mailbox 30 Data Length Code Register */
928#define CAN_MB30_TIMESTAMP 0xFFC02FD4 /* Mailbox 30 Time Stamp Value Register */
929#define CAN_MB30_ID0 0xFFC02FD8 /* Mailbox 30 Identifier Low Register */
930#define CAN_MB30_ID1 0xFFC02FDC /* Mailbox 30 Identifier High Register */
931
932#define CAN_MB31_DATA0 0xFFC02FE0 /* Mailbox 31 Data Word 0 [15:0] Register */
933#define CAN_MB31_DATA1 0xFFC02FE4 /* Mailbox 31 Data Word 1 [31:16] Register */
934#define CAN_MB31_DATA2 0xFFC02FE8 /* Mailbox 31 Data Word 2 [47:32] Register */
935#define CAN_MB31_DATA3 0xFFC02FEC /* Mailbox 31 Data Word 3 [63:48] Register */
936#define CAN_MB31_LENGTH 0xFFC02FF0 /* Mailbox 31 Data Length Code Register */
937#define CAN_MB31_TIMESTAMP 0xFFC02FF4 /* Mailbox 31 Time Stamp Value Register */
938#define CAN_MB31_ID0 0xFFC02FF8 /* Mailbox 31 Identifier Low Register */
939#define CAN_MB31_ID1 0xFFC02FFC /* Mailbox 31 Identifier High Register */
940
941/* CAN Mailbox Area Macros */
942#define CAN_MB_ID1(x) (CAN_MB00_ID1+((x)*0x20))
943#define CAN_MB_ID0(x) (CAN_MB00_ID0+((x)*0x20))
944#define CAN_MB_TIMESTAMP(x) (CAN_MB00_TIMESTAMP+((x)*0x20))
945#define CAN_MB_LENGTH(x) (CAN_MB00_LENGTH+((x)*0x20))
946#define CAN_MB_DATA3(x) (CAN_MB00_DATA3+((x)*0x20))
947#define CAN_MB_DATA2(x) (CAN_MB00_DATA2+((x)*0x20))
948#define CAN_MB_DATA1(x) (CAN_MB00_DATA1+((x)*0x20))
949#define CAN_MB_DATA0(x) (CAN_MB00_DATA0+((x)*0x20))
950
951/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
952#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */
953#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */
954#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */
955#define BFIN_PORT_MUX 0xFFC0320C /* Port Multiplexer Control Register */
956
957/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
958#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */
959#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */
960#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */
961#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshhold Register */
962#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
963#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */
964#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */
965
966#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */
967#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */
968#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */
969#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshhold Register */
970#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
971#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */
972#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */
973
974/***********************************************************************************
975** System MMR Register Bits And Macros
976**
977** Disclaimer: All macros are intended to make C and Assembly code more readable.
978** Use these macros carefully, as any that do left shifts for field
979** depositing will result in the lower order bits being destroyed. Any
980** macro that shifts left to properly position the bit-field should be
981** used as part of an OR to initialize a register and NOT as a dynamic
982** modifier UNLESS the lower order bits are saved and ORed back in when
983** the macro is used.
984*************************************************************************************/
985/*
986** ********************* PLL AND RESET MASKS ****************************************/
987/* PLL_CTL Masks */
988#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
989#define PLL_OFF 0x0002 /* PLL Not Powered */
990#define STOPCK 0x0008 /* Core Clock Off */
991#define PDWN 0x0020 /* Enter Deep Sleep Mode */
992#define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */
993#define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */
994#define BYPASS 0x0100 /* Bypass the PLL */
995#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */
996/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */
997#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
998
999/* PLL_DIV Masks */
1000#define SSEL 0x000F /* System Select */
1001#define CSEL 0x0030 /* Core Select */
1002#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
1003#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
1004#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
1005#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
1006/* PLL_DIV Macros */
1007#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
1008
1009/* VR_CTL Masks */
1010#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */
1011#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
1012#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
1013#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
1014#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
1015
1016#define GAIN 0x000C /* Voltage Level Gain */
1017#define GAIN_5 0x0000 /* GAIN = 5 */
1018#define GAIN_10 0x0004 /* GAIN = 10 */
1019#define GAIN_20 0x0008 /* GAIN = 20 */
1020#define GAIN_50 0x000C /* GAIN = 50 */
1021
1022#define VLEV 0x00F0 /* Internal Voltage Level */
1023#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
1024#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
1025#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
1026#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
1027#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
1028#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
1029#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
1030#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
1031#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */
1032#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
1033
1034#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
1035#define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */
1036#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */
1037#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */
1038#define PHYCLKOE CLKBUFOE /* Alternative legacy name for the above */
1039#define SCKELOW 0x8000 /* Enable Drive CKE Low During Reset */
1040
1041/* PLL_STAT Masks */
1042#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
1043#define FULL_ON 0x0002 /* Processor In Full On Mode */
1044#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
1045#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
1046
1047/* CHIPID Masks */
1048#define CHIPID_VERSION 0xF0000000
1049#define CHIPID_FAMILY 0x0FFFF000
1050#define CHIPID_MANUFACTURE 0x00000FFE
1051
1052/* SWRST Masks */
1053#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
1054#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
1055#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
1056#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
1057#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
1058
1059/* SYSCR Masks */
1060#define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */
1061#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
1062
1063/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
1064
1065/* SIC_IAR0 Macros */
1066#define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */
1067#define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
1068#define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
1069#define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */
1070#define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
1071#define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
1072#define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
1073#define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
1074
1075/* SIC_IAR1 Macros */
1076#define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */
1077#define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
1078#define P10_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #10 assigned IVG #x */
1079#define P11_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #11 assigned IVG #x */
1080#define P12_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #12 assigned IVG #x */
1081#define P13_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #13 assigned IVG #x */
1082#define P14_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #14 assigned IVG #x */
1083#define P15_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
1084
1085/* SIC_IAR2 Macros */
1086#define P16_IVG(x) (((x)&0xF)-7) /* Peripheral #16 assigned IVG #x */
1087#define P17_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #17 assigned IVG #x */
1088#define P18_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #18 assigned IVG #x */
1089#define P19_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #19 assigned IVG #x */
1090#define P20_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #20 assigned IVG #x */
1091#define P21_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #21 assigned IVG #x */
1092#define P22_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #22 assigned IVG #x */
1093#define P23_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #23 assigned IVG #x */
1094
1095/* SIC_IAR3 Macros */
1096#define P24_IVG(x) (((x)&0xF)-7) /* Peripheral #24 assigned IVG #x */
1097#define P25_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #25 assigned IVG #x */
1098#define P26_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #26 assigned IVG #x */
1099#define P27_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #27 assigned IVG #x */
1100#define P28_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #28 assigned IVG #x */
1101#define P29_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #29 assigned IVG #x */
1102#define P30_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #30 assigned IVG #x */
1103#define P31_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #31 assigned IVG #x */
1104
1105/* SIC_IMASK Masks */
1106#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
1107#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
1108#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
1109#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
1110
1111/* SIC_IWR Masks */
1112#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
1113#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
1114#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
1115#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
1116
1117/* ************** UART CONTROLLER MASKS *************************/
1118/* UARTx_LCR Masks */
1119#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
1120#define STB 0x04 /* Stop Bits */
1121#define PEN 0x08 /* Parity Enable */
1122#define EPS 0x10 /* Even Parity Select */
1123#define STP 0x20 /* Stick Parity */
1124#define SB 0x40 /* Set Break */
1125#define DLAB 0x80 /* Divisor Latch Access */
1126
1127/* UARTx_MCR Mask */
1128#define LOOP_ENA 0x10 /* Loopback Mode Enable */
1129#define LOOP_ENA_P 0x04
1130/* UARTx_LSR Masks */
1131#define DR 0x01 /* Data Ready */
1132#define OE 0x02 /* Overrun Error */
1133#define PE 0x04 /* Parity Error */
1134#define FE 0x08 /* Framing Error */
1135#define BI 0x10 /* Break Interrupt */
1136#define THRE 0x20 /* THR Empty */
1137#define TEMT 0x40 /* TSR and UART_THR Empty */
1138
1139/* UARTx_IER Masks */
1140#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
1141#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
1142#define ELSI 0x04 /* Enable RX Status Interrupt */
1143
1144/* UARTx_IIR Masks */
1145#define NINT 0x01 /* Pending Interrupt */
1146#define IIR_TX_READY 0x02 /* UART_THR empty */
1147#define IIR_RX_READY 0x04 /* Receive data ready */
1148#define IIR_LINE_CHANGE 0x06 /* Receive line status */
1149#define IIR_STATUS 0x06
1150
1151/* UARTx_GCTL Masks */
1152#define UCEN 0x01 /* Enable UARTx Clocks */
1153#define IREN 0x02 /* Enable IrDA Mode */
1154#define TPOLC 0x04 /* IrDA TX Polarity Change */
1155#define RPOLC 0x08 /* IrDA RX Polarity Change */
1156#define FPE 0x10 /* Force Parity Error On Transmit */
1157#define FFE 0x20 /* Force Framing Error On Transmit */
1158
1159/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS ****************************/
1160/* SPI_CTL Masks */
1161#define TIMOD 0x0003 /* Transfer Initiate Mode */
1162#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */
1163#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */
1164#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */
1165#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */
1166#define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last*) */
1167#define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */
1168#define PSSE 0x0010 /* Slave-Select Input Enable */
1169#define EMISO 0x0020 /* Enable MISO As Output */
1170#define SIZE 0x0100 /* Size of Words (16/8* Bits) */
1171#define LSBF 0x0200 /* LSB First */
1172#define CPHA 0x0400 /* Clock Phase */
1173#define CPOL 0x0800 /* Clock Polarity */
1174#define MSTR 0x1000 /* Master/Slave* */
1175#define WOM 0x2000 /* Write Open Drain Master */
1176#define SPE 0x4000 /* SPI Enable */
1177
1178/* SPI_FLG Masks */
1179#define FLS1 0x0002 /* Enables SPI_FLOUT1 as SPI Slave-Select Output */
1180#define FLS2 0x0004 /* Enables SPI_FLOUT2 as SPI Slave-Select Output */
1181#define FLS3 0x0008 /* Enables SPI_FLOUT3 as SPI Slave-Select Output */
1182#define FLS4 0x0010 /* Enables SPI_FLOUT4 as SPI Slave-Select Output */
1183#define FLS5 0x0020 /* Enables SPI_FLOUT5 as SPI Slave-Select Output */
1184#define FLS6 0x0040 /* Enables SPI_FLOUT6 as SPI Slave-Select Output */
1185#define FLS7 0x0080 /* Enables SPI_FLOUT7 as SPI Slave-Select Output */
1186#define FLG1 0xFDFF /* Activates SPI_FLOUT1 */
1187#define FLG2 0xFBFF /* Activates SPI_FLOUT2 */
1188#define FLG3 0xF7FF /* Activates SPI_FLOUT3 */
1189#define FLG4 0xEFFF /* Activates SPI_FLOUT4 */
1190#define FLG5 0xDFFF /* Activates SPI_FLOUT5 */
1191#define FLG6 0xBFFF /* Activates SPI_FLOUT6 */
1192#define FLG7 0x7FFF /* Activates SPI_FLOUT7 */
1193
1194/* SPI_STAT Masks */
1195#define SPIF 0x0001 /* SPI Finished (Single-Word Transfer Complete) */
1196#define MODF 0x0002 /* Mode Fault Error (Another Device Tried To Become Master) */
1197#define TXE 0x0004 /* Transmission Error (Data Sent With No New Data In TDBR) */
1198#define TXS 0x0008 /* SPI_TDBR Data Buffer Status (Full/Empty*) */
1199#define RBSY 0x0010 /* Receive Error (Data Received With RDBR Full) */
1200#define RXS 0x0020 /* SPI_RDBR Data Buffer Status (Full/Empty*) */
1201#define TXCOL 0x0040 /* Transmit Collision Error (Corrupt Data May Have Been Sent) */
1202
1203/* **************** GENERAL PURPOSE TIMER MASKS **********************/
1204/* TIMER_ENABLE Masks */
1205#define TIMEN0 0x0001 /* Enable Timer 0 */
1206#define TIMEN1 0x0002 /* Enable Timer 1 */
1207#define TIMEN2 0x0004 /* Enable Timer 2 */
1208#define TIMEN3 0x0008 /* Enable Timer 3 */
1209#define TIMEN4 0x0010 /* Enable Timer 4 */
1210#define TIMEN5 0x0020 /* Enable Timer 5 */
1211#define TIMEN6 0x0040 /* Enable Timer 6 */
1212#define TIMEN7 0x0080 /* Enable Timer 7 */
1213
1214/* TIMER_DISABLE Masks */
1215#define TIMDIS0 TIMEN0 /* Disable Timer 0 */
1216#define TIMDIS1 TIMEN1 /* Disable Timer 1 */
1217#define TIMDIS2 TIMEN2 /* Disable Timer 2 */
1218#define TIMDIS3 TIMEN3 /* Disable Timer 3 */
1219#define TIMDIS4 TIMEN4 /* Disable Timer 4 */
1220#define TIMDIS5 TIMEN5 /* Disable Timer 5 */
1221#define TIMDIS6 TIMEN6 /* Disable Timer 6 */
1222#define TIMDIS7 TIMEN7 /* Disable Timer 7 */
1223
1224/* TIMER_STATUS Masks */
1225#define TIMIL0 0x00000001 /* Timer 0 Interrupt */
1226#define TIMIL1 0x00000002 /* Timer 1 Interrupt */
1227#define TIMIL2 0x00000004 /* Timer 2 Interrupt */
1228#define TIMIL3 0x00000008 /* Timer 3 Interrupt */
1229#define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */
1230#define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */
1231#define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */
1232#define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */
1233#define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */
1234#define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */
1235#define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */
1236#define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */
1237#define TIMIL4 0x00010000 /* Timer 4 Interrupt */
1238#define TIMIL5 0x00020000 /* Timer 5 Interrupt */
1239#define TIMIL6 0x00040000 /* Timer 6 Interrupt */
1240#define TIMIL7 0x00080000 /* Timer 7 Interrupt */
1241#define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */
1242#define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */
1243#define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */
1244#define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */
1245#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */
1246#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */
1247#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
1248#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
1249
1250/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
1251#define TOVL_ERR0 TOVF_ERR0
1252#define TOVL_ERR1 TOVF_ERR1
1253#define TOVL_ERR2 TOVF_ERR2
1254#define TOVL_ERR3 TOVF_ERR3
1255#define TOVL_ERR4 TOVF_ERR4
1256#define TOVL_ERR5 TOVF_ERR5
1257#define TOVL_ERR6 TOVF_ERR6
1258#define TOVL_ERR7 TOVF_ERR7
1259/* TIMERx_CONFIG Masks */
1260#define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */
1261#define WDTH_CAP 0x0002 /* Width Capture Input Mode */
1262#define EXT_CLK 0x0003 /* External Clock Mode */
1263#define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */
1264#define PERIOD_CNT 0x0008 /* Period Count */
1265#define IRQ_ENA 0x0010 /* Interrupt Request Enable */
1266#define TIN_SEL 0x0020 /* Timer Input Select */
1267#define OUT_DIS 0x0040 /* Output Pad Disable */
1268#define CLK_SEL 0x0080 /* Timer Clock Select */
1269#define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */
1270#define EMU_RUN 0x0200 /* Emulation Behavior Select */
1271#define ERR_TYP 0xC000 /* Error Type */
1272
1273/* ****************** GPIO PORTS F, G, H MASKS ***********************/
1274/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */
1275/* Port F Masks */
1276#define PF0 0x0001
1277#define PF1 0x0002
1278#define PF2 0x0004
1279#define PF3 0x0008
1280#define PF4 0x0010
1281#define PF5 0x0020
1282#define PF6 0x0040
1283#define PF7 0x0080
1284#define PF8 0x0100
1285#define PF9 0x0200
1286#define PF10 0x0400
1287#define PF11 0x0800
1288#define PF12 0x1000
1289#define PF13 0x2000
1290#define PF14 0x4000
1291#define PF15 0x8000
1292
1293/* Port G Masks */
1294#define PG0 0x0001
1295#define PG1 0x0002
1296#define PG2 0x0004
1297#define PG3 0x0008
1298#define PG4 0x0010
1299#define PG5 0x0020
1300#define PG6 0x0040
1301#define PG7 0x0080
1302#define PG8 0x0100
1303#define PG9 0x0200
1304#define PG10 0x0400
1305#define PG11 0x0800
1306#define PG12 0x1000
1307#define PG13 0x2000
1308#define PG14 0x4000
1309#define PG15 0x8000
1310
1311/* Port H Masks */
1312#define PH0 0x0001
1313#define PH1 0x0002
1314#define PH2 0x0004
1315#define PH3 0x0008
1316#define PH4 0x0010
1317#define PH5 0x0020
1318#define PH6 0x0040
1319#define PH7 0x0080
1320#define PH8 0x0100
1321#define PH9 0x0200
1322#define PH10 0x0400
1323#define PH11 0x0800
1324#define PH12 0x1000
1325#define PH13 0x2000
1326#define PH14 0x4000
1327#define PH15 0x8000
1328
1329/* ******************* SERIAL PORT MASKS **************************************/
1330/* SPORTx_TCR1 Masks */
1331#define TSPEN 0x0001 /* Transmit Enable */
1332#define ITCLK 0x0002 /* Internal Transmit Clock Select */
1333#define DTYPE_NORM 0x0004 /* Data Format Normal */
1334#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
1335#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
1336#define TLSBIT 0x0010 /* Transmit Bit Order */
1337#define ITFS 0x0200 /* Internal Transmit Frame Sync Select */
1338#define TFSR 0x0400 /* Transmit Frame Sync Required Select */
1339#define DITFS 0x0800 /* Data-Independent Transmit Frame Sync Select */
1340#define LTFS 0x1000 /* Low Transmit Frame Sync Select */
1341#define LATFS 0x2000 /* Late Transmit Frame Sync Select */
1342#define TCKFE 0x4000 /* Clock Falling Edge Select */
1343
1344/* SPORTx_TCR2 Masks and Macro */
1345#define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
1346#define TXSE 0x0100 /* TX Secondary Enable */
1347#define TSFSE 0x0200 /* Transmit Stereo Frame Sync Enable */
1348#define TRFST 0x0400 /* Left/Right Order (1 = Right Channel 1st) */
1349
1350/* SPORTx_RCR1 Masks */
1351#define RSPEN 0x0001 /* Receive Enable */
1352#define IRCLK 0x0002 /* Internal Receive Clock Select */
1353#define DTYPE_NORM 0x0004 /* Data Format Normal */
1354#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
1355#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
1356#define RLSBIT 0x0010 /* Receive Bit Order */
1357#define IRFS 0x0200 /* Internal Receive Frame Sync Select */
1358#define RFSR 0x0400 /* Receive Frame Sync Required Select */
1359#define LRFS 0x1000 /* Low Receive Frame Sync Select */
1360#define LARFS 0x2000 /* Late Receive Frame Sync Select */
1361#define RCKFE 0x4000 /* Clock Falling Edge Select */
1362
1363/* SPORTx_RCR2 Masks */
1364#define SLEN(x) ((x)&0x1F) /* SPORT RX Word Length (2 - 31) */
1365#define RXSE 0x0100 /* RX Secondary Enable */
1366#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */
1367#define RRFST 0x0400 /* Right-First Data Order */
1368
1369/* SPORTx_STAT Masks */
1370#define RXNE 0x0001 /* Receive FIFO Not Empty Status */
1371#define RUVF 0x0002 /* Sticky Receive Underflow Status */
1372#define ROVF 0x0004 /* Sticky Receive Overflow Status */
1373#define TXF 0x0008 /* Transmit FIFO Full Status */
1374#define TUVF 0x0010 /* Sticky Transmit Underflow Status */
1375#define TOVF 0x0020 /* Sticky Transmit Overflow Status */
1376#define TXHRE 0x0040 /* Transmit Hold Register Empty */
1377
1378/* SPORTx_MCMC1 Macros */
1379#define SP_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
1380
1381/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits */
1382#define SP_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
1383
1384/* SPORTx_MCMC2 Masks */
1385#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
1386#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
1387#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
1388#define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */
1389#define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */
1390#define MCMEN 0x0010 /* Multichannel Frame Mode Enable */
1391#define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */
1392#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */
1393#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */
1394#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */
1395#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */
1396#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */
1397#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */
1398#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */
1399#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */
1400#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */
1401#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */
1402#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */
1403#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */
1404#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */
1405#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */
1406#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */
1407#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */
1408
1409/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
1410/* EBIU_AMGCTL Masks */
1411#define AMCKEN 0x0001 /* Enable CLKOUT */
1412#define AMBEN_NONE 0x0000 /* All Banks Disabled */
1413#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */
1414#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */
1415#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */
1416#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */
1417
1418/* EBIU_AMBCTL0 Masks */
1419#define B0RDYEN 0x00000001 /* Bank 0 (B0) RDY Enable */
1420#define B0RDYPOL 0x00000002 /* B0 RDY Active High */
1421#define B0TT_1 0x00000004 /* B0 Transition Time (Read to Write) = 1 cycle */
1422#define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */
1423#define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */
1424#define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */
1425#define B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */
1426#define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */
1427#define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */
1428#define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */
1429#define B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */
1430#define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1431#define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1432#define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1433#define B0RAT_1 0x00000100 /* B0 Read Access Time = 1 cycle */
1434#define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */
1435#define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */
1436#define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */
1437#define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */
1438#define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */
1439#define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */
1440#define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */
1441#define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */
1442#define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */
1443#define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */
1444#define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */
1445#define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */
1446#define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */
1447#define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */
1448#define B0WAT_1 0x00001000 /* B0 Write Access Time = 1 cycle */
1449#define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */
1450#define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */
1451#define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */
1452#define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */
1453#define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */
1454#define B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */
1455#define B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */
1456#define B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */
1457#define B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */
1458#define B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */
1459#define B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */
1460#define B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */
1461#define B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */
1462#define B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */
1463
1464#define B1RDYEN 0x00010000 /* Bank 1 (B1) RDY Enable */
1465#define B1RDYPOL 0x00020000 /* B1 RDY Active High */
1466#define B1TT_1 0x00040000 /* B1 Transition Time (Read to Write) = 1 cycle */
1467#define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */
1468#define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */
1469#define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */
1470#define B1ST_1 0x00100000 /* B1 Setup Time (AOE to Read/Write) = 1 cycle */
1471#define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */
1472#define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */
1473#define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */
1474#define B1HT_1 0x00400000 /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */
1475#define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1476#define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1477#define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1478#define B1RAT_1 0x01000000 /* B1 Read Access Time = 1 cycle */
1479#define B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */
1480#define B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */
1481#define B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */
1482#define B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */
1483#define B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */
1484#define B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */
1485#define B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */
1486#define B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */
1487#define B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */
1488#define B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */
1489#define B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */
1490#define B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */
1491#define B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */
1492#define B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */
1493#define B1WAT_1 0x10000000 /* B1 Write Access Time = 1 cycle */
1494#define B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */
1495#define B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */
1496#define B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */
1497#define B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */
1498#define B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */
1499#define B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */
1500#define B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */
1501#define B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */
1502#define B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */
1503#define B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */
1504#define B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */
1505#define B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */
1506#define B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */
1507#define B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */
1508
1509/* EBIU_AMBCTL1 Masks */
1510#define B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */
1511#define B2RDYPOL 0x00000002 /* B2 RDY Active High */
1512#define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */
1513#define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */
1514#define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */
1515#define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */
1516#define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */
1517#define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */
1518#define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */
1519#define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */
1520#define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */
1521#define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1522#define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1523#define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1524#define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */
1525#define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */
1526#define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */
1527#define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */
1528#define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */
1529#define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */
1530#define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */
1531#define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */
1532#define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */
1533#define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */
1534#define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */
1535#define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */
1536#define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */
1537#define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */
1538#define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */
1539#define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */
1540#define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */
1541#define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */
1542#define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */
1543#define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */
1544#define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */
1545#define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */
1546#define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */
1547#define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */
1548#define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */
1549#define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */
1550#define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */
1551#define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */
1552#define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */
1553#define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */
1554
1555#define B3RDYEN 0x00010000 /* Bank 3 (B3) RDY Enable */
1556#define B3RDYPOL 0x00020000 /* B3 RDY Active High */
1557#define B3TT_1 0x00040000 /* B3 Transition Time (Read to Write) = 1 cycle */
1558#define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */
1559#define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */
1560#define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */
1561#define B3ST_1 0x00100000 /* B3 Setup Time (AOE to Read/Write) = 1 cycle */
1562#define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */
1563#define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */
1564#define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */
1565#define B3HT_1 0x00400000 /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */
1566#define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1567#define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1568#define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1569#define B3RAT_1 0x01000000 /* B3 Read Access Time = 1 cycle */
1570#define B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */
1571#define B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */
1572#define B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */
1573#define B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */
1574#define B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */
1575#define B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */
1576#define B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */
1577#define B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */
1578#define B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */
1579#define B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */
1580#define B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */
1581#define B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */
1582#define B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */
1583#define B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */
1584#define B3WAT_1 0x10000000 /* B3 Write Access Time = 1 cycle */
1585#define B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */
1586#define B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */
1587#define B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */
1588#define B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */
1589#define B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */
1590#define B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */
1591#define B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */
1592#define B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */
1593#define B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */
1594#define B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */
1595#define B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */
1596#define B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */
1597#define B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */
1598#define B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */
1599
1600/* ********************** SDRAM CONTROLLER MASKS **********************************************/
1601/* EBIU_SDGCTL Masks */
1602#define SCTLE 0x00000001 /* Enable SDRAM Signals */
1603#define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */
1604#define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */
1605#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
1606#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
1607#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
1608#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
1609#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
1610#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
1611#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
1612#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
1613#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
1614#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
1615#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
1616#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
1617#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
1618#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
1619#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
1620#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
1621#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
1622#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
1623#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
1624#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
1625#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
1626#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
1627#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
1628#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
1629#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
1630#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
1631#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
1632#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
1633#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
1634#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
1635#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
1636#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
1637#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
1638#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
1639#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
1640#define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */
1641#define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */
1642#define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */
1643#define SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode */
1644#define EBUFE 0x02000000 /* Enable External Buffering Timing */
1645#define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */
1646#define EMREN 0x10000000 /* Extended Mode Register Enable */
1647#define TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */
1648#define CDDBG 0x40000000 /* Tristate SDRAM Controls During Bus Grant */
1649
1650/* EBIU_SDBCTL Masks */
1651#define EBE 0x0001 /* Enable SDRAM External Bank */
1652#define EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */
1653#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */
1654#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */
1655#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */
1656#define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */
1657#define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */
1658#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */
1659#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */
1660#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */
1661#define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */
1662
1663/* EBIU_SDSTAT Masks */
1664#define SDCI 0x0001 /* SDRAM Controller Idle */
1665#define SDSRA 0x0002 /* SDRAM Self-Refresh Active */
1666#define SDPUA 0x0004 /* SDRAM Power-Up Active */
1667#define SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */
1668#define SDEASE 0x0010 /* SDRAM EAB Sticky Error Status */
1669#define BGSTAT 0x0020 /* Bus Grant Status */
1670
1671/* ************************** DMA CONTROLLER MASKS ********************************/
1672/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */
1673#define DMAEN 0x0001 /* DMA Channel Enable */
1674#define WNR 0x0002 /* Channel Direction (W/R*) */
1675#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */
1676#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */
1677#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */
1678#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */
1679#define RESTART 0x0020 /* DMA Buffer Clear */
1680#define DI_SEL 0x0040 /* Data Interrupt Timing Select */
1681#define DI_EN 0x0080 /* Data Interrupt Enable */
1682#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
1683#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
1684#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
1685#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
1686#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
1687#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
1688#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
1689#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
1690#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
1691#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
1692#define NDSIZE 0x0900 /* Next Descriptor Size */
1693
1694#define DMAFLOW 0x7000 /* Flow Control */
1695#define DMAFLOW_STOP 0x0000 /* Stop Mode */
1696#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
1697#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
1698#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
1699#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
1700
1701/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
1702#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */
1703#define PMAP 0xF000 /* Peripheral Mapped To This Channel */
1704#define PMAP_PPI 0x0000 /* PPI Port DMA */
1705#define PMAP_EMACRX 0x1000 /* Ethernet Receive DMA */
1706#define PMAP_EMACTX 0x2000 /* Ethernet Transmit DMA */
1707#define PMAP_SPORT0RX 0x3000 /* SPORT0 Receive DMA */
1708#define PMAP_SPORT0TX 0x4000 /* SPORT0 Transmit DMA */
1709#define PMAP_SPORT1RX 0x5000 /* SPORT1 Receive DMA */
1710#define PMAP_SPORT1TX 0x6000 /* SPORT1 Transmit DMA */
1711#define PMAP_SPI 0x7000 /* SPI Port DMA */
1712#define PMAP_UART0RX 0x8000 /* UART0 Port Receive DMA */
1713#define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */
1714#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */
1715#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */
1716
1717/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
1718#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */
1719#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */
1720#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */
1721#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */
1722
1723/* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
1724/* PPI_CONTROL Masks */
1725#define PORT_EN 0x0001 /* PPI Port Enable */
1726#define PORT_DIR 0x0002 /* PPI Port Direction */
1727#define XFR_TYPE 0x000C /* PPI Transfer Type */
1728#define PORT_CFG 0x0030 /* PPI Port Configuration */
1729#define FLD_SEL 0x0040 /* PPI Active Field Select */
1730#define PACK_EN 0x0080 /* PPI Packing Mode */
1731#define DMA32 0x0100 /* PPI 32-bit DMA Enable */
1732#define SKIP_EN 0x0200 /* PPI Skip Element Enable */
1733#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */
1734#define DLENGTH 0x3800 /* PPI Data Length */
1735#define DLEN_8 0x0000 /* Data Length = 8 Bits */
1736#define DLEN_10 0x0800 /* Data Length = 10 Bits */
1737#define DLEN_11 0x1000 /* Data Length = 11 Bits */
1738#define DLEN_12 0x1800 /* Data Length = 12 Bits */
1739#define DLEN_13 0x2000 /* Data Length = 13 Bits */
1740#define DLEN_14 0x2800 /* Data Length = 14 Bits */
1741#define DLEN_15 0x3000 /* Data Length = 15 Bits */
1742#define DLEN_16 0x3800 /* Data Length = 16 Bits */
1743#define POLC 0x4000 /* PPI Clock Polarity */
1744#define POLS 0x8000 /* PPI Frame Sync Polarity */
1745
1746/* PPI_STATUS Masks */
1747#define FLD 0x0400 /* Field Indicator */
1748#define FT_ERR 0x0800 /* Frame Track Error */
1749#define OVR 0x1000 /* FIFO Overflow Error */
1750#define UNDR 0x2000 /* FIFO Underrun Error */
1751#define ERR_DET 0x4000 /* Error Detected Indicator */
1752#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
1753
1754/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/
1755/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
1756#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
1757#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
1758
1759/* TWI_PRESCALE Masks */
1760#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
1761#define TWI_ENA 0x0080 /* TWI Enable */
1762#define SCCB 0x0200 /* SCCB Compatibility Enable */
1763
1764/* TWI_SLAVE_CTRL Masks */
1765#define SEN 0x0001 /* Slave Enable */
1766#define SADD_LEN 0x0002 /* Slave Address Length */
1767#define STDVAL 0x0004 /* Slave Transmit Data Valid */
1768#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
1769#define GEN 0x0010 /* General Call Adrress Matching Enabled */
1770
1771/* TWI_SLAVE_STAT Masks */
1772#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
1773#define GCALL 0x0002 /* General Call Indicator */
1774
1775/* TWI_MASTER_CTRL Masks */
1776#define MEN 0x0001 /* Master Mode Enable */
1777#define MADD_LEN 0x0002 /* Master Address Length */
1778#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
1779#define FAST 0x0008 /* Use Fast Mode Timing Specs */
1780#define STOP 0x0010 /* Issue Stop Condition */
1781#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */
1782#define DCNT 0x3FC0 /* Data Bytes To Transfer */
1783#define SDAOVR 0x4000 /* Serial Data Override */
1784#define SCLOVR 0x8000 /* Serial Clock Override */
1785
1786/* TWI_MASTER_STAT Masks */
1787#define MPROG 0x0001 /* Master Transfer In Progress */
1788#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */
1789#define ANAK 0x0004 /* Address Not Acknowledged */
1790#define DNAK 0x0008 /* Data Not Acknowledged */
1791#define BUFRDERR 0x0010 /* Buffer Read Error */
1792#define BUFWRERR 0x0020 /* Buffer Write Error */
1793#define SDASEN 0x0040 /* Serial Data Sense */
1794#define SCLSEN 0x0080 /* Serial Clock Sense */
1795#define BUSBUSY 0x0100 /* Bus Busy Indicator */
1796
1797/* TWI_INT_SRC and TWI_INT_ENABLE Masks */
1798#define SINIT 0x0001 /* Slave Transfer Initiated */
1799#define SCOMP 0x0002 /* Slave Transfer Complete */
1800#define SERR 0x0004 /* Slave Transfer Error */
1801#define SOVF 0x0008 /* Slave Overflow */
1802#define MCOMP 0x0010 /* Master Transfer Complete */
1803#define MERR 0x0020 /* Master Transfer Error */
1804#define XMTSERV 0x0040 /* Transmit FIFO Service */
1805#define RCVSERV 0x0080 /* Receive FIFO Service */
1806
1807/* TWI_FIFO_CTRL Masks */
1808#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
1809#define RCVFLUSH 0x0002 /* Receive Buffer Flush */
1810#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */
1811#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */
1812
1813/* TWI_FIFO_STAT Masks */
1814#define XMTSTAT 0x0003 /* Transmit FIFO Status */
1815#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */
1816#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */
1817#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */
1818
1819#define RCVSTAT 0x000C /* Receive FIFO Status */
1820#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */
1821#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
1822#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
1823
1824/* ************ CONTROLLER AREA NETWORK (CAN) MASKS ***************/
1825/* CAN_CONTROL Masks */
1826#define SRS 0x0001 /* Software Reset */
1827#define DNM 0x0002 /* Device Net Mode */
1828#define ABO 0x0004 /* Auto-Bus On Enable */
1829#define TXPRIO 0x0008 /* TX Priority (Priority/Mailbox*) */
1830#define WBA 0x0010 /* Wake-Up On CAN Bus Activity Enable */
1831#define SMR 0x0020 /* Sleep Mode Request */
1832#define CSR 0x0040 /* CAN Suspend Mode Request */
1833#define CCR 0x0080 /* CAN Configuration Mode Request */
1834
1835/* CAN_STATUS Masks */
1836#define WT 0x0001 /* TX Warning Flag */
1837#define WR 0x0002 /* RX Warning Flag */
1838#define EP 0x0004 /* Error Passive Mode */
1839#define EBO 0x0008 /* Error Bus Off Mode */
1840#define SMA 0x0020 /* Sleep Mode Acknowledge */
1841#define CSA 0x0040 /* Suspend Mode Acknowledge */
1842#define CCA 0x0080 /* Configuration Mode Acknowledge */
1843#define MBPTR 0x1F00 /* Mailbox Pointer */
1844#define TRM 0x4000 /* Transmit Mode */
1845#define REC 0x8000 /* Receive Mode */
1846
1847/* CAN_CLOCK Masks */
1848#define BRP 0x03FF /* Bit-Rate Pre-Scaler */
1849
1850/* CAN_TIMING Masks */
1851#define TSEG1 0x000F /* Time Segment 1 */
1852#define TSEG2 0x0070 /* Time Segment 2 */
1853#define SAM 0x0080 /* Sampling */
1854#define SJW 0x0300 /* Synchronization Jump Width */
1855
1856/* CAN_DEBUG Masks */
1857#define DEC 0x0001 /* Disable CAN Error Counters */
1858#define DRI 0x0002 /* Disable CAN RX Input */
1859#define DTO 0x0004 /* Disable CAN TX Output */
1860#define DIL 0x0008 /* Disable CAN Internal Loop */
1861#define MAA 0x0010 /* Mode Auto-Acknowledge Enable */
1862#define MRB 0x0020 /* Mode Read Back Enable */
1863#define CDE 0x8000 /* CAN Debug Enable */
1864
1865/* CAN_CEC Masks */
1866#define RXECNT 0x00FF /* Receive Error Counter */
1867#define TXECNT 0xFF00 /* Transmit Error Counter */
1868
1869/* CAN_INTR Masks */
1870#define MBRIRQ 0x0001 /* Mailbox Receive Interrupt */
1871#define MBRIF MBRIRQ /* legacy */
1872#define MBTIRQ 0x0002 /* Mailbox Transmit Interrupt */
1873#define MBTIF MBTIRQ /* legacy */
1874#define GIRQ 0x0004 /* Global Interrupt */
1875#define SMACK 0x0008 /* Sleep Mode Acknowledge */
1876#define CANTX 0x0040 /* CAN TX Bus Value */
1877#define CANRX 0x0080 /* CAN RX Bus Value */
1878
1879/* CAN_MBxx_ID1 and CAN_MBxx_ID0 Masks */
1880#define DFC 0xFFFF /* Data Filtering Code (If Enabled) (ID0) */
1881#define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (ID0) */
1882#define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (ID1) */
1883#define BASEID 0x1FFC /* Base Identifier */
1884#define IDE 0x2000 /* Identifier Extension */
1885#define RTR 0x4000 /* Remote Frame Transmission Request */
1886#define AME 0x8000 /* Acceptance Mask Enable */
1887
1888/* CAN_MBxx_TIMESTAMP Masks */
1889#define TSV 0xFFFF /* Timestamp */
1890
1891/* CAN_MBxx_LENGTH Masks */
1892#define DLC 0x000F /* Data Length Code */
1893
1894/* CAN_AMxxH and CAN_AMxxL Masks */
1895#define DFM 0xFFFF /* Data Field Mask (If Enabled) (CAN_AMxxL) */
1896#define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (CAN_AMxxL) */
1897#define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (CAN_AMxxH) */
1898#define BASEID 0x1FFC /* Base Identifier */
1899#define AMIDE 0x2000 /* Acceptance Mask ID Extension Enable */
1900#define FMD 0x4000 /* Full Mask Data Field Enable */
1901#define FDF 0x8000 /* Filter On Data Field Enable */
1902
1903/* CAN_MC1 Masks */
1904#define MC0 0x0001 /* Enable Mailbox 0 */
1905#define MC1 0x0002 /* Enable Mailbox 1 */
1906#define MC2 0x0004 /* Enable Mailbox 2 */
1907#define MC3 0x0008 /* Enable Mailbox 3 */
1908#define MC4 0x0010 /* Enable Mailbox 4 */
1909#define MC5 0x0020 /* Enable Mailbox 5 */
1910#define MC6 0x0040 /* Enable Mailbox 6 */
1911#define MC7 0x0080 /* Enable Mailbox 7 */
1912#define MC8 0x0100 /* Enable Mailbox 8 */
1913#define MC9 0x0200 /* Enable Mailbox 9 */
1914#define MC10 0x0400 /* Enable Mailbox 10 */
1915#define MC11 0x0800 /* Enable Mailbox 11 */
1916#define MC12 0x1000 /* Enable Mailbox 12 */
1917#define MC13 0x2000 /* Enable Mailbox 13 */
1918#define MC14 0x4000 /* Enable Mailbox 14 */
1919#define MC15 0x8000 /* Enable Mailbox 15 */
1920
1921/* CAN_MC2 Masks */
1922#define MC16 0x0001 /* Enable Mailbox 16 */
1923#define MC17 0x0002 /* Enable Mailbox 17 */
1924#define MC18 0x0004 /* Enable Mailbox 18 */
1925#define MC19 0x0008 /* Enable Mailbox 19 */
1926#define MC20 0x0010 /* Enable Mailbox 20 */
1927#define MC21 0x0020 /* Enable Mailbox 21 */
1928#define MC22 0x0040 /* Enable Mailbox 22 */
1929#define MC23 0x0080 /* Enable Mailbox 23 */
1930#define MC24 0x0100 /* Enable Mailbox 24 */
1931#define MC25 0x0200 /* Enable Mailbox 25 */
1932#define MC26 0x0400 /* Enable Mailbox 26 */
1933#define MC27 0x0800 /* Enable Mailbox 27 */
1934#define MC28 0x1000 /* Enable Mailbox 28 */
1935#define MC29 0x2000 /* Enable Mailbox 29 */
1936#define MC30 0x4000 /* Enable Mailbox 30 */
1937#define MC31 0x8000 /* Enable Mailbox 31 */
1938
1939/* CAN_MD1 Masks */
1940#define MD0 0x0001 /* Enable Mailbox 0 For Receive */
1941#define MD1 0x0002 /* Enable Mailbox 1 For Receive */
1942#define MD2 0x0004 /* Enable Mailbox 2 For Receive */
1943#define MD3 0x0008 /* Enable Mailbox 3 For Receive */
1944#define MD4 0x0010 /* Enable Mailbox 4 For Receive */
1945#define MD5 0x0020 /* Enable Mailbox 5 For Receive */
1946#define MD6 0x0040 /* Enable Mailbox 6 For Receive */
1947#define MD7 0x0080 /* Enable Mailbox 7 For Receive */
1948#define MD8 0x0100 /* Enable Mailbox 8 For Receive */
1949#define MD9 0x0200 /* Enable Mailbox 9 For Receive */
1950#define MD10 0x0400 /* Enable Mailbox 10 For Receive */
1951#define MD11 0x0800 /* Enable Mailbox 11 For Receive */
1952#define MD12 0x1000 /* Enable Mailbox 12 For Receive */
1953#define MD13 0x2000 /* Enable Mailbox 13 For Receive */
1954#define MD14 0x4000 /* Enable Mailbox 14 For Receive */
1955#define MD15 0x8000 /* Enable Mailbox 15 For Receive */
1956
1957/* CAN_MD2 Masks */
1958#define MD16 0x0001 /* Enable Mailbox 16 For Receive */
1959#define MD17 0x0002 /* Enable Mailbox 17 For Receive */
1960#define MD18 0x0004 /* Enable Mailbox 18 For Receive */
1961#define MD19 0x0008 /* Enable Mailbox 19 For Receive */
1962#define MD20 0x0010 /* Enable Mailbox 20 For Receive */
1963#define MD21 0x0020 /* Enable Mailbox 21 For Receive */
1964#define MD22 0x0040 /* Enable Mailbox 22 For Receive */
1965#define MD23 0x0080 /* Enable Mailbox 23 For Receive */
1966#define MD24 0x0100 /* Enable Mailbox 24 For Receive */
1967#define MD25 0x0200 /* Enable Mailbox 25 For Receive */
1968#define MD26 0x0400 /* Enable Mailbox 26 For Receive */
1969#define MD27 0x0800 /* Enable Mailbox 27 For Receive */
1970#define MD28 0x1000 /* Enable Mailbox 28 For Receive */
1971#define MD29 0x2000 /* Enable Mailbox 29 For Receive */
1972#define MD30 0x4000 /* Enable Mailbox 30 For Receive */
1973#define MD31 0x8000 /* Enable Mailbox 31 For Receive */
1974
1975/* CAN_RMP1 Masks */
1976#define RMP0 0x0001 /* RX Message Pending In Mailbox 0 */
1977#define RMP1 0x0002 /* RX Message Pending In Mailbox 1 */
1978#define RMP2 0x0004 /* RX Message Pending In Mailbox 2 */
1979#define RMP3 0x0008 /* RX Message Pending In Mailbox 3 */
1980#define RMP4 0x0010 /* RX Message Pending In Mailbox 4 */
1981#define RMP5 0x0020 /* RX Message Pending In Mailbox 5 */
1982#define RMP6 0x0040 /* RX Message Pending In Mailbox 6 */
1983#define RMP7 0x0080 /* RX Message Pending In Mailbox 7 */
1984#define RMP8 0x0100 /* RX Message Pending In Mailbox 8 */
1985#define RMP9 0x0200 /* RX Message Pending In Mailbox 9 */
1986#define RMP10 0x0400 /* RX Message Pending In Mailbox 10 */
1987#define RMP11 0x0800 /* RX Message Pending In Mailbox 11 */
1988#define RMP12 0x1000 /* RX Message Pending In Mailbox 12 */
1989#define RMP13 0x2000 /* RX Message Pending In Mailbox 13 */
1990#define RMP14 0x4000 /* RX Message Pending In Mailbox 14 */
1991#define RMP15 0x8000 /* RX Message Pending In Mailbox 15 */
1992
1993/* CAN_RMP2 Masks */
1994#define RMP16 0x0001 /* RX Message Pending In Mailbox 16 */
1995#define RMP17 0x0002 /* RX Message Pending In Mailbox 17 */
1996#define RMP18 0x0004 /* RX Message Pending In Mailbox 18 */
1997#define RMP19 0x0008 /* RX Message Pending In Mailbox 19 */
1998#define RMP20 0x0010 /* RX Message Pending In Mailbox 20 */
1999#define RMP21 0x0020 /* RX Message Pending In Mailbox 21 */
2000#define RMP22 0x0040 /* RX Message Pending In Mailbox 22 */
2001#define RMP23 0x0080 /* RX Message Pending In Mailbox 23 */
2002#define RMP24 0x0100 /* RX Message Pending In Mailbox 24 */
2003#define RMP25 0x0200 /* RX Message Pending In Mailbox 25 */
2004#define RMP26 0x0400 /* RX Message Pending In Mailbox 26 */
2005#define RMP27 0x0800 /* RX Message Pending In Mailbox 27 */
2006#define RMP28 0x1000 /* RX Message Pending In Mailbox 28 */
2007#define RMP29 0x2000 /* RX Message Pending In Mailbox 29 */
2008#define RMP30 0x4000 /* RX Message Pending In Mailbox 30 */
2009#define RMP31 0x8000 /* RX Message Pending In Mailbox 31 */
2010
2011/* CAN_RML1 Masks */
2012#define RML0 0x0001 /* RX Message Lost In Mailbox 0 */
2013#define RML1 0x0002 /* RX Message Lost In Mailbox 1 */
2014#define RML2 0x0004 /* RX Message Lost In Mailbox 2 */
2015#define RML3 0x0008 /* RX Message Lost In Mailbox 3 */
2016#define RML4 0x0010 /* RX Message Lost In Mailbox 4 */
2017#define RML5 0x0020 /* RX Message Lost In Mailbox 5 */
2018#define RML6 0x0040 /* RX Message Lost In Mailbox 6 */
2019#define RML7 0x0080 /* RX Message Lost In Mailbox 7 */
2020#define RML8 0x0100 /* RX Message Lost In Mailbox 8 */
2021#define RML9 0x0200 /* RX Message Lost In Mailbox 9 */
2022#define RML10 0x0400 /* RX Message Lost In Mailbox 10 */
2023#define RML11 0x0800 /* RX Message Lost In Mailbox 11 */
2024#define RML12 0x1000 /* RX Message Lost In Mailbox 12 */
2025#define RML13 0x2000 /* RX Message Lost In Mailbox 13 */
2026#define RML14 0x4000 /* RX Message Lost In Mailbox 14 */
2027#define RML15 0x8000 /* RX Message Lost In Mailbox 15 */
2028
2029/* CAN_RML2 Masks */
2030#define RML16 0x0001 /* RX Message Lost In Mailbox 16 */
2031#define RML17 0x0002 /* RX Message Lost In Mailbox 17 */
2032#define RML18 0x0004 /* RX Message Lost In Mailbox 18 */
2033#define RML19 0x0008 /* RX Message Lost In Mailbox 19 */
2034#define RML20 0x0010 /* RX Message Lost In Mailbox 20 */
2035#define RML21 0x0020 /* RX Message Lost In Mailbox 21 */
2036#define RML22 0x0040 /* RX Message Lost In Mailbox 22 */
2037#define RML23 0x0080 /* RX Message Lost In Mailbox 23 */
2038#define RML24 0x0100 /* RX Message Lost In Mailbox 24 */
2039#define RML25 0x0200 /* RX Message Lost In Mailbox 25 */
2040#define RML26 0x0400 /* RX Message Lost In Mailbox 26 */
2041#define RML27 0x0800 /* RX Message Lost In Mailbox 27 */
2042#define RML28 0x1000 /* RX Message Lost In Mailbox 28 */
2043#define RML29 0x2000 /* RX Message Lost In Mailbox 29 */
2044#define RML30 0x4000 /* RX Message Lost In Mailbox 30 */
2045#define RML31 0x8000 /* RX Message Lost In Mailbox 31 */
2046
2047/* CAN_OPSS1 Masks */
2048#define OPSS0 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 0 */
2049#define OPSS1 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 1 */
2050#define OPSS2 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 2 */
2051#define OPSS3 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 3 */
2052#define OPSS4 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 4 */
2053#define OPSS5 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 5 */
2054#define OPSS6 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 6 */
2055#define OPSS7 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 7 */
2056#define OPSS8 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 8 */
2057#define OPSS9 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 9 */
2058#define OPSS10 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 10 */
2059#define OPSS11 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 11 */
2060#define OPSS12 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 12 */
2061#define OPSS13 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 13 */
2062#define OPSS14 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 14 */
2063#define OPSS15 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 15 */
2064
2065/* CAN_OPSS2 Masks */
2066#define OPSS16 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 16 */
2067#define OPSS17 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 17 */
2068#define OPSS18 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 18 */
2069#define OPSS19 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 19 */
2070#define OPSS20 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 20 */
2071#define OPSS21 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 21 */
2072#define OPSS22 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 22 */
2073#define OPSS23 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 23 */
2074#define OPSS24 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 24 */
2075#define OPSS25 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 25 */
2076#define OPSS26 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 26 */
2077#define OPSS27 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 27 */
2078#define OPSS28 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 28 */
2079#define OPSS29 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 29 */
2080#define OPSS30 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 30 */
2081#define OPSS31 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 31 */
2082
2083/* CAN_TRR1 Masks */
2084#define TRR0 0x0001 /* Deny But Don't Lock Access To Mailbox 0 */
2085#define TRR1 0x0002 /* Deny But Don't Lock Access To Mailbox 1 */
2086#define TRR2 0x0004 /* Deny But Don't Lock Access To Mailbox 2 */
2087#define TRR3 0x0008 /* Deny But Don't Lock Access To Mailbox 3 */
2088#define TRR4 0x0010 /* Deny But Don't Lock Access To Mailbox 4 */
2089#define TRR5 0x0020 /* Deny But Don't Lock Access To Mailbox 5 */
2090#define TRR6 0x0040 /* Deny But Don't Lock Access To Mailbox 6 */
2091#define TRR7 0x0080 /* Deny But Don't Lock Access To Mailbox 7 */
2092#define TRR8 0x0100 /* Deny But Don't Lock Access To Mailbox 8 */
2093#define TRR9 0x0200 /* Deny But Don't Lock Access To Mailbox 9 */
2094#define TRR10 0x0400 /* Deny But Don't Lock Access To Mailbox 10 */
2095#define TRR11 0x0800 /* Deny But Don't Lock Access To Mailbox 11 */
2096#define TRR12 0x1000 /* Deny But Don't Lock Access To Mailbox 12 */
2097#define TRR13 0x2000 /* Deny But Don't Lock Access To Mailbox 13 */
2098#define TRR14 0x4000 /* Deny But Don't Lock Access To Mailbox 14 */
2099#define TRR15 0x8000 /* Deny But Don't Lock Access To Mailbox 15 */
2100
2101/* CAN_TRR2 Masks */
2102#define TRR16 0x0001 /* Deny But Don't Lock Access To Mailbox 16 */
2103#define TRR17 0x0002 /* Deny But Don't Lock Access To Mailbox 17 */
2104#define TRR18 0x0004 /* Deny But Don't Lock Access To Mailbox 18 */
2105#define TRR19 0x0008 /* Deny But Don't Lock Access To Mailbox 19 */
2106#define TRR20 0x0010 /* Deny But Don't Lock Access To Mailbox 20 */
2107#define TRR21 0x0020 /* Deny But Don't Lock Access To Mailbox 21 */
2108#define TRR22 0x0040 /* Deny But Don't Lock Access To Mailbox 22 */
2109#define TRR23 0x0080 /* Deny But Don't Lock Access To Mailbox 23 */
2110#define TRR24 0x0100 /* Deny But Don't Lock Access To Mailbox 24 */
2111#define TRR25 0x0200 /* Deny But Don't Lock Access To Mailbox 25 */
2112#define TRR26 0x0400 /* Deny But Don't Lock Access To Mailbox 26 */
2113#define TRR27 0x0800 /* Deny But Don't Lock Access To Mailbox 27 */
2114#define TRR28 0x1000 /* Deny But Don't Lock Access To Mailbox 28 */
2115#define TRR29 0x2000 /* Deny But Don't Lock Access To Mailbox 29 */
2116#define TRR30 0x4000 /* Deny But Don't Lock Access To Mailbox 30 */
2117#define TRR31 0x8000 /* Deny But Don't Lock Access To Mailbox 31 */
2118
2119/* CAN_TRS1 Masks */
2120#define TRS0 0x0001 /* Remote Frame Request For Mailbox 0 */
2121#define TRS1 0x0002 /* Remote Frame Request For Mailbox 1 */
2122#define TRS2 0x0004 /* Remote Frame Request For Mailbox 2 */
2123#define TRS3 0x0008 /* Remote Frame Request For Mailbox 3 */
2124#define TRS4 0x0010 /* Remote Frame Request For Mailbox 4 */
2125#define TRS5 0x0020 /* Remote Frame Request For Mailbox 5 */
2126#define TRS6 0x0040 /* Remote Frame Request For Mailbox 6 */
2127#define TRS7 0x0080 /* Remote Frame Request For Mailbox 7 */
2128#define TRS8 0x0100 /* Remote Frame Request For Mailbox 8 */
2129#define TRS9 0x0200 /* Remote Frame Request For Mailbox 9 */
2130#define TRS10 0x0400 /* Remote Frame Request For Mailbox 10 */
2131#define TRS11 0x0800 /* Remote Frame Request For Mailbox 11 */
2132#define TRS12 0x1000 /* Remote Frame Request For Mailbox 12 */
2133#define TRS13 0x2000 /* Remote Frame Request For Mailbox 13 */
2134#define TRS14 0x4000 /* Remote Frame Request For Mailbox 14 */
2135#define TRS15 0x8000 /* Remote Frame Request For Mailbox 15 */
2136
2137/* CAN_TRS2 Masks */
2138#define TRS16 0x0001 /* Remote Frame Request For Mailbox 16 */
2139#define TRS17 0x0002 /* Remote Frame Request For Mailbox 17 */
2140#define TRS18 0x0004 /* Remote Frame Request For Mailbox 18 */
2141#define TRS19 0x0008 /* Remote Frame Request For Mailbox 19 */
2142#define TRS20 0x0010 /* Remote Frame Request For Mailbox 20 */
2143#define TRS21 0x0020 /* Remote Frame Request For Mailbox 21 */
2144#define TRS22 0x0040 /* Remote Frame Request For Mailbox 22 */
2145#define TRS23 0x0080 /* Remote Frame Request For Mailbox 23 */
2146#define TRS24 0x0100 /* Remote Frame Request For Mailbox 24 */
2147#define TRS25 0x0200 /* Remote Frame Request For Mailbox 25 */
2148#define TRS26 0x0400 /* Remote Frame Request For Mailbox 26 */
2149#define TRS27 0x0800 /* Remote Frame Request For Mailbox 27 */
2150#define TRS28 0x1000 /* Remote Frame Request For Mailbox 28 */
2151#define TRS29 0x2000 /* Remote Frame Request For Mailbox 29 */
2152#define TRS30 0x4000 /* Remote Frame Request For Mailbox 30 */
2153#define TRS31 0x8000 /* Remote Frame Request For Mailbox 31 */
2154
2155/* CAN_AA1 Masks */
2156#define AA0 0x0001 /* Aborted Message In Mailbox 0 */
2157#define AA1 0x0002 /* Aborted Message In Mailbox 1 */
2158#define AA2 0x0004 /* Aborted Message In Mailbox 2 */
2159#define AA3 0x0008 /* Aborted Message In Mailbox 3 */
2160#define AA4 0x0010 /* Aborted Message In Mailbox 4 */
2161#define AA5 0x0020 /* Aborted Message In Mailbox 5 */
2162#define AA6 0x0040 /* Aborted Message In Mailbox 6 */
2163#define AA7 0x0080 /* Aborted Message In Mailbox 7 */
2164#define AA8 0x0100 /* Aborted Message In Mailbox 8 */
2165#define AA9 0x0200 /* Aborted Message In Mailbox 9 */
2166#define AA10 0x0400 /* Aborted Message In Mailbox 10 */
2167#define AA11 0x0800 /* Aborted Message In Mailbox 11 */
2168#define AA12 0x1000 /* Aborted Message In Mailbox 12 */
2169#define AA13 0x2000 /* Aborted Message In Mailbox 13 */
2170#define AA14 0x4000 /* Aborted Message In Mailbox 14 */
2171#define AA15 0x8000 /* Aborted Message In Mailbox 15 */
2172
2173/* CAN_AA2 Masks */
2174#define AA16 0x0001 /* Aborted Message In Mailbox 16 */
2175#define AA17 0x0002 /* Aborted Message In Mailbox 17 */
2176#define AA18 0x0004 /* Aborted Message In Mailbox 18 */
2177#define AA19 0x0008 /* Aborted Message In Mailbox 19 */
2178#define AA20 0x0010 /* Aborted Message In Mailbox 20 */
2179#define AA21 0x0020 /* Aborted Message In Mailbox 21 */
2180#define AA22 0x0040 /* Aborted Message In Mailbox 22 */
2181#define AA23 0x0080 /* Aborted Message In Mailbox 23 */
2182#define AA24 0x0100 /* Aborted Message In Mailbox 24 */
2183#define AA25 0x0200 /* Aborted Message In Mailbox 25 */
2184#define AA26 0x0400 /* Aborted Message In Mailbox 26 */
2185#define AA27 0x0800 /* Aborted Message In Mailbox 27 */
2186#define AA28 0x1000 /* Aborted Message In Mailbox 28 */
2187#define AA29 0x2000 /* Aborted Message In Mailbox 29 */
2188#define AA30 0x4000 /* Aborted Message In Mailbox 30 */
2189#define AA31 0x8000 /* Aborted Message In Mailbox 31 */
2190
2191/* CAN_TA1 Masks */
2192#define TA0 0x0001 /* Transmit Successful From Mailbox 0 */
2193#define TA1 0x0002 /* Transmit Successful From Mailbox 1 */
2194#define TA2 0x0004 /* Transmit Successful From Mailbox 2 */
2195#define TA3 0x0008 /* Transmit Successful From Mailbox 3 */
2196#define TA4 0x0010 /* Transmit Successful From Mailbox 4 */
2197#define TA5 0x0020 /* Transmit Successful From Mailbox 5 */
2198#define TA6 0x0040 /* Transmit Successful From Mailbox 6 */
2199#define TA7 0x0080 /* Transmit Successful From Mailbox 7 */
2200#define TA8 0x0100 /* Transmit Successful From Mailbox 8 */
2201#define TA9 0x0200 /* Transmit Successful From Mailbox 9 */
2202#define TA10 0x0400 /* Transmit Successful From Mailbox 10 */
2203#define TA11 0x0800 /* Transmit Successful From Mailbox 11 */
2204#define TA12 0x1000 /* Transmit Successful From Mailbox 12 */
2205#define TA13 0x2000 /* Transmit Successful From Mailbox 13 */
2206#define TA14 0x4000 /* Transmit Successful From Mailbox 14 */
2207#define TA15 0x8000 /* Transmit Successful From Mailbox 15 */
2208
2209/* CAN_TA2 Masks */
2210#define TA16 0x0001 /* Transmit Successful From Mailbox 16 */
2211#define TA17 0x0002 /* Transmit Successful From Mailbox 17 */
2212#define TA18 0x0004 /* Transmit Successful From Mailbox 18 */
2213#define TA19 0x0008 /* Transmit Successful From Mailbox 19 */
2214#define TA20 0x0010 /* Transmit Successful From Mailbox 20 */
2215#define TA21 0x0020 /* Transmit Successful From Mailbox 21 */
2216#define TA22 0x0040 /* Transmit Successful From Mailbox 22 */
2217#define TA23 0x0080 /* Transmit Successful From Mailbox 23 */
2218#define TA24 0x0100 /* Transmit Successful From Mailbox 24 */
2219#define TA25 0x0200 /* Transmit Successful From Mailbox 25 */
2220#define TA26 0x0400 /* Transmit Successful From Mailbox 26 */
2221#define TA27 0x0800 /* Transmit Successful From Mailbox 27 */
2222#define TA28 0x1000 /* Transmit Successful From Mailbox 28 */
2223#define TA29 0x2000 /* Transmit Successful From Mailbox 29 */
2224#define TA30 0x4000 /* Transmit Successful From Mailbox 30 */
2225#define TA31 0x8000 /* Transmit Successful From Mailbox 31 */
2226
2227/* CAN_MBTD Masks */
2228#define TDPTR 0x001F /* Mailbox To Temporarily Disable */
2229#define TDA 0x0040 /* Temporary Disable Acknowledge */
2230#define TDR 0x0080 /* Temporary Disable Request */
2231
2232/* CAN_RFH1 Masks */
2233#define RFH0 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 0 */
2234#define RFH1 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 1 */
2235#define RFH2 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 2 */
2236#define RFH3 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 3 */
2237#define RFH4 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 4 */
2238#define RFH5 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 5 */
2239#define RFH6 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 6 */
2240#define RFH7 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 7 */
2241#define RFH8 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 8 */
2242#define RFH9 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 9 */
2243#define RFH10 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 10 */
2244#define RFH11 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 11 */
2245#define RFH12 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 12 */
2246#define RFH13 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 13 */
2247#define RFH14 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 14 */
2248#define RFH15 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 15 */
2249
2250/* CAN_RFH2 Masks */
2251#define RFH16 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 16 */
2252#define RFH17 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 17 */
2253#define RFH18 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 18 */
2254#define RFH19 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 19 */
2255#define RFH20 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 20 */
2256#define RFH21 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 21 */
2257#define RFH22 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 22 */
2258#define RFH23 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 23 */
2259#define RFH24 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 24 */
2260#define RFH25 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 25 */
2261#define RFH26 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 26 */
2262#define RFH27 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 27 */
2263#define RFH28 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 28 */
2264#define RFH29 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 29 */
2265#define RFH30 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 30 */
2266#define RFH31 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 31 */
2267
2268/* CAN_MBTIF1 Masks */
2269#define MBTIF0 0x0001 /* TX Interrupt Active In Mailbox 0 */
2270#define MBTIF1 0x0002 /* TX Interrupt Active In Mailbox 1 */
2271#define MBTIF2 0x0004 /* TX Interrupt Active In Mailbox 2 */
2272#define MBTIF3 0x0008 /* TX Interrupt Active In Mailbox 3 */
2273#define MBTIF4 0x0010 /* TX Interrupt Active In Mailbox 4 */
2274#define MBTIF5 0x0020 /* TX Interrupt Active In Mailbox 5 */
2275#define MBTIF6 0x0040 /* TX Interrupt Active In Mailbox 6 */
2276#define MBTIF7 0x0080 /* TX Interrupt Active In Mailbox 7 */
2277#define MBTIF8 0x0100 /* TX Interrupt Active In Mailbox 8 */
2278#define MBTIF9 0x0200 /* TX Interrupt Active In Mailbox 9 */
2279#define MBTIF10 0x0400 /* TX Interrupt Active In Mailbox 10 */
2280#define MBTIF11 0x0800 /* TX Interrupt Active In Mailbox 11 */
2281#define MBTIF12 0x1000 /* TX Interrupt Active In Mailbox 12 */
2282#define MBTIF13 0x2000 /* TX Interrupt Active In Mailbox 13 */
2283#define MBTIF14 0x4000 /* TX Interrupt Active In Mailbox 14 */
2284#define MBTIF15 0x8000 /* TX Interrupt Active In Mailbox 15 */
2285
2286/* CAN_MBTIF2 Masks */
2287#define MBTIF16 0x0001 /* TX Interrupt Active In Mailbox 16 */
2288#define MBTIF17 0x0002 /* TX Interrupt Active In Mailbox 17 */
2289#define MBTIF18 0x0004 /* TX Interrupt Active In Mailbox 18 */
2290#define MBTIF19 0x0008 /* TX Interrupt Active In Mailbox 19 */
2291#define MBTIF20 0x0010 /* TX Interrupt Active In Mailbox 20 */
2292#define MBTIF21 0x0020 /* TX Interrupt Active In Mailbox 21 */
2293#define MBTIF22 0x0040 /* TX Interrupt Active In Mailbox 22 */
2294#define MBTIF23 0x0080 /* TX Interrupt Active In Mailbox 23 */
2295#define MBTIF24 0x0100 /* TX Interrupt Active In Mailbox 24 */
2296#define MBTIF25 0x0200 /* TX Interrupt Active In Mailbox 25 */
2297#define MBTIF26 0x0400 /* TX Interrupt Active In Mailbox 26 */
2298#define MBTIF27 0x0800 /* TX Interrupt Active In Mailbox 27 */
2299#define MBTIF28 0x1000 /* TX Interrupt Active In Mailbox 28 */
2300#define MBTIF29 0x2000 /* TX Interrupt Active In Mailbox 29 */
2301#define MBTIF30 0x4000 /* TX Interrupt Active In Mailbox 30 */
2302#define MBTIF31 0x8000 /* TX Interrupt Active In Mailbox 31 */
2303
2304/* CAN_MBRIF1 Masks */
2305#define MBRIF0 0x0001 /* RX Interrupt Active In Mailbox 0 */
2306#define MBRIF1 0x0002 /* RX Interrupt Active In Mailbox 1 */
2307#define MBRIF2 0x0004 /* RX Interrupt Active In Mailbox 2 */
2308#define MBRIF3 0x0008 /* RX Interrupt Active In Mailbox 3 */
2309#define MBRIF4 0x0010 /* RX Interrupt Active In Mailbox 4 */
2310#define MBRIF5 0x0020 /* RX Interrupt Active In Mailbox 5 */
2311#define MBRIF6 0x0040 /* RX Interrupt Active In Mailbox 6 */
2312#define MBRIF7 0x0080 /* RX Interrupt Active In Mailbox 7 */
2313#define MBRIF8 0x0100 /* RX Interrupt Active In Mailbox 8 */
2314#define MBRIF9 0x0200 /* RX Interrupt Active In Mailbox 9 */
2315#define MBRIF10 0x0400 /* RX Interrupt Active In Mailbox 10 */
2316#define MBRIF11 0x0800 /* RX Interrupt Active In Mailbox 11 */
2317#define MBRIF12 0x1000 /* RX Interrupt Active In Mailbox 12 */
2318#define MBRIF13 0x2000 /* RX Interrupt Active In Mailbox 13 */
2319#define MBRIF14 0x4000 /* RX Interrupt Active In Mailbox 14 */
2320#define MBRIF15 0x8000 /* RX Interrupt Active In Mailbox 15 */
2321
2322/* CAN_MBRIF2 Masks */
2323#define MBRIF16 0x0001 /* RX Interrupt Active In Mailbox 16 */
2324#define MBRIF17 0x0002 /* RX Interrupt Active In Mailbox 17 */
2325#define MBRIF18 0x0004 /* RX Interrupt Active In Mailbox 18 */
2326#define MBRIF19 0x0008 /* RX Interrupt Active In Mailbox 19 */
2327#define MBRIF20 0x0010 /* RX Interrupt Active In Mailbox 20 */
2328#define MBRIF21 0x0020 /* RX Interrupt Active In Mailbox 21 */
2329#define MBRIF22 0x0040 /* RX Interrupt Active In Mailbox 22 */
2330#define MBRIF23 0x0080 /* RX Interrupt Active In Mailbox 23 */
2331#define MBRIF24 0x0100 /* RX Interrupt Active In Mailbox 24 */
2332#define MBRIF25 0x0200 /* RX Interrupt Active In Mailbox 25 */
2333#define MBRIF26 0x0400 /* RX Interrupt Active In Mailbox 26 */
2334#define MBRIF27 0x0800 /* RX Interrupt Active In Mailbox 27 */
2335#define MBRIF28 0x1000 /* RX Interrupt Active In Mailbox 28 */
2336#define MBRIF29 0x2000 /* RX Interrupt Active In Mailbox 29 */
2337#define MBRIF30 0x4000 /* RX Interrupt Active In Mailbox 30 */
2338#define MBRIF31 0x8000 /* RX Interrupt Active In Mailbox 31 */
2339
2340/* CAN_MBIM1 Masks */
2341#define MBIM0 0x0001 /* Enable Interrupt For Mailbox 0 */
2342#define MBIM1 0x0002 /* Enable Interrupt For Mailbox 1 */
2343#define MBIM2 0x0004 /* Enable Interrupt For Mailbox 2 */
2344#define MBIM3 0x0008 /* Enable Interrupt For Mailbox 3 */
2345#define MBIM4 0x0010 /* Enable Interrupt For Mailbox 4 */
2346#define MBIM5 0x0020 /* Enable Interrupt For Mailbox 5 */
2347#define MBIM6 0x0040 /* Enable Interrupt For Mailbox 6 */
2348#define MBIM7 0x0080 /* Enable Interrupt For Mailbox 7 */
2349#define MBIM8 0x0100 /* Enable Interrupt For Mailbox 8 */
2350#define MBIM9 0x0200 /* Enable Interrupt For Mailbox 9 */
2351#define MBIM10 0x0400 /* Enable Interrupt For Mailbox 10 */
2352#define MBIM11 0x0800 /* Enable Interrupt For Mailbox 11 */
2353#define MBIM12 0x1000 /* Enable Interrupt For Mailbox 12 */
2354#define MBIM13 0x2000 /* Enable Interrupt For Mailbox 13 */
2355#define MBIM14 0x4000 /* Enable Interrupt For Mailbox 14 */
2356#define MBIM15 0x8000 /* Enable Interrupt For Mailbox 15 */
2357
2358/* CAN_MBIM2 Masks */
2359#define MBIM16 0x0001 /* Enable Interrupt For Mailbox 16 */
2360#define MBIM17 0x0002 /* Enable Interrupt For Mailbox 17 */
2361#define MBIM18 0x0004 /* Enable Interrupt For Mailbox 18 */
2362#define MBIM19 0x0008 /* Enable Interrupt For Mailbox 19 */
2363#define MBIM20 0x0010 /* Enable Interrupt For Mailbox 20 */
2364#define MBIM21 0x0020 /* Enable Interrupt For Mailbox 21 */
2365#define MBIM22 0x0040 /* Enable Interrupt For Mailbox 22 */
2366#define MBIM23 0x0080 /* Enable Interrupt For Mailbox 23 */
2367#define MBIM24 0x0100 /* Enable Interrupt For Mailbox 24 */
2368#define MBIM25 0x0200 /* Enable Interrupt For Mailbox 25 */
2369#define MBIM26 0x0400 /* Enable Interrupt For Mailbox 26 */
2370#define MBIM27 0x0800 /* Enable Interrupt For Mailbox 27 */
2371#define MBIM28 0x1000 /* Enable Interrupt For Mailbox 28 */
2372#define MBIM29 0x2000 /* Enable Interrupt For Mailbox 29 */
2373#define MBIM30 0x4000 /* Enable Interrupt For Mailbox 30 */
2374#define MBIM31 0x8000 /* Enable Interrupt For Mailbox 31 */
2375
2376/* CAN_GIM Masks */
2377#define EWTIM 0x0001 /* Enable TX Error Count Interrupt */
2378#define EWRIM 0x0002 /* Enable RX Error Count Interrupt */
2379#define EPIM 0x0004 /* Enable Error-Passive Mode Interrupt */
2380#define BOIM 0x0008 /* Enable Bus Off Interrupt */
2381#define WUIM 0x0010 /* Enable Wake-Up Interrupt */
2382#define UIAIM 0x0020 /* Enable Access To Unimplemented Address Interrupt */
2383#define AAIM 0x0040 /* Enable Abort Acknowledge Interrupt */
2384#define RMLIM 0x0080 /* Enable RX Message Lost Interrupt */
2385#define UCEIM 0x0100 /* Enable Universal Counter Overflow Interrupt */
2386#define EXTIM 0x0200 /* Enable External Trigger Output Interrupt */
2387#define ADIM 0x0400 /* Enable Access Denied Interrupt */
2388
2389/* CAN_GIS Masks */
2390#define EWTIS 0x0001 /* TX Error Count IRQ Status */
2391#define EWRIS 0x0002 /* RX Error Count IRQ Status */
2392#define EPIS 0x0004 /* Error-Passive Mode IRQ Status */
2393#define BOIS 0x0008 /* Bus Off IRQ Status */
2394#define WUIS 0x0010 /* Wake-Up IRQ Status */
2395#define UIAIS 0x0020 /* Access To Unimplemented Address IRQ Status */
2396#define AAIS 0x0040 /* Abort Acknowledge IRQ Status */
2397#define RMLIS 0x0080 /* RX Message Lost IRQ Status */
2398#define UCEIS 0x0100 /* Universal Counter Overflow IRQ Status */
2399#define EXTIS 0x0200 /* External Trigger Output IRQ Status */
2400#define ADIS 0x0400 /* Access Denied IRQ Status */
2401
2402/* CAN_GIF Masks */
2403#define EWTIF 0x0001 /* TX Error Count IRQ Flag */
2404#define EWRIF 0x0002 /* RX Error Count IRQ Flag */
2405#define EPIF 0x0004 /* Error-Passive Mode IRQ Flag */
2406#define BOIF 0x0008 /* Bus Off IRQ Flag */
2407#define WUIF 0x0010 /* Wake-Up IRQ Flag */
2408#define UIAIF 0x0020 /* Access To Unimplemented Address IRQ Flag */
2409#define AAIF 0x0040 /* Abort Acknowledge IRQ Flag */
2410#define RMLIF 0x0080 /* RX Message Lost IRQ Flag */
2411#define UCEIF 0x0100 /* Universal Counter Overflow IRQ Flag */
2412#define EXTIF 0x0200 /* External Trigger Output IRQ Flag */
2413#define ADIF 0x0400 /* Access Denied IRQ Flag */
2414
2415/* CAN_UCCNF Masks */
2416#define UCCNF 0x000F /* Universal Counter Mode */
2417#define UC_STAMP 0x0001 /* Timestamp Mode */
2418#define UC_WDOG 0x0002 /* Watchdog Mode */
2419#define UC_AUTOTX 0x0003 /* Auto-Transmit Mode */
2420#define UC_ERROR 0x0006 /* CAN Error Frame Count */
2421#define UC_OVER 0x0007 /* CAN Overload Frame Count */
2422#define UC_LOST 0x0008 /* Arbitration Lost During TX Count */
2423#define UC_AA 0x0009 /* TX Abort Count */
2424#define UC_TA 0x000A /* TX Successful Count */
2425#define UC_REJECT 0x000B /* RX Message Rejected Count */
2426#define UC_RML 0x000C /* RX Message Lost Count */
2427#define UC_RX 0x000D /* Total Successful RX Messages Count */
2428#define UC_RMP 0x000E /* Successful RX W/Matching ID Count */
2429#define UC_ALL 0x000F /* Correct Message On CAN Bus Line Count */
2430#define UCRC 0x0020 /* Universal Counter Reload/Clear */
2431#define UCCT 0x0040 /* Universal Counter CAN Trigger */
2432#define UCE 0x0080 /* Universal Counter Enable */
2433
2434/* CAN_ESR Masks */
2435#define ACKE 0x0004 /* Acknowledge Error */
2436#define SER 0x0008 /* Stuff Error */
2437#define CRCE 0x0010 /* CRC Error */
2438#define SA0 0x0020 /* Stuck At Dominant Error */
2439#define BEF 0x0040 /* Bit Error Flag */
2440#define FER 0x0080 /* Form Error Flag */
2441
2442/* CAN_EWR Masks */
2443#define EWLREC 0x00FF /* RX Error Count Limit (For EWRIS) */
2444#define EWLTEC 0xFF00 /* TX Error Count Limit (For EWTIS) */
2445
2446/* ******************* PIN CONTROL REGISTER MASKS ************************/
2447/* PORT_MUX Masks */
2448#define PJSE 0x0001 /* Port J SPI/SPORT Enable */
2449#define PJSE_SPORT 0x0000 /* Enable TFS0/DT0PRI */
2450#define PJSE_SPI 0x0001 /* Enable SPI_SSEL3:2 */
2451
2452#define PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */
2453#define PJCE_SPORT 0x0000 /* Enable DR0SEC/DT0SEC */
2454#define PJCE_CAN 0x0002 /* Enable CAN RX/TX */
2455#define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */
2456
2457#define PFDE 0x0008 /* Port F DMA Request Enable */
2458#define PFDE_UART 0x0000 /* Enable UART0 RX/TX */
2459#define PFDE_DMA 0x0008 /* Enable DMAR1:0 */
2460
2461#define PFTE 0x0010 /* Port F Timer Enable */
2462#define PFTE_UART 0x0000 /* Enable UART1 RX/TX */
2463#define PFTE_TIMER 0x0010 /* Enable TMR7:6 */
2464
2465#define PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */
2466#define PFS6E_TIMER 0x0000 /* Enable TMR5 */
2467#define PFS6E_SPI 0x0020 /* Enable SPI_SSEL6 */
2468
2469#define PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */
2470#define PFS5E_TIMER 0x0000 /* Enable TMR4 */
2471#define PFS5E_SPI 0x0040 /* Enable SPI_SSEL5 */
2472
2473#define PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */
2474#define PFS4E_TIMER 0x0000 /* Enable TMR3 */
2475#define PFS4E_SPI 0x0080 /* Enable SPI_SSEL4 */
2476
2477#define PFFE 0x0100 /* Port F PPI Frame Sync Enable */
2478#define PFFE_TIMER 0x0000 /* Enable TMR2 */
2479#define PFFE_PPI 0x0100 /* Enable PPI FS3 */
2480
2481#define PGSE 0x0200 /* Port G SPORT1 Secondary Enable */
2482#define PGSE_PPI 0x0000 /* Enable PPI D9:8 */
2483#define PGSE_SPORT 0x0200 /* Enable DR1SEC/DT1SEC */
2484
2485#define PGRE 0x0400 /* Port G SPORT1 Receive Enable */
2486#define PGRE_PPI 0x0000 /* Enable PPI D12:10 */
2487#define PGRE_SPORT 0x0400 /* Enable DR1PRI/RFS1/RSCLK1 */
2488
2489#define PGTE 0x0800 /* Port G SPORT1 Transmit Enable */
2490#define PGTE_PPI 0x0000 /* Enable PPI D15:13 */
2491#define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */
2492
2493/* ****************** HANDSHAKE DMA (HDMA) MASKS *********************/
2494/* HDMAx_CTL Masks */
2495#define HMDMAEN 0x0001 /* Enable Handshake DMA 0/1 */
2496#define REP 0x0002 /* HDMA Request Polarity */
2497#define UTE 0x0004 /* Urgency Threshold Enable */
2498#define OIE 0x0010 /* Overflow Interrupt Enable */
2499#define BDIE 0x0020 /* Block Done Interrupt Enable */
2500#define MBDI 0x0040 /* Mask Block Done IRQ If Pending ECNT */
2501#define DRQ 0x0300 /* HDMA Request Type */
2502#define DRQ_NONE 0x0000 /* No Request */
2503#define DRQ_SINGLE 0x0100 /* Channels Request Single */
2504#define DRQ_MULTI 0x0200 /* Channels Request Multi (Default) */
2505#define DRQ_URGENT 0x0300 /* Channels Request Multi Urgent */
2506#define RBC 0x1000 /* Reload BCNT With IBCNT */
2507#define PS 0x2000 /* HDMA Pin Status */
2508#define OI 0x4000 /* Overflow Interrupt Generated */
2509#define BDI 0x8000 /* Block Done Interrupt Generated */
2510
2511/* entry addresses of the user-callable Boot ROM functions */
2512
2513#define _BOOTROM_RESET 0xEF000000
2514#define _BOOTROM_FINAL_INIT 0xEF000002
2515#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
2516#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
2517#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
2518#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
2519#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
2520#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
2521#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
2522
2523/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
2524#define PGDE_UART PFDE_UART
2525#define PGDE_DMA PFDE_DMA
2526#define CKELOW SCKELOW
2527#endif /* _DEF_BF534_H */
diff --git a/arch/blackfin/mach-bf537/include/mach/defBF537.h b/arch/blackfin/mach-bf537/include/mach/defBF537.h
new file mode 100644
index 000000000000..3d6c83e31b1e
--- /dev/null
+++ b/arch/blackfin/mach-bf537/include/mach/defBF537.h
@@ -0,0 +1,405 @@
1/*
2 * file: include/asm-blackfin/mach-bf537/defbf537.h
3 * based on:
4 * author:
5 *
6 * created:
7 * description:
8 * system mmr register map
9 * rev:
10 *
11 * modified:
12 *
13 *
14 * bugs: enter bugs at http://blackfin.uclinux.org/
15 *
16 * this program is free software; you can redistribute it and/or modify
17 * it under the terms of the gnu general public license as published by
18 * the free software foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * this program is distributed in the hope that it will be useful,
22 * but without any warranty; without even the implied warranty of
23 * merchantability or fitness for a particular purpose. see the
24 * gnu general public license for more details.
25 *
26 * you should have received a copy of the gnu general public license
27 * along with this program; see the file copying.
28 * if not, write to the free software foundation,
29 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
30 */
31
32#ifndef _DEF_BF537_H
33#define _DEF_BF537_H
34
35/* Include all Core registers and bit definitions*/
36#include <asm/cdef_LPBlackfin.h>
37
38/* Include all MMR and bit defines common to BF534 */
39#include "defBF534.h"
40
41/************************************************************************************
42** Define EMAC Section Unique to BF536/BF537
43*************************************************************************************/
44
45/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
46#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
47#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
48#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
49#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
50#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
51#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */
52#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */
53#define EMAC_FLC 0xFFC0301C /* Flow Control Register */
54#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */
55#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */
56#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */
57#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
58#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
59#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
60#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
61#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */
62#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
63#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
64#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
65
66#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */
67#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */
68#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */
69#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */
70#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */
71#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */
72#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */
73#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */
74
75#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */
76#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */
77#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */
78#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */
79#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */
80
81#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */
82#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */
83#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */
84#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */
85#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
86#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */
87#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */
88#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */
89#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */
90#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */
91#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */
92#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */
93#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */
94#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */
95#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */
96#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */
97#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */
98#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
99#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
100#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 <= x < 128 */
101#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
102#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
103#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
104#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
105
106#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */
107#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */
108#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
109#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */
110#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
111#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */
112#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
113#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
114#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
115#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */
116#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */
117#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */
118#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */
119#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */
120#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */
121#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */
122#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
123#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 <= x < 128 */
124#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
125#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
126#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
127#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
128#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */
129
130/* Listing for IEEE-Supported Count Registers */
131#define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */
132#define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */
133#define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */
134#define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */
135#define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */
136#define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */
137#define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */
138#define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */
139#define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */
140#define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */
141#define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */
142#define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */
143#define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */
144#define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */
145#define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */
146#define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */
147#define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */
148#define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */
149#define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */
150#define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 <= x < 128 */
151#define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
152#define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
153#define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
154#define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */
155
156#define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */
157#define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */
158#define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */
159#define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */
160#define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */
161#define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */
162#define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */
163#define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */
164#define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */
165#define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */
166#define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */
167#define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */
168#define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */
169#define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */
170#define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */
171#define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */
172#define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */
173#define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 <= x < 128 */
174#define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
175#define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */
176#define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
177#define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */
178#define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */
179
180/***********************************************************************************
181** System MMR Register Bits And Macros
182**
183** Disclaimer: All macros are intended to make C and Assembly code more readable.
184** Use these macros carefully, as any that do left shifts for field
185** depositing will result in the lower order bits being destroyed. Any
186** macro that shifts left to properly position the bit-field should be
187** used as part of an OR to initialize a register and NOT as a dynamic
188** modifier UNLESS the lower order bits are saved and ORed back in when
189** the macro is used.
190*************************************************************************************/
191/************************ ETHERNET 10/100 CONTROLLER MASKS ************************/
192/* EMAC_OPMODE Masks */
193#define RE 0x00000001 /* Receiver Enable */
194#define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */
195#define HU 0x00000010 /* Hash Filter Unicast Address */
196#define HM 0x00000020 /* Hash Filter Multicast Address */
197#define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */
198#define PR 0x00000080 /* Promiscuous Mode Enable */
199#define IFE 0x00000100 /* Inverse Filtering Enable */
200#define DBF 0x00000200 /* Disable Broadcast Frame Reception */
201#define PBF 0x00000400 /* Pass Bad Frames Enable */
202#define PSF 0x00000800 /* Pass Short Frames Enable */
203#define RAF 0x00001000 /* Receive-All Mode */
204#define TE 0x00010000 /* Transmitter Enable */
205#define DTXPAD 0x00020000 /* Disable Automatic TX Padding */
206#define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */
207#define DC 0x00080000 /* Deferral Check */
208#define BOLMT 0x00300000 /* Back-Off Limit */
209#define BOLMT_10 0x00000000 /* 10-bit range */
210#define BOLMT_8 0x00100000 /* 8-bit range */
211#define BOLMT_4 0x00200000 /* 4-bit range */
212#define BOLMT_1 0x00300000 /* 1-bit range */
213#define DRTY 0x00400000 /* Disable TX Retry On Collision */
214#define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */
215#define RMII 0x01000000 /* RMII/MII* Mode */
216#define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */
217#define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */
218#define LB 0x08000000 /* Internal Loopback Enable */
219#define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */
220
221/* EMAC_STAADD Masks */
222#define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */
223#define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */
224#define STADISPRE 0x00000004 /* Disable Preamble Generation */
225#define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */
226#define REGAD 0x000007C0 /* STA Register Address */
227#define PHYAD 0x0000F800 /* PHY Device Address */
228
229#define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */
230#define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */
231
232/* EMAC_STADAT Mask */
233#define STADATA 0x0000FFFF /* Station Management Data */
234
235/* EMAC_FLC Masks */
236#define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */
237#define FLCE 0x00000002 /* Flow Control Enable */
238#define PCF 0x00000004 /* Pass Control Frames */
239#define BKPRSEN 0x00000008 /* Enable Backpressure */
240#define FLCPAUSE 0xFFFF0000 /* Pause Time */
241
242#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */
243
244/* EMAC_WKUP_CTL Masks */
245#define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */
246#define MPKE 0x00000002 /* Magic Packet Enable */
247#define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */
248#define GUWKE 0x00000008 /* Global Unicast Wake Enable */
249#define MPKS 0x00000020 /* Magic Packet Received Status */
250#define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */
251
252/* EMAC_WKUP_FFCMD Masks */
253#define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */
254#define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */
255#define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */
256#define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */
257#define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */
258#define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */
259#define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */
260#define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */
261
262/* EMAC_WKUP_FFOFF Masks */
263#define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */
264#define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */
265#define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */
266#define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */
267
268#define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */
269#define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */
270#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */
271#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */
272/* Set ALL Offsets */
273#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
274
275/* EMAC_WKUP_FFCRC0 Masks */
276#define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */
277#define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */
278
279#define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */
280#define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */
281
282/* EMAC_WKUP_FFCRC1 Masks */
283#define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */
284#define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */
285
286#define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */
287#define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */
288
289/* EMAC_SYSCTL Masks */
290#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */
291#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */
292#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */
293#define TXDWA 0x00000010 /* Transmit Frame DMA Word Alignment (Odd/Even*) */
294#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
295
296#define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */
297
298/* EMAC_SYSTAT Masks */
299#define PHYINT 0x00000001 /* PHY_INT Interrupt Status */
300#define MMCINT 0x00000002 /* MMC Counter Interrupt Status */
301#define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */
302#define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */
303#define WAKEDET 0x00000010 /* Wake-Up Detected Status */
304#define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */
305#define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */
306#define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */
307
308/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
309#define RX_FRLEN 0x000007FF /* Frame Length In Bytes */
310#define RX_COMP 0x00001000 /* RX Frame Complete */
311#define RX_OK 0x00002000 /* RX Frame Received With No Errors */
312#define RX_LONG 0x00004000 /* RX Frame Too Long Error */
313#define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */
314#define RX_CRC 0x00010000 /* RX Frame CRC Error */
315#define RX_LEN 0x00020000 /* RX Frame Length Error */
316#define RX_FRAG 0x00040000 /* RX Frame Fragment Error */
317#define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */
318#define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */
319#define RX_PHY 0x00200000 /* RX Frame PHY Error */
320#define RX_LATE 0x00400000 /* RX Frame Late Collision Error */
321#define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */
322#define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */
323#define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */
324#define RX_CTL 0x04000000 /* RX Control Frame Indicator */
325#define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */
326#define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */
327#define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */
328#define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */
329#define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */
330
331/* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */
332#define TX_COMP 0x00000001 /* TX Frame Complete */
333#define TX_OK 0x00000002 /* TX Frame Sent With No Errors */
334#define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */
335#define TX_LATE 0x00000008 /* TX Frame Late Collision Error */
336#define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */
337#define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */
338#define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */
339#define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */
340#define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */
341#define TX_CCNT 0x00000F00 /* TX Frame Collision Count */
342#define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */
343#define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */
344#define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */
345#define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */
346#define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */
347
348/* EMAC_MMC_CTL Masks */
349#define RSTC 0x00000001 /* Reset All Counters */
350#define CROLL 0x00000002 /* Counter Roll-Over Enable */
351#define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */
352#define MMCE 0x00000008 /* Enable MMC Counter Operation */
353
354/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
355#define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */
356#define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */
357#define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */
358#define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */
359#define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */
360#define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */
361#define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */
362#define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */
363#define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */
364#define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */
365#define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */
366#define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */
367#define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */
368#define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */
369#define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */
370#define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */
371#define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */
372#define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */
373#define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */
374#define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */
375#define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */
376#define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */
377#define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */
378#define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */
379
380/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */
381#define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */
382#define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */
383#define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */
384#define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */
385#define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */
386#define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */
387#define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */
388#define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */
389#define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */
390#define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */
391#define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */
392#define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */
393#define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */
394#define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */
395#define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */
396#define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */
397#define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */
398#define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */
399#define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */
400#define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */
401#define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */
402#define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */
403#define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */
404
405#endif /* _DEF_BF537_H */
diff --git a/arch/blackfin/mach-bf537/include/mach/dma.h b/arch/blackfin/mach-bf537/include/mach/dma.h
new file mode 100644
index 000000000000..7a964040870a
--- /dev/null
+++ b/arch/blackfin/mach-bf537/include/mach/dma.h
@@ -0,0 +1,55 @@
1/*
2 * file: include/asm-blackfin/mach-bf537/dma.h
3 * based on:
4 * author:
5 *
6 * created:
7 * description:
8 * system mmr register map
9 * rev:
10 *
11 * modified:
12 *
13 *
14 * bugs: enter bugs at http://blackfin.uclinux.org/
15 *
16 * this program is free software; you can redistribute it and/or modify
17 * it under the terms of the gnu general public license as published by
18 * the free software foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * this program is distributed in the hope that it will be useful,
22 * but without any warranty; without even the implied warranty of
23 * merchantability or fitness for a particular purpose. see the
24 * gnu general public license for more details.
25 *
26 * you should have received a copy of the gnu general public license
27 * along with this program; see the file copying.
28 * if not, write to the free software foundation,
29 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
30 */
31
32#ifndef _MACH_DMA_H_
33#define _MACH_DMA_H_
34
35#define MAX_BLACKFIN_DMA_CHANNEL 16
36
37#define CH_PPI 0
38#define CH_EMAC_RX 1
39#define CH_EMAC_TX 2
40#define CH_SPORT0_RX 3
41#define CH_SPORT0_TX 4
42#define CH_SPORT1_RX 5
43#define CH_SPORT1_TX 6
44#define CH_SPI 7
45#define CH_UART0_RX 8
46#define CH_UART0_TX 9
47#define CH_UART1_RX 10
48#define CH_UART1_TX 11
49
50#define CH_MEM_STREAM0_DEST 12 /* TX */
51#define CH_MEM_STREAM0_SRC 13 /* RX */
52#define CH_MEM_STREAM1_DEST 14 /* TX */
53#define CH_MEM_STREAM1_SRC 15 /* RX */
54
55#endif
diff --git a/arch/blackfin/mach-bf537/include/mach/irq.h b/arch/blackfin/mach-bf537/include/mach/irq.h
new file mode 100644
index 000000000000..2e68a8a1e730
--- /dev/null
+++ b/arch/blackfin/mach-bf537/include/mach/irq.h
@@ -0,0 +1,214 @@
1/*
2 * file: include/asm-blackfin/mach-bf537/irq.h
3 * based on:
4 * author:
5 *
6 * created:
7 * description:
8 * system mmr register map
9 * rev:
10 *
11 * modified:
12 *
13 *
14 * bugs: enter bugs at http://blackfin.uclinux.org/
15 *
16 * this program is free software; you can redistribute it and/or modify
17 * it under the terms of the gnu general public license as published by
18 * the free software foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * this program is distributed in the hope that it will be useful,
22 * but without any warranty; without even the implied warranty of
23 * merchantability or fitness for a particular purpose. see the
24 * gnu general public license for more details.
25 *
26 * you should have received a copy of the gnu general public license
27 * along with this program; see the file copying.
28 * if not, write to the free software foundation,
29 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
30 */
31
32#ifndef _BF537_IRQ_H_
33#define _BF537_IRQ_H_
34
35/*
36 * Interrupt source definitions
37 * Event Source Core Event Name
38 * Core Emulation **
39 * Events (highest priority) EMU 0
40 * Reset RST 1
41 * NMI NMI 2
42 * Exception EVX 3
43 * Reserved -- 4
44 * Hardware Error IVHW 5
45 * Core Timer IVTMR 6
46 * .....
47 *
48 * Softirq IVG14
49 * System Call --
50 * (lowest priority) IVG15
51 */
52
53#define SYS_IRQS 39
54#define NR_PERI_INTS 32
55
56/* The ABSTRACT IRQ definitions */
57/** the first seven of the following are fixed, the rest you change if you need to **/
58#define IRQ_EMU 0 /*Emulation */
59#define IRQ_RST 1 /*reset */
60#define IRQ_NMI 2 /*Non Maskable */
61#define IRQ_EVX 3 /*Exception */
62#define IRQ_UNUSED 4 /*- unused interrupt*/
63#define IRQ_HWERR 5 /*Hardware Error */
64#define IRQ_CORETMR 6 /*Core timer */
65
66#define IRQ_PLL_WAKEUP 7 /*PLL Wakeup Interrupt */
67#define IRQ_DMA_ERROR 8 /*DMA Error (general) */
68#define IRQ_GENERIC_ERROR 9 /*GENERIC Error Interrupt */
69#define IRQ_RTC 10 /*RTC Interrupt */
70#define IRQ_PPI 11 /*DMA0 Interrupt (PPI) */
71#define IRQ_SPORT0_RX 12 /*DMA3 Interrupt (SPORT0 RX) */
72#define IRQ_SPORT0_TX 13 /*DMA4 Interrupt (SPORT0 TX) */
73#define IRQ_SPORT1_RX 14 /*DMA5 Interrupt (SPORT1 RX) */
74#define IRQ_SPORT1_TX 15 /*DMA6 Interrupt (SPORT1 TX) */
75#define IRQ_TWI 16 /*TWI Interrupt */
76#define IRQ_SPI 17 /*DMA7 Interrupt (SPI) */
77#define IRQ_UART0_RX 18 /*DMA8 Interrupt (UART0 RX) */
78#define IRQ_UART0_TX 19 /*DMA9 Interrupt (UART0 TX) */
79#define IRQ_UART1_RX 20 /*DMA10 Interrupt (UART1 RX) */
80#define IRQ_UART1_TX 21 /*DMA11 Interrupt (UART1 TX) */
81#define IRQ_CAN_RX 22 /*CAN Receive Interrupt */
82#define IRQ_CAN_TX 23 /*CAN Transmit Interrupt */
83#define IRQ_MAC_RX 24 /*DMA1 (Ethernet RX) Interrupt */
84#define IRQ_MAC_TX 25 /*DMA2 (Ethernet TX) Interrupt */
85#define IRQ_TMR0 26 /*Timer 0 */
86#define IRQ_TMR1 27 /*Timer 1 */
87#define IRQ_TMR2 28 /*Timer 2 */
88#define IRQ_TMR3 29 /*Timer 3 */
89#define IRQ_TMR4 30 /*Timer 4 */
90#define IRQ_TMR5 31 /*Timer 5 */
91#define IRQ_TMR6 32 /*Timer 6 */
92#define IRQ_TMR7 33 /*Timer 7 */
93#define IRQ_PROG_INTA 34 /* PF Ports F&G (PF15:0) Interrupt A */
94#define IRQ_PORTG_INTB 35 /* PF Port G (PF15:0) Interrupt B */
95#define IRQ_MEM_DMA0 36 /*(Memory DMA Stream 0) */
96#define IRQ_MEM_DMA1 37 /*(Memory DMA Stream 1) */
97#define IRQ_PROG_INTB 38 /* PF Ports F (PF15:0) Interrupt B */
98#define IRQ_WATCH 38 /*Watch Dog Timer */
99
100#define IRQ_PPI_ERROR 42 /*PPI Error Interrupt */
101#define IRQ_CAN_ERROR 43 /*CAN Error Interrupt */
102#define IRQ_MAC_ERROR 44 /*PPI Error Interrupt */
103#define IRQ_SPORT0_ERROR 45 /*SPORT0 Error Interrupt */
104#define IRQ_SPORT1_ERROR 46 /*SPORT1 Error Interrupt */
105#define IRQ_SPI_ERROR 47 /*SPI Error Interrupt */
106#define IRQ_UART0_ERROR 48 /*UART Error Interrupt */
107#define IRQ_UART1_ERROR 49 /*UART Error Interrupt */
108
109#define IRQ_PF0 50
110#define IRQ_PF1 51
111#define IRQ_PF2 52
112#define IRQ_PF3 53
113#define IRQ_PF4 54
114#define IRQ_PF5 55
115#define IRQ_PF6 56
116#define IRQ_PF7 57
117#define IRQ_PF8 58
118#define IRQ_PF9 59
119#define IRQ_PF10 60
120#define IRQ_PF11 61
121#define IRQ_PF12 62
122#define IRQ_PF13 63
123#define IRQ_PF14 64
124#define IRQ_PF15 65
125
126#define IRQ_PG0 66
127#define IRQ_PG1 67
128#define IRQ_PG2 68
129#define IRQ_PG3 69
130#define IRQ_PG4 70
131#define IRQ_PG5 71
132#define IRQ_PG6 72
133#define IRQ_PG7 73
134#define IRQ_PG8 74
135#define IRQ_PG9 75
136#define IRQ_PG10 76
137#define IRQ_PG11 77
138#define IRQ_PG12 78
139#define IRQ_PG13 79
140#define IRQ_PG14 80
141#define IRQ_PG15 81
142
143#define IRQ_PH0 82
144#define IRQ_PH1 83
145#define IRQ_PH2 84
146#define IRQ_PH3 85
147#define IRQ_PH4 86
148#define IRQ_PH5 87
149#define IRQ_PH6 88
150#define IRQ_PH7 89
151#define IRQ_PH8 90
152#define IRQ_PH9 91
153#define IRQ_PH10 92
154#define IRQ_PH11 93
155#define IRQ_PH12 94
156#define IRQ_PH13 95
157#define IRQ_PH14 96
158#define IRQ_PH15 97
159
160#define GPIO_IRQ_BASE IRQ_PF0
161
162#define NR_IRQS (IRQ_PH15+1)
163
164#define IVG7 7
165#define IVG8 8
166#define IVG9 9
167#define IVG10 10
168#define IVG11 11
169#define IVG12 12
170#define IVG13 13
171#define IVG14 14
172#define IVG15 15
173
174/* IAR0 BIT FIELDS*/
175#define IRQ_PLL_WAKEUP_POS 0
176#define IRQ_DMA_ERROR_POS 4
177#define IRQ_ERROR_POS 8
178#define IRQ_RTC_POS 12
179#define IRQ_PPI_POS 16
180#define IRQ_SPORT0_RX_POS 20
181#define IRQ_SPORT0_TX_POS 24
182#define IRQ_SPORT1_RX_POS 28
183
184/* IAR1 BIT FIELDS*/
185#define IRQ_SPORT1_TX_POS 0
186#define IRQ_TWI_POS 4
187#define IRQ_SPI_POS 8
188#define IRQ_UART0_RX_POS 12
189#define IRQ_UART0_TX_POS 16
190#define IRQ_UART1_RX_POS 20
191#define IRQ_UART1_TX_POS 24
192#define IRQ_CAN_RX_POS 28
193
194/* IAR2 BIT FIELDS*/
195#define IRQ_CAN_TX_POS 0
196#define IRQ_MAC_RX_POS 4
197#define IRQ_MAC_TX_POS 8
198#define IRQ_TMR0_POS 12
199#define IRQ_TMR1_POS 16
200#define IRQ_TMR2_POS 20
201#define IRQ_TMR3_POS 24
202#define IRQ_TMR4_POS 28
203
204/* IAR3 BIT FIELDS*/
205#define IRQ_TMR5_POS 0
206#define IRQ_TMR6_POS 4
207#define IRQ_TMR7_POS 8
208#define IRQ_PROG_INTA_POS 12
209#define IRQ_PORTG_INTB_POS 16
210#define IRQ_MEM_DMA0_POS 20
211#define IRQ_MEM_DMA1_POS 24
212#define IRQ_WATCH_POS 28
213
214#endif /* _BF537_IRQ_H_ */
diff --git a/arch/blackfin/mach-bf537/include/mach/mem_init.h b/arch/blackfin/mach-bf537/include/mach/mem_init.h
new file mode 100644
index 000000000000..f67698f670ca
--- /dev/null
+++ b/arch/blackfin/mach-bf537/include/mach/mem_init.h
@@ -0,0 +1,303 @@
1/*
2 * File: include/asm-blackfin/mach-bf537/mem_init.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 * Copyright 2004-2006 Analog Devices Inc.
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || CONFIG_MEM_MT48LC16M8A2TG_75 || CONFIG_MEM_GENERIC_BOARD || CONFIG_MEM_MT48LC32M8A2_75)
33#if (CONFIG_SCLK_HZ > 119402985)
34#define SDRAM_tRP TRP_2
35#define SDRAM_tRP_num 2
36#define SDRAM_tRAS TRAS_7
37#define SDRAM_tRAS_num 7
38#define SDRAM_tRCD TRCD_2
39#define SDRAM_tWR TWR_2
40#endif
41#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
42#define SDRAM_tRP TRP_2
43#define SDRAM_tRP_num 2
44#define SDRAM_tRAS TRAS_6
45#define SDRAM_tRAS_num 6
46#define SDRAM_tRCD TRCD_2
47#define SDRAM_tWR TWR_2
48#endif
49#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
50#define SDRAM_tRP TRP_2
51#define SDRAM_tRP_num 2
52#define SDRAM_tRAS TRAS_5
53#define SDRAM_tRAS_num 5
54#define SDRAM_tRCD TRCD_2
55#define SDRAM_tWR TWR_2
56#endif
57#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
58#define SDRAM_tRP TRP_2
59#define SDRAM_tRP_num 2
60#define SDRAM_tRAS TRAS_4
61#define SDRAM_tRAS_num 4
62#define SDRAM_tRCD TRCD_2
63#define SDRAM_tWR TWR_2
64#endif
65#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
66#define SDRAM_tRP TRP_2
67#define SDRAM_tRP_num 2
68#define SDRAM_tRAS TRAS_3
69#define SDRAM_tRAS_num 3
70#define SDRAM_tRCD TRCD_2
71#define SDRAM_tWR TWR_2
72#endif
73#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
74#define SDRAM_tRP TRP_1
75#define SDRAM_tRP_num 1
76#define SDRAM_tRAS TRAS_4
77#define SDRAM_tRAS_num 3
78#define SDRAM_tRCD TRCD_1
79#define SDRAM_tWR TWR_2
80#endif
81#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
82#define SDRAM_tRP TRP_1
83#define SDRAM_tRP_num 1
84#define SDRAM_tRAS TRAS_3
85#define SDRAM_tRAS_num 3
86#define SDRAM_tRCD TRCD_1
87#define SDRAM_tWR TWR_2
88#endif
89#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
90#define SDRAM_tRP TRP_1
91#define SDRAM_tRP_num 1
92#define SDRAM_tRAS TRAS_2
93#define SDRAM_tRAS_num 2
94#define SDRAM_tRCD TRCD_1
95#define SDRAM_tWR TWR_2
96#endif
97#if (CONFIG_SCLK_HZ <= 29850746)
98#define SDRAM_tRP TRP_1
99#define SDRAM_tRP_num 1
100#define SDRAM_tRAS TRAS_1
101#define SDRAM_tRAS_num 1
102#define SDRAM_tRCD TRCD_1
103#define SDRAM_tWR TWR_2
104#endif
105#endif
106
107#if (CONFIG_MEM_MT48LC16M16A2TG_75)
108 /*SDRAM INFORMATION: */
109#define SDRAM_Tref 64 /* Refresh period in milliseconds */
110#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
111#define SDRAM_CL CL_3
112#endif
113
114#if (CONFIG_MEM_MT48LC16M8A2TG_75)
115 /*SDRAM INFORMATION: */
116#define SDRAM_Tref 64 /* Refresh period in milliseconds */
117#define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
118#define SDRAM_CL CL_3
119#endif
120
121#if (CONFIG_MEM_MT48LC32M8A2_75)
122 /*SDRAM INFORMATION: */
123#define SDRAM_Tref 64 /* Refresh period in milliseconds */
124#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
125#define SDRAM_CL CL_3
126#endif
127
128#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
129 /*SDRAM INFORMATION: */
130#define SDRAM_Tref 64 /* Refresh period in milliseconds */
131#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
132#define SDRAM_CL CL_3
133#endif
134
135#if (CONFIG_MEM_GENERIC_BOARD)
136 /*SDRAM INFORMATION: Modify this for your board */
137#define SDRAM_Tref 64 /* Refresh period in milliseconds */
138#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
139#define SDRAM_CL CL_3
140#endif
141
142/* Equation from section 17 (p17-46) of BF533 HRM */
143#define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
144
145/* Enable SCLK Out */
146#define mem_SDGCTL (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
147
148#if defined CONFIG_CLKIN_HALF
149#define CLKIN_HALF 1
150#else
151#define CLKIN_HALF 0
152#endif
153
154#if defined CONFIG_PLL_BYPASS
155#define PLL_BYPASS 1
156#else
157#define PLL_BYPASS 0
158#endif
159
160/***************************************Currently Not Being Used *********************************/
161#define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
162#define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
163#define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ))
164#define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
165#define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
166
167#if (flash_EBIU_AMBCTL_TT > 3)
168#define flash_EBIU_AMBCTL0_TT B0TT_4
169#endif
170#if (flash_EBIU_AMBCTL_TT == 3)
171#define flash_EBIU_AMBCTL0_TT B0TT_3
172#endif
173#if (flash_EBIU_AMBCTL_TT == 2)
174#define flash_EBIU_AMBCTL0_TT B0TT_2
175#endif
176#if (flash_EBIU_AMBCTL_TT < 2)
177#define flash_EBIU_AMBCTL0_TT B0TT_1
178#endif
179
180#if (flash_EBIU_AMBCTL_ST > 3)
181#define flash_EBIU_AMBCTL0_ST B0ST_4
182#endif
183#if (flash_EBIU_AMBCTL_ST == 3)
184#define flash_EBIU_AMBCTL0_ST B0ST_3
185#endif
186#if (flash_EBIU_AMBCTL_ST == 2)
187#define flash_EBIU_AMBCTL0_ST B0ST_2
188#endif
189#if (flash_EBIU_AMBCTL_ST < 2)
190#define flash_EBIU_AMBCTL0_ST B0ST_1
191#endif
192
193#if (flash_EBIU_AMBCTL_HT > 2)
194#define flash_EBIU_AMBCTL0_HT B0HT_3
195#endif
196#if (flash_EBIU_AMBCTL_HT == 2)
197#define flash_EBIU_AMBCTL0_HT B0HT_2
198#endif
199#if (flash_EBIU_AMBCTL_HT == 1)
200#define flash_EBIU_AMBCTL0_HT B0HT_1
201#endif
202#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
203#define flash_EBIU_AMBCTL0_HT B0HT_0
204#endif
205#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
206#define flash_EBIU_AMBCTL0_HT B0HT_1
207#endif
208
209#if (flash_EBIU_AMBCTL_WAT > 14)
210#define flash_EBIU_AMBCTL0_WAT B0WAT_15
211#endif
212#if (flash_EBIU_AMBCTL_WAT == 14)
213#define flash_EBIU_AMBCTL0_WAT B0WAT_14
214#endif
215#if (flash_EBIU_AMBCTL_WAT == 13)
216#define flash_EBIU_AMBCTL0_WAT B0WAT_13
217#endif
218#if (flash_EBIU_AMBCTL_WAT == 12)
219#define flash_EBIU_AMBCTL0_WAT B0WAT_12
220#endif
221#if (flash_EBIU_AMBCTL_WAT == 11)
222#define flash_EBIU_AMBCTL0_WAT B0WAT_11
223#endif
224#if (flash_EBIU_AMBCTL_WAT == 10)
225#define flash_EBIU_AMBCTL0_WAT B0WAT_10
226#endif
227#if (flash_EBIU_AMBCTL_WAT == 9)
228#define flash_EBIU_AMBCTL0_WAT B0WAT_9
229#endif
230#if (flash_EBIU_AMBCTL_WAT == 8)
231#define flash_EBIU_AMBCTL0_WAT B0WAT_8
232#endif
233#if (flash_EBIU_AMBCTL_WAT == 7)
234#define flash_EBIU_AMBCTL0_WAT B0WAT_7
235#endif
236#if (flash_EBIU_AMBCTL_WAT == 6)
237#define flash_EBIU_AMBCTL0_WAT B0WAT_6
238#endif
239#if (flash_EBIU_AMBCTL_WAT == 5)
240#define flash_EBIU_AMBCTL0_WAT B0WAT_5
241#endif
242#if (flash_EBIU_AMBCTL_WAT == 4)
243#define flash_EBIU_AMBCTL0_WAT B0WAT_4
244#endif
245#if (flash_EBIU_AMBCTL_WAT == 3)
246#define flash_EBIU_AMBCTL0_WAT B0WAT_3
247#endif
248#if (flash_EBIU_AMBCTL_WAT == 2)
249#define flash_EBIU_AMBCTL0_WAT B0WAT_2
250#endif
251#if (flash_EBIU_AMBCTL_WAT == 1)
252#define flash_EBIU_AMBCTL0_WAT B0WAT_1
253#endif
254
255#if (flash_EBIU_AMBCTL_RAT > 14)
256#define flash_EBIU_AMBCTL0_RAT B0RAT_15
257#endif
258#if (flash_EBIU_AMBCTL_RAT == 14)
259#define flash_EBIU_AMBCTL0_RAT B0RAT_14
260#endif
261#if (flash_EBIU_AMBCTL_RAT == 13)
262#define flash_EBIU_AMBCTL0_RAT B0RAT_13
263#endif
264#if (flash_EBIU_AMBCTL_RAT == 12)
265#define flash_EBIU_AMBCTL0_RAT B0RAT_12
266#endif
267#if (flash_EBIU_AMBCTL_RAT == 11)
268#define flash_EBIU_AMBCTL0_RAT B0RAT_11
269#endif
270#if (flash_EBIU_AMBCTL_RAT == 10)
271#define flash_EBIU_AMBCTL0_RAT B0RAT_10
272#endif
273#if (flash_EBIU_AMBCTL_RAT == 9)
274#define flash_EBIU_AMBCTL0_RAT B0RAT_9
275#endif
276#if (flash_EBIU_AMBCTL_RAT == 8)
277#define flash_EBIU_AMBCTL0_RAT B0RAT_8
278#endif
279#if (flash_EBIU_AMBCTL_RAT == 7)
280#define flash_EBIU_AMBCTL0_RAT B0RAT_7
281#endif
282#if (flash_EBIU_AMBCTL_RAT == 6)
283#define flash_EBIU_AMBCTL0_RAT B0RAT_6
284#endif
285#if (flash_EBIU_AMBCTL_RAT == 5)
286#define flash_EBIU_AMBCTL0_RAT B0RAT_5
287#endif
288#if (flash_EBIU_AMBCTL_RAT == 4)
289#define flash_EBIU_AMBCTL0_RAT B0RAT_4
290#endif
291#if (flash_EBIU_AMBCTL_RAT == 3)
292#define flash_EBIU_AMBCTL0_RAT B0RAT_3
293#endif
294#if (flash_EBIU_AMBCTL_RAT == 2)
295#define flash_EBIU_AMBCTL0_RAT B0RAT_2
296#endif
297#if (flash_EBIU_AMBCTL_RAT == 1)
298#define flash_EBIU_AMBCTL0_RAT B0RAT_1
299#endif
300
301#define flash_EBIU_AMBCTL0 \
302 (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
303 flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
diff --git a/arch/blackfin/mach-bf537/include/mach/mem_map.h b/arch/blackfin/mach-bf537/include/mach/mem_map.h
new file mode 100644
index 000000000000..5078b669431f
--- /dev/null
+++ b/arch/blackfin/mach-bf537/include/mach/mem_map.h
@@ -0,0 +1,179 @@
1/*
2 * file: include/asm-blackfin/mach-bf537/mem_map.h
3 * based on:
4 * author:
5 *
6 * created:
7 * description:
8 * Memory MAP Common header file for blackfin BF537/6/4 of processors.
9 * rev:
10 *
11 * modified:
12 *
13 * bugs: enter bugs at http://blackfin.uclinux.org/
14 *
15 * this program is free software; you can redistribute it and/or modify
16 * it under the terms of the gnu general public license as published by
17 * the free software foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * this program is distributed in the hope that it will be useful,
21 * but without any warranty; without even the implied warranty of
22 * merchantability or fitness for a particular purpose. see the
23 * gnu general public license for more details.
24 *
25 * you should have received a copy of the gnu general public license
26 * along with this program; see the file copying.
27 * if not, write to the free software foundation,
28 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
29 */
30
31#ifndef _MEM_MAP_537_H_
32#define _MEM_MAP_537_H_
33
34#define COREMMR_BASE 0xFFE00000 /* Core MMRs */
35#define SYSMMR_BASE 0xFFC00000 /* System MMRs */
36
37/* Async Memory Banks */
38#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */
39#define ASYNC_BANK3_SIZE 0x00100000 /* 1M */
40#define ASYNC_BANK2_BASE 0x20200000 /* Async Bank 2 */
41#define ASYNC_BANK2_SIZE 0x00100000 /* 1M */
42#define ASYNC_BANK1_BASE 0x20100000 /* Async Bank 1 */
43#define ASYNC_BANK1_SIZE 0x00100000 /* 1M */
44#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
45#define ASYNC_BANK0_SIZE 0x00100000 /* 1M */
46
47/* Boot ROM Memory */
48
49#define BOOT_ROM_START 0xEF000000
50#define BOOT_ROM_LENGTH 0x800
51
52/* Level 1 Memory */
53
54/* Memory Map for ADSP-BF537 processors */
55
56#ifdef CONFIG_BFIN_ICACHE
57#define BFIN_ICACHESIZE (16*1024)
58#else
59#define BFIN_ICACHESIZE (0*1024)
60#endif
61
62
63#ifdef CONFIG_BF537
64#define L1_CODE_START 0xFFA00000
65#define L1_DATA_A_START 0xFF800000
66#define L1_DATA_B_START 0xFF900000
67
68#define L1_CODE_LENGTH 0xC000
69
70#ifdef CONFIG_BFIN_DCACHE
71
72#ifdef CONFIG_BFIN_DCACHE_BANKA
73#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
74#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
75#define L1_DATA_B_LENGTH 0x8000
76#define BFIN_DCACHESIZE (16*1024)
77#define BFIN_DSUPBANKS 1
78#else
79#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
80#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
81#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
82#define BFIN_DCACHESIZE (32*1024)
83#define BFIN_DSUPBANKS 2
84#endif
85
86#else
87#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
88#define L1_DATA_A_LENGTH 0x8000
89#define L1_DATA_B_LENGTH 0x8000
90#define BFIN_DCACHESIZE (0*1024)
91#define BFIN_DSUPBANKS 0
92#endif /*CONFIG_BFIN_DCACHE*/
93
94#endif /*CONFIG_BF537*/
95
96/* Memory Map for ADSP-BF536 processors */
97
98#ifdef CONFIG_BF536
99#define L1_CODE_START 0xFFA00000
100#define L1_DATA_A_START 0xFF804000
101#define L1_DATA_B_START 0xFF904000
102
103#define L1_CODE_LENGTH 0xC000
104
105
106#ifdef CONFIG_BFIN_DCACHE
107
108#ifdef CONFIG_BFIN_DCACHE_BANKA
109#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
110#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
111#define L1_DATA_B_LENGTH 0x4000
112#define BFIN_DCACHESIZE (16*1024)
113#define BFIN_DSUPBANKS 1
114
115#else
116#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
117#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
118#define L1_DATA_B_LENGTH (0x4000 - 0x4000)
119#define BFIN_DCACHESIZE (32*1024)
120#define BFIN_DSUPBANKS 2
121#endif
122
123#else
124#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
125#define L1_DATA_A_LENGTH 0x4000
126#define L1_DATA_B_LENGTH 0x4000
127#define BFIN_DCACHESIZE (0*1024)
128#define BFIN_DSUPBANKS 0
129#endif /*CONFIG_BFIN_DCACHE*/
130
131#endif
132
133/* Memory Map for ADSP-BF534 processors */
134
135#ifdef CONFIG_BF534
136#define L1_CODE_START 0xFFA00000
137#define L1_DATA_A_START 0xFF800000
138#define L1_DATA_B_START 0xFF900000
139
140#define L1_CODE_LENGTH 0xC000
141
142#ifdef CONFIG_BFIN_DCACHE
143
144#ifdef CONFIG_BFIN_DCACHE_BANKA
145#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
146#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
147#define L1_DATA_B_LENGTH 0x8000
148#define BFIN_DCACHESIZE (16*1024)
149#define BFIN_DSUPBANKS 1
150
151#else
152#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
153#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
154#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
155#define BFIN_DCACHESIZE (32*1024)
156#define BFIN_DSUPBANKS 2
157#endif
158
159#else
160#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
161#define L1_DATA_A_LENGTH 0x8000
162#define L1_DATA_B_LENGTH 0x8000
163#define BFIN_DCACHESIZE (0*1024)
164#define BFIN_DSUPBANKS 0
165#endif /*CONFIG_BFIN_DCACHE*/
166
167#endif
168
169/* Level 2 Memory - none */
170
171#define L2_START 0
172#define L2_LENGTH 0
173
174/* Scratch Pad Memory */
175
176#define L1_SCRATCH_START 0xFFB00000
177#define L1_SCRATCH_LENGTH 0x1000
178
179#endif /* _MEM_MAP_537_H_ */
diff --git a/arch/blackfin/mach-bf537/include/mach/portmux.h b/arch/blackfin/mach-bf537/include/mach/portmux.h
new file mode 100644
index 000000000000..78fee6e0f237
--- /dev/null
+++ b/arch/blackfin/mach-bf537/include/mach/portmux.h
@@ -0,0 +1,144 @@
1#ifndef _MACH_PORTMUX_H_
2#define _MACH_PORTMUX_H_
3
4#define MAX_RESOURCES (MAX_BLACKFIN_GPIOS + GPIO_BANKSIZE) /* We additionally handle PORTJ */
5
6#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
7#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
8#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
9#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
10#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
11#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
12#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
13#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
14#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
15#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
16#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
17#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
18#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
19#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
20#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
21#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
22#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
23#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
24#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
25#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
26#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
27#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
28#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
29#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
30#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
31#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
32#define P_TACLK0 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
33#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
34
35#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
36#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
37#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
38#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
39#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
40#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
41#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
42#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
43#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
44#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
45#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
46#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
47#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
48#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
49#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
50#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
51#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
52#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
53#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
54#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
55#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
56#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
57#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
58#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
59
60#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
61#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
62#define P_MII0_ETxD2 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
63#define P_MII0_ETxD3 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
64#define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
65#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
66#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
67#define P_MII0_COL (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
68#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0))
69#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0))
70#define P_MII0_ERxD2 (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0))
71#define P_MII0_ERxD3 (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0))
72#define P_MII0_ERxDV (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0))
73#define P_MII0_ERxCLK (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0))
74#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(0))
75#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(0))
76#define P_RMII0_REF_CLK (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1))
77#define P_RMII0_MDINT (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
78#define P_RMII0_CRS_DV (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(1))
79
80#define PORT_PJ0 (GPIO_PH15 + 1)
81#define PORT_PJ1 (GPIO_PH15 + 2)
82#define PORT_PJ2 (GPIO_PH15 + 3)
83#define PORT_PJ3 (GPIO_PH15 + 4)
84#define PORT_PJ4 (GPIO_PH15 + 5)
85#define PORT_PJ5 (GPIO_PH15 + 6)
86#define PORT_PJ6 (GPIO_PH15 + 7)
87#define PORT_PJ7 (GPIO_PH15 + 8)
88#define PORT_PJ8 (GPIO_PH15 + 9)
89#define PORT_PJ9 (GPIO_PH15 + 10)
90#define PORT_PJ10 (GPIO_PH15 + 11)
91#define PORT_PJ11 (GPIO_PH15 + 12)
92
93#define P_MDC (P_DEFINED | P_IDENT(PORT_PJ0) | P_FUNCT(0))
94#define P_MDIO (P_DEFINED | P_IDENT(PORT_PJ1) | P_FUNCT(0))
95#define P_TWI0_SCL (P_DEFINED | P_IDENT(PORT_PJ2) | P_FUNCT(0))
96#define P_TWI0_SDA (P_DEFINED | P_IDENT(PORT_PJ3) | P_FUNCT(0))
97#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(PORT_PJ4) | P_FUNCT(0))
98#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(0))
99#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(PORT_PJ6) | P_FUNCT(0))
100#define P_SPORT0_RFS (P_DEFINED | P_IDENT(PORT_PJ7) | P_FUNCT(0))
101#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(PORT_PJ8) | P_FUNCT(0))
102#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(PORT_PJ9) | P_FUNCT(0))
103#define P_SPORT0_TFS (P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(0))
104#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(0))
105#define P_CAN0_RX (P_DEFINED | P_IDENT(PORT_PJ4) | P_FUNCT(1))
106#define P_CAN0_TX (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(1))
107#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(1))
108#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(1))
109#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(2))
110
111#define P_MII0 {\
112 P_MII0_ETxD0, \
113 P_MII0_ETxD1, \
114 P_MII0_ETxD2, \
115 P_MII0_ETxD3, \
116 P_MII0_ETxEN, \
117 P_MII0_TxCLK, \
118 P_MII0_PHYINT, \
119 P_MII0_COL, \
120 P_MII0_ERxD0, \
121 P_MII0_ERxD1, \
122 P_MII0_ERxD2, \
123 P_MII0_ERxD3, \
124 P_MII0_ERxDV, \
125 P_MII0_ERxCLK, \
126 P_MII0_ERxER, \
127 P_MII0_CRS, \
128 P_MDC, \
129 P_MDIO, 0}
130
131
132#define P_RMII0 {\
133 P_MII0_ETxD0, \
134 P_MII0_ETxD1, \
135 P_MII0_ETxEN, \
136 P_MII0_ERxD0, \
137 P_MII0_ERxD1, \
138 P_MII0_ERxER, \
139 P_RMII0_REF_CLK, \
140 P_RMII0_MDINT, \
141 P_RMII0_CRS_DV, \
142 P_MDC, \
143 P_MDIO, 0}
144#endif /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/mach-bf548/boards/cm_bf548.c b/arch/blackfin/mach-bf548/boards/cm_bf548.c
index 58abbed0a225..ce934ee174e0 100644
--- a/arch/blackfin/mach-bf548/boards/cm_bf548.c
+++ b/arch/blackfin/mach-bf548/boards/cm_bf548.c
@@ -45,7 +45,7 @@
45#include <asm/gpio.h> 45#include <asm/gpio.h>
46#include <asm/nand.h> 46#include <asm/nand.h>
47#include <asm/portmux.h> 47#include <asm/portmux.h>
48#include <asm/mach/bf54x_keys.h> 48#include <mach/bf54x_keys.h>
49#include <asm/dpmc.h> 49#include <asm/dpmc.h>
50#include <linux/input.h> 50#include <linux/input.h>
51#include <linux/spi/ad7877.h> 51#include <linux/spi/ad7877.h>
@@ -61,7 +61,7 @@ const char bfin_board_name[] = "Bluetechnix CM-BF548";
61 61
62#if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE) 62#if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE)
63 63
64#include <asm/mach/bf54x-lq043.h> 64#include <mach/bf54x-lq043.h>
65 65
66static struct bfin_bf54xfb_mach_info bf54x_lq043_data = { 66static struct bfin_bf54xfb_mach_info bf54x_lq043_data = {
67 .width = 480, 67 .width = 480,
diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c
index 0d6333ada1d9..39357693046d 100644
--- a/arch/blackfin/mach-bf548/boards/ezkit.c
+++ b/arch/blackfin/mach-bf548/boards/ezkit.c
@@ -48,7 +48,7 @@
48#include <asm/nand.h> 48#include <asm/nand.h>
49#include <asm/dpmc.h> 49#include <asm/dpmc.h>
50#include <asm/portmux.h> 50#include <asm/portmux.h>
51#include <asm/mach/bf54x_keys.h> 51#include <mach/bf54x_keys.h>
52#include <linux/input.h> 52#include <linux/input.h>
53#include <linux/spi/ad7877.h> 53#include <linux/spi/ad7877.h>
54 54
@@ -106,7 +106,7 @@ arch_initcall(bfin_isp1761_init);
106 106
107#if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE) 107#if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE)
108 108
109#include <asm/mach/bf54x-lq043.h> 109#include <mach/bf54x-lq043.h>
110 110
111static struct bfin_bf54xfb_mach_info bf54x_lq043_data = { 111static struct bfin_bf54xfb_mach_info bf54x_lq043_data = {
112 .width = 480, 112 .width = 480,
diff --git a/arch/blackfin/mach-bf548/head.S b/arch/blackfin/mach-bf548/head.S
index e3000f70a26e..4d5cfeacb123 100644
--- a/arch/blackfin/mach-bf548/head.S
+++ b/arch/blackfin/mach-bf548/head.S
@@ -31,8 +31,8 @@
31#include <linux/init.h> 31#include <linux/init.h>
32#include <asm/blackfin.h> 32#include <asm/blackfin.h>
33#ifdef CONFIG_BFIN_KERNEL_CLOCK 33#ifdef CONFIG_BFIN_KERNEL_CLOCK
34#include <asm/mach-common/clocks.h> 34#include <asm/clocks.h>
35#include <asm/mach/mem_init.h> 35#include <mach/mem_init.h>
36#endif 36#endif
37 37
38.section .l1.text 38.section .l1.text
diff --git a/arch/blackfin/mach-bf548/include/mach/anomaly.h b/arch/blackfin/mach-bf548/include/mach/anomaly.h
new file mode 100644
index 000000000000..3ad59655881a
--- /dev/null
+++ b/arch/blackfin/mach-bf548/include/mach/anomaly.h
@@ -0,0 +1,100 @@
1/*
2 * File: include/asm-blackfin/mach-bf548/anomaly.h
3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
4 *
5 * Copyright (C) 2004-2007 Analog Devices Inc.
6 * Licensed under the GPL-2 or later.
7 */
8
9/* This file shoule be up to date with:
10 * - Revision E, 11/28/2007; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
11 */
12
13#ifndef _MACH_ANOMALY_H_
14#define _MACH_ANOMALY_H_
15
16/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */
17#define ANOMALY_05000074 (1)
18/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
19#define ANOMALY_05000119 (1)
20/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
21#define ANOMALY_05000122 (1)
22/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
23#define ANOMALY_05000245 (1)
24/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
25#define ANOMALY_05000265 (1)
26/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
27#define ANOMALY_05000272 (1)
28/* False Hardware Error Exception when ISR context is not restored */
29#define ANOMALY_05000281 (__SILICON_REVISION__ < 1)
30/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
31#define ANOMALY_05000304 (__SILICON_REVISION__ < 1)
32/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
33#define ANOMALY_05000310 (1)
34/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
35#define ANOMALY_05000312 (__SILICON_REVISION__ < 1)
36/* TWI Slave Boot Mode Is Not Functional */
37#define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
38/* External FIFO Boot Mode Is Not Functional */
39#define ANOMALY_05000325 (__SILICON_REVISION__ < 1)
40/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
41#define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
42/* Incorrect Access of OTP_STATUS During otp_write() Function */
43#define ANOMALY_05000328 (__SILICON_REVISION__ < 1)
44/* Synchronous Burst Flash Boot Mode Is Not Functional */
45#define ANOMALY_05000329 (__SILICON_REVISION__ < 1)
46/* Host DMA Boot Mode Is Not Functional */
47#define ANOMALY_05000330 (__SILICON_REVISION__ < 1)
48/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */
49#define ANOMALY_05000334 (__SILICON_REVISION__ < 1)
50/* Inadequate Rotary Debounce Logic Duration */
51#define ANOMALY_05000335 (__SILICON_REVISION__ < 1)
52/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */
53#define ANOMALY_05000336 (__SILICON_REVISION__ < 1)
54/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
55#define ANOMALY_05000337 (__SILICON_REVISION__ < 1)
56/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
57#define ANOMALY_05000338 (__SILICON_REVISION__ < 1)
58/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */
59#define ANOMALY_05000340 (__SILICON_REVISION__ < 1)
60/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */
61#define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
62/* USB Calibration Value Is Not Intialized */
63#define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
64/* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */
65#define ANOMALY_05000347 (__SILICON_REVISION__ < 1)
66/* Data Lost when Core Reads SDH Data FIFO */
67#define ANOMALY_05000349 (__SILICON_REVISION__ < 1)
68/* PLL Status Register Is Inaccurate */
69#define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
70/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
71#define ANOMALY_05000357 (1)
72/* External Memory Read Access Hangs Core With PLL Bypass */
73#define ANOMALY_05000360 (1)
74/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
75#define ANOMALY_05000365 (1)
76/* Addressing Conflict between Boot ROM and Asynchronous Memory */
77#define ANOMALY_05000369 (1)
78/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
79#define ANOMALY_05000371 (1)
80/* Mobile DDR Operation Not Functional */
81#define ANOMALY_05000377 (1)
82/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
83#define ANOMALY_05000378 (1)
84
85/* Anomalies that don't exist on this proc */
86#define ANOMALY_05000125 (0)
87#define ANOMALY_05000158 (0)
88#define ANOMALY_05000183 (0)
89#define ANOMALY_05000198 (0)
90#define ANOMALY_05000230 (0)
91#define ANOMALY_05000244 (0)
92#define ANOMALY_05000261 (0)
93#define ANOMALY_05000263 (0)
94#define ANOMALY_05000266 (0)
95#define ANOMALY_05000273 (0)
96#define ANOMALY_05000311 (0)
97#define ANOMALY_05000323 (0)
98#define ANOMALY_05000363 (0)
99
100#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/bf548.h b/arch/blackfin/mach-bf548/include/mach/bf548.h
new file mode 100644
index 000000000000..e748588e8930
--- /dev/null
+++ b/arch/blackfin/mach-bf548/include/mach/bf548.h
@@ -0,0 +1,127 @@
1/*
2 * File: include/asm-blackfin/mach-bf548/bf548.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: System MMR register and memory map for ADSP-BF548
8 *
9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#ifndef __MACH_BF548_H__
31#define __MACH_BF548_H__
32
33#define SUPPORTED_REVID 0
34
35#define OFFSET_(x) ((x) & 0x0000FFFF)
36
37/*some misc defines*/
38#define IMASK_IVG15 0x8000
39#define IMASK_IVG14 0x4000
40#define IMASK_IVG13 0x2000
41#define IMASK_IVG12 0x1000
42
43#define IMASK_IVG11 0x0800
44#define IMASK_IVG10 0x0400
45#define IMASK_IVG9 0x0200
46#define IMASK_IVG8 0x0100
47
48#define IMASK_IVG7 0x0080
49#define IMASK_IVGTMR 0x0040
50#define IMASK_IVGHW 0x0020
51
52/***************************/
53
54
55#define BFIN_DSUBBANKS 4
56#define BFIN_DWAYS 2
57#define BFIN_DLINES 64
58#define BFIN_ISUBBANKS 4
59#define BFIN_IWAYS 4
60#define BFIN_ILINES 32
61
62#define WAY0_L 0x1
63#define WAY1_L 0x2
64#define WAY01_L 0x3
65#define WAY2_L 0x4
66#define WAY02_L 0x5
67#define WAY12_L 0x6
68#define WAY012_L 0x7
69
70#define WAY3_L 0x8
71#define WAY03_L 0x9
72#define WAY13_L 0xA
73#define WAY013_L 0xB
74
75#define WAY32_L 0xC
76#define WAY320_L 0xD
77#define WAY321_L 0xE
78#define WAYALL_L 0xF
79
80#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
81
82/********************************* EBIU Settings ************************************/
83#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
84#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
85
86#ifdef CONFIG_C_AMBEN_ALL
87#define V_AMBEN AMBEN_ALL
88#endif
89#ifdef CONFIG_C_AMBEN
90#define V_AMBEN 0x0
91#endif
92#ifdef CONFIG_C_AMBEN_B0
93#define V_AMBEN AMBEN_B0
94#endif
95#ifdef CONFIG_C_AMBEN_B0_B1
96#define V_AMBEN AMBEN_B0_B1
97#endif
98#ifdef CONFIG_C_AMBEN_B0_B1_B2
99#define V_AMBEN AMBEN_B0_B1_B2
100#endif
101#ifdef CONFIG_C_AMCKEN
102#define V_AMCKEN AMCKEN
103#else
104#define V_AMCKEN 0x0
105#endif
106
107#define AMGCTLVAL (V_AMBEN | V_AMCKEN)
108
109#if defined(CONFIG_BF542)
110# define CPU "BF542"
111# define CPUID 0x027c8000
112#elif defined(CONFIG_BF544)
113# define CPU "BF544"
114# define CPUID 0x027c8000
115#elif defined(CONFIG_BF547)
116# define CPU "BF547"
117#elif defined(CONFIG_BF548)
118# define CPU "BF548"
119# define CPUID 0x027c6000
120#elif defined(CONFIG_BF549)
121# define CPU "BF549"
122#else
123# define CPU "UNKNOWN"
124# define CPUID 0x0
125#endif
126
127#endif /* __MACH_BF48_H__ */
diff --git a/arch/blackfin/mach-bf548/include/mach/bf54x-lq043.h b/arch/blackfin/mach-bf548/include/mach/bf54x-lq043.h
new file mode 100644
index 000000000000..9c7ca62a45eb
--- /dev/null
+++ b/arch/blackfin/mach-bf548/include/mach/bf54x-lq043.h
@@ -0,0 +1,30 @@
1#ifndef BF54X_LQ043_H
2#define BF54X_LQ043_H
3
4struct bfin_bf54xfb_val {
5 unsigned int defval;
6 unsigned int min;
7 unsigned int max;
8};
9
10struct bfin_bf54xfb_mach_info {
11 unsigned char fixed_syncs; /* do not update sync/border */
12
13 /* LCD types */
14 int type;
15
16 /* Screen size */
17 int width;
18 int height;
19
20 /* Screen info */
21 struct bfin_bf54xfb_val xres;
22 struct bfin_bf54xfb_val yres;
23 struct bfin_bf54xfb_val bpp;
24
25 /* GPIOs */
26 unsigned short disp;
27
28};
29
30#endif /* BF54X_LQ043_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/bf54x_keys.h b/arch/blackfin/mach-bf548/include/mach/bf54x_keys.h
new file mode 100644
index 000000000000..1fb4ec77cc25
--- /dev/null
+++ b/arch/blackfin/mach-bf548/include/mach/bf54x_keys.h
@@ -0,0 +1,17 @@
1#ifndef _BFIN_KPAD_H
2#define _BFIN_KPAD_H
3
4struct bfin_kpad_platform_data {
5 int rows;
6 int cols;
7 const unsigned int *keymap;
8 unsigned short keymapsize;
9 unsigned short repeat;
10 u32 debounce_time; /* in ns */
11 u32 coldrive_time; /* in ns */
12 u32 keyup_test_interval; /* in ms */
13};
14
15#define KEYVAL(col, row, val) (((1 << col) << 24) | ((1 << row) << 16) | (val))
16
17#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h
new file mode 100644
index 000000000000..5e29446a8e03
--- /dev/null
+++ b/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h
@@ -0,0 +1,220 @@
1/*
2 * file: include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
3 * based on:
4 * author:
5 *
6 * created:
7 * description:
8 * blackfin serial driver head file
9 * rev:
10 *
11 * modified:
12 *
13 *
14 * bugs: enter bugs at http://blackfin.uclinux.org/
15 *
16 * this program is free software; you can redistribute it and/or modify
17 * it under the terms of the gnu general public license as published by
18 * the free software foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * this program is distributed in the hope that it will be useful,
22 * but without any warranty; without even the implied warranty of
23 * merchantability or fitness for a particular purpose. see the
24 * gnu general public license for more details.
25 *
26 * you should have received a copy of the gnu general public license
27 * along with this program; see the file copying.
28 * if not, write to the free software foundation,
29 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
30 */
31
32#include <linux/serial.h>
33#include <asm/dma.h>
34#include <asm/portmux.h>
35
36#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
37#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
38#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
39#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER_SET))
40#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
41#define UART_GET_LSR(uart) bfin_read16(((uart)->port.membase + OFFSET_LSR))
42#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
43#define UART_GET_MSR(uart) bfin_read16(((uart)->port.membase + OFFSET_MSR))
44#define UART_GET_MCR(uart) bfin_read16(((uart)->port.membase + OFFSET_MCR))
45
46#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
47#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
48#define UART_SET_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER_SET),v)
49#define UART_CLEAR_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER_CLEAR),v)
50#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
51#define UART_PUT_LSR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LSR),v)
52#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
53#define UART_CLEAR_LSR(uart) bfin_write16(((uart)->port.membase + OFFSET_LSR), -1)
54#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
55#define UART_PUT_MCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_MCR),v)
56
57#define UART_SET_DLAB(uart) /* MMRs not muxed on BF54x */
58#define UART_CLEAR_DLAB(uart) /* MMRs not muxed on BF54x */
59
60#define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS)
61#define UART_SET_RTS(x) (UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS))
62#define UART_CLEAR_RTS(x) (UART_PUT_MCR(x, UART_GET_MCR(x) & ~MRTS))
63#define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v)
64#define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF)
65
66#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
67# define CONFIG_SERIAL_BFIN_CTSRTS
68
69# ifndef CONFIG_UART0_CTS_PIN
70# define CONFIG_UART0_CTS_PIN -1
71# endif
72
73# ifndef CONFIG_UART0_RTS_PIN
74# define CONFIG_UART0_RTS_PIN -1
75# endif
76
77# ifndef CONFIG_UART1_CTS_PIN
78# define CONFIG_UART1_CTS_PIN -1
79# endif
80
81# ifndef CONFIG_UART1_RTS_PIN
82# define CONFIG_UART1_RTS_PIN -1
83# endif
84#endif
85/*
86 * The pin configuration is different from schematic
87 */
88struct bfin_serial_port {
89 struct uart_port port;
90 unsigned int old_status;
91#ifdef CONFIG_SERIAL_BFIN_DMA
92 int tx_done;
93 int tx_count;
94 struct circ_buf rx_dma_buf;
95 struct timer_list rx_dma_timer;
96 int rx_dma_nrows;
97 unsigned int tx_dma_channel;
98 unsigned int rx_dma_channel;
99 struct work_struct tx_dma_workqueue;
100#endif
101#ifdef CONFIG_SERIAL_BFIN_CTSRTS
102 struct timer_list cts_timer;
103 int cts_pin;
104 int rts_pin;
105#endif
106};
107
108struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
109struct bfin_serial_res {
110 unsigned long uart_base_addr;
111 int uart_irq;
112#ifdef CONFIG_SERIAL_BFIN_DMA
113 unsigned int uart_tx_dma_channel;
114 unsigned int uart_rx_dma_channel;
115#endif
116#ifdef CONFIG_SERIAL_BFIN_CTSRTS
117 int uart_cts_pin;
118 int uart_rts_pin;
119#endif
120};
121
122struct bfin_serial_res bfin_serial_resource[] = {
123#ifdef CONFIG_SERIAL_BFIN_UART0
124 {
125 0xFFC00400,
126 IRQ_UART0_RX,
127#ifdef CONFIG_SERIAL_BFIN_DMA
128 CH_UART0_TX,
129 CH_UART0_RX,
130#endif
131#ifdef CONFIG_BFIN_UART0_CTSRTS
132 CONFIG_UART0_CTS_PIN,
133 CONFIG_UART0_RTS_PIN,
134#endif
135 },
136#endif
137#ifdef CONFIG_SERIAL_BFIN_UART1
138 {
139 0xFFC02000,
140 IRQ_UART1_RX,
141#ifdef CONFIG_SERIAL_BFIN_DMA
142 CH_UART1_TX,
143 CH_UART1_RX,
144#endif
145 },
146#endif
147#ifdef CONFIG_SERIAL_BFIN_UART2
148 {
149 0xFFC02100,
150 IRQ_UART2_RX,
151#ifdef CONFIG_SERIAL_BFIN_DMA
152 CH_UART2_TX,
153 CH_UART2_RX,
154#endif
155#ifdef CONFIG_BFIN_UART2_CTSRTS
156 CONFIG_UART2_CTS_PIN,
157 CONFIG_UART2_RTS_PIN,
158#endif
159 },
160#endif
161#ifdef CONFIG_SERIAL_BFIN_UART3
162 {
163 0xFFC03100,
164 IRQ_UART3_RX,
165#ifdef CONFIG_SERIAL_BFIN_DMA
166 CH_UART3_TX,
167 CH_UART3_RX,
168#endif
169 },
170#endif
171};
172
173int nr_ports = ARRAY_SIZE(bfin_serial_resource);
174
175#define DRIVER_NAME "bfin-uart"
176
177static void bfin_serial_hw_init(struct bfin_serial_port *uart)
178{
179#ifdef CONFIG_SERIAL_BFIN_UART0
180 peripheral_request(P_UART0_TX, DRIVER_NAME);
181 peripheral_request(P_UART0_RX, DRIVER_NAME);
182#endif
183
184#ifdef CONFIG_SERIAL_BFIN_UART1
185 peripheral_request(P_UART1_TX, DRIVER_NAME);
186 peripheral_request(P_UART1_RX, DRIVER_NAME);
187
188#ifdef CONFIG_BFIN_UART1_CTSRTS
189 peripheral_request(P_UART1_RTS, DRIVER_NAME);
190 peripheral_request(P_UART1_CTS, DRIVER_NAME);
191#endif
192#endif
193
194#ifdef CONFIG_SERIAL_BFIN_UART2
195 peripheral_request(P_UART2_TX, DRIVER_NAME);
196 peripheral_request(P_UART2_RX, DRIVER_NAME);
197#endif
198
199#ifdef CONFIG_SERIAL_BFIN_UART3
200 peripheral_request(P_UART3_TX, DRIVER_NAME);
201 peripheral_request(P_UART3_RX, DRIVER_NAME);
202
203#ifdef CONFIG_BFIN_UART3_CTSRTS
204 peripheral_request(P_UART3_RTS, DRIVER_NAME);
205 peripheral_request(P_UART3_CTS, DRIVER_NAME);
206#endif
207#endif
208 SSYNC();
209#ifdef CONFIG_SERIAL_BFIN_CTSRTS
210 if (uart->cts_pin >= 0) {
211 gpio_request(uart->cts_pin, DRIVER_NAME);
212 gpio_direction_input(uart->cts_pin);
213 }
214
215 if (uart->rts_pin >= 0) {
216 gpio_request(uart->rts_pin, DRIVER_NAME);
217 gpio_direction_output(uart->rts_pin, 0);
218 }
219#endif
220}
diff --git a/arch/blackfin/mach-bf548/include/mach/bfin_sir.h b/arch/blackfin/mach-bf548/include/mach/bfin_sir.h
new file mode 100644
index 000000000000..c41f9cf00268
--- /dev/null
+++ b/arch/blackfin/mach-bf548/include/mach/bfin_sir.h
@@ -0,0 +1,166 @@
1/*
2 * Blackfin Infra-red Driver
3 *
4 * Copyright 2006-2008 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 *
10 */
11
12#include <linux/serial.h>
13#include <asm/dma.h>
14#include <asm/portmux.h>
15
16#define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR)
17#define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL)
18#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER_SET)
19#define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH)
20#define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR)
21#define SIR_UART_GET_LSR(port) bfin_read16((port)->membase + OFFSET_LSR)
22#define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL)
23
24#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
25#define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v)
26#define SIR_UART_SET_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER_SET), v)
27#define SIR_UART_CLEAR_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER_CLEAR), v)
28#define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v)
29#define SIR_UART_PUT_LSR(port, v) bfin_write16(((port)->membase + OFFSET_LSR), v)
30#define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v)
31#define SIR_UART_CLEAR_LSR(port) bfin_write16(((port)->membase + OFFSET_LSR), -1)
32#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
33
34#ifdef CONFIG_SIR_BFIN_DMA
35struct dma_rx_buf {
36 char *buf;
37 int head;
38 int tail;
39 };
40#endif /* CONFIG_SIR_BFIN_DMA */
41
42struct bfin_sir_port {
43 unsigned char __iomem *membase;
44 unsigned int irq;
45 unsigned int lsr;
46 unsigned long clk;
47 struct net_device *dev;
48#ifdef CONFIG_SIR_BFIN_DMA
49 int tx_done;
50 struct dma_rx_buf rx_dma_buf;
51 struct timer_list rx_dma_timer;
52 int rx_dma_nrows;
53#endif /* CONFIG_SIR_BFIN_DMA */
54 unsigned int tx_dma_channel;
55 unsigned int rx_dma_channel;
56};
57
58struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS];
59
60struct bfin_sir_port_res {
61 unsigned long base_addr;
62 int irq;
63 unsigned int rx_dma_channel;
64 unsigned int tx_dma_channel;
65};
66
67struct bfin_sir_port_res bfin_sir_port_resource[] = {
68#ifdef CONFIG_BFIN_SIR0
69 {
70 0xFFC00400,
71 IRQ_UART0_RX,
72 CH_UART0_RX,
73 CH_UART0_TX,
74 },
75#endif
76#ifdef CONFIG_BFIN_SIR1
77 {
78 0xFFC02000,
79 IRQ_UART1_RX,
80 CH_UART1_RX,
81 CH_UART1_TX,
82 },
83#endif
84#ifdef CONFIG_BFIN_SIR2
85 {
86 0xFFC02100,
87 IRQ_UART2_RX,
88 CH_UART2_RX,
89 CH_UART2_TX,
90 },
91#endif
92#ifdef CONFIG_BFIN_SIR3
93 {
94 0xFFC03100,
95 IRQ_UART3_RX,
96 CH_UART3_RX,
97 CH_UART3_TX,
98 },
99#endif
100};
101
102int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource);
103
104struct bfin_sir_self {
105 struct bfin_sir_port *sir_port;
106 spinlock_t lock;
107 unsigned int open;
108 int speed;
109 int newspeed;
110
111 struct sk_buff *txskb;
112 struct sk_buff *rxskb;
113 struct net_device_stats stats;
114 struct device *dev;
115 struct irlap_cb *irlap;
116 struct qos_info qos;
117
118 iobuff_t tx_buff;
119 iobuff_t rx_buff;
120
121 struct work_struct work;
122 int mtt;
123};
124
125#define DRIVER_NAME "bfin_sir"
126
127static int bfin_sir_hw_init(void)
128{
129 int ret = -ENODEV;
130#ifdef CONFIG_BFIN_SIR0
131 ret = peripheral_request(P_UART0_TX, DRIVER_NAME);
132 if (ret)
133 return ret;
134 ret = peripheral_request(P_UART0_RX, DRIVER_NAME);
135 if (ret)
136 return ret;
137#endif
138
139#ifdef CONFIG_BFIN_SIR1
140 ret = peripheral_request(P_UART1_TX, DRIVER_NAME);
141 if (ret)
142 return ret;
143 ret = peripheral_request(P_UART1_RX, DRIVER_NAME);
144 if (ret)
145 return ret;
146#endif
147
148#ifdef CONFIG_BFIN_SIR2
149 ret = peripheral_request(P_UART2_TX, DRIVER_NAME);
150 if (ret)
151 return ret;
152 ret = peripheral_request(P_UART2_RX, DRIVER_NAME);
153 if (ret)
154 return ret;
155#endif
156
157#ifdef CONFIG_BFIN_SIR3
158 ret = peripheral_request(P_UART3_TX, DRIVER_NAME);
159 if (ret)
160 return ret;
161 ret = peripheral_request(P_UART3_RX, DRIVER_NAME);
162 if (ret)
163 return ret;
164#endif
165 return ret;
166}
diff --git a/arch/blackfin/mach-bf548/include/mach/blackfin.h b/arch/blackfin/mach-bf548/include/mach/blackfin.h
new file mode 100644
index 000000000000..d6ee74ac0460
--- /dev/null
+++ b/arch/blackfin/mach-bf548/include/mach/blackfin.h
@@ -0,0 +1,190 @@
1/*
2 * File: include/asm-blackfin/mach-bf548/blackfin.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#ifndef _MACH_BLACKFIN_H_
33#define _MACH_BLACKFIN_H_
34
35#define BF548_FAMILY
36
37#include "bf548.h"
38#include "mem_map.h"
39#include "anomaly.h"
40
41#ifdef CONFIG_BF542
42#include "defBF542.h"
43#endif
44
45#ifdef CONFIG_BF544
46#include "defBF544.h"
47#endif
48
49#ifdef CONFIG_BF547
50#include "defBF547.h"
51#endif
52
53#ifdef CONFIG_BF548
54#include "defBF548.h"
55#endif
56
57#ifdef CONFIG_BF549
58#include "defBF549.h"
59#endif
60
61#if !defined(__ASSEMBLY__)
62#ifdef CONFIG_BF542
63#include "cdefBF542.h"
64#endif
65#ifdef CONFIG_BF544
66#include "cdefBF544.h"
67#endif
68#ifdef CONFIG_BF547
69#include "cdefBF547.h"
70#endif
71#ifdef CONFIG_BF548
72#include "cdefBF548.h"
73#endif
74#ifdef CONFIG_BF549
75#include "cdefBF549.h"
76#endif
77
78/* UART 1*/
79#define bfin_read_UART_THR() bfin_read_UART1_THR()
80#define bfin_write_UART_THR(val) bfin_write_UART1_THR(val)
81#define bfin_read_UART_RBR() bfin_read_UART1_RBR()
82#define bfin_write_UART_RBR(val) bfin_write_UART1_RBR(val)
83#define bfin_read_UART_DLL() bfin_read_UART1_DLL()
84#define bfin_write_UART_DLL(val) bfin_write_UART1_DLL(val)
85#define bfin_read_UART_IER() bfin_read_UART1_IER()
86#define bfin_write_UART_IER(val) bfin_write_UART1_IER(val)
87#define bfin_read_UART_DLH() bfin_read_UART1_DLH()
88#define bfin_write_UART_DLH(val) bfin_write_UART1_DLH(val)
89#define bfin_read_UART_IIR() bfin_read_UART1_IIR()
90#define bfin_write_UART_IIR(val) bfin_write_UART1_IIR(val)
91#define bfin_read_UART_LCR() bfin_read_UART1_LCR()
92#define bfin_write_UART_LCR(val) bfin_write_UART1_LCR(val)
93#define bfin_read_UART_MCR() bfin_read_UART1_MCR()
94#define bfin_write_UART_MCR(val) bfin_write_UART1_MCR(val)
95#define bfin_read_UART_LSR() bfin_read_UART1_LSR()
96#define bfin_write_UART_LSR(val) bfin_write_UART1_LSR(val)
97#define bfin_read_UART_SCR() bfin_read_UART1_SCR()
98#define bfin_write_UART_SCR(val) bfin_write_UART1_SCR(val)
99#define bfin_read_UART_GCTL() bfin_read_UART1_GCTL()
100#define bfin_write_UART_GCTL(val) bfin_write_UART1_GCTL(val)
101
102#endif
103
104/* MAP used DEFINES from BF533 to BF54x - so we don't need to change
105 * them in the driver, kernel, etc. */
106
107/* UART_IIR Register */
108#define STATUS(x) ((x << 1) & 0x06)
109#define STATUS_P1 0x02
110#define STATUS_P0 0x01
111
112/* UART 0*/
113
114/* DMA Channnel */
115#define bfin_read_CH_UART_RX() bfin_read_CH_UART1_RX()
116#define bfin_write_CH_UART_RX(val) bfin_write_CH_UART1_RX(val)
117#define bfin_read_CH_UART_TX() bfin_read_CH_UART1_TX()
118#define bfin_write_CH_UART_TX(val) bfin_write_CH_UART1_TX(val)
119#define CH_UART_RX CH_UART1_RX
120#define CH_UART_TX CH_UART1_TX
121
122/* System Interrupt Controller */
123#define bfin_read_IRQ_UART_RX() bfin_read_IRQ_UART1_RX()
124#define bfin_write_IRQ_UART_RX(val) bfin_write_IRQ_UART1_RX(val)
125#define bfin_read_IRQ_UART_TX() bfin_read_IRQ_UART1_TX()
126#define bfin_write_IRQ_UART_TX(val) bfin_write_IRQ_UART1_TX(val)
127#define bfin_read_IRQ_UART_ERROR() bfin_read_IRQ_UART1_ERROR()
128#define bfin_write_IRQ_UART_ERROR(val) bfin_write_IRQ_UART1_ERROR(val)
129#define IRQ_UART_RX IRQ_UART1_RX
130#define IRQ_UART_TX IRQ_UART1_TX
131#define IRQ_UART_ERROR IRQ_UART1_ERROR
132
133/* MMR Registers*/
134#define bfin_read_UART_THR() bfin_read_UART1_THR()
135#define bfin_write_UART_THR(val) bfin_write_UART1_THR(val)
136#define bfin_read_UART_RBR() bfin_read_UART1_RBR()
137#define bfin_write_UART_RBR(val) bfin_write_UART1_RBR(val)
138#define bfin_read_UART_DLL() bfin_read_UART1_DLL()
139#define bfin_write_UART_DLL(val) bfin_write_UART1_DLL(val)
140#define bfin_read_UART_IER() bfin_read_UART1_IER()
141#define bfin_write_UART_IER(val) bfin_write_UART1_IER(val)
142#define bfin_read_UART_DLH() bfin_read_UART1_DLH()
143#define bfin_write_UART_DLH(val) bfin_write_UART1_DLH(val)
144#define bfin_read_UART_IIR() bfin_read_UART1_IIR()
145#define bfin_write_UART_IIR(val) bfin_write_UART1_IIR(val)
146#define bfin_read_UART_LCR() bfin_read_UART1_LCR()
147#define bfin_write_UART_LCR(val) bfin_write_UART1_LCR(val)
148#define bfin_read_UART_MCR() bfin_read_UART1_MCR()
149#define bfin_write_UART_MCR(val) bfin_write_UART1_MCR(val)
150#define bfin_read_UART_LSR() bfin_read_UART1_LSR()
151#define bfin_write_UART_LSR(val) bfin_write_UART1_LSR(val)
152#define bfin_read_UART_SCR() bfin_read_UART1_SCR()
153#define bfin_write_UART_SCR(val) bfin_write_UART1_SCR(val)
154#define bfin_read_UART_GCTL() bfin_read_UART1_GCTL()
155#define bfin_write_UART_GCTL(val) bfin_write_UART1_GCTL(val)
156
157#define BFIN_UART_THR UART1_THR
158#define BFIN_UART_RBR UART1_RBR
159#define BFIN_UART_DLL UART1_DLL
160#define BFIN_UART_IER UART1_IER
161#define BFIN_UART_DLH UART1_DLH
162#define BFIN_UART_IIR UART1_IIR
163#define BFIN_UART_LCR UART1_LCR
164#define BFIN_UART_MCR UART1_MCR
165#define BFIN_UART_LSR UART1_LSR
166#define BFIN_UART_SCR UART1_SCR
167#define BFIN_UART_GCTL UART1_GCTL
168
169#define BFIN_UART_NR_PORTS 4
170
171#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
172#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
173#define OFFSET_GCTL 0x08 /* Global Control Register */
174#define OFFSET_LCR 0x0C /* Line Control Register */
175#define OFFSET_MCR 0x10 /* Modem Control Register */
176#define OFFSET_LSR 0x14 /* Line Status Register */
177#define OFFSET_MSR 0x18 /* Modem Status Register */
178#define OFFSET_SCR 0x1C /* SCR Scratch Register */
179#define OFFSET_IER_SET 0x20 /* Set Interrupt Enable Register */
180#define OFFSET_IER_CLEAR 0x24 /* Clear Interrupt Enable Register */
181#define OFFSET_THR 0x28 /* Transmit Holding register */
182#define OFFSET_RBR 0x2C /* Receive Buffer register */
183
184/* PLL_DIV Masks */
185#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */
186#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */
187#define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */
188#define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */
189
190#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF542.h b/arch/blackfin/mach-bf548/include/mach/cdefBF542.h
new file mode 100644
index 000000000000..07aefb9ed79b
--- /dev/null
+++ b/arch/blackfin/mach-bf548/include/mach/cdefBF542.h
@@ -0,0 +1,590 @@
1/*
2 * File: include/asm-blackfin/mach-bf548/cdefBF542.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _CDEF_BF542_H
32#define _CDEF_BF542_H
33
34/* include all Core registers and bit definitions */
35#include "defBF542.h"
36
37/* include core sbfin_read_()ecific register pointer definitions */
38#include <asm/cdef_LPBlackfin.h>
39
40/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF542 */
41
42/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
43#include "cdefBF54x_base.h"
44
45/* The following are the #defines needed by ADSP-BF542 that are not in the common header */
46
47/* ATAPI Registers */
48
49#define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL)
50#define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val)
51#define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS)
52#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val)
53#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR)
54#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
55#define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF)
56#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
57#define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF)
58#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
59#define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK)
60#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
61#define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS)
62#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
63#define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN)
64#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
65#define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS)
66#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
67#define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE)
68#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
69#define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE)
70#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
71#define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT)
72#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
73#define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT)
74#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
75#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT)
76#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
77#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT)
78#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
79#define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0)
80#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
81#define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0)
82#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
83#define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1)
84#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
85#define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0)
86#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
87#define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1)
88#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
89#define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2)
90#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
91#define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0)
92#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
93#define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1)
94#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
95#define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2)
96#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
97#define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3)
98#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
99
100/* SDH Registers */
101
102#define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL)
103#define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val)
104#define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL)
105#define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val)
106#define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT)
107#define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val)
108#define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND)
109#define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val)
110#define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD)
111#define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val)
112#define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0)
113#define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val)
114#define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1)
115#define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val)
116#define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2)
117#define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val)
118#define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3)
119#define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val)
120#define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER)
121#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
122#define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH)
123#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val)
124#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL)
125#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val)
126#define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT)
127#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val)
128#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS)
129#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val)
130#define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR)
131#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val)
132#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0)
133#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val)
134#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1)
135#define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val)
136#define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT)
137#define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val)
138#define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO)
139#define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val)
140#define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS)
141#define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val)
142#define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK)
143#define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val)
144#define bfin_read_SDH_CFG() bfin_read16(SDH_CFG)
145#define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val)
146#define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN)
147#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
148#define bfin_read_SDH_PID0() bfin_read16(SDH_PID0)
149#define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val)
150#define bfin_read_SDH_PID1() bfin_read16(SDH_PID1)
151#define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val)
152#define bfin_read_SDH_PID2() bfin_read16(SDH_PID2)
153#define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val)
154#define bfin_read_SDH_PID3() bfin_read16(SDH_PID3)
155#define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val)
156#define bfin_read_SDH_PID4() bfin_read16(SDH_PID4)
157#define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val)
158#define bfin_read_SDH_PID5() bfin_read16(SDH_PID5)
159#define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val)
160#define bfin_read_SDH_PID6() bfin_read16(SDH_PID6)
161#define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val)
162#define bfin_read_SDH_PID7() bfin_read16(SDH_PID7)
163#define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val)
164
165/* USB Control Registers */
166
167#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
168#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
169#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
170#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
171#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
172#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
173#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
174#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
175#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
176#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
177#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
178#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
179#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
180#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
181#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
182#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
183#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
184#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
185#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
186#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
187#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
188#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
189#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
190#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
191#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
192#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
193
194/* USB Packet Control Registers */
195
196#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
197#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
198#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
199#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
200#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
201#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
202#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
203#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
204#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
205#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
206#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
207#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
208#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
209#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
210#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
211#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
212#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
213#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
214#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
215#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
216#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
217#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
218#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
219#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
220#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
221#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
222
223/* USB Endbfin_read_()oint FIFO Registers */
224
225#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
226#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
227#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
228#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
229#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
230#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
231#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
232#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
233#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
234#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
235#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
236#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
237#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
238#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
239#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
240#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
241
242/* USB OTG Control Registers */
243
244#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
245#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
246#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
247#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
248#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
249#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
250
251/* USB Phy Control Registers */
252
253#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
254#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
255#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
256#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
257#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
258#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
259#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
260#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
261#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
262#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
263
264/* (APHY_CNTRL is for ADI usage only) */
265
266#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
267#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
268
269/* (APHY_CALIB is for ADI usage only) */
270
271#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
272#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
273#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
274#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
275
276/* (PHY_TEST is for ADI usage only) */
277
278#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST)
279#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val)
280#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
281#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
282#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
283#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
284
285/* USB Endbfin_read_()oint 0 Control Registers */
286
287#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
288#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
289#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
290#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
291#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
292#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
293#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
294#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
295#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
296#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
297#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
298#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
299#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
300#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
301#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
302#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
303#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
304#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
305
306/* USB Endbfin_read_()oint 1 Control Registers */
307
308#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
309#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
310#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
311#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
312#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
313#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
314#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
315#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
316#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
317#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
318#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
319#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
320#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
321#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
322#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
323#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
324#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
325#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
326#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
327#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
328
329/* USB Endbfin_read_()oint 2 Control Registers */
330
331#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
332#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
333#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
334#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
335#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
336#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
337#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
338#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
339#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
340#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
341#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
342#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
343#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
344#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
345#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
346#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
347#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
348#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
349#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
350#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
351
352/* USB Endbfin_read_()oint 3 Control Registers */
353
354#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
355#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
356#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
357#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
358#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
359#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
360#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
361#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
362#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
363#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
364#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
365#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
366#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
367#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
368#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
369#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
370#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
371#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
372#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
373#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
374
375/* USB Endbfin_read_()oint 4 Control Registers */
376
377#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
378#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
379#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
380#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
381#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
382#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
383#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
384#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
385#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
386#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
387#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
388#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
389#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
390#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
391#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
392#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
393#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
394#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
395#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
396#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
397
398/* USB Endbfin_read_()oint 5 Control Registers */
399
400#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
401#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
402#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
403#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
404#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
405#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
406#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
407#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
408#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
409#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
410#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
411#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
412#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
413#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
414#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
415#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
416#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
417#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
418#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
419#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
420
421/* USB Endbfin_read_()oint 6 Control Registers */
422
423#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
424#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
425#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
426#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
427#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
428#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
429#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
430#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
431#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
432#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
433#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
434#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
435#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
436#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
437#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
438#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
439#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
440#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
441#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
442#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
443
444/* USB Endbfin_read_()oint 7 Control Registers */
445
446#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
447#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
448#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
449#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
450#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
451#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
452#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
453#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
454#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
455#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
456#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
457#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
458#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
459#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
460#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
461#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
462#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
463#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
464#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
465#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
466#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
467#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
468#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
469#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
470
471/* USB Channel 0 Config Registers */
472
473#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL)
474#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val)
475#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW)
476#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val)
477#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH)
478#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val)
479#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW)
480#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val)
481#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH)
482#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val)
483
484/* USB Channel 1 Config Registers */
485
486#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL)
487#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val)
488#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW)
489#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val)
490#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH)
491#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val)
492#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW)
493#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val)
494#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH)
495#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val)
496
497/* USB Channel 2 Config Registers */
498
499#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL)
500#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val)
501#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW)
502#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val)
503#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH)
504#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val)
505#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW)
506#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val)
507#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH)
508#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val)
509
510/* USB Channel 3 Config Registers */
511
512#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL)
513#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val)
514#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW)
515#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val)
516#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH)
517#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val)
518#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW)
519#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val)
520#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH)
521#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val)
522
523/* USB Channel 4 Config Registers */
524
525#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL)
526#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val)
527#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW)
528#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val)
529#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH)
530#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val)
531#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW)
532#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val)
533#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH)
534#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val)
535
536/* USB Channel 5 Config Registers */
537
538#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL)
539#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val)
540#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW)
541#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val)
542#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH)
543#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val)
544#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW)
545#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val)
546#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH)
547#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val)
548
549/* USB Channel 6 Config Registers */
550
551#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL)
552#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val)
553#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW)
554#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val)
555#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH)
556#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val)
557#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW)
558#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val)
559#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH)
560#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val)
561
562/* USB Channel 7 Config Registers */
563
564#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL)
565#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val)
566#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW)
567#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val)
568#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH)
569#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val)
570#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW)
571#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val)
572#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH)
573#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val)
574
575/* Keybfin_read_()ad Registers */
576
577#define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL)
578#define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val)
579#define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE)
580#define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val)
581#define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL)
582#define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val)
583#define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL)
584#define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val)
585#define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT)
586#define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val)
587#define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL)
588#define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val)
589
590#endif /* _CDEF_BF542_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF544.h b/arch/blackfin/mach-bf548/include/mach/cdefBF544.h
new file mode 100644
index 000000000000..431a69278991
--- /dev/null
+++ b/arch/blackfin/mach-bf548/include/mach/cdefBF544.h
@@ -0,0 +1,945 @@
1/*
2 * File: include/asm-blackfin/mach-bf548/cdefBF544.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _CDEF_BF544_H
32#define _CDEF_BF544_H
33
34/* include all Core registers and bit definitions */
35#include "defBF544.h"
36
37/* include core sbfin_read_()ecific register pointer definitions */
38#include <asm/cdef_LPBlackfin.h>
39
40/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF544 */
41
42/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
43#include "cdefBF54x_base.h"
44
45/* The following are the #defines needed by ADSP-BF544 that are not in the common header */
46
47/* Timer Registers */
48
49#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG)
50#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val)
51#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER)
52#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
53#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD)
54#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val)
55#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH)
56#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val)
57#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG)
58#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val)
59#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER)
60#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
61#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD)
62#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val)
63#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH)
64#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val)
65#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG)
66#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
67#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER)
68#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
69#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD)
70#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
71#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH)
72#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val)
73
74/* Timer Groubfin_read_() of 3 */
75
76#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1)
77#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val)
78#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1)
79#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
80#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1)
81#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val)
82
83/* EPPI0 Registers */
84
85#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS)
86#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val)
87#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT)
88#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val)
89#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY)
90#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val)
91#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT)
92#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val)
93#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY)
94#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val)
95#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME)
96#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val)
97#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE)
98#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val)
99#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV)
100#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val)
101#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL)
102#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val)
103#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL)
104#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
105#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL)
106#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
107#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB)
108#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
109#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF)
110#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
111#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP)
112#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val)
113
114/* Two Wire Interface Registers (TWI1) */
115
116/* CAN Controller 1 Config 1 Registers */
117
118#define bfin_read_CAN1_MC1() bfin_read16(CAN1_MC1)
119#define bfin_write_CAN1_MC1(val) bfin_write16(CAN1_MC1, val)
120#define bfin_read_CAN1_MD1() bfin_read16(CAN1_MD1)
121#define bfin_write_CAN1_MD1(val) bfin_write16(CAN1_MD1, val)
122#define bfin_read_CAN1_TRS1() bfin_read16(CAN1_TRS1)
123#define bfin_write_CAN1_TRS1(val) bfin_write16(CAN1_TRS1, val)
124#define bfin_read_CAN1_TRR1() bfin_read16(CAN1_TRR1)
125#define bfin_write_CAN1_TRR1(val) bfin_write16(CAN1_TRR1, val)
126#define bfin_read_CAN1_TA1() bfin_read16(CAN1_TA1)
127#define bfin_write_CAN1_TA1(val) bfin_write16(CAN1_TA1, val)
128#define bfin_read_CAN1_AA1() bfin_read16(CAN1_AA1)
129#define bfin_write_CAN1_AA1(val) bfin_write16(CAN1_AA1, val)
130#define bfin_read_CAN1_RMP1() bfin_read16(CAN1_RMP1)
131#define bfin_write_CAN1_RMP1(val) bfin_write16(CAN1_RMP1, val)
132#define bfin_read_CAN1_RML1() bfin_read16(CAN1_RML1)
133#define bfin_write_CAN1_RML1(val) bfin_write16(CAN1_RML1, val)
134#define bfin_read_CAN1_MBTIF1() bfin_read16(CAN1_MBTIF1)
135#define bfin_write_CAN1_MBTIF1(val) bfin_write16(CAN1_MBTIF1, val)
136#define bfin_read_CAN1_MBRIF1() bfin_read16(CAN1_MBRIF1)
137#define bfin_write_CAN1_MBRIF1(val) bfin_write16(CAN1_MBRIF1, val)
138#define bfin_read_CAN1_MBIM1() bfin_read16(CAN1_MBIM1)
139#define bfin_write_CAN1_MBIM1(val) bfin_write16(CAN1_MBIM1, val)
140#define bfin_read_CAN1_RFH1() bfin_read16(CAN1_RFH1)
141#define bfin_write_CAN1_RFH1(val) bfin_write16(CAN1_RFH1, val)
142#define bfin_read_CAN1_OPSS1() bfin_read16(CAN1_OPSS1)
143#define bfin_write_CAN1_OPSS1(val) bfin_write16(CAN1_OPSS1, val)
144
145/* CAN Controller 1 Config 2 Registers */
146
147#define bfin_read_CAN1_MC2() bfin_read16(CAN1_MC2)
148#define bfin_write_CAN1_MC2(val) bfin_write16(CAN1_MC2, val)
149#define bfin_read_CAN1_MD2() bfin_read16(CAN1_MD2)
150#define bfin_write_CAN1_MD2(val) bfin_write16(CAN1_MD2, val)
151#define bfin_read_CAN1_TRS2() bfin_read16(CAN1_TRS2)
152#define bfin_write_CAN1_TRS2(val) bfin_write16(CAN1_TRS2, val)
153#define bfin_read_CAN1_TRR2() bfin_read16(CAN1_TRR2)
154#define bfin_write_CAN1_TRR2(val) bfin_write16(CAN1_TRR2, val)
155#define bfin_read_CAN1_TA2() bfin_read16(CAN1_TA2)
156#define bfin_write_CAN1_TA2(val) bfin_write16(CAN1_TA2, val)
157#define bfin_read_CAN1_AA2() bfin_read16(CAN1_AA2)
158#define bfin_write_CAN1_AA2(val) bfin_write16(CAN1_AA2, val)
159#define bfin_read_CAN1_RMP2() bfin_read16(CAN1_RMP2)
160#define bfin_write_CAN1_RMP2(val) bfin_write16(CAN1_RMP2, val)
161#define bfin_read_CAN1_RML2() bfin_read16(CAN1_RML2)
162#define bfin_write_CAN1_RML2(val) bfin_write16(CAN1_RML2, val)
163#define bfin_read_CAN1_MBTIF2() bfin_read16(CAN1_MBTIF2)
164#define bfin_write_CAN1_MBTIF2(val) bfin_write16(CAN1_MBTIF2, val)
165#define bfin_read_CAN1_MBRIF2() bfin_read16(CAN1_MBRIF2)
166#define bfin_write_CAN1_MBRIF2(val) bfin_write16(CAN1_MBRIF2, val)
167#define bfin_read_CAN1_MBIM2() bfin_read16(CAN1_MBIM2)
168#define bfin_write_CAN1_MBIM2(val) bfin_write16(CAN1_MBIM2, val)
169#define bfin_read_CAN1_RFH2() bfin_read16(CAN1_RFH2)
170#define bfin_write_CAN1_RFH2(val) bfin_write16(CAN1_RFH2, val)
171#define bfin_read_CAN1_OPSS2() bfin_read16(CAN1_OPSS2)
172#define bfin_write_CAN1_OPSS2(val) bfin_write16(CAN1_OPSS2, val)
173
174/* CAN Controller 1 Clock/Interrubfin_read_()t/Counter Registers */
175
176#define bfin_read_CAN1_CLOCK() bfin_read16(CAN1_CLOCK)
177#define bfin_write_CAN1_CLOCK(val) bfin_write16(CAN1_CLOCK, val)
178#define bfin_read_CAN1_TIMING() bfin_read16(CAN1_TIMING)
179#define bfin_write_CAN1_TIMING(val) bfin_write16(CAN1_TIMING, val)
180#define bfin_read_CAN1_DEBUG() bfin_read16(CAN1_DEBUG)
181#define bfin_write_CAN1_DEBUG(val) bfin_write16(CAN1_DEBUG, val)
182#define bfin_read_CAN1_STATUS() bfin_read16(CAN1_STATUS)
183#define bfin_write_CAN1_STATUS(val) bfin_write16(CAN1_STATUS, val)
184#define bfin_read_CAN1_CEC() bfin_read16(CAN1_CEC)
185#define bfin_write_CAN1_CEC(val) bfin_write16(CAN1_CEC, val)
186#define bfin_read_CAN1_GIS() bfin_read16(CAN1_GIS)
187#define bfin_write_CAN1_GIS(val) bfin_write16(CAN1_GIS, val)
188#define bfin_read_CAN1_GIM() bfin_read16(CAN1_GIM)
189#define bfin_write_CAN1_GIM(val) bfin_write16(CAN1_GIM, val)
190#define bfin_read_CAN1_GIF() bfin_read16(CAN1_GIF)
191#define bfin_write_CAN1_GIF(val) bfin_write16(CAN1_GIF, val)
192#define bfin_read_CAN1_CONTROL() bfin_read16(CAN1_CONTROL)
193#define bfin_write_CAN1_CONTROL(val) bfin_write16(CAN1_CONTROL, val)
194#define bfin_read_CAN1_INTR() bfin_read16(CAN1_INTR)
195#define bfin_write_CAN1_INTR(val) bfin_write16(CAN1_INTR, val)
196#define bfin_read_CAN1_MBTD() bfin_read16(CAN1_MBTD)
197#define bfin_write_CAN1_MBTD(val) bfin_write16(CAN1_MBTD, val)
198#define bfin_read_CAN1_EWR() bfin_read16(CAN1_EWR)
199#define bfin_write_CAN1_EWR(val) bfin_write16(CAN1_EWR, val)
200#define bfin_read_CAN1_ESR() bfin_read16(CAN1_ESR)
201#define bfin_write_CAN1_ESR(val) bfin_write16(CAN1_ESR, val)
202#define bfin_read_CAN1_UCCNT() bfin_read16(CAN1_UCCNT)
203#define bfin_write_CAN1_UCCNT(val) bfin_write16(CAN1_UCCNT, val)
204#define bfin_read_CAN1_UCRC() bfin_read16(CAN1_UCRC)
205#define bfin_write_CAN1_UCRC(val) bfin_write16(CAN1_UCRC, val)
206#define bfin_read_CAN1_UCCNF() bfin_read16(CAN1_UCCNF)
207#define bfin_write_CAN1_UCCNF(val) bfin_write16(CAN1_UCCNF, val)
208
209/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
210
211#define bfin_read_CAN1_AM00L() bfin_read16(CAN1_AM00L)
212#define bfin_write_CAN1_AM00L(val) bfin_write16(CAN1_AM00L, val)
213#define bfin_read_CAN1_AM00H() bfin_read16(CAN1_AM00H)
214#define bfin_write_CAN1_AM00H(val) bfin_write16(CAN1_AM00H, val)
215#define bfin_read_CAN1_AM01L() bfin_read16(CAN1_AM01L)
216#define bfin_write_CAN1_AM01L(val) bfin_write16(CAN1_AM01L, val)
217#define bfin_read_CAN1_AM01H() bfin_read16(CAN1_AM01H)
218#define bfin_write_CAN1_AM01H(val) bfin_write16(CAN1_AM01H, val)
219#define bfin_read_CAN1_AM02L() bfin_read16(CAN1_AM02L)
220#define bfin_write_CAN1_AM02L(val) bfin_write16(CAN1_AM02L, val)
221#define bfin_read_CAN1_AM02H() bfin_read16(CAN1_AM02H)
222#define bfin_write_CAN1_AM02H(val) bfin_write16(CAN1_AM02H, val)
223#define bfin_read_CAN1_AM03L() bfin_read16(CAN1_AM03L)
224#define bfin_write_CAN1_AM03L(val) bfin_write16(CAN1_AM03L, val)
225#define bfin_read_CAN1_AM03H() bfin_read16(CAN1_AM03H)
226#define bfin_write_CAN1_AM03H(val) bfin_write16(CAN1_AM03H, val)
227#define bfin_read_CAN1_AM04L() bfin_read16(CAN1_AM04L)
228#define bfin_write_CAN1_AM04L(val) bfin_write16(CAN1_AM04L, val)
229#define bfin_read_CAN1_AM04H() bfin_read16(CAN1_AM04H)
230#define bfin_write_CAN1_AM04H(val) bfin_write16(CAN1_AM04H, val)
231#define bfin_read_CAN1_AM05L() bfin_read16(CAN1_AM05L)
232#define bfin_write_CAN1_AM05L(val) bfin_write16(CAN1_AM05L, val)
233#define bfin_read_CAN1_AM05H() bfin_read16(CAN1_AM05H)
234#define bfin_write_CAN1_AM05H(val) bfin_write16(CAN1_AM05H, val)
235#define bfin_read_CAN1_AM06L() bfin_read16(CAN1_AM06L)
236#define bfin_write_CAN1_AM06L(val) bfin_write16(CAN1_AM06L, val)
237#define bfin_read_CAN1_AM06H() bfin_read16(CAN1_AM06H)
238#define bfin_write_CAN1_AM06H(val) bfin_write16(CAN1_AM06H, val)
239#define bfin_read_CAN1_AM07L() bfin_read16(CAN1_AM07L)
240#define bfin_write_CAN1_AM07L(val) bfin_write16(CAN1_AM07L, val)
241#define bfin_read_CAN1_AM07H() bfin_read16(CAN1_AM07H)
242#define bfin_write_CAN1_AM07H(val) bfin_write16(CAN1_AM07H, val)
243#define bfin_read_CAN1_AM08L() bfin_read16(CAN1_AM08L)
244#define bfin_write_CAN1_AM08L(val) bfin_write16(CAN1_AM08L, val)
245#define bfin_read_CAN1_AM08H() bfin_read16(CAN1_AM08H)
246#define bfin_write_CAN1_AM08H(val) bfin_write16(CAN1_AM08H, val)
247#define bfin_read_CAN1_AM09L() bfin_read16(CAN1_AM09L)
248#define bfin_write_CAN1_AM09L(val) bfin_write16(CAN1_AM09L, val)
249#define bfin_read_CAN1_AM09H() bfin_read16(CAN1_AM09H)
250#define bfin_write_CAN1_AM09H(val) bfin_write16(CAN1_AM09H, val)
251#define bfin_read_CAN1_AM10L() bfin_read16(CAN1_AM10L)
252#define bfin_write_CAN1_AM10L(val) bfin_write16(CAN1_AM10L, val)
253#define bfin_read_CAN1_AM10H() bfin_read16(CAN1_AM10H)
254#define bfin_write_CAN1_AM10H(val) bfin_write16(CAN1_AM10H, val)
255#define bfin_read_CAN1_AM11L() bfin_read16(CAN1_AM11L)
256#define bfin_write_CAN1_AM11L(val) bfin_write16(CAN1_AM11L, val)
257#define bfin_read_CAN1_AM11H() bfin_read16(CAN1_AM11H)
258#define bfin_write_CAN1_AM11H(val) bfin_write16(CAN1_AM11H, val)
259#define bfin_read_CAN1_AM12L() bfin_read16(CAN1_AM12L)
260#define bfin_write_CAN1_AM12L(val) bfin_write16(CAN1_AM12L, val)
261#define bfin_read_CAN1_AM12H() bfin_read16(CAN1_AM12H)
262#define bfin_write_CAN1_AM12H(val) bfin_write16(CAN1_AM12H, val)
263#define bfin_read_CAN1_AM13L() bfin_read16(CAN1_AM13L)
264#define bfin_write_CAN1_AM13L(val) bfin_write16(CAN1_AM13L, val)
265#define bfin_read_CAN1_AM13H() bfin_read16(CAN1_AM13H)
266#define bfin_write_CAN1_AM13H(val) bfin_write16(CAN1_AM13H, val)
267#define bfin_read_CAN1_AM14L() bfin_read16(CAN1_AM14L)
268#define bfin_write_CAN1_AM14L(val) bfin_write16(CAN1_AM14L, val)
269#define bfin_read_CAN1_AM14H() bfin_read16(CAN1_AM14H)
270#define bfin_write_CAN1_AM14H(val) bfin_write16(CAN1_AM14H, val)
271#define bfin_read_CAN1_AM15L() bfin_read16(CAN1_AM15L)
272#define bfin_write_CAN1_AM15L(val) bfin_write16(CAN1_AM15L, val)
273#define bfin_read_CAN1_AM15H() bfin_read16(CAN1_AM15H)
274#define bfin_write_CAN1_AM15H(val) bfin_write16(CAN1_AM15H, val)
275
276/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
277
278#define bfin_read_CAN1_AM16L() bfin_read16(CAN1_AM16L)
279#define bfin_write_CAN1_AM16L(val) bfin_write16(CAN1_AM16L, val)
280#define bfin_read_CAN1_AM16H() bfin_read16(CAN1_AM16H)
281#define bfin_write_CAN1_AM16H(val) bfin_write16(CAN1_AM16H, val)
282#define bfin_read_CAN1_AM17L() bfin_read16(CAN1_AM17L)
283#define bfin_write_CAN1_AM17L(val) bfin_write16(CAN1_AM17L, val)
284#define bfin_read_CAN1_AM17H() bfin_read16(CAN1_AM17H)
285#define bfin_write_CAN1_AM17H(val) bfin_write16(CAN1_AM17H, val)
286#define bfin_read_CAN1_AM18L() bfin_read16(CAN1_AM18L)
287#define bfin_write_CAN1_AM18L(val) bfin_write16(CAN1_AM18L, val)
288#define bfin_read_CAN1_AM18H() bfin_read16(CAN1_AM18H)
289#define bfin_write_CAN1_AM18H(val) bfin_write16(CAN1_AM18H, val)
290#define bfin_read_CAN1_AM19L() bfin_read16(CAN1_AM19L)
291#define bfin_write_CAN1_AM19L(val) bfin_write16(CAN1_AM19L, val)
292#define bfin_read_CAN1_AM19H() bfin_read16(CAN1_AM19H)
293#define bfin_write_CAN1_AM19H(val) bfin_write16(CAN1_AM19H, val)
294#define bfin_read_CAN1_AM20L() bfin_read16(CAN1_AM20L)
295#define bfin_write_CAN1_AM20L(val) bfin_write16(CAN1_AM20L, val)
296#define bfin_read_CAN1_AM20H() bfin_read16(CAN1_AM20H)
297#define bfin_write_CAN1_AM20H(val) bfin_write16(CAN1_AM20H, val)
298#define bfin_read_CAN1_AM21L() bfin_read16(CAN1_AM21L)
299#define bfin_write_CAN1_AM21L(val) bfin_write16(CAN1_AM21L, val)
300#define bfin_read_CAN1_AM21H() bfin_read16(CAN1_AM21H)
301#define bfin_write_CAN1_AM21H(val) bfin_write16(CAN1_AM21H, val)
302#define bfin_read_CAN1_AM22L() bfin_read16(CAN1_AM22L)
303#define bfin_write_CAN1_AM22L(val) bfin_write16(CAN1_AM22L, val)
304#define bfin_read_CAN1_AM22H() bfin_read16(CAN1_AM22H)
305#define bfin_write_CAN1_AM22H(val) bfin_write16(CAN1_AM22H, val)
306#define bfin_read_CAN1_AM23L() bfin_read16(CAN1_AM23L)
307#define bfin_write_CAN1_AM23L(val) bfin_write16(CAN1_AM23L, val)
308#define bfin_read_CAN1_AM23H() bfin_read16(CAN1_AM23H)
309#define bfin_write_CAN1_AM23H(val) bfin_write16(CAN1_AM23H, val)
310#define bfin_read_CAN1_AM24L() bfin_read16(CAN1_AM24L)
311#define bfin_write_CAN1_AM24L(val) bfin_write16(CAN1_AM24L, val)
312#define bfin_read_CAN1_AM24H() bfin_read16(CAN1_AM24H)
313#define bfin_write_CAN1_AM24H(val) bfin_write16(CAN1_AM24H, val)
314#define bfin_read_CAN1_AM25L() bfin_read16(CAN1_AM25L)
315#define bfin_write_CAN1_AM25L(val) bfin_write16(CAN1_AM25L, val)
316#define bfin_read_CAN1_AM25H() bfin_read16(CAN1_AM25H)
317#define bfin_write_CAN1_AM25H(val) bfin_write16(CAN1_AM25H, val)
318#define bfin_read_CAN1_AM26L() bfin_read16(CAN1_AM26L)
319#define bfin_write_CAN1_AM26L(val) bfin_write16(CAN1_AM26L, val)
320#define bfin_read_CAN1_AM26H() bfin_read16(CAN1_AM26H)
321#define bfin_write_CAN1_AM26H(val) bfin_write16(CAN1_AM26H, val)
322#define bfin_read_CAN1_AM27L() bfin_read16(CAN1_AM27L)
323#define bfin_write_CAN1_AM27L(val) bfin_write16(CAN1_AM27L, val)
324#define bfin_read_CAN1_AM27H() bfin_read16(CAN1_AM27H)
325#define bfin_write_CAN1_AM27H(val) bfin_write16(CAN1_AM27H, val)
326#define bfin_read_CAN1_AM28L() bfin_read16(CAN1_AM28L)
327#define bfin_write_CAN1_AM28L(val) bfin_write16(CAN1_AM28L, val)
328#define bfin_read_CAN1_AM28H() bfin_read16(CAN1_AM28H)
329#define bfin_write_CAN1_AM28H(val) bfin_write16(CAN1_AM28H, val)
330#define bfin_read_CAN1_AM29L() bfin_read16(CAN1_AM29L)
331#define bfin_write_CAN1_AM29L(val) bfin_write16(CAN1_AM29L, val)
332#define bfin_read_CAN1_AM29H() bfin_read16(CAN1_AM29H)
333#define bfin_write_CAN1_AM29H(val) bfin_write16(CAN1_AM29H, val)
334#define bfin_read_CAN1_AM30L() bfin_read16(CAN1_AM30L)
335#define bfin_write_CAN1_AM30L(val) bfin_write16(CAN1_AM30L, val)
336#define bfin_read_CAN1_AM30H() bfin_read16(CAN1_AM30H)
337#define bfin_write_CAN1_AM30H(val) bfin_write16(CAN1_AM30H, val)
338#define bfin_read_CAN1_AM31L() bfin_read16(CAN1_AM31L)
339#define bfin_write_CAN1_AM31L(val) bfin_write16(CAN1_AM31L, val)
340#define bfin_read_CAN1_AM31H() bfin_read16(CAN1_AM31H)
341#define bfin_write_CAN1_AM31H(val) bfin_write16(CAN1_AM31H, val)
342
343/* CAN Controller 1 Mailbox Data Registers */
344
345#define bfin_read_CAN1_MB00_DATA0() bfin_read16(CAN1_MB00_DATA0)
346#define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val)
347#define bfin_read_CAN1_MB00_DATA1() bfin_read16(CAN1_MB00_DATA1)
348#define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val)
349#define bfin_read_CAN1_MB00_DATA2() bfin_read16(CAN1_MB00_DATA2)
350#define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val)
351#define bfin_read_CAN1_MB00_DATA3() bfin_read16(CAN1_MB00_DATA3)
352#define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val)
353#define bfin_read_CAN1_MB00_LENGTH() bfin_read16(CAN1_MB00_LENGTH)
354#define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val)
355#define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP)
356#define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val)
357#define bfin_read_CAN1_MB00_ID0() bfin_read16(CAN1_MB00_ID0)
358#define bfin_write_CAN1_MB00_ID0(val) bfin_write16(CAN1_MB00_ID0, val)
359#define bfin_read_CAN1_MB00_ID1() bfin_read16(CAN1_MB00_ID1)
360#define bfin_write_CAN1_MB00_ID1(val) bfin_write16(CAN1_MB00_ID1, val)
361#define bfin_read_CAN1_MB01_DATA0() bfin_read16(CAN1_MB01_DATA0)
362#define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val)
363#define bfin_read_CAN1_MB01_DATA1() bfin_read16(CAN1_MB01_DATA1)
364#define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val)
365#define bfin_read_CAN1_MB01_DATA2() bfin_read16(CAN1_MB01_DATA2)
366#define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val)
367#define bfin_read_CAN1_MB01_DATA3() bfin_read16(CAN1_MB01_DATA3)
368#define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val)
369#define bfin_read_CAN1_MB01_LENGTH() bfin_read16(CAN1_MB01_LENGTH)
370#define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val)
371#define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP)
372#define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val)
373#define bfin_read_CAN1_MB01_ID0() bfin_read16(CAN1_MB01_ID0)
374#define bfin_write_CAN1_MB01_ID0(val) bfin_write16(CAN1_MB01_ID0, val)
375#define bfin_read_CAN1_MB01_ID1() bfin_read16(CAN1_MB01_ID1)
376#define bfin_write_CAN1_MB01_ID1(val) bfin_write16(CAN1_MB01_ID1, val)
377#define bfin_read_CAN1_MB02_DATA0() bfin_read16(CAN1_MB02_DATA0)
378#define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val)
379#define bfin_read_CAN1_MB02_DATA1() bfin_read16(CAN1_MB02_DATA1)
380#define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val)
381#define bfin_read_CAN1_MB02_DATA2() bfin_read16(CAN1_MB02_DATA2)
382#define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val)
383#define bfin_read_CAN1_MB02_DATA3() bfin_read16(CAN1_MB02_DATA3)
384#define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val)
385#define bfin_read_CAN1_MB02_LENGTH() bfin_read16(CAN1_MB02_LENGTH)
386#define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val)
387#define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP)
388#define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val)
389#define bfin_read_CAN1_MB02_ID0() bfin_read16(CAN1_MB02_ID0)
390#define bfin_write_CAN1_MB02_ID0(val) bfin_write16(CAN1_MB02_ID0, val)
391#define bfin_read_CAN1_MB02_ID1() bfin_read16(CAN1_MB02_ID1)
392#define bfin_write_CAN1_MB02_ID1(val) bfin_write16(CAN1_MB02_ID1, val)
393#define bfin_read_CAN1_MB03_DATA0() bfin_read16(CAN1_MB03_DATA0)
394#define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val)
395#define bfin_read_CAN1_MB03_DATA1() bfin_read16(CAN1_MB03_DATA1)
396#define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val)
397#define bfin_read_CAN1_MB03_DATA2() bfin_read16(CAN1_MB03_DATA2)
398#define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val)
399#define bfin_read_CAN1_MB03_DATA3() bfin_read16(CAN1_MB03_DATA3)
400#define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val)
401#define bfin_read_CAN1_MB03_LENGTH() bfin_read16(CAN1_MB03_LENGTH)
402#define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val)
403#define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP)
404#define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val)
405#define bfin_read_CAN1_MB03_ID0() bfin_read16(CAN1_MB03_ID0)
406#define bfin_write_CAN1_MB03_ID0(val) bfin_write16(CAN1_MB03_ID0, val)
407#define bfin_read_CAN1_MB03_ID1() bfin_read16(CAN1_MB03_ID1)
408#define bfin_write_CAN1_MB03_ID1(val) bfin_write16(CAN1_MB03_ID1, val)
409#define bfin_read_CAN1_MB04_DATA0() bfin_read16(CAN1_MB04_DATA0)
410#define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val)
411#define bfin_read_CAN1_MB04_DATA1() bfin_read16(CAN1_MB04_DATA1)
412#define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val)
413#define bfin_read_CAN1_MB04_DATA2() bfin_read16(CAN1_MB04_DATA2)
414#define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val)
415#define bfin_read_CAN1_MB04_DATA3() bfin_read16(CAN1_MB04_DATA3)
416#define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val)
417#define bfin_read_CAN1_MB04_LENGTH() bfin_read16(CAN1_MB04_LENGTH)
418#define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val)
419#define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP)
420#define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val)
421#define bfin_read_CAN1_MB04_ID0() bfin_read16(CAN1_MB04_ID0)
422#define bfin_write_CAN1_MB04_ID0(val) bfin_write16(CAN1_MB04_ID0, val)
423#define bfin_read_CAN1_MB04_ID1() bfin_read16(CAN1_MB04_ID1)
424#define bfin_write_CAN1_MB04_ID1(val) bfin_write16(CAN1_MB04_ID1, val)
425#define bfin_read_CAN1_MB05_DATA0() bfin_read16(CAN1_MB05_DATA0)
426#define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val)
427#define bfin_read_CAN1_MB05_DATA1() bfin_read16(CAN1_MB05_DATA1)
428#define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val)
429#define bfin_read_CAN1_MB05_DATA2() bfin_read16(CAN1_MB05_DATA2)
430#define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val)
431#define bfin_read_CAN1_MB05_DATA3() bfin_read16(CAN1_MB05_DATA3)
432#define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val)
433#define bfin_read_CAN1_MB05_LENGTH() bfin_read16(CAN1_MB05_LENGTH)
434#define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val)
435#define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP)
436#define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val)
437#define bfin_read_CAN1_MB05_ID0() bfin_read16(CAN1_MB05_ID0)
438#define bfin_write_CAN1_MB05_ID0(val) bfin_write16(CAN1_MB05_ID0, val)
439#define bfin_read_CAN1_MB05_ID1() bfin_read16(CAN1_MB05_ID1)
440#define bfin_write_CAN1_MB05_ID1(val) bfin_write16(CAN1_MB05_ID1, val)
441#define bfin_read_CAN1_MB06_DATA0() bfin_read16(CAN1_MB06_DATA0)
442#define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val)
443#define bfin_read_CAN1_MB06_DATA1() bfin_read16(CAN1_MB06_DATA1)
444#define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val)
445#define bfin_read_CAN1_MB06_DATA2() bfin_read16(CAN1_MB06_DATA2)
446#define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val)
447#define bfin_read_CAN1_MB06_DATA3() bfin_read16(CAN1_MB06_DATA3)
448#define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val)
449#define bfin_read_CAN1_MB06_LENGTH() bfin_read16(CAN1_MB06_LENGTH)
450#define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val)
451#define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP)
452#define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val)
453#define bfin_read_CAN1_MB06_ID0() bfin_read16(CAN1_MB06_ID0)
454#define bfin_write_CAN1_MB06_ID0(val) bfin_write16(CAN1_MB06_ID0, val)
455#define bfin_read_CAN1_MB06_ID1() bfin_read16(CAN1_MB06_ID1)
456#define bfin_write_CAN1_MB06_ID1(val) bfin_write16(CAN1_MB06_ID1, val)
457#define bfin_read_CAN1_MB07_DATA0() bfin_read16(CAN1_MB07_DATA0)
458#define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val)
459#define bfin_read_CAN1_MB07_DATA1() bfin_read16(CAN1_MB07_DATA1)
460#define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val)
461#define bfin_read_CAN1_MB07_DATA2() bfin_read16(CAN1_MB07_DATA2)
462#define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val)
463#define bfin_read_CAN1_MB07_DATA3() bfin_read16(CAN1_MB07_DATA3)
464#define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val)
465#define bfin_read_CAN1_MB07_LENGTH() bfin_read16(CAN1_MB07_LENGTH)
466#define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val)
467#define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP)
468#define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val)
469#define bfin_read_CAN1_MB07_ID0() bfin_read16(CAN1_MB07_ID0)
470#define bfin_write_CAN1_MB07_ID0(val) bfin_write16(CAN1_MB07_ID0, val)
471#define bfin_read_CAN1_MB07_ID1() bfin_read16(CAN1_MB07_ID1)
472#define bfin_write_CAN1_MB07_ID1(val) bfin_write16(CAN1_MB07_ID1, val)
473#define bfin_read_CAN1_MB08_DATA0() bfin_read16(CAN1_MB08_DATA0)
474#define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val)
475#define bfin_read_CAN1_MB08_DATA1() bfin_read16(CAN1_MB08_DATA1)
476#define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val)
477#define bfin_read_CAN1_MB08_DATA2() bfin_read16(CAN1_MB08_DATA2)
478#define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val)
479#define bfin_read_CAN1_MB08_DATA3() bfin_read16(CAN1_MB08_DATA3)
480#define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val)
481#define bfin_read_CAN1_MB08_LENGTH() bfin_read16(CAN1_MB08_LENGTH)
482#define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val)
483#define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP)
484#define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val)
485#define bfin_read_CAN1_MB08_ID0() bfin_read16(CAN1_MB08_ID0)
486#define bfin_write_CAN1_MB08_ID0(val) bfin_write16(CAN1_MB08_ID0, val)
487#define bfin_read_CAN1_MB08_ID1() bfin_read16(CAN1_MB08_ID1)
488#define bfin_write_CAN1_MB08_ID1(val) bfin_write16(CAN1_MB08_ID1, val)
489#define bfin_read_CAN1_MB09_DATA0() bfin_read16(CAN1_MB09_DATA0)
490#define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val)
491#define bfin_read_CAN1_MB09_DATA1() bfin_read16(CAN1_MB09_DATA1)
492#define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val)
493#define bfin_read_CAN1_MB09_DATA2() bfin_read16(CAN1_MB09_DATA2)
494#define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val)
495#define bfin_read_CAN1_MB09_DATA3() bfin_read16(CAN1_MB09_DATA3)
496#define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val)
497#define bfin_read_CAN1_MB09_LENGTH() bfin_read16(CAN1_MB09_LENGTH)
498#define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val)
499#define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP)
500#define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val)
501#define bfin_read_CAN1_MB09_ID0() bfin_read16(CAN1_MB09_ID0)
502#define bfin_write_CAN1_MB09_ID0(val) bfin_write16(CAN1_MB09_ID0, val)
503#define bfin_read_CAN1_MB09_ID1() bfin_read16(CAN1_MB09_ID1)
504#define bfin_write_CAN1_MB09_ID1(val) bfin_write16(CAN1_MB09_ID1, val)
505#define bfin_read_CAN1_MB10_DATA0() bfin_read16(CAN1_MB10_DATA0)
506#define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val)
507#define bfin_read_CAN1_MB10_DATA1() bfin_read16(CAN1_MB10_DATA1)
508#define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val)
509#define bfin_read_CAN1_MB10_DATA2() bfin_read16(CAN1_MB10_DATA2)
510#define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val)
511#define bfin_read_CAN1_MB10_DATA3() bfin_read16(CAN1_MB10_DATA3)
512#define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val)
513#define bfin_read_CAN1_MB10_LENGTH() bfin_read16(CAN1_MB10_LENGTH)
514#define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val)
515#define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP)
516#define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val)
517#define bfin_read_CAN1_MB10_ID0() bfin_read16(CAN1_MB10_ID0)
518#define bfin_write_CAN1_MB10_ID0(val) bfin_write16(CAN1_MB10_ID0, val)
519#define bfin_read_CAN1_MB10_ID1() bfin_read16(CAN1_MB10_ID1)
520#define bfin_write_CAN1_MB10_ID1(val) bfin_write16(CAN1_MB10_ID1, val)
521#define bfin_read_CAN1_MB11_DATA0() bfin_read16(CAN1_MB11_DATA0)
522#define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val)
523#define bfin_read_CAN1_MB11_DATA1() bfin_read16(CAN1_MB11_DATA1)
524#define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val)
525#define bfin_read_CAN1_MB11_DATA2() bfin_read16(CAN1_MB11_DATA2)
526#define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val)
527#define bfin_read_CAN1_MB11_DATA3() bfin_read16(CAN1_MB11_DATA3)
528#define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val)
529#define bfin_read_CAN1_MB11_LENGTH() bfin_read16(CAN1_MB11_LENGTH)
530#define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val)
531#define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP)
532#define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val)
533#define bfin_read_CAN1_MB11_ID0() bfin_read16(CAN1_MB11_ID0)
534#define bfin_write_CAN1_MB11_ID0(val) bfin_write16(CAN1_MB11_ID0, val)
535#define bfin_read_CAN1_MB11_ID1() bfin_read16(CAN1_MB11_ID1)
536#define bfin_write_CAN1_MB11_ID1(val) bfin_write16(CAN1_MB11_ID1, val)
537#define bfin_read_CAN1_MB12_DATA0() bfin_read16(CAN1_MB12_DATA0)
538#define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val)
539#define bfin_read_CAN1_MB12_DATA1() bfin_read16(CAN1_MB12_DATA1)
540#define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val)
541#define bfin_read_CAN1_MB12_DATA2() bfin_read16(CAN1_MB12_DATA2)
542#define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val)
543#define bfin_read_CAN1_MB12_DATA3() bfin_read16(CAN1_MB12_DATA3)
544#define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val)
545#define bfin_read_CAN1_MB12_LENGTH() bfin_read16(CAN1_MB12_LENGTH)
546#define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val)
547#define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP)
548#define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val)
549#define bfin_read_CAN1_MB12_ID0() bfin_read16(CAN1_MB12_ID0)
550#define bfin_write_CAN1_MB12_ID0(val) bfin_write16(CAN1_MB12_ID0, val)
551#define bfin_read_CAN1_MB12_ID1() bfin_read16(CAN1_MB12_ID1)
552#define bfin_write_CAN1_MB12_ID1(val) bfin_write16(CAN1_MB12_ID1, val)
553#define bfin_read_CAN1_MB13_DATA0() bfin_read16(CAN1_MB13_DATA0)
554#define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val)
555#define bfin_read_CAN1_MB13_DATA1() bfin_read16(CAN1_MB13_DATA1)
556#define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val)
557#define bfin_read_CAN1_MB13_DATA2() bfin_read16(CAN1_MB13_DATA2)
558#define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val)
559#define bfin_read_CAN1_MB13_DATA3() bfin_read16(CAN1_MB13_DATA3)
560#define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val)
561#define bfin_read_CAN1_MB13_LENGTH() bfin_read16(CAN1_MB13_LENGTH)
562#define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val)
563#define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP)
564#define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val)
565#define bfin_read_CAN1_MB13_ID0() bfin_read16(CAN1_MB13_ID0)
566#define bfin_write_CAN1_MB13_ID0(val) bfin_write16(CAN1_MB13_ID0, val)
567#define bfin_read_CAN1_MB13_ID1() bfin_read16(CAN1_MB13_ID1)
568#define bfin_write_CAN1_MB13_ID1(val) bfin_write16(CAN1_MB13_ID1, val)
569#define bfin_read_CAN1_MB14_DATA0() bfin_read16(CAN1_MB14_DATA0)
570#define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val)
571#define bfin_read_CAN1_MB14_DATA1() bfin_read16(CAN1_MB14_DATA1)
572#define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val)
573#define bfin_read_CAN1_MB14_DATA2() bfin_read16(CAN1_MB14_DATA2)
574#define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val)
575#define bfin_read_CAN1_MB14_DATA3() bfin_read16(CAN1_MB14_DATA3)
576#define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val)
577#define bfin_read_CAN1_MB14_LENGTH() bfin_read16(CAN1_MB14_LENGTH)
578#define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val)
579#define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP)
580#define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val)
581#define bfin_read_CAN1_MB14_ID0() bfin_read16(CAN1_MB14_ID0)
582#define bfin_write_CAN1_MB14_ID0(val) bfin_write16(CAN1_MB14_ID0, val)
583#define bfin_read_CAN1_MB14_ID1() bfin_read16(CAN1_MB14_ID1)
584#define bfin_write_CAN1_MB14_ID1(val) bfin_write16(CAN1_MB14_ID1, val)
585#define bfin_read_CAN1_MB15_DATA0() bfin_read16(CAN1_MB15_DATA0)
586#define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val)
587#define bfin_read_CAN1_MB15_DATA1() bfin_read16(CAN1_MB15_DATA1)
588#define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val)
589#define bfin_read_CAN1_MB15_DATA2() bfin_read16(CAN1_MB15_DATA2)
590#define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val)
591#define bfin_read_CAN1_MB15_DATA3() bfin_read16(CAN1_MB15_DATA3)
592#define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val)
593#define bfin_read_CAN1_MB15_LENGTH() bfin_read16(CAN1_MB15_LENGTH)
594#define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val)
595#define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP)
596#define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val)
597#define bfin_read_CAN1_MB15_ID0() bfin_read16(CAN1_MB15_ID0)
598#define bfin_write_CAN1_MB15_ID0(val) bfin_write16(CAN1_MB15_ID0, val)
599#define bfin_read_CAN1_MB15_ID1() bfin_read16(CAN1_MB15_ID1)
600#define bfin_write_CAN1_MB15_ID1(val) bfin_write16(CAN1_MB15_ID1, val)
601
602/* CAN Controller 1 Mailbox Data Registers */
603
604#define bfin_read_CAN1_MB16_DATA0() bfin_read16(CAN1_MB16_DATA0)
605#define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val)
606#define bfin_read_CAN1_MB16_DATA1() bfin_read16(CAN1_MB16_DATA1)
607#define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val)
608#define bfin_read_CAN1_MB16_DATA2() bfin_read16(CAN1_MB16_DATA2)
609#define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val)
610#define bfin_read_CAN1_MB16_DATA3() bfin_read16(CAN1_MB16_DATA3)
611#define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val)
612#define bfin_read_CAN1_MB16_LENGTH() bfin_read16(CAN1_MB16_LENGTH)
613#define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val)
614#define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP)
615#define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val)
616#define bfin_read_CAN1_MB16_ID0() bfin_read16(CAN1_MB16_ID0)
617#define bfin_write_CAN1_MB16_ID0(val) bfin_write16(CAN1_MB16_ID0, val)
618#define bfin_read_CAN1_MB16_ID1() bfin_read16(CAN1_MB16_ID1)
619#define bfin_write_CAN1_MB16_ID1(val) bfin_write16(CAN1_MB16_ID1, val)
620#define bfin_read_CAN1_MB17_DATA0() bfin_read16(CAN1_MB17_DATA0)
621#define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val)
622#define bfin_read_CAN1_MB17_DATA1() bfin_read16(CAN1_MB17_DATA1)
623#define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val)
624#define bfin_read_CAN1_MB17_DATA2() bfin_read16(CAN1_MB17_DATA2)
625#define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val)
626#define bfin_read_CAN1_MB17_DATA3() bfin_read16(CAN1_MB17_DATA3)
627#define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val)
628#define bfin_read_CAN1_MB17_LENGTH() bfin_read16(CAN1_MB17_LENGTH)
629#define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val)
630#define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP)
631#define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val)
632#define bfin_read_CAN1_MB17_ID0() bfin_read16(CAN1_MB17_ID0)
633#define bfin_write_CAN1_MB17_ID0(val) bfin_write16(CAN1_MB17_ID0, val)
634#define bfin_read_CAN1_MB17_ID1() bfin_read16(CAN1_MB17_ID1)
635#define bfin_write_CAN1_MB17_ID1(val) bfin_write16(CAN1_MB17_ID1, val)
636#define bfin_read_CAN1_MB18_DATA0() bfin_read16(CAN1_MB18_DATA0)
637#define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val)
638#define bfin_read_CAN1_MB18_DATA1() bfin_read16(CAN1_MB18_DATA1)
639#define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val)
640#define bfin_read_CAN1_MB18_DATA2() bfin_read16(CAN1_MB18_DATA2)
641#define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val)
642#define bfin_read_CAN1_MB18_DATA3() bfin_read16(CAN1_MB18_DATA3)
643#define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val)
644#define bfin_read_CAN1_MB18_LENGTH() bfin_read16(CAN1_MB18_LENGTH)
645#define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val)
646#define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP)
647#define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val)
648#define bfin_read_CAN1_MB18_ID0() bfin_read16(CAN1_MB18_ID0)
649#define bfin_write_CAN1_MB18_ID0(val) bfin_write16(CAN1_MB18_ID0, val)
650#define bfin_read_CAN1_MB18_ID1() bfin_read16(CAN1_MB18_ID1)
651#define bfin_write_CAN1_MB18_ID1(val) bfin_write16(CAN1_MB18_ID1, val)
652#define bfin_read_CAN1_MB19_DATA0() bfin_read16(CAN1_MB19_DATA0)
653#define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val)
654#define bfin_read_CAN1_MB19_DATA1() bfin_read16(CAN1_MB19_DATA1)
655#define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val)
656#define bfin_read_CAN1_MB19_DATA2() bfin_read16(CAN1_MB19_DATA2)
657#define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val)
658#define bfin_read_CAN1_MB19_DATA3() bfin_read16(CAN1_MB19_DATA3)
659#define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val)
660#define bfin_read_CAN1_MB19_LENGTH() bfin_read16(CAN1_MB19_LENGTH)
661#define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val)
662#define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP)
663#define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val)
664#define bfin_read_CAN1_MB19_ID0() bfin_read16(CAN1_MB19_ID0)
665#define bfin_write_CAN1_MB19_ID0(val) bfin_write16(CAN1_MB19_ID0, val)
666#define bfin_read_CAN1_MB19_ID1() bfin_read16(CAN1_MB19_ID1)
667#define bfin_write_CAN1_MB19_ID1(val) bfin_write16(CAN1_MB19_ID1, val)
668#define bfin_read_CAN1_MB20_DATA0() bfin_read16(CAN1_MB20_DATA0)
669#define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val)
670#define bfin_read_CAN1_MB20_DATA1() bfin_read16(CAN1_MB20_DATA1)
671#define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val)
672#define bfin_read_CAN1_MB20_DATA2() bfin_read16(CAN1_MB20_DATA2)
673#define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val)
674#define bfin_read_CAN1_MB20_DATA3() bfin_read16(CAN1_MB20_DATA3)
675#define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val)
676#define bfin_read_CAN1_MB20_LENGTH() bfin_read16(CAN1_MB20_LENGTH)
677#define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val)
678#define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP)
679#define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val)
680#define bfin_read_CAN1_MB20_ID0() bfin_read16(CAN1_MB20_ID0)
681#define bfin_write_CAN1_MB20_ID0(val) bfin_write16(CAN1_MB20_ID0, val)
682#define bfin_read_CAN1_MB20_ID1() bfin_read16(CAN1_MB20_ID1)
683#define bfin_write_CAN1_MB20_ID1(val) bfin_write16(CAN1_MB20_ID1, val)
684#define bfin_read_CAN1_MB21_DATA0() bfin_read16(CAN1_MB21_DATA0)
685#define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val)
686#define bfin_read_CAN1_MB21_DATA1() bfin_read16(CAN1_MB21_DATA1)
687#define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val)
688#define bfin_read_CAN1_MB21_DATA2() bfin_read16(CAN1_MB21_DATA2)
689#define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val)
690#define bfin_read_CAN1_MB21_DATA3() bfin_read16(CAN1_MB21_DATA3)
691#define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val)
692#define bfin_read_CAN1_MB21_LENGTH() bfin_read16(CAN1_MB21_LENGTH)
693#define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val)
694#define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP)
695#define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val)
696#define bfin_read_CAN1_MB21_ID0() bfin_read16(CAN1_MB21_ID0)
697#define bfin_write_CAN1_MB21_ID0(val) bfin_write16(CAN1_MB21_ID0, val)
698#define bfin_read_CAN1_MB21_ID1() bfin_read16(CAN1_MB21_ID1)
699#define bfin_write_CAN1_MB21_ID1(val) bfin_write16(CAN1_MB21_ID1, val)
700#define bfin_read_CAN1_MB22_DATA0() bfin_read16(CAN1_MB22_DATA0)
701#define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val)
702#define bfin_read_CAN1_MB22_DATA1() bfin_read16(CAN1_MB22_DATA1)
703#define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val)
704#define bfin_read_CAN1_MB22_DATA2() bfin_read16(CAN1_MB22_DATA2)
705#define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val)
706#define bfin_read_CAN1_MB22_DATA3() bfin_read16(CAN1_MB22_DATA3)
707#define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val)
708#define bfin_read_CAN1_MB22_LENGTH() bfin_read16(CAN1_MB22_LENGTH)
709#define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val)
710#define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP)
711#define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val)
712#define bfin_read_CAN1_MB22_ID0() bfin_read16(CAN1_MB22_ID0)
713#define bfin_write_CAN1_MB22_ID0(val) bfin_write16(CAN1_MB22_ID0, val)
714#define bfin_read_CAN1_MB22_ID1() bfin_read16(CAN1_MB22_ID1)
715#define bfin_write_CAN1_MB22_ID1(val) bfin_write16(CAN1_MB22_ID1, val)
716#define bfin_read_CAN1_MB23_DATA0() bfin_read16(CAN1_MB23_DATA0)
717#define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val)
718#define bfin_read_CAN1_MB23_DATA1() bfin_read16(CAN1_MB23_DATA1)
719#define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val)
720#define bfin_read_CAN1_MB23_DATA2() bfin_read16(CAN1_MB23_DATA2)
721#define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val)
722#define bfin_read_CAN1_MB23_DATA3() bfin_read16(CAN1_MB23_DATA3)
723#define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val)
724#define bfin_read_CAN1_MB23_LENGTH() bfin_read16(CAN1_MB23_LENGTH)
725#define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val)
726#define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP)
727#define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val)
728#define bfin_read_CAN1_MB23_ID0() bfin_read16(CAN1_MB23_ID0)
729#define bfin_write_CAN1_MB23_ID0(val) bfin_write16(CAN1_MB23_ID0, val)
730#define bfin_read_CAN1_MB23_ID1() bfin_read16(CAN1_MB23_ID1)
731#define bfin_write_CAN1_MB23_ID1(val) bfin_write16(CAN1_MB23_ID1, val)
732#define bfin_read_CAN1_MB24_DATA0() bfin_read16(CAN1_MB24_DATA0)
733#define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val)
734#define bfin_read_CAN1_MB24_DATA1() bfin_read16(CAN1_MB24_DATA1)
735#define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val)
736#define bfin_read_CAN1_MB24_DATA2() bfin_read16(CAN1_MB24_DATA2)
737#define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val)
738#define bfin_read_CAN1_MB24_DATA3() bfin_read16(CAN1_MB24_DATA3)
739#define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val)
740#define bfin_read_CAN1_MB24_LENGTH() bfin_read16(CAN1_MB24_LENGTH)
741#define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val)
742#define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP)
743#define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val)
744#define bfin_read_CAN1_MB24_ID0() bfin_read16(CAN1_MB24_ID0)
745#define bfin_write_CAN1_MB24_ID0(val) bfin_write16(CAN1_MB24_ID0, val)
746#define bfin_read_CAN1_MB24_ID1() bfin_read16(CAN1_MB24_ID1)
747#define bfin_write_CAN1_MB24_ID1(val) bfin_write16(CAN1_MB24_ID1, val)
748#define bfin_read_CAN1_MB25_DATA0() bfin_read16(CAN1_MB25_DATA0)
749#define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val)
750#define bfin_read_CAN1_MB25_DATA1() bfin_read16(CAN1_MB25_DATA1)
751#define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val)
752#define bfin_read_CAN1_MB25_DATA2() bfin_read16(CAN1_MB25_DATA2)
753#define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val)
754#define bfin_read_CAN1_MB25_DATA3() bfin_read16(CAN1_MB25_DATA3)
755#define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val)
756#define bfin_read_CAN1_MB25_LENGTH() bfin_read16(CAN1_MB25_LENGTH)
757#define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val)
758#define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP)
759#define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val)
760#define bfin_read_CAN1_MB25_ID0() bfin_read16(CAN1_MB25_ID0)
761#define bfin_write_CAN1_MB25_ID0(val) bfin_write16(CAN1_MB25_ID0, val)
762#define bfin_read_CAN1_MB25_ID1() bfin_read16(CAN1_MB25_ID1)
763#define bfin_write_CAN1_MB25_ID1(val) bfin_write16(CAN1_MB25_ID1, val)
764#define bfin_read_CAN1_MB26_DATA0() bfin_read16(CAN1_MB26_DATA0)
765#define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val)
766#define bfin_read_CAN1_MB26_DATA1() bfin_read16(CAN1_MB26_DATA1)
767#define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val)
768#define bfin_read_CAN1_MB26_DATA2() bfin_read16(CAN1_MB26_DATA2)
769#define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val)
770#define bfin_read_CAN1_MB26_DATA3() bfin_read16(CAN1_MB26_DATA3)
771#define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val)
772#define bfin_read_CAN1_MB26_LENGTH() bfin_read16(CAN1_MB26_LENGTH)
773#define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val)
774#define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP)
775#define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val)
776#define bfin_read_CAN1_MB26_ID0() bfin_read16(CAN1_MB26_ID0)
777#define bfin_write_CAN1_MB26_ID0(val) bfin_write16(CAN1_MB26_ID0, val)
778#define bfin_read_CAN1_MB26_ID1() bfin_read16(CAN1_MB26_ID1)
779#define bfin_write_CAN1_MB26_ID1(val) bfin_write16(CAN1_MB26_ID1, val)
780#define bfin_read_CAN1_MB27_DATA0() bfin_read16(CAN1_MB27_DATA0)
781#define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val)
782#define bfin_read_CAN1_MB27_DATA1() bfin_read16(CAN1_MB27_DATA1)
783#define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val)
784#define bfin_read_CAN1_MB27_DATA2() bfin_read16(CAN1_MB27_DATA2)
785#define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val)
786#define bfin_read_CAN1_MB27_DATA3() bfin_read16(CAN1_MB27_DATA3)
787#define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val)
788#define bfin_read_CAN1_MB27_LENGTH() bfin_read16(CAN1_MB27_LENGTH)
789#define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val)
790#define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP)
791#define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val)
792#define bfin_read_CAN1_MB27_ID0() bfin_read16(CAN1_MB27_ID0)
793#define bfin_write_CAN1_MB27_ID0(val) bfin_write16(CAN1_MB27_ID0, val)
794#define bfin_read_CAN1_MB27_ID1() bfin_read16(CAN1_MB27_ID1)
795#define bfin_write_CAN1_MB27_ID1(val) bfin_write16(CAN1_MB27_ID1, val)
796#define bfin_read_CAN1_MB28_DATA0() bfin_read16(CAN1_MB28_DATA0)
797#define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val)
798#define bfin_read_CAN1_MB28_DATA1() bfin_read16(CAN1_MB28_DATA1)
799#define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val)
800#define bfin_read_CAN1_MB28_DATA2() bfin_read16(CAN1_MB28_DATA2)
801#define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val)
802#define bfin_read_CAN1_MB28_DATA3() bfin_read16(CAN1_MB28_DATA3)
803#define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val)
804#define bfin_read_CAN1_MB28_LENGTH() bfin_read16(CAN1_MB28_LENGTH)
805#define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val)
806#define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP)
807#define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val)
808#define bfin_read_CAN1_MB28_ID0() bfin_read16(CAN1_MB28_ID0)
809#define bfin_write_CAN1_MB28_ID0(val) bfin_write16(CAN1_MB28_ID0, val)
810#define bfin_read_CAN1_MB28_ID1() bfin_read16(CAN1_MB28_ID1)
811#define bfin_write_CAN1_MB28_ID1(val) bfin_write16(CAN1_MB28_ID1, val)
812#define bfin_read_CAN1_MB29_DATA0() bfin_read16(CAN1_MB29_DATA0)
813#define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val)
814#define bfin_read_CAN1_MB29_DATA1() bfin_read16(CAN1_MB29_DATA1)
815#define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val)
816#define bfin_read_CAN1_MB29_DATA2() bfin_read16(CAN1_MB29_DATA2)
817#define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val)
818#define bfin_read_CAN1_MB29_DATA3() bfin_read16(CAN1_MB29_DATA3)
819#define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val)
820#define bfin_read_CAN1_MB29_LENGTH() bfin_read16(CAN1_MB29_LENGTH)
821#define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val)
822#define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP)
823#define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val)
824#define bfin_read_CAN1_MB29_ID0() bfin_read16(CAN1_MB29_ID0)
825#define bfin_write_CAN1_MB29_ID0(val) bfin_write16(CAN1_MB29_ID0, val)
826#define bfin_read_CAN1_MB29_ID1() bfin_read16(CAN1_MB29_ID1)
827#define bfin_write_CAN1_MB29_ID1(val) bfin_write16(CAN1_MB29_ID1, val)
828#define bfin_read_CAN1_MB30_DATA0() bfin_read16(CAN1_MB30_DATA0)
829#define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val)
830#define bfin_read_CAN1_MB30_DATA1() bfin_read16(CAN1_MB30_DATA1)
831#define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val)
832#define bfin_read_CAN1_MB30_DATA2() bfin_read16(CAN1_MB30_DATA2)
833#define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val)
834#define bfin_read_CAN1_MB30_DATA3() bfin_read16(CAN1_MB30_DATA3)
835#define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val)
836#define bfin_read_CAN1_MB30_LENGTH() bfin_read16(CAN1_MB30_LENGTH)
837#define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val)
838#define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP)
839#define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val)
840#define bfin_read_CAN1_MB30_ID0() bfin_read16(CAN1_MB30_ID0)
841#define bfin_write_CAN1_MB30_ID0(val) bfin_write16(CAN1_MB30_ID0, val)
842#define bfin_read_CAN1_MB30_ID1() bfin_read16(CAN1_MB30_ID1)
843#define bfin_write_CAN1_MB30_ID1(val) bfin_write16(CAN1_MB30_ID1, val)
844#define bfin_read_CAN1_MB31_DATA0() bfin_read16(CAN1_MB31_DATA0)
845#define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val)
846#define bfin_read_CAN1_MB31_DATA1() bfin_read16(CAN1_MB31_DATA1)
847#define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val)
848#define bfin_read_CAN1_MB31_DATA2() bfin_read16(CAN1_MB31_DATA2)
849#define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val)
850#define bfin_read_CAN1_MB31_DATA3() bfin_read16(CAN1_MB31_DATA3)
851#define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val)
852#define bfin_read_CAN1_MB31_LENGTH() bfin_read16(CAN1_MB31_LENGTH)
853#define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val)
854#define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP)
855#define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val)
856#define bfin_read_CAN1_MB31_ID0() bfin_read16(CAN1_MB31_ID0)
857#define bfin_write_CAN1_MB31_ID0(val) bfin_write16(CAN1_MB31_ID0, val)
858#define bfin_read_CAN1_MB31_ID1() bfin_read16(CAN1_MB31_ID1)
859#define bfin_write_CAN1_MB31_ID1(val) bfin_write16(CAN1_MB31_ID1, val)
860
861/* HOST Port Registers */
862
863#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
864#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
865#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
866#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
867#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
868#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
869
870/* Pixel Combfin_read_()ositor (PIXC) Registers */
871
872#define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL)
873#define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val)
874#define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL)
875#define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val)
876#define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF)
877#define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val)
878#define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART)
879#define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val)
880#define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND)
881#define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val)
882#define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART)
883#define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val)
884#define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND)
885#define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val)
886#define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP)
887#define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val)
888#define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART)
889#define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val)
890#define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND)
891#define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val)
892#define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART)
893#define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val)
894#define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND)
895#define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val)
896#define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP)
897#define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val)
898#define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT)
899#define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val)
900#define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON)
901#define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val)
902#define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON)
903#define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val)
904#define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON)
905#define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val)
906#define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS)
907#define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val)
908#define bfin_read_PIXC_TC() bfin_read32(PIXC_TC)
909#define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val)
910
911/* Handshake MDMA 0 Registers */
912
913#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
914#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
915#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
916#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
917#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
918#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
919#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
920#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
921#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
922#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
923#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
924#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
925#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
926#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
927
928/* Handshake MDMA 1 Registers */
929
930#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
931#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
932#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
933#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
934#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
935#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
936#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
937#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
938#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
939#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
940#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
941#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
942#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
943#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
944
945#endif /* _CDEF_BF544_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF547.h b/arch/blackfin/mach-bf548/include/mach/cdefBF547.h
new file mode 100644
index 000000000000..93376e90dfc5
--- /dev/null
+++ b/arch/blackfin/mach-bf548/include/mach/cdefBF547.h
@@ -0,0 +1,832 @@
1/*
2 * File: include/asm-blackfin/mach-bf548/cdefBF547.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _CDEF_BF548_H
32#define _CDEF_BF548_H
33
34/* include all Core registers and bit definitions */
35#include "defBF548.h"
36
37/* include core sbfin_read_()ecific register pointer definitions */
38#include <asm/cdef_LPBlackfin.h>
39
40/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */
41
42/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
43#include "cdefBF54x_base.h"
44
45/* The following are the #defines needed by ADSP-BF548 that are not in the common header */
46
47/* Timer Registers */
48
49#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG)
50#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val)
51#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER)
52#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
53#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD)
54#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val)
55#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH)
56#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val)
57#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG)
58#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val)
59#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER)
60#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
61#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD)
62#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val)
63#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH)
64#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val)
65#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG)
66#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
67#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER)
68#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
69#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD)
70#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
71#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH)
72#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val)
73
74/* Timer Groubfin_read_() of 3 */
75
76#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1)
77#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val)
78#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1)
79#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
80#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1)
81#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val)
82
83/* SPORT0 Registers */
84
85#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
86#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
87#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
88#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
89#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
90#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
91#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
92#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
93#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
94#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
95#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
96#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
97#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
98#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
99#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
100#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
101#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
102#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
103#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
104#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
105#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
106#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
107#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
108#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
109#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
110#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
111#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
112#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
113#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
114#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
115#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
116#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
117#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
118#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
119#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
120#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
121#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
122#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
123#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
124#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
125#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
126#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
127#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
128#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
129
130/* EPPI0 Registers */
131
132#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS)
133#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val)
134#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT)
135#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val)
136#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY)
137#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val)
138#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT)
139#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val)
140#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY)
141#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val)
142#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME)
143#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val)
144#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE)
145#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val)
146#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV)
147#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val)
148#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL)
149#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val)
150#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL)
151#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
152#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL)
153#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
154#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB)
155#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
156#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF)
157#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
158#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP)
159#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val)
160
161/* UART2 Registers */
162
163#define bfin_read_UART2_DLL() bfin_read16(UART2_DLL)
164#define bfin_write_UART2_DLL(val) bfin_write16(UART2_DLL, val)
165#define bfin_read_UART2_DLH() bfin_read16(UART2_DLH)
166#define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val)
167#define bfin_read_UART2_GCTL() bfin_read16(UART2_GCTL)
168#define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val)
169#define bfin_read_UART2_LCR() bfin_read16(UART2_LCR)
170#define bfin_write_UART2_LCR(val) bfin_write16(UART2_LCR, val)
171#define bfin_read_UART2_MCR() bfin_read16(UART2_MCR)
172#define bfin_write_UART2_MCR(val) bfin_write16(UART2_MCR, val)
173#define bfin_read_UART2_LSR() bfin_read16(UART2_LSR)
174#define bfin_write_UART2_LSR(val) bfin_write16(UART2_LSR, val)
175#define bfin_read_UART2_MSR() bfin_read16(UART2_MSR)
176#define bfin_write_UART2_MSR(val) bfin_write16(UART2_MSR, val)
177#define bfin_read_UART2_SCR() bfin_read16(UART2_SCR)
178#define bfin_write_UART2_SCR(val) bfin_write16(UART2_SCR, val)
179#define bfin_read_UART2_IER_SET() bfin_read16(UART2_IER_SET)
180#define bfin_write_UART2_IER_SET(val) bfin_write16(UART2_IER_SET, val)
181#define bfin_read_UART2_IER_CLEAR() bfin_read16(UART2_IER_CLEAR)
182#define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val)
183#define bfin_read_UART2_RBR() bfin_read16(UART2_RBR)
184#define bfin_write_UART2_RBR(val) bfin_write16(UART2_RBR, val)
185
186/* Two Wire Interface Registers (TWI1) */
187
188/* SPI2 Registers */
189
190#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL)
191#define bfin_write_SPI2_CTL(val) bfin_write16(SPI2_CTL, val)
192#define bfin_read_SPI2_FLG() bfin_read16(SPI2_FLG)
193#define bfin_write_SPI2_FLG(val) bfin_write16(SPI2_FLG, val)
194#define bfin_read_SPI2_STAT() bfin_read16(SPI2_STAT)
195#define bfin_write_SPI2_STAT(val) bfin_write16(SPI2_STAT, val)
196#define bfin_read_SPI2_TDBR() bfin_read16(SPI2_TDBR)
197#define bfin_write_SPI2_TDBR(val) bfin_write16(SPI2_TDBR, val)
198#define bfin_read_SPI2_RDBR() bfin_read16(SPI2_RDBR)
199#define bfin_write_SPI2_RDBR(val) bfin_write16(SPI2_RDBR, val)
200#define bfin_read_SPI2_BAUD() bfin_read16(SPI2_BAUD)
201#define bfin_write_SPI2_BAUD(val) bfin_write16(SPI2_BAUD, val)
202#define bfin_read_SPI2_SHADOW() bfin_read16(SPI2_SHADOW)
203#define bfin_write_SPI2_SHADOW(val) bfin_write16(SPI2_SHADOW, val)
204
205/* ATAPI Registers */
206
207#define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL)
208#define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val)
209#define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS)
210#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val)
211#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR)
212#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
213#define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF)
214#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
215#define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF)
216#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
217#define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK)
218#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
219#define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS)
220#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
221#define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN)
222#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
223#define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS)
224#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
225#define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE)
226#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
227#define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE)
228#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
229#define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT)
230#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
231#define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT)
232#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
233#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT)
234#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
235#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT)
236#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
237#define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0)
238#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
239#define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0)
240#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
241#define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1)
242#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
243#define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0)
244#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
245#define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1)
246#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
247#define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2)
248#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
249#define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0)
250#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
251#define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1)
252#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
253#define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2)
254#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
255#define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3)
256#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
257
258/* SDH Registers */
259
260#define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL)
261#define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val)
262#define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL)
263#define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val)
264#define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT)
265#define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val)
266#define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND)
267#define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val)
268#define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD)
269#define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val)
270#define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0)
271#define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val)
272#define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1)
273#define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val)
274#define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2)
275#define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val)
276#define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3)
277#define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val)
278#define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER)
279#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
280#define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH)
281#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val)
282#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL)
283#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val)
284#define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT)
285#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val)
286#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS)
287#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val)
288#define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR)
289#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val)
290#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0)
291#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val)
292#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1)
293#define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val)
294#define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT)
295#define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val)
296#define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO)
297#define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val)
298#define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS)
299#define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val)
300#define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK)
301#define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val)
302#define bfin_read_SDH_CFG() bfin_read16(SDH_CFG)
303#define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val)
304#define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN)
305#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
306#define bfin_read_SDH_PID0() bfin_read16(SDH_PID0)
307#define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val)
308#define bfin_read_SDH_PID1() bfin_read16(SDH_PID1)
309#define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val)
310#define bfin_read_SDH_PID2() bfin_read16(SDH_PID2)
311#define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val)
312#define bfin_read_SDH_PID3() bfin_read16(SDH_PID3)
313#define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val)
314#define bfin_read_SDH_PID4() bfin_read16(SDH_PID4)
315#define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val)
316#define bfin_read_SDH_PID5() bfin_read16(SDH_PID5)
317#define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val)
318#define bfin_read_SDH_PID6() bfin_read16(SDH_PID6)
319#define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val)
320#define bfin_read_SDH_PID7() bfin_read16(SDH_PID7)
321#define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val)
322
323/* HOST Port Registers */
324
325#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
326#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
327#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
328#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
329#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
330#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
331
332/* USB Control Registers */
333
334#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
335#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
336#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
337#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
338#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
339#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
340#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
341#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
342#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
343#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
344#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
345#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
346#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
347#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
348#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
349#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
350#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
351#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
352#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
353#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
354#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
355#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
356#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
357#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
358#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
359#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
360
361/* USB Packet Control Registers */
362
363#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
364#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
365#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
366#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
367#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
368#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
369#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
370#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
371#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
372#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
373#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
374#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
375#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
376#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
377#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
378#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
379#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
380#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
381#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
382#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
383#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
384#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
385#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
386#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
387#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
388#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
389
390/* USB Endbfin_read_()oint FIFO Registers */
391
392#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
393#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
394#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
395#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
396#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
397#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
398#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
399#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
400#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
401#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
402#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
403#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
404#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
405#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
406#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
407#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
408
409/* USB OTG Control Registers */
410
411#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
412#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
413#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
414#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
415#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
416#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
417
418/* USB Phy Control Registers */
419
420#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
421#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
422#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
423#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
424#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
425#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
426#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
427#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
428#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
429#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
430
431/* (APHY_CNTRL is for ADI usage only) */
432
433#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
434#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
435
436/* (APHY_CALIB is for ADI usage only) */
437
438#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
439#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
440#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
441#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
442
443/* (PHY_TEST is for ADI usage only) */
444
445#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST)
446#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val)
447#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
448#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
449#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
450#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
451
452/* USB Endbfin_read_()oint 0 Control Registers */
453
454#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
455#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
456#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
457#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
458#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
459#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
460#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
461#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
462#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
463#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
464#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
465#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
466#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
467#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
468#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
469#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
470#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
471#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
472
473/* USB Endbfin_read_()oint 1 Control Registers */
474
475#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
476#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
477#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
478#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
479#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
480#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
481#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
482#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
483#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
484#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
485#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
486#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
487#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
488#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
489#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
490#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
491#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
492#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
493#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
494#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
495
496/* USB Endbfin_read_()oint 2 Control Registers */
497
498#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
499#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
500#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
501#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
502#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
503#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
504#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
505#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
506#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
507#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
508#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
509#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
510#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
511#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
512#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
513#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
514#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
515#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
516#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
517#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
518
519/* USB Endbfin_read_()oint 3 Control Registers */
520
521#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
522#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
523#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
524#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
525#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
526#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
527#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
528#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
529#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
530#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
531#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
532#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
533#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
534#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
535#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
536#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
537#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
538#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
539#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
540#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
541
542/* USB Endbfin_read_()oint 4 Control Registers */
543
544#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
545#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
546#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
547#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
548#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
549#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
550#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
551#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
552#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
553#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
554#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
555#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
556#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
557#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
558#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
559#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
560#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
561#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
562#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
563#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
564
565/* USB Endbfin_read_()oint 5 Control Registers */
566
567#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
568#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
569#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
570#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
571#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
572#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
573#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
574#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
575#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
576#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
577#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
578#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
579#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
580#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
581#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
582#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
583#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
584#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
585#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
586#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
587
588/* USB Endbfin_read_()oint 6 Control Registers */
589
590#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
591#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
592#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
593#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
594#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
595#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
596#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
597#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
598#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
599#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
600#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
601#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
602#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
603#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
604#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
605#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
606#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
607#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
608#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
609#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
610
611/* USB Endbfin_read_()oint 7 Control Registers */
612
613#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
614#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
615#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
616#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
617#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
618#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
619#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
620#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
621#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
622#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
623#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
624#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
625#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
626#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
627#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
628#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
629#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
630#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
631#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
632#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
633#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
634#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
635#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
636#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
637
638/* USB Channel 0 Config Registers */
639
640#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL)
641#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val)
642#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW)
643#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val)
644#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH)
645#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val)
646#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW)
647#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val)
648#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH)
649#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val)
650
651/* USB Channel 1 Config Registers */
652
653#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL)
654#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val)
655#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW)
656#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val)
657#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH)
658#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val)
659#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW)
660#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val)
661#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH)
662#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val)
663
664/* USB Channel 2 Config Registers */
665
666#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL)
667#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val)
668#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW)
669#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val)
670#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH)
671#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val)
672#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW)
673#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val)
674#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH)
675#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val)
676
677/* USB Channel 3 Config Registers */
678
679#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL)
680#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val)
681#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW)
682#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val)
683#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH)
684#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val)
685#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW)
686#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val)
687#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH)
688#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val)
689
690/* USB Channel 4 Config Registers */
691
692#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL)
693#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val)
694#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW)
695#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val)
696#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH)
697#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val)
698#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW)
699#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val)
700#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH)
701#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val)
702
703/* USB Channel 5 Config Registers */
704
705#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL)
706#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val)
707#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW)
708#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val)
709#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH)
710#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val)
711#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW)
712#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val)
713#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH)
714#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val)
715
716/* USB Channel 6 Config Registers */
717
718#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL)
719#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val)
720#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW)
721#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val)
722#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH)
723#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val)
724#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW)
725#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val)
726#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH)
727#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val)
728
729/* USB Channel 7 Config Registers */
730
731#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL)
732#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val)
733#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW)
734#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val)
735#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH)
736#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val)
737#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW)
738#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val)
739#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH)
740#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val)
741
742/* Keybfin_read_()ad Registers */
743
744#define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL)
745#define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val)
746#define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE)
747#define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val)
748#define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL)
749#define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val)
750#define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL)
751#define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val)
752#define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT)
753#define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val)
754#define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL)
755#define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val)
756
757/* Pixel Combfin_read_()ositor (PIXC) Registers */
758
759#define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL)
760#define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val)
761#define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL)
762#define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val)
763#define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF)
764#define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val)
765#define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART)
766#define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val)
767#define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND)
768#define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val)
769#define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART)
770#define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val)
771#define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND)
772#define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val)
773#define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP)
774#define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val)
775#define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART)
776#define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val)
777#define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND)
778#define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val)
779#define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART)
780#define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val)
781#define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND)
782#define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val)
783#define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP)
784#define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val)
785#define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT)
786#define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val)
787#define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON)
788#define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val)
789#define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON)
790#define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val)
791#define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON)
792#define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val)
793#define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS)
794#define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val)
795#define bfin_read_PIXC_TC() bfin_read32(PIXC_TC)
796#define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val)
797
798/* Handshake MDMA 0 Registers */
799
800#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
801#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
802#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
803#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
804#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
805#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
806#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
807#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
808#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
809#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
810#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
811#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
812#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
813#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
814
815/* Handshake MDMA 1 Registers */
816
817#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
818#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
819#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
820#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
821#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
822#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
823#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
824#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
825#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
826#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
827#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
828#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
829#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
830#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
831
832#endif /* _CDEF_BF548_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF548.h b/arch/blackfin/mach-bf548/include/mach/cdefBF548.h
new file mode 100644
index 000000000000..9cd74384136f
--- /dev/null
+++ b/arch/blackfin/mach-bf548/include/mach/cdefBF548.h
@@ -0,0 +1,1577 @@
1/*
2 * File: include/asm-blackfin/mach-bf548/cdefBF548.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _CDEF_BF548_H
32#define _CDEF_BF548_H
33
34/* include all Core registers and bit definitions */
35#include "defBF548.h"
36
37/* include core sbfin_read_()ecific register pointer definitions */
38#include <asm/cdef_LPBlackfin.h>
39
40/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */
41
42/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
43#include "cdefBF54x_base.h"
44
45/* The following are the #defines needed by ADSP-BF548 that are not in the common header */
46
47/* Timer Registers */
48
49#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG)
50#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val)
51#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER)
52#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
53#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD)
54#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val)
55#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH)
56#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val)
57#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG)
58#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val)
59#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER)
60#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
61#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD)
62#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val)
63#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH)
64#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val)
65#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG)
66#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
67#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER)
68#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
69#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD)
70#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
71#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH)
72#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val)
73
74/* Timer Groubfin_read_() of 3 */
75
76#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1)
77#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val)
78#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1)
79#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
80#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1)
81#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val)
82
83/* SPORT0 Registers */
84
85#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
86#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
87#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
88#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
89#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
90#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
91#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
92#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
93#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
94#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
95#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
96#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
97#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
98#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
99#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
100#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
101#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
102#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
103#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
104#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
105#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
106#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
107#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
108#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
109#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
110#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
111#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
112#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
113#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
114#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
115#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
116#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
117#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
118#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
119#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
120#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
121#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
122#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
123#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
124#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
125#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
126#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
127#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
128#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
129
130/* EPPI0 Registers */
131
132#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS)
133#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val)
134#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT)
135#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val)
136#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY)
137#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val)
138#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT)
139#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val)
140#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY)
141#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val)
142#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME)
143#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val)
144#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE)
145#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val)
146#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV)
147#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val)
148#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL)
149#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val)
150#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL)
151#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
152#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL)
153#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
154#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB)
155#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
156#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF)
157#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
158#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP)
159#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val)
160
161/* UART2 Registers */
162
163#define bfin_read_UART2_DLL() bfin_read16(UART2_DLL)
164#define bfin_write_UART2_DLL(val) bfin_write16(UART2_DLL, val)
165#define bfin_read_UART2_DLH() bfin_read16(UART2_DLH)
166#define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val)
167#define bfin_read_UART2_GCTL() bfin_read16(UART2_GCTL)
168#define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val)
169#define bfin_read_UART2_LCR() bfin_read16(UART2_LCR)
170#define bfin_write_UART2_LCR(val) bfin_write16(UART2_LCR, val)
171#define bfin_read_UART2_MCR() bfin_read16(UART2_MCR)
172#define bfin_write_UART2_MCR(val) bfin_write16(UART2_MCR, val)
173#define bfin_read_UART2_LSR() bfin_read16(UART2_LSR)
174#define bfin_write_UART2_LSR(val) bfin_write16(UART2_LSR, val)
175#define bfin_read_UART2_MSR() bfin_read16(UART2_MSR)
176#define bfin_write_UART2_MSR(val) bfin_write16(UART2_MSR, val)
177#define bfin_read_UART2_SCR() bfin_read16(UART2_SCR)
178#define bfin_write_UART2_SCR(val) bfin_write16(UART2_SCR, val)
179#define bfin_read_UART2_IER_SET() bfin_read16(UART2_IER_SET)
180#define bfin_write_UART2_IER_SET(val) bfin_write16(UART2_IER_SET, val)
181#define bfin_read_UART2_IER_CLEAR() bfin_read16(UART2_IER_CLEAR)
182#define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val)
183#define bfin_read_UART2_RBR() bfin_read16(UART2_RBR)
184#define bfin_write_UART2_RBR(val) bfin_write16(UART2_RBR, val)
185
186/* Two Wire Interface Registers (TWI1) */
187
188/* SPI2 Registers */
189
190#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL)
191#define bfin_write_SPI2_CTL(val) bfin_write16(SPI2_CTL, val)
192#define bfin_read_SPI2_FLG() bfin_read16(SPI2_FLG)
193#define bfin_write_SPI2_FLG(val) bfin_write16(SPI2_FLG, val)
194#define bfin_read_SPI2_STAT() bfin_read16(SPI2_STAT)
195#define bfin_write_SPI2_STAT(val) bfin_write16(SPI2_STAT, val)
196#define bfin_read_SPI2_TDBR() bfin_read16(SPI2_TDBR)
197#define bfin_write_SPI2_TDBR(val) bfin_write16(SPI2_TDBR, val)
198#define bfin_read_SPI2_RDBR() bfin_read16(SPI2_RDBR)
199#define bfin_write_SPI2_RDBR(val) bfin_write16(SPI2_RDBR, val)
200#define bfin_read_SPI2_BAUD() bfin_read16(SPI2_BAUD)
201#define bfin_write_SPI2_BAUD(val) bfin_write16(SPI2_BAUD, val)
202#define bfin_read_SPI2_SHADOW() bfin_read16(SPI2_SHADOW)
203#define bfin_write_SPI2_SHADOW(val) bfin_write16(SPI2_SHADOW, val)
204
205/* CAN Controller 1 Config 1 Registers */
206
207#define bfin_read_CAN1_MC1() bfin_read16(CAN1_MC1)
208#define bfin_write_CAN1_MC1(val) bfin_write16(CAN1_MC1, val)
209#define bfin_read_CAN1_MD1() bfin_read16(CAN1_MD1)
210#define bfin_write_CAN1_MD1(val) bfin_write16(CAN1_MD1, val)
211#define bfin_read_CAN1_TRS1() bfin_read16(CAN1_TRS1)
212#define bfin_write_CAN1_TRS1(val) bfin_write16(CAN1_TRS1, val)
213#define bfin_read_CAN1_TRR1() bfin_read16(CAN1_TRR1)
214#define bfin_write_CAN1_TRR1(val) bfin_write16(CAN1_TRR1, val)
215#define bfin_read_CAN1_TA1() bfin_read16(CAN1_TA1)
216#define bfin_write_CAN1_TA1(val) bfin_write16(CAN1_TA1, val)
217#define bfin_read_CAN1_AA1() bfin_read16(CAN1_AA1)
218#define bfin_write_CAN1_AA1(val) bfin_write16(CAN1_AA1, val)
219#define bfin_read_CAN1_RMP1() bfin_read16(CAN1_RMP1)
220#define bfin_write_CAN1_RMP1(val) bfin_write16(CAN1_RMP1, val)
221#define bfin_read_CAN1_RML1() bfin_read16(CAN1_RML1)
222#define bfin_write_CAN1_RML1(val) bfin_write16(CAN1_RML1, val)
223#define bfin_read_CAN1_MBTIF1() bfin_read16(CAN1_MBTIF1)
224#define bfin_write_CAN1_MBTIF1(val) bfin_write16(CAN1_MBTIF1, val)
225#define bfin_read_CAN1_MBRIF1() bfin_read16(CAN1_MBRIF1)
226#define bfin_write_CAN1_MBRIF1(val) bfin_write16(CAN1_MBRIF1, val)
227#define bfin_read_CAN1_MBIM1() bfin_read16(CAN1_MBIM1)
228#define bfin_write_CAN1_MBIM1(val) bfin_write16(CAN1_MBIM1, val)
229#define bfin_read_CAN1_RFH1() bfin_read16(CAN1_RFH1)
230#define bfin_write_CAN1_RFH1(val) bfin_write16(CAN1_RFH1, val)
231#define bfin_read_CAN1_OPSS1() bfin_read16(CAN1_OPSS1)
232#define bfin_write_CAN1_OPSS1(val) bfin_write16(CAN1_OPSS1, val)
233
234/* CAN Controller 1 Config 2 Registers */
235
236#define bfin_read_CAN1_MC2() bfin_read16(CAN1_MC2)
237#define bfin_write_CAN1_MC2(val) bfin_write16(CAN1_MC2, val)
238#define bfin_read_CAN1_MD2() bfin_read16(CAN1_MD2)
239#define bfin_write_CAN1_MD2(val) bfin_write16(CAN1_MD2, val)
240#define bfin_read_CAN1_TRS2() bfin_read16(CAN1_TRS2)
241#define bfin_write_CAN1_TRS2(val) bfin_write16(CAN1_TRS2, val)
242#define bfin_read_CAN1_TRR2() bfin_read16(CAN1_TRR2)
243#define bfin_write_CAN1_TRR2(val) bfin_write16(CAN1_TRR2, val)
244#define bfin_read_CAN1_TA2() bfin_read16(CAN1_TA2)
245#define bfin_write_CAN1_TA2(val) bfin_write16(CAN1_TA2, val)
246#define bfin_read_CAN1_AA2() bfin_read16(CAN1_AA2)
247#define bfin_write_CAN1_AA2(val) bfin_write16(CAN1_AA2, val)
248#define bfin_read_CAN1_RMP2() bfin_read16(CAN1_RMP2)
249#define bfin_write_CAN1_RMP2(val) bfin_write16(CAN1_RMP2, val)
250#define bfin_read_CAN1_RML2() bfin_read16(CAN1_RML2)
251#define bfin_write_CAN1_RML2(val) bfin_write16(CAN1_RML2, val)
252#define bfin_read_CAN1_MBTIF2() bfin_read16(CAN1_MBTIF2)
253#define bfin_write_CAN1_MBTIF2(val) bfin_write16(CAN1_MBTIF2, val)
254#define bfin_read_CAN1_MBRIF2() bfin_read16(CAN1_MBRIF2)
255#define bfin_write_CAN1_MBRIF2(val) bfin_write16(CAN1_MBRIF2, val)
256#define bfin_read_CAN1_MBIM2() bfin_read16(CAN1_MBIM2)
257#define bfin_write_CAN1_MBIM2(val) bfin_write16(CAN1_MBIM2, val)
258#define bfin_read_CAN1_RFH2() bfin_read16(CAN1_RFH2)
259#define bfin_write_CAN1_RFH2(val) bfin_write16(CAN1_RFH2, val)
260#define bfin_read_CAN1_OPSS2() bfin_read16(CAN1_OPSS2)
261#define bfin_write_CAN1_OPSS2(val) bfin_write16(CAN1_OPSS2, val)
262
263/* CAN Controller 1 Clock/Interrubfin_read_()t/Counter Registers */
264
265#define bfin_read_CAN1_CLOCK() bfin_read16(CAN1_CLOCK)
266#define bfin_write_CAN1_CLOCK(val) bfin_write16(CAN1_CLOCK, val)
267#define bfin_read_CAN1_TIMING() bfin_read16(CAN1_TIMING)
268#define bfin_write_CAN1_TIMING(val) bfin_write16(CAN1_TIMING, val)
269#define bfin_read_CAN1_DEBUG() bfin_read16(CAN1_DEBUG)
270#define bfin_write_CAN1_DEBUG(val) bfin_write16(CAN1_DEBUG, val)
271#define bfin_read_CAN1_STATUS() bfin_read16(CAN1_STATUS)
272#define bfin_write_CAN1_STATUS(val) bfin_write16(CAN1_STATUS, val)
273#define bfin_read_CAN1_CEC() bfin_read16(CAN1_CEC)
274#define bfin_write_CAN1_CEC(val) bfin_write16(CAN1_CEC, val)
275#define bfin_read_CAN1_GIS() bfin_read16(CAN1_GIS)
276#define bfin_write_CAN1_GIS(val) bfin_write16(CAN1_GIS, val)
277#define bfin_read_CAN1_GIM() bfin_read16(CAN1_GIM)
278#define bfin_write_CAN1_GIM(val) bfin_write16(CAN1_GIM, val)
279#define bfin_read_CAN1_GIF() bfin_read16(CAN1_GIF)
280#define bfin_write_CAN1_GIF(val) bfin_write16(CAN1_GIF, val)
281#define bfin_read_CAN1_CONTROL() bfin_read16(CAN1_CONTROL)
282#define bfin_write_CAN1_CONTROL(val) bfin_write16(CAN1_CONTROL, val)
283#define bfin_read_CAN1_INTR() bfin_read16(CAN1_INTR)
284#define bfin_write_CAN1_INTR(val) bfin_write16(CAN1_INTR, val)
285#define bfin_read_CAN1_MBTD() bfin_read16(CAN1_MBTD)
286#define bfin_write_CAN1_MBTD(val) bfin_write16(CAN1_MBTD, val)
287#define bfin_read_CAN1_EWR() bfin_read16(CAN1_EWR)
288#define bfin_write_CAN1_EWR(val) bfin_write16(CAN1_EWR, val)
289#define bfin_read_CAN1_ESR() bfin_read16(CAN1_ESR)
290#define bfin_write_CAN1_ESR(val) bfin_write16(CAN1_ESR, val)
291#define bfin_read_CAN1_UCCNT() bfin_read16(CAN1_UCCNT)
292#define bfin_write_CAN1_UCCNT(val) bfin_write16(CAN1_UCCNT, val)
293#define bfin_read_CAN1_UCRC() bfin_read16(CAN1_UCRC)
294#define bfin_write_CAN1_UCRC(val) bfin_write16(CAN1_UCRC, val)
295#define bfin_read_CAN1_UCCNF() bfin_read16(CAN1_UCCNF)
296#define bfin_write_CAN1_UCCNF(val) bfin_write16(CAN1_UCCNF, val)
297
298/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
299
300#define bfin_read_CAN1_AM00L() bfin_read16(CAN1_AM00L)
301#define bfin_write_CAN1_AM00L(val) bfin_write16(CAN1_AM00L, val)
302#define bfin_read_CAN1_AM00H() bfin_read16(CAN1_AM00H)
303#define bfin_write_CAN1_AM00H(val) bfin_write16(CAN1_AM00H, val)
304#define bfin_read_CAN1_AM01L() bfin_read16(CAN1_AM01L)
305#define bfin_write_CAN1_AM01L(val) bfin_write16(CAN1_AM01L, val)
306#define bfin_read_CAN1_AM01H() bfin_read16(CAN1_AM01H)
307#define bfin_write_CAN1_AM01H(val) bfin_write16(CAN1_AM01H, val)
308#define bfin_read_CAN1_AM02L() bfin_read16(CAN1_AM02L)
309#define bfin_write_CAN1_AM02L(val) bfin_write16(CAN1_AM02L, val)
310#define bfin_read_CAN1_AM02H() bfin_read16(CAN1_AM02H)
311#define bfin_write_CAN1_AM02H(val) bfin_write16(CAN1_AM02H, val)
312#define bfin_read_CAN1_AM03L() bfin_read16(CAN1_AM03L)
313#define bfin_write_CAN1_AM03L(val) bfin_write16(CAN1_AM03L, val)
314#define bfin_read_CAN1_AM03H() bfin_read16(CAN1_AM03H)
315#define bfin_write_CAN1_AM03H(val) bfin_write16(CAN1_AM03H, val)
316#define bfin_read_CAN1_AM04L() bfin_read16(CAN1_AM04L)
317#define bfin_write_CAN1_AM04L(val) bfin_write16(CAN1_AM04L, val)
318#define bfin_read_CAN1_AM04H() bfin_read16(CAN1_AM04H)
319#define bfin_write_CAN1_AM04H(val) bfin_write16(CAN1_AM04H, val)
320#define bfin_read_CAN1_AM05L() bfin_read16(CAN1_AM05L)
321#define bfin_write_CAN1_AM05L(val) bfin_write16(CAN1_AM05L, val)
322#define bfin_read_CAN1_AM05H() bfin_read16(CAN1_AM05H)
323#define bfin_write_CAN1_AM05H(val) bfin_write16(CAN1_AM05H, val)
324#define bfin_read_CAN1_AM06L() bfin_read16(CAN1_AM06L)
325#define bfin_write_CAN1_AM06L(val) bfin_write16(CAN1_AM06L, val)
326#define bfin_read_CAN1_AM06H() bfin_read16(CAN1_AM06H)
327#define bfin_write_CAN1_AM06H(val) bfin_write16(CAN1_AM06H, val)
328#define bfin_read_CAN1_AM07L() bfin_read16(CAN1_AM07L)
329#define bfin_write_CAN1_AM07L(val) bfin_write16(CAN1_AM07L, val)
330#define bfin_read_CAN1_AM07H() bfin_read16(CAN1_AM07H)
331#define bfin_write_CAN1_AM07H(val) bfin_write16(CAN1_AM07H, val)
332#define bfin_read_CAN1_AM08L() bfin_read16(CAN1_AM08L)
333#define bfin_write_CAN1_AM08L(val) bfin_write16(CAN1_AM08L, val)
334#define bfin_read_CAN1_AM08H() bfin_read16(CAN1_AM08H)
335#define bfin_write_CAN1_AM08H(val) bfin_write16(CAN1_AM08H, val)
336#define bfin_read_CAN1_AM09L() bfin_read16(CAN1_AM09L)
337#define bfin_write_CAN1_AM09L(val) bfin_write16(CAN1_AM09L, val)
338#define bfin_read_CAN1_AM09H() bfin_read16(CAN1_AM09H)
339#define bfin_write_CAN1_AM09H(val) bfin_write16(CAN1_AM09H, val)
340#define bfin_read_CAN1_AM10L() bfin_read16(CAN1_AM10L)
341#define bfin_write_CAN1_AM10L(val) bfin_write16(CAN1_AM10L, val)
342#define bfin_read_CAN1_AM10H() bfin_read16(CAN1_AM10H)
343#define bfin_write_CAN1_AM10H(val) bfin_write16(CAN1_AM10H, val)
344#define bfin_read_CAN1_AM11L() bfin_read16(CAN1_AM11L)
345#define bfin_write_CAN1_AM11L(val) bfin_write16(CAN1_AM11L, val)
346#define bfin_read_CAN1_AM11H() bfin_read16(CAN1_AM11H)
347#define bfin_write_CAN1_AM11H(val) bfin_write16(CAN1_AM11H, val)
348#define bfin_read_CAN1_AM12L() bfin_read16(CAN1_AM12L)
349#define bfin_write_CAN1_AM12L(val) bfin_write16(CAN1_AM12L, val)
350#define bfin_read_CAN1_AM12H() bfin_read16(CAN1_AM12H)
351#define bfin_write_CAN1_AM12H(val) bfin_write16(CAN1_AM12H, val)
352#define bfin_read_CAN1_AM13L() bfin_read16(CAN1_AM13L)
353#define bfin_write_CAN1_AM13L(val) bfin_write16(CAN1_AM13L, val)
354#define bfin_read_CAN1_AM13H() bfin_read16(CAN1_AM13H)
355#define bfin_write_CAN1_AM13H(val) bfin_write16(CAN1_AM13H, val)
356#define bfin_read_CAN1_AM14L() bfin_read16(CAN1_AM14L)
357#define bfin_write_CAN1_AM14L(val) bfin_write16(CAN1_AM14L, val)
358#define bfin_read_CAN1_AM14H() bfin_read16(CAN1_AM14H)
359#define bfin_write_CAN1_AM14H(val) bfin_write16(CAN1_AM14H, val)
360#define bfin_read_CAN1_AM15L() bfin_read16(CAN1_AM15L)
361#define bfin_write_CAN1_AM15L(val) bfin_write16(CAN1_AM15L, val)
362#define bfin_read_CAN1_AM15H() bfin_read16(CAN1_AM15H)
363#define bfin_write_CAN1_AM15H(val) bfin_write16(CAN1_AM15H, val)
364
365/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
366
367#define bfin_read_CAN1_AM16L() bfin_read16(CAN1_AM16L)
368#define bfin_write_CAN1_AM16L(val) bfin_write16(CAN1_AM16L, val)
369#define bfin_read_CAN1_AM16H() bfin_read16(CAN1_AM16H)
370#define bfin_write_CAN1_AM16H(val) bfin_write16(CAN1_AM16H, val)
371#define bfin_read_CAN1_AM17L() bfin_read16(CAN1_AM17L)
372#define bfin_write_CAN1_AM17L(val) bfin_write16(CAN1_AM17L, val)
373#define bfin_read_CAN1_AM17H() bfin_read16(CAN1_AM17H)
374#define bfin_write_CAN1_AM17H(val) bfin_write16(CAN1_AM17H, val)
375#define bfin_read_CAN1_AM18L() bfin_read16(CAN1_AM18L)
376#define bfin_write_CAN1_AM18L(val) bfin_write16(CAN1_AM18L, val)
377#define bfin_read_CAN1_AM18H() bfin_read16(CAN1_AM18H)
378#define bfin_write_CAN1_AM18H(val) bfin_write16(CAN1_AM18H, val)
379#define bfin_read_CAN1_AM19L() bfin_read16(CAN1_AM19L)
380#define bfin_write_CAN1_AM19L(val) bfin_write16(CAN1_AM19L, val)
381#define bfin_read_CAN1_AM19H() bfin_read16(CAN1_AM19H)
382#define bfin_write_CAN1_AM19H(val) bfin_write16(CAN1_AM19H, val)
383#define bfin_read_CAN1_AM20L() bfin_read16(CAN1_AM20L)
384#define bfin_write_CAN1_AM20L(val) bfin_write16(CAN1_AM20L, val)
385#define bfin_read_CAN1_AM20H() bfin_read16(CAN1_AM20H)
386#define bfin_write_CAN1_AM20H(val) bfin_write16(CAN1_AM20H, val)
387#define bfin_read_CAN1_AM21L() bfin_read16(CAN1_AM21L)
388#define bfin_write_CAN1_AM21L(val) bfin_write16(CAN1_AM21L, val)
389#define bfin_read_CAN1_AM21H() bfin_read16(CAN1_AM21H)
390#define bfin_write_CAN1_AM21H(val) bfin_write16(CAN1_AM21H, val)
391#define bfin_read_CAN1_AM22L() bfin_read16(CAN1_AM22L)
392#define bfin_write_CAN1_AM22L(val) bfin_write16(CAN1_AM22L, val)
393#define bfin_read_CAN1_AM22H() bfin_read16(CAN1_AM22H)
394#define bfin_write_CAN1_AM22H(val) bfin_write16(CAN1_AM22H, val)
395#define bfin_read_CAN1_AM23L() bfin_read16(CAN1_AM23L)
396#define bfin_write_CAN1_AM23L(val) bfin_write16(CAN1_AM23L, val)
397#define bfin_read_CAN1_AM23H() bfin_read16(CAN1_AM23H)
398#define bfin_write_CAN1_AM23H(val) bfin_write16(CAN1_AM23H, val)
399#define bfin_read_CAN1_AM24L() bfin_read16(CAN1_AM24L)
400#define bfin_write_CAN1_AM24L(val) bfin_write16(CAN1_AM24L, val)
401#define bfin_read_CAN1_AM24H() bfin_read16(CAN1_AM24H)
402#define bfin_write_CAN1_AM24H(val) bfin_write16(CAN1_AM24H, val)
403#define bfin_read_CAN1_AM25L() bfin_read16(CAN1_AM25L)
404#define bfin_write_CAN1_AM25L(val) bfin_write16(CAN1_AM25L, val)
405#define bfin_read_CAN1_AM25H() bfin_read16(CAN1_AM25H)
406#define bfin_write_CAN1_AM25H(val) bfin_write16(CAN1_AM25H, val)
407#define bfin_read_CAN1_AM26L() bfin_read16(CAN1_AM26L)
408#define bfin_write_CAN1_AM26L(val) bfin_write16(CAN1_AM26L, val)
409#define bfin_read_CAN1_AM26H() bfin_read16(CAN1_AM26H)
410#define bfin_write_CAN1_AM26H(val) bfin_write16(CAN1_AM26H, val)
411#define bfin_read_CAN1_AM27L() bfin_read16(CAN1_AM27L)
412#define bfin_write_CAN1_AM27L(val) bfin_write16(CAN1_AM27L, val)
413#define bfin_read_CAN1_AM27H() bfin_read16(CAN1_AM27H)
414#define bfin_write_CAN1_AM27H(val) bfin_write16(CAN1_AM27H, val)
415#define bfin_read_CAN1_AM28L() bfin_read16(CAN1_AM28L)
416#define bfin_write_CAN1_AM28L(val) bfin_write16(CAN1_AM28L, val)
417#define bfin_read_CAN1_AM28H() bfin_read16(CAN1_AM28H)
418#define bfin_write_CAN1_AM28H(val) bfin_write16(CAN1_AM28H, val)
419#define bfin_read_CAN1_AM29L() bfin_read16(CAN1_AM29L)
420#define bfin_write_CAN1_AM29L(val) bfin_write16(CAN1_AM29L, val)
421#define bfin_read_CAN1_AM29H() bfin_read16(CAN1_AM29H)
422#define bfin_write_CAN1_AM29H(val) bfin_write16(CAN1_AM29H, val)
423#define bfin_read_CAN1_AM30L() bfin_read16(CAN1_AM30L)
424#define bfin_write_CAN1_AM30L(val) bfin_write16(CAN1_AM30L, val)
425#define bfin_read_CAN1_AM30H() bfin_read16(CAN1_AM30H)
426#define bfin_write_CAN1_AM30H(val) bfin_write16(CAN1_AM30H, val)
427#define bfin_read_CAN1_AM31L() bfin_read16(CAN1_AM31L)
428#define bfin_write_CAN1_AM31L(val) bfin_write16(CAN1_AM31L, val)
429#define bfin_read_CAN1_AM31H() bfin_read16(CAN1_AM31H)
430#define bfin_write_CAN1_AM31H(val) bfin_write16(CAN1_AM31H, val)
431
432/* CAN Controller 1 Mailbox Data Registers */
433
434#define bfin_read_CAN1_MB00_DATA0() bfin_read16(CAN1_MB00_DATA0)
435#define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val)
436#define bfin_read_CAN1_MB00_DATA1() bfin_read16(CAN1_MB00_DATA1)
437#define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val)
438#define bfin_read_CAN1_MB00_DATA2() bfin_read16(CAN1_MB00_DATA2)
439#define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val)
440#define bfin_read_CAN1_MB00_DATA3() bfin_read16(CAN1_MB00_DATA3)
441#define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val)
442#define bfin_read_CAN1_MB00_LENGTH() bfin_read16(CAN1_MB00_LENGTH)
443#define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val)
444#define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP)
445#define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val)
446#define bfin_read_CAN1_MB00_ID0() bfin_read16(CAN1_MB00_ID0)
447#define bfin_write_CAN1_MB00_ID0(val) bfin_write16(CAN1_MB00_ID0, val)
448#define bfin_read_CAN1_MB00_ID1() bfin_read16(CAN1_MB00_ID1)
449#define bfin_write_CAN1_MB00_ID1(val) bfin_write16(CAN1_MB00_ID1, val)
450#define bfin_read_CAN1_MB01_DATA0() bfin_read16(CAN1_MB01_DATA0)
451#define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val)
452#define bfin_read_CAN1_MB01_DATA1() bfin_read16(CAN1_MB01_DATA1)
453#define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val)
454#define bfin_read_CAN1_MB01_DATA2() bfin_read16(CAN1_MB01_DATA2)
455#define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val)
456#define bfin_read_CAN1_MB01_DATA3() bfin_read16(CAN1_MB01_DATA3)
457#define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val)
458#define bfin_read_CAN1_MB01_LENGTH() bfin_read16(CAN1_MB01_LENGTH)
459#define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val)
460#define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP)
461#define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val)
462#define bfin_read_CAN1_MB01_ID0() bfin_read16(CAN1_MB01_ID0)
463#define bfin_write_CAN1_MB01_ID0(val) bfin_write16(CAN1_MB01_ID0, val)
464#define bfin_read_CAN1_MB01_ID1() bfin_read16(CAN1_MB01_ID1)
465#define bfin_write_CAN1_MB01_ID1(val) bfin_write16(CAN1_MB01_ID1, val)
466#define bfin_read_CAN1_MB02_DATA0() bfin_read16(CAN1_MB02_DATA0)
467#define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val)
468#define bfin_read_CAN1_MB02_DATA1() bfin_read16(CAN1_MB02_DATA1)
469#define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val)
470#define bfin_read_CAN1_MB02_DATA2() bfin_read16(CAN1_MB02_DATA2)
471#define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val)
472#define bfin_read_CAN1_MB02_DATA3() bfin_read16(CAN1_MB02_DATA3)
473#define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val)
474#define bfin_read_CAN1_MB02_LENGTH() bfin_read16(CAN1_MB02_LENGTH)
475#define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val)
476#define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP)
477#define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val)
478#define bfin_read_CAN1_MB02_ID0() bfin_read16(CAN1_MB02_ID0)
479#define bfin_write_CAN1_MB02_ID0(val) bfin_write16(CAN1_MB02_ID0, val)
480#define bfin_read_CAN1_MB02_ID1() bfin_read16(CAN1_MB02_ID1)
481#define bfin_write_CAN1_MB02_ID1(val) bfin_write16(CAN1_MB02_ID1, val)
482#define bfin_read_CAN1_MB03_DATA0() bfin_read16(CAN1_MB03_DATA0)
483#define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val)
484#define bfin_read_CAN1_MB03_DATA1() bfin_read16(CAN1_MB03_DATA1)
485#define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val)
486#define bfin_read_CAN1_MB03_DATA2() bfin_read16(CAN1_MB03_DATA2)
487#define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val)
488#define bfin_read_CAN1_MB03_DATA3() bfin_read16(CAN1_MB03_DATA3)
489#define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val)
490#define bfin_read_CAN1_MB03_LENGTH() bfin_read16(CAN1_MB03_LENGTH)
491#define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val)
492#define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP)
493#define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val)
494#define bfin_read_CAN1_MB03_ID0() bfin_read16(CAN1_MB03_ID0)
495#define bfin_write_CAN1_MB03_ID0(val) bfin_write16(CAN1_MB03_ID0, val)
496#define bfin_read_CAN1_MB03_ID1() bfin_read16(CAN1_MB03_ID1)
497#define bfin_write_CAN1_MB03_ID1(val) bfin_write16(CAN1_MB03_ID1, val)
498#define bfin_read_CAN1_MB04_DATA0() bfin_read16(CAN1_MB04_DATA0)
499#define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val)
500#define bfin_read_CAN1_MB04_DATA1() bfin_read16(CAN1_MB04_DATA1)
501#define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val)
502#define bfin_read_CAN1_MB04_DATA2() bfin_read16(CAN1_MB04_DATA2)
503#define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val)
504#define bfin_read_CAN1_MB04_DATA3() bfin_read16(CAN1_MB04_DATA3)
505#define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val)
506#define bfin_read_CAN1_MB04_LENGTH() bfin_read16(CAN1_MB04_LENGTH)
507#define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val)
508#define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP)
509#define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val)
510#define bfin_read_CAN1_MB04_ID0() bfin_read16(CAN1_MB04_ID0)
511#define bfin_write_CAN1_MB04_ID0(val) bfin_write16(CAN1_MB04_ID0, val)
512#define bfin_read_CAN1_MB04_ID1() bfin_read16(CAN1_MB04_ID1)
513#define bfin_write_CAN1_MB04_ID1(val) bfin_write16(CAN1_MB04_ID1, val)
514#define bfin_read_CAN1_MB05_DATA0() bfin_read16(CAN1_MB05_DATA0)
515#define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val)
516#define bfin_read_CAN1_MB05_DATA1() bfin_read16(CAN1_MB05_DATA1)
517#define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val)
518#define bfin_read_CAN1_MB05_DATA2() bfin_read16(CAN1_MB05_DATA2)
519#define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val)
520#define bfin_read_CAN1_MB05_DATA3() bfin_read16(CAN1_MB05_DATA3)
521#define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val)
522#define bfin_read_CAN1_MB05_LENGTH() bfin_read16(CAN1_MB05_LENGTH)
523#define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val)
524#define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP)
525#define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val)
526#define bfin_read_CAN1_MB05_ID0() bfin_read16(CAN1_MB05_ID0)
527#define bfin_write_CAN1_MB05_ID0(val) bfin_write16(CAN1_MB05_ID0, val)
528#define bfin_read_CAN1_MB05_ID1() bfin_read16(CAN1_MB05_ID1)
529#define bfin_write_CAN1_MB05_ID1(val) bfin_write16(CAN1_MB05_ID1, val)
530#define bfin_read_CAN1_MB06_DATA0() bfin_read16(CAN1_MB06_DATA0)
531#define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val)
532#define bfin_read_CAN1_MB06_DATA1() bfin_read16(CAN1_MB06_DATA1)
533#define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val)
534#define bfin_read_CAN1_MB06_DATA2() bfin_read16(CAN1_MB06_DATA2)
535#define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val)
536#define bfin_read_CAN1_MB06_DATA3() bfin_read16(CAN1_MB06_DATA3)
537#define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val)
538#define bfin_read_CAN1_MB06_LENGTH() bfin_read16(CAN1_MB06_LENGTH)
539#define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val)
540#define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP)
541#define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val)
542#define bfin_read_CAN1_MB06_ID0() bfin_read16(CAN1_MB06_ID0)
543#define bfin_write_CAN1_MB06_ID0(val) bfin_write16(CAN1_MB06_ID0, val)
544#define bfin_read_CAN1_MB06_ID1() bfin_read16(CAN1_MB06_ID1)
545#define bfin_write_CAN1_MB06_ID1(val) bfin_write16(CAN1_MB06_ID1, val)
546#define bfin_read_CAN1_MB07_DATA0() bfin_read16(CAN1_MB07_DATA0)
547#define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val)
548#define bfin_read_CAN1_MB07_DATA1() bfin_read16(CAN1_MB07_DATA1)
549#define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val)
550#define bfin_read_CAN1_MB07_DATA2() bfin_read16(CAN1_MB07_DATA2)
551#define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val)
552#define bfin_read_CAN1_MB07_DATA3() bfin_read16(CAN1_MB07_DATA3)
553#define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val)
554#define bfin_read_CAN1_MB07_LENGTH() bfin_read16(CAN1_MB07_LENGTH)
555#define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val)
556#define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP)
557#define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val)
558#define bfin_read_CAN1_MB07_ID0() bfin_read16(CAN1_MB07_ID0)
559#define bfin_write_CAN1_MB07_ID0(val) bfin_write16(CAN1_MB07_ID0, val)
560#define bfin_read_CAN1_MB07_ID1() bfin_read16(CAN1_MB07_ID1)
561#define bfin_write_CAN1_MB07_ID1(val) bfin_write16(CAN1_MB07_ID1, val)
562#define bfin_read_CAN1_MB08_DATA0() bfin_read16(CAN1_MB08_DATA0)
563#define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val)
564#define bfin_read_CAN1_MB08_DATA1() bfin_read16(CAN1_MB08_DATA1)
565#define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val)
566#define bfin_read_CAN1_MB08_DATA2() bfin_read16(CAN1_MB08_DATA2)
567#define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val)
568#define bfin_read_CAN1_MB08_DATA3() bfin_read16(CAN1_MB08_DATA3)
569#define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val)
570#define bfin_read_CAN1_MB08_LENGTH() bfin_read16(CAN1_MB08_LENGTH)
571#define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val)
572#define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP)
573#define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val)
574#define bfin_read_CAN1_MB08_ID0() bfin_read16(CAN1_MB08_ID0)
575#define bfin_write_CAN1_MB08_ID0(val) bfin_write16(CAN1_MB08_ID0, val)
576#define bfin_read_CAN1_MB08_ID1() bfin_read16(CAN1_MB08_ID1)
577#define bfin_write_CAN1_MB08_ID1(val) bfin_write16(CAN1_MB08_ID1, val)
578#define bfin_read_CAN1_MB09_DATA0() bfin_read16(CAN1_MB09_DATA0)
579#define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val)
580#define bfin_read_CAN1_MB09_DATA1() bfin_read16(CAN1_MB09_DATA1)
581#define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val)
582#define bfin_read_CAN1_MB09_DATA2() bfin_read16(CAN1_MB09_DATA2)
583#define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val)
584#define bfin_read_CAN1_MB09_DATA3() bfin_read16(CAN1_MB09_DATA3)
585#define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val)
586#define bfin_read_CAN1_MB09_LENGTH() bfin_read16(CAN1_MB09_LENGTH)
587#define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val)
588#define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP)
589#define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val)
590#define bfin_read_CAN1_MB09_ID0() bfin_read16(CAN1_MB09_ID0)
591#define bfin_write_CAN1_MB09_ID0(val) bfin_write16(CAN1_MB09_ID0, val)
592#define bfin_read_CAN1_MB09_ID1() bfin_read16(CAN1_MB09_ID1)
593#define bfin_write_CAN1_MB09_ID1(val) bfin_write16(CAN1_MB09_ID1, val)
594#define bfin_read_CAN1_MB10_DATA0() bfin_read16(CAN1_MB10_DATA0)
595#define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val)
596#define bfin_read_CAN1_MB10_DATA1() bfin_read16(CAN1_MB10_DATA1)
597#define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val)
598#define bfin_read_CAN1_MB10_DATA2() bfin_read16(CAN1_MB10_DATA2)
599#define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val)
600#define bfin_read_CAN1_MB10_DATA3() bfin_read16(CAN1_MB10_DATA3)
601#define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val)
602#define bfin_read_CAN1_MB10_LENGTH() bfin_read16(CAN1_MB10_LENGTH)
603#define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val)
604#define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP)
605#define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val)
606#define bfin_read_CAN1_MB10_ID0() bfin_read16(CAN1_MB10_ID0)
607#define bfin_write_CAN1_MB10_ID0(val) bfin_write16(CAN1_MB10_ID0, val)
608#define bfin_read_CAN1_MB10_ID1() bfin_read16(CAN1_MB10_ID1)
609#define bfin_write_CAN1_MB10_ID1(val) bfin_write16(CAN1_MB10_ID1, val)
610#define bfin_read_CAN1_MB11_DATA0() bfin_read16(CAN1_MB11_DATA0)
611#define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val)
612#define bfin_read_CAN1_MB11_DATA1() bfin_read16(CAN1_MB11_DATA1)
613#define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val)
614#define bfin_read_CAN1_MB11_DATA2() bfin_read16(CAN1_MB11_DATA2)
615#define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val)
616#define bfin_read_CAN1_MB11_DATA3() bfin_read16(CAN1_MB11_DATA3)
617#define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val)
618#define bfin_read_CAN1_MB11_LENGTH() bfin_read16(CAN1_MB11_LENGTH)
619#define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val)
620#define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP)
621#define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val)
622#define bfin_read_CAN1_MB11_ID0() bfin_read16(CAN1_MB11_ID0)
623#define bfin_write_CAN1_MB11_ID0(val) bfin_write16(CAN1_MB11_ID0, val)
624#define bfin_read_CAN1_MB11_ID1() bfin_read16(CAN1_MB11_ID1)
625#define bfin_write_CAN1_MB11_ID1(val) bfin_write16(CAN1_MB11_ID1, val)
626#define bfin_read_CAN1_MB12_DATA0() bfin_read16(CAN1_MB12_DATA0)
627#define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val)
628#define bfin_read_CAN1_MB12_DATA1() bfin_read16(CAN1_MB12_DATA1)
629#define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val)
630#define bfin_read_CAN1_MB12_DATA2() bfin_read16(CAN1_MB12_DATA2)
631#define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val)
632#define bfin_read_CAN1_MB12_DATA3() bfin_read16(CAN1_MB12_DATA3)
633#define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val)
634#define bfin_read_CAN1_MB12_LENGTH() bfin_read16(CAN1_MB12_LENGTH)
635#define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val)
636#define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP)
637#define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val)
638#define bfin_read_CAN1_MB12_ID0() bfin_read16(CAN1_MB12_ID0)
639#define bfin_write_CAN1_MB12_ID0(val) bfin_write16(CAN1_MB12_ID0, val)
640#define bfin_read_CAN1_MB12_ID1() bfin_read16(CAN1_MB12_ID1)
641#define bfin_write_CAN1_MB12_ID1(val) bfin_write16(CAN1_MB12_ID1, val)
642#define bfin_read_CAN1_MB13_DATA0() bfin_read16(CAN1_MB13_DATA0)
643#define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val)
644#define bfin_read_CAN1_MB13_DATA1() bfin_read16(CAN1_MB13_DATA1)
645#define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val)
646#define bfin_read_CAN1_MB13_DATA2() bfin_read16(CAN1_MB13_DATA2)
647#define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val)
648#define bfin_read_CAN1_MB13_DATA3() bfin_read16(CAN1_MB13_DATA3)
649#define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val)
650#define bfin_read_CAN1_MB13_LENGTH() bfin_read16(CAN1_MB13_LENGTH)
651#define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val)
652#define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP)
653#define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val)
654#define bfin_read_CAN1_MB13_ID0() bfin_read16(CAN1_MB13_ID0)
655#define bfin_write_CAN1_MB13_ID0(val) bfin_write16(CAN1_MB13_ID0, val)
656#define bfin_read_CAN1_MB13_ID1() bfin_read16(CAN1_MB13_ID1)
657#define bfin_write_CAN1_MB13_ID1(val) bfin_write16(CAN1_MB13_ID1, val)
658#define bfin_read_CAN1_MB14_DATA0() bfin_read16(CAN1_MB14_DATA0)
659#define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val)
660#define bfin_read_CAN1_MB14_DATA1() bfin_read16(CAN1_MB14_DATA1)
661#define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val)
662#define bfin_read_CAN1_MB14_DATA2() bfin_read16(CAN1_MB14_DATA2)
663#define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val)
664#define bfin_read_CAN1_MB14_DATA3() bfin_read16(CAN1_MB14_DATA3)
665#define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val)
666#define bfin_read_CAN1_MB14_LENGTH() bfin_read16(CAN1_MB14_LENGTH)
667#define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val)
668#define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP)
669#define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val)
670#define bfin_read_CAN1_MB14_ID0() bfin_read16(CAN1_MB14_ID0)
671#define bfin_write_CAN1_MB14_ID0(val) bfin_write16(CAN1_MB14_ID0, val)
672#define bfin_read_CAN1_MB14_ID1() bfin_read16(CAN1_MB14_ID1)
673#define bfin_write_CAN1_MB14_ID1(val) bfin_write16(CAN1_MB14_ID1, val)
674#define bfin_read_CAN1_MB15_DATA0() bfin_read16(CAN1_MB15_DATA0)
675#define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val)
676#define bfin_read_CAN1_MB15_DATA1() bfin_read16(CAN1_MB15_DATA1)
677#define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val)
678#define bfin_read_CAN1_MB15_DATA2() bfin_read16(CAN1_MB15_DATA2)
679#define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val)
680#define bfin_read_CAN1_MB15_DATA3() bfin_read16(CAN1_MB15_DATA3)
681#define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val)
682#define bfin_read_CAN1_MB15_LENGTH() bfin_read16(CAN1_MB15_LENGTH)
683#define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val)
684#define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP)
685#define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val)
686#define bfin_read_CAN1_MB15_ID0() bfin_read16(CAN1_MB15_ID0)
687#define bfin_write_CAN1_MB15_ID0(val) bfin_write16(CAN1_MB15_ID0, val)
688#define bfin_read_CAN1_MB15_ID1() bfin_read16(CAN1_MB15_ID1)
689#define bfin_write_CAN1_MB15_ID1(val) bfin_write16(CAN1_MB15_ID1, val)
690
691/* CAN Controller 1 Mailbox Data Registers */
692
693#define bfin_read_CAN1_MB16_DATA0() bfin_read16(CAN1_MB16_DATA0)
694#define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val)
695#define bfin_read_CAN1_MB16_DATA1() bfin_read16(CAN1_MB16_DATA1)
696#define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val)
697#define bfin_read_CAN1_MB16_DATA2() bfin_read16(CAN1_MB16_DATA2)
698#define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val)
699#define bfin_read_CAN1_MB16_DATA3() bfin_read16(CAN1_MB16_DATA3)
700#define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val)
701#define bfin_read_CAN1_MB16_LENGTH() bfin_read16(CAN1_MB16_LENGTH)
702#define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val)
703#define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP)
704#define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val)
705#define bfin_read_CAN1_MB16_ID0() bfin_read16(CAN1_MB16_ID0)
706#define bfin_write_CAN1_MB16_ID0(val) bfin_write16(CAN1_MB16_ID0, val)
707#define bfin_read_CAN1_MB16_ID1() bfin_read16(CAN1_MB16_ID1)
708#define bfin_write_CAN1_MB16_ID1(val) bfin_write16(CAN1_MB16_ID1, val)
709#define bfin_read_CAN1_MB17_DATA0() bfin_read16(CAN1_MB17_DATA0)
710#define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val)
711#define bfin_read_CAN1_MB17_DATA1() bfin_read16(CAN1_MB17_DATA1)
712#define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val)
713#define bfin_read_CAN1_MB17_DATA2() bfin_read16(CAN1_MB17_DATA2)
714#define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val)
715#define bfin_read_CAN1_MB17_DATA3() bfin_read16(CAN1_MB17_DATA3)
716#define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val)
717#define bfin_read_CAN1_MB17_LENGTH() bfin_read16(CAN1_MB17_LENGTH)
718#define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val)
719#define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP)
720#define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val)
721#define bfin_read_CAN1_MB17_ID0() bfin_read16(CAN1_MB17_ID0)
722#define bfin_write_CAN1_MB17_ID0(val) bfin_write16(CAN1_MB17_ID0, val)
723#define bfin_read_CAN1_MB17_ID1() bfin_read16(CAN1_MB17_ID1)
724#define bfin_write_CAN1_MB17_ID1(val) bfin_write16(CAN1_MB17_ID1, val)
725#define bfin_read_CAN1_MB18_DATA0() bfin_read16(CAN1_MB18_DATA0)
726#define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val)
727#define bfin_read_CAN1_MB18_DATA1() bfin_read16(CAN1_MB18_DATA1)
728#define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val)
729#define bfin_read_CAN1_MB18_DATA2() bfin_read16(CAN1_MB18_DATA2)
730#define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val)
731#define bfin_read_CAN1_MB18_DATA3() bfin_read16(CAN1_MB18_DATA3)
732#define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val)
733#define bfin_read_CAN1_MB18_LENGTH() bfin_read16(CAN1_MB18_LENGTH)
734#define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val)
735#define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP)
736#define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val)
737#define bfin_read_CAN1_MB18_ID0() bfin_read16(CAN1_MB18_ID0)
738#define bfin_write_CAN1_MB18_ID0(val) bfin_write16(CAN1_MB18_ID0, val)
739#define bfin_read_CAN1_MB18_ID1() bfin_read16(CAN1_MB18_ID1)
740#define bfin_write_CAN1_MB18_ID1(val) bfin_write16(CAN1_MB18_ID1, val)
741#define bfin_read_CAN1_MB19_DATA0() bfin_read16(CAN1_MB19_DATA0)
742#define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val)
743#define bfin_read_CAN1_MB19_DATA1() bfin_read16(CAN1_MB19_DATA1)
744#define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val)
745#define bfin_read_CAN1_MB19_DATA2() bfin_read16(CAN1_MB19_DATA2)
746#define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val)
747#define bfin_read_CAN1_MB19_DATA3() bfin_read16(CAN1_MB19_DATA3)
748#define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val)
749#define bfin_read_CAN1_MB19_LENGTH() bfin_read16(CAN1_MB19_LENGTH)
750#define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val)
751#define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP)
752#define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val)
753#define bfin_read_CAN1_MB19_ID0() bfin_read16(CAN1_MB19_ID0)
754#define bfin_write_CAN1_MB19_ID0(val) bfin_write16(CAN1_MB19_ID0, val)
755#define bfin_read_CAN1_MB19_ID1() bfin_read16(CAN1_MB19_ID1)
756#define bfin_write_CAN1_MB19_ID1(val) bfin_write16(CAN1_MB19_ID1, val)
757#define bfin_read_CAN1_MB20_DATA0() bfin_read16(CAN1_MB20_DATA0)
758#define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val)
759#define bfin_read_CAN1_MB20_DATA1() bfin_read16(CAN1_MB20_DATA1)
760#define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val)
761#define bfin_read_CAN1_MB20_DATA2() bfin_read16(CAN1_MB20_DATA2)
762#define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val)
763#define bfin_read_CAN1_MB20_DATA3() bfin_read16(CAN1_MB20_DATA3)
764#define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val)
765#define bfin_read_CAN1_MB20_LENGTH() bfin_read16(CAN1_MB20_LENGTH)
766#define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val)
767#define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP)
768#define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val)
769#define bfin_read_CAN1_MB20_ID0() bfin_read16(CAN1_MB20_ID0)
770#define bfin_write_CAN1_MB20_ID0(val) bfin_write16(CAN1_MB20_ID0, val)
771#define bfin_read_CAN1_MB20_ID1() bfin_read16(CAN1_MB20_ID1)
772#define bfin_write_CAN1_MB20_ID1(val) bfin_write16(CAN1_MB20_ID1, val)
773#define bfin_read_CAN1_MB21_DATA0() bfin_read16(CAN1_MB21_DATA0)
774#define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val)
775#define bfin_read_CAN1_MB21_DATA1() bfin_read16(CAN1_MB21_DATA1)
776#define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val)
777#define bfin_read_CAN1_MB21_DATA2() bfin_read16(CAN1_MB21_DATA2)
778#define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val)
779#define bfin_read_CAN1_MB21_DATA3() bfin_read16(CAN1_MB21_DATA3)
780#define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val)
781#define bfin_read_CAN1_MB21_LENGTH() bfin_read16(CAN1_MB21_LENGTH)
782#define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val)
783#define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP)
784#define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val)
785#define bfin_read_CAN1_MB21_ID0() bfin_read16(CAN1_MB21_ID0)
786#define bfin_write_CAN1_MB21_ID0(val) bfin_write16(CAN1_MB21_ID0, val)
787#define bfin_read_CAN1_MB21_ID1() bfin_read16(CAN1_MB21_ID1)
788#define bfin_write_CAN1_MB21_ID1(val) bfin_write16(CAN1_MB21_ID1, val)
789#define bfin_read_CAN1_MB22_DATA0() bfin_read16(CAN1_MB22_DATA0)
790#define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val)
791#define bfin_read_CAN1_MB22_DATA1() bfin_read16(CAN1_MB22_DATA1)
792#define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val)
793#define bfin_read_CAN1_MB22_DATA2() bfin_read16(CAN1_MB22_DATA2)
794#define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val)
795#define bfin_read_CAN1_MB22_DATA3() bfin_read16(CAN1_MB22_DATA3)
796#define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val)
797#define bfin_read_CAN1_MB22_LENGTH() bfin_read16(CAN1_MB22_LENGTH)
798#define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val)
799#define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP)
800#define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val)
801#define bfin_read_CAN1_MB22_ID0() bfin_read16(CAN1_MB22_ID0)
802#define bfin_write_CAN1_MB22_ID0(val) bfin_write16(CAN1_MB22_ID0, val)
803#define bfin_read_CAN1_MB22_ID1() bfin_read16(CAN1_MB22_ID1)
804#define bfin_write_CAN1_MB22_ID1(val) bfin_write16(CAN1_MB22_ID1, val)
805#define bfin_read_CAN1_MB23_DATA0() bfin_read16(CAN1_MB23_DATA0)
806#define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val)
807#define bfin_read_CAN1_MB23_DATA1() bfin_read16(CAN1_MB23_DATA1)
808#define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val)
809#define bfin_read_CAN1_MB23_DATA2() bfin_read16(CAN1_MB23_DATA2)
810#define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val)
811#define bfin_read_CAN1_MB23_DATA3() bfin_read16(CAN1_MB23_DATA3)
812#define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val)
813#define bfin_read_CAN1_MB23_LENGTH() bfin_read16(CAN1_MB23_LENGTH)
814#define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val)
815#define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP)
816#define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val)
817#define bfin_read_CAN1_MB23_ID0() bfin_read16(CAN1_MB23_ID0)
818#define bfin_write_CAN1_MB23_ID0(val) bfin_write16(CAN1_MB23_ID0, val)
819#define bfin_read_CAN1_MB23_ID1() bfin_read16(CAN1_MB23_ID1)
820#define bfin_write_CAN1_MB23_ID1(val) bfin_write16(CAN1_MB23_ID1, val)
821#define bfin_read_CAN1_MB24_DATA0() bfin_read16(CAN1_MB24_DATA0)
822#define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val)
823#define bfin_read_CAN1_MB24_DATA1() bfin_read16(CAN1_MB24_DATA1)
824#define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val)
825#define bfin_read_CAN1_MB24_DATA2() bfin_read16(CAN1_MB24_DATA2)
826#define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val)
827#define bfin_read_CAN1_MB24_DATA3() bfin_read16(CAN1_MB24_DATA3)
828#define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val)
829#define bfin_read_CAN1_MB24_LENGTH() bfin_read16(CAN1_MB24_LENGTH)
830#define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val)
831#define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP)
832#define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val)
833#define bfin_read_CAN1_MB24_ID0() bfin_read16(CAN1_MB24_ID0)
834#define bfin_write_CAN1_MB24_ID0(val) bfin_write16(CAN1_MB24_ID0, val)
835#define bfin_read_CAN1_MB24_ID1() bfin_read16(CAN1_MB24_ID1)
836#define bfin_write_CAN1_MB24_ID1(val) bfin_write16(CAN1_MB24_ID1, val)
837#define bfin_read_CAN1_MB25_DATA0() bfin_read16(CAN1_MB25_DATA0)
838#define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val)
839#define bfin_read_CAN1_MB25_DATA1() bfin_read16(CAN1_MB25_DATA1)
840#define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val)
841#define bfin_read_CAN1_MB25_DATA2() bfin_read16(CAN1_MB25_DATA2)
842#define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val)
843#define bfin_read_CAN1_MB25_DATA3() bfin_read16(CAN1_MB25_DATA3)
844#define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val)
845#define bfin_read_CAN1_MB25_LENGTH() bfin_read16(CAN1_MB25_LENGTH)
846#define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val)
847#define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP)
848#define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val)
849#define bfin_read_CAN1_MB25_ID0() bfin_read16(CAN1_MB25_ID0)
850#define bfin_write_CAN1_MB25_ID0(val) bfin_write16(CAN1_MB25_ID0, val)
851#define bfin_read_CAN1_MB25_ID1() bfin_read16(CAN1_MB25_ID1)
852#define bfin_write_CAN1_MB25_ID1(val) bfin_write16(CAN1_MB25_ID1, val)
853#define bfin_read_CAN1_MB26_DATA0() bfin_read16(CAN1_MB26_DATA0)
854#define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val)
855#define bfin_read_CAN1_MB26_DATA1() bfin_read16(CAN1_MB26_DATA1)
856#define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val)
857#define bfin_read_CAN1_MB26_DATA2() bfin_read16(CAN1_MB26_DATA2)
858#define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val)
859#define bfin_read_CAN1_MB26_DATA3() bfin_read16(CAN1_MB26_DATA3)
860#define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val)
861#define bfin_read_CAN1_MB26_LENGTH() bfin_read16(CAN1_MB26_LENGTH)
862#define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val)
863#define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP)
864#define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val)
865#define bfin_read_CAN1_MB26_ID0() bfin_read16(CAN1_MB26_ID0)
866#define bfin_write_CAN1_MB26_ID0(val) bfin_write16(CAN1_MB26_ID0, val)
867#define bfin_read_CAN1_MB26_ID1() bfin_read16(CAN1_MB26_ID1)
868#define bfin_write_CAN1_MB26_ID1(val) bfin_write16(CAN1_MB26_ID1, val)
869#define bfin_read_CAN1_MB27_DATA0() bfin_read16(CAN1_MB27_DATA0)
870#define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val)
871#define bfin_read_CAN1_MB27_DATA1() bfin_read16(CAN1_MB27_DATA1)
872#define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val)
873#define bfin_read_CAN1_MB27_DATA2() bfin_read16(CAN1_MB27_DATA2)
874#define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val)
875#define bfin_read_CAN1_MB27_DATA3() bfin_read16(CAN1_MB27_DATA3)
876#define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val)
877#define bfin_read_CAN1_MB27_LENGTH() bfin_read16(CAN1_MB27_LENGTH)
878#define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val)
879#define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP)
880#define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val)
881#define bfin_read_CAN1_MB27_ID0() bfin_read16(CAN1_MB27_ID0)
882#define bfin_write_CAN1_MB27_ID0(val) bfin_write16(CAN1_MB27_ID0, val)
883#define bfin_read_CAN1_MB27_ID1() bfin_read16(CAN1_MB27_ID1)
884#define bfin_write_CAN1_MB27_ID1(val) bfin_write16(CAN1_MB27_ID1, val)
885#define bfin_read_CAN1_MB28_DATA0() bfin_read16(CAN1_MB28_DATA0)
886#define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val)
887#define bfin_read_CAN1_MB28_DATA1() bfin_read16(CAN1_MB28_DATA1)
888#define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val)
889#define bfin_read_CAN1_MB28_DATA2() bfin_read16(CAN1_MB28_DATA2)
890#define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val)
891#define bfin_read_CAN1_MB28_DATA3() bfin_read16(CAN1_MB28_DATA3)
892#define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val)
893#define bfin_read_CAN1_MB28_LENGTH() bfin_read16(CAN1_MB28_LENGTH)
894#define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val)
895#define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP)
896#define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val)
897#define bfin_read_CAN1_MB28_ID0() bfin_read16(CAN1_MB28_ID0)
898#define bfin_write_CAN1_MB28_ID0(val) bfin_write16(CAN1_MB28_ID0, val)
899#define bfin_read_CAN1_MB28_ID1() bfin_read16(CAN1_MB28_ID1)
900#define bfin_write_CAN1_MB28_ID1(val) bfin_write16(CAN1_MB28_ID1, val)
901#define bfin_read_CAN1_MB29_DATA0() bfin_read16(CAN1_MB29_DATA0)
902#define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val)
903#define bfin_read_CAN1_MB29_DATA1() bfin_read16(CAN1_MB29_DATA1)
904#define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val)
905#define bfin_read_CAN1_MB29_DATA2() bfin_read16(CAN1_MB29_DATA2)
906#define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val)
907#define bfin_read_CAN1_MB29_DATA3() bfin_read16(CAN1_MB29_DATA3)
908#define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val)
909#define bfin_read_CAN1_MB29_LENGTH() bfin_read16(CAN1_MB29_LENGTH)
910#define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val)
911#define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP)
912#define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val)
913#define bfin_read_CAN1_MB29_ID0() bfin_read16(CAN1_MB29_ID0)
914#define bfin_write_CAN1_MB29_ID0(val) bfin_write16(CAN1_MB29_ID0, val)
915#define bfin_read_CAN1_MB29_ID1() bfin_read16(CAN1_MB29_ID1)
916#define bfin_write_CAN1_MB29_ID1(val) bfin_write16(CAN1_MB29_ID1, val)
917#define bfin_read_CAN1_MB30_DATA0() bfin_read16(CAN1_MB30_DATA0)
918#define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val)
919#define bfin_read_CAN1_MB30_DATA1() bfin_read16(CAN1_MB30_DATA1)
920#define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val)
921#define bfin_read_CAN1_MB30_DATA2() bfin_read16(CAN1_MB30_DATA2)
922#define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val)
923#define bfin_read_CAN1_MB30_DATA3() bfin_read16(CAN1_MB30_DATA3)
924#define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val)
925#define bfin_read_CAN1_MB30_LENGTH() bfin_read16(CAN1_MB30_LENGTH)
926#define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val)
927#define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP)
928#define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val)
929#define bfin_read_CAN1_MB30_ID0() bfin_read16(CAN1_MB30_ID0)
930#define bfin_write_CAN1_MB30_ID0(val) bfin_write16(CAN1_MB30_ID0, val)
931#define bfin_read_CAN1_MB30_ID1() bfin_read16(CAN1_MB30_ID1)
932#define bfin_write_CAN1_MB30_ID1(val) bfin_write16(CAN1_MB30_ID1, val)
933#define bfin_read_CAN1_MB31_DATA0() bfin_read16(CAN1_MB31_DATA0)
934#define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val)
935#define bfin_read_CAN1_MB31_DATA1() bfin_read16(CAN1_MB31_DATA1)
936#define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val)
937#define bfin_read_CAN1_MB31_DATA2() bfin_read16(CAN1_MB31_DATA2)
938#define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val)
939#define bfin_read_CAN1_MB31_DATA3() bfin_read16(CAN1_MB31_DATA3)
940#define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val)
941#define bfin_read_CAN1_MB31_LENGTH() bfin_read16(CAN1_MB31_LENGTH)
942#define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val)
943#define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP)
944#define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val)
945#define bfin_read_CAN1_MB31_ID0() bfin_read16(CAN1_MB31_ID0)
946#define bfin_write_CAN1_MB31_ID0(val) bfin_write16(CAN1_MB31_ID0, val)
947#define bfin_read_CAN1_MB31_ID1() bfin_read16(CAN1_MB31_ID1)
948#define bfin_write_CAN1_MB31_ID1(val) bfin_write16(CAN1_MB31_ID1, val)
949
950/* ATAPI Registers */
951
952#define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL)
953#define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val)
954#define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS)
955#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val)
956#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR)
957#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
958#define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF)
959#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
960#define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF)
961#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
962#define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK)
963#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
964#define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS)
965#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
966#define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN)
967#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
968#define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS)
969#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
970#define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE)
971#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
972#define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE)
973#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
974#define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT)
975#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
976#define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT)
977#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
978#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT)
979#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
980#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT)
981#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
982#define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0)
983#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
984#define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0)
985#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
986#define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1)
987#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
988#define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0)
989#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
990#define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1)
991#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
992#define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2)
993#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
994#define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0)
995#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
996#define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1)
997#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
998#define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2)
999#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
1000#define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3)
1001#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
1002
1003/* SDH Registers */
1004
1005#define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL)
1006#define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val)
1007#define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL)
1008#define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val)
1009#define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT)
1010#define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val)
1011#define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND)
1012#define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val)
1013#define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD)
1014#define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val)
1015#define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0)
1016#define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val)
1017#define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1)
1018#define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val)
1019#define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2)
1020#define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val)
1021#define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3)
1022#define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val)
1023#define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER)
1024#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
1025#define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH)
1026#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val)
1027#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL)
1028#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val)
1029#define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT)
1030#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val)
1031#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS)
1032#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val)
1033#define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR)
1034#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val)
1035#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0)
1036#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val)
1037#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1)
1038#define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val)
1039#define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT)
1040#define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val)
1041#define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO)
1042#define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val)
1043#define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS)
1044#define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val)
1045#define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK)
1046#define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val)
1047#define bfin_read_SDH_CFG() bfin_read16(SDH_CFG)
1048#define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val)
1049#define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN)
1050#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
1051#define bfin_read_SDH_PID0() bfin_read16(SDH_PID0)
1052#define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val)
1053#define bfin_read_SDH_PID1() bfin_read16(SDH_PID1)
1054#define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val)
1055#define bfin_read_SDH_PID2() bfin_read16(SDH_PID2)
1056#define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val)
1057#define bfin_read_SDH_PID3() bfin_read16(SDH_PID3)
1058#define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val)
1059#define bfin_read_SDH_PID4() bfin_read16(SDH_PID4)
1060#define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val)
1061#define bfin_read_SDH_PID5() bfin_read16(SDH_PID5)
1062#define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val)
1063#define bfin_read_SDH_PID6() bfin_read16(SDH_PID6)
1064#define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val)
1065#define bfin_read_SDH_PID7() bfin_read16(SDH_PID7)
1066#define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val)
1067
1068/* HOST Port Registers */
1069
1070#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
1071#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
1072#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
1073#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
1074#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
1075#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
1076
1077/* USB Control Registers */
1078
1079#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
1080#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
1081#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
1082#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
1083#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
1084#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
1085#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
1086#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
1087#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
1088#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
1089#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
1090#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
1091#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
1092#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
1093#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
1094#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
1095#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
1096#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
1097#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
1098#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
1099#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
1100#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
1101#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
1102#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
1103#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
1104#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
1105
1106/* USB Packet Control Registers */
1107
1108#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
1109#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
1110#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
1111#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
1112#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
1113#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
1114#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
1115#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
1116#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
1117#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
1118#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
1119#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
1120#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
1121#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
1122#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
1123#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
1124#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
1125#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
1126#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
1127#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
1128#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
1129#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
1130#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
1131#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
1132#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
1133#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
1134
1135/* USB Endbfin_read_()oint FIFO Registers */
1136
1137#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
1138#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
1139#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
1140#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
1141#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
1142#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
1143#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
1144#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
1145#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
1146#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
1147#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
1148#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
1149#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
1150#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
1151#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
1152#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
1153
1154/* USB OTG Control Registers */
1155
1156#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
1157#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
1158#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
1159#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
1160#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
1161#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
1162
1163/* USB Phy Control Registers */
1164
1165#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
1166#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
1167#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
1168#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
1169#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
1170#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
1171#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
1172#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
1173#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
1174#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
1175
1176/* (APHY_CNTRL is for ADI usage only) */
1177
1178#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
1179#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
1180
1181/* (APHY_CALIB is for ADI usage only) */
1182
1183#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
1184#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
1185#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
1186#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
1187
1188/* (PHY_TEST is for ADI usage only) */
1189
1190#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST)
1191#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val)
1192#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
1193#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
1194#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
1195#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
1196
1197/* USB Endbfin_read_()oint 0 Control Registers */
1198
1199#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
1200#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
1201#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
1202#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
1203#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
1204#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
1205#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
1206#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
1207#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
1208#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
1209#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
1210#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
1211#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
1212#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
1213#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
1214#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
1215#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
1216#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
1217
1218/* USB Endbfin_read_()oint 1 Control Registers */
1219
1220#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
1221#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
1222#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
1223#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
1224#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
1225#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
1226#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
1227#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
1228#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
1229#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
1230#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
1231#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
1232#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
1233#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
1234#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
1235#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
1236#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
1237#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
1238#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
1239#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
1240
1241/* USB Endbfin_read_()oint 2 Control Registers */
1242
1243#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
1244#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
1245#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
1246#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
1247#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
1248#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
1249#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
1250#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
1251#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
1252#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
1253#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
1254#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
1255#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
1256#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
1257#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
1258#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
1259#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
1260#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
1261#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
1262#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
1263
1264/* USB Endbfin_read_()oint 3 Control Registers */
1265
1266#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
1267#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
1268#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
1269#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
1270#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
1271#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
1272#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
1273#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
1274#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
1275#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
1276#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
1277#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
1278#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
1279#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
1280#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
1281#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
1282#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
1283#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
1284#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
1285#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
1286
1287/* USB Endbfin_read_()oint 4 Control Registers */
1288
1289#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
1290#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
1291#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
1292#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
1293#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
1294#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
1295#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
1296#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
1297#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
1298#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
1299#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
1300#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
1301#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
1302#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
1303#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
1304#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
1305#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
1306#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
1307#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
1308#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
1309
1310/* USB Endbfin_read_()oint 5 Control Registers */
1311
1312#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
1313#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
1314#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
1315#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
1316#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
1317#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
1318#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
1319#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
1320#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
1321#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
1322#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
1323#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
1324#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
1325#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
1326#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
1327#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
1328#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
1329#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
1330#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
1331#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
1332
1333/* USB Endbfin_read_()oint 6 Control Registers */
1334
1335#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
1336#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
1337#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
1338#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
1339#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
1340#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
1341#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
1342#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
1343#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
1344#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
1345#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
1346#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
1347#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
1348#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
1349#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
1350#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
1351#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
1352#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
1353#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
1354#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
1355
1356/* USB Endbfin_read_()oint 7 Control Registers */
1357
1358#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
1359#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
1360#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
1361#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
1362#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
1363#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
1364#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
1365#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
1366#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
1367#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
1368#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
1369#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
1370#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
1371#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
1372#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
1373#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
1374#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
1375#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
1376#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
1377#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
1378#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
1379#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
1380#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
1381#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
1382
1383/* USB Channel 0 Config Registers */
1384
1385#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL)
1386#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val)
1387#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW)
1388#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val)
1389#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH)
1390#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val)
1391#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW)
1392#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val)
1393#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH)
1394#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val)
1395
1396/* USB Channel 1 Config Registers */
1397
1398#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL)
1399#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val)
1400#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW)
1401#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val)
1402#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH)
1403#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val)
1404#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW)
1405#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val)
1406#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH)
1407#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val)
1408
1409/* USB Channel 2 Config Registers */
1410
1411#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL)
1412#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val)
1413#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW)
1414#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val)
1415#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH)
1416#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val)
1417#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW)
1418#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val)
1419#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH)
1420#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val)
1421
1422/* USB Channel 3 Config Registers */
1423
1424#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL)
1425#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val)
1426#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW)
1427#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val)
1428#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH)
1429#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val)
1430#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW)
1431#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val)
1432#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH)
1433#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val)
1434
1435/* USB Channel 4 Config Registers */
1436
1437#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL)
1438#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val)
1439#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW)
1440#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val)
1441#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH)
1442#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val)
1443#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW)
1444#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val)
1445#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH)
1446#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val)
1447
1448/* USB Channel 5 Config Registers */
1449
1450#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL)
1451#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val)
1452#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW)
1453#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val)
1454#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH)
1455#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val)
1456#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW)
1457#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val)
1458#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH)
1459#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val)
1460
1461/* USB Channel 6 Config Registers */
1462
1463#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL)
1464#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val)
1465#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW)
1466#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val)
1467#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH)
1468#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val)
1469#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW)
1470#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val)
1471#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH)
1472#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val)
1473
1474/* USB Channel 7 Config Registers */
1475
1476#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL)
1477#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val)
1478#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW)
1479#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val)
1480#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH)
1481#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val)
1482#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW)
1483#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val)
1484#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH)
1485#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val)
1486
1487/* Keybfin_read_()ad Registers */
1488
1489#define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL)
1490#define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val)
1491#define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE)
1492#define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val)
1493#define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL)
1494#define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val)
1495#define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL)
1496#define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val)
1497#define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT)
1498#define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val)
1499#define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL)
1500#define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val)
1501
1502/* Pixel Combfin_read_()ositor (PIXC) Registers */
1503
1504#define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL)
1505#define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val)
1506#define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL)
1507#define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val)
1508#define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF)
1509#define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val)
1510#define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART)
1511#define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val)
1512#define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND)
1513#define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val)
1514#define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART)
1515#define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val)
1516#define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND)
1517#define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val)
1518#define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP)
1519#define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val)
1520#define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART)
1521#define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val)
1522#define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND)
1523#define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val)
1524#define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART)
1525#define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val)
1526#define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND)
1527#define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val)
1528#define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP)
1529#define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val)
1530#define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT)
1531#define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val)
1532#define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON)
1533#define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val)
1534#define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON)
1535#define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val)
1536#define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON)
1537#define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val)
1538#define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS)
1539#define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val)
1540#define bfin_read_PIXC_TC() bfin_read32(PIXC_TC)
1541#define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val)
1542
1543/* Handshake MDMA 0 Registers */
1544
1545#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
1546#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
1547#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
1548#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
1549#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
1550#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
1551#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
1552#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
1553#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
1554#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
1555#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
1556#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
1557#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
1558#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
1559
1560/* Handshake MDMA 1 Registers */
1561
1562#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
1563#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
1564#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
1565#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
1566#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
1567#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
1568#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
1569#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
1570#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
1571#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
1572#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
1573#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
1574#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
1575#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
1576
1577#endif /* _CDEF_BF548_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF549.h b/arch/blackfin/mach-bf548/include/mach/cdefBF549.h
new file mode 100644
index 000000000000..ead360b69dea
--- /dev/null
+++ b/arch/blackfin/mach-bf548/include/mach/cdefBF549.h
@@ -0,0 +1,1863 @@
1/*
2 * File: include/asm-blackfin/mach-bf549/cdefBF549.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _CDEF_BF549_H
32#define _CDEF_BF549_H
33
34/* include all Core registers and bit definitions */
35#include "defBF549.h"
36
37/* include core sbfin_read_()ecific register pointer definitions */
38#include <asm/cdef_LPBlackfin.h>
39
40/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF549 */
41
42/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
43#include "cdefBF54x_base.h"
44
45/* The following are the #defines needed by ADSP-BF549 that are not in the common header */
46
47/* Timer Registers */
48
49#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG)
50#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val)
51#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER)
52#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
53#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD)
54#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val)
55#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH)
56#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val)
57#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG)
58#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val)
59#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER)
60#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
61#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD)
62#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val)
63#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH)
64#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val)
65#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG)
66#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
67#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER)
68#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
69#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD)
70#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
71#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH)
72#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val)
73
74/* Timer Groubfin_read_() of 3 */
75
76#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1)
77#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val)
78#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1)
79#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
80#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1)
81#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val)
82
83/* SPORT0 Registers */
84
85#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
86#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
87#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
88#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
89#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
90#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
91#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
92#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
93#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
94#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
95#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
96#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
97#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
98#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
99#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
100#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
101#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
102#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
103#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
104#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
105#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
106#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
107#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
108#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
109#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
110#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
111#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
112#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
113#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
114#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
115#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
116#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
117#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
118#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
119#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
120#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
121#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
122#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
123#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
124#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
125#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
126#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
127#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
128#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
129
130/* EPPI0 Registers */
131
132#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS)
133#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val)
134#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT)
135#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val)
136#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY)
137#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val)
138#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT)
139#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val)
140#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY)
141#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val)
142#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME)
143#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val)
144#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE)
145#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val)
146#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV)
147#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val)
148#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL)
149#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val)
150#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL)
151#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
152#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL)
153#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
154#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB)
155#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
156#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF)
157#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
158#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP)
159#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val)
160
161/* UART2 Registers */
162
163#define bfin_read_UART2_DLL() bfin_read16(UART2_DLL)
164#define bfin_write_UART2_DLL(val) bfin_write16(UART2_DLL, val)
165#define bfin_read_UART2_DLH() bfin_read16(UART2_DLH)
166#define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val)
167#define bfin_read_UART2_GCTL() bfin_read16(UART2_GCTL)
168#define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val)
169#define bfin_read_UART2_LCR() bfin_read16(UART2_LCR)
170#define bfin_write_UART2_LCR(val) bfin_write16(UART2_LCR, val)
171#define bfin_read_UART2_MCR() bfin_read16(UART2_MCR)
172#define bfin_write_UART2_MCR(val) bfin_write16(UART2_MCR, val)
173#define bfin_read_UART2_LSR() bfin_read16(UART2_LSR)
174#define bfin_write_UART2_LSR(val) bfin_write16(UART2_LSR, val)
175#define bfin_read_UART2_MSR() bfin_read16(UART2_MSR)
176#define bfin_write_UART2_MSR(val) bfin_write16(UART2_MSR, val)
177#define bfin_read_UART2_SCR() bfin_read16(UART2_SCR)
178#define bfin_write_UART2_SCR(val) bfin_write16(UART2_SCR, val)
179#define bfin_read_UART2_IER_SET() bfin_read16(UART2_IER_SET)
180#define bfin_write_UART2_IER_SET(val) bfin_write16(UART2_IER_SET, val)
181#define bfin_read_UART2_IER_CLEAR() bfin_read16(UART2_IER_CLEAR)
182#define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val)
183#define bfin_read_UART2_RBR() bfin_read16(UART2_RBR)
184#define bfin_write_UART2_RBR(val) bfin_write16(UART2_RBR, val)
185
186/* Two Wire Interface Registers (TWI1) */
187
188/* SPI2 Registers */
189
190#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL)
191#define bfin_write_SPI2_CTL(val) bfin_write16(SPI2_CTL, val)
192#define bfin_read_SPI2_FLG() bfin_read16(SPI2_FLG)
193#define bfin_write_SPI2_FLG(val) bfin_write16(SPI2_FLG, val)
194#define bfin_read_SPI2_STAT() bfin_read16(SPI2_STAT)
195#define bfin_write_SPI2_STAT(val) bfin_write16(SPI2_STAT, val)
196#define bfin_read_SPI2_TDBR() bfin_read16(SPI2_TDBR)
197#define bfin_write_SPI2_TDBR(val) bfin_write16(SPI2_TDBR, val)
198#define bfin_read_SPI2_RDBR() bfin_read16(SPI2_RDBR)
199#define bfin_write_SPI2_RDBR(val) bfin_write16(SPI2_RDBR, val)
200#define bfin_read_SPI2_BAUD() bfin_read16(SPI2_BAUD)
201#define bfin_write_SPI2_BAUD(val) bfin_write16(SPI2_BAUD, val)
202#define bfin_read_SPI2_SHADOW() bfin_read16(SPI2_SHADOW)
203#define bfin_write_SPI2_SHADOW(val) bfin_write16(SPI2_SHADOW, val)
204
205/* MXVR Registers */
206
207#define bfin_read_MXVR_CONFIG() bfin_read16(MXVR_CONFIG)
208#define bfin_write_MXVR_CONFIG(val) bfin_write16(MXVR_CONFIG, val)
209#define bfin_read_MXVR_STATE_0() bfin_read32(MXVR_STATE_0)
210#define bfin_write_MXVR_STATE_0(val) bfin_write32(MXVR_STATE_0, val)
211#define bfin_read_MXVR_STATE_1() bfin_read32(MXVR_STATE_1)
212#define bfin_write_MXVR_STATE_1(val) bfin_write32(MXVR_STATE_1, val)
213#define bfin_read_MXVR_INT_STAT_0() bfin_read32(MXVR_INT_STAT_0)
214#define bfin_write_MXVR_INT_STAT_0(val) bfin_write32(MXVR_INT_STAT_0, val)
215#define bfin_read_MXVR_INT_STAT_1() bfin_read32(MXVR_INT_STAT_1)
216#define bfin_write_MXVR_INT_STAT_1(val) bfin_write32(MXVR_INT_STAT_1, val)
217#define bfin_read_MXVR_INT_EN_0() bfin_read32(MXVR_INT_EN_0)
218#define bfin_write_MXVR_INT_EN_0(val) bfin_write32(MXVR_INT_EN_0, val)
219#define bfin_read_MXVR_INT_EN_1() bfin_read32(MXVR_INT_EN_1)
220#define bfin_write_MXVR_INT_EN_1(val) bfin_write32(MXVR_INT_EN_1, val)
221#define bfin_read_MXVR_POSITION() bfin_read16(MXVR_POSITION)
222#define bfin_write_MXVR_POSITION(val) bfin_write16(MXVR_POSITION, val)
223#define bfin_read_MXVR_MAX_POSITION() bfin_read16(MXVR_MAX_POSITION)
224#define bfin_write_MXVR_MAX_POSITION(val) bfin_write16(MXVR_MAX_POSITION, val)
225#define bfin_read_MXVR_DELAY() bfin_read16(MXVR_DELAY)
226#define bfin_write_MXVR_DELAY(val) bfin_write16(MXVR_DELAY, val)
227#define bfin_read_MXVR_MAX_DELAY() bfin_read16(MXVR_MAX_DELAY)
228#define bfin_write_MXVR_MAX_DELAY(val) bfin_write16(MXVR_MAX_DELAY, val)
229#define bfin_read_MXVR_LADDR() bfin_read32(MXVR_LADDR)
230#define bfin_write_MXVR_LADDR(val) bfin_write32(MXVR_LADDR, val)
231#define bfin_read_MXVR_GADDR() bfin_read16(MXVR_GADDR)
232#define bfin_write_MXVR_GADDR(val) bfin_write16(MXVR_GADDR, val)
233#define bfin_read_MXVR_AADDR() bfin_read32(MXVR_AADDR)
234#define bfin_write_MXVR_AADDR(val) bfin_write32(MXVR_AADDR, val)
235
236/* MXVR Allocation Table Registers */
237
238#define bfin_read_MXVR_ALLOC_0() bfin_read32(MXVR_ALLOC_0)
239#define bfin_write_MXVR_ALLOC_0(val) bfin_write32(MXVR_ALLOC_0, val)
240#define bfin_read_MXVR_ALLOC_1() bfin_read32(MXVR_ALLOC_1)
241#define bfin_write_MXVR_ALLOC_1(val) bfin_write32(MXVR_ALLOC_1, val)
242#define bfin_read_MXVR_ALLOC_2() bfin_read32(MXVR_ALLOC_2)
243#define bfin_write_MXVR_ALLOC_2(val) bfin_write32(MXVR_ALLOC_2, val)
244#define bfin_read_MXVR_ALLOC_3() bfin_read32(MXVR_ALLOC_3)
245#define bfin_write_MXVR_ALLOC_3(val) bfin_write32(MXVR_ALLOC_3, val)
246#define bfin_read_MXVR_ALLOC_4() bfin_read32(MXVR_ALLOC_4)
247#define bfin_write_MXVR_ALLOC_4(val) bfin_write32(MXVR_ALLOC_4, val)
248#define bfin_read_MXVR_ALLOC_5() bfin_read32(MXVR_ALLOC_5)
249#define bfin_write_MXVR_ALLOC_5(val) bfin_write32(MXVR_ALLOC_5, val)
250#define bfin_read_MXVR_ALLOC_6() bfin_read32(MXVR_ALLOC_6)
251#define bfin_write_MXVR_ALLOC_6(val) bfin_write32(MXVR_ALLOC_6, val)
252#define bfin_read_MXVR_ALLOC_7() bfin_read32(MXVR_ALLOC_7)
253#define bfin_write_MXVR_ALLOC_7(val) bfin_write32(MXVR_ALLOC_7, val)
254#define bfin_read_MXVR_ALLOC_8() bfin_read32(MXVR_ALLOC_8)
255#define bfin_write_MXVR_ALLOC_8(val) bfin_write32(MXVR_ALLOC_8, val)
256#define bfin_read_MXVR_ALLOC_9() bfin_read32(MXVR_ALLOC_9)
257#define bfin_write_MXVR_ALLOC_9(val) bfin_write32(MXVR_ALLOC_9, val)
258#define bfin_read_MXVR_ALLOC_10() bfin_read32(MXVR_ALLOC_10)
259#define bfin_write_MXVR_ALLOC_10(val) bfin_write32(MXVR_ALLOC_10, val)
260#define bfin_read_MXVR_ALLOC_11() bfin_read32(MXVR_ALLOC_11)
261#define bfin_write_MXVR_ALLOC_11(val) bfin_write32(MXVR_ALLOC_11, val)
262#define bfin_read_MXVR_ALLOC_12() bfin_read32(MXVR_ALLOC_12)
263#define bfin_write_MXVR_ALLOC_12(val) bfin_write32(MXVR_ALLOC_12, val)
264#define bfin_read_MXVR_ALLOC_13() bfin_read32(MXVR_ALLOC_13)
265#define bfin_write_MXVR_ALLOC_13(val) bfin_write32(MXVR_ALLOC_13, val)
266#define bfin_read_MXVR_ALLOC_14() bfin_read32(MXVR_ALLOC_14)
267#define bfin_write_MXVR_ALLOC_14(val) bfin_write32(MXVR_ALLOC_14, val)
268
269/* MXVR Channel Assign Registers */
270
271#define bfin_read_MXVR_SYNC_LCHAN_0() bfin_read32(MXVR_SYNC_LCHAN_0)
272#define bfin_write_MXVR_SYNC_LCHAN_0(val) bfin_write32(MXVR_SYNC_LCHAN_0, val)
273#define bfin_read_MXVR_SYNC_LCHAN_1() bfin_read32(MXVR_SYNC_LCHAN_1)
274#define bfin_write_MXVR_SYNC_LCHAN_1(val) bfin_write32(MXVR_SYNC_LCHAN_1, val)
275#define bfin_read_MXVR_SYNC_LCHAN_2() bfin_read32(MXVR_SYNC_LCHAN_2)
276#define bfin_write_MXVR_SYNC_LCHAN_2(val) bfin_write32(MXVR_SYNC_LCHAN_2, val)
277#define bfin_read_MXVR_SYNC_LCHAN_3() bfin_read32(MXVR_SYNC_LCHAN_3)
278#define bfin_write_MXVR_SYNC_LCHAN_3(val) bfin_write32(MXVR_SYNC_LCHAN_3, val)
279#define bfin_read_MXVR_SYNC_LCHAN_4() bfin_read32(MXVR_SYNC_LCHAN_4)
280#define bfin_write_MXVR_SYNC_LCHAN_4(val) bfin_write32(MXVR_SYNC_LCHAN_4, val)
281#define bfin_read_MXVR_SYNC_LCHAN_5() bfin_read32(MXVR_SYNC_LCHAN_5)
282#define bfin_write_MXVR_SYNC_LCHAN_5(val) bfin_write32(MXVR_SYNC_LCHAN_5, val)
283#define bfin_read_MXVR_SYNC_LCHAN_6() bfin_read32(MXVR_SYNC_LCHAN_6)
284#define bfin_write_MXVR_SYNC_LCHAN_6(val) bfin_write32(MXVR_SYNC_LCHAN_6, val)
285#define bfin_read_MXVR_SYNC_LCHAN_7() bfin_read32(MXVR_SYNC_LCHAN_7)
286#define bfin_write_MXVR_SYNC_LCHAN_7(val) bfin_write32(MXVR_SYNC_LCHAN_7, val)
287
288/* MXVR DMA0 Registers */
289
290#define bfin_read_MXVR_DMA0_CONFIG() bfin_read32(MXVR_DMA0_CONFIG)
291#define bfin_write_MXVR_DMA0_CONFIG(val) bfin_write32(MXVR_DMA0_CONFIG, val)
292#define bfin_read_MXVR_DMA0_START_ADDR() bfin_read32(MXVR_DMA0_START_ADDR)
293#define bfin_write_MXVR_DMA0_START_ADDR(val) bfin_write32(MXVR_DMA0_START_ADDR)
294#define bfin_read_MXVR_DMA0_COUNT() bfin_read16(MXVR_DMA0_COUNT)
295#define bfin_write_MXVR_DMA0_COUNT(val) bfin_write16(MXVR_DMA0_COUNT, val)
296#define bfin_read_MXVR_DMA0_CURR_ADDR() bfin_read32(MXVR_DMA0_CURR_ADDR)
297#define bfin_write_MXVR_DMA0_CURR_ADDR(val) bfin_write32(MXVR_DMA0_CURR_ADDR)
298#define bfin_read_MXVR_DMA0_CURR_COUNT() bfin_read16(MXVR_DMA0_CURR_COUNT)
299#define bfin_write_MXVR_DMA0_CURR_COUNT(val) bfin_write16(MXVR_DMA0_CURR_COUNT, val)
300
301/* MXVR DMA1 Registers */
302
303#define bfin_read_MXVR_DMA1_CONFIG() bfin_read32(MXVR_DMA1_CONFIG)
304#define bfin_write_MXVR_DMA1_CONFIG(val) bfin_write32(MXVR_DMA1_CONFIG, val)
305#define bfin_read_MXVR_DMA1_START_ADDR() bfin_read32(MXVR_DMA1_START_ADDR)
306#define bfin_write_MXVR_DMA1_START_ADDR(val) bfin_write32(MXVR_DMA1_START_ADDR)
307#define bfin_read_MXVR_DMA1_COUNT() bfin_read16(MXVR_DMA1_COUNT)
308#define bfin_write_MXVR_DMA1_COUNT(val) bfin_write16(MXVR_DMA1_COUNT, val)
309#define bfin_read_MXVR_DMA1_CURR_ADDR() bfin_read32(MXVR_DMA1_CURR_ADDR)
310#define bfin_write_MXVR_DMA1_CURR_ADDR(val) bfin_write32(MXVR_DMA1_CURR_ADDR)
311#define bfin_read_MXVR_DMA1_CURR_COUNT() bfin_read16(MXVR_DMA1_CURR_COUNT)
312#define bfin_write_MXVR_DMA1_CURR_COUNT(val) bfin_write16(MXVR_DMA1_CURR_COUNT, val)
313
314/* MXVR DMA2 Registers */
315
316#define bfin_read_MXVR_DMA2_CONFIG() bfin_read32(MXVR_DMA2_CONFIG)
317#define bfin_write_MXVR_DMA2_CONFIG(val) bfin_write32(MXVR_DMA2_CONFIG, val)
318#define bfin_read_MXVR_DMA2_START_ADDR() bfin_read32(MXVR_DMA2_START_ADDR)
319#define bfin_write_MXVR_DMA2_START_ADDR(val) bfin_write32(MXVR_DMA2_START_ADDR)
320#define bfin_read_MXVR_DMA2_COUNT() bfin_read16(MXVR_DMA2_COUNT)
321#define bfin_write_MXVR_DMA2_COUNT(val) bfin_write16(MXVR_DMA2_COUNT, val)
322#define bfin_read_MXVR_DMA2_CURR_ADDR() bfin_read32(MXVR_DMA2_CURR_ADDR)
323#define bfin_write_MXVR_DMA2_CURR_ADDR(val) bfin_write32(MXVR_DMA2_CURR_ADDR)
324#define bfin_read_MXVR_DMA2_CURR_COUNT() bfin_read16(MXVR_DMA2_CURR_COUNT)
325#define bfin_write_MXVR_DMA2_CURR_COUNT(val) bfin_write16(MXVR_DMA2_CURR_COUNT, val)
326
327/* MXVR DMA3 Registers */
328
329#define bfin_read_MXVR_DMA3_CONFIG() bfin_read32(MXVR_DMA3_CONFIG)
330#define bfin_write_MXVR_DMA3_CONFIG(val) bfin_write32(MXVR_DMA3_CONFIG, val)
331#define bfin_read_MXVR_DMA3_START_ADDR() bfin_read32(MXVR_DMA3_START_ADDR)
332#define bfin_write_MXVR_DMA3_START_ADDR(val) bfin_write32(MXVR_DMA3_START_ADDR)
333#define bfin_read_MXVR_DMA3_COUNT() bfin_read16(MXVR_DMA3_COUNT)
334#define bfin_write_MXVR_DMA3_COUNT(val) bfin_write16(MXVR_DMA3_COUNT, val)
335#define bfin_read_MXVR_DMA3_CURR_ADDR() bfin_read32(MXVR_DMA3_CURR_ADDR)
336#define bfin_write_MXVR_DMA3_CURR_ADDR(val) bfin_write32(MXVR_DMA3_CURR_ADDR)
337#define bfin_read_MXVR_DMA3_CURR_COUNT() bfin_read16(MXVR_DMA3_CURR_COUNT)
338#define bfin_write_MXVR_DMA3_CURR_COUNT(val) bfin_write16(MXVR_DMA3_CURR_COUNT, val)
339
340/* MXVR DMA4 Registers */
341
342#define bfin_read_MXVR_DMA4_CONFIG() bfin_read32(MXVR_DMA4_CONFIG)
343#define bfin_write_MXVR_DMA4_CONFIG(val) bfin_write32(MXVR_DMA4_CONFIG, val)
344#define bfin_read_MXVR_DMA4_START_ADDR() bfin_read32(MXVR_DMA4_START_ADDR)
345#define bfin_write_MXVR_DMA4_START_ADDR(val) bfin_write32(MXVR_DMA4_START_ADDR)
346#define bfin_read_MXVR_DMA4_COUNT() bfin_read16(MXVR_DMA4_COUNT)
347#define bfin_write_MXVR_DMA4_COUNT(val) bfin_write16(MXVR_DMA4_COUNT, val)
348#define bfin_read_MXVR_DMA4_CURR_ADDR() bfin_read32(MXVR_DMA4_CURR_ADDR)
349#define bfin_write_MXVR_DMA4_CURR_ADDR(val) bfin_write32(MXVR_DMA4_CURR_ADDR)
350#define bfin_read_MXVR_DMA4_CURR_COUNT() bfin_read16(MXVR_DMA4_CURR_COUNT)
351#define bfin_write_MXVR_DMA4_CURR_COUNT(val) bfin_write16(MXVR_DMA4_CURR_COUNT, val)
352
353/* MXVR DMA5 Registers */
354
355#define bfin_read_MXVR_DMA5_CONFIG() bfin_read32(MXVR_DMA5_CONFIG)
356#define bfin_write_MXVR_DMA5_CONFIG(val) bfin_write32(MXVR_DMA5_CONFIG, val)
357#define bfin_read_MXVR_DMA5_START_ADDR() bfin_read32(MXVR_DMA5_START_ADDR)
358#define bfin_write_MXVR_DMA5_START_ADDR(val) bfin_write32(MXVR_DMA5_START_ADDR)
359#define bfin_read_MXVR_DMA5_COUNT() bfin_read16(MXVR_DMA5_COUNT)
360#define bfin_write_MXVR_DMA5_COUNT(val) bfin_write16(MXVR_DMA5_COUNT, val)
361#define bfin_read_MXVR_DMA5_CURR_ADDR() bfin_read32(MXVR_DMA5_CURR_ADDR)
362#define bfin_write_MXVR_DMA5_CURR_ADDR(val) bfin_write32(MXVR_DMA5_CURR_ADDR)
363#define bfin_read_MXVR_DMA5_CURR_COUNT() bfin_read16(MXVR_DMA5_CURR_COUNT)
364#define bfin_write_MXVR_DMA5_CURR_COUNT(val) bfin_write16(MXVR_DMA5_CURR_COUNT, val)
365
366/* MXVR DMA6 Registers */
367
368#define bfin_read_MXVR_DMA6_CONFIG() bfin_read32(MXVR_DMA6_CONFIG)
369#define bfin_write_MXVR_DMA6_CONFIG(val) bfin_write32(MXVR_DMA6_CONFIG, val)
370#define bfin_read_MXVR_DMA6_START_ADDR() bfin_read32(MXVR_DMA6_START_ADDR)
371#define bfin_write_MXVR_DMA6_START_ADDR(val) bfin_write32(MXVR_DMA6_START_ADDR)
372#define bfin_read_MXVR_DMA6_COUNT() bfin_read16(MXVR_DMA6_COUNT)
373#define bfin_write_MXVR_DMA6_COUNT(val) bfin_write16(MXVR_DMA6_COUNT, val)
374#define bfin_read_MXVR_DMA6_CURR_ADDR() bfin_read32(MXVR_DMA6_CURR_ADDR)
375#define bfin_write_MXVR_DMA6_CURR_ADDR(val) bfin_write32(MXVR_DMA6_CURR_ADDR)
376#define bfin_read_MXVR_DMA6_CURR_COUNT() bfin_read16(MXVR_DMA6_CURR_COUNT)
377#define bfin_write_MXVR_DMA6_CURR_COUNT(val) bfin_write16(MXVR_DMA6_CURR_COUNT, val)
378
379/* MXVR DMA7 Registers */
380
381#define bfin_read_MXVR_DMA7_CONFIG() bfin_read32(MXVR_DMA7_CONFIG)
382#define bfin_write_MXVR_DMA7_CONFIG(val) bfin_write32(MXVR_DMA7_CONFIG, val)
383#define bfin_read_MXVR_DMA7_START_ADDR() bfin_read32(MXVR_DMA7_START_ADDR)
384#define bfin_write_MXVR_DMA7_START_ADDR(val) bfin_write32(MXVR_DMA7_START_ADDR)
385#define bfin_read_MXVR_DMA7_COUNT() bfin_read16(MXVR_DMA7_COUNT)
386#define bfin_write_MXVR_DMA7_COUNT(val) bfin_write16(MXVR_DMA7_COUNT, val)
387#define bfin_read_MXVR_DMA7_CURR_ADDR() bfin_read32(MXVR_DMA7_CURR_ADDR)
388#define bfin_write_MXVR_DMA7_CURR_ADDR(val) bfin_write32(MXVR_DMA7_CURR_ADDR)
389#define bfin_read_MXVR_DMA7_CURR_COUNT() bfin_read16(MXVR_DMA7_CURR_COUNT)
390#define bfin_write_MXVR_DMA7_CURR_COUNT(val) bfin_write16(MXVR_DMA7_CURR_COUNT, val)
391
392/* MXVR Asynch Packet Registers */
393
394#define bfin_read_MXVR_AP_CTL() bfin_read16(MXVR_AP_CTL)
395#define bfin_write_MXVR_AP_CTL(val) bfin_write16(MXVR_AP_CTL, val)
396#define bfin_read_MXVR_APRB_START_ADDR() bfin_read32(MXVR_APRB_START_ADDR)
397#define bfin_write_MXVR_APRB_START_ADDR(val) bfin_write32(MXVR_APRB_START_ADDR)
398#define bfin_read_MXVR_APRB_CURR_ADDR() bfin_read32(MXVR_APRB_CURR_ADDR)
399#define bfin_write_MXVR_APRB_CURR_ADDR(val) bfin_write32(MXVR_APRB_CURR_ADDR)
400#define bfin_read_MXVR_APTB_START_ADDR() bfin_read32(MXVR_APTB_START_ADDR)
401#define bfin_write_MXVR_APTB_START_ADDR(val) bfin_write32(MXVR_APTB_START_ADDR)
402#define bfin_read_MXVR_APTB_CURR_ADDR() bfin_read32(MXVR_APTB_CURR_ADDR)
403#define bfin_write_MXVR_APTB_CURR_ADDR(val) bfin_write32(MXVR_APTB_CURR_ADDR)
404
405/* MXVR Control Message Registers */
406
407#define bfin_read_MXVR_CM_CTL() bfin_read32(MXVR_CM_CTL)
408#define bfin_write_MXVR_CM_CTL(val) bfin_write32(MXVR_CM_CTL, val)
409#define bfin_read_MXVR_CMRB_START_ADDR() bfin_read32(MXVR_CMRB_START_ADDR)
410#define bfin_write_MXVR_CMRB_START_ADDR(val) bfin_write32(MXVR_CMRB_START_ADDR)
411#define bfin_read_MXVR_CMRB_CURR_ADDR() bfin_read32(MXVR_CMRB_CURR_ADDR)
412#define bfin_write_MXVR_CMRB_CURR_ADDR(val) bfin_write32(MXVR_CMRB_CURR_ADDR)
413#define bfin_read_MXVR_CMTB_START_ADDR() bfin_read32(MXVR_CMTB_START_ADDR)
414#define bfin_write_MXVR_CMTB_START_ADDR(val) bfin_write32(MXVR_CMTB_START_ADDR)
415#define bfin_read_MXVR_CMTB_CURR_ADDR() bfin_read32(MXVR_CMTB_CURR_ADDR)
416#define bfin_write_MXVR_CMTB_CURR_ADDR(val) bfin_write32(MXVR_CMTB_CURR_ADDR)
417
418/* MXVR Remote Read Registers */
419
420#define bfin_read_MXVR_RRDB_START_ADDR() bfin_read32(MXVR_RRDB_START_ADDR)
421#define bfin_write_MXVR_RRDB_START_ADDR(val) bfin_write32(MXVR_RRDB_START_ADDR)
422#define bfin_read_MXVR_RRDB_CURR_ADDR() bfin_read32(MXVR_RRDB_CURR_ADDR)
423#define bfin_write_MXVR_RRDB_CURR_ADDR(val) bfin_write32(MXVR_RRDB_CURR_ADDR)
424
425/* MXVR Pattern Data Registers */
426
427#define bfin_read_MXVR_PAT_DATA_0() bfin_read32(MXVR_PAT_DATA_0)
428#define bfin_write_MXVR_PAT_DATA_0(val) bfin_write32(MXVR_PAT_DATA_0, val)
429#define bfin_read_MXVR_PAT_EN_0() bfin_read32(MXVR_PAT_EN_0)
430#define bfin_write_MXVR_PAT_EN_0(val) bfin_write32(MXVR_PAT_EN_0, val)
431#define bfin_read_MXVR_PAT_DATA_1() bfin_read32(MXVR_PAT_DATA_1)
432#define bfin_write_MXVR_PAT_DATA_1(val) bfin_write32(MXVR_PAT_DATA_1, val)
433#define bfin_read_MXVR_PAT_EN_1() bfin_read32(MXVR_PAT_EN_1)
434#define bfin_write_MXVR_PAT_EN_1(val) bfin_write32(MXVR_PAT_EN_1, val)
435
436/* MXVR Frame Counter Registers */
437
438#define bfin_read_MXVR_FRAME_CNT_0() bfin_read16(MXVR_FRAME_CNT_0)
439#define bfin_write_MXVR_FRAME_CNT_0(val) bfin_write16(MXVR_FRAME_CNT_0, val)
440#define bfin_read_MXVR_FRAME_CNT_1() bfin_read16(MXVR_FRAME_CNT_1)
441#define bfin_write_MXVR_FRAME_CNT_1(val) bfin_write16(MXVR_FRAME_CNT_1, val)
442
443/* MXVR Routing Table Registers */
444
445#define bfin_read_MXVR_ROUTING_0() bfin_read32(MXVR_ROUTING_0)
446#define bfin_write_MXVR_ROUTING_0(val) bfin_write32(MXVR_ROUTING_0, val)
447#define bfin_read_MXVR_ROUTING_1() bfin_read32(MXVR_ROUTING_1)
448#define bfin_write_MXVR_ROUTING_1(val) bfin_write32(MXVR_ROUTING_1, val)
449#define bfin_read_MXVR_ROUTING_2() bfin_read32(MXVR_ROUTING_2)
450#define bfin_write_MXVR_ROUTING_2(val) bfin_write32(MXVR_ROUTING_2, val)
451#define bfin_read_MXVR_ROUTING_3() bfin_read32(MXVR_ROUTING_3)
452#define bfin_write_MXVR_ROUTING_3(val) bfin_write32(MXVR_ROUTING_3, val)
453#define bfin_read_MXVR_ROUTING_4() bfin_read32(MXVR_ROUTING_4)
454#define bfin_write_MXVR_ROUTING_4(val) bfin_write32(MXVR_ROUTING_4, val)
455#define bfin_read_MXVR_ROUTING_5() bfin_read32(MXVR_ROUTING_5)
456#define bfin_write_MXVR_ROUTING_5(val) bfin_write32(MXVR_ROUTING_5, val)
457#define bfin_read_MXVR_ROUTING_6() bfin_read32(MXVR_ROUTING_6)
458#define bfin_write_MXVR_ROUTING_6(val) bfin_write32(MXVR_ROUTING_6, val)
459#define bfin_read_MXVR_ROUTING_7() bfin_read32(MXVR_ROUTING_7)
460#define bfin_write_MXVR_ROUTING_7(val) bfin_write32(MXVR_ROUTING_7, val)
461#define bfin_read_MXVR_ROUTING_8() bfin_read32(MXVR_ROUTING_8)
462#define bfin_write_MXVR_ROUTING_8(val) bfin_write32(MXVR_ROUTING_8, val)
463#define bfin_read_MXVR_ROUTING_9() bfin_read32(MXVR_ROUTING_9)
464#define bfin_write_MXVR_ROUTING_9(val) bfin_write32(MXVR_ROUTING_9, val)
465#define bfin_read_MXVR_ROUTING_10() bfin_read32(MXVR_ROUTING_10)
466#define bfin_write_MXVR_ROUTING_10(val) bfin_write32(MXVR_ROUTING_10, val)
467#define bfin_read_MXVR_ROUTING_11() bfin_read32(MXVR_ROUTING_11)
468#define bfin_write_MXVR_ROUTING_11(val) bfin_write32(MXVR_ROUTING_11, val)
469#define bfin_read_MXVR_ROUTING_12() bfin_read32(MXVR_ROUTING_12)
470#define bfin_write_MXVR_ROUTING_12(val) bfin_write32(MXVR_ROUTING_12, val)
471#define bfin_read_MXVR_ROUTING_13() bfin_read32(MXVR_ROUTING_13)
472#define bfin_write_MXVR_ROUTING_13(val) bfin_write32(MXVR_ROUTING_13, val)
473#define bfin_read_MXVR_ROUTING_14() bfin_read32(MXVR_ROUTING_14)
474#define bfin_write_MXVR_ROUTING_14(val) bfin_write32(MXVR_ROUTING_14, val)
475
476/* MXVR Counter-Clock-Control Registers */
477
478#define bfin_read_MXVR_BLOCK_CNT() bfin_read16(MXVR_BLOCK_CNT)
479#define bfin_write_MXVR_BLOCK_CNT(val) bfin_write16(MXVR_BLOCK_CNT, val)
480#define bfin_read_MXVR_CLK_CTL() bfin_read32(MXVR_CLK_CTL)
481#define bfin_write_MXVR_CLK_CTL(val) bfin_write32(MXVR_CLK_CTL, val)
482#define bfin_read_MXVR_CDRPLL_CTL() bfin_read32(MXVR_CDRPLL_CTL)
483#define bfin_write_MXVR_CDRPLL_CTL(val) bfin_write32(MXVR_CDRPLL_CTL, val)
484#define bfin_read_MXVR_FMPLL_CTL() bfin_read32(MXVR_FMPLL_CTL)
485#define bfin_write_MXVR_FMPLL_CTL(val) bfin_write32(MXVR_FMPLL_CTL, val)
486#define bfin_read_MXVR_PIN_CTL() bfin_read16(MXVR_PIN_CTL)
487#define bfin_write_MXVR_PIN_CTL(val) bfin_write16(MXVR_PIN_CTL, val)
488#define bfin_read_MXVR_SCLK_CNT() bfin_read16(MXVR_SCLK_CNT)
489#define bfin_write_MXVR_SCLK_CNT(val) bfin_write16(MXVR_SCLK_CNT, val)
490
491/* CAN Controller 1 Config 1 Registers */
492
493#define bfin_read_CAN1_MC1() bfin_read16(CAN1_MC1)
494#define bfin_write_CAN1_MC1(val) bfin_write16(CAN1_MC1, val)
495#define bfin_read_CAN1_MD1() bfin_read16(CAN1_MD1)
496#define bfin_write_CAN1_MD1(val) bfin_write16(CAN1_MD1, val)
497#define bfin_read_CAN1_TRS1() bfin_read16(CAN1_TRS1)
498#define bfin_write_CAN1_TRS1(val) bfin_write16(CAN1_TRS1, val)
499#define bfin_read_CAN1_TRR1() bfin_read16(CAN1_TRR1)
500#define bfin_write_CAN1_TRR1(val) bfin_write16(CAN1_TRR1, val)
501#define bfin_read_CAN1_TA1() bfin_read16(CAN1_TA1)
502#define bfin_write_CAN1_TA1(val) bfin_write16(CAN1_TA1, val)
503#define bfin_read_CAN1_AA1() bfin_read16(CAN1_AA1)
504#define bfin_write_CAN1_AA1(val) bfin_write16(CAN1_AA1, val)
505#define bfin_read_CAN1_RMP1() bfin_read16(CAN1_RMP1)
506#define bfin_write_CAN1_RMP1(val) bfin_write16(CAN1_RMP1, val)
507#define bfin_read_CAN1_RML1() bfin_read16(CAN1_RML1)
508#define bfin_write_CAN1_RML1(val) bfin_write16(CAN1_RML1, val)
509#define bfin_read_CAN1_MBTIF1() bfin_read16(CAN1_MBTIF1)
510#define bfin_write_CAN1_MBTIF1(val) bfin_write16(CAN1_MBTIF1, val)
511#define bfin_read_CAN1_MBRIF1() bfin_read16(CAN1_MBRIF1)
512#define bfin_write_CAN1_MBRIF1(val) bfin_write16(CAN1_MBRIF1, val)
513#define bfin_read_CAN1_MBIM1() bfin_read16(CAN1_MBIM1)
514#define bfin_write_CAN1_MBIM1(val) bfin_write16(CAN1_MBIM1, val)
515#define bfin_read_CAN1_RFH1() bfin_read16(CAN1_RFH1)
516#define bfin_write_CAN1_RFH1(val) bfin_write16(CAN1_RFH1, val)
517#define bfin_read_CAN1_OPSS1() bfin_read16(CAN1_OPSS1)
518#define bfin_write_CAN1_OPSS1(val) bfin_write16(CAN1_OPSS1, val)
519
520/* CAN Controller 1 Config 2 Registers */
521
522#define bfin_read_CAN1_MC2() bfin_read16(CAN1_MC2)
523#define bfin_write_CAN1_MC2(val) bfin_write16(CAN1_MC2, val)
524#define bfin_read_CAN1_MD2() bfin_read16(CAN1_MD2)
525#define bfin_write_CAN1_MD2(val) bfin_write16(CAN1_MD2, val)
526#define bfin_read_CAN1_TRS2() bfin_read16(CAN1_TRS2)
527#define bfin_write_CAN1_TRS2(val) bfin_write16(CAN1_TRS2, val)
528#define bfin_read_CAN1_TRR2() bfin_read16(CAN1_TRR2)
529#define bfin_write_CAN1_TRR2(val) bfin_write16(CAN1_TRR2, val)
530#define bfin_read_CAN1_TA2() bfin_read16(CAN1_TA2)
531#define bfin_write_CAN1_TA2(val) bfin_write16(CAN1_TA2, val)
532#define bfin_read_CAN1_AA2() bfin_read16(CAN1_AA2)
533#define bfin_write_CAN1_AA2(val) bfin_write16(CAN1_AA2, val)
534#define bfin_read_CAN1_RMP2() bfin_read16(CAN1_RMP2)
535#define bfin_write_CAN1_RMP2(val) bfin_write16(CAN1_RMP2, val)
536#define bfin_read_CAN1_RML2() bfin_read16(CAN1_RML2)
537#define bfin_write_CAN1_RML2(val) bfin_write16(CAN1_RML2, val)
538#define bfin_read_CAN1_MBTIF2() bfin_read16(CAN1_MBTIF2)
539#define bfin_write_CAN1_MBTIF2(val) bfin_write16(CAN1_MBTIF2, val)
540#define bfin_read_CAN1_MBRIF2() bfin_read16(CAN1_MBRIF2)
541#define bfin_write_CAN1_MBRIF2(val) bfin_write16(CAN1_MBRIF2, val)
542#define bfin_read_CAN1_MBIM2() bfin_read16(CAN1_MBIM2)
543#define bfin_write_CAN1_MBIM2(val) bfin_write16(CAN1_MBIM2, val)
544#define bfin_read_CAN1_RFH2() bfin_read16(CAN1_RFH2)
545#define bfin_write_CAN1_RFH2(val) bfin_write16(CAN1_RFH2, val)
546#define bfin_read_CAN1_OPSS2() bfin_read16(CAN1_OPSS2)
547#define bfin_write_CAN1_OPSS2(val) bfin_write16(CAN1_OPSS2, val)
548
549/* CAN Controller 1 Clock/Interrubfin_read_()t/Counter Registers */
550
551#define bfin_read_CAN1_CLOCK() bfin_read16(CAN1_CLOCK)
552#define bfin_write_CAN1_CLOCK(val) bfin_write16(CAN1_CLOCK, val)
553#define bfin_read_CAN1_TIMING() bfin_read16(CAN1_TIMING)
554#define bfin_write_CAN1_TIMING(val) bfin_write16(CAN1_TIMING, val)
555#define bfin_read_CAN1_DEBUG() bfin_read16(CAN1_DEBUG)
556#define bfin_write_CAN1_DEBUG(val) bfin_write16(CAN1_DEBUG, val)
557#define bfin_read_CAN1_STATUS() bfin_read16(CAN1_STATUS)
558#define bfin_write_CAN1_STATUS(val) bfin_write16(CAN1_STATUS, val)
559#define bfin_read_CAN1_CEC() bfin_read16(CAN1_CEC)
560#define bfin_write_CAN1_CEC(val) bfin_write16(CAN1_CEC, val)
561#define bfin_read_CAN1_GIS() bfin_read16(CAN1_GIS)
562#define bfin_write_CAN1_GIS(val) bfin_write16(CAN1_GIS, val)
563#define bfin_read_CAN1_GIM() bfin_read16(CAN1_GIM)
564#define bfin_write_CAN1_GIM(val) bfin_write16(CAN1_GIM, val)
565#define bfin_read_CAN1_GIF() bfin_read16(CAN1_GIF)
566#define bfin_write_CAN1_GIF(val) bfin_write16(CAN1_GIF, val)
567#define bfin_read_CAN1_CONTROL() bfin_read16(CAN1_CONTROL)
568#define bfin_write_CAN1_CONTROL(val) bfin_write16(CAN1_CONTROL, val)
569#define bfin_read_CAN1_INTR() bfin_read16(CAN1_INTR)
570#define bfin_write_CAN1_INTR(val) bfin_write16(CAN1_INTR, val)
571#define bfin_read_CAN1_MBTD() bfin_read16(CAN1_MBTD)
572#define bfin_write_CAN1_MBTD(val) bfin_write16(CAN1_MBTD, val)
573#define bfin_read_CAN1_EWR() bfin_read16(CAN1_EWR)
574#define bfin_write_CAN1_EWR(val) bfin_write16(CAN1_EWR, val)
575#define bfin_read_CAN1_ESR() bfin_read16(CAN1_ESR)
576#define bfin_write_CAN1_ESR(val) bfin_write16(CAN1_ESR, val)
577#define bfin_read_CAN1_UCCNT() bfin_read16(CAN1_UCCNT)
578#define bfin_write_CAN1_UCCNT(val) bfin_write16(CAN1_UCCNT, val)
579#define bfin_read_CAN1_UCRC() bfin_read16(CAN1_UCRC)
580#define bfin_write_CAN1_UCRC(val) bfin_write16(CAN1_UCRC, val)
581#define bfin_read_CAN1_UCCNF() bfin_read16(CAN1_UCCNF)
582#define bfin_write_CAN1_UCCNF(val) bfin_write16(CAN1_UCCNF, val)
583
584/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
585
586#define bfin_read_CAN1_AM00L() bfin_read16(CAN1_AM00L)
587#define bfin_write_CAN1_AM00L(val) bfin_write16(CAN1_AM00L, val)
588#define bfin_read_CAN1_AM00H() bfin_read16(CAN1_AM00H)
589#define bfin_write_CAN1_AM00H(val) bfin_write16(CAN1_AM00H, val)
590#define bfin_read_CAN1_AM01L() bfin_read16(CAN1_AM01L)
591#define bfin_write_CAN1_AM01L(val) bfin_write16(CAN1_AM01L, val)
592#define bfin_read_CAN1_AM01H() bfin_read16(CAN1_AM01H)
593#define bfin_write_CAN1_AM01H(val) bfin_write16(CAN1_AM01H, val)
594#define bfin_read_CAN1_AM02L() bfin_read16(CAN1_AM02L)
595#define bfin_write_CAN1_AM02L(val) bfin_write16(CAN1_AM02L, val)
596#define bfin_read_CAN1_AM02H() bfin_read16(CAN1_AM02H)
597#define bfin_write_CAN1_AM02H(val) bfin_write16(CAN1_AM02H, val)
598#define bfin_read_CAN1_AM03L() bfin_read16(CAN1_AM03L)
599#define bfin_write_CAN1_AM03L(val) bfin_write16(CAN1_AM03L, val)
600#define bfin_read_CAN1_AM03H() bfin_read16(CAN1_AM03H)
601#define bfin_write_CAN1_AM03H(val) bfin_write16(CAN1_AM03H, val)
602#define bfin_read_CAN1_AM04L() bfin_read16(CAN1_AM04L)
603#define bfin_write_CAN1_AM04L(val) bfin_write16(CAN1_AM04L, val)
604#define bfin_read_CAN1_AM04H() bfin_read16(CAN1_AM04H)
605#define bfin_write_CAN1_AM04H(val) bfin_write16(CAN1_AM04H, val)
606#define bfin_read_CAN1_AM05L() bfin_read16(CAN1_AM05L)
607#define bfin_write_CAN1_AM05L(val) bfin_write16(CAN1_AM05L, val)
608#define bfin_read_CAN1_AM05H() bfin_read16(CAN1_AM05H)
609#define bfin_write_CAN1_AM05H(val) bfin_write16(CAN1_AM05H, val)
610#define bfin_read_CAN1_AM06L() bfin_read16(CAN1_AM06L)
611#define bfin_write_CAN1_AM06L(val) bfin_write16(CAN1_AM06L, val)
612#define bfin_read_CAN1_AM06H() bfin_read16(CAN1_AM06H)
613#define bfin_write_CAN1_AM06H(val) bfin_write16(CAN1_AM06H, val)
614#define bfin_read_CAN1_AM07L() bfin_read16(CAN1_AM07L)
615#define bfin_write_CAN1_AM07L(val) bfin_write16(CAN1_AM07L, val)
616#define bfin_read_CAN1_AM07H() bfin_read16(CAN1_AM07H)
617#define bfin_write_CAN1_AM07H(val) bfin_write16(CAN1_AM07H, val)
618#define bfin_read_CAN1_AM08L() bfin_read16(CAN1_AM08L)
619#define bfin_write_CAN1_AM08L(val) bfin_write16(CAN1_AM08L, val)
620#define bfin_read_CAN1_AM08H() bfin_read16(CAN1_AM08H)
621#define bfin_write_CAN1_AM08H(val) bfin_write16(CAN1_AM08H, val)
622#define bfin_read_CAN1_AM09L() bfin_read16(CAN1_AM09L)
623#define bfin_write_CAN1_AM09L(val) bfin_write16(CAN1_AM09L, val)
624#define bfin_read_CAN1_AM09H() bfin_read16(CAN1_AM09H)
625#define bfin_write_CAN1_AM09H(val) bfin_write16(CAN1_AM09H, val)
626#define bfin_read_CAN1_AM10L() bfin_read16(CAN1_AM10L)
627#define bfin_write_CAN1_AM10L(val) bfin_write16(CAN1_AM10L, val)
628#define bfin_read_CAN1_AM10H() bfin_read16(CAN1_AM10H)
629#define bfin_write_CAN1_AM10H(val) bfin_write16(CAN1_AM10H, val)
630#define bfin_read_CAN1_AM11L() bfin_read16(CAN1_AM11L)
631#define bfin_write_CAN1_AM11L(val) bfin_write16(CAN1_AM11L, val)
632#define bfin_read_CAN1_AM11H() bfin_read16(CAN1_AM11H)
633#define bfin_write_CAN1_AM11H(val) bfin_write16(CAN1_AM11H, val)
634#define bfin_read_CAN1_AM12L() bfin_read16(CAN1_AM12L)
635#define bfin_write_CAN1_AM12L(val) bfin_write16(CAN1_AM12L, val)
636#define bfin_read_CAN1_AM12H() bfin_read16(CAN1_AM12H)
637#define bfin_write_CAN1_AM12H(val) bfin_write16(CAN1_AM12H, val)
638#define bfin_read_CAN1_AM13L() bfin_read16(CAN1_AM13L)
639#define bfin_write_CAN1_AM13L(val) bfin_write16(CAN1_AM13L, val)
640#define bfin_read_CAN1_AM13H() bfin_read16(CAN1_AM13H)
641#define bfin_write_CAN1_AM13H(val) bfin_write16(CAN1_AM13H, val)
642#define bfin_read_CAN1_AM14L() bfin_read16(CAN1_AM14L)
643#define bfin_write_CAN1_AM14L(val) bfin_write16(CAN1_AM14L, val)
644#define bfin_read_CAN1_AM14H() bfin_read16(CAN1_AM14H)
645#define bfin_write_CAN1_AM14H(val) bfin_write16(CAN1_AM14H, val)
646#define bfin_read_CAN1_AM15L() bfin_read16(CAN1_AM15L)
647#define bfin_write_CAN1_AM15L(val) bfin_write16(CAN1_AM15L, val)
648#define bfin_read_CAN1_AM15H() bfin_read16(CAN1_AM15H)
649#define bfin_write_CAN1_AM15H(val) bfin_write16(CAN1_AM15H, val)
650
651/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
652
653#define bfin_read_CAN1_AM16L() bfin_read16(CAN1_AM16L)
654#define bfin_write_CAN1_AM16L(val) bfin_write16(CAN1_AM16L, val)
655#define bfin_read_CAN1_AM16H() bfin_read16(CAN1_AM16H)
656#define bfin_write_CAN1_AM16H(val) bfin_write16(CAN1_AM16H, val)
657#define bfin_read_CAN1_AM17L() bfin_read16(CAN1_AM17L)
658#define bfin_write_CAN1_AM17L(val) bfin_write16(CAN1_AM17L, val)
659#define bfin_read_CAN1_AM17H() bfin_read16(CAN1_AM17H)
660#define bfin_write_CAN1_AM17H(val) bfin_write16(CAN1_AM17H, val)
661#define bfin_read_CAN1_AM18L() bfin_read16(CAN1_AM18L)
662#define bfin_write_CAN1_AM18L(val) bfin_write16(CAN1_AM18L, val)
663#define bfin_read_CAN1_AM18H() bfin_read16(CAN1_AM18H)
664#define bfin_write_CAN1_AM18H(val) bfin_write16(CAN1_AM18H, val)
665#define bfin_read_CAN1_AM19L() bfin_read16(CAN1_AM19L)
666#define bfin_write_CAN1_AM19L(val) bfin_write16(CAN1_AM19L, val)
667#define bfin_read_CAN1_AM19H() bfin_read16(CAN1_AM19H)
668#define bfin_write_CAN1_AM19H(val) bfin_write16(CAN1_AM19H, val)
669#define bfin_read_CAN1_AM20L() bfin_read16(CAN1_AM20L)
670#define bfin_write_CAN1_AM20L(val) bfin_write16(CAN1_AM20L, val)
671#define bfin_read_CAN1_AM20H() bfin_read16(CAN1_AM20H)
672#define bfin_write_CAN1_AM20H(val) bfin_write16(CAN1_AM20H, val)
673#define bfin_read_CAN1_AM21L() bfin_read16(CAN1_AM21L)
674#define bfin_write_CAN1_AM21L(val) bfin_write16(CAN1_AM21L, val)
675#define bfin_read_CAN1_AM21H() bfin_read16(CAN1_AM21H)
676#define bfin_write_CAN1_AM21H(val) bfin_write16(CAN1_AM21H, val)
677#define bfin_read_CAN1_AM22L() bfin_read16(CAN1_AM22L)
678#define bfin_write_CAN1_AM22L(val) bfin_write16(CAN1_AM22L, val)
679#define bfin_read_CAN1_AM22H() bfin_read16(CAN1_AM22H)
680#define bfin_write_CAN1_AM22H(val) bfin_write16(CAN1_AM22H, val)
681#define bfin_read_CAN1_AM23L() bfin_read16(CAN1_AM23L)
682#define bfin_write_CAN1_AM23L(val) bfin_write16(CAN1_AM23L, val)
683#define bfin_read_CAN1_AM23H() bfin_read16(CAN1_AM23H)
684#define bfin_write_CAN1_AM23H(val) bfin_write16(CAN1_AM23H, val)
685#define bfin_read_CAN1_AM24L() bfin_read16(CAN1_AM24L)
686#define bfin_write_CAN1_AM24L(val) bfin_write16(CAN1_AM24L, val)
687#define bfin_read_CAN1_AM24H() bfin_read16(CAN1_AM24H)
688#define bfin_write_CAN1_AM24H(val) bfin_write16(CAN1_AM24H, val)
689#define bfin_read_CAN1_AM25L() bfin_read16(CAN1_AM25L)
690#define bfin_write_CAN1_AM25L(val) bfin_write16(CAN1_AM25L, val)
691#define bfin_read_CAN1_AM25H() bfin_read16(CAN1_AM25H)
692#define bfin_write_CAN1_AM25H(val) bfin_write16(CAN1_AM25H, val)
693#define bfin_read_CAN1_AM26L() bfin_read16(CAN1_AM26L)
694#define bfin_write_CAN1_AM26L(val) bfin_write16(CAN1_AM26L, val)
695#define bfin_read_CAN1_AM26H() bfin_read16(CAN1_AM26H)
696#define bfin_write_CAN1_AM26H(val) bfin_write16(CAN1_AM26H, val)
697#define bfin_read_CAN1_AM27L() bfin_read16(CAN1_AM27L)
698#define bfin_write_CAN1_AM27L(val) bfin_write16(CAN1_AM27L, val)
699#define bfin_read_CAN1_AM27H() bfin_read16(CAN1_AM27H)
700#define bfin_write_CAN1_AM27H(val) bfin_write16(CAN1_AM27H, val)
701#define bfin_read_CAN1_AM28L() bfin_read16(CAN1_AM28L)
702#define bfin_write_CAN1_AM28L(val) bfin_write16(CAN1_AM28L, val)
703#define bfin_read_CAN1_AM28H() bfin_read16(CAN1_AM28H)
704#define bfin_write_CAN1_AM28H(val) bfin_write16(CAN1_AM28H, val)
705#define bfin_read_CAN1_AM29L() bfin_read16(CAN1_AM29L)
706#define bfin_write_CAN1_AM29L(val) bfin_write16(CAN1_AM29L, val)
707#define bfin_read_CAN1_AM29H() bfin_read16(CAN1_AM29H)
708#define bfin_write_CAN1_AM29H(val) bfin_write16(CAN1_AM29H, val)
709#define bfin_read_CAN1_AM30L() bfin_read16(CAN1_AM30L)
710#define bfin_write_CAN1_AM30L(val) bfin_write16(CAN1_AM30L, val)
711#define bfin_read_CAN1_AM30H() bfin_read16(CAN1_AM30H)
712#define bfin_write_CAN1_AM30H(val) bfin_write16(CAN1_AM30H, val)
713#define bfin_read_CAN1_AM31L() bfin_read16(CAN1_AM31L)
714#define bfin_write_CAN1_AM31L(val) bfin_write16(CAN1_AM31L, val)
715#define bfin_read_CAN1_AM31H() bfin_read16(CAN1_AM31H)
716#define bfin_write_CAN1_AM31H(val) bfin_write16(CAN1_AM31H, val)
717
718/* CAN Controller 1 Mailbox Data Registers */
719
720#define bfin_read_CAN1_MB00_DATA0() bfin_read16(CAN1_MB00_DATA0)
721#define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val)
722#define bfin_read_CAN1_MB00_DATA1() bfin_read16(CAN1_MB00_DATA1)
723#define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val)
724#define bfin_read_CAN1_MB00_DATA2() bfin_read16(CAN1_MB00_DATA2)
725#define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val)
726#define bfin_read_CAN1_MB00_DATA3() bfin_read16(CAN1_MB00_DATA3)
727#define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val)
728#define bfin_read_CAN1_MB00_LENGTH() bfin_read16(CAN1_MB00_LENGTH)
729#define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val)
730#define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP)
731#define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val)
732#define bfin_read_CAN1_MB00_ID0() bfin_read16(CAN1_MB00_ID0)
733#define bfin_write_CAN1_MB00_ID0(val) bfin_write16(CAN1_MB00_ID0, val)
734#define bfin_read_CAN1_MB00_ID1() bfin_read16(CAN1_MB00_ID1)
735#define bfin_write_CAN1_MB00_ID1(val) bfin_write16(CAN1_MB00_ID1, val)
736#define bfin_read_CAN1_MB01_DATA0() bfin_read16(CAN1_MB01_DATA0)
737#define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val)
738#define bfin_read_CAN1_MB01_DATA1() bfin_read16(CAN1_MB01_DATA1)
739#define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val)
740#define bfin_read_CAN1_MB01_DATA2() bfin_read16(CAN1_MB01_DATA2)
741#define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val)
742#define bfin_read_CAN1_MB01_DATA3() bfin_read16(CAN1_MB01_DATA3)
743#define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val)
744#define bfin_read_CAN1_MB01_LENGTH() bfin_read16(CAN1_MB01_LENGTH)
745#define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val)
746#define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP)
747#define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val)
748#define bfin_read_CAN1_MB01_ID0() bfin_read16(CAN1_MB01_ID0)
749#define bfin_write_CAN1_MB01_ID0(val) bfin_write16(CAN1_MB01_ID0, val)
750#define bfin_read_CAN1_MB01_ID1() bfin_read16(CAN1_MB01_ID1)
751#define bfin_write_CAN1_MB01_ID1(val) bfin_write16(CAN1_MB01_ID1, val)
752#define bfin_read_CAN1_MB02_DATA0() bfin_read16(CAN1_MB02_DATA0)
753#define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val)
754#define bfin_read_CAN1_MB02_DATA1() bfin_read16(CAN1_MB02_DATA1)
755#define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val)
756#define bfin_read_CAN1_MB02_DATA2() bfin_read16(CAN1_MB02_DATA2)
757#define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val)
758#define bfin_read_CAN1_MB02_DATA3() bfin_read16(CAN1_MB02_DATA3)
759#define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val)
760#define bfin_read_CAN1_MB02_LENGTH() bfin_read16(CAN1_MB02_LENGTH)
761#define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val)
762#define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP)
763#define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val)
764#define bfin_read_CAN1_MB02_ID0() bfin_read16(CAN1_MB02_ID0)
765#define bfin_write_CAN1_MB02_ID0(val) bfin_write16(CAN1_MB02_ID0, val)
766#define bfin_read_CAN1_MB02_ID1() bfin_read16(CAN1_MB02_ID1)
767#define bfin_write_CAN1_MB02_ID1(val) bfin_write16(CAN1_MB02_ID1, val)
768#define bfin_read_CAN1_MB03_DATA0() bfin_read16(CAN1_MB03_DATA0)
769#define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val)
770#define bfin_read_CAN1_MB03_DATA1() bfin_read16(CAN1_MB03_DATA1)
771#define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val)
772#define bfin_read_CAN1_MB03_DATA2() bfin_read16(CAN1_MB03_DATA2)
773#define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val)
774#define bfin_read_CAN1_MB03_DATA3() bfin_read16(CAN1_MB03_DATA3)
775#define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val)
776#define bfin_read_CAN1_MB03_LENGTH() bfin_read16(CAN1_MB03_LENGTH)
777#define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val)
778#define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP)
779#define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val)
780#define bfin_read_CAN1_MB03_ID0() bfin_read16(CAN1_MB03_ID0)
781#define bfin_write_CAN1_MB03_ID0(val) bfin_write16(CAN1_MB03_ID0, val)
782#define bfin_read_CAN1_MB03_ID1() bfin_read16(CAN1_MB03_ID1)
783#define bfin_write_CAN1_MB03_ID1(val) bfin_write16(CAN1_MB03_ID1, val)
784#define bfin_read_CAN1_MB04_DATA0() bfin_read16(CAN1_MB04_DATA0)
785#define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val)
786#define bfin_read_CAN1_MB04_DATA1() bfin_read16(CAN1_MB04_DATA1)
787#define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val)
788#define bfin_read_CAN1_MB04_DATA2() bfin_read16(CAN1_MB04_DATA2)
789#define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val)
790#define bfin_read_CAN1_MB04_DATA3() bfin_read16(CAN1_MB04_DATA3)
791#define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val)
792#define bfin_read_CAN1_MB04_LENGTH() bfin_read16(CAN1_MB04_LENGTH)
793#define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val)
794#define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP)
795#define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val)
796#define bfin_read_CAN1_MB04_ID0() bfin_read16(CAN1_MB04_ID0)
797#define bfin_write_CAN1_MB04_ID0(val) bfin_write16(CAN1_MB04_ID0, val)
798#define bfin_read_CAN1_MB04_ID1() bfin_read16(CAN1_MB04_ID1)
799#define bfin_write_CAN1_MB04_ID1(val) bfin_write16(CAN1_MB04_ID1, val)
800#define bfin_read_CAN1_MB05_DATA0() bfin_read16(CAN1_MB05_DATA0)
801#define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val)
802#define bfin_read_CAN1_MB05_DATA1() bfin_read16(CAN1_MB05_DATA1)
803#define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val)
804#define bfin_read_CAN1_MB05_DATA2() bfin_read16(CAN1_MB05_DATA2)
805#define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val)
806#define bfin_read_CAN1_MB05_DATA3() bfin_read16(CAN1_MB05_DATA3)
807#define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val)
808#define bfin_read_CAN1_MB05_LENGTH() bfin_read16(CAN1_MB05_LENGTH)
809#define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val)
810#define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP)
811#define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val)
812#define bfin_read_CAN1_MB05_ID0() bfin_read16(CAN1_MB05_ID0)
813#define bfin_write_CAN1_MB05_ID0(val) bfin_write16(CAN1_MB05_ID0, val)
814#define bfin_read_CAN1_MB05_ID1() bfin_read16(CAN1_MB05_ID1)
815#define bfin_write_CAN1_MB05_ID1(val) bfin_write16(CAN1_MB05_ID1, val)
816#define bfin_read_CAN1_MB06_DATA0() bfin_read16(CAN1_MB06_DATA0)
817#define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val)
818#define bfin_read_CAN1_MB06_DATA1() bfin_read16(CAN1_MB06_DATA1)
819#define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val)
820#define bfin_read_CAN1_MB06_DATA2() bfin_read16(CAN1_MB06_DATA2)
821#define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val)
822#define bfin_read_CAN1_MB06_DATA3() bfin_read16(CAN1_MB06_DATA3)
823#define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val)
824#define bfin_read_CAN1_MB06_LENGTH() bfin_read16(CAN1_MB06_LENGTH)
825#define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val)
826#define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP)
827#define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val)
828#define bfin_read_CAN1_MB06_ID0() bfin_read16(CAN1_MB06_ID0)
829#define bfin_write_CAN1_MB06_ID0(val) bfin_write16(CAN1_MB06_ID0, val)
830#define bfin_read_CAN1_MB06_ID1() bfin_read16(CAN1_MB06_ID1)
831#define bfin_write_CAN1_MB06_ID1(val) bfin_write16(CAN1_MB06_ID1, val)
832#define bfin_read_CAN1_MB07_DATA0() bfin_read16(CAN1_MB07_DATA0)
833#define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val)
834#define bfin_read_CAN1_MB07_DATA1() bfin_read16(CAN1_MB07_DATA1)
835#define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val)
836#define bfin_read_CAN1_MB07_DATA2() bfin_read16(CAN1_MB07_DATA2)
837#define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val)
838#define bfin_read_CAN1_MB07_DATA3() bfin_read16(CAN1_MB07_DATA3)
839#define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val)
840#define bfin_read_CAN1_MB07_LENGTH() bfin_read16(CAN1_MB07_LENGTH)
841#define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val)
842#define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP)
843#define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val)
844#define bfin_read_CAN1_MB07_ID0() bfin_read16(CAN1_MB07_ID0)
845#define bfin_write_CAN1_MB07_ID0(val) bfin_write16(CAN1_MB07_ID0, val)
846#define bfin_read_CAN1_MB07_ID1() bfin_read16(CAN1_MB07_ID1)
847#define bfin_write_CAN1_MB07_ID1(val) bfin_write16(CAN1_MB07_ID1, val)
848#define bfin_read_CAN1_MB08_DATA0() bfin_read16(CAN1_MB08_DATA0)
849#define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val)
850#define bfin_read_CAN1_MB08_DATA1() bfin_read16(CAN1_MB08_DATA1)
851#define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val)
852#define bfin_read_CAN1_MB08_DATA2() bfin_read16(CAN1_MB08_DATA2)
853#define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val)
854#define bfin_read_CAN1_MB08_DATA3() bfin_read16(CAN1_MB08_DATA3)
855#define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val)
856#define bfin_read_CAN1_MB08_LENGTH() bfin_read16(CAN1_MB08_LENGTH)
857#define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val)
858#define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP)
859#define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val)
860#define bfin_read_CAN1_MB08_ID0() bfin_read16(CAN1_MB08_ID0)
861#define bfin_write_CAN1_MB08_ID0(val) bfin_write16(CAN1_MB08_ID0, val)
862#define bfin_read_CAN1_MB08_ID1() bfin_read16(CAN1_MB08_ID1)
863#define bfin_write_CAN1_MB08_ID1(val) bfin_write16(CAN1_MB08_ID1, val)
864#define bfin_read_CAN1_MB09_DATA0() bfin_read16(CAN1_MB09_DATA0)
865#define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val)
866#define bfin_read_CAN1_MB09_DATA1() bfin_read16(CAN1_MB09_DATA1)
867#define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val)
868#define bfin_read_CAN1_MB09_DATA2() bfin_read16(CAN1_MB09_DATA2)
869#define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val)
870#define bfin_read_CAN1_MB09_DATA3() bfin_read16(CAN1_MB09_DATA3)
871#define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val)
872#define bfin_read_CAN1_MB09_LENGTH() bfin_read16(CAN1_MB09_LENGTH)
873#define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val)
874#define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP)
875#define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val)
876#define bfin_read_CAN1_MB09_ID0() bfin_read16(CAN1_MB09_ID0)
877#define bfin_write_CAN1_MB09_ID0(val) bfin_write16(CAN1_MB09_ID0, val)
878#define bfin_read_CAN1_MB09_ID1() bfin_read16(CAN1_MB09_ID1)
879#define bfin_write_CAN1_MB09_ID1(val) bfin_write16(CAN1_MB09_ID1, val)
880#define bfin_read_CAN1_MB10_DATA0() bfin_read16(CAN1_MB10_DATA0)
881#define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val)
882#define bfin_read_CAN1_MB10_DATA1() bfin_read16(CAN1_MB10_DATA1)
883#define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val)
884#define bfin_read_CAN1_MB10_DATA2() bfin_read16(CAN1_MB10_DATA2)
885#define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val)
886#define bfin_read_CAN1_MB10_DATA3() bfin_read16(CAN1_MB10_DATA3)
887#define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val)
888#define bfin_read_CAN1_MB10_LENGTH() bfin_read16(CAN1_MB10_LENGTH)
889#define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val)
890#define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP)
891#define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val)
892#define bfin_read_CAN1_MB10_ID0() bfin_read16(CAN1_MB10_ID0)
893#define bfin_write_CAN1_MB10_ID0(val) bfin_write16(CAN1_MB10_ID0, val)
894#define bfin_read_CAN1_MB10_ID1() bfin_read16(CAN1_MB10_ID1)
895#define bfin_write_CAN1_MB10_ID1(val) bfin_write16(CAN1_MB10_ID1, val)
896#define bfin_read_CAN1_MB11_DATA0() bfin_read16(CAN1_MB11_DATA0)
897#define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val)
898#define bfin_read_CAN1_MB11_DATA1() bfin_read16(CAN1_MB11_DATA1)
899#define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val)
900#define bfin_read_CAN1_MB11_DATA2() bfin_read16(CAN1_MB11_DATA2)
901#define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val)
902#define bfin_read_CAN1_MB11_DATA3() bfin_read16(CAN1_MB11_DATA3)
903#define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val)
904#define bfin_read_CAN1_MB11_LENGTH() bfin_read16(CAN1_MB11_LENGTH)
905#define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val)
906#define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP)
907#define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val)
908#define bfin_read_CAN1_MB11_ID0() bfin_read16(CAN1_MB11_ID0)
909#define bfin_write_CAN1_MB11_ID0(val) bfin_write16(CAN1_MB11_ID0, val)
910#define bfin_read_CAN1_MB11_ID1() bfin_read16(CAN1_MB11_ID1)
911#define bfin_write_CAN1_MB11_ID1(val) bfin_write16(CAN1_MB11_ID1, val)
912#define bfin_read_CAN1_MB12_DATA0() bfin_read16(CAN1_MB12_DATA0)
913#define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val)
914#define bfin_read_CAN1_MB12_DATA1() bfin_read16(CAN1_MB12_DATA1)
915#define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val)
916#define bfin_read_CAN1_MB12_DATA2() bfin_read16(CAN1_MB12_DATA2)
917#define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val)
918#define bfin_read_CAN1_MB12_DATA3() bfin_read16(CAN1_MB12_DATA3)
919#define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val)
920#define bfin_read_CAN1_MB12_LENGTH() bfin_read16(CAN1_MB12_LENGTH)
921#define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val)
922#define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP)
923#define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val)
924#define bfin_read_CAN1_MB12_ID0() bfin_read16(CAN1_MB12_ID0)
925#define bfin_write_CAN1_MB12_ID0(val) bfin_write16(CAN1_MB12_ID0, val)
926#define bfin_read_CAN1_MB12_ID1() bfin_read16(CAN1_MB12_ID1)
927#define bfin_write_CAN1_MB12_ID1(val) bfin_write16(CAN1_MB12_ID1, val)
928#define bfin_read_CAN1_MB13_DATA0() bfin_read16(CAN1_MB13_DATA0)
929#define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val)
930#define bfin_read_CAN1_MB13_DATA1() bfin_read16(CAN1_MB13_DATA1)
931#define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val)
932#define bfin_read_CAN1_MB13_DATA2() bfin_read16(CAN1_MB13_DATA2)
933#define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val)
934#define bfin_read_CAN1_MB13_DATA3() bfin_read16(CAN1_MB13_DATA3)
935#define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val)
936#define bfin_read_CAN1_MB13_LENGTH() bfin_read16(CAN1_MB13_LENGTH)
937#define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val)
938#define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP)
939#define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val)
940#define bfin_read_CAN1_MB13_ID0() bfin_read16(CAN1_MB13_ID0)
941#define bfin_write_CAN1_MB13_ID0(val) bfin_write16(CAN1_MB13_ID0, val)
942#define bfin_read_CAN1_MB13_ID1() bfin_read16(CAN1_MB13_ID1)
943#define bfin_write_CAN1_MB13_ID1(val) bfin_write16(CAN1_MB13_ID1, val)
944#define bfin_read_CAN1_MB14_DATA0() bfin_read16(CAN1_MB14_DATA0)
945#define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val)
946#define bfin_read_CAN1_MB14_DATA1() bfin_read16(CAN1_MB14_DATA1)
947#define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val)
948#define bfin_read_CAN1_MB14_DATA2() bfin_read16(CAN1_MB14_DATA2)
949#define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val)
950#define bfin_read_CAN1_MB14_DATA3() bfin_read16(CAN1_MB14_DATA3)
951#define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val)
952#define bfin_read_CAN1_MB14_LENGTH() bfin_read16(CAN1_MB14_LENGTH)
953#define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val)
954#define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP)
955#define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val)
956#define bfin_read_CAN1_MB14_ID0() bfin_read16(CAN1_MB14_ID0)
957#define bfin_write_CAN1_MB14_ID0(val) bfin_write16(CAN1_MB14_ID0, val)
958#define bfin_read_CAN1_MB14_ID1() bfin_read16(CAN1_MB14_ID1)
959#define bfin_write_CAN1_MB14_ID1(val) bfin_write16(CAN1_MB14_ID1, val)
960#define bfin_read_CAN1_MB15_DATA0() bfin_read16(CAN1_MB15_DATA0)
961#define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val)
962#define bfin_read_CAN1_MB15_DATA1() bfin_read16(CAN1_MB15_DATA1)
963#define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val)
964#define bfin_read_CAN1_MB15_DATA2() bfin_read16(CAN1_MB15_DATA2)
965#define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val)
966#define bfin_read_CAN1_MB15_DATA3() bfin_read16(CAN1_MB15_DATA3)
967#define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val)
968#define bfin_read_CAN1_MB15_LENGTH() bfin_read16(CAN1_MB15_LENGTH)
969#define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val)
970#define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP)
971#define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val)
972#define bfin_read_CAN1_MB15_ID0() bfin_read16(CAN1_MB15_ID0)
973#define bfin_write_CAN1_MB15_ID0(val) bfin_write16(CAN1_MB15_ID0, val)
974#define bfin_read_CAN1_MB15_ID1() bfin_read16(CAN1_MB15_ID1)
975#define bfin_write_CAN1_MB15_ID1(val) bfin_write16(CAN1_MB15_ID1, val)
976
977/* CAN Controller 1 Mailbox Data Registers */
978
979#define bfin_read_CAN1_MB16_DATA0() bfin_read16(CAN1_MB16_DATA0)
980#define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val)
981#define bfin_read_CAN1_MB16_DATA1() bfin_read16(CAN1_MB16_DATA1)
982#define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val)
983#define bfin_read_CAN1_MB16_DATA2() bfin_read16(CAN1_MB16_DATA2)
984#define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val)
985#define bfin_read_CAN1_MB16_DATA3() bfin_read16(CAN1_MB16_DATA3)
986#define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val)
987#define bfin_read_CAN1_MB16_LENGTH() bfin_read16(CAN1_MB16_LENGTH)
988#define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val)
989#define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP)
990#define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val)
991#define bfin_read_CAN1_MB16_ID0() bfin_read16(CAN1_MB16_ID0)
992#define bfin_write_CAN1_MB16_ID0(val) bfin_write16(CAN1_MB16_ID0, val)
993#define bfin_read_CAN1_MB16_ID1() bfin_read16(CAN1_MB16_ID1)
994#define bfin_write_CAN1_MB16_ID1(val) bfin_write16(CAN1_MB16_ID1, val)
995#define bfin_read_CAN1_MB17_DATA0() bfin_read16(CAN1_MB17_DATA0)
996#define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val)
997#define bfin_read_CAN1_MB17_DATA1() bfin_read16(CAN1_MB17_DATA1)
998#define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val)
999#define bfin_read_CAN1_MB17_DATA2() bfin_read16(CAN1_MB17_DATA2)
1000#define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val)
1001#define bfin_read_CAN1_MB17_DATA3() bfin_read16(CAN1_MB17_DATA3)
1002#define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val)
1003#define bfin_read_CAN1_MB17_LENGTH() bfin_read16(CAN1_MB17_LENGTH)
1004#define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val)
1005#define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP)
1006#define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val)
1007#define bfin_read_CAN1_MB17_ID0() bfin_read16(CAN1_MB17_ID0)
1008#define bfin_write_CAN1_MB17_ID0(val) bfin_write16(CAN1_MB17_ID0, val)
1009#define bfin_read_CAN1_MB17_ID1() bfin_read16(CAN1_MB17_ID1)
1010#define bfin_write_CAN1_MB17_ID1(val) bfin_write16(CAN1_MB17_ID1, val)
1011#define bfin_read_CAN1_MB18_DATA0() bfin_read16(CAN1_MB18_DATA0)
1012#define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val)
1013#define bfin_read_CAN1_MB18_DATA1() bfin_read16(CAN1_MB18_DATA1)
1014#define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val)
1015#define bfin_read_CAN1_MB18_DATA2() bfin_read16(CAN1_MB18_DATA2)
1016#define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val)
1017#define bfin_read_CAN1_MB18_DATA3() bfin_read16(CAN1_MB18_DATA3)
1018#define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val)
1019#define bfin_read_CAN1_MB18_LENGTH() bfin_read16(CAN1_MB18_LENGTH)
1020#define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val)
1021#define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP)
1022#define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val)
1023#define bfin_read_CAN1_MB18_ID0() bfin_read16(CAN1_MB18_ID0)
1024#define bfin_write_CAN1_MB18_ID0(val) bfin_write16(CAN1_MB18_ID0, val)
1025#define bfin_read_CAN1_MB18_ID1() bfin_read16(CAN1_MB18_ID1)
1026#define bfin_write_CAN1_MB18_ID1(val) bfin_write16(CAN1_MB18_ID1, val)
1027#define bfin_read_CAN1_MB19_DATA0() bfin_read16(CAN1_MB19_DATA0)
1028#define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val)
1029#define bfin_read_CAN1_MB19_DATA1() bfin_read16(CAN1_MB19_DATA1)
1030#define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val)
1031#define bfin_read_CAN1_MB19_DATA2() bfin_read16(CAN1_MB19_DATA2)
1032#define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val)
1033#define bfin_read_CAN1_MB19_DATA3() bfin_read16(CAN1_MB19_DATA3)
1034#define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val)
1035#define bfin_read_CAN1_MB19_LENGTH() bfin_read16(CAN1_MB19_LENGTH)
1036#define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val)
1037#define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP)
1038#define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val)
1039#define bfin_read_CAN1_MB19_ID0() bfin_read16(CAN1_MB19_ID0)
1040#define bfin_write_CAN1_MB19_ID0(val) bfin_write16(CAN1_MB19_ID0, val)
1041#define bfin_read_CAN1_MB19_ID1() bfin_read16(CAN1_MB19_ID1)
1042#define bfin_write_CAN1_MB19_ID1(val) bfin_write16(CAN1_MB19_ID1, val)
1043#define bfin_read_CAN1_MB20_DATA0() bfin_read16(CAN1_MB20_DATA0)
1044#define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val)
1045#define bfin_read_CAN1_MB20_DATA1() bfin_read16(CAN1_MB20_DATA1)
1046#define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val)
1047#define bfin_read_CAN1_MB20_DATA2() bfin_read16(CAN1_MB20_DATA2)
1048#define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val)
1049#define bfin_read_CAN1_MB20_DATA3() bfin_read16(CAN1_MB20_DATA3)
1050#define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val)
1051#define bfin_read_CAN1_MB20_LENGTH() bfin_read16(CAN1_MB20_LENGTH)
1052#define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val)
1053#define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP)
1054#define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val)
1055#define bfin_read_CAN1_MB20_ID0() bfin_read16(CAN1_MB20_ID0)
1056#define bfin_write_CAN1_MB20_ID0(val) bfin_write16(CAN1_MB20_ID0, val)
1057#define bfin_read_CAN1_MB20_ID1() bfin_read16(CAN1_MB20_ID1)
1058#define bfin_write_CAN1_MB20_ID1(val) bfin_write16(CAN1_MB20_ID1, val)
1059#define bfin_read_CAN1_MB21_DATA0() bfin_read16(CAN1_MB21_DATA0)
1060#define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val)
1061#define bfin_read_CAN1_MB21_DATA1() bfin_read16(CAN1_MB21_DATA1)
1062#define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val)
1063#define bfin_read_CAN1_MB21_DATA2() bfin_read16(CAN1_MB21_DATA2)
1064#define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val)
1065#define bfin_read_CAN1_MB21_DATA3() bfin_read16(CAN1_MB21_DATA3)
1066#define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val)
1067#define bfin_read_CAN1_MB21_LENGTH() bfin_read16(CAN1_MB21_LENGTH)
1068#define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val)
1069#define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP)
1070#define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val)
1071#define bfin_read_CAN1_MB21_ID0() bfin_read16(CAN1_MB21_ID0)
1072#define bfin_write_CAN1_MB21_ID0(val) bfin_write16(CAN1_MB21_ID0, val)
1073#define bfin_read_CAN1_MB21_ID1() bfin_read16(CAN1_MB21_ID1)
1074#define bfin_write_CAN1_MB21_ID1(val) bfin_write16(CAN1_MB21_ID1, val)
1075#define bfin_read_CAN1_MB22_DATA0() bfin_read16(CAN1_MB22_DATA0)
1076#define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val)
1077#define bfin_read_CAN1_MB22_DATA1() bfin_read16(CAN1_MB22_DATA1)
1078#define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val)
1079#define bfin_read_CAN1_MB22_DATA2() bfin_read16(CAN1_MB22_DATA2)
1080#define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val)
1081#define bfin_read_CAN1_MB22_DATA3() bfin_read16(CAN1_MB22_DATA3)
1082#define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val)
1083#define bfin_read_CAN1_MB22_LENGTH() bfin_read16(CAN1_MB22_LENGTH)
1084#define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val)
1085#define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP)
1086#define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val)
1087#define bfin_read_CAN1_MB22_ID0() bfin_read16(CAN1_MB22_ID0)
1088#define bfin_write_CAN1_MB22_ID0(val) bfin_write16(CAN1_MB22_ID0, val)
1089#define bfin_read_CAN1_MB22_ID1() bfin_read16(CAN1_MB22_ID1)
1090#define bfin_write_CAN1_MB22_ID1(val) bfin_write16(CAN1_MB22_ID1, val)
1091#define bfin_read_CAN1_MB23_DATA0() bfin_read16(CAN1_MB23_DATA0)
1092#define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val)
1093#define bfin_read_CAN1_MB23_DATA1() bfin_read16(CAN1_MB23_DATA1)
1094#define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val)
1095#define bfin_read_CAN1_MB23_DATA2() bfin_read16(CAN1_MB23_DATA2)
1096#define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val)
1097#define bfin_read_CAN1_MB23_DATA3() bfin_read16(CAN1_MB23_DATA3)
1098#define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val)
1099#define bfin_read_CAN1_MB23_LENGTH() bfin_read16(CAN1_MB23_LENGTH)
1100#define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val)
1101#define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP)
1102#define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val)
1103#define bfin_read_CAN1_MB23_ID0() bfin_read16(CAN1_MB23_ID0)
1104#define bfin_write_CAN1_MB23_ID0(val) bfin_write16(CAN1_MB23_ID0, val)
1105#define bfin_read_CAN1_MB23_ID1() bfin_read16(CAN1_MB23_ID1)
1106#define bfin_write_CAN1_MB23_ID1(val) bfin_write16(CAN1_MB23_ID1, val)
1107#define bfin_read_CAN1_MB24_DATA0() bfin_read16(CAN1_MB24_DATA0)
1108#define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val)
1109#define bfin_read_CAN1_MB24_DATA1() bfin_read16(CAN1_MB24_DATA1)
1110#define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val)
1111#define bfin_read_CAN1_MB24_DATA2() bfin_read16(CAN1_MB24_DATA2)
1112#define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val)
1113#define bfin_read_CAN1_MB24_DATA3() bfin_read16(CAN1_MB24_DATA3)
1114#define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val)
1115#define bfin_read_CAN1_MB24_LENGTH() bfin_read16(CAN1_MB24_LENGTH)
1116#define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val)
1117#define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP)
1118#define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val)
1119#define bfin_read_CAN1_MB24_ID0() bfin_read16(CAN1_MB24_ID0)
1120#define bfin_write_CAN1_MB24_ID0(val) bfin_write16(CAN1_MB24_ID0, val)
1121#define bfin_read_CAN1_MB24_ID1() bfin_read16(CAN1_MB24_ID1)
1122#define bfin_write_CAN1_MB24_ID1(val) bfin_write16(CAN1_MB24_ID1, val)
1123#define bfin_read_CAN1_MB25_DATA0() bfin_read16(CAN1_MB25_DATA0)
1124#define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val)
1125#define bfin_read_CAN1_MB25_DATA1() bfin_read16(CAN1_MB25_DATA1)
1126#define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val)
1127#define bfin_read_CAN1_MB25_DATA2() bfin_read16(CAN1_MB25_DATA2)
1128#define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val)
1129#define bfin_read_CAN1_MB25_DATA3() bfin_read16(CAN1_MB25_DATA3)
1130#define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val)
1131#define bfin_read_CAN1_MB25_LENGTH() bfin_read16(CAN1_MB25_LENGTH)
1132#define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val)
1133#define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP)
1134#define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val)
1135#define bfin_read_CAN1_MB25_ID0() bfin_read16(CAN1_MB25_ID0)
1136#define bfin_write_CAN1_MB25_ID0(val) bfin_write16(CAN1_MB25_ID0, val)
1137#define bfin_read_CAN1_MB25_ID1() bfin_read16(CAN1_MB25_ID1)
1138#define bfin_write_CAN1_MB25_ID1(val) bfin_write16(CAN1_MB25_ID1, val)
1139#define bfin_read_CAN1_MB26_DATA0() bfin_read16(CAN1_MB26_DATA0)
1140#define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val)
1141#define bfin_read_CAN1_MB26_DATA1() bfin_read16(CAN1_MB26_DATA1)
1142#define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val)
1143#define bfin_read_CAN1_MB26_DATA2() bfin_read16(CAN1_MB26_DATA2)
1144#define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val)
1145#define bfin_read_CAN1_MB26_DATA3() bfin_read16(CAN1_MB26_DATA3)
1146#define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val)
1147#define bfin_read_CAN1_MB26_LENGTH() bfin_read16(CAN1_MB26_LENGTH)
1148#define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val)
1149#define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP)
1150#define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val)
1151#define bfin_read_CAN1_MB26_ID0() bfin_read16(CAN1_MB26_ID0)
1152#define bfin_write_CAN1_MB26_ID0(val) bfin_write16(CAN1_MB26_ID0, val)
1153#define bfin_read_CAN1_MB26_ID1() bfin_read16(CAN1_MB26_ID1)
1154#define bfin_write_CAN1_MB26_ID1(val) bfin_write16(CAN1_MB26_ID1, val)
1155#define bfin_read_CAN1_MB27_DATA0() bfin_read16(CAN1_MB27_DATA0)
1156#define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val)
1157#define bfin_read_CAN1_MB27_DATA1() bfin_read16(CAN1_MB27_DATA1)
1158#define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val)
1159#define bfin_read_CAN1_MB27_DATA2() bfin_read16(CAN1_MB27_DATA2)
1160#define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val)
1161#define bfin_read_CAN1_MB27_DATA3() bfin_read16(CAN1_MB27_DATA3)
1162#define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val)
1163#define bfin_read_CAN1_MB27_LENGTH() bfin_read16(CAN1_MB27_LENGTH)
1164#define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val)
1165#define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP)
1166#define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val)
1167#define bfin_read_CAN1_MB27_ID0() bfin_read16(CAN1_MB27_ID0)
1168#define bfin_write_CAN1_MB27_ID0(val) bfin_write16(CAN1_MB27_ID0, val)
1169#define bfin_read_CAN1_MB27_ID1() bfin_read16(CAN1_MB27_ID1)
1170#define bfin_write_CAN1_MB27_ID1(val) bfin_write16(CAN1_MB27_ID1, val)
1171#define bfin_read_CAN1_MB28_DATA0() bfin_read16(CAN1_MB28_DATA0)
1172#define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val)
1173#define bfin_read_CAN1_MB28_DATA1() bfin_read16(CAN1_MB28_DATA1)
1174#define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val)
1175#define bfin_read_CAN1_MB28_DATA2() bfin_read16(CAN1_MB28_DATA2)
1176#define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val)
1177#define bfin_read_CAN1_MB28_DATA3() bfin_read16(CAN1_MB28_DATA3)
1178#define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val)
1179#define bfin_read_CAN1_MB28_LENGTH() bfin_read16(CAN1_MB28_LENGTH)
1180#define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val)
1181#define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP)
1182#define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val)
1183#define bfin_read_CAN1_MB28_ID0() bfin_read16(CAN1_MB28_ID0)
1184#define bfin_write_CAN1_MB28_ID0(val) bfin_write16(CAN1_MB28_ID0, val)
1185#define bfin_read_CAN1_MB28_ID1() bfin_read16(CAN1_MB28_ID1)
1186#define bfin_write_CAN1_MB28_ID1(val) bfin_write16(CAN1_MB28_ID1, val)
1187#define bfin_read_CAN1_MB29_DATA0() bfin_read16(CAN1_MB29_DATA0)
1188#define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val)
1189#define bfin_read_CAN1_MB29_DATA1() bfin_read16(CAN1_MB29_DATA1)
1190#define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val)
1191#define bfin_read_CAN1_MB29_DATA2() bfin_read16(CAN1_MB29_DATA2)
1192#define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val)
1193#define bfin_read_CAN1_MB29_DATA3() bfin_read16(CAN1_MB29_DATA3)
1194#define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val)
1195#define bfin_read_CAN1_MB29_LENGTH() bfin_read16(CAN1_MB29_LENGTH)
1196#define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val)
1197#define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP)
1198#define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val)
1199#define bfin_read_CAN1_MB29_ID0() bfin_read16(CAN1_MB29_ID0)
1200#define bfin_write_CAN1_MB29_ID0(val) bfin_write16(CAN1_MB29_ID0, val)
1201#define bfin_read_CAN1_MB29_ID1() bfin_read16(CAN1_MB29_ID1)
1202#define bfin_write_CAN1_MB29_ID1(val) bfin_write16(CAN1_MB29_ID1, val)
1203#define bfin_read_CAN1_MB30_DATA0() bfin_read16(CAN1_MB30_DATA0)
1204#define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val)
1205#define bfin_read_CAN1_MB30_DATA1() bfin_read16(CAN1_MB30_DATA1)
1206#define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val)
1207#define bfin_read_CAN1_MB30_DATA2() bfin_read16(CAN1_MB30_DATA2)
1208#define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val)
1209#define bfin_read_CAN1_MB30_DATA3() bfin_read16(CAN1_MB30_DATA3)
1210#define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val)
1211#define bfin_read_CAN1_MB30_LENGTH() bfin_read16(CAN1_MB30_LENGTH)
1212#define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val)
1213#define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP)
1214#define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val)
1215#define bfin_read_CAN1_MB30_ID0() bfin_read16(CAN1_MB30_ID0)
1216#define bfin_write_CAN1_MB30_ID0(val) bfin_write16(CAN1_MB30_ID0, val)
1217#define bfin_read_CAN1_MB30_ID1() bfin_read16(CAN1_MB30_ID1)
1218#define bfin_write_CAN1_MB30_ID1(val) bfin_write16(CAN1_MB30_ID1, val)
1219#define bfin_read_CAN1_MB31_DATA0() bfin_read16(CAN1_MB31_DATA0)
1220#define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val)
1221#define bfin_read_CAN1_MB31_DATA1() bfin_read16(CAN1_MB31_DATA1)
1222#define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val)
1223#define bfin_read_CAN1_MB31_DATA2() bfin_read16(CAN1_MB31_DATA2)
1224#define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val)
1225#define bfin_read_CAN1_MB31_DATA3() bfin_read16(CAN1_MB31_DATA3)
1226#define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val)
1227#define bfin_read_CAN1_MB31_LENGTH() bfin_read16(CAN1_MB31_LENGTH)
1228#define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val)
1229#define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP)
1230#define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val)
1231#define bfin_read_CAN1_MB31_ID0() bfin_read16(CAN1_MB31_ID0)
1232#define bfin_write_CAN1_MB31_ID0(val) bfin_write16(CAN1_MB31_ID0, val)
1233#define bfin_read_CAN1_MB31_ID1() bfin_read16(CAN1_MB31_ID1)
1234#define bfin_write_CAN1_MB31_ID1(val) bfin_write16(CAN1_MB31_ID1, val)
1235
1236/* ATAPI Registers */
1237
1238#define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL)
1239#define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val)
1240#define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS)
1241#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val)
1242#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR)
1243#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
1244#define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF)
1245#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
1246#define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF)
1247#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
1248#define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK)
1249#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
1250#define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS)
1251#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
1252#define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN)
1253#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
1254#define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS)
1255#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
1256#define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE)
1257#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
1258#define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE)
1259#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
1260#define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT)
1261#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
1262#define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT)
1263#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
1264#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT)
1265#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
1266#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT)
1267#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
1268#define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0)
1269#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
1270#define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0)
1271#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
1272#define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1)
1273#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
1274#define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0)
1275#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
1276#define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1)
1277#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
1278#define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2)
1279#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
1280#define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0)
1281#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
1282#define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1)
1283#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
1284#define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2)
1285#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
1286#define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3)
1287#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
1288
1289/* SDH Registers */
1290
1291#define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL)
1292#define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val)
1293#define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL)
1294#define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val)
1295#define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT)
1296#define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val)
1297#define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND)
1298#define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val)
1299#define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD)
1300#define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val)
1301#define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0)
1302#define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val)
1303#define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1)
1304#define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val)
1305#define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2)
1306#define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val)
1307#define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3)
1308#define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val)
1309#define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER)
1310#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
1311#define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH)
1312#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val)
1313#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL)
1314#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val)
1315#define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT)
1316#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val)
1317#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS)
1318#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val)
1319#define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR)
1320#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val)
1321#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0)
1322#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val)
1323#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1)
1324#define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val)
1325#define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT)
1326#define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val)
1327#define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO)
1328#define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val)
1329#define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS)
1330#define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val)
1331#define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK)
1332#define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val)
1333#define bfin_read_SDH_CFG() bfin_read16(SDH_CFG)
1334#define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val)
1335#define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN)
1336#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
1337#define bfin_read_SDH_PID0() bfin_read16(SDH_PID0)
1338#define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val)
1339#define bfin_read_SDH_PID1() bfin_read16(SDH_PID1)
1340#define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val)
1341#define bfin_read_SDH_PID2() bfin_read16(SDH_PID2)
1342#define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val)
1343#define bfin_read_SDH_PID3() bfin_read16(SDH_PID3)
1344#define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val)
1345#define bfin_read_SDH_PID4() bfin_read16(SDH_PID4)
1346#define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val)
1347#define bfin_read_SDH_PID5() bfin_read16(SDH_PID5)
1348#define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val)
1349#define bfin_read_SDH_PID6() bfin_read16(SDH_PID6)
1350#define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val)
1351#define bfin_read_SDH_PID7() bfin_read16(SDH_PID7)
1352#define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val)
1353
1354/* HOST Port Registers */
1355
1356#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
1357#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
1358#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
1359#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
1360#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
1361#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
1362
1363/* USB Control Registers */
1364
1365#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
1366#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
1367#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
1368#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
1369#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
1370#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
1371#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
1372#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
1373#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
1374#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
1375#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
1376#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
1377#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
1378#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
1379#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
1380#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
1381#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
1382#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
1383#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
1384#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
1385#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
1386#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
1387#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
1388#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
1389#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
1390#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
1391
1392/* USB Packet Control Registers */
1393
1394#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
1395#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
1396#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
1397#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
1398#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
1399#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
1400#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
1401#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
1402#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
1403#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
1404#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
1405#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
1406#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
1407#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
1408#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
1409#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
1410#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
1411#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
1412#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
1413#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
1414#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
1415#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
1416#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
1417#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
1418#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
1419#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
1420
1421/* USB Endbfin_read_()oint FIFO Registers */
1422
1423#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
1424#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
1425#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
1426#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
1427#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
1428#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
1429#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
1430#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
1431#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
1432#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
1433#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
1434#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
1435#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
1436#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
1437#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
1438#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
1439
1440/* USB OTG Control Registers */
1441
1442#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
1443#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
1444#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
1445#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
1446#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
1447#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
1448
1449/* USB Phy Control Registers */
1450
1451#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
1452#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
1453#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
1454#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
1455#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
1456#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
1457#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
1458#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
1459#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
1460#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
1461
1462/* (APHY_CNTRL is for ADI usage only) */
1463
1464#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
1465#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
1466
1467/* (APHY_CALIB is for ADI usage only) */
1468
1469#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
1470#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
1471#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
1472#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
1473
1474/* (PHY_TEST is for ADI usage only) */
1475
1476#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST)
1477#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val)
1478#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
1479#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
1480#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
1481#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
1482
1483/* USB Endbfin_read_()oint 0 Control Registers */
1484
1485#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
1486#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
1487#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
1488#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
1489#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
1490#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
1491#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
1492#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
1493#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
1494#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
1495#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
1496#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
1497#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
1498#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
1499#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
1500#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
1501#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
1502#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
1503
1504/* USB Endbfin_read_()oint 1 Control Registers */
1505
1506#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
1507#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
1508#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
1509#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
1510#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
1511#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
1512#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
1513#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
1514#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
1515#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
1516#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
1517#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
1518#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
1519#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
1520#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
1521#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
1522#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
1523#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
1524#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
1525#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
1526
1527/* USB Endbfin_read_()oint 2 Control Registers */
1528
1529#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
1530#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
1531#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
1532#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
1533#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
1534#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
1535#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
1536#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
1537#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
1538#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
1539#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
1540#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
1541#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
1542#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
1543#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
1544#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
1545#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
1546#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
1547#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
1548#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
1549
1550/* USB Endbfin_read_()oint 3 Control Registers */
1551
1552#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
1553#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
1554#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
1555#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
1556#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
1557#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
1558#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
1559#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
1560#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
1561#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
1562#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
1563#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
1564#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
1565#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
1566#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
1567#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
1568#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
1569#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
1570#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
1571#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
1572
1573/* USB Endbfin_read_()oint 4 Control Registers */
1574
1575#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
1576#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
1577#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
1578#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
1579#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
1580#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
1581#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
1582#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
1583#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
1584#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
1585#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
1586#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
1587#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
1588#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
1589#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
1590#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
1591#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
1592#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
1593#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
1594#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
1595
1596/* USB Endbfin_read_()oint 5 Control Registers */
1597
1598#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
1599#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
1600#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
1601#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
1602#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
1603#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
1604#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
1605#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
1606#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
1607#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
1608#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
1609#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
1610#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
1611#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
1612#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
1613#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
1614#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
1615#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
1616#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
1617#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
1618
1619/* USB Endbfin_read_()oint 6 Control Registers */
1620
1621#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
1622#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
1623#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
1624#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
1625#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
1626#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
1627#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
1628#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
1629#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
1630#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
1631#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
1632#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
1633#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
1634#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
1635#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
1636#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
1637#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
1638#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
1639#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
1640#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
1641
1642/* USB Endbfin_read_()oint 7 Control Registers */
1643
1644#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
1645#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
1646#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
1647#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
1648#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
1649#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
1650#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
1651#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
1652#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
1653#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
1654#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
1655#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
1656#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
1657#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
1658#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
1659#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
1660#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
1661#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
1662#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
1663#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
1664#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
1665#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
1666#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
1667#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
1668
1669/* USB Channel 0 Config Registers */
1670
1671#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL)
1672#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val)
1673#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW)
1674#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val)
1675#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH)
1676#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val)
1677#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW)
1678#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val)
1679#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH)
1680#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val)
1681
1682/* USB Channel 1 Config Registers */
1683
1684#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL)
1685#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val)
1686#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW)
1687#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val)
1688#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH)
1689#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val)
1690#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW)
1691#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val)
1692#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH)
1693#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val)
1694
1695/* USB Channel 2 Config Registers */
1696
1697#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL)
1698#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val)
1699#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW)
1700#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val)
1701#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH)
1702#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val)
1703#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW)
1704#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val)
1705#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH)
1706#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val)
1707
1708/* USB Channel 3 Config Registers */
1709
1710#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL)
1711#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val)
1712#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW)
1713#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val)
1714#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH)
1715#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val)
1716#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW)
1717#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val)
1718#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH)
1719#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val)
1720
1721/* USB Channel 4 Config Registers */
1722
1723#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL)
1724#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val)
1725#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW)
1726#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val)
1727#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH)
1728#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val)
1729#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW)
1730#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val)
1731#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH)
1732#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val)
1733
1734/* USB Channel 5 Config Registers */
1735
1736#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL)
1737#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val)
1738#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW)
1739#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val)
1740#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH)
1741#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val)
1742#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW)
1743#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val)
1744#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH)
1745#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val)
1746
1747/* USB Channel 6 Config Registers */
1748
1749#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL)
1750#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val)
1751#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW)
1752#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val)
1753#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH)
1754#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val)
1755#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW)
1756#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val)
1757#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH)
1758#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val)
1759
1760/* USB Channel 7 Config Registers */
1761
1762#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL)
1763#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val)
1764#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW)
1765#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val)
1766#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH)
1767#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val)
1768#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW)
1769#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val)
1770#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH)
1771#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val)
1772
1773/* Keybfin_read_()ad Registers */
1774
1775#define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL)
1776#define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val)
1777#define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE)
1778#define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val)
1779#define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL)
1780#define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val)
1781#define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL)
1782#define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val)
1783#define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT)
1784#define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val)
1785#define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL)
1786#define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val)
1787
1788/* Pixel Combfin_read_()ositor (PIXC) Registers */
1789
1790#define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL)
1791#define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val)
1792#define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL)
1793#define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val)
1794#define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF)
1795#define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val)
1796#define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART)
1797#define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val)
1798#define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND)
1799#define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val)
1800#define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART)
1801#define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val)
1802#define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND)
1803#define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val)
1804#define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP)
1805#define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val)
1806#define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART)
1807#define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val)
1808#define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND)
1809#define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val)
1810#define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART)
1811#define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val)
1812#define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND)
1813#define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val)
1814#define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP)
1815#define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val)
1816#define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT)
1817#define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val)
1818#define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON)
1819#define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val)
1820#define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON)
1821#define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val)
1822#define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON)
1823#define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val)
1824#define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS)
1825#define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val)
1826#define bfin_read_PIXC_TC() bfin_read32(PIXC_TC)
1827#define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val)
1828
1829/* Handshake MDMA 0 Registers */
1830
1831#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
1832#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
1833#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
1834#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
1835#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
1836#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
1837#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
1838#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
1839#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
1840#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
1841#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
1842#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
1843#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
1844#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
1845
1846/* Handshake MDMA 1 Registers */
1847
1848#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
1849#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
1850#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
1851#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
1852#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
1853#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
1854#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
1855#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
1856#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
1857#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
1858#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
1859#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
1860#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
1861#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
1862
1863#endif /* _CDEF_BF549_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
new file mode 100644
index 000000000000..57ac8cb9b1f6
--- /dev/null
+++ b/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
@@ -0,0 +1,2750 @@
1/*
2 * File: include/asm-blackfin/mach-bf548/cdefBF54x_base.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _CDEF_BF54X_H
32#define _CDEF_BF54X_H
33
34#include <asm/blackfin.h>
35
36#include "defBF54x_base.h"
37#include <asm/system.h>
38
39/* ************************************************************** */
40/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */
41/* ************************************************************** */
42
43/* PLL Registers */
44
45#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
46/* Writing to PLL_CTL initiates a PLL relock sequence. */
47static __inline__ void bfin_write_PLL_CTL(unsigned int val)
48{
49 unsigned long flags, iwr0, iwr1, iwr2;
50
51 if (val == bfin_read_PLL_CTL())
52 return;
53
54 local_irq_save(flags);
55 /* Enable the PLL Wakeup bit in SIC IWR */
56 iwr0 = bfin_read32(SIC_IWR0);
57 iwr1 = bfin_read32(SIC_IWR1);
58 iwr2 = bfin_read32(SIC_IWR2);
59 /* Only allow PPL Wakeup) */
60 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
61 bfin_write32(SIC_IWR1, 0);
62 bfin_write32(SIC_IWR2, 0);
63
64 bfin_write16(PLL_CTL, val);
65 SSYNC();
66 asm("IDLE;");
67
68 bfin_write32(SIC_IWR0, iwr0);
69 bfin_write32(SIC_IWR1, iwr1);
70 bfin_write32(SIC_IWR2, iwr2);
71 local_irq_restore(flags);
72}
73#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
74#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
75#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
76/* Writing to VR_CTL initiates a PLL relock sequence. */
77static __inline__ void bfin_write_VR_CTL(unsigned int val)
78{
79 unsigned long flags, iwr0, iwr1, iwr2;
80
81 if (val == bfin_read_VR_CTL())
82 return;
83
84 local_irq_save(flags);
85 /* Enable the PLL Wakeup bit in SIC IWR */
86 iwr0 = bfin_read32(SIC_IWR0);
87 iwr1 = bfin_read32(SIC_IWR1);
88 iwr2 = bfin_read32(SIC_IWR2);
89 /* Only allow PPL Wakeup) */
90 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
91 bfin_write32(SIC_IWR1, 0);
92 bfin_write32(SIC_IWR2, 0);
93
94 bfin_write16(VR_CTL, val);
95 SSYNC();
96 asm("IDLE;");
97
98 bfin_write32(SIC_IWR0, iwr0);
99 bfin_write32(SIC_IWR1, iwr1);
100 bfin_write32(SIC_IWR2, iwr2);
101 local_irq_restore(flags);
102}
103#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
104#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
105#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
106#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
107
108/* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */
109
110#define bfin_read_CHIPID() bfin_read32(CHIPID)
111#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
112
113/* System Reset and Interrubfin_read_()t Controller (0xFFC00100 - 0xFFC00104) */
114
115#define bfin_read_SWRST() bfin_read16(SWRST)
116#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
117#define bfin_read_SYSCR() bfin_read16(SYSCR)
118#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
119
120/* SIC Registers */
121
122#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
123#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
124#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
125#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
126#define bfin_read_SIC_IMASK2() bfin_read32(SIC_IMASK2)
127#define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val)
128#define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 2))
129#define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 2)), val)
130
131#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
132#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
133#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
134#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
135#define bfin_read_SIC_ISR2() bfin_read32(SIC_ISR2)
136#define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val)
137#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 2))
138#define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 2)), val)
139
140#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
141#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
142#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
143#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
144#define bfin_read_SIC_IWR2() bfin_read32(SIC_IWR2)
145#define bfin_write_SIC_IWR2(val) bfin_write32(SIC_IWR2, val)
146#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
147#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
148#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
149#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
150#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
151#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
152#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
153#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
154#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
155#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
156#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
157#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
158#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
159#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
160#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
161#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val)
162#define bfin_read_SIC_IAR8() bfin_read32(SIC_IAR8)
163#define bfin_write_SIC_IAR8(val) bfin_write32(SIC_IAR8, val)
164#define bfin_read_SIC_IAR9() bfin_read32(SIC_IAR9)
165#define bfin_write_SIC_IAR9(val) bfin_write32(SIC_IAR9, val)
166#define bfin_read_SIC_IAR10() bfin_read32(SIC_IAR10)
167#define bfin_write_SIC_IAR10(val) bfin_write32(SIC_IAR10, val)
168#define bfin_read_SIC_IAR11() bfin_read32(SIC_IAR11)
169#define bfin_write_SIC_IAR11(val) bfin_write32(SIC_IAR11, val)
170
171/* Watchdog Timer Registers */
172
173#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
174#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
175#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
176#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
177#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
178#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
179
180/* RTC Registers */
181
182#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
183#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
184#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
185#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
186#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
187#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
188#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
189#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
190#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
191#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
192#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
193#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
194
195/* UART0 Registers */
196
197#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
198#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
199#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
200#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
201#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
202#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
203#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
204#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
205#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
206#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
207#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
208#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
209#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
210#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val)
211#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
212#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
213#define bfin_read_UART0_IER_SET() bfin_read16(UART0_IER_SET)
214#define bfin_write_UART0_IER_SET(val) bfin_write16(UART0_IER_SET, val)
215#define bfin_read_UART0_IER_CLEAR() bfin_read16(UART0_IER_CLEAR)
216#define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val)
217#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
218#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
219#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
220#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
221
222/* SPI0 Registers */
223
224#define bfin_read_SPI0_CTL() bfin_read16(SPI0_CTL)
225#define bfin_write_SPI0_CTL(val) bfin_write16(SPI0_CTL, val)
226#define bfin_read_SPI0_FLG() bfin_read16(SPI0_FLG)
227#define bfin_write_SPI0_FLG(val) bfin_write16(SPI0_FLG, val)
228#define bfin_read_SPI0_STAT() bfin_read16(SPI0_STAT)
229#define bfin_write_SPI0_STAT(val) bfin_write16(SPI0_STAT, val)
230#define bfin_read_SPI0_TDBR() bfin_read16(SPI0_TDBR)
231#define bfin_write_SPI0_TDBR(val) bfin_write16(SPI0_TDBR, val)
232#define bfin_read_SPI0_RDBR() bfin_read16(SPI0_RDBR)
233#define bfin_write_SPI0_RDBR(val) bfin_write16(SPI0_RDBR, val)
234#define bfin_read_SPI0_BAUD() bfin_read16(SPI0_BAUD)
235#define bfin_write_SPI0_BAUD(val) bfin_write16(SPI0_BAUD, val)
236#define bfin_read_SPI0_SHADOW() bfin_read16(SPI0_SHADOW)
237#define bfin_write_SPI0_SHADOW(val) bfin_write16(SPI0_SHADOW, val)
238
239/* Timer Groubfin_read_() of 3 registers are not defined in the shared file because they are not available on the ADSP-BF542 processor */
240
241/* Two Wire Interface Registers (TWI0) */
242
243/* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */
244
245/* SPORT1 Registers */
246
247#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
248#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
249#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
250#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
251#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
252#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
253#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
254#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
255#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
256#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
257#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
258#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
259#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
260#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
261#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
262#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
263#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
264#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
265#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
266#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
267#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
268#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
269#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
270#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
271#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
272#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
273#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
274#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
275#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
276#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
277#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
278#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
279#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
280#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
281#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
282#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
283#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
284#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
285#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
286#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
287#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
288#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
289#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
290#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
291
292/* Asynchronous Memory Control Registers */
293
294#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
295#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
296#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
297#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
298#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
299#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
300#define bfin_read_EBIU_MBSCTL() bfin_read16(EBIU_MBSCTL)
301#define bfin_write_EBIU_MBSCTL(val) bfin_write16(EBIU_MBSCTL, val)
302#define bfin_read_EBIU_ARBSTAT() bfin_read32(EBIU_ARBSTAT)
303#define bfin_write_EBIU_ARBSTAT(val) bfin_write32(EBIU_ARBSTAT, val)
304#define bfin_read_EBIU_MODE() bfin_read32(EBIU_MODE)
305#define bfin_write_EBIU_MODE(val) bfin_write32(EBIU_MODE, val)
306#define bfin_read_EBIU_FCTL() bfin_read16(EBIU_FCTL)
307#define bfin_write_EBIU_FCTL(val) bfin_write16(EBIU_FCTL, val)
308
309/* DDR Memory Control Registers */
310
311#define bfin_read_EBIU_DDRCTL0() bfin_read32(EBIU_DDRCTL0)
312#define bfin_write_EBIU_DDRCTL0(val) bfin_write32(EBIU_DDRCTL0, val)
313#define bfin_read_EBIU_DDRCTL1() bfin_read32(EBIU_DDRCTL1)
314#define bfin_write_EBIU_DDRCTL1(val) bfin_write32(EBIU_DDRCTL1, val)
315#define bfin_read_EBIU_DDRCTL2() bfin_read32(EBIU_DDRCTL2)
316#define bfin_write_EBIU_DDRCTL2(val) bfin_write32(EBIU_DDRCTL2, val)
317#define bfin_read_EBIU_DDRCTL3() bfin_read32(EBIU_DDRCTL3)
318#define bfin_write_EBIU_DDRCTL3(val) bfin_write32(EBIU_DDRCTL3, val)
319#define bfin_read_EBIU_DDRQUE() bfin_read32(EBIU_DDRQUE)
320#define bfin_write_EBIU_DDRQUE(val) bfin_write32(EBIU_DDRQUE, val)
321#define bfin_read_EBIU_ERRADD() bfin_read32(EBIU_ERRADD)
322#define bfin_write_EBIU_ERRADD(val) bfin_write32(EBIU_ERRADD, val)
323#define bfin_read_EBIU_ERRMST() bfin_read16(EBIU_ERRMST)
324#define bfin_write_EBIU_ERRMST(val) bfin_write16(EBIU_ERRMST, val)
325#define bfin_read_EBIU_RSTCTL() bfin_read16(EBIU_RSTCTL)
326#define bfin_write_EBIU_RSTCTL(val) bfin_write16(EBIU_RSTCTL, val)
327
328/* DDR BankRead and Write Count Registers */
329
330#define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0)
331#define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val)
332#define bfin_read_EBIU_DDRBRC1() bfin_read32(EBIU_DDRBRC1)
333#define bfin_write_EBIU_DDRBRC1(val) bfin_write32(EBIU_DDRBRC1, val)
334#define bfin_read_EBIU_DDRBRC2() bfin_read32(EBIU_DDRBRC2)
335#define bfin_write_EBIU_DDRBRC2(val) bfin_write32(EBIU_DDRBRC2, val)
336#define bfin_read_EBIU_DDRBRC3() bfin_read32(EBIU_DDRBRC3)
337#define bfin_write_EBIU_DDRBRC3(val) bfin_write32(EBIU_DDRBRC3, val)
338#define bfin_read_EBIU_DDRBRC4() bfin_read32(EBIU_DDRBRC4)
339#define bfin_write_EBIU_DDRBRC4(val) bfin_write32(EBIU_DDRBRC4, val)
340#define bfin_read_EBIU_DDRBRC5() bfin_read32(EBIU_DDRBRC5)
341#define bfin_write_EBIU_DDRBRC5(val) bfin_write32(EBIU_DDRBRC5, val)
342#define bfin_read_EBIU_DDRBRC6() bfin_read32(EBIU_DDRBRC6)
343#define bfin_write_EBIU_DDRBRC6(val) bfin_write32(EBIU_DDRBRC6, val)
344#define bfin_read_EBIU_DDRBRC7() bfin_read32(EBIU_DDRBRC7)
345#define bfin_write_EBIU_DDRBRC7(val) bfin_write32(EBIU_DDRBRC7, val)
346#define bfin_read_EBIU_DDRBWC0() bfin_read32(EBIU_DDRBWC0)
347#define bfin_write_EBIU_DDRBWC0(val) bfin_write32(EBIU_DDRBWC0, val)
348#define bfin_read_EBIU_DDRBWC1() bfin_read32(EBIU_DDRBWC1)
349#define bfin_write_EBIU_DDRBWC1(val) bfin_write32(EBIU_DDRBWC1, val)
350#define bfin_read_EBIU_DDRBWC2() bfin_read32(EBIU_DDRBWC2)
351#define bfin_write_EBIU_DDRBWC2(val) bfin_write32(EBIU_DDRBWC2, val)
352#define bfin_read_EBIU_DDRBWC3() bfin_read32(EBIU_DDRBWC3)
353#define bfin_write_EBIU_DDRBWC3(val) bfin_write32(EBIU_DDRBWC3, val)
354#define bfin_read_EBIU_DDRBWC4() bfin_read32(EBIU_DDRBWC4)
355#define bfin_write_EBIU_DDRBWC4(val) bfin_write32(EBIU_DDRBWC4, val)
356#define bfin_read_EBIU_DDRBWC5() bfin_read32(EBIU_DDRBWC5)
357#define bfin_write_EBIU_DDRBWC5(val) bfin_write32(EBIU_DDRBWC5, val)
358#define bfin_read_EBIU_DDRBWC6() bfin_read32(EBIU_DDRBWC6)
359#define bfin_write_EBIU_DDRBWC6(val) bfin_write32(EBIU_DDRBWC6, val)
360#define bfin_read_EBIU_DDRBWC7() bfin_read32(EBIU_DDRBWC7)
361#define bfin_write_EBIU_DDRBWC7(val) bfin_write32(EBIU_DDRBWC7, val)
362#define bfin_read_EBIU_DDRACCT() bfin_read32(EBIU_DDRACCT)
363#define bfin_write_EBIU_DDRACCT(val) bfin_write32(EBIU_DDRACCT, val)
364#define bfin_read_EBIU_DDRTACT() bfin_read32(EBIU_DDRTACT)
365#define bfin_write_EBIU_DDRTACT(val) bfin_write32(EBIU_DDRTACT, val)
366#define bfin_read_EBIU_DDRARCT() bfin_read32(EBIU_DDRARCT)
367#define bfin_write_EBIU_DDRARCT(val) bfin_write32(EBIU_DDRARCT, val)
368#define bfin_read_EBIU_DDRGC0() bfin_read32(EBIU_DDRGC0)
369#define bfin_write_EBIU_DDRGC0(val) bfin_write32(EBIU_DDRGC0, val)
370#define bfin_read_EBIU_DDRGC1() bfin_read32(EBIU_DDRGC1)
371#define bfin_write_EBIU_DDRGC1(val) bfin_write32(EBIU_DDRGC1, val)
372#define bfin_read_EBIU_DDRGC2() bfin_read32(EBIU_DDRGC2)
373#define bfin_write_EBIU_DDRGC2(val) bfin_write32(EBIU_DDRGC2, val)
374#define bfin_read_EBIU_DDRGC3() bfin_read32(EBIU_DDRGC3)
375#define bfin_write_EBIU_DDRGC3(val) bfin_write32(EBIU_DDRGC3, val)
376#define bfin_read_EBIU_DDRMCEN() bfin_read32(EBIU_DDRMCEN)
377#define bfin_write_EBIU_DDRMCEN(val) bfin_write32(EBIU_DDRMCEN, val)
378#define bfin_read_EBIU_DDRMCCL() bfin_read32(EBIU_DDRMCCL)
379#define bfin_write_EBIU_DDRMCCL(val) bfin_write32(EBIU_DDRMCCL, val)
380
381/* DMAC0 Registers */
382
383#define bfin_read_DMAC0_TCPER() bfin_read16(DMAC0_TCPER)
384#define bfin_write_DMAC0_TCPER(val) bfin_write16(DMAC0_TCPER, val)
385#define bfin_read_DMAC0_TCCNT() bfin_read16(DMAC0_TCCNT)
386#define bfin_write_DMAC0_TCCNT(val) bfin_write16(DMAC0_TCCNT, val)
387
388/* DMA Channel 0 Registers */
389
390#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
391#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val)
392#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
393#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val)
394#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
395#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
396#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
397#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
398#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
399#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
400#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
401#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
402#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
403#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
404#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
405#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val)
406#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
407#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val)
408#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
409#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
410#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
411#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
412#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
413#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
414#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
415#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
416
417/* DMA Channel 1 Registers */
418
419#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
420#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val)
421#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
422#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val)
423#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
424#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
425#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
426#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
427#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
428#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
429#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
430#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
431#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
432#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
433#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
434#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val)
435#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
436#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val)
437#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
438#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
439#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
440#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
441#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
442#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
443#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
444#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
445
446/* DMA Channel 2 Registers */
447
448#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
449#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val)
450#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
451#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val)
452#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
453#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
454#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
455#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
456#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
457#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
458#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
459#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
460#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
461#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
462#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
463#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val)
464#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
465#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val)
466#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
467#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
468#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
469#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
470#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
471#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
472#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
473#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
474
475/* DMA Channel 3 Registers */
476
477#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
478#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val)
479#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
480#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val)
481#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
482#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
483#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
484#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
485#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
486#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
487#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
488#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
489#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
490#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
491#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
492#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val)
493#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
494#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val)
495#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
496#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
497#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
498#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
499#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
500#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
501#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
502#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
503
504/* DMA Channel 4 Registers */
505
506#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
507#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val)
508#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
509#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val)
510#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
511#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
512#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
513#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
514#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
515#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
516#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
517#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
518#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
519#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
520#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
521#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val)
522#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
523#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val)
524#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
525#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
526#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
527#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
528#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
529#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
530#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
531#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
532
533/* DMA Channel 5 Registers */
534
535#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
536#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val)
537#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
538#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val)
539#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
540#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
541#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
542#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
543#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
544#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
545#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
546#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
547#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
548#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
549#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
550#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val)
551#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
552#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val)
553#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
554#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
555#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
556#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
557#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
558#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
559#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
560#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
561
562/* DMA Channel 6 Registers */
563
564#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
565#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
566#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
567#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val)
568#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
569#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
570#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
571#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
572#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
573#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
574#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
575#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
576#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
577#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
578#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
579#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val)
580#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
581#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val)
582#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
583#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
584#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
585#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
586#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
587#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
588#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
589#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
590
591/* DMA Channel 7 Registers */
592
593#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
594#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val)
595#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
596#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val)
597#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
598#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
599#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
600#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
601#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
602#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
603#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
604#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
605#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
606#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
607#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
608#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val)
609#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
610#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val)
611#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
612#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
613#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
614#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
615#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
616#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
617#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
618#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
619
620/* DMA Channel 8 Registers */
621
622#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR)
623#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val)
624#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR)
625#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val)
626#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
627#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
628#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
629#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
630#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
631#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
632#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
633#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
634#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
635#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
636#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR)
637#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val)
638#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR)
639#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val)
640#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
641#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
642#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
643#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
644#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
645#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
646#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
647#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
648
649/* DMA Channel 9 Registers */
650
651#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR)
652#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val)
653#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR)
654#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val)
655#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
656#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
657#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
658#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
659#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
660#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
661#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
662#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
663#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
664#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
665#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR)
666#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val)
667#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR)
668#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val)
669#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
670#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
671#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
672#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
673#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
674#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
675#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
676#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
677
678/* DMA Channel 10 Registers */
679
680#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR)
681#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val)
682#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR)
683#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val)
684#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
685#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
686#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
687#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
688#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
689#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
690#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
691#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
692#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
693#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
694#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR)
695#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val)
696#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR)
697#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val)
698#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
699#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
700#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
701#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
702#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
703#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
704#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
705#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
706
707/* DMA Channel 11 Registers */
708
709#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR)
710#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val)
711#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR)
712#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val)
713#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
714#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
715#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
716#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
717#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
718#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
719#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
720#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
721#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
722#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
723#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR)
724#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val)
725#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR)
726#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val)
727#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
728#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
729#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
730#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
731#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
732#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
733#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
734#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
735
736/* MDMA Stream 0 Registers */
737
738#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
739#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
740#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
741#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val)
742#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
743#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
744#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
745#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
746#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
747#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
748#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
749#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
750#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
751#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
752#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
753#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
754#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
755#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val)
756#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
757#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
758#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
759#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
760#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
761#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
762#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
763#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
764#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
765#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
766#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
767#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val)
768#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
769#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
770#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
771#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
772#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
773#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
774#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
775#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
776#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
777#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
778#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
779#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
780#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
781#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val)
782#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
783#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
784#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
785#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
786#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
787#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
788#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
789#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
790
791/* MDMA Stream 1 Registers */
792
793#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
794#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
795#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
796#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val)
797#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
798#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
799#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
800#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
801#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
802#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
803#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
804#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
805#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
806#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
807#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
808#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
809#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
810#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val)
811#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
812#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
813#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
814#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
815#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
816#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
817#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
818#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
819#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
820#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
821#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
822#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val)
823#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
824#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
825#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
826#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
827#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
828#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
829#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
830#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
831#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
832#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
833#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
834#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
835#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
836#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val)
837#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
838#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
839#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
840#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
841#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
842#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
843#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
844#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
845
846/* EPPI1 Registers */
847
848#define bfin_read_EPPI1_STATUS() bfin_read16(EPPI1_STATUS)
849#define bfin_write_EPPI1_STATUS(val) bfin_write16(EPPI1_STATUS, val)
850#define bfin_read_EPPI1_HCOUNT() bfin_read16(EPPI1_HCOUNT)
851#define bfin_write_EPPI1_HCOUNT(val) bfin_write16(EPPI1_HCOUNT, val)
852#define bfin_read_EPPI1_HDELAY() bfin_read16(EPPI1_HDELAY)
853#define bfin_write_EPPI1_HDELAY(val) bfin_write16(EPPI1_HDELAY, val)
854#define bfin_read_EPPI1_VCOUNT() bfin_read16(EPPI1_VCOUNT)
855#define bfin_write_EPPI1_VCOUNT(val) bfin_write16(EPPI1_VCOUNT, val)
856#define bfin_read_EPPI1_VDELAY() bfin_read16(EPPI1_VDELAY)
857#define bfin_write_EPPI1_VDELAY(val) bfin_write16(EPPI1_VDELAY, val)
858#define bfin_read_EPPI1_FRAME() bfin_read16(EPPI1_FRAME)
859#define bfin_write_EPPI1_FRAME(val) bfin_write16(EPPI1_FRAME, val)
860#define bfin_read_EPPI1_LINE() bfin_read16(EPPI1_LINE)
861#define bfin_write_EPPI1_LINE(val) bfin_write16(EPPI1_LINE, val)
862#define bfin_read_EPPI1_CLKDIV() bfin_read16(EPPI1_CLKDIV)
863#define bfin_write_EPPI1_CLKDIV(val) bfin_write16(EPPI1_CLKDIV, val)
864#define bfin_read_EPPI1_CONTROL() bfin_read32(EPPI1_CONTROL)
865#define bfin_write_EPPI1_CONTROL(val) bfin_write32(EPPI1_CONTROL, val)
866#define bfin_read_EPPI1_FS1W_HBL() bfin_read32(EPPI1_FS1W_HBL)
867#define bfin_write_EPPI1_FS1W_HBL(val) bfin_write32(EPPI1_FS1W_HBL, val)
868#define bfin_read_EPPI1_FS1P_AVPL() bfin_read32(EPPI1_FS1P_AVPL)
869#define bfin_write_EPPI1_FS1P_AVPL(val) bfin_write32(EPPI1_FS1P_AVPL, val)
870#define bfin_read_EPPI1_FS2W_LVB() bfin_read32(EPPI1_FS2W_LVB)
871#define bfin_write_EPPI1_FS2W_LVB(val) bfin_write32(EPPI1_FS2W_LVB, val)
872#define bfin_read_EPPI1_FS2P_LAVF() bfin_read32(EPPI1_FS2P_LAVF)
873#define bfin_write_EPPI1_FS2P_LAVF(val) bfin_write32(EPPI1_FS2P_LAVF, val)
874#define bfin_read_EPPI1_CLIP() bfin_read32(EPPI1_CLIP)
875#define bfin_write_EPPI1_CLIP(val) bfin_write32(EPPI1_CLIP, val)
876
877/* Port Interrubfin_read_()t 0 Registers (32-bit) */
878
879#define bfin_read_PINT0_MASK_SET() bfin_read32(PINT0_MASK_SET)
880#define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val)
881#define bfin_read_PINT0_MASK_CLEAR() bfin_read32(PINT0_MASK_CLEAR)
882#define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val)
883#define bfin_read_PINT0_REQUEST() bfin_read32(PINT0_REQUEST)
884#define bfin_write_PINT0_REQUEST(val) bfin_write32(PINT0_REQUEST, val)
885#define bfin_read_PINT0_ASSIGN() bfin_read32(PINT0_ASSIGN)
886#define bfin_write_PINT0_ASSIGN(val) bfin_write32(PINT0_ASSIGN, val)
887#define bfin_read_PINT0_EDGE_SET() bfin_read32(PINT0_EDGE_SET)
888#define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val)
889#define bfin_read_PINT0_EDGE_CLEAR() bfin_read32(PINT0_EDGE_CLEAR)
890#define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val)
891#define bfin_read_PINT0_INVERT_SET() bfin_read32(PINT0_INVERT_SET)
892#define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val)
893#define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR)
894#define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val)
895#define bfin_read_PINT0_PINSTATE() bfin_read32(PINT0_PINSTATE)
896#define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val)
897#define bfin_read_PINT0_LATCH() bfin_read32(PINT0_LATCH)
898#define bfin_write_PINT0_LATCH(val) bfin_write32(PINT0_LATCH, val)
899
900/* Port Interrubfin_read_()t 1 Registers (32-bit) */
901
902#define bfin_read_PINT1_MASK_SET() bfin_read32(PINT1_MASK_SET)
903#define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val)
904#define bfin_read_PINT1_MASK_CLEAR() bfin_read32(PINT1_MASK_CLEAR)
905#define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val)
906#define bfin_read_PINT1_REQUEST() bfin_read32(PINT1_REQUEST)
907#define bfin_write_PINT1_REQUEST(val) bfin_write32(PINT1_REQUEST, val)
908#define bfin_read_PINT1_ASSIGN() bfin_read32(PINT1_ASSIGN)
909#define bfin_write_PINT1_ASSIGN(val) bfin_write32(PINT1_ASSIGN, val)
910#define bfin_read_PINT1_EDGE_SET() bfin_read32(PINT1_EDGE_SET)
911#define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val)
912#define bfin_read_PINT1_EDGE_CLEAR() bfin_read32(PINT1_EDGE_CLEAR)
913#define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val)
914#define bfin_read_PINT1_INVERT_SET() bfin_read32(PINT1_INVERT_SET)
915#define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val)
916#define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR)
917#define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val)
918#define bfin_read_PINT1_PINSTATE() bfin_read32(PINT1_PINSTATE)
919#define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val)
920#define bfin_read_PINT1_LATCH() bfin_read32(PINT1_LATCH)
921#define bfin_write_PINT1_LATCH(val) bfin_write32(PINT1_LATCH, val)
922
923/* Port Interrubfin_read_()t 2 Registers (32-bit) */
924
925#define bfin_read_PINT2_MASK_SET() bfin_read32(PINT2_MASK_SET)
926#define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val)
927#define bfin_read_PINT2_MASK_CLEAR() bfin_read32(PINT2_MASK_CLEAR)
928#define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val)
929#define bfin_read_PINT2_REQUEST() bfin_read32(PINT2_REQUEST)
930#define bfin_write_PINT2_REQUEST(val) bfin_write32(PINT2_REQUEST, val)
931#define bfin_read_PINT2_ASSIGN() bfin_read32(PINT2_ASSIGN)
932#define bfin_write_PINT2_ASSIGN(val) bfin_write32(PINT2_ASSIGN, val)
933#define bfin_read_PINT2_EDGE_SET() bfin_read32(PINT2_EDGE_SET)
934#define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val)
935#define bfin_read_PINT2_EDGE_CLEAR() bfin_read32(PINT2_EDGE_CLEAR)
936#define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val)
937#define bfin_read_PINT2_INVERT_SET() bfin_read32(PINT2_INVERT_SET)
938#define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val)
939#define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR)
940#define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val)
941#define bfin_read_PINT2_PINSTATE() bfin_read32(PINT2_PINSTATE)
942#define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val)
943#define bfin_read_PINT2_LATCH() bfin_read32(PINT2_LATCH)
944#define bfin_write_PINT2_LATCH(val) bfin_write32(PINT2_LATCH, val)
945
946/* Port Interrubfin_read_()t 3 Registers (32-bit) */
947
948#define bfin_read_PINT3_MASK_SET() bfin_read32(PINT3_MASK_SET)
949#define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val)
950#define bfin_read_PINT3_MASK_CLEAR() bfin_read32(PINT3_MASK_CLEAR)
951#define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val)
952#define bfin_read_PINT3_REQUEST() bfin_read32(PINT3_REQUEST)
953#define bfin_write_PINT3_REQUEST(val) bfin_write32(PINT3_REQUEST, val)
954#define bfin_read_PINT3_ASSIGN() bfin_read32(PINT3_ASSIGN)
955#define bfin_write_PINT3_ASSIGN(val) bfin_write32(PINT3_ASSIGN, val)
956#define bfin_read_PINT3_EDGE_SET() bfin_read32(PINT3_EDGE_SET)
957#define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val)
958#define bfin_read_PINT3_EDGE_CLEAR() bfin_read32(PINT3_EDGE_CLEAR)
959#define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val)
960#define bfin_read_PINT3_INVERT_SET() bfin_read32(PINT3_INVERT_SET)
961#define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val)
962#define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR)
963#define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val)
964#define bfin_read_PINT3_PINSTATE() bfin_read32(PINT3_PINSTATE)
965#define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val)
966#define bfin_read_PINT3_LATCH() bfin_read32(PINT3_LATCH)
967#define bfin_write_PINT3_LATCH(val) bfin_write32(PINT3_LATCH, val)
968
969/* Port A Registers */
970
971#define bfin_read_PORTA_FER() bfin_read16(PORTA_FER)
972#define bfin_write_PORTA_FER(val) bfin_write16(PORTA_FER, val)
973#define bfin_read_PORTA() bfin_read16(PORTA)
974#define bfin_write_PORTA(val) bfin_write16(PORTA, val)
975#define bfin_read_PORTA_SET() bfin_read16(PORTA_SET)
976#define bfin_write_PORTA_SET(val) bfin_write16(PORTA_SET, val)
977#define bfin_read_PORTA_CLEAR() bfin_read16(PORTA_CLEAR)
978#define bfin_write_PORTA_CLEAR(val) bfin_write16(PORTA_CLEAR, val)
979#define bfin_read_PORTA_DIR_SET() bfin_read16(PORTA_DIR_SET)
980#define bfin_write_PORTA_DIR_SET(val) bfin_write16(PORTA_DIR_SET, val)
981#define bfin_read_PORTA_DIR_CLEAR() bfin_read16(PORTA_DIR_CLEAR)
982#define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val)
983#define bfin_read_PORTA_INEN() bfin_read16(PORTA_INEN)
984#define bfin_write_PORTA_INEN(val) bfin_write16(PORTA_INEN, val)
985#define bfin_read_PORTA_MUX() bfin_read32(PORTA_MUX)
986#define bfin_write_PORTA_MUX(val) bfin_write32(PORTA_MUX, val)
987
988/* Port B Registers */
989
990#define bfin_read_PORTB_FER() bfin_read16(PORTB_FER)
991#define bfin_write_PORTB_FER(val) bfin_write16(PORTB_FER, val)
992#define bfin_read_PORTB() bfin_read16(PORTB)
993#define bfin_write_PORTB(val) bfin_write16(PORTB, val)
994#define bfin_read_PORTB_SET() bfin_read16(PORTB_SET)
995#define bfin_write_PORTB_SET(val) bfin_write16(PORTB_SET, val)
996#define bfin_read_PORTB_CLEAR() bfin_read16(PORTB_CLEAR)
997#define bfin_write_PORTB_CLEAR(val) bfin_write16(PORTB_CLEAR, val)
998#define bfin_read_PORTB_DIR_SET() bfin_read16(PORTB_DIR_SET)
999#define bfin_write_PORTB_DIR_SET(val) bfin_write16(PORTB_DIR_SET, val)
1000#define bfin_read_PORTB_DIR_CLEAR() bfin_read16(PORTB_DIR_CLEAR)
1001#define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val)
1002#define bfin_read_PORTB_INEN() bfin_read16(PORTB_INEN)
1003#define bfin_write_PORTB_INEN(val) bfin_write16(PORTB_INEN, val)
1004#define bfin_read_PORTB_MUX() bfin_read32(PORTB_MUX)
1005#define bfin_write_PORTB_MUX(val) bfin_write32(PORTB_MUX, val)
1006
1007/* Port C Registers */
1008
1009#define bfin_read_PORTC_FER() bfin_read16(PORTC_FER)
1010#define bfin_write_PORTC_FER(val) bfin_write16(PORTC_FER, val)
1011#define bfin_read_PORTC() bfin_read16(PORTC)
1012#define bfin_write_PORTC(val) bfin_write16(PORTC, val)
1013#define bfin_read_PORTC_SET() bfin_read16(PORTC_SET)
1014#define bfin_write_PORTC_SET(val) bfin_write16(PORTC_SET, val)
1015#define bfin_read_PORTC_CLEAR() bfin_read16(PORTC_CLEAR)
1016#define bfin_write_PORTC_CLEAR(val) bfin_write16(PORTC_CLEAR, val)
1017#define bfin_read_PORTC_DIR_SET() bfin_read16(PORTC_DIR_SET)
1018#define bfin_write_PORTC_DIR_SET(val) bfin_write16(PORTC_DIR_SET, val)
1019#define bfin_read_PORTC_DIR_CLEAR() bfin_read16(PORTC_DIR_CLEAR)
1020#define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val)
1021#define bfin_read_PORTC_INEN() bfin_read16(PORTC_INEN)
1022#define bfin_write_PORTC_INEN(val) bfin_write16(PORTC_INEN, val)
1023#define bfin_read_PORTC_MUX() bfin_read32(PORTC_MUX)
1024#define bfin_write_PORTC_MUX(val) bfin_write32(PORTC_MUX, val)
1025
1026/* Port D Registers */
1027
1028#define bfin_read_PORTD_FER() bfin_read16(PORTD_FER)
1029#define bfin_write_PORTD_FER(val) bfin_write16(PORTD_FER, val)
1030#define bfin_read_PORTD() bfin_read16(PORTD)
1031#define bfin_write_PORTD(val) bfin_write16(PORTD, val)
1032#define bfin_read_PORTD_SET() bfin_read16(PORTD_SET)
1033#define bfin_write_PORTD_SET(val) bfin_write16(PORTD_SET, val)
1034#define bfin_read_PORTD_CLEAR() bfin_read16(PORTD_CLEAR)
1035#define bfin_write_PORTD_CLEAR(val) bfin_write16(PORTD_CLEAR, val)
1036#define bfin_read_PORTD_DIR_SET() bfin_read16(PORTD_DIR_SET)
1037#define bfin_write_PORTD_DIR_SET(val) bfin_write16(PORTD_DIR_SET, val)
1038#define bfin_read_PORTD_DIR_CLEAR() bfin_read16(PORTD_DIR_CLEAR)
1039#define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val)
1040#define bfin_read_PORTD_INEN() bfin_read16(PORTD_INEN)
1041#define bfin_write_PORTD_INEN(val) bfin_write16(PORTD_INEN, val)
1042#define bfin_read_PORTD_MUX() bfin_read32(PORTD_MUX)
1043#define bfin_write_PORTD_MUX(val) bfin_write32(PORTD_MUX, val)
1044
1045/* Port E Registers */
1046
1047#define bfin_read_PORTE_FER() bfin_read16(PORTE_FER)
1048#define bfin_write_PORTE_FER(val) bfin_write16(PORTE_FER, val)
1049#define bfin_read_PORTE() bfin_read16(PORTE)
1050#define bfin_write_PORTE(val) bfin_write16(PORTE, val)
1051#define bfin_read_PORTE_SET() bfin_read16(PORTE_SET)
1052#define bfin_write_PORTE_SET(val) bfin_write16(PORTE_SET, val)
1053#define bfin_read_PORTE_CLEAR() bfin_read16(PORTE_CLEAR)
1054#define bfin_write_PORTE_CLEAR(val) bfin_write16(PORTE_CLEAR, val)
1055#define bfin_read_PORTE_DIR_SET() bfin_read16(PORTE_DIR_SET)
1056#define bfin_write_PORTE_DIR_SET(val) bfin_write16(PORTE_DIR_SET, val)
1057#define bfin_read_PORTE_DIR_CLEAR() bfin_read16(PORTE_DIR_CLEAR)
1058#define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val)
1059#define bfin_read_PORTE_INEN() bfin_read16(PORTE_INEN)
1060#define bfin_write_PORTE_INEN(val) bfin_write16(PORTE_INEN, val)
1061#define bfin_read_PORTE_MUX() bfin_read32(PORTE_MUX)
1062#define bfin_write_PORTE_MUX(val) bfin_write32(PORTE_MUX, val)
1063
1064/* Port F Registers */
1065
1066#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER)
1067#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val)
1068#define bfin_read_PORTF() bfin_read16(PORTF)
1069#define bfin_write_PORTF(val) bfin_write16(PORTF, val)
1070#define bfin_read_PORTF_SET() bfin_read16(PORTF_SET)
1071#define bfin_write_PORTF_SET(val) bfin_write16(PORTF_SET, val)
1072#define bfin_read_PORTF_CLEAR() bfin_read16(PORTF_CLEAR)
1073#define bfin_write_PORTF_CLEAR(val) bfin_write16(PORTF_CLEAR, val)
1074#define bfin_read_PORTF_DIR_SET() bfin_read16(PORTF_DIR_SET)
1075#define bfin_write_PORTF_DIR_SET(val) bfin_write16(PORTF_DIR_SET, val)
1076#define bfin_read_PORTF_DIR_CLEAR() bfin_read16(PORTF_DIR_CLEAR)
1077#define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val)
1078#define bfin_read_PORTF_INEN() bfin_read16(PORTF_INEN)
1079#define bfin_write_PORTF_INEN(val) bfin_write16(PORTF_INEN, val)
1080#define bfin_read_PORTF_MUX() bfin_read32(PORTF_MUX)
1081#define bfin_write_PORTF_MUX(val) bfin_write32(PORTF_MUX, val)
1082
1083/* Port G Registers */
1084
1085#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER)
1086#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val)
1087#define bfin_read_PORTG() bfin_read16(PORTG)
1088#define bfin_write_PORTG(val) bfin_write16(PORTG, val)
1089#define bfin_read_PORTG_SET() bfin_read16(PORTG_SET)
1090#define bfin_write_PORTG_SET(val) bfin_write16(PORTG_SET, val)
1091#define bfin_read_PORTG_CLEAR() bfin_read16(PORTG_CLEAR)
1092#define bfin_write_PORTG_CLEAR(val) bfin_write16(PORTG_CLEAR, val)
1093#define bfin_read_PORTG_DIR_SET() bfin_read16(PORTG_DIR_SET)
1094#define bfin_write_PORTG_DIR_SET(val) bfin_write16(PORTG_DIR_SET, val)
1095#define bfin_read_PORTG_DIR_CLEAR() bfin_read16(PORTG_DIR_CLEAR)
1096#define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val)
1097#define bfin_read_PORTG_INEN() bfin_read16(PORTG_INEN)
1098#define bfin_write_PORTG_INEN(val) bfin_write16(PORTG_INEN, val)
1099#define bfin_read_PORTG_MUX() bfin_read32(PORTG_MUX)
1100#define bfin_write_PORTG_MUX(val) bfin_write32(PORTG_MUX, val)
1101
1102/* Port H Registers */
1103
1104#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER)
1105#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val)
1106#define bfin_read_PORTH() bfin_read16(PORTH)
1107#define bfin_write_PORTH(val) bfin_write16(PORTH, val)
1108#define bfin_read_PORTH_SET() bfin_read16(PORTH_SET)
1109#define bfin_write_PORTH_SET(val) bfin_write16(PORTH_SET, val)
1110#define bfin_read_PORTH_CLEAR() bfin_read16(PORTH_CLEAR)
1111#define bfin_write_PORTH_CLEAR(val) bfin_write16(PORTH_CLEAR, val)
1112#define bfin_read_PORTH_DIR_SET() bfin_read16(PORTH_DIR_SET)
1113#define bfin_write_PORTH_DIR_SET(val) bfin_write16(PORTH_DIR_SET, val)
1114#define bfin_read_PORTH_DIR_CLEAR() bfin_read16(PORTH_DIR_CLEAR)
1115#define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val)
1116#define bfin_read_PORTH_INEN() bfin_read16(PORTH_INEN)
1117#define bfin_write_PORTH_INEN(val) bfin_write16(PORTH_INEN, val)
1118#define bfin_read_PORTH_MUX() bfin_read32(PORTH_MUX)
1119#define bfin_write_PORTH_MUX(val) bfin_write32(PORTH_MUX, val)
1120
1121/* Port I Registers */
1122
1123#define bfin_read_PORTI_FER() bfin_read16(PORTI_FER)
1124#define bfin_write_PORTI_FER(val) bfin_write16(PORTI_FER, val)
1125#define bfin_read_PORTI() bfin_read16(PORTI)
1126#define bfin_write_PORTI(val) bfin_write16(PORTI, val)
1127#define bfin_read_PORTI_SET() bfin_read16(PORTI_SET)
1128#define bfin_write_PORTI_SET(val) bfin_write16(PORTI_SET, val)
1129#define bfin_read_PORTI_CLEAR() bfin_read16(PORTI_CLEAR)
1130#define bfin_write_PORTI_CLEAR(val) bfin_write16(PORTI_CLEAR, val)
1131#define bfin_read_PORTI_DIR_SET() bfin_read16(PORTI_DIR_SET)
1132#define bfin_write_PORTI_DIR_SET(val) bfin_write16(PORTI_DIR_SET, val)
1133#define bfin_read_PORTI_DIR_CLEAR() bfin_read16(PORTI_DIR_CLEAR)
1134#define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val)
1135#define bfin_read_PORTI_INEN() bfin_read16(PORTI_INEN)
1136#define bfin_write_PORTI_INEN(val) bfin_write16(PORTI_INEN, val)
1137#define bfin_read_PORTI_MUX() bfin_read32(PORTI_MUX)
1138#define bfin_write_PORTI_MUX(val) bfin_write32(PORTI_MUX, val)
1139
1140/* Port J Registers */
1141
1142#define bfin_read_PORTJ_FER() bfin_read16(PORTJ_FER)
1143#define bfin_write_PORTJ_FER(val) bfin_write16(PORTJ_FER, val)
1144#define bfin_read_PORTJ() bfin_read16(PORTJ)
1145#define bfin_write_PORTJ(val) bfin_write16(PORTJ, val)
1146#define bfin_read_PORTJ_SET() bfin_read16(PORTJ_SET)
1147#define bfin_write_PORTJ_SET(val) bfin_write16(PORTJ_SET, val)
1148#define bfin_read_PORTJ_CLEAR() bfin_read16(PORTJ_CLEAR)
1149#define bfin_write_PORTJ_CLEAR(val) bfin_write16(PORTJ_CLEAR, val)
1150#define bfin_read_PORTJ_DIR_SET() bfin_read16(PORTJ_DIR_SET)
1151#define bfin_write_PORTJ_DIR_SET(val) bfin_write16(PORTJ_DIR_SET, val)
1152#define bfin_read_PORTJ_DIR_CLEAR() bfin_read16(PORTJ_DIR_CLEAR)
1153#define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val)
1154#define bfin_read_PORTJ_INEN() bfin_read16(PORTJ_INEN)
1155#define bfin_write_PORTJ_INEN(val) bfin_write16(PORTJ_INEN, val)
1156#define bfin_read_PORTJ_MUX() bfin_read32(PORTJ_MUX)
1157#define bfin_write_PORTJ_MUX(val) bfin_write32(PORTJ_MUX, val)
1158
1159/* PWM Timer Registers */
1160
1161#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
1162#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
1163#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
1164#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
1165#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
1166#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
1167#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
1168#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
1169#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
1170#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
1171#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
1172#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
1173#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
1174#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
1175#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
1176#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
1177#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
1178#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
1179#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
1180#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
1181#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
1182#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
1183#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
1184#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
1185#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
1186#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
1187#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
1188#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
1189#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
1190#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
1191#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
1192#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
1193#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
1194#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
1195#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
1196#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
1197#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
1198#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
1199#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
1200#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
1201#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
1202#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
1203#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
1204#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
1205#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
1206#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
1207#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
1208#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
1209#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
1210#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
1211#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
1212#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
1213#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
1214#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
1215#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
1216#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
1217#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
1218#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
1219#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
1220#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
1221#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
1222#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
1223#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
1224#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
1225
1226/* Timer Groubfin_read_() of 8 */
1227
1228#define bfin_read_TIMER_ENABLE0() bfin_read16(TIMER_ENABLE0)
1229#define bfin_write_TIMER_ENABLE0(val) bfin_write16(TIMER_ENABLE0, val)
1230#define bfin_read_TIMER_DISABLE0() bfin_read16(TIMER_DISABLE0)
1231#define bfin_write_TIMER_DISABLE0(val) bfin_write16(TIMER_DISABLE0, val)
1232#define bfin_read_TIMER_STATUS0() bfin_read32(TIMER_STATUS0)
1233#define bfin_write_TIMER_STATUS0(val) bfin_write32(TIMER_STATUS0, val)
1234
1235/* DMAC1 Registers */
1236
1237#define bfin_read_DMAC1_TCPER() bfin_read16(DMAC1_TCPER)
1238#define bfin_write_DMAC1_TCPER(val) bfin_write16(DMAC1_TCPER, val)
1239#define bfin_read_DMAC1_TCCNT() bfin_read16(DMAC1_TCCNT)
1240#define bfin_write_DMAC1_TCCNT(val) bfin_write16(DMAC1_TCCNT, val)
1241
1242/* DMA Channel 12 Registers */
1243
1244#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_read32(DMA12_NEXT_DESC_PTR)
1245#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_write32(DMA12_NEXT_DESC_PTR, val)
1246#define bfin_read_DMA12_START_ADDR() bfin_read32(DMA12_START_ADDR)
1247#define bfin_write_DMA12_START_ADDR(val) bfin_write32(DMA12_START_ADDR, val)
1248#define bfin_read_DMA12_CONFIG() bfin_read16(DMA12_CONFIG)
1249#define bfin_write_DMA12_CONFIG(val) bfin_write16(DMA12_CONFIG, val)
1250#define bfin_read_DMA12_X_COUNT() bfin_read16(DMA12_X_COUNT)
1251#define bfin_write_DMA12_X_COUNT(val) bfin_write16(DMA12_X_COUNT, val)
1252#define bfin_read_DMA12_X_MODIFY() bfin_read16(DMA12_X_MODIFY)
1253#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val)
1254#define bfin_read_DMA12_Y_COUNT() bfin_read16(DMA12_Y_COUNT)
1255#define bfin_write_DMA12_Y_COUNT(val) bfin_write16(DMA12_Y_COUNT, val)
1256#define bfin_read_DMA12_Y_MODIFY() bfin_read16(DMA12_Y_MODIFY)
1257#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val)
1258#define bfin_read_DMA12_CURR_DESC_PTR() bfin_read32(DMA12_CURR_DESC_PTR)
1259#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_write32(DMA12_CURR_DESC_PTR, val)
1260#define bfin_read_DMA12_CURR_ADDR() bfin_read32(DMA12_CURR_ADDR)
1261#define bfin_write_DMA12_CURR_ADDR(val) bfin_write32(DMA12_CURR_ADDR, val)
1262#define bfin_read_DMA12_IRQ_STATUS() bfin_read16(DMA12_IRQ_STATUS)
1263#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)
1264#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP)
1265#define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val)
1266#define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT)
1267#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val)
1268#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT)
1269#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val)
1270
1271/* DMA Channel 13 Registers */
1272
1273#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_read32(DMA13_NEXT_DESC_PTR)
1274#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_write32(DMA13_NEXT_DESC_PTR, val)
1275#define bfin_read_DMA13_START_ADDR() bfin_read32(DMA13_START_ADDR)
1276#define bfin_write_DMA13_START_ADDR(val) bfin_write32(DMA13_START_ADDR, val)
1277#define bfin_read_DMA13_CONFIG() bfin_read16(DMA13_CONFIG)
1278#define bfin_write_DMA13_CONFIG(val) bfin_write16(DMA13_CONFIG, val)
1279#define bfin_read_DMA13_X_COUNT() bfin_read16(DMA13_X_COUNT)
1280#define bfin_write_DMA13_X_COUNT(val) bfin_write16(DMA13_X_COUNT, val)
1281#define bfin_read_DMA13_X_MODIFY() bfin_read16(DMA13_X_MODIFY)
1282#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val)
1283#define bfin_read_DMA13_Y_COUNT() bfin_read16(DMA13_Y_COUNT)
1284#define bfin_write_DMA13_Y_COUNT(val) bfin_write16(DMA13_Y_COUNT, val)
1285#define bfin_read_DMA13_Y_MODIFY() bfin_read16(DMA13_Y_MODIFY)
1286#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val)
1287#define bfin_read_DMA13_CURR_DESC_PTR() bfin_read32(DMA13_CURR_DESC_PTR)
1288#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_write32(DMA13_CURR_DESC_PTR, val)
1289#define bfin_read_DMA13_CURR_ADDR() bfin_read32(DMA13_CURR_ADDR)
1290#define bfin_write_DMA13_CURR_ADDR(val) bfin_write32(DMA13_CURR_ADDR, val)
1291#define bfin_read_DMA13_IRQ_STATUS() bfin_read16(DMA13_IRQ_STATUS)
1292#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val)
1293#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP)
1294#define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val)
1295#define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT)
1296#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val)
1297#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT)
1298#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val)
1299
1300/* DMA Channel 14 Registers */
1301
1302#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_read32(DMA14_NEXT_DESC_PTR)
1303#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_write32(DMA14_NEXT_DESC_PTR, val)
1304#define bfin_read_DMA14_START_ADDR() bfin_read32(DMA14_START_ADDR)
1305#define bfin_write_DMA14_START_ADDR(val) bfin_write32(DMA14_START_ADDR, val)
1306#define bfin_read_DMA14_CONFIG() bfin_read16(DMA14_CONFIG)
1307#define bfin_write_DMA14_CONFIG(val) bfin_write16(DMA14_CONFIG, val)
1308#define bfin_read_DMA14_X_COUNT() bfin_read16(DMA14_X_COUNT)
1309#define bfin_write_DMA14_X_COUNT(val) bfin_write16(DMA14_X_COUNT, val)
1310#define bfin_read_DMA14_X_MODIFY() bfin_read16(DMA14_X_MODIFY)
1311#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val)
1312#define bfin_read_DMA14_Y_COUNT() bfin_read16(DMA14_Y_COUNT)
1313#define bfin_write_DMA14_Y_COUNT(val) bfin_write16(DMA14_Y_COUNT, val)
1314#define bfin_read_DMA14_Y_MODIFY() bfin_read16(DMA14_Y_MODIFY)
1315#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val)
1316#define bfin_read_DMA14_CURR_DESC_PTR() bfin_read32(DMA14_CURR_DESC_PTR)
1317#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_write32(DMA14_CURR_DESC_PTR, val)
1318#define bfin_read_DMA14_CURR_ADDR() bfin_read32(DMA14_CURR_ADDR)
1319#define bfin_write_DMA14_CURR_ADDR(val) bfin_write32(DMA14_CURR_ADDR, val)
1320#define bfin_read_DMA14_IRQ_STATUS() bfin_read16(DMA14_IRQ_STATUS)
1321#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val)
1322#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP)
1323#define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val)
1324#define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT)
1325#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val)
1326#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT)
1327#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val)
1328
1329/* DMA Channel 15 Registers */
1330
1331#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_read32(DMA15_NEXT_DESC_PTR)
1332#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_write32(DMA15_NEXT_DESC_PTR, val)
1333#define bfin_read_DMA15_START_ADDR() bfin_read32(DMA15_START_ADDR)
1334#define bfin_write_DMA15_START_ADDR(val) bfin_write32(DMA15_START_ADDR, val)
1335#define bfin_read_DMA15_CONFIG() bfin_read16(DMA15_CONFIG)
1336#define bfin_write_DMA15_CONFIG(val) bfin_write16(DMA15_CONFIG, val)
1337#define bfin_read_DMA15_X_COUNT() bfin_read16(DMA15_X_COUNT)
1338#define bfin_write_DMA15_X_COUNT(val) bfin_write16(DMA15_X_COUNT, val)
1339#define bfin_read_DMA15_X_MODIFY() bfin_read16(DMA15_X_MODIFY)
1340#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val)
1341#define bfin_read_DMA15_Y_COUNT() bfin_read16(DMA15_Y_COUNT)
1342#define bfin_write_DMA15_Y_COUNT(val) bfin_write16(DMA15_Y_COUNT, val)
1343#define bfin_read_DMA15_Y_MODIFY() bfin_read16(DMA15_Y_MODIFY)
1344#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val)
1345#define bfin_read_DMA15_CURR_DESC_PTR() bfin_read32(DMA15_CURR_DESC_PTR)
1346#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_write32(DMA15_CURR_DESC_PTR, val)
1347#define bfin_read_DMA15_CURR_ADDR() bfin_read32(DMA15_CURR_ADDR)
1348#define bfin_write_DMA15_CURR_ADDR(val) bfin_write32(DMA15_CURR_ADDR, val)
1349#define bfin_read_DMA15_IRQ_STATUS() bfin_read16(DMA15_IRQ_STATUS)
1350#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
1351#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP)
1352#define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val)
1353#define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT)
1354#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val)
1355#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT)
1356#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val)
1357
1358/* DMA Channel 16 Registers */
1359
1360#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_read32(DMA16_NEXT_DESC_PTR)
1361#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_write32(DMA16_NEXT_DESC_PTR, val)
1362#define bfin_read_DMA16_START_ADDR() bfin_read32(DMA16_START_ADDR)
1363#define bfin_write_DMA16_START_ADDR(val) bfin_write32(DMA16_START_ADDR, val)
1364#define bfin_read_DMA16_CONFIG() bfin_read16(DMA16_CONFIG)
1365#define bfin_write_DMA16_CONFIG(val) bfin_write16(DMA16_CONFIG, val)
1366#define bfin_read_DMA16_X_COUNT() bfin_read16(DMA16_X_COUNT)
1367#define bfin_write_DMA16_X_COUNT(val) bfin_write16(DMA16_X_COUNT, val)
1368#define bfin_read_DMA16_X_MODIFY() bfin_read16(DMA16_X_MODIFY)
1369#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val)
1370#define bfin_read_DMA16_Y_COUNT() bfin_read16(DMA16_Y_COUNT)
1371#define bfin_write_DMA16_Y_COUNT(val) bfin_write16(DMA16_Y_COUNT, val)
1372#define bfin_read_DMA16_Y_MODIFY() bfin_read16(DMA16_Y_MODIFY)
1373#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val)
1374#define bfin_read_DMA16_CURR_DESC_PTR() bfin_read32(DMA16_CURR_DESC_PTR)
1375#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_write32(DMA16_CURR_DESC_PTR, val)
1376#define bfin_read_DMA16_CURR_ADDR() bfin_read32(DMA16_CURR_ADDR)
1377#define bfin_write_DMA16_CURR_ADDR(val) bfin_write32(DMA16_CURR_ADDR, val)
1378#define bfin_read_DMA16_IRQ_STATUS() bfin_read16(DMA16_IRQ_STATUS)
1379#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val)
1380#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP)
1381#define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val)
1382#define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT)
1383#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val)
1384#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT)
1385#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val)
1386
1387/* DMA Channel 17 Registers */
1388
1389#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_read32(DMA17_NEXT_DESC_PTR)
1390#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_write32(DMA17_NEXT_DESC_PTR, val)
1391#define bfin_read_DMA17_START_ADDR() bfin_read32(DMA17_START_ADDR)
1392#define bfin_write_DMA17_START_ADDR(val) bfin_write32(DMA17_START_ADDR, val)
1393#define bfin_read_DMA17_CONFIG() bfin_read16(DMA17_CONFIG)
1394#define bfin_write_DMA17_CONFIG(val) bfin_write16(DMA17_CONFIG, val)
1395#define bfin_read_DMA17_X_COUNT() bfin_read16(DMA17_X_COUNT)
1396#define bfin_write_DMA17_X_COUNT(val) bfin_write16(DMA17_X_COUNT, val)
1397#define bfin_read_DMA17_X_MODIFY() bfin_read16(DMA17_X_MODIFY)
1398#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val)
1399#define bfin_read_DMA17_Y_COUNT() bfin_read16(DMA17_Y_COUNT)
1400#define bfin_write_DMA17_Y_COUNT(val) bfin_write16(DMA17_Y_COUNT, val)
1401#define bfin_read_DMA17_Y_MODIFY() bfin_read16(DMA17_Y_MODIFY)
1402#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val)
1403#define bfin_read_DMA17_CURR_DESC_PTR() bfin_read32(DMA17_CURR_DESC_PTR)
1404#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_write32(DMA17_CURR_DESC_PTR, val)
1405#define bfin_read_DMA17_CURR_ADDR() bfin_read32(DMA17_CURR_ADDR)
1406#define bfin_write_DMA17_CURR_ADDR(val) bfin_write32(DMA17_CURR_ADDR, val)
1407#define bfin_read_DMA17_IRQ_STATUS() bfin_read16(DMA17_IRQ_STATUS)
1408#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val)
1409#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP)
1410#define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val)
1411#define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT)
1412#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val)
1413#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT)
1414#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val)
1415
1416/* DMA Channel 18 Registers */
1417
1418#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_read32(DMA18_NEXT_DESC_PTR)
1419#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_write32(DMA18_NEXT_DESC_PTR, val)
1420#define bfin_read_DMA18_START_ADDR() bfin_read32(DMA18_START_ADDR)
1421#define bfin_write_DMA18_START_ADDR(val) bfin_write32(DMA18_START_ADDR, val)
1422#define bfin_read_DMA18_CONFIG() bfin_read16(DMA18_CONFIG)
1423#define bfin_write_DMA18_CONFIG(val) bfin_write16(DMA18_CONFIG, val)
1424#define bfin_read_DMA18_X_COUNT() bfin_read16(DMA18_X_COUNT)
1425#define bfin_write_DMA18_X_COUNT(val) bfin_write16(DMA18_X_COUNT, val)
1426#define bfin_read_DMA18_X_MODIFY() bfin_read16(DMA18_X_MODIFY)
1427#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val)
1428#define bfin_read_DMA18_Y_COUNT() bfin_read16(DMA18_Y_COUNT)
1429#define bfin_write_DMA18_Y_COUNT(val) bfin_write16(DMA18_Y_COUNT, val)
1430#define bfin_read_DMA18_Y_MODIFY() bfin_read16(DMA18_Y_MODIFY)
1431#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val)
1432#define bfin_read_DMA18_CURR_DESC_PTR() bfin_read32(DMA18_CURR_DESC_PTR)
1433#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_write32(DMA18_CURR_DESC_PTR, val)
1434#define bfin_read_DMA18_CURR_ADDR() bfin_read32(DMA18_CURR_ADDR)
1435#define bfin_write_DMA18_CURR_ADDR(val) bfin_write32(DMA18_CURR_ADDR, val)
1436#define bfin_read_DMA18_IRQ_STATUS() bfin_read16(DMA18_IRQ_STATUS)
1437#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val)
1438#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP)
1439#define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val)
1440#define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT)
1441#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val)
1442#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT)
1443#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val)
1444
1445/* DMA Channel 19 Registers */
1446
1447#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_read32(DMA19_NEXT_DESC_PTR)
1448#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_write32(DMA19_NEXT_DESC_PTR, val)
1449#define bfin_read_DMA19_START_ADDR() bfin_read32(DMA19_START_ADDR)
1450#define bfin_write_DMA19_START_ADDR(val) bfin_write32(DMA19_START_ADDR, val)
1451#define bfin_read_DMA19_CONFIG() bfin_read16(DMA19_CONFIG)
1452#define bfin_write_DMA19_CONFIG(val) bfin_write16(DMA19_CONFIG, val)
1453#define bfin_read_DMA19_X_COUNT() bfin_read16(DMA19_X_COUNT)
1454#define bfin_write_DMA19_X_COUNT(val) bfin_write16(DMA19_X_COUNT, val)
1455#define bfin_read_DMA19_X_MODIFY() bfin_read16(DMA19_X_MODIFY)
1456#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val)
1457#define bfin_read_DMA19_Y_COUNT() bfin_read16(DMA19_Y_COUNT)
1458#define bfin_write_DMA19_Y_COUNT(val) bfin_write16(DMA19_Y_COUNT, val)
1459#define bfin_read_DMA19_Y_MODIFY() bfin_read16(DMA19_Y_MODIFY)
1460#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val)
1461#define bfin_read_DMA19_CURR_DESC_PTR() bfin_read32(DMA19_CURR_DESC_PTR)
1462#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_write32(DMA19_CURR_DESC_PTR, val)
1463#define bfin_read_DMA19_CURR_ADDR() bfin_read32(DMA19_CURR_ADDR)
1464#define bfin_write_DMA19_CURR_ADDR(val) bfin_write32(DMA19_CURR_ADDR, val)
1465#define bfin_read_DMA19_IRQ_STATUS() bfin_read16(DMA19_IRQ_STATUS)
1466#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val)
1467#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP)
1468#define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val)
1469#define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT)
1470#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val)
1471#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT)
1472#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val)
1473
1474/* DMA Channel 20 Registers */
1475
1476#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_read32(DMA20_NEXT_DESC_PTR)
1477#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_write32(DMA20_NEXT_DESC_PTR, val)
1478#define bfin_read_DMA20_START_ADDR() bfin_read32(DMA20_START_ADDR)
1479#define bfin_write_DMA20_START_ADDR(val) bfin_write32(DMA20_START_ADDR, val)
1480#define bfin_read_DMA20_CONFIG() bfin_read16(DMA20_CONFIG)
1481#define bfin_write_DMA20_CONFIG(val) bfin_write16(DMA20_CONFIG, val)
1482#define bfin_read_DMA20_X_COUNT() bfin_read16(DMA20_X_COUNT)
1483#define bfin_write_DMA20_X_COUNT(val) bfin_write16(DMA20_X_COUNT, val)
1484#define bfin_read_DMA20_X_MODIFY() bfin_read16(DMA20_X_MODIFY)
1485#define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val)
1486#define bfin_read_DMA20_Y_COUNT() bfin_read16(DMA20_Y_COUNT)
1487#define bfin_write_DMA20_Y_COUNT(val) bfin_write16(DMA20_Y_COUNT, val)
1488#define bfin_read_DMA20_Y_MODIFY() bfin_read16(DMA20_Y_MODIFY)
1489#define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val)
1490#define bfin_read_DMA20_CURR_DESC_PTR() bfin_read32(DMA20_CURR_DESC_PTR)
1491#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_write32(DMA20_CURR_DESC_PTR, val)
1492#define bfin_read_DMA20_CURR_ADDR() bfin_read32(DMA20_CURR_ADDR)
1493#define bfin_write_DMA20_CURR_ADDR(val) bfin_write32(DMA20_CURR_ADDR, val)
1494#define bfin_read_DMA20_IRQ_STATUS() bfin_read16(DMA20_IRQ_STATUS)
1495#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val)
1496#define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP)
1497#define bfin_write_DMA20_PERIPHERAL_MAP(val) bfin_write16(DMA20_PERIPHERAL_MAP, val)
1498#define bfin_read_DMA20_CURR_X_COUNT() bfin_read16(DMA20_CURR_X_COUNT)
1499#define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write16(DMA20_CURR_X_COUNT, val)
1500#define bfin_read_DMA20_CURR_Y_COUNT() bfin_read16(DMA20_CURR_Y_COUNT)
1501#define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write16(DMA20_CURR_Y_COUNT, val)
1502
1503/* DMA Channel 21 Registers */
1504
1505#define bfin_read_DMA21_NEXT_DESC_PTR() bfin_read32(DMA21_NEXT_DESC_PTR)
1506#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_write32(DMA21_NEXT_DESC_PTR, val)
1507#define bfin_read_DMA21_START_ADDR() bfin_read32(DMA21_START_ADDR)
1508#define bfin_write_DMA21_START_ADDR(val) bfin_write32(DMA21_START_ADDR, val)
1509#define bfin_read_DMA21_CONFIG() bfin_read16(DMA21_CONFIG)
1510#define bfin_write_DMA21_CONFIG(val) bfin_write16(DMA21_CONFIG, val)
1511#define bfin_read_DMA21_X_COUNT() bfin_read16(DMA21_X_COUNT)
1512#define bfin_write_DMA21_X_COUNT(val) bfin_write16(DMA21_X_COUNT, val)
1513#define bfin_read_DMA21_X_MODIFY() bfin_read16(DMA21_X_MODIFY)
1514#define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val)
1515#define bfin_read_DMA21_Y_COUNT() bfin_read16(DMA21_Y_COUNT)
1516#define bfin_write_DMA21_Y_COUNT(val) bfin_write16(DMA21_Y_COUNT, val)
1517#define bfin_read_DMA21_Y_MODIFY() bfin_read16(DMA21_Y_MODIFY)
1518#define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val)
1519#define bfin_read_DMA21_CURR_DESC_PTR() bfin_read32(DMA21_CURR_DESC_PTR)
1520#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_write32(DMA21_CURR_DESC_PTR, val)
1521#define bfin_read_DMA21_CURR_ADDR() bfin_read32(DMA21_CURR_ADDR)
1522#define bfin_write_DMA21_CURR_ADDR(val) bfin_write32(DMA21_CURR_ADDR, val)
1523#define bfin_read_DMA21_IRQ_STATUS() bfin_read16(DMA21_IRQ_STATUS)
1524#define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val)
1525#define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP)
1526#define bfin_write_DMA21_PERIPHERAL_MAP(val) bfin_write16(DMA21_PERIPHERAL_MAP, val)
1527#define bfin_read_DMA21_CURR_X_COUNT() bfin_read16(DMA21_CURR_X_COUNT)
1528#define bfin_write_DMA21_CURR_X_COUNT(val) bfin_write16(DMA21_CURR_X_COUNT, val)
1529#define bfin_read_DMA21_CURR_Y_COUNT() bfin_read16(DMA21_CURR_Y_COUNT)
1530#define bfin_write_DMA21_CURR_Y_COUNT(val) bfin_write16(DMA21_CURR_Y_COUNT, val)
1531
1532/* DMA Channel 22 Registers */
1533
1534#define bfin_read_DMA22_NEXT_DESC_PTR() bfin_read32(DMA22_NEXT_DESC_PTR)
1535#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_write32(DMA22_NEXT_DESC_PTR, val)
1536#define bfin_read_DMA22_START_ADDR() bfin_read32(DMA22_START_ADDR)
1537#define bfin_write_DMA22_START_ADDR(val) bfin_write32(DMA22_START_ADDR, val)
1538#define bfin_read_DMA22_CONFIG() bfin_read16(DMA22_CONFIG)
1539#define bfin_write_DMA22_CONFIG(val) bfin_write16(DMA22_CONFIG, val)
1540#define bfin_read_DMA22_X_COUNT() bfin_read16(DMA22_X_COUNT)
1541#define bfin_write_DMA22_X_COUNT(val) bfin_write16(DMA22_X_COUNT, val)
1542#define bfin_read_DMA22_X_MODIFY() bfin_read16(DMA22_X_MODIFY)
1543#define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val)
1544#define bfin_read_DMA22_Y_COUNT() bfin_read16(DMA22_Y_COUNT)
1545#define bfin_write_DMA22_Y_COUNT(val) bfin_write16(DMA22_Y_COUNT, val)
1546#define bfin_read_DMA22_Y_MODIFY() bfin_read16(DMA22_Y_MODIFY)
1547#define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val)
1548#define bfin_read_DMA22_CURR_DESC_PTR() bfin_read32(DMA22_CURR_DESC_PTR)
1549#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_write32(DMA22_CURR_DESC_PTR, val)
1550#define bfin_read_DMA22_CURR_ADDR() bfin_read32(DMA22_CURR_ADDR)
1551#define bfin_write_DMA22_CURR_ADDR(val) bfin_write32(DMA22_CURR_ADDR, val)
1552#define bfin_read_DMA22_IRQ_STATUS() bfin_read16(DMA22_IRQ_STATUS)
1553#define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val)
1554#define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP)
1555#define bfin_write_DMA22_PERIPHERAL_MAP(val) bfin_write16(DMA22_PERIPHERAL_MAP, val)
1556#define bfin_read_DMA22_CURR_X_COUNT() bfin_read16(DMA22_CURR_X_COUNT)
1557#define bfin_write_DMA22_CURR_X_COUNT(val) bfin_write16(DMA22_CURR_X_COUNT, val)
1558#define bfin_read_DMA22_CURR_Y_COUNT() bfin_read16(DMA22_CURR_Y_COUNT)
1559#define bfin_write_DMA22_CURR_Y_COUNT(val) bfin_write16(DMA22_CURR_Y_COUNT, val)
1560
1561/* DMA Channel 23 Registers */
1562
1563#define bfin_read_DMA23_NEXT_DESC_PTR() bfin_read32(DMA23_NEXT_DESC_PTR)
1564#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_write32(DMA23_NEXT_DESC_PTR, val)
1565#define bfin_read_DMA23_START_ADDR() bfin_read32(DMA23_START_ADDR)
1566#define bfin_write_DMA23_START_ADDR(val) bfin_write32(DMA23_START_ADDR, val)
1567#define bfin_read_DMA23_CONFIG() bfin_read16(DMA23_CONFIG)
1568#define bfin_write_DMA23_CONFIG(val) bfin_write16(DMA23_CONFIG, val)
1569#define bfin_read_DMA23_X_COUNT() bfin_read16(DMA23_X_COUNT)
1570#define bfin_write_DMA23_X_COUNT(val) bfin_write16(DMA23_X_COUNT, val)
1571#define bfin_read_DMA23_X_MODIFY() bfin_read16(DMA23_X_MODIFY)
1572#define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val)
1573#define bfin_read_DMA23_Y_COUNT() bfin_read16(DMA23_Y_COUNT)
1574#define bfin_write_DMA23_Y_COUNT(val) bfin_write16(DMA23_Y_COUNT, val)
1575#define bfin_read_DMA23_Y_MODIFY() bfin_read16(DMA23_Y_MODIFY)
1576#define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val)
1577#define bfin_read_DMA23_CURR_DESC_PTR() bfin_read32(DMA23_CURR_DESC_PTR)
1578#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_write32(DMA23_CURR_DESC_PTR, val)
1579#define bfin_read_DMA23_CURR_ADDR() bfin_read32(DMA23_CURR_ADDR)
1580#define bfin_write_DMA23_CURR_ADDR(val) bfin_write32(DMA23_CURR_ADDR, val)
1581#define bfin_read_DMA23_IRQ_STATUS() bfin_read16(DMA23_IRQ_STATUS)
1582#define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val)
1583#define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP)
1584#define bfin_write_DMA23_PERIPHERAL_MAP(val) bfin_write16(DMA23_PERIPHERAL_MAP, val)
1585#define bfin_read_DMA23_CURR_X_COUNT() bfin_read16(DMA23_CURR_X_COUNT)
1586#define bfin_write_DMA23_CURR_X_COUNT(val) bfin_write16(DMA23_CURR_X_COUNT, val)
1587#define bfin_read_DMA23_CURR_Y_COUNT() bfin_read16(DMA23_CURR_Y_COUNT)
1588#define bfin_write_DMA23_CURR_Y_COUNT(val) bfin_write16(DMA23_CURR_Y_COUNT, val)
1589
1590/* MDMA Stream 2 Registers */
1591
1592#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_read32(MDMA_D2_NEXT_DESC_PTR)
1593#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_write32(MDMA_D2_NEXT_DESC_PTR, val)
1594#define bfin_read_MDMA_D2_START_ADDR() bfin_read32(MDMA_D2_START_ADDR)
1595#define bfin_write_MDMA_D2_START_ADDR(val) bfin_write32(MDMA_D2_START_ADDR, val)
1596#define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG)
1597#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val)
1598#define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT)
1599#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val)
1600#define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY)
1601#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val)
1602#define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT)
1603#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val)
1604#define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY)
1605#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val)
1606#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_read32(MDMA_D2_CURR_DESC_PTR)
1607#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_write32(MDMA_D2_CURR_DESC_PTR, val)
1608#define bfin_read_MDMA_D2_CURR_ADDR() bfin_read32(MDMA_D2_CURR_ADDR)
1609#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_write32(MDMA_D2_CURR_ADDR, val)
1610#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
1611#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val)
1612#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
1613#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val)
1614#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT)
1615#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val)
1616#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
1617#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val)
1618#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_read32(MDMA_S2_NEXT_DESC_PTR)
1619#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_write32(MDMA_S2_NEXT_DESC_PTR, val)
1620#define bfin_read_MDMA_S2_START_ADDR() bfin_read32(MDMA_S2_START_ADDR)
1621#define bfin_write_MDMA_S2_START_ADDR(val) bfin_write32(MDMA_S2_START_ADDR, val)
1622#define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG)
1623#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val)
1624#define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT)
1625#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val)
1626#define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY)
1627#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val)
1628#define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT)
1629#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val)
1630#define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY)
1631#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val)
1632#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_read32(MDMA_S2_CURR_DESC_PTR)
1633#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_write32(MDMA_S2_CURR_DESC_PTR, val)
1634#define bfin_read_MDMA_S2_CURR_ADDR() bfin_read32(MDMA_S2_CURR_ADDR)
1635#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_write32(MDMA_S2_CURR_ADDR, val)
1636#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
1637#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val)
1638#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
1639#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val)
1640#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT)
1641#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val)
1642#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT)
1643#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val)
1644
1645/* MDMA Stream 3 Registers */
1646
1647#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_read32(MDMA_D3_NEXT_DESC_PTR)
1648#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_write32(MDMA_D3_NEXT_DESC_PTR, val)
1649#define bfin_read_MDMA_D3_START_ADDR() bfin_read32(MDMA_D3_START_ADDR)
1650#define bfin_write_MDMA_D3_START_ADDR(val) bfin_write32(MDMA_D3_START_ADDR, val)
1651#define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG)
1652#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val)
1653#define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT)
1654#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val)
1655#define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY)
1656#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val)
1657#define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT)
1658#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val)
1659#define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY)
1660#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val)
1661#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_read32(MDMA_D3_CURR_DESC_PTR)
1662#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_write32(MDMA_D3_CURR_DESC_PTR, val)
1663#define bfin_read_MDMA_D3_CURR_ADDR() bfin_read32(MDMA_D3_CURR_ADDR)
1664#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_write32(MDMA_D3_CURR_ADDR, val)
1665#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
1666#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val)
1667#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
1668#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val)
1669#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT)
1670#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val)
1671#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
1672#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val)
1673#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_read32(MDMA_S3_NEXT_DESC_PTR)
1674#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_write32(MDMA_S3_NEXT_DESC_PTR, val)
1675#define bfin_read_MDMA_S3_START_ADDR() bfin_read32(MDMA_S3_START_ADDR)
1676#define bfin_write_MDMA_S3_START_ADDR(val) bfin_write32(MDMA_S3_START_ADDR, val)
1677#define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG)
1678#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val)
1679#define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT)
1680#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val)
1681#define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY)
1682#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val)
1683#define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT)
1684#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val)
1685#define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY)
1686#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val)
1687#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_read32(MDMA_S3_CURR_DESC_PTR)
1688#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_write32(MDMA_S3_CURR_DESC_PTR, val)
1689#define bfin_read_MDMA_S3_CURR_ADDR() bfin_read32(MDMA_S3_CURR_ADDR)
1690#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_write32(MDMA_S3_CURR_ADDR, val)
1691#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
1692#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val)
1693#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
1694#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val)
1695#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT)
1696#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val)
1697#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT)
1698#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val)
1699
1700/* UART1 Registers */
1701
1702#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
1703#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
1704#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
1705#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
1706#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
1707#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
1708#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
1709#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
1710#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
1711#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
1712#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
1713#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
1714#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR)
1715#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val)
1716#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
1717#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
1718#define bfin_read_UART1_IER_SET() bfin_read16(UART1_IER_SET)
1719#define bfin_write_UART1_IER_SET(val) bfin_write16(UART1_IER_SET, val)
1720#define bfin_read_UART1_IER_CLEAR() bfin_read16(UART1_IER_CLEAR)
1721#define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val)
1722#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
1723#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
1724#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
1725#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
1726
1727/* UART2 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */
1728
1729/* SPI1 Registers */
1730
1731#define bfin_read_SPI1_CTL() bfin_read16(SPI1_CTL)
1732#define bfin_write_SPI1_CTL(val) bfin_write16(SPI1_CTL, val)
1733#define bfin_read_SPI1_FLG() bfin_read16(SPI1_FLG)
1734#define bfin_write_SPI1_FLG(val) bfin_write16(SPI1_FLG, val)
1735#define bfin_read_SPI1_STAT() bfin_read16(SPI1_STAT)
1736#define bfin_write_SPI1_STAT(val) bfin_write16(SPI1_STAT, val)
1737#define bfin_read_SPI1_TDBR() bfin_read16(SPI1_TDBR)
1738#define bfin_write_SPI1_TDBR(val) bfin_write16(SPI1_TDBR, val)
1739#define bfin_read_SPI1_RDBR() bfin_read16(SPI1_RDBR)
1740#define bfin_write_SPI1_RDBR(val) bfin_write16(SPI1_RDBR, val)
1741#define bfin_read_SPI1_BAUD() bfin_read16(SPI1_BAUD)
1742#define bfin_write_SPI1_BAUD(val) bfin_write16(SPI1_BAUD, val)
1743#define bfin_read_SPI1_SHADOW() bfin_read16(SPI1_SHADOW)
1744#define bfin_write_SPI1_SHADOW(val) bfin_write16(SPI1_SHADOW, val)
1745
1746/* SPORT2 Registers */
1747
1748#define bfin_read_SPORT2_TCR1() bfin_read16(SPORT2_TCR1)
1749#define bfin_write_SPORT2_TCR1(val) bfin_write16(SPORT2_TCR1, val)
1750#define bfin_read_SPORT2_TCR2() bfin_read16(SPORT2_TCR2)
1751#define bfin_write_SPORT2_TCR2(val) bfin_write16(SPORT2_TCR2, val)
1752#define bfin_read_SPORT2_TCLKDIV() bfin_read16(SPORT2_TCLKDIV)
1753#define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val)
1754#define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV)
1755#define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val)
1756#define bfin_read_SPORT2_TX() bfin_read32(SPORT2_TX)
1757#define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val)
1758#define bfin_read_SPORT2_RX() bfin_read32(SPORT2_RX)
1759#define bfin_write_SPORT2_RX(val) bfin_write32(SPORT2_RX, val)
1760#define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1)
1761#define bfin_write_SPORT2_RCR1(val) bfin_write16(SPORT2_RCR1, val)
1762#define bfin_read_SPORT2_RCR2() bfin_read16(SPORT2_RCR2)
1763#define bfin_write_SPORT2_RCR2(val) bfin_write16(SPORT2_RCR2, val)
1764#define bfin_read_SPORT2_RCLKDIV() bfin_read16(SPORT2_RCLKDIV)
1765#define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val)
1766#define bfin_read_SPORT2_RFSDIV() bfin_read16(SPORT2_RFSDIV)
1767#define bfin_write_SPORT2_RFSDIV(val) bfin_write16(SPORT2_RFSDIV, val)
1768#define bfin_read_SPORT2_STAT() bfin_read16(SPORT2_STAT)
1769#define bfin_write_SPORT2_STAT(val) bfin_write16(SPORT2_STAT, val)
1770#define bfin_read_SPORT2_CHNL() bfin_read16(SPORT2_CHNL)
1771#define bfin_write_SPORT2_CHNL(val) bfin_write16(SPORT2_CHNL, val)
1772#define bfin_read_SPORT2_MCMC1() bfin_read16(SPORT2_MCMC1)
1773#define bfin_write_SPORT2_MCMC1(val) bfin_write16(SPORT2_MCMC1, val)
1774#define bfin_read_SPORT2_MCMC2() bfin_read16(SPORT2_MCMC2)
1775#define bfin_write_SPORT2_MCMC2(val) bfin_write16(SPORT2_MCMC2, val)
1776#define bfin_read_SPORT2_MTCS0() bfin_read32(SPORT2_MTCS0)
1777#define bfin_write_SPORT2_MTCS0(val) bfin_write32(SPORT2_MTCS0, val)
1778#define bfin_read_SPORT2_MTCS1() bfin_read32(SPORT2_MTCS1)
1779#define bfin_write_SPORT2_MTCS1(val) bfin_write32(SPORT2_MTCS1, val)
1780#define bfin_read_SPORT2_MTCS2() bfin_read32(SPORT2_MTCS2)
1781#define bfin_write_SPORT2_MTCS2(val) bfin_write32(SPORT2_MTCS2, val)
1782#define bfin_read_SPORT2_MTCS3() bfin_read32(SPORT2_MTCS3)
1783#define bfin_write_SPORT2_MTCS3(val) bfin_write32(SPORT2_MTCS3, val)
1784#define bfin_read_SPORT2_MRCS0() bfin_read32(SPORT2_MRCS0)
1785#define bfin_write_SPORT2_MRCS0(val) bfin_write32(SPORT2_MRCS0, val)
1786#define bfin_read_SPORT2_MRCS1() bfin_read32(SPORT2_MRCS1)
1787#define bfin_write_SPORT2_MRCS1(val) bfin_write32(SPORT2_MRCS1, val)
1788#define bfin_read_SPORT2_MRCS2() bfin_read32(SPORT2_MRCS2)
1789#define bfin_write_SPORT2_MRCS2(val) bfin_write32(SPORT2_MRCS2, val)
1790#define bfin_read_SPORT2_MRCS3() bfin_read32(SPORT2_MRCS3)
1791#define bfin_write_SPORT2_MRCS3(val) bfin_write32(SPORT2_MRCS3, val)
1792
1793/* SPORT3 Registers */
1794
1795#define bfin_read_SPORT3_TCR1() bfin_read16(SPORT3_TCR1)
1796#define bfin_write_SPORT3_TCR1(val) bfin_write16(SPORT3_TCR1, val)
1797#define bfin_read_SPORT3_TCR2() bfin_read16(SPORT3_TCR2)
1798#define bfin_write_SPORT3_TCR2(val) bfin_write16(SPORT3_TCR2, val)
1799#define bfin_read_SPORT3_TCLKDIV() bfin_read16(SPORT3_TCLKDIV)
1800#define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val)
1801#define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV)
1802#define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val)
1803#define bfin_read_SPORT3_TX() bfin_read32(SPORT3_TX)
1804#define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val)
1805#define bfin_read_SPORT3_RX() bfin_read32(SPORT3_RX)
1806#define bfin_write_SPORT3_RX(val) bfin_write32(SPORT3_RX, val)
1807#define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1)
1808#define bfin_write_SPORT3_RCR1(val) bfin_write16(SPORT3_RCR1, val)
1809#define bfin_read_SPORT3_RCR2() bfin_read16(SPORT3_RCR2)
1810#define bfin_write_SPORT3_RCR2(val) bfin_write16(SPORT3_RCR2, val)
1811#define bfin_read_SPORT3_RCLKDIV() bfin_read16(SPORT3_RCLKDIV)
1812#define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val)
1813#define bfin_read_SPORT3_RFSDIV() bfin_read16(SPORT3_RFSDIV)
1814#define bfin_write_SPORT3_RFSDIV(val) bfin_write16(SPORT3_RFSDIV, val)
1815#define bfin_read_SPORT3_STAT() bfin_read16(SPORT3_STAT)
1816#define bfin_write_SPORT3_STAT(val) bfin_write16(SPORT3_STAT, val)
1817#define bfin_read_SPORT3_CHNL() bfin_read16(SPORT3_CHNL)
1818#define bfin_write_SPORT3_CHNL(val) bfin_write16(SPORT3_CHNL, val)
1819#define bfin_read_SPORT3_MCMC1() bfin_read16(SPORT3_MCMC1)
1820#define bfin_write_SPORT3_MCMC1(val) bfin_write16(SPORT3_MCMC1, val)
1821#define bfin_read_SPORT3_MCMC2() bfin_read16(SPORT3_MCMC2)
1822#define bfin_write_SPORT3_MCMC2(val) bfin_write16(SPORT3_MCMC2, val)
1823#define bfin_read_SPORT3_MTCS0() bfin_read32(SPORT3_MTCS0)
1824#define bfin_write_SPORT3_MTCS0(val) bfin_write32(SPORT3_MTCS0, val)
1825#define bfin_read_SPORT3_MTCS1() bfin_read32(SPORT3_MTCS1)
1826#define bfin_write_SPORT3_MTCS1(val) bfin_write32(SPORT3_MTCS1, val)
1827#define bfin_read_SPORT3_MTCS2() bfin_read32(SPORT3_MTCS2)
1828#define bfin_write_SPORT3_MTCS2(val) bfin_write32(SPORT3_MTCS2, val)
1829#define bfin_read_SPORT3_MTCS3() bfin_read32(SPORT3_MTCS3)
1830#define bfin_write_SPORT3_MTCS3(val) bfin_write32(SPORT3_MTCS3, val)
1831#define bfin_read_SPORT3_MRCS0() bfin_read32(SPORT3_MRCS0)
1832#define bfin_write_SPORT3_MRCS0(val) bfin_write32(SPORT3_MRCS0, val)
1833#define bfin_read_SPORT3_MRCS1() bfin_read32(SPORT3_MRCS1)
1834#define bfin_write_SPORT3_MRCS1(val) bfin_write32(SPORT3_MRCS1, val)
1835#define bfin_read_SPORT3_MRCS2() bfin_read32(SPORT3_MRCS2)
1836#define bfin_write_SPORT3_MRCS2(val) bfin_write32(SPORT3_MRCS2, val)
1837#define bfin_read_SPORT3_MRCS3() bfin_read32(SPORT3_MRCS3)
1838#define bfin_write_SPORT3_MRCS3(val) bfin_write32(SPORT3_MRCS3, val)
1839
1840/* EPPI2 Registers */
1841
1842#define bfin_read_EPPI2_STATUS() bfin_read16(EPPI2_STATUS)
1843#define bfin_write_EPPI2_STATUS(val) bfin_write16(EPPI2_STATUS, val)
1844#define bfin_read_EPPI2_HCOUNT() bfin_read16(EPPI2_HCOUNT)
1845#define bfin_write_EPPI2_HCOUNT(val) bfin_write16(EPPI2_HCOUNT, val)
1846#define bfin_read_EPPI2_HDELAY() bfin_read16(EPPI2_HDELAY)
1847#define bfin_write_EPPI2_HDELAY(val) bfin_write16(EPPI2_HDELAY, val)
1848#define bfin_read_EPPI2_VCOUNT() bfin_read16(EPPI2_VCOUNT)
1849#define bfin_write_EPPI2_VCOUNT(val) bfin_write16(EPPI2_VCOUNT, val)
1850#define bfin_read_EPPI2_VDELAY() bfin_read16(EPPI2_VDELAY)
1851#define bfin_write_EPPI2_VDELAY(val) bfin_write16(EPPI2_VDELAY, val)
1852#define bfin_read_EPPI2_FRAME() bfin_read16(EPPI2_FRAME)
1853#define bfin_write_EPPI2_FRAME(val) bfin_write16(EPPI2_FRAME, val)
1854#define bfin_read_EPPI2_LINE() bfin_read16(EPPI2_LINE)
1855#define bfin_write_EPPI2_LINE(val) bfin_write16(EPPI2_LINE, val)
1856#define bfin_read_EPPI2_CLKDIV() bfin_read16(EPPI2_CLKDIV)
1857#define bfin_write_EPPI2_CLKDIV(val) bfin_write16(EPPI2_CLKDIV, val)
1858#define bfin_read_EPPI2_CONTROL() bfin_read32(EPPI2_CONTROL)
1859#define bfin_write_EPPI2_CONTROL(val) bfin_write32(EPPI2_CONTROL, val)
1860#define bfin_read_EPPI2_FS1W_HBL() bfin_read32(EPPI2_FS1W_HBL)
1861#define bfin_write_EPPI2_FS1W_HBL(val) bfin_write32(EPPI2_FS1W_HBL, val)
1862#define bfin_read_EPPI2_FS1P_AVPL() bfin_read32(EPPI2_FS1P_AVPL)
1863#define bfin_write_EPPI2_FS1P_AVPL(val) bfin_write32(EPPI2_FS1P_AVPL, val)
1864#define bfin_read_EPPI2_FS2W_LVB() bfin_read32(EPPI2_FS2W_LVB)
1865#define bfin_write_EPPI2_FS2W_LVB(val) bfin_write32(EPPI2_FS2W_LVB, val)
1866#define bfin_read_EPPI2_FS2P_LAVF() bfin_read32(EPPI2_FS2P_LAVF)
1867#define bfin_write_EPPI2_FS2P_LAVF(val) bfin_write32(EPPI2_FS2P_LAVF, val)
1868#define bfin_read_EPPI2_CLIP() bfin_read32(EPPI2_CLIP)
1869#define bfin_write_EPPI2_CLIP(val) bfin_write32(EPPI2_CLIP, val)
1870
1871/* CAN Controller 0 Config 1 Registers */
1872
1873#define bfin_read_CAN0_MC1() bfin_read16(CAN0_MC1)
1874#define bfin_write_CAN0_MC1(val) bfin_write16(CAN0_MC1, val)
1875#define bfin_read_CAN0_MD1() bfin_read16(CAN0_MD1)
1876#define bfin_write_CAN0_MD1(val) bfin_write16(CAN0_MD1, val)
1877#define bfin_read_CAN0_TRS1() bfin_read16(CAN0_TRS1)
1878#define bfin_write_CAN0_TRS1(val) bfin_write16(CAN0_TRS1, val)
1879#define bfin_read_CAN0_TRR1() bfin_read16(CAN0_TRR1)
1880#define bfin_write_CAN0_TRR1(val) bfin_write16(CAN0_TRR1, val)
1881#define bfin_read_CAN0_TA1() bfin_read16(CAN0_TA1)
1882#define bfin_write_CAN0_TA1(val) bfin_write16(CAN0_TA1, val)
1883#define bfin_read_CAN0_AA1() bfin_read16(CAN0_AA1)
1884#define bfin_write_CAN0_AA1(val) bfin_write16(CAN0_AA1, val)
1885#define bfin_read_CAN0_RMP1() bfin_read16(CAN0_RMP1)
1886#define bfin_write_CAN0_RMP1(val) bfin_write16(CAN0_RMP1, val)
1887#define bfin_read_CAN0_RML1() bfin_read16(CAN0_RML1)
1888#define bfin_write_CAN0_RML1(val) bfin_write16(CAN0_RML1, val)
1889#define bfin_read_CAN0_MBTIF1() bfin_read16(CAN0_MBTIF1)
1890#define bfin_write_CAN0_MBTIF1(val) bfin_write16(CAN0_MBTIF1, val)
1891#define bfin_read_CAN0_MBRIF1() bfin_read16(CAN0_MBRIF1)
1892#define bfin_write_CAN0_MBRIF1(val) bfin_write16(CAN0_MBRIF1, val)
1893#define bfin_read_CAN0_MBIM1() bfin_read16(CAN0_MBIM1)
1894#define bfin_write_CAN0_MBIM1(val) bfin_write16(CAN0_MBIM1, val)
1895#define bfin_read_CAN0_RFH1() bfin_read16(CAN0_RFH1)
1896#define bfin_write_CAN0_RFH1(val) bfin_write16(CAN0_RFH1, val)
1897#define bfin_read_CAN0_OPSS1() bfin_read16(CAN0_OPSS1)
1898#define bfin_write_CAN0_OPSS1(val) bfin_write16(CAN0_OPSS1, val)
1899
1900/* CAN Controller 0 Config 2 Registers */
1901
1902#define bfin_read_CAN0_MC2() bfin_read16(CAN0_MC2)
1903#define bfin_write_CAN0_MC2(val) bfin_write16(CAN0_MC2, val)
1904#define bfin_read_CAN0_MD2() bfin_read16(CAN0_MD2)
1905#define bfin_write_CAN0_MD2(val) bfin_write16(CAN0_MD2, val)
1906#define bfin_read_CAN0_TRS2() bfin_read16(CAN0_TRS2)
1907#define bfin_write_CAN0_TRS2(val) bfin_write16(CAN0_TRS2, val)
1908#define bfin_read_CAN0_TRR2() bfin_read16(CAN0_TRR2)
1909#define bfin_write_CAN0_TRR2(val) bfin_write16(CAN0_TRR2, val)
1910#define bfin_read_CAN0_TA2() bfin_read16(CAN0_TA2)
1911#define bfin_write_CAN0_TA2(val) bfin_write16(CAN0_TA2, val)
1912#define bfin_read_CAN0_AA2() bfin_read16(CAN0_AA2)
1913#define bfin_write_CAN0_AA2(val) bfin_write16(CAN0_AA2, val)
1914#define bfin_read_CAN0_RMP2() bfin_read16(CAN0_RMP2)
1915#define bfin_write_CAN0_RMP2(val) bfin_write16(CAN0_RMP2, val)
1916#define bfin_read_CAN0_RML2() bfin_read16(CAN0_RML2)
1917#define bfin_write_CAN0_RML2(val) bfin_write16(CAN0_RML2, val)
1918#define bfin_read_CAN0_MBTIF2() bfin_read16(CAN0_MBTIF2)
1919#define bfin_write_CAN0_MBTIF2(val) bfin_write16(CAN0_MBTIF2, val)
1920#define bfin_read_CAN0_MBRIF2() bfin_read16(CAN0_MBRIF2)
1921#define bfin_write_CAN0_MBRIF2(val) bfin_write16(CAN0_MBRIF2, val)
1922#define bfin_read_CAN0_MBIM2() bfin_read16(CAN0_MBIM2)
1923#define bfin_write_CAN0_MBIM2(val) bfin_write16(CAN0_MBIM2, val)
1924#define bfin_read_CAN0_RFH2() bfin_read16(CAN0_RFH2)
1925#define bfin_write_CAN0_RFH2(val) bfin_write16(CAN0_RFH2, val)
1926#define bfin_read_CAN0_OPSS2() bfin_read16(CAN0_OPSS2)
1927#define bfin_write_CAN0_OPSS2(val) bfin_write16(CAN0_OPSS2, val)
1928
1929/* CAN Controller 0 Clock/Interrubfin_read_()t/Counter Registers */
1930
1931#define bfin_read_CAN0_CLOCK() bfin_read16(CAN0_CLOCK)
1932#define bfin_write_CAN0_CLOCK(val) bfin_write16(CAN0_CLOCK, val)
1933#define bfin_read_CAN0_TIMING() bfin_read16(CAN0_TIMING)
1934#define bfin_write_CAN0_TIMING(val) bfin_write16(CAN0_TIMING, val)
1935#define bfin_read_CAN0_DEBUG() bfin_read16(CAN0_DEBUG)
1936#define bfin_write_CAN0_DEBUG(val) bfin_write16(CAN0_DEBUG, val)
1937#define bfin_read_CAN0_STATUS() bfin_read16(CAN0_STATUS)
1938#define bfin_write_CAN0_STATUS(val) bfin_write16(CAN0_STATUS, val)
1939#define bfin_read_CAN0_CEC() bfin_read16(CAN0_CEC)
1940#define bfin_write_CAN0_CEC(val) bfin_write16(CAN0_CEC, val)
1941#define bfin_read_CAN0_GIS() bfin_read16(CAN0_GIS)
1942#define bfin_write_CAN0_GIS(val) bfin_write16(CAN0_GIS, val)
1943#define bfin_read_CAN0_GIM() bfin_read16(CAN0_GIM)
1944#define bfin_write_CAN0_GIM(val) bfin_write16(CAN0_GIM, val)
1945#define bfin_read_CAN0_GIF() bfin_read16(CAN0_GIF)
1946#define bfin_write_CAN0_GIF(val) bfin_write16(CAN0_GIF, val)
1947#define bfin_read_CAN0_CONTROL() bfin_read16(CAN0_CONTROL)
1948#define bfin_write_CAN0_CONTROL(val) bfin_write16(CAN0_CONTROL, val)
1949#define bfin_read_CAN0_INTR() bfin_read16(CAN0_INTR)
1950#define bfin_write_CAN0_INTR(val) bfin_write16(CAN0_INTR, val)
1951#define bfin_read_CAN0_MBTD() bfin_read16(CAN0_MBTD)
1952#define bfin_write_CAN0_MBTD(val) bfin_write16(CAN0_MBTD, val)
1953#define bfin_read_CAN0_EWR() bfin_read16(CAN0_EWR)
1954#define bfin_write_CAN0_EWR(val) bfin_write16(CAN0_EWR, val)
1955#define bfin_read_CAN0_ESR() bfin_read16(CAN0_ESR)
1956#define bfin_write_CAN0_ESR(val) bfin_write16(CAN0_ESR, val)
1957#define bfin_read_CAN0_UCCNT() bfin_read16(CAN0_UCCNT)
1958#define bfin_write_CAN0_UCCNT(val) bfin_write16(CAN0_UCCNT, val)
1959#define bfin_read_CAN0_UCRC() bfin_read16(CAN0_UCRC)
1960#define bfin_write_CAN0_UCRC(val) bfin_write16(CAN0_UCRC, val)
1961#define bfin_read_CAN0_UCCNF() bfin_read16(CAN0_UCCNF)
1962#define bfin_write_CAN0_UCCNF(val) bfin_write16(CAN0_UCCNF, val)
1963
1964/* CAN Controller 0 Accebfin_read_()tance Registers */
1965
1966#define bfin_read_CAN0_AM00L() bfin_read16(CAN0_AM00L)
1967#define bfin_write_CAN0_AM00L(val) bfin_write16(CAN0_AM00L, val)
1968#define bfin_read_CAN0_AM00H() bfin_read16(CAN0_AM00H)
1969#define bfin_write_CAN0_AM00H(val) bfin_write16(CAN0_AM00H, val)
1970#define bfin_read_CAN0_AM01L() bfin_read16(CAN0_AM01L)
1971#define bfin_write_CAN0_AM01L(val) bfin_write16(CAN0_AM01L, val)
1972#define bfin_read_CAN0_AM01H() bfin_read16(CAN0_AM01H)
1973#define bfin_write_CAN0_AM01H(val) bfin_write16(CAN0_AM01H, val)
1974#define bfin_read_CAN0_AM02L() bfin_read16(CAN0_AM02L)
1975#define bfin_write_CAN0_AM02L(val) bfin_write16(CAN0_AM02L, val)
1976#define bfin_read_CAN0_AM02H() bfin_read16(CAN0_AM02H)
1977#define bfin_write_CAN0_AM02H(val) bfin_write16(CAN0_AM02H, val)
1978#define bfin_read_CAN0_AM03L() bfin_read16(CAN0_AM03L)
1979#define bfin_write_CAN0_AM03L(val) bfin_write16(CAN0_AM03L, val)
1980#define bfin_read_CAN0_AM03H() bfin_read16(CAN0_AM03H)
1981#define bfin_write_CAN0_AM03H(val) bfin_write16(CAN0_AM03H, val)
1982#define bfin_read_CAN0_AM04L() bfin_read16(CAN0_AM04L)
1983#define bfin_write_CAN0_AM04L(val) bfin_write16(CAN0_AM04L, val)
1984#define bfin_read_CAN0_AM04H() bfin_read16(CAN0_AM04H)
1985#define bfin_write_CAN0_AM04H(val) bfin_write16(CAN0_AM04H, val)
1986#define bfin_read_CAN0_AM05L() bfin_read16(CAN0_AM05L)
1987#define bfin_write_CAN0_AM05L(val) bfin_write16(CAN0_AM05L, val)
1988#define bfin_read_CAN0_AM05H() bfin_read16(CAN0_AM05H)
1989#define bfin_write_CAN0_AM05H(val) bfin_write16(CAN0_AM05H, val)
1990#define bfin_read_CAN0_AM06L() bfin_read16(CAN0_AM06L)
1991#define bfin_write_CAN0_AM06L(val) bfin_write16(CAN0_AM06L, val)
1992#define bfin_read_CAN0_AM06H() bfin_read16(CAN0_AM06H)
1993#define bfin_write_CAN0_AM06H(val) bfin_write16(CAN0_AM06H, val)
1994#define bfin_read_CAN0_AM07L() bfin_read16(CAN0_AM07L)
1995#define bfin_write_CAN0_AM07L(val) bfin_write16(CAN0_AM07L, val)
1996#define bfin_read_CAN0_AM07H() bfin_read16(CAN0_AM07H)
1997#define bfin_write_CAN0_AM07H(val) bfin_write16(CAN0_AM07H, val)
1998#define bfin_read_CAN0_AM08L() bfin_read16(CAN0_AM08L)
1999#define bfin_write_CAN0_AM08L(val) bfin_write16(CAN0_AM08L, val)
2000#define bfin_read_CAN0_AM08H() bfin_read16(CAN0_AM08H)
2001#define bfin_write_CAN0_AM08H(val) bfin_write16(CAN0_AM08H, val)
2002#define bfin_read_CAN0_AM09L() bfin_read16(CAN0_AM09L)
2003#define bfin_write_CAN0_AM09L(val) bfin_write16(CAN0_AM09L, val)
2004#define bfin_read_CAN0_AM09H() bfin_read16(CAN0_AM09H)
2005#define bfin_write_CAN0_AM09H(val) bfin_write16(CAN0_AM09H, val)
2006#define bfin_read_CAN0_AM10L() bfin_read16(CAN0_AM10L)
2007#define bfin_write_CAN0_AM10L(val) bfin_write16(CAN0_AM10L, val)
2008#define bfin_read_CAN0_AM10H() bfin_read16(CAN0_AM10H)
2009#define bfin_write_CAN0_AM10H(val) bfin_write16(CAN0_AM10H, val)
2010#define bfin_read_CAN0_AM11L() bfin_read16(CAN0_AM11L)
2011#define bfin_write_CAN0_AM11L(val) bfin_write16(CAN0_AM11L, val)
2012#define bfin_read_CAN0_AM11H() bfin_read16(CAN0_AM11H)
2013#define bfin_write_CAN0_AM11H(val) bfin_write16(CAN0_AM11H, val)
2014#define bfin_read_CAN0_AM12L() bfin_read16(CAN0_AM12L)
2015#define bfin_write_CAN0_AM12L(val) bfin_write16(CAN0_AM12L, val)
2016#define bfin_read_CAN0_AM12H() bfin_read16(CAN0_AM12H)
2017#define bfin_write_CAN0_AM12H(val) bfin_write16(CAN0_AM12H, val)
2018#define bfin_read_CAN0_AM13L() bfin_read16(CAN0_AM13L)
2019#define bfin_write_CAN0_AM13L(val) bfin_write16(CAN0_AM13L, val)
2020#define bfin_read_CAN0_AM13H() bfin_read16(CAN0_AM13H)
2021#define bfin_write_CAN0_AM13H(val) bfin_write16(CAN0_AM13H, val)
2022#define bfin_read_CAN0_AM14L() bfin_read16(CAN0_AM14L)
2023#define bfin_write_CAN0_AM14L(val) bfin_write16(CAN0_AM14L, val)
2024#define bfin_read_CAN0_AM14H() bfin_read16(CAN0_AM14H)
2025#define bfin_write_CAN0_AM14H(val) bfin_write16(CAN0_AM14H, val)
2026#define bfin_read_CAN0_AM15L() bfin_read16(CAN0_AM15L)
2027#define bfin_write_CAN0_AM15L(val) bfin_write16(CAN0_AM15L, val)
2028#define bfin_read_CAN0_AM15H() bfin_read16(CAN0_AM15H)
2029#define bfin_write_CAN0_AM15H(val) bfin_write16(CAN0_AM15H, val)
2030
2031/* CAN Controller 0 Accebfin_read_()tance Registers */
2032
2033#define bfin_read_CAN0_AM16L() bfin_read16(CAN0_AM16L)
2034#define bfin_write_CAN0_AM16L(val) bfin_write16(CAN0_AM16L, val)
2035#define bfin_read_CAN0_AM16H() bfin_read16(CAN0_AM16H)
2036#define bfin_write_CAN0_AM16H(val) bfin_write16(CAN0_AM16H, val)
2037#define bfin_read_CAN0_AM17L() bfin_read16(CAN0_AM17L)
2038#define bfin_write_CAN0_AM17L(val) bfin_write16(CAN0_AM17L, val)
2039#define bfin_read_CAN0_AM17H() bfin_read16(CAN0_AM17H)
2040#define bfin_write_CAN0_AM17H(val) bfin_write16(CAN0_AM17H, val)
2041#define bfin_read_CAN0_AM18L() bfin_read16(CAN0_AM18L)
2042#define bfin_write_CAN0_AM18L(val) bfin_write16(CAN0_AM18L, val)
2043#define bfin_read_CAN0_AM18H() bfin_read16(CAN0_AM18H)
2044#define bfin_write_CAN0_AM18H(val) bfin_write16(CAN0_AM18H, val)
2045#define bfin_read_CAN0_AM19L() bfin_read16(CAN0_AM19L)
2046#define bfin_write_CAN0_AM19L(val) bfin_write16(CAN0_AM19L, val)
2047#define bfin_read_CAN0_AM19H() bfin_read16(CAN0_AM19H)
2048#define bfin_write_CAN0_AM19H(val) bfin_write16(CAN0_AM19H, val)
2049#define bfin_read_CAN0_AM20L() bfin_read16(CAN0_AM20L)
2050#define bfin_write_CAN0_AM20L(val) bfin_write16(CAN0_AM20L, val)
2051#define bfin_read_CAN0_AM20H() bfin_read16(CAN0_AM20H)
2052#define bfin_write_CAN0_AM20H(val) bfin_write16(CAN0_AM20H, val)
2053#define bfin_read_CAN0_AM21L() bfin_read16(CAN0_AM21L)
2054#define bfin_write_CAN0_AM21L(val) bfin_write16(CAN0_AM21L, val)
2055#define bfin_read_CAN0_AM21H() bfin_read16(CAN0_AM21H)
2056#define bfin_write_CAN0_AM21H(val) bfin_write16(CAN0_AM21H, val)
2057#define bfin_read_CAN0_AM22L() bfin_read16(CAN0_AM22L)
2058#define bfin_write_CAN0_AM22L(val) bfin_write16(CAN0_AM22L, val)
2059#define bfin_read_CAN0_AM22H() bfin_read16(CAN0_AM22H)
2060#define bfin_write_CAN0_AM22H(val) bfin_write16(CAN0_AM22H, val)
2061#define bfin_read_CAN0_AM23L() bfin_read16(CAN0_AM23L)
2062#define bfin_write_CAN0_AM23L(val) bfin_write16(CAN0_AM23L, val)
2063#define bfin_read_CAN0_AM23H() bfin_read16(CAN0_AM23H)
2064#define bfin_write_CAN0_AM23H(val) bfin_write16(CAN0_AM23H, val)
2065#define bfin_read_CAN0_AM24L() bfin_read16(CAN0_AM24L)
2066#define bfin_write_CAN0_AM24L(val) bfin_write16(CAN0_AM24L, val)
2067#define bfin_read_CAN0_AM24H() bfin_read16(CAN0_AM24H)
2068#define bfin_write_CAN0_AM24H(val) bfin_write16(CAN0_AM24H, val)
2069#define bfin_read_CAN0_AM25L() bfin_read16(CAN0_AM25L)
2070#define bfin_write_CAN0_AM25L(val) bfin_write16(CAN0_AM25L, val)
2071#define bfin_read_CAN0_AM25H() bfin_read16(CAN0_AM25H)
2072#define bfin_write_CAN0_AM25H(val) bfin_write16(CAN0_AM25H, val)
2073#define bfin_read_CAN0_AM26L() bfin_read16(CAN0_AM26L)
2074#define bfin_write_CAN0_AM26L(val) bfin_write16(CAN0_AM26L, val)
2075#define bfin_read_CAN0_AM26H() bfin_read16(CAN0_AM26H)
2076#define bfin_write_CAN0_AM26H(val) bfin_write16(CAN0_AM26H, val)
2077#define bfin_read_CAN0_AM27L() bfin_read16(CAN0_AM27L)
2078#define bfin_write_CAN0_AM27L(val) bfin_write16(CAN0_AM27L, val)
2079#define bfin_read_CAN0_AM27H() bfin_read16(CAN0_AM27H)
2080#define bfin_write_CAN0_AM27H(val) bfin_write16(CAN0_AM27H, val)
2081#define bfin_read_CAN0_AM28L() bfin_read16(CAN0_AM28L)
2082#define bfin_write_CAN0_AM28L(val) bfin_write16(CAN0_AM28L, val)
2083#define bfin_read_CAN0_AM28H() bfin_read16(CAN0_AM28H)
2084#define bfin_write_CAN0_AM28H(val) bfin_write16(CAN0_AM28H, val)
2085#define bfin_read_CAN0_AM29L() bfin_read16(CAN0_AM29L)
2086#define bfin_write_CAN0_AM29L(val) bfin_write16(CAN0_AM29L, val)
2087#define bfin_read_CAN0_AM29H() bfin_read16(CAN0_AM29H)
2088#define bfin_write_CAN0_AM29H(val) bfin_write16(CAN0_AM29H, val)
2089#define bfin_read_CAN0_AM30L() bfin_read16(CAN0_AM30L)
2090#define bfin_write_CAN0_AM30L(val) bfin_write16(CAN0_AM30L, val)
2091#define bfin_read_CAN0_AM30H() bfin_read16(CAN0_AM30H)
2092#define bfin_write_CAN0_AM30H(val) bfin_write16(CAN0_AM30H, val)
2093#define bfin_read_CAN0_AM31L() bfin_read16(CAN0_AM31L)
2094#define bfin_write_CAN0_AM31L(val) bfin_write16(CAN0_AM31L, val)
2095#define bfin_read_CAN0_AM31H() bfin_read16(CAN0_AM31H)
2096#define bfin_write_CAN0_AM31H(val) bfin_write16(CAN0_AM31H, val)
2097
2098/* CAN Controller 0 Mailbox Data Registers */
2099
2100#define bfin_read_CAN0_MB00_DATA0() bfin_read16(CAN0_MB00_DATA0)
2101#define bfin_write_CAN0_MB00_DATA0(val) bfin_write16(CAN0_MB00_DATA0, val)
2102#define bfin_read_CAN0_MB00_DATA1() bfin_read16(CAN0_MB00_DATA1)
2103#define bfin_write_CAN0_MB00_DATA1(val) bfin_write16(CAN0_MB00_DATA1, val)
2104#define bfin_read_CAN0_MB00_DATA2() bfin_read16(CAN0_MB00_DATA2)
2105#define bfin_write_CAN0_MB00_DATA2(val) bfin_write16(CAN0_MB00_DATA2, val)
2106#define bfin_read_CAN0_MB00_DATA3() bfin_read16(CAN0_MB00_DATA3)
2107#define bfin_write_CAN0_MB00_DATA3(val) bfin_write16(CAN0_MB00_DATA3, val)
2108#define bfin_read_CAN0_MB00_LENGTH() bfin_read16(CAN0_MB00_LENGTH)
2109#define bfin_write_CAN0_MB00_LENGTH(val) bfin_write16(CAN0_MB00_LENGTH, val)
2110#define bfin_read_CAN0_MB00_TIMESTAMP() bfin_read16(CAN0_MB00_TIMESTAMP)
2111#define bfin_write_CAN0_MB00_TIMESTAMP(val) bfin_write16(CAN0_MB00_TIMESTAMP, val)
2112#define bfin_read_CAN0_MB00_ID0() bfin_read16(CAN0_MB00_ID0)
2113#define bfin_write_CAN0_MB00_ID0(val) bfin_write16(CAN0_MB00_ID0, val)
2114#define bfin_read_CAN0_MB00_ID1() bfin_read16(CAN0_MB00_ID1)
2115#define bfin_write_CAN0_MB00_ID1(val) bfin_write16(CAN0_MB00_ID1, val)
2116#define bfin_read_CAN0_MB01_DATA0() bfin_read16(CAN0_MB01_DATA0)
2117#define bfin_write_CAN0_MB01_DATA0(val) bfin_write16(CAN0_MB01_DATA0, val)
2118#define bfin_read_CAN0_MB01_DATA1() bfin_read16(CAN0_MB01_DATA1)
2119#define bfin_write_CAN0_MB01_DATA1(val) bfin_write16(CAN0_MB01_DATA1, val)
2120#define bfin_read_CAN0_MB01_DATA2() bfin_read16(CAN0_MB01_DATA2)
2121#define bfin_write_CAN0_MB01_DATA2(val) bfin_write16(CAN0_MB01_DATA2, val)
2122#define bfin_read_CAN0_MB01_DATA3() bfin_read16(CAN0_MB01_DATA3)
2123#define bfin_write_CAN0_MB01_DATA3(val) bfin_write16(CAN0_MB01_DATA3, val)
2124#define bfin_read_CAN0_MB01_LENGTH() bfin_read16(CAN0_MB01_LENGTH)
2125#define bfin_write_CAN0_MB01_LENGTH(val) bfin_write16(CAN0_MB01_LENGTH, val)
2126#define bfin_read_CAN0_MB01_TIMESTAMP() bfin_read16(CAN0_MB01_TIMESTAMP)
2127#define bfin_write_CAN0_MB01_TIMESTAMP(val) bfin_write16(CAN0_MB01_TIMESTAMP, val)
2128#define bfin_read_CAN0_MB01_ID0() bfin_read16(CAN0_MB01_ID0)
2129#define bfin_write_CAN0_MB01_ID0(val) bfin_write16(CAN0_MB01_ID0, val)
2130#define bfin_read_CAN0_MB01_ID1() bfin_read16(CAN0_MB01_ID1)
2131#define bfin_write_CAN0_MB01_ID1(val) bfin_write16(CAN0_MB01_ID1, val)
2132#define bfin_read_CAN0_MB02_DATA0() bfin_read16(CAN0_MB02_DATA0)
2133#define bfin_write_CAN0_MB02_DATA0(val) bfin_write16(CAN0_MB02_DATA0, val)
2134#define bfin_read_CAN0_MB02_DATA1() bfin_read16(CAN0_MB02_DATA1)
2135#define bfin_write_CAN0_MB02_DATA1(val) bfin_write16(CAN0_MB02_DATA1, val)
2136#define bfin_read_CAN0_MB02_DATA2() bfin_read16(CAN0_MB02_DATA2)
2137#define bfin_write_CAN0_MB02_DATA2(val) bfin_write16(CAN0_MB02_DATA2, val)
2138#define bfin_read_CAN0_MB02_DATA3() bfin_read16(CAN0_MB02_DATA3)
2139#define bfin_write_CAN0_MB02_DATA3(val) bfin_write16(CAN0_MB02_DATA3, val)
2140#define bfin_read_CAN0_MB02_LENGTH() bfin_read16(CAN0_MB02_LENGTH)
2141#define bfin_write_CAN0_MB02_LENGTH(val) bfin_write16(CAN0_MB02_LENGTH, val)
2142#define bfin_read_CAN0_MB02_TIMESTAMP() bfin_read16(CAN0_MB02_TIMESTAMP)
2143#define bfin_write_CAN0_MB02_TIMESTAMP(val) bfin_write16(CAN0_MB02_TIMESTAMP, val)
2144#define bfin_read_CAN0_MB02_ID0() bfin_read16(CAN0_MB02_ID0)
2145#define bfin_write_CAN0_MB02_ID0(val) bfin_write16(CAN0_MB02_ID0, val)
2146#define bfin_read_CAN0_MB02_ID1() bfin_read16(CAN0_MB02_ID1)
2147#define bfin_write_CAN0_MB02_ID1(val) bfin_write16(CAN0_MB02_ID1, val)
2148#define bfin_read_CAN0_MB03_DATA0() bfin_read16(CAN0_MB03_DATA0)
2149#define bfin_write_CAN0_MB03_DATA0(val) bfin_write16(CAN0_MB03_DATA0, val)
2150#define bfin_read_CAN0_MB03_DATA1() bfin_read16(CAN0_MB03_DATA1)
2151#define bfin_write_CAN0_MB03_DATA1(val) bfin_write16(CAN0_MB03_DATA1, val)
2152#define bfin_read_CAN0_MB03_DATA2() bfin_read16(CAN0_MB03_DATA2)
2153#define bfin_write_CAN0_MB03_DATA2(val) bfin_write16(CAN0_MB03_DATA2, val)
2154#define bfin_read_CAN0_MB03_DATA3() bfin_read16(CAN0_MB03_DATA3)
2155#define bfin_write_CAN0_MB03_DATA3(val) bfin_write16(CAN0_MB03_DATA3, val)
2156#define bfin_read_CAN0_MB03_LENGTH() bfin_read16(CAN0_MB03_LENGTH)
2157#define bfin_write_CAN0_MB03_LENGTH(val) bfin_write16(CAN0_MB03_LENGTH, val)
2158#define bfin_read_CAN0_MB03_TIMESTAMP() bfin_read16(CAN0_MB03_TIMESTAMP)
2159#define bfin_write_CAN0_MB03_TIMESTAMP(val) bfin_write16(CAN0_MB03_TIMESTAMP, val)
2160#define bfin_read_CAN0_MB03_ID0() bfin_read16(CAN0_MB03_ID0)
2161#define bfin_write_CAN0_MB03_ID0(val) bfin_write16(CAN0_MB03_ID0, val)
2162#define bfin_read_CAN0_MB03_ID1() bfin_read16(CAN0_MB03_ID1)
2163#define bfin_write_CAN0_MB03_ID1(val) bfin_write16(CAN0_MB03_ID1, val)
2164#define bfin_read_CAN0_MB04_DATA0() bfin_read16(CAN0_MB04_DATA0)
2165#define bfin_write_CAN0_MB04_DATA0(val) bfin_write16(CAN0_MB04_DATA0, val)
2166#define bfin_read_CAN0_MB04_DATA1() bfin_read16(CAN0_MB04_DATA1)
2167#define bfin_write_CAN0_MB04_DATA1(val) bfin_write16(CAN0_MB04_DATA1, val)
2168#define bfin_read_CAN0_MB04_DATA2() bfin_read16(CAN0_MB04_DATA2)
2169#define bfin_write_CAN0_MB04_DATA2(val) bfin_write16(CAN0_MB04_DATA2, val)
2170#define bfin_read_CAN0_MB04_DATA3() bfin_read16(CAN0_MB04_DATA3)
2171#define bfin_write_CAN0_MB04_DATA3(val) bfin_write16(CAN0_MB04_DATA3, val)
2172#define bfin_read_CAN0_MB04_LENGTH() bfin_read16(CAN0_MB04_LENGTH)
2173#define bfin_write_CAN0_MB04_LENGTH(val) bfin_write16(CAN0_MB04_LENGTH, val)
2174#define bfin_read_CAN0_MB04_TIMESTAMP() bfin_read16(CAN0_MB04_TIMESTAMP)
2175#define bfin_write_CAN0_MB04_TIMESTAMP(val) bfin_write16(CAN0_MB04_TIMESTAMP, val)
2176#define bfin_read_CAN0_MB04_ID0() bfin_read16(CAN0_MB04_ID0)
2177#define bfin_write_CAN0_MB04_ID0(val) bfin_write16(CAN0_MB04_ID0, val)
2178#define bfin_read_CAN0_MB04_ID1() bfin_read16(CAN0_MB04_ID1)
2179#define bfin_write_CAN0_MB04_ID1(val) bfin_write16(CAN0_MB04_ID1, val)
2180#define bfin_read_CAN0_MB05_DATA0() bfin_read16(CAN0_MB05_DATA0)
2181#define bfin_write_CAN0_MB05_DATA0(val) bfin_write16(CAN0_MB05_DATA0, val)
2182#define bfin_read_CAN0_MB05_DATA1() bfin_read16(CAN0_MB05_DATA1)
2183#define bfin_write_CAN0_MB05_DATA1(val) bfin_write16(CAN0_MB05_DATA1, val)
2184#define bfin_read_CAN0_MB05_DATA2() bfin_read16(CAN0_MB05_DATA2)
2185#define bfin_write_CAN0_MB05_DATA2(val) bfin_write16(CAN0_MB05_DATA2, val)
2186#define bfin_read_CAN0_MB05_DATA3() bfin_read16(CAN0_MB05_DATA3)
2187#define bfin_write_CAN0_MB05_DATA3(val) bfin_write16(CAN0_MB05_DATA3, val)
2188#define bfin_read_CAN0_MB05_LENGTH() bfin_read16(CAN0_MB05_LENGTH)
2189#define bfin_write_CAN0_MB05_LENGTH(val) bfin_write16(CAN0_MB05_LENGTH, val)
2190#define bfin_read_CAN0_MB05_TIMESTAMP() bfin_read16(CAN0_MB05_TIMESTAMP)
2191#define bfin_write_CAN0_MB05_TIMESTAMP(val) bfin_write16(CAN0_MB05_TIMESTAMP, val)
2192#define bfin_read_CAN0_MB05_ID0() bfin_read16(CAN0_MB05_ID0)
2193#define bfin_write_CAN0_MB05_ID0(val) bfin_write16(CAN0_MB05_ID0, val)
2194#define bfin_read_CAN0_MB05_ID1() bfin_read16(CAN0_MB05_ID1)
2195#define bfin_write_CAN0_MB05_ID1(val) bfin_write16(CAN0_MB05_ID1, val)
2196#define bfin_read_CAN0_MB06_DATA0() bfin_read16(CAN0_MB06_DATA0)
2197#define bfin_write_CAN0_MB06_DATA0(val) bfin_write16(CAN0_MB06_DATA0, val)
2198#define bfin_read_CAN0_MB06_DATA1() bfin_read16(CAN0_MB06_DATA1)
2199#define bfin_write_CAN0_MB06_DATA1(val) bfin_write16(CAN0_MB06_DATA1, val)
2200#define bfin_read_CAN0_MB06_DATA2() bfin_read16(CAN0_MB06_DATA2)
2201#define bfin_write_CAN0_MB06_DATA2(val) bfin_write16(CAN0_MB06_DATA2, val)
2202#define bfin_read_CAN0_MB06_DATA3() bfin_read16(CAN0_MB06_DATA3)
2203#define bfin_write_CAN0_MB06_DATA3(val) bfin_write16(CAN0_MB06_DATA3, val)
2204#define bfin_read_CAN0_MB06_LENGTH() bfin_read16(CAN0_MB06_LENGTH)
2205#define bfin_write_CAN0_MB06_LENGTH(val) bfin_write16(CAN0_MB06_LENGTH, val)
2206#define bfin_read_CAN0_MB06_TIMESTAMP() bfin_read16(CAN0_MB06_TIMESTAMP)
2207#define bfin_write_CAN0_MB06_TIMESTAMP(val) bfin_write16(CAN0_MB06_TIMESTAMP, val)
2208#define bfin_read_CAN0_MB06_ID0() bfin_read16(CAN0_MB06_ID0)
2209#define bfin_write_CAN0_MB06_ID0(val) bfin_write16(CAN0_MB06_ID0, val)
2210#define bfin_read_CAN0_MB06_ID1() bfin_read16(CAN0_MB06_ID1)
2211#define bfin_write_CAN0_MB06_ID1(val) bfin_write16(CAN0_MB06_ID1, val)
2212#define bfin_read_CAN0_MB07_DATA0() bfin_read16(CAN0_MB07_DATA0)
2213#define bfin_write_CAN0_MB07_DATA0(val) bfin_write16(CAN0_MB07_DATA0, val)
2214#define bfin_read_CAN0_MB07_DATA1() bfin_read16(CAN0_MB07_DATA1)
2215#define bfin_write_CAN0_MB07_DATA1(val) bfin_write16(CAN0_MB07_DATA1, val)
2216#define bfin_read_CAN0_MB07_DATA2() bfin_read16(CAN0_MB07_DATA2)
2217#define bfin_write_CAN0_MB07_DATA2(val) bfin_write16(CAN0_MB07_DATA2, val)
2218#define bfin_read_CAN0_MB07_DATA3() bfin_read16(CAN0_MB07_DATA3)
2219#define bfin_write_CAN0_MB07_DATA3(val) bfin_write16(CAN0_MB07_DATA3, val)
2220#define bfin_read_CAN0_MB07_LENGTH() bfin_read16(CAN0_MB07_LENGTH)
2221#define bfin_write_CAN0_MB07_LENGTH(val) bfin_write16(CAN0_MB07_LENGTH, val)
2222#define bfin_read_CAN0_MB07_TIMESTAMP() bfin_read16(CAN0_MB07_TIMESTAMP)
2223#define bfin_write_CAN0_MB07_TIMESTAMP(val) bfin_write16(CAN0_MB07_TIMESTAMP, val)
2224#define bfin_read_CAN0_MB07_ID0() bfin_read16(CAN0_MB07_ID0)
2225#define bfin_write_CAN0_MB07_ID0(val) bfin_write16(CAN0_MB07_ID0, val)
2226#define bfin_read_CAN0_MB07_ID1() bfin_read16(CAN0_MB07_ID1)
2227#define bfin_write_CAN0_MB07_ID1(val) bfin_write16(CAN0_MB07_ID1, val)
2228#define bfin_read_CAN0_MB08_DATA0() bfin_read16(CAN0_MB08_DATA0)
2229#define bfin_write_CAN0_MB08_DATA0(val) bfin_write16(CAN0_MB08_DATA0, val)
2230#define bfin_read_CAN0_MB08_DATA1() bfin_read16(CAN0_MB08_DATA1)
2231#define bfin_write_CAN0_MB08_DATA1(val) bfin_write16(CAN0_MB08_DATA1, val)
2232#define bfin_read_CAN0_MB08_DATA2() bfin_read16(CAN0_MB08_DATA2)
2233#define bfin_write_CAN0_MB08_DATA2(val) bfin_write16(CAN0_MB08_DATA2, val)
2234#define bfin_read_CAN0_MB08_DATA3() bfin_read16(CAN0_MB08_DATA3)
2235#define bfin_write_CAN0_MB08_DATA3(val) bfin_write16(CAN0_MB08_DATA3, val)
2236#define bfin_read_CAN0_MB08_LENGTH() bfin_read16(CAN0_MB08_LENGTH)
2237#define bfin_write_CAN0_MB08_LENGTH(val) bfin_write16(CAN0_MB08_LENGTH, val)
2238#define bfin_read_CAN0_MB08_TIMESTAMP() bfin_read16(CAN0_MB08_TIMESTAMP)
2239#define bfin_write_CAN0_MB08_TIMESTAMP(val) bfin_write16(CAN0_MB08_TIMESTAMP, val)
2240#define bfin_read_CAN0_MB08_ID0() bfin_read16(CAN0_MB08_ID0)
2241#define bfin_write_CAN0_MB08_ID0(val) bfin_write16(CAN0_MB08_ID0, val)
2242#define bfin_read_CAN0_MB08_ID1() bfin_read16(CAN0_MB08_ID1)
2243#define bfin_write_CAN0_MB08_ID1(val) bfin_write16(CAN0_MB08_ID1, val)
2244#define bfin_read_CAN0_MB09_DATA0() bfin_read16(CAN0_MB09_DATA0)
2245#define bfin_write_CAN0_MB09_DATA0(val) bfin_write16(CAN0_MB09_DATA0, val)
2246#define bfin_read_CAN0_MB09_DATA1() bfin_read16(CAN0_MB09_DATA1)
2247#define bfin_write_CAN0_MB09_DATA1(val) bfin_write16(CAN0_MB09_DATA1, val)
2248#define bfin_read_CAN0_MB09_DATA2() bfin_read16(CAN0_MB09_DATA2)
2249#define bfin_write_CAN0_MB09_DATA2(val) bfin_write16(CAN0_MB09_DATA2, val)
2250#define bfin_read_CAN0_MB09_DATA3() bfin_read16(CAN0_MB09_DATA3)
2251#define bfin_write_CAN0_MB09_DATA3(val) bfin_write16(CAN0_MB09_DATA3, val)
2252#define bfin_read_CAN0_MB09_LENGTH() bfin_read16(CAN0_MB09_LENGTH)
2253#define bfin_write_CAN0_MB09_LENGTH(val) bfin_write16(CAN0_MB09_LENGTH, val)
2254#define bfin_read_CAN0_MB09_TIMESTAMP() bfin_read16(CAN0_MB09_TIMESTAMP)
2255#define bfin_write_CAN0_MB09_TIMESTAMP(val) bfin_write16(CAN0_MB09_TIMESTAMP, val)
2256#define bfin_read_CAN0_MB09_ID0() bfin_read16(CAN0_MB09_ID0)
2257#define bfin_write_CAN0_MB09_ID0(val) bfin_write16(CAN0_MB09_ID0, val)
2258#define bfin_read_CAN0_MB09_ID1() bfin_read16(CAN0_MB09_ID1)
2259#define bfin_write_CAN0_MB09_ID1(val) bfin_write16(CAN0_MB09_ID1, val)
2260#define bfin_read_CAN0_MB10_DATA0() bfin_read16(CAN0_MB10_DATA0)
2261#define bfin_write_CAN0_MB10_DATA0(val) bfin_write16(CAN0_MB10_DATA0, val)
2262#define bfin_read_CAN0_MB10_DATA1() bfin_read16(CAN0_MB10_DATA1)
2263#define bfin_write_CAN0_MB10_DATA1(val) bfin_write16(CAN0_MB10_DATA1, val)
2264#define bfin_read_CAN0_MB10_DATA2() bfin_read16(CAN0_MB10_DATA2)
2265#define bfin_write_CAN0_MB10_DATA2(val) bfin_write16(CAN0_MB10_DATA2, val)
2266#define bfin_read_CAN0_MB10_DATA3() bfin_read16(CAN0_MB10_DATA3)
2267#define bfin_write_CAN0_MB10_DATA3(val) bfin_write16(CAN0_MB10_DATA3, val)
2268#define bfin_read_CAN0_MB10_LENGTH() bfin_read16(CAN0_MB10_LENGTH)
2269#define bfin_write_CAN0_MB10_LENGTH(val) bfin_write16(CAN0_MB10_LENGTH, val)
2270#define bfin_read_CAN0_MB10_TIMESTAMP() bfin_read16(CAN0_MB10_TIMESTAMP)
2271#define bfin_write_CAN0_MB10_TIMESTAMP(val) bfin_write16(CAN0_MB10_TIMESTAMP, val)
2272#define bfin_read_CAN0_MB10_ID0() bfin_read16(CAN0_MB10_ID0)
2273#define bfin_write_CAN0_MB10_ID0(val) bfin_write16(CAN0_MB10_ID0, val)
2274#define bfin_read_CAN0_MB10_ID1() bfin_read16(CAN0_MB10_ID1)
2275#define bfin_write_CAN0_MB10_ID1(val) bfin_write16(CAN0_MB10_ID1, val)
2276#define bfin_read_CAN0_MB11_DATA0() bfin_read16(CAN0_MB11_DATA0)
2277#define bfin_write_CAN0_MB11_DATA0(val) bfin_write16(CAN0_MB11_DATA0, val)
2278#define bfin_read_CAN0_MB11_DATA1() bfin_read16(CAN0_MB11_DATA1)
2279#define bfin_write_CAN0_MB11_DATA1(val) bfin_write16(CAN0_MB11_DATA1, val)
2280#define bfin_read_CAN0_MB11_DATA2() bfin_read16(CAN0_MB11_DATA2)
2281#define bfin_write_CAN0_MB11_DATA2(val) bfin_write16(CAN0_MB11_DATA2, val)
2282#define bfin_read_CAN0_MB11_DATA3() bfin_read16(CAN0_MB11_DATA3)
2283#define bfin_write_CAN0_MB11_DATA3(val) bfin_write16(CAN0_MB11_DATA3, val)
2284#define bfin_read_CAN0_MB11_LENGTH() bfin_read16(CAN0_MB11_LENGTH)
2285#define bfin_write_CAN0_MB11_LENGTH(val) bfin_write16(CAN0_MB11_LENGTH, val)
2286#define bfin_read_CAN0_MB11_TIMESTAMP() bfin_read16(CAN0_MB11_TIMESTAMP)
2287#define bfin_write_CAN0_MB11_TIMESTAMP(val) bfin_write16(CAN0_MB11_TIMESTAMP, val)
2288#define bfin_read_CAN0_MB11_ID0() bfin_read16(CAN0_MB11_ID0)
2289#define bfin_write_CAN0_MB11_ID0(val) bfin_write16(CAN0_MB11_ID0, val)
2290#define bfin_read_CAN0_MB11_ID1() bfin_read16(CAN0_MB11_ID1)
2291#define bfin_write_CAN0_MB11_ID1(val) bfin_write16(CAN0_MB11_ID1, val)
2292#define bfin_read_CAN0_MB12_DATA0() bfin_read16(CAN0_MB12_DATA0)
2293#define bfin_write_CAN0_MB12_DATA0(val) bfin_write16(CAN0_MB12_DATA0, val)
2294#define bfin_read_CAN0_MB12_DATA1() bfin_read16(CAN0_MB12_DATA1)
2295#define bfin_write_CAN0_MB12_DATA1(val) bfin_write16(CAN0_MB12_DATA1, val)
2296#define bfin_read_CAN0_MB12_DATA2() bfin_read16(CAN0_MB12_DATA2)
2297#define bfin_write_CAN0_MB12_DATA2(val) bfin_write16(CAN0_MB12_DATA2, val)
2298#define bfin_read_CAN0_MB12_DATA3() bfin_read16(CAN0_MB12_DATA3)
2299#define bfin_write_CAN0_MB12_DATA3(val) bfin_write16(CAN0_MB12_DATA3, val)
2300#define bfin_read_CAN0_MB12_LENGTH() bfin_read16(CAN0_MB12_LENGTH)
2301#define bfin_write_CAN0_MB12_LENGTH(val) bfin_write16(CAN0_MB12_LENGTH, val)
2302#define bfin_read_CAN0_MB12_TIMESTAMP() bfin_read16(CAN0_MB12_TIMESTAMP)
2303#define bfin_write_CAN0_MB12_TIMESTAMP(val) bfin_write16(CAN0_MB12_TIMESTAMP, val)
2304#define bfin_read_CAN0_MB12_ID0() bfin_read16(CAN0_MB12_ID0)
2305#define bfin_write_CAN0_MB12_ID0(val) bfin_write16(CAN0_MB12_ID0, val)
2306#define bfin_read_CAN0_MB12_ID1() bfin_read16(CAN0_MB12_ID1)
2307#define bfin_write_CAN0_MB12_ID1(val) bfin_write16(CAN0_MB12_ID1, val)
2308#define bfin_read_CAN0_MB13_DATA0() bfin_read16(CAN0_MB13_DATA0)
2309#define bfin_write_CAN0_MB13_DATA0(val) bfin_write16(CAN0_MB13_DATA0, val)
2310#define bfin_read_CAN0_MB13_DATA1() bfin_read16(CAN0_MB13_DATA1)
2311#define bfin_write_CAN0_MB13_DATA1(val) bfin_write16(CAN0_MB13_DATA1, val)
2312#define bfin_read_CAN0_MB13_DATA2() bfin_read16(CAN0_MB13_DATA2)
2313#define bfin_write_CAN0_MB13_DATA2(val) bfin_write16(CAN0_MB13_DATA2, val)
2314#define bfin_read_CAN0_MB13_DATA3() bfin_read16(CAN0_MB13_DATA3)
2315#define bfin_write_CAN0_MB13_DATA3(val) bfin_write16(CAN0_MB13_DATA3, val)
2316#define bfin_read_CAN0_MB13_LENGTH() bfin_read16(CAN0_MB13_LENGTH)
2317#define bfin_write_CAN0_MB13_LENGTH(val) bfin_write16(CAN0_MB13_LENGTH, val)
2318#define bfin_read_CAN0_MB13_TIMESTAMP() bfin_read16(CAN0_MB13_TIMESTAMP)
2319#define bfin_write_CAN0_MB13_TIMESTAMP(val) bfin_write16(CAN0_MB13_TIMESTAMP, val)
2320#define bfin_read_CAN0_MB13_ID0() bfin_read16(CAN0_MB13_ID0)
2321#define bfin_write_CAN0_MB13_ID0(val) bfin_write16(CAN0_MB13_ID0, val)
2322#define bfin_read_CAN0_MB13_ID1() bfin_read16(CAN0_MB13_ID1)
2323#define bfin_write_CAN0_MB13_ID1(val) bfin_write16(CAN0_MB13_ID1, val)
2324#define bfin_read_CAN0_MB14_DATA0() bfin_read16(CAN0_MB14_DATA0)
2325#define bfin_write_CAN0_MB14_DATA0(val) bfin_write16(CAN0_MB14_DATA0, val)
2326#define bfin_read_CAN0_MB14_DATA1() bfin_read16(CAN0_MB14_DATA1)
2327#define bfin_write_CAN0_MB14_DATA1(val) bfin_write16(CAN0_MB14_DATA1, val)
2328#define bfin_read_CAN0_MB14_DATA2() bfin_read16(CAN0_MB14_DATA2)
2329#define bfin_write_CAN0_MB14_DATA2(val) bfin_write16(CAN0_MB14_DATA2, val)
2330#define bfin_read_CAN0_MB14_DATA3() bfin_read16(CAN0_MB14_DATA3)
2331#define bfin_write_CAN0_MB14_DATA3(val) bfin_write16(CAN0_MB14_DATA3, val)
2332#define bfin_read_CAN0_MB14_LENGTH() bfin_read16(CAN0_MB14_LENGTH)
2333#define bfin_write_CAN0_MB14_LENGTH(val) bfin_write16(CAN0_MB14_LENGTH, val)
2334#define bfin_read_CAN0_MB14_TIMESTAMP() bfin_read16(CAN0_MB14_TIMESTAMP)
2335#define bfin_write_CAN0_MB14_TIMESTAMP(val) bfin_write16(CAN0_MB14_TIMESTAMP, val)
2336#define bfin_read_CAN0_MB14_ID0() bfin_read16(CAN0_MB14_ID0)
2337#define bfin_write_CAN0_MB14_ID0(val) bfin_write16(CAN0_MB14_ID0, val)
2338#define bfin_read_CAN0_MB14_ID1() bfin_read16(CAN0_MB14_ID1)
2339#define bfin_write_CAN0_MB14_ID1(val) bfin_write16(CAN0_MB14_ID1, val)
2340#define bfin_read_CAN0_MB15_DATA0() bfin_read16(CAN0_MB15_DATA0)
2341#define bfin_write_CAN0_MB15_DATA0(val) bfin_write16(CAN0_MB15_DATA0, val)
2342#define bfin_read_CAN0_MB15_DATA1() bfin_read16(CAN0_MB15_DATA1)
2343#define bfin_write_CAN0_MB15_DATA1(val) bfin_write16(CAN0_MB15_DATA1, val)
2344#define bfin_read_CAN0_MB15_DATA2() bfin_read16(CAN0_MB15_DATA2)
2345#define bfin_write_CAN0_MB15_DATA2(val) bfin_write16(CAN0_MB15_DATA2, val)
2346#define bfin_read_CAN0_MB15_DATA3() bfin_read16(CAN0_MB15_DATA3)
2347#define bfin_write_CAN0_MB15_DATA3(val) bfin_write16(CAN0_MB15_DATA3, val)
2348#define bfin_read_CAN0_MB15_LENGTH() bfin_read16(CAN0_MB15_LENGTH)
2349#define bfin_write_CAN0_MB15_LENGTH(val) bfin_write16(CAN0_MB15_LENGTH, val)
2350#define bfin_read_CAN0_MB15_TIMESTAMP() bfin_read16(CAN0_MB15_TIMESTAMP)
2351#define bfin_write_CAN0_MB15_TIMESTAMP(val) bfin_write16(CAN0_MB15_TIMESTAMP, val)
2352#define bfin_read_CAN0_MB15_ID0() bfin_read16(CAN0_MB15_ID0)
2353#define bfin_write_CAN0_MB15_ID0(val) bfin_write16(CAN0_MB15_ID0, val)
2354#define bfin_read_CAN0_MB15_ID1() bfin_read16(CAN0_MB15_ID1)
2355#define bfin_write_CAN0_MB15_ID1(val) bfin_write16(CAN0_MB15_ID1, val)
2356
2357/* CAN Controller 0 Mailbox Data Registers */
2358
2359#define bfin_read_CAN0_MB16_DATA0() bfin_read16(CAN0_MB16_DATA0)
2360#define bfin_write_CAN0_MB16_DATA0(val) bfin_write16(CAN0_MB16_DATA0, val)
2361#define bfin_read_CAN0_MB16_DATA1() bfin_read16(CAN0_MB16_DATA1)
2362#define bfin_write_CAN0_MB16_DATA1(val) bfin_write16(CAN0_MB16_DATA1, val)
2363#define bfin_read_CAN0_MB16_DATA2() bfin_read16(CAN0_MB16_DATA2)
2364#define bfin_write_CAN0_MB16_DATA2(val) bfin_write16(CAN0_MB16_DATA2, val)
2365#define bfin_read_CAN0_MB16_DATA3() bfin_read16(CAN0_MB16_DATA3)
2366#define bfin_write_CAN0_MB16_DATA3(val) bfin_write16(CAN0_MB16_DATA3, val)
2367#define bfin_read_CAN0_MB16_LENGTH() bfin_read16(CAN0_MB16_LENGTH)
2368#define bfin_write_CAN0_MB16_LENGTH(val) bfin_write16(CAN0_MB16_LENGTH, val)
2369#define bfin_read_CAN0_MB16_TIMESTAMP() bfin_read16(CAN0_MB16_TIMESTAMP)
2370#define bfin_write_CAN0_MB16_TIMESTAMP(val) bfin_write16(CAN0_MB16_TIMESTAMP, val)
2371#define bfin_read_CAN0_MB16_ID0() bfin_read16(CAN0_MB16_ID0)
2372#define bfin_write_CAN0_MB16_ID0(val) bfin_write16(CAN0_MB16_ID0, val)
2373#define bfin_read_CAN0_MB16_ID1() bfin_read16(CAN0_MB16_ID1)
2374#define bfin_write_CAN0_MB16_ID1(val) bfin_write16(CAN0_MB16_ID1, val)
2375#define bfin_read_CAN0_MB17_DATA0() bfin_read16(CAN0_MB17_DATA0)
2376#define bfin_write_CAN0_MB17_DATA0(val) bfin_write16(CAN0_MB17_DATA0, val)
2377#define bfin_read_CAN0_MB17_DATA1() bfin_read16(CAN0_MB17_DATA1)
2378#define bfin_write_CAN0_MB17_DATA1(val) bfin_write16(CAN0_MB17_DATA1, val)
2379#define bfin_read_CAN0_MB17_DATA2() bfin_read16(CAN0_MB17_DATA2)
2380#define bfin_write_CAN0_MB17_DATA2(val) bfin_write16(CAN0_MB17_DATA2, val)
2381#define bfin_read_CAN0_MB17_DATA3() bfin_read16(CAN0_MB17_DATA3)
2382#define bfin_write_CAN0_MB17_DATA3(val) bfin_write16(CAN0_MB17_DATA3, val)
2383#define bfin_read_CAN0_MB17_LENGTH() bfin_read16(CAN0_MB17_LENGTH)
2384#define bfin_write_CAN0_MB17_LENGTH(val) bfin_write16(CAN0_MB17_LENGTH, val)
2385#define bfin_read_CAN0_MB17_TIMESTAMP() bfin_read16(CAN0_MB17_TIMESTAMP)
2386#define bfin_write_CAN0_MB17_TIMESTAMP(val) bfin_write16(CAN0_MB17_TIMESTAMP, val)
2387#define bfin_read_CAN0_MB17_ID0() bfin_read16(CAN0_MB17_ID0)
2388#define bfin_write_CAN0_MB17_ID0(val) bfin_write16(CAN0_MB17_ID0, val)
2389#define bfin_read_CAN0_MB17_ID1() bfin_read16(CAN0_MB17_ID1)
2390#define bfin_write_CAN0_MB17_ID1(val) bfin_write16(CAN0_MB17_ID1, val)
2391#define bfin_read_CAN0_MB18_DATA0() bfin_read16(CAN0_MB18_DATA0)
2392#define bfin_write_CAN0_MB18_DATA0(val) bfin_write16(CAN0_MB18_DATA0, val)
2393#define bfin_read_CAN0_MB18_DATA1() bfin_read16(CAN0_MB18_DATA1)
2394#define bfin_write_CAN0_MB18_DATA1(val) bfin_write16(CAN0_MB18_DATA1, val)
2395#define bfin_read_CAN0_MB18_DATA2() bfin_read16(CAN0_MB18_DATA2)
2396#define bfin_write_CAN0_MB18_DATA2(val) bfin_write16(CAN0_MB18_DATA2, val)
2397#define bfin_read_CAN0_MB18_DATA3() bfin_read16(CAN0_MB18_DATA3)
2398#define bfin_write_CAN0_MB18_DATA3(val) bfin_write16(CAN0_MB18_DATA3, val)
2399#define bfin_read_CAN0_MB18_LENGTH() bfin_read16(CAN0_MB18_LENGTH)
2400#define bfin_write_CAN0_MB18_LENGTH(val) bfin_write16(CAN0_MB18_LENGTH, val)
2401#define bfin_read_CAN0_MB18_TIMESTAMP() bfin_read16(CAN0_MB18_TIMESTAMP)
2402#define bfin_write_CAN0_MB18_TIMESTAMP(val) bfin_write16(CAN0_MB18_TIMESTAMP, val)
2403#define bfin_read_CAN0_MB18_ID0() bfin_read16(CAN0_MB18_ID0)
2404#define bfin_write_CAN0_MB18_ID0(val) bfin_write16(CAN0_MB18_ID0, val)
2405#define bfin_read_CAN0_MB18_ID1() bfin_read16(CAN0_MB18_ID1)
2406#define bfin_write_CAN0_MB18_ID1(val) bfin_write16(CAN0_MB18_ID1, val)
2407#define bfin_read_CAN0_MB19_DATA0() bfin_read16(CAN0_MB19_DATA0)
2408#define bfin_write_CAN0_MB19_DATA0(val) bfin_write16(CAN0_MB19_DATA0, val)
2409#define bfin_read_CAN0_MB19_DATA1() bfin_read16(CAN0_MB19_DATA1)
2410#define bfin_write_CAN0_MB19_DATA1(val) bfin_write16(CAN0_MB19_DATA1, val)
2411#define bfin_read_CAN0_MB19_DATA2() bfin_read16(CAN0_MB19_DATA2)
2412#define bfin_write_CAN0_MB19_DATA2(val) bfin_write16(CAN0_MB19_DATA2, val)
2413#define bfin_read_CAN0_MB19_DATA3() bfin_read16(CAN0_MB19_DATA3)
2414#define bfin_write_CAN0_MB19_DATA3(val) bfin_write16(CAN0_MB19_DATA3, val)
2415#define bfin_read_CAN0_MB19_LENGTH() bfin_read16(CAN0_MB19_LENGTH)
2416#define bfin_write_CAN0_MB19_LENGTH(val) bfin_write16(CAN0_MB19_LENGTH, val)
2417#define bfin_read_CAN0_MB19_TIMESTAMP() bfin_read16(CAN0_MB19_TIMESTAMP)
2418#define bfin_write_CAN0_MB19_TIMESTAMP(val) bfin_write16(CAN0_MB19_TIMESTAMP, val)
2419#define bfin_read_CAN0_MB19_ID0() bfin_read16(CAN0_MB19_ID0)
2420#define bfin_write_CAN0_MB19_ID0(val) bfin_write16(CAN0_MB19_ID0, val)
2421#define bfin_read_CAN0_MB19_ID1() bfin_read16(CAN0_MB19_ID1)
2422#define bfin_write_CAN0_MB19_ID1(val) bfin_write16(CAN0_MB19_ID1, val)
2423#define bfin_read_CAN0_MB20_DATA0() bfin_read16(CAN0_MB20_DATA0)
2424#define bfin_write_CAN0_MB20_DATA0(val) bfin_write16(CAN0_MB20_DATA0, val)
2425#define bfin_read_CAN0_MB20_DATA1() bfin_read16(CAN0_MB20_DATA1)
2426#define bfin_write_CAN0_MB20_DATA1(val) bfin_write16(CAN0_MB20_DATA1, val)
2427#define bfin_read_CAN0_MB20_DATA2() bfin_read16(CAN0_MB20_DATA2)
2428#define bfin_write_CAN0_MB20_DATA2(val) bfin_write16(CAN0_MB20_DATA2, val)
2429#define bfin_read_CAN0_MB20_DATA3() bfin_read16(CAN0_MB20_DATA3)
2430#define bfin_write_CAN0_MB20_DATA3(val) bfin_write16(CAN0_MB20_DATA3, val)
2431#define bfin_read_CAN0_MB20_LENGTH() bfin_read16(CAN0_MB20_LENGTH)
2432#define bfin_write_CAN0_MB20_LENGTH(val) bfin_write16(CAN0_MB20_LENGTH, val)
2433#define bfin_read_CAN0_MB20_TIMESTAMP() bfin_read16(CAN0_MB20_TIMESTAMP)
2434#define bfin_write_CAN0_MB20_TIMESTAMP(val) bfin_write16(CAN0_MB20_TIMESTAMP, val)
2435#define bfin_read_CAN0_MB20_ID0() bfin_read16(CAN0_MB20_ID0)
2436#define bfin_write_CAN0_MB20_ID0(val) bfin_write16(CAN0_MB20_ID0, val)
2437#define bfin_read_CAN0_MB20_ID1() bfin_read16(CAN0_MB20_ID1)
2438#define bfin_write_CAN0_MB20_ID1(val) bfin_write16(CAN0_MB20_ID1, val)
2439#define bfin_read_CAN0_MB21_DATA0() bfin_read16(CAN0_MB21_DATA0)
2440#define bfin_write_CAN0_MB21_DATA0(val) bfin_write16(CAN0_MB21_DATA0, val)
2441#define bfin_read_CAN0_MB21_DATA1() bfin_read16(CAN0_MB21_DATA1)
2442#define bfin_write_CAN0_MB21_DATA1(val) bfin_write16(CAN0_MB21_DATA1, val)
2443#define bfin_read_CAN0_MB21_DATA2() bfin_read16(CAN0_MB21_DATA2)
2444#define bfin_write_CAN0_MB21_DATA2(val) bfin_write16(CAN0_MB21_DATA2, val)
2445#define bfin_read_CAN0_MB21_DATA3() bfin_read16(CAN0_MB21_DATA3)
2446#define bfin_write_CAN0_MB21_DATA3(val) bfin_write16(CAN0_MB21_DATA3, val)
2447#define bfin_read_CAN0_MB21_LENGTH() bfin_read16(CAN0_MB21_LENGTH)
2448#define bfin_write_CAN0_MB21_LENGTH(val) bfin_write16(CAN0_MB21_LENGTH, val)
2449#define bfin_read_CAN0_MB21_TIMESTAMP() bfin_read16(CAN0_MB21_TIMESTAMP)
2450#define bfin_write_CAN0_MB21_TIMESTAMP(val) bfin_write16(CAN0_MB21_TIMESTAMP, val)
2451#define bfin_read_CAN0_MB21_ID0() bfin_read16(CAN0_MB21_ID0)
2452#define bfin_write_CAN0_MB21_ID0(val) bfin_write16(CAN0_MB21_ID0, val)
2453#define bfin_read_CAN0_MB21_ID1() bfin_read16(CAN0_MB21_ID1)
2454#define bfin_write_CAN0_MB21_ID1(val) bfin_write16(CAN0_MB21_ID1, val)
2455#define bfin_read_CAN0_MB22_DATA0() bfin_read16(CAN0_MB22_DATA0)
2456#define bfin_write_CAN0_MB22_DATA0(val) bfin_write16(CAN0_MB22_DATA0, val)
2457#define bfin_read_CAN0_MB22_DATA1() bfin_read16(CAN0_MB22_DATA1)
2458#define bfin_write_CAN0_MB22_DATA1(val) bfin_write16(CAN0_MB22_DATA1, val)
2459#define bfin_read_CAN0_MB22_DATA2() bfin_read16(CAN0_MB22_DATA2)
2460#define bfin_write_CAN0_MB22_DATA2(val) bfin_write16(CAN0_MB22_DATA2, val)
2461#define bfin_read_CAN0_MB22_DATA3() bfin_read16(CAN0_MB22_DATA3)
2462#define bfin_write_CAN0_MB22_DATA3(val) bfin_write16(CAN0_MB22_DATA3, val)
2463#define bfin_read_CAN0_MB22_LENGTH() bfin_read16(CAN0_MB22_LENGTH)
2464#define bfin_write_CAN0_MB22_LENGTH(val) bfin_write16(CAN0_MB22_LENGTH, val)
2465#define bfin_read_CAN0_MB22_TIMESTAMP() bfin_read16(CAN0_MB22_TIMESTAMP)
2466#define bfin_write_CAN0_MB22_TIMESTAMP(val) bfin_write16(CAN0_MB22_TIMESTAMP, val)
2467#define bfin_read_CAN0_MB22_ID0() bfin_read16(CAN0_MB22_ID0)
2468#define bfin_write_CAN0_MB22_ID0(val) bfin_write16(CAN0_MB22_ID0, val)
2469#define bfin_read_CAN0_MB22_ID1() bfin_read16(CAN0_MB22_ID1)
2470#define bfin_write_CAN0_MB22_ID1(val) bfin_write16(CAN0_MB22_ID1, val)
2471#define bfin_read_CAN0_MB23_DATA0() bfin_read16(CAN0_MB23_DATA0)
2472#define bfin_write_CAN0_MB23_DATA0(val) bfin_write16(CAN0_MB23_DATA0, val)
2473#define bfin_read_CAN0_MB23_DATA1() bfin_read16(CAN0_MB23_DATA1)
2474#define bfin_write_CAN0_MB23_DATA1(val) bfin_write16(CAN0_MB23_DATA1, val)
2475#define bfin_read_CAN0_MB23_DATA2() bfin_read16(CAN0_MB23_DATA2)
2476#define bfin_write_CAN0_MB23_DATA2(val) bfin_write16(CAN0_MB23_DATA2, val)
2477#define bfin_read_CAN0_MB23_DATA3() bfin_read16(CAN0_MB23_DATA3)
2478#define bfin_write_CAN0_MB23_DATA3(val) bfin_write16(CAN0_MB23_DATA3, val)
2479#define bfin_read_CAN0_MB23_LENGTH() bfin_read16(CAN0_MB23_LENGTH)
2480#define bfin_write_CAN0_MB23_LENGTH(val) bfin_write16(CAN0_MB23_LENGTH, val)
2481#define bfin_read_CAN0_MB23_TIMESTAMP() bfin_read16(CAN0_MB23_TIMESTAMP)
2482#define bfin_write_CAN0_MB23_TIMESTAMP(val) bfin_write16(CAN0_MB23_TIMESTAMP, val)
2483#define bfin_read_CAN0_MB23_ID0() bfin_read16(CAN0_MB23_ID0)
2484#define bfin_write_CAN0_MB23_ID0(val) bfin_write16(CAN0_MB23_ID0, val)
2485#define bfin_read_CAN0_MB23_ID1() bfin_read16(CAN0_MB23_ID1)
2486#define bfin_write_CAN0_MB23_ID1(val) bfin_write16(CAN0_MB23_ID1, val)
2487#define bfin_read_CAN0_MB24_DATA0() bfin_read16(CAN0_MB24_DATA0)
2488#define bfin_write_CAN0_MB24_DATA0(val) bfin_write16(CAN0_MB24_DATA0, val)
2489#define bfin_read_CAN0_MB24_DATA1() bfin_read16(CAN0_MB24_DATA1)
2490#define bfin_write_CAN0_MB24_DATA1(val) bfin_write16(CAN0_MB24_DATA1, val)
2491#define bfin_read_CAN0_MB24_DATA2() bfin_read16(CAN0_MB24_DATA2)
2492#define bfin_write_CAN0_MB24_DATA2(val) bfin_write16(CAN0_MB24_DATA2, val)
2493#define bfin_read_CAN0_MB24_DATA3() bfin_read16(CAN0_MB24_DATA3)
2494#define bfin_write_CAN0_MB24_DATA3(val) bfin_write16(CAN0_MB24_DATA3, val)
2495#define bfin_read_CAN0_MB24_LENGTH() bfin_read16(CAN0_MB24_LENGTH)
2496#define bfin_write_CAN0_MB24_LENGTH(val) bfin_write16(CAN0_MB24_LENGTH, val)
2497#define bfin_read_CAN0_MB24_TIMESTAMP() bfin_read16(CAN0_MB24_TIMESTAMP)
2498#define bfin_write_CAN0_MB24_TIMESTAMP(val) bfin_write16(CAN0_MB24_TIMESTAMP, val)
2499#define bfin_read_CAN0_MB24_ID0() bfin_read16(CAN0_MB24_ID0)
2500#define bfin_write_CAN0_MB24_ID0(val) bfin_write16(CAN0_MB24_ID0, val)
2501#define bfin_read_CAN0_MB24_ID1() bfin_read16(CAN0_MB24_ID1)
2502#define bfin_write_CAN0_MB24_ID1(val) bfin_write16(CAN0_MB24_ID1, val)
2503#define bfin_read_CAN0_MB25_DATA0() bfin_read16(CAN0_MB25_DATA0)
2504#define bfin_write_CAN0_MB25_DATA0(val) bfin_write16(CAN0_MB25_DATA0, val)
2505#define bfin_read_CAN0_MB25_DATA1() bfin_read16(CAN0_MB25_DATA1)
2506#define bfin_write_CAN0_MB25_DATA1(val) bfin_write16(CAN0_MB25_DATA1, val)
2507#define bfin_read_CAN0_MB25_DATA2() bfin_read16(CAN0_MB25_DATA2)
2508#define bfin_write_CAN0_MB25_DATA2(val) bfin_write16(CAN0_MB25_DATA2, val)
2509#define bfin_read_CAN0_MB25_DATA3() bfin_read16(CAN0_MB25_DATA3)
2510#define bfin_write_CAN0_MB25_DATA3(val) bfin_write16(CAN0_MB25_DATA3, val)
2511#define bfin_read_CAN0_MB25_LENGTH() bfin_read16(CAN0_MB25_LENGTH)
2512#define bfin_write_CAN0_MB25_LENGTH(val) bfin_write16(CAN0_MB25_LENGTH, val)
2513#define bfin_read_CAN0_MB25_TIMESTAMP() bfin_read16(CAN0_MB25_TIMESTAMP)
2514#define bfin_write_CAN0_MB25_TIMESTAMP(val) bfin_write16(CAN0_MB25_TIMESTAMP, val)
2515#define bfin_read_CAN0_MB25_ID0() bfin_read16(CAN0_MB25_ID0)
2516#define bfin_write_CAN0_MB25_ID0(val) bfin_write16(CAN0_MB25_ID0, val)
2517#define bfin_read_CAN0_MB25_ID1() bfin_read16(CAN0_MB25_ID1)
2518#define bfin_write_CAN0_MB25_ID1(val) bfin_write16(CAN0_MB25_ID1, val)
2519#define bfin_read_CAN0_MB26_DATA0() bfin_read16(CAN0_MB26_DATA0)
2520#define bfin_write_CAN0_MB26_DATA0(val) bfin_write16(CAN0_MB26_DATA0, val)
2521#define bfin_read_CAN0_MB26_DATA1() bfin_read16(CAN0_MB26_DATA1)
2522#define bfin_write_CAN0_MB26_DATA1(val) bfin_write16(CAN0_MB26_DATA1, val)
2523#define bfin_read_CAN0_MB26_DATA2() bfin_read16(CAN0_MB26_DATA2)
2524#define bfin_write_CAN0_MB26_DATA2(val) bfin_write16(CAN0_MB26_DATA2, val)
2525#define bfin_read_CAN0_MB26_DATA3() bfin_read16(CAN0_MB26_DATA3)
2526#define bfin_write_CAN0_MB26_DATA3(val) bfin_write16(CAN0_MB26_DATA3, val)
2527#define bfin_read_CAN0_MB26_LENGTH() bfin_read16(CAN0_MB26_LENGTH)
2528#define bfin_write_CAN0_MB26_LENGTH(val) bfin_write16(CAN0_MB26_LENGTH, val)
2529#define bfin_read_CAN0_MB26_TIMESTAMP() bfin_read16(CAN0_MB26_TIMESTAMP)
2530#define bfin_write_CAN0_MB26_TIMESTAMP(val) bfin_write16(CAN0_MB26_TIMESTAMP, val)
2531#define bfin_read_CAN0_MB26_ID0() bfin_read16(CAN0_MB26_ID0)
2532#define bfin_write_CAN0_MB26_ID0(val) bfin_write16(CAN0_MB26_ID0, val)
2533#define bfin_read_CAN0_MB26_ID1() bfin_read16(CAN0_MB26_ID1)
2534#define bfin_write_CAN0_MB26_ID1(val) bfin_write16(CAN0_MB26_ID1, val)
2535#define bfin_read_CAN0_MB27_DATA0() bfin_read16(CAN0_MB27_DATA0)
2536#define bfin_write_CAN0_MB27_DATA0(val) bfin_write16(CAN0_MB27_DATA0, val)
2537#define bfin_read_CAN0_MB27_DATA1() bfin_read16(CAN0_MB27_DATA1)
2538#define bfin_write_CAN0_MB27_DATA1(val) bfin_write16(CAN0_MB27_DATA1, val)
2539#define bfin_read_CAN0_MB27_DATA2() bfin_read16(CAN0_MB27_DATA2)
2540#define bfin_write_CAN0_MB27_DATA2(val) bfin_write16(CAN0_MB27_DATA2, val)
2541#define bfin_read_CAN0_MB27_DATA3() bfin_read16(CAN0_MB27_DATA3)
2542#define bfin_write_CAN0_MB27_DATA3(val) bfin_write16(CAN0_MB27_DATA3, val)
2543#define bfin_read_CAN0_MB27_LENGTH() bfin_read16(CAN0_MB27_LENGTH)
2544#define bfin_write_CAN0_MB27_LENGTH(val) bfin_write16(CAN0_MB27_LENGTH, val)
2545#define bfin_read_CAN0_MB27_TIMESTAMP() bfin_read16(CAN0_MB27_TIMESTAMP)
2546#define bfin_write_CAN0_MB27_TIMESTAMP(val) bfin_write16(CAN0_MB27_TIMESTAMP, val)
2547#define bfin_read_CAN0_MB27_ID0() bfin_read16(CAN0_MB27_ID0)
2548#define bfin_write_CAN0_MB27_ID0(val) bfin_write16(CAN0_MB27_ID0, val)
2549#define bfin_read_CAN0_MB27_ID1() bfin_read16(CAN0_MB27_ID1)
2550#define bfin_write_CAN0_MB27_ID1(val) bfin_write16(CAN0_MB27_ID1, val)
2551#define bfin_read_CAN0_MB28_DATA0() bfin_read16(CAN0_MB28_DATA0)
2552#define bfin_write_CAN0_MB28_DATA0(val) bfin_write16(CAN0_MB28_DATA0, val)
2553#define bfin_read_CAN0_MB28_DATA1() bfin_read16(CAN0_MB28_DATA1)
2554#define bfin_write_CAN0_MB28_DATA1(val) bfin_write16(CAN0_MB28_DATA1, val)
2555#define bfin_read_CAN0_MB28_DATA2() bfin_read16(CAN0_MB28_DATA2)
2556#define bfin_write_CAN0_MB28_DATA2(val) bfin_write16(CAN0_MB28_DATA2, val)
2557#define bfin_read_CAN0_MB28_DATA3() bfin_read16(CAN0_MB28_DATA3)
2558#define bfin_write_CAN0_MB28_DATA3(val) bfin_write16(CAN0_MB28_DATA3, val)
2559#define bfin_read_CAN0_MB28_LENGTH() bfin_read16(CAN0_MB28_LENGTH)
2560#define bfin_write_CAN0_MB28_LENGTH(val) bfin_write16(CAN0_MB28_LENGTH, val)
2561#define bfin_read_CAN0_MB28_TIMESTAMP() bfin_read16(CAN0_MB28_TIMESTAMP)
2562#define bfin_write_CAN0_MB28_TIMESTAMP(val) bfin_write16(CAN0_MB28_TIMESTAMP, val)
2563#define bfin_read_CAN0_MB28_ID0() bfin_read16(CAN0_MB28_ID0)
2564#define bfin_write_CAN0_MB28_ID0(val) bfin_write16(CAN0_MB28_ID0, val)
2565#define bfin_read_CAN0_MB28_ID1() bfin_read16(CAN0_MB28_ID1)
2566#define bfin_write_CAN0_MB28_ID1(val) bfin_write16(CAN0_MB28_ID1, val)
2567#define bfin_read_CAN0_MB29_DATA0() bfin_read16(CAN0_MB29_DATA0)
2568#define bfin_write_CAN0_MB29_DATA0(val) bfin_write16(CAN0_MB29_DATA0, val)
2569#define bfin_read_CAN0_MB29_DATA1() bfin_read16(CAN0_MB29_DATA1)
2570#define bfin_write_CAN0_MB29_DATA1(val) bfin_write16(CAN0_MB29_DATA1, val)
2571#define bfin_read_CAN0_MB29_DATA2() bfin_read16(CAN0_MB29_DATA2)
2572#define bfin_write_CAN0_MB29_DATA2(val) bfin_write16(CAN0_MB29_DATA2, val)
2573#define bfin_read_CAN0_MB29_DATA3() bfin_read16(CAN0_MB29_DATA3)
2574#define bfin_write_CAN0_MB29_DATA3(val) bfin_write16(CAN0_MB29_DATA3, val)
2575#define bfin_read_CAN0_MB29_LENGTH() bfin_read16(CAN0_MB29_LENGTH)
2576#define bfin_write_CAN0_MB29_LENGTH(val) bfin_write16(CAN0_MB29_LENGTH, val)
2577#define bfin_read_CAN0_MB29_TIMESTAMP() bfin_read16(CAN0_MB29_TIMESTAMP)
2578#define bfin_write_CAN0_MB29_TIMESTAMP(val) bfin_write16(CAN0_MB29_TIMESTAMP, val)
2579#define bfin_read_CAN0_MB29_ID0() bfin_read16(CAN0_MB29_ID0)
2580#define bfin_write_CAN0_MB29_ID0(val) bfin_write16(CAN0_MB29_ID0, val)
2581#define bfin_read_CAN0_MB29_ID1() bfin_read16(CAN0_MB29_ID1)
2582#define bfin_write_CAN0_MB29_ID1(val) bfin_write16(CAN0_MB29_ID1, val)
2583#define bfin_read_CAN0_MB30_DATA0() bfin_read16(CAN0_MB30_DATA0)
2584#define bfin_write_CAN0_MB30_DATA0(val) bfin_write16(CAN0_MB30_DATA0, val)
2585#define bfin_read_CAN0_MB30_DATA1() bfin_read16(CAN0_MB30_DATA1)
2586#define bfin_write_CAN0_MB30_DATA1(val) bfin_write16(CAN0_MB30_DATA1, val)
2587#define bfin_read_CAN0_MB30_DATA2() bfin_read16(CAN0_MB30_DATA2)
2588#define bfin_write_CAN0_MB30_DATA2(val) bfin_write16(CAN0_MB30_DATA2, val)
2589#define bfin_read_CAN0_MB30_DATA3() bfin_read16(CAN0_MB30_DATA3)
2590#define bfin_write_CAN0_MB30_DATA3(val) bfin_write16(CAN0_MB30_DATA3, val)
2591#define bfin_read_CAN0_MB30_LENGTH() bfin_read16(CAN0_MB30_LENGTH)
2592#define bfin_write_CAN0_MB30_LENGTH(val) bfin_write16(CAN0_MB30_LENGTH, val)
2593#define bfin_read_CAN0_MB30_TIMESTAMP() bfin_read16(CAN0_MB30_TIMESTAMP)
2594#define bfin_write_CAN0_MB30_TIMESTAMP(val) bfin_write16(CAN0_MB30_TIMESTAMP, val)
2595#define bfin_read_CAN0_MB30_ID0() bfin_read16(CAN0_MB30_ID0)
2596#define bfin_write_CAN0_MB30_ID0(val) bfin_write16(CAN0_MB30_ID0, val)
2597#define bfin_read_CAN0_MB30_ID1() bfin_read16(CAN0_MB30_ID1)
2598#define bfin_write_CAN0_MB30_ID1(val) bfin_write16(CAN0_MB30_ID1, val)
2599#define bfin_read_CAN0_MB31_DATA0() bfin_read16(CAN0_MB31_DATA0)
2600#define bfin_write_CAN0_MB31_DATA0(val) bfin_write16(CAN0_MB31_DATA0, val)
2601#define bfin_read_CAN0_MB31_DATA1() bfin_read16(CAN0_MB31_DATA1)
2602#define bfin_write_CAN0_MB31_DATA1(val) bfin_write16(CAN0_MB31_DATA1, val)
2603#define bfin_read_CAN0_MB31_DATA2() bfin_read16(CAN0_MB31_DATA2)
2604#define bfin_write_CAN0_MB31_DATA2(val) bfin_write16(CAN0_MB31_DATA2, val)
2605#define bfin_read_CAN0_MB31_DATA3() bfin_read16(CAN0_MB31_DATA3)
2606#define bfin_write_CAN0_MB31_DATA3(val) bfin_write16(CAN0_MB31_DATA3, val)
2607#define bfin_read_CAN0_MB31_LENGTH() bfin_read16(CAN0_MB31_LENGTH)
2608#define bfin_write_CAN0_MB31_LENGTH(val) bfin_write16(CAN0_MB31_LENGTH, val)
2609#define bfin_read_CAN0_MB31_TIMESTAMP() bfin_read16(CAN0_MB31_TIMESTAMP)
2610#define bfin_write_CAN0_MB31_TIMESTAMP(val) bfin_write16(CAN0_MB31_TIMESTAMP, val)
2611#define bfin_read_CAN0_MB31_ID0() bfin_read16(CAN0_MB31_ID0)
2612#define bfin_write_CAN0_MB31_ID0(val) bfin_write16(CAN0_MB31_ID0, val)
2613#define bfin_read_CAN0_MB31_ID1() bfin_read16(CAN0_MB31_ID1)
2614#define bfin_write_CAN0_MB31_ID1(val) bfin_write16(CAN0_MB31_ID1, val)
2615
2616/* UART3 Registers */
2617
2618#define bfin_read_UART3_DLL() bfin_read16(UART3_DLL)
2619#define bfin_write_UART3_DLL(val) bfin_write16(UART3_DLL, val)
2620#define bfin_read_UART3_DLH() bfin_read16(UART3_DLH)
2621#define bfin_write_UART3_DLH(val) bfin_write16(UART3_DLH, val)
2622#define bfin_read_UART3_GCTL() bfin_read16(UART3_GCTL)
2623#define bfin_write_UART3_GCTL(val) bfin_write16(UART3_GCTL, val)
2624#define bfin_read_UART3_LCR() bfin_read16(UART3_LCR)
2625#define bfin_write_UART3_LCR(val) bfin_write16(UART3_LCR, val)
2626#define bfin_read_UART3_MCR() bfin_read16(UART3_MCR)
2627#define bfin_write_UART3_MCR(val) bfin_write16(UART3_MCR, val)
2628#define bfin_read_UART3_LSR() bfin_read16(UART3_LSR)
2629#define bfin_write_UART3_LSR(val) bfin_write16(UART3_LSR, val)
2630#define bfin_read_UART3_MSR() bfin_read16(UART3_MSR)
2631#define bfin_write_UART3_MSR(val) bfin_write16(UART3_MSR, val)
2632#define bfin_read_UART3_SCR() bfin_read16(UART3_SCR)
2633#define bfin_write_UART3_SCR(val) bfin_write16(UART3_SCR, val)
2634#define bfin_read_UART3_IER_SET() bfin_read16(UART3_IER_SET)
2635#define bfin_write_UART3_IER_SET(val) bfin_write16(UART3_IER_SET, val)
2636#define bfin_read_UART3_IER_CLEAR() bfin_read16(UART3_IER_CLEAR)
2637#define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val)
2638#define bfin_read_UART3_THR() bfin_read16(UART3_THR)
2639#define bfin_write_UART3_THR(val) bfin_write16(UART3_THR, val)
2640#define bfin_read_UART3_RBR() bfin_read16(UART3_RBR)
2641#define bfin_write_UART3_RBR(val) bfin_write16(UART3_RBR, val)
2642
2643/* NFC Registers */
2644
2645#define bfin_read_NFC_CTL() bfin_read16(NFC_CTL)
2646#define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val)
2647#define bfin_read_NFC_STAT() bfin_read16(NFC_STAT)
2648#define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val)
2649#define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT)
2650#define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val)
2651#define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK)
2652#define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val)
2653#define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0)
2654#define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val)
2655#define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1)
2656#define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val)
2657#define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2)
2658#define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val)
2659#define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3)
2660#define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val)
2661#define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT)
2662#define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val)
2663#define bfin_read_NFC_RST() bfin_read16(NFC_RST)
2664#define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val)
2665#define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL)
2666#define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val)
2667#define bfin_read_NFC_READ() bfin_read16(NFC_READ)
2668#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val)
2669#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR)
2670#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val)
2671#define bfin_read_NFC_CMD() bfin_read16(NFC_CMD)
2672#define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val)
2673#define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR)
2674#define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val)
2675#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD)
2676#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val)
2677
2678/* Counter Registers */
2679
2680#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG)
2681#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val)
2682#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK)
2683#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val)
2684#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS)
2685#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val)
2686#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND)
2687#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val)
2688#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE)
2689#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val)
2690#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER)
2691#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val)
2692#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX)
2693#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val)
2694#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
2695#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
2696
2697/* OTP/FUSE Registers */
2698
2699#define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL)
2700#define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val)
2701#define bfin_read_OTP_BEN() bfin_read16(OTP_BEN)
2702#define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val)
2703#define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS)
2704#define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val)
2705#define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING)
2706#define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val)
2707
2708/* Security Registers */
2709
2710#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT)
2711#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val)
2712#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL)
2713#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
2714#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS)
2715#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val)
2716
2717/* DMA Peribfin_read_()heral Mux Register */
2718
2719#define bfin_read_DMAC1_PERIMUX() bfin_read16(DMAC1_PERIMUX)
2720#define bfin_write_DMAC1_PERIMUX(val) bfin_write16(DMAC1_PERIMUX, val)
2721
2722/* OTP Read/Write Data Buffer Registers */
2723
2724#define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0)
2725#define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val)
2726#define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1)
2727#define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val)
2728#define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2)
2729#define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val)
2730#define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3)
2731#define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val)
2732
2733/* Handshake MDMA is not defined in the shared file because it is not available on the ADSP-BF542 bfin_read_()rocessor */
2734
2735/* legacy definitions */
2736#define bfin_read_EBIU_AMCBCTL0 bfin_read_EBIU_AMBCTL0
2737#define bfin_write_EBIU_AMCBCTL0 bfin_write_EBIU_AMBCTL0
2738#define bfin_read_EBIU_AMCBCTL1 bfin_read_EBIU_AMBCTL1
2739#define bfin_write_EBIU_AMCBCTL1 bfin_write_EBIU_AMBCTL1
2740#define bfin_read_PINT0_IRQ bfin_read_PINT0_REQUEST
2741#define bfin_write_PINT0_IRQ bfin_write_PINT0_REQUEST
2742#define bfin_read_PINT1_IRQ bfin_read_PINT1_REQUEST
2743#define bfin_write_PINT1_IRQ bfin_write_PINT1_REQUEST
2744#define bfin_read_PINT2_IRQ bfin_read_PINT2_REQUEST
2745#define bfin_write_PINT2_IRQ bfin_write_PINT2_REQUEST
2746#define bfin_read_PINT3_IRQ bfin_read_PINT3_REQUEST
2747#define bfin_write_PINT3_IRQ bfin_write_PINT3_REQUEST
2748
2749#endif /* _CDEF_BF54X_H */
2750
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF542.h b/arch/blackfin/mach-bf548/include/mach/defBF542.h
new file mode 100644
index 000000000000..b1316541b8d6
--- /dev/null
+++ b/arch/blackfin/mach-bf548/include/mach/defBF542.h
@@ -0,0 +1,925 @@
1/*
2 * File: include/asm-blackfin/mach-bf548/defBF542.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _DEF_BF542_H
32#define _DEF_BF542_H
33
34/* Include all Core registers and bit definitions */
35#include <asm/def_LPBlackfin.h>
36
37/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF542 */
38
39/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
40#include "defBF54x_base.h"
41
42/* The following are the #defines needed by ADSP-BF542 that are not in the common header */
43
44/* ATAPI Registers */
45
46#define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */
47#define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */
48#define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */
49#define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */
50#define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */
51#define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */
52#define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */
53#define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */
54#define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */
55#define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */
56#define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */
57#define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */
58#define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */
59#define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */
60#define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */
61#define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */
62#define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */
63#define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */
64#define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */
65#define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */
66#define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */
67#define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */
68#define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */
69#define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */
70#define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */
71
72/* SDH Registers */
73
74#define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */
75#define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */
76#define SDH_ARGUMENT 0xffc03908 /* SDH Argument */
77#define SDH_COMMAND 0xffc0390c /* SDH Command */
78#define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */
79#define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */
80#define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */
81#define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */
82#define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */
83#define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */
84#define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */
85#define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */
86#define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */
87#define SDH_STATUS 0xffc03934 /* SDH Status */
88#define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */
89#define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */
90#define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */
91#define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */
92#define SDH_FIFO 0xffc03980 /* SDH Data FIFO */
93#define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */
94#define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */
95#define SDH_CFG 0xffc039c8 /* SDH Configuration */
96#define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */
97#define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */
98#define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */
99#define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */
100#define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */
101#define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */
102#define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */
103#define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */
104#define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */
105
106/* USB Control Registers */
107
108#define USB_FADDR 0xffc03c00 /* Function address register */
109#define USB_POWER 0xffc03c04 /* Power management register */
110#define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
111#define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */
112#define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */
113#define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */
114#define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */
115#define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */
116#define USB_FRAME 0xffc03c20 /* USB frame number */
117#define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */
118#define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */
119#define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
120#define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */
121
122/* USB Packet Control Registers */
123
124#define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */
125#define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
126#define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
127#define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */
128#define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */
129#define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
130#define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
131#define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
132#define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
133#define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
134#define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
135#define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
136#define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
137
138/* USB Endpoint FIFO Registers */
139
140#define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */
141#define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */
142#define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */
143#define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */
144#define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */
145#define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */
146#define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */
147#define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */
148
149/* USB OTG Control Registers */
150
151#define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */
152#define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */
153#define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */
154
155/* USB Phy Control Registers */
156
157#define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */
158#define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */
159#define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */
160#define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */
161#define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */
162
163/* (APHY_CNTRL is for ADI usage only) */
164
165#define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */
166
167/* (APHY_CALIB is for ADI usage only) */
168
169#define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */
170#define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
171
172/* (PHY_TEST is for ADI usage only) */
173
174#define USB_PHY_TEST 0xffc03dec /* Used for reducing simulation time and simplifies FIFO testability */
175#define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */
176#define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
177
178/* USB Endpoint 0 Control Registers */
179
180#define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */
181#define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */
182#define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */
183#define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */
184#define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */
185#define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
186#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */
187#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
188#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
189
190/* USB Endpoint 1 Control Registers */
191
192#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
193#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */
194#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */
195#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */
196#define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */
197#define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */
198#define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
199#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */
200#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
201#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
202
203/* USB Endpoint 2 Control Registers */
204
205#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
206#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */
207#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */
208#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */
209#define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */
210#define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */
211#define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
212#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */
213#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
214#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
215
216/* USB Endpoint 3 Control Registers */
217
218#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
219#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */
220#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */
221#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */
222#define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */
223#define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */
224#define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
225#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */
226#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
227#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
228
229/* USB Endpoint 4 Control Registers */
230
231#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
232#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */
233#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */
234#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */
235#define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */
236#define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */
237#define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
238#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */
239#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
240#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
241
242/* USB Endpoint 5 Control Registers */
243
244#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
245#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */
246#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */
247#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */
248#define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */
249#define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */
250#define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
251#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */
252#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
253#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
254
255/* USB Endpoint 6 Control Registers */
256
257#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
258#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */
259#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */
260#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */
261#define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */
262#define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */
263#define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
264#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */
265#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
266#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
267
268/* USB Endpoint 7 Control Registers */
269
270#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
271#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */
272#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */
273#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */
274#define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */
275#define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */
276#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
277#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */
278#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
279#define USB_EP_NI7_RXINTERVAL 0xffc03ff0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
280#define USB_EP_NI7_TXCOUNT 0xffc03ff8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
281#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */
282
283/* USB Channel 0 Config Registers */
284
285#define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */
286#define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
287#define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
288#define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
289#define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
290
291/* USB Channel 1 Config Registers */
292
293#define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */
294#define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
295#define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
296#define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
297#define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
298
299/* USB Channel 2 Config Registers */
300
301#define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */
302#define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
303#define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
304#define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
305#define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
306
307/* USB Channel 3 Config Registers */
308
309#define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */
310#define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
311#define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
312#define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
313#define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
314
315/* USB Channel 4 Config Registers */
316
317#define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */
318#define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
319#define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
320#define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
321#define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
322
323/* USB Channel 5 Config Registers */
324
325#define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */
326#define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
327#define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
328#define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
329#define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
330
331/* USB Channel 6 Config Registers */
332
333#define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */
334#define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
335#define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
336#define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
337#define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
338
339/* USB Channel 7 Config Registers */
340
341#define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */
342#define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
343#define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
344#define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
345#define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
346
347/* Keypad Registers */
348
349#define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */
350#define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */
351#define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */
352#define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */
353#define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */
354#define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */
355
356
357/* ********************************************************** */
358/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
359/* and MULTI BIT READ MACROS */
360/* ********************************************************** */
361
362/* Bit masks for KPAD_CTL */
363
364#define KPAD_EN 0x1 /* Keypad Enable */
365#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */
366#define KPAD_ROWEN 0x1c00 /* Row Enable Width */
367#define KPAD_COLEN 0xe000 /* Column Enable Width */
368
369/* Bit masks for KPAD_PRESCALE */
370
371#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */
372
373/* Bit masks for KPAD_MSEL */
374
375#define DBON_SCALE 0xff /* Debounce Scale Value */
376#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */
377
378/* Bit masks for KPAD_ROWCOL */
379
380#define KPAD_ROW 0xff /* Rows Pressed */
381#define KPAD_COL 0xff00 /* Columns Pressed */
382
383/* Bit masks for KPAD_STAT */
384
385#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */
386#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */
387#define KPAD_PRESSED 0x8 /* Key press current status */
388
389/* Bit masks for KPAD_SOFTEVAL */
390
391#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
392
393/* Bit masks for SDH_COMMAND */
394
395#define CMD_IDX 0x3f /* Command Index */
396#define CMD_RSP 0x40 /* Response */
397#define CMD_L_RSP 0x80 /* Long Response */
398#define CMD_INT_E 0x100 /* Command Interrupt */
399#define CMD_PEND_E 0x200 /* Command Pending */
400#define CMD_E 0x400 /* Command Enable */
401
402/* Bit masks for SDH_PWR_CTL */
403
404#define PWR_ON 0x3 /* Power On */
405#if 0
406#define TBD 0x3c /* TBD */
407#endif
408#define SD_CMD_OD 0x40 /* Open Drain Output */
409#define ROD_CTL 0x80 /* Rod Control */
410
411/* Bit masks for SDH_CLK_CTL */
412
413#define CLKDIV 0xff /* MC_CLK Divisor */
414#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
415#define PWR_SV_E 0x200 /* Power Save Enable */
416#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
417#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
418
419/* Bit masks for SDH_RESP_CMD */
420
421#define RESP_CMD 0x3f /* Response Command */
422
423/* Bit masks for SDH_DATA_CTL */
424
425#define DTX_E 0x1 /* Data Transfer Enable */
426#define DTX_DIR 0x2 /* Data Transfer Direction */
427#define DTX_MODE 0x4 /* Data Transfer Mode */
428#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
429#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
430
431/* Bit masks for SDH_STATUS */
432
433#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
434#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
435#define CMD_TIME_OUT 0x4 /* CMD Time Out */
436#define DAT_TIME_OUT 0x8 /* Data Time Out */
437#define TX_UNDERRUN 0x10 /* Transmit Underrun */
438#define RX_OVERRUN 0x20 /* Receive Overrun */
439#define CMD_RESP_END 0x40 /* CMD Response End */
440#define CMD_SENT 0x80 /* CMD Sent */
441#define DAT_END 0x100 /* Data End */
442#define START_BIT_ERR 0x200 /* Start Bit Error */
443#define DAT_BLK_END 0x400 /* Data Block End */
444#define CMD_ACT 0x800 /* CMD Active */
445#define TX_ACT 0x1000 /* Transmit Active */
446#define RX_ACT 0x2000 /* Receive Active */
447#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
448#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
449#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
450#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
451#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
452#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
453#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
454#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
455
456/* Bit masks for SDH_STATUS_CLR */
457
458#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
459#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
460#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
461#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
462#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
463#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
464#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
465#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
466#define DAT_END_STAT 0x100 /* Data End Status */
467#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
468#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
469
470/* Bit masks for SDH_MASK0 */
471
472#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
473#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
474#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
475#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
476#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
477#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
478#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
479#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
480#define DAT_END_MASK 0x100 /* Data End Mask */
481#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
482#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
483#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
484#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
485#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
486#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
487#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
488#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
489#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
490#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
491#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
492#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
493#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
494
495/* Bit masks for SDH_FIFO_CNT */
496
497#define FIFO_COUNT 0x7fff /* FIFO Count */
498
499/* Bit masks for SDH_E_STATUS */
500
501#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
502#define SD_CARD_DET 0x10 /* SD Card Detect */
503
504/* Bit masks for SDH_E_MASK */
505
506#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
507#define SCD_MSK 0x40 /* Mask Card Detect */
508
509/* Bit masks for SDH_CFG */
510
511#define CLKS_EN 0x1 /* Clocks Enable */
512#define SD4E 0x4 /* SDIO 4-Bit Enable */
513#define MWE 0x8 /* Moving Window Enable */
514#define SD_RST 0x10 /* SDMMC Reset */
515#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
516#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
517#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
518
519/* Bit masks for SDH_RD_WAIT_EN */
520
521#define RWR 0x1 /* Read Wait Request */
522
523/* Bit masks for ATAPI_CONTROL */
524
525#define PIO_START 0x1 /* Start PIO/Reg Op */
526#define MULTI_START 0x2 /* Start Multi-DMA Op */
527#define ULTRA_START 0x4 /* Start Ultra-DMA Op */
528#define XFER_DIR 0x8 /* Transfer Direction */
529#define IORDY_EN 0x10 /* IORDY Enable */
530#define FIFO_FLUSH 0x20 /* Flush FIFOs */
531#define SOFT_RST 0x40 /* Soft Reset */
532#define DEV_RST 0x80 /* Device Reset */
533#define TFRCNT_RST 0x100 /* Trans Count Reset */
534#define END_ON_TERM 0x200 /* End/Terminate Select */
535#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
536#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
537
538/* Bit masks for ATAPI_STATUS */
539
540#define PIO_XFER_ON 0x1 /* PIO transfer in progress */
541#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
542#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
543#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */
544
545/* Bit masks for ATAPI_DEV_ADDR */
546
547#define DEV_ADDR 0x1f /* Device Address */
548
549/* Bit masks for ATAPI_INT_MASK */
550
551#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */
552#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
553#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
554#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
555#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
556#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
557#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
558#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
559#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
560
561/* Bit masks for ATAPI_INT_STATUS */
562
563#define ATAPI_DEV_INT 0x1 /* Device interrupt status */
564#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
565#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
566#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
567#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
568#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
569#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
570#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
571#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
572
573/* Bit masks for ATAPI_LINE_STATUS */
574
575#define ATAPI_INTR 0x1 /* Device interrupt to host line status */
576#define ATAPI_DASP 0x2 /* Device dasp to host line status */
577#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
578#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
579#define ATAPI_ADDR 0x70 /* ATAPI address line status */
580#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
581#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
582#define ATAPI_DIOWN 0x200 /* ATAPI write line status */
583#define ATAPI_DIORN 0x400 /* ATAPI read line status */
584#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
585
586/* Bit masks for ATAPI_SM_STATE */
587
588#define PIO_CSTATE 0xf /* PIO mode state machine current state */
589#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */
590#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */
591#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */
592
593/* Bit masks for ATAPI_TERMINATE */
594
595#define ATAPI_HOST_TERM 0x1 /* Host terminationation */
596
597/* Bit masks for ATAPI_REG_TIM_0 */
598
599#define T2_REG 0xff /* End of cycle time for register access transfers */
600#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */
601
602/* Bit masks for ATAPI_PIO_TIM_0 */
603
604#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */
605#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */
606#define T4_REG 0xf000 /* DIOW data hold */
607
608/* Bit masks for ATAPI_PIO_TIM_1 */
609
610#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */
611
612/* Bit masks for ATAPI_MULTI_TIM_0 */
613
614#define TD 0xff /* DIOR/DIOW asserted pulsewidth */
615#define TM 0xff00 /* Time from address valid to DIOR/DIOW */
616
617/* Bit masks for ATAPI_MULTI_TIM_1 */
618
619#define TKW 0xff /* Selects DIOW negated pulsewidth */
620#define TKR 0xff00 /* Selects DIOR negated pulsewidth */
621
622/* Bit masks for ATAPI_MULTI_TIM_2 */
623
624#define TH 0xff /* Selects DIOW data hold */
625#define TEOC 0xff00 /* Selects end of cycle for DMA */
626
627/* Bit masks for ATAPI_ULTRA_TIM_0 */
628
629#define TACK 0xff /* Selects setup and hold times for TACK */
630#define TENV 0xff00 /* Selects envelope time */
631
632/* Bit masks for ATAPI_ULTRA_TIM_1 */
633
634#define TDVS 0xff /* Selects data valid setup time */
635#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */
636
637/* Bit masks for ATAPI_ULTRA_TIM_2 */
638
639#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
640#define TMLI 0xff00 /* Selects interlock time */
641
642/* Bit masks for ATAPI_ULTRA_TIM_3 */
643
644#define TZAH 0xff /* Selects minimum delay required for output */
645#define READY_PAUSE 0xff00 /* Selects ready to pause */
646
647/* Bit masks for USB_FADDR */
648
649#define FUNCTION_ADDRESS 0x7f /* Function address */
650
651/* Bit masks for USB_POWER */
652
653#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
654#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
655#define RESUME_MODE 0x4 /* DMA Mode */
656#define RESET 0x8 /* Reset indicator */
657#define HS_MODE 0x10 /* High Speed mode indicator */
658#define HS_ENABLE 0x20 /* high Speed Enable */
659#define SOFT_CONN 0x40 /* Soft connect */
660#define ISO_UPDATE 0x80 /* Isochronous update */
661
662/* Bit masks for USB_INTRTX */
663
664#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
665#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
666#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
667#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
668#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
669#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
670#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
671#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
672
673/* Bit masks for USB_INTRRX */
674
675#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
676#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
677#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
678#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
679#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
680#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
681#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
682
683/* Bit masks for USB_INTRTXE */
684
685#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
686#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
687#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
688#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
689#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
690#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
691#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
692#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
693
694/* Bit masks for USB_INTRRXE */
695
696#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
697#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
698#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
699#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
700#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
701#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
702#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
703
704/* Bit masks for USB_INTRUSB */
705
706#define SUSPEND_B 0x1 /* Suspend indicator */
707#define RESUME_B 0x2 /* Resume indicator */
708#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
709#define SOF_B 0x8 /* Start of frame */
710#define CONN_B 0x10 /* Connection indicator */
711#define DISCON_B 0x20 /* Disconnect indicator */
712#define SESSION_REQ_B 0x40 /* Session Request */
713#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
714
715/* Bit masks for USB_INTRUSBE */
716
717#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
718#define RESUME_BE 0x2 /* Resume indicator int enable */
719#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
720#define SOF_BE 0x8 /* Start of frame int enable */
721#define CONN_BE 0x10 /* Connection indicator int enable */
722#define DISCON_BE 0x20 /* Disconnect indicator int enable */
723#define SESSION_REQ_BE 0x40 /* Session Request int enable */
724#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
725
726/* Bit masks for USB_FRAME */
727
728#define FRAME_NUMBER 0x7ff /* Frame number */
729
730/* Bit masks for USB_INDEX */
731
732#define SELECTED_ENDPOINT 0xf /* selected endpoint */
733
734/* Bit masks for USB_GLOBAL_CTL */
735
736#define GLOBAL_ENA 0x1 /* enables USB module */
737#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
738#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
739#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
740#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
741#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
742#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
743#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
744#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
745#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
746#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
747#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
748#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
749#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
750#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
751
752/* Bit masks for USB_OTG_DEV_CTL */
753
754#define SESSION 0x1 /* session indicator */
755#define HOST_REQ 0x2 /* Host negotiation request */
756#define HOST_MODE 0x4 /* indicates USBDRC is a host */
757#define VBUS0 0x8 /* Vbus level indicator[0] */
758#define VBUS1 0x10 /* Vbus level indicator[1] */
759#define LSDEV 0x20 /* Low-speed indicator */
760#define FSDEV 0x40 /* Full or High-speed indicator */
761#define B_DEVICE 0x80 /* A' or 'B' device indicator */
762
763/* Bit masks for USB_OTG_VBUS_IRQ */
764
765#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
766#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
767#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
768#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
769#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
770#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
771
772/* Bit masks for USB_OTG_VBUS_MASK */
773
774#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
775#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
776#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
777#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
778#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
779#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
780
781/* Bit masks for USB_CSR0 */
782
783#define RXPKTRDY 0x1 /* data packet receive indicator */
784#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
785#define STALL_SENT 0x4 /* STALL handshake sent */
786#define DATAEND 0x8 /* Data end indicator */
787#define SETUPEND 0x10 /* Setup end */
788#define SENDSTALL 0x20 /* Send STALL handshake */
789#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
790#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
791#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
792#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
793#define SETUPPKT_H 0x8 /* send Setup token host mode */
794#define ERROR_H 0x10 /* timeout error indicator host mode */
795#define REQPKT_H 0x20 /* Request an IN transaction host mode */
796#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
797#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
798
799/* Bit masks for USB_COUNT0 */
800
801#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
802
803/* Bit masks for USB_NAKLIMIT0 */
804
805#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
806
807/* Bit masks for USB_TX_MAX_PACKET */
808
809#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
810
811/* Bit masks for USB_RX_MAX_PACKET */
812
813#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
814
815/* Bit masks for USB_TXCSR */
816
817#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
818#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
819#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
820#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
821#define STALL_SEND_T 0x10 /* issue a Stall handshake */
822#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
823#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
824#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
825#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
826#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
827#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
828#define ISO_T 0x4000 /* enable Isochronous transfers */
829#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
830#define ERROR_TH 0x4 /* error condition host mode */
831#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
832#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
833
834/* Bit masks for USB_TXCOUNT */
835
836#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
837
838/* Bit masks for USB_RXCSR */
839
840#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
841#define FIFO_FULL_R 0x2 /* FIFO not empty */
842#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
843#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
844#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
845#define STALL_SEND_R 0x20 /* issue a Stall handshake */
846#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
847#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
848#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
849#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
850#define DISNYET_R 0x1000 /* disable Nyet handshakes */
851#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
852#define ISO_R 0x4000 /* enable Isochronous transfers */
853#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
854#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
855#define REQPKT_RH 0x20 /* request an IN transaction host mode */
856#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
857#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
858#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
859#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
860
861/* Bit masks for USB_RXCOUNT */
862
863#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
864
865/* Bit masks for USB_TXTYPE */
866
867#define TARGET_EP_NO_T 0xf /* EP number */
868#define PROTOCOL_T 0xc /* transfer type */
869
870/* Bit masks for USB_TXINTERVAL */
871
872#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
873
874/* Bit masks for USB_RXTYPE */
875
876#define TARGET_EP_NO_R 0xf /* EP number */
877#define PROTOCOL_R 0xc /* transfer type */
878
879/* Bit masks for USB_RXINTERVAL */
880
881#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
882
883/* Bit masks for USB_DMA_INTERRUPT */
884
885#define DMA0_INT 0x1 /* DMA0 pending interrupt */
886#define DMA1_INT 0x2 /* DMA1 pending interrupt */
887#define DMA2_INT 0x4 /* DMA2 pending interrupt */
888#define DMA3_INT 0x8 /* DMA3 pending interrupt */
889#define DMA4_INT 0x10 /* DMA4 pending interrupt */
890#define DMA5_INT 0x20 /* DMA5 pending interrupt */
891#define DMA6_INT 0x40 /* DMA6 pending interrupt */
892#define DMA7_INT 0x80 /* DMA7 pending interrupt */
893
894/* Bit masks for USB_DMAxCONTROL */
895
896#define DMA_ENA 0x1 /* DMA enable */
897#define DIRECTION 0x2 /* direction of DMA transfer */
898#define MODE 0x4 /* DMA Bus error */
899#define INT_ENA 0x8 /* Interrupt enable */
900#define EPNUM 0xf0 /* EP number */
901#define BUSERROR 0x100 /* DMA Bus error */
902
903/* Bit masks for USB_DMAxADDRHIGH */
904
905#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
906
907/* Bit masks for USB_DMAxADDRLOW */
908
909#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
910
911/* Bit masks for USB_DMAxCOUNTHIGH */
912
913#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
914
915/* Bit masks for USB_DMAxCOUNTLOW */
916
917#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
918
919
920/* ******************************************* */
921/* MULTI BIT MACRO ENUMERATIONS */
922/* ******************************************* */
923
924
925#endif /* _DEF_BF542_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF544.h b/arch/blackfin/mach-bf548/include/mach/defBF544.h
new file mode 100644
index 000000000000..c2c785bdc5fc
--- /dev/null
+++ b/arch/blackfin/mach-bf548/include/mach/defBF544.h
@@ -0,0 +1,707 @@
1/*
2 * File: include/asm-blackfin/mach-bf548/defBF544.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _DEF_BF544_H
32#define _DEF_BF544_H
33
34/* Include all Core registers and bit definitions */
35#include <asm/def_LPBlackfin.h>
36
37/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF544 */
38
39/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
40#include "defBF54x_base.h"
41
42/* The following are the #defines needed by ADSP-BF544 that are not in the common header */
43
44/* Timer Registers */
45
46#define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */
47#define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */
48#define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */
49#define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */
50#define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */
51#define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */
52#define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */
53#define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */
54#define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */
55#define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */
56#define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */
57#define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */
58
59/* Timer Group of 3 Registers */
60
61#define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */
62#define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */
63#define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */
64
65/* EPPI0 Registers */
66
67#define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */
68#define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */
69#define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */
70#define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */
71#define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */
72#define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */
73#define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */
74#define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */
75#define EPPI0_CONTROL 0xffc01020 /* EPPI0 Control Register */
76#define EPPI0_FS1W_HBL 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
77#define EPPI0_FS1P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
78#define EPPI0_FS2W_LVB 0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
79#define EPPI0_FS2P_LAVF 0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
80#define EPPI0_CLIP 0xffc01034 /* EPPI0 Clipping Register */
81
82/* Two Wire Interface Registers (TWI1) */
83
84#define TWI1_REGBASE 0xffc02200
85#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
86#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
87#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */
88#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */
89#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */
90#define TWI1_MASTER_CTRL 0xffc02214 /* TWI Master Mode Control Register */
91#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */
92#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */
93#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */
94#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */
95#define TWI1_FIFO_CTRL 0xffc02228 /* TWI FIFO Control Register */
96#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */
97#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */
98#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */
99#define TWI1_RCV_DATA8 0xffc02288 /* TWI FIFO Receive Data Single Byte Register */
100#define TWI1_RCV_DATA16 0xffc0228c /* TWI FIFO Receive Data Double Byte Register */
101
102/* CAN Controller 1 Config 1 Registers */
103
104#define CAN1_MC1 0xffc03200 /* CAN Controller 1 Mailbox Configuration Register 1 */
105#define CAN1_MD1 0xffc03204 /* CAN Controller 1 Mailbox Direction Register 1 */
106#define CAN1_TRS1 0xffc03208 /* CAN Controller 1 Transmit Request Set Register 1 */
107#define CAN1_TRR1 0xffc0320c /* CAN Controller 1 Transmit Request Reset Register 1 */
108#define CAN1_TA1 0xffc03210 /* CAN Controller 1 Transmit Acknowledge Register 1 */
109#define CAN1_AA1 0xffc03214 /* CAN Controller 1 Abort Acknowledge Register 1 */
110#define CAN1_RMP1 0xffc03218 /* CAN Controller 1 Receive Message Pending Register 1 */
111#define CAN1_RML1 0xffc0321c /* CAN Controller 1 Receive Message Lost Register 1 */
112#define CAN1_MBTIF1 0xffc03220 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
113#define CAN1_MBRIF1 0xffc03224 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
114#define CAN1_MBIM1 0xffc03228 /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
115#define CAN1_RFH1 0xffc0322c /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
116#define CAN1_OPSS1 0xffc03230 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
117
118/* CAN Controller 1 Config 2 Registers */
119
120#define CAN1_MC2 0xffc03240 /* CAN Controller 1 Mailbox Configuration Register 2 */
121#define CAN1_MD2 0xffc03244 /* CAN Controller 1 Mailbox Direction Register 2 */
122#define CAN1_TRS2 0xffc03248 /* CAN Controller 1 Transmit Request Set Register 2 */
123#define CAN1_TRR2 0xffc0324c /* CAN Controller 1 Transmit Request Reset Register 2 */
124#define CAN1_TA2 0xffc03250 /* CAN Controller 1 Transmit Acknowledge Register 2 */
125#define CAN1_AA2 0xffc03254 /* CAN Controller 1 Abort Acknowledge Register 2 */
126#define CAN1_RMP2 0xffc03258 /* CAN Controller 1 Receive Message Pending Register 2 */
127#define CAN1_RML2 0xffc0325c /* CAN Controller 1 Receive Message Lost Register 2 */
128#define CAN1_MBTIF2 0xffc03260 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
129#define CAN1_MBRIF2 0xffc03264 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
130#define CAN1_MBIM2 0xffc03268 /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
131#define CAN1_RFH2 0xffc0326c /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
132#define CAN1_OPSS2 0xffc03270 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
133
134/* CAN Controller 1 Clock/Interrupt/Counter Registers */
135
136#define CAN1_CLOCK 0xffc03280 /* CAN Controller 1 Clock Register */
137#define CAN1_TIMING 0xffc03284 /* CAN Controller 1 Timing Register */
138#define CAN1_DEBUG 0xffc03288 /* CAN Controller 1 Debug Register */
139#define CAN1_STATUS 0xffc0328c /* CAN Controller 1 Global Status Register */
140#define CAN1_CEC 0xffc03290 /* CAN Controller 1 Error Counter Register */
141#define CAN1_GIS 0xffc03294 /* CAN Controller 1 Global Interrupt Status Register */
142#define CAN1_GIM 0xffc03298 /* CAN Controller 1 Global Interrupt Mask Register */
143#define CAN1_GIF 0xffc0329c /* CAN Controller 1 Global Interrupt Flag Register */
144#define CAN1_CONTROL 0xffc032a0 /* CAN Controller 1 Master Control Register */
145#define CAN1_INTR 0xffc032a4 /* CAN Controller 1 Interrupt Pending Register */
146#define CAN1_MBTD 0xffc032ac /* CAN Controller 1 Mailbox Temporary Disable Register */
147#define CAN1_EWR 0xffc032b0 /* CAN Controller 1 Programmable Warning Level Register */
148#define CAN1_ESR 0xffc032b4 /* CAN Controller 1 Error Status Register */
149#define CAN1_UCCNT 0xffc032c4 /* CAN Controller 1 Universal Counter Register */
150#define CAN1_UCRC 0xffc032c8 /* CAN Controller 1 Universal Counter Force Reload Register */
151#define CAN1_UCCNF 0xffc032cc /* CAN Controller 1 Universal Counter Configuration Register */
152
153/* CAN Controller 1 Mailbox Acceptance Registers */
154
155#define CAN1_AM00L 0xffc03300 /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
156#define CAN1_AM00H 0xffc03304 /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
157#define CAN1_AM01L 0xffc03308 /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
158#define CAN1_AM01H 0xffc0330c /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
159#define CAN1_AM02L 0xffc03310 /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
160#define CAN1_AM02H 0xffc03314 /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
161#define CAN1_AM03L 0xffc03318 /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
162#define CAN1_AM03H 0xffc0331c /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
163#define CAN1_AM04L 0xffc03320 /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
164#define CAN1_AM04H 0xffc03324 /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
165#define CAN1_AM05L 0xffc03328 /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
166#define CAN1_AM05H 0xffc0332c /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
167#define CAN1_AM06L 0xffc03330 /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
168#define CAN1_AM06H 0xffc03334 /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
169#define CAN1_AM07L 0xffc03338 /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
170#define CAN1_AM07H 0xffc0333c /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
171#define CAN1_AM08L 0xffc03340 /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
172#define CAN1_AM08H 0xffc03344 /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
173#define CAN1_AM09L 0xffc03348 /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
174#define CAN1_AM09H 0xffc0334c /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
175#define CAN1_AM10L 0xffc03350 /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
176#define CAN1_AM10H 0xffc03354 /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
177#define CAN1_AM11L 0xffc03358 /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
178#define CAN1_AM11H 0xffc0335c /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
179#define CAN1_AM12L 0xffc03360 /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
180#define CAN1_AM12H 0xffc03364 /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
181#define CAN1_AM13L 0xffc03368 /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
182#define CAN1_AM13H 0xffc0336c /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
183#define CAN1_AM14L 0xffc03370 /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
184#define CAN1_AM14H 0xffc03374 /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
185#define CAN1_AM15L 0xffc03378 /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
186#define CAN1_AM15H 0xffc0337c /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
187
188/* CAN Controller 1 Mailbox Acceptance Registers */
189
190#define CAN1_AM16L 0xffc03380 /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
191#define CAN1_AM16H 0xffc03384 /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
192#define CAN1_AM17L 0xffc03388 /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
193#define CAN1_AM17H 0xffc0338c /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
194#define CAN1_AM18L 0xffc03390 /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
195#define CAN1_AM18H 0xffc03394 /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
196#define CAN1_AM19L 0xffc03398 /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
197#define CAN1_AM19H 0xffc0339c /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
198#define CAN1_AM20L 0xffc033a0 /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
199#define CAN1_AM20H 0xffc033a4 /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
200#define CAN1_AM21L 0xffc033a8 /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
201#define CAN1_AM21H 0xffc033ac /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
202#define CAN1_AM22L 0xffc033b0 /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
203#define CAN1_AM22H 0xffc033b4 /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
204#define CAN1_AM23L 0xffc033b8 /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
205#define CAN1_AM23H 0xffc033bc /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
206#define CAN1_AM24L 0xffc033c0 /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
207#define CAN1_AM24H 0xffc033c4 /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
208#define CAN1_AM25L 0xffc033c8 /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
209#define CAN1_AM25H 0xffc033cc /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
210#define CAN1_AM26L 0xffc033d0 /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
211#define CAN1_AM26H 0xffc033d4 /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
212#define CAN1_AM27L 0xffc033d8 /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
213#define CAN1_AM27H 0xffc033dc /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
214#define CAN1_AM28L 0xffc033e0 /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
215#define CAN1_AM28H 0xffc033e4 /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
216#define CAN1_AM29L 0xffc033e8 /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
217#define CAN1_AM29H 0xffc033ec /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
218#define CAN1_AM30L 0xffc033f0 /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
219#define CAN1_AM30H 0xffc033f4 /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
220#define CAN1_AM31L 0xffc033f8 /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
221#define CAN1_AM31H 0xffc033fc /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
222
223/* CAN Controller 1 Mailbox Data Registers */
224
225#define CAN1_MB00_DATA0 0xffc03400 /* CAN Controller 1 Mailbox 0 Data 0 Register */
226#define CAN1_MB00_DATA1 0xffc03404 /* CAN Controller 1 Mailbox 0 Data 1 Register */
227#define CAN1_MB00_DATA2 0xffc03408 /* CAN Controller 1 Mailbox 0 Data 2 Register */
228#define CAN1_MB00_DATA3 0xffc0340c /* CAN Controller 1 Mailbox 0 Data 3 Register */
229#define CAN1_MB00_LENGTH 0xffc03410 /* CAN Controller 1 Mailbox 0 Length Register */
230#define CAN1_MB00_TIMESTAMP 0xffc03414 /* CAN Controller 1 Mailbox 0 Timestamp Register */
231#define CAN1_MB00_ID0 0xffc03418 /* CAN Controller 1 Mailbox 0 ID0 Register */
232#define CAN1_MB00_ID1 0xffc0341c /* CAN Controller 1 Mailbox 0 ID1 Register */
233#define CAN1_MB01_DATA0 0xffc03420 /* CAN Controller 1 Mailbox 1 Data 0 Register */
234#define CAN1_MB01_DATA1 0xffc03424 /* CAN Controller 1 Mailbox 1 Data 1 Register */
235#define CAN1_MB01_DATA2 0xffc03428 /* CAN Controller 1 Mailbox 1 Data 2 Register */
236#define CAN1_MB01_DATA3 0xffc0342c /* CAN Controller 1 Mailbox 1 Data 3 Register */
237#define CAN1_MB01_LENGTH 0xffc03430 /* CAN Controller 1 Mailbox 1 Length Register */
238#define CAN1_MB01_TIMESTAMP 0xffc03434 /* CAN Controller 1 Mailbox 1 Timestamp Register */
239#define CAN1_MB01_ID0 0xffc03438 /* CAN Controller 1 Mailbox 1 ID0 Register */
240#define CAN1_MB01_ID1 0xffc0343c /* CAN Controller 1 Mailbox 1 ID1 Register */
241#define CAN1_MB02_DATA0 0xffc03440 /* CAN Controller 1 Mailbox 2 Data 0 Register */
242#define CAN1_MB02_DATA1 0xffc03444 /* CAN Controller 1 Mailbox 2 Data 1 Register */
243#define CAN1_MB02_DATA2 0xffc03448 /* CAN Controller 1 Mailbox 2 Data 2 Register */
244#define CAN1_MB02_DATA3 0xffc0344c /* CAN Controller 1 Mailbox 2 Data 3 Register */
245#define CAN1_MB02_LENGTH 0xffc03450 /* CAN Controller 1 Mailbox 2 Length Register */
246#define CAN1_MB02_TIMESTAMP 0xffc03454 /* CAN Controller 1 Mailbox 2 Timestamp Register */
247#define CAN1_MB02_ID0 0xffc03458 /* CAN Controller 1 Mailbox 2 ID0 Register */
248#define CAN1_MB02_ID1 0xffc0345c /* CAN Controller 1 Mailbox 2 ID1 Register */
249#define CAN1_MB03_DATA0 0xffc03460 /* CAN Controller 1 Mailbox 3 Data 0 Register */
250#define CAN1_MB03_DATA1 0xffc03464 /* CAN Controller 1 Mailbox 3 Data 1 Register */
251#define CAN1_MB03_DATA2 0xffc03468 /* CAN Controller 1 Mailbox 3 Data 2 Register */
252#define CAN1_MB03_DATA3 0xffc0346c /* CAN Controller 1 Mailbox 3 Data 3 Register */
253#define CAN1_MB03_LENGTH 0xffc03470 /* CAN Controller 1 Mailbox 3 Length Register */
254#define CAN1_MB03_TIMESTAMP 0xffc03474 /* CAN Controller 1 Mailbox 3 Timestamp Register */
255#define CAN1_MB03_ID0 0xffc03478 /* CAN Controller 1 Mailbox 3 ID0 Register */
256#define CAN1_MB03_ID1 0xffc0347c /* CAN Controller 1 Mailbox 3 ID1 Register */
257#define CAN1_MB04_DATA0 0xffc03480 /* CAN Controller 1 Mailbox 4 Data 0 Register */
258#define CAN1_MB04_DATA1 0xffc03484 /* CAN Controller 1 Mailbox 4 Data 1 Register */
259#define CAN1_MB04_DATA2 0xffc03488 /* CAN Controller 1 Mailbox 4 Data 2 Register */
260#define CAN1_MB04_DATA3 0xffc0348c /* CAN Controller 1 Mailbox 4 Data 3 Register */
261#define CAN1_MB04_LENGTH 0xffc03490 /* CAN Controller 1 Mailbox 4 Length Register */
262#define CAN1_MB04_TIMESTAMP 0xffc03494 /* CAN Controller 1 Mailbox 4 Timestamp Register */
263#define CAN1_MB04_ID0 0xffc03498 /* CAN Controller 1 Mailbox 4 ID0 Register */
264#define CAN1_MB04_ID1 0xffc0349c /* CAN Controller 1 Mailbox 4 ID1 Register */
265#define CAN1_MB05_DATA0 0xffc034a0 /* CAN Controller 1 Mailbox 5 Data 0 Register */
266#define CAN1_MB05_DATA1 0xffc034a4 /* CAN Controller 1 Mailbox 5 Data 1 Register */
267#define CAN1_MB05_DATA2 0xffc034a8 /* CAN Controller 1 Mailbox 5 Data 2 Register */
268#define CAN1_MB05_DATA3 0xffc034ac /* CAN Controller 1 Mailbox 5 Data 3 Register */
269#define CAN1_MB05_LENGTH 0xffc034b0 /* CAN Controller 1 Mailbox 5 Length Register */
270#define CAN1_MB05_TIMESTAMP 0xffc034b4 /* CAN Controller 1 Mailbox 5 Timestamp Register */
271#define CAN1_MB05_ID0 0xffc034b8 /* CAN Controller 1 Mailbox 5 ID0 Register */
272#define CAN1_MB05_ID1 0xffc034bc /* CAN Controller 1 Mailbox 5 ID1 Register */
273#define CAN1_MB06_DATA0 0xffc034c0 /* CAN Controller 1 Mailbox 6 Data 0 Register */
274#define CAN1_MB06_DATA1 0xffc034c4 /* CAN Controller 1 Mailbox 6 Data 1 Register */
275#define CAN1_MB06_DATA2 0xffc034c8 /* CAN Controller 1 Mailbox 6 Data 2 Register */
276#define CAN1_MB06_DATA3 0xffc034cc /* CAN Controller 1 Mailbox 6 Data 3 Register */
277#define CAN1_MB06_LENGTH 0xffc034d0 /* CAN Controller 1 Mailbox 6 Length Register */
278#define CAN1_MB06_TIMESTAMP 0xffc034d4 /* CAN Controller 1 Mailbox 6 Timestamp Register */
279#define CAN1_MB06_ID0 0xffc034d8 /* CAN Controller 1 Mailbox 6 ID0 Register */
280#define CAN1_MB06_ID1 0xffc034dc /* CAN Controller 1 Mailbox 6 ID1 Register */
281#define CAN1_MB07_DATA0 0xffc034e0 /* CAN Controller 1 Mailbox 7 Data 0 Register */
282#define CAN1_MB07_DATA1 0xffc034e4 /* CAN Controller 1 Mailbox 7 Data 1 Register */
283#define CAN1_MB07_DATA2 0xffc034e8 /* CAN Controller 1 Mailbox 7 Data 2 Register */
284#define CAN1_MB07_DATA3 0xffc034ec /* CAN Controller 1 Mailbox 7 Data 3 Register */
285#define CAN1_MB07_LENGTH 0xffc034f0 /* CAN Controller 1 Mailbox 7 Length Register */
286#define CAN1_MB07_TIMESTAMP 0xffc034f4 /* CAN Controller 1 Mailbox 7 Timestamp Register */
287#define CAN1_MB07_ID0 0xffc034f8 /* CAN Controller 1 Mailbox 7 ID0 Register */
288#define CAN1_MB07_ID1 0xffc034fc /* CAN Controller 1 Mailbox 7 ID1 Register */
289#define CAN1_MB08_DATA0 0xffc03500 /* CAN Controller 1 Mailbox 8 Data 0 Register */
290#define CAN1_MB08_DATA1 0xffc03504 /* CAN Controller 1 Mailbox 8 Data 1 Register */
291#define CAN1_MB08_DATA2 0xffc03508 /* CAN Controller 1 Mailbox 8 Data 2 Register */
292#define CAN1_MB08_DATA3 0xffc0350c /* CAN Controller 1 Mailbox 8 Data 3 Register */
293#define CAN1_MB08_LENGTH 0xffc03510 /* CAN Controller 1 Mailbox 8 Length Register */
294#define CAN1_MB08_TIMESTAMP 0xffc03514 /* CAN Controller 1 Mailbox 8 Timestamp Register */
295#define CAN1_MB08_ID0 0xffc03518 /* CAN Controller 1 Mailbox 8 ID0 Register */
296#define CAN1_MB08_ID1 0xffc0351c /* CAN Controller 1 Mailbox 8 ID1 Register */
297#define CAN1_MB09_DATA0 0xffc03520 /* CAN Controller 1 Mailbox 9 Data 0 Register */
298#define CAN1_MB09_DATA1 0xffc03524 /* CAN Controller 1 Mailbox 9 Data 1 Register */
299#define CAN1_MB09_DATA2 0xffc03528 /* CAN Controller 1 Mailbox 9 Data 2 Register */
300#define CAN1_MB09_DATA3 0xffc0352c /* CAN Controller 1 Mailbox 9 Data 3 Register */
301#define CAN1_MB09_LENGTH 0xffc03530 /* CAN Controller 1 Mailbox 9 Length Register */
302#define CAN1_MB09_TIMESTAMP 0xffc03534 /* CAN Controller 1 Mailbox 9 Timestamp Register */
303#define CAN1_MB09_ID0 0xffc03538 /* CAN Controller 1 Mailbox 9 ID0 Register */
304#define CAN1_MB09_ID1 0xffc0353c /* CAN Controller 1 Mailbox 9 ID1 Register */
305#define CAN1_MB10_DATA0 0xffc03540 /* CAN Controller 1 Mailbox 10 Data 0 Register */
306#define CAN1_MB10_DATA1 0xffc03544 /* CAN Controller 1 Mailbox 10 Data 1 Register */
307#define CAN1_MB10_DATA2 0xffc03548 /* CAN Controller 1 Mailbox 10 Data 2 Register */
308#define CAN1_MB10_DATA3 0xffc0354c /* CAN Controller 1 Mailbox 10 Data 3 Register */
309#define CAN1_MB10_LENGTH 0xffc03550 /* CAN Controller 1 Mailbox 10 Length Register */
310#define CAN1_MB10_TIMESTAMP 0xffc03554 /* CAN Controller 1 Mailbox 10 Timestamp Register */
311#define CAN1_MB10_ID0 0xffc03558 /* CAN Controller 1 Mailbox 10 ID0 Register */
312#define CAN1_MB10_ID1 0xffc0355c /* CAN Controller 1 Mailbox 10 ID1 Register */
313#define CAN1_MB11_DATA0 0xffc03560 /* CAN Controller 1 Mailbox 11 Data 0 Register */
314#define CAN1_MB11_DATA1 0xffc03564 /* CAN Controller 1 Mailbox 11 Data 1 Register */
315#define CAN1_MB11_DATA2 0xffc03568 /* CAN Controller 1 Mailbox 11 Data 2 Register */
316#define CAN1_MB11_DATA3 0xffc0356c /* CAN Controller 1 Mailbox 11 Data 3 Register */
317#define CAN1_MB11_LENGTH 0xffc03570 /* CAN Controller 1 Mailbox 11 Length Register */
318#define CAN1_MB11_TIMESTAMP 0xffc03574 /* CAN Controller 1 Mailbox 11 Timestamp Register */
319#define CAN1_MB11_ID0 0xffc03578 /* CAN Controller 1 Mailbox 11 ID0 Register */
320#define CAN1_MB11_ID1 0xffc0357c /* CAN Controller 1 Mailbox 11 ID1 Register */
321#define CAN1_MB12_DATA0 0xffc03580 /* CAN Controller 1 Mailbox 12 Data 0 Register */
322#define CAN1_MB12_DATA1 0xffc03584 /* CAN Controller 1 Mailbox 12 Data 1 Register */
323#define CAN1_MB12_DATA2 0xffc03588 /* CAN Controller 1 Mailbox 12 Data 2 Register */
324#define CAN1_MB12_DATA3 0xffc0358c /* CAN Controller 1 Mailbox 12 Data 3 Register */
325#define CAN1_MB12_LENGTH 0xffc03590 /* CAN Controller 1 Mailbox 12 Length Register */
326#define CAN1_MB12_TIMESTAMP 0xffc03594 /* CAN Controller 1 Mailbox 12 Timestamp Register */
327#define CAN1_MB12_ID0 0xffc03598 /* CAN Controller 1 Mailbox 12 ID0 Register */
328#define CAN1_MB12_ID1 0xffc0359c /* CAN Controller 1 Mailbox 12 ID1 Register */
329#define CAN1_MB13_DATA0 0xffc035a0 /* CAN Controller 1 Mailbox 13 Data 0 Register */
330#define CAN1_MB13_DATA1 0xffc035a4 /* CAN Controller 1 Mailbox 13 Data 1 Register */
331#define CAN1_MB13_DATA2 0xffc035a8 /* CAN Controller 1 Mailbox 13 Data 2 Register */
332#define CAN1_MB13_DATA3 0xffc035ac /* CAN Controller 1 Mailbox 13 Data 3 Register */
333#define CAN1_MB13_LENGTH 0xffc035b0 /* CAN Controller 1 Mailbox 13 Length Register */
334#define CAN1_MB13_TIMESTAMP 0xffc035b4 /* CAN Controller 1 Mailbox 13 Timestamp Register */
335#define CAN1_MB13_ID0 0xffc035b8 /* CAN Controller 1 Mailbox 13 ID0 Register */
336#define CAN1_MB13_ID1 0xffc035bc /* CAN Controller 1 Mailbox 13 ID1 Register */
337#define CAN1_MB14_DATA0 0xffc035c0 /* CAN Controller 1 Mailbox 14 Data 0 Register */
338#define CAN1_MB14_DATA1 0xffc035c4 /* CAN Controller 1 Mailbox 14 Data 1 Register */
339#define CAN1_MB14_DATA2 0xffc035c8 /* CAN Controller 1 Mailbox 14 Data 2 Register */
340#define CAN1_MB14_DATA3 0xffc035cc /* CAN Controller 1 Mailbox 14 Data 3 Register */
341#define CAN1_MB14_LENGTH 0xffc035d0 /* CAN Controller 1 Mailbox 14 Length Register */
342#define CAN1_MB14_TIMESTAMP 0xffc035d4 /* CAN Controller 1 Mailbox 14 Timestamp Register */
343#define CAN1_MB14_ID0 0xffc035d8 /* CAN Controller 1 Mailbox 14 ID0 Register */
344#define CAN1_MB14_ID1 0xffc035dc /* CAN Controller 1 Mailbox 14 ID1 Register */
345#define CAN1_MB15_DATA0 0xffc035e0 /* CAN Controller 1 Mailbox 15 Data 0 Register */
346#define CAN1_MB15_DATA1 0xffc035e4 /* CAN Controller 1 Mailbox 15 Data 1 Register */
347#define CAN1_MB15_DATA2 0xffc035e8 /* CAN Controller 1 Mailbox 15 Data 2 Register */
348#define CAN1_MB15_DATA3 0xffc035ec /* CAN Controller 1 Mailbox 15 Data 3 Register */
349#define CAN1_MB15_LENGTH 0xffc035f0 /* CAN Controller 1 Mailbox 15 Length Register */
350#define CAN1_MB15_TIMESTAMP 0xffc035f4 /* CAN Controller 1 Mailbox 15 Timestamp Register */
351#define CAN1_MB15_ID0 0xffc035f8 /* CAN Controller 1 Mailbox 15 ID0 Register */
352#define CAN1_MB15_ID1 0xffc035fc /* CAN Controller 1 Mailbox 15 ID1 Register */
353
354/* CAN Controller 1 Mailbox Data Registers */
355
356#define CAN1_MB16_DATA0 0xffc03600 /* CAN Controller 1 Mailbox 16 Data 0 Register */
357#define CAN1_MB16_DATA1 0xffc03604 /* CAN Controller 1 Mailbox 16 Data 1 Register */
358#define CAN1_MB16_DATA2 0xffc03608 /* CAN Controller 1 Mailbox 16 Data 2 Register */
359#define CAN1_MB16_DATA3 0xffc0360c /* CAN Controller 1 Mailbox 16 Data 3 Register */
360#define CAN1_MB16_LENGTH 0xffc03610 /* CAN Controller 1 Mailbox 16 Length Register */
361#define CAN1_MB16_TIMESTAMP 0xffc03614 /* CAN Controller 1 Mailbox 16 Timestamp Register */
362#define CAN1_MB16_ID0 0xffc03618 /* CAN Controller 1 Mailbox 16 ID0 Register */
363#define CAN1_MB16_ID1 0xffc0361c /* CAN Controller 1 Mailbox 16 ID1 Register */
364#define CAN1_MB17_DATA0 0xffc03620 /* CAN Controller 1 Mailbox 17 Data 0 Register */
365#define CAN1_MB17_DATA1 0xffc03624 /* CAN Controller 1 Mailbox 17 Data 1 Register */
366#define CAN1_MB17_DATA2 0xffc03628 /* CAN Controller 1 Mailbox 17 Data 2 Register */
367#define CAN1_MB17_DATA3 0xffc0362c /* CAN Controller 1 Mailbox 17 Data 3 Register */
368#define CAN1_MB17_LENGTH 0xffc03630 /* CAN Controller 1 Mailbox 17 Length Register */
369#define CAN1_MB17_TIMESTAMP 0xffc03634 /* CAN Controller 1 Mailbox 17 Timestamp Register */
370#define CAN1_MB17_ID0 0xffc03638 /* CAN Controller 1 Mailbox 17 ID0 Register */
371#define CAN1_MB17_ID1 0xffc0363c /* CAN Controller 1 Mailbox 17 ID1 Register */
372#define CAN1_MB18_DATA0 0xffc03640 /* CAN Controller 1 Mailbox 18 Data 0 Register */
373#define CAN1_MB18_DATA1 0xffc03644 /* CAN Controller 1 Mailbox 18 Data 1 Register */
374#define CAN1_MB18_DATA2 0xffc03648 /* CAN Controller 1 Mailbox 18 Data 2 Register */
375#define CAN1_MB18_DATA3 0xffc0364c /* CAN Controller 1 Mailbox 18 Data 3 Register */
376#define CAN1_MB18_LENGTH 0xffc03650 /* CAN Controller 1 Mailbox 18 Length Register */
377#define CAN1_MB18_TIMESTAMP 0xffc03654 /* CAN Controller 1 Mailbox 18 Timestamp Register */
378#define CAN1_MB18_ID0 0xffc03658 /* CAN Controller 1 Mailbox 18 ID0 Register */
379#define CAN1_MB18_ID1 0xffc0365c /* CAN Controller 1 Mailbox 18 ID1 Register */
380#define CAN1_MB19_DATA0 0xffc03660 /* CAN Controller 1 Mailbox 19 Data 0 Register */
381#define CAN1_MB19_DATA1 0xffc03664 /* CAN Controller 1 Mailbox 19 Data 1 Register */
382#define CAN1_MB19_DATA2 0xffc03668 /* CAN Controller 1 Mailbox 19 Data 2 Register */
383#define CAN1_MB19_DATA3 0xffc0366c /* CAN Controller 1 Mailbox 19 Data 3 Register */
384#define CAN1_MB19_LENGTH 0xffc03670 /* CAN Controller 1 Mailbox 19 Length Register */
385#define CAN1_MB19_TIMESTAMP 0xffc03674 /* CAN Controller 1 Mailbox 19 Timestamp Register */
386#define CAN1_MB19_ID0 0xffc03678 /* CAN Controller 1 Mailbox 19 ID0 Register */
387#define CAN1_MB19_ID1 0xffc0367c /* CAN Controller 1 Mailbox 19 ID1 Register */
388#define CAN1_MB20_DATA0 0xffc03680 /* CAN Controller 1 Mailbox 20 Data 0 Register */
389#define CAN1_MB20_DATA1 0xffc03684 /* CAN Controller 1 Mailbox 20 Data 1 Register */
390#define CAN1_MB20_DATA2 0xffc03688 /* CAN Controller 1 Mailbox 20 Data 2 Register */
391#define CAN1_MB20_DATA3 0xffc0368c /* CAN Controller 1 Mailbox 20 Data 3 Register */
392#define CAN1_MB20_LENGTH 0xffc03690 /* CAN Controller 1 Mailbox 20 Length Register */
393#define CAN1_MB20_TIMESTAMP 0xffc03694 /* CAN Controller 1 Mailbox 20 Timestamp Register */
394#define CAN1_MB20_ID0 0xffc03698 /* CAN Controller 1 Mailbox 20 ID0 Register */
395#define CAN1_MB20_ID1 0xffc0369c /* CAN Controller 1 Mailbox 20 ID1 Register */
396#define CAN1_MB21_DATA0 0xffc036a0 /* CAN Controller 1 Mailbox 21 Data 0 Register */
397#define CAN1_MB21_DATA1 0xffc036a4 /* CAN Controller 1 Mailbox 21 Data 1 Register */
398#define CAN1_MB21_DATA2 0xffc036a8 /* CAN Controller 1 Mailbox 21 Data 2 Register */
399#define CAN1_MB21_DATA3 0xffc036ac /* CAN Controller 1 Mailbox 21 Data 3 Register */
400#define CAN1_MB21_LENGTH 0xffc036b0 /* CAN Controller 1 Mailbox 21 Length Register */
401#define CAN1_MB21_TIMESTAMP 0xffc036b4 /* CAN Controller 1 Mailbox 21 Timestamp Register */
402#define CAN1_MB21_ID0 0xffc036b8 /* CAN Controller 1 Mailbox 21 ID0 Register */
403#define CAN1_MB21_ID1 0xffc036bc /* CAN Controller 1 Mailbox 21 ID1 Register */
404#define CAN1_MB22_DATA0 0xffc036c0 /* CAN Controller 1 Mailbox 22 Data 0 Register */
405#define CAN1_MB22_DATA1 0xffc036c4 /* CAN Controller 1 Mailbox 22 Data 1 Register */
406#define CAN1_MB22_DATA2 0xffc036c8 /* CAN Controller 1 Mailbox 22 Data 2 Register */
407#define CAN1_MB22_DATA3 0xffc036cc /* CAN Controller 1 Mailbox 22 Data 3 Register */
408#define CAN1_MB22_LENGTH 0xffc036d0 /* CAN Controller 1 Mailbox 22 Length Register */
409#define CAN1_MB22_TIMESTAMP 0xffc036d4 /* CAN Controller 1 Mailbox 22 Timestamp Register */
410#define CAN1_MB22_ID0 0xffc036d8 /* CAN Controller 1 Mailbox 22 ID0 Register */
411#define CAN1_MB22_ID1 0xffc036dc /* CAN Controller 1 Mailbox 22 ID1 Register */
412#define CAN1_MB23_DATA0 0xffc036e0 /* CAN Controller 1 Mailbox 23 Data 0 Register */
413#define CAN1_MB23_DATA1 0xffc036e4 /* CAN Controller 1 Mailbox 23 Data 1 Register */
414#define CAN1_MB23_DATA2 0xffc036e8 /* CAN Controller 1 Mailbox 23 Data 2 Register */
415#define CAN1_MB23_DATA3 0xffc036ec /* CAN Controller 1 Mailbox 23 Data 3 Register */
416#define CAN1_MB23_LENGTH 0xffc036f0 /* CAN Controller 1 Mailbox 23 Length Register */
417#define CAN1_MB23_TIMESTAMP 0xffc036f4 /* CAN Controller 1 Mailbox 23 Timestamp Register */
418#define CAN1_MB23_ID0 0xffc036f8 /* CAN Controller 1 Mailbox 23 ID0 Register */
419#define CAN1_MB23_ID1 0xffc036fc /* CAN Controller 1 Mailbox 23 ID1 Register */
420#define CAN1_MB24_DATA0 0xffc03700 /* CAN Controller 1 Mailbox 24 Data 0 Register */
421#define CAN1_MB24_DATA1 0xffc03704 /* CAN Controller 1 Mailbox 24 Data 1 Register */
422#define CAN1_MB24_DATA2 0xffc03708 /* CAN Controller 1 Mailbox 24 Data 2 Register */
423#define CAN1_MB24_DATA3 0xffc0370c /* CAN Controller 1 Mailbox 24 Data 3 Register */
424#define CAN1_MB24_LENGTH 0xffc03710 /* CAN Controller 1 Mailbox 24 Length Register */
425#define CAN1_MB24_TIMESTAMP 0xffc03714 /* CAN Controller 1 Mailbox 24 Timestamp Register */
426#define CAN1_MB24_ID0 0xffc03718 /* CAN Controller 1 Mailbox 24 ID0 Register */
427#define CAN1_MB24_ID1 0xffc0371c /* CAN Controller 1 Mailbox 24 ID1 Register */
428#define CAN1_MB25_DATA0 0xffc03720 /* CAN Controller 1 Mailbox 25 Data 0 Register */
429#define CAN1_MB25_DATA1 0xffc03724 /* CAN Controller 1 Mailbox 25 Data 1 Register */
430#define CAN1_MB25_DATA2 0xffc03728 /* CAN Controller 1 Mailbox 25 Data 2 Register */
431#define CAN1_MB25_DATA3 0xffc0372c /* CAN Controller 1 Mailbox 25 Data 3 Register */
432#define CAN1_MB25_LENGTH 0xffc03730 /* CAN Controller 1 Mailbox 25 Length Register */
433#define CAN1_MB25_TIMESTAMP 0xffc03734 /* CAN Controller 1 Mailbox 25 Timestamp Register */
434#define CAN1_MB25_ID0 0xffc03738 /* CAN Controller 1 Mailbox 25 ID0 Register */
435#define CAN1_MB25_ID1 0xffc0373c /* CAN Controller 1 Mailbox 25 ID1 Register */
436#define CAN1_MB26_DATA0 0xffc03740 /* CAN Controller 1 Mailbox 26 Data 0 Register */
437#define CAN1_MB26_DATA1 0xffc03744 /* CAN Controller 1 Mailbox 26 Data 1 Register */
438#define CAN1_MB26_DATA2 0xffc03748 /* CAN Controller 1 Mailbox 26 Data 2 Register */
439#define CAN1_MB26_DATA3 0xffc0374c /* CAN Controller 1 Mailbox 26 Data 3 Register */
440#define CAN1_MB26_LENGTH 0xffc03750 /* CAN Controller 1 Mailbox 26 Length Register */
441#define CAN1_MB26_TIMESTAMP 0xffc03754 /* CAN Controller 1 Mailbox 26 Timestamp Register */
442#define CAN1_MB26_ID0 0xffc03758 /* CAN Controller 1 Mailbox 26 ID0 Register */
443#define CAN1_MB26_ID1 0xffc0375c /* CAN Controller 1 Mailbox 26 ID1 Register */
444#define CAN1_MB27_DATA0 0xffc03760 /* CAN Controller 1 Mailbox 27 Data 0 Register */
445#define CAN1_MB27_DATA1 0xffc03764 /* CAN Controller 1 Mailbox 27 Data 1 Register */
446#define CAN1_MB27_DATA2 0xffc03768 /* CAN Controller 1 Mailbox 27 Data 2 Register */
447#define CAN1_MB27_DATA3 0xffc0376c /* CAN Controller 1 Mailbox 27 Data 3 Register */
448#define CAN1_MB27_LENGTH 0xffc03770 /* CAN Controller 1 Mailbox 27 Length Register */
449#define CAN1_MB27_TIMESTAMP 0xffc03774 /* CAN Controller 1 Mailbox 27 Timestamp Register */
450#define CAN1_MB27_ID0 0xffc03778 /* CAN Controller 1 Mailbox 27 ID0 Register */
451#define CAN1_MB27_ID1 0xffc0377c /* CAN Controller 1 Mailbox 27 ID1 Register */
452#define CAN1_MB28_DATA0 0xffc03780 /* CAN Controller 1 Mailbox 28 Data 0 Register */
453#define CAN1_MB28_DATA1 0xffc03784 /* CAN Controller 1 Mailbox 28 Data 1 Register */
454#define CAN1_MB28_DATA2 0xffc03788 /* CAN Controller 1 Mailbox 28 Data 2 Register */
455#define CAN1_MB28_DATA3 0xffc0378c /* CAN Controller 1 Mailbox 28 Data 3 Register */
456#define CAN1_MB28_LENGTH 0xffc03790 /* CAN Controller 1 Mailbox 28 Length Register */
457#define CAN1_MB28_TIMESTAMP 0xffc03794 /* CAN Controller 1 Mailbox 28 Timestamp Register */
458#define CAN1_MB28_ID0 0xffc03798 /* CAN Controller 1 Mailbox 28 ID0 Register */
459#define CAN1_MB28_ID1 0xffc0379c /* CAN Controller 1 Mailbox 28 ID1 Register */
460#define CAN1_MB29_DATA0 0xffc037a0 /* CAN Controller 1 Mailbox 29 Data 0 Register */
461#define CAN1_MB29_DATA1 0xffc037a4 /* CAN Controller 1 Mailbox 29 Data 1 Register */
462#define CAN1_MB29_DATA2 0xffc037a8 /* CAN Controller 1 Mailbox 29 Data 2 Register */
463#define CAN1_MB29_DATA3 0xffc037ac /* CAN Controller 1 Mailbox 29 Data 3 Register */
464#define CAN1_MB29_LENGTH 0xffc037b0 /* CAN Controller 1 Mailbox 29 Length Register */
465#define CAN1_MB29_TIMESTAMP 0xffc037b4 /* CAN Controller 1 Mailbox 29 Timestamp Register */
466#define CAN1_MB29_ID0 0xffc037b8 /* CAN Controller 1 Mailbox 29 ID0 Register */
467#define CAN1_MB29_ID1 0xffc037bc /* CAN Controller 1 Mailbox 29 ID1 Register */
468#define CAN1_MB30_DATA0 0xffc037c0 /* CAN Controller 1 Mailbox 30 Data 0 Register */
469#define CAN1_MB30_DATA1 0xffc037c4 /* CAN Controller 1 Mailbox 30 Data 1 Register */
470#define CAN1_MB30_DATA2 0xffc037c8 /* CAN Controller 1 Mailbox 30 Data 2 Register */
471#define CAN1_MB30_DATA3 0xffc037cc /* CAN Controller 1 Mailbox 30 Data 3 Register */
472#define CAN1_MB30_LENGTH 0xffc037d0 /* CAN Controller 1 Mailbox 30 Length Register */
473#define CAN1_MB30_TIMESTAMP 0xffc037d4 /* CAN Controller 1 Mailbox 30 Timestamp Register */
474#define CAN1_MB30_ID0 0xffc037d8 /* CAN Controller 1 Mailbox 30 ID0 Register */
475#define CAN1_MB30_ID1 0xffc037dc /* CAN Controller 1 Mailbox 30 ID1 Register */
476#define CAN1_MB31_DATA0 0xffc037e0 /* CAN Controller 1 Mailbox 31 Data 0 Register */
477#define CAN1_MB31_DATA1 0xffc037e4 /* CAN Controller 1 Mailbox 31 Data 1 Register */
478#define CAN1_MB31_DATA2 0xffc037e8 /* CAN Controller 1 Mailbox 31 Data 2 Register */
479#define CAN1_MB31_DATA3 0xffc037ec /* CAN Controller 1 Mailbox 31 Data 3 Register */
480#define CAN1_MB31_LENGTH 0xffc037f0 /* CAN Controller 1 Mailbox 31 Length Register */
481#define CAN1_MB31_TIMESTAMP 0xffc037f4 /* CAN Controller 1 Mailbox 31 Timestamp Register */
482#define CAN1_MB31_ID0 0xffc037f8 /* CAN Controller 1 Mailbox 31 ID0 Register */
483#define CAN1_MB31_ID1 0xffc037fc /* CAN Controller 1 Mailbox 31 ID1 Register */
484
485/* HOST Port Registers */
486
487#define HOST_CONTROL 0xffc03a00 /* HOST Control Register */
488#define HOST_STATUS 0xffc03a04 /* HOST Status Register */
489#define HOST_TIMEOUT 0xffc03a08 /* HOST Acknowledge Mode Timeout Register */
490
491/* Pixel Compositor (PIXC) Registers */
492
493#define PIXC_CTL 0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
494#define PIXC_PPL 0xffc04404 /* Holds the number of pixels per line of the display */
495#define PIXC_LPF 0xffc04408 /* Holds the number of lines per frame of the display */
496#define PIXC_AHSTART 0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */
497#define PIXC_AHEND 0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */
498#define PIXC_AVSTART 0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */
499#define PIXC_AVEND 0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */
500#define PIXC_ATRANSP 0xffc0441c /* Contains the transparency ratio (set A) */
501#define PIXC_BHSTART 0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */
502#define PIXC_BHEND 0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */
503#define PIXC_BVSTART 0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */
504#define PIXC_BVEND 0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */
505#define PIXC_BTRANSP 0xffc04430 /* Contains the transparency ratio (set B) */
506#define PIXC_INTRSTAT 0xffc0443c /* Overlay interrupt configuration/status */
507#define PIXC_RYCON 0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
508#define PIXC_GUCON 0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
509#define PIXC_BVCON 0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
510#define PIXC_CCBIAS 0xffc0444c /* Bias values for the color space conversion matrix */
511#define PIXC_TC 0xffc04450 /* Holds the transparent color value */
512
513/* Handshake MDMA 0 Registers */
514
515#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */
516#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */
517#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */
518#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
519#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
520#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */
521#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */
522
523/* Handshake MDMA 1 Registers */
524
525#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */
526#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */
527#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */
528#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
529#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
530#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */
531#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */
532
533
534/* ********************************************************** */
535/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
536/* and MULTI BIT READ MACROS */
537/* ********************************************************** */
538
539/* Bit masks for PIXC_CTL */
540
541#define PIXC_EN 0x1 /* Pixel Compositor Enable */
542#define OVR_A_EN 0x2 /* Overlay A Enable */
543#define OVR_B_EN 0x4 /* Overlay B Enable */
544#define IMG_FORM 0x8 /* Image Data Format */
545#define OVR_FORM 0x10 /* Overlay Data Format */
546#define OUT_FORM 0x20 /* Output Data Format */
547#define UDS_MOD 0x40 /* Resampling Mode */
548#define TC_EN 0x80 /* Transparent Color Enable */
549#define IMG_STAT 0x300 /* Image FIFO Status */
550#define OVR_STAT 0xc00 /* Overlay FIFO Status */
551#define WM_LVL 0x3000 /* FIFO Watermark Level */
552
553/* Bit masks for PIXC_AHSTART */
554
555#define A_HSTART 0xfff /* Horizontal Start Coordinates */
556
557/* Bit masks for PIXC_AHEND */
558
559#define A_HEND 0xfff /* Horizontal End Coordinates */
560
561/* Bit masks for PIXC_AVSTART */
562
563#define A_VSTART 0x3ff /* Vertical Start Coordinates */
564
565/* Bit masks for PIXC_AVEND */
566
567#define A_VEND 0x3ff /* Vertical End Coordinates */
568
569/* Bit masks for PIXC_ATRANSP */
570
571#define A_TRANSP 0xf /* Transparency Value */
572
573/* Bit masks for PIXC_BHSTART */
574
575#define B_HSTART 0xfff /* Horizontal Start Coordinates */
576
577/* Bit masks for PIXC_BHEND */
578
579#define B_HEND 0xfff /* Horizontal End Coordinates */
580
581/* Bit masks for PIXC_BVSTART */
582
583#define B_VSTART 0x3ff /* Vertical Start Coordinates */
584
585/* Bit masks for PIXC_BVEND */
586
587#define B_VEND 0x3ff /* Vertical End Coordinates */
588
589/* Bit masks for PIXC_BTRANSP */
590
591#define B_TRANSP 0xf /* Transparency Value */
592
593/* Bit masks for PIXC_INTRSTAT */
594
595#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */
596#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */
597#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */
598#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */
599
600/* Bit masks for PIXC_RYCON */
601
602#define A11 0x3ff /* A11 in the Coefficient Matrix */
603#define A12 0xffc00 /* A12 in the Coefficient Matrix */
604#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */
605#define RY_MULT4 0x40000000 /* Multiply Row by 4 */
606
607/* Bit masks for PIXC_GUCON */
608
609#define A21 0x3ff /* A21 in the Coefficient Matrix */
610#define A22 0xffc00 /* A22 in the Coefficient Matrix */
611#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */
612#define GU_MULT4 0x40000000 /* Multiply Row by 4 */
613
614/* Bit masks for PIXC_BVCON */
615
616#define A31 0x3ff /* A31 in the Coefficient Matrix */
617#define A32 0xffc00 /* A32 in the Coefficient Matrix */
618#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */
619#define BV_MULT4 0x40000000 /* Multiply Row by 4 */
620
621/* Bit masks for PIXC_CCBIAS */
622
623#define A14 0x3ff /* A14 in the Bias Vector */
624#define A24 0xffc00 /* A24 in the Bias Vector */
625#define A34 0x3ff00000 /* A34 in the Bias Vector */
626
627/* Bit masks for PIXC_TC */
628
629#define RY_TRANS 0xff /* Transparent Color - R/Y Component */
630#define GU_TRANS 0xff00 /* Transparent Color - G/U Component */
631#define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */
632
633/* Bit masks for HOST_CONTROL */
634
635#define HOST_EN 0x1 /* Host Enable */
636#define HOST_END 0x2 /* Host Endianess */
637#define DATA_SIZE 0x4 /* Data Size */
638#define HOST_RST 0x8 /* Host Reset */
639#define HRDY_OVR 0x20 /* Host Ready Override */
640#define INT_MODE 0x40 /* Interrupt Mode */
641#define BT_EN 0x80 /* Bus Timeout Enable */
642#define EHW 0x100 /* Enable Host Write */
643#define EHR 0x200 /* Enable Host Read */
644#define BDR 0x400 /* Burst DMA Requests */
645
646/* Bit masks for HOST_STATUS */
647
648#define DMA_READY 0x1 /* DMA Ready */
649#define FIFOFULL 0x2 /* FIFO Full */
650#define FIFOEMPTY 0x4 /* FIFO Empty */
651#define COMPLETE 0x8 /* DMA Complete */
652#define HSHK 0x10 /* Host Handshake */
653#define TIMEOUT 0x20 /* Host Timeout */
654#define HIRQ 0x40 /* Host Interrupt Request */
655#define ALLOW_CNFG 0x80 /* Allow New Configuration */
656#define DMA_DIR 0x100 /* DMA Direction */
657#define BTE 0x200 /* Bus Timeout Enabled */
658
659/* Bit masks for HOST_TIMEOUT */
660
661#define COUNT_TIMEOUT 0x7ff /* Host Timeout count */
662
663/* Bit masks for TIMER_ENABLE1 */
664
665#define TIMEN8 0x1 /* Timer 8 Enable */
666#define TIMEN9 0x2 /* Timer 9 Enable */
667#define TIMEN10 0x4 /* Timer 10 Enable */
668
669/* Bit masks for TIMER_DISABLE1 */
670
671#define TIMDIS8 0x1 /* Timer 8 Disable */
672#define TIMDIS9 0x2 /* Timer 9 Disable */
673#define TIMDIS10 0x4 /* Timer 10 Disable */
674
675/* Bit masks for TIMER_STATUS1 */
676
677#define TIMIL8 0x1 /* Timer 8 Interrupt */
678#define TIMIL9 0x2 /* Timer 9 Interrupt */
679#define TIMIL10 0x4 /* Timer 10 Interrupt */
680#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */
681#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */
682#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */
683#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */
684#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */
685#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */
686
687/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
688
689/* Bit masks for HMDMAx_CONTROL */
690
691#define HMDMAEN 0x1 /* Handshake MDMA Enable */
692#define REP 0x2 /* Handshake MDMA Request Polarity */
693#define UTE 0x8 /* Urgency Threshold Enable */
694#define OIE 0x10 /* Overflow Interrupt Enable */
695#define BDIE 0x20 /* Block Done Interrupt Enable */
696#define MBDI 0x40 /* Mask Block Done Interrupt */
697#define DRQ 0x300 /* Handshake MDMA Request Type */
698#define RBC 0x1000 /* Force Reload of BCOUNT */
699#define PS 0x2000 /* Pin Status */
700#define OI 0x4000 /* Overflow Interrupt Generated */
701#define BDI 0x8000 /* Block Done Interrupt Generated */
702
703/* ******************************************* */
704/* MULTI BIT MACRO ENUMERATIONS */
705/* ******************************************* */
706
707#endif /* _DEF_BF544_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF547.h b/arch/blackfin/mach-bf548/include/mach/defBF547.h
new file mode 100644
index 000000000000..661f0d877bd1
--- /dev/null
+++ b/arch/blackfin/mach-bf548/include/mach/defBF547.h
@@ -0,0 +1,1244 @@
1/*
2 * File: include/asm-blackfin/mach-bf548/defBF547.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _DEF_BF548_H
32#define _DEF_BF548_H
33
34/* Include all Core registers and bit definitions */
35#include <asm/def_LPBlackfin.h>
36
37/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */
38
39/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
40#include "defBF54x_base.h"
41
42/* The following are the #defines needed by ADSP-BF548 that are not in the common header */
43
44/* Timer Registers */
45
46#define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */
47#define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */
48#define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */
49#define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */
50#define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */
51#define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */
52#define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */
53#define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */
54#define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */
55#define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */
56#define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */
57#define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */
58
59/* Timer Group of 3 Registers */
60
61#define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */
62#define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */
63#define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */
64
65/* SPORT0 Registers */
66
67#define SPORT0_TCR1 0xffc00800 /* SPORT0 Transmit Configuration 1 Register */
68#define SPORT0_TCR2 0xffc00804 /* SPORT0 Transmit Configuration 2 Register */
69#define SPORT0_TCLKDIV 0xffc00808 /* SPORT0 Transmit Serial Clock Divider Register */
70#define SPORT0_TFSDIV 0xffc0080c /* SPORT0 Transmit Frame Sync Divider Register */
71#define SPORT0_TX 0xffc00810 /* SPORT0 Transmit Data Register */
72#define SPORT0_RX 0xffc00818 /* SPORT0 Receive Data Register */
73#define SPORT0_RCR1 0xffc00820 /* SPORT0 Receive Configuration 1 Register */
74#define SPORT0_RCR2 0xffc00824 /* SPORT0 Receive Configuration 2 Register */
75#define SPORT0_RCLKDIV 0xffc00828 /* SPORT0 Receive Serial Clock Divider Register */
76#define SPORT0_RFSDIV 0xffc0082c /* SPORT0 Receive Frame Sync Divider Register */
77#define SPORT0_STAT 0xffc00830 /* SPORT0 Status Register */
78#define SPORT0_CHNL 0xffc00834 /* SPORT0 Current Channel Register */
79#define SPORT0_MCMC1 0xffc00838 /* SPORT0 Multi channel Configuration Register 1 */
80#define SPORT0_MCMC2 0xffc0083c /* SPORT0 Multi channel Configuration Register 2 */
81#define SPORT0_MTCS0 0xffc00840 /* SPORT0 Multi channel Transmit Select Register 0 */
82#define SPORT0_MTCS1 0xffc00844 /* SPORT0 Multi channel Transmit Select Register 1 */
83#define SPORT0_MTCS2 0xffc00848 /* SPORT0 Multi channel Transmit Select Register 2 */
84#define SPORT0_MTCS3 0xffc0084c /* SPORT0 Multi channel Transmit Select Register 3 */
85#define SPORT0_MRCS0 0xffc00850 /* SPORT0 Multi channel Receive Select Register 0 */
86#define SPORT0_MRCS1 0xffc00854 /* SPORT0 Multi channel Receive Select Register 1 */
87#define SPORT0_MRCS2 0xffc00858 /* SPORT0 Multi channel Receive Select Register 2 */
88#define SPORT0_MRCS3 0xffc0085c /* SPORT0 Multi channel Receive Select Register 3 */
89
90/* EPPI0 Registers */
91
92#define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */
93#define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */
94#define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */
95#define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */
96#define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */
97#define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */
98#define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */
99#define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */
100#define EPPI0_CONTROL 0xffc01020 /* EPPI0 Control Register */
101#define EPPI0_FS1W_HBL 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
102#define EPPI0_FS1P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
103#define EPPI0_FS2W_LVB 0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
104#define EPPI0_FS2P_LAVF 0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
105#define EPPI0_CLIP 0xffc01034 /* EPPI0 Clipping Register */
106
107/* UART2 Registers */
108
109#define UART2_DLL 0xffc02100 /* Divisor Latch Low Byte */
110#define UART2_DLH 0xffc02104 /* Divisor Latch High Byte */
111#define UART2_GCTL 0xffc02108 /* Global Control Register */
112#define UART2_LCR 0xffc0210c /* Line Control Register */
113#define UART2_MCR 0xffc02110 /* Modem Control Register */
114#define UART2_LSR 0xffc02114 /* Line Status Register */
115#define UART2_MSR 0xffc02118 /* Modem Status Register */
116#define UART2_SCR 0xffc0211c /* Scratch Register */
117#define UART2_IER_SET 0xffc02120 /* Interrupt Enable Register Set */
118#define UART2_IER_CLEAR 0xffc02124 /* Interrupt Enable Register Clear */
119#define UART2_RBR 0xffc0212c /* Receive Buffer Register */
120
121/* Two Wire Interface Registers (TWI1) */
122
123#define TWI1_REGBASE 0xffc02200
124#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
125#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
126#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */
127#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */
128#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */
129#define TWI1_MASTER_CTRL 0xffc02214 /* TWI Master Mode Control Register */
130#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */
131#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */
132#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */
133#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */
134#define TWI1_FIFO_CTRL 0xffc02228 /* TWI FIFO Control Register */
135#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */
136#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */
137#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */
138#define TWI1_RCV_DATA8 0xffc02288 /* TWI FIFO Receive Data Single Byte Register */
139#define TWI1_RCV_DATA16 0xffc0228c /* TWI FIFO Receive Data Double Byte Register */
140
141/* SPI2 Registers */
142
143#define SPI2_REGBASE 0xffc02400
144#define SPI2_CTL 0xffc02400 /* SPI2 Control Register */
145#define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */
146#define SPI2_STAT 0xffc02408 /* SPI2 Status Register */
147#define SPI2_TDBR 0xffc0240c /* SPI2 Transmit Data Buffer Register */
148#define SPI2_RDBR 0xffc02410 /* SPI2 Receive Data Buffer Register */
149#define SPI2_BAUD 0xffc02414 /* SPI2 Baud Rate Register */
150#define SPI2_SHADOW 0xffc02418 /* SPI2 Receive Data Buffer Shadow Register */
151
152/* ATAPI Registers */
153
154#define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */
155#define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */
156#define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */
157#define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */
158#define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */
159#define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */
160#define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */
161#define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */
162#define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */
163#define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */
164#define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */
165#define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */
166#define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */
167#define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */
168#define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */
169#define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */
170#define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */
171#define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */
172#define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */
173#define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */
174#define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */
175#define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */
176#define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */
177#define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */
178#define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */
179
180/* SDH Registers */
181
182#define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */
183#define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */
184#define SDH_ARGUMENT 0xffc03908 /* SDH Argument */
185#define SDH_COMMAND 0xffc0390c /* SDH Command */
186#define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */
187#define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */
188#define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */
189#define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */
190#define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */
191#define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */
192#define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */
193#define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */
194#define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */
195#define SDH_STATUS 0xffc03934 /* SDH Status */
196#define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */
197#define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */
198#define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */
199#define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */
200#define SDH_FIFO 0xffc03980 /* SDH Data FIFO */
201#define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */
202#define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */
203#define SDH_CFG 0xffc039c8 /* SDH Configuration */
204#define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */
205#define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */
206#define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */
207#define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */
208#define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */
209#define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */
210#define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */
211#define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */
212#define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */
213
214/* HOST Port Registers */
215
216#define HOST_CONTROL 0xffc03a00 /* HOST Control Register */
217#define HOST_STATUS 0xffc03a04 /* HOST Status Register */
218#define HOST_TIMEOUT 0xffc03a08 /* HOST Acknowledge Mode Timeout Register */
219
220/* USB Control Registers */
221
222#define USB_FADDR 0xffc03c00 /* Function address register */
223#define USB_POWER 0xffc03c04 /* Power management register */
224#define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
225#define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */
226#define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */
227#define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */
228#define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */
229#define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */
230#define USB_FRAME 0xffc03c20 /* USB frame number */
231#define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */
232#define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */
233#define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
234#define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */
235
236/* USB Packet Control Registers */
237
238#define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */
239#define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
240#define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
241#define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */
242#define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */
243#define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
244#define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
245#define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
246#define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
247#define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
248#define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
249#define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
250#define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
251
252/* USB Endpoint FIFO Registers */
253
254#define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */
255#define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */
256#define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */
257#define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */
258#define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */
259#define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */
260#define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */
261#define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */
262
263/* USB OTG Control Registers */
264
265#define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */
266#define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */
267#define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */
268
269/* USB Phy Control Registers */
270
271#define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */
272#define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */
273#define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */
274#define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */
275#define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */
276
277/* (APHY_CNTRL is for ADI usage only) */
278
279#define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */
280
281/* (APHY_CALIB is for ADI usage only) */
282
283#define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */
284#define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
285
286/* (PHY_TEST is for ADI usage only) */
287
288#define USB_PHY_TEST 0xffc03dec /* Used for reducing simulation time and simplifies FIFO testability */
289#define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */
290#define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
291
292/* USB Endpoint 0 Control Registers */
293
294#define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */
295#define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */
296#define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */
297#define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */
298#define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */
299#define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
300#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */
301#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
302#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
303
304/* USB Endpoint 1 Control Registers */
305
306#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
307#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */
308#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */
309#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */
310#define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */
311#define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */
312#define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
313#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */
314#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
315#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
316
317/* USB Endpoint 2 Control Registers */
318
319#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
320#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */
321#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */
322#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */
323#define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */
324#define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */
325#define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
326#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */
327#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
328#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
329
330/* USB Endpoint 3 Control Registers */
331
332#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
333#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */
334#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */
335#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */
336#define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */
337#define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */
338#define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
339#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */
340#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
341#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
342
343/* USB Endpoint 4 Control Registers */
344
345#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
346#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */
347#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */
348#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */
349#define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */
350#define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */
351#define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
352#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */
353#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
354#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
355
356/* USB Endpoint 5 Control Registers */
357
358#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
359#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */
360#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */
361#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */
362#define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */
363#define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */
364#define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
365#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */
366#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
367#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
368
369/* USB Endpoint 6 Control Registers */
370
371#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
372#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */
373#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */
374#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */
375#define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */
376#define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */
377#define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
378#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */
379#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
380#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
381
382/* USB Endpoint 7 Control Registers */
383
384#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
385#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */
386#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */
387#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */
388#define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */
389#define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */
390#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
391#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */
392#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
393#define USB_EP_NI7_RXINTERVAL 0xffc03ff0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
394#define USB_EP_NI7_TXCOUNT 0xffc03ff8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
395#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */
396
397/* USB Channel 0 Config Registers */
398
399#define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */
400#define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
401#define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
402#define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
403#define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
404
405/* USB Channel 1 Config Registers */
406
407#define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */
408#define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
409#define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
410#define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
411#define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
412
413/* USB Channel 2 Config Registers */
414
415#define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */
416#define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
417#define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
418#define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
419#define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
420
421/* USB Channel 3 Config Registers */
422
423#define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */
424#define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
425#define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
426#define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
427#define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
428
429/* USB Channel 4 Config Registers */
430
431#define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */
432#define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
433#define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
434#define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
435#define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
436
437/* USB Channel 5 Config Registers */
438
439#define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */
440#define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
441#define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
442#define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
443#define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
444
445/* USB Channel 6 Config Registers */
446
447#define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */
448#define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
449#define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
450#define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
451#define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
452
453/* USB Channel 7 Config Registers */
454
455#define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */
456#define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
457#define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
458#define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
459#define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
460
461/* Keypad Registers */
462
463#define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */
464#define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */
465#define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */
466#define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */
467#define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */
468#define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */
469
470/* Pixel Compositor (PIXC) Registers */
471
472#define PIXC_CTL 0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
473#define PIXC_PPL 0xffc04404 /* Holds the number of pixels per line of the display */
474#define PIXC_LPF 0xffc04408 /* Holds the number of lines per frame of the display */
475#define PIXC_AHSTART 0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */
476#define PIXC_AHEND 0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */
477#define PIXC_AVSTART 0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */
478#define PIXC_AVEND 0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */
479#define PIXC_ATRANSP 0xffc0441c /* Contains the transparency ratio (set A) */
480#define PIXC_BHSTART 0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */
481#define PIXC_BHEND 0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */
482#define PIXC_BVSTART 0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */
483#define PIXC_BVEND 0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */
484#define PIXC_BTRANSP 0xffc04430 /* Contains the transparency ratio (set B) */
485#define PIXC_INTRSTAT 0xffc0443c /* Overlay interrupt configuration/status */
486#define PIXC_RYCON 0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
487#define PIXC_GUCON 0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
488#define PIXC_BVCON 0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
489#define PIXC_CCBIAS 0xffc0444c /* Bias values for the color space conversion matrix */
490#define PIXC_TC 0xffc04450 /* Holds the transparent color value */
491
492/* Handshake MDMA 0 Registers */
493
494#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */
495#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */
496#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */
497#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
498#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
499#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */
500#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */
501
502/* Handshake MDMA 1 Registers */
503
504#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */
505#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */
506#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */
507#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
508#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
509#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */
510#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */
511
512
513/* ********************************************************** */
514/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
515/* and MULTI BIT READ MACROS */
516/* ********************************************************** */
517
518/* Bit masks for PIXC_CTL */
519
520#define PIXC_EN 0x1 /* Pixel Compositor Enable */
521#define OVR_A_EN 0x2 /* Overlay A Enable */
522#define OVR_B_EN 0x4 /* Overlay B Enable */
523#define IMG_FORM 0x8 /* Image Data Format */
524#define OVR_FORM 0x10 /* Overlay Data Format */
525#define OUT_FORM 0x20 /* Output Data Format */
526#define UDS_MOD 0x40 /* Resampling Mode */
527#define TC_EN 0x80 /* Transparent Color Enable */
528#define IMG_STAT 0x300 /* Image FIFO Status */
529#define OVR_STAT 0xc00 /* Overlay FIFO Status */
530#define WM_LVL 0x3000 /* FIFO Watermark Level */
531
532/* Bit masks for PIXC_AHSTART */
533
534#define A_HSTART 0xfff /* Horizontal Start Coordinates */
535
536/* Bit masks for PIXC_AHEND */
537
538#define A_HEND 0xfff /* Horizontal End Coordinates */
539
540/* Bit masks for PIXC_AVSTART */
541
542#define A_VSTART 0x3ff /* Vertical Start Coordinates */
543
544/* Bit masks for PIXC_AVEND */
545
546#define A_VEND 0x3ff /* Vertical End Coordinates */
547
548/* Bit masks for PIXC_ATRANSP */
549
550#define A_TRANSP 0xf /* Transparency Value */
551
552/* Bit masks for PIXC_BHSTART */
553
554#define B_HSTART 0xfff /* Horizontal Start Coordinates */
555
556/* Bit masks for PIXC_BHEND */
557
558#define B_HEND 0xfff /* Horizontal End Coordinates */
559
560/* Bit masks for PIXC_BVSTART */
561
562#define B_VSTART 0x3ff /* Vertical Start Coordinates */
563
564/* Bit masks for PIXC_BVEND */
565
566#define B_VEND 0x3ff /* Vertical End Coordinates */
567
568/* Bit masks for PIXC_BTRANSP */
569
570#define B_TRANSP 0xf /* Transparency Value */
571
572/* Bit masks for PIXC_INTRSTAT */
573
574#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */
575#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */
576#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */
577#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */
578
579/* Bit masks for PIXC_RYCON */
580
581#define A11 0x3ff /* A11 in the Coefficient Matrix */
582#define A12 0xffc00 /* A12 in the Coefficient Matrix */
583#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */
584#define RY_MULT4 0x40000000 /* Multiply Row by 4 */
585
586/* Bit masks for PIXC_GUCON */
587
588#define A21 0x3ff /* A21 in the Coefficient Matrix */
589#define A22 0xffc00 /* A22 in the Coefficient Matrix */
590#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */
591#define GU_MULT4 0x40000000 /* Multiply Row by 4 */
592
593/* Bit masks for PIXC_BVCON */
594
595#define A31 0x3ff /* A31 in the Coefficient Matrix */
596#define A32 0xffc00 /* A32 in the Coefficient Matrix */
597#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */
598#define BV_MULT4 0x40000000 /* Multiply Row by 4 */
599
600/* Bit masks for PIXC_CCBIAS */
601
602#define A14 0x3ff /* A14 in the Bias Vector */
603#define A24 0xffc00 /* A24 in the Bias Vector */
604#define A34 0x3ff00000 /* A34 in the Bias Vector */
605
606/* Bit masks for PIXC_TC */
607
608#define RY_TRANS 0xff /* Transparent Color - R/Y Component */
609#define GU_TRANS 0xff00 /* Transparent Color - G/U Component */
610#define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */
611
612/* Bit masks for HOST_CONTROL */
613
614#define HOST_EN 0x1 /* Host Enable */
615#define HOST_END 0x2 /* Host Endianess */
616#define DATA_SIZE 0x4 /* Data Size */
617#define HOST_RST 0x8 /* Host Reset */
618#define HRDY_OVR 0x20 /* Host Ready Override */
619#define INT_MODE 0x40 /* Interrupt Mode */
620#define BT_EN 0x80 /* Bus Timeout Enable */
621#define EHW 0x100 /* Enable Host Write */
622#define EHR 0x200 /* Enable Host Read */
623#define BDR 0x400 /* Burst DMA Requests */
624
625/* Bit masks for HOST_STATUS */
626
627#define DMA_READY 0x1 /* DMA Ready */
628#define FIFOFULL 0x2 /* FIFO Full */
629#define FIFOEMPTY 0x4 /* FIFO Empty */
630#define DMA_COMPLETE 0x8 /* DMA Complete */
631#define HSHK 0x10 /* Host Handshake */
632#define HSTIMEOUT 0x20 /* Host Timeout */
633#define HIRQ 0x40 /* Host Interrupt Request */
634#define ALLOW_CNFG 0x80 /* Allow New Configuration */
635#define DMA_DIR 0x100 /* DMA Direction */
636#define BTE 0x200 /* Bus Timeout Enabled */
637
638/* Bit masks for HOST_TIMEOUT */
639
640#define COUNT_TIMEOUT 0x7ff /* Host Timeout count */
641
642/* Bit masks for KPAD_CTL */
643
644#define KPAD_EN 0x1 /* Keypad Enable */
645#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */
646#define KPAD_ROWEN 0x1c00 /* Row Enable Width */
647#define KPAD_COLEN 0xe000 /* Column Enable Width */
648
649/* Bit masks for KPAD_PRESCALE */
650
651#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */
652
653/* Bit masks for KPAD_MSEL */
654
655#define DBON_SCALE 0xff /* Debounce Scale Value */
656#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */
657
658/* Bit masks for KPAD_ROWCOL */
659
660#define KPAD_ROW 0xff /* Rows Pressed */
661#define KPAD_COL 0xff00 /* Columns Pressed */
662
663/* Bit masks for KPAD_STAT */
664
665#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */
666#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */
667#define KPAD_PRESSED 0x8 /* Key press current status */
668
669/* Bit masks for KPAD_SOFTEVAL */
670
671#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
672
673/* Bit masks for SDH_COMMAND */
674
675#define CMD_IDX 0x3f /* Command Index */
676#define CMD_RSP 0x40 /* Response */
677#define CMD_L_RSP 0x80 /* Long Response */
678#define CMD_INT_E 0x100 /* Command Interrupt */
679#define CMD_PEND_E 0x200 /* Command Pending */
680#define CMD_E 0x400 /* Command Enable */
681
682/* Bit masks for SDH_PWR_CTL */
683
684#define PWR_ON 0x3 /* Power On */
685#if 0
686#define TBD 0x3c /* TBD */
687#endif
688#define SD_CMD_OD 0x40 /* Open Drain Output */
689#define ROD_CTL 0x80 /* Rod Control */
690
691/* Bit masks for SDH_CLK_CTL */
692
693#define CLKDIV 0xff /* MC_CLK Divisor */
694#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
695#define PWR_SV_E 0x200 /* Power Save Enable */
696#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
697#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
698
699/* Bit masks for SDH_RESP_CMD */
700
701#define RESP_CMD 0x3f /* Response Command */
702
703/* Bit masks for SDH_DATA_CTL */
704
705#define DTX_E 0x1 /* Data Transfer Enable */
706#define DTX_DIR 0x2 /* Data Transfer Direction */
707#define DTX_MODE 0x4 /* Data Transfer Mode */
708#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
709#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
710
711/* Bit masks for SDH_STATUS */
712
713#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
714#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
715#define CMD_TIME_OUT 0x4 /* CMD Time Out */
716#define DAT_TIME_OUT 0x8 /* Data Time Out */
717#define TX_UNDERRUN 0x10 /* Transmit Underrun */
718#define RX_OVERRUN 0x20 /* Receive Overrun */
719#define CMD_RESP_END 0x40 /* CMD Response End */
720#define CMD_SENT 0x80 /* CMD Sent */
721#define DAT_END 0x100 /* Data End */
722#define START_BIT_ERR 0x200 /* Start Bit Error */
723#define DAT_BLK_END 0x400 /* Data Block End */
724#define CMD_ACT 0x800 /* CMD Active */
725#define TX_ACT 0x1000 /* Transmit Active */
726#define RX_ACT 0x2000 /* Receive Active */
727#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
728#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
729#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
730#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
731#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
732#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
733#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
734#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
735
736/* Bit masks for SDH_STATUS_CLR */
737
738#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
739#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
740#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
741#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
742#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
743#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
744#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
745#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
746#define DAT_END_STAT 0x100 /* Data End Status */
747#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
748#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
749
750/* Bit masks for SDH_MASK0 */
751
752#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
753#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
754#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
755#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
756#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
757#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
758#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
759#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
760#define DAT_END_MASK 0x100 /* Data End Mask */
761#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
762#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
763#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
764#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
765#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
766#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
767#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
768#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
769#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
770#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
771#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
772#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
773#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
774
775/* Bit masks for SDH_FIFO_CNT */
776
777#define FIFO_COUNT 0x7fff /* FIFO Count */
778
779/* Bit masks for SDH_E_STATUS */
780
781#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
782#define SD_CARD_DET 0x10 /* SD Card Detect */
783
784/* Bit masks for SDH_E_MASK */
785
786#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
787#define SCD_MSK 0x40 /* Mask Card Detect */
788
789/* Bit masks for SDH_CFG */
790
791#define CLKS_EN 0x1 /* Clocks Enable */
792#define SD4E 0x4 /* SDIO 4-Bit Enable */
793#define MWE 0x8 /* Moving Window Enable */
794#define SD_RST 0x10 /* SDMMC Reset */
795#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
796#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
797#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
798
799/* Bit masks for SDH_RD_WAIT_EN */
800
801#define RWR 0x1 /* Read Wait Request */
802
803/* Bit masks for ATAPI_CONTROL */
804
805#define PIO_START 0x1 /* Start PIO/Reg Op */
806#define MULTI_START 0x2 /* Start Multi-DMA Op */
807#define ULTRA_START 0x4 /* Start Ultra-DMA Op */
808#define XFER_DIR 0x8 /* Transfer Direction */
809#define IORDY_EN 0x10 /* IORDY Enable */
810#define FIFO_FLUSH 0x20 /* Flush FIFOs */
811#define SOFT_RST 0x40 /* Soft Reset */
812#define DEV_RST 0x80 /* Device Reset */
813#define TFRCNT_RST 0x100 /* Trans Count Reset */
814#define END_ON_TERM 0x200 /* End/Terminate Select */
815#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
816#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
817
818/* Bit masks for ATAPI_STATUS */
819
820#define PIO_XFER_ON 0x1 /* PIO transfer in progress */
821#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
822#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
823#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */
824
825/* Bit masks for ATAPI_DEV_ADDR */
826
827#define DEV_ADDR 0x1f /* Device Address */
828
829/* Bit masks for ATAPI_INT_MASK */
830
831#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */
832#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
833#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
834#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
835#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
836#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
837#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
838#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
839#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
840
841/* Bit masks for ATAPI_INT_STATUS */
842
843#define ATAPI_DEV_INT 0x1 /* Device interrupt status */
844#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
845#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
846#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
847#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
848#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
849#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
850#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
851#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
852
853/* Bit masks for ATAPI_LINE_STATUS */
854
855#define ATAPI_INTR 0x1 /* Device interrupt to host line status */
856#define ATAPI_DASP 0x2 /* Device dasp to host line status */
857#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
858#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
859#define ATAPI_ADDR 0x70 /* ATAPI address line status */
860#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
861#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
862#define ATAPI_DIOWN 0x200 /* ATAPI write line status */
863#define ATAPI_DIORN 0x400 /* ATAPI read line status */
864#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
865
866/* Bit masks for ATAPI_SM_STATE */
867
868#define PIO_CSTATE 0xf /* PIO mode state machine current state */
869#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */
870#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */
871#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */
872
873/* Bit masks for ATAPI_TERMINATE */
874
875#define ATAPI_HOST_TERM 0x1 /* Host terminationation */
876
877/* Bit masks for ATAPI_REG_TIM_0 */
878
879#define T2_REG 0xff /* End of cycle time for register access transfers */
880#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */
881
882/* Bit masks for ATAPI_PIO_TIM_0 */
883
884#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */
885#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */
886#define T4_REG 0xf000 /* DIOW data hold */
887
888/* Bit masks for ATAPI_PIO_TIM_1 */
889
890#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */
891
892/* Bit masks for ATAPI_MULTI_TIM_0 */
893
894#define TD 0xff /* DIOR/DIOW asserted pulsewidth */
895#define TM 0xff00 /* Time from address valid to DIOR/DIOW */
896
897/* Bit masks for ATAPI_MULTI_TIM_1 */
898
899#define TKW 0xff /* Selects DIOW negated pulsewidth */
900#define TKR 0xff00 /* Selects DIOR negated pulsewidth */
901
902/* Bit masks for ATAPI_MULTI_TIM_2 */
903
904#define TH 0xff /* Selects DIOW data hold */
905#define TEOC 0xff00 /* Selects end of cycle for DMA */
906
907/* Bit masks for ATAPI_ULTRA_TIM_0 */
908
909#define TACK 0xff /* Selects setup and hold times for TACK */
910#define TENV 0xff00 /* Selects envelope time */
911
912/* Bit masks for ATAPI_ULTRA_TIM_1 */
913
914#define TDVS 0xff /* Selects data valid setup time */
915#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */
916
917/* Bit masks for ATAPI_ULTRA_TIM_2 */
918
919#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
920#define TMLI 0xff00 /* Selects interlock time */
921
922/* Bit masks for ATAPI_ULTRA_TIM_3 */
923
924#define TZAH 0xff /* Selects minimum delay required for output */
925#define READY_PAUSE 0xff00 /* Selects ready to pause */
926
927/* Bit masks for TIMER_ENABLE1 */
928
929#define TIMEN8 0x1 /* Timer 8 Enable */
930#define TIMEN9 0x2 /* Timer 9 Enable */
931#define TIMEN10 0x4 /* Timer 10 Enable */
932
933/* Bit masks for TIMER_DISABLE1 */
934
935#define TIMDIS8 0x1 /* Timer 8 Disable */
936#define TIMDIS9 0x2 /* Timer 9 Disable */
937#define TIMDIS10 0x4 /* Timer 10 Disable */
938
939/* Bit masks for TIMER_STATUS1 */
940
941#define TIMIL8 0x1 /* Timer 8 Interrupt */
942#define TIMIL9 0x2 /* Timer 9 Interrupt */
943#define TIMIL10 0x4 /* Timer 10 Interrupt */
944#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */
945#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */
946#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */
947#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */
948#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */
949#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */
950
951/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
952
953/* Bit masks for USB_FADDR */
954
955#define FUNCTION_ADDRESS 0x7f /* Function address */
956
957/* Bit masks for USB_POWER */
958
959#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
960#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
961#define RESUME_MODE 0x4 /* DMA Mode */
962#define RESET 0x8 /* Reset indicator */
963#define HS_MODE 0x10 /* High Speed mode indicator */
964#define HS_ENABLE 0x20 /* high Speed Enable */
965#define SOFT_CONN 0x40 /* Soft connect */
966#define ISO_UPDATE 0x80 /* Isochronous update */
967
968/* Bit masks for USB_INTRTX */
969
970#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
971#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
972#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
973#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
974#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
975#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
976#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
977#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
978
979/* Bit masks for USB_INTRRX */
980
981#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
982#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
983#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
984#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
985#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
986#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
987#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
988
989/* Bit masks for USB_INTRTXE */
990
991#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
992#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
993#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
994#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
995#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
996#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
997#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
998#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
999
1000/* Bit masks for USB_INTRRXE */
1001
1002#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
1003#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
1004#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
1005#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
1006#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
1007#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
1008#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
1009
1010/* Bit masks for USB_INTRUSB */
1011
1012#define SUSPEND_B 0x1 /* Suspend indicator */
1013#define RESUME_B 0x2 /* Resume indicator */
1014#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
1015#define SOF_B 0x8 /* Start of frame */
1016#define CONN_B 0x10 /* Connection indicator */
1017#define DISCON_B 0x20 /* Disconnect indicator */
1018#define SESSION_REQ_B 0x40 /* Session Request */
1019#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
1020
1021/* Bit masks for USB_INTRUSBE */
1022
1023#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
1024#define RESUME_BE 0x2 /* Resume indicator int enable */
1025#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
1026#define SOF_BE 0x8 /* Start of frame int enable */
1027#define CONN_BE 0x10 /* Connection indicator int enable */
1028#define DISCON_BE 0x20 /* Disconnect indicator int enable */
1029#define SESSION_REQ_BE 0x40 /* Session Request int enable */
1030#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
1031
1032/* Bit masks for USB_FRAME */
1033
1034#define FRAME_NUMBER 0x7ff /* Frame number */
1035
1036/* Bit masks for USB_INDEX */
1037
1038#define SELECTED_ENDPOINT 0xf /* selected endpoint */
1039
1040/* Bit masks for USB_GLOBAL_CTL */
1041
1042#define GLOBAL_ENA 0x1 /* enables USB module */
1043#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
1044#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
1045#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
1046#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
1047#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
1048#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
1049#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
1050#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
1051#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
1052#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
1053#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
1054#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
1055#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
1056#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
1057
1058/* Bit masks for USB_OTG_DEV_CTL */
1059
1060#define SESSION 0x1 /* session indicator */
1061#define HOST_REQ 0x2 /* Host negotiation request */
1062#define HOST_MODE 0x4 /* indicates USBDRC is a host */
1063#define VBUS0 0x8 /* Vbus level indicator[0] */
1064#define VBUS1 0x10 /* Vbus level indicator[1] */
1065#define LSDEV 0x20 /* Low-speed indicator */
1066#define FSDEV 0x40 /* Full or High-speed indicator */
1067#define B_DEVICE 0x80 /* A' or 'B' device indicator */
1068
1069/* Bit masks for USB_OTG_VBUS_IRQ */
1070
1071#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
1072#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
1073#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
1074#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
1075#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
1076#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
1077
1078/* Bit masks for USB_OTG_VBUS_MASK */
1079
1080#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
1081#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
1082#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
1083#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
1084#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
1085#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
1086
1087/* Bit masks for USB_CSR0 */
1088
1089#define RXPKTRDY 0x1 /* data packet receive indicator */
1090#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
1091#define STALL_SENT 0x4 /* STALL handshake sent */
1092#define DATAEND 0x8 /* Data end indicator */
1093#define SETUPEND 0x10 /* Setup end */
1094#define SENDSTALL 0x20 /* Send STALL handshake */
1095#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
1096#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
1097#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
1098#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
1099#define SETUPPKT_H 0x8 /* send Setup token host mode */
1100#define ERROR_H 0x10 /* timeout error indicator host mode */
1101#define REQPKT_H 0x20 /* Request an IN transaction host mode */
1102#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
1103#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
1104
1105/* Bit masks for USB_COUNT0 */
1106
1107#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
1108
1109/* Bit masks for USB_NAKLIMIT0 */
1110
1111#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
1112
1113/* Bit masks for USB_TX_MAX_PACKET */
1114
1115#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
1116
1117/* Bit masks for USB_RX_MAX_PACKET */
1118
1119#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
1120
1121/* Bit masks for USB_TXCSR */
1122
1123#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
1124#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
1125#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
1126#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
1127#define STALL_SEND_T 0x10 /* issue a Stall handshake */
1128#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
1129#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
1130#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
1131#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
1132#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
1133#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
1134#define ISO_T 0x4000 /* enable Isochronous transfers */
1135#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
1136#define ERROR_TH 0x4 /* error condition host mode */
1137#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
1138#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
1139
1140/* Bit masks for USB_TXCOUNT */
1141
1142#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
1143
1144/* Bit masks for USB_RXCSR */
1145
1146#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
1147#define FIFO_FULL_R 0x2 /* FIFO not empty */
1148#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
1149#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
1150#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
1151#define STALL_SEND_R 0x20 /* issue a Stall handshake */
1152#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
1153#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
1154#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
1155#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
1156#define DISNYET_R 0x1000 /* disable Nyet handshakes */
1157#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
1158#define ISO_R 0x4000 /* enable Isochronous transfers */
1159#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
1160#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
1161#define REQPKT_RH 0x20 /* request an IN transaction host mode */
1162#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
1163#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
1164#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
1165#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
1166
1167/* Bit masks for USB_RXCOUNT */
1168
1169#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
1170
1171/* Bit masks for USB_TXTYPE */
1172
1173#define TARGET_EP_NO_T 0xf /* EP number */
1174#define PROTOCOL_T 0xc /* transfer type */
1175
1176/* Bit masks for USB_TXINTERVAL */
1177
1178#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
1179
1180/* Bit masks for USB_RXTYPE */
1181
1182#define TARGET_EP_NO_R 0xf /* EP number */
1183#define PROTOCOL_R 0xc /* transfer type */
1184
1185/* Bit masks for USB_RXINTERVAL */
1186
1187#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
1188
1189/* Bit masks for USB_DMA_INTERRUPT */
1190
1191#define DMA0_INT 0x1 /* DMA0 pending interrupt */
1192#define DMA1_INT 0x2 /* DMA1 pending interrupt */
1193#define DMA2_INT 0x4 /* DMA2 pending interrupt */
1194#define DMA3_INT 0x8 /* DMA3 pending interrupt */
1195#define DMA4_INT 0x10 /* DMA4 pending interrupt */
1196#define DMA5_INT 0x20 /* DMA5 pending interrupt */
1197#define DMA6_INT 0x40 /* DMA6 pending interrupt */
1198#define DMA7_INT 0x80 /* DMA7 pending interrupt */
1199
1200/* Bit masks for USB_DMAxCONTROL */
1201
1202#define DMA_ENA 0x1 /* DMA enable */
1203#define DIRECTION 0x2 /* direction of DMA transfer */
1204#define MODE 0x4 /* DMA Bus error */
1205#define INT_ENA 0x8 /* Interrupt enable */
1206#define EPNUM 0xf0 /* EP number */
1207#define BUSERROR 0x100 /* DMA Bus error */
1208
1209/* Bit masks for USB_DMAxADDRHIGH */
1210
1211#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
1212
1213/* Bit masks for USB_DMAxADDRLOW */
1214
1215#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
1216
1217/* Bit masks for USB_DMAxCOUNTHIGH */
1218
1219#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
1220
1221/* Bit masks for USB_DMAxCOUNTLOW */
1222
1223#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
1224
1225/* Bit masks for HMDMAx_CONTROL */
1226
1227#define HMDMAEN 0x1 /* Handshake MDMA Enable */
1228#define REP 0x2 /* Handshake MDMA Request Polarity */
1229#define UTE 0x8 /* Urgency Threshold Enable */
1230#define OIE 0x10 /* Overflow Interrupt Enable */
1231#define BDIE 0x20 /* Block Done Interrupt Enable */
1232#define MBDI 0x40 /* Mask Block Done Interrupt */
1233#define DRQ 0x300 /* Handshake MDMA Request Type */
1234#define RBC 0x1000 /* Force Reload of BCOUNT */
1235#define PS 0x2000 /* Pin Status */
1236#define OI 0x4000 /* Overflow Interrupt Generated */
1237#define BDI 0x8000 /* Block Done Interrupt Generated */
1238
1239/* ******************************************* */
1240/* MULTI BIT MACRO ENUMERATIONS */
1241/* ******************************************* */
1242
1243
1244#endif /* _DEF_BF548_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF548.h b/arch/blackfin/mach-bf548/include/mach/defBF548.h
new file mode 100644
index 000000000000..85d4bade911d
--- /dev/null
+++ b/arch/blackfin/mach-bf548/include/mach/defBF548.h
@@ -0,0 +1,1627 @@
1/*
2 * File: include/asm-blackfin/mach-bf548/defBF548.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _DEF_BF548_H
32#define _DEF_BF548_H
33
34/* Include all Core registers and bit definitions */
35#include <asm/def_LPBlackfin.h>
36
37/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */
38
39/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
40#include "defBF54x_base.h"
41
42/* The following are the #defines needed by ADSP-BF548 that are not in the common header */
43
44/* Timer Registers */
45
46#define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */
47#define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */
48#define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */
49#define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */
50#define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */
51#define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */
52#define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */
53#define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */
54#define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */
55#define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */
56#define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */
57#define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */
58
59/* Timer Group of 3 Registers */
60
61#define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */
62#define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */
63#define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */
64
65/* SPORT0 Registers */
66
67#define SPORT0_TCR1 0xffc00800 /* SPORT0 Transmit Configuration 1 Register */
68#define SPORT0_TCR2 0xffc00804 /* SPORT0 Transmit Configuration 2 Register */
69#define SPORT0_TCLKDIV 0xffc00808 /* SPORT0 Transmit Serial Clock Divider Register */
70#define SPORT0_TFSDIV 0xffc0080c /* SPORT0 Transmit Frame Sync Divider Register */
71#define SPORT0_TX 0xffc00810 /* SPORT0 Transmit Data Register */
72#define SPORT0_RX 0xffc00818 /* SPORT0 Receive Data Register */
73#define SPORT0_RCR1 0xffc00820 /* SPORT0 Receive Configuration 1 Register */
74#define SPORT0_RCR2 0xffc00824 /* SPORT0 Receive Configuration 2 Register */
75#define SPORT0_RCLKDIV 0xffc00828 /* SPORT0 Receive Serial Clock Divider Register */
76#define SPORT0_RFSDIV 0xffc0082c /* SPORT0 Receive Frame Sync Divider Register */
77#define SPORT0_STAT 0xffc00830 /* SPORT0 Status Register */
78#define SPORT0_CHNL 0xffc00834 /* SPORT0 Current Channel Register */
79#define SPORT0_MCMC1 0xffc00838 /* SPORT0 Multi channel Configuration Register 1 */
80#define SPORT0_MCMC2 0xffc0083c /* SPORT0 Multi channel Configuration Register 2 */
81#define SPORT0_MTCS0 0xffc00840 /* SPORT0 Multi channel Transmit Select Register 0 */
82#define SPORT0_MTCS1 0xffc00844 /* SPORT0 Multi channel Transmit Select Register 1 */
83#define SPORT0_MTCS2 0xffc00848 /* SPORT0 Multi channel Transmit Select Register 2 */
84#define SPORT0_MTCS3 0xffc0084c /* SPORT0 Multi channel Transmit Select Register 3 */
85#define SPORT0_MRCS0 0xffc00850 /* SPORT0 Multi channel Receive Select Register 0 */
86#define SPORT0_MRCS1 0xffc00854 /* SPORT0 Multi channel Receive Select Register 1 */
87#define SPORT0_MRCS2 0xffc00858 /* SPORT0 Multi channel Receive Select Register 2 */
88#define SPORT0_MRCS3 0xffc0085c /* SPORT0 Multi channel Receive Select Register 3 */
89
90/* EPPI0 Registers */
91
92#define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */
93#define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */
94#define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */
95#define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */
96#define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */
97#define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */
98#define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */
99#define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */
100#define EPPI0_CONTROL 0xffc01020 /* EPPI0 Control Register */
101#define EPPI0_FS1W_HBL 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
102#define EPPI0_FS1P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
103#define EPPI0_FS2W_LVB 0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
104#define EPPI0_FS2P_LAVF 0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
105#define EPPI0_CLIP 0xffc01034 /* EPPI0 Clipping Register */
106
107/* UART2 Registers */
108
109#define UART2_DLL 0xffc02100 /* Divisor Latch Low Byte */
110#define UART2_DLH 0xffc02104 /* Divisor Latch High Byte */
111#define UART2_GCTL 0xffc02108 /* Global Control Register */
112#define UART2_LCR 0xffc0210c /* Line Control Register */
113#define UART2_MCR 0xffc02110 /* Modem Control Register */
114#define UART2_LSR 0xffc02114 /* Line Status Register */
115#define UART2_MSR 0xffc02118 /* Modem Status Register */
116#define UART2_SCR 0xffc0211c /* Scratch Register */
117#define UART2_IER_SET 0xffc02120 /* Interrupt Enable Register Set */
118#define UART2_IER_CLEAR 0xffc02124 /* Interrupt Enable Register Clear */
119#define UART2_RBR 0xffc0212c /* Receive Buffer Register */
120
121/* Two Wire Interface Registers (TWI1) */
122
123#define TWI1_REGBASE 0xffc02200
124#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
125#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
126#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */
127#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */
128#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */
129#define TWI1_MASTER_CTRL 0xffc02214 /* TWI Master Mode Control Register */
130#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */
131#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */
132#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */
133#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */
134#define TWI1_FIFO_CTRL 0xffc02228 /* TWI FIFO Control Register */
135#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */
136#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */
137#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */
138#define TWI1_RCV_DATA8 0xffc02288 /* TWI FIFO Receive Data Single Byte Register */
139#define TWI1_RCV_DATA16 0xffc0228c /* TWI FIFO Receive Data Double Byte Register */
140
141/* SPI2 Registers */
142
143#define SPI2_REGBASE 0xffc02400
144#define SPI2_CTL 0xffc02400 /* SPI2 Control Register */
145#define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */
146#define SPI2_STAT 0xffc02408 /* SPI2 Status Register */
147#define SPI2_TDBR 0xffc0240c /* SPI2 Transmit Data Buffer Register */
148#define SPI2_RDBR 0xffc02410 /* SPI2 Receive Data Buffer Register */
149#define SPI2_BAUD 0xffc02414 /* SPI2 Baud Rate Register */
150#define SPI2_SHADOW 0xffc02418 /* SPI2 Receive Data Buffer Shadow Register */
151
152/* CAN Controller 1 Config 1 Registers */
153
154#define CAN1_MC1 0xffc03200 /* CAN Controller 1 Mailbox Configuration Register 1 */
155#define CAN1_MD1 0xffc03204 /* CAN Controller 1 Mailbox Direction Register 1 */
156#define CAN1_TRS1 0xffc03208 /* CAN Controller 1 Transmit Request Set Register 1 */
157#define CAN1_TRR1 0xffc0320c /* CAN Controller 1 Transmit Request Reset Register 1 */
158#define CAN1_TA1 0xffc03210 /* CAN Controller 1 Transmit Acknowledge Register 1 */
159#define CAN1_AA1 0xffc03214 /* CAN Controller 1 Abort Acknowledge Register 1 */
160#define CAN1_RMP1 0xffc03218 /* CAN Controller 1 Receive Message Pending Register 1 */
161#define CAN1_RML1 0xffc0321c /* CAN Controller 1 Receive Message Lost Register 1 */
162#define CAN1_MBTIF1 0xffc03220 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
163#define CAN1_MBRIF1 0xffc03224 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
164#define CAN1_MBIM1 0xffc03228 /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
165#define CAN1_RFH1 0xffc0322c /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
166#define CAN1_OPSS1 0xffc03230 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
167
168/* CAN Controller 1 Config 2 Registers */
169
170#define CAN1_MC2 0xffc03240 /* CAN Controller 1 Mailbox Configuration Register 2 */
171#define CAN1_MD2 0xffc03244 /* CAN Controller 1 Mailbox Direction Register 2 */
172#define CAN1_TRS2 0xffc03248 /* CAN Controller 1 Transmit Request Set Register 2 */
173#define CAN1_TRR2 0xffc0324c /* CAN Controller 1 Transmit Request Reset Register 2 */
174#define CAN1_TA2 0xffc03250 /* CAN Controller 1 Transmit Acknowledge Register 2 */
175#define CAN1_AA2 0xffc03254 /* CAN Controller 1 Abort Acknowledge Register 2 */
176#define CAN1_RMP2 0xffc03258 /* CAN Controller 1 Receive Message Pending Register 2 */
177#define CAN1_RML2 0xffc0325c /* CAN Controller 1 Receive Message Lost Register 2 */
178#define CAN1_MBTIF2 0xffc03260 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
179#define CAN1_MBRIF2 0xffc03264 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
180#define CAN1_MBIM2 0xffc03268 /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
181#define CAN1_RFH2 0xffc0326c /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
182#define CAN1_OPSS2 0xffc03270 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
183
184/* CAN Controller 1 Clock/Interrupt/Counter Registers */
185
186#define CAN1_CLOCK 0xffc03280 /* CAN Controller 1 Clock Register */
187#define CAN1_TIMING 0xffc03284 /* CAN Controller 1 Timing Register */
188#define CAN1_DEBUG 0xffc03288 /* CAN Controller 1 Debug Register */
189#define CAN1_STATUS 0xffc0328c /* CAN Controller 1 Global Status Register */
190#define CAN1_CEC 0xffc03290 /* CAN Controller 1 Error Counter Register */
191#define CAN1_GIS 0xffc03294 /* CAN Controller 1 Global Interrupt Status Register */
192#define CAN1_GIM 0xffc03298 /* CAN Controller 1 Global Interrupt Mask Register */
193#define CAN1_GIF 0xffc0329c /* CAN Controller 1 Global Interrupt Flag Register */
194#define CAN1_CONTROL 0xffc032a0 /* CAN Controller 1 Master Control Register */
195#define CAN1_INTR 0xffc032a4 /* CAN Controller 1 Interrupt Pending Register */
196#define CAN1_MBTD 0xffc032ac /* CAN Controller 1 Mailbox Temporary Disable Register */
197#define CAN1_EWR 0xffc032b0 /* CAN Controller 1 Programmable Warning Level Register */
198#define CAN1_ESR 0xffc032b4 /* CAN Controller 1 Error Status Register */
199#define CAN1_UCCNT 0xffc032c4 /* CAN Controller 1 Universal Counter Register */
200#define CAN1_UCRC 0xffc032c8 /* CAN Controller 1 Universal Counter Force Reload Register */
201#define CAN1_UCCNF 0xffc032cc /* CAN Controller 1 Universal Counter Configuration Register */
202
203/* CAN Controller 1 Mailbox Acceptance Registers */
204
205#define CAN1_AM00L 0xffc03300 /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
206#define CAN1_AM00H 0xffc03304 /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
207#define CAN1_AM01L 0xffc03308 /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
208#define CAN1_AM01H 0xffc0330c /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
209#define CAN1_AM02L 0xffc03310 /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
210#define CAN1_AM02H 0xffc03314 /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
211#define CAN1_AM03L 0xffc03318 /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
212#define CAN1_AM03H 0xffc0331c /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
213#define CAN1_AM04L 0xffc03320 /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
214#define CAN1_AM04H 0xffc03324 /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
215#define CAN1_AM05L 0xffc03328 /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
216#define CAN1_AM05H 0xffc0332c /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
217#define CAN1_AM06L 0xffc03330 /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
218#define CAN1_AM06H 0xffc03334 /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
219#define CAN1_AM07L 0xffc03338 /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
220#define CAN1_AM07H 0xffc0333c /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
221#define CAN1_AM08L 0xffc03340 /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
222#define CAN1_AM08H 0xffc03344 /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
223#define CAN1_AM09L 0xffc03348 /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
224#define CAN1_AM09H 0xffc0334c /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
225#define CAN1_AM10L 0xffc03350 /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
226#define CAN1_AM10H 0xffc03354 /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
227#define CAN1_AM11L 0xffc03358 /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
228#define CAN1_AM11H 0xffc0335c /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
229#define CAN1_AM12L 0xffc03360 /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
230#define CAN1_AM12H 0xffc03364 /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
231#define CAN1_AM13L 0xffc03368 /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
232#define CAN1_AM13H 0xffc0336c /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
233#define CAN1_AM14L 0xffc03370 /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
234#define CAN1_AM14H 0xffc03374 /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
235#define CAN1_AM15L 0xffc03378 /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
236#define CAN1_AM15H 0xffc0337c /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
237
238/* CAN Controller 1 Mailbox Acceptance Registers */
239
240#define CAN1_AM16L 0xffc03380 /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
241#define CAN1_AM16H 0xffc03384 /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
242#define CAN1_AM17L 0xffc03388 /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
243#define CAN1_AM17H 0xffc0338c /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
244#define CAN1_AM18L 0xffc03390 /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
245#define CAN1_AM18H 0xffc03394 /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
246#define CAN1_AM19L 0xffc03398 /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
247#define CAN1_AM19H 0xffc0339c /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
248#define CAN1_AM20L 0xffc033a0 /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
249#define CAN1_AM20H 0xffc033a4 /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
250#define CAN1_AM21L 0xffc033a8 /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
251#define CAN1_AM21H 0xffc033ac /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
252#define CAN1_AM22L 0xffc033b0 /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
253#define CAN1_AM22H 0xffc033b4 /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
254#define CAN1_AM23L 0xffc033b8 /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
255#define CAN1_AM23H 0xffc033bc /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
256#define CAN1_AM24L 0xffc033c0 /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
257#define CAN1_AM24H 0xffc033c4 /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
258#define CAN1_AM25L 0xffc033c8 /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
259#define CAN1_AM25H 0xffc033cc /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
260#define CAN1_AM26L 0xffc033d0 /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
261#define CAN1_AM26H 0xffc033d4 /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
262#define CAN1_AM27L 0xffc033d8 /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
263#define CAN1_AM27H 0xffc033dc /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
264#define CAN1_AM28L 0xffc033e0 /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
265#define CAN1_AM28H 0xffc033e4 /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
266#define CAN1_AM29L 0xffc033e8 /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
267#define CAN1_AM29H 0xffc033ec /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
268#define CAN1_AM30L 0xffc033f0 /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
269#define CAN1_AM30H 0xffc033f4 /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
270#define CAN1_AM31L 0xffc033f8 /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
271#define CAN1_AM31H 0xffc033fc /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
272
273/* CAN Controller 1 Mailbox Data Registers */
274
275#define CAN1_MB00_DATA0 0xffc03400 /* CAN Controller 1 Mailbox 0 Data 0 Register */
276#define CAN1_MB00_DATA1 0xffc03404 /* CAN Controller 1 Mailbox 0 Data 1 Register */
277#define CAN1_MB00_DATA2 0xffc03408 /* CAN Controller 1 Mailbox 0 Data 2 Register */
278#define CAN1_MB00_DATA3 0xffc0340c /* CAN Controller 1 Mailbox 0 Data 3 Register */
279#define CAN1_MB00_LENGTH 0xffc03410 /* CAN Controller 1 Mailbox 0 Length Register */
280#define CAN1_MB00_TIMESTAMP 0xffc03414 /* CAN Controller 1 Mailbox 0 Timestamp Register */
281#define CAN1_MB00_ID0 0xffc03418 /* CAN Controller 1 Mailbox 0 ID0 Register */
282#define CAN1_MB00_ID1 0xffc0341c /* CAN Controller 1 Mailbox 0 ID1 Register */
283#define CAN1_MB01_DATA0 0xffc03420 /* CAN Controller 1 Mailbox 1 Data 0 Register */
284#define CAN1_MB01_DATA1 0xffc03424 /* CAN Controller 1 Mailbox 1 Data 1 Register */
285#define CAN1_MB01_DATA2 0xffc03428 /* CAN Controller 1 Mailbox 1 Data 2 Register */
286#define CAN1_MB01_DATA3 0xffc0342c /* CAN Controller 1 Mailbox 1 Data 3 Register */
287#define CAN1_MB01_LENGTH 0xffc03430 /* CAN Controller 1 Mailbox 1 Length Register */
288#define CAN1_MB01_TIMESTAMP 0xffc03434 /* CAN Controller 1 Mailbox 1 Timestamp Register */
289#define CAN1_MB01_ID0 0xffc03438 /* CAN Controller 1 Mailbox 1 ID0 Register */
290#define CAN1_MB01_ID1 0xffc0343c /* CAN Controller 1 Mailbox 1 ID1 Register */
291#define CAN1_MB02_DATA0 0xffc03440 /* CAN Controller 1 Mailbox 2 Data 0 Register */
292#define CAN1_MB02_DATA1 0xffc03444 /* CAN Controller 1 Mailbox 2 Data 1 Register */
293#define CAN1_MB02_DATA2 0xffc03448 /* CAN Controller 1 Mailbox 2 Data 2 Register */
294#define CAN1_MB02_DATA3 0xffc0344c /* CAN Controller 1 Mailbox 2 Data 3 Register */
295#define CAN1_MB02_LENGTH 0xffc03450 /* CAN Controller 1 Mailbox 2 Length Register */
296#define CAN1_MB02_TIMESTAMP 0xffc03454 /* CAN Controller 1 Mailbox 2 Timestamp Register */
297#define CAN1_MB02_ID0 0xffc03458 /* CAN Controller 1 Mailbox 2 ID0 Register */
298#define CAN1_MB02_ID1 0xffc0345c /* CAN Controller 1 Mailbox 2 ID1 Register */
299#define CAN1_MB03_DATA0 0xffc03460 /* CAN Controller 1 Mailbox 3 Data 0 Register */
300#define CAN1_MB03_DATA1 0xffc03464 /* CAN Controller 1 Mailbox 3 Data 1 Register */
301#define CAN1_MB03_DATA2 0xffc03468 /* CAN Controller 1 Mailbox 3 Data 2 Register */
302#define CAN1_MB03_DATA3 0xffc0346c /* CAN Controller 1 Mailbox 3 Data 3 Register */
303#define CAN1_MB03_LENGTH 0xffc03470 /* CAN Controller 1 Mailbox 3 Length Register */
304#define CAN1_MB03_TIMESTAMP 0xffc03474 /* CAN Controller 1 Mailbox 3 Timestamp Register */
305#define CAN1_MB03_ID0 0xffc03478 /* CAN Controller 1 Mailbox 3 ID0 Register */
306#define CAN1_MB03_ID1 0xffc0347c /* CAN Controller 1 Mailbox 3 ID1 Register */
307#define CAN1_MB04_DATA0 0xffc03480 /* CAN Controller 1 Mailbox 4 Data 0 Register */
308#define CAN1_MB04_DATA1 0xffc03484 /* CAN Controller 1 Mailbox 4 Data 1 Register */
309#define CAN1_MB04_DATA2 0xffc03488 /* CAN Controller 1 Mailbox 4 Data 2 Register */
310#define CAN1_MB04_DATA3 0xffc0348c /* CAN Controller 1 Mailbox 4 Data 3 Register */
311#define CAN1_MB04_LENGTH 0xffc03490 /* CAN Controller 1 Mailbox 4 Length Register */
312#define CAN1_MB04_TIMESTAMP 0xffc03494 /* CAN Controller 1 Mailbox 4 Timestamp Register */
313#define CAN1_MB04_ID0 0xffc03498 /* CAN Controller 1 Mailbox 4 ID0 Register */
314#define CAN1_MB04_ID1 0xffc0349c /* CAN Controller 1 Mailbox 4 ID1 Register */
315#define CAN1_MB05_DATA0 0xffc034a0 /* CAN Controller 1 Mailbox 5 Data 0 Register */
316#define CAN1_MB05_DATA1 0xffc034a4 /* CAN Controller 1 Mailbox 5 Data 1 Register */
317#define CAN1_MB05_DATA2 0xffc034a8 /* CAN Controller 1 Mailbox 5 Data 2 Register */
318#define CAN1_MB05_DATA3 0xffc034ac /* CAN Controller 1 Mailbox 5 Data 3 Register */
319#define CAN1_MB05_LENGTH 0xffc034b0 /* CAN Controller 1 Mailbox 5 Length Register */
320#define CAN1_MB05_TIMESTAMP 0xffc034b4 /* CAN Controller 1 Mailbox 5 Timestamp Register */
321#define CAN1_MB05_ID0 0xffc034b8 /* CAN Controller 1 Mailbox 5 ID0 Register */
322#define CAN1_MB05_ID1 0xffc034bc /* CAN Controller 1 Mailbox 5 ID1 Register */
323#define CAN1_MB06_DATA0 0xffc034c0 /* CAN Controller 1 Mailbox 6 Data 0 Register */
324#define CAN1_MB06_DATA1 0xffc034c4 /* CAN Controller 1 Mailbox 6 Data 1 Register */
325#define CAN1_MB06_DATA2 0xffc034c8 /* CAN Controller 1 Mailbox 6 Data 2 Register */
326#define CAN1_MB06_DATA3 0xffc034cc /* CAN Controller 1 Mailbox 6 Data 3 Register */
327#define CAN1_MB06_LENGTH 0xffc034d0 /* CAN Controller 1 Mailbox 6 Length Register */
328#define CAN1_MB06_TIMESTAMP 0xffc034d4 /* CAN Controller 1 Mailbox 6 Timestamp Register */
329#define CAN1_MB06_ID0 0xffc034d8 /* CAN Controller 1 Mailbox 6 ID0 Register */
330#define CAN1_MB06_ID1 0xffc034dc /* CAN Controller 1 Mailbox 6 ID1 Register */
331#define CAN1_MB07_DATA0 0xffc034e0 /* CAN Controller 1 Mailbox 7 Data 0 Register */
332#define CAN1_MB07_DATA1 0xffc034e4 /* CAN Controller 1 Mailbox 7 Data 1 Register */
333#define CAN1_MB07_DATA2 0xffc034e8 /* CAN Controller 1 Mailbox 7 Data 2 Register */
334#define CAN1_MB07_DATA3 0xffc034ec /* CAN Controller 1 Mailbox 7 Data 3 Register */
335#define CAN1_MB07_LENGTH 0xffc034f0 /* CAN Controller 1 Mailbox 7 Length Register */
336#define CAN1_MB07_TIMESTAMP 0xffc034f4 /* CAN Controller 1 Mailbox 7 Timestamp Register */
337#define CAN1_MB07_ID0 0xffc034f8 /* CAN Controller 1 Mailbox 7 ID0 Register */
338#define CAN1_MB07_ID1 0xffc034fc /* CAN Controller 1 Mailbox 7 ID1 Register */
339#define CAN1_MB08_DATA0 0xffc03500 /* CAN Controller 1 Mailbox 8 Data 0 Register */
340#define CAN1_MB08_DATA1 0xffc03504 /* CAN Controller 1 Mailbox 8 Data 1 Register */
341#define CAN1_MB08_DATA2 0xffc03508 /* CAN Controller 1 Mailbox 8 Data 2 Register */
342#define CAN1_MB08_DATA3 0xffc0350c /* CAN Controller 1 Mailbox 8 Data 3 Register */
343#define CAN1_MB08_LENGTH 0xffc03510 /* CAN Controller 1 Mailbox 8 Length Register */
344#define CAN1_MB08_TIMESTAMP 0xffc03514 /* CAN Controller 1 Mailbox 8 Timestamp Register */
345#define CAN1_MB08_ID0 0xffc03518 /* CAN Controller 1 Mailbox 8 ID0 Register */
346#define CAN1_MB08_ID1 0xffc0351c /* CAN Controller 1 Mailbox 8 ID1 Register */
347#define CAN1_MB09_DATA0 0xffc03520 /* CAN Controller 1 Mailbox 9 Data 0 Register */
348#define CAN1_MB09_DATA1 0xffc03524 /* CAN Controller 1 Mailbox 9 Data 1 Register */
349#define CAN1_MB09_DATA2 0xffc03528 /* CAN Controller 1 Mailbox 9 Data 2 Register */
350#define CAN1_MB09_DATA3 0xffc0352c /* CAN Controller 1 Mailbox 9 Data 3 Register */
351#define CAN1_MB09_LENGTH 0xffc03530 /* CAN Controller 1 Mailbox 9 Length Register */
352#define CAN1_MB09_TIMESTAMP 0xffc03534 /* CAN Controller 1 Mailbox 9 Timestamp Register */
353#define CAN1_MB09_ID0 0xffc03538 /* CAN Controller 1 Mailbox 9 ID0 Register */
354#define CAN1_MB09_ID1 0xffc0353c /* CAN Controller 1 Mailbox 9 ID1 Register */
355#define CAN1_MB10_DATA0 0xffc03540 /* CAN Controller 1 Mailbox 10 Data 0 Register */
356#define CAN1_MB10_DATA1 0xffc03544 /* CAN Controller 1 Mailbox 10 Data 1 Register */
357#define CAN1_MB10_DATA2 0xffc03548 /* CAN Controller 1 Mailbox 10 Data 2 Register */
358#define CAN1_MB10_DATA3 0xffc0354c /* CAN Controller 1 Mailbox 10 Data 3 Register */
359#define CAN1_MB10_LENGTH 0xffc03550 /* CAN Controller 1 Mailbox 10 Length Register */
360#define CAN1_MB10_TIMESTAMP 0xffc03554 /* CAN Controller 1 Mailbox 10 Timestamp Register */
361#define CAN1_MB10_ID0 0xffc03558 /* CAN Controller 1 Mailbox 10 ID0 Register */
362#define CAN1_MB10_ID1 0xffc0355c /* CAN Controller 1 Mailbox 10 ID1 Register */
363#define CAN1_MB11_DATA0 0xffc03560 /* CAN Controller 1 Mailbox 11 Data 0 Register */
364#define CAN1_MB11_DATA1 0xffc03564 /* CAN Controller 1 Mailbox 11 Data 1 Register */
365#define CAN1_MB11_DATA2 0xffc03568 /* CAN Controller 1 Mailbox 11 Data 2 Register */
366#define CAN1_MB11_DATA3 0xffc0356c /* CAN Controller 1 Mailbox 11 Data 3 Register */
367#define CAN1_MB11_LENGTH 0xffc03570 /* CAN Controller 1 Mailbox 11 Length Register */
368#define CAN1_MB11_TIMESTAMP 0xffc03574 /* CAN Controller 1 Mailbox 11 Timestamp Register */
369#define CAN1_MB11_ID0 0xffc03578 /* CAN Controller 1 Mailbox 11 ID0 Register */
370#define CAN1_MB11_ID1 0xffc0357c /* CAN Controller 1 Mailbox 11 ID1 Register */
371#define CAN1_MB12_DATA0 0xffc03580 /* CAN Controller 1 Mailbox 12 Data 0 Register */
372#define CAN1_MB12_DATA1 0xffc03584 /* CAN Controller 1 Mailbox 12 Data 1 Register */
373#define CAN1_MB12_DATA2 0xffc03588 /* CAN Controller 1 Mailbox 12 Data 2 Register */
374#define CAN1_MB12_DATA3 0xffc0358c /* CAN Controller 1 Mailbox 12 Data 3 Register */
375#define CAN1_MB12_LENGTH 0xffc03590 /* CAN Controller 1 Mailbox 12 Length Register */
376#define CAN1_MB12_TIMESTAMP 0xffc03594 /* CAN Controller 1 Mailbox 12 Timestamp Register */
377#define CAN1_MB12_ID0 0xffc03598 /* CAN Controller 1 Mailbox 12 ID0 Register */
378#define CAN1_MB12_ID1 0xffc0359c /* CAN Controller 1 Mailbox 12 ID1 Register */
379#define CAN1_MB13_DATA0 0xffc035a0 /* CAN Controller 1 Mailbox 13 Data 0 Register */
380#define CAN1_MB13_DATA1 0xffc035a4 /* CAN Controller 1 Mailbox 13 Data 1 Register */
381#define CAN1_MB13_DATA2 0xffc035a8 /* CAN Controller 1 Mailbox 13 Data 2 Register */
382#define CAN1_MB13_DATA3 0xffc035ac /* CAN Controller 1 Mailbox 13 Data 3 Register */
383#define CAN1_MB13_LENGTH 0xffc035b0 /* CAN Controller 1 Mailbox 13 Length Register */
384#define CAN1_MB13_TIMESTAMP 0xffc035b4 /* CAN Controller 1 Mailbox 13 Timestamp Register */
385#define CAN1_MB13_ID0 0xffc035b8 /* CAN Controller 1 Mailbox 13 ID0 Register */
386#define CAN1_MB13_ID1 0xffc035bc /* CAN Controller 1 Mailbox 13 ID1 Register */
387#define CAN1_MB14_DATA0 0xffc035c0 /* CAN Controller 1 Mailbox 14 Data 0 Register */
388#define CAN1_MB14_DATA1 0xffc035c4 /* CAN Controller 1 Mailbox 14 Data 1 Register */
389#define CAN1_MB14_DATA2 0xffc035c8 /* CAN Controller 1 Mailbox 14 Data 2 Register */
390#define CAN1_MB14_DATA3 0xffc035cc /* CAN Controller 1 Mailbox 14 Data 3 Register */
391#define CAN1_MB14_LENGTH 0xffc035d0 /* CAN Controller 1 Mailbox 14 Length Register */
392#define CAN1_MB14_TIMESTAMP 0xffc035d4 /* CAN Controller 1 Mailbox 14 Timestamp Register */
393#define CAN1_MB14_ID0 0xffc035d8 /* CAN Controller 1 Mailbox 14 ID0 Register */
394#define CAN1_MB14_ID1 0xffc035dc /* CAN Controller 1 Mailbox 14 ID1 Register */
395#define CAN1_MB15_DATA0 0xffc035e0 /* CAN Controller 1 Mailbox 15 Data 0 Register */
396#define CAN1_MB15_DATA1 0xffc035e4 /* CAN Controller 1 Mailbox 15 Data 1 Register */
397#define CAN1_MB15_DATA2 0xffc035e8 /* CAN Controller 1 Mailbox 15 Data 2 Register */
398#define CAN1_MB15_DATA3 0xffc035ec /* CAN Controller 1 Mailbox 15 Data 3 Register */
399#define CAN1_MB15_LENGTH 0xffc035f0 /* CAN Controller 1 Mailbox 15 Length Register */
400#define CAN1_MB15_TIMESTAMP 0xffc035f4 /* CAN Controller 1 Mailbox 15 Timestamp Register */
401#define CAN1_MB15_ID0 0xffc035f8 /* CAN Controller 1 Mailbox 15 ID0 Register */
402#define CAN1_MB15_ID1 0xffc035fc /* CAN Controller 1 Mailbox 15 ID1 Register */
403
404/* CAN Controller 1 Mailbox Data Registers */
405
406#define CAN1_MB16_DATA0 0xffc03600 /* CAN Controller 1 Mailbox 16 Data 0 Register */
407#define CAN1_MB16_DATA1 0xffc03604 /* CAN Controller 1 Mailbox 16 Data 1 Register */
408#define CAN1_MB16_DATA2 0xffc03608 /* CAN Controller 1 Mailbox 16 Data 2 Register */
409#define CAN1_MB16_DATA3 0xffc0360c /* CAN Controller 1 Mailbox 16 Data 3 Register */
410#define CAN1_MB16_LENGTH 0xffc03610 /* CAN Controller 1 Mailbox 16 Length Register */
411#define CAN1_MB16_TIMESTAMP 0xffc03614 /* CAN Controller 1 Mailbox 16 Timestamp Register */
412#define CAN1_MB16_ID0 0xffc03618 /* CAN Controller 1 Mailbox 16 ID0 Register */
413#define CAN1_MB16_ID1 0xffc0361c /* CAN Controller 1 Mailbox 16 ID1 Register */
414#define CAN1_MB17_DATA0 0xffc03620 /* CAN Controller 1 Mailbox 17 Data 0 Register */
415#define CAN1_MB17_DATA1 0xffc03624 /* CAN Controller 1 Mailbox 17 Data 1 Register */
416#define CAN1_MB17_DATA2 0xffc03628 /* CAN Controller 1 Mailbox 17 Data 2 Register */
417#define CAN1_MB17_DATA3 0xffc0362c /* CAN Controller 1 Mailbox 17 Data 3 Register */
418#define CAN1_MB17_LENGTH 0xffc03630 /* CAN Controller 1 Mailbox 17 Length Register */
419#define CAN1_MB17_TIMESTAMP 0xffc03634 /* CAN Controller 1 Mailbox 17 Timestamp Register */
420#define CAN1_MB17_ID0 0xffc03638 /* CAN Controller 1 Mailbox 17 ID0 Register */
421#define CAN1_MB17_ID1 0xffc0363c /* CAN Controller 1 Mailbox 17 ID1 Register */
422#define CAN1_MB18_DATA0 0xffc03640 /* CAN Controller 1 Mailbox 18 Data 0 Register */
423#define CAN1_MB18_DATA1 0xffc03644 /* CAN Controller 1 Mailbox 18 Data 1 Register */
424#define CAN1_MB18_DATA2 0xffc03648 /* CAN Controller 1 Mailbox 18 Data 2 Register */
425#define CAN1_MB18_DATA3 0xffc0364c /* CAN Controller 1 Mailbox 18 Data 3 Register */
426#define CAN1_MB18_LENGTH 0xffc03650 /* CAN Controller 1 Mailbox 18 Length Register */
427#define CAN1_MB18_TIMESTAMP 0xffc03654 /* CAN Controller 1 Mailbox 18 Timestamp Register */
428#define CAN1_MB18_ID0 0xffc03658 /* CAN Controller 1 Mailbox 18 ID0 Register */
429#define CAN1_MB18_ID1 0xffc0365c /* CAN Controller 1 Mailbox 18 ID1 Register */
430#define CAN1_MB19_DATA0 0xffc03660 /* CAN Controller 1 Mailbox 19 Data 0 Register */
431#define CAN1_MB19_DATA1 0xffc03664 /* CAN Controller 1 Mailbox 19 Data 1 Register */
432#define CAN1_MB19_DATA2 0xffc03668 /* CAN Controller 1 Mailbox 19 Data 2 Register */
433#define CAN1_MB19_DATA3 0xffc0366c /* CAN Controller 1 Mailbox 19 Data 3 Register */
434#define CAN1_MB19_LENGTH 0xffc03670 /* CAN Controller 1 Mailbox 19 Length Register */
435#define CAN1_MB19_TIMESTAMP 0xffc03674 /* CAN Controller 1 Mailbox 19 Timestamp Register */
436#define CAN1_MB19_ID0 0xffc03678 /* CAN Controller 1 Mailbox 19 ID0 Register */
437#define CAN1_MB19_ID1 0xffc0367c /* CAN Controller 1 Mailbox 19 ID1 Register */
438#define CAN1_MB20_DATA0 0xffc03680 /* CAN Controller 1 Mailbox 20 Data 0 Register */
439#define CAN1_MB20_DATA1 0xffc03684 /* CAN Controller 1 Mailbox 20 Data 1 Register */
440#define CAN1_MB20_DATA2 0xffc03688 /* CAN Controller 1 Mailbox 20 Data 2 Register */
441#define CAN1_MB20_DATA3 0xffc0368c /* CAN Controller 1 Mailbox 20 Data 3 Register */
442#define CAN1_MB20_LENGTH 0xffc03690 /* CAN Controller 1 Mailbox 20 Length Register */
443#define CAN1_MB20_TIMESTAMP 0xffc03694 /* CAN Controller 1 Mailbox 20 Timestamp Register */
444#define CAN1_MB20_ID0 0xffc03698 /* CAN Controller 1 Mailbox 20 ID0 Register */
445#define CAN1_MB20_ID1 0xffc0369c /* CAN Controller 1 Mailbox 20 ID1 Register */
446#define CAN1_MB21_DATA0 0xffc036a0 /* CAN Controller 1 Mailbox 21 Data 0 Register */
447#define CAN1_MB21_DATA1 0xffc036a4 /* CAN Controller 1 Mailbox 21 Data 1 Register */
448#define CAN1_MB21_DATA2 0xffc036a8 /* CAN Controller 1 Mailbox 21 Data 2 Register */
449#define CAN1_MB21_DATA3 0xffc036ac /* CAN Controller 1 Mailbox 21 Data 3 Register */
450#define CAN1_MB21_LENGTH 0xffc036b0 /* CAN Controller 1 Mailbox 21 Length Register */
451#define CAN1_MB21_TIMESTAMP 0xffc036b4 /* CAN Controller 1 Mailbox 21 Timestamp Register */
452#define CAN1_MB21_ID0 0xffc036b8 /* CAN Controller 1 Mailbox 21 ID0 Register */
453#define CAN1_MB21_ID1 0xffc036bc /* CAN Controller 1 Mailbox 21 ID1 Register */
454#define CAN1_MB22_DATA0 0xffc036c0 /* CAN Controller 1 Mailbox 22 Data 0 Register */
455#define CAN1_MB22_DATA1 0xffc036c4 /* CAN Controller 1 Mailbox 22 Data 1 Register */
456#define CAN1_MB22_DATA2 0xffc036c8 /* CAN Controller 1 Mailbox 22 Data 2 Register */
457#define CAN1_MB22_DATA3 0xffc036cc /* CAN Controller 1 Mailbox 22 Data 3 Register */
458#define CAN1_MB22_LENGTH 0xffc036d0 /* CAN Controller 1 Mailbox 22 Length Register */
459#define CAN1_MB22_TIMESTAMP 0xffc036d4 /* CAN Controller 1 Mailbox 22 Timestamp Register */
460#define CAN1_MB22_ID0 0xffc036d8 /* CAN Controller 1 Mailbox 22 ID0 Register */
461#define CAN1_MB22_ID1 0xffc036dc /* CAN Controller 1 Mailbox 22 ID1 Register */
462#define CAN1_MB23_DATA0 0xffc036e0 /* CAN Controller 1 Mailbox 23 Data 0 Register */
463#define CAN1_MB23_DATA1 0xffc036e4 /* CAN Controller 1 Mailbox 23 Data 1 Register */
464#define CAN1_MB23_DATA2 0xffc036e8 /* CAN Controller 1 Mailbox 23 Data 2 Register */
465#define CAN1_MB23_DATA3 0xffc036ec /* CAN Controller 1 Mailbox 23 Data 3 Register */
466#define CAN1_MB23_LENGTH 0xffc036f0 /* CAN Controller 1 Mailbox 23 Length Register */
467#define CAN1_MB23_TIMESTAMP 0xffc036f4 /* CAN Controller 1 Mailbox 23 Timestamp Register */
468#define CAN1_MB23_ID0 0xffc036f8 /* CAN Controller 1 Mailbox 23 ID0 Register */
469#define CAN1_MB23_ID1 0xffc036fc /* CAN Controller 1 Mailbox 23 ID1 Register */
470#define CAN1_MB24_DATA0 0xffc03700 /* CAN Controller 1 Mailbox 24 Data 0 Register */
471#define CAN1_MB24_DATA1 0xffc03704 /* CAN Controller 1 Mailbox 24 Data 1 Register */
472#define CAN1_MB24_DATA2 0xffc03708 /* CAN Controller 1 Mailbox 24 Data 2 Register */
473#define CAN1_MB24_DATA3 0xffc0370c /* CAN Controller 1 Mailbox 24 Data 3 Register */
474#define CAN1_MB24_LENGTH 0xffc03710 /* CAN Controller 1 Mailbox 24 Length Register */
475#define CAN1_MB24_TIMESTAMP 0xffc03714 /* CAN Controller 1 Mailbox 24 Timestamp Register */
476#define CAN1_MB24_ID0 0xffc03718 /* CAN Controller 1 Mailbox 24 ID0 Register */
477#define CAN1_MB24_ID1 0xffc0371c /* CAN Controller 1 Mailbox 24 ID1 Register */
478#define CAN1_MB25_DATA0 0xffc03720 /* CAN Controller 1 Mailbox 25 Data 0 Register */
479#define CAN1_MB25_DATA1 0xffc03724 /* CAN Controller 1 Mailbox 25 Data 1 Register */
480#define CAN1_MB25_DATA2 0xffc03728 /* CAN Controller 1 Mailbox 25 Data 2 Register */
481#define CAN1_MB25_DATA3 0xffc0372c /* CAN Controller 1 Mailbox 25 Data 3 Register */
482#define CAN1_MB25_LENGTH 0xffc03730 /* CAN Controller 1 Mailbox 25 Length Register */
483#define CAN1_MB25_TIMESTAMP 0xffc03734 /* CAN Controller 1 Mailbox 25 Timestamp Register */
484#define CAN1_MB25_ID0 0xffc03738 /* CAN Controller 1 Mailbox 25 ID0 Register */
485#define CAN1_MB25_ID1 0xffc0373c /* CAN Controller 1 Mailbox 25 ID1 Register */
486#define CAN1_MB26_DATA0 0xffc03740 /* CAN Controller 1 Mailbox 26 Data 0 Register */
487#define CAN1_MB26_DATA1 0xffc03744 /* CAN Controller 1 Mailbox 26 Data 1 Register */
488#define CAN1_MB26_DATA2 0xffc03748 /* CAN Controller 1 Mailbox 26 Data 2 Register */
489#define CAN1_MB26_DATA3 0xffc0374c /* CAN Controller 1 Mailbox 26 Data 3 Register */
490#define CAN1_MB26_LENGTH 0xffc03750 /* CAN Controller 1 Mailbox 26 Length Register */
491#define CAN1_MB26_TIMESTAMP 0xffc03754 /* CAN Controller 1 Mailbox 26 Timestamp Register */
492#define CAN1_MB26_ID0 0xffc03758 /* CAN Controller 1 Mailbox 26 ID0 Register */
493#define CAN1_MB26_ID1 0xffc0375c /* CAN Controller 1 Mailbox 26 ID1 Register */
494#define CAN1_MB27_DATA0 0xffc03760 /* CAN Controller 1 Mailbox 27 Data 0 Register */
495#define CAN1_MB27_DATA1 0xffc03764 /* CAN Controller 1 Mailbox 27 Data 1 Register */
496#define CAN1_MB27_DATA2 0xffc03768 /* CAN Controller 1 Mailbox 27 Data 2 Register */
497#define CAN1_MB27_DATA3 0xffc0376c /* CAN Controller 1 Mailbox 27 Data 3 Register */
498#define CAN1_MB27_LENGTH 0xffc03770 /* CAN Controller 1 Mailbox 27 Length Register */
499#define CAN1_MB27_TIMESTAMP 0xffc03774 /* CAN Controller 1 Mailbox 27 Timestamp Register */
500#define CAN1_MB27_ID0 0xffc03778 /* CAN Controller 1 Mailbox 27 ID0 Register */
501#define CAN1_MB27_ID1 0xffc0377c /* CAN Controller 1 Mailbox 27 ID1 Register */
502#define CAN1_MB28_DATA0 0xffc03780 /* CAN Controller 1 Mailbox 28 Data 0 Register */
503#define CAN1_MB28_DATA1 0xffc03784 /* CAN Controller 1 Mailbox 28 Data 1 Register */
504#define CAN1_MB28_DATA2 0xffc03788 /* CAN Controller 1 Mailbox 28 Data 2 Register */
505#define CAN1_MB28_DATA3 0xffc0378c /* CAN Controller 1 Mailbox 28 Data 3 Register */
506#define CAN1_MB28_LENGTH 0xffc03790 /* CAN Controller 1 Mailbox 28 Length Register */
507#define CAN1_MB28_TIMESTAMP 0xffc03794 /* CAN Controller 1 Mailbox 28 Timestamp Register */
508#define CAN1_MB28_ID0 0xffc03798 /* CAN Controller 1 Mailbox 28 ID0 Register */
509#define CAN1_MB28_ID1 0xffc0379c /* CAN Controller 1 Mailbox 28 ID1 Register */
510#define CAN1_MB29_DATA0 0xffc037a0 /* CAN Controller 1 Mailbox 29 Data 0 Register */
511#define CAN1_MB29_DATA1 0xffc037a4 /* CAN Controller 1 Mailbox 29 Data 1 Register */
512#define CAN1_MB29_DATA2 0xffc037a8 /* CAN Controller 1 Mailbox 29 Data 2 Register */
513#define CAN1_MB29_DATA3 0xffc037ac /* CAN Controller 1 Mailbox 29 Data 3 Register */
514#define CAN1_MB29_LENGTH 0xffc037b0 /* CAN Controller 1 Mailbox 29 Length Register */
515#define CAN1_MB29_TIMESTAMP 0xffc037b4 /* CAN Controller 1 Mailbox 29 Timestamp Register */
516#define CAN1_MB29_ID0 0xffc037b8 /* CAN Controller 1 Mailbox 29 ID0 Register */
517#define CAN1_MB29_ID1 0xffc037bc /* CAN Controller 1 Mailbox 29 ID1 Register */
518#define CAN1_MB30_DATA0 0xffc037c0 /* CAN Controller 1 Mailbox 30 Data 0 Register */
519#define CAN1_MB30_DATA1 0xffc037c4 /* CAN Controller 1 Mailbox 30 Data 1 Register */
520#define CAN1_MB30_DATA2 0xffc037c8 /* CAN Controller 1 Mailbox 30 Data 2 Register */
521#define CAN1_MB30_DATA3 0xffc037cc /* CAN Controller 1 Mailbox 30 Data 3 Register */
522#define CAN1_MB30_LENGTH 0xffc037d0 /* CAN Controller 1 Mailbox 30 Length Register */
523#define CAN1_MB30_TIMESTAMP 0xffc037d4 /* CAN Controller 1 Mailbox 30 Timestamp Register */
524#define CAN1_MB30_ID0 0xffc037d8 /* CAN Controller 1 Mailbox 30 ID0 Register */
525#define CAN1_MB30_ID1 0xffc037dc /* CAN Controller 1 Mailbox 30 ID1 Register */
526#define CAN1_MB31_DATA0 0xffc037e0 /* CAN Controller 1 Mailbox 31 Data 0 Register */
527#define CAN1_MB31_DATA1 0xffc037e4 /* CAN Controller 1 Mailbox 31 Data 1 Register */
528#define CAN1_MB31_DATA2 0xffc037e8 /* CAN Controller 1 Mailbox 31 Data 2 Register */
529#define CAN1_MB31_DATA3 0xffc037ec /* CAN Controller 1 Mailbox 31 Data 3 Register */
530#define CAN1_MB31_LENGTH 0xffc037f0 /* CAN Controller 1 Mailbox 31 Length Register */
531#define CAN1_MB31_TIMESTAMP 0xffc037f4 /* CAN Controller 1 Mailbox 31 Timestamp Register */
532#define CAN1_MB31_ID0 0xffc037f8 /* CAN Controller 1 Mailbox 31 ID0 Register */
533#define CAN1_MB31_ID1 0xffc037fc /* CAN Controller 1 Mailbox 31 ID1 Register */
534
535/* ATAPI Registers */
536
537#define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */
538#define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */
539#define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */
540#define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */
541#define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */
542#define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */
543#define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */
544#define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */
545#define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */
546#define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */
547#define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */
548#define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */
549#define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */
550#define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */
551#define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */
552#define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */
553#define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */
554#define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */
555#define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */
556#define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */
557#define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */
558#define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */
559#define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */
560#define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */
561#define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */
562
563/* SDH Registers */
564
565#define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */
566#define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */
567#define SDH_ARGUMENT 0xffc03908 /* SDH Argument */
568#define SDH_COMMAND 0xffc0390c /* SDH Command */
569#define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */
570#define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */
571#define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */
572#define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */
573#define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */
574#define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */
575#define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */
576#define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */
577#define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */
578#define SDH_STATUS 0xffc03934 /* SDH Status */
579#define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */
580#define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */
581#define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */
582#define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */
583#define SDH_FIFO 0xffc03980 /* SDH Data FIFO */
584#define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */
585#define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */
586#define SDH_CFG 0xffc039c8 /* SDH Configuration */
587#define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */
588#define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */
589#define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */
590#define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */
591#define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */
592#define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */
593#define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */
594#define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */
595#define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */
596
597/* HOST Port Registers */
598
599#define HOST_CONTROL 0xffc03a00 /* HOST Control Register */
600#define HOST_STATUS 0xffc03a04 /* HOST Status Register */
601#define HOST_TIMEOUT 0xffc03a08 /* HOST Acknowledge Mode Timeout Register */
602
603/* USB Control Registers */
604
605#define USB_FADDR 0xffc03c00 /* Function address register */
606#define USB_POWER 0xffc03c04 /* Power management register */
607#define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
608#define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */
609#define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */
610#define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */
611#define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */
612#define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */
613#define USB_FRAME 0xffc03c20 /* USB frame number */
614#define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */
615#define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */
616#define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
617#define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */
618
619/* USB Packet Control Registers */
620
621#define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */
622#define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
623#define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
624#define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */
625#define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */
626#define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
627#define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
628#define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
629#define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
630#define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
631#define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
632#define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
633#define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
634
635/* USB Endpoint FIFO Registers */
636
637#define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */
638#define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */
639#define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */
640#define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */
641#define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */
642#define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */
643#define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */
644#define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */
645
646/* USB OTG Control Registers */
647
648#define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */
649#define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */
650#define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */
651
652/* USB Phy Control Registers */
653
654#define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */
655#define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */
656#define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */
657#define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */
658#define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */
659
660/* (APHY_CNTRL is for ADI usage only) */
661
662#define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */
663
664/* (APHY_CALIB is for ADI usage only) */
665
666#define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */
667#define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
668
669/* (PHY_TEST is for ADI usage only) */
670
671#define USB_PHY_TEST 0xffc03dec /* Used for reducing simulation time and simplifies FIFO testability */
672#define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */
673#define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
674
675/* USB Endpoint 0 Control Registers */
676
677#define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */
678#define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */
679#define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */
680#define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */
681#define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */
682#define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
683#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */
684#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
685#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
686
687/* USB Endpoint 1 Control Registers */
688
689#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
690#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */
691#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */
692#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */
693#define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */
694#define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */
695#define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
696#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */
697#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
698#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
699
700/* USB Endpoint 2 Control Registers */
701
702#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
703#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */
704#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */
705#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */
706#define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */
707#define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */
708#define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
709#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */
710#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
711#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
712
713/* USB Endpoint 3 Control Registers */
714
715#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
716#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */
717#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */
718#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */
719#define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */
720#define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */
721#define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
722#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */
723#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
724#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
725
726/* USB Endpoint 4 Control Registers */
727
728#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
729#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */
730#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */
731#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */
732#define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */
733#define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */
734#define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
735#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */
736#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
737#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
738
739/* USB Endpoint 5 Control Registers */
740
741#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
742#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */
743#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */
744#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */
745#define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */
746#define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */
747#define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
748#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */
749#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
750#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
751
752/* USB Endpoint 6 Control Registers */
753
754#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
755#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */
756#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */
757#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */
758#define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */
759#define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */
760#define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
761#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */
762#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
763#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
764
765/* USB Endpoint 7 Control Registers */
766
767#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
768#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */
769#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */
770#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */
771#define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */
772#define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */
773#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
774#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */
775#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
776#define USB_EP_NI7_RXINTERVAL 0xffc03ff0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
777#define USB_EP_NI7_TXCOUNT 0xffc03ff8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
778#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */
779
780/* USB Channel 0 Config Registers */
781
782#define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */
783#define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
784#define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
785#define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
786#define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
787
788/* USB Channel 1 Config Registers */
789
790#define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */
791#define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
792#define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
793#define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
794#define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
795
796/* USB Channel 2 Config Registers */
797
798#define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */
799#define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
800#define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
801#define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
802#define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
803
804/* USB Channel 3 Config Registers */
805
806#define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */
807#define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
808#define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
809#define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
810#define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
811
812/* USB Channel 4 Config Registers */
813
814#define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */
815#define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
816#define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
817#define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
818#define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
819
820/* USB Channel 5 Config Registers */
821
822#define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */
823#define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
824#define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
825#define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
826#define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
827
828/* USB Channel 6 Config Registers */
829
830#define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */
831#define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
832#define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
833#define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
834#define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
835
836/* USB Channel 7 Config Registers */
837
838#define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */
839#define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
840#define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
841#define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
842#define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
843
844/* Keypad Registers */
845
846#define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */
847#define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */
848#define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */
849#define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */
850#define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */
851#define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */
852
853/* Pixel Compositor (PIXC) Registers */
854
855#define PIXC_CTL 0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
856#define PIXC_PPL 0xffc04404 /* Holds the number of pixels per line of the display */
857#define PIXC_LPF 0xffc04408 /* Holds the number of lines per frame of the display */
858#define PIXC_AHSTART 0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */
859#define PIXC_AHEND 0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */
860#define PIXC_AVSTART 0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */
861#define PIXC_AVEND 0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */
862#define PIXC_ATRANSP 0xffc0441c /* Contains the transparency ratio (set A) */
863#define PIXC_BHSTART 0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */
864#define PIXC_BHEND 0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */
865#define PIXC_BVSTART 0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */
866#define PIXC_BVEND 0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */
867#define PIXC_BTRANSP 0xffc04430 /* Contains the transparency ratio (set B) */
868#define PIXC_INTRSTAT 0xffc0443c /* Overlay interrupt configuration/status */
869#define PIXC_RYCON 0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
870#define PIXC_GUCON 0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
871#define PIXC_BVCON 0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
872#define PIXC_CCBIAS 0xffc0444c /* Bias values for the color space conversion matrix */
873#define PIXC_TC 0xffc04450 /* Holds the transparent color value */
874
875/* Handshake MDMA 0 Registers */
876
877#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */
878#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */
879#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */
880#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
881#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
882#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */
883#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */
884
885/* Handshake MDMA 1 Registers */
886
887#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */
888#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */
889#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */
890#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
891#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
892#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */
893#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */
894
895
896/* ********************************************************** */
897/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
898/* and MULTI BIT READ MACROS */
899/* ********************************************************** */
900
901/* Bit masks for PIXC_CTL */
902
903#define PIXC_EN 0x1 /* Pixel Compositor Enable */
904#define OVR_A_EN 0x2 /* Overlay A Enable */
905#define OVR_B_EN 0x4 /* Overlay B Enable */
906#define IMG_FORM 0x8 /* Image Data Format */
907#define OVR_FORM 0x10 /* Overlay Data Format */
908#define OUT_FORM 0x20 /* Output Data Format */
909#define UDS_MOD 0x40 /* Resampling Mode */
910#define TC_EN 0x80 /* Transparent Color Enable */
911#define IMG_STAT 0x300 /* Image FIFO Status */
912#define OVR_STAT 0xc00 /* Overlay FIFO Status */
913#define WM_LVL 0x3000 /* FIFO Watermark Level */
914
915/* Bit masks for PIXC_AHSTART */
916
917#define A_HSTART 0xfff /* Horizontal Start Coordinates */
918
919/* Bit masks for PIXC_AHEND */
920
921#define A_HEND 0xfff /* Horizontal End Coordinates */
922
923/* Bit masks for PIXC_AVSTART */
924
925#define A_VSTART 0x3ff /* Vertical Start Coordinates */
926
927/* Bit masks for PIXC_AVEND */
928
929#define A_VEND 0x3ff /* Vertical End Coordinates */
930
931/* Bit masks for PIXC_ATRANSP */
932
933#define A_TRANSP 0xf /* Transparency Value */
934
935/* Bit masks for PIXC_BHSTART */
936
937#define B_HSTART 0xfff /* Horizontal Start Coordinates */
938
939/* Bit masks for PIXC_BHEND */
940
941#define B_HEND 0xfff /* Horizontal End Coordinates */
942
943/* Bit masks for PIXC_BVSTART */
944
945#define B_VSTART 0x3ff /* Vertical Start Coordinates */
946
947/* Bit masks for PIXC_BVEND */
948
949#define B_VEND 0x3ff /* Vertical End Coordinates */
950
951/* Bit masks for PIXC_BTRANSP */
952
953#define B_TRANSP 0xf /* Transparency Value */
954
955/* Bit masks for PIXC_INTRSTAT */
956
957#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */
958#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */
959#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */
960#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */
961
962/* Bit masks for PIXC_RYCON */
963
964#define A11 0x3ff /* A11 in the Coefficient Matrix */
965#define A12 0xffc00 /* A12 in the Coefficient Matrix */
966#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */
967#define RY_MULT4 0x40000000 /* Multiply Row by 4 */
968
969/* Bit masks for PIXC_GUCON */
970
971#define A21 0x3ff /* A21 in the Coefficient Matrix */
972#define A22 0xffc00 /* A22 in the Coefficient Matrix */
973#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */
974#define GU_MULT4 0x40000000 /* Multiply Row by 4 */
975
976/* Bit masks for PIXC_BVCON */
977
978#define A31 0x3ff /* A31 in the Coefficient Matrix */
979#define A32 0xffc00 /* A32 in the Coefficient Matrix */
980#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */
981#define BV_MULT4 0x40000000 /* Multiply Row by 4 */
982
983/* Bit masks for PIXC_CCBIAS */
984
985#define A14 0x3ff /* A14 in the Bias Vector */
986#define A24 0xffc00 /* A24 in the Bias Vector */
987#define A34 0x3ff00000 /* A34 in the Bias Vector */
988
989/* Bit masks for PIXC_TC */
990
991#define RY_TRANS 0xff /* Transparent Color - R/Y Component */
992#define GU_TRANS 0xff00 /* Transparent Color - G/U Component */
993#define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */
994
995/* Bit masks for HOST_CONTROL */
996
997#define HOST_EN 0x1 /* Host Enable */
998#define HOST_END 0x2 /* Host Endianess */
999#define DATA_SIZE 0x4 /* Data Size */
1000#define HOST_RST 0x8 /* Host Reset */
1001#define HRDY_OVR 0x20 /* Host Ready Override */
1002#define INT_MODE 0x40 /* Interrupt Mode */
1003#define BT_EN 0x80 /* Bus Timeout Enable */
1004#define EHW 0x100 /* Enable Host Write */
1005#define EHR 0x200 /* Enable Host Read */
1006#define BDR 0x400 /* Burst DMA Requests */
1007
1008/* Bit masks for HOST_STATUS */
1009
1010#define DMA_READY 0x1 /* DMA Ready */
1011#define FIFOFULL 0x2 /* FIFO Full */
1012#define FIFOEMPTY 0x4 /* FIFO Empty */
1013#define DMA_COMPLETE 0x8 /* DMA Complete */
1014#define HSHK 0x10 /* Host Handshake */
1015#define HSTIMEOUT 0x20 /* Host Timeout */
1016#define HIRQ 0x40 /* Host Interrupt Request */
1017#define ALLOW_CNFG 0x80 /* Allow New Configuration */
1018#define DMA_DIR 0x100 /* DMA Direction */
1019#define BTE 0x200 /* Bus Timeout Enabled */
1020
1021/* Bit masks for HOST_TIMEOUT */
1022
1023#define COUNT_TIMEOUT 0x7ff /* Host Timeout count */
1024
1025/* Bit masks for KPAD_CTL */
1026
1027#define KPAD_EN 0x1 /* Keypad Enable */
1028#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */
1029#define KPAD_ROWEN 0x1c00 /* Row Enable Width */
1030#define KPAD_COLEN 0xe000 /* Column Enable Width */
1031
1032/* Bit masks for KPAD_PRESCALE */
1033
1034#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */
1035
1036/* Bit masks for KPAD_MSEL */
1037
1038#define DBON_SCALE 0xff /* Debounce Scale Value */
1039#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */
1040
1041/* Bit masks for KPAD_ROWCOL */
1042
1043#define KPAD_ROW 0xff /* Rows Pressed */
1044#define KPAD_COL 0xff00 /* Columns Pressed */
1045
1046/* Bit masks for KPAD_STAT */
1047
1048#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */
1049#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */
1050#define KPAD_PRESSED 0x8 /* Key press current status */
1051
1052/* Bit masks for KPAD_SOFTEVAL */
1053
1054#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
1055
1056/* Bit masks for SDH_COMMAND */
1057
1058#define CMD_IDX 0x3f /* Command Index */
1059#define CMD_RSP 0x40 /* Response */
1060#define CMD_L_RSP 0x80 /* Long Response */
1061#define CMD_INT_E 0x100 /* Command Interrupt */
1062#define CMD_PEND_E 0x200 /* Command Pending */
1063#define CMD_E 0x400 /* Command Enable */
1064
1065/* Bit masks for SDH_PWR_CTL */
1066
1067#define PWR_ON 0x3 /* Power On */
1068#if 0
1069#define TBD 0x3c /* TBD */
1070#endif
1071#define SD_CMD_OD 0x40 /* Open Drain Output */
1072#define ROD_CTL 0x80 /* Rod Control */
1073
1074/* Bit masks for SDH_CLK_CTL */
1075
1076#define CLKDIV 0xff /* MC_CLK Divisor */
1077#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
1078#define PWR_SV_E 0x200 /* Power Save Enable */
1079#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
1080#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
1081
1082/* Bit masks for SDH_RESP_CMD */
1083
1084#define RESP_CMD 0x3f /* Response Command */
1085
1086/* Bit masks for SDH_DATA_CTL */
1087
1088#define DTX_E 0x1 /* Data Transfer Enable */
1089#define DTX_DIR 0x2 /* Data Transfer Direction */
1090#define DTX_MODE 0x4 /* Data Transfer Mode */
1091#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
1092#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
1093
1094/* Bit masks for SDH_STATUS */
1095
1096#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
1097#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
1098#define CMD_TIME_OUT 0x4 /* CMD Time Out */
1099#define DAT_TIME_OUT 0x8 /* Data Time Out */
1100#define TX_UNDERRUN 0x10 /* Transmit Underrun */
1101#define RX_OVERRUN 0x20 /* Receive Overrun */
1102#define CMD_RESP_END 0x40 /* CMD Response End */
1103#define CMD_SENT 0x80 /* CMD Sent */
1104#define DAT_END 0x100 /* Data End */
1105#define START_BIT_ERR 0x200 /* Start Bit Error */
1106#define DAT_BLK_END 0x400 /* Data Block End */
1107#define CMD_ACT 0x800 /* CMD Active */
1108#define TX_ACT 0x1000 /* Transmit Active */
1109#define RX_ACT 0x2000 /* Receive Active */
1110#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
1111#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
1112#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
1113#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
1114#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
1115#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
1116#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
1117#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
1118
1119/* Bit masks for SDH_STATUS_CLR */
1120
1121#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
1122#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
1123#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
1124#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
1125#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
1126#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
1127#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
1128#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
1129#define DAT_END_STAT 0x100 /* Data End Status */
1130#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
1131#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
1132
1133/* Bit masks for SDH_MASK0 */
1134
1135#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
1136#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
1137#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
1138#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
1139#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
1140#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
1141#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
1142#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
1143#define DAT_END_MASK 0x100 /* Data End Mask */
1144#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
1145#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
1146#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
1147#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
1148#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
1149#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
1150#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
1151#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
1152#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
1153#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
1154#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
1155#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
1156#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
1157
1158/* Bit masks for SDH_FIFO_CNT */
1159
1160#define FIFO_COUNT 0x7fff /* FIFO Count */
1161
1162/* Bit masks for SDH_E_STATUS */
1163
1164#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
1165#define SD_CARD_DET 0x10 /* SD Card Detect */
1166
1167/* Bit masks for SDH_E_MASK */
1168
1169#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
1170#define SCD_MSK 0x40 /* Mask Card Detect */
1171
1172/* Bit masks for SDH_CFG */
1173
1174#define CLKS_EN 0x1 /* Clocks Enable */
1175#define SD4E 0x4 /* SDIO 4-Bit Enable */
1176#define MWE 0x8 /* Moving Window Enable */
1177#define SD_RST 0x10 /* SDMMC Reset */
1178#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
1179#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
1180#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
1181
1182/* Bit masks for SDH_RD_WAIT_EN */
1183
1184#define RWR 0x1 /* Read Wait Request */
1185
1186/* Bit masks for ATAPI_CONTROL */
1187
1188#define PIO_START 0x1 /* Start PIO/Reg Op */
1189#define MULTI_START 0x2 /* Start Multi-DMA Op */
1190#define ULTRA_START 0x4 /* Start Ultra-DMA Op */
1191#define XFER_DIR 0x8 /* Transfer Direction */
1192#define IORDY_EN 0x10 /* IORDY Enable */
1193#define FIFO_FLUSH 0x20 /* Flush FIFOs */
1194#define SOFT_RST 0x40 /* Soft Reset */
1195#define DEV_RST 0x80 /* Device Reset */
1196#define TFRCNT_RST 0x100 /* Trans Count Reset */
1197#define END_ON_TERM 0x200 /* End/Terminate Select */
1198#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
1199#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
1200
1201/* Bit masks for ATAPI_STATUS */
1202
1203#define PIO_XFER_ON 0x1 /* PIO transfer in progress */
1204#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
1205#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
1206#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */
1207
1208/* Bit masks for ATAPI_DEV_ADDR */
1209
1210#define DEV_ADDR 0x1f /* Device Address */
1211
1212/* Bit masks for ATAPI_INT_MASK */
1213
1214#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */
1215#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
1216#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
1217#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
1218#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
1219#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
1220#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
1221#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
1222#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
1223
1224/* Bit masks for ATAPI_INT_STATUS */
1225
1226#define ATAPI_DEV_INT 0x1 /* Device interrupt status */
1227#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
1228#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
1229#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
1230#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
1231#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
1232#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
1233#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
1234#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
1235
1236/* Bit masks for ATAPI_LINE_STATUS */
1237
1238#define ATAPI_INTR 0x1 /* Device interrupt to host line status */
1239#define ATAPI_DASP 0x2 /* Device dasp to host line status */
1240#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
1241#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
1242#define ATAPI_ADDR 0x70 /* ATAPI address line status */
1243#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
1244#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
1245#define ATAPI_DIOWN 0x200 /* ATAPI write line status */
1246#define ATAPI_DIORN 0x400 /* ATAPI read line status */
1247#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
1248
1249/* Bit masks for ATAPI_SM_STATE */
1250
1251#define PIO_CSTATE 0xf /* PIO mode state machine current state */
1252#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */
1253#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */
1254#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */
1255
1256/* Bit masks for ATAPI_TERMINATE */
1257
1258#define ATAPI_HOST_TERM 0x1 /* Host terminationation */
1259
1260/* Bit masks for ATAPI_REG_TIM_0 */
1261
1262#define T2_REG 0xff /* End of cycle time for register access transfers */
1263#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */
1264
1265/* Bit masks for ATAPI_PIO_TIM_0 */
1266
1267#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */
1268#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */
1269#define T4_REG 0xf000 /* DIOW data hold */
1270
1271/* Bit masks for ATAPI_PIO_TIM_1 */
1272
1273#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */
1274
1275/* Bit masks for ATAPI_MULTI_TIM_0 */
1276
1277#define TD 0xff /* DIOR/DIOW asserted pulsewidth */
1278#define TM 0xff00 /* Time from address valid to DIOR/DIOW */
1279
1280/* Bit masks for ATAPI_MULTI_TIM_1 */
1281
1282#define TKW 0xff /* Selects DIOW negated pulsewidth */
1283#define TKR 0xff00 /* Selects DIOR negated pulsewidth */
1284
1285/* Bit masks for ATAPI_MULTI_TIM_2 */
1286
1287#define TH 0xff /* Selects DIOW data hold */
1288#define TEOC 0xff00 /* Selects end of cycle for DMA */
1289
1290/* Bit masks for ATAPI_ULTRA_TIM_0 */
1291
1292#define TACK 0xff /* Selects setup and hold times for TACK */
1293#define TENV 0xff00 /* Selects envelope time */
1294
1295/* Bit masks for ATAPI_ULTRA_TIM_1 */
1296
1297#define TDVS 0xff /* Selects data valid setup time */
1298#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */
1299
1300/* Bit masks for ATAPI_ULTRA_TIM_2 */
1301
1302#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
1303#define TMLI 0xff00 /* Selects interlock time */
1304
1305/* Bit masks for ATAPI_ULTRA_TIM_3 */
1306
1307#define TZAH 0xff /* Selects minimum delay required for output */
1308#define READY_PAUSE 0xff00 /* Selects ready to pause */
1309
1310/* Bit masks for TIMER_ENABLE1 */
1311
1312#define TIMEN8 0x1 /* Timer 8 Enable */
1313#define TIMEN9 0x2 /* Timer 9 Enable */
1314#define TIMEN10 0x4 /* Timer 10 Enable */
1315
1316/* Bit masks for TIMER_DISABLE1 */
1317
1318#define TIMDIS8 0x1 /* Timer 8 Disable */
1319#define TIMDIS9 0x2 /* Timer 9 Disable */
1320#define TIMDIS10 0x4 /* Timer 10 Disable */
1321
1322/* Bit masks for TIMER_STATUS1 */
1323
1324#define TIMIL8 0x1 /* Timer 8 Interrupt */
1325#define TIMIL9 0x2 /* Timer 9 Interrupt */
1326#define TIMIL10 0x4 /* Timer 10 Interrupt */
1327#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */
1328#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */
1329#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */
1330#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */
1331#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */
1332#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */
1333
1334/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
1335
1336/* Bit masks for USB_FADDR */
1337
1338#define FUNCTION_ADDRESS 0x7f /* Function address */
1339
1340/* Bit masks for USB_POWER */
1341
1342#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
1343#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
1344#define RESUME_MODE 0x4 /* DMA Mode */
1345#define RESET 0x8 /* Reset indicator */
1346#define HS_MODE 0x10 /* High Speed mode indicator */
1347#define HS_ENABLE 0x20 /* high Speed Enable */
1348#define SOFT_CONN 0x40 /* Soft connect */
1349#define ISO_UPDATE 0x80 /* Isochronous update */
1350
1351/* Bit masks for USB_INTRTX */
1352
1353#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
1354#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
1355#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
1356#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
1357#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
1358#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
1359#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
1360#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
1361
1362/* Bit masks for USB_INTRRX */
1363
1364#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
1365#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
1366#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
1367#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
1368#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
1369#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
1370#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
1371
1372/* Bit masks for USB_INTRTXE */
1373
1374#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
1375#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
1376#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
1377#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
1378#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
1379#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
1380#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
1381#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
1382
1383/* Bit masks for USB_INTRRXE */
1384
1385#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
1386#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
1387#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
1388#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
1389#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
1390#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
1391#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
1392
1393/* Bit masks for USB_INTRUSB */
1394
1395#define SUSPEND_B 0x1 /* Suspend indicator */
1396#define RESUME_B 0x2 /* Resume indicator */
1397#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
1398#define SOF_B 0x8 /* Start of frame */
1399#define CONN_B 0x10 /* Connection indicator */
1400#define DISCON_B 0x20 /* Disconnect indicator */
1401#define SESSION_REQ_B 0x40 /* Session Request */
1402#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
1403
1404/* Bit masks for USB_INTRUSBE */
1405
1406#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
1407#define RESUME_BE 0x2 /* Resume indicator int enable */
1408#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
1409#define SOF_BE 0x8 /* Start of frame int enable */
1410#define CONN_BE 0x10 /* Connection indicator int enable */
1411#define DISCON_BE 0x20 /* Disconnect indicator int enable */
1412#define SESSION_REQ_BE 0x40 /* Session Request int enable */
1413#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
1414
1415/* Bit masks for USB_FRAME */
1416
1417#define FRAME_NUMBER 0x7ff /* Frame number */
1418
1419/* Bit masks for USB_INDEX */
1420
1421#define SELECTED_ENDPOINT 0xf /* selected endpoint */
1422
1423/* Bit masks for USB_GLOBAL_CTL */
1424
1425#define GLOBAL_ENA 0x1 /* enables USB module */
1426#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
1427#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
1428#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
1429#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
1430#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
1431#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
1432#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
1433#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
1434#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
1435#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
1436#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
1437#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
1438#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
1439#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
1440
1441/* Bit masks for USB_OTG_DEV_CTL */
1442
1443#define SESSION 0x1 /* session indicator */
1444#define HOST_REQ 0x2 /* Host negotiation request */
1445#define HOST_MODE 0x4 /* indicates USBDRC is a host */
1446#define VBUS0 0x8 /* Vbus level indicator[0] */
1447#define VBUS1 0x10 /* Vbus level indicator[1] */
1448#define LSDEV 0x20 /* Low-speed indicator */
1449#define FSDEV 0x40 /* Full or High-speed indicator */
1450#define B_DEVICE 0x80 /* A' or 'B' device indicator */
1451
1452/* Bit masks for USB_OTG_VBUS_IRQ */
1453
1454#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
1455#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
1456#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
1457#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
1458#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
1459#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
1460
1461/* Bit masks for USB_OTG_VBUS_MASK */
1462
1463#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
1464#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
1465#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
1466#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
1467#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
1468#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
1469
1470/* Bit masks for USB_CSR0 */
1471
1472#define RXPKTRDY 0x1 /* data packet receive indicator */
1473#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
1474#define STALL_SENT 0x4 /* STALL handshake sent */
1475#define DATAEND 0x8 /* Data end indicator */
1476#define SETUPEND 0x10 /* Setup end */
1477#define SENDSTALL 0x20 /* Send STALL handshake */
1478#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
1479#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
1480#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
1481#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
1482#define SETUPPKT_H 0x8 /* send Setup token host mode */
1483#define ERROR_H 0x10 /* timeout error indicator host mode */
1484#define REQPKT_H 0x20 /* Request an IN transaction host mode */
1485#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
1486#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
1487
1488/* Bit masks for USB_COUNT0 */
1489
1490#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
1491
1492/* Bit masks for USB_NAKLIMIT0 */
1493
1494#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
1495
1496/* Bit masks for USB_TX_MAX_PACKET */
1497
1498#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
1499
1500/* Bit masks for USB_RX_MAX_PACKET */
1501
1502#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
1503
1504/* Bit masks for USB_TXCSR */
1505
1506#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
1507#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
1508#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
1509#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
1510#define STALL_SEND_T 0x10 /* issue a Stall handshake */
1511#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
1512#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
1513#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
1514#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
1515#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
1516#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
1517#define ISO_T 0x4000 /* enable Isochronous transfers */
1518#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
1519#define ERROR_TH 0x4 /* error condition host mode */
1520#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
1521#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
1522
1523/* Bit masks for USB_TXCOUNT */
1524
1525#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
1526
1527/* Bit masks for USB_RXCSR */
1528
1529#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
1530#define FIFO_FULL_R 0x2 /* FIFO not empty */
1531#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
1532#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
1533#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
1534#define STALL_SEND_R 0x20 /* issue a Stall handshake */
1535#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
1536#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
1537#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
1538#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
1539#define DISNYET_R 0x1000 /* disable Nyet handshakes */
1540#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
1541#define ISO_R 0x4000 /* enable Isochronous transfers */
1542#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
1543#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
1544#define REQPKT_RH 0x20 /* request an IN transaction host mode */
1545#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
1546#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
1547#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
1548#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
1549
1550/* Bit masks for USB_RXCOUNT */
1551
1552#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
1553
1554/* Bit masks for USB_TXTYPE */
1555
1556#define TARGET_EP_NO_T 0xf /* EP number */
1557#define PROTOCOL_T 0xc /* transfer type */
1558
1559/* Bit masks for USB_TXINTERVAL */
1560
1561#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
1562
1563/* Bit masks for USB_RXTYPE */
1564
1565#define TARGET_EP_NO_R 0xf /* EP number */
1566#define PROTOCOL_R 0xc /* transfer type */
1567
1568/* Bit masks for USB_RXINTERVAL */
1569
1570#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
1571
1572/* Bit masks for USB_DMA_INTERRUPT */
1573
1574#define DMA0_INT 0x1 /* DMA0 pending interrupt */
1575#define DMA1_INT 0x2 /* DMA1 pending interrupt */
1576#define DMA2_INT 0x4 /* DMA2 pending interrupt */
1577#define DMA3_INT 0x8 /* DMA3 pending interrupt */
1578#define DMA4_INT 0x10 /* DMA4 pending interrupt */
1579#define DMA5_INT 0x20 /* DMA5 pending interrupt */
1580#define DMA6_INT 0x40 /* DMA6 pending interrupt */
1581#define DMA7_INT 0x80 /* DMA7 pending interrupt */
1582
1583/* Bit masks for USB_DMAxCONTROL */
1584
1585#define DMA_ENA 0x1 /* DMA enable */
1586#define DIRECTION 0x2 /* direction of DMA transfer */
1587#define MODE 0x4 /* DMA Bus error */
1588#define INT_ENA 0x8 /* Interrupt enable */
1589#define EPNUM 0xf0 /* EP number */
1590#define BUSERROR 0x100 /* DMA Bus error */
1591
1592/* Bit masks for USB_DMAxADDRHIGH */
1593
1594#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
1595
1596/* Bit masks for USB_DMAxADDRLOW */
1597
1598#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
1599
1600/* Bit masks for USB_DMAxCOUNTHIGH */
1601
1602#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
1603
1604/* Bit masks for USB_DMAxCOUNTLOW */
1605
1606#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
1607
1608/* Bit masks for HMDMAx_CONTROL */
1609
1610#define HMDMAEN 0x1 /* Handshake MDMA Enable */
1611#define REP 0x2 /* Handshake MDMA Request Polarity */
1612#define UTE 0x8 /* Urgency Threshold Enable */
1613#define OIE 0x10 /* Overflow Interrupt Enable */
1614#define BDIE 0x20 /* Block Done Interrupt Enable */
1615#define MBDI 0x40 /* Mask Block Done Interrupt */
1616#define DRQ 0x300 /* Handshake MDMA Request Type */
1617#define RBC 0x1000 /* Force Reload of BCOUNT */
1618#define PS 0x2000 /* Pin Status */
1619#define OI 0x4000 /* Overflow Interrupt Generated */
1620#define BDI 0x8000 /* Block Done Interrupt Generated */
1621
1622/* ******************************************* */
1623/* MULTI BIT MACRO ENUMERATIONS */
1624/* ******************************************* */
1625
1626
1627#endif /* _DEF_BF548_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF549.h b/arch/blackfin/mach-bf548/include/mach/defBF549.h
new file mode 100644
index 000000000000..096734541644
--- /dev/null
+++ b/arch/blackfin/mach-bf548/include/mach/defBF549.h
@@ -0,0 +1,2737 @@
1/*
2 * File: include/asm-blackfin/mach-bf548/defBF549.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _DEF_BF549_H
32#define _DEF_BF549_H
33
34/* Include all Core registers and bit definitions */
35#include <asm/def_LPBlackfin.h>
36
37
38/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF549 */
39
40/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
41#include "defBF54x_base.h"
42
43/* The following are the #defines needed by ADSP-BF549 that are not in the common header */
44
45/* Timer Registers */
46
47#define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */
48#define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */
49#define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */
50#define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */
51#define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */
52#define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */
53#define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */
54#define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */
55#define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */
56#define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */
57#define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */
58#define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */
59
60/* Timer Group of 3 Registers */
61
62#define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */
63#define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */
64#define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */
65
66/* SPORT0 Registers */
67
68#define SPORT0_TCR1 0xffc00800 /* SPORT0 Transmit Configuration 1 Register */
69#define SPORT0_TCR2 0xffc00804 /* SPORT0 Transmit Configuration 2 Register */
70#define SPORT0_TCLKDIV 0xffc00808 /* SPORT0 Transmit Serial Clock Divider Register */
71#define SPORT0_TFSDIV 0xffc0080c /* SPORT0 Transmit Frame Sync Divider Register */
72#define SPORT0_TX 0xffc00810 /* SPORT0 Transmit Data Register */
73#define SPORT0_RX 0xffc00818 /* SPORT0 Receive Data Register */
74#define SPORT0_RCR1 0xffc00820 /* SPORT0 Receive Configuration 1 Register */
75#define SPORT0_RCR2 0xffc00824 /* SPORT0 Receive Configuration 2 Register */
76#define SPORT0_RCLKDIV 0xffc00828 /* SPORT0 Receive Serial Clock Divider Register */
77#define SPORT0_RFSDIV 0xffc0082c /* SPORT0 Receive Frame Sync Divider Register */
78#define SPORT0_STAT 0xffc00830 /* SPORT0 Status Register */
79#define SPORT0_CHNL 0xffc00834 /* SPORT0 Current Channel Register */
80#define SPORT0_MCMC1 0xffc00838 /* SPORT0 Multi channel Configuration Register 1 */
81#define SPORT0_MCMC2 0xffc0083c /* SPORT0 Multi channel Configuration Register 2 */
82#define SPORT0_MTCS0 0xffc00840 /* SPORT0 Multi channel Transmit Select Register 0 */
83#define SPORT0_MTCS1 0xffc00844 /* SPORT0 Multi channel Transmit Select Register 1 */
84#define SPORT0_MTCS2 0xffc00848 /* SPORT0 Multi channel Transmit Select Register 2 */
85#define SPORT0_MTCS3 0xffc0084c /* SPORT0 Multi channel Transmit Select Register 3 */
86#define SPORT0_MRCS0 0xffc00850 /* SPORT0 Multi channel Receive Select Register 0 */
87#define SPORT0_MRCS1 0xffc00854 /* SPORT0 Multi channel Receive Select Register 1 */
88#define SPORT0_MRCS2 0xffc00858 /* SPORT0 Multi channel Receive Select Register 2 */
89#define SPORT0_MRCS3 0xffc0085c /* SPORT0 Multi channel Receive Select Register 3 */
90
91/* EPPI0 Registers */
92
93#define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */
94#define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */
95#define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */
96#define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */
97#define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */
98#define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */
99#define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */
100#define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */
101#define EPPI0_CONTROL 0xffc01020 /* EPPI0 Control Register */
102#define EPPI0_FS1W_HBL 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
103#define EPPI0_FS1P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
104#define EPPI0_FS2W_LVB 0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
105#define EPPI0_FS2P_LAVF 0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
106#define EPPI0_CLIP 0xffc01034 /* EPPI0 Clipping Register */
107
108/* UART2 Registers */
109
110#define UART2_DLL 0xffc02100 /* Divisor Latch Low Byte */
111#define UART2_DLH 0xffc02104 /* Divisor Latch High Byte */
112#define UART2_GCTL 0xffc02108 /* Global Control Register */
113#define UART2_LCR 0xffc0210c /* Line Control Register */
114#define UART2_MCR 0xffc02110 /* Modem Control Register */
115#define UART2_LSR 0xffc02114 /* Line Status Register */
116#define UART2_MSR 0xffc02118 /* Modem Status Register */
117#define UART2_SCR 0xffc0211c /* Scratch Register */
118#define UART2_IER_SET 0xffc02120 /* Interrupt Enable Register Set */
119#define UART2_IER_CLEAR 0xffc02124 /* Interrupt Enable Register Clear */
120#define UART2_RBR 0xffc0212c /* Receive Buffer Register */
121
122/* Two Wire Interface Registers (TWI1) */
123
124#define TWI1_REGBASE 0xffc02200
125#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
126#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
127#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */
128#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */
129#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */
130#define TWI1_MASTER_CTRL 0xffc02214 /* TWI Master Mode Control Register */
131#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */
132#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */
133#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */
134#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */
135#define TWI1_FIFO_CTRL 0xffc02228 /* TWI FIFO Control Register */
136#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */
137#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */
138#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */
139#define TWI1_RCV_DATA8 0xffc02288 /* TWI FIFO Receive Data Single Byte Register */
140#define TWI1_RCV_DATA16 0xffc0228c /* TWI FIFO Receive Data Double Byte Register */
141
142/* SPI2 Registers */
143
144#define SPI2_REGBASE 0xffc02400
145#define SPI2_CTL 0xffc02400 /* SPI2 Control Register */
146#define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */
147#define SPI2_STAT 0xffc02408 /* SPI2 Status Register */
148#define SPI2_TDBR 0xffc0240c /* SPI2 Transmit Data Buffer Register */
149#define SPI2_RDBR 0xffc02410 /* SPI2 Receive Data Buffer Register */
150#define SPI2_BAUD 0xffc02414 /* SPI2 Baud Rate Register */
151#define SPI2_SHADOW 0xffc02418 /* SPI2 Receive Data Buffer Shadow Register */
152
153/* MXVR Registers */
154
155#define MXVR_CONFIG 0xffc02700 /* MXVR Configuration Register */
156#define MXVR_STATE_0 0xffc02708 /* MXVR State Register 0 */
157#define MXVR_STATE_1 0xffc0270c /* MXVR State Register 1 */
158#define MXVR_INT_STAT_0 0xffc02710 /* MXVR Interrupt Status Register 0 */
159#define MXVR_INT_STAT_1 0xffc02714 /* MXVR Interrupt Status Register 1 */
160#define MXVR_INT_EN_0 0xffc02718 /* MXVR Interrupt Enable Register 0 */
161#define MXVR_INT_EN_1 0xffc0271c /* MXVR Interrupt Enable Register 1 */
162#define MXVR_POSITION 0xffc02720 /* MXVR Node Position Register */
163#define MXVR_MAX_POSITION 0xffc02724 /* MXVR Maximum Node Position Register */
164#define MXVR_DELAY 0xffc02728 /* MXVR Node Frame Delay Register */
165#define MXVR_MAX_DELAY 0xffc0272c /* MXVR Maximum Node Frame Delay Register */
166#define MXVR_LADDR 0xffc02730 /* MXVR Logical Address Register */
167#define MXVR_GADDR 0xffc02734 /* MXVR Group Address Register */
168#define MXVR_AADDR 0xffc02738 /* MXVR Alternate Address Register */
169
170/* MXVR Allocation Table Registers */
171
172#define MXVR_ALLOC_0 0xffc0273c /* MXVR Allocation Table Register 0 */
173#define MXVR_ALLOC_1 0xffc02740 /* MXVR Allocation Table Register 1 */
174#define MXVR_ALLOC_2 0xffc02744 /* MXVR Allocation Table Register 2 */
175#define MXVR_ALLOC_3 0xffc02748 /* MXVR Allocation Table Register 3 */
176#define MXVR_ALLOC_4 0xffc0274c /* MXVR Allocation Table Register 4 */
177#define MXVR_ALLOC_5 0xffc02750 /* MXVR Allocation Table Register 5 */
178#define MXVR_ALLOC_6 0xffc02754 /* MXVR Allocation Table Register 6 */
179#define MXVR_ALLOC_7 0xffc02758 /* MXVR Allocation Table Register 7 */
180#define MXVR_ALLOC_8 0xffc0275c /* MXVR Allocation Table Register 8 */
181#define MXVR_ALLOC_9 0xffc02760 /* MXVR Allocation Table Register 9 */
182#define MXVR_ALLOC_10 0xffc02764 /* MXVR Allocation Table Register 10 */
183#define MXVR_ALLOC_11 0xffc02768 /* MXVR Allocation Table Register 11 */
184#define MXVR_ALLOC_12 0xffc0276c /* MXVR Allocation Table Register 12 */
185#define MXVR_ALLOC_13 0xffc02770 /* MXVR Allocation Table Register 13 */
186#define MXVR_ALLOC_14 0xffc02774 /* MXVR Allocation Table Register 14 */
187
188/* MXVR Channel Assign Registers */
189
190#define MXVR_SYNC_LCHAN_0 0xffc02778 /* MXVR Sync Data Logical Channel Assign Register 0 */
191#define MXVR_SYNC_LCHAN_1 0xffc0277c /* MXVR Sync Data Logical Channel Assign Register 1 */
192#define MXVR_SYNC_LCHAN_2 0xffc02780 /* MXVR Sync Data Logical Channel Assign Register 2 */
193#define MXVR_SYNC_LCHAN_3 0xffc02784 /* MXVR Sync Data Logical Channel Assign Register 3 */
194#define MXVR_SYNC_LCHAN_4 0xffc02788 /* MXVR Sync Data Logical Channel Assign Register 4 */
195#define MXVR_SYNC_LCHAN_5 0xffc0278c /* MXVR Sync Data Logical Channel Assign Register 5 */
196#define MXVR_SYNC_LCHAN_6 0xffc02790 /* MXVR Sync Data Logical Channel Assign Register 6 */
197#define MXVR_SYNC_LCHAN_7 0xffc02794 /* MXVR Sync Data Logical Channel Assign Register 7 */
198
199/* MXVR DMA0 Registers */
200
201#define MXVR_DMA0_CONFIG 0xffc02798 /* MXVR Sync Data DMA0 Config Register */
202#define MXVR_DMA0_START_ADDR 0xffc0279c /* MXVR Sync Data DMA0 Start Address */
203#define MXVR_DMA0_COUNT 0xffc027a0 /* MXVR Sync Data DMA0 Loop Count Register */
204#define MXVR_DMA0_CURR_ADDR 0xffc027a4 /* MXVR Sync Data DMA0 Current Address */
205#define MXVR_DMA0_CURR_COUNT 0xffc027a8 /* MXVR Sync Data DMA0 Current Loop Count */
206
207/* MXVR DMA1 Registers */
208
209#define MXVR_DMA1_CONFIG 0xffc027ac /* MXVR Sync Data DMA1 Config Register */
210#define MXVR_DMA1_START_ADDR 0xffc027b0 /* MXVR Sync Data DMA1 Start Address */
211#define MXVR_DMA1_COUNT 0xffc027b4 /* MXVR Sync Data DMA1 Loop Count Register */
212#define MXVR_DMA1_CURR_ADDR 0xffc027b8 /* MXVR Sync Data DMA1 Current Address */
213#define MXVR_DMA1_CURR_COUNT 0xffc027bc /* MXVR Sync Data DMA1 Current Loop Count */
214
215/* MXVR DMA2 Registers */
216
217#define MXVR_DMA2_CONFIG 0xffc027c0 /* MXVR Sync Data DMA2 Config Register */
218#define MXVR_DMA2_START_ADDR 0xffc027c4 /* MXVR Sync Data DMA2 Start Address */
219#define MXVR_DMA2_COUNT 0xffc027c8 /* MXVR Sync Data DMA2 Loop Count Register */
220#define MXVR_DMA2_CURR_ADDR 0xffc027cc /* MXVR Sync Data DMA2 Current Address */
221#define MXVR_DMA2_CURR_COUNT 0xffc027d0 /* MXVR Sync Data DMA2 Current Loop Count */
222
223/* MXVR DMA3 Registers */
224
225#define MXVR_DMA3_CONFIG 0xffc027d4 /* MXVR Sync Data DMA3 Config Register */
226#define MXVR_DMA3_START_ADDR 0xffc027d8 /* MXVR Sync Data DMA3 Start Address */
227#define MXVR_DMA3_COUNT 0xffc027dc /* MXVR Sync Data DMA3 Loop Count Register */
228#define MXVR_DMA3_CURR_ADDR 0xffc027e0 /* MXVR Sync Data DMA3 Current Address */
229#define MXVR_DMA3_CURR_COUNT 0xffc027e4 /* MXVR Sync Data DMA3 Current Loop Count */
230
231/* MXVR DMA4 Registers */
232
233#define MXVR_DMA4_CONFIG 0xffc027e8 /* MXVR Sync Data DMA4 Config Register */
234#define MXVR_DMA4_START_ADDR 0xffc027ec /* MXVR Sync Data DMA4 Start Address */
235#define MXVR_DMA4_COUNT 0xffc027f0 /* MXVR Sync Data DMA4 Loop Count Register */
236#define MXVR_DMA4_CURR_ADDR 0xffc027f4 /* MXVR Sync Data DMA4 Current Address */
237#define MXVR_DMA4_CURR_COUNT 0xffc027f8 /* MXVR Sync Data DMA4 Current Loop Count */
238
239/* MXVR DMA5 Registers */
240
241#define MXVR_DMA5_CONFIG 0xffc027fc /* MXVR Sync Data DMA5 Config Register */
242#define MXVR_DMA5_START_ADDR 0xffc02800 /* MXVR Sync Data DMA5 Start Address */
243#define MXVR_DMA5_COUNT 0xffc02804 /* MXVR Sync Data DMA5 Loop Count Register */
244#define MXVR_DMA5_CURR_ADDR 0xffc02808 /* MXVR Sync Data DMA5 Current Address */
245#define MXVR_DMA5_CURR_COUNT 0xffc0280c /* MXVR Sync Data DMA5 Current Loop Count */
246
247/* MXVR DMA6 Registers */
248
249#define MXVR_DMA6_CONFIG 0xffc02810 /* MXVR Sync Data DMA6 Config Register */
250#define MXVR_DMA6_START_ADDR 0xffc02814 /* MXVR Sync Data DMA6 Start Address */
251#define MXVR_DMA6_COUNT 0xffc02818 /* MXVR Sync Data DMA6 Loop Count Register */
252#define MXVR_DMA6_CURR_ADDR 0xffc0281c /* MXVR Sync Data DMA6 Current Address */
253#define MXVR_DMA6_CURR_COUNT 0xffc02820 /* MXVR Sync Data DMA6 Current Loop Count */
254
255/* MXVR DMA7 Registers */
256
257#define MXVR_DMA7_CONFIG 0xffc02824 /* MXVR Sync Data DMA7 Config Register */
258#define MXVR_DMA7_START_ADDR 0xffc02828 /* MXVR Sync Data DMA7 Start Address */
259#define MXVR_DMA7_COUNT 0xffc0282c /* MXVR Sync Data DMA7 Loop Count Register */
260#define MXVR_DMA7_CURR_ADDR 0xffc02830 /* MXVR Sync Data DMA7 Current Address */
261#define MXVR_DMA7_CURR_COUNT 0xffc02834 /* MXVR Sync Data DMA7 Current Loop Count */
262
263/* MXVR Asynch Packet Registers */
264
265#define MXVR_AP_CTL 0xffc02838 /* MXVR Async Packet Control Register */
266#define MXVR_APRB_START_ADDR 0xffc0283c /* MXVR Async Packet RX Buffer Start Addr Register */
267#define MXVR_APRB_CURR_ADDR 0xffc02840 /* MXVR Async Packet RX Buffer Current Addr Register */
268#define MXVR_APTB_START_ADDR 0xffc02844 /* MXVR Async Packet TX Buffer Start Addr Register */
269#define MXVR_APTB_CURR_ADDR 0xffc02848 /* MXVR Async Packet TX Buffer Current Addr Register */
270
271/* MXVR Control Message Registers */
272
273#define MXVR_CM_CTL 0xffc0284c /* MXVR Control Message Control Register */
274#define MXVR_CMRB_START_ADDR 0xffc02850 /* MXVR Control Message RX Buffer Start Addr Register */
275#define MXVR_CMRB_CURR_ADDR 0xffc02854 /* MXVR Control Message RX Buffer Current Address */
276#define MXVR_CMTB_START_ADDR 0xffc02858 /* MXVR Control Message TX Buffer Start Addr Register */
277#define MXVR_CMTB_CURR_ADDR 0xffc0285c /* MXVR Control Message TX Buffer Current Address */
278
279/* MXVR Remote Read Registers */
280
281#define MXVR_RRDB_START_ADDR 0xffc02860 /* MXVR Remote Read Buffer Start Addr Register */
282#define MXVR_RRDB_CURR_ADDR 0xffc02864 /* MXVR Remote Read Buffer Current Addr Register */
283
284/* MXVR Pattern Data Registers */
285
286#define MXVR_PAT_DATA_0 0xffc02868 /* MXVR Pattern Data Register 0 */
287#define MXVR_PAT_EN_0 0xffc0286c /* MXVR Pattern Enable Register 0 */
288#define MXVR_PAT_DATA_1 0xffc02870 /* MXVR Pattern Data Register 1 */
289#define MXVR_PAT_EN_1 0xffc02874 /* MXVR Pattern Enable Register 1 */
290
291/* MXVR Frame Counter Registers */
292
293#define MXVR_FRAME_CNT_0 0xffc02878 /* MXVR Frame Counter 0 */
294#define MXVR_FRAME_CNT_1 0xffc0287c /* MXVR Frame Counter 1 */
295
296/* MXVR Routing Table Registers */
297
298#define MXVR_ROUTING_0 0xffc02880 /* MXVR Routing Table Register 0 */
299#define MXVR_ROUTING_1 0xffc02884 /* MXVR Routing Table Register 1 */
300#define MXVR_ROUTING_2 0xffc02888 /* MXVR Routing Table Register 2 */
301#define MXVR_ROUTING_3 0xffc0288c /* MXVR Routing Table Register 3 */
302#define MXVR_ROUTING_4 0xffc02890 /* MXVR Routing Table Register 4 */
303#define MXVR_ROUTING_5 0xffc02894 /* MXVR Routing Table Register 5 */
304#define MXVR_ROUTING_6 0xffc02898 /* MXVR Routing Table Register 6 */
305#define MXVR_ROUTING_7 0xffc0289c /* MXVR Routing Table Register 7 */
306#define MXVR_ROUTING_8 0xffc028a0 /* MXVR Routing Table Register 8 */
307#define MXVR_ROUTING_9 0xffc028a4 /* MXVR Routing Table Register 9 */
308#define MXVR_ROUTING_10 0xffc028a8 /* MXVR Routing Table Register 10 */
309#define MXVR_ROUTING_11 0xffc028ac /* MXVR Routing Table Register 11 */
310#define MXVR_ROUTING_12 0xffc028b0 /* MXVR Routing Table Register 12 */
311#define MXVR_ROUTING_13 0xffc028b4 /* MXVR Routing Table Register 13 */
312#define MXVR_ROUTING_14 0xffc028b8 /* MXVR Routing Table Register 14 */
313
314/* MXVR Counter-Clock-Control Registers */
315
316#define MXVR_BLOCK_CNT 0xffc028c0 /* MXVR Block Counter */
317#define MXVR_CLK_CTL 0xffc028d0 /* MXVR Clock Control Register */
318#define MXVR_CDRPLL_CTL 0xffc028d4 /* MXVR Clock/Data Recovery PLL Control Register */
319#define MXVR_FMPLL_CTL 0xffc028d8 /* MXVR Frequency Multiply PLL Control Register */
320#define MXVR_PIN_CTL 0xffc028dc /* MXVR Pin Control Register */
321#define MXVR_SCLK_CNT 0xffc028e0 /* MXVR System Clock Counter Register */
322
323/* CAN Controller 1 Config 1 Registers */
324
325#define CAN1_MC1 0xffc03200 /* CAN Controller 1 Mailbox Configuration Register 1 */
326#define CAN1_MD1 0xffc03204 /* CAN Controller 1 Mailbox Direction Register 1 */
327#define CAN1_TRS1 0xffc03208 /* CAN Controller 1 Transmit Request Set Register 1 */
328#define CAN1_TRR1 0xffc0320c /* CAN Controller 1 Transmit Request Reset Register 1 */
329#define CAN1_TA1 0xffc03210 /* CAN Controller 1 Transmit Acknowledge Register 1 */
330#define CAN1_AA1 0xffc03214 /* CAN Controller 1 Abort Acknowledge Register 1 */
331#define CAN1_RMP1 0xffc03218 /* CAN Controller 1 Receive Message Pending Register 1 */
332#define CAN1_RML1 0xffc0321c /* CAN Controller 1 Receive Message Lost Register 1 */
333#define CAN1_MBTIF1 0xffc03220 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
334#define CAN1_MBRIF1 0xffc03224 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
335#define CAN1_MBIM1 0xffc03228 /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
336#define CAN1_RFH1 0xffc0322c /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
337#define CAN1_OPSS1 0xffc03230 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
338
339/* CAN Controller 1 Config 2 Registers */
340
341#define CAN1_MC2 0xffc03240 /* CAN Controller 1 Mailbox Configuration Register 2 */
342#define CAN1_MD2 0xffc03244 /* CAN Controller 1 Mailbox Direction Register 2 */
343#define CAN1_TRS2 0xffc03248 /* CAN Controller 1 Transmit Request Set Register 2 */
344#define CAN1_TRR2 0xffc0324c /* CAN Controller 1 Transmit Request Reset Register 2 */
345#define CAN1_TA2 0xffc03250 /* CAN Controller 1 Transmit Acknowledge Register 2 */
346#define CAN1_AA2 0xffc03254 /* CAN Controller 1 Abort Acknowledge Register 2 */
347#define CAN1_RMP2 0xffc03258 /* CAN Controller 1 Receive Message Pending Register 2 */
348#define CAN1_RML2 0xffc0325c /* CAN Controller 1 Receive Message Lost Register 2 */
349#define CAN1_MBTIF2 0xffc03260 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
350#define CAN1_MBRIF2 0xffc03264 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
351#define CAN1_MBIM2 0xffc03268 /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
352#define CAN1_RFH2 0xffc0326c /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
353#define CAN1_OPSS2 0xffc03270 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
354
355/* CAN Controller 1 Clock/Interrupt/Counter Registers */
356
357#define CAN1_CLOCK 0xffc03280 /* CAN Controller 1 Clock Register */
358#define CAN1_TIMING 0xffc03284 /* CAN Controller 1 Timing Register */
359#define CAN1_DEBUG 0xffc03288 /* CAN Controller 1 Debug Register */
360#define CAN1_STATUS 0xffc0328c /* CAN Controller 1 Global Status Register */
361#define CAN1_CEC 0xffc03290 /* CAN Controller 1 Error Counter Register */
362#define CAN1_GIS 0xffc03294 /* CAN Controller 1 Global Interrupt Status Register */
363#define CAN1_GIM 0xffc03298 /* CAN Controller 1 Global Interrupt Mask Register */
364#define CAN1_GIF 0xffc0329c /* CAN Controller 1 Global Interrupt Flag Register */
365#define CAN1_CONTROL 0xffc032a0 /* CAN Controller 1 Master Control Register */
366#define CAN1_INTR 0xffc032a4 /* CAN Controller 1 Interrupt Pending Register */
367#define CAN1_MBTD 0xffc032ac /* CAN Controller 1 Mailbox Temporary Disable Register */
368#define CAN1_EWR 0xffc032b0 /* CAN Controller 1 Programmable Warning Level Register */
369#define CAN1_ESR 0xffc032b4 /* CAN Controller 1 Error Status Register */
370#define CAN1_UCCNT 0xffc032c4 /* CAN Controller 1 Universal Counter Register */
371#define CAN1_UCRC 0xffc032c8 /* CAN Controller 1 Universal Counter Force Reload Register */
372#define CAN1_UCCNF 0xffc032cc /* CAN Controller 1 Universal Counter Configuration Register */
373
374/* CAN Controller 1 Mailbox Acceptance Registers */
375
376#define CAN1_AM00L 0xffc03300 /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
377#define CAN1_AM00H 0xffc03304 /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
378#define CAN1_AM01L 0xffc03308 /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
379#define CAN1_AM01H 0xffc0330c /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
380#define CAN1_AM02L 0xffc03310 /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
381#define CAN1_AM02H 0xffc03314 /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
382#define CAN1_AM03L 0xffc03318 /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
383#define CAN1_AM03H 0xffc0331c /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
384#define CAN1_AM04L 0xffc03320 /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
385#define CAN1_AM04H 0xffc03324 /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
386#define CAN1_AM05L 0xffc03328 /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
387#define CAN1_AM05H 0xffc0332c /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
388#define CAN1_AM06L 0xffc03330 /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
389#define CAN1_AM06H 0xffc03334 /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
390#define CAN1_AM07L 0xffc03338 /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
391#define CAN1_AM07H 0xffc0333c /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
392#define CAN1_AM08L 0xffc03340 /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
393#define CAN1_AM08H 0xffc03344 /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
394#define CAN1_AM09L 0xffc03348 /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
395#define CAN1_AM09H 0xffc0334c /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
396#define CAN1_AM10L 0xffc03350 /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
397#define CAN1_AM10H 0xffc03354 /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
398#define CAN1_AM11L 0xffc03358 /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
399#define CAN1_AM11H 0xffc0335c /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
400#define CAN1_AM12L 0xffc03360 /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
401#define CAN1_AM12H 0xffc03364 /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
402#define CAN1_AM13L 0xffc03368 /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
403#define CAN1_AM13H 0xffc0336c /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
404#define CAN1_AM14L 0xffc03370 /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
405#define CAN1_AM14H 0xffc03374 /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
406#define CAN1_AM15L 0xffc03378 /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
407#define CAN1_AM15H 0xffc0337c /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
408
409/* CAN Controller 1 Mailbox Acceptance Registers */
410
411#define CAN1_AM16L 0xffc03380 /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
412#define CAN1_AM16H 0xffc03384 /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
413#define CAN1_AM17L 0xffc03388 /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
414#define CAN1_AM17H 0xffc0338c /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
415#define CAN1_AM18L 0xffc03390 /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
416#define CAN1_AM18H 0xffc03394 /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
417#define CAN1_AM19L 0xffc03398 /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
418#define CAN1_AM19H 0xffc0339c /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
419#define CAN1_AM20L 0xffc033a0 /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
420#define CAN1_AM20H 0xffc033a4 /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
421#define CAN1_AM21L 0xffc033a8 /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
422#define CAN1_AM21H 0xffc033ac /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
423#define CAN1_AM22L 0xffc033b0 /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
424#define CAN1_AM22H 0xffc033b4 /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
425#define CAN1_AM23L 0xffc033b8 /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
426#define CAN1_AM23H 0xffc033bc /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
427#define CAN1_AM24L 0xffc033c0 /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
428#define CAN1_AM24H 0xffc033c4 /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
429#define CAN1_AM25L 0xffc033c8 /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
430#define CAN1_AM25H 0xffc033cc /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
431#define CAN1_AM26L 0xffc033d0 /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
432#define CAN1_AM26H 0xffc033d4 /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
433#define CAN1_AM27L 0xffc033d8 /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
434#define CAN1_AM27H 0xffc033dc /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
435#define CAN1_AM28L 0xffc033e0 /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
436#define CAN1_AM28H 0xffc033e4 /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
437#define CAN1_AM29L 0xffc033e8 /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
438#define CAN1_AM29H 0xffc033ec /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
439#define CAN1_AM30L 0xffc033f0 /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
440#define CAN1_AM30H 0xffc033f4 /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
441#define CAN1_AM31L 0xffc033f8 /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
442#define CAN1_AM31H 0xffc033fc /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
443
444/* CAN Controller 1 Mailbox Data Registers */
445
446#define CAN1_MB00_DATA0 0xffc03400 /* CAN Controller 1 Mailbox 0 Data 0 Register */
447#define CAN1_MB00_DATA1 0xffc03404 /* CAN Controller 1 Mailbox 0 Data 1 Register */
448#define CAN1_MB00_DATA2 0xffc03408 /* CAN Controller 1 Mailbox 0 Data 2 Register */
449#define CAN1_MB00_DATA3 0xffc0340c /* CAN Controller 1 Mailbox 0 Data 3 Register */
450#define CAN1_MB00_LENGTH 0xffc03410 /* CAN Controller 1 Mailbox 0 Length Register */
451#define CAN1_MB00_TIMESTAMP 0xffc03414 /* CAN Controller 1 Mailbox 0 Timestamp Register */
452#define CAN1_MB00_ID0 0xffc03418 /* CAN Controller 1 Mailbox 0 ID0 Register */
453#define CAN1_MB00_ID1 0xffc0341c /* CAN Controller 1 Mailbox 0 ID1 Register */
454#define CAN1_MB01_DATA0 0xffc03420 /* CAN Controller 1 Mailbox 1 Data 0 Register */
455#define CAN1_MB01_DATA1 0xffc03424 /* CAN Controller 1 Mailbox 1 Data 1 Register */
456#define CAN1_MB01_DATA2 0xffc03428 /* CAN Controller 1 Mailbox 1 Data 2 Register */
457#define CAN1_MB01_DATA3 0xffc0342c /* CAN Controller 1 Mailbox 1 Data 3 Register */
458#define CAN1_MB01_LENGTH 0xffc03430 /* CAN Controller 1 Mailbox 1 Length Register */
459#define CAN1_MB01_TIMESTAMP 0xffc03434 /* CAN Controller 1 Mailbox 1 Timestamp Register */
460#define CAN1_MB01_ID0 0xffc03438 /* CAN Controller 1 Mailbox 1 ID0 Register */
461#define CAN1_MB01_ID1 0xffc0343c /* CAN Controller 1 Mailbox 1 ID1 Register */
462#define CAN1_MB02_DATA0 0xffc03440 /* CAN Controller 1 Mailbox 2 Data 0 Register */
463#define CAN1_MB02_DATA1 0xffc03444 /* CAN Controller 1 Mailbox 2 Data 1 Register */
464#define CAN1_MB02_DATA2 0xffc03448 /* CAN Controller 1 Mailbox 2 Data 2 Register */
465#define CAN1_MB02_DATA3 0xffc0344c /* CAN Controller 1 Mailbox 2 Data 3 Register */
466#define CAN1_MB02_LENGTH 0xffc03450 /* CAN Controller 1 Mailbox 2 Length Register */
467#define CAN1_MB02_TIMESTAMP 0xffc03454 /* CAN Controller 1 Mailbox 2 Timestamp Register */
468#define CAN1_MB02_ID0 0xffc03458 /* CAN Controller 1 Mailbox 2 ID0 Register */
469#define CAN1_MB02_ID1 0xffc0345c /* CAN Controller 1 Mailbox 2 ID1 Register */
470#define CAN1_MB03_DATA0 0xffc03460 /* CAN Controller 1 Mailbox 3 Data 0 Register */
471#define CAN1_MB03_DATA1 0xffc03464 /* CAN Controller 1 Mailbox 3 Data 1 Register */
472#define CAN1_MB03_DATA2 0xffc03468 /* CAN Controller 1 Mailbox 3 Data 2 Register */
473#define CAN1_MB03_DATA3 0xffc0346c /* CAN Controller 1 Mailbox 3 Data 3 Register */
474#define CAN1_MB03_LENGTH 0xffc03470 /* CAN Controller 1 Mailbox 3 Length Register */
475#define CAN1_MB03_TIMESTAMP 0xffc03474 /* CAN Controller 1 Mailbox 3 Timestamp Register */
476#define CAN1_MB03_ID0 0xffc03478 /* CAN Controller 1 Mailbox 3 ID0 Register */
477#define CAN1_MB03_ID1 0xffc0347c /* CAN Controller 1 Mailbox 3 ID1 Register */
478#define CAN1_MB04_DATA0 0xffc03480 /* CAN Controller 1 Mailbox 4 Data 0 Register */
479#define CAN1_MB04_DATA1 0xffc03484 /* CAN Controller 1 Mailbox 4 Data 1 Register */
480#define CAN1_MB04_DATA2 0xffc03488 /* CAN Controller 1 Mailbox 4 Data 2 Register */
481#define CAN1_MB04_DATA3 0xffc0348c /* CAN Controller 1 Mailbox 4 Data 3 Register */
482#define CAN1_MB04_LENGTH 0xffc03490 /* CAN Controller 1 Mailbox 4 Length Register */
483#define CAN1_MB04_TIMESTAMP 0xffc03494 /* CAN Controller 1 Mailbox 4 Timestamp Register */
484#define CAN1_MB04_ID0 0xffc03498 /* CAN Controller 1 Mailbox 4 ID0 Register */
485#define CAN1_MB04_ID1 0xffc0349c /* CAN Controller 1 Mailbox 4 ID1 Register */
486#define CAN1_MB05_DATA0 0xffc034a0 /* CAN Controller 1 Mailbox 5 Data 0 Register */
487#define CAN1_MB05_DATA1 0xffc034a4 /* CAN Controller 1 Mailbox 5 Data 1 Register */
488#define CAN1_MB05_DATA2 0xffc034a8 /* CAN Controller 1 Mailbox 5 Data 2 Register */
489#define CAN1_MB05_DATA3 0xffc034ac /* CAN Controller 1 Mailbox 5 Data 3 Register */
490#define CAN1_MB05_LENGTH 0xffc034b0 /* CAN Controller 1 Mailbox 5 Length Register */
491#define CAN1_MB05_TIMESTAMP 0xffc034b4 /* CAN Controller 1 Mailbox 5 Timestamp Register */
492#define CAN1_MB05_ID0 0xffc034b8 /* CAN Controller 1 Mailbox 5 ID0 Register */
493#define CAN1_MB05_ID1 0xffc034bc /* CAN Controller 1 Mailbox 5 ID1 Register */
494#define CAN1_MB06_DATA0 0xffc034c0 /* CAN Controller 1 Mailbox 6 Data 0 Register */
495#define CAN1_MB06_DATA1 0xffc034c4 /* CAN Controller 1 Mailbox 6 Data 1 Register */
496#define CAN1_MB06_DATA2 0xffc034c8 /* CAN Controller 1 Mailbox 6 Data 2 Register */
497#define CAN1_MB06_DATA3 0xffc034cc /* CAN Controller 1 Mailbox 6 Data 3 Register */
498#define CAN1_MB06_LENGTH 0xffc034d0 /* CAN Controller 1 Mailbox 6 Length Register */
499#define CAN1_MB06_TIMESTAMP 0xffc034d4 /* CAN Controller 1 Mailbox 6 Timestamp Register */
500#define CAN1_MB06_ID0 0xffc034d8 /* CAN Controller 1 Mailbox 6 ID0 Register */
501#define CAN1_MB06_ID1 0xffc034dc /* CAN Controller 1 Mailbox 6 ID1 Register */
502#define CAN1_MB07_DATA0 0xffc034e0 /* CAN Controller 1 Mailbox 7 Data 0 Register */
503#define CAN1_MB07_DATA1 0xffc034e4 /* CAN Controller 1 Mailbox 7 Data 1 Register */
504#define CAN1_MB07_DATA2 0xffc034e8 /* CAN Controller 1 Mailbox 7 Data 2 Register */
505#define CAN1_MB07_DATA3 0xffc034ec /* CAN Controller 1 Mailbox 7 Data 3 Register */
506#define CAN1_MB07_LENGTH 0xffc034f0 /* CAN Controller 1 Mailbox 7 Length Register */
507#define CAN1_MB07_TIMESTAMP 0xffc034f4 /* CAN Controller 1 Mailbox 7 Timestamp Register */
508#define CAN1_MB07_ID0 0xffc034f8 /* CAN Controller 1 Mailbox 7 ID0 Register */
509#define CAN1_MB07_ID1 0xffc034fc /* CAN Controller 1 Mailbox 7 ID1 Register */
510#define CAN1_MB08_DATA0 0xffc03500 /* CAN Controller 1 Mailbox 8 Data 0 Register */
511#define CAN1_MB08_DATA1 0xffc03504 /* CAN Controller 1 Mailbox 8 Data 1 Register */
512#define CAN1_MB08_DATA2 0xffc03508 /* CAN Controller 1 Mailbox 8 Data 2 Register */
513#define CAN1_MB08_DATA3 0xffc0350c /* CAN Controller 1 Mailbox 8 Data 3 Register */
514#define CAN1_MB08_LENGTH 0xffc03510 /* CAN Controller 1 Mailbox 8 Length Register */
515#define CAN1_MB08_TIMESTAMP 0xffc03514 /* CAN Controller 1 Mailbox 8 Timestamp Register */
516#define CAN1_MB08_ID0 0xffc03518 /* CAN Controller 1 Mailbox 8 ID0 Register */
517#define CAN1_MB08_ID1 0xffc0351c /* CAN Controller 1 Mailbox 8 ID1 Register */
518#define CAN1_MB09_DATA0 0xffc03520 /* CAN Controller 1 Mailbox 9 Data 0 Register */
519#define CAN1_MB09_DATA1 0xffc03524 /* CAN Controller 1 Mailbox 9 Data 1 Register */
520#define CAN1_MB09_DATA2 0xffc03528 /* CAN Controller 1 Mailbox 9 Data 2 Register */
521#define CAN1_MB09_DATA3 0xffc0352c /* CAN Controller 1 Mailbox 9 Data 3 Register */
522#define CAN1_MB09_LENGTH 0xffc03530 /* CAN Controller 1 Mailbox 9 Length Register */
523#define CAN1_MB09_TIMESTAMP 0xffc03534 /* CAN Controller 1 Mailbox 9 Timestamp Register */
524#define CAN1_MB09_ID0 0xffc03538 /* CAN Controller 1 Mailbox 9 ID0 Register */
525#define CAN1_MB09_ID1 0xffc0353c /* CAN Controller 1 Mailbox 9 ID1 Register */
526#define CAN1_MB10_DATA0 0xffc03540 /* CAN Controller 1 Mailbox 10 Data 0 Register */
527#define CAN1_MB10_DATA1 0xffc03544 /* CAN Controller 1 Mailbox 10 Data 1 Register */
528#define CAN1_MB10_DATA2 0xffc03548 /* CAN Controller 1 Mailbox 10 Data 2 Register */
529#define CAN1_MB10_DATA3 0xffc0354c /* CAN Controller 1 Mailbox 10 Data 3 Register */
530#define CAN1_MB10_LENGTH 0xffc03550 /* CAN Controller 1 Mailbox 10 Length Register */
531#define CAN1_MB10_TIMESTAMP 0xffc03554 /* CAN Controller 1 Mailbox 10 Timestamp Register */
532#define CAN1_MB10_ID0 0xffc03558 /* CAN Controller 1 Mailbox 10 ID0 Register */
533#define CAN1_MB10_ID1 0xffc0355c /* CAN Controller 1 Mailbox 10 ID1 Register */
534#define CAN1_MB11_DATA0 0xffc03560 /* CAN Controller 1 Mailbox 11 Data 0 Register */
535#define CAN1_MB11_DATA1 0xffc03564 /* CAN Controller 1 Mailbox 11 Data 1 Register */
536#define CAN1_MB11_DATA2 0xffc03568 /* CAN Controller 1 Mailbox 11 Data 2 Register */
537#define CAN1_MB11_DATA3 0xffc0356c /* CAN Controller 1 Mailbox 11 Data 3 Register */
538#define CAN1_MB11_LENGTH 0xffc03570 /* CAN Controller 1 Mailbox 11 Length Register */
539#define CAN1_MB11_TIMESTAMP 0xffc03574 /* CAN Controller 1 Mailbox 11 Timestamp Register */
540#define CAN1_MB11_ID0 0xffc03578 /* CAN Controller 1 Mailbox 11 ID0 Register */
541#define CAN1_MB11_ID1 0xffc0357c /* CAN Controller 1 Mailbox 11 ID1 Register */
542#define CAN1_MB12_DATA0 0xffc03580 /* CAN Controller 1 Mailbox 12 Data 0 Register */
543#define CAN1_MB12_DATA1 0xffc03584 /* CAN Controller 1 Mailbox 12 Data 1 Register */
544#define CAN1_MB12_DATA2 0xffc03588 /* CAN Controller 1 Mailbox 12 Data 2 Register */
545#define CAN1_MB12_DATA3 0xffc0358c /* CAN Controller 1 Mailbox 12 Data 3 Register */
546#define CAN1_MB12_LENGTH 0xffc03590 /* CAN Controller 1 Mailbox 12 Length Register */
547#define CAN1_MB12_TIMESTAMP 0xffc03594 /* CAN Controller 1 Mailbox 12 Timestamp Register */
548#define CAN1_MB12_ID0 0xffc03598 /* CAN Controller 1 Mailbox 12 ID0 Register */
549#define CAN1_MB12_ID1 0xffc0359c /* CAN Controller 1 Mailbox 12 ID1 Register */
550#define CAN1_MB13_DATA0 0xffc035a0 /* CAN Controller 1 Mailbox 13 Data 0 Register */
551#define CAN1_MB13_DATA1 0xffc035a4 /* CAN Controller 1 Mailbox 13 Data 1 Register */
552#define CAN1_MB13_DATA2 0xffc035a8 /* CAN Controller 1 Mailbox 13 Data 2 Register */
553#define CAN1_MB13_DATA3 0xffc035ac /* CAN Controller 1 Mailbox 13 Data 3 Register */
554#define CAN1_MB13_LENGTH 0xffc035b0 /* CAN Controller 1 Mailbox 13 Length Register */
555#define CAN1_MB13_TIMESTAMP 0xffc035b4 /* CAN Controller 1 Mailbox 13 Timestamp Register */
556#define CAN1_MB13_ID0 0xffc035b8 /* CAN Controller 1 Mailbox 13 ID0 Register */
557#define CAN1_MB13_ID1 0xffc035bc /* CAN Controller 1 Mailbox 13 ID1 Register */
558#define CAN1_MB14_DATA0 0xffc035c0 /* CAN Controller 1 Mailbox 14 Data 0 Register */
559#define CAN1_MB14_DATA1 0xffc035c4 /* CAN Controller 1 Mailbox 14 Data 1 Register */
560#define CAN1_MB14_DATA2 0xffc035c8 /* CAN Controller 1 Mailbox 14 Data 2 Register */
561#define CAN1_MB14_DATA3 0xffc035cc /* CAN Controller 1 Mailbox 14 Data 3 Register */
562#define CAN1_MB14_LENGTH 0xffc035d0 /* CAN Controller 1 Mailbox 14 Length Register */
563#define CAN1_MB14_TIMESTAMP 0xffc035d4 /* CAN Controller 1 Mailbox 14 Timestamp Register */
564#define CAN1_MB14_ID0 0xffc035d8 /* CAN Controller 1 Mailbox 14 ID0 Register */
565#define CAN1_MB14_ID1 0xffc035dc /* CAN Controller 1 Mailbox 14 ID1 Register */
566#define CAN1_MB15_DATA0 0xffc035e0 /* CAN Controller 1 Mailbox 15 Data 0 Register */
567#define CAN1_MB15_DATA1 0xffc035e4 /* CAN Controller 1 Mailbox 15 Data 1 Register */
568#define CAN1_MB15_DATA2 0xffc035e8 /* CAN Controller 1 Mailbox 15 Data 2 Register */
569#define CAN1_MB15_DATA3 0xffc035ec /* CAN Controller 1 Mailbox 15 Data 3 Register */
570#define CAN1_MB15_LENGTH 0xffc035f0 /* CAN Controller 1 Mailbox 15 Length Register */
571#define CAN1_MB15_TIMESTAMP 0xffc035f4 /* CAN Controller 1 Mailbox 15 Timestamp Register */
572#define CAN1_MB15_ID0 0xffc035f8 /* CAN Controller 1 Mailbox 15 ID0 Register */
573#define CAN1_MB15_ID1 0xffc035fc /* CAN Controller 1 Mailbox 15 ID1 Register */
574
575/* CAN Controller 1 Mailbox Data Registers */
576
577#define CAN1_MB16_DATA0 0xffc03600 /* CAN Controller 1 Mailbox 16 Data 0 Register */
578#define CAN1_MB16_DATA1 0xffc03604 /* CAN Controller 1 Mailbox 16 Data 1 Register */
579#define CAN1_MB16_DATA2 0xffc03608 /* CAN Controller 1 Mailbox 16 Data 2 Register */
580#define CAN1_MB16_DATA3 0xffc0360c /* CAN Controller 1 Mailbox 16 Data 3 Register */
581#define CAN1_MB16_LENGTH 0xffc03610 /* CAN Controller 1 Mailbox 16 Length Register */
582#define CAN1_MB16_TIMESTAMP 0xffc03614 /* CAN Controller 1 Mailbox 16 Timestamp Register */
583#define CAN1_MB16_ID0 0xffc03618 /* CAN Controller 1 Mailbox 16 ID0 Register */
584#define CAN1_MB16_ID1 0xffc0361c /* CAN Controller 1 Mailbox 16 ID1 Register */
585#define CAN1_MB17_DATA0 0xffc03620 /* CAN Controller 1 Mailbox 17 Data 0 Register */
586#define CAN1_MB17_DATA1 0xffc03624 /* CAN Controller 1 Mailbox 17 Data 1 Register */
587#define CAN1_MB17_DATA2 0xffc03628 /* CAN Controller 1 Mailbox 17 Data 2 Register */
588#define CAN1_MB17_DATA3 0xffc0362c /* CAN Controller 1 Mailbox 17 Data 3 Register */
589#define CAN1_MB17_LENGTH 0xffc03630 /* CAN Controller 1 Mailbox 17 Length Register */
590#define CAN1_MB17_TIMESTAMP 0xffc03634 /* CAN Controller 1 Mailbox 17 Timestamp Register */
591#define CAN1_MB17_ID0 0xffc03638 /* CAN Controller 1 Mailbox 17 ID0 Register */
592#define CAN1_MB17_ID1 0xffc0363c /* CAN Controller 1 Mailbox 17 ID1 Register */
593#define CAN1_MB18_DATA0 0xffc03640 /* CAN Controller 1 Mailbox 18 Data 0 Register */
594#define CAN1_MB18_DATA1 0xffc03644 /* CAN Controller 1 Mailbox 18 Data 1 Register */
595#define CAN1_MB18_DATA2 0xffc03648 /* CAN Controller 1 Mailbox 18 Data 2 Register */
596#define CAN1_MB18_DATA3 0xffc0364c /* CAN Controller 1 Mailbox 18 Data 3 Register */
597#define CAN1_MB18_LENGTH 0xffc03650 /* CAN Controller 1 Mailbox 18 Length Register */
598#define CAN1_MB18_TIMESTAMP 0xffc03654 /* CAN Controller 1 Mailbox 18 Timestamp Register */
599#define CAN1_MB18_ID0 0xffc03658 /* CAN Controller 1 Mailbox 18 ID0 Register */
600#define CAN1_MB18_ID1 0xffc0365c /* CAN Controller 1 Mailbox 18 ID1 Register */
601#define CAN1_MB19_DATA0 0xffc03660 /* CAN Controller 1 Mailbox 19 Data 0 Register */
602#define CAN1_MB19_DATA1 0xffc03664 /* CAN Controller 1 Mailbox 19 Data 1 Register */
603#define CAN1_MB19_DATA2 0xffc03668 /* CAN Controller 1 Mailbox 19 Data 2 Register */
604#define CAN1_MB19_DATA3 0xffc0366c /* CAN Controller 1 Mailbox 19 Data 3 Register */
605#define CAN1_MB19_LENGTH 0xffc03670 /* CAN Controller 1 Mailbox 19 Length Register */
606#define CAN1_MB19_TIMESTAMP 0xffc03674 /* CAN Controller 1 Mailbox 19 Timestamp Register */
607#define CAN1_MB19_ID0 0xffc03678 /* CAN Controller 1 Mailbox 19 ID0 Register */
608#define CAN1_MB19_ID1 0xffc0367c /* CAN Controller 1 Mailbox 19 ID1 Register */
609#define CAN1_MB20_DATA0 0xffc03680 /* CAN Controller 1 Mailbox 20 Data 0 Register */
610#define CAN1_MB20_DATA1 0xffc03684 /* CAN Controller 1 Mailbox 20 Data 1 Register */
611#define CAN1_MB20_DATA2 0xffc03688 /* CAN Controller 1 Mailbox 20 Data 2 Register */
612#define CAN1_MB20_DATA3 0xffc0368c /* CAN Controller 1 Mailbox 20 Data 3 Register */
613#define CAN1_MB20_LENGTH 0xffc03690 /* CAN Controller 1 Mailbox 20 Length Register */
614#define CAN1_MB20_TIMESTAMP 0xffc03694 /* CAN Controller 1 Mailbox 20 Timestamp Register */
615#define CAN1_MB20_ID0 0xffc03698 /* CAN Controller 1 Mailbox 20 ID0 Register */
616#define CAN1_MB20_ID1 0xffc0369c /* CAN Controller 1 Mailbox 20 ID1 Register */
617#define CAN1_MB21_DATA0 0xffc036a0 /* CAN Controller 1 Mailbox 21 Data 0 Register */
618#define CAN1_MB21_DATA1 0xffc036a4 /* CAN Controller 1 Mailbox 21 Data 1 Register */
619#define CAN1_MB21_DATA2 0xffc036a8 /* CAN Controller 1 Mailbox 21 Data 2 Register */
620#define CAN1_MB21_DATA3 0xffc036ac /* CAN Controller 1 Mailbox 21 Data 3 Register */
621#define CAN1_MB21_LENGTH 0xffc036b0 /* CAN Controller 1 Mailbox 21 Length Register */
622#define CAN1_MB21_TIMESTAMP 0xffc036b4 /* CAN Controller 1 Mailbox 21 Timestamp Register */
623#define CAN1_MB21_ID0 0xffc036b8 /* CAN Controller 1 Mailbox 21 ID0 Register */
624#define CAN1_MB21_ID1 0xffc036bc /* CAN Controller 1 Mailbox 21 ID1 Register */
625#define CAN1_MB22_DATA0 0xffc036c0 /* CAN Controller 1 Mailbox 22 Data 0 Register */
626#define CAN1_MB22_DATA1 0xffc036c4 /* CAN Controller 1 Mailbox 22 Data 1 Register */
627#define CAN1_MB22_DATA2 0xffc036c8 /* CAN Controller 1 Mailbox 22 Data 2 Register */
628#define CAN1_MB22_DATA3 0xffc036cc /* CAN Controller 1 Mailbox 22 Data 3 Register */
629#define CAN1_MB22_LENGTH 0xffc036d0 /* CAN Controller 1 Mailbox 22 Length Register */
630#define CAN1_MB22_TIMESTAMP 0xffc036d4 /* CAN Controller 1 Mailbox 22 Timestamp Register */
631#define CAN1_MB22_ID0 0xffc036d8 /* CAN Controller 1 Mailbox 22 ID0 Register */
632#define CAN1_MB22_ID1 0xffc036dc /* CAN Controller 1 Mailbox 22 ID1 Register */
633#define CAN1_MB23_DATA0 0xffc036e0 /* CAN Controller 1 Mailbox 23 Data 0 Register */
634#define CAN1_MB23_DATA1 0xffc036e4 /* CAN Controller 1 Mailbox 23 Data 1 Register */
635#define CAN1_MB23_DATA2 0xffc036e8 /* CAN Controller 1 Mailbox 23 Data 2 Register */
636#define CAN1_MB23_DATA3 0xffc036ec /* CAN Controller 1 Mailbox 23 Data 3 Register */
637#define CAN1_MB23_LENGTH 0xffc036f0 /* CAN Controller 1 Mailbox 23 Length Register */
638#define CAN1_MB23_TIMESTAMP 0xffc036f4 /* CAN Controller 1 Mailbox 23 Timestamp Register */
639#define CAN1_MB23_ID0 0xffc036f8 /* CAN Controller 1 Mailbox 23 ID0 Register */
640#define CAN1_MB23_ID1 0xffc036fc /* CAN Controller 1 Mailbox 23 ID1 Register */
641#define CAN1_MB24_DATA0 0xffc03700 /* CAN Controller 1 Mailbox 24 Data 0 Register */
642#define CAN1_MB24_DATA1 0xffc03704 /* CAN Controller 1 Mailbox 24 Data 1 Register */
643#define CAN1_MB24_DATA2 0xffc03708 /* CAN Controller 1 Mailbox 24 Data 2 Register */
644#define CAN1_MB24_DATA3 0xffc0370c /* CAN Controller 1 Mailbox 24 Data 3 Register */
645#define CAN1_MB24_LENGTH 0xffc03710 /* CAN Controller 1 Mailbox 24 Length Register */
646#define CAN1_MB24_TIMESTAMP 0xffc03714 /* CAN Controller 1 Mailbox 24 Timestamp Register */
647#define CAN1_MB24_ID0 0xffc03718 /* CAN Controller 1 Mailbox 24 ID0 Register */
648#define CAN1_MB24_ID1 0xffc0371c /* CAN Controller 1 Mailbox 24 ID1 Register */
649#define CAN1_MB25_DATA0 0xffc03720 /* CAN Controller 1 Mailbox 25 Data 0 Register */
650#define CAN1_MB25_DATA1 0xffc03724 /* CAN Controller 1 Mailbox 25 Data 1 Register */
651#define CAN1_MB25_DATA2 0xffc03728 /* CAN Controller 1 Mailbox 25 Data 2 Register */
652#define CAN1_MB25_DATA3 0xffc0372c /* CAN Controller 1 Mailbox 25 Data 3 Register */
653#define CAN1_MB25_LENGTH 0xffc03730 /* CAN Controller 1 Mailbox 25 Length Register */
654#define CAN1_MB25_TIMESTAMP 0xffc03734 /* CAN Controller 1 Mailbox 25 Timestamp Register */
655#define CAN1_MB25_ID0 0xffc03738 /* CAN Controller 1 Mailbox 25 ID0 Register */
656#define CAN1_MB25_ID1 0xffc0373c /* CAN Controller 1 Mailbox 25 ID1 Register */
657#define CAN1_MB26_DATA0 0xffc03740 /* CAN Controller 1 Mailbox 26 Data 0 Register */
658#define CAN1_MB26_DATA1 0xffc03744 /* CAN Controller 1 Mailbox 26 Data 1 Register */
659#define CAN1_MB26_DATA2 0xffc03748 /* CAN Controller 1 Mailbox 26 Data 2 Register */
660#define CAN1_MB26_DATA3 0xffc0374c /* CAN Controller 1 Mailbox 26 Data 3 Register */
661#define CAN1_MB26_LENGTH 0xffc03750 /* CAN Controller 1 Mailbox 26 Length Register */
662#define CAN1_MB26_TIMESTAMP 0xffc03754 /* CAN Controller 1 Mailbox 26 Timestamp Register */
663#define CAN1_MB26_ID0 0xffc03758 /* CAN Controller 1 Mailbox 26 ID0 Register */
664#define CAN1_MB26_ID1 0xffc0375c /* CAN Controller 1 Mailbox 26 ID1 Register */
665#define CAN1_MB27_DATA0 0xffc03760 /* CAN Controller 1 Mailbox 27 Data 0 Register */
666#define CAN1_MB27_DATA1 0xffc03764 /* CAN Controller 1 Mailbox 27 Data 1 Register */
667#define CAN1_MB27_DATA2 0xffc03768 /* CAN Controller 1 Mailbox 27 Data 2 Register */
668#define CAN1_MB27_DATA3 0xffc0376c /* CAN Controller 1 Mailbox 27 Data 3 Register */
669#define CAN1_MB27_LENGTH 0xffc03770 /* CAN Controller 1 Mailbox 27 Length Register */
670#define CAN1_MB27_TIMESTAMP 0xffc03774 /* CAN Controller 1 Mailbox 27 Timestamp Register */
671#define CAN1_MB27_ID0 0xffc03778 /* CAN Controller 1 Mailbox 27 ID0 Register */
672#define CAN1_MB27_ID1 0xffc0377c /* CAN Controller 1 Mailbox 27 ID1 Register */
673#define CAN1_MB28_DATA0 0xffc03780 /* CAN Controller 1 Mailbox 28 Data 0 Register */
674#define CAN1_MB28_DATA1 0xffc03784 /* CAN Controller 1 Mailbox 28 Data 1 Register */
675#define CAN1_MB28_DATA2 0xffc03788 /* CAN Controller 1 Mailbox 28 Data 2 Register */
676#define CAN1_MB28_DATA3 0xffc0378c /* CAN Controller 1 Mailbox 28 Data 3 Register */
677#define CAN1_MB28_LENGTH 0xffc03790 /* CAN Controller 1 Mailbox 28 Length Register */
678#define CAN1_MB28_TIMESTAMP 0xffc03794 /* CAN Controller 1 Mailbox 28 Timestamp Register */
679#define CAN1_MB28_ID0 0xffc03798 /* CAN Controller 1 Mailbox 28 ID0 Register */
680#define CAN1_MB28_ID1 0xffc0379c /* CAN Controller 1 Mailbox 28 ID1 Register */
681#define CAN1_MB29_DATA0 0xffc037a0 /* CAN Controller 1 Mailbox 29 Data 0 Register */
682#define CAN1_MB29_DATA1 0xffc037a4 /* CAN Controller 1 Mailbox 29 Data 1 Register */
683#define CAN1_MB29_DATA2 0xffc037a8 /* CAN Controller 1 Mailbox 29 Data 2 Register */
684#define CAN1_MB29_DATA3 0xffc037ac /* CAN Controller 1 Mailbox 29 Data 3 Register */
685#define CAN1_MB29_LENGTH 0xffc037b0 /* CAN Controller 1 Mailbox 29 Length Register */
686#define CAN1_MB29_TIMESTAMP 0xffc037b4 /* CAN Controller 1 Mailbox 29 Timestamp Register */
687#define CAN1_MB29_ID0 0xffc037b8 /* CAN Controller 1 Mailbox 29 ID0 Register */
688#define CAN1_MB29_ID1 0xffc037bc /* CAN Controller 1 Mailbox 29 ID1 Register */
689#define CAN1_MB30_DATA0 0xffc037c0 /* CAN Controller 1 Mailbox 30 Data 0 Register */
690#define CAN1_MB30_DATA1 0xffc037c4 /* CAN Controller 1 Mailbox 30 Data 1 Register */
691#define CAN1_MB30_DATA2 0xffc037c8 /* CAN Controller 1 Mailbox 30 Data 2 Register */
692#define CAN1_MB30_DATA3 0xffc037cc /* CAN Controller 1 Mailbox 30 Data 3 Register */
693#define CAN1_MB30_LENGTH 0xffc037d0 /* CAN Controller 1 Mailbox 30 Length Register */
694#define CAN1_MB30_TIMESTAMP 0xffc037d4 /* CAN Controller 1 Mailbox 30 Timestamp Register */
695#define CAN1_MB30_ID0 0xffc037d8 /* CAN Controller 1 Mailbox 30 ID0 Register */
696#define CAN1_MB30_ID1 0xffc037dc /* CAN Controller 1 Mailbox 30 ID1 Register */
697#define CAN1_MB31_DATA0 0xffc037e0 /* CAN Controller 1 Mailbox 31 Data 0 Register */
698#define CAN1_MB31_DATA1 0xffc037e4 /* CAN Controller 1 Mailbox 31 Data 1 Register */
699#define CAN1_MB31_DATA2 0xffc037e8 /* CAN Controller 1 Mailbox 31 Data 2 Register */
700#define CAN1_MB31_DATA3 0xffc037ec /* CAN Controller 1 Mailbox 31 Data 3 Register */
701#define CAN1_MB31_LENGTH 0xffc037f0 /* CAN Controller 1 Mailbox 31 Length Register */
702#define CAN1_MB31_TIMESTAMP 0xffc037f4 /* CAN Controller 1 Mailbox 31 Timestamp Register */
703#define CAN1_MB31_ID0 0xffc037f8 /* CAN Controller 1 Mailbox 31 ID0 Register */
704#define CAN1_MB31_ID1 0xffc037fc /* CAN Controller 1 Mailbox 31 ID1 Register */
705
706/* ATAPI Registers */
707
708#define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */
709#define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */
710#define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */
711#define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */
712#define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */
713#define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */
714#define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */
715#define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */
716#define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */
717#define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */
718#define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */
719#define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */
720#define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */
721#define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */
722#define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */
723#define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */
724#define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */
725#define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */
726#define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */
727#define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */
728#define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */
729#define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */
730#define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */
731#define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */
732#define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */
733
734/* SDH Registers */
735
736#define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */
737#define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */
738#define SDH_ARGUMENT 0xffc03908 /* SDH Argument */
739#define SDH_COMMAND 0xffc0390c /* SDH Command */
740#define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */
741#define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */
742#define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */
743#define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */
744#define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */
745#define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */
746#define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */
747#define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */
748#define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */
749#define SDH_STATUS 0xffc03934 /* SDH Status */
750#define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */
751#define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */
752#define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */
753#define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */
754#define SDH_FIFO 0xffc03980 /* SDH Data FIFO */
755#define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */
756#define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */
757#define SDH_CFG 0xffc039c8 /* SDH Configuration */
758#define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */
759#define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */
760#define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */
761#define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */
762#define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */
763#define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */
764#define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */
765#define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */
766#define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */
767
768/* HOST Port Registers */
769
770#define HOST_CONTROL 0xffc03a00 /* HOST Control Register */
771#define HOST_STATUS 0xffc03a04 /* HOST Status Register */
772#define HOST_TIMEOUT 0xffc03a08 /* HOST Acknowledge Mode Timeout Register */
773
774/* USB Control Registers */
775
776#define USB_FADDR 0xffc03c00 /* Function address register */
777#define USB_POWER 0xffc03c04 /* Power management register */
778#define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
779#define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */
780#define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */
781#define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */
782#define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */
783#define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */
784#define USB_FRAME 0xffc03c20 /* USB frame number */
785#define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */
786#define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */
787#define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
788#define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */
789
790/* USB Packet Control Registers */
791
792#define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */
793#define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
794#define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
795#define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */
796#define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */
797#define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
798#define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
799#define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
800#define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
801#define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
802#define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
803#define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
804#define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
805
806/* USB Endpoint FIFO Registers */
807
808#define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */
809#define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */
810#define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */
811#define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */
812#define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */
813#define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */
814#define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */
815#define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */
816
817/* USB OTG Control Registers */
818
819#define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */
820#define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */
821#define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */
822
823/* USB Phy Control Registers */
824
825#define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */
826#define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */
827#define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */
828#define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */
829#define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */
830
831/* (APHY_CNTRL is for ADI usage only) */
832
833#define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */
834
835/* (APHY_CALIB is for ADI usage only) */
836
837#define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */
838#define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
839
840/* (PHY_TEST is for ADI usage only) */
841
842#define USB_PHY_TEST 0xffc03dec /* Used for reducing simulation time and simplifies FIFO testability */
843#define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */
844#define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
845
846/* USB Endpoint 0 Control Registers */
847
848#define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */
849#define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */
850#define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */
851#define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */
852#define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */
853#define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
854#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */
855#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
856#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
857
858/* USB Endpoint 1 Control Registers */
859
860#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
861#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */
862#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */
863#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */
864#define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */
865#define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */
866#define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
867#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */
868#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
869#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
870
871/* USB Endpoint 2 Control Registers */
872
873#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
874#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */
875#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */
876#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */
877#define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */
878#define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */
879#define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
880#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */
881#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
882#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
883
884/* USB Endpoint 3 Control Registers */
885
886#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
887#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */
888#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */
889#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */
890#define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */
891#define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */
892#define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
893#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */
894#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
895#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
896
897/* USB Endpoint 4 Control Registers */
898
899#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
900#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */
901#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */
902#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */
903#define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */
904#define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */
905#define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
906#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */
907#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
908#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
909
910/* USB Endpoint 5 Control Registers */
911
912#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
913#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */
914#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */
915#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */
916#define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */
917#define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */
918#define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
919#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */
920#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
921#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
922
923/* USB Endpoint 6 Control Registers */
924
925#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
926#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */
927#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */
928#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */
929#define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */
930#define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */
931#define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
932#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */
933#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
934#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
935
936/* USB Endpoint 7 Control Registers */
937
938#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
939#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */
940#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */
941#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */
942#define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */
943#define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */
944#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
945#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */
946#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
947#define USB_EP_NI7_RXINTERVAL 0xffc03ff0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
948#define USB_EP_NI7_TXCOUNT 0xffc03ff8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
949#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */
950
951/* USB Channel 0 Config Registers */
952
953#define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */
954#define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
955#define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
956#define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
957#define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
958
959/* USB Channel 1 Config Registers */
960
961#define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */
962#define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
963#define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
964#define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
965#define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
966
967/* USB Channel 2 Config Registers */
968
969#define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */
970#define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
971#define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
972#define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
973#define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
974
975/* USB Channel 3 Config Registers */
976
977#define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */
978#define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
979#define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
980#define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
981#define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
982
983/* USB Channel 4 Config Registers */
984
985#define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */
986#define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
987#define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
988#define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
989#define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
990
991/* USB Channel 5 Config Registers */
992
993#define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */
994#define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
995#define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
996#define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
997#define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
998
999/* USB Channel 6 Config Registers */
1000
1001#define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */
1002#define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
1003#define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
1004#define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
1005#define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
1006
1007/* USB Channel 7 Config Registers */
1008
1009#define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */
1010#define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
1011#define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
1012#define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
1013#define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
1014
1015/* Keypad Registers */
1016
1017#define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */
1018#define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */
1019#define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */
1020#define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */
1021#define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */
1022#define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */
1023
1024/* Pixel Compositor (PIXC) Registers */
1025
1026#define PIXC_CTL 0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
1027#define PIXC_PPL 0xffc04404 /* Holds the number of pixels per line of the display */
1028#define PIXC_LPF 0xffc04408 /* Holds the number of lines per frame of the display */
1029#define PIXC_AHSTART 0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */
1030#define PIXC_AHEND 0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */
1031#define PIXC_AVSTART 0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */
1032#define PIXC_AVEND 0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */
1033#define PIXC_ATRANSP 0xffc0441c /* Contains the transparency ratio (set A) */
1034#define PIXC_BHSTART 0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */
1035#define PIXC_BHEND 0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */
1036#define PIXC_BVSTART 0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */
1037#define PIXC_BVEND 0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */
1038#define PIXC_BTRANSP 0xffc04430 /* Contains the transparency ratio (set B) */
1039#define PIXC_INTRSTAT 0xffc0443c /* Overlay interrupt configuration/status */
1040#define PIXC_RYCON 0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
1041#define PIXC_GUCON 0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
1042#define PIXC_BVCON 0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
1043#define PIXC_CCBIAS 0xffc0444c /* Bias values for the color space conversion matrix */
1044#define PIXC_TC 0xffc04450 /* Holds the transparent color value */
1045
1046/* Handshake MDMA 0 Registers */
1047
1048#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */
1049#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */
1050#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */
1051#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
1052#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
1053#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */
1054#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */
1055
1056/* Handshake MDMA 1 Registers */
1057
1058#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */
1059#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */
1060#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */
1061#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
1062#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
1063#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */
1064#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */
1065
1066
1067/* ********************************************************** */
1068/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
1069/* and MULTI BIT READ MACROS */
1070/* ********************************************************** */
1071
1072/* Bit masks for PIXC_CTL */
1073
1074#define PIXC_EN 0x1 /* Pixel Compositor Enable */
1075#define OVR_A_EN 0x2 /* Overlay A Enable */
1076#define OVR_B_EN 0x4 /* Overlay B Enable */
1077#define IMG_FORM 0x8 /* Image Data Format */
1078#define OVR_FORM 0x10 /* Overlay Data Format */
1079#define OUT_FORM 0x20 /* Output Data Format */
1080#define UDS_MOD 0x40 /* Resampling Mode */
1081#define TC_EN 0x80 /* Transparent Color Enable */
1082#define IMG_STAT 0x300 /* Image FIFO Status */
1083#define OVR_STAT 0xc00 /* Overlay FIFO Status */
1084#define WM_LVL 0x3000 /* FIFO Watermark Level */
1085
1086/* Bit masks for PIXC_AHSTART */
1087
1088#define A_HSTART 0xfff /* Horizontal Start Coordinates */
1089
1090/* Bit masks for PIXC_AHEND */
1091
1092#define A_HEND 0xfff /* Horizontal End Coordinates */
1093
1094/* Bit masks for PIXC_AVSTART */
1095
1096#define A_VSTART 0x3ff /* Vertical Start Coordinates */
1097
1098/* Bit masks for PIXC_AVEND */
1099
1100#define A_VEND 0x3ff /* Vertical End Coordinates */
1101
1102/* Bit masks for PIXC_ATRANSP */
1103
1104#define A_TRANSP 0xf /* Transparency Value */
1105
1106/* Bit masks for PIXC_BHSTART */
1107
1108#define B_HSTART 0xfff /* Horizontal Start Coordinates */
1109
1110/* Bit masks for PIXC_BHEND */
1111
1112#define B_HEND 0xfff /* Horizontal End Coordinates */
1113
1114/* Bit masks for PIXC_BVSTART */
1115
1116#define B_VSTART 0x3ff /* Vertical Start Coordinates */
1117
1118/* Bit masks for PIXC_BVEND */
1119
1120#define B_VEND 0x3ff /* Vertical End Coordinates */
1121
1122/* Bit masks for PIXC_BTRANSP */
1123
1124#define B_TRANSP 0xf /* Transparency Value */
1125
1126/* Bit masks for PIXC_INTRSTAT */
1127
1128#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */
1129#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */
1130#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */
1131#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */
1132
1133/* Bit masks for PIXC_RYCON */
1134
1135#define A11 0x3ff /* A11 in the Coefficient Matrix */
1136#define A12 0xffc00 /* A12 in the Coefficient Matrix */
1137#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */
1138#define RY_MULT4 0x40000000 /* Multiply Row by 4 */
1139
1140/* Bit masks for PIXC_GUCON */
1141
1142#define A21 0x3ff /* A21 in the Coefficient Matrix */
1143#define A22 0xffc00 /* A22 in the Coefficient Matrix */
1144#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */
1145#define GU_MULT4 0x40000000 /* Multiply Row by 4 */
1146
1147/* Bit masks for PIXC_BVCON */
1148
1149#define A31 0x3ff /* A31 in the Coefficient Matrix */
1150#define A32 0xffc00 /* A32 in the Coefficient Matrix */
1151#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */
1152#define BV_MULT4 0x40000000 /* Multiply Row by 4 */
1153
1154/* Bit masks for PIXC_CCBIAS */
1155
1156#define A14 0x3ff /* A14 in the Bias Vector */
1157#define A24 0xffc00 /* A24 in the Bias Vector */
1158#define A34 0x3ff00000 /* A34 in the Bias Vector */
1159
1160/* Bit masks for PIXC_TC */
1161
1162#define RY_TRANS 0xff /* Transparent Color - R/Y Component */
1163#define GU_TRANS 0xff00 /* Transparent Color - G/U Component */
1164#define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */
1165
1166/* Bit masks for HOST_CONTROL */
1167
1168#define HOST_EN 0x1 /* Host Enable */
1169#define HOST_END 0x2 /* Host Endianess */
1170#define DATA_SIZE 0x4 /* Data Size */
1171#define HOST_RST 0x8 /* Host Reset */
1172#define HRDY_OVR 0x20 /* Host Ready Override */
1173#define INT_MODE 0x40 /* Interrupt Mode */
1174#define BT_EN 0x80 /* Bus Timeout Enable */
1175#define EHW 0x100 /* Enable Host Write */
1176#define EHR 0x200 /* Enable Host Read */
1177#define BDR 0x400 /* Burst DMA Requests */
1178
1179/* Bit masks for HOST_STATUS */
1180
1181#define DMA_READY 0x1 /* DMA Ready */
1182#define FIFOFULL 0x2 /* FIFO Full */
1183#define FIFOEMPTY 0x4 /* FIFO Empty */
1184#define DMA_COMPLETE 0x8 /* DMA Complete */
1185#define HSHK 0x10 /* Host Handshake */
1186#define TIMEOUT 0x20 /* Host Timeout */
1187#define HIRQ 0x40 /* Host Interrupt Request */
1188#define ALLOW_CNFG 0x80 /* Allow New Configuration */
1189#define DMA_DIR 0x100 /* DMA Direction */
1190#define BTE 0x200 /* Bus Timeout Enabled */
1191
1192/* Bit masks for HOST_TIMEOUT */
1193
1194#define COUNT_TIMEOUT 0x7ff /* Host Timeout count */
1195
1196/* Bit masks for MXVR_CONFIG */
1197
1198#define MXVREN 0x1 /* MXVR Enable */
1199#define MMSM 0x2 /* MXVR Master/Slave Mode Select */
1200#define ACTIVE 0x4 /* Active Mode */
1201#define SDELAY 0x8 /* Synchronous Data Delay */
1202#define NCMRXEN 0x10 /* Normal Control Message Receive Enable */
1203#define RWRRXEN 0x20 /* Remote Write Receive Enable */
1204#define MTXEN 0x40 /* MXVR Transmit Data Enable */
1205#define MTXONB 0x80 /* MXVR Phy Transmitter On */
1206#define EPARITY 0x100 /* Even Parity Select */
1207#define MSB 0x1e00 /* Master Synchronous Boundary */
1208#define APRXEN 0x2000 /* Asynchronous Packet Receive Enable */
1209#define WAKEUP 0x4000 /* Wake-Up */
1210#define LMECH 0x8000 /* Lock Mechanism Select */
1211
1212/* Bit masks for MXVR_STATE_0 */
1213
1214#define NACT 0x1 /* Network Activity */
1215#define SBLOCK 0x2 /* Super Block Lock */
1216#define FMPLLST 0xc /* Frequency Multiply PLL SM State */
1217#define CDRPLLST 0xe0 /* Clock/Data Recovery PLL SM State */
1218#define APBSY 0x100 /* Asynchronous Packet Transmit Buffer Busy */
1219#define APARB 0x200 /* Asynchronous Packet Arbitrating */
1220#define APTX 0x400 /* Asynchronous Packet Transmitting */
1221#define APRX 0x800 /* Receiving Asynchronous Packet */
1222#define CMBSY 0x1000 /* Control Message Transmit Buffer Busy */
1223#define CMARB 0x2000 /* Control Message Arbitrating */
1224#define CMTX 0x4000 /* Control Message Transmitting */
1225#define CMRX 0x8000 /* Receiving Control Message */
1226#define MRXONB 0x10000 /* MRXONB Pin State */
1227#define RGSIP 0x20000 /* Remote Get Source In Progress */
1228#define DALIP 0x40000 /* Resource Deallocate In Progress */
1229#define ALIP 0x80000 /* Resource Allocate In Progress */
1230#define RRDIP 0x100000 /* Remote Read In Progress */
1231#define RWRIP 0x200000 /* Remote Write In Progress */
1232#define FLOCK 0x400000 /* Frame Lock */
1233#define BLOCK 0x800000 /* Block Lock */
1234#define RSB 0xf000000 /* Received Synchronous Boundary */
1235#define DERRNUM 0xf0000000 /* DMA Error Channel Number */
1236
1237/* Bit masks for MXVR_STATE_1 */
1238
1239#define SRXNUMB 0xf /* Synchronous Receive FIFO Number of Bytes */
1240#define STXNUMB 0xf0 /* Synchronous Transmit FIFO Number of Bytes */
1241#define APCONT 0x100 /* Asynchronous Packet Continuation */
1242#define OBERRNUM 0xe00 /* DMA Out of Bounds Error Channel Number */
1243#define DMAACTIVE0 0x10000 /* DMA0 Active */
1244#define DMAACTIVE1 0x20000 /* DMA1 Active */
1245#define DMAACTIVE2 0x40000 /* DMA2 Active */
1246#define DMAACTIVE3 0x80000 /* DMA3 Active */
1247#define DMAACTIVE4 0x100000 /* DMA4 Active */
1248#define DMAACTIVE5 0x200000 /* DMA5 Active */
1249#define DMAACTIVE6 0x400000 /* DMA6 Active */
1250#define DMAACTIVE7 0x800000 /* DMA7 Active */
1251#define DMAPMEN0 0x1000000 /* DMA0 Pattern Matching Enabled */
1252#define DMAPMEN1 0x2000000 /* DMA1 Pattern Matching Enabled */
1253#define DMAPMEN2 0x4000000 /* DMA2 Pattern Matching Enabled */
1254#define DMAPMEN3 0x8000000 /* DMA3 Pattern Matching Enabled */
1255#define DMAPMEN4 0x10000000 /* DMA4 Pattern Matching Enabled */
1256#define DMAPMEN5 0x20000000 /* DMA5 Pattern Matching Enabled */
1257#define DMAPMEN6 0x40000000 /* DMA6 Pattern Matching Enabled */
1258#define DMAPMEN7 0x80000000 /* DMA7 Pattern Matching Enabled */
1259
1260/* Bit masks for MXVR_INT_STAT_0 */
1261
1262#define NI2A 0x1 /* Network Inactive to Active */
1263#define NA2I 0x2 /* Network Active to Inactive */
1264#define SBU2L 0x4 /* Super Block Unlock to Lock */
1265#define SBL2U 0x8 /* Super Block Lock to Unlock */
1266#define PRU 0x10 /* Position Register Updated */
1267#define MPRU 0x20 /* Maximum Position Register Updated */
1268#define DRU 0x40 /* Delay Register Updated */
1269#define MDRU 0x80 /* Maximum Delay Register Updated */
1270#define SBU 0x100 /* Synchronous Boundary Updated */
1271#define ATU 0x200 /* Allocation Table Updated */
1272#define FCZ0 0x400 /* Frame Counter 0 Zero */
1273#define FCZ1 0x800 /* Frame Counter 1 Zero */
1274#define PERR 0x1000 /* Parity Error */
1275#define MH2L 0x2000 /* MRXONB High to Low */
1276#define ML2H 0x4000 /* MRXONB Low to High */
1277#define WUP 0x8000 /* Wake-Up Preamble Received */
1278#define FU2L 0x10000 /* Frame Unlock to Lock */
1279#define FL2U 0x20000 /* Frame Lock to Unlock */
1280#define BU2L 0x40000 /* Block Unlock to Lock */
1281#define BL2U 0x80000 /* Block Lock to Unlock */
1282#define OBERR 0x100000 /* DMA Out of Bounds Error */
1283#define PFL 0x200000 /* PLL Frequency Locked */
1284#define SCZ 0x400000 /* System Clock Counter Zero */
1285#define FERR 0x800000 /* FIFO Error */
1286#define CMR 0x1000000 /* Control Message Received */
1287#define CMROF 0x2000000 /* Control Message Receive Buffer Overflow */
1288#define CMTS 0x4000000 /* Control Message Transmit Buffer Successfully Sent */
1289#define CMTC 0x8000000 /* Control Message Transmit Buffer Successfully Cancelled */
1290#define RWRC 0x10000000 /* Remote Write Control Message Completed */
1291#define BCZ 0x20000000 /* Block Counter Zero */
1292#define BMERR 0x40000000 /* Biphase Mark Coding Error */
1293#define DERR 0x80000000 /* DMA Error */
1294
1295/* Bit masks for MXVR_INT_STAT_1 */
1296
1297#define HDONE0 0x1 /* DMA0 Half Done */
1298#define DONE0 0x2 /* DMA0 Done */
1299#define APR 0x4 /* Asynchronous Packet Received */
1300#define APROF 0x8 /* Asynchronous Packet Receive Buffer Overflow */
1301#define HDONE1 0x10 /* DMA1 Half Done */
1302#define DONE1 0x20 /* DMA1 Done */
1303#define APTS 0x40 /* Asynchronous Packet Transmit Buffer Successfully Sent */
1304#define APTC 0x80 /* Asynchronous Packet Transmit Buffer Successfully Cancelled */
1305#define HDONE2 0x100 /* DMA2 Half Done */
1306#define DONE2 0x200 /* DMA2 Done */
1307#define APRCE 0x400 /* Asynchronous Packet Receive CRC Error */
1308#define APRPE 0x800 /* Asynchronous Packet Receive Packet Error */
1309#define HDONE3 0x1000 /* DMA3 Half Done */
1310#define DONE3 0x2000 /* DMA3 Done */
1311#define HDONE4 0x10000 /* DMA4 Half Done */
1312#define DONE4 0x20000 /* DMA4 Done */
1313#define HDONE5 0x100000 /* DMA5 Half Done */
1314#define DONE5 0x200000 /* DMA5 Done */
1315#define HDONE6 0x1000000 /* DMA6 Half Done */
1316#define DONE6 0x2000000 /* DMA6 Done */
1317#define HDONE7 0x10000000 /* DMA7 Half Done */
1318#define DONE7 0x20000000 /* DMA7 Done */
1319
1320/* Bit masks for MXVR_INT_EN_0 */
1321
1322#define NI2AEN 0x1 /* Network Inactive to Active Interrupt Enable */
1323#define NA2IEN 0x2 /* Network Active to Inactive Interrupt Enable */
1324#define SBU2LEN 0x4 /* Super Block Unlock to Lock Interrupt Enable */
1325#define SBL2UEN 0x8 /* Super Block Lock to Unlock Interrupt Enable */
1326#define PRUEN 0x10 /* Position Register Updated Interrupt Enable */
1327#define MPRUEN 0x20 /* Maximum Position Register Updated Interrupt Enable */
1328#define DRUEN 0x40 /* Delay Register Updated Interrupt Enable */
1329#define MDRUEN 0x80 /* Maximum Delay Register Updated Interrupt Enable */
1330#define SBUEN 0x100 /* Synchronous Boundary Updated Interrupt Enable */
1331#define ATUEN 0x200 /* Allocation Table Updated Interrupt Enable */
1332#define FCZ0EN 0x400 /* Frame Counter 0 Zero Interrupt Enable */
1333#define FCZ1EN 0x800 /* Frame Counter 1 Zero Interrupt Enable */
1334#define PERREN 0x1000 /* Parity Error Interrupt Enable */
1335#define MH2LEN 0x2000 /* MRXONB High to Low Interrupt Enable */
1336#define ML2HEN 0x4000 /* MRXONB Low to High Interrupt Enable */
1337#define WUPEN 0x8000 /* Wake-Up Preamble Received Interrupt Enable */
1338#define FU2LEN 0x10000 /* Frame Unlock to Lock Interrupt Enable */
1339#define FL2UEN 0x20000 /* Frame Lock to Unlock Interrupt Enable */
1340#define BU2LEN 0x40000 /* Block Unlock to Lock Interrupt Enable */
1341#define BL2UEN 0x80000 /* Block Lock to Unlock Interrupt Enable */
1342#define OBERREN 0x100000 /* DMA Out of Bounds Error Interrupt Enable */
1343#define PFLEN 0x200000 /* PLL Frequency Locked Interrupt Enable */
1344#define SCZEN 0x400000 /* System Clock Counter Zero Interrupt Enable */
1345#define FERREN 0x800000 /* FIFO Error Interrupt Enable */
1346#define CMREN 0x1000000 /* Control Message Received Interrupt Enable */
1347#define CMROFEN 0x2000000 /* Control Message Receive Buffer Overflow Interrupt Enable */
1348#define CMTSEN 0x4000000 /* Control Message Transmit Buffer Successfully Sent Interrupt Enable */
1349#define CMTCEN 0x8000000 /* Control Message Transmit Buffer Successfully Cancelled Interrupt Enable */
1350#define RWRCEN 0x10000000 /* Remote Write Control Message Completed Interrupt Enable */
1351#define BCZEN 0x20000000 /* Block Counter Zero Interrupt Enable */
1352#define BMERREN 0x40000000 /* Biphase Mark Coding Error Interrupt Enable */
1353#define DERREN 0x80000000 /* DMA Error Interrupt Enable */
1354
1355/* Bit masks for MXVR_INT_EN_1 */
1356
1357#define HDONEEN0 0x1 /* DMA0 Half Done Interrupt Enable */
1358#define DONEEN0 0x2 /* DMA0 Done Interrupt Enable */
1359#define APREN 0x4 /* Asynchronous Packet Received Interrupt Enable */
1360#define APROFEN 0x8 /* Asynchronous Packet Receive Buffer Overflow Interrupt Enable */
1361#define HDONEEN1 0x10 /* DMA1 Half Done Interrupt Enable */
1362#define DONEEN1 0x20 /* DMA1 Done Interrupt Enable */
1363#define APTSEN 0x40 /* Asynchronous Packet Transmit Buffer Successfully Sent Interrupt Enable */
1364#define APTCEN 0x80 /* Asynchronous Packet Transmit Buffer Successfully Cancelled Interrupt Enable */
1365#define HDONEEN2 0x100 /* DMA2 Half Done Interrupt Enable */
1366#define DONEEN2 0x200 /* DMA2 Done Interrupt Enable */
1367#define APRCEEN 0x400 /* Asynchronous Packet Receive CRC Error Interrupt Enable */
1368#define APRPEEN 0x800 /* Asynchronous Packet Receive Packet Error Interrupt Enable */
1369#define HDONEEN3 0x1000 /* DMA3 Half Done Interrupt Enable */
1370#define DONEEN3 0x2000 /* DMA3 Done Interrupt Enable */
1371#define HDONEEN4 0x10000 /* DMA4 Half Done Interrupt Enable */
1372#define DONEEN4 0x20000 /* DMA4 Done Interrupt Enable */
1373#define HDONEEN5 0x100000 /* DMA5 Half Done Interrupt Enable */
1374#define DONEEN5 0x200000 /* DMA5 Done Interrupt Enable */
1375#define HDONEEN6 0x1000000 /* DMA6 Half Done Interrupt Enable */
1376#define DONEEN6 0x2000000 /* DMA6 Done Interrupt Enable */
1377#define HDONEEN7 0x10000000 /* DMA7 Half Done Interrupt Enable */
1378#define DONEEN7 0x20000000 /* DMA7 Done Interrupt Enable */
1379
1380/* Bit masks for MXVR_POSITION */
1381
1382#define POSITION 0x3f /* Node Position */
1383#define PVALID 0x8000 /* Node Position Valid */
1384
1385/* Bit masks for MXVR_MAX_POSITION */
1386
1387#define MPOSITION 0x3f /* Maximum Node Position */
1388#define MPVALID 0x8000 /* Maximum Node Position Valid */
1389
1390/* Bit masks for MXVR_DELAY */
1391
1392#define DELAY 0x3f /* Node Frame Delay */
1393#define DVALID 0x8000 /* Node Frame Delay Valid */
1394
1395/* Bit masks for MXVR_MAX_DELAY */
1396
1397#define MDELAY 0x3f /* Maximum Node Frame Delay */
1398#define MDVALID 0x8000 /* Maximum Node Frame Delay Valid */
1399
1400/* Bit masks for MXVR_LADDR */
1401
1402#define LADDR 0xffff /* Logical Address */
1403#define LVALID 0x80000000 /* Logical Address Valid */
1404
1405/* Bit masks for MXVR_GADDR */
1406
1407#define GADDRL 0xff /* Group Address Lower Byte */
1408#define GVALID 0x8000 /* Group Address Valid */
1409
1410/* Bit masks for MXVR_AADDR */
1411
1412#define AADDR 0xffff /* Alternate Address */
1413#define AVALID 0x80000000 /* Alternate Address Valid */
1414
1415/* Bit masks for MXVR_ALLOC_0 */
1416
1417#define CL0 0x7f /* Channel 0 Connection Label */
1418#define CIU0 0x80 /* Channel 0 In Use */
1419#define CL1 0x7f00 /* Channel 0 Connection Label */
1420#define CIU1 0x8000 /* Channel 0 In Use */
1421#define CL2 0x7f0000 /* Channel 0 Connection Label */
1422#define CIU2 0x800000 /* Channel 0 In Use */
1423#define CL3 0x7f000000 /* Channel 0 Connection Label */
1424#define CIU3 0x80000000 /* Channel 0 In Use */
1425
1426/* Bit masks for MXVR_ALLOC_1 */
1427
1428#define CL4 0x7f /* Channel 4 Connection Label */
1429#define CIU4 0x80 /* Channel 4 In Use */
1430#define CL5 0x7f00 /* Channel 5 Connection Label */
1431#define CIU5 0x8000 /* Channel 5 In Use */
1432#define CL6 0x7f0000 /* Channel 6 Connection Label */
1433#define CIU6 0x800000 /* Channel 6 In Use */
1434#define CL7 0x7f000000 /* Channel 7 Connection Label */
1435#define CIU7 0x80000000 /* Channel 7 In Use */
1436
1437/* Bit masks for MXVR_ALLOC_2 */
1438
1439#define CL8 0x7f /* Channel 8 Connection Label */
1440#define CIU8 0x80 /* Channel 8 In Use */
1441#define CL9 0x7f00 /* Channel 9 Connection Label */
1442#define CIU9 0x8000 /* Channel 9 In Use */
1443#define CL10 0x7f0000 /* Channel 10 Connection Label */
1444#define CIU10 0x800000 /* Channel 10 In Use */
1445#define CL11 0x7f000000 /* Channel 11 Connection Label */
1446#define CIU11 0x80000000 /* Channel 11 In Use */
1447
1448/* Bit masks for MXVR_ALLOC_3 */
1449
1450#define CL12 0x7f /* Channel 12 Connection Label */
1451#define CIU12 0x80 /* Channel 12 In Use */
1452#define CL13 0x7f00 /* Channel 13 Connection Label */
1453#define CIU13 0x8000 /* Channel 13 In Use */
1454#define CL14 0x7f0000 /* Channel 14 Connection Label */
1455#define CIU14 0x800000 /* Channel 14 In Use */
1456#define CL15 0x7f000000 /* Channel 15 Connection Label */
1457#define CIU15 0x80000000 /* Channel 15 In Use */
1458
1459/* Bit masks for MXVR_ALLOC_4 */
1460
1461#define CL16 0x7f /* Channel 16 Connection Label */
1462#define CIU16 0x80 /* Channel 16 In Use */
1463#define CL17 0x7f00 /* Channel 17 Connection Label */
1464#define CIU17 0x8000 /* Channel 17 In Use */
1465#define CL18 0x7f0000 /* Channel 18 Connection Label */
1466#define CIU18 0x800000 /* Channel 18 In Use */
1467#define CL19 0x7f000000 /* Channel 19 Connection Label */
1468#define CIU19 0x80000000 /* Channel 19 In Use */
1469
1470/* Bit masks for MXVR_ALLOC_5 */
1471
1472#define CL20 0x7f /* Channel 20 Connection Label */
1473#define CIU20 0x80 /* Channel 20 In Use */
1474#define CL21 0x7f00 /* Channel 21 Connection Label */
1475#define CIU21 0x8000 /* Channel 21 In Use */
1476#define CL22 0x7f0000 /* Channel 22 Connection Label */
1477#define CIU22 0x800000 /* Channel 22 In Use */
1478#define CL23 0x7f000000 /* Channel 23 Connection Label */
1479#define CIU23 0x80000000 /* Channel 23 In Use */
1480
1481/* Bit masks for MXVR_ALLOC_6 */
1482
1483#define CL24 0x7f /* Channel 24 Connection Label */
1484#define CIU24 0x80 /* Channel 24 In Use */
1485#define CL25 0x7f00 /* Channel 25 Connection Label */
1486#define CIU25 0x8000 /* Channel 25 In Use */
1487#define CL26 0x7f0000 /* Channel 26 Connection Label */
1488#define CIU26 0x800000 /* Channel 26 In Use */
1489#define CL27 0x7f000000 /* Channel 27 Connection Label */
1490#define CIU27 0x80000000 /* Channel 27 In Use */
1491
1492/* Bit masks for MXVR_ALLOC_7 */
1493
1494#define CL28 0x7f /* Channel 28 Connection Label */
1495#define CIU28 0x80 /* Channel 28 In Use */
1496#define CL29 0x7f00 /* Channel 29 Connection Label */
1497#define CIU29 0x8000 /* Channel 29 In Use */
1498#define CL30 0x7f0000 /* Channel 30 Connection Label */
1499#define CIU30 0x800000 /* Channel 30 In Use */
1500#define CL31 0x7f000000 /* Channel 31 Connection Label */
1501#define CIU31 0x80000000 /* Channel 31 In Use */
1502
1503/* Bit masks for MXVR_ALLOC_8 */
1504
1505#define CL32 0x7f /* Channel 32 Connection Label */
1506#define CIU32 0x80 /* Channel 32 In Use */
1507#define CL33 0x7f00 /* Channel 33 Connection Label */
1508#define CIU33 0x8000 /* Channel 33 In Use */
1509#define CL34 0x7f0000 /* Channel 34 Connection Label */
1510#define CIU34 0x800000 /* Channel 34 In Use */
1511#define CL35 0x7f000000 /* Channel 35 Connection Label */
1512#define CIU35 0x80000000 /* Channel 35 In Use */
1513
1514/* Bit masks for MXVR_ALLOC_9 */
1515
1516#define CL36 0x7f /* Channel 36 Connection Label */
1517#define CIU36 0x80 /* Channel 36 In Use */
1518#define CL37 0x7f00 /* Channel 37 Connection Label */
1519#define CIU37 0x8000 /* Channel 37 In Use */
1520#define CL38 0x7f0000 /* Channel 38 Connection Label */
1521#define CIU38 0x800000 /* Channel 38 In Use */
1522#define CL39 0x7f000000 /* Channel 39 Connection Label */
1523#define CIU39 0x80000000 /* Channel 39 In Use */
1524
1525/* Bit masks for MXVR_ALLOC_10 */
1526
1527#define CL40 0x7f /* Channel 40 Connection Label */
1528#define CIU40 0x80 /* Channel 40 In Use */
1529#define CL41 0x7f00 /* Channel 41 Connection Label */
1530#define CIU41 0x8000 /* Channel 41 In Use */
1531#define CL42 0x7f0000 /* Channel 42 Connection Label */
1532#define CIU42 0x800000 /* Channel 42 In Use */
1533#define CL43 0x7f000000 /* Channel 43 Connection Label */
1534#define CIU43 0x80000000 /* Channel 43 In Use */
1535
1536/* Bit masks for MXVR_ALLOC_11 */
1537
1538#define CL44 0x7f /* Channel 44 Connection Label */
1539#define CIU44 0x80 /* Channel 44 In Use */
1540#define CL45 0x7f00 /* Channel 45 Connection Label */
1541#define CIU45 0x8000 /* Channel 45 In Use */
1542#define CL46 0x7f0000 /* Channel 46 Connection Label */
1543#define CIU46 0x800000 /* Channel 46 In Use */
1544#define CL47 0x7f000000 /* Channel 47 Connection Label */
1545#define CIU47 0x80000000 /* Channel 47 In Use */
1546
1547/* Bit masks for MXVR_ALLOC_12 */
1548
1549#define CL48 0x7f /* Channel 48 Connection Label */
1550#define CIU48 0x80 /* Channel 48 In Use */
1551#define CL49 0x7f00 /* Channel 49 Connection Label */
1552#define CIU49 0x8000 /* Channel 49 In Use */
1553#define CL50 0x7f0000 /* Channel 50 Connection Label */
1554#define CIU50 0x800000 /* Channel 50 In Use */
1555#define CL51 0x7f000000 /* Channel 51 Connection Label */
1556#define CIU51 0x80000000 /* Channel 51 In Use */
1557
1558/* Bit masks for MXVR_ALLOC_13 */
1559
1560#define CL52 0x7f /* Channel 52 Connection Label */
1561#define CIU52 0x80 /* Channel 52 In Use */
1562#define CL53 0x7f00 /* Channel 53 Connection Label */
1563#define CIU53 0x8000 /* Channel 53 In Use */
1564#define CL54 0x7f0000 /* Channel 54 Connection Label */
1565#define CIU54 0x800000 /* Channel 54 In Use */
1566#define CL55 0x7f000000 /* Channel 55 Connection Label */
1567#define CIU55 0x80000000 /* Channel 55 In Use */
1568
1569/* Bit masks for MXVR_ALLOC_14 */
1570
1571#define CL56 0x7f /* Channel 56 Connection Label */
1572#define CIU56 0x80 /* Channel 56 In Use */
1573#define CL57 0x7f00 /* Channel 57 Connection Label */
1574#define CIU57 0x8000 /* Channel 57 In Use */
1575#define CL58 0x7f0000 /* Channel 58 Connection Label */
1576#define CIU58 0x800000 /* Channel 58 In Use */
1577#define CL59 0x7f000000 /* Channel 59 Connection Label */
1578#define CIU59 0x80000000 /* Channel 59 In Use */
1579
1580/* MXVR_SYNC_LCHAN_0 Masks */
1581
1582#define LCHANPC0 0x0000000Flu
1583#define LCHANPC1 0x000000F0lu
1584#define LCHANPC2 0x00000F00lu
1585#define LCHANPC3 0x0000F000lu
1586#define LCHANPC4 0x000F0000lu
1587#define LCHANPC5 0x00F00000lu
1588#define LCHANPC6 0x0F000000lu
1589#define LCHANPC7 0xF0000000lu
1590
1591
1592/* MXVR_SYNC_LCHAN_1 Masks */
1593
1594#define LCHANPC8 0x0000000Flu
1595#define LCHANPC9 0x000000F0lu
1596#define LCHANPC10 0x00000F00lu
1597#define LCHANPC11 0x0000F000lu
1598#define LCHANPC12 0x000F0000lu
1599#define LCHANPC13 0x00F00000lu
1600#define LCHANPC14 0x0F000000lu
1601#define LCHANPC15 0xF0000000lu
1602
1603
1604/* MXVR_SYNC_LCHAN_2 Masks */
1605
1606#define LCHANPC16 0x0000000Flu
1607#define LCHANPC17 0x000000F0lu
1608#define LCHANPC18 0x00000F00lu
1609#define LCHANPC19 0x0000F000lu
1610#define LCHANPC20 0x000F0000lu
1611#define LCHANPC21 0x00F00000lu
1612#define LCHANPC22 0x0F000000lu
1613#define LCHANPC23 0xF0000000lu
1614
1615
1616/* MXVR_SYNC_LCHAN_3 Masks */
1617
1618#define LCHANPC24 0x0000000Flu
1619#define LCHANPC25 0x000000F0lu
1620#define LCHANPC26 0x00000F00lu
1621#define LCHANPC27 0x0000F000lu
1622#define LCHANPC28 0x000F0000lu
1623#define LCHANPC29 0x00F00000lu
1624#define LCHANPC30 0x0F000000lu
1625#define LCHANPC31 0xF0000000lu
1626
1627
1628/* MXVR_SYNC_LCHAN_4 Masks */
1629
1630#define LCHANPC32 0x0000000Flu
1631#define LCHANPC33 0x000000F0lu
1632#define LCHANPC34 0x00000F00lu
1633#define LCHANPC35 0x0000F000lu
1634#define LCHANPC36 0x000F0000lu
1635#define LCHANPC37 0x00F00000lu
1636#define LCHANPC38 0x0F000000lu
1637#define LCHANPC39 0xF0000000lu
1638
1639
1640/* MXVR_SYNC_LCHAN_5 Masks */
1641
1642#define LCHANPC40 0x0000000Flu
1643#define LCHANPC41 0x000000F0lu
1644#define LCHANPC42 0x00000F00lu
1645#define LCHANPC43 0x0000F000lu
1646#define LCHANPC44 0x000F0000lu
1647#define LCHANPC45 0x00F00000lu
1648#define LCHANPC46 0x0F000000lu
1649#define LCHANPC47 0xF0000000lu
1650
1651
1652/* MXVR_SYNC_LCHAN_6 Masks */
1653
1654#define LCHANPC48 0x0000000Flu
1655#define LCHANPC49 0x000000F0lu
1656#define LCHANPC50 0x00000F00lu
1657#define LCHANPC51 0x0000F000lu
1658#define LCHANPC52 0x000F0000lu
1659#define LCHANPC53 0x00F00000lu
1660#define LCHANPC54 0x0F000000lu
1661#define LCHANPC55 0xF0000000lu
1662
1663
1664/* MXVR_SYNC_LCHAN_7 Masks */
1665
1666#define LCHANPC56 0x0000000Flu
1667#define LCHANPC57 0x000000F0lu
1668#define LCHANPC58 0x00000F00lu
1669#define LCHANPC59 0x0000F000lu
1670
1671/* Bit masks for MXVR_DMAx_CONFIG */
1672
1673#define MDMAEN 0x1 /* DMA Channel Enable */
1674#define DMADD 0x2 /* DMA Channel Direction */
1675#define BY4SWAPEN 0x20 /* DMA Channel Four Byte Swap Enable */
1676#define LCHAN 0x3c0 /* DMA Channel Logical Channel */
1677#define BITSWAPEN 0x400 /* DMA Channel Bit Swap Enable */
1678#define BY2SWAPEN 0x800 /* DMA Channel Two Byte Swap Enable */
1679#define MFLOW 0x7000 /* DMA Channel Operation Flow */
1680#define FIXEDPM 0x80000 /* DMA Channel Fixed Pattern Matching Select */
1681#define STARTPAT 0x300000 /* DMA Channel Start Pattern Select */
1682#define STOPPAT 0xc00000 /* DMA Channel Stop Pattern Select */
1683#define COUNTPOS 0x1c000000 /* DMA Channel Count Position */
1684
1685/* Bit masks for MXVR_AP_CTL */
1686
1687#define STARTAP 0x1 /* Start Asynchronous Packet Transmission */
1688#define CANCELAP 0x2 /* Cancel Asynchronous Packet Transmission */
1689#define RESETAP 0x4 /* Reset Asynchronous Packet Arbitration */
1690#define APRBE0 0x4000 /* Asynchronous Packet Receive Buffer Entry 0 */
1691#define APRBE1 0x8000 /* Asynchronous Packet Receive Buffer Entry 1 */
1692
1693/* Bit masks for MXVR_APRB_START_ADDR */
1694
1695#define MXVR_APRB_START_ADDR_MASK 0x1fffffe /* Asynchronous Packet Receive Buffer Start Address */
1696
1697/* Bit masks for MXVR_APRB_CURR_ADDR */
1698
1699#define MXVR_APRB_CURR_ADDR_MASK 0xffffffff /* Asynchronous Packet Receive Buffer Current Address */
1700
1701/* Bit masks for MXVR_APTB_START_ADDR */
1702
1703#define MXVR_APTB_START_ADDR_MASK 0x1fffffe /* Asynchronous Packet Transmit Buffer Start Address */
1704
1705/* Bit masks for MXVR_APTB_CURR_ADDR */
1706
1707#define MXVR_APTB_CURR_ADDR_MASK 0xffffffff /* Asynchronous Packet Transmit Buffer Current Address */
1708
1709/* Bit masks for MXVR_CM_CTL */
1710
1711#define STARTCM 0x1 /* Start Control Message Transmission */
1712#define CANCELCM 0x2 /* Cancel Control Message Transmission */
1713#define CMRBE0 0x10000 /* Control Message Receive Buffer Entry 0 */
1714#define CMRBE1 0x20000 /* Control Message Receive Buffer Entry 1 */
1715#define CMRBE2 0x40000 /* Control Message Receive Buffer Entry 2 */
1716#define CMRBE3 0x80000 /* Control Message Receive Buffer Entry 3 */
1717#define CMRBE4 0x100000 /* Control Message Receive Buffer Entry 4 */
1718#define CMRBE5 0x200000 /* Control Message Receive Buffer Entry 5 */
1719#define CMRBE6 0x400000 /* Control Message Receive Buffer Entry 6 */
1720#define CMRBE7 0x800000 /* Control Message Receive Buffer Entry 7 */
1721#define CMRBE8 0x1000000 /* Control Message Receive Buffer Entry 8 */
1722#define CMRBE9 0x2000000 /* Control Message Receive Buffer Entry 9 */
1723#define CMRBE10 0x4000000 /* Control Message Receive Buffer Entry 10 */
1724#define CMRBE11 0x8000000 /* Control Message Receive Buffer Entry 11 */
1725#define CMRBE12 0x10000000 /* Control Message Receive Buffer Entry 12 */
1726#define CMRBE13 0x20000000 /* Control Message Receive Buffer Entry 13 */
1727#define CMRBE14 0x40000000 /* Control Message Receive Buffer Entry 14 */
1728#define CMRBE15 0x80000000 /* Control Message Receive Buffer Entry 15 */
1729
1730/* Bit masks for MXVR_CMRB_START_ADDR */
1731
1732#define MXVR_CMRB_START_ADDR_MASK 0x1fffffe /* Control Message Receive Buffer Start Address */
1733
1734/* Bit masks for MXVR_CMRB_CURR_ADDR */
1735
1736#define MXVR_CMRB_CURR_ADDR_MASK 0xffffffff /* Control Message Receive Buffer Current Address */
1737
1738/* Bit masks for MXVR_CMTB_START_ADDR */
1739
1740#define MXVR_CMTB_START_ADDR_MASK 0x1fffffe /* Control Message Transmit Buffer Start Address */
1741
1742/* Bit masks for MXVR_CMTB_CURR_ADDR */
1743
1744#define MXVR_CMTB_CURR_ADDR_MASK 0xffffffff /* Control Message Transmit Buffer Current Address */
1745
1746/* Bit masks for MXVR_RRDB_START_ADDR */
1747
1748#define MXVR_RRDB_START_ADDR_MASK 0x1fffffe /* Remote Read Buffer Start Address */
1749
1750/* Bit masks for MXVR_RRDB_CURR_ADDR */
1751
1752#define MXVR_RRDB_CURR_ADDR_MASK 0xffffffff /* Remote Read Buffer Current Address */
1753
1754/* Bit masks for MXVR_PAT_DATAx */
1755
1756#define MATCH_DATA_0 0xff /* Pattern Match Data Byte 0 */
1757#define MATCH_DATA_1 0xff00 /* Pattern Match Data Byte 1 */
1758#define MATCH_DATA_2 0xff0000 /* Pattern Match Data Byte 2 */
1759#define MATCH_DATA_3 0xff000000 /* Pattern Match Data Byte 3 */
1760
1761/* Bit masks for MXVR_PAT_EN_0 */
1762
1763#define MATCH_EN_0_0 0x1 /* Pattern Match Enable Byte 0 Bit 0 */
1764#define MATCH_EN_0_1 0x2 /* Pattern Match Enable Byte 0 Bit 1 */
1765#define MATCH_EN_0_2 0x4 /* Pattern Match Enable Byte 0 Bit 2 */
1766#define MATCH_EN_0_3 0x8 /* Pattern Match Enable Byte 0 Bit 3 */
1767#define MATCH_EN_0_4 0x10 /* Pattern Match Enable Byte 0 Bit 4 */
1768#define MATCH_EN_0_5 0x20 /* Pattern Match Enable Byte 0 Bit 5 */
1769#define MATCH_EN_0_6 0x40 /* Pattern Match Enable Byte 0 Bit 6 */
1770#define MATCH_EN_0_7 0x80 /* Pattern Match Enable Byte 0 Bit 7 */
1771#define MATCH_EN_1_0 0x100 /* Pattern Match Enable Byte 1 Bit 0 */
1772#define MATCH_EN_1_1 0x200 /* Pattern Match Enable Byte 1 Bit 1 */
1773#define MATCH_EN_1_2 0x400 /* Pattern Match Enable Byte 1 Bit 2 */
1774#define MATCH_EN_1_3 0x800 /* Pattern Match Enable Byte 1 Bit 3 */
1775#define MATCH_EN_1_4 0x1000 /* Pattern Match Enable Byte 1 Bit 4 */
1776#define MATCH_EN_1_5 0x2000 /* Pattern Match Enable Byte 1 Bit 5 */
1777#define MATCH_EN_1_6 0x4000 /* Pattern Match Enable Byte 1 Bit 6 */
1778#define MATCH_EN_1_7 0x8000 /* Pattern Match Enable Byte 1 Bit 7 */
1779#define MATCH_EN_2_0 0x10000 /* Pattern Match Enable Byte 2 Bit 0 */
1780#define MATCH_EN_2_1 0x20000 /* Pattern Match Enable Byte 2 Bit 1 */
1781#define MATCH_EN_2_2 0x40000 /* Pattern Match Enable Byte 2 Bit 2 */
1782#define MATCH_EN_2_3 0x80000 /* Pattern Match Enable Byte 2 Bit 3 */
1783#define MATCH_EN_2_4 0x100000 /* Pattern Match Enable Byte 2 Bit 4 */
1784#define MATCH_EN_2_5 0x200000 /* Pattern Match Enable Byte 2 Bit 5 */
1785#define MATCH_EN_2_6 0x400000 /* Pattern Match Enable Byte 2 Bit 6 */
1786#define MATCH_EN_2_7 0x800000 /* Pattern Match Enable Byte 2 Bit 7 */
1787#define MATCH_EN_3_0 0x1000000 /* Pattern Match Enable Byte 3 Bit 0 */
1788#define MATCH_EN_3_1 0x2000000 /* Pattern Match Enable Byte 3 Bit 1 */
1789#define MATCH_EN_3_2 0x4000000 /* Pattern Match Enable Byte 3 Bit 2 */
1790#define MATCH_EN_3_3 0x8000000 /* Pattern Match Enable Byte 3 Bit 3 */
1791#define MATCH_EN_3_4 0x10000000 /* Pattern Match Enable Byte 3 Bit 4 */
1792#define MATCH_EN_3_5 0x20000000 /* Pattern Match Enable Byte 3 Bit 5 */
1793#define MATCH_EN_3_6 0x40000000 /* Pattern Match Enable Byte 3 Bit 6 */
1794#define MATCH_EN_3_7 0x80000000 /* Pattern Match Enable Byte 3 Bit 7 */
1795
1796/* Bit masks for MXVR_PAT_EN_1 */
1797
1798#define MATCH_EN_0_0 0x1 /* Pattern Match Enable Byte 0 Bit 0 */
1799#define MATCH_EN_0_1 0x2 /* Pattern Match Enable Byte 0 Bit 1 */
1800#define MATCH_EN_0_2 0x4 /* Pattern Match Enable Byte 0 Bit 2 */
1801#define MATCH_EN_0_3 0x8 /* Pattern Match Enable Byte 0 Bit 3 */
1802#define MATCH_EN_0_4 0x10 /* Pattern Match Enable Byte 0 Bit 4 */
1803#define MATCH_EN_0_5 0x20 /* Pattern Match Enable Byte 0 Bit 5 */
1804#define MATCH_EN_0_6 0x40 /* Pattern Match Enable Byte 0 Bit 6 */
1805#define MATCH_EN_0_7 0x80 /* Pattern Match Enable Byte 0 Bit 7 */
1806#define MATCH_EN_1_0 0x100 /* Pattern Match Enable Byte 1 Bit 0 */
1807#define MATCH_EN_1_1 0x200 /* Pattern Match Enable Byte 1 Bit 1 */
1808#define MATCH_EN_1_2 0x400 /* Pattern Match Enable Byte 1 Bit 2 */
1809#define MATCH_EN_1_3 0x800 /* Pattern Match Enable Byte 1 Bit 3 */
1810#define MATCH_EN_1_4 0x1000 /* Pattern Match Enable Byte 1 Bit 4 */
1811#define MATCH_EN_1_5 0x2000 /* Pattern Match Enable Byte 1 Bit 5 */
1812#define MATCH_EN_1_6 0x4000 /* Pattern Match Enable Byte 1 Bit 6 */
1813#define MATCH_EN_1_7 0x8000 /* Pattern Match Enable Byte 1 Bit 7 */
1814#define MATCH_EN_2_0 0x10000 /* Pattern Match Enable Byte 2 Bit 0 */
1815#define MATCH_EN_2_1 0x20000 /* Pattern Match Enable Byte 2 Bit 1 */
1816#define MATCH_EN_2_2 0x40000 /* Pattern Match Enable Byte 2 Bit 2 */
1817#define MATCH_EN_2_3 0x80000 /* Pattern Match Enable Byte 2 Bit 3 */
1818#define MATCH_EN_2_4 0x100000 /* Pattern Match Enable Byte 2 Bit 4 */
1819#define MATCH_EN_2_5 0x200000 /* Pattern Match Enable Byte 2 Bit 5 */
1820#define MATCH_EN_2_6 0x400000 /* Pattern Match Enable Byte 2 Bit 6 */
1821#define MATCH_EN_2_7 0x800000 /* Pattern Match Enable Byte 2 Bit 7 */
1822#define MATCH_EN_3_0 0x1000000 /* Pattern Match Enable Byte 3 Bit 0 */
1823#define MATCH_EN_3_1 0x2000000 /* Pattern Match Enable Byte 3 Bit 1 */
1824#define MATCH_EN_3_2 0x4000000 /* Pattern Match Enable Byte 3 Bit 2 */
1825#define MATCH_EN_3_3 0x8000000 /* Pattern Match Enable Byte 3 Bit 3 */
1826#define MATCH_EN_3_4 0x10000000 /* Pattern Match Enable Byte 3 Bit 4 */
1827#define MATCH_EN_3_5 0x20000000 /* Pattern Match Enable Byte 3 Bit 5 */
1828#define MATCH_EN_3_6 0x40000000 /* Pattern Match Enable Byte 3 Bit 6 */
1829#define MATCH_EN_3_7 0x80000000 /* Pattern Match Enable Byte 3 Bit 7 */
1830
1831/* Bit masks for MXVR_FRAME_CNT_0 */
1832
1833#define FCNT 0xffff /* Frame Count */
1834
1835/* Bit masks for MXVR_FRAME_CNT_1 */
1836
1837#define FCNT 0xffff /* Frame Count */
1838
1839/* Bit masks for MXVR_ROUTING_0 */
1840
1841#define TX_CH0 0x3f /* Transmit Channel 0 */
1842#define MUTE_CH0 0x80 /* Mute Channel 0 */
1843#define TX_CH1 0x3f00 /* Transmit Channel 0 */
1844#define MUTE_CH1 0x8000 /* Mute Channel 0 */
1845#define TX_CH2 0x3f0000 /* Transmit Channel 0 */
1846#define MUTE_CH2 0x800000 /* Mute Channel 0 */
1847#define TX_CH3 0x3f000000 /* Transmit Channel 0 */
1848#define MUTE_CH3 0x80000000 /* Mute Channel 0 */
1849
1850/* Bit masks for MXVR_ROUTING_1 */
1851
1852#define TX_CH4 0x3f /* Transmit Channel 4 */
1853#define MUTE_CH4 0x80 /* Mute Channel 4 */
1854#define TX_CH5 0x3f00 /* Transmit Channel 5 */
1855#define MUTE_CH5 0x8000 /* Mute Channel 5 */
1856#define TX_CH6 0x3f0000 /* Transmit Channel 6 */
1857#define MUTE_CH6 0x800000 /* Mute Channel 6 */
1858#define TX_CH7 0x3f000000 /* Transmit Channel 7 */
1859#define MUTE_CH7 0x80000000 /* Mute Channel 7 */
1860
1861/* Bit masks for MXVR_ROUTING_2 */
1862
1863#define TX_CH8 0x3f /* Transmit Channel 8 */
1864#define MUTE_CH8 0x80 /* Mute Channel 8 */
1865#define TX_CH9 0x3f00 /* Transmit Channel 9 */
1866#define MUTE_CH9 0x8000 /* Mute Channel 9 */
1867#define TX_CH10 0x3f0000 /* Transmit Channel 10 */
1868#define MUTE_CH10 0x800000 /* Mute Channel 10 */
1869#define TX_CH11 0x3f000000 /* Transmit Channel 11 */
1870#define MUTE_CH11 0x80000000 /* Mute Channel 11 */
1871
1872/* Bit masks for MXVR_ROUTING_3 */
1873
1874#define TX_CH12 0x3f /* Transmit Channel 12 */
1875#define MUTE_CH12 0x80 /* Mute Channel 12 */
1876#define TX_CH13 0x3f00 /* Transmit Channel 13 */
1877#define MUTE_CH13 0x8000 /* Mute Channel 13 */
1878#define TX_CH14 0x3f0000 /* Transmit Channel 14 */
1879#define MUTE_CH14 0x800000 /* Mute Channel 14 */
1880#define TX_CH15 0x3f000000 /* Transmit Channel 15 */
1881#define MUTE_CH15 0x80000000 /* Mute Channel 15 */
1882
1883/* Bit masks for MXVR_ROUTING_4 */
1884
1885#define TX_CH16 0x3f /* Transmit Channel 16 */
1886#define MUTE_CH16 0x80 /* Mute Channel 16 */
1887#define TX_CH17 0x3f00 /* Transmit Channel 17 */
1888#define MUTE_CH17 0x8000 /* Mute Channel 17 */
1889#define TX_CH18 0x3f0000 /* Transmit Channel 18 */
1890#define MUTE_CH18 0x800000 /* Mute Channel 18 */
1891#define TX_CH19 0x3f000000 /* Transmit Channel 19 */
1892#define MUTE_CH19 0x80000000 /* Mute Channel 19 */
1893
1894/* Bit masks for MXVR_ROUTING_5 */
1895
1896#define TX_CH20 0x3f /* Transmit Channel 20 */
1897#define MUTE_CH20 0x80 /* Mute Channel 20 */
1898#define TX_CH21 0x3f00 /* Transmit Channel 21 */
1899#define MUTE_CH21 0x8000 /* Mute Channel 21 */
1900#define TX_CH22 0x3f0000 /* Transmit Channel 22 */
1901#define MUTE_CH22 0x800000 /* Mute Channel 22 */
1902#define TX_CH23 0x3f000000 /* Transmit Channel 23 */
1903#define MUTE_CH23 0x80000000 /* Mute Channel 23 */
1904
1905/* Bit masks for MXVR_ROUTING_6 */
1906
1907#define TX_CH24 0x3f /* Transmit Channel 24 */
1908#define MUTE_CH24 0x80 /* Mute Channel 24 */
1909#define TX_CH25 0x3f00 /* Transmit Channel 25 */
1910#define MUTE_CH25 0x8000 /* Mute Channel 25 */
1911#define TX_CH26 0x3f0000 /* Transmit Channel 26 */
1912#define MUTE_CH26 0x800000 /* Mute Channel 26 */
1913#define TX_CH27 0x3f000000 /* Transmit Channel 27 */
1914#define MUTE_CH27 0x80000000 /* Mute Channel 27 */
1915
1916/* Bit masks for MXVR_ROUTING_7 */
1917
1918#define TX_CH28 0x3f /* Transmit Channel 28 */
1919#define MUTE_CH28 0x80 /* Mute Channel 28 */
1920#define TX_CH29 0x3f00 /* Transmit Channel 29 */
1921#define MUTE_CH29 0x8000 /* Mute Channel 29 */
1922#define TX_CH30 0x3f0000 /* Transmit Channel 30 */
1923#define MUTE_CH30 0x800000 /* Mute Channel 30 */
1924#define TX_CH31 0x3f000000 /* Transmit Channel 31 */
1925#define MUTE_CH31 0x80000000 /* Mute Channel 31 */
1926
1927/* Bit masks for MXVR_ROUTING_8 */
1928
1929#define TX_CH32 0x3f /* Transmit Channel 32 */
1930#define MUTE_CH32 0x80 /* Mute Channel 32 */
1931#define TX_CH33 0x3f00 /* Transmit Channel 33 */
1932#define MUTE_CH33 0x8000 /* Mute Channel 33 */
1933#define TX_CH34 0x3f0000 /* Transmit Channel 34 */
1934#define MUTE_CH34 0x800000 /* Mute Channel 34 */
1935#define TX_CH35 0x3f000000 /* Transmit Channel 35 */
1936#define MUTE_CH35 0x80000000 /* Mute Channel 35 */
1937
1938/* Bit masks for MXVR_ROUTING_9 */
1939
1940#define TX_CH36 0x3f /* Transmit Channel 36 */
1941#define MUTE_CH36 0x80 /* Mute Channel 36 */
1942#define TX_CH37 0x3f00 /* Transmit Channel 37 */
1943#define MUTE_CH37 0x8000 /* Mute Channel 37 */
1944#define TX_CH38 0x3f0000 /* Transmit Channel 38 */
1945#define MUTE_CH38 0x800000 /* Mute Channel 38 */
1946#define TX_CH39 0x3f000000 /* Transmit Channel 39 */
1947#define MUTE_CH39 0x80000000 /* Mute Channel 39 */
1948
1949/* Bit masks for MXVR_ROUTING_10 */
1950
1951#define TX_CH40 0x3f /* Transmit Channel 40 */
1952#define MUTE_CH40 0x80 /* Mute Channel 40 */
1953#define TX_CH41 0x3f00 /* Transmit Channel 41 */
1954#define MUTE_CH41 0x8000 /* Mute Channel 41 */
1955#define TX_CH42 0x3f0000 /* Transmit Channel 42 */
1956#define MUTE_CH42 0x800000 /* Mute Channel 42 */
1957#define TX_CH43 0x3f000000 /* Transmit Channel 43 */
1958#define MUTE_CH43 0x80000000 /* Mute Channel 43 */
1959
1960/* Bit masks for MXVR_ROUTING_11 */
1961
1962#define TX_CH44 0x3f /* Transmit Channel 44 */
1963#define MUTE_CH44 0x80 /* Mute Channel 44 */
1964#define TX_CH45 0x3f00 /* Transmit Channel 45 */
1965#define MUTE_CH45 0x8000 /* Mute Channel 45 */
1966#define TX_CH46 0x3f0000 /* Transmit Channel 46 */
1967#define MUTE_CH46 0x800000 /* Mute Channel 46 */
1968#define TX_CH47 0x3f000000 /* Transmit Channel 47 */
1969#define MUTE_CH47 0x80000000 /* Mute Channel 47 */
1970
1971/* Bit masks for MXVR_ROUTING_12 */
1972
1973#define TX_CH48 0x3f /* Transmit Channel 48 */
1974#define MUTE_CH48 0x80 /* Mute Channel 48 */
1975#define TX_CH49 0x3f00 /* Transmit Channel 49 */
1976#define MUTE_CH49 0x8000 /* Mute Channel 49 */
1977#define TX_CH50 0x3f0000 /* Transmit Channel 50 */
1978#define MUTE_CH50 0x800000 /* Mute Channel 50 */
1979#define TX_CH51 0x3f000000 /* Transmit Channel 51 */
1980#define MUTE_CH51 0x80000000 /* Mute Channel 51 */
1981
1982/* Bit masks for MXVR_ROUTING_13 */
1983
1984#define TX_CH52 0x3f /* Transmit Channel 52 */
1985#define MUTE_CH52 0x80 /* Mute Channel 52 */
1986#define TX_CH53 0x3f00 /* Transmit Channel 53 */
1987#define MUTE_CH53 0x8000 /* Mute Channel 53 */
1988#define TX_CH54 0x3f0000 /* Transmit Channel 54 */
1989#define MUTE_CH54 0x800000 /* Mute Channel 54 */
1990#define TX_CH55 0x3f000000 /* Transmit Channel 55 */
1991#define MUTE_CH55 0x80000000 /* Mute Channel 55 */
1992
1993/* Bit masks for MXVR_ROUTING_14 */
1994
1995#define TX_CH56 0x3f /* Transmit Channel 56 */
1996#define MUTE_CH56 0x80 /* Mute Channel 56 */
1997#define TX_CH57 0x3f00 /* Transmit Channel 57 */
1998#define MUTE_CH57 0x8000 /* Mute Channel 57 */
1999#define TX_CH58 0x3f0000 /* Transmit Channel 58 */
2000#define MUTE_CH58 0x800000 /* Mute Channel 58 */
2001#define TX_CH59 0x3f000000 /* Transmit Channel 59 */
2002#define MUTE_CH59 0x80000000 /* Mute Channel 59 */
2003
2004/* Bit masks for MXVR_BLOCK_CNT */
2005
2006#define BCNT 0xffff /* Block Count */
2007
2008/* Bit masks for MXVR_CLK_CTL */
2009
2010#define MXTALCEN 0x1 /* MXVR Crystal Oscillator Clock Enable */
2011#define MXTALFEN 0x2 /* MXVR Crystal Oscillator Feedback Enable */
2012#define MXTALMUL 0x30 /* MXVR Crystal Multiplier */
2013#define CLKX3SEL 0x80 /* Clock Generation Source Select */
2014#define MMCLKEN 0x100 /* Master Clock Enable */
2015#define MMCLKMUL 0x1e00 /* Master Clock Multiplication Factor */
2016#define PLLSMPS 0xe000 /* MXVR PLL State Machine Prescaler */
2017#define MBCLKEN 0x10000 /* Bit Clock Enable */
2018#define MBCLKDIV 0x1e0000 /* Bit Clock Divide Factor */
2019#define INVRX 0x800000 /* Invert Receive Data */
2020#define MFSEN 0x1000000 /* Frame Sync Enable */
2021#define MFSDIV 0x1e000000 /* Frame Sync Divide Factor */
2022#define MFSSEL 0x60000000 /* Frame Sync Select */
2023#define MFSSYNC 0x80000000 /* Frame Sync Synchronization Select */
2024
2025/* Bit masks for MXVR_CDRPLL_CTL */
2026
2027#define CDRSMEN 0x1 /* MXVR CDRPLL State Machine Enable */
2028#define CDRRSTB 0x2 /* MXVR CDRPLL Reset */
2029#define CDRSVCO 0x4 /* MXVR CDRPLL Start VCO */
2030#define CDRMODE 0x8 /* MXVR CDRPLL CDR Mode Select */
2031#define CDRSCNT 0x3f0 /* MXVR CDRPLL Start Counter */
2032#define CDRLCNT 0xfc00 /* MXVR CDRPLL Lock Counter */
2033#define CDRSHPSEL 0x3f0000 /* MXVR CDRPLL Shaper Select */
2034#define CDRSHPEN 0x800000 /* MXVR CDRPLL Shaper Enable */
2035#define CDRCPSEL 0xff000000 /* MXVR CDRPLL Charge Pump Current Select */
2036
2037/* Bit masks for MXVR_FMPLL_CTL */
2038
2039#define FMSMEN 0x1 /* MXVR FMPLL State Machine Enable */
2040#define FMRSTB 0x2 /* MXVR FMPLL Reset */
2041#define FMSVCO 0x4 /* MXVR FMPLL Start VCO */
2042#define FMSCNT 0x3f0 /* MXVR FMPLL Start Counter */
2043#define FMLCNT 0xfc00 /* MXVR FMPLL Lock Counter */
2044#define FMCPSEL 0xff000000 /* MXVR FMPLL Charge Pump Current Select */
2045
2046/* Bit masks for MXVR_PIN_CTL */
2047
2048#define MTXONBOD 0x1 /* MTXONB Open Drain Select */
2049#define MTXONBG 0x2 /* MTXONB Gates MTX Select */
2050#define MFSOE 0x10 /* MFS Output Enable */
2051#define MFSGPSEL 0x20 /* MFS General Purpose Output Select */
2052#define MFSGPDAT 0x40 /* MFS General Purpose Output Data */
2053
2054/* Bit masks for MXVR_SCLK_CNT */
2055
2056#define SCNT 0xffff /* System Clock Count */
2057
2058/* Bit masks for KPAD_CTL */
2059
2060#define KPAD_EN 0x1 /* Keypad Enable */
2061#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */
2062#define KPAD_ROWEN 0x1c00 /* Row Enable Width */
2063#define KPAD_COLEN 0xe000 /* Column Enable Width */
2064
2065/* Bit masks for KPAD_PRESCALE */
2066
2067#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */
2068
2069/* Bit masks for KPAD_MSEL */
2070
2071#define DBON_SCALE 0xff /* Debounce Scale Value */
2072#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */
2073
2074/* Bit masks for KPAD_ROWCOL */
2075
2076#define KPAD_ROW 0xff /* Rows Pressed */
2077#define KPAD_COL 0xff00 /* Columns Pressed */
2078
2079/* Bit masks for KPAD_STAT */
2080
2081#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */
2082#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */
2083#define KPAD_PRESSED 0x8 /* Key press current status */
2084
2085/* Bit masks for KPAD_SOFTEVAL */
2086
2087#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
2088
2089/* Bit masks for SDH_COMMAND */
2090
2091#define CMD_IDX 0x3f /* Command Index */
2092#define CMD_RSP 0x40 /* Response */
2093#define CMD_L_RSP 0x80 /* Long Response */
2094#define CMD_INT_E 0x100 /* Command Interrupt */
2095#define CMD_PEND_E 0x200 /* Command Pending */
2096#define CMD_E 0x400 /* Command Enable */
2097
2098/* Bit masks for SDH_PWR_CTL */
2099
2100#define PWR_ON 0x3 /* Power On */
2101#if 0
2102#define TBD 0x3c /* TBD */
2103#endif
2104#define SD_CMD_OD 0x40 /* Open Drain Output */
2105#define ROD_CTL 0x80 /* Rod Control */
2106
2107/* Bit masks for SDH_CLK_CTL */
2108
2109#define CLKDIV 0xff /* MC_CLK Divisor */
2110#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
2111#define PWR_SV_E 0x200 /* Power Save Enable */
2112#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
2113#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
2114
2115/* Bit masks for SDH_RESP_CMD */
2116
2117#define RESP_CMD 0x3f /* Response Command */
2118
2119/* Bit masks for SDH_DATA_CTL */
2120
2121#define DTX_E 0x1 /* Data Transfer Enable */
2122#define DTX_DIR 0x2 /* Data Transfer Direction */
2123#define DTX_MODE 0x4 /* Data Transfer Mode */
2124#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
2125#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
2126
2127/* Bit masks for SDH_STATUS */
2128
2129#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
2130#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
2131#define CMD_TIME_OUT 0x4 /* CMD Time Out */
2132#define DAT_TIME_OUT 0x8 /* Data Time Out */
2133#define TX_UNDERRUN 0x10 /* Transmit Underrun */
2134#define RX_OVERRUN 0x20 /* Receive Overrun */
2135#define CMD_RESP_END 0x40 /* CMD Response End */
2136#define CMD_SENT 0x80 /* CMD Sent */
2137#define DAT_END 0x100 /* Data End */
2138#define START_BIT_ERR 0x200 /* Start Bit Error */
2139#define DAT_BLK_END 0x400 /* Data Block End */
2140#define CMD_ACT 0x800 /* CMD Active */
2141#define TX_ACT 0x1000 /* Transmit Active */
2142#define RX_ACT 0x2000 /* Receive Active */
2143#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
2144#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
2145#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
2146#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
2147#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
2148#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
2149#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
2150#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
2151
2152/* Bit masks for SDH_STATUS_CLR */
2153
2154#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
2155#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
2156#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
2157#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
2158#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
2159#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
2160#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
2161#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
2162#define DAT_END_STAT 0x100 /* Data End Status */
2163#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
2164#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
2165
2166/* Bit masks for SDH_MASK0 */
2167
2168#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
2169#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
2170#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
2171#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
2172#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
2173#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
2174#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
2175#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
2176#define DAT_END_MASK 0x100 /* Data End Mask */
2177#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
2178#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
2179#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
2180#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
2181#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
2182#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
2183#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
2184#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
2185#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
2186#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
2187#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
2188#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
2189#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
2190
2191/* Bit masks for SDH_FIFO_CNT */
2192
2193#define FIFO_COUNT 0x7fff /* FIFO Count */
2194
2195/* Bit masks for SDH_E_STATUS */
2196
2197#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
2198#define SD_CARD_DET 0x10 /* SD Card Detect */
2199
2200/* Bit masks for SDH_E_MASK */
2201
2202#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
2203#define SCD_MSK 0x40 /* Mask Card Detect */
2204
2205/* Bit masks for SDH_CFG */
2206
2207#define CLKS_EN 0x1 /* Clocks Enable */
2208#define SD4E 0x4 /* SDIO 4-Bit Enable */
2209#define MWE 0x8 /* Moving Window Enable */
2210#define SD_RST 0x10 /* SDMMC Reset */
2211#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
2212#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
2213#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
2214
2215/* Bit masks for SDH_RD_WAIT_EN */
2216
2217#define RWR 0x1 /* Read Wait Request */
2218
2219/* Bit masks for ATAPI_CONTROL */
2220
2221#define PIO_START 0x1 /* Start PIO/Reg Op */
2222#define MULTI_START 0x2 /* Start Multi-DMA Op */
2223#define ULTRA_START 0x4 /* Start Ultra-DMA Op */
2224#define XFER_DIR 0x8 /* Transfer Direction */
2225#define IORDY_EN 0x10 /* IORDY Enable */
2226#define FIFO_FLUSH 0x20 /* Flush FIFOs */
2227#define SOFT_RST 0x40 /* Soft Reset */
2228#define DEV_RST 0x80 /* Device Reset */
2229#define TFRCNT_RST 0x100 /* Trans Count Reset */
2230#define END_ON_TERM 0x200 /* End/Terminate Select */
2231#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
2232#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
2233
2234/* Bit masks for ATAPI_STATUS */
2235
2236#define PIO_XFER_ON 0x1 /* PIO transfer in progress */
2237#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
2238#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
2239#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */
2240
2241/* Bit masks for ATAPI_DEV_ADDR */
2242
2243#define DEV_ADDR 0x1f /* Device Address */
2244
2245/* Bit masks for ATAPI_INT_MASK */
2246
2247#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */
2248#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
2249#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
2250#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
2251#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
2252#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
2253#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
2254#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
2255#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
2256
2257/* Bit masks for ATAPI_INT_STATUS */
2258
2259#define ATAPI_DEV_INT 0x1 /* Device interrupt status */
2260#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
2261#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
2262#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
2263#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
2264#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
2265#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
2266#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
2267#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
2268
2269/* Bit masks for ATAPI_LINE_STATUS */
2270
2271#define ATAPI_INTR 0x1 /* Device interrupt to host line status */
2272#define ATAPI_DASP 0x2 /* Device dasp to host line status */
2273#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
2274#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
2275#define ATAPI_ADDR 0x70 /* ATAPI address line status */
2276#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
2277#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
2278#define ATAPI_DIOWN 0x200 /* ATAPI write line status */
2279#define ATAPI_DIORN 0x400 /* ATAPI read line status */
2280#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
2281
2282/* Bit masks for ATAPI_SM_STATE */
2283
2284#define PIO_CSTATE 0xf /* PIO mode state machine current state */
2285#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */
2286#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */
2287#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */
2288
2289/* Bit masks for ATAPI_TERMINATE */
2290
2291#define ATAPI_HOST_TERM 0x1 /* Host terminationation */
2292
2293/* Bit masks for ATAPI_REG_TIM_0 */
2294
2295#define T2_REG 0xff /* End of cycle time for register access transfers */
2296#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */
2297
2298/* Bit masks for ATAPI_PIO_TIM_0 */
2299
2300#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */
2301#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */
2302#define T4_REG 0xf000 /* DIOW data hold */
2303
2304/* Bit masks for ATAPI_PIO_TIM_1 */
2305
2306#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */
2307
2308/* Bit masks for ATAPI_MULTI_TIM_0 */
2309
2310#define TD 0xff /* DIOR/DIOW asserted pulsewidth */
2311#define TM 0xff00 /* Time from address valid to DIOR/DIOW */
2312
2313/* Bit masks for ATAPI_MULTI_TIM_1 */
2314
2315#define TKW 0xff /* Selects DIOW negated pulsewidth */
2316#define TKR 0xff00 /* Selects DIOR negated pulsewidth */
2317
2318/* Bit masks for ATAPI_MULTI_TIM_2 */
2319
2320#define TH 0xff /* Selects DIOW data hold */
2321#define TEOC 0xff00 /* Selects end of cycle for DMA */
2322
2323/* Bit masks for ATAPI_ULTRA_TIM_0 */
2324
2325#define TACK 0xff /* Selects setup and hold times for TACK */
2326#define TENV 0xff00 /* Selects envelope time */
2327
2328/* Bit masks for ATAPI_ULTRA_TIM_1 */
2329
2330#define TDVS 0xff /* Selects data valid setup time */
2331#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */
2332
2333/* Bit masks for ATAPI_ULTRA_TIM_2 */
2334
2335#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
2336#define TMLI 0xff00 /* Selects interlock time */
2337
2338/* Bit masks for ATAPI_ULTRA_TIM_3 */
2339
2340#define TZAH 0xff /* Selects minimum delay required for output */
2341#define READY_PAUSE 0xff00 /* Selects ready to pause */
2342
2343/* Bit masks for TIMER_ENABLE1 */
2344
2345#define TIMEN8 0x1 /* Timer 8 Enable */
2346#define TIMEN9 0x2 /* Timer 9 Enable */
2347#define TIMEN10 0x4 /* Timer 10 Enable */
2348
2349/* Bit masks for TIMER_DISABLE1 */
2350
2351#define TIMDIS8 0x1 /* Timer 8 Disable */
2352#define TIMDIS9 0x2 /* Timer 9 Disable */
2353#define TIMDIS10 0x4 /* Timer 10 Disable */
2354
2355/* Bit masks for TIMER_STATUS1 */
2356
2357#define TIMIL8 0x1 /* Timer 8 Interrupt */
2358#define TIMIL9 0x2 /* Timer 9 Interrupt */
2359#define TIMIL10 0x4 /* Timer 10 Interrupt */
2360#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */
2361#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */
2362#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */
2363#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */
2364#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */
2365#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */
2366
2367/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
2368
2369/* Bit masks for USB_FADDR */
2370
2371#define FUNCTION_ADDRESS 0x7f /* Function address */
2372
2373/* Bit masks for USB_POWER */
2374
2375#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
2376#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
2377#define RESUME_MODE 0x4 /* DMA Mode */
2378#define RESET 0x8 /* Reset indicator */
2379#define HS_MODE 0x10 /* High Speed mode indicator */
2380#define HS_ENABLE 0x20 /* high Speed Enable */
2381#define SOFT_CONN 0x40 /* Soft connect */
2382#define ISO_UPDATE 0x80 /* Isochronous update */
2383
2384/* Bit masks for USB_INTRTX */
2385
2386#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
2387#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
2388#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
2389#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
2390#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
2391#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
2392#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
2393#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
2394
2395/* Bit masks for USB_INTRRX */
2396
2397#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
2398#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
2399#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
2400#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
2401#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
2402#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
2403#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
2404
2405/* Bit masks for USB_INTRTXE */
2406
2407#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
2408#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
2409#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
2410#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
2411#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
2412#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
2413#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
2414#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
2415
2416/* Bit masks for USB_INTRRXE */
2417
2418#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
2419#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
2420#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
2421#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
2422#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
2423#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
2424#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
2425
2426/* Bit masks for USB_INTRUSB */
2427
2428#define SUSPEND_B 0x1 /* Suspend indicator */
2429#define RESUME_B 0x2 /* Resume indicator */
2430#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
2431#define SOF_B 0x8 /* Start of frame */
2432#define CONN_B 0x10 /* Connection indicator */
2433#define DISCON_B 0x20 /* Disconnect indicator */
2434#define SESSION_REQ_B 0x40 /* Session Request */
2435#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
2436
2437/* Bit masks for USB_INTRUSBE */
2438
2439#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
2440#define RESUME_BE 0x2 /* Resume indicator int enable */
2441#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
2442#define SOF_BE 0x8 /* Start of frame int enable */
2443#define CONN_BE 0x10 /* Connection indicator int enable */
2444#define DISCON_BE 0x20 /* Disconnect indicator int enable */
2445#define SESSION_REQ_BE 0x40 /* Session Request int enable */
2446#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
2447
2448/* Bit masks for USB_FRAME */
2449
2450#define FRAME_NUMBER 0x7ff /* Frame number */
2451
2452/* Bit masks for USB_INDEX */
2453
2454#define SELECTED_ENDPOINT 0xf /* selected endpoint */
2455
2456/* Bit masks for USB_GLOBAL_CTL */
2457
2458#define GLOBAL_ENA 0x1 /* enables USB module */
2459#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
2460#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
2461#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
2462#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
2463#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
2464#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
2465#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
2466#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
2467#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
2468#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
2469#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
2470#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
2471#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
2472#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
2473
2474/* Bit masks for USB_OTG_DEV_CTL */
2475
2476#define SESSION 0x1 /* session indicator */
2477#define HOST_REQ 0x2 /* Host negotiation request */
2478#define HOST_MODE 0x4 /* indicates USBDRC is a host */
2479#define VBUS0 0x8 /* Vbus level indicator[0] */
2480#define VBUS1 0x10 /* Vbus level indicator[1] */
2481#define LSDEV 0x20 /* Low-speed indicator */
2482#define FSDEV 0x40 /* Full or High-speed indicator */
2483#define B_DEVICE 0x80 /* A' or 'B' device indicator */
2484
2485/* Bit masks for USB_OTG_VBUS_IRQ */
2486
2487#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
2488#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
2489#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
2490#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
2491#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
2492#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
2493
2494/* Bit masks for USB_OTG_VBUS_MASK */
2495
2496#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
2497#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
2498#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
2499#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
2500#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
2501#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
2502
2503/* Bit masks for USB_CSR0 */
2504
2505#define RXPKTRDY 0x1 /* data packet receive indicator */
2506#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
2507#define STALL_SENT 0x4 /* STALL handshake sent */
2508#define DATAEND 0x8 /* Data end indicator */
2509#define SETUPEND 0x10 /* Setup end */
2510#define SENDSTALL 0x20 /* Send STALL handshake */
2511#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
2512#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
2513#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
2514#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
2515#define SETUPPKT_H 0x8 /* send Setup token host mode */
2516#define ERROR_H 0x10 /* timeout error indicator host mode */
2517#define REQPKT_H 0x20 /* Request an IN transaction host mode */
2518#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
2519#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
2520
2521/* Bit masks for USB_COUNT0 */
2522
2523#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
2524
2525/* Bit masks for USB_NAKLIMIT0 */
2526
2527#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
2528
2529/* Bit masks for USB_TX_MAX_PACKET */
2530
2531#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
2532
2533/* Bit masks for USB_RX_MAX_PACKET */
2534
2535#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
2536
2537/* Bit masks for USB_TXCSR */
2538
2539#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
2540#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
2541#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
2542#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
2543#define STALL_SEND_T 0x10 /* issue a Stall handshake */
2544#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
2545#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
2546#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
2547#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
2548#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
2549#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
2550#define ISO_T 0x4000 /* enable Isochronous transfers */
2551#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
2552#define ERROR_TH 0x4 /* error condition host mode */
2553#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
2554#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
2555
2556/* Bit masks for USB_TXCOUNT */
2557
2558#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
2559
2560/* Bit masks for USB_RXCSR */
2561
2562#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
2563#define FIFO_FULL_R 0x2 /* FIFO not empty */
2564#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
2565#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
2566#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
2567#define STALL_SEND_R 0x20 /* issue a Stall handshake */
2568#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
2569#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
2570#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
2571#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
2572#define DISNYET_R 0x1000 /* disable Nyet handshakes */
2573#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
2574#define ISO_R 0x4000 /* enable Isochronous transfers */
2575#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
2576#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
2577#define REQPKT_RH 0x20 /* request an IN transaction host mode */
2578#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
2579#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
2580#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
2581#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
2582
2583/* Bit masks for USB_RXCOUNT */
2584
2585#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
2586
2587/* Bit masks for USB_TXTYPE */
2588
2589#define TARGET_EP_NO_T 0xf /* EP number */
2590#define PROTOCOL_T 0xc /* transfer type */
2591
2592/* Bit masks for USB_TXINTERVAL */
2593
2594#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
2595
2596/* Bit masks for USB_RXTYPE */
2597
2598#define TARGET_EP_NO_R 0xf /* EP number */
2599#define PROTOCOL_R 0xc /* transfer type */
2600
2601/* Bit masks for USB_RXINTERVAL */
2602
2603#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
2604
2605/* Bit masks for USB_DMA_INTERRUPT */
2606
2607#define DMA0_INT 0x1 /* DMA0 pending interrupt */
2608#define DMA1_INT 0x2 /* DMA1 pending interrupt */
2609#define DMA2_INT 0x4 /* DMA2 pending interrupt */
2610#define DMA3_INT 0x8 /* DMA3 pending interrupt */
2611#define DMA4_INT 0x10 /* DMA4 pending interrupt */
2612#define DMA5_INT 0x20 /* DMA5 pending interrupt */
2613#define DMA6_INT 0x40 /* DMA6 pending interrupt */
2614#define DMA7_INT 0x80 /* DMA7 pending interrupt */
2615
2616/* Bit masks for USB_DMAxCONTROL */
2617
2618#define DMA_ENA 0x1 /* DMA enable */
2619#define DIRECTION 0x2 /* direction of DMA transfer */
2620#define MODE 0x4 /* DMA Bus error */
2621#define INT_ENA 0x8 /* Interrupt enable */
2622#define EPNUM 0xf0 /* EP number */
2623#define BUSERROR 0x100 /* DMA Bus error */
2624
2625/* Bit masks for USB_DMAxADDRHIGH */
2626
2627#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
2628
2629/* Bit masks for USB_DMAxADDRLOW */
2630
2631#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
2632
2633/* Bit masks for USB_DMAxCOUNTHIGH */
2634
2635#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
2636
2637/* Bit masks for USB_DMAxCOUNTLOW */
2638
2639#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
2640
2641/* Bit masks for HMDMAx_CONTROL */
2642
2643#define HMDMAEN 0x1 /* Handshake MDMA Enable */
2644#define REP 0x2 /* Handshake MDMA Request Polarity */
2645#define UTE 0x8 /* Urgency Threshold Enable */
2646#define OIE 0x10 /* Overflow Interrupt Enable */
2647#define BDIE 0x20 /* Block Done Interrupt Enable */
2648#define MBDI 0x40 /* Mask Block Done Interrupt */
2649#define DRQ 0x300 /* Handshake MDMA Request Type */
2650#define RBC 0x1000 /* Force Reload of BCOUNT */
2651#define PS 0x2000 /* Pin Status */
2652#define OI 0x4000 /* Overflow Interrupt Generated */
2653#define BDI 0x8000 /* Block Done Interrupt Generated */
2654
2655/* ******************************************* */
2656/* MULTI BIT MACRO ENUMERATIONS */
2657/* ******************************************* */
2658
2659/* ************************ */
2660/* MXVR Address Offsets */
2661/* ************************ */
2662
2663/* Control Message Receive Buffer (CMRB) Address Offsets */
2664
2665#define CMRB_STRIDE 0x00000016lu
2666
2667#define CMRB_DST_OFFSET 0x00000000lu
2668#define CMRB_SRC_OFFSET 0x00000002lu
2669#define CMRB_DATA_OFFSET 0x00000005lu
2670
2671/* Control Message Transmit Buffer (CMTB) Address Offsets */
2672
2673#define CMTB_PRIO_OFFSET 0x00000000lu
2674#define CMTB_DST_OFFSET 0x00000002lu
2675#define CMTB_SRC_OFFSET 0x00000004lu
2676#define CMTB_TYPE_OFFSET 0x00000006lu
2677#define CMTB_DATA_OFFSET 0x00000007lu
2678
2679#define CMTB_ANSWER_OFFSET 0x0000000Alu
2680
2681#define CMTB_STAT_N_OFFSET 0x00000018lu
2682#define CMTB_STAT_A_OFFSET 0x00000016lu
2683#define CMTB_STAT_D_OFFSET 0x0000000Elu
2684#define CMTB_STAT_R_OFFSET 0x00000014lu
2685#define CMTB_STAT_W_OFFSET 0x00000014lu
2686#define CMTB_STAT_G_OFFSET 0x00000014lu
2687
2688/* Asynchronous Packet Receive Buffer (APRB) Address Offsets */
2689
2690#define APRB_STRIDE 0x00000400lu
2691
2692#define APRB_DST_OFFSET 0x00000000lu
2693#define APRB_LEN_OFFSET 0x00000002lu
2694#define APRB_SRC_OFFSET 0x00000004lu
2695#define APRB_DATA_OFFSET 0x00000006lu
2696
2697/* Asynchronous Packet Transmit Buffer (APTB) Address Offsets */
2698
2699#define APTB_PRIO_OFFSET 0x00000000lu
2700#define APTB_DST_OFFSET 0x00000002lu
2701#define APTB_LEN_OFFSET 0x00000004lu
2702#define APTB_SRC_OFFSET 0x00000006lu
2703#define APTB_DATA_OFFSET 0x00000008lu
2704
2705/* Remote Read Buffer (RRDB) Address Offsets */
2706
2707#define RRDB_WADDR_OFFSET 0x00000100lu
2708#define RRDB_WLEN_OFFSET 0x00000101lu
2709
2710/* **************** */
2711/* MXVR Macros */
2712/* **************** */
2713
2714/* MXVR_CONFIG Macros */
2715
2716#define SET_MSB(x) ( ( (x) & 0xF ) << 9)
2717
2718/* MXVR_INT_STAT_1 Macros */
2719
2720#define DONEX(x) (0x00000002 << (4 * (x)))
2721#define HDONEX(x) (0x00000001 << (4 * (x)))
2722
2723/* MXVR_INT_EN_1 Macros */
2724
2725#define DONEENX(x) (0x00000002 << (4 * (x)))
2726#define HDONEENX(x) (0x00000001 << (4 * (x)))
2727
2728/* MXVR_CDRPLL_CTL Macros */
2729
2730#define SET_CDRSHPSEL(x) ( ( (x) & 0x3F ) << 16)
2731
2732/* MXVR_FMPLL_CTL Macros */
2733
2734#define SET_CDRCPSEL(x) ( ( (x) & 0xFF ) << 24)
2735#define SET_FMCPSEL(x) ( ( (x) & 0xFF ) << 24)
2736
2737#endif /* _DEF_BF549_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
new file mode 100644
index 000000000000..e022e896cb18
--- /dev/null
+++ b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
@@ -0,0 +1,3956 @@
1/*
2 * File: include/asm-blackfin/mach-bf548/defBF54x_base.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _DEF_BF54X_H
32#define _DEF_BF54X_H
33
34
35/* ************************************************************** */
36/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */
37/* ************************************************************** */
38
39/* PLL Registers */
40
41#define PLL_CTL 0xffc00000 /* PLL Control Register */
42#define PLL_DIV 0xffc00004 /* PLL Divisor Register */
43#define VR_CTL 0xffc00008 /* Voltage Regulator Control Register */
44#define PLL_STAT 0xffc0000c /* PLL Status Register */
45#define PLL_LOCKCNT 0xffc00010 /* PLL Lock Count Register */
46
47/* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */
48
49#define CHIPID 0xffc00014
50/* CHIPID Masks */
51#define CHIPID_VERSION 0xF0000000
52#define CHIPID_FAMILY 0x0FFFF000
53#define CHIPID_MANUFACTURE 0x00000FFE
54
55/* System Reset and Interrupt Controller (0xFFC00100 - 0xFFC00104) */
56
57#define SWRST 0xffc00100 /* Software Reset Register */
58#define SYSCR 0xffc00104 /* System Configuration register */
59
60/* SIC Registers */
61
62#define SIC_IMASK0 0xffc0010c /* System Interrupt Mask Register 0 */
63#define SIC_IMASK1 0xffc00110 /* System Interrupt Mask Register 1 */
64#define SIC_IMASK2 0xffc00114 /* System Interrupt Mask Register 2 */
65#define SIC_ISR0 0xffc00118 /* System Interrupt Status Register 0 */
66#define SIC_ISR1 0xffc0011c /* System Interrupt Status Register 1 */
67#define SIC_ISR2 0xffc00120 /* System Interrupt Status Register 2 */
68#define SIC_IWR0 0xffc00124 /* System Interrupt Wakeup Register 0 */
69#define SIC_IWR1 0xffc00128 /* System Interrupt Wakeup Register 1 */
70#define SIC_IWR2 0xffc0012c /* System Interrupt Wakeup Register 2 */
71#define SIC_IAR0 0xffc00130 /* System Interrupt Assignment Register 0 */
72#define SIC_IAR1 0xffc00134 /* System Interrupt Assignment Register 1 */
73#define SIC_IAR2 0xffc00138 /* System Interrupt Assignment Register 2 */
74#define SIC_IAR3 0xffc0013c /* System Interrupt Assignment Register 3 */
75#define SIC_IAR4 0xffc00140 /* System Interrupt Assignment Register 4 */
76#define SIC_IAR5 0xffc00144 /* System Interrupt Assignment Register 5 */
77#define SIC_IAR6 0xffc00148 /* System Interrupt Assignment Register 6 */
78#define SIC_IAR7 0xffc0014c /* System Interrupt Assignment Register 7 */
79#define SIC_IAR8 0xffc00150 /* System Interrupt Assignment Register 8 */
80#define SIC_IAR9 0xffc00154 /* System Interrupt Assignment Register 9 */
81#define SIC_IAR10 0xffc00158 /* System Interrupt Assignment Register 10 */
82#define SIC_IAR11 0xffc0015c /* System Interrupt Assignment Register 11 */
83
84/* Watchdog Timer Registers */
85
86#define WDOG_CTL 0xffc00200 /* Watchdog Control Register */
87#define WDOG_CNT 0xffc00204 /* Watchdog Count Register */
88#define WDOG_STAT 0xffc00208 /* Watchdog Status Register */
89
90/* RTC Registers */
91
92#define RTC_STAT 0xffc00300 /* RTC Status Register */
93#define RTC_ICTL 0xffc00304 /* RTC Interrupt Control Register */
94#define RTC_ISTAT 0xffc00308 /* RTC Interrupt Status Register */
95#define RTC_SWCNT 0xffc0030c /* RTC Stopwatch Count Register */
96#define RTC_ALARM 0xffc00310 /* RTC Alarm Register */
97#define RTC_PREN 0xffc00314 /* RTC Prescaler Enable Register */
98
99/* UART0 Registers */
100
101#define UART0_DLL 0xffc00400 /* Divisor Latch Low Byte */
102#define UART0_DLH 0xffc00404 /* Divisor Latch High Byte */
103#define UART0_GCTL 0xffc00408 /* Global Control Register */
104#define UART0_LCR 0xffc0040c /* Line Control Register */
105#define UART0_MCR 0xffc00410 /* Modem Control Register */
106#define UART0_LSR 0xffc00414 /* Line Status Register */
107#define UART0_MSR 0xffc00418 /* Modem Status Register */
108#define UART0_SCR 0xffc0041c /* Scratch Register */
109#define UART0_IER_SET 0xffc00420 /* Interrupt Enable Register Set */
110#define UART0_IER_CLEAR 0xffc00424 /* Interrupt Enable Register Clear */
111#define UART0_THR 0xffc00428 /* Transmit Hold Register */
112#define UART0_RBR 0xffc0042c /* Receive Buffer Register */
113
114/* SPI0 Registers */
115
116#define SPI0_REGBASE 0xffc00500
117#define SPI0_CTL 0xffc00500 /* SPI0 Control Register */
118#define SPI0_FLG 0xffc00504 /* SPI0 Flag Register */
119#define SPI0_STAT 0xffc00508 /* SPI0 Status Register */
120#define SPI0_TDBR 0xffc0050c /* SPI0 Transmit Data Buffer Register */
121#define SPI0_RDBR 0xffc00510 /* SPI0 Receive Data Buffer Register */
122#define SPI0_BAUD 0xffc00514 /* SPI0 Baud Rate Register */
123#define SPI0_SHADOW 0xffc00518 /* SPI0 Receive Data Buffer Shadow Register */
124
125/* Timer Group of 3 registers are not defined in the shared file because they are not available on the ADSP-BF542 processor */
126
127/* Two Wire Interface Registers (TWI0) */
128
129#define TWI0_REGBASE 0xffc00700
130#define TWI0_CLKDIV 0xffc00700 /* Clock Divider Register */
131#define TWI0_CONTROL 0xffc00704 /* TWI Control Register */
132#define TWI0_SLAVE_CTRL 0xffc00708 /* TWI Slave Mode Control Register */
133#define TWI0_SLAVE_STAT 0xffc0070c /* TWI Slave Mode Status Register */
134#define TWI0_SLAVE_ADDR 0xffc00710 /* TWI Slave Mode Address Register */
135#define TWI0_MASTER_CTRL 0xffc00714 /* TWI Master Mode Control Register */
136#define TWI0_MASTER_STAT 0xffc00718 /* TWI Master Mode Status Register */
137#define TWI0_MASTER_ADDR 0xffc0071c /* TWI Master Mode Address Register */
138#define TWI0_INT_STAT 0xffc00720 /* TWI Interrupt Status Register */
139#define TWI0_INT_MASK 0xffc00724 /* TWI Interrupt Mask Register */
140#define TWI0_FIFO_CTRL 0xffc00728 /* TWI FIFO Control Register */
141#define TWI0_FIFO_STAT 0xffc0072c /* TWI FIFO Status Register */
142#define TWI0_XMT_DATA8 0xffc00780 /* TWI FIFO Transmit Data Single Byte Register */
143#define TWI0_XMT_DATA16 0xffc00784 /* TWI FIFO Transmit Data Double Byte Register */
144#define TWI0_RCV_DATA8 0xffc00788 /* TWI FIFO Receive Data Single Byte Register */
145#define TWI0_RCV_DATA16 0xffc0078c /* TWI FIFO Receive Data Double Byte Register */
146
147/* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 processors */
148
149/* SPORT1 Registers */
150
151#define SPORT1_TCR1 0xffc00900 /* SPORT1 Transmit Configuration 1 Register */
152#define SPORT1_TCR2 0xffc00904 /* SPORT1 Transmit Configuration 2 Register */
153#define SPORT1_TCLKDIV 0xffc00908 /* SPORT1 Transmit Serial Clock Divider Register */
154#define SPORT1_TFSDIV 0xffc0090c /* SPORT1 Transmit Frame Sync Divider Register */
155#define SPORT1_TX 0xffc00910 /* SPORT1 Transmit Data Register */
156#define SPORT1_RX 0xffc00918 /* SPORT1 Receive Data Register */
157#define SPORT1_RCR1 0xffc00920 /* SPORT1 Receive Configuration 1 Register */
158#define SPORT1_RCR2 0xffc00924 /* SPORT1 Receive Configuration 2 Register */
159#define SPORT1_RCLKDIV 0xffc00928 /* SPORT1 Receive Serial Clock Divider Register */
160#define SPORT1_RFSDIV 0xffc0092c /* SPORT1 Receive Frame Sync Divider Register */
161#define SPORT1_STAT 0xffc00930 /* SPORT1 Status Register */
162#define SPORT1_CHNL 0xffc00934 /* SPORT1 Current Channel Register */
163#define SPORT1_MCMC1 0xffc00938 /* SPORT1 Multi channel Configuration Register 1 */
164#define SPORT1_MCMC2 0xffc0093c /* SPORT1 Multi channel Configuration Register 2 */
165#define SPORT1_MTCS0 0xffc00940 /* SPORT1 Multi channel Transmit Select Register 0 */
166#define SPORT1_MTCS1 0xffc00944 /* SPORT1 Multi channel Transmit Select Register 1 */
167#define SPORT1_MTCS2 0xffc00948 /* SPORT1 Multi channel Transmit Select Register 2 */
168#define SPORT1_MTCS3 0xffc0094c /* SPORT1 Multi channel Transmit Select Register 3 */
169#define SPORT1_MRCS0 0xffc00950 /* SPORT1 Multi channel Receive Select Register 0 */
170#define SPORT1_MRCS1 0xffc00954 /* SPORT1 Multi channel Receive Select Register 1 */
171#define SPORT1_MRCS2 0xffc00958 /* SPORT1 Multi channel Receive Select Register 2 */
172#define SPORT1_MRCS3 0xffc0095c /* SPORT1 Multi channel Receive Select Register 3 */
173
174/* Asynchronous Memory Control Registers */
175
176#define EBIU_AMGCTL 0xffc00a00 /* Asynchronous Memory Global Control Register */
177#define EBIU_AMBCTL0 0xffc00a04 /* Asynchronous Memory Bank Control Register */
178#define EBIU_AMBCTL1 0xffc00a08 /* Asynchronous Memory Bank Control Register */
179#define EBIU_MBSCTL 0xffc00a0c /* Asynchronous Memory Bank Select Control Register */
180#define EBIU_ARBSTAT 0xffc00a10 /* Asynchronous Memory Arbiter Status Register */
181#define EBIU_MODE 0xffc00a14 /* Asynchronous Mode Control Register */
182#define EBIU_FCTL 0xffc00a18 /* Asynchronous Memory Flash Control Register */
183
184/* DDR Memory Control Registers */
185
186#define EBIU_DDRCTL0 0xffc00a20 /* DDR Memory Control 0 Register */
187#define EBIU_DDRCTL1 0xffc00a24 /* DDR Memory Control 1 Register */
188#define EBIU_DDRCTL2 0xffc00a28 /* DDR Memory Control 2 Register */
189#define EBIU_DDRCTL3 0xffc00a2c /* DDR Memory Control 3 Register */
190#define EBIU_DDRQUE 0xffc00a30 /* DDR Queue Configuration Register */
191#define EBIU_ERRADD 0xffc00a34 /* DDR Error Address Register */
192#define EBIU_ERRMST 0xffc00a38 /* DDR Error Master Register */
193#define EBIU_RSTCTL 0xffc00a3c /* DDR Reset Control Register */
194
195/* DDR BankRead and Write Count Registers */
196
197#define EBIU_DDRBRC0 0xffc00a60 /* DDR Bank0 Read Count Register */
198#define EBIU_DDRBRC1 0xffc00a64 /* DDR Bank1 Read Count Register */
199#define EBIU_DDRBRC2 0xffc00a68 /* DDR Bank2 Read Count Register */
200#define EBIU_DDRBRC3 0xffc00a6c /* DDR Bank3 Read Count Register */
201#define EBIU_DDRBRC4 0xffc00a70 /* DDR Bank4 Read Count Register */
202#define EBIU_DDRBRC5 0xffc00a74 /* DDR Bank5 Read Count Register */
203#define EBIU_DDRBRC6 0xffc00a78 /* DDR Bank6 Read Count Register */
204#define EBIU_DDRBRC7 0xffc00a7c /* DDR Bank7 Read Count Register */
205#define EBIU_DDRBWC0 0xffc00a80 /* DDR Bank0 Write Count Register */
206#define EBIU_DDRBWC1 0xffc00a84 /* DDR Bank1 Write Count Register */
207#define EBIU_DDRBWC2 0xffc00a88 /* DDR Bank2 Write Count Register */
208#define EBIU_DDRBWC3 0xffc00a8c /* DDR Bank3 Write Count Register */
209#define EBIU_DDRBWC4 0xffc00a90 /* DDR Bank4 Write Count Register */
210#define EBIU_DDRBWC5 0xffc00a94 /* DDR Bank5 Write Count Register */
211#define EBIU_DDRBWC6 0xffc00a98 /* DDR Bank6 Write Count Register */
212#define EBIU_DDRBWC7 0xffc00a9c /* DDR Bank7 Write Count Register */
213#define EBIU_DDRACCT 0xffc00aa0 /* DDR Activation Count Register */
214#define EBIU_DDRTACT 0xffc00aa8 /* DDR Turn Around Count Register */
215#define EBIU_DDRARCT 0xffc00aac /* DDR Auto-refresh Count Register */
216#define EBIU_DDRGC0 0xffc00ab0 /* DDR Grant Count 0 Register */
217#define EBIU_DDRGC1 0xffc00ab4 /* DDR Grant Count 1 Register */
218#define EBIU_DDRGC2 0xffc00ab8 /* DDR Grant Count 2 Register */
219#define EBIU_DDRGC3 0xffc00abc /* DDR Grant Count 3 Register */
220#define EBIU_DDRMCEN 0xffc00ac0 /* DDR Metrics Counter Enable Register */
221#define EBIU_DDRMCCL 0xffc00ac4 /* DDR Metrics Counter Clear Register */
222
223/* DMAC0 Registers */
224
225#define DMAC0_TCPER 0xffc00b0c /* DMA Controller 0 Traffic Control Periods Register */
226#define DMAC0_TCCNT 0xffc00b10 /* DMA Controller 0 Current Counts Register */
227
228/* DMA Channel 0 Registers */
229
230#define DMA0_NEXT_DESC_PTR 0xffc00c00 /* DMA Channel 0 Next Descriptor Pointer Register */
231#define DMA0_START_ADDR 0xffc00c04 /* DMA Channel 0 Start Address Register */
232#define DMA0_CONFIG 0xffc00c08 /* DMA Channel 0 Configuration Register */
233#define DMA0_X_COUNT 0xffc00c10 /* DMA Channel 0 X Count Register */
234#define DMA0_X_MODIFY 0xffc00c14 /* DMA Channel 0 X Modify Register */
235#define DMA0_Y_COUNT 0xffc00c18 /* DMA Channel 0 Y Count Register */
236#define DMA0_Y_MODIFY 0xffc00c1c /* DMA Channel 0 Y Modify Register */
237#define DMA0_CURR_DESC_PTR 0xffc00c20 /* DMA Channel 0 Current Descriptor Pointer Register */
238#define DMA0_CURR_ADDR 0xffc00c24 /* DMA Channel 0 Current Address Register */
239#define DMA0_IRQ_STATUS 0xffc00c28 /* DMA Channel 0 Interrupt/Status Register */
240#define DMA0_PERIPHERAL_MAP 0xffc00c2c /* DMA Channel 0 Peripheral Map Register */
241#define DMA0_CURR_X_COUNT 0xffc00c30 /* DMA Channel 0 Current X Count Register */
242#define DMA0_CURR_Y_COUNT 0xffc00c38 /* DMA Channel 0 Current Y Count Register */
243
244/* DMA Channel 1 Registers */
245
246#define DMA1_NEXT_DESC_PTR 0xffc00c40 /* DMA Channel 1 Next Descriptor Pointer Register */
247#define DMA1_START_ADDR 0xffc00c44 /* DMA Channel 1 Start Address Register */
248#define DMA1_CONFIG 0xffc00c48 /* DMA Channel 1 Configuration Register */
249#define DMA1_X_COUNT 0xffc00c50 /* DMA Channel 1 X Count Register */
250#define DMA1_X_MODIFY 0xffc00c54 /* DMA Channel 1 X Modify Register */
251#define DMA1_Y_COUNT 0xffc00c58 /* DMA Channel 1 Y Count Register */
252#define DMA1_Y_MODIFY 0xffc00c5c /* DMA Channel 1 Y Modify Register */
253#define DMA1_CURR_DESC_PTR 0xffc00c60 /* DMA Channel 1 Current Descriptor Pointer Register */
254#define DMA1_CURR_ADDR 0xffc00c64 /* DMA Channel 1 Current Address Register */
255#define DMA1_IRQ_STATUS 0xffc00c68 /* DMA Channel 1 Interrupt/Status Register */
256#define DMA1_PERIPHERAL_MAP 0xffc00c6c /* DMA Channel 1 Peripheral Map Register */
257#define DMA1_CURR_X_COUNT 0xffc00c70 /* DMA Channel 1 Current X Count Register */
258#define DMA1_CURR_Y_COUNT 0xffc00c78 /* DMA Channel 1 Current Y Count Register */
259
260/* DMA Channel 2 Registers */
261
262#define DMA2_NEXT_DESC_PTR 0xffc00c80 /* DMA Channel 2 Next Descriptor Pointer Register */
263#define DMA2_START_ADDR 0xffc00c84 /* DMA Channel 2 Start Address Register */
264#define DMA2_CONFIG 0xffc00c88 /* DMA Channel 2 Configuration Register */
265#define DMA2_X_COUNT 0xffc00c90 /* DMA Channel 2 X Count Register */
266#define DMA2_X_MODIFY 0xffc00c94 /* DMA Channel 2 X Modify Register */
267#define DMA2_Y_COUNT 0xffc00c98 /* DMA Channel 2 Y Count Register */
268#define DMA2_Y_MODIFY 0xffc00c9c /* DMA Channel 2 Y Modify Register */
269#define DMA2_CURR_DESC_PTR 0xffc00ca0 /* DMA Channel 2 Current Descriptor Pointer Register */
270#define DMA2_CURR_ADDR 0xffc00ca4 /* DMA Channel 2 Current Address Register */
271#define DMA2_IRQ_STATUS 0xffc00ca8 /* DMA Channel 2 Interrupt/Status Register */
272#define DMA2_PERIPHERAL_MAP 0xffc00cac /* DMA Channel 2 Peripheral Map Register */
273#define DMA2_CURR_X_COUNT 0xffc00cb0 /* DMA Channel 2 Current X Count Register */
274#define DMA2_CURR_Y_COUNT 0xffc00cb8 /* DMA Channel 2 Current Y Count Register */
275
276/* DMA Channel 3 Registers */
277
278#define DMA3_NEXT_DESC_PTR 0xffc00cc0 /* DMA Channel 3 Next Descriptor Pointer Register */
279#define DMA3_START_ADDR 0xffc00cc4 /* DMA Channel 3 Start Address Register */
280#define DMA3_CONFIG 0xffc00cc8 /* DMA Channel 3 Configuration Register */
281#define DMA3_X_COUNT 0xffc00cd0 /* DMA Channel 3 X Count Register */
282#define DMA3_X_MODIFY 0xffc00cd4 /* DMA Channel 3 X Modify Register */
283#define DMA3_Y_COUNT 0xffc00cd8 /* DMA Channel 3 Y Count Register */
284#define DMA3_Y_MODIFY 0xffc00cdc /* DMA Channel 3 Y Modify Register */
285#define DMA3_CURR_DESC_PTR 0xffc00ce0 /* DMA Channel 3 Current Descriptor Pointer Register */
286#define DMA3_CURR_ADDR 0xffc00ce4 /* DMA Channel 3 Current Address Register */
287#define DMA3_IRQ_STATUS 0xffc00ce8 /* DMA Channel 3 Interrupt/Status Register */
288#define DMA3_PERIPHERAL_MAP 0xffc00cec /* DMA Channel 3 Peripheral Map Register */
289#define DMA3_CURR_X_COUNT 0xffc00cf0 /* DMA Channel 3 Current X Count Register */
290#define DMA3_CURR_Y_COUNT 0xffc00cf8 /* DMA Channel 3 Current Y Count Register */
291
292/* DMA Channel 4 Registers */
293
294#define DMA4_NEXT_DESC_PTR 0xffc00d00 /* DMA Channel 4 Next Descriptor Pointer Register */
295#define DMA4_START_ADDR 0xffc00d04 /* DMA Channel 4 Start Address Register */
296#define DMA4_CONFIG 0xffc00d08 /* DMA Channel 4 Configuration Register */
297#define DMA4_X_COUNT 0xffc00d10 /* DMA Channel 4 X Count Register */
298#define DMA4_X_MODIFY 0xffc00d14 /* DMA Channel 4 X Modify Register */
299#define DMA4_Y_COUNT 0xffc00d18 /* DMA Channel 4 Y Count Register */
300#define DMA4_Y_MODIFY 0xffc00d1c /* DMA Channel 4 Y Modify Register */
301#define DMA4_CURR_DESC_PTR 0xffc00d20 /* DMA Channel 4 Current Descriptor Pointer Register */
302#define DMA4_CURR_ADDR 0xffc00d24 /* DMA Channel 4 Current Address Register */
303#define DMA4_IRQ_STATUS 0xffc00d28 /* DMA Channel 4 Interrupt/Status Register */
304#define DMA4_PERIPHERAL_MAP 0xffc00d2c /* DMA Channel 4 Peripheral Map Register */
305#define DMA4_CURR_X_COUNT 0xffc00d30 /* DMA Channel 4 Current X Count Register */
306#define DMA4_CURR_Y_COUNT 0xffc00d38 /* DMA Channel 4 Current Y Count Register */
307
308/* DMA Channel 5 Registers */
309
310#define DMA5_NEXT_DESC_PTR 0xffc00d40 /* DMA Channel 5 Next Descriptor Pointer Register */
311#define DMA5_START_ADDR 0xffc00d44 /* DMA Channel 5 Start Address Register */
312#define DMA5_CONFIG 0xffc00d48 /* DMA Channel 5 Configuration Register */
313#define DMA5_X_COUNT 0xffc00d50 /* DMA Channel 5 X Count Register */
314#define DMA5_X_MODIFY 0xffc00d54 /* DMA Channel 5 X Modify Register */
315#define DMA5_Y_COUNT 0xffc00d58 /* DMA Channel 5 Y Count Register */
316#define DMA5_Y_MODIFY 0xffc00d5c /* DMA Channel 5 Y Modify Register */
317#define DMA5_CURR_DESC_PTR 0xffc00d60 /* DMA Channel 5 Current Descriptor Pointer Register */
318#define DMA5_CURR_ADDR 0xffc00d64 /* DMA Channel 5 Current Address Register */
319#define DMA5_IRQ_STATUS 0xffc00d68 /* DMA Channel 5 Interrupt/Status Register */
320#define DMA5_PERIPHERAL_MAP 0xffc00d6c /* DMA Channel 5 Peripheral Map Register */
321#define DMA5_CURR_X_COUNT 0xffc00d70 /* DMA Channel 5 Current X Count Register */
322#define DMA5_CURR_Y_COUNT 0xffc00d78 /* DMA Channel 5 Current Y Count Register */
323
324/* DMA Channel 6 Registers */
325
326#define DMA6_NEXT_DESC_PTR 0xffc00d80 /* DMA Channel 6 Next Descriptor Pointer Register */
327#define DMA6_START_ADDR 0xffc00d84 /* DMA Channel 6 Start Address Register */
328#define DMA6_CONFIG 0xffc00d88 /* DMA Channel 6 Configuration Register */
329#define DMA6_X_COUNT 0xffc00d90 /* DMA Channel 6 X Count Register */
330#define DMA6_X_MODIFY 0xffc00d94 /* DMA Channel 6 X Modify Register */
331#define DMA6_Y_COUNT 0xffc00d98 /* DMA Channel 6 Y Count Register */
332#define DMA6_Y_MODIFY 0xffc00d9c /* DMA Channel 6 Y Modify Register */
333#define DMA6_CURR_DESC_PTR 0xffc00da0 /* DMA Channel 6 Current Descriptor Pointer Register */
334#define DMA6_CURR_ADDR 0xffc00da4 /* DMA Channel 6 Current Address Register */
335#define DMA6_IRQ_STATUS 0xffc00da8 /* DMA Channel 6 Interrupt/Status Register */
336#define DMA6_PERIPHERAL_MAP 0xffc00dac /* DMA Channel 6 Peripheral Map Register */
337#define DMA6_CURR_X_COUNT 0xffc00db0 /* DMA Channel 6 Current X Count Register */
338#define DMA6_CURR_Y_COUNT 0xffc00db8 /* DMA Channel 6 Current Y Count Register */
339
340/* DMA Channel 7 Registers */
341
342#define DMA7_NEXT_DESC_PTR 0xffc00dc0 /* DMA Channel 7 Next Descriptor Pointer Register */
343#define DMA7_START_ADDR 0xffc00dc4 /* DMA Channel 7 Start Address Register */
344#define DMA7_CONFIG 0xffc00dc8 /* DMA Channel 7 Configuration Register */
345#define DMA7_X_COUNT 0xffc00dd0 /* DMA Channel 7 X Count Register */
346#define DMA7_X_MODIFY 0xffc00dd4 /* DMA Channel 7 X Modify Register */
347#define DMA7_Y_COUNT 0xffc00dd8 /* DMA Channel 7 Y Count Register */
348#define DMA7_Y_MODIFY 0xffc00ddc /* DMA Channel 7 Y Modify Register */
349#define DMA7_CURR_DESC_PTR 0xffc00de0 /* DMA Channel 7 Current Descriptor Pointer Register */
350#define DMA7_CURR_ADDR 0xffc00de4 /* DMA Channel 7 Current Address Register */
351#define DMA7_IRQ_STATUS 0xffc00de8 /* DMA Channel 7 Interrupt/Status Register */
352#define DMA7_PERIPHERAL_MAP 0xffc00dec /* DMA Channel 7 Peripheral Map Register */
353#define DMA7_CURR_X_COUNT 0xffc00df0 /* DMA Channel 7 Current X Count Register */
354#define DMA7_CURR_Y_COUNT 0xffc00df8 /* DMA Channel 7 Current Y Count Register */
355
356/* DMA Channel 8 Registers */
357
358#define DMA8_NEXT_DESC_PTR 0xffc00e00 /* DMA Channel 8 Next Descriptor Pointer Register */
359#define DMA8_START_ADDR 0xffc00e04 /* DMA Channel 8 Start Address Register */
360#define DMA8_CONFIG 0xffc00e08 /* DMA Channel 8 Configuration Register */
361#define DMA8_X_COUNT 0xffc00e10 /* DMA Channel 8 X Count Register */
362#define DMA8_X_MODIFY 0xffc00e14 /* DMA Channel 8 X Modify Register */
363#define DMA8_Y_COUNT 0xffc00e18 /* DMA Channel 8 Y Count Register */
364#define DMA8_Y_MODIFY 0xffc00e1c /* DMA Channel 8 Y Modify Register */
365#define DMA8_CURR_DESC_PTR 0xffc00e20 /* DMA Channel 8 Current Descriptor Pointer Register */
366#define DMA8_CURR_ADDR 0xffc00e24 /* DMA Channel 8 Current Address Register */
367#define DMA8_IRQ_STATUS 0xffc00e28 /* DMA Channel 8 Interrupt/Status Register */
368#define DMA8_PERIPHERAL_MAP 0xffc00e2c /* DMA Channel 8 Peripheral Map Register */
369#define DMA8_CURR_X_COUNT 0xffc00e30 /* DMA Channel 8 Current X Count Register */
370#define DMA8_CURR_Y_COUNT 0xffc00e38 /* DMA Channel 8 Current Y Count Register */
371
372/* DMA Channel 9 Registers */
373
374#define DMA9_NEXT_DESC_PTR 0xffc00e40 /* DMA Channel 9 Next Descriptor Pointer Register */
375#define DMA9_START_ADDR 0xffc00e44 /* DMA Channel 9 Start Address Register */
376#define DMA9_CONFIG 0xffc00e48 /* DMA Channel 9 Configuration Register */
377#define DMA9_X_COUNT 0xffc00e50 /* DMA Channel 9 X Count Register */
378#define DMA9_X_MODIFY 0xffc00e54 /* DMA Channel 9 X Modify Register */
379#define DMA9_Y_COUNT 0xffc00e58 /* DMA Channel 9 Y Count Register */
380#define DMA9_Y_MODIFY 0xffc00e5c /* DMA Channel 9 Y Modify Register */
381#define DMA9_CURR_DESC_PTR 0xffc00e60 /* DMA Channel 9 Current Descriptor Pointer Register */
382#define DMA9_CURR_ADDR 0xffc00e64 /* DMA Channel 9 Current Address Register */
383#define DMA9_IRQ_STATUS 0xffc00e68 /* DMA Channel 9 Interrupt/Status Register */
384#define DMA9_PERIPHERAL_MAP 0xffc00e6c /* DMA Channel 9 Peripheral Map Register */
385#define DMA9_CURR_X_COUNT 0xffc00e70 /* DMA Channel 9 Current X Count Register */
386#define DMA9_CURR_Y_COUNT 0xffc00e78 /* DMA Channel 9 Current Y Count Register */
387
388/* DMA Channel 10 Registers */
389
390#define DMA10_NEXT_DESC_PTR 0xffc00e80 /* DMA Channel 10 Next Descriptor Pointer Register */
391#define DMA10_START_ADDR 0xffc00e84 /* DMA Channel 10 Start Address Register */
392#define DMA10_CONFIG 0xffc00e88 /* DMA Channel 10 Configuration Register */
393#define DMA10_X_COUNT 0xffc00e90 /* DMA Channel 10 X Count Register */
394#define DMA10_X_MODIFY 0xffc00e94 /* DMA Channel 10 X Modify Register */
395#define DMA10_Y_COUNT 0xffc00e98 /* DMA Channel 10 Y Count Register */
396#define DMA10_Y_MODIFY 0xffc00e9c /* DMA Channel 10 Y Modify Register */
397#define DMA10_CURR_DESC_PTR 0xffc00ea0 /* DMA Channel 10 Current Descriptor Pointer Register */
398#define DMA10_CURR_ADDR 0xffc00ea4 /* DMA Channel 10 Current Address Register */
399#define DMA10_IRQ_STATUS 0xffc00ea8 /* DMA Channel 10 Interrupt/Status Register */
400#define DMA10_PERIPHERAL_MAP 0xffc00eac /* DMA Channel 10 Peripheral Map Register */
401#define DMA10_CURR_X_COUNT 0xffc00eb0 /* DMA Channel 10 Current X Count Register */
402#define DMA10_CURR_Y_COUNT 0xffc00eb8 /* DMA Channel 10 Current Y Count Register */
403
404/* DMA Channel 11 Registers */
405
406#define DMA11_NEXT_DESC_PTR 0xffc00ec0 /* DMA Channel 11 Next Descriptor Pointer Register */
407#define DMA11_START_ADDR 0xffc00ec4 /* DMA Channel 11 Start Address Register */
408#define DMA11_CONFIG 0xffc00ec8 /* DMA Channel 11 Configuration Register */
409#define DMA11_X_COUNT 0xffc00ed0 /* DMA Channel 11 X Count Register */
410#define DMA11_X_MODIFY 0xffc00ed4 /* DMA Channel 11 X Modify Register */
411#define DMA11_Y_COUNT 0xffc00ed8 /* DMA Channel 11 Y Count Register */
412#define DMA11_Y_MODIFY 0xffc00edc /* DMA Channel 11 Y Modify Register */
413#define DMA11_CURR_DESC_PTR 0xffc00ee0 /* DMA Channel 11 Current Descriptor Pointer Register */
414#define DMA11_CURR_ADDR 0xffc00ee4 /* DMA Channel 11 Current Address Register */
415#define DMA11_IRQ_STATUS 0xffc00ee8 /* DMA Channel 11 Interrupt/Status Register */
416#define DMA11_PERIPHERAL_MAP 0xffc00eec /* DMA Channel 11 Peripheral Map Register */
417#define DMA11_CURR_X_COUNT 0xffc00ef0 /* DMA Channel 11 Current X Count Register */
418#define DMA11_CURR_Y_COUNT 0xffc00ef8 /* DMA Channel 11 Current Y Count Register */
419
420/* MDMA Stream 0 Registers */
421
422#define MDMA_D0_NEXT_DESC_PTR 0xffc00f00 /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
423#define MDMA_D0_START_ADDR 0xffc00f04 /* Memory DMA Stream 0 Destination Start Address Register */
424#define MDMA_D0_CONFIG 0xffc00f08 /* Memory DMA Stream 0 Destination Configuration Register */
425#define MDMA_D0_X_COUNT 0xffc00f10 /* Memory DMA Stream 0 Destination X Count Register */
426#define MDMA_D0_X_MODIFY 0xffc00f14 /* Memory DMA Stream 0 Destination X Modify Register */
427#define MDMA_D0_Y_COUNT 0xffc00f18 /* Memory DMA Stream 0 Destination Y Count Register */
428#define MDMA_D0_Y_MODIFY 0xffc00f1c /* Memory DMA Stream 0 Destination Y Modify Register */
429#define MDMA_D0_CURR_DESC_PTR 0xffc00f20 /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
430#define MDMA_D0_CURR_ADDR 0xffc00f24 /* Memory DMA Stream 0 Destination Current Address Register */
431#define MDMA_D0_IRQ_STATUS 0xffc00f28 /* Memory DMA Stream 0 Destination Interrupt/Status Register */
432#define MDMA_D0_PERIPHERAL_MAP 0xffc00f2c /* Memory DMA Stream 0 Destination Peripheral Map Register */
433#define MDMA_D0_CURR_X_COUNT 0xffc00f30 /* Memory DMA Stream 0 Destination Current X Count Register */
434#define MDMA_D0_CURR_Y_COUNT 0xffc00f38 /* Memory DMA Stream 0 Destination Current Y Count Register */
435#define MDMA_S0_NEXT_DESC_PTR 0xffc00f40 /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
436#define MDMA_S0_START_ADDR 0xffc00f44 /* Memory DMA Stream 0 Source Start Address Register */
437#define MDMA_S0_CONFIG 0xffc00f48 /* Memory DMA Stream 0 Source Configuration Register */
438#define MDMA_S0_X_COUNT 0xffc00f50 /* Memory DMA Stream 0 Source X Count Register */
439#define MDMA_S0_X_MODIFY 0xffc00f54 /* Memory DMA Stream 0 Source X Modify Register */
440#define MDMA_S0_Y_COUNT 0xffc00f58 /* Memory DMA Stream 0 Source Y Count Register */
441#define MDMA_S0_Y_MODIFY 0xffc00f5c /* Memory DMA Stream 0 Source Y Modify Register */
442#define MDMA_S0_CURR_DESC_PTR 0xffc00f60 /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
443#define MDMA_S0_CURR_ADDR 0xffc00f64 /* Memory DMA Stream 0 Source Current Address Register */
444#define MDMA_S0_IRQ_STATUS 0xffc00f68 /* Memory DMA Stream 0 Source Interrupt/Status Register */
445#define MDMA_S0_PERIPHERAL_MAP 0xffc00f6c /* Memory DMA Stream 0 Source Peripheral Map Register */
446#define MDMA_S0_CURR_X_COUNT 0xffc00f70 /* Memory DMA Stream 0 Source Current X Count Register */
447#define MDMA_S0_CURR_Y_COUNT 0xffc00f78 /* Memory DMA Stream 0 Source Current Y Count Register */
448
449/* MDMA Stream 1 Registers */
450
451#define MDMA_D1_NEXT_DESC_PTR 0xffc00f80 /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
452#define MDMA_D1_START_ADDR 0xffc00f84 /* Memory DMA Stream 1 Destination Start Address Register */
453#define MDMA_D1_CONFIG 0xffc00f88 /* Memory DMA Stream 1 Destination Configuration Register */
454#define MDMA_D1_X_COUNT 0xffc00f90 /* Memory DMA Stream 1 Destination X Count Register */
455#define MDMA_D1_X_MODIFY 0xffc00f94 /* Memory DMA Stream 1 Destination X Modify Register */
456#define MDMA_D1_Y_COUNT 0xffc00f98 /* Memory DMA Stream 1 Destination Y Count Register */
457#define MDMA_D1_Y_MODIFY 0xffc00f9c /* Memory DMA Stream 1 Destination Y Modify Register */
458#define MDMA_D1_CURR_DESC_PTR 0xffc00fa0 /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
459#define MDMA_D1_CURR_ADDR 0xffc00fa4 /* Memory DMA Stream 1 Destination Current Address Register */
460#define MDMA_D1_IRQ_STATUS 0xffc00fa8 /* Memory DMA Stream 1 Destination Interrupt/Status Register */
461#define MDMA_D1_PERIPHERAL_MAP 0xffc00fac /* Memory DMA Stream 1 Destination Peripheral Map Register */
462#define MDMA_D1_CURR_X_COUNT 0xffc00fb0 /* Memory DMA Stream 1 Destination Current X Count Register */
463#define MDMA_D1_CURR_Y_COUNT 0xffc00fb8 /* Memory DMA Stream 1 Destination Current Y Count Register */
464#define MDMA_S1_NEXT_DESC_PTR 0xffc00fc0 /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
465#define MDMA_S1_START_ADDR 0xffc00fc4 /* Memory DMA Stream 1 Source Start Address Register */
466#define MDMA_S1_CONFIG 0xffc00fc8 /* Memory DMA Stream 1 Source Configuration Register */
467#define MDMA_S1_X_COUNT 0xffc00fd0 /* Memory DMA Stream 1 Source X Count Register */
468#define MDMA_S1_X_MODIFY 0xffc00fd4 /* Memory DMA Stream 1 Source X Modify Register */
469#define MDMA_S1_Y_COUNT 0xffc00fd8 /* Memory DMA Stream 1 Source Y Count Register */
470#define MDMA_S1_Y_MODIFY 0xffc00fdc /* Memory DMA Stream 1 Source Y Modify Register */
471#define MDMA_S1_CURR_DESC_PTR 0xffc00fe0 /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
472#define MDMA_S1_CURR_ADDR 0xffc00fe4 /* Memory DMA Stream 1 Source Current Address Register */
473#define MDMA_S1_IRQ_STATUS 0xffc00fe8 /* Memory DMA Stream 1 Source Interrupt/Status Register */
474#define MDMA_S1_PERIPHERAL_MAP 0xffc00fec /* Memory DMA Stream 1 Source Peripheral Map Register */
475#define MDMA_S1_CURR_X_COUNT 0xffc00ff0 /* Memory DMA Stream 1 Source Current X Count Register */
476#define MDMA_S1_CURR_Y_COUNT 0xffc00ff8 /* Memory DMA Stream 1 Source Current Y Count Register */
477
478/* UART3 Registers */
479
480#define UART3_DLL 0xffc03100 /* Divisor Latch Low Byte */
481#define UART3_DLH 0xffc03104 /* Divisor Latch High Byte */
482#define UART3_GCTL 0xffc03108 /* Global Control Register */
483#define UART3_LCR 0xffc0310c /* Line Control Register */
484#define UART3_MCR 0xffc03110 /* Modem Control Register */
485#define UART3_LSR 0xffc03114 /* Line Status Register */
486#define UART3_MSR 0xffc03118 /* Modem Status Register */
487#define UART3_SCR 0xffc0311c /* Scratch Register */
488#define UART3_IER_SET 0xffc03120 /* Interrupt Enable Register Set */
489#define UART3_IER_CLEAR 0xffc03124 /* Interrupt Enable Register Clear */
490#define UART3_THR 0xffc03128 /* Transmit Hold Register */
491#define UART3_RBR 0xffc0312c /* Receive Buffer Register */
492
493/* EPPI1 Registers */
494
495#define EPPI1_STATUS 0xffc01300 /* EPPI1 Status Register */
496#define EPPI1_HCOUNT 0xffc01304 /* EPPI1 Horizontal Transfer Count Register */
497#define EPPI1_HDELAY 0xffc01308 /* EPPI1 Horizontal Delay Count Register */
498#define EPPI1_VCOUNT 0xffc0130c /* EPPI1 Vertical Transfer Count Register */
499#define EPPI1_VDELAY 0xffc01310 /* EPPI1 Vertical Delay Count Register */
500#define EPPI1_FRAME 0xffc01314 /* EPPI1 Lines per Frame Register */
501#define EPPI1_LINE 0xffc01318 /* EPPI1 Samples per Line Register */
502#define EPPI1_CLKDIV 0xffc0131c /* EPPI1 Clock Divide Register */
503#define EPPI1_CONTROL 0xffc01320 /* EPPI1 Control Register */
504#define EPPI1_FS1W_HBL 0xffc01324 /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
505#define EPPI1_FS1P_AVPL 0xffc01328 /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
506#define EPPI1_FS2W_LVB 0xffc0132c /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
507#define EPPI1_FS2P_LAVF 0xffc01330 /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
508#define EPPI1_CLIP 0xffc01334 /* EPPI1 Clipping Register */
509
510/* Port Interrupt 0 Registers (32-bit) */
511
512#define PINT0_MASK_SET 0xffc01400 /* Pin Interrupt 0 Mask Set Register */
513#define PINT0_MASK_CLEAR 0xffc01404 /* Pin Interrupt 0 Mask Clear Register */
514#define PINT0_REQUEST 0xffc01408 /* Pin Interrupt 0 Interrupt Request Register */
515#define PINT0_ASSIGN 0xffc0140c /* Pin Interrupt 0 Port Assign Register */
516#define PINT0_EDGE_SET 0xffc01410 /* Pin Interrupt 0 Edge-sensitivity Set Register */
517#define PINT0_EDGE_CLEAR 0xffc01414 /* Pin Interrupt 0 Edge-sensitivity Clear Register */
518#define PINT0_INVERT_SET 0xffc01418 /* Pin Interrupt 0 Inversion Set Register */
519#define PINT0_INVERT_CLEAR 0xffc0141c /* Pin Interrupt 0 Inversion Clear Register */
520#define PINT0_PINSTATE 0xffc01420 /* Pin Interrupt 0 Pin Status Register */
521#define PINT0_LATCH 0xffc01424 /* Pin Interrupt 0 Latch Register */
522
523/* Port Interrupt 1 Registers (32-bit) */
524
525#define PINT1_MASK_SET 0xffc01430 /* Pin Interrupt 1 Mask Set Register */
526#define PINT1_MASK_CLEAR 0xffc01434 /* Pin Interrupt 1 Mask Clear Register */
527#define PINT1_REQUEST 0xffc01438 /* Pin Interrupt 1 Interrupt Request Register */
528#define PINT1_ASSIGN 0xffc0143c /* Pin Interrupt 1 Port Assign Register */
529#define PINT1_EDGE_SET 0xffc01440 /* Pin Interrupt 1 Edge-sensitivity Set Register */
530#define PINT1_EDGE_CLEAR 0xffc01444 /* Pin Interrupt 1 Edge-sensitivity Clear Register */
531#define PINT1_INVERT_SET 0xffc01448 /* Pin Interrupt 1 Inversion Set Register */
532#define PINT1_INVERT_CLEAR 0xffc0144c /* Pin Interrupt 1 Inversion Clear Register */
533#define PINT1_PINSTATE 0xffc01450 /* Pin Interrupt 1 Pin Status Register */
534#define PINT1_LATCH 0xffc01454 /* Pin Interrupt 1 Latch Register */
535
536/* Port Interrupt 2 Registers (32-bit) */
537
538#define PINT2_MASK_SET 0xffc01460 /* Pin Interrupt 2 Mask Set Register */
539#define PINT2_MASK_CLEAR 0xffc01464 /* Pin Interrupt 2 Mask Clear Register */
540#define PINT2_REQUEST 0xffc01468 /* Pin Interrupt 2 Interrupt Request Register */
541#define PINT2_ASSIGN 0xffc0146c /* Pin Interrupt 2 Port Assign Register */
542#define PINT2_EDGE_SET 0xffc01470 /* Pin Interrupt 2 Edge-sensitivity Set Register */
543#define PINT2_EDGE_CLEAR 0xffc01474 /* Pin Interrupt 2 Edge-sensitivity Clear Register */
544#define PINT2_INVERT_SET 0xffc01478 /* Pin Interrupt 2 Inversion Set Register */
545#define PINT2_INVERT_CLEAR 0xffc0147c /* Pin Interrupt 2 Inversion Clear Register */
546#define PINT2_PINSTATE 0xffc01480 /* Pin Interrupt 2 Pin Status Register */
547#define PINT2_LATCH 0xffc01484 /* Pin Interrupt 2 Latch Register */
548
549/* Port Interrupt 3 Registers (32-bit) */
550
551#define PINT3_MASK_SET 0xffc01490 /* Pin Interrupt 3 Mask Set Register */
552#define PINT3_MASK_CLEAR 0xffc01494 /* Pin Interrupt 3 Mask Clear Register */
553#define PINT3_REQUEST 0xffc01498 /* Pin Interrupt 3 Interrupt Request Register */
554#define PINT3_ASSIGN 0xffc0149c /* Pin Interrupt 3 Port Assign Register */
555#define PINT3_EDGE_SET 0xffc014a0 /* Pin Interrupt 3 Edge-sensitivity Set Register */
556#define PINT3_EDGE_CLEAR 0xffc014a4 /* Pin Interrupt 3 Edge-sensitivity Clear Register */
557#define PINT3_INVERT_SET 0xffc014a8 /* Pin Interrupt 3 Inversion Set Register */
558#define PINT3_INVERT_CLEAR 0xffc014ac /* Pin Interrupt 3 Inversion Clear Register */
559#define PINT3_PINSTATE 0xffc014b0 /* Pin Interrupt 3 Pin Status Register */
560#define PINT3_LATCH 0xffc014b4 /* Pin Interrupt 3 Latch Register */
561
562/* Port A Registers */
563
564#define PORTA_FER 0xffc014c0 /* Function Enable Register */
565#define PORTA 0xffc014c4 /* GPIO Data Register */
566#define PORTA_SET 0xffc014c8 /* GPIO Data Set Register */
567#define PORTA_CLEAR 0xffc014cc /* GPIO Data Clear Register */
568#define PORTA_DIR_SET 0xffc014d0 /* GPIO Direction Set Register */
569#define PORTA_DIR_CLEAR 0xffc014d4 /* GPIO Direction Clear Register */
570#define PORTA_INEN 0xffc014d8 /* GPIO Input Enable Register */
571#define PORTA_MUX 0xffc014dc /* Multiplexer Control Register */
572
573/* Port B Registers */
574
575#define PORTB_FER 0xffc014e0 /* Function Enable Register */
576#define PORTB 0xffc014e4 /* GPIO Data Register */
577#define PORTB_SET 0xffc014e8 /* GPIO Data Set Register */
578#define PORTB_CLEAR 0xffc014ec /* GPIO Data Clear Register */
579#define PORTB_DIR_SET 0xffc014f0 /* GPIO Direction Set Register */
580#define PORTB_DIR_CLEAR 0xffc014f4 /* GPIO Direction Clear Register */
581#define PORTB_INEN 0xffc014f8 /* GPIO Input Enable Register */
582#define PORTB_MUX 0xffc014fc /* Multiplexer Control Register */
583
584/* Port C Registers */
585
586#define PORTC_FER 0xffc01500 /* Function Enable Register */
587#define PORTC 0xffc01504 /* GPIO Data Register */
588#define PORTC_SET 0xffc01508 /* GPIO Data Set Register */
589#define PORTC_CLEAR 0xffc0150c /* GPIO Data Clear Register */
590#define PORTC_DIR_SET 0xffc01510 /* GPIO Direction Set Register */
591#define PORTC_DIR_CLEAR 0xffc01514 /* GPIO Direction Clear Register */
592#define PORTC_INEN 0xffc01518 /* GPIO Input Enable Register */
593#define PORTC_MUX 0xffc0151c /* Multiplexer Control Register */
594
595/* Port D Registers */
596
597#define PORTD_FER 0xffc01520 /* Function Enable Register */
598#define PORTD 0xffc01524 /* GPIO Data Register */
599#define PORTD_SET 0xffc01528 /* GPIO Data Set Register */
600#define PORTD_CLEAR 0xffc0152c /* GPIO Data Clear Register */
601#define PORTD_DIR_SET 0xffc01530 /* GPIO Direction Set Register */
602#define PORTD_DIR_CLEAR 0xffc01534 /* GPIO Direction Clear Register */
603#define PORTD_INEN 0xffc01538 /* GPIO Input Enable Register */
604#define PORTD_MUX 0xffc0153c /* Multiplexer Control Register */
605
606/* Port E Registers */
607
608#define PORTE_FER 0xffc01540 /* Function Enable Register */
609#define PORTE 0xffc01544 /* GPIO Data Register */
610#define PORTE_SET 0xffc01548 /* GPIO Data Set Register */
611#define PORTE_CLEAR 0xffc0154c /* GPIO Data Clear Register */
612#define PORTE_DIR_SET 0xffc01550 /* GPIO Direction Set Register */
613#define PORTE_DIR_CLEAR 0xffc01554 /* GPIO Direction Clear Register */
614#define PORTE_INEN 0xffc01558 /* GPIO Input Enable Register */
615#define PORTE_MUX 0xffc0155c /* Multiplexer Control Register */
616
617/* Port F Registers */
618
619#define PORTF_FER 0xffc01560 /* Function Enable Register */
620#define PORTF 0xffc01564 /* GPIO Data Register */
621#define PORTF_SET 0xffc01568 /* GPIO Data Set Register */
622#define PORTF_CLEAR 0xffc0156c /* GPIO Data Clear Register */
623#define PORTF_DIR_SET 0xffc01570 /* GPIO Direction Set Register */
624#define PORTF_DIR_CLEAR 0xffc01574 /* GPIO Direction Clear Register */
625#define PORTF_INEN 0xffc01578 /* GPIO Input Enable Register */
626#define PORTF_MUX 0xffc0157c /* Multiplexer Control Register */
627
628/* Port G Registers */
629
630#define PORTG_FER 0xffc01580 /* Function Enable Register */
631#define PORTG 0xffc01584 /* GPIO Data Register */
632#define PORTG_SET 0xffc01588 /* GPIO Data Set Register */
633#define PORTG_CLEAR 0xffc0158c /* GPIO Data Clear Register */
634#define PORTG_DIR_SET 0xffc01590 /* GPIO Direction Set Register */
635#define PORTG_DIR_CLEAR 0xffc01594 /* GPIO Direction Clear Register */
636#define PORTG_INEN 0xffc01598 /* GPIO Input Enable Register */
637#define PORTG_MUX 0xffc0159c /* Multiplexer Control Register */
638
639/* Port H Registers */
640
641#define PORTH_FER 0xffc015a0 /* Function Enable Register */
642#define PORTH 0xffc015a4 /* GPIO Data Register */
643#define PORTH_SET 0xffc015a8 /* GPIO Data Set Register */
644#define PORTH_CLEAR 0xffc015ac /* GPIO Data Clear Register */
645#define PORTH_DIR_SET 0xffc015b0 /* GPIO Direction Set Register */
646#define PORTH_DIR_CLEAR 0xffc015b4 /* GPIO Direction Clear Register */
647#define PORTH_INEN 0xffc015b8 /* GPIO Input Enable Register */
648#define PORTH_MUX 0xffc015bc /* Multiplexer Control Register */
649
650/* Port I Registers */
651
652#define PORTI_FER 0xffc015c0 /* Function Enable Register */
653#define PORTI 0xffc015c4 /* GPIO Data Register */
654#define PORTI_SET 0xffc015c8 /* GPIO Data Set Register */
655#define PORTI_CLEAR 0xffc015cc /* GPIO Data Clear Register */
656#define PORTI_DIR_SET 0xffc015d0 /* GPIO Direction Set Register */
657#define PORTI_DIR_CLEAR 0xffc015d4 /* GPIO Direction Clear Register */
658#define PORTI_INEN 0xffc015d8 /* GPIO Input Enable Register */
659#define PORTI_MUX 0xffc015dc /* Multiplexer Control Register */
660
661/* Port J Registers */
662
663#define PORTJ_FER 0xffc015e0 /* Function Enable Register */
664#define PORTJ 0xffc015e4 /* GPIO Data Register */
665#define PORTJ_SET 0xffc015e8 /* GPIO Data Set Register */
666#define PORTJ_CLEAR 0xffc015ec /* GPIO Data Clear Register */
667#define PORTJ_DIR_SET 0xffc015f0 /* GPIO Direction Set Register */
668#define PORTJ_DIR_CLEAR 0xffc015f4 /* GPIO Direction Clear Register */
669#define PORTJ_INEN 0xffc015f8 /* GPIO Input Enable Register */
670#define PORTJ_MUX 0xffc015fc /* Multiplexer Control Register */
671
672/* PWM Timer Registers */
673
674#define TIMER0_CONFIG 0xffc01600 /* Timer 0 Configuration Register */
675#define TIMER0_COUNTER 0xffc01604 /* Timer 0 Counter Register */
676#define TIMER0_PERIOD 0xffc01608 /* Timer 0 Period Register */
677#define TIMER0_WIDTH 0xffc0160c /* Timer 0 Width Register */
678#define TIMER1_CONFIG 0xffc01610 /* Timer 1 Configuration Register */
679#define TIMER1_COUNTER 0xffc01614 /* Timer 1 Counter Register */
680#define TIMER1_PERIOD 0xffc01618 /* Timer 1 Period Register */
681#define TIMER1_WIDTH 0xffc0161c /* Timer 1 Width Register */
682#define TIMER2_CONFIG 0xffc01620 /* Timer 2 Configuration Register */
683#define TIMER2_COUNTER 0xffc01624 /* Timer 2 Counter Register */
684#define TIMER2_PERIOD 0xffc01628 /* Timer 2 Period Register */
685#define TIMER2_WIDTH 0xffc0162c /* Timer 2 Width Register */
686#define TIMER3_CONFIG 0xffc01630 /* Timer 3 Configuration Register */
687#define TIMER3_COUNTER 0xffc01634 /* Timer 3 Counter Register */
688#define TIMER3_PERIOD 0xffc01638 /* Timer 3 Period Register */
689#define TIMER3_WIDTH 0xffc0163c /* Timer 3 Width Register */
690#define TIMER4_CONFIG 0xffc01640 /* Timer 4 Configuration Register */
691#define TIMER4_COUNTER 0xffc01644 /* Timer 4 Counter Register */
692#define TIMER4_PERIOD 0xffc01648 /* Timer 4 Period Register */
693#define TIMER4_WIDTH 0xffc0164c /* Timer 4 Width Register */
694#define TIMER5_CONFIG 0xffc01650 /* Timer 5 Configuration Register */
695#define TIMER5_COUNTER 0xffc01654 /* Timer 5 Counter Register */
696#define TIMER5_PERIOD 0xffc01658 /* Timer 5 Period Register */
697#define TIMER5_WIDTH 0xffc0165c /* Timer 5 Width Register */
698#define TIMER6_CONFIG 0xffc01660 /* Timer 6 Configuration Register */
699#define TIMER6_COUNTER 0xffc01664 /* Timer 6 Counter Register */
700#define TIMER6_PERIOD 0xffc01668 /* Timer 6 Period Register */
701#define TIMER6_WIDTH 0xffc0166c /* Timer 6 Width Register */
702#define TIMER7_CONFIG 0xffc01670 /* Timer 7 Configuration Register */
703#define TIMER7_COUNTER 0xffc01674 /* Timer 7 Counter Register */
704#define TIMER7_PERIOD 0xffc01678 /* Timer 7 Period Register */
705#define TIMER7_WIDTH 0xffc0167c /* Timer 7 Width Register */
706
707/* Timer Group of 8 */
708
709#define TIMER_ENABLE0 0xffc01680 /* Timer Group of 8 Enable Register */
710#define TIMER_DISABLE0 0xffc01684 /* Timer Group of 8 Disable Register */
711#define TIMER_STATUS0 0xffc01688 /* Timer Group of 8 Status Register */
712
713/* DMAC1 Registers */
714
715#define DMAC1_TCPER 0xffc01b0c /* DMA Controller 1 Traffic Control Periods Register */
716#define DMAC1_TCCNT 0xffc01b10 /* DMA Controller 1 Current Counts Register */
717
718/* DMA Channel 12 Registers */
719
720#define DMA12_NEXT_DESC_PTR 0xffc01c00 /* DMA Channel 12 Next Descriptor Pointer Register */
721#define DMA12_START_ADDR 0xffc01c04 /* DMA Channel 12 Start Address Register */
722#define DMA12_CONFIG 0xffc01c08 /* DMA Channel 12 Configuration Register */
723#define DMA12_X_COUNT 0xffc01c10 /* DMA Channel 12 X Count Register */
724#define DMA12_X_MODIFY 0xffc01c14 /* DMA Channel 12 X Modify Register */
725#define DMA12_Y_COUNT 0xffc01c18 /* DMA Channel 12 Y Count Register */
726#define DMA12_Y_MODIFY 0xffc01c1c /* DMA Channel 12 Y Modify Register */
727#define DMA12_CURR_DESC_PTR 0xffc01c20 /* DMA Channel 12 Current Descriptor Pointer Register */
728#define DMA12_CURR_ADDR 0xffc01c24 /* DMA Channel 12 Current Address Register */
729#define DMA12_IRQ_STATUS 0xffc01c28 /* DMA Channel 12 Interrupt/Status Register */
730#define DMA12_PERIPHERAL_MAP 0xffc01c2c /* DMA Channel 12 Peripheral Map Register */
731#define DMA12_CURR_X_COUNT 0xffc01c30 /* DMA Channel 12 Current X Count Register */
732#define DMA12_CURR_Y_COUNT 0xffc01c38 /* DMA Channel 12 Current Y Count Register */
733
734/* DMA Channel 13 Registers */
735
736#define DMA13_NEXT_DESC_PTR 0xffc01c40 /* DMA Channel 13 Next Descriptor Pointer Register */
737#define DMA13_START_ADDR 0xffc01c44 /* DMA Channel 13 Start Address Register */
738#define DMA13_CONFIG 0xffc01c48 /* DMA Channel 13 Configuration Register */
739#define DMA13_X_COUNT 0xffc01c50 /* DMA Channel 13 X Count Register */
740#define DMA13_X_MODIFY 0xffc01c54 /* DMA Channel 13 X Modify Register */
741#define DMA13_Y_COUNT 0xffc01c58 /* DMA Channel 13 Y Count Register */
742#define DMA13_Y_MODIFY 0xffc01c5c /* DMA Channel 13 Y Modify Register */
743#define DMA13_CURR_DESC_PTR 0xffc01c60 /* DMA Channel 13 Current Descriptor Pointer Register */
744#define DMA13_CURR_ADDR 0xffc01c64 /* DMA Channel 13 Current Address Register */
745#define DMA13_IRQ_STATUS 0xffc01c68 /* DMA Channel 13 Interrupt/Status Register */
746#define DMA13_PERIPHERAL_MAP 0xffc01c6c /* DMA Channel 13 Peripheral Map Register */
747#define DMA13_CURR_X_COUNT 0xffc01c70 /* DMA Channel 13 Current X Count Register */
748#define DMA13_CURR_Y_COUNT 0xffc01c78 /* DMA Channel 13 Current Y Count Register */
749
750/* DMA Channel 14 Registers */
751
752#define DMA14_NEXT_DESC_PTR 0xffc01c80 /* DMA Channel 14 Next Descriptor Pointer Register */
753#define DMA14_START_ADDR 0xffc01c84 /* DMA Channel 14 Start Address Register */
754#define DMA14_CONFIG 0xffc01c88 /* DMA Channel 14 Configuration Register */
755#define DMA14_X_COUNT 0xffc01c90 /* DMA Channel 14 X Count Register */
756#define DMA14_X_MODIFY 0xffc01c94 /* DMA Channel 14 X Modify Register */
757#define DMA14_Y_COUNT 0xffc01c98 /* DMA Channel 14 Y Count Register */
758#define DMA14_Y_MODIFY 0xffc01c9c /* DMA Channel 14 Y Modify Register */
759#define DMA14_CURR_DESC_PTR 0xffc01ca0 /* DMA Channel 14 Current Descriptor Pointer Register */
760#define DMA14_CURR_ADDR 0xffc01ca4 /* DMA Channel 14 Current Address Register */
761#define DMA14_IRQ_STATUS 0xffc01ca8 /* DMA Channel 14 Interrupt/Status Register */
762#define DMA14_PERIPHERAL_MAP 0xffc01cac /* DMA Channel 14 Peripheral Map Register */
763#define DMA14_CURR_X_COUNT 0xffc01cb0 /* DMA Channel 14 Current X Count Register */
764#define DMA14_CURR_Y_COUNT 0xffc01cb8 /* DMA Channel 14 Current Y Count Register */
765
766/* DMA Channel 15 Registers */
767
768#define DMA15_NEXT_DESC_PTR 0xffc01cc0 /* DMA Channel 15 Next Descriptor Pointer Register */
769#define DMA15_START_ADDR 0xffc01cc4 /* DMA Channel 15 Start Address Register */
770#define DMA15_CONFIG 0xffc01cc8 /* DMA Channel 15 Configuration Register */
771#define DMA15_X_COUNT 0xffc01cd0 /* DMA Channel 15 X Count Register */
772#define DMA15_X_MODIFY 0xffc01cd4 /* DMA Channel 15 X Modify Register */
773#define DMA15_Y_COUNT 0xffc01cd8 /* DMA Channel 15 Y Count Register */
774#define DMA15_Y_MODIFY 0xffc01cdc /* DMA Channel 15 Y Modify Register */
775#define DMA15_CURR_DESC_PTR 0xffc01ce0 /* DMA Channel 15 Current Descriptor Pointer Register */
776#define DMA15_CURR_ADDR 0xffc01ce4 /* DMA Channel 15 Current Address Register */
777#define DMA15_IRQ_STATUS 0xffc01ce8 /* DMA Channel 15 Interrupt/Status Register */
778#define DMA15_PERIPHERAL_MAP 0xffc01cec /* DMA Channel 15 Peripheral Map Register */
779#define DMA15_CURR_X_COUNT 0xffc01cf0 /* DMA Channel 15 Current X Count Register */
780#define DMA15_CURR_Y_COUNT 0xffc01cf8 /* DMA Channel 15 Current Y Count Register */
781
782/* DMA Channel 16 Registers */
783
784#define DMA16_NEXT_DESC_PTR 0xffc01d00 /* DMA Channel 16 Next Descriptor Pointer Register */
785#define DMA16_START_ADDR 0xffc01d04 /* DMA Channel 16 Start Address Register */
786#define DMA16_CONFIG 0xffc01d08 /* DMA Channel 16 Configuration Register */
787#define DMA16_X_COUNT 0xffc01d10 /* DMA Channel 16 X Count Register */
788#define DMA16_X_MODIFY 0xffc01d14 /* DMA Channel 16 X Modify Register */
789#define DMA16_Y_COUNT 0xffc01d18 /* DMA Channel 16 Y Count Register */
790#define DMA16_Y_MODIFY 0xffc01d1c /* DMA Channel 16 Y Modify Register */
791#define DMA16_CURR_DESC_PTR 0xffc01d20 /* DMA Channel 16 Current Descriptor Pointer Register */
792#define DMA16_CURR_ADDR 0xffc01d24 /* DMA Channel 16 Current Address Register */
793#define DMA16_IRQ_STATUS 0xffc01d28 /* DMA Channel 16 Interrupt/Status Register */
794#define DMA16_PERIPHERAL_MAP 0xffc01d2c /* DMA Channel 16 Peripheral Map Register */
795#define DMA16_CURR_X_COUNT 0xffc01d30 /* DMA Channel 16 Current X Count Register */
796#define DMA16_CURR_Y_COUNT 0xffc01d38 /* DMA Channel 16 Current Y Count Register */
797
798/* DMA Channel 17 Registers */
799
800#define DMA17_NEXT_DESC_PTR 0xffc01d40 /* DMA Channel 17 Next Descriptor Pointer Register */
801#define DMA17_START_ADDR 0xffc01d44 /* DMA Channel 17 Start Address Register */
802#define DMA17_CONFIG 0xffc01d48 /* DMA Channel 17 Configuration Register */
803#define DMA17_X_COUNT 0xffc01d50 /* DMA Channel 17 X Count Register */
804#define DMA17_X_MODIFY 0xffc01d54 /* DMA Channel 17 X Modify Register */
805#define DMA17_Y_COUNT 0xffc01d58 /* DMA Channel 17 Y Count Register */
806#define DMA17_Y_MODIFY 0xffc01d5c /* DMA Channel 17 Y Modify Register */
807#define DMA17_CURR_DESC_PTR 0xffc01d60 /* DMA Channel 17 Current Descriptor Pointer Register */
808#define DMA17_CURR_ADDR 0xffc01d64 /* DMA Channel 17 Current Address Register */
809#define DMA17_IRQ_STATUS 0xffc01d68 /* DMA Channel 17 Interrupt/Status Register */
810#define DMA17_PERIPHERAL_MAP 0xffc01d6c /* DMA Channel 17 Peripheral Map Register */
811#define DMA17_CURR_X_COUNT 0xffc01d70 /* DMA Channel 17 Current X Count Register */
812#define DMA17_CURR_Y_COUNT 0xffc01d78 /* DMA Channel 17 Current Y Count Register */
813
814/* DMA Channel 18 Registers */
815
816#define DMA18_NEXT_DESC_PTR 0xffc01d80 /* DMA Channel 18 Next Descriptor Pointer Register */
817#define DMA18_START_ADDR 0xffc01d84 /* DMA Channel 18 Start Address Register */
818#define DMA18_CONFIG 0xffc01d88 /* DMA Channel 18 Configuration Register */
819#define DMA18_X_COUNT 0xffc01d90 /* DMA Channel 18 X Count Register */
820#define DMA18_X_MODIFY 0xffc01d94 /* DMA Channel 18 X Modify Register */
821#define DMA18_Y_COUNT 0xffc01d98 /* DMA Channel 18 Y Count Register */
822#define DMA18_Y_MODIFY 0xffc01d9c /* DMA Channel 18 Y Modify Register */
823#define DMA18_CURR_DESC_PTR 0xffc01da0 /* DMA Channel 18 Current Descriptor Pointer Register */
824#define DMA18_CURR_ADDR 0xffc01da4 /* DMA Channel 18 Current Address Register */
825#define DMA18_IRQ_STATUS 0xffc01da8 /* DMA Channel 18 Interrupt/Status Register */
826#define DMA18_PERIPHERAL_MAP 0xffc01dac /* DMA Channel 18 Peripheral Map Register */
827#define DMA18_CURR_X_COUNT 0xffc01db0 /* DMA Channel 18 Current X Count Register */
828#define DMA18_CURR_Y_COUNT 0xffc01db8 /* DMA Channel 18 Current Y Count Register */
829
830/* DMA Channel 19 Registers */
831
832#define DMA19_NEXT_DESC_PTR 0xffc01dc0 /* DMA Channel 19 Next Descriptor Pointer Register */
833#define DMA19_START_ADDR 0xffc01dc4 /* DMA Channel 19 Start Address Register */
834#define DMA19_CONFIG 0xffc01dc8 /* DMA Channel 19 Configuration Register */
835#define DMA19_X_COUNT 0xffc01dd0 /* DMA Channel 19 X Count Register */
836#define DMA19_X_MODIFY 0xffc01dd4 /* DMA Channel 19 X Modify Register */
837#define DMA19_Y_COUNT 0xffc01dd8 /* DMA Channel 19 Y Count Register */
838#define DMA19_Y_MODIFY 0xffc01ddc /* DMA Channel 19 Y Modify Register */
839#define DMA19_CURR_DESC_PTR 0xffc01de0 /* DMA Channel 19 Current Descriptor Pointer Register */
840#define DMA19_CURR_ADDR 0xffc01de4 /* DMA Channel 19 Current Address Register */
841#define DMA19_IRQ_STATUS 0xffc01de8 /* DMA Channel 19 Interrupt/Status Register */
842#define DMA19_PERIPHERAL_MAP 0xffc01dec /* DMA Channel 19 Peripheral Map Register */
843#define DMA19_CURR_X_COUNT 0xffc01df0 /* DMA Channel 19 Current X Count Register */
844#define DMA19_CURR_Y_COUNT 0xffc01df8 /* DMA Channel 19 Current Y Count Register */
845
846/* DMA Channel 20 Registers */
847
848#define DMA20_NEXT_DESC_PTR 0xffc01e00 /* DMA Channel 20 Next Descriptor Pointer Register */
849#define DMA20_START_ADDR 0xffc01e04 /* DMA Channel 20 Start Address Register */
850#define DMA20_CONFIG 0xffc01e08 /* DMA Channel 20 Configuration Register */
851#define DMA20_X_COUNT 0xffc01e10 /* DMA Channel 20 X Count Register */
852#define DMA20_X_MODIFY 0xffc01e14 /* DMA Channel 20 X Modify Register */
853#define DMA20_Y_COUNT 0xffc01e18 /* DMA Channel 20 Y Count Register */
854#define DMA20_Y_MODIFY 0xffc01e1c /* DMA Channel 20 Y Modify Register */
855#define DMA20_CURR_DESC_PTR 0xffc01e20 /* DMA Channel 20 Current Descriptor Pointer Register */
856#define DMA20_CURR_ADDR 0xffc01e24 /* DMA Channel 20 Current Address Register */
857#define DMA20_IRQ_STATUS 0xffc01e28 /* DMA Channel 20 Interrupt/Status Register */
858#define DMA20_PERIPHERAL_MAP 0xffc01e2c /* DMA Channel 20 Peripheral Map Register */
859#define DMA20_CURR_X_COUNT 0xffc01e30 /* DMA Channel 20 Current X Count Register */
860#define DMA20_CURR_Y_COUNT 0xffc01e38 /* DMA Channel 20 Current Y Count Register */
861
862/* DMA Channel 21 Registers */
863
864#define DMA21_NEXT_DESC_PTR 0xffc01e40 /* DMA Channel 21 Next Descriptor Pointer Register */
865#define DMA21_START_ADDR 0xffc01e44 /* DMA Channel 21 Start Address Register */
866#define DMA21_CONFIG 0xffc01e48 /* DMA Channel 21 Configuration Register */
867#define DMA21_X_COUNT 0xffc01e50 /* DMA Channel 21 X Count Register */
868#define DMA21_X_MODIFY 0xffc01e54 /* DMA Channel 21 X Modify Register */
869#define DMA21_Y_COUNT 0xffc01e58 /* DMA Channel 21 Y Count Register */
870#define DMA21_Y_MODIFY 0xffc01e5c /* DMA Channel 21 Y Modify Register */
871#define DMA21_CURR_DESC_PTR 0xffc01e60 /* DMA Channel 21 Current Descriptor Pointer Register */
872#define DMA21_CURR_ADDR 0xffc01e64 /* DMA Channel 21 Current Address Register */
873#define DMA21_IRQ_STATUS 0xffc01e68 /* DMA Channel 21 Interrupt/Status Register */
874#define DMA21_PERIPHERAL_MAP 0xffc01e6c /* DMA Channel 21 Peripheral Map Register */
875#define DMA21_CURR_X_COUNT 0xffc01e70 /* DMA Channel 21 Current X Count Register */
876#define DMA21_CURR_Y_COUNT 0xffc01e78 /* DMA Channel 21 Current Y Count Register */
877
878/* DMA Channel 22 Registers */
879
880#define DMA22_NEXT_DESC_PTR 0xffc01e80 /* DMA Channel 22 Next Descriptor Pointer Register */
881#define DMA22_START_ADDR 0xffc01e84 /* DMA Channel 22 Start Address Register */
882#define DMA22_CONFIG 0xffc01e88 /* DMA Channel 22 Configuration Register */
883#define DMA22_X_COUNT 0xffc01e90 /* DMA Channel 22 X Count Register */
884#define DMA22_X_MODIFY 0xffc01e94 /* DMA Channel 22 X Modify Register */
885#define DMA22_Y_COUNT 0xffc01e98 /* DMA Channel 22 Y Count Register */
886#define DMA22_Y_MODIFY 0xffc01e9c /* DMA Channel 22 Y Modify Register */
887#define DMA22_CURR_DESC_PTR 0xffc01ea0 /* DMA Channel 22 Current Descriptor Pointer Register */
888#define DMA22_CURR_ADDR 0xffc01ea4 /* DMA Channel 22 Current Address Register */
889#define DMA22_IRQ_STATUS 0xffc01ea8 /* DMA Channel 22 Interrupt/Status Register */
890#define DMA22_PERIPHERAL_MAP 0xffc01eac /* DMA Channel 22 Peripheral Map Register */
891#define DMA22_CURR_X_COUNT 0xffc01eb0 /* DMA Channel 22 Current X Count Register */
892#define DMA22_CURR_Y_COUNT 0xffc01eb8 /* DMA Channel 22 Current Y Count Register */
893
894/* DMA Channel 23 Registers */
895
896#define DMA23_NEXT_DESC_PTR 0xffc01ec0 /* DMA Channel 23 Next Descriptor Pointer Register */
897#define DMA23_START_ADDR 0xffc01ec4 /* DMA Channel 23 Start Address Register */
898#define DMA23_CONFIG 0xffc01ec8 /* DMA Channel 23 Configuration Register */
899#define DMA23_X_COUNT 0xffc01ed0 /* DMA Channel 23 X Count Register */
900#define DMA23_X_MODIFY 0xffc01ed4 /* DMA Channel 23 X Modify Register */
901#define DMA23_Y_COUNT 0xffc01ed8 /* DMA Channel 23 Y Count Register */
902#define DMA23_Y_MODIFY 0xffc01edc /* DMA Channel 23 Y Modify Register */
903#define DMA23_CURR_DESC_PTR 0xffc01ee0 /* DMA Channel 23 Current Descriptor Pointer Register */
904#define DMA23_CURR_ADDR 0xffc01ee4 /* DMA Channel 23 Current Address Register */
905#define DMA23_IRQ_STATUS 0xffc01ee8 /* DMA Channel 23 Interrupt/Status Register */
906#define DMA23_PERIPHERAL_MAP 0xffc01eec /* DMA Channel 23 Peripheral Map Register */
907#define DMA23_CURR_X_COUNT 0xffc01ef0 /* DMA Channel 23 Current X Count Register */
908#define DMA23_CURR_Y_COUNT 0xffc01ef8 /* DMA Channel 23 Current Y Count Register */
909
910/* MDMA Stream 2 Registers */
911
912#define MDMA_D2_NEXT_DESC_PTR 0xffc01f00 /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
913#define MDMA_D2_START_ADDR 0xffc01f04 /* Memory DMA Stream 2 Destination Start Address Register */
914#define MDMA_D2_CONFIG 0xffc01f08 /* Memory DMA Stream 2 Destination Configuration Register */
915#define MDMA_D2_X_COUNT 0xffc01f10 /* Memory DMA Stream 2 Destination X Count Register */
916#define MDMA_D2_X_MODIFY 0xffc01f14 /* Memory DMA Stream 2 Destination X Modify Register */
917#define MDMA_D2_Y_COUNT 0xffc01f18 /* Memory DMA Stream 2 Destination Y Count Register */
918#define MDMA_D2_Y_MODIFY 0xffc01f1c /* Memory DMA Stream 2 Destination Y Modify Register */
919#define MDMA_D2_CURR_DESC_PTR 0xffc01f20 /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
920#define MDMA_D2_CURR_ADDR 0xffc01f24 /* Memory DMA Stream 2 Destination Current Address Register */
921#define MDMA_D2_IRQ_STATUS 0xffc01f28 /* Memory DMA Stream 2 Destination Interrupt/Status Register */
922#define MDMA_D2_PERIPHERAL_MAP 0xffc01f2c /* Memory DMA Stream 2 Destination Peripheral Map Register */
923#define MDMA_D2_CURR_X_COUNT 0xffc01f30 /* Memory DMA Stream 2 Destination Current X Count Register */
924#define MDMA_D2_CURR_Y_COUNT 0xffc01f38 /* Memory DMA Stream 2 Destination Current Y Count Register */
925#define MDMA_S2_NEXT_DESC_PTR 0xffc01f40 /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
926#define MDMA_S2_START_ADDR 0xffc01f44 /* Memory DMA Stream 2 Source Start Address Register */
927#define MDMA_S2_CONFIG 0xffc01f48 /* Memory DMA Stream 2 Source Configuration Register */
928#define MDMA_S2_X_COUNT 0xffc01f50 /* Memory DMA Stream 2 Source X Count Register */
929#define MDMA_S2_X_MODIFY 0xffc01f54 /* Memory DMA Stream 2 Source X Modify Register */
930#define MDMA_S2_Y_COUNT 0xffc01f58 /* Memory DMA Stream 2 Source Y Count Register */
931#define MDMA_S2_Y_MODIFY 0xffc01f5c /* Memory DMA Stream 2 Source Y Modify Register */
932#define MDMA_S2_CURR_DESC_PTR 0xffc01f60 /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
933#define MDMA_S2_CURR_ADDR 0xffc01f64 /* Memory DMA Stream 2 Source Current Address Register */
934#define MDMA_S2_IRQ_STATUS 0xffc01f68 /* Memory DMA Stream 2 Source Interrupt/Status Register */
935#define MDMA_S2_PERIPHERAL_MAP 0xffc01f6c /* Memory DMA Stream 2 Source Peripheral Map Register */
936#define MDMA_S2_CURR_X_COUNT 0xffc01f70 /* Memory DMA Stream 2 Source Current X Count Register */
937#define MDMA_S2_CURR_Y_COUNT 0xffc01f78 /* Memory DMA Stream 2 Source Current Y Count Register */
938
939/* MDMA Stream 3 Registers */
940
941#define MDMA_D3_NEXT_DESC_PTR 0xffc01f80 /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
942#define MDMA_D3_START_ADDR 0xffc01f84 /* Memory DMA Stream 3 Destination Start Address Register */
943#define MDMA_D3_CONFIG 0xffc01f88 /* Memory DMA Stream 3 Destination Configuration Register */
944#define MDMA_D3_X_COUNT 0xffc01f90 /* Memory DMA Stream 3 Destination X Count Register */
945#define MDMA_D3_X_MODIFY 0xffc01f94 /* Memory DMA Stream 3 Destination X Modify Register */
946#define MDMA_D3_Y_COUNT 0xffc01f98 /* Memory DMA Stream 3 Destination Y Count Register */
947#define MDMA_D3_Y_MODIFY 0xffc01f9c /* Memory DMA Stream 3 Destination Y Modify Register */
948#define MDMA_D3_CURR_DESC_PTR 0xffc01fa0 /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
949#define MDMA_D3_CURR_ADDR 0xffc01fa4 /* Memory DMA Stream 3 Destination Current Address Register */
950#define MDMA_D3_IRQ_STATUS 0xffc01fa8 /* Memory DMA Stream 3 Destination Interrupt/Status Register */
951#define MDMA_D3_PERIPHERAL_MAP 0xffc01fac /* Memory DMA Stream 3 Destination Peripheral Map Register */
952#define MDMA_D3_CURR_X_COUNT 0xffc01fb0 /* Memory DMA Stream 3 Destination Current X Count Register */
953#define MDMA_D3_CURR_Y_COUNT 0xffc01fb8 /* Memory DMA Stream 3 Destination Current Y Count Register */
954#define MDMA_S3_NEXT_DESC_PTR 0xffc01fc0 /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
955#define MDMA_S3_START_ADDR 0xffc01fc4 /* Memory DMA Stream 3 Source Start Address Register */
956#define MDMA_S3_CONFIG 0xffc01fc8 /* Memory DMA Stream 3 Source Configuration Register */
957#define MDMA_S3_X_COUNT 0xffc01fd0 /* Memory DMA Stream 3 Source X Count Register */
958#define MDMA_S3_X_MODIFY 0xffc01fd4 /* Memory DMA Stream 3 Source X Modify Register */
959#define MDMA_S3_Y_COUNT 0xffc01fd8 /* Memory DMA Stream 3 Source Y Count Register */
960#define MDMA_S3_Y_MODIFY 0xffc01fdc /* Memory DMA Stream 3 Source Y Modify Register */
961#define MDMA_S3_CURR_DESC_PTR 0xffc01fe0 /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
962#define MDMA_S3_CURR_ADDR 0xffc01fe4 /* Memory DMA Stream 3 Source Current Address Register */
963#define MDMA_S3_IRQ_STATUS 0xffc01fe8 /* Memory DMA Stream 3 Source Interrupt/Status Register */
964#define MDMA_S3_PERIPHERAL_MAP 0xffc01fec /* Memory DMA Stream 3 Source Peripheral Map Register */
965#define MDMA_S3_CURR_X_COUNT 0xffc01ff0 /* Memory DMA Stream 3 Source Current X Count Register */
966#define MDMA_S3_CURR_Y_COUNT 0xffc01ff8 /* Memory DMA Stream 3 Source Current Y Count Register */
967
968/* UART1 Registers */
969
970#define UART1_DLL 0xffc02000 /* Divisor Latch Low Byte */
971#define UART1_DLH 0xffc02004 /* Divisor Latch High Byte */
972#define UART1_GCTL 0xffc02008 /* Global Control Register */
973#define UART1_LCR 0xffc0200c /* Line Control Register */
974#define UART1_MCR 0xffc02010 /* Modem Control Register */
975#define UART1_LSR 0xffc02014 /* Line Status Register */
976#define UART1_MSR 0xffc02018 /* Modem Status Register */
977#define UART1_SCR 0xffc0201c /* Scratch Register */
978#define UART1_IER_SET 0xffc02020 /* Interrupt Enable Register Set */
979#define UART1_IER_CLEAR 0xffc02024 /* Interrupt Enable Register Clear */
980#define UART1_THR 0xffc02028 /* Transmit Hold Register */
981#define UART1_RBR 0xffc0202c /* Receive Buffer Register */
982
983/* UART2 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 processors */
984
985/* SPI1 Registers */
986
987#define SPI1_REGBASE 0xffc02300
988#define SPI1_CTL 0xffc02300 /* SPI1 Control Register */
989#define SPI1_FLG 0xffc02304 /* SPI1 Flag Register */
990#define SPI1_STAT 0xffc02308 /* SPI1 Status Register */
991#define SPI1_TDBR 0xffc0230c /* SPI1 Transmit Data Buffer Register */
992#define SPI1_RDBR 0xffc02310 /* SPI1 Receive Data Buffer Register */
993#define SPI1_BAUD 0xffc02314 /* SPI1 Baud Rate Register */
994#define SPI1_SHADOW 0xffc02318 /* SPI1 Receive Data Buffer Shadow Register */
995
996/* SPORT2 Registers */
997
998#define SPORT2_TCR1 0xffc02500 /* SPORT2 Transmit Configuration 1 Register */
999#define SPORT2_TCR2 0xffc02504 /* SPORT2 Transmit Configuration 2 Register */
1000#define SPORT2_TCLKDIV 0xffc02508 /* SPORT2 Transmit Serial Clock Divider Register */
1001#define SPORT2_TFSDIV 0xffc0250c /* SPORT2 Transmit Frame Sync Divider Register */
1002#define SPORT2_TX 0xffc02510 /* SPORT2 Transmit Data Register */
1003#define SPORT2_RX 0xffc02518 /* SPORT2 Receive Data Register */
1004#define SPORT2_RCR1 0xffc02520 /* SPORT2 Receive Configuration 1 Register */
1005#define SPORT2_RCR2 0xffc02524 /* SPORT2 Receive Configuration 2 Register */
1006#define SPORT2_RCLKDIV 0xffc02528 /* SPORT2 Receive Serial Clock Divider Register */
1007#define SPORT2_RFSDIV 0xffc0252c /* SPORT2 Receive Frame Sync Divider Register */
1008#define SPORT2_STAT 0xffc02530 /* SPORT2 Status Register */
1009#define SPORT2_CHNL 0xffc02534 /* SPORT2 Current Channel Register */
1010#define SPORT2_MCMC1 0xffc02538 /* SPORT2 Multi channel Configuration Register 1 */
1011#define SPORT2_MCMC2 0xffc0253c /* SPORT2 Multi channel Configuration Register 2 */
1012#define SPORT2_MTCS0 0xffc02540 /* SPORT2 Multi channel Transmit Select Register 0 */
1013#define SPORT2_MTCS1 0xffc02544 /* SPORT2 Multi channel Transmit Select Register 1 */
1014#define SPORT2_MTCS2 0xffc02548 /* SPORT2 Multi channel Transmit Select Register 2 */
1015#define SPORT2_MTCS3 0xffc0254c /* SPORT2 Multi channel Transmit Select Register 3 */
1016#define SPORT2_MRCS0 0xffc02550 /* SPORT2 Multi channel Receive Select Register 0 */
1017#define SPORT2_MRCS1 0xffc02554 /* SPORT2 Multi channel Receive Select Register 1 */
1018#define SPORT2_MRCS2 0xffc02558 /* SPORT2 Multi channel Receive Select Register 2 */
1019#define SPORT2_MRCS3 0xffc0255c /* SPORT2 Multi channel Receive Select Register 3 */
1020
1021/* SPORT3 Registers */
1022
1023#define SPORT3_TCR1 0xffc02600 /* SPORT3 Transmit Configuration 1 Register */
1024#define SPORT3_TCR2 0xffc02604 /* SPORT3 Transmit Configuration 2 Register */
1025#define SPORT3_TCLKDIV 0xffc02608 /* SPORT3 Transmit Serial Clock Divider Register */
1026#define SPORT3_TFSDIV 0xffc0260c /* SPORT3 Transmit Frame Sync Divider Register */
1027#define SPORT3_TX 0xffc02610 /* SPORT3 Transmit Data Register */
1028#define SPORT3_RX 0xffc02618 /* SPORT3 Receive Data Register */
1029#define SPORT3_RCR1 0xffc02620 /* SPORT3 Receive Configuration 1 Register */
1030#define SPORT3_RCR2 0xffc02624 /* SPORT3 Receive Configuration 2 Register */
1031#define SPORT3_RCLKDIV 0xffc02628 /* SPORT3 Receive Serial Clock Divider Register */
1032#define SPORT3_RFSDIV 0xffc0262c /* SPORT3 Receive Frame Sync Divider Register */
1033#define SPORT3_STAT 0xffc02630 /* SPORT3 Status Register */
1034#define SPORT3_CHNL 0xffc02634 /* SPORT3 Current Channel Register */
1035#define SPORT3_MCMC1 0xffc02638 /* SPORT3 Multi channel Configuration Register 1 */
1036#define SPORT3_MCMC2 0xffc0263c /* SPORT3 Multi channel Configuration Register 2 */
1037#define SPORT3_MTCS0 0xffc02640 /* SPORT3 Multi channel Transmit Select Register 0 */
1038#define SPORT3_MTCS1 0xffc02644 /* SPORT3 Multi channel Transmit Select Register 1 */
1039#define SPORT3_MTCS2 0xffc02648 /* SPORT3 Multi channel Transmit Select Register 2 */
1040#define SPORT3_MTCS3 0xffc0264c /* SPORT3 Multi channel Transmit Select Register 3 */
1041#define SPORT3_MRCS0 0xffc02650 /* SPORT3 Multi channel Receive Select Register 0 */
1042#define SPORT3_MRCS1 0xffc02654 /* SPORT3 Multi channel Receive Select Register 1 */
1043#define SPORT3_MRCS2 0xffc02658 /* SPORT3 Multi channel Receive Select Register 2 */
1044#define SPORT3_MRCS3 0xffc0265c /* SPORT3 Multi channel Receive Select Register 3 */
1045
1046/* EPPI2 Registers */
1047
1048#define EPPI2_STATUS 0xffc02900 /* EPPI2 Status Register */
1049#define EPPI2_HCOUNT 0xffc02904 /* EPPI2 Horizontal Transfer Count Register */
1050#define EPPI2_HDELAY 0xffc02908 /* EPPI2 Horizontal Delay Count Register */
1051#define EPPI2_VCOUNT 0xffc0290c /* EPPI2 Vertical Transfer Count Register */
1052#define EPPI2_VDELAY 0xffc02910 /* EPPI2 Vertical Delay Count Register */
1053#define EPPI2_FRAME 0xffc02914 /* EPPI2 Lines per Frame Register */
1054#define EPPI2_LINE 0xffc02918 /* EPPI2 Samples per Line Register */
1055#define EPPI2_CLKDIV 0xffc0291c /* EPPI2 Clock Divide Register */
1056#define EPPI2_CONTROL 0xffc02920 /* EPPI2 Control Register */
1057#define EPPI2_FS1W_HBL 0xffc02924 /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
1058#define EPPI2_FS1P_AVPL 0xffc02928 /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
1059#define EPPI2_FS2W_LVB 0xffc0292c /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
1060#define EPPI2_FS2P_LAVF 0xffc02930 /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
1061#define EPPI2_CLIP 0xffc02934 /* EPPI2 Clipping Register */
1062
1063/* CAN Controller 0 Config 1 Registers */
1064
1065#define CAN0_MC1 0xffc02a00 /* CAN Controller 0 Mailbox Configuration Register 1 */
1066#define CAN0_MD1 0xffc02a04 /* CAN Controller 0 Mailbox Direction Register 1 */
1067#define CAN0_TRS1 0xffc02a08 /* CAN Controller 0 Transmit Request Set Register 1 */
1068#define CAN0_TRR1 0xffc02a0c /* CAN Controller 0 Transmit Request Reset Register 1 */
1069#define CAN0_TA1 0xffc02a10 /* CAN Controller 0 Transmit Acknowledge Register 1 */
1070#define CAN0_AA1 0xffc02a14 /* CAN Controller 0 Abort Acknowledge Register 1 */
1071#define CAN0_RMP1 0xffc02a18 /* CAN Controller 0 Receive Message Pending Register 1 */
1072#define CAN0_RML1 0xffc02a1c /* CAN Controller 0 Receive Message Lost Register 1 */
1073#define CAN0_MBTIF1 0xffc02a20 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */
1074#define CAN0_MBRIF1 0xffc02a24 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */
1075#define CAN0_MBIM1 0xffc02a28 /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */
1076#define CAN0_RFH1 0xffc02a2c /* CAN Controller 0 Remote Frame Handling Enable Register 1 */
1077#define CAN0_OPSS1 0xffc02a30 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */
1078
1079/* CAN Controller 0 Config 2 Registers */
1080
1081#define CAN0_MC2 0xffc02a40 /* CAN Controller 0 Mailbox Configuration Register 2 */
1082#define CAN0_MD2 0xffc02a44 /* CAN Controller 0 Mailbox Direction Register 2 */
1083#define CAN0_TRS2 0xffc02a48 /* CAN Controller 0 Transmit Request Set Register 2 */
1084#define CAN0_TRR2 0xffc02a4c /* CAN Controller 0 Transmit Request Reset Register 2 */
1085#define CAN0_TA2 0xffc02a50 /* CAN Controller 0 Transmit Acknowledge Register 2 */
1086#define CAN0_AA2 0xffc02a54 /* CAN Controller 0 Abort Acknowledge Register 2 */
1087#define CAN0_RMP2 0xffc02a58 /* CAN Controller 0 Receive Message Pending Register 2 */
1088#define CAN0_RML2 0xffc02a5c /* CAN Controller 0 Receive Message Lost Register 2 */
1089#define CAN0_MBTIF2 0xffc02a60 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */
1090#define CAN0_MBRIF2 0xffc02a64 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */
1091#define CAN0_MBIM2 0xffc02a68 /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */
1092#define CAN0_RFH2 0xffc02a6c /* CAN Controller 0 Remote Frame Handling Enable Register 2 */
1093#define CAN0_OPSS2 0xffc02a70 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */
1094
1095/* CAN Controller 0 Clock/Interrupt/Counter Registers */
1096
1097#define CAN0_CLOCK 0xffc02a80 /* CAN Controller 0 Clock Register */
1098#define CAN0_TIMING 0xffc02a84 /* CAN Controller 0 Timing Register */
1099#define CAN0_DEBUG 0xffc02a88 /* CAN Controller 0 Debug Register */
1100#define CAN0_STATUS 0xffc02a8c /* CAN Controller 0 Global Status Register */
1101#define CAN0_CEC 0xffc02a90 /* CAN Controller 0 Error Counter Register */
1102#define CAN0_GIS 0xffc02a94 /* CAN Controller 0 Global Interrupt Status Register */
1103#define CAN0_GIM 0xffc02a98 /* CAN Controller 0 Global Interrupt Mask Register */
1104#define CAN0_GIF 0xffc02a9c /* CAN Controller 0 Global Interrupt Flag Register */
1105#define CAN0_CONTROL 0xffc02aa0 /* CAN Controller 0 Master Control Register */
1106#define CAN0_INTR 0xffc02aa4 /* CAN Controller 0 Interrupt Pending Register */
1107#define CAN0_MBTD 0xffc02aac /* CAN Controller 0 Mailbox Temporary Disable Register */
1108#define CAN0_EWR 0xffc02ab0 /* CAN Controller 0 Programmable Warning Level Register */
1109#define CAN0_ESR 0xffc02ab4 /* CAN Controller 0 Error Status Register */
1110#define CAN0_UCCNT 0xffc02ac4 /* CAN Controller 0 Universal Counter Register */
1111#define CAN0_UCRC 0xffc02ac8 /* CAN Controller 0 Universal Counter Force Reload Register */
1112#define CAN0_UCCNF 0xffc02acc /* CAN Controller 0 Universal Counter Configuration Register */
1113
1114/* CAN Controller 0 Acceptance Registers */
1115
1116#define CAN0_AM00L 0xffc02b00 /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */
1117#define CAN0_AM00H 0xffc02b04 /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */
1118#define CAN0_AM01L 0xffc02b08 /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */
1119#define CAN0_AM01H 0xffc02b0c /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */
1120#define CAN0_AM02L 0xffc02b10 /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */
1121#define CAN0_AM02H 0xffc02b14 /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */
1122#define CAN0_AM03L 0xffc02b18 /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */
1123#define CAN0_AM03H 0xffc02b1c /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */
1124#define CAN0_AM04L 0xffc02b20 /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */
1125#define CAN0_AM04H 0xffc02b24 /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */
1126#define CAN0_AM05L 0xffc02b28 /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */
1127#define CAN0_AM05H 0xffc02b2c /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */
1128#define CAN0_AM06L 0xffc02b30 /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */
1129#define CAN0_AM06H 0xffc02b34 /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */
1130#define CAN0_AM07L 0xffc02b38 /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */
1131#define CAN0_AM07H 0xffc02b3c /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */
1132#define CAN0_AM08L 0xffc02b40 /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */
1133#define CAN0_AM08H 0xffc02b44 /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */
1134#define CAN0_AM09L 0xffc02b48 /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */
1135#define CAN0_AM09H 0xffc02b4c /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */
1136#define CAN0_AM10L 0xffc02b50 /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */
1137#define CAN0_AM10H 0xffc02b54 /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */
1138#define CAN0_AM11L 0xffc02b58 /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */
1139#define CAN0_AM11H 0xffc02b5c /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */
1140#define CAN0_AM12L 0xffc02b60 /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */
1141#define CAN0_AM12H 0xffc02b64 /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */
1142#define CAN0_AM13L 0xffc02b68 /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */
1143#define CAN0_AM13H 0xffc02b6c /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */
1144#define CAN0_AM14L 0xffc02b70 /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */
1145#define CAN0_AM14H 0xffc02b74 /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */
1146#define CAN0_AM15L 0xffc02b78 /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */
1147#define CAN0_AM15H 0xffc02b7c /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */
1148
1149/* CAN Controller 0 Acceptance Registers */
1150
1151#define CAN0_AM16L 0xffc02b80 /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */
1152#define CAN0_AM16H 0xffc02b84 /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */
1153#define CAN0_AM17L 0xffc02b88 /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */
1154#define CAN0_AM17H 0xffc02b8c /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */
1155#define CAN0_AM18L 0xffc02b90 /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */
1156#define CAN0_AM18H 0xffc02b94 /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */
1157#define CAN0_AM19L 0xffc02b98 /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */
1158#define CAN0_AM19H 0xffc02b9c /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */
1159#define CAN0_AM20L 0xffc02ba0 /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */
1160#define CAN0_AM20H 0xffc02ba4 /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */
1161#define CAN0_AM21L 0xffc02ba8 /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */
1162#define CAN0_AM21H 0xffc02bac /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */
1163#define CAN0_AM22L 0xffc02bb0 /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */
1164#define CAN0_AM22H 0xffc02bb4 /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */
1165#define CAN0_AM23L 0xffc02bb8 /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */
1166#define CAN0_AM23H 0xffc02bbc /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */
1167#define CAN0_AM24L 0xffc02bc0 /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */
1168#define CAN0_AM24H 0xffc02bc4 /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */
1169#define CAN0_AM25L 0xffc02bc8 /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */
1170#define CAN0_AM25H 0xffc02bcc /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */
1171#define CAN0_AM26L 0xffc02bd0 /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */
1172#define CAN0_AM26H 0xffc02bd4 /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */
1173#define CAN0_AM27L 0xffc02bd8 /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */
1174#define CAN0_AM27H 0xffc02bdc /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */
1175#define CAN0_AM28L 0xffc02be0 /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */
1176#define CAN0_AM28H 0xffc02be4 /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */
1177#define CAN0_AM29L 0xffc02be8 /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */
1178#define CAN0_AM29H 0xffc02bec /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */
1179#define CAN0_AM30L 0xffc02bf0 /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */
1180#define CAN0_AM30H 0xffc02bf4 /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */
1181#define CAN0_AM31L 0xffc02bf8 /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */
1182#define CAN0_AM31H 0xffc02bfc /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */
1183
1184/* CAN Controller 0 Mailbox Data Registers */
1185
1186#define CAN0_MB00_DATA0 0xffc02c00 /* CAN Controller 0 Mailbox 0 Data 0 Register */
1187#define CAN0_MB00_DATA1 0xffc02c04 /* CAN Controller 0 Mailbox 0 Data 1 Register */
1188#define CAN0_MB00_DATA2 0xffc02c08 /* CAN Controller 0 Mailbox 0 Data 2 Register */
1189#define CAN0_MB00_DATA3 0xffc02c0c /* CAN Controller 0 Mailbox 0 Data 3 Register */
1190#define CAN0_MB00_LENGTH 0xffc02c10 /* CAN Controller 0 Mailbox 0 Length Register */
1191#define CAN0_MB00_TIMESTAMP 0xffc02c14 /* CAN Controller 0 Mailbox 0 Timestamp Register */
1192#define CAN0_MB00_ID0 0xffc02c18 /* CAN Controller 0 Mailbox 0 ID0 Register */
1193#define CAN0_MB00_ID1 0xffc02c1c /* CAN Controller 0 Mailbox 0 ID1 Register */
1194#define CAN0_MB01_DATA0 0xffc02c20 /* CAN Controller 0 Mailbox 1 Data 0 Register */
1195#define CAN0_MB01_DATA1 0xffc02c24 /* CAN Controller 0 Mailbox 1 Data 1 Register */
1196#define CAN0_MB01_DATA2 0xffc02c28 /* CAN Controller 0 Mailbox 1 Data 2 Register */
1197#define CAN0_MB01_DATA3 0xffc02c2c /* CAN Controller 0 Mailbox 1 Data 3 Register */
1198#define CAN0_MB01_LENGTH 0xffc02c30 /* CAN Controller 0 Mailbox 1 Length Register */
1199#define CAN0_MB01_TIMESTAMP 0xffc02c34 /* CAN Controller 0 Mailbox 1 Timestamp Register */
1200#define CAN0_MB01_ID0 0xffc02c38 /* CAN Controller 0 Mailbox 1 ID0 Register */
1201#define CAN0_MB01_ID1 0xffc02c3c /* CAN Controller 0 Mailbox 1 ID1 Register */
1202#define CAN0_MB02_DATA0 0xffc02c40 /* CAN Controller 0 Mailbox 2 Data 0 Register */
1203#define CAN0_MB02_DATA1 0xffc02c44 /* CAN Controller 0 Mailbox 2 Data 1 Register */
1204#define CAN0_MB02_DATA2 0xffc02c48 /* CAN Controller 0 Mailbox 2 Data 2 Register */
1205#define CAN0_MB02_DATA3 0xffc02c4c /* CAN Controller 0 Mailbox 2 Data 3 Register */
1206#define CAN0_MB02_LENGTH 0xffc02c50 /* CAN Controller 0 Mailbox 2 Length Register */
1207#define CAN0_MB02_TIMESTAMP 0xffc02c54 /* CAN Controller 0 Mailbox 2 Timestamp Register */
1208#define CAN0_MB02_ID0 0xffc02c58 /* CAN Controller 0 Mailbox 2 ID0 Register */
1209#define CAN0_MB02_ID1 0xffc02c5c /* CAN Controller 0 Mailbox 2 ID1 Register */
1210#define CAN0_MB03_DATA0 0xffc02c60 /* CAN Controller 0 Mailbox 3 Data 0 Register */
1211#define CAN0_MB03_DATA1 0xffc02c64 /* CAN Controller 0 Mailbox 3 Data 1 Register */
1212#define CAN0_MB03_DATA2 0xffc02c68 /* CAN Controller 0 Mailbox 3 Data 2 Register */
1213#define CAN0_MB03_DATA3 0xffc02c6c /* CAN Controller 0 Mailbox 3 Data 3 Register */
1214#define CAN0_MB03_LENGTH 0xffc02c70 /* CAN Controller 0 Mailbox 3 Length Register */
1215#define CAN0_MB03_TIMESTAMP 0xffc02c74 /* CAN Controller 0 Mailbox 3 Timestamp Register */
1216#define CAN0_MB03_ID0 0xffc02c78 /* CAN Controller 0 Mailbox 3 ID0 Register */
1217#define CAN0_MB03_ID1 0xffc02c7c /* CAN Controller 0 Mailbox 3 ID1 Register */
1218#define CAN0_MB04_DATA0 0xffc02c80 /* CAN Controller 0 Mailbox 4 Data 0 Register */
1219#define CAN0_MB04_DATA1 0xffc02c84 /* CAN Controller 0 Mailbox 4 Data 1 Register */
1220#define CAN0_MB04_DATA2 0xffc02c88 /* CAN Controller 0 Mailbox 4 Data 2 Register */
1221#define CAN0_MB04_DATA3 0xffc02c8c /* CAN Controller 0 Mailbox 4 Data 3 Register */
1222#define CAN0_MB04_LENGTH 0xffc02c90 /* CAN Controller 0 Mailbox 4 Length Register */
1223#define CAN0_MB04_TIMESTAMP 0xffc02c94 /* CAN Controller 0 Mailbox 4 Timestamp Register */
1224#define CAN0_MB04_ID0 0xffc02c98 /* CAN Controller 0 Mailbox 4 ID0 Register */
1225#define CAN0_MB04_ID1 0xffc02c9c /* CAN Controller 0 Mailbox 4 ID1 Register */
1226#define CAN0_MB05_DATA0 0xffc02ca0 /* CAN Controller 0 Mailbox 5 Data 0 Register */
1227#define CAN0_MB05_DATA1 0xffc02ca4 /* CAN Controller 0 Mailbox 5 Data 1 Register */
1228#define CAN0_MB05_DATA2 0xffc02ca8 /* CAN Controller 0 Mailbox 5 Data 2 Register */
1229#define CAN0_MB05_DATA3 0xffc02cac /* CAN Controller 0 Mailbox 5 Data 3 Register */
1230#define CAN0_MB05_LENGTH 0xffc02cb0 /* CAN Controller 0 Mailbox 5 Length Register */
1231#define CAN0_MB05_TIMESTAMP 0xffc02cb4 /* CAN Controller 0 Mailbox 5 Timestamp Register */
1232#define CAN0_MB05_ID0 0xffc02cb8 /* CAN Controller 0 Mailbox 5 ID0 Register */
1233#define CAN0_MB05_ID1 0xffc02cbc /* CAN Controller 0 Mailbox 5 ID1 Register */
1234#define CAN0_MB06_DATA0 0xffc02cc0 /* CAN Controller 0 Mailbox 6 Data 0 Register */
1235#define CAN0_MB06_DATA1 0xffc02cc4 /* CAN Controller 0 Mailbox 6 Data 1 Register */
1236#define CAN0_MB06_DATA2 0xffc02cc8 /* CAN Controller 0 Mailbox 6 Data 2 Register */
1237#define CAN0_MB06_DATA3 0xffc02ccc /* CAN Controller 0 Mailbox 6 Data 3 Register */
1238#define CAN0_MB06_LENGTH 0xffc02cd0 /* CAN Controller 0 Mailbox 6 Length Register */
1239#define CAN0_MB06_TIMESTAMP 0xffc02cd4 /* CAN Controller 0 Mailbox 6 Timestamp Register */
1240#define CAN0_MB06_ID0 0xffc02cd8 /* CAN Controller 0 Mailbox 6 ID0 Register */
1241#define CAN0_MB06_ID1 0xffc02cdc /* CAN Controller 0 Mailbox 6 ID1 Register */
1242#define CAN0_MB07_DATA0 0xffc02ce0 /* CAN Controller 0 Mailbox 7 Data 0 Register */
1243#define CAN0_MB07_DATA1 0xffc02ce4 /* CAN Controller 0 Mailbox 7 Data 1 Register */
1244#define CAN0_MB07_DATA2 0xffc02ce8 /* CAN Controller 0 Mailbox 7 Data 2 Register */
1245#define CAN0_MB07_DATA3 0xffc02cec /* CAN Controller 0 Mailbox 7 Data 3 Register */
1246#define CAN0_MB07_LENGTH 0xffc02cf0 /* CAN Controller 0 Mailbox 7 Length Register */
1247#define CAN0_MB07_TIMESTAMP 0xffc02cf4 /* CAN Controller 0 Mailbox 7 Timestamp Register */
1248#define CAN0_MB07_ID0 0xffc02cf8 /* CAN Controller 0 Mailbox 7 ID0 Register */
1249#define CAN0_MB07_ID1 0xffc02cfc /* CAN Controller 0 Mailbox 7 ID1 Register */
1250#define CAN0_MB08_DATA0 0xffc02d00 /* CAN Controller 0 Mailbox 8 Data 0 Register */
1251#define CAN0_MB08_DATA1 0xffc02d04 /* CAN Controller 0 Mailbox 8 Data 1 Register */
1252#define CAN0_MB08_DATA2 0xffc02d08 /* CAN Controller 0 Mailbox 8 Data 2 Register */
1253#define CAN0_MB08_DATA3 0xffc02d0c /* CAN Controller 0 Mailbox 8 Data 3 Register */
1254#define CAN0_MB08_LENGTH 0xffc02d10 /* CAN Controller 0 Mailbox 8 Length Register */
1255#define CAN0_MB08_TIMESTAMP 0xffc02d14 /* CAN Controller 0 Mailbox 8 Timestamp Register */
1256#define CAN0_MB08_ID0 0xffc02d18 /* CAN Controller 0 Mailbox 8 ID0 Register */
1257#define CAN0_MB08_ID1 0xffc02d1c /* CAN Controller 0 Mailbox 8 ID1 Register */
1258#define CAN0_MB09_DATA0 0xffc02d20 /* CAN Controller 0 Mailbox 9 Data 0 Register */
1259#define CAN0_MB09_DATA1 0xffc02d24 /* CAN Controller 0 Mailbox 9 Data 1 Register */
1260#define CAN0_MB09_DATA2 0xffc02d28 /* CAN Controller 0 Mailbox 9 Data 2 Register */
1261#define CAN0_MB09_DATA3 0xffc02d2c /* CAN Controller 0 Mailbox 9 Data 3 Register */
1262#define CAN0_MB09_LENGTH 0xffc02d30 /* CAN Controller 0 Mailbox 9 Length Register */
1263#define CAN0_MB09_TIMESTAMP 0xffc02d34 /* CAN Controller 0 Mailbox 9 Timestamp Register */
1264#define CAN0_MB09_ID0 0xffc02d38 /* CAN Controller 0 Mailbox 9 ID0 Register */
1265#define CAN0_MB09_ID1 0xffc02d3c /* CAN Controller 0 Mailbox 9 ID1 Register */
1266#define CAN0_MB10_DATA0 0xffc02d40 /* CAN Controller 0 Mailbox 10 Data 0 Register */
1267#define CAN0_MB10_DATA1 0xffc02d44 /* CAN Controller 0 Mailbox 10 Data 1 Register */
1268#define CAN0_MB10_DATA2 0xffc02d48 /* CAN Controller 0 Mailbox 10 Data 2 Register */
1269#define CAN0_MB10_DATA3 0xffc02d4c /* CAN Controller 0 Mailbox 10 Data 3 Register */
1270#define CAN0_MB10_LENGTH 0xffc02d50 /* CAN Controller 0 Mailbox 10 Length Register */
1271#define CAN0_MB10_TIMESTAMP 0xffc02d54 /* CAN Controller 0 Mailbox 10 Timestamp Register */
1272#define CAN0_MB10_ID0 0xffc02d58 /* CAN Controller 0 Mailbox 10 ID0 Register */
1273#define CAN0_MB10_ID1 0xffc02d5c /* CAN Controller 0 Mailbox 10 ID1 Register */
1274#define CAN0_MB11_DATA0 0xffc02d60 /* CAN Controller 0 Mailbox 11 Data 0 Register */
1275#define CAN0_MB11_DATA1 0xffc02d64 /* CAN Controller 0 Mailbox 11 Data 1 Register */
1276#define CAN0_MB11_DATA2 0xffc02d68 /* CAN Controller 0 Mailbox 11 Data 2 Register */
1277#define CAN0_MB11_DATA3 0xffc02d6c /* CAN Controller 0 Mailbox 11 Data 3 Register */
1278#define CAN0_MB11_LENGTH 0xffc02d70 /* CAN Controller 0 Mailbox 11 Length Register */
1279#define CAN0_MB11_TIMESTAMP 0xffc02d74 /* CAN Controller 0 Mailbox 11 Timestamp Register */
1280#define CAN0_MB11_ID0 0xffc02d78 /* CAN Controller 0 Mailbox 11 ID0 Register */
1281#define CAN0_MB11_ID1 0xffc02d7c /* CAN Controller 0 Mailbox 11 ID1 Register */
1282#define CAN0_MB12_DATA0 0xffc02d80 /* CAN Controller 0 Mailbox 12 Data 0 Register */
1283#define CAN0_MB12_DATA1 0xffc02d84 /* CAN Controller 0 Mailbox 12 Data 1 Register */
1284#define CAN0_MB12_DATA2 0xffc02d88 /* CAN Controller 0 Mailbox 12 Data 2 Register */
1285#define CAN0_MB12_DATA3 0xffc02d8c /* CAN Controller 0 Mailbox 12 Data 3 Register */
1286#define CAN0_MB12_LENGTH 0xffc02d90 /* CAN Controller 0 Mailbox 12 Length Register */
1287#define CAN0_MB12_TIMESTAMP 0xffc02d94 /* CAN Controller 0 Mailbox 12 Timestamp Register */
1288#define CAN0_MB12_ID0 0xffc02d98 /* CAN Controller 0 Mailbox 12 ID0 Register */
1289#define CAN0_MB12_ID1 0xffc02d9c /* CAN Controller 0 Mailbox 12 ID1 Register */
1290#define CAN0_MB13_DATA0 0xffc02da0 /* CAN Controller 0 Mailbox 13 Data 0 Register */
1291#define CAN0_MB13_DATA1 0xffc02da4 /* CAN Controller 0 Mailbox 13 Data 1 Register */
1292#define CAN0_MB13_DATA2 0xffc02da8 /* CAN Controller 0 Mailbox 13 Data 2 Register */
1293#define CAN0_MB13_DATA3 0xffc02dac /* CAN Controller 0 Mailbox 13 Data 3 Register */
1294#define CAN0_MB13_LENGTH 0xffc02db0 /* CAN Controller 0 Mailbox 13 Length Register */
1295#define CAN0_MB13_TIMESTAMP 0xffc02db4 /* CAN Controller 0 Mailbox 13 Timestamp Register */
1296#define CAN0_MB13_ID0 0xffc02db8 /* CAN Controller 0 Mailbox 13 ID0 Register */
1297#define CAN0_MB13_ID1 0xffc02dbc /* CAN Controller 0 Mailbox 13 ID1 Register */
1298#define CAN0_MB14_DATA0 0xffc02dc0 /* CAN Controller 0 Mailbox 14 Data 0 Register */
1299#define CAN0_MB14_DATA1 0xffc02dc4 /* CAN Controller 0 Mailbox 14 Data 1 Register */
1300#define CAN0_MB14_DATA2 0xffc02dc8 /* CAN Controller 0 Mailbox 14 Data 2 Register */
1301#define CAN0_MB14_DATA3 0xffc02dcc /* CAN Controller 0 Mailbox 14 Data 3 Register */
1302#define CAN0_MB14_LENGTH 0xffc02dd0 /* CAN Controller 0 Mailbox 14 Length Register */
1303#define CAN0_MB14_TIMESTAMP 0xffc02dd4 /* CAN Controller 0 Mailbox 14 Timestamp Register */
1304#define CAN0_MB14_ID0 0xffc02dd8 /* CAN Controller 0 Mailbox 14 ID0 Register */
1305#define CAN0_MB14_ID1 0xffc02ddc /* CAN Controller 0 Mailbox 14 ID1 Register */
1306#define CAN0_MB15_DATA0 0xffc02de0 /* CAN Controller 0 Mailbox 15 Data 0 Register */
1307#define CAN0_MB15_DATA1 0xffc02de4 /* CAN Controller 0 Mailbox 15 Data 1 Register */
1308#define CAN0_MB15_DATA2 0xffc02de8 /* CAN Controller 0 Mailbox 15 Data 2 Register */
1309#define CAN0_MB15_DATA3 0xffc02dec /* CAN Controller 0 Mailbox 15 Data 3 Register */
1310#define CAN0_MB15_LENGTH 0xffc02df0 /* CAN Controller 0 Mailbox 15 Length Register */
1311#define CAN0_MB15_TIMESTAMP 0xffc02df4 /* CAN Controller 0 Mailbox 15 Timestamp Register */
1312#define CAN0_MB15_ID0 0xffc02df8 /* CAN Controller 0 Mailbox 15 ID0 Register */
1313#define CAN0_MB15_ID1 0xffc02dfc /* CAN Controller 0 Mailbox 15 ID1 Register */
1314
1315/* CAN Controller 0 Mailbox Data Registers */
1316
1317#define CAN0_MB16_DATA0 0xffc02e00 /* CAN Controller 0 Mailbox 16 Data 0 Register */
1318#define CAN0_MB16_DATA1 0xffc02e04 /* CAN Controller 0 Mailbox 16 Data 1 Register */
1319#define CAN0_MB16_DATA2 0xffc02e08 /* CAN Controller 0 Mailbox 16 Data 2 Register */
1320#define CAN0_MB16_DATA3 0xffc02e0c /* CAN Controller 0 Mailbox 16 Data 3 Register */
1321#define CAN0_MB16_LENGTH 0xffc02e10 /* CAN Controller 0 Mailbox 16 Length Register */
1322#define CAN0_MB16_TIMESTAMP 0xffc02e14 /* CAN Controller 0 Mailbox 16 Timestamp Register */
1323#define CAN0_MB16_ID0 0xffc02e18 /* CAN Controller 0 Mailbox 16 ID0 Register */
1324#define CAN0_MB16_ID1 0xffc02e1c /* CAN Controller 0 Mailbox 16 ID1 Register */
1325#define CAN0_MB17_DATA0 0xffc02e20 /* CAN Controller 0 Mailbox 17 Data 0 Register */
1326#define CAN0_MB17_DATA1 0xffc02e24 /* CAN Controller 0 Mailbox 17 Data 1 Register */
1327#define CAN0_MB17_DATA2 0xffc02e28 /* CAN Controller 0 Mailbox 17 Data 2 Register */
1328#define CAN0_MB17_DATA3 0xffc02e2c /* CAN Controller 0 Mailbox 17 Data 3 Register */
1329#define CAN0_MB17_LENGTH 0xffc02e30 /* CAN Controller 0 Mailbox 17 Length Register */
1330#define CAN0_MB17_TIMESTAMP 0xffc02e34 /* CAN Controller 0 Mailbox 17 Timestamp Register */
1331#define CAN0_MB17_ID0 0xffc02e38 /* CAN Controller 0 Mailbox 17 ID0 Register */
1332#define CAN0_MB17_ID1 0xffc02e3c /* CAN Controller 0 Mailbox 17 ID1 Register */
1333#define CAN0_MB18_DATA0 0xffc02e40 /* CAN Controller 0 Mailbox 18 Data 0 Register */
1334#define CAN0_MB18_DATA1 0xffc02e44 /* CAN Controller 0 Mailbox 18 Data 1 Register */
1335#define CAN0_MB18_DATA2 0xffc02e48 /* CAN Controller 0 Mailbox 18 Data 2 Register */
1336#define CAN0_MB18_DATA3 0xffc02e4c /* CAN Controller 0 Mailbox 18 Data 3 Register */
1337#define CAN0_MB18_LENGTH 0xffc02e50 /* CAN Controller 0 Mailbox 18 Length Register */
1338#define CAN0_MB18_TIMESTAMP 0xffc02e54 /* CAN Controller 0 Mailbox 18 Timestamp Register */
1339#define CAN0_MB18_ID0 0xffc02e58 /* CAN Controller 0 Mailbox 18 ID0 Register */
1340#define CAN0_MB18_ID1 0xffc02e5c /* CAN Controller 0 Mailbox 18 ID1 Register */
1341#define CAN0_MB19_DATA0 0xffc02e60 /* CAN Controller 0 Mailbox 19 Data 0 Register */
1342#define CAN0_MB19_DATA1 0xffc02e64 /* CAN Controller 0 Mailbox 19 Data 1 Register */
1343#define CAN0_MB19_DATA2 0xffc02e68 /* CAN Controller 0 Mailbox 19 Data 2 Register */
1344#define CAN0_MB19_DATA3 0xffc02e6c /* CAN Controller 0 Mailbox 19 Data 3 Register */
1345#define CAN0_MB19_LENGTH 0xffc02e70 /* CAN Controller 0 Mailbox 19 Length Register */
1346#define CAN0_MB19_TIMESTAMP 0xffc02e74 /* CAN Controller 0 Mailbox 19 Timestamp Register */
1347#define CAN0_MB19_ID0 0xffc02e78 /* CAN Controller 0 Mailbox 19 ID0 Register */
1348#define CAN0_MB19_ID1 0xffc02e7c /* CAN Controller 0 Mailbox 19 ID1 Register */
1349#define CAN0_MB20_DATA0 0xffc02e80 /* CAN Controller 0 Mailbox 20 Data 0 Register */
1350#define CAN0_MB20_DATA1 0xffc02e84 /* CAN Controller 0 Mailbox 20 Data 1 Register */
1351#define CAN0_MB20_DATA2 0xffc02e88 /* CAN Controller 0 Mailbox 20 Data 2 Register */
1352#define CAN0_MB20_DATA3 0xffc02e8c /* CAN Controller 0 Mailbox 20 Data 3 Register */
1353#define CAN0_MB20_LENGTH 0xffc02e90 /* CAN Controller 0 Mailbox 20 Length Register */
1354#define CAN0_MB20_TIMESTAMP 0xffc02e94 /* CAN Controller 0 Mailbox 20 Timestamp Register */
1355#define CAN0_MB20_ID0 0xffc02e98 /* CAN Controller 0 Mailbox 20 ID0 Register */
1356#define CAN0_MB20_ID1 0xffc02e9c /* CAN Controller 0 Mailbox 20 ID1 Register */
1357#define CAN0_MB21_DATA0 0xffc02ea0 /* CAN Controller 0 Mailbox 21 Data 0 Register */
1358#define CAN0_MB21_DATA1 0xffc02ea4 /* CAN Controller 0 Mailbox 21 Data 1 Register */
1359#define CAN0_MB21_DATA2 0xffc02ea8 /* CAN Controller 0 Mailbox 21 Data 2 Register */
1360#define CAN0_MB21_DATA3 0xffc02eac /* CAN Controller 0 Mailbox 21 Data 3 Register */
1361#define CAN0_MB21_LENGTH 0xffc02eb0 /* CAN Controller 0 Mailbox 21 Length Register */
1362#define CAN0_MB21_TIMESTAMP 0xffc02eb4 /* CAN Controller 0 Mailbox 21 Timestamp Register */
1363#define CAN0_MB21_ID0 0xffc02eb8 /* CAN Controller 0 Mailbox 21 ID0 Register */
1364#define CAN0_MB21_ID1 0xffc02ebc /* CAN Controller 0 Mailbox 21 ID1 Register */
1365#define CAN0_MB22_DATA0 0xffc02ec0 /* CAN Controller 0 Mailbox 22 Data 0 Register */
1366#define CAN0_MB22_DATA1 0xffc02ec4 /* CAN Controller 0 Mailbox 22 Data 1 Register */
1367#define CAN0_MB22_DATA2 0xffc02ec8 /* CAN Controller 0 Mailbox 22 Data 2 Register */
1368#define CAN0_MB22_DATA3 0xffc02ecc /* CAN Controller 0 Mailbox 22 Data 3 Register */
1369#define CAN0_MB22_LENGTH 0xffc02ed0 /* CAN Controller 0 Mailbox 22 Length Register */
1370#define CAN0_MB22_TIMESTAMP 0xffc02ed4 /* CAN Controller 0 Mailbox 22 Timestamp Register */
1371#define CAN0_MB22_ID0 0xffc02ed8 /* CAN Controller 0 Mailbox 22 ID0 Register */
1372#define CAN0_MB22_ID1 0xffc02edc /* CAN Controller 0 Mailbox 22 ID1 Register */
1373#define CAN0_MB23_DATA0 0xffc02ee0 /* CAN Controller 0 Mailbox 23 Data 0 Register */
1374#define CAN0_MB23_DATA1 0xffc02ee4 /* CAN Controller 0 Mailbox 23 Data 1 Register */
1375#define CAN0_MB23_DATA2 0xffc02ee8 /* CAN Controller 0 Mailbox 23 Data 2 Register */
1376#define CAN0_MB23_DATA3 0xffc02eec /* CAN Controller 0 Mailbox 23 Data 3 Register */
1377#define CAN0_MB23_LENGTH 0xffc02ef0 /* CAN Controller 0 Mailbox 23 Length Register */
1378#define CAN0_MB23_TIMESTAMP 0xffc02ef4 /* CAN Controller 0 Mailbox 23 Timestamp Register */
1379#define CAN0_MB23_ID0 0xffc02ef8 /* CAN Controller 0 Mailbox 23 ID0 Register */
1380#define CAN0_MB23_ID1 0xffc02efc /* CAN Controller 0 Mailbox 23 ID1 Register */
1381#define CAN0_MB24_DATA0 0xffc02f00 /* CAN Controller 0 Mailbox 24 Data 0 Register */
1382#define CAN0_MB24_DATA1 0xffc02f04 /* CAN Controller 0 Mailbox 24 Data 1 Register */
1383#define CAN0_MB24_DATA2 0xffc02f08 /* CAN Controller 0 Mailbox 24 Data 2 Register */
1384#define CAN0_MB24_DATA3 0xffc02f0c /* CAN Controller 0 Mailbox 24 Data 3 Register */
1385#define CAN0_MB24_LENGTH 0xffc02f10 /* CAN Controller 0 Mailbox 24 Length Register */
1386#define CAN0_MB24_TIMESTAMP 0xffc02f14 /* CAN Controller 0 Mailbox 24 Timestamp Register */
1387#define CAN0_MB24_ID0 0xffc02f18 /* CAN Controller 0 Mailbox 24 ID0 Register */
1388#define CAN0_MB24_ID1 0xffc02f1c /* CAN Controller 0 Mailbox 24 ID1 Register */
1389#define CAN0_MB25_DATA0 0xffc02f20 /* CAN Controller 0 Mailbox 25 Data 0 Register */
1390#define CAN0_MB25_DATA1 0xffc02f24 /* CAN Controller 0 Mailbox 25 Data 1 Register */
1391#define CAN0_MB25_DATA2 0xffc02f28 /* CAN Controller 0 Mailbox 25 Data 2 Register */
1392#define CAN0_MB25_DATA3 0xffc02f2c /* CAN Controller 0 Mailbox 25 Data 3 Register */
1393#define CAN0_MB25_LENGTH 0xffc02f30 /* CAN Controller 0 Mailbox 25 Length Register */
1394#define CAN0_MB25_TIMESTAMP 0xffc02f34 /* CAN Controller 0 Mailbox 25 Timestamp Register */
1395#define CAN0_MB25_ID0 0xffc02f38 /* CAN Controller 0 Mailbox 25 ID0 Register */
1396#define CAN0_MB25_ID1 0xffc02f3c /* CAN Controller 0 Mailbox 25 ID1 Register */
1397#define CAN0_MB26_DATA0 0xffc02f40 /* CAN Controller 0 Mailbox 26 Data 0 Register */
1398#define CAN0_MB26_DATA1 0xffc02f44 /* CAN Controller 0 Mailbox 26 Data 1 Register */
1399#define CAN0_MB26_DATA2 0xffc02f48 /* CAN Controller 0 Mailbox 26 Data 2 Register */
1400#define CAN0_MB26_DATA3 0xffc02f4c /* CAN Controller 0 Mailbox 26 Data 3 Register */
1401#define CAN0_MB26_LENGTH 0xffc02f50 /* CAN Controller 0 Mailbox 26 Length Register */
1402#define CAN0_MB26_TIMESTAMP 0xffc02f54 /* CAN Controller 0 Mailbox 26 Timestamp Register */
1403#define CAN0_MB26_ID0 0xffc02f58 /* CAN Controller 0 Mailbox 26 ID0 Register */
1404#define CAN0_MB26_ID1 0xffc02f5c /* CAN Controller 0 Mailbox 26 ID1 Register */
1405#define CAN0_MB27_DATA0 0xffc02f60 /* CAN Controller 0 Mailbox 27 Data 0 Register */
1406#define CAN0_MB27_DATA1 0xffc02f64 /* CAN Controller 0 Mailbox 27 Data 1 Register */
1407#define CAN0_MB27_DATA2 0xffc02f68 /* CAN Controller 0 Mailbox 27 Data 2 Register */
1408#define CAN0_MB27_DATA3 0xffc02f6c /* CAN Controller 0 Mailbox 27 Data 3 Register */
1409#define CAN0_MB27_LENGTH 0xffc02f70 /* CAN Controller 0 Mailbox 27 Length Register */
1410#define CAN0_MB27_TIMESTAMP 0xffc02f74 /* CAN Controller 0 Mailbox 27 Timestamp Register */
1411#define CAN0_MB27_ID0 0xffc02f78 /* CAN Controller 0 Mailbox 27 ID0 Register */
1412#define CAN0_MB27_ID1 0xffc02f7c /* CAN Controller 0 Mailbox 27 ID1 Register */
1413#define CAN0_MB28_DATA0 0xffc02f80 /* CAN Controller 0 Mailbox 28 Data 0 Register */
1414#define CAN0_MB28_DATA1 0xffc02f84 /* CAN Controller 0 Mailbox 28 Data 1 Register */
1415#define CAN0_MB28_DATA2 0xffc02f88 /* CAN Controller 0 Mailbox 28 Data 2 Register */
1416#define CAN0_MB28_DATA3 0xffc02f8c /* CAN Controller 0 Mailbox 28 Data 3 Register */
1417#define CAN0_MB28_LENGTH 0xffc02f90 /* CAN Controller 0 Mailbox 28 Length Register */
1418#define CAN0_MB28_TIMESTAMP 0xffc02f94 /* CAN Controller 0 Mailbox 28 Timestamp Register */
1419#define CAN0_MB28_ID0 0xffc02f98 /* CAN Controller 0 Mailbox 28 ID0 Register */
1420#define CAN0_MB28_ID1 0xffc02f9c /* CAN Controller 0 Mailbox 28 ID1 Register */
1421#define CAN0_MB29_DATA0 0xffc02fa0 /* CAN Controller 0 Mailbox 29 Data 0 Register */
1422#define CAN0_MB29_DATA1 0xffc02fa4 /* CAN Controller 0 Mailbox 29 Data 1 Register */
1423#define CAN0_MB29_DATA2 0xffc02fa8 /* CAN Controller 0 Mailbox 29 Data 2 Register */
1424#define CAN0_MB29_DATA3 0xffc02fac /* CAN Controller 0 Mailbox 29 Data 3 Register */
1425#define CAN0_MB29_LENGTH 0xffc02fb0 /* CAN Controller 0 Mailbox 29 Length Register */
1426#define CAN0_MB29_TIMESTAMP 0xffc02fb4 /* CAN Controller 0 Mailbox 29 Timestamp Register */
1427#define CAN0_MB29_ID0 0xffc02fb8 /* CAN Controller 0 Mailbox 29 ID0 Register */
1428#define CAN0_MB29_ID1 0xffc02fbc /* CAN Controller 0 Mailbox 29 ID1 Register */
1429#define CAN0_MB30_DATA0 0xffc02fc0 /* CAN Controller 0 Mailbox 30 Data 0 Register */
1430#define CAN0_MB30_DATA1 0xffc02fc4 /* CAN Controller 0 Mailbox 30 Data 1 Register */
1431#define CAN0_MB30_DATA2 0xffc02fc8 /* CAN Controller 0 Mailbox 30 Data 2 Register */
1432#define CAN0_MB30_DATA3 0xffc02fcc /* CAN Controller 0 Mailbox 30 Data 3 Register */
1433#define CAN0_MB30_LENGTH 0xffc02fd0 /* CAN Controller 0 Mailbox 30 Length Register */
1434#define CAN0_MB30_TIMESTAMP 0xffc02fd4 /* CAN Controller 0 Mailbox 30 Timestamp Register */
1435#define CAN0_MB30_ID0 0xffc02fd8 /* CAN Controller 0 Mailbox 30 ID0 Register */
1436#define CAN0_MB30_ID1 0xffc02fdc /* CAN Controller 0 Mailbox 30 ID1 Register */
1437#define CAN0_MB31_DATA0 0xffc02fe0 /* CAN Controller 0 Mailbox 31 Data 0 Register */
1438#define CAN0_MB31_DATA1 0xffc02fe4 /* CAN Controller 0 Mailbox 31 Data 1 Register */
1439#define CAN0_MB31_DATA2 0xffc02fe8 /* CAN Controller 0 Mailbox 31 Data 2 Register */
1440#define CAN0_MB31_DATA3 0xffc02fec /* CAN Controller 0 Mailbox 31 Data 3 Register */
1441#define CAN0_MB31_LENGTH 0xffc02ff0 /* CAN Controller 0 Mailbox 31 Length Register */
1442#define CAN0_MB31_TIMESTAMP 0xffc02ff4 /* CAN Controller 0 Mailbox 31 Timestamp Register */
1443#define CAN0_MB31_ID0 0xffc02ff8 /* CAN Controller 0 Mailbox 31 ID0 Register */
1444#define CAN0_MB31_ID1 0xffc02ffc /* CAN Controller 0 Mailbox 31 ID1 Register */
1445
1446/* UART3 Registers */
1447
1448#define UART3_DLL 0xffc03100 /* Divisor Latch Low Byte */
1449#define UART3_DLH 0xffc03104 /* Divisor Latch High Byte */
1450#define UART3_GCTL 0xffc03108 /* Global Control Register */
1451#define UART3_LCR 0xffc0310c /* Line Control Register */
1452#define UART3_MCR 0xffc03110 /* Modem Control Register */
1453#define UART3_LSR 0xffc03114 /* Line Status Register */
1454#define UART3_MSR 0xffc03118 /* Modem Status Register */
1455#define UART3_SCR 0xffc0311c /* Scratch Register */
1456#define UART3_IER_SET 0xffc03120 /* Interrupt Enable Register Set */
1457#define UART3_IER_CLEAR 0xffc03124 /* Interrupt Enable Register Clear */
1458#define UART3_THR 0xffc03128 /* Transmit Hold Register */
1459#define UART3_RBR 0xffc0312c /* Receive Buffer Register */
1460
1461/* NFC Registers */
1462
1463#define NFC_CTL 0xffc03b00 /* NAND Control Register */
1464#define NFC_STAT 0xffc03b04 /* NAND Status Register */
1465#define NFC_IRQSTAT 0xffc03b08 /* NAND Interrupt Status Register */
1466#define NFC_IRQMASK 0xffc03b0c /* NAND Interrupt Mask Register */
1467#define NFC_ECC0 0xffc03b10 /* NAND ECC Register 0 */
1468#define NFC_ECC1 0xffc03b14 /* NAND ECC Register 1 */
1469#define NFC_ECC2 0xffc03b18 /* NAND ECC Register 2 */
1470#define NFC_ECC3 0xffc03b1c /* NAND ECC Register 3 */
1471#define NFC_COUNT 0xffc03b20 /* NAND ECC Count Register */
1472#define NFC_RST 0xffc03b24 /* NAND ECC Reset Register */
1473#define NFC_PGCTL 0xffc03b28 /* NAND Page Control Register */
1474#define NFC_READ 0xffc03b2c /* NAND Read Data Register */
1475#define NFC_ADDR 0xffc03b40 /* NAND Address Register */
1476#define NFC_CMD 0xffc03b44 /* NAND Command Register */
1477#define NFC_DATA_WR 0xffc03b48 /* NAND Data Write Register */
1478#define NFC_DATA_RD 0xffc03b4c /* NAND Data Read Register */
1479
1480/* Counter Registers */
1481
1482#define CNT_CONFIG 0xffc04200 /* Configuration Register */
1483#define CNT_IMASK 0xffc04204 /* Interrupt Mask Register */
1484#define CNT_STATUS 0xffc04208 /* Status Register */
1485#define CNT_COMMAND 0xffc0420c /* Command Register */
1486#define CNT_DEBOUNCE 0xffc04210 /* Debounce Register */
1487#define CNT_COUNTER 0xffc04214 /* Counter Register */
1488#define CNT_MAX 0xffc04218 /* Maximal Count Register */
1489#define CNT_MIN 0xffc0421c /* Minimal Count Register */
1490
1491/* OTP/FUSE Registers */
1492
1493#define OTP_CONTROL 0xffc04300 /* OTP/Fuse Control Register */
1494#define OTP_BEN 0xffc04304 /* OTP/Fuse Byte Enable */
1495#define OTP_STATUS 0xffc04308 /* OTP/Fuse Status */
1496#define OTP_TIMING 0xffc0430c /* OTP/Fuse Access Timing */
1497
1498/* Security Registers */
1499
1500#define SECURE_SYSSWT 0xffc04320 /* Secure System Switches */
1501#define SECURE_CONTROL 0xffc04324 /* Secure Control */
1502#define SECURE_STATUS 0xffc04328 /* Secure Status */
1503
1504/* DMA Peripheral Mux Register */
1505
1506#define DMAC1_PERIMUX 0xffc04340 /* DMA Controller 1 Peripheral Multiplexer Register */
1507
1508/* OTP Read/Write Data Buffer Registers */
1509
1510#define OTP_DATA0 0xffc04380 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1511#define OTP_DATA1 0xffc04384 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1512#define OTP_DATA2 0xffc04388 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1513#define OTP_DATA3 0xffc0438c /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1514
1515/* Handshake MDMA is not defined in the shared file because it is not available on the ADSP-BF542 processor */
1516
1517/* ********************************************************** */
1518/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
1519/* and MULTI BIT READ MACROS */
1520/* ********************************************************** */
1521
1522/* SIC_IMASK Masks */
1523#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
1524#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
1525#define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */
1526#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */
1527
1528/* SIC_IWR Masks */
1529#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
1530#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
1531#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
1532#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */
1533
1534/* Bit masks for SIC_IAR0 */
1535
1536#define PLL_WAKEUP 0x1 /* PLL Wakeup */
1537
1538/* Bit masks for SIC_IWR0, SIC_IMASK0, SIC_ISR0 */
1539
1540#define DMA0_ERR 0x2 /* DMA Controller 0 Error */
1541#define EPPI0_ERR 0x4 /* EPPI0 Error */
1542#define SPORT0_ERR 0x8 /* SPORT0 Error */
1543#define SPORT1_ERR 0x10 /* SPORT1 Error */
1544#define SPI0_ERR 0x20 /* SPI0 Error */
1545#define UART0_ERR 0x40 /* UART0 Error */
1546#define RTC 0x80 /* Real-Time Clock */
1547#define DMA12 0x100 /* DMA Channel 12 */
1548#define DMA0 0x200 /* DMA Channel 0 */
1549#define DMA1 0x400 /* DMA Channel 1 */
1550#define DMA2 0x800 /* DMA Channel 2 */
1551#define DMA3 0x1000 /* DMA Channel 3 */
1552#define DMA4 0x2000 /* DMA Channel 4 */
1553#define DMA6 0x4000 /* DMA Channel 6 */
1554#define DMA7 0x8000 /* DMA Channel 7 */
1555#define PINT0 0x80000 /* Pin Interrupt 0 */
1556#define PINT1 0x100000 /* Pin Interrupt 1 */
1557#define MDMA0 0x200000 /* Memory DMA Stream 0 */
1558#define MDMA1 0x400000 /* Memory DMA Stream 1 */
1559#define WDOG 0x800000 /* Watchdog Timer */
1560#define DMA1_ERR 0x1000000 /* DMA Controller 1 Error */
1561#define SPORT2_ERR 0x2000000 /* SPORT2 Error */
1562#define SPORT3_ERR 0x4000000 /* SPORT3 Error */
1563#define MXVR_SD 0x8000000 /* MXVR Synchronous Data */
1564#define SPI1_ERR 0x10000000 /* SPI1 Error */
1565#define SPI2_ERR 0x20000000 /* SPI2 Error */
1566#define UART1_ERR 0x40000000 /* UART1 Error */
1567#define UART2_ERR 0x80000000 /* UART2 Error */
1568
1569/* Bit masks for SIC_IWR1, SIC_IMASK1, SIC_ISR1 */
1570
1571#define CAN0_ERR 0x1 /* CAN0 Error */
1572#define DMA18 0x2 /* DMA Channel 18 */
1573#define DMA19 0x4 /* DMA Channel 19 */
1574#define DMA20 0x8 /* DMA Channel 20 */
1575#define DMA21 0x10 /* DMA Channel 21 */
1576#define DMA13 0x20 /* DMA Channel 13 */
1577#define DMA14 0x40 /* DMA Channel 14 */
1578#define DMA5 0x80 /* DMA Channel 5 */
1579#define DMA23 0x100 /* DMA Channel 23 */
1580#define DMA8 0x200 /* DMA Channel 8 */
1581#define DMA9 0x400 /* DMA Channel 9 */
1582#define DMA10 0x800 /* DMA Channel 10 */
1583#define DMA11 0x1000 /* DMA Channel 11 */
1584#define TWI0 0x2000 /* TWI0 */
1585#define TWI1 0x4000 /* TWI1 */
1586#define CAN0_RX 0x8000 /* CAN0 Receive */
1587#define CAN0_TX 0x10000 /* CAN0 Transmit */
1588#define MDMA2 0x20000 /* Memory DMA Stream 0 */
1589#define MDMA3 0x40000 /* Memory DMA Stream 1 */
1590#define MXVR_STAT 0x80000 /* MXVR Status */
1591#define MXVR_CM 0x100000 /* MXVR Control Message */
1592#define MXVR_AP 0x200000 /* MXVR Asynchronous Packet */
1593#define EPPI1_ERR 0x400000 /* EPPI1 Error */
1594#define EPPI2_ERR 0x800000 /* EPPI2 Error */
1595#define UART3_ERR 0x1000000 /* UART3 Error */
1596#define HOST_ERR 0x2000000 /* Host DMA Port Error */
1597#define USB_ERR 0x4000000 /* USB Error */
1598#define PIXC_ERR 0x8000000 /* Pixel Compositor Error */
1599#define NFC_ERR 0x10000000 /* Nand Flash Controller Error */
1600#define ATAPI_ERR 0x20000000 /* ATAPI Error */
1601#define CAN1_ERR 0x40000000 /* CAN1 Error */
1602#define DMAR0_ERR 0x80000000 /* DMAR0 Overflow Error */
1603#define DMAR1_ERR 0x80000000 /* DMAR1 Overflow Error */
1604#define DMAR0 0x80000000 /* DMAR0 Block */
1605#define DMAR1 0x80000000 /* DMAR1 Block */
1606
1607/* Bit masks for SIC_IWR2, SIC_IMASK2, SIC_ISR2 */
1608
1609#define DMA15 0x1 /* DMA Channel 15 */
1610#define DMA16 0x2 /* DMA Channel 16 */
1611#define DMA17 0x4 /* DMA Channel 17 */
1612#define DMA22 0x8 /* DMA Channel 22 */
1613#define CNT 0x10 /* Counter */
1614#define KEY 0x20 /* Keypad */
1615#define CAN1_RX 0x40 /* CAN1 Receive */
1616#define CAN1_TX 0x80 /* CAN1 Transmit */
1617#define SDH_INT_MASK0 0x100 /* SDH Mask 0 */
1618#define SDH_INT_MASK1 0x200 /* SDH Mask 1 */
1619#define USB_EINT 0x400 /* USB Exception */
1620#define USB_INT0 0x800 /* USB Interrupt 0 */
1621#define USB_INT1 0x1000 /* USB Interrupt 1 */
1622#define USB_INT2 0x2000 /* USB Interrupt 2 */
1623#define USB_DMAINT 0x4000 /* USB DMA */
1624#define OTPSEC 0x8000 /* OTP Access Complete */
1625#define TIMER0 0x400000 /* Timer 0 */
1626#define TIMER1 0x800000 /* Timer 1 */
1627#define TIMER2 0x1000000 /* Timer 2 */
1628#define TIMER3 0x2000000 /* Timer 3 */
1629#define TIMER4 0x4000000 /* Timer 4 */
1630#define TIMER5 0x8000000 /* Timer 5 */
1631#define TIMER6 0x10000000 /* Timer 6 */
1632#define TIMER7 0x20000000 /* Timer 7 */
1633#define PINT2 0x40000000 /* Pin Interrupt 2 */
1634#define PINT3 0x80000000 /* Pin Interrupt 3 */
1635
1636/* Bit masks for DMAx_CONFIG, MDMA_Sx_CONFIG, MDMA_Dx_CONFIG */
1637
1638#define DMAEN 0x1 /* DMA Channel Enable */
1639#define WNR 0x2 /* DMA Direction */
1640#define WDSIZE_8 0x0 /* Transfer Word Size = 8 */
1641#define WDSIZE_16 0x4 /* Transfer Word Size = 16 */
1642#define WDSIZE_32 0x8 /* Transfer Word Size = 32 */
1643#define DMA2D 0x10 /* DMA Mode */
1644#define RESTART 0x20 /* Work Unit Transitions */
1645#define DI_SEL 0x40 /* Data Interrupt Timing Select */
1646#define DI_EN 0x80 /* Data Interrupt Enable */
1647
1648#define NDSIZE 0xf00 /* Flex Descriptor Size */
1649#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
1650#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
1651#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
1652#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
1653#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
1654#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
1655#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
1656#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
1657#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
1658#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
1659
1660#define DMAFLOW 0xf000 /* Next Operation */
1661#define DMAFLOW_STOP 0x0000 /* Stop Mode */
1662#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
1663#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
1664#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
1665#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
1666
1667/* Bit masks for DMAx_IRQ_STATUS, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */
1668
1669#define DMA_DONE 0x1 /* DMA Completion Interrupt Status */
1670#define DMA_ERR 0x2 /* DMA Error Interrupt Status */
1671#define DFETCH 0x4 /* DMA Descriptor Fetch */
1672#define DMA_RUN 0x8 /* DMA Channel Running */
1673
1674/* Bit masks for DMAx_PERIPHERAL_MAP, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */
1675
1676#define CTYPE 0x40 /* DMA Channel Type */
1677#define PMAP 0xf000 /* Peripheral Mapped To This Channel */
1678
1679/* Bit masks for DMACx_TCPER */
1680
1681#define DCB_TRAFFIC_PERIOD 0xf /* DCB Traffic Control Period */
1682#define DEB_TRAFFIC_PERIOD 0xf0 /* DEB Traffic Control Period */
1683#define DAB_TRAFFIC_PERIOD 0x700 /* DAB Traffic Control Period */
1684#define MDMA_ROUND_ROBIN_PERIOD 0xf800 /* MDMA Round Robin Period */
1685
1686/* Bit masks for DMACx_TCCNT */
1687
1688#define DCB_TRAFFIC_COUNT 0xf /* DCB Traffic Control Count */
1689#define DEB_TRAFFIC_COUNT 0xf0 /* DEB Traffic Control Count */
1690#define DAB_TRAFFIC_COUNT 0x700 /* DAB Traffic Control Count */
1691#define MDMA_ROUND_ROBIN_COUNT 0xf800 /* MDMA Round Robin Count */
1692
1693/* Bit masks for DMAC1_PERIMUX */
1694
1695#define PMUXSDH 0x1 /* Peripheral Select for DMA22 channel */
1696
1697/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
1698/* EBIU_AMGCTL Masks */
1699#define AMCKEN 0x0001 /* Enable CLKOUT */
1700#define AMBEN_NONE 0x0000 /* All Banks Disabled */
1701#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */
1702#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */
1703#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */
1704#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */
1705
1706
1707/* Bit masks for EBIU_AMBCTL0 */
1708
1709#define B0RDYEN 0x1 /* Bank 0 ARDY Enable */
1710#define B0RDYPOL 0x2 /* Bank 0 ARDY Polarity */
1711#define B0TT 0xc /* Bank 0 transition time */
1712#define B0ST 0x30 /* Bank 0 Setup time */
1713#define B0HT 0xc0 /* Bank 0 Hold time */
1714#define B0RAT 0xf00 /* Bank 0 Read access time */
1715#define B0WAT 0xf000 /* Bank 0 write access time */
1716#define B1RDYEN 0x10000 /* Bank 1 ARDY Enable */
1717#define B1RDYPOL 0x20000 /* Bank 1 ARDY Polarity */
1718#define B1TT 0xc0000 /* Bank 1 transition time */
1719#define B1ST 0x300000 /* Bank 1 Setup time */
1720#define B1HT 0xc00000 /* Bank 1 Hold time */
1721#define B1RAT 0xf000000 /* Bank 1 Read access time */
1722#define B1WAT 0xf0000000 /* Bank 1 write access time */
1723
1724/* Bit masks for EBIU_AMBCTL1 */
1725
1726#define B2RDYEN 0x1 /* Bank 2 ARDY Enable */
1727#define B2RDYPOL 0x2 /* Bank 2 ARDY Polarity */
1728#define B2TT 0xc /* Bank 2 transition time */
1729#define B2ST 0x30 /* Bank 2 Setup time */
1730#define B2HT 0xc0 /* Bank 2 Hold time */
1731#define B2RAT 0xf00 /* Bank 2 Read access time */
1732#define B2WAT 0xf000 /* Bank 2 write access time */
1733#define B3RDYEN 0x10000 /* Bank 3 ARDY Enable */
1734#define B3RDYPOL 0x20000 /* Bank 3 ARDY Polarity */
1735#define B3TT 0xc0000 /* Bank 3 transition time */
1736#define B3ST 0x300000 /* Bank 3 Setup time */
1737#define B3HT 0xc00000 /* Bank 3 Hold time */
1738#define B3RAT 0xf000000 /* Bank 3 Read access time */
1739#define B3WAT 0xf0000000 /* Bank 3 write access time */
1740
1741/* Bit masks for EBIU_MBSCTL */
1742
1743#define AMSB0CTL 0x3 /* Async Memory Bank 0 select */
1744#define AMSB1CTL 0xc /* Async Memory Bank 1 select */
1745#define AMSB2CTL 0x30 /* Async Memory Bank 2 select */
1746#define AMSB3CTL 0xc0 /* Async Memory Bank 3 select */
1747
1748/* Bit masks for EBIU_MODE */
1749
1750#define B0MODE 0x3 /* Async Memory Bank 0 Access Mode */
1751#define B1MODE 0xc /* Async Memory Bank 1 Access Mode */
1752#define B2MODE 0x30 /* Async Memory Bank 2 Access Mode */
1753#define B3MODE 0xc0 /* Async Memory Bank 3 Access Mode */
1754
1755/* Bit masks for EBIU_FCTL */
1756
1757#define TESTSETLOCK 0x1 /* Test set lock */
1758#define BCLK 0x6 /* Burst clock frequency */
1759#define PGWS 0x38 /* Page wait states */
1760#define PGSZ 0x40 /* Page size */
1761#define RDDL 0x380 /* Read data delay */
1762
1763/* Bit masks for EBIU_ARBSTAT */
1764
1765#define ARBSTAT 0x1 /* Arbitration status */
1766#define BGSTAT 0x2 /* Bus grant status */
1767
1768/* Bit masks for EBIU_DDRCTL0 */
1769
1770#define TREFI 0x3fff /* Refresh Interval */
1771#define TRFC 0x3c000 /* Auto-refresh command period */
1772#define TRP 0x3c0000 /* Pre charge-to-active command period */
1773#define TRAS 0x3c00000 /* Min Active-to-pre charge time */
1774#define TRC 0x3c000000 /* Active-to-active time */
1775#define DDR_TRAS(x) ((x<<22)&TRAS) /* DDR tRAS = (1~15) cycles */
1776#define DDR_TRP(x) ((x<<18)&TRP) /* DDR tRP = (1~15) cycles */
1777#define DDR_TRC(x) ((x<<26)&TRC) /* DDR tRC = (1~15) cycles */
1778#define DDR_TRFC(x) ((x<<14)&TRFC) /* DDR tRFC = (1~15) cycles */
1779#define DDR_TREFI(x) (x&TREFI) /* DDR tRFC = (1~15) cycles */
1780
1781/* Bit masks for EBIU_DDRCTL1 */
1782
1783#define TRCD 0xf /* Active-to-Read/write delay */
1784#define TMRD 0xf0 /* Mode register set to active */
1785#define TWR 0x300 /* Write Recovery time */
1786#define DDRDATWIDTH 0x3000 /* DDR data width */
1787#define EXTBANKS 0xc000 /* External banks */
1788#define DDRDEVWIDTH 0x30000 /* DDR device width */
1789#define DDRDEVSIZE 0xc0000 /* DDR device size */
1790#define TWTR 0xf0000000 /* Write-to-read delay */
1791#define DDR_TWTR(x) ((x<<28)&TWTR) /* DDR tWTR = (1~15) cycles */
1792#define DDR_TMRD(x) ((x<<4)&TMRD) /* DDR tMRD = (1~15) cycles */
1793#define DDR_TWR(x) ((x<<8)&TWR) /* DDR tWR = (1~15) cycles */
1794#define DDR_TRCD(x) (x&TRCD) /* DDR tRCD = (1~15) cycles */
1795#define DDR_DATWIDTH 0x2000 /* DDR data width */
1796#define EXTBANK_1 0 /* 1 external bank */
1797#define EXTBANK_2 0x4000 /* 2 external banks */
1798#define DEVSZ_64 0x40000 /* DDR External Bank Size = 64MB */
1799#define DEVSZ_128 0x80000 /* DDR External Bank Size = 128MB */
1800#define DEVSZ_256 0xc0000 /* DDR External Bank Size = 256MB */
1801#define DEVSZ_512 0 /* DDR External Bank Size = 512MB */
1802#define DEVWD_4 0 /* DDR Device Width = 4 Bits */
1803#define DEVWD_8 0x10000 /* DDR Device Width = 8 Bits */
1804#define DEVWD_16 0x20000 /* DDR Device Width = 16 Bits */
1805
1806/* Bit masks for EBIU_DDRCTL2 */
1807
1808#define BURSTLENGTH 0x7 /* Burst length */
1809#define CASLATENCY 0x70 /* CAS latency */
1810#define DLLRESET 0x100 /* DLL Reset */
1811#define REGE 0x1000 /* Register mode enable */
1812#define CL_1_5 0x50 /* DDR CAS Latency = 1.5 cycles */
1813#define CL_2 0x20 /* DDR CAS Latency = 2 cycles */
1814#define CL_2_5 0x60 /* DDR CAS Latency = 2.5 cycles */
1815#define CL_3 0x30 /* DDR CAS Latency = 3 cycles */
1816
1817/* Bit masks for EBIU_DDRCTL3 */
1818
1819#define PASR 0x7 /* Partial array self-refresh */
1820
1821/* Bit masks for EBIU_DDRQUE */
1822
1823#define DEB1_PFLEN 0x3 /* Pre fetch length for DEB1 accesses */
1824#define DEB2_PFLEN 0xc /* Pre fetch length for DEB2 accesses */
1825#define DEB3_PFLEN 0x30 /* Pre fetch length for DEB3 accesses */
1826#define DEB_ARB_PRIORITY 0x700 /* Arbitration between DEB busses */
1827#define DEB1_URGENT 0x1000 /* DEB1 Urgent */
1828#define DEB2_URGENT 0x2000 /* DEB2 Urgent */
1829#define DEB3_URGENT 0x4000 /* DEB3 Urgent */
1830
1831/* Bit masks for EBIU_ERRMST */
1832
1833#define DEB1_ERROR 0x1 /* DEB1 Error */
1834#define DEB2_ERROR 0x2 /* DEB2 Error */
1835#define DEB3_ERROR 0x4 /* DEB3 Error */
1836#define CORE_ERROR 0x8 /* Core error */
1837#define DEB_MERROR 0x10 /* DEB1 Error (2nd) */
1838#define DEB2_MERROR 0x20 /* DEB2 Error (2nd) */
1839#define DEB3_MERROR 0x40 /* DEB3 Error (2nd) */
1840#define CORE_MERROR 0x80 /* Core Error (2nd) */
1841
1842/* Bit masks for EBIU_ERRADD */
1843
1844#define ERROR_ADDRESS 0xffffffff /* Error Address */
1845
1846/* Bit masks for EBIU_RSTCTL */
1847
1848#define DDRSRESET 0x1 /* DDR soft reset */
1849#define PFTCHSRESET 0x4 /* DDR prefetch reset */
1850#define SRREQ 0x8 /* Self-refresh request */
1851#define SRACK 0x10 /* Self-refresh acknowledge */
1852#define MDDRENABLE 0x20 /* Mobile DDR enable */
1853
1854/* Bit masks for EBIU_DDRBRC0 */
1855
1856#define BRC0 0xffffffff /* Count */
1857
1858/* Bit masks for EBIU_DDRBRC1 */
1859
1860#define BRC1 0xffffffff /* Count */
1861
1862/* Bit masks for EBIU_DDRBRC2 */
1863
1864#define BRC2 0xffffffff /* Count */
1865
1866/* Bit masks for EBIU_DDRBRC3 */
1867
1868#define BRC3 0xffffffff /* Count */
1869
1870/* Bit masks for EBIU_DDRBRC4 */
1871
1872#define BRC4 0xffffffff /* Count */
1873
1874/* Bit masks for EBIU_DDRBRC5 */
1875
1876#define BRC5 0xffffffff /* Count */
1877
1878/* Bit masks for EBIU_DDRBRC6 */
1879
1880#define BRC6 0xffffffff /* Count */
1881
1882/* Bit masks for EBIU_DDRBRC7 */
1883
1884#define BRC7 0xffffffff /* Count */
1885
1886/* Bit masks for EBIU_DDRBWC0 */
1887
1888#define BWC0 0xffffffff /* Count */
1889
1890/* Bit masks for EBIU_DDRBWC1 */
1891
1892#define BWC1 0xffffffff /* Count */
1893
1894/* Bit masks for EBIU_DDRBWC2 */
1895
1896#define BWC2 0xffffffff /* Count */
1897
1898/* Bit masks for EBIU_DDRBWC3 */
1899
1900#define BWC3 0xffffffff /* Count */
1901
1902/* Bit masks for EBIU_DDRBWC4 */
1903
1904#define BWC4 0xffffffff /* Count */
1905
1906/* Bit masks for EBIU_DDRBWC5 */
1907
1908#define BWC5 0xffffffff /* Count */
1909
1910/* Bit masks for EBIU_DDRBWC6 */
1911
1912#define BWC6 0xffffffff /* Count */
1913
1914/* Bit masks for EBIU_DDRBWC7 */
1915
1916#define BWC7 0xffffffff /* Count */
1917
1918/* Bit masks for EBIU_DDRACCT */
1919
1920#define ACCT 0xffffffff /* Count */
1921
1922/* Bit masks for EBIU_DDRTACT */
1923
1924#define TECT 0xffffffff /* Count */
1925
1926/* Bit masks for EBIU_DDRARCT */
1927
1928#define ARCT 0xffffffff /* Count */
1929
1930/* Bit masks for EBIU_DDRGC0 */
1931
1932#define GC0 0xffffffff /* Count */
1933
1934/* Bit masks for EBIU_DDRGC1 */
1935
1936#define GC1 0xffffffff /* Count */
1937
1938/* Bit masks for EBIU_DDRGC2 */
1939
1940#define GC2 0xffffffff /* Count */
1941
1942/* Bit masks for EBIU_DDRGC3 */
1943
1944#define GC3 0xffffffff /* Count */
1945
1946/* Bit masks for EBIU_DDRMCEN */
1947
1948#define B0WCENABLE 0x1 /* Bank 0 write count enable */
1949#define B1WCENABLE 0x2 /* Bank 1 write count enable */
1950#define B2WCENABLE 0x4 /* Bank 2 write count enable */
1951#define B3WCENABLE 0x8 /* Bank 3 write count enable */
1952#define B4WCENABLE 0x10 /* Bank 4 write count enable */
1953#define B5WCENABLE 0x20 /* Bank 5 write count enable */
1954#define B6WCENABLE 0x40 /* Bank 6 write count enable */
1955#define B7WCENABLE 0x80 /* Bank 7 write count enable */
1956#define B0RCENABLE 0x100 /* Bank 0 read count enable */
1957#define B1RCENABLE 0x200 /* Bank 1 read count enable */
1958#define B2RCENABLE 0x400 /* Bank 2 read count enable */
1959#define B3RCENABLE 0x800 /* Bank 3 read count enable */
1960#define B4RCENABLE 0x1000 /* Bank 4 read count enable */
1961#define B5RCENABLE 0x2000 /* Bank 5 read count enable */
1962#define B6RCENABLE 0x4000 /* Bank 6 read count enable */
1963#define B7RCENABLE 0x8000 /* Bank 7 read count enable */
1964#define ROWACTCENABLE 0x10000 /* DDR Row activate count enable */
1965#define RWTCENABLE 0x20000 /* DDR R/W Turn around count enable */
1966#define ARCENABLE 0x40000 /* DDR Auto-refresh count enable */
1967#define GC0ENABLE 0x100000 /* DDR Grant count 0 enable */
1968#define GC1ENABLE 0x200000 /* DDR Grant count 1 enable */
1969#define GC2ENABLE 0x400000 /* DDR Grant count 2 enable */
1970#define GC3ENABLE 0x800000 /* DDR Grant count 3 enable */
1971#define GCCONTROL 0x3000000 /* DDR Grant Count Control */
1972
1973/* Bit masks for EBIU_DDRMCCL */
1974
1975#define CB0WCOUNT 0x1 /* Clear write count 0 */
1976#define CB1WCOUNT 0x2 /* Clear write count 1 */
1977#define CB2WCOUNT 0x4 /* Clear write count 2 */
1978#define CB3WCOUNT 0x8 /* Clear write count 3 */
1979#define CB4WCOUNT 0x10 /* Clear write count 4 */
1980#define CB5WCOUNT 0x20 /* Clear write count 5 */
1981#define CB6WCOUNT 0x40 /* Clear write count 6 */
1982#define CB7WCOUNT 0x80 /* Clear write count 7 */
1983#define CBRCOUNT 0x100 /* Clear read count 0 */
1984#define CB1RCOUNT 0x200 /* Clear read count 1 */
1985#define CB2RCOUNT 0x400 /* Clear read count 2 */
1986#define CB3RCOUNT 0x800 /* Clear read count 3 */
1987#define CB4RCOUNT 0x1000 /* Clear read count 4 */
1988#define CB5RCOUNT 0x2000 /* Clear read count 5 */
1989#define CB6RCOUNT 0x4000 /* Clear read count 6 */
1990#define CB7RCOUNT 0x8000 /* Clear read count 7 */
1991#define CRACOUNT 0x10000 /* Clear row activation count */
1992#define CRWTACOUNT 0x20000 /* Clear R/W turn-around count */
1993#define CARCOUNT 0x40000 /* Clear auto-refresh count */
1994#define CG0COUNT 0x100000 /* Clear grant count 0 */
1995#define CG1COUNT 0x200000 /* Clear grant count 1 */
1996#define CG2COUNT 0x400000 /* Clear grant count 2 */
1997#define CG3COUNT 0x800000 /* Clear grant count 3 */
1998
1999/* Bit masks for (PORTx is PORTA - PORTJ) includes PORTx_FER, PORTx_SET, PORTx_CLEAR, PORTx_DIR_SET, PORTx_DIR_CLEAR, PORTx_INEN */
2000
2001#define Px0 0x1 /* GPIO 0 */
2002#define Px1 0x2 /* GPIO 1 */
2003#define Px2 0x4 /* GPIO 2 */
2004#define Px3 0x8 /* GPIO 3 */
2005#define Px4 0x10 /* GPIO 4 */
2006#define Px5 0x20 /* GPIO 5 */
2007#define Px6 0x40 /* GPIO 6 */
2008#define Px7 0x80 /* GPIO 7 */
2009#define Px8 0x100 /* GPIO 8 */
2010#define Px9 0x200 /* GPIO 9 */
2011#define Px10 0x400 /* GPIO 10 */
2012#define Px11 0x800 /* GPIO 11 */
2013#define Px12 0x1000 /* GPIO 12 */
2014#define Px13 0x2000 /* GPIO 13 */
2015#define Px14 0x4000 /* GPIO 14 */
2016#define Px15 0x8000 /* GPIO 15 */
2017
2018/* Bit masks for PORTA_MUX - PORTJ_MUX */
2019
2020#define PxM0 0x3 /* GPIO Mux 0 */
2021#define PxM1 0xc /* GPIO Mux 1 */
2022#define PxM2 0x30 /* GPIO Mux 2 */
2023#define PxM3 0xc0 /* GPIO Mux 3 */
2024#define PxM4 0x300 /* GPIO Mux 4 */
2025#define PxM5 0xc00 /* GPIO Mux 5 */
2026#define PxM6 0x3000 /* GPIO Mux 6 */
2027#define PxM7 0xc000 /* GPIO Mux 7 */
2028#define PxM8 0x30000 /* GPIO Mux 8 */
2029#define PxM9 0xc0000 /* GPIO Mux 9 */
2030#define PxM10 0x300000 /* GPIO Mux 10 */
2031#define PxM11 0xc00000 /* GPIO Mux 11 */
2032#define PxM12 0x3000000 /* GPIO Mux 12 */
2033#define PxM13 0xc000000 /* GPIO Mux 13 */
2034#define PxM14 0x30000000 /* GPIO Mux 14 */
2035#define PxM15 0xc0000000 /* GPIO Mux 15 */
2036
2037
2038/* Bit masks for PINTx_MASK_SET/CLEAR, PINTx_REQUEST, PINTx_LATCH, PINTx_EDGE_SET/CLEAR, PINTx_INVERT_SET/CLEAR, PINTx_PINTSTATE */
2039
2040#define IB0 0x1 /* Interrupt Bit 0 */
2041#define IB1 0x2 /* Interrupt Bit 1 */
2042#define IB2 0x4 /* Interrupt Bit 2 */
2043#define IB3 0x8 /* Interrupt Bit 3 */
2044#define IB4 0x10 /* Interrupt Bit 4 */
2045#define IB5 0x20 /* Interrupt Bit 5 */
2046#define IB6 0x40 /* Interrupt Bit 6 */
2047#define IB7 0x80 /* Interrupt Bit 7 */
2048#define IB8 0x100 /* Interrupt Bit 8 */
2049#define IB9 0x200 /* Interrupt Bit 9 */
2050#define IB10 0x400 /* Interrupt Bit 10 */
2051#define IB11 0x800 /* Interrupt Bit 11 */
2052#define IB12 0x1000 /* Interrupt Bit 12 */
2053#define IB13 0x2000 /* Interrupt Bit 13 */
2054#define IB14 0x4000 /* Interrupt Bit 14 */
2055#define IB15 0x8000 /* Interrupt Bit 15 */
2056
2057/* Bit masks for TIMERx_CONFIG */
2058
2059#define TMODE 0x3 /* Timer Mode */
2060#define PULSE_HI 0x4 /* Pulse Polarity */
2061#define PERIOD_CNT 0x8 /* Period Count */
2062#define IRQ_ENA 0x10 /* Interrupt Request Enable */
2063#define TIN_SEL 0x20 /* Timer Input Select */
2064#define OUT_DIS 0x40 /* Output Pad Disable */
2065#define CLK_SEL 0x80 /* Timer Clock Select */
2066#define TOGGLE_HI 0x100 /* Toggle Mode */
2067#define EMU_RUN 0x200 /* Emulation Behavior Select */
2068#define ERR_TYP 0xc000 /* Error Type */
2069
2070/* Bit masks for TIMER_ENABLE0 */
2071
2072#define TIMEN0 0x1 /* Timer 0 Enable */
2073#define TIMEN1 0x2 /* Timer 1 Enable */
2074#define TIMEN2 0x4 /* Timer 2 Enable */
2075#define TIMEN3 0x8 /* Timer 3 Enable */
2076#define TIMEN4 0x10 /* Timer 4 Enable */
2077#define TIMEN5 0x20 /* Timer 5 Enable */
2078#define TIMEN6 0x40 /* Timer 6 Enable */
2079#define TIMEN7 0x80 /* Timer 7 Enable */
2080
2081/* Bit masks for TIMER_DISABLE0 */
2082
2083#define TIMDIS0 0x1 /* Timer 0 Disable */
2084#define TIMDIS1 0x2 /* Timer 1 Disable */
2085#define TIMDIS2 0x4 /* Timer 2 Disable */
2086#define TIMDIS3 0x8 /* Timer 3 Disable */
2087#define TIMDIS4 0x10 /* Timer 4 Disable */
2088#define TIMDIS5 0x20 /* Timer 5 Disable */
2089#define TIMDIS6 0x40 /* Timer 6 Disable */
2090#define TIMDIS7 0x80 /* Timer 7 Disable */
2091
2092/* Bit masks for TIMER_STATUS0 */
2093
2094#define TIMIL0 0x1 /* Timer 0 Interrupt */
2095#define TIMIL1 0x2 /* Timer 1 Interrupt */
2096#define TIMIL2 0x4 /* Timer 2 Interrupt */
2097#define TIMIL3 0x8 /* Timer 3 Interrupt */
2098#define TOVF_ERR0 0x10 /* Timer 0 Counter Overflow */
2099#define TOVF_ERR1 0x20 /* Timer 1 Counter Overflow */
2100#define TOVF_ERR2 0x40 /* Timer 2 Counter Overflow */
2101#define TOVF_ERR3 0x80 /* Timer 3 Counter Overflow */
2102#define TRUN0 0x1000 /* Timer 0 Slave Enable Status */
2103#define TRUN1 0x2000 /* Timer 1 Slave Enable Status */
2104#define TRUN2 0x4000 /* Timer 2 Slave Enable Status */
2105#define TRUN3 0x8000 /* Timer 3 Slave Enable Status */
2106#define TIMIL4 0x10000 /* Timer 4 Interrupt */
2107#define TIMIL5 0x20000 /* Timer 5 Interrupt */
2108#define TIMIL6 0x40000 /* Timer 6 Interrupt */
2109#define TIMIL7 0x80000 /* Timer 7 Interrupt */
2110#define TOVF_ERR4 0x100000 /* Timer 4 Counter Overflow */
2111#define TOVF_ERR5 0x200000 /* Timer 5 Counter Overflow */
2112#define TOVF_ERR6 0x400000 /* Timer 6 Counter Overflow */
2113#define TOVF_ERR7 0x800000 /* Timer 7 Counter Overflow */
2114#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */
2115#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */
2116#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
2117#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
2118
2119/* Bit masks for WDOG_CTL */
2120
2121#define WDEV 0x6 /* Watchdog Event */
2122#define WDEN 0xff0 /* Watchdog Enable */
2123#define WDRO 0x8000 /* Watchdog Rolled Over */
2124
2125/* Bit masks for CNT_CONFIG */
2126
2127#define CNTE 0x1 /* Counter Enable */
2128#define DEBE 0x2 /* Debounce Enable */
2129#define CDGINV 0x10 /* CDG Pin Polarity Invert */
2130#define CUDINV 0x20 /* CUD Pin Polarity Invert */
2131#define CZMINV 0x40 /* CZM Pin Polarity Invert */
2132#define CNTMODE 0x700 /* Counter Operating Mode */
2133#define ZMZC 0x800 /* CZM Zeroes Counter Enable */
2134#define BNDMODE 0x3000 /* Boundary register Mode */
2135#define INPDIS 0x8000 /* CUG and CDG Input Disable */
2136
2137/* Bit masks for CNT_IMASK */
2138
2139#define ICIE 0x1 /* Illegal Gray/Binary Code Interrupt Enable */
2140#define UCIE 0x2 /* Up count Interrupt Enable */
2141#define DCIE 0x4 /* Down count Interrupt Enable */
2142#define MINCIE 0x8 /* Min Count Interrupt Enable */
2143#define MAXCIE 0x10 /* Max Count Interrupt Enable */
2144#define COV31IE 0x20 /* Bit 31 Overflow Interrupt Enable */
2145#define COV15IE 0x40 /* Bit 15 Overflow Interrupt Enable */
2146#define CZEROIE 0x80 /* Count to Zero Interrupt Enable */
2147#define CZMIE 0x100 /* CZM Pin Interrupt Enable */
2148#define CZMEIE 0x200 /* CZM Error Interrupt Enable */
2149#define CZMZIE 0x400 /* CZM Zeroes Counter Interrupt Enable */
2150
2151/* Bit masks for CNT_STATUS */
2152
2153#define ICII 0x1 /* Illegal Gray/Binary Code Interrupt Identifier */
2154#define UCII 0x2 /* Up count Interrupt Identifier */
2155#define DCII 0x4 /* Down count Interrupt Identifier */
2156#define MINCII 0x8 /* Min Count Interrupt Identifier */
2157#define MAXCII 0x10 /* Max Count Interrupt Identifier */
2158#define COV31II 0x20 /* Bit 31 Overflow Interrupt Identifier */
2159#define COV15II 0x40 /* Bit 15 Overflow Interrupt Identifier */
2160#define CZEROII 0x80 /* Count to Zero Interrupt Identifier */
2161#define CZMII 0x100 /* CZM Pin Interrupt Identifier */
2162#define CZMEII 0x200 /* CZM Error Interrupt Identifier */
2163#define CZMZII 0x400 /* CZM Zeroes Counter Interrupt Identifier */
2164
2165/* Bit masks for CNT_COMMAND */
2166
2167#define W1LCNT 0xf /* Load Counter Register */
2168#define W1LMIN 0xf0 /* Load Min Register */
2169#define W1LMAX 0xf00 /* Load Max Register */
2170#define W1ZMONCE 0x1000 /* Enable CZM Clear Counter Once */
2171
2172/* Bit masks for CNT_DEBOUNCE */
2173
2174#define DPRESCALE 0xf /* Load Counter Register */
2175
2176/* Bit masks for RTC_STAT */
2177
2178#define SECONDS 0x3f /* Seconds */
2179#define MINUTES 0xfc0 /* Minutes */
2180#define HOURS 0x1f000 /* Hours */
2181#define DAY_COUNTER 0xfffe0000 /* Day Counter */
2182
2183/* Bit masks for RTC_ICTL */
2184
2185#define STOPWATCH_INTERRUPT_ENABLE 0x1 /* Stopwatch Interrupt Enable */
2186#define ALARM_INTERRUPT_ENABLE 0x2 /* Alarm Interrupt Enable */
2187#define SECONDS_INTERRUPT_ENABLE 0x4 /* Seconds Interrupt Enable */
2188#define MINUTES_INTERRUPT_ENABLE 0x8 /* Minutes Interrupt Enable */
2189#define HOURS_INTERRUPT_ENABLE 0x10 /* Hours Interrupt Enable */
2190#define TWENTY_FOUR_HOURS_INTERRUPT_ENABLE 0x20 /* 24 Hours Interrupt Enable */
2191#define DAY_ALARM_INTERRUPT_ENABLE 0x40 /* Day Alarm Interrupt Enable */
2192#define WRITE_COMPLETE_INTERRUPT_ENABLE 0x8000 /* Write Complete Interrupt Enable */
2193
2194/* Bit masks for RTC_ISTAT */
2195
2196#define STOPWATCH_EVENT_FLAG 0x1 /* Stopwatch Event Flag */
2197#define ALARM_EVENT_FLAG 0x2 /* Alarm Event Flag */
2198#define SECONDS_EVENT_FLAG 0x4 /* Seconds Event Flag */
2199#define MINUTES_EVENT_FLAG 0x8 /* Minutes Event Flag */
2200#define HOURS_EVENT_FLAG 0x10 /* Hours Event Flag */
2201#define TWENTY_FOUR_HOURS_EVENT_FLAG 0x20 /* 24 Hours Event Flag */
2202#define DAY_ALARM_EVENT_FLAG 0x40 /* Day Alarm Event Flag */
2203#define WRITE_PENDING__STATUS 0x4000 /* Write Pending Status */
2204#define WRITE_COMPLETE 0x8000 /* Write Complete */
2205
2206/* Bit masks for RTC_SWCNT */
2207
2208#define STOPWATCH_COUNT 0xffff /* Stopwatch Count */
2209
2210/* Bit masks for RTC_ALARM */
2211
2212#define SECONDS 0x3f /* Seconds */
2213#define MINUTES 0xfc0 /* Minutes */
2214#define HOURS 0x1f000 /* Hours */
2215#define DAY 0xfffe0000 /* Day */
2216
2217/* Bit masks for RTC_PREN */
2218
2219#define PREN 0x1 /* Prescaler Enable */
2220
2221/* Bit masks for OTP_CONTROL */
2222
2223#define FUSE_FADDR 0x1ff /* OTP/Fuse Address */
2224#define FIEN 0x800 /* OTP/Fuse Interrupt Enable */
2225#define FTESTDEC 0x1000 /* OTP/Fuse Test Decoder */
2226#define FWRTEST 0x2000 /* OTP/Fuse Write Test */
2227#define FRDEN 0x4000 /* OTP/Fuse Read Enable */
2228#define FWREN 0x8000 /* OTP/Fuse Write Enable */
2229
2230/* Bit masks for OTP_BEN */
2231
2232#define FBEN 0xffff /* OTP/Fuse Byte Enable */
2233
2234/* Bit masks for OTP_STATUS */
2235
2236#define FCOMP 0x1 /* OTP/Fuse Access Complete */
2237#define FERROR 0x2 /* OTP/Fuse Access Error */
2238#define MMRGLOAD 0x10 /* Memory Mapped Register Gasket Load */
2239#define MMRGLOCK 0x20 /* Memory Mapped Register Gasket Lock */
2240#define FPGMEN 0x40 /* OTP/Fuse Program Enable */
2241
2242/* Bit masks for OTP_TIMING */
2243
2244#define USECDIV 0xff /* Micro Second Divider */
2245#define READACC 0x7f00 /* Read Access Time */
2246#define CPUMPRL 0x38000 /* Charge Pump Release Time */
2247#define CPUMPSU 0xc0000 /* Charge Pump Setup Time */
2248#define CPUMPHD 0xf00000 /* Charge Pump Hold Time */
2249#define PGMTIME 0xff000000 /* Program Time */
2250
2251/* Bit masks for SECURE_SYSSWT */
2252
2253#define EMUDABL 0x1 /* Emulation Disable. */
2254#define RSTDABL 0x2 /* Reset Disable */
2255#define L1IDABL 0x1c /* L1 Instruction Memory Disable. */
2256#define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */
2257#define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */
2258#define DMA0OVR 0x800 /* DMA0 Memory Access Override */
2259#define DMA1OVR 0x1000 /* DMA1 Memory Access Override */
2260#define EMUOVR 0x4000 /* Emulation Override */
2261#define OTPSEN 0x8000 /* OTP Secrets Enable. */
2262#define L2DABL 0x70000 /* L2 Memory Disable. */
2263
2264/* Bit masks for SECURE_CONTROL */
2265
2266#define SECURE0 0x1 /* SECURE 0 */
2267#define SECURE1 0x2 /* SECURE 1 */
2268#define SECURE2 0x4 /* SECURE 2 */
2269#define SECURE3 0x8 /* SECURE 3 */
2270
2271/* Bit masks for SECURE_STATUS */
2272
2273#define SECMODE 0x3 /* Secured Mode Control State */
2274#define NMI 0x4 /* Non Maskable Interrupt */
2275#define AFVALID 0x8 /* Authentication Firmware Valid */
2276#define AFEXIT 0x10 /* Authentication Firmware Exit */
2277#define SECSTAT 0xe0 /* Secure Status */
2278
2279/* Bit masks for PLL_DIV */
2280
2281#define CSEL 0x30 /* Core Select */
2282#define SSEL 0xf /* System Select */
2283#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
2284#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
2285#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
2286#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
2287
2288/* Bit masks for PLL_CTL */
2289
2290#define MSEL 0x7e00 /* Multiplier Select */
2291#define BYPASS 0x100 /* PLL Bypass Enable */
2292#define OUTPUT_DELAY 0x80 /* External Memory Output Delay Enable */
2293#define INPUT_DELAY 0x40 /* External Memory Input Delay Enable */
2294#define PDWN 0x20 /* Power Down */
2295#define STOPCK 0x8 /* Stop Clock */
2296#define PLL_OFF 0x2 /* Disable PLL */
2297#define DF 0x1 /* Divide Frequency */
2298
2299/* SWRST Masks */
2300#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
2301#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
2302#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
2303#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
2304#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
2305
2306/* Bit masks for PLL_STAT */
2307
2308#define PLL_LOCKED 0x20 /* PLL Locked Status */
2309#define ACTIVE_PLLDISABLED 0x4 /* Active Mode With PLL Disabled */
2310#define FULL_ON 0x2 /* Full-On Mode */
2311#define ACTIVE_PLLENABLED 0x1 /* Active Mode With PLL Enabled */
2312#define RTCWS 0x400 /* RTC/Reset Wake-Up Status */
2313#define CANWS 0x800 /* CAN Wake-Up Status */
2314#define USBWS 0x2000 /* USB Wake-Up Status */
2315#define KPADWS 0x4000 /* Keypad Wake-Up Status */
2316#define ROTWS 0x8000 /* Rotary Wake-Up Status */
2317#define GPWS 0x1000 /* General-Purpose Wake-Up Status */
2318
2319/* Bit masks for VR_CTL */
2320
2321#define FREQ 0x3 /* Regulator Switching Frequency */
2322#define GAIN 0xc /* Voltage Output Level Gain */
2323#define VLEV 0xf0 /* Internal Voltage Level */
2324#define SCKELOW 0x8000 /* Drive SCKE Low During Reset Enable */
2325#define WAKE 0x100 /* RTC/Reset Wake-Up Enable */
2326#define CANWE 0x200 /* CAN0/1 Wake-Up Enable */
2327#define GPWE 0x400 /* General-Purpose Wake-Up Enable */
2328#define USBWE 0x800 /* USB Wake-Up Enable */
2329#define KPADWE 0x1000 /* Keypad Wake-Up Enable */
2330#define ROTWE 0x2000 /* Rotary Wake-Up Enable */
2331
2332#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
2333#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
2334#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
2335
2336#define GAIN_5 0x0000 /* GAIN = 5*/
2337#define GAIN_10 0x0004 /* GAIN = 1*/
2338#define GAIN_20 0x0008 /* GAIN = 2*/
2339#define GAIN_50 0x000C /* GAIN = 5*/
2340
2341#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
2342#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
2343#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
2344#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
2345#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
2346#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
2347#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
2348#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
2349#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */
2350#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
2351
2352/* Bit masks for NFC_CTL */
2353
2354#define WR_DLY 0xf /* Write Strobe Delay */
2355#define RD_DLY 0xf0 /* Read Strobe Delay */
2356#define NWIDTH 0x100 /* NAND Data Width */
2357#define PG_SIZE 0x200 /* Page Size */
2358
2359/* Bit masks for NFC_STAT */
2360
2361#define NBUSY 0x1 /* Not Busy */
2362#define WB_FULL 0x2 /* Write Buffer Full */
2363#define PG_WR_STAT 0x4 /* Page Write Pending */
2364#define PG_RD_STAT 0x8 /* Page Read Pending */
2365#define WB_EMPTY 0x10 /* Write Buffer Empty */
2366
2367/* Bit masks for NFC_IRQSTAT */
2368
2369#define NBUSYIRQ 0x1 /* Not Busy IRQ */
2370#define WB_OVF 0x2 /* Write Buffer Overflow */
2371#define WB_EDGE 0x4 /* Write Buffer Edge Detect */
2372#define RD_RDY 0x8 /* Read Data Ready */
2373#define WR_DONE 0x10 /* Page Write Done */
2374
2375/* Bit masks for NFC_IRQMASK */
2376
2377#define MASK_BUSYIRQ 0x1 /* Mask Not Busy IRQ */
2378#define MASK_WBOVF 0x2 /* Mask Write Buffer Overflow */
2379#define MASK_WBEMPTY 0x4 /* Mask Write Buffer Empty */
2380#define MASK_RDRDY 0x8 /* Mask Read Data Ready */
2381#define MASK_WRDONE 0x10 /* Mask Write Done */
2382
2383/* Bit masks for NFC_RST */
2384
2385#define ECC_RST 0x1 /* ECC (and NFC counters) Reset */
2386
2387/* Bit masks for NFC_PGCTL */
2388
2389#define PG_RD_START 0x1 /* Page Read Start */
2390#define PG_WR_START 0x2 /* Page Write Start */
2391
2392/* Bit masks for NFC_ECC0 */
2393
2394#define ECC0 0x7ff /* Parity Calculation Result0 */
2395
2396/* Bit masks for NFC_ECC1 */
2397
2398#define ECC1 0x7ff /* Parity Calculation Result1 */
2399
2400/* Bit masks for NFC_ECC2 */
2401
2402#define ECC2 0x7ff /* Parity Calculation Result2 */
2403
2404/* Bit masks for NFC_ECC3 */
2405
2406#define ECC3 0x7ff /* Parity Calculation Result3 */
2407
2408/* Bit masks for NFC_COUNT */
2409
2410#define ECCCNT 0x3ff /* Transfer Count */
2411
2412/* Bit masks for CAN0_CONTROL */
2413
2414#define SRS 0x1 /* Software Reset */
2415#define DNM 0x2 /* DeviceNet Mode */
2416#define ABO 0x4 /* Auto Bus On */
2417#define WBA 0x10 /* Wakeup On CAN Bus Activity */
2418#define SMR 0x20 /* Sleep Mode Request */
2419#define CSR 0x40 /* CAN Suspend Mode Request */
2420#define CCR 0x80 /* CAN Configuration Mode Request */
2421
2422/* Bit masks for CAN0_STATUS */
2423
2424#define WT 0x1 /* CAN Transmit Warning Flag */
2425#define WR 0x2 /* CAN Receive Warning Flag */
2426#define EP 0x4 /* CAN Error Passive Mode */
2427#define EBO 0x8 /* CAN Error Bus Off Mode */
2428#define CSA 0x40 /* CAN Suspend Mode Acknowledge */
2429#define CCA 0x80 /* CAN Configuration Mode Acknowledge */
2430#define MBPTR 0x1f00 /* Mailbox Pointer */
2431#define TRM 0x4000 /* Transmit Mode Status */
2432#define REC 0x8000 /* Receive Mode Status */
2433
2434/* Bit masks for CAN0_DEBUG */
2435
2436#define DEC 0x1 /* Disable Transmit/Receive Error Counters */
2437#define DRI 0x2 /* Disable CANRX Input Pin */
2438#define DTO 0x4 /* Disable CANTX Output Pin */
2439#define DIL 0x8 /* Disable Internal Loop */
2440#define MAA 0x10 /* Mode Auto-Acknowledge */
2441#define MRB 0x20 /* Mode Read Back */
2442#define CDE 0x8000 /* CAN Debug Mode Enable */
2443
2444/* Bit masks for CAN0_CLOCK */
2445
2446#define BRP 0x3ff /* CAN Bit Rate Prescaler */
2447
2448/* Bit masks for CAN0_TIMING */
2449
2450#define SJW 0x300 /* Synchronization Jump Width */
2451#define SAM 0x80 /* Sampling */
2452#define TSEG2 0x70 /* Time Segment 2 */
2453#define TSEG1 0xf /* Time Segment 1 */
2454
2455/* Bit masks for CAN0_INTR */
2456
2457#define CANRX 0x80 /* Serial Input From Transceiver */
2458#define CANTX 0x40 /* Serial Output To Transceiver */
2459#define SMACK 0x8 /* Sleep Mode Acknowledge */
2460#define GIRQ 0x4 /* Global Interrupt Request Status */
2461#define MBTIRQ 0x2 /* Mailbox Transmit Interrupt Request */
2462#define MBRIRQ 0x1 /* Mailbox Receive Interrupt Request */
2463
2464/* Bit masks for CAN0_GIM */
2465
2466#define EWTIM 0x1 /* Error Warning Transmit Interrupt Mask */
2467#define EWRIM 0x2 /* Error Warning Receive Interrupt Mask */
2468#define EPIM 0x4 /* Error Passive Interrupt Mask */
2469#define BOIM 0x8 /* Bus Off Interrupt Mask */
2470#define WUIM 0x10 /* Wakeup Interrupt Mask */
2471#define UIAIM 0x20 /* Unimplemented Address Interrupt Mask */
2472#define AAIM 0x40 /* Abort Acknowledge Interrupt Mask */
2473#define RMLIM 0x80 /* Receive Message Lost Interrupt Mask */
2474#define UCEIM 0x100 /* Universal Counter Exceeded Interrupt Mask */
2475#define ADIM 0x400 /* Access Denied Interrupt Mask */
2476
2477/* Bit masks for CAN0_GIS */
2478
2479#define EWTIS 0x1 /* Error Warning Transmit Interrupt Status */
2480#define EWRIS 0x2 /* Error Warning Receive Interrupt Status */
2481#define EPIS 0x4 /* Error Passive Interrupt Status */
2482#define BOIS 0x8 /* Bus Off Interrupt Status */
2483#define WUIS 0x10 /* Wakeup Interrupt Status */
2484#define UIAIS 0x20 /* Unimplemented Address Interrupt Status */
2485#define AAIS 0x40 /* Abort Acknowledge Interrupt Status */
2486#define RMLIS 0x80 /* Receive Message Lost Interrupt Status */
2487#define UCEIS 0x100 /* Universal Counter Exceeded Interrupt Status */
2488#define ADIS 0x400 /* Access Denied Interrupt Status */
2489
2490/* Bit masks for CAN0_GIF */
2491
2492#define EWTIF 0x1 /* Error Warning Transmit Interrupt Flag */
2493#define EWRIF 0x2 /* Error Warning Receive Interrupt Flag */
2494#define EPIF 0x4 /* Error Passive Interrupt Flag */
2495#define BOIF 0x8 /* Bus Off Interrupt Flag */
2496#define WUIF 0x10 /* Wakeup Interrupt Flag */
2497#define UIAIF 0x20 /* Unimplemented Address Interrupt Flag */
2498#define AAIF 0x40 /* Abort Acknowledge Interrupt Flag */
2499#define RMLIF 0x80 /* Receive Message Lost Interrupt Flag */
2500#define UCEIF 0x100 /* Universal Counter Exceeded Interrupt Flag */
2501#define ADIF 0x400 /* Access Denied Interrupt Flag */
2502
2503/* Bit masks for CAN0_MBTD */
2504
2505#define TDR 0x80 /* Temporary Disable Request */
2506#define TDA 0x40 /* Temporary Disable Acknowledge */
2507#define TDPTR 0x1f /* Temporary Disable Pointer */
2508
2509/* Bit masks for CAN0_UCCNF */
2510
2511#define UCCNF 0xf /* Universal Counter Configuration */
2512#define UCRC 0x20 /* Universal Counter Reload/Clear */
2513#define UCCT 0x40 /* Universal Counter CAN Trigger */
2514#define UCE 0x80 /* Universal Counter Enable */
2515
2516/* Bit masks for CAN0_UCCNT */
2517
2518#define UCCNT 0xffff /* Universal Counter Count Value */
2519
2520/* Bit masks for CAN0_UCRC */
2521
2522#define UCVAL 0xffff /* Universal Counter Reload/Capture Value */
2523
2524/* Bit masks for CAN0_CEC */
2525
2526#define RXECNT 0xff /* Receive Error Counter */
2527#define TXECNT 0xff00 /* Transmit Error Counter */
2528
2529/* Bit masks for CAN0_ESR */
2530
2531#define FER 0x80 /* Form Error */
2532#define BEF 0x40 /* Bit Error Flag */
2533#define SA0 0x20 /* Stuck At Dominant */
2534#define CRCE 0x10 /* CRC Error */
2535#define SER 0x8 /* Stuff Bit Error */
2536#define ACKE 0x4 /* Acknowledge Error */
2537
2538/* Bit masks for CAN0_EWR */
2539
2540#define EWLTEC 0xff00 /* Transmit Error Warning Limit */
2541#define EWLREC 0xff /* Receive Error Warning Limit */
2542
2543/* Bit masks for CAN0_AMxx_H */
2544
2545#define FDF 0x8000 /* Filter On Data Field */
2546#define FMD 0x4000 /* Full Mask Data */
2547#define AMIDE 0x2000 /* Acceptance Mask Identifier Extension */
2548#define BASEID 0x1ffc /* Base Identifier */
2549#define EXTID_HI 0x3 /* Extended Identifier High Bits */
2550
2551/* Bit masks for CAN0_AMxx_L */
2552
2553#define EXTID_LO 0xffff /* Extended Identifier Low Bits */
2554#define DFM 0xffff /* Data Field Mask */
2555
2556/* Bit masks for CAN0_MBxx_ID1 */
2557
2558#define AME 0x8000 /* Acceptance Mask Enable */
2559#define RTR 0x4000 /* Remote Transmission Request */
2560#define IDE 0x2000 /* Identifier Extension */
2561#define BASEID 0x1ffc /* Base Identifier */
2562#define EXTID_HI 0x3 /* Extended Identifier High Bits */
2563
2564/* Bit masks for CAN0_MBxx_ID0 */
2565
2566#define EXTID_LO 0xffff /* Extended Identifier Low Bits */
2567#define DFM 0xffff /* Data Field Mask */
2568
2569/* Bit masks for CAN0_MBxx_TIMESTAMP */
2570
2571#define TSV 0xffff /* Time Stamp Value */
2572
2573/* Bit masks for CAN0_MBxx_LENGTH */
2574
2575#define DLC 0xf /* Data Length Code */
2576
2577/* Bit masks for CAN0_MBxx_DATA3 */
2578
2579#define CAN_BYTE0 0xff00 /* Data Field Byte 0 */
2580#define CAN_BYTE1 0xff /* Data Field Byte 1 */
2581
2582/* Bit masks for CAN0_MBxx_DATA2 */
2583
2584#define CAN_BYTE2 0xff00 /* Data Field Byte 2 */
2585#define CAN_BYTE3 0xff /* Data Field Byte 3 */
2586
2587/* Bit masks for CAN0_MBxx_DATA1 */
2588
2589#define CAN_BYTE4 0xff00 /* Data Field Byte 4 */
2590#define CAN_BYTE5 0xff /* Data Field Byte 5 */
2591
2592/* Bit masks for CAN0_MBxx_DATA0 */
2593
2594#define CAN_BYTE6 0xff00 /* Data Field Byte 6 */
2595#define CAN_BYTE7 0xff /* Data Field Byte 7 */
2596
2597/* Bit masks for CAN0_MC1 */
2598
2599#define MC0 0x1 /* Mailbox 0 Enable */
2600#define MC1 0x2 /* Mailbox 1 Enable */
2601#define MC2 0x4 /* Mailbox 2 Enable */
2602#define MC3 0x8 /* Mailbox 3 Enable */
2603#define MC4 0x10 /* Mailbox 4 Enable */
2604#define MC5 0x20 /* Mailbox 5 Enable */
2605#define MC6 0x40 /* Mailbox 6 Enable */
2606#define MC7 0x80 /* Mailbox 7 Enable */
2607#define MC8 0x100 /* Mailbox 8 Enable */
2608#define MC9 0x200 /* Mailbox 9 Enable */
2609#define MC10 0x400 /* Mailbox 10 Enable */
2610#define MC11 0x800 /* Mailbox 11 Enable */
2611#define MC12 0x1000 /* Mailbox 12 Enable */
2612#define MC13 0x2000 /* Mailbox 13 Enable */
2613#define MC14 0x4000 /* Mailbox 14 Enable */
2614#define MC15 0x8000 /* Mailbox 15 Enable */
2615
2616/* Bit masks for CAN0_MC2 */
2617
2618#define MC16 0x1 /* Mailbox 16 Enable */
2619#define MC17 0x2 /* Mailbox 17 Enable */
2620#define MC18 0x4 /* Mailbox 18 Enable */
2621#define MC19 0x8 /* Mailbox 19 Enable */
2622#define MC20 0x10 /* Mailbox 20 Enable */
2623#define MC21 0x20 /* Mailbox 21 Enable */
2624#define MC22 0x40 /* Mailbox 22 Enable */
2625#define MC23 0x80 /* Mailbox 23 Enable */
2626#define MC24 0x100 /* Mailbox 24 Enable */
2627#define MC25 0x200 /* Mailbox 25 Enable */
2628#define MC26 0x400 /* Mailbox 26 Enable */
2629#define MC27 0x800 /* Mailbox 27 Enable */
2630#define MC28 0x1000 /* Mailbox 28 Enable */
2631#define MC29 0x2000 /* Mailbox 29 Enable */
2632#define MC30 0x4000 /* Mailbox 30 Enable */
2633#define MC31 0x8000 /* Mailbox 31 Enable */
2634
2635/* Bit masks for CAN0_MD1 */
2636
2637#define MD0 0x1 /* Mailbox 0 Receive Enable */
2638#define MD1 0x2 /* Mailbox 1 Receive Enable */
2639#define MD2 0x4 /* Mailbox 2 Receive Enable */
2640#define MD3 0x8 /* Mailbox 3 Receive Enable */
2641#define MD4 0x10 /* Mailbox 4 Receive Enable */
2642#define MD5 0x20 /* Mailbox 5 Receive Enable */
2643#define MD6 0x40 /* Mailbox 6 Receive Enable */
2644#define MD7 0x80 /* Mailbox 7 Receive Enable */
2645#define MD8 0x100 /* Mailbox 8 Receive Enable */
2646#define MD9 0x200 /* Mailbox 9 Receive Enable */
2647#define MD10 0x400 /* Mailbox 10 Receive Enable */
2648#define MD11 0x800 /* Mailbox 11 Receive Enable */
2649#define MD12 0x1000 /* Mailbox 12 Receive Enable */
2650#define MD13 0x2000 /* Mailbox 13 Receive Enable */
2651#define MD14 0x4000 /* Mailbox 14 Receive Enable */
2652#define MD15 0x8000 /* Mailbox 15 Receive Enable */
2653
2654/* Bit masks for CAN0_MD2 */
2655
2656#define MD16 0x1 /* Mailbox 16 Receive Enable */
2657#define MD17 0x2 /* Mailbox 17 Receive Enable */
2658#define MD18 0x4 /* Mailbox 18 Receive Enable */
2659#define MD19 0x8 /* Mailbox 19 Receive Enable */
2660#define MD20 0x10 /* Mailbox 20 Receive Enable */
2661#define MD21 0x20 /* Mailbox 21 Receive Enable */
2662#define MD22 0x40 /* Mailbox 22 Receive Enable */
2663#define MD23 0x80 /* Mailbox 23 Receive Enable */
2664#define MD24 0x100 /* Mailbox 24 Receive Enable */
2665#define MD25 0x200 /* Mailbox 25 Receive Enable */
2666#define MD26 0x400 /* Mailbox 26 Receive Enable */
2667#define MD27 0x800 /* Mailbox 27 Receive Enable */
2668#define MD28 0x1000 /* Mailbox 28 Receive Enable */
2669#define MD29 0x2000 /* Mailbox 29 Receive Enable */
2670#define MD30 0x4000 /* Mailbox 30 Receive Enable */
2671#define MD31 0x8000 /* Mailbox 31 Receive Enable */
2672
2673/* Bit masks for CAN0_RMP1 */
2674
2675#define RMP0 0x1 /* Mailbox 0 Receive Message Pending */
2676#define RMP1 0x2 /* Mailbox 1 Receive Message Pending */
2677#define RMP2 0x4 /* Mailbox 2 Receive Message Pending */
2678#define RMP3 0x8 /* Mailbox 3 Receive Message Pending */
2679#define RMP4 0x10 /* Mailbox 4 Receive Message Pending */
2680#define RMP5 0x20 /* Mailbox 5 Receive Message Pending */
2681#define RMP6 0x40 /* Mailbox 6 Receive Message Pending */
2682#define RMP7 0x80 /* Mailbox 7 Receive Message Pending */
2683#define RMP8 0x100 /* Mailbox 8 Receive Message Pending */
2684#define RMP9 0x200 /* Mailbox 9 Receive Message Pending */
2685#define RMP10 0x400 /* Mailbox 10 Receive Message Pending */
2686#define RMP11 0x800 /* Mailbox 11 Receive Message Pending */
2687#define RMP12 0x1000 /* Mailbox 12 Receive Message Pending */
2688#define RMP13 0x2000 /* Mailbox 13 Receive Message Pending */
2689#define RMP14 0x4000 /* Mailbox 14 Receive Message Pending */
2690#define RMP15 0x8000 /* Mailbox 15 Receive Message Pending */
2691
2692/* Bit masks for CAN0_RMP2 */
2693
2694#define RMP16 0x1 /* Mailbox 16 Receive Message Pending */
2695#define RMP17 0x2 /* Mailbox 17 Receive Message Pending */
2696#define RMP18 0x4 /* Mailbox 18 Receive Message Pending */
2697#define RMP19 0x8 /* Mailbox 19 Receive Message Pending */
2698#define RMP20 0x10 /* Mailbox 20 Receive Message Pending */
2699#define RMP21 0x20 /* Mailbox 21 Receive Message Pending */
2700#define RMP22 0x40 /* Mailbox 22 Receive Message Pending */
2701#define RMP23 0x80 /* Mailbox 23 Receive Message Pending */
2702#define RMP24 0x100 /* Mailbox 24 Receive Message Pending */
2703#define RMP25 0x200 /* Mailbox 25 Receive Message Pending */
2704#define RMP26 0x400 /* Mailbox 26 Receive Message Pending */
2705#define RMP27 0x800 /* Mailbox 27 Receive Message Pending */
2706#define RMP28 0x1000 /* Mailbox 28 Receive Message Pending */
2707#define RMP29 0x2000 /* Mailbox 29 Receive Message Pending */
2708#define RMP30 0x4000 /* Mailbox 30 Receive Message Pending */
2709#define RMP31 0x8000 /* Mailbox 31 Receive Message Pending */
2710
2711/* Bit masks for CAN0_RML1 */
2712
2713#define RML0 0x1 /* Mailbox 0 Receive Message Lost */
2714#define RML1 0x2 /* Mailbox 1 Receive Message Lost */
2715#define RML2 0x4 /* Mailbox 2 Receive Message Lost */
2716#define RML3 0x8 /* Mailbox 3 Receive Message Lost */
2717#define RML4 0x10 /* Mailbox 4 Receive Message Lost */
2718#define RML5 0x20 /* Mailbox 5 Receive Message Lost */
2719#define RML6 0x40 /* Mailbox 6 Receive Message Lost */
2720#define RML7 0x80 /* Mailbox 7 Receive Message Lost */
2721#define RML8 0x100 /* Mailbox 8 Receive Message Lost */
2722#define RML9 0x200 /* Mailbox 9 Receive Message Lost */
2723#define RML10 0x400 /* Mailbox 10 Receive Message Lost */
2724#define RML11 0x800 /* Mailbox 11 Receive Message Lost */
2725#define RML12 0x1000 /* Mailbox 12 Receive Message Lost */
2726#define RML13 0x2000 /* Mailbox 13 Receive Message Lost */
2727#define RML14 0x4000 /* Mailbox 14 Receive Message Lost */
2728#define RML15 0x8000 /* Mailbox 15 Receive Message Lost */
2729
2730/* Bit masks for CAN0_RML2 */
2731
2732#define RML16 0x1 /* Mailbox 16 Receive Message Lost */
2733#define RML17 0x2 /* Mailbox 17 Receive Message Lost */
2734#define RML18 0x4 /* Mailbox 18 Receive Message Lost */
2735#define RML19 0x8 /* Mailbox 19 Receive Message Lost */
2736#define RML20 0x10 /* Mailbox 20 Receive Message Lost */
2737#define RML21 0x20 /* Mailbox 21 Receive Message Lost */
2738#define RML22 0x40 /* Mailbox 22 Receive Message Lost */
2739#define RML23 0x80 /* Mailbox 23 Receive Message Lost */
2740#define RML24 0x100 /* Mailbox 24 Receive Message Lost */
2741#define RML25 0x200 /* Mailbox 25 Receive Message Lost */
2742#define RML26 0x400 /* Mailbox 26 Receive Message Lost */
2743#define RML27 0x800 /* Mailbox 27 Receive Message Lost */
2744#define RML28 0x1000 /* Mailbox 28 Receive Message Lost */
2745#define RML29 0x2000 /* Mailbox 29 Receive Message Lost */
2746#define RML30 0x4000 /* Mailbox 30 Receive Message Lost */
2747#define RML31 0x8000 /* Mailbox 31 Receive Message Lost */
2748
2749/* Bit masks for CAN0_OPSS1 */
2750
2751#define OPSS0 0x1 /* Mailbox 0 Overwrite Protection/Single-Shot Transmission Enable */
2752#define OPSS1 0x2 /* Mailbox 1 Overwrite Protection/Single-Shot Transmission Enable */
2753#define OPSS2 0x4 /* Mailbox 2 Overwrite Protection/Single-Shot Transmission Enable */
2754#define OPSS3 0x8 /* Mailbox 3 Overwrite Protection/Single-Shot Transmission Enable */
2755#define OPSS4 0x10 /* Mailbox 4 Overwrite Protection/Single-Shot Transmission Enable */
2756#define OPSS5 0x20 /* Mailbox 5 Overwrite Protection/Single-Shot Transmission Enable */
2757#define OPSS6 0x40 /* Mailbox 6 Overwrite Protection/Single-Shot Transmission Enable */
2758#define OPSS7 0x80 /* Mailbox 7 Overwrite Protection/Single-Shot Transmission Enable */
2759#define OPSS8 0x100 /* Mailbox 8 Overwrite Protection/Single-Shot Transmission Enable */
2760#define OPSS9 0x200 /* Mailbox 9 Overwrite Protection/Single-Shot Transmission Enable */
2761#define OPSS10 0x400 /* Mailbox 10 Overwrite Protection/Single-Shot Transmission Enable */
2762#define OPSS11 0x800 /* Mailbox 11 Overwrite Protection/Single-Shot Transmission Enable */
2763#define OPSS12 0x1000 /* Mailbox 12 Overwrite Protection/Single-Shot Transmission Enable */
2764#define OPSS13 0x2000 /* Mailbox 13 Overwrite Protection/Single-Shot Transmission Enable */
2765#define OPSS14 0x4000 /* Mailbox 14 Overwrite Protection/Single-Shot Transmission Enable */
2766#define OPSS15 0x8000 /* Mailbox 15 Overwrite Protection/Single-Shot Transmission Enable */
2767
2768/* Bit masks for CAN0_OPSS2 */
2769
2770#define OPSS16 0x1 /* Mailbox 16 Overwrite Protection/Single-Shot Transmission Enable */
2771#define OPSS17 0x2 /* Mailbox 17 Overwrite Protection/Single-Shot Transmission Enable */
2772#define OPSS18 0x4 /* Mailbox 18 Overwrite Protection/Single-Shot Transmission Enable */
2773#define OPSS19 0x8 /* Mailbox 19 Overwrite Protection/Single-Shot Transmission Enable */
2774#define OPSS20 0x10 /* Mailbox 20 Overwrite Protection/Single-Shot Transmission Enable */
2775#define OPSS21 0x20 /* Mailbox 21 Overwrite Protection/Single-Shot Transmission Enable */
2776#define OPSS22 0x40 /* Mailbox 22 Overwrite Protection/Single-Shot Transmission Enable */
2777#define OPSS23 0x80 /* Mailbox 23 Overwrite Protection/Single-Shot Transmission Enable */
2778#define OPSS24 0x100 /* Mailbox 24 Overwrite Protection/Single-Shot Transmission Enable */
2779#define OPSS25 0x200 /* Mailbox 25 Overwrite Protection/Single-Shot Transmission Enable */
2780#define OPSS26 0x400 /* Mailbox 26 Overwrite Protection/Single-Shot Transmission Enable */
2781#define OPSS27 0x800 /* Mailbox 27 Overwrite Protection/Single-Shot Transmission Enable */
2782#define OPSS28 0x1000 /* Mailbox 28 Overwrite Protection/Single-Shot Transmission Enable */
2783#define OPSS29 0x2000 /* Mailbox 29 Overwrite Protection/Single-Shot Transmission Enable */
2784#define OPSS30 0x4000 /* Mailbox 30 Overwrite Protection/Single-Shot Transmission Enable */
2785#define OPSS31 0x8000 /* Mailbox 31 Overwrite Protection/Single-Shot Transmission Enable */
2786
2787/* Bit masks for CAN0_TRS1 */
2788
2789#define TRS0 0x1 /* Mailbox 0 Transmit Request Set */
2790#define TRS1 0x2 /* Mailbox 1 Transmit Request Set */
2791#define TRS2 0x4 /* Mailbox 2 Transmit Request Set */
2792#define TRS3 0x8 /* Mailbox 3 Transmit Request Set */
2793#define TRS4 0x10 /* Mailbox 4 Transmit Request Set */
2794#define TRS5 0x20 /* Mailbox 5 Transmit Request Set */
2795#define TRS6 0x40 /* Mailbox 6 Transmit Request Set */
2796#define TRS7 0x80 /* Mailbox 7 Transmit Request Set */
2797#define TRS8 0x100 /* Mailbox 8 Transmit Request Set */
2798#define TRS9 0x200 /* Mailbox 9 Transmit Request Set */
2799#define TRS10 0x400 /* Mailbox 10 Transmit Request Set */
2800#define TRS11 0x800 /* Mailbox 11 Transmit Request Set */
2801#define TRS12 0x1000 /* Mailbox 12 Transmit Request Set */
2802#define TRS13 0x2000 /* Mailbox 13 Transmit Request Set */
2803#define TRS14 0x4000 /* Mailbox 14 Transmit Request Set */
2804#define TRS15 0x8000 /* Mailbox 15 Transmit Request Set */
2805
2806/* Bit masks for CAN0_TRS2 */
2807
2808#define TRS16 0x1 /* Mailbox 16 Transmit Request Set */
2809#define TRS17 0x2 /* Mailbox 17 Transmit Request Set */
2810#define TRS18 0x4 /* Mailbox 18 Transmit Request Set */
2811#define TRS19 0x8 /* Mailbox 19 Transmit Request Set */
2812#define TRS20 0x10 /* Mailbox 20 Transmit Request Set */
2813#define TRS21 0x20 /* Mailbox 21 Transmit Request Set */
2814#define TRS22 0x40 /* Mailbox 22 Transmit Request Set */
2815#define TRS23 0x80 /* Mailbox 23 Transmit Request Set */
2816#define TRS24 0x100 /* Mailbox 24 Transmit Request Set */
2817#define TRS25 0x200 /* Mailbox 25 Transmit Request Set */
2818#define TRS26 0x400 /* Mailbox 26 Transmit Request Set */
2819#define TRS27 0x800 /* Mailbox 27 Transmit Request Set */
2820#define TRS28 0x1000 /* Mailbox 28 Transmit Request Set */
2821#define TRS29 0x2000 /* Mailbox 29 Transmit Request Set */
2822#define TRS30 0x4000 /* Mailbox 30 Transmit Request Set */
2823#define TRS31 0x8000 /* Mailbox 31 Transmit Request Set */
2824
2825/* Bit masks for CAN0_TRR1 */
2826
2827#define TRR0 0x1 /* Mailbox 0 Transmit Request Reset */
2828#define TRR1 0x2 /* Mailbox 1 Transmit Request Reset */
2829#define TRR2 0x4 /* Mailbox 2 Transmit Request Reset */
2830#define TRR3 0x8 /* Mailbox 3 Transmit Request Reset */
2831#define TRR4 0x10 /* Mailbox 4 Transmit Request Reset */
2832#define TRR5 0x20 /* Mailbox 5 Transmit Request Reset */
2833#define TRR6 0x40 /* Mailbox 6 Transmit Request Reset */
2834#define TRR7 0x80 /* Mailbox 7 Transmit Request Reset */
2835#define TRR8 0x100 /* Mailbox 8 Transmit Request Reset */
2836#define TRR9 0x200 /* Mailbox 9 Transmit Request Reset */
2837#define TRR10 0x400 /* Mailbox 10 Transmit Request Reset */
2838#define TRR11 0x800 /* Mailbox 11 Transmit Request Reset */
2839#define TRR12 0x1000 /* Mailbox 12 Transmit Request Reset */
2840#define TRR13 0x2000 /* Mailbox 13 Transmit Request Reset */
2841#define TRR14 0x4000 /* Mailbox 14 Transmit Request Reset */
2842#define TRR15 0x8000 /* Mailbox 15 Transmit Request Reset */
2843
2844/* Bit masks for CAN0_TRR2 */
2845
2846#define TRR16 0x1 /* Mailbox 16 Transmit Request Reset */
2847#define TRR17 0x2 /* Mailbox 17 Transmit Request Reset */
2848#define TRR18 0x4 /* Mailbox 18 Transmit Request Reset */
2849#define TRR19 0x8 /* Mailbox 19 Transmit Request Reset */
2850#define TRR20 0x10 /* Mailbox 20 Transmit Request Reset */
2851#define TRR21 0x20 /* Mailbox 21 Transmit Request Reset */
2852#define TRR22 0x40 /* Mailbox 22 Transmit Request Reset */
2853#define TRR23 0x80 /* Mailbox 23 Transmit Request Reset */
2854#define TRR24 0x100 /* Mailbox 24 Transmit Request Reset */
2855#define TRR25 0x200 /* Mailbox 25 Transmit Request Reset */
2856#define TRR26 0x400 /* Mailbox 26 Transmit Request Reset */
2857#define TRR27 0x800 /* Mailbox 27 Transmit Request Reset */
2858#define TRR28 0x1000 /* Mailbox 28 Transmit Request Reset */
2859#define TRR29 0x2000 /* Mailbox 29 Transmit Request Reset */
2860#define TRR30 0x4000 /* Mailbox 30 Transmit Request Reset */
2861#define TRR31 0x8000 /* Mailbox 31 Transmit Request Reset */
2862
2863/* Bit masks for CAN0_AA1 */
2864
2865#define AA0 0x1 /* Mailbox 0 Abort Acknowledge */
2866#define AA1 0x2 /* Mailbox 1 Abort Acknowledge */
2867#define AA2 0x4 /* Mailbox 2 Abort Acknowledge */
2868#define AA3 0x8 /* Mailbox 3 Abort Acknowledge */
2869#define AA4 0x10 /* Mailbox 4 Abort Acknowledge */
2870#define AA5 0x20 /* Mailbox 5 Abort Acknowledge */
2871#define AA6 0x40 /* Mailbox 6 Abort Acknowledge */
2872#define AA7 0x80 /* Mailbox 7 Abort Acknowledge */
2873#define AA8 0x100 /* Mailbox 8 Abort Acknowledge */
2874#define AA9 0x200 /* Mailbox 9 Abort Acknowledge */
2875#define AA10 0x400 /* Mailbox 10 Abort Acknowledge */
2876#define AA11 0x800 /* Mailbox 11 Abort Acknowledge */
2877#define AA12 0x1000 /* Mailbox 12 Abort Acknowledge */
2878#define AA13 0x2000 /* Mailbox 13 Abort Acknowledge */
2879#define AA14 0x4000 /* Mailbox 14 Abort Acknowledge */
2880#define AA15 0x8000 /* Mailbox 15 Abort Acknowledge */
2881
2882/* Bit masks for CAN0_AA2 */
2883
2884#define AA16 0x1 /* Mailbox 16 Abort Acknowledge */
2885#define AA17 0x2 /* Mailbox 17 Abort Acknowledge */
2886#define AA18 0x4 /* Mailbox 18 Abort Acknowledge */
2887#define AA19 0x8 /* Mailbox 19 Abort Acknowledge */
2888#define AA20 0x10 /* Mailbox 20 Abort Acknowledge */
2889#define AA21 0x20 /* Mailbox 21 Abort Acknowledge */
2890#define AA22 0x40 /* Mailbox 22 Abort Acknowledge */
2891#define AA23 0x80 /* Mailbox 23 Abort Acknowledge */
2892#define AA24 0x100 /* Mailbox 24 Abort Acknowledge */
2893#define AA25 0x200 /* Mailbox 25 Abort Acknowledge */
2894#define AA26 0x400 /* Mailbox 26 Abort Acknowledge */
2895#define AA27 0x800 /* Mailbox 27 Abort Acknowledge */
2896#define AA28 0x1000 /* Mailbox 28 Abort Acknowledge */
2897#define AA29 0x2000 /* Mailbox 29 Abort Acknowledge */
2898#define AA30 0x4000 /* Mailbox 30 Abort Acknowledge */
2899#define AA31 0x8000 /* Mailbox 31 Abort Acknowledge */
2900
2901/* Bit masks for CAN0_TA1 */
2902
2903#define TA0 0x1 /* Mailbox 0 Transmit Acknowledge */
2904#define TA1 0x2 /* Mailbox 1 Transmit Acknowledge */
2905#define TA2 0x4 /* Mailbox 2 Transmit Acknowledge */
2906#define TA3 0x8 /* Mailbox 3 Transmit Acknowledge */
2907#define TA4 0x10 /* Mailbox 4 Transmit Acknowledge */
2908#define TA5 0x20 /* Mailbox 5 Transmit Acknowledge */
2909#define TA6 0x40 /* Mailbox 6 Transmit Acknowledge */
2910#define TA7 0x80 /* Mailbox 7 Transmit Acknowledge */
2911#define TA8 0x100 /* Mailbox 8 Transmit Acknowledge */
2912#define TA9 0x200 /* Mailbox 9 Transmit Acknowledge */
2913#define TA10 0x400 /* Mailbox 10 Transmit Acknowledge */
2914#define TA11 0x800 /* Mailbox 11 Transmit Acknowledge */
2915#define TA12 0x1000 /* Mailbox 12 Transmit Acknowledge */
2916#define TA13 0x2000 /* Mailbox 13 Transmit Acknowledge */
2917#define TA14 0x4000 /* Mailbox 14 Transmit Acknowledge */
2918#define TA15 0x8000 /* Mailbox 15 Transmit Acknowledge */
2919
2920/* Bit masks for CAN0_TA2 */
2921
2922#define TA16 0x1 /* Mailbox 16 Transmit Acknowledge */
2923#define TA17 0x2 /* Mailbox 17 Transmit Acknowledge */
2924#define TA18 0x4 /* Mailbox 18 Transmit Acknowledge */
2925#define TA19 0x8 /* Mailbox 19 Transmit Acknowledge */
2926#define TA20 0x10 /* Mailbox 20 Transmit Acknowledge */
2927#define TA21 0x20 /* Mailbox 21 Transmit Acknowledge */
2928#define TA22 0x40 /* Mailbox 22 Transmit Acknowledge */
2929#define TA23 0x80 /* Mailbox 23 Transmit Acknowledge */
2930#define TA24 0x100 /* Mailbox 24 Transmit Acknowledge */
2931#define TA25 0x200 /* Mailbox 25 Transmit Acknowledge */
2932#define TA26 0x400 /* Mailbox 26 Transmit Acknowledge */
2933#define TA27 0x800 /* Mailbox 27 Transmit Acknowledge */
2934#define TA28 0x1000 /* Mailbox 28 Transmit Acknowledge */
2935#define TA29 0x2000 /* Mailbox 29 Transmit Acknowledge */
2936#define TA30 0x4000 /* Mailbox 30 Transmit Acknowledge */
2937#define TA31 0x8000 /* Mailbox 31 Transmit Acknowledge */
2938
2939/* Bit masks for CAN0_RFH1 */
2940
2941#define RFH0 0x1 /* Mailbox 0 Remote Frame Handling Enable */
2942#define RFH1 0x2 /* Mailbox 1 Remote Frame Handling Enable */
2943#define RFH2 0x4 /* Mailbox 2 Remote Frame Handling Enable */
2944#define RFH3 0x8 /* Mailbox 3 Remote Frame Handling Enable */
2945#define RFH4 0x10 /* Mailbox 4 Remote Frame Handling Enable */
2946#define RFH5 0x20 /* Mailbox 5 Remote Frame Handling Enable */
2947#define RFH6 0x40 /* Mailbox 6 Remote Frame Handling Enable */
2948#define RFH7 0x80 /* Mailbox 7 Remote Frame Handling Enable */
2949#define RFH8 0x100 /* Mailbox 8 Remote Frame Handling Enable */
2950#define RFH9 0x200 /* Mailbox 9 Remote Frame Handling Enable */
2951#define RFH10 0x400 /* Mailbox 10 Remote Frame Handling Enable */
2952#define RFH11 0x800 /* Mailbox 11 Remote Frame Handling Enable */
2953#define RFH12 0x1000 /* Mailbox 12 Remote Frame Handling Enable */
2954#define RFH13 0x2000 /* Mailbox 13 Remote Frame Handling Enable */
2955#define RFH14 0x4000 /* Mailbox 14 Remote Frame Handling Enable */
2956#define RFH15 0x8000 /* Mailbox 15 Remote Frame Handling Enable */
2957
2958/* Bit masks for CAN0_RFH2 */
2959
2960#define RFH16 0x1 /* Mailbox 16 Remote Frame Handling Enable */
2961#define RFH17 0x2 /* Mailbox 17 Remote Frame Handling Enable */
2962#define RFH18 0x4 /* Mailbox 18 Remote Frame Handling Enable */
2963#define RFH19 0x8 /* Mailbox 19 Remote Frame Handling Enable */
2964#define RFH20 0x10 /* Mailbox 20 Remote Frame Handling Enable */
2965#define RFH21 0x20 /* Mailbox 21 Remote Frame Handling Enable */
2966#define RFH22 0x40 /* Mailbox 22 Remote Frame Handling Enable */
2967#define RFH23 0x80 /* Mailbox 23 Remote Frame Handling Enable */
2968#define RFH24 0x100 /* Mailbox 24 Remote Frame Handling Enable */
2969#define RFH25 0x200 /* Mailbox 25 Remote Frame Handling Enable */
2970#define RFH26 0x400 /* Mailbox 26 Remote Frame Handling Enable */
2971#define RFH27 0x800 /* Mailbox 27 Remote Frame Handling Enable */
2972#define RFH28 0x1000 /* Mailbox 28 Remote Frame Handling Enable */
2973#define RFH29 0x2000 /* Mailbox 29 Remote Frame Handling Enable */
2974#define RFH30 0x4000 /* Mailbox 30 Remote Frame Handling Enable */
2975#define RFH31 0x8000 /* Mailbox 31 Remote Frame Handling Enable */
2976
2977/* Bit masks for CAN0_MBIM1 */
2978
2979#define MBIM0 0x1 /* Mailbox 0 Mailbox Interrupt Mask */
2980#define MBIM1 0x2 /* Mailbox 1 Mailbox Interrupt Mask */
2981#define MBIM2 0x4 /* Mailbox 2 Mailbox Interrupt Mask */
2982#define MBIM3 0x8 /* Mailbox 3 Mailbox Interrupt Mask */
2983#define MBIM4 0x10 /* Mailbox 4 Mailbox Interrupt Mask */
2984#define MBIM5 0x20 /* Mailbox 5 Mailbox Interrupt Mask */
2985#define MBIM6 0x40 /* Mailbox 6 Mailbox Interrupt Mask */
2986#define MBIM7 0x80 /* Mailbox 7 Mailbox Interrupt Mask */
2987#define MBIM8 0x100 /* Mailbox 8 Mailbox Interrupt Mask */
2988#define MBIM9 0x200 /* Mailbox 9 Mailbox Interrupt Mask */
2989#define MBIM10 0x400 /* Mailbox 10 Mailbox Interrupt Mask */
2990#define MBIM11 0x800 /* Mailbox 11 Mailbox Interrupt Mask */
2991#define MBIM12 0x1000 /* Mailbox 12 Mailbox Interrupt Mask */
2992#define MBIM13 0x2000 /* Mailbox 13 Mailbox Interrupt Mask */
2993#define MBIM14 0x4000 /* Mailbox 14 Mailbox Interrupt Mask */
2994#define MBIM15 0x8000 /* Mailbox 15 Mailbox Interrupt Mask */
2995
2996/* Bit masks for CAN0_MBIM2 */
2997
2998#define MBIM16 0x1 /* Mailbox 16 Mailbox Interrupt Mask */
2999#define MBIM17 0x2 /* Mailbox 17 Mailbox Interrupt Mask */
3000#define MBIM18 0x4 /* Mailbox 18 Mailbox Interrupt Mask */
3001#define MBIM19 0x8 /* Mailbox 19 Mailbox Interrupt Mask */
3002#define MBIM20 0x10 /* Mailbox 20 Mailbox Interrupt Mask */
3003#define MBIM21 0x20 /* Mailbox 21 Mailbox Interrupt Mask */
3004#define MBIM22 0x40 /* Mailbox 22 Mailbox Interrupt Mask */
3005#define MBIM23 0x80 /* Mailbox 23 Mailbox Interrupt Mask */
3006#define MBIM24 0x100 /* Mailbox 24 Mailbox Interrupt Mask */
3007#define MBIM25 0x200 /* Mailbox 25 Mailbox Interrupt Mask */
3008#define MBIM26 0x400 /* Mailbox 26 Mailbox Interrupt Mask */
3009#define MBIM27 0x800 /* Mailbox 27 Mailbox Interrupt Mask */
3010#define MBIM28 0x1000 /* Mailbox 28 Mailbox Interrupt Mask */
3011#define MBIM29 0x2000 /* Mailbox 29 Mailbox Interrupt Mask */
3012#define MBIM30 0x4000 /* Mailbox 30 Mailbox Interrupt Mask */
3013#define MBIM31 0x8000 /* Mailbox 31 Mailbox Interrupt Mask */
3014
3015/* Bit masks for CAN0_MBTIF1 */
3016
3017#define MBTIF0 0x1 /* Mailbox 0 Mailbox Transmit Interrupt Flag */
3018#define MBTIF1 0x2 /* Mailbox 1 Mailbox Transmit Interrupt Flag */
3019#define MBTIF2 0x4 /* Mailbox 2 Mailbox Transmit Interrupt Flag */
3020#define MBTIF3 0x8 /* Mailbox 3 Mailbox Transmit Interrupt Flag */
3021#define MBTIF4 0x10 /* Mailbox 4 Mailbox Transmit Interrupt Flag */
3022#define MBTIF5 0x20 /* Mailbox 5 Mailbox Transmit Interrupt Flag */
3023#define MBTIF6 0x40 /* Mailbox 6 Mailbox Transmit Interrupt Flag */
3024#define MBTIF7 0x80 /* Mailbox 7 Mailbox Transmit Interrupt Flag */
3025#define MBTIF8 0x100 /* Mailbox 8 Mailbox Transmit Interrupt Flag */
3026#define MBTIF9 0x200 /* Mailbox 9 Mailbox Transmit Interrupt Flag */
3027#define MBTIF10 0x400 /* Mailbox 10 Mailbox Transmit Interrupt Flag */
3028#define MBTIF11 0x800 /* Mailbox 11 Mailbox Transmit Interrupt Flag */
3029#define MBTIF12 0x1000 /* Mailbox 12 Mailbox Transmit Interrupt Flag */
3030#define MBTIF13 0x2000 /* Mailbox 13 Mailbox Transmit Interrupt Flag */
3031#define MBTIF14 0x4000 /* Mailbox 14 Mailbox Transmit Interrupt Flag */
3032#define MBTIF15 0x8000 /* Mailbox 15 Mailbox Transmit Interrupt Flag */
3033
3034/* Bit masks for CAN0_MBTIF2 */
3035
3036#define MBTIF16 0x1 /* Mailbox 16 Mailbox Transmit Interrupt Flag */
3037#define MBTIF17 0x2 /* Mailbox 17 Mailbox Transmit Interrupt Flag */
3038#define MBTIF18 0x4 /* Mailbox 18 Mailbox Transmit Interrupt Flag */
3039#define MBTIF19 0x8 /* Mailbox 19 Mailbox Transmit Interrupt Flag */
3040#define MBTIF20 0x10 /* Mailbox 20 Mailbox Transmit Interrupt Flag */
3041#define MBTIF21 0x20 /* Mailbox 21 Mailbox Transmit Interrupt Flag */
3042#define MBTIF22 0x40 /* Mailbox 22 Mailbox Transmit Interrupt Flag */
3043#define MBTIF23 0x80 /* Mailbox 23 Mailbox Transmit Interrupt Flag */
3044#define MBTIF24 0x100 /* Mailbox 24 Mailbox Transmit Interrupt Flag */
3045#define MBTIF25 0x200 /* Mailbox 25 Mailbox Transmit Interrupt Flag */
3046#define MBTIF26 0x400 /* Mailbox 26 Mailbox Transmit Interrupt Flag */
3047#define MBTIF27 0x800 /* Mailbox 27 Mailbox Transmit Interrupt Flag */
3048#define MBTIF28 0x1000 /* Mailbox 28 Mailbox Transmit Interrupt Flag */
3049#define MBTIF29 0x2000 /* Mailbox 29 Mailbox Transmit Interrupt Flag */
3050#define MBTIF30 0x4000 /* Mailbox 30 Mailbox Transmit Interrupt Flag */
3051#define MBTIF31 0x8000 /* Mailbox 31 Mailbox Transmit Interrupt Flag */
3052
3053/* Bit masks for CAN0_MBRIF1 */
3054
3055#define MBRIF0 0x1 /* Mailbox 0 Mailbox Receive Interrupt Flag */
3056#define MBRIF1 0x2 /* Mailbox 1 Mailbox Receive Interrupt Flag */
3057#define MBRIF2 0x4 /* Mailbox 2 Mailbox Receive Interrupt Flag */
3058#define MBRIF3 0x8 /* Mailbox 3 Mailbox Receive Interrupt Flag */
3059#define MBRIF4 0x10 /* Mailbox 4 Mailbox Receive Interrupt Flag */
3060#define MBRIF5 0x20 /* Mailbox 5 Mailbox Receive Interrupt Flag */
3061#define MBRIF6 0x40 /* Mailbox 6 Mailbox Receive Interrupt Flag */
3062#define MBRIF7 0x80 /* Mailbox 7 Mailbox Receive Interrupt Flag */
3063#define MBRIF8 0x100 /* Mailbox 8 Mailbox Receive Interrupt Flag */
3064#define MBRIF9 0x200 /* Mailbox 9 Mailbox Receive Interrupt Flag */
3065#define MBRIF10 0x400 /* Mailbox 10 Mailbox Receive Interrupt Flag */
3066#define MBRIF11 0x800 /* Mailbox 11 Mailbox Receive Interrupt Flag */
3067#define MBRIF12 0x1000 /* Mailbox 12 Mailbox Receive Interrupt Flag */
3068#define MBRIF13 0x2000 /* Mailbox 13 Mailbox Receive Interrupt Flag */
3069#define MBRIF14 0x4000 /* Mailbox 14 Mailbox Receive Interrupt Flag */
3070#define MBRIF15 0x8000 /* Mailbox 15 Mailbox Receive Interrupt Flag */
3071
3072/* Bit masks for CAN0_MBRIF2 */
3073
3074#define MBRIF16 0x1 /* Mailbox 16 Mailbox Receive Interrupt Flag */
3075#define MBRIF17 0x2 /* Mailbox 17 Mailbox Receive Interrupt Flag */
3076#define MBRIF18 0x4 /* Mailbox 18 Mailbox Receive Interrupt Flag */
3077#define MBRIF19 0x8 /* Mailbox 19 Mailbox Receive Interrupt Flag */
3078#define MBRIF20 0x10 /* Mailbox 20 Mailbox Receive Interrupt Flag */
3079#define MBRIF21 0x20 /* Mailbox 21 Mailbox Receive Interrupt Flag */
3080#define MBRIF22 0x40 /* Mailbox 22 Mailbox Receive Interrupt Flag */
3081#define MBRIF23 0x80 /* Mailbox 23 Mailbox Receive Interrupt Flag */
3082#define MBRIF24 0x100 /* Mailbox 24 Mailbox Receive Interrupt Flag */
3083#define MBRIF25 0x200 /* Mailbox 25 Mailbox Receive Interrupt Flag */
3084#define MBRIF26 0x400 /* Mailbox 26 Mailbox Receive Interrupt Flag */
3085#define MBRIF27 0x800 /* Mailbox 27 Mailbox Receive Interrupt Flag */
3086#define MBRIF28 0x1000 /* Mailbox 28 Mailbox Receive Interrupt Flag */
3087#define MBRIF29 0x2000 /* Mailbox 29 Mailbox Receive Interrupt Flag */
3088#define MBRIF30 0x4000 /* Mailbox 30 Mailbox Receive Interrupt Flag */
3089#define MBRIF31 0x8000 /* Mailbox 31 Mailbox Receive Interrupt Flag */
3090
3091/* Bit masks for EPPIx_STATUS */
3092
3093#define CFIFO_ERR 0x1 /* Chroma FIFO Error */
3094#define YFIFO_ERR 0x2 /* Luma FIFO Error */
3095#define LTERR_OVR 0x4 /* Line Track Overflow */
3096#define LTERR_UNDR 0x8 /* Line Track Underflow */
3097#define FTERR_OVR 0x10 /* Frame Track Overflow */
3098#define FTERR_UNDR 0x20 /* Frame Track Underflow */
3099#define ERR_NCOR 0x40 /* Preamble Error Not Corrected */
3100#define DMA1URQ 0x80 /* DMA1 Urgent Request */
3101#define DMA0URQ 0x100 /* DMA0 Urgent Request */
3102#define ERR_DET 0x4000 /* Preamble Error Detected */
3103#define FLD 0x8000 /* Field */
3104
3105/* Bit masks for EPPIx_CONTROL */
3106
3107#define EPPI_EN 0x1 /* Enable */
3108#define EPPI_DIR 0x2 /* Direction */
3109#define XFR_TYPE 0xc /* Operating Mode */
3110#define FS_CFG 0x30 /* Frame Sync Configuration */
3111#define FLD_SEL 0x40 /* Field Select/Trigger */
3112#define ITU_TYPE 0x80 /* ITU Interlaced or Progressive */
3113#define BLANKGEN 0x100 /* ITU Output Mode with Internal Blanking Generation */
3114#define ICLKGEN 0x200 /* Internal Clock Generation */
3115#define IFSGEN 0x400 /* Internal Frame Sync Generation */
3116#define POLC 0x1800 /* Frame Sync and Data Driving/Sampling Edges */
3117#define POLS 0x6000 /* Frame Sync Polarity */
3118#define DLENGTH 0x38000 /* Data Length */
3119#define SKIP_EN 0x40000 /* Skip Enable */
3120#define SKIP_EO 0x80000 /* Skip Even or Odd */
3121#define PACKEN 0x100000 /* Packing/Unpacking Enable */
3122#define SWAPEN 0x200000 /* Swap Enable */
3123#define SIGN_EXT 0x400000 /* Sign Extension or Zero-filled / Data Split Format */
3124#define SPLT_EVEN_ODD 0x800000 /* Split Even and Odd Data Samples */
3125#define SUBSPLT_ODD 0x1000000 /* Sub-split Odd Samples */
3126#define DMACFG 0x2000000 /* One or Two DMA Channels Mode */
3127#define RGB_FMT_EN 0x4000000 /* RGB Formatting Enable */
3128#define FIFO_RWM 0x18000000 /* FIFO Regular Watermarks */
3129#define FIFO_UWM 0x60000000 /* FIFO Urgent Watermarks */
3130
3131#define DLEN_8 (0 << 15) /* 000 - 8 bits */
3132#define DLEN_10 (1 << 15) /* 001 - 10 bits */
3133#define DLEN_12 (2 << 15) /* 010 - 12 bits */
3134#define DLEN_14 (3 << 15) /* 011 - 14 bits */
3135#define DLEN_16 (4 << 15) /* 100 - 16 bits */
3136#define DLEN_18 (5 << 15) /* 101 - 18 bits */
3137#define DLEN_24 (6 << 15) /* 110 - 24 bits */
3138
3139
3140/* Bit masks for EPPIx_FS2W_LVB */
3141
3142#define F1VB_BD 0xff /* Vertical Blanking before Field 1 Active Data */
3143#define F1VB_AD 0xff00 /* Vertical Blanking after Field 1 Active Data */
3144#define F2VB_BD 0xff0000 /* Vertical Blanking before Field 2 Active Data */
3145#define F2VB_AD 0xff000000 /* Vertical Blanking after Field 2 Active Data */
3146
3147/* Bit masks for EPPIx_FS2W_LAVF */
3148
3149#define F1_ACT 0xffff /* Number of Lines of Active Data in Field 1 */
3150#define F2_ACT 0xffff0000 /* Number of Lines of Active Data in Field 2 */
3151
3152/* Bit masks for EPPIx_CLIP */
3153
3154#define LOW_ODD 0xff /* Lower Limit for Odd Bytes (Chroma) */
3155#define HIGH_ODD 0xff00 /* Upper Limit for Odd Bytes (Chroma) */
3156#define LOW_EVEN 0xff0000 /* Lower Limit for Even Bytes (Luma) */
3157#define HIGH_EVEN 0xff000000 /* Upper Limit for Even Bytes (Luma) */
3158
3159/* Bit masks for SPIx_BAUD */
3160
3161#define SPI_BAUD 0xffff /* Baud Rate */
3162
3163/* Bit masks for SPIx_CTL */
3164
3165#define SPE 0x4000 /* SPI Enable */
3166#define WOM 0x2000 /* Write Open Drain Master */
3167#define MSTR 0x1000 /* Master Mode */
3168#define CPOL 0x800 /* Clock Polarity */
3169#define CPHA 0x400 /* Clock Phase */
3170#define LSBF 0x200 /* LSB First */
3171#define SIZE 0x100 /* Size of Words */
3172#define EMISO 0x20 /* Enable MISO Output */
3173#define PSSE 0x10 /* Slave-Select Enable */
3174#define GM 0x8 /* Get More Data */
3175#define SZ 0x4 /* Send Zero */
3176#define TIMOD 0x3 /* Transfer Initiation Mode */
3177
3178/* Bit masks for SPIx_FLG */
3179
3180#define FLS1 0x2 /* Slave Select Enable 1 */
3181#define FLS2 0x4 /* Slave Select Enable 2 */
3182#define FLS3 0x8 /* Slave Select Enable 3 */
3183#define FLG1 0x200 /* Slave Select Value 1 */
3184#define FLG2 0x400 /* Slave Select Value 2 */
3185#define FLG3 0x800 /* Slave Select Value 3 */
3186
3187/* Bit masks for SPIx_STAT */
3188
3189#define TXCOL 0x40 /* Transmit Collision Error */
3190#define RXS 0x20 /* RDBR Data Buffer Status */
3191#define RBSY 0x10 /* Receive Error */
3192#define TXS 0x8 /* TDBR Data Buffer Status */
3193#define TXE 0x4 /* Transmission Error */
3194#define MODF 0x2 /* Mode Fault Error */
3195#define SPIF 0x1 /* SPI Finished */
3196
3197/* Bit masks for SPIx_TDBR */
3198
3199#define TDBR 0xffff /* Transmit Data Buffer */
3200
3201/* Bit masks for SPIx_RDBR */
3202
3203#define RDBR 0xffff /* Receive Data Buffer */
3204
3205/* Bit masks for SPIx_SHADOW */
3206
3207#define SHADOW 0xffff /* RDBR Shadow */
3208
3209/* ************************************************ */
3210/* The TWI bit masks fields are from the ADSP-BF538 */
3211/* and they have not been verified as the final */
3212/* ones for the Moab processors ... bz 1/19/2007 */
3213/* ************************************************ */
3214
3215/* Bit masks for TWIx_CONTROL */
3216
3217#define PRESCALE 0x7f /* Prescale Value */
3218#define TWI_ENA 0x80 /* TWI Enable */
3219#define SCCB 0x200 /* Serial Camera Control Bus */
3220
3221/* Bit maskes for TWIx_CLKDIV */
3222
3223#define CLKLOW 0xff /* Clock Low */
3224#define CLKHI 0xff00 /* Clock High */
3225
3226/* Bit maskes for TWIx_SLAVE_CTL */
3227
3228#define SEN 0x1 /* Slave Enable */
3229#define STDVAL 0x4 /* Slave Transmit Data Valid */
3230#define NAK 0x8 /* Not Acknowledge */
3231#define GEN 0x10 /* General Call Enable */
3232
3233/* Bit maskes for TWIx_SLAVE_ADDR */
3234
3235#define SADDR 0x7f /* Slave Mode Address */
3236
3237/* Bit maskes for TWIx_SLAVE_STAT */
3238
3239#define SDIR 0x1 /* Slave Transfer Direction */
3240#define GCALL 0x2 /* General Call */
3241
3242/* Bit maskes for TWIx_MASTER_CTL */
3243
3244#define MEN 0x1 /* Master Mode Enable */
3245#define MDIR 0x4 /* Master Transfer Direction */
3246#define FAST 0x8 /* Fast Mode */
3247#define STOP 0x10 /* Issue Stop Condition */
3248#define RSTART 0x20 /* Repeat Start */
3249#define DCNT 0x3fc0 /* Data Transfer Count */
3250#define SDAOVR 0x4000 /* Serial Data Override */
3251#define SCLOVR 0x8000 /* Serial Clock Override */
3252
3253/* Bit maskes for TWIx_MASTER_ADDR */
3254
3255#define MADDR 0x7f /* Master Mode Address */
3256
3257/* Bit maskes for TWIx_MASTER_STAT */
3258
3259#define MPROG 0x1 /* Master Transfer in Progress */
3260#define LOSTARB 0x2 /* Lost Arbitration */
3261#define ANAK 0x4 /* Address Not Acknowledged */
3262#define DNAK 0x8 /* Data Not Acknowledged */
3263#define BUFRDERR 0x10 /* Buffer Read Error */
3264#define BUFWRERR 0x20 /* Buffer Write Error */
3265#define SDASEN 0x40 /* Serial Data Sense */
3266#define SCLSEN 0x80 /* Serial Clock Sense */
3267#define BUSBUSY 0x100 /* Bus Busy */
3268
3269/* Bit maskes for TWIx_FIFO_CTL */
3270
3271#define XMTFLUSH 0x1 /* Transmit Buffer Flush */
3272#define RCVFLUSH 0x2 /* Receive Buffer Flush */
3273#define XMTINTLEN 0x4 /* Transmit Buffer Interrupt Length */
3274#define RCVINTLEN 0x8 /* Receive Buffer Interrupt Length */
3275
3276/* Bit maskes for TWIx_FIFO_STAT */
3277
3278#define XMTSTAT 0x3 /* Transmit FIFO Status */
3279#define RCVSTAT 0xc /* Receive FIFO Status */
3280
3281/* Bit maskes for TWIx_INT_MASK */
3282
3283#define SINITM 0x1 /* Slave Transfer Initiated Interrupt Mask */
3284#define SCOMPM 0x2 /* Slave Transfer Complete Interrupt Mask */
3285#define SERRM 0x4 /* Slave Transfer Error Interrupt Mask */
3286#define SOVFM 0x8 /* Slave Overflow Interrupt Mask */
3287#define MCOMPM 0x10 /* Master Transfer Complete Interrupt Mask */
3288#define MERRM 0x20 /* Master Transfer Error Interrupt Mask */
3289#define XMTSERVM 0x40 /* Transmit FIFO Service Interrupt Mask */
3290#define RCVSERVM 0x80 /* Receive FIFO Service Interrupt Mask */
3291
3292/* Bit maskes for TWIx_INT_STAT */
3293
3294#define SINIT 0x1 /* Slave Transfer Initiated */
3295#define SCOMP 0x2 /* Slave Transfer Complete */
3296#define SERR 0x4 /* Slave Transfer Error */
3297#define SOVF 0x8 /* Slave Overflow */
3298#define MCOMP 0x10 /* Master Transfer Complete */
3299#define MERR 0x20 /* Master Transfer Error */
3300#define XMTSERV 0x40 /* Transmit FIFO Service */
3301#define RCVSERV 0x80 /* Receive FIFO Service */
3302
3303/* Bit maskes for TWIx_XMT_DATA8 */
3304
3305#define XMTDATA8 0xff /* Transmit FIFO 8-Bit Data */
3306
3307/* Bit maskes for TWIx_XMT_DATA16 */
3308
3309#define XMTDATA16 0xffff /* Transmit FIFO 16-Bit Data */
3310
3311/* Bit maskes for TWIx_RCV_DATA8 */
3312
3313#define RCVDATA8 0xff /* Receive FIFO 8-Bit Data */
3314
3315/* Bit maskes for TWIx_RCV_DATA16 */
3316
3317#define RCVDATA16 0xffff /* Receive FIFO 16-Bit Data */
3318
3319/* Bit masks for SPORTx_TCR1 */
3320
3321#define TCKFE 0x4000 /* Clock Falling Edge Select */
3322#define LATFS 0x2000 /* Late Transmit Frame Sync */
3323#define LTFS 0x1000 /* Low Transmit Frame Sync Select */
3324#define DITFS 0x800 /* Data-Independent Transmit Frame Sync Select */
3325#define TFSR 0x400 /* Transmit Frame Sync Required Select */
3326#define ITFS 0x200 /* Internal Transmit Frame Sync Select */
3327#define TLSBIT 0x10 /* Transmit Bit Order */
3328#define TDTYPE 0xc /* Data Formatting Type Select */
3329#define ITCLK 0x2 /* Internal Transmit Clock Select */
3330#define TSPEN 0x1 /* Transmit Enable */
3331
3332/* Bit masks for SPORTx_TCR2 */
3333
3334#define TRFST 0x400 /* Left/Right Order */
3335#define TSFSE 0x200 /* Transmit Stereo Frame Sync Enable */
3336#define TXSE 0x100 /* TxSEC Enable */
3337#define SLEN_T 0x1f /* SPORT Word Length */
3338
3339/* Bit masks for SPORTx_RCR1 */
3340
3341#define RCKFE 0x4000 /* Clock Falling Edge Select */
3342#define LARFS 0x2000 /* Late Receive Frame Sync */
3343#define LRFS 0x1000 /* Low Receive Frame Sync Select */
3344#define RFSR 0x400 /* Receive Frame Sync Required Select */
3345#define IRFS 0x200 /* Internal Receive Frame Sync Select */
3346#define RLSBIT 0x10 /* Receive Bit Order */
3347#define RDTYPE 0xc /* Data Formatting Type Select */
3348#define IRCLK 0x2 /* Internal Receive Clock Select */
3349#define RSPEN 0x1 /* Receive Enable */
3350
3351/* Bit masks for SPORTx_RCR2 */
3352
3353#define RRFST 0x400 /* Left/Right Order */
3354#define RSFSE 0x200 /* Receive Stereo Frame Sync Enable */
3355#define RXSE 0x100 /* RxSEC Enable */
3356#define SLEN_R 0x1f /* SPORT Word Length */
3357
3358/* Bit masks for SPORTx_STAT */
3359
3360#define TXHRE 0x40 /* Transmit Hold Register Empty */
3361#define TOVF 0x20 /* Sticky Transmit Overflow Status */
3362#define TUVF 0x10 /* Sticky Transmit Underflow Status */
3363#define TXF 0x8 /* Transmit FIFO Full Status */
3364#define ROVF 0x4 /* Sticky Receive Overflow Status */
3365#define RUVF 0x2 /* Sticky Receive Underflow Status */
3366#define RXNE 0x1 /* Receive FIFO Not Empty Status */
3367
3368/* Bit masks for SPORTx_MCMC1 */
3369
3370#define SP_WSIZE 0xf000 /* Window Size */
3371#define SP_WOFF 0x3ff /* Windows Offset */
3372
3373/* Bit masks for SPORTx_MCMC2 */
3374
3375#define MFD 0xf000 /* Multi channel Frame Delay */
3376#define FSDR 0x80 /* Frame Sync to Data Relationship */
3377#define MCMEN 0x10 /* Multi channel Frame Mode Enable */
3378#define MCDRXPE 0x8 /* Multi channel DMA Receive Packing */
3379#define MCDTXPE 0x4 /* Multi channel DMA Transmit Packing */
3380#define MCCRM 0x3 /* 2X Clock Recovery Mode */
3381
3382/* Bit masks for SPORTx_CHNL */
3383
3384#define CUR_CHNL 0x3ff /* Current Channel Indicator */
3385
3386/* Bit masks for UARTx_LCR */
3387
3388#if 0
3389/* conflicts with legacy one in last section */
3390#define WLS 0x3 /* Word Length Select */
3391#endif
3392#define STB 0x4 /* Stop Bits */
3393#define PEN 0x8 /* Parity Enable */
3394#define EPS 0x10 /* Even Parity Select */
3395#define STP 0x20 /* Sticky Parity */
3396#define SB 0x40 /* Set Break */
3397
3398/* Bit masks for UARTx_MCR */
3399
3400#define XOFF 0x1 /* Transmitter Off */
3401#define MRTS 0x2 /* Manual Request To Send */
3402#define RFIT 0x4 /* Receive FIFO IRQ Threshold */
3403#define RFRT 0x8 /* Receive FIFO RTS Threshold */
3404#define LOOP_ENA 0x10 /* Loopback Mode Enable */
3405#define FCPOL 0x20 /* Flow Control Pin Polarity */
3406#define ARTS 0x40 /* Automatic Request To Send */
3407#define ACTS 0x80 /* Automatic Clear To Send */
3408
3409/* Bit masks for UARTx_LSR */
3410
3411#define DR 0x1 /* Data Ready */
3412#define OE 0x2 /* Overrun Error */
3413#define PE 0x4 /* Parity Error */
3414#define FE 0x8 /* Framing Error */
3415#define BI 0x10 /* Break Interrupt */
3416#define THRE 0x20 /* THR Empty */
3417#define TEMT 0x40 /* Transmitter Empty */
3418#define TFI 0x80 /* Transmission Finished Indicator */
3419
3420/* Bit masks for UARTx_MSR */
3421
3422#define SCTS 0x1 /* Sticky CTS */
3423#define CTS 0x10 /* Clear To Send */
3424#define RFCS 0x20 /* Receive FIFO Count Status */
3425
3426/* Bit masks for UARTx_IER_SET & UARTx_IER_CLEAR */
3427
3428#define ERBFI 0x1 /* Enable Receive Buffer Full Interrupt */
3429#define ETBEI 0x2 /* Enable Transmit Buffer Empty Interrupt */
3430#define ELSI 0x4 /* Enable Receive Status Interrupt */
3431#define EDSSI 0x8 /* Enable Modem Status Interrupt */
3432#define EDTPTI 0x10 /* Enable DMA Transmit PIRQ Interrupt */
3433#define ETFI 0x20 /* Enable Transmission Finished Interrupt */
3434#define ERFCI 0x40 /* Enable Receive FIFO Count Interrupt */
3435
3436/* Bit masks for UARTx_GCTL */
3437
3438#define UCEN 0x1 /* UART Enable */
3439#define IREN 0x2 /* IrDA Mode Enable */
3440#define TPOLC 0x4 /* IrDA TX Polarity Change */
3441#define RPOLC 0x8 /* IrDA RX Polarity Change */
3442#define FPE 0x10 /* Force Parity Error */
3443#define FFE 0x20 /* Force Framing Error */
3444#define EDBO 0x40 /* Enable Divide-by-One */
3445#define EGLSI 0x80 /* Enable Global LS Interrupt */
3446
3447
3448/* ******************************************* */
3449/* MULTI BIT MACRO ENUMERATIONS */
3450/* ******************************************* */
3451
3452/* BCODE bit field options (SYSCFG register) */
3453
3454#define BCODE_WAKEUP 0x0000 /* boot according to wake-up condition */
3455#define BCODE_FULLBOOT 0x0010 /* always perform full boot */
3456#define BCODE_QUICKBOOT 0x0020 /* always perform quick boot */
3457#define BCODE_NOBOOT 0x0030 /* always perform full boot */
3458
3459/* CNT_COMMAND bit field options */
3460
3461#define W1LCNT_ZERO 0x0001 /* write 1 to load CNT_COUNTER with zero */
3462#define W1LCNT_MIN 0x0004 /* write 1 to load CNT_COUNTER from CNT_MIN */
3463#define W1LCNT_MAX 0x0008 /* write 1 to load CNT_COUNTER from CNT_MAX */
3464
3465#define W1LMIN_ZERO 0x0010 /* write 1 to load CNT_MIN with zero */
3466#define W1LMIN_CNT 0x0020 /* write 1 to load CNT_MIN from CNT_COUNTER */
3467#define W1LMIN_MAX 0x0080 /* write 1 to load CNT_MIN from CNT_MAX */
3468
3469#define W1LMAX_ZERO 0x0100 /* write 1 to load CNT_MAX with zero */
3470#define W1LMAX_CNT 0x0200 /* write 1 to load CNT_MAX from CNT_COUNTER */
3471#define W1LMAX_MIN 0x0400 /* write 1 to load CNT_MAX from CNT_MIN */
3472
3473/* CNT_CONFIG bit field options */
3474
3475#define CNTMODE_QUADENC 0x0000 /* quadrature encoder mode */
3476#define CNTMODE_BINENC 0x0100 /* binary encoder mode */
3477#define CNTMODE_UDCNT 0x0200 /* up/down counter mode */
3478#define CNTMODE_DIRCNT 0x0400 /* direction counter mode */
3479#define CNTMODE_DIRTMR 0x0500 /* direction timer mode */
3480
3481#define BNDMODE_COMP 0x0000 /* boundary compare mode */
3482#define BNDMODE_ZERO 0x1000 /* boundary compare and zero mode */
3483#define BNDMODE_CAPT 0x2000 /* boundary capture mode */
3484#define BNDMODE_AEXT 0x3000 /* boundary auto-extend mode */
3485
3486/* TMODE in TIMERx_CONFIG bit field options */
3487
3488#define PWM_OUT 0x0001
3489#define WDTH_CAP 0x0002
3490#define EXT_CLK 0x0003
3491
3492/* UARTx_LCR bit field options */
3493
3494#define WLS_5 0x0000 /* 5 data bits */
3495#define WLS_6 0x0001 /* 6 data bits */
3496#define WLS_7 0x0002 /* 7 data bits */
3497#define WLS_8 0x0003 /* 8 data bits */
3498
3499/* PINTx Register Bit Definitions */
3500
3501#define PIQ0 0x00000001
3502#define PIQ1 0x00000002
3503#define PIQ2 0x00000004
3504#define PIQ3 0x00000008
3505
3506#define PIQ4 0x00000010
3507#define PIQ5 0x00000020
3508#define PIQ6 0x00000040
3509#define PIQ7 0x00000080
3510
3511#define PIQ8 0x00000100
3512#define PIQ9 0x00000200
3513#define PIQ10 0x00000400
3514#define PIQ11 0x00000800
3515
3516#define PIQ12 0x00001000
3517#define PIQ13 0x00002000
3518#define PIQ14 0x00004000
3519#define PIQ15 0x00008000
3520
3521#define PIQ16 0x00010000
3522#define PIQ17 0x00020000
3523#define PIQ18 0x00040000
3524#define PIQ19 0x00080000
3525
3526#define PIQ20 0x00100000
3527#define PIQ21 0x00200000
3528#define PIQ22 0x00400000
3529#define PIQ23 0x00800000
3530
3531#define PIQ24 0x01000000
3532#define PIQ25 0x02000000
3533#define PIQ26 0x04000000
3534#define PIQ27 0x08000000
3535
3536#define PIQ28 0x10000000
3537#define PIQ29 0x20000000
3538#define PIQ30 0x40000000
3539#define PIQ31 0x80000000
3540
3541/* PORT A Bit Definitions for the registers
3542PORTA, PORTA_SET, PORTA_CLEAR,
3543PORTA_DIR_SET, PORTA_DIR_CLEAR, PORTA_INEN,
3544PORTA_FER registers
3545*/
3546
3547#define PA0 0x0001
3548#define PA1 0x0002
3549#define PA2 0x0004
3550#define PA3 0x0008
3551#define PA4 0x0010
3552#define PA5 0x0020
3553#define PA6 0x0040
3554#define PA7 0x0080
3555#define PA8 0x0100
3556#define PA9 0x0200
3557#define PA10 0x0400
3558#define PA11 0x0800
3559#define PA12 0x1000
3560#define PA13 0x2000
3561#define PA14 0x4000
3562#define PA15 0x8000
3563
3564/* PORT B Bit Definitions for the registers
3565PORTB, PORTB_SET, PORTB_CLEAR,
3566PORTB_DIR_SET, PORTB_DIR_CLEAR, PORTB_INEN,
3567PORTB_FER registers
3568*/
3569
3570#define PB0 0x0001
3571#define PB1 0x0002
3572#define PB2 0x0004
3573#define PB3 0x0008
3574#define PB4 0x0010
3575#define PB5 0x0020
3576#define PB6 0x0040
3577#define PB7 0x0080
3578#define PB8 0x0100
3579#define PB9 0x0200
3580#define PB10 0x0400
3581#define PB11 0x0800
3582#define PB12 0x1000
3583#define PB13 0x2000
3584#define PB14 0x4000
3585
3586
3587/* PORT C Bit Definitions for the registers
3588PORTC, PORTC_SET, PORTC_CLEAR,
3589PORTC_DIR_SET, PORTC_DIR_CLEAR, PORTC_INEN,
3590PORTC_FER registers
3591*/
3592
3593
3594#define PC0 0x0001
3595#define PC1 0x0002
3596#define PC2 0x0004
3597#define PC3 0x0008
3598#define PC4 0x0010
3599#define PC5 0x0020
3600#define PC6 0x0040
3601#define PC7 0x0080
3602#define PC8 0x0100
3603#define PC9 0x0200
3604#define PC10 0x0400
3605#define PC11 0x0800
3606#define PC12 0x1000
3607#define PC13 0x2000
3608
3609
3610/* PORT D Bit Definitions for the registers
3611PORTD, PORTD_SET, PORTD_CLEAR,
3612PORTD_DIR_SET, PORTD_DIR_CLEAR, PORTD_INEN,
3613PORTD_FER registers
3614*/
3615
3616#define PD0 0x0001
3617#define PD1 0x0002
3618#define PD2 0x0004
3619#define PD3 0x0008
3620#define PD4 0x0010
3621#define PD5 0x0020
3622#define PD6 0x0040
3623#define PD7 0x0080
3624#define PD8 0x0100
3625#define PD9 0x0200
3626#define PD10 0x0400
3627#define PD11 0x0800
3628#define PD12 0x1000
3629#define PD13 0x2000
3630#define PD14 0x4000
3631#define PD15 0x8000
3632
3633/* PORT E Bit Definitions for the registers
3634PORTE, PORTE_SET, PORTE_CLEAR,
3635PORTE_DIR_SET, PORTE_DIR_CLEAR, PORTE_INEN,
3636PORTE_FER registers
3637*/
3638
3639
3640#define PE0 0x0001
3641#define PE1 0x0002
3642#define PE2 0x0004
3643#define PE3 0x0008
3644#define PE4 0x0010
3645#define PE5 0x0020
3646#define PE6 0x0040
3647#define PE7 0x0080
3648#define PE8 0x0100
3649#define PE9 0x0200
3650#define PE10 0x0400
3651#define PE11 0x0800
3652#define PE12 0x1000
3653#define PE13 0x2000
3654#define PE14 0x4000
3655#define PE15 0x8000
3656
3657/* PORT F Bit Definitions for the registers
3658PORTF, PORTF_SET, PORTF_CLEAR,
3659PORTF_DIR_SET, PORTF_DIR_CLEAR, PORTF_INEN,
3660PORTF_FER registers
3661*/
3662
3663
3664#define PF0 0x0001
3665#define PF1 0x0002
3666#define PF2 0x0004
3667#define PF3 0x0008
3668#define PF4 0x0010
3669#define PF5 0x0020
3670#define PF6 0x0040
3671#define PF7 0x0080
3672#define PF8 0x0100
3673#define PF9 0x0200
3674#define PF10 0x0400
3675#define PF11 0x0800
3676#define PF12 0x1000
3677#define PF13 0x2000
3678#define PF14 0x4000
3679#define PF15 0x8000
3680
3681/* PORT G Bit Definitions for the registers
3682PORTG, PORTG_SET, PORTG_CLEAR,
3683PORTG_DIR_SET, PORTG_DIR_CLEAR, PORTG_INEN,
3684PORTG_FER registers
3685*/
3686
3687
3688#define PG0 0x0001
3689#define PG1 0x0002
3690#define PG2 0x0004
3691#define PG3 0x0008
3692#define PG4 0x0010
3693#define PG5 0x0020
3694#define PG6 0x0040
3695#define PG7 0x0080
3696#define PG8 0x0100
3697#define PG9 0x0200
3698#define PG10 0x0400
3699#define PG11 0x0800
3700#define PG12 0x1000
3701#define PG13 0x2000
3702#define PG14 0x4000
3703#define PG15 0x8000
3704
3705/* PORT H Bit Definitions for the registers
3706PORTH, PORTH_SET, PORTH_CLEAR,
3707PORTH_DIR_SET, PORTH_DIR_CLEAR, PORTH_INEN,
3708PORTH_FER registers
3709*/
3710
3711
3712#define PH0 0x0001
3713#define PH1 0x0002
3714#define PH2 0x0004
3715#define PH3 0x0008
3716#define PH4 0x0010
3717#define PH5 0x0020
3718#define PH6 0x0040
3719#define PH7 0x0080
3720#define PH8 0x0100
3721#define PH9 0x0200
3722#define PH10 0x0400
3723#define PH11 0x0800
3724#define PH12 0x1000
3725#define PH13 0x2000
3726
3727
3728/* PORT I Bit Definitions for the registers
3729PORTI, PORTI_SET, PORTI_CLEAR,
3730PORTI_DIR_SET, PORTI_DIR_CLEAR, PORTI_INEN,
3731PORTI_FER registers
3732*/
3733
3734
3735#define PI0 0x0001
3736#define PI1 0x0002
3737#define PI2 0x0004
3738#define PI3 0x0008
3739#define PI4 0x0010
3740#define PI5 0x0020
3741#define PI6 0x0040
3742#define PI7 0x0080
3743#define PI8 0x0100
3744#define PI9 0x0200
3745#define PI10 0x0400
3746#define PI11 0x0800
3747#define PI12 0x1000
3748#define PI13 0x2000
3749#define PI14 0x4000
3750#define PI15 0x8000
3751
3752/* PORT J Bit Definitions for the registers
3753PORTJ, PORTJ_SET, PORTJ_CLEAR,
3754PORTJ_DIR_SET, PORTJ_DIR_CLEAR, PORTJ_INEN,
3755PORTJ_FER registers
3756*/
3757
3758
3759#define PJ0 0x0001
3760#define PJ1 0x0002
3761#define PJ2 0x0004
3762#define PJ3 0x0008
3763#define PJ4 0x0010
3764#define PJ5 0x0020
3765#define PJ6 0x0040
3766#define PJ7 0x0080
3767#define PJ8 0x0100
3768#define PJ9 0x0200
3769#define PJ10 0x0400
3770#define PJ11 0x0800
3771#define PJ12 0x1000
3772#define PJ13 0x2000
3773
3774
3775/* Port Muxing Bit Fields for PORTx_MUX Registers */
3776
3777#define MUX0 0x00000003
3778#define MUX0_0 0x00000000
3779#define MUX0_1 0x00000001
3780#define MUX0_2 0x00000002
3781#define MUX0_3 0x00000003
3782
3783#define MUX1 0x0000000C
3784#define MUX1_0 0x00000000
3785#define MUX1_1 0x00000004
3786#define MUX1_2 0x00000008
3787#define MUX1_3 0x0000000C
3788
3789#define MUX2 0x00000030
3790#define MUX2_0 0x00000000
3791#define MUX2_1 0x00000010
3792#define MUX2_2 0x00000020
3793#define MUX2_3 0x00000030
3794
3795#define MUX3 0x000000C0
3796#define MUX3_0 0x00000000
3797#define MUX3_1 0x00000040
3798#define MUX3_2 0x00000080
3799#define MUX3_3 0x000000C0
3800
3801#define MUX4 0x00000300
3802#define MUX4_0 0x00000000
3803#define MUX4_1 0x00000100
3804#define MUX4_2 0x00000200
3805#define MUX4_3 0x00000300
3806
3807#define MUX5 0x00000C00
3808#define MUX5_0 0x00000000
3809#define MUX5_1 0x00000400
3810#define MUX5_2 0x00000800
3811#define MUX5_3 0x00000C00
3812
3813#define MUX6 0x00003000
3814#define MUX6_0 0x00000000
3815#define MUX6_1 0x00001000
3816#define MUX6_2 0x00002000
3817#define MUX6_3 0x00003000
3818
3819#define MUX7 0x0000C000
3820#define MUX7_0 0x00000000
3821#define MUX7_1 0x00004000
3822#define MUX7_2 0x00008000
3823#define MUX7_3 0x0000C000
3824
3825#define MUX8 0x00030000
3826#define MUX8_0 0x00000000
3827#define MUX8_1 0x00010000
3828#define MUX8_2 0x00020000
3829#define MUX8_3 0x00030000
3830
3831#define MUX9 0x000C0000
3832#define MUX9_0 0x00000000
3833#define MUX9_1 0x00040000
3834#define MUX9_2 0x00080000
3835#define MUX9_3 0x000C0000
3836
3837#define MUX10 0x00300000
3838#define MUX10_0 0x00000000
3839#define MUX10_1 0x00100000
3840#define MUX10_2 0x00200000
3841#define MUX10_3 0x00300000
3842
3843#define MUX11 0x00C00000
3844#define MUX11_0 0x00000000
3845#define MUX11_1 0x00400000
3846#define MUX11_2 0x00800000
3847#define MUX11_3 0x00C00000
3848
3849#define MUX12 0x03000000
3850#define MUX12_0 0x00000000
3851#define MUX12_1 0x01000000
3852#define MUX12_2 0x02000000
3853#define MUX12_3 0x03000000
3854
3855#define MUX13 0x0C000000
3856#define MUX13_0 0x00000000
3857#define MUX13_1 0x04000000
3858#define MUX13_2 0x08000000
3859#define MUX13_3 0x0C000000
3860
3861#define MUX14 0x30000000
3862#define MUX14_0 0x00000000
3863#define MUX14_1 0x10000000
3864#define MUX14_2 0x20000000
3865#define MUX14_3 0x30000000
3866
3867#define MUX15 0xC0000000
3868#define MUX15_0 0x00000000
3869#define MUX15_1 0x40000000
3870#define MUX15_2 0x80000000
3871#define MUX15_3 0xC0000000
3872
3873#define MUX(b15,b14,b13,b12,b11,b10,b9,b8,b7,b6,b5,b4,b3,b2,b1,b0) \
3874 ((((b15)&3) << 30) | \
3875 (((b14)&3) << 28) | \
3876 (((b13)&3) << 26) | \
3877 (((b12)&3) << 24) | \
3878 (((b11)&3) << 22) | \
3879 (((b10)&3) << 20) | \
3880 (((b9) &3) << 18) | \
3881 (((b8) &3) << 16) | \
3882 (((b7) &3) << 14) | \
3883 (((b6) &3) << 12) | \
3884 (((b5) &3) << 10) | \
3885 (((b4) &3) << 8) | \
3886 (((b3) &3) << 6) | \
3887 (((b2) &3) << 4) | \
3888 (((b1) &3) << 2) | \
3889 (((b0) &3)))
3890
3891/* Bit fields for PINT0_ASSIGN and PINT1_ASSIGN registers */
3892
3893#define B0MAP 0x000000FF /* Byte 0 Lower Half Port Mapping */
3894#define B0MAP_PAL 0x00000000 /* Map Port A Low to Byte 0 */
3895#define B0MAP_PBL 0x00000001 /* Map Port B Low to Byte 0 */
3896#define B1MAP 0x0000FF00 /* Byte 1 Upper Half Port Mapping */
3897#define B1MAP_PAH 0x00000000 /* Map Port A High to Byte 1 */
3898#define B1MAP_PBH 0x00000100 /* Map Port B High to Byte 1 */
3899#define B2MAP 0x00FF0000 /* Byte 2 Lower Half Port Mapping */
3900#define B2MAP_PAL 0x00000000 /* Map Port A Low to Byte 2 */
3901#define B2MAP_PBL 0x00010000 /* Map Port B Low to Byte 2 */
3902#define B3MAP 0xFF000000 /* Byte 3 Upper Half Port Mapping */
3903#define B3MAP_PAH 0x00000000 /* Map Port A High to Byte 3 */
3904#define B3MAP_PBH 0x01000000 /* Map Port B High to Byte 3 */
3905
3906/* Bit fields for PINT2_ASSIGN and PINT3_ASSIGN registers */
3907
3908#define B0MAP_PCL 0x00000000 /* Map Port C Low to Byte 0 */
3909#define B0MAP_PDL 0x00000001 /* Map Port D Low to Byte 0 */
3910#define B0MAP_PEL 0x00000002 /* Map Port E Low to Byte 0 */
3911#define B0MAP_PFL 0x00000003 /* Map Port F Low to Byte 0 */
3912#define B0MAP_PGL 0x00000004 /* Map Port G Low to Byte 0 */
3913#define B0MAP_PHL 0x00000005 /* Map Port H Low to Byte 0 */
3914#define B0MAP_PIL 0x00000006 /* Map Port I Low to Byte 0 */
3915#define B0MAP_PJL 0x00000007 /* Map Port J Low to Byte 0 */
3916
3917#define B1MAP_PCH 0x00000000 /* Map Port C High to Byte 1 */
3918#define B1MAP_PDH 0x00000100 /* Map Port D High to Byte 1 */
3919#define B1MAP_PEH 0x00000200 /* Map Port E High to Byte 1 */
3920#define B1MAP_PFH 0x00000300 /* Map Port F High to Byte 1 */
3921#define B1MAP_PGH 0x00000400 /* Map Port G High to Byte 1 */
3922#define B1MAP_PHH 0x00000500 /* Map Port H High to Byte 1 */
3923#define B1MAP_PIH 0x00000600 /* Map Port I High to Byte 1 */
3924#define B1MAP_PJH 0x00000700 /* Map Port J High to Byte 1 */
3925
3926#define B2MAP_PCL 0x00000000 /* Map Port C Low to Byte 2 */
3927#define B2MAP_PDL 0x00010000 /* Map Port D Low to Byte 2 */
3928#define B2MAP_PEL 0x00020000 /* Map Port E Low to Byte 2 */
3929#define B2MAP_PFL 0x00030000 /* Map Port F Low to Byte 2 */
3930#define B2MAP_PGL 0x00040000 /* Map Port G Low to Byte 2 */
3931#define B2MAP_PHL 0x00050000 /* Map Port H Low to Byte 2 */
3932#define B2MAP_PIL 0x00060000 /* Map Port I Low to Byte 2 */
3933#define B2MAP_PJL 0x00070000 /* Map Port J Low to Byte 2 */
3934
3935#define B3MAP_PCH 0x00000000 /* Map Port C High to Byte 3 */
3936#define B3MAP_PDH 0x01000000 /* Map Port D High to Byte 3 */
3937#define B3MAP_PEH 0x02000000 /* Map Port E High to Byte 3 */
3938#define B3MAP_PFH 0x03000000 /* Map Port F High to Byte 3 */
3939#define B3MAP_PGH 0x04000000 /* Map Port G High to Byte 3 */
3940#define B3MAP_PHH 0x05000000 /* Map Port H High to Byte 3 */
3941#define B3MAP_PIH 0x06000000 /* Map Port I High to Byte 3 */
3942#define B3MAP_PJH 0x07000000 /* Map Port J High to Byte 3 */
3943
3944
3945/* for legacy compatibility */
3946
3947#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
3948#define W1LMAX_MAX W1LMAX_MIN
3949#define EBIU_AMCBCTL0 EBIU_AMBCTL0
3950#define EBIU_AMCBCTL1 EBIU_AMBCTL1
3951#define PINT0_IRQ PINT0_REQUEST
3952#define PINT1_IRQ PINT1_REQUEST
3953#define PINT2_IRQ PINT2_REQUEST
3954#define PINT3_IRQ PINT3_REQUEST
3955
3956#endif /* _DEF_BF54X_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/dma.h b/arch/blackfin/mach-bf548/include/mach/dma.h
new file mode 100644
index 000000000000..36a2ef7e7849
--- /dev/null
+++ b/arch/blackfin/mach-bf548/include/mach/dma.h
@@ -0,0 +1,76 @@
1/*
2 * file: include/asm-blackfin/mach-bf548/dma.h
3 * based on:
4 * author:
5 *
6 * created:
7 * description:
8 * system mmr register map
9 * rev:
10 *
11 * modified:
12 *
13 *
14 * bugs: enter bugs at http://blackfin.uclinux.org/
15 *
16 * this program is free software; you can redistribute it and/or modify
17 * it under the terms of the gnu general public license as published by
18 * the free software foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * this program is distributed in the hope that it will be useful,
22 * but without any warranty; without even the implied warranty of
23 * merchantability or fitness for a particular purpose. see the
24 * gnu general public license for more details.
25 *
26 * you should have received a copy of the gnu general public license
27 * along with this program; see the file copying.
28 * if not, write to the free software foundation,
29 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
30 */
31
32#ifndef _MACH_DMA_H_
33#define _MACH_DMA_H_
34
35#define CH_SPORT0_RX 0
36#define CH_SPORT0_TX 1
37#define CH_SPORT1_RX 2
38#define CH_SPORT1_TX 3
39#define CH_SPI0 4
40#define CH_SPI1 5
41#define CH_UART0_RX 6
42#define CH_UART0_TX 7
43#define CH_UART1_RX 8
44#define CH_UART1_TX 9
45#define CH_ATAPI_RX 10
46#define CH_ATAPI_TX 11
47#define CH_EPPI0 12
48#define CH_EPPI1 13
49#define CH_EPPI2 14
50#define CH_PIXC_IMAGE 15
51#define CH_PIXC_OVERLAY 16
52#define CH_PIXC_OUTPUT 17
53#define CH_SPORT2_RX 18
54#define CH_UART2_RX 18
55#define CH_SPORT2_TX 19
56#define CH_UART2_TX 19
57#define CH_SPORT3_RX 20
58#define CH_UART3_RX 20
59#define CH_SPORT3_TX 21
60#define CH_UART3_TX 21
61#define CH_SDH 22
62#define CH_NFC 22
63#define CH_SPI2 23
64
65#define CH_MEM_STREAM0_DEST 24
66#define CH_MEM_STREAM0_SRC 25
67#define CH_MEM_STREAM1_DEST 26
68#define CH_MEM_STREAM1_SRC 27
69#define CH_MEM_STREAM2_DEST 28
70#define CH_MEM_STREAM2_SRC 29
71#define CH_MEM_STREAM3_DEST 30
72#define CH_MEM_STREAM3_SRC 31
73
74#define MAX_BLACKFIN_DMA_CHANNEL 32
75
76#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/gpio.h b/arch/blackfin/mach-bf548/include/mach/gpio.h
new file mode 100644
index 000000000000..bba82dc75f16
--- /dev/null
+++ b/arch/blackfin/mach-bf548/include/mach/gpio.h
@@ -0,0 +1,219 @@
1/*
2 * File: include/asm-blackfin/mach-bf548/gpio.h
3 * Based on:
4 * Author: Michael Hennerich (hennerich@blackfin.uclinux.org)
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30
31
32#define GPIO_PA0 0
33#define GPIO_PA1 1
34#define GPIO_PA2 2
35#define GPIO_PA3 3
36#define GPIO_PA4 4
37#define GPIO_PA5 5
38#define GPIO_PA6 6
39#define GPIO_PA7 7
40#define GPIO_PA8 8
41#define GPIO_PA9 9
42#define GPIO_PA10 10
43#define GPIO_PA11 11
44#define GPIO_PA12 12
45#define GPIO_PA13 13
46#define GPIO_PA14 14
47#define GPIO_PA15 15
48#define GPIO_PB0 16
49#define GPIO_PB1 17
50#define GPIO_PB2 18
51#define GPIO_PB3 19
52#define GPIO_PB4 20
53#define GPIO_PB5 21
54#define GPIO_PB6 22
55#define GPIO_PB7 23
56#define GPIO_PB8 24
57#define GPIO_PB9 25
58#define GPIO_PB10 26
59#define GPIO_PB11 27
60#define GPIO_PB12 28
61#define GPIO_PB13 29
62#define GPIO_PB14 30
63#define GPIO_PB15 31 /* N/A */
64#define GPIO_PC0 32
65#define GPIO_PC1 33
66#define GPIO_PC2 34
67#define GPIO_PC3 35
68#define GPIO_PC4 36
69#define GPIO_PC5 37
70#define GPIO_PC6 38
71#define GPIO_PC7 39
72#define GPIO_PC8 40
73#define GPIO_PC9 41
74#define GPIO_PC10 42
75#define GPIO_PC11 43
76#define GPIO_PC12 44
77#define GPIO_PC13 45
78#define GPIO_PC14 46 /* N/A */
79#define GPIO_PC15 47 /* N/A */
80#define GPIO_PD0 48
81#define GPIO_PD1 49
82#define GPIO_PD2 50
83#define GPIO_PD3 51
84#define GPIO_PD4 52
85#define GPIO_PD5 53
86#define GPIO_PD6 54
87#define GPIO_PD7 55
88#define GPIO_PD8 56
89#define GPIO_PD9 57
90#define GPIO_PD10 58
91#define GPIO_PD11 59
92#define GPIO_PD12 60
93#define GPIO_PD13 61
94#define GPIO_PD14 62
95#define GPIO_PD15 63
96#define GPIO_PE0 64
97#define GPIO_PE1 65
98#define GPIO_PE2 66
99#define GPIO_PE3 67
100#define GPIO_PE4 68
101#define GPIO_PE5 69
102#define GPIO_PE6 70
103#define GPIO_PE7 71
104#define GPIO_PE8 72
105#define GPIO_PE9 73
106#define GPIO_PE10 74
107#define GPIO_PE11 75
108#define GPIO_PE12 76
109#define GPIO_PE13 77
110#define GPIO_PE14 78
111#define GPIO_PE15 79
112#define GPIO_PF0 80
113#define GPIO_PF1 81
114#define GPIO_PF2 82
115#define GPIO_PF3 83
116#define GPIO_PF4 84
117#define GPIO_PF5 85
118#define GPIO_PF6 86
119#define GPIO_PF7 87
120#define GPIO_PF8 88
121#define GPIO_PF9 89
122#define GPIO_PF10 90
123#define GPIO_PF11 91
124#define GPIO_PF12 92
125#define GPIO_PF13 93
126#define GPIO_PF14 94
127#define GPIO_PF15 95
128#define GPIO_PG0 96
129#define GPIO_PG1 97
130#define GPIO_PG2 98
131#define GPIO_PG3 99
132#define GPIO_PG4 100
133#define GPIO_PG5 101
134#define GPIO_PG6 102
135#define GPIO_PG7 103
136#define GPIO_PG8 104
137#define GPIO_PG9 105
138#define GPIO_PG10 106
139#define GPIO_PG11 107
140#define GPIO_PG12 108
141#define GPIO_PG13 109
142#define GPIO_PG14 110
143#define GPIO_PG15 111
144#define GPIO_PH0 112
145#define GPIO_PH1 113
146#define GPIO_PH2 114
147#define GPIO_PH3 115
148#define GPIO_PH4 116
149#define GPIO_PH5 117
150#define GPIO_PH6 118
151#define GPIO_PH7 119
152#define GPIO_PH8 120
153#define GPIO_PH9 121
154#define GPIO_PH10 122
155#define GPIO_PH11 123
156#define GPIO_PH12 124
157#define GPIO_PH13 125
158#define GPIO_PH14 126 /* N/A */
159#define GPIO_PH15 127 /* N/A */
160#define GPIO_PI0 128
161#define GPIO_PI1 129
162#define GPIO_PI2 130
163#define GPIO_PI3 131
164#define GPIO_PI4 132
165#define GPIO_PI5 133
166#define GPIO_PI6 134
167#define GPIO_PI7 135
168#define GPIO_PI8 136
169#define GPIO_PI9 137
170#define GPIO_PI10 138
171#define GPIO_PI11 139
172#define GPIO_PI12 140
173#define GPIO_PI13 141
174#define GPIO_PI14 142
175#define GPIO_PI15 143
176#define GPIO_PJ0 144
177#define GPIO_PJ1 145
178#define GPIO_PJ2 146
179#define GPIO_PJ3 147
180#define GPIO_PJ4 148
181#define GPIO_PJ5 149
182#define GPIO_PJ6 150
183#define GPIO_PJ7 151
184#define GPIO_PJ8 152
185#define GPIO_PJ9 153
186#define GPIO_PJ10 154
187#define GPIO_PJ11 155
188#define GPIO_PJ12 156
189#define GPIO_PJ13 157
190#define GPIO_PJ14 158 /* N/A */
191#define GPIO_PJ15 159 /* N/A */
192
193#define MAX_BLACKFIN_GPIOS 160
194
195struct gpio_port_t {
196 unsigned short port_fer;
197 unsigned short dummy1;
198 unsigned short port_data;
199 unsigned short dummy2;
200 unsigned short port_set;
201 unsigned short dummy3;
202 unsigned short port_clear;
203 unsigned short dummy4;
204 unsigned short port_dir_set;
205 unsigned short dummy5;
206 unsigned short port_dir_clear;
207 unsigned short dummy6;
208 unsigned short port_inen;
209 unsigned short dummy7;
210 unsigned int port_mux;
211};
212
213struct gpio_port_s {
214 unsigned short fer;
215 unsigned short data;
216 unsigned short dir;
217 unsigned short inen;
218 unsigned int mux;
219};
diff --git a/arch/blackfin/mach-bf548/include/mach/irq.h b/arch/blackfin/mach-bf548/include/mach/irq.h
new file mode 100644
index 000000000000..ad380d1f5872
--- /dev/null
+++ b/arch/blackfin/mach-bf548/include/mach/irq.h
@@ -0,0 +1,501 @@
1/*
2 * file: include/asm-blackfin/mach-bf548/irq.h
3 * based on: include/asm-blackfin/mach-bf537/irq.h
4 * author: Roy Huang (roy.huang@analog.com)
5 *
6 * created:
7 * description:
8 * system mmr register map
9 * rev:
10 *
11 * modified:
12 *
13 *
14 * bugs: enter bugs at http://blackfin.uclinux.org/
15 *
16 * this program is free software; you can redistribute it and/or modify
17 * it under the terms of the gnu general public license as published by
18 * the free software foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * this program is distributed in the hope that it will be useful,
22 * but without any warranty; without even the implied warranty of
23 * merchantability or fitness for a particular purpose. see the
24 * gnu general public license for more details.
25 *
26 * you should have received a copy of the gnu general public license
27 * along with this program; see the file copying.
28 * if not, write to the free software foundation,
29 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
30 */
31
32#ifndef _BF548_IRQ_H_
33#define _BF548_IRQ_H_
34
35/*
36 * Interrupt source definitions
37 Event Source Core Event Name
38Core Emulation **
39Events (highest priority) EMU 0
40 Reset RST 1
41 NMI NMI 2
42 Exception EVX 3
43 Reserved -- 4
44 Hardware Error IVHW 5
45 Core Timer IVTMR 6 *
46
47.....
48
49 Software Interrupt 1 IVG14 31
50 Software Interrupt 2 --
51 (lowest priority) IVG15 32 *
52 */
53
54#define NR_PERI_INTS (32 * 3)
55
56/* The ABSTRACT IRQ definitions */
57/** the first seven of the following are fixed, the rest you change if you need to **/
58#define IRQ_EMU 0 /* Emulation */
59#define IRQ_RST 1 /* reset */
60#define IRQ_NMI 2 /* Non Maskable */
61#define IRQ_EVX 3 /* Exception */
62#define IRQ_UNUSED 4 /* - unused interrupt*/
63#define IRQ_HWERR 5 /* Hardware Error */
64#define IRQ_CORETMR 6 /* Core timer */
65
66#define BFIN_IRQ(x) ((x) + 7)
67
68#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
69#define IRQ_DMAC0_ERROR BFIN_IRQ(1) /* DMAC0 Status Interrupt */
70#define IRQ_EPPI0_ERROR BFIN_IRQ(2) /* EPPI0 Error Interrupt */
71#define IRQ_SPORT0_ERROR BFIN_IRQ(3) /* SPORT0 Error Interrupt */
72#define IRQ_SPORT1_ERROR BFIN_IRQ(4) /* SPORT1 Error Interrupt */
73#define IRQ_SPI0_ERROR BFIN_IRQ(5) /* SPI0 Status(Error) Interrupt */
74#define IRQ_UART0_ERROR BFIN_IRQ(6) /* UART0 Status(Error) Interrupt */
75#define IRQ_RTC BFIN_IRQ(7) /* RTC Interrupt */
76#define IRQ_EPPI0 BFIN_IRQ(8) /* EPPI0 Interrupt (DMA12) */
77#define IRQ_SPORT0_RX BFIN_IRQ(9) /* SPORT0 RX Interrupt (DMA0) */
78#define IRQ_SPORT0_TX BFIN_IRQ(10) /* SPORT0 TX Interrupt (DMA1) */
79#define IRQ_SPORT1_RX BFIN_IRQ(11) /* SPORT1 RX Interrupt (DMA2) */
80#define IRQ_SPORT1_TX BFIN_IRQ(12) /* SPORT1 TX Interrupt (DMA3) */
81#define IRQ_SPI0 BFIN_IRQ(13) /* SPI0 Interrupt (DMA4) */
82#define IRQ_UART0_RX BFIN_IRQ(14) /* UART0 RX Interrupt (DMA6) */
83#define IRQ_UART0_TX BFIN_IRQ(15) /* UART0 TX Interrupt (DMA7) */
84#define IRQ_TIMER8 BFIN_IRQ(16) /* TIMER 8 Interrupt */
85#define IRQ_TIMER9 BFIN_IRQ(17) /* TIMER 9 Interrupt */
86#define IRQ_TIMER10 BFIN_IRQ(18) /* TIMER 10 Interrupt */
87#define IRQ_PINT0 BFIN_IRQ(19) /* PINT0 Interrupt */
88#define IRQ_PINT1 BFIN_IRQ(20) /* PINT1 Interrupt */
89#define IRQ_MDMAS0 BFIN_IRQ(21) /* MDMA Stream 0 Interrupt */
90#define IRQ_MDMAS1 BFIN_IRQ(22) /* MDMA Stream 1 Interrupt */
91#define IRQ_WATCH BFIN_IRQ(23) /* Watchdog Interrupt */
92#define IRQ_DMAC1_ERROR BFIN_IRQ(24) /* DMAC1 Status (Error) Interrupt */
93#define IRQ_SPORT2_ERROR BFIN_IRQ(25) /* SPORT2 Error Interrupt */
94#define IRQ_SPORT3_ERROR BFIN_IRQ(26) /* SPORT3 Error Interrupt */
95#define IRQ_MXVR_DATA BFIN_IRQ(27) /* MXVR Data Interrupt */
96#define IRQ_SPI1_ERROR BFIN_IRQ(28) /* SPI1 Status (Error) Interrupt */
97#define IRQ_SPI2_ERROR BFIN_IRQ(29) /* SPI2 Status (Error) Interrupt */
98#define IRQ_UART1_ERROR BFIN_IRQ(30) /* UART1 Status (Error) Interrupt */
99#define IRQ_UART2_ERROR BFIN_IRQ(31) /* UART2 Status (Error) Interrupt */
100#define IRQ_CAN0_ERROR BFIN_IRQ(32) /* CAN0 Status (Error) Interrupt */
101#define IRQ_SPORT2_RX BFIN_IRQ(33) /* SPORT2 RX (DMA18) Interrupt */
102#define IRQ_UART2_RX BFIN_IRQ(33) /* UART2 RX (DMA18) Interrupt */
103#define IRQ_SPORT2_TX BFIN_IRQ(34) /* SPORT2 TX (DMA19) Interrupt */
104#define IRQ_UART2_TX BFIN_IRQ(34) /* UART2 TX (DMA19) Interrupt */
105#define IRQ_SPORT3_RX BFIN_IRQ(35) /* SPORT3 RX (DMA20) Interrupt */
106#define IRQ_UART3_RX BFIN_IRQ(35) /* UART3 RX (DMA20) Interrupt */
107#define IRQ_SPORT3_TX BFIN_IRQ(36) /* SPORT3 TX (DMA21) Interrupt */
108#define IRQ_UART3_TX BFIN_IRQ(36) /* UART3 TX (DMA21) Interrupt */
109#define IRQ_EPPI1 BFIN_IRQ(37) /* EPP1 (DMA13) Interrupt */
110#define IRQ_EPPI2 BFIN_IRQ(38) /* EPP2 (DMA14) Interrupt */
111#define IRQ_SPI1 BFIN_IRQ(39) /* SPI1 (DMA5) Interrupt */
112#define IRQ_SPI2 BFIN_IRQ(40) /* SPI2 (DMA23) Interrupt */
113#define IRQ_UART1_RX BFIN_IRQ(41) /* UART1 RX (DMA8) Interrupt */
114#define IRQ_UART1_TX BFIN_IRQ(42) /* UART1 TX (DMA9) Interrupt */
115#define IRQ_ATAPI_RX BFIN_IRQ(43) /* ATAPI RX (DMA10) Interrupt */
116#define IRQ_ATAPI_TX BFIN_IRQ(44) /* ATAPI TX (DMA11) Interrupt */
117#define IRQ_TWI0 BFIN_IRQ(45) /* TWI0 Interrupt */
118#define IRQ_TWI1 BFIN_IRQ(46) /* TWI1 Interrupt */
119#define IRQ_CAN0_RX BFIN_IRQ(47) /* CAN0 Receive Interrupt */
120#define IRQ_CAN0_TX BFIN_IRQ(48) /* CAN0 Transmit Interrupt */
121#define IRQ_MDMAS2 BFIN_IRQ(49) /* MDMA Stream 2 Interrupt */
122#define IRQ_MDMAS3 BFIN_IRQ(50) /* MDMA Stream 3 Interrupt */
123#define IRQ_MXVR_ERROR BFIN_IRQ(51) /* MXVR Status (Error) Interrupt */
124#define IRQ_MXVR_MSG BFIN_IRQ(52) /* MXVR Message Interrupt */
125#define IRQ_MXVR_PKT BFIN_IRQ(53) /* MXVR Packet Interrupt */
126#define IRQ_EPP1_ERROR BFIN_IRQ(54) /* EPPI1 Error Interrupt */
127#define IRQ_EPP2_ERROR BFIN_IRQ(55) /* EPPI2 Error Interrupt */
128#define IRQ_UART3_ERROR BFIN_IRQ(56) /* UART3 Status (Error) Interrupt */
129#define IRQ_HOST_ERROR BFIN_IRQ(57) /* HOST Status (Error) Interrupt */
130#define IRQ_PIXC_ERROR BFIN_IRQ(59) /* PIXC Status (Error) Interrupt */
131#define IRQ_NFC_ERROR BFIN_IRQ(60) /* NFC Error Interrupt */
132#define IRQ_ATAPI_ERROR BFIN_IRQ(61) /* ATAPI Error Interrupt */
133#define IRQ_CAN1_ERROR BFIN_IRQ(62) /* CAN1 Status (Error) Interrupt */
134#define IRQ_HS_DMA_ERROR BFIN_IRQ(63) /* Handshake DMA Status Interrupt */
135#define IRQ_PIXC_IN0 BFIN_IRQ(64) /* PIXC IN0 (DMA15) Interrupt */
136#define IRQ_PIXC_IN1 BFIN_IRQ(65) /* PIXC IN1 (DMA16) Interrupt */
137#define IRQ_PIXC_OUT BFIN_IRQ(66) /* PIXC OUT (DMA17) Interrupt */
138#define IRQ_SDH BFIN_IRQ(67) /* SDH/NFC (DMA22) Interrupt */
139#define IRQ_CNT BFIN_IRQ(68) /* CNT Interrupt */
140#define IRQ_KEY BFIN_IRQ(69) /* KEY Interrupt */
141#define IRQ_CAN1_RX BFIN_IRQ(70) /* CAN1 RX Interrupt */
142#define IRQ_CAN1_TX BFIN_IRQ(71) /* CAN1 TX Interrupt */
143#define IRQ_SDH_MASK0 BFIN_IRQ(72) /* SDH Mask 0 Interrupt */
144#define IRQ_SDH_MASK1 BFIN_IRQ(73) /* SDH Mask 1 Interrupt */
145#define IRQ_USB_INT0 BFIN_IRQ(75) /* USB INT0 Interrupt */
146#define IRQ_USB_INT1 BFIN_IRQ(76) /* USB INT1 Interrupt */
147#define IRQ_USB_INT2 BFIN_IRQ(77) /* USB INT2 Interrupt */
148#define IRQ_USB_DMA BFIN_IRQ(78) /* USB DMA Interrupt */
149#define IRQ_OPTSEC BFIN_IRQ(79) /* OTPSEC Interrupt */
150#define IRQ_TIMER0 BFIN_IRQ(86) /* Timer 0 Interrupt */
151#define IRQ_TIMER1 BFIN_IRQ(87) /* Timer 1 Interrupt */
152#define IRQ_TIMER2 BFIN_IRQ(88) /* Timer 2 Interrupt */
153#define IRQ_TIMER3 BFIN_IRQ(89) /* Timer 3 Interrupt */
154#define IRQ_TIMER4 BFIN_IRQ(90) /* Timer 4 Interrupt */
155#define IRQ_TIMER5 BFIN_IRQ(91) /* Timer 5 Interrupt */
156#define IRQ_TIMER6 BFIN_IRQ(92) /* Timer 6 Interrupt */
157#define IRQ_TIMER7 BFIN_IRQ(93) /* Timer 7 Interrupt */
158#define IRQ_PINT2 BFIN_IRQ(94) /* PINT2 Interrupt */
159#define IRQ_PINT3 BFIN_IRQ(95) /* PINT3 Interrupt */
160
161#define SYS_IRQS IRQ_PINT3
162
163#define BFIN_PA_IRQ(x) ((x) + SYS_IRQS + 1)
164#define IRQ_PA0 BFIN_PA_IRQ(0)
165#define IRQ_PA1 BFIN_PA_IRQ(1)
166#define IRQ_PA2 BFIN_PA_IRQ(2)
167#define IRQ_PA3 BFIN_PA_IRQ(3)
168#define IRQ_PA4 BFIN_PA_IRQ(4)
169#define IRQ_PA5 BFIN_PA_IRQ(5)
170#define IRQ_PA6 BFIN_PA_IRQ(6)
171#define IRQ_PA7 BFIN_PA_IRQ(7)
172#define IRQ_PA8 BFIN_PA_IRQ(8)
173#define IRQ_PA9 BFIN_PA_IRQ(9)
174#define IRQ_PA10 BFIN_PA_IRQ(10)
175#define IRQ_PA11 BFIN_PA_IRQ(11)
176#define IRQ_PA12 BFIN_PA_IRQ(12)
177#define IRQ_PA13 BFIN_PA_IRQ(13)
178#define IRQ_PA14 BFIN_PA_IRQ(14)
179#define IRQ_PA15 BFIN_PA_IRQ(15)
180
181#define BFIN_PB_IRQ(x) ((x) + IRQ_PA15 + 1)
182#define IRQ_PB0 BFIN_PB_IRQ(0)
183#define IRQ_PB1 BFIN_PB_IRQ(1)
184#define IRQ_PB2 BFIN_PB_IRQ(2)
185#define IRQ_PB3 BFIN_PB_IRQ(3)
186#define IRQ_PB4 BFIN_PB_IRQ(4)
187#define IRQ_PB5 BFIN_PB_IRQ(5)
188#define IRQ_PB6 BFIN_PB_IRQ(6)
189#define IRQ_PB7 BFIN_PB_IRQ(7)
190#define IRQ_PB8 BFIN_PB_IRQ(8)
191#define IRQ_PB9 BFIN_PB_IRQ(9)
192#define IRQ_PB10 BFIN_PB_IRQ(10)
193#define IRQ_PB11 BFIN_PB_IRQ(11)
194#define IRQ_PB12 BFIN_PB_IRQ(12)
195#define IRQ_PB13 BFIN_PB_IRQ(13)
196#define IRQ_PB14 BFIN_PB_IRQ(14)
197#define IRQ_PB15 BFIN_PB_IRQ(15) /* N/A */
198
199#define BFIN_PC_IRQ(x) ((x) + IRQ_PB15 + 1)
200#define IRQ_PC0 BFIN_PC_IRQ(0)
201#define IRQ_PC1 BFIN_PC_IRQ(1)
202#define IRQ_PC2 BFIN_PC_IRQ(2)
203#define IRQ_PC3 BFIN_PC_IRQ(3)
204#define IRQ_PC4 BFIN_PC_IRQ(4)
205#define IRQ_PC5 BFIN_PC_IRQ(5)
206#define IRQ_PC6 BFIN_PC_IRQ(6)
207#define IRQ_PC7 BFIN_PC_IRQ(7)
208#define IRQ_PC8 BFIN_PC_IRQ(8)
209#define IRQ_PC9 BFIN_PC_IRQ(9)
210#define IRQ_PC10 BFIN_PC_IRQ(10)
211#define IRQ_PC11 BFIN_PC_IRQ(11)
212#define IRQ_PC12 BFIN_PC_IRQ(12)
213#define IRQ_PC13 BFIN_PC_IRQ(13)
214#define IRQ_PC14 BFIN_PC_IRQ(14) /* N/A */
215#define IRQ_PC15 BFIN_PC_IRQ(15) /* N/A */
216
217#define BFIN_PD_IRQ(x) ((x) + IRQ_PC15 + 1)
218#define IRQ_PD0 BFIN_PD_IRQ(0)
219#define IRQ_PD1 BFIN_PD_IRQ(1)
220#define IRQ_PD2 BFIN_PD_IRQ(2)
221#define IRQ_PD3 BFIN_PD_IRQ(3)
222#define IRQ_PD4 BFIN_PD_IRQ(4)
223#define IRQ_PD5 BFIN_PD_IRQ(5)
224#define IRQ_PD6 BFIN_PD_IRQ(6)
225#define IRQ_PD7 BFIN_PD_IRQ(7)
226#define IRQ_PD8 BFIN_PD_IRQ(8)
227#define IRQ_PD9 BFIN_PD_IRQ(9)
228#define IRQ_PD10 BFIN_PD_IRQ(10)
229#define IRQ_PD11 BFIN_PD_IRQ(11)
230#define IRQ_PD12 BFIN_PD_IRQ(12)
231#define IRQ_PD13 BFIN_PD_IRQ(13)
232#define IRQ_PD14 BFIN_PD_IRQ(14)
233#define IRQ_PD15 BFIN_PD_IRQ(15)
234
235#define BFIN_PE_IRQ(x) ((x) + IRQ_PD15 + 1)
236#define IRQ_PE0 BFIN_PE_IRQ(0)
237#define IRQ_PE1 BFIN_PE_IRQ(1)
238#define IRQ_PE2 BFIN_PE_IRQ(2)
239#define IRQ_PE3 BFIN_PE_IRQ(3)
240#define IRQ_PE4 BFIN_PE_IRQ(4)
241#define IRQ_PE5 BFIN_PE_IRQ(5)
242#define IRQ_PE6 BFIN_PE_IRQ(6)
243#define IRQ_PE7 BFIN_PE_IRQ(7)
244#define IRQ_PE8 BFIN_PE_IRQ(8)
245#define IRQ_PE9 BFIN_PE_IRQ(9)
246#define IRQ_PE10 BFIN_PE_IRQ(10)
247#define IRQ_PE11 BFIN_PE_IRQ(11)
248#define IRQ_PE12 BFIN_PE_IRQ(12)
249#define IRQ_PE13 BFIN_PE_IRQ(13)
250#define IRQ_PE14 BFIN_PE_IRQ(14)
251#define IRQ_PE15 BFIN_PE_IRQ(15)
252
253#define BFIN_PF_IRQ(x) ((x) + IRQ_PE15 + 1)
254#define IRQ_PF0 BFIN_PF_IRQ(0)
255#define IRQ_PF1 BFIN_PF_IRQ(1)
256#define IRQ_PF2 BFIN_PF_IRQ(2)
257#define IRQ_PF3 BFIN_PF_IRQ(3)
258#define IRQ_PF4 BFIN_PF_IRQ(4)
259#define IRQ_PF5 BFIN_PF_IRQ(5)
260#define IRQ_PF6 BFIN_PF_IRQ(6)
261#define IRQ_PF7 BFIN_PF_IRQ(7)
262#define IRQ_PF8 BFIN_PF_IRQ(8)
263#define IRQ_PF9 BFIN_PF_IRQ(9)
264#define IRQ_PF10 BFIN_PF_IRQ(10)
265#define IRQ_PF11 BFIN_PF_IRQ(11)
266#define IRQ_PF12 BFIN_PF_IRQ(12)
267#define IRQ_PF13 BFIN_PF_IRQ(13)
268#define IRQ_PF14 BFIN_PF_IRQ(14)
269#define IRQ_PF15 BFIN_PF_IRQ(15)
270
271#define BFIN_PG_IRQ(x) ((x) + IRQ_PF15 + 1)
272#define IRQ_PG0 BFIN_PG_IRQ(0)
273#define IRQ_PG1 BFIN_PG_IRQ(1)
274#define IRQ_PG2 BFIN_PG_IRQ(2)
275#define IRQ_PG3 BFIN_PG_IRQ(3)
276#define IRQ_PG4 BFIN_PG_IRQ(4)
277#define IRQ_PG5 BFIN_PG_IRQ(5)
278#define IRQ_PG6 BFIN_PG_IRQ(6)
279#define IRQ_PG7 BFIN_PG_IRQ(7)
280#define IRQ_PG8 BFIN_PG_IRQ(8)
281#define IRQ_PG9 BFIN_PG_IRQ(9)
282#define IRQ_PG10 BFIN_PG_IRQ(10)
283#define IRQ_PG11 BFIN_PG_IRQ(11)
284#define IRQ_PG12 BFIN_PG_IRQ(12)
285#define IRQ_PG13 BFIN_PG_IRQ(13)
286#define IRQ_PG14 BFIN_PG_IRQ(14)
287#define IRQ_PG15 BFIN_PG_IRQ(15)
288
289#define BFIN_PH_IRQ(x) ((x) + IRQ_PG15 + 1)
290#define IRQ_PH0 BFIN_PH_IRQ(0)
291#define IRQ_PH1 BFIN_PH_IRQ(1)
292#define IRQ_PH2 BFIN_PH_IRQ(2)
293#define IRQ_PH3 BFIN_PH_IRQ(3)
294#define IRQ_PH4 BFIN_PH_IRQ(4)
295#define IRQ_PH5 BFIN_PH_IRQ(5)
296#define IRQ_PH6 BFIN_PH_IRQ(6)
297#define IRQ_PH7 BFIN_PH_IRQ(7)
298#define IRQ_PH8 BFIN_PH_IRQ(8)
299#define IRQ_PH9 BFIN_PH_IRQ(9)
300#define IRQ_PH10 BFIN_PH_IRQ(10)
301#define IRQ_PH11 BFIN_PH_IRQ(11)
302#define IRQ_PH12 BFIN_PH_IRQ(12)
303#define IRQ_PH13 BFIN_PH_IRQ(13)
304#define IRQ_PH14 BFIN_PH_IRQ(14) /* N/A */
305#define IRQ_PH15 BFIN_PH_IRQ(15) /* N/A */
306
307#define BFIN_PI_IRQ(x) ((x) + IRQ_PH15 + 1)
308#define IRQ_PI0 BFIN_PI_IRQ(0)
309#define IRQ_PI1 BFIN_PI_IRQ(1)
310#define IRQ_PI2 BFIN_PI_IRQ(2)
311#define IRQ_PI3 BFIN_PI_IRQ(3)
312#define IRQ_PI4 BFIN_PI_IRQ(4)
313#define IRQ_PI5 BFIN_PI_IRQ(5)
314#define IRQ_PI6 BFIN_PI_IRQ(6)
315#define IRQ_PI7 BFIN_PI_IRQ(7)
316#define IRQ_PI8 BFIN_PI_IRQ(8)
317#define IRQ_PI9 BFIN_PI_IRQ(9)
318#define IRQ_PI10 BFIN_PI_IRQ(10)
319#define IRQ_PI11 BFIN_PI_IRQ(11)
320#define IRQ_PI12 BFIN_PI_IRQ(12)
321#define IRQ_PI13 BFIN_PI_IRQ(13)
322#define IRQ_PI14 BFIN_PI_IRQ(14)
323#define IRQ_PI15 BFIN_PI_IRQ(15)
324
325#define BFIN_PJ_IRQ(x) ((x) + IRQ_PI15 + 1)
326#define IRQ_PJ0 BFIN_PJ_IRQ(0)
327#define IRQ_PJ1 BFIN_PJ_IRQ(1)
328#define IRQ_PJ2 BFIN_PJ_IRQ(2)
329#define IRQ_PJ3 BFIN_PJ_IRQ(3)
330#define IRQ_PJ4 BFIN_PJ_IRQ(4)
331#define IRQ_PJ5 BFIN_PJ_IRQ(5)
332#define IRQ_PJ6 BFIN_PJ_IRQ(6)
333#define IRQ_PJ7 BFIN_PJ_IRQ(7)
334#define IRQ_PJ8 BFIN_PJ_IRQ(8)
335#define IRQ_PJ9 BFIN_PJ_IRQ(9)
336#define IRQ_PJ10 BFIN_PJ_IRQ(10)
337#define IRQ_PJ11 BFIN_PJ_IRQ(11)
338#define IRQ_PJ12 BFIN_PJ_IRQ(12)
339#define IRQ_PJ13 BFIN_PJ_IRQ(13)
340#define IRQ_PJ14 BFIN_PJ_IRQ(14) /* N/A */
341#define IRQ_PJ15 BFIN_PJ_IRQ(15) /* N/A */
342
343#define GPIO_IRQ_BASE IRQ_PA0
344
345#define NR_IRQS (IRQ_PJ15+1)
346
347/* For compatibility reasons with existing code */
348
349#define IRQ_DMAC0_ERR IRQ_DMAC0_ERROR
350#define IRQ_EPPI0_ERR IRQ_EPPI0_ERROR
351#define IRQ_SPORT0_ERR IRQ_SPORT0_ERROR
352#define IRQ_SPORT1_ERR IRQ_SPORT1_ERROR
353#define IRQ_SPI0_ERR IRQ_SPI0_ERROR
354#define IRQ_UART0_ERR IRQ_UART0_ERROR
355#define IRQ_DMAC1_ERR IRQ_DMAC1_ERROR
356#define IRQ_SPORT2_ERR IRQ_SPORT2_ERROR
357#define IRQ_SPORT3_ERR IRQ_SPORT3_ERROR
358#define IRQ_SPI1_ERR IRQ_SPI1_ERROR
359#define IRQ_SPI2_ERR IRQ_SPI2_ERROR
360#define IRQ_UART1_ERR IRQ_UART1_ERROR
361#define IRQ_UART2_ERR IRQ_UART2_ERROR
362#define IRQ_CAN0_ERR IRQ_CAN0_ERROR
363#define IRQ_MXVR_ERR IRQ_MXVR_ERROR
364#define IRQ_EPP1_ERR IRQ_EPP1_ERROR
365#define IRQ_EPP2_ERR IRQ_EPP2_ERROR
366#define IRQ_UART3_ERR IRQ_UART3_ERROR
367#define IRQ_HOST_ERR IRQ_HOST_ERROR
368#define IRQ_PIXC_ERR IRQ_PIXC_ERROR
369#define IRQ_NFC_ERR IRQ_NFC_ERROR
370#define IRQ_ATAPI_ERR IRQ_ATAPI_ERROR
371#define IRQ_CAN1_ERR IRQ_CAN1_ERROR
372#define IRQ_HS_DMA_ERR IRQ_HS_DMA_ERROR
373
374
375#define IVG7 7
376#define IVG8 8
377#define IVG9 9
378#define IVG10 10
379#define IVG11 11
380#define IVG12 12
381#define IVG13 13
382#define IVG14 14
383#define IVG15 15
384
385/* IAR0 BIT FIELDS */
386#define IRQ_PLL_WAKEUP_POS 0
387#define IRQ_DMAC0_ERR_POS 4
388#define IRQ_EPPI0_ERR_POS 8
389#define IRQ_SPORT0_ERR_POS 12
390#define IRQ_SPORT1_ERR_POS 16
391#define IRQ_SPI0_ERR_POS 20
392#define IRQ_UART0_ERR_POS 24
393#define IRQ_RTC_POS 28
394
395/* IAR1 BIT FIELDS */
396#define IRQ_EPPI0_POS 0
397#define IRQ_SPORT0_RX_POS 4
398#define IRQ_SPORT0_TX_POS 8
399#define IRQ_SPORT1_RX_POS 12
400#define IRQ_SPORT1_TX_POS 16
401#define IRQ_SPI0_POS 20
402#define IRQ_UART0_RX_POS 24
403#define IRQ_UART0_TX_POS 28
404
405/* IAR2 BIT FIELDS */
406#define IRQ_TIMER8_POS 0
407#define IRQ_TIMER9_POS 4
408#define IRQ_TIMER10_POS 8
409#define IRQ_PINT0_POS 12
410#define IRQ_PINT1_POS 16
411#define IRQ_MDMAS0_POS 20
412#define IRQ_MDMAS1_POS 24
413#define IRQ_WATCH_POS 28
414
415/* IAR3 BIT FIELDS */
416#define IRQ_DMAC1_ERR_POS 0
417#define IRQ_SPORT2_ERR_POS 4
418#define IRQ_SPORT3_ERR_POS 8
419#define IRQ_MXVR_DATA_POS 12
420#define IRQ_SPI1_ERR_POS 16
421#define IRQ_SPI2_ERR_POS 20
422#define IRQ_UART1_ERR_POS 24
423#define IRQ_UART2_ERR_POS 28
424
425/* IAR4 BIT FILEDS */
426#define IRQ_CAN0_ERR_POS 0
427#define IRQ_SPORT2_RX_POS 4
428#define IRQ_UART2_RX_POS 4
429#define IRQ_SPORT2_TX_POS 8
430#define IRQ_UART2_TX_POS 8
431#define IRQ_SPORT3_RX_POS 12
432#define IRQ_UART3_RX_POS 12
433#define IRQ_SPORT3_TX_POS 16
434#define IRQ_UART3_TX_POS 16
435#define IRQ_EPPI1_POS 20
436#define IRQ_EPPI2_POS 24
437#define IRQ_SPI1_POS 28
438
439/* IAR5 BIT FIELDS */
440#define IRQ_SPI2_POS 0
441#define IRQ_UART1_RX_POS 4
442#define IRQ_UART1_TX_POS 8
443#define IRQ_ATAPI_RX_POS 12
444#define IRQ_ATAPI_TX_POS 16
445#define IRQ_TWI0_POS 20
446#define IRQ_TWI1_POS 24
447#define IRQ_CAN0_RX_POS 28
448
449/* IAR6 BIT FIELDS */
450#define IRQ_CAN0_TX_POS 0
451#define IRQ_MDMAS2_POS 4
452#define IRQ_MDMAS3_POS 8
453#define IRQ_MXVR_ERR_POS 12
454#define IRQ_MXVR_MSG_POS 16
455#define IRQ_MXVR_PKT_POS 20
456#define IRQ_EPPI1_ERR_POS 24
457#define IRQ_EPPI2_ERR_POS 28
458
459/* IAR7 BIT FIELDS */
460#define IRQ_UART3_ERR_POS 0
461#define IRQ_HOST_ERR_POS 4
462#define IRQ_PIXC_ERR_POS 12
463#define IRQ_NFC_ERR_POS 16
464#define IRQ_ATAPI_ERR_POS 20
465#define IRQ_CAN1_ERR_POS 24
466#define IRQ_HS_DMA_ERR_POS 28
467
468/* IAR8 BIT FIELDS */
469#define IRQ_PIXC_IN0_POS 0
470#define IRQ_PIXC_IN1_POS 4
471#define IRQ_PIXC_OUT_POS 8
472#define IRQ_SDH_POS 12
473#define IRQ_CNT_POS 16
474#define IRQ_KEY_POS 20
475#define IRQ_CAN1_RX_POS 24
476#define IRQ_CAN1_TX_POS 28
477
478/* IAR9 BIT FIELDS */
479#define IRQ_SDH_MASK0_POS 0
480#define IRQ_SDH_MASK1_POS 4
481#define IRQ_USB_INT0_POS 12
482#define IRQ_USB_INT1_POS 16
483#define IRQ_USB_INT2_POS 20
484#define IRQ_USB_DMA_POS 24
485#define IRQ_OTPSEC_POS 28
486
487/* IAR10 BIT FIELDS */
488#define IRQ_TIMER0_POS 24
489#define IRQ_TIMER1_POS 28
490
491/* IAR11 BIT FIELDS */
492#define IRQ_TIMER2_POS 0
493#define IRQ_TIMER3_POS 4
494#define IRQ_TIMER4_POS 8
495#define IRQ_TIMER5_POS 12
496#define IRQ_TIMER6_POS 16
497#define IRQ_TIMER7_POS 20
498#define IRQ_PINT2_POS 24
499#define IRQ_PINT3_POS 28
500
501#endif /* _BF548_IRQ_H_ */
diff --git a/arch/blackfin/mach-bf548/include/mach/mem_init.h b/arch/blackfin/mach-bf548/include/mach/mem_init.h
new file mode 100644
index 000000000000..ab0b863eee66
--- /dev/null
+++ b/arch/blackfin/mach-bf548/include/mach/mem_init.h
@@ -0,0 +1,255 @@
1/*
2 * File: include/asm-blackfin/mach-bf548/mem_init.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 * Copyright 2004-2006 Analog Devices Inc.
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31#define MIN_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000 + 1)
32#define MAX_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000)
33#define DDR_CLK_HZ(x) (1000*1000*1000/x)
34
35#if (CONFIG_MEM_MT46V32M16_6T)
36#define DDR_SIZE DEVSZ_512
37#define DDR_WIDTH DEVWD_16
38#define DDR_MAX_tCK 13
39
40#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(60))
41#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(42))
42#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15))
43#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(72))
44#define DDR_tREFI DDR_TREFI(MAX_DDR_SCLK(7800))
45
46#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15))
47#define DDR_tWTR DDR_TWTR(1)
48#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(12))
49#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15))
50#endif
51
52#if (CONFIG_MEM_MT46V32M16_5B)
53#define DDR_SIZE DEVSZ_512
54#define DDR_WIDTH DEVWD_16
55#define DDR_MAX_tCK 13
56
57#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(55))
58#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(40))
59#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15))
60#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(70))
61#define DDR_tREFI DDR_TREFI(MAX_DDR_SCLK(7800))
62
63#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15))
64#define DDR_tWTR DDR_TWTR(2)
65#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(10))
66#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15))
67#endif
68
69#if (CONFIG_MEM_GENERIC_BOARD)
70#define DDR_SIZE DEVSZ_512
71#define DDR_WIDTH DEVWD_16
72#define DDR_MAX_tCK 13
73
74#define DDR_tRCD DDR_TRCD(3)
75#define DDR_tWTR DDR_TWTR(2)
76#define DDR_tWR DDR_TWR(2)
77#define DDR_tMRD DDR_TMRD(2)
78#define DDR_tRP DDR_TRP(3)
79#define DDR_tRAS DDR_TRAS(7)
80#define DDR_tRC DDR_TRC(10)
81#define DDR_tRFC DDR_TRFC(12)
82#define DDR_tREFI DDR_TREFI(1288)
83#endif
84
85#if (CONFIG_SCLK_HZ < DDR_CLK_HZ(DDR_MAX_tCK))
86# error "CONFIG_SCLK_HZ is too small (<DDR_CLK_HZ(DDR_MAX_tCK) Hz)."
87#elif(CONFIG_SCLK_HZ <= 133333333)
88# define DDR_CL CL_2
89#else
90# error "CONFIG_SCLK_HZ is too large (>133333333 Hz)."
91#endif
92
93
94#define mem_DDRCTL0 (DDR_tRP | DDR_tRAS | DDR_tRC | DDR_tRFC | DDR_tREFI)
95#define mem_DDRCTL1 (DDR_DATWIDTH | EXTBANK_1 | DDR_SIZE | DDR_WIDTH | DDR_tWTR \
96 | DDR_tMRD | DDR_tWR | DDR_tRCD)
97#define mem_DDRCTL2 DDR_CL
98
99
100#if defined CONFIG_CLKIN_HALF
101#define CLKIN_HALF 1
102#else
103#define CLKIN_HALF 0
104#endif
105
106#if defined CONFIG_PLL_BYPASS
107#define PLL_BYPASS 1
108#else
109#define PLL_BYPASS 0
110#endif
111
112/***************************************Currently Not Being Used *********************************/
113#define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
114#define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
115#define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ))
116#define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
117#define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
118
119#if (flash_EBIU_AMBCTL_TT > 3)
120#define flash_EBIU_AMBCTL0_TT B0TT_4
121#endif
122#if (flash_EBIU_AMBCTL_TT == 3)
123#define flash_EBIU_AMBCTL0_TT B0TT_3
124#endif
125#if (flash_EBIU_AMBCTL_TT == 2)
126#define flash_EBIU_AMBCTL0_TT B0TT_2
127#endif
128#if (flash_EBIU_AMBCTL_TT < 2)
129#define flash_EBIU_AMBCTL0_TT B0TT_1
130#endif
131
132#if (flash_EBIU_AMBCTL_ST > 3)
133#define flash_EBIU_AMBCTL0_ST B0ST_4
134#endif
135#if (flash_EBIU_AMBCTL_ST == 3)
136#define flash_EBIU_AMBCTL0_ST B0ST_3
137#endif
138#if (flash_EBIU_AMBCTL_ST == 2)
139#define flash_EBIU_AMBCTL0_ST B0ST_2
140#endif
141#if (flash_EBIU_AMBCTL_ST < 2)
142#define flash_EBIU_AMBCTL0_ST B0ST_1
143#endif
144
145#if (flash_EBIU_AMBCTL_HT > 2)
146#define flash_EBIU_AMBCTL0_HT B0HT_3
147#endif
148#if (flash_EBIU_AMBCTL_HT == 2)
149#define flash_EBIU_AMBCTL0_HT B0HT_2
150#endif
151#if (flash_EBIU_AMBCTL_HT == 1)
152#define flash_EBIU_AMBCTL0_HT B0HT_1
153#endif
154#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
155#define flash_EBIU_AMBCTL0_HT B0HT_0
156#endif
157#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
158#define flash_EBIU_AMBCTL0_HT B0HT_1
159#endif
160
161#if (flash_EBIU_AMBCTL_WAT > 14)
162#define flash_EBIU_AMBCTL0_WAT B0WAT_15
163#endif
164#if (flash_EBIU_AMBCTL_WAT == 14)
165#define flash_EBIU_AMBCTL0_WAT B0WAT_14
166#endif
167#if (flash_EBIU_AMBCTL_WAT == 13)
168#define flash_EBIU_AMBCTL0_WAT B0WAT_13
169#endif
170#if (flash_EBIU_AMBCTL_WAT == 12)
171#define flash_EBIU_AMBCTL0_WAT B0WAT_12
172#endif
173#if (flash_EBIU_AMBCTL_WAT == 11)
174#define flash_EBIU_AMBCTL0_WAT B0WAT_11
175#endif
176#if (flash_EBIU_AMBCTL_WAT == 10)
177#define flash_EBIU_AMBCTL0_WAT B0WAT_10
178#endif
179#if (flash_EBIU_AMBCTL_WAT == 9)
180#define flash_EBIU_AMBCTL0_WAT B0WAT_9
181#endif
182#if (flash_EBIU_AMBCTL_WAT == 8)
183#define flash_EBIU_AMBCTL0_WAT B0WAT_8
184#endif
185#if (flash_EBIU_AMBCTL_WAT == 7)
186#define flash_EBIU_AMBCTL0_WAT B0WAT_7
187#endif
188#if (flash_EBIU_AMBCTL_WAT == 6)
189#define flash_EBIU_AMBCTL0_WAT B0WAT_6
190#endif
191#if (flash_EBIU_AMBCTL_WAT == 5)
192#define flash_EBIU_AMBCTL0_WAT B0WAT_5
193#endif
194#if (flash_EBIU_AMBCTL_WAT == 4)
195#define flash_EBIU_AMBCTL0_WAT B0WAT_4
196#endif
197#if (flash_EBIU_AMBCTL_WAT == 3)
198#define flash_EBIU_AMBCTL0_WAT B0WAT_3
199#endif
200#if (flash_EBIU_AMBCTL_WAT == 2)
201#define flash_EBIU_AMBCTL0_WAT B0WAT_2
202#endif
203#if (flash_EBIU_AMBCTL_WAT == 1)
204#define flash_EBIU_AMBCTL0_WAT B0WAT_1
205#endif
206
207#if (flash_EBIU_AMBCTL_RAT > 14)
208#define flash_EBIU_AMBCTL0_RAT B0RAT_15
209#endif
210#if (flash_EBIU_AMBCTL_RAT == 14)
211#define flash_EBIU_AMBCTL0_RAT B0RAT_14
212#endif
213#if (flash_EBIU_AMBCTL_RAT == 13)
214#define flash_EBIU_AMBCTL0_RAT B0RAT_13
215#endif
216#if (flash_EBIU_AMBCTL_RAT == 12)
217#define flash_EBIU_AMBCTL0_RAT B0RAT_12
218#endif
219#if (flash_EBIU_AMBCTL_RAT == 11)
220#define flash_EBIU_AMBCTL0_RAT B0RAT_11
221#endif
222#if (flash_EBIU_AMBCTL_RAT == 10)
223#define flash_EBIU_AMBCTL0_RAT B0RAT_10
224#endif
225#if (flash_EBIU_AMBCTL_RAT == 9)
226#define flash_EBIU_AMBCTL0_RAT B0RAT_9
227#endif
228#if (flash_EBIU_AMBCTL_RAT == 8)
229#define flash_EBIU_AMBCTL0_RAT B0RAT_8
230#endif
231#if (flash_EBIU_AMBCTL_RAT == 7)
232#define flash_EBIU_AMBCTL0_RAT B0RAT_7
233#endif
234#if (flash_EBIU_AMBCTL_RAT == 6)
235#define flash_EBIU_AMBCTL0_RAT B0RAT_6
236#endif
237#if (flash_EBIU_AMBCTL_RAT == 5)
238#define flash_EBIU_AMBCTL0_RAT B0RAT_5
239#endif
240#if (flash_EBIU_AMBCTL_RAT == 4)
241#define flash_EBIU_AMBCTL0_RAT B0RAT_4
242#endif
243#if (flash_EBIU_AMBCTL_RAT == 3)
244#define flash_EBIU_AMBCTL0_RAT B0RAT_3
245#endif
246#if (flash_EBIU_AMBCTL_RAT == 2)
247#define flash_EBIU_AMBCTL0_RAT B0RAT_2
248#endif
249#if (flash_EBIU_AMBCTL_RAT == 1)
250#define flash_EBIU_AMBCTL0_RAT B0RAT_1
251#endif
252
253#define flash_EBIU_AMBCTL0 \
254 (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
255 flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
diff --git a/arch/blackfin/mach-bf548/include/mach/mem_map.h b/arch/blackfin/mach-bf548/include/mach/mem_map.h
new file mode 100644
index 000000000000..f99f47bc3a07
--- /dev/null
+++ b/arch/blackfin/mach-bf548/include/mach/mem_map.h
@@ -0,0 +1,111 @@
1/*
2 * file: include/asm-blackfin/mach-bf548/mem_map.h
3 * based on:
4 * author:
5 *
6 * created:
7 * description:
8 * Memory MAP Common header file for blackfin BF537/6/4 of processors.
9 * rev:
10 *
11 * modified:
12 *
13 * bugs: enter bugs at http://blackfin.uclinux.org/
14 *
15 * this program is free software; you can redistribute it and/or modify
16 * it under the terms of the gnu general public license as published by
17 * the free software foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * this program is distributed in the hope that it will be useful,
21 * but without any warranty; without even the implied warranty of
22 * merchantability or fitness for a particular purpose. see the
23 * gnu general public license for more details.
24 *
25 * you should have received a copy of the gnu general public license
26 * along with this program; see the file copying.
27 * if not, write to the free software foundation,
28 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
29 */
30
31#ifndef _MEM_MAP_548_H_
32#define _MEM_MAP_548_H_
33
34#define COREMMR_BASE 0xFFE00000 /* Core MMRs */
35#define SYSMMR_BASE 0xFFC00000 /* System MMRs */
36
37/* Async Memory Banks */
38#define ASYNC_BANK3_BASE 0x2C000000 /* Async Bank 3 */
39#define ASYNC_BANK3_SIZE 0x04000000 /* 64M */
40#define ASYNC_BANK2_BASE 0x28000000 /* Async Bank 2 */
41#define ASYNC_BANK2_SIZE 0x04000000 /* 64M */
42#define ASYNC_BANK1_BASE 0x24000000 /* Async Bank 1 */
43#define ASYNC_BANK1_SIZE 0x04000000 /* 64M */
44#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
45#define ASYNC_BANK0_SIZE 0x04000000 /* 64M */
46
47/* Boot ROM Memory */
48
49#define BOOT_ROM_START 0xEF000000
50#define BOOT_ROM_LENGTH 0x1000
51
52/* L1 Instruction ROM */
53
54#define L1_ROM_START 0xFFA14000
55#define L1_ROM_LENGTH 0x10000
56
57/* Level 1 Memory */
58
59/* Memory Map for ADSP-BF548 processors */
60#ifdef CONFIG_BFIN_ICACHE
61#define BFIN_ICACHESIZE (16*1024)
62#else
63#define BFIN_ICACHESIZE (0*1024)
64#endif
65
66#define L1_CODE_START 0xFFA00000
67#define L1_DATA_A_START 0xFF800000
68#define L1_DATA_B_START 0xFF900000
69
70#define L1_CODE_LENGTH 0xC000
71
72#ifdef CONFIG_BFIN_DCACHE
73
74#ifdef CONFIG_BFIN_DCACHE_BANKA
75#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
76#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
77#define L1_DATA_B_LENGTH 0x8000
78#define BFIN_DCACHESIZE (16*1024)
79#define BFIN_DSUPBANKS 1
80#else
81#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
82#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
83#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
84#define BFIN_DCACHESIZE (32*1024)
85#define BFIN_DSUPBANKS 2
86#endif
87
88#else
89#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
90#define L1_DATA_A_LENGTH 0x8000
91#define L1_DATA_B_LENGTH 0x8000
92#define BFIN_DCACHESIZE (0*1024)
93#define BFIN_DSUPBANKS 0
94#endif /*CONFIG_BFIN_DCACHE*/
95
96/* Level 2 Memory */
97#if !defined(CONFIG_BF542)
98# define L2_START 0xFEB00000
99# if defined(CONFIG_BF544)
100# define L2_LENGTH 0x10000
101# else
102# define L2_LENGTH 0x20000
103# endif
104#endif
105
106/* Scratch Pad Memory */
107
108#define L1_SCRATCH_START 0xFFB00000
109#define L1_SCRATCH_LENGTH 0x1000
110
111#endif/* _MEM_MAP_548_H_ */
diff --git a/arch/blackfin/mach-bf548/include/mach/portmux.h b/arch/blackfin/mach-bf548/include/mach/portmux.h
new file mode 100644
index 000000000000..8177a567dcdb
--- /dev/null
+++ b/arch/blackfin/mach-bf548/include/mach/portmux.h
@@ -0,0 +1,286 @@
1#ifndef _MACH_PORTMUX_H_
2#define _MACH_PORTMUX_H_
3
4#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
5
6#define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0))
7#define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0))
8#define P_SPORT2_DTPRI (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0))
9#define P_SPORT2_TSCLK (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(0))
10#define P_SPORT2_RFS (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(0))
11#define P_SPORT2_DRSEC (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(0))
12#define P_SPORT2_DRPRI (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(0))
13#define P_SPORT2_RSCLK (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(0))
14#define P_SPORT3_TFS (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(0))
15#define P_SPORT3_DTSEC (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(0))
16#define P_SPORT3_DTPRI (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(0))
17#define P_SPORT3_TSCLK (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(0))
18#define P_SPORT3_RFS (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(0))
19#define P_SPORT3_DRSEC (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(0))
20#define P_SPORT3_DRPRI (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(0))
21#define P_SPORT3_RSCLK (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(0))
22#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(1))
23#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(1))
24#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(1))
25#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(1))
26
27#define P_TWI1_SCL (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(0))
28#define P_TWI1_SDA (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(0))
29#define P_UART3_RTS (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(0))
30#define P_UART3_CTS (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(0))
31#define P_UART2_TX (P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(0))
32#define P_UART2_RX (P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(0))
33#define P_UART3_TX (P_DEFINED | P_IDENT(GPIO_PB6) | P_FUNCT(0))
34#define P_UART3_RX (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(0))
35#define P_SPI2_SS (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(0))
36#define P_SPI2_SSEL1 (P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(0))
37#define P_SPI2_SSEL2 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(0))
38#define P_SPI2_SSEL3 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(0))
39#define P_SPI2_SCK (P_DEFINED | P_IDENT(GPIO_PB12) | P_FUNCT(0))
40#define P_SPI2_MOSI (P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(0))
41#define P_SPI2_MISO (P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(0))
42#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(1))
43#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(1))
44#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(1))
45#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(1))
46
47#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(0))
48#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(0))
49#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(0))
50#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(0))
51#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(0))
52#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(0))
53#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(0))
54#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(0))
55#define P_SD_D0 (P_DEFINED | P_IDENT(GPIO_PC8) | P_FUNCT(0))
56#define P_SD_D1 (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(0))
57#define P_SD_D2 (P_DEFINED | P_IDENT(GPIO_PC10) | P_FUNCT(0))
58#define P_SD_D3 (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(0))
59#define P_SD_CLK (P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(0))
60#define P_SD_CMD (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(0))
61#define P_MMCLK (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(1))
62#define P_MBCLK (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(1))
63
64#define P_PPI1_D0 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(0))
65#define P_PPI1_D1 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(0))
66#define P_PPI1_D2 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(0))
67#define P_PPI1_D3 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(0))
68#define P_PPI1_D4 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(0))
69#define P_PPI1_D5 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(0))
70#define P_PPI1_D6 (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(0))
71#define P_PPI1_D7 (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(0))
72#define P_PPI1_D8 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(0))
73#define P_PPI1_D9 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(0))
74#define P_PPI1_D10 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(0))
75#define P_PPI1_D11 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(0))
76#define P_PPI1_D12 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(0))
77#define P_PPI1_D13 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(0))
78#define P_PPI1_D14 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(0))
79#define P_PPI1_D15 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(0))
80
81#define P_HOST_D8 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(1))
82#define P_HOST_D9 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(1))
83#define P_HOST_D10 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(1))
84#define P_HOST_D11 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(1))
85#define P_HOST_D12 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(1))
86#define P_HOST_D13 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(1))
87#define P_HOST_D14 (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(1))
88#define P_HOST_D15 (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(1))
89#define P_HOST_D0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(1))
90#define P_HOST_D1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(1))
91#define P_HOST_D2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(1))
92#define P_HOST_D3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(1))
93#define P_HOST_D4 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(1))
94#define P_HOST_D5 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(1))
95#define P_HOST_D6 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(1))
96#define P_HOST_D7 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(1))
97#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(2))
98#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(2))
99#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(2))
100#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(2))
101#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(2))
102#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(2))
103#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(2))
104#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(2))
105#define P_PPI2_D0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(2))
106#define P_PPI2_D1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(2))
107#define P_PPI2_D2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(2))
108#define P_PPI2_D3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(2))
109#define P_PPI2_D4 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(2))
110#define P_PPI2_D5 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(2))
111#define P_PPI2_D6 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(2))
112#define P_PPI2_D7 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(2))
113#define P_PPI0_D18 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(3))
114#define P_PPI0_D19 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(3))
115#define P_PPI0_D20 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(3))
116#define P_PPI0_D21 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(3))
117#define P_PPI0_D22 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(3))
118#define P_PPI0_D23 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(3))
119#define P_KEY_ROW0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(3))
120#define P_KEY_ROW1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(3))
121#define P_KEY_ROW2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(3))
122#define P_KEY_ROW3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(3))
123#define P_KEY_COL0 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(3))
124#define P_KEY_COL1 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(3))
125#define P_KEY_COL2 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(3))
126#define P_KEY_COL3 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(3))
127
128#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(0))
129#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(0))
130#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(0))
131#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(0))
132#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(0))
133#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(0))
134#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(0))
135#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(0))
136#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PE8) | P_FUNCT(0))
137#define P_UART1_RTS (P_DEFINED | P_IDENT(GPIO_PE9) | P_FUNCT(0))
138#define P_UART1_CTS (P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(0))
139#define P_PPI1_CLK (P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(0))
140#define P_PPI1_FS1 (P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(0))
141#define P_PPI1_FS2 (P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(0))
142#define P_TWI0_SCL (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(0))
143#define P_TWI0_SDA (P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(0))
144#define P_KEY_COL7 (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(1))
145#define P_KEY_ROW6 (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(1))
146#define P_KEY_COL6 (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(1))
147#define P_KEY_ROW5 (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(1))
148#define P_KEY_COL5 (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(1))
149#define P_KEY_ROW4 (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(1))
150#define P_KEY_COL4 (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(1))
151#define P_KEY_ROW7 (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(1))
152
153#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
154#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
155#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
156#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
157#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
158#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
159#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
160#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
161#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
162#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
163#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
164#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
165#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
166#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
167#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
168#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
169#define P_ATAPI_D0A (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
170#define P_ATAPI_D1A (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
171#define P_ATAPI_D2A (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
172#define P_ATAPI_D3A (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
173#define P_ATAPI_D4A (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
174#define P_ATAPI_D5A (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
175#define P_ATAPI_D6A (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
176#define P_ATAPI_D7A (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
177#define P_ATAPI_D8A (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
178#define P_ATAPI_D9A (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
179#define P_ATAPI_D10A (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
180#define P_ATAPI_D11A (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
181#define P_ATAPI_D12A (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
182#define P_ATAPI_D13A (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
183#define P_ATAPI_D14A (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
184#define P_ATAPI_D15A (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
185
186#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
187#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
188#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
189#define P_PPI0_D16 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
190#define P_PPI0_D17 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
191#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
192#define P_SPI1_SSEL2 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
193#define P_SPI1_SSEL3 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
194#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
195#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
196#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
197#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
198#define P_CAN0_TX (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
199#define P_CAN0_RX (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
200#define P_CAN1_TX (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
201#define P_CAN1_RX (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
202#define P_ATAPI_A0A (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(1))
203#define P_ATAPI_A1A (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
204#define P_ATAPI_A2A (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
205#define P_HOST_CE (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
206#define P_HOST_RD (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
207#define P_HOST_WR (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
208#define P_MTXONB (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
209#define P_PPI2_FS2 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(2))
210#define P_PPI2_FS1 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
211#define P_PPI2_CLK (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
212#define P_CNT_CZM (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(3))
213
214#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
215#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
216#define P_ATAPI_RESET (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
217#define P_HOST_ADDR (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
218#define P_HOST_ACK (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
219#define P_MTX (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
220#define P_MRX (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
221#define P_MRXONB (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
222#define P_A4 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0))
223#define P_A5 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0))
224#define P_A6 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0))
225#define P_A7 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0))
226#define P_A8 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0))
227#define P_A9 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0))
228#define P_PPI1_FS3 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
229#define P_PPI2_FS3 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1))
230#define P_TMR8 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1))
231#define P_TMR9 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1))
232#define P_TMR10 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1))
233#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1))
234#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
235#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2))
236#define P_CNT_CDG (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2))
237#define P_CNT_CUD (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2))
238
239#define P_A10 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI0) | P_FUNCT(0))
240#define P_A11 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI1) | P_FUNCT(0))
241#define P_A12 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI2) | P_FUNCT(0))
242#define P_A13 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI3) | P_FUNCT(0))
243#define P_A14 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI4) | P_FUNCT(0))
244#define P_A15 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI5) | P_FUNCT(0))
245#define P_A16 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI6) | P_FUNCT(0))
246#define P_A17 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI7) | P_FUNCT(0))
247#define P_A18 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI8) | P_FUNCT(0))
248#define P_A19 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI9) | P_FUNCT(0))
249#define P_A20 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI10) | P_FUNCT(0))
250#define P_A21 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI11) | P_FUNCT(0))
251#define P_A22 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI12) | P_FUNCT(0))
252#define P_A23 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI13) | P_FUNCT(0))
253#define P_A24 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI14) | P_FUNCT(0))
254#define P_A25 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI15) | P_FUNCT(0))
255#define P_NOR_CLK (P_DEFINED | P_IDENT(GPIO_PI15) | P_FUNCT(1))
256
257#define P_AMC_ARDY_NOR_WAIT (P_DEFINED | P_IDENT(GPIO_PJ0) | P_FUNCT(0))
258#define P_NAND_CE (P_DEFINED | P_IDENT(GPIO_PJ1) | P_FUNCT(0))
259#define P_NAND_RB (P_DEFINED | P_IDENT(GPIO_PJ2) | P_FUNCT(0))
260#define P_ATAPI_DIOR (P_DEFINED | P_IDENT(GPIO_PJ3) | P_FUNCT(0))
261#define P_ATAPI_DIOW (P_DEFINED | P_IDENT(GPIO_PJ4) | P_FUNCT(0))
262#define P_ATAPI_CS0 (P_DEFINED | P_IDENT(GPIO_PJ5) | P_FUNCT(0))
263#define P_ATAPI_CS1 (P_DEFINED | P_IDENT(GPIO_PJ6) | P_FUNCT(0))
264#define P_ATAPI_DMACK (P_DEFINED | P_IDENT(GPIO_PJ7) | P_FUNCT(0))
265#define P_ATAPI_DMARQ (P_DEFINED | P_IDENT(GPIO_PJ8) | P_FUNCT(0))
266#define P_ATAPI_INTRQ (P_DEFINED | P_IDENT(GPIO_PJ9) | P_FUNCT(0))
267#define P_ATAPI_IORDY (P_DEFINED | P_IDENT(GPIO_PJ10) | P_FUNCT(0))
268#define P_AMC_BR (P_DEFINED | P_IDENT(GPIO_PJ11) | P_FUNCT(0))
269#define P_AMC_BG (P_DEFINED | P_IDENT(GPIO_PJ12) | P_FUNCT(0))
270#define P_AMC_BGH (P_DEFINED | P_IDENT(GPIO_PJ13) | P_FUNCT(0))
271
272
273#define P_NAND_D0 (P_DONTCARE)
274#define P_NAND_D1 (P_DONTCARE)
275#define P_NAND_D2 (P_DONTCARE)
276#define P_NAND_D3 (P_DONTCARE)
277#define P_NAND_D4 (P_DONTCARE)
278#define P_NAND_D5 (P_DONTCARE)
279#define P_NAND_D6 (P_DONTCARE)
280#define P_NAND_D7 (P_DONTCARE)
281#define P_NAND_WE (P_DONTCARE)
282#define P_NAND_RE (P_DONTCARE)
283#define P_NAND_CLE (P_DONTCARE)
284#define P_NAND_ALE (P_DONTCARE)
285
286#endif /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/mach-bf561/head.S b/arch/blackfin/mach-bf561/head.S
index c7a81e34703d..75ea6a905829 100644
--- a/arch/blackfin/mach-bf561/head.S
+++ b/arch/blackfin/mach-bf561/head.S
@@ -31,8 +31,8 @@
31#include <linux/init.h> 31#include <linux/init.h>
32#include <asm/blackfin.h> 32#include <asm/blackfin.h>
33#ifdef CONFIG_BFIN_KERNEL_CLOCK 33#ifdef CONFIG_BFIN_KERNEL_CLOCK
34#include <asm/mach-common/clocks.h> 34#include <asm/clocks.h>
35#include <asm/mach/mem_init.h> 35#include <mach/mem_init.h>
36#endif 36#endif
37 37
38.section .l1.text 38.section .l1.text
diff --git a/arch/blackfin/mach-bf561/include/mach/anomaly.h b/arch/blackfin/mach-bf561/include/mach/anomaly.h
new file mode 100644
index 000000000000..5c5d7d7d695f
--- /dev/null
+++ b/arch/blackfin/mach-bf561/include/mach/anomaly.h
@@ -0,0 +1,274 @@
1/*
2 * File: include/asm-blackfin/mach-bf561/anomaly.h
3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
4 *
5 * Copyright (C) 2004-2008 Analog Devices Inc.
6 * Licensed under the GPL-2 or later.
7 */
8
9/* This file shoule be up to date with:
10 * - Revision P, 02/08/2008; ADSP-BF561 Blackfin Processor Anomaly List
11 */
12
13#ifndef _MACH_ANOMALY_H_
14#define _MACH_ANOMALY_H_
15
16/* We do not support 0.1, 0.2, or 0.4 silicon - sorry */
17#if __SILICON_REVISION__ < 3 || __SILICON_REVISION__ == 4
18# error will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4
19#endif
20
21/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */
22#define ANOMALY_05000074 (1)
23/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */
24#define ANOMALY_05000099 (__SILICON_REVISION__ < 5)
25/* Trace Buffers may contain errors in emulation mode and/or exception, NMI, reset handlers */
26#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
27/* Testset instructions restricted to 32-bit aligned memory locations */
28#define ANOMALY_05000120 (1)
29/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
30#define ANOMALY_05000122 (1)
31/* Erroneous exception when enabling cache */
32#define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
33/* Signbits instruction not functional under certain conditions */
34#define ANOMALY_05000127 (1)
35/* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */
36#define ANOMALY_05000134 (__SILICON_REVISION__ < 3)
37/* Enable wires from the Data Watchpoint Address Control Register (WPDACTL) are swapped */
38#define ANOMALY_05000135 (__SILICON_REVISION__ < 3)
39/* Stall in multi-unit DMA operations */
40#define ANOMALY_05000136 (__SILICON_REVISION__ < 3)
41/* Allowing the SPORT RX FIFO to fill will cause an overflow */
42#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
43/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */
44#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
45/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
46#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
47/* DMA and TESTSET conflict when both are accessing external memory */
48#define ANOMALY_05000144 (__SILICON_REVISION__ < 3)
49/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */
50#define ANOMALY_05000145 (__SILICON_REVISION__ < 3)
51/* MDMA may lose the first few words of a descriptor chain */
52#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
53/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */
54#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
55/* IMDMA S1/D1 channel may stall */
56#define ANOMALY_05000149 (1)
57/* DMA engine may lose data due to incorrect handshaking */
58#define ANOMALY_05000150 (__SILICON_REVISION__ < 3)
59/* DMA stalls when all three controllers read data from the same source */
60#define ANOMALY_05000151 (__SILICON_REVISION__ < 3)
61/* Execution stall when executing in L2 and doing external accesses */
62#define ANOMALY_05000152 (__SILICON_REVISION__ < 3)
63/* Frame Delay in SPORT Multichannel Mode */
64#define ANOMALY_05000153 (__SILICON_REVISION__ < 3)
65/* SPORT TFS signal stays active in multichannel mode outside of valid channels */
66#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
67/* Timers in PWM-Out Mode with PPI GP Receive (Input) Mode with 0 Frame Syncs */
68#define ANOMALY_05000156 (__SILICON_REVISION__ < 4)
69/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */
70#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
71/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
72#define ANOMALY_05000159 (__SILICON_REVISION__ < 3)
73/* A read from external memory may return a wrong value with data cache enabled */
74#define ANOMALY_05000160 (__SILICON_REVISION__ < 3)
75/* Data Cache Fill data can be corrupted after/during Instruction DMA if certain core stalls exist */
76#define ANOMALY_05000161 (__SILICON_REVISION__ < 3)
77/* DMEM_CONTROL<12> is not set on Reset */
78#define ANOMALY_05000162 (__SILICON_REVISION__ < 3)
79/* SPORT transmit data is not gated by external frame sync in certain conditions */
80#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
81/* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */
82#define ANOMALY_05000166 (1)
83/* Turning Serial Ports on with External Frame Syncs */
84#define ANOMALY_05000167 (1)
85/* SDRAM auto-refresh and subsequent Power Ups */
86#define ANOMALY_05000168 (__SILICON_REVISION__ < 5)
87/* DATA CPLB page miss can result in lost write-through cache data writes */
88#define ANOMALY_05000169 (__SILICON_REVISION__ < 5)
89/* Boot-ROM code modifies SICA_IWRx wakeup registers */
90#define ANOMALY_05000171 (__SILICON_REVISION__ < 5)
91/* DSPID register values incorrect */
92#define ANOMALY_05000172 (__SILICON_REVISION__ < 3)
93/* DMA vs Core accesses to external memory */
94#define ANOMALY_05000173 (__SILICON_REVISION__ < 3)
95/* Cache Fill Buffer Data lost */
96#define ANOMALY_05000174 (__SILICON_REVISION__ < 5)
97/* Overlapping Sequencer and Memory Stalls */
98#define ANOMALY_05000175 (__SILICON_REVISION__ < 5)
99/* Multiplication of (-1) by (-1) followed by an accumulator saturation */
100#define ANOMALY_05000176 (__SILICON_REVISION__ < 5)
101/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
102#define ANOMALY_05000179 (__SILICON_REVISION__ < 5)
103/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
104#define ANOMALY_05000180 (1)
105/* Disabling the PPI resets the PPI configuration registers */
106#define ANOMALY_05000181 (__SILICON_REVISION__ < 5)
107/* IMDMA does not operate to full speed for 600MHz and higher devices */
108#define ANOMALY_05000182 (1)
109/* Timer Pin limitations for PPI TX Modes with External Frame Syncs */
110#define ANOMALY_05000184 (__SILICON_REVISION__ < 5)
111/* PPI TX Mode with 2 External Frame Syncs */
112#define ANOMALY_05000185 (__SILICON_REVISION__ < 5)
113/* PPI packing with Data Length greater than 8 bits (not a meaningful mode) */
114#define ANOMALY_05000186 (__SILICON_REVISION__ < 5)
115/* IMDMA Corrupted Data after a Halt */
116#define ANOMALY_05000187 (1)
117/* IMDMA Restrictions on Descriptor and Buffer Placement in Memory */
118#define ANOMALY_05000188 (__SILICON_REVISION__ < 5)
119/* False Protection Exceptions */
120#define ANOMALY_05000189 (__SILICON_REVISION__ < 5)
121/* PPI not functional at core voltage < 1Volt */
122#define ANOMALY_05000190 (1)
123/* PPI does not invert the Driving PPICLK edge in Transmit Modes */
124#define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
125/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
126#define ANOMALY_05000193 (__SILICON_REVISION__ < 5)
127/* Restarting SPORT in Specific Modes May Cause Data Corruption */
128#define ANOMALY_05000194 (__SILICON_REVISION__ < 5)
129/* Failing MMR Accesses When Stalled by Preceding Memory Read */
130#define ANOMALY_05000198 (__SILICON_REVISION__ < 5)
131/* Current DMA Address Shows Wrong Value During Carry Fix */
132#define ANOMALY_05000199 (__SILICON_REVISION__ < 5)
133/* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */
134#define ANOMALY_05000200 (__SILICON_REVISION__ < 5)
135/* Possible Infinite Stall with Specific Dual-DAG Situation */
136#define ANOMALY_05000202 (__SILICON_REVISION__ < 5)
137/* Incorrect data read with write-through cache and allocate cache lines on reads only mode */
138#define ANOMALY_05000204 (__SILICON_REVISION__ < 5)
139/* Specific sequence that can cause DMA error or DMA stopping */
140#define ANOMALY_05000205 (__SILICON_REVISION__ < 5)
141/* Recovery from "Brown-Out" Condition */
142#define ANOMALY_05000207 (__SILICON_REVISION__ < 5)
143/* VSTAT Status Bit in PLL_STAT Register Is Not Functional */
144#define ANOMALY_05000208 (1)
145/* Speed Path in Computational Unit Affects Certain Instructions */
146#define ANOMALY_05000209 (__SILICON_REVISION__ < 5)
147/* UART TX Interrupt Masked Erroneously */
148#define ANOMALY_05000215 (__SILICON_REVISION__ < 5)
149/* NMI Event at Boot Time Results in Unpredictable State */
150#define ANOMALY_05000219 (__SILICON_REVISION__ < 5)
151/* Data Corruption with Cached External Memory and Non-Cached On-Chip L2 Memory */
152#define ANOMALY_05000220 (__SILICON_REVISION__ < 5)
153/* Incorrect Pulse-Width of UART Start Bit */
154#define ANOMALY_05000225 (__SILICON_REVISION__ < 5)
155/* Scratchpad Memory Bank Reads May Return Incorrect Data */
156#define ANOMALY_05000227 (__SILICON_REVISION__ < 5)
157/* UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions */
158#define ANOMALY_05000230 (__SILICON_REVISION__ < 5)
159/* UART STB Bit Incorrectly Affects Receiver Setting */
160#define ANOMALY_05000231 (__SILICON_REVISION__ < 5)
161/* SPORT data transmit lines are incorrectly driven in multichannel mode */
162#define ANOMALY_05000232 (__SILICON_REVISION__ < 5)
163/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */
164#define ANOMALY_05000242 (__SILICON_REVISION__ < 5)
165/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
166#define ANOMALY_05000244 (__SILICON_REVISION__ < 5)
167/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
168#define ANOMALY_05000245 (__SILICON_REVISION__ < 5)
169/* TESTSET operation forces stall on the other core */
170#define ANOMALY_05000248 (__SILICON_REVISION__ < 5)
171/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
172#define ANOMALY_05000250 (__SILICON_REVISION__ > 2 && __SILICON_REVISION__ < 5)
173/* Exception Not Generated for MMR Accesses in Reserved Region */
174#define ANOMALY_05000251 (__SILICON_REVISION__ < 5)
175/* Maximum External Clock Speed for Timers */
176#define ANOMALY_05000253 (__SILICON_REVISION__ < 5)
177/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
178#define ANOMALY_05000254 (__SILICON_REVISION__ > 3)
179/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
180#define ANOMALY_05000257 (__SILICON_REVISION__ < 5)
181/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
182#define ANOMALY_05000258 (__SILICON_REVISION__ < 5)
183/* ICPLB_STATUS MMR Register May Be Corrupted */
184#define ANOMALY_05000260 (__SILICON_REVISION__ < 5)
185/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
186#define ANOMALY_05000261 (__SILICON_REVISION__ < 5)
187/* Stores To Data Cache May Be Lost */
188#define ANOMALY_05000262 (__SILICON_REVISION__ < 5)
189/* Hardware Loop Corrupted When Taking an ICPLB Exception */
190#define ANOMALY_05000263 (__SILICON_REVISION__ < 5)
191/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
192#define ANOMALY_05000264 (__SILICON_REVISION__ < 5)
193/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
194#define ANOMALY_05000265 (__SILICON_REVISION__ < 5)
195/* IMDMA destination IRQ status must be read prior to using IMDMA */
196#define ANOMALY_05000266 (__SILICON_REVISION__ > 3)
197/* IMDMA may corrupt data under certain conditions */
198#define ANOMALY_05000267 (1)
199/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */
200#define ANOMALY_05000269 (1)
201/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
202#define ANOMALY_05000270 (1)
203/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
204#define ANOMALY_05000272 (1)
205/* Data cache write back to external synchronous memory may be lost */
206#define ANOMALY_05000274 (1)
207/* PPI Timing and Sampling Information Updates */
208#define ANOMALY_05000275 (__SILICON_REVISION__ > 2)
209/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
210#define ANOMALY_05000276 (__SILICON_REVISION__ < 5)
211/* Writes to an I/O data register one SCLK cycle after an edge is detected may clear interrupt */
212#define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
213/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
214#define ANOMALY_05000278 (__SILICON_REVISION__ < 5)
215/* False Hardware Error Exception When ISR Context Is Not Restored */
216#define ANOMALY_05000281 (__SILICON_REVISION__ < 5)
217/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */
218#define ANOMALY_05000283 (1)
219/* A read will receive incorrect data under certain conditions */
220#define ANOMALY_05000287 (__SILICON_REVISION__ < 5)
221/* SPORTs May Receive Bad Data If FIFOs Fill Up */
222#define ANOMALY_05000288 (__SILICON_REVISION__ < 5)
223/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
224#define ANOMALY_05000301 (1)
225/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */
226#define ANOMALY_05000302 (1)
227/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */
228#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
229/* SCKELOW Bit Does Not Maintain State Through Hibernate */
230#define ANOMALY_05000307 (__SILICON_REVISION__ < 5)
231/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
232#define ANOMALY_05000310 (1)
233/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
234#define ANOMALY_05000312 (1)
235/* PPI Is Level-Sensitive on First Transfer */
236#define ANOMALY_05000313 (1)
237/* Killed System MMR Write Completes Erroneously On Next System MMR Access */
238#define ANOMALY_05000315 (1)
239/* PF2 Output Remains Asserted After SPI Master Boot */
240#define ANOMALY_05000320 (__SILICON_REVISION__ > 3)
241/* Erroneous GPIO Flag Pin Operations Under Specific Sequences */
242#define ANOMALY_05000323 (1)
243/* SPORT Secondary Receive Channel Not Functional When Word Length Exceeds 16 Bits */
244#define ANOMALY_05000326 (__SILICON_REVISION__ > 3)
245/* New Feature: 24-Bit SPI Boot Mode Support (Not Available On Older Silicon) */
246#define ANOMALY_05000331 (__SILICON_REVISION__ < 5)
247/* New Feature: Slave SPI Boot Mode Supported (Not Available On Older Silicon) */
248#define ANOMALY_05000332 (__SILICON_REVISION__ < 5)
249/* Flag Data Register Writes One SCLK Cycle After Edge Is Detected May Clear Interrupt Status */
250#define ANOMALY_05000333 (__SILICON_REVISION__ < 5)
251/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available on Older Silicon) */
252#define ANOMALY_05000339 (__SILICON_REVISION__ < 5)
253/* Memory DMA FIFO Causes Throughput Degradation on Writes to External Memory */
254#define ANOMALY_05000343 (__SILICON_REVISION__ < 5)
255/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
256#define ANOMALY_05000357 (1)
257/* Conflicting Column Address Widths Causes SDRAM Errors */
258#define ANOMALY_05000362 (1)
259/* UART Break Signal Issues */
260#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
261/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
262#define ANOMALY_05000366 (1)
263/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
264#define ANOMALY_05000371 (1)
265/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
266#define ANOMALY_05000403 (1)
267
268/* Anomalies that don't exist on this proc */
269#define ANOMALY_05000158 (0)
270#define ANOMALY_05000183 (0)
271#define ANOMALY_05000273 (0)
272#define ANOMALY_05000311 (0)
273
274#endif
diff --git a/arch/blackfin/mach-bf561/include/mach/bf561.h b/arch/blackfin/mach-bf561/include/mach/bf561.h
new file mode 100644
index 000000000000..3ef9e5f36136
--- /dev/null
+++ b/arch/blackfin/mach-bf561/include/mach/bf561.h
@@ -0,0 +1,223 @@
1/*
2 * File: include/asm-blackfin/mach-bf561/bf561.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#ifndef __MACH_BF561_H__
31#define __MACH_BF561_H__
32
33#define SUPPORTED_REVID 0x3
34
35#define OFFSET_(x) ((x) & 0x0000FFFF)
36
37/*some misc defines*/
38#define IMASK_IVG15 0x8000
39#define IMASK_IVG14 0x4000
40#define IMASK_IVG13 0x2000
41#define IMASK_IVG12 0x1000
42
43#define IMASK_IVG11 0x0800
44#define IMASK_IVG10 0x0400
45#define IMASK_IVG9 0x0200
46#define IMASK_IVG8 0x0100
47
48#define IMASK_IVG7 0x0080
49#define IMASK_IVGTMR 0x0040
50#define IMASK_IVGHW 0x0020
51
52/***************************
53 * Blackfin Cache setup
54 */
55
56
57#define BFIN_ISUBBANKS 4
58#define BFIN_IWAYS 4
59#define BFIN_ILINES 32
60
61#define BFIN_DSUBBANKS 4
62#define BFIN_DWAYS 2
63#define BFIN_DLINES 64
64
65#define WAY0_L 0x1
66#define WAY1_L 0x2
67#define WAY01_L 0x3
68#define WAY2_L 0x4
69#define WAY02_L 0x5
70#define WAY12_L 0x6
71#define WAY012_L 0x7
72
73#define WAY3_L 0x8
74#define WAY03_L 0x9
75#define WAY13_L 0xA
76#define WAY013_L 0xB
77
78#define WAY32_L 0xC
79#define WAY320_L 0xD
80#define WAY321_L 0xE
81#define WAYALL_L 0xF
82
83#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
84
85/* IAR0 BIT FIELDS */
86#define PLL_WAKEUP_BIT 0xFFFFFFFF
87#define DMA1_ERROR_BIT 0xFFFFFF0F
88#define DMA2_ERROR_BIT 0xFFFFF0FF
89#define IMDMA_ERROR_BIT 0xFFFF0FFF
90#define PPI1_ERROR_BIT 0xFFF0FFFF
91#define PPI2_ERROR_BIT 0xFF0FFFFF
92#define SPORT0_ERROR_BIT 0xF0FFFFFF
93#define SPORT1_ERROR_BIT 0x0FFFFFFF
94/* IAR1 BIT FIELDS */
95#define SPI_ERROR_BIT 0xFFFFFFFF
96#define UART_ERROR_BIT 0xFFFFFF0F
97#define RESERVED_ERROR_BIT 0xFFFFF0FF
98#define DMA1_0_BIT 0xFFFF0FFF
99#define DMA1_1_BIT 0xFFF0FFFF
100#define DMA1_2_BIT 0xFF0FFFFF
101#define DMA1_3_BIT 0xF0FFFFFF
102#define DMA1_4_BIT 0x0FFFFFFF
103/* IAR2 BIT FIELDS */
104#define DMA1_5_BIT 0xFFFFFFFF
105#define DMA1_6_BIT 0xFFFFFF0F
106#define DMA1_7_BIT 0xFFFFF0FF
107#define DMA1_8_BIT 0xFFFF0FFF
108#define DMA1_9_BIT 0xFFF0FFFF
109#define DMA1_10_BIT 0xFF0FFFFF
110#define DMA1_11_BIT 0xF0FFFFFF
111#define DMA2_0_BIT 0x0FFFFFFF
112/* IAR3 BIT FIELDS */
113#define DMA2_1_BIT 0xFFFFFFFF
114#define DMA2_2_BIT 0xFFFFFF0F
115#define DMA2_3_BIT 0xFFFFF0FF
116#define DMA2_4_BIT 0xFFFF0FFF
117#define DMA2_5_BIT 0xFFF0FFFF
118#define DMA2_6_BIT 0xFF0FFFFF
119#define DMA2_7_BIT 0xF0FFFFFF
120#define DMA2_8_BIT 0x0FFFFFFF
121/* IAR4 BIT FIELDS */
122#define DMA2_9_BIT 0xFFFFFFFF
123#define DMA2_10_BIT 0xFFFFFF0F
124#define DMA2_11_BIT 0xFFFFF0FF
125#define TIMER0_BIT 0xFFFF0FFF
126#define TIMER1_BIT 0xFFF0FFFF
127#define TIMER2_BIT 0xFF0FFFFF
128#define TIMER3_BIT 0xF0FFFFFF
129#define TIMER4_BIT 0x0FFFFFFF
130/* IAR5 BIT FIELDS */
131#define TIMER5_BIT 0xFFFFFFFF
132#define TIMER6_BIT 0xFFFFFF0F
133#define TIMER7_BIT 0xFFFFF0FF
134#define TIMER8_BIT 0xFFFF0FFF
135#define TIMER9_BIT 0xFFF0FFFF
136#define TIMER10_BIT 0xFF0FFFFF
137#define TIMER11_BIT 0xF0FFFFFF
138#define PROG0_INTA_BIT 0x0FFFFFFF
139/* IAR6 BIT FIELDS */
140#define PROG0_INTB_BIT 0xFFFFFFFF
141#define PROG1_INTA_BIT 0xFFFFFF0F
142#define PROG1_INTB_BIT 0xFFFFF0FF
143#define PROG2_INTA_BIT 0xFFFF0FFF
144#define PROG2_INTB_BIT 0xFFF0FFFF
145#define DMA1_WRRD0_BIT 0xFF0FFFFF
146#define DMA1_WRRD1_BIT 0xF0FFFFFF
147#define DMA2_WRRD0_BIT 0x0FFFFFFF
148/* IAR7 BIT FIELDS */
149#define DMA2_WRRD1_BIT 0xFFFFFFFF
150#define IMDMA_WRRD0_BIT 0xFFFFFF0F
151#define IMDMA_WRRD1_BIT 0xFFFFF0FF
152#define WATCH_BIT 0xFFFF0FFF
153#define RESERVED_1_BIT 0xFFF0FFFF
154#define RESERVED_2_BIT 0xFF0FFFFF
155#define SUPPLE_0_BIT 0xF0FFFFFF
156#define SUPPLE_1_BIT 0x0FFFFFFF
157
158/* Miscellaneous Values */
159
160/****************************** EBIU Settings ********************************/
161#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
162#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
163
164#if defined(CONFIG_C_AMBEN_ALL)
165#define V_AMBEN AMBEN_ALL
166#elif defined(CONFIG_C_AMBEN)
167#define V_AMBEN 0x0
168#elif defined(CONFIG_C_AMBEN_B0)
169#define V_AMBEN AMBEN_B0
170#elif defined(CONFIG_C_AMBEN_B0_B1)
171#define V_AMBEN AMBEN_B0_B1
172#elif defined(CONFIG_C_AMBEN_B0_B1_B2)
173#define V_AMBEN AMBEN_B0_B1_B2
174#endif
175
176#ifdef CONFIG_C_AMCKEN
177#define V_AMCKEN AMCKEN
178#else
179#define V_AMCKEN 0x0
180#endif
181
182#ifdef CONFIG_C_B0PEN
183#define V_B0PEN 0x10
184#else
185#define V_B0PEN 0x00
186#endif
187
188#ifdef CONFIG_C_B1PEN
189#define V_B1PEN 0x20
190#else
191#define V_B1PEN 0x00
192#endif
193
194#ifdef CONFIG_C_B2PEN
195#define V_B2PEN 0x40
196#else
197#define V_B2PEN 0x00
198#endif
199
200#ifdef CONFIG_C_B3PEN
201#define V_B3PEN 0x80
202#else
203#define V_B3PEN 0x00
204#endif
205
206#ifdef CONFIG_C_CDPRIO
207#define V_CDPRIO 0x100
208#else
209#define V_CDPRIO 0x0
210#endif
211
212#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO | V_B0PEN | V_B1PEN | V_B2PEN | V_B3PEN | 0x0002)
213
214#ifdef CONFIG_BF561
215#define CPU "BF561"
216#define CPUID 0x027bb000
217#endif
218#ifndef CPU
219#define CPU "UNKNOWN"
220#define CPUID 0x0
221#endif
222
223#endif /* __MACH_BF561_H__ */
diff --git a/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h
new file mode 100644
index 000000000000..8aa02780e642
--- /dev/null
+++ b/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h
@@ -0,0 +1,164 @@
1/*
2 * file: include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
3 * based on:
4 * author:
5 *
6 * created:
7 * description:
8 * blackfin serial driver head file
9 * rev:
10 *
11 * modified:
12 *
13 *
14 * bugs: enter bugs at http://blackfin.uclinux.org/
15 *
16 * this program is free software; you can redistribute it and/or modify
17 * it under the terms of the gnu general public license as published by
18 * the free software foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * this program is distributed in the hope that it will be useful,
22 * but without any warranty; without even the implied warranty of
23 * merchantability or fitness for a particular purpose. see the
24 * gnu general public license for more details.
25 *
26 * you should have received a copy of the gnu general public license
27 * along with this program; see the file copying.
28 * if not, write to the free software foundation,
29 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
30 */
31
32#include <linux/serial.h>
33#include <asm/dma.h>
34#include <asm/portmux.h>
35
36#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
37#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
38#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
39#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
40#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
41#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
42#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
43
44#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
45#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
46#define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v)
47#define UART_SET_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
48#define UART_CLEAR_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
49#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
50#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
51#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
52
53#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
54#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
55
56#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
57#define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1)
58#define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0)
59#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
60#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
61
62#ifdef CONFIG_BFIN_UART0_CTSRTS
63# define CONFIG_SERIAL_BFIN_CTSRTS
64# ifndef CONFIG_UART0_CTS_PIN
65# define CONFIG_UART0_CTS_PIN -1
66# endif
67# ifndef CONFIG_UART0_RTS_PIN
68# define CONFIG_UART0_RTS_PIN -1
69# endif
70#endif
71
72struct bfin_serial_port {
73 struct uart_port port;
74 unsigned int old_status;
75 unsigned int lsr;
76#ifdef CONFIG_SERIAL_BFIN_DMA
77 int tx_done;
78 int tx_count;
79 struct circ_buf rx_dma_buf;
80 struct timer_list rx_dma_timer;
81 int rx_dma_nrows;
82 unsigned int tx_dma_channel;
83 unsigned int rx_dma_channel;
84 struct work_struct tx_dma_workqueue;
85#else
86# if ANOMALY_05000230
87 unsigned int anomaly_threshold;
88# endif
89#endif
90#ifdef CONFIG_SERIAL_BFIN_CTSRTS
91 struct timer_list cts_timer;
92 int cts_pin;
93 int rts_pin;
94#endif
95};
96
97/* The hardware clears the LSR bits upon read, so we need to cache
98 * some of the more fun bits in software so they don't get lost
99 * when checking the LSR in other code paths (TX).
100 */
101static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
102{
103 unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
104 uart->lsr |= (lsr & (BI|FE|PE|OE));
105 return lsr | uart->lsr;
106}
107
108static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
109{
110 uart->lsr = 0;
111 bfin_write16(uart->port.membase + OFFSET_LSR, -1);
112}
113
114struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
115struct bfin_serial_res {
116 unsigned long uart_base_addr;
117 int uart_irq;
118#ifdef CONFIG_SERIAL_BFIN_DMA
119 unsigned int uart_tx_dma_channel;
120 unsigned int uart_rx_dma_channel;
121#endif
122#ifdef CONFIG_SERIAL_BFIN_CTSRTS
123 int uart_cts_pin;
124 int uart_rts_pin;
125#endif
126};
127
128struct bfin_serial_res bfin_serial_resource[] = {
129 {
130 0xFFC00400,
131 IRQ_UART_RX,
132#ifdef CONFIG_SERIAL_BFIN_DMA
133 CH_UART_TX,
134 CH_UART_RX,
135#endif
136#ifdef CONFIG_BFIN_UART0_CTSRTS
137 CONFIG_UART0_CTS_PIN,
138 CONFIG_UART0_RTS_PIN,
139#endif
140 }
141};
142
143#define DRIVER_NAME "bfin-uart"
144
145int nr_ports = BFIN_UART_NR_PORTS;
146static void bfin_serial_hw_init(struct bfin_serial_port *uart)
147{
148
149#ifdef CONFIG_SERIAL_BFIN_UART0
150 peripheral_request(P_UART0_TX, DRIVER_NAME);
151 peripheral_request(P_UART0_RX, DRIVER_NAME);
152#endif
153
154#ifdef CONFIG_SERIAL_BFIN_CTSRTS
155 if (uart->cts_pin >= 0) {
156 gpio_request(uart->cts_pin, DRIVER_NAME);
157 gpio_direction_input(uart->cts_pin);
158 }
159 if (uart->rts_pin >= 0) {
160 gpio_request(uart->rts_pin, DRIVER_NAME);
161 gpio_direction_input(uart->rts_pin, 0);
162 }
163#endif
164}
diff --git a/arch/blackfin/mach-bf561/include/mach/bfin_sir.h b/arch/blackfin/mach-bf561/include/mach/bfin_sir.h
new file mode 100644
index 000000000000..9bb87e9e2e9b
--- /dev/null
+++ b/arch/blackfin/mach-bf561/include/mach/bfin_sir.h
@@ -0,0 +1,125 @@
1/*
2 * Blackfin Infra-red Driver
3 *
4 * Copyright 2006-2008 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 *
10 */
11
12#include <linux/serial.h>
13#include <asm/dma.h>
14#include <asm/portmux.h>
15
16#define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR)
17#define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL)
18#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER)
19#define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH)
20#define SIR_UART_GET_IIR(port) bfin_read16((port)->membase + OFFSET_IIR)
21#define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR)
22#define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL)
23
24#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
25#define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v)
26#define SIR_UART_PUT_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER), v)
27#define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v)
28#define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v)
29#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
30
31#ifdef CONFIG_SIR_BFIN_DMA
32struct dma_rx_buf {
33 char *buf;
34 int head;
35 int tail;
36 };
37#endif /* CONFIG_SIR_BFIN_DMA */
38
39struct bfin_sir_port {
40 unsigned char __iomem *membase;
41 unsigned int irq;
42 unsigned int lsr;
43 unsigned long clk;
44 struct net_device *dev;
45#ifdef CONFIG_SIR_BFIN_DMA
46 int tx_done;
47 struct dma_rx_buf rx_dma_buf;
48 struct timer_list rx_dma_timer;
49 int rx_dma_nrows;
50#endif /* CONFIG_SIR_BFIN_DMA */
51 unsigned int tx_dma_channel;
52 unsigned int rx_dma_channel;
53};
54
55struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS];
56
57struct bfin_sir_port_res {
58 unsigned long base_addr;
59 int irq;
60 unsigned int rx_dma_channel;
61 unsigned int tx_dma_channel;
62};
63
64struct bfin_sir_port_res bfin_sir_port_resource[] = {
65#ifdef CONFIG_BFIN_SIR0
66 {
67 0xFFC00400,
68 IRQ_UART_RX,
69 CH_UART_RX,
70 CH_UART_TX,
71 },
72#endif
73};
74
75int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource);
76
77struct bfin_sir_self {
78 struct bfin_sir_port *sir_port;
79 spinlock_t lock;
80 unsigned int open;
81 int speed;
82 int newspeed;
83
84 struct sk_buff *txskb;
85 struct sk_buff *rxskb;
86 struct net_device_stats stats;
87 struct device *dev;
88 struct irlap_cb *irlap;
89 struct qos_info qos;
90
91 iobuff_t tx_buff;
92 iobuff_t rx_buff;
93
94 struct work_struct work;
95 int mtt;
96};
97
98static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port)
99{
100 unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR);
101 port->lsr |= (lsr & (BI|FE|PE|OE));
102 return lsr | port->lsr;
103}
104
105static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port)
106{
107 port->lsr = 0;
108 bfin_read16(port->membase + OFFSET_LSR);
109}
110
111#define DRIVER_NAME "bfin_sir"
112
113static int bfin_sir_hw_init(void)
114{
115 int ret = -ENODEV;
116#ifdef CONFIG_BFIN_SIR0
117 ret = peripheral_request(P_UART0_TX, DRIVER_NAME);
118 if (ret)
119 return ret;
120 ret = peripheral_request(P_UART0_RX, DRIVER_NAME);
121 if (ret)
122 return ret;
123#endif
124 return ret;
125}
diff --git a/arch/blackfin/mach-bf561/include/mach/blackfin.h b/arch/blackfin/mach-bf561/include/mach/blackfin.h
new file mode 100644
index 000000000000..0ea8666e6764
--- /dev/null
+++ b/arch/blackfin/mach-bf561/include/mach/blackfin.h
@@ -0,0 +1,87 @@
1/*
2 * File: include/asm-blackfin/mach-bf561/blackfin.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _MACH_BLACKFIN_H_
32#define _MACH_BLACKFIN_H_
33
34#define BF561_FAMILY
35
36#include "bf561.h"
37#include "mem_map.h"
38#include "defBF561.h"
39#include "anomaly.h"
40
41#if !defined(__ASSEMBLY__)
42#include "cdefBF561.h"
43#endif
44
45#define bfin_read_FIO_FLAG_D() bfin_read_FIO0_FLAG_D()
46#define bfin_write_FIO_FLAG_D(val) bfin_write_FIO0_FLAG_D(val)
47#define bfin_read_FIO_DIR() bfin_read_FIO0_DIR()
48#define bfin_write_FIO_DIR(val) bfin_write_FIO0_DIR(val)
49#define bfin_read_FIO_INEN() bfin_read_FIO0_INEN()
50#define bfin_write_FIO_INEN(val) bfin_write_FIO0_INEN(val)
51
52#define SIC_IWR0 SICA_IWR0
53#define SIC_IWR1 SICA_IWR1
54#define SIC_IAR0 SICA_IAR0
55#define bfin_write_SIC_IMASK0 bfin_write_SICA_IMASK0
56#define bfin_write_SIC_IMASK1 bfin_write_SICA_IMASK1
57#define bfin_write_SIC_IWR0 bfin_write_SICA_IWR0
58#define bfin_write_SIC_IWR1 bfin_write_SICA_IWR1
59
60#define bfin_read_SIC_IMASK0 bfin_read_SICA_IMASK0
61#define bfin_read_SIC_IMASK1 bfin_read_SICA_IMASK1
62#define bfin_read_SIC_IWR0 bfin_read_SICA_IWR0
63#define bfin_read_SIC_IWR1 bfin_read_SICA_IWR1
64#define bfin_read_SIC_ISR0 bfin_read_SICA_ISR0
65#define bfin_read_SIC_ISR1 bfin_read_SICA_ISR1
66
67#define bfin_read_SIC_IMASK(x) bfin_read32(SICA_IMASK0 + (x << 2))
68#define bfin_write_SIC_IMASK(x, val) bfin_write32((SICA_IMASK0 + (x << 2)), val)
69#define bfin_read_SIC_ISR(x) bfin_read32(SICA_ISR0 + (x << 2))
70#define bfin_write_SIC_ISR(x, val) bfin_write32((SICA_ISR0 + (x << 2)), val)
71
72#define BFIN_UART_NR_PORTS 1
73
74#define OFFSET_THR 0x00 /* Transmit Holding register */
75#define OFFSET_RBR 0x00 /* Receive Buffer register */
76#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
77#define OFFSET_IER 0x04 /* Interrupt Enable Register */
78#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
79#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
80#define OFFSET_LCR 0x0C /* Line Control Register */
81#define OFFSET_MCR 0x10 /* Modem Control Register */
82#define OFFSET_LSR 0x14 /* Line Status Register */
83#define OFFSET_MSR 0x18 /* Modem Status Register */
84#define OFFSET_SCR 0x1C /* SCR Scratch Register */
85#define OFFSET_GCTL 0x24 /* Global Control Register */
86
87#endif /* _MACH_BLACKFIN_H_ */
diff --git a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
new file mode 100644
index 000000000000..c14d63402e70
--- /dev/null
+++ b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
@@ -0,0 +1,1579 @@
1/*
2 * File: include/asm-blackfin/mach-bf561/cdefBF561.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: C POINTERS TO SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _CDEF_BF561_H
32#define _CDEF_BF561_H
33
34#include <asm/blackfin.h>
35
36/* include all Core registers and bit definitions */
37#include "defBF561.h"
38
39/*include core specific register pointer definitions*/
40#include <asm/cdef_LPBlackfin.h>
41
42#include <asm/system.h>
43
44/*********************************************************************************** */
45/* System MMR Register Map */
46/*********************************************************************************** */
47
48/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
49#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
50/* Writing to PLL_CTL initiates a PLL relock sequence. */
51static __inline__ void bfin_write_PLL_CTL(unsigned int val)
52{
53 unsigned long flags, iwr0, iwr1;
54
55 if (val == bfin_read_PLL_CTL())
56 return;
57
58 local_irq_save(flags);
59 /* Enable the PLL Wakeup bit in SIC IWR */
60 iwr0 = bfin_read32(SICA_IWR0);
61 iwr1 = bfin_read32(SICA_IWR1);
62 /* Only allow PPL Wakeup) */
63 bfin_write32(SICA_IWR0, IWR_ENABLE(0));
64 bfin_write32(SICA_IWR1, 0);
65
66 bfin_write16(PLL_CTL, val);
67 SSYNC();
68 asm("IDLE;");
69
70 bfin_write32(SICA_IWR0, iwr0);
71 bfin_write32(SICA_IWR1, iwr1);
72 local_irq_restore(flags);
73}
74#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
75#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
76#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
77/* Writing to VR_CTL initiates a PLL relock sequence. */
78static __inline__ void bfin_write_VR_CTL(unsigned int val)
79{
80 unsigned long flags, iwr0, iwr1;
81
82 if (val == bfin_read_VR_CTL())
83 return;
84
85 local_irq_save(flags);
86 /* Enable the PLL Wakeup bit in SIC IWR */
87 iwr0 = bfin_read32(SICA_IWR0);
88 iwr1 = bfin_read32(SICA_IWR1);
89 /* Only allow PPL Wakeup) */
90 bfin_write32(SICA_IWR0, IWR_ENABLE(0));
91 bfin_write32(SICA_IWR1, 0);
92
93 bfin_write16(VR_CTL, val);
94 SSYNC();
95 asm("IDLE;");
96
97 bfin_write32(SICA_IWR0, iwr0);
98 bfin_write32(SICA_IWR1, iwr1);
99 local_irq_restore(flags);
100}
101#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
102#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
103#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
104#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val)
105#define bfin_read_CHIPID() bfin_read32(CHIPID)
106
107/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */
108#define bfin_read_SWRST() bfin_read_SICA_SWRST()
109#define bfin_write_SWRST(val) bfin_write_SICA_SWRST(val)
110#define bfin_read_SYSCR() bfin_read_SICA_SYSCR()
111#define bfin_write_SYSCR(val) bfin_write_SICA_SYSCR(val)
112
113/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
114#define bfin_read_SICA_SWRST() bfin_read16(SICA_SWRST)
115#define bfin_write_SICA_SWRST(val) bfin_write16(SICA_SWRST,val)
116#define bfin_read_SICA_SYSCR() bfin_read16(SICA_SYSCR)
117#define bfin_write_SICA_SYSCR(val) bfin_write16(SICA_SYSCR,val)
118#define bfin_read_SICA_RVECT() bfin_read16(SICA_RVECT)
119#define bfin_write_SICA_RVECT(val) bfin_write16(SICA_RVECT,val)
120#define bfin_read_SICA_IMASK() bfin_read32(SICA_IMASK)
121#define bfin_write_SICA_IMASK(val) bfin_write32(SICA_IMASK,val)
122#define bfin_read_SICA_IMASK0() bfin_read32(SICA_IMASK0)
123#define bfin_write_SICA_IMASK0(val) bfin_write32(SICA_IMASK0,val)
124#define bfin_read_SICA_IMASK1() bfin_read32(SICA_IMASK1)
125#define bfin_write_SICA_IMASK1(val) bfin_write32(SICA_IMASK1,val)
126#define bfin_read_SICA_IAR0() bfin_read32(SICA_IAR0)
127#define bfin_write_SICA_IAR0(val) bfin_write32(SICA_IAR0,val)
128#define bfin_read_SICA_IAR1() bfin_read32(SICA_IAR1)
129#define bfin_write_SICA_IAR1(val) bfin_write32(SICA_IAR1,val)
130#define bfin_read_SICA_IAR2() bfin_read32(SICA_IAR2)
131#define bfin_write_SICA_IAR2(val) bfin_write32(SICA_IAR2,val)
132#define bfin_read_SICA_IAR3() bfin_read32(SICA_IAR3)
133#define bfin_write_SICA_IAR3(val) bfin_write32(SICA_IAR3,val)
134#define bfin_read_SICA_IAR4() bfin_read32(SICA_IAR4)
135#define bfin_write_SICA_IAR4(val) bfin_write32(SICA_IAR4,val)
136#define bfin_read_SICA_IAR5() bfin_read32(SICA_IAR5)
137#define bfin_write_SICA_IAR5(val) bfin_write32(SICA_IAR5,val)
138#define bfin_read_SICA_IAR6() bfin_read32(SICA_IAR6)
139#define bfin_write_SICA_IAR6(val) bfin_write32(SICA_IAR6,val)
140#define bfin_read_SICA_IAR7() bfin_read32(SICA_IAR7)
141#define bfin_write_SICA_IAR7(val) bfin_write32(SICA_IAR7,val)
142#define bfin_read_SICA_ISR0() bfin_read32(SICA_ISR0)
143#define bfin_write_SICA_ISR0(val) bfin_write32(SICA_ISR0,val)
144#define bfin_read_SICA_ISR1() bfin_read32(SICA_ISR1)
145#define bfin_write_SICA_ISR1(val) bfin_write32(SICA_ISR1,val)
146#define bfin_read_SICA_IWR0() bfin_read32(SICA_IWR0)
147#define bfin_write_SICA_IWR0(val) bfin_write32(SICA_IWR0,val)
148#define bfin_read_SICA_IWR1() bfin_read32(SICA_IWR1)
149#define bfin_write_SICA_IWR1(val) bfin_write32(SICA_IWR1,val)
150
151/* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */
152#define bfin_read_SICB_SWRST() bfin_read16(SICB_SWRST)
153#define bfin_write_SICB_SWRST(val) bfin_write16(SICB_SWRST,val)
154#define bfin_read_SICB_SYSCR() bfin_read16(SICB_SYSCR)
155#define bfin_write_SICB_SYSCR(val) bfin_write16(SICB_SYSCR,val)
156#define bfin_read_SICB_RVECT() bfin_read16(SICB_RVECT)
157#define bfin_write_SICB_RVECT(val) bfin_write16(SICB_RVECT,val)
158#define bfin_read_SICB_IMASK0() bfin_read32(SICB_IMASK0)
159#define bfin_write_SICB_IMASK0(val) bfin_write32(SICB_IMASK0,val)
160#define bfin_read_SICB_IMASK1() bfin_read32(SICB_IMASK1)
161#define bfin_write_SICB_IMASK1(val) bfin_write32(SICB_IMASK1,val)
162#define bfin_read_SICB_IAR0() bfin_read32(SICB_IAR0)
163#define bfin_write_SICB_IAR0(val) bfin_write32(SICB_IAR0,val)
164#define bfin_read_SICB_IAR1() bfin_read32(SICB_IAR1)
165#define bfin_write_SICB_IAR1(val) bfin_write32(SICB_IAR1,val)
166#define bfin_read_SICB_IAR2() bfin_read32(SICB_IAR2)
167#define bfin_write_SICB_IAR2(val) bfin_write32(SICB_IAR2,val)
168#define bfin_read_SICB_IAR3() bfin_read32(SICB_IAR3)
169#define bfin_write_SICB_IAR3(val) bfin_write32(SICB_IAR3,val)
170#define bfin_read_SICB_IAR4() bfin_read32(SICB_IAR4)
171#define bfin_write_SICB_IAR4(val) bfin_write32(SICB_IAR4,val)
172#define bfin_read_SICB_IAR5() bfin_read32(SICB_IAR5)
173#define bfin_write_SICB_IAR5(val) bfin_write32(SICB_IAR5,val)
174#define bfin_read_SICB_IAR6() bfin_read32(SICB_IAR6)
175#define bfin_write_SICB_IAR6(val) bfin_write32(SICB_IAR6,val)
176#define bfin_read_SICB_IAR7() bfin_read32(SICB_IAR7)
177#define bfin_write_SICB_IAR7(val) bfin_write32(SICB_IAR7,val)
178#define bfin_read_SICB_ISR0() bfin_read32(SICB_ISR0)
179#define bfin_write_SICB_ISR0(val) bfin_write32(SICB_ISR0,val)
180#define bfin_read_SICB_ISR1() bfin_read32(SICB_ISR1)
181#define bfin_write_SICB_ISR1(val) bfin_write32(SICB_ISR1,val)
182#define bfin_read_SICB_IWR0() bfin_read32(SICB_IWR0)
183#define bfin_write_SICB_IWR0(val) bfin_write32(SICB_IWR0,val)
184#define bfin_read_SICB_IWR1() bfin_read32(SICB_IWR1)
185#define bfin_write_SICB_IWR1(val) bfin_write32(SICB_IWR1,val)
186/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */
187#define bfin_read_WDOGA_CTL() bfin_read16(WDOGA_CTL)
188#define bfin_write_WDOGA_CTL(val) bfin_write16(WDOGA_CTL,val)
189#define bfin_read_WDOGA_CNT() bfin_read32(WDOGA_CNT)
190#define bfin_write_WDOGA_CNT(val) bfin_write32(WDOGA_CNT,val)
191#define bfin_read_WDOGA_STAT() bfin_read32(WDOGA_STAT)
192#define bfin_write_WDOGA_STAT(val) bfin_write32(WDOGA_STAT,val)
193
194/* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */
195#define bfin_read_WDOGB_CTL() bfin_read16(WDOGB_CTL)
196#define bfin_write_WDOGB_CTL(val) bfin_write16(WDOGB_CTL,val)
197#define bfin_read_WDOGB_CNT() bfin_read32(WDOGB_CNT)
198#define bfin_write_WDOGB_CNT(val) bfin_write32(WDOGB_CNT,val)
199#define bfin_read_WDOGB_STAT() bfin_read32(WDOGB_STAT)
200#define bfin_write_WDOGB_STAT(val) bfin_write32(WDOGB_STAT,val)
201
202/* UART Controller (0xFFC00400 - 0xFFC004FF) */
203#define bfin_read_UART_THR() bfin_read16(UART_THR)
204#define bfin_write_UART_THR(val) bfin_write16(UART_THR,val)
205#define bfin_read_UART_RBR() bfin_read16(UART_RBR)
206#define bfin_write_UART_RBR(val) bfin_write16(UART_RBR,val)
207#define bfin_read_UART_DLL() bfin_read16(UART_DLL)
208#define bfin_write_UART_DLL(val) bfin_write16(UART_DLL,val)
209#define bfin_read_UART_IER() bfin_read16(UART_IER)
210#define bfin_write_UART_IER(val) bfin_write16(UART_IER,val)
211#define bfin_read_UART_DLH() bfin_read16(UART_DLH)
212#define bfin_write_UART_DLH(val) bfin_write16(UART_DLH,val)
213#define bfin_read_UART_IIR() bfin_read16(UART_IIR)
214#define bfin_write_UART_IIR(val) bfin_write16(UART_IIR,val)
215#define bfin_read_UART_LCR() bfin_read16(UART_LCR)
216#define bfin_write_UART_LCR(val) bfin_write16(UART_LCR,val)
217#define bfin_read_UART_MCR() bfin_read16(UART_MCR)
218#define bfin_write_UART_MCR(val) bfin_write16(UART_MCR,val)
219#define bfin_read_UART_LSR() bfin_read16(UART_LSR)
220#define bfin_write_UART_LSR(val) bfin_write16(UART_LSR,val)
221#define bfin_read_UART_MSR() bfin_read16(UART_MSR)
222#define bfin_write_UART_MSR(val) bfin_write16(UART_MSR,val)
223#define bfin_read_UART_SCR() bfin_read16(UART_SCR)
224#define bfin_write_UART_SCR(val) bfin_write16(UART_SCR,val)
225#define bfin_read_UART_GCTL() bfin_read16(UART_GCTL)
226#define bfin_write_UART_GCTL(val) bfin_write16(UART_GCTL,val)
227
228/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
229#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL)
230#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL,val)
231#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG)
232#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG,val)
233#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT)
234#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT,val)
235#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR)
236#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR,val)
237#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR)
238#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR,val)
239#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD)
240#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD,val)
241#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW)
242#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW,val)
243
244/* Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) */
245#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
246#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG,val)
247#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
248#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER,val)
249#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
250#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD,val)
251#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
252#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH,val)
253#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
254#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG,val)
255#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
256#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER,val)
257#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
258#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD,val)
259#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
260#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH,val)
261#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
262#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG,val)
263#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
264#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER,val)
265#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
266#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD,val)
267#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
268#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH,val)
269#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
270#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG,val)
271#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
272#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER,val)
273#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
274#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD,val)
275#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
276#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH,val)
277#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
278#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG,val)
279#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
280#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER,val)
281#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
282#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD,val)
283#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
284#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH,val)
285#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
286#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG,val)
287#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
288#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER,val)
289#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
290#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD,val)
291#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
292#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH,val)
293#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
294#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG,val)
295#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
296#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER,val)
297#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
298#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD,val)
299#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
300#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH,val)
301#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
302#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG,val)
303#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
304#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER,val)
305#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
306#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD,val)
307#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
308#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH,val)
309
310/* Timer registers 8-11 (0xFFC0 1600-0xFFC0 16FF) */
311#define bfin_read_TMRS8_ENABLE() bfin_read16(TMRS8_ENABLE)
312#define bfin_write_TMRS8_ENABLE(val) bfin_write16(TMRS8_ENABLE,val)
313#define bfin_read_TMRS8_DISABLE() bfin_read16(TMRS8_DISABLE)
314#define bfin_write_TMRS8_DISABLE(val) bfin_write16(TMRS8_DISABLE,val)
315#define bfin_read_TMRS8_STATUS() bfin_read32(TMRS8_STATUS)
316#define bfin_write_TMRS8_STATUS(val) bfin_write32(TMRS8_STATUS,val)
317#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG)
318#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG,val)
319#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER)
320#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER,val)
321#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD)
322#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD,val)
323#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH)
324#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH,val)
325#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG)
326#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG,val)
327#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER)
328#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER,val)
329#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD)
330#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD,val)
331#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH)
332#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH,val)
333#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG)
334#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG,val)
335#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER)
336#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER,val)
337#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD)
338#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD,val)
339#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH)
340#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH,val)
341#define bfin_read_TIMER11_CONFIG() bfin_read16(TIMER11_CONFIG)
342#define bfin_write_TIMER11_CONFIG(val) bfin_write16(TIMER11_CONFIG,val)
343#define bfin_read_TIMER11_COUNTER() bfin_read32(TIMER11_COUNTER)
344#define bfin_write_TIMER11_COUNTER(val) bfin_write32(TIMER11_COUNTER,val)
345#define bfin_read_TIMER11_PERIOD() bfin_read32(TIMER11_PERIOD)
346#define bfin_write_TIMER11_PERIOD(val) bfin_write32(TIMER11_PERIOD,val)
347#define bfin_read_TIMER11_WIDTH() bfin_read32(TIMER11_WIDTH)
348#define bfin_write_TIMER11_WIDTH(val) bfin_write32(TIMER11_WIDTH,val)
349#define bfin_read_TMRS4_ENABLE() bfin_read16(TMRS4_ENABLE)
350#define bfin_write_TMRS4_ENABLE(val) bfin_write16(TMRS4_ENABLE,val)
351#define bfin_read_TMRS4_DISABLE() bfin_read16(TMRS4_DISABLE)
352#define bfin_write_TMRS4_DISABLE(val) bfin_write16(TMRS4_DISABLE,val)
353#define bfin_read_TMRS4_STATUS() bfin_read32(TMRS4_STATUS)
354#define bfin_write_TMRS4_STATUS(val) bfin_write32(TMRS4_STATUS,val)
355
356/* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */
357#define bfin_read_FIO0_FLAG_D() bfin_read16(FIO0_FLAG_D)
358#define bfin_write_FIO0_FLAG_D(val) bfin_write16(FIO0_FLAG_D,val)
359#define bfin_read_FIO0_FLAG_C() bfin_read16(FIO0_FLAG_C)
360#define bfin_write_FIO0_FLAG_C(val) bfin_write16(FIO0_FLAG_C,val)
361#define bfin_read_FIO0_FLAG_S() bfin_read16(FIO0_FLAG_S)
362#define bfin_write_FIO0_FLAG_S(val) bfin_write16(FIO0_FLAG_S,val)
363#define bfin_read_FIO0_FLAG_T() bfin_read16(FIO0_FLAG_T)
364#define bfin_write_FIO0_FLAG_T(val) bfin_write16(FIO0_FLAG_T,val)
365#define bfin_read_FIO0_MASKA_D() bfin_read16(FIO0_MASKA_D)
366#define bfin_write_FIO0_MASKA_D(val) bfin_write16(FIO0_MASKA_D,val)
367#define bfin_read_FIO0_MASKA_C() bfin_read16(FIO0_MASKA_C)
368#define bfin_write_FIO0_MASKA_C(val) bfin_write16(FIO0_MASKA_C,val)
369#define bfin_read_FIO0_MASKA_S() bfin_read16(FIO0_MASKA_S)
370#define bfin_write_FIO0_MASKA_S(val) bfin_write16(FIO0_MASKA_S,val)
371#define bfin_read_FIO0_MASKA_T() bfin_read16(FIO0_MASKA_T)
372#define bfin_write_FIO0_MASKA_T(val) bfin_write16(FIO0_MASKA_T,val)
373#define bfin_read_FIO0_MASKB_D() bfin_read16(FIO0_MASKB_D)
374#define bfin_write_FIO0_MASKB_D(val) bfin_write16(FIO0_MASKB_D,val)
375#define bfin_read_FIO0_MASKB_C() bfin_read16(FIO0_MASKB_C)
376#define bfin_write_FIO0_MASKB_C(val) bfin_write16(FIO0_MASKB_C,val)
377#define bfin_read_FIO0_MASKB_S() bfin_read16(FIO0_MASKB_S)
378#define bfin_write_FIO0_MASKB_S(val) bfin_write16(FIO0_MASKB_S,val)
379#define bfin_read_FIO0_MASKB_T() bfin_read16(FIO0_MASKB_T)
380#define bfin_write_FIO0_MASKB_T(val) bfin_write16(FIO0_MASKB_T,val)
381#define bfin_read_FIO0_DIR() bfin_read16(FIO0_DIR)
382#define bfin_write_FIO0_DIR(val) bfin_write16(FIO0_DIR,val)
383#define bfin_read_FIO0_POLAR() bfin_read16(FIO0_POLAR)
384#define bfin_write_FIO0_POLAR(val) bfin_write16(FIO0_POLAR,val)
385#define bfin_read_FIO0_EDGE() bfin_read16(FIO0_EDGE)
386#define bfin_write_FIO0_EDGE(val) bfin_write16(FIO0_EDGE,val)
387#define bfin_read_FIO0_BOTH() bfin_read16(FIO0_BOTH)
388#define bfin_write_FIO0_BOTH(val) bfin_write16(FIO0_BOTH,val)
389#define bfin_read_FIO0_INEN() bfin_read16(FIO0_INEN)
390#define bfin_write_FIO0_INEN(val) bfin_write16(FIO0_INEN,val)
391/* Programmable Flag 1 registers (0xFFC0 1500-0xFFC0 15FF) */
392#define bfin_read_FIO1_FLAG_D() bfin_read16(FIO1_FLAG_D)
393#define bfin_write_FIO1_FLAG_D(val) bfin_write16(FIO1_FLAG_D,val)
394#define bfin_read_FIO1_FLAG_C() bfin_read16(FIO1_FLAG_C)
395#define bfin_write_FIO1_FLAG_C(val) bfin_write16(FIO1_FLAG_C,val)
396#define bfin_read_FIO1_FLAG_S() bfin_read16(FIO1_FLAG_S)
397#define bfin_write_FIO1_FLAG_S(val) bfin_write16(FIO1_FLAG_S,val)
398#define bfin_read_FIO1_FLAG_T() bfin_read16(FIO1_FLAG_T)
399#define bfin_write_FIO1_FLAG_T(val) bfin_write16(FIO1_FLAG_T,val)
400#define bfin_read_FIO1_MASKA_D() bfin_read16(FIO1_MASKA_D)
401#define bfin_write_FIO1_MASKA_D(val) bfin_write16(FIO1_MASKA_D,val)
402#define bfin_read_FIO1_MASKA_C() bfin_read16(FIO1_MASKA_C)
403#define bfin_write_FIO1_MASKA_C(val) bfin_write16(FIO1_MASKA_C,val)
404#define bfin_read_FIO1_MASKA_S() bfin_read16(FIO1_MASKA_S)
405#define bfin_write_FIO1_MASKA_S(val) bfin_write16(FIO1_MASKA_S,val)
406#define bfin_read_FIO1_MASKA_T() bfin_read16(FIO1_MASKA_T)
407#define bfin_write_FIO1_MASKA_T(val) bfin_write16(FIO1_MASKA_T,val)
408#define bfin_read_FIO1_MASKB_D() bfin_read16(FIO1_MASKB_D)
409#define bfin_write_FIO1_MASKB_D(val) bfin_write16(FIO1_MASKB_D,val)
410#define bfin_read_FIO1_MASKB_C() bfin_read16(FIO1_MASKB_C)
411#define bfin_write_FIO1_MASKB_C(val) bfin_write16(FIO1_MASKB_C,val)
412#define bfin_read_FIO1_MASKB_S() bfin_read16(FIO1_MASKB_S)
413#define bfin_write_FIO1_MASKB_S(val) bfin_write16(FIO1_MASKB_S,val)
414#define bfin_read_FIO1_MASKB_T() bfin_read16(FIO1_MASKB_T)
415#define bfin_write_FIO1_MASKB_T(val) bfin_write16(FIO1_MASKB_T,val)
416#define bfin_read_FIO1_DIR() bfin_read16(FIO1_DIR)
417#define bfin_write_FIO1_DIR(val) bfin_write16(FIO1_DIR,val)
418#define bfin_read_FIO1_POLAR() bfin_read16(FIO1_POLAR)
419#define bfin_write_FIO1_POLAR(val) bfin_write16(FIO1_POLAR,val)
420#define bfin_read_FIO1_EDGE() bfin_read16(FIO1_EDGE)
421#define bfin_write_FIO1_EDGE(val) bfin_write16(FIO1_EDGE,val)
422#define bfin_read_FIO1_BOTH() bfin_read16(FIO1_BOTH)
423#define bfin_write_FIO1_BOTH(val) bfin_write16(FIO1_BOTH,val)
424#define bfin_read_FIO1_INEN() bfin_read16(FIO1_INEN)
425#define bfin_write_FIO1_INEN(val) bfin_write16(FIO1_INEN,val)
426/* Programmable Flag registers (0xFFC0 1700-0xFFC0 17FF) */
427#define bfin_read_FIO2_FLAG_D() bfin_read16(FIO2_FLAG_D)
428#define bfin_write_FIO2_FLAG_D(val) bfin_write16(FIO2_FLAG_D,val)
429#define bfin_read_FIO2_FLAG_C() bfin_read16(FIO2_FLAG_C)
430#define bfin_write_FIO2_FLAG_C(val) bfin_write16(FIO2_FLAG_C,val)
431#define bfin_read_FIO2_FLAG_S() bfin_read16(FIO2_FLAG_S)
432#define bfin_write_FIO2_FLAG_S(val) bfin_write16(FIO2_FLAG_S,val)
433#define bfin_read_FIO2_FLAG_T() bfin_read16(FIO2_FLAG_T)
434#define bfin_write_FIO2_FLAG_T(val) bfin_write16(FIO2_FLAG_T,val)
435#define bfin_read_FIO2_MASKA_D() bfin_read16(FIO2_MASKA_D)
436#define bfin_write_FIO2_MASKA_D(val) bfin_write16(FIO2_MASKA_D,val)
437#define bfin_read_FIO2_MASKA_C() bfin_read16(FIO2_MASKA_C)
438#define bfin_write_FIO2_MASKA_C(val) bfin_write16(FIO2_MASKA_C,val)
439#define bfin_read_FIO2_MASKA_S() bfin_read16(FIO2_MASKA_S)
440#define bfin_write_FIO2_MASKA_S(val) bfin_write16(FIO2_MASKA_S,val)
441#define bfin_read_FIO2_MASKA_T() bfin_read16(FIO2_MASKA_T)
442#define bfin_write_FIO2_MASKA_T(val) bfin_write16(FIO2_MASKA_T,val)
443#define bfin_read_FIO2_MASKB_D() bfin_read16(FIO2_MASKB_D)
444#define bfin_write_FIO2_MASKB_D(val) bfin_write16(FIO2_MASKB_D,val)
445#define bfin_read_FIO2_MASKB_C() bfin_read16(FIO2_MASKB_C)
446#define bfin_write_FIO2_MASKB_C(val) bfin_write16(FIO2_MASKB_C,val)
447#define bfin_read_FIO2_MASKB_S() bfin_read16(FIO2_MASKB_S)
448#define bfin_write_FIO2_MASKB_S(val) bfin_write16(FIO2_MASKB_S,val)
449#define bfin_read_FIO2_MASKB_T() bfin_read16(FIO2_MASKB_T)
450#define bfin_write_FIO2_MASKB_T(val) bfin_write16(FIO2_MASKB_T,val)
451#define bfin_read_FIO2_DIR() bfin_read16(FIO2_DIR)
452#define bfin_write_FIO2_DIR(val) bfin_write16(FIO2_DIR,val)
453#define bfin_read_FIO2_POLAR() bfin_read16(FIO2_POLAR)
454#define bfin_write_FIO2_POLAR(val) bfin_write16(FIO2_POLAR,val)
455#define bfin_read_FIO2_EDGE() bfin_read16(FIO2_EDGE)
456#define bfin_write_FIO2_EDGE(val) bfin_write16(FIO2_EDGE,val)
457#define bfin_read_FIO2_BOTH() bfin_read16(FIO2_BOTH)
458#define bfin_write_FIO2_BOTH(val) bfin_write16(FIO2_BOTH,val)
459#define bfin_read_FIO2_INEN() bfin_read16(FIO2_INEN)
460#define bfin_write_FIO2_INEN(val) bfin_write16(FIO2_INEN,val)
461/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
462#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
463#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1,val)
464#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
465#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2,val)
466#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
467#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV,val)
468#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
469#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV,val)
470#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
471#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX,val)
472#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
473#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX,val)
474#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX)
475#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX,val)
476#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX)
477#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX,val)
478#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX)
479#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX,val)
480#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX)
481#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX,val)
482#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
483#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1,val)
484#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
485#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2,val)
486#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
487#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV,val)
488#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
489#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV,val)
490#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
491#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT,val)
492#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
493#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL,val)
494#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
495#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1,val)
496#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
497#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2,val)
498#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
499#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0,val)
500#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
501#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1,val)
502#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
503#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2,val)
504#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
505#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3,val)
506#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
507#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0,val)
508#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
509#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1,val)
510#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
511#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2,val)
512#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
513#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3,val)
514/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
515#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
516#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1,val)
517#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
518#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2,val)
519#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
520#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV,val)
521#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
522#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV,val)
523#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
524#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX,val)
525#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
526#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX,val)
527#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX)
528#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX,val)
529#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX)
530#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX,val)
531#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX)
532#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX,val)
533#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX)
534#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX,val)
535#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
536#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1,val)
537#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
538#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2,val)
539#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
540#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV,val)
541#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
542#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV,val)
543#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
544#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT,val)
545#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
546#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL,val)
547#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
548#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1,val)
549#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
550#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2,val)
551#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
552#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0,val)
553#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
554#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1,val)
555#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
556#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2,val)
557#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
558#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3,val)
559#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
560#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0,val)
561#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
562#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1,val)
563#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
564#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2,val)
565#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
566#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3,val)
567/* Asynchronous Memory Controller - External Bus Interface Unit */
568#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
569#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL,val)
570#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
571#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0,val)
572#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
573#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1,val)
574/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
575#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
576#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL,val)
577#define bfin_read_EBIU_SDBCTL() bfin_read32(EBIU_SDBCTL)
578#define bfin_write_EBIU_SDBCTL(val) bfin_write32(EBIU_SDBCTL,val)
579#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
580#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC,val)
581#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
582#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val)
583/* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF) */
584#define bfin_read_PPI0_CONTROL() bfin_read16(PPI0_CONTROL)
585#define bfin_write_PPI0_CONTROL(val) bfin_write16(PPI0_CONTROL,val)
586#define bfin_read_PPI0_STATUS() bfin_read16(PPI0_STATUS)
587#define bfin_write_PPI0_STATUS(val) bfin_write16(PPI0_STATUS,val)
588#define bfin_clear_PPI0_STATUS() bfin_read_PPI0_STATUS()
589#define bfin_read_PPI0_COUNT() bfin_read16(PPI0_COUNT)
590#define bfin_write_PPI0_COUNT(val) bfin_write16(PPI0_COUNT,val)
591#define bfin_read_PPI0_DELAY() bfin_read16(PPI0_DELAY)
592#define bfin_write_PPI0_DELAY(val) bfin_write16(PPI0_DELAY,val)
593#define bfin_read_PPI0_FRAME() bfin_read16(PPI0_FRAME)
594#define bfin_write_PPI0_FRAME(val) bfin_write16(PPI0_FRAME,val)
595/* Parallel Peripheral Interface (PPI) 1 registers (0xFFC0 1300-0xFFC0 13FF) */
596#define bfin_read_PPI1_CONTROL() bfin_read16(PPI1_CONTROL)
597#define bfin_write_PPI1_CONTROL(val) bfin_write16(PPI1_CONTROL,val)
598#define bfin_read_PPI1_STATUS() bfin_read16(PPI1_STATUS)
599#define bfin_write_PPI1_STATUS(val) bfin_write16(PPI1_STATUS,val)
600#define bfin_clear_PPI1_STATUS() bfin_read_PPI1_STATUS()
601#define bfin_read_PPI1_COUNT() bfin_read16(PPI1_COUNT)
602#define bfin_write_PPI1_COUNT(val) bfin_write16(PPI1_COUNT,val)
603#define bfin_read_PPI1_DELAY() bfin_read16(PPI1_DELAY)
604#define bfin_write_PPI1_DELAY(val) bfin_write16(PPI1_DELAY,val)
605#define bfin_read_PPI1_FRAME() bfin_read16(PPI1_FRAME)
606#define bfin_write_PPI1_FRAME(val) bfin_write16(PPI1_FRAME,val)
607/*DMA traffic control registers */
608#define bfin_read_DMA1_TC_PER() bfin_read16(DMA1_TC_PER)
609#define bfin_write_DMA1_TC_PER(val) bfin_write16(DMA1_TC_PER,val)
610#define bfin_read_DMA1_TC_CNT() bfin_read16(DMA1_TC_CNT)
611#define bfin_write_DMA1_TC_CNT(val) bfin_write16(DMA1_TC_CNT,val)
612#define bfin_read_DMA2_TC_PER() bfin_read16(DMA2_TC_PER)
613#define bfin_write_DMA2_TC_PER(val) bfin_write16(DMA2_TC_PER,val)
614#define bfin_read_DMA2_TC_CNT() bfin_read16(DMA2_TC_CNT)
615#define bfin_write_DMA2_TC_CNT(val) bfin_write16(DMA2_TC_CNT,val)
616/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */
617#define bfin_read_DMA1_0_CONFIG() bfin_read16(DMA1_0_CONFIG)
618#define bfin_write_DMA1_0_CONFIG(val) bfin_write16(DMA1_0_CONFIG,val)
619#define bfin_read_DMA1_0_NEXT_DESC_PTR() bfin_read32(DMA1_0_NEXT_DESC_PTR)
620#define bfin_write_DMA1_0_NEXT_DESC_PTR(val) bfin_write32(DMA1_0_NEXT_DESC_PTR,val)
621#define bfin_read_DMA1_0_START_ADDR() bfin_read32(DMA1_0_START_ADDR)
622#define bfin_write_DMA1_0_START_ADDR(val) bfin_write32(DMA1_0_START_ADDR,val)
623#define bfin_read_DMA1_0_X_COUNT() bfin_read16(DMA1_0_X_COUNT)
624#define bfin_write_DMA1_0_X_COUNT(val) bfin_write16(DMA1_0_X_COUNT,val)
625#define bfin_read_DMA1_0_Y_COUNT() bfin_read16(DMA1_0_Y_COUNT)
626#define bfin_write_DMA1_0_Y_COUNT(val) bfin_write16(DMA1_0_Y_COUNT,val)
627#define bfin_read_DMA1_0_X_MODIFY() bfin_read16(DMA1_0_X_MODIFY)
628#define bfin_write_DMA1_0_X_MODIFY(val) bfin_write16(DMA1_0_X_MODIFY,val)
629#define bfin_read_DMA1_0_Y_MODIFY() bfin_read16(DMA1_0_Y_MODIFY)
630#define bfin_write_DMA1_0_Y_MODIFY(val) bfin_write16(DMA1_0_Y_MODIFY,val)
631#define bfin_read_DMA1_0_CURR_DESC_PTR() bfin_read32(DMA1_0_CURR_DESC_PTR)
632#define bfin_write_DMA1_0_CURR_DESC_PTR(val) bfin_write32(DMA1_0_CURR_DESC_PTR,val)
633#define bfin_read_DMA1_0_CURR_ADDR() bfin_read32(DMA1_0_CURR_ADDR)
634#define bfin_write_DMA1_0_CURR_ADDR(val) bfin_write32(DMA1_0_CURR_ADDR,val)
635#define bfin_read_DMA1_0_CURR_X_COUNT() bfin_read16(DMA1_0_CURR_X_COUNT)
636#define bfin_write_DMA1_0_CURR_X_COUNT(val) bfin_write16(DMA1_0_CURR_X_COUNT,val)
637#define bfin_read_DMA1_0_CURR_Y_COUNT() bfin_read16(DMA1_0_CURR_Y_COUNT)
638#define bfin_write_DMA1_0_CURR_Y_COUNT(val) bfin_write16(DMA1_0_CURR_Y_COUNT,val)
639#define bfin_read_DMA1_0_IRQ_STATUS() bfin_read16(DMA1_0_IRQ_STATUS)
640#define bfin_write_DMA1_0_IRQ_STATUS(val) bfin_write16(DMA1_0_IRQ_STATUS,val)
641#define bfin_read_DMA1_0_PERIPHERAL_MAP() bfin_read16(DMA1_0_PERIPHERAL_MAP)
642#define bfin_write_DMA1_0_PERIPHERAL_MAP(val) bfin_write16(DMA1_0_PERIPHERAL_MAP,val)
643#define bfin_read_DMA1_1_CONFIG() bfin_read16(DMA1_1_CONFIG)
644#define bfin_write_DMA1_1_CONFIG(val) bfin_write16(DMA1_1_CONFIG,val)
645#define bfin_read_DMA1_1_NEXT_DESC_PTR() bfin_read32(DMA1_1_NEXT_DESC_PTR)
646#define bfin_write_DMA1_1_NEXT_DESC_PTR(val) bfin_write32(DMA1_1_NEXT_DESC_PTR,val)
647#define bfin_read_DMA1_1_START_ADDR() bfin_read32(DMA1_1_START_ADDR)
648#define bfin_write_DMA1_1_START_ADDR(val) bfin_write32(DMA1_1_START_ADDR,val)
649#define bfin_read_DMA1_1_X_COUNT() bfin_read16(DMA1_1_X_COUNT)
650#define bfin_write_DMA1_1_X_COUNT(val) bfin_write16(DMA1_1_X_COUNT,val)
651#define bfin_read_DMA1_1_Y_COUNT() bfin_read16(DMA1_1_Y_COUNT)
652#define bfin_write_DMA1_1_Y_COUNT(val) bfin_write16(DMA1_1_Y_COUNT,val)
653#define bfin_read_DMA1_1_X_MODIFY() bfin_read16(DMA1_1_X_MODIFY)
654#define bfin_write_DMA1_1_X_MODIFY(val) bfin_write16(DMA1_1_X_MODIFY,val)
655#define bfin_read_DMA1_1_Y_MODIFY() bfin_read16(DMA1_1_Y_MODIFY)
656#define bfin_write_DMA1_1_Y_MODIFY(val) bfin_write16(DMA1_1_Y_MODIFY,val)
657#define bfin_read_DMA1_1_CURR_DESC_PTR() bfin_read32(DMA1_1_CURR_DESC_PTR)
658#define bfin_write_DMA1_1_CURR_DESC_PTR(val) bfin_write32(DMA1_1_CURR_DESC_PTR,val)
659#define bfin_read_DMA1_1_CURR_ADDR() bfin_read32(DMA1_1_CURR_ADDR)
660#define bfin_write_DMA1_1_CURR_ADDR(val) bfin_write32(DMA1_1_CURR_ADDR,val)
661#define bfin_read_DMA1_1_CURR_X_COUNT() bfin_read16(DMA1_1_CURR_X_COUNT)
662#define bfin_write_DMA1_1_CURR_X_COUNT(val) bfin_write16(DMA1_1_CURR_X_COUNT,val)
663#define bfin_read_DMA1_1_CURR_Y_COUNT() bfin_read16(DMA1_1_CURR_Y_COUNT)
664#define bfin_write_DMA1_1_CURR_Y_COUNT(val) bfin_write16(DMA1_1_CURR_Y_COUNT,val)
665#define bfin_read_DMA1_1_IRQ_STATUS() bfin_read16(DMA1_1_IRQ_STATUS)
666#define bfin_write_DMA1_1_IRQ_STATUS(val) bfin_write16(DMA1_1_IRQ_STATUS,val)
667#define bfin_read_DMA1_1_PERIPHERAL_MAP() bfin_read16(DMA1_1_PERIPHERAL_MAP)
668#define bfin_write_DMA1_1_PERIPHERAL_MAP(val) bfin_write16(DMA1_1_PERIPHERAL_MAP,val)
669#define bfin_read_DMA1_2_CONFIG() bfin_read16(DMA1_2_CONFIG)
670#define bfin_write_DMA1_2_CONFIG(val) bfin_write16(DMA1_2_CONFIG,val)
671#define bfin_read_DMA1_2_NEXT_DESC_PTR() bfin_read32(DMA1_2_NEXT_DESC_PTR)
672#define bfin_write_DMA1_2_NEXT_DESC_PTR(val) bfin_write32(DMA1_2_NEXT_DESC_PTR,val)
673#define bfin_read_DMA1_2_START_ADDR() bfin_read32(DMA1_2_START_ADDR)
674#define bfin_write_DMA1_2_START_ADDR(val) bfin_write32(DMA1_2_START_ADDR,val)
675#define bfin_read_DMA1_2_X_COUNT() bfin_read16(DMA1_2_X_COUNT)
676#define bfin_write_DMA1_2_X_COUNT(val) bfin_write16(DMA1_2_X_COUNT,val)
677#define bfin_read_DMA1_2_Y_COUNT() bfin_read16(DMA1_2_Y_COUNT)
678#define bfin_write_DMA1_2_Y_COUNT(val) bfin_write16(DMA1_2_Y_COUNT,val)
679#define bfin_read_DMA1_2_X_MODIFY() bfin_read16(DMA1_2_X_MODIFY)
680#define bfin_write_DMA1_2_X_MODIFY(val) bfin_write16(DMA1_2_X_MODIFY,val)
681#define bfin_read_DMA1_2_Y_MODIFY() bfin_read16(DMA1_2_Y_MODIFY)
682#define bfin_write_DMA1_2_Y_MODIFY(val) bfin_write16(DMA1_2_Y_MODIFY,val)
683#define bfin_read_DMA1_2_CURR_DESC_PTR() bfin_read32(DMA1_2_CURR_DESC_PTR)
684#define bfin_write_DMA1_2_CURR_DESC_PTR(val) bfin_write32(DMA1_2_CURR_DESC_PTR,val)
685#define bfin_read_DMA1_2_CURR_ADDR() bfin_read32(DMA1_2_CURR_ADDR)
686#define bfin_write_DMA1_2_CURR_ADDR(val) bfin_write32(DMA1_2_CURR_ADDR,val)
687#define bfin_read_DMA1_2_CURR_X_COUNT() bfin_read16(DMA1_2_CURR_X_COUNT)
688#define bfin_write_DMA1_2_CURR_X_COUNT(val) bfin_write16(DMA1_2_CURR_X_COUNT,val)
689#define bfin_read_DMA1_2_CURR_Y_COUNT() bfin_read16(DMA1_2_CURR_Y_COUNT)
690#define bfin_write_DMA1_2_CURR_Y_COUNT(val) bfin_write16(DMA1_2_CURR_Y_COUNT,val)
691#define bfin_read_DMA1_2_IRQ_STATUS() bfin_read16(DMA1_2_IRQ_STATUS)
692#define bfin_write_DMA1_2_IRQ_STATUS(val) bfin_write16(DMA1_2_IRQ_STATUS,val)
693#define bfin_read_DMA1_2_PERIPHERAL_MAP() bfin_read16(DMA1_2_PERIPHERAL_MAP)
694#define bfin_write_DMA1_2_PERIPHERAL_MAP(val) bfin_write16(DMA1_2_PERIPHERAL_MAP,val)
695#define bfin_read_DMA1_3_CONFIG() bfin_read16(DMA1_3_CONFIG)
696#define bfin_write_DMA1_3_CONFIG(val) bfin_write16(DMA1_3_CONFIG,val)
697#define bfin_read_DMA1_3_NEXT_DESC_PTR() bfin_read32(DMA1_3_NEXT_DESC_PTR)
698#define bfin_write_DMA1_3_NEXT_DESC_PTR(val) bfin_write32(DMA1_3_NEXT_DESC_PTR,val)
699#define bfin_read_DMA1_3_START_ADDR() bfin_read32(DMA1_3_START_ADDR)
700#define bfin_write_DMA1_3_START_ADDR(val) bfin_write32(DMA1_3_START_ADDR,val)
701#define bfin_read_DMA1_3_X_COUNT() bfin_read16(DMA1_3_X_COUNT)
702#define bfin_write_DMA1_3_X_COUNT(val) bfin_write16(DMA1_3_X_COUNT,val)
703#define bfin_read_DMA1_3_Y_COUNT() bfin_read16(DMA1_3_Y_COUNT)
704#define bfin_write_DMA1_3_Y_COUNT(val) bfin_write16(DMA1_3_Y_COUNT,val)
705#define bfin_read_DMA1_3_X_MODIFY() bfin_read16(DMA1_3_X_MODIFY)
706#define bfin_write_DMA1_3_X_MODIFY(val) bfin_write16(DMA1_3_X_MODIFY,val)
707#define bfin_read_DMA1_3_Y_MODIFY() bfin_read16(DMA1_3_Y_MODIFY)
708#define bfin_write_DMA1_3_Y_MODIFY(val) bfin_write16(DMA1_3_Y_MODIFY,val)
709#define bfin_read_DMA1_3_CURR_DESC_PTR() bfin_read32(DMA1_3_CURR_DESC_PTR)
710#define bfin_write_DMA1_3_CURR_DESC_PTR(val) bfin_write32(DMA1_3_CURR_DESC_PTR,val)
711#define bfin_read_DMA1_3_CURR_ADDR() bfin_read32(DMA1_3_CURR_ADDR)
712#define bfin_write_DMA1_3_CURR_ADDR(val) bfin_write32(DMA1_3_CURR_ADDR,val)
713#define bfin_read_DMA1_3_CURR_X_COUNT() bfin_read16(DMA1_3_CURR_X_COUNT)
714#define bfin_write_DMA1_3_CURR_X_COUNT(val) bfin_write16(DMA1_3_CURR_X_COUNT,val)
715#define bfin_read_DMA1_3_CURR_Y_COUNT() bfin_read16(DMA1_3_CURR_Y_COUNT)
716#define bfin_write_DMA1_3_CURR_Y_COUNT(val) bfin_write16(DMA1_3_CURR_Y_COUNT,val)
717#define bfin_read_DMA1_3_IRQ_STATUS() bfin_read16(DMA1_3_IRQ_STATUS)
718#define bfin_write_DMA1_3_IRQ_STATUS(val) bfin_write16(DMA1_3_IRQ_STATUS,val)
719#define bfin_read_DMA1_3_PERIPHERAL_MAP() bfin_read16(DMA1_3_PERIPHERAL_MAP)
720#define bfin_write_DMA1_3_PERIPHERAL_MAP(val) bfin_write16(DMA1_3_PERIPHERAL_MAP,val)
721#define bfin_read_DMA1_4_CONFIG() bfin_read16(DMA1_4_CONFIG)
722#define bfin_write_DMA1_4_CONFIG(val) bfin_write16(DMA1_4_CONFIG,val)
723#define bfin_read_DMA1_4_NEXT_DESC_PTR() bfin_read32(DMA1_4_NEXT_DESC_PTR)
724#define bfin_write_DMA1_4_NEXT_DESC_PTR(val) bfin_write32(DMA1_4_NEXT_DESC_PTR,val)
725#define bfin_read_DMA1_4_START_ADDR() bfin_read32(DMA1_4_START_ADDR)
726#define bfin_write_DMA1_4_START_ADDR(val) bfin_write32(DMA1_4_START_ADDR,val)
727#define bfin_read_DMA1_4_X_COUNT() bfin_read16(DMA1_4_X_COUNT)
728#define bfin_write_DMA1_4_X_COUNT(val) bfin_write16(DMA1_4_X_COUNT,val)
729#define bfin_read_DMA1_4_Y_COUNT() bfin_read16(DMA1_4_Y_COUNT)
730#define bfin_write_DMA1_4_Y_COUNT(val) bfin_write16(DMA1_4_Y_COUNT,val)
731#define bfin_read_DMA1_4_X_MODIFY() bfin_read16(DMA1_4_X_MODIFY)
732#define bfin_write_DMA1_4_X_MODIFY(val) bfin_write16(DMA1_4_X_MODIFY,val)
733#define bfin_read_DMA1_4_Y_MODIFY() bfin_read16(DMA1_4_Y_MODIFY)
734#define bfin_write_DMA1_4_Y_MODIFY(val) bfin_write16(DMA1_4_Y_MODIFY,val)
735#define bfin_read_DMA1_4_CURR_DESC_PTR() bfin_read32(DMA1_4_CURR_DESC_PTR)
736#define bfin_write_DMA1_4_CURR_DESC_PTR(val) bfin_write32(DMA1_4_CURR_DESC_PTR,val)
737#define bfin_read_DMA1_4_CURR_ADDR() bfin_read32(DMA1_4_CURR_ADDR)
738#define bfin_write_DMA1_4_CURR_ADDR(val) bfin_write32(DMA1_4_CURR_ADDR,val)
739#define bfin_read_DMA1_4_CURR_X_COUNT() bfin_read16(DMA1_4_CURR_X_COUNT)
740#define bfin_write_DMA1_4_CURR_X_COUNT(val) bfin_write16(DMA1_4_CURR_X_COUNT,val)
741#define bfin_read_DMA1_4_CURR_Y_COUNT() bfin_read16(DMA1_4_CURR_Y_COUNT)
742#define bfin_write_DMA1_4_CURR_Y_COUNT(val) bfin_write16(DMA1_4_CURR_Y_COUNT,val)
743#define bfin_read_DMA1_4_IRQ_STATUS() bfin_read16(DMA1_4_IRQ_STATUS)
744#define bfin_write_DMA1_4_IRQ_STATUS(val) bfin_write16(DMA1_4_IRQ_STATUS,val)
745#define bfin_read_DMA1_4_PERIPHERAL_MAP() bfin_read16(DMA1_4_PERIPHERAL_MAP)
746#define bfin_write_DMA1_4_PERIPHERAL_MAP(val) bfin_write16(DMA1_4_PERIPHERAL_MAP,val)
747#define bfin_read_DMA1_5_CONFIG() bfin_read16(DMA1_5_CONFIG)
748#define bfin_write_DMA1_5_CONFIG(val) bfin_write16(DMA1_5_CONFIG,val)
749#define bfin_read_DMA1_5_NEXT_DESC_PTR() bfin_read32(DMA1_5_NEXT_DESC_PTR)
750#define bfin_write_DMA1_5_NEXT_DESC_PTR(val) bfin_write32(DMA1_5_NEXT_DESC_PTR,val)
751#define bfin_read_DMA1_5_START_ADDR() bfin_read32(DMA1_5_START_ADDR)
752#define bfin_write_DMA1_5_START_ADDR(val) bfin_write32(DMA1_5_START_ADDR,val)
753#define bfin_read_DMA1_5_X_COUNT() bfin_read16(DMA1_5_X_COUNT)
754#define bfin_write_DMA1_5_X_COUNT(val) bfin_write16(DMA1_5_X_COUNT,val)
755#define bfin_read_DMA1_5_Y_COUNT() bfin_read16(DMA1_5_Y_COUNT)
756#define bfin_write_DMA1_5_Y_COUNT(val) bfin_write16(DMA1_5_Y_COUNT,val)
757#define bfin_read_DMA1_5_X_MODIFY() bfin_read16(DMA1_5_X_MODIFY)
758#define bfin_write_DMA1_5_X_MODIFY(val) bfin_write16(DMA1_5_X_MODIFY,val)
759#define bfin_read_DMA1_5_Y_MODIFY() bfin_read16(DMA1_5_Y_MODIFY)
760#define bfin_write_DMA1_5_Y_MODIFY(val) bfin_write16(DMA1_5_Y_MODIFY,val)
761#define bfin_read_DMA1_5_CURR_DESC_PTR() bfin_read32(DMA1_5_CURR_DESC_PTR)
762#define bfin_write_DMA1_5_CURR_DESC_PTR(val) bfin_write32(DMA1_5_CURR_DESC_PTR,val)
763#define bfin_read_DMA1_5_CURR_ADDR() bfin_read32(DMA1_5_CURR_ADDR)
764#define bfin_write_DMA1_5_CURR_ADDR(val) bfin_write32(DMA1_5_CURR_ADDR,val)
765#define bfin_read_DMA1_5_CURR_X_COUNT() bfin_read16(DMA1_5_CURR_X_COUNT)
766#define bfin_write_DMA1_5_CURR_X_COUNT(val) bfin_write16(DMA1_5_CURR_X_COUNT,val)
767#define bfin_read_DMA1_5_CURR_Y_COUNT() bfin_read16(DMA1_5_CURR_Y_COUNT)
768#define bfin_write_DMA1_5_CURR_Y_COUNT(val) bfin_write16(DMA1_5_CURR_Y_COUNT,val)
769#define bfin_read_DMA1_5_IRQ_STATUS() bfin_read16(DMA1_5_IRQ_STATUS)
770#define bfin_write_DMA1_5_IRQ_STATUS(val) bfin_write16(DMA1_5_IRQ_STATUS,val)
771#define bfin_read_DMA1_5_PERIPHERAL_MAP() bfin_read16(DMA1_5_PERIPHERAL_MAP)
772#define bfin_write_DMA1_5_PERIPHERAL_MAP(val) bfin_write16(DMA1_5_PERIPHERAL_MAP,val)
773#define bfin_read_DMA1_6_CONFIG() bfin_read16(DMA1_6_CONFIG)
774#define bfin_write_DMA1_6_CONFIG(val) bfin_write16(DMA1_6_CONFIG,val)
775#define bfin_read_DMA1_6_NEXT_DESC_PTR() bfin_read32(DMA1_6_NEXT_DESC_PTR)
776#define bfin_write_DMA1_6_NEXT_DESC_PTR(val) bfin_write32(DMA1_6_NEXT_DESC_PTR,val)
777#define bfin_read_DMA1_6_START_ADDR() bfin_read32(DMA1_6_START_ADDR)
778#define bfin_write_DMA1_6_START_ADDR(val) bfin_write32(DMA1_6_START_ADDR,val)
779#define bfin_read_DMA1_6_X_COUNT() bfin_read16(DMA1_6_X_COUNT)
780#define bfin_write_DMA1_6_X_COUNT(val) bfin_write16(DMA1_6_X_COUNT,val)
781#define bfin_read_DMA1_6_Y_COUNT() bfin_read16(DMA1_6_Y_COUNT)
782#define bfin_write_DMA1_6_Y_COUNT(val) bfin_write16(DMA1_6_Y_COUNT,val)
783#define bfin_read_DMA1_6_X_MODIFY() bfin_read16(DMA1_6_X_MODIFY)
784#define bfin_write_DMA1_6_X_MODIFY(val) bfin_write16(DMA1_6_X_MODIFY,val)
785#define bfin_read_DMA1_6_Y_MODIFY() bfin_read16(DMA1_6_Y_MODIFY)
786#define bfin_write_DMA1_6_Y_MODIFY(val) bfin_write16(DMA1_6_Y_MODIFY,val)
787#define bfin_read_DMA1_6_CURR_DESC_PTR() bfin_read32(DMA1_6_CURR_DESC_PTR)
788#define bfin_write_DMA1_6_CURR_DESC_PTR(val) bfin_write32(DMA1_6_CURR_DESC_PTR,val)
789#define bfin_read_DMA1_6_CURR_ADDR() bfin_read32(DMA1_6_CURR_ADDR)
790#define bfin_write_DMA1_6_CURR_ADDR(val) bfin_write32(DMA1_6_CURR_ADDR,val)
791#define bfin_read_DMA1_6_CURR_X_COUNT() bfin_read16(DMA1_6_CURR_X_COUNT)
792#define bfin_write_DMA1_6_CURR_X_COUNT(val) bfin_write16(DMA1_6_CURR_X_COUNT,val)
793#define bfin_read_DMA1_6_CURR_Y_COUNT() bfin_read16(DMA1_6_CURR_Y_COUNT)
794#define bfin_write_DMA1_6_CURR_Y_COUNT(val) bfin_write16(DMA1_6_CURR_Y_COUNT,val)
795#define bfin_read_DMA1_6_IRQ_STATUS() bfin_read16(DMA1_6_IRQ_STATUS)
796#define bfin_write_DMA1_6_IRQ_STATUS(val) bfin_write16(DMA1_6_IRQ_STATUS,val)
797#define bfin_read_DMA1_6_PERIPHERAL_MAP() bfin_read16(DMA1_6_PERIPHERAL_MAP)
798#define bfin_write_DMA1_6_PERIPHERAL_MAP(val) bfin_write16(DMA1_6_PERIPHERAL_MAP,val)
799#define bfin_read_DMA1_7_CONFIG() bfin_read16(DMA1_7_CONFIG)
800#define bfin_write_DMA1_7_CONFIG(val) bfin_write16(DMA1_7_CONFIG,val)
801#define bfin_read_DMA1_7_NEXT_DESC_PTR() bfin_read32(DMA1_7_NEXT_DESC_PTR)
802#define bfin_write_DMA1_7_NEXT_DESC_PTR(val) bfin_write32(DMA1_7_NEXT_DESC_PTR,val)
803#define bfin_read_DMA1_7_START_ADDR() bfin_read32(DMA1_7_START_ADDR)
804#define bfin_write_DMA1_7_START_ADDR(val) bfin_write32(DMA1_7_START_ADDR,val)
805#define bfin_read_DMA1_7_X_COUNT() bfin_read16(DMA1_7_X_COUNT)
806#define bfin_write_DMA1_7_X_COUNT(val) bfin_write16(DMA1_7_X_COUNT,val)
807#define bfin_read_DMA1_7_Y_COUNT() bfin_read16(DMA1_7_Y_COUNT)
808#define bfin_write_DMA1_7_Y_COUNT(val) bfin_write16(DMA1_7_Y_COUNT,val)
809#define bfin_read_DMA1_7_X_MODIFY() bfin_read16(DMA1_7_X_MODIFY)
810#define bfin_write_DMA1_7_X_MODIFY(val) bfin_write16(DMA1_7_X_MODIFY,val)
811#define bfin_read_DMA1_7_Y_MODIFY() bfin_read16(DMA1_7_Y_MODIFY)
812#define bfin_write_DMA1_7_Y_MODIFY(val) bfin_write16(DMA1_7_Y_MODIFY,val)
813#define bfin_read_DMA1_7_CURR_DESC_PTR() bfin_read32(DMA1_7_CURR_DESC_PTR)
814#define bfin_write_DMA1_7_CURR_DESC_PTR(val) bfin_write32(DMA1_7_CURR_DESC_PTR,val)
815#define bfin_read_DMA1_7_CURR_ADDR() bfin_read32(DMA1_7_CURR_ADDR)
816#define bfin_write_DMA1_7_CURR_ADDR(val) bfin_write32(DMA1_7_CURR_ADDR,val)
817#define bfin_read_DMA1_7_CURR_X_COUNT() bfin_read16(DMA1_7_CURR_X_COUNT)
818#define bfin_write_DMA1_7_CURR_X_COUNT(val) bfin_write16(DMA1_7_CURR_X_COUNT,val)
819#define bfin_read_DMA1_7_CURR_Y_COUNT() bfin_read16(DMA1_7_CURR_Y_COUNT)
820#define bfin_write_DMA1_7_CURR_Y_COUNT(val) bfin_write16(DMA1_7_CURR_Y_COUNT,val)
821#define bfin_read_DMA1_7_IRQ_STATUS() bfin_read16(DMA1_7_IRQ_STATUS)
822#define bfin_write_DMA1_7_IRQ_STATUS(val) bfin_write16(DMA1_7_IRQ_STATUS,val)
823#define bfin_read_DMA1_7_PERIPHERAL_MAP() bfin_read16(DMA1_7_PERIPHERAL_MAP)
824#define bfin_write_DMA1_7_PERIPHERAL_MAP(val) bfin_write16(DMA1_7_PERIPHERAL_MAP,val)
825#define bfin_read_DMA1_8_CONFIG() bfin_read16(DMA1_8_CONFIG)
826#define bfin_write_DMA1_8_CONFIG(val) bfin_write16(DMA1_8_CONFIG,val)
827#define bfin_read_DMA1_8_NEXT_DESC_PTR() bfin_read32(DMA1_8_NEXT_DESC_PTR)
828#define bfin_write_DMA1_8_NEXT_DESC_PTR(val) bfin_write32(DMA1_8_NEXT_DESC_PTR,val)
829#define bfin_read_DMA1_8_START_ADDR() bfin_read32(DMA1_8_START_ADDR)
830#define bfin_write_DMA1_8_START_ADDR(val) bfin_write32(DMA1_8_START_ADDR,val)
831#define bfin_read_DMA1_8_X_COUNT() bfin_read16(DMA1_8_X_COUNT)
832#define bfin_write_DMA1_8_X_COUNT(val) bfin_write16(DMA1_8_X_COUNT,val)
833#define bfin_read_DMA1_8_Y_COUNT() bfin_read16(DMA1_8_Y_COUNT)
834#define bfin_write_DMA1_8_Y_COUNT(val) bfin_write16(DMA1_8_Y_COUNT,val)
835#define bfin_read_DMA1_8_X_MODIFY() bfin_read16(DMA1_8_X_MODIFY)
836#define bfin_write_DMA1_8_X_MODIFY(val) bfin_write16(DMA1_8_X_MODIFY,val)
837#define bfin_read_DMA1_8_Y_MODIFY() bfin_read16(DMA1_8_Y_MODIFY)
838#define bfin_write_DMA1_8_Y_MODIFY(val) bfin_write16(DMA1_8_Y_MODIFY,val)
839#define bfin_read_DMA1_8_CURR_DESC_PTR() bfin_read32(DMA1_8_CURR_DESC_PTR)
840#define bfin_write_DMA1_8_CURR_DESC_PTR(val) bfin_write32(DMA1_8_CURR_DESC_PTR,val)
841#define bfin_read_DMA1_8_CURR_ADDR() bfin_read32(DMA1_8_CURR_ADDR)
842#define bfin_write_DMA1_8_CURR_ADDR(val) bfin_write32(DMA1_8_CURR_ADDR,val)
843#define bfin_read_DMA1_8_CURR_X_COUNT() bfin_read16(DMA1_8_CURR_X_COUNT)
844#define bfin_write_DMA1_8_CURR_X_COUNT(val) bfin_write16(DMA1_8_CURR_X_COUNT,val)
845#define bfin_read_DMA1_8_CURR_Y_COUNT() bfin_read16(DMA1_8_CURR_Y_COUNT)
846#define bfin_write_DMA1_8_CURR_Y_COUNT(val) bfin_write16(DMA1_8_CURR_Y_COUNT,val)
847#define bfin_read_DMA1_8_IRQ_STATUS() bfin_read16(DMA1_8_IRQ_STATUS)
848#define bfin_write_DMA1_8_IRQ_STATUS(val) bfin_write16(DMA1_8_IRQ_STATUS,val)
849#define bfin_read_DMA1_8_PERIPHERAL_MAP() bfin_read16(DMA1_8_PERIPHERAL_MAP)
850#define bfin_write_DMA1_8_PERIPHERAL_MAP(val) bfin_write16(DMA1_8_PERIPHERAL_MAP,val)
851#define bfin_read_DMA1_9_CONFIG() bfin_read16(DMA1_9_CONFIG)
852#define bfin_write_DMA1_9_CONFIG(val) bfin_write16(DMA1_9_CONFIG,val)
853#define bfin_read_DMA1_9_NEXT_DESC_PTR() bfin_read32(DMA1_9_NEXT_DESC_PTR)
854#define bfin_write_DMA1_9_NEXT_DESC_PTR(val) bfin_write32(DMA1_9_NEXT_DESC_PTR,val)
855#define bfin_read_DMA1_9_START_ADDR() bfin_read32(DMA1_9_START_ADDR)
856#define bfin_write_DMA1_9_START_ADDR(val) bfin_write32(DMA1_9_START_ADDR,val)
857#define bfin_read_DMA1_9_X_COUNT() bfin_read16(DMA1_9_X_COUNT)
858#define bfin_write_DMA1_9_X_COUNT(val) bfin_write16(DMA1_9_X_COUNT,val)
859#define bfin_read_DMA1_9_Y_COUNT() bfin_read16(DMA1_9_Y_COUNT)
860#define bfin_write_DMA1_9_Y_COUNT(val) bfin_write16(DMA1_9_Y_COUNT,val)
861#define bfin_read_DMA1_9_X_MODIFY() bfin_read16(DMA1_9_X_MODIFY)
862#define bfin_write_DMA1_9_X_MODIFY(val) bfin_write16(DMA1_9_X_MODIFY,val)
863#define bfin_read_DMA1_9_Y_MODIFY() bfin_read16(DMA1_9_Y_MODIFY)
864#define bfin_write_DMA1_9_Y_MODIFY(val) bfin_write16(DMA1_9_Y_MODIFY,val)
865#define bfin_read_DMA1_9_CURR_DESC_PTR() bfin_read32(DMA1_9_CURR_DESC_PTR)
866#define bfin_write_DMA1_9_CURR_DESC_PTR(val) bfin_write32(DMA1_9_CURR_DESC_PTR,val)
867#define bfin_read_DMA1_9_CURR_ADDR() bfin_read32(DMA1_9_CURR_ADDR)
868#define bfin_write_DMA1_9_CURR_ADDR(val) bfin_write32(DMA1_9_CURR_ADDR,val)
869#define bfin_read_DMA1_9_CURR_X_COUNT() bfin_read16(DMA1_9_CURR_X_COUNT)
870#define bfin_write_DMA1_9_CURR_X_COUNT(val) bfin_write16(DMA1_9_CURR_X_COUNT,val)
871#define bfin_read_DMA1_9_CURR_Y_COUNT() bfin_read16(DMA1_9_CURR_Y_COUNT)
872#define bfin_write_DMA1_9_CURR_Y_COUNT(val) bfin_write16(DMA1_9_CURR_Y_COUNT,val)
873#define bfin_read_DMA1_9_IRQ_STATUS() bfin_read16(DMA1_9_IRQ_STATUS)
874#define bfin_write_DMA1_9_IRQ_STATUS(val) bfin_write16(DMA1_9_IRQ_STATUS,val)
875#define bfin_read_DMA1_9_PERIPHERAL_MAP() bfin_read16(DMA1_9_PERIPHERAL_MAP)
876#define bfin_write_DMA1_9_PERIPHERAL_MAP(val) bfin_write16(DMA1_9_PERIPHERAL_MAP,val)
877#define bfin_read_DMA1_10_CONFIG() bfin_read16(DMA1_10_CONFIG)
878#define bfin_write_DMA1_10_CONFIG(val) bfin_write16(DMA1_10_CONFIG,val)
879#define bfin_read_DMA1_10_NEXT_DESC_PTR() bfin_read32(DMA1_10_NEXT_DESC_PTR)
880#define bfin_write_DMA1_10_NEXT_DESC_PTR(val) bfin_write32(DMA1_10_NEXT_DESC_PTR,val)
881#define bfin_read_DMA1_10_START_ADDR() bfin_read32(DMA1_10_START_ADDR)
882#define bfin_write_DMA1_10_START_ADDR(val) bfin_write32(DMA1_10_START_ADDR,val)
883#define bfin_read_DMA1_10_X_COUNT() bfin_read16(DMA1_10_X_COUNT)
884#define bfin_write_DMA1_10_X_COUNT(val) bfin_write16(DMA1_10_X_COUNT,val)
885#define bfin_read_DMA1_10_Y_COUNT() bfin_read16(DMA1_10_Y_COUNT)
886#define bfin_write_DMA1_10_Y_COUNT(val) bfin_write16(DMA1_10_Y_COUNT,val)
887#define bfin_read_DMA1_10_X_MODIFY() bfin_read16(DMA1_10_X_MODIFY)
888#define bfin_write_DMA1_10_X_MODIFY(val) bfin_write16(DMA1_10_X_MODIFY,val)
889#define bfin_read_DMA1_10_Y_MODIFY() bfin_read16(DMA1_10_Y_MODIFY)
890#define bfin_write_DMA1_10_Y_MODIFY(val) bfin_write16(DMA1_10_Y_MODIFY,val)
891#define bfin_read_DMA1_10_CURR_DESC_PTR() bfin_read32(DMA1_10_CURR_DESC_PTR)
892#define bfin_write_DMA1_10_CURR_DESC_PTR(val) bfin_write32(DMA1_10_CURR_DESC_PTR,val)
893#define bfin_read_DMA1_10_CURR_ADDR() bfin_read32(DMA1_10_CURR_ADDR)
894#define bfin_write_DMA1_10_CURR_ADDR(val) bfin_write32(DMA1_10_CURR_ADDR,val)
895#define bfin_read_DMA1_10_CURR_X_COUNT() bfin_read16(DMA1_10_CURR_X_COUNT)
896#define bfin_write_DMA1_10_CURR_X_COUNT(val) bfin_write16(DMA1_10_CURR_X_COUNT,val)
897#define bfin_read_DMA1_10_CURR_Y_COUNT() bfin_read16(DMA1_10_CURR_Y_COUNT)
898#define bfin_write_DMA1_10_CURR_Y_COUNT(val) bfin_write16(DMA1_10_CURR_Y_COUNT,val)
899#define bfin_read_DMA1_10_IRQ_STATUS() bfin_read16(DMA1_10_IRQ_STATUS)
900#define bfin_write_DMA1_10_IRQ_STATUS(val) bfin_write16(DMA1_10_IRQ_STATUS,val)
901#define bfin_read_DMA1_10_PERIPHERAL_MAP() bfin_read16(DMA1_10_PERIPHERAL_MAP)
902#define bfin_write_DMA1_10_PERIPHERAL_MAP(val) bfin_write16(DMA1_10_PERIPHERAL_MAP,val)
903#define bfin_read_DMA1_11_CONFIG() bfin_read16(DMA1_11_CONFIG)
904#define bfin_write_DMA1_11_CONFIG(val) bfin_write16(DMA1_11_CONFIG,val)
905#define bfin_read_DMA1_11_NEXT_DESC_PTR() bfin_read32(DMA1_11_NEXT_DESC_PTR)
906#define bfin_write_DMA1_11_NEXT_DESC_PTR(val) bfin_write32(DMA1_11_NEXT_DESC_PTR,val)
907#define bfin_read_DMA1_11_START_ADDR() bfin_read32(DMA1_11_START_ADDR)
908#define bfin_write_DMA1_11_START_ADDR(val) bfin_write32(DMA1_11_START_ADDR,val)
909#define bfin_read_DMA1_11_X_COUNT() bfin_read16(DMA1_11_X_COUNT)
910#define bfin_write_DMA1_11_X_COUNT(val) bfin_write16(DMA1_11_X_COUNT,val)
911#define bfin_read_DMA1_11_Y_COUNT() bfin_read16(DMA1_11_Y_COUNT)
912#define bfin_write_DMA1_11_Y_COUNT(val) bfin_write16(DMA1_11_Y_COUNT,val)
913#define bfin_read_DMA1_11_X_MODIFY() bfin_read16(DMA1_11_X_MODIFY)
914#define bfin_write_DMA1_11_X_MODIFY(val) bfin_write16(DMA1_11_X_MODIFY,val)
915#define bfin_read_DMA1_11_Y_MODIFY() bfin_read16(DMA1_11_Y_MODIFY)
916#define bfin_write_DMA1_11_Y_MODIFY(val) bfin_write16(DMA1_11_Y_MODIFY,val)
917#define bfin_read_DMA1_11_CURR_DESC_PTR() bfin_read32(DMA1_11_CURR_DESC_PTR)
918#define bfin_write_DMA1_11_CURR_DESC_PTR(val) bfin_write32(DMA1_11_CURR_DESC_PTR,val)
919#define bfin_read_DMA1_11_CURR_ADDR() bfin_read32(DMA1_11_CURR_ADDR)
920#define bfin_write_DMA1_11_CURR_ADDR(val) bfin_write32(DMA1_11_CURR_ADDR,val)
921#define bfin_read_DMA1_11_CURR_X_COUNT() bfin_read16(DMA1_11_CURR_X_COUNT)
922#define bfin_write_DMA1_11_CURR_X_COUNT(val) bfin_write16(DMA1_11_CURR_X_COUNT,val)
923#define bfin_read_DMA1_11_CURR_Y_COUNT() bfin_read16(DMA1_11_CURR_Y_COUNT)
924#define bfin_write_DMA1_11_CURR_Y_COUNT(val) bfin_write16(DMA1_11_CURR_Y_COUNT,val)
925#define bfin_read_DMA1_11_IRQ_STATUS() bfin_read16(DMA1_11_IRQ_STATUS)
926#define bfin_write_DMA1_11_IRQ_STATUS(val) bfin_write16(DMA1_11_IRQ_STATUS,val)
927#define bfin_read_DMA1_11_PERIPHERAL_MAP() bfin_read16(DMA1_11_PERIPHERAL_MAP)
928#define bfin_write_DMA1_11_PERIPHERAL_MAP(val) bfin_write16(DMA1_11_PERIPHERAL_MAP,val)
929/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */
930#define bfin_read_MDMA1_D0_CONFIG() bfin_read16(MDMA1_D0_CONFIG)
931#define bfin_write_MDMA1_D0_CONFIG(val) bfin_write16(MDMA1_D0_CONFIG,val)
932#define bfin_read_MDMA1_D0_NEXT_DESC_PTR() bfin_read32(MDMA1_D0_NEXT_DESC_PTR)
933#define bfin_write_MDMA1_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA1_D0_NEXT_DESC_PTR,val)
934#define bfin_read_MDMA1_D0_START_ADDR() bfin_read32(MDMA1_D0_START_ADDR)
935#define bfin_write_MDMA1_D0_START_ADDR(val) bfin_write32(MDMA1_D0_START_ADDR,val)
936#define bfin_read_MDMA1_D0_X_COUNT() bfin_read16(MDMA1_D0_X_COUNT)
937#define bfin_write_MDMA1_D0_X_COUNT(val) bfin_write16(MDMA1_D0_X_COUNT,val)
938#define bfin_read_MDMA1_D0_Y_COUNT() bfin_read16(MDMA1_D0_Y_COUNT)
939#define bfin_write_MDMA1_D0_Y_COUNT(val) bfin_write16(MDMA1_D0_Y_COUNT,val)
940#define bfin_read_MDMA1_D0_X_MODIFY() bfin_read16(MDMA1_D0_X_MODIFY)
941#define bfin_write_MDMA1_D0_X_MODIFY(val) bfin_write16(MDMA1_D0_X_MODIFY,val)
942#define bfin_read_MDMA1_D0_Y_MODIFY() bfin_read16(MDMA1_D0_Y_MODIFY)
943#define bfin_write_MDMA1_D0_Y_MODIFY(val) bfin_write16(MDMA1_D0_Y_MODIFY,val)
944#define bfin_read_MDMA1_D0_CURR_DESC_PTR() bfin_read32(MDMA1_D0_CURR_DESC_PTR)
945#define bfin_write_MDMA1_D0_CURR_DESC_PTR(val) bfin_write32(MDMA1_D0_CURR_DESC_PTR,val)
946#define bfin_read_MDMA1_D0_CURR_ADDR() bfin_read32(MDMA1_D0_CURR_ADDR)
947#define bfin_write_MDMA1_D0_CURR_ADDR(val) bfin_write32(MDMA1_D0_CURR_ADDR,val)
948#define bfin_read_MDMA1_D0_CURR_X_COUNT() bfin_read16(MDMA1_D0_CURR_X_COUNT)
949#define bfin_write_MDMA1_D0_CURR_X_COUNT(val) bfin_write16(MDMA1_D0_CURR_X_COUNT,val)
950#define bfin_read_MDMA1_D0_CURR_Y_COUNT() bfin_read16(MDMA1_D0_CURR_Y_COUNT)
951#define bfin_write_MDMA1_D0_CURR_Y_COUNT(val) bfin_write16(MDMA1_D0_CURR_Y_COUNT,val)
952#define bfin_read_MDMA1_D0_IRQ_STATUS() bfin_read16(MDMA1_D0_IRQ_STATUS)
953#define bfin_write_MDMA1_D0_IRQ_STATUS(val) bfin_write16(MDMA1_D0_IRQ_STATUS,val)
954#define bfin_read_MDMA1_D0_PERIPHERAL_MAP() bfin_read16(MDMA1_D0_PERIPHERAL_MAP)
955#define bfin_write_MDMA1_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D0_PERIPHERAL_MAP,val)
956#define bfin_read_MDMA1_S0_CONFIG() bfin_read16(MDMA1_S0_CONFIG)
957#define bfin_write_MDMA1_S0_CONFIG(val) bfin_write16(MDMA1_S0_CONFIG,val)
958#define bfin_read_MDMA1_S0_NEXT_DESC_PTR() bfin_read32(MDMA1_S0_NEXT_DESC_PTR)
959#define bfin_write_MDMA1_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA1_S0_NEXT_DESC_PTR,val)
960#define bfin_read_MDMA1_S0_START_ADDR() bfin_read32(MDMA1_S0_START_ADDR)
961#define bfin_write_MDMA1_S0_START_ADDR(val) bfin_write32(MDMA1_S0_START_ADDR,val)
962#define bfin_read_MDMA1_S0_X_COUNT() bfin_read16(MDMA1_S0_X_COUNT)
963#define bfin_write_MDMA1_S0_X_COUNT(val) bfin_write16(MDMA1_S0_X_COUNT,val)
964#define bfin_read_MDMA1_S0_Y_COUNT() bfin_read16(MDMA1_S0_Y_COUNT)
965#define bfin_write_MDMA1_S0_Y_COUNT(val) bfin_write16(MDMA1_S0_Y_COUNT,val)
966#define bfin_read_MDMA1_S0_X_MODIFY() bfin_read16(MDMA1_S0_X_MODIFY)
967#define bfin_write_MDMA1_S0_X_MODIFY(val) bfin_write16(MDMA1_S0_X_MODIFY,val)
968#define bfin_read_MDMA1_S0_Y_MODIFY() bfin_read16(MDMA1_S0_Y_MODIFY)
969#define bfin_write_MDMA1_S0_Y_MODIFY(val) bfin_write16(MDMA1_S0_Y_MODIFY,val)
970#define bfin_read_MDMA1_S0_CURR_DESC_PTR() bfin_read32(MDMA1_S0_CURR_DESC_PTR)
971#define bfin_write_MDMA1_S0_CURR_DESC_PTR(val) bfin_write32(MDMA1_S0_CURR_DESC_PTR,val)
972#define bfin_read_MDMA1_S0_CURR_ADDR() bfin_read32(MDMA1_S0_CURR_ADDR)
973#define bfin_write_MDMA1_S0_CURR_ADDR(val) bfin_write32(MDMA1_S0_CURR_ADDR,val)
974#define bfin_read_MDMA1_S0_CURR_X_COUNT() bfin_read16(MDMA1_S0_CURR_X_COUNT)
975#define bfin_write_MDMA1_S0_CURR_X_COUNT(val) bfin_write16(MDMA1_S0_CURR_X_COUNT,val)
976#define bfin_read_MDMA1_S0_CURR_Y_COUNT() bfin_read16(MDMA1_S0_CURR_Y_COUNT)
977#define bfin_write_MDMA1_S0_CURR_Y_COUNT(val) bfin_write16(MDMA1_S0_CURR_Y_COUNT,val)
978#define bfin_read_MDMA1_S0_IRQ_STATUS() bfin_read16(MDMA1_S0_IRQ_STATUS)
979#define bfin_write_MDMA1_S0_IRQ_STATUS(val) bfin_write16(MDMA1_S0_IRQ_STATUS,val)
980#define bfin_read_MDMA1_S0_PERIPHERAL_MAP() bfin_read16(MDMA1_S0_PERIPHERAL_MAP)
981#define bfin_write_MDMA1_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S0_PERIPHERAL_MAP,val)
982#define bfin_read_MDMA1_D1_CONFIG() bfin_read16(MDMA1_D1_CONFIG)
983#define bfin_write_MDMA1_D1_CONFIG(val) bfin_write16(MDMA1_D1_CONFIG,val)
984#define bfin_read_MDMA1_D1_NEXT_DESC_PTR() bfin_read32(MDMA1_D1_NEXT_DESC_PTR)
985#define bfin_write_MDMA1_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA1_D1_NEXT_DESC_PTR,val)
986#define bfin_read_MDMA1_D1_START_ADDR() bfin_read32(MDMA1_D1_START_ADDR)
987#define bfin_write_MDMA1_D1_START_ADDR(val) bfin_write32(MDMA1_D1_START_ADDR,val)
988#define bfin_read_MDMA1_D1_X_COUNT() bfin_read16(MDMA1_D1_X_COUNT)
989#define bfin_write_MDMA1_D1_X_COUNT(val) bfin_write16(MDMA1_D1_X_COUNT,val)
990#define bfin_read_MDMA1_D1_Y_COUNT() bfin_read16(MDMA1_D1_Y_COUNT)
991#define bfin_write_MDMA1_D1_Y_COUNT(val) bfin_write16(MDMA1_D1_Y_COUNT,val)
992#define bfin_read_MDMA1_D1_X_MODIFY() bfin_read16(MDMA1_D1_X_MODIFY)
993#define bfin_write_MDMA1_D1_X_MODIFY(val) bfin_write16(MDMA1_D1_X_MODIFY,val)
994#define bfin_read_MDMA1_D1_Y_MODIFY() bfin_read16(MDMA1_D1_Y_MODIFY)
995#define bfin_write_MDMA1_D1_Y_MODIFY(val) bfin_write16(MDMA1_D1_Y_MODIFY,val)
996#define bfin_read_MDMA1_D1_CURR_DESC_PTR() bfin_read32(MDMA1_D1_CURR_DESC_PTR)
997#define bfin_write_MDMA1_D1_CURR_DESC_PTR(val) bfin_write32(MDMA1_D1_CURR_DESC_PTR,val)
998#define bfin_read_MDMA1_D1_CURR_ADDR() bfin_read32(MDMA1_D1_CURR_ADDR)
999#define bfin_write_MDMA1_D1_CURR_ADDR(val) bfin_write32(MDMA1_D1_CURR_ADDR,val)
1000#define bfin_read_MDMA1_D1_CURR_X_COUNT() bfin_read16(MDMA1_D1_CURR_X_COUNT)
1001#define bfin_write_MDMA1_D1_CURR_X_COUNT(val) bfin_write16(MDMA1_D1_CURR_X_COUNT,val)
1002#define bfin_read_MDMA1_D1_CURR_Y_COUNT() bfin_read16(MDMA1_D1_CURR_Y_COUNT)
1003#define bfin_write_MDMA1_D1_CURR_Y_COUNT(val) bfin_write16(MDMA1_D1_CURR_Y_COUNT,val)
1004#define bfin_read_MDMA1_D1_IRQ_STATUS() bfin_read16(MDMA1_D1_IRQ_STATUS)
1005#define bfin_write_MDMA1_D1_IRQ_STATUS(val) bfin_write16(MDMA1_D1_IRQ_STATUS,val)
1006#define bfin_read_MDMA1_D1_PERIPHERAL_MAP() bfin_read16(MDMA1_D1_PERIPHERAL_MAP)
1007#define bfin_write_MDMA1_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D1_PERIPHERAL_MAP,val)
1008#define bfin_read_MDMA1_S1_CONFIG() bfin_read16(MDMA1_S1_CONFIG)
1009#define bfin_write_MDMA1_S1_CONFIG(val) bfin_write16(MDMA1_S1_CONFIG,val)
1010#define bfin_read_MDMA1_S1_NEXT_DESC_PTR() bfin_read32(MDMA1_S1_NEXT_DESC_PTR)
1011#define bfin_write_MDMA1_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA1_S1_NEXT_DESC_PTR,val)
1012#define bfin_read_MDMA1_S1_START_ADDR() bfin_read32(MDMA1_S1_START_ADDR)
1013#define bfin_write_MDMA1_S1_START_ADDR(val) bfin_write32(MDMA1_S1_START_ADDR,val)
1014#define bfin_read_MDMA1_S1_X_COUNT() bfin_read16(MDMA1_S1_X_COUNT)
1015#define bfin_write_MDMA1_S1_X_COUNT(val) bfin_write16(MDMA1_S1_X_COUNT,val)
1016#define bfin_read_MDMA1_S1_Y_COUNT() bfin_read16(MDMA1_S1_Y_COUNT)
1017#define bfin_write_MDMA1_S1_Y_COUNT(val) bfin_write16(MDMA1_S1_Y_COUNT,val)
1018#define bfin_read_MDMA1_S1_X_MODIFY() bfin_read16(MDMA1_S1_X_MODIFY)
1019#define bfin_write_MDMA1_S1_X_MODIFY(val) bfin_write16(MDMA1_S1_X_MODIFY,val)
1020#define bfin_read_MDMA1_S1_Y_MODIFY() bfin_read16(MDMA1_S1_Y_MODIFY)
1021#define bfin_write_MDMA1_S1_Y_MODIFY(val) bfin_write16(MDMA1_S1_Y_MODIFY,val)
1022#define bfin_read_MDMA1_S1_CURR_DESC_PTR() bfin_read32(MDMA1_S1_CURR_DESC_PTR)
1023#define bfin_write_MDMA1_S1_CURR_DESC_PTR(val) bfin_write32(MDMA1_S1_CURR_DESC_PTR,val)
1024#define bfin_read_MDMA1_S1_CURR_ADDR() bfin_read32(MDMA1_S1_CURR_ADDR)
1025#define bfin_write_MDMA1_S1_CURR_ADDR(val) bfin_write32(MDMA1_S1_CURR_ADDR,val)
1026#define bfin_read_MDMA1_S1_CURR_X_COUNT() bfin_read16(MDMA1_S1_CURR_X_COUNT)
1027#define bfin_write_MDMA1_S1_CURR_X_COUNT(val) bfin_write16(MDMA1_S1_CURR_X_COUNT,val)
1028#define bfin_read_MDMA1_S1_CURR_Y_COUNT() bfin_read16(MDMA1_S1_CURR_Y_COUNT)
1029#define bfin_write_MDMA1_S1_CURR_Y_COUNT(val) bfin_write16(MDMA1_S1_CURR_Y_COUNT,val)
1030#define bfin_read_MDMA1_S1_IRQ_STATUS() bfin_read16(MDMA1_S1_IRQ_STATUS)
1031#define bfin_write_MDMA1_S1_IRQ_STATUS(val) bfin_write16(MDMA1_S1_IRQ_STATUS,val)
1032#define bfin_read_MDMA1_S1_PERIPHERAL_MAP() bfin_read16(MDMA1_S1_PERIPHERAL_MAP)
1033#define bfin_write_MDMA1_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S1_PERIPHERAL_MAP,val)
1034/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */
1035#define bfin_read_DMA2_0_CONFIG() bfin_read16(DMA2_0_CONFIG)
1036#define bfin_write_DMA2_0_CONFIG(val) bfin_write16(DMA2_0_CONFIG,val)
1037#define bfin_read_DMA2_0_NEXT_DESC_PTR() bfin_read32(DMA2_0_NEXT_DESC_PTR)
1038#define bfin_write_DMA2_0_NEXT_DESC_PTR(val) bfin_write32(DMA2_0_NEXT_DESC_PTR,val)
1039#define bfin_read_DMA2_0_START_ADDR() bfin_read32(DMA2_0_START_ADDR)
1040#define bfin_write_DMA2_0_START_ADDR(val) bfin_write32(DMA2_0_START_ADDR,val)
1041#define bfin_read_DMA2_0_X_COUNT() bfin_read16(DMA2_0_X_COUNT)
1042#define bfin_write_DMA2_0_X_COUNT(val) bfin_write16(DMA2_0_X_COUNT,val)
1043#define bfin_read_DMA2_0_Y_COUNT() bfin_read16(DMA2_0_Y_COUNT)
1044#define bfin_write_DMA2_0_Y_COUNT(val) bfin_write16(DMA2_0_Y_COUNT,val)
1045#define bfin_read_DMA2_0_X_MODIFY() bfin_read16(DMA2_0_X_MODIFY)
1046#define bfin_write_DMA2_0_X_MODIFY(val) bfin_write16(DMA2_0_X_MODIFY,val)
1047#define bfin_read_DMA2_0_Y_MODIFY() bfin_read16(DMA2_0_Y_MODIFY)
1048#define bfin_write_DMA2_0_Y_MODIFY(val) bfin_write16(DMA2_0_Y_MODIFY,val)
1049#define bfin_read_DMA2_0_CURR_DESC_PTR() bfin_read32(DMA2_0_CURR_DESC_PTR)
1050#define bfin_write_DMA2_0_CURR_DESC_PTR(val) bfin_write32(DMA2_0_CURR_DESC_PTR,val)
1051#define bfin_read_DMA2_0_CURR_ADDR() bfin_read32(DMA2_0_CURR_ADDR)
1052#define bfin_write_DMA2_0_CURR_ADDR(val) bfin_write32(DMA2_0_CURR_ADDR,val)
1053#define bfin_read_DMA2_0_CURR_X_COUNT() bfin_read16(DMA2_0_CURR_X_COUNT)
1054#define bfin_write_DMA2_0_CURR_X_COUNT(val) bfin_write16(DMA2_0_CURR_X_COUNT,val)
1055#define bfin_read_DMA2_0_CURR_Y_COUNT() bfin_read16(DMA2_0_CURR_Y_COUNT)
1056#define bfin_write_DMA2_0_CURR_Y_COUNT(val) bfin_write16(DMA2_0_CURR_Y_COUNT,val)
1057#define bfin_read_DMA2_0_IRQ_STATUS() bfin_read16(DMA2_0_IRQ_STATUS)
1058#define bfin_write_DMA2_0_IRQ_STATUS(val) bfin_write16(DMA2_0_IRQ_STATUS,val)
1059#define bfin_read_DMA2_0_PERIPHERAL_MAP() bfin_read16(DMA2_0_PERIPHERAL_MAP)
1060#define bfin_write_DMA2_0_PERIPHERAL_MAP(val) bfin_write16(DMA2_0_PERIPHERAL_MAP,val)
1061#define bfin_read_DMA2_1_CONFIG() bfin_read16(DMA2_1_CONFIG)
1062#define bfin_write_DMA2_1_CONFIG(val) bfin_write16(DMA2_1_CONFIG,val)
1063#define bfin_read_DMA2_1_NEXT_DESC_PTR() bfin_read32(DMA2_1_NEXT_DESC_PTR)
1064#define bfin_write_DMA2_1_NEXT_DESC_PTR(val) bfin_write32(DMA2_1_NEXT_DESC_PTR,val)
1065#define bfin_read_DMA2_1_START_ADDR() bfin_read32(DMA2_1_START_ADDR)
1066#define bfin_write_DMA2_1_START_ADDR(val) bfin_write32(DMA2_1_START_ADDR,val)
1067#define bfin_read_DMA2_1_X_COUNT() bfin_read16(DMA2_1_X_COUNT)
1068#define bfin_write_DMA2_1_X_COUNT(val) bfin_write16(DMA2_1_X_COUNT,val)
1069#define bfin_read_DMA2_1_Y_COUNT() bfin_read16(DMA2_1_Y_COUNT)
1070#define bfin_write_DMA2_1_Y_COUNT(val) bfin_write16(DMA2_1_Y_COUNT,val)
1071#define bfin_read_DMA2_1_X_MODIFY() bfin_read16(DMA2_1_X_MODIFY)
1072#define bfin_write_DMA2_1_X_MODIFY(val) bfin_write16(DMA2_1_X_MODIFY,val)
1073#define bfin_read_DMA2_1_Y_MODIFY() bfin_read16(DMA2_1_Y_MODIFY)
1074#define bfin_write_DMA2_1_Y_MODIFY(val) bfin_write16(DMA2_1_Y_MODIFY,val)
1075#define bfin_read_DMA2_1_CURR_DESC_PTR() bfin_read32(DMA2_1_CURR_DESC_PTR)
1076#define bfin_write_DMA2_1_CURR_DESC_PTR(val) bfin_write32(DMA2_1_CURR_DESC_PTR,val)
1077#define bfin_read_DMA2_1_CURR_ADDR() bfin_read32(DMA2_1_CURR_ADDR)
1078#define bfin_write_DMA2_1_CURR_ADDR(val) bfin_write32(DMA2_1_CURR_ADDR,val)
1079#define bfin_read_DMA2_1_CURR_X_COUNT() bfin_read16(DMA2_1_CURR_X_COUNT)
1080#define bfin_write_DMA2_1_CURR_X_COUNT(val) bfin_write16(DMA2_1_CURR_X_COUNT,val)
1081#define bfin_read_DMA2_1_CURR_Y_COUNT() bfin_read16(DMA2_1_CURR_Y_COUNT)
1082#define bfin_write_DMA2_1_CURR_Y_COUNT(val) bfin_write16(DMA2_1_CURR_Y_COUNT,val)
1083#define bfin_read_DMA2_1_IRQ_STATUS() bfin_read16(DMA2_1_IRQ_STATUS)
1084#define bfin_write_DMA2_1_IRQ_STATUS(val) bfin_write16(DMA2_1_IRQ_STATUS,val)
1085#define bfin_read_DMA2_1_PERIPHERAL_MAP() bfin_read16(DMA2_1_PERIPHERAL_MAP)
1086#define bfin_write_DMA2_1_PERIPHERAL_MAP(val) bfin_write16(DMA2_1_PERIPHERAL_MAP,val)
1087#define bfin_read_DMA2_2_CONFIG() bfin_read16(DMA2_2_CONFIG)
1088#define bfin_write_DMA2_2_CONFIG(val) bfin_write16(DMA2_2_CONFIG,val)
1089#define bfin_read_DMA2_2_NEXT_DESC_PTR() bfin_read32(DMA2_2_NEXT_DESC_PTR)
1090#define bfin_write_DMA2_2_NEXT_DESC_PTR(val) bfin_write32(DMA2_2_NEXT_DESC_PTR,val)
1091#define bfin_read_DMA2_2_START_ADDR() bfin_read32(DMA2_2_START_ADDR)
1092#define bfin_write_DMA2_2_START_ADDR(val) bfin_write32(DMA2_2_START_ADDR,val)
1093#define bfin_read_DMA2_2_X_COUNT() bfin_read16(DMA2_2_X_COUNT)
1094#define bfin_write_DMA2_2_X_COUNT(val) bfin_write16(DMA2_2_X_COUNT,val)
1095#define bfin_read_DMA2_2_Y_COUNT() bfin_read16(DMA2_2_Y_COUNT)
1096#define bfin_write_DMA2_2_Y_COUNT(val) bfin_write16(DMA2_2_Y_COUNT,val)
1097#define bfin_read_DMA2_2_X_MODIFY() bfin_read16(DMA2_2_X_MODIFY)
1098#define bfin_write_DMA2_2_X_MODIFY(val) bfin_write16(DMA2_2_X_MODIFY,val)
1099#define bfin_read_DMA2_2_Y_MODIFY() bfin_read16(DMA2_2_Y_MODIFY)
1100#define bfin_write_DMA2_2_Y_MODIFY(val) bfin_write16(DMA2_2_Y_MODIFY,val)
1101#define bfin_read_DMA2_2_CURR_DESC_PTR() bfin_read32(DMA2_2_CURR_DESC_PTR)
1102#define bfin_write_DMA2_2_CURR_DESC_PTR(val) bfin_write32(DMA2_2_CURR_DESC_PTR,val)
1103#define bfin_read_DMA2_2_CURR_ADDR() bfin_read32(DMA2_2_CURR_ADDR)
1104#define bfin_write_DMA2_2_CURR_ADDR(val) bfin_write32(DMA2_2_CURR_ADDR,val)
1105#define bfin_read_DMA2_2_CURR_X_COUNT() bfin_read16(DMA2_2_CURR_X_COUNT)
1106#define bfin_write_DMA2_2_CURR_X_COUNT(val) bfin_write16(DMA2_2_CURR_X_COUNT,val)
1107#define bfin_read_DMA2_2_CURR_Y_COUNT() bfin_read16(DMA2_2_CURR_Y_COUNT)
1108#define bfin_write_DMA2_2_CURR_Y_COUNT(val) bfin_write16(DMA2_2_CURR_Y_COUNT,val)
1109#define bfin_read_DMA2_2_IRQ_STATUS() bfin_read16(DMA2_2_IRQ_STATUS)
1110#define bfin_write_DMA2_2_IRQ_STATUS(val) bfin_write16(DMA2_2_IRQ_STATUS,val)
1111#define bfin_read_DMA2_2_PERIPHERAL_MAP() bfin_read16(DMA2_2_PERIPHERAL_MAP)
1112#define bfin_write_DMA2_2_PERIPHERAL_MAP(val) bfin_write16(DMA2_2_PERIPHERAL_MAP,val)
1113#define bfin_read_DMA2_3_CONFIG() bfin_read16(DMA2_3_CONFIG)
1114#define bfin_write_DMA2_3_CONFIG(val) bfin_write16(DMA2_3_CONFIG,val)
1115#define bfin_read_DMA2_3_NEXT_DESC_PTR() bfin_read32(DMA2_3_NEXT_DESC_PTR)
1116#define bfin_write_DMA2_3_NEXT_DESC_PTR(val) bfin_write32(DMA2_3_NEXT_DESC_PTR,val)
1117#define bfin_read_DMA2_3_START_ADDR() bfin_read32(DMA2_3_START_ADDR)
1118#define bfin_write_DMA2_3_START_ADDR(val) bfin_write32(DMA2_3_START_ADDR,val)
1119#define bfin_read_DMA2_3_X_COUNT() bfin_read16(DMA2_3_X_COUNT)
1120#define bfin_write_DMA2_3_X_COUNT(val) bfin_write16(DMA2_3_X_COUNT,val)
1121#define bfin_read_DMA2_3_Y_COUNT() bfin_read16(DMA2_3_Y_COUNT)
1122#define bfin_write_DMA2_3_Y_COUNT(val) bfin_write16(DMA2_3_Y_COUNT,val)
1123#define bfin_read_DMA2_3_X_MODIFY() bfin_read16(DMA2_3_X_MODIFY)
1124#define bfin_write_DMA2_3_X_MODIFY(val) bfin_write16(DMA2_3_X_MODIFY,val)
1125#define bfin_read_DMA2_3_Y_MODIFY() bfin_read16(DMA2_3_Y_MODIFY)
1126#define bfin_write_DMA2_3_Y_MODIFY(val) bfin_write16(DMA2_3_Y_MODIFY,val)
1127#define bfin_read_DMA2_3_CURR_DESC_PTR() bfin_read32(DMA2_3_CURR_DESC_PTR)
1128#define bfin_write_DMA2_3_CURR_DESC_PTR(val) bfin_write32(DMA2_3_CURR_DESC_PTR,val)
1129#define bfin_read_DMA2_3_CURR_ADDR() bfin_read32(DMA2_3_CURR_ADDR)
1130#define bfin_write_DMA2_3_CURR_ADDR(val) bfin_write32(DMA2_3_CURR_ADDR,val)
1131#define bfin_read_DMA2_3_CURR_X_COUNT() bfin_read16(DMA2_3_CURR_X_COUNT)
1132#define bfin_write_DMA2_3_CURR_X_COUNT(val) bfin_write16(DMA2_3_CURR_X_COUNT,val)
1133#define bfin_read_DMA2_3_CURR_Y_COUNT() bfin_read16(DMA2_3_CURR_Y_COUNT)
1134#define bfin_write_DMA2_3_CURR_Y_COUNT(val) bfin_write16(DMA2_3_CURR_Y_COUNT,val)
1135#define bfin_read_DMA2_3_IRQ_STATUS() bfin_read16(DMA2_3_IRQ_STATUS)
1136#define bfin_write_DMA2_3_IRQ_STATUS(val) bfin_write16(DMA2_3_IRQ_STATUS,val)
1137#define bfin_read_DMA2_3_PERIPHERAL_MAP() bfin_read16(DMA2_3_PERIPHERAL_MAP)
1138#define bfin_write_DMA2_3_PERIPHERAL_MAP(val) bfin_write16(DMA2_3_PERIPHERAL_MAP,val)
1139#define bfin_read_DMA2_4_CONFIG() bfin_read16(DMA2_4_CONFIG)
1140#define bfin_write_DMA2_4_CONFIG(val) bfin_write16(DMA2_4_CONFIG,val)
1141#define bfin_read_DMA2_4_NEXT_DESC_PTR() bfin_read32(DMA2_4_NEXT_DESC_PTR)
1142#define bfin_write_DMA2_4_NEXT_DESC_PTR(val) bfin_write32(DMA2_4_NEXT_DESC_PTR,val)
1143#define bfin_read_DMA2_4_START_ADDR() bfin_read32(DMA2_4_START_ADDR)
1144#define bfin_write_DMA2_4_START_ADDR(val) bfin_write32(DMA2_4_START_ADDR,val)
1145#define bfin_read_DMA2_4_X_COUNT() bfin_read16(DMA2_4_X_COUNT)
1146#define bfin_write_DMA2_4_X_COUNT(val) bfin_write16(DMA2_4_X_COUNT,val)
1147#define bfin_read_DMA2_4_Y_COUNT() bfin_read16(DMA2_4_Y_COUNT)
1148#define bfin_write_DMA2_4_Y_COUNT(val) bfin_write16(DMA2_4_Y_COUNT,val)
1149#define bfin_read_DMA2_4_X_MODIFY() bfin_read16(DMA2_4_X_MODIFY)
1150#define bfin_write_DMA2_4_X_MODIFY(val) bfin_write16(DMA2_4_X_MODIFY,val)
1151#define bfin_read_DMA2_4_Y_MODIFY() bfin_read16(DMA2_4_Y_MODIFY)
1152#define bfin_write_DMA2_4_Y_MODIFY(val) bfin_write16(DMA2_4_Y_MODIFY,val)
1153#define bfin_read_DMA2_4_CURR_DESC_PTR() bfin_read32(DMA2_4_CURR_DESC_PTR)
1154#define bfin_write_DMA2_4_CURR_DESC_PTR(val) bfin_write32(DMA2_4_CURR_DESC_PTR,val)
1155#define bfin_read_DMA2_4_CURR_ADDR() bfin_read32(DMA2_4_CURR_ADDR)
1156#define bfin_write_DMA2_4_CURR_ADDR(val) bfin_write32(DMA2_4_CURR_ADDR,val)
1157#define bfin_read_DMA2_4_CURR_X_COUNT() bfin_read16(DMA2_4_CURR_X_COUNT)
1158#define bfin_write_DMA2_4_CURR_X_COUNT(val) bfin_write16(DMA2_4_CURR_X_COUNT,val)
1159#define bfin_read_DMA2_4_CURR_Y_COUNT() bfin_read16(DMA2_4_CURR_Y_COUNT)
1160#define bfin_write_DMA2_4_CURR_Y_COUNT(val) bfin_write16(DMA2_4_CURR_Y_COUNT,val)
1161#define bfin_read_DMA2_4_IRQ_STATUS() bfin_read16(DMA2_4_IRQ_STATUS)
1162#define bfin_write_DMA2_4_IRQ_STATUS(val) bfin_write16(DMA2_4_IRQ_STATUS,val)
1163#define bfin_read_DMA2_4_PERIPHERAL_MAP() bfin_read16(DMA2_4_PERIPHERAL_MAP)
1164#define bfin_write_DMA2_4_PERIPHERAL_MAP(val) bfin_write16(DMA2_4_PERIPHERAL_MAP,val)
1165#define bfin_read_DMA2_5_CONFIG() bfin_read16(DMA2_5_CONFIG)
1166#define bfin_write_DMA2_5_CONFIG(val) bfin_write16(DMA2_5_CONFIG,val)
1167#define bfin_read_DMA2_5_NEXT_DESC_PTR() bfin_read32(DMA2_5_NEXT_DESC_PTR)
1168#define bfin_write_DMA2_5_NEXT_DESC_PTR(val) bfin_write32(DMA2_5_NEXT_DESC_PTR,val)
1169#define bfin_read_DMA2_5_START_ADDR() bfin_read32(DMA2_5_START_ADDR)
1170#define bfin_write_DMA2_5_START_ADDR(val) bfin_write32(DMA2_5_START_ADDR,val)
1171#define bfin_read_DMA2_5_X_COUNT() bfin_read16(DMA2_5_X_COUNT)
1172#define bfin_write_DMA2_5_X_COUNT(val) bfin_write16(DMA2_5_X_COUNT,val)
1173#define bfin_read_DMA2_5_Y_COUNT() bfin_read16(DMA2_5_Y_COUNT)
1174#define bfin_write_DMA2_5_Y_COUNT(val) bfin_write16(DMA2_5_Y_COUNT,val)
1175#define bfin_read_DMA2_5_X_MODIFY() bfin_read16(DMA2_5_X_MODIFY)
1176#define bfin_write_DMA2_5_X_MODIFY(val) bfin_write16(DMA2_5_X_MODIFY,val)
1177#define bfin_read_DMA2_5_Y_MODIFY() bfin_read16(DMA2_5_Y_MODIFY)
1178#define bfin_write_DMA2_5_Y_MODIFY(val) bfin_write16(DMA2_5_Y_MODIFY,val)
1179#define bfin_read_DMA2_5_CURR_DESC_PTR() bfin_read32(DMA2_5_CURR_DESC_PTR)
1180#define bfin_write_DMA2_5_CURR_DESC_PTR(val) bfin_write32(DMA2_5_CURR_DESC_PTR,val)
1181#define bfin_read_DMA2_5_CURR_ADDR() bfin_read32(DMA2_5_CURR_ADDR)
1182#define bfin_write_DMA2_5_CURR_ADDR(val) bfin_write32(DMA2_5_CURR_ADDR,val)
1183#define bfin_read_DMA2_5_CURR_X_COUNT() bfin_read16(DMA2_5_CURR_X_COUNT)
1184#define bfin_write_DMA2_5_CURR_X_COUNT(val) bfin_write16(DMA2_5_CURR_X_COUNT,val)
1185#define bfin_read_DMA2_5_CURR_Y_COUNT() bfin_read16(DMA2_5_CURR_Y_COUNT)
1186#define bfin_write_DMA2_5_CURR_Y_COUNT(val) bfin_write16(DMA2_5_CURR_Y_COUNT,val)
1187#define bfin_read_DMA2_5_IRQ_STATUS() bfin_read16(DMA2_5_IRQ_STATUS)
1188#define bfin_write_DMA2_5_IRQ_STATUS(val) bfin_write16(DMA2_5_IRQ_STATUS,val)
1189#define bfin_read_DMA2_5_PERIPHERAL_MAP() bfin_read16(DMA2_5_PERIPHERAL_MAP)
1190#define bfin_write_DMA2_5_PERIPHERAL_MAP(val) bfin_write16(DMA2_5_PERIPHERAL_MAP,val)
1191#define bfin_read_DMA2_6_CONFIG() bfin_read16(DMA2_6_CONFIG)
1192#define bfin_write_DMA2_6_CONFIG(val) bfin_write16(DMA2_6_CONFIG,val)
1193#define bfin_read_DMA2_6_NEXT_DESC_PTR() bfin_read32(DMA2_6_NEXT_DESC_PTR)
1194#define bfin_write_DMA2_6_NEXT_DESC_PTR(val) bfin_write32(DMA2_6_NEXT_DESC_PTR,val)
1195#define bfin_read_DMA2_6_START_ADDR() bfin_read32(DMA2_6_START_ADDR)
1196#define bfin_write_DMA2_6_START_ADDR(val) bfin_write32(DMA2_6_START_ADDR,val)
1197#define bfin_read_DMA2_6_X_COUNT() bfin_read16(DMA2_6_X_COUNT)
1198#define bfin_write_DMA2_6_X_COUNT(val) bfin_write16(DMA2_6_X_COUNT,val)
1199#define bfin_read_DMA2_6_Y_COUNT() bfin_read16(DMA2_6_Y_COUNT)
1200#define bfin_write_DMA2_6_Y_COUNT(val) bfin_write16(DMA2_6_Y_COUNT,val)
1201#define bfin_read_DMA2_6_X_MODIFY() bfin_read16(DMA2_6_X_MODIFY)
1202#define bfin_write_DMA2_6_X_MODIFY(val) bfin_write16(DMA2_6_X_MODIFY,val)
1203#define bfin_read_DMA2_6_Y_MODIFY() bfin_read16(DMA2_6_Y_MODIFY)
1204#define bfin_write_DMA2_6_Y_MODIFY(val) bfin_write16(DMA2_6_Y_MODIFY,val)
1205#define bfin_read_DMA2_6_CURR_DESC_PTR() bfin_read32(DMA2_6_CURR_DESC_PTR)
1206#define bfin_write_DMA2_6_CURR_DESC_PTR(val) bfin_write32(DMA2_6_CURR_DESC_PTR,val)
1207#define bfin_read_DMA2_6_CURR_ADDR() bfin_read32(DMA2_6_CURR_ADDR)
1208#define bfin_write_DMA2_6_CURR_ADDR(val) bfin_write32(DMA2_6_CURR_ADDR,val)
1209#define bfin_read_DMA2_6_CURR_X_COUNT() bfin_read16(DMA2_6_CURR_X_COUNT)
1210#define bfin_write_DMA2_6_CURR_X_COUNT(val) bfin_write16(DMA2_6_CURR_X_COUNT,val)
1211#define bfin_read_DMA2_6_CURR_Y_COUNT() bfin_read16(DMA2_6_CURR_Y_COUNT)
1212#define bfin_write_DMA2_6_CURR_Y_COUNT(val) bfin_write16(DMA2_6_CURR_Y_COUNT,val)
1213#define bfin_read_DMA2_6_IRQ_STATUS() bfin_read16(DMA2_6_IRQ_STATUS)
1214#define bfin_write_DMA2_6_IRQ_STATUS(val) bfin_write16(DMA2_6_IRQ_STATUS,val)
1215#define bfin_read_DMA2_6_PERIPHERAL_MAP() bfin_read16(DMA2_6_PERIPHERAL_MAP)
1216#define bfin_write_DMA2_6_PERIPHERAL_MAP(val) bfin_write16(DMA2_6_PERIPHERAL_MAP,val)
1217#define bfin_read_DMA2_7_CONFIG() bfin_read16(DMA2_7_CONFIG)
1218#define bfin_write_DMA2_7_CONFIG(val) bfin_write16(DMA2_7_CONFIG,val)
1219#define bfin_read_DMA2_7_NEXT_DESC_PTR() bfin_read32(DMA2_7_NEXT_DESC_PTR)
1220#define bfin_write_DMA2_7_NEXT_DESC_PTR(val) bfin_write32(DMA2_7_NEXT_DESC_PTR,val)
1221#define bfin_read_DMA2_7_START_ADDR() bfin_read32(DMA2_7_START_ADDR)
1222#define bfin_write_DMA2_7_START_ADDR(val) bfin_write32(DMA2_7_START_ADDR,val)
1223#define bfin_read_DMA2_7_X_COUNT() bfin_read16(DMA2_7_X_COUNT)
1224#define bfin_write_DMA2_7_X_COUNT(val) bfin_write16(DMA2_7_X_COUNT,val)
1225#define bfin_read_DMA2_7_Y_COUNT() bfin_read16(DMA2_7_Y_COUNT)
1226#define bfin_write_DMA2_7_Y_COUNT(val) bfin_write16(DMA2_7_Y_COUNT,val)
1227#define bfin_read_DMA2_7_X_MODIFY() bfin_read16(DMA2_7_X_MODIFY)
1228#define bfin_write_DMA2_7_X_MODIFY(val) bfin_write16(DMA2_7_X_MODIFY,val)
1229#define bfin_read_DMA2_7_Y_MODIFY() bfin_read16(DMA2_7_Y_MODIFY)
1230#define bfin_write_DMA2_7_Y_MODIFY(val) bfin_write16(DMA2_7_Y_MODIFY,val)
1231#define bfin_read_DMA2_7_CURR_DESC_PTR() bfin_read32(DMA2_7_CURR_DESC_PTR)
1232#define bfin_write_DMA2_7_CURR_DESC_PTR(val) bfin_write32(DMA2_7_CURR_DESC_PTR,val)
1233#define bfin_read_DMA2_7_CURR_ADDR() bfin_read32(DMA2_7_CURR_ADDR)
1234#define bfin_write_DMA2_7_CURR_ADDR(val) bfin_write32(DMA2_7_CURR_ADDR,val)
1235#define bfin_read_DMA2_7_CURR_X_COUNT() bfin_read16(DMA2_7_CURR_X_COUNT)
1236#define bfin_write_DMA2_7_CURR_X_COUNT(val) bfin_write16(DMA2_7_CURR_X_COUNT,val)
1237#define bfin_read_DMA2_7_CURR_Y_COUNT() bfin_read16(DMA2_7_CURR_Y_COUNT)
1238#define bfin_write_DMA2_7_CURR_Y_COUNT(val) bfin_write16(DMA2_7_CURR_Y_COUNT,val)
1239#define bfin_read_DMA2_7_IRQ_STATUS() bfin_read16(DMA2_7_IRQ_STATUS)
1240#define bfin_write_DMA2_7_IRQ_STATUS(val) bfin_write16(DMA2_7_IRQ_STATUS,val)
1241#define bfin_read_DMA2_7_PERIPHERAL_MAP() bfin_read16(DMA2_7_PERIPHERAL_MAP)
1242#define bfin_write_DMA2_7_PERIPHERAL_MAP(val) bfin_write16(DMA2_7_PERIPHERAL_MAP,val)
1243#define bfin_read_DMA2_8_CONFIG() bfin_read16(DMA2_8_CONFIG)
1244#define bfin_write_DMA2_8_CONFIG(val) bfin_write16(DMA2_8_CONFIG,val)
1245#define bfin_read_DMA2_8_NEXT_DESC_PTR() bfin_read32(DMA2_8_NEXT_DESC_PTR)
1246#define bfin_write_DMA2_8_NEXT_DESC_PTR(val) bfin_write32(DMA2_8_NEXT_DESC_PTR,val)
1247#define bfin_read_DMA2_8_START_ADDR() bfin_read32(DMA2_8_START_ADDR)
1248#define bfin_write_DMA2_8_START_ADDR(val) bfin_write32(DMA2_8_START_ADDR,val)
1249#define bfin_read_DMA2_8_X_COUNT() bfin_read16(DMA2_8_X_COUNT)
1250#define bfin_write_DMA2_8_X_COUNT(val) bfin_write16(DMA2_8_X_COUNT,val)
1251#define bfin_read_DMA2_8_Y_COUNT() bfin_read16(DMA2_8_Y_COUNT)
1252#define bfin_write_DMA2_8_Y_COUNT(val) bfin_write16(DMA2_8_Y_COUNT,val)
1253#define bfin_read_DMA2_8_X_MODIFY() bfin_read16(DMA2_8_X_MODIFY)
1254#define bfin_write_DMA2_8_X_MODIFY(val) bfin_write16(DMA2_8_X_MODIFY,val)
1255#define bfin_read_DMA2_8_Y_MODIFY() bfin_read16(DMA2_8_Y_MODIFY)
1256#define bfin_write_DMA2_8_Y_MODIFY(val) bfin_write16(DMA2_8_Y_MODIFY,val)
1257#define bfin_read_DMA2_8_CURR_DESC_PTR() bfin_read32(DMA2_8_CURR_DESC_PTR)
1258#define bfin_write_DMA2_8_CURR_DESC_PTR(val) bfin_write32(DMA2_8_CURR_DESC_PTR,val)
1259#define bfin_read_DMA2_8_CURR_ADDR() bfin_read32(DMA2_8_CURR_ADDR)
1260#define bfin_write_DMA2_8_CURR_ADDR(val) bfin_write32(DMA2_8_CURR_ADDR,val)
1261#define bfin_read_DMA2_8_CURR_X_COUNT() bfin_read16(DMA2_8_CURR_X_COUNT)
1262#define bfin_write_DMA2_8_CURR_X_COUNT(val) bfin_write16(DMA2_8_CURR_X_COUNT,val)
1263#define bfin_read_DMA2_8_CURR_Y_COUNT() bfin_read16(DMA2_8_CURR_Y_COUNT)
1264#define bfin_write_DMA2_8_CURR_Y_COUNT(val) bfin_write16(DMA2_8_CURR_Y_COUNT,val)
1265#define bfin_read_DMA2_8_IRQ_STATUS() bfin_read16(DMA2_8_IRQ_STATUS)
1266#define bfin_write_DMA2_8_IRQ_STATUS(val) bfin_write16(DMA2_8_IRQ_STATUS,val)
1267#define bfin_read_DMA2_8_PERIPHERAL_MAP() bfin_read16(DMA2_8_PERIPHERAL_MAP)
1268#define bfin_write_DMA2_8_PERIPHERAL_MAP(val) bfin_write16(DMA2_8_PERIPHERAL_MAP,val)
1269#define bfin_read_DMA2_9_CONFIG() bfin_read16(DMA2_9_CONFIG)
1270#define bfin_write_DMA2_9_CONFIG(val) bfin_write16(DMA2_9_CONFIG,val)
1271#define bfin_read_DMA2_9_NEXT_DESC_PTR() bfin_read32(DMA2_9_NEXT_DESC_PTR)
1272#define bfin_write_DMA2_9_NEXT_DESC_PTR(val) bfin_write32(DMA2_9_NEXT_DESC_PTR,val)
1273#define bfin_read_DMA2_9_START_ADDR() bfin_read32(DMA2_9_START_ADDR)
1274#define bfin_write_DMA2_9_START_ADDR(val) bfin_write32(DMA2_9_START_ADDR,val)
1275#define bfin_read_DMA2_9_X_COUNT() bfin_read16(DMA2_9_X_COUNT)
1276#define bfin_write_DMA2_9_X_COUNT(val) bfin_write16(DMA2_9_X_COUNT,val)
1277#define bfin_read_DMA2_9_Y_COUNT() bfin_read16(DMA2_9_Y_COUNT)
1278#define bfin_write_DMA2_9_Y_COUNT(val) bfin_write16(DMA2_9_Y_COUNT,val)
1279#define bfin_read_DMA2_9_X_MODIFY() bfin_read16(DMA2_9_X_MODIFY)
1280#define bfin_write_DMA2_9_X_MODIFY(val) bfin_write16(DMA2_9_X_MODIFY,val)
1281#define bfin_read_DMA2_9_Y_MODIFY() bfin_read16(DMA2_9_Y_MODIFY)
1282#define bfin_write_DMA2_9_Y_MODIFY(val) bfin_write16(DMA2_9_Y_MODIFY,val)
1283#define bfin_read_DMA2_9_CURR_DESC_PTR() bfin_read32(DMA2_9_CURR_DESC_PTR)
1284#define bfin_write_DMA2_9_CURR_DESC_PTR(val) bfin_write32(DMA2_9_CURR_DESC_PTR,val)
1285#define bfin_read_DMA2_9_CURR_ADDR() bfin_read32(DMA2_9_CURR_ADDR)
1286#define bfin_write_DMA2_9_CURR_ADDR(val) bfin_write32(DMA2_9_CURR_ADDR,val)
1287#define bfin_read_DMA2_9_CURR_X_COUNT() bfin_read16(DMA2_9_CURR_X_COUNT)
1288#define bfin_write_DMA2_9_CURR_X_COUNT(val) bfin_write16(DMA2_9_CURR_X_COUNT,val)
1289#define bfin_read_DMA2_9_CURR_Y_COUNT() bfin_read16(DMA2_9_CURR_Y_COUNT)
1290#define bfin_write_DMA2_9_CURR_Y_COUNT(val) bfin_write16(DMA2_9_CURR_Y_COUNT,val)
1291#define bfin_read_DMA2_9_IRQ_STATUS() bfin_read16(DMA2_9_IRQ_STATUS)
1292#define bfin_write_DMA2_9_IRQ_STATUS(val) bfin_write16(DMA2_9_IRQ_STATUS,val)
1293#define bfin_read_DMA2_9_PERIPHERAL_MAP() bfin_read16(DMA2_9_PERIPHERAL_MAP)
1294#define bfin_write_DMA2_9_PERIPHERAL_MAP(val) bfin_write16(DMA2_9_PERIPHERAL_MAP,val)
1295#define bfin_read_DMA2_10_CONFIG() bfin_read16(DMA2_10_CONFIG)
1296#define bfin_write_DMA2_10_CONFIG(val) bfin_write16(DMA2_10_CONFIG,val)
1297#define bfin_read_DMA2_10_NEXT_DESC_PTR() bfin_read32(DMA2_10_NEXT_DESC_PTR)
1298#define bfin_write_DMA2_10_NEXT_DESC_PTR(val) bfin_write32(DMA2_10_NEXT_DESC_PTR,val)
1299#define bfin_read_DMA2_10_START_ADDR() bfin_read32(DMA2_10_START_ADDR)
1300#define bfin_write_DMA2_10_START_ADDR(val) bfin_write32(DMA2_10_START_ADDR,val)
1301#define bfin_read_DMA2_10_X_COUNT() bfin_read16(DMA2_10_X_COUNT)
1302#define bfin_write_DMA2_10_X_COUNT(val) bfin_write16(DMA2_10_X_COUNT,val)
1303#define bfin_read_DMA2_10_Y_COUNT() bfin_read16(DMA2_10_Y_COUNT)
1304#define bfin_write_DMA2_10_Y_COUNT(val) bfin_write16(DMA2_10_Y_COUNT,val)
1305#define bfin_read_DMA2_10_X_MODIFY() bfin_read16(DMA2_10_X_MODIFY)
1306#define bfin_write_DMA2_10_X_MODIFY(val) bfin_write16(DMA2_10_X_MODIFY,val)
1307#define bfin_read_DMA2_10_Y_MODIFY() bfin_read16(DMA2_10_Y_MODIFY)
1308#define bfin_write_DMA2_10_Y_MODIFY(val) bfin_write16(DMA2_10_Y_MODIFY,val)
1309#define bfin_read_DMA2_10_CURR_DESC_PTR() bfin_read32(DMA2_10_CURR_DESC_PTR)
1310#define bfin_write_DMA2_10_CURR_DESC_PTR(val) bfin_write32(DMA2_10_CURR_DESC_PTR,val)
1311#define bfin_read_DMA2_10_CURR_ADDR() bfin_read32(DMA2_10_CURR_ADDR)
1312#define bfin_write_DMA2_10_CURR_ADDR(val) bfin_write32(DMA2_10_CURR_ADDR,val)
1313#define bfin_read_DMA2_10_CURR_X_COUNT() bfin_read16(DMA2_10_CURR_X_COUNT)
1314#define bfin_write_DMA2_10_CURR_X_COUNT(val) bfin_write16(DMA2_10_CURR_X_COUNT,val)
1315#define bfin_read_DMA2_10_CURR_Y_COUNT() bfin_read16(DMA2_10_CURR_Y_COUNT)
1316#define bfin_write_DMA2_10_CURR_Y_COUNT(val) bfin_write16(DMA2_10_CURR_Y_COUNT,val)
1317#define bfin_read_DMA2_10_IRQ_STATUS() bfin_read16(DMA2_10_IRQ_STATUS)
1318#define bfin_write_DMA2_10_IRQ_STATUS(val) bfin_write16(DMA2_10_IRQ_STATUS,val)
1319#define bfin_read_DMA2_10_PERIPHERAL_MAP() bfin_read16(DMA2_10_PERIPHERAL_MAP)
1320#define bfin_write_DMA2_10_PERIPHERAL_MAP(val) bfin_write16(DMA2_10_PERIPHERAL_MAP,val)
1321#define bfin_read_DMA2_11_CONFIG() bfin_read16(DMA2_11_CONFIG)
1322#define bfin_write_DMA2_11_CONFIG(val) bfin_write16(DMA2_11_CONFIG,val)
1323#define bfin_read_DMA2_11_NEXT_DESC_PTR() bfin_read32(DMA2_11_NEXT_DESC_PTR)
1324#define bfin_write_DMA2_11_NEXT_DESC_PTR(val) bfin_write32(DMA2_11_NEXT_DESC_PTR,val)
1325#define bfin_read_DMA2_11_START_ADDR() bfin_read32(DMA2_11_START_ADDR)
1326#define bfin_write_DMA2_11_START_ADDR(val) bfin_write32(DMA2_11_START_ADDR,val)
1327#define bfin_read_DMA2_11_X_COUNT() bfin_read16(DMA2_11_X_COUNT)
1328#define bfin_write_DMA2_11_X_COUNT(val) bfin_write16(DMA2_11_X_COUNT,val)
1329#define bfin_read_DMA2_11_Y_COUNT() bfin_read16(DMA2_11_Y_COUNT)
1330#define bfin_write_DMA2_11_Y_COUNT(val) bfin_write16(DMA2_11_Y_COUNT,val)
1331#define bfin_read_DMA2_11_X_MODIFY() bfin_read16(DMA2_11_X_MODIFY)
1332#define bfin_write_DMA2_11_X_MODIFY(val) bfin_write16(DMA2_11_X_MODIFY,val)
1333#define bfin_read_DMA2_11_Y_MODIFY() bfin_read16(DMA2_11_Y_MODIFY)
1334#define bfin_write_DMA2_11_Y_MODIFY(val) bfin_write16(DMA2_11_Y_MODIFY,val)
1335#define bfin_read_DMA2_11_CURR_DESC_PTR() bfin_read32(DMA2_11_CURR_DESC_PTR)
1336#define bfin_write_DMA2_11_CURR_DESC_PTR(val) bfin_write32(DMA2_11_CURR_DESC_PTR,val)
1337#define bfin_read_DMA2_11_CURR_ADDR() bfin_read32(DMA2_11_CURR_ADDR)
1338#define bfin_write_DMA2_11_CURR_ADDR(val) bfin_write32(DMA2_11_CURR_ADDR,val)
1339#define bfin_read_DMA2_11_CURR_X_COUNT() bfin_read16(DMA2_11_CURR_X_COUNT)
1340#define bfin_write_DMA2_11_CURR_X_COUNT(val) bfin_write16(DMA2_11_CURR_X_COUNT,val)
1341#define bfin_read_DMA2_11_CURR_Y_COUNT() bfin_read16(DMA2_11_CURR_Y_COUNT)
1342#define bfin_write_DMA2_11_CURR_Y_COUNT(val) bfin_write16(DMA2_11_CURR_Y_COUNT,val)
1343#define bfin_read_DMA2_11_IRQ_STATUS() bfin_read16(DMA2_11_IRQ_STATUS)
1344#define bfin_write_DMA2_11_IRQ_STATUS(val) bfin_write16(DMA2_11_IRQ_STATUS,val)
1345#define bfin_read_DMA2_11_PERIPHERAL_MAP() bfin_read16(DMA2_11_PERIPHERAL_MAP)
1346#define bfin_write_DMA2_11_PERIPHERAL_MAP(val) bfin_write16(DMA2_11_PERIPHERAL_MAP,val)
1347/* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */
1348#define bfin_read_MDMA2_D0_CONFIG() bfin_read16(MDMA2_D0_CONFIG)
1349#define bfin_write_MDMA2_D0_CONFIG(val) bfin_write16(MDMA2_D0_CONFIG,val)
1350#define bfin_read_MDMA2_D0_NEXT_DESC_PTR() bfin_read32(MDMA2_D0_NEXT_DESC_PTR)
1351#define bfin_write_MDMA2_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA2_D0_NEXT_DESC_PTR,val)
1352#define bfin_read_MDMA2_D0_START_ADDR() bfin_read32(MDMA2_D0_START_ADDR)
1353#define bfin_write_MDMA2_D0_START_ADDR(val) bfin_write32(MDMA2_D0_START_ADDR,val)
1354#define bfin_read_MDMA2_D0_X_COUNT() bfin_read16(MDMA2_D0_X_COUNT)
1355#define bfin_write_MDMA2_D0_X_COUNT(val) bfin_write16(MDMA2_D0_X_COUNT,val)
1356#define bfin_read_MDMA2_D0_Y_COUNT() bfin_read16(MDMA2_D0_Y_COUNT)
1357#define bfin_write_MDMA2_D0_Y_COUNT(val) bfin_write16(MDMA2_D0_Y_COUNT,val)
1358#define bfin_read_MDMA2_D0_X_MODIFY() bfin_read16(MDMA2_D0_X_MODIFY)
1359#define bfin_write_MDMA2_D0_X_MODIFY(val) bfin_write16(MDMA2_D0_X_MODIFY,val)
1360#define bfin_read_MDMA2_D0_Y_MODIFY() bfin_read16(MDMA2_D0_Y_MODIFY)
1361#define bfin_write_MDMA2_D0_Y_MODIFY(val) bfin_write16(MDMA2_D0_Y_MODIFY,val)
1362#define bfin_read_MDMA2_D0_CURR_DESC_PTR() bfin_read32(MDMA2_D0_CURR_DESC_PTR)
1363#define bfin_write_MDMA2_D0_CURR_DESC_PTR(val) bfin_write32(MDMA2_D0_CURR_DESC_PTR,val)
1364#define bfin_read_MDMA2_D0_CURR_ADDR() bfin_read32(MDMA2_D0_CURR_ADDR)
1365#define bfin_write_MDMA2_D0_CURR_ADDR(val) bfin_write32(MDMA2_D0_CURR_ADDR,val)
1366#define bfin_read_MDMA2_D0_CURR_X_COUNT() bfin_read16(MDMA2_D0_CURR_X_COUNT)
1367#define bfin_write_MDMA2_D0_CURR_X_COUNT(val) bfin_write16(MDMA2_D0_CURR_X_COUNT,val)
1368#define bfin_read_MDMA2_D0_CURR_Y_COUNT() bfin_read16(MDMA2_D0_CURR_Y_COUNT)
1369#define bfin_write_MDMA2_D0_CURR_Y_COUNT(val) bfin_write16(MDMA2_D0_CURR_Y_COUNT,val)
1370#define bfin_read_MDMA2_D0_IRQ_STATUS() bfin_read16(MDMA2_D0_IRQ_STATUS)
1371#define bfin_write_MDMA2_D0_IRQ_STATUS(val) bfin_write16(MDMA2_D0_IRQ_STATUS,val)
1372#define bfin_read_MDMA2_D0_PERIPHERAL_MAP() bfin_read16(MDMA2_D0_PERIPHERAL_MAP)
1373#define bfin_write_MDMA2_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA2_D0_PERIPHERAL_MAP,val)
1374#define bfin_read_MDMA2_S0_CONFIG() bfin_read16(MDMA2_S0_CONFIG)
1375#define bfin_write_MDMA2_S0_CONFIG(val) bfin_write16(MDMA2_S0_CONFIG,val)
1376#define bfin_read_MDMA2_S0_NEXT_DESC_PTR() bfin_read32(MDMA2_S0_NEXT_DESC_PTR)
1377#define bfin_write_MDMA2_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA2_S0_NEXT_DESC_PTR,val)
1378#define bfin_read_MDMA2_S0_START_ADDR() bfin_read32(MDMA2_S0_START_ADDR)
1379#define bfin_write_MDMA2_S0_START_ADDR(val) bfin_write32(MDMA2_S0_START_ADDR,val)
1380#define bfin_read_MDMA2_S0_X_COUNT() bfin_read16(MDMA2_S0_X_COUNT)
1381#define bfin_write_MDMA2_S0_X_COUNT(val) bfin_write16(MDMA2_S0_X_COUNT,val)
1382#define bfin_read_MDMA2_S0_Y_COUNT() bfin_read16(MDMA2_S0_Y_COUNT)
1383#define bfin_write_MDMA2_S0_Y_COUNT(val) bfin_write16(MDMA2_S0_Y_COUNT,val)
1384#define bfin_read_MDMA2_S0_X_MODIFY() bfin_read16(MDMA2_S0_X_MODIFY)
1385#define bfin_write_MDMA2_S0_X_MODIFY(val) bfin_write16(MDMA2_S0_X_MODIFY,val)
1386#define bfin_read_MDMA2_S0_Y_MODIFY() bfin_read16(MDMA2_S0_Y_MODIFY)
1387#define bfin_write_MDMA2_S0_Y_MODIFY(val) bfin_write16(MDMA2_S0_Y_MODIFY,val)
1388#define bfin_read_MDMA2_S0_CURR_DESC_PTR() bfin_read32(MDMA2_S0_CURR_DESC_PTR)
1389#define bfin_write_MDMA2_S0_CURR_DESC_PTR(val) bfin_write32(MDMA2_S0_CURR_DESC_PTR,val)
1390#define bfin_read_MDMA2_S0_CURR_ADDR() bfin_read32(MDMA2_S0_CURR_ADDR)
1391#define bfin_write_MDMA2_S0_CURR_ADDR(val) bfin_write32(MDMA2_S0_CURR_ADDR,val)
1392#define bfin_read_MDMA2_S0_CURR_X_COUNT() bfin_read16(MDMA2_S0_CURR_X_COUNT)
1393#define bfin_write_MDMA2_S0_CURR_X_COUNT(val) bfin_write16(MDMA2_S0_CURR_X_COUNT,val)
1394#define bfin_read_MDMA2_S0_CURR_Y_COUNT() bfin_read16(MDMA2_S0_CURR_Y_COUNT)
1395#define bfin_write_MDMA2_S0_CURR_Y_COUNT(val) bfin_write16(MDMA2_S0_CURR_Y_COUNT,val)
1396#define bfin_read_MDMA2_S0_IRQ_STATUS() bfin_read16(MDMA2_S0_IRQ_STATUS)
1397#define bfin_write_MDMA2_S0_IRQ_STATUS(val) bfin_write16(MDMA2_S0_IRQ_STATUS,val)
1398#define bfin_read_MDMA2_S0_PERIPHERAL_MAP() bfin_read16(MDMA2_S0_PERIPHERAL_MAP)
1399#define bfin_write_MDMA2_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA2_S0_PERIPHERAL_MAP,val)
1400#define bfin_read_MDMA2_D1_CONFIG() bfin_read16(MDMA2_D1_CONFIG)
1401#define bfin_write_MDMA2_D1_CONFIG(val) bfin_write16(MDMA2_D1_CONFIG,val)
1402#define bfin_read_MDMA2_D1_NEXT_DESC_PTR() bfin_read32(MDMA2_D1_NEXT_DESC_PTR)
1403#define bfin_write_MDMA2_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA2_D1_NEXT_DESC_PTR,val)
1404#define bfin_read_MDMA2_D1_START_ADDR() bfin_read32(MDMA2_D1_START_ADDR)
1405#define bfin_write_MDMA2_D1_START_ADDR(val) bfin_write32(MDMA2_D1_START_ADDR,val)
1406#define bfin_read_MDMA2_D1_X_COUNT() bfin_read16(MDMA2_D1_X_COUNT)
1407#define bfin_write_MDMA2_D1_X_COUNT(val) bfin_write16(MDMA2_D1_X_COUNT,val)
1408#define bfin_read_MDMA2_D1_Y_COUNT() bfin_read16(MDMA2_D1_Y_COUNT)
1409#define bfin_write_MDMA2_D1_Y_COUNT(val) bfin_write16(MDMA2_D1_Y_COUNT,val)
1410#define bfin_read_MDMA2_D1_X_MODIFY() bfin_read16(MDMA2_D1_X_MODIFY)
1411#define bfin_write_MDMA2_D1_X_MODIFY(val) bfin_write16(MDMA2_D1_X_MODIFY,val)
1412#define bfin_read_MDMA2_D1_Y_MODIFY() bfin_read16(MDMA2_D1_Y_MODIFY)
1413#define bfin_write_MDMA2_D1_Y_MODIFY(val) bfin_write16(MDMA2_D1_Y_MODIFY,val)
1414#define bfin_read_MDMA2_D1_CURR_DESC_PTR() bfin_read32(MDMA2_D1_CURR_DESC_PTR)
1415#define bfin_write_MDMA2_D1_CURR_DESC_PTR(val) bfin_write32(MDMA2_D1_CURR_DESC_PTR,val)
1416#define bfin_read_MDMA2_D1_CURR_ADDR() bfin_read32(MDMA2_D1_CURR_ADDR)
1417#define bfin_write_MDMA2_D1_CURR_ADDR(val) bfin_write32(MDMA2_D1_CURR_ADDR,val)
1418#define bfin_read_MDMA2_D1_CURR_X_COUNT() bfin_read16(MDMA2_D1_CURR_X_COUNT)
1419#define bfin_write_MDMA2_D1_CURR_X_COUNT(val) bfin_write16(MDMA2_D1_CURR_X_COUNT,val)
1420#define bfin_read_MDMA2_D1_CURR_Y_COUNT() bfin_read16(MDMA2_D1_CURR_Y_COUNT)
1421#define bfin_write_MDMA2_D1_CURR_Y_COUNT(val) bfin_write16(MDMA2_D1_CURR_Y_COUNT,val)
1422#define bfin_read_MDMA2_D1_IRQ_STATUS() bfin_read16(MDMA2_D1_IRQ_STATUS)
1423#define bfin_write_MDMA2_D1_IRQ_STATUS(val) bfin_write16(MDMA2_D1_IRQ_STATUS,val)
1424#define bfin_read_MDMA2_D1_PERIPHERAL_MAP() bfin_read16(MDMA2_D1_PERIPHERAL_MAP)
1425#define bfin_write_MDMA2_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA2_D1_PERIPHERAL_MAP,val)
1426#define bfin_read_MDMA2_S1_CONFIG() bfin_read16(MDMA2_S1_CONFIG)
1427#define bfin_write_MDMA2_S1_CONFIG(val) bfin_write16(MDMA2_S1_CONFIG,val)
1428#define bfin_read_MDMA2_S1_NEXT_DESC_PTR() bfin_read32(MDMA2_S1_NEXT_DESC_PTR)
1429#define bfin_write_MDMA2_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA2_S1_NEXT_DESC_PTR,val)
1430#define bfin_read_MDMA2_S1_START_ADDR() bfin_read32(MDMA2_S1_START_ADDR)
1431#define bfin_write_MDMA2_S1_START_ADDR(val) bfin_write32(MDMA2_S1_START_ADDR,val)
1432#define bfin_read_MDMA2_S1_X_COUNT() bfin_read16(MDMA2_S1_X_COUNT)
1433#define bfin_write_MDMA2_S1_X_COUNT(val) bfin_write16(MDMA2_S1_X_COUNT,val)
1434#define bfin_read_MDMA2_S1_Y_COUNT() bfin_read16(MDMA2_S1_Y_COUNT)
1435#define bfin_write_MDMA2_S1_Y_COUNT(val) bfin_write16(MDMA2_S1_Y_COUNT,val)
1436#define bfin_read_MDMA2_S1_X_MODIFY() bfin_read16(MDMA2_S1_X_MODIFY)
1437#define bfin_write_MDMA2_S1_X_MODIFY(val) bfin_write16(MDMA2_S1_X_MODIFY,val)
1438#define bfin_read_MDMA2_S1_Y_MODIFY() bfin_read16(MDMA2_S1_Y_MODIFY)
1439#define bfin_write_MDMA2_S1_Y_MODIFY(val) bfin_write16(MDMA2_S1_Y_MODIFY,val)
1440#define bfin_read_MDMA2_S1_CURR_DESC_PTR() bfin_read32(MDMA2_S1_CURR_DESC_PTR)
1441#define bfin_write_MDMA2_S1_CURR_DESC_PTR(val) bfin_write32(MDMA2_S1_CURR_DESC_PTR,val)
1442#define bfin_read_MDMA2_S1_CURR_ADDR() bfin_read32(MDMA2_S1_CURR_ADDR)
1443#define bfin_write_MDMA2_S1_CURR_ADDR(val) bfin_write32(MDMA2_S1_CURR_ADDR,val)
1444#define bfin_read_MDMA2_S1_CURR_X_COUNT() bfin_read16(MDMA2_S1_CURR_X_COUNT)
1445#define bfin_write_MDMA2_S1_CURR_X_COUNT(val) bfin_write16(MDMA2_S1_CURR_X_COUNT,val)
1446#define bfin_read_MDMA2_S1_CURR_Y_COUNT() bfin_read16(MDMA2_S1_CURR_Y_COUNT)
1447#define bfin_write_MDMA2_S1_CURR_Y_COUNT(val) bfin_write16(MDMA2_S1_CURR_Y_COUNT,val)
1448#define bfin_read_MDMA2_S1_IRQ_STATUS() bfin_read16(MDMA2_S1_IRQ_STATUS)
1449#define bfin_write_MDMA2_S1_IRQ_STATUS(val) bfin_write16(MDMA2_S1_IRQ_STATUS,val)
1450#define bfin_read_MDMA2_S1_PERIPHERAL_MAP() bfin_read16(MDMA2_S1_PERIPHERAL_MAP)
1451#define bfin_write_MDMA2_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA2_S1_PERIPHERAL_MAP,val)
1452/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */
1453#define bfin_read_IMDMA_D0_CONFIG() bfin_read16(IMDMA_D0_CONFIG)
1454#define bfin_write_IMDMA_D0_CONFIG(val) bfin_write16(IMDMA_D0_CONFIG,val)
1455#define bfin_read_IMDMA_D0_NEXT_DESC_PTR() bfin_read32(IMDMA_D0_NEXT_DESC_PTR)
1456#define bfin_write_IMDMA_D0_NEXT_DESC_PTR(val) bfin_write32(IMDMA_D0_NEXT_DESC_PTR,val)
1457#define bfin_read_IMDMA_D0_START_ADDR() bfin_read32(IMDMA_D0_START_ADDR)
1458#define bfin_write_IMDMA_D0_START_ADDR(val) bfin_write32(IMDMA_D0_START_ADDR,val)
1459#define bfin_read_IMDMA_D0_X_COUNT() bfin_read16(IMDMA_D0_X_COUNT)
1460#define bfin_write_IMDMA_D0_X_COUNT(val) bfin_write16(IMDMA_D0_X_COUNT,val)
1461#define bfin_read_IMDMA_D0_Y_COUNT() bfin_read16(IMDMA_D0_Y_COUNT)
1462#define bfin_write_IMDMA_D0_Y_COUNT(val) bfin_write16(IMDMA_D0_Y_COUNT,val)
1463#define bfin_read_IMDMA_D0_X_MODIFY() bfin_read16(IMDMA_D0_X_MODIFY)
1464#define bfin_write_IMDMA_D0_X_MODIFY(val) bfin_write16(IMDMA_D0_X_MODIFY,val)
1465#define bfin_read_IMDMA_D0_Y_MODIFY() bfin_read16(IMDMA_D0_Y_MODIFY)
1466#define bfin_write_IMDMA_D0_Y_MODIFY(val) bfin_write16(IMDMA_D0_Y_MODIFY,val)
1467#define bfin_read_IMDMA_D0_CURR_DESC_PTR() bfin_read32(IMDMA_D0_CURR_DESC_PTR)
1468#define bfin_write_IMDMA_D0_CURR_DESC_PTR(val) bfin_write32(IMDMA_D0_CURR_DESC_PTR,val)
1469#define bfin_read_IMDMA_D0_CURR_ADDR() bfin_read32(IMDMA_D0_CURR_ADDR)
1470#define bfin_write_IMDMA_D0_CURR_ADDR(val) bfin_write32(IMDMA_D0_CURR_ADDR,val)
1471#define bfin_read_IMDMA_D0_CURR_X_COUNT() bfin_read16(IMDMA_D0_CURR_X_COUNT)
1472#define bfin_write_IMDMA_D0_CURR_X_COUNT(val) bfin_write16(IMDMA_D0_CURR_X_COUNT,val)
1473#define bfin_read_IMDMA_D0_CURR_Y_COUNT() bfin_read16(IMDMA_D0_CURR_Y_COUNT)
1474#define bfin_write_IMDMA_D0_CURR_Y_COUNT(val) bfin_write16(IMDMA_D0_CURR_Y_COUNT,val)
1475#define bfin_read_IMDMA_D0_IRQ_STATUS() bfin_read16(IMDMA_D0_IRQ_STATUS)
1476#define bfin_write_IMDMA_D0_IRQ_STATUS(val) bfin_write16(IMDMA_D0_IRQ_STATUS,val)
1477#define bfin_read_IMDMA_S0_CONFIG() bfin_read16(IMDMA_S0_CONFIG)
1478#define bfin_write_IMDMA_S0_CONFIG(val) bfin_write16(IMDMA_S0_CONFIG,val)
1479#define bfin_read_IMDMA_S0_NEXT_DESC_PTR() bfin_read32(IMDMA_S0_NEXT_DESC_PTR)
1480#define bfin_write_IMDMA_S0_NEXT_DESC_PTR(val) bfin_write32(IMDMA_S0_NEXT_DESC_PTR,val)
1481#define bfin_read_IMDMA_S0_START_ADDR() bfin_read32(IMDMA_S0_START_ADDR)
1482#define bfin_write_IMDMA_S0_START_ADDR(val) bfin_write32(IMDMA_S0_START_ADDR,val)
1483#define bfin_read_IMDMA_S0_X_COUNT() bfin_read16(IMDMA_S0_X_COUNT)
1484#define bfin_write_IMDMA_S0_X_COUNT(val) bfin_write16(IMDMA_S0_X_COUNT,val)
1485#define bfin_read_IMDMA_S0_Y_COUNT() bfin_read16(IMDMA_S0_Y_COUNT)
1486#define bfin_write_IMDMA_S0_Y_COUNT(val) bfin_write16(IMDMA_S0_Y_COUNT,val)
1487#define bfin_read_IMDMA_S0_X_MODIFY() bfin_read16(IMDMA_S0_X_MODIFY)
1488#define bfin_write_IMDMA_S0_X_MODIFY(val) bfin_write16(IMDMA_S0_X_MODIFY,val)
1489#define bfin_read_IMDMA_S0_Y_MODIFY() bfin_read16(IMDMA_S0_Y_MODIFY)
1490#define bfin_write_IMDMA_S0_Y_MODIFY(val) bfin_write16(IMDMA_S0_Y_MODIFY,val)
1491#define bfin_read_IMDMA_S0_CURR_DESC_PTR() bfin_read32(IMDMA_S0_CURR_DESC_PTR)
1492#define bfin_write_IMDMA_S0_CURR_DESC_PTR(val) bfin_write32(IMDMA_S0_CURR_DESC_PTR,val)
1493#define bfin_read_IMDMA_S0_CURR_ADDR() bfin_read32(IMDMA_S0_CURR_ADDR)
1494#define bfin_write_IMDMA_S0_CURR_ADDR(val) bfin_write32(IMDMA_S0_CURR_ADDR,val)
1495#define bfin_read_IMDMA_S0_CURR_X_COUNT() bfin_read16(IMDMA_S0_CURR_X_COUNT)
1496#define bfin_write_IMDMA_S0_CURR_X_COUNT(val) bfin_write16(IMDMA_S0_CURR_X_COUNT,val)
1497#define bfin_read_IMDMA_S0_CURR_Y_COUNT() bfin_read16(IMDMA_S0_CURR_Y_COUNT)
1498#define bfin_write_IMDMA_S0_CURR_Y_COUNT(val) bfin_write16(IMDMA_S0_CURR_Y_COUNT,val)
1499#define bfin_read_IMDMA_S0_IRQ_STATUS() bfin_read16(IMDMA_S0_IRQ_STATUS)
1500#define bfin_write_IMDMA_S0_IRQ_STATUS(val) bfin_write16(IMDMA_S0_IRQ_STATUS,val)
1501#define bfin_read_IMDMA_D1_CONFIG() bfin_read16(IMDMA_D1_CONFIG)
1502#define bfin_write_IMDMA_D1_CONFIG(val) bfin_write16(IMDMA_D1_CONFIG,val)
1503#define bfin_read_IMDMA_D1_NEXT_DESC_PTR() bfin_read32(IMDMA_D1_NEXT_DESC_PTR)
1504#define bfin_write_IMDMA_D1_NEXT_DESC_PTR(val) bfin_write32(IMDMA_D1_NEXT_DESC_PTR,val)
1505#define bfin_read_IMDMA_D1_START_ADDR() bfin_read32(IMDMA_D1_START_ADDR)
1506#define bfin_write_IMDMA_D1_START_ADDR(val) bfin_write32(IMDMA_D1_START_ADDR,val)
1507#define bfin_read_IMDMA_D1_X_COUNT() bfin_read16(IMDMA_D1_X_COUNT)
1508#define bfin_write_IMDMA_D1_X_COUNT(val) bfin_write16(IMDMA_D1_X_COUNT,val)
1509#define bfin_read_IMDMA_D1_Y_COUNT() bfin_read16(IMDMA_D1_Y_COUNT)
1510#define bfin_write_IMDMA_D1_Y_COUNT(val) bfin_write16(IMDMA_D1_Y_COUNT,val)
1511#define bfin_read_IMDMA_D1_X_MODIFY() bfin_read16(IMDMA_D1_X_MODIFY)
1512#define bfin_write_IMDMA_D1_X_MODIFY(val) bfin_write16(IMDMA_D1_X_MODIFY,val)
1513#define bfin_read_IMDMA_D1_Y_MODIFY() bfin_read16(IMDMA_D1_Y_MODIFY)
1514#define bfin_write_IMDMA_D1_Y_MODIFY(val) bfin_write16(IMDMA_D1_Y_MODIFY,val)
1515#define bfin_read_IMDMA_D1_CURR_DESC_PTR() bfin_read32(IMDMA_D1_CURR_DESC_PTR)
1516#define bfin_write_IMDMA_D1_CURR_DESC_PTR(val) bfin_write32(IMDMA_D1_CURR_DESC_PTR,val)
1517#define bfin_read_IMDMA_D1_CURR_ADDR() bfin_read32(IMDMA_D1_CURR_ADDR)
1518#define bfin_write_IMDMA_D1_CURR_ADDR(val) bfin_write32(IMDMA_D1_CURR_ADDR,val)
1519#define bfin_read_IMDMA_D1_CURR_X_COUNT() bfin_read16(IMDMA_D1_CURR_X_COUNT)
1520#define bfin_write_IMDMA_D1_CURR_X_COUNT(val) bfin_write16(IMDMA_D1_CURR_X_COUNT,val)
1521#define bfin_read_IMDMA_D1_CURR_Y_COUNT() bfin_read16(IMDMA_D1_CURR_Y_COUNT)
1522#define bfin_write_IMDMA_D1_CURR_Y_COUNT(val) bfin_write16(IMDMA_D1_CURR_Y_COUNT,val)
1523#define bfin_read_IMDMA_D1_IRQ_STATUS() bfin_read16(IMDMA_D1_IRQ_STATUS)
1524#define bfin_write_IMDMA_D1_IRQ_STATUS(val) bfin_write16(IMDMA_D1_IRQ_STATUS,val)
1525#define bfin_read_IMDMA_S1_CONFIG() bfin_read16(IMDMA_S1_CONFIG)
1526#define bfin_write_IMDMA_S1_CONFIG(val) bfin_write16(IMDMA_S1_CONFIG,val)
1527#define bfin_read_IMDMA_S1_NEXT_DESC_PTR() bfin_read32(IMDMA_S1_NEXT_DESC_PTR)
1528#define bfin_write_IMDMA_S1_NEXT_DESC_PTR(val) bfin_write32(IMDMA_S1_NEXT_DESC_PTR,val)
1529#define bfin_read_IMDMA_S1_START_ADDR() bfin_read32(IMDMA_S1_START_ADDR)
1530#define bfin_write_IMDMA_S1_START_ADDR(val) bfin_write32(IMDMA_S1_START_ADDR,val)
1531#define bfin_read_IMDMA_S1_X_COUNT() bfin_read16(IMDMA_S1_X_COUNT)
1532#define bfin_write_IMDMA_S1_X_COUNT(val) bfin_write16(IMDMA_S1_X_COUNT,val)
1533#define bfin_read_IMDMA_S1_Y_COUNT() bfin_read16(IMDMA_S1_Y_COUNT)
1534#define bfin_write_IMDMA_S1_Y_COUNT(val) bfin_write16(IMDMA_S1_Y_COUNT,val)
1535#define bfin_read_IMDMA_S1_X_MODIFY() bfin_read16(IMDMA_S1_X_MODIFY)
1536#define bfin_write_IMDMA_S1_X_MODIFY(val) bfin_write16(IMDMA_S1_X_MODIFY,val)
1537#define bfin_read_IMDMA_S1_Y_MODIFY() bfin_read16(IMDMA_S1_Y_MODIFY)
1538#define bfin_write_IMDMA_S1_Y_MODIFY(val) bfin_write16(IMDMA_S1_Y_MODIFY,val)
1539#define bfin_read_IMDMA_S1_CURR_DESC_PTR() bfin_read32(IMDMA_S1_CURR_DESC_PTR)
1540#define bfin_write_IMDMA_S1_CURR_DESC_PTR(val) bfin_write32(IMDMA_S1_CURR_DESC_PTR,val)
1541#define bfin_read_IMDMA_S1_CURR_ADDR() bfin_read32(IMDMA_S1_CURR_ADDR)
1542#define bfin_write_IMDMA_S1_CURR_ADDR(val) bfin_write32(IMDMA_S1_CURR_ADDR,val)
1543#define bfin_read_IMDMA_S1_CURR_X_COUNT() bfin_read16(IMDMA_S1_CURR_X_COUNT)
1544#define bfin_write_IMDMA_S1_CURR_X_COUNT(val) bfin_write16(IMDMA_S1_CURR_X_COUNT,val)
1545#define bfin_read_IMDMA_S1_CURR_Y_COUNT() bfin_read16(IMDMA_S1_CURR_Y_COUNT)
1546#define bfin_write_IMDMA_S1_CURR_Y_COUNT(val) bfin_write16(IMDMA_S1_CURR_Y_COUNT,val)
1547#define bfin_read_IMDMA_S1_IRQ_STATUS() bfin_read16(IMDMA_S1_IRQ_STATUS)
1548#define bfin_write_IMDMA_S1_IRQ_STATUS(val) bfin_write16(IMDMA_S1_IRQ_STATUS,val)
1549
1550#define bfin_read_MDMA_S0_CONFIG() bfin_read_MDMA1_S0_CONFIG()
1551#define bfin_write_MDMA_S0_CONFIG(val) bfin_write_MDMA1_S0_CONFIG(val)
1552#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read_MDMA1_S0_IRQ_STATUS()
1553#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write_MDMA1_S0_IRQ_STATUS(val)
1554#define bfin_read_MDMA_S0_X_MODIFY() bfin_read_MDMA1_S0_X_MODIFY()
1555#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write_MDMA1_S0_X_MODIFY(val)
1556#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read_MDMA1_S0_Y_MODIFY()
1557#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write_MDMA1_S0_Y_MODIFY(val)
1558#define bfin_read_MDMA_S0_X_COUNT() bfin_read_MDMA1_S0_X_COUNT()
1559#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write_MDMA1_S0_X_COUNT(val)
1560#define bfin_read_MDMA_S0_Y_COUNT() bfin_read_MDMA1_S0_Y_COUNT()
1561#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write_MDMA1_S0_Y_COUNT(val)
1562#define bfin_read_MDMA_S0_START_ADDR() bfin_read_MDMA1_S0_START_ADDR()
1563#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write_MDMA1_S0_START_ADDR(val)
1564#define bfin_read_MDMA_D0_CONFIG() bfin_read_MDMA1_D0_CONFIG()
1565#define bfin_write_MDMA_D0_CONFIG(val) bfin_write_MDMA1_D0_CONFIG(val)
1566#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read_MDMA1_D0_IRQ_STATUS()
1567#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write_MDMA1_D0_IRQ_STATUS(val)
1568#define bfin_read_MDMA_D0_X_MODIFY() bfin_read_MDMA1_D0_X_MODIFY()
1569#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write_MDMA1_D0_X_MODIFY(val)
1570#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read_MDMA1_D0_Y_MODIFY()
1571#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write_MDMA1_D0_Y_MODIFY(val)
1572#define bfin_read_MDMA_D0_X_COUNT() bfin_read_MDMA1_D0_X_COUNT()
1573#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write_MDMA1_D0_X_COUNT(val)
1574#define bfin_read_MDMA_D0_Y_COUNT() bfin_read_MDMA1_D0_Y_COUNT()
1575#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write_MDMA1_D0_Y_COUNT(val)
1576#define bfin_read_MDMA_D0_START_ADDR() bfin_read_MDMA1_D0_START_ADDR()
1577#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write_MDMA1_D0_START_ADDR(val)
1578
1579#endif /* _CDEF_BF561_H */
diff --git a/arch/blackfin/mach-bf561/include/mach/defBF561.h b/arch/blackfin/mach-bf561/include/mach/defBF561.h
new file mode 100644
index 000000000000..4eca2026bb92
--- /dev/null
+++ b/arch/blackfin/mach-bf561/include/mach/defBF561.h
@@ -0,0 +1,1758 @@
1
2/*
3 * File: include/asm-blackfin/mach-bf561/defBF561.h
4 * Based on:
5 * Author:
6 *
7 * Created:
8 * Description:
9 * SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561
10 * Rev:
11 *
12 * Modified:
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#ifndef _DEF_BF561_H
33#define _DEF_BF561_H
34/*
35#if !defined(__ADSPBF561__)
36#warning defBF561.h should only be included for BF561 chip.
37#endif
38*/
39/* include all Core registers and bit definitions */
40#include <asm/def_LPBlackfin.h>
41
42/*********************************************************************************** */
43/* System MMR Register Map */
44/*********************************************************************************** */
45
46/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
47
48#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */
49#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */
50#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */
51#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */
52#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
53#define CHIPID 0xFFC00014 /* Chip ID Register */
54
55/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */
56#define SWRST SICA_SWRST
57#define SYSCR SICA_SYSCR
58#define DOUBLE_FAULT (DOUBLE_FAULT_B|DOUBLE_FAULT_A)
59#define RESET_DOUBLE (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A)
60#define RESET_WDOG (SWRST_WDT_B|SWRST_WDT_A)
61#define RESET_SOFTWARE (SWRST_OCCURRED)
62
63/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
64#define SICA_SWRST 0xFFC00100 /* Software Reset register */
65#define SICA_SYSCR 0xFFC00104 /* System Reset Configuration register */
66#define SICA_RVECT 0xFFC00108 /* SIC Reset Vector Address Register */
67#define SICA_IMASK 0xFFC0010C /* SIC Interrupt Mask register 0 - hack to fix old tests */
68#define SICA_IMASK0 0xFFC0010C /* SIC Interrupt Mask register 0 */
69#define SICA_IMASK1 0xFFC00110 /* SIC Interrupt Mask register 1 */
70#define SICA_IAR0 0xFFC00124 /* SIC Interrupt Assignment Register 0 */
71#define SICA_IAR1 0xFFC00128 /* SIC Interrupt Assignment Register 1 */
72#define SICA_IAR2 0xFFC0012C /* SIC Interrupt Assignment Register 2 */
73#define SICA_IAR3 0xFFC00130 /* SIC Interrupt Assignment Register 3 */
74#define SICA_IAR4 0xFFC00134 /* SIC Interrupt Assignment Register 4 */
75#define SICA_IAR5 0xFFC00138 /* SIC Interrupt Assignment Register 5 */
76#define SICA_IAR6 0xFFC0013C /* SIC Interrupt Assignment Register 6 */
77#define SICA_IAR7 0xFFC00140 /* SIC Interrupt Assignment Register 7 */
78#define SICA_ISR0 0xFFC00114 /* SIC Interrupt Status register 0 */
79#define SICA_ISR1 0xFFC00118 /* SIC Interrupt Status register 1 */
80#define SICA_IWR0 0xFFC0011C /* SIC Interrupt Wakeup-Enable register 0 */
81#define SICA_IWR1 0xFFC00120 /* SIC Interrupt Wakeup-Enable register 1 */
82
83/* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */
84#define SICB_SWRST 0xFFC01100 /* reserved */
85#define SICB_SYSCR 0xFFC01104 /* reserved */
86#define SICB_RVECT 0xFFC01108 /* SIC Reset Vector Address Register */
87#define SICB_IMASK0 0xFFC0110C /* SIC Interrupt Mask register 0 */
88#define SICB_IMASK1 0xFFC01110 /* SIC Interrupt Mask register 1 */
89#define SICB_IAR0 0xFFC01124 /* SIC Interrupt Assignment Register 0 */
90#define SICB_IAR1 0xFFC01128 /* SIC Interrupt Assignment Register 1 */
91#define SICB_IAR2 0xFFC0112C /* SIC Interrupt Assignment Register 2 */
92#define SICB_IAR3 0xFFC01130 /* SIC Interrupt Assignment Register 3 */
93#define SICB_IAR4 0xFFC01134 /* SIC Interrupt Assignment Register 4 */
94#define SICB_IAR5 0xFFC01138 /* SIC Interrupt Assignment Register 5 */
95#define SICB_IAR6 0xFFC0113C /* SIC Interrupt Assignment Register 6 */
96#define SICB_IAR7 0xFFC01140 /* SIC Interrupt Assignment Register 7 */
97#define SICB_ISR0 0xFFC01114 /* SIC Interrupt Status register 0 */
98#define SICB_ISR1 0xFFC01118 /* SIC Interrupt Status register 1 */
99#define SICB_IWR0 0xFFC0111C /* SIC Interrupt Wakeup-Enable register 0 */
100#define SICB_IWR1 0xFFC01120 /* SIC Interrupt Wakeup-Enable register 1 */
101
102/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */
103#define WDOGA_CTL 0xFFC00200 /* Watchdog Control register */
104#define WDOGA_CNT 0xFFC00204 /* Watchdog Count register */
105#define WDOGA_STAT 0xFFC00208 /* Watchdog Status register */
106
107/* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */
108#define WDOGB_CTL 0xFFC01200 /* Watchdog Control register */
109#define WDOGB_CNT 0xFFC01204 /* Watchdog Count register */
110#define WDOGB_STAT 0xFFC01208 /* Watchdog Status register */
111
112/* UART Controller (0xFFC00400 - 0xFFC004FF) */
113
114/*
115 * Because include/linux/serial_reg.h have defined UART_*,
116 * So we define blackfin uart regs to BFIN_UART0_*.
117 */
118#define BFIN_UART_THR 0xFFC00400 /* Transmit Holding register */
119#define BFIN_UART_RBR 0xFFC00400 /* Receive Buffer register */
120#define BFIN_UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
121#define BFIN_UART_IER 0xFFC00404 /* Interrupt Enable Register */
122#define BFIN_UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
123#define BFIN_UART_IIR 0xFFC00408 /* Interrupt Identification Register */
124#define BFIN_UART_LCR 0xFFC0040C /* Line Control Register */
125#define BFIN_UART_MCR 0xFFC00410 /* Modem Control Register */
126#define BFIN_UART_LSR 0xFFC00414 /* Line Status Register */
127#define BFIN_UART_MSR 0xFFC00418 /* Modem Status Register */
128#define BFIN_UART_SCR 0xFFC0041C /* SCR Scratch Register */
129#define BFIN_UART_GCTL 0xFFC00424 /* Global Control Register */
130
131/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
132#define SPI0_REGBASE 0xFFC00500
133#define SPI_CTL 0xFFC00500 /* SPI Control Register */
134#define SPI_FLG 0xFFC00504 /* SPI Flag register */
135#define SPI_STAT 0xFFC00508 /* SPI Status register */
136#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
137#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
138#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
139#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
140
141/* Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) */
142#define TIMER0_CONFIG 0xFFC00600 /* Timer0 Configuration register */
143#define TIMER0_COUNTER 0xFFC00604 /* Timer0 Counter register */
144#define TIMER0_PERIOD 0xFFC00608 /* Timer0 Period register */
145#define TIMER0_WIDTH 0xFFC0060C /* Timer0 Width register */
146
147#define TIMER1_CONFIG 0xFFC00610 /* Timer1 Configuration register */
148#define TIMER1_COUNTER 0xFFC00614 /* Timer1 Counter register */
149#define TIMER1_PERIOD 0xFFC00618 /* Timer1 Period register */
150#define TIMER1_WIDTH 0xFFC0061C /* Timer1 Width register */
151
152#define TIMER2_CONFIG 0xFFC00620 /* Timer2 Configuration register */
153#define TIMER2_COUNTER 0xFFC00624 /* Timer2 Counter register */
154#define TIMER2_PERIOD 0xFFC00628 /* Timer2 Period register */
155#define TIMER2_WIDTH 0xFFC0062C /* Timer2 Width register */
156
157#define TIMER3_CONFIG 0xFFC00630 /* Timer3 Configuration register */
158#define TIMER3_COUNTER 0xFFC00634 /* Timer3 Counter register */
159#define TIMER3_PERIOD 0xFFC00638 /* Timer3 Period register */
160#define TIMER3_WIDTH 0xFFC0063C /* Timer3 Width register */
161
162#define TIMER4_CONFIG 0xFFC00640 /* Timer4 Configuration register */
163#define TIMER4_COUNTER 0xFFC00644 /* Timer4 Counter register */
164#define TIMER4_PERIOD 0xFFC00648 /* Timer4 Period register */
165#define TIMER4_WIDTH 0xFFC0064C /* Timer4 Width register */
166
167#define TIMER5_CONFIG 0xFFC00650 /* Timer5 Configuration register */
168#define TIMER5_COUNTER 0xFFC00654 /* Timer5 Counter register */
169#define TIMER5_PERIOD 0xFFC00658 /* Timer5 Period register */
170#define TIMER5_WIDTH 0xFFC0065C /* Timer5 Width register */
171
172#define TIMER6_CONFIG 0xFFC00660 /* Timer6 Configuration register */
173#define TIMER6_COUNTER 0xFFC00664 /* Timer6 Counter register */
174#define TIMER6_PERIOD 0xFFC00668 /* Timer6 Period register */
175#define TIMER6_WIDTH 0xFFC0066C /* Timer6 Width register */
176
177#define TIMER7_CONFIG 0xFFC00670 /* Timer7 Configuration register */
178#define TIMER7_COUNTER 0xFFC00674 /* Timer7 Counter register */
179#define TIMER7_PERIOD 0xFFC00678 /* Timer7 Period register */
180#define TIMER7_WIDTH 0xFFC0067C /* Timer7 Width register */
181
182#define TMRS8_ENABLE 0xFFC00680 /* Timer Enable Register */
183#define TMRS8_DISABLE 0xFFC00684 /* Timer Disable register */
184#define TMRS8_STATUS 0xFFC00688 /* Timer Status register */
185
186/* Timer registers 8-11 (0xFFC0 1600-0xFFC0 16FF) */
187#define TIMER8_CONFIG 0xFFC01600 /* Timer8 Configuration register */
188#define TIMER8_COUNTER 0xFFC01604 /* Timer8 Counter register */
189#define TIMER8_PERIOD 0xFFC01608 /* Timer8 Period register */
190#define TIMER8_WIDTH 0xFFC0160C /* Timer8 Width register */
191
192#define TIMER9_CONFIG 0xFFC01610 /* Timer9 Configuration register */
193#define TIMER9_COUNTER 0xFFC01614 /* Timer9 Counter register */
194#define TIMER9_PERIOD 0xFFC01618 /* Timer9 Period register */
195#define TIMER9_WIDTH 0xFFC0161C /* Timer9 Width register */
196
197#define TIMER10_CONFIG 0xFFC01620 /* Timer10 Configuration register */
198#define TIMER10_COUNTER 0xFFC01624 /* Timer10 Counter register */
199#define TIMER10_PERIOD 0xFFC01628 /* Timer10 Period register */
200#define TIMER10_WIDTH 0xFFC0162C /* Timer10 Width register */
201
202#define TIMER11_CONFIG 0xFFC01630 /* Timer11 Configuration register */
203#define TIMER11_COUNTER 0xFFC01634 /* Timer11 Counter register */
204#define TIMER11_PERIOD 0xFFC01638 /* Timer11 Period register */
205#define TIMER11_WIDTH 0xFFC0163C /* Timer11 Width register */
206
207#define TMRS4_ENABLE 0xFFC01640 /* Timer Enable Register */
208#define TMRS4_DISABLE 0xFFC01644 /* Timer Disable register */
209#define TMRS4_STATUS 0xFFC01648 /* Timer Status register */
210
211/* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */
212#define FIO0_FLAG_D 0xFFC00700 /* Flag Data register */
213#define FIO0_FLAG_C 0xFFC00704 /* Flag Clear register */
214#define FIO0_FLAG_S 0xFFC00708 /* Flag Set register */
215#define FIO0_FLAG_T 0xFFC0070C /* Flag Toggle register */
216#define FIO0_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Data register */
217#define FIO0_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Clear register */
218#define FIO0_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Set register */
219#define FIO0_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Toggle register */
220#define FIO0_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Data register */
221#define FIO0_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Clear register */
222#define FIO0_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Set register */
223#define FIO0_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Toggle register */
224#define FIO0_DIR 0xFFC00730 /* Flag Direction register */
225#define FIO0_POLAR 0xFFC00734 /* Flag Polarity register */
226#define FIO0_EDGE 0xFFC00738 /* Flag Interrupt Sensitivity register */
227#define FIO0_BOTH 0xFFC0073C /* Flag Set on Both Edges register */
228#define FIO0_INEN 0xFFC00740 /* Flag Input Enable register */
229
230/* Programmable Flag 1 registers (0xFFC0 1500-0xFFC0 15FF) */
231#define FIO1_FLAG_D 0xFFC01500 /* Flag Data register (mask used to directly */
232#define FIO1_FLAG_C 0xFFC01504 /* Flag Clear register */
233#define FIO1_FLAG_S 0xFFC01508 /* Flag Set register */
234#define FIO1_FLAG_T 0xFFC0150C /* Flag Toggle register (mask used to */
235#define FIO1_MASKA_D 0xFFC01510 /* Flag Mask Interrupt A Data register */
236#define FIO1_MASKA_C 0xFFC01514 /* Flag Mask Interrupt A Clear register */
237#define FIO1_MASKA_S 0xFFC01518 /* Flag Mask Interrupt A Set register */
238#define FIO1_MASKA_T 0xFFC0151C /* Flag Mask Interrupt A Toggle register */
239#define FIO1_MASKB_D 0xFFC01520 /* Flag Mask Interrupt B Data register */
240#define FIO1_MASKB_C 0xFFC01524 /* Flag Mask Interrupt B Clear register */
241#define FIO1_MASKB_S 0xFFC01528 /* Flag Mask Interrupt B Set register */
242#define FIO1_MASKB_T 0xFFC0152C /* Flag Mask Interrupt B Toggle register */
243#define FIO1_DIR 0xFFC01530 /* Flag Direction register */
244#define FIO1_POLAR 0xFFC01534 /* Flag Polarity register */
245#define FIO1_EDGE 0xFFC01538 /* Flag Interrupt Sensitivity register */
246#define FIO1_BOTH 0xFFC0153C /* Flag Set on Both Edges register */
247#define FIO1_INEN 0xFFC01540 /* Flag Input Enable register */
248
249/* Programmable Flag registers (0xFFC0 1700-0xFFC0 17FF) */
250#define FIO2_FLAG_D 0xFFC01700 /* Flag Data register (mask used to directly */
251#define FIO2_FLAG_C 0xFFC01704 /* Flag Clear register */
252#define FIO2_FLAG_S 0xFFC01708 /* Flag Set register */
253#define FIO2_FLAG_T 0xFFC0170C /* Flag Toggle register (mask used to */
254#define FIO2_MASKA_D 0xFFC01710 /* Flag Mask Interrupt A Data register */
255#define FIO2_MASKA_C 0xFFC01714 /* Flag Mask Interrupt A Clear register */
256#define FIO2_MASKA_S 0xFFC01718 /* Flag Mask Interrupt A Set register */
257#define FIO2_MASKA_T 0xFFC0171C /* Flag Mask Interrupt A Toggle register */
258#define FIO2_MASKB_D 0xFFC01720 /* Flag Mask Interrupt B Data register */
259#define FIO2_MASKB_C 0xFFC01724 /* Flag Mask Interrupt B Clear register */
260#define FIO2_MASKB_S 0xFFC01728 /* Flag Mask Interrupt B Set register */
261#define FIO2_MASKB_T 0xFFC0172C /* Flag Mask Interrupt B Toggle register */
262#define FIO2_DIR 0xFFC01730 /* Flag Direction register */
263#define FIO2_POLAR 0xFFC01734 /* Flag Polarity register */
264#define FIO2_EDGE 0xFFC01738 /* Flag Interrupt Sensitivity register */
265#define FIO2_BOTH 0xFFC0173C /* Flag Set on Both Edges register */
266#define FIO2_INEN 0xFFC01740 /* Flag Input Enable register */
267
268/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
269#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
270#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
271#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
272#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
273#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
274#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
275#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
276#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
277#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
278#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
279#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
280#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
281#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
282#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
283#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
284#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
285#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
286#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
287#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
288#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
289#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
290#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
291
292/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
293#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
294#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
295#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
296#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
297#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
298#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
299#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
300#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
301#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
302#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
303#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
304#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
305#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
306#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
307#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
308#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
309#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
310#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
311#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
312#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
313#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
314#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
315
316/* Asynchronous Memory Controller - External Bus Interface Unit */
317#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
318#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
319#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
320
321/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
322#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
323#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
324#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
325#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
326
327/* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF) */
328#define PPI0_CONTROL 0xFFC01000 /* PPI0 Control register */
329#define PPI0_STATUS 0xFFC01004 /* PPI0 Status register */
330#define PPI0_COUNT 0xFFC01008 /* PPI0 Transfer Count register */
331#define PPI0_DELAY 0xFFC0100C /* PPI0 Delay Count register */
332#define PPI0_FRAME 0xFFC01010 /* PPI0 Frame Length register */
333
334/*Parallel Peripheral Interface (PPI) 1 registers (0xFFC0 1300-0xFFC0 13FF) */
335#define PPI1_CONTROL 0xFFC01300 /* PPI1 Control register */
336#define PPI1_STATUS 0xFFC01304 /* PPI1 Status register */
337#define PPI1_COUNT 0xFFC01308 /* PPI1 Transfer Count register */
338#define PPI1_DELAY 0xFFC0130C /* PPI1 Delay Count register */
339#define PPI1_FRAME 0xFFC01310 /* PPI1 Frame Length register */
340
341/*DMA traffic control registers */
342#define DMA1_TC_PER 0xFFC01B0C /* Traffic control periods */
343#define DMA1_TC_CNT 0xFFC01B10 /* Traffic control current counts */
344#define DMA2_TC_PER 0xFFC00B0C /* Traffic control periods */
345#define DMA2_TC_CNT 0xFFC00B10 /* Traffic control current counts */
346
347/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */
348#define DMA1_0_CONFIG 0xFFC01C08 /* DMA1 Channel 0 Configuration register */
349#define DMA1_0_NEXT_DESC_PTR 0xFFC01C00 /* DMA1 Channel 0 Next Descripter Ptr Reg */
350#define DMA1_0_START_ADDR 0xFFC01C04 /* DMA1 Channel 0 Start Address */
351#define DMA1_0_X_COUNT 0xFFC01C10 /* DMA1 Channel 0 Inner Loop Count */
352#define DMA1_0_Y_COUNT 0xFFC01C18 /* DMA1 Channel 0 Outer Loop Count */
353#define DMA1_0_X_MODIFY 0xFFC01C14 /* DMA1 Channel 0 Inner Loop Addr Increment */
354#define DMA1_0_Y_MODIFY 0xFFC01C1C /* DMA1 Channel 0 Outer Loop Addr Increment */
355#define DMA1_0_CURR_DESC_PTR 0xFFC01C20 /* DMA1 Channel 0 Current Descriptor Pointer */
356#define DMA1_0_CURR_ADDR 0xFFC01C24 /* DMA1 Channel 0 Current Address Pointer */
357#define DMA1_0_CURR_X_COUNT 0xFFC01C30 /* DMA1 Channel 0 Current Inner Loop Count */
358#define DMA1_0_CURR_Y_COUNT 0xFFC01C38 /* DMA1 Channel 0 Current Outer Loop Count */
359#define DMA1_0_IRQ_STATUS 0xFFC01C28 /* DMA1 Channel 0 Interrupt/Status Register */
360#define DMA1_0_PERIPHERAL_MAP 0xFFC01C2C /* DMA1 Channel 0 Peripheral Map Register */
361
362#define DMA1_1_CONFIG 0xFFC01C48 /* DMA1 Channel 1 Configuration register */
363#define DMA1_1_NEXT_DESC_PTR 0xFFC01C40 /* DMA1 Channel 1 Next Descripter Ptr Reg */
364#define DMA1_1_START_ADDR 0xFFC01C44 /* DMA1 Channel 1 Start Address */
365#define DMA1_1_X_COUNT 0xFFC01C50 /* DMA1 Channel 1 Inner Loop Count */
366#define DMA1_1_Y_COUNT 0xFFC01C58 /* DMA1 Channel 1 Outer Loop Count */
367#define DMA1_1_X_MODIFY 0xFFC01C54 /* DMA1 Channel 1 Inner Loop Addr Increment */
368#define DMA1_1_Y_MODIFY 0xFFC01C5C /* DMA1 Channel 1 Outer Loop Addr Increment */
369#define DMA1_1_CURR_DESC_PTR 0xFFC01C60 /* DMA1 Channel 1 Current Descriptor Pointer */
370#define DMA1_1_CURR_ADDR 0xFFC01C64 /* DMA1 Channel 1 Current Address Pointer */
371#define DMA1_1_CURR_X_COUNT 0xFFC01C70 /* DMA1 Channel 1 Current Inner Loop Count */
372#define DMA1_1_CURR_Y_COUNT 0xFFC01C78 /* DMA1 Channel 1 Current Outer Loop Count */
373#define DMA1_1_IRQ_STATUS 0xFFC01C68 /* DMA1 Channel 1 Interrupt/Status Register */
374#define DMA1_1_PERIPHERAL_MAP 0xFFC01C6C /* DMA1 Channel 1 Peripheral Map Register */
375
376#define DMA1_2_CONFIG 0xFFC01C88 /* DMA1 Channel 2 Configuration register */
377#define DMA1_2_NEXT_DESC_PTR 0xFFC01C80 /* DMA1 Channel 2 Next Descripter Ptr Reg */
378#define DMA1_2_START_ADDR 0xFFC01C84 /* DMA1 Channel 2 Start Address */
379#define DMA1_2_X_COUNT 0xFFC01C90 /* DMA1 Channel 2 Inner Loop Count */
380#define DMA1_2_Y_COUNT 0xFFC01C98 /* DMA1 Channel 2 Outer Loop Count */
381#define DMA1_2_X_MODIFY 0xFFC01C94 /* DMA1 Channel 2 Inner Loop Addr Increment */
382#define DMA1_2_Y_MODIFY 0xFFC01C9C /* DMA1 Channel 2 Outer Loop Addr Increment */
383#define DMA1_2_CURR_DESC_PTR 0xFFC01CA0 /* DMA1 Channel 2 Current Descriptor Pointer */
384#define DMA1_2_CURR_ADDR 0xFFC01CA4 /* DMA1 Channel 2 Current Address Pointer */
385#define DMA1_2_CURR_X_COUNT 0xFFC01CB0 /* DMA1 Channel 2 Current Inner Loop Count */
386#define DMA1_2_CURR_Y_COUNT 0xFFC01CB8 /* DMA1 Channel 2 Current Outer Loop Count */
387#define DMA1_2_IRQ_STATUS 0xFFC01CA8 /* DMA1 Channel 2 Interrupt/Status Register */
388#define DMA1_2_PERIPHERAL_MAP 0xFFC01CAC /* DMA1 Channel 2 Peripheral Map Register */
389
390#define DMA1_3_CONFIG 0xFFC01CC8 /* DMA1 Channel 3 Configuration register */
391#define DMA1_3_NEXT_DESC_PTR 0xFFC01CC0 /* DMA1 Channel 3 Next Descripter Ptr Reg */
392#define DMA1_3_START_ADDR 0xFFC01CC4 /* DMA1 Channel 3 Start Address */
393#define DMA1_3_X_COUNT 0xFFC01CD0 /* DMA1 Channel 3 Inner Loop Count */
394#define DMA1_3_Y_COUNT 0xFFC01CD8 /* DMA1 Channel 3 Outer Loop Count */
395#define DMA1_3_X_MODIFY 0xFFC01CD4 /* DMA1 Channel 3 Inner Loop Addr Increment */
396#define DMA1_3_Y_MODIFY 0xFFC01CDC /* DMA1 Channel 3 Outer Loop Addr Increment */
397#define DMA1_3_CURR_DESC_PTR 0xFFC01CE0 /* DMA1 Channel 3 Current Descriptor Pointer */
398#define DMA1_3_CURR_ADDR 0xFFC01CE4 /* DMA1 Channel 3 Current Address Pointer */
399#define DMA1_3_CURR_X_COUNT 0xFFC01CF0 /* DMA1 Channel 3 Current Inner Loop Count */
400#define DMA1_3_CURR_Y_COUNT 0xFFC01CF8 /* DMA1 Channel 3 Current Outer Loop Count */
401#define DMA1_3_IRQ_STATUS 0xFFC01CE8 /* DMA1 Channel 3 Interrupt/Status Register */
402#define DMA1_3_PERIPHERAL_MAP 0xFFC01CEC /* DMA1 Channel 3 Peripheral Map Register */
403
404#define DMA1_4_CONFIG 0xFFC01D08 /* DMA1 Channel 4 Configuration register */
405#define DMA1_4_NEXT_DESC_PTR 0xFFC01D00 /* DMA1 Channel 4 Next Descripter Ptr Reg */
406#define DMA1_4_START_ADDR 0xFFC01D04 /* DMA1 Channel 4 Start Address */
407#define DMA1_4_X_COUNT 0xFFC01D10 /* DMA1 Channel 4 Inner Loop Count */
408#define DMA1_4_Y_COUNT 0xFFC01D18 /* DMA1 Channel 4 Outer Loop Count */
409#define DMA1_4_X_MODIFY 0xFFC01D14 /* DMA1 Channel 4 Inner Loop Addr Increment */
410#define DMA1_4_Y_MODIFY 0xFFC01D1C /* DMA1 Channel 4 Outer Loop Addr Increment */
411#define DMA1_4_CURR_DESC_PTR 0xFFC01D20 /* DMA1 Channel 4 Current Descriptor Pointer */
412#define DMA1_4_CURR_ADDR 0xFFC01D24 /* DMA1 Channel 4 Current Address Pointer */
413#define DMA1_4_CURR_X_COUNT 0xFFC01D30 /* DMA1 Channel 4 Current Inner Loop Count */
414#define DMA1_4_CURR_Y_COUNT 0xFFC01D38 /* DMA1 Channel 4 Current Outer Loop Count */
415#define DMA1_4_IRQ_STATUS 0xFFC01D28 /* DMA1 Channel 4 Interrupt/Status Register */
416#define DMA1_4_PERIPHERAL_MAP 0xFFC01D2C /* DMA1 Channel 4 Peripheral Map Register */
417
418#define DMA1_5_CONFIG 0xFFC01D48 /* DMA1 Channel 5 Configuration register */
419#define DMA1_5_NEXT_DESC_PTR 0xFFC01D40 /* DMA1 Channel 5 Next Descripter Ptr Reg */
420#define DMA1_5_START_ADDR 0xFFC01D44 /* DMA1 Channel 5 Start Address */
421#define DMA1_5_X_COUNT 0xFFC01D50 /* DMA1 Channel 5 Inner Loop Count */
422#define DMA1_5_Y_COUNT 0xFFC01D58 /* DMA1 Channel 5 Outer Loop Count */
423#define DMA1_5_X_MODIFY 0xFFC01D54 /* DMA1 Channel 5 Inner Loop Addr Increment */
424#define DMA1_5_Y_MODIFY 0xFFC01D5C /* DMA1 Channel 5 Outer Loop Addr Increment */
425#define DMA1_5_CURR_DESC_PTR 0xFFC01D60 /* DMA1 Channel 5 Current Descriptor Pointer */
426#define DMA1_5_CURR_ADDR 0xFFC01D64 /* DMA1 Channel 5 Current Address Pointer */
427#define DMA1_5_CURR_X_COUNT 0xFFC01D70 /* DMA1 Channel 5 Current Inner Loop Count */
428#define DMA1_5_CURR_Y_COUNT 0xFFC01D78 /* DMA1 Channel 5 Current Outer Loop Count */
429#define DMA1_5_IRQ_STATUS 0xFFC01D68 /* DMA1 Channel 5 Interrupt/Status Register */
430#define DMA1_5_PERIPHERAL_MAP 0xFFC01D6C /* DMA1 Channel 5 Peripheral Map Register */
431
432#define DMA1_6_CONFIG 0xFFC01D88 /* DMA1 Channel 6 Configuration register */
433#define DMA1_6_NEXT_DESC_PTR 0xFFC01D80 /* DMA1 Channel 6 Next Descripter Ptr Reg */
434#define DMA1_6_START_ADDR 0xFFC01D84 /* DMA1 Channel 6 Start Address */
435#define DMA1_6_X_COUNT 0xFFC01D90 /* DMA1 Channel 6 Inner Loop Count */
436#define DMA1_6_Y_COUNT 0xFFC01D98 /* DMA1 Channel 6 Outer Loop Count */
437#define DMA1_6_X_MODIFY 0xFFC01D94 /* DMA1 Channel 6 Inner Loop Addr Increment */
438#define DMA1_6_Y_MODIFY 0xFFC01D9C /* DMA1 Channel 6 Outer Loop Addr Increment */
439#define DMA1_6_CURR_DESC_PTR 0xFFC01DA0 /* DMA1 Channel 6 Current Descriptor Pointer */
440#define DMA1_6_CURR_ADDR 0xFFC01DA4 /* DMA1 Channel 6 Current Address Pointer */
441#define DMA1_6_CURR_X_COUNT 0xFFC01DB0 /* DMA1 Channel 6 Current Inner Loop Count */
442#define DMA1_6_CURR_Y_COUNT 0xFFC01DB8 /* DMA1 Channel 6 Current Outer Loop Count */
443#define DMA1_6_IRQ_STATUS 0xFFC01DA8 /* DMA1 Channel 6 Interrupt/Status Register */
444#define DMA1_6_PERIPHERAL_MAP 0xFFC01DAC /* DMA1 Channel 6 Peripheral Map Register */
445
446#define DMA1_7_CONFIG 0xFFC01DC8 /* DMA1 Channel 7 Configuration register */
447#define DMA1_7_NEXT_DESC_PTR 0xFFC01DC0 /* DMA1 Channel 7 Next Descripter Ptr Reg */
448#define DMA1_7_START_ADDR 0xFFC01DC4 /* DMA1 Channel 7 Start Address */
449#define DMA1_7_X_COUNT 0xFFC01DD0 /* DMA1 Channel 7 Inner Loop Count */
450#define DMA1_7_Y_COUNT 0xFFC01DD8 /* DMA1 Channel 7 Outer Loop Count */
451#define DMA1_7_X_MODIFY 0xFFC01DD4 /* DMA1 Channel 7 Inner Loop Addr Increment */
452#define DMA1_7_Y_MODIFY 0xFFC01DDC /* DMA1 Channel 7 Outer Loop Addr Increment */
453#define DMA1_7_CURR_DESC_PTR 0xFFC01DE0 /* DMA1 Channel 7 Current Descriptor Pointer */
454#define DMA1_7_CURR_ADDR 0xFFC01DE4 /* DMA1 Channel 7 Current Address Pointer */
455#define DMA1_7_CURR_X_COUNT 0xFFC01DF0 /* DMA1 Channel 7 Current Inner Loop Count */
456#define DMA1_7_CURR_Y_COUNT 0xFFC01DF8 /* DMA1 Channel 7 Current Outer Loop Count */
457#define DMA1_7_IRQ_STATUS 0xFFC01DE8 /* DMA1 Channel 7 Interrupt/Status Register */
458#define DMA1_7_PERIPHERAL_MAP 0xFFC01DEC /* DMA1 Channel 7 Peripheral Map Register */
459
460#define DMA1_8_CONFIG 0xFFC01E08 /* DMA1 Channel 8 Configuration register */
461#define DMA1_8_NEXT_DESC_PTR 0xFFC01E00 /* DMA1 Channel 8 Next Descripter Ptr Reg */
462#define DMA1_8_START_ADDR 0xFFC01E04 /* DMA1 Channel 8 Start Address */
463#define DMA1_8_X_COUNT 0xFFC01E10 /* DMA1 Channel 8 Inner Loop Count */
464#define DMA1_8_Y_COUNT 0xFFC01E18 /* DMA1 Channel 8 Outer Loop Count */
465#define DMA1_8_X_MODIFY 0xFFC01E14 /* DMA1 Channel 8 Inner Loop Addr Increment */
466#define DMA1_8_Y_MODIFY 0xFFC01E1C /* DMA1 Channel 8 Outer Loop Addr Increment */
467#define DMA1_8_CURR_DESC_PTR 0xFFC01E20 /* DMA1 Channel 8 Current Descriptor Pointer */
468#define DMA1_8_CURR_ADDR 0xFFC01E24 /* DMA1 Channel 8 Current Address Pointer */
469#define DMA1_8_CURR_X_COUNT 0xFFC01E30 /* DMA1 Channel 8 Current Inner Loop Count */
470#define DMA1_8_CURR_Y_COUNT 0xFFC01E38 /* DMA1 Channel 8 Current Outer Loop Count */
471#define DMA1_8_IRQ_STATUS 0xFFC01E28 /* DMA1 Channel 8 Interrupt/Status Register */
472#define DMA1_8_PERIPHERAL_MAP 0xFFC01E2C /* DMA1 Channel 8 Peripheral Map Register */
473
474#define DMA1_9_CONFIG 0xFFC01E48 /* DMA1 Channel 9 Configuration register */
475#define DMA1_9_NEXT_DESC_PTR 0xFFC01E40 /* DMA1 Channel 9 Next Descripter Ptr Reg */
476#define DMA1_9_START_ADDR 0xFFC01E44 /* DMA1 Channel 9 Start Address */
477#define DMA1_9_X_COUNT 0xFFC01E50 /* DMA1 Channel 9 Inner Loop Count */
478#define DMA1_9_Y_COUNT 0xFFC01E58 /* DMA1 Channel 9 Outer Loop Count */
479#define DMA1_9_X_MODIFY 0xFFC01E54 /* DMA1 Channel 9 Inner Loop Addr Increment */
480#define DMA1_9_Y_MODIFY 0xFFC01E5C /* DMA1 Channel 9 Outer Loop Addr Increment */
481#define DMA1_9_CURR_DESC_PTR 0xFFC01E60 /* DMA1 Channel 9 Current Descriptor Pointer */
482#define DMA1_9_CURR_ADDR 0xFFC01E64 /* DMA1 Channel 9 Current Address Pointer */
483#define DMA1_9_CURR_X_COUNT 0xFFC01E70 /* DMA1 Channel 9 Current Inner Loop Count */
484#define DMA1_9_CURR_Y_COUNT 0xFFC01E78 /* DMA1 Channel 9 Current Outer Loop Count */
485#define DMA1_9_IRQ_STATUS 0xFFC01E68 /* DMA1 Channel 9 Interrupt/Status Register */
486#define DMA1_9_PERIPHERAL_MAP 0xFFC01E6C /* DMA1 Channel 9 Peripheral Map Register */
487
488#define DMA1_10_CONFIG 0xFFC01E88 /* DMA1 Channel 10 Configuration register */
489#define DMA1_10_NEXT_DESC_PTR 0xFFC01E80 /* DMA1 Channel 10 Next Descripter Ptr Reg */
490#define DMA1_10_START_ADDR 0xFFC01E84 /* DMA1 Channel 10 Start Address */
491#define DMA1_10_X_COUNT 0xFFC01E90 /* DMA1 Channel 10 Inner Loop Count */
492#define DMA1_10_Y_COUNT 0xFFC01E98 /* DMA1 Channel 10 Outer Loop Count */
493#define DMA1_10_X_MODIFY 0xFFC01E94 /* DMA1 Channel 10 Inner Loop Addr Increment */
494#define DMA1_10_Y_MODIFY 0xFFC01E9C /* DMA1 Channel 10 Outer Loop Addr Increment */
495#define DMA1_10_CURR_DESC_PTR 0xFFC01EA0 /* DMA1 Channel 10 Current Descriptor Pointer */
496#define DMA1_10_CURR_ADDR 0xFFC01EA4 /* DMA1 Channel 10 Current Address Pointer */
497#define DMA1_10_CURR_X_COUNT 0xFFC01EB0 /* DMA1 Channel 10 Current Inner Loop Count */
498#define DMA1_10_CURR_Y_COUNT 0xFFC01EB8 /* DMA1 Channel 10 Current Outer Loop Count */
499#define DMA1_10_IRQ_STATUS 0xFFC01EA8 /* DMA1 Channel 10 Interrupt/Status Register */
500#define DMA1_10_PERIPHERAL_MAP 0xFFC01EAC /* DMA1 Channel 10 Peripheral Map Register */
501
502#define DMA1_11_CONFIG 0xFFC01EC8 /* DMA1 Channel 11 Configuration register */
503#define DMA1_11_NEXT_DESC_PTR 0xFFC01EC0 /* DMA1 Channel 11 Next Descripter Ptr Reg */
504#define DMA1_11_START_ADDR 0xFFC01EC4 /* DMA1 Channel 11 Start Address */
505#define DMA1_11_X_COUNT 0xFFC01ED0 /* DMA1 Channel 11 Inner Loop Count */
506#define DMA1_11_Y_COUNT 0xFFC01ED8 /* DMA1 Channel 11 Outer Loop Count */
507#define DMA1_11_X_MODIFY 0xFFC01ED4 /* DMA1 Channel 11 Inner Loop Addr Increment */
508#define DMA1_11_Y_MODIFY 0xFFC01EDC /* DMA1 Channel 11 Outer Loop Addr Increment */
509#define DMA1_11_CURR_DESC_PTR 0xFFC01EE0 /* DMA1 Channel 11 Current Descriptor Pointer */
510#define DMA1_11_CURR_ADDR 0xFFC01EE4 /* DMA1 Channel 11 Current Address Pointer */
511#define DMA1_11_CURR_X_COUNT 0xFFC01EF0 /* DMA1 Channel 11 Current Inner Loop Count */
512#define DMA1_11_CURR_Y_COUNT 0xFFC01EF8 /* DMA1 Channel 11 Current Outer Loop Count */
513#define DMA1_11_IRQ_STATUS 0xFFC01EE8 /* DMA1 Channel 11 Interrupt/Status Register */
514#define DMA1_11_PERIPHERAL_MAP 0xFFC01EEC /* DMA1 Channel 11 Peripheral Map Register */
515
516/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */
517#define MDMA1_D0_CONFIG 0xFFC01F08 /*MemDMA1 Stream 0 Destination Configuration */
518#define MDMA1_D0_NEXT_DESC_PTR 0xFFC01F00 /*MemDMA1 Stream 0 Destination Next Descriptor Ptr Reg */
519#define MDMA1_D0_START_ADDR 0xFFC01F04 /*MemDMA1 Stream 0 Destination Start Address */
520#define MDMA1_D0_X_COUNT 0xFFC01F10 /*MemDMA1 Stream 0 Destination Inner-Loop Count */
521#define MDMA1_D0_Y_COUNT 0xFFC01F18 /*MemDMA1 Stream 0 Destination Outer-Loop Count */
522#define MDMA1_D0_X_MODIFY 0xFFC01F14 /*MemDMA1 Stream 0 Dest Inner-Loop Address-Increment */
523#define MDMA1_D0_Y_MODIFY 0xFFC01F1C /*MemDMA1 Stream 0 Dest Outer-Loop Address-Increment */
524#define MDMA1_D0_CURR_DESC_PTR 0xFFC01F20 /*MemDMA1 Stream 0 Dest Current Descriptor Ptr reg */
525#define MDMA1_D0_CURR_ADDR 0xFFC01F24 /*MemDMA1 Stream 0 Destination Current Address */
526#define MDMA1_D0_CURR_X_COUNT 0xFFC01F30 /*MemDMA1 Stream 0 Dest Current Inner-Loop Count */
527#define MDMA1_D0_CURR_Y_COUNT 0xFFC01F38 /*MemDMA1 Stream 0 Dest Current Outer-Loop Count */
528#define MDMA1_D0_IRQ_STATUS 0xFFC01F28 /*MemDMA1 Stream 0 Destination Interrupt/Status */
529#define MDMA1_D0_PERIPHERAL_MAP 0xFFC01F2C /*MemDMA1 Stream 0 Destination Peripheral Map */
530
531#define MDMA1_S0_CONFIG 0xFFC01F48 /*MemDMA1 Stream 0 Source Configuration */
532#define MDMA1_S0_NEXT_DESC_PTR 0xFFC01F40 /*MemDMA1 Stream 0 Source Next Descriptor Ptr Reg */
533#define MDMA1_S0_START_ADDR 0xFFC01F44 /*MemDMA1 Stream 0 Source Start Address */
534#define MDMA1_S0_X_COUNT 0xFFC01F50 /*MemDMA1 Stream 0 Source Inner-Loop Count */
535#define MDMA1_S0_Y_COUNT 0xFFC01F58 /*MemDMA1 Stream 0 Source Outer-Loop Count */
536#define MDMA1_S0_X_MODIFY 0xFFC01F54 /*MemDMA1 Stream 0 Source Inner-Loop Address-Increment */
537#define MDMA1_S0_Y_MODIFY 0xFFC01F5C /*MemDMA1 Stream 0 Source Outer-Loop Address-Increment */
538#define MDMA1_S0_CURR_DESC_PTR 0xFFC01F60 /*MemDMA1 Stream 0 Source Current Descriptor Ptr reg */
539#define MDMA1_S0_CURR_ADDR 0xFFC01F64 /*MemDMA1 Stream 0 Source Current Address */
540#define MDMA1_S0_CURR_X_COUNT 0xFFC01F70 /*MemDMA1 Stream 0 Source Current Inner-Loop Count */
541#define MDMA1_S0_CURR_Y_COUNT 0xFFC01F78 /*MemDMA1 Stream 0 Source Current Outer-Loop Count */
542#define MDMA1_S0_IRQ_STATUS 0xFFC01F68 /*MemDMA1 Stream 0 Source Interrupt/Status */
543#define MDMA1_S0_PERIPHERAL_MAP 0xFFC01F6C /*MemDMA1 Stream 0 Source Peripheral Map */
544
545#define MDMA1_D1_CONFIG 0xFFC01F88 /*MemDMA1 Stream 1 Destination Configuration */
546#define MDMA1_D1_NEXT_DESC_PTR 0xFFC01F80 /*MemDMA1 Stream 1 Destination Next Descriptor Ptr Reg */
547#define MDMA1_D1_START_ADDR 0xFFC01F84 /*MemDMA1 Stream 1 Destination Start Address */
548#define MDMA1_D1_X_COUNT 0xFFC01F90 /*MemDMA1 Stream 1 Destination Inner-Loop Count */
549#define MDMA1_D1_Y_COUNT 0xFFC01F98 /*MemDMA1 Stream 1 Destination Outer-Loop Count */
550#define MDMA1_D1_X_MODIFY 0xFFC01F94 /*MemDMA1 Stream 1 Dest Inner-Loop Address-Increment */
551#define MDMA1_D1_Y_MODIFY 0xFFC01F9C /*MemDMA1 Stream 1 Dest Outer-Loop Address-Increment */
552#define MDMA1_D1_CURR_DESC_PTR 0xFFC01FA0 /*MemDMA1 Stream 1 Dest Current Descriptor Ptr reg */
553#define MDMA1_D1_CURR_ADDR 0xFFC01FA4 /*MemDMA1 Stream 1 Dest Current Address */
554#define MDMA1_D1_CURR_X_COUNT 0xFFC01FB0 /*MemDMA1 Stream 1 Dest Current Inner-Loop Count */
555#define MDMA1_D1_CURR_Y_COUNT 0xFFC01FB8 /*MemDMA1 Stream 1 Dest Current Outer-Loop Count */
556#define MDMA1_D1_IRQ_STATUS 0xFFC01FA8 /*MemDMA1 Stream 1 Dest Interrupt/Status */
557#define MDMA1_D1_PERIPHERAL_MAP 0xFFC01FAC /*MemDMA1 Stream 1 Dest Peripheral Map */
558
559#define MDMA1_S1_CONFIG 0xFFC01FC8 /*MemDMA1 Stream 1 Source Configuration */
560#define MDMA1_S1_NEXT_DESC_PTR 0xFFC01FC0 /*MemDMA1 Stream 1 Source Next Descriptor Ptr Reg */
561#define MDMA1_S1_START_ADDR 0xFFC01FC4 /*MemDMA1 Stream 1 Source Start Address */
562#define MDMA1_S1_X_COUNT 0xFFC01FD0 /*MemDMA1 Stream 1 Source Inner-Loop Count */
563#define MDMA1_S1_Y_COUNT 0xFFC01FD8 /*MemDMA1 Stream 1 Source Outer-Loop Count */
564#define MDMA1_S1_X_MODIFY 0xFFC01FD4 /*MemDMA1 Stream 1 Source Inner-Loop Address-Increment */
565#define MDMA1_S1_Y_MODIFY 0xFFC01FDC /*MemDMA1 Stream 1 Source Outer-Loop Address-Increment */
566#define MDMA1_S1_CURR_DESC_PTR 0xFFC01FE0 /*MemDMA1 Stream 1 Source Current Descriptor Ptr reg */
567#define MDMA1_S1_CURR_ADDR 0xFFC01FE4 /*MemDMA1 Stream 1 Source Current Address */
568#define MDMA1_S1_CURR_X_COUNT 0xFFC01FF0 /*MemDMA1 Stream 1 Source Current Inner-Loop Count */
569#define MDMA1_S1_CURR_Y_COUNT 0xFFC01FF8 /*MemDMA1 Stream 1 Source Current Outer-Loop Count */
570#define MDMA1_S1_IRQ_STATUS 0xFFC01FE8 /*MemDMA1 Stream 1 Source Interrupt/Status */
571#define MDMA1_S1_PERIPHERAL_MAP 0xFFC01FEC /*MemDMA1 Stream 1 Source Peripheral Map */
572
573/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */
574#define DMA2_0_CONFIG 0xFFC00C08 /* DMA2 Channel 0 Configuration register */
575#define DMA2_0_NEXT_DESC_PTR 0xFFC00C00 /* DMA2 Channel 0 Next Descripter Ptr Reg */
576#define DMA2_0_START_ADDR 0xFFC00C04 /* DMA2 Channel 0 Start Address */
577#define DMA2_0_X_COUNT 0xFFC00C10 /* DMA2 Channel 0 Inner Loop Count */
578#define DMA2_0_Y_COUNT 0xFFC00C18 /* DMA2 Channel 0 Outer Loop Count */
579#define DMA2_0_X_MODIFY 0xFFC00C14 /* DMA2 Channel 0 Inner Loop Addr Increment */
580#define DMA2_0_Y_MODIFY 0xFFC00C1C /* DMA2 Channel 0 Outer Loop Addr Increment */
581#define DMA2_0_CURR_DESC_PTR 0xFFC00C20 /* DMA2 Channel 0 Current Descriptor Pointer */
582#define DMA2_0_CURR_ADDR 0xFFC00C24 /* DMA2 Channel 0 Current Address Pointer */
583#define DMA2_0_CURR_X_COUNT 0xFFC00C30 /* DMA2 Channel 0 Current Inner Loop Count */
584#define DMA2_0_CURR_Y_COUNT 0xFFC00C38 /* DMA2 Channel 0 Current Outer Loop Count */
585#define DMA2_0_IRQ_STATUS 0xFFC00C28 /* DMA2 Channel 0 Interrupt/Status Register */
586#define DMA2_0_PERIPHERAL_MAP 0xFFC00C2C /* DMA2 Channel 0 Peripheral Map Register */
587
588#define DMA2_1_CONFIG 0xFFC00C48 /* DMA2 Channel 1 Configuration register */
589#define DMA2_1_NEXT_DESC_PTR 0xFFC00C40 /* DMA2 Channel 1 Next Descripter Ptr Reg */
590#define DMA2_1_START_ADDR 0xFFC00C44 /* DMA2 Channel 1 Start Address */
591#define DMA2_1_X_COUNT 0xFFC00C50 /* DMA2 Channel 1 Inner Loop Count */
592#define DMA2_1_Y_COUNT 0xFFC00C58 /* DMA2 Channel 1 Outer Loop Count */
593#define DMA2_1_X_MODIFY 0xFFC00C54 /* DMA2 Channel 1 Inner Loop Addr Increment */
594#define DMA2_1_Y_MODIFY 0xFFC00C5C /* DMA2 Channel 1 Outer Loop Addr Increment */
595#define DMA2_1_CURR_DESC_PTR 0xFFC00C60 /* DMA2 Channel 1 Current Descriptor Pointer */
596#define DMA2_1_CURR_ADDR 0xFFC00C64 /* DMA2 Channel 1 Current Address Pointer */
597#define DMA2_1_CURR_X_COUNT 0xFFC00C70 /* DMA2 Channel 1 Current Inner Loop Count */
598#define DMA2_1_CURR_Y_COUNT 0xFFC00C78 /* DMA2 Channel 1 Current Outer Loop Count */
599#define DMA2_1_IRQ_STATUS 0xFFC00C68 /* DMA2 Channel 1 Interrupt/Status Register */
600#define DMA2_1_PERIPHERAL_MAP 0xFFC00C6C /* DMA2 Channel 1 Peripheral Map Register */
601
602#define DMA2_2_CONFIG 0xFFC00C88 /* DMA2 Channel 2 Configuration register */
603#define DMA2_2_NEXT_DESC_PTR 0xFFC00C80 /* DMA2 Channel 2 Next Descripter Ptr Reg */
604#define DMA2_2_START_ADDR 0xFFC00C84 /* DMA2 Channel 2 Start Address */
605#define DMA2_2_X_COUNT 0xFFC00C90 /* DMA2 Channel 2 Inner Loop Count */
606#define DMA2_2_Y_COUNT 0xFFC00C98 /* DMA2 Channel 2 Outer Loop Count */
607#define DMA2_2_X_MODIFY 0xFFC00C94 /* DMA2 Channel 2 Inner Loop Addr Increment */
608#define DMA2_2_Y_MODIFY 0xFFC00C9C /* DMA2 Channel 2 Outer Loop Addr Increment */
609#define DMA2_2_CURR_DESC_PTR 0xFFC00CA0 /* DMA2 Channel 2 Current Descriptor Pointer */
610#define DMA2_2_CURR_ADDR 0xFFC00CA4 /* DMA2 Channel 2 Current Address Pointer */
611#define DMA2_2_CURR_X_COUNT 0xFFC00CB0 /* DMA2 Channel 2 Current Inner Loop Count */
612#define DMA2_2_CURR_Y_COUNT 0xFFC00CB8 /* DMA2 Channel 2 Current Outer Loop Count */
613#define DMA2_2_IRQ_STATUS 0xFFC00CA8 /* DMA2 Channel 2 Interrupt/Status Register */
614#define DMA2_2_PERIPHERAL_MAP 0xFFC00CAC /* DMA2 Channel 2 Peripheral Map Register */
615
616#define DMA2_3_CONFIG 0xFFC00CC8 /* DMA2 Channel 3 Configuration register */
617#define DMA2_3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA2 Channel 3 Next Descripter Ptr Reg */
618#define DMA2_3_START_ADDR 0xFFC00CC4 /* DMA2 Channel 3 Start Address */
619#define DMA2_3_X_COUNT 0xFFC00CD0 /* DMA2 Channel 3 Inner Loop Count */
620#define DMA2_3_Y_COUNT 0xFFC00CD8 /* DMA2 Channel 3 Outer Loop Count */
621#define DMA2_3_X_MODIFY 0xFFC00CD4 /* DMA2 Channel 3 Inner Loop Addr Increment */
622#define DMA2_3_Y_MODIFY 0xFFC00CDC /* DMA2 Channel 3 Outer Loop Addr Increment */
623#define DMA2_3_CURR_DESC_PTR 0xFFC00CE0 /* DMA2 Channel 3 Current Descriptor Pointer */
624#define DMA2_3_CURR_ADDR 0xFFC00CE4 /* DMA2 Channel 3 Current Address Pointer */
625#define DMA2_3_CURR_X_COUNT 0xFFC00CF0 /* DMA2 Channel 3 Current Inner Loop Count */
626#define DMA2_3_CURR_Y_COUNT 0xFFC00CF8 /* DMA2 Channel 3 Current Outer Loop Count */
627#define DMA2_3_IRQ_STATUS 0xFFC00CE8 /* DMA2 Channel 3 Interrupt/Status Register */
628#define DMA2_3_PERIPHERAL_MAP 0xFFC00CEC /* DMA2 Channel 3 Peripheral Map Register */
629
630#define DMA2_4_CONFIG 0xFFC00D08 /* DMA2 Channel 4 Configuration register */
631#define DMA2_4_NEXT_DESC_PTR 0xFFC00D00 /* DMA2 Channel 4 Next Descripter Ptr Reg */
632#define DMA2_4_START_ADDR 0xFFC00D04 /* DMA2 Channel 4 Start Address */
633#define DMA2_4_X_COUNT 0xFFC00D10 /* DMA2 Channel 4 Inner Loop Count */
634#define DMA2_4_Y_COUNT 0xFFC00D18 /* DMA2 Channel 4 Outer Loop Count */
635#define DMA2_4_X_MODIFY 0xFFC00D14 /* DMA2 Channel 4 Inner Loop Addr Increment */
636#define DMA2_4_Y_MODIFY 0xFFC00D1C /* DMA2 Channel 4 Outer Loop Addr Increment */
637#define DMA2_4_CURR_DESC_PTR 0xFFC00D20 /* DMA2 Channel 4 Current Descriptor Pointer */
638#define DMA2_4_CURR_ADDR 0xFFC00D24 /* DMA2 Channel 4 Current Address Pointer */
639#define DMA2_4_CURR_X_COUNT 0xFFC00D30 /* DMA2 Channel 4 Current Inner Loop Count */
640#define DMA2_4_CURR_Y_COUNT 0xFFC00D38 /* DMA2 Channel 4 Current Outer Loop Count */
641#define DMA2_4_IRQ_STATUS 0xFFC00D28 /* DMA2 Channel 4 Interrupt/Status Register */
642#define DMA2_4_PERIPHERAL_MAP 0xFFC00D2C /* DMA2 Channel 4 Peripheral Map Register */
643
644#define DMA2_5_CONFIG 0xFFC00D48 /* DMA2 Channel 5 Configuration register */
645#define DMA2_5_NEXT_DESC_PTR 0xFFC00D40 /* DMA2 Channel 5 Next Descripter Ptr Reg */
646#define DMA2_5_START_ADDR 0xFFC00D44 /* DMA2 Channel 5 Start Address */
647#define DMA2_5_X_COUNT 0xFFC00D50 /* DMA2 Channel 5 Inner Loop Count */
648#define DMA2_5_Y_COUNT 0xFFC00D58 /* DMA2 Channel 5 Outer Loop Count */
649#define DMA2_5_X_MODIFY 0xFFC00D54 /* DMA2 Channel 5 Inner Loop Addr Increment */
650#define DMA2_5_Y_MODIFY 0xFFC00D5C /* DMA2 Channel 5 Outer Loop Addr Increment */
651#define DMA2_5_CURR_DESC_PTR 0xFFC00D60 /* DMA2 Channel 5 Current Descriptor Pointer */
652#define DMA2_5_CURR_ADDR 0xFFC00D64 /* DMA2 Channel 5 Current Address Pointer */
653#define DMA2_5_CURR_X_COUNT 0xFFC00D70 /* DMA2 Channel 5 Current Inner Loop Count */
654#define DMA2_5_CURR_Y_COUNT 0xFFC00D78 /* DMA2 Channel 5 Current Outer Loop Count */
655#define DMA2_5_IRQ_STATUS 0xFFC00D68 /* DMA2 Channel 5 Interrupt/Status Register */
656#define DMA2_5_PERIPHERAL_MAP 0xFFC00D6C /* DMA2 Channel 5 Peripheral Map Register */
657
658#define DMA2_6_CONFIG 0xFFC00D88 /* DMA2 Channel 6 Configuration register */
659#define DMA2_6_NEXT_DESC_PTR 0xFFC00D80 /* DMA2 Channel 6 Next Descripter Ptr Reg */
660#define DMA2_6_START_ADDR 0xFFC00D84 /* DMA2 Channel 6 Start Address */
661#define DMA2_6_X_COUNT 0xFFC00D90 /* DMA2 Channel 6 Inner Loop Count */
662#define DMA2_6_Y_COUNT 0xFFC00D98 /* DMA2 Channel 6 Outer Loop Count */
663#define DMA2_6_X_MODIFY 0xFFC00D94 /* DMA2 Channel 6 Inner Loop Addr Increment */
664#define DMA2_6_Y_MODIFY 0xFFC00D9C /* DMA2 Channel 6 Outer Loop Addr Increment */
665#define DMA2_6_CURR_DESC_PTR 0xFFC00DA0 /* DMA2 Channel 6 Current Descriptor Pointer */
666#define DMA2_6_CURR_ADDR 0xFFC00DA4 /* DMA2 Channel 6 Current Address Pointer */
667#define DMA2_6_CURR_X_COUNT 0xFFC00DB0 /* DMA2 Channel 6 Current Inner Loop Count */
668#define DMA2_6_CURR_Y_COUNT 0xFFC00DB8 /* DMA2 Channel 6 Current Outer Loop Count */
669#define DMA2_6_IRQ_STATUS 0xFFC00DA8 /* DMA2 Channel 6 Interrupt/Status Register */
670#define DMA2_6_PERIPHERAL_MAP 0xFFC00DAC /* DMA2 Channel 6 Peripheral Map Register */
671
672#define DMA2_7_CONFIG 0xFFC00DC8 /* DMA2 Channel 7 Configuration register */
673#define DMA2_7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA2 Channel 7 Next Descripter Ptr Reg */
674#define DMA2_7_START_ADDR 0xFFC00DC4 /* DMA2 Channel 7 Start Address */
675#define DMA2_7_X_COUNT 0xFFC00DD0 /* DMA2 Channel 7 Inner Loop Count */
676#define DMA2_7_Y_COUNT 0xFFC00DD8 /* DMA2 Channel 7 Outer Loop Count */
677#define DMA2_7_X_MODIFY 0xFFC00DD4 /* DMA2 Channel 7 Inner Loop Addr Increment */
678#define DMA2_7_Y_MODIFY 0xFFC00DDC /* DMA2 Channel 7 Outer Loop Addr Increment */
679#define DMA2_7_CURR_DESC_PTR 0xFFC00DE0 /* DMA2 Channel 7 Current Descriptor Pointer */
680#define DMA2_7_CURR_ADDR 0xFFC00DE4 /* DMA2 Channel 7 Current Address Pointer */
681#define DMA2_7_CURR_X_COUNT 0xFFC00DF0 /* DMA2 Channel 7 Current Inner Loop Count */
682#define DMA2_7_CURR_Y_COUNT 0xFFC00DF8 /* DMA2 Channel 7 Current Outer Loop Count */
683#define DMA2_7_IRQ_STATUS 0xFFC00DE8 /* DMA2 Channel 7 Interrupt/Status Register */
684#define DMA2_7_PERIPHERAL_MAP 0xFFC00DEC /* DMA2 Channel 7 Peripheral Map Register */
685
686#define DMA2_8_CONFIG 0xFFC00E08 /* DMA2 Channel 8 Configuration register */
687#define DMA2_8_NEXT_DESC_PTR 0xFFC00E00 /* DMA2 Channel 8 Next Descripter Ptr Reg */
688#define DMA2_8_START_ADDR 0xFFC00E04 /* DMA2 Channel 8 Start Address */
689#define DMA2_8_X_COUNT 0xFFC00E10 /* DMA2 Channel 8 Inner Loop Count */
690#define DMA2_8_Y_COUNT 0xFFC00E18 /* DMA2 Channel 8 Outer Loop Count */
691#define DMA2_8_X_MODIFY 0xFFC00E14 /* DMA2 Channel 8 Inner Loop Addr Increment */
692#define DMA2_8_Y_MODIFY 0xFFC00E1C /* DMA2 Channel 8 Outer Loop Addr Increment */
693#define DMA2_8_CURR_DESC_PTR 0xFFC00E20 /* DMA2 Channel 8 Current Descriptor Pointer */
694#define DMA2_8_CURR_ADDR 0xFFC00E24 /* DMA2 Channel 8 Current Address Pointer */
695#define DMA2_8_CURR_X_COUNT 0xFFC00E30 /* DMA2 Channel 8 Current Inner Loop Count */
696#define DMA2_8_CURR_Y_COUNT 0xFFC00E38 /* DMA2 Channel 8 Current Outer Loop Count */
697#define DMA2_8_IRQ_STATUS 0xFFC00E28 /* DMA2 Channel 8 Interrupt/Status Register */
698#define DMA2_8_PERIPHERAL_MAP 0xFFC00E2C /* DMA2 Channel 8 Peripheral Map Register */
699
700#define DMA2_9_CONFIG 0xFFC00E48 /* DMA2 Channel 9 Configuration register */
701#define DMA2_9_NEXT_DESC_PTR 0xFFC00E40 /* DMA2 Channel 9 Next Descripter Ptr Reg */
702#define DMA2_9_START_ADDR 0xFFC00E44 /* DMA2 Channel 9 Start Address */
703#define DMA2_9_X_COUNT 0xFFC00E50 /* DMA2 Channel 9 Inner Loop Count */
704#define DMA2_9_Y_COUNT 0xFFC00E58 /* DMA2 Channel 9 Outer Loop Count */
705#define DMA2_9_X_MODIFY 0xFFC00E54 /* DMA2 Channel 9 Inner Loop Addr Increment */
706#define DMA2_9_Y_MODIFY 0xFFC00E5C /* DMA2 Channel 9 Outer Loop Addr Increment */
707#define DMA2_9_CURR_DESC_PTR 0xFFC00E60 /* DMA2 Channel 9 Current Descriptor Pointer */
708#define DMA2_9_CURR_ADDR 0xFFC00E64 /* DMA2 Channel 9 Current Address Pointer */
709#define DMA2_9_CURR_X_COUNT 0xFFC00E70 /* DMA2 Channel 9 Current Inner Loop Count */
710#define DMA2_9_CURR_Y_COUNT 0xFFC00E78 /* DMA2 Channel 9 Current Outer Loop Count */
711#define DMA2_9_IRQ_STATUS 0xFFC00E68 /* DMA2 Channel 9 Interrupt/Status Register */
712#define DMA2_9_PERIPHERAL_MAP 0xFFC00E6C /* DMA2 Channel 9 Peripheral Map Register */
713
714#define DMA2_10_CONFIG 0xFFC00E88 /* DMA2 Channel 10 Configuration register */
715#define DMA2_10_NEXT_DESC_PTR 0xFFC00E80 /* DMA2 Channel 10 Next Descripter Ptr Reg */
716#define DMA2_10_START_ADDR 0xFFC00E84 /* DMA2 Channel 10 Start Address */
717#define DMA2_10_X_COUNT 0xFFC00E90 /* DMA2 Channel 10 Inner Loop Count */
718#define DMA2_10_Y_COUNT 0xFFC00E98 /* DMA2 Channel 10 Outer Loop Count */
719#define DMA2_10_X_MODIFY 0xFFC00E94 /* DMA2 Channel 10 Inner Loop Addr Increment */
720#define DMA2_10_Y_MODIFY 0xFFC00E9C /* DMA2 Channel 10 Outer Loop Addr Increment */
721#define DMA2_10_CURR_DESC_PTR 0xFFC00EA0 /* DMA2 Channel 10 Current Descriptor Pointer */
722#define DMA2_10_CURR_ADDR 0xFFC00EA4 /* DMA2 Channel 10 Current Address Pointer */
723#define DMA2_10_CURR_X_COUNT 0xFFC00EB0 /* DMA2 Channel 10 Current Inner Loop Count */
724#define DMA2_10_CURR_Y_COUNT 0xFFC00EB8 /* DMA2 Channel 10 Current Outer Loop Count */
725#define DMA2_10_IRQ_STATUS 0xFFC00EA8 /* DMA2 Channel 10 Interrupt/Status Register */
726#define DMA2_10_PERIPHERAL_MAP 0xFFC00EAC /* DMA2 Channel 10 Peripheral Map Register */
727
728#define DMA2_11_CONFIG 0xFFC00EC8 /* DMA2 Channel 11 Configuration register */
729#define DMA2_11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA2 Channel 11 Next Descripter Ptr Reg */
730#define DMA2_11_START_ADDR 0xFFC00EC4 /* DMA2 Channel 11 Start Address */
731#define DMA2_11_X_COUNT 0xFFC00ED0 /* DMA2 Channel 11 Inner Loop Count */
732#define DMA2_11_Y_COUNT 0xFFC00ED8 /* DMA2 Channel 11 Outer Loop Count */
733#define DMA2_11_X_MODIFY 0xFFC00ED4 /* DMA2 Channel 11 Inner Loop Addr Increment */
734#define DMA2_11_Y_MODIFY 0xFFC00EDC /* DMA2 Channel 11 Outer Loop Addr Increment */
735#define DMA2_11_CURR_DESC_PTR 0xFFC00EE0 /* DMA2 Channel 11 Current Descriptor Pointer */
736#define DMA2_11_CURR_ADDR 0xFFC00EE4 /* DMA2 Channel 11 Current Address Pointer */
737#define DMA2_11_CURR_X_COUNT 0xFFC00EF0 /* DMA2 Channel 11 Current Inner Loop Count */
738#define DMA2_11_CURR_Y_COUNT 0xFFC00EF8 /* DMA2 Channel 11 Current Outer Loop Count */
739#define DMA2_11_IRQ_STATUS 0xFFC00EE8 /* DMA2 Channel 11 Interrupt/Status Register */
740#define DMA2_11_PERIPHERAL_MAP 0xFFC00EEC /* DMA2 Channel 11 Peripheral Map Register */
741
742/* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */
743#define MDMA2_D0_CONFIG 0xFFC00F08 /*MemDMA2 Stream 0 Destination Configuration register */
744#define MDMA2_D0_NEXT_DESC_PTR 0xFFC00F00 /*MemDMA2 Stream 0 Destination Next Descriptor Ptr Reg */
745#define MDMA2_D0_START_ADDR 0xFFC00F04 /*MemDMA2 Stream 0 Destination Start Address */
746#define MDMA2_D0_X_COUNT 0xFFC00F10 /*MemDMA2 Stream 0 Dest Inner-Loop Count register */
747#define MDMA2_D0_Y_COUNT 0xFFC00F18 /*MemDMA2 Stream 0 Dest Outer-Loop Count register */
748#define MDMA2_D0_X_MODIFY 0xFFC00F14 /*MemDMA2 Stream 0 Dest Inner-Loop Address-Increment */
749#define MDMA2_D0_Y_MODIFY 0xFFC00F1C /*MemDMA2 Stream 0 Dest Outer-Loop Address-Increment */
750#define MDMA2_D0_CURR_DESC_PTR 0xFFC00F20 /*MemDMA2 Stream 0 Dest Current Descriptor Ptr reg */
751#define MDMA2_D0_CURR_ADDR 0xFFC00F24 /*MemDMA2 Stream 0 Destination Current Address */
752#define MDMA2_D0_CURR_X_COUNT 0xFFC00F30 /*MemDMA2 Stream 0 Dest Current Inner-Loop Count reg */
753#define MDMA2_D0_CURR_Y_COUNT 0xFFC00F38 /*MemDMA2 Stream 0 Dest Current Outer-Loop Count reg */
754#define MDMA2_D0_IRQ_STATUS 0xFFC00F28 /*MemDMA2 Stream 0 Dest Interrupt/Status Register */
755#define MDMA2_D0_PERIPHERAL_MAP 0xFFC00F2C /*MemDMA2 Stream 0 Destination Peripheral Map register */
756
757#define MDMA2_S0_CONFIG 0xFFC00F48 /*MemDMA2 Stream 0 Source Configuration register */
758#define MDMA2_S0_NEXT_DESC_PTR 0xFFC00F40 /*MemDMA2 Stream 0 Source Next Descriptor Ptr Reg */
759#define MDMA2_S0_START_ADDR 0xFFC00F44 /*MemDMA2 Stream 0 Source Start Address */
760#define MDMA2_S0_X_COUNT 0xFFC00F50 /*MemDMA2 Stream 0 Source Inner-Loop Count register */
761#define MDMA2_S0_Y_COUNT 0xFFC00F58 /*MemDMA2 Stream 0 Source Outer-Loop Count register */
762#define MDMA2_S0_X_MODIFY 0xFFC00F54 /*MemDMA2 Stream 0 Src Inner-Loop Addr-Increment reg */
763#define MDMA2_S0_Y_MODIFY 0xFFC00F5C /*MemDMA2 Stream 0 Src Outer-Loop Addr-Increment reg */
764#define MDMA2_S0_CURR_DESC_PTR 0xFFC00F60 /*MemDMA2 Stream 0 Source Current Descriptor Ptr reg */
765#define MDMA2_S0_CURR_ADDR 0xFFC00F64 /*MemDMA2 Stream 0 Source Current Address */
766#define MDMA2_S0_CURR_X_COUNT 0xFFC00F70 /*MemDMA2 Stream 0 Src Current Inner-Loop Count reg */
767#define MDMA2_S0_CURR_Y_COUNT 0xFFC00F78 /*MemDMA2 Stream 0 Src Current Outer-Loop Count reg */
768#define MDMA2_S0_IRQ_STATUS 0xFFC00F68 /*MemDMA2 Stream 0 Source Interrupt/Status Register */
769#define MDMA2_S0_PERIPHERAL_MAP 0xFFC00F6C /*MemDMA2 Stream 0 Source Peripheral Map register */
770
771#define MDMA2_D1_CONFIG 0xFFC00F88 /*MemDMA2 Stream 1 Destination Configuration register */
772#define MDMA2_D1_NEXT_DESC_PTR 0xFFC00F80 /*MemDMA2 Stream 1 Destination Next Descriptor Ptr Reg */
773#define MDMA2_D1_START_ADDR 0xFFC00F84 /*MemDMA2 Stream 1 Destination Start Address */
774#define MDMA2_D1_X_COUNT 0xFFC00F90 /*MemDMA2 Stream 1 Dest Inner-Loop Count register */
775#define MDMA2_D1_Y_COUNT 0xFFC00F98 /*MemDMA2 Stream 1 Dest Outer-Loop Count register */
776#define MDMA2_D1_X_MODIFY 0xFFC00F94 /*MemDMA2 Stream 1 Dest Inner-Loop Address-Increment */
777#define MDMA2_D1_Y_MODIFY 0xFFC00F9C /*MemDMA2 Stream 1 Dest Outer-Loop Address-Increment */
778#define MDMA2_D1_CURR_DESC_PTR 0xFFC00FA0 /*MemDMA2 Stream 1 Destination Current Descriptor Ptr */
779#define MDMA2_D1_CURR_ADDR 0xFFC00FA4 /*MemDMA2 Stream 1 Destination Current Address reg */
780#define MDMA2_D1_CURR_X_COUNT 0xFFC00FB0 /*MemDMA2 Stream 1 Dest Current Inner-Loop Count reg */
781#define MDMA2_D1_CURR_Y_COUNT 0xFFC00FB8 /*MemDMA2 Stream 1 Dest Current Outer-Loop Count reg */
782#define MDMA2_D1_IRQ_STATUS 0xFFC00FA8 /*MemDMA2 Stream 1 Destination Interrupt/Status Reg */
783#define MDMA2_D1_PERIPHERAL_MAP 0xFFC00FAC /*MemDMA2 Stream 1 Destination Peripheral Map register */
784
785#define MDMA2_S1_CONFIG 0xFFC00FC8 /*MemDMA2 Stream 1 Source Configuration register */
786#define MDMA2_S1_NEXT_DESC_PTR 0xFFC00FC0 /*MemDMA2 Stream 1 Source Next Descriptor Ptr Reg */
787#define MDMA2_S1_START_ADDR 0xFFC00FC4 /*MemDMA2 Stream 1 Source Start Address */
788#define MDMA2_S1_X_COUNT 0xFFC00FD0 /*MemDMA2 Stream 1 Source Inner-Loop Count register */
789#define MDMA2_S1_Y_COUNT 0xFFC00FD8 /*MemDMA2 Stream 1 Source Outer-Loop Count register */
790#define MDMA2_S1_X_MODIFY 0xFFC00FD4 /*MemDMA2 Stream 1 Src Inner-Loop Address-Increment */
791#define MDMA2_S1_Y_MODIFY 0xFFC00FDC /*MemDMA2 Stream 1 Source Outer-Loop Address-Increment */
792#define MDMA2_S1_CURR_DESC_PTR 0xFFC00FE0 /*MemDMA2 Stream 1 Source Current Descriptor Ptr reg */
793#define MDMA2_S1_CURR_ADDR 0xFFC00FE4 /*MemDMA2 Stream 1 Source Current Address */
794#define MDMA2_S1_CURR_X_COUNT 0xFFC00FF0 /*MemDMA2 Stream 1 Source Current Inner-Loop Count */
795#define MDMA2_S1_CURR_Y_COUNT 0xFFC00FF8 /*MemDMA2 Stream 1 Source Current Outer-Loop Count */
796#define MDMA2_S1_IRQ_STATUS 0xFFC00FE8 /*MemDMA2 Stream 1 Source Interrupt/Status Register */
797#define MDMA2_S1_PERIPHERAL_MAP 0xFFC00FEC /*MemDMA2 Stream 1 Source Peripheral Map register */
798
799/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */
800#define IMDMA_D0_CONFIG 0xFFC01808 /*IMDMA Stream 0 Destination Configuration */
801#define IMDMA_D0_NEXT_DESC_PTR 0xFFC01800 /*IMDMA Stream 0 Destination Next Descriptor Ptr Reg */
802#define IMDMA_D0_START_ADDR 0xFFC01804 /*IMDMA Stream 0 Destination Start Address */
803#define IMDMA_D0_X_COUNT 0xFFC01810 /*IMDMA Stream 0 Destination Inner-Loop Count */
804#define IMDMA_D0_Y_COUNT 0xFFC01818 /*IMDMA Stream 0 Destination Outer-Loop Count */
805#define IMDMA_D0_X_MODIFY 0xFFC01814 /*IMDMA Stream 0 Dest Inner-Loop Address-Increment */
806#define IMDMA_D0_Y_MODIFY 0xFFC0181C /*IMDMA Stream 0 Dest Outer-Loop Address-Increment */
807#define IMDMA_D0_CURR_DESC_PTR 0xFFC01820 /*IMDMA Stream 0 Destination Current Descriptor Ptr */
808#define IMDMA_D0_CURR_ADDR 0xFFC01824 /*IMDMA Stream 0 Destination Current Address */
809#define IMDMA_D0_CURR_X_COUNT 0xFFC01830 /*IMDMA Stream 0 Destination Current Inner-Loop Count */
810#define IMDMA_D0_CURR_Y_COUNT 0xFFC01838 /*IMDMA Stream 0 Destination Current Outer-Loop Count */
811#define IMDMA_D0_IRQ_STATUS 0xFFC01828 /*IMDMA Stream 0 Destination Interrupt/Status */
812
813#define IMDMA_S0_CONFIG 0xFFC01848 /*IMDMA Stream 0 Source Configuration */
814#define IMDMA_S0_NEXT_DESC_PTR 0xFFC01840 /*IMDMA Stream 0 Source Next Descriptor Ptr Reg */
815#define IMDMA_S0_START_ADDR 0xFFC01844 /*IMDMA Stream 0 Source Start Address */
816#define IMDMA_S0_X_COUNT 0xFFC01850 /*IMDMA Stream 0 Source Inner-Loop Count */
817#define IMDMA_S0_Y_COUNT 0xFFC01858 /*IMDMA Stream 0 Source Outer-Loop Count */
818#define IMDMA_S0_X_MODIFY 0xFFC01854 /*IMDMA Stream 0 Source Inner-Loop Address-Increment */
819#define IMDMA_S0_Y_MODIFY 0xFFC0185C /*IMDMA Stream 0 Source Outer-Loop Address-Increment */
820#define IMDMA_S0_CURR_DESC_PTR 0xFFC01860 /*IMDMA Stream 0 Source Current Descriptor Ptr reg */
821#define IMDMA_S0_CURR_ADDR 0xFFC01864 /*IMDMA Stream 0 Source Current Address */
822#define IMDMA_S0_CURR_X_COUNT 0xFFC01870 /*IMDMA Stream 0 Source Current Inner-Loop Count */
823#define IMDMA_S0_CURR_Y_COUNT 0xFFC01878 /*IMDMA Stream 0 Source Current Outer-Loop Count */
824#define IMDMA_S0_IRQ_STATUS 0xFFC01868 /*IMDMA Stream 0 Source Interrupt/Status */
825
826#define IMDMA_D1_CONFIG 0xFFC01888 /*IMDMA Stream 1 Destination Configuration */
827#define IMDMA_D1_NEXT_DESC_PTR 0xFFC01880 /*IMDMA Stream 1 Destination Next Descriptor Ptr Reg */
828#define IMDMA_D1_START_ADDR 0xFFC01884 /*IMDMA Stream 1 Destination Start Address */
829#define IMDMA_D1_X_COUNT 0xFFC01890 /*IMDMA Stream 1 Destination Inner-Loop Count */
830#define IMDMA_D1_Y_COUNT 0xFFC01898 /*IMDMA Stream 1 Destination Outer-Loop Count */
831#define IMDMA_D1_X_MODIFY 0xFFC01894 /*IMDMA Stream 1 Dest Inner-Loop Address-Increment */
832#define IMDMA_D1_Y_MODIFY 0xFFC0189C /*IMDMA Stream 1 Dest Outer-Loop Address-Increment */
833#define IMDMA_D1_CURR_DESC_PTR 0xFFC018A0 /*IMDMA Stream 1 Destination Current Descriptor Ptr */
834#define IMDMA_D1_CURR_ADDR 0xFFC018A4 /*IMDMA Stream 1 Destination Current Address */
835#define IMDMA_D1_CURR_X_COUNT 0xFFC018B0 /*IMDMA Stream 1 Destination Current Inner-Loop Count */
836#define IMDMA_D1_CURR_Y_COUNT 0xFFC018B8 /*IMDMA Stream 1 Destination Current Outer-Loop Count */
837#define IMDMA_D1_IRQ_STATUS 0xFFC018A8 /*IMDMA Stream 1 Destination Interrupt/Status */
838
839#define IMDMA_S1_CONFIG 0xFFC018C8 /*IMDMA Stream 1 Source Configuration */
840#define IMDMA_S1_NEXT_DESC_PTR 0xFFC018C0 /*IMDMA Stream 1 Source Next Descriptor Ptr Reg */
841#define IMDMA_S1_START_ADDR 0xFFC018C4 /*IMDMA Stream 1 Source Start Address */
842#define IMDMA_S1_X_COUNT 0xFFC018D0 /*IMDMA Stream 1 Source Inner-Loop Count */
843#define IMDMA_S1_Y_COUNT 0xFFC018D8 /*IMDMA Stream 1 Source Outer-Loop Count */
844#define IMDMA_S1_X_MODIFY 0xFFC018D4 /*IMDMA Stream 1 Source Inner-Loop Address-Increment */
845#define IMDMA_S1_Y_MODIFY 0xFFC018DC /*IMDMA Stream 1 Source Outer-Loop Address-Increment */
846#define IMDMA_S1_CURR_DESC_PTR 0xFFC018E0 /*IMDMA Stream 1 Source Current Descriptor Ptr reg */
847#define IMDMA_S1_CURR_ADDR 0xFFC018E4 /*IMDMA Stream 1 Source Current Address */
848#define IMDMA_S1_CURR_X_COUNT 0xFFC018F0 /*IMDMA Stream 1 Source Current Inner-Loop Count */
849#define IMDMA_S1_CURR_Y_COUNT 0xFFC018F8 /*IMDMA Stream 1 Source Current Outer-Loop Count */
850#define IMDMA_S1_IRQ_STATUS 0xFFC018E8 /*IMDMA Stream 1 Source Interrupt/Status */
851
852/*********************************************************************************** */
853/* System MMR Register Bits */
854/******************************************************************************* */
855
856/* ********************* PLL AND RESET MASKS ************************ */
857
858/* PLL_CTL Masks */
859#define PLL_CLKIN 0x00000000 /* Pass CLKIN to PLL */
860#define PLL_CLKIN_DIV2 0x00000001 /* Pass CLKIN/2 to PLL */
861#define PLL_OFF 0x00000002 /* Shut off PLL clocks */
862#define STOPCK_OFF 0x00000008 /* Core clock off */
863#define PDWN 0x00000020 /* Put the PLL in a Deep Sleep state */
864#define BYPASS 0x00000100 /* Bypass the PLL */
865
866/* CHIPID Masks */
867#define CHIPID_VERSION 0xF0000000
868#define CHIPID_FAMILY 0x0FFFF000
869#define CHIPID_MANUFACTURE 0x00000FFE
870
871/* VR_CTL Masks */
872#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */
873#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
874#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
875#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
876#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
877
878#define GAIN 0x000C /* Voltage Level Gain */
879#define GAIN_5 0x0000 /* GAIN = 5*/
880#define GAIN_10 0x0004 /* GAIN = 1*/
881#define GAIN_20 0x0008 /* GAIN = 2*/
882#define GAIN_50 0x000C /* GAIN = 5*/
883
884#define VLEV 0x00F0 /* Internal Voltage Level */
885#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
886#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
887#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
888#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
889#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
890#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
891#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
892#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
893#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */
894#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
895
896#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
897#define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */
898
899/* PLL_DIV Masks */
900#define SCLK_DIV(x) (x) /* SCLK = VCO / x */
901
902#define CSEL 0x30 /* Core Select */
903#define SSEL 0xf /* System Select */
904#define CCLK_DIV1 0x00000000 /* CCLK = VCO / 1 */
905#define CCLK_DIV2 0x00000010 /* CCLK = VCO / 2 */
906#define CCLK_DIV4 0x00000020 /* CCLK = VCO / 4 */
907#define CCLK_DIV8 0x00000030 /* CCLK = VCO / 8 */
908
909/* PLL_STAT Masks */
910#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
911#define FULL_ON 0x0002 /* Processor In Full On Mode */
912#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
913#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
914
915/* SWRST Mask */
916#define SYSTEM_RESET 0x0007 /* Initiates a system software reset */
917#define DOUBLE_FAULT_A 0x0008 /* Core A Double Fault Causes Reset */
918#define DOUBLE_FAULT_B 0x0010 /* Core B Double Fault Causes Reset */
919#define SWRST_DBL_FAULT_A 0x0800 /* SWRST Core A Double Fault */
920#define SWRST_DBL_FAULT_B 0x1000 /* SWRST Core B Double Fault */
921#define SWRST_WDT_B 0x2000 /* SWRST Watchdog B */
922#define SWRST_WDT_A 0x4000 /* SWRST Watchdog A */
923#define SWRST_OCCURRED 0x8000 /* SWRST Status */
924
925/* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
926
927/* SICu_IARv Masks */
928/* u = A or B */
929/* v = 0 to 7 */
930/* w = 0 or 1 */
931
932/* Per_number = 0 to 63 */
933/* IVG_number = 7 to 15 */
934#define Peripheral_IVG(Per_number, IVG_number) \
935 ((IVG_number) - 7) << (((Per_number) % 8) * 4) /* Peripheral #Per_number assigned IVG #IVG_number */
936 /* Usage: r0.l = lo(Peripheral_IVG(62, 10)); */
937 /* r0.h = hi(Peripheral_IVG(62, 10)); */
938
939/* SICx_IMASKw Masks */
940/* masks are 32 bit wide, so two writes reguired for "64 bit" wide registers */
941#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
942#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
943#define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */
944#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */
945
946/* SIC_IWR Masks */
947#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
948#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
949/* x = pos 0 to 31, for 32-63 use value-32 */
950#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
951#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */
952
953/* ***************************** UART CONTROLLER MASKS ********************** */
954
955/* UART_LCR Register */
956
957#define DLAB 0x80
958#define SB 0x40
959#define STP 0x20
960#define EPS 0x10
961#define PEN 0x08
962#define STB 0x04
963#define WLS(x) ((x-5) & 0x03)
964
965#define DLAB_P 0x07
966#define SB_P 0x06
967#define STP_P 0x05
968#define EPS_P 0x04
969#define PEN_P 0x03
970#define STB_P 0x02
971#define WLS_P1 0x01
972#define WLS_P0 0x00
973
974/* UART_MCR Register */
975#define LOOP_ENA 0x10
976#define LOOP_ENA_P 0x04
977
978/* UART_LSR Register */
979#define TEMT 0x40
980#define THRE 0x20
981#define BI 0x10
982#define FE 0x08
983#define PE 0x04
984#define OE 0x02
985#define DR 0x01
986
987#define TEMP_P 0x06
988#define THRE_P 0x05
989#define BI_P 0x04
990#define FE_P 0x03
991#define PE_P 0x02
992#define OE_P 0x01
993#define DR_P 0x00
994
995/* UART_IER Register */
996#define ELSI 0x04
997#define ETBEI 0x02
998#define ERBFI 0x01
999
1000#define ELSI_P 0x02
1001#define ETBEI_P 0x01
1002#define ERBFI_P 0x00
1003
1004/* UART_IIR Register */
1005#define STATUS(x) ((x << 1) & 0x06)
1006#define NINT 0x01
1007#define STATUS_P1 0x02
1008#define STATUS_P0 0x01
1009#define NINT_P 0x00
1010#define IIR_TX_READY 0x02 /* UART_THR empty */
1011#define IIR_RX_READY 0x04 /* Receive data ready */
1012#define IIR_LINE_CHANGE 0x06 /* Receive line status */
1013#define IIR_STATUS 0x06
1014
1015/* UART_GCTL Register */
1016#define FFE 0x20
1017#define FPE 0x10
1018#define RPOLC 0x08
1019#define TPOLC 0x04
1020#define IREN 0x02
1021#define UCEN 0x01
1022
1023#define FFE_P 0x05
1024#define FPE_P 0x04
1025#define RPOLC_P 0x03
1026#define TPOLC_P 0x02
1027#define IREN_P 0x01
1028#define UCEN_P 0x00
1029
1030/* ********** SERIAL PORT MASKS ********************** */
1031
1032/* SPORTx_TCR1 Masks */
1033#define TSPEN 0x0001 /* TX enable */
1034#define ITCLK 0x0002 /* Internal TX Clock Select */
1035#define TDTYPE 0x000C /* TX Data Formatting Select */
1036#define TLSBIT 0x0010 /* TX Bit Order */
1037#define ITFS 0x0200 /* Internal TX Frame Sync Select */
1038#define TFSR 0x0400 /* TX Frame Sync Required Select */
1039#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */
1040#define LTFS 0x1000 /* Low TX Frame Sync Select */
1041#define LATFS 0x2000 /* Late TX Frame Sync Select */
1042#define TCKFE 0x4000 /* TX Clock Falling Edge Select */
1043
1044/* SPORTx_TCR2 Masks */
1045#define SLEN 0x001F /*TX Word Length */
1046#define TXSE 0x0100 /*TX Secondary Enable */
1047#define TSFSE 0x0200 /*TX Stereo Frame Sync Enable */
1048#define TRFST 0x0400 /*TX Right-First Data Order */
1049
1050/* SPORTx_RCR1 Masks */
1051#define RSPEN 0x0001 /* RX enable */
1052#define IRCLK 0x0002 /* Internal RX Clock Select */
1053#define RDTYPE 0x000C /* RX Data Formatting Select */
1054#define RULAW 0x0008 /* u-Law enable */
1055#define RALAW 0x000C /* A-Law enable */
1056#define RLSBIT 0x0010 /* RX Bit Order */
1057#define IRFS 0x0200 /* Internal RX Frame Sync Select */
1058#define RFSR 0x0400 /* RX Frame Sync Required Select */
1059#define LRFS 0x1000 /* Low RX Frame Sync Select */
1060#define LARFS 0x2000 /* Late RX Frame Sync Select */
1061#define RCKFE 0x4000 /* RX Clock Falling Edge Select */
1062
1063/* SPORTx_RCR2 Masks */
1064#define SLEN 0x001F /*RX Word Length */
1065#define RXSE 0x0100 /*RX Secondary Enable */
1066#define RSFSE 0x0200 /*RX Stereo Frame Sync Enable */
1067#define RRFST 0x0400 /*Right-First Data Order */
1068
1069/*SPORTx_STAT Masks */
1070#define RXNE 0x0001 /*RX FIFO Not Empty Status */
1071#define RUVF 0x0002 /*RX Underflow Status */
1072#define ROVF 0x0004 /*RX Overflow Status */
1073#define TXF 0x0008 /*TX FIFO Full Status */
1074#define TUVF 0x0010 /*TX Underflow Status */
1075#define TOVF 0x0020 /*TX Overflow Status */
1076#define TXHRE 0x0040 /*TX Hold Register Empty */
1077
1078/*SPORTx_MCMC1 Masks */
1079#define SP_WSIZE 0x0000F000 /*Multichannel Window Size Field */
1080#define SP_WOFF 0x000003FF /*Multichannel Window Offset Field */
1081
1082/*SPORTx_MCMC2 Masks */
1083#define MCCRM 0x00000003 /*Multichannel Clock Recovery Mode */
1084#define MCDTXPE 0x00000004 /*Multichannel DMA Transmit Packing */
1085#define MCDRXPE 0x00000008 /*Multichannel DMA Receive Packing */
1086#define MCMEN 0x00000010 /*Multichannel Frame Mode Enable */
1087#define FSDR 0x00000080 /*Multichannel Frame Sync to Data Relationship */
1088#define MFD 0x0000F000 /*Multichannel Frame Delay */
1089
1090/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */
1091
1092/* PPI_CONTROL Masks */
1093#define PORT_EN 0x00000001 /* PPI Port Enable */
1094#define PORT_DIR 0x00000002 /* PPI Port Direction */
1095#define XFR_TYPE 0x0000000C /* PPI Transfer Type */
1096#define PORT_CFG 0x00000030 /* PPI Port Configuration */
1097#define FLD_SEL 0x00000040 /* PPI Active Field Select */
1098#define PACK_EN 0x00000080 /* PPI Packing Mode */
1099#define DMA32 0x00000100 /* PPI 32-bit DMA Enable */
1100#define SKIP_EN 0x00000200 /* PPI Skip Element Enable */
1101#define SKIP_EO 0x00000400 /* PPI Skip Even/Odd Elements */
1102#define DLENGTH 0x00003800 /* PPI Data Length */
1103#define DLEN_8 0x0 /* PPI Data Length mask for DLEN=8 */
1104#define DLEN(x) (((x-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */
1105#define POL 0x0000C000 /* PPI Signal Polarities */
1106
1107/* PPI_STATUS Masks */
1108#define FLD 0x00000400 /* Field Indicator */
1109#define FT_ERR 0x00000800 /* Frame Track Error */
1110#define OVR 0x00001000 /* FIFO Overflow Error */
1111#define UNDR 0x00002000 /* FIFO Underrun Error */
1112#define ERR_DET 0x00004000 /* Error Detected Indicator */
1113#define ERR_NCOR 0x00008000 /* Error Not Corrected Indicator */
1114
1115/* ********** DMA CONTROLLER MASKS *********************8 */
1116
1117/* DMAx_CONFIG, MDMA_yy_CONFIG, IMDMA_yy_CONFIG Masks */
1118#define DMAEN 0x00000001 /* Channel Enable */
1119#define WNR 0x00000002 /* Channel Direction (W/R*) */
1120#define WDSIZE_8 0x00000000 /* Word Size 8 bits */
1121#define WDSIZE_16 0x00000004 /* Word Size 16 bits */
1122#define WDSIZE_32 0x00000008 /* Word Size 32 bits */
1123#define DMA2D 0x00000010 /* 2D/1D* Mode */
1124#define RESTART 0x00000020 /* Restart */
1125#define DI_SEL 0x00000040 /* Data Interrupt Select */
1126#define DI_EN 0x00000080 /* Data Interrupt Enable */
1127#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
1128#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
1129#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
1130#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
1131#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
1132#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
1133#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
1134#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
1135#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
1136#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
1137#define NDSIZE 0x00000900 /* Next Descriptor Size */
1138#define DMAFLOW 0x00007000 /* Flow Control */
1139#define DMAFLOW_STOP 0x0000 /* Stop Mode */
1140#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
1141#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
1142#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
1143#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
1144
1145#define DMAEN_P 0 /* Channel Enable */
1146#define WNR_P 1 /* Channel Direction (W/R*) */
1147#define DMA2D_P 4 /* 2D/1D* Mode */
1148#define RESTART_P 5 /* Restart */
1149#define DI_SEL_P 6 /* Data Interrupt Select */
1150#define DI_EN_P 7 /* Data Interrupt Enable */
1151
1152/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS, IMDMA_yy_IRQ_STATUS Masks */
1153
1154#define DMA_DONE 0x00000001 /* DMA Done Indicator */
1155#define DMA_ERR 0x00000002 /* DMA Error Indicator */
1156#define DFETCH 0x00000004 /* Descriptor Fetch Indicator */
1157#define DMA_RUN 0x00000008 /* DMA Running Indicator */
1158
1159#define DMA_DONE_P 0 /* DMA Done Indicator */
1160#define DMA_ERR_P 1 /* DMA Error Indicator */
1161#define DFETCH_P 2 /* Descriptor Fetch Indicator */
1162#define DMA_RUN_P 3 /* DMA Running Indicator */
1163
1164/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP, IMDMA_yy_PERIPHERAL_MAP Masks */
1165
1166#define CTYPE 0x00000040 /* DMA Channel Type Indicator */
1167#define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */
1168#define PCAP8 0x00000080 /* DMA 8-bit Operation Indicator */
1169#define PCAP16 0x00000100 /* DMA 16-bit Operation Indicator */
1170#define PCAP32 0x00000200 /* DMA 32-bit Operation Indicator */
1171#define PCAPWR 0x00000400 /* DMA Write Operation Indicator */
1172#define PCAPRD 0x00000800 /* DMA Read Operation Indicator */
1173#define PMAP 0x00007000 /* DMA Peripheral Map Field */
1174
1175/* ************* GENERAL PURPOSE TIMER MASKS ******************** */
1176
1177/* PWM Timer bit definitions */
1178
1179/* TIMER_ENABLE Register */
1180#define TIMEN0 0x0001
1181#define TIMEN1 0x0002
1182#define TIMEN2 0x0004
1183#define TIMEN3 0x0008
1184#define TIMEN4 0x0010
1185#define TIMEN5 0x0020
1186#define TIMEN6 0x0040
1187#define TIMEN7 0x0080
1188#define TIMEN8 0x0001
1189#define TIMEN9 0x0002
1190#define TIMEN10 0x0004
1191#define TIMEN11 0x0008
1192
1193#define TIMEN0_P 0x00
1194#define TIMEN1_P 0x01
1195#define TIMEN2_P 0x02
1196#define TIMEN3_P 0x03
1197#define TIMEN4_P 0x04
1198#define TIMEN5_P 0x05
1199#define TIMEN6_P 0x06
1200#define TIMEN7_P 0x07
1201#define TIMEN8_P 0x00
1202#define TIMEN9_P 0x01
1203#define TIMEN10_P 0x02
1204#define TIMEN11_P 0x03
1205
1206/* TIMER_DISABLE Register */
1207#define TIMDIS0 0x0001
1208#define TIMDIS1 0x0002
1209#define TIMDIS2 0x0004
1210#define TIMDIS3 0x0008
1211#define TIMDIS4 0x0010
1212#define TIMDIS5 0x0020
1213#define TIMDIS6 0x0040
1214#define TIMDIS7 0x0080
1215#define TIMDIS8 0x0001
1216#define TIMDIS9 0x0002
1217#define TIMDIS10 0x0004
1218#define TIMDIS11 0x0008
1219
1220#define TIMDIS0_P 0x00
1221#define TIMDIS1_P 0x01
1222#define TIMDIS2_P 0x02
1223#define TIMDIS3_P 0x03
1224#define TIMDIS4_P 0x04
1225#define TIMDIS5_P 0x05
1226#define TIMDIS6_P 0x06
1227#define TIMDIS7_P 0x07
1228#define TIMDIS8_P 0x00
1229#define TIMDIS9_P 0x01
1230#define TIMDIS10_P 0x02
1231#define TIMDIS11_P 0x03
1232
1233/* TIMER_STATUS Register */
1234#define TIMIL0 0x00000001
1235#define TIMIL1 0x00000002
1236#define TIMIL2 0x00000004
1237#define TIMIL3 0x00000008
1238#define TIMIL4 0x00010000
1239#define TIMIL5 0x00020000
1240#define TIMIL6 0x00040000
1241#define TIMIL7 0x00080000
1242#define TIMIL8 0x0001
1243#define TIMIL9 0x0002
1244#define TIMIL10 0x0004
1245#define TIMIL11 0x0008
1246#define TOVF_ERR0 0x00000010
1247#define TOVF_ERR1 0x00000020
1248#define TOVF_ERR2 0x00000040
1249#define TOVF_ERR3 0x00000080
1250#define TOVF_ERR4 0x00100000
1251#define TOVF_ERR5 0x00200000
1252#define TOVF_ERR6 0x00400000
1253#define TOVF_ERR7 0x00800000
1254#define TOVF_ERR8 0x0010
1255#define TOVF_ERR9 0x0020
1256#define TOVF_ERR10 0x0040
1257#define TOVF_ERR11 0x0080
1258#define TRUN0 0x00001000
1259#define TRUN1 0x00002000
1260#define TRUN2 0x00004000
1261#define TRUN3 0x00008000
1262#define TRUN4 0x10000000
1263#define TRUN5 0x20000000
1264#define TRUN6 0x40000000
1265#define TRUN7 0x80000000
1266#define TRUN8 0x1000
1267#define TRUN9 0x2000
1268#define TRUN10 0x4000
1269#define TRUN11 0x8000
1270
1271#define TIMIL0_P 0x00
1272#define TIMIL1_P 0x01
1273#define TIMIL2_P 0x02
1274#define TIMIL3_P 0x03
1275#define TIMIL4_P 0x10
1276#define TIMIL5_P 0x11
1277#define TIMIL6_P 0x12
1278#define TIMIL7_P 0x13
1279#define TIMIL8_P 0x00
1280#define TIMIL9_P 0x01
1281#define TIMIL10_P 0x02
1282#define TIMIL11_P 0x03
1283#define TOVF_ERR0_P 0x04
1284#define TOVF_ERR1_P 0x05
1285#define TOVF_ERR2_P 0x06
1286#define TOVF_ERR3_P 0x07
1287#define TOVF_ERR4_P 0x14
1288#define TOVF_ERR5_P 0x15
1289#define TOVF_ERR6_P 0x16
1290#define TOVF_ERR7_P 0x17
1291#define TOVF_ERR8_P 0x04
1292#define TOVF_ERR9_P 0x05
1293#define TOVF_ERR10_P 0x06
1294#define TOVF_ERR11_P 0x07
1295#define TRUN0_P 0x0C
1296#define TRUN1_P 0x0D
1297#define TRUN2_P 0x0E
1298#define TRUN3_P 0x0F
1299#define TRUN4_P 0x1C
1300#define TRUN5_P 0x1D
1301#define TRUN6_P 0x1E
1302#define TRUN7_P 0x1F
1303#define TRUN8_P 0x0C
1304#define TRUN9_P 0x0D
1305#define TRUN10_P 0x0E
1306#define TRUN11_P 0x0F
1307
1308/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
1309#define TOVL_ERR0 TOVF_ERR0
1310#define TOVL_ERR1 TOVF_ERR1
1311#define TOVL_ERR2 TOVF_ERR2
1312#define TOVL_ERR3 TOVF_ERR3
1313#define TOVL_ERR4 TOVF_ERR4
1314#define TOVL_ERR5 TOVF_ERR5
1315#define TOVL_ERR6 TOVF_ERR6
1316#define TOVL_ERR7 TOVF_ERR7
1317#define TOVL_ERR8 TOVF_ERR8
1318#define TOVL_ERR9 TOVF_ERR9
1319#define TOVL_ERR10 TOVF_ERR10
1320#define TOVL_ERR11 TOVF_ERR11
1321#define TOVL_ERR0_P TOVF_ERR0_P
1322#define TOVL_ERR1_P TOVF_ERR1_P
1323#define TOVL_ERR2_P TOVF_ERR2_P
1324#define TOVL_ERR3_P TOVF_ERR3_P
1325#define TOVL_ERR4_P TOVF_ERR4_P
1326#define TOVL_ERR5_P TOVF_ERR5_P
1327#define TOVL_ERR6_P TOVF_ERR6_P
1328#define TOVL_ERR7_P TOVF_ERR7_P
1329#define TOVL_ERR8_P TOVF_ERR8_P
1330#define TOVL_ERR9_P TOVF_ERR9_P
1331#define TOVL_ERR10_P TOVF_ERR10_P
1332#define TOVL_ERR11_P TOVF_ERR11_P
1333
1334/* TIMERx_CONFIG Registers */
1335#define PWM_OUT 0x0001
1336#define WDTH_CAP 0x0002
1337#define EXT_CLK 0x0003
1338#define PULSE_HI 0x0004
1339#define PERIOD_CNT 0x0008
1340#define IRQ_ENA 0x0010
1341#define TIN_SEL 0x0020
1342#define OUT_DIS 0x0040
1343#define CLK_SEL 0x0080
1344#define TOGGLE_HI 0x0100
1345#define EMU_RUN 0x0200
1346#define ERR_TYP(x) ((x & 0x03) << 14)
1347
1348#define TMODE_P0 0x00
1349#define TMODE_P1 0x01
1350#define PULSE_HI_P 0x02
1351#define PERIOD_CNT_P 0x03
1352#define IRQ_ENA_P 0x04
1353#define TIN_SEL_P 0x05
1354#define OUT_DIS_P 0x06
1355#define CLK_SEL_P 0x07
1356#define TOGGLE_HI_P 0x08
1357#define EMU_RUN_P 0x09
1358#define ERR_TYP_P0 0x0E
1359#define ERR_TYP_P1 0x0F
1360
1361/*/ ****************** PROGRAMMABLE FLAG MASKS ********************* */
1362
1363/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */
1364#define PF0 0x0001
1365#define PF1 0x0002
1366#define PF2 0x0004
1367#define PF3 0x0008
1368#define PF4 0x0010
1369#define PF5 0x0020
1370#define PF6 0x0040
1371#define PF7 0x0080
1372#define PF8 0x0100
1373#define PF9 0x0200
1374#define PF10 0x0400
1375#define PF11 0x0800
1376#define PF12 0x1000
1377#define PF13 0x2000
1378#define PF14 0x4000
1379#define PF15 0x8000
1380
1381/* General Purpose IO (0xFFC00700 - 0xFFC007FF) BIT POSITIONS */
1382#define PF0_P 0
1383#define PF1_P 1
1384#define PF2_P 2
1385#define PF3_P 3
1386#define PF4_P 4
1387#define PF5_P 5
1388#define PF6_P 6
1389#define PF7_P 7
1390#define PF8_P 8
1391#define PF9_P 9
1392#define PF10_P 10
1393#define PF11_P 11
1394#define PF12_P 12
1395#define PF13_P 13
1396#define PF14_P 14
1397#define PF15_P 15
1398
1399/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS **************** */
1400
1401/* SPI_CTL Masks */
1402#define TIMOD 0x00000003 /* Transfer initiation mode and interrupt generation */
1403#define SZ 0x00000004 /* Send Zero (=0) or last (=1) word when TDBR empty. */
1404#define GM 0x00000008 /* When RDBR full, get more (=1) data or discard (=0) incoming Data */
1405#define PSSE 0x00000010 /* Enable (=1) Slave-Select input for Master. */
1406#define EMISO 0x00000020 /* Enable (=1) MISO pin as an output. */
1407#define SIZE 0x00000100 /* Word length (0 => 8 bits, 1 => 16 bits) */
1408#define LSBF 0x00000200 /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */
1409#define CPHA 0x00000400 /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */
1410#define CPOL 0x00000800 /* Clock polarity (0 => active-high, 1 => active-low) */
1411#define MSTR 0x00001000 /* Configures SPI as master (=1) or slave (=0) */
1412#define WOM 0x00002000 /* Open drain (=1) data output enable (for MOSI and MISO) */
1413#define SPE 0x00004000 /* SPI module enable (=1), disable (=0) */
1414
1415/* SPI_FLG Masks */
1416#define FLS1 0x00000002 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
1417#define FLS2 0x00000004 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
1418#define FLS3 0x00000008 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
1419#define FLS4 0x00000010 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
1420#define FLS5 0x00000020 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
1421#define FLS6 0x00000040 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
1422#define FLS7 0x00000080 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
1423#define FLG1 0x00000200 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
1424#define FLG2 0x00000400 /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
1425#define FLG3 0x00000800 /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
1426#define FLG4 0x00001000 /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
1427#define FLG5 0x00002000 /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
1428#define FLG6 0x00004000 /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
1429#define FLG7 0x00008000 /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
1430
1431/* SPI_FLG Bit Positions */
1432#define FLS1_P 0x00000001 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
1433#define FLS2_P 0x00000002 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
1434#define FLS3_P 0x00000003 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
1435#define FLS4_P 0x00000004 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
1436#define FLS5_P 0x00000005 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
1437#define FLS6_P 0x00000006 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
1438#define FLS7_P 0x00000007 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
1439#define FLG1_P 0x00000009 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
1440#define FLG2_P 0x0000000A /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
1441#define FLG3_P 0x0000000B /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
1442#define FLG4_P 0x0000000C /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
1443#define FLG5_P 0x0000000D /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
1444#define FLG6_P 0x0000000E /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
1445#define FLG7_P 0x0000000F /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
1446
1447/* SPI_STAT Masks */
1448#define SPIF 0x00000001 /* Set (=1) when SPI single-word transfer complete */
1449#define MODF 0x00000002 /* Set (=1) in a master device when some other device tries to become master */
1450#define TXE 0x00000004 /* Set (=1) when transmission occurs with no new data in SPI_TDBR */
1451#define TXS 0x00000008 /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */
1452#define RBSY 0x00000010 /* Set (=1) when data is received with RDBR full */
1453#define RXS 0x00000020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */
1454#define TXCOL 0x00000040 /* When set (=1), corrupt data may have been transmitted */
1455
1456/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */
1457
1458/* AMGCTL Masks */
1459#define AMCKEN 0x0001 /* Enable CLKOUT */
1460#define AMBEN_B0 0x0002 /* Enable Asynchronous Memory Bank 0 only */
1461#define AMBEN_B0_B1 0x0004 /* Enable Asynchronous Memory Banks 0 & 1 only */
1462#define AMBEN_B0_B1_B2 0x0006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */
1463#define AMBEN_ALL 0x0008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
1464#define B0_PEN 0x0010 /* Enable 16-bit packing Bank 0 */
1465#define B1_PEN 0x0020 /* Enable 16-bit packing Bank 1 */
1466#define B2_PEN 0x0040 /* Enable 16-bit packing Bank 2 */
1467#define B3_PEN 0x0080 /* Enable 16-bit packing Bank 3 */
1468
1469/* AMGCTL Bit Positions */
1470#define AMCKEN_P 0x00000000 /* Enable CLKOUT */
1471#define AMBEN_P0 0x00000001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
1472#define AMBEN_P1 0x00000002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */
1473#define AMBEN_P2 0x00000003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
1474#define B0_PEN_P 0x004 /* Enable 16-bit packing Bank 0 */
1475#define B1_PEN_P 0x005 /* Enable 16-bit packing Bank 1 */
1476#define B2_PEN_P 0x006 /* Enable 16-bit packing Bank 2 */
1477#define B3_PEN_P 0x007 /* Enable 16-bit packing Bank 3 */
1478
1479/* AMBCTL0 Masks */
1480#define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */
1481#define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */
1482#define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */
1483#define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */
1484#define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */
1485#define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */
1486#define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
1487#define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
1488#define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
1489#define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
1490#define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
1491#define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
1492#define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
1493#define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
1494#define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */
1495#define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */
1496#define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */
1497#define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */
1498#define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */
1499#define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */
1500#define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */
1501#define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */
1502#define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */
1503#define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */
1504#define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */
1505#define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */
1506#define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */
1507#define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */
1508#define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */
1509#define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */
1510#define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */
1511#define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */
1512#define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */
1513#define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */
1514#define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */
1515#define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */
1516#define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */
1517#define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */
1518#define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */
1519#define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */
1520#define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */
1521#define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */
1522#define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */
1523#define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */
1524#define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */
1525#define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */
1526#define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */
1527#define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */
1528#define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */
1529#define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */
1530#define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
1531#define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
1532#define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
1533#define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
1534#define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
1535#define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
1536#define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
1537#define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
1538#define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */
1539#define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */
1540#define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */
1541#define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */
1542#define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */
1543#define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */
1544#define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */
1545#define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */
1546#define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */
1547#define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */
1548#define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */
1549#define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */
1550#define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */
1551#define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */
1552#define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */
1553#define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */
1554#define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */
1555#define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */
1556#define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */
1557#define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */
1558#define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */
1559#define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */
1560#define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */
1561#define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */
1562#define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */
1563#define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */
1564#define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */
1565#define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */
1566#define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */
1567#define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */
1568
1569/* AMBCTL1 Masks */
1570#define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */
1571#define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */
1572#define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */
1573#define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */
1574#define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */
1575#define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */
1576#define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
1577#define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
1578#define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
1579#define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
1580#define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
1581#define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
1582#define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
1583#define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
1584#define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */
1585#define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */
1586#define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */
1587#define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */
1588#define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */
1589#define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */
1590#define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */
1591#define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */
1592#define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */
1593#define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */
1594#define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */
1595#define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */
1596#define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */
1597#define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */
1598#define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */
1599#define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */
1600#define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */
1601#define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */
1602#define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */
1603#define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */
1604#define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */
1605#define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */
1606#define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */
1607#define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */
1608#define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */
1609#define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */
1610#define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */
1611#define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */
1612#define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */
1613#define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */
1614#define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */
1615#define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */
1616#define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */
1617#define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */
1618#define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */
1619#define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */
1620#define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
1621#define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
1622#define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
1623#define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
1624#define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
1625#define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
1626#define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
1627#define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
1628#define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */
1629#define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */
1630#define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */
1631#define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */
1632#define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */
1633#define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */
1634#define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */
1635#define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */
1636#define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */
1637#define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */
1638#define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */
1639#define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */
1640#define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */
1641#define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */
1642#define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */
1643#define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */
1644#define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */
1645#define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */
1646#define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */
1647#define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */
1648#define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */
1649#define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */
1650#define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */
1651#define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */
1652#define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */
1653#define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */
1654#define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */
1655#define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */
1656#define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */
1657#define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */
1658
1659/* ********************** SDRAM CONTROLLER MASKS *************************** */
1660
1661/* EBIU_SDGCTL Masks */
1662#define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
1663#define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */
1664#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */
1665#define PFE 0x00000010 /* Enable SDRAM prefetch */
1666#define PFP 0x00000020 /* Prefetch has priority over AMC requests */
1667#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
1668#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
1669#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
1670#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
1671#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
1672#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
1673#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
1674#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
1675#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
1676#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
1677#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
1678#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
1679#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
1680#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
1681#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
1682#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
1683#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
1684#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
1685#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
1686#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
1687#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
1688#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
1689#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
1690#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
1691#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
1692#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
1693#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
1694#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
1695#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
1696#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
1697#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
1698#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
1699#define PUPSD 0x00200000 /*Power-up start delay */
1700#define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
1701#define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */
1702#define SRFS 0x01000000 /* Start SDRAM self-refresh mode */
1703#define EBUFE 0x02000000 /* Enable external buffering timing */
1704#define FBBRW 0x04000000 /* Fast back-to-back read write enable */
1705#define EMREN 0x10000000 /* Extended mode register enable */
1706#define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */
1707#define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */
1708
1709/* EBIU_SDBCTL Masks */
1710#define EB0_E 0x00000001 /* Enable SDRAM external bank 0 */
1711#define EB0_SZ_16 0x00000000 /* SDRAM external bank size = 16MB */
1712#define EB0_SZ_32 0x00000002 /* SDRAM external bank size = 32MB */
1713#define EB0_SZ_64 0x00000004 /* SDRAM external bank size = 64MB */
1714#define EB0_SZ_128 0x00000006 /* SDRAM external bank size = 128MB */
1715#define EB0_CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
1716#define EB0_CAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */
1717#define EB0_CAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */
1718#define EB0_CAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */
1719
1720#define EB1_E 0x00000100 /* Enable SDRAM external bank 1 */
1721#define EB1__SZ_16 0x00000000 /* SDRAM external bank size = 16MB */
1722#define EB1__SZ_32 0x00000200 /* SDRAM external bank size = 32MB */
1723#define EB1__SZ_64 0x00000400 /* SDRAM external bank size = 64MB */
1724#define EB1__SZ_128 0x00000600 /* SDRAM external bank size = 128MB */
1725#define EB1__CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
1726#define EB1__CAW_9 0x00001000 /* SDRAM external bank column address width = 9 bits */
1727#define EB1__CAW_10 0x00002000 /* SDRAM external bank column address width = 9 bits */
1728#define EB1__CAW_11 0x00003000 /* SDRAM external bank column address width = 9 bits */
1729
1730#define EB2__E 0x00010000 /* Enable SDRAM external bank 2 */
1731#define EB2__SZ_16 0x00000000 /* SDRAM external bank size = 16MB */
1732#define EB2__SZ_32 0x00020000 /* SDRAM external bank size = 32MB */
1733#define EB2__SZ_64 0x00040000 /* SDRAM external bank size = 64MB */
1734#define EB2__SZ_128 0x00060000 /* SDRAM external bank size = 128MB */
1735#define EB2__CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
1736#define EB2__CAW_9 0x00100000 /* SDRAM external bank column address width = 9 bits */
1737#define EB2__CAW_10 0x00200000 /* SDRAM external bank column address width = 9 bits */
1738#define EB2__CAW_11 0x00300000 /* SDRAM external bank column address width = 9 bits */
1739
1740#define EB3__E 0x01000000 /* Enable SDRAM external bank 3 */
1741#define EB3__SZ_16 0x00000000 /* SDRAM external bank size = 16MB */
1742#define EB3__SZ_32 0x02000000 /* SDRAM external bank size = 32MB */
1743#define EB3__SZ_64 0x04000000 /* SDRAM external bank size = 64MB */
1744#define EB3__SZ_128 0x06000000 /* SDRAM external bank size = 128MB */
1745#define EB3__CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
1746#define EB3__CAW_9 0x10000000 /* SDRAM external bank column address width = 9 bits */
1747#define EB3__CAW_10 0x20000000 /* SDRAM external bank column address width = 9 bits */
1748#define EB3__CAW_11 0x30000000 /* SDRAM external bank column address width = 9 bits */
1749
1750/* EBIU_SDSTAT Masks */
1751#define SDCI 0x00000001 /* SDRAM controller is idle */
1752#define SDSRA 0x00000002 /* SDRAM SDRAM self refresh is active */
1753#define SDPUA 0x00000004 /* SDRAM power up active */
1754#define SDRS 0x00000008 /* SDRAM is in reset state */
1755#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */
1756#define BGSTAT 0x00000020 /* Bus granted */
1757
1758#endif /* _DEF_BF561_H */
diff --git a/arch/blackfin/mach-bf561/include/mach/dma.h b/arch/blackfin/mach-bf561/include/mach/dma.h
new file mode 100644
index 000000000000..8bc46cd89a02
--- /dev/null
+++ b/arch/blackfin/mach-bf561/include/mach/dma.h
@@ -0,0 +1,35 @@
1/*****************************************************************************
2*
3* BF-533/2/1 Specific Declarations
4*
5****************************************************************************/
6
7#ifndef _MACH_DMA_H_
8#define _MACH_DMA_H_
9
10#define MAX_BLACKFIN_DMA_CHANNEL 36
11
12#define CH_PPI0 0
13#define CH_PPI (CH_PPI0)
14#define CH_PPI1 1
15#define CH_SPORT0_RX 12
16#define CH_SPORT0_TX 13
17#define CH_SPORT1_RX 14
18#define CH_SPORT1_TX 15
19#define CH_SPI 16
20#define CH_UART_RX 17
21#define CH_UART_TX 18
22#define CH_MEM_STREAM0_DEST 24 /* TX */
23#define CH_MEM_STREAM0_SRC 25 /* RX */
24#define CH_MEM_STREAM1_DEST 26 /* TX */
25#define CH_MEM_STREAM1_SRC 27 /* RX */
26#define CH_MEM_STREAM2_DEST 28
27#define CH_MEM_STREAM2_SRC 29
28#define CH_MEM_STREAM3_DEST 30
29#define CH_MEM_STREAM3_SRC 31
30#define CH_IMEM_STREAM0_DEST 32
31#define CH_IMEM_STREAM0_SRC 33
32#define CH_IMEM_STREAM1_DEST 34
33#define CH_IMEM_STREAM1_SRC 35
34
35#endif
diff --git a/arch/blackfin/mach-bf561/include/mach/irq.h b/arch/blackfin/mach-bf561/include/mach/irq.h
new file mode 100644
index 000000000000..6698389c5564
--- /dev/null
+++ b/arch/blackfin/mach-bf561/include/mach/irq.h
@@ -0,0 +1,447 @@
1
2/*
3 * File: include/asm-blackfin/mach-bf561/irq.h
4 * Based on:
5 * Author:
6 *
7 * Created:
8 * Description:
9 *
10 * Rev:
11 *
12 * Modified:
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#ifndef _BF561_IRQ_H_
33#define _BF561_IRQ_H_
34
35/***********************************************************************
36 * Interrupt source definitions:
37 Event Source Core Event Name IRQ No
38 (highest priority)
39 Emulation Events EMU 0
40 Reset RST 1
41 NMI NMI 2
42 Exception EVX 3
43 Reserved -- 4
44 Hardware Error IVHW 5
45 Core Timer IVTMR 6 *
46
47 PLL Wakeup Interrupt IVG7 7
48 DMA1 Error (generic) IVG7 8
49 DMA2 Error (generic) IVG7 9
50 IMDMA Error (generic) IVG7 10
51 PPI1 Error Interrupt IVG7 11
52 PPI2 Error Interrupt IVG7 12
53 SPORT0 Error Interrupt IVG7 13
54 SPORT1 Error Interrupt IVG7 14
55 SPI Error Interrupt IVG7 15
56 UART Error Interrupt IVG7 16
57 Reserved Interrupt IVG7 17
58
59 DMA1 0 Interrupt(PPI1) IVG8 18
60 DMA1 1 Interrupt(PPI2) IVG8 19
61 DMA1 2 Interrupt IVG8 20
62 DMA1 3 Interrupt IVG8 21
63 DMA1 4 Interrupt IVG8 22
64 DMA1 5 Interrupt IVG8 23
65 DMA1 6 Interrupt IVG8 24
66 DMA1 7 Interrupt IVG8 25
67 DMA1 8 Interrupt IVG8 26
68 DMA1 9 Interrupt IVG8 27
69 DMA1 10 Interrupt IVG8 28
70 DMA1 11 Interrupt IVG8 29
71
72 DMA2 0 (SPORT0 RX) IVG9 30
73 DMA2 1 (SPORT0 TX) IVG9 31
74 DMA2 2 (SPORT1 RX) IVG9 32
75 DMA2 3 (SPORT2 TX) IVG9 33
76 DMA2 4 (SPI) IVG9 34
77 DMA2 5 (UART RX) IVG9 35
78 DMA2 6 (UART TX) IVG9 36
79 DMA2 7 Interrupt IVG9 37
80 DMA2 8 Interrupt IVG9 38
81 DMA2 9 Interrupt IVG9 39
82 DMA2 10 Interrupt IVG9 40
83 DMA2 11 Interrupt IVG9 41
84
85 TIMER 0 Interrupt IVG10 42
86 TIMER 1 Interrupt IVG10 43
87 TIMER 2 Interrupt IVG10 44
88 TIMER 3 Interrupt IVG10 45
89 TIMER 4 Interrupt IVG10 46
90 TIMER 5 Interrupt IVG10 47
91 TIMER 6 Interrupt IVG10 48
92 TIMER 7 Interrupt IVG10 49
93 TIMER 8 Interrupt IVG10 50
94 TIMER 9 Interrupt IVG10 51
95 TIMER 10 Interrupt IVG10 52
96 TIMER 11 Interrupt IVG10 53
97
98 Programmable Flags0 A (8) IVG11 54
99 Programmable Flags0 B (8) IVG11 55
100 Programmable Flags1 A (8) IVG11 56
101 Programmable Flags1 B (8) IVG11 57
102 Programmable Flags2 A (8) IVG11 58
103 Programmable Flags2 B (8) IVG11 59
104
105 MDMA1 0 write/read INT IVG8 60
106 MDMA1 1 write/read INT IVG8 61
107
108 MDMA2 0 write/read INT IVG9 62
109 MDMA2 1 write/read INT IVG9 63
110
111 IMDMA 0 write/read INT IVG12 64
112 IMDMA 1 write/read INT IVG12 65
113
114 Watch Dog Timer IVG13 66
115
116 Reserved interrupt IVG7 67
117 Reserved interrupt IVG7 68
118 Supplemental interrupt 0 IVG7 69
119 supplemental interrupt 1 IVG7 70
120
121 Softirq IVG14
122 System Call --
123 (lowest priority) IVG15
124
125 **********************************************************************/
126
127#define SYS_IRQS 71
128#define NR_PERI_INTS 64
129
130/*
131 * The ABSTRACT IRQ definitions
132 * the first seven of the following are fixed,
133 * the rest you change if you need to.
134 */
135/* IVG 0-6*/
136#define IRQ_EMU 0 /* Emulation */
137#define IRQ_RST 1 /* Reset */
138#define IRQ_NMI 2 /* Non Maskable Interrupt */
139#define IRQ_EVX 3 /* Exception */
140#define IRQ_UNUSED 4 /* Reserved interrupt */
141#define IRQ_HWERR 5 /* Hardware Error */
142#define IRQ_CORETMR 6 /* Core timer */
143
144#define IVG_BASE 7
145/* IVG 7 */
146#define IRQ_PLL_WAKEUP (IVG_BASE + 0) /* PLL Wakeup Interrupt */
147#define IRQ_DMA1_ERROR (IVG_BASE + 1) /* DMA1 Error (general) */
148#define IRQ_DMA_ERROR IRQ_DMA1_ERROR /* DMA1 Error (general) */
149#define IRQ_DMA2_ERROR (IVG_BASE + 2) /* DMA2 Error (general) */
150#define IRQ_IMDMA_ERROR (IVG_BASE + 3) /* IMDMA Error Interrupt */
151#define IRQ_PPI1_ERROR (IVG_BASE + 4) /* PPI1 Error Interrupt */
152#define IRQ_PPI_ERROR IRQ_PPI1_ERROR /* PPI1 Error Interrupt */
153#define IRQ_PPI2_ERROR (IVG_BASE + 5) /* PPI2 Error Interrupt */
154#define IRQ_SPORT0_ERROR (IVG_BASE + 6) /* SPORT0 Error Interrupt */
155#define IRQ_SPORT1_ERROR (IVG_BASE + 7) /* SPORT1 Error Interrupt */
156#define IRQ_SPI_ERROR (IVG_BASE + 8) /* SPI Error Interrupt */
157#define IRQ_UART_ERROR (IVG_BASE + 9) /* UART Error Interrupt */
158#define IRQ_RESERVED_ERROR (IVG_BASE + 10) /* Reversed Interrupt */
159/* IVG 8 */
160#define IRQ_DMA1_0 (IVG_BASE + 11) /* DMA1 0 Interrupt(PPI1) */
161#define IRQ_PPI IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */
162#define IRQ_PPI0 IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */
163#define IRQ_DMA1_1 (IVG_BASE + 12) /* DMA1 1 Interrupt(PPI2) */
164#define IRQ_PPI1 IRQ_DMA1_1 /* DMA1 1 Interrupt(PPI2) */
165#define IRQ_DMA1_2 (IVG_BASE + 13) /* DMA1 2 Interrupt */
166#define IRQ_DMA1_3 (IVG_BASE + 14) /* DMA1 3 Interrupt */
167#define IRQ_DMA1_4 (IVG_BASE + 15) /* DMA1 4 Interrupt */
168#define IRQ_DMA1_5 (IVG_BASE + 16) /* DMA1 5 Interrupt */
169#define IRQ_DMA1_6 (IVG_BASE + 17) /* DMA1 6 Interrupt */
170#define IRQ_DMA1_7 (IVG_BASE + 18) /* DMA1 7 Interrupt */
171#define IRQ_DMA1_8 (IVG_BASE + 19) /* DMA1 8 Interrupt */
172#define IRQ_DMA1_9 (IVG_BASE + 20) /* DMA1 9 Interrupt */
173#define IRQ_DMA1_10 (IVG_BASE + 21) /* DMA1 10 Interrupt */
174#define IRQ_DMA1_11 (IVG_BASE + 22) /* DMA1 11 Interrupt */
175/* IVG 9 */
176#define IRQ_DMA2_0 (IVG_BASE + 23) /* DMA2 0 (SPORT0 RX) */
177#define IRQ_SPORT0_RX IRQ_DMA2_0 /* DMA2 0 (SPORT0 RX) */
178#define IRQ_DMA2_1 (IVG_BASE + 24) /* DMA2 1 (SPORT0 TX) */
179#define IRQ_SPORT0_TX IRQ_DMA2_1 /* DMA2 1 (SPORT0 TX) */
180#define IRQ_DMA2_2 (IVG_BASE + 25) /* DMA2 2 (SPORT1 RX) */
181#define IRQ_SPORT1_RX IRQ_DMA2_2 /* DMA2 2 (SPORT1 RX) */
182#define IRQ_DMA2_3 (IVG_BASE + 26) /* DMA2 3 (SPORT2 TX) */
183#define IRQ_SPORT1_TX IRQ_DMA2_3 /* DMA2 3 (SPORT2 TX) */
184#define IRQ_DMA2_4 (IVG_BASE + 27) /* DMA2 4 (SPI) */
185#define IRQ_SPI IRQ_DMA2_4 /* DMA2 4 (SPI) */
186#define IRQ_DMA2_5 (IVG_BASE + 28) /* DMA2 5 (UART RX) */
187#define IRQ_UART_RX IRQ_DMA2_5 /* DMA2 5 (UART RX) */
188#define IRQ_DMA2_6 (IVG_BASE + 29) /* DMA2 6 (UART TX) */
189#define IRQ_UART_TX IRQ_DMA2_6 /* DMA2 6 (UART TX) */
190#define IRQ_DMA2_7 (IVG_BASE + 30) /* DMA2 7 Interrupt */
191#define IRQ_DMA2_8 (IVG_BASE + 31) /* DMA2 8 Interrupt */
192#define IRQ_DMA2_9 (IVG_BASE + 32) /* DMA2 9 Interrupt */
193#define IRQ_DMA2_10 (IVG_BASE + 33) /* DMA2 10 Interrupt */
194#define IRQ_DMA2_11 (IVG_BASE + 34) /* DMA2 11 Interrupt */
195/* IVG 10 */
196#define IRQ_TIMER0 (IVG_BASE + 35) /* TIMER 0 Interrupt */
197#define IRQ_TIMER1 (IVG_BASE + 36) /* TIMER 1 Interrupt */
198#define IRQ_TIMER2 (IVG_BASE + 37) /* TIMER 2 Interrupt */
199#define IRQ_TIMER3 (IVG_BASE + 38) /* TIMER 3 Interrupt */
200#define IRQ_TIMER4 (IVG_BASE + 39) /* TIMER 4 Interrupt */
201#define IRQ_TIMER5 (IVG_BASE + 40) /* TIMER 5 Interrupt */
202#define IRQ_TIMER6 (IVG_BASE + 41) /* TIMER 6 Interrupt */
203#define IRQ_TIMER7 (IVG_BASE + 42) /* TIMER 7 Interrupt */
204#define IRQ_TIMER8 (IVG_BASE + 43) /* TIMER 8 Interrupt */
205#define IRQ_TIMER9 (IVG_BASE + 44) /* TIMER 9 Interrupt */
206#define IRQ_TIMER10 (IVG_BASE + 45) /* TIMER 10 Interrupt */
207#define IRQ_TIMER11 (IVG_BASE + 46) /* TIMER 11 Interrupt */
208/* IVG 11 */
209#define IRQ_PROG0_INTA (IVG_BASE + 47) /* Programmable Flags0 A (8) */
210#define IRQ_PROG_INTA IRQ_PROG0_INTA /* Programmable Flags0 A (8) */
211#define IRQ_PROG0_INTB (IVG_BASE + 48) /* Programmable Flags0 B (8) */
212#define IRQ_PROG_INTB IRQ_PROG0_INTB /* Programmable Flags0 B (8) */
213#define IRQ_PROG1_INTA (IVG_BASE + 49) /* Programmable Flags1 A (8) */
214#define IRQ_PROG1_INTB (IVG_BASE + 50) /* Programmable Flags1 B (8) */
215#define IRQ_PROG2_INTA (IVG_BASE + 51) /* Programmable Flags2 A (8) */
216#define IRQ_PROG2_INTB (IVG_BASE + 52) /* Programmable Flags2 B (8) */
217/* IVG 8 */
218#define IRQ_DMA1_WRRD0 (IVG_BASE + 53) /* MDMA1 0 write/read INT */
219#define IRQ_DMA_WRRD0 IRQ_DMA1_WRRD0 /* MDMA1 0 write/read INT */
220#define IRQ_MEM_DMA0 IRQ_DMA1_WRRD0
221#define IRQ_DMA1_WRRD1 (IVG_BASE + 54) /* MDMA1 1 write/read INT */
222#define IRQ_DMA_WRRD1 IRQ_DMA1_WRRD1 /* MDMA1 1 write/read INT */
223#define IRQ_MEM_DMA1 IRQ_DMA1_WRRD1
224/* IVG 9 */
225#define IRQ_DMA2_WRRD0 (IVG_BASE + 55) /* MDMA2 0 write/read INT */
226#define IRQ_MEM_DMA2 IRQ_DMA2_WRRD0
227#define IRQ_DMA2_WRRD1 (IVG_BASE + 56) /* MDMA2 1 write/read INT */
228#define IRQ_MEM_DMA3 IRQ_DMA2_WRRD1
229/* IVG 12 */
230#define IRQ_IMDMA_WRRD0 (IVG_BASE + 57) /* IMDMA 0 write/read INT */
231#define IRQ_IMEM_DMA0 IRQ_IMDMA_WRRD0
232#define IRQ_IMDMA_WRRD1 (IVG_BASE + 58) /* IMDMA 1 write/read INT */
233#define IRQ_IMEM_DMA1 IRQ_IMDMA_WRRD1
234/* IVG 13 */
235#define IRQ_WATCH (IVG_BASE + 59) /* Watch Dog Timer */
236/* IVG 7 */
237#define IRQ_RESERVED_1 (IVG_BASE + 60) /* Reserved interrupt */
238#define IRQ_RESERVED_2 (IVG_BASE + 61) /* Reserved interrupt */
239#define IRQ_SUPPLE_0 (IVG_BASE + 62) /* Supplemental interrupt 0 */
240#define IRQ_SUPPLE_1 (IVG_BASE + 63) /* supplemental interrupt 1 */
241
242#define IRQ_PF0 73
243#define IRQ_PF1 74
244#define IRQ_PF2 75
245#define IRQ_PF3 76
246#define IRQ_PF4 77
247#define IRQ_PF5 78
248#define IRQ_PF6 79
249#define IRQ_PF7 80
250#define IRQ_PF8 81
251#define IRQ_PF9 82
252#define IRQ_PF10 83
253#define IRQ_PF11 84
254#define IRQ_PF12 85
255#define IRQ_PF13 86
256#define IRQ_PF14 87
257#define IRQ_PF15 88
258#define IRQ_PF16 89
259#define IRQ_PF17 90
260#define IRQ_PF18 91
261#define IRQ_PF19 92
262#define IRQ_PF20 93
263#define IRQ_PF21 94
264#define IRQ_PF22 95
265#define IRQ_PF23 96
266#define IRQ_PF24 97
267#define IRQ_PF25 98
268#define IRQ_PF26 99
269#define IRQ_PF27 100
270#define IRQ_PF28 101
271#define IRQ_PF29 102
272#define IRQ_PF30 103
273#define IRQ_PF31 104
274#define IRQ_PF32 105
275#define IRQ_PF33 106
276#define IRQ_PF34 107
277#define IRQ_PF35 108
278#define IRQ_PF36 109
279#define IRQ_PF37 110
280#define IRQ_PF38 111
281#define IRQ_PF39 112
282#define IRQ_PF40 113
283#define IRQ_PF41 114
284#define IRQ_PF42 115
285#define IRQ_PF43 116
286#define IRQ_PF44 117
287#define IRQ_PF45 118
288#define IRQ_PF46 119
289#define IRQ_PF47 120
290
291#define GPIO_IRQ_BASE IRQ_PF0
292
293#define NR_IRQS (IRQ_PF47 + 1)
294
295#define IVG7 7
296#define IVG8 8
297#define IVG9 9
298#define IVG10 10
299#define IVG11 11
300#define IVG12 12
301#define IVG13 13
302#define IVG14 14
303#define IVG15 15
304
305/*
306 * DEFAULT PRIORITIES:
307 */
308
309#define CONFIG_DEF_PLL_WAKEUP 7
310#define CONFIG_DEF_DMA1_ERROR 7
311#define CONFIG_DEF_DMA2_ERROR 7
312#define CONFIG_DEF_IMDMA_ERROR 7
313#define CONFIG_DEF_PPI1_ERROR 7
314#define CONFIG_DEF_PPI2_ERROR 7
315#define CONFIG_DEF_SPORT0_ERROR 7
316#define CONFIG_DEF_SPORT1_ERROR 7
317#define CONFIG_DEF_SPI_ERROR 7
318#define CONFIG_DEF_UART_ERROR 7
319#define CONFIG_DEF_RESERVED_ERROR 7
320#define CONFIG_DEF_DMA1_0 8
321#define CONFIG_DEF_DMA1_1 8
322#define CONFIG_DEF_DMA1_2 8
323#define CONFIG_DEF_DMA1_3 8
324#define CONFIG_DEF_DMA1_4 8
325#define CONFIG_DEF_DMA1_5 8
326#define CONFIG_DEF_DMA1_6 8
327#define CONFIG_DEF_DMA1_7 8
328#define CONFIG_DEF_DMA1_8 8
329#define CONFIG_DEF_DMA1_9 8
330#define CONFIG_DEF_DMA1_10 8
331#define CONFIG_DEF_DMA1_11 8
332#define CONFIG_DEF_DMA2_0 9
333#define CONFIG_DEF_DMA2_1 9
334#define CONFIG_DEF_DMA2_2 9
335#define CONFIG_DEF_DMA2_3 9
336#define CONFIG_DEF_DMA2_4 9
337#define CONFIG_DEF_DMA2_5 9
338#define CONFIG_DEF_DMA2_6 9
339#define CONFIG_DEF_DMA2_7 9
340#define CONFIG_DEF_DMA2_8 9
341#define CONFIG_DEF_DMA2_9 9
342#define CONFIG_DEF_DMA2_10 9
343#define CONFIG_DEF_DMA2_11 9
344#define CONFIG_DEF_TIMER0 10
345#define CONFIG_DEF_TIMER1 10
346#define CONFIG_DEF_TIMER2 10
347#define CONFIG_DEF_TIMER3 10
348#define CONFIG_DEF_TIMER4 10
349#define CONFIG_DEF_TIMER5 10
350#define CONFIG_DEF_TIMER6 10
351#define CONFIG_DEF_TIMER7 10
352#define CONFIG_DEF_TIMER8 10
353#define CONFIG_DEF_TIMER9 10
354#define CONFIG_DEF_TIMER10 10
355#define CONFIG_DEF_TIMER11 10
356#define CONFIG_DEF_PROG0_INTA 11
357#define CONFIG_DEF_PROG0_INTB 11
358#define CONFIG_DEF_PROG1_INTA 11
359#define CONFIG_DEF_PROG1_INTB 11
360#define CONFIG_DEF_PROG2_INTA 11
361#define CONFIG_DEF_PROG2_INTB 11
362#define CONFIG_DEF_DMA1_WRRD0 8
363#define CONFIG_DEF_DMA1_WRRD1 8
364#define CONFIG_DEF_DMA2_WRRD0 9
365#define CONFIG_DEF_DMA2_WRRD1 9
366#define CONFIG_DEF_IMDMA_WRRD0 12
367#define CONFIG_DEF_IMDMA_WRRD1 12
368#define CONFIG_DEF_WATCH 13
369#define CONFIG_DEF_RESERVED_1 7
370#define CONFIG_DEF_RESERVED_2 7
371#define CONFIG_DEF_SUPPLE_0 7
372#define CONFIG_DEF_SUPPLE_1 7
373
374/* IAR0 BIT FIELDS */
375#define IRQ_PLL_WAKEUP_POS 0
376#define IRQ_DMA1_ERROR_POS 4
377#define IRQ_DMA2_ERROR_POS 8
378#define IRQ_IMDMA_ERROR_POS 12
379#define IRQ_PPI0_ERROR_POS 16
380#define IRQ_PPI1_ERROR_POS 20
381#define IRQ_SPORT0_ERROR_POS 24
382#define IRQ_SPORT1_ERROR_POS 28
383/* IAR1 BIT FIELDS */
384#define IRQ_SPI_ERROR_POS 0
385#define IRQ_UART_ERROR_POS 4
386#define IRQ_RESERVED_ERROR_POS 8
387#define IRQ_DMA1_0_POS 12
388#define IRQ_DMA1_1_POS 16
389#define IRQ_DMA1_2_POS 20
390#define IRQ_DMA1_3_POS 24
391#define IRQ_DMA1_4_POS 28
392/* IAR2 BIT FIELDS */
393#define IRQ_DMA1_5_POS 0
394#define IRQ_DMA1_6_POS 4
395#define IRQ_DMA1_7_POS 8
396#define IRQ_DMA1_8_POS 12
397#define IRQ_DMA1_9_POS 16
398#define IRQ_DMA1_10_POS 20
399#define IRQ_DMA1_11_POS 24
400#define IRQ_DMA2_0_POS 28
401/* IAR3 BIT FIELDS */
402#define IRQ_DMA2_1_POS 0
403#define IRQ_DMA2_2_POS 4
404#define IRQ_DMA2_3_POS 8
405#define IRQ_DMA2_4_POS 12
406#define IRQ_DMA2_5_POS 16
407#define IRQ_DMA2_6_POS 20
408#define IRQ_DMA2_7_POS 24
409#define IRQ_DMA2_8_POS 28
410/* IAR4 BIT FIELDS */
411#define IRQ_DMA2_9_POS 0
412#define IRQ_DMA2_10_POS 4
413#define IRQ_DMA2_11_POS 8
414#define IRQ_TIMER0_POS 12
415#define IRQ_TIMER1_POS 16
416#define IRQ_TIMER2_POS 20
417#define IRQ_TIMER3_POS 24
418#define IRQ_TIMER4_POS 28
419/* IAR5 BIT FIELDS */
420#define IRQ_TIMER5_POS 0
421#define IRQ_TIMER6_POS 4
422#define IRQ_TIMER7_POS 8
423#define IRQ_TIMER8_POS 12
424#define IRQ_TIMER9_POS 16
425#define IRQ_TIMER10_POS 20
426#define IRQ_TIMER11_POS 24
427#define IRQ_PROG0_INTA_POS 28
428/* IAR6 BIT FIELDS */
429#define IRQ_PROG0_INTB_POS 0
430#define IRQ_PROG1_INTA_POS 4
431#define IRQ_PROG1_INTB_POS 8
432#define IRQ_PROG2_INTA_POS 12
433#define IRQ_PROG2_INTB_POS 16
434#define IRQ_DMA1_WRRD0_POS 20
435#define IRQ_DMA1_WRRD1_POS 24
436#define IRQ_DMA2_WRRD0_POS 28
437/* IAR7 BIT FIELDS */
438#define IRQ_DMA2_WRRD1_POS 0
439#define IRQ_IMDMA_WRRD0_POS 4
440#define IRQ_IMDMA_WRRD1_POS 8
441#define IRQ_WDTIMER_POS 12
442#define IRQ_RESERVED_1_POS 16
443#define IRQ_RESERVED_2_POS 20
444#define IRQ_SUPPLE_0_POS 24
445#define IRQ_SUPPLE_1_POS 28
446
447#endif /* _BF561_IRQ_H_ */
diff --git a/arch/blackfin/mach-bf561/include/mach/mem_init.h b/arch/blackfin/mach-bf561/include/mach/mem_init.h
new file mode 100644
index 000000000000..e163260bca18
--- /dev/null
+++ b/arch/blackfin/mach-bf561/include/mach/mem_init.h
@@ -0,0 +1,295 @@
1/*
2 * File: include/asm-blackfin/mach-bf561/mem_init.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || CONFIG_MEM_GENERIC_BOARD || CONFIG_MEM_MT48LC8M32B2B5_7)
32#if (CONFIG_SCLK_HZ > 119402985)
33#define SDRAM_tRP TRP_2
34#define SDRAM_tRP_num 2
35#define SDRAM_tRAS TRAS_7
36#define SDRAM_tRAS_num 7
37#define SDRAM_tRCD TRCD_2
38#define SDRAM_tWR TWR_2
39#endif
40#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
41#define SDRAM_tRP TRP_2
42#define SDRAM_tRP_num 2
43#define SDRAM_tRAS TRAS_6
44#define SDRAM_tRAS_num 6
45#define SDRAM_tRCD TRCD_2
46#define SDRAM_tWR TWR_2
47#endif
48#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
49#define SDRAM_tRP TRP_2
50#define SDRAM_tRP_num 2
51#define SDRAM_tRAS TRAS_5
52#define SDRAM_tRAS_num 5
53#define SDRAM_tRCD TRCD_2
54#define SDRAM_tWR TWR_2
55#endif
56#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
57#define SDRAM_tRP TRP_2
58#define SDRAM_tRP_num 2
59#define SDRAM_tRAS TRAS_4
60#define SDRAM_tRAS_num 4
61#define SDRAM_tRCD TRCD_2
62#define SDRAM_tWR TWR_2
63#endif
64#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
65#define SDRAM_tRP TRP_2
66#define SDRAM_tRP_num 2
67#define SDRAM_tRAS TRAS_3
68#define SDRAM_tRAS_num 3
69#define SDRAM_tRCD TRCD_2
70#define SDRAM_tWR TWR_2
71#endif
72#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
73#define SDRAM_tRP TRP_1
74#define SDRAM_tRP_num 1
75#define SDRAM_tRAS TRAS_4
76#define SDRAM_tRAS_num 3
77#define SDRAM_tRCD TRCD_1
78#define SDRAM_tWR TWR_2
79#endif
80#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
81#define SDRAM_tRP TRP_1
82#define SDRAM_tRP_num 1
83#define SDRAM_tRAS TRAS_3
84#define SDRAM_tRAS_num 3
85#define SDRAM_tRCD TRCD_1
86#define SDRAM_tWR TWR_2
87#endif
88#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
89#define SDRAM_tRP TRP_1
90#define SDRAM_tRP_num 1
91#define SDRAM_tRAS TRAS_2
92#define SDRAM_tRAS_num 2
93#define SDRAM_tRCD TRCD_1
94#define SDRAM_tWR TWR_2
95#endif
96#if (CONFIG_SCLK_HZ <= 29850746)
97#define SDRAM_tRP TRP_1
98#define SDRAM_tRP_num 1
99#define SDRAM_tRAS TRAS_1
100#define SDRAM_tRAS_num 1
101#define SDRAM_tRCD TRCD_1
102#define SDRAM_tWR TWR_2
103#endif
104#endif
105
106#if (CONFIG_MEM_MT48LC16M16A2TG_75)
107 /*SDRAM INFORMATION: */
108#define SDRAM_Tref 64 /* Refresh period in milliseconds */
109#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
110#define SDRAM_CL CL_3
111#endif
112
113#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
114 /*SDRAM INFORMATION: */
115#define SDRAM_Tref 64 /* Refresh period in milliseconds */
116#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
117#define SDRAM_CL CL_3
118#endif
119
120#if (CONFIG_MEM_MT48LC8M32B2B5_7)
121 /*SDRAM INFORMATION: */
122#define SDRAM_Tref 64 /* Refresh period in milliseconds */
123#define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
124#define SDRAM_CL CL_3
125#endif
126
127#if (CONFIG_MEM_GENERIC_BOARD)
128 /*SDRAM INFORMATION: Modify this for your board */
129#define SDRAM_Tref 64 /* Refresh period in milliseconds */
130#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
131#define SDRAM_CL CL_3
132#endif
133
134/* Equation from section 17 (p17-46) of BF533 HRM */
135#define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
136
137/* Enable SCLK Out */
138#define mem_SDGCTL (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
139
140#if defined CONFIG_CLKIN_HALF
141#define CLKIN_HALF 1
142#else
143#define CLKIN_HALF 0
144#endif
145
146#if defined CONFIG_PLL_BYPASS
147#define PLL_BYPASS 1
148#else
149#define PLL_BYPASS 0
150#endif
151
152/***************************************Currently Not Being Used *********************************/
153#define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
154#define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
155#define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ))
156#define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
157#define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
158
159#if (flash_EBIU_AMBCTL_TT > 3)
160#define flash_EBIU_AMBCTL0_TT B0TT_4
161#endif
162#if (flash_EBIU_AMBCTL_TT == 3)
163#define flash_EBIU_AMBCTL0_TT B0TT_3
164#endif
165#if (flash_EBIU_AMBCTL_TT == 2)
166#define flash_EBIU_AMBCTL0_TT B0TT_2
167#endif
168#if (flash_EBIU_AMBCTL_TT < 2)
169#define flash_EBIU_AMBCTL0_TT B0TT_1
170#endif
171
172#if (flash_EBIU_AMBCTL_ST > 3)
173#define flash_EBIU_AMBCTL0_ST B0ST_4
174#endif
175#if (flash_EBIU_AMBCTL_ST == 3)
176#define flash_EBIU_AMBCTL0_ST B0ST_3
177#endif
178#if (flash_EBIU_AMBCTL_ST == 2)
179#define flash_EBIU_AMBCTL0_ST B0ST_2
180#endif
181#if (flash_EBIU_AMBCTL_ST < 2)
182#define flash_EBIU_AMBCTL0_ST B0ST_1
183#endif
184
185#if (flash_EBIU_AMBCTL_HT > 2)
186#define flash_EBIU_AMBCTL0_HT B0HT_3
187#endif
188#if (flash_EBIU_AMBCTL_HT == 2)
189#define flash_EBIU_AMBCTL0_HT B0HT_2
190#endif
191#if (flash_EBIU_AMBCTL_HT == 1)
192#define flash_EBIU_AMBCTL0_HT B0HT_1
193#endif
194#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
195#define flash_EBIU_AMBCTL0_HT B0HT_0
196#endif
197#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
198#define flash_EBIU_AMBCTL0_HT B0HT_1
199#endif
200
201#if (flash_EBIU_AMBCTL_WAT > 14)
202#define flash_EBIU_AMBCTL0_WAT B0WAT_15
203#endif
204#if (flash_EBIU_AMBCTL_WAT == 14)
205#define flash_EBIU_AMBCTL0_WAT B0WAT_14
206#endif
207#if (flash_EBIU_AMBCTL_WAT == 13)
208#define flash_EBIU_AMBCTL0_WAT B0WAT_13
209#endif
210#if (flash_EBIU_AMBCTL_WAT == 12)
211#define flash_EBIU_AMBCTL0_WAT B0WAT_12
212#endif
213#if (flash_EBIU_AMBCTL_WAT == 11)
214#define flash_EBIU_AMBCTL0_WAT B0WAT_11
215#endif
216#if (flash_EBIU_AMBCTL_WAT == 10)
217#define flash_EBIU_AMBCTL0_WAT B0WAT_10
218#endif
219#if (flash_EBIU_AMBCTL_WAT == 9)
220#define flash_EBIU_AMBCTL0_WAT B0WAT_9
221#endif
222#if (flash_EBIU_AMBCTL_WAT == 8)
223#define flash_EBIU_AMBCTL0_WAT B0WAT_8
224#endif
225#if (flash_EBIU_AMBCTL_WAT == 7)
226#define flash_EBIU_AMBCTL0_WAT B0WAT_7
227#endif
228#if (flash_EBIU_AMBCTL_WAT == 6)
229#define flash_EBIU_AMBCTL0_WAT B0WAT_6
230#endif
231#if (flash_EBIU_AMBCTL_WAT == 5)
232#define flash_EBIU_AMBCTL0_WAT B0WAT_5
233#endif
234#if (flash_EBIU_AMBCTL_WAT == 4)
235#define flash_EBIU_AMBCTL0_WAT B0WAT_4
236#endif
237#if (flash_EBIU_AMBCTL_WAT == 3)
238#define flash_EBIU_AMBCTL0_WAT B0WAT_3
239#endif
240#if (flash_EBIU_AMBCTL_WAT == 2)
241#define flash_EBIU_AMBCTL0_WAT B0WAT_2
242#endif
243#if (flash_EBIU_AMBCTL_WAT == 1)
244#define flash_EBIU_AMBCTL0_WAT B0WAT_1
245#endif
246
247#if (flash_EBIU_AMBCTL_RAT > 14)
248#define flash_EBIU_AMBCTL0_RAT B0RAT_15
249#endif
250#if (flash_EBIU_AMBCTL_RAT == 14)
251#define flash_EBIU_AMBCTL0_RAT B0RAT_14
252#endif
253#if (flash_EBIU_AMBCTL_RAT == 13)
254#define flash_EBIU_AMBCTL0_RAT B0RAT_13
255#endif
256#if (flash_EBIU_AMBCTL_RAT == 12)
257#define flash_EBIU_AMBCTL0_RAT B0RAT_12
258#endif
259#if (flash_EBIU_AMBCTL_RAT == 11)
260#define flash_EBIU_AMBCTL0_RAT B0RAT_11
261#endif
262#if (flash_EBIU_AMBCTL_RAT == 10)
263#define flash_EBIU_AMBCTL0_RAT B0RAT_10
264#endif
265#if (flash_EBIU_AMBCTL_RAT == 9)
266#define flash_EBIU_AMBCTL0_RAT B0RAT_9
267#endif
268#if (flash_EBIU_AMBCTL_RAT == 8)
269#define flash_EBIU_AMBCTL0_RAT B0RAT_8
270#endif
271#if (flash_EBIU_AMBCTL_RAT == 7)
272#define flash_EBIU_AMBCTL0_RAT B0RAT_7
273#endif
274#if (flash_EBIU_AMBCTL_RAT == 6)
275#define flash_EBIU_AMBCTL0_RAT B0RAT_6
276#endif
277#if (flash_EBIU_AMBCTL_RAT == 5)
278#define flash_EBIU_AMBCTL0_RAT B0RAT_5
279#endif
280#if (flash_EBIU_AMBCTL_RAT == 4)
281#define flash_EBIU_AMBCTL0_RAT B0RAT_4
282#endif
283#if (flash_EBIU_AMBCTL_RAT == 3)
284#define flash_EBIU_AMBCTL0_RAT B0RAT_3
285#endif
286#if (flash_EBIU_AMBCTL_RAT == 2)
287#define flash_EBIU_AMBCTL0_RAT B0RAT_2
288#endif
289#if (flash_EBIU_AMBCTL_RAT == 1)
290#define flash_EBIU_AMBCTL0_RAT B0RAT_1
291#endif
292
293#define flash_EBIU_AMBCTL0 \
294 (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
295 flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
diff --git a/arch/blackfin/mach-bf561/include/mach/mem_map.h b/arch/blackfin/mach-bf561/include/mach/mem_map.h
new file mode 100644
index 000000000000..c26d8486cc4b
--- /dev/null
+++ b/arch/blackfin/mach-bf561/include/mach/mem_map.h
@@ -0,0 +1,78 @@
1/*
2 * Memory MAP
3 * Common header file for blackfin BF561 of processors.
4 */
5
6#ifndef _MEM_MAP_561_H_
7#define _MEM_MAP_561_H_
8
9#define COREMMR_BASE 0xFFE00000 /* Core MMRs */
10#define SYSMMR_BASE 0xFFC00000 /* System MMRs */
11
12/* Async Memory Banks */
13#define ASYNC_BANK3_BASE 0x2C000000 /* Async Bank 3 */
14#define ASYNC_BANK3_SIZE 0x04000000 /* 64M */
15#define ASYNC_BANK2_BASE 0x28000000 /* Async Bank 2 */
16#define ASYNC_BANK2_SIZE 0x04000000 /* 64M */
17#define ASYNC_BANK1_BASE 0x24000000 /* Async Bank 1 */
18#define ASYNC_BANK1_SIZE 0x04000000 /* 64M */
19#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
20#define ASYNC_BANK0_SIZE 0x04000000 /* 64M */
21
22/* Boot ROM Memory */
23
24#define BOOT_ROM_START 0xEF000000
25#define BOOT_ROM_LENGTH 0x800
26
27/* Level 1 Memory */
28
29#ifdef CONFIG_BFIN_ICACHE
30#define BFIN_ICACHESIZE (16*1024)
31#else
32#define BFIN_ICACHESIZE (0*1024)
33#endif
34
35/* Memory Map for ADSP-BF561 processors */
36
37#ifdef CONFIG_BF561
38#define L1_CODE_START 0xFFA00000
39#define L1_DATA_A_START 0xFF800000
40#define L1_DATA_B_START 0xFF900000
41
42#define L1_CODE_LENGTH 0x4000
43
44#ifdef CONFIG_BFIN_DCACHE
45
46#ifdef CONFIG_BFIN_DCACHE_BANKA
47#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
48#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
49#define L1_DATA_B_LENGTH 0x8000
50#define BFIN_DCACHESIZE (16*1024)
51#define BFIN_DSUPBANKS 1
52#else
53#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
54#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
55#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
56#define BFIN_DCACHESIZE (32*1024)
57#define BFIN_DSUPBANKS 2
58#endif
59
60#else
61#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
62#define L1_DATA_A_LENGTH 0x8000
63#define L1_DATA_B_LENGTH 0x8000
64#define BFIN_DCACHESIZE (0*1024)
65#define BFIN_DSUPBANKS 0
66#endif /*CONFIG_BFIN_DCACHE*/
67#endif
68
69/* Level 2 Memory */
70#define L2_START 0xFEB00000
71#define L2_LENGTH 0x20000
72
73/* Scratch Pad Memory */
74
75#define L1_SCRATCH_START 0xFFB00000
76#define L1_SCRATCH_LENGTH 0x1000
77
78#endif /* _MEM_MAP_533_H_ */
diff --git a/arch/blackfin/mach-bf561/include/mach/portmux.h b/arch/blackfin/mach-bf561/include/mach/portmux.h
new file mode 100644
index 000000000000..a6ee8206efb6
--- /dev/null
+++ b/arch/blackfin/mach-bf561/include/mach/portmux.h
@@ -0,0 +1,89 @@
1#ifndef _MACH_PORTMUX_H_
2#define _MACH_PORTMUX_H_
3
4#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
5
6#define P_PPI0_CLK (P_DONTCARE)
7#define P_PPI0_FS1 (P_DONTCARE)
8#define P_PPI0_FS2 (P_DONTCARE)
9#define P_PPI0_FS3 (P_DONTCARE)
10#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF47))
11#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF46))
12#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF45))
13#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF44))
14#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF43))
15#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF42))
16#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF41))
17#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF40))
18#define P_PPI0_D0 (P_DONTCARE)
19#define P_PPI0_D1 (P_DONTCARE)
20#define P_PPI0_D2 (P_DONTCARE)
21#define P_PPI0_D3 (P_DONTCARE)
22#define P_PPI0_D4 (P_DONTCARE)
23#define P_PPI0_D5 (P_DONTCARE)
24#define P_PPI0_D6 (P_DONTCARE)
25#define P_PPI0_D7 (P_DONTCARE)
26#define P_PPI1_CLK (P_DONTCARE)
27#define P_PPI1_FS1 (P_DONTCARE)
28#define P_PPI1_FS2 (P_DONTCARE)
29#define P_PPI1_FS3 (P_DONTCARE)
30#define P_PPI1_D15 (P_DEFINED | P_IDENT(GPIO_PF39))
31#define P_PPI1_D14 (P_DEFINED | P_IDENT(GPIO_PF38))
32#define P_PPI1_D13 (P_DEFINED | P_IDENT(GPIO_PF37))
33#define P_PPI1_D12 (P_DEFINED | P_IDENT(GPIO_PF36))
34#define P_PPI1_D11 (P_DEFINED | P_IDENT(GPIO_PF35))
35#define P_PPI1_D10 (P_DEFINED | P_IDENT(GPIO_PF34))
36#define P_PPI1_D9 (P_DEFINED | P_IDENT(GPIO_PF33))
37#define P_PPI1_D8 (P_DEFINED | P_IDENT(GPIO_PF32))
38#define P_PPI1_D0 (P_DONTCARE)
39#define P_PPI1_D1 (P_DONTCARE)
40#define P_PPI1_D2 (P_DONTCARE)
41#define P_PPI1_D3 (P_DONTCARE)
42#define P_PPI1_D4 (P_DONTCARE)
43#define P_PPI1_D5 (P_DONTCARE)
44#define P_PPI1_D6 (P_DONTCARE)
45#define P_PPI1_D7 (P_DONTCARE)
46#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PF31))
47#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PF30))
48#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PF29))
49#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PF28))
50#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF27))
51#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF26))
52#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PF25))
53#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PF24))
54#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PF23))
55#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PF22))
56#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PF21))
57#define P_SPORT1_DRPRI (P_DONTCARE)
58#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PF20))
59#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PF19))
60#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PF18))
61#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PF17))
62#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PF16))
63#define P_SPORT0_DRPRI (P_DONTCARE)
64#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF15))
65#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7))
66#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6))
67#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5))
68#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4))
69#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3))
70#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2))
71#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1))
72#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0))
73#define P_TMR11 (P_DONTCARE)
74#define P_TMR10 (P_DONTCARE)
75#define P_TMR9 (P_DONTCARE)
76#define P_TMR8 (P_DONTCARE)
77#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PF7))
78#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PF6))
79#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PF5))
80#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PF4))
81#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF3))
82#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF2))
83#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PF1))
84#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PF0))
85#define P_SPI0_MOSI (P_DONTCARE)
86#define P_SPI0_MISO (P_DONTCARE)
87#define P_SPI0_SCK (P_DONTCARE)
88
89#endif /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/mach-common/arch_checks.c b/arch/blackfin/mach-common/arch_checks.c
index 5986758b2752..98133b968f7b 100644
--- a/arch/blackfin/mach-common/arch_checks.c
+++ b/arch/blackfin/mach-common/arch_checks.c
@@ -28,8 +28,8 @@
28 */ 28 */
29 29
30#include <asm/fixed_code.h> 30#include <asm/fixed_code.h>
31#include <asm/mach/anomaly.h> 31#include <mach/anomaly.h>
32#include <asm/mach-common/clocks.h> 32#include <asm/clocks.h>
33 33
34#ifdef CONFIG_BFIN_KERNEL_CLOCK 34#ifdef CONFIG_BFIN_KERNEL_CLOCK
35 35
diff --git a/arch/blackfin/mach-common/dpmc_modes.S b/arch/blackfin/mach-common/dpmc_modes.S
index 838b0b2ce9a5..ad5431e2cd05 100644
--- a/arch/blackfin/mach-common/dpmc_modes.S
+++ b/arch/blackfin/mach-common/dpmc_modes.S
@@ -6,7 +6,7 @@
6 6
7#include <linux/linkage.h> 7#include <linux/linkage.h>
8#include <asm/blackfin.h> 8#include <asm/blackfin.h>
9#include <asm/mach/irq.h> 9#include <mach/irq.h>
10#include <asm/dpmc.h> 10#include <asm/dpmc.h>
11 11
12.section .l1.text 12.section .l1.text
diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S
index 117c01c2c6b0..847c172a99eb 100644
--- a/arch/blackfin/mach-common/entry.S
+++ b/arch/blackfin/mach-common/entry.S
@@ -43,7 +43,7 @@
43#include <asm/asm-offsets.h> 43#include <asm/asm-offsets.h>
44#include <asm/trace.h> 44#include <asm/trace.h>
45 45
46#include <asm/mach-common/context.S> 46#include <asm/context.S>
47 47
48#if defined(CONFIG_BFIN_SCRATCH_REG_RETN) 48#if defined(CONFIG_BFIN_SCRATCH_REG_RETN)
49# define EX_SCRATCH_REG RETN 49# define EX_SCRATCH_REG RETN
diff --git a/arch/blackfin/mach-common/interrupt.S b/arch/blackfin/mach-common/interrupt.S
index 7f752c87fe46..b27e59d32401 100644
--- a/arch/blackfin/mach-common/interrupt.S
+++ b/arch/blackfin/mach-common/interrupt.S
@@ -29,7 +29,7 @@
29 */ 29 */
30 30
31#include <asm/blackfin.h> 31#include <asm/blackfin.h>
32#include <asm/mach/irq.h> 32#include <mach/irq.h>
33#include <linux/linkage.h> 33#include <linux/linkage.h>
34#include <asm/entry.h> 34#include <asm/entry.h>
35#include <asm/asm-offsets.h> 35#include <asm/asm-offsets.h>
@@ -37,7 +37,7 @@
37#include <asm/traps.h> 37#include <asm/traps.h>
38#include <asm/thread_info.h> 38#include <asm/thread_info.h>
39 39
40#include <asm/mach-common/context.S> 40#include <asm/context.S>
41 41
42.extern _ret_from_exception 42.extern _ret_from_exception
43 43
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index 62f8883a5c27..5fa536727c61 100644
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -216,7 +216,7 @@ int bfin_internal_set_wake(unsigned int irq, unsigned int state)
216 wakeup |= KPADWE; 216 wakeup |= KPADWE;
217 break; 217 break;
218#endif 218#endif
219#ifdef IRQ_CNT 219#ifdef CONFIG_BF54x
220 case IRQ_CNT: 220 case IRQ_CNT:
221 wakeup |= ROTWE; 221 wakeup |= ROTWE;
222 break; 222 break;
@@ -983,7 +983,7 @@ int __init init_arch_irq(void)
983 983
984 local_irq_disable(); 984 local_irq_disable();
985 985
986#if defined(CONFIG_BF527) || defined(CONFIG_BF536) || defined(CONFIG_BF537) 986#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
987 /* Clear EMAC Interrupt Status bits so we can demux it later */ 987 /* Clear EMAC Interrupt Status bits so we can demux it later */
988 bfin_write_EMAC_SYSTAT(-1); 988 bfin_write_EMAC_SYSTAT(-1);
989#endif 989#endif
diff --git a/arch/blackfin/mm/blackfin_sram.c b/arch/blackfin/mm/blackfin_sram.c
index 9d2be43ac3da..4f5e887a0d96 100644
--- a/arch/blackfin/mm/blackfin_sram.c
+++ b/arch/blackfin/mm/blackfin_sram.c
@@ -335,7 +335,7 @@ static int _sram_free(const void *addr,
335 plast->size += pavail->size; 335 plast->size += pavail->size;
336 kmem_cache_free(sram_piece_cache, pavail); 336 kmem_cache_free(sram_piece_cache, pavail);
337 } else { 337 } else {
338 pavail->next = plast; 338 pavail->next = plast->next;
339 plast->next = pavail; 339 plast->next = pavail;
340 plast = pavail; 340 plast = pavail;
341 } 341 }
@@ -379,7 +379,7 @@ EXPORT_SYMBOL(sram_free);
379 379
380void *l1_data_A_sram_alloc(size_t size) 380void *l1_data_A_sram_alloc(size_t size)
381{ 381{
382 unsigned flags; 382 unsigned long flags;
383 void *addr = NULL; 383 void *addr = NULL;
384 384
385 /* add mutex operation */ 385 /* add mutex operation */
@@ -402,7 +402,7 @@ EXPORT_SYMBOL(l1_data_A_sram_alloc);
402 402
403int l1_data_A_sram_free(const void *addr) 403int l1_data_A_sram_free(const void *addr)
404{ 404{
405 unsigned flags; 405 unsigned long flags;
406 int ret; 406 int ret;
407 407
408 /* add mutex operation */ 408 /* add mutex operation */
@@ -425,7 +425,7 @@ EXPORT_SYMBOL(l1_data_A_sram_free);
425void *l1_data_B_sram_alloc(size_t size) 425void *l1_data_B_sram_alloc(size_t size)
426{ 426{
427#if L1_DATA_B_LENGTH != 0 427#if L1_DATA_B_LENGTH != 0
428 unsigned flags; 428 unsigned long flags;
429 void *addr; 429 void *addr;
430 430
431 /* add mutex operation */ 431 /* add mutex operation */
@@ -450,7 +450,7 @@ EXPORT_SYMBOL(l1_data_B_sram_alloc);
450int l1_data_B_sram_free(const void *addr) 450int l1_data_B_sram_free(const void *addr)
451{ 451{
452#if L1_DATA_B_LENGTH != 0 452#if L1_DATA_B_LENGTH != 0
453 unsigned flags; 453 unsigned long flags;
454 int ret; 454 int ret;
455 455
456 /* add mutex operation */ 456 /* add mutex operation */
@@ -504,7 +504,7 @@ EXPORT_SYMBOL(l1_data_sram_free);
504void *l1_inst_sram_alloc(size_t size) 504void *l1_inst_sram_alloc(size_t size)
505{ 505{
506#if L1_CODE_LENGTH != 0 506#if L1_CODE_LENGTH != 0
507 unsigned flags; 507 unsigned long flags;
508 void *addr; 508 void *addr;
509 509
510 /* add mutex operation */ 510 /* add mutex operation */
@@ -529,7 +529,7 @@ EXPORT_SYMBOL(l1_inst_sram_alloc);
529int l1_inst_sram_free(const void *addr) 529int l1_inst_sram_free(const void *addr)
530{ 530{
531#if L1_CODE_LENGTH != 0 531#if L1_CODE_LENGTH != 0
532 unsigned flags; 532 unsigned long flags;
533 int ret; 533 int ret;
534 534
535 /* add mutex operation */ 535 /* add mutex operation */
@@ -551,7 +551,7 @@ EXPORT_SYMBOL(l1_inst_sram_free);
551/* L1 Scratchpad memory allocate function */ 551/* L1 Scratchpad memory allocate function */
552void *l1sram_alloc(size_t size) 552void *l1sram_alloc(size_t size)
553{ 553{
554 unsigned flags; 554 unsigned long flags;
555 void *addr; 555 void *addr;
556 556
557 /* add mutex operation */ 557 /* add mutex operation */
@@ -569,7 +569,7 @@ void *l1sram_alloc(size_t size)
569/* L1 Scratchpad memory allocate function */ 569/* L1 Scratchpad memory allocate function */
570void *l1sram_alloc_max(size_t *psize) 570void *l1sram_alloc_max(size_t *psize)
571{ 571{
572 unsigned flags; 572 unsigned long flags;
573 void *addr; 573 void *addr;
574 574
575 /* add mutex operation */ 575 /* add mutex operation */
@@ -587,7 +587,7 @@ void *l1sram_alloc_max(size_t *psize)
587/* L1 Scratchpad memory free function */ 587/* L1 Scratchpad memory free function */
588int l1sram_free(const void *addr) 588int l1sram_free(const void *addr)
589{ 589{
590 unsigned flags; 590 unsigned long flags;
591 int ret; 591 int ret;
592 592
593 /* add mutex operation */ 593 /* add mutex operation */
@@ -605,7 +605,7 @@ int l1sram_free(const void *addr)
605void *l2_sram_alloc(size_t size) 605void *l2_sram_alloc(size_t size)
606{ 606{
607#if L2_LENGTH != 0 607#if L2_LENGTH != 0
608 unsigned flags; 608 unsigned long flags;
609 void *addr; 609 void *addr;
610 610
611 /* add mutex operation */ 611 /* add mutex operation */
@@ -641,7 +641,7 @@ EXPORT_SYMBOL(l2_sram_zalloc);
641int l2_sram_free(const void *addr) 641int l2_sram_free(const void *addr)
642{ 642{
643#if L2_LENGTH != 0 643#if L2_LENGTH != 0
644 unsigned flags; 644 unsigned long flags;
645 int ret; 645 int ret;
646 646
647 /* add mutex operation */ 647 /* add mutex operation */
diff --git a/arch/ia64/include/asm/io.h b/arch/ia64/include/asm/io.h
index 260a85ac9d6a..7f257507cd86 100644
--- a/arch/ia64/include/asm/io.h
+++ b/arch/ia64/include/asm/io.h
@@ -19,6 +19,8 @@
19 * Copyright (C) 1999 Don Dugger <don.dugger@intel.com> 19 * Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
20 */ 20 */
21 21
22#include <asm/unaligned.h>
23
22/* We don't use IO slowdowns on the ia64, but.. */ 24/* We don't use IO slowdowns on the ia64, but.. */
23#define __SLOW_DOWN_IO do { } while (0) 25#define __SLOW_DOWN_IO do { } while (0)
24#define SLOW_DOWN_IO do { } while (0) 26#define SLOW_DOWN_IO do { } while (0)
@@ -241,7 +243,7 @@ __insw (unsigned long port, void *dst, unsigned long count)
241 unsigned short *dp = dst; 243 unsigned short *dp = dst;
242 244
243 while (count--) 245 while (count--)
244 *dp++ = platform_inw(port); 246 put_unaligned(platform_inw(port), dp++);
245} 247}
246 248
247static inline void 249static inline void
@@ -250,7 +252,7 @@ __insl (unsigned long port, void *dst, unsigned long count)
250 unsigned int *dp = dst; 252 unsigned int *dp = dst;
251 253
252 while (count--) 254 while (count--)
253 *dp++ = platform_inl(port); 255 put_unaligned(platform_inl(port), dp++);
254} 256}
255 257
256static inline void 258static inline void
@@ -268,7 +270,7 @@ __outsw (unsigned long port, const void *src, unsigned long count)
268 const unsigned short *sp = src; 270 const unsigned short *sp = src;
269 271
270 while (count--) 272 while (count--)
271 platform_outw(*sp++, port); 273 platform_outw(get_unaligned(sp++), port);
272} 274}
273 275
274static inline void 276static inline void
@@ -277,7 +279,7 @@ __outsl (unsigned long port, const void *src, unsigned long count)
277 const unsigned int *sp = src; 279 const unsigned int *sp = src;
278 280
279 while (count--) 281 while (count--)
280 platform_outl(*sp++, port); 282 platform_outl(get_unaligned(sp++), port);
281} 283}
282 284
283/* 285/*
diff --git a/arch/ia64/kernel/smpboot.c b/arch/ia64/kernel/smpboot.c
index b39853a292d5..bcea81e432fd 100644
--- a/arch/ia64/kernel/smpboot.c
+++ b/arch/ia64/kernel/smpboot.c
@@ -138,6 +138,7 @@ cpumask_t cpu_possible_map = CPU_MASK_NONE;
138EXPORT_SYMBOL(cpu_possible_map); 138EXPORT_SYMBOL(cpu_possible_map);
139 139
140cpumask_t cpu_core_map[NR_CPUS] __cacheline_aligned; 140cpumask_t cpu_core_map[NR_CPUS] __cacheline_aligned;
141EXPORT_SYMBOL(cpu_core_map);
141DEFINE_PER_CPU_SHARED_ALIGNED(cpumask_t, cpu_sibling_map); 142DEFINE_PER_CPU_SHARED_ALIGNED(cpumask_t, cpu_sibling_map);
142EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 143EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
143 144
diff --git a/arch/m68k/atari/atakeyb.c b/arch/m68k/atari/atakeyb.c
index 8a2a53b33616..bb959fbab2dc 100644
--- a/arch/m68k/atari/atakeyb.c
+++ b/arch/m68k/atari/atakeyb.c
@@ -580,13 +580,15 @@ int atari_keyb_init(void)
580 do { 580 do {
581 /* reset IKBD ACIA */ 581 /* reset IKBD ACIA */
582 acia.key_ctrl = ACIA_RESET | 582 acia.key_ctrl = ACIA_RESET |
583 (atari_switches & ATARI_SWITCH_IKBD) ? ACIA_RHTID : 0; 583 ((atari_switches & ATARI_SWITCH_IKBD) ?
584 ACIA_RHTID : 0);
584 (void)acia.key_ctrl; 585 (void)acia.key_ctrl;
585 (void)acia.key_data; 586 (void)acia.key_data;
586 587
587 /* reset MIDI ACIA */ 588 /* reset MIDI ACIA */
588 acia.mid_ctrl = ACIA_RESET | 589 acia.mid_ctrl = ACIA_RESET |
589 (atari_switches & ATARI_SWITCH_MIDI) ? ACIA_RHTID : 0; 590 ((atari_switches & ATARI_SWITCH_MIDI) ?
591 ACIA_RHTID : 0);
590 (void)acia.mid_ctrl; 592 (void)acia.mid_ctrl;
591 (void)acia.mid_data; 593 (void)acia.mid_data;
592 594
@@ -599,7 +601,8 @@ int atari_keyb_init(void)
599 ACIA_RHTID : ACIA_RLTID); 601 ACIA_RHTID : ACIA_RLTID);
600 602
601 acia.mid_ctrl = ACIA_DIV16 | ACIA_D8N1S | 603 acia.mid_ctrl = ACIA_DIV16 | ACIA_D8N1S |
602 (atari_switches & ATARI_SWITCH_MIDI) ? ACIA_RHTID : 0; 604 ((atari_switches & ATARI_SWITCH_MIDI) ?
605 ACIA_RHTID : 0);
603 606
604 /* make sure the interrupt line is up */ 607 /* make sure the interrupt line is up */
605 } while ((mfp.par_dt_reg & 0x10) == 0); 608 } while ((mfp.par_dt_reg & 0x10) == 0);
diff --git a/arch/mips/emma2rh/markeins/setup.c b/arch/mips/emma2rh/markeins/setup.c
index 822a20e21fa4..b6a23ad539f8 100644
--- a/arch/mips/emma2rh/markeins/setup.c
+++ b/arch/mips/emma2rh/markeins/setup.c
@@ -25,23 +25,9 @@
25#include <linux/init.h> 25#include <linux/init.h>
26#include <linux/kernel.h> 26#include <linux/kernel.h>
27#include <linux/types.h> 27#include <linux/types.h>
28#include <linux/initrd.h> 28
29#include <linux/irq.h>
30#include <linux/ioport.h>
31#include <linux/param.h> /* for HZ */
32#include <linux/root_dev.h>
33#include <linux/serial.h>
34#include <linux/serial_core.h>
35
36#include <asm/cpu.h>
37#include <asm/bootinfo.h>
38#include <asm/addrspace.h>
39#include <asm/time.h> 29#include <asm/time.h>
40#include <asm/bcache.h>
41#include <asm/irq.h>
42#include <asm/reboot.h> 30#include <asm/reboot.h>
43#include <asm/traps.h>
44#include <asm/debug.h>
45 31
46#include <asm/emma2rh/emma2rh.h> 32#include <asm/emma2rh/emma2rh.h>
47 33
diff --git a/arch/mips/jazz/setup.c b/arch/mips/jazz/setup.c
index b59ba6b93cdd..7043f6b9ff3c 100644
--- a/arch/mips/jazz/setup.c
+++ b/arch/mips/jazz/setup.c
@@ -5,33 +5,22 @@
5 * License. See the file "COPYING" in the main directory of this archive 5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details. 6 * for more details.
7 * 7 *
8 * Copyright (C) 1996, 1997, 1998, 2001, 07 by Ralf Baechle 8 * Copyright (C) 1996, 1997, 1998, 2001, 07, 08 by Ralf Baechle
9 * Copyright (C) 2001 MIPS Technologies, Inc. 9 * Copyright (C) 2001 MIPS Technologies, Inc.
10 * Copyright (C) 2007 by Thomas Bogendoerfer 10 * Copyright (C) 2007 by Thomas Bogendoerfer
11 */ 11 */
12#include <linux/eisa.h> 12#include <linux/eisa.h>
13#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/ioport.h> 14#include <linux/ioport.h>
15#include <linux/sched.h>
16#include <linux/interrupt.h>
17#include <linux/mm.h>
18#include <linux/console.h> 15#include <linux/console.h>
19#include <linux/fb.h>
20#include <linux/pm.h>
21#include <linux/screen_info.h> 16#include <linux/screen_info.h>
22#include <linux/platform_device.h> 17#include <linux/platform_device.h>
23#include <linux/serial_8250.h> 18#include <linux/serial_8250.h>
24 19
25#include <asm/bootinfo.h>
26#include <asm/irq.h>
27#include <asm/jazz.h> 20#include <asm/jazz.h>
28#include <asm/jazzdma.h> 21#include <asm/jazzdma.h>
29#include <asm/reboot.h> 22#include <asm/reboot.h>
30#include <asm/io.h>
31#include <asm/pgtable.h> 23#include <asm/pgtable.h>
32#include <asm/time.h>
33#include <asm/traps.h>
34#include <asm/mc146818-time.h>
35 24
36extern asmlinkage void jazz_handle_int(void); 25extern asmlinkage void jazz_handle_int(void);
37 26
diff --git a/arch/mips/kernel/.gitignore b/arch/mips/kernel/.gitignore
new file mode 100644
index 000000000000..c5f676c3c224
--- /dev/null
+++ b/arch/mips/kernel/.gitignore
@@ -0,0 +1 @@
vmlinux.lds
diff --git a/arch/mips/kernel/kgdb.c b/arch/mips/kernel/kgdb.c
index c5a8b2d21ca4..8f6d58ede33c 100644
--- a/arch/mips/kernel/kgdb.c
+++ b/arch/mips/kernel/kgdb.c
@@ -62,13 +62,13 @@ void arch_kgdb_breakpoint(void)
62 62
63static void kgdb_call_nmi_hook(void *ignored) 63static void kgdb_call_nmi_hook(void *ignored)
64{ 64{
65 kgdb_nmicallback(raw_smp_processor_id(), (void *)0); 65 kgdb_nmicallback(raw_smp_processor_id(), NULL);
66} 66}
67 67
68void kgdb_roundup_cpus(unsigned long flags) 68void kgdb_roundup_cpus(unsigned long flags)
69{ 69{
70 local_irq_enable(); 70 local_irq_enable();
71 smp_call_function(kgdb_call_nmi_hook, NULL, NULL); 71 smp_call_function(kgdb_call_nmi_hook, NULL, 0);
72 local_irq_disable(); 72 local_irq_disable();
73} 73}
74 74
@@ -190,9 +190,6 @@ static int kgdb_mips_notify(struct notifier_block *self, unsigned long cmd,
190 struct pt_regs *regs = args->regs; 190 struct pt_regs *regs = args->regs;
191 int trap = (regs->cp0_cause & 0x7c) >> 2; 191 int trap = (regs->cp0_cause & 0x7c) >> 2;
192 192
193 if (fixup_exception(regs))
194 return NOTIFY_DONE;
195
196 /* Userpace events, ignore. */ 193 /* Userpace events, ignore. */
197 if (user_mode(regs)) 194 if (user_mode(regs))
198 return NOTIFY_DONE; 195 return NOTIFY_DONE;
diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S
index fc4fd4d705e2..5e75a316f6b1 100644
--- a/arch/mips/kernel/scall32-o32.S
+++ b/arch/mips/kernel/scall32-o32.S
@@ -647,6 +647,12 @@ einval: li v0, -EINVAL
647 sys sys_timerfd_create 2 647 sys sys_timerfd_create 2
648 sys sys_timerfd_gettime 2 648 sys sys_timerfd_gettime 2
649 sys sys_timerfd_settime 4 649 sys sys_timerfd_settime 4
650 sys sys_signalfd4 4
651 sys sys_eventfd2 2 /* 4325 */
652 sys sys_epoll_create1 1
653 sys sys_dup3 3
654 sys sys_pipe2 2
655 sys sys_inotify_init1 1
650 .endm 656 .endm
651 657
652 /* We pre-compute the number of _instruction_ bytes needed to 658 /* We pre-compute the number of _instruction_ bytes needed to
diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S
index 2b73fd1e4528..3d58204c9d44 100644
--- a/arch/mips/kernel/scall64-64.S
+++ b/arch/mips/kernel/scall64-64.S
@@ -481,4 +481,10 @@ sys_call_table:
481 PTR sys_timerfd_create /* 5280 */ 481 PTR sys_timerfd_create /* 5280 */
482 PTR sys_timerfd_gettime 482 PTR sys_timerfd_gettime
483 PTR sys_timerfd_settime 483 PTR sys_timerfd_settime
484 PTR sys_signalfd4
485 PTR sys_eventfd2
486 PTR sys_epoll_create1 /* 5285 */
487 PTR sys_dup3
488 PTR sys_pipe2
489 PTR sys_inotify_init1
484 .size sys_call_table,.-sys_call_table 490 .size sys_call_table,.-sys_call_table
diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S
index 2654e75d2fef..da7f1b6ea0fb 100644
--- a/arch/mips/kernel/scall64-n32.S
+++ b/arch/mips/kernel/scall64-n32.S
@@ -407,4 +407,10 @@ EXPORT(sysn32_call_table)
407 PTR sys_timerfd_create 407 PTR sys_timerfd_create
408 PTR sys_timerfd_gettime /* 5285 */ 408 PTR sys_timerfd_gettime /* 5285 */
409 PTR sys_timerfd_settime 409 PTR sys_timerfd_settime
410 PTR sys_signalfd4
411 PTR sys_eventfd2
412 PTR sys_epoll_create1
413 PTR sys_dup3 /* 5290 */
414 PTR sys_pipe2
415 PTR sys_inotify_init1
410 .size sysn32_call_table,.-sysn32_call_table 416 .size sysn32_call_table,.-sysn32_call_table
diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S
index 76167bea5a70..d7cd1aac9ada 100644
--- a/arch/mips/kernel/scall64-o32.S
+++ b/arch/mips/kernel/scall64-o32.S
@@ -529,4 +529,10 @@ sys_call_table:
529 PTR sys_timerfd_create 529 PTR sys_timerfd_create
530 PTR sys_timerfd_gettime 530 PTR sys_timerfd_gettime
531 PTR sys_timerfd_settime 531 PTR sys_timerfd_settime
532 PTR compat_sys_signalfd4
533 PTR sys_eventfd2 /* 4325 */
534 PTR sys_epoll_create1
535 PTR sys_dup3
536 PTR sys_pipe2
537 PTR sys_inotify_init1
532 .size sys_call_table,.-sys_call_table 538 .size sys_call_table,.-sys_call_table
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index 8af84867e74d..2aae76bce293 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -78,7 +78,7 @@ void __init add_memory_region(phys_t start, phys_t size, long type)
78 78
79 /* Sanity check */ 79 /* Sanity check */
80 if (start + size < start) { 80 if (start + size < start) {
81 printk("Trying to add an invalid memory region, skipped\n"); 81 pr_warning("Trying to add an invalid memory region, skipped\n");
82 return; 82 return;
83 } 83 }
84 84
@@ -92,7 +92,7 @@ void __init add_memory_region(phys_t start, phys_t size, long type)
92 } 92 }
93 93
94 if (x == BOOT_MEM_MAP_MAX) { 94 if (x == BOOT_MEM_MAP_MAX) {
95 printk("Ooops! Too many entries in the memory map!\n"); 95 pr_err("Ooops! Too many entries in the memory map!\n");
96 return; 96 return;
97 } 97 }
98 98
@@ -108,22 +108,22 @@ static void __init print_memory_map(void)
108 const int field = 2 * sizeof(unsigned long); 108 const int field = 2 * sizeof(unsigned long);
109 109
110 for (i = 0; i < boot_mem_map.nr_map; i++) { 110 for (i = 0; i < boot_mem_map.nr_map; i++) {
111 printk(" memory: %0*Lx @ %0*Lx ", 111 printk(KERN_INFO " memory: %0*Lx @ %0*Lx ",
112 field, (unsigned long long) boot_mem_map.map[i].size, 112 field, (unsigned long long) boot_mem_map.map[i].size,
113 field, (unsigned long long) boot_mem_map.map[i].addr); 113 field, (unsigned long long) boot_mem_map.map[i].addr);
114 114
115 switch (boot_mem_map.map[i].type) { 115 switch (boot_mem_map.map[i].type) {
116 case BOOT_MEM_RAM: 116 case BOOT_MEM_RAM:
117 printk("(usable)\n"); 117 printk(KERN_CONT "(usable)\n");
118 break; 118 break;
119 case BOOT_MEM_ROM_DATA: 119 case BOOT_MEM_ROM_DATA:
120 printk("(ROM data)\n"); 120 printk(KERN_CONT "(ROM data)\n");
121 break; 121 break;
122 case BOOT_MEM_RESERVED: 122 case BOOT_MEM_RESERVED:
123 printk("(reserved)\n"); 123 printk(KERN_CONT "(reserved)\n");
124 break; 124 break;
125 default: 125 default:
126 printk("type %lu\n", boot_mem_map.map[i].type); 126 printk(KERN_CONT "type %lu\n", boot_mem_map.map[i].type);
127 break; 127 break;
128 } 128 }
129 } 129 }
@@ -185,11 +185,11 @@ static unsigned long __init init_initrd(void)
185 185
186sanitize: 186sanitize:
187 if (initrd_start & ~PAGE_MASK) { 187 if (initrd_start & ~PAGE_MASK) {
188 printk(KERN_ERR "initrd start must be page aligned\n"); 188 pr_err("initrd start must be page aligned\n");
189 goto disable; 189 goto disable;
190 } 190 }
191 if (initrd_start < PAGE_OFFSET) { 191 if (initrd_start < PAGE_OFFSET) {
192 printk(KERN_ERR "initrd start < PAGE_OFFSET\n"); 192 pr_err("initrd start < PAGE_OFFSET\n");
193 goto disable; 193 goto disable;
194 } 194 }
195 195
@@ -221,18 +221,18 @@ static void __init finalize_initrd(void)
221 goto disable; 221 goto disable;
222 } 222 }
223 if (__pa(initrd_end) > PFN_PHYS(max_low_pfn)) { 223 if (__pa(initrd_end) > PFN_PHYS(max_low_pfn)) {
224 printk("Initrd extends beyond end of memory"); 224 printk(KERN_ERR "Initrd extends beyond end of memory");
225 goto disable; 225 goto disable;
226 } 226 }
227 227
228 reserve_bootmem(__pa(initrd_start), size, BOOTMEM_DEFAULT); 228 reserve_bootmem(__pa(initrd_start), size, BOOTMEM_DEFAULT);
229 initrd_below_start_ok = 1; 229 initrd_below_start_ok = 1;
230 230
231 printk(KERN_INFO "Initial ramdisk at: 0x%lx (%lu bytes)\n", 231 pr_info("Initial ramdisk at: 0x%lx (%lu bytes)\n",
232 initrd_start, size); 232 initrd_start, size);
233 return; 233 return;
234disable: 234disable:
235 printk(" - disabling initrd\n"); 235 printk(KERN_CONT " - disabling initrd\n");
236 initrd_start = 0; 236 initrd_start = 0;
237 initrd_end = 0; 237 initrd_end = 0;
238} 238}
@@ -310,14 +310,12 @@ static void __init bootmem_init(void)
310 if (min_low_pfn >= max_low_pfn) 310 if (min_low_pfn >= max_low_pfn)
311 panic("Incorrect memory mapping !!!"); 311 panic("Incorrect memory mapping !!!");
312 if (min_low_pfn > ARCH_PFN_OFFSET) { 312 if (min_low_pfn > ARCH_PFN_OFFSET) {
313 printk(KERN_INFO 313 pr_info("Wasting %lu bytes for tracking %lu unused pages\n",
314 "Wasting %lu bytes for tracking %lu unused pages\n", 314 (min_low_pfn - ARCH_PFN_OFFSET) * sizeof(struct page),
315 (min_low_pfn - ARCH_PFN_OFFSET) * sizeof(struct page), 315 min_low_pfn - ARCH_PFN_OFFSET);
316 min_low_pfn - ARCH_PFN_OFFSET);
317 } else if (min_low_pfn < ARCH_PFN_OFFSET) { 316 } else if (min_low_pfn < ARCH_PFN_OFFSET) {
318 printk(KERN_INFO 317 pr_info("%lu free pages won't be used\n",
319 "%lu free pages won't be used\n", 318 ARCH_PFN_OFFSET - min_low_pfn);
320 ARCH_PFN_OFFSET - min_low_pfn);
321 } 319 }
322 min_low_pfn = ARCH_PFN_OFFSET; 320 min_low_pfn = ARCH_PFN_OFFSET;
323 321
@@ -471,7 +469,7 @@ static void __init arch_mem_init(char **cmdline_p)
471 /* call board setup routine */ 469 /* call board setup routine */
472 plat_mem_setup(); 470 plat_mem_setup();
473 471
474 printk("Determined physical RAM map:\n"); 472 pr_info("Determined physical RAM map:\n");
475 print_memory_map(); 473 print_memory_map();
476 474
477 strlcpy(command_line, arcs_cmdline, sizeof(command_line)); 475 strlcpy(command_line, arcs_cmdline, sizeof(command_line));
@@ -482,7 +480,7 @@ static void __init arch_mem_init(char **cmdline_p)
482 parse_early_param(); 480 parse_early_param();
483 481
484 if (usermem) { 482 if (usermem) {
485 printk("User-defined physical RAM map:\n"); 483 pr_info("User-defined physical RAM map:\n");
486 print_memory_map(); 484 print_memory_map();
487 } 485 }
488 486
diff --git a/arch/mips/pci/pci-ip27.c b/arch/mips/pci/pci-ip27.c
index ce92f82b16d2..bd78368c82bf 100644
--- a/arch/mips/pci/pci-ip27.c
+++ b/arch/mips/pci/pci-ip27.c
@@ -205,6 +205,7 @@ int pcibus_to_node(struct pci_bus *bus)
205 205
206 return bc->nasid; 206 return bc->nasid;
207} 207}
208EXPORT_SYMBOL(pcibus_to_node);
208 209
209DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, 210DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
210 pci_fixup_ioc3); 211 pci_fixup_ioc3);
diff --git a/arch/mips/rb532/devices.c b/arch/mips/rb532/devices.c
index 44fb0a62877f..82ab395efa33 100644
--- a/arch/mips/rb532/devices.c
+++ b/arch/mips/rb532/devices.c
@@ -49,8 +49,6 @@
49#define GPIO_ALE (1 << 0x0a) 49#define GPIO_ALE (1 << 0x0a)
50#define GPIO_CLE (1 << 0x0b) 50#define GPIO_CLE (1 << 0x0b)
51 51
52extern char *board_type;
53
54static struct resource korina_dev0_res[] = { 52static struct resource korina_dev0_res[] = {
55 { 53 {
56 .name = "korina_regs", 54 .name = "korina_regs",
@@ -265,14 +263,6 @@ static void __init parse_mac_addr(char *macstr)
265} 263}
266 264
267 265
268/* DEVICE CONTROLLER 1 */
269#define CFG_DC_DEV1 ((void *)0xb8010010)
270#define CFG_DC_DEV2 ((void *)0xb8010020)
271#define CFG_DC_DEVBASE 0x0
272#define CFG_DC_DEVMASK 0x4
273#define CFG_DC_DEVC 0x8
274#define CFG_DC_DEVTC 0xC
275
276/* NAND definitions */ 266/* NAND definitions */
277#define NAND_CHIP_DELAY 25 267#define NAND_CHIP_DELAY 25
278 268
@@ -301,16 +291,16 @@ static void __init rb532_nand_setup(void)
301static int __init plat_setup_devices(void) 291static int __init plat_setup_devices(void)
302{ 292{
303 /* Look for the CF card reader */ 293 /* Look for the CF card reader */
304 if (!readl(CFG_DC_DEV1 + CFG_DC_DEVMASK)) 294 if (!readl(IDT434_REG_BASE + DEV1MASK))
305 rb532_devs[1] = NULL; 295 rb532_devs[1] = NULL;
306 else { 296 else {
307 cf_slot0_res[0].start = 297 cf_slot0_res[0].start =
308 readl(CFG_DC_DEV1 + CFG_DC_DEVBASE); 298 readl(IDT434_REG_BASE + DEV1BASE);
309 cf_slot0_res[0].end = cf_slot0_res[0].start + 0x1000; 299 cf_slot0_res[0].end = cf_slot0_res[0].start + 0x1000;
310 } 300 }
311 301
312 /* Read the NAND resources from the device controller */ 302 /* Read the NAND resources from the device controller */
313 nand_slot0_res[0].start = readl(CFG_DC_DEV2 + CFG_DC_DEVBASE); 303 nand_slot0_res[0].start = readl(IDT434_REG_BASE + DEV2BASE);
314 nand_slot0_res[0].end = nand_slot0_res[0].start + 0x1000; 304 nand_slot0_res[0].end = nand_slot0_res[0].start + 0x1000;
315 305
316 /* Initialise the NAND device */ 306 /* Initialise the NAND device */
diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c
index 1bc57d0f4c5c..0afe94c48fb6 100644
--- a/arch/mips/txx9/generic/setup.c
+++ b/arch/mips/txx9/generic/setup.c
@@ -328,6 +328,9 @@ void __init arch_init_irq(void)
328 328
329void __init plat_time_init(void) 329void __init plat_time_init(void)
330{ 330{
331#ifdef CONFIG_CPU_TX49XX
332 mips_hpt_frequency = txx9_cpu_clock / 2;
333#endif
331 txx9_board_vec->time_init(); 334 txx9_board_vec->time_init();
332} 335}
333 336
diff --git a/arch/parisc/hpux/fs.c b/arch/parisc/hpux/fs.c
index 1263f00dc35d..12c04c5e558b 100644
--- a/arch/parisc/hpux/fs.c
+++ b/arch/parisc/hpux/fs.c
@@ -84,22 +84,28 @@ static int filldir(void * __buf, const char * name, int namlen, loff_t offset,
84 if (reclen > buf->count) 84 if (reclen > buf->count)
85 return -EINVAL; 85 return -EINVAL;
86 d_ino = ino; 86 d_ino = ino;
87 if (sizeof(d_ino) < sizeof(ino) && d_ino != ino) 87 if (sizeof(d_ino) < sizeof(ino) && d_ino != ino) {
88 buf->error = -EOVERFLOW;
88 return -EOVERFLOW; 89 return -EOVERFLOW;
90 }
89 dirent = buf->previous; 91 dirent = buf->previous;
90 if (dirent) 92 if (dirent)
91 put_user(offset, &dirent->d_off); 93 if (put_user(offset, &dirent->d_off))
94 goto Efault;
92 dirent = buf->current_dir; 95 dirent = buf->current_dir;
96 if (put_user(d_ino, &dirent->d_ino) ||
97 put_user(reclen, &dirent->d_reclen) ||
98 put_user(namlen, &dirent->d_namlen) ||
99 copy_to_user(dirent->d_name, name, namlen) ||
100 put_user(0, dirent->d_name + namlen))
101 goto Efault;
93 buf->previous = dirent; 102 buf->previous = dirent;
94 put_user(d_ino, &dirent->d_ino); 103 buf->current_dir = (void __user *)dirent + reclen;
95 put_user(reclen, &dirent->d_reclen);
96 put_user(namlen, &dirent->d_namlen);
97 copy_to_user(dirent->d_name, name, namlen);
98 put_user(0, dirent->d_name + namlen);
99 dirent = (void __user *)dirent + reclen;
100 buf->current_dir = dirent;
101 buf->count -= reclen; 104 buf->count -= reclen;
102 return 0; 105 return 0;
106Efault:
107 buf->error = -EFAULT;
108 return -EFAULT;
103} 109}
104 110
105#undef NAME_OFFSET 111#undef NAME_OFFSET
@@ -126,8 +132,10 @@ int hpux_getdents(unsigned int fd, struct hpux_dirent __user *dirent, unsigned i
126 error = buf.error; 132 error = buf.error;
127 lastdirent = buf.previous; 133 lastdirent = buf.previous;
128 if (lastdirent) { 134 if (lastdirent) {
129 put_user(file->f_pos, &lastdirent->d_off); 135 if (put_user(file->f_pos, &lastdirent->d_off))
130 error = count - buf.count; 136 error = -EFAULT;
137 else
138 error = count - buf.count;
131 } 139 }
132 140
133out_putf: 141out_putf:
diff --git a/arch/powerpc/boot/dts/mpc8641_hpcn.dts b/arch/powerpc/boot/dts/mpc8641_hpcn.dts
index ae08761ffff1..d665e767822a 100644
--- a/arch/powerpc/boot/dts/mpc8641_hpcn.dts
+++ b/arch/powerpc/boot/dts/mpc8641_hpcn.dts
@@ -411,7 +411,7 @@
411 0xe000 0 0 1 &i8259 12 2 411 0xe000 0 0 1 &i8259 12 2
412 0xe100 0 0 2 &i8259 9 2 412 0xe100 0 0 2 &i8259 9 2
413 0xe200 0 0 3 &i8259 10 2 413 0xe200 0 0 3 &i8259 10 2
414 0xe300 0 0 4 &i8259 112 414 0xe300 0 0 4 &i8259 11 2
415 415
416 // IDSEL 0x1d Audio 416 // IDSEL 0x1d Audio
417 0xe800 0 0 1 &i8259 6 2 417 0xe800 0 0 1 &i8259 6 2
diff --git a/arch/powerpc/boot/dts/tqm8548-bigflash.dts b/arch/powerpc/boot/dts/tqm8548-bigflash.dts
index 64d2d5bbcdf1..4199e89b4e50 100644
--- a/arch/powerpc/boot/dts/tqm8548-bigflash.dts
+++ b/arch/powerpc/boot/dts/tqm8548-bigflash.dts
@@ -50,13 +50,14 @@
50 reg = <0x00000000 0x00000000>; // Filled in by U-Boot 50 reg = <0x00000000 0x00000000>; // Filled in by U-Boot
51 }; 51 };
52 52
53 soc8548@a0000000 { 53 soc@a0000000 {
54 #address-cells = <1>; 54 #address-cells = <1>;
55 #size-cells = <1>; 55 #size-cells = <1>;
56 device_type = "soc"; 56 device_type = "soc";
57 ranges = <0x0 0xa0000000 0x100000>; 57 ranges = <0x0 0xa0000000 0x100000>;
58 reg = <0xa0000000 0x1000>; // CCSRBAR 58 reg = <0xa0000000 0x1000>; // CCSRBAR
59 bus-frequency = <0>; 59 bus-frequency = <0>;
60 compatible = "fsl,mpc8548-immr", "simple-bus";
60 61
61 memory-controller@2000 { 62 memory-controller@2000 {
62 compatible = "fsl,mpc8548-memory-controller"; 63 compatible = "fsl,mpc8548-memory-controller";
@@ -83,6 +84,11 @@
83 interrupts = <43 2>; 84 interrupts = <43 2>;
84 interrupt-parent = <&mpic>; 85 interrupt-parent = <&mpic>;
85 dfsrr; 86 dfsrr;
87
88 rtc@68 {
89 compatible = "dallas,ds1337";
90 reg = <0x68>;
91 };
86 }; 92 };
87 93
88 i2c@3100 { 94 i2c@3100 {
diff --git a/arch/powerpc/boot/dts/tqm8548.dts b/arch/powerpc/boot/dts/tqm8548.dts
index 2563112cabd3..58ee4185454b 100644
--- a/arch/powerpc/boot/dts/tqm8548.dts
+++ b/arch/powerpc/boot/dts/tqm8548.dts
@@ -50,13 +50,14 @@
50 reg = <0x00000000 0x00000000>; // Filled in by U-Boot 50 reg = <0x00000000 0x00000000>; // Filled in by U-Boot
51 }; 51 };
52 52
53 soc8548@e0000000 { 53 soc@e0000000 {
54 #address-cells = <1>; 54 #address-cells = <1>;
55 #size-cells = <1>; 55 #size-cells = <1>;
56 device_type = "soc"; 56 device_type = "soc";
57 ranges = <0x0 0xe0000000 0x100000>; 57 ranges = <0x0 0xe0000000 0x100000>;
58 reg = <0xe0000000 0x1000>; // CCSRBAR 58 reg = <0xe0000000 0x1000>; // CCSRBAR
59 bus-frequency = <0>; 59 bus-frequency = <0>;
60 compatible = "fsl,mpc8548-immr", "simple-bus";
60 61
61 memory-controller@2000 { 62 memory-controller@2000 {
62 compatible = "fsl,mpc8548-memory-controller"; 63 compatible = "fsl,mpc8548-memory-controller";
diff --git a/arch/powerpc/boot/wrapper b/arch/powerpc/boot/wrapper
index 644bf9d4ea00..965c237c122d 100755
--- a/arch/powerpc/boot/wrapper
+++ b/arch/powerpc/boot/wrapper
@@ -165,7 +165,7 @@ cuboot*)
165 binary=y 165 binary=y
166 gzip= 166 gzip=
167 case "$platform" in 167 case "$platform" in
168 *-mpc885ads|*-adder875*|*-ep88xc) 168 *-mpc866ads|*-mpc885ads|*-adder875*|*-ep88xc)
169 platformo=$object/cuboot-8xx.o 169 platformo=$object/cuboot-8xx.o
170 ;; 170 ;;
171 *5200*|*-motionpro) 171 *5200*|*-motionpro)
diff --git a/arch/powerpc/configs/asp8347_defconfig b/arch/powerpc/configs/83xx/asp8347_defconfig
index 60bb4d106c87..5e6780a088ce 100644
--- a/arch/powerpc/configs/asp8347_defconfig
+++ b/arch/powerpc/configs/83xx/asp8347_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.25-rc6 3# Linux kernel version: 2.6.27-rc4
4# Tue May 6 02:21:00 2008 4# Thu Aug 21 00:52:01 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -16,6 +16,7 @@ CONFIG_6xx=y
16# CONFIG_E200 is not set 16# CONFIG_E200 is not set
17CONFIG_PPC_FPU=y 17CONFIG_PPC_FPU=y
18CONFIG_FSL_EMB_PERFMON=y 18CONFIG_FSL_EMB_PERFMON=y
19# CONFIG_ALTIVEC is not set
19CONFIG_PPC_STD_MMU=y 20CONFIG_PPC_STD_MMU=y
20CONFIG_PPC_STD_MMU_32=y 21CONFIG_PPC_STD_MMU_32=y
21# CONFIG_PPC_MM_SLICES is not set 22# CONFIG_PPC_MM_SLICES is not set
@@ -31,6 +32,9 @@ CONFIG_GENERIC_CLOCKEVENTS=y
31CONFIG_GENERIC_HARDIRQS=y 32CONFIG_GENERIC_HARDIRQS=y
32# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set 33# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
33CONFIG_IRQ_PER_CPU=y 34CONFIG_IRQ_PER_CPU=y
35CONFIG_STACKTRACE_SUPPORT=y
36CONFIG_HAVE_LATENCYTOP_SUPPORT=y
37CONFIG_LOCKDEP_SUPPORT=y
34CONFIG_RWSEM_XCHGADD_ALGORITHM=y 38CONFIG_RWSEM_XCHGADD_ALGORITHM=y
35CONFIG_ARCH_HAS_ILOG2_U32=y 39CONFIG_ARCH_HAS_ILOG2_U32=y
36CONFIG_GENERIC_HWEIGHT=y 40CONFIG_GENERIC_HWEIGHT=y
@@ -50,6 +54,9 @@ CONFIG_AUDIT_ARCH=y
50CONFIG_GENERIC_BUG=y 54CONFIG_GENERIC_BUG=y
51# CONFIG_DEFAULT_UIMAGE is not set 55# CONFIG_DEFAULT_UIMAGE is not set
52CONFIG_REDBOOT=y 56CONFIG_REDBOOT=y
57CONFIG_HIBERNATE_32=y
58CONFIG_ARCH_HIBERNATION_POSSIBLE=y
59CONFIG_ARCH_SUSPEND_POSSIBLE=y
53# CONFIG_PPC_DCR_NATIVE is not set 60# CONFIG_PPC_DCR_NATIVE is not set
54# CONFIG_PPC_DCR_MMIO is not set 61# CONFIG_PPC_DCR_MMIO is not set
55CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 62CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
@@ -92,6 +99,7 @@ CONFIG_HOTPLUG=y
92CONFIG_PRINTK=y 99CONFIG_PRINTK=y
93CONFIG_BUG=y 100CONFIG_BUG=y
94CONFIG_ELF_CORE=y 101CONFIG_ELF_CORE=y
102CONFIG_PCSPKR_PLATFORM=y
95CONFIG_COMPAT_BRK=y 103CONFIG_COMPAT_BRK=y
96CONFIG_BASE_FULL=y 104CONFIG_BASE_FULL=y
97CONFIG_FUTEX=y 105CONFIG_FUTEX=y
@@ -109,24 +117,33 @@ CONFIG_SLUB=y
109# CONFIG_PROFILING is not set 117# CONFIG_PROFILING is not set
110# CONFIG_MARKERS is not set 118# CONFIG_MARKERS is not set
111CONFIG_HAVE_OPROFILE=y 119CONFIG_HAVE_OPROFILE=y
120CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
121CONFIG_HAVE_IOREMAP_PROT=y
112CONFIG_HAVE_KPROBES=y 122CONFIG_HAVE_KPROBES=y
113CONFIG_HAVE_KRETPROBES=y 123CONFIG_HAVE_KRETPROBES=y
124CONFIG_HAVE_ARCH_TRACEHOOK=y
125# CONFIG_HAVE_DMA_ATTRS is not set
126# CONFIG_USE_GENERIC_SMP_HELPERS is not set
127# CONFIG_HAVE_CLK is not set
114CONFIG_PROC_PAGE_MONITOR=y 128CONFIG_PROC_PAGE_MONITOR=y
129# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
115CONFIG_SLABINFO=y 130CONFIG_SLABINFO=y
116CONFIG_RT_MUTEXES=y 131CONFIG_RT_MUTEXES=y
117# CONFIG_TINY_SHMEM is not set 132# CONFIG_TINY_SHMEM is not set
118CONFIG_BASE_SMALL=0 133CONFIG_BASE_SMALL=0
119CONFIG_MODULES=y 134CONFIG_MODULES=y
135# CONFIG_MODULE_FORCE_LOAD is not set
120CONFIG_MODULE_UNLOAD=y 136CONFIG_MODULE_UNLOAD=y
121# CONFIG_MODULE_FORCE_UNLOAD is not set 137# CONFIG_MODULE_FORCE_UNLOAD is not set
122# CONFIG_MODVERSIONS is not set 138# CONFIG_MODVERSIONS is not set
123# CONFIG_MODULE_SRCVERSION_ALL is not set 139# CONFIG_MODULE_SRCVERSION_ALL is not set
124# CONFIG_KMOD is not set 140CONFIG_KMOD=y
125CONFIG_BLOCK=y 141CONFIG_BLOCK=y
126# CONFIG_LBD is not set 142# CONFIG_LBD is not set
127# CONFIG_BLK_DEV_IO_TRACE is not set 143# CONFIG_BLK_DEV_IO_TRACE is not set
128# CONFIG_LSF is not set 144# CONFIG_LSF is not set
129# CONFIG_BLK_DEV_BSG is not set 145# CONFIG_BLK_DEV_BSG is not set
146# CONFIG_BLK_DEV_INTEGRITY is not set
130 147
131# 148#
132# IO Schedulers 149# IO Schedulers
@@ -145,38 +162,49 @@ CONFIG_CLASSIC_RCU=y
145# 162#
146# Platform support 163# Platform support
147# 164#
148# CONFIG_PPC_MULTIPLATFORM is not set 165CONFIG_PPC_MULTIPLATFORM=y
149# CONFIG_PPC_82xx is not set 166CONFIG_CLASSIC32=y
150CONFIG_PPC_83xx=y 167CONFIG_PPC_CHRP=y
151# CONFIG_PPC_86xx is not set 168# CONFIG_MPC5121_ADS is not set
152# CONFIG_PPC_MPC512x is not set 169# CONFIG_MPC5121_GENERIC is not set
153# CONFIG_PPC_MPC5121 is not set 170# CONFIG_PPC_MPC52xx is not set
171CONFIG_PPC_PMAC=y
154# CONFIG_PPC_CELL is not set 172# CONFIG_PPC_CELL is not set
155# CONFIG_PPC_CELL_NATIVE is not set 173# CONFIG_PPC_CELL_NATIVE is not set
174# CONFIG_PPC_82xx is not set
156# CONFIG_PQ2ADS is not set 175# CONFIG_PQ2ADS is not set
157CONFIG_MPC83xx=y 176CONFIG_PPC_83xx=y
158# CONFIG_MPC831x_RDB is not set 177# CONFIG_MPC831x_RDB is not set
159# CONFIG_MPC832x_MDS is not set 178# CONFIG_MPC832x_MDS is not set
160# CONFIG_MPC832x_RDB is not set 179# CONFIG_MPC832x_RDB is not set
161# CONFIG_MPC834x_MDS is not set 180# CONFIG_MPC834x_MDS is not set
162# CONFIG_MPC834x_ITX is not set 181# CONFIG_MPC834x_ITX is not set
163# CONFIG_MPC836x_MDS is not set 182# CONFIG_MPC836x_MDS is not set
183# CONFIG_MPC836x_RDK is not set
164# CONFIG_MPC837x_MDS is not set 184# CONFIG_MPC837x_MDS is not set
165# CONFIG_MPC837x_RDB is not set 185# CONFIG_MPC837x_RDB is not set
166# CONFIG_SBC834x is not set 186# CONFIG_SBC834x is not set
167CONFIG_ASP834x=y 187CONFIG_ASP834x=y
168CONFIG_PPC_MPC834x=y 188CONFIG_PPC_MPC834x=y
189# CONFIG_PPC_86xx is not set
190# CONFIG_EMBEDDED6xx is not set
191CONFIG_PPC_NATIVE=y
192# CONFIG_UDBG_RTAS_CONSOLE is not set
169CONFIG_IPIC=y 193CONFIG_IPIC=y
170# CONFIG_MPIC is not set 194CONFIG_MPIC=y
171# CONFIG_MPIC_WEIRD is not set 195# CONFIG_MPIC_WEIRD is not set
172# CONFIG_PPC_I8259 is not set 196CONFIG_PPC_I8259=y
173# CONFIG_PPC_RTAS is not set 197CONFIG_PPC_RTAS=y
198# CONFIG_RTAS_ERROR_LOGGING is not set
199CONFIG_RTAS_PROC=y
174# CONFIG_MMIO_NVRAM is not set 200# CONFIG_MMIO_NVRAM is not set
175# CONFIG_PPC_MPC106 is not set 201CONFIG_PPC_MPC106=y
176# CONFIG_PPC_970_NAP is not set 202# CONFIG_PPC_970_NAP is not set
177# CONFIG_PPC_INDIRECT_IO is not set 203# CONFIG_PPC_INDIRECT_IO is not set
178# CONFIG_GENERIC_IOMAP is not set 204# CONFIG_GENERIC_IOMAP is not set
179# CONFIG_CPU_FREQ is not set 205# CONFIG_CPU_FREQ is not set
206# CONFIG_PPC601_SYNC_FIX is not set
207# CONFIG_TAU is not set
180# CONFIG_FSL_ULI1575 is not set 208# CONFIG_FSL_ULI1575 is not set
181 209
182# 210#
@@ -192,7 +220,7 @@ CONFIG_HZ_250=y
192# CONFIG_HZ_300 is not set 220# CONFIG_HZ_300 is not set
193# CONFIG_HZ_1000 is not set 221# CONFIG_HZ_1000 is not set
194CONFIG_HZ=250 222CONFIG_HZ=250
195# CONFIG_SCHED_HRTICK is not set 223CONFIG_SCHED_HRTICK=y
196CONFIG_PREEMPT_NONE=y 224CONFIG_PREEMPT_NONE=y
197# CONFIG_PREEMPT_VOLUNTARY is not set 225# CONFIG_PREEMPT_VOLUNTARY is not set
198# CONFIG_PREEMPT is not set 226# CONFIG_PREEMPT is not set
@@ -202,6 +230,7 @@ CONFIG_BINFMT_ELF=y
202CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y 230CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
203CONFIG_ARCH_HAS_WALK_MEMORY=y 231CONFIG_ARCH_HAS_WALK_MEMORY=y
204CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y 232CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
233# CONFIG_KEXEC is not set
205CONFIG_ARCH_FLATMEM_ENABLE=y 234CONFIG_ARCH_FLATMEM_ENABLE=y
206CONFIG_ARCH_POPULATES_NODE_MAP=y 235CONFIG_ARCH_POPULATES_NODE_MAP=y
207CONFIG_SELECT_MEMORY_MODEL=y 236CONFIG_SELECT_MEMORY_MODEL=y
@@ -212,13 +241,17 @@ CONFIG_FLATMEM=y
212CONFIG_FLAT_NODE_MEM_MAP=y 241CONFIG_FLAT_NODE_MEM_MAP=y
213# CONFIG_SPARSEMEM_STATIC is not set 242# CONFIG_SPARSEMEM_STATIC is not set
214# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set 243# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
244CONFIG_PAGEFLAGS_EXTENDED=y
215CONFIG_SPLIT_PTLOCK_CPUS=4 245CONFIG_SPLIT_PTLOCK_CPUS=4
246CONFIG_MIGRATION=y
216# CONFIG_RESOURCES_64BIT is not set 247# CONFIG_RESOURCES_64BIT is not set
217CONFIG_ZONE_DMA_FLAG=1 248CONFIG_ZONE_DMA_FLAG=1
218CONFIG_BOUNCE=y 249CONFIG_BOUNCE=y
219CONFIG_VIRT_TO_BUS=y 250CONFIG_VIRT_TO_BUS=y
251CONFIG_FORCE_MAX_ZONEORDER=11
220CONFIG_PROC_DEVICETREE=y 252CONFIG_PROC_DEVICETREE=y
221# CONFIG_CMDLINE_BOOL is not set 253# CONFIG_CMDLINE_BOOL is not set
254CONFIG_EXTRA_TARGETS=""
222# CONFIG_PM is not set 255# CONFIG_PM is not set
223CONFIG_SECCOMP=y 256CONFIG_SECCOMP=y
224CONFIG_ISA_DMA_API=y 257CONFIG_ISA_DMA_API=y
@@ -226,10 +259,13 @@ CONFIG_ISA_DMA_API=y
226# 259#
227# Bus options 260# Bus options
228# 261#
262# CONFIG_ISA is not set
229CONFIG_ZONE_DMA=y 263CONFIG_ZONE_DMA=y
230CONFIG_GENERIC_ISA_DMA=y 264CONFIG_GENERIC_ISA_DMA=y
231CONFIG_PPC_INDIRECT_PCI=y 265CONFIG_PPC_INDIRECT_PCI=y
232CONFIG_FSL_SOC=y 266CONFIG_FSL_SOC=y
267CONFIG_FSL_PCI=y
268CONFIG_PPC_PCI_CHOICE=y
233CONFIG_PCI=y 269CONFIG_PCI=y
234CONFIG_PCI_DOMAINS=y 270CONFIG_PCI_DOMAINS=y
235CONFIG_PCI_SYSCALL=y 271CONFIG_PCI_SYSCALL=y
@@ -239,6 +275,7 @@ CONFIG_ARCH_SUPPORTS_MSI=y
239CONFIG_PCI_LEGACY=y 275CONFIG_PCI_LEGACY=y
240# CONFIG_PCCARD is not set 276# CONFIG_PCCARD is not set
241# CONFIG_HOTPLUG_PCI is not set 277# CONFIG_HOTPLUG_PCI is not set
278# CONFIG_HAS_RAPIDIO is not set
242 279
243# 280#
244# Advanced setup 281# Advanced setup
@@ -248,15 +285,11 @@ CONFIG_PCI_LEGACY=y
248# 285#
249# Default settings for advanced configuration options are used 286# Default settings for advanced configuration options are used
250# 287#
251CONFIG_HIGHMEM_START=0xfe000000
252CONFIG_LOWMEM_SIZE=0x30000000 288CONFIG_LOWMEM_SIZE=0x30000000
289CONFIG_PAGE_OFFSET=0xc0000000
253CONFIG_KERNEL_START=0xc0000000 290CONFIG_KERNEL_START=0xc0000000
291CONFIG_PHYSICAL_START=0x00000000
254CONFIG_TASK_SIZE=0xc0000000 292CONFIG_TASK_SIZE=0xc0000000
255CONFIG_BOOT_LOAD=0x00800000
256
257#
258# Networking
259#
260CONFIG_NET=y 293CONFIG_NET=y
261 294
262# 295#
@@ -300,8 +333,6 @@ CONFIG_TCP_CONG_CUBIC=y
300CONFIG_DEFAULT_TCP_CONG="cubic" 333CONFIG_DEFAULT_TCP_CONG="cubic"
301# CONFIG_TCP_MD5SIG is not set 334# CONFIG_TCP_MD5SIG is not set
302# CONFIG_IPV6 is not set 335# CONFIG_IPV6 is not set
303# CONFIG_INET6_XFRM_TUNNEL is not set
304# CONFIG_INET6_TUNNEL is not set
305# CONFIG_NETWORK_SECMARK is not set 336# CONFIG_NETWORK_SECMARK is not set
306# CONFIG_NETFILTER is not set 337# CONFIG_NETFILTER is not set
307# CONFIG_IP_DCCP is not set 338# CONFIG_IP_DCCP is not set
@@ -363,6 +394,7 @@ CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
363# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set 394# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
364# CONFIG_MTD_CMDLINE_PARTS is not set 395# CONFIG_MTD_CMDLINE_PARTS is not set
365CONFIG_MTD_OF_PARTS=y 396CONFIG_MTD_OF_PARTS=y
397# CONFIG_MTD_AR7_PARTS is not set
366 398
367# 399#
368# User Modules And Translation Layers 400# User Modules And Translation Layers
@@ -434,9 +466,11 @@ CONFIG_MTD_PHYSMAP_OF=y
434# 466#
435# CONFIG_MTD_UBI is not set 467# CONFIG_MTD_UBI is not set
436CONFIG_OF_DEVICE=y 468CONFIG_OF_DEVICE=y
469CONFIG_OF_I2C=y
437# CONFIG_PARPORT is not set 470# CONFIG_PARPORT is not set
438CONFIG_BLK_DEV=y 471CONFIG_BLK_DEV=y
439# CONFIG_BLK_DEV_FD is not set 472# CONFIG_BLK_DEV_FD is not set
473# CONFIG_MAC_FLOPPY is not set
440# CONFIG_BLK_CPQ_DA is not set 474# CONFIG_BLK_CPQ_DA is not set
441# CONFIG_BLK_CPQ_CISS_DA is not set 475# CONFIG_BLK_CPQ_CISS_DA is not set
442# CONFIG_BLK_DEV_DAC960 is not set 476# CONFIG_BLK_DEV_DAC960 is not set
@@ -453,12 +487,14 @@ CONFIG_BLK_DEV_RAM_SIZE=32768
453# CONFIG_BLK_DEV_XIP is not set 487# CONFIG_BLK_DEV_XIP is not set
454# CONFIG_CDROM_PKTCDVD is not set 488# CONFIG_CDROM_PKTCDVD is not set
455# CONFIG_ATA_OVER_ETH is not set 489# CONFIG_ATA_OVER_ETH is not set
490# CONFIG_BLK_DEV_HD is not set
456CONFIG_MISC_DEVICES=y 491CONFIG_MISC_DEVICES=y
457# CONFIG_PHANTOM is not set 492# CONFIG_PHANTOM is not set
458# CONFIG_EEPROM_93CX6 is not set 493# CONFIG_EEPROM_93CX6 is not set
459# CONFIG_SGI_IOC4 is not set 494# CONFIG_SGI_IOC4 is not set
460# CONFIG_TIFM_CORE is not set 495# CONFIG_TIFM_CORE is not set
461# CONFIG_ENCLOSURE_SERVICES is not set 496# CONFIG_ENCLOSURE_SERVICES is not set
497# CONFIG_HP_ILO is not set
462CONFIG_HAVE_IDE=y 498CONFIG_HAVE_IDE=y
463# CONFIG_IDE is not set 499# CONFIG_IDE is not set
464 500
@@ -476,12 +512,15 @@ CONFIG_HAVE_IDE=y
476# 512#
477# IEEE 1394 (FireWire) support 513# IEEE 1394 (FireWire) support
478# 514#
515
516#
517# Enable only one of the two stacks, unless you know what you are doing
518#
479# CONFIG_FIREWIRE is not set 519# CONFIG_FIREWIRE is not set
480# CONFIG_IEEE1394 is not set 520# CONFIG_IEEE1394 is not set
481# CONFIG_I2O is not set 521# CONFIG_I2O is not set
482# CONFIG_MACINTOSH_DRIVERS is not set 522# CONFIG_MACINTOSH_DRIVERS is not set
483CONFIG_NETDEVICES=y 523CONFIG_NETDEVICES=y
484# CONFIG_NETDEVICES_MULTIQUEUE is not set
485# CONFIG_DUMMY is not set 524# CONFIG_DUMMY is not set
486# CONFIG_BONDING is not set 525# CONFIG_BONDING is not set
487# CONFIG_MACVLAN is not set 526# CONFIG_MACVLAN is not set
@@ -508,6 +547,8 @@ CONFIG_PHYLIB=y
508# CONFIG_MDIO_BITBANG is not set 547# CONFIG_MDIO_BITBANG is not set
509CONFIG_NET_ETHERNET=y 548CONFIG_NET_ETHERNET=y
510CONFIG_MII=y 549CONFIG_MII=y
550# CONFIG_MACE is not set
551# CONFIG_BMAC is not set
511# CONFIG_HAPPYMEAL is not set 552# CONFIG_HAPPYMEAL is not set
512# CONFIG_SUNGEM is not set 553# CONFIG_SUNGEM is not set
513# CONFIG_CASSINI is not set 554# CONFIG_CASSINI is not set
@@ -525,7 +566,6 @@ CONFIG_NETDEV_1000=y
525# CONFIG_DL2K is not set 566# CONFIG_DL2K is not set
526# CONFIG_E1000 is not set 567# CONFIG_E1000 is not set
527# CONFIG_E1000E is not set 568# CONFIG_E1000E is not set
528# CONFIG_E1000E_ENABLED is not set
529# CONFIG_IP1000 is not set 569# CONFIG_IP1000 is not set
530# CONFIG_IGB is not set 570# CONFIG_IGB is not set
531# CONFIG_NS83820 is not set 571# CONFIG_NS83820 is not set
@@ -535,14 +575,14 @@ CONFIG_NETDEV_1000=y
535# CONFIG_SIS190 is not set 575# CONFIG_SIS190 is not set
536# CONFIG_SKGE is not set 576# CONFIG_SKGE is not set
537# CONFIG_SKY2 is not set 577# CONFIG_SKY2 is not set
538# CONFIG_SK98LIN is not set
539# CONFIG_VIA_VELOCITY is not set 578# CONFIG_VIA_VELOCITY is not set
540# CONFIG_TIGON3 is not set 579# CONFIG_TIGON3 is not set
541# CONFIG_BNX2 is not set 580# CONFIG_BNX2 is not set
542CONFIG_GIANFAR=y 581CONFIG_GIANFAR=y
543# CONFIG_GFAR_NAPI is not set 582# CONFIG_MV643XX_ETH is not set
544# CONFIG_QLA3XXX is not set 583# CONFIG_QLA3XXX is not set
545# CONFIG_ATL1 is not set 584# CONFIG_ATL1 is not set
585# CONFIG_ATL1E is not set
546# CONFIG_NETDEV_10000 is not set 586# CONFIG_NETDEV_10000 is not set
547# CONFIG_TR is not set 587# CONFIG_TR is not set
548 588
@@ -551,6 +591,7 @@ CONFIG_GIANFAR=y
551# 591#
552# CONFIG_WLAN_PRE80211 is not set 592# CONFIG_WLAN_PRE80211 is not set
553# CONFIG_WLAN_80211 is not set 593# CONFIG_WLAN_80211 is not set
594# CONFIG_IWLWIFI_LEDS is not set
554 595
555# 596#
556# USB Network Adapters 597# USB Network Adapters
@@ -606,6 +647,7 @@ CONFIG_INPUT=y
606# Character devices 647# Character devices
607# 648#
608# CONFIG_VT is not set 649# CONFIG_VT is not set
650CONFIG_DEVKMEM=y
609# CONFIG_SERIAL_NONSTANDARD is not set 651# CONFIG_SERIAL_NONSTANDARD is not set
610# CONFIG_NOZOMI is not set 652# CONFIG_NOZOMI is not set
611 653
@@ -625,16 +667,17 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=4
625# CONFIG_SERIAL_UARTLITE is not set 667# CONFIG_SERIAL_UARTLITE is not set
626CONFIG_SERIAL_CORE=y 668CONFIG_SERIAL_CORE=y
627CONFIG_SERIAL_CORE_CONSOLE=y 669CONFIG_SERIAL_CORE_CONSOLE=y
670# CONFIG_SERIAL_PMACZILOG is not set
628# CONFIG_SERIAL_JSM is not set 671# CONFIG_SERIAL_JSM is not set
629# CONFIG_SERIAL_OF_PLATFORM is not set 672# CONFIG_SERIAL_OF_PLATFORM is not set
630CONFIG_UNIX98_PTYS=y 673CONFIG_UNIX98_PTYS=y
631CONFIG_LEGACY_PTYS=y 674CONFIG_LEGACY_PTYS=y
632CONFIG_LEGACY_PTY_COUNT=256 675CONFIG_LEGACY_PTY_COUNT=256
676# CONFIG_BRIQ_PANEL is not set
677# CONFIG_HVC_RTAS is not set
633# CONFIG_IPMI_HANDLER is not set 678# CONFIG_IPMI_HANDLER is not set
634# CONFIG_HW_RANDOM is not set 679# CONFIG_HW_RANDOM is not set
635# CONFIG_NVRAM is not set 680# CONFIG_NVRAM is not set
636CONFIG_GEN_RTC=y
637# CONFIG_GEN_RTC_X is not set
638# CONFIG_R3964 is not set 681# CONFIG_R3964 is not set
639# CONFIG_APPLICOM is not set 682# CONFIG_APPLICOM is not set
640# CONFIG_RAW_DRIVER is not set 683# CONFIG_RAW_DRIVER is not set
@@ -643,16 +686,14 @@ CONFIG_DEVPORT=y
643CONFIG_I2C=y 686CONFIG_I2C=y
644CONFIG_I2C_BOARDINFO=y 687CONFIG_I2C_BOARDINFO=y
645CONFIG_I2C_CHARDEV=y 688CONFIG_I2C_CHARDEV=y
689CONFIG_I2C_HELPER_AUTO=y
646 690
647# 691#
648# I2C Algorithms 692# I2C Hardware Bus support
649# 693#
650# CONFIG_I2C_ALGOBIT is not set
651# CONFIG_I2C_ALGOPCF is not set
652# CONFIG_I2C_ALGOPCA is not set
653 694
654# 695#
655# I2C Hardware Bus support 696# PC SMBus host controller drivers
656# 697#
657# CONFIG_I2C_ALI1535 is not set 698# CONFIG_I2C_ALI1535 is not set
658# CONFIG_I2C_ALI1563 is not set 699# CONFIG_I2C_ALI1563 is not set
@@ -660,50 +701,70 @@ CONFIG_I2C_CHARDEV=y
660# CONFIG_I2C_AMD756 is not set 701# CONFIG_I2C_AMD756 is not set
661# CONFIG_I2C_AMD8111 is not set 702# CONFIG_I2C_AMD8111 is not set
662# CONFIG_I2C_I801 is not set 703# CONFIG_I2C_I801 is not set
663# CONFIG_I2C_I810 is not set 704# CONFIG_I2C_ISCH is not set
664# CONFIG_I2C_PIIX4 is not set 705# CONFIG_I2C_PIIX4 is not set
665CONFIG_I2C_MPC=y
666# CONFIG_I2C_NFORCE2 is not set 706# CONFIG_I2C_NFORCE2 is not set
667# CONFIG_I2C_OCORES is not set
668# CONFIG_I2C_PARPORT_LIGHT is not set
669# CONFIG_I2C_PROSAVAGE is not set
670# CONFIG_I2C_SAVAGE4 is not set
671# CONFIG_I2C_SIMTEC is not set
672# CONFIG_I2C_SIS5595 is not set 707# CONFIG_I2C_SIS5595 is not set
673# CONFIG_I2C_SIS630 is not set 708# CONFIG_I2C_SIS630 is not set
674# CONFIG_I2C_SIS96X is not set 709# CONFIG_I2C_SIS96X is not set
675# CONFIG_I2C_TAOS_EVM is not set
676# CONFIG_I2C_STUB is not set
677# CONFIG_I2C_TINY_USB is not set
678# CONFIG_I2C_VIA is not set 710# CONFIG_I2C_VIA is not set
679# CONFIG_I2C_VIAPRO is not set 711# CONFIG_I2C_VIAPRO is not set
712
713#
714# Mac SMBus host controller drivers
715#
716# CONFIG_I2C_HYDRA is not set
717CONFIG_I2C_POWERMAC=y
718
719#
720# I2C system bus drivers (mostly embedded / system-on-chip)
721#
722CONFIG_I2C_MPC=y
723# CONFIG_I2C_OCORES is not set
724# CONFIG_I2C_SIMTEC is not set
725
726#
727# External I2C/SMBus adapter drivers
728#
729# CONFIG_I2C_PARPORT_LIGHT is not set
730# CONFIG_I2C_TAOS_EVM is not set
731# CONFIG_I2C_TINY_USB is not set
732
733#
734# Graphics adapter I2C/DDC channel drivers
735#
680# CONFIG_I2C_VOODOO3 is not set 736# CONFIG_I2C_VOODOO3 is not set
681 737
682# 738#
739# Other I2C/SMBus bus drivers
740#
741# CONFIG_I2C_PCA_PLATFORM is not set
742# CONFIG_I2C_STUB is not set
743
744#
683# Miscellaneous I2C Chip support 745# Miscellaneous I2C Chip support
684# 746#
685# CONFIG_DS1682 is not set 747# CONFIG_DS1682 is not set
748# CONFIG_AT24 is not set
686# CONFIG_SENSORS_EEPROM is not set 749# CONFIG_SENSORS_EEPROM is not set
687# CONFIG_SENSORS_PCF8574 is not set 750# CONFIG_SENSORS_PCF8574 is not set
688# CONFIG_PCF8575 is not set 751# CONFIG_PCF8575 is not set
752# CONFIG_SENSORS_PCA9539 is not set
689# CONFIG_SENSORS_PCF8591 is not set 753# CONFIG_SENSORS_PCF8591 is not set
690# CONFIG_TPS65010 is not set
691# CONFIG_SENSORS_MAX6875 is not set 754# CONFIG_SENSORS_MAX6875 is not set
692# CONFIG_SENSORS_TSL2550 is not set 755# CONFIG_SENSORS_TSL2550 is not set
693# CONFIG_I2C_DEBUG_CORE is not set 756# CONFIG_I2C_DEBUG_CORE is not set
694# CONFIG_I2C_DEBUG_ALGO is not set 757# CONFIG_I2C_DEBUG_ALGO is not set
695# CONFIG_I2C_DEBUG_BUS is not set 758# CONFIG_I2C_DEBUG_BUS is not set
696# CONFIG_I2C_DEBUG_CHIP is not set 759# CONFIG_I2C_DEBUG_CHIP is not set
697
698#
699# SPI support
700#
701# CONFIG_SPI is not set 760# CONFIG_SPI is not set
702# CONFIG_SPI_MASTER is not set 761CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
762# CONFIG_GPIOLIB is not set
703# CONFIG_W1 is not set 763# CONFIG_W1 is not set
704# CONFIG_POWER_SUPPLY is not set 764# CONFIG_POWER_SUPPLY is not set
705CONFIG_HWMON=y 765CONFIG_HWMON=y
706# CONFIG_HWMON_VID is not set 766# CONFIG_HWMON_VID is not set
767# CONFIG_SENSORS_AD7414 is not set
707# CONFIG_SENSORS_AD7418 is not set 768# CONFIG_SENSORS_AD7418 is not set
708# CONFIG_SENSORS_ADM1021 is not set 769# CONFIG_SENSORS_ADM1021 is not set
709# CONFIG_SENSORS_ADM1025 is not set 770# CONFIG_SENSORS_ADM1025 is not set
@@ -713,6 +774,7 @@ CONFIG_HWMON=y
713# CONFIG_SENSORS_ADM9240 is not set 774# CONFIG_SENSORS_ADM9240 is not set
714# CONFIG_SENSORS_ADT7470 is not set 775# CONFIG_SENSORS_ADT7470 is not set
715# CONFIG_SENSORS_ADT7473 is not set 776# CONFIG_SENSORS_ADT7473 is not set
777# CONFIG_SENSORS_AMS is not set
716# CONFIG_SENSORS_ATXP1 is not set 778# CONFIG_SENSORS_ATXP1 is not set
717# CONFIG_SENSORS_DS1621 is not set 779# CONFIG_SENSORS_DS1621 is not set
718# CONFIG_SENSORS_I5K_AMB is not set 780# CONFIG_SENSORS_I5K_AMB is not set
@@ -757,6 +819,7 @@ CONFIG_HWMON=y
757# CONFIG_SENSORS_W83627EHF is not set 819# CONFIG_SENSORS_W83627EHF is not set
758# CONFIG_HWMON_DEBUG_CHIP is not set 820# CONFIG_HWMON_DEBUG_CHIP is not set
759CONFIG_THERMAL=y 821CONFIG_THERMAL=y
822# CONFIG_THERMAL_HWMON is not set
760CONFIG_WATCHDOG=y 823CONFIG_WATCHDOG=y
761# CONFIG_WATCHDOG_NOWAYOUT is not set 824# CONFIG_WATCHDOG_NOWAYOUT is not set
762 825
@@ -764,7 +827,9 @@ CONFIG_WATCHDOG=y
764# Watchdog Device Drivers 827# Watchdog Device Drivers
765# 828#
766# CONFIG_SOFT_WATCHDOG is not set 829# CONFIG_SOFT_WATCHDOG is not set
767CONFIG_83xx_WDT=y 830# CONFIG_ALIM7101_WDT is not set
831# CONFIG_8xxx_WDT is not set
832# CONFIG_WATCHDOG_RTAS is not set
768 833
769# 834#
770# PCI-based Watchdog Cards 835# PCI-based Watchdog Cards
@@ -786,13 +851,25 @@ CONFIG_SSB_POSSIBLE=y
786# 851#
787# Multifunction device drivers 852# Multifunction device drivers
788# 853#
854# CONFIG_MFD_CORE is not set
789# CONFIG_MFD_SM501 is not set 855# CONFIG_MFD_SM501 is not set
856# CONFIG_HTC_PASIC3 is not set
857# CONFIG_MFD_TMIO is not set
790 858
791# 859#
792# Multimedia devices 860# Multimedia devices
793# 861#
862
863#
864# Multimedia core support
865#
794# CONFIG_VIDEO_DEV is not set 866# CONFIG_VIDEO_DEV is not set
795# CONFIG_DVB_CORE is not set 867# CONFIG_DVB_CORE is not set
868# CONFIG_VIDEO_MEDIA is not set
869
870#
871# Multimedia drivers
872#
796CONFIG_DAB=y 873CONFIG_DAB=y
797# CONFIG_USB_DABUSB is not set 874# CONFIG_USB_DABUSB is not set
798 875
@@ -810,10 +887,6 @@ CONFIG_VIDEO_OUTPUT_CONTROL=m
810# Display device support 887# Display device support
811# 888#
812# CONFIG_DISPLAY_SUPPORT is not set 889# CONFIG_DISPLAY_SUPPORT is not set
813
814#
815# Sound
816#
817# CONFIG_SOUND is not set 890# CONFIG_SOUND is not set
818# CONFIG_HID_SUPPORT is not set 891# CONFIG_HID_SUPPORT is not set
819CONFIG_USB_SUPPORT=y 892CONFIG_USB_SUPPORT=y
@@ -831,16 +904,21 @@ CONFIG_USB=y
831CONFIG_USB_DEVICE_CLASS=y 904CONFIG_USB_DEVICE_CLASS=y
832# CONFIG_USB_DYNAMIC_MINORS is not set 905# CONFIG_USB_DYNAMIC_MINORS is not set
833# CONFIG_USB_OTG is not set 906# CONFIG_USB_OTG is not set
907# CONFIG_USB_OTG_WHITELIST is not set
908# CONFIG_USB_OTG_BLACKLIST_HUB is not set
909CONFIG_USB_MON=y
834 910
835# 911#
836# USB Host Controller Drivers 912# USB Host Controller Drivers
837# 913#
914# CONFIG_USB_C67X00_HCD is not set
838CONFIG_USB_EHCI_HCD=y 915CONFIG_USB_EHCI_HCD=y
839CONFIG_USB_EHCI_ROOT_HUB_TT=y 916CONFIG_USB_EHCI_ROOT_HUB_TT=y
840# CONFIG_USB_EHCI_TT_NEWSCHED is not set 917# CONFIG_USB_EHCI_TT_NEWSCHED is not set
841CONFIG_USB_EHCI_FSL=y 918CONFIG_USB_EHCI_FSL=y
842CONFIG_USB_EHCI_HCD_PPC_OF=y 919CONFIG_USB_EHCI_HCD_PPC_OF=y
843# CONFIG_USB_ISP116X_HCD is not set 920# CONFIG_USB_ISP116X_HCD is not set
921# CONFIG_USB_ISP1760_HCD is not set
844# CONFIG_USB_OHCI_HCD is not set 922# CONFIG_USB_OHCI_HCD is not set
845# CONFIG_USB_UHCI_HCD is not set 923# CONFIG_USB_UHCI_HCD is not set
846# CONFIG_USB_SL811_HCD is not set 924# CONFIG_USB_SL811_HCD is not set
@@ -851,6 +929,7 @@ CONFIG_USB_EHCI_HCD_PPC_OF=y
851# 929#
852# CONFIG_USB_ACM is not set 930# CONFIG_USB_ACM is not set
853# CONFIG_USB_PRINTER is not set 931# CONFIG_USB_PRINTER is not set
932# CONFIG_USB_WDM is not set
854 933
855# 934#
856# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 935# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
@@ -865,7 +944,6 @@ CONFIG_USB_EHCI_HCD_PPC_OF=y
865# USB Imaging devices 944# USB Imaging devices
866# 945#
867# CONFIG_USB_MDC800 is not set 946# CONFIG_USB_MDC800 is not set
868CONFIG_USB_MON=y
869 947
870# 948#
871# USB port drivers 949# USB port drivers
@@ -878,7 +956,6 @@ CONFIG_USB_MON=y
878# CONFIG_USB_EMI62 is not set 956# CONFIG_USB_EMI62 is not set
879# CONFIG_USB_EMI26 is not set 957# CONFIG_USB_EMI26 is not set
880# CONFIG_USB_ADUTUX is not set 958# CONFIG_USB_ADUTUX is not set
881# CONFIG_USB_AUERSWALD is not set
882# CONFIG_USB_RIO500 is not set 959# CONFIG_USB_RIO500 is not set
883# CONFIG_USB_LEGOTOWER is not set 960# CONFIG_USB_LEGOTOWER is not set
884# CONFIG_USB_LCD is not set 961# CONFIG_USB_LCD is not set
@@ -894,18 +971,16 @@ CONFIG_USB_MON=y
894# CONFIG_USB_LD is not set 971# CONFIG_USB_LD is not set
895# CONFIG_USB_TRANCEVIBRATOR is not set 972# CONFIG_USB_TRANCEVIBRATOR is not set
896# CONFIG_USB_IOWARRIOR is not set 973# CONFIG_USB_IOWARRIOR is not set
974# CONFIG_USB_ISIGHTFW is not set
897# CONFIG_USB_GADGET is not set 975# CONFIG_USB_GADGET is not set
898# CONFIG_MMC is not set 976# CONFIG_MMC is not set
899# CONFIG_MEMSTICK is not set 977# CONFIG_MEMSTICK is not set
900# CONFIG_NEW_LEDS is not set 978# CONFIG_NEW_LEDS is not set
979# CONFIG_ACCESSIBILITY is not set
901# CONFIG_INFINIBAND is not set 980# CONFIG_INFINIBAND is not set
902# CONFIG_EDAC is not set 981# CONFIG_EDAC is not set
903CONFIG_RTC_LIB=y 982CONFIG_RTC_LIB=y
904CONFIG_RTC_CLASS=y 983CONFIG_RTC_CLASS=y
905
906#
907# Conflicting RTC option has been selected, check GEN_RTC and RTC
908#
909CONFIG_RTC_HCTOSYS=y 984CONFIG_RTC_HCTOSYS=y
910CONFIG_RTC_HCTOSYS_DEVICE="rtc0" 985CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
911# CONFIG_RTC_DEBUG is not set 986# CONFIG_RTC_DEBUG is not set
@@ -933,6 +1008,7 @@ CONFIG_RTC_DRV_DS1374=y
933# CONFIG_RTC_DRV_PCF8583 is not set 1008# CONFIG_RTC_DRV_PCF8583 is not set
934# CONFIG_RTC_DRV_M41T80 is not set 1009# CONFIG_RTC_DRV_M41T80 is not set
935# CONFIG_RTC_DRV_S35390A is not set 1010# CONFIG_RTC_DRV_S35390A is not set
1011# CONFIG_RTC_DRV_FM3130 is not set
936 1012
937# 1013#
938# SPI RTC drivers 1014# SPI RTC drivers
@@ -953,11 +1029,8 @@ CONFIG_RTC_DRV_DS1374=y
953# 1029#
954# on-CPU RTC drivers 1030# on-CPU RTC drivers
955# 1031#
1032# CONFIG_RTC_DRV_PPC is not set
956# CONFIG_DMADEVICES is not set 1033# CONFIG_DMADEVICES is not set
957
958#
959# Userspace I/O
960#
961# CONFIG_UIO is not set 1034# CONFIG_UIO is not set
962 1035
963# 1036#
@@ -977,7 +1050,6 @@ CONFIG_FS_MBCACHE=y
977# CONFIG_JFS_FS is not set 1050# CONFIG_JFS_FS is not set
978# CONFIG_FS_POSIX_ACL is not set 1051# CONFIG_FS_POSIX_ACL is not set
979# CONFIG_XFS_FS is not set 1052# CONFIG_XFS_FS is not set
980# CONFIG_GFS2_FS is not set
981# CONFIG_OCFS2_FS is not set 1053# CONFIG_OCFS2_FS is not set
982CONFIG_DNOTIFY=y 1054CONFIG_DNOTIFY=y
983CONFIG_INOTIFY=y 1055CONFIG_INOTIFY=y
@@ -1036,6 +1108,7 @@ CONFIG_JFFS2_RTIME=y
1036# CONFIG_CRAMFS is not set 1108# CONFIG_CRAMFS is not set
1037# CONFIG_VXFS_FS is not set 1109# CONFIG_VXFS_FS is not set
1038# CONFIG_MINIX_FS is not set 1110# CONFIG_MINIX_FS is not set
1111# CONFIG_OMFS_FS is not set
1039# CONFIG_HPFS_FS is not set 1112# CONFIG_HPFS_FS is not set
1040# CONFIG_QNX4FS_FS is not set 1113# CONFIG_QNX4FS_FS is not set
1041# CONFIG_ROMFS_FS is not set 1114# CONFIG_ROMFS_FS is not set
@@ -1046,15 +1119,13 @@ CONFIG_NFS_FS=y
1046CONFIG_NFS_V3=y 1119CONFIG_NFS_V3=y
1047# CONFIG_NFS_V3_ACL is not set 1120# CONFIG_NFS_V3_ACL is not set
1048CONFIG_NFS_V4=y 1121CONFIG_NFS_V4=y
1049# CONFIG_NFS_DIRECTIO is not set
1050# CONFIG_NFSD is not set
1051CONFIG_ROOT_NFS=y 1122CONFIG_ROOT_NFS=y
1123# CONFIG_NFSD is not set
1052CONFIG_LOCKD=y 1124CONFIG_LOCKD=y
1053CONFIG_LOCKD_V4=y 1125CONFIG_LOCKD_V4=y
1054CONFIG_NFS_COMMON=y 1126CONFIG_NFS_COMMON=y
1055CONFIG_SUNRPC=y 1127CONFIG_SUNRPC=y
1056CONFIG_SUNRPC_GSS=y 1128CONFIG_SUNRPC_GSS=y
1057# CONFIG_SUNRPC_BIND34 is not set
1058CONFIG_RPCSEC_GSS_KRB5=y 1129CONFIG_RPCSEC_GSS_KRB5=y
1059# CONFIG_RPCSEC_GSS_SPKM3 is not set 1130# CONFIG_RPCSEC_GSS_SPKM3 is not set
1060# CONFIG_SMB_FS is not set 1131# CONFIG_SMB_FS is not set
@@ -1126,8 +1197,10 @@ CONFIG_NLS_DEFAULT="iso8859-1"
1126# Library routines 1197# Library routines
1127# 1198#
1128CONFIG_BITREVERSE=y 1199CONFIG_BITREVERSE=y
1200# CONFIG_GENERIC_FIND_FIRST_BIT is not set
1129# CONFIG_CRC_CCITT is not set 1201# CONFIG_CRC_CCITT is not set
1130# CONFIG_CRC16 is not set 1202# CONFIG_CRC16 is not set
1203# CONFIG_CRC_T10DIF is not set
1131# CONFIG_CRC_ITU_T is not set 1204# CONFIG_CRC_ITU_T is not set
1132CONFIG_CRC32=y 1205CONFIG_CRC32=y
1133# CONFIG_CRC7 is not set 1206# CONFIG_CRC7 is not set
@@ -1146,6 +1219,7 @@ CONFIG_HAVE_LMB=y
1146# CONFIG_PRINTK_TIME is not set 1219# CONFIG_PRINTK_TIME is not set
1147CONFIG_ENABLE_WARN_DEPRECATED=y 1220CONFIG_ENABLE_WARN_DEPRECATED=y
1148CONFIG_ENABLE_MUST_CHECK=y 1221CONFIG_ENABLE_MUST_CHECK=y
1222CONFIG_FRAME_WARN=1024
1149# CONFIG_MAGIC_SYSRQ is not set 1223# CONFIG_MAGIC_SYSRQ is not set
1150# CONFIG_UNUSED_SYMBOLS is not set 1224# CONFIG_UNUSED_SYMBOLS is not set
1151# CONFIG_DEBUG_FS is not set 1225# CONFIG_DEBUG_FS is not set
@@ -1154,7 +1228,18 @@ CONFIG_ENABLE_MUST_CHECK=y
1154# CONFIG_SLUB_DEBUG_ON is not set 1228# CONFIG_SLUB_DEBUG_ON is not set
1155# CONFIG_SLUB_STATS is not set 1229# CONFIG_SLUB_STATS is not set
1156# CONFIG_DEBUG_BUGVERBOSE is not set 1230# CONFIG_DEBUG_BUGVERBOSE is not set
1231# CONFIG_DEBUG_MEMORY_INIT is not set
1232# CONFIG_LATENCYTOP is not set
1233# CONFIG_SYSCTL_SYSCALL_CHECK is not set
1234CONFIG_HAVE_FTRACE=y
1235CONFIG_HAVE_DYNAMIC_FTRACE=y
1236# CONFIG_FTRACE is not set
1237# CONFIG_SCHED_TRACER is not set
1238# CONFIG_CONTEXT_SWITCH_TRACER is not set
1157# CONFIG_SAMPLES is not set 1239# CONFIG_SAMPLES is not set
1240CONFIG_HAVE_ARCH_KGDB=y
1241# CONFIG_IRQSTACKS is not set
1242# CONFIG_BOOTX_TEXT is not set
1158# CONFIG_PPC_EARLY_DEBUG is not set 1243# CONFIG_PPC_EARLY_DEBUG is not set
1159 1244
1160# 1245#
@@ -1164,51 +1249,86 @@ CONFIG_ENABLE_MUST_CHECK=y
1164# CONFIG_SECURITY is not set 1249# CONFIG_SECURITY is not set
1165# CONFIG_SECURITY_FILE_CAPABILITIES is not set 1250# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1166CONFIG_CRYPTO=y 1251CONFIG_CRYPTO=y
1252
1253#
1254# Crypto core or helper
1255#
1167CONFIG_CRYPTO_ALGAPI=y 1256CONFIG_CRYPTO_ALGAPI=y
1168CONFIG_CRYPTO_BLKCIPHER=y 1257CONFIG_CRYPTO_BLKCIPHER=y
1169# CONFIG_CRYPTO_SEQIV is not set
1170CONFIG_CRYPTO_MANAGER=y 1258CONFIG_CRYPTO_MANAGER=y
1259# CONFIG_CRYPTO_GF128MUL is not set
1260# CONFIG_CRYPTO_NULL is not set
1261# CONFIG_CRYPTO_CRYPTD is not set
1262# CONFIG_CRYPTO_AUTHENC is not set
1263# CONFIG_CRYPTO_TEST is not set
1264
1265#
1266# Authenticated Encryption with Associated Data
1267#
1268# CONFIG_CRYPTO_CCM is not set
1269# CONFIG_CRYPTO_GCM is not set
1270# CONFIG_CRYPTO_SEQIV is not set
1271
1272#
1273# Block modes
1274#
1275CONFIG_CRYPTO_CBC=y
1276# CONFIG_CRYPTO_CTR is not set
1277# CONFIG_CRYPTO_CTS is not set
1278CONFIG_CRYPTO_ECB=m
1279# CONFIG_CRYPTO_LRW is not set
1280CONFIG_CRYPTO_PCBC=m
1281# CONFIG_CRYPTO_XTS is not set
1282
1283#
1284# Hash modes
1285#
1171# CONFIG_CRYPTO_HMAC is not set 1286# CONFIG_CRYPTO_HMAC is not set
1172# CONFIG_CRYPTO_XCBC is not set 1287# CONFIG_CRYPTO_XCBC is not set
1173# CONFIG_CRYPTO_NULL is not set 1288
1289#
1290# Digest
1291#
1292# CONFIG_CRYPTO_CRC32C is not set
1174# CONFIG_CRYPTO_MD4 is not set 1293# CONFIG_CRYPTO_MD4 is not set
1175CONFIG_CRYPTO_MD5=y 1294CONFIG_CRYPTO_MD5=y
1295# CONFIG_CRYPTO_MICHAEL_MIC is not set
1296# CONFIG_CRYPTO_RMD128 is not set
1297# CONFIG_CRYPTO_RMD160 is not set
1298# CONFIG_CRYPTO_RMD256 is not set
1299# CONFIG_CRYPTO_RMD320 is not set
1176# CONFIG_CRYPTO_SHA1 is not set 1300# CONFIG_CRYPTO_SHA1 is not set
1177# CONFIG_CRYPTO_SHA256 is not set 1301# CONFIG_CRYPTO_SHA256 is not set
1178# CONFIG_CRYPTO_SHA512 is not set 1302# CONFIG_CRYPTO_SHA512 is not set
1179# CONFIG_CRYPTO_WP512 is not set
1180# CONFIG_CRYPTO_TGR192 is not set 1303# CONFIG_CRYPTO_TGR192 is not set
1181# CONFIG_CRYPTO_GF128MUL is not set 1304# CONFIG_CRYPTO_WP512 is not set
1182CONFIG_CRYPTO_ECB=m 1305
1183CONFIG_CRYPTO_CBC=y 1306#
1184CONFIG_CRYPTO_PCBC=m 1307# Ciphers
1185# CONFIG_CRYPTO_LRW is not set 1308#
1186# CONFIG_CRYPTO_XTS is not set
1187# CONFIG_CRYPTO_CTR is not set
1188# CONFIG_CRYPTO_GCM is not set
1189# CONFIG_CRYPTO_CCM is not set
1190# CONFIG_CRYPTO_CRYPTD is not set
1191CONFIG_CRYPTO_DES=y
1192# CONFIG_CRYPTO_FCRYPT is not set
1193# CONFIG_CRYPTO_BLOWFISH is not set
1194# CONFIG_CRYPTO_TWOFISH is not set
1195# CONFIG_CRYPTO_SERPENT is not set
1196# CONFIG_CRYPTO_AES is not set 1309# CONFIG_CRYPTO_AES is not set
1310# CONFIG_CRYPTO_ANUBIS is not set
1311# CONFIG_CRYPTO_ARC4 is not set
1312# CONFIG_CRYPTO_BLOWFISH is not set
1313# CONFIG_CRYPTO_CAMELLIA is not set
1197# CONFIG_CRYPTO_CAST5 is not set 1314# CONFIG_CRYPTO_CAST5 is not set
1198# CONFIG_CRYPTO_CAST6 is not set 1315# CONFIG_CRYPTO_CAST6 is not set
1199# CONFIG_CRYPTO_TEA is not set 1316CONFIG_CRYPTO_DES=y
1200# CONFIG_CRYPTO_ARC4 is not set 1317# CONFIG_CRYPTO_FCRYPT is not set
1201# CONFIG_CRYPTO_KHAZAD is not set 1318# CONFIG_CRYPTO_KHAZAD is not set
1202# CONFIG_CRYPTO_ANUBIS is not set
1203# CONFIG_CRYPTO_SEED is not set
1204# CONFIG_CRYPTO_SALSA20 is not set 1319# CONFIG_CRYPTO_SALSA20 is not set
1320# CONFIG_CRYPTO_SEED is not set
1321# CONFIG_CRYPTO_SERPENT is not set
1322# CONFIG_CRYPTO_TEA is not set
1323# CONFIG_CRYPTO_TWOFISH is not set
1324
1325#
1326# Compression
1327#
1205# CONFIG_CRYPTO_DEFLATE is not set 1328# CONFIG_CRYPTO_DEFLATE is not set
1206# CONFIG_CRYPTO_MICHAEL_MIC is not set
1207# CONFIG_CRYPTO_CRC32C is not set
1208# CONFIG_CRYPTO_CAMELLIA is not set
1209# CONFIG_CRYPTO_TEST is not set
1210# CONFIG_CRYPTO_AUTHENC is not set
1211# CONFIG_CRYPTO_LZO is not set 1329# CONFIG_CRYPTO_LZO is not set
1212CONFIG_CRYPTO_HW=y 1330CONFIG_CRYPTO_HW=y
1213# CONFIG_CRYPTO_DEV_HIFN_795X is not set 1331# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1332# CONFIG_CRYPTO_DEV_TALITOS is not set
1214# CONFIG_PPC_CLOCK is not set 1333# CONFIG_PPC_CLOCK is not set
1334# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/configs/83xx/mpc8313_rdb_defconfig b/arch/powerpc/configs/83xx/mpc8313_rdb_defconfig
index 5428f9f5ed85..2028337868b4 100644
--- a/arch/powerpc/configs/83xx/mpc8313_rdb_defconfig
+++ b/arch/powerpc/configs/83xx/mpc8313_rdb_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc5 3# Linux kernel version: 2.6.27-rc4
4# Mon Jun 9 08:52:21 2008 4# Thu Aug 21 00:52:17 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -16,6 +16,7 @@ CONFIG_6xx=y
16# CONFIG_E200 is not set 16# CONFIG_E200 is not set
17CONFIG_PPC_FPU=y 17CONFIG_PPC_FPU=y
18# CONFIG_FSL_EMB_PERFMON is not set 18# CONFIG_FSL_EMB_PERFMON is not set
19# CONFIG_ALTIVEC is not set
19CONFIG_PPC_STD_MMU=y 20CONFIG_PPC_STD_MMU=y
20CONFIG_PPC_STD_MMU_32=y 21CONFIG_PPC_STD_MMU_32=y
21# CONFIG_PPC_MM_SLICES is not set 22# CONFIG_PPC_MM_SLICES is not set
@@ -32,6 +33,7 @@ CONFIG_GENERIC_HARDIRQS=y
32# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set 33# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
33CONFIG_IRQ_PER_CPU=y 34CONFIG_IRQ_PER_CPU=y
34CONFIG_STACKTRACE_SUPPORT=y 35CONFIG_STACKTRACE_SUPPORT=y
36CONFIG_HAVE_LATENCYTOP_SUPPORT=y
35CONFIG_LOCKDEP_SUPPORT=y 37CONFIG_LOCKDEP_SUPPORT=y
36CONFIG_RWSEM_XCHGADD_ALGORITHM=y 38CONFIG_RWSEM_XCHGADD_ALGORITHM=y
37CONFIG_ARCH_HAS_ILOG2_U32=y 39CONFIG_ARCH_HAS_ILOG2_U32=y
@@ -51,6 +53,9 @@ CONFIG_PPC_UDBG_16550=y
51CONFIG_AUDIT_ARCH=y 53CONFIG_AUDIT_ARCH=y
52CONFIG_GENERIC_BUG=y 54CONFIG_GENERIC_BUG=y
53CONFIG_DEFAULT_UIMAGE=y 55CONFIG_DEFAULT_UIMAGE=y
56CONFIG_HIBERNATE_32=y
57CONFIG_ARCH_HIBERNATION_POSSIBLE=y
58CONFIG_ARCH_SUSPEND_POSSIBLE=y
54# CONFIG_PPC_DCR_NATIVE is not set 59# CONFIG_PPC_DCR_NATIVE is not set
55# CONFIG_PPC_DCR_MMIO is not set 60# CONFIG_PPC_DCR_MMIO is not set
56CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 61CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
@@ -88,12 +93,12 @@ CONFIG_INITRAMFS_SOURCE=""
88CONFIG_SYSCTL=y 93CONFIG_SYSCTL=y
89CONFIG_EMBEDDED=y 94CONFIG_EMBEDDED=y
90CONFIG_SYSCTL_SYSCALL=y 95CONFIG_SYSCTL_SYSCALL=y
91CONFIG_SYSCTL_SYSCALL_CHECK=y
92# CONFIG_KALLSYMS is not set 96# CONFIG_KALLSYMS is not set
93CONFIG_HOTPLUG=y 97CONFIG_HOTPLUG=y
94CONFIG_PRINTK=y 98CONFIG_PRINTK=y
95CONFIG_BUG=y 99CONFIG_BUG=y
96CONFIG_ELF_CORE=y 100CONFIG_ELF_CORE=y
101CONFIG_PCSPKR_PLATFORM=y
97CONFIG_COMPAT_BRK=y 102CONFIG_COMPAT_BRK=y
98CONFIG_BASE_FULL=y 103CONFIG_BASE_FULL=y
99CONFIG_FUTEX=y 104CONFIG_FUTEX=y
@@ -111,10 +116,16 @@ CONFIG_SLUB=y
111# CONFIG_PROFILING is not set 116# CONFIG_PROFILING is not set
112# CONFIG_MARKERS is not set 117# CONFIG_MARKERS is not set
113CONFIG_HAVE_OPROFILE=y 118CONFIG_HAVE_OPROFILE=y
119CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
120CONFIG_HAVE_IOREMAP_PROT=y
114CONFIG_HAVE_KPROBES=y 121CONFIG_HAVE_KPROBES=y
115CONFIG_HAVE_KRETPROBES=y 122CONFIG_HAVE_KRETPROBES=y
123CONFIG_HAVE_ARCH_TRACEHOOK=y
116# CONFIG_HAVE_DMA_ATTRS is not set 124# CONFIG_HAVE_DMA_ATTRS is not set
125# CONFIG_USE_GENERIC_SMP_HELPERS is not set
126# CONFIG_HAVE_CLK is not set
117CONFIG_PROC_PAGE_MONITOR=y 127CONFIG_PROC_PAGE_MONITOR=y
128# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
118CONFIG_SLABINFO=y 129CONFIG_SLABINFO=y
119CONFIG_RT_MUTEXES=y 130CONFIG_RT_MUTEXES=y
120# CONFIG_TINY_SHMEM is not set 131# CONFIG_TINY_SHMEM is not set
@@ -125,12 +136,13 @@ CONFIG_MODULE_UNLOAD=y
125# CONFIG_MODULE_FORCE_UNLOAD is not set 136# CONFIG_MODULE_FORCE_UNLOAD is not set
126# CONFIG_MODVERSIONS is not set 137# CONFIG_MODVERSIONS is not set
127# CONFIG_MODULE_SRCVERSION_ALL is not set 138# CONFIG_MODULE_SRCVERSION_ALL is not set
128# CONFIG_KMOD is not set 139CONFIG_KMOD=y
129CONFIG_BLOCK=y 140CONFIG_BLOCK=y
130# CONFIG_LBD is not set 141# CONFIG_LBD is not set
131# CONFIG_BLK_DEV_IO_TRACE is not set 142# CONFIG_BLK_DEV_IO_TRACE is not set
132# CONFIG_LSF is not set 143# CONFIG_LSF is not set
133# CONFIG_BLK_DEV_BSG is not set 144# CONFIG_BLK_DEV_BSG is not set
145# CONFIG_BLK_DEV_INTEGRITY is not set
134 146
135# 147#
136# IO Schedulers 148# IO Schedulers
@@ -149,37 +161,49 @@ CONFIG_CLASSIC_RCU=y
149# 161#
150# Platform support 162# Platform support
151# 163#
152# CONFIG_PPC_MULTIPLATFORM is not set 164CONFIG_PPC_MULTIPLATFORM=y
153# CONFIG_PPC_82xx is not set 165CONFIG_CLASSIC32=y
154CONFIG_PPC_83xx=y 166CONFIG_PPC_CHRP=y
155# CONFIG_PPC_86xx is not set 167# CONFIG_MPC5121_ADS is not set
156# CONFIG_PPC_MPC512x is not set 168# CONFIG_MPC5121_GENERIC is not set
157# CONFIG_PPC_MPC5121 is not set 169# CONFIG_PPC_MPC52xx is not set
170CONFIG_PPC_PMAC=y
158# CONFIG_PPC_CELL is not set 171# CONFIG_PPC_CELL is not set
159# CONFIG_PPC_CELL_NATIVE is not set 172# CONFIG_PPC_CELL_NATIVE is not set
173# CONFIG_PPC_82xx is not set
160# CONFIG_PQ2ADS is not set 174# CONFIG_PQ2ADS is not set
161CONFIG_MPC83xx=y 175CONFIG_PPC_83xx=y
162CONFIG_MPC831x_RDB=y 176CONFIG_MPC831x_RDB=y
163# CONFIG_MPC832x_MDS is not set 177# CONFIG_MPC832x_MDS is not set
164# CONFIG_MPC832x_RDB is not set 178# CONFIG_MPC832x_RDB is not set
165# CONFIG_MPC834x_MDS is not set 179# CONFIG_MPC834x_MDS is not set
166# CONFIG_MPC834x_ITX is not set 180# CONFIG_MPC834x_ITX is not set
167# CONFIG_MPC836x_MDS is not set 181# CONFIG_MPC836x_MDS is not set
182# CONFIG_MPC836x_RDK is not set
168# CONFIG_MPC837x_MDS is not set 183# CONFIG_MPC837x_MDS is not set
169# CONFIG_MPC837x_RDB is not set 184# CONFIG_MPC837x_RDB is not set
170# CONFIG_SBC834x is not set 185# CONFIG_SBC834x is not set
186# CONFIG_ASP834x is not set
171CONFIG_PPC_MPC831x=y 187CONFIG_PPC_MPC831x=y
188# CONFIG_PPC_86xx is not set
189# CONFIG_EMBEDDED6xx is not set
190CONFIG_PPC_NATIVE=y
191# CONFIG_UDBG_RTAS_CONSOLE is not set
172CONFIG_IPIC=y 192CONFIG_IPIC=y
173# CONFIG_MPIC is not set 193CONFIG_MPIC=y
174# CONFIG_MPIC_WEIRD is not set 194# CONFIG_MPIC_WEIRD is not set
175# CONFIG_PPC_I8259 is not set 195CONFIG_PPC_I8259=y
176# CONFIG_PPC_RTAS is not set 196CONFIG_PPC_RTAS=y
197# CONFIG_RTAS_ERROR_LOGGING is not set
198CONFIG_RTAS_PROC=y
177# CONFIG_MMIO_NVRAM is not set 199# CONFIG_MMIO_NVRAM is not set
178# CONFIG_PPC_MPC106 is not set 200CONFIG_PPC_MPC106=y
179# CONFIG_PPC_970_NAP is not set 201# CONFIG_PPC_970_NAP is not set
180# CONFIG_PPC_INDIRECT_IO is not set 202# CONFIG_PPC_INDIRECT_IO is not set
181# CONFIG_GENERIC_IOMAP is not set 203# CONFIG_GENERIC_IOMAP is not set
182# CONFIG_CPU_FREQ is not set 204# CONFIG_CPU_FREQ is not set
205# CONFIG_PPC601_SYNC_FIX is not set
206# CONFIG_TAU is not set
183# CONFIG_FSL_ULI1575 is not set 207# CONFIG_FSL_ULI1575 is not set
184 208
185# 209#
@@ -195,7 +219,7 @@ CONFIG_HZ_250=y
195# CONFIG_HZ_300 is not set 219# CONFIG_HZ_300 is not set
196# CONFIG_HZ_1000 is not set 220# CONFIG_HZ_1000 is not set
197CONFIG_HZ=250 221CONFIG_HZ=250
198# CONFIG_SCHED_HRTICK is not set 222CONFIG_SCHED_HRTICK=y
199CONFIG_PREEMPT_NONE=y 223CONFIG_PREEMPT_NONE=y
200# CONFIG_PREEMPT_VOLUNTARY is not set 224# CONFIG_PREEMPT_VOLUNTARY is not set
201# CONFIG_PREEMPT is not set 225# CONFIG_PREEMPT is not set
@@ -205,6 +229,7 @@ CONFIG_BINFMT_ELF=y
205CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y 229CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
206CONFIG_ARCH_HAS_WALK_MEMORY=y 230CONFIG_ARCH_HAS_WALK_MEMORY=y
207CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y 231CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
232# CONFIG_KEXEC is not set
208CONFIG_ARCH_FLATMEM_ENABLE=y 233CONFIG_ARCH_FLATMEM_ENABLE=y
209CONFIG_ARCH_POPULATES_NODE_MAP=y 234CONFIG_ARCH_POPULATES_NODE_MAP=y
210CONFIG_SELECT_MEMORY_MODEL=y 235CONFIG_SELECT_MEMORY_MODEL=y
@@ -217,6 +242,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
217# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set 242# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
218CONFIG_PAGEFLAGS_EXTENDED=y 243CONFIG_PAGEFLAGS_EXTENDED=y
219CONFIG_SPLIT_PTLOCK_CPUS=4 244CONFIG_SPLIT_PTLOCK_CPUS=4
245CONFIG_MIGRATION=y
220# CONFIG_RESOURCES_64BIT is not set 246# CONFIG_RESOURCES_64BIT is not set
221CONFIG_ZONE_DMA_FLAG=1 247CONFIG_ZONE_DMA_FLAG=1
222CONFIG_BOUNCE=y 248CONFIG_BOUNCE=y
@@ -224,6 +250,7 @@ CONFIG_VIRT_TO_BUS=y
224CONFIG_FORCE_MAX_ZONEORDER=11 250CONFIG_FORCE_MAX_ZONEORDER=11
225CONFIG_PROC_DEVICETREE=y 251CONFIG_PROC_DEVICETREE=y
226# CONFIG_CMDLINE_BOOL is not set 252# CONFIG_CMDLINE_BOOL is not set
253CONFIG_EXTRA_TARGETS=""
227# CONFIG_PM is not set 254# CONFIG_PM is not set
228CONFIG_SECCOMP=y 255CONFIG_SECCOMP=y
229CONFIG_ISA_DMA_API=y 256CONFIG_ISA_DMA_API=y
@@ -231,10 +258,13 @@ CONFIG_ISA_DMA_API=y
231# 258#
232# Bus options 259# Bus options
233# 260#
261# CONFIG_ISA is not set
234CONFIG_ZONE_DMA=y 262CONFIG_ZONE_DMA=y
235CONFIG_GENERIC_ISA_DMA=y 263CONFIG_GENERIC_ISA_DMA=y
236CONFIG_PPC_INDIRECT_PCI=y 264CONFIG_PPC_INDIRECT_PCI=y
237CONFIG_FSL_SOC=y 265CONFIG_FSL_SOC=y
266CONFIG_FSL_PCI=y
267CONFIG_PPC_PCI_CHOICE=y
238CONFIG_PCI=y 268CONFIG_PCI=y
239CONFIG_PCI_DOMAINS=y 269CONFIG_PCI_DOMAINS=y
240CONFIG_PCI_SYSCALL=y 270CONFIG_PCI_SYSCALL=y
@@ -260,10 +290,6 @@ CONFIG_PAGE_OFFSET=0xc0000000
260CONFIG_KERNEL_START=0xc0000000 290CONFIG_KERNEL_START=0xc0000000
261CONFIG_PHYSICAL_START=0x00000000 291CONFIG_PHYSICAL_START=0x00000000
262CONFIG_TASK_SIZE=0xc0000000 292CONFIG_TASK_SIZE=0xc0000000
263
264#
265# Networking
266#
267CONFIG_NET=y 293CONFIG_NET=y
268 294
269# 295#
@@ -452,9 +478,11 @@ CONFIG_MTD_NAND_FSL_ELBC=y
452# CONFIG_MTD_UBI is not set 478# CONFIG_MTD_UBI is not set
453CONFIG_OF_DEVICE=y 479CONFIG_OF_DEVICE=y
454CONFIG_OF_I2C=y 480CONFIG_OF_I2C=y
481CONFIG_OF_SPI=y
455# CONFIG_PARPORT is not set 482# CONFIG_PARPORT is not set
456CONFIG_BLK_DEV=y 483CONFIG_BLK_DEV=y
457# CONFIG_BLK_DEV_FD is not set 484# CONFIG_BLK_DEV_FD is not set
485# CONFIG_MAC_FLOPPY is not set
458# CONFIG_BLK_CPQ_DA is not set 486# CONFIG_BLK_CPQ_DA is not set
459# CONFIG_BLK_CPQ_CISS_DA is not set 487# CONFIG_BLK_CPQ_CISS_DA is not set
460# CONFIG_BLK_DEV_DAC960 is not set 488# CONFIG_BLK_DEV_DAC960 is not set
@@ -471,12 +499,14 @@ CONFIG_BLK_DEV_RAM_SIZE=32768
471# CONFIG_BLK_DEV_XIP is not set 499# CONFIG_BLK_DEV_XIP is not set
472# CONFIG_CDROM_PKTCDVD is not set 500# CONFIG_CDROM_PKTCDVD is not set
473# CONFIG_ATA_OVER_ETH is not set 501# CONFIG_ATA_OVER_ETH is not set
502# CONFIG_BLK_DEV_HD is not set
474CONFIG_MISC_DEVICES=y 503CONFIG_MISC_DEVICES=y
475# CONFIG_PHANTOM is not set 504# CONFIG_PHANTOM is not set
476# CONFIG_EEPROM_93CX6 is not set 505# CONFIG_EEPROM_93CX6 is not set
477# CONFIG_SGI_IOC4 is not set 506# CONFIG_SGI_IOC4 is not set
478# CONFIG_TIFM_CORE is not set 507# CONFIG_TIFM_CORE is not set
479# CONFIG_ENCLOSURE_SERVICES is not set 508# CONFIG_ENCLOSURE_SERVICES is not set
509# CONFIG_HP_ILO is not set
480CONFIG_HAVE_IDE=y 510CONFIG_HAVE_IDE=y
481# CONFIG_IDE is not set 511# CONFIG_IDE is not set
482 512
@@ -553,7 +583,10 @@ CONFIG_SCSI_LOWLEVEL=y
553# CONFIG_SCSI_DC390T is not set 583# CONFIG_SCSI_DC390T is not set
554# CONFIG_SCSI_NSP32 is not set 584# CONFIG_SCSI_NSP32 is not set
555# CONFIG_SCSI_DEBUG is not set 585# CONFIG_SCSI_DEBUG is not set
586# CONFIG_SCSI_MESH is not set
587# CONFIG_SCSI_MAC53C94 is not set
556# CONFIG_SCSI_SRP is not set 588# CONFIG_SCSI_SRP is not set
589# CONFIG_SCSI_DH is not set
557# CONFIG_ATA is not set 590# CONFIG_ATA is not set
558CONFIG_MD=y 591CONFIG_MD=y
559CONFIG_BLK_DEV_MD=y 592CONFIG_BLK_DEV_MD=y
@@ -570,12 +603,15 @@ CONFIG_MD_RAID1=y
570# 603#
571# IEEE 1394 (FireWire) support 604# IEEE 1394 (FireWire) support
572# 605#
606
607#
608# Enable only one of the two stacks, unless you know what you are doing
609#
573# CONFIG_FIREWIRE is not set 610# CONFIG_FIREWIRE is not set
574# CONFIG_IEEE1394 is not set 611# CONFIG_IEEE1394 is not set
575# CONFIG_I2O is not set 612# CONFIG_I2O is not set
576# CONFIG_MACINTOSH_DRIVERS is not set 613# CONFIG_MACINTOSH_DRIVERS is not set
577CONFIG_NETDEVICES=y 614CONFIG_NETDEVICES=y
578# CONFIG_NETDEVICES_MULTIQUEUE is not set
579# CONFIG_DUMMY is not set 615# CONFIG_DUMMY is not set
580# CONFIG_BONDING is not set 616# CONFIG_BONDING is not set
581# CONFIG_MACVLAN is not set 617# CONFIG_MACVLAN is not set
@@ -602,6 +638,8 @@ CONFIG_CICADA_PHY=y
602# CONFIG_MDIO_BITBANG is not set 638# CONFIG_MDIO_BITBANG is not set
603CONFIG_NET_ETHERNET=y 639CONFIG_NET_ETHERNET=y
604CONFIG_MII=y 640CONFIG_MII=y
641# CONFIG_MACE is not set
642# CONFIG_BMAC is not set
605# CONFIG_HAPPYMEAL is not set 643# CONFIG_HAPPYMEAL is not set
606# CONFIG_SUNGEM is not set 644# CONFIG_SUNGEM is not set
607# CONFIG_CASSINI is not set 645# CONFIG_CASSINI is not set
@@ -638,7 +676,6 @@ CONFIG_NETDEV_1000=y
638# CONFIG_DL2K is not set 676# CONFIG_DL2K is not set
639# CONFIG_E1000 is not set 677# CONFIG_E1000 is not set
640# CONFIG_E1000E is not set 678# CONFIG_E1000E is not set
641# CONFIG_E1000E_ENABLED is not set
642# CONFIG_IP1000 is not set 679# CONFIG_IP1000 is not set
643# CONFIG_IGB is not set 680# CONFIG_IGB is not set
644# CONFIG_NS83820 is not set 681# CONFIG_NS83820 is not set
@@ -652,9 +689,10 @@ CONFIG_NETDEV_1000=y
652# CONFIG_TIGON3 is not set 689# CONFIG_TIGON3 is not set
653# CONFIG_BNX2 is not set 690# CONFIG_BNX2 is not set
654CONFIG_GIANFAR=y 691CONFIG_GIANFAR=y
655CONFIG_GFAR_NAPI=y 692# CONFIG_MV643XX_ETH is not set
656# CONFIG_QLA3XXX is not set 693# CONFIG_QLA3XXX is not set
657# CONFIG_ATL1 is not set 694# CONFIG_ATL1 is not set
695# CONFIG_ATL1E is not set
658CONFIG_NETDEV_10000=y 696CONFIG_NETDEV_10000=y
659# CONFIG_CHELSIO_T1 is not set 697# CONFIG_CHELSIO_T1 is not set
660# CONFIG_CHELSIO_T3 is not set 698# CONFIG_CHELSIO_T3 is not set
@@ -752,11 +790,14 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=4
752# CONFIG_SERIAL_UARTLITE is not set 790# CONFIG_SERIAL_UARTLITE is not set
753CONFIG_SERIAL_CORE=y 791CONFIG_SERIAL_CORE=y
754CONFIG_SERIAL_CORE_CONSOLE=y 792CONFIG_SERIAL_CORE_CONSOLE=y
793# CONFIG_SERIAL_PMACZILOG is not set
755# CONFIG_SERIAL_JSM is not set 794# CONFIG_SERIAL_JSM is not set
756# CONFIG_SERIAL_OF_PLATFORM is not set 795# CONFIG_SERIAL_OF_PLATFORM is not set
757CONFIG_UNIX98_PTYS=y 796CONFIG_UNIX98_PTYS=y
758CONFIG_LEGACY_PTYS=y 797CONFIG_LEGACY_PTYS=y
759CONFIG_LEGACY_PTY_COUNT=256 798CONFIG_LEGACY_PTY_COUNT=256
799# CONFIG_BRIQ_PANEL is not set
800# CONFIG_HVC_RTAS is not set
760# CONFIG_IPMI_HANDLER is not set 801# CONFIG_IPMI_HANDLER is not set
761CONFIG_HW_RANDOM=y 802CONFIG_HW_RANDOM=y
762# CONFIG_NVRAM is not set 803# CONFIG_NVRAM is not set
@@ -768,43 +809,70 @@ CONFIG_DEVPORT=y
768CONFIG_I2C=y 809CONFIG_I2C=y
769CONFIG_I2C_BOARDINFO=y 810CONFIG_I2C_BOARDINFO=y
770CONFIG_I2C_CHARDEV=y 811CONFIG_I2C_CHARDEV=y
812CONFIG_I2C_HELPER_AUTO=y
771 813
772# 814#
773# I2C Hardware Bus support 815# I2C Hardware Bus support
774# 816#
817
818#
819# PC SMBus host controller drivers
820#
775# CONFIG_I2C_ALI1535 is not set 821# CONFIG_I2C_ALI1535 is not set
776# CONFIG_I2C_ALI1563 is not set 822# CONFIG_I2C_ALI1563 is not set
777# CONFIG_I2C_ALI15X3 is not set 823# CONFIG_I2C_ALI15X3 is not set
778# CONFIG_I2C_AMD756 is not set 824# CONFIG_I2C_AMD756 is not set
779# CONFIG_I2C_AMD8111 is not set 825# CONFIG_I2C_AMD8111 is not set
780# CONFIG_I2C_I801 is not set 826# CONFIG_I2C_I801 is not set
781# CONFIG_I2C_I810 is not set 827# CONFIG_I2C_ISCH is not set
782# CONFIG_I2C_PIIX4 is not set 828# CONFIG_I2C_PIIX4 is not set
783CONFIG_I2C_MPC=y
784# CONFIG_I2C_NFORCE2 is not set 829# CONFIG_I2C_NFORCE2 is not set
785# CONFIG_I2C_OCORES is not set
786# CONFIG_I2C_PARPORT_LIGHT is not set
787# CONFIG_I2C_PROSAVAGE is not set
788# CONFIG_I2C_SAVAGE4 is not set
789# CONFIG_I2C_SIMTEC is not set
790# CONFIG_I2C_SIS5595 is not set 830# CONFIG_I2C_SIS5595 is not set
791# CONFIG_I2C_SIS630 is not set 831# CONFIG_I2C_SIS630 is not set
792# CONFIG_I2C_SIS96X is not set 832# CONFIG_I2C_SIS96X is not set
793# CONFIG_I2C_TAOS_EVM is not set
794# CONFIG_I2C_STUB is not set
795# CONFIG_I2C_TINY_USB is not set
796# CONFIG_I2C_VIA is not set 833# CONFIG_I2C_VIA is not set
797# CONFIG_I2C_VIAPRO is not set 834# CONFIG_I2C_VIAPRO is not set
835
836#
837# Mac SMBus host controller drivers
838#
839# CONFIG_I2C_HYDRA is not set
840CONFIG_I2C_POWERMAC=y
841
842#
843# I2C system bus drivers (mostly embedded / system-on-chip)
844#
845CONFIG_I2C_MPC=y
846# CONFIG_I2C_OCORES is not set
847# CONFIG_I2C_SIMTEC is not set
848
849#
850# External I2C/SMBus adapter drivers
851#
852# CONFIG_I2C_PARPORT_LIGHT is not set
853# CONFIG_I2C_TAOS_EVM is not set
854# CONFIG_I2C_TINY_USB is not set
855
856#
857# Graphics adapter I2C/DDC channel drivers
858#
798# CONFIG_I2C_VOODOO3 is not set 859# CONFIG_I2C_VOODOO3 is not set
860
861#
862# Other I2C/SMBus bus drivers
863#
799# CONFIG_I2C_PCA_PLATFORM is not set 864# CONFIG_I2C_PCA_PLATFORM is not set
865# CONFIG_I2C_STUB is not set
800 866
801# 867#
802# Miscellaneous I2C Chip support 868# Miscellaneous I2C Chip support
803# 869#
804# CONFIG_DS1682 is not set 870# CONFIG_DS1682 is not set
871# CONFIG_AT24 is not set
805# CONFIG_SENSORS_EEPROM is not set 872# CONFIG_SENSORS_EEPROM is not set
806# CONFIG_SENSORS_PCF8574 is not set 873# CONFIG_SENSORS_PCF8574 is not set
807# CONFIG_PCF8575 is not set 874# CONFIG_PCF8575 is not set
875# CONFIG_SENSORS_PCA9539 is not set
808# CONFIG_SENSORS_PCF8591 is not set 876# CONFIG_SENSORS_PCF8591 is not set
809# CONFIG_SENSORS_MAX6875 is not set 877# CONFIG_SENSORS_MAX6875 is not set
810# CONFIG_SENSORS_TSL2550 is not set 878# CONFIG_SENSORS_TSL2550 is not set
@@ -828,11 +896,15 @@ CONFIG_SPI_MPC83xx=y
828# CONFIG_SPI_AT25 is not set 896# CONFIG_SPI_AT25 is not set
829# CONFIG_SPI_SPIDEV is not set 897# CONFIG_SPI_SPIDEV is not set
830# CONFIG_SPI_TLE62X0 is not set 898# CONFIG_SPI_TLE62X0 is not set
899CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
900# CONFIG_GPIOLIB is not set
831# CONFIG_W1 is not set 901# CONFIG_W1 is not set
832# CONFIG_POWER_SUPPLY is not set 902# CONFIG_POWER_SUPPLY is not set
833CONFIG_HWMON=y 903CONFIG_HWMON=y
834# CONFIG_HWMON_VID is not set 904# CONFIG_HWMON_VID is not set
905# CONFIG_SENSORS_AD7414 is not set
835# CONFIG_SENSORS_AD7418 is not set 906# CONFIG_SENSORS_AD7418 is not set
907# CONFIG_SENSORS_ADCXX is not set
836# CONFIG_SENSORS_ADM1021 is not set 908# CONFIG_SENSORS_ADM1021 is not set
837# CONFIG_SENSORS_ADM1025 is not set 909# CONFIG_SENSORS_ADM1025 is not set
838# CONFIG_SENSORS_ADM1026 is not set 910# CONFIG_SENSORS_ADM1026 is not set
@@ -841,6 +913,7 @@ CONFIG_HWMON=y
841# CONFIG_SENSORS_ADM9240 is not set 913# CONFIG_SENSORS_ADM9240 is not set
842# CONFIG_SENSORS_ADT7470 is not set 914# CONFIG_SENSORS_ADT7470 is not set
843# CONFIG_SENSORS_ADT7473 is not set 915# CONFIG_SENSORS_ADT7473 is not set
916# CONFIG_SENSORS_AMS is not set
844# CONFIG_SENSORS_ATXP1 is not set 917# CONFIG_SENSORS_ATXP1 is not set
845# CONFIG_SENSORS_DS1621 is not set 918# CONFIG_SENSORS_DS1621 is not set
846# CONFIG_SENSORS_I5K_AMB is not set 919# CONFIG_SENSORS_I5K_AMB is not set
@@ -886,6 +959,7 @@ CONFIG_HWMON=y
886# CONFIG_SENSORS_W83627EHF is not set 959# CONFIG_SENSORS_W83627EHF is not set
887# CONFIG_HWMON_DEBUG_CHIP is not set 960# CONFIG_HWMON_DEBUG_CHIP is not set
888# CONFIG_THERMAL is not set 961# CONFIG_THERMAL is not set
962# CONFIG_THERMAL_HWMON is not set
889CONFIG_WATCHDOG=y 963CONFIG_WATCHDOG=y
890# CONFIG_WATCHDOG_NOWAYOUT is not set 964# CONFIG_WATCHDOG_NOWAYOUT is not set
891 965
@@ -893,7 +967,9 @@ CONFIG_WATCHDOG=y
893# Watchdog Device Drivers 967# Watchdog Device Drivers
894# 968#
895# CONFIG_SOFT_WATCHDOG is not set 969# CONFIG_SOFT_WATCHDOG is not set
896CONFIG_83xx_WDT=y 970# CONFIG_ALIM7101_WDT is not set
971# CONFIG_8xxx_WDT is not set
972# CONFIG_WATCHDOG_RTAS is not set
897 973
898# 974#
899# PCI-based Watchdog Cards 975# PCI-based Watchdog Cards
@@ -915,8 +991,10 @@ CONFIG_SSB_POSSIBLE=y
915# 991#
916# Multifunction device drivers 992# Multifunction device drivers
917# 993#
994# CONFIG_MFD_CORE is not set
918# CONFIG_MFD_SM501 is not set 995# CONFIG_MFD_SM501 is not set
919# CONFIG_HTC_PASIC3 is not set 996# CONFIG_HTC_PASIC3 is not set
997# CONFIG_MFD_TMIO is not set
920 998
921# 999#
922# Multimedia devices 1000# Multimedia devices
@@ -949,10 +1027,6 @@ CONFIG_VIDEO_OUTPUT_CONTROL=m
949# Display device support 1027# Display device support
950# 1028#
951# CONFIG_DISPLAY_SUPPORT is not set 1029# CONFIG_DISPLAY_SUPPORT is not set
952
953#
954# Sound
955#
956# CONFIG_SOUND is not set 1030# CONFIG_SOUND is not set
957CONFIG_HID_SUPPORT=y 1031CONFIG_HID_SUPPORT=y
958CONFIG_HID=y 1032CONFIG_HID=y
@@ -986,6 +1060,7 @@ CONFIG_USB_DEVICE_CLASS=y
986# CONFIG_USB_OTG is not set 1060# CONFIG_USB_OTG is not set
987# CONFIG_USB_OTG_WHITELIST is not set 1061# CONFIG_USB_OTG_WHITELIST is not set
988# CONFIG_USB_OTG_BLACKLIST_HUB is not set 1062# CONFIG_USB_OTG_BLACKLIST_HUB is not set
1063CONFIG_USB_MON=y
989 1064
990# 1065#
991# USB Host Controller Drivers 1066# USB Host Controller Drivers
@@ -1009,6 +1084,7 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y
1009CONFIG_USB_UHCI_HCD=y 1084CONFIG_USB_UHCI_HCD=y
1010# CONFIG_USB_SL811_HCD is not set 1085# CONFIG_USB_SL811_HCD is not set
1011# CONFIG_USB_R8A66597_HCD is not set 1086# CONFIG_USB_R8A66597_HCD is not set
1087# CONFIG_USB_GADGET_MUSB_HDRC is not set
1012 1088
1013# 1089#
1014# USB Device Class drivers 1090# USB Device Class drivers
@@ -1037,6 +1113,7 @@ CONFIG_USB_STORAGE=y
1037# CONFIG_USB_STORAGE_ALAUDA is not set 1113# CONFIG_USB_STORAGE_ALAUDA is not set
1038# CONFIG_USB_STORAGE_ONETOUCH is not set 1114# CONFIG_USB_STORAGE_ONETOUCH is not set
1039# CONFIG_USB_STORAGE_KARMA is not set 1115# CONFIG_USB_STORAGE_KARMA is not set
1116# CONFIG_USB_STORAGE_SIERRA is not set
1040# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set 1117# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
1041# CONFIG_USB_LIBUSUAL is not set 1118# CONFIG_USB_LIBUSUAL is not set
1042 1119
@@ -1045,7 +1122,6 @@ CONFIG_USB_STORAGE=y
1045# 1122#
1046# CONFIG_USB_MDC800 is not set 1123# CONFIG_USB_MDC800 is not set
1047# CONFIG_USB_MICROTEK is not set 1124# CONFIG_USB_MICROTEK is not set
1048CONFIG_USB_MON=y
1049 1125
1050# 1126#
1051# USB port drivers 1127# USB port drivers
@@ -1058,7 +1134,6 @@ CONFIG_USB_MON=y
1058# CONFIG_USB_EMI62 is not set 1134# CONFIG_USB_EMI62 is not set
1059# CONFIG_USB_EMI26 is not set 1135# CONFIG_USB_EMI26 is not set
1060# CONFIG_USB_ADUTUX is not set 1136# CONFIG_USB_ADUTUX is not set
1061# CONFIG_USB_AUERSWALD is not set
1062# CONFIG_USB_RIO500 is not set 1137# CONFIG_USB_RIO500 is not set
1063# CONFIG_USB_LEGOTOWER is not set 1138# CONFIG_USB_LEGOTOWER is not set
1064# CONFIG_USB_LCD is not set 1139# CONFIG_USB_LCD is not set
@@ -1085,7 +1160,7 @@ CONFIG_USB_GADGET_SELECTED=y
1085# CONFIG_USB_GADGET_FSL_USB2 is not set 1160# CONFIG_USB_GADGET_FSL_USB2 is not set
1086CONFIG_USB_GADGET_NET2280=y 1161CONFIG_USB_GADGET_NET2280=y
1087CONFIG_USB_NET2280=y 1162CONFIG_USB_NET2280=y
1088# CONFIG_USB_GADGET_PXA2XX is not set 1163# CONFIG_USB_GADGET_PXA25X is not set
1089# CONFIG_USB_GADGET_M66592 is not set 1164# CONFIG_USB_GADGET_M66592 is not set
1090# CONFIG_USB_GADGET_PXA27X is not set 1165# CONFIG_USB_GADGET_PXA27X is not set
1091# CONFIG_USB_GADGET_GOKU is not set 1166# CONFIG_USB_GADGET_GOKU is not set
@@ -1103,6 +1178,7 @@ CONFIG_USB_ETH_RNDIS=y
1103# CONFIG_USB_G_SERIAL is not set 1178# CONFIG_USB_G_SERIAL is not set
1104# CONFIG_USB_MIDI_GADGET is not set 1179# CONFIG_USB_MIDI_GADGET is not set
1105# CONFIG_USB_G_PRINTER is not set 1180# CONFIG_USB_G_PRINTER is not set
1181# CONFIG_USB_CDC_COMPOSITE is not set
1106# CONFIG_MMC is not set 1182# CONFIG_MMC is not set
1107# CONFIG_MEMSTICK is not set 1183# CONFIG_MEMSTICK is not set
1108# CONFIG_NEW_LEDS is not set 1184# CONFIG_NEW_LEDS is not set
@@ -1138,10 +1214,13 @@ CONFIG_RTC_DRV_DS1307=y
1138# CONFIG_RTC_DRV_PCF8583 is not set 1214# CONFIG_RTC_DRV_PCF8583 is not set
1139# CONFIG_RTC_DRV_M41T80 is not set 1215# CONFIG_RTC_DRV_M41T80 is not set
1140# CONFIG_RTC_DRV_S35390A is not set 1216# CONFIG_RTC_DRV_S35390A is not set
1217# CONFIG_RTC_DRV_FM3130 is not set
1141 1218
1142# 1219#
1143# SPI RTC drivers 1220# SPI RTC drivers
1144# 1221#
1222# CONFIG_RTC_DRV_M41T94 is not set
1223# CONFIG_RTC_DRV_DS1305 is not set
1145# CONFIG_RTC_DRV_MAX6902 is not set 1224# CONFIG_RTC_DRV_MAX6902 is not set
1146# CONFIG_RTC_DRV_R9701 is not set 1225# CONFIG_RTC_DRV_R9701 is not set
1147# CONFIG_RTC_DRV_RS5C348 is not set 1226# CONFIG_RTC_DRV_RS5C348 is not set
@@ -1240,6 +1319,7 @@ CONFIG_JFFS2_RTIME=y
1240# CONFIG_CRAMFS is not set 1319# CONFIG_CRAMFS is not set
1241# CONFIG_VXFS_FS is not set 1320# CONFIG_VXFS_FS is not set
1242# CONFIG_MINIX_FS is not set 1321# CONFIG_MINIX_FS is not set
1322# CONFIG_OMFS_FS is not set
1243# CONFIG_HPFS_FS is not set 1323# CONFIG_HPFS_FS is not set
1244# CONFIG_QNX4FS_FS is not set 1324# CONFIG_QNX4FS_FS is not set
1245# CONFIG_ROMFS_FS is not set 1325# CONFIG_ROMFS_FS is not set
@@ -1250,14 +1330,13 @@ CONFIG_NFS_FS=y
1250CONFIG_NFS_V3=y 1330CONFIG_NFS_V3=y
1251# CONFIG_NFS_V3_ACL is not set 1331# CONFIG_NFS_V3_ACL is not set
1252CONFIG_NFS_V4=y 1332CONFIG_NFS_V4=y
1253# CONFIG_NFSD is not set
1254CONFIG_ROOT_NFS=y 1333CONFIG_ROOT_NFS=y
1334# CONFIG_NFSD is not set
1255CONFIG_LOCKD=y 1335CONFIG_LOCKD=y
1256CONFIG_LOCKD_V4=y 1336CONFIG_LOCKD_V4=y
1257CONFIG_NFS_COMMON=y 1337CONFIG_NFS_COMMON=y
1258CONFIG_SUNRPC=y 1338CONFIG_SUNRPC=y
1259CONFIG_SUNRPC_GSS=y 1339CONFIG_SUNRPC_GSS=y
1260# CONFIG_SUNRPC_BIND34 is not set
1261CONFIG_RPCSEC_GSS_KRB5=y 1340CONFIG_RPCSEC_GSS_KRB5=y
1262# CONFIG_RPCSEC_GSS_SPKM3 is not set 1341# CONFIG_RPCSEC_GSS_SPKM3 is not set
1263# CONFIG_SMB_FS is not set 1342# CONFIG_SMB_FS is not set
@@ -1297,6 +1376,7 @@ CONFIG_BITREVERSE=y
1297# CONFIG_GENERIC_FIND_FIRST_BIT is not set 1376# CONFIG_GENERIC_FIND_FIRST_BIT is not set
1298# CONFIG_CRC_CCITT is not set 1377# CONFIG_CRC_CCITT is not set
1299# CONFIG_CRC16 is not set 1378# CONFIG_CRC16 is not set
1379# CONFIG_CRC_T10DIF is not set
1300# CONFIG_CRC_ITU_T is not set 1380# CONFIG_CRC_ITU_T is not set
1301CONFIG_CRC32=y 1381CONFIG_CRC32=y
1302# CONFIG_CRC7 is not set 1382# CONFIG_CRC7 is not set
@@ -1323,6 +1403,8 @@ CONFIG_FRAME_WARN=1024
1323CONFIG_DEBUG_KERNEL=y 1403CONFIG_DEBUG_KERNEL=y
1324# CONFIG_DEBUG_SHIRQ is not set 1404# CONFIG_DEBUG_SHIRQ is not set
1325CONFIG_DETECT_SOFTLOCKUP=y 1405CONFIG_DETECT_SOFTLOCKUP=y
1406# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
1407CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
1326CONFIG_SCHED_DEBUG=y 1408CONFIG_SCHED_DEBUG=y
1327# CONFIG_SCHEDSTATS is not set 1409# CONFIG_SCHEDSTATS is not set
1328# CONFIG_TIMER_STATS is not set 1410# CONFIG_TIMER_STATS is not set
@@ -1340,19 +1422,32 @@ CONFIG_SCHED_DEBUG=y
1340# CONFIG_DEBUG_INFO is not set 1422# CONFIG_DEBUG_INFO is not set
1341# CONFIG_DEBUG_VM is not set 1423# CONFIG_DEBUG_VM is not set
1342# CONFIG_DEBUG_WRITECOUNT is not set 1424# CONFIG_DEBUG_WRITECOUNT is not set
1425# CONFIG_DEBUG_MEMORY_INIT is not set
1343# CONFIG_DEBUG_LIST is not set 1426# CONFIG_DEBUG_LIST is not set
1344# CONFIG_DEBUG_SG is not set 1427# CONFIG_DEBUG_SG is not set
1345# CONFIG_BOOT_PRINTK_DELAY is not set 1428# CONFIG_BOOT_PRINTK_DELAY is not set
1346# CONFIG_RCU_TORTURE_TEST is not set 1429# CONFIG_RCU_TORTURE_TEST is not set
1347# CONFIG_BACKTRACE_SELF_TEST is not set 1430# CONFIG_BACKTRACE_SELF_TEST is not set
1348# CONFIG_FAULT_INJECTION is not set 1431# CONFIG_FAULT_INJECTION is not set
1432# CONFIG_LATENCYTOP is not set
1433CONFIG_SYSCTL_SYSCALL_CHECK=y
1434CONFIG_HAVE_FTRACE=y
1435CONFIG_HAVE_DYNAMIC_FTRACE=y
1436# CONFIG_FTRACE is not set
1437# CONFIG_SCHED_TRACER is not set
1438# CONFIG_CONTEXT_SWITCH_TRACER is not set
1349# CONFIG_SAMPLES is not set 1439# CONFIG_SAMPLES is not set
1440CONFIG_HAVE_ARCH_KGDB=y
1441# CONFIG_KGDB is not set
1350# CONFIG_DEBUG_STACKOVERFLOW is not set 1442# CONFIG_DEBUG_STACKOVERFLOW is not set
1351# CONFIG_DEBUG_STACK_USAGE is not set 1443# CONFIG_DEBUG_STACK_USAGE is not set
1352# CONFIG_DEBUG_PAGEALLOC is not set 1444# CONFIG_DEBUG_PAGEALLOC is not set
1353# CONFIG_DEBUGGER is not set 1445# CONFIG_CODE_PATCHING_SELFTEST is not set
1446# CONFIG_FTR_FIXUP_SELFTEST is not set
1447# CONFIG_XMON is not set
1354# CONFIG_IRQSTACKS is not set 1448# CONFIG_IRQSTACKS is not set
1355# CONFIG_BDI_SWITCH is not set 1449# CONFIG_BDI_SWITCH is not set
1450# CONFIG_BOOTX_TEXT is not set
1356# CONFIG_PPC_EARLY_DEBUG is not set 1451# CONFIG_PPC_EARLY_DEBUG is not set
1357 1452
1358# 1453#
@@ -1406,6 +1501,10 @@ CONFIG_CRYPTO_PCBC=m
1406# CONFIG_CRYPTO_MD4 is not set 1501# CONFIG_CRYPTO_MD4 is not set
1407CONFIG_CRYPTO_MD5=y 1502CONFIG_CRYPTO_MD5=y
1408# CONFIG_CRYPTO_MICHAEL_MIC is not set 1503# CONFIG_CRYPTO_MICHAEL_MIC is not set
1504# CONFIG_CRYPTO_RMD128 is not set
1505# CONFIG_CRYPTO_RMD160 is not set
1506# CONFIG_CRYPTO_RMD256 is not set
1507# CONFIG_CRYPTO_RMD320 is not set
1409# CONFIG_CRYPTO_SHA1 is not set 1508# CONFIG_CRYPTO_SHA1 is not set
1410# CONFIG_CRYPTO_SHA256 is not set 1509# CONFIG_CRYPTO_SHA256 is not set
1411# CONFIG_CRYPTO_SHA512 is not set 1510# CONFIG_CRYPTO_SHA512 is not set
@@ -1438,5 +1537,6 @@ CONFIG_CRYPTO_DES=y
1438# CONFIG_CRYPTO_LZO is not set 1537# CONFIG_CRYPTO_LZO is not set
1439CONFIG_CRYPTO_HW=y 1538CONFIG_CRYPTO_HW=y
1440# CONFIG_CRYPTO_DEV_HIFN_795X is not set 1539# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1540# CONFIG_CRYPTO_DEV_TALITOS is not set
1441# CONFIG_PPC_CLOCK is not set 1541# CONFIG_PPC_CLOCK is not set
1442# CONFIG_VIRTUALIZATION is not set 1542# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/configs/83xx/mpc8315_rdb_defconfig b/arch/powerpc/configs/83xx/mpc8315_rdb_defconfig
index 9bc3a03ae264..dd80eb0a87a1 100644
--- a/arch/powerpc/configs/83xx/mpc8315_rdb_defconfig
+++ b/arch/powerpc/configs/83xx/mpc8315_rdb_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc5 3# Linux kernel version: 2.6.27-rc4
4# Mon Jun 9 08:52:21 2008 4# Thu Aug 21 00:52:18 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -16,6 +16,7 @@ CONFIG_6xx=y
16# CONFIG_E200 is not set 16# CONFIG_E200 is not set
17CONFIG_PPC_FPU=y 17CONFIG_PPC_FPU=y
18# CONFIG_FSL_EMB_PERFMON is not set 18# CONFIG_FSL_EMB_PERFMON is not set
19# CONFIG_ALTIVEC is not set
19CONFIG_PPC_STD_MMU=y 20CONFIG_PPC_STD_MMU=y
20CONFIG_PPC_STD_MMU_32=y 21CONFIG_PPC_STD_MMU_32=y
21# CONFIG_PPC_MM_SLICES is not set 22# CONFIG_PPC_MM_SLICES is not set
@@ -32,6 +33,7 @@ CONFIG_GENERIC_HARDIRQS=y
32# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set 33# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
33CONFIG_IRQ_PER_CPU=y 34CONFIG_IRQ_PER_CPU=y
34CONFIG_STACKTRACE_SUPPORT=y 35CONFIG_STACKTRACE_SUPPORT=y
36CONFIG_HAVE_LATENCYTOP_SUPPORT=y
35CONFIG_LOCKDEP_SUPPORT=y 37CONFIG_LOCKDEP_SUPPORT=y
36CONFIG_RWSEM_XCHGADD_ALGORITHM=y 38CONFIG_RWSEM_XCHGADD_ALGORITHM=y
37CONFIG_ARCH_HAS_ILOG2_U32=y 39CONFIG_ARCH_HAS_ILOG2_U32=y
@@ -51,6 +53,9 @@ CONFIG_PPC_UDBG_16550=y
51CONFIG_AUDIT_ARCH=y 53CONFIG_AUDIT_ARCH=y
52CONFIG_GENERIC_BUG=y 54CONFIG_GENERIC_BUG=y
53CONFIG_DEFAULT_UIMAGE=y 55CONFIG_DEFAULT_UIMAGE=y
56CONFIG_HIBERNATE_32=y
57CONFIG_ARCH_HIBERNATION_POSSIBLE=y
58CONFIG_ARCH_SUSPEND_POSSIBLE=y
54# CONFIG_PPC_DCR_NATIVE is not set 59# CONFIG_PPC_DCR_NATIVE is not set
55# CONFIG_PPC_DCR_MMIO is not set 60# CONFIG_PPC_DCR_MMIO is not set
56CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 61CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
@@ -88,12 +93,12 @@ CONFIG_INITRAMFS_SOURCE=""
88CONFIG_SYSCTL=y 93CONFIG_SYSCTL=y
89CONFIG_EMBEDDED=y 94CONFIG_EMBEDDED=y
90CONFIG_SYSCTL_SYSCALL=y 95CONFIG_SYSCTL_SYSCALL=y
91CONFIG_SYSCTL_SYSCALL_CHECK=y
92# CONFIG_KALLSYMS is not set 96# CONFIG_KALLSYMS is not set
93CONFIG_HOTPLUG=y 97CONFIG_HOTPLUG=y
94CONFIG_PRINTK=y 98CONFIG_PRINTK=y
95CONFIG_BUG=y 99CONFIG_BUG=y
96CONFIG_ELF_CORE=y 100CONFIG_ELF_CORE=y
101CONFIG_PCSPKR_PLATFORM=y
97CONFIG_COMPAT_BRK=y 102CONFIG_COMPAT_BRK=y
98CONFIG_BASE_FULL=y 103CONFIG_BASE_FULL=y
99CONFIG_FUTEX=y 104CONFIG_FUTEX=y
@@ -111,10 +116,16 @@ CONFIG_SLUB=y
111# CONFIG_PROFILING is not set 116# CONFIG_PROFILING is not set
112# CONFIG_MARKERS is not set 117# CONFIG_MARKERS is not set
113CONFIG_HAVE_OPROFILE=y 118CONFIG_HAVE_OPROFILE=y
119CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
120CONFIG_HAVE_IOREMAP_PROT=y
114CONFIG_HAVE_KPROBES=y 121CONFIG_HAVE_KPROBES=y
115CONFIG_HAVE_KRETPROBES=y 122CONFIG_HAVE_KRETPROBES=y
123CONFIG_HAVE_ARCH_TRACEHOOK=y
116# CONFIG_HAVE_DMA_ATTRS is not set 124# CONFIG_HAVE_DMA_ATTRS is not set
125# CONFIG_USE_GENERIC_SMP_HELPERS is not set
126# CONFIG_HAVE_CLK is not set
117CONFIG_PROC_PAGE_MONITOR=y 127CONFIG_PROC_PAGE_MONITOR=y
128# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
118CONFIG_SLABINFO=y 129CONFIG_SLABINFO=y
119CONFIG_RT_MUTEXES=y 130CONFIG_RT_MUTEXES=y
120# CONFIG_TINY_SHMEM is not set 131# CONFIG_TINY_SHMEM is not set
@@ -125,12 +136,13 @@ CONFIG_MODULE_UNLOAD=y
125# CONFIG_MODULE_FORCE_UNLOAD is not set 136# CONFIG_MODULE_FORCE_UNLOAD is not set
126# CONFIG_MODVERSIONS is not set 137# CONFIG_MODVERSIONS is not set
127# CONFIG_MODULE_SRCVERSION_ALL is not set 138# CONFIG_MODULE_SRCVERSION_ALL is not set
128# CONFIG_KMOD is not set 139CONFIG_KMOD=y
129CONFIG_BLOCK=y 140CONFIG_BLOCK=y
130# CONFIG_LBD is not set 141# CONFIG_LBD is not set
131# CONFIG_BLK_DEV_IO_TRACE is not set 142# CONFIG_BLK_DEV_IO_TRACE is not set
132# CONFIG_LSF is not set 143# CONFIG_LSF is not set
133# CONFIG_BLK_DEV_BSG is not set 144# CONFIG_BLK_DEV_BSG is not set
145# CONFIG_BLK_DEV_INTEGRITY is not set
134 146
135# 147#
136# IO Schedulers 148# IO Schedulers
@@ -149,37 +161,49 @@ CONFIG_CLASSIC_RCU=y
149# 161#
150# Platform support 162# Platform support
151# 163#
152# CONFIG_PPC_MULTIPLATFORM is not set 164CONFIG_PPC_MULTIPLATFORM=y
153# CONFIG_PPC_82xx is not set 165CONFIG_CLASSIC32=y
154CONFIG_PPC_83xx=y 166CONFIG_PPC_CHRP=y
155# CONFIG_PPC_86xx is not set 167# CONFIG_MPC5121_ADS is not set
156# CONFIG_PPC_MPC512x is not set 168# CONFIG_MPC5121_GENERIC is not set
157# CONFIG_PPC_MPC5121 is not set 169# CONFIG_PPC_MPC52xx is not set
170CONFIG_PPC_PMAC=y
158# CONFIG_PPC_CELL is not set 171# CONFIG_PPC_CELL is not set
159# CONFIG_PPC_CELL_NATIVE is not set 172# CONFIG_PPC_CELL_NATIVE is not set
173# CONFIG_PPC_82xx is not set
160# CONFIG_PQ2ADS is not set 174# CONFIG_PQ2ADS is not set
161CONFIG_MPC83xx=y 175CONFIG_PPC_83xx=y
162CONFIG_MPC831x_RDB=y 176CONFIG_MPC831x_RDB=y
163# CONFIG_MPC832x_MDS is not set 177# CONFIG_MPC832x_MDS is not set
164# CONFIG_MPC832x_RDB is not set 178# CONFIG_MPC832x_RDB is not set
165# CONFIG_MPC834x_MDS is not set 179# CONFIG_MPC834x_MDS is not set
166# CONFIG_MPC834x_ITX is not set 180# CONFIG_MPC834x_ITX is not set
167# CONFIG_MPC836x_MDS is not set 181# CONFIG_MPC836x_MDS is not set
182# CONFIG_MPC836x_RDK is not set
168# CONFIG_MPC837x_MDS is not set 183# CONFIG_MPC837x_MDS is not set
169# CONFIG_MPC837x_RDB is not set 184# CONFIG_MPC837x_RDB is not set
170# CONFIG_SBC834x is not set 185# CONFIG_SBC834x is not set
186# CONFIG_ASP834x is not set
171CONFIG_PPC_MPC831x=y 187CONFIG_PPC_MPC831x=y
188# CONFIG_PPC_86xx is not set
189# CONFIG_EMBEDDED6xx is not set
190CONFIG_PPC_NATIVE=y
191# CONFIG_UDBG_RTAS_CONSOLE is not set
172CONFIG_IPIC=y 192CONFIG_IPIC=y
173# CONFIG_MPIC is not set 193CONFIG_MPIC=y
174# CONFIG_MPIC_WEIRD is not set 194# CONFIG_MPIC_WEIRD is not set
175# CONFIG_PPC_I8259 is not set 195CONFIG_PPC_I8259=y
176# CONFIG_PPC_RTAS is not set 196CONFIG_PPC_RTAS=y
197# CONFIG_RTAS_ERROR_LOGGING is not set
198CONFIG_RTAS_PROC=y
177# CONFIG_MMIO_NVRAM is not set 199# CONFIG_MMIO_NVRAM is not set
178# CONFIG_PPC_MPC106 is not set 200CONFIG_PPC_MPC106=y
179# CONFIG_PPC_970_NAP is not set 201# CONFIG_PPC_970_NAP is not set
180# CONFIG_PPC_INDIRECT_IO is not set 202# CONFIG_PPC_INDIRECT_IO is not set
181# CONFIG_GENERIC_IOMAP is not set 203# CONFIG_GENERIC_IOMAP is not set
182# CONFIG_CPU_FREQ is not set 204# CONFIG_CPU_FREQ is not set
205# CONFIG_PPC601_SYNC_FIX is not set
206# CONFIG_TAU is not set
183# CONFIG_FSL_ULI1575 is not set 207# CONFIG_FSL_ULI1575 is not set
184 208
185# 209#
@@ -195,7 +219,7 @@ CONFIG_HZ_250=y
195# CONFIG_HZ_300 is not set 219# CONFIG_HZ_300 is not set
196# CONFIG_HZ_1000 is not set 220# CONFIG_HZ_1000 is not set
197CONFIG_HZ=250 221CONFIG_HZ=250
198# CONFIG_SCHED_HRTICK is not set 222CONFIG_SCHED_HRTICK=y
199CONFIG_PREEMPT_NONE=y 223CONFIG_PREEMPT_NONE=y
200# CONFIG_PREEMPT_VOLUNTARY is not set 224# CONFIG_PREEMPT_VOLUNTARY is not set
201# CONFIG_PREEMPT is not set 225# CONFIG_PREEMPT is not set
@@ -205,6 +229,7 @@ CONFIG_BINFMT_ELF=y
205CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y 229CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
206CONFIG_ARCH_HAS_WALK_MEMORY=y 230CONFIG_ARCH_HAS_WALK_MEMORY=y
207CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y 231CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
232# CONFIG_KEXEC is not set
208CONFIG_ARCH_FLATMEM_ENABLE=y 233CONFIG_ARCH_FLATMEM_ENABLE=y
209CONFIG_ARCH_POPULATES_NODE_MAP=y 234CONFIG_ARCH_POPULATES_NODE_MAP=y
210CONFIG_SELECT_MEMORY_MODEL=y 235CONFIG_SELECT_MEMORY_MODEL=y
@@ -217,6 +242,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
217# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set 242# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
218CONFIG_PAGEFLAGS_EXTENDED=y 243CONFIG_PAGEFLAGS_EXTENDED=y
219CONFIG_SPLIT_PTLOCK_CPUS=4 244CONFIG_SPLIT_PTLOCK_CPUS=4
245CONFIG_MIGRATION=y
220# CONFIG_RESOURCES_64BIT is not set 246# CONFIG_RESOURCES_64BIT is not set
221CONFIG_ZONE_DMA_FLAG=1 247CONFIG_ZONE_DMA_FLAG=1
222CONFIG_BOUNCE=y 248CONFIG_BOUNCE=y
@@ -224,6 +250,7 @@ CONFIG_VIRT_TO_BUS=y
224CONFIG_FORCE_MAX_ZONEORDER=11 250CONFIG_FORCE_MAX_ZONEORDER=11
225CONFIG_PROC_DEVICETREE=y 251CONFIG_PROC_DEVICETREE=y
226# CONFIG_CMDLINE_BOOL is not set 252# CONFIG_CMDLINE_BOOL is not set
253CONFIG_EXTRA_TARGETS=""
227# CONFIG_PM is not set 254# CONFIG_PM is not set
228CONFIG_SECCOMP=y 255CONFIG_SECCOMP=y
229CONFIG_ISA_DMA_API=y 256CONFIG_ISA_DMA_API=y
@@ -231,10 +258,13 @@ CONFIG_ISA_DMA_API=y
231# 258#
232# Bus options 259# Bus options
233# 260#
261# CONFIG_ISA is not set
234CONFIG_ZONE_DMA=y 262CONFIG_ZONE_DMA=y
235CONFIG_GENERIC_ISA_DMA=y 263CONFIG_GENERIC_ISA_DMA=y
236CONFIG_PPC_INDIRECT_PCI=y 264CONFIG_PPC_INDIRECT_PCI=y
237CONFIG_FSL_SOC=y 265CONFIG_FSL_SOC=y
266CONFIG_FSL_PCI=y
267CONFIG_PPC_PCI_CHOICE=y
238CONFIG_PCI=y 268CONFIG_PCI=y
239CONFIG_PCI_DOMAINS=y 269CONFIG_PCI_DOMAINS=y
240CONFIG_PCI_SYSCALL=y 270CONFIG_PCI_SYSCALL=y
@@ -260,10 +290,6 @@ CONFIG_PAGE_OFFSET=0xc0000000
260CONFIG_KERNEL_START=0xc0000000 290CONFIG_KERNEL_START=0xc0000000
261CONFIG_PHYSICAL_START=0x00000000 291CONFIG_PHYSICAL_START=0x00000000
262CONFIG_TASK_SIZE=0xc0000000 292CONFIG_TASK_SIZE=0xc0000000
263
264#
265# Networking
266#
267CONFIG_NET=y 293CONFIG_NET=y
268 294
269# 295#
@@ -452,9 +478,11 @@ CONFIG_MTD_NAND_IDS=y
452# CONFIG_MTD_UBI is not set 478# CONFIG_MTD_UBI is not set
453CONFIG_OF_DEVICE=y 479CONFIG_OF_DEVICE=y
454CONFIG_OF_I2C=y 480CONFIG_OF_I2C=y
481CONFIG_OF_SPI=y
455# CONFIG_PARPORT is not set 482# CONFIG_PARPORT is not set
456CONFIG_BLK_DEV=y 483CONFIG_BLK_DEV=y
457# CONFIG_BLK_DEV_FD is not set 484# CONFIG_BLK_DEV_FD is not set
485# CONFIG_MAC_FLOPPY is not set
458# CONFIG_BLK_CPQ_DA is not set 486# CONFIG_BLK_CPQ_DA is not set
459# CONFIG_BLK_CPQ_CISS_DA is not set 487# CONFIG_BLK_CPQ_CISS_DA is not set
460# CONFIG_BLK_DEV_DAC960 is not set 488# CONFIG_BLK_DEV_DAC960 is not set
@@ -471,12 +499,14 @@ CONFIG_BLK_DEV_RAM_SIZE=32768
471# CONFIG_BLK_DEV_XIP is not set 499# CONFIG_BLK_DEV_XIP is not set
472# CONFIG_CDROM_PKTCDVD is not set 500# CONFIG_CDROM_PKTCDVD is not set
473# CONFIG_ATA_OVER_ETH is not set 501# CONFIG_ATA_OVER_ETH is not set
502# CONFIG_BLK_DEV_HD is not set
474CONFIG_MISC_DEVICES=y 503CONFIG_MISC_DEVICES=y
475# CONFIG_PHANTOM is not set 504# CONFIG_PHANTOM is not set
476# CONFIG_EEPROM_93CX6 is not set 505# CONFIG_EEPROM_93CX6 is not set
477# CONFIG_SGI_IOC4 is not set 506# CONFIG_SGI_IOC4 is not set
478# CONFIG_TIFM_CORE is not set 507# CONFIG_TIFM_CORE is not set
479# CONFIG_ENCLOSURE_SERVICES is not set 508# CONFIG_ENCLOSURE_SERVICES is not set
509# CONFIG_HP_ILO is not set
480CONFIG_HAVE_IDE=y 510CONFIG_HAVE_IDE=y
481# CONFIG_IDE is not set 511# CONFIG_IDE is not set
482 512
@@ -554,7 +584,10 @@ CONFIG_SCSI_LOWLEVEL=y
554# CONFIG_SCSI_DC390T is not set 584# CONFIG_SCSI_DC390T is not set
555# CONFIG_SCSI_NSP32 is not set 585# CONFIG_SCSI_NSP32 is not set
556# CONFIG_SCSI_DEBUG is not set 586# CONFIG_SCSI_DEBUG is not set
587# CONFIG_SCSI_MESH is not set
588# CONFIG_SCSI_MAC53C94 is not set
557# CONFIG_SCSI_SRP is not set 589# CONFIG_SCSI_SRP is not set
590# CONFIG_SCSI_DH is not set
558CONFIG_ATA=y 591CONFIG_ATA=y
559# CONFIG_ATA_NONSTANDARD is not set 592# CONFIG_ATA_NONSTANDARD is not set
560CONFIG_SATA_PMP=y 593CONFIG_SATA_PMP=y
@@ -631,12 +664,15 @@ CONFIG_MD_RAID1=y
631# 664#
632# IEEE 1394 (FireWire) support 665# IEEE 1394 (FireWire) support
633# 666#
667
668#
669# Enable only one of the two stacks, unless you know what you are doing
670#
634# CONFIG_FIREWIRE is not set 671# CONFIG_FIREWIRE is not set
635# CONFIG_IEEE1394 is not set 672# CONFIG_IEEE1394 is not set
636# CONFIG_I2O is not set 673# CONFIG_I2O is not set
637# CONFIG_MACINTOSH_DRIVERS is not set 674# CONFIG_MACINTOSH_DRIVERS is not set
638CONFIG_NETDEVICES=y 675CONFIG_NETDEVICES=y
639# CONFIG_NETDEVICES_MULTIQUEUE is not set
640# CONFIG_DUMMY is not set 676# CONFIG_DUMMY is not set
641# CONFIG_BONDING is not set 677# CONFIG_BONDING is not set
642# CONFIG_MACVLAN is not set 678# CONFIG_MACVLAN is not set
@@ -663,6 +699,8 @@ CONFIG_PHYLIB=y
663# CONFIG_MDIO_BITBANG is not set 699# CONFIG_MDIO_BITBANG is not set
664CONFIG_NET_ETHERNET=y 700CONFIG_NET_ETHERNET=y
665CONFIG_MII=y 701CONFIG_MII=y
702# CONFIG_MACE is not set
703# CONFIG_BMAC is not set
666# CONFIG_HAPPYMEAL is not set 704# CONFIG_HAPPYMEAL is not set
667# CONFIG_SUNGEM is not set 705# CONFIG_SUNGEM is not set
668# CONFIG_CASSINI is not set 706# CONFIG_CASSINI is not set
@@ -699,7 +737,6 @@ CONFIG_NETDEV_1000=y
699# CONFIG_DL2K is not set 737# CONFIG_DL2K is not set
700# CONFIG_E1000 is not set 738# CONFIG_E1000 is not set
701# CONFIG_E1000E is not set 739# CONFIG_E1000E is not set
702# CONFIG_E1000E_ENABLED is not set
703# CONFIG_IP1000 is not set 740# CONFIG_IP1000 is not set
704# CONFIG_IGB is not set 741# CONFIG_IGB is not set
705# CONFIG_NS83820 is not set 742# CONFIG_NS83820 is not set
@@ -713,9 +750,10 @@ CONFIG_NETDEV_1000=y
713# CONFIG_TIGON3 is not set 750# CONFIG_TIGON3 is not set
714# CONFIG_BNX2 is not set 751# CONFIG_BNX2 is not set
715CONFIG_GIANFAR=y 752CONFIG_GIANFAR=y
716CONFIG_GFAR_NAPI=y 753# CONFIG_MV643XX_ETH is not set
717# CONFIG_QLA3XXX is not set 754# CONFIG_QLA3XXX is not set
718# CONFIG_ATL1 is not set 755# CONFIG_ATL1 is not set
756# CONFIG_ATL1E is not set
719CONFIG_NETDEV_10000=y 757CONFIG_NETDEV_10000=y
720# CONFIG_CHELSIO_T1 is not set 758# CONFIG_CHELSIO_T1 is not set
721# CONFIG_CHELSIO_T3 is not set 759# CONFIG_CHELSIO_T3 is not set
@@ -813,11 +851,14 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=4
813# CONFIG_SERIAL_UARTLITE is not set 851# CONFIG_SERIAL_UARTLITE is not set
814CONFIG_SERIAL_CORE=y 852CONFIG_SERIAL_CORE=y
815CONFIG_SERIAL_CORE_CONSOLE=y 853CONFIG_SERIAL_CORE_CONSOLE=y
854# CONFIG_SERIAL_PMACZILOG is not set
816# CONFIG_SERIAL_JSM is not set 855# CONFIG_SERIAL_JSM is not set
817# CONFIG_SERIAL_OF_PLATFORM is not set 856# CONFIG_SERIAL_OF_PLATFORM is not set
818CONFIG_UNIX98_PTYS=y 857CONFIG_UNIX98_PTYS=y
819CONFIG_LEGACY_PTYS=y 858CONFIG_LEGACY_PTYS=y
820CONFIG_LEGACY_PTY_COUNT=256 859CONFIG_LEGACY_PTY_COUNT=256
860# CONFIG_BRIQ_PANEL is not set
861# CONFIG_HVC_RTAS is not set
821# CONFIG_IPMI_HANDLER is not set 862# CONFIG_IPMI_HANDLER is not set
822CONFIG_HW_RANDOM=y 863CONFIG_HW_RANDOM=y
823# CONFIG_NVRAM is not set 864# CONFIG_NVRAM is not set
@@ -829,43 +870,70 @@ CONFIG_DEVPORT=y
829CONFIG_I2C=y 870CONFIG_I2C=y
830CONFIG_I2C_BOARDINFO=y 871CONFIG_I2C_BOARDINFO=y
831CONFIG_I2C_CHARDEV=y 872CONFIG_I2C_CHARDEV=y
873CONFIG_I2C_HELPER_AUTO=y
832 874
833# 875#
834# I2C Hardware Bus support 876# I2C Hardware Bus support
835# 877#
878
879#
880# PC SMBus host controller drivers
881#
836# CONFIG_I2C_ALI1535 is not set 882# CONFIG_I2C_ALI1535 is not set
837# CONFIG_I2C_ALI1563 is not set 883# CONFIG_I2C_ALI1563 is not set
838# CONFIG_I2C_ALI15X3 is not set 884# CONFIG_I2C_ALI15X3 is not set
839# CONFIG_I2C_AMD756 is not set 885# CONFIG_I2C_AMD756 is not set
840# CONFIG_I2C_AMD8111 is not set 886# CONFIG_I2C_AMD8111 is not set
841# CONFIG_I2C_I801 is not set 887# CONFIG_I2C_I801 is not set
842# CONFIG_I2C_I810 is not set 888# CONFIG_I2C_ISCH is not set
843# CONFIG_I2C_PIIX4 is not set 889# CONFIG_I2C_PIIX4 is not set
844CONFIG_I2C_MPC=y
845# CONFIG_I2C_NFORCE2 is not set 890# CONFIG_I2C_NFORCE2 is not set
846# CONFIG_I2C_OCORES is not set
847# CONFIG_I2C_PARPORT_LIGHT is not set
848# CONFIG_I2C_PROSAVAGE is not set
849# CONFIG_I2C_SAVAGE4 is not set
850# CONFIG_I2C_SIMTEC is not set
851# CONFIG_I2C_SIS5595 is not set 891# CONFIG_I2C_SIS5595 is not set
852# CONFIG_I2C_SIS630 is not set 892# CONFIG_I2C_SIS630 is not set
853# CONFIG_I2C_SIS96X is not set 893# CONFIG_I2C_SIS96X is not set
854# CONFIG_I2C_TAOS_EVM is not set
855# CONFIG_I2C_STUB is not set
856# CONFIG_I2C_TINY_USB is not set
857# CONFIG_I2C_VIA is not set 894# CONFIG_I2C_VIA is not set
858# CONFIG_I2C_VIAPRO is not set 895# CONFIG_I2C_VIAPRO is not set
896
897#
898# Mac SMBus host controller drivers
899#
900# CONFIG_I2C_HYDRA is not set
901CONFIG_I2C_POWERMAC=y
902
903#
904# I2C system bus drivers (mostly embedded / system-on-chip)
905#
906CONFIG_I2C_MPC=y
907# CONFIG_I2C_OCORES is not set
908# CONFIG_I2C_SIMTEC is not set
909
910#
911# External I2C/SMBus adapter drivers
912#
913# CONFIG_I2C_PARPORT_LIGHT is not set
914# CONFIG_I2C_TAOS_EVM is not set
915# CONFIG_I2C_TINY_USB is not set
916
917#
918# Graphics adapter I2C/DDC channel drivers
919#
859# CONFIG_I2C_VOODOO3 is not set 920# CONFIG_I2C_VOODOO3 is not set
921
922#
923# Other I2C/SMBus bus drivers
924#
860# CONFIG_I2C_PCA_PLATFORM is not set 925# CONFIG_I2C_PCA_PLATFORM is not set
926# CONFIG_I2C_STUB is not set
861 927
862# 928#
863# Miscellaneous I2C Chip support 929# Miscellaneous I2C Chip support
864# 930#
865# CONFIG_DS1682 is not set 931# CONFIG_DS1682 is not set
932# CONFIG_AT24 is not set
866# CONFIG_SENSORS_EEPROM is not set 933# CONFIG_SENSORS_EEPROM is not set
867# CONFIG_SENSORS_PCF8574 is not set 934# CONFIG_SENSORS_PCF8574 is not set
868# CONFIG_PCF8575 is not set 935# CONFIG_PCF8575 is not set
936# CONFIG_SENSORS_PCA9539 is not set
869# CONFIG_SENSORS_PCF8591 is not set 937# CONFIG_SENSORS_PCF8591 is not set
870# CONFIG_SENSORS_MAX6875 is not set 938# CONFIG_SENSORS_MAX6875 is not set
871# CONFIG_SENSORS_TSL2550 is not set 939# CONFIG_SENSORS_TSL2550 is not set
@@ -889,11 +957,15 @@ CONFIG_SPI_MPC83xx=y
889# CONFIG_SPI_AT25 is not set 957# CONFIG_SPI_AT25 is not set
890# CONFIG_SPI_SPIDEV is not set 958# CONFIG_SPI_SPIDEV is not set
891# CONFIG_SPI_TLE62X0 is not set 959# CONFIG_SPI_TLE62X0 is not set
960CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
961# CONFIG_GPIOLIB is not set
892# CONFIG_W1 is not set 962# CONFIG_W1 is not set
893# CONFIG_POWER_SUPPLY is not set 963# CONFIG_POWER_SUPPLY is not set
894CONFIG_HWMON=y 964CONFIG_HWMON=y
895# CONFIG_HWMON_VID is not set 965# CONFIG_HWMON_VID is not set
966# CONFIG_SENSORS_AD7414 is not set
896# CONFIG_SENSORS_AD7418 is not set 967# CONFIG_SENSORS_AD7418 is not set
968# CONFIG_SENSORS_ADCXX is not set
897# CONFIG_SENSORS_ADM1021 is not set 969# CONFIG_SENSORS_ADM1021 is not set
898# CONFIG_SENSORS_ADM1025 is not set 970# CONFIG_SENSORS_ADM1025 is not set
899# CONFIG_SENSORS_ADM1026 is not set 971# CONFIG_SENSORS_ADM1026 is not set
@@ -902,6 +974,7 @@ CONFIG_HWMON=y
902# CONFIG_SENSORS_ADM9240 is not set 974# CONFIG_SENSORS_ADM9240 is not set
903# CONFIG_SENSORS_ADT7470 is not set 975# CONFIG_SENSORS_ADT7470 is not set
904# CONFIG_SENSORS_ADT7473 is not set 976# CONFIG_SENSORS_ADT7473 is not set
977# CONFIG_SENSORS_AMS is not set
905# CONFIG_SENSORS_ATXP1 is not set 978# CONFIG_SENSORS_ATXP1 is not set
906# CONFIG_SENSORS_DS1621 is not set 979# CONFIG_SENSORS_DS1621 is not set
907# CONFIG_SENSORS_I5K_AMB is not set 980# CONFIG_SENSORS_I5K_AMB is not set
@@ -947,6 +1020,7 @@ CONFIG_HWMON=y
947# CONFIG_SENSORS_W83627EHF is not set 1020# CONFIG_SENSORS_W83627EHF is not set
948# CONFIG_HWMON_DEBUG_CHIP is not set 1021# CONFIG_HWMON_DEBUG_CHIP is not set
949# CONFIG_THERMAL is not set 1022# CONFIG_THERMAL is not set
1023# CONFIG_THERMAL_HWMON is not set
950CONFIG_WATCHDOG=y 1024CONFIG_WATCHDOG=y
951# CONFIG_WATCHDOG_NOWAYOUT is not set 1025# CONFIG_WATCHDOG_NOWAYOUT is not set
952 1026
@@ -954,7 +1028,9 @@ CONFIG_WATCHDOG=y
954# Watchdog Device Drivers 1028# Watchdog Device Drivers
955# 1029#
956# CONFIG_SOFT_WATCHDOG is not set 1030# CONFIG_SOFT_WATCHDOG is not set
957CONFIG_83xx_WDT=y 1031# CONFIG_ALIM7101_WDT is not set
1032# CONFIG_8xxx_WDT is not set
1033# CONFIG_WATCHDOG_RTAS is not set
958 1034
959# 1035#
960# PCI-based Watchdog Cards 1036# PCI-based Watchdog Cards
@@ -976,8 +1052,10 @@ CONFIG_SSB_POSSIBLE=y
976# 1052#
977# Multifunction device drivers 1053# Multifunction device drivers
978# 1054#
1055# CONFIG_MFD_CORE is not set
979# CONFIG_MFD_SM501 is not set 1056# CONFIG_MFD_SM501 is not set
980# CONFIG_HTC_PASIC3 is not set 1057# CONFIG_HTC_PASIC3 is not set
1058# CONFIG_MFD_TMIO is not set
981 1059
982# 1060#
983# Multimedia devices 1061# Multimedia devices
@@ -1010,10 +1088,6 @@ CONFIG_VIDEO_OUTPUT_CONTROL=m
1010# Display device support 1088# Display device support
1011# 1089#
1012# CONFIG_DISPLAY_SUPPORT is not set 1090# CONFIG_DISPLAY_SUPPORT is not set
1013
1014#
1015# Sound
1016#
1017# CONFIG_SOUND is not set 1091# CONFIG_SOUND is not set
1018CONFIG_HID_SUPPORT=y 1092CONFIG_HID_SUPPORT=y
1019CONFIG_HID=y 1093CONFIG_HID=y
@@ -1047,6 +1121,7 @@ CONFIG_USB_DEVICE_CLASS=y
1047# CONFIG_USB_OTG is not set 1121# CONFIG_USB_OTG is not set
1048# CONFIG_USB_OTG_WHITELIST is not set 1122# CONFIG_USB_OTG_WHITELIST is not set
1049# CONFIG_USB_OTG_BLACKLIST_HUB is not set 1123# CONFIG_USB_OTG_BLACKLIST_HUB is not set
1124CONFIG_USB_MON=y
1050 1125
1051# 1126#
1052# USB Host Controller Drivers 1127# USB Host Controller Drivers
@@ -1070,6 +1145,7 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y
1070CONFIG_USB_UHCI_HCD=y 1145CONFIG_USB_UHCI_HCD=y
1071# CONFIG_USB_SL811_HCD is not set 1146# CONFIG_USB_SL811_HCD is not set
1072# CONFIG_USB_R8A66597_HCD is not set 1147# CONFIG_USB_R8A66597_HCD is not set
1148# CONFIG_USB_GADGET_MUSB_HDRC is not set
1073 1149
1074# 1150#
1075# USB Device Class drivers 1151# USB Device Class drivers
@@ -1098,6 +1174,7 @@ CONFIG_USB_STORAGE=y
1098# CONFIG_USB_STORAGE_ALAUDA is not set 1174# CONFIG_USB_STORAGE_ALAUDA is not set
1099# CONFIG_USB_STORAGE_ONETOUCH is not set 1175# CONFIG_USB_STORAGE_ONETOUCH is not set
1100# CONFIG_USB_STORAGE_KARMA is not set 1176# CONFIG_USB_STORAGE_KARMA is not set
1177# CONFIG_USB_STORAGE_SIERRA is not set
1101# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set 1178# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
1102# CONFIG_USB_LIBUSUAL is not set 1179# CONFIG_USB_LIBUSUAL is not set
1103 1180
@@ -1106,7 +1183,6 @@ CONFIG_USB_STORAGE=y
1106# 1183#
1107# CONFIG_USB_MDC800 is not set 1184# CONFIG_USB_MDC800 is not set
1108# CONFIG_USB_MICROTEK is not set 1185# CONFIG_USB_MICROTEK is not set
1109CONFIG_USB_MON=y
1110 1186
1111# 1187#
1112# USB port drivers 1188# USB port drivers
@@ -1119,7 +1195,6 @@ CONFIG_USB_MON=y
1119# CONFIG_USB_EMI62 is not set 1195# CONFIG_USB_EMI62 is not set
1120# CONFIG_USB_EMI26 is not set 1196# CONFIG_USB_EMI26 is not set
1121# CONFIG_USB_ADUTUX is not set 1197# CONFIG_USB_ADUTUX is not set
1122# CONFIG_USB_AUERSWALD is not set
1123# CONFIG_USB_RIO500 is not set 1198# CONFIG_USB_RIO500 is not set
1124# CONFIG_USB_LEGOTOWER is not set 1199# CONFIG_USB_LEGOTOWER is not set
1125# CONFIG_USB_LCD is not set 1200# CONFIG_USB_LCD is not set
@@ -1146,7 +1221,7 @@ CONFIG_USB_GADGET_SELECTED=y
1146# CONFIG_USB_GADGET_FSL_USB2 is not set 1221# CONFIG_USB_GADGET_FSL_USB2 is not set
1147CONFIG_USB_GADGET_NET2280=y 1222CONFIG_USB_GADGET_NET2280=y
1148CONFIG_USB_NET2280=y 1223CONFIG_USB_NET2280=y
1149# CONFIG_USB_GADGET_PXA2XX is not set 1224# CONFIG_USB_GADGET_PXA25X is not set
1150# CONFIG_USB_GADGET_M66592 is not set 1225# CONFIG_USB_GADGET_M66592 is not set
1151# CONFIG_USB_GADGET_PXA27X is not set 1226# CONFIG_USB_GADGET_PXA27X is not set
1152# CONFIG_USB_GADGET_GOKU is not set 1227# CONFIG_USB_GADGET_GOKU is not set
@@ -1164,6 +1239,7 @@ CONFIG_USB_ETH_RNDIS=y
1164# CONFIG_USB_G_SERIAL is not set 1239# CONFIG_USB_G_SERIAL is not set
1165# CONFIG_USB_MIDI_GADGET is not set 1240# CONFIG_USB_MIDI_GADGET is not set
1166# CONFIG_USB_G_PRINTER is not set 1241# CONFIG_USB_G_PRINTER is not set
1242# CONFIG_USB_CDC_COMPOSITE is not set
1167# CONFIG_MMC is not set 1243# CONFIG_MMC is not set
1168# CONFIG_MEMSTICK is not set 1244# CONFIG_MEMSTICK is not set
1169# CONFIG_NEW_LEDS is not set 1245# CONFIG_NEW_LEDS is not set
@@ -1199,10 +1275,13 @@ CONFIG_RTC_DRV_DS1307=y
1199# CONFIG_RTC_DRV_PCF8583 is not set 1275# CONFIG_RTC_DRV_PCF8583 is not set
1200# CONFIG_RTC_DRV_M41T80 is not set 1276# CONFIG_RTC_DRV_M41T80 is not set
1201# CONFIG_RTC_DRV_S35390A is not set 1277# CONFIG_RTC_DRV_S35390A is not set
1278# CONFIG_RTC_DRV_FM3130 is not set
1202 1279
1203# 1280#
1204# SPI RTC drivers 1281# SPI RTC drivers
1205# 1282#
1283# CONFIG_RTC_DRV_M41T94 is not set
1284# CONFIG_RTC_DRV_DS1305 is not set
1206# CONFIG_RTC_DRV_MAX6902 is not set 1285# CONFIG_RTC_DRV_MAX6902 is not set
1207# CONFIG_RTC_DRV_R9701 is not set 1286# CONFIG_RTC_DRV_R9701 is not set
1208# CONFIG_RTC_DRV_RS5C348 is not set 1287# CONFIG_RTC_DRV_RS5C348 is not set
@@ -1301,6 +1380,7 @@ CONFIG_JFFS2_RTIME=y
1301# CONFIG_CRAMFS is not set 1380# CONFIG_CRAMFS is not set
1302# CONFIG_VXFS_FS is not set 1381# CONFIG_VXFS_FS is not set
1303# CONFIG_MINIX_FS is not set 1382# CONFIG_MINIX_FS is not set
1383# CONFIG_OMFS_FS is not set
1304# CONFIG_HPFS_FS is not set 1384# CONFIG_HPFS_FS is not set
1305# CONFIG_QNX4FS_FS is not set 1385# CONFIG_QNX4FS_FS is not set
1306# CONFIG_ROMFS_FS is not set 1386# CONFIG_ROMFS_FS is not set
@@ -1311,14 +1391,13 @@ CONFIG_NFS_FS=y
1311CONFIG_NFS_V3=y 1391CONFIG_NFS_V3=y
1312# CONFIG_NFS_V3_ACL is not set 1392# CONFIG_NFS_V3_ACL is not set
1313CONFIG_NFS_V4=y 1393CONFIG_NFS_V4=y
1314# CONFIG_NFSD is not set
1315CONFIG_ROOT_NFS=y 1394CONFIG_ROOT_NFS=y
1395# CONFIG_NFSD is not set
1316CONFIG_LOCKD=y 1396CONFIG_LOCKD=y
1317CONFIG_LOCKD_V4=y 1397CONFIG_LOCKD_V4=y
1318CONFIG_NFS_COMMON=y 1398CONFIG_NFS_COMMON=y
1319CONFIG_SUNRPC=y 1399CONFIG_SUNRPC=y
1320CONFIG_SUNRPC_GSS=y 1400CONFIG_SUNRPC_GSS=y
1321# CONFIG_SUNRPC_BIND34 is not set
1322CONFIG_RPCSEC_GSS_KRB5=y 1401CONFIG_RPCSEC_GSS_KRB5=y
1323# CONFIG_RPCSEC_GSS_SPKM3 is not set 1402# CONFIG_RPCSEC_GSS_SPKM3 is not set
1324# CONFIG_SMB_FS is not set 1403# CONFIG_SMB_FS is not set
@@ -1358,6 +1437,7 @@ CONFIG_BITREVERSE=y
1358# CONFIG_GENERIC_FIND_FIRST_BIT is not set 1437# CONFIG_GENERIC_FIND_FIRST_BIT is not set
1359# CONFIG_CRC_CCITT is not set 1438# CONFIG_CRC_CCITT is not set
1360# CONFIG_CRC16 is not set 1439# CONFIG_CRC16 is not set
1440# CONFIG_CRC_T10DIF is not set
1361# CONFIG_CRC_ITU_T is not set 1441# CONFIG_CRC_ITU_T is not set
1362CONFIG_CRC32=y 1442CONFIG_CRC32=y
1363# CONFIG_CRC7 is not set 1443# CONFIG_CRC7 is not set
@@ -1384,6 +1464,8 @@ CONFIG_FRAME_WARN=1024
1384CONFIG_DEBUG_KERNEL=y 1464CONFIG_DEBUG_KERNEL=y
1385# CONFIG_DEBUG_SHIRQ is not set 1465# CONFIG_DEBUG_SHIRQ is not set
1386CONFIG_DETECT_SOFTLOCKUP=y 1466CONFIG_DETECT_SOFTLOCKUP=y
1467# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
1468CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
1387CONFIG_SCHED_DEBUG=y 1469CONFIG_SCHED_DEBUG=y
1388# CONFIG_SCHEDSTATS is not set 1470# CONFIG_SCHEDSTATS is not set
1389# CONFIG_TIMER_STATS is not set 1471# CONFIG_TIMER_STATS is not set
@@ -1401,19 +1483,32 @@ CONFIG_SCHED_DEBUG=y
1401# CONFIG_DEBUG_INFO is not set 1483# CONFIG_DEBUG_INFO is not set
1402# CONFIG_DEBUG_VM is not set 1484# CONFIG_DEBUG_VM is not set
1403# CONFIG_DEBUG_WRITECOUNT is not set 1485# CONFIG_DEBUG_WRITECOUNT is not set
1486# CONFIG_DEBUG_MEMORY_INIT is not set
1404# CONFIG_DEBUG_LIST is not set 1487# CONFIG_DEBUG_LIST is not set
1405# CONFIG_DEBUG_SG is not set 1488# CONFIG_DEBUG_SG is not set
1406# CONFIG_BOOT_PRINTK_DELAY is not set 1489# CONFIG_BOOT_PRINTK_DELAY is not set
1407# CONFIG_RCU_TORTURE_TEST is not set 1490# CONFIG_RCU_TORTURE_TEST is not set
1408# CONFIG_BACKTRACE_SELF_TEST is not set 1491# CONFIG_BACKTRACE_SELF_TEST is not set
1409# CONFIG_FAULT_INJECTION is not set 1492# CONFIG_FAULT_INJECTION is not set
1493# CONFIG_LATENCYTOP is not set
1494CONFIG_SYSCTL_SYSCALL_CHECK=y
1495CONFIG_HAVE_FTRACE=y
1496CONFIG_HAVE_DYNAMIC_FTRACE=y
1497# CONFIG_FTRACE is not set
1498# CONFIG_SCHED_TRACER is not set
1499# CONFIG_CONTEXT_SWITCH_TRACER is not set
1410# CONFIG_SAMPLES is not set 1500# CONFIG_SAMPLES is not set
1501CONFIG_HAVE_ARCH_KGDB=y
1502# CONFIG_KGDB is not set
1411# CONFIG_DEBUG_STACKOVERFLOW is not set 1503# CONFIG_DEBUG_STACKOVERFLOW is not set
1412# CONFIG_DEBUG_STACK_USAGE is not set 1504# CONFIG_DEBUG_STACK_USAGE is not set
1413# CONFIG_DEBUG_PAGEALLOC is not set 1505# CONFIG_DEBUG_PAGEALLOC is not set
1414# CONFIG_DEBUGGER is not set 1506# CONFIG_CODE_PATCHING_SELFTEST is not set
1507# CONFIG_FTR_FIXUP_SELFTEST is not set
1508# CONFIG_XMON is not set
1415# CONFIG_IRQSTACKS is not set 1509# CONFIG_IRQSTACKS is not set
1416# CONFIG_BDI_SWITCH is not set 1510# CONFIG_BDI_SWITCH is not set
1511# CONFIG_BOOTX_TEXT is not set
1417# CONFIG_PPC_EARLY_DEBUG is not set 1512# CONFIG_PPC_EARLY_DEBUG is not set
1418 1513
1419# 1514#
@@ -1467,6 +1562,10 @@ CONFIG_CRYPTO_PCBC=m
1467# CONFIG_CRYPTO_MD4 is not set 1562# CONFIG_CRYPTO_MD4 is not set
1468CONFIG_CRYPTO_MD5=y 1563CONFIG_CRYPTO_MD5=y
1469# CONFIG_CRYPTO_MICHAEL_MIC is not set 1564# CONFIG_CRYPTO_MICHAEL_MIC is not set
1565# CONFIG_CRYPTO_RMD128 is not set
1566# CONFIG_CRYPTO_RMD160 is not set
1567# CONFIG_CRYPTO_RMD256 is not set
1568# CONFIG_CRYPTO_RMD320 is not set
1470# CONFIG_CRYPTO_SHA1 is not set 1569# CONFIG_CRYPTO_SHA1 is not set
1471# CONFIG_CRYPTO_SHA256 is not set 1570# CONFIG_CRYPTO_SHA256 is not set
1472# CONFIG_CRYPTO_SHA512 is not set 1571# CONFIG_CRYPTO_SHA512 is not set
@@ -1499,5 +1598,6 @@ CONFIG_CRYPTO_DES=y
1499# CONFIG_CRYPTO_LZO is not set 1598# CONFIG_CRYPTO_LZO is not set
1500CONFIG_CRYPTO_HW=y 1599CONFIG_CRYPTO_HW=y
1501# CONFIG_CRYPTO_DEV_HIFN_795X is not set 1600# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1601# CONFIG_CRYPTO_DEV_TALITOS is not set
1502# CONFIG_PPC_CLOCK is not set 1602# CONFIG_PPC_CLOCK is not set
1503# CONFIG_VIRTUALIZATION is not set 1603# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/configs/83xx/mpc832x_mds_defconfig b/arch/powerpc/configs/83xx/mpc832x_mds_defconfig
index 1eca26f3659a..bdf50c8a17e6 100644
--- a/arch/powerpc/configs/83xx/mpc832x_mds_defconfig
+++ b/arch/powerpc/configs/83xx/mpc832x_mds_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc5 3# Linux kernel version: 2.6.27-rc4
4# Mon Jun 9 08:52:22 2008 4# Thu Aug 21 00:52:18 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -16,6 +16,7 @@ CONFIG_6xx=y
16# CONFIG_E200 is not set 16# CONFIG_E200 is not set
17CONFIG_PPC_FPU=y 17CONFIG_PPC_FPU=y
18# CONFIG_FSL_EMB_PERFMON is not set 18# CONFIG_FSL_EMB_PERFMON is not set
19# CONFIG_ALTIVEC is not set
19CONFIG_PPC_STD_MMU=y 20CONFIG_PPC_STD_MMU=y
20CONFIG_PPC_STD_MMU_32=y 21CONFIG_PPC_STD_MMU_32=y
21# CONFIG_PPC_MM_SLICES is not set 22# CONFIG_PPC_MM_SLICES is not set
@@ -32,6 +33,7 @@ CONFIG_GENERIC_HARDIRQS=y
32# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set 33# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
33CONFIG_IRQ_PER_CPU=y 34CONFIG_IRQ_PER_CPU=y
34CONFIG_STACKTRACE_SUPPORT=y 35CONFIG_STACKTRACE_SUPPORT=y
36CONFIG_HAVE_LATENCYTOP_SUPPORT=y
35CONFIG_LOCKDEP_SUPPORT=y 37CONFIG_LOCKDEP_SUPPORT=y
36CONFIG_RWSEM_XCHGADD_ALGORITHM=y 38CONFIG_RWSEM_XCHGADD_ALGORITHM=y
37CONFIG_ARCH_HAS_ILOG2_U32=y 39CONFIG_ARCH_HAS_ILOG2_U32=y
@@ -51,6 +53,9 @@ CONFIG_PPC_UDBG_16550=y
51CONFIG_AUDIT_ARCH=y 53CONFIG_AUDIT_ARCH=y
52CONFIG_GENERIC_BUG=y 54CONFIG_GENERIC_BUG=y
53CONFIG_DEFAULT_UIMAGE=y 55CONFIG_DEFAULT_UIMAGE=y
56CONFIG_HIBERNATE_32=y
57CONFIG_ARCH_HIBERNATION_POSSIBLE=y
58CONFIG_ARCH_SUSPEND_POSSIBLE=y
54# CONFIG_PPC_DCR_NATIVE is not set 59# CONFIG_PPC_DCR_NATIVE is not set
55# CONFIG_PPC_DCR_MMIO is not set 60# CONFIG_PPC_DCR_MMIO is not set
56CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 61CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
@@ -88,12 +93,12 @@ CONFIG_INITRAMFS_SOURCE=""
88CONFIG_SYSCTL=y 93CONFIG_SYSCTL=y
89CONFIG_EMBEDDED=y 94CONFIG_EMBEDDED=y
90CONFIG_SYSCTL_SYSCALL=y 95CONFIG_SYSCTL_SYSCALL=y
91CONFIG_SYSCTL_SYSCALL_CHECK=y
92# CONFIG_KALLSYMS is not set 96# CONFIG_KALLSYMS is not set
93CONFIG_HOTPLUG=y 97CONFIG_HOTPLUG=y
94CONFIG_PRINTK=y 98CONFIG_PRINTK=y
95CONFIG_BUG=y 99CONFIG_BUG=y
96CONFIG_ELF_CORE=y 100CONFIG_ELF_CORE=y
101CONFIG_PCSPKR_PLATFORM=y
97CONFIG_COMPAT_BRK=y 102CONFIG_COMPAT_BRK=y
98CONFIG_BASE_FULL=y 103CONFIG_BASE_FULL=y
99CONFIG_FUTEX=y 104CONFIG_FUTEX=y
@@ -111,10 +116,16 @@ CONFIG_SLUB=y
111# CONFIG_PROFILING is not set 116# CONFIG_PROFILING is not set
112# CONFIG_MARKERS is not set 117# CONFIG_MARKERS is not set
113CONFIG_HAVE_OPROFILE=y 118CONFIG_HAVE_OPROFILE=y
119CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
120CONFIG_HAVE_IOREMAP_PROT=y
114CONFIG_HAVE_KPROBES=y 121CONFIG_HAVE_KPROBES=y
115CONFIG_HAVE_KRETPROBES=y 122CONFIG_HAVE_KRETPROBES=y
123CONFIG_HAVE_ARCH_TRACEHOOK=y
116# CONFIG_HAVE_DMA_ATTRS is not set 124# CONFIG_HAVE_DMA_ATTRS is not set
125# CONFIG_USE_GENERIC_SMP_HELPERS is not set
126# CONFIG_HAVE_CLK is not set
117CONFIG_PROC_PAGE_MONITOR=y 127CONFIG_PROC_PAGE_MONITOR=y
128# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
118CONFIG_SLABINFO=y 129CONFIG_SLABINFO=y
119CONFIG_RT_MUTEXES=y 130CONFIG_RT_MUTEXES=y
120# CONFIG_TINY_SHMEM is not set 131# CONFIG_TINY_SHMEM is not set
@@ -125,12 +136,13 @@ CONFIG_MODULE_UNLOAD=y
125# CONFIG_MODULE_FORCE_UNLOAD is not set 136# CONFIG_MODULE_FORCE_UNLOAD is not set
126# CONFIG_MODVERSIONS is not set 137# CONFIG_MODVERSIONS is not set
127# CONFIG_MODULE_SRCVERSION_ALL is not set 138# CONFIG_MODULE_SRCVERSION_ALL is not set
128# CONFIG_KMOD is not set 139CONFIG_KMOD=y
129CONFIG_BLOCK=y 140CONFIG_BLOCK=y
130# CONFIG_LBD is not set 141# CONFIG_LBD is not set
131# CONFIG_BLK_DEV_IO_TRACE is not set 142# CONFIG_BLK_DEV_IO_TRACE is not set
132# CONFIG_LSF is not set 143# CONFIG_LSF is not set
133# CONFIG_BLK_DEV_BSG is not set 144# CONFIG_BLK_DEV_BSG is not set
145# CONFIG_BLK_DEV_INTEGRITY is not set
134 146
135# 147#
136# IO Schedulers 148# IO Schedulers
@@ -149,37 +161,49 @@ CONFIG_CLASSIC_RCU=y
149# 161#
150# Platform support 162# Platform support
151# 163#
152# CONFIG_PPC_MULTIPLATFORM is not set 164CONFIG_PPC_MULTIPLATFORM=y
153# CONFIG_PPC_82xx is not set 165CONFIG_CLASSIC32=y
154CONFIG_PPC_83xx=y 166CONFIG_PPC_CHRP=y
155# CONFIG_PPC_86xx is not set 167# CONFIG_MPC5121_ADS is not set
156# CONFIG_PPC_MPC512x is not set 168# CONFIG_MPC5121_GENERIC is not set
157# CONFIG_PPC_MPC5121 is not set 169# CONFIG_PPC_MPC52xx is not set
170CONFIG_PPC_PMAC=y
158# CONFIG_PPC_CELL is not set 171# CONFIG_PPC_CELL is not set
159# CONFIG_PPC_CELL_NATIVE is not set 172# CONFIG_PPC_CELL_NATIVE is not set
173# CONFIG_PPC_82xx is not set
160# CONFIG_PQ2ADS is not set 174# CONFIG_PQ2ADS is not set
161CONFIG_MPC83xx=y 175CONFIG_PPC_83xx=y
162# CONFIG_MPC831x_RDB is not set 176# CONFIG_MPC831x_RDB is not set
163CONFIG_MPC832x_MDS=y 177CONFIG_MPC832x_MDS=y
164# CONFIG_MPC832x_RDB is not set 178# CONFIG_MPC832x_RDB is not set
165# CONFIG_MPC834x_MDS is not set 179# CONFIG_MPC834x_MDS is not set
166# CONFIG_MPC834x_ITX is not set 180# CONFIG_MPC834x_ITX is not set
167# CONFIG_MPC836x_MDS is not set 181# CONFIG_MPC836x_MDS is not set
182# CONFIG_MPC836x_RDK is not set
168# CONFIG_MPC837x_MDS is not set 183# CONFIG_MPC837x_MDS is not set
169# CONFIG_MPC837x_RDB is not set 184# CONFIG_MPC837x_RDB is not set
170# CONFIG_SBC834x is not set 185# CONFIG_SBC834x is not set
186# CONFIG_ASP834x is not set
171CONFIG_PPC_MPC832x=y 187CONFIG_PPC_MPC832x=y
188# CONFIG_PPC_86xx is not set
189# CONFIG_EMBEDDED6xx is not set
190CONFIG_PPC_NATIVE=y
191# CONFIG_UDBG_RTAS_CONSOLE is not set
172CONFIG_IPIC=y 192CONFIG_IPIC=y
173# CONFIG_MPIC is not set 193CONFIG_MPIC=y
174# CONFIG_MPIC_WEIRD is not set 194# CONFIG_MPIC_WEIRD is not set
175# CONFIG_PPC_I8259 is not set 195CONFIG_PPC_I8259=y
176# CONFIG_PPC_RTAS is not set 196CONFIG_PPC_RTAS=y
197# CONFIG_RTAS_ERROR_LOGGING is not set
198CONFIG_RTAS_PROC=y
177# CONFIG_MMIO_NVRAM is not set 199# CONFIG_MMIO_NVRAM is not set
178# CONFIG_PPC_MPC106 is not set 200CONFIG_PPC_MPC106=y
179# CONFIG_PPC_970_NAP is not set 201# CONFIG_PPC_970_NAP is not set
180# CONFIG_PPC_INDIRECT_IO is not set 202# CONFIG_PPC_INDIRECT_IO is not set
181# CONFIG_GENERIC_IOMAP is not set 203# CONFIG_GENERIC_IOMAP is not set
182# CONFIG_CPU_FREQ is not set 204# CONFIG_CPU_FREQ is not set
205# CONFIG_PPC601_SYNC_FIX is not set
206# CONFIG_TAU is not set
183CONFIG_QUICC_ENGINE=y 207CONFIG_QUICC_ENGINE=y
184# CONFIG_FSL_ULI1575 is not set 208# CONFIG_FSL_ULI1575 is not set
185 209
@@ -196,7 +220,7 @@ CONFIG_HZ_250=y
196# CONFIG_HZ_300 is not set 220# CONFIG_HZ_300 is not set
197# CONFIG_HZ_1000 is not set 221# CONFIG_HZ_1000 is not set
198CONFIG_HZ=250 222CONFIG_HZ=250
199# CONFIG_SCHED_HRTICK is not set 223CONFIG_SCHED_HRTICK=y
200CONFIG_PREEMPT_NONE=y 224CONFIG_PREEMPT_NONE=y
201# CONFIG_PREEMPT_VOLUNTARY is not set 225# CONFIG_PREEMPT_VOLUNTARY is not set
202# CONFIG_PREEMPT is not set 226# CONFIG_PREEMPT is not set
@@ -207,6 +231,7 @@ CONFIG_MATH_EMULATION=y
207CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y 231CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
208CONFIG_ARCH_HAS_WALK_MEMORY=y 232CONFIG_ARCH_HAS_WALK_MEMORY=y
209CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y 233CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
234# CONFIG_KEXEC is not set
210CONFIG_ARCH_FLATMEM_ENABLE=y 235CONFIG_ARCH_FLATMEM_ENABLE=y
211CONFIG_ARCH_POPULATES_NODE_MAP=y 236CONFIG_ARCH_POPULATES_NODE_MAP=y
212CONFIG_SELECT_MEMORY_MODEL=y 237CONFIG_SELECT_MEMORY_MODEL=y
@@ -219,6 +244,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
219# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set 244# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
220CONFIG_PAGEFLAGS_EXTENDED=y 245CONFIG_PAGEFLAGS_EXTENDED=y
221CONFIG_SPLIT_PTLOCK_CPUS=4 246CONFIG_SPLIT_PTLOCK_CPUS=4
247CONFIG_MIGRATION=y
222# CONFIG_RESOURCES_64BIT is not set 248# CONFIG_RESOURCES_64BIT is not set
223CONFIG_ZONE_DMA_FLAG=1 249CONFIG_ZONE_DMA_FLAG=1
224CONFIG_BOUNCE=y 250CONFIG_BOUNCE=y
@@ -226,6 +252,7 @@ CONFIG_VIRT_TO_BUS=y
226CONFIG_FORCE_MAX_ZONEORDER=11 252CONFIG_FORCE_MAX_ZONEORDER=11
227CONFIG_PROC_DEVICETREE=y 253CONFIG_PROC_DEVICETREE=y
228# CONFIG_CMDLINE_BOOL is not set 254# CONFIG_CMDLINE_BOOL is not set
255CONFIG_EXTRA_TARGETS=""
229# CONFIG_PM is not set 256# CONFIG_PM is not set
230CONFIG_SECCOMP=y 257CONFIG_SECCOMP=y
231CONFIG_ISA_DMA_API=y 258CONFIG_ISA_DMA_API=y
@@ -233,10 +260,13 @@ CONFIG_ISA_DMA_API=y
233# 260#
234# Bus options 261# Bus options
235# 262#
263# CONFIG_ISA is not set
236CONFIG_ZONE_DMA=y 264CONFIG_ZONE_DMA=y
237CONFIG_GENERIC_ISA_DMA=y 265CONFIG_GENERIC_ISA_DMA=y
238CONFIG_PPC_INDIRECT_PCI=y 266CONFIG_PPC_INDIRECT_PCI=y
239CONFIG_FSL_SOC=y 267CONFIG_FSL_SOC=y
268CONFIG_FSL_PCI=y
269CONFIG_PPC_PCI_CHOICE=y
240CONFIG_PCI=y 270CONFIG_PCI=y
241CONFIG_PCI_DOMAINS=y 271CONFIG_PCI_DOMAINS=y
242CONFIG_PCI_SYSCALL=y 272CONFIG_PCI_SYSCALL=y
@@ -261,10 +291,6 @@ CONFIG_PAGE_OFFSET=0xc0000000
261CONFIG_KERNEL_START=0xc0000000 291CONFIG_KERNEL_START=0xc0000000
262CONFIG_PHYSICAL_START=0x00000000 292CONFIG_PHYSICAL_START=0x00000000
263CONFIG_TASK_SIZE=0xc0000000 293CONFIG_TASK_SIZE=0xc0000000
264
265#
266# Networking
267#
268CONFIG_NET=y 294CONFIG_NET=y
269 295
270# 296#
@@ -365,6 +391,7 @@ CONFIG_OF_I2C=y
365# CONFIG_PARPORT is not set 391# CONFIG_PARPORT is not set
366CONFIG_BLK_DEV=y 392CONFIG_BLK_DEV=y
367# CONFIG_BLK_DEV_FD is not set 393# CONFIG_BLK_DEV_FD is not set
394# CONFIG_MAC_FLOPPY is not set
368# CONFIG_BLK_CPQ_DA is not set 395# CONFIG_BLK_CPQ_DA is not set
369# CONFIG_BLK_CPQ_CISS_DA is not set 396# CONFIG_BLK_CPQ_CISS_DA is not set
370# CONFIG_BLK_DEV_DAC960 is not set 397# CONFIG_BLK_DEV_DAC960 is not set
@@ -380,12 +407,14 @@ CONFIG_BLK_DEV_RAM_SIZE=32768
380# CONFIG_BLK_DEV_XIP is not set 407# CONFIG_BLK_DEV_XIP is not set
381# CONFIG_CDROM_PKTCDVD is not set 408# CONFIG_CDROM_PKTCDVD is not set
382# CONFIG_ATA_OVER_ETH is not set 409# CONFIG_ATA_OVER_ETH is not set
410# CONFIG_BLK_DEV_HD is not set
383CONFIG_MISC_DEVICES=y 411CONFIG_MISC_DEVICES=y
384# CONFIG_PHANTOM is not set 412# CONFIG_PHANTOM is not set
385# CONFIG_EEPROM_93CX6 is not set 413# CONFIG_EEPROM_93CX6 is not set
386# CONFIG_SGI_IOC4 is not set 414# CONFIG_SGI_IOC4 is not set
387# CONFIG_TIFM_CORE is not set 415# CONFIG_TIFM_CORE is not set
388# CONFIG_ENCLOSURE_SERVICES is not set 416# CONFIG_ENCLOSURE_SERVICES is not set
417# CONFIG_HP_ILO is not set
389CONFIG_HAVE_IDE=y 418CONFIG_HAVE_IDE=y
390# CONFIG_IDE is not set 419# CONFIG_IDE is not set
391 420
@@ -462,7 +491,10 @@ CONFIG_SCSI_LOWLEVEL=y
462# CONFIG_SCSI_DC390T is not set 491# CONFIG_SCSI_DC390T is not set
463# CONFIG_SCSI_NSP32 is not set 492# CONFIG_SCSI_NSP32 is not set
464# CONFIG_SCSI_DEBUG is not set 493# CONFIG_SCSI_DEBUG is not set
494# CONFIG_SCSI_MESH is not set
495# CONFIG_SCSI_MAC53C94 is not set
465# CONFIG_SCSI_SRP is not set 496# CONFIG_SCSI_SRP is not set
497# CONFIG_SCSI_DH is not set
466# CONFIG_ATA is not set 498# CONFIG_ATA is not set
467# CONFIG_MD is not set 499# CONFIG_MD is not set
468# CONFIG_FUSION is not set 500# CONFIG_FUSION is not set
@@ -470,12 +502,15 @@ CONFIG_SCSI_LOWLEVEL=y
470# 502#
471# IEEE 1394 (FireWire) support 503# IEEE 1394 (FireWire) support
472# 504#
505
506#
507# Enable only one of the two stacks, unless you know what you are doing
508#
473# CONFIG_FIREWIRE is not set 509# CONFIG_FIREWIRE is not set
474# CONFIG_IEEE1394 is not set 510# CONFIG_IEEE1394 is not set
475# CONFIG_I2O is not set 511# CONFIG_I2O is not set
476# CONFIG_MACINTOSH_DRIVERS is not set 512# CONFIG_MACINTOSH_DRIVERS is not set
477CONFIG_NETDEVICES=y 513CONFIG_NETDEVICES=y
478# CONFIG_NETDEVICES_MULTIQUEUE is not set
479# CONFIG_DUMMY is not set 514# CONFIG_DUMMY is not set
480# CONFIG_BONDING is not set 515# CONFIG_BONDING is not set
481# CONFIG_MACVLAN is not set 516# CONFIG_MACVLAN is not set
@@ -502,6 +537,8 @@ CONFIG_DAVICOM_PHY=y
502# CONFIG_MDIO_BITBANG is not set 537# CONFIG_MDIO_BITBANG is not set
503CONFIG_NET_ETHERNET=y 538CONFIG_NET_ETHERNET=y
504CONFIG_MII=y 539CONFIG_MII=y
540# CONFIG_MACE is not set
541# CONFIG_BMAC is not set
505# CONFIG_HAPPYMEAL is not set 542# CONFIG_HAPPYMEAL is not set
506# CONFIG_SUNGEM is not set 543# CONFIG_SUNGEM is not set
507# CONFIG_CASSINI is not set 544# CONFIG_CASSINI is not set
@@ -519,7 +556,6 @@ CONFIG_NETDEV_1000=y
519# CONFIG_DL2K is not set 556# CONFIG_DL2K is not set
520# CONFIG_E1000 is not set 557# CONFIG_E1000 is not set
521# CONFIG_E1000E is not set 558# CONFIG_E1000E is not set
522# CONFIG_E1000E_ENABLED is not set
523# CONFIG_IP1000 is not set 559# CONFIG_IP1000 is not set
524# CONFIG_IGB is not set 560# CONFIG_IGB is not set
525# CONFIG_NS83820 is not set 561# CONFIG_NS83820 is not set
@@ -534,12 +570,13 @@ CONFIG_NETDEV_1000=y
534# CONFIG_BNX2 is not set 570# CONFIG_BNX2 is not set
535# CONFIG_GIANFAR is not set 571# CONFIG_GIANFAR is not set
536CONFIG_UCC_GETH=y 572CONFIG_UCC_GETH=y
537# CONFIG_UGETH_NAPI is not set
538# CONFIG_UGETH_MAGIC_PACKET is not set 573# CONFIG_UGETH_MAGIC_PACKET is not set
539# CONFIG_UGETH_FILTERING is not set 574# CONFIG_UGETH_FILTERING is not set
540# CONFIG_UGETH_TX_ON_DEMAND is not set 575# CONFIG_UGETH_TX_ON_DEMAND is not set
576# CONFIG_MV643XX_ETH is not set
541# CONFIG_QLA3XXX is not set 577# CONFIG_QLA3XXX is not set
542# CONFIG_ATL1 is not set 578# CONFIG_ATL1 is not set
579# CONFIG_ATL1E is not set
543CONFIG_NETDEV_10000=y 580CONFIG_NETDEV_10000=y
544# CONFIG_CHELSIO_T1 is not set 581# CONFIG_CHELSIO_T1 is not set
545# CONFIG_CHELSIO_T3 is not set 582# CONFIG_CHELSIO_T3 is not set
@@ -628,12 +665,15 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=4
628# CONFIG_SERIAL_UARTLITE is not set 665# CONFIG_SERIAL_UARTLITE is not set
629CONFIG_SERIAL_CORE=y 666CONFIG_SERIAL_CORE=y
630CONFIG_SERIAL_CORE_CONSOLE=y 667CONFIG_SERIAL_CORE_CONSOLE=y
668# CONFIG_SERIAL_PMACZILOG is not set
631# CONFIG_SERIAL_JSM is not set 669# CONFIG_SERIAL_JSM is not set
632# CONFIG_SERIAL_OF_PLATFORM is not set 670# CONFIG_SERIAL_OF_PLATFORM is not set
633# CONFIG_SERIAL_QE is not set 671# CONFIG_SERIAL_QE is not set
634CONFIG_UNIX98_PTYS=y 672CONFIG_UNIX98_PTYS=y
635CONFIG_LEGACY_PTYS=y 673CONFIG_LEGACY_PTYS=y
636CONFIG_LEGACY_PTY_COUNT=256 674CONFIG_LEGACY_PTY_COUNT=256
675# CONFIG_BRIQ_PANEL is not set
676# CONFIG_HVC_RTAS is not set
637# CONFIG_IPMI_HANDLER is not set 677# CONFIG_IPMI_HANDLER is not set
638CONFIG_HW_RANDOM=y 678CONFIG_HW_RANDOM=y
639# CONFIG_NVRAM is not set 679# CONFIG_NVRAM is not set
@@ -645,42 +685,69 @@ CONFIG_DEVPORT=y
645CONFIG_I2C=y 685CONFIG_I2C=y
646CONFIG_I2C_BOARDINFO=y 686CONFIG_I2C_BOARDINFO=y
647CONFIG_I2C_CHARDEV=y 687CONFIG_I2C_CHARDEV=y
688CONFIG_I2C_HELPER_AUTO=y
648 689
649# 690#
650# I2C Hardware Bus support 691# I2C Hardware Bus support
651# 692#
693
694#
695# PC SMBus host controller drivers
696#
652# CONFIG_I2C_ALI1535 is not set 697# CONFIG_I2C_ALI1535 is not set
653# CONFIG_I2C_ALI1563 is not set 698# CONFIG_I2C_ALI1563 is not set
654# CONFIG_I2C_ALI15X3 is not set 699# CONFIG_I2C_ALI15X3 is not set
655# CONFIG_I2C_AMD756 is not set 700# CONFIG_I2C_AMD756 is not set
656# CONFIG_I2C_AMD8111 is not set 701# CONFIG_I2C_AMD8111 is not set
657# CONFIG_I2C_I801 is not set 702# CONFIG_I2C_I801 is not set
658# CONFIG_I2C_I810 is not set 703# CONFIG_I2C_ISCH is not set
659# CONFIG_I2C_PIIX4 is not set 704# CONFIG_I2C_PIIX4 is not set
660CONFIG_I2C_MPC=y
661# CONFIG_I2C_NFORCE2 is not set 705# CONFIG_I2C_NFORCE2 is not set
662# CONFIG_I2C_OCORES is not set
663# CONFIG_I2C_PARPORT_LIGHT is not set
664# CONFIG_I2C_PROSAVAGE is not set
665# CONFIG_I2C_SAVAGE4 is not set
666# CONFIG_I2C_SIMTEC is not set
667# CONFIG_I2C_SIS5595 is not set 706# CONFIG_I2C_SIS5595 is not set
668# CONFIG_I2C_SIS630 is not set 707# CONFIG_I2C_SIS630 is not set
669# CONFIG_I2C_SIS96X is not set 708# CONFIG_I2C_SIS96X is not set
670# CONFIG_I2C_TAOS_EVM is not set
671# CONFIG_I2C_STUB is not set
672# CONFIG_I2C_VIA is not set 709# CONFIG_I2C_VIA is not set
673# CONFIG_I2C_VIAPRO is not set 710# CONFIG_I2C_VIAPRO is not set
711
712#
713# Mac SMBus host controller drivers
714#
715# CONFIG_I2C_HYDRA is not set
716CONFIG_I2C_POWERMAC=y
717
718#
719# I2C system bus drivers (mostly embedded / system-on-chip)
720#
721CONFIG_I2C_MPC=y
722# CONFIG_I2C_OCORES is not set
723# CONFIG_I2C_SIMTEC is not set
724
725#
726# External I2C/SMBus adapter drivers
727#
728# CONFIG_I2C_PARPORT_LIGHT is not set
729# CONFIG_I2C_TAOS_EVM is not set
730
731#
732# Graphics adapter I2C/DDC channel drivers
733#
674# CONFIG_I2C_VOODOO3 is not set 734# CONFIG_I2C_VOODOO3 is not set
735
736#
737# Other I2C/SMBus bus drivers
738#
675# CONFIG_I2C_PCA_PLATFORM is not set 739# CONFIG_I2C_PCA_PLATFORM is not set
740# CONFIG_I2C_STUB is not set
676 741
677# 742#
678# Miscellaneous I2C Chip support 743# Miscellaneous I2C Chip support
679# 744#
680# CONFIG_DS1682 is not set 745# CONFIG_DS1682 is not set
746# CONFIG_AT24 is not set
681# CONFIG_SENSORS_EEPROM is not set 747# CONFIG_SENSORS_EEPROM is not set
682# CONFIG_SENSORS_PCF8574 is not set 748# CONFIG_SENSORS_PCF8574 is not set
683# CONFIG_PCF8575 is not set 749# CONFIG_PCF8575 is not set
750# CONFIG_SENSORS_PCA9539 is not set
684# CONFIG_SENSORS_PCF8591 is not set 751# CONFIG_SENSORS_PCF8591 is not set
685# CONFIG_SENSORS_MAX6875 is not set 752# CONFIG_SENSORS_MAX6875 is not set
686# CONFIG_SENSORS_TSL2550 is not set 753# CONFIG_SENSORS_TSL2550 is not set
@@ -689,10 +756,13 @@ CONFIG_I2C_MPC=y
689# CONFIG_I2C_DEBUG_BUS is not set 756# CONFIG_I2C_DEBUG_BUS is not set
690# CONFIG_I2C_DEBUG_CHIP is not set 757# CONFIG_I2C_DEBUG_CHIP is not set
691# CONFIG_SPI is not set 758# CONFIG_SPI is not set
759CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
760# CONFIG_GPIOLIB is not set
692# CONFIG_W1 is not set 761# CONFIG_W1 is not set
693# CONFIG_POWER_SUPPLY is not set 762# CONFIG_POWER_SUPPLY is not set
694CONFIG_HWMON=y 763CONFIG_HWMON=y
695# CONFIG_HWMON_VID is not set 764# CONFIG_HWMON_VID is not set
765# CONFIG_SENSORS_AD7414 is not set
696# CONFIG_SENSORS_AD7418 is not set 766# CONFIG_SENSORS_AD7418 is not set
697# CONFIG_SENSORS_ADM1021 is not set 767# CONFIG_SENSORS_ADM1021 is not set
698# CONFIG_SENSORS_ADM1025 is not set 768# CONFIG_SENSORS_ADM1025 is not set
@@ -702,6 +772,7 @@ CONFIG_HWMON=y
702# CONFIG_SENSORS_ADM9240 is not set 772# CONFIG_SENSORS_ADM9240 is not set
703# CONFIG_SENSORS_ADT7470 is not set 773# CONFIG_SENSORS_ADT7470 is not set
704# CONFIG_SENSORS_ADT7473 is not set 774# CONFIG_SENSORS_ADT7473 is not set
775# CONFIG_SENSORS_AMS is not set
705# CONFIG_SENSORS_ATXP1 is not set 776# CONFIG_SENSORS_ATXP1 is not set
706# CONFIG_SENSORS_DS1621 is not set 777# CONFIG_SENSORS_DS1621 is not set
707# CONFIG_SENSORS_I5K_AMB is not set 778# CONFIG_SENSORS_I5K_AMB is not set
@@ -746,6 +817,7 @@ CONFIG_HWMON=y
746# CONFIG_SENSORS_W83627EHF is not set 817# CONFIG_SENSORS_W83627EHF is not set
747# CONFIG_HWMON_DEBUG_CHIP is not set 818# CONFIG_HWMON_DEBUG_CHIP is not set
748# CONFIG_THERMAL is not set 819# CONFIG_THERMAL is not set
820# CONFIG_THERMAL_HWMON is not set
749CONFIG_WATCHDOG=y 821CONFIG_WATCHDOG=y
750# CONFIG_WATCHDOG_NOWAYOUT is not set 822# CONFIG_WATCHDOG_NOWAYOUT is not set
751 823
@@ -753,7 +825,9 @@ CONFIG_WATCHDOG=y
753# Watchdog Device Drivers 825# Watchdog Device Drivers
754# 826#
755# CONFIG_SOFT_WATCHDOG is not set 827# CONFIG_SOFT_WATCHDOG is not set
756CONFIG_83xx_WDT=y 828# CONFIG_ALIM7101_WDT is not set
829# CONFIG_8xxx_WDT is not set
830# CONFIG_WATCHDOG_RTAS is not set
757 831
758# 832#
759# PCI-based Watchdog Cards 833# PCI-based Watchdog Cards
@@ -770,8 +844,10 @@ CONFIG_SSB_POSSIBLE=y
770# 844#
771# Multifunction device drivers 845# Multifunction device drivers
772# 846#
847# CONFIG_MFD_CORE is not set
773# CONFIG_MFD_SM501 is not set 848# CONFIG_MFD_SM501 is not set
774# CONFIG_HTC_PASIC3 is not set 849# CONFIG_HTC_PASIC3 is not set
850# CONFIG_MFD_TMIO is not set
775 851
776# 852#
777# Multimedia devices 853# Multimedia devices
@@ -803,10 +879,6 @@ CONFIG_VIDEO_OUTPUT_CONTROL=m
803# Display device support 879# Display device support
804# 880#
805# CONFIG_DISPLAY_SUPPORT is not set 881# CONFIG_DISPLAY_SUPPORT is not set
806
807#
808# Sound
809#
810# CONFIG_SOUND is not set 882# CONFIG_SOUND is not set
811CONFIG_HID_SUPPORT=y 883CONFIG_HID_SUPPORT=y
812CONFIG_HID=y 884CONFIG_HID=y
@@ -821,6 +893,10 @@ CONFIG_USB_ARCH_HAS_EHCI=y
821# CONFIG_USB_OTG_BLACKLIST_HUB is not set 893# CONFIG_USB_OTG_BLACKLIST_HUB is not set
822 894
823# 895#
896# Enable Host or Gadget support to see Inventra options
897#
898
899#
824# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 900# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
825# 901#
826# CONFIG_USB_GADGET is not set 902# CONFIG_USB_GADGET is not set
@@ -859,6 +935,7 @@ CONFIG_RTC_DRV_DS1374=y
859# CONFIG_RTC_DRV_PCF8583 is not set 935# CONFIG_RTC_DRV_PCF8583 is not set
860# CONFIG_RTC_DRV_M41T80 is not set 936# CONFIG_RTC_DRV_M41T80 is not set
861# CONFIG_RTC_DRV_S35390A is not set 937# CONFIG_RTC_DRV_S35390A is not set
938# CONFIG_RTC_DRV_FM3130 is not set
862 939
863# 940#
864# SPI RTC drivers 941# SPI RTC drivers
@@ -947,6 +1024,7 @@ CONFIG_TMPFS=y
947# CONFIG_CRAMFS is not set 1024# CONFIG_CRAMFS is not set
948# CONFIG_VXFS_FS is not set 1025# CONFIG_VXFS_FS is not set
949# CONFIG_MINIX_FS is not set 1026# CONFIG_MINIX_FS is not set
1027# CONFIG_OMFS_FS is not set
950# CONFIG_HPFS_FS is not set 1028# CONFIG_HPFS_FS is not set
951# CONFIG_QNX4FS_FS is not set 1029# CONFIG_QNX4FS_FS is not set
952# CONFIG_ROMFS_FS is not set 1030# CONFIG_ROMFS_FS is not set
@@ -957,14 +1035,13 @@ CONFIG_NFS_FS=y
957CONFIG_NFS_V3=y 1035CONFIG_NFS_V3=y
958# CONFIG_NFS_V3_ACL is not set 1036# CONFIG_NFS_V3_ACL is not set
959CONFIG_NFS_V4=y 1037CONFIG_NFS_V4=y
960# CONFIG_NFSD is not set
961CONFIG_ROOT_NFS=y 1038CONFIG_ROOT_NFS=y
1039# CONFIG_NFSD is not set
962CONFIG_LOCKD=y 1040CONFIG_LOCKD=y
963CONFIG_LOCKD_V4=y 1041CONFIG_LOCKD_V4=y
964CONFIG_NFS_COMMON=y 1042CONFIG_NFS_COMMON=y
965CONFIG_SUNRPC=y 1043CONFIG_SUNRPC=y
966CONFIG_SUNRPC_GSS=y 1044CONFIG_SUNRPC_GSS=y
967# CONFIG_SUNRPC_BIND34 is not set
968CONFIG_RPCSEC_GSS_KRB5=y 1045CONFIG_RPCSEC_GSS_KRB5=y
969# CONFIG_RPCSEC_GSS_SPKM3 is not set 1046# CONFIG_RPCSEC_GSS_SPKM3 is not set
970# CONFIG_SMB_FS is not set 1047# CONFIG_SMB_FS is not set
@@ -994,6 +1071,7 @@ CONFIG_PARTITION_ADVANCED=y
994# CONFIG_DLM is not set 1071# CONFIG_DLM is not set
995CONFIG_UCC_FAST=y 1072CONFIG_UCC_FAST=y
996CONFIG_UCC=y 1073CONFIG_UCC=y
1074# CONFIG_QE_GPIO is not set
997 1075
998# 1076#
999# Library routines 1077# Library routines
@@ -1002,6 +1080,7 @@ CONFIG_BITREVERSE=y
1002# CONFIG_GENERIC_FIND_FIRST_BIT is not set 1080# CONFIG_GENERIC_FIND_FIRST_BIT is not set
1003# CONFIG_CRC_CCITT is not set 1081# CONFIG_CRC_CCITT is not set
1004# CONFIG_CRC16 is not set 1082# CONFIG_CRC16 is not set
1083# CONFIG_CRC_T10DIF is not set
1005# CONFIG_CRC_ITU_T is not set 1084# CONFIG_CRC_ITU_T is not set
1006CONFIG_CRC32=y 1085CONFIG_CRC32=y
1007# CONFIG_CRC7 is not set 1086# CONFIG_CRC7 is not set
@@ -1027,8 +1106,18 @@ CONFIG_FRAME_WARN=1024
1027# CONFIG_SLUB_DEBUG_ON is not set 1106# CONFIG_SLUB_DEBUG_ON is not set
1028# CONFIG_SLUB_STATS is not set 1107# CONFIG_SLUB_STATS is not set
1029# CONFIG_DEBUG_BUGVERBOSE is not set 1108# CONFIG_DEBUG_BUGVERBOSE is not set
1109# CONFIG_DEBUG_MEMORY_INIT is not set
1110# CONFIG_LATENCYTOP is not set
1111CONFIG_SYSCTL_SYSCALL_CHECK=y
1112CONFIG_HAVE_FTRACE=y
1113CONFIG_HAVE_DYNAMIC_FTRACE=y
1114# CONFIG_FTRACE is not set
1115# CONFIG_SCHED_TRACER is not set
1116# CONFIG_CONTEXT_SWITCH_TRACER is not set
1030# CONFIG_SAMPLES is not set 1117# CONFIG_SAMPLES is not set
1118CONFIG_HAVE_ARCH_KGDB=y
1031# CONFIG_IRQSTACKS is not set 1119# CONFIG_IRQSTACKS is not set
1120# CONFIG_BOOTX_TEXT is not set
1032# CONFIG_PPC_EARLY_DEBUG is not set 1121# CONFIG_PPC_EARLY_DEBUG is not set
1033 1122
1034# 1123#
@@ -1082,6 +1171,10 @@ CONFIG_CRYPTO_PCBC=m
1082# CONFIG_CRYPTO_MD4 is not set 1171# CONFIG_CRYPTO_MD4 is not set
1083CONFIG_CRYPTO_MD5=y 1172CONFIG_CRYPTO_MD5=y
1084# CONFIG_CRYPTO_MICHAEL_MIC is not set 1173# CONFIG_CRYPTO_MICHAEL_MIC is not set
1174# CONFIG_CRYPTO_RMD128 is not set
1175# CONFIG_CRYPTO_RMD160 is not set
1176# CONFIG_CRYPTO_RMD256 is not set
1177# CONFIG_CRYPTO_RMD320 is not set
1085# CONFIG_CRYPTO_SHA1 is not set 1178# CONFIG_CRYPTO_SHA1 is not set
1086# CONFIG_CRYPTO_SHA256 is not set 1179# CONFIG_CRYPTO_SHA256 is not set
1087# CONFIG_CRYPTO_SHA512 is not set 1180# CONFIG_CRYPTO_SHA512 is not set
@@ -1114,6 +1207,7 @@ CONFIG_CRYPTO_DES=y
1114# CONFIG_CRYPTO_LZO is not set 1207# CONFIG_CRYPTO_LZO is not set
1115CONFIG_CRYPTO_HW=y 1208CONFIG_CRYPTO_HW=y
1116# CONFIG_CRYPTO_DEV_HIFN_795X is not set 1209# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1210# CONFIG_CRYPTO_DEV_TALITOS is not set
1117# CONFIG_PPC_CLOCK is not set 1211# CONFIG_PPC_CLOCK is not set
1118CONFIG_PPC_LIB_RHEAP=y 1212CONFIG_PPC_LIB_RHEAP=y
1119# CONFIG_VIRTUALIZATION is not set 1213# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/configs/83xx/mpc832x_rdb_defconfig b/arch/powerpc/configs/83xx/mpc832x_rdb_defconfig
index de95d327463c..4eef8c95480e 100644
--- a/arch/powerpc/configs/83xx/mpc832x_rdb_defconfig
+++ b/arch/powerpc/configs/83xx/mpc832x_rdb_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc5 3# Linux kernel version: 2.6.27-rc4
4# Mon Jun 9 08:52:24 2008 4# Thu Aug 21 00:52:19 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -16,6 +16,7 @@ CONFIG_6xx=y
16# CONFIG_E200 is not set 16# CONFIG_E200 is not set
17CONFIG_PPC_FPU=y 17CONFIG_PPC_FPU=y
18# CONFIG_FSL_EMB_PERFMON is not set 18# CONFIG_FSL_EMB_PERFMON is not set
19# CONFIG_ALTIVEC is not set
19CONFIG_PPC_STD_MMU=y 20CONFIG_PPC_STD_MMU=y
20CONFIG_PPC_STD_MMU_32=y 21CONFIG_PPC_STD_MMU_32=y
21# CONFIG_PPC_MM_SLICES is not set 22# CONFIG_PPC_MM_SLICES is not set
@@ -32,6 +33,7 @@ CONFIG_GENERIC_HARDIRQS=y
32# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set 33# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
33CONFIG_IRQ_PER_CPU=y 34CONFIG_IRQ_PER_CPU=y
34CONFIG_STACKTRACE_SUPPORT=y 35CONFIG_STACKTRACE_SUPPORT=y
36CONFIG_HAVE_LATENCYTOP_SUPPORT=y
35CONFIG_LOCKDEP_SUPPORT=y 37CONFIG_LOCKDEP_SUPPORT=y
36CONFIG_RWSEM_XCHGADD_ALGORITHM=y 38CONFIG_RWSEM_XCHGADD_ALGORITHM=y
37CONFIG_ARCH_HAS_ILOG2_U32=y 39CONFIG_ARCH_HAS_ILOG2_U32=y
@@ -51,6 +53,9 @@ CONFIG_PPC_UDBG_16550=y
51CONFIG_AUDIT_ARCH=y 53CONFIG_AUDIT_ARCH=y
52CONFIG_GENERIC_BUG=y 54CONFIG_GENERIC_BUG=y
53CONFIG_DEFAULT_UIMAGE=y 55CONFIG_DEFAULT_UIMAGE=y
56CONFIG_HIBERNATE_32=y
57CONFIG_ARCH_HIBERNATION_POSSIBLE=y
58CONFIG_ARCH_SUSPEND_POSSIBLE=y
54# CONFIG_PPC_DCR_NATIVE is not set 59# CONFIG_PPC_DCR_NATIVE is not set
55# CONFIG_PPC_DCR_MMIO is not set 60# CONFIG_PPC_DCR_MMIO is not set
56CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 61CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
@@ -88,12 +93,12 @@ CONFIG_INITRAMFS_SOURCE=""
88CONFIG_SYSCTL=y 93CONFIG_SYSCTL=y
89CONFIG_EMBEDDED=y 94CONFIG_EMBEDDED=y
90CONFIG_SYSCTL_SYSCALL=y 95CONFIG_SYSCTL_SYSCALL=y
91CONFIG_SYSCTL_SYSCALL_CHECK=y
92# CONFIG_KALLSYMS is not set 96# CONFIG_KALLSYMS is not set
93CONFIG_HOTPLUG=y 97CONFIG_HOTPLUG=y
94CONFIG_PRINTK=y 98CONFIG_PRINTK=y
95CONFIG_BUG=y 99CONFIG_BUG=y
96CONFIG_ELF_CORE=y 100CONFIG_ELF_CORE=y
101CONFIG_PCSPKR_PLATFORM=y
97CONFIG_COMPAT_BRK=y 102CONFIG_COMPAT_BRK=y
98CONFIG_BASE_FULL=y 103CONFIG_BASE_FULL=y
99CONFIG_FUTEX=y 104CONFIG_FUTEX=y
@@ -111,10 +116,16 @@ CONFIG_SLUB=y
111# CONFIG_PROFILING is not set 116# CONFIG_PROFILING is not set
112# CONFIG_MARKERS is not set 117# CONFIG_MARKERS is not set
113CONFIG_HAVE_OPROFILE=y 118CONFIG_HAVE_OPROFILE=y
119CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
120CONFIG_HAVE_IOREMAP_PROT=y
114CONFIG_HAVE_KPROBES=y 121CONFIG_HAVE_KPROBES=y
115CONFIG_HAVE_KRETPROBES=y 122CONFIG_HAVE_KRETPROBES=y
123CONFIG_HAVE_ARCH_TRACEHOOK=y
116# CONFIG_HAVE_DMA_ATTRS is not set 124# CONFIG_HAVE_DMA_ATTRS is not set
125# CONFIG_USE_GENERIC_SMP_HELPERS is not set
126# CONFIG_HAVE_CLK is not set
117CONFIG_PROC_PAGE_MONITOR=y 127CONFIG_PROC_PAGE_MONITOR=y
128# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
118CONFIG_SLABINFO=y 129CONFIG_SLABINFO=y
119CONFIG_RT_MUTEXES=y 130CONFIG_RT_MUTEXES=y
120# CONFIG_TINY_SHMEM is not set 131# CONFIG_TINY_SHMEM is not set
@@ -125,12 +136,13 @@ CONFIG_MODULE_UNLOAD=y
125# CONFIG_MODULE_FORCE_UNLOAD is not set 136# CONFIG_MODULE_FORCE_UNLOAD is not set
126# CONFIG_MODVERSIONS is not set 137# CONFIG_MODVERSIONS is not set
127# CONFIG_MODULE_SRCVERSION_ALL is not set 138# CONFIG_MODULE_SRCVERSION_ALL is not set
128# CONFIG_KMOD is not set 139CONFIG_KMOD=y
129CONFIG_BLOCK=y 140CONFIG_BLOCK=y
130# CONFIG_LBD is not set 141# CONFIG_LBD is not set
131# CONFIG_BLK_DEV_IO_TRACE is not set 142# CONFIG_BLK_DEV_IO_TRACE is not set
132# CONFIG_LSF is not set 143# CONFIG_LSF is not set
133# CONFIG_BLK_DEV_BSG is not set 144# CONFIG_BLK_DEV_BSG is not set
145# CONFIG_BLK_DEV_INTEGRITY is not set
134 146
135# 147#
136# IO Schedulers 148# IO Schedulers
@@ -149,37 +161,49 @@ CONFIG_CLASSIC_RCU=y
149# 161#
150# Platform support 162# Platform support
151# 163#
152# CONFIG_PPC_MULTIPLATFORM is not set 164CONFIG_PPC_MULTIPLATFORM=y
153# CONFIG_PPC_82xx is not set 165CONFIG_CLASSIC32=y
154CONFIG_PPC_83xx=y 166CONFIG_PPC_CHRP=y
155# CONFIG_PPC_86xx is not set 167# CONFIG_MPC5121_ADS is not set
156# CONFIG_PPC_MPC512x is not set 168# CONFIG_MPC5121_GENERIC is not set
157# CONFIG_PPC_MPC5121 is not set 169# CONFIG_PPC_MPC52xx is not set
170CONFIG_PPC_PMAC=y
158# CONFIG_PPC_CELL is not set 171# CONFIG_PPC_CELL is not set
159# CONFIG_PPC_CELL_NATIVE is not set 172# CONFIG_PPC_CELL_NATIVE is not set
173# CONFIG_PPC_82xx is not set
160# CONFIG_PQ2ADS is not set 174# CONFIG_PQ2ADS is not set
161CONFIG_MPC83xx=y 175CONFIG_PPC_83xx=y
162# CONFIG_MPC831x_RDB is not set 176# CONFIG_MPC831x_RDB is not set
163# CONFIG_MPC832x_MDS is not set 177# CONFIG_MPC832x_MDS is not set
164CONFIG_MPC832x_RDB=y 178CONFIG_MPC832x_RDB=y
165# CONFIG_MPC834x_MDS is not set 179# CONFIG_MPC834x_MDS is not set
166# CONFIG_MPC834x_ITX is not set 180# CONFIG_MPC834x_ITX is not set
167# CONFIG_MPC836x_MDS is not set 181# CONFIG_MPC836x_MDS is not set
182# CONFIG_MPC836x_RDK is not set
168# CONFIG_MPC837x_MDS is not set 183# CONFIG_MPC837x_MDS is not set
169# CONFIG_MPC837x_RDB is not set 184# CONFIG_MPC837x_RDB is not set
170# CONFIG_SBC834x is not set 185# CONFIG_SBC834x is not set
186# CONFIG_ASP834x is not set
171CONFIG_PPC_MPC832x=y 187CONFIG_PPC_MPC832x=y
188# CONFIG_PPC_86xx is not set
189# CONFIG_EMBEDDED6xx is not set
190CONFIG_PPC_NATIVE=y
191# CONFIG_UDBG_RTAS_CONSOLE is not set
172CONFIG_IPIC=y 192CONFIG_IPIC=y
173# CONFIG_MPIC is not set 193CONFIG_MPIC=y
174# CONFIG_MPIC_WEIRD is not set 194# CONFIG_MPIC_WEIRD is not set
175# CONFIG_PPC_I8259 is not set 195CONFIG_PPC_I8259=y
176# CONFIG_PPC_RTAS is not set 196CONFIG_PPC_RTAS=y
197# CONFIG_RTAS_ERROR_LOGGING is not set
198CONFIG_RTAS_PROC=y
177# CONFIG_MMIO_NVRAM is not set 199# CONFIG_MMIO_NVRAM is not set
178# CONFIG_PPC_MPC106 is not set 200CONFIG_PPC_MPC106=y
179# CONFIG_PPC_970_NAP is not set 201# CONFIG_PPC_970_NAP is not set
180# CONFIG_PPC_INDIRECT_IO is not set 202# CONFIG_PPC_INDIRECT_IO is not set
181# CONFIG_GENERIC_IOMAP is not set 203# CONFIG_GENERIC_IOMAP is not set
182# CONFIG_CPU_FREQ is not set 204# CONFIG_CPU_FREQ is not set
205# CONFIG_PPC601_SYNC_FIX is not set
206# CONFIG_TAU is not set
183CONFIG_QUICC_ENGINE=y 207CONFIG_QUICC_ENGINE=y
184# CONFIG_FSL_ULI1575 is not set 208# CONFIG_FSL_ULI1575 is not set
185 209
@@ -196,7 +220,7 @@ CONFIG_HZ_250=y
196# CONFIG_HZ_300 is not set 220# CONFIG_HZ_300 is not set
197# CONFIG_HZ_1000 is not set 221# CONFIG_HZ_1000 is not set
198CONFIG_HZ=250 222CONFIG_HZ=250
199# CONFIG_SCHED_HRTICK is not set 223CONFIG_SCHED_HRTICK=y
200CONFIG_PREEMPT_NONE=y 224CONFIG_PREEMPT_NONE=y
201# CONFIG_PREEMPT_VOLUNTARY is not set 225# CONFIG_PREEMPT_VOLUNTARY is not set
202# CONFIG_PREEMPT is not set 226# CONFIG_PREEMPT is not set
@@ -207,6 +231,7 @@ CONFIG_MATH_EMULATION=y
207CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y 231CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
208CONFIG_ARCH_HAS_WALK_MEMORY=y 232CONFIG_ARCH_HAS_WALK_MEMORY=y
209CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y 233CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
234# CONFIG_KEXEC is not set
210CONFIG_ARCH_FLATMEM_ENABLE=y 235CONFIG_ARCH_FLATMEM_ENABLE=y
211CONFIG_ARCH_POPULATES_NODE_MAP=y 236CONFIG_ARCH_POPULATES_NODE_MAP=y
212CONFIG_SELECT_MEMORY_MODEL=y 237CONFIG_SELECT_MEMORY_MODEL=y
@@ -219,6 +244,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
219# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set 244# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
220CONFIG_PAGEFLAGS_EXTENDED=y 245CONFIG_PAGEFLAGS_EXTENDED=y
221CONFIG_SPLIT_PTLOCK_CPUS=4 246CONFIG_SPLIT_PTLOCK_CPUS=4
247CONFIG_MIGRATION=y
222# CONFIG_RESOURCES_64BIT is not set 248# CONFIG_RESOURCES_64BIT is not set
223CONFIG_ZONE_DMA_FLAG=1 249CONFIG_ZONE_DMA_FLAG=1
224CONFIG_BOUNCE=y 250CONFIG_BOUNCE=y
@@ -226,6 +252,7 @@ CONFIG_VIRT_TO_BUS=y
226CONFIG_FORCE_MAX_ZONEORDER=11 252CONFIG_FORCE_MAX_ZONEORDER=11
227CONFIG_PROC_DEVICETREE=y 253CONFIG_PROC_DEVICETREE=y
228# CONFIG_CMDLINE_BOOL is not set 254# CONFIG_CMDLINE_BOOL is not set
255CONFIG_EXTRA_TARGETS=""
229# CONFIG_PM is not set 256# CONFIG_PM is not set
230CONFIG_SECCOMP=y 257CONFIG_SECCOMP=y
231CONFIG_ISA_DMA_API=y 258CONFIG_ISA_DMA_API=y
@@ -233,10 +260,13 @@ CONFIG_ISA_DMA_API=y
233# 260#
234# Bus options 261# Bus options
235# 262#
263# CONFIG_ISA is not set
236CONFIG_ZONE_DMA=y 264CONFIG_ZONE_DMA=y
237CONFIG_GENERIC_ISA_DMA=y 265CONFIG_GENERIC_ISA_DMA=y
238CONFIG_PPC_INDIRECT_PCI=y 266CONFIG_PPC_INDIRECT_PCI=y
239CONFIG_FSL_SOC=y 267CONFIG_FSL_SOC=y
268CONFIG_FSL_PCI=y
269CONFIG_PPC_PCI_CHOICE=y
240CONFIG_PCI=y 270CONFIG_PCI=y
241CONFIG_PCI_DOMAINS=y 271CONFIG_PCI_DOMAINS=y
242CONFIG_PCI_SYSCALL=y 272CONFIG_PCI_SYSCALL=y
@@ -261,10 +291,6 @@ CONFIG_PAGE_OFFSET=0xc0000000
261CONFIG_KERNEL_START=0xc0000000 291CONFIG_KERNEL_START=0xc0000000
262CONFIG_PHYSICAL_START=0x00000000 292CONFIG_PHYSICAL_START=0x00000000
263CONFIG_TASK_SIZE=0xc0000000 293CONFIG_TASK_SIZE=0xc0000000
264
265#
266# Networking
267#
268CONFIG_NET=y 294CONFIG_NET=y
269 295
270# 296#
@@ -362,9 +388,11 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
362# CONFIG_MTD is not set 388# CONFIG_MTD is not set
363CONFIG_OF_DEVICE=y 389CONFIG_OF_DEVICE=y
364CONFIG_OF_I2C=y 390CONFIG_OF_I2C=y
391CONFIG_OF_SPI=y
365# CONFIG_PARPORT is not set 392# CONFIG_PARPORT is not set
366CONFIG_BLK_DEV=y 393CONFIG_BLK_DEV=y
367# CONFIG_BLK_DEV_FD is not set 394# CONFIG_BLK_DEV_FD is not set
395# CONFIG_MAC_FLOPPY is not set
368# CONFIG_BLK_CPQ_DA is not set 396# CONFIG_BLK_CPQ_DA is not set
369# CONFIG_BLK_CPQ_CISS_DA is not set 397# CONFIG_BLK_CPQ_CISS_DA is not set
370# CONFIG_BLK_DEV_DAC960 is not set 398# CONFIG_BLK_DEV_DAC960 is not set
@@ -381,12 +409,14 @@ CONFIG_BLK_DEV_RAM_SIZE=32768
381# CONFIG_BLK_DEV_XIP is not set 409# CONFIG_BLK_DEV_XIP is not set
382# CONFIG_CDROM_PKTCDVD is not set 410# CONFIG_CDROM_PKTCDVD is not set
383# CONFIG_ATA_OVER_ETH is not set 411# CONFIG_ATA_OVER_ETH is not set
412# CONFIG_BLK_DEV_HD is not set
384CONFIG_MISC_DEVICES=y 413CONFIG_MISC_DEVICES=y
385# CONFIG_PHANTOM is not set 414# CONFIG_PHANTOM is not set
386# CONFIG_EEPROM_93CX6 is not set 415# CONFIG_EEPROM_93CX6 is not set
387# CONFIG_SGI_IOC4 is not set 416# CONFIG_SGI_IOC4 is not set
388# CONFIG_TIFM_CORE is not set 417# CONFIG_TIFM_CORE is not set
389# CONFIG_ENCLOSURE_SERVICES is not set 418# CONFIG_ENCLOSURE_SERVICES is not set
419# CONFIG_HP_ILO is not set
390CONFIG_HAVE_IDE=y 420CONFIG_HAVE_IDE=y
391# CONFIG_IDE is not set 421# CONFIG_IDE is not set
392 422
@@ -463,7 +493,10 @@ CONFIG_SCSI_LOWLEVEL=y
463# CONFIG_SCSI_DC390T is not set 493# CONFIG_SCSI_DC390T is not set
464# CONFIG_SCSI_NSP32 is not set 494# CONFIG_SCSI_NSP32 is not set
465# CONFIG_SCSI_DEBUG is not set 495# CONFIG_SCSI_DEBUG is not set
496# CONFIG_SCSI_MESH is not set
497# CONFIG_SCSI_MAC53C94 is not set
466# CONFIG_SCSI_SRP is not set 498# CONFIG_SCSI_SRP is not set
499# CONFIG_SCSI_DH is not set
467# CONFIG_ATA is not set 500# CONFIG_ATA is not set
468# CONFIG_MD is not set 501# CONFIG_MD is not set
469# CONFIG_FUSION is not set 502# CONFIG_FUSION is not set
@@ -471,12 +504,15 @@ CONFIG_SCSI_LOWLEVEL=y
471# 504#
472# IEEE 1394 (FireWire) support 505# IEEE 1394 (FireWire) support
473# 506#
507
508#
509# Enable only one of the two stacks, unless you know what you are doing
510#
474# CONFIG_FIREWIRE is not set 511# CONFIG_FIREWIRE is not set
475# CONFIG_IEEE1394 is not set 512# CONFIG_IEEE1394 is not set
476# CONFIG_I2O is not set 513# CONFIG_I2O is not set
477# CONFIG_MACINTOSH_DRIVERS is not set 514# CONFIG_MACINTOSH_DRIVERS is not set
478CONFIG_NETDEVICES=y 515CONFIG_NETDEVICES=y
479# CONFIG_NETDEVICES_MULTIQUEUE is not set
480# CONFIG_DUMMY is not set 516# CONFIG_DUMMY is not set
481# CONFIG_BONDING is not set 517# CONFIG_BONDING is not set
482# CONFIG_MACVLAN is not set 518# CONFIG_MACVLAN is not set
@@ -503,6 +539,8 @@ CONFIG_ICPLUS_PHY=y
503# CONFIG_MDIO_BITBANG is not set 539# CONFIG_MDIO_BITBANG is not set
504CONFIG_NET_ETHERNET=y 540CONFIG_NET_ETHERNET=y
505CONFIG_MII=y 541CONFIG_MII=y
542# CONFIG_MACE is not set
543# CONFIG_BMAC is not set
506# CONFIG_HAPPYMEAL is not set 544# CONFIG_HAPPYMEAL is not set
507# CONFIG_SUNGEM is not set 545# CONFIG_SUNGEM is not set
508# CONFIG_CASSINI is not set 546# CONFIG_CASSINI is not set
@@ -520,10 +558,8 @@ CONFIG_NETDEV_1000=y
520# CONFIG_ACENIC is not set 558# CONFIG_ACENIC is not set
521# CONFIG_DL2K is not set 559# CONFIG_DL2K is not set
522CONFIG_E1000=y 560CONFIG_E1000=y
523# CONFIG_E1000_NAPI is not set
524# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set 561# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
525# CONFIG_E1000E is not set 562# CONFIG_E1000E is not set
526# CONFIG_E1000E_ENABLED is not set
527# CONFIG_IP1000 is not set 563# CONFIG_IP1000 is not set
528# CONFIG_IGB is not set 564# CONFIG_IGB is not set
529# CONFIG_NS83820 is not set 565# CONFIG_NS83820 is not set
@@ -538,12 +574,13 @@ CONFIG_E1000=y
538# CONFIG_BNX2 is not set 574# CONFIG_BNX2 is not set
539# CONFIG_GIANFAR is not set 575# CONFIG_GIANFAR is not set
540CONFIG_UCC_GETH=y 576CONFIG_UCC_GETH=y
541CONFIG_UGETH_NAPI=y
542# CONFIG_UGETH_MAGIC_PACKET is not set 577# CONFIG_UGETH_MAGIC_PACKET is not set
543# CONFIG_UGETH_FILTERING is not set 578# CONFIG_UGETH_FILTERING is not set
544# CONFIG_UGETH_TX_ON_DEMAND is not set 579# CONFIG_UGETH_TX_ON_DEMAND is not set
580# CONFIG_MV643XX_ETH is not set
545# CONFIG_QLA3XXX is not set 581# CONFIG_QLA3XXX is not set
546# CONFIG_ATL1 is not set 582# CONFIG_ATL1 is not set
583# CONFIG_ATL1E is not set
547CONFIG_NETDEV_10000=y 584CONFIG_NETDEV_10000=y
548# CONFIG_CHELSIO_T1 is not set 585# CONFIG_CHELSIO_T1 is not set
549# CONFIG_CHELSIO_T3 is not set 586# CONFIG_CHELSIO_T3 is not set
@@ -641,12 +678,15 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=4
641# CONFIG_SERIAL_UARTLITE is not set 678# CONFIG_SERIAL_UARTLITE is not set
642CONFIG_SERIAL_CORE=y 679CONFIG_SERIAL_CORE=y
643CONFIG_SERIAL_CORE_CONSOLE=y 680CONFIG_SERIAL_CORE_CONSOLE=y
681# CONFIG_SERIAL_PMACZILOG is not set
644# CONFIG_SERIAL_JSM is not set 682# CONFIG_SERIAL_JSM is not set
645# CONFIG_SERIAL_OF_PLATFORM is not set 683# CONFIG_SERIAL_OF_PLATFORM is not set
646# CONFIG_SERIAL_QE is not set 684# CONFIG_SERIAL_QE is not set
647CONFIG_UNIX98_PTYS=y 685CONFIG_UNIX98_PTYS=y
648CONFIG_LEGACY_PTYS=y 686CONFIG_LEGACY_PTYS=y
649CONFIG_LEGACY_PTY_COUNT=256 687CONFIG_LEGACY_PTY_COUNT=256
688# CONFIG_BRIQ_PANEL is not set
689# CONFIG_HVC_RTAS is not set
650# CONFIG_IPMI_HANDLER is not set 690# CONFIG_IPMI_HANDLER is not set
651CONFIG_HW_RANDOM=y 691CONFIG_HW_RANDOM=y
652# CONFIG_NVRAM is not set 692# CONFIG_NVRAM is not set
@@ -660,43 +700,70 @@ CONFIG_DEVPORT=y
660CONFIG_I2C=y 700CONFIG_I2C=y
661CONFIG_I2C_BOARDINFO=y 701CONFIG_I2C_BOARDINFO=y
662CONFIG_I2C_CHARDEV=y 702CONFIG_I2C_CHARDEV=y
703CONFIG_I2C_HELPER_AUTO=y
663 704
664# 705#
665# I2C Hardware Bus support 706# I2C Hardware Bus support
666# 707#
708
709#
710# PC SMBus host controller drivers
711#
667# CONFIG_I2C_ALI1535 is not set 712# CONFIG_I2C_ALI1535 is not set
668# CONFIG_I2C_ALI1563 is not set 713# CONFIG_I2C_ALI1563 is not set
669# CONFIG_I2C_ALI15X3 is not set 714# CONFIG_I2C_ALI15X3 is not set
670# CONFIG_I2C_AMD756 is not set 715# CONFIG_I2C_AMD756 is not set
671# CONFIG_I2C_AMD8111 is not set 716# CONFIG_I2C_AMD8111 is not set
672# CONFIG_I2C_I801 is not set 717# CONFIG_I2C_I801 is not set
673# CONFIG_I2C_I810 is not set 718# CONFIG_I2C_ISCH is not set
674# CONFIG_I2C_PIIX4 is not set 719# CONFIG_I2C_PIIX4 is not set
675CONFIG_I2C_MPC=y
676# CONFIG_I2C_NFORCE2 is not set 720# CONFIG_I2C_NFORCE2 is not set
677# CONFIG_I2C_OCORES is not set
678# CONFIG_I2C_PARPORT_LIGHT is not set
679# CONFIG_I2C_PROSAVAGE is not set
680# CONFIG_I2C_SAVAGE4 is not set
681# CONFIG_I2C_SIMTEC is not set
682# CONFIG_I2C_SIS5595 is not set 721# CONFIG_I2C_SIS5595 is not set
683# CONFIG_I2C_SIS630 is not set 722# CONFIG_I2C_SIS630 is not set
684# CONFIG_I2C_SIS96X is not set 723# CONFIG_I2C_SIS96X is not set
685# CONFIG_I2C_TAOS_EVM is not set
686# CONFIG_I2C_STUB is not set
687# CONFIG_I2C_TINY_USB is not set
688# CONFIG_I2C_VIA is not set 724# CONFIG_I2C_VIA is not set
689# CONFIG_I2C_VIAPRO is not set 725# CONFIG_I2C_VIAPRO is not set
726
727#
728# Mac SMBus host controller drivers
729#
730# CONFIG_I2C_HYDRA is not set
731CONFIG_I2C_POWERMAC=y
732
733#
734# I2C system bus drivers (mostly embedded / system-on-chip)
735#
736CONFIG_I2C_MPC=y
737# CONFIG_I2C_OCORES is not set
738# CONFIG_I2C_SIMTEC is not set
739
740#
741# External I2C/SMBus adapter drivers
742#
743# CONFIG_I2C_PARPORT_LIGHT is not set
744# CONFIG_I2C_TAOS_EVM is not set
745# CONFIG_I2C_TINY_USB is not set
746
747#
748# Graphics adapter I2C/DDC channel drivers
749#
690# CONFIG_I2C_VOODOO3 is not set 750# CONFIG_I2C_VOODOO3 is not set
751
752#
753# Other I2C/SMBus bus drivers
754#
691# CONFIG_I2C_PCA_PLATFORM is not set 755# CONFIG_I2C_PCA_PLATFORM is not set
756# CONFIG_I2C_STUB is not set
692 757
693# 758#
694# Miscellaneous I2C Chip support 759# Miscellaneous I2C Chip support
695# 760#
696# CONFIG_DS1682 is not set 761# CONFIG_DS1682 is not set
762# CONFIG_AT24 is not set
697# CONFIG_SENSORS_EEPROM is not set 763# CONFIG_SENSORS_EEPROM is not set
698# CONFIG_SENSORS_PCF8574 is not set 764# CONFIG_SENSORS_PCF8574 is not set
699# CONFIG_PCF8575 is not set 765# CONFIG_PCF8575 is not set
766# CONFIG_SENSORS_PCA9539 is not set
700# CONFIG_SENSORS_PCF8591 is not set 767# CONFIG_SENSORS_PCF8591 is not set
701# CONFIG_SENSORS_MAX6875 is not set 768# CONFIG_SENSORS_MAX6875 is not set
702# CONFIG_SENSORS_TSL2550 is not set 769# CONFIG_SENSORS_TSL2550 is not set
@@ -719,11 +786,15 @@ CONFIG_SPI_MPC83xx=y
719# CONFIG_SPI_AT25 is not set 786# CONFIG_SPI_AT25 is not set
720# CONFIG_SPI_SPIDEV is not set 787# CONFIG_SPI_SPIDEV is not set
721# CONFIG_SPI_TLE62X0 is not set 788# CONFIG_SPI_TLE62X0 is not set
789CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
790# CONFIG_GPIOLIB is not set
722# CONFIG_W1 is not set 791# CONFIG_W1 is not set
723# CONFIG_POWER_SUPPLY is not set 792# CONFIG_POWER_SUPPLY is not set
724CONFIG_HWMON=y 793CONFIG_HWMON=y
725# CONFIG_HWMON_VID is not set 794# CONFIG_HWMON_VID is not set
795# CONFIG_SENSORS_AD7414 is not set
726# CONFIG_SENSORS_AD7418 is not set 796# CONFIG_SENSORS_AD7418 is not set
797# CONFIG_SENSORS_ADCXX is not set
727# CONFIG_SENSORS_ADM1021 is not set 798# CONFIG_SENSORS_ADM1021 is not set
728# CONFIG_SENSORS_ADM1025 is not set 799# CONFIG_SENSORS_ADM1025 is not set
729# CONFIG_SENSORS_ADM1026 is not set 800# CONFIG_SENSORS_ADM1026 is not set
@@ -732,6 +803,7 @@ CONFIG_HWMON=y
732# CONFIG_SENSORS_ADM9240 is not set 803# CONFIG_SENSORS_ADM9240 is not set
733# CONFIG_SENSORS_ADT7470 is not set 804# CONFIG_SENSORS_ADT7470 is not set
734# CONFIG_SENSORS_ADT7473 is not set 805# CONFIG_SENSORS_ADT7473 is not set
806# CONFIG_SENSORS_AMS is not set
735# CONFIG_SENSORS_ATXP1 is not set 807# CONFIG_SENSORS_ATXP1 is not set
736# CONFIG_SENSORS_DS1621 is not set 808# CONFIG_SENSORS_DS1621 is not set
737# CONFIG_SENSORS_I5K_AMB is not set 809# CONFIG_SENSORS_I5K_AMB is not set
@@ -777,6 +849,7 @@ CONFIG_HWMON=y
777# CONFIG_SENSORS_W83627EHF is not set 849# CONFIG_SENSORS_W83627EHF is not set
778# CONFIG_HWMON_DEBUG_CHIP is not set 850# CONFIG_HWMON_DEBUG_CHIP is not set
779# CONFIG_THERMAL is not set 851# CONFIG_THERMAL is not set
852# CONFIG_THERMAL_HWMON is not set
780CONFIG_WATCHDOG=y 853CONFIG_WATCHDOG=y
781# CONFIG_WATCHDOG_NOWAYOUT is not set 854# CONFIG_WATCHDOG_NOWAYOUT is not set
782 855
@@ -784,7 +857,9 @@ CONFIG_WATCHDOG=y
784# Watchdog Device Drivers 857# Watchdog Device Drivers
785# 858#
786# CONFIG_SOFT_WATCHDOG is not set 859# CONFIG_SOFT_WATCHDOG is not set
787CONFIG_83xx_WDT=y 860# CONFIG_ALIM7101_WDT is not set
861# CONFIG_8xxx_WDT is not set
862# CONFIG_WATCHDOG_RTAS is not set
788 863
789# 864#
790# PCI-based Watchdog Cards 865# PCI-based Watchdog Cards
@@ -806,8 +881,10 @@ CONFIG_SSB_POSSIBLE=y
806# 881#
807# Multifunction device drivers 882# Multifunction device drivers
808# 883#
884# CONFIG_MFD_CORE is not set
809# CONFIG_MFD_SM501 is not set 885# CONFIG_MFD_SM501 is not set
810# CONFIG_HTC_PASIC3 is not set 886# CONFIG_HTC_PASIC3 is not set
887# CONFIG_MFD_TMIO is not set
811 888
812# 889#
813# Multimedia devices 890# Multimedia devices
@@ -840,10 +917,6 @@ CONFIG_VIDEO_OUTPUT_CONTROL=m
840# Display device support 917# Display device support
841# 918#
842# CONFIG_DISPLAY_SUPPORT is not set 919# CONFIG_DISPLAY_SUPPORT is not set
843
844#
845# Sound
846#
847# CONFIG_SOUND is not set 920# CONFIG_SOUND is not set
848CONFIG_HID_SUPPORT=y 921CONFIG_HID_SUPPORT=y
849CONFIG_HID=y 922CONFIG_HID=y
@@ -877,6 +950,7 @@ CONFIG_USB_DEVICE_CLASS=y
877# CONFIG_USB_OTG is not set 950# CONFIG_USB_OTG is not set
878# CONFIG_USB_OTG_WHITELIST is not set 951# CONFIG_USB_OTG_WHITELIST is not set
879# CONFIG_USB_OTG_BLACKLIST_HUB is not set 952# CONFIG_USB_OTG_BLACKLIST_HUB is not set
953CONFIG_USB_MON=y
880 954
881# 955#
882# USB Host Controller Drivers 956# USB Host Controller Drivers
@@ -928,6 +1002,7 @@ CONFIG_USB_STORAGE=y
928# CONFIG_USB_STORAGE_ALAUDA is not set 1002# CONFIG_USB_STORAGE_ALAUDA is not set
929# CONFIG_USB_STORAGE_ONETOUCH is not set 1003# CONFIG_USB_STORAGE_ONETOUCH is not set
930# CONFIG_USB_STORAGE_KARMA is not set 1004# CONFIG_USB_STORAGE_KARMA is not set
1005# CONFIG_USB_STORAGE_SIERRA is not set
931# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set 1006# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
932# CONFIG_USB_LIBUSUAL is not set 1007# CONFIG_USB_LIBUSUAL is not set
933 1008
@@ -936,7 +1011,6 @@ CONFIG_USB_STORAGE=y
936# 1011#
937# CONFIG_USB_MDC800 is not set 1012# CONFIG_USB_MDC800 is not set
938# CONFIG_USB_MICROTEK is not set 1013# CONFIG_USB_MICROTEK is not set
939CONFIG_USB_MON=y
940 1014
941# 1015#
942# USB port drivers 1016# USB port drivers
@@ -949,7 +1023,6 @@ CONFIG_USB_MON=y
949# CONFIG_USB_EMI62 is not set 1023# CONFIG_USB_EMI62 is not set
950# CONFIG_USB_EMI26 is not set 1024# CONFIG_USB_EMI26 is not set
951# CONFIG_USB_ADUTUX is not set 1025# CONFIG_USB_ADUTUX is not set
952# CONFIG_USB_AUERSWALD is not set
953# CONFIG_USB_RIO500 is not set 1026# CONFIG_USB_RIO500 is not set
954# CONFIG_USB_LEGOTOWER is not set 1027# CONFIG_USB_LEGOTOWER is not set
955# CONFIG_USB_LCD is not set 1028# CONFIG_USB_LCD is not set
@@ -1063,6 +1136,7 @@ CONFIG_TMPFS=y
1063# CONFIG_CRAMFS is not set 1136# CONFIG_CRAMFS is not set
1064# CONFIG_VXFS_FS is not set 1137# CONFIG_VXFS_FS is not set
1065# CONFIG_MINIX_FS is not set 1138# CONFIG_MINIX_FS is not set
1139# CONFIG_OMFS_FS is not set
1066# CONFIG_HPFS_FS is not set 1140# CONFIG_HPFS_FS is not set
1067# CONFIG_QNX4FS_FS is not set 1141# CONFIG_QNX4FS_FS is not set
1068# CONFIG_ROMFS_FS is not set 1142# CONFIG_ROMFS_FS is not set
@@ -1073,14 +1147,13 @@ CONFIG_NFS_FS=y
1073CONFIG_NFS_V3=y 1147CONFIG_NFS_V3=y
1074# CONFIG_NFS_V3_ACL is not set 1148# CONFIG_NFS_V3_ACL is not set
1075CONFIG_NFS_V4=y 1149CONFIG_NFS_V4=y
1076# CONFIG_NFSD is not set
1077CONFIG_ROOT_NFS=y 1150CONFIG_ROOT_NFS=y
1151# CONFIG_NFSD is not set
1078CONFIG_LOCKD=y 1152CONFIG_LOCKD=y
1079CONFIG_LOCKD_V4=y 1153CONFIG_LOCKD_V4=y
1080CONFIG_NFS_COMMON=y 1154CONFIG_NFS_COMMON=y
1081CONFIG_SUNRPC=y 1155CONFIG_SUNRPC=y
1082CONFIG_SUNRPC_GSS=y 1156CONFIG_SUNRPC_GSS=y
1083# CONFIG_SUNRPC_BIND34 is not set
1084CONFIG_RPCSEC_GSS_KRB5=y 1157CONFIG_RPCSEC_GSS_KRB5=y
1085# CONFIG_RPCSEC_GSS_SPKM3 is not set 1158# CONFIG_RPCSEC_GSS_SPKM3 is not set
1086# CONFIG_SMB_FS is not set 1159# CONFIG_SMB_FS is not set
@@ -1154,6 +1227,7 @@ CONFIG_NLS_ISO8859_1=y
1154# CONFIG_DLM is not set 1227# CONFIG_DLM is not set
1155CONFIG_UCC_FAST=y 1228CONFIG_UCC_FAST=y
1156CONFIG_UCC=y 1229CONFIG_UCC=y
1230# CONFIG_QE_GPIO is not set
1157 1231
1158# 1232#
1159# Library routines 1233# Library routines
@@ -1162,6 +1236,7 @@ CONFIG_BITREVERSE=y
1162# CONFIG_GENERIC_FIND_FIRST_BIT is not set 1236# CONFIG_GENERIC_FIND_FIRST_BIT is not set
1163# CONFIG_CRC_CCITT is not set 1237# CONFIG_CRC_CCITT is not set
1164# CONFIG_CRC16 is not set 1238# CONFIG_CRC16 is not set
1239CONFIG_CRC_T10DIF=y
1165CONFIG_CRC_ITU_T=y 1240CONFIG_CRC_ITU_T=y
1166CONFIG_CRC32=y 1241CONFIG_CRC32=y
1167CONFIG_CRC7=y 1242CONFIG_CRC7=y
@@ -1187,8 +1262,18 @@ CONFIG_FRAME_WARN=1024
1187# CONFIG_SLUB_DEBUG_ON is not set 1262# CONFIG_SLUB_DEBUG_ON is not set
1188# CONFIG_SLUB_STATS is not set 1263# CONFIG_SLUB_STATS is not set
1189# CONFIG_DEBUG_BUGVERBOSE is not set 1264# CONFIG_DEBUG_BUGVERBOSE is not set
1265# CONFIG_DEBUG_MEMORY_INIT is not set
1266# CONFIG_LATENCYTOP is not set
1267CONFIG_SYSCTL_SYSCALL_CHECK=y
1268CONFIG_HAVE_FTRACE=y
1269CONFIG_HAVE_DYNAMIC_FTRACE=y
1270# CONFIG_FTRACE is not set
1271# CONFIG_SCHED_TRACER is not set
1272# CONFIG_CONTEXT_SWITCH_TRACER is not set
1190# CONFIG_SAMPLES is not set 1273# CONFIG_SAMPLES is not set
1274CONFIG_HAVE_ARCH_KGDB=y
1191# CONFIG_IRQSTACKS is not set 1275# CONFIG_IRQSTACKS is not set
1276# CONFIG_BOOTX_TEXT is not set
1192# CONFIG_PPC_EARLY_DEBUG is not set 1277# CONFIG_PPC_EARLY_DEBUG is not set
1193 1278
1194# 1279#
@@ -1242,6 +1327,10 @@ CONFIG_CRYPTO_PCBC=m
1242# CONFIG_CRYPTO_MD4 is not set 1327# CONFIG_CRYPTO_MD4 is not set
1243CONFIG_CRYPTO_MD5=y 1328CONFIG_CRYPTO_MD5=y
1244# CONFIG_CRYPTO_MICHAEL_MIC is not set 1329# CONFIG_CRYPTO_MICHAEL_MIC is not set
1330# CONFIG_CRYPTO_RMD128 is not set
1331# CONFIG_CRYPTO_RMD160 is not set
1332# CONFIG_CRYPTO_RMD256 is not set
1333# CONFIG_CRYPTO_RMD320 is not set
1245# CONFIG_CRYPTO_SHA1 is not set 1334# CONFIG_CRYPTO_SHA1 is not set
1246# CONFIG_CRYPTO_SHA256 is not set 1335# CONFIG_CRYPTO_SHA256 is not set
1247# CONFIG_CRYPTO_SHA512 is not set 1336# CONFIG_CRYPTO_SHA512 is not set
@@ -1274,6 +1363,7 @@ CONFIG_CRYPTO_DES=y
1274# CONFIG_CRYPTO_LZO is not set 1363# CONFIG_CRYPTO_LZO is not set
1275CONFIG_CRYPTO_HW=y 1364CONFIG_CRYPTO_HW=y
1276# CONFIG_CRYPTO_DEV_HIFN_795X is not set 1365# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1366# CONFIG_CRYPTO_DEV_TALITOS is not set
1277# CONFIG_PPC_CLOCK is not set 1367# CONFIG_PPC_CLOCK is not set
1278CONFIG_PPC_LIB_RHEAP=y 1368CONFIG_PPC_LIB_RHEAP=y
1279# CONFIG_VIRTUALIZATION is not set 1369# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/configs/83xx/mpc834x_itx_defconfig b/arch/powerpc/configs/83xx/mpc834x_itx_defconfig
index b47fc9185708..8d6513931850 100644
--- a/arch/powerpc/configs/83xx/mpc834x_itx_defconfig
+++ b/arch/powerpc/configs/83xx/mpc834x_itx_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc5 3# Linux kernel version: 2.6.27-rc4
4# Mon Jun 9 08:52:25 2008 4# Thu Aug 21 00:52:20 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -16,6 +16,7 @@ CONFIG_6xx=y
16# CONFIG_E200 is not set 16# CONFIG_E200 is not set
17CONFIG_PPC_FPU=y 17CONFIG_PPC_FPU=y
18# CONFIG_FSL_EMB_PERFMON is not set 18# CONFIG_FSL_EMB_PERFMON is not set
19# CONFIG_ALTIVEC is not set
19CONFIG_PPC_STD_MMU=y 20CONFIG_PPC_STD_MMU=y
20CONFIG_PPC_STD_MMU_32=y 21CONFIG_PPC_STD_MMU_32=y
21# CONFIG_PPC_MM_SLICES is not set 22# CONFIG_PPC_MM_SLICES is not set
@@ -32,6 +33,7 @@ CONFIG_GENERIC_HARDIRQS=y
32# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set 33# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
33CONFIG_IRQ_PER_CPU=y 34CONFIG_IRQ_PER_CPU=y
34CONFIG_STACKTRACE_SUPPORT=y 35CONFIG_STACKTRACE_SUPPORT=y
36CONFIG_HAVE_LATENCYTOP_SUPPORT=y
35CONFIG_LOCKDEP_SUPPORT=y 37CONFIG_LOCKDEP_SUPPORT=y
36CONFIG_RWSEM_XCHGADD_ALGORITHM=y 38CONFIG_RWSEM_XCHGADD_ALGORITHM=y
37CONFIG_ARCH_HAS_ILOG2_U32=y 39CONFIG_ARCH_HAS_ILOG2_U32=y
@@ -51,6 +53,9 @@ CONFIG_PPC_UDBG_16550=y
51CONFIG_AUDIT_ARCH=y 53CONFIG_AUDIT_ARCH=y
52CONFIG_GENERIC_BUG=y 54CONFIG_GENERIC_BUG=y
53CONFIG_DEFAULT_UIMAGE=y 55CONFIG_DEFAULT_UIMAGE=y
56CONFIG_HIBERNATE_32=y
57CONFIG_ARCH_HIBERNATION_POSSIBLE=y
58CONFIG_ARCH_SUSPEND_POSSIBLE=y
54# CONFIG_PPC_DCR_NATIVE is not set 59# CONFIG_PPC_DCR_NATIVE is not set
55# CONFIG_PPC_DCR_MMIO is not set 60# CONFIG_PPC_DCR_MMIO is not set
56CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 61CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
@@ -88,12 +93,12 @@ CONFIG_INITRAMFS_SOURCE=""
88CONFIG_SYSCTL=y 93CONFIG_SYSCTL=y
89CONFIG_EMBEDDED=y 94CONFIG_EMBEDDED=y
90CONFIG_SYSCTL_SYSCALL=y 95CONFIG_SYSCTL_SYSCALL=y
91CONFIG_SYSCTL_SYSCALL_CHECK=y
92# CONFIG_KALLSYMS is not set 96# CONFIG_KALLSYMS is not set
93CONFIG_HOTPLUG=y 97CONFIG_HOTPLUG=y
94CONFIG_PRINTK=y 98CONFIG_PRINTK=y
95CONFIG_BUG=y 99CONFIG_BUG=y
96CONFIG_ELF_CORE=y 100CONFIG_ELF_CORE=y
101CONFIG_PCSPKR_PLATFORM=y
97CONFIG_COMPAT_BRK=y 102CONFIG_COMPAT_BRK=y
98CONFIG_BASE_FULL=y 103CONFIG_BASE_FULL=y
99CONFIG_FUTEX=y 104CONFIG_FUTEX=y
@@ -111,10 +116,16 @@ CONFIG_SLUB=y
111# CONFIG_PROFILING is not set 116# CONFIG_PROFILING is not set
112# CONFIG_MARKERS is not set 117# CONFIG_MARKERS is not set
113CONFIG_HAVE_OPROFILE=y 118CONFIG_HAVE_OPROFILE=y
119CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
120CONFIG_HAVE_IOREMAP_PROT=y
114CONFIG_HAVE_KPROBES=y 121CONFIG_HAVE_KPROBES=y
115CONFIG_HAVE_KRETPROBES=y 122CONFIG_HAVE_KRETPROBES=y
123CONFIG_HAVE_ARCH_TRACEHOOK=y
116# CONFIG_HAVE_DMA_ATTRS is not set 124# CONFIG_HAVE_DMA_ATTRS is not set
125# CONFIG_USE_GENERIC_SMP_HELPERS is not set
126# CONFIG_HAVE_CLK is not set
117CONFIG_PROC_PAGE_MONITOR=y 127CONFIG_PROC_PAGE_MONITOR=y
128# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
118CONFIG_SLABINFO=y 129CONFIG_SLABINFO=y
119CONFIG_RT_MUTEXES=y 130CONFIG_RT_MUTEXES=y
120# CONFIG_TINY_SHMEM is not set 131# CONFIG_TINY_SHMEM is not set
@@ -125,12 +136,13 @@ CONFIG_MODULE_UNLOAD=y
125# CONFIG_MODULE_FORCE_UNLOAD is not set 136# CONFIG_MODULE_FORCE_UNLOAD is not set
126# CONFIG_MODVERSIONS is not set 137# CONFIG_MODVERSIONS is not set
127# CONFIG_MODULE_SRCVERSION_ALL is not set 138# CONFIG_MODULE_SRCVERSION_ALL is not set
128# CONFIG_KMOD is not set 139CONFIG_KMOD=y
129CONFIG_BLOCK=y 140CONFIG_BLOCK=y
130# CONFIG_LBD is not set 141# CONFIG_LBD is not set
131# CONFIG_BLK_DEV_IO_TRACE is not set 142# CONFIG_BLK_DEV_IO_TRACE is not set
132# CONFIG_LSF is not set 143# CONFIG_LSF is not set
133# CONFIG_BLK_DEV_BSG is not set 144# CONFIG_BLK_DEV_BSG is not set
145# CONFIG_BLK_DEV_INTEGRITY is not set
134 146
135# 147#
136# IO Schedulers 148# IO Schedulers
@@ -149,37 +161,49 @@ CONFIG_CLASSIC_RCU=y
149# 161#
150# Platform support 162# Platform support
151# 163#
152# CONFIG_PPC_MULTIPLATFORM is not set 164CONFIG_PPC_MULTIPLATFORM=y
153# CONFIG_PPC_82xx is not set 165CONFIG_CLASSIC32=y
154CONFIG_PPC_83xx=y 166CONFIG_PPC_CHRP=y
155# CONFIG_PPC_86xx is not set 167# CONFIG_MPC5121_ADS is not set
156# CONFIG_PPC_MPC512x is not set 168# CONFIG_MPC5121_GENERIC is not set
157# CONFIG_PPC_MPC5121 is not set 169# CONFIG_PPC_MPC52xx is not set
170CONFIG_PPC_PMAC=y
158# CONFIG_PPC_CELL is not set 171# CONFIG_PPC_CELL is not set
159# CONFIG_PPC_CELL_NATIVE is not set 172# CONFIG_PPC_CELL_NATIVE is not set
173# CONFIG_PPC_82xx is not set
160# CONFIG_PQ2ADS is not set 174# CONFIG_PQ2ADS is not set
161CONFIG_MPC83xx=y 175CONFIG_PPC_83xx=y
162# CONFIG_MPC831x_RDB is not set 176# CONFIG_MPC831x_RDB is not set
163# CONFIG_MPC832x_MDS is not set 177# CONFIG_MPC832x_MDS is not set
164# CONFIG_MPC832x_RDB is not set 178# CONFIG_MPC832x_RDB is not set
165# CONFIG_MPC834x_MDS is not set 179# CONFIG_MPC834x_MDS is not set
166CONFIG_MPC834x_ITX=y 180CONFIG_MPC834x_ITX=y
167# CONFIG_MPC836x_MDS is not set 181# CONFIG_MPC836x_MDS is not set
182# CONFIG_MPC836x_RDK is not set
168# CONFIG_MPC837x_MDS is not set 183# CONFIG_MPC837x_MDS is not set
169# CONFIG_MPC837x_RDB is not set 184# CONFIG_MPC837x_RDB is not set
170# CONFIG_SBC834x is not set 185# CONFIG_SBC834x is not set
186# CONFIG_ASP834x is not set
171CONFIG_PPC_MPC834x=y 187CONFIG_PPC_MPC834x=y
188# CONFIG_PPC_86xx is not set
189# CONFIG_EMBEDDED6xx is not set
190CONFIG_PPC_NATIVE=y
191# CONFIG_UDBG_RTAS_CONSOLE is not set
172CONFIG_IPIC=y 192CONFIG_IPIC=y
173# CONFIG_MPIC is not set 193CONFIG_MPIC=y
174# CONFIG_MPIC_WEIRD is not set 194# CONFIG_MPIC_WEIRD is not set
175# CONFIG_PPC_I8259 is not set 195CONFIG_PPC_I8259=y
176# CONFIG_PPC_RTAS is not set 196CONFIG_PPC_RTAS=y
197# CONFIG_RTAS_ERROR_LOGGING is not set
198CONFIG_RTAS_PROC=y
177# CONFIG_MMIO_NVRAM is not set 199# CONFIG_MMIO_NVRAM is not set
178# CONFIG_PPC_MPC106 is not set 200CONFIG_PPC_MPC106=y
179# CONFIG_PPC_970_NAP is not set 201# CONFIG_PPC_970_NAP is not set
180# CONFIG_PPC_INDIRECT_IO is not set 202# CONFIG_PPC_INDIRECT_IO is not set
181# CONFIG_GENERIC_IOMAP is not set 203# CONFIG_GENERIC_IOMAP is not set
182# CONFIG_CPU_FREQ is not set 204# CONFIG_CPU_FREQ is not set
205# CONFIG_PPC601_SYNC_FIX is not set
206# CONFIG_TAU is not set
183# CONFIG_FSL_ULI1575 is not set 207# CONFIG_FSL_ULI1575 is not set
184 208
185# 209#
@@ -195,7 +219,7 @@ CONFIG_HZ_250=y
195# CONFIG_HZ_300 is not set 219# CONFIG_HZ_300 is not set
196# CONFIG_HZ_1000 is not set 220# CONFIG_HZ_1000 is not set
197CONFIG_HZ=250 221CONFIG_HZ=250
198# CONFIG_SCHED_HRTICK is not set 222CONFIG_SCHED_HRTICK=y
199CONFIG_PREEMPT_NONE=y 223CONFIG_PREEMPT_NONE=y
200# CONFIG_PREEMPT_VOLUNTARY is not set 224# CONFIG_PREEMPT_VOLUNTARY is not set
201# CONFIG_PREEMPT is not set 225# CONFIG_PREEMPT is not set
@@ -205,6 +229,7 @@ CONFIG_BINFMT_ELF=y
205CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y 229CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
206CONFIG_ARCH_HAS_WALK_MEMORY=y 230CONFIG_ARCH_HAS_WALK_MEMORY=y
207CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y 231CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
232# CONFIG_KEXEC is not set
208CONFIG_ARCH_FLATMEM_ENABLE=y 233CONFIG_ARCH_FLATMEM_ENABLE=y
209CONFIG_ARCH_POPULATES_NODE_MAP=y 234CONFIG_ARCH_POPULATES_NODE_MAP=y
210CONFIG_SELECT_MEMORY_MODEL=y 235CONFIG_SELECT_MEMORY_MODEL=y
@@ -217,6 +242,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
217# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set 242# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
218CONFIG_PAGEFLAGS_EXTENDED=y 243CONFIG_PAGEFLAGS_EXTENDED=y
219CONFIG_SPLIT_PTLOCK_CPUS=4 244CONFIG_SPLIT_PTLOCK_CPUS=4
245CONFIG_MIGRATION=y
220# CONFIG_RESOURCES_64BIT is not set 246# CONFIG_RESOURCES_64BIT is not set
221CONFIG_ZONE_DMA_FLAG=1 247CONFIG_ZONE_DMA_FLAG=1
222CONFIG_BOUNCE=y 248CONFIG_BOUNCE=y
@@ -224,6 +250,7 @@ CONFIG_VIRT_TO_BUS=y
224CONFIG_FORCE_MAX_ZONEORDER=11 250CONFIG_FORCE_MAX_ZONEORDER=11
225CONFIG_PROC_DEVICETREE=y 251CONFIG_PROC_DEVICETREE=y
226# CONFIG_CMDLINE_BOOL is not set 252# CONFIG_CMDLINE_BOOL is not set
253CONFIG_EXTRA_TARGETS=""
227# CONFIG_PM is not set 254# CONFIG_PM is not set
228CONFIG_SECCOMP=y 255CONFIG_SECCOMP=y
229CONFIG_ISA_DMA_API=y 256CONFIG_ISA_DMA_API=y
@@ -231,10 +258,13 @@ CONFIG_ISA_DMA_API=y
231# 258#
232# Bus options 259# Bus options
233# 260#
261# CONFIG_ISA is not set
234CONFIG_ZONE_DMA=y 262CONFIG_ZONE_DMA=y
235CONFIG_GENERIC_ISA_DMA=y 263CONFIG_GENERIC_ISA_DMA=y
236CONFIG_PPC_INDIRECT_PCI=y 264CONFIG_PPC_INDIRECT_PCI=y
237CONFIG_FSL_SOC=y 265CONFIG_FSL_SOC=y
266CONFIG_FSL_PCI=y
267CONFIG_PPC_PCI_CHOICE=y
238CONFIG_PCI=y 268CONFIG_PCI=y
239CONFIG_PCI_DOMAINS=y 269CONFIG_PCI_DOMAINS=y
240CONFIG_PCI_SYSCALL=y 270CONFIG_PCI_SYSCALL=y
@@ -259,10 +289,6 @@ CONFIG_PAGE_OFFSET=0xc0000000
259CONFIG_KERNEL_START=0xc0000000 289CONFIG_KERNEL_START=0xc0000000
260CONFIG_PHYSICAL_START=0x00000000 290CONFIG_PHYSICAL_START=0x00000000
261CONFIG_TASK_SIZE=0xc0000000 291CONFIG_TASK_SIZE=0xc0000000
262
263#
264# Networking
265#
266CONFIG_NET=y 292CONFIG_NET=y
267 293
268# 294#
@@ -439,9 +465,11 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=2
439# CONFIG_MTD_UBI is not set 465# CONFIG_MTD_UBI is not set
440CONFIG_OF_DEVICE=y 466CONFIG_OF_DEVICE=y
441CONFIG_OF_I2C=y 467CONFIG_OF_I2C=y
468CONFIG_OF_SPI=y
442# CONFIG_PARPORT is not set 469# CONFIG_PARPORT is not set
443CONFIG_BLK_DEV=y 470CONFIG_BLK_DEV=y
444# CONFIG_BLK_DEV_FD is not set 471# CONFIG_BLK_DEV_FD is not set
472# CONFIG_MAC_FLOPPY is not set
445# CONFIG_BLK_CPQ_DA is not set 473# CONFIG_BLK_CPQ_DA is not set
446# CONFIG_BLK_CPQ_CISS_DA is not set 474# CONFIG_BLK_CPQ_CISS_DA is not set
447# CONFIG_BLK_DEV_DAC960 is not set 475# CONFIG_BLK_DEV_DAC960 is not set
@@ -458,18 +486,17 @@ CONFIG_BLK_DEV_RAM_SIZE=32768
458# CONFIG_BLK_DEV_XIP is not set 486# CONFIG_BLK_DEV_XIP is not set
459# CONFIG_CDROM_PKTCDVD is not set 487# CONFIG_CDROM_PKTCDVD is not set
460# CONFIG_ATA_OVER_ETH is not set 488# CONFIG_ATA_OVER_ETH is not set
489# CONFIG_BLK_DEV_HD is not set
461CONFIG_MISC_DEVICES=y 490CONFIG_MISC_DEVICES=y
462# CONFIG_PHANTOM is not set 491# CONFIG_PHANTOM is not set
463# CONFIG_EEPROM_93CX6 is not set 492# CONFIG_EEPROM_93CX6 is not set
464# CONFIG_SGI_IOC4 is not set 493# CONFIG_SGI_IOC4 is not set
465# CONFIG_TIFM_CORE is not set 494# CONFIG_TIFM_CORE is not set
466# CONFIG_ENCLOSURE_SERVICES is not set 495# CONFIG_ENCLOSURE_SERVICES is not set
496# CONFIG_HP_ILO is not set
467CONFIG_HAVE_IDE=y 497CONFIG_HAVE_IDE=y
468CONFIG_IDE=y 498CONFIG_IDE=y
469CONFIG_IDE_MAX_HWIFS=4
470# CONFIG_BLK_DEV_IDE is not set 499# CONFIG_BLK_DEV_IDE is not set
471# CONFIG_BLK_DEV_HD_ONLY is not set
472# CONFIG_BLK_DEV_HD is not set
473 500
474# 501#
475# SCSI device support 502# SCSI device support
@@ -545,7 +572,10 @@ CONFIG_SCSI_LOWLEVEL=y
545# CONFIG_SCSI_DC390T is not set 572# CONFIG_SCSI_DC390T is not set
546# CONFIG_SCSI_NSP32 is not set 573# CONFIG_SCSI_NSP32 is not set
547# CONFIG_SCSI_DEBUG is not set 574# CONFIG_SCSI_DEBUG is not set
575# CONFIG_SCSI_MESH is not set
576# CONFIG_SCSI_MAC53C94 is not set
548# CONFIG_SCSI_SRP is not set 577# CONFIG_SCSI_SRP is not set
578# CONFIG_SCSI_DH is not set
549CONFIG_ATA=y 579CONFIG_ATA=y
550# CONFIG_ATA_NONSTANDARD is not set 580# CONFIG_ATA_NONSTANDARD is not set
551CONFIG_SATA_PMP=y 581CONFIG_SATA_PMP=y
@@ -623,12 +653,15 @@ CONFIG_MD_RAID1=y
623# 653#
624# IEEE 1394 (FireWire) support 654# IEEE 1394 (FireWire) support
625# 655#
656
657#
658# Enable only one of the two stacks, unless you know what you are doing
659#
626# CONFIG_FIREWIRE is not set 660# CONFIG_FIREWIRE is not set
627# CONFIG_IEEE1394 is not set 661# CONFIG_IEEE1394 is not set
628# CONFIG_I2O is not set 662# CONFIG_I2O is not set
629# CONFIG_MACINTOSH_DRIVERS is not set 663# CONFIG_MACINTOSH_DRIVERS is not set
630CONFIG_NETDEVICES=y 664CONFIG_NETDEVICES=y
631# CONFIG_NETDEVICES_MULTIQUEUE is not set
632# CONFIG_DUMMY is not set 665# CONFIG_DUMMY is not set
633# CONFIG_BONDING is not set 666# CONFIG_BONDING is not set
634# CONFIG_MACVLAN is not set 667# CONFIG_MACVLAN is not set
@@ -659,7 +692,6 @@ CONFIG_NETDEV_1000=y
659# CONFIG_DL2K is not set 692# CONFIG_DL2K is not set
660# CONFIG_E1000 is not set 693# CONFIG_E1000 is not set
661# CONFIG_E1000E is not set 694# CONFIG_E1000E is not set
662# CONFIG_E1000E_ENABLED is not set
663# CONFIG_IP1000 is not set 695# CONFIG_IP1000 is not set
664# CONFIG_IGB is not set 696# CONFIG_IGB is not set
665# CONFIG_NS83820 is not set 697# CONFIG_NS83820 is not set
@@ -673,9 +705,10 @@ CONFIG_NETDEV_1000=y
673# CONFIG_TIGON3 is not set 705# CONFIG_TIGON3 is not set
674# CONFIG_BNX2 is not set 706# CONFIG_BNX2 is not set
675CONFIG_GIANFAR=y 707CONFIG_GIANFAR=y
676CONFIG_GFAR_NAPI=y 708# CONFIG_MV643XX_ETH is not set
677# CONFIG_QLA3XXX is not set 709# CONFIG_QLA3XXX is not set
678# CONFIG_ATL1 is not set 710# CONFIG_ATL1 is not set
711# CONFIG_ATL1E is not set
679CONFIG_NETDEV_10000=y 712CONFIG_NETDEV_10000=y
680# CONFIG_CHELSIO_T1 is not set 713# CONFIG_CHELSIO_T1 is not set
681# CONFIG_CHELSIO_T3 is not set 714# CONFIG_CHELSIO_T3 is not set
@@ -753,11 +786,14 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=4
753# CONFIG_SERIAL_UARTLITE is not set 786# CONFIG_SERIAL_UARTLITE is not set
754CONFIG_SERIAL_CORE=y 787CONFIG_SERIAL_CORE=y
755CONFIG_SERIAL_CORE_CONSOLE=y 788CONFIG_SERIAL_CORE_CONSOLE=y
789# CONFIG_SERIAL_PMACZILOG is not set
756# CONFIG_SERIAL_JSM is not set 790# CONFIG_SERIAL_JSM is not set
757# CONFIG_SERIAL_OF_PLATFORM is not set 791# CONFIG_SERIAL_OF_PLATFORM is not set
758CONFIG_UNIX98_PTYS=y 792CONFIG_UNIX98_PTYS=y
759CONFIG_LEGACY_PTYS=y 793CONFIG_LEGACY_PTYS=y
760CONFIG_LEGACY_PTY_COUNT=256 794CONFIG_LEGACY_PTY_COUNT=256
795# CONFIG_BRIQ_PANEL is not set
796# CONFIG_HVC_RTAS is not set
761# CONFIG_IPMI_HANDLER is not set 797# CONFIG_IPMI_HANDLER is not set
762CONFIG_HW_RANDOM=y 798CONFIG_HW_RANDOM=y
763# CONFIG_NVRAM is not set 799# CONFIG_NVRAM is not set
@@ -769,43 +805,70 @@ CONFIG_DEVPORT=y
769CONFIG_I2C=y 805CONFIG_I2C=y
770CONFIG_I2C_BOARDINFO=y 806CONFIG_I2C_BOARDINFO=y
771CONFIG_I2C_CHARDEV=y 807CONFIG_I2C_CHARDEV=y
808CONFIG_I2C_HELPER_AUTO=y
772 809
773# 810#
774# I2C Hardware Bus support 811# I2C Hardware Bus support
775# 812#
813
814#
815# PC SMBus host controller drivers
816#
776# CONFIG_I2C_ALI1535 is not set 817# CONFIG_I2C_ALI1535 is not set
777# CONFIG_I2C_ALI1563 is not set 818# CONFIG_I2C_ALI1563 is not set
778# CONFIG_I2C_ALI15X3 is not set 819# CONFIG_I2C_ALI15X3 is not set
779# CONFIG_I2C_AMD756 is not set 820# CONFIG_I2C_AMD756 is not set
780# CONFIG_I2C_AMD8111 is not set 821# CONFIG_I2C_AMD8111 is not set
781# CONFIG_I2C_I801 is not set 822# CONFIG_I2C_I801 is not set
782# CONFIG_I2C_I810 is not set 823# CONFIG_I2C_ISCH is not set
783# CONFIG_I2C_PIIX4 is not set 824# CONFIG_I2C_PIIX4 is not set
784CONFIG_I2C_MPC=y
785# CONFIG_I2C_NFORCE2 is not set 825# CONFIG_I2C_NFORCE2 is not set
786# CONFIG_I2C_OCORES is not set
787# CONFIG_I2C_PARPORT_LIGHT is not set
788# CONFIG_I2C_PROSAVAGE is not set
789# CONFIG_I2C_SAVAGE4 is not set
790# CONFIG_I2C_SIMTEC is not set
791# CONFIG_I2C_SIS5595 is not set 826# CONFIG_I2C_SIS5595 is not set
792# CONFIG_I2C_SIS630 is not set 827# CONFIG_I2C_SIS630 is not set
793# CONFIG_I2C_SIS96X is not set 828# CONFIG_I2C_SIS96X is not set
794# CONFIG_I2C_TAOS_EVM is not set
795# CONFIG_I2C_STUB is not set
796# CONFIG_I2C_TINY_USB is not set
797# CONFIG_I2C_VIA is not set 829# CONFIG_I2C_VIA is not set
798# CONFIG_I2C_VIAPRO is not set 830# CONFIG_I2C_VIAPRO is not set
831
832#
833# Mac SMBus host controller drivers
834#
835# CONFIG_I2C_HYDRA is not set
836CONFIG_I2C_POWERMAC=y
837
838#
839# I2C system bus drivers (mostly embedded / system-on-chip)
840#
841CONFIG_I2C_MPC=y
842# CONFIG_I2C_OCORES is not set
843# CONFIG_I2C_SIMTEC is not set
844
845#
846# External I2C/SMBus adapter drivers
847#
848# CONFIG_I2C_PARPORT_LIGHT is not set
849# CONFIG_I2C_TAOS_EVM is not set
850# CONFIG_I2C_TINY_USB is not set
851
852#
853# Graphics adapter I2C/DDC channel drivers
854#
799# CONFIG_I2C_VOODOO3 is not set 855# CONFIG_I2C_VOODOO3 is not set
856
857#
858# Other I2C/SMBus bus drivers
859#
800# CONFIG_I2C_PCA_PLATFORM is not set 860# CONFIG_I2C_PCA_PLATFORM is not set
861# CONFIG_I2C_STUB is not set
801 862
802# 863#
803# Miscellaneous I2C Chip support 864# Miscellaneous I2C Chip support
804# 865#
805# CONFIG_DS1682 is not set 866# CONFIG_DS1682 is not set
867# CONFIG_AT24 is not set
806# CONFIG_SENSORS_EEPROM is not set 868# CONFIG_SENSORS_EEPROM is not set
807CONFIG_SENSORS_PCF8574=y 869CONFIG_SENSORS_PCF8574=y
808# CONFIG_PCF8575 is not set 870# CONFIG_PCF8575 is not set
871# CONFIG_SENSORS_PCA9539 is not set
809# CONFIG_SENSORS_PCF8591 is not set 872# CONFIG_SENSORS_PCF8591 is not set
810# CONFIG_SENSORS_MAX6875 is not set 873# CONFIG_SENSORS_MAX6875 is not set
811# CONFIG_SENSORS_TSL2550 is not set 874# CONFIG_SENSORS_TSL2550 is not set
@@ -828,10 +891,13 @@ CONFIG_SPI_MPC83xx=y
828# CONFIG_SPI_AT25 is not set 891# CONFIG_SPI_AT25 is not set
829# CONFIG_SPI_SPIDEV is not set 892# CONFIG_SPI_SPIDEV is not set
830# CONFIG_SPI_TLE62X0 is not set 893# CONFIG_SPI_TLE62X0 is not set
894CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
895# CONFIG_GPIOLIB is not set
831# CONFIG_W1 is not set 896# CONFIG_W1 is not set
832# CONFIG_POWER_SUPPLY is not set 897# CONFIG_POWER_SUPPLY is not set
833# CONFIG_HWMON is not set 898# CONFIG_HWMON is not set
834# CONFIG_THERMAL is not set 899# CONFIG_THERMAL is not set
900# CONFIG_THERMAL_HWMON is not set
835CONFIG_WATCHDOG=y 901CONFIG_WATCHDOG=y
836# CONFIG_WATCHDOG_NOWAYOUT is not set 902# CONFIG_WATCHDOG_NOWAYOUT is not set
837 903
@@ -839,7 +905,9 @@ CONFIG_WATCHDOG=y
839# Watchdog Device Drivers 905# Watchdog Device Drivers
840# 906#
841# CONFIG_SOFT_WATCHDOG is not set 907# CONFIG_SOFT_WATCHDOG is not set
842CONFIG_83xx_WDT=y 908# CONFIG_ALIM7101_WDT is not set
909# CONFIG_8xxx_WDT is not set
910# CONFIG_WATCHDOG_RTAS is not set
843 911
844# 912#
845# PCI-based Watchdog Cards 913# PCI-based Watchdog Cards
@@ -861,8 +929,10 @@ CONFIG_SSB_POSSIBLE=y
861# 929#
862# Multifunction device drivers 930# Multifunction device drivers
863# 931#
932# CONFIG_MFD_CORE is not set
864# CONFIG_MFD_SM501 is not set 933# CONFIG_MFD_SM501 is not set
865# CONFIG_HTC_PASIC3 is not set 934# CONFIG_HTC_PASIC3 is not set
935# CONFIG_MFD_TMIO is not set
866 936
867# 937#
868# Multimedia devices 938# Multimedia devices
@@ -895,10 +965,6 @@ CONFIG_VIDEO_OUTPUT_CONTROL=m
895# Display device support 965# Display device support
896# 966#
897# CONFIG_DISPLAY_SUPPORT is not set 967# CONFIG_DISPLAY_SUPPORT is not set
898
899#
900# Sound
901#
902# CONFIG_SOUND is not set 968# CONFIG_SOUND is not set
903CONFIG_USB_SUPPORT=y 969CONFIG_USB_SUPPORT=y
904CONFIG_USB_ARCH_HAS_HCD=y 970CONFIG_USB_ARCH_HAS_HCD=y
@@ -917,6 +983,7 @@ CONFIG_USB_DEVICE_CLASS=y
917# CONFIG_USB_OTG is not set 983# CONFIG_USB_OTG is not set
918# CONFIG_USB_OTG_WHITELIST is not set 984# CONFIG_USB_OTG_WHITELIST is not set
919# CONFIG_USB_OTG_BLACKLIST_HUB is not set 985# CONFIG_USB_OTG_BLACKLIST_HUB is not set
986CONFIG_USB_MON=y
920 987
921# 988#
922# USB Host Controller Drivers 989# USB Host Controller Drivers
@@ -960,6 +1027,7 @@ CONFIG_USB_STORAGE=y
960# CONFIG_USB_STORAGE_JUMPSHOT is not set 1027# CONFIG_USB_STORAGE_JUMPSHOT is not set
961# CONFIG_USB_STORAGE_ALAUDA is not set 1028# CONFIG_USB_STORAGE_ALAUDA is not set
962# CONFIG_USB_STORAGE_KARMA is not set 1029# CONFIG_USB_STORAGE_KARMA is not set
1030# CONFIG_USB_STORAGE_SIERRA is not set
963# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set 1031# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
964# CONFIG_USB_LIBUSUAL is not set 1032# CONFIG_USB_LIBUSUAL is not set
965 1033
@@ -968,7 +1036,6 @@ CONFIG_USB_STORAGE=y
968# 1036#
969# CONFIG_USB_MDC800 is not set 1037# CONFIG_USB_MDC800 is not set
970# CONFIG_USB_MICROTEK is not set 1038# CONFIG_USB_MICROTEK is not set
971CONFIG_USB_MON=y
972 1039
973# 1040#
974# USB port drivers 1041# USB port drivers
@@ -981,7 +1048,6 @@ CONFIG_USB_MON=y
981# CONFIG_USB_EMI62 is not set 1048# CONFIG_USB_EMI62 is not set
982# CONFIG_USB_EMI26 is not set 1049# CONFIG_USB_EMI26 is not set
983# CONFIG_USB_ADUTUX is not set 1050# CONFIG_USB_ADUTUX is not set
984# CONFIG_USB_AUERSWALD is not set
985# CONFIG_USB_RIO500 is not set 1051# CONFIG_USB_RIO500 is not set
986# CONFIG_USB_LEGOTOWER is not set 1052# CONFIG_USB_LEGOTOWER is not set
987# CONFIG_USB_LCD is not set 1053# CONFIG_USB_LCD is not set
@@ -1035,10 +1101,13 @@ CONFIG_RTC_DRV_DS1307=y
1035# CONFIG_RTC_DRV_PCF8583 is not set 1101# CONFIG_RTC_DRV_PCF8583 is not set
1036# CONFIG_RTC_DRV_M41T80 is not set 1102# CONFIG_RTC_DRV_M41T80 is not set
1037# CONFIG_RTC_DRV_S35390A is not set 1103# CONFIG_RTC_DRV_S35390A is not set
1104# CONFIG_RTC_DRV_FM3130 is not set
1038 1105
1039# 1106#
1040# SPI RTC drivers 1107# SPI RTC drivers
1041# 1108#
1109# CONFIG_RTC_DRV_M41T94 is not set
1110# CONFIG_RTC_DRV_DS1305 is not set
1042# CONFIG_RTC_DRV_MAX6902 is not set 1111# CONFIG_RTC_DRV_MAX6902 is not set
1043# CONFIG_RTC_DRV_R9701 is not set 1112# CONFIG_RTC_DRV_R9701 is not set
1044# CONFIG_RTC_DRV_RS5C348 is not set 1113# CONFIG_RTC_DRV_RS5C348 is not set
@@ -1130,6 +1199,7 @@ CONFIG_TMPFS=y
1130# CONFIG_CRAMFS is not set 1199# CONFIG_CRAMFS is not set
1131# CONFIG_VXFS_FS is not set 1200# CONFIG_VXFS_FS is not set
1132# CONFIG_MINIX_FS is not set 1201# CONFIG_MINIX_FS is not set
1202# CONFIG_OMFS_FS is not set
1133# CONFIG_HPFS_FS is not set 1203# CONFIG_HPFS_FS is not set
1134# CONFIG_QNX4FS_FS is not set 1204# CONFIG_QNX4FS_FS is not set
1135# CONFIG_ROMFS_FS is not set 1205# CONFIG_ROMFS_FS is not set
@@ -1140,14 +1210,13 @@ CONFIG_NFS_FS=y
1140CONFIG_NFS_V3=y 1210CONFIG_NFS_V3=y
1141# CONFIG_NFS_V3_ACL is not set 1211# CONFIG_NFS_V3_ACL is not set
1142CONFIG_NFS_V4=y 1212CONFIG_NFS_V4=y
1143# CONFIG_NFSD is not set
1144CONFIG_ROOT_NFS=y 1213CONFIG_ROOT_NFS=y
1214# CONFIG_NFSD is not set
1145CONFIG_LOCKD=y 1215CONFIG_LOCKD=y
1146CONFIG_LOCKD_V4=y 1216CONFIG_LOCKD_V4=y
1147CONFIG_NFS_COMMON=y 1217CONFIG_NFS_COMMON=y
1148CONFIG_SUNRPC=y 1218CONFIG_SUNRPC=y
1149CONFIG_SUNRPC_GSS=y 1219CONFIG_SUNRPC_GSS=y
1150# CONFIG_SUNRPC_BIND34 is not set
1151CONFIG_RPCSEC_GSS_KRB5=y 1220CONFIG_RPCSEC_GSS_KRB5=y
1152# CONFIG_RPCSEC_GSS_SPKM3 is not set 1221# CONFIG_RPCSEC_GSS_SPKM3 is not set
1153# CONFIG_SMB_FS is not set 1222# CONFIG_SMB_FS is not set
@@ -1226,6 +1295,7 @@ CONFIG_BITREVERSE=y
1226# CONFIG_GENERIC_FIND_FIRST_BIT is not set 1295# CONFIG_GENERIC_FIND_FIRST_BIT is not set
1227# CONFIG_CRC_CCITT is not set 1296# CONFIG_CRC_CCITT is not set
1228# CONFIG_CRC16 is not set 1297# CONFIG_CRC16 is not set
1298CONFIG_CRC_T10DIF=y
1229# CONFIG_CRC_ITU_T is not set 1299# CONFIG_CRC_ITU_T is not set
1230CONFIG_CRC32=y 1300CONFIG_CRC32=y
1231# CONFIG_CRC7 is not set 1301# CONFIG_CRC7 is not set
@@ -1251,8 +1321,18 @@ CONFIG_FRAME_WARN=1024
1251# CONFIG_SLUB_DEBUG_ON is not set 1321# CONFIG_SLUB_DEBUG_ON is not set
1252# CONFIG_SLUB_STATS is not set 1322# CONFIG_SLUB_STATS is not set
1253# CONFIG_DEBUG_BUGVERBOSE is not set 1323# CONFIG_DEBUG_BUGVERBOSE is not set
1324# CONFIG_DEBUG_MEMORY_INIT is not set
1325# CONFIG_LATENCYTOP is not set
1326CONFIG_SYSCTL_SYSCALL_CHECK=y
1327CONFIG_HAVE_FTRACE=y
1328CONFIG_HAVE_DYNAMIC_FTRACE=y
1329# CONFIG_FTRACE is not set
1330# CONFIG_SCHED_TRACER is not set
1331# CONFIG_CONTEXT_SWITCH_TRACER is not set
1254# CONFIG_SAMPLES is not set 1332# CONFIG_SAMPLES is not set
1333CONFIG_HAVE_ARCH_KGDB=y
1255# CONFIG_IRQSTACKS is not set 1334# CONFIG_IRQSTACKS is not set
1335# CONFIG_BOOTX_TEXT is not set
1256# CONFIG_PPC_EARLY_DEBUG is not set 1336# CONFIG_PPC_EARLY_DEBUG is not set
1257 1337
1258# 1338#
@@ -1306,6 +1386,10 @@ CONFIG_CRYPTO_PCBC=m
1306# CONFIG_CRYPTO_MD4 is not set 1386# CONFIG_CRYPTO_MD4 is not set
1307CONFIG_CRYPTO_MD5=y 1387CONFIG_CRYPTO_MD5=y
1308# CONFIG_CRYPTO_MICHAEL_MIC is not set 1388# CONFIG_CRYPTO_MICHAEL_MIC is not set
1389# CONFIG_CRYPTO_RMD128 is not set
1390# CONFIG_CRYPTO_RMD160 is not set
1391# CONFIG_CRYPTO_RMD256 is not set
1392# CONFIG_CRYPTO_RMD320 is not set
1309# CONFIG_CRYPTO_SHA1 is not set 1393# CONFIG_CRYPTO_SHA1 is not set
1310# CONFIG_CRYPTO_SHA256 is not set 1394# CONFIG_CRYPTO_SHA256 is not set
1311# CONFIG_CRYPTO_SHA512 is not set 1395# CONFIG_CRYPTO_SHA512 is not set
@@ -1338,5 +1422,6 @@ CONFIG_CRYPTO_DES=y
1338# CONFIG_CRYPTO_LZO is not set 1422# CONFIG_CRYPTO_LZO is not set
1339CONFIG_CRYPTO_HW=y 1423CONFIG_CRYPTO_HW=y
1340# CONFIG_CRYPTO_DEV_HIFN_795X is not set 1424# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1425# CONFIG_CRYPTO_DEV_TALITOS is not set
1341# CONFIG_PPC_CLOCK is not set 1426# CONFIG_PPC_CLOCK is not set
1342# CONFIG_VIRTUALIZATION is not set 1427# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/configs/83xx/mpc834x_itxgp_defconfig b/arch/powerpc/configs/83xx/mpc834x_itxgp_defconfig
index fdac4845bad9..a8afa39d6f76 100644
--- a/arch/powerpc/configs/83xx/mpc834x_itxgp_defconfig
+++ b/arch/powerpc/configs/83xx/mpc834x_itxgp_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc5 3# Linux kernel version: 2.6.27-rc4
4# Mon Jun 9 08:52:26 2008 4# Thu Aug 21 00:52:21 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -16,6 +16,7 @@ CONFIG_6xx=y
16# CONFIG_E200 is not set 16# CONFIG_E200 is not set
17CONFIG_PPC_FPU=y 17CONFIG_PPC_FPU=y
18# CONFIG_FSL_EMB_PERFMON is not set 18# CONFIG_FSL_EMB_PERFMON is not set
19# CONFIG_ALTIVEC is not set
19CONFIG_PPC_STD_MMU=y 20CONFIG_PPC_STD_MMU=y
20CONFIG_PPC_STD_MMU_32=y 21CONFIG_PPC_STD_MMU_32=y
21# CONFIG_PPC_MM_SLICES is not set 22# CONFIG_PPC_MM_SLICES is not set
@@ -32,6 +33,7 @@ CONFIG_GENERIC_HARDIRQS=y
32# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set 33# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
33CONFIG_IRQ_PER_CPU=y 34CONFIG_IRQ_PER_CPU=y
34CONFIG_STACKTRACE_SUPPORT=y 35CONFIG_STACKTRACE_SUPPORT=y
36CONFIG_HAVE_LATENCYTOP_SUPPORT=y
35CONFIG_LOCKDEP_SUPPORT=y 37CONFIG_LOCKDEP_SUPPORT=y
36CONFIG_RWSEM_XCHGADD_ALGORITHM=y 38CONFIG_RWSEM_XCHGADD_ALGORITHM=y
37CONFIG_ARCH_HAS_ILOG2_U32=y 39CONFIG_ARCH_HAS_ILOG2_U32=y
@@ -51,6 +53,9 @@ CONFIG_PPC_UDBG_16550=y
51CONFIG_AUDIT_ARCH=y 53CONFIG_AUDIT_ARCH=y
52CONFIG_GENERIC_BUG=y 54CONFIG_GENERIC_BUG=y
53CONFIG_DEFAULT_UIMAGE=y 55CONFIG_DEFAULT_UIMAGE=y
56CONFIG_HIBERNATE_32=y
57CONFIG_ARCH_HIBERNATION_POSSIBLE=y
58CONFIG_ARCH_SUSPEND_POSSIBLE=y
54# CONFIG_PPC_DCR_NATIVE is not set 59# CONFIG_PPC_DCR_NATIVE is not set
55# CONFIG_PPC_DCR_MMIO is not set 60# CONFIG_PPC_DCR_MMIO is not set
56CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 61CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
@@ -88,12 +93,12 @@ CONFIG_INITRAMFS_SOURCE=""
88CONFIG_SYSCTL=y 93CONFIG_SYSCTL=y
89CONFIG_EMBEDDED=y 94CONFIG_EMBEDDED=y
90CONFIG_SYSCTL_SYSCALL=y 95CONFIG_SYSCTL_SYSCALL=y
91CONFIG_SYSCTL_SYSCALL_CHECK=y
92# CONFIG_KALLSYMS is not set 96# CONFIG_KALLSYMS is not set
93CONFIG_HOTPLUG=y 97CONFIG_HOTPLUG=y
94CONFIG_PRINTK=y 98CONFIG_PRINTK=y
95CONFIG_BUG=y 99CONFIG_BUG=y
96CONFIG_ELF_CORE=y 100CONFIG_ELF_CORE=y
101CONFIG_PCSPKR_PLATFORM=y
97CONFIG_COMPAT_BRK=y 102CONFIG_COMPAT_BRK=y
98CONFIG_BASE_FULL=y 103CONFIG_BASE_FULL=y
99CONFIG_FUTEX=y 104CONFIG_FUTEX=y
@@ -111,10 +116,16 @@ CONFIG_SLUB=y
111# CONFIG_PROFILING is not set 116# CONFIG_PROFILING is not set
112# CONFIG_MARKERS is not set 117# CONFIG_MARKERS is not set
113CONFIG_HAVE_OPROFILE=y 118CONFIG_HAVE_OPROFILE=y
119CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
120CONFIG_HAVE_IOREMAP_PROT=y
114CONFIG_HAVE_KPROBES=y 121CONFIG_HAVE_KPROBES=y
115CONFIG_HAVE_KRETPROBES=y 122CONFIG_HAVE_KRETPROBES=y
123CONFIG_HAVE_ARCH_TRACEHOOK=y
116# CONFIG_HAVE_DMA_ATTRS is not set 124# CONFIG_HAVE_DMA_ATTRS is not set
125# CONFIG_USE_GENERIC_SMP_HELPERS is not set
126# CONFIG_HAVE_CLK is not set
117CONFIG_PROC_PAGE_MONITOR=y 127CONFIG_PROC_PAGE_MONITOR=y
128# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
118CONFIG_SLABINFO=y 129CONFIG_SLABINFO=y
119CONFIG_RT_MUTEXES=y 130CONFIG_RT_MUTEXES=y
120# CONFIG_TINY_SHMEM is not set 131# CONFIG_TINY_SHMEM is not set
@@ -125,12 +136,13 @@ CONFIG_MODULE_UNLOAD=y
125# CONFIG_MODULE_FORCE_UNLOAD is not set 136# CONFIG_MODULE_FORCE_UNLOAD is not set
126# CONFIG_MODVERSIONS is not set 137# CONFIG_MODVERSIONS is not set
127# CONFIG_MODULE_SRCVERSION_ALL is not set 138# CONFIG_MODULE_SRCVERSION_ALL is not set
128# CONFIG_KMOD is not set 139CONFIG_KMOD=y
129CONFIG_BLOCK=y 140CONFIG_BLOCK=y
130# CONFIG_LBD is not set 141# CONFIG_LBD is not set
131# CONFIG_BLK_DEV_IO_TRACE is not set 142# CONFIG_BLK_DEV_IO_TRACE is not set
132# CONFIG_LSF is not set 143# CONFIG_LSF is not set
133# CONFIG_BLK_DEV_BSG is not set 144# CONFIG_BLK_DEV_BSG is not set
145# CONFIG_BLK_DEV_INTEGRITY is not set
134 146
135# 147#
136# IO Schedulers 148# IO Schedulers
@@ -149,37 +161,49 @@ CONFIG_CLASSIC_RCU=y
149# 161#
150# Platform support 162# Platform support
151# 163#
152# CONFIG_PPC_MULTIPLATFORM is not set 164CONFIG_PPC_MULTIPLATFORM=y
153# CONFIG_PPC_82xx is not set 165CONFIG_CLASSIC32=y
154CONFIG_PPC_83xx=y 166CONFIG_PPC_CHRP=y
155# CONFIG_PPC_86xx is not set 167# CONFIG_MPC5121_ADS is not set
156# CONFIG_PPC_MPC512x is not set 168# CONFIG_MPC5121_GENERIC is not set
157# CONFIG_PPC_MPC5121 is not set 169# CONFIG_PPC_MPC52xx is not set
170CONFIG_PPC_PMAC=y
158# CONFIG_PPC_CELL is not set 171# CONFIG_PPC_CELL is not set
159# CONFIG_PPC_CELL_NATIVE is not set 172# CONFIG_PPC_CELL_NATIVE is not set
173# CONFIG_PPC_82xx is not set
160# CONFIG_PQ2ADS is not set 174# CONFIG_PQ2ADS is not set
161CONFIG_MPC83xx=y 175CONFIG_PPC_83xx=y
162# CONFIG_MPC831x_RDB is not set 176# CONFIG_MPC831x_RDB is not set
163# CONFIG_MPC832x_MDS is not set 177# CONFIG_MPC832x_MDS is not set
164# CONFIG_MPC832x_RDB is not set 178# CONFIG_MPC832x_RDB is not set
165# CONFIG_MPC834x_MDS is not set 179# CONFIG_MPC834x_MDS is not set
166CONFIG_MPC834x_ITX=y 180CONFIG_MPC834x_ITX=y
167# CONFIG_MPC836x_MDS is not set 181# CONFIG_MPC836x_MDS is not set
182# CONFIG_MPC836x_RDK is not set
168# CONFIG_MPC837x_MDS is not set 183# CONFIG_MPC837x_MDS is not set
169# CONFIG_MPC837x_RDB is not set 184# CONFIG_MPC837x_RDB is not set
170# CONFIG_SBC834x is not set 185# CONFIG_SBC834x is not set
186# CONFIG_ASP834x is not set
171CONFIG_PPC_MPC834x=y 187CONFIG_PPC_MPC834x=y
188# CONFIG_PPC_86xx is not set
189# CONFIG_EMBEDDED6xx is not set
190CONFIG_PPC_NATIVE=y
191# CONFIG_UDBG_RTAS_CONSOLE is not set
172CONFIG_IPIC=y 192CONFIG_IPIC=y
173# CONFIG_MPIC is not set 193CONFIG_MPIC=y
174# CONFIG_MPIC_WEIRD is not set 194# CONFIG_MPIC_WEIRD is not set
175# CONFIG_PPC_I8259 is not set 195CONFIG_PPC_I8259=y
176# CONFIG_PPC_RTAS is not set 196CONFIG_PPC_RTAS=y
197# CONFIG_RTAS_ERROR_LOGGING is not set
198CONFIG_RTAS_PROC=y
177# CONFIG_MMIO_NVRAM is not set 199# CONFIG_MMIO_NVRAM is not set
178# CONFIG_PPC_MPC106 is not set 200CONFIG_PPC_MPC106=y
179# CONFIG_PPC_970_NAP is not set 201# CONFIG_PPC_970_NAP is not set
180# CONFIG_PPC_INDIRECT_IO is not set 202# CONFIG_PPC_INDIRECT_IO is not set
181# CONFIG_GENERIC_IOMAP is not set 203# CONFIG_GENERIC_IOMAP is not set
182# CONFIG_CPU_FREQ is not set 204# CONFIG_CPU_FREQ is not set
205# CONFIG_PPC601_SYNC_FIX is not set
206# CONFIG_TAU is not set
183# CONFIG_FSL_ULI1575 is not set 207# CONFIG_FSL_ULI1575 is not set
184 208
185# 209#
@@ -195,7 +219,7 @@ CONFIG_HZ_250=y
195# CONFIG_HZ_300 is not set 219# CONFIG_HZ_300 is not set
196# CONFIG_HZ_1000 is not set 220# CONFIG_HZ_1000 is not set
197CONFIG_HZ=250 221CONFIG_HZ=250
198# CONFIG_SCHED_HRTICK is not set 222CONFIG_SCHED_HRTICK=y
199CONFIG_PREEMPT_NONE=y 223CONFIG_PREEMPT_NONE=y
200# CONFIG_PREEMPT_VOLUNTARY is not set 224# CONFIG_PREEMPT_VOLUNTARY is not set
201# CONFIG_PREEMPT is not set 225# CONFIG_PREEMPT is not set
@@ -205,6 +229,7 @@ CONFIG_BINFMT_ELF=y
205CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y 229CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
206CONFIG_ARCH_HAS_WALK_MEMORY=y 230CONFIG_ARCH_HAS_WALK_MEMORY=y
207CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y 231CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
232# CONFIG_KEXEC is not set
208CONFIG_ARCH_FLATMEM_ENABLE=y 233CONFIG_ARCH_FLATMEM_ENABLE=y
209CONFIG_ARCH_POPULATES_NODE_MAP=y 234CONFIG_ARCH_POPULATES_NODE_MAP=y
210CONFIG_SELECT_MEMORY_MODEL=y 235CONFIG_SELECT_MEMORY_MODEL=y
@@ -217,6 +242,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
217# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set 242# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
218CONFIG_PAGEFLAGS_EXTENDED=y 243CONFIG_PAGEFLAGS_EXTENDED=y
219CONFIG_SPLIT_PTLOCK_CPUS=4 244CONFIG_SPLIT_PTLOCK_CPUS=4
245CONFIG_MIGRATION=y
220# CONFIG_RESOURCES_64BIT is not set 246# CONFIG_RESOURCES_64BIT is not set
221CONFIG_ZONE_DMA_FLAG=1 247CONFIG_ZONE_DMA_FLAG=1
222CONFIG_BOUNCE=y 248CONFIG_BOUNCE=y
@@ -224,6 +250,7 @@ CONFIG_VIRT_TO_BUS=y
224CONFIG_FORCE_MAX_ZONEORDER=11 250CONFIG_FORCE_MAX_ZONEORDER=11
225CONFIG_PROC_DEVICETREE=y 251CONFIG_PROC_DEVICETREE=y
226# CONFIG_CMDLINE_BOOL is not set 252# CONFIG_CMDLINE_BOOL is not set
253CONFIG_EXTRA_TARGETS=""
227# CONFIG_PM is not set 254# CONFIG_PM is not set
228CONFIG_SECCOMP=y 255CONFIG_SECCOMP=y
229CONFIG_ISA_DMA_API=y 256CONFIG_ISA_DMA_API=y
@@ -231,10 +258,13 @@ CONFIG_ISA_DMA_API=y
231# 258#
232# Bus options 259# Bus options
233# 260#
261# CONFIG_ISA is not set
234CONFIG_ZONE_DMA=y 262CONFIG_ZONE_DMA=y
235CONFIG_GENERIC_ISA_DMA=y 263CONFIG_GENERIC_ISA_DMA=y
236CONFIG_PPC_INDIRECT_PCI=y 264CONFIG_PPC_INDIRECT_PCI=y
237CONFIG_FSL_SOC=y 265CONFIG_FSL_SOC=y
266CONFIG_FSL_PCI=y
267CONFIG_PPC_PCI_CHOICE=y
238CONFIG_PCI=y 268CONFIG_PCI=y
239CONFIG_PCI_DOMAINS=y 269CONFIG_PCI_DOMAINS=y
240CONFIG_PCI_SYSCALL=y 270CONFIG_PCI_SYSCALL=y
@@ -259,10 +289,6 @@ CONFIG_PAGE_OFFSET=0xc0000000
259CONFIG_KERNEL_START=0xc0000000 289CONFIG_KERNEL_START=0xc0000000
260CONFIG_PHYSICAL_START=0x00000000 290CONFIG_PHYSICAL_START=0x00000000
261CONFIG_TASK_SIZE=0xc0000000 291CONFIG_TASK_SIZE=0xc0000000
262
263#
264# Networking
265#
266CONFIG_NET=y 292CONFIG_NET=y
267 293
268# 294#
@@ -439,9 +465,11 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=2
439# CONFIG_MTD_UBI is not set 465# CONFIG_MTD_UBI is not set
440CONFIG_OF_DEVICE=y 466CONFIG_OF_DEVICE=y
441CONFIG_OF_I2C=y 467CONFIG_OF_I2C=y
468CONFIG_OF_SPI=y
442# CONFIG_PARPORT is not set 469# CONFIG_PARPORT is not set
443CONFIG_BLK_DEV=y 470CONFIG_BLK_DEV=y
444# CONFIG_BLK_DEV_FD is not set 471# CONFIG_BLK_DEV_FD is not set
472# CONFIG_MAC_FLOPPY is not set
445# CONFIG_BLK_CPQ_DA is not set 473# CONFIG_BLK_CPQ_DA is not set
446# CONFIG_BLK_CPQ_CISS_DA is not set 474# CONFIG_BLK_CPQ_CISS_DA is not set
447# CONFIG_BLK_DEV_DAC960 is not set 475# CONFIG_BLK_DEV_DAC960 is not set
@@ -458,12 +486,14 @@ CONFIG_BLK_DEV_RAM_SIZE=32768
458# CONFIG_BLK_DEV_XIP is not set 486# CONFIG_BLK_DEV_XIP is not set
459# CONFIG_CDROM_PKTCDVD is not set 487# CONFIG_CDROM_PKTCDVD is not set
460# CONFIG_ATA_OVER_ETH is not set 488# CONFIG_ATA_OVER_ETH is not set
489# CONFIG_BLK_DEV_HD is not set
461CONFIG_MISC_DEVICES=y 490CONFIG_MISC_DEVICES=y
462# CONFIG_PHANTOM is not set 491# CONFIG_PHANTOM is not set
463# CONFIG_EEPROM_93CX6 is not set 492# CONFIG_EEPROM_93CX6 is not set
464# CONFIG_SGI_IOC4 is not set 493# CONFIG_SGI_IOC4 is not set
465# CONFIG_TIFM_CORE is not set 494# CONFIG_TIFM_CORE is not set
466# CONFIG_ENCLOSURE_SERVICES is not set 495# CONFIG_ENCLOSURE_SERVICES is not set
496# CONFIG_HP_ILO is not set
467CONFIG_HAVE_IDE=y 497CONFIG_HAVE_IDE=y
468# CONFIG_IDE is not set 498# CONFIG_IDE is not set
469 499
@@ -540,7 +570,10 @@ CONFIG_SCSI_LOWLEVEL=y
540# CONFIG_SCSI_DC390T is not set 570# CONFIG_SCSI_DC390T is not set
541# CONFIG_SCSI_NSP32 is not set 571# CONFIG_SCSI_NSP32 is not set
542# CONFIG_SCSI_DEBUG is not set 572# CONFIG_SCSI_DEBUG is not set
573# CONFIG_SCSI_MESH is not set
574# CONFIG_SCSI_MAC53C94 is not set
543# CONFIG_SCSI_SRP is not set 575# CONFIG_SCSI_SRP is not set
576# CONFIG_SCSI_DH is not set
544# CONFIG_ATA is not set 577# CONFIG_ATA is not set
545# CONFIG_MD is not set 578# CONFIG_MD is not set
546# CONFIG_FUSION is not set 579# CONFIG_FUSION is not set
@@ -548,12 +581,15 @@ CONFIG_SCSI_LOWLEVEL=y
548# 581#
549# IEEE 1394 (FireWire) support 582# IEEE 1394 (FireWire) support
550# 583#
584
585#
586# Enable only one of the two stacks, unless you know what you are doing
587#
551# CONFIG_FIREWIRE is not set 588# CONFIG_FIREWIRE is not set
552# CONFIG_IEEE1394 is not set 589# CONFIG_IEEE1394 is not set
553# CONFIG_I2O is not set 590# CONFIG_I2O is not set
554# CONFIG_MACINTOSH_DRIVERS is not set 591# CONFIG_MACINTOSH_DRIVERS is not set
555CONFIG_NETDEVICES=y 592CONFIG_NETDEVICES=y
556# CONFIG_NETDEVICES_MULTIQUEUE is not set
557# CONFIG_DUMMY is not set 593# CONFIG_DUMMY is not set
558# CONFIG_BONDING is not set 594# CONFIG_BONDING is not set
559# CONFIG_MACVLAN is not set 595# CONFIG_MACVLAN is not set
@@ -584,7 +620,6 @@ CONFIG_NETDEV_1000=y
584# CONFIG_DL2K is not set 620# CONFIG_DL2K is not set
585# CONFIG_E1000 is not set 621# CONFIG_E1000 is not set
586# CONFIG_E1000E is not set 622# CONFIG_E1000E is not set
587# CONFIG_E1000E_ENABLED is not set
588# CONFIG_IP1000 is not set 623# CONFIG_IP1000 is not set
589# CONFIG_IGB is not set 624# CONFIG_IGB is not set
590# CONFIG_NS83820 is not set 625# CONFIG_NS83820 is not set
@@ -598,9 +633,10 @@ CONFIG_NETDEV_1000=y
598# CONFIG_TIGON3 is not set 633# CONFIG_TIGON3 is not set
599# CONFIG_BNX2 is not set 634# CONFIG_BNX2 is not set
600CONFIG_GIANFAR=y 635CONFIG_GIANFAR=y
601CONFIG_GFAR_NAPI=y 636# CONFIG_MV643XX_ETH is not set
602# CONFIG_QLA3XXX is not set 637# CONFIG_QLA3XXX is not set
603# CONFIG_ATL1 is not set 638# CONFIG_ATL1 is not set
639# CONFIG_ATL1E is not set
604CONFIG_NETDEV_10000=y 640CONFIG_NETDEV_10000=y
605# CONFIG_CHELSIO_T1 is not set 641# CONFIG_CHELSIO_T1 is not set
606# CONFIG_CHELSIO_T3 is not set 642# CONFIG_CHELSIO_T3 is not set
@@ -678,11 +714,14 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=4
678# CONFIG_SERIAL_UARTLITE is not set 714# CONFIG_SERIAL_UARTLITE is not set
679CONFIG_SERIAL_CORE=y 715CONFIG_SERIAL_CORE=y
680CONFIG_SERIAL_CORE_CONSOLE=y 716CONFIG_SERIAL_CORE_CONSOLE=y
717# CONFIG_SERIAL_PMACZILOG is not set
681# CONFIG_SERIAL_JSM is not set 718# CONFIG_SERIAL_JSM is not set
682# CONFIG_SERIAL_OF_PLATFORM is not set 719# CONFIG_SERIAL_OF_PLATFORM is not set
683CONFIG_UNIX98_PTYS=y 720CONFIG_UNIX98_PTYS=y
684CONFIG_LEGACY_PTYS=y 721CONFIG_LEGACY_PTYS=y
685CONFIG_LEGACY_PTY_COUNT=256 722CONFIG_LEGACY_PTY_COUNT=256
723# CONFIG_BRIQ_PANEL is not set
724# CONFIG_HVC_RTAS is not set
686# CONFIG_IPMI_HANDLER is not set 725# CONFIG_IPMI_HANDLER is not set
687CONFIG_HW_RANDOM=y 726CONFIG_HW_RANDOM=y
688# CONFIG_NVRAM is not set 727# CONFIG_NVRAM is not set
@@ -694,43 +733,70 @@ CONFIG_DEVPORT=y
694CONFIG_I2C=y 733CONFIG_I2C=y
695CONFIG_I2C_BOARDINFO=y 734CONFIG_I2C_BOARDINFO=y
696CONFIG_I2C_CHARDEV=y 735CONFIG_I2C_CHARDEV=y
736CONFIG_I2C_HELPER_AUTO=y
697 737
698# 738#
699# I2C Hardware Bus support 739# I2C Hardware Bus support
700# 740#
741
742#
743# PC SMBus host controller drivers
744#
701# CONFIG_I2C_ALI1535 is not set 745# CONFIG_I2C_ALI1535 is not set
702# CONFIG_I2C_ALI1563 is not set 746# CONFIG_I2C_ALI1563 is not set
703# CONFIG_I2C_ALI15X3 is not set 747# CONFIG_I2C_ALI15X3 is not set
704# CONFIG_I2C_AMD756 is not set 748# CONFIG_I2C_AMD756 is not set
705# CONFIG_I2C_AMD8111 is not set 749# CONFIG_I2C_AMD8111 is not set
706# CONFIG_I2C_I801 is not set 750# CONFIG_I2C_I801 is not set
707# CONFIG_I2C_I810 is not set 751# CONFIG_I2C_ISCH is not set
708# CONFIG_I2C_PIIX4 is not set 752# CONFIG_I2C_PIIX4 is not set
709CONFIG_I2C_MPC=y
710# CONFIG_I2C_NFORCE2 is not set 753# CONFIG_I2C_NFORCE2 is not set
711# CONFIG_I2C_OCORES is not set
712# CONFIG_I2C_PARPORT_LIGHT is not set
713# CONFIG_I2C_PROSAVAGE is not set
714# CONFIG_I2C_SAVAGE4 is not set
715# CONFIG_I2C_SIMTEC is not set
716# CONFIG_I2C_SIS5595 is not set 754# CONFIG_I2C_SIS5595 is not set
717# CONFIG_I2C_SIS630 is not set 755# CONFIG_I2C_SIS630 is not set
718# CONFIG_I2C_SIS96X is not set 756# CONFIG_I2C_SIS96X is not set
719# CONFIG_I2C_TAOS_EVM is not set
720# CONFIG_I2C_STUB is not set
721# CONFIG_I2C_TINY_USB is not set
722# CONFIG_I2C_VIA is not set 757# CONFIG_I2C_VIA is not set
723# CONFIG_I2C_VIAPRO is not set 758# CONFIG_I2C_VIAPRO is not set
759
760#
761# Mac SMBus host controller drivers
762#
763# CONFIG_I2C_HYDRA is not set
764CONFIG_I2C_POWERMAC=y
765
766#
767# I2C system bus drivers (mostly embedded / system-on-chip)
768#
769CONFIG_I2C_MPC=y
770# CONFIG_I2C_OCORES is not set
771# CONFIG_I2C_SIMTEC is not set
772
773#
774# External I2C/SMBus adapter drivers
775#
776# CONFIG_I2C_PARPORT_LIGHT is not set
777# CONFIG_I2C_TAOS_EVM is not set
778# CONFIG_I2C_TINY_USB is not set
779
780#
781# Graphics adapter I2C/DDC channel drivers
782#
724# CONFIG_I2C_VOODOO3 is not set 783# CONFIG_I2C_VOODOO3 is not set
784
785#
786# Other I2C/SMBus bus drivers
787#
725# CONFIG_I2C_PCA_PLATFORM is not set 788# CONFIG_I2C_PCA_PLATFORM is not set
789# CONFIG_I2C_STUB is not set
726 790
727# 791#
728# Miscellaneous I2C Chip support 792# Miscellaneous I2C Chip support
729# 793#
730# CONFIG_DS1682 is not set 794# CONFIG_DS1682 is not set
795# CONFIG_AT24 is not set
731# CONFIG_SENSORS_EEPROM is not set 796# CONFIG_SENSORS_EEPROM is not set
732CONFIG_SENSORS_PCF8574=y 797CONFIG_SENSORS_PCF8574=y
733# CONFIG_PCF8575 is not set 798# CONFIG_PCF8575 is not set
799# CONFIG_SENSORS_PCA9539 is not set
734# CONFIG_SENSORS_PCF8591 is not set 800# CONFIG_SENSORS_PCF8591 is not set
735# CONFIG_SENSORS_MAX6875 is not set 801# CONFIG_SENSORS_MAX6875 is not set
736# CONFIG_SENSORS_TSL2550 is not set 802# CONFIG_SENSORS_TSL2550 is not set
@@ -753,10 +819,13 @@ CONFIG_SPI_MPC83xx=y
753# CONFIG_SPI_AT25 is not set 819# CONFIG_SPI_AT25 is not set
754# CONFIG_SPI_SPIDEV is not set 820# CONFIG_SPI_SPIDEV is not set
755# CONFIG_SPI_TLE62X0 is not set 821# CONFIG_SPI_TLE62X0 is not set
822CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
823# CONFIG_GPIOLIB is not set
756# CONFIG_W1 is not set 824# CONFIG_W1 is not set
757# CONFIG_POWER_SUPPLY is not set 825# CONFIG_POWER_SUPPLY is not set
758# CONFIG_HWMON is not set 826# CONFIG_HWMON is not set
759# CONFIG_THERMAL is not set 827# CONFIG_THERMAL is not set
828# CONFIG_THERMAL_HWMON is not set
760CONFIG_WATCHDOG=y 829CONFIG_WATCHDOG=y
761# CONFIG_WATCHDOG_NOWAYOUT is not set 830# CONFIG_WATCHDOG_NOWAYOUT is not set
762 831
@@ -764,7 +833,9 @@ CONFIG_WATCHDOG=y
764# Watchdog Device Drivers 833# Watchdog Device Drivers
765# 834#
766# CONFIG_SOFT_WATCHDOG is not set 835# CONFIG_SOFT_WATCHDOG is not set
767CONFIG_83xx_WDT=y 836# CONFIG_ALIM7101_WDT is not set
837# CONFIG_8xxx_WDT is not set
838# CONFIG_WATCHDOG_RTAS is not set
768 839
769# 840#
770# PCI-based Watchdog Cards 841# PCI-based Watchdog Cards
@@ -786,8 +857,10 @@ CONFIG_SSB_POSSIBLE=y
786# 857#
787# Multifunction device drivers 858# Multifunction device drivers
788# 859#
860# CONFIG_MFD_CORE is not set
789# CONFIG_MFD_SM501 is not set 861# CONFIG_MFD_SM501 is not set
790# CONFIG_HTC_PASIC3 is not set 862# CONFIG_HTC_PASIC3 is not set
863# CONFIG_MFD_TMIO is not set
791 864
792# 865#
793# Multimedia devices 866# Multimedia devices
@@ -820,10 +893,6 @@ CONFIG_VIDEO_OUTPUT_CONTROL=m
820# Display device support 893# Display device support
821# 894#
822# CONFIG_DISPLAY_SUPPORT is not set 895# CONFIG_DISPLAY_SUPPORT is not set
823
824#
825# Sound
826#
827# CONFIG_SOUND is not set 896# CONFIG_SOUND is not set
828CONFIG_USB_SUPPORT=y 897CONFIG_USB_SUPPORT=y
829CONFIG_USB_ARCH_HAS_HCD=y 898CONFIG_USB_ARCH_HAS_HCD=y
@@ -842,6 +911,7 @@ CONFIG_USB_DEVICE_CLASS=y
842# CONFIG_USB_OTG is not set 911# CONFIG_USB_OTG is not set
843# CONFIG_USB_OTG_WHITELIST is not set 912# CONFIG_USB_OTG_WHITELIST is not set
844# CONFIG_USB_OTG_BLACKLIST_HUB is not set 913# CONFIG_USB_OTG_BLACKLIST_HUB is not set
914CONFIG_USB_MON=y
845 915
846# 916#
847# USB Host Controller Drivers 917# USB Host Controller Drivers
@@ -885,6 +955,7 @@ CONFIG_USB_STORAGE=y
885# CONFIG_USB_STORAGE_JUMPSHOT is not set 955# CONFIG_USB_STORAGE_JUMPSHOT is not set
886# CONFIG_USB_STORAGE_ALAUDA is not set 956# CONFIG_USB_STORAGE_ALAUDA is not set
887# CONFIG_USB_STORAGE_KARMA is not set 957# CONFIG_USB_STORAGE_KARMA is not set
958# CONFIG_USB_STORAGE_SIERRA is not set
888# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set 959# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
889# CONFIG_USB_LIBUSUAL is not set 960# CONFIG_USB_LIBUSUAL is not set
890 961
@@ -893,7 +964,6 @@ CONFIG_USB_STORAGE=y
893# 964#
894# CONFIG_USB_MDC800 is not set 965# CONFIG_USB_MDC800 is not set
895# CONFIG_USB_MICROTEK is not set 966# CONFIG_USB_MICROTEK is not set
896CONFIG_USB_MON=y
897 967
898# 968#
899# USB port drivers 969# USB port drivers
@@ -906,7 +976,6 @@ CONFIG_USB_MON=y
906# CONFIG_USB_EMI62 is not set 976# CONFIG_USB_EMI62 is not set
907# CONFIG_USB_EMI26 is not set 977# CONFIG_USB_EMI26 is not set
908# CONFIG_USB_ADUTUX is not set 978# CONFIG_USB_ADUTUX is not set
909# CONFIG_USB_AUERSWALD is not set
910# CONFIG_USB_RIO500 is not set 979# CONFIG_USB_RIO500 is not set
911# CONFIG_USB_LEGOTOWER is not set 980# CONFIG_USB_LEGOTOWER is not set
912# CONFIG_USB_LCD is not set 981# CONFIG_USB_LCD is not set
@@ -959,10 +1028,13 @@ CONFIG_RTC_DRV_DS1307=y
959# CONFIG_RTC_DRV_PCF8583 is not set 1028# CONFIG_RTC_DRV_PCF8583 is not set
960# CONFIG_RTC_DRV_M41T80 is not set 1029# CONFIG_RTC_DRV_M41T80 is not set
961# CONFIG_RTC_DRV_S35390A is not set 1030# CONFIG_RTC_DRV_S35390A is not set
1031# CONFIG_RTC_DRV_FM3130 is not set
962 1032
963# 1033#
964# SPI RTC drivers 1034# SPI RTC drivers
965# 1035#
1036# CONFIG_RTC_DRV_M41T94 is not set
1037# CONFIG_RTC_DRV_DS1305 is not set
966# CONFIG_RTC_DRV_MAX6902 is not set 1038# CONFIG_RTC_DRV_MAX6902 is not set
967# CONFIG_RTC_DRV_R9701 is not set 1039# CONFIG_RTC_DRV_R9701 is not set
968# CONFIG_RTC_DRV_RS5C348 is not set 1040# CONFIG_RTC_DRV_RS5C348 is not set
@@ -1054,6 +1126,7 @@ CONFIG_TMPFS=y
1054# CONFIG_CRAMFS is not set 1126# CONFIG_CRAMFS is not set
1055# CONFIG_VXFS_FS is not set 1127# CONFIG_VXFS_FS is not set
1056# CONFIG_MINIX_FS is not set 1128# CONFIG_MINIX_FS is not set
1129# CONFIG_OMFS_FS is not set
1057# CONFIG_HPFS_FS is not set 1130# CONFIG_HPFS_FS is not set
1058# CONFIG_QNX4FS_FS is not set 1131# CONFIG_QNX4FS_FS is not set
1059# CONFIG_ROMFS_FS is not set 1132# CONFIG_ROMFS_FS is not set
@@ -1064,14 +1137,13 @@ CONFIG_NFS_FS=y
1064CONFIG_NFS_V3=y 1137CONFIG_NFS_V3=y
1065# CONFIG_NFS_V3_ACL is not set 1138# CONFIG_NFS_V3_ACL is not set
1066CONFIG_NFS_V4=y 1139CONFIG_NFS_V4=y
1067# CONFIG_NFSD is not set
1068CONFIG_ROOT_NFS=y 1140CONFIG_ROOT_NFS=y
1141# CONFIG_NFSD is not set
1069CONFIG_LOCKD=y 1142CONFIG_LOCKD=y
1070CONFIG_LOCKD_V4=y 1143CONFIG_LOCKD_V4=y
1071CONFIG_NFS_COMMON=y 1144CONFIG_NFS_COMMON=y
1072CONFIG_SUNRPC=y 1145CONFIG_SUNRPC=y
1073CONFIG_SUNRPC_GSS=y 1146CONFIG_SUNRPC_GSS=y
1074# CONFIG_SUNRPC_BIND34 is not set
1075CONFIG_RPCSEC_GSS_KRB5=y 1147CONFIG_RPCSEC_GSS_KRB5=y
1076# CONFIG_RPCSEC_GSS_SPKM3 is not set 1148# CONFIG_RPCSEC_GSS_SPKM3 is not set
1077# CONFIG_SMB_FS is not set 1149# CONFIG_SMB_FS is not set
@@ -1150,6 +1222,7 @@ CONFIG_BITREVERSE=y
1150# CONFIG_GENERIC_FIND_FIRST_BIT is not set 1222# CONFIG_GENERIC_FIND_FIRST_BIT is not set
1151# CONFIG_CRC_CCITT is not set 1223# CONFIG_CRC_CCITT is not set
1152# CONFIG_CRC16 is not set 1224# CONFIG_CRC16 is not set
1225CONFIG_CRC_T10DIF=y
1153# CONFIG_CRC_ITU_T is not set 1226# CONFIG_CRC_ITU_T is not set
1154CONFIG_CRC32=y 1227CONFIG_CRC32=y
1155# CONFIG_CRC7 is not set 1228# CONFIG_CRC7 is not set
@@ -1175,8 +1248,18 @@ CONFIG_FRAME_WARN=1024
1175# CONFIG_SLUB_DEBUG_ON is not set 1248# CONFIG_SLUB_DEBUG_ON is not set
1176# CONFIG_SLUB_STATS is not set 1249# CONFIG_SLUB_STATS is not set
1177# CONFIG_DEBUG_BUGVERBOSE is not set 1250# CONFIG_DEBUG_BUGVERBOSE is not set
1251# CONFIG_DEBUG_MEMORY_INIT is not set
1252# CONFIG_LATENCYTOP is not set
1253CONFIG_SYSCTL_SYSCALL_CHECK=y
1254CONFIG_HAVE_FTRACE=y
1255CONFIG_HAVE_DYNAMIC_FTRACE=y
1256# CONFIG_FTRACE is not set
1257# CONFIG_SCHED_TRACER is not set
1258# CONFIG_CONTEXT_SWITCH_TRACER is not set
1178# CONFIG_SAMPLES is not set 1259# CONFIG_SAMPLES is not set
1260CONFIG_HAVE_ARCH_KGDB=y
1179# CONFIG_IRQSTACKS is not set 1261# CONFIG_IRQSTACKS is not set
1262# CONFIG_BOOTX_TEXT is not set
1180# CONFIG_PPC_EARLY_DEBUG is not set 1263# CONFIG_PPC_EARLY_DEBUG is not set
1181 1264
1182# 1265#
@@ -1230,6 +1313,10 @@ CONFIG_CRYPTO_PCBC=m
1230# CONFIG_CRYPTO_MD4 is not set 1313# CONFIG_CRYPTO_MD4 is not set
1231CONFIG_CRYPTO_MD5=y 1314CONFIG_CRYPTO_MD5=y
1232# CONFIG_CRYPTO_MICHAEL_MIC is not set 1315# CONFIG_CRYPTO_MICHAEL_MIC is not set
1316# CONFIG_CRYPTO_RMD128 is not set
1317# CONFIG_CRYPTO_RMD160 is not set
1318# CONFIG_CRYPTO_RMD256 is not set
1319# CONFIG_CRYPTO_RMD320 is not set
1233# CONFIG_CRYPTO_SHA1 is not set 1320# CONFIG_CRYPTO_SHA1 is not set
1234# CONFIG_CRYPTO_SHA256 is not set 1321# CONFIG_CRYPTO_SHA256 is not set
1235# CONFIG_CRYPTO_SHA512 is not set 1322# CONFIG_CRYPTO_SHA512 is not set
@@ -1262,5 +1349,6 @@ CONFIG_CRYPTO_DES=y
1262# CONFIG_CRYPTO_LZO is not set 1349# CONFIG_CRYPTO_LZO is not set
1263CONFIG_CRYPTO_HW=y 1350CONFIG_CRYPTO_HW=y
1264# CONFIG_CRYPTO_DEV_HIFN_795X is not set 1351# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1352# CONFIG_CRYPTO_DEV_TALITOS is not set
1265# CONFIG_PPC_CLOCK is not set 1353# CONFIG_PPC_CLOCK is not set
1266# CONFIG_VIRTUALIZATION is not set 1354# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/configs/83xx/mpc834x_mds_defconfig b/arch/powerpc/configs/83xx/mpc834x_mds_defconfig
index c82e96e984fc..24c320a36670 100644
--- a/arch/powerpc/configs/83xx/mpc834x_mds_defconfig
+++ b/arch/powerpc/configs/83xx/mpc834x_mds_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc5 3# Linux kernel version: 2.6.27-rc4
4# Mon Jun 9 08:52:26 2008 4# Thu Aug 21 00:52:21 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -16,6 +16,7 @@ CONFIG_6xx=y
16# CONFIG_E200 is not set 16# CONFIG_E200 is not set
17CONFIG_PPC_FPU=y 17CONFIG_PPC_FPU=y
18# CONFIG_FSL_EMB_PERFMON is not set 18# CONFIG_FSL_EMB_PERFMON is not set
19# CONFIG_ALTIVEC is not set
19CONFIG_PPC_STD_MMU=y 20CONFIG_PPC_STD_MMU=y
20CONFIG_PPC_STD_MMU_32=y 21CONFIG_PPC_STD_MMU_32=y
21# CONFIG_PPC_MM_SLICES is not set 22# CONFIG_PPC_MM_SLICES is not set
@@ -32,6 +33,7 @@ CONFIG_GENERIC_HARDIRQS=y
32# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set 33# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
33CONFIG_IRQ_PER_CPU=y 34CONFIG_IRQ_PER_CPU=y
34CONFIG_STACKTRACE_SUPPORT=y 35CONFIG_STACKTRACE_SUPPORT=y
36CONFIG_HAVE_LATENCYTOP_SUPPORT=y
35CONFIG_LOCKDEP_SUPPORT=y 37CONFIG_LOCKDEP_SUPPORT=y
36CONFIG_RWSEM_XCHGADD_ALGORITHM=y 38CONFIG_RWSEM_XCHGADD_ALGORITHM=y
37CONFIG_ARCH_HAS_ILOG2_U32=y 39CONFIG_ARCH_HAS_ILOG2_U32=y
@@ -51,6 +53,9 @@ CONFIG_PPC_UDBG_16550=y
51CONFIG_AUDIT_ARCH=y 53CONFIG_AUDIT_ARCH=y
52CONFIG_GENERIC_BUG=y 54CONFIG_GENERIC_BUG=y
53CONFIG_DEFAULT_UIMAGE=y 55CONFIG_DEFAULT_UIMAGE=y
56CONFIG_HIBERNATE_32=y
57CONFIG_ARCH_HIBERNATION_POSSIBLE=y
58CONFIG_ARCH_SUSPEND_POSSIBLE=y
54# CONFIG_PPC_DCR_NATIVE is not set 59# CONFIG_PPC_DCR_NATIVE is not set
55# CONFIG_PPC_DCR_MMIO is not set 60# CONFIG_PPC_DCR_MMIO is not set
56CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 61CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
@@ -88,12 +93,12 @@ CONFIG_INITRAMFS_SOURCE=""
88CONFIG_SYSCTL=y 93CONFIG_SYSCTL=y
89CONFIG_EMBEDDED=y 94CONFIG_EMBEDDED=y
90CONFIG_SYSCTL_SYSCALL=y 95CONFIG_SYSCTL_SYSCALL=y
91CONFIG_SYSCTL_SYSCALL_CHECK=y
92# CONFIG_KALLSYMS is not set 96# CONFIG_KALLSYMS is not set
93CONFIG_HOTPLUG=y 97CONFIG_HOTPLUG=y
94CONFIG_PRINTK=y 98CONFIG_PRINTK=y
95CONFIG_BUG=y 99CONFIG_BUG=y
96CONFIG_ELF_CORE=y 100CONFIG_ELF_CORE=y
101CONFIG_PCSPKR_PLATFORM=y
97CONFIG_COMPAT_BRK=y 102CONFIG_COMPAT_BRK=y
98CONFIG_BASE_FULL=y 103CONFIG_BASE_FULL=y
99CONFIG_FUTEX=y 104CONFIG_FUTEX=y
@@ -111,10 +116,16 @@ CONFIG_SLUB=y
111# CONFIG_PROFILING is not set 116# CONFIG_PROFILING is not set
112# CONFIG_MARKERS is not set 117# CONFIG_MARKERS is not set
113CONFIG_HAVE_OPROFILE=y 118CONFIG_HAVE_OPROFILE=y
119CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
120CONFIG_HAVE_IOREMAP_PROT=y
114CONFIG_HAVE_KPROBES=y 121CONFIG_HAVE_KPROBES=y
115CONFIG_HAVE_KRETPROBES=y 122CONFIG_HAVE_KRETPROBES=y
123CONFIG_HAVE_ARCH_TRACEHOOK=y
116# CONFIG_HAVE_DMA_ATTRS is not set 124# CONFIG_HAVE_DMA_ATTRS is not set
125# CONFIG_USE_GENERIC_SMP_HELPERS is not set
126# CONFIG_HAVE_CLK is not set
117CONFIG_PROC_PAGE_MONITOR=y 127CONFIG_PROC_PAGE_MONITOR=y
128# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
118CONFIG_SLABINFO=y 129CONFIG_SLABINFO=y
119CONFIG_RT_MUTEXES=y 130CONFIG_RT_MUTEXES=y
120# CONFIG_TINY_SHMEM is not set 131# CONFIG_TINY_SHMEM is not set
@@ -125,12 +136,13 @@ CONFIG_MODULE_UNLOAD=y
125# CONFIG_MODULE_FORCE_UNLOAD is not set 136# CONFIG_MODULE_FORCE_UNLOAD is not set
126# CONFIG_MODVERSIONS is not set 137# CONFIG_MODVERSIONS is not set
127# CONFIG_MODULE_SRCVERSION_ALL is not set 138# CONFIG_MODULE_SRCVERSION_ALL is not set
128# CONFIG_KMOD is not set 139CONFIG_KMOD=y
129CONFIG_BLOCK=y 140CONFIG_BLOCK=y
130# CONFIG_LBD is not set 141# CONFIG_LBD is not set
131# CONFIG_BLK_DEV_IO_TRACE is not set 142# CONFIG_BLK_DEV_IO_TRACE is not set
132# CONFIG_LSF is not set 143# CONFIG_LSF is not set
133# CONFIG_BLK_DEV_BSG is not set 144# CONFIG_BLK_DEV_BSG is not set
145# CONFIG_BLK_DEV_INTEGRITY is not set
134 146
135# 147#
136# IO Schedulers 148# IO Schedulers
@@ -149,37 +161,49 @@ CONFIG_CLASSIC_RCU=y
149# 161#
150# Platform support 162# Platform support
151# 163#
152# CONFIG_PPC_MULTIPLATFORM is not set 164CONFIG_PPC_MULTIPLATFORM=y
153# CONFIG_PPC_82xx is not set 165CONFIG_CLASSIC32=y
154CONFIG_PPC_83xx=y 166CONFIG_PPC_CHRP=y
155# CONFIG_PPC_86xx is not set 167# CONFIG_MPC5121_ADS is not set
156# CONFIG_PPC_MPC512x is not set 168# CONFIG_MPC5121_GENERIC is not set
157# CONFIG_PPC_MPC5121 is not set 169# CONFIG_PPC_MPC52xx is not set
170CONFIG_PPC_PMAC=y
158# CONFIG_PPC_CELL is not set 171# CONFIG_PPC_CELL is not set
159# CONFIG_PPC_CELL_NATIVE is not set 172# CONFIG_PPC_CELL_NATIVE is not set
173# CONFIG_PPC_82xx is not set
160# CONFIG_PQ2ADS is not set 174# CONFIG_PQ2ADS is not set
161CONFIG_MPC83xx=y 175CONFIG_PPC_83xx=y
162# CONFIG_MPC831x_RDB is not set 176# CONFIG_MPC831x_RDB is not set
163# CONFIG_MPC832x_MDS is not set 177# CONFIG_MPC832x_MDS is not set
164# CONFIG_MPC832x_RDB is not set 178# CONFIG_MPC832x_RDB is not set
165CONFIG_MPC834x_MDS=y 179CONFIG_MPC834x_MDS=y
166# CONFIG_MPC834x_ITX is not set 180# CONFIG_MPC834x_ITX is not set
167# CONFIG_MPC836x_MDS is not set 181# CONFIG_MPC836x_MDS is not set
182# CONFIG_MPC836x_RDK is not set
168# CONFIG_MPC837x_MDS is not set 183# CONFIG_MPC837x_MDS is not set
169# CONFIG_MPC837x_RDB is not set 184# CONFIG_MPC837x_RDB is not set
170# CONFIG_SBC834x is not set 185# CONFIG_SBC834x is not set
186# CONFIG_ASP834x is not set
171CONFIG_PPC_MPC834x=y 187CONFIG_PPC_MPC834x=y
188# CONFIG_PPC_86xx is not set
189# CONFIG_EMBEDDED6xx is not set
190CONFIG_PPC_NATIVE=y
191# CONFIG_UDBG_RTAS_CONSOLE is not set
172CONFIG_IPIC=y 192CONFIG_IPIC=y
173# CONFIG_MPIC is not set 193CONFIG_MPIC=y
174# CONFIG_MPIC_WEIRD is not set 194# CONFIG_MPIC_WEIRD is not set
175# CONFIG_PPC_I8259 is not set 195CONFIG_PPC_I8259=y
176# CONFIG_PPC_RTAS is not set 196CONFIG_PPC_RTAS=y
197# CONFIG_RTAS_ERROR_LOGGING is not set
198CONFIG_RTAS_PROC=y
177# CONFIG_MMIO_NVRAM is not set 199# CONFIG_MMIO_NVRAM is not set
178# CONFIG_PPC_MPC106 is not set 200CONFIG_PPC_MPC106=y
179# CONFIG_PPC_970_NAP is not set 201# CONFIG_PPC_970_NAP is not set
180# CONFIG_PPC_INDIRECT_IO is not set 202# CONFIG_PPC_INDIRECT_IO is not set
181# CONFIG_GENERIC_IOMAP is not set 203# CONFIG_GENERIC_IOMAP is not set
182# CONFIG_CPU_FREQ is not set 204# CONFIG_CPU_FREQ is not set
205# CONFIG_PPC601_SYNC_FIX is not set
206# CONFIG_TAU is not set
183# CONFIG_FSL_ULI1575 is not set 207# CONFIG_FSL_ULI1575 is not set
184 208
185# 209#
@@ -195,7 +219,7 @@ CONFIG_HZ_250=y
195# CONFIG_HZ_300 is not set 219# CONFIG_HZ_300 is not set
196# CONFIG_HZ_1000 is not set 220# CONFIG_HZ_1000 is not set
197CONFIG_HZ=250 221CONFIG_HZ=250
198# CONFIG_SCHED_HRTICK is not set 222CONFIG_SCHED_HRTICK=y
199CONFIG_PREEMPT_NONE=y 223CONFIG_PREEMPT_NONE=y
200# CONFIG_PREEMPT_VOLUNTARY is not set 224# CONFIG_PREEMPT_VOLUNTARY is not set
201# CONFIG_PREEMPT is not set 225# CONFIG_PREEMPT is not set
@@ -205,6 +229,7 @@ CONFIG_BINFMT_ELF=y
205CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y 229CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
206CONFIG_ARCH_HAS_WALK_MEMORY=y 230CONFIG_ARCH_HAS_WALK_MEMORY=y
207CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y 231CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
232# CONFIG_KEXEC is not set
208CONFIG_ARCH_FLATMEM_ENABLE=y 233CONFIG_ARCH_FLATMEM_ENABLE=y
209CONFIG_ARCH_POPULATES_NODE_MAP=y 234CONFIG_ARCH_POPULATES_NODE_MAP=y
210CONFIG_SELECT_MEMORY_MODEL=y 235CONFIG_SELECT_MEMORY_MODEL=y
@@ -217,6 +242,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
217# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set 242# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
218CONFIG_PAGEFLAGS_EXTENDED=y 243CONFIG_PAGEFLAGS_EXTENDED=y
219CONFIG_SPLIT_PTLOCK_CPUS=4 244CONFIG_SPLIT_PTLOCK_CPUS=4
245CONFIG_MIGRATION=y
220# CONFIG_RESOURCES_64BIT is not set 246# CONFIG_RESOURCES_64BIT is not set
221CONFIG_ZONE_DMA_FLAG=1 247CONFIG_ZONE_DMA_FLAG=1
222CONFIG_BOUNCE=y 248CONFIG_BOUNCE=y
@@ -224,6 +250,7 @@ CONFIG_VIRT_TO_BUS=y
224CONFIG_FORCE_MAX_ZONEORDER=11 250CONFIG_FORCE_MAX_ZONEORDER=11
225CONFIG_PROC_DEVICETREE=y 251CONFIG_PROC_DEVICETREE=y
226# CONFIG_CMDLINE_BOOL is not set 252# CONFIG_CMDLINE_BOOL is not set
253CONFIG_EXTRA_TARGETS=""
227# CONFIG_PM is not set 254# CONFIG_PM is not set
228CONFIG_SECCOMP=y 255CONFIG_SECCOMP=y
229CONFIG_ISA_DMA_API=y 256CONFIG_ISA_DMA_API=y
@@ -231,10 +258,13 @@ CONFIG_ISA_DMA_API=y
231# 258#
232# Bus options 259# Bus options
233# 260#
261# CONFIG_ISA is not set
234CONFIG_ZONE_DMA=y 262CONFIG_ZONE_DMA=y
235CONFIG_GENERIC_ISA_DMA=y 263CONFIG_GENERIC_ISA_DMA=y
236CONFIG_PPC_INDIRECT_PCI=y 264CONFIG_PPC_INDIRECT_PCI=y
237CONFIG_FSL_SOC=y 265CONFIG_FSL_SOC=y
266CONFIG_FSL_PCI=y
267CONFIG_PPC_PCI_CHOICE=y
238CONFIG_PCI=y 268CONFIG_PCI=y
239CONFIG_PCI_DOMAINS=y 269CONFIG_PCI_DOMAINS=y
240CONFIG_PCI_SYSCALL=y 270CONFIG_PCI_SYSCALL=y
@@ -259,10 +289,6 @@ CONFIG_PAGE_OFFSET=0xc0000000
259CONFIG_KERNEL_START=0xc0000000 289CONFIG_KERNEL_START=0xc0000000
260CONFIG_PHYSICAL_START=0x00000000 290CONFIG_PHYSICAL_START=0x00000000
261CONFIG_TASK_SIZE=0xc0000000 291CONFIG_TASK_SIZE=0xc0000000
262
263#
264# Networking
265#
266CONFIG_NET=y 292CONFIG_NET=y
267 293
268# 294#
@@ -363,6 +389,7 @@ CONFIG_OF_I2C=y
363# CONFIG_PARPORT is not set 389# CONFIG_PARPORT is not set
364CONFIG_BLK_DEV=y 390CONFIG_BLK_DEV=y
365# CONFIG_BLK_DEV_FD is not set 391# CONFIG_BLK_DEV_FD is not set
392# CONFIG_MAC_FLOPPY is not set
366# CONFIG_BLK_CPQ_DA is not set 393# CONFIG_BLK_CPQ_DA is not set
367# CONFIG_BLK_CPQ_CISS_DA is not set 394# CONFIG_BLK_CPQ_CISS_DA is not set
368# CONFIG_BLK_DEV_DAC960 is not set 395# CONFIG_BLK_DEV_DAC960 is not set
@@ -378,12 +405,14 @@ CONFIG_BLK_DEV_RAM_SIZE=32768
378# CONFIG_BLK_DEV_XIP is not set 405# CONFIG_BLK_DEV_XIP is not set
379# CONFIG_CDROM_PKTCDVD is not set 406# CONFIG_CDROM_PKTCDVD is not set
380# CONFIG_ATA_OVER_ETH is not set 407# CONFIG_ATA_OVER_ETH is not set
408# CONFIG_BLK_DEV_HD is not set
381CONFIG_MISC_DEVICES=y 409CONFIG_MISC_DEVICES=y
382# CONFIG_PHANTOM is not set 410# CONFIG_PHANTOM is not set
383# CONFIG_EEPROM_93CX6 is not set 411# CONFIG_EEPROM_93CX6 is not set
384# CONFIG_SGI_IOC4 is not set 412# CONFIG_SGI_IOC4 is not set
385# CONFIG_TIFM_CORE is not set 413# CONFIG_TIFM_CORE is not set
386# CONFIG_ENCLOSURE_SERVICES is not set 414# CONFIG_ENCLOSURE_SERVICES is not set
415# CONFIG_HP_ILO is not set
387CONFIG_HAVE_IDE=y 416CONFIG_HAVE_IDE=y
388# CONFIG_IDE is not set 417# CONFIG_IDE is not set
389 418
@@ -401,12 +430,15 @@ CONFIG_HAVE_IDE=y
401# 430#
402# IEEE 1394 (FireWire) support 431# IEEE 1394 (FireWire) support
403# 432#
433
434#
435# Enable only one of the two stacks, unless you know what you are doing
436#
404# CONFIG_FIREWIRE is not set 437# CONFIG_FIREWIRE is not set
405# CONFIG_IEEE1394 is not set 438# CONFIG_IEEE1394 is not set
406# CONFIG_I2O is not set 439# CONFIG_I2O is not set
407# CONFIG_MACINTOSH_DRIVERS is not set 440# CONFIG_MACINTOSH_DRIVERS is not set
408CONFIG_NETDEVICES=y 441CONFIG_NETDEVICES=y
409# CONFIG_NETDEVICES_MULTIQUEUE is not set
410# CONFIG_DUMMY is not set 442# CONFIG_DUMMY is not set
411# CONFIG_BONDING is not set 443# CONFIG_BONDING is not set
412# CONFIG_MACVLAN is not set 444# CONFIG_MACVLAN is not set
@@ -433,6 +465,8 @@ CONFIG_MARVELL_PHY=y
433# CONFIG_MDIO_BITBANG is not set 465# CONFIG_MDIO_BITBANG is not set
434CONFIG_NET_ETHERNET=y 466CONFIG_NET_ETHERNET=y
435CONFIG_MII=y 467CONFIG_MII=y
468# CONFIG_MACE is not set
469# CONFIG_BMAC is not set
436# CONFIG_HAPPYMEAL is not set 470# CONFIG_HAPPYMEAL is not set
437# CONFIG_SUNGEM is not set 471# CONFIG_SUNGEM is not set
438# CONFIG_CASSINI is not set 472# CONFIG_CASSINI is not set
@@ -468,7 +502,6 @@ CONFIG_NETDEV_1000=y
468# CONFIG_DL2K is not set 502# CONFIG_DL2K is not set
469# CONFIG_E1000 is not set 503# CONFIG_E1000 is not set
470# CONFIG_E1000E is not set 504# CONFIG_E1000E is not set
471# CONFIG_E1000E_ENABLED is not set
472# CONFIG_IP1000 is not set 505# CONFIG_IP1000 is not set
473# CONFIG_IGB is not set 506# CONFIG_IGB is not set
474# CONFIG_NS83820 is not set 507# CONFIG_NS83820 is not set
@@ -482,9 +515,10 @@ CONFIG_NETDEV_1000=y
482# CONFIG_TIGON3 is not set 515# CONFIG_TIGON3 is not set
483# CONFIG_BNX2 is not set 516# CONFIG_BNX2 is not set
484CONFIG_GIANFAR=y 517CONFIG_GIANFAR=y
485# CONFIG_GFAR_NAPI is not set 518# CONFIG_MV643XX_ETH is not set
486# CONFIG_QLA3XXX is not set 519# CONFIG_QLA3XXX is not set
487# CONFIG_ATL1 is not set 520# CONFIG_ATL1 is not set
521# CONFIG_ATL1E is not set
488CONFIG_NETDEV_10000=y 522CONFIG_NETDEV_10000=y
489# CONFIG_CHELSIO_T1 is not set 523# CONFIG_CHELSIO_T1 is not set
490# CONFIG_CHELSIO_T3 is not set 524# CONFIG_CHELSIO_T3 is not set
@@ -572,11 +606,14 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=4
572# CONFIG_SERIAL_UARTLITE is not set 606# CONFIG_SERIAL_UARTLITE is not set
573CONFIG_SERIAL_CORE=y 607CONFIG_SERIAL_CORE=y
574CONFIG_SERIAL_CORE_CONSOLE=y 608CONFIG_SERIAL_CORE_CONSOLE=y
609# CONFIG_SERIAL_PMACZILOG is not set
575# CONFIG_SERIAL_JSM is not set 610# CONFIG_SERIAL_JSM is not set
576# CONFIG_SERIAL_OF_PLATFORM is not set 611# CONFIG_SERIAL_OF_PLATFORM is not set
577CONFIG_UNIX98_PTYS=y 612CONFIG_UNIX98_PTYS=y
578CONFIG_LEGACY_PTYS=y 613CONFIG_LEGACY_PTYS=y
579CONFIG_LEGACY_PTY_COUNT=256 614CONFIG_LEGACY_PTY_COUNT=256
615# CONFIG_BRIQ_PANEL is not set
616# CONFIG_HVC_RTAS is not set
580# CONFIG_IPMI_HANDLER is not set 617# CONFIG_IPMI_HANDLER is not set
581# CONFIG_HW_RANDOM is not set 618# CONFIG_HW_RANDOM is not set
582# CONFIG_NVRAM is not set 619# CONFIG_NVRAM is not set
@@ -588,42 +625,69 @@ CONFIG_DEVPORT=y
588CONFIG_I2C=y 625CONFIG_I2C=y
589CONFIG_I2C_BOARDINFO=y 626CONFIG_I2C_BOARDINFO=y
590CONFIG_I2C_CHARDEV=y 627CONFIG_I2C_CHARDEV=y
628CONFIG_I2C_HELPER_AUTO=y
591 629
592# 630#
593# I2C Hardware Bus support 631# I2C Hardware Bus support
594# 632#
633
634#
635# PC SMBus host controller drivers
636#
595# CONFIG_I2C_ALI1535 is not set 637# CONFIG_I2C_ALI1535 is not set
596# CONFIG_I2C_ALI1563 is not set 638# CONFIG_I2C_ALI1563 is not set
597# CONFIG_I2C_ALI15X3 is not set 639# CONFIG_I2C_ALI15X3 is not set
598# CONFIG_I2C_AMD756 is not set 640# CONFIG_I2C_AMD756 is not set
599# CONFIG_I2C_AMD8111 is not set 641# CONFIG_I2C_AMD8111 is not set
600# CONFIG_I2C_I801 is not set 642# CONFIG_I2C_I801 is not set
601# CONFIG_I2C_I810 is not set 643# CONFIG_I2C_ISCH is not set
602# CONFIG_I2C_PIIX4 is not set 644# CONFIG_I2C_PIIX4 is not set
603CONFIG_I2C_MPC=y
604# CONFIG_I2C_NFORCE2 is not set 645# CONFIG_I2C_NFORCE2 is not set
605# CONFIG_I2C_OCORES is not set
606# CONFIG_I2C_PARPORT_LIGHT is not set
607# CONFIG_I2C_PROSAVAGE is not set
608# CONFIG_I2C_SAVAGE4 is not set
609# CONFIG_I2C_SIMTEC is not set
610# CONFIG_I2C_SIS5595 is not set 646# CONFIG_I2C_SIS5595 is not set
611# CONFIG_I2C_SIS630 is not set 647# CONFIG_I2C_SIS630 is not set
612# CONFIG_I2C_SIS96X is not set 648# CONFIG_I2C_SIS96X is not set
613# CONFIG_I2C_TAOS_EVM is not set
614# CONFIG_I2C_STUB is not set
615# CONFIG_I2C_VIA is not set 649# CONFIG_I2C_VIA is not set
616# CONFIG_I2C_VIAPRO is not set 650# CONFIG_I2C_VIAPRO is not set
651
652#
653# Mac SMBus host controller drivers
654#
655# CONFIG_I2C_HYDRA is not set
656CONFIG_I2C_POWERMAC=y
657
658#
659# I2C system bus drivers (mostly embedded / system-on-chip)
660#
661CONFIG_I2C_MPC=y
662# CONFIG_I2C_OCORES is not set
663# CONFIG_I2C_SIMTEC is not set
664
665#
666# External I2C/SMBus adapter drivers
667#
668# CONFIG_I2C_PARPORT_LIGHT is not set
669# CONFIG_I2C_TAOS_EVM is not set
670
671#
672# Graphics adapter I2C/DDC channel drivers
673#
617# CONFIG_I2C_VOODOO3 is not set 674# CONFIG_I2C_VOODOO3 is not set
675
676#
677# Other I2C/SMBus bus drivers
678#
618# CONFIG_I2C_PCA_PLATFORM is not set 679# CONFIG_I2C_PCA_PLATFORM is not set
680# CONFIG_I2C_STUB is not set
619 681
620# 682#
621# Miscellaneous I2C Chip support 683# Miscellaneous I2C Chip support
622# 684#
623# CONFIG_DS1682 is not set 685# CONFIG_DS1682 is not set
686# CONFIG_AT24 is not set
624# CONFIG_SENSORS_EEPROM is not set 687# CONFIG_SENSORS_EEPROM is not set
625# CONFIG_SENSORS_PCF8574 is not set 688# CONFIG_SENSORS_PCF8574 is not set
626# CONFIG_PCF8575 is not set 689# CONFIG_PCF8575 is not set
690# CONFIG_SENSORS_PCA9539 is not set
627# CONFIG_SENSORS_PCF8591 is not set 691# CONFIG_SENSORS_PCF8591 is not set
628# CONFIG_SENSORS_MAX6875 is not set 692# CONFIG_SENSORS_MAX6875 is not set
629# CONFIG_SENSORS_TSL2550 is not set 693# CONFIG_SENSORS_TSL2550 is not set
@@ -632,10 +696,13 @@ CONFIG_I2C_MPC=y
632# CONFIG_I2C_DEBUG_BUS is not set 696# CONFIG_I2C_DEBUG_BUS is not set
633# CONFIG_I2C_DEBUG_CHIP is not set 697# CONFIG_I2C_DEBUG_CHIP is not set
634# CONFIG_SPI is not set 698# CONFIG_SPI is not set
699CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
700# CONFIG_GPIOLIB is not set
635# CONFIG_W1 is not set 701# CONFIG_W1 is not set
636# CONFIG_POWER_SUPPLY is not set 702# CONFIG_POWER_SUPPLY is not set
637CONFIG_HWMON=y 703CONFIG_HWMON=y
638# CONFIG_HWMON_VID is not set 704# CONFIG_HWMON_VID is not set
705# CONFIG_SENSORS_AD7414 is not set
639# CONFIG_SENSORS_AD7418 is not set 706# CONFIG_SENSORS_AD7418 is not set
640# CONFIG_SENSORS_ADM1021 is not set 707# CONFIG_SENSORS_ADM1021 is not set
641# CONFIG_SENSORS_ADM1025 is not set 708# CONFIG_SENSORS_ADM1025 is not set
@@ -645,6 +712,7 @@ CONFIG_HWMON=y
645# CONFIG_SENSORS_ADM9240 is not set 712# CONFIG_SENSORS_ADM9240 is not set
646# CONFIG_SENSORS_ADT7470 is not set 713# CONFIG_SENSORS_ADT7470 is not set
647# CONFIG_SENSORS_ADT7473 is not set 714# CONFIG_SENSORS_ADT7473 is not set
715# CONFIG_SENSORS_AMS is not set
648# CONFIG_SENSORS_ATXP1 is not set 716# CONFIG_SENSORS_ATXP1 is not set
649# CONFIG_SENSORS_DS1621 is not set 717# CONFIG_SENSORS_DS1621 is not set
650# CONFIG_SENSORS_I5K_AMB is not set 718# CONFIG_SENSORS_I5K_AMB is not set
@@ -689,6 +757,7 @@ CONFIG_HWMON=y
689# CONFIG_SENSORS_W83627EHF is not set 757# CONFIG_SENSORS_W83627EHF is not set
690# CONFIG_HWMON_DEBUG_CHIP is not set 758# CONFIG_HWMON_DEBUG_CHIP is not set
691# CONFIG_THERMAL is not set 759# CONFIG_THERMAL is not set
760# CONFIG_THERMAL_HWMON is not set
692CONFIG_WATCHDOG=y 761CONFIG_WATCHDOG=y
693# CONFIG_WATCHDOG_NOWAYOUT is not set 762# CONFIG_WATCHDOG_NOWAYOUT is not set
694 763
@@ -696,7 +765,9 @@ CONFIG_WATCHDOG=y
696# Watchdog Device Drivers 765# Watchdog Device Drivers
697# 766#
698# CONFIG_SOFT_WATCHDOG is not set 767# CONFIG_SOFT_WATCHDOG is not set
699CONFIG_83xx_WDT=y 768# CONFIG_ALIM7101_WDT is not set
769# CONFIG_8xxx_WDT is not set
770# CONFIG_WATCHDOG_RTAS is not set
700 771
701# 772#
702# PCI-based Watchdog Cards 773# PCI-based Watchdog Cards
@@ -713,8 +784,10 @@ CONFIG_SSB_POSSIBLE=y
713# 784#
714# Multifunction device drivers 785# Multifunction device drivers
715# 786#
787# CONFIG_MFD_CORE is not set
716# CONFIG_MFD_SM501 is not set 788# CONFIG_MFD_SM501 is not set
717# CONFIG_HTC_PASIC3 is not set 789# CONFIG_HTC_PASIC3 is not set
790# CONFIG_MFD_TMIO is not set
718 791
719# 792#
720# Multimedia devices 793# Multimedia devices
@@ -746,10 +819,6 @@ CONFIG_VIDEO_OUTPUT_CONTROL=m
746# Display device support 819# Display device support
747# 820#
748# CONFIG_DISPLAY_SUPPORT is not set 821# CONFIG_DISPLAY_SUPPORT is not set
749
750#
751# Sound
752#
753# CONFIG_SOUND is not set 822# CONFIG_SOUND is not set
754CONFIG_HID_SUPPORT=y 823CONFIG_HID_SUPPORT=y
755CONFIG_HID=y 824CONFIG_HID=y
@@ -764,6 +833,10 @@ CONFIG_USB_ARCH_HAS_EHCI=y
764# CONFIG_USB_OTG_BLACKLIST_HUB is not set 833# CONFIG_USB_OTG_BLACKLIST_HUB is not set
765 834
766# 835#
836# Enable Host or Gadget support to see Inventra options
837#
838
839#
767# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 840# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
768# 841#
769# CONFIG_USB_GADGET is not set 842# CONFIG_USB_GADGET is not set
@@ -802,6 +875,7 @@ CONFIG_RTC_DRV_DS1374=y
802# CONFIG_RTC_DRV_PCF8583 is not set 875# CONFIG_RTC_DRV_PCF8583 is not set
803# CONFIG_RTC_DRV_M41T80 is not set 876# CONFIG_RTC_DRV_M41T80 is not set
804# CONFIG_RTC_DRV_S35390A is not set 877# CONFIG_RTC_DRV_S35390A is not set
878# CONFIG_RTC_DRV_FM3130 is not set
805 879
806# 880#
807# SPI RTC drivers 881# SPI RTC drivers
@@ -890,6 +964,7 @@ CONFIG_TMPFS=y
890# CONFIG_CRAMFS is not set 964# CONFIG_CRAMFS is not set
891# CONFIG_VXFS_FS is not set 965# CONFIG_VXFS_FS is not set
892# CONFIG_MINIX_FS is not set 966# CONFIG_MINIX_FS is not set
967# CONFIG_OMFS_FS is not set
893# CONFIG_HPFS_FS is not set 968# CONFIG_HPFS_FS is not set
894# CONFIG_QNX4FS_FS is not set 969# CONFIG_QNX4FS_FS is not set
895# CONFIG_ROMFS_FS is not set 970# CONFIG_ROMFS_FS is not set
@@ -900,14 +975,13 @@ CONFIG_NFS_FS=y
900CONFIG_NFS_V3=y 975CONFIG_NFS_V3=y
901# CONFIG_NFS_V3_ACL is not set 976# CONFIG_NFS_V3_ACL is not set
902CONFIG_NFS_V4=y 977CONFIG_NFS_V4=y
903# CONFIG_NFSD is not set
904CONFIG_ROOT_NFS=y 978CONFIG_ROOT_NFS=y
979# CONFIG_NFSD is not set
905CONFIG_LOCKD=y 980CONFIG_LOCKD=y
906CONFIG_LOCKD_V4=y 981CONFIG_LOCKD_V4=y
907CONFIG_NFS_COMMON=y 982CONFIG_NFS_COMMON=y
908CONFIG_SUNRPC=y 983CONFIG_SUNRPC=y
909CONFIG_SUNRPC_GSS=y 984CONFIG_SUNRPC_GSS=y
910# CONFIG_SUNRPC_BIND34 is not set
911CONFIG_RPCSEC_GSS_KRB5=y 985CONFIG_RPCSEC_GSS_KRB5=y
912# CONFIG_RPCSEC_GSS_SPKM3 is not set 986# CONFIG_RPCSEC_GSS_SPKM3 is not set
913# CONFIG_SMB_FS is not set 987# CONFIG_SMB_FS is not set
@@ -943,6 +1017,7 @@ CONFIG_BITREVERSE=y
943# CONFIG_GENERIC_FIND_FIRST_BIT is not set 1017# CONFIG_GENERIC_FIND_FIRST_BIT is not set
944# CONFIG_CRC_CCITT is not set 1018# CONFIG_CRC_CCITT is not set
945# CONFIG_CRC16 is not set 1019# CONFIG_CRC16 is not set
1020# CONFIG_CRC_T10DIF is not set
946# CONFIG_CRC_ITU_T is not set 1021# CONFIG_CRC_ITU_T is not set
947CONFIG_CRC32=y 1022CONFIG_CRC32=y
948# CONFIG_CRC7 is not set 1023# CONFIG_CRC7 is not set
@@ -968,8 +1043,18 @@ CONFIG_FRAME_WARN=1024
968# CONFIG_SLUB_DEBUG_ON is not set 1043# CONFIG_SLUB_DEBUG_ON is not set
969# CONFIG_SLUB_STATS is not set 1044# CONFIG_SLUB_STATS is not set
970# CONFIG_DEBUG_BUGVERBOSE is not set 1045# CONFIG_DEBUG_BUGVERBOSE is not set
1046# CONFIG_DEBUG_MEMORY_INIT is not set
1047# CONFIG_LATENCYTOP is not set
1048CONFIG_SYSCTL_SYSCALL_CHECK=y
1049CONFIG_HAVE_FTRACE=y
1050CONFIG_HAVE_DYNAMIC_FTRACE=y
1051# CONFIG_FTRACE is not set
1052# CONFIG_SCHED_TRACER is not set
1053# CONFIG_CONTEXT_SWITCH_TRACER is not set
971# CONFIG_SAMPLES is not set 1054# CONFIG_SAMPLES is not set
1055CONFIG_HAVE_ARCH_KGDB=y
972# CONFIG_IRQSTACKS is not set 1056# CONFIG_IRQSTACKS is not set
1057# CONFIG_BOOTX_TEXT is not set
973# CONFIG_PPC_EARLY_DEBUG is not set 1058# CONFIG_PPC_EARLY_DEBUG is not set
974 1059
975# 1060#
@@ -1023,6 +1108,10 @@ CONFIG_CRYPTO_PCBC=m
1023# CONFIG_CRYPTO_MD4 is not set 1108# CONFIG_CRYPTO_MD4 is not set
1024CONFIG_CRYPTO_MD5=y 1109CONFIG_CRYPTO_MD5=y
1025# CONFIG_CRYPTO_MICHAEL_MIC is not set 1110# CONFIG_CRYPTO_MICHAEL_MIC is not set
1111# CONFIG_CRYPTO_RMD128 is not set
1112# CONFIG_CRYPTO_RMD160 is not set
1113# CONFIG_CRYPTO_RMD256 is not set
1114# CONFIG_CRYPTO_RMD320 is not set
1026# CONFIG_CRYPTO_SHA1 is not set 1115# CONFIG_CRYPTO_SHA1 is not set
1027# CONFIG_CRYPTO_SHA256 is not set 1116# CONFIG_CRYPTO_SHA256 is not set
1028# CONFIG_CRYPTO_SHA512 is not set 1117# CONFIG_CRYPTO_SHA512 is not set
@@ -1055,5 +1144,6 @@ CONFIG_CRYPTO_DES=y
1055# CONFIG_CRYPTO_LZO is not set 1144# CONFIG_CRYPTO_LZO is not set
1056CONFIG_CRYPTO_HW=y 1145CONFIG_CRYPTO_HW=y
1057# CONFIG_CRYPTO_DEV_HIFN_795X is not set 1146# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1147# CONFIG_CRYPTO_DEV_TALITOS is not set
1058# CONFIG_PPC_CLOCK is not set 1148# CONFIG_PPC_CLOCK is not set
1059# CONFIG_VIRTUALIZATION is not set 1149# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/configs/83xx/mpc836x_mds_defconfig b/arch/powerpc/configs/83xx/mpc836x_mds_defconfig
index 20fd9f58cf42..e029e9e14622 100644
--- a/arch/powerpc/configs/83xx/mpc836x_mds_defconfig
+++ b/arch/powerpc/configs/83xx/mpc836x_mds_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc5 3# Linux kernel version: 2.6.27-rc4
4# Mon Jun 9 08:52:27 2008 4# Thu Aug 21 00:52:22 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -16,6 +16,7 @@ CONFIG_6xx=y
16# CONFIG_E200 is not set 16# CONFIG_E200 is not set
17CONFIG_PPC_FPU=y 17CONFIG_PPC_FPU=y
18# CONFIG_FSL_EMB_PERFMON is not set 18# CONFIG_FSL_EMB_PERFMON is not set
19# CONFIG_ALTIVEC is not set
19CONFIG_PPC_STD_MMU=y 20CONFIG_PPC_STD_MMU=y
20CONFIG_PPC_STD_MMU_32=y 21CONFIG_PPC_STD_MMU_32=y
21# CONFIG_PPC_MM_SLICES is not set 22# CONFIG_PPC_MM_SLICES is not set
@@ -32,6 +33,7 @@ CONFIG_GENERIC_HARDIRQS=y
32# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set 33# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
33CONFIG_IRQ_PER_CPU=y 34CONFIG_IRQ_PER_CPU=y
34CONFIG_STACKTRACE_SUPPORT=y 35CONFIG_STACKTRACE_SUPPORT=y
36CONFIG_HAVE_LATENCYTOP_SUPPORT=y
35CONFIG_LOCKDEP_SUPPORT=y 37CONFIG_LOCKDEP_SUPPORT=y
36CONFIG_RWSEM_XCHGADD_ALGORITHM=y 38CONFIG_RWSEM_XCHGADD_ALGORITHM=y
37CONFIG_ARCH_HAS_ILOG2_U32=y 39CONFIG_ARCH_HAS_ILOG2_U32=y
@@ -51,6 +53,9 @@ CONFIG_PPC_UDBG_16550=y
51CONFIG_AUDIT_ARCH=y 53CONFIG_AUDIT_ARCH=y
52CONFIG_GENERIC_BUG=y 54CONFIG_GENERIC_BUG=y
53CONFIG_DEFAULT_UIMAGE=y 55CONFIG_DEFAULT_UIMAGE=y
56CONFIG_HIBERNATE_32=y
57CONFIG_ARCH_HIBERNATION_POSSIBLE=y
58CONFIG_ARCH_SUSPEND_POSSIBLE=y
54# CONFIG_PPC_DCR_NATIVE is not set 59# CONFIG_PPC_DCR_NATIVE is not set
55# CONFIG_PPC_DCR_MMIO is not set 60# CONFIG_PPC_DCR_MMIO is not set
56CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 61CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
@@ -88,12 +93,12 @@ CONFIG_INITRAMFS_SOURCE=""
88CONFIG_SYSCTL=y 93CONFIG_SYSCTL=y
89CONFIG_EMBEDDED=y 94CONFIG_EMBEDDED=y
90CONFIG_SYSCTL_SYSCALL=y 95CONFIG_SYSCTL_SYSCALL=y
91CONFIG_SYSCTL_SYSCALL_CHECK=y
92# CONFIG_KALLSYMS is not set 96# CONFIG_KALLSYMS is not set
93CONFIG_HOTPLUG=y 97CONFIG_HOTPLUG=y
94CONFIG_PRINTK=y 98CONFIG_PRINTK=y
95CONFIG_BUG=y 99CONFIG_BUG=y
96CONFIG_ELF_CORE=y 100CONFIG_ELF_CORE=y
101CONFIG_PCSPKR_PLATFORM=y
97CONFIG_COMPAT_BRK=y 102CONFIG_COMPAT_BRK=y
98CONFIG_BASE_FULL=y 103CONFIG_BASE_FULL=y
99CONFIG_FUTEX=y 104CONFIG_FUTEX=y
@@ -111,10 +116,16 @@ CONFIG_SLUB=y
111# CONFIG_PROFILING is not set 116# CONFIG_PROFILING is not set
112# CONFIG_MARKERS is not set 117# CONFIG_MARKERS is not set
113CONFIG_HAVE_OPROFILE=y 118CONFIG_HAVE_OPROFILE=y
119CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
120CONFIG_HAVE_IOREMAP_PROT=y
114CONFIG_HAVE_KPROBES=y 121CONFIG_HAVE_KPROBES=y
115CONFIG_HAVE_KRETPROBES=y 122CONFIG_HAVE_KRETPROBES=y
123CONFIG_HAVE_ARCH_TRACEHOOK=y
116# CONFIG_HAVE_DMA_ATTRS is not set 124# CONFIG_HAVE_DMA_ATTRS is not set
125# CONFIG_USE_GENERIC_SMP_HELPERS is not set
126# CONFIG_HAVE_CLK is not set
117CONFIG_PROC_PAGE_MONITOR=y 127CONFIG_PROC_PAGE_MONITOR=y
128# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
118CONFIG_SLABINFO=y 129CONFIG_SLABINFO=y
119CONFIG_RT_MUTEXES=y 130CONFIG_RT_MUTEXES=y
120# CONFIG_TINY_SHMEM is not set 131# CONFIG_TINY_SHMEM is not set
@@ -125,12 +136,13 @@ CONFIG_MODULE_UNLOAD=y
125# CONFIG_MODULE_FORCE_UNLOAD is not set 136# CONFIG_MODULE_FORCE_UNLOAD is not set
126# CONFIG_MODVERSIONS is not set 137# CONFIG_MODVERSIONS is not set
127# CONFIG_MODULE_SRCVERSION_ALL is not set 138# CONFIG_MODULE_SRCVERSION_ALL is not set
128# CONFIG_KMOD is not set 139CONFIG_KMOD=y
129CONFIG_BLOCK=y 140CONFIG_BLOCK=y
130# CONFIG_LBD is not set 141# CONFIG_LBD is not set
131# CONFIG_BLK_DEV_IO_TRACE is not set 142# CONFIG_BLK_DEV_IO_TRACE is not set
132# CONFIG_LSF is not set 143# CONFIG_LSF is not set
133# CONFIG_BLK_DEV_BSG is not set 144# CONFIG_BLK_DEV_BSG is not set
145# CONFIG_BLK_DEV_INTEGRITY is not set
134 146
135# 147#
136# IO Schedulers 148# IO Schedulers
@@ -149,36 +161,48 @@ CONFIG_CLASSIC_RCU=y
149# 161#
150# Platform support 162# Platform support
151# 163#
152# CONFIG_PPC_MULTIPLATFORM is not set 164CONFIG_PPC_MULTIPLATFORM=y
153# CONFIG_PPC_82xx is not set 165CONFIG_CLASSIC32=y
154CONFIG_PPC_83xx=y 166CONFIG_PPC_CHRP=y
155# CONFIG_PPC_86xx is not set 167# CONFIG_MPC5121_ADS is not set
156# CONFIG_PPC_MPC512x is not set 168# CONFIG_MPC5121_GENERIC is not set
157# CONFIG_PPC_MPC5121 is not set 169# CONFIG_PPC_MPC52xx is not set
170CONFIG_PPC_PMAC=y
158# CONFIG_PPC_CELL is not set 171# CONFIG_PPC_CELL is not set
159# CONFIG_PPC_CELL_NATIVE is not set 172# CONFIG_PPC_CELL_NATIVE is not set
173# CONFIG_PPC_82xx is not set
160# CONFIG_PQ2ADS is not set 174# CONFIG_PQ2ADS is not set
161CONFIG_MPC83xx=y 175CONFIG_PPC_83xx=y
162# CONFIG_MPC831x_RDB is not set 176# CONFIG_MPC831x_RDB is not set
163# CONFIG_MPC832x_MDS is not set 177# CONFIG_MPC832x_MDS is not set
164# CONFIG_MPC832x_RDB is not set 178# CONFIG_MPC832x_RDB is not set
165# CONFIG_MPC834x_MDS is not set 179# CONFIG_MPC834x_MDS is not set
166# CONFIG_MPC834x_ITX is not set 180# CONFIG_MPC834x_ITX is not set
167CONFIG_MPC836x_MDS=y 181CONFIG_MPC836x_MDS=y
182# CONFIG_MPC836x_RDK is not set
168# CONFIG_MPC837x_MDS is not set 183# CONFIG_MPC837x_MDS is not set
169# CONFIG_MPC837x_RDB is not set 184# CONFIG_MPC837x_RDB is not set
170# CONFIG_SBC834x is not set 185# CONFIG_SBC834x is not set
186# CONFIG_ASP834x is not set
187# CONFIG_PPC_86xx is not set
188# CONFIG_EMBEDDED6xx is not set
189CONFIG_PPC_NATIVE=y
190# CONFIG_UDBG_RTAS_CONSOLE is not set
171CONFIG_IPIC=y 191CONFIG_IPIC=y
172# CONFIG_MPIC is not set 192CONFIG_MPIC=y
173# CONFIG_MPIC_WEIRD is not set 193# CONFIG_MPIC_WEIRD is not set
174# CONFIG_PPC_I8259 is not set 194CONFIG_PPC_I8259=y
175# CONFIG_PPC_RTAS is not set 195CONFIG_PPC_RTAS=y
196# CONFIG_RTAS_ERROR_LOGGING is not set
197CONFIG_RTAS_PROC=y
176# CONFIG_MMIO_NVRAM is not set 198# CONFIG_MMIO_NVRAM is not set
177# CONFIG_PPC_MPC106 is not set 199CONFIG_PPC_MPC106=y
178# CONFIG_PPC_970_NAP is not set 200# CONFIG_PPC_970_NAP is not set
179# CONFIG_PPC_INDIRECT_IO is not set 201# CONFIG_PPC_INDIRECT_IO is not set
180# CONFIG_GENERIC_IOMAP is not set 202# CONFIG_GENERIC_IOMAP is not set
181# CONFIG_CPU_FREQ is not set 203# CONFIG_CPU_FREQ is not set
204# CONFIG_PPC601_SYNC_FIX is not set
205# CONFIG_TAU is not set
182CONFIG_QUICC_ENGINE=y 206CONFIG_QUICC_ENGINE=y
183# CONFIG_FSL_ULI1575 is not set 207# CONFIG_FSL_ULI1575 is not set
184 208
@@ -195,7 +219,7 @@ CONFIG_HZ_250=y
195# CONFIG_HZ_300 is not set 219# CONFIG_HZ_300 is not set
196# CONFIG_HZ_1000 is not set 220# CONFIG_HZ_1000 is not set
197CONFIG_HZ=250 221CONFIG_HZ=250
198# CONFIG_SCHED_HRTICK is not set 222CONFIG_SCHED_HRTICK=y
199CONFIG_PREEMPT_NONE=y 223CONFIG_PREEMPT_NONE=y
200# CONFIG_PREEMPT_VOLUNTARY is not set 224# CONFIG_PREEMPT_VOLUNTARY is not set
201# CONFIG_PREEMPT is not set 225# CONFIG_PREEMPT is not set
@@ -205,6 +229,7 @@ CONFIG_BINFMT_ELF=y
205CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y 229CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
206CONFIG_ARCH_HAS_WALK_MEMORY=y 230CONFIG_ARCH_HAS_WALK_MEMORY=y
207CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y 231CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
232# CONFIG_KEXEC is not set
208CONFIG_ARCH_FLATMEM_ENABLE=y 233CONFIG_ARCH_FLATMEM_ENABLE=y
209CONFIG_ARCH_POPULATES_NODE_MAP=y 234CONFIG_ARCH_POPULATES_NODE_MAP=y
210CONFIG_SELECT_MEMORY_MODEL=y 235CONFIG_SELECT_MEMORY_MODEL=y
@@ -217,6 +242,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
217# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set 242# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
218CONFIG_PAGEFLAGS_EXTENDED=y 243CONFIG_PAGEFLAGS_EXTENDED=y
219CONFIG_SPLIT_PTLOCK_CPUS=4 244CONFIG_SPLIT_PTLOCK_CPUS=4
245CONFIG_MIGRATION=y
220# CONFIG_RESOURCES_64BIT is not set 246# CONFIG_RESOURCES_64BIT is not set
221CONFIG_ZONE_DMA_FLAG=1 247CONFIG_ZONE_DMA_FLAG=1
222CONFIG_BOUNCE=y 248CONFIG_BOUNCE=y
@@ -224,6 +250,7 @@ CONFIG_VIRT_TO_BUS=y
224CONFIG_FORCE_MAX_ZONEORDER=11 250CONFIG_FORCE_MAX_ZONEORDER=11
225CONFIG_PROC_DEVICETREE=y 251CONFIG_PROC_DEVICETREE=y
226# CONFIG_CMDLINE_BOOL is not set 252# CONFIG_CMDLINE_BOOL is not set
253CONFIG_EXTRA_TARGETS=""
227# CONFIG_PM is not set 254# CONFIG_PM is not set
228CONFIG_SECCOMP=y 255CONFIG_SECCOMP=y
229CONFIG_ISA_DMA_API=y 256CONFIG_ISA_DMA_API=y
@@ -231,10 +258,13 @@ CONFIG_ISA_DMA_API=y
231# 258#
232# Bus options 259# Bus options
233# 260#
261# CONFIG_ISA is not set
234CONFIG_ZONE_DMA=y 262CONFIG_ZONE_DMA=y
235CONFIG_GENERIC_ISA_DMA=y 263CONFIG_GENERIC_ISA_DMA=y
236CONFIG_PPC_INDIRECT_PCI=y 264CONFIG_PPC_INDIRECT_PCI=y
237CONFIG_FSL_SOC=y 265CONFIG_FSL_SOC=y
266CONFIG_FSL_PCI=y
267CONFIG_PPC_PCI_CHOICE=y
238CONFIG_PCI=y 268CONFIG_PCI=y
239CONFIG_PCI_DOMAINS=y 269CONFIG_PCI_DOMAINS=y
240CONFIG_PCI_SYSCALL=y 270CONFIG_PCI_SYSCALL=y
@@ -259,10 +289,6 @@ CONFIG_PAGE_OFFSET=0xc0000000
259CONFIG_KERNEL_START=0xc0000000 289CONFIG_KERNEL_START=0xc0000000
260CONFIG_PHYSICAL_START=0x00000000 290CONFIG_PHYSICAL_START=0x00000000
261CONFIG_TASK_SIZE=0xc0000000 291CONFIG_TASK_SIZE=0xc0000000
262
263#
264# Networking
265#
266CONFIG_NET=y 292CONFIG_NET=y
267 293
268# 294#
@@ -363,6 +389,7 @@ CONFIG_OF_I2C=y
363# CONFIG_PARPORT is not set 389# CONFIG_PARPORT is not set
364CONFIG_BLK_DEV=y 390CONFIG_BLK_DEV=y
365# CONFIG_BLK_DEV_FD is not set 391# CONFIG_BLK_DEV_FD is not set
392# CONFIG_MAC_FLOPPY is not set
366# CONFIG_BLK_CPQ_DA is not set 393# CONFIG_BLK_CPQ_DA is not set
367# CONFIG_BLK_CPQ_CISS_DA is not set 394# CONFIG_BLK_CPQ_CISS_DA is not set
368# CONFIG_BLK_DEV_DAC960 is not set 395# CONFIG_BLK_DEV_DAC960 is not set
@@ -378,12 +405,14 @@ CONFIG_BLK_DEV_RAM_SIZE=32768
378# CONFIG_BLK_DEV_XIP is not set 405# CONFIG_BLK_DEV_XIP is not set
379# CONFIG_CDROM_PKTCDVD is not set 406# CONFIG_CDROM_PKTCDVD is not set
380# CONFIG_ATA_OVER_ETH is not set 407# CONFIG_ATA_OVER_ETH is not set
408# CONFIG_BLK_DEV_HD is not set
381CONFIG_MISC_DEVICES=y 409CONFIG_MISC_DEVICES=y
382# CONFIG_PHANTOM is not set 410# CONFIG_PHANTOM is not set
383# CONFIG_EEPROM_93CX6 is not set 411# CONFIG_EEPROM_93CX6 is not set
384# CONFIG_SGI_IOC4 is not set 412# CONFIG_SGI_IOC4 is not set
385# CONFIG_TIFM_CORE is not set 413# CONFIG_TIFM_CORE is not set
386# CONFIG_ENCLOSURE_SERVICES is not set 414# CONFIG_ENCLOSURE_SERVICES is not set
415# CONFIG_HP_ILO is not set
387CONFIG_HAVE_IDE=y 416CONFIG_HAVE_IDE=y
388# CONFIG_IDE is not set 417# CONFIG_IDE is not set
389 418
@@ -460,7 +489,10 @@ CONFIG_SCSI_LOWLEVEL=y
460# CONFIG_SCSI_DC390T is not set 489# CONFIG_SCSI_DC390T is not set
461# CONFIG_SCSI_NSP32 is not set 490# CONFIG_SCSI_NSP32 is not set
462# CONFIG_SCSI_DEBUG is not set 491# CONFIG_SCSI_DEBUG is not set
492# CONFIG_SCSI_MESH is not set
493# CONFIG_SCSI_MAC53C94 is not set
463# CONFIG_SCSI_SRP is not set 494# CONFIG_SCSI_SRP is not set
495# CONFIG_SCSI_DH is not set
464# CONFIG_ATA is not set 496# CONFIG_ATA is not set
465# CONFIG_MD is not set 497# CONFIG_MD is not set
466# CONFIG_FUSION is not set 498# CONFIG_FUSION is not set
@@ -468,12 +500,15 @@ CONFIG_SCSI_LOWLEVEL=y
468# 500#
469# IEEE 1394 (FireWire) support 501# IEEE 1394 (FireWire) support
470# 502#
503
504#
505# Enable only one of the two stacks, unless you know what you are doing
506#
471# CONFIG_FIREWIRE is not set 507# CONFIG_FIREWIRE is not set
472# CONFIG_IEEE1394 is not set 508# CONFIG_IEEE1394 is not set
473# CONFIG_I2O is not set 509# CONFIG_I2O is not set
474# CONFIG_MACINTOSH_DRIVERS is not set 510# CONFIG_MACINTOSH_DRIVERS is not set
475CONFIG_NETDEVICES=y 511CONFIG_NETDEVICES=y
476# CONFIG_NETDEVICES_MULTIQUEUE is not set
477# CONFIG_DUMMY is not set 512# CONFIG_DUMMY is not set
478# CONFIG_BONDING is not set 513# CONFIG_BONDING is not set
479# CONFIG_MACVLAN is not set 514# CONFIG_MACVLAN is not set
@@ -500,6 +535,8 @@ CONFIG_MARVELL_PHY=y
500# CONFIG_MDIO_BITBANG is not set 535# CONFIG_MDIO_BITBANG is not set
501CONFIG_NET_ETHERNET=y 536CONFIG_NET_ETHERNET=y
502CONFIG_MII=y 537CONFIG_MII=y
538# CONFIG_MACE is not set
539# CONFIG_BMAC is not set
503# CONFIG_HAPPYMEAL is not set 540# CONFIG_HAPPYMEAL is not set
504# CONFIG_SUNGEM is not set 541# CONFIG_SUNGEM is not set
505# CONFIG_CASSINI is not set 542# CONFIG_CASSINI is not set
@@ -517,7 +554,6 @@ CONFIG_NETDEV_1000=y
517# CONFIG_DL2K is not set 554# CONFIG_DL2K is not set
518# CONFIG_E1000 is not set 555# CONFIG_E1000 is not set
519# CONFIG_E1000E is not set 556# CONFIG_E1000E is not set
520# CONFIG_E1000E_ENABLED is not set
521# CONFIG_IP1000 is not set 557# CONFIG_IP1000 is not set
522# CONFIG_IGB is not set 558# CONFIG_IGB is not set
523# CONFIG_NS83820 is not set 559# CONFIG_NS83820 is not set
@@ -532,12 +568,13 @@ CONFIG_NETDEV_1000=y
532# CONFIG_BNX2 is not set 568# CONFIG_BNX2 is not set
533# CONFIG_GIANFAR is not set 569# CONFIG_GIANFAR is not set
534CONFIG_UCC_GETH=y 570CONFIG_UCC_GETH=y
535# CONFIG_UGETH_NAPI is not set
536# CONFIG_UGETH_MAGIC_PACKET is not set 571# CONFIG_UGETH_MAGIC_PACKET is not set
537# CONFIG_UGETH_FILTERING is not set 572# CONFIG_UGETH_FILTERING is not set
538# CONFIG_UGETH_TX_ON_DEMAND is not set 573# CONFIG_UGETH_TX_ON_DEMAND is not set
574# CONFIG_MV643XX_ETH is not set
539# CONFIG_QLA3XXX is not set 575# CONFIG_QLA3XXX is not set
540# CONFIG_ATL1 is not set 576# CONFIG_ATL1 is not set
577# CONFIG_ATL1E is not set
541CONFIG_NETDEV_10000=y 578CONFIG_NETDEV_10000=y
542# CONFIG_CHELSIO_T1 is not set 579# CONFIG_CHELSIO_T1 is not set
543# CONFIG_CHELSIO_T3 is not set 580# CONFIG_CHELSIO_T3 is not set
@@ -626,12 +663,15 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=4
626# CONFIG_SERIAL_UARTLITE is not set 663# CONFIG_SERIAL_UARTLITE is not set
627CONFIG_SERIAL_CORE=y 664CONFIG_SERIAL_CORE=y
628CONFIG_SERIAL_CORE_CONSOLE=y 665CONFIG_SERIAL_CORE_CONSOLE=y
666# CONFIG_SERIAL_PMACZILOG is not set
629# CONFIG_SERIAL_JSM is not set 667# CONFIG_SERIAL_JSM is not set
630# CONFIG_SERIAL_OF_PLATFORM is not set 668# CONFIG_SERIAL_OF_PLATFORM is not set
631# CONFIG_SERIAL_QE is not set 669# CONFIG_SERIAL_QE is not set
632CONFIG_UNIX98_PTYS=y 670CONFIG_UNIX98_PTYS=y
633CONFIG_LEGACY_PTYS=y 671CONFIG_LEGACY_PTYS=y
634CONFIG_LEGACY_PTY_COUNT=256 672CONFIG_LEGACY_PTY_COUNT=256
673# CONFIG_BRIQ_PANEL is not set
674# CONFIG_HVC_RTAS is not set
635# CONFIG_IPMI_HANDLER is not set 675# CONFIG_IPMI_HANDLER is not set
636CONFIG_HW_RANDOM=y 676CONFIG_HW_RANDOM=y
637# CONFIG_NVRAM is not set 677# CONFIG_NVRAM is not set
@@ -643,42 +683,69 @@ CONFIG_DEVPORT=y
643CONFIG_I2C=y 683CONFIG_I2C=y
644CONFIG_I2C_BOARDINFO=y 684CONFIG_I2C_BOARDINFO=y
645CONFIG_I2C_CHARDEV=y 685CONFIG_I2C_CHARDEV=y
686CONFIG_I2C_HELPER_AUTO=y
646 687
647# 688#
648# I2C Hardware Bus support 689# I2C Hardware Bus support
649# 690#
691
692#
693# PC SMBus host controller drivers
694#
650# CONFIG_I2C_ALI1535 is not set 695# CONFIG_I2C_ALI1535 is not set
651# CONFIG_I2C_ALI1563 is not set 696# CONFIG_I2C_ALI1563 is not set
652# CONFIG_I2C_ALI15X3 is not set 697# CONFIG_I2C_ALI15X3 is not set
653# CONFIG_I2C_AMD756 is not set 698# CONFIG_I2C_AMD756 is not set
654# CONFIG_I2C_AMD8111 is not set 699# CONFIG_I2C_AMD8111 is not set
655# CONFIG_I2C_I801 is not set 700# CONFIG_I2C_I801 is not set
656# CONFIG_I2C_I810 is not set 701# CONFIG_I2C_ISCH is not set
657# CONFIG_I2C_PIIX4 is not set 702# CONFIG_I2C_PIIX4 is not set
658CONFIG_I2C_MPC=y
659# CONFIG_I2C_NFORCE2 is not set 703# CONFIG_I2C_NFORCE2 is not set
660# CONFIG_I2C_OCORES is not set
661# CONFIG_I2C_PARPORT_LIGHT is not set
662# CONFIG_I2C_PROSAVAGE is not set
663# CONFIG_I2C_SAVAGE4 is not set
664# CONFIG_I2C_SIMTEC is not set
665# CONFIG_I2C_SIS5595 is not set 704# CONFIG_I2C_SIS5595 is not set
666# CONFIG_I2C_SIS630 is not set 705# CONFIG_I2C_SIS630 is not set
667# CONFIG_I2C_SIS96X is not set 706# CONFIG_I2C_SIS96X is not set
668# CONFIG_I2C_TAOS_EVM is not set
669# CONFIG_I2C_STUB is not set
670# CONFIG_I2C_VIA is not set 707# CONFIG_I2C_VIA is not set
671# CONFIG_I2C_VIAPRO is not set 708# CONFIG_I2C_VIAPRO is not set
709
710#
711# Mac SMBus host controller drivers
712#
713# CONFIG_I2C_HYDRA is not set
714CONFIG_I2C_POWERMAC=y
715
716#
717# I2C system bus drivers (mostly embedded / system-on-chip)
718#
719CONFIG_I2C_MPC=y
720# CONFIG_I2C_OCORES is not set
721# CONFIG_I2C_SIMTEC is not set
722
723#
724# External I2C/SMBus adapter drivers
725#
726# CONFIG_I2C_PARPORT_LIGHT is not set
727# CONFIG_I2C_TAOS_EVM is not set
728
729#
730# Graphics adapter I2C/DDC channel drivers
731#
672# CONFIG_I2C_VOODOO3 is not set 732# CONFIG_I2C_VOODOO3 is not set
733
734#
735# Other I2C/SMBus bus drivers
736#
673# CONFIG_I2C_PCA_PLATFORM is not set 737# CONFIG_I2C_PCA_PLATFORM is not set
738# CONFIG_I2C_STUB is not set
674 739
675# 740#
676# Miscellaneous I2C Chip support 741# Miscellaneous I2C Chip support
677# 742#
678# CONFIG_DS1682 is not set 743# CONFIG_DS1682 is not set
744# CONFIG_AT24 is not set
679# CONFIG_SENSORS_EEPROM is not set 745# CONFIG_SENSORS_EEPROM is not set
680# CONFIG_SENSORS_PCF8574 is not set 746# CONFIG_SENSORS_PCF8574 is not set
681# CONFIG_PCF8575 is not set 747# CONFIG_PCF8575 is not set
748# CONFIG_SENSORS_PCA9539 is not set
682# CONFIG_SENSORS_PCF8591 is not set 749# CONFIG_SENSORS_PCF8591 is not set
683# CONFIG_SENSORS_MAX6875 is not set 750# CONFIG_SENSORS_MAX6875 is not set
684# CONFIG_SENSORS_TSL2550 is not set 751# CONFIG_SENSORS_TSL2550 is not set
@@ -687,10 +754,13 @@ CONFIG_I2C_MPC=y
687# CONFIG_I2C_DEBUG_BUS is not set 754# CONFIG_I2C_DEBUG_BUS is not set
688# CONFIG_I2C_DEBUG_CHIP is not set 755# CONFIG_I2C_DEBUG_CHIP is not set
689# CONFIG_SPI is not set 756# CONFIG_SPI is not set
757CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
758# CONFIG_GPIOLIB is not set
690# CONFIG_W1 is not set 759# CONFIG_W1 is not set
691# CONFIG_POWER_SUPPLY is not set 760# CONFIG_POWER_SUPPLY is not set
692CONFIG_HWMON=y 761CONFIG_HWMON=y
693# CONFIG_HWMON_VID is not set 762# CONFIG_HWMON_VID is not set
763# CONFIG_SENSORS_AD7414 is not set
694# CONFIG_SENSORS_AD7418 is not set 764# CONFIG_SENSORS_AD7418 is not set
695# CONFIG_SENSORS_ADM1021 is not set 765# CONFIG_SENSORS_ADM1021 is not set
696# CONFIG_SENSORS_ADM1025 is not set 766# CONFIG_SENSORS_ADM1025 is not set
@@ -700,6 +770,7 @@ CONFIG_HWMON=y
700# CONFIG_SENSORS_ADM9240 is not set 770# CONFIG_SENSORS_ADM9240 is not set
701# CONFIG_SENSORS_ADT7470 is not set 771# CONFIG_SENSORS_ADT7470 is not set
702# CONFIG_SENSORS_ADT7473 is not set 772# CONFIG_SENSORS_ADT7473 is not set
773# CONFIG_SENSORS_AMS is not set
703# CONFIG_SENSORS_ATXP1 is not set 774# CONFIG_SENSORS_ATXP1 is not set
704# CONFIG_SENSORS_DS1621 is not set 775# CONFIG_SENSORS_DS1621 is not set
705# CONFIG_SENSORS_I5K_AMB is not set 776# CONFIG_SENSORS_I5K_AMB is not set
@@ -744,6 +815,7 @@ CONFIG_HWMON=y
744# CONFIG_SENSORS_W83627EHF is not set 815# CONFIG_SENSORS_W83627EHF is not set
745# CONFIG_HWMON_DEBUG_CHIP is not set 816# CONFIG_HWMON_DEBUG_CHIP is not set
746# CONFIG_THERMAL is not set 817# CONFIG_THERMAL is not set
818# CONFIG_THERMAL_HWMON is not set
747CONFIG_WATCHDOG=y 819CONFIG_WATCHDOG=y
748# CONFIG_WATCHDOG_NOWAYOUT is not set 820# CONFIG_WATCHDOG_NOWAYOUT is not set
749 821
@@ -751,7 +823,9 @@ CONFIG_WATCHDOG=y
751# Watchdog Device Drivers 823# Watchdog Device Drivers
752# 824#
753# CONFIG_SOFT_WATCHDOG is not set 825# CONFIG_SOFT_WATCHDOG is not set
754CONFIG_83xx_WDT=y 826# CONFIG_ALIM7101_WDT is not set
827# CONFIG_8xxx_WDT is not set
828# CONFIG_WATCHDOG_RTAS is not set
755 829
756# 830#
757# PCI-based Watchdog Cards 831# PCI-based Watchdog Cards
@@ -768,8 +842,10 @@ CONFIG_SSB_POSSIBLE=y
768# 842#
769# Multifunction device drivers 843# Multifunction device drivers
770# 844#
845# CONFIG_MFD_CORE is not set
771# CONFIG_MFD_SM501 is not set 846# CONFIG_MFD_SM501 is not set
772# CONFIG_HTC_PASIC3 is not set 847# CONFIG_HTC_PASIC3 is not set
848# CONFIG_MFD_TMIO is not set
773 849
774# 850#
775# Multimedia devices 851# Multimedia devices
@@ -801,10 +877,6 @@ CONFIG_VIDEO_OUTPUT_CONTROL=m
801# Display device support 877# Display device support
802# 878#
803# CONFIG_DISPLAY_SUPPORT is not set 879# CONFIG_DISPLAY_SUPPORT is not set
804
805#
806# Sound
807#
808# CONFIG_SOUND is not set 880# CONFIG_SOUND is not set
809CONFIG_HID_SUPPORT=y 881CONFIG_HID_SUPPORT=y
810CONFIG_HID=y 882CONFIG_HID=y
@@ -819,6 +891,10 @@ CONFIG_USB_ARCH_HAS_EHCI=y
819# CONFIG_USB_OTG_BLACKLIST_HUB is not set 891# CONFIG_USB_OTG_BLACKLIST_HUB is not set
820 892
821# 893#
894# Enable Host or Gadget support to see Inventra options
895#
896
897#
822# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 898# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
823# 899#
824# CONFIG_USB_GADGET is not set 900# CONFIG_USB_GADGET is not set
@@ -857,6 +933,7 @@ CONFIG_RTC_DRV_DS1374=y
857# CONFIG_RTC_DRV_PCF8583 is not set 933# CONFIG_RTC_DRV_PCF8583 is not set
858# CONFIG_RTC_DRV_M41T80 is not set 934# CONFIG_RTC_DRV_M41T80 is not set
859# CONFIG_RTC_DRV_S35390A is not set 935# CONFIG_RTC_DRV_S35390A is not set
936# CONFIG_RTC_DRV_FM3130 is not set
860 937
861# 938#
862# SPI RTC drivers 939# SPI RTC drivers
@@ -945,6 +1022,7 @@ CONFIG_TMPFS=y
945# CONFIG_CRAMFS is not set 1022# CONFIG_CRAMFS is not set
946# CONFIG_VXFS_FS is not set 1023# CONFIG_VXFS_FS is not set
947# CONFIG_MINIX_FS is not set 1024# CONFIG_MINIX_FS is not set
1025# CONFIG_OMFS_FS is not set
948# CONFIG_HPFS_FS is not set 1026# CONFIG_HPFS_FS is not set
949# CONFIG_QNX4FS_FS is not set 1027# CONFIG_QNX4FS_FS is not set
950# CONFIG_ROMFS_FS is not set 1028# CONFIG_ROMFS_FS is not set
@@ -955,14 +1033,13 @@ CONFIG_NFS_FS=y
955CONFIG_NFS_V3=y 1033CONFIG_NFS_V3=y
956# CONFIG_NFS_V3_ACL is not set 1034# CONFIG_NFS_V3_ACL is not set
957CONFIG_NFS_V4=y 1035CONFIG_NFS_V4=y
958# CONFIG_NFSD is not set
959CONFIG_ROOT_NFS=y 1036CONFIG_ROOT_NFS=y
1037# CONFIG_NFSD is not set
960CONFIG_LOCKD=y 1038CONFIG_LOCKD=y
961CONFIG_LOCKD_V4=y 1039CONFIG_LOCKD_V4=y
962CONFIG_NFS_COMMON=y 1040CONFIG_NFS_COMMON=y
963CONFIG_SUNRPC=y 1041CONFIG_SUNRPC=y
964CONFIG_SUNRPC_GSS=y 1042CONFIG_SUNRPC_GSS=y
965# CONFIG_SUNRPC_BIND34 is not set
966CONFIG_RPCSEC_GSS_KRB5=y 1043CONFIG_RPCSEC_GSS_KRB5=y
967# CONFIG_RPCSEC_GSS_SPKM3 is not set 1044# CONFIG_RPCSEC_GSS_SPKM3 is not set
968# CONFIG_SMB_FS is not set 1045# CONFIG_SMB_FS is not set
@@ -992,6 +1069,7 @@ CONFIG_PARTITION_ADVANCED=y
992# CONFIG_DLM is not set 1069# CONFIG_DLM is not set
993CONFIG_UCC_FAST=y 1070CONFIG_UCC_FAST=y
994CONFIG_UCC=y 1071CONFIG_UCC=y
1072# CONFIG_QE_GPIO is not set
995 1073
996# 1074#
997# Library routines 1075# Library routines
@@ -1000,6 +1078,7 @@ CONFIG_BITREVERSE=y
1000# CONFIG_GENERIC_FIND_FIRST_BIT is not set 1078# CONFIG_GENERIC_FIND_FIRST_BIT is not set
1001# CONFIG_CRC_CCITT is not set 1079# CONFIG_CRC_CCITT is not set
1002# CONFIG_CRC16 is not set 1080# CONFIG_CRC16 is not set
1081# CONFIG_CRC_T10DIF is not set
1003# CONFIG_CRC_ITU_T is not set 1082# CONFIG_CRC_ITU_T is not set
1004CONFIG_CRC32=y 1083CONFIG_CRC32=y
1005# CONFIG_CRC7 is not set 1084# CONFIG_CRC7 is not set
@@ -1025,8 +1104,18 @@ CONFIG_FRAME_WARN=1024
1025# CONFIG_SLUB_DEBUG_ON is not set 1104# CONFIG_SLUB_DEBUG_ON is not set
1026# CONFIG_SLUB_STATS is not set 1105# CONFIG_SLUB_STATS is not set
1027# CONFIG_DEBUG_BUGVERBOSE is not set 1106# CONFIG_DEBUG_BUGVERBOSE is not set
1107# CONFIG_DEBUG_MEMORY_INIT is not set
1108# CONFIG_LATENCYTOP is not set
1109CONFIG_SYSCTL_SYSCALL_CHECK=y
1110CONFIG_HAVE_FTRACE=y
1111CONFIG_HAVE_DYNAMIC_FTRACE=y
1112# CONFIG_FTRACE is not set
1113# CONFIG_SCHED_TRACER is not set
1114# CONFIG_CONTEXT_SWITCH_TRACER is not set
1028# CONFIG_SAMPLES is not set 1115# CONFIG_SAMPLES is not set
1116CONFIG_HAVE_ARCH_KGDB=y
1029# CONFIG_IRQSTACKS is not set 1117# CONFIG_IRQSTACKS is not set
1118# CONFIG_BOOTX_TEXT is not set
1030# CONFIG_PPC_EARLY_DEBUG is not set 1119# CONFIG_PPC_EARLY_DEBUG is not set
1031 1120
1032# 1121#
@@ -1080,6 +1169,10 @@ CONFIG_CRYPTO_PCBC=m
1080# CONFIG_CRYPTO_MD4 is not set 1169# CONFIG_CRYPTO_MD4 is not set
1081CONFIG_CRYPTO_MD5=y 1170CONFIG_CRYPTO_MD5=y
1082# CONFIG_CRYPTO_MICHAEL_MIC is not set 1171# CONFIG_CRYPTO_MICHAEL_MIC is not set
1172# CONFIG_CRYPTO_RMD128 is not set
1173# CONFIG_CRYPTO_RMD160 is not set
1174# CONFIG_CRYPTO_RMD256 is not set
1175# CONFIG_CRYPTO_RMD320 is not set
1083# CONFIG_CRYPTO_SHA1 is not set 1176# CONFIG_CRYPTO_SHA1 is not set
1084# CONFIG_CRYPTO_SHA256 is not set 1177# CONFIG_CRYPTO_SHA256 is not set
1085# CONFIG_CRYPTO_SHA512 is not set 1178# CONFIG_CRYPTO_SHA512 is not set
@@ -1112,6 +1205,7 @@ CONFIG_CRYPTO_DES=y
1112# CONFIG_CRYPTO_LZO is not set 1205# CONFIG_CRYPTO_LZO is not set
1113CONFIG_CRYPTO_HW=y 1206CONFIG_CRYPTO_HW=y
1114# CONFIG_CRYPTO_DEV_HIFN_795X is not set 1207# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1208# CONFIG_CRYPTO_DEV_TALITOS is not set
1115# CONFIG_PPC_CLOCK is not set 1209# CONFIG_PPC_CLOCK is not set
1116CONFIG_PPC_LIB_RHEAP=y 1210CONFIG_PPC_LIB_RHEAP=y
1117# CONFIG_VIRTUALIZATION is not set 1211# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/configs/83xx/mpc836x_rdk_defconfig b/arch/powerpc/configs/83xx/mpc836x_rdk_defconfig
index d2c435f0da42..7d674be702fe 100644
--- a/arch/powerpc/configs/83xx/mpc836x_rdk_defconfig
+++ b/arch/powerpc/configs/83xx/mpc836x_rdk_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc2 3# Linux kernel version: 2.6.27-rc4
4# Mon May 19 21:12:32 2008 4# Thu Aug 21 00:52:24 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -16,6 +16,7 @@ CONFIG_6xx=y
16# CONFIG_E200 is not set 16# CONFIG_E200 is not set
17CONFIG_PPC_FPU=y 17CONFIG_PPC_FPU=y
18# CONFIG_FSL_EMB_PERFMON is not set 18# CONFIG_FSL_EMB_PERFMON is not set
19# CONFIG_ALTIVEC is not set
19CONFIG_PPC_STD_MMU=y 20CONFIG_PPC_STD_MMU=y
20CONFIG_PPC_STD_MMU_32=y 21CONFIG_PPC_STD_MMU_32=y
21# CONFIG_PPC_MM_SLICES is not set 22# CONFIG_PPC_MM_SLICES is not set
@@ -32,6 +33,7 @@ CONFIG_GENERIC_HARDIRQS=y
32# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set 33# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
33CONFIG_IRQ_PER_CPU=y 34CONFIG_IRQ_PER_CPU=y
34CONFIG_STACKTRACE_SUPPORT=y 35CONFIG_STACKTRACE_SUPPORT=y
36CONFIG_HAVE_LATENCYTOP_SUPPORT=y
35CONFIG_LOCKDEP_SUPPORT=y 37CONFIG_LOCKDEP_SUPPORT=y
36CONFIG_RWSEM_XCHGADD_ALGORITHM=y 38CONFIG_RWSEM_XCHGADD_ALGORITHM=y
37CONFIG_ARCH_HAS_ILOG2_U32=y 39CONFIG_ARCH_HAS_ILOG2_U32=y
@@ -52,6 +54,9 @@ CONFIG_PPC_UDBG_16550=y
52CONFIG_AUDIT_ARCH=y 54CONFIG_AUDIT_ARCH=y
53CONFIG_GENERIC_BUG=y 55CONFIG_GENERIC_BUG=y
54CONFIG_DEFAULT_UIMAGE=y 56CONFIG_DEFAULT_UIMAGE=y
57CONFIG_HIBERNATE_32=y
58CONFIG_ARCH_HIBERNATION_POSSIBLE=y
59CONFIG_ARCH_SUSPEND_POSSIBLE=y
55# CONFIG_PPC_DCR_NATIVE is not set 60# CONFIG_PPC_DCR_NATIVE is not set
56# CONFIG_PPC_DCR_MMIO is not set 61# CONFIG_PPC_DCR_MMIO is not set
57CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 62CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
@@ -89,12 +94,12 @@ CONFIG_INITRAMFS_SOURCE=""
89CONFIG_SYSCTL=y 94CONFIG_SYSCTL=y
90CONFIG_EMBEDDED=y 95CONFIG_EMBEDDED=y
91CONFIG_SYSCTL_SYSCALL=y 96CONFIG_SYSCTL_SYSCALL=y
92CONFIG_SYSCTL_SYSCALL_CHECK=y
93# CONFIG_KALLSYMS is not set 97# CONFIG_KALLSYMS is not set
94CONFIG_HOTPLUG=y 98CONFIG_HOTPLUG=y
95CONFIG_PRINTK=y 99CONFIG_PRINTK=y
96CONFIG_BUG=y 100CONFIG_BUG=y
97CONFIG_ELF_CORE=y 101CONFIG_ELF_CORE=y
102CONFIG_PCSPKR_PLATFORM=y
98CONFIG_COMPAT_BRK=y 103CONFIG_COMPAT_BRK=y
99CONFIG_BASE_FULL=y 104CONFIG_BASE_FULL=y
100CONFIG_FUTEX=y 105CONFIG_FUTEX=y
@@ -112,10 +117,16 @@ CONFIG_SLUB=y
112# CONFIG_PROFILING is not set 117# CONFIG_PROFILING is not set
113# CONFIG_MARKERS is not set 118# CONFIG_MARKERS is not set
114CONFIG_HAVE_OPROFILE=y 119CONFIG_HAVE_OPROFILE=y
120CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
121CONFIG_HAVE_IOREMAP_PROT=y
115CONFIG_HAVE_KPROBES=y 122CONFIG_HAVE_KPROBES=y
116CONFIG_HAVE_KRETPROBES=y 123CONFIG_HAVE_KRETPROBES=y
124CONFIG_HAVE_ARCH_TRACEHOOK=y
117# CONFIG_HAVE_DMA_ATTRS is not set 125# CONFIG_HAVE_DMA_ATTRS is not set
126# CONFIG_USE_GENERIC_SMP_HELPERS is not set
127# CONFIG_HAVE_CLK is not set
118CONFIG_PROC_PAGE_MONITOR=y 128CONFIG_PROC_PAGE_MONITOR=y
129# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
119CONFIG_SLABINFO=y 130CONFIG_SLABINFO=y
120CONFIG_RT_MUTEXES=y 131CONFIG_RT_MUTEXES=y
121# CONFIG_TINY_SHMEM is not set 132# CONFIG_TINY_SHMEM is not set
@@ -126,12 +137,13 @@ CONFIG_MODULE_UNLOAD=y
126# CONFIG_MODULE_FORCE_UNLOAD is not set 137# CONFIG_MODULE_FORCE_UNLOAD is not set
127# CONFIG_MODVERSIONS is not set 138# CONFIG_MODVERSIONS is not set
128# CONFIG_MODULE_SRCVERSION_ALL is not set 139# CONFIG_MODULE_SRCVERSION_ALL is not set
129# CONFIG_KMOD is not set 140CONFIG_KMOD=y
130CONFIG_BLOCK=y 141CONFIG_BLOCK=y
131# CONFIG_LBD is not set 142# CONFIG_LBD is not set
132# CONFIG_BLK_DEV_IO_TRACE is not set 143# CONFIG_BLK_DEV_IO_TRACE is not set
133# CONFIG_LSF is not set 144# CONFIG_LSF is not set
134# CONFIG_BLK_DEV_BSG is not set 145# CONFIG_BLK_DEV_BSG is not set
146# CONFIG_BLK_DEV_INTEGRITY is not set
135 147
136# 148#
137# IO Schedulers 149# IO Schedulers
@@ -150,16 +162,18 @@ CONFIG_CLASSIC_RCU=y
150# 162#
151# Platform support 163# Platform support
152# 164#
153# CONFIG_PPC_MULTIPLATFORM is not set 165CONFIG_PPC_MULTIPLATFORM=y
154# CONFIG_PPC_82xx is not set 166CONFIG_CLASSIC32=y
155CONFIG_PPC_83xx=y 167CONFIG_PPC_CHRP=y
156# CONFIG_PPC_86xx is not set 168# CONFIG_MPC5121_ADS is not set
157# CONFIG_PPC_MPC512x is not set 169# CONFIG_MPC5121_GENERIC is not set
158# CONFIG_PPC_MPC5121 is not set 170# CONFIG_PPC_MPC52xx is not set
171CONFIG_PPC_PMAC=y
159# CONFIG_PPC_CELL is not set 172# CONFIG_PPC_CELL is not set
160# CONFIG_PPC_CELL_NATIVE is not set 173# CONFIG_PPC_CELL_NATIVE is not set
174# CONFIG_PPC_82xx is not set
161# CONFIG_PQ2ADS is not set 175# CONFIG_PQ2ADS is not set
162CONFIG_MPC83xx=y 176CONFIG_PPC_83xx=y
163# CONFIG_MPC831x_RDB is not set 177# CONFIG_MPC831x_RDB is not set
164# CONFIG_MPC832x_MDS is not set 178# CONFIG_MPC832x_MDS is not set
165# CONFIG_MPC832x_RDB is not set 179# CONFIG_MPC832x_RDB is not set
@@ -170,17 +184,26 @@ CONFIG_MPC836x_RDK=y
170# CONFIG_MPC837x_MDS is not set 184# CONFIG_MPC837x_MDS is not set
171# CONFIG_MPC837x_RDB is not set 185# CONFIG_MPC837x_RDB is not set
172# CONFIG_SBC834x is not set 186# CONFIG_SBC834x is not set
187# CONFIG_ASP834x is not set
188# CONFIG_PPC_86xx is not set
189# CONFIG_EMBEDDED6xx is not set
190CONFIG_PPC_NATIVE=y
191# CONFIG_UDBG_RTAS_CONSOLE is not set
173CONFIG_IPIC=y 192CONFIG_IPIC=y
174# CONFIG_MPIC is not set 193CONFIG_MPIC=y
175# CONFIG_MPIC_WEIRD is not set 194# CONFIG_MPIC_WEIRD is not set
176# CONFIG_PPC_I8259 is not set 195CONFIG_PPC_I8259=y
177# CONFIG_PPC_RTAS is not set 196CONFIG_PPC_RTAS=y
197# CONFIG_RTAS_ERROR_LOGGING is not set
198CONFIG_RTAS_PROC=y
178# CONFIG_MMIO_NVRAM is not set 199# CONFIG_MMIO_NVRAM is not set
179# CONFIG_PPC_MPC106 is not set 200CONFIG_PPC_MPC106=y
180# CONFIG_PPC_970_NAP is not set 201# CONFIG_PPC_970_NAP is not set
181# CONFIG_PPC_INDIRECT_IO is not set 202# CONFIG_PPC_INDIRECT_IO is not set
182# CONFIG_GENERIC_IOMAP is not set 203# CONFIG_GENERIC_IOMAP is not set
183# CONFIG_CPU_FREQ is not set 204# CONFIG_CPU_FREQ is not set
205# CONFIG_PPC601_SYNC_FIX is not set
206# CONFIG_TAU is not set
184CONFIG_QUICC_ENGINE=y 207CONFIG_QUICC_ENGINE=y
185# CONFIG_FSL_ULI1575 is not set 208# CONFIG_FSL_ULI1575 is not set
186 209
@@ -207,6 +230,7 @@ CONFIG_BINFMT_ELF=y
207CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y 230CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
208CONFIG_ARCH_HAS_WALK_MEMORY=y 231CONFIG_ARCH_HAS_WALK_MEMORY=y
209CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y 232CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
233# CONFIG_KEXEC is not set
210CONFIG_ARCH_FLATMEM_ENABLE=y 234CONFIG_ARCH_FLATMEM_ENABLE=y
211CONFIG_ARCH_POPULATES_NODE_MAP=y 235CONFIG_ARCH_POPULATES_NODE_MAP=y
212CONFIG_SELECT_MEMORY_MODEL=y 236CONFIG_SELECT_MEMORY_MODEL=y
@@ -219,6 +243,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
219# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set 243# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
220CONFIG_PAGEFLAGS_EXTENDED=y 244CONFIG_PAGEFLAGS_EXTENDED=y
221CONFIG_SPLIT_PTLOCK_CPUS=4 245CONFIG_SPLIT_PTLOCK_CPUS=4
246CONFIG_MIGRATION=y
222# CONFIG_RESOURCES_64BIT is not set 247# CONFIG_RESOURCES_64BIT is not set
223CONFIG_ZONE_DMA_FLAG=1 248CONFIG_ZONE_DMA_FLAG=1
224CONFIG_BOUNCE=y 249CONFIG_BOUNCE=y
@@ -226,6 +251,7 @@ CONFIG_VIRT_TO_BUS=y
226CONFIG_FORCE_MAX_ZONEORDER=11 251CONFIG_FORCE_MAX_ZONEORDER=11
227CONFIG_PROC_DEVICETREE=y 252CONFIG_PROC_DEVICETREE=y
228# CONFIG_CMDLINE_BOOL is not set 253# CONFIG_CMDLINE_BOOL is not set
254CONFIG_EXTRA_TARGETS=""
229# CONFIG_PM is not set 255# CONFIG_PM is not set
230CONFIG_SECCOMP=y 256CONFIG_SECCOMP=y
231CONFIG_ISA_DMA_API=y 257CONFIG_ISA_DMA_API=y
@@ -233,12 +259,15 @@ CONFIG_ISA_DMA_API=y
233# 259#
234# Bus options 260# Bus options
235# 261#
262# CONFIG_ISA is not set
236CONFIG_ZONE_DMA=y 263CONFIG_ZONE_DMA=y
237CONFIG_GENERIC_ISA_DMA=y 264CONFIG_GENERIC_ISA_DMA=y
238CONFIG_PPC_INDIRECT_PCI=y 265CONFIG_PPC_INDIRECT_PCI=y
239CONFIG_FSL_SOC=y 266CONFIG_FSL_SOC=y
267CONFIG_FSL_PCI=y
240CONFIG_FSL_LBC=y 268CONFIG_FSL_LBC=y
241CONFIG_FSL_GTM=y 269CONFIG_FSL_GTM=y
270CONFIG_PPC_PCI_CHOICE=y
242CONFIG_PCI=y 271CONFIG_PCI=y
243CONFIG_PCI_DOMAINS=y 272CONFIG_PCI_DOMAINS=y
244CONFIG_PCI_SYSCALL=y 273CONFIG_PCI_SYSCALL=y
@@ -263,10 +292,6 @@ CONFIG_PAGE_OFFSET=0xc0000000
263CONFIG_KERNEL_START=0xc0000000 292CONFIG_KERNEL_START=0xc0000000
264CONFIG_PHYSICAL_START=0x00000000 293CONFIG_PHYSICAL_START=0x00000000
265CONFIG_TASK_SIZE=0xc0000000 294CONFIG_TASK_SIZE=0xc0000000
266
267#
268# Networking
269#
270CONFIG_NET=y 295CONFIG_NET=y
271 296
272# 297#
@@ -359,6 +384,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
359CONFIG_STANDALONE=y 384CONFIG_STANDALONE=y
360CONFIG_PREVENT_FIRMWARE_BUILD=y 385CONFIG_PREVENT_FIRMWARE_BUILD=y
361CONFIG_FW_LOADER=y 386CONFIG_FW_LOADER=y
387CONFIG_FIRMWARE_IN_KERNEL=y
388CONFIG_EXTRA_FIRMWARE=""
362# CONFIG_SYS_HYPERVISOR is not set 389# CONFIG_SYS_HYPERVISOR is not set
363# CONFIG_CONNECTOR is not set 390# CONFIG_CONNECTOR is not set
364CONFIG_MTD=y 391CONFIG_MTD=y
@@ -449,9 +476,11 @@ CONFIG_MTD_PHYSMAP_OF=y
449CONFIG_OF_DEVICE=y 476CONFIG_OF_DEVICE=y
450CONFIG_OF_GPIO=y 477CONFIG_OF_GPIO=y
451CONFIG_OF_I2C=y 478CONFIG_OF_I2C=y
479CONFIG_OF_SPI=y
452# CONFIG_PARPORT is not set 480# CONFIG_PARPORT is not set
453CONFIG_BLK_DEV=y 481CONFIG_BLK_DEV=y
454# CONFIG_BLK_DEV_FD is not set 482# CONFIG_BLK_DEV_FD is not set
483# CONFIG_MAC_FLOPPY is not set
455# CONFIG_BLK_CPQ_DA is not set 484# CONFIG_BLK_CPQ_DA is not set
456# CONFIG_BLK_CPQ_CISS_DA is not set 485# CONFIG_BLK_CPQ_CISS_DA is not set
457# CONFIG_BLK_DEV_DAC960 is not set 486# CONFIG_BLK_DEV_DAC960 is not set
@@ -467,12 +496,14 @@ CONFIG_BLK_DEV_RAM_SIZE=32768
467# CONFIG_BLK_DEV_XIP is not set 496# CONFIG_BLK_DEV_XIP is not set
468# CONFIG_CDROM_PKTCDVD is not set 497# CONFIG_CDROM_PKTCDVD is not set
469# CONFIG_ATA_OVER_ETH is not set 498# CONFIG_ATA_OVER_ETH is not set
499# CONFIG_BLK_DEV_HD is not set
470CONFIG_MISC_DEVICES=y 500CONFIG_MISC_DEVICES=y
471# CONFIG_PHANTOM is not set 501# CONFIG_PHANTOM is not set
472# CONFIG_EEPROM_93CX6 is not set 502# CONFIG_EEPROM_93CX6 is not set
473# CONFIG_SGI_IOC4 is not set 503# CONFIG_SGI_IOC4 is not set
474# CONFIG_TIFM_CORE is not set 504# CONFIG_TIFM_CORE is not set
475# CONFIG_ENCLOSURE_SERVICES is not set 505# CONFIG_ENCLOSURE_SERVICES is not set
506# CONFIG_HP_ILO is not set
476CONFIG_HAVE_IDE=y 507CONFIG_HAVE_IDE=y
477# CONFIG_IDE is not set 508# CONFIG_IDE is not set
478 509
@@ -490,12 +521,15 @@ CONFIG_HAVE_IDE=y
490# 521#
491# IEEE 1394 (FireWire) support 522# IEEE 1394 (FireWire) support
492# 523#
524
525#
526# Enable only one of the two stacks, unless you know what you are doing
527#
493# CONFIG_FIREWIRE is not set 528# CONFIG_FIREWIRE is not set
494# CONFIG_IEEE1394 is not set 529# CONFIG_IEEE1394 is not set
495# CONFIG_I2O is not set 530# CONFIG_I2O is not set
496# CONFIG_MACINTOSH_DRIVERS is not set 531# CONFIG_MACINTOSH_DRIVERS is not set
497CONFIG_NETDEVICES=y 532CONFIG_NETDEVICES=y
498# CONFIG_NETDEVICES_MULTIQUEUE is not set
499# CONFIG_DUMMY is not set 533# CONFIG_DUMMY is not set
500# CONFIG_BONDING is not set 534# CONFIG_BONDING is not set
501# CONFIG_MACVLAN is not set 535# CONFIG_MACVLAN is not set
@@ -526,7 +560,6 @@ CONFIG_NETDEV_1000=y
526# CONFIG_DL2K is not set 560# CONFIG_DL2K is not set
527# CONFIG_E1000 is not set 561# CONFIG_E1000 is not set
528# CONFIG_E1000E is not set 562# CONFIG_E1000E is not set
529# CONFIG_E1000E_ENABLED is not set
530# CONFIG_IP1000 is not set 563# CONFIG_IP1000 is not set
531# CONFIG_IGB is not set 564# CONFIG_IGB is not set
532# CONFIG_NS83820 is not set 565# CONFIG_NS83820 is not set
@@ -541,12 +574,13 @@ CONFIG_NETDEV_1000=y
541# CONFIG_BNX2 is not set 574# CONFIG_BNX2 is not set
542# CONFIG_GIANFAR is not set 575# CONFIG_GIANFAR is not set
543CONFIG_UCC_GETH=y 576CONFIG_UCC_GETH=y
544CONFIG_UGETH_NAPI=y
545# CONFIG_UGETH_MAGIC_PACKET is not set 577# CONFIG_UGETH_MAGIC_PACKET is not set
546# CONFIG_UGETH_FILTERING is not set 578# CONFIG_UGETH_FILTERING is not set
547# CONFIG_UGETH_TX_ON_DEMAND is not set 579# CONFIG_UGETH_TX_ON_DEMAND is not set
580# CONFIG_MV643XX_ETH is not set
548# CONFIG_QLA3XXX is not set 581# CONFIG_QLA3XXX is not set
549# CONFIG_ATL1 is not set 582# CONFIG_ATL1 is not set
583# CONFIG_ATL1E is not set
550# CONFIG_NETDEV_10000 is not set 584# CONFIG_NETDEV_10000 is not set
551# CONFIG_TR is not set 585# CONFIG_TR is not set
552 586
@@ -602,6 +636,7 @@ CONFIG_INPUT=y
602# Character devices 636# Character devices
603# 637#
604CONFIG_VT=y 638CONFIG_VT=y
639CONFIG_CONSOLE_TRANSLATIONS=y
605CONFIG_VT_CONSOLE=y 640CONFIG_VT_CONSOLE=y
606CONFIG_HW_CONSOLE=y 641CONFIG_HW_CONSOLE=y
607# CONFIG_VT_HW_CONSOLE_BINDING is not set 642# CONFIG_VT_HW_CONSOLE_BINDING is not set
@@ -625,12 +660,15 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=4
625# CONFIG_SERIAL_UARTLITE is not set 660# CONFIG_SERIAL_UARTLITE is not set
626CONFIG_SERIAL_CORE=y 661CONFIG_SERIAL_CORE=y
627CONFIG_SERIAL_CORE_CONSOLE=y 662CONFIG_SERIAL_CORE_CONSOLE=y
663# CONFIG_SERIAL_PMACZILOG is not set
628# CONFIG_SERIAL_JSM is not set 664# CONFIG_SERIAL_JSM is not set
629# CONFIG_SERIAL_OF_PLATFORM is not set 665# CONFIG_SERIAL_OF_PLATFORM is not set
630CONFIG_SERIAL_QE=y 666CONFIG_SERIAL_QE=y
631CONFIG_UNIX98_PTYS=y 667CONFIG_UNIX98_PTYS=y
632CONFIG_LEGACY_PTYS=y 668CONFIG_LEGACY_PTYS=y
633CONFIG_LEGACY_PTY_COUNT=256 669CONFIG_LEGACY_PTY_COUNT=256
670# CONFIG_BRIQ_PANEL is not set
671# CONFIG_HVC_RTAS is not set
634# CONFIG_IPMI_HANDLER is not set 672# CONFIG_IPMI_HANDLER is not set
635CONFIG_HW_RANDOM=y 673CONFIG_HW_RANDOM=y
636# CONFIG_NVRAM is not set 674# CONFIG_NVRAM is not set
@@ -643,43 +681,70 @@ CONFIG_DEVPORT=y
643CONFIG_I2C=y 681CONFIG_I2C=y
644CONFIG_I2C_BOARDINFO=y 682CONFIG_I2C_BOARDINFO=y
645CONFIG_I2C_CHARDEV=y 683CONFIG_I2C_CHARDEV=y
684CONFIG_I2C_HELPER_AUTO=y
646 685
647# 686#
648# I2C Hardware Bus support 687# I2C Hardware Bus support
649# 688#
689
690#
691# PC SMBus host controller drivers
692#
650# CONFIG_I2C_ALI1535 is not set 693# CONFIG_I2C_ALI1535 is not set
651# CONFIG_I2C_ALI1563 is not set 694# CONFIG_I2C_ALI1563 is not set
652# CONFIG_I2C_ALI15X3 is not set 695# CONFIG_I2C_ALI15X3 is not set
653# CONFIG_I2C_AMD756 is not set 696# CONFIG_I2C_AMD756 is not set
654# CONFIG_I2C_AMD8111 is not set 697# CONFIG_I2C_AMD8111 is not set
655# CONFIG_I2C_GPIO is not set
656# CONFIG_I2C_I801 is not set 698# CONFIG_I2C_I801 is not set
657# CONFIG_I2C_I810 is not set 699# CONFIG_I2C_ISCH is not set
658# CONFIG_I2C_PIIX4 is not set 700# CONFIG_I2C_PIIX4 is not set
659CONFIG_I2C_MPC=y
660# CONFIG_I2C_NFORCE2 is not set 701# CONFIG_I2C_NFORCE2 is not set
661# CONFIG_I2C_OCORES is not set
662# CONFIG_I2C_PARPORT_LIGHT is not set
663# CONFIG_I2C_PROSAVAGE is not set
664# CONFIG_I2C_SAVAGE4 is not set
665# CONFIG_I2C_SIMTEC is not set
666# CONFIG_I2C_SIS5595 is not set 702# CONFIG_I2C_SIS5595 is not set
667# CONFIG_I2C_SIS630 is not set 703# CONFIG_I2C_SIS630 is not set
668# CONFIG_I2C_SIS96X is not set 704# CONFIG_I2C_SIS96X is not set
669# CONFIG_I2C_TAOS_EVM is not set
670# CONFIG_I2C_STUB is not set
671# CONFIG_I2C_VIA is not set 705# CONFIG_I2C_VIA is not set
672# CONFIG_I2C_VIAPRO is not set 706# CONFIG_I2C_VIAPRO is not set
707
708#
709# Mac SMBus host controller drivers
710#
711# CONFIG_I2C_HYDRA is not set
712CONFIG_I2C_POWERMAC=y
713
714#
715# I2C system bus drivers (mostly embedded / system-on-chip)
716#
717# CONFIG_I2C_GPIO is not set
718CONFIG_I2C_MPC=y
719# CONFIG_I2C_OCORES is not set
720# CONFIG_I2C_SIMTEC is not set
721
722#
723# External I2C/SMBus adapter drivers
724#
725# CONFIG_I2C_PARPORT_LIGHT is not set
726# CONFIG_I2C_TAOS_EVM is not set
727
728#
729# Graphics adapter I2C/DDC channel drivers
730#
673# CONFIG_I2C_VOODOO3 is not set 731# CONFIG_I2C_VOODOO3 is not set
732
733#
734# Other I2C/SMBus bus drivers
735#
674# CONFIG_I2C_PCA_PLATFORM is not set 736# CONFIG_I2C_PCA_PLATFORM is not set
737# CONFIG_I2C_STUB is not set
675 738
676# 739#
677# Miscellaneous I2C Chip support 740# Miscellaneous I2C Chip support
678# 741#
679# CONFIG_DS1682 is not set 742# CONFIG_DS1682 is not set
743# CONFIG_AT24 is not set
680# CONFIG_SENSORS_EEPROM is not set 744# CONFIG_SENSORS_EEPROM is not set
681# CONFIG_SENSORS_PCF8574 is not set 745# CONFIG_SENSORS_PCF8574 is not set
682# CONFIG_PCF8575 is not set 746# CONFIG_PCF8575 is not set
747# CONFIG_SENSORS_PCA9539 is not set
683# CONFIG_SENSORS_PCF8591 is not set 748# CONFIG_SENSORS_PCF8591 is not set
684# CONFIG_TPS65010 is not set 749# CONFIG_TPS65010 is not set
685# CONFIG_SENSORS_MAX6875 is not set 750# CONFIG_SENSORS_MAX6875 is not set
@@ -703,26 +768,33 @@ CONFIG_SPI_MPC83xx=y
703# CONFIG_SPI_AT25 is not set 768# CONFIG_SPI_AT25 is not set
704CONFIG_SPI_SPIDEV=y 769CONFIG_SPI_SPIDEV=y
705# CONFIG_SPI_TLE62X0 is not set 770# CONFIG_SPI_TLE62X0 is not set
706CONFIG_HAVE_GPIO_LIB=y 771CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
707 772CONFIG_ARCH_REQUIRE_GPIOLIB=y
708# 773CONFIG_GPIOLIB=y
709# GPIO Support 774# CONFIG_GPIO_SYSFS is not set
710#
711 775
712# 776#
713# I2C GPIO expanders: 777# I2C GPIO expanders:
714# 778#
779# CONFIG_GPIO_MAX732X is not set
715# CONFIG_GPIO_PCA953X is not set 780# CONFIG_GPIO_PCA953X is not set
716# CONFIG_GPIO_PCF857X is not set 781# CONFIG_GPIO_PCF857X is not set
717 782
718# 783#
784# PCI GPIO expanders:
785#
786# CONFIG_GPIO_BT8XX is not set
787
788#
719# SPI GPIO expanders: 789# SPI GPIO expanders:
720# 790#
791# CONFIG_GPIO_MAX7301 is not set
721# CONFIG_GPIO_MCP23S08 is not set 792# CONFIG_GPIO_MCP23S08 is not set
722# CONFIG_W1 is not set 793# CONFIG_W1 is not set
723# CONFIG_POWER_SUPPLY is not set 794# CONFIG_POWER_SUPPLY is not set
724# CONFIG_HWMON is not set 795# CONFIG_HWMON is not set
725# CONFIG_THERMAL is not set 796# CONFIG_THERMAL is not set
797# CONFIG_THERMAL_HWMON is not set
726CONFIG_WATCHDOG=y 798CONFIG_WATCHDOG=y
727# CONFIG_WATCHDOG_NOWAYOUT is not set 799# CONFIG_WATCHDOG_NOWAYOUT is not set
728 800
@@ -730,7 +802,9 @@ CONFIG_WATCHDOG=y
730# Watchdog Device Drivers 802# Watchdog Device Drivers
731# 803#
732# CONFIG_SOFT_WATCHDOG is not set 804# CONFIG_SOFT_WATCHDOG is not set
733CONFIG_83xx_WDT=y 805# CONFIG_ALIM7101_WDT is not set
806# CONFIG_8xxx_WDT is not set
807# CONFIG_WATCHDOG_RTAS is not set
734 808
735# 809#
736# PCI-based Watchdog Cards 810# PCI-based Watchdog Cards
@@ -747,9 +821,10 @@ CONFIG_SSB_POSSIBLE=y
747# 821#
748# Multifunction device drivers 822# Multifunction device drivers
749# 823#
824# CONFIG_MFD_CORE is not set
750# CONFIG_MFD_SM501 is not set 825# CONFIG_MFD_SM501 is not set
751# CONFIG_HTC_EGPIO is not set
752# CONFIG_HTC_PASIC3 is not set 826# CONFIG_HTC_PASIC3 is not set
827# CONFIG_MFD_TMIO is not set
753 828
754# 829#
755# Multimedia devices 830# Multimedia devices
@@ -799,6 +874,9 @@ CONFIG_FB_MACMODES=y
799# CONFIG_FB_PM2 is not set 874# CONFIG_FB_PM2 is not set
800# CONFIG_FB_CYBER2000 is not set 875# CONFIG_FB_CYBER2000 is not set
801CONFIG_FB_OF=y 876CONFIG_FB_OF=y
877# CONFIG_FB_CONTROL is not set
878# CONFIG_FB_PLATINUM is not set
879# CONFIG_FB_VALKYRIE is not set
802# CONFIG_FB_CT65550 is not set 880# CONFIG_FB_CT65550 is not set
803# CONFIG_FB_ASILIANT is not set 881# CONFIG_FB_ASILIANT is not set
804# CONFIG_FB_IMSTT is not set 882# CONFIG_FB_IMSTT is not set
@@ -821,6 +899,7 @@ CONFIG_FB_OF=y
821# CONFIG_FB_TRIDENT is not set 899# CONFIG_FB_TRIDENT is not set
822# CONFIG_FB_ARK is not set 900# CONFIG_FB_ARK is not set
823# CONFIG_FB_PM3 is not set 901# CONFIG_FB_PM3 is not set
902# CONFIG_FB_CARMINE is not set
824# CONFIG_FB_FSL_DIU is not set 903# CONFIG_FB_FSL_DIU is not set
825# CONFIG_FB_IBM_GXT4500 is not set 904# CONFIG_FB_IBM_GXT4500 is not set
826# CONFIG_FB_VIRTUAL is not set 905# CONFIG_FB_VIRTUAL is not set
@@ -846,10 +925,6 @@ CONFIG_LOGO=y
846# CONFIG_LOGO_LINUX_MONO is not set 925# CONFIG_LOGO_LINUX_MONO is not set
847CONFIG_LOGO_LINUX_VGA16=y 926CONFIG_LOGO_LINUX_VGA16=y
848CONFIG_LOGO_LINUX_CLUT224=y 927CONFIG_LOGO_LINUX_CLUT224=y
849
850#
851# Sound
852#
853# CONFIG_SOUND is not set 928# CONFIG_SOUND is not set
854CONFIG_HID_SUPPORT=y 929CONFIG_HID_SUPPORT=y
855CONFIG_HID=y 930CONFIG_HID=y
@@ -941,6 +1016,7 @@ CONFIG_JFFS2_RTIME=y
941# CONFIG_CRAMFS is not set 1016# CONFIG_CRAMFS is not set
942# CONFIG_VXFS_FS is not set 1017# CONFIG_VXFS_FS is not set
943# CONFIG_MINIX_FS is not set 1018# CONFIG_MINIX_FS is not set
1019# CONFIG_OMFS_FS is not set
944# CONFIG_HPFS_FS is not set 1020# CONFIG_HPFS_FS is not set
945# CONFIG_QNX4FS_FS is not set 1021# CONFIG_QNX4FS_FS is not set
946# CONFIG_ROMFS_FS is not set 1022# CONFIG_ROMFS_FS is not set
@@ -951,14 +1027,13 @@ CONFIG_NFS_FS=y
951CONFIG_NFS_V3=y 1027CONFIG_NFS_V3=y
952# CONFIG_NFS_V3_ACL is not set 1028# CONFIG_NFS_V3_ACL is not set
953CONFIG_NFS_V4=y 1029CONFIG_NFS_V4=y
954# CONFIG_NFSD is not set
955CONFIG_ROOT_NFS=y 1030CONFIG_ROOT_NFS=y
1031# CONFIG_NFSD is not set
956CONFIG_LOCKD=y 1032CONFIG_LOCKD=y
957CONFIG_LOCKD_V4=y 1033CONFIG_LOCKD_V4=y
958CONFIG_NFS_COMMON=y 1034CONFIG_NFS_COMMON=y
959CONFIG_SUNRPC=y 1035CONFIG_SUNRPC=y
960CONFIG_SUNRPC_GSS=y 1036CONFIG_SUNRPC_GSS=y
961# CONFIG_SUNRPC_BIND34 is not set
962CONFIG_RPCSEC_GSS_KRB5=y 1037CONFIG_RPCSEC_GSS_KRB5=y
963# CONFIG_RPCSEC_GSS_SPKM3 is not set 1038# CONFIG_RPCSEC_GSS_SPKM3 is not set
964# CONFIG_SMB_FS is not set 1039# CONFIG_SMB_FS is not set
@@ -998,6 +1073,7 @@ CONFIG_BITREVERSE=y
998# CONFIG_GENERIC_FIND_FIRST_BIT is not set 1073# CONFIG_GENERIC_FIND_FIRST_BIT is not set
999# CONFIG_CRC_CCITT is not set 1074# CONFIG_CRC_CCITT is not set
1000# CONFIG_CRC16 is not set 1075# CONFIG_CRC16 is not set
1076# CONFIG_CRC_T10DIF is not set
1001# CONFIG_CRC_ITU_T is not set 1077# CONFIG_CRC_ITU_T is not set
1002CONFIG_CRC32=y 1078CONFIG_CRC32=y
1003# CONFIG_CRC7 is not set 1079# CONFIG_CRC7 is not set
@@ -1025,12 +1101,22 @@ CONFIG_FRAME_WARN=1024
1025# CONFIG_SLUB_DEBUG_ON is not set 1101# CONFIG_SLUB_DEBUG_ON is not set
1026# CONFIG_SLUB_STATS is not set 1102# CONFIG_SLUB_STATS is not set
1027# CONFIG_DEBUG_BUGVERBOSE is not set 1103# CONFIG_DEBUG_BUGVERBOSE is not set
1104# CONFIG_DEBUG_MEMORY_INIT is not set
1105# CONFIG_LATENCYTOP is not set
1106CONFIG_SYSCTL_SYSCALL_CHECK=y
1107CONFIG_HAVE_FTRACE=y
1108CONFIG_HAVE_DYNAMIC_FTRACE=y
1109# CONFIG_FTRACE is not set
1110# CONFIG_SCHED_TRACER is not set
1111# CONFIG_CONTEXT_SWITCH_TRACER is not set
1028# CONFIG_SAMPLES is not set 1112# CONFIG_SAMPLES is not set
1113CONFIG_HAVE_ARCH_KGDB=y
1029# CONFIG_IRQSTACKS is not set 1114# CONFIG_IRQSTACKS is not set
1115# CONFIG_BOOTX_TEXT is not set
1030CONFIG_PPC_EARLY_DEBUG=y 1116CONFIG_PPC_EARLY_DEBUG=y
1031# CONFIG_PPC_EARLY_DEBUG_LPAR is not set 1117# CONFIG_PPC_EARLY_DEBUG_LPAR is not set
1032# CONFIG_PPC_EARLY_DEBUG_G5 is not set 1118# CONFIG_PPC_EARLY_DEBUG_G5 is not set
1033# CONFIG_PPC_EARLY_DEBUG_RTAS_PANEL is not set 1119CONFIG_PPC_EARLY_DEBUG_RTAS_PANEL=y
1034# CONFIG_PPC_EARLY_DEBUG_RTAS_CONSOLE is not set 1120# CONFIG_PPC_EARLY_DEBUG_RTAS_CONSOLE is not set
1035# CONFIG_PPC_EARLY_DEBUG_MAPLE is not set 1121# CONFIG_PPC_EARLY_DEBUG_MAPLE is not set
1036# CONFIG_PPC_EARLY_DEBUG_ISERIES is not set 1122# CONFIG_PPC_EARLY_DEBUG_ISERIES is not set
@@ -1091,6 +1177,10 @@ CONFIG_CRYPTO_CBC=y
1091# CONFIG_CRYPTO_MD4 is not set 1177# CONFIG_CRYPTO_MD4 is not set
1092CONFIG_CRYPTO_MD5=y 1178CONFIG_CRYPTO_MD5=y
1093# CONFIG_CRYPTO_MICHAEL_MIC is not set 1179# CONFIG_CRYPTO_MICHAEL_MIC is not set
1180# CONFIG_CRYPTO_RMD128 is not set
1181# CONFIG_CRYPTO_RMD160 is not set
1182# CONFIG_CRYPTO_RMD256 is not set
1183# CONFIG_CRYPTO_RMD320 is not set
1094# CONFIG_CRYPTO_SHA1 is not set 1184# CONFIG_CRYPTO_SHA1 is not set
1095# CONFIG_CRYPTO_SHA256 is not set 1185# CONFIG_CRYPTO_SHA256 is not set
1096# CONFIG_CRYPTO_SHA512 is not set 1186# CONFIG_CRYPTO_SHA512 is not set
@@ -1123,6 +1213,7 @@ CONFIG_CRYPTO_DES=y
1123# CONFIG_CRYPTO_LZO is not set 1213# CONFIG_CRYPTO_LZO is not set
1124CONFIG_CRYPTO_HW=y 1214CONFIG_CRYPTO_HW=y
1125# CONFIG_CRYPTO_DEV_HIFN_795X is not set 1215# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1216# CONFIG_CRYPTO_DEV_TALITOS is not set
1126# CONFIG_PPC_CLOCK is not set 1217# CONFIG_PPC_CLOCK is not set
1127CONFIG_PPC_LIB_RHEAP=y 1218CONFIG_PPC_LIB_RHEAP=y
1128# CONFIG_VIRTUALIZATION is not set 1219# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/configs/83xx/mpc837x_mds_defconfig b/arch/powerpc/configs/83xx/mpc837x_mds_defconfig
index 0f94d9f56beb..de472022aa81 100644
--- a/arch/powerpc/configs/83xx/mpc837x_mds_defconfig
+++ b/arch/powerpc/configs/83xx/mpc837x_mds_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc5 3# Linux kernel version: 2.6.27-rc4
4# Mon Jun 9 08:52:28 2008 4# Thu Aug 21 00:52:23 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -16,6 +16,7 @@ CONFIG_6xx=y
16# CONFIG_E200 is not set 16# CONFIG_E200 is not set
17CONFIG_PPC_FPU=y 17CONFIG_PPC_FPU=y
18# CONFIG_FSL_EMB_PERFMON is not set 18# CONFIG_FSL_EMB_PERFMON is not set
19# CONFIG_ALTIVEC is not set
19CONFIG_PPC_STD_MMU=y 20CONFIG_PPC_STD_MMU=y
20CONFIG_PPC_STD_MMU_32=y 21CONFIG_PPC_STD_MMU_32=y
21# CONFIG_PPC_MM_SLICES is not set 22# CONFIG_PPC_MM_SLICES is not set
@@ -32,6 +33,7 @@ CONFIG_GENERIC_HARDIRQS=y
32# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set 33# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
33CONFIG_IRQ_PER_CPU=y 34CONFIG_IRQ_PER_CPU=y
34CONFIG_STACKTRACE_SUPPORT=y 35CONFIG_STACKTRACE_SUPPORT=y
36CONFIG_HAVE_LATENCYTOP_SUPPORT=y
35CONFIG_LOCKDEP_SUPPORT=y 37CONFIG_LOCKDEP_SUPPORT=y
36CONFIG_RWSEM_XCHGADD_ALGORITHM=y 38CONFIG_RWSEM_XCHGADD_ALGORITHM=y
37CONFIG_ARCH_HAS_ILOG2_U32=y 39CONFIG_ARCH_HAS_ILOG2_U32=y
@@ -51,6 +53,9 @@ CONFIG_PPC_UDBG_16550=y
51CONFIG_AUDIT_ARCH=y 53CONFIG_AUDIT_ARCH=y
52CONFIG_GENERIC_BUG=y 54CONFIG_GENERIC_BUG=y
53CONFIG_DEFAULT_UIMAGE=y 55CONFIG_DEFAULT_UIMAGE=y
56CONFIG_HIBERNATE_32=y
57CONFIG_ARCH_HIBERNATION_POSSIBLE=y
58CONFIG_ARCH_SUSPEND_POSSIBLE=y
54# CONFIG_PPC_DCR_NATIVE is not set 59# CONFIG_PPC_DCR_NATIVE is not set
55# CONFIG_PPC_DCR_MMIO is not set 60# CONFIG_PPC_DCR_MMIO is not set
56CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 61CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
@@ -88,13 +93,13 @@ CONFIG_INITRAMFS_SOURCE=""
88CONFIG_SYSCTL=y 93CONFIG_SYSCTL=y
89CONFIG_EMBEDDED=y 94CONFIG_EMBEDDED=y
90CONFIG_SYSCTL_SYSCALL=y 95CONFIG_SYSCTL_SYSCALL=y
91CONFIG_SYSCTL_SYSCALL_CHECK=y
92CONFIG_KALLSYMS=y 96CONFIG_KALLSYMS=y
93# CONFIG_KALLSYMS_EXTRA_PASS is not set 97# CONFIG_KALLSYMS_EXTRA_PASS is not set
94CONFIG_HOTPLUG=y 98CONFIG_HOTPLUG=y
95CONFIG_PRINTK=y 99CONFIG_PRINTK=y
96CONFIG_BUG=y 100CONFIG_BUG=y
97CONFIG_ELF_CORE=y 101CONFIG_ELF_CORE=y
102CONFIG_PCSPKR_PLATFORM=y
98CONFIG_COMPAT_BRK=y 103CONFIG_COMPAT_BRK=y
99CONFIG_BASE_FULL=y 104CONFIG_BASE_FULL=y
100CONFIG_FUTEX=y 105CONFIG_FUTEX=y
@@ -112,10 +117,16 @@ CONFIG_SLAB=y
112# CONFIG_MARKERS is not set 117# CONFIG_MARKERS is not set
113CONFIG_HAVE_OPROFILE=y 118CONFIG_HAVE_OPROFILE=y
114# CONFIG_KPROBES is not set 119# CONFIG_KPROBES is not set
120CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
121CONFIG_HAVE_IOREMAP_PROT=y
115CONFIG_HAVE_KPROBES=y 122CONFIG_HAVE_KPROBES=y
116CONFIG_HAVE_KRETPROBES=y 123CONFIG_HAVE_KRETPROBES=y
124CONFIG_HAVE_ARCH_TRACEHOOK=y
117# CONFIG_HAVE_DMA_ATTRS is not set 125# CONFIG_HAVE_DMA_ATTRS is not set
126# CONFIG_USE_GENERIC_SMP_HELPERS is not set
127# CONFIG_HAVE_CLK is not set
118CONFIG_PROC_PAGE_MONITOR=y 128CONFIG_PROC_PAGE_MONITOR=y
129# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
119CONFIG_SLABINFO=y 130CONFIG_SLABINFO=y
120CONFIG_RT_MUTEXES=y 131CONFIG_RT_MUTEXES=y
121# CONFIG_TINY_SHMEM is not set 132# CONFIG_TINY_SHMEM is not set
@@ -126,12 +137,13 @@ CONFIG_MODULE_UNLOAD=y
126# CONFIG_MODULE_FORCE_UNLOAD is not set 137# CONFIG_MODULE_FORCE_UNLOAD is not set
127# CONFIG_MODVERSIONS is not set 138# CONFIG_MODVERSIONS is not set
128# CONFIG_MODULE_SRCVERSION_ALL is not set 139# CONFIG_MODULE_SRCVERSION_ALL is not set
129# CONFIG_KMOD is not set 140CONFIG_KMOD=y
130CONFIG_BLOCK=y 141CONFIG_BLOCK=y
131# CONFIG_LBD is not set 142# CONFIG_LBD is not set
132# CONFIG_BLK_DEV_IO_TRACE is not set 143# CONFIG_BLK_DEV_IO_TRACE is not set
133# CONFIG_LSF is not set 144# CONFIG_LSF is not set
134# CONFIG_BLK_DEV_BSG is not set 145# CONFIG_BLK_DEV_BSG is not set
146# CONFIG_BLK_DEV_INTEGRITY is not set
135 147
136# 148#
137# IO Schedulers 149# IO Schedulers
@@ -150,37 +162,49 @@ CONFIG_CLASSIC_RCU=y
150# 162#
151# Platform support 163# Platform support
152# 164#
153# CONFIG_PPC_MULTIPLATFORM is not set 165CONFIG_PPC_MULTIPLATFORM=y
154# CONFIG_PPC_82xx is not set 166CONFIG_CLASSIC32=y
155CONFIG_PPC_83xx=y 167CONFIG_PPC_CHRP=y
156# CONFIG_PPC_86xx is not set 168# CONFIG_MPC5121_ADS is not set
157# CONFIG_PPC_MPC512x is not set 169# CONFIG_MPC5121_GENERIC is not set
158# CONFIG_PPC_MPC5121 is not set 170# CONFIG_PPC_MPC52xx is not set
171CONFIG_PPC_PMAC=y
159# CONFIG_PPC_CELL is not set 172# CONFIG_PPC_CELL is not set
160# CONFIG_PPC_CELL_NATIVE is not set 173# CONFIG_PPC_CELL_NATIVE is not set
174# CONFIG_PPC_82xx is not set
161# CONFIG_PQ2ADS is not set 175# CONFIG_PQ2ADS is not set
162CONFIG_MPC83xx=y 176CONFIG_PPC_83xx=y
163# CONFIG_MPC831x_RDB is not set 177# CONFIG_MPC831x_RDB is not set
164# CONFIG_MPC832x_MDS is not set 178# CONFIG_MPC832x_MDS is not set
165# CONFIG_MPC832x_RDB is not set 179# CONFIG_MPC832x_RDB is not set
166# CONFIG_MPC834x_MDS is not set 180# CONFIG_MPC834x_MDS is not set
167# CONFIG_MPC834x_ITX is not set 181# CONFIG_MPC834x_ITX is not set
168# CONFIG_MPC836x_MDS is not set 182# CONFIG_MPC836x_MDS is not set
183# CONFIG_MPC836x_RDK is not set
169CONFIG_MPC837x_MDS=y 184CONFIG_MPC837x_MDS=y
170# CONFIG_MPC837x_RDB is not set 185# CONFIG_MPC837x_RDB is not set
171# CONFIG_SBC834x is not set 186# CONFIG_SBC834x is not set
187# CONFIG_ASP834x is not set
172CONFIG_PPC_MPC837x=y 188CONFIG_PPC_MPC837x=y
189# CONFIG_PPC_86xx is not set
190# CONFIG_EMBEDDED6xx is not set
191CONFIG_PPC_NATIVE=y
192# CONFIG_UDBG_RTAS_CONSOLE is not set
173CONFIG_IPIC=y 193CONFIG_IPIC=y
174# CONFIG_MPIC is not set 194CONFIG_MPIC=y
175# CONFIG_MPIC_WEIRD is not set 195# CONFIG_MPIC_WEIRD is not set
176# CONFIG_PPC_I8259 is not set 196CONFIG_PPC_I8259=y
177# CONFIG_PPC_RTAS is not set 197CONFIG_PPC_RTAS=y
198# CONFIG_RTAS_ERROR_LOGGING is not set
199CONFIG_RTAS_PROC=y
178# CONFIG_MMIO_NVRAM is not set 200# CONFIG_MMIO_NVRAM is not set
179# CONFIG_PPC_MPC106 is not set 201CONFIG_PPC_MPC106=y
180# CONFIG_PPC_970_NAP is not set 202# CONFIG_PPC_970_NAP is not set
181# CONFIG_PPC_INDIRECT_IO is not set 203# CONFIG_PPC_INDIRECT_IO is not set
182# CONFIG_GENERIC_IOMAP is not set 204# CONFIG_GENERIC_IOMAP is not set
183# CONFIG_CPU_FREQ is not set 205# CONFIG_CPU_FREQ is not set
206# CONFIG_PPC601_SYNC_FIX is not set
207# CONFIG_TAU is not set
184# CONFIG_FSL_ULI1575 is not set 208# CONFIG_FSL_ULI1575 is not set
185 209
186# 210#
@@ -206,6 +230,7 @@ CONFIG_BINFMT_ELF=y
206CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y 230CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
207CONFIG_ARCH_HAS_WALK_MEMORY=y 231CONFIG_ARCH_HAS_WALK_MEMORY=y
208CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y 232CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
233# CONFIG_KEXEC is not set
209CONFIG_ARCH_FLATMEM_ENABLE=y 234CONFIG_ARCH_FLATMEM_ENABLE=y
210CONFIG_ARCH_POPULATES_NODE_MAP=y 235CONFIG_ARCH_POPULATES_NODE_MAP=y
211CONFIG_SELECT_MEMORY_MODEL=y 236CONFIG_SELECT_MEMORY_MODEL=y
@@ -218,6 +243,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
218# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set 243# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
219CONFIG_PAGEFLAGS_EXTENDED=y 244CONFIG_PAGEFLAGS_EXTENDED=y
220CONFIG_SPLIT_PTLOCK_CPUS=4 245CONFIG_SPLIT_PTLOCK_CPUS=4
246CONFIG_MIGRATION=y
221# CONFIG_RESOURCES_64BIT is not set 247# CONFIG_RESOURCES_64BIT is not set
222CONFIG_ZONE_DMA_FLAG=1 248CONFIG_ZONE_DMA_FLAG=1
223CONFIG_BOUNCE=y 249CONFIG_BOUNCE=y
@@ -225,6 +251,7 @@ CONFIG_VIRT_TO_BUS=y
225CONFIG_FORCE_MAX_ZONEORDER=11 251CONFIG_FORCE_MAX_ZONEORDER=11
226CONFIG_PROC_DEVICETREE=y 252CONFIG_PROC_DEVICETREE=y
227# CONFIG_CMDLINE_BOOL is not set 253# CONFIG_CMDLINE_BOOL is not set
254CONFIG_EXTRA_TARGETS=""
228# CONFIG_PM is not set 255# CONFIG_PM is not set
229CONFIG_SECCOMP=y 256CONFIG_SECCOMP=y
230CONFIG_ISA_DMA_API=y 257CONFIG_ISA_DMA_API=y
@@ -232,15 +259,22 @@ CONFIG_ISA_DMA_API=y
232# 259#
233# Bus options 260# Bus options
234# 261#
262# CONFIG_ISA is not set
235CONFIG_ZONE_DMA=y 263CONFIG_ZONE_DMA=y
236CONFIG_GENERIC_ISA_DMA=y 264CONFIG_GENERIC_ISA_DMA=y
237CONFIG_PPC_INDIRECT_PCI=y 265CONFIG_PPC_INDIRECT_PCI=y
238CONFIG_FSL_SOC=y 266CONFIG_FSL_SOC=y
239# CONFIG_PCI is not set 267CONFIG_FSL_PCI=y
240# CONFIG_PCI_DOMAINS is not set 268CONFIG_PPC_PCI_CHOICE=y
241# CONFIG_PCI_SYSCALL is not set 269CONFIG_PCI=y
242# CONFIG_ARCH_SUPPORTS_MSI is not set 270CONFIG_PCI_DOMAINS=y
271CONFIG_PCI_SYSCALL=y
272# CONFIG_PCIEPORTBUS is not set
273CONFIG_ARCH_SUPPORTS_MSI=y
274# CONFIG_PCI_MSI is not set
275CONFIG_PCI_LEGACY=y
243# CONFIG_PCCARD is not set 276# CONFIG_PCCARD is not set
277# CONFIG_HOTPLUG_PCI is not set
244# CONFIG_HAS_RAPIDIO is not set 278# CONFIG_HAS_RAPIDIO is not set
245 279
246# 280#
@@ -256,10 +290,6 @@ CONFIG_PAGE_OFFSET=0xc0000000
256CONFIG_KERNEL_START=0xc0000000 290CONFIG_KERNEL_START=0xc0000000
257CONFIG_PHYSICAL_START=0x00000000 291CONFIG_PHYSICAL_START=0x00000000
258CONFIG_TASK_SIZE=0xc0000000 292CONFIG_TASK_SIZE=0xc0000000
259
260#
261# Networking
262#
263CONFIG_NET=y 293CONFIG_NET=y
264 294
265# 295#
@@ -360,19 +390,30 @@ CONFIG_OF_I2C=y
360# CONFIG_PARPORT is not set 390# CONFIG_PARPORT is not set
361CONFIG_BLK_DEV=y 391CONFIG_BLK_DEV=y
362# CONFIG_BLK_DEV_FD is not set 392# CONFIG_BLK_DEV_FD is not set
393# CONFIG_MAC_FLOPPY is not set
394# CONFIG_BLK_CPQ_DA is not set
395# CONFIG_BLK_CPQ_CISS_DA is not set
396# CONFIG_BLK_DEV_DAC960 is not set
397# CONFIG_BLK_DEV_UMEM is not set
363# CONFIG_BLK_DEV_COW_COMMON is not set 398# CONFIG_BLK_DEV_COW_COMMON is not set
364CONFIG_BLK_DEV_LOOP=y 399CONFIG_BLK_DEV_LOOP=y
365# CONFIG_BLK_DEV_CRYPTOLOOP is not set 400# CONFIG_BLK_DEV_CRYPTOLOOP is not set
366# CONFIG_BLK_DEV_NBD is not set 401# CONFIG_BLK_DEV_NBD is not set
402# CONFIG_BLK_DEV_SX8 is not set
367CONFIG_BLK_DEV_RAM=y 403CONFIG_BLK_DEV_RAM=y
368CONFIG_BLK_DEV_RAM_COUNT=16 404CONFIG_BLK_DEV_RAM_COUNT=16
369CONFIG_BLK_DEV_RAM_SIZE=32768 405CONFIG_BLK_DEV_RAM_SIZE=32768
370# CONFIG_BLK_DEV_XIP is not set 406# CONFIG_BLK_DEV_XIP is not set
371# CONFIG_CDROM_PKTCDVD is not set 407# CONFIG_CDROM_PKTCDVD is not set
372# CONFIG_ATA_OVER_ETH is not set 408# CONFIG_ATA_OVER_ETH is not set
409# CONFIG_BLK_DEV_HD is not set
373CONFIG_MISC_DEVICES=y 410CONFIG_MISC_DEVICES=y
411# CONFIG_PHANTOM is not set
374# CONFIG_EEPROM_93CX6 is not set 412# CONFIG_EEPROM_93CX6 is not set
413# CONFIG_SGI_IOC4 is not set
414# CONFIG_TIFM_CORE is not set
375# CONFIG_ENCLOSURE_SERVICES is not set 415# CONFIG_ENCLOSURE_SERVICES is not set
416# CONFIG_HP_ILO is not set
376CONFIG_HAVE_IDE=y 417CONFIG_HAVE_IDE=y
377# CONFIG_IDE is not set 418# CONFIG_IDE is not set
378 419
@@ -415,24 +456,128 @@ CONFIG_SCSI_WAIT_SCAN=m
415# CONFIG_SCSI_SRP_ATTRS is not set 456# CONFIG_SCSI_SRP_ATTRS is not set
416CONFIG_SCSI_LOWLEVEL=y 457CONFIG_SCSI_LOWLEVEL=y
417# CONFIG_ISCSI_TCP is not set 458# CONFIG_ISCSI_TCP is not set
459# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
460# CONFIG_SCSI_3W_9XXX is not set
461# CONFIG_SCSI_ACARD is not set
462# CONFIG_SCSI_AACRAID is not set
463# CONFIG_SCSI_AIC7XXX is not set
464# CONFIG_SCSI_AIC7XXX_OLD is not set
465# CONFIG_SCSI_AIC79XX is not set
466# CONFIG_SCSI_AIC94XX is not set
467# CONFIG_SCSI_DPT_I2O is not set
468# CONFIG_SCSI_ADVANSYS is not set
469# CONFIG_SCSI_ARCMSR is not set
470# CONFIG_MEGARAID_NEWGEN is not set
471# CONFIG_MEGARAID_LEGACY is not set
472# CONFIG_MEGARAID_SAS is not set
473# CONFIG_SCSI_HPTIOP is not set
474# CONFIG_SCSI_BUSLOGIC is not set
475# CONFIG_SCSI_DMX3191D is not set
476# CONFIG_SCSI_EATA is not set
477# CONFIG_SCSI_FUTURE_DOMAIN is not set
478# CONFIG_SCSI_GDTH is not set
479# CONFIG_SCSI_IPS is not set
480# CONFIG_SCSI_INITIO is not set
481# CONFIG_SCSI_INIA100 is not set
482# CONFIG_SCSI_MVSAS is not set
483# CONFIG_SCSI_STEX is not set
484# CONFIG_SCSI_SYM53C8XX_2 is not set
485# CONFIG_SCSI_IPR is not set
486# CONFIG_SCSI_QLOGIC_1280 is not set
487# CONFIG_SCSI_QLA_FC is not set
488# CONFIG_SCSI_QLA_ISCSI is not set
489# CONFIG_SCSI_LPFC is not set
490# CONFIG_SCSI_DC395x is not set
491# CONFIG_SCSI_DC390T is not set
492# CONFIG_SCSI_NSP32 is not set
418# CONFIG_SCSI_DEBUG is not set 493# CONFIG_SCSI_DEBUG is not set
494# CONFIG_SCSI_MESH is not set
495# CONFIG_SCSI_MAC53C94 is not set
496# CONFIG_SCSI_SRP is not set
497# CONFIG_SCSI_DH is not set
419CONFIG_ATA=y 498CONFIG_ATA=y
420# CONFIG_ATA_NONSTANDARD is not set 499# CONFIG_ATA_NONSTANDARD is not set
421CONFIG_SATA_PMP=y 500CONFIG_SATA_PMP=y
501# CONFIG_SATA_AHCI is not set
502# CONFIG_SATA_SIL24 is not set
422CONFIG_SATA_FSL=y 503CONFIG_SATA_FSL=y
423CONFIG_ATA_SFF=y 504CONFIG_ATA_SFF=y
505# CONFIG_SATA_SVW is not set
506# CONFIG_ATA_PIIX is not set
424# CONFIG_SATA_MV is not set 507# CONFIG_SATA_MV is not set
508# CONFIG_SATA_NV is not set
509# CONFIG_PDC_ADMA is not set
510# CONFIG_SATA_QSTOR is not set
511# CONFIG_SATA_PROMISE is not set
512# CONFIG_SATA_SX4 is not set
513# CONFIG_SATA_SIL is not set
514# CONFIG_SATA_SIS is not set
515# CONFIG_SATA_ULI is not set
516# CONFIG_SATA_VIA is not set
517# CONFIG_SATA_VITESSE is not set
518# CONFIG_SATA_INIC162X is not set
519# CONFIG_PATA_ALI is not set
520# CONFIG_PATA_AMD is not set
521# CONFIG_PATA_ARTOP is not set
522# CONFIG_PATA_ATIIXP is not set
523# CONFIG_PATA_CMD640_PCI is not set
524# CONFIG_PATA_CMD64X is not set
525# CONFIG_PATA_CS5520 is not set
526# CONFIG_PATA_CS5530 is not set
527# CONFIG_PATA_CYPRESS is not set
528# CONFIG_PATA_EFAR is not set
529# CONFIG_ATA_GENERIC is not set
530# CONFIG_PATA_HPT366 is not set
531# CONFIG_PATA_HPT37X is not set
532# CONFIG_PATA_HPT3X2N is not set
533# CONFIG_PATA_HPT3X3 is not set
534# CONFIG_PATA_IT821X is not set
535# CONFIG_PATA_IT8213 is not set
536# CONFIG_PATA_JMICRON is not set
537# CONFIG_PATA_TRIFLEX is not set
538# CONFIG_PATA_MARVELL is not set
539# CONFIG_PATA_MPIIX is not set
540# CONFIG_PATA_OLDPIIX is not set
541# CONFIG_PATA_NETCELL is not set
542# CONFIG_PATA_NINJA32 is not set
543# CONFIG_PATA_NS87410 is not set
544# CONFIG_PATA_NS87415 is not set
545# CONFIG_PATA_OPTI is not set
546# CONFIG_PATA_OPTIDMA is not set
547# CONFIG_PATA_PDC_OLD is not set
548# CONFIG_PATA_RADISYS is not set
549# CONFIG_PATA_RZ1000 is not set
550# CONFIG_PATA_SC1200 is not set
551# CONFIG_PATA_SERVERWORKS is not set
552# CONFIG_PATA_PDC2027X is not set
553# CONFIG_PATA_SIL680 is not set
554# CONFIG_PATA_SIS is not set
555# CONFIG_PATA_VIA is not set
556# CONFIG_PATA_WINBOND is not set
425# CONFIG_PATA_PLATFORM is not set 557# CONFIG_PATA_PLATFORM is not set
558# CONFIG_PATA_SCH is not set
426# CONFIG_MD is not set 559# CONFIG_MD is not set
560# CONFIG_FUSION is not set
561
562#
563# IEEE 1394 (FireWire) support
564#
565
566#
567# Enable only one of the two stacks, unless you know what you are doing
568#
569# CONFIG_FIREWIRE is not set
570# CONFIG_IEEE1394 is not set
571# CONFIG_I2O is not set
427# CONFIG_MACINTOSH_DRIVERS is not set 572# CONFIG_MACINTOSH_DRIVERS is not set
428CONFIG_NETDEVICES=y 573CONFIG_NETDEVICES=y
429# CONFIG_NETDEVICES_MULTIQUEUE is not set
430# CONFIG_DUMMY is not set 574# CONFIG_DUMMY is not set
431# CONFIG_BONDING is not set 575# CONFIG_BONDING is not set
432# CONFIG_MACVLAN is not set 576# CONFIG_MACVLAN is not set
433# CONFIG_EQUALIZER is not set 577# CONFIG_EQUALIZER is not set
434# CONFIG_TUN is not set 578# CONFIG_TUN is not set
435# CONFIG_VETH is not set 579# CONFIG_VETH is not set
580# CONFIG_ARCNET is not set
436CONFIG_PHYLIB=y 581CONFIG_PHYLIB=y
437 582
438# 583#
@@ -452,16 +597,56 @@ CONFIG_MARVELL_PHY=y
452# CONFIG_MDIO_BITBANG is not set 597# CONFIG_MDIO_BITBANG is not set
453CONFIG_NET_ETHERNET=y 598CONFIG_NET_ETHERNET=y
454CONFIG_MII=y 599CONFIG_MII=y
600# CONFIG_MACE is not set
601# CONFIG_BMAC is not set
602# CONFIG_HAPPYMEAL is not set
603# CONFIG_SUNGEM is not set
604# CONFIG_CASSINI is not set
605# CONFIG_NET_VENDOR_3COM is not set
606# CONFIG_NET_TULIP is not set
607# CONFIG_HP100 is not set
455# CONFIG_IBM_NEW_EMAC_ZMII is not set 608# CONFIG_IBM_NEW_EMAC_ZMII is not set
456# CONFIG_IBM_NEW_EMAC_RGMII is not set 609# CONFIG_IBM_NEW_EMAC_RGMII is not set
457# CONFIG_IBM_NEW_EMAC_TAH is not set 610# CONFIG_IBM_NEW_EMAC_TAH is not set
458# CONFIG_IBM_NEW_EMAC_EMAC4 is not set 611# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
612# CONFIG_NET_PCI is not set
459# CONFIG_B44 is not set 613# CONFIG_B44 is not set
460CONFIG_NETDEV_1000=y 614CONFIG_NETDEV_1000=y
461# CONFIG_E1000E_ENABLED is not set 615# CONFIG_ACENIC is not set
616# CONFIG_DL2K is not set
617# CONFIG_E1000 is not set
618# CONFIG_E1000E is not set
619# CONFIG_IP1000 is not set
620# CONFIG_IGB is not set
621# CONFIG_NS83820 is not set
622# CONFIG_HAMACHI is not set
623# CONFIG_YELLOWFIN is not set
624# CONFIG_R8169 is not set
625# CONFIG_SIS190 is not set
626# CONFIG_SKGE is not set
627# CONFIG_SKY2 is not set
628# CONFIG_VIA_VELOCITY is not set
629# CONFIG_TIGON3 is not set
630# CONFIG_BNX2 is not set
462CONFIG_GIANFAR=y 631CONFIG_GIANFAR=y
463# CONFIG_GFAR_NAPI is not set 632# CONFIG_MV643XX_ETH is not set
633# CONFIG_QLA3XXX is not set
634# CONFIG_ATL1 is not set
635# CONFIG_ATL1E is not set
464CONFIG_NETDEV_10000=y 636CONFIG_NETDEV_10000=y
637# CONFIG_CHELSIO_T1 is not set
638# CONFIG_CHELSIO_T3 is not set
639# CONFIG_IXGBE is not set
640# CONFIG_IXGB is not set
641# CONFIG_S2IO is not set
642# CONFIG_MYRI10GE is not set
643# CONFIG_NETXEN_NIC is not set
644# CONFIG_NIU is not set
645# CONFIG_MLX4_CORE is not set
646# CONFIG_TEHUTI is not set
647# CONFIG_BNX2X is not set
648# CONFIG_SFC is not set
649# CONFIG_TR is not set
465 650
466# 651#
467# Wireless LAN 652# Wireless LAN
@@ -470,8 +655,11 @@ CONFIG_NETDEV_10000=y
470# CONFIG_WLAN_80211 is not set 655# CONFIG_WLAN_80211 is not set
471# CONFIG_IWLWIFI_LEDS is not set 656# CONFIG_IWLWIFI_LEDS is not set
472# CONFIG_WAN is not set 657# CONFIG_WAN is not set
658# CONFIG_FDDI is not set
659# CONFIG_HIPPI is not set
473# CONFIG_PPP is not set 660# CONFIG_PPP is not set
474# CONFIG_SLIP is not set 661# CONFIG_SLIP is not set
662# CONFIG_NET_FC is not set
475# CONFIG_NETCONSOLE is not set 663# CONFIG_NETCONSOLE is not set
476# CONFIG_NETPOLL is not set 664# CONFIG_NETPOLL is not set
477# CONFIG_NET_POLL_CONTROLLER is not set 665# CONFIG_NET_POLL_CONTROLLER is not set
@@ -515,12 +703,14 @@ CONFIG_INPUT=y
515# CONFIG_VT is not set 703# CONFIG_VT is not set
516CONFIG_DEVKMEM=y 704CONFIG_DEVKMEM=y
517# CONFIG_SERIAL_NONSTANDARD is not set 705# CONFIG_SERIAL_NONSTANDARD is not set
706# CONFIG_NOZOMI is not set
518 707
519# 708#
520# Serial drivers 709# Serial drivers
521# 710#
522CONFIG_SERIAL_8250=y 711CONFIG_SERIAL_8250=y
523CONFIG_SERIAL_8250_CONSOLE=y 712CONFIG_SERIAL_8250_CONSOLE=y
713CONFIG_SERIAL_8250_PCI=y
524CONFIG_SERIAL_8250_NR_UARTS=4 714CONFIG_SERIAL_8250_NR_UARTS=4
525CONFIG_SERIAL_8250_RUNTIME_UARTS=4 715CONFIG_SERIAL_8250_RUNTIME_UARTS=4
526# CONFIG_SERIAL_8250_EXTENDED is not set 716# CONFIG_SERIAL_8250_EXTENDED is not set
@@ -531,40 +721,90 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=4
531# CONFIG_SERIAL_UARTLITE is not set 721# CONFIG_SERIAL_UARTLITE is not set
532CONFIG_SERIAL_CORE=y 722CONFIG_SERIAL_CORE=y
533CONFIG_SERIAL_CORE_CONSOLE=y 723CONFIG_SERIAL_CORE_CONSOLE=y
724# CONFIG_SERIAL_PMACZILOG is not set
725# CONFIG_SERIAL_JSM is not set
534# CONFIG_SERIAL_OF_PLATFORM is not set 726# CONFIG_SERIAL_OF_PLATFORM is not set
535CONFIG_UNIX98_PTYS=y 727CONFIG_UNIX98_PTYS=y
536CONFIG_LEGACY_PTYS=y 728CONFIG_LEGACY_PTYS=y
537CONFIG_LEGACY_PTY_COUNT=256 729CONFIG_LEGACY_PTY_COUNT=256
730# CONFIG_BRIQ_PANEL is not set
731# CONFIG_HVC_RTAS is not set
538# CONFIG_IPMI_HANDLER is not set 732# CONFIG_IPMI_HANDLER is not set
539# CONFIG_HW_RANDOM is not set 733# CONFIG_HW_RANDOM is not set
540# CONFIG_NVRAM is not set 734# CONFIG_NVRAM is not set
541CONFIG_GEN_RTC=y 735CONFIG_GEN_RTC=y
542# CONFIG_GEN_RTC_X is not set 736# CONFIG_GEN_RTC_X is not set
543# CONFIG_R3964 is not set 737# CONFIG_R3964 is not set
738# CONFIG_APPLICOM is not set
544# CONFIG_RAW_DRIVER is not set 739# CONFIG_RAW_DRIVER is not set
545# CONFIG_TCG_TPM is not set 740# CONFIG_TCG_TPM is not set
741CONFIG_DEVPORT=y
546CONFIG_I2C=y 742CONFIG_I2C=y
547CONFIG_I2C_BOARDINFO=y 743CONFIG_I2C_BOARDINFO=y
548CONFIG_I2C_CHARDEV=y 744CONFIG_I2C_CHARDEV=y
745CONFIG_I2C_HELPER_AUTO=y
549 746
550# 747#
551# I2C Hardware Bus support 748# I2C Hardware Bus support
552# 749#
750
751#
752# PC SMBus host controller drivers
753#
754# CONFIG_I2C_ALI1535 is not set
755# CONFIG_I2C_ALI1563 is not set
756# CONFIG_I2C_ALI15X3 is not set
757# CONFIG_I2C_AMD756 is not set
758# CONFIG_I2C_AMD8111 is not set
759# CONFIG_I2C_I801 is not set
760# CONFIG_I2C_ISCH is not set
761# CONFIG_I2C_PIIX4 is not set
762# CONFIG_I2C_NFORCE2 is not set
763# CONFIG_I2C_SIS5595 is not set
764# CONFIG_I2C_SIS630 is not set
765# CONFIG_I2C_SIS96X is not set
766# CONFIG_I2C_VIA is not set
767# CONFIG_I2C_VIAPRO is not set
768
769#
770# Mac SMBus host controller drivers
771#
772# CONFIG_I2C_HYDRA is not set
773CONFIG_I2C_POWERMAC=y
774
775#
776# I2C system bus drivers (mostly embedded / system-on-chip)
777#
553CONFIG_I2C_MPC=y 778CONFIG_I2C_MPC=y
554# CONFIG_I2C_OCORES is not set 779# CONFIG_I2C_OCORES is not set
555# CONFIG_I2C_PARPORT_LIGHT is not set
556# CONFIG_I2C_SIMTEC is not set 780# CONFIG_I2C_SIMTEC is not set
781
782#
783# External I2C/SMBus adapter drivers
784#
785# CONFIG_I2C_PARPORT_LIGHT is not set
557# CONFIG_I2C_TAOS_EVM is not set 786# CONFIG_I2C_TAOS_EVM is not set
558# CONFIG_I2C_STUB is not set 787
788#
789# Graphics adapter I2C/DDC channel drivers
790#
791# CONFIG_I2C_VOODOO3 is not set
792
793#
794# Other I2C/SMBus bus drivers
795#
559# CONFIG_I2C_PCA_PLATFORM is not set 796# CONFIG_I2C_PCA_PLATFORM is not set
797# CONFIG_I2C_STUB is not set
560 798
561# 799#
562# Miscellaneous I2C Chip support 800# Miscellaneous I2C Chip support
563# 801#
564# CONFIG_DS1682 is not set 802# CONFIG_DS1682 is not set
803# CONFIG_AT24 is not set
565# CONFIG_SENSORS_EEPROM is not set 804# CONFIG_SENSORS_EEPROM is not set
566# CONFIG_SENSORS_PCF8574 is not set 805# CONFIG_SENSORS_PCF8574 is not set
567# CONFIG_PCF8575 is not set 806# CONFIG_PCF8575 is not set
807# CONFIG_SENSORS_PCA9539 is not set
568# CONFIG_SENSORS_PCF8591 is not set 808# CONFIG_SENSORS_PCF8591 is not set
569# CONFIG_SENSORS_MAX6875 is not set 809# CONFIG_SENSORS_MAX6875 is not set
570# CONFIG_SENSORS_TSL2550 is not set 810# CONFIG_SENSORS_TSL2550 is not set
@@ -573,10 +813,13 @@ CONFIG_I2C_MPC=y
573# CONFIG_I2C_DEBUG_BUS is not set 813# CONFIG_I2C_DEBUG_BUS is not set
574# CONFIG_I2C_DEBUG_CHIP is not set 814# CONFIG_I2C_DEBUG_CHIP is not set
575# CONFIG_SPI is not set 815# CONFIG_SPI is not set
816CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
817# CONFIG_GPIOLIB is not set
576# CONFIG_W1 is not set 818# CONFIG_W1 is not set
577# CONFIG_POWER_SUPPLY is not set 819# CONFIG_POWER_SUPPLY is not set
578CONFIG_HWMON=y 820CONFIG_HWMON=y
579# CONFIG_HWMON_VID is not set 821# CONFIG_HWMON_VID is not set
822# CONFIG_SENSORS_AD7414 is not set
580# CONFIG_SENSORS_AD7418 is not set 823# CONFIG_SENSORS_AD7418 is not set
581# CONFIG_SENSORS_ADM1021 is not set 824# CONFIG_SENSORS_ADM1021 is not set
582# CONFIG_SENSORS_ADM1025 is not set 825# CONFIG_SENSORS_ADM1025 is not set
@@ -586,8 +829,10 @@ CONFIG_HWMON=y
586# CONFIG_SENSORS_ADM9240 is not set 829# CONFIG_SENSORS_ADM9240 is not set
587# CONFIG_SENSORS_ADT7470 is not set 830# CONFIG_SENSORS_ADT7470 is not set
588# CONFIG_SENSORS_ADT7473 is not set 831# CONFIG_SENSORS_ADT7473 is not set
832# CONFIG_SENSORS_AMS is not set
589# CONFIG_SENSORS_ATXP1 is not set 833# CONFIG_SENSORS_ATXP1 is not set
590# CONFIG_SENSORS_DS1621 is not set 834# CONFIG_SENSORS_DS1621 is not set
835# CONFIG_SENSORS_I5K_AMB is not set
591# CONFIG_SENSORS_F71805F is not set 836# CONFIG_SENSORS_F71805F is not set
592# CONFIG_SENSORS_F71882FG is not set 837# CONFIG_SENSORS_F71882FG is not set
593# CONFIG_SENSORS_F75375S is not set 838# CONFIG_SENSORS_F75375S is not set
@@ -609,13 +854,16 @@ CONFIG_HWMON=y
609# CONFIG_SENSORS_MAX6650 is not set 854# CONFIG_SENSORS_MAX6650 is not set
610# CONFIG_SENSORS_PC87360 is not set 855# CONFIG_SENSORS_PC87360 is not set
611# CONFIG_SENSORS_PC87427 is not set 856# CONFIG_SENSORS_PC87427 is not set
857# CONFIG_SENSORS_SIS5595 is not set
612# CONFIG_SENSORS_DME1737 is not set 858# CONFIG_SENSORS_DME1737 is not set
613# CONFIG_SENSORS_SMSC47M1 is not set 859# CONFIG_SENSORS_SMSC47M1 is not set
614# CONFIG_SENSORS_SMSC47M192 is not set 860# CONFIG_SENSORS_SMSC47M192 is not set
615# CONFIG_SENSORS_SMSC47B397 is not set 861# CONFIG_SENSORS_SMSC47B397 is not set
616# CONFIG_SENSORS_ADS7828 is not set 862# CONFIG_SENSORS_ADS7828 is not set
617# CONFIG_SENSORS_THMC50 is not set 863# CONFIG_SENSORS_THMC50 is not set
864# CONFIG_SENSORS_VIA686A is not set
618# CONFIG_SENSORS_VT1211 is not set 865# CONFIG_SENSORS_VT1211 is not set
866# CONFIG_SENSORS_VT8231 is not set
619# CONFIG_SENSORS_W83781D is not set 867# CONFIG_SENSORS_W83781D is not set
620# CONFIG_SENSORS_W83791D is not set 868# CONFIG_SENSORS_W83791D is not set
621# CONFIG_SENSORS_W83792D is not set 869# CONFIG_SENSORS_W83792D is not set
@@ -626,6 +874,7 @@ CONFIG_HWMON=y
626# CONFIG_SENSORS_W83627EHF is not set 874# CONFIG_SENSORS_W83627EHF is not set
627# CONFIG_HWMON_DEBUG_CHIP is not set 875# CONFIG_HWMON_DEBUG_CHIP is not set
628# CONFIG_THERMAL is not set 876# CONFIG_THERMAL is not set
877# CONFIG_THERMAL_HWMON is not set
629CONFIG_WATCHDOG=y 878CONFIG_WATCHDOG=y
630# CONFIG_WATCHDOG_NOWAYOUT is not set 879# CONFIG_WATCHDOG_NOWAYOUT is not set
631 880
@@ -633,7 +882,15 @@ CONFIG_WATCHDOG=y
633# Watchdog Device Drivers 882# Watchdog Device Drivers
634# 883#
635# CONFIG_SOFT_WATCHDOG is not set 884# CONFIG_SOFT_WATCHDOG is not set
636CONFIG_83xx_WDT=y 885# CONFIG_ALIM7101_WDT is not set
886# CONFIG_8xxx_WDT is not set
887# CONFIG_WATCHDOG_RTAS is not set
888
889#
890# PCI-based Watchdog Cards
891#
892# CONFIG_PCIPCWATCHDOG is not set
893# CONFIG_WDTPCI is not set
637 894
638# 895#
639# Sonics Silicon Backplane 896# Sonics Silicon Backplane
@@ -644,8 +901,10 @@ CONFIG_SSB_POSSIBLE=y
644# 901#
645# Multifunction device drivers 902# Multifunction device drivers
646# 903#
904# CONFIG_MFD_CORE is not set
647# CONFIG_MFD_SM501 is not set 905# CONFIG_MFD_SM501 is not set
648# CONFIG_HTC_PASIC3 is not set 906# CONFIG_HTC_PASIC3 is not set
907# CONFIG_MFD_TMIO is not set
649 908
650# 909#
651# Multimedia devices 910# Multimedia devices
@@ -666,6 +925,8 @@ CONFIG_DAB=y
666# 925#
667# Graphics support 926# Graphics support
668# 927#
928# CONFIG_AGP is not set
929# CONFIG_DRM is not set
669# CONFIG_VGASTATE is not set 930# CONFIG_VGASTATE is not set
670CONFIG_VIDEO_OUTPUT_CONTROL=m 931CONFIG_VIDEO_OUTPUT_CONTROL=m
671# CONFIG_FB is not set 932# CONFIG_FB is not set
@@ -675,10 +936,6 @@ CONFIG_VIDEO_OUTPUT_CONTROL=m
675# Display device support 936# Display device support
676# 937#
677# CONFIG_DISPLAY_SUPPORT is not set 938# CONFIG_DISPLAY_SUPPORT is not set
678
679#
680# Sound
681#
682# CONFIG_SOUND is not set 939# CONFIG_SOUND is not set
683CONFIG_HID_SUPPORT=y 940CONFIG_HID_SUPPORT=y
684CONFIG_HID=y 941CONFIG_HID=y
@@ -686,13 +943,17 @@ CONFIG_HID=y
686# CONFIG_HIDRAW is not set 943# CONFIG_HIDRAW is not set
687CONFIG_USB_SUPPORT=y 944CONFIG_USB_SUPPORT=y
688CONFIG_USB_ARCH_HAS_HCD=y 945CONFIG_USB_ARCH_HAS_HCD=y
689# CONFIG_USB_ARCH_HAS_OHCI is not set 946CONFIG_USB_ARCH_HAS_OHCI=y
690CONFIG_USB_ARCH_HAS_EHCI=y 947CONFIG_USB_ARCH_HAS_EHCI=y
691# CONFIG_USB is not set 948# CONFIG_USB is not set
692# CONFIG_USB_OTG_WHITELIST is not set 949# CONFIG_USB_OTG_WHITELIST is not set
693# CONFIG_USB_OTG_BLACKLIST_HUB is not set 950# CONFIG_USB_OTG_BLACKLIST_HUB is not set
694 951
695# 952#
953# Enable Host or Gadget support to see Inventra options
954#
955
956#
696# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 957# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
697# 958#
698# CONFIG_USB_GADGET is not set 959# CONFIG_USB_GADGET is not set
@@ -700,6 +961,7 @@ CONFIG_USB_ARCH_HAS_EHCI=y
700# CONFIG_MEMSTICK is not set 961# CONFIG_MEMSTICK is not set
701# CONFIG_NEW_LEDS is not set 962# CONFIG_NEW_LEDS is not set
702# CONFIG_ACCESSIBILITY is not set 963# CONFIG_ACCESSIBILITY is not set
964# CONFIG_INFINIBAND is not set
703# CONFIG_EDAC is not set 965# CONFIG_EDAC is not set
704# CONFIG_RTC_CLASS is not set 966# CONFIG_RTC_CLASS is not set
705# CONFIG_DMADEVICES is not set 967# CONFIG_DMADEVICES is not set
@@ -769,6 +1031,7 @@ CONFIG_TMPFS=y
769# CONFIG_CRAMFS is not set 1031# CONFIG_CRAMFS is not set
770# CONFIG_VXFS_FS is not set 1032# CONFIG_VXFS_FS is not set
771# CONFIG_MINIX_FS is not set 1033# CONFIG_MINIX_FS is not set
1034# CONFIG_OMFS_FS is not set
772# CONFIG_HPFS_FS is not set 1035# CONFIG_HPFS_FS is not set
773# CONFIG_QNX4FS_FS is not set 1036# CONFIG_QNX4FS_FS is not set
774# CONFIG_ROMFS_FS is not set 1037# CONFIG_ROMFS_FS is not set
@@ -779,14 +1042,13 @@ CONFIG_NFS_FS=y
779CONFIG_NFS_V3=y 1042CONFIG_NFS_V3=y
780# CONFIG_NFS_V3_ACL is not set 1043# CONFIG_NFS_V3_ACL is not set
781CONFIG_NFS_V4=y 1044CONFIG_NFS_V4=y
782# CONFIG_NFSD is not set
783CONFIG_ROOT_NFS=y 1045CONFIG_ROOT_NFS=y
1046# CONFIG_NFSD is not set
784CONFIG_LOCKD=y 1047CONFIG_LOCKD=y
785CONFIG_LOCKD_V4=y 1048CONFIG_LOCKD_V4=y
786CONFIG_NFS_COMMON=y 1049CONFIG_NFS_COMMON=y
787CONFIG_SUNRPC=y 1050CONFIG_SUNRPC=y
788CONFIG_SUNRPC_GSS=y 1051CONFIG_SUNRPC_GSS=y
789# CONFIG_SUNRPC_BIND34 is not set
790CONFIG_RPCSEC_GSS_KRB5=y 1052CONFIG_RPCSEC_GSS_KRB5=y
791# CONFIG_RPCSEC_GSS_SPKM3 is not set 1053# CONFIG_RPCSEC_GSS_SPKM3 is not set
792# CONFIG_SMB_FS is not set 1054# CONFIG_SMB_FS is not set
@@ -826,6 +1088,7 @@ CONFIG_BITREVERSE=y
826# CONFIG_GENERIC_FIND_FIRST_BIT is not set 1088# CONFIG_GENERIC_FIND_FIRST_BIT is not set
827# CONFIG_CRC_CCITT is not set 1089# CONFIG_CRC_CCITT is not set
828# CONFIG_CRC16 is not set 1090# CONFIG_CRC16 is not set
1091CONFIG_CRC_T10DIF=y
829# CONFIG_CRC_ITU_T is not set 1092# CONFIG_CRC_ITU_T is not set
830CONFIG_CRC32=y 1093CONFIG_CRC32=y
831# CONFIG_CRC7 is not set 1094# CONFIG_CRC7 is not set
@@ -849,8 +1112,18 @@ CONFIG_FRAME_WARN=1024
849# CONFIG_HEADERS_CHECK is not set 1112# CONFIG_HEADERS_CHECK is not set
850# CONFIG_DEBUG_KERNEL is not set 1113# CONFIG_DEBUG_KERNEL is not set
851# CONFIG_DEBUG_BUGVERBOSE is not set 1114# CONFIG_DEBUG_BUGVERBOSE is not set
1115# CONFIG_DEBUG_MEMORY_INIT is not set
1116# CONFIG_LATENCYTOP is not set
1117CONFIG_SYSCTL_SYSCALL_CHECK=y
1118CONFIG_HAVE_FTRACE=y
1119CONFIG_HAVE_DYNAMIC_FTRACE=y
1120# CONFIG_FTRACE is not set
1121# CONFIG_SCHED_TRACER is not set
1122# CONFIG_CONTEXT_SWITCH_TRACER is not set
852# CONFIG_SAMPLES is not set 1123# CONFIG_SAMPLES is not set
1124CONFIG_HAVE_ARCH_KGDB=y
853# CONFIG_IRQSTACKS is not set 1125# CONFIG_IRQSTACKS is not set
1126# CONFIG_BOOTX_TEXT is not set
854# CONFIG_PPC_EARLY_DEBUG is not set 1127# CONFIG_PPC_EARLY_DEBUG is not set
855 1128
856# 1129#
@@ -904,6 +1177,10 @@ CONFIG_CRYPTO_PCBC=m
904# CONFIG_CRYPTO_MD4 is not set 1177# CONFIG_CRYPTO_MD4 is not set
905CONFIG_CRYPTO_MD5=y 1178CONFIG_CRYPTO_MD5=y
906# CONFIG_CRYPTO_MICHAEL_MIC is not set 1179# CONFIG_CRYPTO_MICHAEL_MIC is not set
1180# CONFIG_CRYPTO_RMD128 is not set
1181# CONFIG_CRYPTO_RMD160 is not set
1182# CONFIG_CRYPTO_RMD256 is not set
1183# CONFIG_CRYPTO_RMD320 is not set
907# CONFIG_CRYPTO_SHA1 is not set 1184# CONFIG_CRYPTO_SHA1 is not set
908# CONFIG_CRYPTO_SHA256 is not set 1185# CONFIG_CRYPTO_SHA256 is not set
909# CONFIG_CRYPTO_SHA512 is not set 1186# CONFIG_CRYPTO_SHA512 is not set
@@ -935,5 +1212,7 @@ CONFIG_CRYPTO_DES=y
935# CONFIG_CRYPTO_DEFLATE is not set 1212# CONFIG_CRYPTO_DEFLATE is not set
936# CONFIG_CRYPTO_LZO is not set 1213# CONFIG_CRYPTO_LZO is not set
937CONFIG_CRYPTO_HW=y 1214CONFIG_CRYPTO_HW=y
1215# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1216# CONFIG_CRYPTO_DEV_TALITOS is not set
938# CONFIG_PPC_CLOCK is not set 1217# CONFIG_PPC_CLOCK is not set
939# CONFIG_VIRTUALIZATION is not set 1218# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/configs/83xx/mpc837x_rdb_defconfig b/arch/powerpc/configs/83xx/mpc837x_rdb_defconfig
index 0d448556f53a..e8d2d691d26c 100644
--- a/arch/powerpc/configs/83xx/mpc837x_rdb_defconfig
+++ b/arch/powerpc/configs/83xx/mpc837x_rdb_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc5 3# Linux kernel version: 2.6.27-rc4
4# Tue Jun 10 09:17:12 2008 4# Thu Aug 21 00:52:25 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -16,6 +16,7 @@ CONFIG_6xx=y
16# CONFIG_E200 is not set 16# CONFIG_E200 is not set
17CONFIG_PPC_FPU=y 17CONFIG_PPC_FPU=y
18# CONFIG_FSL_EMB_PERFMON is not set 18# CONFIG_FSL_EMB_PERFMON is not set
19# CONFIG_ALTIVEC is not set
19CONFIG_PPC_STD_MMU=y 20CONFIG_PPC_STD_MMU=y
20CONFIG_PPC_STD_MMU_32=y 21CONFIG_PPC_STD_MMU_32=y
21# CONFIG_PPC_MM_SLICES is not set 22# CONFIG_PPC_MM_SLICES is not set
@@ -32,6 +33,7 @@ CONFIG_GENERIC_HARDIRQS=y
32# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set 33# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
33CONFIG_IRQ_PER_CPU=y 34CONFIG_IRQ_PER_CPU=y
34CONFIG_STACKTRACE_SUPPORT=y 35CONFIG_STACKTRACE_SUPPORT=y
36CONFIG_HAVE_LATENCYTOP_SUPPORT=y
35CONFIG_LOCKDEP_SUPPORT=y 37CONFIG_LOCKDEP_SUPPORT=y
36CONFIG_RWSEM_XCHGADD_ALGORITHM=y 38CONFIG_RWSEM_XCHGADD_ALGORITHM=y
37CONFIG_ARCH_HAS_ILOG2_U32=y 39CONFIG_ARCH_HAS_ILOG2_U32=y
@@ -51,6 +53,9 @@ CONFIG_PPC_UDBG_16550=y
51CONFIG_AUDIT_ARCH=y 53CONFIG_AUDIT_ARCH=y
52CONFIG_GENERIC_BUG=y 54CONFIG_GENERIC_BUG=y
53CONFIG_DEFAULT_UIMAGE=y 55CONFIG_DEFAULT_UIMAGE=y
56CONFIG_HIBERNATE_32=y
57CONFIG_ARCH_HIBERNATION_POSSIBLE=y
58CONFIG_ARCH_SUSPEND_POSSIBLE=y
54# CONFIG_PPC_DCR_NATIVE is not set 59# CONFIG_PPC_DCR_NATIVE is not set
55# CONFIG_PPC_DCR_MMIO is not set 60# CONFIG_PPC_DCR_MMIO is not set
56CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 61CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
@@ -88,13 +93,13 @@ CONFIG_INITRAMFS_SOURCE=""
88CONFIG_SYSCTL=y 93CONFIG_SYSCTL=y
89CONFIG_EMBEDDED=y 94CONFIG_EMBEDDED=y
90CONFIG_SYSCTL_SYSCALL=y 95CONFIG_SYSCTL_SYSCALL=y
91CONFIG_SYSCTL_SYSCALL_CHECK=y
92CONFIG_KALLSYMS=y 96CONFIG_KALLSYMS=y
93# CONFIG_KALLSYMS_EXTRA_PASS is not set 97# CONFIG_KALLSYMS_EXTRA_PASS is not set
94CONFIG_HOTPLUG=y 98CONFIG_HOTPLUG=y
95CONFIG_PRINTK=y 99CONFIG_PRINTK=y
96CONFIG_BUG=y 100CONFIG_BUG=y
97CONFIG_ELF_CORE=y 101CONFIG_ELF_CORE=y
102CONFIG_PCSPKR_PLATFORM=y
98CONFIG_COMPAT_BRK=y 103CONFIG_COMPAT_BRK=y
99CONFIG_BASE_FULL=y 104CONFIG_BASE_FULL=y
100CONFIG_FUTEX=y 105CONFIG_FUTEX=y
@@ -112,10 +117,16 @@ CONFIG_SLAB=y
112# CONFIG_MARKERS is not set 117# CONFIG_MARKERS is not set
113CONFIG_HAVE_OPROFILE=y 118CONFIG_HAVE_OPROFILE=y
114# CONFIG_KPROBES is not set 119# CONFIG_KPROBES is not set
120CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
121CONFIG_HAVE_IOREMAP_PROT=y
115CONFIG_HAVE_KPROBES=y 122CONFIG_HAVE_KPROBES=y
116CONFIG_HAVE_KRETPROBES=y 123CONFIG_HAVE_KRETPROBES=y
124CONFIG_HAVE_ARCH_TRACEHOOK=y
117# CONFIG_HAVE_DMA_ATTRS is not set 125# CONFIG_HAVE_DMA_ATTRS is not set
126# CONFIG_USE_GENERIC_SMP_HELPERS is not set
127# CONFIG_HAVE_CLK is not set
118CONFIG_PROC_PAGE_MONITOR=y 128CONFIG_PROC_PAGE_MONITOR=y
129# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
119CONFIG_SLABINFO=y 130CONFIG_SLABINFO=y
120CONFIG_RT_MUTEXES=y 131CONFIG_RT_MUTEXES=y
121# CONFIG_TINY_SHMEM is not set 132# CONFIG_TINY_SHMEM is not set
@@ -126,12 +137,13 @@ CONFIG_MODULE_UNLOAD=y
126# CONFIG_MODULE_FORCE_UNLOAD is not set 137# CONFIG_MODULE_FORCE_UNLOAD is not set
127# CONFIG_MODVERSIONS is not set 138# CONFIG_MODVERSIONS is not set
128# CONFIG_MODULE_SRCVERSION_ALL is not set 139# CONFIG_MODULE_SRCVERSION_ALL is not set
129# CONFIG_KMOD is not set 140CONFIG_KMOD=y
130CONFIG_BLOCK=y 141CONFIG_BLOCK=y
131# CONFIG_LBD is not set 142# CONFIG_LBD is not set
132# CONFIG_BLK_DEV_IO_TRACE is not set 143# CONFIG_BLK_DEV_IO_TRACE is not set
133# CONFIG_LSF is not set 144# CONFIG_LSF is not set
134# CONFIG_BLK_DEV_BSG is not set 145# CONFIG_BLK_DEV_BSG is not set
146# CONFIG_BLK_DEV_INTEGRITY is not set
135 147
136# 148#
137# IO Schedulers 149# IO Schedulers
@@ -150,37 +162,49 @@ CONFIG_CLASSIC_RCU=y
150# 162#
151# Platform support 163# Platform support
152# 164#
153# CONFIG_PPC_MULTIPLATFORM is not set 165CONFIG_PPC_MULTIPLATFORM=y
154# CONFIG_PPC_82xx is not set 166CONFIG_CLASSIC32=y
155CONFIG_PPC_83xx=y 167CONFIG_PPC_CHRP=y
156# CONFIG_PPC_86xx is not set 168# CONFIG_MPC5121_ADS is not set
157# CONFIG_PPC_MPC512x is not set 169# CONFIG_MPC5121_GENERIC is not set
158# CONFIG_PPC_MPC5121 is not set 170# CONFIG_PPC_MPC52xx is not set
171CONFIG_PPC_PMAC=y
159# CONFIG_PPC_CELL is not set 172# CONFIG_PPC_CELL is not set
160# CONFIG_PPC_CELL_NATIVE is not set 173# CONFIG_PPC_CELL_NATIVE is not set
174# CONFIG_PPC_82xx is not set
161# CONFIG_PQ2ADS is not set 175# CONFIG_PQ2ADS is not set
162CONFIG_MPC83xx=y 176CONFIG_PPC_83xx=y
163# CONFIG_MPC831x_RDB is not set 177# CONFIG_MPC831x_RDB is not set
164# CONFIG_MPC832x_MDS is not set 178# CONFIG_MPC832x_MDS is not set
165# CONFIG_MPC832x_RDB is not set 179# CONFIG_MPC832x_RDB is not set
166# CONFIG_MPC834x_MDS is not set 180# CONFIG_MPC834x_MDS is not set
167# CONFIG_MPC834x_ITX is not set 181# CONFIG_MPC834x_ITX is not set
168# CONFIG_MPC836x_MDS is not set 182# CONFIG_MPC836x_MDS is not set
183# CONFIG_MPC836x_RDK is not set
169# CONFIG_MPC837x_MDS is not set 184# CONFIG_MPC837x_MDS is not set
170CONFIG_MPC837x_RDB=y 185CONFIG_MPC837x_RDB=y
171# CONFIG_SBC834x is not set 186# CONFIG_SBC834x is not set
187# CONFIG_ASP834x is not set
172CONFIG_PPC_MPC837x=y 188CONFIG_PPC_MPC837x=y
189# CONFIG_PPC_86xx is not set
190# CONFIG_EMBEDDED6xx is not set
191CONFIG_PPC_NATIVE=y
192# CONFIG_UDBG_RTAS_CONSOLE is not set
173CONFIG_IPIC=y 193CONFIG_IPIC=y
174# CONFIG_MPIC is not set 194CONFIG_MPIC=y
175# CONFIG_MPIC_WEIRD is not set 195# CONFIG_MPIC_WEIRD is not set
176# CONFIG_PPC_I8259 is not set 196CONFIG_PPC_I8259=y
177# CONFIG_PPC_RTAS is not set 197CONFIG_PPC_RTAS=y
198# CONFIG_RTAS_ERROR_LOGGING is not set
199CONFIG_RTAS_PROC=y
178# CONFIG_MMIO_NVRAM is not set 200# CONFIG_MMIO_NVRAM is not set
179# CONFIG_PPC_MPC106 is not set 201CONFIG_PPC_MPC106=y
180# CONFIG_PPC_970_NAP is not set 202# CONFIG_PPC_970_NAP is not set
181# CONFIG_PPC_INDIRECT_IO is not set 203# CONFIG_PPC_INDIRECT_IO is not set
182# CONFIG_GENERIC_IOMAP is not set 204# CONFIG_GENERIC_IOMAP is not set
183# CONFIG_CPU_FREQ is not set 205# CONFIG_CPU_FREQ is not set
206# CONFIG_PPC601_SYNC_FIX is not set
207# CONFIG_TAU is not set
184# CONFIG_FSL_ULI1575 is not set 208# CONFIG_FSL_ULI1575 is not set
185 209
186# 210#
@@ -206,6 +230,7 @@ CONFIG_BINFMT_ELF=y
206CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y 230CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
207CONFIG_ARCH_HAS_WALK_MEMORY=y 231CONFIG_ARCH_HAS_WALK_MEMORY=y
208CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y 232CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
233# CONFIG_KEXEC is not set
209CONFIG_ARCH_FLATMEM_ENABLE=y 234CONFIG_ARCH_FLATMEM_ENABLE=y
210CONFIG_ARCH_POPULATES_NODE_MAP=y 235CONFIG_ARCH_POPULATES_NODE_MAP=y
211CONFIG_SELECT_MEMORY_MODEL=y 236CONFIG_SELECT_MEMORY_MODEL=y
@@ -218,6 +243,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
218# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set 243# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
219CONFIG_PAGEFLAGS_EXTENDED=y 244CONFIG_PAGEFLAGS_EXTENDED=y
220CONFIG_SPLIT_PTLOCK_CPUS=4 245CONFIG_SPLIT_PTLOCK_CPUS=4
246CONFIG_MIGRATION=y
221# CONFIG_RESOURCES_64BIT is not set 247# CONFIG_RESOURCES_64BIT is not set
222CONFIG_ZONE_DMA_FLAG=1 248CONFIG_ZONE_DMA_FLAG=1
223CONFIG_BOUNCE=y 249CONFIG_BOUNCE=y
@@ -225,6 +251,7 @@ CONFIG_VIRT_TO_BUS=y
225CONFIG_FORCE_MAX_ZONEORDER=11 251CONFIG_FORCE_MAX_ZONEORDER=11
226CONFIG_PROC_DEVICETREE=y 252CONFIG_PROC_DEVICETREE=y
227# CONFIG_CMDLINE_BOOL is not set 253# CONFIG_CMDLINE_BOOL is not set
254CONFIG_EXTRA_TARGETS=""
228# CONFIG_PM is not set 255# CONFIG_PM is not set
229CONFIG_SECCOMP=y 256CONFIG_SECCOMP=y
230CONFIG_ISA_DMA_API=y 257CONFIG_ISA_DMA_API=y
@@ -232,15 +259,22 @@ CONFIG_ISA_DMA_API=y
232# 259#
233# Bus options 260# Bus options
234# 261#
262# CONFIG_ISA is not set
235CONFIG_ZONE_DMA=y 263CONFIG_ZONE_DMA=y
236CONFIG_GENERIC_ISA_DMA=y 264CONFIG_GENERIC_ISA_DMA=y
237CONFIG_PPC_INDIRECT_PCI=y 265CONFIG_PPC_INDIRECT_PCI=y
238CONFIG_FSL_SOC=y 266CONFIG_FSL_SOC=y
239# CONFIG_PCI is not set 267CONFIG_FSL_PCI=y
240# CONFIG_PCI_DOMAINS is not set 268CONFIG_PPC_PCI_CHOICE=y
241# CONFIG_PCI_SYSCALL is not set 269CONFIG_PCI=y
242# CONFIG_ARCH_SUPPORTS_MSI is not set 270CONFIG_PCI_DOMAINS=y
271CONFIG_PCI_SYSCALL=y
272# CONFIG_PCIEPORTBUS is not set
273CONFIG_ARCH_SUPPORTS_MSI=y
274# CONFIG_PCI_MSI is not set
275CONFIG_PCI_LEGACY=y
243# CONFIG_PCCARD is not set 276# CONFIG_PCCARD is not set
277# CONFIG_HOTPLUG_PCI is not set
244# CONFIG_HAS_RAPIDIO is not set 278# CONFIG_HAS_RAPIDIO is not set
245 279
246# 280#
@@ -256,10 +290,6 @@ CONFIG_PAGE_OFFSET=0xc0000000
256CONFIG_KERNEL_START=0xc0000000 290CONFIG_KERNEL_START=0xc0000000
257CONFIG_PHYSICAL_START=0x00000000 291CONFIG_PHYSICAL_START=0x00000000
258CONFIG_TASK_SIZE=0xc0000000 292CONFIG_TASK_SIZE=0xc0000000
259
260#
261# Networking
262#
263CONFIG_NET=y 293CONFIG_NET=y
264 294
265# 295#
@@ -355,10 +385,16 @@ CONFIG_OF_I2C=y
355# CONFIG_PARPORT is not set 385# CONFIG_PARPORT is not set
356CONFIG_BLK_DEV=y 386CONFIG_BLK_DEV=y
357# CONFIG_BLK_DEV_FD is not set 387# CONFIG_BLK_DEV_FD is not set
388# CONFIG_MAC_FLOPPY is not set
389# CONFIG_BLK_CPQ_DA is not set
390# CONFIG_BLK_CPQ_CISS_DA is not set
391# CONFIG_BLK_DEV_DAC960 is not set
392# CONFIG_BLK_DEV_UMEM is not set
358# CONFIG_BLK_DEV_COW_COMMON is not set 393# CONFIG_BLK_DEV_COW_COMMON is not set
359CONFIG_BLK_DEV_LOOP=y 394CONFIG_BLK_DEV_LOOP=y
360# CONFIG_BLK_DEV_CRYPTOLOOP is not set 395# CONFIG_BLK_DEV_CRYPTOLOOP is not set
361# CONFIG_BLK_DEV_NBD is not set 396# CONFIG_BLK_DEV_NBD is not set
397# CONFIG_BLK_DEV_SX8 is not set
362# CONFIG_BLK_DEV_UB is not set 398# CONFIG_BLK_DEV_UB is not set
363CONFIG_BLK_DEV_RAM=y 399CONFIG_BLK_DEV_RAM=y
364CONFIG_BLK_DEV_RAM_COUNT=16 400CONFIG_BLK_DEV_RAM_COUNT=16
@@ -366,9 +402,14 @@ CONFIG_BLK_DEV_RAM_SIZE=32768
366# CONFIG_BLK_DEV_XIP is not set 402# CONFIG_BLK_DEV_XIP is not set
367# CONFIG_CDROM_PKTCDVD is not set 403# CONFIG_CDROM_PKTCDVD is not set
368# CONFIG_ATA_OVER_ETH is not set 404# CONFIG_ATA_OVER_ETH is not set
405# CONFIG_BLK_DEV_HD is not set
369CONFIG_MISC_DEVICES=y 406CONFIG_MISC_DEVICES=y
407# CONFIG_PHANTOM is not set
370# CONFIG_EEPROM_93CX6 is not set 408# CONFIG_EEPROM_93CX6 is not set
409# CONFIG_SGI_IOC4 is not set
410# CONFIG_TIFM_CORE is not set
371# CONFIG_ENCLOSURE_SERVICES is not set 411# CONFIG_ENCLOSURE_SERVICES is not set
412# CONFIG_HP_ILO is not set
372CONFIG_HAVE_IDE=y 413CONFIG_HAVE_IDE=y
373# CONFIG_IDE is not set 414# CONFIG_IDE is not set
374 415
@@ -411,14 +452,106 @@ CONFIG_SCSI_WAIT_SCAN=m
411# CONFIG_SCSI_SRP_ATTRS is not set 452# CONFIG_SCSI_SRP_ATTRS is not set
412CONFIG_SCSI_LOWLEVEL=y 453CONFIG_SCSI_LOWLEVEL=y
413# CONFIG_ISCSI_TCP is not set 454# CONFIG_ISCSI_TCP is not set
455# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
456# CONFIG_SCSI_3W_9XXX is not set
457# CONFIG_SCSI_ACARD is not set
458# CONFIG_SCSI_AACRAID is not set
459# CONFIG_SCSI_AIC7XXX is not set
460# CONFIG_SCSI_AIC7XXX_OLD is not set
461# CONFIG_SCSI_AIC79XX is not set
462# CONFIG_SCSI_AIC94XX is not set
463# CONFIG_SCSI_DPT_I2O is not set
464# CONFIG_SCSI_ADVANSYS is not set
465# CONFIG_SCSI_ARCMSR is not set
466# CONFIG_MEGARAID_NEWGEN is not set
467# CONFIG_MEGARAID_LEGACY is not set
468# CONFIG_MEGARAID_SAS is not set
469# CONFIG_SCSI_HPTIOP is not set
470# CONFIG_SCSI_BUSLOGIC is not set
471# CONFIG_SCSI_DMX3191D is not set
472# CONFIG_SCSI_EATA is not set
473# CONFIG_SCSI_FUTURE_DOMAIN is not set
474# CONFIG_SCSI_GDTH is not set
475# CONFIG_SCSI_IPS is not set
476# CONFIG_SCSI_INITIO is not set
477# CONFIG_SCSI_INIA100 is not set
478# CONFIG_SCSI_MVSAS is not set
479# CONFIG_SCSI_STEX is not set
480# CONFIG_SCSI_SYM53C8XX_2 is not set
481# CONFIG_SCSI_IPR is not set
482# CONFIG_SCSI_QLOGIC_1280 is not set
483# CONFIG_SCSI_QLA_FC is not set
484# CONFIG_SCSI_QLA_ISCSI is not set
485# CONFIG_SCSI_LPFC is not set
486# CONFIG_SCSI_DC395x is not set
487# CONFIG_SCSI_DC390T is not set
488# CONFIG_SCSI_NSP32 is not set
414# CONFIG_SCSI_DEBUG is not set 489# CONFIG_SCSI_DEBUG is not set
490# CONFIG_SCSI_MESH is not set
491# CONFIG_SCSI_MAC53C94 is not set
492# CONFIG_SCSI_SRP is not set
493# CONFIG_SCSI_DH is not set
415CONFIG_ATA=y 494CONFIG_ATA=y
416# CONFIG_ATA_NONSTANDARD is not set 495# CONFIG_ATA_NONSTANDARD is not set
417CONFIG_SATA_PMP=y 496CONFIG_SATA_PMP=y
497# CONFIG_SATA_AHCI is not set
498# CONFIG_SATA_SIL24 is not set
418CONFIG_SATA_FSL=y 499CONFIG_SATA_FSL=y
419CONFIG_ATA_SFF=y 500CONFIG_ATA_SFF=y
501# CONFIG_SATA_SVW is not set
502# CONFIG_ATA_PIIX is not set
420# CONFIG_SATA_MV is not set 503# CONFIG_SATA_MV is not set
504# CONFIG_SATA_NV is not set
505# CONFIG_PDC_ADMA is not set
506# CONFIG_SATA_QSTOR is not set
507# CONFIG_SATA_PROMISE is not set
508# CONFIG_SATA_SX4 is not set
509# CONFIG_SATA_SIL is not set
510# CONFIG_SATA_SIS is not set
511# CONFIG_SATA_ULI is not set
512# CONFIG_SATA_VIA is not set
513# CONFIG_SATA_VITESSE is not set
514# CONFIG_SATA_INIC162X is not set
515# CONFIG_PATA_ALI is not set
516# CONFIG_PATA_AMD is not set
517# CONFIG_PATA_ARTOP is not set
518# CONFIG_PATA_ATIIXP is not set
519# CONFIG_PATA_CMD640_PCI is not set
520# CONFIG_PATA_CMD64X is not set
521# CONFIG_PATA_CS5520 is not set
522# CONFIG_PATA_CS5530 is not set
523# CONFIG_PATA_CYPRESS is not set
524# CONFIG_PATA_EFAR is not set
525# CONFIG_ATA_GENERIC is not set
526# CONFIG_PATA_HPT366 is not set
527# CONFIG_PATA_HPT37X is not set
528# CONFIG_PATA_HPT3X2N is not set
529# CONFIG_PATA_HPT3X3 is not set
530# CONFIG_PATA_IT821X is not set
531# CONFIG_PATA_IT8213 is not set
532# CONFIG_PATA_JMICRON is not set
533# CONFIG_PATA_TRIFLEX is not set
534# CONFIG_PATA_MARVELL is not set
535# CONFIG_PATA_MPIIX is not set
536# CONFIG_PATA_OLDPIIX is not set
537# CONFIG_PATA_NETCELL is not set
538# CONFIG_PATA_NINJA32 is not set
539# CONFIG_PATA_NS87410 is not set
540# CONFIG_PATA_NS87415 is not set
541# CONFIG_PATA_OPTI is not set
542# CONFIG_PATA_OPTIDMA is not set
543# CONFIG_PATA_PDC_OLD is not set
544# CONFIG_PATA_RADISYS is not set
545# CONFIG_PATA_RZ1000 is not set
546# CONFIG_PATA_SC1200 is not set
547# CONFIG_PATA_SERVERWORKS is not set
548# CONFIG_PATA_PDC2027X is not set
549# CONFIG_PATA_SIL680 is not set
550# CONFIG_PATA_SIS is not set
551# CONFIG_PATA_VIA is not set
552# CONFIG_PATA_WINBOND is not set
421# CONFIG_PATA_PLATFORM is not set 553# CONFIG_PATA_PLATFORM is not set
554# CONFIG_PATA_SCH is not set
422CONFIG_MD=y 555CONFIG_MD=y
423CONFIG_BLK_DEV_MD=y 556CONFIG_BLK_DEV_MD=y
424# CONFIG_MD_LINEAR is not set 557# CONFIG_MD_LINEAR is not set
@@ -430,15 +563,27 @@ CONFIG_MD_RAID5_RESHAPE=y
430# CONFIG_MD_MULTIPATH is not set 563# CONFIG_MD_MULTIPATH is not set
431# CONFIG_MD_FAULTY is not set 564# CONFIG_MD_FAULTY is not set
432# CONFIG_BLK_DEV_DM is not set 565# CONFIG_BLK_DEV_DM is not set
566# CONFIG_FUSION is not set
567
568#
569# IEEE 1394 (FireWire) support
570#
571
572#
573# Enable only one of the two stacks, unless you know what you are doing
574#
575# CONFIG_FIREWIRE is not set
576# CONFIG_IEEE1394 is not set
577# CONFIG_I2O is not set
433# CONFIG_MACINTOSH_DRIVERS is not set 578# CONFIG_MACINTOSH_DRIVERS is not set
434CONFIG_NETDEVICES=y 579CONFIG_NETDEVICES=y
435# CONFIG_NETDEVICES_MULTIQUEUE is not set
436# CONFIG_DUMMY is not set 580# CONFIG_DUMMY is not set
437# CONFIG_BONDING is not set 581# CONFIG_BONDING is not set
438# CONFIG_MACVLAN is not set 582# CONFIG_MACVLAN is not set
439# CONFIG_EQUALIZER is not set 583# CONFIG_EQUALIZER is not set
440# CONFIG_TUN is not set 584# CONFIG_TUN is not set
441# CONFIG_VETH is not set 585# CONFIG_VETH is not set
586# CONFIG_ARCNET is not set
442CONFIG_PHYLIB=y 587CONFIG_PHYLIB=y
443 588
444# 589#
@@ -458,16 +603,44 @@ CONFIG_FIXED_PHY=y
458# CONFIG_MDIO_BITBANG is not set 603# CONFIG_MDIO_BITBANG is not set
459CONFIG_NET_ETHERNET=y 604CONFIG_NET_ETHERNET=y
460CONFIG_MII=y 605CONFIG_MII=y
606# CONFIG_MACE is not set
607# CONFIG_BMAC is not set
608# CONFIG_HAPPYMEAL is not set
609# CONFIG_SUNGEM is not set
610# CONFIG_CASSINI is not set
611# CONFIG_NET_VENDOR_3COM is not set
612# CONFIG_NET_TULIP is not set
613# CONFIG_HP100 is not set
461# CONFIG_IBM_NEW_EMAC_ZMII is not set 614# CONFIG_IBM_NEW_EMAC_ZMII is not set
462# CONFIG_IBM_NEW_EMAC_RGMII is not set 615# CONFIG_IBM_NEW_EMAC_RGMII is not set
463# CONFIG_IBM_NEW_EMAC_TAH is not set 616# CONFIG_IBM_NEW_EMAC_TAH is not set
464# CONFIG_IBM_NEW_EMAC_EMAC4 is not set 617# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
618# CONFIG_NET_PCI is not set
465# CONFIG_B44 is not set 619# CONFIG_B44 is not set
466CONFIG_NETDEV_1000=y 620CONFIG_NETDEV_1000=y
467# CONFIG_E1000E_ENABLED is not set 621# CONFIG_ACENIC is not set
622# CONFIG_DL2K is not set
623# CONFIG_E1000 is not set
624# CONFIG_E1000E is not set
625# CONFIG_IP1000 is not set
626# CONFIG_IGB is not set
627# CONFIG_NS83820 is not set
628# CONFIG_HAMACHI is not set
629# CONFIG_YELLOWFIN is not set
630# CONFIG_R8169 is not set
631# CONFIG_SIS190 is not set
632# CONFIG_SKGE is not set
633# CONFIG_SKY2 is not set
634# CONFIG_VIA_VELOCITY is not set
635# CONFIG_TIGON3 is not set
636# CONFIG_BNX2 is not set
468CONFIG_GIANFAR=y 637CONFIG_GIANFAR=y
469CONFIG_GFAR_NAPI=y 638# CONFIG_MV643XX_ETH is not set
639# CONFIG_QLA3XXX is not set
640# CONFIG_ATL1 is not set
641# CONFIG_ATL1E is not set
470# CONFIG_NETDEV_10000 is not set 642# CONFIG_NETDEV_10000 is not set
643# CONFIG_TR is not set
471 644
472# 645#
473# Wireless LAN 646# Wireless LAN
@@ -485,8 +658,11 @@ CONFIG_GFAR_NAPI=y
485# CONFIG_USB_RTL8150 is not set 658# CONFIG_USB_RTL8150 is not set
486# CONFIG_USB_USBNET is not set 659# CONFIG_USB_USBNET is not set
487# CONFIG_WAN is not set 660# CONFIG_WAN is not set
661# CONFIG_FDDI is not set
662# CONFIG_HIPPI is not set
488# CONFIG_PPP is not set 663# CONFIG_PPP is not set
489# CONFIG_SLIP is not set 664# CONFIG_SLIP is not set
665# CONFIG_NET_FC is not set
490# CONFIG_NETCONSOLE is not set 666# CONFIG_NETCONSOLE is not set
491# CONFIG_NETPOLL is not set 667# CONFIG_NETPOLL is not set
492# CONFIG_NET_POLL_CONTROLLER is not set 668# CONFIG_NET_POLL_CONTROLLER is not set
@@ -530,12 +706,14 @@ CONFIG_INPUT=y
530# CONFIG_VT is not set 706# CONFIG_VT is not set
531CONFIG_DEVKMEM=y 707CONFIG_DEVKMEM=y
532# CONFIG_SERIAL_NONSTANDARD is not set 708# CONFIG_SERIAL_NONSTANDARD is not set
709# CONFIG_NOZOMI is not set
533 710
534# 711#
535# Serial drivers 712# Serial drivers
536# 713#
537CONFIG_SERIAL_8250=y 714CONFIG_SERIAL_8250=y
538CONFIG_SERIAL_8250_CONSOLE=y 715CONFIG_SERIAL_8250_CONSOLE=y
716CONFIG_SERIAL_8250_PCI=y
539CONFIG_SERIAL_8250_NR_UARTS=4 717CONFIG_SERIAL_8250_NR_UARTS=4
540CONFIG_SERIAL_8250_RUNTIME_UARTS=4 718CONFIG_SERIAL_8250_RUNTIME_UARTS=4
541# CONFIG_SERIAL_8250_EXTENDED is not set 719# CONFIG_SERIAL_8250_EXTENDED is not set
@@ -546,41 +724,91 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=4
546# CONFIG_SERIAL_UARTLITE is not set 724# CONFIG_SERIAL_UARTLITE is not set
547CONFIG_SERIAL_CORE=y 725CONFIG_SERIAL_CORE=y
548CONFIG_SERIAL_CORE_CONSOLE=y 726CONFIG_SERIAL_CORE_CONSOLE=y
727# CONFIG_SERIAL_PMACZILOG is not set
728# CONFIG_SERIAL_JSM is not set
549# CONFIG_SERIAL_OF_PLATFORM is not set 729# CONFIG_SERIAL_OF_PLATFORM is not set
550CONFIG_UNIX98_PTYS=y 730CONFIG_UNIX98_PTYS=y
551CONFIG_LEGACY_PTYS=y 731CONFIG_LEGACY_PTYS=y
552CONFIG_LEGACY_PTY_COUNT=256 732CONFIG_LEGACY_PTY_COUNT=256
733# CONFIG_BRIQ_PANEL is not set
734# CONFIG_HVC_RTAS is not set
553# CONFIG_IPMI_HANDLER is not set 735# CONFIG_IPMI_HANDLER is not set
554# CONFIG_HW_RANDOM is not set 736# CONFIG_HW_RANDOM is not set
555# CONFIG_NVRAM is not set 737# CONFIG_NVRAM is not set
556CONFIG_GEN_RTC=y 738CONFIG_GEN_RTC=y
557# CONFIG_GEN_RTC_X is not set 739# CONFIG_GEN_RTC_X is not set
558# CONFIG_R3964 is not set 740# CONFIG_R3964 is not set
741# CONFIG_APPLICOM is not set
559# CONFIG_RAW_DRIVER is not set 742# CONFIG_RAW_DRIVER is not set
560# CONFIG_TCG_TPM is not set 743# CONFIG_TCG_TPM is not set
744CONFIG_DEVPORT=y
561CONFIG_I2C=y 745CONFIG_I2C=y
562CONFIG_I2C_BOARDINFO=y 746CONFIG_I2C_BOARDINFO=y
563CONFIG_I2C_CHARDEV=y 747CONFIG_I2C_CHARDEV=y
748CONFIG_I2C_HELPER_AUTO=y
564 749
565# 750#
566# I2C Hardware Bus support 751# I2C Hardware Bus support
567# 752#
753
754#
755# PC SMBus host controller drivers
756#
757# CONFIG_I2C_ALI1535 is not set
758# CONFIG_I2C_ALI1563 is not set
759# CONFIG_I2C_ALI15X3 is not set
760# CONFIG_I2C_AMD756 is not set
761# CONFIG_I2C_AMD8111 is not set
762# CONFIG_I2C_I801 is not set
763# CONFIG_I2C_ISCH is not set
764# CONFIG_I2C_PIIX4 is not set
765# CONFIG_I2C_NFORCE2 is not set
766# CONFIG_I2C_SIS5595 is not set
767# CONFIG_I2C_SIS630 is not set
768# CONFIG_I2C_SIS96X is not set
769# CONFIG_I2C_VIA is not set
770# CONFIG_I2C_VIAPRO is not set
771
772#
773# Mac SMBus host controller drivers
774#
775# CONFIG_I2C_HYDRA is not set
776CONFIG_I2C_POWERMAC=y
777
778#
779# I2C system bus drivers (mostly embedded / system-on-chip)
780#
568CONFIG_I2C_MPC=y 781CONFIG_I2C_MPC=y
569# CONFIG_I2C_OCORES is not set 782# CONFIG_I2C_OCORES is not set
570# CONFIG_I2C_PARPORT_LIGHT is not set
571# CONFIG_I2C_SIMTEC is not set 783# CONFIG_I2C_SIMTEC is not set
784
785#
786# External I2C/SMBus adapter drivers
787#
788# CONFIG_I2C_PARPORT_LIGHT is not set
572# CONFIG_I2C_TAOS_EVM is not set 789# CONFIG_I2C_TAOS_EVM is not set
573# CONFIG_I2C_STUB is not set
574# CONFIG_I2C_TINY_USB is not set 790# CONFIG_I2C_TINY_USB is not set
791
792#
793# Graphics adapter I2C/DDC channel drivers
794#
795# CONFIG_I2C_VOODOO3 is not set
796
797#
798# Other I2C/SMBus bus drivers
799#
575# CONFIG_I2C_PCA_PLATFORM is not set 800# CONFIG_I2C_PCA_PLATFORM is not set
801# CONFIG_I2C_STUB is not set
576 802
577# 803#
578# Miscellaneous I2C Chip support 804# Miscellaneous I2C Chip support
579# 805#
580# CONFIG_DS1682 is not set 806# CONFIG_DS1682 is not set
807# CONFIG_AT24 is not set
581# CONFIG_SENSORS_EEPROM is not set 808# CONFIG_SENSORS_EEPROM is not set
582# CONFIG_SENSORS_PCF8574 is not set 809# CONFIG_SENSORS_PCF8574 is not set
583# CONFIG_PCF8575 is not set 810# CONFIG_PCF8575 is not set
811# CONFIG_SENSORS_PCA9539 is not set
584# CONFIG_SENSORS_PCF8591 is not set 812# CONFIG_SENSORS_PCF8591 is not set
585# CONFIG_SENSORS_MAX6875 is not set 813# CONFIG_SENSORS_MAX6875 is not set
586# CONFIG_SENSORS_TSL2550 is not set 814# CONFIG_SENSORS_TSL2550 is not set
@@ -589,10 +817,13 @@ CONFIG_I2C_MPC=y
589# CONFIG_I2C_DEBUG_BUS is not set 817# CONFIG_I2C_DEBUG_BUS is not set
590# CONFIG_I2C_DEBUG_CHIP is not set 818# CONFIG_I2C_DEBUG_CHIP is not set
591# CONFIG_SPI is not set 819# CONFIG_SPI is not set
820CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
821# CONFIG_GPIOLIB is not set
592# CONFIG_W1 is not set 822# CONFIG_W1 is not set
593# CONFIG_POWER_SUPPLY is not set 823# CONFIG_POWER_SUPPLY is not set
594CONFIG_HWMON=y 824CONFIG_HWMON=y
595# CONFIG_HWMON_VID is not set 825# CONFIG_HWMON_VID is not set
826# CONFIG_SENSORS_AD7414 is not set
596# CONFIG_SENSORS_AD7418 is not set 827# CONFIG_SENSORS_AD7418 is not set
597# CONFIG_SENSORS_ADM1021 is not set 828# CONFIG_SENSORS_ADM1021 is not set
598# CONFIG_SENSORS_ADM1025 is not set 829# CONFIG_SENSORS_ADM1025 is not set
@@ -602,8 +833,10 @@ CONFIG_HWMON=y
602# CONFIG_SENSORS_ADM9240 is not set 833# CONFIG_SENSORS_ADM9240 is not set
603# CONFIG_SENSORS_ADT7470 is not set 834# CONFIG_SENSORS_ADT7470 is not set
604# CONFIG_SENSORS_ADT7473 is not set 835# CONFIG_SENSORS_ADT7473 is not set
836# CONFIG_SENSORS_AMS is not set
605# CONFIG_SENSORS_ATXP1 is not set 837# CONFIG_SENSORS_ATXP1 is not set
606# CONFIG_SENSORS_DS1621 is not set 838# CONFIG_SENSORS_DS1621 is not set
839# CONFIG_SENSORS_I5K_AMB is not set
607# CONFIG_SENSORS_F71805F is not set 840# CONFIG_SENSORS_F71805F is not set
608# CONFIG_SENSORS_F71882FG is not set 841# CONFIG_SENSORS_F71882FG is not set
609# CONFIG_SENSORS_F75375S is not set 842# CONFIG_SENSORS_F75375S is not set
@@ -625,13 +858,16 @@ CONFIG_HWMON=y
625# CONFIG_SENSORS_MAX6650 is not set 858# CONFIG_SENSORS_MAX6650 is not set
626# CONFIG_SENSORS_PC87360 is not set 859# CONFIG_SENSORS_PC87360 is not set
627# CONFIG_SENSORS_PC87427 is not set 860# CONFIG_SENSORS_PC87427 is not set
861# CONFIG_SENSORS_SIS5595 is not set
628# CONFIG_SENSORS_DME1737 is not set 862# CONFIG_SENSORS_DME1737 is not set
629# CONFIG_SENSORS_SMSC47M1 is not set 863# CONFIG_SENSORS_SMSC47M1 is not set
630# CONFIG_SENSORS_SMSC47M192 is not set 864# CONFIG_SENSORS_SMSC47M192 is not set
631# CONFIG_SENSORS_SMSC47B397 is not set 865# CONFIG_SENSORS_SMSC47B397 is not set
632# CONFIG_SENSORS_ADS7828 is not set 866# CONFIG_SENSORS_ADS7828 is not set
633# CONFIG_SENSORS_THMC50 is not set 867# CONFIG_SENSORS_THMC50 is not set
868# CONFIG_SENSORS_VIA686A is not set
634# CONFIG_SENSORS_VT1211 is not set 869# CONFIG_SENSORS_VT1211 is not set
870# CONFIG_SENSORS_VT8231 is not set
635# CONFIG_SENSORS_W83781D is not set 871# CONFIG_SENSORS_W83781D is not set
636# CONFIG_SENSORS_W83791D is not set 872# CONFIG_SENSORS_W83791D is not set
637# CONFIG_SENSORS_W83792D is not set 873# CONFIG_SENSORS_W83792D is not set
@@ -642,6 +878,7 @@ CONFIG_HWMON=y
642# CONFIG_SENSORS_W83627EHF is not set 878# CONFIG_SENSORS_W83627EHF is not set
643# CONFIG_HWMON_DEBUG_CHIP is not set 879# CONFIG_HWMON_DEBUG_CHIP is not set
644# CONFIG_THERMAL is not set 880# CONFIG_THERMAL is not set
881# CONFIG_THERMAL_HWMON is not set
645CONFIG_WATCHDOG=y 882CONFIG_WATCHDOG=y
646# CONFIG_WATCHDOG_NOWAYOUT is not set 883# CONFIG_WATCHDOG_NOWAYOUT is not set
647 884
@@ -649,7 +886,15 @@ CONFIG_WATCHDOG=y
649# Watchdog Device Drivers 886# Watchdog Device Drivers
650# 887#
651# CONFIG_SOFT_WATCHDOG is not set 888# CONFIG_SOFT_WATCHDOG is not set
652CONFIG_83xx_WDT=y 889# CONFIG_ALIM7101_WDT is not set
890# CONFIG_8xxx_WDT is not set
891# CONFIG_WATCHDOG_RTAS is not set
892
893#
894# PCI-based Watchdog Cards
895#
896# CONFIG_PCIPCWATCHDOG is not set
897# CONFIG_WDTPCI is not set
653 898
654# 899#
655# USB-based Watchdog Cards 900# USB-based Watchdog Cards
@@ -665,8 +910,10 @@ CONFIG_SSB_POSSIBLE=y
665# 910#
666# Multifunction device drivers 911# Multifunction device drivers
667# 912#
913# CONFIG_MFD_CORE is not set
668# CONFIG_MFD_SM501 is not set 914# CONFIG_MFD_SM501 is not set
669# CONFIG_HTC_PASIC3 is not set 915# CONFIG_HTC_PASIC3 is not set
916# CONFIG_MFD_TMIO is not set
670 917
671# 918#
672# Multimedia devices 919# Multimedia devices
@@ -688,6 +935,8 @@ CONFIG_DAB=y
688# 935#
689# Graphics support 936# Graphics support
690# 937#
938# CONFIG_AGP is not set
939# CONFIG_DRM is not set
691# CONFIG_VGASTATE is not set 940# CONFIG_VGASTATE is not set
692CONFIG_VIDEO_OUTPUT_CONTROL=m 941CONFIG_VIDEO_OUTPUT_CONTROL=m
693# CONFIG_FB is not set 942# CONFIG_FB is not set
@@ -697,10 +946,6 @@ CONFIG_VIDEO_OUTPUT_CONTROL=m
697# Display device support 946# Display device support
698# 947#
699# CONFIG_DISPLAY_SUPPORT is not set 948# CONFIG_DISPLAY_SUPPORT is not set
700
701#
702# Sound
703#
704# CONFIG_SOUND is not set 949# CONFIG_SOUND is not set
705CONFIG_HID_SUPPORT=y 950CONFIG_HID_SUPPORT=y
706CONFIG_HID=y 951CONFIG_HID=y
@@ -716,7 +961,7 @@ CONFIG_USB_HID=y
716# CONFIG_USB_HIDDEV is not set 961# CONFIG_USB_HIDDEV is not set
717CONFIG_USB_SUPPORT=y 962CONFIG_USB_SUPPORT=y
718CONFIG_USB_ARCH_HAS_HCD=y 963CONFIG_USB_ARCH_HAS_HCD=y
719# CONFIG_USB_ARCH_HAS_OHCI is not set 964CONFIG_USB_ARCH_HAS_OHCI=y
720CONFIG_USB_ARCH_HAS_EHCI=y 965CONFIG_USB_ARCH_HAS_EHCI=y
721CONFIG_USB=y 966CONFIG_USB=y
722# CONFIG_USB_DEBUG is not set 967# CONFIG_USB_DEBUG is not set
@@ -731,6 +976,7 @@ CONFIG_USB_DEVICE_CLASS=y
731# CONFIG_USB_OTG is not set 976# CONFIG_USB_OTG is not set
732# CONFIG_USB_OTG_WHITELIST is not set 977# CONFIG_USB_OTG_WHITELIST is not set
733# CONFIG_USB_OTG_BLACKLIST_HUB is not set 978# CONFIG_USB_OTG_BLACKLIST_HUB is not set
979CONFIG_USB_MON=y
734 980
735# 981#
736# USB Host Controller Drivers 982# USB Host Controller Drivers
@@ -743,6 +989,8 @@ CONFIG_USB_EHCI_FSL=y
743CONFIG_USB_EHCI_HCD_PPC_OF=y 989CONFIG_USB_EHCI_HCD_PPC_OF=y
744# CONFIG_USB_ISP116X_HCD is not set 990# CONFIG_USB_ISP116X_HCD is not set
745# CONFIG_USB_ISP1760_HCD is not set 991# CONFIG_USB_ISP1760_HCD is not set
992# CONFIG_USB_OHCI_HCD is not set
993# CONFIG_USB_UHCI_HCD is not set
746# CONFIG_USB_SL811_HCD is not set 994# CONFIG_USB_SL811_HCD is not set
747# CONFIG_USB_R8A66597_HCD is not set 995# CONFIG_USB_R8A66597_HCD is not set
748 996
@@ -768,7 +1016,6 @@ CONFIG_USB_EHCI_HCD_PPC_OF=y
768# 1016#
769# CONFIG_USB_MDC800 is not set 1017# CONFIG_USB_MDC800 is not set
770# CONFIG_USB_MICROTEK is not set 1018# CONFIG_USB_MICROTEK is not set
771CONFIG_USB_MON=y
772 1019
773# 1020#
774# USB port drivers 1021# USB port drivers
@@ -781,7 +1028,6 @@ CONFIG_USB_MON=y
781# CONFIG_USB_EMI62 is not set 1028# CONFIG_USB_EMI62 is not set
782# CONFIG_USB_EMI26 is not set 1029# CONFIG_USB_EMI26 is not set
783# CONFIG_USB_ADUTUX is not set 1030# CONFIG_USB_ADUTUX is not set
784# CONFIG_USB_AUERSWALD is not set
785# CONFIG_USB_RIO500 is not set 1031# CONFIG_USB_RIO500 is not set
786# CONFIG_USB_LEGOTOWER is not set 1032# CONFIG_USB_LEGOTOWER is not set
787# CONFIG_USB_LCD is not set 1033# CONFIG_USB_LCD is not set
@@ -803,6 +1049,7 @@ CONFIG_USB_MON=y
803# CONFIG_MEMSTICK is not set 1049# CONFIG_MEMSTICK is not set
804# CONFIG_NEW_LEDS is not set 1050# CONFIG_NEW_LEDS is not set
805# CONFIG_ACCESSIBILITY is not set 1051# CONFIG_ACCESSIBILITY is not set
1052# CONFIG_INFINIBAND is not set
806# CONFIG_EDAC is not set 1053# CONFIG_EDAC is not set
807# CONFIG_RTC_CLASS is not set 1054# CONFIG_RTC_CLASS is not set
808# CONFIG_DMADEVICES is not set 1055# CONFIG_DMADEVICES is not set
@@ -872,6 +1119,7 @@ CONFIG_TMPFS=y
872# CONFIG_CRAMFS is not set 1119# CONFIG_CRAMFS is not set
873# CONFIG_VXFS_FS is not set 1120# CONFIG_VXFS_FS is not set
874# CONFIG_MINIX_FS is not set 1121# CONFIG_MINIX_FS is not set
1122# CONFIG_OMFS_FS is not set
875# CONFIG_HPFS_FS is not set 1123# CONFIG_HPFS_FS is not set
876# CONFIG_QNX4FS_FS is not set 1124# CONFIG_QNX4FS_FS is not set
877# CONFIG_ROMFS_FS is not set 1125# CONFIG_ROMFS_FS is not set
@@ -882,14 +1130,13 @@ CONFIG_NFS_FS=y
882CONFIG_NFS_V3=y 1130CONFIG_NFS_V3=y
883# CONFIG_NFS_V3_ACL is not set 1131# CONFIG_NFS_V3_ACL is not set
884CONFIG_NFS_V4=y 1132CONFIG_NFS_V4=y
885# CONFIG_NFSD is not set
886CONFIG_ROOT_NFS=y 1133CONFIG_ROOT_NFS=y
1134# CONFIG_NFSD is not set
887CONFIG_LOCKD=y 1135CONFIG_LOCKD=y
888CONFIG_LOCKD_V4=y 1136CONFIG_LOCKD_V4=y
889CONFIG_NFS_COMMON=y 1137CONFIG_NFS_COMMON=y
890CONFIG_SUNRPC=y 1138CONFIG_SUNRPC=y
891CONFIG_SUNRPC_GSS=y 1139CONFIG_SUNRPC_GSS=y
892# CONFIG_SUNRPC_BIND34 is not set
893CONFIG_RPCSEC_GSS_KRB5=y 1140CONFIG_RPCSEC_GSS_KRB5=y
894# CONFIG_RPCSEC_GSS_SPKM3 is not set 1141# CONFIG_RPCSEC_GSS_SPKM3 is not set
895# CONFIG_SMB_FS is not set 1142# CONFIG_SMB_FS is not set
@@ -929,6 +1176,7 @@ CONFIG_BITREVERSE=y
929# CONFIG_GENERIC_FIND_FIRST_BIT is not set 1176# CONFIG_GENERIC_FIND_FIRST_BIT is not set
930# CONFIG_CRC_CCITT is not set 1177# CONFIG_CRC_CCITT is not set
931# CONFIG_CRC16 is not set 1178# CONFIG_CRC16 is not set
1179CONFIG_CRC_T10DIF=y
932# CONFIG_CRC_ITU_T is not set 1180# CONFIG_CRC_ITU_T is not set
933CONFIG_CRC32=y 1181CONFIG_CRC32=y
934# CONFIG_CRC7 is not set 1182# CONFIG_CRC7 is not set
@@ -952,8 +1200,18 @@ CONFIG_FRAME_WARN=1024
952# CONFIG_HEADERS_CHECK is not set 1200# CONFIG_HEADERS_CHECK is not set
953# CONFIG_DEBUG_KERNEL is not set 1201# CONFIG_DEBUG_KERNEL is not set
954# CONFIG_DEBUG_BUGVERBOSE is not set 1202# CONFIG_DEBUG_BUGVERBOSE is not set
1203# CONFIG_DEBUG_MEMORY_INIT is not set
1204# CONFIG_LATENCYTOP is not set
1205CONFIG_SYSCTL_SYSCALL_CHECK=y
1206CONFIG_HAVE_FTRACE=y
1207CONFIG_HAVE_DYNAMIC_FTRACE=y
1208# CONFIG_FTRACE is not set
1209# CONFIG_SCHED_TRACER is not set
1210# CONFIG_CONTEXT_SWITCH_TRACER is not set
955# CONFIG_SAMPLES is not set 1211# CONFIG_SAMPLES is not set
1212CONFIG_HAVE_ARCH_KGDB=y
956# CONFIG_IRQSTACKS is not set 1213# CONFIG_IRQSTACKS is not set
1214# CONFIG_BOOTX_TEXT is not set
957# CONFIG_PPC_EARLY_DEBUG is not set 1215# CONFIG_PPC_EARLY_DEBUG is not set
958 1216
959# 1217#
@@ -1011,6 +1269,10 @@ CONFIG_CRYPTO_PCBC=m
1011# CONFIG_CRYPTO_MD4 is not set 1269# CONFIG_CRYPTO_MD4 is not set
1012CONFIG_CRYPTO_MD5=y 1270CONFIG_CRYPTO_MD5=y
1013# CONFIG_CRYPTO_MICHAEL_MIC is not set 1271# CONFIG_CRYPTO_MICHAEL_MIC is not set
1272# CONFIG_CRYPTO_RMD128 is not set
1273# CONFIG_CRYPTO_RMD160 is not set
1274# CONFIG_CRYPTO_RMD256 is not set
1275# CONFIG_CRYPTO_RMD320 is not set
1014# CONFIG_CRYPTO_SHA1 is not set 1276# CONFIG_CRYPTO_SHA1 is not set
1015# CONFIG_CRYPTO_SHA256 is not set 1277# CONFIG_CRYPTO_SHA256 is not set
1016# CONFIG_CRYPTO_SHA512 is not set 1278# CONFIG_CRYPTO_SHA512 is not set
@@ -1042,5 +1304,7 @@ CONFIG_CRYPTO_DES=y
1042# CONFIG_CRYPTO_DEFLATE is not set 1304# CONFIG_CRYPTO_DEFLATE is not set
1043# CONFIG_CRYPTO_LZO is not set 1305# CONFIG_CRYPTO_LZO is not set
1044CONFIG_CRYPTO_HW=y 1306CONFIG_CRYPTO_HW=y
1307# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1308# CONFIG_CRYPTO_DEV_TALITOS is not set
1045# CONFIG_PPC_CLOCK is not set 1309# CONFIG_PPC_CLOCK is not set
1046# CONFIG_VIRTUALIZATION is not set 1310# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/configs/83xx/sbc834x_defconfig b/arch/powerpc/configs/83xx/sbc834x_defconfig
index 1752918be2c1..9245a67da200 100644
--- a/arch/powerpc/configs/83xx/sbc834x_defconfig
+++ b/arch/powerpc/configs/83xx/sbc834x_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc5 3# Linux kernel version: 2.6.27-rc4
4# Mon Jun 9 08:52:30 2008 4# Thu Aug 21 00:52:27 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -16,6 +16,7 @@ CONFIG_6xx=y
16# CONFIG_E200 is not set 16# CONFIG_E200 is not set
17CONFIG_PPC_FPU=y 17CONFIG_PPC_FPU=y
18# CONFIG_FSL_EMB_PERFMON is not set 18# CONFIG_FSL_EMB_PERFMON is not set
19# CONFIG_ALTIVEC is not set
19CONFIG_PPC_STD_MMU=y 20CONFIG_PPC_STD_MMU=y
20CONFIG_PPC_STD_MMU_32=y 21CONFIG_PPC_STD_MMU_32=y
21# CONFIG_PPC_MM_SLICES is not set 22# CONFIG_PPC_MM_SLICES is not set
@@ -32,6 +33,7 @@ CONFIG_GENERIC_HARDIRQS=y
32# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set 33# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
33CONFIG_IRQ_PER_CPU=y 34CONFIG_IRQ_PER_CPU=y
34CONFIG_STACKTRACE_SUPPORT=y 35CONFIG_STACKTRACE_SUPPORT=y
36CONFIG_HAVE_LATENCYTOP_SUPPORT=y
35CONFIG_LOCKDEP_SUPPORT=y 37CONFIG_LOCKDEP_SUPPORT=y
36CONFIG_RWSEM_XCHGADD_ALGORITHM=y 38CONFIG_RWSEM_XCHGADD_ALGORITHM=y
37CONFIG_ARCH_HAS_ILOG2_U32=y 39CONFIG_ARCH_HAS_ILOG2_U32=y
@@ -51,6 +53,9 @@ CONFIG_PPC_UDBG_16550=y
51CONFIG_AUDIT_ARCH=y 53CONFIG_AUDIT_ARCH=y
52CONFIG_GENERIC_BUG=y 54CONFIG_GENERIC_BUG=y
53CONFIG_DEFAULT_UIMAGE=y 55CONFIG_DEFAULT_UIMAGE=y
56CONFIG_HIBERNATE_32=y
57CONFIG_ARCH_HIBERNATION_POSSIBLE=y
58CONFIG_ARCH_SUSPEND_POSSIBLE=y
54# CONFIG_PPC_DCR_NATIVE is not set 59# CONFIG_PPC_DCR_NATIVE is not set
55# CONFIG_PPC_DCR_MMIO is not set 60# CONFIG_PPC_DCR_MMIO is not set
56CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 61CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
@@ -88,12 +93,12 @@ CONFIG_INITRAMFS_SOURCE=""
88CONFIG_SYSCTL=y 93CONFIG_SYSCTL=y
89CONFIG_EMBEDDED=y 94CONFIG_EMBEDDED=y
90CONFIG_SYSCTL_SYSCALL=y 95CONFIG_SYSCTL_SYSCALL=y
91CONFIG_SYSCTL_SYSCALL_CHECK=y
92# CONFIG_KALLSYMS is not set 96# CONFIG_KALLSYMS is not set
93CONFIG_HOTPLUG=y 97CONFIG_HOTPLUG=y
94CONFIG_PRINTK=y 98CONFIG_PRINTK=y
95CONFIG_BUG=y 99CONFIG_BUG=y
96CONFIG_ELF_CORE=y 100CONFIG_ELF_CORE=y
101CONFIG_PCSPKR_PLATFORM=y
97CONFIG_COMPAT_BRK=y 102CONFIG_COMPAT_BRK=y
98CONFIG_BASE_FULL=y 103CONFIG_BASE_FULL=y
99CONFIG_FUTEX=y 104CONFIG_FUTEX=y
@@ -110,10 +115,16 @@ CONFIG_SLAB=y
110# CONFIG_PROFILING is not set 115# CONFIG_PROFILING is not set
111# CONFIG_MARKERS is not set 116# CONFIG_MARKERS is not set
112CONFIG_HAVE_OPROFILE=y 117CONFIG_HAVE_OPROFILE=y
118CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
119CONFIG_HAVE_IOREMAP_PROT=y
113CONFIG_HAVE_KPROBES=y 120CONFIG_HAVE_KPROBES=y
114CONFIG_HAVE_KRETPROBES=y 121CONFIG_HAVE_KRETPROBES=y
122CONFIG_HAVE_ARCH_TRACEHOOK=y
115# CONFIG_HAVE_DMA_ATTRS is not set 123# CONFIG_HAVE_DMA_ATTRS is not set
124# CONFIG_USE_GENERIC_SMP_HELPERS is not set
125# CONFIG_HAVE_CLK is not set
116CONFIG_PROC_PAGE_MONITOR=y 126CONFIG_PROC_PAGE_MONITOR=y
127# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
117CONFIG_SLABINFO=y 128CONFIG_SLABINFO=y
118CONFIG_RT_MUTEXES=y 129CONFIG_RT_MUTEXES=y
119# CONFIG_TINY_SHMEM is not set 130# CONFIG_TINY_SHMEM is not set
@@ -124,12 +135,13 @@ CONFIG_MODULE_UNLOAD=y
124# CONFIG_MODULE_FORCE_UNLOAD is not set 135# CONFIG_MODULE_FORCE_UNLOAD is not set
125# CONFIG_MODVERSIONS is not set 136# CONFIG_MODVERSIONS is not set
126# CONFIG_MODULE_SRCVERSION_ALL is not set 137# CONFIG_MODULE_SRCVERSION_ALL is not set
127# CONFIG_KMOD is not set 138CONFIG_KMOD=y
128CONFIG_BLOCK=y 139CONFIG_BLOCK=y
129# CONFIG_LBD is not set 140# CONFIG_LBD is not set
130# CONFIG_BLK_DEV_IO_TRACE is not set 141# CONFIG_BLK_DEV_IO_TRACE is not set
131# CONFIG_LSF is not set 142# CONFIG_LSF is not set
132# CONFIG_BLK_DEV_BSG is not set 143# CONFIG_BLK_DEV_BSG is not set
144# CONFIG_BLK_DEV_INTEGRITY is not set
133 145
134# 146#
135# IO Schedulers 147# IO Schedulers
@@ -148,37 +160,49 @@ CONFIG_CLASSIC_RCU=y
148# 160#
149# Platform support 161# Platform support
150# 162#
151# CONFIG_PPC_MULTIPLATFORM is not set 163CONFIG_PPC_MULTIPLATFORM=y
152# CONFIG_PPC_82xx is not set 164CONFIG_CLASSIC32=y
153CONFIG_PPC_83xx=y 165CONFIG_PPC_CHRP=y
154# CONFIG_PPC_86xx is not set 166# CONFIG_MPC5121_ADS is not set
155# CONFIG_PPC_MPC512x is not set 167# CONFIG_MPC5121_GENERIC is not set
156# CONFIG_PPC_MPC5121 is not set 168# CONFIG_PPC_MPC52xx is not set
169CONFIG_PPC_PMAC=y
157# CONFIG_PPC_CELL is not set 170# CONFIG_PPC_CELL is not set
158# CONFIG_PPC_CELL_NATIVE is not set 171# CONFIG_PPC_CELL_NATIVE is not set
172# CONFIG_PPC_82xx is not set
159# CONFIG_PQ2ADS is not set 173# CONFIG_PQ2ADS is not set
160CONFIG_MPC83xx=y 174CONFIG_PPC_83xx=y
161# CONFIG_MPC831x_RDB is not set 175# CONFIG_MPC831x_RDB is not set
162# CONFIG_MPC832x_MDS is not set 176# CONFIG_MPC832x_MDS is not set
163# CONFIG_MPC832x_RDB is not set 177# CONFIG_MPC832x_RDB is not set
164# CONFIG_MPC834x_MDS is not set 178# CONFIG_MPC834x_MDS is not set
165# CONFIG_MPC834x_ITX is not set 179# CONFIG_MPC834x_ITX is not set
166# CONFIG_MPC836x_MDS is not set 180# CONFIG_MPC836x_MDS is not set
181# CONFIG_MPC836x_RDK is not set
167# CONFIG_MPC837x_MDS is not set 182# CONFIG_MPC837x_MDS is not set
168# CONFIG_MPC837x_RDB is not set 183# CONFIG_MPC837x_RDB is not set
169CONFIG_SBC834x=y 184CONFIG_SBC834x=y
185# CONFIG_ASP834x is not set
170CONFIG_PPC_MPC834x=y 186CONFIG_PPC_MPC834x=y
187# CONFIG_PPC_86xx is not set
188# CONFIG_EMBEDDED6xx is not set
189CONFIG_PPC_NATIVE=y
190# CONFIG_UDBG_RTAS_CONSOLE is not set
171CONFIG_IPIC=y 191CONFIG_IPIC=y
172# CONFIG_MPIC is not set 192CONFIG_MPIC=y
173# CONFIG_MPIC_WEIRD is not set 193# CONFIG_MPIC_WEIRD is not set
174# CONFIG_PPC_I8259 is not set 194CONFIG_PPC_I8259=y
175# CONFIG_PPC_RTAS is not set 195CONFIG_PPC_RTAS=y
196# CONFIG_RTAS_ERROR_LOGGING is not set
197CONFIG_RTAS_PROC=y
176# CONFIG_MMIO_NVRAM is not set 198# CONFIG_MMIO_NVRAM is not set
177# CONFIG_PPC_MPC106 is not set 199CONFIG_PPC_MPC106=y
178# CONFIG_PPC_970_NAP is not set 200# CONFIG_PPC_970_NAP is not set
179# CONFIG_PPC_INDIRECT_IO is not set 201# CONFIG_PPC_INDIRECT_IO is not set
180# CONFIG_GENERIC_IOMAP is not set 202# CONFIG_GENERIC_IOMAP is not set
181# CONFIG_CPU_FREQ is not set 203# CONFIG_CPU_FREQ is not set
204# CONFIG_PPC601_SYNC_FIX is not set
205# CONFIG_TAU is not set
182# CONFIG_FSL_ULI1575 is not set 206# CONFIG_FSL_ULI1575 is not set
183 207
184# 208#
@@ -204,6 +228,7 @@ CONFIG_BINFMT_ELF=y
204CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y 228CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
205CONFIG_ARCH_HAS_WALK_MEMORY=y 229CONFIG_ARCH_HAS_WALK_MEMORY=y
206CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y 230CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
231# CONFIG_KEXEC is not set
207CONFIG_ARCH_FLATMEM_ENABLE=y 232CONFIG_ARCH_FLATMEM_ENABLE=y
208CONFIG_ARCH_POPULATES_NODE_MAP=y 233CONFIG_ARCH_POPULATES_NODE_MAP=y
209CONFIG_SELECT_MEMORY_MODEL=y 234CONFIG_SELECT_MEMORY_MODEL=y
@@ -216,6 +241,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
216# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set 241# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
217CONFIG_PAGEFLAGS_EXTENDED=y 242CONFIG_PAGEFLAGS_EXTENDED=y
218CONFIG_SPLIT_PTLOCK_CPUS=4 243CONFIG_SPLIT_PTLOCK_CPUS=4
244CONFIG_MIGRATION=y
219# CONFIG_RESOURCES_64BIT is not set 245# CONFIG_RESOURCES_64BIT is not set
220CONFIG_ZONE_DMA_FLAG=1 246CONFIG_ZONE_DMA_FLAG=1
221CONFIG_BOUNCE=y 247CONFIG_BOUNCE=y
@@ -223,6 +249,7 @@ CONFIG_VIRT_TO_BUS=y
223CONFIG_FORCE_MAX_ZONEORDER=11 249CONFIG_FORCE_MAX_ZONEORDER=11
224CONFIG_PROC_DEVICETREE=y 250CONFIG_PROC_DEVICETREE=y
225# CONFIG_CMDLINE_BOOL is not set 251# CONFIG_CMDLINE_BOOL is not set
252CONFIG_EXTRA_TARGETS=""
226# CONFIG_PM is not set 253# CONFIG_PM is not set
227CONFIG_SECCOMP=y 254CONFIG_SECCOMP=y
228CONFIG_ISA_DMA_API=y 255CONFIG_ISA_DMA_API=y
@@ -230,15 +257,22 @@ CONFIG_ISA_DMA_API=y
230# 257#
231# Bus options 258# Bus options
232# 259#
260# CONFIG_ISA is not set
233CONFIG_ZONE_DMA=y 261CONFIG_ZONE_DMA=y
234CONFIG_GENERIC_ISA_DMA=y 262CONFIG_GENERIC_ISA_DMA=y
235CONFIG_PPC_INDIRECT_PCI=y 263CONFIG_PPC_INDIRECT_PCI=y
236CONFIG_FSL_SOC=y 264CONFIG_FSL_SOC=y
237# CONFIG_PCI is not set 265CONFIG_FSL_PCI=y
238# CONFIG_PCI_DOMAINS is not set 266CONFIG_PPC_PCI_CHOICE=y
239# CONFIG_PCI_SYSCALL is not set 267CONFIG_PCI=y
240# CONFIG_ARCH_SUPPORTS_MSI is not set 268CONFIG_PCI_DOMAINS=y
269CONFIG_PCI_SYSCALL=y
270# CONFIG_PCIEPORTBUS is not set
271CONFIG_ARCH_SUPPORTS_MSI=y
272# CONFIG_PCI_MSI is not set
273CONFIG_PCI_LEGACY=y
241# CONFIG_PCCARD is not set 274# CONFIG_PCCARD is not set
275# CONFIG_HOTPLUG_PCI is not set
242# CONFIG_HAS_RAPIDIO is not set 276# CONFIG_HAS_RAPIDIO is not set
243 277
244# 278#
@@ -254,10 +288,6 @@ CONFIG_PAGE_OFFSET=0xc0000000
254CONFIG_KERNEL_START=0xc0000000 288CONFIG_KERNEL_START=0xc0000000
255CONFIG_PHYSICAL_START=0x00000000 289CONFIG_PHYSICAL_START=0x00000000
256CONFIG_TASK_SIZE=0xc0000000 290CONFIG_TASK_SIZE=0xc0000000
257
258#
259# Networking
260#
261CONFIG_NET=y 291CONFIG_NET=y
262 292
263# 293#
@@ -358,19 +388,30 @@ CONFIG_OF_I2C=y
358# CONFIG_PARPORT is not set 388# CONFIG_PARPORT is not set
359CONFIG_BLK_DEV=y 389CONFIG_BLK_DEV=y
360# CONFIG_BLK_DEV_FD is not set 390# CONFIG_BLK_DEV_FD is not set
391# CONFIG_MAC_FLOPPY is not set
392# CONFIG_BLK_CPQ_DA is not set
393# CONFIG_BLK_CPQ_CISS_DA is not set
394# CONFIG_BLK_DEV_DAC960 is not set
395# CONFIG_BLK_DEV_UMEM is not set
361# CONFIG_BLK_DEV_COW_COMMON is not set 396# CONFIG_BLK_DEV_COW_COMMON is not set
362CONFIG_BLK_DEV_LOOP=y 397CONFIG_BLK_DEV_LOOP=y
363# CONFIG_BLK_DEV_CRYPTOLOOP is not set 398# CONFIG_BLK_DEV_CRYPTOLOOP is not set
364# CONFIG_BLK_DEV_NBD is not set 399# CONFIG_BLK_DEV_NBD is not set
400# CONFIG_BLK_DEV_SX8 is not set
365CONFIG_BLK_DEV_RAM=y 401CONFIG_BLK_DEV_RAM=y
366CONFIG_BLK_DEV_RAM_COUNT=16 402CONFIG_BLK_DEV_RAM_COUNT=16
367CONFIG_BLK_DEV_RAM_SIZE=32768 403CONFIG_BLK_DEV_RAM_SIZE=32768
368# CONFIG_BLK_DEV_XIP is not set 404# CONFIG_BLK_DEV_XIP is not set
369# CONFIG_CDROM_PKTCDVD is not set 405# CONFIG_CDROM_PKTCDVD is not set
370# CONFIG_ATA_OVER_ETH is not set 406# CONFIG_ATA_OVER_ETH is not set
407# CONFIG_BLK_DEV_HD is not set
371CONFIG_MISC_DEVICES=y 408CONFIG_MISC_DEVICES=y
409# CONFIG_PHANTOM is not set
372# CONFIG_EEPROM_93CX6 is not set 410# CONFIG_EEPROM_93CX6 is not set
411# CONFIG_SGI_IOC4 is not set
412# CONFIG_TIFM_CORE is not set
373# CONFIG_ENCLOSURE_SERVICES is not set 413# CONFIG_ENCLOSURE_SERVICES is not set
414# CONFIG_HP_ILO is not set
374CONFIG_HAVE_IDE=y 415CONFIG_HAVE_IDE=y
375# CONFIG_IDE is not set 416# CONFIG_IDE is not set
376 417
@@ -383,15 +424,27 @@ CONFIG_HAVE_IDE=y
383# CONFIG_SCSI_NETLINK is not set 424# CONFIG_SCSI_NETLINK is not set
384# CONFIG_ATA is not set 425# CONFIG_ATA is not set
385# CONFIG_MD is not set 426# CONFIG_MD is not set
427# CONFIG_FUSION is not set
428
429#
430# IEEE 1394 (FireWire) support
431#
432
433#
434# Enable only one of the two stacks, unless you know what you are doing
435#
436# CONFIG_FIREWIRE is not set
437# CONFIG_IEEE1394 is not set
438# CONFIG_I2O is not set
386# CONFIG_MACINTOSH_DRIVERS is not set 439# CONFIG_MACINTOSH_DRIVERS is not set
387CONFIG_NETDEVICES=y 440CONFIG_NETDEVICES=y
388# CONFIG_NETDEVICES_MULTIQUEUE is not set
389# CONFIG_DUMMY is not set 441# CONFIG_DUMMY is not set
390# CONFIG_BONDING is not set 442# CONFIG_BONDING is not set
391# CONFIG_MACVLAN is not set 443# CONFIG_MACVLAN is not set
392# CONFIG_EQUALIZER is not set 444# CONFIG_EQUALIZER is not set
393# CONFIG_TUN is not set 445# CONFIG_TUN is not set
394# CONFIG_VETH is not set 446# CONFIG_VETH is not set
447# CONFIG_ARCNET is not set
395CONFIG_PHYLIB=y 448CONFIG_PHYLIB=y
396 449
397# 450#
@@ -411,16 +464,44 @@ CONFIG_BROADCOM_PHY=y
411# CONFIG_MDIO_BITBANG is not set 464# CONFIG_MDIO_BITBANG is not set
412CONFIG_NET_ETHERNET=y 465CONFIG_NET_ETHERNET=y
413CONFIG_MII=y 466CONFIG_MII=y
467# CONFIG_MACE is not set
468# CONFIG_BMAC is not set
469# CONFIG_HAPPYMEAL is not set
470# CONFIG_SUNGEM is not set
471# CONFIG_CASSINI is not set
472# CONFIG_NET_VENDOR_3COM is not set
473# CONFIG_NET_TULIP is not set
474# CONFIG_HP100 is not set
414# CONFIG_IBM_NEW_EMAC_ZMII is not set 475# CONFIG_IBM_NEW_EMAC_ZMII is not set
415# CONFIG_IBM_NEW_EMAC_RGMII is not set 476# CONFIG_IBM_NEW_EMAC_RGMII is not set
416# CONFIG_IBM_NEW_EMAC_TAH is not set 477# CONFIG_IBM_NEW_EMAC_TAH is not set
417# CONFIG_IBM_NEW_EMAC_EMAC4 is not set 478# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
479# CONFIG_NET_PCI is not set
418# CONFIG_B44 is not set 480# CONFIG_B44 is not set
419CONFIG_NETDEV_1000=y 481CONFIG_NETDEV_1000=y
420# CONFIG_E1000E_ENABLED is not set 482# CONFIG_ACENIC is not set
483# CONFIG_DL2K is not set
484# CONFIG_E1000 is not set
485# CONFIG_E1000E is not set
486# CONFIG_IP1000 is not set
487# CONFIG_IGB is not set
488# CONFIG_NS83820 is not set
489# CONFIG_HAMACHI is not set
490# CONFIG_YELLOWFIN is not set
491# CONFIG_R8169 is not set
492# CONFIG_SIS190 is not set
493# CONFIG_SKGE is not set
494# CONFIG_SKY2 is not set
495# CONFIG_VIA_VELOCITY is not set
496# CONFIG_TIGON3 is not set
497# CONFIG_BNX2 is not set
421CONFIG_GIANFAR=y 498CONFIG_GIANFAR=y
422# CONFIG_GFAR_NAPI is not set 499# CONFIG_MV643XX_ETH is not set
500# CONFIG_QLA3XXX is not set
501# CONFIG_ATL1 is not set
502# CONFIG_ATL1E is not set
423# CONFIG_NETDEV_10000 is not set 503# CONFIG_NETDEV_10000 is not set
504# CONFIG_TR is not set
424 505
425# 506#
426# Wireless LAN 507# Wireless LAN
@@ -429,6 +510,8 @@ CONFIG_GIANFAR=y
429# CONFIG_WLAN_80211 is not set 510# CONFIG_WLAN_80211 is not set
430# CONFIG_IWLWIFI_LEDS is not set 511# CONFIG_IWLWIFI_LEDS is not set
431# CONFIG_WAN is not set 512# CONFIG_WAN is not set
513# CONFIG_FDDI is not set
514# CONFIG_HIPPI is not set
432# CONFIG_PPP is not set 515# CONFIG_PPP is not set
433# CONFIG_SLIP is not set 516# CONFIG_SLIP is not set
434# CONFIG_NETCONSOLE is not set 517# CONFIG_NETCONSOLE is not set
@@ -474,12 +557,14 @@ CONFIG_INPUT=y
474# CONFIG_VT is not set 557# CONFIG_VT is not set
475CONFIG_DEVKMEM=y 558CONFIG_DEVKMEM=y
476# CONFIG_SERIAL_NONSTANDARD is not set 559# CONFIG_SERIAL_NONSTANDARD is not set
560# CONFIG_NOZOMI is not set
477 561
478# 562#
479# Serial drivers 563# Serial drivers
480# 564#
481CONFIG_SERIAL_8250=y 565CONFIG_SERIAL_8250=y
482CONFIG_SERIAL_8250_CONSOLE=y 566CONFIG_SERIAL_8250_CONSOLE=y
567CONFIG_SERIAL_8250_PCI=y
483CONFIG_SERIAL_8250_NR_UARTS=4 568CONFIG_SERIAL_8250_NR_UARTS=4
484CONFIG_SERIAL_8250_RUNTIME_UARTS=4 569CONFIG_SERIAL_8250_RUNTIME_UARTS=4
485# CONFIG_SERIAL_8250_EXTENDED is not set 570# CONFIG_SERIAL_8250_EXTENDED is not set
@@ -490,40 +575,90 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=4
490# CONFIG_SERIAL_UARTLITE is not set 575# CONFIG_SERIAL_UARTLITE is not set
491CONFIG_SERIAL_CORE=y 576CONFIG_SERIAL_CORE=y
492CONFIG_SERIAL_CORE_CONSOLE=y 577CONFIG_SERIAL_CORE_CONSOLE=y
578# CONFIG_SERIAL_PMACZILOG is not set
579# CONFIG_SERIAL_JSM is not set
493# CONFIG_SERIAL_OF_PLATFORM is not set 580# CONFIG_SERIAL_OF_PLATFORM is not set
494CONFIG_UNIX98_PTYS=y 581CONFIG_UNIX98_PTYS=y
495CONFIG_LEGACY_PTYS=y 582CONFIG_LEGACY_PTYS=y
496CONFIG_LEGACY_PTY_COUNT=256 583CONFIG_LEGACY_PTY_COUNT=256
584# CONFIG_BRIQ_PANEL is not set
585# CONFIG_HVC_RTAS is not set
497# CONFIG_IPMI_HANDLER is not set 586# CONFIG_IPMI_HANDLER is not set
498# CONFIG_HW_RANDOM is not set 587# CONFIG_HW_RANDOM is not set
499# CONFIG_NVRAM is not set 588# CONFIG_NVRAM is not set
500CONFIG_GEN_RTC=y 589CONFIG_GEN_RTC=y
501# CONFIG_GEN_RTC_X is not set 590# CONFIG_GEN_RTC_X is not set
502# CONFIG_R3964 is not set 591# CONFIG_R3964 is not set
592# CONFIG_APPLICOM is not set
503# CONFIG_RAW_DRIVER is not set 593# CONFIG_RAW_DRIVER is not set
504# CONFIG_TCG_TPM is not set 594# CONFIG_TCG_TPM is not set
595CONFIG_DEVPORT=y
505CONFIG_I2C=y 596CONFIG_I2C=y
506CONFIG_I2C_BOARDINFO=y 597CONFIG_I2C_BOARDINFO=y
507CONFIG_I2C_CHARDEV=y 598CONFIG_I2C_CHARDEV=y
599CONFIG_I2C_HELPER_AUTO=y
508 600
509# 601#
510# I2C Hardware Bus support 602# I2C Hardware Bus support
511# 603#
604
605#
606# PC SMBus host controller drivers
607#
608# CONFIG_I2C_ALI1535 is not set
609# CONFIG_I2C_ALI1563 is not set
610# CONFIG_I2C_ALI15X3 is not set
611# CONFIG_I2C_AMD756 is not set
612# CONFIG_I2C_AMD8111 is not set
613# CONFIG_I2C_I801 is not set
614# CONFIG_I2C_ISCH is not set
615# CONFIG_I2C_PIIX4 is not set
616# CONFIG_I2C_NFORCE2 is not set
617# CONFIG_I2C_SIS5595 is not set
618# CONFIG_I2C_SIS630 is not set
619# CONFIG_I2C_SIS96X is not set
620# CONFIG_I2C_VIA is not set
621# CONFIG_I2C_VIAPRO is not set
622
623#
624# Mac SMBus host controller drivers
625#
626# CONFIG_I2C_HYDRA is not set
627CONFIG_I2C_POWERMAC=y
628
629#
630# I2C system bus drivers (mostly embedded / system-on-chip)
631#
512CONFIG_I2C_MPC=y 632CONFIG_I2C_MPC=y
513# CONFIG_I2C_OCORES is not set 633# CONFIG_I2C_OCORES is not set
514# CONFIG_I2C_PARPORT_LIGHT is not set
515# CONFIG_I2C_SIMTEC is not set 634# CONFIG_I2C_SIMTEC is not set
635
636#
637# External I2C/SMBus adapter drivers
638#
639# CONFIG_I2C_PARPORT_LIGHT is not set
516# CONFIG_I2C_TAOS_EVM is not set 640# CONFIG_I2C_TAOS_EVM is not set
517# CONFIG_I2C_STUB is not set 641
642#
643# Graphics adapter I2C/DDC channel drivers
644#
645# CONFIG_I2C_VOODOO3 is not set
646
647#
648# Other I2C/SMBus bus drivers
649#
518# CONFIG_I2C_PCA_PLATFORM is not set 650# CONFIG_I2C_PCA_PLATFORM is not set
651# CONFIG_I2C_STUB is not set
519 652
520# 653#
521# Miscellaneous I2C Chip support 654# Miscellaneous I2C Chip support
522# 655#
523# CONFIG_DS1682 is not set 656# CONFIG_DS1682 is not set
657# CONFIG_AT24 is not set
524# CONFIG_SENSORS_EEPROM is not set 658# CONFIG_SENSORS_EEPROM is not set
525# CONFIG_SENSORS_PCF8574 is not set 659# CONFIG_SENSORS_PCF8574 is not set
526# CONFIG_PCF8575 is not set 660# CONFIG_PCF8575 is not set
661# CONFIG_SENSORS_PCA9539 is not set
527# CONFIG_SENSORS_PCF8591 is not set 662# CONFIG_SENSORS_PCF8591 is not set
528# CONFIG_SENSORS_MAX6875 is not set 663# CONFIG_SENSORS_MAX6875 is not set
529# CONFIG_SENSORS_TSL2550 is not set 664# CONFIG_SENSORS_TSL2550 is not set
@@ -532,10 +667,13 @@ CONFIG_I2C_MPC=y
532# CONFIG_I2C_DEBUG_BUS is not set 667# CONFIG_I2C_DEBUG_BUS is not set
533# CONFIG_I2C_DEBUG_CHIP is not set 668# CONFIG_I2C_DEBUG_CHIP is not set
534# CONFIG_SPI is not set 669# CONFIG_SPI is not set
670CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
671# CONFIG_GPIOLIB is not set
535# CONFIG_W1 is not set 672# CONFIG_W1 is not set
536# CONFIG_POWER_SUPPLY is not set 673# CONFIG_POWER_SUPPLY is not set
537CONFIG_HWMON=y 674CONFIG_HWMON=y
538# CONFIG_HWMON_VID is not set 675# CONFIG_HWMON_VID is not set
676# CONFIG_SENSORS_AD7414 is not set
539# CONFIG_SENSORS_AD7418 is not set 677# CONFIG_SENSORS_AD7418 is not set
540# CONFIG_SENSORS_ADM1021 is not set 678# CONFIG_SENSORS_ADM1021 is not set
541# CONFIG_SENSORS_ADM1025 is not set 679# CONFIG_SENSORS_ADM1025 is not set
@@ -545,8 +683,10 @@ CONFIG_HWMON=y
545# CONFIG_SENSORS_ADM9240 is not set 683# CONFIG_SENSORS_ADM9240 is not set
546# CONFIG_SENSORS_ADT7470 is not set 684# CONFIG_SENSORS_ADT7470 is not set
547# CONFIG_SENSORS_ADT7473 is not set 685# CONFIG_SENSORS_ADT7473 is not set
686# CONFIG_SENSORS_AMS is not set
548# CONFIG_SENSORS_ATXP1 is not set 687# CONFIG_SENSORS_ATXP1 is not set
549# CONFIG_SENSORS_DS1621 is not set 688# CONFIG_SENSORS_DS1621 is not set
689# CONFIG_SENSORS_I5K_AMB is not set
550# CONFIG_SENSORS_F71805F is not set 690# CONFIG_SENSORS_F71805F is not set
551# CONFIG_SENSORS_F71882FG is not set 691# CONFIG_SENSORS_F71882FG is not set
552# CONFIG_SENSORS_F75375S is not set 692# CONFIG_SENSORS_F75375S is not set
@@ -568,13 +708,16 @@ CONFIG_HWMON=y
568# CONFIG_SENSORS_MAX6650 is not set 708# CONFIG_SENSORS_MAX6650 is not set
569# CONFIG_SENSORS_PC87360 is not set 709# CONFIG_SENSORS_PC87360 is not set
570# CONFIG_SENSORS_PC87427 is not set 710# CONFIG_SENSORS_PC87427 is not set
711# CONFIG_SENSORS_SIS5595 is not set
571# CONFIG_SENSORS_DME1737 is not set 712# CONFIG_SENSORS_DME1737 is not set
572# CONFIG_SENSORS_SMSC47M1 is not set 713# CONFIG_SENSORS_SMSC47M1 is not set
573# CONFIG_SENSORS_SMSC47M192 is not set 714# CONFIG_SENSORS_SMSC47M192 is not set
574# CONFIG_SENSORS_SMSC47B397 is not set 715# CONFIG_SENSORS_SMSC47B397 is not set
575# CONFIG_SENSORS_ADS7828 is not set 716# CONFIG_SENSORS_ADS7828 is not set
576# CONFIG_SENSORS_THMC50 is not set 717# CONFIG_SENSORS_THMC50 is not set
718# CONFIG_SENSORS_VIA686A is not set
577# CONFIG_SENSORS_VT1211 is not set 719# CONFIG_SENSORS_VT1211 is not set
720# CONFIG_SENSORS_VT8231 is not set
578# CONFIG_SENSORS_W83781D is not set 721# CONFIG_SENSORS_W83781D is not set
579# CONFIG_SENSORS_W83791D is not set 722# CONFIG_SENSORS_W83791D is not set
580# CONFIG_SENSORS_W83792D is not set 723# CONFIG_SENSORS_W83792D is not set
@@ -585,6 +728,7 @@ CONFIG_HWMON=y
585# CONFIG_SENSORS_W83627EHF is not set 728# CONFIG_SENSORS_W83627EHF is not set
586# CONFIG_HWMON_DEBUG_CHIP is not set 729# CONFIG_HWMON_DEBUG_CHIP is not set
587# CONFIG_THERMAL is not set 730# CONFIG_THERMAL is not set
731# CONFIG_THERMAL_HWMON is not set
588CONFIG_WATCHDOG=y 732CONFIG_WATCHDOG=y
589# CONFIG_WATCHDOG_NOWAYOUT is not set 733# CONFIG_WATCHDOG_NOWAYOUT is not set
590 734
@@ -592,7 +736,15 @@ CONFIG_WATCHDOG=y
592# Watchdog Device Drivers 736# Watchdog Device Drivers
593# 737#
594# CONFIG_SOFT_WATCHDOG is not set 738# CONFIG_SOFT_WATCHDOG is not set
595CONFIG_83xx_WDT=y 739# CONFIG_ALIM7101_WDT is not set
740# CONFIG_8xxx_WDT is not set
741# CONFIG_WATCHDOG_RTAS is not set
742
743#
744# PCI-based Watchdog Cards
745#
746# CONFIG_PCIPCWATCHDOG is not set
747# CONFIG_WDTPCI is not set
596 748
597# 749#
598# Sonics Silicon Backplane 750# Sonics Silicon Backplane
@@ -603,8 +755,10 @@ CONFIG_SSB_POSSIBLE=y
603# 755#
604# Multifunction device drivers 756# Multifunction device drivers
605# 757#
758# CONFIG_MFD_CORE is not set
606# CONFIG_MFD_SM501 is not set 759# CONFIG_MFD_SM501 is not set
607# CONFIG_HTC_PASIC3 is not set 760# CONFIG_HTC_PASIC3 is not set
761# CONFIG_MFD_TMIO is not set
608 762
609# 763#
610# Multimedia devices 764# Multimedia devices
@@ -625,6 +779,8 @@ CONFIG_SSB_POSSIBLE=y
625# 779#
626# Graphics support 780# Graphics support
627# 781#
782# CONFIG_AGP is not set
783# CONFIG_DRM is not set
628# CONFIG_VGASTATE is not set 784# CONFIG_VGASTATE is not set
629# CONFIG_VIDEO_OUTPUT_CONTROL is not set 785# CONFIG_VIDEO_OUTPUT_CONTROL is not set
630# CONFIG_FB is not set 786# CONFIG_FB is not set
@@ -634,10 +790,6 @@ CONFIG_SSB_POSSIBLE=y
634# Display device support 790# Display device support
635# 791#
636# CONFIG_DISPLAY_SUPPORT is not set 792# CONFIG_DISPLAY_SUPPORT is not set
637
638#
639# Sound
640#
641# CONFIG_SOUND is not set 793# CONFIG_SOUND is not set
642CONFIG_HID_SUPPORT=y 794CONFIG_HID_SUPPORT=y
643CONFIG_HID=y 795CONFIG_HID=y
@@ -648,6 +800,7 @@ CONFIG_HID=y
648# CONFIG_MEMSTICK is not set 800# CONFIG_MEMSTICK is not set
649# CONFIG_NEW_LEDS is not set 801# CONFIG_NEW_LEDS is not set
650# CONFIG_ACCESSIBILITY is not set 802# CONFIG_ACCESSIBILITY is not set
803# CONFIG_INFINIBAND is not set
651# CONFIG_EDAC is not set 804# CONFIG_EDAC is not set
652# CONFIG_RTC_CLASS is not set 805# CONFIG_RTC_CLASS is not set
653# CONFIG_DMADEVICES is not set 806# CONFIG_DMADEVICES is not set
@@ -710,6 +863,7 @@ CONFIG_TMPFS=y
710# CONFIG_CRAMFS is not set 863# CONFIG_CRAMFS is not set
711# CONFIG_VXFS_FS is not set 864# CONFIG_VXFS_FS is not set
712# CONFIG_MINIX_FS is not set 865# CONFIG_MINIX_FS is not set
866# CONFIG_OMFS_FS is not set
713# CONFIG_HPFS_FS is not set 867# CONFIG_HPFS_FS is not set
714# CONFIG_QNX4FS_FS is not set 868# CONFIG_QNX4FS_FS is not set
715# CONFIG_ROMFS_FS is not set 869# CONFIG_ROMFS_FS is not set
@@ -720,14 +874,13 @@ CONFIG_NFS_FS=y
720CONFIG_NFS_V3=y 874CONFIG_NFS_V3=y
721# CONFIG_NFS_V3_ACL is not set 875# CONFIG_NFS_V3_ACL is not set
722CONFIG_NFS_V4=y 876CONFIG_NFS_V4=y
723# CONFIG_NFSD is not set
724CONFIG_ROOT_NFS=y 877CONFIG_ROOT_NFS=y
878# CONFIG_NFSD is not set
725CONFIG_LOCKD=y 879CONFIG_LOCKD=y
726CONFIG_LOCKD_V4=y 880CONFIG_LOCKD_V4=y
727CONFIG_NFS_COMMON=y 881CONFIG_NFS_COMMON=y
728CONFIG_SUNRPC=y 882CONFIG_SUNRPC=y
729CONFIG_SUNRPC_GSS=y 883CONFIG_SUNRPC_GSS=y
730# CONFIG_SUNRPC_BIND34 is not set
731CONFIG_RPCSEC_GSS_KRB5=y 884CONFIG_RPCSEC_GSS_KRB5=y
732# CONFIG_RPCSEC_GSS_SPKM3 is not set 885# CONFIG_RPCSEC_GSS_SPKM3 is not set
733# CONFIG_SMB_FS is not set 886# CONFIG_SMB_FS is not set
@@ -740,6 +893,7 @@ CONFIG_RPCSEC_GSS_KRB5=y
740# Partition Types 893# Partition Types
741# 894#
742# CONFIG_PARTITION_ADVANCED is not set 895# CONFIG_PARTITION_ADVANCED is not set
896CONFIG_MAC_PARTITION=y
743CONFIG_MSDOS_PARTITION=y 897CONFIG_MSDOS_PARTITION=y
744# CONFIG_NLS is not set 898# CONFIG_NLS is not set
745# CONFIG_DLM is not set 899# CONFIG_DLM is not set
@@ -751,6 +905,7 @@ CONFIG_BITREVERSE=y
751# CONFIG_GENERIC_FIND_FIRST_BIT is not set 905# CONFIG_GENERIC_FIND_FIRST_BIT is not set
752# CONFIG_CRC_CCITT is not set 906# CONFIG_CRC_CCITT is not set
753# CONFIG_CRC16 is not set 907# CONFIG_CRC16 is not set
908# CONFIG_CRC_T10DIF is not set
754# CONFIG_CRC_ITU_T is not set 909# CONFIG_CRC_ITU_T is not set
755CONFIG_CRC32=y 910CONFIG_CRC32=y
756# CONFIG_CRC7 is not set 911# CONFIG_CRC7 is not set
@@ -774,8 +929,18 @@ CONFIG_FRAME_WARN=1024
774# CONFIG_HEADERS_CHECK is not set 929# CONFIG_HEADERS_CHECK is not set
775# CONFIG_DEBUG_KERNEL is not set 930# CONFIG_DEBUG_KERNEL is not set
776# CONFIG_DEBUG_BUGVERBOSE is not set 931# CONFIG_DEBUG_BUGVERBOSE is not set
932# CONFIG_DEBUG_MEMORY_INIT is not set
933# CONFIG_LATENCYTOP is not set
934CONFIG_SYSCTL_SYSCALL_CHECK=y
935CONFIG_HAVE_FTRACE=y
936CONFIG_HAVE_DYNAMIC_FTRACE=y
937# CONFIG_FTRACE is not set
938# CONFIG_SCHED_TRACER is not set
939# CONFIG_CONTEXT_SWITCH_TRACER is not set
777# CONFIG_SAMPLES is not set 940# CONFIG_SAMPLES is not set
941CONFIG_HAVE_ARCH_KGDB=y
778# CONFIG_IRQSTACKS is not set 942# CONFIG_IRQSTACKS is not set
943# CONFIG_BOOTX_TEXT is not set
779# CONFIG_PPC_EARLY_DEBUG is not set 944# CONFIG_PPC_EARLY_DEBUG is not set
780 945
781# 946#
@@ -829,6 +994,10 @@ CONFIG_CRYPTO_PCBC=m
829# CONFIG_CRYPTO_MD4 is not set 994# CONFIG_CRYPTO_MD4 is not set
830CONFIG_CRYPTO_MD5=y 995CONFIG_CRYPTO_MD5=y
831# CONFIG_CRYPTO_MICHAEL_MIC is not set 996# CONFIG_CRYPTO_MICHAEL_MIC is not set
997# CONFIG_CRYPTO_RMD128 is not set
998# CONFIG_CRYPTO_RMD160 is not set
999# CONFIG_CRYPTO_RMD256 is not set
1000# CONFIG_CRYPTO_RMD320 is not set
832# CONFIG_CRYPTO_SHA1 is not set 1001# CONFIG_CRYPTO_SHA1 is not set
833# CONFIG_CRYPTO_SHA256 is not set 1002# CONFIG_CRYPTO_SHA256 is not set
834# CONFIG_CRYPTO_SHA512 is not set 1003# CONFIG_CRYPTO_SHA512 is not set
diff --git a/arch/powerpc/configs/85xx/ksi8560_defconfig b/arch/powerpc/configs/85xx/ksi8560_defconfig
index b82bb042308a..8bb89f26a20d 100644
--- a/arch/powerpc/configs/85xx/ksi8560_defconfig
+++ b/arch/powerpc/configs/85xx/ksi8560_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc5 3# Linux kernel version: 2.6.27-rc4
4# Mon Jun 9 08:52:30 2008 4# Thu Aug 21 00:52:28 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -15,6 +15,7 @@ CONFIG_PPC_85xx=y
15# CONFIG_44x is not set 15# CONFIG_44x is not set
16# CONFIG_E200 is not set 16# CONFIG_E200 is not set
17CONFIG_E500=y 17CONFIG_E500=y
18# CONFIG_PPC_E500MC is not set
18CONFIG_BOOKE=y 19CONFIG_BOOKE=y
19CONFIG_FSL_BOOKE=y 20CONFIG_FSL_BOOKE=y
20CONFIG_FSL_EMB_PERFMON=y 21CONFIG_FSL_EMB_PERFMON=y
@@ -33,12 +34,14 @@ CONFIG_GENERIC_HARDIRQS=y
33# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set 34# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
34CONFIG_IRQ_PER_CPU=y 35CONFIG_IRQ_PER_CPU=y
35CONFIG_STACKTRACE_SUPPORT=y 36CONFIG_STACKTRACE_SUPPORT=y
37CONFIG_HAVE_LATENCYTOP_SUPPORT=y
36CONFIG_LOCKDEP_SUPPORT=y 38CONFIG_LOCKDEP_SUPPORT=y
37CONFIG_RWSEM_XCHGADD_ALGORITHM=y 39CONFIG_RWSEM_XCHGADD_ALGORITHM=y
38CONFIG_ARCH_HAS_ILOG2_U32=y 40CONFIG_ARCH_HAS_ILOG2_U32=y
39CONFIG_GENERIC_HWEIGHT=y 41CONFIG_GENERIC_HWEIGHT=y
40CONFIG_GENERIC_CALIBRATE_DELAY=y 42CONFIG_GENERIC_CALIBRATE_DELAY=y
41CONFIG_GENERIC_FIND_NEXT_BIT=y 43CONFIG_GENERIC_FIND_NEXT_BIT=y
44CONFIG_GENERIC_GPIO=y
42# CONFIG_ARCH_NO_VIRT_TO_BUS is not set 45# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
43CONFIG_PPC=y 46CONFIG_PPC=y
44CONFIG_EARLY_PRINTK=y 47CONFIG_EARLY_PRINTK=y
@@ -85,7 +88,6 @@ CONFIG_INITRAMFS_SOURCE=""
85CONFIG_SYSCTL=y 88CONFIG_SYSCTL=y
86CONFIG_EMBEDDED=y 89CONFIG_EMBEDDED=y
87CONFIG_SYSCTL_SYSCALL=y 90CONFIG_SYSCTL_SYSCALL=y
88CONFIG_SYSCTL_SYSCALL_CHECK=y
89CONFIG_KALLSYMS=y 91CONFIG_KALLSYMS=y
90# CONFIG_KALLSYMS_ALL is not set 92# CONFIG_KALLSYMS_ALL is not set
91# CONFIG_KALLSYMS_EXTRA_PASS is not set 93# CONFIG_KALLSYMS_EXTRA_PASS is not set
@@ -110,10 +112,16 @@ CONFIG_SLUB=y
110# CONFIG_PROFILING is not set 112# CONFIG_PROFILING is not set
111# CONFIG_MARKERS is not set 113# CONFIG_MARKERS is not set
112CONFIG_HAVE_OPROFILE=y 114CONFIG_HAVE_OPROFILE=y
115CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
116CONFIG_HAVE_IOREMAP_PROT=y
113CONFIG_HAVE_KPROBES=y 117CONFIG_HAVE_KPROBES=y
114CONFIG_HAVE_KRETPROBES=y 118CONFIG_HAVE_KRETPROBES=y
119CONFIG_HAVE_ARCH_TRACEHOOK=y
115# CONFIG_HAVE_DMA_ATTRS is not set 120# CONFIG_HAVE_DMA_ATTRS is not set
121# CONFIG_USE_GENERIC_SMP_HELPERS is not set
122CONFIG_HAVE_CLK=y
116CONFIG_PROC_PAGE_MONITOR=y 123CONFIG_PROC_PAGE_MONITOR=y
124# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
117CONFIG_SLABINFO=y 125CONFIG_SLABINFO=y
118CONFIG_RT_MUTEXES=y 126CONFIG_RT_MUTEXES=y
119# CONFIG_TINY_SHMEM is not set 127# CONFIG_TINY_SHMEM is not set
@@ -124,6 +132,7 @@ CONFIG_BLOCK=y
124# CONFIG_BLK_DEV_IO_TRACE is not set 132# CONFIG_BLK_DEV_IO_TRACE is not set
125# CONFIG_LSF is not set 133# CONFIG_LSF is not set
126# CONFIG_BLK_DEV_BSG is not set 134# CONFIG_BLK_DEV_BSG is not set
135# CONFIG_BLK_DEV_INTEGRITY is not set
127 136
128# 137#
129# IO Schedulers 138# IO Schedulers
@@ -142,8 +151,6 @@ CONFIG_CLASSIC_RCU=y
142# 151#
143# Platform support 152# Platform support
144# 153#
145# CONFIG_PPC_MPC512x is not set
146# CONFIG_PPC_MPC5121 is not set
147# CONFIG_PPC_CELL is not set 154# CONFIG_PPC_CELL is not set
148# CONFIG_PPC_CELL_NATIVE is not set 155# CONFIG_PPC_CELL_NATIVE is not set
149# CONFIG_PQ2ADS is not set 156# CONFIG_PQ2ADS is not set
@@ -152,11 +159,13 @@ CONFIG_MPC85xx=y
152# CONFIG_MPC8560_ADS is not set 159# CONFIG_MPC8560_ADS is not set
153# CONFIG_MPC85xx_CDS is not set 160# CONFIG_MPC85xx_CDS is not set
154# CONFIG_MPC85xx_MDS is not set 161# CONFIG_MPC85xx_MDS is not set
162# CONFIG_MPC8536_DS is not set
155# CONFIG_MPC85xx_DS is not set 163# CONFIG_MPC85xx_DS is not set
156CONFIG_KSI8560=y 164CONFIG_KSI8560=y
157# CONFIG_STX_GP3 is not set 165# CONFIG_STX_GP3 is not set
158# CONFIG_TQM8540 is not set 166# CONFIG_TQM8540 is not set
159# CONFIG_TQM8541 is not set 167# CONFIG_TQM8541 is not set
168# CONFIG_TQM8548 is not set
160# CONFIG_TQM8555 is not set 169# CONFIG_TQM8555 is not set
161# CONFIG_TQM8560 is not set 170# CONFIG_TQM8560 is not set
162# CONFIG_SBC8548 is not set 171# CONFIG_SBC8548 is not set
@@ -173,7 +182,6 @@ CONFIG_MPIC=y
173# CONFIG_GENERIC_IOMAP is not set 182# CONFIG_GENERIC_IOMAP is not set
174# CONFIG_CPU_FREQ is not set 183# CONFIG_CPU_FREQ is not set
175CONFIG_CPM2=y 184CONFIG_CPM2=y
176CONFIG_PPC_CPM_NEW_BINDING=y
177# CONFIG_FSL_ULI1575 is not set 185# CONFIG_FSL_ULI1575 is not set
178CONFIG_CPM=y 186CONFIG_CPM=y
179 187
@@ -213,6 +221,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
213# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set 221# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
214CONFIG_PAGEFLAGS_EXTENDED=y 222CONFIG_PAGEFLAGS_EXTENDED=y
215CONFIG_SPLIT_PTLOCK_CPUS=4 223CONFIG_SPLIT_PTLOCK_CPUS=4
224CONFIG_MIGRATION=y
216# CONFIG_RESOURCES_64BIT is not set 225# CONFIG_RESOURCES_64BIT is not set
217CONFIG_ZONE_DMA_FLAG=1 226CONFIG_ZONE_DMA_FLAG=1
218CONFIG_BOUNCE=y 227CONFIG_BOUNCE=y
@@ -220,6 +229,7 @@ CONFIG_VIRT_TO_BUS=y
220CONFIG_FORCE_MAX_ZONEORDER=11 229CONFIG_FORCE_MAX_ZONEORDER=11
221# CONFIG_PROC_DEVICETREE is not set 230# CONFIG_PROC_DEVICETREE is not set
222# CONFIG_CMDLINE_BOOL is not set 231# CONFIG_CMDLINE_BOOL is not set
232CONFIG_EXTRA_TARGETS=""
223# CONFIG_PM is not set 233# CONFIG_PM is not set
224# CONFIG_SECCOMP is not set 234# CONFIG_SECCOMP is not set
225CONFIG_ISA_DMA_API=y 235CONFIG_ISA_DMA_API=y
@@ -229,6 +239,7 @@ CONFIG_ISA_DMA_API=y
229# 239#
230CONFIG_ZONE_DMA=y 240CONFIG_ZONE_DMA=y
231CONFIG_FSL_SOC=y 241CONFIG_FSL_SOC=y
242CONFIG_PPC_PCI_CHOICE=y
232# CONFIG_PCI is not set 243# CONFIG_PCI is not set
233# CONFIG_PCI_DOMAINS is not set 244# CONFIG_PCI_DOMAINS is not set
234# CONFIG_PCI_SYSCALL is not set 245# CONFIG_PCI_SYSCALL is not set
@@ -250,10 +261,6 @@ CONFIG_KERNEL_START=0xc0000000
250CONFIG_PHYSICAL_START=0x00000000 261CONFIG_PHYSICAL_START=0x00000000
251CONFIG_PHYSICAL_ALIGN=0x10000000 262CONFIG_PHYSICAL_ALIGN=0x10000000
252CONFIG_TASK_SIZE=0xc0000000 263CONFIG_TASK_SIZE=0xc0000000
253
254#
255# Networking
256#
257CONFIG_NET=y 264CONFIG_NET=y
258 265
259# 266#
@@ -427,6 +434,7 @@ CONFIG_MTD_PHYSMAP_OF=y
427# 434#
428# CONFIG_MTD_UBI is not set 435# CONFIG_MTD_UBI is not set
429CONFIG_OF_DEVICE=y 436CONFIG_OF_DEVICE=y
437CONFIG_OF_GPIO=y
430# CONFIG_PARPORT is not set 438# CONFIG_PARPORT is not set
431CONFIG_BLK_DEV=y 439CONFIG_BLK_DEV=y
432# CONFIG_BLK_DEV_FD is not set 440# CONFIG_BLK_DEV_FD is not set
@@ -440,12 +448,12 @@ CONFIG_BLK_DEV_RAM_SIZE=32768
440# CONFIG_BLK_DEV_XIP is not set 448# CONFIG_BLK_DEV_XIP is not set
441# CONFIG_CDROM_PKTCDVD is not set 449# CONFIG_CDROM_PKTCDVD is not set
442# CONFIG_ATA_OVER_ETH is not set 450# CONFIG_ATA_OVER_ETH is not set
451# CONFIG_BLK_DEV_HD is not set
443CONFIG_MISC_DEVICES=y 452CONFIG_MISC_DEVICES=y
444# CONFIG_EEPROM_93CX6 is not set 453# CONFIG_EEPROM_93CX6 is not set
445# CONFIG_ENCLOSURE_SERVICES is not set 454# CONFIG_ENCLOSURE_SERVICES is not set
446CONFIG_HAVE_IDE=y 455CONFIG_HAVE_IDE=y
447CONFIG_IDE=y 456CONFIG_IDE=y
448CONFIG_IDE_MAX_HWIFS=4
449CONFIG_BLK_DEV_IDE=y 457CONFIG_BLK_DEV_IDE=y
450 458
451# 459#
@@ -463,11 +471,8 @@ CONFIG_IDE_PROC_FS=y
463# 471#
464# IDE chipset support/bugfixes 472# IDE chipset support/bugfixes
465# 473#
466CONFIG_IDE_GENERIC=y
467# CONFIG_BLK_DEV_PLATFORM is not set 474# CONFIG_BLK_DEV_PLATFORM is not set
468# CONFIG_BLK_DEV_IDEDMA is not set 475# CONFIG_BLK_DEV_IDEDMA is not set
469# CONFIG_BLK_DEV_HD_ONLY is not set
470# CONFIG_BLK_DEV_HD is not set
471 476
472# 477#
473# SCSI device support 478# SCSI device support
@@ -480,7 +485,6 @@ CONFIG_IDE_GENERIC=y
480# CONFIG_MD is not set 485# CONFIG_MD is not set
481# CONFIG_MACINTOSH_DRIVERS is not set 486# CONFIG_MACINTOSH_DRIVERS is not set
482CONFIG_NETDEVICES=y 487CONFIG_NETDEVICES=y
483# CONFIG_NETDEVICES_MULTIQUEUE is not set
484# CONFIG_DUMMY is not set 488# CONFIG_DUMMY is not set
485# CONFIG_BONDING is not set 489# CONFIG_BONDING is not set
486# CONFIG_MACVLAN is not set 490# CONFIG_MACVLAN is not set
@@ -504,6 +508,7 @@ CONFIG_MARVELL_PHY=y
504# CONFIG_REALTEK_PHY is not set 508# CONFIG_REALTEK_PHY is not set
505# CONFIG_FIXED_PHY is not set 509# CONFIG_FIXED_PHY is not set
506CONFIG_MDIO_BITBANG=y 510CONFIG_MDIO_BITBANG=y
511# CONFIG_MDIO_OF_GPIO is not set
507CONFIG_NET_ETHERNET=y 512CONFIG_NET_ETHERNET=y
508CONFIG_MII=y 513CONFIG_MII=y
509# CONFIG_IBM_NEW_EMAC_ZMII is not set 514# CONFIG_IBM_NEW_EMAC_ZMII is not set
@@ -516,9 +521,7 @@ CONFIG_FS_ENET=y
516CONFIG_FS_ENET_HAS_FCC=y 521CONFIG_FS_ENET_HAS_FCC=y
517CONFIG_FS_ENET_MDIO_FCC=y 522CONFIG_FS_ENET_MDIO_FCC=y
518CONFIG_NETDEV_1000=y 523CONFIG_NETDEV_1000=y
519# CONFIG_E1000E_ENABLED is not set
520CONFIG_GIANFAR=y 524CONFIG_GIANFAR=y
521CONFIG_GFAR_NAPI=y
522CONFIG_NETDEV_10000=y 525CONFIG_NETDEV_10000=y
523 526
524# 527#
@@ -606,6 +609,23 @@ CONFIG_GEN_RTC=y
606# CONFIG_TCG_TPM is not set 609# CONFIG_TCG_TPM is not set
607# CONFIG_I2C is not set 610# CONFIG_I2C is not set
608# CONFIG_SPI is not set 611# CONFIG_SPI is not set
612CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
613CONFIG_ARCH_REQUIRE_GPIOLIB=y
614CONFIG_GPIOLIB=y
615# CONFIG_DEBUG_GPIO is not set
616# CONFIG_GPIO_SYSFS is not set
617
618#
619# I2C GPIO expanders:
620#
621
622#
623# PCI GPIO expanders:
624#
625
626#
627# SPI GPIO expanders:
628#
609# CONFIG_W1 is not set 629# CONFIG_W1 is not set
610# CONFIG_POWER_SUPPLY is not set 630# CONFIG_POWER_SUPPLY is not set
611CONFIG_HWMON=y 631CONFIG_HWMON=y
@@ -622,6 +642,7 @@ CONFIG_HWMON=y
622# CONFIG_SENSORS_W83627EHF is not set 642# CONFIG_SENSORS_W83627EHF is not set
623# CONFIG_HWMON_DEBUG_CHIP is not set 643# CONFIG_HWMON_DEBUG_CHIP is not set
624# CONFIG_THERMAL is not set 644# CONFIG_THERMAL is not set
645# CONFIG_THERMAL_HWMON is not set
625# CONFIG_WATCHDOG is not set 646# CONFIG_WATCHDOG is not set
626 647
627# 648#
@@ -633,8 +654,10 @@ CONFIG_SSB_POSSIBLE=y
633# 654#
634# Multifunction device drivers 655# Multifunction device drivers
635# 656#
657# CONFIG_MFD_CORE is not set
636# CONFIG_MFD_SM501 is not set 658# CONFIG_MFD_SM501 is not set
637# CONFIG_HTC_PASIC3 is not set 659# CONFIG_HTC_PASIC3 is not set
660# CONFIG_MFD_TMIO is not set
638 661
639# 662#
640# Multimedia devices 663# Multimedia devices
@@ -664,10 +687,6 @@ CONFIG_VIDEO_OUTPUT_CONTROL=y
664# Display device support 687# Display device support
665# 688#
666# CONFIG_DISPLAY_SUPPORT is not set 689# CONFIG_DISPLAY_SUPPORT is not set
667
668#
669# Sound
670#
671# CONFIG_SOUND is not set 690# CONFIG_SOUND is not set
672CONFIG_HID_SUPPORT=y 691CONFIG_HID_SUPPORT=y
673CONFIG_HID=y 692CONFIG_HID=y
@@ -681,6 +700,10 @@ CONFIG_USB_SUPPORT=y
681# CONFIG_USB_OTG_BLACKLIST_HUB is not set 700# CONFIG_USB_OTG_BLACKLIST_HUB is not set
682 701
683# 702#
703# Enable Host or Gadget support to see Inventra options
704#
705
706#
684# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 707# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
685# 708#
686# CONFIG_USB_GADGET is not set 709# CONFIG_USB_GADGET is not set
@@ -759,6 +782,7 @@ CONFIG_TMPFS=y
759# CONFIG_CRAMFS is not set 782# CONFIG_CRAMFS is not set
760# CONFIG_VXFS_FS is not set 783# CONFIG_VXFS_FS is not set
761# CONFIG_MINIX_FS is not set 784# CONFIG_MINIX_FS is not set
785# CONFIG_OMFS_FS is not set
762# CONFIG_HPFS_FS is not set 786# CONFIG_HPFS_FS is not set
763# CONFIG_QNX4FS_FS is not set 787# CONFIG_QNX4FS_FS is not set
764# CONFIG_ROMFS_FS is not set 788# CONFIG_ROMFS_FS is not set
@@ -768,12 +792,11 @@ CONFIG_NETWORK_FILESYSTEMS=y
768CONFIG_NFS_FS=y 792CONFIG_NFS_FS=y
769# CONFIG_NFS_V3 is not set 793# CONFIG_NFS_V3 is not set
770# CONFIG_NFS_V4 is not set 794# CONFIG_NFS_V4 is not set
771# CONFIG_NFSD is not set
772CONFIG_ROOT_NFS=y 795CONFIG_ROOT_NFS=y
796# CONFIG_NFSD is not set
773CONFIG_LOCKD=y 797CONFIG_LOCKD=y
774CONFIG_NFS_COMMON=y 798CONFIG_NFS_COMMON=y
775CONFIG_SUNRPC=y 799CONFIG_SUNRPC=y
776# CONFIG_SUNRPC_BIND34 is not set
777# CONFIG_RPCSEC_GSS_KRB5 is not set 800# CONFIG_RPCSEC_GSS_KRB5 is not set
778# CONFIG_RPCSEC_GSS_SPKM3 is not set 801# CONFIG_RPCSEC_GSS_SPKM3 is not set
779# CONFIG_SMB_FS is not set 802# CONFIG_SMB_FS is not set
@@ -809,6 +832,7 @@ CONFIG_BITREVERSE=y
809# CONFIG_GENERIC_FIND_FIRST_BIT is not set 832# CONFIG_GENERIC_FIND_FIRST_BIT is not set
810# CONFIG_CRC_CCITT is not set 833# CONFIG_CRC_CCITT is not set
811# CONFIG_CRC16 is not set 834# CONFIG_CRC16 is not set
835# CONFIG_CRC_T10DIF is not set
812# CONFIG_CRC_ITU_T is not set 836# CONFIG_CRC_ITU_T is not set
813CONFIG_CRC32=y 837CONFIG_CRC32=y
814# CONFIG_CRC7 is not set 838# CONFIG_CRC7 is not set
@@ -833,6 +857,8 @@ CONFIG_DEBUG_FS=y
833CONFIG_DEBUG_KERNEL=y 857CONFIG_DEBUG_KERNEL=y
834# CONFIG_DEBUG_SHIRQ is not set 858# CONFIG_DEBUG_SHIRQ is not set
835CONFIG_DETECT_SOFTLOCKUP=y 859CONFIG_DETECT_SOFTLOCKUP=y
860# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
861CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
836CONFIG_SCHED_DEBUG=y 862CONFIG_SCHED_DEBUG=y
837# CONFIG_SCHEDSTATS is not set 863# CONFIG_SCHEDSTATS is not set
838# CONFIG_TIMER_STATS is not set 864# CONFIG_TIMER_STATS is not set
@@ -851,17 +877,29 @@ CONFIG_DEBUG_MUTEXES=y
851# CONFIG_DEBUG_INFO is not set 877# CONFIG_DEBUG_INFO is not set
852# CONFIG_DEBUG_VM is not set 878# CONFIG_DEBUG_VM is not set
853# CONFIG_DEBUG_WRITECOUNT is not set 879# CONFIG_DEBUG_WRITECOUNT is not set
880# CONFIG_DEBUG_MEMORY_INIT is not set
854# CONFIG_DEBUG_LIST is not set 881# CONFIG_DEBUG_LIST is not set
855# CONFIG_DEBUG_SG is not set 882# CONFIG_DEBUG_SG is not set
856# CONFIG_BOOT_PRINTK_DELAY is not set 883# CONFIG_BOOT_PRINTK_DELAY is not set
884# CONFIG_RCU_TORTURE_TEST is not set
857# CONFIG_BACKTRACE_SELF_TEST is not set 885# CONFIG_BACKTRACE_SELF_TEST is not set
858# CONFIG_FAULT_INJECTION is not set 886# CONFIG_FAULT_INJECTION is not set
887# CONFIG_LATENCYTOP is not set
888CONFIG_SYSCTL_SYSCALL_CHECK=y
889CONFIG_HAVE_FTRACE=y
890CONFIG_HAVE_DYNAMIC_FTRACE=y
891# CONFIG_FTRACE is not set
892# CONFIG_SCHED_TRACER is not set
893# CONFIG_CONTEXT_SWITCH_TRACER is not set
859# CONFIG_SAMPLES is not set 894# CONFIG_SAMPLES is not set
895CONFIG_HAVE_ARCH_KGDB=y
896# CONFIG_KGDB is not set
860# CONFIG_DEBUG_STACKOVERFLOW is not set 897# CONFIG_DEBUG_STACKOVERFLOW is not set
861# CONFIG_DEBUG_STACK_USAGE is not set 898# CONFIG_DEBUG_STACK_USAGE is not set
862# CONFIG_DEBUG_PAGEALLOC is not set 899# CONFIG_DEBUG_PAGEALLOC is not set
863# CONFIG_DEBUGGER is not set 900# CONFIG_CODE_PATCHING_SELFTEST is not set
864# CONFIG_KGDB_CONSOLE is not set 901# CONFIG_FTR_FIXUP_SELFTEST is not set
902# CONFIG_XMON is not set
865# CONFIG_IRQSTACKS is not set 903# CONFIG_IRQSTACKS is not set
866# CONFIG_VIRQ_DEBUG is not set 904# CONFIG_VIRQ_DEBUG is not set
867# CONFIG_BDI_SWITCH is not set 905# CONFIG_BDI_SWITCH is not set
@@ -915,6 +953,10 @@ CONFIG_CRYPTO=y
915# CONFIG_CRYPTO_MD4 is not set 953# CONFIG_CRYPTO_MD4 is not set
916# CONFIG_CRYPTO_MD5 is not set 954# CONFIG_CRYPTO_MD5 is not set
917# CONFIG_CRYPTO_MICHAEL_MIC is not set 955# CONFIG_CRYPTO_MICHAEL_MIC is not set
956# CONFIG_CRYPTO_RMD128 is not set
957# CONFIG_CRYPTO_RMD160 is not set
958# CONFIG_CRYPTO_RMD256 is not set
959# CONFIG_CRYPTO_RMD320 is not set
918# CONFIG_CRYPTO_SHA1 is not set 960# CONFIG_CRYPTO_SHA1 is not set
919# CONFIG_CRYPTO_SHA256 is not set 961# CONFIG_CRYPTO_SHA256 is not set
920# CONFIG_CRYPTO_SHA512 is not set 962# CONFIG_CRYPTO_SHA512 is not set
@@ -946,6 +988,7 @@ CONFIG_CRYPTO=y
946# CONFIG_CRYPTO_DEFLATE is not set 988# CONFIG_CRYPTO_DEFLATE is not set
947# CONFIG_CRYPTO_LZO is not set 989# CONFIG_CRYPTO_LZO is not set
948CONFIG_CRYPTO_HW=y 990CONFIG_CRYPTO_HW=y
949# CONFIG_PPC_CLOCK is not set 991# CONFIG_CRYPTO_DEV_TALITOS is not set
992CONFIG_PPC_CLOCK=y
950CONFIG_PPC_LIB_RHEAP=y 993CONFIG_PPC_LIB_RHEAP=y
951# CONFIG_VIRTUALIZATION is not set 994# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/configs/mpc8536_ds_defconfig b/arch/powerpc/configs/85xx/mpc8536_ds_defconfig
index f1e2931de5da..6b516bea6e75 100644
--- a/arch/powerpc/configs/mpc8536_ds_defconfig
+++ b/arch/powerpc/configs/85xx/mpc8536_ds_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc8 3# Linux kernel version: 2.6.27-rc4
4# Wed Jul 2 01:34:26 2008 4# Thu Aug 21 07:18:18 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -34,6 +34,7 @@ CONFIG_GENERIC_HARDIRQS=y
34# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set 34# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
35CONFIG_IRQ_PER_CPU=y 35CONFIG_IRQ_PER_CPU=y
36CONFIG_STACKTRACE_SUPPORT=y 36CONFIG_STACKTRACE_SUPPORT=y
37CONFIG_HAVE_LATENCYTOP_SUPPORT=y
37CONFIG_LOCKDEP_SUPPORT=y 38CONFIG_LOCKDEP_SUPPORT=y
38CONFIG_RWSEM_XCHGADD_ALGORITHM=y 39CONFIG_RWSEM_XCHGADD_ALGORITHM=y
39CONFIG_ARCH_HAS_ILOG2_U32=y 40CONFIG_ARCH_HAS_ILOG2_U32=y
@@ -93,7 +94,6 @@ CONFIG_INITRAMFS_SOURCE=""
93CONFIG_SYSCTL=y 94CONFIG_SYSCTL=y
94CONFIG_EMBEDDED=y 95CONFIG_EMBEDDED=y
95CONFIG_SYSCTL_SYSCALL=y 96CONFIG_SYSCTL_SYSCALL=y
96CONFIG_SYSCTL_SYSCALL_CHECK=y
97CONFIG_KALLSYMS=y 97CONFIG_KALLSYMS=y
98CONFIG_KALLSYMS_ALL=y 98CONFIG_KALLSYMS_ALL=y
99CONFIG_KALLSYMS_EXTRA_PASS=y 99CONFIG_KALLSYMS_EXTRA_PASS=y
@@ -119,10 +119,16 @@ CONFIG_SLUB=y
119# CONFIG_MARKERS is not set 119# CONFIG_MARKERS is not set
120CONFIG_HAVE_OPROFILE=y 120CONFIG_HAVE_OPROFILE=y
121# CONFIG_KPROBES is not set 121# CONFIG_KPROBES is not set
122CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
123CONFIG_HAVE_IOREMAP_PROT=y
122CONFIG_HAVE_KPROBES=y 124CONFIG_HAVE_KPROBES=y
123CONFIG_HAVE_KRETPROBES=y 125CONFIG_HAVE_KRETPROBES=y
126CONFIG_HAVE_ARCH_TRACEHOOK=y
124# CONFIG_HAVE_DMA_ATTRS is not set 127# CONFIG_HAVE_DMA_ATTRS is not set
128# CONFIG_USE_GENERIC_SMP_HELPERS is not set
129# CONFIG_HAVE_CLK is not set
125CONFIG_PROC_PAGE_MONITOR=y 130CONFIG_PROC_PAGE_MONITOR=y
131# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
126CONFIG_SLABINFO=y 132CONFIG_SLABINFO=y
127CONFIG_RT_MUTEXES=y 133CONFIG_RT_MUTEXES=y
128# CONFIG_TINY_SHMEM is not set 134# CONFIG_TINY_SHMEM is not set
@@ -139,6 +145,7 @@ CONFIG_LBD=y
139# CONFIG_BLK_DEV_IO_TRACE is not set 145# CONFIG_BLK_DEV_IO_TRACE is not set
140# CONFIG_LSF is not set 146# CONFIG_LSF is not set
141# CONFIG_BLK_DEV_BSG is not set 147# CONFIG_BLK_DEV_BSG is not set
148# CONFIG_BLK_DEV_INTEGRITY is not set
142 149
143# 150#
144# IO Schedulers 151# IO Schedulers
@@ -157,8 +164,6 @@ CONFIG_CLASSIC_RCU=y
157# 164#
158# Platform support 165# Platform support
159# 166#
160# CONFIG_PPC_MPC512x is not set
161# CONFIG_PPC_MPC5121 is not set
162# CONFIG_PPC_CELL is not set 167# CONFIG_PPC_CELL is not set
163# CONFIG_PPC_CELL_NATIVE is not set 168# CONFIG_PPC_CELL_NATIVE is not set
164# CONFIG_PQ2ADS is not set 169# CONFIG_PQ2ADS is not set
@@ -205,7 +210,7 @@ CONFIG_HZ_250=y
205# CONFIG_HZ_300 is not set 210# CONFIG_HZ_300 is not set
206# CONFIG_HZ_1000 is not set 211# CONFIG_HZ_1000 is not set
207CONFIG_HZ=250 212CONFIG_HZ=250
208# CONFIG_SCHED_HRTICK is not set 213CONFIG_SCHED_HRTICK=y
209CONFIG_PREEMPT_NONE=y 214CONFIG_PREEMPT_NONE=y
210# CONFIG_PREEMPT_VOLUNTARY is not set 215# CONFIG_PREEMPT_VOLUNTARY is not set
211# CONFIG_PREEMPT is not set 216# CONFIG_PREEMPT is not set
@@ -228,6 +233,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
228# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set 233# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
229CONFIG_PAGEFLAGS_EXTENDED=y 234CONFIG_PAGEFLAGS_EXTENDED=y
230CONFIG_SPLIT_PTLOCK_CPUS=4 235CONFIG_SPLIT_PTLOCK_CPUS=4
236CONFIG_MIGRATION=y
231# CONFIG_RESOURCES_64BIT is not set 237# CONFIG_RESOURCES_64BIT is not set
232CONFIG_ZONE_DMA_FLAG=1 238CONFIG_ZONE_DMA_FLAG=1
233CONFIG_BOUNCE=y 239CONFIG_BOUNCE=y
@@ -235,6 +241,7 @@ CONFIG_VIRT_TO_BUS=y
235CONFIG_FORCE_MAX_ZONEORDER=11 241CONFIG_FORCE_MAX_ZONEORDER=11
236CONFIG_PROC_DEVICETREE=y 242CONFIG_PROC_DEVICETREE=y
237# CONFIG_CMDLINE_BOOL is not set 243# CONFIG_CMDLINE_BOOL is not set
244CONFIG_EXTRA_TARGETS=""
238# CONFIG_PM is not set 245# CONFIG_PM is not set
239CONFIG_SECCOMP=y 246CONFIG_SECCOMP=y
240CONFIG_ISA_DMA_API=y 247CONFIG_ISA_DMA_API=y
@@ -246,6 +253,7 @@ CONFIG_ZONE_DMA=y
246CONFIG_PPC_INDIRECT_PCI=y 253CONFIG_PPC_INDIRECT_PCI=y
247CONFIG_FSL_SOC=y 254CONFIG_FSL_SOC=y
248CONFIG_FSL_PCI=y 255CONFIG_FSL_PCI=y
256CONFIG_PPC_PCI_CHOICE=y
249CONFIG_PCI=y 257CONFIG_PCI=y
250CONFIG_PCI_DOMAINS=y 258CONFIG_PCI_DOMAINS=y
251CONFIG_PCI_SYSCALL=y 259CONFIG_PCI_SYSCALL=y
@@ -272,10 +280,6 @@ CONFIG_KERNEL_START=0xc0000000
272CONFIG_PHYSICAL_START=0x00000000 280CONFIG_PHYSICAL_START=0x00000000
273CONFIG_PHYSICAL_ALIGN=0x10000000 281CONFIG_PHYSICAL_ALIGN=0x10000000
274CONFIG_TASK_SIZE=0xc0000000 282CONFIG_TASK_SIZE=0xc0000000
275
276#
277# Networking
278#
279CONFIG_NET=y 283CONFIG_NET=y
280 284
281# 285#
@@ -401,6 +405,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
401CONFIG_STANDALONE=y 405CONFIG_STANDALONE=y
402CONFIG_PREVENT_FIRMWARE_BUILD=y 406CONFIG_PREVENT_FIRMWARE_BUILD=y
403CONFIG_FW_LOADER=y 407CONFIG_FW_LOADER=y
408CONFIG_FIRMWARE_IN_KERNEL=y
409CONFIG_EXTRA_FIRMWARE=""
404# CONFIG_DEBUG_DRIVER is not set 410# CONFIG_DEBUG_DRIVER is not set
405# CONFIG_DEBUG_DEVRES is not set 411# CONFIG_DEBUG_DEVRES is not set
406# CONFIG_SYS_HYPERVISOR is not set 412# CONFIG_SYS_HYPERVISOR is not set
@@ -427,12 +433,14 @@ CONFIG_BLK_DEV_RAM_SIZE=524288
427# CONFIG_BLK_DEV_XIP is not set 433# CONFIG_BLK_DEV_XIP is not set
428# CONFIG_CDROM_PKTCDVD is not set 434# CONFIG_CDROM_PKTCDVD is not set
429# CONFIG_ATA_OVER_ETH is not set 435# CONFIG_ATA_OVER_ETH is not set
436# CONFIG_BLK_DEV_HD is not set
430CONFIG_MISC_DEVICES=y 437CONFIG_MISC_DEVICES=y
431# CONFIG_PHANTOM is not set 438# CONFIG_PHANTOM is not set
432# CONFIG_EEPROM_93CX6 is not set 439# CONFIG_EEPROM_93CX6 is not set
433# CONFIG_SGI_IOC4 is not set 440# CONFIG_SGI_IOC4 is not set
434# CONFIG_TIFM_CORE is not set 441# CONFIG_TIFM_CORE is not set
435# CONFIG_ENCLOSURE_SERVICES is not set 442# CONFIG_ENCLOSURE_SERVICES is not set
443# CONFIG_HP_ILO is not set
436CONFIG_HAVE_IDE=y 444CONFIG_HAVE_IDE=y
437# CONFIG_IDE is not set 445# CONFIG_IDE is not set
438 446
@@ -512,6 +520,7 @@ CONFIG_SCSI_LOWLEVEL=y
512# CONFIG_SCSI_NSP32 is not set 520# CONFIG_SCSI_NSP32 is not set
513# CONFIG_SCSI_DEBUG is not set 521# CONFIG_SCSI_DEBUG is not set
514# CONFIG_SCSI_SRP is not set 522# CONFIG_SCSI_SRP is not set
523# CONFIG_SCSI_DH is not set
515CONFIG_ATA=y 524CONFIG_ATA=y
516# CONFIG_ATA_NONSTANDARD is not set 525# CONFIG_ATA_NONSTANDARD is not set
517CONFIG_SATA_PMP=y 526CONFIG_SATA_PMP=y
@@ -588,7 +597,6 @@ CONFIG_SATA_SIL=y
588# CONFIG_I2O is not set 597# CONFIG_I2O is not set
589# CONFIG_MACINTOSH_DRIVERS is not set 598# CONFIG_MACINTOSH_DRIVERS is not set
590CONFIG_NETDEVICES=y 599CONFIG_NETDEVICES=y
591# CONFIG_NETDEVICES_MULTIQUEUE is not set
592CONFIG_DUMMY=y 600CONFIG_DUMMY=y
593# CONFIG_BONDING is not set 601# CONFIG_BONDING is not set
594# CONFIG_MACVLAN is not set 602# CONFIG_MACVLAN is not set
@@ -632,7 +640,6 @@ CONFIG_NETDEV_1000=y
632# CONFIG_DL2K is not set 640# CONFIG_DL2K is not set
633# CONFIG_E1000 is not set 641# CONFIG_E1000 is not set
634# CONFIG_E1000E is not set 642# CONFIG_E1000E is not set
635# CONFIG_E1000E_ENABLED is not set
636# CONFIG_IP1000 is not set 643# CONFIG_IP1000 is not set
637# CONFIG_IGB is not set 644# CONFIG_IGB is not set
638# CONFIG_NS83820 is not set 645# CONFIG_NS83820 is not set
@@ -648,9 +655,9 @@ CONFIG_SKY2=y
648# CONFIG_TIGON3 is not set 655# CONFIG_TIGON3 is not set
649# CONFIG_BNX2 is not set 656# CONFIG_BNX2 is not set
650CONFIG_GIANFAR=y 657CONFIG_GIANFAR=y
651CONFIG_GFAR_NAPI=y
652# CONFIG_QLA3XXX is not set 658# CONFIG_QLA3XXX is not set
653# CONFIG_ATL1 is not set 659# CONFIG_ATL1 is not set
660# CONFIG_ATL1E is not set
654CONFIG_NETDEV_10000=y 661CONFIG_NETDEV_10000=y
655# CONFIG_CHELSIO_T1 is not set 662# CONFIG_CHELSIO_T1 is not set
656# CONFIG_CHELSIO_T3 is not set 663# CONFIG_CHELSIO_T3 is not set
@@ -727,12 +734,14 @@ CONFIG_SERIO_SERPORT=y
727# CONFIG_SERIO_PCIPS2 is not set 734# CONFIG_SERIO_PCIPS2 is not set
728CONFIG_SERIO_LIBPS2=y 735CONFIG_SERIO_LIBPS2=y
729# CONFIG_SERIO_RAW is not set 736# CONFIG_SERIO_RAW is not set
737# CONFIG_SERIO_XILINX_XPS_PS2 is not set
730# CONFIG_GAMEPORT is not set 738# CONFIG_GAMEPORT is not set
731 739
732# 740#
733# Character devices 741# Character devices
734# 742#
735CONFIG_VT=y 743CONFIG_VT=y
744CONFIG_CONSOLE_TRANSLATIONS=y
736CONFIG_VT_CONSOLE=y 745CONFIG_VT_CONSOLE=y
737CONFIG_HW_CONSOLE=y 746CONFIG_HW_CONSOLE=y
738# CONFIG_VT_HW_CONSOLE_BINDING is not set 747# CONFIG_VT_HW_CONSOLE_BINDING is not set
@@ -766,7 +775,7 @@ CONFIG_UNIX98_PTYS=y
766CONFIG_LEGACY_PTYS=y 775CONFIG_LEGACY_PTYS=y
767CONFIG_LEGACY_PTY_COUNT=256 776CONFIG_LEGACY_PTY_COUNT=256
768# CONFIG_IPMI_HANDLER is not set 777# CONFIG_IPMI_HANDLER is not set
769# CONFIG_HW_RANDOM is not set 778CONFIG_HW_RANDOM=y
770# CONFIG_NVRAM is not set 779# CONFIG_NVRAM is not set
771# CONFIG_R3964 is not set 780# CONFIG_R3964 is not set
772# CONFIG_APPLICOM is not set 781# CONFIG_APPLICOM is not set
@@ -776,43 +785,64 @@ CONFIG_DEVPORT=y
776CONFIG_I2C=y 785CONFIG_I2C=y
777CONFIG_I2C_BOARDINFO=y 786CONFIG_I2C_BOARDINFO=y
778# CONFIG_I2C_CHARDEV is not set 787# CONFIG_I2C_CHARDEV is not set
788CONFIG_I2C_HELPER_AUTO=y
779 789
780# 790#
781# I2C Hardware Bus support 791# I2C Hardware Bus support
782# 792#
793
794#
795# PC SMBus host controller drivers
796#
783# CONFIG_I2C_ALI1535 is not set 797# CONFIG_I2C_ALI1535 is not set
784# CONFIG_I2C_ALI1563 is not set 798# CONFIG_I2C_ALI1563 is not set
785# CONFIG_I2C_ALI15X3 is not set 799# CONFIG_I2C_ALI15X3 is not set
786# CONFIG_I2C_AMD756 is not set 800# CONFIG_I2C_AMD756 is not set
787# CONFIG_I2C_AMD8111 is not set 801# CONFIG_I2C_AMD8111 is not set
788# CONFIG_I2C_I801 is not set 802# CONFIG_I2C_I801 is not set
789# CONFIG_I2C_I810 is not set 803# CONFIG_I2C_ISCH is not set
790# CONFIG_I2C_PIIX4 is not set 804# CONFIG_I2C_PIIX4 is not set
791CONFIG_I2C_MPC=y
792# CONFIG_I2C_NFORCE2 is not set 805# CONFIG_I2C_NFORCE2 is not set
793# CONFIG_I2C_OCORES is not set
794# CONFIG_I2C_PARPORT_LIGHT is not set
795# CONFIG_I2C_PROSAVAGE is not set
796# CONFIG_I2C_SAVAGE4 is not set
797# CONFIG_I2C_SIMTEC is not set
798# CONFIG_I2C_SIS5595 is not set 806# CONFIG_I2C_SIS5595 is not set
799# CONFIG_I2C_SIS630 is not set 807# CONFIG_I2C_SIS630 is not set
800# CONFIG_I2C_SIS96X is not set 808# CONFIG_I2C_SIS96X is not set
801# CONFIG_I2C_TAOS_EVM is not set
802# CONFIG_I2C_STUB is not set
803# CONFIG_I2C_TINY_USB is not set
804# CONFIG_I2C_VIA is not set 809# CONFIG_I2C_VIA is not set
805# CONFIG_I2C_VIAPRO is not set 810# CONFIG_I2C_VIAPRO is not set
811
812#
813# I2C system bus drivers (mostly embedded / system-on-chip)
814#
815CONFIG_I2C_MPC=y
816# CONFIG_I2C_OCORES is not set
817# CONFIG_I2C_SIMTEC is not set
818
819#
820# External I2C/SMBus adapter drivers
821#
822# CONFIG_I2C_PARPORT_LIGHT is not set
823# CONFIG_I2C_TAOS_EVM is not set
824# CONFIG_I2C_TINY_USB is not set
825
826#
827# Graphics adapter I2C/DDC channel drivers
828#
806# CONFIG_I2C_VOODOO3 is not set 829# CONFIG_I2C_VOODOO3 is not set
830
831#
832# Other I2C/SMBus bus drivers
833#
807# CONFIG_I2C_PCA_PLATFORM is not set 834# CONFIG_I2C_PCA_PLATFORM is not set
835# CONFIG_I2C_STUB is not set
808 836
809# 837#
810# Miscellaneous I2C Chip support 838# Miscellaneous I2C Chip support
811# 839#
812# CONFIG_DS1682 is not set 840# CONFIG_DS1682 is not set
841# CONFIG_AT24 is not set
813CONFIG_SENSORS_EEPROM=y 842CONFIG_SENSORS_EEPROM=y
814# CONFIG_SENSORS_PCF8574 is not set 843# CONFIG_SENSORS_PCF8574 is not set
815# CONFIG_PCF8575 is not set 844# CONFIG_PCF8575 is not set
845# CONFIG_SENSORS_PCA9539 is not set
816# CONFIG_SENSORS_PCF8591 is not set 846# CONFIG_SENSORS_PCF8591 is not set
817# CONFIG_SENSORS_MAX6875 is not set 847# CONFIG_SENSORS_MAX6875 is not set
818# CONFIG_SENSORS_TSL2550 is not set 848# CONFIG_SENSORS_TSL2550 is not set
@@ -821,6 +851,8 @@ CONFIG_SENSORS_EEPROM=y
821# CONFIG_I2C_DEBUG_BUS is not set 851# CONFIG_I2C_DEBUG_BUS is not set
822# CONFIG_I2C_DEBUG_CHIP is not set 852# CONFIG_I2C_DEBUG_CHIP is not set
823# CONFIG_SPI is not set 853# CONFIG_SPI is not set
854CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
855# CONFIG_GPIOLIB is not set
824# CONFIG_W1 is not set 856# CONFIG_W1 is not set
825# CONFIG_POWER_SUPPLY is not set 857# CONFIG_POWER_SUPPLY is not set
826# CONFIG_HWMON is not set 858# CONFIG_HWMON is not set
@@ -836,8 +868,10 @@ CONFIG_SSB_POSSIBLE=y
836# 868#
837# Multifunction device drivers 869# Multifunction device drivers
838# 870#
871# CONFIG_MFD_CORE is not set
839# CONFIG_MFD_SM501 is not set 872# CONFIG_MFD_SM501 is not set
840# CONFIG_HTC_PASIC3 is not set 873# CONFIG_HTC_PASIC3 is not set
874# CONFIG_MFD_TMIO is not set
841 875
842# 876#
843# Multimedia devices 877# Multimedia devices
@@ -879,6 +913,7 @@ CONFIG_DVB_CAPTURE_DRIVERS=y
879# CONFIG_DVB_TTUSB_BUDGET is not set 913# CONFIG_DVB_TTUSB_BUDGET is not set
880# CONFIG_DVB_TTUSB_DEC is not set 914# CONFIG_DVB_TTUSB_DEC is not set
881# CONFIG_DVB_CINERGYT2 is not set 915# CONFIG_DVB_CINERGYT2 is not set
916# CONFIG_DVB_SIANO_SMS1XXX is not set
882 917
883# 918#
884# Supported FlexCopII (B2C2) Adapters 919# Supported FlexCopII (B2C2) Adapters
@@ -925,6 +960,7 @@ CONFIG_DVB_CAPTURE_DRIVERS=y
925# CONFIG_DVB_SP887X is not set 960# CONFIG_DVB_SP887X is not set
926# CONFIG_DVB_CX22700 is not set 961# CONFIG_DVB_CX22700 is not set
927# CONFIG_DVB_CX22702 is not set 962# CONFIG_DVB_CX22702 is not set
963# CONFIG_DVB_DRX397XD is not set
928# CONFIG_DVB_L64781 is not set 964# CONFIG_DVB_L64781 is not set
929# CONFIG_DVB_TDA1004X is not set 965# CONFIG_DVB_TDA1004X is not set
930# CONFIG_DVB_NXT6000 is not set 966# CONFIG_DVB_NXT6000 is not set
@@ -992,15 +1028,7 @@ CONFIG_VIDEO_OUTPUT_CONTROL=y
992CONFIG_VGA_CONSOLE=y 1028CONFIG_VGA_CONSOLE=y
993# CONFIG_VGACON_SOFT_SCROLLBACK is not set 1029# CONFIG_VGACON_SOFT_SCROLLBACK is not set
994CONFIG_DUMMY_CONSOLE=y 1030CONFIG_DUMMY_CONSOLE=y
995
996#
997# Sound
998#
999CONFIG_SOUND=y 1031CONFIG_SOUND=y
1000
1001#
1002# Advanced Linux Sound Architecture
1003#
1004CONFIG_SND=y 1032CONFIG_SND=y
1005CONFIG_SND_TIMER=y 1033CONFIG_SND_TIMER=y
1006CONFIG_SND_PCM=y 1034CONFIG_SND_PCM=y
@@ -1012,19 +1040,15 @@ CONFIG_SND_SUPPORT_OLD_API=y
1012CONFIG_SND_VERBOSE_PROCFS=y 1040CONFIG_SND_VERBOSE_PROCFS=y
1013# CONFIG_SND_VERBOSE_PRINTK is not set 1041# CONFIG_SND_VERBOSE_PRINTK is not set
1014# CONFIG_SND_DEBUG is not set 1042# CONFIG_SND_DEBUG is not set
1015 1043CONFIG_SND_VMASTER=y
1016#
1017# Generic devices
1018#
1019CONFIG_SND_AC97_CODEC=y 1044CONFIG_SND_AC97_CODEC=y
1045CONFIG_SND_DRIVERS=y
1020# CONFIG_SND_DUMMY is not set 1046# CONFIG_SND_DUMMY is not set
1021# CONFIG_SND_MTPAV is not set 1047# CONFIG_SND_MTPAV is not set
1022# CONFIG_SND_SERIAL_U16550 is not set 1048# CONFIG_SND_SERIAL_U16550 is not set
1023# CONFIG_SND_MPU401 is not set 1049# CONFIG_SND_MPU401 is not set
1024 1050# CONFIG_SND_AC97_POWER_SAVE is not set
1025# 1051CONFIG_SND_PCI=y
1026# PCI devices
1027#
1028# CONFIG_SND_AD1889 is not set 1052# CONFIG_SND_AD1889 is not set
1029# CONFIG_SND_ALS300 is not set 1053# CONFIG_SND_ALS300 is not set
1030# CONFIG_SND_ALS4000 is not set 1054# CONFIG_SND_ALS4000 is not set
@@ -1086,39 +1110,12 @@ CONFIG_SND_INTEL8X0=y
1086# CONFIG_SND_VIRTUOSO is not set 1110# CONFIG_SND_VIRTUOSO is not set
1087# CONFIG_SND_VX222 is not set 1111# CONFIG_SND_VX222 is not set
1088# CONFIG_SND_YMFPCI is not set 1112# CONFIG_SND_YMFPCI is not set
1089# CONFIG_SND_AC97_POWER_SAVE is not set 1113CONFIG_SND_PPC=y
1090 1114CONFIG_SND_USB=y
1091#
1092# ALSA PowerMac devices
1093#
1094
1095#
1096# ALSA PowerPC devices
1097#
1098
1099#
1100# USB devices
1101#
1102# CONFIG_SND_USB_AUDIO is not set 1115# CONFIG_SND_USB_AUDIO is not set
1103# CONFIG_SND_USB_USX2Y is not set 1116# CONFIG_SND_USB_USX2Y is not set
1104# CONFIG_SND_USB_CAIAQ is not set 1117# CONFIG_SND_USB_CAIAQ is not set
1105
1106#
1107# System on Chip audio support
1108#
1109# CONFIG_SND_SOC is not set 1118# CONFIG_SND_SOC is not set
1110
1111#
1112# ALSA SoC audio for Freescale SOCs
1113#
1114
1115#
1116# SoC Audio for the Texas Instruments OMAP
1117#
1118
1119#
1120# Open Sound System
1121#
1122# CONFIG_SOUND_PRIME is not set 1119# CONFIG_SOUND_PRIME is not set
1123CONFIG_AC97_BUS=y 1120CONFIG_AC97_BUS=y
1124CONFIG_HID_SUPPORT=y 1121CONFIG_HID_SUPPORT=y
@@ -1150,6 +1147,7 @@ CONFIG_USB_DEVICE_CLASS=y
1150# CONFIG_USB_OTG is not set 1147# CONFIG_USB_OTG is not set
1151# CONFIG_USB_OTG_WHITELIST is not set 1148# CONFIG_USB_OTG_WHITELIST is not set
1152# CONFIG_USB_OTG_BLACKLIST_HUB is not set 1149# CONFIG_USB_OTG_BLACKLIST_HUB is not set
1150CONFIG_USB_MON=y
1153 1151
1154# 1152#
1155# USB Host Controller Drivers 1153# USB Host Controller Drivers
@@ -1201,6 +1199,7 @@ CONFIG_USB_STORAGE=y
1201# CONFIG_USB_STORAGE_ALAUDA is not set 1199# CONFIG_USB_STORAGE_ALAUDA is not set
1202# CONFIG_USB_STORAGE_ONETOUCH is not set 1200# CONFIG_USB_STORAGE_ONETOUCH is not set
1203# CONFIG_USB_STORAGE_KARMA is not set 1201# CONFIG_USB_STORAGE_KARMA is not set
1202# CONFIG_USB_STORAGE_SIERRA is not set
1204# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set 1203# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
1205# CONFIG_USB_LIBUSUAL is not set 1204# CONFIG_USB_LIBUSUAL is not set
1206 1205
@@ -1209,7 +1208,6 @@ CONFIG_USB_STORAGE=y
1209# 1208#
1210# CONFIG_USB_MDC800 is not set 1209# CONFIG_USB_MDC800 is not set
1211# CONFIG_USB_MICROTEK is not set 1210# CONFIG_USB_MICROTEK is not set
1212CONFIG_USB_MON=y
1213 1211
1214# 1212#
1215# USB port drivers 1213# USB port drivers
@@ -1222,7 +1220,6 @@ CONFIG_USB_MON=y
1222# CONFIG_USB_EMI62 is not set 1220# CONFIG_USB_EMI62 is not set
1223# CONFIG_USB_EMI26 is not set 1221# CONFIG_USB_EMI26 is not set
1224# CONFIG_USB_ADUTUX is not set 1222# CONFIG_USB_ADUTUX is not set
1225# CONFIG_USB_AUERSWALD is not set
1226# CONFIG_USB_RIO500 is not set 1223# CONFIG_USB_RIO500 is not set
1227# CONFIG_USB_LEGOTOWER is not set 1224# CONFIG_USB_LEGOTOWER is not set
1228# CONFIG_USB_LCD is not set 1225# CONFIG_USB_LCD is not set
@@ -1310,6 +1307,7 @@ CONFIG_DMA_ENGINE=y
1310# DMA Clients 1307# DMA Clients
1311# 1308#
1312# CONFIG_NET_DMA is not set 1309# CONFIG_NET_DMA is not set
1310# CONFIG_DMATEST is not set
1313# CONFIG_UIO is not set 1311# CONFIG_UIO is not set
1314 1312
1315# 1313#
@@ -1387,6 +1385,7 @@ CONFIG_EFS_FS=m
1387CONFIG_CRAMFS=y 1385CONFIG_CRAMFS=y
1388CONFIG_VXFS_FS=m 1386CONFIG_VXFS_FS=m
1389# CONFIG_MINIX_FS is not set 1387# CONFIG_MINIX_FS is not set
1388# CONFIG_OMFS_FS is not set
1390CONFIG_HPFS_FS=m 1389CONFIG_HPFS_FS=m
1391CONFIG_QNX4FS_FS=m 1390CONFIG_QNX4FS_FS=m
1392# CONFIG_ROMFS_FS is not set 1391# CONFIG_ROMFS_FS is not set
@@ -1399,17 +1398,16 @@ CONFIG_NFS_FS=y
1399CONFIG_NFS_V3=y 1398CONFIG_NFS_V3=y
1400# CONFIG_NFS_V3_ACL is not set 1399# CONFIG_NFS_V3_ACL is not set
1401CONFIG_NFS_V4=y 1400CONFIG_NFS_V4=y
1401CONFIG_ROOT_NFS=y
1402CONFIG_NFSD=y 1402CONFIG_NFSD=y
1403# CONFIG_NFSD_V3 is not set 1403# CONFIG_NFSD_V3 is not set
1404# CONFIG_NFSD_V4 is not set 1404# CONFIG_NFSD_V4 is not set
1405CONFIG_ROOT_NFS=y
1406CONFIG_LOCKD=y 1405CONFIG_LOCKD=y
1407CONFIG_LOCKD_V4=y 1406CONFIG_LOCKD_V4=y
1408CONFIG_EXPORTFS=y 1407CONFIG_EXPORTFS=y
1409CONFIG_NFS_COMMON=y 1408CONFIG_NFS_COMMON=y
1410CONFIG_SUNRPC=y 1409CONFIG_SUNRPC=y
1411CONFIG_SUNRPC_GSS=y 1410CONFIG_SUNRPC_GSS=y
1412# CONFIG_SUNRPC_BIND34 is not set
1413CONFIG_RPCSEC_GSS_KRB5=y 1411CONFIG_RPCSEC_GSS_KRB5=y
1414# CONFIG_RPCSEC_GSS_SPKM3 is not set 1412# CONFIG_RPCSEC_GSS_SPKM3 is not set
1415# CONFIG_SMB_FS is not set 1413# CONFIG_SMB_FS is not set
@@ -1488,6 +1486,7 @@ CONFIG_BITREVERSE=y
1488# CONFIG_GENERIC_FIND_FIRST_BIT is not set 1486# CONFIG_GENERIC_FIND_FIRST_BIT is not set
1489# CONFIG_CRC_CCITT is not set 1487# CONFIG_CRC_CCITT is not set
1490# CONFIG_CRC16 is not set 1488# CONFIG_CRC16 is not set
1489CONFIG_CRC_T10DIF=y
1491CONFIG_CRC_ITU_T=m 1490CONFIG_CRC_ITU_T=m
1492CONFIG_CRC32=y 1491CONFIG_CRC32=y
1493# CONFIG_CRC7 is not set 1492# CONFIG_CRC7 is not set
@@ -1513,6 +1512,8 @@ CONFIG_DEBUG_FS=y
1513CONFIG_DEBUG_KERNEL=y 1512CONFIG_DEBUG_KERNEL=y
1514# CONFIG_DEBUG_SHIRQ is not set 1513# CONFIG_DEBUG_SHIRQ is not set
1515CONFIG_DETECT_SOFTLOCKUP=y 1514CONFIG_DETECT_SOFTLOCKUP=y
1515# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
1516CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
1516CONFIG_SCHED_DEBUG=y 1517CONFIG_SCHED_DEBUG=y
1517# CONFIG_SCHEDSTATS is not set 1518# CONFIG_SCHEDSTATS is not set
1518# CONFIG_TIMER_STATS is not set 1519# CONFIG_TIMER_STATS is not set
@@ -1531,19 +1532,29 @@ CONFIG_SCHED_DEBUG=y
1531CONFIG_DEBUG_INFO=y 1532CONFIG_DEBUG_INFO=y
1532# CONFIG_DEBUG_VM is not set 1533# CONFIG_DEBUG_VM is not set
1533# CONFIG_DEBUG_WRITECOUNT is not set 1534# CONFIG_DEBUG_WRITECOUNT is not set
1535# CONFIG_DEBUG_MEMORY_INIT is not set
1534# CONFIG_DEBUG_LIST is not set 1536# CONFIG_DEBUG_LIST is not set
1535# CONFIG_DEBUG_SG is not set 1537# CONFIG_DEBUG_SG is not set
1536# CONFIG_BOOT_PRINTK_DELAY is not set 1538# CONFIG_BOOT_PRINTK_DELAY is not set
1537# CONFIG_RCU_TORTURE_TEST is not set 1539# CONFIG_RCU_TORTURE_TEST is not set
1538# CONFIG_BACKTRACE_SELF_TEST is not set 1540# CONFIG_BACKTRACE_SELF_TEST is not set
1539# CONFIG_FAULT_INJECTION is not set 1541# CONFIG_FAULT_INJECTION is not set
1542# CONFIG_LATENCYTOP is not set
1543CONFIG_SYSCTL_SYSCALL_CHECK=y
1544CONFIG_HAVE_FTRACE=y
1545CONFIG_HAVE_DYNAMIC_FTRACE=y
1546# CONFIG_FTRACE is not set
1547# CONFIG_SCHED_TRACER is not set
1548# CONFIG_CONTEXT_SWITCH_TRACER is not set
1540# CONFIG_SAMPLES is not set 1549# CONFIG_SAMPLES is not set
1550CONFIG_HAVE_ARCH_KGDB=y
1551# CONFIG_KGDB is not set
1541# CONFIG_DEBUG_STACKOVERFLOW is not set 1552# CONFIG_DEBUG_STACKOVERFLOW is not set
1542# CONFIG_DEBUG_STACK_USAGE is not set 1553# CONFIG_DEBUG_STACK_USAGE is not set
1543# CONFIG_DEBUG_PAGEALLOC is not set 1554# CONFIG_DEBUG_PAGEALLOC is not set
1544# CONFIG_DEBUGGER is not set
1545# CONFIG_CODE_PATCHING_SELFTEST is not set 1555# CONFIG_CODE_PATCHING_SELFTEST is not set
1546# CONFIG_FTR_FIXUP_SELFTEST is not set 1556# CONFIG_FTR_FIXUP_SELFTEST is not set
1557# CONFIG_XMON is not set
1547# CONFIG_IRQSTACKS is not set 1558# CONFIG_IRQSTACKS is not set
1548# CONFIG_VIRQ_DEBUG is not set 1559# CONFIG_VIRQ_DEBUG is not set
1549# CONFIG_BDI_SWITCH is not set 1560# CONFIG_BDI_SWITCH is not set
@@ -1561,13 +1572,14 @@ CONFIG_CRYPTO=y
1561# Crypto core or helper 1572# Crypto core or helper
1562# 1573#
1563CONFIG_CRYPTO_ALGAPI=y 1574CONFIG_CRYPTO_ALGAPI=y
1575CONFIG_CRYPTO_AEAD=y
1564CONFIG_CRYPTO_BLKCIPHER=y 1576CONFIG_CRYPTO_BLKCIPHER=y
1565CONFIG_CRYPTO_HASH=y 1577CONFIG_CRYPTO_HASH=y
1566CONFIG_CRYPTO_MANAGER=y 1578CONFIG_CRYPTO_MANAGER=y
1567# CONFIG_CRYPTO_GF128MUL is not set 1579# CONFIG_CRYPTO_GF128MUL is not set
1568# CONFIG_CRYPTO_NULL is not set 1580# CONFIG_CRYPTO_NULL is not set
1569# CONFIG_CRYPTO_CRYPTD is not set 1581# CONFIG_CRYPTO_CRYPTD is not set
1570# CONFIG_CRYPTO_AUTHENC is not set 1582CONFIG_CRYPTO_AUTHENC=y
1571# CONFIG_CRYPTO_TEST is not set 1583# CONFIG_CRYPTO_TEST is not set
1572 1584
1573# 1585#
@@ -1601,6 +1613,10 @@ CONFIG_CRYPTO_HMAC=y
1601# CONFIG_CRYPTO_MD4 is not set 1613# CONFIG_CRYPTO_MD4 is not set
1602CONFIG_CRYPTO_MD5=y 1614CONFIG_CRYPTO_MD5=y
1603# CONFIG_CRYPTO_MICHAEL_MIC is not set 1615# CONFIG_CRYPTO_MICHAEL_MIC is not set
1616# CONFIG_CRYPTO_RMD128 is not set
1617# CONFIG_CRYPTO_RMD160 is not set
1618# CONFIG_CRYPTO_RMD256 is not set
1619# CONFIG_CRYPTO_RMD320 is not set
1604CONFIG_CRYPTO_SHA1=m 1620CONFIG_CRYPTO_SHA1=m
1605# CONFIG_CRYPTO_SHA256 is not set 1621# CONFIG_CRYPTO_SHA256 is not set
1606# CONFIG_CRYPTO_SHA512 is not set 1622# CONFIG_CRYPTO_SHA512 is not set
@@ -1633,5 +1649,6 @@ CONFIG_CRYPTO_DES=y
1633# CONFIG_CRYPTO_LZO is not set 1649# CONFIG_CRYPTO_LZO is not set
1634CONFIG_CRYPTO_HW=y 1650CONFIG_CRYPTO_HW=y
1635# CONFIG_CRYPTO_DEV_HIFN_795X is not set 1651# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1652CONFIG_CRYPTO_DEV_TALITOS=y
1636# CONFIG_PPC_CLOCK is not set 1653# CONFIG_PPC_CLOCK is not set
1637# CONFIG_VIRTUALIZATION is not set 1654# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/configs/85xx/mpc8540_ads_defconfig b/arch/powerpc/configs/85xx/mpc8540_ads_defconfig
index f33fd516fd54..1ea181f826f1 100644
--- a/arch/powerpc/configs/85xx/mpc8540_ads_defconfig
+++ b/arch/powerpc/configs/85xx/mpc8540_ads_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc5 3# Linux kernel version: 2.6.27-rc4
4# Mon Jun 9 08:52:31 2008 4# Thu Aug 21 00:52:30 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -15,6 +15,7 @@ CONFIG_PPC_85xx=y
15# CONFIG_44x is not set 15# CONFIG_44x is not set
16# CONFIG_E200 is not set 16# CONFIG_E200 is not set
17CONFIG_E500=y 17CONFIG_E500=y
18# CONFIG_PPC_E500MC is not set
18CONFIG_BOOKE=y 19CONFIG_BOOKE=y
19CONFIG_FSL_BOOKE=y 20CONFIG_FSL_BOOKE=y
20CONFIG_FSL_EMB_PERFMON=y 21CONFIG_FSL_EMB_PERFMON=y
@@ -33,6 +34,7 @@ CONFIG_GENERIC_HARDIRQS=y
33# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set 34# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
34CONFIG_IRQ_PER_CPU=y 35CONFIG_IRQ_PER_CPU=y
35CONFIG_STACKTRACE_SUPPORT=y 36CONFIG_STACKTRACE_SUPPORT=y
37CONFIG_HAVE_LATENCYTOP_SUPPORT=y
36CONFIG_LOCKDEP_SUPPORT=y 38CONFIG_LOCKDEP_SUPPORT=y
37CONFIG_RWSEM_XCHGADD_ALGORITHM=y 39CONFIG_RWSEM_XCHGADD_ALGORITHM=y
38CONFIG_ARCH_HAS_ILOG2_U32=y 40CONFIG_ARCH_HAS_ILOG2_U32=y
@@ -89,7 +91,6 @@ CONFIG_INITRAMFS_SOURCE=""
89CONFIG_SYSCTL=y 91CONFIG_SYSCTL=y
90CONFIG_EMBEDDED=y 92CONFIG_EMBEDDED=y
91CONFIG_SYSCTL_SYSCALL=y 93CONFIG_SYSCTL_SYSCALL=y
92CONFIG_SYSCTL_SYSCALL_CHECK=y
93CONFIG_KALLSYMS=y 94CONFIG_KALLSYMS=y
94# CONFIG_KALLSYMS_ALL is not set 95# CONFIG_KALLSYMS_ALL is not set
95# CONFIG_KALLSYMS_EXTRA_PASS is not set 96# CONFIG_KALLSYMS_EXTRA_PASS is not set
@@ -114,10 +115,16 @@ CONFIG_SLUB=y
114# CONFIG_PROFILING is not set 115# CONFIG_PROFILING is not set
115# CONFIG_MARKERS is not set 116# CONFIG_MARKERS is not set
116CONFIG_HAVE_OPROFILE=y 117CONFIG_HAVE_OPROFILE=y
118CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
119CONFIG_HAVE_IOREMAP_PROT=y
117CONFIG_HAVE_KPROBES=y 120CONFIG_HAVE_KPROBES=y
118CONFIG_HAVE_KRETPROBES=y 121CONFIG_HAVE_KRETPROBES=y
122CONFIG_HAVE_ARCH_TRACEHOOK=y
119# CONFIG_HAVE_DMA_ATTRS is not set 123# CONFIG_HAVE_DMA_ATTRS is not set
124# CONFIG_USE_GENERIC_SMP_HELPERS is not set
125# CONFIG_HAVE_CLK is not set
120CONFIG_PROC_PAGE_MONITOR=y 126CONFIG_PROC_PAGE_MONITOR=y
127# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
121CONFIG_SLABINFO=y 128CONFIG_SLABINFO=y
122CONFIG_RT_MUTEXES=y 129CONFIG_RT_MUTEXES=y
123# CONFIG_TINY_SHMEM is not set 130# CONFIG_TINY_SHMEM is not set
@@ -128,6 +135,7 @@ CONFIG_BLOCK=y
128# CONFIG_BLK_DEV_IO_TRACE is not set 135# CONFIG_BLK_DEV_IO_TRACE is not set
129# CONFIG_LSF is not set 136# CONFIG_LSF is not set
130# CONFIG_BLK_DEV_BSG is not set 137# CONFIG_BLK_DEV_BSG is not set
138# CONFIG_BLK_DEV_INTEGRITY is not set
131 139
132# 140#
133# IO Schedulers 141# IO Schedulers
@@ -146,8 +154,6 @@ CONFIG_CLASSIC_RCU=y
146# 154#
147# Platform support 155# Platform support
148# 156#
149# CONFIG_PPC_MPC512x is not set
150# CONFIG_PPC_MPC5121 is not set
151# CONFIG_PPC_CELL is not set 157# CONFIG_PPC_CELL is not set
152# CONFIG_PPC_CELL_NATIVE is not set 158# CONFIG_PPC_CELL_NATIVE is not set
153# CONFIG_PQ2ADS is not set 159# CONFIG_PQ2ADS is not set
@@ -156,11 +162,13 @@ CONFIG_MPC8540_ADS=y
156# CONFIG_MPC8560_ADS is not set 162# CONFIG_MPC8560_ADS is not set
157# CONFIG_MPC85xx_CDS is not set 163# CONFIG_MPC85xx_CDS is not set
158# CONFIG_MPC85xx_MDS is not set 164# CONFIG_MPC85xx_MDS is not set
165# CONFIG_MPC8536_DS is not set
159# CONFIG_MPC85xx_DS is not set 166# CONFIG_MPC85xx_DS is not set
160# CONFIG_KSI8560 is not set 167# CONFIG_KSI8560 is not set
161# CONFIG_STX_GP3 is not set 168# CONFIG_STX_GP3 is not set
162# CONFIG_TQM8540 is not set 169# CONFIG_TQM8540 is not set
163# CONFIG_TQM8541 is not set 170# CONFIG_TQM8541 is not set
171# CONFIG_TQM8548 is not set
164# CONFIG_TQM8555 is not set 172# CONFIG_TQM8555 is not set
165# CONFIG_TQM8560 is not set 173# CONFIG_TQM8560 is not set
166# CONFIG_SBC8548 is not set 174# CONFIG_SBC8548 is not set
@@ -192,7 +200,7 @@ CONFIG_HZ_250=y
192# CONFIG_HZ_300 is not set 200# CONFIG_HZ_300 is not set
193# CONFIG_HZ_1000 is not set 201# CONFIG_HZ_1000 is not set
194CONFIG_HZ=250 202CONFIG_HZ=250
195# CONFIG_SCHED_HRTICK is not set 203CONFIG_SCHED_HRTICK=y
196CONFIG_PREEMPT_NONE=y 204CONFIG_PREEMPT_NONE=y
197# CONFIG_PREEMPT_VOLUNTARY is not set 205# CONFIG_PREEMPT_VOLUNTARY is not set
198# CONFIG_PREEMPT is not set 206# CONFIG_PREEMPT is not set
@@ -215,6 +223,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
215# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set 223# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
216CONFIG_PAGEFLAGS_EXTENDED=y 224CONFIG_PAGEFLAGS_EXTENDED=y
217CONFIG_SPLIT_PTLOCK_CPUS=4 225CONFIG_SPLIT_PTLOCK_CPUS=4
226CONFIG_MIGRATION=y
218# CONFIG_RESOURCES_64BIT is not set 227# CONFIG_RESOURCES_64BIT is not set
219CONFIG_ZONE_DMA_FLAG=1 228CONFIG_ZONE_DMA_FLAG=1
220CONFIG_BOUNCE=y 229CONFIG_BOUNCE=y
@@ -222,6 +231,7 @@ CONFIG_VIRT_TO_BUS=y
222CONFIG_FORCE_MAX_ZONEORDER=11 231CONFIG_FORCE_MAX_ZONEORDER=11
223CONFIG_PROC_DEVICETREE=y 232CONFIG_PROC_DEVICETREE=y
224# CONFIG_CMDLINE_BOOL is not set 233# CONFIG_CMDLINE_BOOL is not set
234CONFIG_EXTRA_TARGETS=""
225# CONFIG_PM is not set 235# CONFIG_PM is not set
226# CONFIG_SECCOMP is not set 236# CONFIG_SECCOMP is not set
227CONFIG_ISA_DMA_API=y 237CONFIG_ISA_DMA_API=y
@@ -231,6 +241,7 @@ CONFIG_ISA_DMA_API=y
231# 241#
232CONFIG_ZONE_DMA=y 242CONFIG_ZONE_DMA=y
233CONFIG_FSL_SOC=y 243CONFIG_FSL_SOC=y
244CONFIG_PPC_PCI_CHOICE=y
234# CONFIG_PCI is not set 245# CONFIG_PCI is not set
235# CONFIG_PCI_DOMAINS is not set 246# CONFIG_PCI_DOMAINS is not set
236# CONFIG_PCI_SYSCALL is not set 247# CONFIG_PCI_SYSCALL is not set
@@ -252,10 +263,6 @@ CONFIG_KERNEL_START=0xc0000000
252CONFIG_PHYSICAL_START=0x00000000 263CONFIG_PHYSICAL_START=0x00000000
253CONFIG_PHYSICAL_ALIGN=0x10000000 264CONFIG_PHYSICAL_ALIGN=0x10000000
254CONFIG_TASK_SIZE=0xc0000000 265CONFIG_TASK_SIZE=0xc0000000
255
256#
257# Networking
258#
259CONFIG_NET=y 266CONFIG_NET=y
260 267
261# 268#
@@ -367,6 +374,7 @@ CONFIG_BLK_DEV_RAM_SIZE=32768
367# CONFIG_BLK_DEV_XIP is not set 374# CONFIG_BLK_DEV_XIP is not set
368# CONFIG_CDROM_PKTCDVD is not set 375# CONFIG_CDROM_PKTCDVD is not set
369# CONFIG_ATA_OVER_ETH is not set 376# CONFIG_ATA_OVER_ETH is not set
377# CONFIG_BLK_DEV_HD is not set
370CONFIG_MISC_DEVICES=y 378CONFIG_MISC_DEVICES=y
371# CONFIG_EEPROM_93CX6 is not set 379# CONFIG_EEPROM_93CX6 is not set
372# CONFIG_ENCLOSURE_SERVICES is not set 380# CONFIG_ENCLOSURE_SERVICES is not set
@@ -384,7 +392,6 @@ CONFIG_HAVE_IDE=y
384# CONFIG_MD is not set 392# CONFIG_MD is not set
385# CONFIG_MACINTOSH_DRIVERS is not set 393# CONFIG_MACINTOSH_DRIVERS is not set
386CONFIG_NETDEVICES=y 394CONFIG_NETDEVICES=y
387# CONFIG_NETDEVICES_MULTIQUEUE is not set
388# CONFIG_DUMMY is not set 395# CONFIG_DUMMY is not set
389# CONFIG_BONDING is not set 396# CONFIG_BONDING is not set
390# CONFIG_MACVLAN is not set 397# CONFIG_MACVLAN is not set
@@ -416,9 +423,7 @@ CONFIG_MII=y
416# CONFIG_IBM_NEW_EMAC_EMAC4 is not set 423# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
417# CONFIG_B44 is not set 424# CONFIG_B44 is not set
418CONFIG_NETDEV_1000=y 425CONFIG_NETDEV_1000=y
419# CONFIG_E1000E_ENABLED is not set
420CONFIG_GIANFAR=y 426CONFIG_GIANFAR=y
421CONFIG_GFAR_NAPI=y
422CONFIG_NETDEV_10000=y 427CONFIG_NETDEV_10000=y
423 428
424# 429#
@@ -504,6 +509,8 @@ CONFIG_GEN_RTC=y
504# CONFIG_TCG_TPM is not set 509# CONFIG_TCG_TPM is not set
505# CONFIG_I2C is not set 510# CONFIG_I2C is not set
506# CONFIG_SPI is not set 511# CONFIG_SPI is not set
512CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
513# CONFIG_GPIOLIB is not set
507# CONFIG_W1 is not set 514# CONFIG_W1 is not set
508# CONFIG_POWER_SUPPLY is not set 515# CONFIG_POWER_SUPPLY is not set
509CONFIG_HWMON=y 516CONFIG_HWMON=y
@@ -520,6 +527,7 @@ CONFIG_HWMON=y
520# CONFIG_SENSORS_W83627EHF is not set 527# CONFIG_SENSORS_W83627EHF is not set
521# CONFIG_HWMON_DEBUG_CHIP is not set 528# CONFIG_HWMON_DEBUG_CHIP is not set
522# CONFIG_THERMAL is not set 529# CONFIG_THERMAL is not set
530# CONFIG_THERMAL_HWMON is not set
523# CONFIG_WATCHDOG is not set 531# CONFIG_WATCHDOG is not set
524 532
525# 533#
@@ -531,8 +539,10 @@ CONFIG_SSB_POSSIBLE=y
531# 539#
532# Multifunction device drivers 540# Multifunction device drivers
533# 541#
542# CONFIG_MFD_CORE is not set
534# CONFIG_MFD_SM501 is not set 543# CONFIG_MFD_SM501 is not set
535# CONFIG_HTC_PASIC3 is not set 544# CONFIG_HTC_PASIC3 is not set
545# CONFIG_MFD_TMIO is not set
536 546
537# 547#
538# Multimedia devices 548# Multimedia devices
@@ -562,10 +572,6 @@ CONFIG_VIDEO_OUTPUT_CONTROL=y
562# Display device support 572# Display device support
563# 573#
564# CONFIG_DISPLAY_SUPPORT is not set 574# CONFIG_DISPLAY_SUPPORT is not set
565
566#
567# Sound
568#
569# CONFIG_SOUND is not set 575# CONFIG_SOUND is not set
570CONFIG_HID_SUPPORT=y 576CONFIG_HID_SUPPORT=y
571CONFIG_HID=y 577CONFIG_HID=y
@@ -579,6 +585,10 @@ CONFIG_USB_SUPPORT=y
579# CONFIG_USB_OTG_BLACKLIST_HUB is not set 585# CONFIG_USB_OTG_BLACKLIST_HUB is not set
580 586
581# 587#
588# Enable Host or Gadget support to see Inventra options
589#
590
591#
582# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 592# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
583# 593#
584# CONFIG_USB_GADGET is not set 594# CONFIG_USB_GADGET is not set
@@ -655,6 +665,7 @@ CONFIG_TMPFS=y
655# CONFIG_CRAMFS is not set 665# CONFIG_CRAMFS is not set
656# CONFIG_VXFS_FS is not set 666# CONFIG_VXFS_FS is not set
657# CONFIG_MINIX_FS is not set 667# CONFIG_MINIX_FS is not set
668# CONFIG_OMFS_FS is not set
658# CONFIG_HPFS_FS is not set 669# CONFIG_HPFS_FS is not set
659# CONFIG_QNX4FS_FS is not set 670# CONFIG_QNX4FS_FS is not set
660# CONFIG_ROMFS_FS is not set 671# CONFIG_ROMFS_FS is not set
@@ -664,12 +675,11 @@ CONFIG_NETWORK_FILESYSTEMS=y
664CONFIG_NFS_FS=y 675CONFIG_NFS_FS=y
665# CONFIG_NFS_V3 is not set 676# CONFIG_NFS_V3 is not set
666# CONFIG_NFS_V4 is not set 677# CONFIG_NFS_V4 is not set
667# CONFIG_NFSD is not set
668CONFIG_ROOT_NFS=y 678CONFIG_ROOT_NFS=y
679# CONFIG_NFSD is not set
669CONFIG_LOCKD=y 680CONFIG_LOCKD=y
670CONFIG_NFS_COMMON=y 681CONFIG_NFS_COMMON=y
671CONFIG_SUNRPC=y 682CONFIG_SUNRPC=y
672# CONFIG_SUNRPC_BIND34 is not set
673# CONFIG_RPCSEC_GSS_KRB5 is not set 683# CONFIG_RPCSEC_GSS_KRB5 is not set
674# CONFIG_RPCSEC_GSS_SPKM3 is not set 684# CONFIG_RPCSEC_GSS_SPKM3 is not set
675# CONFIG_SMB_FS is not set 685# CONFIG_SMB_FS is not set
@@ -705,6 +715,7 @@ CONFIG_BITREVERSE=y
705# CONFIG_GENERIC_FIND_FIRST_BIT is not set 715# CONFIG_GENERIC_FIND_FIRST_BIT is not set
706# CONFIG_CRC_CCITT is not set 716# CONFIG_CRC_CCITT is not set
707# CONFIG_CRC16 is not set 717# CONFIG_CRC16 is not set
718# CONFIG_CRC_T10DIF is not set
708# CONFIG_CRC_ITU_T is not set 719# CONFIG_CRC_ITU_T is not set
709CONFIG_CRC32=y 720CONFIG_CRC32=y
710# CONFIG_CRC7 is not set 721# CONFIG_CRC7 is not set
@@ -729,6 +740,8 @@ CONFIG_FRAME_WARN=1024
729CONFIG_DEBUG_KERNEL=y 740CONFIG_DEBUG_KERNEL=y
730# CONFIG_DEBUG_SHIRQ is not set 741# CONFIG_DEBUG_SHIRQ is not set
731CONFIG_DETECT_SOFTLOCKUP=y 742CONFIG_DETECT_SOFTLOCKUP=y
743# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
744CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
732CONFIG_SCHED_DEBUG=y 745CONFIG_SCHED_DEBUG=y
733# CONFIG_SCHEDSTATS is not set 746# CONFIG_SCHEDSTATS is not set
734# CONFIG_TIMER_STATS is not set 747# CONFIG_TIMER_STATS is not set
@@ -746,16 +759,29 @@ CONFIG_DEBUG_MUTEXES=y
746# CONFIG_DEBUG_INFO is not set 759# CONFIG_DEBUG_INFO is not set
747# CONFIG_DEBUG_VM is not set 760# CONFIG_DEBUG_VM is not set
748# CONFIG_DEBUG_WRITECOUNT is not set 761# CONFIG_DEBUG_WRITECOUNT is not set
762# CONFIG_DEBUG_MEMORY_INIT is not set
749# CONFIG_DEBUG_LIST is not set 763# CONFIG_DEBUG_LIST is not set
750# CONFIG_DEBUG_SG is not set 764# CONFIG_DEBUG_SG is not set
751# CONFIG_BOOT_PRINTK_DELAY is not set 765# CONFIG_BOOT_PRINTK_DELAY is not set
766# CONFIG_RCU_TORTURE_TEST is not set
752# CONFIG_BACKTRACE_SELF_TEST is not set 767# CONFIG_BACKTRACE_SELF_TEST is not set
753# CONFIG_FAULT_INJECTION is not set 768# CONFIG_FAULT_INJECTION is not set
769# CONFIG_LATENCYTOP is not set
770CONFIG_SYSCTL_SYSCALL_CHECK=y
771CONFIG_HAVE_FTRACE=y
772CONFIG_HAVE_DYNAMIC_FTRACE=y
773# CONFIG_FTRACE is not set
774# CONFIG_SCHED_TRACER is not set
775# CONFIG_CONTEXT_SWITCH_TRACER is not set
754# CONFIG_SAMPLES is not set 776# CONFIG_SAMPLES is not set
777CONFIG_HAVE_ARCH_KGDB=y
778# CONFIG_KGDB is not set
755# CONFIG_DEBUG_STACKOVERFLOW is not set 779# CONFIG_DEBUG_STACKOVERFLOW is not set
756# CONFIG_DEBUG_STACK_USAGE is not set 780# CONFIG_DEBUG_STACK_USAGE is not set
757# CONFIG_DEBUG_PAGEALLOC is not set 781# CONFIG_DEBUG_PAGEALLOC is not set
758# CONFIG_DEBUGGER is not set 782# CONFIG_CODE_PATCHING_SELFTEST is not set
783# CONFIG_FTR_FIXUP_SELFTEST is not set
784# CONFIG_XMON is not set
759# CONFIG_IRQSTACKS is not set 785# CONFIG_IRQSTACKS is not set
760# CONFIG_BDI_SWITCH is not set 786# CONFIG_BDI_SWITCH is not set
761# CONFIG_PPC_EARLY_DEBUG is not set 787# CONFIG_PPC_EARLY_DEBUG is not set
@@ -808,6 +834,10 @@ CONFIG_CRYPTO=y
808# CONFIG_CRYPTO_MD4 is not set 834# CONFIG_CRYPTO_MD4 is not set
809# CONFIG_CRYPTO_MD5 is not set 835# CONFIG_CRYPTO_MD5 is not set
810# CONFIG_CRYPTO_MICHAEL_MIC is not set 836# CONFIG_CRYPTO_MICHAEL_MIC is not set
837# CONFIG_CRYPTO_RMD128 is not set
838# CONFIG_CRYPTO_RMD160 is not set
839# CONFIG_CRYPTO_RMD256 is not set
840# CONFIG_CRYPTO_RMD320 is not set
811# CONFIG_CRYPTO_SHA1 is not set 841# CONFIG_CRYPTO_SHA1 is not set
812# CONFIG_CRYPTO_SHA256 is not set 842# CONFIG_CRYPTO_SHA256 is not set
813# CONFIG_CRYPTO_SHA512 is not set 843# CONFIG_CRYPTO_SHA512 is not set
@@ -839,5 +869,6 @@ CONFIG_CRYPTO=y
839# CONFIG_CRYPTO_DEFLATE is not set 869# CONFIG_CRYPTO_DEFLATE is not set
840# CONFIG_CRYPTO_LZO is not set 870# CONFIG_CRYPTO_LZO is not set
841CONFIG_CRYPTO_HW=y 871CONFIG_CRYPTO_HW=y
872# CONFIG_CRYPTO_DEV_TALITOS is not set
842# CONFIG_PPC_CLOCK is not set 873# CONFIG_PPC_CLOCK is not set
843# CONFIG_VIRTUALIZATION is not set 874# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/configs/85xx/mpc8544_ds_defconfig b/arch/powerpc/configs/85xx/mpc8544_ds_defconfig
index a0583e5119f5..1aecdeab9841 100644
--- a/arch/powerpc/configs/85xx/mpc8544_ds_defconfig
+++ b/arch/powerpc/configs/85xx/mpc8544_ds_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc5 3# Linux kernel version: 2.6.27-rc4
4# Mon Jun 9 08:52:32 2008 4# Thu Aug 21 07:20:43 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -15,6 +15,7 @@ CONFIG_PPC_85xx=y
15# CONFIG_44x is not set 15# CONFIG_44x is not set
16# CONFIG_E200 is not set 16# CONFIG_E200 is not set
17CONFIG_E500=y 17CONFIG_E500=y
18# CONFIG_PPC_E500MC is not set
18CONFIG_BOOKE=y 19CONFIG_BOOKE=y
19CONFIG_FSL_BOOKE=y 20CONFIG_FSL_BOOKE=y
20CONFIG_FSL_EMB_PERFMON=y 21CONFIG_FSL_EMB_PERFMON=y
@@ -33,6 +34,7 @@ CONFIG_GENERIC_HARDIRQS=y
33# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set 34# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
34CONFIG_IRQ_PER_CPU=y 35CONFIG_IRQ_PER_CPU=y
35CONFIG_STACKTRACE_SUPPORT=y 36CONFIG_STACKTRACE_SUPPORT=y
37CONFIG_HAVE_LATENCYTOP_SUPPORT=y
36CONFIG_LOCKDEP_SUPPORT=y 38CONFIG_LOCKDEP_SUPPORT=y
37CONFIG_RWSEM_XCHGADD_ALGORITHM=y 39CONFIG_RWSEM_XCHGADD_ALGORITHM=y
38CONFIG_ARCH_HAS_ILOG2_U32=y 40CONFIG_ARCH_HAS_ILOG2_U32=y
@@ -92,7 +94,6 @@ CONFIG_INITRAMFS_SOURCE=""
92CONFIG_SYSCTL=y 94CONFIG_SYSCTL=y
93CONFIG_EMBEDDED=y 95CONFIG_EMBEDDED=y
94CONFIG_SYSCTL_SYSCALL=y 96CONFIG_SYSCTL_SYSCALL=y
95CONFIG_SYSCTL_SYSCALL_CHECK=y
96CONFIG_KALLSYMS=y 97CONFIG_KALLSYMS=y
97CONFIG_KALLSYMS_ALL=y 98CONFIG_KALLSYMS_ALL=y
98CONFIG_KALLSYMS_EXTRA_PASS=y 99CONFIG_KALLSYMS_EXTRA_PASS=y
@@ -118,10 +119,16 @@ CONFIG_SLUB=y
118# CONFIG_MARKERS is not set 119# CONFIG_MARKERS is not set
119CONFIG_HAVE_OPROFILE=y 120CONFIG_HAVE_OPROFILE=y
120# CONFIG_KPROBES is not set 121# CONFIG_KPROBES is not set
122CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
123CONFIG_HAVE_IOREMAP_PROT=y
121CONFIG_HAVE_KPROBES=y 124CONFIG_HAVE_KPROBES=y
122CONFIG_HAVE_KRETPROBES=y 125CONFIG_HAVE_KRETPROBES=y
126CONFIG_HAVE_ARCH_TRACEHOOK=y
123# CONFIG_HAVE_DMA_ATTRS is not set 127# CONFIG_HAVE_DMA_ATTRS is not set
128# CONFIG_USE_GENERIC_SMP_HELPERS is not set
129# CONFIG_HAVE_CLK is not set
124CONFIG_PROC_PAGE_MONITOR=y 130CONFIG_PROC_PAGE_MONITOR=y
131# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
125CONFIG_SLABINFO=y 132CONFIG_SLABINFO=y
126CONFIG_RT_MUTEXES=y 133CONFIG_RT_MUTEXES=y
127# CONFIG_TINY_SHMEM is not set 134# CONFIG_TINY_SHMEM is not set
@@ -138,6 +145,7 @@ CONFIG_LBD=y
138# CONFIG_BLK_DEV_IO_TRACE is not set 145# CONFIG_BLK_DEV_IO_TRACE is not set
139# CONFIG_LSF is not set 146# CONFIG_LSF is not set
140# CONFIG_BLK_DEV_BSG is not set 147# CONFIG_BLK_DEV_BSG is not set
148# CONFIG_BLK_DEV_INTEGRITY is not set
141 149
142# 150#
143# IO Schedulers 151# IO Schedulers
@@ -156,8 +164,6 @@ CONFIG_CLASSIC_RCU=y
156# 164#
157# Platform support 165# Platform support
158# 166#
159# CONFIG_PPC_MPC512x is not set
160# CONFIG_PPC_MPC5121 is not set
161# CONFIG_PPC_CELL is not set 167# CONFIG_PPC_CELL is not set
162# CONFIG_PPC_CELL_NATIVE is not set 168# CONFIG_PPC_CELL_NATIVE is not set
163# CONFIG_PQ2ADS is not set 169# CONFIG_PQ2ADS is not set
@@ -166,11 +172,13 @@ CONFIG_MPC85xx=y
166# CONFIG_MPC8560_ADS is not set 172# CONFIG_MPC8560_ADS is not set
167# CONFIG_MPC85xx_CDS is not set 173# CONFIG_MPC85xx_CDS is not set
168# CONFIG_MPC85xx_MDS is not set 174# CONFIG_MPC85xx_MDS is not set
175# CONFIG_MPC8536_DS is not set
169CONFIG_MPC85xx_DS=y 176CONFIG_MPC85xx_DS=y
170# CONFIG_KSI8560 is not set 177# CONFIG_KSI8560 is not set
171# CONFIG_STX_GP3 is not set 178# CONFIG_STX_GP3 is not set
172# CONFIG_TQM8540 is not set 179# CONFIG_TQM8540 is not set
173# CONFIG_TQM8541 is not set 180# CONFIG_TQM8541 is not set
181# CONFIG_TQM8548 is not set
174# CONFIG_TQM8555 is not set 182# CONFIG_TQM8555 is not set
175# CONFIG_TQM8560 is not set 183# CONFIG_TQM8560 is not set
176# CONFIG_SBC8548 is not set 184# CONFIG_SBC8548 is not set
@@ -202,7 +210,7 @@ CONFIG_HZ_250=y
202# CONFIG_HZ_300 is not set 210# CONFIG_HZ_300 is not set
203# CONFIG_HZ_1000 is not set 211# CONFIG_HZ_1000 is not set
204CONFIG_HZ=250 212CONFIG_HZ=250
205# CONFIG_SCHED_HRTICK is not set 213CONFIG_SCHED_HRTICK=y
206CONFIG_PREEMPT_NONE=y 214CONFIG_PREEMPT_NONE=y
207# CONFIG_PREEMPT_VOLUNTARY is not set 215# CONFIG_PREEMPT_VOLUNTARY is not set
208# CONFIG_PREEMPT is not set 216# CONFIG_PREEMPT is not set
@@ -225,6 +233,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
225# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set 233# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
226CONFIG_PAGEFLAGS_EXTENDED=y 234CONFIG_PAGEFLAGS_EXTENDED=y
227CONFIG_SPLIT_PTLOCK_CPUS=4 235CONFIG_SPLIT_PTLOCK_CPUS=4
236CONFIG_MIGRATION=y
228# CONFIG_RESOURCES_64BIT is not set 237# CONFIG_RESOURCES_64BIT is not set
229CONFIG_ZONE_DMA_FLAG=1 238CONFIG_ZONE_DMA_FLAG=1
230CONFIG_BOUNCE=y 239CONFIG_BOUNCE=y
@@ -232,6 +241,7 @@ CONFIG_VIRT_TO_BUS=y
232CONFIG_FORCE_MAX_ZONEORDER=11 241CONFIG_FORCE_MAX_ZONEORDER=11
233CONFIG_PROC_DEVICETREE=y 242CONFIG_PROC_DEVICETREE=y
234# CONFIG_CMDLINE_BOOL is not set 243# CONFIG_CMDLINE_BOOL is not set
244CONFIG_EXTRA_TARGETS=""
235# CONFIG_PM is not set 245# CONFIG_PM is not set
236CONFIG_SECCOMP=y 246CONFIG_SECCOMP=y
237CONFIG_ISA_DMA_API=y 247CONFIG_ISA_DMA_API=y
@@ -244,6 +254,7 @@ CONFIG_GENERIC_ISA_DMA=y
244CONFIG_PPC_INDIRECT_PCI=y 254CONFIG_PPC_INDIRECT_PCI=y
245CONFIG_FSL_SOC=y 255CONFIG_FSL_SOC=y
246CONFIG_FSL_PCI=y 256CONFIG_FSL_PCI=y
257CONFIG_PPC_PCI_CHOICE=y
247CONFIG_PCI=y 258CONFIG_PCI=y
248CONFIG_PCI_DOMAINS=y 259CONFIG_PCI_DOMAINS=y
249CONFIG_PCI_SYSCALL=y 260CONFIG_PCI_SYSCALL=y
@@ -270,10 +281,6 @@ CONFIG_KERNEL_START=0xc0000000
270CONFIG_PHYSICAL_START=0x00000000 281CONFIG_PHYSICAL_START=0x00000000
271CONFIG_PHYSICAL_ALIGN=0x10000000 282CONFIG_PHYSICAL_ALIGN=0x10000000
272CONFIG_TASK_SIZE=0xc0000000 283CONFIG_TASK_SIZE=0xc0000000
273
274#
275# Networking
276#
277CONFIG_NET=y 284CONFIG_NET=y
278 285
279# 286#
@@ -399,6 +406,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
399CONFIG_STANDALONE=y 406CONFIG_STANDALONE=y
400CONFIG_PREVENT_FIRMWARE_BUILD=y 407CONFIG_PREVENT_FIRMWARE_BUILD=y
401CONFIG_FW_LOADER=y 408CONFIG_FW_LOADER=y
409CONFIG_FIRMWARE_IN_KERNEL=y
410CONFIG_EXTRA_FIRMWARE=""
402# CONFIG_DEBUG_DRIVER is not set 411# CONFIG_DEBUG_DRIVER is not set
403# CONFIG_DEBUG_DEVRES is not set 412# CONFIG_DEBUG_DEVRES is not set
404# CONFIG_SYS_HYPERVISOR is not set 413# CONFIG_SYS_HYPERVISOR is not set
@@ -425,12 +434,14 @@ CONFIG_BLK_DEV_RAM_SIZE=131072
425# CONFIG_BLK_DEV_XIP is not set 434# CONFIG_BLK_DEV_XIP is not set
426# CONFIG_CDROM_PKTCDVD is not set 435# CONFIG_CDROM_PKTCDVD is not set
427# CONFIG_ATA_OVER_ETH is not set 436# CONFIG_ATA_OVER_ETH is not set
437# CONFIG_BLK_DEV_HD is not set
428CONFIG_MISC_DEVICES=y 438CONFIG_MISC_DEVICES=y
429# CONFIG_PHANTOM is not set 439# CONFIG_PHANTOM is not set
430# CONFIG_EEPROM_93CX6 is not set 440# CONFIG_EEPROM_93CX6 is not set
431# CONFIG_SGI_IOC4 is not set 441# CONFIG_SGI_IOC4 is not set
432# CONFIG_TIFM_CORE is not set 442# CONFIG_TIFM_CORE is not set
433# CONFIG_ENCLOSURE_SERVICES is not set 443# CONFIG_ENCLOSURE_SERVICES is not set
444# CONFIG_HP_ILO is not set
434CONFIG_HAVE_IDE=y 445CONFIG_HAVE_IDE=y
435# CONFIG_IDE is not set 446# CONFIG_IDE is not set
436 447
@@ -510,6 +521,7 @@ CONFIG_SCSI_LOWLEVEL=y
510# CONFIG_SCSI_NSP32 is not set 521# CONFIG_SCSI_NSP32 is not set
511# CONFIG_SCSI_DEBUG is not set 522# CONFIG_SCSI_DEBUG is not set
512# CONFIG_SCSI_SRP is not set 523# CONFIG_SCSI_SRP is not set
524# CONFIG_SCSI_DH is not set
513CONFIG_ATA=y 525CONFIG_ATA=y
514# CONFIG_ATA_NONSTANDARD is not set 526# CONFIG_ATA_NONSTANDARD is not set
515CONFIG_SATA_PMP=y 527CONFIG_SATA_PMP=y
@@ -577,12 +589,15 @@ CONFIG_PATA_ALI=y
577# 589#
578# IEEE 1394 (FireWire) support 590# IEEE 1394 (FireWire) support
579# 591#
592
593#
594# Enable only one of the two stacks, unless you know what you are doing
595#
580# CONFIG_FIREWIRE is not set 596# CONFIG_FIREWIRE is not set
581# CONFIG_IEEE1394 is not set 597# CONFIG_IEEE1394 is not set
582# CONFIG_I2O is not set 598# CONFIG_I2O is not set
583# CONFIG_MACINTOSH_DRIVERS is not set 599# CONFIG_MACINTOSH_DRIVERS is not set
584CONFIG_NETDEVICES=y 600CONFIG_NETDEVICES=y
585# CONFIG_NETDEVICES_MULTIQUEUE is not set
586CONFIG_DUMMY=y 601CONFIG_DUMMY=y
587# CONFIG_BONDING is not set 602# CONFIG_BONDING is not set
588# CONFIG_MACVLAN is not set 603# CONFIG_MACVLAN is not set
@@ -626,7 +641,6 @@ CONFIG_NETDEV_1000=y
626# CONFIG_DL2K is not set 641# CONFIG_DL2K is not set
627# CONFIG_E1000 is not set 642# CONFIG_E1000 is not set
628# CONFIG_E1000E is not set 643# CONFIG_E1000E is not set
629# CONFIG_E1000E_ENABLED is not set
630# CONFIG_IP1000 is not set 644# CONFIG_IP1000 is not set
631# CONFIG_IGB is not set 645# CONFIG_IGB is not set
632# CONFIG_NS83820 is not set 646# CONFIG_NS83820 is not set
@@ -640,9 +654,9 @@ CONFIG_NETDEV_1000=y
640# CONFIG_TIGON3 is not set 654# CONFIG_TIGON3 is not set
641# CONFIG_BNX2 is not set 655# CONFIG_BNX2 is not set
642CONFIG_GIANFAR=y 656CONFIG_GIANFAR=y
643CONFIG_GFAR_NAPI=y
644# CONFIG_QLA3XXX is not set 657# CONFIG_QLA3XXX is not set
645# CONFIG_ATL1 is not set 658# CONFIG_ATL1 is not set
659# CONFIG_ATL1E is not set
646CONFIG_NETDEV_10000=y 660CONFIG_NETDEV_10000=y
647# CONFIG_CHELSIO_T1 is not set 661# CONFIG_CHELSIO_T1 is not set
648# CONFIG_CHELSIO_T3 is not set 662# CONFIG_CHELSIO_T3 is not set
@@ -719,12 +733,14 @@ CONFIG_SERIO_SERPORT=y
719# CONFIG_SERIO_PCIPS2 is not set 733# CONFIG_SERIO_PCIPS2 is not set
720CONFIG_SERIO_LIBPS2=y 734CONFIG_SERIO_LIBPS2=y
721# CONFIG_SERIO_RAW is not set 735# CONFIG_SERIO_RAW is not set
736# CONFIG_SERIO_XILINX_XPS_PS2 is not set
722# CONFIG_GAMEPORT is not set 737# CONFIG_GAMEPORT is not set
723 738
724# 739#
725# Character devices 740# Character devices
726# 741#
727CONFIG_VT=y 742CONFIG_VT=y
743CONFIG_CONSOLE_TRANSLATIONS=y
728CONFIG_VT_CONSOLE=y 744CONFIG_VT_CONSOLE=y
729CONFIG_HW_CONSOLE=y 745CONFIG_HW_CONSOLE=y
730# CONFIG_VT_HW_CONSOLE_BINDING is not set 746# CONFIG_VT_HW_CONSOLE_BINDING is not set
@@ -758,7 +774,7 @@ CONFIG_UNIX98_PTYS=y
758CONFIG_LEGACY_PTYS=y 774CONFIG_LEGACY_PTYS=y
759CONFIG_LEGACY_PTY_COUNT=256 775CONFIG_LEGACY_PTY_COUNT=256
760# CONFIG_IPMI_HANDLER is not set 776# CONFIG_IPMI_HANDLER is not set
761# CONFIG_HW_RANDOM is not set 777CONFIG_HW_RANDOM=y
762CONFIG_NVRAM=y 778CONFIG_NVRAM=y
763# CONFIG_R3964 is not set 779# CONFIG_R3964 is not set
764# CONFIG_APPLICOM is not set 780# CONFIG_APPLICOM is not set
@@ -768,43 +784,64 @@ CONFIG_DEVPORT=y
768CONFIG_I2C=y 784CONFIG_I2C=y
769CONFIG_I2C_BOARDINFO=y 785CONFIG_I2C_BOARDINFO=y
770# CONFIG_I2C_CHARDEV is not set 786# CONFIG_I2C_CHARDEV is not set
787CONFIG_I2C_HELPER_AUTO=y
771 788
772# 789#
773# I2C Hardware Bus support 790# I2C Hardware Bus support
774# 791#
792
793#
794# PC SMBus host controller drivers
795#
775# CONFIG_I2C_ALI1535 is not set 796# CONFIG_I2C_ALI1535 is not set
776# CONFIG_I2C_ALI1563 is not set 797# CONFIG_I2C_ALI1563 is not set
777# CONFIG_I2C_ALI15X3 is not set 798# CONFIG_I2C_ALI15X3 is not set
778# CONFIG_I2C_AMD756 is not set 799# CONFIG_I2C_AMD756 is not set
779# CONFIG_I2C_AMD8111 is not set 800# CONFIG_I2C_AMD8111 is not set
780# CONFIG_I2C_I801 is not set 801# CONFIG_I2C_I801 is not set
781# CONFIG_I2C_I810 is not set 802# CONFIG_I2C_ISCH is not set
782# CONFIG_I2C_PIIX4 is not set 803# CONFIG_I2C_PIIX4 is not set
783CONFIG_I2C_MPC=y
784# CONFIG_I2C_NFORCE2 is not set 804# CONFIG_I2C_NFORCE2 is not set
785# CONFIG_I2C_OCORES is not set
786# CONFIG_I2C_PARPORT_LIGHT is not set
787# CONFIG_I2C_PROSAVAGE is not set
788# CONFIG_I2C_SAVAGE4 is not set
789# CONFIG_I2C_SIMTEC is not set
790# CONFIG_I2C_SIS5595 is not set 805# CONFIG_I2C_SIS5595 is not set
791# CONFIG_I2C_SIS630 is not set 806# CONFIG_I2C_SIS630 is not set
792# CONFIG_I2C_SIS96X is not set 807# CONFIG_I2C_SIS96X is not set
793# CONFIG_I2C_TAOS_EVM is not set
794# CONFIG_I2C_STUB is not set
795# CONFIG_I2C_TINY_USB is not set
796# CONFIG_I2C_VIA is not set 808# CONFIG_I2C_VIA is not set
797# CONFIG_I2C_VIAPRO is not set 809# CONFIG_I2C_VIAPRO is not set
810
811#
812# I2C system bus drivers (mostly embedded / system-on-chip)
813#
814CONFIG_I2C_MPC=y
815# CONFIG_I2C_OCORES is not set
816# CONFIG_I2C_SIMTEC is not set
817
818#
819# External I2C/SMBus adapter drivers
820#
821# CONFIG_I2C_PARPORT_LIGHT is not set
822# CONFIG_I2C_TAOS_EVM is not set
823# CONFIG_I2C_TINY_USB is not set
824
825#
826# Graphics adapter I2C/DDC channel drivers
827#
798# CONFIG_I2C_VOODOO3 is not set 828# CONFIG_I2C_VOODOO3 is not set
829
830#
831# Other I2C/SMBus bus drivers
832#
799# CONFIG_I2C_PCA_PLATFORM is not set 833# CONFIG_I2C_PCA_PLATFORM is not set
834# CONFIG_I2C_STUB is not set
800 835
801# 836#
802# Miscellaneous I2C Chip support 837# Miscellaneous I2C Chip support
803# 838#
804# CONFIG_DS1682 is not set 839# CONFIG_DS1682 is not set
840# CONFIG_AT24 is not set
805CONFIG_SENSORS_EEPROM=y 841CONFIG_SENSORS_EEPROM=y
806# CONFIG_SENSORS_PCF8574 is not set 842# CONFIG_SENSORS_PCF8574 is not set
807# CONFIG_PCF8575 is not set 843# CONFIG_PCF8575 is not set
844# CONFIG_SENSORS_PCA9539 is not set
808# CONFIG_SENSORS_PCF8591 is not set 845# CONFIG_SENSORS_PCF8591 is not set
809# CONFIG_SENSORS_MAX6875 is not set 846# CONFIG_SENSORS_MAX6875 is not set
810# CONFIG_SENSORS_TSL2550 is not set 847# CONFIG_SENSORS_TSL2550 is not set
@@ -813,10 +850,13 @@ CONFIG_SENSORS_EEPROM=y
813# CONFIG_I2C_DEBUG_BUS is not set 850# CONFIG_I2C_DEBUG_BUS is not set
814# CONFIG_I2C_DEBUG_CHIP is not set 851# CONFIG_I2C_DEBUG_CHIP is not set
815# CONFIG_SPI is not set 852# CONFIG_SPI is not set
853CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
854# CONFIG_GPIOLIB is not set
816# CONFIG_W1 is not set 855# CONFIG_W1 is not set
817# CONFIG_POWER_SUPPLY is not set 856# CONFIG_POWER_SUPPLY is not set
818# CONFIG_HWMON is not set 857# CONFIG_HWMON is not set
819# CONFIG_THERMAL is not set 858# CONFIG_THERMAL is not set
859# CONFIG_THERMAL_HWMON is not set
820# CONFIG_WATCHDOG is not set 860# CONFIG_WATCHDOG is not set
821 861
822# 862#
@@ -828,8 +868,10 @@ CONFIG_SSB_POSSIBLE=y
828# 868#
829# Multifunction device drivers 869# Multifunction device drivers
830# 870#
871# CONFIG_MFD_CORE is not set
831# CONFIG_MFD_SM501 is not set 872# CONFIG_MFD_SM501 is not set
832# CONFIG_HTC_PASIC3 is not set 873# CONFIG_HTC_PASIC3 is not set
874# CONFIG_MFD_TMIO is not set
833 875
834# 876#
835# Multimedia devices 877# Multimedia devices
@@ -871,6 +913,7 @@ CONFIG_DVB_CAPTURE_DRIVERS=y
871# CONFIG_DVB_TTUSB_BUDGET is not set 913# CONFIG_DVB_TTUSB_BUDGET is not set
872# CONFIG_DVB_TTUSB_DEC is not set 914# CONFIG_DVB_TTUSB_DEC is not set
873# CONFIG_DVB_CINERGYT2 is not set 915# CONFIG_DVB_CINERGYT2 is not set
916# CONFIG_DVB_SIANO_SMS1XXX is not set
874 917
875# 918#
876# Supported FlexCopII (B2C2) Adapters 919# Supported FlexCopII (B2C2) Adapters
@@ -917,6 +960,7 @@ CONFIG_DVB_CAPTURE_DRIVERS=y
917# CONFIG_DVB_SP887X is not set 960# CONFIG_DVB_SP887X is not set
918# CONFIG_DVB_CX22700 is not set 961# CONFIG_DVB_CX22700 is not set
919# CONFIG_DVB_CX22702 is not set 962# CONFIG_DVB_CX22702 is not set
963# CONFIG_DVB_DRX397XD is not set
920# CONFIG_DVB_L64781 is not set 964# CONFIG_DVB_L64781 is not set
921# CONFIG_DVB_TDA1004X is not set 965# CONFIG_DVB_TDA1004X is not set
922# CONFIG_DVB_NXT6000 is not set 966# CONFIG_DVB_NXT6000 is not set
@@ -984,15 +1028,7 @@ CONFIG_VIDEO_OUTPUT_CONTROL=y
984CONFIG_VGA_CONSOLE=y 1028CONFIG_VGA_CONSOLE=y
985# CONFIG_VGACON_SOFT_SCROLLBACK is not set 1029# CONFIG_VGACON_SOFT_SCROLLBACK is not set
986CONFIG_DUMMY_CONSOLE=y 1030CONFIG_DUMMY_CONSOLE=y
987
988#
989# Sound
990#
991CONFIG_SOUND=y 1031CONFIG_SOUND=y
992
993#
994# Advanced Linux Sound Architecture
995#
996CONFIG_SND=y 1032CONFIG_SND=y
997CONFIG_SND_TIMER=y 1033CONFIG_SND_TIMER=y
998CONFIG_SND_PCM=y 1034CONFIG_SND_PCM=y
@@ -1006,19 +1042,15 @@ CONFIG_SND_PCM_OSS_PLUGINS=y
1006CONFIG_SND_VERBOSE_PROCFS=y 1042CONFIG_SND_VERBOSE_PROCFS=y
1007# CONFIG_SND_VERBOSE_PRINTK is not set 1043# CONFIG_SND_VERBOSE_PRINTK is not set
1008# CONFIG_SND_DEBUG is not set 1044# CONFIG_SND_DEBUG is not set
1009 1045CONFIG_SND_VMASTER=y
1010#
1011# Generic devices
1012#
1013CONFIG_SND_AC97_CODEC=y 1046CONFIG_SND_AC97_CODEC=y
1047CONFIG_SND_DRIVERS=y
1014# CONFIG_SND_DUMMY is not set 1048# CONFIG_SND_DUMMY is not set
1015# CONFIG_SND_MTPAV is not set 1049# CONFIG_SND_MTPAV is not set
1016# CONFIG_SND_SERIAL_U16550 is not set 1050# CONFIG_SND_SERIAL_U16550 is not set
1017# CONFIG_SND_MPU401 is not set 1051# CONFIG_SND_MPU401 is not set
1018 1052# CONFIG_SND_AC97_POWER_SAVE is not set
1019# 1053CONFIG_SND_PCI=y
1020# PCI devices
1021#
1022# CONFIG_SND_AD1889 is not set 1054# CONFIG_SND_AD1889 is not set
1023# CONFIG_SND_ALS300 is not set 1055# CONFIG_SND_ALS300 is not set
1024# CONFIG_SND_ALS4000 is not set 1056# CONFIG_SND_ALS4000 is not set
@@ -1080,39 +1112,12 @@ CONFIG_SND_INTEL8X0=y
1080# CONFIG_SND_VIRTUOSO is not set 1112# CONFIG_SND_VIRTUOSO is not set
1081# CONFIG_SND_VX222 is not set 1113# CONFIG_SND_VX222 is not set
1082# CONFIG_SND_YMFPCI is not set 1114# CONFIG_SND_YMFPCI is not set
1083# CONFIG_SND_AC97_POWER_SAVE is not set 1115CONFIG_SND_PPC=y
1084 1116CONFIG_SND_USB=y
1085#
1086# ALSA PowerMac devices
1087#
1088
1089#
1090# ALSA PowerPC devices
1091#
1092
1093#
1094# USB devices
1095#
1096# CONFIG_SND_USB_AUDIO is not set 1117# CONFIG_SND_USB_AUDIO is not set
1097# CONFIG_SND_USB_USX2Y is not set 1118# CONFIG_SND_USB_USX2Y is not set
1098# CONFIG_SND_USB_CAIAQ is not set 1119# CONFIG_SND_USB_CAIAQ is not set
1099
1100#
1101# System on Chip audio support
1102#
1103# CONFIG_SND_SOC is not set 1120# CONFIG_SND_SOC is not set
1104
1105#
1106# ALSA SoC audio for Freescale SOCs
1107#
1108
1109#
1110# SoC Audio for the Texas Instruments OMAP
1111#
1112
1113#
1114# Open Sound System
1115#
1116# CONFIG_SOUND_PRIME is not set 1121# CONFIG_SOUND_PRIME is not set
1117CONFIG_AC97_BUS=y 1122CONFIG_AC97_BUS=y
1118CONFIG_HID_SUPPORT=y 1123CONFIG_HID_SUPPORT=y
@@ -1144,6 +1149,7 @@ CONFIG_USB_DEVICE_CLASS=y
1144# CONFIG_USB_OTG is not set 1149# CONFIG_USB_OTG is not set
1145# CONFIG_USB_OTG_WHITELIST is not set 1150# CONFIG_USB_OTG_WHITELIST is not set
1146# CONFIG_USB_OTG_BLACKLIST_HUB is not set 1151# CONFIG_USB_OTG_BLACKLIST_HUB is not set
1152CONFIG_USB_MON=y
1147 1153
1148# 1154#
1149# USB Host Controller Drivers 1155# USB Host Controller Drivers
@@ -1195,6 +1201,7 @@ CONFIG_USB_STORAGE=y
1195# CONFIG_USB_STORAGE_ALAUDA is not set 1201# CONFIG_USB_STORAGE_ALAUDA is not set
1196# CONFIG_USB_STORAGE_ONETOUCH is not set 1202# CONFIG_USB_STORAGE_ONETOUCH is not set
1197# CONFIG_USB_STORAGE_KARMA is not set 1203# CONFIG_USB_STORAGE_KARMA is not set
1204# CONFIG_USB_STORAGE_SIERRA is not set
1198# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set 1205# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
1199# CONFIG_USB_LIBUSUAL is not set 1206# CONFIG_USB_LIBUSUAL is not set
1200 1207
@@ -1203,7 +1210,6 @@ CONFIG_USB_STORAGE=y
1203# 1210#
1204# CONFIG_USB_MDC800 is not set 1211# CONFIG_USB_MDC800 is not set
1205# CONFIG_USB_MICROTEK is not set 1212# CONFIG_USB_MICROTEK is not set
1206CONFIG_USB_MON=y
1207 1213
1208# 1214#
1209# USB port drivers 1215# USB port drivers
@@ -1216,7 +1222,6 @@ CONFIG_USB_MON=y
1216# CONFIG_USB_EMI62 is not set 1222# CONFIG_USB_EMI62 is not set
1217# CONFIG_USB_EMI26 is not set 1223# CONFIG_USB_EMI26 is not set
1218# CONFIG_USB_ADUTUX is not set 1224# CONFIG_USB_ADUTUX is not set
1219# CONFIG_USB_AUERSWALD is not set
1220# CONFIG_USB_RIO500 is not set 1225# CONFIG_USB_RIO500 is not set
1221# CONFIG_USB_LEGOTOWER is not set 1226# CONFIG_USB_LEGOTOWER is not set
1222# CONFIG_USB_LCD is not set 1227# CONFIG_USB_LCD is not set
@@ -1270,6 +1275,7 @@ CONFIG_RTC_INTF_DEV=y
1270# CONFIG_RTC_DRV_PCF8583 is not set 1275# CONFIG_RTC_DRV_PCF8583 is not set
1271# CONFIG_RTC_DRV_M41T80 is not set 1276# CONFIG_RTC_DRV_M41T80 is not set
1272# CONFIG_RTC_DRV_S35390A is not set 1277# CONFIG_RTC_DRV_S35390A is not set
1278# CONFIG_RTC_DRV_FM3130 is not set
1273 1279
1274# 1280#
1275# SPI RTC drivers 1281# SPI RTC drivers
@@ -1303,6 +1309,7 @@ CONFIG_DMA_ENGINE=y
1303# DMA Clients 1309# DMA Clients
1304# 1310#
1305# CONFIG_NET_DMA is not set 1311# CONFIG_NET_DMA is not set
1312# CONFIG_DMATEST is not set
1306# CONFIG_UIO is not set 1313# CONFIG_UIO is not set
1307 1314
1308# 1315#
@@ -1379,6 +1386,7 @@ CONFIG_EFS_FS=m
1379CONFIG_CRAMFS=y 1386CONFIG_CRAMFS=y
1380CONFIG_VXFS_FS=m 1387CONFIG_VXFS_FS=m
1381# CONFIG_MINIX_FS is not set 1388# CONFIG_MINIX_FS is not set
1389# CONFIG_OMFS_FS is not set
1382CONFIG_HPFS_FS=m 1390CONFIG_HPFS_FS=m
1383CONFIG_QNX4FS_FS=m 1391CONFIG_QNX4FS_FS=m
1384# CONFIG_ROMFS_FS is not set 1392# CONFIG_ROMFS_FS is not set
@@ -1391,17 +1399,16 @@ CONFIG_NFS_FS=y
1391CONFIG_NFS_V3=y 1399CONFIG_NFS_V3=y
1392# CONFIG_NFS_V3_ACL is not set 1400# CONFIG_NFS_V3_ACL is not set
1393CONFIG_NFS_V4=y 1401CONFIG_NFS_V4=y
1402CONFIG_ROOT_NFS=y
1394CONFIG_NFSD=y 1403CONFIG_NFSD=y
1395# CONFIG_NFSD_V3 is not set 1404# CONFIG_NFSD_V3 is not set
1396# CONFIG_NFSD_V4 is not set 1405# CONFIG_NFSD_V4 is not set
1397CONFIG_ROOT_NFS=y
1398CONFIG_LOCKD=y 1406CONFIG_LOCKD=y
1399CONFIG_LOCKD_V4=y 1407CONFIG_LOCKD_V4=y
1400CONFIG_EXPORTFS=y 1408CONFIG_EXPORTFS=y
1401CONFIG_NFS_COMMON=y 1409CONFIG_NFS_COMMON=y
1402CONFIG_SUNRPC=y 1410CONFIG_SUNRPC=y
1403CONFIG_SUNRPC_GSS=y 1411CONFIG_SUNRPC_GSS=y
1404# CONFIG_SUNRPC_BIND34 is not set
1405CONFIG_RPCSEC_GSS_KRB5=y 1412CONFIG_RPCSEC_GSS_KRB5=y
1406# CONFIG_RPCSEC_GSS_SPKM3 is not set 1413# CONFIG_RPCSEC_GSS_SPKM3 is not set
1407# CONFIG_SMB_FS is not set 1414# CONFIG_SMB_FS is not set
@@ -1480,6 +1487,7 @@ CONFIG_BITREVERSE=y
1480# CONFIG_GENERIC_FIND_FIRST_BIT is not set 1487# CONFIG_GENERIC_FIND_FIRST_BIT is not set
1481# CONFIG_CRC_CCITT is not set 1488# CONFIG_CRC_CCITT is not set
1482# CONFIG_CRC16 is not set 1489# CONFIG_CRC16 is not set
1490CONFIG_CRC_T10DIF=y
1483CONFIG_CRC_ITU_T=m 1491CONFIG_CRC_ITU_T=m
1484CONFIG_CRC32=y 1492CONFIG_CRC32=y
1485# CONFIG_CRC7 is not set 1493# CONFIG_CRC7 is not set
@@ -1505,6 +1513,8 @@ CONFIG_FRAME_WARN=1024
1505CONFIG_DEBUG_KERNEL=y 1513CONFIG_DEBUG_KERNEL=y
1506# CONFIG_DEBUG_SHIRQ is not set 1514# CONFIG_DEBUG_SHIRQ is not set
1507CONFIG_DETECT_SOFTLOCKUP=y 1515CONFIG_DETECT_SOFTLOCKUP=y
1516# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
1517CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
1508CONFIG_SCHED_DEBUG=y 1518CONFIG_SCHED_DEBUG=y
1509# CONFIG_SCHEDSTATS is not set 1519# CONFIG_SCHEDSTATS is not set
1510# CONFIG_TIMER_STATS is not set 1520# CONFIG_TIMER_STATS is not set
@@ -1523,17 +1533,29 @@ CONFIG_SCHED_DEBUG=y
1523CONFIG_DEBUG_INFO=y 1533CONFIG_DEBUG_INFO=y
1524# CONFIG_DEBUG_VM is not set 1534# CONFIG_DEBUG_VM is not set
1525# CONFIG_DEBUG_WRITECOUNT is not set 1535# CONFIG_DEBUG_WRITECOUNT is not set
1536# CONFIG_DEBUG_MEMORY_INIT is not set
1526# CONFIG_DEBUG_LIST is not set 1537# CONFIG_DEBUG_LIST is not set
1527# CONFIG_DEBUG_SG is not set 1538# CONFIG_DEBUG_SG is not set
1528# CONFIG_BOOT_PRINTK_DELAY is not set 1539# CONFIG_BOOT_PRINTK_DELAY is not set
1529# CONFIG_RCU_TORTURE_TEST is not set 1540# CONFIG_RCU_TORTURE_TEST is not set
1530# CONFIG_BACKTRACE_SELF_TEST is not set 1541# CONFIG_BACKTRACE_SELF_TEST is not set
1531# CONFIG_FAULT_INJECTION is not set 1542# CONFIG_FAULT_INJECTION is not set
1543# CONFIG_LATENCYTOP is not set
1544CONFIG_SYSCTL_SYSCALL_CHECK=y
1545CONFIG_HAVE_FTRACE=y
1546CONFIG_HAVE_DYNAMIC_FTRACE=y
1547# CONFIG_FTRACE is not set
1548# CONFIG_SCHED_TRACER is not set
1549# CONFIG_CONTEXT_SWITCH_TRACER is not set
1532# CONFIG_SAMPLES is not set 1550# CONFIG_SAMPLES is not set
1551CONFIG_HAVE_ARCH_KGDB=y
1552# CONFIG_KGDB is not set
1533# CONFIG_DEBUG_STACKOVERFLOW is not set 1553# CONFIG_DEBUG_STACKOVERFLOW is not set
1534# CONFIG_DEBUG_STACK_USAGE is not set 1554# CONFIG_DEBUG_STACK_USAGE is not set
1535# CONFIG_DEBUG_PAGEALLOC is not set 1555# CONFIG_DEBUG_PAGEALLOC is not set
1536# CONFIG_DEBUGGER is not set 1556# CONFIG_CODE_PATCHING_SELFTEST is not set
1557# CONFIG_FTR_FIXUP_SELFTEST is not set
1558# CONFIG_XMON is not set
1537# CONFIG_IRQSTACKS is not set 1559# CONFIG_IRQSTACKS is not set
1538# CONFIG_BDI_SWITCH is not set 1560# CONFIG_BDI_SWITCH is not set
1539# CONFIG_PPC_EARLY_DEBUG is not set 1561# CONFIG_PPC_EARLY_DEBUG is not set
@@ -1550,13 +1572,14 @@ CONFIG_CRYPTO=y
1550# Crypto core or helper 1572# Crypto core or helper
1551# 1573#
1552CONFIG_CRYPTO_ALGAPI=y 1574CONFIG_CRYPTO_ALGAPI=y
1575CONFIG_CRYPTO_AEAD=y
1553CONFIG_CRYPTO_BLKCIPHER=y 1576CONFIG_CRYPTO_BLKCIPHER=y
1554CONFIG_CRYPTO_HASH=y 1577CONFIG_CRYPTO_HASH=y
1555CONFIG_CRYPTO_MANAGER=y 1578CONFIG_CRYPTO_MANAGER=y
1556# CONFIG_CRYPTO_GF128MUL is not set 1579# CONFIG_CRYPTO_GF128MUL is not set
1557# CONFIG_CRYPTO_NULL is not set 1580# CONFIG_CRYPTO_NULL is not set
1558# CONFIG_CRYPTO_CRYPTD is not set 1581# CONFIG_CRYPTO_CRYPTD is not set
1559# CONFIG_CRYPTO_AUTHENC is not set 1582CONFIG_CRYPTO_AUTHENC=y
1560# CONFIG_CRYPTO_TEST is not set 1583# CONFIG_CRYPTO_TEST is not set
1561 1584
1562# 1585#
@@ -1590,6 +1613,10 @@ CONFIG_CRYPTO_HMAC=y
1590# CONFIG_CRYPTO_MD4 is not set 1613# CONFIG_CRYPTO_MD4 is not set
1591CONFIG_CRYPTO_MD5=y 1614CONFIG_CRYPTO_MD5=y
1592# CONFIG_CRYPTO_MICHAEL_MIC is not set 1615# CONFIG_CRYPTO_MICHAEL_MIC is not set
1616# CONFIG_CRYPTO_RMD128 is not set
1617# CONFIG_CRYPTO_RMD160 is not set
1618# CONFIG_CRYPTO_RMD256 is not set
1619# CONFIG_CRYPTO_RMD320 is not set
1593CONFIG_CRYPTO_SHA1=m 1620CONFIG_CRYPTO_SHA1=m
1594# CONFIG_CRYPTO_SHA256 is not set 1621# CONFIG_CRYPTO_SHA256 is not set
1595# CONFIG_CRYPTO_SHA512 is not set 1622# CONFIG_CRYPTO_SHA512 is not set
@@ -1622,5 +1649,6 @@ CONFIG_CRYPTO_DES=y
1622# CONFIG_CRYPTO_LZO is not set 1649# CONFIG_CRYPTO_LZO is not set
1623CONFIG_CRYPTO_HW=y 1650CONFIG_CRYPTO_HW=y
1624# CONFIG_CRYPTO_DEV_HIFN_795X is not set 1651# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1652CONFIG_CRYPTO_DEV_TALITOS=y
1625# CONFIG_PPC_CLOCK is not set 1653# CONFIG_PPC_CLOCK is not set
1626# CONFIG_VIRTUALIZATION is not set 1654# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/configs/85xx/mpc8560_ads_defconfig b/arch/powerpc/configs/85xx/mpc8560_ads_defconfig
index e19592b42043..06e26d906f65 100644
--- a/arch/powerpc/configs/85xx/mpc8560_ads_defconfig
+++ b/arch/powerpc/configs/85xx/mpc8560_ads_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc5 3# Linux kernel version: 2.6.27-rc4
4# Mon Jun 9 08:52:33 2008 4# Thu Aug 21 00:52:32 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -15,6 +15,7 @@ CONFIG_PPC_85xx=y
15# CONFIG_44x is not set 15# CONFIG_44x is not set
16# CONFIG_E200 is not set 16# CONFIG_E200 is not set
17CONFIG_E500=y 17CONFIG_E500=y
18# CONFIG_PPC_E500MC is not set
18CONFIG_BOOKE=y 19CONFIG_BOOKE=y
19CONFIG_FSL_BOOKE=y 20CONFIG_FSL_BOOKE=y
20CONFIG_FSL_EMB_PERFMON=y 21CONFIG_FSL_EMB_PERFMON=y
@@ -33,12 +34,14 @@ CONFIG_GENERIC_HARDIRQS=y
33# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set 34# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
34CONFIG_IRQ_PER_CPU=y 35CONFIG_IRQ_PER_CPU=y
35CONFIG_STACKTRACE_SUPPORT=y 36CONFIG_STACKTRACE_SUPPORT=y
37CONFIG_HAVE_LATENCYTOP_SUPPORT=y
36CONFIG_LOCKDEP_SUPPORT=y 38CONFIG_LOCKDEP_SUPPORT=y
37CONFIG_RWSEM_XCHGADD_ALGORITHM=y 39CONFIG_RWSEM_XCHGADD_ALGORITHM=y
38CONFIG_ARCH_HAS_ILOG2_U32=y 40CONFIG_ARCH_HAS_ILOG2_U32=y
39CONFIG_GENERIC_HWEIGHT=y 41CONFIG_GENERIC_HWEIGHT=y
40CONFIG_GENERIC_CALIBRATE_DELAY=y 42CONFIG_GENERIC_CALIBRATE_DELAY=y
41CONFIG_GENERIC_FIND_NEXT_BIT=y 43CONFIG_GENERIC_FIND_NEXT_BIT=y
44CONFIG_GENERIC_GPIO=y
42# CONFIG_ARCH_NO_VIRT_TO_BUS is not set 45# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
43CONFIG_PPC=y 46CONFIG_PPC=y
44CONFIG_EARLY_PRINTK=y 47CONFIG_EARLY_PRINTK=y
@@ -89,7 +92,6 @@ CONFIG_INITRAMFS_SOURCE=""
89CONFIG_SYSCTL=y 92CONFIG_SYSCTL=y
90CONFIG_EMBEDDED=y 93CONFIG_EMBEDDED=y
91CONFIG_SYSCTL_SYSCALL=y 94CONFIG_SYSCTL_SYSCALL=y
92CONFIG_SYSCTL_SYSCALL_CHECK=y
93CONFIG_KALLSYMS=y 95CONFIG_KALLSYMS=y
94# CONFIG_KALLSYMS_ALL is not set 96# CONFIG_KALLSYMS_ALL is not set
95# CONFIG_KALLSYMS_EXTRA_PASS is not set 97# CONFIG_KALLSYMS_EXTRA_PASS is not set
@@ -114,10 +116,16 @@ CONFIG_SLUB=y
114# CONFIG_PROFILING is not set 116# CONFIG_PROFILING is not set
115# CONFIG_MARKERS is not set 117# CONFIG_MARKERS is not set
116CONFIG_HAVE_OPROFILE=y 118CONFIG_HAVE_OPROFILE=y
119CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
120CONFIG_HAVE_IOREMAP_PROT=y
117CONFIG_HAVE_KPROBES=y 121CONFIG_HAVE_KPROBES=y
118CONFIG_HAVE_KRETPROBES=y 122CONFIG_HAVE_KRETPROBES=y
123CONFIG_HAVE_ARCH_TRACEHOOK=y
119# CONFIG_HAVE_DMA_ATTRS is not set 124# CONFIG_HAVE_DMA_ATTRS is not set
125# CONFIG_USE_GENERIC_SMP_HELPERS is not set
126CONFIG_HAVE_CLK=y
120CONFIG_PROC_PAGE_MONITOR=y 127CONFIG_PROC_PAGE_MONITOR=y
128# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
121CONFIG_SLABINFO=y 129CONFIG_SLABINFO=y
122CONFIG_RT_MUTEXES=y 130CONFIG_RT_MUTEXES=y
123# CONFIG_TINY_SHMEM is not set 131# CONFIG_TINY_SHMEM is not set
@@ -128,6 +136,7 @@ CONFIG_BLOCK=y
128# CONFIG_BLK_DEV_IO_TRACE is not set 136# CONFIG_BLK_DEV_IO_TRACE is not set
129# CONFIG_LSF is not set 137# CONFIG_LSF is not set
130# CONFIG_BLK_DEV_BSG is not set 138# CONFIG_BLK_DEV_BSG is not set
139# CONFIG_BLK_DEV_INTEGRITY is not set
131 140
132# 141#
133# IO Schedulers 142# IO Schedulers
@@ -146,8 +155,6 @@ CONFIG_CLASSIC_RCU=y
146# 155#
147# Platform support 156# Platform support
148# 157#
149# CONFIG_PPC_MPC512x is not set
150# CONFIG_PPC_MPC5121 is not set
151# CONFIG_PPC_CELL is not set 158# CONFIG_PPC_CELL is not set
152# CONFIG_PPC_CELL_NATIVE is not set 159# CONFIG_PPC_CELL_NATIVE is not set
153# CONFIG_PQ2ADS is not set 160# CONFIG_PQ2ADS is not set
@@ -156,11 +163,13 @@ CONFIG_MPC85xx=y
156CONFIG_MPC8560_ADS=y 163CONFIG_MPC8560_ADS=y
157# CONFIG_MPC85xx_CDS is not set 164# CONFIG_MPC85xx_CDS is not set
158# CONFIG_MPC85xx_MDS is not set 165# CONFIG_MPC85xx_MDS is not set
166# CONFIG_MPC8536_DS is not set
159# CONFIG_MPC85xx_DS is not set 167# CONFIG_MPC85xx_DS is not set
160# CONFIG_KSI8560 is not set 168# CONFIG_KSI8560 is not set
161# CONFIG_STX_GP3 is not set 169# CONFIG_STX_GP3 is not set
162# CONFIG_TQM8540 is not set 170# CONFIG_TQM8540 is not set
163# CONFIG_TQM8541 is not set 171# CONFIG_TQM8541 is not set
172# CONFIG_TQM8548 is not set
164# CONFIG_TQM8555 is not set 173# CONFIG_TQM8555 is not set
165# CONFIG_TQM8560 is not set 174# CONFIG_TQM8560 is not set
166# CONFIG_SBC8548 is not set 175# CONFIG_SBC8548 is not set
@@ -177,7 +186,6 @@ CONFIG_MPIC=y
177# CONFIG_GENERIC_IOMAP is not set 186# CONFIG_GENERIC_IOMAP is not set
178# CONFIG_CPU_FREQ is not set 187# CONFIG_CPU_FREQ is not set
179CONFIG_CPM2=y 188CONFIG_CPM2=y
180CONFIG_PPC_CPM_NEW_BINDING=y
181# CONFIG_FSL_ULI1575 is not set 189# CONFIG_FSL_ULI1575 is not set
182CONFIG_CPM=y 190CONFIG_CPM=y
183 191
@@ -217,6 +225,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
217# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set 225# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
218CONFIG_PAGEFLAGS_EXTENDED=y 226CONFIG_PAGEFLAGS_EXTENDED=y
219CONFIG_SPLIT_PTLOCK_CPUS=4 227CONFIG_SPLIT_PTLOCK_CPUS=4
228CONFIG_MIGRATION=y
220# CONFIG_RESOURCES_64BIT is not set 229# CONFIG_RESOURCES_64BIT is not set
221CONFIG_ZONE_DMA_FLAG=1 230CONFIG_ZONE_DMA_FLAG=1
222CONFIG_BOUNCE=y 231CONFIG_BOUNCE=y
@@ -224,6 +233,7 @@ CONFIG_VIRT_TO_BUS=y
224CONFIG_FORCE_MAX_ZONEORDER=11 233CONFIG_FORCE_MAX_ZONEORDER=11
225# CONFIG_PROC_DEVICETREE is not set 234# CONFIG_PROC_DEVICETREE is not set
226# CONFIG_CMDLINE_BOOL is not set 235# CONFIG_CMDLINE_BOOL is not set
236CONFIG_EXTRA_TARGETS=""
227# CONFIG_PM is not set 237# CONFIG_PM is not set
228# CONFIG_SECCOMP is not set 238# CONFIG_SECCOMP is not set
229CONFIG_ISA_DMA_API=y 239CONFIG_ISA_DMA_API=y
@@ -235,6 +245,7 @@ CONFIG_ZONE_DMA=y
235CONFIG_PPC_INDIRECT_PCI=y 245CONFIG_PPC_INDIRECT_PCI=y
236CONFIG_FSL_SOC=y 246CONFIG_FSL_SOC=y
237CONFIG_FSL_PCI=y 247CONFIG_FSL_PCI=y
248CONFIG_PPC_PCI_CHOICE=y
238CONFIG_PCI=y 249CONFIG_PCI=y
239CONFIG_PCI_DOMAINS=y 250CONFIG_PCI_DOMAINS=y
240CONFIG_PCI_SYSCALL=y 251CONFIG_PCI_SYSCALL=y
@@ -261,10 +272,6 @@ CONFIG_KERNEL_START=0xc0000000
261CONFIG_PHYSICAL_START=0x00000000 272CONFIG_PHYSICAL_START=0x00000000
262CONFIG_PHYSICAL_ALIGN=0x10000000 273CONFIG_PHYSICAL_ALIGN=0x10000000
263CONFIG_TASK_SIZE=0xc0000000 274CONFIG_TASK_SIZE=0xc0000000
264
265#
266# Networking
267#
268CONFIG_NET=y 275CONFIG_NET=y
269 276
270# 277#
@@ -363,6 +370,7 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
363# CONFIG_CONNECTOR is not set 370# CONFIG_CONNECTOR is not set
364# CONFIG_MTD is not set 371# CONFIG_MTD is not set
365CONFIG_OF_DEVICE=y 372CONFIG_OF_DEVICE=y
373CONFIG_OF_GPIO=y
366# CONFIG_PARPORT is not set 374# CONFIG_PARPORT is not set
367CONFIG_BLK_DEV=y 375CONFIG_BLK_DEV=y
368# CONFIG_BLK_DEV_FD is not set 376# CONFIG_BLK_DEV_FD is not set
@@ -381,12 +389,14 @@ CONFIG_BLK_DEV_RAM_SIZE=32768
381# CONFIG_BLK_DEV_XIP is not set 389# CONFIG_BLK_DEV_XIP is not set
382# CONFIG_CDROM_PKTCDVD is not set 390# CONFIG_CDROM_PKTCDVD is not set
383# CONFIG_ATA_OVER_ETH is not set 391# CONFIG_ATA_OVER_ETH is not set
392# CONFIG_BLK_DEV_HD is not set
384CONFIG_MISC_DEVICES=y 393CONFIG_MISC_DEVICES=y
385# CONFIG_PHANTOM is not set 394# CONFIG_PHANTOM is not set
386# CONFIG_EEPROM_93CX6 is not set 395# CONFIG_EEPROM_93CX6 is not set
387# CONFIG_SGI_IOC4 is not set 396# CONFIG_SGI_IOC4 is not set
388# CONFIG_TIFM_CORE is not set 397# CONFIG_TIFM_CORE is not set
389# CONFIG_ENCLOSURE_SERVICES is not set 398# CONFIG_ENCLOSURE_SERVICES is not set
399# CONFIG_HP_ILO is not set
390CONFIG_HAVE_IDE=y 400CONFIG_HAVE_IDE=y
391# CONFIG_IDE is not set 401# CONFIG_IDE is not set
392 402
@@ -404,12 +414,15 @@ CONFIG_HAVE_IDE=y
404# 414#
405# IEEE 1394 (FireWire) support 415# IEEE 1394 (FireWire) support
406# 416#
417
418#
419# Enable only one of the two stacks, unless you know what you are doing
420#
407# CONFIG_FIREWIRE is not set 421# CONFIG_FIREWIRE is not set
408# CONFIG_IEEE1394 is not set 422# CONFIG_IEEE1394 is not set
409# CONFIG_I2O is not set 423# CONFIG_I2O is not set
410# CONFIG_MACINTOSH_DRIVERS is not set 424# CONFIG_MACINTOSH_DRIVERS is not set
411CONFIG_NETDEVICES=y 425CONFIG_NETDEVICES=y
412# CONFIG_NETDEVICES_MULTIQUEUE is not set
413# CONFIG_DUMMY is not set 426# CONFIG_DUMMY is not set
414# CONFIG_BONDING is not set 427# CONFIG_BONDING is not set
415# CONFIG_MACVLAN is not set 428# CONFIG_MACVLAN is not set
@@ -456,10 +469,8 @@ CONFIG_NETDEV_1000=y
456# CONFIG_ACENIC is not set 469# CONFIG_ACENIC is not set
457# CONFIG_DL2K is not set 470# CONFIG_DL2K is not set
458CONFIG_E1000=y 471CONFIG_E1000=y
459CONFIG_E1000_NAPI=y
460# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set 472# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
461# CONFIG_E1000E is not set 473# CONFIG_E1000E is not set
462# CONFIG_E1000E_ENABLED is not set
463# CONFIG_IP1000 is not set 474# CONFIG_IP1000 is not set
464# CONFIG_IGB is not set 475# CONFIG_IGB is not set
465# CONFIG_NS83820 is not set 476# CONFIG_NS83820 is not set
@@ -473,9 +484,9 @@ CONFIG_E1000_NAPI=y
473# CONFIG_TIGON3 is not set 484# CONFIG_TIGON3 is not set
474# CONFIG_BNX2 is not set 485# CONFIG_BNX2 is not set
475CONFIG_GIANFAR=y 486CONFIG_GIANFAR=y
476CONFIG_GFAR_NAPI=y
477# CONFIG_QLA3XXX is not set 487# CONFIG_QLA3XXX is not set
478# CONFIG_ATL1 is not set 488# CONFIG_ATL1 is not set
489# CONFIG_ATL1E is not set
479CONFIG_NETDEV_10000=y 490CONFIG_NETDEV_10000=y
480# CONFIG_CHELSIO_T1 is not set 491# CONFIG_CHELSIO_T1 is not set
481# CONFIG_CHELSIO_T3 is not set 492# CONFIG_CHELSIO_T3 is not set
@@ -582,6 +593,24 @@ CONFIG_GEN_RTC=y
582CONFIG_DEVPORT=y 593CONFIG_DEVPORT=y
583# CONFIG_I2C is not set 594# CONFIG_I2C is not set
584# CONFIG_SPI is not set 595# CONFIG_SPI is not set
596CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
597CONFIG_ARCH_REQUIRE_GPIOLIB=y
598CONFIG_GPIOLIB=y
599# CONFIG_DEBUG_GPIO is not set
600# CONFIG_GPIO_SYSFS is not set
601
602#
603# I2C GPIO expanders:
604#
605
606#
607# PCI GPIO expanders:
608#
609# CONFIG_GPIO_BT8XX is not set
610
611#
612# SPI GPIO expanders:
613#
585# CONFIG_W1 is not set 614# CONFIG_W1 is not set
586# CONFIG_POWER_SUPPLY is not set 615# CONFIG_POWER_SUPPLY is not set
587CONFIG_HWMON=y 616CONFIG_HWMON=y
@@ -602,6 +631,7 @@ CONFIG_HWMON=y
602# CONFIG_SENSORS_W83627EHF is not set 631# CONFIG_SENSORS_W83627EHF is not set
603# CONFIG_HWMON_DEBUG_CHIP is not set 632# CONFIG_HWMON_DEBUG_CHIP is not set
604# CONFIG_THERMAL is not set 633# CONFIG_THERMAL is not set
634# CONFIG_THERMAL_HWMON is not set
605# CONFIG_WATCHDOG is not set 635# CONFIG_WATCHDOG is not set
606 636
607# 637#
@@ -613,8 +643,10 @@ CONFIG_SSB_POSSIBLE=y
613# 643#
614# Multifunction device drivers 644# Multifunction device drivers
615# 645#
646# CONFIG_MFD_CORE is not set
616# CONFIG_MFD_SM501 is not set 647# CONFIG_MFD_SM501 is not set
617# CONFIG_HTC_PASIC3 is not set 648# CONFIG_HTC_PASIC3 is not set
649# CONFIG_MFD_TMIO is not set
618 650
619# 651#
620# Multimedia devices 652# Multimedia devices
@@ -646,10 +678,6 @@ CONFIG_VIDEO_OUTPUT_CONTROL=y
646# Display device support 678# Display device support
647# 679#
648# CONFIG_DISPLAY_SUPPORT is not set 680# CONFIG_DISPLAY_SUPPORT is not set
649
650#
651# Sound
652#
653# CONFIG_SOUND is not set 681# CONFIG_SOUND is not set
654CONFIG_HID_SUPPORT=y 682CONFIG_HID_SUPPORT=y
655CONFIG_HID=y 683CONFIG_HID=y
@@ -664,6 +692,10 @@ CONFIG_USB_ARCH_HAS_EHCI=y
664# CONFIG_USB_OTG_BLACKLIST_HUB is not set 692# CONFIG_USB_OTG_BLACKLIST_HUB is not set
665 693
666# 694#
695# Enable Host or Gadget support to see Inventra options
696#
697
698#
667# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 699# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
668# 700#
669# CONFIG_USB_GADGET is not set 701# CONFIG_USB_GADGET is not set
@@ -741,6 +773,7 @@ CONFIG_TMPFS=y
741# CONFIG_CRAMFS is not set 773# CONFIG_CRAMFS is not set
742# CONFIG_VXFS_FS is not set 774# CONFIG_VXFS_FS is not set
743# CONFIG_MINIX_FS is not set 775# CONFIG_MINIX_FS is not set
776# CONFIG_OMFS_FS is not set
744# CONFIG_HPFS_FS is not set 777# CONFIG_HPFS_FS is not set
745# CONFIG_QNX4FS_FS is not set 778# CONFIG_QNX4FS_FS is not set
746# CONFIG_ROMFS_FS is not set 779# CONFIG_ROMFS_FS is not set
@@ -750,12 +783,11 @@ CONFIG_NETWORK_FILESYSTEMS=y
750CONFIG_NFS_FS=y 783CONFIG_NFS_FS=y
751# CONFIG_NFS_V3 is not set 784# CONFIG_NFS_V3 is not set
752# CONFIG_NFS_V4 is not set 785# CONFIG_NFS_V4 is not set
753# CONFIG_NFSD is not set
754CONFIG_ROOT_NFS=y 786CONFIG_ROOT_NFS=y
787# CONFIG_NFSD is not set
755CONFIG_LOCKD=y 788CONFIG_LOCKD=y
756CONFIG_NFS_COMMON=y 789CONFIG_NFS_COMMON=y
757CONFIG_SUNRPC=y 790CONFIG_SUNRPC=y
758# CONFIG_SUNRPC_BIND34 is not set
759# CONFIG_RPCSEC_GSS_KRB5 is not set 791# CONFIG_RPCSEC_GSS_KRB5 is not set
760# CONFIG_RPCSEC_GSS_SPKM3 is not set 792# CONFIG_RPCSEC_GSS_SPKM3 is not set
761# CONFIG_SMB_FS is not set 793# CONFIG_SMB_FS is not set
@@ -791,6 +823,7 @@ CONFIG_BITREVERSE=y
791# CONFIG_GENERIC_FIND_FIRST_BIT is not set 823# CONFIG_GENERIC_FIND_FIRST_BIT is not set
792# CONFIG_CRC_CCITT is not set 824# CONFIG_CRC_CCITT is not set
793# CONFIG_CRC16 is not set 825# CONFIG_CRC16 is not set
826# CONFIG_CRC_T10DIF is not set
794# CONFIG_CRC_ITU_T is not set 827# CONFIG_CRC_ITU_T is not set
795CONFIG_CRC32=y 828CONFIG_CRC32=y
796# CONFIG_CRC7 is not set 829# CONFIG_CRC7 is not set
@@ -815,6 +848,8 @@ CONFIG_FRAME_WARN=1024
815CONFIG_DEBUG_KERNEL=y 848CONFIG_DEBUG_KERNEL=y
816# CONFIG_DEBUG_SHIRQ is not set 849# CONFIG_DEBUG_SHIRQ is not set
817CONFIG_DETECT_SOFTLOCKUP=y 850CONFIG_DETECT_SOFTLOCKUP=y
851# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
852CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
818CONFIG_SCHED_DEBUG=y 853CONFIG_SCHED_DEBUG=y
819# CONFIG_SCHEDSTATS is not set 854# CONFIG_SCHEDSTATS is not set
820# CONFIG_TIMER_STATS is not set 855# CONFIG_TIMER_STATS is not set
@@ -832,17 +867,29 @@ CONFIG_DEBUG_MUTEXES=y
832# CONFIG_DEBUG_INFO is not set 867# CONFIG_DEBUG_INFO is not set
833# CONFIG_DEBUG_VM is not set 868# CONFIG_DEBUG_VM is not set
834# CONFIG_DEBUG_WRITECOUNT is not set 869# CONFIG_DEBUG_WRITECOUNT is not set
870# CONFIG_DEBUG_MEMORY_INIT is not set
835# CONFIG_DEBUG_LIST is not set 871# CONFIG_DEBUG_LIST is not set
836# CONFIG_DEBUG_SG is not set 872# CONFIG_DEBUG_SG is not set
837# CONFIG_BOOT_PRINTK_DELAY is not set 873# CONFIG_BOOT_PRINTK_DELAY is not set
874# CONFIG_RCU_TORTURE_TEST is not set
838# CONFIG_BACKTRACE_SELF_TEST is not set 875# CONFIG_BACKTRACE_SELF_TEST is not set
839# CONFIG_FAULT_INJECTION is not set 876# CONFIG_FAULT_INJECTION is not set
877# CONFIG_LATENCYTOP is not set
878CONFIG_SYSCTL_SYSCALL_CHECK=y
879CONFIG_HAVE_FTRACE=y
880CONFIG_HAVE_DYNAMIC_FTRACE=y
881# CONFIG_FTRACE is not set
882# CONFIG_SCHED_TRACER is not set
883# CONFIG_CONTEXT_SWITCH_TRACER is not set
840# CONFIG_SAMPLES is not set 884# CONFIG_SAMPLES is not set
885CONFIG_HAVE_ARCH_KGDB=y
886# CONFIG_KGDB is not set
841# CONFIG_DEBUG_STACKOVERFLOW is not set 887# CONFIG_DEBUG_STACKOVERFLOW is not set
842# CONFIG_DEBUG_STACK_USAGE is not set 888# CONFIG_DEBUG_STACK_USAGE is not set
843# CONFIG_DEBUG_PAGEALLOC is not set 889# CONFIG_DEBUG_PAGEALLOC is not set
844# CONFIG_DEBUGGER is not set 890# CONFIG_CODE_PATCHING_SELFTEST is not set
845# CONFIG_KGDB_CONSOLE is not set 891# CONFIG_FTR_FIXUP_SELFTEST is not set
892# CONFIG_XMON is not set
846# CONFIG_IRQSTACKS is not set 893# CONFIG_IRQSTACKS is not set
847# CONFIG_BDI_SWITCH is not set 894# CONFIG_BDI_SWITCH is not set
848# CONFIG_PPC_EARLY_DEBUG is not set 895# CONFIG_PPC_EARLY_DEBUG is not set
@@ -895,6 +942,10 @@ CONFIG_CRYPTO=y
895# CONFIG_CRYPTO_MD4 is not set 942# CONFIG_CRYPTO_MD4 is not set
896# CONFIG_CRYPTO_MD5 is not set 943# CONFIG_CRYPTO_MD5 is not set
897# CONFIG_CRYPTO_MICHAEL_MIC is not set 944# CONFIG_CRYPTO_MICHAEL_MIC is not set
945# CONFIG_CRYPTO_RMD128 is not set
946# CONFIG_CRYPTO_RMD160 is not set
947# CONFIG_CRYPTO_RMD256 is not set
948# CONFIG_CRYPTO_RMD320 is not set
898# CONFIG_CRYPTO_SHA1 is not set 949# CONFIG_CRYPTO_SHA1 is not set
899# CONFIG_CRYPTO_SHA256 is not set 950# CONFIG_CRYPTO_SHA256 is not set
900# CONFIG_CRYPTO_SHA512 is not set 951# CONFIG_CRYPTO_SHA512 is not set
@@ -927,6 +978,7 @@ CONFIG_CRYPTO=y
927# CONFIG_CRYPTO_LZO is not set 978# CONFIG_CRYPTO_LZO is not set
928CONFIG_CRYPTO_HW=y 979CONFIG_CRYPTO_HW=y
929# CONFIG_CRYPTO_DEV_HIFN_795X is not set 980# CONFIG_CRYPTO_DEV_HIFN_795X is not set
930# CONFIG_PPC_CLOCK is not set 981# CONFIG_CRYPTO_DEV_TALITOS is not set
982CONFIG_PPC_CLOCK=y
931CONFIG_PPC_LIB_RHEAP=y 983CONFIG_PPC_LIB_RHEAP=y
932# CONFIG_VIRTUALIZATION is not set 984# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/configs/85xx/mpc8568mds_defconfig b/arch/powerpc/configs/85xx/mpc8568mds_defconfig
index 28004e93aeee..dc27c74955fa 100644
--- a/arch/powerpc/configs/85xx/mpc8568mds_defconfig
+++ b/arch/powerpc/configs/85xx/mpc8568mds_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc5 3# Linux kernel version: 2.6.27-rc4
4# Mon Jun 9 08:52:34 2008 4# Thu Aug 21 00:52:33 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -15,6 +15,7 @@ CONFIG_PPC_85xx=y
15# CONFIG_44x is not set 15# CONFIG_44x is not set
16# CONFIG_E200 is not set 16# CONFIG_E200 is not set
17CONFIG_E500=y 17CONFIG_E500=y
18# CONFIG_PPC_E500MC is not set
18CONFIG_BOOKE=y 19CONFIG_BOOKE=y
19CONFIG_FSL_BOOKE=y 20CONFIG_FSL_BOOKE=y
20CONFIG_FSL_EMB_PERFMON=y 21CONFIG_FSL_EMB_PERFMON=y
@@ -33,6 +34,7 @@ CONFIG_GENERIC_HARDIRQS=y
33# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set 34# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
34CONFIG_IRQ_PER_CPU=y 35CONFIG_IRQ_PER_CPU=y
35CONFIG_STACKTRACE_SUPPORT=y 36CONFIG_STACKTRACE_SUPPORT=y
37CONFIG_HAVE_LATENCYTOP_SUPPORT=y
36CONFIG_LOCKDEP_SUPPORT=y 38CONFIG_LOCKDEP_SUPPORT=y
37CONFIG_RWSEM_XCHGADD_ALGORITHM=y 39CONFIG_RWSEM_XCHGADD_ALGORITHM=y
38CONFIG_ARCH_HAS_ILOG2_U32=y 40CONFIG_ARCH_HAS_ILOG2_U32=y
@@ -89,7 +91,6 @@ CONFIG_INITRAMFS_SOURCE=""
89CONFIG_SYSCTL=y 91CONFIG_SYSCTL=y
90CONFIG_EMBEDDED=y 92CONFIG_EMBEDDED=y
91CONFIG_SYSCTL_SYSCALL=y 93CONFIG_SYSCTL_SYSCALL=y
92CONFIG_SYSCTL_SYSCALL_CHECK=y
93# CONFIG_KALLSYMS is not set 94# CONFIG_KALLSYMS is not set
94CONFIG_HOTPLUG=y 95CONFIG_HOTPLUG=y
95CONFIG_PRINTK=y 96CONFIG_PRINTK=y
@@ -112,10 +113,16 @@ CONFIG_SLUB=y
112# CONFIG_PROFILING is not set 113# CONFIG_PROFILING is not set
113# CONFIG_MARKERS is not set 114# CONFIG_MARKERS is not set
114CONFIG_HAVE_OPROFILE=y 115CONFIG_HAVE_OPROFILE=y
116CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
117CONFIG_HAVE_IOREMAP_PROT=y
115CONFIG_HAVE_KPROBES=y 118CONFIG_HAVE_KPROBES=y
116CONFIG_HAVE_KRETPROBES=y 119CONFIG_HAVE_KRETPROBES=y
120CONFIG_HAVE_ARCH_TRACEHOOK=y
117# CONFIG_HAVE_DMA_ATTRS is not set 121# CONFIG_HAVE_DMA_ATTRS is not set
122# CONFIG_USE_GENERIC_SMP_HELPERS is not set
123# CONFIG_HAVE_CLK is not set
118CONFIG_PROC_PAGE_MONITOR=y 124CONFIG_PROC_PAGE_MONITOR=y
125# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
119CONFIG_SLABINFO=y 126CONFIG_SLABINFO=y
120CONFIG_RT_MUTEXES=y 127CONFIG_RT_MUTEXES=y
121# CONFIG_TINY_SHMEM is not set 128# CONFIG_TINY_SHMEM is not set
@@ -126,12 +133,13 @@ CONFIG_MODULE_UNLOAD=y
126# CONFIG_MODULE_FORCE_UNLOAD is not set 133# CONFIG_MODULE_FORCE_UNLOAD is not set
127# CONFIG_MODVERSIONS is not set 134# CONFIG_MODVERSIONS is not set
128# CONFIG_MODULE_SRCVERSION_ALL is not set 135# CONFIG_MODULE_SRCVERSION_ALL is not set
129# CONFIG_KMOD is not set 136CONFIG_KMOD=y
130CONFIG_BLOCK=y 137CONFIG_BLOCK=y
131# CONFIG_LBD is not set 138# CONFIG_LBD is not set
132# CONFIG_BLK_DEV_IO_TRACE is not set 139# CONFIG_BLK_DEV_IO_TRACE is not set
133# CONFIG_LSF is not set 140# CONFIG_LSF is not set
134# CONFIG_BLK_DEV_BSG is not set 141# CONFIG_BLK_DEV_BSG is not set
142# CONFIG_BLK_DEV_INTEGRITY is not set
135 143
136# 144#
137# IO Schedulers 145# IO Schedulers
@@ -150,8 +158,6 @@ CONFIG_CLASSIC_RCU=y
150# 158#
151# Platform support 159# Platform support
152# 160#
153# CONFIG_PPC_MPC512x is not set
154# CONFIG_PPC_MPC5121 is not set
155# CONFIG_PPC_CELL is not set 161# CONFIG_PPC_CELL is not set
156# CONFIG_PPC_CELL_NATIVE is not set 162# CONFIG_PPC_CELL_NATIVE is not set
157# CONFIG_PQ2ADS is not set 163# CONFIG_PQ2ADS is not set
@@ -160,11 +166,13 @@ CONFIG_MPC85xx=y
160# CONFIG_MPC8560_ADS is not set 166# CONFIG_MPC8560_ADS is not set
161# CONFIG_MPC85xx_CDS is not set 167# CONFIG_MPC85xx_CDS is not set
162CONFIG_MPC85xx_MDS=y 168CONFIG_MPC85xx_MDS=y
169# CONFIG_MPC8536_DS is not set
163# CONFIG_MPC85xx_DS is not set 170# CONFIG_MPC85xx_DS is not set
164# CONFIG_KSI8560 is not set 171# CONFIG_KSI8560 is not set
165# CONFIG_STX_GP3 is not set 172# CONFIG_STX_GP3 is not set
166# CONFIG_TQM8540 is not set 173# CONFIG_TQM8540 is not set
167# CONFIG_TQM8541 is not set 174# CONFIG_TQM8541 is not set
175# CONFIG_TQM8548 is not set
168# CONFIG_TQM8555 is not set 176# CONFIG_TQM8555 is not set
169# CONFIG_TQM8560 is not set 177# CONFIG_TQM8560 is not set
170# CONFIG_SBC8548 is not set 178# CONFIG_SBC8548 is not set
@@ -197,7 +205,7 @@ CONFIG_HZ_250=y
197# CONFIG_HZ_300 is not set 205# CONFIG_HZ_300 is not set
198# CONFIG_HZ_1000 is not set 206# CONFIG_HZ_1000 is not set
199CONFIG_HZ=250 207CONFIG_HZ=250
200# CONFIG_SCHED_HRTICK is not set 208CONFIG_SCHED_HRTICK=y
201CONFIG_PREEMPT_NONE=y 209CONFIG_PREEMPT_NONE=y
202# CONFIG_PREEMPT_VOLUNTARY is not set 210# CONFIG_PREEMPT_VOLUNTARY is not set
203# CONFIG_PREEMPT is not set 211# CONFIG_PREEMPT is not set
@@ -220,6 +228,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
220# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set 228# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
221CONFIG_PAGEFLAGS_EXTENDED=y 229CONFIG_PAGEFLAGS_EXTENDED=y
222CONFIG_SPLIT_PTLOCK_CPUS=4 230CONFIG_SPLIT_PTLOCK_CPUS=4
231CONFIG_MIGRATION=y
223# CONFIG_RESOURCES_64BIT is not set 232# CONFIG_RESOURCES_64BIT is not set
224CONFIG_ZONE_DMA_FLAG=1 233CONFIG_ZONE_DMA_FLAG=1
225CONFIG_BOUNCE=y 234CONFIG_BOUNCE=y
@@ -227,6 +236,7 @@ CONFIG_VIRT_TO_BUS=y
227CONFIG_FORCE_MAX_ZONEORDER=11 236CONFIG_FORCE_MAX_ZONEORDER=11
228CONFIG_PROC_DEVICETREE=y 237CONFIG_PROC_DEVICETREE=y
229# CONFIG_CMDLINE_BOOL is not set 238# CONFIG_CMDLINE_BOOL is not set
239CONFIG_EXTRA_TARGETS=""
230# CONFIG_PM is not set 240# CONFIG_PM is not set
231CONFIG_SECCOMP=y 241CONFIG_SECCOMP=y
232CONFIG_ISA_DMA_API=y 242CONFIG_ISA_DMA_API=y
@@ -238,6 +248,7 @@ CONFIG_ZONE_DMA=y
238CONFIG_PPC_INDIRECT_PCI=y 248CONFIG_PPC_INDIRECT_PCI=y
239CONFIG_FSL_SOC=y 249CONFIG_FSL_SOC=y
240CONFIG_FSL_PCI=y 250CONFIG_FSL_PCI=y
251CONFIG_PPC_PCI_CHOICE=y
241CONFIG_PCI=y 252CONFIG_PCI=y
242CONFIG_PCI_DOMAINS=y 253CONFIG_PCI_DOMAINS=y
243CONFIG_PCI_SYSCALL=y 254CONFIG_PCI_SYSCALL=y
@@ -264,10 +275,6 @@ CONFIG_KERNEL_START=0xc0000000
264CONFIG_PHYSICAL_START=0x00000000 275CONFIG_PHYSICAL_START=0x00000000
265CONFIG_PHYSICAL_ALIGN=0x10000000 276CONFIG_PHYSICAL_ALIGN=0x10000000
266CONFIG_TASK_SIZE=0xc0000000 277CONFIG_TASK_SIZE=0xc0000000
267
268#
269# Networking
270#
271CONFIG_NET=y 278CONFIG_NET=y
272 279
273# 280#
@@ -385,12 +392,14 @@ CONFIG_BLK_DEV_RAM_SIZE=32768
385# CONFIG_BLK_DEV_XIP is not set 392# CONFIG_BLK_DEV_XIP is not set
386# CONFIG_CDROM_PKTCDVD is not set 393# CONFIG_CDROM_PKTCDVD is not set
387# CONFIG_ATA_OVER_ETH is not set 394# CONFIG_ATA_OVER_ETH is not set
395# CONFIG_BLK_DEV_HD is not set
388CONFIG_MISC_DEVICES=y 396CONFIG_MISC_DEVICES=y
389# CONFIG_PHANTOM is not set 397# CONFIG_PHANTOM is not set
390# CONFIG_EEPROM_93CX6 is not set 398# CONFIG_EEPROM_93CX6 is not set
391# CONFIG_SGI_IOC4 is not set 399# CONFIG_SGI_IOC4 is not set
392# CONFIG_TIFM_CORE is not set 400# CONFIG_TIFM_CORE is not set
393# CONFIG_ENCLOSURE_SERVICES is not set 401# CONFIG_ENCLOSURE_SERVICES is not set
402# CONFIG_HP_ILO is not set
394CONFIG_HAVE_IDE=y 403CONFIG_HAVE_IDE=y
395# CONFIG_IDE is not set 404# CONFIG_IDE is not set
396 405
@@ -468,6 +477,7 @@ CONFIG_SCSI_LOWLEVEL=y
468# CONFIG_SCSI_NSP32 is not set 477# CONFIG_SCSI_NSP32 is not set
469# CONFIG_SCSI_DEBUG is not set 478# CONFIG_SCSI_DEBUG is not set
470# CONFIG_SCSI_SRP is not set 479# CONFIG_SCSI_SRP is not set
480# CONFIG_SCSI_DH is not set
471# CONFIG_ATA is not set 481# CONFIG_ATA is not set
472# CONFIG_MD is not set 482# CONFIG_MD is not set
473# CONFIG_FUSION is not set 483# CONFIG_FUSION is not set
@@ -475,12 +485,15 @@ CONFIG_SCSI_LOWLEVEL=y
475# 485#
476# IEEE 1394 (FireWire) support 486# IEEE 1394 (FireWire) support
477# 487#
488
489#
490# Enable only one of the two stacks, unless you know what you are doing
491#
478# CONFIG_FIREWIRE is not set 492# CONFIG_FIREWIRE is not set
479# CONFIG_IEEE1394 is not set 493# CONFIG_IEEE1394 is not set
480# CONFIG_I2O is not set 494# CONFIG_I2O is not set
481# CONFIG_MACINTOSH_DRIVERS is not set 495# CONFIG_MACINTOSH_DRIVERS is not set
482CONFIG_NETDEVICES=y 496CONFIG_NETDEVICES=y
483# CONFIG_NETDEVICES_MULTIQUEUE is not set
484# CONFIG_DUMMY is not set 497# CONFIG_DUMMY is not set
485# CONFIG_BONDING is not set 498# CONFIG_BONDING is not set
486# CONFIG_MACVLAN is not set 499# CONFIG_MACVLAN is not set
@@ -524,7 +537,6 @@ CONFIG_NETDEV_1000=y
524# CONFIG_DL2K is not set 537# CONFIG_DL2K is not set
525# CONFIG_E1000 is not set 538# CONFIG_E1000 is not set
526# CONFIG_E1000E is not set 539# CONFIG_E1000E is not set
527# CONFIG_E1000E_ENABLED is not set
528# CONFIG_IP1000 is not set 540# CONFIG_IP1000 is not set
529# CONFIG_IGB is not set 541# CONFIG_IGB is not set
530# CONFIG_NS83820 is not set 542# CONFIG_NS83820 is not set
@@ -538,10 +550,10 @@ CONFIG_NETDEV_1000=y
538# CONFIG_TIGON3 is not set 550# CONFIG_TIGON3 is not set
539# CONFIG_BNX2 is not set 551# CONFIG_BNX2 is not set
540CONFIG_GIANFAR=y 552CONFIG_GIANFAR=y
541CONFIG_GFAR_NAPI=y
542# CONFIG_UCC_GETH is not set 553# CONFIG_UCC_GETH is not set
543# CONFIG_QLA3XXX is not set 554# CONFIG_QLA3XXX is not set
544# CONFIG_ATL1 is not set 555# CONFIG_ATL1 is not set
556# CONFIG_ATL1E is not set
545CONFIG_NETDEV_10000=y 557CONFIG_NETDEV_10000=y
546# CONFIG_CHELSIO_T1 is not set 558# CONFIG_CHELSIO_T1 is not set
547# CONFIG_CHELSIO_T3 is not set 559# CONFIG_CHELSIO_T3 is not set
@@ -648,42 +660,63 @@ CONFIG_DEVPORT=y
648CONFIG_I2C=y 660CONFIG_I2C=y
649CONFIG_I2C_BOARDINFO=y 661CONFIG_I2C_BOARDINFO=y
650CONFIG_I2C_CHARDEV=y 662CONFIG_I2C_CHARDEV=y
663CONFIG_I2C_HELPER_AUTO=y
651 664
652# 665#
653# I2C Hardware Bus support 666# I2C Hardware Bus support
654# 667#
668
669#
670# PC SMBus host controller drivers
671#
655# CONFIG_I2C_ALI1535 is not set 672# CONFIG_I2C_ALI1535 is not set
656# CONFIG_I2C_ALI1563 is not set 673# CONFIG_I2C_ALI1563 is not set
657# CONFIG_I2C_ALI15X3 is not set 674# CONFIG_I2C_ALI15X3 is not set
658# CONFIG_I2C_AMD756 is not set 675# CONFIG_I2C_AMD756 is not set
659# CONFIG_I2C_AMD8111 is not set 676# CONFIG_I2C_AMD8111 is not set
660# CONFIG_I2C_I801 is not set 677# CONFIG_I2C_I801 is not set
661# CONFIG_I2C_I810 is not set 678# CONFIG_I2C_ISCH is not set
662# CONFIG_I2C_PIIX4 is not set 679# CONFIG_I2C_PIIX4 is not set
663CONFIG_I2C_MPC=y
664# CONFIG_I2C_NFORCE2 is not set 680# CONFIG_I2C_NFORCE2 is not set
665# CONFIG_I2C_OCORES is not set
666# CONFIG_I2C_PARPORT_LIGHT is not set
667# CONFIG_I2C_PROSAVAGE is not set
668# CONFIG_I2C_SAVAGE4 is not set
669# CONFIG_I2C_SIMTEC is not set
670# CONFIG_I2C_SIS5595 is not set 681# CONFIG_I2C_SIS5595 is not set
671# CONFIG_I2C_SIS630 is not set 682# CONFIG_I2C_SIS630 is not set
672# CONFIG_I2C_SIS96X is not set 683# CONFIG_I2C_SIS96X is not set
673# CONFIG_I2C_TAOS_EVM is not set
674# CONFIG_I2C_STUB is not set
675# CONFIG_I2C_VIA is not set 684# CONFIG_I2C_VIA is not set
676# CONFIG_I2C_VIAPRO is not set 685# CONFIG_I2C_VIAPRO is not set
686
687#
688# I2C system bus drivers (mostly embedded / system-on-chip)
689#
690CONFIG_I2C_MPC=y
691# CONFIG_I2C_OCORES is not set
692# CONFIG_I2C_SIMTEC is not set
693
694#
695# External I2C/SMBus adapter drivers
696#
697# CONFIG_I2C_PARPORT_LIGHT is not set
698# CONFIG_I2C_TAOS_EVM is not set
699
700#
701# Graphics adapter I2C/DDC channel drivers
702#
677# CONFIG_I2C_VOODOO3 is not set 703# CONFIG_I2C_VOODOO3 is not set
704
705#
706# Other I2C/SMBus bus drivers
707#
678# CONFIG_I2C_PCA_PLATFORM is not set 708# CONFIG_I2C_PCA_PLATFORM is not set
709# CONFIG_I2C_STUB is not set
679 710
680# 711#
681# Miscellaneous I2C Chip support 712# Miscellaneous I2C Chip support
682# 713#
683# CONFIG_DS1682 is not set 714# CONFIG_DS1682 is not set
715# CONFIG_AT24 is not set
684# CONFIG_SENSORS_EEPROM is not set 716# CONFIG_SENSORS_EEPROM is not set
685# CONFIG_SENSORS_PCF8574 is not set 717# CONFIG_SENSORS_PCF8574 is not set
686# CONFIG_PCF8575 is not set 718# CONFIG_PCF8575 is not set
719# CONFIG_SENSORS_PCA9539 is not set
687# CONFIG_SENSORS_PCF8591 is not set 720# CONFIG_SENSORS_PCF8591 is not set
688# CONFIG_SENSORS_MAX6875 is not set 721# CONFIG_SENSORS_MAX6875 is not set
689# CONFIG_SENSORS_TSL2550 is not set 722# CONFIG_SENSORS_TSL2550 is not set
@@ -692,10 +725,13 @@ CONFIG_I2C_MPC=y
692# CONFIG_I2C_DEBUG_BUS is not set 725# CONFIG_I2C_DEBUG_BUS is not set
693# CONFIG_I2C_DEBUG_CHIP is not set 726# CONFIG_I2C_DEBUG_CHIP is not set
694# CONFIG_SPI is not set 727# CONFIG_SPI is not set
728CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
729# CONFIG_GPIOLIB is not set
695# CONFIG_W1 is not set 730# CONFIG_W1 is not set
696# CONFIG_POWER_SUPPLY is not set 731# CONFIG_POWER_SUPPLY is not set
697CONFIG_HWMON=y 732CONFIG_HWMON=y
698# CONFIG_HWMON_VID is not set 733# CONFIG_HWMON_VID is not set
734# CONFIG_SENSORS_AD7414 is not set
699# CONFIG_SENSORS_AD7418 is not set 735# CONFIG_SENSORS_AD7418 is not set
700# CONFIG_SENSORS_ADM1021 is not set 736# CONFIG_SENSORS_ADM1021 is not set
701# CONFIG_SENSORS_ADM1025 is not set 737# CONFIG_SENSORS_ADM1025 is not set
@@ -749,6 +785,7 @@ CONFIG_HWMON=y
749# CONFIG_SENSORS_W83627EHF is not set 785# CONFIG_SENSORS_W83627EHF is not set
750# CONFIG_HWMON_DEBUG_CHIP is not set 786# CONFIG_HWMON_DEBUG_CHIP is not set
751# CONFIG_THERMAL is not set 787# CONFIG_THERMAL is not set
788# CONFIG_THERMAL_HWMON is not set
752CONFIG_WATCHDOG=y 789CONFIG_WATCHDOG=y
753# CONFIG_WATCHDOG_NOWAYOUT is not set 790# CONFIG_WATCHDOG_NOWAYOUT is not set
754 791
@@ -756,6 +793,7 @@ CONFIG_WATCHDOG=y
756# Watchdog Device Drivers 793# Watchdog Device Drivers
757# 794#
758# CONFIG_SOFT_WATCHDOG is not set 795# CONFIG_SOFT_WATCHDOG is not set
796# CONFIG_ALIM7101_WDT is not set
759# CONFIG_BOOKE_WDT is not set 797# CONFIG_BOOKE_WDT is not set
760 798
761# 799#
@@ -773,8 +811,10 @@ CONFIG_SSB_POSSIBLE=y
773# 811#
774# Multifunction device drivers 812# Multifunction device drivers
775# 813#
814# CONFIG_MFD_CORE is not set
776# CONFIG_MFD_SM501 is not set 815# CONFIG_MFD_SM501 is not set
777# CONFIG_HTC_PASIC3 is not set 816# CONFIG_HTC_PASIC3 is not set
817# CONFIG_MFD_TMIO is not set
778 818
779# 819#
780# Multimedia devices 820# Multimedia devices
@@ -806,10 +846,6 @@ CONFIG_VIDEO_OUTPUT_CONTROL=m
806# Display device support 846# Display device support
807# 847#
808# CONFIG_DISPLAY_SUPPORT is not set 848# CONFIG_DISPLAY_SUPPORT is not set
809
810#
811# Sound
812#
813# CONFIG_SOUND is not set 849# CONFIG_SOUND is not set
814CONFIG_HID_SUPPORT=y 850CONFIG_HID_SUPPORT=y
815CONFIG_HID=y 851CONFIG_HID=y
@@ -824,6 +860,10 @@ CONFIG_USB_ARCH_HAS_EHCI=y
824# CONFIG_USB_OTG_BLACKLIST_HUB is not set 860# CONFIG_USB_OTG_BLACKLIST_HUB is not set
825 861
826# 862#
863# Enable Host or Gadget support to see Inventra options
864#
865
866#
827# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 867# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
828# 868#
829# CONFIG_USB_GADGET is not set 869# CONFIG_USB_GADGET is not set
@@ -862,6 +902,7 @@ CONFIG_RTC_DRV_DS1374=y
862# CONFIG_RTC_DRV_PCF8583 is not set 902# CONFIG_RTC_DRV_PCF8583 is not set
863# CONFIG_RTC_DRV_M41T80 is not set 903# CONFIG_RTC_DRV_M41T80 is not set
864# CONFIG_RTC_DRV_S35390A is not set 904# CONFIG_RTC_DRV_S35390A is not set
905# CONFIG_RTC_DRV_FM3130 is not set
865 906
866# 907#
867# SPI RTC drivers 908# SPI RTC drivers
@@ -950,6 +991,7 @@ CONFIG_TMPFS=y
950# CONFIG_CRAMFS is not set 991# CONFIG_CRAMFS is not set
951# CONFIG_VXFS_FS is not set 992# CONFIG_VXFS_FS is not set
952# CONFIG_MINIX_FS is not set 993# CONFIG_MINIX_FS is not set
994# CONFIG_OMFS_FS is not set
953# CONFIG_HPFS_FS is not set 995# CONFIG_HPFS_FS is not set
954# CONFIG_QNX4FS_FS is not set 996# CONFIG_QNX4FS_FS is not set
955# CONFIG_ROMFS_FS is not set 997# CONFIG_ROMFS_FS is not set
@@ -960,14 +1002,13 @@ CONFIG_NFS_FS=y
960CONFIG_NFS_V3=y 1002CONFIG_NFS_V3=y
961# CONFIG_NFS_V3_ACL is not set 1003# CONFIG_NFS_V3_ACL is not set
962CONFIG_NFS_V4=y 1004CONFIG_NFS_V4=y
963# CONFIG_NFSD is not set
964CONFIG_ROOT_NFS=y 1005CONFIG_ROOT_NFS=y
1006# CONFIG_NFSD is not set
965CONFIG_LOCKD=y 1007CONFIG_LOCKD=y
966CONFIG_LOCKD_V4=y 1008CONFIG_LOCKD_V4=y
967CONFIG_NFS_COMMON=y 1009CONFIG_NFS_COMMON=y
968CONFIG_SUNRPC=y 1010CONFIG_SUNRPC=y
969CONFIG_SUNRPC_GSS=y 1011CONFIG_SUNRPC_GSS=y
970# CONFIG_SUNRPC_BIND34 is not set
971CONFIG_RPCSEC_GSS_KRB5=y 1012CONFIG_RPCSEC_GSS_KRB5=y
972# CONFIG_RPCSEC_GSS_SPKM3 is not set 1013# CONFIG_RPCSEC_GSS_SPKM3 is not set
973# CONFIG_SMB_FS is not set 1014# CONFIG_SMB_FS is not set
@@ -995,6 +1036,7 @@ CONFIG_PARTITION_ADVANCED=y
995# CONFIG_SYSV68_PARTITION is not set 1036# CONFIG_SYSV68_PARTITION is not set
996# CONFIG_NLS is not set 1037# CONFIG_NLS is not set
997# CONFIG_DLM is not set 1038# CONFIG_DLM is not set
1039# CONFIG_QE_GPIO is not set
998 1040
999# 1041#
1000# Library routines 1042# Library routines
@@ -1003,6 +1045,7 @@ CONFIG_BITREVERSE=y
1003# CONFIG_GENERIC_FIND_FIRST_BIT is not set 1045# CONFIG_GENERIC_FIND_FIRST_BIT is not set
1004# CONFIG_CRC_CCITT is not set 1046# CONFIG_CRC_CCITT is not set
1005# CONFIG_CRC16 is not set 1047# CONFIG_CRC16 is not set
1048# CONFIG_CRC_T10DIF is not set
1006# CONFIG_CRC_ITU_T is not set 1049# CONFIG_CRC_ITU_T is not set
1007CONFIG_CRC32=y 1050CONFIG_CRC32=y
1008# CONFIG_CRC7 is not set 1051# CONFIG_CRC7 is not set
@@ -1027,6 +1070,8 @@ CONFIG_FRAME_WARN=1024
1027CONFIG_DEBUG_KERNEL=y 1070CONFIG_DEBUG_KERNEL=y
1028# CONFIG_DEBUG_SHIRQ is not set 1071# CONFIG_DEBUG_SHIRQ is not set
1029CONFIG_DETECT_SOFTLOCKUP=y 1072CONFIG_DETECT_SOFTLOCKUP=y
1073# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
1074CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
1030CONFIG_SCHED_DEBUG=y 1075CONFIG_SCHED_DEBUG=y
1031# CONFIG_SCHEDSTATS is not set 1076# CONFIG_SCHEDSTATS is not set
1032# CONFIG_TIMER_STATS is not set 1077# CONFIG_TIMER_STATS is not set
@@ -1044,17 +1089,28 @@ CONFIG_SCHED_DEBUG=y
1044# CONFIG_DEBUG_INFO is not set 1089# CONFIG_DEBUG_INFO is not set
1045# CONFIG_DEBUG_VM is not set 1090# CONFIG_DEBUG_VM is not set
1046# CONFIG_DEBUG_WRITECOUNT is not set 1091# CONFIG_DEBUG_WRITECOUNT is not set
1092# CONFIG_DEBUG_MEMORY_INIT is not set
1047# CONFIG_DEBUG_LIST is not set 1093# CONFIG_DEBUG_LIST is not set
1048# CONFIG_DEBUG_SG is not set 1094# CONFIG_DEBUG_SG is not set
1049# CONFIG_BOOT_PRINTK_DELAY is not set 1095# CONFIG_BOOT_PRINTK_DELAY is not set
1050# CONFIG_RCU_TORTURE_TEST is not set 1096# CONFIG_RCU_TORTURE_TEST is not set
1051# CONFIG_BACKTRACE_SELF_TEST is not set 1097# CONFIG_BACKTRACE_SELF_TEST is not set
1052# CONFIG_FAULT_INJECTION is not set 1098# CONFIG_FAULT_INJECTION is not set
1099# CONFIG_LATENCYTOP is not set
1100CONFIG_SYSCTL_SYSCALL_CHECK=y
1101CONFIG_HAVE_FTRACE=y
1102CONFIG_HAVE_DYNAMIC_FTRACE=y
1103# CONFIG_FTRACE is not set
1104# CONFIG_SCHED_TRACER is not set
1105# CONFIG_CONTEXT_SWITCH_TRACER is not set
1053# CONFIG_SAMPLES is not set 1106# CONFIG_SAMPLES is not set
1107CONFIG_HAVE_ARCH_KGDB=y
1108# CONFIG_KGDB is not set
1054# CONFIG_DEBUG_STACKOVERFLOW is not set 1109# CONFIG_DEBUG_STACKOVERFLOW is not set
1055# CONFIG_DEBUG_STACK_USAGE is not set 1110# CONFIG_DEBUG_STACK_USAGE is not set
1056# CONFIG_DEBUG_PAGEALLOC is not set 1111# CONFIG_DEBUG_PAGEALLOC is not set
1057CONFIG_DEBUGGER=y 1112# CONFIG_CODE_PATCHING_SELFTEST is not set
1113# CONFIG_FTR_FIXUP_SELFTEST is not set
1058# CONFIG_XMON is not set 1114# CONFIG_XMON is not set
1059# CONFIG_IRQSTACKS is not set 1115# CONFIG_IRQSTACKS is not set
1060# CONFIG_BDI_SWITCH is not set 1116# CONFIG_BDI_SWITCH is not set
@@ -1122,6 +1178,10 @@ CONFIG_CRYPTO_PCBC=m
1122# CONFIG_CRYPTO_MD4 is not set 1178# CONFIG_CRYPTO_MD4 is not set
1123CONFIG_CRYPTO_MD5=y 1179CONFIG_CRYPTO_MD5=y
1124# CONFIG_CRYPTO_MICHAEL_MIC is not set 1180# CONFIG_CRYPTO_MICHAEL_MIC is not set
1181# CONFIG_CRYPTO_RMD128 is not set
1182# CONFIG_CRYPTO_RMD160 is not set
1183# CONFIG_CRYPTO_RMD256 is not set
1184# CONFIG_CRYPTO_RMD320 is not set
1125# CONFIG_CRYPTO_SHA1 is not set 1185# CONFIG_CRYPTO_SHA1 is not set
1126# CONFIG_CRYPTO_SHA256 is not set 1186# CONFIG_CRYPTO_SHA256 is not set
1127# CONFIG_CRYPTO_SHA512 is not set 1187# CONFIG_CRYPTO_SHA512 is not set
@@ -1154,6 +1214,7 @@ CONFIG_CRYPTO_DES=y
1154# CONFIG_CRYPTO_LZO is not set 1214# CONFIG_CRYPTO_LZO is not set
1155CONFIG_CRYPTO_HW=y 1215CONFIG_CRYPTO_HW=y
1156# CONFIG_CRYPTO_DEV_HIFN_795X is not set 1216# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1217# CONFIG_CRYPTO_DEV_TALITOS is not set
1157# CONFIG_PPC_CLOCK is not set 1218# CONFIG_PPC_CLOCK is not set
1158CONFIG_PPC_LIB_RHEAP=y 1219CONFIG_PPC_LIB_RHEAP=y
1159# CONFIG_VIRTUALIZATION is not set 1220# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/configs/85xx/mpc8572_ds_defconfig b/arch/powerpc/configs/85xx/mpc8572_ds_defconfig
index 164fd9606ee6..eda45bb8a13f 100644
--- a/arch/powerpc/configs/85xx/mpc8572_ds_defconfig
+++ b/arch/powerpc/configs/85xx/mpc8572_ds_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc5 3# Linux kernel version: 2.6.27-rc4
4# Mon Jun 9 08:52:35 2008 4# Thu Aug 21 07:21:42 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -15,6 +15,7 @@ CONFIG_PPC_85xx=y
15# CONFIG_44x is not set 15# CONFIG_44x is not set
16# CONFIG_E200 is not set 16# CONFIG_E200 is not set
17CONFIG_E500=y 17CONFIG_E500=y
18# CONFIG_PPC_E500MC is not set
18CONFIG_BOOKE=y 19CONFIG_BOOKE=y
19CONFIG_FSL_BOOKE=y 20CONFIG_FSL_BOOKE=y
20CONFIG_FSL_EMB_PERFMON=y 21CONFIG_FSL_EMB_PERFMON=y
@@ -33,6 +34,7 @@ CONFIG_GENERIC_HARDIRQS=y
33# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set 34# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
34CONFIG_IRQ_PER_CPU=y 35CONFIG_IRQ_PER_CPU=y
35CONFIG_STACKTRACE_SUPPORT=y 36CONFIG_STACKTRACE_SUPPORT=y
37CONFIG_HAVE_LATENCYTOP_SUPPORT=y
36CONFIG_LOCKDEP_SUPPORT=y 38CONFIG_LOCKDEP_SUPPORT=y
37CONFIG_RWSEM_XCHGADD_ALGORITHM=y 39CONFIG_RWSEM_XCHGADD_ALGORITHM=y
38CONFIG_ARCH_HAS_ILOG2_U32=y 40CONFIG_ARCH_HAS_ILOG2_U32=y
@@ -92,7 +94,6 @@ CONFIG_INITRAMFS_SOURCE=""
92CONFIG_SYSCTL=y 94CONFIG_SYSCTL=y
93CONFIG_EMBEDDED=y 95CONFIG_EMBEDDED=y
94CONFIG_SYSCTL_SYSCALL=y 96CONFIG_SYSCTL_SYSCALL=y
95CONFIG_SYSCTL_SYSCALL_CHECK=y
96CONFIG_KALLSYMS=y 97CONFIG_KALLSYMS=y
97CONFIG_KALLSYMS_ALL=y 98CONFIG_KALLSYMS_ALL=y
98CONFIG_KALLSYMS_EXTRA_PASS=y 99CONFIG_KALLSYMS_EXTRA_PASS=y
@@ -118,10 +119,16 @@ CONFIG_SLUB=y
118# CONFIG_MARKERS is not set 119# CONFIG_MARKERS is not set
119CONFIG_HAVE_OPROFILE=y 120CONFIG_HAVE_OPROFILE=y
120# CONFIG_KPROBES is not set 121# CONFIG_KPROBES is not set
122CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
123CONFIG_HAVE_IOREMAP_PROT=y
121CONFIG_HAVE_KPROBES=y 124CONFIG_HAVE_KPROBES=y
122CONFIG_HAVE_KRETPROBES=y 125CONFIG_HAVE_KRETPROBES=y
126CONFIG_HAVE_ARCH_TRACEHOOK=y
123# CONFIG_HAVE_DMA_ATTRS is not set 127# CONFIG_HAVE_DMA_ATTRS is not set
128# CONFIG_USE_GENERIC_SMP_HELPERS is not set
129# CONFIG_HAVE_CLK is not set
124CONFIG_PROC_PAGE_MONITOR=y 130CONFIG_PROC_PAGE_MONITOR=y
131# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
125CONFIG_SLABINFO=y 132CONFIG_SLABINFO=y
126CONFIG_RT_MUTEXES=y 133CONFIG_RT_MUTEXES=y
127# CONFIG_TINY_SHMEM is not set 134# CONFIG_TINY_SHMEM is not set
@@ -138,6 +145,7 @@ CONFIG_LBD=y
138# CONFIG_BLK_DEV_IO_TRACE is not set 145# CONFIG_BLK_DEV_IO_TRACE is not set
139# CONFIG_LSF is not set 146# CONFIG_LSF is not set
140# CONFIG_BLK_DEV_BSG is not set 147# CONFIG_BLK_DEV_BSG is not set
148# CONFIG_BLK_DEV_INTEGRITY is not set
141 149
142# 150#
143# IO Schedulers 151# IO Schedulers
@@ -156,8 +164,6 @@ CONFIG_CLASSIC_RCU=y
156# 164#
157# Platform support 165# Platform support
158# 166#
159# CONFIG_PPC_MPC512x is not set
160# CONFIG_PPC_MPC5121 is not set
161# CONFIG_PPC_CELL is not set 167# CONFIG_PPC_CELL is not set
162# CONFIG_PPC_CELL_NATIVE is not set 168# CONFIG_PPC_CELL_NATIVE is not set
163# CONFIG_PQ2ADS is not set 169# CONFIG_PQ2ADS is not set
@@ -166,11 +172,13 @@ CONFIG_MPC85xx=y
166# CONFIG_MPC8560_ADS is not set 172# CONFIG_MPC8560_ADS is not set
167# CONFIG_MPC85xx_CDS is not set 173# CONFIG_MPC85xx_CDS is not set
168# CONFIG_MPC85xx_MDS is not set 174# CONFIG_MPC85xx_MDS is not set
175# CONFIG_MPC8536_DS is not set
169CONFIG_MPC85xx_DS=y 176CONFIG_MPC85xx_DS=y
170# CONFIG_KSI8560 is not set 177# CONFIG_KSI8560 is not set
171# CONFIG_STX_GP3 is not set 178# CONFIG_STX_GP3 is not set
172# CONFIG_TQM8540 is not set 179# CONFIG_TQM8540 is not set
173# CONFIG_TQM8541 is not set 180# CONFIG_TQM8541 is not set
181# CONFIG_TQM8548 is not set
174# CONFIG_TQM8555 is not set 182# CONFIG_TQM8555 is not set
175# CONFIG_TQM8560 is not set 183# CONFIG_TQM8560 is not set
176# CONFIG_SBC8548 is not set 184# CONFIG_SBC8548 is not set
@@ -202,7 +210,7 @@ CONFIG_HZ_250=y
202# CONFIG_HZ_300 is not set 210# CONFIG_HZ_300 is not set
203# CONFIG_HZ_1000 is not set 211# CONFIG_HZ_1000 is not set
204CONFIG_HZ=250 212CONFIG_HZ=250
205# CONFIG_SCHED_HRTICK is not set 213CONFIG_SCHED_HRTICK=y
206CONFIG_PREEMPT_NONE=y 214CONFIG_PREEMPT_NONE=y
207# CONFIG_PREEMPT_VOLUNTARY is not set 215# CONFIG_PREEMPT_VOLUNTARY is not set
208# CONFIG_PREEMPT is not set 216# CONFIG_PREEMPT is not set
@@ -225,6 +233,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
225# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set 233# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
226CONFIG_PAGEFLAGS_EXTENDED=y 234CONFIG_PAGEFLAGS_EXTENDED=y
227CONFIG_SPLIT_PTLOCK_CPUS=4 235CONFIG_SPLIT_PTLOCK_CPUS=4
236CONFIG_MIGRATION=y
228# CONFIG_RESOURCES_64BIT is not set 237# CONFIG_RESOURCES_64BIT is not set
229CONFIG_ZONE_DMA_FLAG=1 238CONFIG_ZONE_DMA_FLAG=1
230CONFIG_BOUNCE=y 239CONFIG_BOUNCE=y
@@ -232,6 +241,7 @@ CONFIG_VIRT_TO_BUS=y
232CONFIG_FORCE_MAX_ZONEORDER=11 241CONFIG_FORCE_MAX_ZONEORDER=11
233CONFIG_PROC_DEVICETREE=y 242CONFIG_PROC_DEVICETREE=y
234# CONFIG_CMDLINE_BOOL is not set 243# CONFIG_CMDLINE_BOOL is not set
244CONFIG_EXTRA_TARGETS=""
235# CONFIG_PM is not set 245# CONFIG_PM is not set
236CONFIG_SECCOMP=y 246CONFIG_SECCOMP=y
237CONFIG_ISA_DMA_API=y 247CONFIG_ISA_DMA_API=y
@@ -244,6 +254,7 @@ CONFIG_GENERIC_ISA_DMA=y
244CONFIG_PPC_INDIRECT_PCI=y 254CONFIG_PPC_INDIRECT_PCI=y
245CONFIG_FSL_SOC=y 255CONFIG_FSL_SOC=y
246CONFIG_FSL_PCI=y 256CONFIG_FSL_PCI=y
257CONFIG_PPC_PCI_CHOICE=y
247CONFIG_PCI=y 258CONFIG_PCI=y
248CONFIG_PCI_DOMAINS=y 259CONFIG_PCI_DOMAINS=y
249CONFIG_PCI_SYSCALL=y 260CONFIG_PCI_SYSCALL=y
@@ -270,10 +281,6 @@ CONFIG_KERNEL_START=0xc0000000
270CONFIG_PHYSICAL_START=0x00000000 281CONFIG_PHYSICAL_START=0x00000000
271CONFIG_PHYSICAL_ALIGN=0x10000000 282CONFIG_PHYSICAL_ALIGN=0x10000000
272CONFIG_TASK_SIZE=0xc0000000 283CONFIG_TASK_SIZE=0xc0000000
273
274#
275# Networking
276#
277CONFIG_NET=y 284CONFIG_NET=y
278 285
279# 286#
@@ -399,6 +406,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
399CONFIG_STANDALONE=y 406CONFIG_STANDALONE=y
400CONFIG_PREVENT_FIRMWARE_BUILD=y 407CONFIG_PREVENT_FIRMWARE_BUILD=y
401CONFIG_FW_LOADER=y 408CONFIG_FW_LOADER=y
409CONFIG_FIRMWARE_IN_KERNEL=y
410CONFIG_EXTRA_FIRMWARE=""
402# CONFIG_DEBUG_DRIVER is not set 411# CONFIG_DEBUG_DRIVER is not set
403# CONFIG_DEBUG_DEVRES is not set 412# CONFIG_DEBUG_DEVRES is not set
404# CONFIG_SYS_HYPERVISOR is not set 413# CONFIG_SYS_HYPERVISOR is not set
@@ -425,12 +434,14 @@ CONFIG_BLK_DEV_RAM_SIZE=131072
425# CONFIG_BLK_DEV_XIP is not set 434# CONFIG_BLK_DEV_XIP is not set
426# CONFIG_CDROM_PKTCDVD is not set 435# CONFIG_CDROM_PKTCDVD is not set
427# CONFIG_ATA_OVER_ETH is not set 436# CONFIG_ATA_OVER_ETH is not set
437# CONFIG_BLK_DEV_HD is not set
428CONFIG_MISC_DEVICES=y 438CONFIG_MISC_DEVICES=y
429# CONFIG_PHANTOM is not set 439# CONFIG_PHANTOM is not set
430# CONFIG_EEPROM_93CX6 is not set 440# CONFIG_EEPROM_93CX6 is not set
431# CONFIG_SGI_IOC4 is not set 441# CONFIG_SGI_IOC4 is not set
432# CONFIG_TIFM_CORE is not set 442# CONFIG_TIFM_CORE is not set
433# CONFIG_ENCLOSURE_SERVICES is not set 443# CONFIG_ENCLOSURE_SERVICES is not set
444# CONFIG_HP_ILO is not set
434CONFIG_HAVE_IDE=y 445CONFIG_HAVE_IDE=y
435# CONFIG_IDE is not set 446# CONFIG_IDE is not set
436 447
@@ -510,6 +521,7 @@ CONFIG_SCSI_LOWLEVEL=y
510# CONFIG_SCSI_NSP32 is not set 521# CONFIG_SCSI_NSP32 is not set
511# CONFIG_SCSI_DEBUG is not set 522# CONFIG_SCSI_DEBUG is not set
512# CONFIG_SCSI_SRP is not set 523# CONFIG_SCSI_SRP is not set
524# CONFIG_SCSI_DH is not set
513CONFIG_ATA=y 525CONFIG_ATA=y
514# CONFIG_ATA_NONSTANDARD is not set 526# CONFIG_ATA_NONSTANDARD is not set
515CONFIG_SATA_PMP=y 527CONFIG_SATA_PMP=y
@@ -577,12 +589,15 @@ CONFIG_PATA_ALI=y
577# 589#
578# IEEE 1394 (FireWire) support 590# IEEE 1394 (FireWire) support
579# 591#
592
593#
594# Enable only one of the two stacks, unless you know what you are doing
595#
580# CONFIG_FIREWIRE is not set 596# CONFIG_FIREWIRE is not set
581# CONFIG_IEEE1394 is not set 597# CONFIG_IEEE1394 is not set
582# CONFIG_I2O is not set 598# CONFIG_I2O is not set
583# CONFIG_MACINTOSH_DRIVERS is not set 599# CONFIG_MACINTOSH_DRIVERS is not set
584CONFIG_NETDEVICES=y 600CONFIG_NETDEVICES=y
585# CONFIG_NETDEVICES_MULTIQUEUE is not set
586CONFIG_DUMMY=y 601CONFIG_DUMMY=y
587# CONFIG_BONDING is not set 602# CONFIG_BONDING is not set
588# CONFIG_MACVLAN is not set 603# CONFIG_MACVLAN is not set
@@ -626,7 +641,6 @@ CONFIG_NETDEV_1000=y
626# CONFIG_DL2K is not set 641# CONFIG_DL2K is not set
627# CONFIG_E1000 is not set 642# CONFIG_E1000 is not set
628# CONFIG_E1000E is not set 643# CONFIG_E1000E is not set
629# CONFIG_E1000E_ENABLED is not set
630# CONFIG_IP1000 is not set 644# CONFIG_IP1000 is not set
631# CONFIG_IGB is not set 645# CONFIG_IGB is not set
632# CONFIG_NS83820 is not set 646# CONFIG_NS83820 is not set
@@ -640,9 +654,9 @@ CONFIG_NETDEV_1000=y
640# CONFIG_TIGON3 is not set 654# CONFIG_TIGON3 is not set
641# CONFIG_BNX2 is not set 655# CONFIG_BNX2 is not set
642CONFIG_GIANFAR=y 656CONFIG_GIANFAR=y
643CONFIG_GFAR_NAPI=y
644# CONFIG_QLA3XXX is not set 657# CONFIG_QLA3XXX is not set
645# CONFIG_ATL1 is not set 658# CONFIG_ATL1 is not set
659# CONFIG_ATL1E is not set
646CONFIG_NETDEV_10000=y 660CONFIG_NETDEV_10000=y
647# CONFIG_CHELSIO_T1 is not set 661# CONFIG_CHELSIO_T1 is not set
648# CONFIG_CHELSIO_T3 is not set 662# CONFIG_CHELSIO_T3 is not set
@@ -719,12 +733,14 @@ CONFIG_SERIO_SERPORT=y
719# CONFIG_SERIO_PCIPS2 is not set 733# CONFIG_SERIO_PCIPS2 is not set
720CONFIG_SERIO_LIBPS2=y 734CONFIG_SERIO_LIBPS2=y
721# CONFIG_SERIO_RAW is not set 735# CONFIG_SERIO_RAW is not set
736# CONFIG_SERIO_XILINX_XPS_PS2 is not set
722# CONFIG_GAMEPORT is not set 737# CONFIG_GAMEPORT is not set
723 738
724# 739#
725# Character devices 740# Character devices
726# 741#
727CONFIG_VT=y 742CONFIG_VT=y
743CONFIG_CONSOLE_TRANSLATIONS=y
728CONFIG_VT_CONSOLE=y 744CONFIG_VT_CONSOLE=y
729CONFIG_HW_CONSOLE=y 745CONFIG_HW_CONSOLE=y
730# CONFIG_VT_HW_CONSOLE_BINDING is not set 746# CONFIG_VT_HW_CONSOLE_BINDING is not set
@@ -758,7 +774,7 @@ CONFIG_UNIX98_PTYS=y
758CONFIG_LEGACY_PTYS=y 774CONFIG_LEGACY_PTYS=y
759CONFIG_LEGACY_PTY_COUNT=256 775CONFIG_LEGACY_PTY_COUNT=256
760# CONFIG_IPMI_HANDLER is not set 776# CONFIG_IPMI_HANDLER is not set
761# CONFIG_HW_RANDOM is not set 777CONFIG_HW_RANDOM=y
762CONFIG_NVRAM=y 778CONFIG_NVRAM=y
763# CONFIG_R3964 is not set 779# CONFIG_R3964 is not set
764# CONFIG_APPLICOM is not set 780# CONFIG_APPLICOM is not set
@@ -768,43 +784,64 @@ CONFIG_DEVPORT=y
768CONFIG_I2C=y 784CONFIG_I2C=y
769CONFIG_I2C_BOARDINFO=y 785CONFIG_I2C_BOARDINFO=y
770# CONFIG_I2C_CHARDEV is not set 786# CONFIG_I2C_CHARDEV is not set
787CONFIG_I2C_HELPER_AUTO=y
771 788
772# 789#
773# I2C Hardware Bus support 790# I2C Hardware Bus support
774# 791#
792
793#
794# PC SMBus host controller drivers
795#
775# CONFIG_I2C_ALI1535 is not set 796# CONFIG_I2C_ALI1535 is not set
776# CONFIG_I2C_ALI1563 is not set 797# CONFIG_I2C_ALI1563 is not set
777# CONFIG_I2C_ALI15X3 is not set 798# CONFIG_I2C_ALI15X3 is not set
778# CONFIG_I2C_AMD756 is not set 799# CONFIG_I2C_AMD756 is not set
779# CONFIG_I2C_AMD8111 is not set 800# CONFIG_I2C_AMD8111 is not set
780# CONFIG_I2C_I801 is not set 801# CONFIG_I2C_I801 is not set
781# CONFIG_I2C_I810 is not set 802# CONFIG_I2C_ISCH is not set
782# CONFIG_I2C_PIIX4 is not set 803# CONFIG_I2C_PIIX4 is not set
783CONFIG_I2C_MPC=y
784# CONFIG_I2C_NFORCE2 is not set 804# CONFIG_I2C_NFORCE2 is not set
785# CONFIG_I2C_OCORES is not set
786# CONFIG_I2C_PARPORT_LIGHT is not set
787# CONFIG_I2C_PROSAVAGE is not set
788# CONFIG_I2C_SAVAGE4 is not set
789# CONFIG_I2C_SIMTEC is not set
790# CONFIG_I2C_SIS5595 is not set 805# CONFIG_I2C_SIS5595 is not set
791# CONFIG_I2C_SIS630 is not set 806# CONFIG_I2C_SIS630 is not set
792# CONFIG_I2C_SIS96X is not set 807# CONFIG_I2C_SIS96X is not set
793# CONFIG_I2C_TAOS_EVM is not set
794# CONFIG_I2C_STUB is not set
795# CONFIG_I2C_TINY_USB is not set
796# CONFIG_I2C_VIA is not set 808# CONFIG_I2C_VIA is not set
797# CONFIG_I2C_VIAPRO is not set 809# CONFIG_I2C_VIAPRO is not set
810
811#
812# I2C system bus drivers (mostly embedded / system-on-chip)
813#
814CONFIG_I2C_MPC=y
815# CONFIG_I2C_OCORES is not set
816# CONFIG_I2C_SIMTEC is not set
817
818#
819# External I2C/SMBus adapter drivers
820#
821# CONFIG_I2C_PARPORT_LIGHT is not set
822# CONFIG_I2C_TAOS_EVM is not set
823# CONFIG_I2C_TINY_USB is not set
824
825#
826# Graphics adapter I2C/DDC channel drivers
827#
798# CONFIG_I2C_VOODOO3 is not set 828# CONFIG_I2C_VOODOO3 is not set
829
830#
831# Other I2C/SMBus bus drivers
832#
799# CONFIG_I2C_PCA_PLATFORM is not set 833# CONFIG_I2C_PCA_PLATFORM is not set
834# CONFIG_I2C_STUB is not set
800 835
801# 836#
802# Miscellaneous I2C Chip support 837# Miscellaneous I2C Chip support
803# 838#
804# CONFIG_DS1682 is not set 839# CONFIG_DS1682 is not set
840# CONFIG_AT24 is not set
805CONFIG_SENSORS_EEPROM=y 841CONFIG_SENSORS_EEPROM=y
806# CONFIG_SENSORS_PCF8574 is not set 842# CONFIG_SENSORS_PCF8574 is not set
807# CONFIG_PCF8575 is not set 843# CONFIG_PCF8575 is not set
844# CONFIG_SENSORS_PCA9539 is not set
808# CONFIG_SENSORS_PCF8591 is not set 845# CONFIG_SENSORS_PCF8591 is not set
809# CONFIG_SENSORS_MAX6875 is not set 846# CONFIG_SENSORS_MAX6875 is not set
810# CONFIG_SENSORS_TSL2550 is not set 847# CONFIG_SENSORS_TSL2550 is not set
@@ -813,10 +850,13 @@ CONFIG_SENSORS_EEPROM=y
813# CONFIG_I2C_DEBUG_BUS is not set 850# CONFIG_I2C_DEBUG_BUS is not set
814# CONFIG_I2C_DEBUG_CHIP is not set 851# CONFIG_I2C_DEBUG_CHIP is not set
815# CONFIG_SPI is not set 852# CONFIG_SPI is not set
853CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
854# CONFIG_GPIOLIB is not set
816# CONFIG_W1 is not set 855# CONFIG_W1 is not set
817# CONFIG_POWER_SUPPLY is not set 856# CONFIG_POWER_SUPPLY is not set
818# CONFIG_HWMON is not set 857# CONFIG_HWMON is not set
819# CONFIG_THERMAL is not set 858# CONFIG_THERMAL is not set
859# CONFIG_THERMAL_HWMON is not set
820# CONFIG_WATCHDOG is not set 860# CONFIG_WATCHDOG is not set
821 861
822# 862#
@@ -828,8 +868,10 @@ CONFIG_SSB_POSSIBLE=y
828# 868#
829# Multifunction device drivers 869# Multifunction device drivers
830# 870#
871# CONFIG_MFD_CORE is not set
831# CONFIG_MFD_SM501 is not set 872# CONFIG_MFD_SM501 is not set
832# CONFIG_HTC_PASIC3 is not set 873# CONFIG_HTC_PASIC3 is not set
874# CONFIG_MFD_TMIO is not set
833 875
834# 876#
835# Multimedia devices 877# Multimedia devices
@@ -871,6 +913,7 @@ CONFIG_DVB_CAPTURE_DRIVERS=y
871# CONFIG_DVB_TTUSB_BUDGET is not set 913# CONFIG_DVB_TTUSB_BUDGET is not set
872# CONFIG_DVB_TTUSB_DEC is not set 914# CONFIG_DVB_TTUSB_DEC is not set
873# CONFIG_DVB_CINERGYT2 is not set 915# CONFIG_DVB_CINERGYT2 is not set
916# CONFIG_DVB_SIANO_SMS1XXX is not set
874 917
875# 918#
876# Supported FlexCopII (B2C2) Adapters 919# Supported FlexCopII (B2C2) Adapters
@@ -917,6 +960,7 @@ CONFIG_DVB_CAPTURE_DRIVERS=y
917# CONFIG_DVB_SP887X is not set 960# CONFIG_DVB_SP887X is not set
918# CONFIG_DVB_CX22700 is not set 961# CONFIG_DVB_CX22700 is not set
919# CONFIG_DVB_CX22702 is not set 962# CONFIG_DVB_CX22702 is not set
963# CONFIG_DVB_DRX397XD is not set
920# CONFIG_DVB_L64781 is not set 964# CONFIG_DVB_L64781 is not set
921# CONFIG_DVB_TDA1004X is not set 965# CONFIG_DVB_TDA1004X is not set
922# CONFIG_DVB_NXT6000 is not set 966# CONFIG_DVB_NXT6000 is not set
@@ -984,15 +1028,7 @@ CONFIG_VIDEO_OUTPUT_CONTROL=y
984CONFIG_VGA_CONSOLE=y 1028CONFIG_VGA_CONSOLE=y
985# CONFIG_VGACON_SOFT_SCROLLBACK is not set 1029# CONFIG_VGACON_SOFT_SCROLLBACK is not set
986CONFIG_DUMMY_CONSOLE=y 1030CONFIG_DUMMY_CONSOLE=y
987
988#
989# Sound
990#
991CONFIG_SOUND=y 1031CONFIG_SOUND=y
992
993#
994# Advanced Linux Sound Architecture
995#
996CONFIG_SND=y 1032CONFIG_SND=y
997CONFIG_SND_TIMER=y 1033CONFIG_SND_TIMER=y
998CONFIG_SND_PCM=y 1034CONFIG_SND_PCM=y
@@ -1006,19 +1042,15 @@ CONFIG_SND_PCM_OSS_PLUGINS=y
1006CONFIG_SND_VERBOSE_PROCFS=y 1042CONFIG_SND_VERBOSE_PROCFS=y
1007# CONFIG_SND_VERBOSE_PRINTK is not set 1043# CONFIG_SND_VERBOSE_PRINTK is not set
1008# CONFIG_SND_DEBUG is not set 1044# CONFIG_SND_DEBUG is not set
1009 1045CONFIG_SND_VMASTER=y
1010#
1011# Generic devices
1012#
1013CONFIG_SND_AC97_CODEC=y 1046CONFIG_SND_AC97_CODEC=y
1047CONFIG_SND_DRIVERS=y
1014# CONFIG_SND_DUMMY is not set 1048# CONFIG_SND_DUMMY is not set
1015# CONFIG_SND_MTPAV is not set 1049# CONFIG_SND_MTPAV is not set
1016# CONFIG_SND_SERIAL_U16550 is not set 1050# CONFIG_SND_SERIAL_U16550 is not set
1017# CONFIG_SND_MPU401 is not set 1051# CONFIG_SND_MPU401 is not set
1018 1052# CONFIG_SND_AC97_POWER_SAVE is not set
1019# 1053CONFIG_SND_PCI=y
1020# PCI devices
1021#
1022# CONFIG_SND_AD1889 is not set 1054# CONFIG_SND_AD1889 is not set
1023# CONFIG_SND_ALS300 is not set 1055# CONFIG_SND_ALS300 is not set
1024# CONFIG_SND_ALS4000 is not set 1056# CONFIG_SND_ALS4000 is not set
@@ -1080,39 +1112,12 @@ CONFIG_SND_INTEL8X0=y
1080# CONFIG_SND_VIRTUOSO is not set 1112# CONFIG_SND_VIRTUOSO is not set
1081# CONFIG_SND_VX222 is not set 1113# CONFIG_SND_VX222 is not set
1082# CONFIG_SND_YMFPCI is not set 1114# CONFIG_SND_YMFPCI is not set
1083# CONFIG_SND_AC97_POWER_SAVE is not set 1115CONFIG_SND_PPC=y
1084 1116CONFIG_SND_USB=y
1085#
1086# ALSA PowerMac devices
1087#
1088
1089#
1090# ALSA PowerPC devices
1091#
1092
1093#
1094# USB devices
1095#
1096# CONFIG_SND_USB_AUDIO is not set 1117# CONFIG_SND_USB_AUDIO is not set
1097# CONFIG_SND_USB_USX2Y is not set 1118# CONFIG_SND_USB_USX2Y is not set
1098# CONFIG_SND_USB_CAIAQ is not set 1119# CONFIG_SND_USB_CAIAQ is not set
1099
1100#
1101# System on Chip audio support
1102#
1103# CONFIG_SND_SOC is not set 1120# CONFIG_SND_SOC is not set
1104
1105#
1106# ALSA SoC audio for Freescale SOCs
1107#
1108
1109#
1110# SoC Audio for the Texas Instruments OMAP
1111#
1112
1113#
1114# Open Sound System
1115#
1116# CONFIG_SOUND_PRIME is not set 1121# CONFIG_SOUND_PRIME is not set
1117CONFIG_AC97_BUS=y 1122CONFIG_AC97_BUS=y
1118CONFIG_HID_SUPPORT=y 1123CONFIG_HID_SUPPORT=y
@@ -1144,6 +1149,7 @@ CONFIG_USB_DEVICE_CLASS=y
1144# CONFIG_USB_OTG is not set 1149# CONFIG_USB_OTG is not set
1145# CONFIG_USB_OTG_WHITELIST is not set 1150# CONFIG_USB_OTG_WHITELIST is not set
1146# CONFIG_USB_OTG_BLACKLIST_HUB is not set 1151# CONFIG_USB_OTG_BLACKLIST_HUB is not set
1152CONFIG_USB_MON=y
1147 1153
1148# 1154#
1149# USB Host Controller Drivers 1155# USB Host Controller Drivers
@@ -1195,6 +1201,7 @@ CONFIG_USB_STORAGE=y
1195# CONFIG_USB_STORAGE_ALAUDA is not set 1201# CONFIG_USB_STORAGE_ALAUDA is not set
1196# CONFIG_USB_STORAGE_ONETOUCH is not set 1202# CONFIG_USB_STORAGE_ONETOUCH is not set
1197# CONFIG_USB_STORAGE_KARMA is not set 1203# CONFIG_USB_STORAGE_KARMA is not set
1204# CONFIG_USB_STORAGE_SIERRA is not set
1198# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set 1205# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
1199# CONFIG_USB_LIBUSUAL is not set 1206# CONFIG_USB_LIBUSUAL is not set
1200 1207
@@ -1203,7 +1210,6 @@ CONFIG_USB_STORAGE=y
1203# 1210#
1204# CONFIG_USB_MDC800 is not set 1211# CONFIG_USB_MDC800 is not set
1205# CONFIG_USB_MICROTEK is not set 1212# CONFIG_USB_MICROTEK is not set
1206CONFIG_USB_MON=y
1207 1213
1208# 1214#
1209# USB port drivers 1215# USB port drivers
@@ -1216,7 +1222,6 @@ CONFIG_USB_MON=y
1216# CONFIG_USB_EMI62 is not set 1222# CONFIG_USB_EMI62 is not set
1217# CONFIG_USB_EMI26 is not set 1223# CONFIG_USB_EMI26 is not set
1218# CONFIG_USB_ADUTUX is not set 1224# CONFIG_USB_ADUTUX is not set
1219# CONFIG_USB_AUERSWALD is not set
1220# CONFIG_USB_RIO500 is not set 1225# CONFIG_USB_RIO500 is not set
1221# CONFIG_USB_LEGOTOWER is not set 1226# CONFIG_USB_LEGOTOWER is not set
1222# CONFIG_USB_LCD is not set 1227# CONFIG_USB_LCD is not set
@@ -1270,6 +1275,7 @@ CONFIG_RTC_INTF_DEV=y
1270# CONFIG_RTC_DRV_PCF8583 is not set 1275# CONFIG_RTC_DRV_PCF8583 is not set
1271# CONFIG_RTC_DRV_M41T80 is not set 1276# CONFIG_RTC_DRV_M41T80 is not set
1272# CONFIG_RTC_DRV_S35390A is not set 1277# CONFIG_RTC_DRV_S35390A is not set
1278# CONFIG_RTC_DRV_FM3130 is not set
1273 1279
1274# 1280#
1275# SPI RTC drivers 1281# SPI RTC drivers
@@ -1368,6 +1374,7 @@ CONFIG_EFS_FS=m
1368CONFIG_CRAMFS=y 1374CONFIG_CRAMFS=y
1369CONFIG_VXFS_FS=m 1375CONFIG_VXFS_FS=m
1370# CONFIG_MINIX_FS is not set 1376# CONFIG_MINIX_FS is not set
1377# CONFIG_OMFS_FS is not set
1371CONFIG_HPFS_FS=m 1378CONFIG_HPFS_FS=m
1372CONFIG_QNX4FS_FS=m 1379CONFIG_QNX4FS_FS=m
1373# CONFIG_ROMFS_FS is not set 1380# CONFIG_ROMFS_FS is not set
@@ -1380,17 +1387,16 @@ CONFIG_NFS_FS=y
1380CONFIG_NFS_V3=y 1387CONFIG_NFS_V3=y
1381# CONFIG_NFS_V3_ACL is not set 1388# CONFIG_NFS_V3_ACL is not set
1382CONFIG_NFS_V4=y 1389CONFIG_NFS_V4=y
1390CONFIG_ROOT_NFS=y
1383CONFIG_NFSD=y 1391CONFIG_NFSD=y
1384# CONFIG_NFSD_V3 is not set 1392# CONFIG_NFSD_V3 is not set
1385# CONFIG_NFSD_V4 is not set 1393# CONFIG_NFSD_V4 is not set
1386CONFIG_ROOT_NFS=y
1387CONFIG_LOCKD=y 1394CONFIG_LOCKD=y
1388CONFIG_LOCKD_V4=y 1395CONFIG_LOCKD_V4=y
1389CONFIG_EXPORTFS=y 1396CONFIG_EXPORTFS=y
1390CONFIG_NFS_COMMON=y 1397CONFIG_NFS_COMMON=y
1391CONFIG_SUNRPC=y 1398CONFIG_SUNRPC=y
1392CONFIG_SUNRPC_GSS=y 1399CONFIG_SUNRPC_GSS=y
1393# CONFIG_SUNRPC_BIND34 is not set
1394CONFIG_RPCSEC_GSS_KRB5=y 1400CONFIG_RPCSEC_GSS_KRB5=y
1395# CONFIG_RPCSEC_GSS_SPKM3 is not set 1401# CONFIG_RPCSEC_GSS_SPKM3 is not set
1396# CONFIG_SMB_FS is not set 1402# CONFIG_SMB_FS is not set
@@ -1469,6 +1475,7 @@ CONFIG_BITREVERSE=y
1469# CONFIG_GENERIC_FIND_FIRST_BIT is not set 1475# CONFIG_GENERIC_FIND_FIRST_BIT is not set
1470# CONFIG_CRC_CCITT is not set 1476# CONFIG_CRC_CCITT is not set
1471# CONFIG_CRC16 is not set 1477# CONFIG_CRC16 is not set
1478CONFIG_CRC_T10DIF=y
1472CONFIG_CRC_ITU_T=m 1479CONFIG_CRC_ITU_T=m
1473CONFIG_CRC32=y 1480CONFIG_CRC32=y
1474# CONFIG_CRC7 is not set 1481# CONFIG_CRC7 is not set
@@ -1494,6 +1501,8 @@ CONFIG_FRAME_WARN=1024
1494CONFIG_DEBUG_KERNEL=y 1501CONFIG_DEBUG_KERNEL=y
1495# CONFIG_DEBUG_SHIRQ is not set 1502# CONFIG_DEBUG_SHIRQ is not set
1496CONFIG_DETECT_SOFTLOCKUP=y 1503CONFIG_DETECT_SOFTLOCKUP=y
1504# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
1505CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
1497CONFIG_SCHED_DEBUG=y 1506CONFIG_SCHED_DEBUG=y
1498# CONFIG_SCHEDSTATS is not set 1507# CONFIG_SCHEDSTATS is not set
1499# CONFIG_TIMER_STATS is not set 1508# CONFIG_TIMER_STATS is not set
@@ -1512,17 +1521,29 @@ CONFIG_SCHED_DEBUG=y
1512CONFIG_DEBUG_INFO=y 1521CONFIG_DEBUG_INFO=y
1513# CONFIG_DEBUG_VM is not set 1522# CONFIG_DEBUG_VM is not set
1514# CONFIG_DEBUG_WRITECOUNT is not set 1523# CONFIG_DEBUG_WRITECOUNT is not set
1524# CONFIG_DEBUG_MEMORY_INIT is not set
1515# CONFIG_DEBUG_LIST is not set 1525# CONFIG_DEBUG_LIST is not set
1516# CONFIG_DEBUG_SG is not set 1526# CONFIG_DEBUG_SG is not set
1517# CONFIG_BOOT_PRINTK_DELAY is not set 1527# CONFIG_BOOT_PRINTK_DELAY is not set
1518# CONFIG_RCU_TORTURE_TEST is not set 1528# CONFIG_RCU_TORTURE_TEST is not set
1519# CONFIG_BACKTRACE_SELF_TEST is not set 1529# CONFIG_BACKTRACE_SELF_TEST is not set
1520# CONFIG_FAULT_INJECTION is not set 1530# CONFIG_FAULT_INJECTION is not set
1531# CONFIG_LATENCYTOP is not set
1532CONFIG_SYSCTL_SYSCALL_CHECK=y
1533CONFIG_HAVE_FTRACE=y
1534CONFIG_HAVE_DYNAMIC_FTRACE=y
1535# CONFIG_FTRACE is not set
1536# CONFIG_SCHED_TRACER is not set
1537# CONFIG_CONTEXT_SWITCH_TRACER is not set
1521# CONFIG_SAMPLES is not set 1538# CONFIG_SAMPLES is not set
1539CONFIG_HAVE_ARCH_KGDB=y
1540# CONFIG_KGDB is not set
1522# CONFIG_DEBUG_STACKOVERFLOW is not set 1541# CONFIG_DEBUG_STACKOVERFLOW is not set
1523# CONFIG_DEBUG_STACK_USAGE is not set 1542# CONFIG_DEBUG_STACK_USAGE is not set
1524# CONFIG_DEBUG_PAGEALLOC is not set 1543# CONFIG_DEBUG_PAGEALLOC is not set
1525# CONFIG_DEBUGGER is not set 1544# CONFIG_CODE_PATCHING_SELFTEST is not set
1545# CONFIG_FTR_FIXUP_SELFTEST is not set
1546# CONFIG_XMON is not set
1526# CONFIG_IRQSTACKS is not set 1547# CONFIG_IRQSTACKS is not set
1527# CONFIG_BDI_SWITCH is not set 1548# CONFIG_BDI_SWITCH is not set
1528# CONFIG_PPC_EARLY_DEBUG is not set 1549# CONFIG_PPC_EARLY_DEBUG is not set
@@ -1539,13 +1560,14 @@ CONFIG_CRYPTO=y
1539# Crypto core or helper 1560# Crypto core or helper
1540# 1561#
1541CONFIG_CRYPTO_ALGAPI=y 1562CONFIG_CRYPTO_ALGAPI=y
1563CONFIG_CRYPTO_AEAD=y
1542CONFIG_CRYPTO_BLKCIPHER=y 1564CONFIG_CRYPTO_BLKCIPHER=y
1543CONFIG_CRYPTO_HASH=y 1565CONFIG_CRYPTO_HASH=y
1544CONFIG_CRYPTO_MANAGER=y 1566CONFIG_CRYPTO_MANAGER=y
1545# CONFIG_CRYPTO_GF128MUL is not set 1567# CONFIG_CRYPTO_GF128MUL is not set
1546# CONFIG_CRYPTO_NULL is not set 1568# CONFIG_CRYPTO_NULL is not set
1547# CONFIG_CRYPTO_CRYPTD is not set 1569# CONFIG_CRYPTO_CRYPTD is not set
1548# CONFIG_CRYPTO_AUTHENC is not set 1570CONFIG_CRYPTO_AUTHENC=y
1549# CONFIG_CRYPTO_TEST is not set 1571# CONFIG_CRYPTO_TEST is not set
1550 1572
1551# 1573#
@@ -1579,6 +1601,10 @@ CONFIG_CRYPTO_HMAC=y
1579# CONFIG_CRYPTO_MD4 is not set 1601# CONFIG_CRYPTO_MD4 is not set
1580CONFIG_CRYPTO_MD5=y 1602CONFIG_CRYPTO_MD5=y
1581# CONFIG_CRYPTO_MICHAEL_MIC is not set 1603# CONFIG_CRYPTO_MICHAEL_MIC is not set
1604# CONFIG_CRYPTO_RMD128 is not set
1605# CONFIG_CRYPTO_RMD160 is not set
1606# CONFIG_CRYPTO_RMD256 is not set
1607# CONFIG_CRYPTO_RMD320 is not set
1582CONFIG_CRYPTO_SHA1=m 1608CONFIG_CRYPTO_SHA1=m
1583# CONFIG_CRYPTO_SHA256 is not set 1609# CONFIG_CRYPTO_SHA256 is not set
1584# CONFIG_CRYPTO_SHA512 is not set 1610# CONFIG_CRYPTO_SHA512 is not set
@@ -1611,5 +1637,6 @@ CONFIG_CRYPTO_DES=y
1611# CONFIG_CRYPTO_LZO is not set 1637# CONFIG_CRYPTO_LZO is not set
1612CONFIG_CRYPTO_HW=y 1638CONFIG_CRYPTO_HW=y
1613# CONFIG_CRYPTO_DEV_HIFN_795X is not set 1639# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1640CONFIG_CRYPTO_DEV_TALITOS=y
1614# CONFIG_PPC_CLOCK is not set 1641# CONFIG_PPC_CLOCK is not set
1615# CONFIG_VIRTUALIZATION is not set 1642# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/configs/85xx/mpc85xx_cds_defconfig b/arch/powerpc/configs/85xx/mpc85xx_cds_defconfig
index b09f0032a10b..97f3c4fe440b 100644
--- a/arch/powerpc/configs/85xx/mpc85xx_cds_defconfig
+++ b/arch/powerpc/configs/85xx/mpc85xx_cds_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc5 3# Linux kernel version: 2.6.27-rc4
4# Mon Jun 9 08:52:36 2008 4# Thu Aug 21 00:52:34 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -15,6 +15,7 @@ CONFIG_PPC_85xx=y
15# CONFIG_44x is not set 15# CONFIG_44x is not set
16# CONFIG_E200 is not set 16# CONFIG_E200 is not set
17CONFIG_E500=y 17CONFIG_E500=y
18# CONFIG_PPC_E500MC is not set
18CONFIG_BOOKE=y 19CONFIG_BOOKE=y
19CONFIG_FSL_BOOKE=y 20CONFIG_FSL_BOOKE=y
20CONFIG_FSL_EMB_PERFMON=y 21CONFIG_FSL_EMB_PERFMON=y
@@ -33,6 +34,7 @@ CONFIG_GENERIC_HARDIRQS=y
33# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set 34# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
34CONFIG_IRQ_PER_CPU=y 35CONFIG_IRQ_PER_CPU=y
35CONFIG_STACKTRACE_SUPPORT=y 36CONFIG_STACKTRACE_SUPPORT=y
37CONFIG_HAVE_LATENCYTOP_SUPPORT=y
36CONFIG_LOCKDEP_SUPPORT=y 38CONFIG_LOCKDEP_SUPPORT=y
37CONFIG_RWSEM_XCHGADD_ALGORITHM=y 39CONFIG_RWSEM_XCHGADD_ALGORITHM=y
38CONFIG_ARCH_HAS_ILOG2_U32=y 40CONFIG_ARCH_HAS_ILOG2_U32=y
@@ -89,7 +91,6 @@ CONFIG_INITRAMFS_SOURCE=""
89CONFIG_SYSCTL=y 91CONFIG_SYSCTL=y
90CONFIG_EMBEDDED=y 92CONFIG_EMBEDDED=y
91CONFIG_SYSCTL_SYSCALL=y 93CONFIG_SYSCTL_SYSCALL=y
92CONFIG_SYSCTL_SYSCALL_CHECK=y
93CONFIG_KALLSYMS=y 94CONFIG_KALLSYMS=y
94# CONFIG_KALLSYMS_ALL is not set 95# CONFIG_KALLSYMS_ALL is not set
95# CONFIG_KALLSYMS_EXTRA_PASS is not set 96# CONFIG_KALLSYMS_EXTRA_PASS is not set
@@ -114,10 +115,16 @@ CONFIG_SLUB=y
114# CONFIG_PROFILING is not set 115# CONFIG_PROFILING is not set
115# CONFIG_MARKERS is not set 116# CONFIG_MARKERS is not set
116CONFIG_HAVE_OPROFILE=y 117CONFIG_HAVE_OPROFILE=y
118CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
119CONFIG_HAVE_IOREMAP_PROT=y
117CONFIG_HAVE_KPROBES=y 120CONFIG_HAVE_KPROBES=y
118CONFIG_HAVE_KRETPROBES=y 121CONFIG_HAVE_KRETPROBES=y
122CONFIG_HAVE_ARCH_TRACEHOOK=y
119# CONFIG_HAVE_DMA_ATTRS is not set 123# CONFIG_HAVE_DMA_ATTRS is not set
124# CONFIG_USE_GENERIC_SMP_HELPERS is not set
125# CONFIG_HAVE_CLK is not set
120CONFIG_PROC_PAGE_MONITOR=y 126CONFIG_PROC_PAGE_MONITOR=y
127# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
121CONFIG_SLABINFO=y 128CONFIG_SLABINFO=y
122CONFIG_RT_MUTEXES=y 129CONFIG_RT_MUTEXES=y
123# CONFIG_TINY_SHMEM is not set 130# CONFIG_TINY_SHMEM is not set
@@ -128,6 +135,7 @@ CONFIG_BLOCK=y
128# CONFIG_BLK_DEV_IO_TRACE is not set 135# CONFIG_BLK_DEV_IO_TRACE is not set
129# CONFIG_LSF is not set 136# CONFIG_LSF is not set
130# CONFIG_BLK_DEV_BSG is not set 137# CONFIG_BLK_DEV_BSG is not set
138# CONFIG_BLK_DEV_INTEGRITY is not set
131 139
132# 140#
133# IO Schedulers 141# IO Schedulers
@@ -146,8 +154,6 @@ CONFIG_CLASSIC_RCU=y
146# 154#
147# Platform support 155# Platform support
148# 156#
149# CONFIG_PPC_MPC512x is not set
150# CONFIG_PPC_MPC5121 is not set
151# CONFIG_PPC_CELL is not set 157# CONFIG_PPC_CELL is not set
152# CONFIG_PPC_CELL_NATIVE is not set 158# CONFIG_PPC_CELL_NATIVE is not set
153# CONFIG_PQ2ADS is not set 159# CONFIG_PQ2ADS is not set
@@ -156,11 +162,13 @@ CONFIG_MPC85xx=y
156# CONFIG_MPC8560_ADS is not set 162# CONFIG_MPC8560_ADS is not set
157CONFIG_MPC85xx_CDS=y 163CONFIG_MPC85xx_CDS=y
158# CONFIG_MPC85xx_MDS is not set 164# CONFIG_MPC85xx_MDS is not set
165# CONFIG_MPC8536_DS is not set
159# CONFIG_MPC85xx_DS is not set 166# CONFIG_MPC85xx_DS is not set
160# CONFIG_KSI8560 is not set 167# CONFIG_KSI8560 is not set
161# CONFIG_STX_GP3 is not set 168# CONFIG_STX_GP3 is not set
162# CONFIG_TQM8540 is not set 169# CONFIG_TQM8540 is not set
163# CONFIG_TQM8541 is not set 170# CONFIG_TQM8541 is not set
171# CONFIG_TQM8548 is not set
164# CONFIG_TQM8555 is not set 172# CONFIG_TQM8555 is not set
165# CONFIG_TQM8560 is not set 173# CONFIG_TQM8560 is not set
166# CONFIG_SBC8548 is not set 174# CONFIG_SBC8548 is not set
@@ -192,7 +200,7 @@ CONFIG_HZ_250=y
192# CONFIG_HZ_300 is not set 200# CONFIG_HZ_300 is not set
193# CONFIG_HZ_1000 is not set 201# CONFIG_HZ_1000 is not set
194CONFIG_HZ=250 202CONFIG_HZ=250
195# CONFIG_SCHED_HRTICK is not set 203CONFIG_SCHED_HRTICK=y
196CONFIG_PREEMPT_NONE=y 204CONFIG_PREEMPT_NONE=y
197# CONFIG_PREEMPT_VOLUNTARY is not set 205# CONFIG_PREEMPT_VOLUNTARY is not set
198# CONFIG_PREEMPT is not set 206# CONFIG_PREEMPT is not set
@@ -215,6 +223,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
215# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set 223# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
216CONFIG_PAGEFLAGS_EXTENDED=y 224CONFIG_PAGEFLAGS_EXTENDED=y
217CONFIG_SPLIT_PTLOCK_CPUS=4 225CONFIG_SPLIT_PTLOCK_CPUS=4
226CONFIG_MIGRATION=y
218# CONFIG_RESOURCES_64BIT is not set 227# CONFIG_RESOURCES_64BIT is not set
219CONFIG_ZONE_DMA_FLAG=1 228CONFIG_ZONE_DMA_FLAG=1
220CONFIG_BOUNCE=y 229CONFIG_BOUNCE=y
@@ -222,6 +231,7 @@ CONFIG_VIRT_TO_BUS=y
222CONFIG_FORCE_MAX_ZONEORDER=11 231CONFIG_FORCE_MAX_ZONEORDER=11
223CONFIG_PROC_DEVICETREE=y 232CONFIG_PROC_DEVICETREE=y
224# CONFIG_CMDLINE_BOOL is not set 233# CONFIG_CMDLINE_BOOL is not set
234CONFIG_EXTRA_TARGETS=""
225# CONFIG_PM is not set 235# CONFIG_PM is not set
226# CONFIG_SECCOMP is not set 236# CONFIG_SECCOMP is not set
227CONFIG_ISA_DMA_API=y 237CONFIG_ISA_DMA_API=y
@@ -233,6 +243,7 @@ CONFIG_ZONE_DMA=y
233CONFIG_PPC_INDIRECT_PCI=y 243CONFIG_PPC_INDIRECT_PCI=y
234CONFIG_FSL_SOC=y 244CONFIG_FSL_SOC=y
235CONFIG_FSL_PCI=y 245CONFIG_FSL_PCI=y
246CONFIG_PPC_PCI_CHOICE=y
236CONFIG_PCI=y 247CONFIG_PCI=y
237CONFIG_PCI_DOMAINS=y 248CONFIG_PCI_DOMAINS=y
238CONFIG_PCI_SYSCALL=y 249CONFIG_PCI_SYSCALL=y
@@ -259,10 +270,6 @@ CONFIG_KERNEL_START=0xc0000000
259CONFIG_PHYSICAL_START=0x00000000 270CONFIG_PHYSICAL_START=0x00000000
260CONFIG_PHYSICAL_ALIGN=0x10000000 271CONFIG_PHYSICAL_ALIGN=0x10000000
261CONFIG_TASK_SIZE=0xc0000000 272CONFIG_TASK_SIZE=0xc0000000
262
263#
264# Networking
265#
266CONFIG_NET=y 273CONFIG_NET=y
267 274
268# 275#
@@ -379,20 +386,22 @@ CONFIG_BLK_DEV_RAM_SIZE=32768
379# CONFIG_BLK_DEV_XIP is not set 386# CONFIG_BLK_DEV_XIP is not set
380# CONFIG_CDROM_PKTCDVD is not set 387# CONFIG_CDROM_PKTCDVD is not set
381# CONFIG_ATA_OVER_ETH is not set 388# CONFIG_ATA_OVER_ETH is not set
389# CONFIG_BLK_DEV_HD is not set
382CONFIG_MISC_DEVICES=y 390CONFIG_MISC_DEVICES=y
383# CONFIG_PHANTOM is not set 391# CONFIG_PHANTOM is not set
384# CONFIG_EEPROM_93CX6 is not set 392# CONFIG_EEPROM_93CX6 is not set
385# CONFIG_SGI_IOC4 is not set 393# CONFIG_SGI_IOC4 is not set
386# CONFIG_TIFM_CORE is not set 394# CONFIG_TIFM_CORE is not set
387# CONFIG_ENCLOSURE_SERVICES is not set 395# CONFIG_ENCLOSURE_SERVICES is not set
396# CONFIG_HP_ILO is not set
388CONFIG_HAVE_IDE=y 397CONFIG_HAVE_IDE=y
389CONFIG_IDE=y 398CONFIG_IDE=y
390CONFIG_IDE_MAX_HWIFS=4
391CONFIG_BLK_DEV_IDE=y 399CONFIG_BLK_DEV_IDE=y
392 400
393# 401#
394# Please see Documentation/ide/ide.txt for help/info on IDE drives 402# Please see Documentation/ide/ide.txt for help/info on IDE drives
395# 403#
404CONFIG_IDE_TIMINGS=y
396# CONFIG_BLK_DEV_IDE_SATA is not set 405# CONFIG_BLK_DEV_IDE_SATA is not set
397# CONFIG_BLK_DEV_IDEDISK is not set 406# CONFIG_BLK_DEV_IDEDISK is not set
398# CONFIG_IDEDISK_MULTI_MODE is not set 407# CONFIG_IDEDISK_MULTI_MODE is not set
@@ -405,7 +414,6 @@ CONFIG_IDE_PROC_FS=y
405# 414#
406# IDE chipset support/bugfixes 415# IDE chipset support/bugfixes
407# 416#
408CONFIG_IDE_GENERIC=y
409# CONFIG_BLK_DEV_PLATFORM is not set 417# CONFIG_BLK_DEV_PLATFORM is not set
410CONFIG_BLK_DEV_IDEDMA_SFF=y 418CONFIG_BLK_DEV_IDEDMA_SFF=y
411 419
@@ -423,10 +431,8 @@ CONFIG_BLK_DEV_IDEDMA_PCI=y
423# CONFIG_BLK_DEV_AMD74XX is not set 431# CONFIG_BLK_DEV_AMD74XX is not set
424# CONFIG_BLK_DEV_CMD64X is not set 432# CONFIG_BLK_DEV_CMD64X is not set
425# CONFIG_BLK_DEV_TRIFLEX is not set 433# CONFIG_BLK_DEV_TRIFLEX is not set
426# CONFIG_BLK_DEV_CY82C693 is not set
427# CONFIG_BLK_DEV_CS5520 is not set 434# CONFIG_BLK_DEV_CS5520 is not set
428# CONFIG_BLK_DEV_CS5530 is not set 435# CONFIG_BLK_DEV_CS5530 is not set
429# CONFIG_BLK_DEV_HPT34X is not set
430# CONFIG_BLK_DEV_HPT366 is not set 436# CONFIG_BLK_DEV_HPT366 is not set
431# CONFIG_BLK_DEV_JMICRON is not set 437# CONFIG_BLK_DEV_JMICRON is not set
432# CONFIG_BLK_DEV_SC1200 is not set 438# CONFIG_BLK_DEV_SC1200 is not set
@@ -444,8 +450,6 @@ CONFIG_BLK_DEV_IDEDMA_PCI=y
444CONFIG_BLK_DEV_VIA82CXXX=y 450CONFIG_BLK_DEV_VIA82CXXX=y
445# CONFIG_BLK_DEV_TC86C001 is not set 451# CONFIG_BLK_DEV_TC86C001 is not set
446CONFIG_BLK_DEV_IDEDMA=y 452CONFIG_BLK_DEV_IDEDMA=y
447# CONFIG_BLK_DEV_HD_ONLY is not set
448# CONFIG_BLK_DEV_HD is not set
449 453
450# 454#
451# SCSI device support 455# SCSI device support
@@ -461,12 +465,15 @@ CONFIG_BLK_DEV_IDEDMA=y
461# 465#
462# IEEE 1394 (FireWire) support 466# IEEE 1394 (FireWire) support
463# 467#
468
469#
470# Enable only one of the two stacks, unless you know what you are doing
471#
464# CONFIG_FIREWIRE is not set 472# CONFIG_FIREWIRE is not set
465# CONFIG_IEEE1394 is not set 473# CONFIG_IEEE1394 is not set
466# CONFIG_I2O is not set 474# CONFIG_I2O is not set
467# CONFIG_MACINTOSH_DRIVERS is not set 475# CONFIG_MACINTOSH_DRIVERS is not set
468CONFIG_NETDEVICES=y 476CONFIG_NETDEVICES=y
469# CONFIG_NETDEVICES_MULTIQUEUE is not set
470# CONFIG_DUMMY is not set 477# CONFIG_DUMMY is not set
471# CONFIG_BONDING is not set 478# CONFIG_BONDING is not set
472# CONFIG_MACVLAN is not set 479# CONFIG_MACVLAN is not set
@@ -509,10 +516,8 @@ CONFIG_NETDEV_1000=y
509# CONFIG_ACENIC is not set 516# CONFIG_ACENIC is not set
510# CONFIG_DL2K is not set 517# CONFIG_DL2K is not set
511CONFIG_E1000=y 518CONFIG_E1000=y
512CONFIG_E1000_NAPI=y
513# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set 519# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
514# CONFIG_E1000E is not set 520# CONFIG_E1000E is not set
515# CONFIG_E1000E_ENABLED is not set
516# CONFIG_IP1000 is not set 521# CONFIG_IP1000 is not set
517# CONFIG_IGB is not set 522# CONFIG_IGB is not set
518# CONFIG_NS83820 is not set 523# CONFIG_NS83820 is not set
@@ -526,9 +531,9 @@ CONFIG_E1000_NAPI=y
526# CONFIG_TIGON3 is not set 531# CONFIG_TIGON3 is not set
527# CONFIG_BNX2 is not set 532# CONFIG_BNX2 is not set
528CONFIG_GIANFAR=y 533CONFIG_GIANFAR=y
529CONFIG_GFAR_NAPI=y
530# CONFIG_QLA3XXX is not set 534# CONFIG_QLA3XXX is not set
531# CONFIG_ATL1 is not set 535# CONFIG_ATL1 is not set
536# CONFIG_ATL1E is not set
532CONFIG_NETDEV_10000=y 537CONFIG_NETDEV_10000=y
533# CONFIG_CHELSIO_T1 is not set 538# CONFIG_CHELSIO_T1 is not set
534# CONFIG_CHELSIO_T3 is not set 539# CONFIG_CHELSIO_T3 is not set
@@ -634,6 +639,8 @@ CONFIG_GEN_RTC=y
634CONFIG_DEVPORT=y 639CONFIG_DEVPORT=y
635# CONFIG_I2C is not set 640# CONFIG_I2C is not set
636# CONFIG_SPI is not set 641# CONFIG_SPI is not set
642CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
643# CONFIG_GPIOLIB is not set
637# CONFIG_W1 is not set 644# CONFIG_W1 is not set
638# CONFIG_POWER_SUPPLY is not set 645# CONFIG_POWER_SUPPLY is not set
639CONFIG_HWMON=y 646CONFIG_HWMON=y
@@ -654,6 +661,7 @@ CONFIG_HWMON=y
654# CONFIG_SENSORS_W83627EHF is not set 661# CONFIG_SENSORS_W83627EHF is not set
655# CONFIG_HWMON_DEBUG_CHIP is not set 662# CONFIG_HWMON_DEBUG_CHIP is not set
656# CONFIG_THERMAL is not set 663# CONFIG_THERMAL is not set
664# CONFIG_THERMAL_HWMON is not set
657# CONFIG_WATCHDOG is not set 665# CONFIG_WATCHDOG is not set
658 666
659# 667#
@@ -665,8 +673,10 @@ CONFIG_SSB_POSSIBLE=y
665# 673#
666# Multifunction device drivers 674# Multifunction device drivers
667# 675#
676# CONFIG_MFD_CORE is not set
668# CONFIG_MFD_SM501 is not set 677# CONFIG_MFD_SM501 is not set
669# CONFIG_HTC_PASIC3 is not set 678# CONFIG_HTC_PASIC3 is not set
679# CONFIG_MFD_TMIO is not set
670 680
671# 681#
672# Multimedia devices 682# Multimedia devices
@@ -698,10 +708,6 @@ CONFIG_VIDEO_OUTPUT_CONTROL=y
698# Display device support 708# Display device support
699# 709#
700# CONFIG_DISPLAY_SUPPORT is not set 710# CONFIG_DISPLAY_SUPPORT is not set
701
702#
703# Sound
704#
705# CONFIG_SOUND is not set 711# CONFIG_SOUND is not set
706CONFIG_HID_SUPPORT=y 712CONFIG_HID_SUPPORT=y
707CONFIG_HID=y 713CONFIG_HID=y
@@ -716,6 +722,10 @@ CONFIG_USB_ARCH_HAS_EHCI=y
716# CONFIG_USB_OTG_BLACKLIST_HUB is not set 722# CONFIG_USB_OTG_BLACKLIST_HUB is not set
717 723
718# 724#
725# Enable Host or Gadget support to see Inventra options
726#
727
728#
719# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 729# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
720# 730#
721# CONFIG_USB_GADGET is not set 731# CONFIG_USB_GADGET is not set
@@ -793,6 +803,7 @@ CONFIG_TMPFS=y
793# CONFIG_CRAMFS is not set 803# CONFIG_CRAMFS is not set
794# CONFIG_VXFS_FS is not set 804# CONFIG_VXFS_FS is not set
795# CONFIG_MINIX_FS is not set 805# CONFIG_MINIX_FS is not set
806# CONFIG_OMFS_FS is not set
796# CONFIG_HPFS_FS is not set 807# CONFIG_HPFS_FS is not set
797# CONFIG_QNX4FS_FS is not set 808# CONFIG_QNX4FS_FS is not set
798# CONFIG_ROMFS_FS is not set 809# CONFIG_ROMFS_FS is not set
@@ -802,12 +813,11 @@ CONFIG_NETWORK_FILESYSTEMS=y
802CONFIG_NFS_FS=y 813CONFIG_NFS_FS=y
803# CONFIG_NFS_V3 is not set 814# CONFIG_NFS_V3 is not set
804# CONFIG_NFS_V4 is not set 815# CONFIG_NFS_V4 is not set
805# CONFIG_NFSD is not set
806CONFIG_ROOT_NFS=y 816CONFIG_ROOT_NFS=y
817# CONFIG_NFSD is not set
807CONFIG_LOCKD=y 818CONFIG_LOCKD=y
808CONFIG_NFS_COMMON=y 819CONFIG_NFS_COMMON=y
809CONFIG_SUNRPC=y 820CONFIG_SUNRPC=y
810# CONFIG_SUNRPC_BIND34 is not set
811# CONFIG_RPCSEC_GSS_KRB5 is not set 821# CONFIG_RPCSEC_GSS_KRB5 is not set
812# CONFIG_RPCSEC_GSS_SPKM3 is not set 822# CONFIG_RPCSEC_GSS_SPKM3 is not set
813# CONFIG_SMB_FS is not set 823# CONFIG_SMB_FS is not set
@@ -843,6 +853,7 @@ CONFIG_BITREVERSE=y
843# CONFIG_GENERIC_FIND_FIRST_BIT is not set 853# CONFIG_GENERIC_FIND_FIRST_BIT is not set
844# CONFIG_CRC_CCITT is not set 854# CONFIG_CRC_CCITT is not set
845# CONFIG_CRC16 is not set 855# CONFIG_CRC16 is not set
856# CONFIG_CRC_T10DIF is not set
846# CONFIG_CRC_ITU_T is not set 857# CONFIG_CRC_ITU_T is not set
847CONFIG_CRC32=y 858CONFIG_CRC32=y
848# CONFIG_CRC7 is not set 859# CONFIG_CRC7 is not set
@@ -867,6 +878,8 @@ CONFIG_FRAME_WARN=1024
867CONFIG_DEBUG_KERNEL=y 878CONFIG_DEBUG_KERNEL=y
868# CONFIG_DEBUG_SHIRQ is not set 879# CONFIG_DEBUG_SHIRQ is not set
869CONFIG_DETECT_SOFTLOCKUP=y 880CONFIG_DETECT_SOFTLOCKUP=y
881# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
882CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
870CONFIG_SCHED_DEBUG=y 883CONFIG_SCHED_DEBUG=y
871# CONFIG_SCHEDSTATS is not set 884# CONFIG_SCHEDSTATS is not set
872# CONFIG_TIMER_STATS is not set 885# CONFIG_TIMER_STATS is not set
@@ -884,16 +897,29 @@ CONFIG_DEBUG_MUTEXES=y
884# CONFIG_DEBUG_INFO is not set 897# CONFIG_DEBUG_INFO is not set
885# CONFIG_DEBUG_VM is not set 898# CONFIG_DEBUG_VM is not set
886# CONFIG_DEBUG_WRITECOUNT is not set 899# CONFIG_DEBUG_WRITECOUNT is not set
900# CONFIG_DEBUG_MEMORY_INIT is not set
887# CONFIG_DEBUG_LIST is not set 901# CONFIG_DEBUG_LIST is not set
888# CONFIG_DEBUG_SG is not set 902# CONFIG_DEBUG_SG is not set
889# CONFIG_BOOT_PRINTK_DELAY is not set 903# CONFIG_BOOT_PRINTK_DELAY is not set
904# CONFIG_RCU_TORTURE_TEST is not set
890# CONFIG_BACKTRACE_SELF_TEST is not set 905# CONFIG_BACKTRACE_SELF_TEST is not set
891# CONFIG_FAULT_INJECTION is not set 906# CONFIG_FAULT_INJECTION is not set
907# CONFIG_LATENCYTOP is not set
908CONFIG_SYSCTL_SYSCALL_CHECK=y
909CONFIG_HAVE_FTRACE=y
910CONFIG_HAVE_DYNAMIC_FTRACE=y
911# CONFIG_FTRACE is not set
912# CONFIG_SCHED_TRACER is not set
913# CONFIG_CONTEXT_SWITCH_TRACER is not set
892# CONFIG_SAMPLES is not set 914# CONFIG_SAMPLES is not set
915CONFIG_HAVE_ARCH_KGDB=y
916# CONFIG_KGDB is not set
893# CONFIG_DEBUG_STACKOVERFLOW is not set 917# CONFIG_DEBUG_STACKOVERFLOW is not set
894# CONFIG_DEBUG_STACK_USAGE is not set 918# CONFIG_DEBUG_STACK_USAGE is not set
895# CONFIG_DEBUG_PAGEALLOC is not set 919# CONFIG_DEBUG_PAGEALLOC is not set
896# CONFIG_DEBUGGER is not set 920# CONFIG_CODE_PATCHING_SELFTEST is not set
921# CONFIG_FTR_FIXUP_SELFTEST is not set
922# CONFIG_XMON is not set
897# CONFIG_IRQSTACKS is not set 923# CONFIG_IRQSTACKS is not set
898# CONFIG_BDI_SWITCH is not set 924# CONFIG_BDI_SWITCH is not set
899# CONFIG_PPC_EARLY_DEBUG is not set 925# CONFIG_PPC_EARLY_DEBUG is not set
@@ -946,6 +972,10 @@ CONFIG_CRYPTO=y
946# CONFIG_CRYPTO_MD4 is not set 972# CONFIG_CRYPTO_MD4 is not set
947# CONFIG_CRYPTO_MD5 is not set 973# CONFIG_CRYPTO_MD5 is not set
948# CONFIG_CRYPTO_MICHAEL_MIC is not set 974# CONFIG_CRYPTO_MICHAEL_MIC is not set
975# CONFIG_CRYPTO_RMD128 is not set
976# CONFIG_CRYPTO_RMD160 is not set
977# CONFIG_CRYPTO_RMD256 is not set
978# CONFIG_CRYPTO_RMD320 is not set
949# CONFIG_CRYPTO_SHA1 is not set 979# CONFIG_CRYPTO_SHA1 is not set
950# CONFIG_CRYPTO_SHA256 is not set 980# CONFIG_CRYPTO_SHA256 is not set
951# CONFIG_CRYPTO_SHA512 is not set 981# CONFIG_CRYPTO_SHA512 is not set
@@ -978,5 +1008,6 @@ CONFIG_CRYPTO=y
978# CONFIG_CRYPTO_LZO is not set 1008# CONFIG_CRYPTO_LZO is not set
979CONFIG_CRYPTO_HW=y 1009CONFIG_CRYPTO_HW=y
980# CONFIG_CRYPTO_DEV_HIFN_795X is not set 1010# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1011# CONFIG_CRYPTO_DEV_TALITOS is not set
981# CONFIG_PPC_CLOCK is not set 1012# CONFIG_PPC_CLOCK is not set
982# CONFIG_VIRTUALIZATION is not set 1013# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/configs/85xx/sbc8548_defconfig b/arch/powerpc/configs/85xx/sbc8548_defconfig
index 24f7f44b4821..41cedc4b63f6 100644
--- a/arch/powerpc/configs/85xx/sbc8548_defconfig
+++ b/arch/powerpc/configs/85xx/sbc8548_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc5 3# Linux kernel version: 2.6.27-rc4
4# Mon Jun 9 08:52:37 2008 4# Thu Aug 21 00:52:35 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -15,6 +15,7 @@ CONFIG_PPC_85xx=y
15# CONFIG_44x is not set 15# CONFIG_44x is not set
16# CONFIG_E200 is not set 16# CONFIG_E200 is not set
17CONFIG_E500=y 17CONFIG_E500=y
18# CONFIG_PPC_E500MC is not set
18CONFIG_BOOKE=y 19CONFIG_BOOKE=y
19CONFIG_FSL_BOOKE=y 20CONFIG_FSL_BOOKE=y
20CONFIG_FSL_EMB_PERFMON=y 21CONFIG_FSL_EMB_PERFMON=y
@@ -33,6 +34,7 @@ CONFIG_GENERIC_HARDIRQS=y
33# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set 34# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
34CONFIG_IRQ_PER_CPU=y 35CONFIG_IRQ_PER_CPU=y
35CONFIG_STACKTRACE_SUPPORT=y 36CONFIG_STACKTRACE_SUPPORT=y
37CONFIG_HAVE_LATENCYTOP_SUPPORT=y
36CONFIG_LOCKDEP_SUPPORT=y 38CONFIG_LOCKDEP_SUPPORT=y
37CONFIG_RWSEM_XCHGADD_ALGORITHM=y 39CONFIG_RWSEM_XCHGADD_ALGORITHM=y
38CONFIG_ARCH_HAS_ILOG2_U32=y 40CONFIG_ARCH_HAS_ILOG2_U32=y
@@ -89,7 +91,6 @@ CONFIG_INITRAMFS_SOURCE=""
89CONFIG_SYSCTL=y 91CONFIG_SYSCTL=y
90CONFIG_EMBEDDED=y 92CONFIG_EMBEDDED=y
91CONFIG_SYSCTL_SYSCALL=y 93CONFIG_SYSCTL_SYSCALL=y
92CONFIG_SYSCTL_SYSCALL_CHECK=y
93CONFIG_KALLSYMS=y 94CONFIG_KALLSYMS=y
94# CONFIG_KALLSYMS_EXTRA_PASS is not set 95# CONFIG_KALLSYMS_EXTRA_PASS is not set
95CONFIG_HOTPLUG=y 96CONFIG_HOTPLUG=y
@@ -112,10 +113,16 @@ CONFIG_SLAB=y
112# CONFIG_PROFILING is not set 113# CONFIG_PROFILING is not set
113# CONFIG_MARKERS is not set 114# CONFIG_MARKERS is not set
114CONFIG_HAVE_OPROFILE=y 115CONFIG_HAVE_OPROFILE=y
116CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
117CONFIG_HAVE_IOREMAP_PROT=y
115CONFIG_HAVE_KPROBES=y 118CONFIG_HAVE_KPROBES=y
116CONFIG_HAVE_KRETPROBES=y 119CONFIG_HAVE_KRETPROBES=y
120CONFIG_HAVE_ARCH_TRACEHOOK=y
117# CONFIG_HAVE_DMA_ATTRS is not set 121# CONFIG_HAVE_DMA_ATTRS is not set
122# CONFIG_USE_GENERIC_SMP_HELPERS is not set
123# CONFIG_HAVE_CLK is not set
118CONFIG_PROC_PAGE_MONITOR=y 124CONFIG_PROC_PAGE_MONITOR=y
125# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
119CONFIG_SLABINFO=y 126CONFIG_SLABINFO=y
120CONFIG_RT_MUTEXES=y 127CONFIG_RT_MUTEXES=y
121# CONFIG_TINY_SHMEM is not set 128# CONFIG_TINY_SHMEM is not set
@@ -126,6 +133,7 @@ CONFIG_BLOCK=y
126# CONFIG_BLK_DEV_IO_TRACE is not set 133# CONFIG_BLK_DEV_IO_TRACE is not set
127# CONFIG_LSF is not set 134# CONFIG_LSF is not set
128# CONFIG_BLK_DEV_BSG is not set 135# CONFIG_BLK_DEV_BSG is not set
136# CONFIG_BLK_DEV_INTEGRITY is not set
129 137
130# 138#
131# IO Schedulers 139# IO Schedulers
@@ -144,8 +152,6 @@ CONFIG_CLASSIC_RCU=y
144# 152#
145# Platform support 153# Platform support
146# 154#
147# CONFIG_PPC_MPC512x is not set
148# CONFIG_PPC_MPC5121 is not set
149# CONFIG_PPC_CELL is not set 155# CONFIG_PPC_CELL is not set
150# CONFIG_PPC_CELL_NATIVE is not set 156# CONFIG_PPC_CELL_NATIVE is not set
151# CONFIG_PQ2ADS is not set 157# CONFIG_PQ2ADS is not set
@@ -154,11 +160,13 @@ CONFIG_MPC85xx=y
154# CONFIG_MPC8560_ADS is not set 160# CONFIG_MPC8560_ADS is not set
155# CONFIG_MPC85xx_CDS is not set 161# CONFIG_MPC85xx_CDS is not set
156# CONFIG_MPC85xx_MDS is not set 162# CONFIG_MPC85xx_MDS is not set
163# CONFIG_MPC8536_DS is not set
157# CONFIG_MPC85xx_DS is not set 164# CONFIG_MPC85xx_DS is not set
158# CONFIG_KSI8560 is not set 165# CONFIG_KSI8560 is not set
159# CONFIG_STX_GP3 is not set 166# CONFIG_STX_GP3 is not set
160# CONFIG_TQM8540 is not set 167# CONFIG_TQM8540 is not set
161# CONFIG_TQM8541 is not set 168# CONFIG_TQM8541 is not set
169# CONFIG_TQM8548 is not set
162# CONFIG_TQM8555 is not set 170# CONFIG_TQM8555 is not set
163# CONFIG_TQM8560 is not set 171# CONFIG_TQM8560 is not set
164CONFIG_SBC8548=y 172CONFIG_SBC8548=y
@@ -213,6 +221,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
213# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set 221# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
214CONFIG_PAGEFLAGS_EXTENDED=y 222CONFIG_PAGEFLAGS_EXTENDED=y
215CONFIG_SPLIT_PTLOCK_CPUS=4 223CONFIG_SPLIT_PTLOCK_CPUS=4
224CONFIG_MIGRATION=y
216# CONFIG_RESOURCES_64BIT is not set 225# CONFIG_RESOURCES_64BIT is not set
217CONFIG_ZONE_DMA_FLAG=1 226CONFIG_ZONE_DMA_FLAG=1
218CONFIG_BOUNCE=y 227CONFIG_BOUNCE=y
@@ -220,6 +229,7 @@ CONFIG_VIRT_TO_BUS=y
220CONFIG_FORCE_MAX_ZONEORDER=11 229CONFIG_FORCE_MAX_ZONEORDER=11
221CONFIG_PROC_DEVICETREE=y 230CONFIG_PROC_DEVICETREE=y
222# CONFIG_CMDLINE_BOOL is not set 231# CONFIG_CMDLINE_BOOL is not set
232CONFIG_EXTRA_TARGETS=""
223# CONFIG_PM is not set 233# CONFIG_PM is not set
224# CONFIG_SECCOMP is not set 234# CONFIG_SECCOMP is not set
225CONFIG_ISA_DMA_API=y 235CONFIG_ISA_DMA_API=y
@@ -231,6 +241,7 @@ CONFIG_ZONE_DMA=y
231CONFIG_PPC_INDIRECT_PCI=y 241CONFIG_PPC_INDIRECT_PCI=y
232CONFIG_FSL_SOC=y 242CONFIG_FSL_SOC=y
233CONFIG_FSL_PCI=y 243CONFIG_FSL_PCI=y
244CONFIG_PPC_PCI_CHOICE=y
234CONFIG_PCI=y 245CONFIG_PCI=y
235CONFIG_PCI_DOMAINS=y 246CONFIG_PCI_DOMAINS=y
236CONFIG_PCI_SYSCALL=y 247CONFIG_PCI_SYSCALL=y
@@ -256,10 +267,6 @@ CONFIG_KERNEL_START=0xc0000000
256CONFIG_PHYSICAL_START=0x00000000 267CONFIG_PHYSICAL_START=0x00000000
257CONFIG_PHYSICAL_ALIGN=0x10000000 268CONFIG_PHYSICAL_ALIGN=0x10000000
258CONFIG_TASK_SIZE=0xc0000000 269CONFIG_TASK_SIZE=0xc0000000
259
260#
261# Networking
262#
263CONFIG_NET=y 270CONFIG_NET=y
264 271
265# 272#
@@ -374,12 +381,14 @@ CONFIG_BLK_DEV_RAM_SIZE=4096
374# CONFIG_BLK_DEV_XIP is not set 381# CONFIG_BLK_DEV_XIP is not set
375# CONFIG_CDROM_PKTCDVD is not set 382# CONFIG_CDROM_PKTCDVD is not set
376# CONFIG_ATA_OVER_ETH is not set 383# CONFIG_ATA_OVER_ETH is not set
384# CONFIG_BLK_DEV_HD is not set
377CONFIG_MISC_DEVICES=y 385CONFIG_MISC_DEVICES=y
378# CONFIG_PHANTOM is not set 386# CONFIG_PHANTOM is not set
379# CONFIG_EEPROM_93CX6 is not set 387# CONFIG_EEPROM_93CX6 is not set
380# CONFIG_SGI_IOC4 is not set 388# CONFIG_SGI_IOC4 is not set
381# CONFIG_TIFM_CORE is not set 389# CONFIG_TIFM_CORE is not set
382# CONFIG_ENCLOSURE_SERVICES is not set 390# CONFIG_ENCLOSURE_SERVICES is not set
391# CONFIG_HP_ILO is not set
383CONFIG_HAVE_IDE=y 392CONFIG_HAVE_IDE=y
384# CONFIG_IDE is not set 393# CONFIG_IDE is not set
385 394
@@ -397,12 +406,15 @@ CONFIG_HAVE_IDE=y
397# 406#
398# IEEE 1394 (FireWire) support 407# IEEE 1394 (FireWire) support
399# 408#
409
410#
411# Enable only one of the two stacks, unless you know what you are doing
412#
400# CONFIG_FIREWIRE is not set 413# CONFIG_FIREWIRE is not set
401# CONFIG_IEEE1394 is not set 414# CONFIG_IEEE1394 is not set
402# CONFIG_I2O is not set 415# CONFIG_I2O is not set
403# CONFIG_MACINTOSH_DRIVERS is not set 416# CONFIG_MACINTOSH_DRIVERS is not set
404CONFIG_NETDEVICES=y 417CONFIG_NETDEVICES=y
405# CONFIG_NETDEVICES_MULTIQUEUE is not set
406# CONFIG_DUMMY is not set 418# CONFIG_DUMMY is not set
407# CONFIG_BONDING is not set 419# CONFIG_BONDING is not set
408# CONFIG_MACVLAN is not set 420# CONFIG_MACVLAN is not set
@@ -446,7 +458,6 @@ CONFIG_NETDEV_1000=y
446# CONFIG_DL2K is not set 458# CONFIG_DL2K is not set
447# CONFIG_E1000 is not set 459# CONFIG_E1000 is not set
448# CONFIG_E1000E is not set 460# CONFIG_E1000E is not set
449# CONFIG_E1000E_ENABLED is not set
450# CONFIG_IP1000 is not set 461# CONFIG_IP1000 is not set
451# CONFIG_IGB is not set 462# CONFIG_IGB is not set
452# CONFIG_NS83820 is not set 463# CONFIG_NS83820 is not set
@@ -460,9 +471,9 @@ CONFIG_NETDEV_1000=y
460# CONFIG_TIGON3 is not set 471# CONFIG_TIGON3 is not set
461# CONFIG_BNX2 is not set 472# CONFIG_BNX2 is not set
462CONFIG_GIANFAR=y 473CONFIG_GIANFAR=y
463CONFIG_GFAR_NAPI=y
464# CONFIG_QLA3XXX is not set 474# CONFIG_QLA3XXX is not set
465# CONFIG_ATL1 is not set 475# CONFIG_ATL1 is not set
476# CONFIG_ATL1E is not set
466CONFIG_NETDEV_10000=y 477CONFIG_NETDEV_10000=y
467# CONFIG_CHELSIO_T1 is not set 478# CONFIG_CHELSIO_T1 is not set
468# CONFIG_CHELSIO_T3 is not set 479# CONFIG_CHELSIO_T3 is not set
@@ -568,6 +579,8 @@ CONFIG_GEN_RTC=y
568CONFIG_DEVPORT=y 579CONFIG_DEVPORT=y
569# CONFIG_I2C is not set 580# CONFIG_I2C is not set
570# CONFIG_SPI is not set 581# CONFIG_SPI is not set
582CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
583# CONFIG_GPIOLIB is not set
571# CONFIG_W1 is not set 584# CONFIG_W1 is not set
572# CONFIG_POWER_SUPPLY is not set 585# CONFIG_POWER_SUPPLY is not set
573CONFIG_HWMON=y 586CONFIG_HWMON=y
@@ -588,6 +601,7 @@ CONFIG_HWMON=y
588# CONFIG_SENSORS_W83627EHF is not set 601# CONFIG_SENSORS_W83627EHF is not set
589# CONFIG_HWMON_DEBUG_CHIP is not set 602# CONFIG_HWMON_DEBUG_CHIP is not set
590# CONFIG_THERMAL is not set 603# CONFIG_THERMAL is not set
604# CONFIG_THERMAL_HWMON is not set
591# CONFIG_WATCHDOG is not set 605# CONFIG_WATCHDOG is not set
592 606
593# 607#
@@ -599,8 +613,10 @@ CONFIG_SSB_POSSIBLE=y
599# 613#
600# Multifunction device drivers 614# Multifunction device drivers
601# 615#
616# CONFIG_MFD_CORE is not set
602# CONFIG_MFD_SM501 is not set 617# CONFIG_MFD_SM501 is not set
603# CONFIG_HTC_PASIC3 is not set 618# CONFIG_HTC_PASIC3 is not set
619# CONFIG_MFD_TMIO is not set
604 620
605# 621#
606# Multimedia devices 622# Multimedia devices
@@ -632,10 +648,6 @@ CONFIG_VIDEO_OUTPUT_CONTROL=y
632# Display device support 648# Display device support
633# 649#
634# CONFIG_DISPLAY_SUPPORT is not set 650# CONFIG_DISPLAY_SUPPORT is not set
635
636#
637# Sound
638#
639# CONFIG_SOUND is not set 651# CONFIG_SOUND is not set
640# CONFIG_HID_SUPPORT is not set 652# CONFIG_HID_SUPPORT is not set
641# CONFIG_USB_SUPPORT is not set 653# CONFIG_USB_SUPPORT is not set
@@ -706,6 +718,7 @@ CONFIG_TMPFS=y
706# CONFIG_CRAMFS is not set 718# CONFIG_CRAMFS is not set
707# CONFIG_VXFS_FS is not set 719# CONFIG_VXFS_FS is not set
708# CONFIG_MINIX_FS is not set 720# CONFIG_MINIX_FS is not set
721# CONFIG_OMFS_FS is not set
709# CONFIG_HPFS_FS is not set 722# CONFIG_HPFS_FS is not set
710# CONFIG_QNX4FS_FS is not set 723# CONFIG_QNX4FS_FS is not set
711# CONFIG_ROMFS_FS is not set 724# CONFIG_ROMFS_FS is not set
@@ -715,12 +728,11 @@ CONFIG_NETWORK_FILESYSTEMS=y
715CONFIG_NFS_FS=y 728CONFIG_NFS_FS=y
716# CONFIG_NFS_V3 is not set 729# CONFIG_NFS_V3 is not set
717# CONFIG_NFS_V4 is not set 730# CONFIG_NFS_V4 is not set
718# CONFIG_NFSD is not set
719CONFIG_ROOT_NFS=y 731CONFIG_ROOT_NFS=y
732# CONFIG_NFSD is not set
720CONFIG_LOCKD=y 733CONFIG_LOCKD=y
721CONFIG_NFS_COMMON=y 734CONFIG_NFS_COMMON=y
722CONFIG_SUNRPC=y 735CONFIG_SUNRPC=y
723# CONFIG_SUNRPC_BIND34 is not set
724# CONFIG_RPCSEC_GSS_KRB5 is not set 736# CONFIG_RPCSEC_GSS_KRB5 is not set
725# CONFIG_RPCSEC_GSS_SPKM3 is not set 737# CONFIG_RPCSEC_GSS_SPKM3 is not set
726# CONFIG_SMB_FS is not set 738# CONFIG_SMB_FS is not set
@@ -744,6 +756,7 @@ CONFIG_BITREVERSE=y
744# CONFIG_GENERIC_FIND_FIRST_BIT is not set 756# CONFIG_GENERIC_FIND_FIRST_BIT is not set
745# CONFIG_CRC_CCITT is not set 757# CONFIG_CRC_CCITT is not set
746# CONFIG_CRC16 is not set 758# CONFIG_CRC16 is not set
759# CONFIG_CRC_T10DIF is not set
747# CONFIG_CRC_ITU_T is not set 760# CONFIG_CRC_ITU_T is not set
748CONFIG_CRC32=y 761CONFIG_CRC32=y
749# CONFIG_CRC7 is not set 762# CONFIG_CRC7 is not set
@@ -767,7 +780,16 @@ CONFIG_FRAME_WARN=1024
767# CONFIG_HEADERS_CHECK is not set 780# CONFIG_HEADERS_CHECK is not set
768# CONFIG_DEBUG_KERNEL is not set 781# CONFIG_DEBUG_KERNEL is not set
769# CONFIG_DEBUG_BUGVERBOSE is not set 782# CONFIG_DEBUG_BUGVERBOSE is not set
783# CONFIG_DEBUG_MEMORY_INIT is not set
784# CONFIG_LATENCYTOP is not set
785CONFIG_SYSCTL_SYSCALL_CHECK=y
786CONFIG_HAVE_FTRACE=y
787CONFIG_HAVE_DYNAMIC_FTRACE=y
788# CONFIG_FTRACE is not set
789# CONFIG_SCHED_TRACER is not set
790# CONFIG_CONTEXT_SWITCH_TRACER is not set
770# CONFIG_SAMPLES is not set 791# CONFIG_SAMPLES is not set
792CONFIG_HAVE_ARCH_KGDB=y
771# CONFIG_IRQSTACKS is not set 793# CONFIG_IRQSTACKS is not set
772# CONFIG_PPC_EARLY_DEBUG is not set 794# CONFIG_PPC_EARLY_DEBUG is not set
773 795
@@ -819,6 +841,10 @@ CONFIG_CRYPTO=y
819# CONFIG_CRYPTO_MD4 is not set 841# CONFIG_CRYPTO_MD4 is not set
820# CONFIG_CRYPTO_MD5 is not set 842# CONFIG_CRYPTO_MD5 is not set
821# CONFIG_CRYPTO_MICHAEL_MIC is not set 843# CONFIG_CRYPTO_MICHAEL_MIC is not set
844# CONFIG_CRYPTO_RMD128 is not set
845# CONFIG_CRYPTO_RMD160 is not set
846# CONFIG_CRYPTO_RMD256 is not set
847# CONFIG_CRYPTO_RMD320 is not set
822# CONFIG_CRYPTO_SHA1 is not set 848# CONFIG_CRYPTO_SHA1 is not set
823# CONFIG_CRYPTO_SHA256 is not set 849# CONFIG_CRYPTO_SHA256 is not set
824# CONFIG_CRYPTO_SHA512 is not set 850# CONFIG_CRYPTO_SHA512 is not set
@@ -851,5 +877,6 @@ CONFIG_CRYPTO=y
851# CONFIG_CRYPTO_LZO is not set 877# CONFIG_CRYPTO_LZO is not set
852CONFIG_CRYPTO_HW=y 878CONFIG_CRYPTO_HW=y
853# CONFIG_CRYPTO_DEV_HIFN_795X is not set 879# CONFIG_CRYPTO_DEV_HIFN_795X is not set
880# CONFIG_CRYPTO_DEV_TALITOS is not set
854# CONFIG_PPC_CLOCK is not set 881# CONFIG_PPC_CLOCK is not set
855# CONFIG_VIRTUALIZATION is not set 882# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/configs/85xx/sbc8560_defconfig b/arch/powerpc/configs/85xx/sbc8560_defconfig
index 655518dcd73f..daef36f41b42 100644
--- a/arch/powerpc/configs/85xx/sbc8560_defconfig
+++ b/arch/powerpc/configs/85xx/sbc8560_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc5 3# Linux kernel version: 2.6.27-rc4
4# Mon Jun 9 08:52:38 2008 4# Thu Aug 21 00:52:36 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -15,6 +15,7 @@ CONFIG_PPC_85xx=y
15# CONFIG_44x is not set 15# CONFIG_44x is not set
16# CONFIG_E200 is not set 16# CONFIG_E200 is not set
17CONFIG_E500=y 17CONFIG_E500=y
18# CONFIG_PPC_E500MC is not set
18CONFIG_BOOKE=y 19CONFIG_BOOKE=y
19CONFIG_FSL_BOOKE=y 20CONFIG_FSL_BOOKE=y
20CONFIG_FSL_EMB_PERFMON=y 21CONFIG_FSL_EMB_PERFMON=y
@@ -33,6 +34,7 @@ CONFIG_GENERIC_HARDIRQS=y
33# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set 34# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
34CONFIG_IRQ_PER_CPU=y 35CONFIG_IRQ_PER_CPU=y
35CONFIG_STACKTRACE_SUPPORT=y 36CONFIG_STACKTRACE_SUPPORT=y
37CONFIG_HAVE_LATENCYTOP_SUPPORT=y
36CONFIG_LOCKDEP_SUPPORT=y 38CONFIG_LOCKDEP_SUPPORT=y
37CONFIG_RWSEM_XCHGADD_ALGORITHM=y 39CONFIG_RWSEM_XCHGADD_ALGORITHM=y
38CONFIG_ARCH_HAS_ILOG2_U32=y 40CONFIG_ARCH_HAS_ILOG2_U32=y
@@ -89,7 +91,6 @@ CONFIG_INITRAMFS_SOURCE=""
89CONFIG_SYSCTL=y 91CONFIG_SYSCTL=y
90CONFIG_EMBEDDED=y 92CONFIG_EMBEDDED=y
91CONFIG_SYSCTL_SYSCALL=y 93CONFIG_SYSCTL_SYSCALL=y
92CONFIG_SYSCTL_SYSCALL_CHECK=y
93CONFIG_KALLSYMS=y 94CONFIG_KALLSYMS=y
94# CONFIG_KALLSYMS_ALL is not set 95# CONFIG_KALLSYMS_ALL is not set
95# CONFIG_KALLSYMS_EXTRA_PASS is not set 96# CONFIG_KALLSYMS_EXTRA_PASS is not set
@@ -113,10 +114,16 @@ CONFIG_SLAB=y
113# CONFIG_PROFILING is not set 114# CONFIG_PROFILING is not set
114# CONFIG_MARKERS is not set 115# CONFIG_MARKERS is not set
115CONFIG_HAVE_OPROFILE=y 116CONFIG_HAVE_OPROFILE=y
117CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
118CONFIG_HAVE_IOREMAP_PROT=y
116CONFIG_HAVE_KPROBES=y 119CONFIG_HAVE_KPROBES=y
117CONFIG_HAVE_KRETPROBES=y 120CONFIG_HAVE_KRETPROBES=y
121CONFIG_HAVE_ARCH_TRACEHOOK=y
118# CONFIG_HAVE_DMA_ATTRS is not set 122# CONFIG_HAVE_DMA_ATTRS is not set
123# CONFIG_USE_GENERIC_SMP_HELPERS is not set
124# CONFIG_HAVE_CLK is not set
119CONFIG_PROC_PAGE_MONITOR=y 125CONFIG_PROC_PAGE_MONITOR=y
126# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
120CONFIG_SLABINFO=y 127CONFIG_SLABINFO=y
121CONFIG_RT_MUTEXES=y 128CONFIG_RT_MUTEXES=y
122# CONFIG_TINY_SHMEM is not set 129# CONFIG_TINY_SHMEM is not set
@@ -127,6 +134,7 @@ CONFIG_BLOCK=y
127# CONFIG_BLK_DEV_IO_TRACE is not set 134# CONFIG_BLK_DEV_IO_TRACE is not set
128# CONFIG_LSF is not set 135# CONFIG_LSF is not set
129# CONFIG_BLK_DEV_BSG is not set 136# CONFIG_BLK_DEV_BSG is not set
137# CONFIG_BLK_DEV_INTEGRITY is not set
130 138
131# 139#
132# IO Schedulers 140# IO Schedulers
@@ -145,8 +153,6 @@ CONFIG_CLASSIC_RCU=y
145# 153#
146# Platform support 154# Platform support
147# 155#
148# CONFIG_PPC_MPC512x is not set
149# CONFIG_PPC_MPC5121 is not set
150# CONFIG_PPC_CELL is not set 156# CONFIG_PPC_CELL is not set
151# CONFIG_PPC_CELL_NATIVE is not set 157# CONFIG_PPC_CELL_NATIVE is not set
152# CONFIG_PQ2ADS is not set 158# CONFIG_PQ2ADS is not set
@@ -155,11 +161,13 @@ CONFIG_MPC85xx=y
155# CONFIG_MPC8560_ADS is not set 161# CONFIG_MPC8560_ADS is not set
156# CONFIG_MPC85xx_CDS is not set 162# CONFIG_MPC85xx_CDS is not set
157# CONFIG_MPC85xx_MDS is not set 163# CONFIG_MPC85xx_MDS is not set
164# CONFIG_MPC8536_DS is not set
158# CONFIG_MPC85xx_DS is not set 165# CONFIG_MPC85xx_DS is not set
159# CONFIG_KSI8560 is not set 166# CONFIG_KSI8560 is not set
160# CONFIG_STX_GP3 is not set 167# CONFIG_STX_GP3 is not set
161# CONFIG_TQM8540 is not set 168# CONFIG_TQM8540 is not set
162# CONFIG_TQM8541 is not set 169# CONFIG_TQM8541 is not set
170# CONFIG_TQM8548 is not set
163# CONFIG_TQM8555 is not set 171# CONFIG_TQM8555 is not set
164# CONFIG_TQM8560 is not set 172# CONFIG_TQM8560 is not set
165# CONFIG_SBC8548 is not set 173# CONFIG_SBC8548 is not set
@@ -214,6 +222,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
214# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set 222# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
215CONFIG_PAGEFLAGS_EXTENDED=y 223CONFIG_PAGEFLAGS_EXTENDED=y
216CONFIG_SPLIT_PTLOCK_CPUS=4 224CONFIG_SPLIT_PTLOCK_CPUS=4
225CONFIG_MIGRATION=y
217# CONFIG_RESOURCES_64BIT is not set 226# CONFIG_RESOURCES_64BIT is not set
218CONFIG_ZONE_DMA_FLAG=1 227CONFIG_ZONE_DMA_FLAG=1
219CONFIG_BOUNCE=y 228CONFIG_BOUNCE=y
@@ -221,6 +230,7 @@ CONFIG_VIRT_TO_BUS=y
221CONFIG_FORCE_MAX_ZONEORDER=11 230CONFIG_FORCE_MAX_ZONEORDER=11
222CONFIG_PROC_DEVICETREE=y 231CONFIG_PROC_DEVICETREE=y
223# CONFIG_CMDLINE_BOOL is not set 232# CONFIG_CMDLINE_BOOL is not set
233CONFIG_EXTRA_TARGETS=""
224# CONFIG_PM is not set 234# CONFIG_PM is not set
225# CONFIG_SECCOMP is not set 235# CONFIG_SECCOMP is not set
226CONFIG_ISA_DMA_API=y 236CONFIG_ISA_DMA_API=y
@@ -230,6 +240,7 @@ CONFIG_ISA_DMA_API=y
230# 240#
231CONFIG_ZONE_DMA=y 241CONFIG_ZONE_DMA=y
232CONFIG_FSL_SOC=y 242CONFIG_FSL_SOC=y
243CONFIG_PPC_PCI_CHOICE=y
233# CONFIG_PCI is not set 244# CONFIG_PCI is not set
234# CONFIG_PCI_DOMAINS is not set 245# CONFIG_PCI_DOMAINS is not set
235# CONFIG_PCI_SYSCALL is not set 246# CONFIG_PCI_SYSCALL is not set
@@ -251,10 +262,6 @@ CONFIG_KERNEL_START=0xc0000000
251CONFIG_PHYSICAL_START=0x00000000 262CONFIG_PHYSICAL_START=0x00000000
252CONFIG_PHYSICAL_ALIGN=0x10000000 263CONFIG_PHYSICAL_ALIGN=0x10000000
253CONFIG_TASK_SIZE=0xc0000000 264CONFIG_TASK_SIZE=0xc0000000
254
255#
256# Networking
257#
258CONFIG_NET=y 265CONFIG_NET=y
259 266
260# 267#
@@ -366,6 +373,7 @@ CONFIG_BLK_DEV_RAM_SIZE=32768
366# CONFIG_BLK_DEV_XIP is not set 373# CONFIG_BLK_DEV_XIP is not set
367# CONFIG_CDROM_PKTCDVD is not set 374# CONFIG_CDROM_PKTCDVD is not set
368# CONFIG_ATA_OVER_ETH is not set 375# CONFIG_ATA_OVER_ETH is not set
376# CONFIG_BLK_DEV_HD is not set
369CONFIG_MISC_DEVICES=y 377CONFIG_MISC_DEVICES=y
370# CONFIG_EEPROM_93CX6 is not set 378# CONFIG_EEPROM_93CX6 is not set
371# CONFIG_ENCLOSURE_SERVICES is not set 379# CONFIG_ENCLOSURE_SERVICES is not set
@@ -383,7 +391,6 @@ CONFIG_HAVE_IDE=y
383# CONFIG_MD is not set 391# CONFIG_MD is not set
384# CONFIG_MACINTOSH_DRIVERS is not set 392# CONFIG_MACINTOSH_DRIVERS is not set
385CONFIG_NETDEVICES=y 393CONFIG_NETDEVICES=y
386# CONFIG_NETDEVICES_MULTIQUEUE is not set
387# CONFIG_DUMMY is not set 394# CONFIG_DUMMY is not set
388# CONFIG_BONDING is not set 395# CONFIG_BONDING is not set
389# CONFIG_MACVLAN is not set 396# CONFIG_MACVLAN is not set
@@ -415,9 +422,7 @@ CONFIG_MII=y
415# CONFIG_IBM_NEW_EMAC_EMAC4 is not set 422# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
416# CONFIG_B44 is not set 423# CONFIG_B44 is not set
417CONFIG_NETDEV_1000=y 424CONFIG_NETDEV_1000=y
418# CONFIG_E1000E_ENABLED is not set
419CONFIG_GIANFAR=y 425CONFIG_GIANFAR=y
420CONFIG_GFAR_NAPI=y
421CONFIG_NETDEV_10000=y 426CONFIG_NETDEV_10000=y
422 427
423# 428#
@@ -501,6 +506,8 @@ CONFIG_LEGACY_PTY_COUNT=256
501# CONFIG_TCG_TPM is not set 506# CONFIG_TCG_TPM is not set
502# CONFIG_I2C is not set 507# CONFIG_I2C is not set
503# CONFIG_SPI is not set 508# CONFIG_SPI is not set
509CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
510# CONFIG_GPIOLIB is not set
504# CONFIG_W1 is not set 511# CONFIG_W1 is not set
505# CONFIG_POWER_SUPPLY is not set 512# CONFIG_POWER_SUPPLY is not set
506CONFIG_HWMON=y 513CONFIG_HWMON=y
@@ -517,6 +524,7 @@ CONFIG_HWMON=y
517# CONFIG_SENSORS_W83627EHF is not set 524# CONFIG_SENSORS_W83627EHF is not set
518# CONFIG_HWMON_DEBUG_CHIP is not set 525# CONFIG_HWMON_DEBUG_CHIP is not set
519# CONFIG_THERMAL is not set 526# CONFIG_THERMAL is not set
527# CONFIG_THERMAL_HWMON is not set
520# CONFIG_WATCHDOG is not set 528# CONFIG_WATCHDOG is not set
521 529
522# 530#
@@ -528,8 +536,10 @@ CONFIG_SSB_POSSIBLE=y
528# 536#
529# Multifunction device drivers 537# Multifunction device drivers
530# 538#
539# CONFIG_MFD_CORE is not set
531# CONFIG_MFD_SM501 is not set 540# CONFIG_MFD_SM501 is not set
532# CONFIG_HTC_PASIC3 is not set 541# CONFIG_HTC_PASIC3 is not set
542# CONFIG_MFD_TMIO is not set
533 543
534# 544#
535# Multimedia devices 545# Multimedia devices
@@ -559,10 +569,6 @@ CONFIG_VIDEO_OUTPUT_CONTROL=y
559# Display device support 569# Display device support
560# 570#
561# CONFIG_DISPLAY_SUPPORT is not set 571# CONFIG_DISPLAY_SUPPORT is not set
562
563#
564# Sound
565#
566# CONFIG_SOUND is not set 572# CONFIG_SOUND is not set
567CONFIG_HID_SUPPORT=y 573CONFIG_HID_SUPPORT=y
568CONFIG_HID=y 574CONFIG_HID=y
@@ -576,6 +582,10 @@ CONFIG_USB_SUPPORT=y
576# CONFIG_USB_OTG_BLACKLIST_HUB is not set 582# CONFIG_USB_OTG_BLACKLIST_HUB is not set
577 583
578# 584#
585# Enable Host or Gadget support to see Inventra options
586#
587
588#
579# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 589# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
580# 590#
581# CONFIG_USB_GADGET is not set 591# CONFIG_USB_GADGET is not set
@@ -679,6 +689,7 @@ CONFIG_TMPFS=y
679# CONFIG_CRAMFS is not set 689# CONFIG_CRAMFS is not set
680# CONFIG_VXFS_FS is not set 690# CONFIG_VXFS_FS is not set
681# CONFIG_MINIX_FS is not set 691# CONFIG_MINIX_FS is not set
692# CONFIG_OMFS_FS is not set
682# CONFIG_HPFS_FS is not set 693# CONFIG_HPFS_FS is not set
683# CONFIG_QNX4FS_FS is not set 694# CONFIG_QNX4FS_FS is not set
684# CONFIG_ROMFS_FS is not set 695# CONFIG_ROMFS_FS is not set
@@ -688,12 +699,11 @@ CONFIG_NETWORK_FILESYSTEMS=y
688CONFIG_NFS_FS=y 699CONFIG_NFS_FS=y
689# CONFIG_NFS_V3 is not set 700# CONFIG_NFS_V3 is not set
690# CONFIG_NFS_V4 is not set 701# CONFIG_NFS_V4 is not set
691# CONFIG_NFSD is not set
692CONFIG_ROOT_NFS=y 702CONFIG_ROOT_NFS=y
703# CONFIG_NFSD is not set
693CONFIG_LOCKD=y 704CONFIG_LOCKD=y
694CONFIG_NFS_COMMON=y 705CONFIG_NFS_COMMON=y
695CONFIG_SUNRPC=y 706CONFIG_SUNRPC=y
696# CONFIG_SUNRPC_BIND34 is not set
697# CONFIG_RPCSEC_GSS_KRB5 is not set 707# CONFIG_RPCSEC_GSS_KRB5 is not set
698# CONFIG_RPCSEC_GSS_SPKM3 is not set 708# CONFIG_RPCSEC_GSS_SPKM3 is not set
699# CONFIG_SMB_FS is not set 709# CONFIG_SMB_FS is not set
@@ -729,6 +739,7 @@ CONFIG_BITREVERSE=y
729# CONFIG_GENERIC_FIND_FIRST_BIT is not set 739# CONFIG_GENERIC_FIND_FIRST_BIT is not set
730# CONFIG_CRC_CCITT is not set 740# CONFIG_CRC_CCITT is not set
731# CONFIG_CRC16 is not set 741# CONFIG_CRC16 is not set
742# CONFIG_CRC_T10DIF is not set
732# CONFIG_CRC_ITU_T is not set 743# CONFIG_CRC_ITU_T is not set
733CONFIG_CRC32=y 744CONFIG_CRC32=y
734# CONFIG_CRC7 is not set 745# CONFIG_CRC7 is not set
@@ -753,6 +764,8 @@ CONFIG_MAGIC_SYSRQ=y
753CONFIG_DEBUG_KERNEL=y 764CONFIG_DEBUG_KERNEL=y
754# CONFIG_DEBUG_SHIRQ is not set 765# CONFIG_DEBUG_SHIRQ is not set
755CONFIG_DETECT_SOFTLOCKUP=y 766CONFIG_DETECT_SOFTLOCKUP=y
767# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
768CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
756CONFIG_SCHED_DEBUG=y 769CONFIG_SCHED_DEBUG=y
757# CONFIG_SCHEDSTATS is not set 770# CONFIG_SCHEDSTATS is not set
758# CONFIG_TIMER_STATS is not set 771# CONFIG_TIMER_STATS is not set
@@ -769,16 +782,29 @@ CONFIG_DEBUG_MUTEXES=y
769# CONFIG_DEBUG_INFO is not set 782# CONFIG_DEBUG_INFO is not set
770# CONFIG_DEBUG_VM is not set 783# CONFIG_DEBUG_VM is not set
771# CONFIG_DEBUG_WRITECOUNT is not set 784# CONFIG_DEBUG_WRITECOUNT is not set
785# CONFIG_DEBUG_MEMORY_INIT is not set
772# CONFIG_DEBUG_LIST is not set 786# CONFIG_DEBUG_LIST is not set
773# CONFIG_DEBUG_SG is not set 787# CONFIG_DEBUG_SG is not set
774# CONFIG_BOOT_PRINTK_DELAY is not set 788# CONFIG_BOOT_PRINTK_DELAY is not set
789# CONFIG_RCU_TORTURE_TEST is not set
775# CONFIG_BACKTRACE_SELF_TEST is not set 790# CONFIG_BACKTRACE_SELF_TEST is not set
776# CONFIG_FAULT_INJECTION is not set 791# CONFIG_FAULT_INJECTION is not set
792# CONFIG_LATENCYTOP is not set
793CONFIG_SYSCTL_SYSCALL_CHECK=y
794CONFIG_HAVE_FTRACE=y
795CONFIG_HAVE_DYNAMIC_FTRACE=y
796# CONFIG_FTRACE is not set
797# CONFIG_SCHED_TRACER is not set
798# CONFIG_CONTEXT_SWITCH_TRACER is not set
777# CONFIG_SAMPLES is not set 799# CONFIG_SAMPLES is not set
800CONFIG_HAVE_ARCH_KGDB=y
801# CONFIG_KGDB is not set
778# CONFIG_DEBUG_STACKOVERFLOW is not set 802# CONFIG_DEBUG_STACKOVERFLOW is not set
779# CONFIG_DEBUG_STACK_USAGE is not set 803# CONFIG_DEBUG_STACK_USAGE is not set
780# CONFIG_DEBUG_PAGEALLOC is not set 804# CONFIG_DEBUG_PAGEALLOC is not set
781# CONFIG_DEBUGGER is not set 805# CONFIG_CODE_PATCHING_SELFTEST is not set
806# CONFIG_FTR_FIXUP_SELFTEST is not set
807# CONFIG_XMON is not set
782# CONFIG_IRQSTACKS is not set 808# CONFIG_IRQSTACKS is not set
783# CONFIG_BDI_SWITCH is not set 809# CONFIG_BDI_SWITCH is not set
784CONFIG_PPC_EARLY_DEBUG=y 810CONFIG_PPC_EARLY_DEBUG=y
@@ -842,6 +868,10 @@ CONFIG_CRYPTO=y
842# CONFIG_CRYPTO_MD4 is not set 868# CONFIG_CRYPTO_MD4 is not set
843# CONFIG_CRYPTO_MD5 is not set 869# CONFIG_CRYPTO_MD5 is not set
844# CONFIG_CRYPTO_MICHAEL_MIC is not set 870# CONFIG_CRYPTO_MICHAEL_MIC is not set
871# CONFIG_CRYPTO_RMD128 is not set
872# CONFIG_CRYPTO_RMD160 is not set
873# CONFIG_CRYPTO_RMD256 is not set
874# CONFIG_CRYPTO_RMD320 is not set
845# CONFIG_CRYPTO_SHA1 is not set 875# CONFIG_CRYPTO_SHA1 is not set
846# CONFIG_CRYPTO_SHA256 is not set 876# CONFIG_CRYPTO_SHA256 is not set
847# CONFIG_CRYPTO_SHA512 is not set 877# CONFIG_CRYPTO_SHA512 is not set
@@ -873,5 +903,6 @@ CONFIG_CRYPTO=y
873# CONFIG_CRYPTO_DEFLATE is not set 903# CONFIG_CRYPTO_DEFLATE is not set
874# CONFIG_CRYPTO_LZO is not set 904# CONFIG_CRYPTO_LZO is not set
875CONFIG_CRYPTO_HW=y 905CONFIG_CRYPTO_HW=y
906# CONFIG_CRYPTO_DEV_TALITOS is not set
876# CONFIG_PPC_CLOCK is not set 907# CONFIG_PPC_CLOCK is not set
877# CONFIG_VIRTUALIZATION is not set 908# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/configs/85xx/stx_gp3_defconfig b/arch/powerpc/configs/85xx/stx_gp3_defconfig
index 7804ca1ecc94..2b05d43f8f7e 100644
--- a/arch/powerpc/configs/85xx/stx_gp3_defconfig
+++ b/arch/powerpc/configs/85xx/stx_gp3_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc5 3# Linux kernel version: 2.6.27-rc4
4# Mon Jun 9 08:52:38 2008 4# Thu Aug 21 00:52:37 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -15,6 +15,7 @@ CONFIG_PPC_85xx=y
15# CONFIG_44x is not set 15# CONFIG_44x is not set
16# CONFIG_E200 is not set 16# CONFIG_E200 is not set
17CONFIG_E500=y 17CONFIG_E500=y
18# CONFIG_PPC_E500MC is not set
18CONFIG_BOOKE=y 19CONFIG_BOOKE=y
19CONFIG_FSL_BOOKE=y 20CONFIG_FSL_BOOKE=y
20CONFIG_FSL_EMB_PERFMON=y 21CONFIG_FSL_EMB_PERFMON=y
@@ -33,12 +34,14 @@ CONFIG_GENERIC_HARDIRQS=y
33# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set 34# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
34CONFIG_IRQ_PER_CPU=y 35CONFIG_IRQ_PER_CPU=y
35CONFIG_STACKTRACE_SUPPORT=y 36CONFIG_STACKTRACE_SUPPORT=y
37CONFIG_HAVE_LATENCYTOP_SUPPORT=y
36CONFIG_LOCKDEP_SUPPORT=y 38CONFIG_LOCKDEP_SUPPORT=y
37CONFIG_RWSEM_XCHGADD_ALGORITHM=y 39CONFIG_RWSEM_XCHGADD_ALGORITHM=y
38CONFIG_ARCH_HAS_ILOG2_U32=y 40CONFIG_ARCH_HAS_ILOG2_U32=y
39CONFIG_GENERIC_HWEIGHT=y 41CONFIG_GENERIC_HWEIGHT=y
40CONFIG_GENERIC_CALIBRATE_DELAY=y 42CONFIG_GENERIC_CALIBRATE_DELAY=y
41CONFIG_GENERIC_FIND_NEXT_BIT=y 43CONFIG_GENERIC_FIND_NEXT_BIT=y
44CONFIG_GENERIC_GPIO=y
42# CONFIG_ARCH_NO_VIRT_TO_BUS is not set 45# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
43CONFIG_PPC=y 46CONFIG_PPC=y
44CONFIG_EARLY_PRINTK=y 47CONFIG_EARLY_PRINTK=y
@@ -89,7 +92,6 @@ CONFIG_INITRAMFS_SOURCE=""
89CONFIG_SYSCTL=y 92CONFIG_SYSCTL=y
90CONFIG_EMBEDDED=y 93CONFIG_EMBEDDED=y
91CONFIG_SYSCTL_SYSCALL=y 94CONFIG_SYSCTL_SYSCALL=y
92CONFIG_SYSCTL_SYSCALL_CHECK=y
93CONFIG_KALLSYMS=y 95CONFIG_KALLSYMS=y
94# CONFIG_KALLSYMS_ALL is not set 96# CONFIG_KALLSYMS_ALL is not set
95# CONFIG_KALLSYMS_EXTRA_PASS is not set 97# CONFIG_KALLSYMS_EXTRA_PASS is not set
@@ -115,10 +117,16 @@ CONFIG_SLUB=y
115# CONFIG_MARKERS is not set 117# CONFIG_MARKERS is not set
116CONFIG_HAVE_OPROFILE=y 118CONFIG_HAVE_OPROFILE=y
117# CONFIG_KPROBES is not set 119# CONFIG_KPROBES is not set
120CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
121CONFIG_HAVE_IOREMAP_PROT=y
118CONFIG_HAVE_KPROBES=y 122CONFIG_HAVE_KPROBES=y
119CONFIG_HAVE_KRETPROBES=y 123CONFIG_HAVE_KRETPROBES=y
124CONFIG_HAVE_ARCH_TRACEHOOK=y
120# CONFIG_HAVE_DMA_ATTRS is not set 125# CONFIG_HAVE_DMA_ATTRS is not set
126# CONFIG_USE_GENERIC_SMP_HELPERS is not set
127CONFIG_HAVE_CLK=y
121CONFIG_PROC_PAGE_MONITOR=y 128CONFIG_PROC_PAGE_MONITOR=y
129# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
122CONFIG_SLABINFO=y 130CONFIG_SLABINFO=y
123CONFIG_RT_MUTEXES=y 131CONFIG_RT_MUTEXES=y
124# CONFIG_TINY_SHMEM is not set 132# CONFIG_TINY_SHMEM is not set
@@ -134,6 +142,7 @@ CONFIG_BLOCK=y
134# CONFIG_BLK_DEV_IO_TRACE is not set 142# CONFIG_BLK_DEV_IO_TRACE is not set
135# CONFIG_LSF is not set 143# CONFIG_LSF is not set
136# CONFIG_BLK_DEV_BSG is not set 144# CONFIG_BLK_DEV_BSG is not set
145# CONFIG_BLK_DEV_INTEGRITY is not set
137 146
138# 147#
139# IO Schedulers 148# IO Schedulers
@@ -152,8 +161,6 @@ CONFIG_CLASSIC_RCU=y
152# 161#
153# Platform support 162# Platform support
154# 163#
155# CONFIG_PPC_MPC512x is not set
156# CONFIG_PPC_MPC5121 is not set
157# CONFIG_PPC_CELL is not set 164# CONFIG_PPC_CELL is not set
158# CONFIG_PPC_CELL_NATIVE is not set 165# CONFIG_PPC_CELL_NATIVE is not set
159# CONFIG_PQ2ADS is not set 166# CONFIG_PQ2ADS is not set
@@ -162,11 +169,13 @@ CONFIG_MPC85xx=y
162# CONFIG_MPC8560_ADS is not set 169# CONFIG_MPC8560_ADS is not set
163# CONFIG_MPC85xx_CDS is not set 170# CONFIG_MPC85xx_CDS is not set
164# CONFIG_MPC85xx_MDS is not set 171# CONFIG_MPC85xx_MDS is not set
172# CONFIG_MPC8536_DS is not set
165# CONFIG_MPC85xx_DS is not set 173# CONFIG_MPC85xx_DS is not set
166# CONFIG_KSI8560 is not set 174# CONFIG_KSI8560 is not set
167CONFIG_STX_GP3=y 175CONFIG_STX_GP3=y
168# CONFIG_TQM8540 is not set 176# CONFIG_TQM8540 is not set
169# CONFIG_TQM8541 is not set 177# CONFIG_TQM8541 is not set
178# CONFIG_TQM8548 is not set
170# CONFIG_TQM8555 is not set 179# CONFIG_TQM8555 is not set
171# CONFIG_TQM8560 is not set 180# CONFIG_TQM8560 is not set
172# CONFIG_SBC8548 is not set 181# CONFIG_SBC8548 is not set
@@ -183,7 +192,6 @@ CONFIG_MPIC=y
183# CONFIG_GENERIC_IOMAP is not set 192# CONFIG_GENERIC_IOMAP is not set
184# CONFIG_CPU_FREQ is not set 193# CONFIG_CPU_FREQ is not set
185CONFIG_CPM2=y 194CONFIG_CPM2=y
186CONFIG_PPC_CPM_NEW_BINDING=y
187# CONFIG_FSL_ULI1575 is not set 195# CONFIG_FSL_ULI1575 is not set
188CONFIG_CPM=y 196CONFIG_CPM=y
189 197
@@ -223,6 +231,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
223# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set 231# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
224CONFIG_PAGEFLAGS_EXTENDED=y 232CONFIG_PAGEFLAGS_EXTENDED=y
225CONFIG_SPLIT_PTLOCK_CPUS=4 233CONFIG_SPLIT_PTLOCK_CPUS=4
234CONFIG_MIGRATION=y
226# CONFIG_RESOURCES_64BIT is not set 235# CONFIG_RESOURCES_64BIT is not set
227CONFIG_ZONE_DMA_FLAG=1 236CONFIG_ZONE_DMA_FLAG=1
228CONFIG_BOUNCE=y 237CONFIG_BOUNCE=y
@@ -230,6 +239,7 @@ CONFIG_VIRT_TO_BUS=y
230CONFIG_FORCE_MAX_ZONEORDER=11 239CONFIG_FORCE_MAX_ZONEORDER=11
231CONFIG_PROC_DEVICETREE=y 240CONFIG_PROC_DEVICETREE=y
232# CONFIG_CMDLINE_BOOL is not set 241# CONFIG_CMDLINE_BOOL is not set
242CONFIG_EXTRA_TARGETS=""
233# CONFIG_PM is not set 243# CONFIG_PM is not set
234CONFIG_SECCOMP=y 244CONFIG_SECCOMP=y
235CONFIG_ISA_DMA_API=y 245CONFIG_ISA_DMA_API=y
@@ -241,6 +251,7 @@ CONFIG_ZONE_DMA=y
241CONFIG_PPC_INDIRECT_PCI=y 251CONFIG_PPC_INDIRECT_PCI=y
242CONFIG_FSL_SOC=y 252CONFIG_FSL_SOC=y
243CONFIG_FSL_PCI=y 253CONFIG_FSL_PCI=y
254CONFIG_PPC_PCI_CHOICE=y
244CONFIG_PCI=y 255CONFIG_PCI=y
245CONFIG_PCI_DOMAINS=y 256CONFIG_PCI_DOMAINS=y
246CONFIG_PCI_SYSCALL=y 257CONFIG_PCI_SYSCALL=y
@@ -267,10 +278,6 @@ CONFIG_KERNEL_START=0xc0000000
267CONFIG_PHYSICAL_START=0x00000000 278CONFIG_PHYSICAL_START=0x00000000
268CONFIG_PHYSICAL_ALIGN=0x10000000 279CONFIG_PHYSICAL_ALIGN=0x10000000
269CONFIG_TASK_SIZE=0xc0000000 280CONFIG_TASK_SIZE=0xc0000000
270
271#
272# Networking
273#
274CONFIG_NET=y 281CONFIG_NET=y
275 282
276# 283#
@@ -426,6 +433,7 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
426# CONFIG_CONNECTOR is not set 433# CONFIG_CONNECTOR is not set
427# CONFIG_MTD is not set 434# CONFIG_MTD is not set
428CONFIG_OF_DEVICE=y 435CONFIG_OF_DEVICE=y
436CONFIG_OF_GPIO=y
429CONFIG_OF_I2C=m 437CONFIG_OF_I2C=m
430CONFIG_PARPORT=m 438CONFIG_PARPORT=m
431CONFIG_PARPORT_PC=m 439CONFIG_PARPORT_PC=m
@@ -452,15 +460,16 @@ CONFIG_BLK_DEV_RAM_SIZE=32768
452# CONFIG_BLK_DEV_XIP is not set 460# CONFIG_BLK_DEV_XIP is not set
453# CONFIG_CDROM_PKTCDVD is not set 461# CONFIG_CDROM_PKTCDVD is not set
454# CONFIG_ATA_OVER_ETH is not set 462# CONFIG_ATA_OVER_ETH is not set
463# CONFIG_BLK_DEV_HD is not set
455CONFIG_MISC_DEVICES=y 464CONFIG_MISC_DEVICES=y
456# CONFIG_PHANTOM is not set 465# CONFIG_PHANTOM is not set
457# CONFIG_EEPROM_93CX6 is not set 466# CONFIG_EEPROM_93CX6 is not set
458# CONFIG_SGI_IOC4 is not set 467# CONFIG_SGI_IOC4 is not set
459# CONFIG_TIFM_CORE is not set 468# CONFIG_TIFM_CORE is not set
460# CONFIG_ENCLOSURE_SERVICES is not set 469# CONFIG_ENCLOSURE_SERVICES is not set
470# CONFIG_HP_ILO is not set
461CONFIG_HAVE_IDE=y 471CONFIG_HAVE_IDE=y
462CONFIG_IDE=y 472CONFIG_IDE=y
463CONFIG_IDE_MAX_HWIFS=4
464CONFIG_BLK_DEV_IDE=y 473CONFIG_BLK_DEV_IDE=y
465 474
466# 475#
@@ -480,7 +489,6 @@ CONFIG_IDE_PROC_FS=y
480# 489#
481# IDE chipset support/bugfixes 490# IDE chipset support/bugfixes
482# 491#
483CONFIG_IDE_GENERIC=y
484# CONFIG_BLK_DEV_PLATFORM is not set 492# CONFIG_BLK_DEV_PLATFORM is not set
485 493
486# 494#
@@ -493,10 +501,8 @@ CONFIG_IDE_GENERIC=y
493# CONFIG_BLK_DEV_AMD74XX is not set 501# CONFIG_BLK_DEV_AMD74XX is not set
494# CONFIG_BLK_DEV_CMD64X is not set 502# CONFIG_BLK_DEV_CMD64X is not set
495# CONFIG_BLK_DEV_TRIFLEX is not set 503# CONFIG_BLK_DEV_TRIFLEX is not set
496# CONFIG_BLK_DEV_CY82C693 is not set
497# CONFIG_BLK_DEV_CS5520 is not set 504# CONFIG_BLK_DEV_CS5520 is not set
498# CONFIG_BLK_DEV_CS5530 is not set 505# CONFIG_BLK_DEV_CS5530 is not set
499# CONFIG_BLK_DEV_HPT34X is not set
500# CONFIG_BLK_DEV_HPT366 is not set 506# CONFIG_BLK_DEV_HPT366 is not set
501# CONFIG_BLK_DEV_JMICRON is not set 507# CONFIG_BLK_DEV_JMICRON is not set
502# CONFIG_BLK_DEV_SC1200 is not set 508# CONFIG_BLK_DEV_SC1200 is not set
@@ -514,8 +520,6 @@ CONFIG_IDE_GENERIC=y
514# CONFIG_BLK_DEV_VIA82CXXX is not set 520# CONFIG_BLK_DEV_VIA82CXXX is not set
515# CONFIG_BLK_DEV_TC86C001 is not set 521# CONFIG_BLK_DEV_TC86C001 is not set
516# CONFIG_BLK_DEV_IDEDMA is not set 522# CONFIG_BLK_DEV_IDEDMA is not set
517# CONFIG_BLK_DEV_HD_ONLY is not set
518# CONFIG_BLK_DEV_HD is not set
519 523
520# 524#
521# SCSI device support 525# SCSI device support
@@ -594,6 +598,7 @@ CONFIG_SCSI_LOWLEVEL=y
594# CONFIG_SCSI_NSP32 is not set 598# CONFIG_SCSI_NSP32 is not set
595# CONFIG_SCSI_DEBUG is not set 599# CONFIG_SCSI_DEBUG is not set
596# CONFIG_SCSI_SRP is not set 600# CONFIG_SCSI_SRP is not set
601# CONFIG_SCSI_DH is not set
597# CONFIG_ATA is not set 602# CONFIG_ATA is not set
598# CONFIG_MD is not set 603# CONFIG_MD is not set
599# CONFIG_FUSION is not set 604# CONFIG_FUSION is not set
@@ -601,12 +606,15 @@ CONFIG_SCSI_LOWLEVEL=y
601# 606#
602# IEEE 1394 (FireWire) support 607# IEEE 1394 (FireWire) support
603# 608#
609
610#
611# Enable only one of the two stacks, unless you know what you are doing
612#
604# CONFIG_FIREWIRE is not set 613# CONFIG_FIREWIRE is not set
605# CONFIG_IEEE1394 is not set 614# CONFIG_IEEE1394 is not set
606# CONFIG_I2O is not set 615# CONFIG_I2O is not set
607# CONFIG_MACINTOSH_DRIVERS is not set 616# CONFIG_MACINTOSH_DRIVERS is not set
608CONFIG_NETDEVICES=y 617CONFIG_NETDEVICES=y
609# CONFIG_NETDEVICES_MULTIQUEUE is not set
610# CONFIG_DUMMY is not set 618# CONFIG_DUMMY is not set
611# CONFIG_BONDING is not set 619# CONFIG_BONDING is not set
612# CONFIG_MACVLAN is not set 620# CONFIG_MACVLAN is not set
@@ -652,7 +660,6 @@ CONFIG_NETDEV_1000=y
652# CONFIG_DL2K is not set 660# CONFIG_DL2K is not set
653# CONFIG_E1000 is not set 661# CONFIG_E1000 is not set
654# CONFIG_E1000E is not set 662# CONFIG_E1000E is not set
655# CONFIG_E1000E_ENABLED is not set
656# CONFIG_IP1000 is not set 663# CONFIG_IP1000 is not set
657# CONFIG_IGB is not set 664# CONFIG_IGB is not set
658# CONFIG_NS83820 is not set 665# CONFIG_NS83820 is not set
@@ -666,9 +673,9 @@ CONFIG_NETDEV_1000=y
666# CONFIG_TIGON3 is not set 673# CONFIG_TIGON3 is not set
667# CONFIG_BNX2 is not set 674# CONFIG_BNX2 is not set
668CONFIG_GIANFAR=y 675CONFIG_GIANFAR=y
669CONFIG_GFAR_NAPI=y
670# CONFIG_QLA3XXX is not set 676# CONFIG_QLA3XXX is not set
671# CONFIG_ATL1 is not set 677# CONFIG_ATL1 is not set
678# CONFIG_ATL1E is not set
672CONFIG_NETDEV_10000=y 679CONFIG_NETDEV_10000=y
673# CONFIG_CHELSIO_T1 is not set 680# CONFIG_CHELSIO_T1 is not set
674# CONFIG_CHELSIO_T3 is not set 681# CONFIG_CHELSIO_T3 is not set
@@ -731,6 +738,7 @@ CONFIG_KEYBOARD_ATKBD=y
731# CONFIG_KEYBOARD_XTKBD is not set 738# CONFIG_KEYBOARD_XTKBD is not set
732# CONFIG_KEYBOARD_NEWTON is not set 739# CONFIG_KEYBOARD_NEWTON is not set
733# CONFIG_KEYBOARD_STOWAWAY is not set 740# CONFIG_KEYBOARD_STOWAWAY is not set
741# CONFIG_KEYBOARD_GPIO is not set
734CONFIG_INPUT_MOUSE=y 742CONFIG_INPUT_MOUSE=y
735CONFIG_MOUSE_PS2=y 743CONFIG_MOUSE_PS2=y
736CONFIG_MOUSE_PS2_ALPS=y 744CONFIG_MOUSE_PS2_ALPS=y
@@ -741,7 +749,9 @@ CONFIG_MOUSE_PS2_TRACKPOINT=y
741# CONFIG_MOUSE_PS2_TOUCHKIT is not set 749# CONFIG_MOUSE_PS2_TOUCHKIT is not set
742# CONFIG_MOUSE_SERIAL is not set 750# CONFIG_MOUSE_SERIAL is not set
743# CONFIG_MOUSE_APPLETOUCH is not set 751# CONFIG_MOUSE_APPLETOUCH is not set
752# CONFIG_MOUSE_BCM5974 is not set
744# CONFIG_MOUSE_VSXXXAA is not set 753# CONFIG_MOUSE_VSXXXAA is not set
754# CONFIG_MOUSE_GPIO is not set
745# CONFIG_INPUT_JOYSTICK is not set 755# CONFIG_INPUT_JOYSTICK is not set
746# CONFIG_INPUT_TABLET is not set 756# CONFIG_INPUT_TABLET is not set
747# CONFIG_INPUT_TOUCHSCREEN is not set 757# CONFIG_INPUT_TOUCHSCREEN is not set
@@ -757,6 +767,7 @@ CONFIG_SERIO_SERPORT=y
757# CONFIG_SERIO_PCIPS2 is not set 767# CONFIG_SERIO_PCIPS2 is not set
758CONFIG_SERIO_LIBPS2=y 768CONFIG_SERIO_LIBPS2=y
759# CONFIG_SERIO_RAW is not set 769# CONFIG_SERIO_RAW is not set
770# CONFIG_SERIO_XILINX_XPS_PS2 is not set
760# CONFIG_GAMEPORT is not set 771# CONFIG_GAMEPORT is not set
761 772
762# 773#
@@ -805,44 +816,68 @@ CONFIG_DEVPORT=y
805CONFIG_I2C=m 816CONFIG_I2C=m
806CONFIG_I2C_BOARDINFO=y 817CONFIG_I2C_BOARDINFO=y
807CONFIG_I2C_CHARDEV=m 818CONFIG_I2C_CHARDEV=m
819CONFIG_I2C_HELPER_AUTO=y
808 820
809# 821#
810# I2C Hardware Bus support 822# I2C Hardware Bus support
811# 823#
824
825#
826# PC SMBus host controller drivers
827#
812# CONFIG_I2C_ALI1535 is not set 828# CONFIG_I2C_ALI1535 is not set
813# CONFIG_I2C_ALI1563 is not set 829# CONFIG_I2C_ALI1563 is not set
814# CONFIG_I2C_ALI15X3 is not set 830# CONFIG_I2C_ALI15X3 is not set
815# CONFIG_I2C_AMD756 is not set 831# CONFIG_I2C_AMD756 is not set
816# CONFIG_I2C_AMD8111 is not set 832# CONFIG_I2C_AMD8111 is not set
817# CONFIG_I2C_I801 is not set 833# CONFIG_I2C_I801 is not set
818# CONFIG_I2C_I810 is not set 834# CONFIG_I2C_ISCH is not set
819# CONFIG_I2C_PIIX4 is not set 835# CONFIG_I2C_PIIX4 is not set
820# CONFIG_I2C_MPC is not set
821# CONFIG_I2C_NFORCE2 is not set 836# CONFIG_I2C_NFORCE2 is not set
822# CONFIG_I2C_OCORES is not set
823# CONFIG_I2C_PARPORT is not set
824# CONFIG_I2C_PARPORT_LIGHT is not set
825# CONFIG_I2C_PROSAVAGE is not set
826# CONFIG_I2C_SAVAGE4 is not set
827# CONFIG_I2C_SIMTEC is not set
828# CONFIG_I2C_SIS5595 is not set 837# CONFIG_I2C_SIS5595 is not set
829# CONFIG_I2C_SIS630 is not set 838# CONFIG_I2C_SIS630 is not set
830# CONFIG_I2C_SIS96X is not set 839# CONFIG_I2C_SIS96X is not set
831# CONFIG_I2C_TAOS_EVM is not set
832# CONFIG_I2C_STUB is not set
833# CONFIG_I2C_VIA is not set 840# CONFIG_I2C_VIA is not set
834# CONFIG_I2C_VIAPRO is not set 841# CONFIG_I2C_VIAPRO is not set
842
843#
844# I2C system bus drivers (mostly embedded / system-on-chip)
845#
846# CONFIG_I2C_CPM is not set
847# CONFIG_I2C_GPIO is not set
848# CONFIG_I2C_MPC is not set
849# CONFIG_I2C_OCORES is not set
850# CONFIG_I2C_SIMTEC is not set
851
852#
853# External I2C/SMBus adapter drivers
854#
855# CONFIG_I2C_PARPORT is not set
856# CONFIG_I2C_PARPORT_LIGHT is not set
857# CONFIG_I2C_TAOS_EVM is not set
858
859#
860# Graphics adapter I2C/DDC channel drivers
861#
835# CONFIG_I2C_VOODOO3 is not set 862# CONFIG_I2C_VOODOO3 is not set
863
864#
865# Other I2C/SMBus bus drivers
866#
836# CONFIG_I2C_PCA_PLATFORM is not set 867# CONFIG_I2C_PCA_PLATFORM is not set
868# CONFIG_I2C_STUB is not set
837 869
838# 870#
839# Miscellaneous I2C Chip support 871# Miscellaneous I2C Chip support
840# 872#
841# CONFIG_DS1682 is not set 873# CONFIG_DS1682 is not set
874# CONFIG_AT24 is not set
842# CONFIG_SENSORS_EEPROM is not set 875# CONFIG_SENSORS_EEPROM is not set
843# CONFIG_SENSORS_PCF8574 is not set 876# CONFIG_SENSORS_PCF8574 is not set
844# CONFIG_PCF8575 is not set 877# CONFIG_PCF8575 is not set
878# CONFIG_SENSORS_PCA9539 is not set
845# CONFIG_SENSORS_PCF8591 is not set 879# CONFIG_SENSORS_PCF8591 is not set
880# CONFIG_TPS65010 is not set
846# CONFIG_SENSORS_MAX6875 is not set 881# CONFIG_SENSORS_MAX6875 is not set
847# CONFIG_SENSORS_TSL2550 is not set 882# CONFIG_SENSORS_TSL2550 is not set
848# CONFIG_I2C_DEBUG_CORE is not set 883# CONFIG_I2C_DEBUG_CORE is not set
@@ -850,10 +885,32 @@ CONFIG_I2C_CHARDEV=m
850# CONFIG_I2C_DEBUG_BUS is not set 885# CONFIG_I2C_DEBUG_BUS is not set
851# CONFIG_I2C_DEBUG_CHIP is not set 886# CONFIG_I2C_DEBUG_CHIP is not set
852# CONFIG_SPI is not set 887# CONFIG_SPI is not set
888CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
889CONFIG_ARCH_REQUIRE_GPIOLIB=y
890CONFIG_GPIOLIB=y
891# CONFIG_DEBUG_GPIO is not set
892# CONFIG_GPIO_SYSFS is not set
893
894#
895# I2C GPIO expanders:
896#
897# CONFIG_GPIO_MAX732X is not set
898# CONFIG_GPIO_PCA953X is not set
899# CONFIG_GPIO_PCF857X is not set
900
901#
902# PCI GPIO expanders:
903#
904# CONFIG_GPIO_BT8XX is not set
905
906#
907# SPI GPIO expanders:
908#
853# CONFIG_W1 is not set 909# CONFIG_W1 is not set
854# CONFIG_POWER_SUPPLY is not set 910# CONFIG_POWER_SUPPLY is not set
855CONFIG_HWMON=y 911CONFIG_HWMON=y
856# CONFIG_HWMON_VID is not set 912# CONFIG_HWMON_VID is not set
913# CONFIG_SENSORS_AD7414 is not set
857# CONFIG_SENSORS_AD7418 is not set 914# CONFIG_SENSORS_AD7418 is not set
858# CONFIG_SENSORS_ADM1021 is not set 915# CONFIG_SENSORS_ADM1021 is not set
859# CONFIG_SENSORS_ADM1025 is not set 916# CONFIG_SENSORS_ADM1025 is not set
@@ -907,6 +964,7 @@ CONFIG_HWMON=y
907# CONFIG_SENSORS_W83627EHF is not set 964# CONFIG_SENSORS_W83627EHF is not set
908# CONFIG_HWMON_DEBUG_CHIP is not set 965# CONFIG_HWMON_DEBUG_CHIP is not set
909# CONFIG_THERMAL is not set 966# CONFIG_THERMAL is not set
967# CONFIG_THERMAL_HWMON is not set
910# CONFIG_WATCHDOG is not set 968# CONFIG_WATCHDOG is not set
911 969
912# 970#
@@ -918,8 +976,10 @@ CONFIG_SSB_POSSIBLE=y
918# 976#
919# Multifunction device drivers 977# Multifunction device drivers
920# 978#
979# CONFIG_MFD_CORE is not set
921# CONFIG_MFD_SM501 is not set 980# CONFIG_MFD_SM501 is not set
922# CONFIG_HTC_PASIC3 is not set 981# CONFIG_HTC_PASIC3 is not set
982# CONFIG_MFD_TMIO is not set
923 983
924# 984#
925# Multimedia devices 985# Multimedia devices
@@ -958,20 +1018,8 @@ CONFIG_DRM=m
958# Display device support 1018# Display device support
959# 1019#
960# CONFIG_DISPLAY_SUPPORT is not set 1020# CONFIG_DISPLAY_SUPPORT is not set
961
962#
963# Sound
964#
965CONFIG_SOUND=m 1021CONFIG_SOUND=m
966
967#
968# Advanced Linux Sound Architecture
969#
970# CONFIG_SND is not set 1022# CONFIG_SND is not set
971
972#
973# Open Sound System
974#
975# CONFIG_SOUND_PRIME is not set 1023# CONFIG_SOUND_PRIME is not set
976CONFIG_HID_SUPPORT=y 1024CONFIG_HID_SUPPORT=y
977CONFIG_HID=y 1025CONFIG_HID=y
@@ -986,6 +1034,10 @@ CONFIG_USB_ARCH_HAS_EHCI=y
986# CONFIG_USB_OTG_BLACKLIST_HUB is not set 1034# CONFIG_USB_OTG_BLACKLIST_HUB is not set
987 1035
988# 1036#
1037# Enable Host or Gadget support to see Inventra options
1038#
1039
1040#
989# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 1041# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
990# 1042#
991# CONFIG_USB_GADGET is not set 1043# CONFIG_USB_GADGET is not set
@@ -1070,6 +1122,7 @@ CONFIG_TMPFS=y
1070CONFIG_CRAMFS=m 1122CONFIG_CRAMFS=m
1071# CONFIG_VXFS_FS is not set 1123# CONFIG_VXFS_FS is not set
1072# CONFIG_MINIX_FS is not set 1124# CONFIG_MINIX_FS is not set
1125# CONFIG_OMFS_FS is not set
1073# CONFIG_HPFS_FS is not set 1126# CONFIG_HPFS_FS is not set
1074# CONFIG_QNX4FS_FS is not set 1127# CONFIG_QNX4FS_FS is not set
1075# CONFIG_ROMFS_FS is not set 1128# CONFIG_ROMFS_FS is not set
@@ -1080,13 +1133,12 @@ CONFIG_NFS_FS=y
1080CONFIG_NFS_V3=y 1133CONFIG_NFS_V3=y
1081# CONFIG_NFS_V3_ACL is not set 1134# CONFIG_NFS_V3_ACL is not set
1082# CONFIG_NFS_V4 is not set 1135# CONFIG_NFS_V4 is not set
1083# CONFIG_NFSD is not set
1084CONFIG_ROOT_NFS=y 1136CONFIG_ROOT_NFS=y
1137# CONFIG_NFSD is not set
1085CONFIG_LOCKD=y 1138CONFIG_LOCKD=y
1086CONFIG_LOCKD_V4=y 1139CONFIG_LOCKD_V4=y
1087CONFIG_NFS_COMMON=y 1140CONFIG_NFS_COMMON=y
1088CONFIG_SUNRPC=y 1141CONFIG_SUNRPC=y
1089# CONFIG_SUNRPC_BIND34 is not set
1090# CONFIG_RPCSEC_GSS_KRB5 is not set 1142# CONFIG_RPCSEC_GSS_KRB5 is not set
1091# CONFIG_RPCSEC_GSS_SPKM3 is not set 1143# CONFIG_RPCSEC_GSS_SPKM3 is not set
1092CONFIG_SMB_FS=m 1144CONFIG_SMB_FS=m
@@ -1150,6 +1202,7 @@ CONFIG_BITREVERSE=y
1150# CONFIG_GENERIC_FIND_FIRST_BIT is not set 1202# CONFIG_GENERIC_FIND_FIRST_BIT is not set
1151CONFIG_CRC_CCITT=y 1203CONFIG_CRC_CCITT=y
1152# CONFIG_CRC16 is not set 1204# CONFIG_CRC16 is not set
1205CONFIG_CRC_T10DIF=m
1153CONFIG_CRC_ITU_T=m 1206CONFIG_CRC_ITU_T=m
1154CONFIG_CRC32=y 1207CONFIG_CRC32=y
1155# CONFIG_CRC7 is not set 1208# CONFIG_CRC7 is not set
@@ -1175,6 +1228,8 @@ CONFIG_FRAME_WARN=1024
1175CONFIG_DEBUG_KERNEL=y 1228CONFIG_DEBUG_KERNEL=y
1176# CONFIG_DEBUG_SHIRQ is not set 1229# CONFIG_DEBUG_SHIRQ is not set
1177CONFIG_DETECT_SOFTLOCKUP=y 1230CONFIG_DETECT_SOFTLOCKUP=y
1231# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
1232CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
1178CONFIG_SCHED_DEBUG=y 1233CONFIG_SCHED_DEBUG=y
1179# CONFIG_SCHEDSTATS is not set 1234# CONFIG_SCHEDSTATS is not set
1180# CONFIG_TIMER_STATS is not set 1235# CONFIG_TIMER_STATS is not set
@@ -1193,18 +1248,29 @@ CONFIG_SCHED_DEBUG=y
1193# CONFIG_DEBUG_INFO is not set 1248# CONFIG_DEBUG_INFO is not set
1194# CONFIG_DEBUG_VM is not set 1249# CONFIG_DEBUG_VM is not set
1195# CONFIG_DEBUG_WRITECOUNT is not set 1250# CONFIG_DEBUG_WRITECOUNT is not set
1251# CONFIG_DEBUG_MEMORY_INIT is not set
1196# CONFIG_DEBUG_LIST is not set 1252# CONFIG_DEBUG_LIST is not set
1197# CONFIG_DEBUG_SG is not set 1253# CONFIG_DEBUG_SG is not set
1198# CONFIG_BOOT_PRINTK_DELAY is not set 1254# CONFIG_BOOT_PRINTK_DELAY is not set
1199# CONFIG_RCU_TORTURE_TEST is not set 1255# CONFIG_RCU_TORTURE_TEST is not set
1200# CONFIG_BACKTRACE_SELF_TEST is not set 1256# CONFIG_BACKTRACE_SELF_TEST is not set
1201# CONFIG_FAULT_INJECTION is not set 1257# CONFIG_FAULT_INJECTION is not set
1258# CONFIG_LATENCYTOP is not set
1259CONFIG_SYSCTL_SYSCALL_CHECK=y
1260CONFIG_HAVE_FTRACE=y
1261CONFIG_HAVE_DYNAMIC_FTRACE=y
1262# CONFIG_FTRACE is not set
1263# CONFIG_SCHED_TRACER is not set
1264# CONFIG_CONTEXT_SWITCH_TRACER is not set
1202# CONFIG_SAMPLES is not set 1265# CONFIG_SAMPLES is not set
1266CONFIG_HAVE_ARCH_KGDB=y
1267# CONFIG_KGDB is not set
1203# CONFIG_DEBUG_STACKOVERFLOW is not set 1268# CONFIG_DEBUG_STACKOVERFLOW is not set
1204# CONFIG_DEBUG_STACK_USAGE is not set 1269# CONFIG_DEBUG_STACK_USAGE is not set
1205# CONFIG_DEBUG_PAGEALLOC is not set 1270# CONFIG_DEBUG_PAGEALLOC is not set
1206# CONFIG_DEBUGGER is not set 1271# CONFIG_CODE_PATCHING_SELFTEST is not set
1207# CONFIG_KGDB_CONSOLE is not set 1272# CONFIG_FTR_FIXUP_SELFTEST is not set
1273# CONFIG_XMON is not set
1208# CONFIG_IRQSTACKS is not set 1274# CONFIG_IRQSTACKS is not set
1209CONFIG_BDI_SWITCH=y 1275CONFIG_BDI_SWITCH=y
1210# CONFIG_PPC_EARLY_DEBUG is not set 1276# CONFIG_PPC_EARLY_DEBUG is not set
@@ -1258,6 +1324,10 @@ CONFIG_CRYPTO=y
1258# CONFIG_CRYPTO_MD4 is not set 1324# CONFIG_CRYPTO_MD4 is not set
1259# CONFIG_CRYPTO_MD5 is not set 1325# CONFIG_CRYPTO_MD5 is not set
1260# CONFIG_CRYPTO_MICHAEL_MIC is not set 1326# CONFIG_CRYPTO_MICHAEL_MIC is not set
1327# CONFIG_CRYPTO_RMD128 is not set
1328# CONFIG_CRYPTO_RMD160 is not set
1329# CONFIG_CRYPTO_RMD256 is not set
1330# CONFIG_CRYPTO_RMD320 is not set
1261# CONFIG_CRYPTO_SHA1 is not set 1331# CONFIG_CRYPTO_SHA1 is not set
1262# CONFIG_CRYPTO_SHA256 is not set 1332# CONFIG_CRYPTO_SHA256 is not set
1263# CONFIG_CRYPTO_SHA512 is not set 1333# CONFIG_CRYPTO_SHA512 is not set
@@ -1290,6 +1360,7 @@ CONFIG_CRYPTO=y
1290# CONFIG_CRYPTO_LZO is not set 1360# CONFIG_CRYPTO_LZO is not set
1291CONFIG_CRYPTO_HW=y 1361CONFIG_CRYPTO_HW=y
1292# CONFIG_CRYPTO_DEV_HIFN_795X is not set 1362# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1293# CONFIG_PPC_CLOCK is not set 1363# CONFIG_CRYPTO_DEV_TALITOS is not set
1364CONFIG_PPC_CLOCK=y
1294CONFIG_PPC_LIB_RHEAP=y 1365CONFIG_PPC_LIB_RHEAP=y
1295# CONFIG_VIRTUALIZATION is not set 1366# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/configs/85xx/tqm8540_defconfig b/arch/powerpc/configs/85xx/tqm8540_defconfig
index e0b5559e84aa..1b2d5d577915 100644
--- a/arch/powerpc/configs/85xx/tqm8540_defconfig
+++ b/arch/powerpc/configs/85xx/tqm8540_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc5 3# Linux kernel version: 2.6.27-rc4
4# Mon Jun 9 08:52:39 2008 4# Thu Aug 21 00:52:37 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -15,6 +15,7 @@ CONFIG_PPC_85xx=y
15# CONFIG_44x is not set 15# CONFIG_44x is not set
16# CONFIG_E200 is not set 16# CONFIG_E200 is not set
17CONFIG_E500=y 17CONFIG_E500=y
18# CONFIG_PPC_E500MC is not set
18CONFIG_BOOKE=y 19CONFIG_BOOKE=y
19CONFIG_FSL_BOOKE=y 20CONFIG_FSL_BOOKE=y
20CONFIG_FSL_EMB_PERFMON=y 21CONFIG_FSL_EMB_PERFMON=y
@@ -33,6 +34,7 @@ CONFIG_GENERIC_HARDIRQS=y
33# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set 34# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
34CONFIG_IRQ_PER_CPU=y 35CONFIG_IRQ_PER_CPU=y
35CONFIG_STACKTRACE_SUPPORT=y 36CONFIG_STACKTRACE_SUPPORT=y
37CONFIG_HAVE_LATENCYTOP_SUPPORT=y
36CONFIG_LOCKDEP_SUPPORT=y 38CONFIG_LOCKDEP_SUPPORT=y
37CONFIG_RWSEM_XCHGADD_ALGORITHM=y 39CONFIG_RWSEM_XCHGADD_ALGORITHM=y
38CONFIG_ARCH_HAS_ILOG2_U32=y 40CONFIG_ARCH_HAS_ILOG2_U32=y
@@ -89,7 +91,6 @@ CONFIG_INITRAMFS_SOURCE=""
89CONFIG_SYSCTL=y 91CONFIG_SYSCTL=y
90CONFIG_EMBEDDED=y 92CONFIG_EMBEDDED=y
91CONFIG_SYSCTL_SYSCALL=y 93CONFIG_SYSCTL_SYSCALL=y
92CONFIG_SYSCTL_SYSCALL_CHECK=y
93# CONFIG_KALLSYMS is not set 94# CONFIG_KALLSYMS is not set
94# CONFIG_HOTPLUG is not set 95# CONFIG_HOTPLUG is not set
95CONFIG_PRINTK=y 96CONFIG_PRINTK=y
@@ -112,10 +113,16 @@ CONFIG_SLUB=y
112# CONFIG_PROFILING is not set 113# CONFIG_PROFILING is not set
113# CONFIG_MARKERS is not set 114# CONFIG_MARKERS is not set
114CONFIG_HAVE_OPROFILE=y 115CONFIG_HAVE_OPROFILE=y
116CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
117CONFIG_HAVE_IOREMAP_PROT=y
115CONFIG_HAVE_KPROBES=y 118CONFIG_HAVE_KPROBES=y
116CONFIG_HAVE_KRETPROBES=y 119CONFIG_HAVE_KRETPROBES=y
120CONFIG_HAVE_ARCH_TRACEHOOK=y
117# CONFIG_HAVE_DMA_ATTRS is not set 121# CONFIG_HAVE_DMA_ATTRS is not set
122# CONFIG_USE_GENERIC_SMP_HELPERS is not set
123# CONFIG_HAVE_CLK is not set
118CONFIG_PROC_PAGE_MONITOR=y 124CONFIG_PROC_PAGE_MONITOR=y
125# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
119CONFIG_SLABINFO=y 126CONFIG_SLABINFO=y
120CONFIG_RT_MUTEXES=y 127CONFIG_RT_MUTEXES=y
121# CONFIG_TINY_SHMEM is not set 128# CONFIG_TINY_SHMEM is not set
@@ -126,6 +133,7 @@ CONFIG_BLOCK=y
126# CONFIG_BLK_DEV_IO_TRACE is not set 133# CONFIG_BLK_DEV_IO_TRACE is not set
127# CONFIG_LSF is not set 134# CONFIG_LSF is not set
128# CONFIG_BLK_DEV_BSG is not set 135# CONFIG_BLK_DEV_BSG is not set
136# CONFIG_BLK_DEV_INTEGRITY is not set
129 137
130# 138#
131# IO Schedulers 139# IO Schedulers
@@ -144,8 +152,6 @@ CONFIG_CLASSIC_RCU=y
144# 152#
145# Platform support 153# Platform support
146# 154#
147# CONFIG_PPC_MPC512x is not set
148# CONFIG_PPC_MPC5121 is not set
149# CONFIG_PPC_CELL is not set 155# CONFIG_PPC_CELL is not set
150# CONFIG_PPC_CELL_NATIVE is not set 156# CONFIG_PPC_CELL_NATIVE is not set
151# CONFIG_PQ2ADS is not set 157# CONFIG_PQ2ADS is not set
@@ -154,11 +160,13 @@ CONFIG_MPC85xx=y
154# CONFIG_MPC8560_ADS is not set 160# CONFIG_MPC8560_ADS is not set
155# CONFIG_MPC85xx_CDS is not set 161# CONFIG_MPC85xx_CDS is not set
156# CONFIG_MPC85xx_MDS is not set 162# CONFIG_MPC85xx_MDS is not set
163# CONFIG_MPC8536_DS is not set
157# CONFIG_MPC85xx_DS is not set 164# CONFIG_MPC85xx_DS is not set
158# CONFIG_KSI8560 is not set 165# CONFIG_KSI8560 is not set
159# CONFIG_STX_GP3 is not set 166# CONFIG_STX_GP3 is not set
160CONFIG_TQM8540=y 167CONFIG_TQM8540=y
161# CONFIG_TQM8541 is not set 168# CONFIG_TQM8541 is not set
169# CONFIG_TQM8548 is not set
162# CONFIG_TQM8555 is not set 170# CONFIG_TQM8555 is not set
163# CONFIG_TQM8560 is not set 171# CONFIG_TQM8560 is not set
164# CONFIG_SBC8548 is not set 172# CONFIG_SBC8548 is not set
@@ -214,6 +222,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
214# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set 222# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
215CONFIG_PAGEFLAGS_EXTENDED=y 223CONFIG_PAGEFLAGS_EXTENDED=y
216CONFIG_SPLIT_PTLOCK_CPUS=4 224CONFIG_SPLIT_PTLOCK_CPUS=4
225CONFIG_MIGRATION=y
217# CONFIG_RESOURCES_64BIT is not set 226# CONFIG_RESOURCES_64BIT is not set
218CONFIG_ZONE_DMA_FLAG=1 227CONFIG_ZONE_DMA_FLAG=1
219CONFIG_BOUNCE=y 228CONFIG_BOUNCE=y
@@ -221,6 +230,7 @@ CONFIG_VIRT_TO_BUS=y
221CONFIG_FORCE_MAX_ZONEORDER=11 230CONFIG_FORCE_MAX_ZONEORDER=11
222# CONFIG_PROC_DEVICETREE is not set 231# CONFIG_PROC_DEVICETREE is not set
223# CONFIG_CMDLINE_BOOL is not set 232# CONFIG_CMDLINE_BOOL is not set
233CONFIG_EXTRA_TARGETS=""
224# CONFIG_PM is not set 234# CONFIG_PM is not set
225CONFIG_SECCOMP=y 235CONFIG_SECCOMP=y
226CONFIG_ISA_DMA_API=y 236CONFIG_ISA_DMA_API=y
@@ -232,6 +242,7 @@ CONFIG_ZONE_DMA=y
232CONFIG_PPC_INDIRECT_PCI=y 242CONFIG_PPC_INDIRECT_PCI=y
233CONFIG_FSL_SOC=y 243CONFIG_FSL_SOC=y
234CONFIG_FSL_PCI=y 244CONFIG_FSL_PCI=y
245CONFIG_PPC_PCI_CHOICE=y
235CONFIG_PCI=y 246CONFIG_PCI=y
236CONFIG_PCI_DOMAINS=y 247CONFIG_PCI_DOMAINS=y
237CONFIG_PCI_SYSCALL=y 248CONFIG_PCI_SYSCALL=y
@@ -255,10 +266,6 @@ CONFIG_KERNEL_START=0xc0000000
255CONFIG_PHYSICAL_START=0x00000000 266CONFIG_PHYSICAL_START=0x00000000
256CONFIG_PHYSICAL_ALIGN=0x10000000 267CONFIG_PHYSICAL_ALIGN=0x10000000
257CONFIG_TASK_SIZE=0xc0000000 268CONFIG_TASK_SIZE=0xc0000000
258
259#
260# Networking
261#
262CONFIG_NET=y 269CONFIG_NET=y
263 270
264# 271#
@@ -449,20 +456,22 @@ CONFIG_BLK_DEV_RAM_SIZE=32768
449# CONFIG_BLK_DEV_XIP is not set 456# CONFIG_BLK_DEV_XIP is not set
450# CONFIG_CDROM_PKTCDVD is not set 457# CONFIG_CDROM_PKTCDVD is not set
451# CONFIG_ATA_OVER_ETH is not set 458# CONFIG_ATA_OVER_ETH is not set
459# CONFIG_BLK_DEV_HD is not set
452CONFIG_MISC_DEVICES=y 460CONFIG_MISC_DEVICES=y
453# CONFIG_PHANTOM is not set 461# CONFIG_PHANTOM is not set
454# CONFIG_EEPROM_93CX6 is not set 462# CONFIG_EEPROM_93CX6 is not set
455# CONFIG_SGI_IOC4 is not set 463# CONFIG_SGI_IOC4 is not set
456# CONFIG_TIFM_CORE is not set 464# CONFIG_TIFM_CORE is not set
457# CONFIG_ENCLOSURE_SERVICES is not set 465# CONFIG_ENCLOSURE_SERVICES is not set
466# CONFIG_HP_ILO is not set
458CONFIG_HAVE_IDE=y 467CONFIG_HAVE_IDE=y
459CONFIG_IDE=y 468CONFIG_IDE=y
460CONFIG_IDE_MAX_HWIFS=4
461CONFIG_BLK_DEV_IDE=y 469CONFIG_BLK_DEV_IDE=y
462 470
463# 471#
464# Please see Documentation/ide/ide.txt for help/info on IDE drives 472# Please see Documentation/ide/ide.txt for help/info on IDE drives
465# 473#
474CONFIG_IDE_TIMINGS=y
466# CONFIG_BLK_DEV_IDE_SATA is not set 475# CONFIG_BLK_DEV_IDE_SATA is not set
467CONFIG_BLK_DEV_IDEDISK=y 476CONFIG_BLK_DEV_IDEDISK=y
468# CONFIG_IDEDISK_MULTI_MODE is not set 477# CONFIG_IDEDISK_MULTI_MODE is not set
@@ -475,7 +484,6 @@ CONFIG_IDE_PROC_FS=y
475# 484#
476# IDE chipset support/bugfixes 485# IDE chipset support/bugfixes
477# 486#
478CONFIG_IDE_GENERIC=y
479# CONFIG_BLK_DEV_PLATFORM is not set 487# CONFIG_BLK_DEV_PLATFORM is not set
480CONFIG_BLK_DEV_IDEDMA_SFF=y 488CONFIG_BLK_DEV_IDEDMA_SFF=y
481 489
@@ -493,10 +501,8 @@ CONFIG_BLK_DEV_IDEDMA_PCI=y
493# CONFIG_BLK_DEV_AMD74XX is not set 501# CONFIG_BLK_DEV_AMD74XX is not set
494# CONFIG_BLK_DEV_CMD64X is not set 502# CONFIG_BLK_DEV_CMD64X is not set
495# CONFIG_BLK_DEV_TRIFLEX is not set 503# CONFIG_BLK_DEV_TRIFLEX is not set
496# CONFIG_BLK_DEV_CY82C693 is not set
497# CONFIG_BLK_DEV_CS5520 is not set 504# CONFIG_BLK_DEV_CS5520 is not set
498# CONFIG_BLK_DEV_CS5530 is not set 505# CONFIG_BLK_DEV_CS5530 is not set
499# CONFIG_BLK_DEV_HPT34X is not set
500# CONFIG_BLK_DEV_HPT366 is not set 506# CONFIG_BLK_DEV_HPT366 is not set
501# CONFIG_BLK_DEV_JMICRON is not set 507# CONFIG_BLK_DEV_JMICRON is not set
502# CONFIG_BLK_DEV_SC1200 is not set 508# CONFIG_BLK_DEV_SC1200 is not set
@@ -514,8 +520,6 @@ CONFIG_BLK_DEV_IDEDMA_PCI=y
514CONFIG_BLK_DEV_VIA82CXXX=y 520CONFIG_BLK_DEV_VIA82CXXX=y
515# CONFIG_BLK_DEV_TC86C001 is not set 521# CONFIG_BLK_DEV_TC86C001 is not set
516CONFIG_BLK_DEV_IDEDMA=y 522CONFIG_BLK_DEV_IDEDMA=y
517# CONFIG_BLK_DEV_HD_ONLY is not set
518# CONFIG_BLK_DEV_HD is not set
519 523
520# 524#
521# SCSI device support 525# SCSI device support
@@ -531,12 +535,15 @@ CONFIG_BLK_DEV_IDEDMA=y
531# 535#
532# IEEE 1394 (FireWire) support 536# IEEE 1394 (FireWire) support
533# 537#
538
539#
540# Enable only one of the two stacks, unless you know what you are doing
541#
534# CONFIG_FIREWIRE is not set 542# CONFIG_FIREWIRE is not set
535# CONFIG_IEEE1394 is not set 543# CONFIG_IEEE1394 is not set
536# CONFIG_I2O is not set 544# CONFIG_I2O is not set
537# CONFIG_MACINTOSH_DRIVERS is not set 545# CONFIG_MACINTOSH_DRIVERS is not set
538CONFIG_NETDEVICES=y 546CONFIG_NETDEVICES=y
539# CONFIG_NETDEVICES_MULTIQUEUE is not set
540# CONFIG_DUMMY is not set 547# CONFIG_DUMMY is not set
541# CONFIG_BONDING is not set 548# CONFIG_BONDING is not set
542# CONFIG_MACVLAN is not set 549# CONFIG_MACVLAN is not set
@@ -598,7 +605,6 @@ CONFIG_NETDEV_1000=y
598# CONFIG_DL2K is not set 605# CONFIG_DL2K is not set
599# CONFIG_E1000 is not set 606# CONFIG_E1000 is not set
600# CONFIG_E1000E is not set 607# CONFIG_E1000E is not set
601# CONFIG_E1000E_ENABLED is not set
602# CONFIG_IP1000 is not set 608# CONFIG_IP1000 is not set
603# CONFIG_IGB is not set 609# CONFIG_IGB is not set
604# CONFIG_NS83820 is not set 610# CONFIG_NS83820 is not set
@@ -612,9 +618,9 @@ CONFIG_NETDEV_1000=y
612# CONFIG_TIGON3 is not set 618# CONFIG_TIGON3 is not set
613# CONFIG_BNX2 is not set 619# CONFIG_BNX2 is not set
614CONFIG_GIANFAR=y 620CONFIG_GIANFAR=y
615CONFIG_GFAR_NAPI=y
616# CONFIG_QLA3XXX is not set 621# CONFIG_QLA3XXX is not set
617# CONFIG_ATL1 is not set 622# CONFIG_ATL1 is not set
623# CONFIG_ATL1E is not set
618CONFIG_NETDEV_10000=y 624CONFIG_NETDEV_10000=y
619# CONFIG_CHELSIO_T1 is not set 625# CONFIG_CHELSIO_T1 is not set
620# CONFIG_CHELSIO_T3 is not set 626# CONFIG_CHELSIO_T3 is not set
@@ -721,41 +727,62 @@ CONFIG_DEVPORT=y
721CONFIG_I2C=y 727CONFIG_I2C=y
722CONFIG_I2C_BOARDINFO=y 728CONFIG_I2C_BOARDINFO=y
723CONFIG_I2C_CHARDEV=y 729CONFIG_I2C_CHARDEV=y
730CONFIG_I2C_HELPER_AUTO=y
724 731
725# 732#
726# I2C Hardware Bus support 733# I2C Hardware Bus support
727# 734#
735
736#
737# PC SMBus host controller drivers
738#
728# CONFIG_I2C_ALI1535 is not set 739# CONFIG_I2C_ALI1535 is not set
729# CONFIG_I2C_ALI1563 is not set 740# CONFIG_I2C_ALI1563 is not set
730# CONFIG_I2C_ALI15X3 is not set 741# CONFIG_I2C_ALI15X3 is not set
731# CONFIG_I2C_AMD756 is not set 742# CONFIG_I2C_AMD756 is not set
732# CONFIG_I2C_AMD8111 is not set 743# CONFIG_I2C_AMD8111 is not set
733# CONFIG_I2C_I801 is not set 744# CONFIG_I2C_I801 is not set
734# CONFIG_I2C_I810 is not set 745# CONFIG_I2C_ISCH is not set
735# CONFIG_I2C_PIIX4 is not set 746# CONFIG_I2C_PIIX4 is not set
736CONFIG_I2C_MPC=y
737# CONFIG_I2C_NFORCE2 is not set 747# CONFIG_I2C_NFORCE2 is not set
738# CONFIG_I2C_OCORES is not set
739# CONFIG_I2C_PARPORT_LIGHT is not set
740# CONFIG_I2C_PROSAVAGE is not set
741# CONFIG_I2C_SAVAGE4 is not set
742# CONFIG_I2C_SIMTEC is not set
743# CONFIG_I2C_SIS5595 is not set 748# CONFIG_I2C_SIS5595 is not set
744# CONFIG_I2C_SIS630 is not set 749# CONFIG_I2C_SIS630 is not set
745# CONFIG_I2C_SIS96X is not set 750# CONFIG_I2C_SIS96X is not set
746# CONFIG_I2C_TAOS_EVM is not set
747# CONFIG_I2C_VIA is not set 751# CONFIG_I2C_VIA is not set
748# CONFIG_I2C_VIAPRO is not set 752# CONFIG_I2C_VIAPRO is not set
753
754#
755# I2C system bus drivers (mostly embedded / system-on-chip)
756#
757CONFIG_I2C_MPC=y
758# CONFIG_I2C_OCORES is not set
759# CONFIG_I2C_SIMTEC is not set
760
761#
762# External I2C/SMBus adapter drivers
763#
764# CONFIG_I2C_PARPORT_LIGHT is not set
765# CONFIG_I2C_TAOS_EVM is not set
766
767#
768# Graphics adapter I2C/DDC channel drivers
769#
749# CONFIG_I2C_VOODOO3 is not set 770# CONFIG_I2C_VOODOO3 is not set
771
772#
773# Other I2C/SMBus bus drivers
774#
750# CONFIG_I2C_PCA_PLATFORM is not set 775# CONFIG_I2C_PCA_PLATFORM is not set
751 776
752# 777#
753# Miscellaneous I2C Chip support 778# Miscellaneous I2C Chip support
754# 779#
755# CONFIG_DS1682 is not set 780# CONFIG_DS1682 is not set
781# CONFIG_AT24 is not set
756# CONFIG_SENSORS_EEPROM is not set 782# CONFIG_SENSORS_EEPROM is not set
757# CONFIG_SENSORS_PCF8574 is not set 783# CONFIG_SENSORS_PCF8574 is not set
758# CONFIG_PCF8575 is not set 784# CONFIG_PCF8575 is not set
785# CONFIG_SENSORS_PCA9539 is not set
759# CONFIG_SENSORS_PCF8591 is not set 786# CONFIG_SENSORS_PCF8591 is not set
760# CONFIG_SENSORS_MAX6875 is not set 787# CONFIG_SENSORS_MAX6875 is not set
761# CONFIG_SENSORS_TSL2550 is not set 788# CONFIG_SENSORS_TSL2550 is not set
@@ -764,10 +791,13 @@ CONFIG_I2C_MPC=y
764# CONFIG_I2C_DEBUG_BUS is not set 791# CONFIG_I2C_DEBUG_BUS is not set
765# CONFIG_I2C_DEBUG_CHIP is not set 792# CONFIG_I2C_DEBUG_CHIP is not set
766# CONFIG_SPI is not set 793# CONFIG_SPI is not set
794CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
795# CONFIG_GPIOLIB is not set
767# CONFIG_W1 is not set 796# CONFIG_W1 is not set
768# CONFIG_POWER_SUPPLY is not set 797# CONFIG_POWER_SUPPLY is not set
769CONFIG_HWMON=y 798CONFIG_HWMON=y
770# CONFIG_HWMON_VID is not set 799# CONFIG_HWMON_VID is not set
800# CONFIG_SENSORS_AD7414 is not set
771# CONFIG_SENSORS_AD7418 is not set 801# CONFIG_SENSORS_AD7418 is not set
772# CONFIG_SENSORS_ADM1021 is not set 802# CONFIG_SENSORS_ADM1021 is not set
773# CONFIG_SENSORS_ADM1025 is not set 803# CONFIG_SENSORS_ADM1025 is not set
@@ -821,6 +851,7 @@ CONFIG_SENSORS_LM75=y
821# CONFIG_SENSORS_W83627EHF is not set 851# CONFIG_SENSORS_W83627EHF is not set
822CONFIG_HWMON_DEBUG_CHIP=y 852CONFIG_HWMON_DEBUG_CHIP=y
823# CONFIG_THERMAL is not set 853# CONFIG_THERMAL is not set
854# CONFIG_THERMAL_HWMON is not set
824# CONFIG_WATCHDOG is not set 855# CONFIG_WATCHDOG is not set
825 856
826# 857#
@@ -832,8 +863,10 @@ CONFIG_SSB_POSSIBLE=y
832# 863#
833# Multifunction device drivers 864# Multifunction device drivers
834# 865#
866# CONFIG_MFD_CORE is not set
835# CONFIG_MFD_SM501 is not set 867# CONFIG_MFD_SM501 is not set
836# CONFIG_HTC_PASIC3 is not set 868# CONFIG_HTC_PASIC3 is not set
869# CONFIG_MFD_TMIO is not set
837 870
838# 871#
839# Multimedia devices 872# Multimedia devices
@@ -865,10 +898,6 @@ CONFIG_DAB=y
865# Display device support 898# Display device support
866# 899#
867# CONFIG_DISPLAY_SUPPORT is not set 900# CONFIG_DISPLAY_SUPPORT is not set
868
869#
870# Sound
871#
872# CONFIG_SOUND is not set 901# CONFIG_SOUND is not set
873CONFIG_HID_SUPPORT=y 902CONFIG_HID_SUPPORT=y
874CONFIG_HID=y 903CONFIG_HID=y
@@ -883,6 +912,10 @@ CONFIG_USB_ARCH_HAS_EHCI=y
883# CONFIG_USB_OTG_BLACKLIST_HUB is not set 912# CONFIG_USB_OTG_BLACKLIST_HUB is not set
884 913
885# 914#
915# Enable Host or Gadget support to see Inventra options
916#
917
918#
886# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 919# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
887# 920#
888# CONFIG_USB_GADGET is not set 921# CONFIG_USB_GADGET is not set
@@ -971,6 +1004,7 @@ CONFIG_JFFS2_RTIME=y
971CONFIG_CRAMFS=y 1004CONFIG_CRAMFS=y
972# CONFIG_VXFS_FS is not set 1005# CONFIG_VXFS_FS is not set
973# CONFIG_MINIX_FS is not set 1006# CONFIG_MINIX_FS is not set
1007# CONFIG_OMFS_FS is not set
974# CONFIG_HPFS_FS is not set 1008# CONFIG_HPFS_FS is not set
975# CONFIG_QNX4FS_FS is not set 1009# CONFIG_QNX4FS_FS is not set
976# CONFIG_ROMFS_FS is not set 1010# CONFIG_ROMFS_FS is not set
@@ -980,12 +1014,11 @@ CONFIG_NETWORK_FILESYSTEMS=y
980CONFIG_NFS_FS=y 1014CONFIG_NFS_FS=y
981# CONFIG_NFS_V3 is not set 1015# CONFIG_NFS_V3 is not set
982# CONFIG_NFS_V4 is not set 1016# CONFIG_NFS_V4 is not set
983# CONFIG_NFSD is not set
984CONFIG_ROOT_NFS=y 1017CONFIG_ROOT_NFS=y
1018# CONFIG_NFSD is not set
985CONFIG_LOCKD=y 1019CONFIG_LOCKD=y
986CONFIG_NFS_COMMON=y 1020CONFIG_NFS_COMMON=y
987CONFIG_SUNRPC=y 1021CONFIG_SUNRPC=y
988# CONFIG_SUNRPC_BIND34 is not set
989# CONFIG_RPCSEC_GSS_KRB5 is not set 1022# CONFIG_RPCSEC_GSS_KRB5 is not set
990# CONFIG_RPCSEC_GSS_SPKM3 is not set 1023# CONFIG_RPCSEC_GSS_SPKM3 is not set
991# CONFIG_SMB_FS is not set 1024# CONFIG_SMB_FS is not set
@@ -1021,6 +1054,7 @@ CONFIG_BITREVERSE=y
1021# CONFIG_GENERIC_FIND_FIRST_BIT is not set 1054# CONFIG_GENERIC_FIND_FIRST_BIT is not set
1022# CONFIG_CRC_CCITT is not set 1055# CONFIG_CRC_CCITT is not set
1023# CONFIG_CRC16 is not set 1056# CONFIG_CRC16 is not set
1057# CONFIG_CRC_T10DIF is not set
1024# CONFIG_CRC_ITU_T is not set 1058# CONFIG_CRC_ITU_T is not set
1025CONFIG_CRC32=y 1059CONFIG_CRC32=y
1026# CONFIG_CRC7 is not set 1060# CONFIG_CRC7 is not set
@@ -1048,7 +1082,16 @@ CONFIG_FRAME_WARN=1024
1048# CONFIG_SLUB_DEBUG_ON is not set 1082# CONFIG_SLUB_DEBUG_ON is not set
1049# CONFIG_SLUB_STATS is not set 1083# CONFIG_SLUB_STATS is not set
1050# CONFIG_DEBUG_BUGVERBOSE is not set 1084# CONFIG_DEBUG_BUGVERBOSE is not set
1085# CONFIG_DEBUG_MEMORY_INIT is not set
1086# CONFIG_LATENCYTOP is not set
1087CONFIG_SYSCTL_SYSCALL_CHECK=y
1088CONFIG_HAVE_FTRACE=y
1089CONFIG_HAVE_DYNAMIC_FTRACE=y
1090# CONFIG_FTRACE is not set
1091# CONFIG_SCHED_TRACER is not set
1092# CONFIG_CONTEXT_SWITCH_TRACER is not set
1051# CONFIG_SAMPLES is not set 1093# CONFIG_SAMPLES is not set
1094CONFIG_HAVE_ARCH_KGDB=y
1052# CONFIG_IRQSTACKS is not set 1095# CONFIG_IRQSTACKS is not set
1053# CONFIG_PPC_EARLY_DEBUG is not set 1096# CONFIG_PPC_EARLY_DEBUG is not set
1054 1097
@@ -1100,6 +1143,10 @@ CONFIG_CRYPTO=y
1100# CONFIG_CRYPTO_MD4 is not set 1143# CONFIG_CRYPTO_MD4 is not set
1101# CONFIG_CRYPTO_MD5 is not set 1144# CONFIG_CRYPTO_MD5 is not set
1102# CONFIG_CRYPTO_MICHAEL_MIC is not set 1145# CONFIG_CRYPTO_MICHAEL_MIC is not set
1146# CONFIG_CRYPTO_RMD128 is not set
1147# CONFIG_CRYPTO_RMD160 is not set
1148# CONFIG_CRYPTO_RMD256 is not set
1149# CONFIG_CRYPTO_RMD320 is not set
1103# CONFIG_CRYPTO_SHA1 is not set 1150# CONFIG_CRYPTO_SHA1 is not set
1104# CONFIG_CRYPTO_SHA256 is not set 1151# CONFIG_CRYPTO_SHA256 is not set
1105# CONFIG_CRYPTO_SHA512 is not set 1152# CONFIG_CRYPTO_SHA512 is not set
@@ -1132,5 +1179,6 @@ CONFIG_CRYPTO=y
1132# CONFIG_CRYPTO_LZO is not set 1179# CONFIG_CRYPTO_LZO is not set
1133CONFIG_CRYPTO_HW=y 1180CONFIG_CRYPTO_HW=y
1134# CONFIG_CRYPTO_DEV_HIFN_795X is not set 1181# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1182# CONFIG_CRYPTO_DEV_TALITOS is not set
1135# CONFIG_PPC_CLOCK is not set 1183# CONFIG_PPC_CLOCK is not set
1136# CONFIG_VIRTUALIZATION is not set 1184# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/configs/85xx/tqm8541_defconfig b/arch/powerpc/configs/85xx/tqm8541_defconfig
index 6f9067b49e07..da841a09755c 100644
--- a/arch/powerpc/configs/85xx/tqm8541_defconfig
+++ b/arch/powerpc/configs/85xx/tqm8541_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc5 3# Linux kernel version: 2.6.27-rc4
4# Mon Jun 9 08:52:40 2008 4# Thu Aug 21 00:52:39 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -15,6 +15,7 @@ CONFIG_PPC_85xx=y
15# CONFIG_44x is not set 15# CONFIG_44x is not set
16# CONFIG_E200 is not set 16# CONFIG_E200 is not set
17CONFIG_E500=y 17CONFIG_E500=y
18# CONFIG_PPC_E500MC is not set
18CONFIG_BOOKE=y 19CONFIG_BOOKE=y
19CONFIG_FSL_BOOKE=y 20CONFIG_FSL_BOOKE=y
20CONFIG_FSL_EMB_PERFMON=y 21CONFIG_FSL_EMB_PERFMON=y
@@ -33,12 +34,14 @@ CONFIG_GENERIC_HARDIRQS=y
33# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set 34# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
34CONFIG_IRQ_PER_CPU=y 35CONFIG_IRQ_PER_CPU=y
35CONFIG_STACKTRACE_SUPPORT=y 36CONFIG_STACKTRACE_SUPPORT=y
37CONFIG_HAVE_LATENCYTOP_SUPPORT=y
36CONFIG_LOCKDEP_SUPPORT=y 38CONFIG_LOCKDEP_SUPPORT=y
37CONFIG_RWSEM_XCHGADD_ALGORITHM=y 39CONFIG_RWSEM_XCHGADD_ALGORITHM=y
38CONFIG_ARCH_HAS_ILOG2_U32=y 40CONFIG_ARCH_HAS_ILOG2_U32=y
39CONFIG_GENERIC_HWEIGHT=y 41CONFIG_GENERIC_HWEIGHT=y
40CONFIG_GENERIC_CALIBRATE_DELAY=y 42CONFIG_GENERIC_CALIBRATE_DELAY=y
41CONFIG_GENERIC_FIND_NEXT_BIT=y 43CONFIG_GENERIC_FIND_NEXT_BIT=y
44CONFIG_GENERIC_GPIO=y
42# CONFIG_ARCH_NO_VIRT_TO_BUS is not set 45# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
43CONFIG_PPC=y 46CONFIG_PPC=y
44CONFIG_EARLY_PRINTK=y 47CONFIG_EARLY_PRINTK=y
@@ -89,7 +92,6 @@ CONFIG_INITRAMFS_SOURCE=""
89CONFIG_SYSCTL=y 92CONFIG_SYSCTL=y
90CONFIG_EMBEDDED=y 93CONFIG_EMBEDDED=y
91CONFIG_SYSCTL_SYSCALL=y 94CONFIG_SYSCTL_SYSCALL=y
92CONFIG_SYSCTL_SYSCALL_CHECK=y
93# CONFIG_KALLSYMS is not set 95# CONFIG_KALLSYMS is not set
94# CONFIG_HOTPLUG is not set 96# CONFIG_HOTPLUG is not set
95CONFIG_PRINTK=y 97CONFIG_PRINTK=y
@@ -112,10 +114,16 @@ CONFIG_SLUB=y
112# CONFIG_PROFILING is not set 114# CONFIG_PROFILING is not set
113# CONFIG_MARKERS is not set 115# CONFIG_MARKERS is not set
114CONFIG_HAVE_OPROFILE=y 116CONFIG_HAVE_OPROFILE=y
117CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
118CONFIG_HAVE_IOREMAP_PROT=y
115CONFIG_HAVE_KPROBES=y 119CONFIG_HAVE_KPROBES=y
116CONFIG_HAVE_KRETPROBES=y 120CONFIG_HAVE_KRETPROBES=y
121CONFIG_HAVE_ARCH_TRACEHOOK=y
117# CONFIG_HAVE_DMA_ATTRS is not set 122# CONFIG_HAVE_DMA_ATTRS is not set
123# CONFIG_USE_GENERIC_SMP_HELPERS is not set
124CONFIG_HAVE_CLK=y
118CONFIG_PROC_PAGE_MONITOR=y 125CONFIG_PROC_PAGE_MONITOR=y
126# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
119CONFIG_SLABINFO=y 127CONFIG_SLABINFO=y
120CONFIG_RT_MUTEXES=y 128CONFIG_RT_MUTEXES=y
121# CONFIG_TINY_SHMEM is not set 129# CONFIG_TINY_SHMEM is not set
@@ -126,6 +134,7 @@ CONFIG_BLOCK=y
126# CONFIG_BLK_DEV_IO_TRACE is not set 134# CONFIG_BLK_DEV_IO_TRACE is not set
127# CONFIG_LSF is not set 135# CONFIG_LSF is not set
128# CONFIG_BLK_DEV_BSG is not set 136# CONFIG_BLK_DEV_BSG is not set
137# CONFIG_BLK_DEV_INTEGRITY is not set
129 138
130# 139#
131# IO Schedulers 140# IO Schedulers
@@ -144,8 +153,6 @@ CONFIG_CLASSIC_RCU=y
144# 153#
145# Platform support 154# Platform support
146# 155#
147# CONFIG_PPC_MPC512x is not set
148# CONFIG_PPC_MPC5121 is not set
149# CONFIG_PPC_CELL is not set 156# CONFIG_PPC_CELL is not set
150# CONFIG_PPC_CELL_NATIVE is not set 157# CONFIG_PPC_CELL_NATIVE is not set
151# CONFIG_PQ2ADS is not set 158# CONFIG_PQ2ADS is not set
@@ -154,11 +161,13 @@ CONFIG_MPC85xx=y
154# CONFIG_MPC8560_ADS is not set 161# CONFIG_MPC8560_ADS is not set
155# CONFIG_MPC85xx_CDS is not set 162# CONFIG_MPC85xx_CDS is not set
156# CONFIG_MPC85xx_MDS is not set 163# CONFIG_MPC85xx_MDS is not set
164# CONFIG_MPC8536_DS is not set
157# CONFIG_MPC85xx_DS is not set 165# CONFIG_MPC85xx_DS is not set
158# CONFIG_KSI8560 is not set 166# CONFIG_KSI8560 is not set
159# CONFIG_STX_GP3 is not set 167# CONFIG_STX_GP3 is not set
160# CONFIG_TQM8540 is not set 168# CONFIG_TQM8540 is not set
161CONFIG_TQM8541=y 169CONFIG_TQM8541=y
170# CONFIG_TQM8548 is not set
162# CONFIG_TQM8555 is not set 171# CONFIG_TQM8555 is not set
163# CONFIG_TQM8560 is not set 172# CONFIG_TQM8560 is not set
164# CONFIG_SBC8548 is not set 173# CONFIG_SBC8548 is not set
@@ -176,7 +185,6 @@ CONFIG_MPIC=y
176# CONFIG_GENERIC_IOMAP is not set 185# CONFIG_GENERIC_IOMAP is not set
177# CONFIG_CPU_FREQ is not set 186# CONFIG_CPU_FREQ is not set
178CONFIG_CPM2=y 187CONFIG_CPM2=y
179CONFIG_PPC_CPM_NEW_BINDING=y
180# CONFIG_FSL_ULI1575 is not set 188# CONFIG_FSL_ULI1575 is not set
181CONFIG_CPM=y 189CONFIG_CPM=y
182 190
@@ -216,6 +224,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
216# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set 224# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
217CONFIG_PAGEFLAGS_EXTENDED=y 225CONFIG_PAGEFLAGS_EXTENDED=y
218CONFIG_SPLIT_PTLOCK_CPUS=4 226CONFIG_SPLIT_PTLOCK_CPUS=4
227CONFIG_MIGRATION=y
219# CONFIG_RESOURCES_64BIT is not set 228# CONFIG_RESOURCES_64BIT is not set
220CONFIG_ZONE_DMA_FLAG=1 229CONFIG_ZONE_DMA_FLAG=1
221CONFIG_BOUNCE=y 230CONFIG_BOUNCE=y
@@ -223,6 +232,7 @@ CONFIG_VIRT_TO_BUS=y
223CONFIG_FORCE_MAX_ZONEORDER=11 232CONFIG_FORCE_MAX_ZONEORDER=11
224# CONFIG_PROC_DEVICETREE is not set 233# CONFIG_PROC_DEVICETREE is not set
225# CONFIG_CMDLINE_BOOL is not set 234# CONFIG_CMDLINE_BOOL is not set
235CONFIG_EXTRA_TARGETS=""
226# CONFIG_PM is not set 236# CONFIG_PM is not set
227CONFIG_SECCOMP=y 237CONFIG_SECCOMP=y
228CONFIG_ISA_DMA_API=y 238CONFIG_ISA_DMA_API=y
@@ -234,6 +244,7 @@ CONFIG_ZONE_DMA=y
234CONFIG_PPC_INDIRECT_PCI=y 244CONFIG_PPC_INDIRECT_PCI=y
235CONFIG_FSL_SOC=y 245CONFIG_FSL_SOC=y
236CONFIG_FSL_PCI=y 246CONFIG_FSL_PCI=y
247CONFIG_PPC_PCI_CHOICE=y
237CONFIG_PCI=y 248CONFIG_PCI=y
238CONFIG_PCI_DOMAINS=y 249CONFIG_PCI_DOMAINS=y
239CONFIG_PCI_SYSCALL=y 250CONFIG_PCI_SYSCALL=y
@@ -257,10 +268,6 @@ CONFIG_KERNEL_START=0xc0000000
257CONFIG_PHYSICAL_START=0x00000000 268CONFIG_PHYSICAL_START=0x00000000
258CONFIG_PHYSICAL_ALIGN=0x10000000 269CONFIG_PHYSICAL_ALIGN=0x10000000
259CONFIG_TASK_SIZE=0xc0000000 270CONFIG_TASK_SIZE=0xc0000000
260
261#
262# Networking
263#
264CONFIG_NET=y 271CONFIG_NET=y
265 272
266# 273#
@@ -432,6 +439,7 @@ CONFIG_MTD_CFI_UTIL=y
432# 439#
433# CONFIG_MTD_UBI is not set 440# CONFIG_MTD_UBI is not set
434CONFIG_OF_DEVICE=y 441CONFIG_OF_DEVICE=y
442CONFIG_OF_GPIO=y
435CONFIG_OF_I2C=y 443CONFIG_OF_I2C=y
436# CONFIG_PARPORT is not set 444# CONFIG_PARPORT is not set
437CONFIG_BLK_DEV=y 445CONFIG_BLK_DEV=y
@@ -451,20 +459,22 @@ CONFIG_BLK_DEV_RAM_SIZE=32768
451# CONFIG_BLK_DEV_XIP is not set 459# CONFIG_BLK_DEV_XIP is not set
452# CONFIG_CDROM_PKTCDVD is not set 460# CONFIG_CDROM_PKTCDVD is not set
453# CONFIG_ATA_OVER_ETH is not set 461# CONFIG_ATA_OVER_ETH is not set
462# CONFIG_BLK_DEV_HD is not set
454CONFIG_MISC_DEVICES=y 463CONFIG_MISC_DEVICES=y
455# CONFIG_PHANTOM is not set 464# CONFIG_PHANTOM is not set
456# CONFIG_EEPROM_93CX6 is not set 465# CONFIG_EEPROM_93CX6 is not set
457# CONFIG_SGI_IOC4 is not set 466# CONFIG_SGI_IOC4 is not set
458# CONFIG_TIFM_CORE is not set 467# CONFIG_TIFM_CORE is not set
459# CONFIG_ENCLOSURE_SERVICES is not set 468# CONFIG_ENCLOSURE_SERVICES is not set
469# CONFIG_HP_ILO is not set
460CONFIG_HAVE_IDE=y 470CONFIG_HAVE_IDE=y
461CONFIG_IDE=y 471CONFIG_IDE=y
462CONFIG_IDE_MAX_HWIFS=4
463CONFIG_BLK_DEV_IDE=y 472CONFIG_BLK_DEV_IDE=y
464 473
465# 474#
466# Please see Documentation/ide/ide.txt for help/info on IDE drives 475# Please see Documentation/ide/ide.txt for help/info on IDE drives
467# 476#
477CONFIG_IDE_TIMINGS=y
468# CONFIG_BLK_DEV_IDE_SATA is not set 478# CONFIG_BLK_DEV_IDE_SATA is not set
469CONFIG_BLK_DEV_IDEDISK=y 479CONFIG_BLK_DEV_IDEDISK=y
470# CONFIG_IDEDISK_MULTI_MODE is not set 480# CONFIG_IDEDISK_MULTI_MODE is not set
@@ -477,7 +487,6 @@ CONFIG_IDE_PROC_FS=y
477# 487#
478# IDE chipset support/bugfixes 488# IDE chipset support/bugfixes
479# 489#
480CONFIG_IDE_GENERIC=y
481# CONFIG_BLK_DEV_PLATFORM is not set 490# CONFIG_BLK_DEV_PLATFORM is not set
482CONFIG_BLK_DEV_IDEDMA_SFF=y 491CONFIG_BLK_DEV_IDEDMA_SFF=y
483 492
@@ -495,10 +504,8 @@ CONFIG_BLK_DEV_IDEDMA_PCI=y
495# CONFIG_BLK_DEV_AMD74XX is not set 504# CONFIG_BLK_DEV_AMD74XX is not set
496# CONFIG_BLK_DEV_CMD64X is not set 505# CONFIG_BLK_DEV_CMD64X is not set
497# CONFIG_BLK_DEV_TRIFLEX is not set 506# CONFIG_BLK_DEV_TRIFLEX is not set
498# CONFIG_BLK_DEV_CY82C693 is not set
499# CONFIG_BLK_DEV_CS5520 is not set 507# CONFIG_BLK_DEV_CS5520 is not set
500# CONFIG_BLK_DEV_CS5530 is not set 508# CONFIG_BLK_DEV_CS5530 is not set
501# CONFIG_BLK_DEV_HPT34X is not set
502# CONFIG_BLK_DEV_HPT366 is not set 509# CONFIG_BLK_DEV_HPT366 is not set
503# CONFIG_BLK_DEV_JMICRON is not set 510# CONFIG_BLK_DEV_JMICRON is not set
504# CONFIG_BLK_DEV_SC1200 is not set 511# CONFIG_BLK_DEV_SC1200 is not set
@@ -516,8 +523,6 @@ CONFIG_BLK_DEV_IDEDMA_PCI=y
516CONFIG_BLK_DEV_VIA82CXXX=y 523CONFIG_BLK_DEV_VIA82CXXX=y
517# CONFIG_BLK_DEV_TC86C001 is not set 524# CONFIG_BLK_DEV_TC86C001 is not set
518CONFIG_BLK_DEV_IDEDMA=y 525CONFIG_BLK_DEV_IDEDMA=y
519# CONFIG_BLK_DEV_HD_ONLY is not set
520# CONFIG_BLK_DEV_HD is not set
521 526
522# 527#
523# SCSI device support 528# SCSI device support
@@ -533,12 +538,15 @@ CONFIG_BLK_DEV_IDEDMA=y
533# 538#
534# IEEE 1394 (FireWire) support 539# IEEE 1394 (FireWire) support
535# 540#
541
542#
543# Enable only one of the two stacks, unless you know what you are doing
544#
536# CONFIG_FIREWIRE is not set 545# CONFIG_FIREWIRE is not set
537# CONFIG_IEEE1394 is not set 546# CONFIG_IEEE1394 is not set
538# CONFIG_I2O is not set 547# CONFIG_I2O is not set
539# CONFIG_MACINTOSH_DRIVERS is not set 548# CONFIG_MACINTOSH_DRIVERS is not set
540CONFIG_NETDEVICES=y 549CONFIG_NETDEVICES=y
541# CONFIG_NETDEVICES_MULTIQUEUE is not set
542# CONFIG_DUMMY is not set 550# CONFIG_DUMMY is not set
543# CONFIG_BONDING is not set 551# CONFIG_BONDING is not set
544# CONFIG_MACVLAN is not set 552# CONFIG_MACVLAN is not set
@@ -601,7 +609,6 @@ CONFIG_NETDEV_1000=y
601# CONFIG_DL2K is not set 609# CONFIG_DL2K is not set
602# CONFIG_E1000 is not set 610# CONFIG_E1000 is not set
603# CONFIG_E1000E is not set 611# CONFIG_E1000E is not set
604# CONFIG_E1000E_ENABLED is not set
605# CONFIG_IP1000 is not set 612# CONFIG_IP1000 is not set
606# CONFIG_IGB is not set 613# CONFIG_IGB is not set
607# CONFIG_NS83820 is not set 614# CONFIG_NS83820 is not set
@@ -615,9 +622,9 @@ CONFIG_NETDEV_1000=y
615# CONFIG_TIGON3 is not set 622# CONFIG_TIGON3 is not set
616# CONFIG_BNX2 is not set 623# CONFIG_BNX2 is not set
617CONFIG_GIANFAR=y 624CONFIG_GIANFAR=y
618CONFIG_GFAR_NAPI=y
619# CONFIG_QLA3XXX is not set 625# CONFIG_QLA3XXX is not set
620# CONFIG_ATL1 is not set 626# CONFIG_ATL1 is not set
627# CONFIG_ATL1E is not set
621CONFIG_NETDEV_10000=y 628CONFIG_NETDEV_10000=y
622# CONFIG_CHELSIO_T1 is not set 629# CONFIG_CHELSIO_T1 is not set
623# CONFIG_CHELSIO_T3 is not set 630# CONFIG_CHELSIO_T3 is not set
@@ -732,42 +739,66 @@ CONFIG_DEVPORT=y
732CONFIG_I2C=y 739CONFIG_I2C=y
733CONFIG_I2C_BOARDINFO=y 740CONFIG_I2C_BOARDINFO=y
734CONFIG_I2C_CHARDEV=y 741CONFIG_I2C_CHARDEV=y
742CONFIG_I2C_HELPER_AUTO=y
735 743
736# 744#
737# I2C Hardware Bus support 745# I2C Hardware Bus support
738# 746#
747
748#
749# PC SMBus host controller drivers
750#
739# CONFIG_I2C_ALI1535 is not set 751# CONFIG_I2C_ALI1535 is not set
740# CONFIG_I2C_ALI1563 is not set 752# CONFIG_I2C_ALI1563 is not set
741# CONFIG_I2C_ALI15X3 is not set 753# CONFIG_I2C_ALI15X3 is not set
742# CONFIG_I2C_AMD756 is not set 754# CONFIG_I2C_AMD756 is not set
743# CONFIG_I2C_AMD8111 is not set 755# CONFIG_I2C_AMD8111 is not set
744# CONFIG_I2C_I801 is not set 756# CONFIG_I2C_I801 is not set
745# CONFIG_I2C_I810 is not set 757# CONFIG_I2C_ISCH is not set
746# CONFIG_I2C_PIIX4 is not set 758# CONFIG_I2C_PIIX4 is not set
747CONFIG_I2C_MPC=y
748# CONFIG_I2C_NFORCE2 is not set 759# CONFIG_I2C_NFORCE2 is not set
749# CONFIG_I2C_OCORES is not set
750# CONFIG_I2C_PARPORT_LIGHT is not set
751# CONFIG_I2C_PROSAVAGE is not set
752# CONFIG_I2C_SAVAGE4 is not set
753# CONFIG_I2C_SIMTEC is not set
754# CONFIG_I2C_SIS5595 is not set 760# CONFIG_I2C_SIS5595 is not set
755# CONFIG_I2C_SIS630 is not set 761# CONFIG_I2C_SIS630 is not set
756# CONFIG_I2C_SIS96X is not set 762# CONFIG_I2C_SIS96X is not set
757# CONFIG_I2C_TAOS_EVM is not set
758# CONFIG_I2C_VIA is not set 763# CONFIG_I2C_VIA is not set
759# CONFIG_I2C_VIAPRO is not set 764# CONFIG_I2C_VIAPRO is not set
765
766#
767# I2C system bus drivers (mostly embedded / system-on-chip)
768#
769# CONFIG_I2C_CPM is not set
770# CONFIG_I2C_GPIO is not set
771CONFIG_I2C_MPC=y
772# CONFIG_I2C_OCORES is not set
773# CONFIG_I2C_SIMTEC is not set
774
775#
776# External I2C/SMBus adapter drivers
777#
778# CONFIG_I2C_PARPORT_LIGHT is not set
779# CONFIG_I2C_TAOS_EVM is not set
780
781#
782# Graphics adapter I2C/DDC channel drivers
783#
760# CONFIG_I2C_VOODOO3 is not set 784# CONFIG_I2C_VOODOO3 is not set
785
786#
787# Other I2C/SMBus bus drivers
788#
761# CONFIG_I2C_PCA_PLATFORM is not set 789# CONFIG_I2C_PCA_PLATFORM is not set
762 790
763# 791#
764# Miscellaneous I2C Chip support 792# Miscellaneous I2C Chip support
765# 793#
766# CONFIG_DS1682 is not set 794# CONFIG_DS1682 is not set
795# CONFIG_AT24 is not set
767# CONFIG_SENSORS_EEPROM is not set 796# CONFIG_SENSORS_EEPROM is not set
768# CONFIG_SENSORS_PCF8574 is not set 797# CONFIG_SENSORS_PCF8574 is not set
769# CONFIG_PCF8575 is not set 798# CONFIG_PCF8575 is not set
799# CONFIG_SENSORS_PCA9539 is not set
770# CONFIG_SENSORS_PCF8591 is not set 800# CONFIG_SENSORS_PCF8591 is not set
801# CONFIG_TPS65010 is not set
771# CONFIG_SENSORS_MAX6875 is not set 802# CONFIG_SENSORS_MAX6875 is not set
772# CONFIG_SENSORS_TSL2550 is not set 803# CONFIG_SENSORS_TSL2550 is not set
773# CONFIG_I2C_DEBUG_CORE is not set 804# CONFIG_I2C_DEBUG_CORE is not set
@@ -775,10 +806,31 @@ CONFIG_I2C_MPC=y
775# CONFIG_I2C_DEBUG_BUS is not set 806# CONFIG_I2C_DEBUG_BUS is not set
776# CONFIG_I2C_DEBUG_CHIP is not set 807# CONFIG_I2C_DEBUG_CHIP is not set
777# CONFIG_SPI is not set 808# CONFIG_SPI is not set
809CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
810CONFIG_ARCH_REQUIRE_GPIOLIB=y
811CONFIG_GPIOLIB=y
812# CONFIG_GPIO_SYSFS is not set
813
814#
815# I2C GPIO expanders:
816#
817# CONFIG_GPIO_MAX732X is not set
818# CONFIG_GPIO_PCA953X is not set
819# CONFIG_GPIO_PCF857X is not set
820
821#
822# PCI GPIO expanders:
823#
824# CONFIG_GPIO_BT8XX is not set
825
826#
827# SPI GPIO expanders:
828#
778# CONFIG_W1 is not set 829# CONFIG_W1 is not set
779# CONFIG_POWER_SUPPLY is not set 830# CONFIG_POWER_SUPPLY is not set
780CONFIG_HWMON=y 831CONFIG_HWMON=y
781# CONFIG_HWMON_VID is not set 832# CONFIG_HWMON_VID is not set
833# CONFIG_SENSORS_AD7414 is not set
782# CONFIG_SENSORS_AD7418 is not set 834# CONFIG_SENSORS_AD7418 is not set
783# CONFIG_SENSORS_ADM1021 is not set 835# CONFIG_SENSORS_ADM1021 is not set
784# CONFIG_SENSORS_ADM1025 is not set 836# CONFIG_SENSORS_ADM1025 is not set
@@ -832,6 +884,7 @@ CONFIG_SENSORS_LM75=y
832# CONFIG_SENSORS_W83627EHF is not set 884# CONFIG_SENSORS_W83627EHF is not set
833CONFIG_HWMON_DEBUG_CHIP=y 885CONFIG_HWMON_DEBUG_CHIP=y
834# CONFIG_THERMAL is not set 886# CONFIG_THERMAL is not set
887# CONFIG_THERMAL_HWMON is not set
835# CONFIG_WATCHDOG is not set 888# CONFIG_WATCHDOG is not set
836 889
837# 890#
@@ -843,8 +896,10 @@ CONFIG_SSB_POSSIBLE=y
843# 896#
844# Multifunction device drivers 897# Multifunction device drivers
845# 898#
899# CONFIG_MFD_CORE is not set
846# CONFIG_MFD_SM501 is not set 900# CONFIG_MFD_SM501 is not set
847# CONFIG_HTC_PASIC3 is not set 901# CONFIG_HTC_PASIC3 is not set
902# CONFIG_MFD_TMIO is not set
848 903
849# 904#
850# Multimedia devices 905# Multimedia devices
@@ -876,10 +931,6 @@ CONFIG_DAB=y
876# Display device support 931# Display device support
877# 932#
878# CONFIG_DISPLAY_SUPPORT is not set 933# CONFIG_DISPLAY_SUPPORT is not set
879
880#
881# Sound
882#
883# CONFIG_SOUND is not set 934# CONFIG_SOUND is not set
884CONFIG_HID_SUPPORT=y 935CONFIG_HID_SUPPORT=y
885CONFIG_HID=y 936CONFIG_HID=y
@@ -894,6 +945,10 @@ CONFIG_USB_ARCH_HAS_EHCI=y
894# CONFIG_USB_OTG_BLACKLIST_HUB is not set 945# CONFIG_USB_OTG_BLACKLIST_HUB is not set
895 946
896# 947#
948# Enable Host or Gadget support to see Inventra options
949#
950
951#
897# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 952# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
898# 953#
899# CONFIG_USB_GADGET is not set 954# CONFIG_USB_GADGET is not set
@@ -982,6 +1037,7 @@ CONFIG_JFFS2_RTIME=y
982CONFIG_CRAMFS=y 1037CONFIG_CRAMFS=y
983# CONFIG_VXFS_FS is not set 1038# CONFIG_VXFS_FS is not set
984# CONFIG_MINIX_FS is not set 1039# CONFIG_MINIX_FS is not set
1040# CONFIG_OMFS_FS is not set
985# CONFIG_HPFS_FS is not set 1041# CONFIG_HPFS_FS is not set
986# CONFIG_QNX4FS_FS is not set 1042# CONFIG_QNX4FS_FS is not set
987# CONFIG_ROMFS_FS is not set 1043# CONFIG_ROMFS_FS is not set
@@ -991,12 +1047,11 @@ CONFIG_NETWORK_FILESYSTEMS=y
991CONFIG_NFS_FS=y 1047CONFIG_NFS_FS=y
992# CONFIG_NFS_V3 is not set 1048# CONFIG_NFS_V3 is not set
993# CONFIG_NFS_V4 is not set 1049# CONFIG_NFS_V4 is not set
994# CONFIG_NFSD is not set
995CONFIG_ROOT_NFS=y 1050CONFIG_ROOT_NFS=y
1051# CONFIG_NFSD is not set
996CONFIG_LOCKD=y 1052CONFIG_LOCKD=y
997CONFIG_NFS_COMMON=y 1053CONFIG_NFS_COMMON=y
998CONFIG_SUNRPC=y 1054CONFIG_SUNRPC=y
999# CONFIG_SUNRPC_BIND34 is not set
1000# CONFIG_RPCSEC_GSS_KRB5 is not set 1055# CONFIG_RPCSEC_GSS_KRB5 is not set
1001# CONFIG_RPCSEC_GSS_SPKM3 is not set 1056# CONFIG_RPCSEC_GSS_SPKM3 is not set
1002# CONFIG_SMB_FS is not set 1057# CONFIG_SMB_FS is not set
@@ -1032,6 +1087,7 @@ CONFIG_BITREVERSE=y
1032# CONFIG_GENERIC_FIND_FIRST_BIT is not set 1087# CONFIG_GENERIC_FIND_FIRST_BIT is not set
1033# CONFIG_CRC_CCITT is not set 1088# CONFIG_CRC_CCITT is not set
1034# CONFIG_CRC16 is not set 1089# CONFIG_CRC16 is not set
1090# CONFIG_CRC_T10DIF is not set
1035# CONFIG_CRC_ITU_T is not set 1091# CONFIG_CRC_ITU_T is not set
1036CONFIG_CRC32=y 1092CONFIG_CRC32=y
1037# CONFIG_CRC7 is not set 1093# CONFIG_CRC7 is not set
@@ -1059,8 +1115,16 @@ CONFIG_FRAME_WARN=1024
1059# CONFIG_SLUB_DEBUG_ON is not set 1115# CONFIG_SLUB_DEBUG_ON is not set
1060# CONFIG_SLUB_STATS is not set 1116# CONFIG_SLUB_STATS is not set
1061# CONFIG_DEBUG_BUGVERBOSE is not set 1117# CONFIG_DEBUG_BUGVERBOSE is not set
1118# CONFIG_DEBUG_MEMORY_INIT is not set
1119# CONFIG_LATENCYTOP is not set
1120CONFIG_SYSCTL_SYSCALL_CHECK=y
1121CONFIG_HAVE_FTRACE=y
1122CONFIG_HAVE_DYNAMIC_FTRACE=y
1123# CONFIG_FTRACE is not set
1124# CONFIG_SCHED_TRACER is not set
1125# CONFIG_CONTEXT_SWITCH_TRACER is not set
1062# CONFIG_SAMPLES is not set 1126# CONFIG_SAMPLES is not set
1063# CONFIG_KGDB_CONSOLE is not set 1127CONFIG_HAVE_ARCH_KGDB=y
1064# CONFIG_IRQSTACKS is not set 1128# CONFIG_IRQSTACKS is not set
1065# CONFIG_PPC_EARLY_DEBUG is not set 1129# CONFIG_PPC_EARLY_DEBUG is not set
1066 1130
@@ -1112,6 +1176,10 @@ CONFIG_CRYPTO=y
1112# CONFIG_CRYPTO_MD4 is not set 1176# CONFIG_CRYPTO_MD4 is not set
1113# CONFIG_CRYPTO_MD5 is not set 1177# CONFIG_CRYPTO_MD5 is not set
1114# CONFIG_CRYPTO_MICHAEL_MIC is not set 1178# CONFIG_CRYPTO_MICHAEL_MIC is not set
1179# CONFIG_CRYPTO_RMD128 is not set
1180# CONFIG_CRYPTO_RMD160 is not set
1181# CONFIG_CRYPTO_RMD256 is not set
1182# CONFIG_CRYPTO_RMD320 is not set
1115# CONFIG_CRYPTO_SHA1 is not set 1183# CONFIG_CRYPTO_SHA1 is not set
1116# CONFIG_CRYPTO_SHA256 is not set 1184# CONFIG_CRYPTO_SHA256 is not set
1117# CONFIG_CRYPTO_SHA512 is not set 1185# CONFIG_CRYPTO_SHA512 is not set
@@ -1144,6 +1212,7 @@ CONFIG_CRYPTO=y
1144# CONFIG_CRYPTO_LZO is not set 1212# CONFIG_CRYPTO_LZO is not set
1145CONFIG_CRYPTO_HW=y 1213CONFIG_CRYPTO_HW=y
1146# CONFIG_CRYPTO_DEV_HIFN_795X is not set 1214# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1147# CONFIG_PPC_CLOCK is not set 1215# CONFIG_CRYPTO_DEV_TALITOS is not set
1216CONFIG_PPC_CLOCK=y
1148CONFIG_PPC_LIB_RHEAP=y 1217CONFIG_PPC_LIB_RHEAP=y
1149# CONFIG_VIRTUALIZATION is not set 1218# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/configs/85xx/tqm8548_defconfig b/arch/powerpc/configs/85xx/tqm8548_defconfig
index b3b770be3cc9..ca1234d26855 100644
--- a/arch/powerpc/configs/85xx/tqm8548_defconfig
+++ b/arch/powerpc/configs/85xx/tqm8548_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc5 3# Linux kernel version: 2.6.27-rc4
4# Thu Jun 26 14:40:02 2008 4# Thu Aug 21 00:52:40 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -34,6 +34,7 @@ CONFIG_GENERIC_HARDIRQS=y
34# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set 34# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
35CONFIG_IRQ_PER_CPU=y 35CONFIG_IRQ_PER_CPU=y
36CONFIG_STACKTRACE_SUPPORT=y 36CONFIG_STACKTRACE_SUPPORT=y
37CONFIG_HAVE_LATENCYTOP_SUPPORT=y
37CONFIG_LOCKDEP_SUPPORT=y 38CONFIG_LOCKDEP_SUPPORT=y
38CONFIG_RWSEM_XCHGADD_ALGORITHM=y 39CONFIG_RWSEM_XCHGADD_ALGORITHM=y
39CONFIG_ARCH_HAS_ILOG2_U32=y 40CONFIG_ARCH_HAS_ILOG2_U32=y
@@ -90,7 +91,6 @@ CONFIG_INITRAMFS_SOURCE=""
90CONFIG_SYSCTL=y 91CONFIG_SYSCTL=y
91CONFIG_EMBEDDED=y 92CONFIG_EMBEDDED=y
92CONFIG_SYSCTL_SYSCALL=y 93CONFIG_SYSCTL_SYSCALL=y
93CONFIG_SYSCTL_SYSCALL_CHECK=y
94CONFIG_KALLSYMS=y 94CONFIG_KALLSYMS=y
95# CONFIG_KALLSYMS_ALL is not set 95# CONFIG_KALLSYMS_ALL is not set
96# CONFIG_KALLSYMS_EXTRA_PASS is not set 96# CONFIG_KALLSYMS_EXTRA_PASS is not set
@@ -116,10 +116,16 @@ CONFIG_SLUB=y
116# CONFIG_MARKERS is not set 116# CONFIG_MARKERS is not set
117CONFIG_HAVE_OPROFILE=y 117CONFIG_HAVE_OPROFILE=y
118# CONFIG_KPROBES is not set 118# CONFIG_KPROBES is not set
119CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
120CONFIG_HAVE_IOREMAP_PROT=y
119CONFIG_HAVE_KPROBES=y 121CONFIG_HAVE_KPROBES=y
120CONFIG_HAVE_KRETPROBES=y 122CONFIG_HAVE_KRETPROBES=y
123CONFIG_HAVE_ARCH_TRACEHOOK=y
121# CONFIG_HAVE_DMA_ATTRS is not set 124# CONFIG_HAVE_DMA_ATTRS is not set
125# CONFIG_USE_GENERIC_SMP_HELPERS is not set
126# CONFIG_HAVE_CLK is not set
122CONFIG_PROC_PAGE_MONITOR=y 127CONFIG_PROC_PAGE_MONITOR=y
128# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
123CONFIG_SLABINFO=y 129CONFIG_SLABINFO=y
124CONFIG_RT_MUTEXES=y 130CONFIG_RT_MUTEXES=y
125# CONFIG_TINY_SHMEM is not set 131# CONFIG_TINY_SHMEM is not set
@@ -130,12 +136,13 @@ CONFIG_MODULE_UNLOAD=y
130# CONFIG_MODULE_FORCE_UNLOAD is not set 136# CONFIG_MODULE_FORCE_UNLOAD is not set
131# CONFIG_MODVERSIONS is not set 137# CONFIG_MODVERSIONS is not set
132# CONFIG_MODULE_SRCVERSION_ALL is not set 138# CONFIG_MODULE_SRCVERSION_ALL is not set
133# CONFIG_KMOD is not set 139CONFIG_KMOD=y
134CONFIG_BLOCK=y 140CONFIG_BLOCK=y
135# CONFIG_LBD is not set 141# CONFIG_LBD is not set
136# CONFIG_BLK_DEV_IO_TRACE is not set 142# CONFIG_BLK_DEV_IO_TRACE is not set
137# CONFIG_LSF is not set 143# CONFIG_LSF is not set
138# CONFIG_BLK_DEV_BSG is not set 144# CONFIG_BLK_DEV_BSG is not set
145# CONFIG_BLK_DEV_INTEGRITY is not set
139 146
140# 147#
141# IO Schedulers 148# IO Schedulers
@@ -154,8 +161,6 @@ CONFIG_CLASSIC_RCU=y
154# 161#
155# Platform support 162# Platform support
156# 163#
157# CONFIG_PPC_MPC512x is not set
158# CONFIG_PPC_MPC5121 is not set
159# CONFIG_PPC_CELL is not set 164# CONFIG_PPC_CELL is not set
160# CONFIG_PPC_CELL_NATIVE is not set 165# CONFIG_PPC_CELL_NATIVE is not set
161# CONFIG_PQ2ADS is not set 166# CONFIG_PQ2ADS is not set
@@ -164,6 +169,7 @@ CONFIG_MPC85xx=y
164# CONFIG_MPC8560_ADS is not set 169# CONFIG_MPC8560_ADS is not set
165# CONFIG_MPC85xx_CDS is not set 170# CONFIG_MPC85xx_CDS is not set
166# CONFIG_MPC85xx_MDS is not set 171# CONFIG_MPC85xx_MDS is not set
172# CONFIG_MPC8536_DS is not set
167# CONFIG_MPC85xx_DS is not set 173# CONFIG_MPC85xx_DS is not set
168# CONFIG_KSI8560 is not set 174# CONFIG_KSI8560 is not set
169# CONFIG_STX_GP3 is not set 175# CONFIG_STX_GP3 is not set
@@ -187,7 +193,6 @@ CONFIG_MPIC=y
187# CONFIG_GENERIC_IOMAP is not set 193# CONFIG_GENERIC_IOMAP is not set
188# CONFIG_CPU_FREQ is not set 194# CONFIG_CPU_FREQ is not set
189# CONFIG_CPM2 is not set 195# CONFIG_CPM2 is not set
190CONFIG_PPC_CPM_NEW_BINDING=y
191# CONFIG_FSL_ULI1575 is not set 196# CONFIG_FSL_ULI1575 is not set
192 197
193# 198#
@@ -203,7 +208,7 @@ CONFIG_HZ_250=y
203# CONFIG_HZ_300 is not set 208# CONFIG_HZ_300 is not set
204# CONFIG_HZ_1000 is not set 209# CONFIG_HZ_1000 is not set
205CONFIG_HZ=250 210CONFIG_HZ=250
206# CONFIG_SCHED_HRTICK is not set 211CONFIG_SCHED_HRTICK=y
207CONFIG_PREEMPT_NONE=y 212CONFIG_PREEMPT_NONE=y
208# CONFIG_PREEMPT_VOLUNTARY is not set 213# CONFIG_PREEMPT_VOLUNTARY is not set
209# CONFIG_PREEMPT is not set 214# CONFIG_PREEMPT is not set
@@ -226,6 +231,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
226# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set 231# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
227CONFIG_PAGEFLAGS_EXTENDED=y 232CONFIG_PAGEFLAGS_EXTENDED=y
228CONFIG_SPLIT_PTLOCK_CPUS=4 233CONFIG_SPLIT_PTLOCK_CPUS=4
234CONFIG_MIGRATION=y
229# CONFIG_RESOURCES_64BIT is not set 235# CONFIG_RESOURCES_64BIT is not set
230CONFIG_ZONE_DMA_FLAG=1 236CONFIG_ZONE_DMA_FLAG=1
231CONFIG_BOUNCE=y 237CONFIG_BOUNCE=y
@@ -233,6 +239,7 @@ CONFIG_VIRT_TO_BUS=y
233CONFIG_FORCE_MAX_ZONEORDER=11 239CONFIG_FORCE_MAX_ZONEORDER=11
234CONFIG_PROC_DEVICETREE=y 240CONFIG_PROC_DEVICETREE=y
235# CONFIG_CMDLINE_BOOL is not set 241# CONFIG_CMDLINE_BOOL is not set
242CONFIG_EXTRA_TARGETS=""
236# CONFIG_PM is not set 243# CONFIG_PM is not set
237# CONFIG_SECCOMP is not set 244# CONFIG_SECCOMP is not set
238CONFIG_ISA_DMA_API=y 245CONFIG_ISA_DMA_API=y
@@ -244,7 +251,7 @@ CONFIG_ZONE_DMA=y
244CONFIG_PPC_INDIRECT_PCI=y 251CONFIG_PPC_INDIRECT_PCI=y
245CONFIG_FSL_SOC=y 252CONFIG_FSL_SOC=y
246CONFIG_FSL_PCI=y 253CONFIG_FSL_PCI=y
247CONFIG_FSL_LBC=y 254CONFIG_PPC_PCI_CHOICE=y
248CONFIG_PCI=y 255CONFIG_PCI=y
249CONFIG_PCI_DOMAINS=y 256CONFIG_PCI_DOMAINS=y
250CONFIG_PCI_SYSCALL=y 257CONFIG_PCI_SYSCALL=y
@@ -273,10 +280,6 @@ CONFIG_KERNEL_START=0xc0000000
273CONFIG_PHYSICAL_START=0x00000000 280CONFIG_PHYSICAL_START=0x00000000
274CONFIG_PHYSICAL_ALIGN=0x10000000 281CONFIG_PHYSICAL_ALIGN=0x10000000
275CONFIG_TASK_SIZE=0xc0000000 282CONFIG_TASK_SIZE=0xc0000000
276
277#
278# Networking
279#
280CONFIG_NET=y 283CONFIG_NET=y
281 284
282# 285#
@@ -455,7 +458,6 @@ CONFIG_MTD_NAND_IDS=y
455# CONFIG_MTD_NAND_NANDSIM is not set 458# CONFIG_MTD_NAND_NANDSIM is not set
456# CONFIG_MTD_NAND_PLATFORM is not set 459# CONFIG_MTD_NAND_PLATFORM is not set
457# CONFIG_MTD_NAND_FSL_ELBC is not set 460# CONFIG_MTD_NAND_FSL_ELBC is not set
458CONFIG_MTD_NAND_FSL_UPM=y
459# CONFIG_MTD_ONENAND is not set 461# CONFIG_MTD_ONENAND is not set
460 462
461# 463#
@@ -490,20 +492,22 @@ CONFIG_BLK_DEV_RAM_SIZE=32768
490# CONFIG_BLK_DEV_XIP is not set 492# CONFIG_BLK_DEV_XIP is not set
491# CONFIG_CDROM_PKTCDVD is not set 493# CONFIG_CDROM_PKTCDVD is not set
492# CONFIG_ATA_OVER_ETH is not set 494# CONFIG_ATA_OVER_ETH is not set
495# CONFIG_BLK_DEV_HD is not set
493CONFIG_MISC_DEVICES=y 496CONFIG_MISC_DEVICES=y
494# CONFIG_PHANTOM is not set 497# CONFIG_PHANTOM is not set
495# CONFIG_EEPROM_93CX6 is not set 498# CONFIG_EEPROM_93CX6 is not set
496# CONFIG_SGI_IOC4 is not set 499# CONFIG_SGI_IOC4 is not set
497# CONFIG_TIFM_CORE is not set 500# CONFIG_TIFM_CORE is not set
498# CONFIG_ENCLOSURE_SERVICES is not set 501# CONFIG_ENCLOSURE_SERVICES is not set
502# CONFIG_HP_ILO is not set
499CONFIG_HAVE_IDE=y 503CONFIG_HAVE_IDE=y
500CONFIG_IDE=y 504CONFIG_IDE=y
501CONFIG_IDE_MAX_HWIFS=4
502CONFIG_BLK_DEV_IDE=y 505CONFIG_BLK_DEV_IDE=y
503 506
504# 507#
505# Please see Documentation/ide/ide.txt for help/info on IDE drives 508# Please see Documentation/ide/ide.txt for help/info on IDE drives
506# 509#
510CONFIG_IDE_TIMINGS=y
507# CONFIG_BLK_DEV_IDE_SATA is not set 511# CONFIG_BLK_DEV_IDE_SATA is not set
508# CONFIG_BLK_DEV_IDEDISK is not set 512# CONFIG_BLK_DEV_IDEDISK is not set
509# CONFIG_IDEDISK_MULTI_MODE is not set 513# CONFIG_IDEDISK_MULTI_MODE is not set
@@ -516,7 +520,6 @@ CONFIG_IDE_PROC_FS=y
516# 520#
517# IDE chipset support/bugfixes 521# IDE chipset support/bugfixes
518# 522#
519CONFIG_IDE_GENERIC=y
520# CONFIG_BLK_DEV_PLATFORM is not set 523# CONFIG_BLK_DEV_PLATFORM is not set
521CONFIG_BLK_DEV_IDEDMA_SFF=y 524CONFIG_BLK_DEV_IDEDMA_SFF=y
522 525
@@ -534,10 +537,8 @@ CONFIG_BLK_DEV_IDEDMA_PCI=y
534# CONFIG_BLK_DEV_AMD74XX is not set 537# CONFIG_BLK_DEV_AMD74XX is not set
535# CONFIG_BLK_DEV_CMD64X is not set 538# CONFIG_BLK_DEV_CMD64X is not set
536# CONFIG_BLK_DEV_TRIFLEX is not set 539# CONFIG_BLK_DEV_TRIFLEX is not set
537# CONFIG_BLK_DEV_CY82C693 is not set
538# CONFIG_BLK_DEV_CS5520 is not set 540# CONFIG_BLK_DEV_CS5520 is not set
539# CONFIG_BLK_DEV_CS5530 is not set 541# CONFIG_BLK_DEV_CS5530 is not set
540# CONFIG_BLK_DEV_HPT34X is not set
541# CONFIG_BLK_DEV_HPT366 is not set 542# CONFIG_BLK_DEV_HPT366 is not set
542# CONFIG_BLK_DEV_JMICRON is not set 543# CONFIG_BLK_DEV_JMICRON is not set
543# CONFIG_BLK_DEV_SC1200 is not set 544# CONFIG_BLK_DEV_SC1200 is not set
@@ -555,8 +556,6 @@ CONFIG_BLK_DEV_IDEDMA_PCI=y
555CONFIG_BLK_DEV_VIA82CXXX=y 556CONFIG_BLK_DEV_VIA82CXXX=y
556# CONFIG_BLK_DEV_TC86C001 is not set 557# CONFIG_BLK_DEV_TC86C001 is not set
557CONFIG_BLK_DEV_IDEDMA=y 558CONFIG_BLK_DEV_IDEDMA=y
558# CONFIG_BLK_DEV_HD_ONLY is not set
559# CONFIG_BLK_DEV_HD is not set
560 559
561# 560#
562# SCSI device support 561# SCSI device support
@@ -572,12 +571,15 @@ CONFIG_BLK_DEV_IDEDMA=y
572# 571#
573# IEEE 1394 (FireWire) support 572# IEEE 1394 (FireWire) support
574# 573#
574
575#
576# Enable only one of the two stacks, unless you know what you are doing
577#
575# CONFIG_FIREWIRE is not set 578# CONFIG_FIREWIRE is not set
576# CONFIG_IEEE1394 is not set 579# CONFIG_IEEE1394 is not set
577# CONFIG_I2O is not set 580# CONFIG_I2O is not set
578# CONFIG_MACINTOSH_DRIVERS is not set 581# CONFIG_MACINTOSH_DRIVERS is not set
579CONFIG_NETDEVICES=y 582CONFIG_NETDEVICES=y
580# CONFIG_NETDEVICES_MULTIQUEUE is not set
581# CONFIG_DUMMY is not set 583# CONFIG_DUMMY is not set
582# CONFIG_BONDING is not set 584# CONFIG_BONDING is not set
583# CONFIG_MACVLAN is not set 585# CONFIG_MACVLAN is not set
@@ -620,10 +622,8 @@ CONFIG_NETDEV_1000=y
620# CONFIG_ACENIC is not set 622# CONFIG_ACENIC is not set
621# CONFIG_DL2K is not set 623# CONFIG_DL2K is not set
622CONFIG_E1000=y 624CONFIG_E1000=y
623CONFIG_E1000_NAPI=y
624# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set 625# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
625# CONFIG_E1000E is not set 626# CONFIG_E1000E is not set
626# CONFIG_E1000E_ENABLED is not set
627# CONFIG_IP1000 is not set 627# CONFIG_IP1000 is not set
628# CONFIG_IGB is not set 628# CONFIG_IGB is not set
629# CONFIG_NS83820 is not set 629# CONFIG_NS83820 is not set
@@ -637,9 +637,9 @@ CONFIG_E1000_NAPI=y
637# CONFIG_TIGON3 is not set 637# CONFIG_TIGON3 is not set
638# CONFIG_BNX2 is not set 638# CONFIG_BNX2 is not set
639CONFIG_GIANFAR=y 639CONFIG_GIANFAR=y
640CONFIG_GFAR_NAPI=y
641# CONFIG_QLA3XXX is not set 640# CONFIG_QLA3XXX is not set
642# CONFIG_ATL1 is not set 641# CONFIG_ATL1 is not set
642# CONFIG_ATL1E is not set
643CONFIG_NETDEV_10000=y 643CONFIG_NETDEV_10000=y
644# CONFIG_CHELSIO_T1 is not set 644# CONFIG_CHELSIO_T1 is not set
645# CONFIG_CHELSIO_T3 is not set 645# CONFIG_CHELSIO_T3 is not set
@@ -744,42 +744,63 @@ CONFIG_DEVPORT=y
744CONFIG_I2C=y 744CONFIG_I2C=y
745CONFIG_I2C_BOARDINFO=y 745CONFIG_I2C_BOARDINFO=y
746CONFIG_I2C_CHARDEV=y 746CONFIG_I2C_CHARDEV=y
747CONFIG_I2C_HELPER_AUTO=y
747 748
748# 749#
749# I2C Hardware Bus support 750# I2C Hardware Bus support
750# 751#
752
753#
754# PC SMBus host controller drivers
755#
751# CONFIG_I2C_ALI1535 is not set 756# CONFIG_I2C_ALI1535 is not set
752# CONFIG_I2C_ALI1563 is not set 757# CONFIG_I2C_ALI1563 is not set
753# CONFIG_I2C_ALI15X3 is not set 758# CONFIG_I2C_ALI15X3 is not set
754# CONFIG_I2C_AMD756 is not set 759# CONFIG_I2C_AMD756 is not set
755# CONFIG_I2C_AMD8111 is not set 760# CONFIG_I2C_AMD8111 is not set
756# CONFIG_I2C_I801 is not set 761# CONFIG_I2C_I801 is not set
757# CONFIG_I2C_I810 is not set 762# CONFIG_I2C_ISCH is not set
758# CONFIG_I2C_PIIX4 is not set 763# CONFIG_I2C_PIIX4 is not set
759CONFIG_I2C_MPC=y
760# CONFIG_I2C_NFORCE2 is not set 764# CONFIG_I2C_NFORCE2 is not set
761# CONFIG_I2C_OCORES is not set
762# CONFIG_I2C_PARPORT_LIGHT is not set
763# CONFIG_I2C_PROSAVAGE is not set
764# CONFIG_I2C_SAVAGE4 is not set
765# CONFIG_I2C_SIMTEC is not set
766# CONFIG_I2C_SIS5595 is not set 765# CONFIG_I2C_SIS5595 is not set
767# CONFIG_I2C_SIS630 is not set 766# CONFIG_I2C_SIS630 is not set
768# CONFIG_I2C_SIS96X is not set 767# CONFIG_I2C_SIS96X is not set
769# CONFIG_I2C_TAOS_EVM is not set
770# CONFIG_I2C_STUB is not set
771# CONFIG_I2C_VIA is not set 768# CONFIG_I2C_VIA is not set
772# CONFIG_I2C_VIAPRO is not set 769# CONFIG_I2C_VIAPRO is not set
770
771#
772# I2C system bus drivers (mostly embedded / system-on-chip)
773#
774CONFIG_I2C_MPC=y
775# CONFIG_I2C_OCORES is not set
776# CONFIG_I2C_SIMTEC is not set
777
778#
779# External I2C/SMBus adapter drivers
780#
781# CONFIG_I2C_PARPORT_LIGHT is not set
782# CONFIG_I2C_TAOS_EVM is not set
783
784#
785# Graphics adapter I2C/DDC channel drivers
786#
773# CONFIG_I2C_VOODOO3 is not set 787# CONFIG_I2C_VOODOO3 is not set
788
789#
790# Other I2C/SMBus bus drivers
791#
774# CONFIG_I2C_PCA_PLATFORM is not set 792# CONFIG_I2C_PCA_PLATFORM is not set
793# CONFIG_I2C_STUB is not set
775 794
776# 795#
777# Miscellaneous I2C Chip support 796# Miscellaneous I2C Chip support
778# 797#
779# CONFIG_DS1682 is not set 798# CONFIG_DS1682 is not set
799# CONFIG_AT24 is not set
780# CONFIG_SENSORS_EEPROM is not set 800# CONFIG_SENSORS_EEPROM is not set
781# CONFIG_SENSORS_PCF8574 is not set 801# CONFIG_SENSORS_PCF8574 is not set
782# CONFIG_PCF8575 is not set 802# CONFIG_PCF8575 is not set
803# CONFIG_SENSORS_PCA9539 is not set
783# CONFIG_SENSORS_PCF8591 is not set 804# CONFIG_SENSORS_PCF8591 is not set
784# CONFIG_SENSORS_MAX6875 is not set 805# CONFIG_SENSORS_MAX6875 is not set
785# CONFIG_SENSORS_TSL2550 is not set 806# CONFIG_SENSORS_TSL2550 is not set
@@ -788,10 +809,13 @@ CONFIG_I2C_MPC=y
788# CONFIG_I2C_DEBUG_BUS is not set 809# CONFIG_I2C_DEBUG_BUS is not set
789# CONFIG_I2C_DEBUG_CHIP is not set 810# CONFIG_I2C_DEBUG_CHIP is not set
790# CONFIG_SPI is not set 811# CONFIG_SPI is not set
812CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
813# CONFIG_GPIOLIB is not set
791# CONFIG_W1 is not set 814# CONFIG_W1 is not set
792# CONFIG_POWER_SUPPLY is not set 815# CONFIG_POWER_SUPPLY is not set
793CONFIG_HWMON=y 816CONFIG_HWMON=y
794# CONFIG_HWMON_VID is not set 817# CONFIG_HWMON_VID is not set
818# CONFIG_SENSORS_AD7414 is not set
795# CONFIG_SENSORS_AD7418 is not set 819# CONFIG_SENSORS_AD7418 is not set
796# CONFIG_SENSORS_ADM1021 is not set 820# CONFIG_SENSORS_ADM1021 is not set
797# CONFIG_SENSORS_ADM1025 is not set 821# CONFIG_SENSORS_ADM1025 is not set
@@ -845,6 +869,7 @@ CONFIG_SENSORS_LM75=y
845# CONFIG_SENSORS_W83627EHF is not set 869# CONFIG_SENSORS_W83627EHF is not set
846# CONFIG_HWMON_DEBUG_CHIP is not set 870# CONFIG_HWMON_DEBUG_CHIP is not set
847# CONFIG_THERMAL is not set 871# CONFIG_THERMAL is not set
872# CONFIG_THERMAL_HWMON is not set
848# CONFIG_WATCHDOG is not set 873# CONFIG_WATCHDOG is not set
849 874
850# 875#
@@ -856,8 +881,10 @@ CONFIG_SSB_POSSIBLE=y
856# 881#
857# Multifunction device drivers 882# Multifunction device drivers
858# 883#
884# CONFIG_MFD_CORE is not set
859# CONFIG_MFD_SM501 is not set 885# CONFIG_MFD_SM501 is not set
860# CONFIG_HTC_PASIC3 is not set 886# CONFIG_HTC_PASIC3 is not set
887# CONFIG_MFD_TMIO is not set
861 888
862# 889#
863# Multimedia devices 890# Multimedia devices
@@ -889,10 +916,6 @@ CONFIG_VIDEO_OUTPUT_CONTROL=y
889# Display device support 916# Display device support
890# 917#
891# CONFIG_DISPLAY_SUPPORT is not set 918# CONFIG_DISPLAY_SUPPORT is not set
892
893#
894# Sound
895#
896# CONFIG_SOUND is not set 919# CONFIG_SOUND is not set
897CONFIG_HID_SUPPORT=y 920CONFIG_HID_SUPPORT=y
898CONFIG_HID=y 921CONFIG_HID=y
@@ -907,6 +930,10 @@ CONFIG_USB_ARCH_HAS_EHCI=y
907# CONFIG_USB_OTG_BLACKLIST_HUB is not set 930# CONFIG_USB_OTG_BLACKLIST_HUB is not set
908 931
909# 932#
933# Enable Host or Gadget support to see Inventra options
934#
935
936#
910# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 937# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
911# 938#
912# CONFIG_USB_GADGET is not set 939# CONFIG_USB_GADGET is not set
@@ -945,6 +972,7 @@ CONFIG_RTC_DRV_DS1307=y
945# CONFIG_RTC_DRV_PCF8583 is not set 972# CONFIG_RTC_DRV_PCF8583 is not set
946# CONFIG_RTC_DRV_M41T80 is not set 973# CONFIG_RTC_DRV_M41T80 is not set
947# CONFIG_RTC_DRV_S35390A is not set 974# CONFIG_RTC_DRV_S35390A is not set
975# CONFIG_RTC_DRV_FM3130 is not set
948 976
949# 977#
950# SPI RTC drivers 978# SPI RTC drivers
@@ -1031,9 +1059,11 @@ CONFIG_TMPFS=y
1031# CONFIG_BFS_FS is not set 1059# CONFIG_BFS_FS is not set
1032# CONFIG_EFS_FS is not set 1060# CONFIG_EFS_FS is not set
1033# CONFIG_JFFS2_FS is not set 1061# CONFIG_JFFS2_FS is not set
1062# CONFIG_UBIFS_FS is not set
1034# CONFIG_CRAMFS is not set 1063# CONFIG_CRAMFS is not set
1035# CONFIG_VXFS_FS is not set 1064# CONFIG_VXFS_FS is not set
1036# CONFIG_MINIX_FS is not set 1065# CONFIG_MINIX_FS is not set
1066# CONFIG_OMFS_FS is not set
1037# CONFIG_HPFS_FS is not set 1067# CONFIG_HPFS_FS is not set
1038# CONFIG_QNX4FS_FS is not set 1068# CONFIG_QNX4FS_FS is not set
1039# CONFIG_ROMFS_FS is not set 1069# CONFIG_ROMFS_FS is not set
@@ -1043,12 +1073,11 @@ CONFIG_NETWORK_FILESYSTEMS=y
1043CONFIG_NFS_FS=y 1073CONFIG_NFS_FS=y
1044# CONFIG_NFS_V3 is not set 1074# CONFIG_NFS_V3 is not set
1045# CONFIG_NFS_V4 is not set 1075# CONFIG_NFS_V4 is not set
1046# CONFIG_NFSD is not set
1047CONFIG_ROOT_NFS=y 1076CONFIG_ROOT_NFS=y
1077# CONFIG_NFSD is not set
1048CONFIG_LOCKD=y 1078CONFIG_LOCKD=y
1049CONFIG_NFS_COMMON=y 1079CONFIG_NFS_COMMON=y
1050CONFIG_SUNRPC=y 1080CONFIG_SUNRPC=y
1051# CONFIG_SUNRPC_BIND34 is not set
1052# CONFIG_RPCSEC_GSS_KRB5 is not set 1081# CONFIG_RPCSEC_GSS_KRB5 is not set
1053# CONFIG_RPCSEC_GSS_SPKM3 is not set 1082# CONFIG_RPCSEC_GSS_SPKM3 is not set
1054# CONFIG_SMB_FS is not set 1083# CONFIG_SMB_FS is not set
@@ -1084,6 +1113,7 @@ CONFIG_BITREVERSE=y
1084# CONFIG_GENERIC_FIND_FIRST_BIT is not set 1113# CONFIG_GENERIC_FIND_FIRST_BIT is not set
1085# CONFIG_CRC_CCITT is not set 1114# CONFIG_CRC_CCITT is not set
1086# CONFIG_CRC16 is not set 1115# CONFIG_CRC16 is not set
1116# CONFIG_CRC_T10DIF is not set
1087# CONFIG_CRC_ITU_T is not set 1117# CONFIG_CRC_ITU_T is not set
1088CONFIG_CRC32=y 1118CONFIG_CRC32=y
1089# CONFIG_CRC7 is not set 1119# CONFIG_CRC7 is not set
@@ -1108,6 +1138,8 @@ CONFIG_FRAME_WARN=1024
1108CONFIG_DEBUG_KERNEL=y 1138CONFIG_DEBUG_KERNEL=y
1109# CONFIG_DEBUG_SHIRQ is not set 1139# CONFIG_DEBUG_SHIRQ is not set
1110CONFIG_DETECT_SOFTLOCKUP=y 1140CONFIG_DETECT_SOFTLOCKUP=y
1141# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
1142CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
1111CONFIG_SCHED_DEBUG=y 1143CONFIG_SCHED_DEBUG=y
1112# CONFIG_SCHEDSTATS is not set 1144# CONFIG_SCHEDSTATS is not set
1113# CONFIG_TIMER_STATS is not set 1145# CONFIG_TIMER_STATS is not set
@@ -1125,17 +1157,29 @@ CONFIG_DEBUG_MUTEXES=y
1125# CONFIG_DEBUG_INFO is not set 1157# CONFIG_DEBUG_INFO is not set
1126# CONFIG_DEBUG_VM is not set 1158# CONFIG_DEBUG_VM is not set
1127# CONFIG_DEBUG_WRITECOUNT is not set 1159# CONFIG_DEBUG_WRITECOUNT is not set
1160# CONFIG_DEBUG_MEMORY_INIT is not set
1128# CONFIG_DEBUG_LIST is not set 1161# CONFIG_DEBUG_LIST is not set
1129# CONFIG_DEBUG_SG is not set 1162# CONFIG_DEBUG_SG is not set
1130# CONFIG_BOOT_PRINTK_DELAY is not set 1163# CONFIG_BOOT_PRINTK_DELAY is not set
1131# CONFIG_RCU_TORTURE_TEST is not set 1164# CONFIG_RCU_TORTURE_TEST is not set
1132# CONFIG_BACKTRACE_SELF_TEST is not set 1165# CONFIG_BACKTRACE_SELF_TEST is not set
1133# CONFIG_FAULT_INJECTION is not set 1166# CONFIG_FAULT_INJECTION is not set
1167# CONFIG_LATENCYTOP is not set
1168CONFIG_SYSCTL_SYSCALL_CHECK=y
1169CONFIG_HAVE_FTRACE=y
1170CONFIG_HAVE_DYNAMIC_FTRACE=y
1171# CONFIG_FTRACE is not set
1172# CONFIG_SCHED_TRACER is not set
1173# CONFIG_CONTEXT_SWITCH_TRACER is not set
1134# CONFIG_SAMPLES is not set 1174# CONFIG_SAMPLES is not set
1175CONFIG_HAVE_ARCH_KGDB=y
1176# CONFIG_KGDB is not set
1135# CONFIG_DEBUG_STACKOVERFLOW is not set 1177# CONFIG_DEBUG_STACKOVERFLOW is not set
1136# CONFIG_DEBUG_STACK_USAGE is not set 1178# CONFIG_DEBUG_STACK_USAGE is not set
1137# CONFIG_DEBUG_PAGEALLOC is not set 1179# CONFIG_DEBUG_PAGEALLOC is not set
1138# CONFIG_DEBUGGER is not set 1180# CONFIG_CODE_PATCHING_SELFTEST is not set
1181# CONFIG_FTR_FIXUP_SELFTEST is not set
1182# CONFIG_XMON is not set
1139# CONFIG_IRQSTACKS is not set 1183# CONFIG_IRQSTACKS is not set
1140# CONFIG_BDI_SWITCH is not set 1184# CONFIG_BDI_SWITCH is not set
1141# CONFIG_PPC_EARLY_DEBUG is not set 1185# CONFIG_PPC_EARLY_DEBUG is not set
@@ -1189,6 +1233,10 @@ CONFIG_CRYPTO=y
1189# CONFIG_CRYPTO_MD4 is not set 1233# CONFIG_CRYPTO_MD4 is not set
1190# CONFIG_CRYPTO_MD5 is not set 1234# CONFIG_CRYPTO_MD5 is not set
1191# CONFIG_CRYPTO_MICHAEL_MIC is not set 1235# CONFIG_CRYPTO_MICHAEL_MIC is not set
1236# CONFIG_CRYPTO_RMD128 is not set
1237# CONFIG_CRYPTO_RMD160 is not set
1238# CONFIG_CRYPTO_RMD256 is not set
1239# CONFIG_CRYPTO_RMD320 is not set
1192# CONFIG_CRYPTO_SHA1 is not set 1240# CONFIG_CRYPTO_SHA1 is not set
1193# CONFIG_CRYPTO_SHA256 is not set 1241# CONFIG_CRYPTO_SHA256 is not set
1194# CONFIG_CRYPTO_SHA512 is not set 1242# CONFIG_CRYPTO_SHA512 is not set
@@ -1221,5 +1269,6 @@ CONFIG_CRYPTO=y
1221# CONFIG_CRYPTO_LZO is not set 1269# CONFIG_CRYPTO_LZO is not set
1222CONFIG_CRYPTO_HW=y 1270CONFIG_CRYPTO_HW=y
1223# CONFIG_CRYPTO_DEV_HIFN_795X is not set 1271# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1272# CONFIG_CRYPTO_DEV_TALITOS is not set
1224# CONFIG_PPC_CLOCK is not set 1273# CONFIG_PPC_CLOCK is not set
1225# CONFIG_VIRTUALIZATION is not set 1274# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/configs/85xx/tqm8555_defconfig b/arch/powerpc/configs/85xx/tqm8555_defconfig
index 03120b5b52fa..dcf9cfe28b55 100644
--- a/arch/powerpc/configs/85xx/tqm8555_defconfig
+++ b/arch/powerpc/configs/85xx/tqm8555_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc5 3# Linux kernel version: 2.6.27-rc4
4# Mon Jun 9 08:52:41 2008 4# Thu Aug 21 00:52:42 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -15,6 +15,7 @@ CONFIG_PPC_85xx=y
15# CONFIG_44x is not set 15# CONFIG_44x is not set
16# CONFIG_E200 is not set 16# CONFIG_E200 is not set
17CONFIG_E500=y 17CONFIG_E500=y
18# CONFIG_PPC_E500MC is not set
18CONFIG_BOOKE=y 19CONFIG_BOOKE=y
19CONFIG_FSL_BOOKE=y 20CONFIG_FSL_BOOKE=y
20CONFIG_FSL_EMB_PERFMON=y 21CONFIG_FSL_EMB_PERFMON=y
@@ -33,12 +34,14 @@ CONFIG_GENERIC_HARDIRQS=y
33# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set 34# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
34CONFIG_IRQ_PER_CPU=y 35CONFIG_IRQ_PER_CPU=y
35CONFIG_STACKTRACE_SUPPORT=y 36CONFIG_STACKTRACE_SUPPORT=y
37CONFIG_HAVE_LATENCYTOP_SUPPORT=y
36CONFIG_LOCKDEP_SUPPORT=y 38CONFIG_LOCKDEP_SUPPORT=y
37CONFIG_RWSEM_XCHGADD_ALGORITHM=y 39CONFIG_RWSEM_XCHGADD_ALGORITHM=y
38CONFIG_ARCH_HAS_ILOG2_U32=y 40CONFIG_ARCH_HAS_ILOG2_U32=y
39CONFIG_GENERIC_HWEIGHT=y 41CONFIG_GENERIC_HWEIGHT=y
40CONFIG_GENERIC_CALIBRATE_DELAY=y 42CONFIG_GENERIC_CALIBRATE_DELAY=y
41CONFIG_GENERIC_FIND_NEXT_BIT=y 43CONFIG_GENERIC_FIND_NEXT_BIT=y
44CONFIG_GENERIC_GPIO=y
42# CONFIG_ARCH_NO_VIRT_TO_BUS is not set 45# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
43CONFIG_PPC=y 46CONFIG_PPC=y
44CONFIG_EARLY_PRINTK=y 47CONFIG_EARLY_PRINTK=y
@@ -89,7 +92,6 @@ CONFIG_INITRAMFS_SOURCE=""
89CONFIG_SYSCTL=y 92CONFIG_SYSCTL=y
90CONFIG_EMBEDDED=y 93CONFIG_EMBEDDED=y
91CONFIG_SYSCTL_SYSCALL=y 94CONFIG_SYSCTL_SYSCALL=y
92CONFIG_SYSCTL_SYSCALL_CHECK=y
93# CONFIG_KALLSYMS is not set 95# CONFIG_KALLSYMS is not set
94# CONFIG_HOTPLUG is not set 96# CONFIG_HOTPLUG is not set
95CONFIG_PRINTK=y 97CONFIG_PRINTK=y
@@ -112,10 +114,16 @@ CONFIG_SLUB=y
112# CONFIG_PROFILING is not set 114# CONFIG_PROFILING is not set
113# CONFIG_MARKERS is not set 115# CONFIG_MARKERS is not set
114CONFIG_HAVE_OPROFILE=y 116CONFIG_HAVE_OPROFILE=y
117CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
118CONFIG_HAVE_IOREMAP_PROT=y
115CONFIG_HAVE_KPROBES=y 119CONFIG_HAVE_KPROBES=y
116CONFIG_HAVE_KRETPROBES=y 120CONFIG_HAVE_KRETPROBES=y
121CONFIG_HAVE_ARCH_TRACEHOOK=y
117# CONFIG_HAVE_DMA_ATTRS is not set 122# CONFIG_HAVE_DMA_ATTRS is not set
123# CONFIG_USE_GENERIC_SMP_HELPERS is not set
124CONFIG_HAVE_CLK=y
118CONFIG_PROC_PAGE_MONITOR=y 125CONFIG_PROC_PAGE_MONITOR=y
126# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
119CONFIG_SLABINFO=y 127CONFIG_SLABINFO=y
120CONFIG_RT_MUTEXES=y 128CONFIG_RT_MUTEXES=y
121# CONFIG_TINY_SHMEM is not set 129# CONFIG_TINY_SHMEM is not set
@@ -126,6 +134,7 @@ CONFIG_BLOCK=y
126# CONFIG_BLK_DEV_IO_TRACE is not set 134# CONFIG_BLK_DEV_IO_TRACE is not set
127# CONFIG_LSF is not set 135# CONFIG_LSF is not set
128# CONFIG_BLK_DEV_BSG is not set 136# CONFIG_BLK_DEV_BSG is not set
137# CONFIG_BLK_DEV_INTEGRITY is not set
129 138
130# 139#
131# IO Schedulers 140# IO Schedulers
@@ -144,8 +153,6 @@ CONFIG_CLASSIC_RCU=y
144# 153#
145# Platform support 154# Platform support
146# 155#
147# CONFIG_PPC_MPC512x is not set
148# CONFIG_PPC_MPC5121 is not set
149# CONFIG_PPC_CELL is not set 156# CONFIG_PPC_CELL is not set
150# CONFIG_PPC_CELL_NATIVE is not set 157# CONFIG_PPC_CELL_NATIVE is not set
151# CONFIG_PQ2ADS is not set 158# CONFIG_PQ2ADS is not set
@@ -154,11 +161,13 @@ CONFIG_MPC85xx=y
154# CONFIG_MPC8560_ADS is not set 161# CONFIG_MPC8560_ADS is not set
155# CONFIG_MPC85xx_CDS is not set 162# CONFIG_MPC85xx_CDS is not set
156# CONFIG_MPC85xx_MDS is not set 163# CONFIG_MPC85xx_MDS is not set
164# CONFIG_MPC8536_DS is not set
157# CONFIG_MPC85xx_DS is not set 165# CONFIG_MPC85xx_DS is not set
158# CONFIG_KSI8560 is not set 166# CONFIG_KSI8560 is not set
159# CONFIG_STX_GP3 is not set 167# CONFIG_STX_GP3 is not set
160# CONFIG_TQM8540 is not set 168# CONFIG_TQM8540 is not set
161# CONFIG_TQM8541 is not set 169# CONFIG_TQM8541 is not set
170# CONFIG_TQM8548 is not set
162CONFIG_TQM8555=y 171CONFIG_TQM8555=y
163# CONFIG_TQM8560 is not set 172# CONFIG_TQM8560 is not set
164# CONFIG_SBC8548 is not set 173# CONFIG_SBC8548 is not set
@@ -176,7 +185,6 @@ CONFIG_MPIC=y
176# CONFIG_GENERIC_IOMAP is not set 185# CONFIG_GENERIC_IOMAP is not set
177# CONFIG_CPU_FREQ is not set 186# CONFIG_CPU_FREQ is not set
178CONFIG_CPM2=y 187CONFIG_CPM2=y
179CONFIG_PPC_CPM_NEW_BINDING=y
180# CONFIG_FSL_ULI1575 is not set 188# CONFIG_FSL_ULI1575 is not set
181CONFIG_CPM=y 189CONFIG_CPM=y
182 190
@@ -216,6 +224,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
216# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set 224# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
217CONFIG_PAGEFLAGS_EXTENDED=y 225CONFIG_PAGEFLAGS_EXTENDED=y
218CONFIG_SPLIT_PTLOCK_CPUS=4 226CONFIG_SPLIT_PTLOCK_CPUS=4
227CONFIG_MIGRATION=y
219# CONFIG_RESOURCES_64BIT is not set 228# CONFIG_RESOURCES_64BIT is not set
220CONFIG_ZONE_DMA_FLAG=1 229CONFIG_ZONE_DMA_FLAG=1
221CONFIG_BOUNCE=y 230CONFIG_BOUNCE=y
@@ -223,6 +232,7 @@ CONFIG_VIRT_TO_BUS=y
223CONFIG_FORCE_MAX_ZONEORDER=11 232CONFIG_FORCE_MAX_ZONEORDER=11
224# CONFIG_PROC_DEVICETREE is not set 233# CONFIG_PROC_DEVICETREE is not set
225# CONFIG_CMDLINE_BOOL is not set 234# CONFIG_CMDLINE_BOOL is not set
235CONFIG_EXTRA_TARGETS=""
226# CONFIG_PM is not set 236# CONFIG_PM is not set
227CONFIG_SECCOMP=y 237CONFIG_SECCOMP=y
228CONFIG_ISA_DMA_API=y 238CONFIG_ISA_DMA_API=y
@@ -234,6 +244,7 @@ CONFIG_ZONE_DMA=y
234CONFIG_PPC_INDIRECT_PCI=y 244CONFIG_PPC_INDIRECT_PCI=y
235CONFIG_FSL_SOC=y 245CONFIG_FSL_SOC=y
236CONFIG_FSL_PCI=y 246CONFIG_FSL_PCI=y
247CONFIG_PPC_PCI_CHOICE=y
237CONFIG_PCI=y 248CONFIG_PCI=y
238CONFIG_PCI_DOMAINS=y 249CONFIG_PCI_DOMAINS=y
239CONFIG_PCI_SYSCALL=y 250CONFIG_PCI_SYSCALL=y
@@ -257,10 +268,6 @@ CONFIG_KERNEL_START=0xc0000000
257CONFIG_PHYSICAL_START=0x00000000 268CONFIG_PHYSICAL_START=0x00000000
258CONFIG_PHYSICAL_ALIGN=0x10000000 269CONFIG_PHYSICAL_ALIGN=0x10000000
259CONFIG_TASK_SIZE=0xc0000000 270CONFIG_TASK_SIZE=0xc0000000
260
261#
262# Networking
263#
264CONFIG_NET=y 271CONFIG_NET=y
265 272
266# 273#
@@ -432,6 +439,7 @@ CONFIG_MTD_CFI_UTIL=y
432# 439#
433# CONFIG_MTD_UBI is not set 440# CONFIG_MTD_UBI is not set
434CONFIG_OF_DEVICE=y 441CONFIG_OF_DEVICE=y
442CONFIG_OF_GPIO=y
435CONFIG_OF_I2C=y 443CONFIG_OF_I2C=y
436# CONFIG_PARPORT is not set 444# CONFIG_PARPORT is not set
437CONFIG_BLK_DEV=y 445CONFIG_BLK_DEV=y
@@ -451,20 +459,22 @@ CONFIG_BLK_DEV_RAM_SIZE=32768
451# CONFIG_BLK_DEV_XIP is not set 459# CONFIG_BLK_DEV_XIP is not set
452# CONFIG_CDROM_PKTCDVD is not set 460# CONFIG_CDROM_PKTCDVD is not set
453# CONFIG_ATA_OVER_ETH is not set 461# CONFIG_ATA_OVER_ETH is not set
462# CONFIG_BLK_DEV_HD is not set
454CONFIG_MISC_DEVICES=y 463CONFIG_MISC_DEVICES=y
455# CONFIG_PHANTOM is not set 464# CONFIG_PHANTOM is not set
456# CONFIG_EEPROM_93CX6 is not set 465# CONFIG_EEPROM_93CX6 is not set
457# CONFIG_SGI_IOC4 is not set 466# CONFIG_SGI_IOC4 is not set
458# CONFIG_TIFM_CORE is not set 467# CONFIG_TIFM_CORE is not set
459# CONFIG_ENCLOSURE_SERVICES is not set 468# CONFIG_ENCLOSURE_SERVICES is not set
469# CONFIG_HP_ILO is not set
460CONFIG_HAVE_IDE=y 470CONFIG_HAVE_IDE=y
461CONFIG_IDE=y 471CONFIG_IDE=y
462CONFIG_IDE_MAX_HWIFS=4
463CONFIG_BLK_DEV_IDE=y 472CONFIG_BLK_DEV_IDE=y
464 473
465# 474#
466# Please see Documentation/ide/ide.txt for help/info on IDE drives 475# Please see Documentation/ide/ide.txt for help/info on IDE drives
467# 476#
477CONFIG_IDE_TIMINGS=y
468# CONFIG_BLK_DEV_IDE_SATA is not set 478# CONFIG_BLK_DEV_IDE_SATA is not set
469CONFIG_BLK_DEV_IDEDISK=y 479CONFIG_BLK_DEV_IDEDISK=y
470# CONFIG_IDEDISK_MULTI_MODE is not set 480# CONFIG_IDEDISK_MULTI_MODE is not set
@@ -477,7 +487,6 @@ CONFIG_IDE_PROC_FS=y
477# 487#
478# IDE chipset support/bugfixes 488# IDE chipset support/bugfixes
479# 489#
480CONFIG_IDE_GENERIC=y
481# CONFIG_BLK_DEV_PLATFORM is not set 490# CONFIG_BLK_DEV_PLATFORM is not set
482CONFIG_BLK_DEV_IDEDMA_SFF=y 491CONFIG_BLK_DEV_IDEDMA_SFF=y
483 492
@@ -495,10 +504,8 @@ CONFIG_BLK_DEV_IDEDMA_PCI=y
495# CONFIG_BLK_DEV_AMD74XX is not set 504# CONFIG_BLK_DEV_AMD74XX is not set
496# CONFIG_BLK_DEV_CMD64X is not set 505# CONFIG_BLK_DEV_CMD64X is not set
497# CONFIG_BLK_DEV_TRIFLEX is not set 506# CONFIG_BLK_DEV_TRIFLEX is not set
498# CONFIG_BLK_DEV_CY82C693 is not set
499# CONFIG_BLK_DEV_CS5520 is not set 507# CONFIG_BLK_DEV_CS5520 is not set
500# CONFIG_BLK_DEV_CS5530 is not set 508# CONFIG_BLK_DEV_CS5530 is not set
501# CONFIG_BLK_DEV_HPT34X is not set
502# CONFIG_BLK_DEV_HPT366 is not set 509# CONFIG_BLK_DEV_HPT366 is not set
503# CONFIG_BLK_DEV_JMICRON is not set 510# CONFIG_BLK_DEV_JMICRON is not set
504# CONFIG_BLK_DEV_SC1200 is not set 511# CONFIG_BLK_DEV_SC1200 is not set
@@ -516,8 +523,6 @@ CONFIG_BLK_DEV_IDEDMA_PCI=y
516CONFIG_BLK_DEV_VIA82CXXX=y 523CONFIG_BLK_DEV_VIA82CXXX=y
517# CONFIG_BLK_DEV_TC86C001 is not set 524# CONFIG_BLK_DEV_TC86C001 is not set
518CONFIG_BLK_DEV_IDEDMA=y 525CONFIG_BLK_DEV_IDEDMA=y
519# CONFIG_BLK_DEV_HD_ONLY is not set
520# CONFIG_BLK_DEV_HD is not set
521 526
522# 527#
523# SCSI device support 528# SCSI device support
@@ -533,12 +538,15 @@ CONFIG_BLK_DEV_IDEDMA=y
533# 538#
534# IEEE 1394 (FireWire) support 539# IEEE 1394 (FireWire) support
535# 540#
541
542#
543# Enable only one of the two stacks, unless you know what you are doing
544#
536# CONFIG_FIREWIRE is not set 545# CONFIG_FIREWIRE is not set
537# CONFIG_IEEE1394 is not set 546# CONFIG_IEEE1394 is not set
538# CONFIG_I2O is not set 547# CONFIG_I2O is not set
539# CONFIG_MACINTOSH_DRIVERS is not set 548# CONFIG_MACINTOSH_DRIVERS is not set
540CONFIG_NETDEVICES=y 549CONFIG_NETDEVICES=y
541# CONFIG_NETDEVICES_MULTIQUEUE is not set
542# CONFIG_DUMMY is not set 550# CONFIG_DUMMY is not set
543# CONFIG_BONDING is not set 551# CONFIG_BONDING is not set
544# CONFIG_MACVLAN is not set 552# CONFIG_MACVLAN is not set
@@ -601,7 +609,6 @@ CONFIG_NETDEV_1000=y
601# CONFIG_DL2K is not set 609# CONFIG_DL2K is not set
602# CONFIG_E1000 is not set 610# CONFIG_E1000 is not set
603# CONFIG_E1000E is not set 611# CONFIG_E1000E is not set
604# CONFIG_E1000E_ENABLED is not set
605# CONFIG_IP1000 is not set 612# CONFIG_IP1000 is not set
606# CONFIG_IGB is not set 613# CONFIG_IGB is not set
607# CONFIG_NS83820 is not set 614# CONFIG_NS83820 is not set
@@ -615,9 +622,9 @@ CONFIG_NETDEV_1000=y
615# CONFIG_TIGON3 is not set 622# CONFIG_TIGON3 is not set
616# CONFIG_BNX2 is not set 623# CONFIG_BNX2 is not set
617CONFIG_GIANFAR=y 624CONFIG_GIANFAR=y
618CONFIG_GFAR_NAPI=y
619# CONFIG_QLA3XXX is not set 625# CONFIG_QLA3XXX is not set
620# CONFIG_ATL1 is not set 626# CONFIG_ATL1 is not set
627# CONFIG_ATL1E is not set
621CONFIG_NETDEV_10000=y 628CONFIG_NETDEV_10000=y
622# CONFIG_CHELSIO_T1 is not set 629# CONFIG_CHELSIO_T1 is not set
623# CONFIG_CHELSIO_T3 is not set 630# CONFIG_CHELSIO_T3 is not set
@@ -732,42 +739,66 @@ CONFIG_DEVPORT=y
732CONFIG_I2C=y 739CONFIG_I2C=y
733CONFIG_I2C_BOARDINFO=y 740CONFIG_I2C_BOARDINFO=y
734CONFIG_I2C_CHARDEV=y 741CONFIG_I2C_CHARDEV=y
742CONFIG_I2C_HELPER_AUTO=y
735 743
736# 744#
737# I2C Hardware Bus support 745# I2C Hardware Bus support
738# 746#
747
748#
749# PC SMBus host controller drivers
750#
739# CONFIG_I2C_ALI1535 is not set 751# CONFIG_I2C_ALI1535 is not set
740# CONFIG_I2C_ALI1563 is not set 752# CONFIG_I2C_ALI1563 is not set
741# CONFIG_I2C_ALI15X3 is not set 753# CONFIG_I2C_ALI15X3 is not set
742# CONFIG_I2C_AMD756 is not set 754# CONFIG_I2C_AMD756 is not set
743# CONFIG_I2C_AMD8111 is not set 755# CONFIG_I2C_AMD8111 is not set
744# CONFIG_I2C_I801 is not set 756# CONFIG_I2C_I801 is not set
745# CONFIG_I2C_I810 is not set 757# CONFIG_I2C_ISCH is not set
746# CONFIG_I2C_PIIX4 is not set 758# CONFIG_I2C_PIIX4 is not set
747CONFIG_I2C_MPC=y
748# CONFIG_I2C_NFORCE2 is not set 759# CONFIG_I2C_NFORCE2 is not set
749# CONFIG_I2C_OCORES is not set
750# CONFIG_I2C_PARPORT_LIGHT is not set
751# CONFIG_I2C_PROSAVAGE is not set
752# CONFIG_I2C_SAVAGE4 is not set
753# CONFIG_I2C_SIMTEC is not set
754# CONFIG_I2C_SIS5595 is not set 760# CONFIG_I2C_SIS5595 is not set
755# CONFIG_I2C_SIS630 is not set 761# CONFIG_I2C_SIS630 is not set
756# CONFIG_I2C_SIS96X is not set 762# CONFIG_I2C_SIS96X is not set
757# CONFIG_I2C_TAOS_EVM is not set
758# CONFIG_I2C_VIA is not set 763# CONFIG_I2C_VIA is not set
759# CONFIG_I2C_VIAPRO is not set 764# CONFIG_I2C_VIAPRO is not set
765
766#
767# I2C system bus drivers (mostly embedded / system-on-chip)
768#
769# CONFIG_I2C_CPM is not set
770# CONFIG_I2C_GPIO is not set
771CONFIG_I2C_MPC=y
772# CONFIG_I2C_OCORES is not set
773# CONFIG_I2C_SIMTEC is not set
774
775#
776# External I2C/SMBus adapter drivers
777#
778# CONFIG_I2C_PARPORT_LIGHT is not set
779# CONFIG_I2C_TAOS_EVM is not set
780
781#
782# Graphics adapter I2C/DDC channel drivers
783#
760# CONFIG_I2C_VOODOO3 is not set 784# CONFIG_I2C_VOODOO3 is not set
785
786#
787# Other I2C/SMBus bus drivers
788#
761# CONFIG_I2C_PCA_PLATFORM is not set 789# CONFIG_I2C_PCA_PLATFORM is not set
762 790
763# 791#
764# Miscellaneous I2C Chip support 792# Miscellaneous I2C Chip support
765# 793#
766# CONFIG_DS1682 is not set 794# CONFIG_DS1682 is not set
795# CONFIG_AT24 is not set
767# CONFIG_SENSORS_EEPROM is not set 796# CONFIG_SENSORS_EEPROM is not set
768# CONFIG_SENSORS_PCF8574 is not set 797# CONFIG_SENSORS_PCF8574 is not set
769# CONFIG_PCF8575 is not set 798# CONFIG_PCF8575 is not set
799# CONFIG_SENSORS_PCA9539 is not set
770# CONFIG_SENSORS_PCF8591 is not set 800# CONFIG_SENSORS_PCF8591 is not set
801# CONFIG_TPS65010 is not set
771# CONFIG_SENSORS_MAX6875 is not set 802# CONFIG_SENSORS_MAX6875 is not set
772# CONFIG_SENSORS_TSL2550 is not set 803# CONFIG_SENSORS_TSL2550 is not set
773# CONFIG_I2C_DEBUG_CORE is not set 804# CONFIG_I2C_DEBUG_CORE is not set
@@ -775,10 +806,31 @@ CONFIG_I2C_MPC=y
775# CONFIG_I2C_DEBUG_BUS is not set 806# CONFIG_I2C_DEBUG_BUS is not set
776# CONFIG_I2C_DEBUG_CHIP is not set 807# CONFIG_I2C_DEBUG_CHIP is not set
777# CONFIG_SPI is not set 808# CONFIG_SPI is not set
809CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
810CONFIG_ARCH_REQUIRE_GPIOLIB=y
811CONFIG_GPIOLIB=y
812# CONFIG_GPIO_SYSFS is not set
813
814#
815# I2C GPIO expanders:
816#
817# CONFIG_GPIO_MAX732X is not set
818# CONFIG_GPIO_PCA953X is not set
819# CONFIG_GPIO_PCF857X is not set
820
821#
822# PCI GPIO expanders:
823#
824# CONFIG_GPIO_BT8XX is not set
825
826#
827# SPI GPIO expanders:
828#
778# CONFIG_W1 is not set 829# CONFIG_W1 is not set
779# CONFIG_POWER_SUPPLY is not set 830# CONFIG_POWER_SUPPLY is not set
780CONFIG_HWMON=y 831CONFIG_HWMON=y
781# CONFIG_HWMON_VID is not set 832# CONFIG_HWMON_VID is not set
833# CONFIG_SENSORS_AD7414 is not set
782# CONFIG_SENSORS_AD7418 is not set 834# CONFIG_SENSORS_AD7418 is not set
783# CONFIG_SENSORS_ADM1021 is not set 835# CONFIG_SENSORS_ADM1021 is not set
784# CONFIG_SENSORS_ADM1025 is not set 836# CONFIG_SENSORS_ADM1025 is not set
@@ -832,6 +884,7 @@ CONFIG_SENSORS_LM75=y
832# CONFIG_SENSORS_W83627EHF is not set 884# CONFIG_SENSORS_W83627EHF is not set
833CONFIG_HWMON_DEBUG_CHIP=y 885CONFIG_HWMON_DEBUG_CHIP=y
834# CONFIG_THERMAL is not set 886# CONFIG_THERMAL is not set
887# CONFIG_THERMAL_HWMON is not set
835# CONFIG_WATCHDOG is not set 888# CONFIG_WATCHDOG is not set
836 889
837# 890#
@@ -843,8 +896,10 @@ CONFIG_SSB_POSSIBLE=y
843# 896#
844# Multifunction device drivers 897# Multifunction device drivers
845# 898#
899# CONFIG_MFD_CORE is not set
846# CONFIG_MFD_SM501 is not set 900# CONFIG_MFD_SM501 is not set
847# CONFIG_HTC_PASIC3 is not set 901# CONFIG_HTC_PASIC3 is not set
902# CONFIG_MFD_TMIO is not set
848 903
849# 904#
850# Multimedia devices 905# Multimedia devices
@@ -876,10 +931,6 @@ CONFIG_DAB=y
876# Display device support 931# Display device support
877# 932#
878# CONFIG_DISPLAY_SUPPORT is not set 933# CONFIG_DISPLAY_SUPPORT is not set
879
880#
881# Sound
882#
883# CONFIG_SOUND is not set 934# CONFIG_SOUND is not set
884CONFIG_HID_SUPPORT=y 935CONFIG_HID_SUPPORT=y
885CONFIG_HID=y 936CONFIG_HID=y
@@ -894,6 +945,10 @@ CONFIG_USB_ARCH_HAS_EHCI=y
894# CONFIG_USB_OTG_BLACKLIST_HUB is not set 945# CONFIG_USB_OTG_BLACKLIST_HUB is not set
895 946
896# 947#
948# Enable Host or Gadget support to see Inventra options
949#
950
951#
897# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 952# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
898# 953#
899# CONFIG_USB_GADGET is not set 954# CONFIG_USB_GADGET is not set
@@ -982,6 +1037,7 @@ CONFIG_JFFS2_RTIME=y
982CONFIG_CRAMFS=y 1037CONFIG_CRAMFS=y
983# CONFIG_VXFS_FS is not set 1038# CONFIG_VXFS_FS is not set
984# CONFIG_MINIX_FS is not set 1039# CONFIG_MINIX_FS is not set
1040# CONFIG_OMFS_FS is not set
985# CONFIG_HPFS_FS is not set 1041# CONFIG_HPFS_FS is not set
986# CONFIG_QNX4FS_FS is not set 1042# CONFIG_QNX4FS_FS is not set
987# CONFIG_ROMFS_FS is not set 1043# CONFIG_ROMFS_FS is not set
@@ -991,12 +1047,11 @@ CONFIG_NETWORK_FILESYSTEMS=y
991CONFIG_NFS_FS=y 1047CONFIG_NFS_FS=y
992# CONFIG_NFS_V3 is not set 1048# CONFIG_NFS_V3 is not set
993# CONFIG_NFS_V4 is not set 1049# CONFIG_NFS_V4 is not set
994# CONFIG_NFSD is not set
995CONFIG_ROOT_NFS=y 1050CONFIG_ROOT_NFS=y
1051# CONFIG_NFSD is not set
996CONFIG_LOCKD=y 1052CONFIG_LOCKD=y
997CONFIG_NFS_COMMON=y 1053CONFIG_NFS_COMMON=y
998CONFIG_SUNRPC=y 1054CONFIG_SUNRPC=y
999# CONFIG_SUNRPC_BIND34 is not set
1000# CONFIG_RPCSEC_GSS_KRB5 is not set 1055# CONFIG_RPCSEC_GSS_KRB5 is not set
1001# CONFIG_RPCSEC_GSS_SPKM3 is not set 1056# CONFIG_RPCSEC_GSS_SPKM3 is not set
1002# CONFIG_SMB_FS is not set 1057# CONFIG_SMB_FS is not set
@@ -1032,6 +1087,7 @@ CONFIG_BITREVERSE=y
1032# CONFIG_GENERIC_FIND_FIRST_BIT is not set 1087# CONFIG_GENERIC_FIND_FIRST_BIT is not set
1033# CONFIG_CRC_CCITT is not set 1088# CONFIG_CRC_CCITT is not set
1034# CONFIG_CRC16 is not set 1089# CONFIG_CRC16 is not set
1090# CONFIG_CRC_T10DIF is not set
1035# CONFIG_CRC_ITU_T is not set 1091# CONFIG_CRC_ITU_T is not set
1036CONFIG_CRC32=y 1092CONFIG_CRC32=y
1037# CONFIG_CRC7 is not set 1093# CONFIG_CRC7 is not set
@@ -1059,8 +1115,16 @@ CONFIG_FRAME_WARN=1024
1059# CONFIG_SLUB_DEBUG_ON is not set 1115# CONFIG_SLUB_DEBUG_ON is not set
1060# CONFIG_SLUB_STATS is not set 1116# CONFIG_SLUB_STATS is not set
1061# CONFIG_DEBUG_BUGVERBOSE is not set 1117# CONFIG_DEBUG_BUGVERBOSE is not set
1118# CONFIG_DEBUG_MEMORY_INIT is not set
1119# CONFIG_LATENCYTOP is not set
1120CONFIG_SYSCTL_SYSCALL_CHECK=y
1121CONFIG_HAVE_FTRACE=y
1122CONFIG_HAVE_DYNAMIC_FTRACE=y
1123# CONFIG_FTRACE is not set
1124# CONFIG_SCHED_TRACER is not set
1125# CONFIG_CONTEXT_SWITCH_TRACER is not set
1062# CONFIG_SAMPLES is not set 1126# CONFIG_SAMPLES is not set
1063# CONFIG_KGDB_CONSOLE is not set 1127CONFIG_HAVE_ARCH_KGDB=y
1064# CONFIG_IRQSTACKS is not set 1128# CONFIG_IRQSTACKS is not set
1065# CONFIG_PPC_EARLY_DEBUG is not set 1129# CONFIG_PPC_EARLY_DEBUG is not set
1066 1130
@@ -1112,6 +1176,10 @@ CONFIG_CRYPTO=y
1112# CONFIG_CRYPTO_MD4 is not set 1176# CONFIG_CRYPTO_MD4 is not set
1113# CONFIG_CRYPTO_MD5 is not set 1177# CONFIG_CRYPTO_MD5 is not set
1114# CONFIG_CRYPTO_MICHAEL_MIC is not set 1178# CONFIG_CRYPTO_MICHAEL_MIC is not set
1179# CONFIG_CRYPTO_RMD128 is not set
1180# CONFIG_CRYPTO_RMD160 is not set
1181# CONFIG_CRYPTO_RMD256 is not set
1182# CONFIG_CRYPTO_RMD320 is not set
1115# CONFIG_CRYPTO_SHA1 is not set 1183# CONFIG_CRYPTO_SHA1 is not set
1116# CONFIG_CRYPTO_SHA256 is not set 1184# CONFIG_CRYPTO_SHA256 is not set
1117# CONFIG_CRYPTO_SHA512 is not set 1185# CONFIG_CRYPTO_SHA512 is not set
@@ -1144,6 +1212,7 @@ CONFIG_CRYPTO=y
1144# CONFIG_CRYPTO_LZO is not set 1212# CONFIG_CRYPTO_LZO is not set
1145CONFIG_CRYPTO_HW=y 1213CONFIG_CRYPTO_HW=y
1146# CONFIG_CRYPTO_DEV_HIFN_795X is not set 1214# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1147# CONFIG_PPC_CLOCK is not set 1215# CONFIG_CRYPTO_DEV_TALITOS is not set
1216CONFIG_PPC_CLOCK=y
1148CONFIG_PPC_LIB_RHEAP=y 1217CONFIG_PPC_LIB_RHEAP=y
1149# CONFIG_VIRTUALIZATION is not set 1218# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/configs/85xx/tqm8560_defconfig b/arch/powerpc/configs/85xx/tqm8560_defconfig
index 3113257edf5a..8d676629cdb1 100644
--- a/arch/powerpc/configs/85xx/tqm8560_defconfig
+++ b/arch/powerpc/configs/85xx/tqm8560_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc5 3# Linux kernel version: 2.6.27-rc4
4# Mon Jun 9 08:52:42 2008 4# Thu Aug 21 00:52:43 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -15,6 +15,7 @@ CONFIG_PPC_85xx=y
15# CONFIG_44x is not set 15# CONFIG_44x is not set
16# CONFIG_E200 is not set 16# CONFIG_E200 is not set
17CONFIG_E500=y 17CONFIG_E500=y
18# CONFIG_PPC_E500MC is not set
18CONFIG_BOOKE=y 19CONFIG_BOOKE=y
19CONFIG_FSL_BOOKE=y 20CONFIG_FSL_BOOKE=y
20CONFIG_FSL_EMB_PERFMON=y 21CONFIG_FSL_EMB_PERFMON=y
@@ -33,12 +34,14 @@ CONFIG_GENERIC_HARDIRQS=y
33# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set 34# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
34CONFIG_IRQ_PER_CPU=y 35CONFIG_IRQ_PER_CPU=y
35CONFIG_STACKTRACE_SUPPORT=y 36CONFIG_STACKTRACE_SUPPORT=y
37CONFIG_HAVE_LATENCYTOP_SUPPORT=y
36CONFIG_LOCKDEP_SUPPORT=y 38CONFIG_LOCKDEP_SUPPORT=y
37CONFIG_RWSEM_XCHGADD_ALGORITHM=y 39CONFIG_RWSEM_XCHGADD_ALGORITHM=y
38CONFIG_ARCH_HAS_ILOG2_U32=y 40CONFIG_ARCH_HAS_ILOG2_U32=y
39CONFIG_GENERIC_HWEIGHT=y 41CONFIG_GENERIC_HWEIGHT=y
40CONFIG_GENERIC_CALIBRATE_DELAY=y 42CONFIG_GENERIC_CALIBRATE_DELAY=y
41CONFIG_GENERIC_FIND_NEXT_BIT=y 43CONFIG_GENERIC_FIND_NEXT_BIT=y
44CONFIG_GENERIC_GPIO=y
42# CONFIG_ARCH_NO_VIRT_TO_BUS is not set 45# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
43CONFIG_PPC=y 46CONFIG_PPC=y
44CONFIG_EARLY_PRINTK=y 47CONFIG_EARLY_PRINTK=y
@@ -89,7 +92,6 @@ CONFIG_INITRAMFS_SOURCE=""
89CONFIG_SYSCTL=y 92CONFIG_SYSCTL=y
90CONFIG_EMBEDDED=y 93CONFIG_EMBEDDED=y
91CONFIG_SYSCTL_SYSCALL=y 94CONFIG_SYSCTL_SYSCALL=y
92CONFIG_SYSCTL_SYSCALL_CHECK=y
93# CONFIG_KALLSYMS is not set 95# CONFIG_KALLSYMS is not set
94# CONFIG_HOTPLUG is not set 96# CONFIG_HOTPLUG is not set
95CONFIG_PRINTK=y 97CONFIG_PRINTK=y
@@ -112,10 +114,16 @@ CONFIG_SLUB=y
112# CONFIG_PROFILING is not set 114# CONFIG_PROFILING is not set
113# CONFIG_MARKERS is not set 115# CONFIG_MARKERS is not set
114CONFIG_HAVE_OPROFILE=y 116CONFIG_HAVE_OPROFILE=y
117CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
118CONFIG_HAVE_IOREMAP_PROT=y
115CONFIG_HAVE_KPROBES=y 119CONFIG_HAVE_KPROBES=y
116CONFIG_HAVE_KRETPROBES=y 120CONFIG_HAVE_KRETPROBES=y
121CONFIG_HAVE_ARCH_TRACEHOOK=y
117# CONFIG_HAVE_DMA_ATTRS is not set 122# CONFIG_HAVE_DMA_ATTRS is not set
123# CONFIG_USE_GENERIC_SMP_HELPERS is not set
124CONFIG_HAVE_CLK=y
118CONFIG_PROC_PAGE_MONITOR=y 125CONFIG_PROC_PAGE_MONITOR=y
126# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
119CONFIG_SLABINFO=y 127CONFIG_SLABINFO=y
120CONFIG_RT_MUTEXES=y 128CONFIG_RT_MUTEXES=y
121# CONFIG_TINY_SHMEM is not set 129# CONFIG_TINY_SHMEM is not set
@@ -126,6 +134,7 @@ CONFIG_BLOCK=y
126# CONFIG_BLK_DEV_IO_TRACE is not set 134# CONFIG_BLK_DEV_IO_TRACE is not set
127# CONFIG_LSF is not set 135# CONFIG_LSF is not set
128# CONFIG_BLK_DEV_BSG is not set 136# CONFIG_BLK_DEV_BSG is not set
137# CONFIG_BLK_DEV_INTEGRITY is not set
129 138
130# 139#
131# IO Schedulers 140# IO Schedulers
@@ -144,8 +153,6 @@ CONFIG_CLASSIC_RCU=y
144# 153#
145# Platform support 154# Platform support
146# 155#
147# CONFIG_PPC_MPC512x is not set
148# CONFIG_PPC_MPC5121 is not set
149# CONFIG_PPC_CELL is not set 156# CONFIG_PPC_CELL is not set
150# CONFIG_PPC_CELL_NATIVE is not set 157# CONFIG_PPC_CELL_NATIVE is not set
151# CONFIG_PQ2ADS is not set 158# CONFIG_PQ2ADS is not set
@@ -154,11 +161,13 @@ CONFIG_MPC85xx=y
154# CONFIG_MPC8560_ADS is not set 161# CONFIG_MPC8560_ADS is not set
155# CONFIG_MPC85xx_CDS is not set 162# CONFIG_MPC85xx_CDS is not set
156# CONFIG_MPC85xx_MDS is not set 163# CONFIG_MPC85xx_MDS is not set
164# CONFIG_MPC8536_DS is not set
157# CONFIG_MPC85xx_DS is not set 165# CONFIG_MPC85xx_DS is not set
158# CONFIG_KSI8560 is not set 166# CONFIG_KSI8560 is not set
159# CONFIG_STX_GP3 is not set 167# CONFIG_STX_GP3 is not set
160# CONFIG_TQM8540 is not set 168# CONFIG_TQM8540 is not set
161# CONFIG_TQM8541 is not set 169# CONFIG_TQM8541 is not set
170# CONFIG_TQM8548 is not set
162# CONFIG_TQM8555 is not set 171# CONFIG_TQM8555 is not set
163CONFIG_TQM8560=y 172CONFIG_TQM8560=y
164# CONFIG_SBC8548 is not set 173# CONFIG_SBC8548 is not set
@@ -176,7 +185,6 @@ CONFIG_MPIC=y
176# CONFIG_GENERIC_IOMAP is not set 185# CONFIG_GENERIC_IOMAP is not set
177# CONFIG_CPU_FREQ is not set 186# CONFIG_CPU_FREQ is not set
178CONFIG_CPM2=y 187CONFIG_CPM2=y
179CONFIG_PPC_CPM_NEW_BINDING=y
180# CONFIG_FSL_ULI1575 is not set 188# CONFIG_FSL_ULI1575 is not set
181CONFIG_CPM=y 189CONFIG_CPM=y
182 190
@@ -216,6 +224,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
216# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set 224# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
217CONFIG_PAGEFLAGS_EXTENDED=y 225CONFIG_PAGEFLAGS_EXTENDED=y
218CONFIG_SPLIT_PTLOCK_CPUS=4 226CONFIG_SPLIT_PTLOCK_CPUS=4
227CONFIG_MIGRATION=y
219# CONFIG_RESOURCES_64BIT is not set 228# CONFIG_RESOURCES_64BIT is not set
220CONFIG_ZONE_DMA_FLAG=1 229CONFIG_ZONE_DMA_FLAG=1
221CONFIG_BOUNCE=y 230CONFIG_BOUNCE=y
@@ -223,6 +232,7 @@ CONFIG_VIRT_TO_BUS=y
223CONFIG_FORCE_MAX_ZONEORDER=11 232CONFIG_FORCE_MAX_ZONEORDER=11
224# CONFIG_PROC_DEVICETREE is not set 233# CONFIG_PROC_DEVICETREE is not set
225# CONFIG_CMDLINE_BOOL is not set 234# CONFIG_CMDLINE_BOOL is not set
235CONFIG_EXTRA_TARGETS=""
226# CONFIG_PM is not set 236# CONFIG_PM is not set
227CONFIG_SECCOMP=y 237CONFIG_SECCOMP=y
228CONFIG_ISA_DMA_API=y 238CONFIG_ISA_DMA_API=y
@@ -234,6 +244,7 @@ CONFIG_ZONE_DMA=y
234CONFIG_PPC_INDIRECT_PCI=y 244CONFIG_PPC_INDIRECT_PCI=y
235CONFIG_FSL_SOC=y 245CONFIG_FSL_SOC=y
236CONFIG_FSL_PCI=y 246CONFIG_FSL_PCI=y
247CONFIG_PPC_PCI_CHOICE=y
237CONFIG_PCI=y 248CONFIG_PCI=y
238CONFIG_PCI_DOMAINS=y 249CONFIG_PCI_DOMAINS=y
239CONFIG_PCI_SYSCALL=y 250CONFIG_PCI_SYSCALL=y
@@ -257,10 +268,6 @@ CONFIG_KERNEL_START=0xc0000000
257CONFIG_PHYSICAL_START=0x00000000 268CONFIG_PHYSICAL_START=0x00000000
258CONFIG_PHYSICAL_ALIGN=0x10000000 269CONFIG_PHYSICAL_ALIGN=0x10000000
259CONFIG_TASK_SIZE=0xc0000000 270CONFIG_TASK_SIZE=0xc0000000
260
261#
262# Networking
263#
264CONFIG_NET=y 271CONFIG_NET=y
265 272
266# 273#
@@ -432,6 +439,7 @@ CONFIG_MTD_CFI_UTIL=y
432# 439#
433# CONFIG_MTD_UBI is not set 440# CONFIG_MTD_UBI is not set
434CONFIG_OF_DEVICE=y 441CONFIG_OF_DEVICE=y
442CONFIG_OF_GPIO=y
435CONFIG_OF_I2C=y 443CONFIG_OF_I2C=y
436# CONFIG_PARPORT is not set 444# CONFIG_PARPORT is not set
437CONFIG_BLK_DEV=y 445CONFIG_BLK_DEV=y
@@ -451,20 +459,22 @@ CONFIG_BLK_DEV_RAM_SIZE=32768
451# CONFIG_BLK_DEV_XIP is not set 459# CONFIG_BLK_DEV_XIP is not set
452# CONFIG_CDROM_PKTCDVD is not set 460# CONFIG_CDROM_PKTCDVD is not set
453# CONFIG_ATA_OVER_ETH is not set 461# CONFIG_ATA_OVER_ETH is not set
462# CONFIG_BLK_DEV_HD is not set
454CONFIG_MISC_DEVICES=y 463CONFIG_MISC_DEVICES=y
455# CONFIG_PHANTOM is not set 464# CONFIG_PHANTOM is not set
456# CONFIG_EEPROM_93CX6 is not set 465# CONFIG_EEPROM_93CX6 is not set
457# CONFIG_SGI_IOC4 is not set 466# CONFIG_SGI_IOC4 is not set
458# CONFIG_TIFM_CORE is not set 467# CONFIG_TIFM_CORE is not set
459# CONFIG_ENCLOSURE_SERVICES is not set 468# CONFIG_ENCLOSURE_SERVICES is not set
469# CONFIG_HP_ILO is not set
460CONFIG_HAVE_IDE=y 470CONFIG_HAVE_IDE=y
461CONFIG_IDE=y 471CONFIG_IDE=y
462CONFIG_IDE_MAX_HWIFS=4
463CONFIG_BLK_DEV_IDE=y 472CONFIG_BLK_DEV_IDE=y
464 473
465# 474#
466# Please see Documentation/ide/ide.txt for help/info on IDE drives 475# Please see Documentation/ide/ide.txt for help/info on IDE drives
467# 476#
477CONFIG_IDE_TIMINGS=y
468# CONFIG_BLK_DEV_IDE_SATA is not set 478# CONFIG_BLK_DEV_IDE_SATA is not set
469CONFIG_BLK_DEV_IDEDISK=y 479CONFIG_BLK_DEV_IDEDISK=y
470# CONFIG_IDEDISK_MULTI_MODE is not set 480# CONFIG_IDEDISK_MULTI_MODE is not set
@@ -477,7 +487,6 @@ CONFIG_IDE_PROC_FS=y
477# 487#
478# IDE chipset support/bugfixes 488# IDE chipset support/bugfixes
479# 489#
480CONFIG_IDE_GENERIC=y
481# CONFIG_BLK_DEV_PLATFORM is not set 490# CONFIG_BLK_DEV_PLATFORM is not set
482CONFIG_BLK_DEV_IDEDMA_SFF=y 491CONFIG_BLK_DEV_IDEDMA_SFF=y
483 492
@@ -495,10 +504,8 @@ CONFIG_BLK_DEV_IDEDMA_PCI=y
495# CONFIG_BLK_DEV_AMD74XX is not set 504# CONFIG_BLK_DEV_AMD74XX is not set
496# CONFIG_BLK_DEV_CMD64X is not set 505# CONFIG_BLK_DEV_CMD64X is not set
497# CONFIG_BLK_DEV_TRIFLEX is not set 506# CONFIG_BLK_DEV_TRIFLEX is not set
498# CONFIG_BLK_DEV_CY82C693 is not set
499# CONFIG_BLK_DEV_CS5520 is not set 507# CONFIG_BLK_DEV_CS5520 is not set
500# CONFIG_BLK_DEV_CS5530 is not set 508# CONFIG_BLK_DEV_CS5530 is not set
501# CONFIG_BLK_DEV_HPT34X is not set
502# CONFIG_BLK_DEV_HPT366 is not set 509# CONFIG_BLK_DEV_HPT366 is not set
503# CONFIG_BLK_DEV_JMICRON is not set 510# CONFIG_BLK_DEV_JMICRON is not set
504# CONFIG_BLK_DEV_SC1200 is not set 511# CONFIG_BLK_DEV_SC1200 is not set
@@ -516,8 +523,6 @@ CONFIG_BLK_DEV_IDEDMA_PCI=y
516CONFIG_BLK_DEV_VIA82CXXX=y 523CONFIG_BLK_DEV_VIA82CXXX=y
517# CONFIG_BLK_DEV_TC86C001 is not set 524# CONFIG_BLK_DEV_TC86C001 is not set
518CONFIG_BLK_DEV_IDEDMA=y 525CONFIG_BLK_DEV_IDEDMA=y
519# CONFIG_BLK_DEV_HD_ONLY is not set
520# CONFIG_BLK_DEV_HD is not set
521 526
522# 527#
523# SCSI device support 528# SCSI device support
@@ -533,12 +538,15 @@ CONFIG_BLK_DEV_IDEDMA=y
533# 538#
534# IEEE 1394 (FireWire) support 539# IEEE 1394 (FireWire) support
535# 540#
541
542#
543# Enable only one of the two stacks, unless you know what you are doing
544#
536# CONFIG_FIREWIRE is not set 545# CONFIG_FIREWIRE is not set
537# CONFIG_IEEE1394 is not set 546# CONFIG_IEEE1394 is not set
538# CONFIG_I2O is not set 547# CONFIG_I2O is not set
539# CONFIG_MACINTOSH_DRIVERS is not set 548# CONFIG_MACINTOSH_DRIVERS is not set
540CONFIG_NETDEVICES=y 549CONFIG_NETDEVICES=y
541# CONFIG_NETDEVICES_MULTIQUEUE is not set
542# CONFIG_DUMMY is not set 550# CONFIG_DUMMY is not set
543# CONFIG_BONDING is not set 551# CONFIG_BONDING is not set
544# CONFIG_MACVLAN is not set 552# CONFIG_MACVLAN is not set
@@ -601,7 +609,6 @@ CONFIG_NETDEV_1000=y
601# CONFIG_DL2K is not set 609# CONFIG_DL2K is not set
602# CONFIG_E1000 is not set 610# CONFIG_E1000 is not set
603# CONFIG_E1000E is not set 611# CONFIG_E1000E is not set
604# CONFIG_E1000E_ENABLED is not set
605# CONFIG_IP1000 is not set 612# CONFIG_IP1000 is not set
606# CONFIG_IGB is not set 613# CONFIG_IGB is not set
607# CONFIG_NS83820 is not set 614# CONFIG_NS83820 is not set
@@ -615,9 +622,9 @@ CONFIG_NETDEV_1000=y
615# CONFIG_TIGON3 is not set 622# CONFIG_TIGON3 is not set
616# CONFIG_BNX2 is not set 623# CONFIG_BNX2 is not set
617CONFIG_GIANFAR=y 624CONFIG_GIANFAR=y
618CONFIG_GFAR_NAPI=y
619# CONFIG_QLA3XXX is not set 625# CONFIG_QLA3XXX is not set
620# CONFIG_ATL1 is not set 626# CONFIG_ATL1 is not set
627# CONFIG_ATL1E is not set
621CONFIG_NETDEV_10000=y 628CONFIG_NETDEV_10000=y
622# CONFIG_CHELSIO_T1 is not set 629# CONFIG_CHELSIO_T1 is not set
623# CONFIG_CHELSIO_T3 is not set 630# CONFIG_CHELSIO_T3 is not set
@@ -732,42 +739,66 @@ CONFIG_DEVPORT=y
732CONFIG_I2C=y 739CONFIG_I2C=y
733CONFIG_I2C_BOARDINFO=y 740CONFIG_I2C_BOARDINFO=y
734CONFIG_I2C_CHARDEV=y 741CONFIG_I2C_CHARDEV=y
742CONFIG_I2C_HELPER_AUTO=y
735 743
736# 744#
737# I2C Hardware Bus support 745# I2C Hardware Bus support
738# 746#
747
748#
749# PC SMBus host controller drivers
750#
739# CONFIG_I2C_ALI1535 is not set 751# CONFIG_I2C_ALI1535 is not set
740# CONFIG_I2C_ALI1563 is not set 752# CONFIG_I2C_ALI1563 is not set
741# CONFIG_I2C_ALI15X3 is not set 753# CONFIG_I2C_ALI15X3 is not set
742# CONFIG_I2C_AMD756 is not set 754# CONFIG_I2C_AMD756 is not set
743# CONFIG_I2C_AMD8111 is not set 755# CONFIG_I2C_AMD8111 is not set
744# CONFIG_I2C_I801 is not set 756# CONFIG_I2C_I801 is not set
745# CONFIG_I2C_I810 is not set 757# CONFIG_I2C_ISCH is not set
746# CONFIG_I2C_PIIX4 is not set 758# CONFIG_I2C_PIIX4 is not set
747CONFIG_I2C_MPC=y
748# CONFIG_I2C_NFORCE2 is not set 759# CONFIG_I2C_NFORCE2 is not set
749# CONFIG_I2C_OCORES is not set
750# CONFIG_I2C_PARPORT_LIGHT is not set
751# CONFIG_I2C_PROSAVAGE is not set
752# CONFIG_I2C_SAVAGE4 is not set
753# CONFIG_I2C_SIMTEC is not set
754# CONFIG_I2C_SIS5595 is not set 760# CONFIG_I2C_SIS5595 is not set
755# CONFIG_I2C_SIS630 is not set 761# CONFIG_I2C_SIS630 is not set
756# CONFIG_I2C_SIS96X is not set 762# CONFIG_I2C_SIS96X is not set
757# CONFIG_I2C_TAOS_EVM is not set
758# CONFIG_I2C_VIA is not set 763# CONFIG_I2C_VIA is not set
759# CONFIG_I2C_VIAPRO is not set 764# CONFIG_I2C_VIAPRO is not set
765
766#
767# I2C system bus drivers (mostly embedded / system-on-chip)
768#
769# CONFIG_I2C_CPM is not set
770# CONFIG_I2C_GPIO is not set
771CONFIG_I2C_MPC=y
772# CONFIG_I2C_OCORES is not set
773# CONFIG_I2C_SIMTEC is not set
774
775#
776# External I2C/SMBus adapter drivers
777#
778# CONFIG_I2C_PARPORT_LIGHT is not set
779# CONFIG_I2C_TAOS_EVM is not set
780
781#
782# Graphics adapter I2C/DDC channel drivers
783#
760# CONFIG_I2C_VOODOO3 is not set 784# CONFIG_I2C_VOODOO3 is not set
785
786#
787# Other I2C/SMBus bus drivers
788#
761# CONFIG_I2C_PCA_PLATFORM is not set 789# CONFIG_I2C_PCA_PLATFORM is not set
762 790
763# 791#
764# Miscellaneous I2C Chip support 792# Miscellaneous I2C Chip support
765# 793#
766# CONFIG_DS1682 is not set 794# CONFIG_DS1682 is not set
795# CONFIG_AT24 is not set
767# CONFIG_SENSORS_EEPROM is not set 796# CONFIG_SENSORS_EEPROM is not set
768# CONFIG_SENSORS_PCF8574 is not set 797# CONFIG_SENSORS_PCF8574 is not set
769# CONFIG_PCF8575 is not set 798# CONFIG_PCF8575 is not set
799# CONFIG_SENSORS_PCA9539 is not set
770# CONFIG_SENSORS_PCF8591 is not set 800# CONFIG_SENSORS_PCF8591 is not set
801# CONFIG_TPS65010 is not set
771# CONFIG_SENSORS_MAX6875 is not set 802# CONFIG_SENSORS_MAX6875 is not set
772# CONFIG_SENSORS_TSL2550 is not set 803# CONFIG_SENSORS_TSL2550 is not set
773# CONFIG_I2C_DEBUG_CORE is not set 804# CONFIG_I2C_DEBUG_CORE is not set
@@ -775,10 +806,31 @@ CONFIG_I2C_MPC=y
775# CONFIG_I2C_DEBUG_BUS is not set 806# CONFIG_I2C_DEBUG_BUS is not set
776# CONFIG_I2C_DEBUG_CHIP is not set 807# CONFIG_I2C_DEBUG_CHIP is not set
777# CONFIG_SPI is not set 808# CONFIG_SPI is not set
809CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
810CONFIG_ARCH_REQUIRE_GPIOLIB=y
811CONFIG_GPIOLIB=y
812# CONFIG_GPIO_SYSFS is not set
813
814#
815# I2C GPIO expanders:
816#
817# CONFIG_GPIO_MAX732X is not set
818# CONFIG_GPIO_PCA953X is not set
819# CONFIG_GPIO_PCF857X is not set
820
821#
822# PCI GPIO expanders:
823#
824# CONFIG_GPIO_BT8XX is not set
825
826#
827# SPI GPIO expanders:
828#
778# CONFIG_W1 is not set 829# CONFIG_W1 is not set
779# CONFIG_POWER_SUPPLY is not set 830# CONFIG_POWER_SUPPLY is not set
780CONFIG_HWMON=y 831CONFIG_HWMON=y
781# CONFIG_HWMON_VID is not set 832# CONFIG_HWMON_VID is not set
833# CONFIG_SENSORS_AD7414 is not set
782# CONFIG_SENSORS_AD7418 is not set 834# CONFIG_SENSORS_AD7418 is not set
783# CONFIG_SENSORS_ADM1021 is not set 835# CONFIG_SENSORS_ADM1021 is not set
784# CONFIG_SENSORS_ADM1025 is not set 836# CONFIG_SENSORS_ADM1025 is not set
@@ -832,6 +884,7 @@ CONFIG_SENSORS_LM75=y
832# CONFIG_SENSORS_W83627EHF is not set 884# CONFIG_SENSORS_W83627EHF is not set
833CONFIG_HWMON_DEBUG_CHIP=y 885CONFIG_HWMON_DEBUG_CHIP=y
834# CONFIG_THERMAL is not set 886# CONFIG_THERMAL is not set
887# CONFIG_THERMAL_HWMON is not set
835# CONFIG_WATCHDOG is not set 888# CONFIG_WATCHDOG is not set
836 889
837# 890#
@@ -843,8 +896,10 @@ CONFIG_SSB_POSSIBLE=y
843# 896#
844# Multifunction device drivers 897# Multifunction device drivers
845# 898#
899# CONFIG_MFD_CORE is not set
846# CONFIG_MFD_SM501 is not set 900# CONFIG_MFD_SM501 is not set
847# CONFIG_HTC_PASIC3 is not set 901# CONFIG_HTC_PASIC3 is not set
902# CONFIG_MFD_TMIO is not set
848 903
849# 904#
850# Multimedia devices 905# Multimedia devices
@@ -876,10 +931,6 @@ CONFIG_DAB=y
876# Display device support 931# Display device support
877# 932#
878# CONFIG_DISPLAY_SUPPORT is not set 933# CONFIG_DISPLAY_SUPPORT is not set
879
880#
881# Sound
882#
883# CONFIG_SOUND is not set 934# CONFIG_SOUND is not set
884CONFIG_HID_SUPPORT=y 935CONFIG_HID_SUPPORT=y
885CONFIG_HID=y 936CONFIG_HID=y
@@ -894,6 +945,10 @@ CONFIG_USB_ARCH_HAS_EHCI=y
894# CONFIG_USB_OTG_BLACKLIST_HUB is not set 945# CONFIG_USB_OTG_BLACKLIST_HUB is not set
895 946
896# 947#
948# Enable Host or Gadget support to see Inventra options
949#
950
951#
897# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 952# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
898# 953#
899# CONFIG_USB_GADGET is not set 954# CONFIG_USB_GADGET is not set
@@ -982,6 +1037,7 @@ CONFIG_JFFS2_RTIME=y
982CONFIG_CRAMFS=y 1037CONFIG_CRAMFS=y
983# CONFIG_VXFS_FS is not set 1038# CONFIG_VXFS_FS is not set
984# CONFIG_MINIX_FS is not set 1039# CONFIG_MINIX_FS is not set
1040# CONFIG_OMFS_FS is not set
985# CONFIG_HPFS_FS is not set 1041# CONFIG_HPFS_FS is not set
986# CONFIG_QNX4FS_FS is not set 1042# CONFIG_QNX4FS_FS is not set
987# CONFIG_ROMFS_FS is not set 1043# CONFIG_ROMFS_FS is not set
@@ -991,12 +1047,11 @@ CONFIG_NETWORK_FILESYSTEMS=y
991CONFIG_NFS_FS=y 1047CONFIG_NFS_FS=y
992# CONFIG_NFS_V3 is not set 1048# CONFIG_NFS_V3 is not set
993# CONFIG_NFS_V4 is not set 1049# CONFIG_NFS_V4 is not set
994# CONFIG_NFSD is not set
995CONFIG_ROOT_NFS=y 1050CONFIG_ROOT_NFS=y
1051# CONFIG_NFSD is not set
996CONFIG_LOCKD=y 1052CONFIG_LOCKD=y
997CONFIG_NFS_COMMON=y 1053CONFIG_NFS_COMMON=y
998CONFIG_SUNRPC=y 1054CONFIG_SUNRPC=y
999# CONFIG_SUNRPC_BIND34 is not set
1000# CONFIG_RPCSEC_GSS_KRB5 is not set 1055# CONFIG_RPCSEC_GSS_KRB5 is not set
1001# CONFIG_RPCSEC_GSS_SPKM3 is not set 1056# CONFIG_RPCSEC_GSS_SPKM3 is not set
1002# CONFIG_SMB_FS is not set 1057# CONFIG_SMB_FS is not set
@@ -1032,6 +1087,7 @@ CONFIG_BITREVERSE=y
1032# CONFIG_GENERIC_FIND_FIRST_BIT is not set 1087# CONFIG_GENERIC_FIND_FIRST_BIT is not set
1033# CONFIG_CRC_CCITT is not set 1088# CONFIG_CRC_CCITT is not set
1034# CONFIG_CRC16 is not set 1089# CONFIG_CRC16 is not set
1090# CONFIG_CRC_T10DIF is not set
1035# CONFIG_CRC_ITU_T is not set 1091# CONFIG_CRC_ITU_T is not set
1036CONFIG_CRC32=y 1092CONFIG_CRC32=y
1037# CONFIG_CRC7 is not set 1093# CONFIG_CRC7 is not set
@@ -1059,8 +1115,16 @@ CONFIG_FRAME_WARN=1024
1059# CONFIG_SLUB_DEBUG_ON is not set 1115# CONFIG_SLUB_DEBUG_ON is not set
1060# CONFIG_SLUB_STATS is not set 1116# CONFIG_SLUB_STATS is not set
1061# CONFIG_DEBUG_BUGVERBOSE is not set 1117# CONFIG_DEBUG_BUGVERBOSE is not set
1118# CONFIG_DEBUG_MEMORY_INIT is not set
1119# CONFIG_LATENCYTOP is not set
1120CONFIG_SYSCTL_SYSCALL_CHECK=y
1121CONFIG_HAVE_FTRACE=y
1122CONFIG_HAVE_DYNAMIC_FTRACE=y
1123# CONFIG_FTRACE is not set
1124# CONFIG_SCHED_TRACER is not set
1125# CONFIG_CONTEXT_SWITCH_TRACER is not set
1062# CONFIG_SAMPLES is not set 1126# CONFIG_SAMPLES is not set
1063# CONFIG_KGDB_CONSOLE is not set 1127CONFIG_HAVE_ARCH_KGDB=y
1064# CONFIG_IRQSTACKS is not set 1128# CONFIG_IRQSTACKS is not set
1065# CONFIG_PPC_EARLY_DEBUG is not set 1129# CONFIG_PPC_EARLY_DEBUG is not set
1066 1130
@@ -1112,6 +1176,10 @@ CONFIG_CRYPTO=y
1112# CONFIG_CRYPTO_MD4 is not set 1176# CONFIG_CRYPTO_MD4 is not set
1113# CONFIG_CRYPTO_MD5 is not set 1177# CONFIG_CRYPTO_MD5 is not set
1114# CONFIG_CRYPTO_MICHAEL_MIC is not set 1178# CONFIG_CRYPTO_MICHAEL_MIC is not set
1179# CONFIG_CRYPTO_RMD128 is not set
1180# CONFIG_CRYPTO_RMD160 is not set
1181# CONFIG_CRYPTO_RMD256 is not set
1182# CONFIG_CRYPTO_RMD320 is not set
1115# CONFIG_CRYPTO_SHA1 is not set 1183# CONFIG_CRYPTO_SHA1 is not set
1116# CONFIG_CRYPTO_SHA256 is not set 1184# CONFIG_CRYPTO_SHA256 is not set
1117# CONFIG_CRYPTO_SHA512 is not set 1185# CONFIG_CRYPTO_SHA512 is not set
@@ -1144,6 +1212,7 @@ CONFIG_CRYPTO=y
1144# CONFIG_CRYPTO_LZO is not set 1212# CONFIG_CRYPTO_LZO is not set
1145CONFIG_CRYPTO_HW=y 1213CONFIG_CRYPTO_HW=y
1146# CONFIG_CRYPTO_DEV_HIFN_795X is not set 1214# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1147# CONFIG_PPC_CLOCK is not set 1215# CONFIG_CRYPTO_DEV_TALITOS is not set
1216CONFIG_PPC_CLOCK=y
1148CONFIG_PPC_LIB_RHEAP=y 1217CONFIG_PPC_LIB_RHEAP=y
1149# CONFIG_VIRTUALIZATION is not set 1218# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/configs/adder875_defconfig b/arch/powerpc/configs/adder875_defconfig
index 6740f2a3aa3d..63cd51fbb4b9 100644
--- a/arch/powerpc/configs/adder875_defconfig
+++ b/arch/powerpc/configs/adder875_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc5 3# Linux kernel version: 2.6.27-rc4
4# Mon Jun 9 08:52:08 2008 4# Thu Aug 21 00:52:00 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -29,6 +29,7 @@ CONFIG_GENERIC_HARDIRQS=y
29# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set 29# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
30CONFIG_IRQ_PER_CPU=y 30CONFIG_IRQ_PER_CPU=y
31CONFIG_STACKTRACE_SUPPORT=y 31CONFIG_STACKTRACE_SUPPORT=y
32CONFIG_HAVE_LATENCYTOP_SUPPORT=y
32CONFIG_LOCKDEP_SUPPORT=y 33CONFIG_LOCKDEP_SUPPORT=y
33CONFIG_RWSEM_XCHGADD_ALGORITHM=y 34CONFIG_RWSEM_XCHGADD_ALGORITHM=y
34CONFIG_ARCH_HAS_ILOG2_U32=y 35CONFIG_ARCH_HAS_ILOG2_U32=y
@@ -109,10 +110,16 @@ CONFIG_SLUB=y
109# CONFIG_PROFILING is not set 110# CONFIG_PROFILING is not set
110# CONFIG_MARKERS is not set 111# CONFIG_MARKERS is not set
111CONFIG_HAVE_OPROFILE=y 112CONFIG_HAVE_OPROFILE=y
113CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
114CONFIG_HAVE_IOREMAP_PROT=y
112CONFIG_HAVE_KPROBES=y 115CONFIG_HAVE_KPROBES=y
113CONFIG_HAVE_KRETPROBES=y 116CONFIG_HAVE_KRETPROBES=y
117CONFIG_HAVE_ARCH_TRACEHOOK=y
114# CONFIG_HAVE_DMA_ATTRS is not set 118# CONFIG_HAVE_DMA_ATTRS is not set
119# CONFIG_USE_GENERIC_SMP_HELPERS is not set
120CONFIG_HAVE_CLK=y
115CONFIG_PROC_PAGE_MONITOR=y 121CONFIG_PROC_PAGE_MONITOR=y
122# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
116CONFIG_SLABINFO=y 123CONFIG_SLABINFO=y
117# CONFIG_TINY_SHMEM is not set 124# CONFIG_TINY_SHMEM is not set
118CONFIG_BASE_SMALL=1 125CONFIG_BASE_SMALL=1
@@ -122,6 +129,7 @@ CONFIG_BLOCK=y
122# CONFIG_BLK_DEV_IO_TRACE is not set 129# CONFIG_BLK_DEV_IO_TRACE is not set
123# CONFIG_LSF is not set 130# CONFIG_LSF is not set
124# CONFIG_BLK_DEV_BSG is not set 131# CONFIG_BLK_DEV_BSG is not set
132# CONFIG_BLK_DEV_INTEGRITY is not set
125 133
126# 134#
127# IO Schedulers 135# IO Schedulers
@@ -140,8 +148,6 @@ CONFIG_CLASSIC_RCU=y
140# 148#
141# Platform support 149# Platform support
142# 150#
143# CONFIG_PPC_MPC512x is not set
144# CONFIG_PPC_MPC5121 is not set
145# CONFIG_PPC_CELL is not set 151# CONFIG_PPC_CELL is not set
146# CONFIG_PPC_CELL_NATIVE is not set 152# CONFIG_PPC_CELL_NATIVE is not set
147CONFIG_CPM1=y 153CONFIG_CPM1=y
@@ -159,6 +165,7 @@ CONFIG_PPC_ADDER875=y
159# Generic MPC8xx Options 165# Generic MPC8xx Options
160# 166#
161CONFIG_8xx_COPYBACK=y 167CONFIG_8xx_COPYBACK=y
168# CONFIG_8xx_GPIO is not set
162# CONFIG_8xx_CPU6 is not set 169# CONFIG_8xx_CPU6 is not set
163CONFIG_8xx_CPU15=y 170CONFIG_8xx_CPU15=y
164CONFIG_NO_UCODE_PATCH=y 171CONFIG_NO_UCODE_PATCH=y
@@ -177,7 +184,6 @@ CONFIG_NO_UCODE_PATCH=y
177# CONFIG_PPC_INDIRECT_IO is not set 184# CONFIG_PPC_INDIRECT_IO is not set
178# CONFIG_GENERIC_IOMAP is not set 185# CONFIG_GENERIC_IOMAP is not set
179# CONFIG_CPU_FREQ is not set 186# CONFIG_CPU_FREQ is not set
180CONFIG_PPC_CPM_NEW_BINDING=y
181# CONFIG_FSL_ULI1575 is not set 187# CONFIG_FSL_ULI1575 is not set
182CONFIG_CPM=y 188CONFIG_CPM=y
183 189
@@ -218,6 +224,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
218# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set 224# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
219CONFIG_PAGEFLAGS_EXTENDED=y 225CONFIG_PAGEFLAGS_EXTENDED=y
220CONFIG_SPLIT_PTLOCK_CPUS=4 226CONFIG_SPLIT_PTLOCK_CPUS=4
227CONFIG_MIGRATION=y
221# CONFIG_RESOURCES_64BIT is not set 228# CONFIG_RESOURCES_64BIT is not set
222CONFIG_ZONE_DMA_FLAG=1 229CONFIG_ZONE_DMA_FLAG=1
223CONFIG_BOUNCE=y 230CONFIG_BOUNCE=y
@@ -225,6 +232,7 @@ CONFIG_VIRT_TO_BUS=y
225CONFIG_FORCE_MAX_ZONEORDER=11 232CONFIG_FORCE_MAX_ZONEORDER=11
226# CONFIG_PROC_DEVICETREE is not set 233# CONFIG_PROC_DEVICETREE is not set
227# CONFIG_CMDLINE_BOOL is not set 234# CONFIG_CMDLINE_BOOL is not set
235CONFIG_EXTRA_TARGETS=""
228# CONFIG_PM is not set 236# CONFIG_PM is not set
229# CONFIG_SECCOMP is not set 237# CONFIG_SECCOMP is not set
230CONFIG_ISA_DMA_API=y 238CONFIG_ISA_DMA_API=y
@@ -257,10 +265,6 @@ CONFIG_PHYSICAL_START=0x00000000
257CONFIG_TASK_SIZE=0x80000000 265CONFIG_TASK_SIZE=0x80000000
258CONFIG_CONSISTENT_START=0xfd000000 266CONFIG_CONSISTENT_START=0xfd000000
259CONFIG_CONSISTENT_SIZE=0x00200000 267CONFIG_CONSISTENT_SIZE=0x00200000
260
261#
262# Networking
263#
264CONFIG_NET=y 268CONFIG_NET=y
265 269
266# 270#
@@ -443,7 +447,6 @@ CONFIG_HAVE_IDE=y
443# CONFIG_MD is not set 447# CONFIG_MD is not set
444# CONFIG_MACINTOSH_DRIVERS is not set 448# CONFIG_MACINTOSH_DRIVERS is not set
445CONFIG_NETDEVICES=y 449CONFIG_NETDEVICES=y
446# CONFIG_NETDEVICES_MULTIQUEUE is not set
447# CONFIG_DUMMY is not set 450# CONFIG_DUMMY is not set
448# CONFIG_BONDING is not set 451# CONFIG_BONDING is not set
449# CONFIG_MACVLAN is not set 452# CONFIG_MACVLAN is not set
@@ -547,6 +550,7 @@ CONFIG_SERIO_I8042=y
547CONFIG_SERIO_SERPORT=y 550CONFIG_SERIO_SERPORT=y
548CONFIG_SERIO_LIBPS2=y 551CONFIG_SERIO_LIBPS2=y
549# CONFIG_SERIO_RAW is not set 552# CONFIG_SERIO_RAW is not set
553# CONFIG_SERIO_XILINX_XPS_PS2 is not set
550# CONFIG_GAMEPORT is not set 554# CONFIG_GAMEPORT is not set
551 555
552# 556#
@@ -587,6 +591,8 @@ CONFIG_GEN_RTC=y
587# CONFIG_TCG_TPM is not set 591# CONFIG_TCG_TPM is not set
588# CONFIG_I2C is not set 592# CONFIG_I2C is not set
589# CONFIG_SPI is not set 593# CONFIG_SPI is not set
594CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
595# CONFIG_GPIOLIB is not set
590# CONFIG_W1 is not set 596# CONFIG_W1 is not set
591# CONFIG_POWER_SUPPLY is not set 597# CONFIG_POWER_SUPPLY is not set
592# CONFIG_HWMON is not set 598# CONFIG_HWMON is not set
@@ -602,8 +608,10 @@ CONFIG_SSB_POSSIBLE=y
602# 608#
603# Multifunction device drivers 609# Multifunction device drivers
604# 610#
611# CONFIG_MFD_CORE is not set
605# CONFIG_MFD_SM501 is not set 612# CONFIG_MFD_SM501 is not set
606# CONFIG_HTC_PASIC3 is not set 613# CONFIG_HTC_PASIC3 is not set
614# CONFIG_MFD_TMIO is not set
607 615
608# 616#
609# Multimedia devices 617# Multimedia devices
@@ -633,10 +641,6 @@ CONFIG_VIDEO_OUTPUT_CONTROL=y
633# Display device support 641# Display device support
634# 642#
635# CONFIG_DISPLAY_SUPPORT is not set 643# CONFIG_DISPLAY_SUPPORT is not set
636
637#
638# Sound
639#
640# CONFIG_SOUND is not set 644# CONFIG_SOUND is not set
641# CONFIG_HID_SUPPORT is not set 645# CONFIG_HID_SUPPORT is not set
642# CONFIG_USB_SUPPORT is not set 646# CONFIG_USB_SUPPORT is not set
@@ -706,6 +710,7 @@ CONFIG_TMPFS=y
706CONFIG_CRAMFS=y 710CONFIG_CRAMFS=y
707# CONFIG_VXFS_FS is not set 711# CONFIG_VXFS_FS is not set
708# CONFIG_MINIX_FS is not set 712# CONFIG_MINIX_FS is not set
713# CONFIG_OMFS_FS is not set
709# CONFIG_HPFS_FS is not set 714# CONFIG_HPFS_FS is not set
710# CONFIG_QNX4FS_FS is not set 715# CONFIG_QNX4FS_FS is not set
711# CONFIG_ROMFS_FS is not set 716# CONFIG_ROMFS_FS is not set
@@ -716,13 +721,12 @@ CONFIG_NFS_FS=y
716CONFIG_NFS_V3=y 721CONFIG_NFS_V3=y
717# CONFIG_NFS_V3_ACL is not set 722# CONFIG_NFS_V3_ACL is not set
718# CONFIG_NFS_V4 is not set 723# CONFIG_NFS_V4 is not set
719# CONFIG_NFSD is not set
720CONFIG_ROOT_NFS=y 724CONFIG_ROOT_NFS=y
725# CONFIG_NFSD is not set
721CONFIG_LOCKD=y 726CONFIG_LOCKD=y
722CONFIG_LOCKD_V4=y 727CONFIG_LOCKD_V4=y
723CONFIG_NFS_COMMON=y 728CONFIG_NFS_COMMON=y
724CONFIG_SUNRPC=y 729CONFIG_SUNRPC=y
725# CONFIG_SUNRPC_BIND34 is not set
726# CONFIG_RPCSEC_GSS_KRB5 is not set 730# CONFIG_RPCSEC_GSS_KRB5 is not set
727# CONFIG_RPCSEC_GSS_SPKM3 is not set 731# CONFIG_RPCSEC_GSS_SPKM3 is not set
728# CONFIG_SMB_FS is not set 732# CONFIG_SMB_FS is not set
@@ -761,6 +765,7 @@ CONFIG_MSDOS_PARTITION=y
761# CONFIG_GENERIC_FIND_FIRST_BIT is not set 765# CONFIG_GENERIC_FIND_FIRST_BIT is not set
762# CONFIG_CRC_CCITT is not set 766# CONFIG_CRC_CCITT is not set
763# CONFIG_CRC16 is not set 767# CONFIG_CRC16 is not set
768# CONFIG_CRC_T10DIF is not set
764# CONFIG_CRC_ITU_T is not set 769# CONFIG_CRC_ITU_T is not set
765# CONFIG_CRC32 is not set 770# CONFIG_CRC32 is not set
766# CONFIG_CRC7 is not set 771# CONFIG_CRC7 is not set
@@ -785,6 +790,8 @@ CONFIG_DEBUG_FS=y
785CONFIG_DEBUG_KERNEL=y 790CONFIG_DEBUG_KERNEL=y
786# CONFIG_DEBUG_SHIRQ is not set 791# CONFIG_DEBUG_SHIRQ is not set
787CONFIG_DETECT_SOFTLOCKUP=y 792CONFIG_DETECT_SOFTLOCKUP=y
793# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
794CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
788CONFIG_SCHED_DEBUG=y 795CONFIG_SCHED_DEBUG=y
789# CONFIG_SCHEDSTATS is not set 796# CONFIG_SCHEDSTATS is not set
790# CONFIG_TIMER_STATS is not set 797# CONFIG_TIMER_STATS is not set
@@ -800,16 +807,28 @@ CONFIG_DEBUG_BUGVERBOSE=y
800CONFIG_DEBUG_INFO=y 807CONFIG_DEBUG_INFO=y
801# CONFIG_DEBUG_VM is not set 808# CONFIG_DEBUG_VM is not set
802# CONFIG_DEBUG_WRITECOUNT is not set 809# CONFIG_DEBUG_WRITECOUNT is not set
810# CONFIG_DEBUG_MEMORY_INIT is not set
803# CONFIG_DEBUG_LIST is not set 811# CONFIG_DEBUG_LIST is not set
804# CONFIG_DEBUG_SG is not set 812# CONFIG_DEBUG_SG is not set
805# CONFIG_BOOT_PRINTK_DELAY is not set 813# CONFIG_BOOT_PRINTK_DELAY is not set
814# CONFIG_RCU_TORTURE_TEST is not set
806# CONFIG_BACKTRACE_SELF_TEST is not set 815# CONFIG_BACKTRACE_SELF_TEST is not set
807# CONFIG_FAULT_INJECTION is not set 816# CONFIG_FAULT_INJECTION is not set
817# CONFIG_LATENCYTOP is not set
818CONFIG_HAVE_FTRACE=y
819CONFIG_HAVE_DYNAMIC_FTRACE=y
820# CONFIG_FTRACE is not set
821# CONFIG_SCHED_TRACER is not set
822# CONFIG_CONTEXT_SWITCH_TRACER is not set
808# CONFIG_SAMPLES is not set 823# CONFIG_SAMPLES is not set
824CONFIG_HAVE_ARCH_KGDB=y
825# CONFIG_KGDB is not set
809# CONFIG_DEBUG_STACKOVERFLOW is not set 826# CONFIG_DEBUG_STACKOVERFLOW is not set
810# CONFIG_DEBUG_STACK_USAGE is not set 827# CONFIG_DEBUG_STACK_USAGE is not set
811# CONFIG_DEBUG_PAGEALLOC is not set 828# CONFIG_DEBUG_PAGEALLOC is not set
812# CONFIG_DEBUGGER is not set 829# CONFIG_CODE_PATCHING_SELFTEST is not set
830# CONFIG_FTR_FIXUP_SELFTEST is not set
831# CONFIG_XMON is not set
813# CONFIG_IRQSTACKS is not set 832# CONFIG_IRQSTACKS is not set
814# CONFIG_VIRQ_DEBUG is not set 833# CONFIG_VIRQ_DEBUG is not set
815# CONFIG_BDI_SWITCH is not set 834# CONFIG_BDI_SWITCH is not set
@@ -822,6 +841,6 @@ CONFIG_DEBUG_INFO=y
822# CONFIG_SECURITY is not set 841# CONFIG_SECURITY is not set
823# CONFIG_SECURITY_FILE_CAPABILITIES is not set 842# CONFIG_SECURITY_FILE_CAPABILITIES is not set
824# CONFIG_CRYPTO is not set 843# CONFIG_CRYPTO is not set
825# CONFIG_PPC_CLOCK is not set 844CONFIG_PPC_CLOCK=y
826CONFIG_PPC_LIB_RHEAP=y 845CONFIG_PPC_LIB_RHEAP=y
827# CONFIG_VIRTUALIZATION is not set 846# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/configs/c2k_defconfig b/arch/powerpc/configs/c2k_defconfig
index dc599c7e97d5..c16521ffb477 100644
--- a/arch/powerpc/configs/c2k_defconfig
+++ b/arch/powerpc/configs/c2k_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc2 3# Linux kernel version: 2.6.27-rc4
4# Thu May 15 11:00:14 2008 4# Thu Aug 21 00:52:02 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -34,6 +34,7 @@ CONFIG_GENERIC_HARDIRQS=y
34# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set 34# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
35CONFIG_IRQ_PER_CPU=y 35CONFIG_IRQ_PER_CPU=y
36CONFIG_STACKTRACE_SUPPORT=y 36CONFIG_STACKTRACE_SUPPORT=y
37CONFIG_HAVE_LATENCYTOP_SUPPORT=y
37CONFIG_LOCKDEP_SUPPORT=y 38CONFIG_LOCKDEP_SUPPORT=y
38CONFIG_RWSEM_XCHGADD_ALGORITHM=y 39CONFIG_RWSEM_XCHGADD_ALGORITHM=y
39CONFIG_ARCH_HAS_ILOG2_U32=y 40CONFIG_ARCH_HAS_ILOG2_U32=y
@@ -97,7 +98,6 @@ CONFIG_CC_OPTIMIZE_FOR_SIZE=y
97CONFIG_SYSCTL=y 98CONFIG_SYSCTL=y
98# CONFIG_EMBEDDED is not set 99# CONFIG_EMBEDDED is not set
99CONFIG_SYSCTL_SYSCALL=y 100CONFIG_SYSCTL_SYSCALL=y
100CONFIG_SYSCTL_SYSCALL_CHECK=y
101CONFIG_KALLSYMS=y 101CONFIG_KALLSYMS=y
102# CONFIG_KALLSYMS_ALL is not set 102# CONFIG_KALLSYMS_ALL is not set
103CONFIG_KALLSYMS_EXTRA_PASS=y 103CONFIG_KALLSYMS_EXTRA_PASS=y
@@ -124,11 +124,17 @@ CONFIG_PROFILING=y
124CONFIG_OPROFILE=m 124CONFIG_OPROFILE=m
125CONFIG_HAVE_OPROFILE=y 125CONFIG_HAVE_OPROFILE=y
126CONFIG_KPROBES=y 126CONFIG_KPROBES=y
127CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
127CONFIG_KRETPROBES=y 128CONFIG_KRETPROBES=y
129CONFIG_HAVE_IOREMAP_PROT=y
128CONFIG_HAVE_KPROBES=y 130CONFIG_HAVE_KPROBES=y
129CONFIG_HAVE_KRETPROBES=y 131CONFIG_HAVE_KRETPROBES=y
132CONFIG_HAVE_ARCH_TRACEHOOK=y
130# CONFIG_HAVE_DMA_ATTRS is not set 133# CONFIG_HAVE_DMA_ATTRS is not set
134# CONFIG_USE_GENERIC_SMP_HELPERS is not set
135# CONFIG_HAVE_CLK is not set
131CONFIG_PROC_PAGE_MONITOR=y 136CONFIG_PROC_PAGE_MONITOR=y
137# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
132CONFIG_SLABINFO=y 138CONFIG_SLABINFO=y
133CONFIG_RT_MUTEXES=y 139CONFIG_RT_MUTEXES=y
134# CONFIG_TINY_SHMEM is not set 140# CONFIG_TINY_SHMEM is not set
@@ -145,6 +151,7 @@ CONFIG_LBD=y
145# CONFIG_BLK_DEV_IO_TRACE is not set 151# CONFIG_BLK_DEV_IO_TRACE is not set
146# CONFIG_LSF is not set 152# CONFIG_LSF is not set
147# CONFIG_BLK_DEV_BSG is not set 153# CONFIG_BLK_DEV_BSG is not set
154# CONFIG_BLK_DEV_INTEGRITY is not set
148 155
149# 156#
150# IO Schedulers 157# IO Schedulers
@@ -164,19 +171,18 @@ CONFIG_CLASSIC_RCU=y
164# Platform support 171# Platform support
165# 172#
166CONFIG_PPC_MULTIPLATFORM=y 173CONFIG_PPC_MULTIPLATFORM=y
167# CONFIG_PPC_82xx is not set
168# CONFIG_PPC_83xx is not set
169# CONFIG_PPC_86xx is not set
170CONFIG_CLASSIC32=y 174CONFIG_CLASSIC32=y
171# CONFIG_PPC_CHRP is not set 175# CONFIG_PPC_CHRP is not set
172# CONFIG_PPC_MPC512x is not set
173# CONFIG_PPC_MPC5121 is not set
174# CONFIG_MPC5121_ADS is not set 176# CONFIG_MPC5121_ADS is not set
177# CONFIG_MPC5121_GENERIC is not set
175# CONFIG_PPC_MPC52xx is not set 178# CONFIG_PPC_MPC52xx is not set
176# CONFIG_PPC_PMAC is not set 179# CONFIG_PPC_PMAC is not set
177# CONFIG_PPC_CELL is not set 180# CONFIG_PPC_CELL is not set
178# CONFIG_PPC_CELL_NATIVE is not set 181# CONFIG_PPC_CELL_NATIVE is not set
182# CONFIG_PPC_82xx is not set
179# CONFIG_PQ2ADS is not set 183# CONFIG_PQ2ADS is not set
184# CONFIG_PPC_83xx is not set
185# CONFIG_PPC_86xx is not set
180CONFIG_EMBEDDED6xx=y 186CONFIG_EMBEDDED6xx=y
181# CONFIG_LINKSTATION is not set 187# CONFIG_LINKSTATION is not set
182# CONFIG_STORCENTER is not set 188# CONFIG_STORCENTER is not set
@@ -253,6 +259,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
253# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set 259# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
254CONFIG_PAGEFLAGS_EXTENDED=y 260CONFIG_PAGEFLAGS_EXTENDED=y
255CONFIG_SPLIT_PTLOCK_CPUS=4 261CONFIG_SPLIT_PTLOCK_CPUS=4
262CONFIG_MIGRATION=y
256# CONFIG_RESOURCES_64BIT is not set 263# CONFIG_RESOURCES_64BIT is not set
257CONFIG_ZONE_DMA_FLAG=1 264CONFIG_ZONE_DMA_FLAG=1
258CONFIG_BOUNCE=y 265CONFIG_BOUNCE=y
@@ -260,6 +267,7 @@ CONFIG_VIRT_TO_BUS=y
260CONFIG_FORCE_MAX_ZONEORDER=11 267CONFIG_FORCE_MAX_ZONEORDER=11
261# CONFIG_PROC_DEVICETREE is not set 268# CONFIG_PROC_DEVICETREE is not set
262# CONFIG_CMDLINE_BOOL is not set 269# CONFIG_CMDLINE_BOOL is not set
270CONFIG_EXTRA_TARGETS=""
263CONFIG_PM=y 271CONFIG_PM=y
264# CONFIG_PM_DEBUG is not set 272# CONFIG_PM_DEBUG is not set
265CONFIG_SECCOMP=y 273CONFIG_SECCOMP=y
@@ -301,10 +309,6 @@ CONFIG_PHYSICAL_START=0x00000000
301CONFIG_TASK_SIZE=0xc0000000 309CONFIG_TASK_SIZE=0xc0000000
302CONFIG_CONSISTENT_START=0xff100000 310CONFIG_CONSISTENT_START=0xff100000
303CONFIG_CONSISTENT_SIZE=0x00200000 311CONFIG_CONSISTENT_SIZE=0x00200000
304
305#
306# Networking
307#
308CONFIG_NET=y 312CONFIG_NET=y
309 313
310# 314#
@@ -318,6 +322,7 @@ CONFIG_XFRM_USER=y
318# CONFIG_XFRM_SUB_POLICY is not set 322# CONFIG_XFRM_SUB_POLICY is not set
319# CONFIG_XFRM_MIGRATE is not set 323# CONFIG_XFRM_MIGRATE is not set
320# CONFIG_XFRM_STATISTICS is not set 324# CONFIG_XFRM_STATISTICS is not set
325CONFIG_XFRM_IPCOMP=m
321CONFIG_NET_KEY=m 326CONFIG_NET_KEY=m
322# CONFIG_NET_KEY_MIGRATE is not set 327# CONFIG_NET_KEY_MIGRATE is not set
323CONFIG_INET=y 328CONFIG_INET=y
@@ -349,7 +354,7 @@ CONFIG_INET_TUNNEL=m
349CONFIG_INET_XFRM_MODE_TRANSPORT=y 354CONFIG_INET_XFRM_MODE_TRANSPORT=y
350CONFIG_INET_XFRM_MODE_TUNNEL=y 355CONFIG_INET_XFRM_MODE_TUNNEL=y
351CONFIG_INET_XFRM_MODE_BEET=y 356CONFIG_INET_XFRM_MODE_BEET=y
352# CONFIG_INET_LRO is not set 357CONFIG_INET_LRO=m
353CONFIG_INET_DIAG=y 358CONFIG_INET_DIAG=y
354CONFIG_INET_TCP_DIAG=y 359CONFIG_INET_TCP_DIAG=y
355# CONFIG_TCP_CONG_ADVANCED is not set 360# CONFIG_TCP_CONG_ADVANCED is not set
@@ -472,6 +477,7 @@ CONFIG_IP_NF_MANGLE=m
472CONFIG_IP_NF_TARGET_ECN=m 477CONFIG_IP_NF_TARGET_ECN=m
473# CONFIG_IP_NF_TARGET_TTL is not set 478# CONFIG_IP_NF_TARGET_TTL is not set
474CONFIG_IP_NF_RAW=m 479CONFIG_IP_NF_RAW=m
480# CONFIG_IP_NF_SECURITY is not set
475CONFIG_IP_NF_ARPTABLES=m 481CONFIG_IP_NF_ARPTABLES=m
476CONFIG_IP_NF_ARPFILTER=m 482CONFIG_IP_NF_ARPFILTER=m
477CONFIG_IP_NF_ARP_MANGLE=m 483CONFIG_IP_NF_ARP_MANGLE=m
@@ -495,6 +501,7 @@ CONFIG_IP6_NF_TARGET_LOG=m
495CONFIG_IP6_NF_MANGLE=m 501CONFIG_IP6_NF_MANGLE=m
496# CONFIG_IP6_NF_TARGET_HL is not set 502# CONFIG_IP6_NF_TARGET_HL is not set
497CONFIG_IP6_NF_RAW=m 503CONFIG_IP6_NF_RAW=m
504# CONFIG_IP6_NF_SECURITY is not set
498 505
499# 506#
500# Bridge: Netfilter Configuration 507# Bridge: Netfilter Configuration
@@ -507,6 +514,7 @@ CONFIG_BRIDGE_EBT_802_3=m
507CONFIG_BRIDGE_EBT_AMONG=m 514CONFIG_BRIDGE_EBT_AMONG=m
508CONFIG_BRIDGE_EBT_ARP=m 515CONFIG_BRIDGE_EBT_ARP=m
509CONFIG_BRIDGE_EBT_IP=m 516CONFIG_BRIDGE_EBT_IP=m
517# CONFIG_BRIDGE_EBT_IP6 is not set
510CONFIG_BRIDGE_EBT_LIMIT=m 518CONFIG_BRIDGE_EBT_LIMIT=m
511CONFIG_BRIDGE_EBT_MARK=m 519CONFIG_BRIDGE_EBT_MARK=m
512CONFIG_BRIDGE_EBT_PKTTYPE=m 520CONFIG_BRIDGE_EBT_PKTTYPE=m
@@ -535,8 +543,10 @@ CONFIG_ATM_LANE=m
535# CONFIG_ATM_MPOA is not set 543# CONFIG_ATM_MPOA is not set
536CONFIG_ATM_BR2684=m 544CONFIG_ATM_BR2684=m
537# CONFIG_ATM_BR2684_IPFILTER is not set 545# CONFIG_ATM_BR2684_IPFILTER is not set
546CONFIG_STP=m
538CONFIG_BRIDGE=m 547CONFIG_BRIDGE=m
539CONFIG_VLAN_8021Q=m 548CONFIG_VLAN_8021Q=m
549# CONFIG_VLAN_8021Q_GVRP is not set
540# CONFIG_DECNET is not set 550# CONFIG_DECNET is not set
541CONFIG_LLC=m 551CONFIG_LLC=m
542# CONFIG_LLC2 is not set 552# CONFIG_LLC2 is not set
@@ -556,7 +566,6 @@ CONFIG_NET_SCH_HTB=m
556CONFIG_NET_SCH_HFSC=m 566CONFIG_NET_SCH_HFSC=m
557CONFIG_NET_SCH_ATM=m 567CONFIG_NET_SCH_ATM=m
558CONFIG_NET_SCH_PRIO=m 568CONFIG_NET_SCH_PRIO=m
559# CONFIG_NET_SCH_RR is not set
560CONFIG_NET_SCH_RED=m 569CONFIG_NET_SCH_RED=m
561CONFIG_NET_SCH_SFQ=m 570CONFIG_NET_SCH_SFQ=m
562CONFIG_NET_SCH_TEQL=m 571CONFIG_NET_SCH_TEQL=m
@@ -601,7 +610,6 @@ CONFIG_BT_RFCOMM_TTY=y
601CONFIG_BT_BNEP=m 610CONFIG_BT_BNEP=m
602CONFIG_BT_BNEP_MC_FILTER=y 611CONFIG_BT_BNEP_MC_FILTER=y
603CONFIG_BT_BNEP_PROTO_FILTER=y 612CONFIG_BT_BNEP_PROTO_FILTER=y
604CONFIG_BT_CMTP=m
605CONFIG_BT_HIDP=m 613CONFIG_BT_HIDP=m
606 614
607# 615#
@@ -609,6 +617,7 @@ CONFIG_BT_HIDP=m
609# 617#
610CONFIG_BT_HCIUSB=m 618CONFIG_BT_HCIUSB=m
611CONFIG_BT_HCIUSB_SCO=y 619CONFIG_BT_HCIUSB_SCO=y
620# CONFIG_BT_HCIBTUSB is not set
612CONFIG_BT_HCIUART=m 621CONFIG_BT_HCIUART=m
613CONFIG_BT_HCIUART_H4=y 622CONFIG_BT_HCIUART_H4=y
614CONFIG_BT_HCIUART_BCSP=y 623CONFIG_BT_HCIUART_BCSP=y
@@ -625,6 +634,7 @@ CONFIG_FIB_RULES=y
625# 634#
626# CONFIG_CFG80211 is not set 635# CONFIG_CFG80211 is not set
627CONFIG_WIRELESS_EXT=y 636CONFIG_WIRELESS_EXT=y
637CONFIG_WIRELESS_EXT_SYSFS=y
628# CONFIG_MAC80211 is not set 638# CONFIG_MAC80211 is not set
629CONFIG_IEEE80211=m 639CONFIG_IEEE80211=m
630# CONFIG_IEEE80211_DEBUG is not set 640# CONFIG_IEEE80211_DEBUG is not set
@@ -645,6 +655,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
645CONFIG_STANDALONE=y 655CONFIG_STANDALONE=y
646CONFIG_PREVENT_FIRMWARE_BUILD=y 656CONFIG_PREVENT_FIRMWARE_BUILD=y
647CONFIG_FW_LOADER=y 657CONFIG_FW_LOADER=y
658CONFIG_FIRMWARE_IN_KERNEL=y
659CONFIG_EXTRA_FIRMWARE=""
648# CONFIG_DEBUG_DRIVER is not set 660# CONFIG_DEBUG_DRIVER is not set
649# CONFIG_DEBUG_DEVRES is not set 661# CONFIG_DEBUG_DEVRES is not set
650# CONFIG_SYS_HYPERVISOR is not set 662# CONFIG_SYS_HYPERVISOR is not set
@@ -749,6 +761,7 @@ CONFIG_BLK_DEV_RAM_SIZE=16384
749# CONFIG_BLK_DEV_XIP is not set 761# CONFIG_BLK_DEV_XIP is not set
750# CONFIG_CDROM_PKTCDVD is not set 762# CONFIG_CDROM_PKTCDVD is not set
751# CONFIG_ATA_OVER_ETH is not set 763# CONFIG_ATA_OVER_ETH is not set
764# CONFIG_BLK_DEV_HD is not set
752# CONFIG_MISC_DEVICES is not set 765# CONFIG_MISC_DEVICES is not set
753CONFIG_HAVE_IDE=y 766CONFIG_HAVE_IDE=y
754# CONFIG_IDE is not set 767# CONFIG_IDE is not set
@@ -844,6 +857,7 @@ CONFIG_SCSI_LPFC=m
844# CONFIG_SCSI_NSP32 is not set 857# CONFIG_SCSI_NSP32 is not set
845# CONFIG_SCSI_DEBUG is not set 858# CONFIG_SCSI_DEBUG is not set
846# CONFIG_SCSI_SRP is not set 859# CONFIG_SCSI_SRP is not set
860# CONFIG_SCSI_DH is not set
847# CONFIG_ATA is not set 861# CONFIG_ATA is not set
848# CONFIG_MD is not set 862# CONFIG_MD is not set
849# CONFIG_FUSION is not set 863# CONFIG_FUSION is not set
@@ -851,12 +865,15 @@ CONFIG_SCSI_LPFC=m
851# 865#
852# IEEE 1394 (FireWire) support 866# IEEE 1394 (FireWire) support
853# 867#
868
869#
870# Enable only one of the two stacks, unless you know what you are doing
871#
854# CONFIG_FIREWIRE is not set 872# CONFIG_FIREWIRE is not set
855# CONFIG_IEEE1394 is not set 873# CONFIG_IEEE1394 is not set
856# CONFIG_I2O is not set 874# CONFIG_I2O is not set
857# CONFIG_MACINTOSH_DRIVERS is not set 875# CONFIG_MACINTOSH_DRIVERS is not set
858CONFIG_NETDEVICES=y 876CONFIG_NETDEVICES=y
859# CONFIG_NETDEVICES_MULTIQUEUE is not set
860CONFIG_DUMMY=m 877CONFIG_DUMMY=m
861CONFIG_BONDING=m 878CONFIG_BONDING=m
862# CONFIG_MACVLAN is not set 879# CONFIG_MACVLAN is not set
@@ -900,7 +917,6 @@ CONFIG_NETDEV_1000=y
900# CONFIG_DL2K is not set 917# CONFIG_DL2K is not set
901# CONFIG_E1000 is not set 918# CONFIG_E1000 is not set
902# CONFIG_E1000E is not set 919# CONFIG_E1000E is not set
903# CONFIG_E1000E_ENABLED is not set
904# CONFIG_IP1000 is not set 920# CONFIG_IP1000 is not set
905# CONFIG_IGB is not set 921# CONFIG_IGB is not set
906# CONFIG_NS83820 is not set 922# CONFIG_NS83820 is not set
@@ -916,6 +932,7 @@ CONFIG_NETDEV_1000=y
916CONFIG_MV643XX_ETH=y 932CONFIG_MV643XX_ETH=y
917# CONFIG_QLA3XXX is not set 933# CONFIG_QLA3XXX is not set
918# CONFIG_ATL1 is not set 934# CONFIG_ATL1 is not set
935# CONFIG_ATL1E is not set
919# CONFIG_NETDEV_10000 is not set 936# CONFIG_NETDEV_10000 is not set
920# CONFIG_TR is not set 937# CONFIG_TR is not set
921 938
@@ -940,112 +957,13 @@ CONFIG_MV643XX_ETH=y
940# CONFIG_HIPPI is not set 957# CONFIG_HIPPI is not set
941# CONFIG_PPP is not set 958# CONFIG_PPP is not set
942# CONFIG_SLIP is not set 959# CONFIG_SLIP is not set
943CONFIG_SLHC=m
944# CONFIG_NET_FC is not set 960# CONFIG_NET_FC is not set
945CONFIG_NETCONSOLE=m 961CONFIG_NETCONSOLE=m
946# CONFIG_NETCONSOLE_DYNAMIC is not set 962# CONFIG_NETCONSOLE_DYNAMIC is not set
947CONFIG_NETPOLL=y 963CONFIG_NETPOLL=y
948CONFIG_NETPOLL_TRAP=y 964CONFIG_NETPOLL_TRAP=y
949CONFIG_NET_POLL_CONTROLLER=y 965CONFIG_NET_POLL_CONTROLLER=y
950CONFIG_ISDN=m 966# CONFIG_ISDN is not set
951CONFIG_ISDN_I4L=m
952CONFIG_ISDN_PPP=y
953CONFIG_ISDN_PPP_VJ=y
954CONFIG_ISDN_MPP=y
955CONFIG_IPPP_FILTER=y
956# CONFIG_ISDN_PPP_BSDCOMP is not set
957CONFIG_ISDN_AUDIO=y
958CONFIG_ISDN_TTY_FAX=y
959
960#
961# ISDN feature submodules
962#
963CONFIG_ISDN_DRV_LOOP=m
964# CONFIG_ISDN_DIVERSION is not set
965
966#
967# ISDN4Linux hardware drivers
968#
969
970#
971# Passive cards
972#
973CONFIG_ISDN_DRV_HISAX=m
974
975#
976# D-channel protocol features
977#
978CONFIG_HISAX_EURO=y
979CONFIG_DE_AOC=y
980CONFIG_HISAX_NO_SENDCOMPLETE=y
981CONFIG_HISAX_NO_LLC=y
982CONFIG_HISAX_NO_KEYPAD=y
983CONFIG_HISAX_1TR6=y
984CONFIG_HISAX_NI1=y
985CONFIG_HISAX_MAX_CARDS=8
986
987#
988# HiSax supported cards
989#
990CONFIG_HISAX_16_3=y
991CONFIG_HISAX_S0BOX=y
992CONFIG_HISAX_FRITZPCI=y
993CONFIG_HISAX_AVM_A1_PCMCIA=y
994CONFIG_HISAX_ELSA=y
995CONFIG_HISAX_DIEHLDIVA=y
996CONFIG_HISAX_SEDLBAUER=y
997CONFIG_HISAX_NICCY=y
998CONFIG_HISAX_BKM_A4T=y
999CONFIG_HISAX_SCT_QUADRO=y
1000CONFIG_HISAX_GAZEL=y
1001CONFIG_HISAX_W6692=y
1002CONFIG_HISAX_HFC_SX=y
1003# CONFIG_HISAX_DEBUG is not set
1004
1005#
1006# HiSax PCMCIA card service modules
1007#
1008
1009#
1010# HiSax sub driver modules
1011#
1012CONFIG_HISAX_ST5481=m
1013CONFIG_HISAX_HFCUSB=m
1014# CONFIG_HISAX_HFC4S8S is not set
1015CONFIG_HISAX_FRITZ_PCIPNP=m
1016CONFIG_HISAX_HDLC=y
1017
1018#
1019# Active cards
1020#
1021CONFIG_HYSDN=m
1022CONFIG_HYSDN_CAPI=y
1023# CONFIG_ISDN_DRV_GIGASET is not set
1024CONFIG_ISDN_CAPI=m
1025CONFIG_ISDN_DRV_AVMB1_VERBOSE_REASON=y
1026CONFIG_CAPI_TRACE=y
1027CONFIG_ISDN_CAPI_MIDDLEWARE=y
1028CONFIG_ISDN_CAPI_CAPI20=m
1029CONFIG_ISDN_CAPI_CAPIFS_BOOL=y
1030CONFIG_ISDN_CAPI_CAPIFS=m
1031CONFIG_ISDN_CAPI_CAPIDRV=m
1032
1033#
1034# CAPI hardware drivers
1035#
1036CONFIG_CAPI_AVM=y
1037CONFIG_ISDN_DRV_AVMB1_B1PCI=m
1038CONFIG_ISDN_DRV_AVMB1_B1PCIV4=y
1039CONFIG_ISDN_DRV_AVMB1_B1PCMCIA=m
1040CONFIG_ISDN_DRV_AVMB1_T1PCI=m
1041CONFIG_ISDN_DRV_AVMB1_C4=m
1042CONFIG_CAPI_EICON=y
1043CONFIG_ISDN_DIVAS=m
1044CONFIG_ISDN_DIVAS_BRIPCI=y
1045CONFIG_ISDN_DIVAS_PRIPCI=y
1046CONFIG_ISDN_DIVAS_DIVACAPI=m
1047CONFIG_ISDN_DIVAS_USERIDI=m
1048CONFIG_ISDN_DIVAS_MAINT=m
1049# CONFIG_PHONE is not set 967# CONFIG_PHONE is not set
1050 968
1051# 969#
@@ -1092,6 +1010,7 @@ CONFIG_INPUT_UINPUT=m
1092# Character devices 1010# Character devices
1093# 1011#
1094CONFIG_VT=y 1012CONFIG_VT=y
1013CONFIG_CONSOLE_TRANSLATIONS=y
1095CONFIG_VT_CONSOLE=y 1014CONFIG_VT_CONSOLE=y
1096CONFIG_HW_CONSOLE=y 1015CONFIG_HW_CONSOLE=y
1097# CONFIG_VT_HW_CONSOLE_BINDING is not set 1016# CONFIG_VT_HW_CONSOLE_BINDING is not set
@@ -1145,44 +1064,65 @@ CONFIG_DEVPORT=y
1145CONFIG_I2C=m 1064CONFIG_I2C=m
1146CONFIG_I2C_BOARDINFO=y 1065CONFIG_I2C_BOARDINFO=y
1147CONFIG_I2C_CHARDEV=m 1066CONFIG_I2C_CHARDEV=m
1067CONFIG_I2C_HELPER_AUTO=y
1148 1068
1149# 1069#
1150# I2C Hardware Bus support 1070# I2C Hardware Bus support
1151# 1071#
1072
1073#
1074# PC SMBus host controller drivers
1075#
1152# CONFIG_I2C_ALI1535 is not set 1076# CONFIG_I2C_ALI1535 is not set
1153# CONFIG_I2C_ALI1563 is not set 1077# CONFIG_I2C_ALI1563 is not set
1154# CONFIG_I2C_ALI15X3 is not set 1078# CONFIG_I2C_ALI15X3 is not set
1155# CONFIG_I2C_AMD756 is not set 1079# CONFIG_I2C_AMD756 is not set
1156# CONFIG_I2C_AMD8111 is not set 1080# CONFIG_I2C_AMD8111 is not set
1157# CONFIG_I2C_I801 is not set 1081# CONFIG_I2C_I801 is not set
1158# CONFIG_I2C_I810 is not set 1082# CONFIG_I2C_ISCH is not set
1159# CONFIG_I2C_PIIX4 is not set 1083# CONFIG_I2C_PIIX4 is not set
1160# CONFIG_I2C_MPC is not set
1161# CONFIG_I2C_NFORCE2 is not set 1084# CONFIG_I2C_NFORCE2 is not set
1162# CONFIG_I2C_OCORES is not set
1163# CONFIG_I2C_PARPORT_LIGHT is not set
1164# CONFIG_I2C_PROSAVAGE is not set
1165# CONFIG_I2C_SAVAGE4 is not set
1166# CONFIG_I2C_SIMTEC is not set
1167# CONFIG_I2C_SIS5595 is not set 1085# CONFIG_I2C_SIS5595 is not set
1168# CONFIG_I2C_SIS630 is not set 1086# CONFIG_I2C_SIS630 is not set
1169# CONFIG_I2C_SIS96X is not set 1087# CONFIG_I2C_SIS96X is not set
1170# CONFIG_I2C_TAOS_EVM is not set
1171# CONFIG_I2C_STUB is not set
1172# CONFIG_I2C_TINY_USB is not set
1173# CONFIG_I2C_VIA is not set 1088# CONFIG_I2C_VIA is not set
1174# CONFIG_I2C_VIAPRO is not set 1089# CONFIG_I2C_VIAPRO is not set
1090
1091#
1092# I2C system bus drivers (mostly embedded / system-on-chip)
1093#
1094# CONFIG_I2C_MPC is not set
1095CONFIG_I2C_MV64XXX=m
1096# CONFIG_I2C_OCORES is not set
1097# CONFIG_I2C_SIMTEC is not set
1098
1099#
1100# External I2C/SMBus adapter drivers
1101#
1102# CONFIG_I2C_PARPORT_LIGHT is not set
1103# CONFIG_I2C_TAOS_EVM is not set
1104# CONFIG_I2C_TINY_USB is not set
1105
1106#
1107# Graphics adapter I2C/DDC channel drivers
1108#
1175# CONFIG_I2C_VOODOO3 is not set 1109# CONFIG_I2C_VOODOO3 is not set
1110
1111#
1112# Other I2C/SMBus bus drivers
1113#
1176# CONFIG_I2C_PCA_PLATFORM is not set 1114# CONFIG_I2C_PCA_PLATFORM is not set
1177CONFIG_I2C_MV64XXX=m 1115# CONFIG_I2C_STUB is not set
1178 1116
1179# 1117#
1180# Miscellaneous I2C Chip support 1118# Miscellaneous I2C Chip support
1181# 1119#
1182# CONFIG_DS1682 is not set 1120# CONFIG_DS1682 is not set
1121# CONFIG_AT24 is not set
1183CONFIG_SENSORS_EEPROM=m 1122CONFIG_SENSORS_EEPROM=m
1184CONFIG_SENSORS_PCF8574=m 1123CONFIG_SENSORS_PCF8574=m
1185# CONFIG_PCF8575 is not set 1124# CONFIG_PCF8575 is not set
1125# CONFIG_SENSORS_PCA9539 is not set
1186CONFIG_SENSORS_PCF8591=m 1126CONFIG_SENSORS_PCF8591=m
1187# CONFIG_SENSORS_MAX6875 is not set 1127# CONFIG_SENSORS_MAX6875 is not set
1188# CONFIG_SENSORS_TSL2550 is not set 1128# CONFIG_SENSORS_TSL2550 is not set
@@ -1191,10 +1131,13 @@ CONFIG_SENSORS_PCF8591=m
1191# CONFIG_I2C_DEBUG_BUS is not set 1131# CONFIG_I2C_DEBUG_BUS is not set
1192# CONFIG_I2C_DEBUG_CHIP is not set 1132# CONFIG_I2C_DEBUG_CHIP is not set
1193# CONFIG_SPI is not set 1133# CONFIG_SPI is not set
1134CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
1135# CONFIG_GPIOLIB is not set
1194# CONFIG_W1 is not set 1136# CONFIG_W1 is not set
1195# CONFIG_POWER_SUPPLY is not set 1137# CONFIG_POWER_SUPPLY is not set
1196CONFIG_HWMON=m 1138CONFIG_HWMON=m
1197CONFIG_HWMON_VID=m 1139CONFIG_HWMON_VID=m
1140# CONFIG_SENSORS_AD7414 is not set
1198# CONFIG_SENSORS_AD7418 is not set 1141# CONFIG_SENSORS_AD7418 is not set
1199CONFIG_SENSORS_ADM1021=m 1142CONFIG_SENSORS_ADM1021=m
1200CONFIG_SENSORS_ADM1025=m 1143CONFIG_SENSORS_ADM1025=m
@@ -1255,6 +1198,7 @@ CONFIG_WATCHDOG=y
1255# Watchdog Device Drivers 1198# Watchdog Device Drivers
1256# 1199#
1257CONFIG_SOFT_WATCHDOG=m 1200CONFIG_SOFT_WATCHDOG=m
1201# CONFIG_ALIM7101_WDT is not set
1258# CONFIG_MV64X60_WDT is not set 1202# CONFIG_MV64X60_WDT is not set
1259 1203
1260# 1204#
@@ -1278,8 +1222,10 @@ CONFIG_SSB_POSSIBLE=y
1278# 1222#
1279# Multifunction device drivers 1223# Multifunction device drivers
1280# 1224#
1225# CONFIG_MFD_CORE is not set
1281# CONFIG_MFD_SM501 is not set 1226# CONFIG_MFD_SM501 is not set
1282# CONFIG_HTC_PASIC3 is not set 1227# CONFIG_HTC_PASIC3 is not set
1228# CONFIG_MFD_TMIO is not set
1283 1229
1284# 1230#
1285# Multimedia devices 1231# Multimedia devices
@@ -1290,6 +1236,7 @@ CONFIG_SSB_POSSIBLE=y
1290# 1236#
1291# CONFIG_VIDEO_DEV is not set 1237# CONFIG_VIDEO_DEV is not set
1292# CONFIG_DVB_CORE is not set 1238# CONFIG_DVB_CORE is not set
1239# CONFIG_VIDEO_MEDIA is not set
1293 1240
1294# 1241#
1295# Multimedia drivers 1242# Multimedia drivers
@@ -1316,10 +1263,6 @@ CONFIG_SSB_POSSIBLE=y
1316# 1263#
1317# CONFIG_VGA_CONSOLE is not set 1264# CONFIG_VGA_CONSOLE is not set
1318CONFIG_DUMMY_CONSOLE=y 1265CONFIG_DUMMY_CONSOLE=y
1319
1320#
1321# Sound
1322#
1323# CONFIG_SOUND is not set 1266# CONFIG_SOUND is not set
1324# CONFIG_HID_SUPPORT is not set 1267# CONFIG_HID_SUPPORT is not set
1325CONFIG_HID=m 1268CONFIG_HID=m
@@ -1339,6 +1282,7 @@ CONFIG_USB_DEVICEFS=y
1339# CONFIG_USB_DYNAMIC_MINORS is not set 1282# CONFIG_USB_DYNAMIC_MINORS is not set
1340CONFIG_USB_SUSPEND=y 1283CONFIG_USB_SUSPEND=y
1341# CONFIG_USB_OTG is not set 1284# CONFIG_USB_OTG is not set
1285CONFIG_USB_MON=y
1342 1286
1343# 1287#
1344# USB Host Controller Drivers 1288# USB Host Controller Drivers
@@ -1363,10 +1307,15 @@ CONFIG_USB_UHCI_HCD=m
1363# CONFIG_USB_R8A66597_HCD is not set 1307# CONFIG_USB_R8A66597_HCD is not set
1364 1308
1365# 1309#
1310# Enable Host or Gadget support to see Inventra options
1311#
1312
1313#
1366# USB Device Class drivers 1314# USB Device Class drivers
1367# 1315#
1368CONFIG_USB_ACM=m 1316CONFIG_USB_ACM=m
1369CONFIG_USB_PRINTER=m 1317CONFIG_USB_PRINTER=m
1318# CONFIG_USB_WDM is not set
1370 1319
1371# 1320#
1372# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 1321# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
@@ -1388,6 +1337,7 @@ CONFIG_USB_STORAGE_JUMPSHOT=y
1388# CONFIG_USB_STORAGE_ALAUDA is not set 1337# CONFIG_USB_STORAGE_ALAUDA is not set
1389# CONFIG_USB_STORAGE_ONETOUCH is not set 1338# CONFIG_USB_STORAGE_ONETOUCH is not set
1390# CONFIG_USB_STORAGE_KARMA is not set 1339# CONFIG_USB_STORAGE_KARMA is not set
1340# CONFIG_USB_STORAGE_SIERRA is not set
1391# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set 1341# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
1392# CONFIG_USB_LIBUSUAL is not set 1342# CONFIG_USB_LIBUSUAL is not set
1393 1343
@@ -1396,7 +1346,6 @@ CONFIG_USB_STORAGE_JUMPSHOT=y
1396# 1346#
1397CONFIG_USB_MDC800=m 1347CONFIG_USB_MDC800=m
1398CONFIG_USB_MICROTEK=m 1348CONFIG_USB_MICROTEK=m
1399CONFIG_USB_MON=y
1400 1349
1401# 1350#
1402# USB port drivers 1351# USB port drivers
@@ -1405,7 +1354,6 @@ CONFIG_USB_SERIAL=m
1405CONFIG_USB_EZUSB=y 1354CONFIG_USB_EZUSB=y
1406CONFIG_USB_SERIAL_GENERIC=y 1355CONFIG_USB_SERIAL_GENERIC=y
1407# CONFIG_USB_SERIAL_AIRCABLE is not set 1356# CONFIG_USB_SERIAL_AIRCABLE is not set
1408# CONFIG_USB_SERIAL_AIRPRIME is not set
1409# CONFIG_USB_SERIAL_ARK3116 is not set 1357# CONFIG_USB_SERIAL_ARK3116 is not set
1410CONFIG_USB_SERIAL_BELKIN=m 1358CONFIG_USB_SERIAL_BELKIN=m
1411# CONFIG_USB_SERIAL_CH341 is not set 1359# CONFIG_USB_SERIAL_CH341 is not set
@@ -1443,6 +1391,7 @@ CONFIG_USB_SERIAL_KOBIL_SCT=m
1443CONFIG_USB_SERIAL_MCT_U232=m 1391CONFIG_USB_SERIAL_MCT_U232=m
1444# CONFIG_USB_SERIAL_MOS7720 is not set 1392# CONFIG_USB_SERIAL_MOS7720 is not set
1445# CONFIG_USB_SERIAL_MOS7840 is not set 1393# CONFIG_USB_SERIAL_MOS7840 is not set
1394# CONFIG_USB_SERIAL_MOTOROLA is not set
1446# CONFIG_USB_SERIAL_NAVMAN is not set 1395# CONFIG_USB_SERIAL_NAVMAN is not set
1447CONFIG_USB_SERIAL_PL2303=m 1396CONFIG_USB_SERIAL_PL2303=m
1448# CONFIG_USB_SERIAL_OTI6858 is not set 1397# CONFIG_USB_SERIAL_OTI6858 is not set
@@ -1464,7 +1413,6 @@ CONFIG_USB_SERIAL_OMNINET=m
1464CONFIG_USB_EMI62=m 1413CONFIG_USB_EMI62=m
1465# CONFIG_USB_EMI26 is not set 1414# CONFIG_USB_EMI26 is not set
1466# CONFIG_USB_ADUTUX is not set 1415# CONFIG_USB_ADUTUX is not set
1467CONFIG_USB_AUERSWALD=m
1468CONFIG_USB_RIO500=m 1416CONFIG_USB_RIO500=m
1469CONFIG_USB_LEGOTOWER=m 1417CONFIG_USB_LEGOTOWER=m
1470CONFIG_USB_LCD=m 1418CONFIG_USB_LCD=m
@@ -1481,6 +1429,7 @@ CONFIG_USB_LED=m
1481# CONFIG_USB_TRANCEVIBRATOR is not set 1429# CONFIG_USB_TRANCEVIBRATOR is not set
1482# CONFIG_USB_IOWARRIOR is not set 1430# CONFIG_USB_IOWARRIOR is not set
1483CONFIG_USB_TEST=m 1431CONFIG_USB_TEST=m
1432# CONFIG_USB_ISIGHTFW is not set
1484CONFIG_USB_ATM=m 1433CONFIG_USB_ATM=m
1485CONFIG_USB_SPEEDTOUCH=m 1434CONFIG_USB_SPEEDTOUCH=m
1486# CONFIG_USB_CXACRU is not set 1435# CONFIG_USB_CXACRU is not set
@@ -1601,6 +1550,7 @@ CONFIG_JFFS2_RTIME=y
1601CONFIG_CRAMFS=m 1550CONFIG_CRAMFS=m
1602CONFIG_VXFS_FS=m 1551CONFIG_VXFS_FS=m
1603# CONFIG_MINIX_FS is not set 1552# CONFIG_MINIX_FS is not set
1553# CONFIG_OMFS_FS is not set
1604# CONFIG_HPFS_FS is not set 1554# CONFIG_HPFS_FS is not set
1605# CONFIG_QNX4FS_FS is not set 1555# CONFIG_QNX4FS_FS is not set
1606# CONFIG_ROMFS_FS is not set 1556# CONFIG_ROMFS_FS is not set
@@ -1611,8 +1561,8 @@ CONFIG_NFS_FS=y
1611CONFIG_NFS_V3=y 1561CONFIG_NFS_V3=y
1612CONFIG_NFS_V3_ACL=y 1562CONFIG_NFS_V3_ACL=y
1613CONFIG_NFS_V4=y 1563CONFIG_NFS_V4=y
1614# CONFIG_NFSD is not set
1615CONFIG_ROOT_NFS=y 1564CONFIG_ROOT_NFS=y
1565# CONFIG_NFSD is not set
1616CONFIG_LOCKD=y 1566CONFIG_LOCKD=y
1617CONFIG_LOCKD_V4=y 1567CONFIG_LOCKD_V4=y
1618CONFIG_NFS_ACL_SUPPORT=y 1568CONFIG_NFS_ACL_SUPPORT=y
@@ -1620,7 +1570,6 @@ CONFIG_NFS_COMMON=y
1620CONFIG_SUNRPC=y 1570CONFIG_SUNRPC=y
1621CONFIG_SUNRPC_GSS=y 1571CONFIG_SUNRPC_GSS=y
1622CONFIG_SUNRPC_XPRT_RDMA=m 1572CONFIG_SUNRPC_XPRT_RDMA=m
1623# CONFIG_SUNRPC_BIND34 is not set
1624CONFIG_RPCSEC_GSS_KRB5=y 1573CONFIG_RPCSEC_GSS_KRB5=y
1625CONFIG_RPCSEC_GSS_SPKM3=m 1574CONFIG_RPCSEC_GSS_SPKM3=m
1626# CONFIG_SMB_FS is not set 1575# CONFIG_SMB_FS is not set
@@ -1705,6 +1654,7 @@ CONFIG_BITREVERSE=y
1705# CONFIG_GENERIC_FIND_FIRST_BIT is not set 1654# CONFIG_GENERIC_FIND_FIRST_BIT is not set
1706CONFIG_CRC_CCITT=m 1655CONFIG_CRC_CCITT=m
1707# CONFIG_CRC16 is not set 1656# CONFIG_CRC16 is not set
1657CONFIG_CRC_T10DIF=m
1708CONFIG_CRC_ITU_T=m 1658CONFIG_CRC_ITU_T=m
1709CONFIG_CRC32=y 1659CONFIG_CRC32=y
1710# CONFIG_CRC7 is not set 1660# CONFIG_CRC7 is not set
@@ -1732,6 +1682,8 @@ CONFIG_MAGIC_SYSRQ=y
1732CONFIG_DEBUG_KERNEL=y 1682CONFIG_DEBUG_KERNEL=y
1733# CONFIG_DEBUG_SHIRQ is not set 1683# CONFIG_DEBUG_SHIRQ is not set
1734CONFIG_DETECT_SOFTLOCKUP=y 1684CONFIG_DETECT_SOFTLOCKUP=y
1685# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
1686CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
1735CONFIG_SCHED_DEBUG=y 1687CONFIG_SCHED_DEBUG=y
1736# CONFIG_SCHEDSTATS is not set 1688# CONFIG_SCHEDSTATS is not set
1737# CONFIG_TIMER_STATS is not set 1689# CONFIG_TIMER_STATS is not set
@@ -1750,6 +1702,7 @@ CONFIG_DEBUG_BUGVERBOSE=y
1750CONFIG_DEBUG_INFO=y 1702CONFIG_DEBUG_INFO=y
1751# CONFIG_DEBUG_VM is not set 1703# CONFIG_DEBUG_VM is not set
1752# CONFIG_DEBUG_WRITECOUNT is not set 1704# CONFIG_DEBUG_WRITECOUNT is not set
1705CONFIG_DEBUG_MEMORY_INIT=y
1753# CONFIG_DEBUG_LIST is not set 1706# CONFIG_DEBUG_LIST is not set
1754# CONFIG_DEBUG_SG is not set 1707# CONFIG_DEBUG_SG is not set
1755# CONFIG_BOOT_PRINTK_DELAY is not set 1708# CONFIG_BOOT_PRINTK_DELAY is not set
@@ -1758,11 +1711,22 @@ CONFIG_DEBUG_INFO=y
1758# CONFIG_BACKTRACE_SELF_TEST is not set 1711# CONFIG_BACKTRACE_SELF_TEST is not set
1759# CONFIG_LKDTM is not set 1712# CONFIG_LKDTM is not set
1760# CONFIG_FAULT_INJECTION is not set 1713# CONFIG_FAULT_INJECTION is not set
1714# CONFIG_LATENCYTOP is not set
1715CONFIG_SYSCTL_SYSCALL_CHECK=y
1716CONFIG_HAVE_FTRACE=y
1717CONFIG_HAVE_DYNAMIC_FTRACE=y
1718# CONFIG_FTRACE is not set
1719# CONFIG_SCHED_TRACER is not set
1720# CONFIG_CONTEXT_SWITCH_TRACER is not set
1761# CONFIG_SAMPLES is not set 1721# CONFIG_SAMPLES is not set
1722CONFIG_HAVE_ARCH_KGDB=y
1723# CONFIG_KGDB is not set
1762CONFIG_DEBUG_STACKOVERFLOW=y 1724CONFIG_DEBUG_STACKOVERFLOW=y
1763CONFIG_DEBUG_STACK_USAGE=y 1725CONFIG_DEBUG_STACK_USAGE=y
1764# CONFIG_DEBUG_PAGEALLOC is not set 1726# CONFIG_DEBUG_PAGEALLOC is not set
1765# CONFIG_DEBUGGER is not set 1727# CONFIG_CODE_PATCHING_SELFTEST is not set
1728# CONFIG_FTR_FIXUP_SELFTEST is not set
1729# CONFIG_XMON is not set
1766# CONFIG_IRQSTACKS is not set 1730# CONFIG_IRQSTACKS is not set
1767# CONFIG_BDI_SWITCH is not set 1731# CONFIG_BDI_SWITCH is not set
1768CONFIG_BOOTX_TEXT=y 1732CONFIG_BOOTX_TEXT=y
@@ -1776,7 +1740,6 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
1776CONFIG_SECURITY=y 1740CONFIG_SECURITY=y
1777CONFIG_SECURITY_NETWORK=y 1741CONFIG_SECURITY_NETWORK=y
1778# CONFIG_SECURITY_NETWORK_XFRM is not set 1742# CONFIG_SECURITY_NETWORK_XFRM is not set
1779CONFIG_SECURITY_CAPABILITIES=y
1780# CONFIG_SECURITY_FILE_CAPABILITIES is not set 1743# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1781CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0 1744CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0
1782CONFIG_SECURITY_SELINUX=y 1745CONFIG_SECURITY_SELINUX=y
@@ -1835,6 +1798,10 @@ CONFIG_CRYPTO_CRC32C=m
1835CONFIG_CRYPTO_MD4=m 1798CONFIG_CRYPTO_MD4=m
1836CONFIG_CRYPTO_MD5=y 1799CONFIG_CRYPTO_MD5=y
1837CONFIG_CRYPTO_MICHAEL_MIC=m 1800CONFIG_CRYPTO_MICHAEL_MIC=m
1801# CONFIG_CRYPTO_RMD128 is not set
1802# CONFIG_CRYPTO_RMD160 is not set
1803# CONFIG_CRYPTO_RMD256 is not set
1804# CONFIG_CRYPTO_RMD320 is not set
1838CONFIG_CRYPTO_SHA1=y 1805CONFIG_CRYPTO_SHA1=y
1839CONFIG_CRYPTO_SHA256=m 1806CONFIG_CRYPTO_SHA256=m
1840CONFIG_CRYPTO_SHA512=m 1807CONFIG_CRYPTO_SHA512=m
diff --git a/arch/powerpc/configs/chrp32_defconfig b/arch/powerpc/configs/chrp32_defconfig
index 05360d4ef1b1..2e0ef8c18227 100644
--- a/arch/powerpc/configs/chrp32_defconfig
+++ b/arch/powerpc/configs/chrp32_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc3 3# Linux kernel version: 2.6.27-rc4
4# Tue May 20 20:00:44 2008 4# Tue Aug 26 13:12:40 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -33,6 +33,7 @@ CONFIG_GENERIC_HARDIRQS=y
33# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set 33# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
34CONFIG_IRQ_PER_CPU=y 34CONFIG_IRQ_PER_CPU=y
35CONFIG_STACKTRACE_SUPPORT=y 35CONFIG_STACKTRACE_SUPPORT=y
36CONFIG_HAVE_LATENCYTOP_SUPPORT=y
36CONFIG_LOCKDEP_SUPPORT=y 37CONFIG_LOCKDEP_SUPPORT=y
37CONFIG_RWSEM_XCHGADD_ALGORITHM=y 38CONFIG_RWSEM_XCHGADD_ALGORITHM=y
38CONFIG_ARCH_HAS_ILOG2_U32=y 39CONFIG_ARCH_HAS_ILOG2_U32=y
@@ -90,7 +91,6 @@ CONFIG_INITRAMFS_SOURCE=""
90CONFIG_SYSCTL=y 91CONFIG_SYSCTL=y
91# CONFIG_EMBEDDED is not set 92# CONFIG_EMBEDDED is not set
92CONFIG_SYSCTL_SYSCALL=y 93CONFIG_SYSCTL_SYSCALL=y
93CONFIG_SYSCTL_SYSCALL_CHECK=y
94CONFIG_KALLSYMS=y 94CONFIG_KALLSYMS=y
95# CONFIG_KALLSYMS_ALL is not set 95# CONFIG_KALLSYMS_ALL is not set
96# CONFIG_KALLSYMS_EXTRA_PASS is not set 96# CONFIG_KALLSYMS_EXTRA_PASS is not set
@@ -117,10 +117,16 @@ CONFIG_SLUB=y
117# CONFIG_MARKERS is not set 117# CONFIG_MARKERS is not set
118CONFIG_HAVE_OPROFILE=y 118CONFIG_HAVE_OPROFILE=y
119# CONFIG_KPROBES is not set 119# CONFIG_KPROBES is not set
120CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
121CONFIG_HAVE_IOREMAP_PROT=y
120CONFIG_HAVE_KPROBES=y 122CONFIG_HAVE_KPROBES=y
121CONFIG_HAVE_KRETPROBES=y 123CONFIG_HAVE_KRETPROBES=y
124CONFIG_HAVE_ARCH_TRACEHOOK=y
122# CONFIG_HAVE_DMA_ATTRS is not set 125# CONFIG_HAVE_DMA_ATTRS is not set
126CONFIG_USE_GENERIC_SMP_HELPERS=y
127# CONFIG_HAVE_CLK is not set
123CONFIG_PROC_PAGE_MONITOR=y 128CONFIG_PROC_PAGE_MONITOR=y
129# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
124CONFIG_SLABINFO=y 130CONFIG_SLABINFO=y
125CONFIG_RT_MUTEXES=y 131CONFIG_RT_MUTEXES=y
126# CONFIG_TINY_SHMEM is not set 132# CONFIG_TINY_SHMEM is not set
@@ -138,6 +144,7 @@ CONFIG_LBD=y
138# CONFIG_BLK_DEV_IO_TRACE is not set 144# CONFIG_BLK_DEV_IO_TRACE is not set
139# CONFIG_LSF is not set 145# CONFIG_LSF is not set
140# CONFIG_BLK_DEV_BSG is not set 146# CONFIG_BLK_DEV_BSG is not set
147# CONFIG_BLK_DEV_INTEGRITY is not set
141 148
142# 149#
143# IO Schedulers 150# IO Schedulers
@@ -157,19 +164,18 @@ CONFIG_CLASSIC_RCU=y
157# Platform support 164# Platform support
158# 165#
159CONFIG_PPC_MULTIPLATFORM=y 166CONFIG_PPC_MULTIPLATFORM=y
160# CONFIG_PPC_82xx is not set
161# CONFIG_PPC_83xx is not set
162# CONFIG_PPC_86xx is not set
163CONFIG_CLASSIC32=y 167CONFIG_CLASSIC32=y
164CONFIG_PPC_CHRP=y 168CONFIG_PPC_CHRP=y
165# CONFIG_PPC_MPC512x is not set
166# CONFIG_PPC_MPC5121 is not set
167# CONFIG_MPC5121_ADS is not set 169# CONFIG_MPC5121_ADS is not set
170# CONFIG_MPC5121_GENERIC is not set
168# CONFIG_PPC_MPC52xx is not set 171# CONFIG_PPC_MPC52xx is not set
169# CONFIG_PPC_PMAC is not set 172# CONFIG_PPC_PMAC is not set
170# CONFIG_PPC_CELL is not set 173# CONFIG_PPC_CELL is not set
171# CONFIG_PPC_CELL_NATIVE is not set 174# CONFIG_PPC_CELL_NATIVE is not set
175# CONFIG_PPC_82xx is not set
172# CONFIG_PQ2ADS is not set 176# CONFIG_PQ2ADS is not set
177# CONFIG_PPC_83xx is not set
178# CONFIG_PPC_86xx is not set
173CONFIG_PPC_NATIVE=y 179CONFIG_PPC_NATIVE=y
174# CONFIG_UDBG_RTAS_CONSOLE is not set 180# CONFIG_UDBG_RTAS_CONSOLE is not set
175# CONFIG_IPIC is not set 181# CONFIG_IPIC is not set
@@ -201,7 +207,7 @@ CONFIG_HZ_250=y
201# CONFIG_HZ_300 is not set 207# CONFIG_HZ_300 is not set
202# CONFIG_HZ_1000 is not set 208# CONFIG_HZ_1000 is not set
203CONFIG_HZ=250 209CONFIG_HZ=250
204# CONFIG_SCHED_HRTICK is not set 210CONFIG_SCHED_HRTICK=y
205CONFIG_PREEMPT_NONE=y 211CONFIG_PREEMPT_NONE=y
206# CONFIG_PREEMPT_VOLUNTARY is not set 212# CONFIG_PREEMPT_VOLUNTARY is not set
207# CONFIG_PREEMPT is not set 213# CONFIG_PREEMPT is not set
@@ -225,6 +231,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
225# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set 231# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
226CONFIG_PAGEFLAGS_EXTENDED=y 232CONFIG_PAGEFLAGS_EXTENDED=y
227CONFIG_SPLIT_PTLOCK_CPUS=4 233CONFIG_SPLIT_PTLOCK_CPUS=4
234# CONFIG_MIGRATION is not set
228# CONFIG_RESOURCES_64BIT is not set 235# CONFIG_RESOURCES_64BIT is not set
229CONFIG_ZONE_DMA_FLAG=1 236CONFIG_ZONE_DMA_FLAG=1
230CONFIG_BOUNCE=y 237CONFIG_BOUNCE=y
@@ -232,6 +239,7 @@ CONFIG_VIRT_TO_BUS=y
232CONFIG_FORCE_MAX_ZONEORDER=11 239CONFIG_FORCE_MAX_ZONEORDER=11
233CONFIG_PROC_DEVICETREE=y 240CONFIG_PROC_DEVICETREE=y
234# CONFIG_CMDLINE_BOOL is not set 241# CONFIG_CMDLINE_BOOL is not set
242CONFIG_EXTRA_TARGETS=""
235# CONFIG_PM is not set 243# CONFIG_PM is not set
236CONFIG_SECCOMP=y 244CONFIG_SECCOMP=y
237CONFIG_ISA_DMA_API=y 245CONFIG_ISA_DMA_API=y
@@ -268,10 +276,6 @@ CONFIG_PAGE_OFFSET=0xc0000000
268CONFIG_KERNEL_START=0xc0000000 276CONFIG_KERNEL_START=0xc0000000
269CONFIG_PHYSICAL_START=0x00000000 277CONFIG_PHYSICAL_START=0x00000000
270CONFIG_TASK_SIZE=0xc0000000 278CONFIG_TASK_SIZE=0xc0000000
271
272#
273# Networking
274#
275CONFIG_NET=y 279CONFIG_NET=y
276 280
277# 281#
@@ -398,7 +402,9 @@ CONFIG_NF_NAT_SIP=m
398CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 402CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
399# CONFIG_STANDALONE is not set 403# CONFIG_STANDALONE is not set
400CONFIG_PREVENT_FIRMWARE_BUILD=y 404CONFIG_PREVENT_FIRMWARE_BUILD=y
401# CONFIG_FW_LOADER is not set 405CONFIG_FW_LOADER=y
406CONFIG_FIRMWARE_IN_KERNEL=y
407CONFIG_EXTRA_FIRMWARE=""
402# CONFIG_DEBUG_DRIVER is not set 408# CONFIG_DEBUG_DRIVER is not set
403# CONFIG_DEBUG_DEVRES is not set 409# CONFIG_DEBUG_DEVRES is not set
404# CONFIG_SYS_HYPERVISOR is not set 410# CONFIG_SYS_HYPERVISOR is not set
@@ -427,12 +433,14 @@ CONFIG_BLK_DEV_RAM_SIZE=4096
427# CONFIG_BLK_DEV_XIP is not set 433# CONFIG_BLK_DEV_XIP is not set
428# CONFIG_CDROM_PKTCDVD is not set 434# CONFIG_CDROM_PKTCDVD is not set
429# CONFIG_ATA_OVER_ETH is not set 435# CONFIG_ATA_OVER_ETH is not set
436# CONFIG_BLK_DEV_HD is not set
430CONFIG_MISC_DEVICES=y 437CONFIG_MISC_DEVICES=y
431# CONFIG_PHANTOM is not set 438# CONFIG_PHANTOM is not set
432# CONFIG_EEPROM_93CX6 is not set 439# CONFIG_EEPROM_93CX6 is not set
433# CONFIG_SGI_IOC4 is not set 440# CONFIG_SGI_IOC4 is not set
434# CONFIG_TIFM_CORE is not set 441# CONFIG_TIFM_CORE is not set
435# CONFIG_ENCLOSURE_SERVICES is not set 442# CONFIG_ENCLOSURE_SERVICES is not set
443# CONFIG_HP_ILO is not set
436CONFIG_HAVE_IDE=y 444CONFIG_HAVE_IDE=y
437CONFIG_IDE=y 445CONFIG_IDE=y
438CONFIG_BLK_DEV_IDE=y 446CONFIG_BLK_DEV_IDE=y
@@ -440,6 +448,7 @@ CONFIG_BLK_DEV_IDE=y
440# 448#
441# Please see Documentation/ide/ide.txt for help/info on IDE drives 449# Please see Documentation/ide/ide.txt for help/info on IDE drives
442# 450#
451CONFIG_IDE_TIMINGS=y
443# CONFIG_BLK_DEV_IDE_SATA is not set 452# CONFIG_BLK_DEV_IDE_SATA is not set
444CONFIG_BLK_DEV_IDEDISK=y 453CONFIG_BLK_DEV_IDEDISK=y
445CONFIG_IDEDISK_MULTI_MODE=y 454CONFIG_IDEDISK_MULTI_MODE=y
@@ -454,7 +463,6 @@ CONFIG_IDE_PROC_FS=y
454# 463#
455# IDE chipset support/bugfixes 464# IDE chipset support/bugfixes
456# 465#
457CONFIG_IDE_GENERIC=y
458# CONFIG_BLK_DEV_PLATFORM is not set 466# CONFIG_BLK_DEV_PLATFORM is not set
459CONFIG_BLK_DEV_IDEDMA_SFF=y 467CONFIG_BLK_DEV_IDEDMA_SFF=y
460 468
@@ -472,10 +480,8 @@ CONFIG_BLK_DEV_IDEDMA_PCI=y
472# CONFIG_BLK_DEV_AMD74XX is not set 480# CONFIG_BLK_DEV_AMD74XX is not set
473# CONFIG_BLK_DEV_CMD64X is not set 481# CONFIG_BLK_DEV_CMD64X is not set
474# CONFIG_BLK_DEV_TRIFLEX is not set 482# CONFIG_BLK_DEV_TRIFLEX is not set
475# CONFIG_BLK_DEV_CY82C693 is not set
476# CONFIG_BLK_DEV_CS5520 is not set 483# CONFIG_BLK_DEV_CS5520 is not set
477# CONFIG_BLK_DEV_CS5530 is not set 484# CONFIG_BLK_DEV_CS5530 is not set
478# CONFIG_BLK_DEV_HPT34X is not set
479# CONFIG_BLK_DEV_HPT366 is not set 485# CONFIG_BLK_DEV_HPT366 is not set
480# CONFIG_BLK_DEV_JMICRON is not set 486# CONFIG_BLK_DEV_JMICRON is not set
481# CONFIG_BLK_DEV_SC1200 is not set 487# CONFIG_BLK_DEV_SC1200 is not set
@@ -493,8 +499,6 @@ CONFIG_BLK_DEV_SL82C105=y
493CONFIG_BLK_DEV_VIA82CXXX=y 499CONFIG_BLK_DEV_VIA82CXXX=y
494# CONFIG_BLK_DEV_TC86C001 is not set 500# CONFIG_BLK_DEV_TC86C001 is not set
495CONFIG_BLK_DEV_IDEDMA=y 501CONFIG_BLK_DEV_IDEDMA=y
496# CONFIG_BLK_DEV_HD_ONLY is not set
497# CONFIG_BLK_DEV_HD is not set
498 502
499# 503#
500# SCSI device support 504# SCSI device support
@@ -588,6 +592,7 @@ CONFIG_SCSI_SYM53C8XX_MMIO=y
588# CONFIG_SCSI_NSP32 is not set 592# CONFIG_SCSI_NSP32 is not set
589# CONFIG_SCSI_DEBUG is not set 593# CONFIG_SCSI_DEBUG is not set
590# CONFIG_SCSI_SRP is not set 594# CONFIG_SCSI_SRP is not set
595# CONFIG_SCSI_DH is not set
591# CONFIG_ATA is not set 596# CONFIG_ATA is not set
592# CONFIG_MD is not set 597# CONFIG_MD is not set
593# CONFIG_FUSION is not set 598# CONFIG_FUSION is not set
@@ -595,12 +600,15 @@ CONFIG_SCSI_SYM53C8XX_MMIO=y
595# 600#
596# IEEE 1394 (FireWire) support 601# IEEE 1394 (FireWire) support
597# 602#
603
604#
605# Enable only one of the two stacks, unless you know what you are doing
606#
598# CONFIG_FIREWIRE is not set 607# CONFIG_FIREWIRE is not set
599# CONFIG_IEEE1394 is not set 608# CONFIG_IEEE1394 is not set
600# CONFIG_I2O is not set 609# CONFIG_I2O is not set
601# CONFIG_MACINTOSH_DRIVERS is not set 610# CONFIG_MACINTOSH_DRIVERS is not set
602CONFIG_NETDEVICES=y 611CONFIG_NETDEVICES=y
603# CONFIG_NETDEVICES_MULTIQUEUE is not set
604# CONFIG_DUMMY is not set 612# CONFIG_DUMMY is not set
605# CONFIG_BONDING is not set 613# CONFIG_BONDING is not set
606# CONFIG_MACVLAN is not set 614# CONFIG_MACVLAN is not set
@@ -660,14 +668,12 @@ CONFIG_8139TOO=y
660# CONFIG_TLAN is not set 668# CONFIG_TLAN is not set
661CONFIG_VIA_RHINE=y 669CONFIG_VIA_RHINE=y
662# CONFIG_VIA_RHINE_MMIO is not set 670# CONFIG_VIA_RHINE_MMIO is not set
663# CONFIG_VIA_RHINE_NAPI is not set
664# CONFIG_SC92031 is not set 671# CONFIG_SC92031 is not set
665CONFIG_NETDEV_1000=y 672CONFIG_NETDEV_1000=y
666# CONFIG_ACENIC is not set 673# CONFIG_ACENIC is not set
667# CONFIG_DL2K is not set 674# CONFIG_DL2K is not set
668# CONFIG_E1000 is not set 675# CONFIG_E1000 is not set
669# CONFIG_E1000E is not set 676# CONFIG_E1000E is not set
670# CONFIG_E1000E_ENABLED is not set
671# CONFIG_IP1000 is not set 677# CONFIG_IP1000 is not set
672# CONFIG_IGB is not set 678# CONFIG_IGB is not set
673# CONFIG_NS83820 is not set 679# CONFIG_NS83820 is not set
@@ -683,6 +689,7 @@ CONFIG_NETDEV_1000=y
683CONFIG_MV643XX_ETH=y 689CONFIG_MV643XX_ETH=y
684# CONFIG_QLA3XXX is not set 690# CONFIG_QLA3XXX is not set
685# CONFIG_ATL1 is not set 691# CONFIG_ATL1 is not set
692# CONFIG_ATL1E is not set
686CONFIG_NETDEV_10000=y 693CONFIG_NETDEV_10000=y
687# CONFIG_CHELSIO_T1 is not set 694# CONFIG_CHELSIO_T1 is not set
688# CONFIG_CHELSIO_T3 is not set 695# CONFIG_CHELSIO_T3 is not set
@@ -773,6 +780,7 @@ CONFIG_MOUSE_PS2_TRACKPOINT=y
773# CONFIG_MOUSE_PS2_TOUCHKIT is not set 780# CONFIG_MOUSE_PS2_TOUCHKIT is not set
774# CONFIG_MOUSE_SERIAL is not set 781# CONFIG_MOUSE_SERIAL is not set
775# CONFIG_MOUSE_APPLETOUCH is not set 782# CONFIG_MOUSE_APPLETOUCH is not set
783# CONFIG_MOUSE_BCM5974 is not set
776# CONFIG_MOUSE_INPORT is not set 784# CONFIG_MOUSE_INPORT is not set
777# CONFIG_MOUSE_LOGIBM is not set 785# CONFIG_MOUSE_LOGIBM is not set
778# CONFIG_MOUSE_PC110PAD is not set 786# CONFIG_MOUSE_PC110PAD is not set
@@ -798,12 +806,14 @@ CONFIG_SERIO_SERPORT=y
798# CONFIG_SERIO_PCIPS2 is not set 806# CONFIG_SERIO_PCIPS2 is not set
799CONFIG_SERIO_LIBPS2=y 807CONFIG_SERIO_LIBPS2=y
800# CONFIG_SERIO_RAW is not set 808# CONFIG_SERIO_RAW is not set
809# CONFIG_SERIO_XILINX_XPS_PS2 is not set
801# CONFIG_GAMEPORT is not set 810# CONFIG_GAMEPORT is not set
802 811
803# 812#
804# Character devices 813# Character devices
805# 814#
806CONFIG_VT=y 815CONFIG_VT=y
816CONFIG_CONSOLE_TRANSLATIONS=y
807CONFIG_VT_CONSOLE=y 817CONFIG_VT_CONSOLE=y
808CONFIG_HW_CONSOLE=y 818CONFIG_HW_CONSOLE=y
809# CONFIG_VT_HW_CONSOLE_BINDING is not set 819# CONFIG_VT_HW_CONSOLE_BINDING is not set
@@ -848,46 +858,71 @@ CONFIG_DEVPORT=y
848CONFIG_I2C=y 858CONFIG_I2C=y
849CONFIG_I2C_BOARDINFO=y 859CONFIG_I2C_BOARDINFO=y
850# CONFIG_I2C_CHARDEV is not set 860# CONFIG_I2C_CHARDEV is not set
861CONFIG_I2C_HELPER_AUTO=y
851CONFIG_I2C_ALGOBIT=y 862CONFIG_I2C_ALGOBIT=y
852 863
853# 864#
854# I2C Hardware Bus support 865# I2C Hardware Bus support
855# 866#
867
868#
869# PC SMBus host controller drivers
870#
856# CONFIG_I2C_ALI1535 is not set 871# CONFIG_I2C_ALI1535 is not set
857# CONFIG_I2C_ALI1563 is not set 872# CONFIG_I2C_ALI1563 is not set
858# CONFIG_I2C_ALI15X3 is not set 873# CONFIG_I2C_ALI15X3 is not set
859# CONFIG_I2C_AMD756 is not set 874# CONFIG_I2C_AMD756 is not set
860# CONFIG_I2C_AMD8111 is not set 875# CONFIG_I2C_AMD8111 is not set
861# CONFIG_I2C_HYDRA is not set
862# CONFIG_I2C_I801 is not set 876# CONFIG_I2C_I801 is not set
863# CONFIG_I2C_I810 is not set 877# CONFIG_I2C_ISCH is not set
864# CONFIG_I2C_PIIX4 is not set 878# CONFIG_I2C_PIIX4 is not set
865# CONFIG_I2C_MPC is not set
866# CONFIG_I2C_NFORCE2 is not set 879# CONFIG_I2C_NFORCE2 is not set
867# CONFIG_I2C_OCORES is not set
868# CONFIG_I2C_PARPORT_LIGHT is not set
869# CONFIG_I2C_PROSAVAGE is not set
870# CONFIG_I2C_SAVAGE4 is not set
871# CONFIG_I2C_SIMTEC is not set
872# CONFIG_I2C_SIS5595 is not set 880# CONFIG_I2C_SIS5595 is not set
873# CONFIG_I2C_SIS630 is not set 881# CONFIG_I2C_SIS630 is not set
874# CONFIG_I2C_SIS96X is not set 882# CONFIG_I2C_SIS96X is not set
875# CONFIG_I2C_TAOS_EVM is not set
876# CONFIG_I2C_STUB is not set
877# CONFIG_I2C_TINY_USB is not set
878# CONFIG_I2C_VIA is not set 883# CONFIG_I2C_VIA is not set
879# CONFIG_I2C_VIAPRO is not set 884# CONFIG_I2C_VIAPRO is not set
885
886#
887# Mac SMBus host controller drivers
888#
889# CONFIG_I2C_HYDRA is not set
890
891#
892# I2C system bus drivers (mostly embedded / system-on-chip)
893#
894# CONFIG_I2C_MPC is not set
895# CONFIG_I2C_OCORES is not set
896# CONFIG_I2C_SIMTEC is not set
897
898#
899# External I2C/SMBus adapter drivers
900#
901# CONFIG_I2C_PARPORT_LIGHT is not set
902# CONFIG_I2C_TAOS_EVM is not set
903# CONFIG_I2C_TINY_USB is not set
904
905#
906# Graphics adapter I2C/DDC channel drivers
907#
880# CONFIG_I2C_VOODOO3 is not set 908# CONFIG_I2C_VOODOO3 is not set
909
910#
911# Other I2C/SMBus bus drivers
912#
881# CONFIG_I2C_PCA_ISA is not set 913# CONFIG_I2C_PCA_ISA is not set
882# CONFIG_I2C_PCA_PLATFORM is not set 914# CONFIG_I2C_PCA_PLATFORM is not set
915# CONFIG_I2C_STUB is not set
883 916
884# 917#
885# Miscellaneous I2C Chip support 918# Miscellaneous I2C Chip support
886# 919#
887# CONFIG_DS1682 is not set 920# CONFIG_DS1682 is not set
921# CONFIG_AT24 is not set
888# CONFIG_SENSORS_EEPROM is not set 922# CONFIG_SENSORS_EEPROM is not set
889# CONFIG_SENSORS_PCF8574 is not set 923# CONFIG_SENSORS_PCF8574 is not set
890# CONFIG_PCF8575 is not set 924# CONFIG_PCF8575 is not set
925# CONFIG_SENSORS_PCA9539 is not set
891# CONFIG_SENSORS_PCF8591 is not set 926# CONFIG_SENSORS_PCF8591 is not set
892# CONFIG_SENSORS_MAX6875 is not set 927# CONFIG_SENSORS_MAX6875 is not set
893# CONFIG_SENSORS_TSL2550 is not set 928# CONFIG_SENSORS_TSL2550 is not set
@@ -896,10 +931,13 @@ CONFIG_I2C_ALGOBIT=y
896# CONFIG_I2C_DEBUG_BUS is not set 931# CONFIG_I2C_DEBUG_BUS is not set
897# CONFIG_I2C_DEBUG_CHIP is not set 932# CONFIG_I2C_DEBUG_CHIP is not set
898# CONFIG_SPI is not set 933# CONFIG_SPI is not set
934CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
935# CONFIG_GPIOLIB is not set
899# CONFIG_W1 is not set 936# CONFIG_W1 is not set
900# CONFIG_POWER_SUPPLY is not set 937# CONFIG_POWER_SUPPLY is not set
901# CONFIG_HWMON is not set 938# CONFIG_HWMON is not set
902# CONFIG_THERMAL is not set 939# CONFIG_THERMAL is not set
940# CONFIG_THERMAL_HWMON is not set
903# CONFIG_WATCHDOG is not set 941# CONFIG_WATCHDOG is not set
904 942
905# 943#
@@ -911,8 +949,10 @@ CONFIG_SSB_POSSIBLE=y
911# 949#
912# Multifunction device drivers 950# Multifunction device drivers
913# 951#
952# CONFIG_MFD_CORE is not set
914# CONFIG_MFD_SM501 is not set 953# CONFIG_MFD_SM501 is not set
915# CONFIG_HTC_PASIC3 is not set 954# CONFIG_HTC_PASIC3 is not set
955# CONFIG_MFD_TMIO is not set
916 956
917# 957#
918# Multimedia devices 958# Multimedia devices
@@ -997,10 +1037,13 @@ CONFIG_FB_3DFX=y
997# CONFIG_FB_TRIDENT is not set 1037# CONFIG_FB_TRIDENT is not set
998# CONFIG_FB_ARK is not set 1038# CONFIG_FB_ARK is not set
999# CONFIG_FB_PM3 is not set 1039# CONFIG_FB_PM3 is not set
1040# CONFIG_FB_CARMINE is not set
1000# CONFIG_FB_IBM_GXT4500 is not set 1041# CONFIG_FB_IBM_GXT4500 is not set
1001# CONFIG_FB_VIRTUAL is not set 1042# CONFIG_FB_VIRTUAL is not set
1002CONFIG_BACKLIGHT_LCD_SUPPORT=y 1043CONFIG_BACKLIGHT_LCD_SUPPORT=y
1003CONFIG_LCD_CLASS_DEVICE=m 1044CONFIG_LCD_CLASS_DEVICE=m
1045# CONFIG_LCD_ILI9320 is not set
1046# CONFIG_LCD_PLATFORM is not set
1004CONFIG_BACKLIGHT_CLASS_DEVICE=y 1047CONFIG_BACKLIGHT_CLASS_DEVICE=y
1005# CONFIG_BACKLIGHT_CORGI is not set 1048# CONFIG_BACKLIGHT_CORGI is not set
1006 1049
@@ -1030,10 +1073,6 @@ CONFIG_LOGO=y
1030CONFIG_LOGO_LINUX_MONO=y 1073CONFIG_LOGO_LINUX_MONO=y
1031CONFIG_LOGO_LINUX_VGA16=y 1074CONFIG_LOGO_LINUX_VGA16=y
1032CONFIG_LOGO_LINUX_CLUT224=y 1075CONFIG_LOGO_LINUX_CLUT224=y
1033
1034#
1035# Sound
1036#
1037# CONFIG_SOUND is not set 1076# CONFIG_SOUND is not set
1038CONFIG_HID_SUPPORT=y 1077CONFIG_HID_SUPPORT=y
1039CONFIG_HID=y 1078CONFIG_HID=y
@@ -1062,6 +1101,7 @@ CONFIG_USB_DEVICEFS=y
1062CONFIG_USB_DEVICE_CLASS=y 1101CONFIG_USB_DEVICE_CLASS=y
1063# CONFIG_USB_DYNAMIC_MINORS is not set 1102# CONFIG_USB_DYNAMIC_MINORS is not set
1064# CONFIG_USB_OTG is not set 1103# CONFIG_USB_OTG is not set
1104CONFIG_USB_MON=y
1065 1105
1066# 1106#
1067# USB Host Controller Drivers 1107# USB Host Controller Drivers
@@ -1087,6 +1127,7 @@ CONFIG_USB_UHCI_HCD=y
1087# 1127#
1088# CONFIG_USB_ACM is not set 1128# CONFIG_USB_ACM is not set
1089# CONFIG_USB_PRINTER is not set 1129# CONFIG_USB_PRINTER is not set
1130# CONFIG_USB_WDM is not set
1090 1131
1091# 1132#
1092# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 1133# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
@@ -1108,6 +1149,7 @@ CONFIG_USB_STORAGE=m
1108# CONFIG_USB_STORAGE_ALAUDA is not set 1149# CONFIG_USB_STORAGE_ALAUDA is not set
1109# CONFIG_USB_STORAGE_ONETOUCH is not set 1150# CONFIG_USB_STORAGE_ONETOUCH is not set
1110# CONFIG_USB_STORAGE_KARMA is not set 1151# CONFIG_USB_STORAGE_KARMA is not set
1152# CONFIG_USB_STORAGE_SIERRA is not set
1111# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set 1153# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
1112# CONFIG_USB_LIBUSUAL is not set 1154# CONFIG_USB_LIBUSUAL is not set
1113 1155
@@ -1116,7 +1158,6 @@ CONFIG_USB_STORAGE=m
1116# 1158#
1117# CONFIG_USB_MDC800 is not set 1159# CONFIG_USB_MDC800 is not set
1118# CONFIG_USB_MICROTEK is not set 1160# CONFIG_USB_MICROTEK is not set
1119CONFIG_USB_MON=y
1120 1161
1121# 1162#
1122# USB port drivers 1163# USB port drivers
@@ -1129,7 +1170,6 @@ CONFIG_USB_MON=y
1129# CONFIG_USB_EMI62 is not set 1170# CONFIG_USB_EMI62 is not set
1130# CONFIG_USB_EMI26 is not set 1171# CONFIG_USB_EMI26 is not set
1131# CONFIG_USB_ADUTUX is not set 1172# CONFIG_USB_ADUTUX is not set
1132# CONFIG_USB_AUERSWALD is not set
1133# CONFIG_USB_RIO500 is not set 1173# CONFIG_USB_RIO500 is not set
1134# CONFIG_USB_LEGOTOWER is not set 1174# CONFIG_USB_LEGOTOWER is not set
1135# CONFIG_USB_LCD is not set 1175# CONFIG_USB_LCD is not set
@@ -1146,6 +1186,7 @@ CONFIG_USB_MON=y
1146# CONFIG_USB_TRANCEVIBRATOR is not set 1186# CONFIG_USB_TRANCEVIBRATOR is not set
1147# CONFIG_USB_IOWARRIOR is not set 1187# CONFIG_USB_IOWARRIOR is not set
1148# CONFIG_USB_TEST is not set 1188# CONFIG_USB_TEST is not set
1189# CONFIG_USB_ISIGHTFW is not set
1149# CONFIG_USB_GADGET is not set 1190# CONFIG_USB_GADGET is not set
1150# CONFIG_MMC is not set 1191# CONFIG_MMC is not set
1151# CONFIG_MEMSTICK is not set 1192# CONFIG_MEMSTICK is not set
@@ -1226,6 +1267,7 @@ CONFIG_TMPFS=y
1226# CONFIG_CRAMFS is not set 1267# CONFIG_CRAMFS is not set
1227# CONFIG_VXFS_FS is not set 1268# CONFIG_VXFS_FS is not set
1228# CONFIG_MINIX_FS is not set 1269# CONFIG_MINIX_FS is not set
1270# CONFIG_OMFS_FS is not set
1229# CONFIG_HPFS_FS is not set 1271# CONFIG_HPFS_FS is not set
1230# CONFIG_QNX4FS_FS is not set 1272# CONFIG_QNX4FS_FS is not set
1231# CONFIG_ROMFS_FS is not set 1273# CONFIG_ROMFS_FS is not set
@@ -1310,6 +1352,7 @@ CONFIG_BITREVERSE=y
1310# CONFIG_GENERIC_FIND_FIRST_BIT is not set 1352# CONFIG_GENERIC_FIND_FIRST_BIT is not set
1311CONFIG_CRC_CCITT=m 1353CONFIG_CRC_CCITT=m
1312# CONFIG_CRC16 is not set 1354# CONFIG_CRC16 is not set
1355CONFIG_CRC_T10DIF=y
1313# CONFIG_CRC_ITU_T is not set 1356# CONFIG_CRC_ITU_T is not set
1314CONFIG_CRC32=y 1357CONFIG_CRC32=y
1315# CONFIG_CRC7 is not set 1358# CONFIG_CRC7 is not set
@@ -1336,6 +1379,8 @@ CONFIG_MAGIC_SYSRQ=y
1336CONFIG_DEBUG_KERNEL=y 1379CONFIG_DEBUG_KERNEL=y
1337# CONFIG_DEBUG_SHIRQ is not set 1380# CONFIG_DEBUG_SHIRQ is not set
1338CONFIG_DETECT_SOFTLOCKUP=y 1381CONFIG_DETECT_SOFTLOCKUP=y
1382# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
1383CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
1339CONFIG_SCHED_DEBUG=y 1384CONFIG_SCHED_DEBUG=y
1340# CONFIG_SCHEDSTATS is not set 1385# CONFIG_SCHEDSTATS is not set
1341# CONFIG_TIMER_STATS is not set 1386# CONFIG_TIMER_STATS is not set
@@ -1354,20 +1399,32 @@ CONFIG_DEBUG_BUGVERBOSE=y
1354# CONFIG_DEBUG_INFO is not set 1399# CONFIG_DEBUG_INFO is not set
1355# CONFIG_DEBUG_VM is not set 1400# CONFIG_DEBUG_VM is not set
1356# CONFIG_DEBUG_WRITECOUNT is not set 1401# CONFIG_DEBUG_WRITECOUNT is not set
1402CONFIG_DEBUG_MEMORY_INIT=y
1357# CONFIG_DEBUG_LIST is not set 1403# CONFIG_DEBUG_LIST is not set
1358# CONFIG_DEBUG_SG is not set 1404# CONFIG_DEBUG_SG is not set
1359# CONFIG_BOOT_PRINTK_DELAY is not set 1405# CONFIG_BOOT_PRINTK_DELAY is not set
1360# CONFIG_RCU_TORTURE_TEST is not set 1406# CONFIG_RCU_TORTURE_TEST is not set
1361# CONFIG_BACKTRACE_SELF_TEST is not set 1407# CONFIG_BACKTRACE_SELF_TEST is not set
1362# CONFIG_FAULT_INJECTION is not set 1408# CONFIG_FAULT_INJECTION is not set
1409# CONFIG_LATENCYTOP is not set
1410CONFIG_SYSCTL_SYSCALL_CHECK=y
1411CONFIG_HAVE_FTRACE=y
1412CONFIG_HAVE_DYNAMIC_FTRACE=y
1413# CONFIG_FTRACE is not set
1414# CONFIG_SCHED_TRACER is not set
1415# CONFIG_CONTEXT_SWITCH_TRACER is not set
1363# CONFIG_SAMPLES is not set 1416# CONFIG_SAMPLES is not set
1417CONFIG_HAVE_ARCH_KGDB=y
1418# CONFIG_KGDB is not set
1364# CONFIG_DEBUG_STACKOVERFLOW is not set 1419# CONFIG_DEBUG_STACKOVERFLOW is not set
1365# CONFIG_DEBUG_STACK_USAGE is not set 1420# CONFIG_DEBUG_STACK_USAGE is not set
1366# CONFIG_DEBUG_PAGEALLOC is not set 1421# CONFIG_DEBUG_PAGEALLOC is not set
1367CONFIG_DEBUGGER=y 1422# CONFIG_CODE_PATCHING_SELFTEST is not set
1423# CONFIG_FTR_FIXUP_SELFTEST is not set
1368CONFIG_XMON=y 1424CONFIG_XMON=y
1369CONFIG_XMON_DEFAULT=y 1425CONFIG_XMON_DEFAULT=y
1370CONFIG_XMON_DISASSEMBLY=y 1426CONFIG_XMON_DISASSEMBLY=y
1427CONFIG_DEBUGGER=y
1371CONFIG_IRQSTACKS=y 1428CONFIG_IRQSTACKS=y
1372# CONFIG_BDI_SWITCH is not set 1429# CONFIG_BDI_SWITCH is not set
1373# CONFIG_BOOTX_TEXT is not set 1430# CONFIG_BOOTX_TEXT is not set
@@ -1424,6 +1481,10 @@ CONFIG_CRYPTO_PCBC=m
1424# CONFIG_CRYPTO_MD4 is not set 1481# CONFIG_CRYPTO_MD4 is not set
1425# CONFIG_CRYPTO_MD5 is not set 1482# CONFIG_CRYPTO_MD5 is not set
1426# CONFIG_CRYPTO_MICHAEL_MIC is not set 1483# CONFIG_CRYPTO_MICHAEL_MIC is not set
1484# CONFIG_CRYPTO_RMD128 is not set
1485# CONFIG_CRYPTO_RMD160 is not set
1486# CONFIG_CRYPTO_RMD256 is not set
1487# CONFIG_CRYPTO_RMD320 is not set
1427CONFIG_CRYPTO_SHA1=m 1488CONFIG_CRYPTO_SHA1=m
1428# CONFIG_CRYPTO_SHA256 is not set 1489# CONFIG_CRYPTO_SHA256 is not set
1429# CONFIG_CRYPTO_SHA512 is not set 1490# CONFIG_CRYPTO_SHA512 is not set
diff --git a/arch/powerpc/configs/ep8248e_defconfig b/arch/powerpc/configs/ep8248e_defconfig
index ba2a463b9305..ef0c6e800508 100644
--- a/arch/powerpc/configs/ep8248e_defconfig
+++ b/arch/powerpc/configs/ep8248e_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc5 3# Linux kernel version: 2.6.27-rc4
4# Mon Jun 9 08:52:09 2008 4# Thu Aug 21 00:52:03 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -15,6 +15,7 @@ CONFIG_6xx=y
15# CONFIG_44x is not set 15# CONFIG_44x is not set
16# CONFIG_E200 is not set 16# CONFIG_E200 is not set
17CONFIG_PPC_FPU=y 17CONFIG_PPC_FPU=y
18# CONFIG_ALTIVEC is not set
18CONFIG_PPC_STD_MMU=y 19CONFIG_PPC_STD_MMU=y
19CONFIG_PPC_STD_MMU_32=y 20CONFIG_PPC_STD_MMU_32=y
20# CONFIG_PPC_MM_SLICES is not set 21# CONFIG_PPC_MM_SLICES is not set
@@ -31,12 +32,14 @@ CONFIG_GENERIC_HARDIRQS=y
31# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set 32# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
32CONFIG_IRQ_PER_CPU=y 33CONFIG_IRQ_PER_CPU=y
33CONFIG_STACKTRACE_SUPPORT=y 34CONFIG_STACKTRACE_SUPPORT=y
35CONFIG_HAVE_LATENCYTOP_SUPPORT=y
34CONFIG_LOCKDEP_SUPPORT=y 36CONFIG_LOCKDEP_SUPPORT=y
35CONFIG_RWSEM_XCHGADD_ALGORITHM=y 37CONFIG_RWSEM_XCHGADD_ALGORITHM=y
36CONFIG_ARCH_HAS_ILOG2_U32=y 38CONFIG_ARCH_HAS_ILOG2_U32=y
37CONFIG_GENERIC_HWEIGHT=y 39CONFIG_GENERIC_HWEIGHT=y
38CONFIG_GENERIC_CALIBRATE_DELAY=y 40CONFIG_GENERIC_CALIBRATE_DELAY=y
39CONFIG_GENERIC_FIND_NEXT_BIT=y 41CONFIG_GENERIC_FIND_NEXT_BIT=y
42CONFIG_GENERIC_GPIO=y
40# CONFIG_ARCH_NO_VIRT_TO_BUS is not set 43# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
41CONFIG_PPC=y 44CONFIG_PPC=y
42CONFIG_EARLY_PRINTK=y 45CONFIG_EARLY_PRINTK=y
@@ -45,11 +48,13 @@ CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
45CONFIG_ARCH_MAY_HAVE_PC_FDC=y 48CONFIG_ARCH_MAY_HAVE_PC_FDC=y
46CONFIG_PPC_OF=y 49CONFIG_PPC_OF=y
47CONFIG_OF=y 50CONFIG_OF=y
48# CONFIG_PPC_UDBG_16550 is not set 51CONFIG_PPC_UDBG_16550=y
49# CONFIG_GENERIC_TBSYNC is not set 52# CONFIG_GENERIC_TBSYNC is not set
50CONFIG_AUDIT_ARCH=y 53CONFIG_AUDIT_ARCH=y
51CONFIG_GENERIC_BUG=y 54CONFIG_GENERIC_BUG=y
52# CONFIG_DEFAULT_UIMAGE is not set 55# CONFIG_DEFAULT_UIMAGE is not set
56CONFIG_HIBERNATE_32=y
57CONFIG_ARCH_HIBERNATION_POSSIBLE=y
53# CONFIG_PPC_DCR_NATIVE is not set 58# CONFIG_PPC_DCR_NATIVE is not set
54# CONFIG_PPC_DCR_MMIO is not set 59# CONFIG_PPC_DCR_MMIO is not set
55CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 60CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
@@ -81,7 +86,6 @@ CONFIG_CC_OPTIMIZE_FOR_SIZE=y
81CONFIG_SYSCTL=y 86CONFIG_SYSCTL=y
82CONFIG_EMBEDDED=y 87CONFIG_EMBEDDED=y
83CONFIG_SYSCTL_SYSCALL=y 88CONFIG_SYSCTL_SYSCALL=y
84CONFIG_SYSCTL_SYSCALL_CHECK=y
85CONFIG_KALLSYMS=y 89CONFIG_KALLSYMS=y
86CONFIG_KALLSYMS_ALL=y 90CONFIG_KALLSYMS_ALL=y
87# CONFIG_KALLSYMS_EXTRA_PASS is not set 91# CONFIG_KALLSYMS_EXTRA_PASS is not set
@@ -89,6 +93,7 @@ CONFIG_HOTPLUG=y
89CONFIG_PRINTK=y 93CONFIG_PRINTK=y
90CONFIG_BUG=y 94CONFIG_BUG=y
91CONFIG_ELF_CORE=y 95CONFIG_ELF_CORE=y
96CONFIG_PCSPKR_PLATFORM=y
92CONFIG_COMPAT_BRK=y 97CONFIG_COMPAT_BRK=y
93CONFIG_BASE_FULL=y 98CONFIG_BASE_FULL=y
94CONFIG_FUTEX=y 99CONFIG_FUTEX=y
@@ -105,10 +110,16 @@ CONFIG_SLAB=y
105# CONFIG_PROFILING is not set 110# CONFIG_PROFILING is not set
106# CONFIG_MARKERS is not set 111# CONFIG_MARKERS is not set
107CONFIG_HAVE_OPROFILE=y 112CONFIG_HAVE_OPROFILE=y
113CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
114CONFIG_HAVE_IOREMAP_PROT=y
108CONFIG_HAVE_KPROBES=y 115CONFIG_HAVE_KPROBES=y
109CONFIG_HAVE_KRETPROBES=y 116CONFIG_HAVE_KRETPROBES=y
117CONFIG_HAVE_ARCH_TRACEHOOK=y
110# CONFIG_HAVE_DMA_ATTRS is not set 118# CONFIG_HAVE_DMA_ATTRS is not set
119# CONFIG_USE_GENERIC_SMP_HELPERS is not set
120CONFIG_HAVE_CLK=y
111CONFIG_PROC_PAGE_MONITOR=y 121CONFIG_PROC_PAGE_MONITOR=y
122# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
112CONFIG_SLABINFO=y 123CONFIG_SLABINFO=y
113CONFIG_RT_MUTEXES=y 124CONFIG_RT_MUTEXES=y
114# CONFIG_TINY_SHMEM is not set 125# CONFIG_TINY_SHMEM is not set
@@ -118,6 +129,7 @@ CONFIG_BLOCK=y
118# CONFIG_LBD is not set 129# CONFIG_LBD is not set
119# CONFIG_BLK_DEV_IO_TRACE is not set 130# CONFIG_BLK_DEV_IO_TRACE is not set
120# CONFIG_LSF is not set 131# CONFIG_LSF is not set
132# CONFIG_BLK_DEV_INTEGRITY is not set
121 133
122# 134#
123# IO Schedulers 135# IO Schedulers
@@ -136,33 +148,43 @@ CONFIG_CLASSIC_RCU=y
136# 148#
137# Platform support 149# Platform support
138# 150#
139# CONFIG_PPC_MULTIPLATFORM is not set 151CONFIG_PPC_MULTIPLATFORM=y
140CONFIG_PPC_82xx=y 152CONFIG_CLASSIC32=y
141# CONFIG_PPC_83xx is not set 153CONFIG_PPC_CHRP=y
142# CONFIG_PPC_86xx is not set 154# CONFIG_MPC5121_ADS is not set
143# CONFIG_PPC_MPC512x is not set 155# CONFIG_MPC5121_GENERIC is not set
144# CONFIG_PPC_MPC5121 is not set 156# CONFIG_PPC_MPC52xx is not set
157CONFIG_PPC_PMAC=y
145# CONFIG_PPC_CELL is not set 158# CONFIG_PPC_CELL is not set
146# CONFIG_PPC_CELL_NATIVE is not set 159# CONFIG_PPC_CELL_NATIVE is not set
160CONFIG_PPC_82xx=y
147# CONFIG_MPC8272_ADS is not set 161# CONFIG_MPC8272_ADS is not set
148# CONFIG_PQ2FADS is not set 162# CONFIG_PQ2FADS is not set
149CONFIG_EP8248E=y 163CONFIG_EP8248E=y
150# CONFIG_PQ2ADS is not set 164# CONFIG_PQ2ADS is not set
151CONFIG_8260=y 165CONFIG_8260=y
152CONFIG_8272=y 166CONFIG_8272=y
167# CONFIG_PPC_83xx is not set
168# CONFIG_PPC_86xx is not set
169# CONFIG_EMBEDDED6xx is not set
170CONFIG_PPC_NATIVE=y
171# CONFIG_UDBG_RTAS_CONSOLE is not set
153# CONFIG_IPIC is not set 172# CONFIG_IPIC is not set
154# CONFIG_MPIC is not set 173CONFIG_MPIC=y
155# CONFIG_MPIC_WEIRD is not set 174# CONFIG_MPIC_WEIRD is not set
156# CONFIG_PPC_I8259 is not set 175CONFIG_PPC_I8259=y
157# CONFIG_PPC_RTAS is not set 176CONFIG_PPC_RTAS=y
177# CONFIG_RTAS_ERROR_LOGGING is not set
178CONFIG_RTAS_PROC=y
158# CONFIG_MMIO_NVRAM is not set 179# CONFIG_MMIO_NVRAM is not set
159# CONFIG_PPC_MPC106 is not set 180CONFIG_PPC_MPC106=y
160# CONFIG_PPC_970_NAP is not set 181# CONFIG_PPC_970_NAP is not set
161# CONFIG_PPC_INDIRECT_IO is not set 182# CONFIG_PPC_INDIRECT_IO is not set
162# CONFIG_GENERIC_IOMAP is not set 183# CONFIG_GENERIC_IOMAP is not set
163# CONFIG_CPU_FREQ is not set 184# CONFIG_CPU_FREQ is not set
185# CONFIG_PPC601_SYNC_FIX is not set
186# CONFIG_TAU is not set
164CONFIG_CPM2=y 187CONFIG_CPM2=y
165CONFIG_PPC_CPM_NEW_BINDING=y
166# CONFIG_FSL_ULI1575 is not set 188# CONFIG_FSL_ULI1575 is not set
167CONFIG_CPM=y 189CONFIG_CPM=y
168 190
@@ -197,6 +219,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
197# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set 219# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
198CONFIG_PAGEFLAGS_EXTENDED=y 220CONFIG_PAGEFLAGS_EXTENDED=y
199CONFIG_SPLIT_PTLOCK_CPUS=4 221CONFIG_SPLIT_PTLOCK_CPUS=4
222CONFIG_MIGRATION=y
200# CONFIG_RESOURCES_64BIT is not set 223# CONFIG_RESOURCES_64BIT is not set
201CONFIG_ZONE_DMA_FLAG=1 224CONFIG_ZONE_DMA_FLAG=1
202CONFIG_BOUNCE=y 225CONFIG_BOUNCE=y
@@ -204,6 +227,7 @@ CONFIG_VIRT_TO_BUS=y
204CONFIG_FORCE_MAX_ZONEORDER=11 227CONFIG_FORCE_MAX_ZONEORDER=11
205CONFIG_PROC_DEVICETREE=y 228CONFIG_PROC_DEVICETREE=y
206# CONFIG_CMDLINE_BOOL is not set 229# CONFIG_CMDLINE_BOOL is not set
230CONFIG_EXTRA_TARGETS=""
207# CONFIG_PM is not set 231# CONFIG_PM is not set
208# CONFIG_SECCOMP is not set 232# CONFIG_SECCOMP is not set
209CONFIG_ISA_DMA_API=y 233CONFIG_ISA_DMA_API=y
@@ -211,13 +235,22 @@ CONFIG_ISA_DMA_API=y
211# 235#
212# Bus options 236# Bus options
213# 237#
238# CONFIG_ISA is not set
214CONFIG_ZONE_DMA=y 239CONFIG_ZONE_DMA=y
240CONFIG_PPC_INDIRECT_PCI=y
215CONFIG_FSL_SOC=y 241CONFIG_FSL_SOC=y
216# CONFIG_PCI is not set 242CONFIG_PPC_PCI_CHOICE=y
217# CONFIG_PCI_DOMAINS is not set 243CONFIG_PCI=y
218# CONFIG_PCI_SYSCALL is not set 244CONFIG_PCI_DOMAINS=y
219# CONFIG_ARCH_SUPPORTS_MSI is not set 245CONFIG_PCI_SYSCALL=y
246CONFIG_PCI_8260=y
247# CONFIG_PCIEPORTBUS is not set
248CONFIG_ARCH_SUPPORTS_MSI=y
249# CONFIG_PCI_MSI is not set
250CONFIG_PCI_LEGACY=y
251# CONFIG_PCI_DEBUG is not set
220# CONFIG_PCCARD is not set 252# CONFIG_PCCARD is not set
253# CONFIG_HOTPLUG_PCI is not set
221# CONFIG_HAS_RAPIDIO is not set 254# CONFIG_HAS_RAPIDIO is not set
222 255
223# 256#
@@ -233,10 +266,6 @@ CONFIG_PAGE_OFFSET=0xc0000000
233CONFIG_KERNEL_START=0xc0000000 266CONFIG_KERNEL_START=0xc0000000
234CONFIG_PHYSICAL_START=0x00000000 267CONFIG_PHYSICAL_START=0x00000000
235CONFIG_TASK_SIZE=0xc0000000 268CONFIG_TASK_SIZE=0xc0000000
236
237#
238# Networking
239#
240CONFIG_NET=y 269CONFIG_NET=y
241 270
242# 271#
@@ -410,11 +439,13 @@ CONFIG_MTD_CFI_UTIL=y
410# CONFIG_MTD_COMPLEX_MAPPINGS is not set 439# CONFIG_MTD_COMPLEX_MAPPINGS is not set
411# CONFIG_MTD_PHYSMAP is not set 440# CONFIG_MTD_PHYSMAP is not set
412CONFIG_MTD_PHYSMAP_OF=y 441CONFIG_MTD_PHYSMAP_OF=y
442# CONFIG_MTD_INTEL_VR_NOR is not set
413# CONFIG_MTD_PLATRAM is not set 443# CONFIG_MTD_PLATRAM is not set
414 444
415# 445#
416# Self-contained MTD device drivers 446# Self-contained MTD device drivers
417# 447#
448# CONFIG_MTD_PMC551 is not set
418# CONFIG_MTD_SLRAM is not set 449# CONFIG_MTD_SLRAM is not set
419# CONFIG_MTD_PHRAM is not set 450# CONFIG_MTD_PHRAM is not set
420# CONFIG_MTD_MTDRAM is not set 451# CONFIG_MTD_MTDRAM is not set
@@ -434,16 +465,23 @@ CONFIG_MTD_PHYSMAP_OF=y
434# 465#
435# CONFIG_MTD_UBI is not set 466# CONFIG_MTD_UBI is not set
436CONFIG_OF_DEVICE=y 467CONFIG_OF_DEVICE=y
468CONFIG_OF_GPIO=y
437# CONFIG_PARPORT is not set 469# CONFIG_PARPORT is not set
438CONFIG_BLK_DEV=y 470CONFIG_BLK_DEV=y
439# CONFIG_BLK_DEV_FD is not set 471# CONFIG_BLK_DEV_FD is not set
472# CONFIG_MAC_FLOPPY is not set
473# CONFIG_BLK_CPQ_DA is not set
474# CONFIG_BLK_CPQ_CISS_DA is not set
475# CONFIG_BLK_DEV_DAC960 is not set
440# CONFIG_BLK_DEV_COW_COMMON is not set 476# CONFIG_BLK_DEV_COW_COMMON is not set
441CONFIG_BLK_DEV_LOOP=y 477CONFIG_BLK_DEV_LOOP=y
442# CONFIG_BLK_DEV_CRYPTOLOOP is not set 478# CONFIG_BLK_DEV_CRYPTOLOOP is not set
443# CONFIG_BLK_DEV_NBD is not set 479# CONFIG_BLK_DEV_NBD is not set
480# CONFIG_BLK_DEV_SX8 is not set
444# CONFIG_BLK_DEV_RAM is not set 481# CONFIG_BLK_DEV_RAM is not set
445# CONFIG_CDROM_PKTCDVD is not set 482# CONFIG_CDROM_PKTCDVD is not set
446# CONFIG_ATA_OVER_ETH is not set 483# CONFIG_ATA_OVER_ETH is not set
484# CONFIG_BLK_DEV_HD is not set
447# CONFIG_MISC_DEVICES is not set 485# CONFIG_MISC_DEVICES is not set
448CONFIG_HAVE_IDE=y 486CONFIG_HAVE_IDE=y
449# CONFIG_IDE is not set 487# CONFIG_IDE is not set
@@ -457,14 +495,25 @@ CONFIG_HAVE_IDE=y
457# CONFIG_SCSI_NETLINK is not set 495# CONFIG_SCSI_NETLINK is not set
458# CONFIG_ATA is not set 496# CONFIG_ATA is not set
459# CONFIG_MD is not set 497# CONFIG_MD is not set
498# CONFIG_FUSION is not set
499
500#
501# IEEE 1394 (FireWire) support
502#
503
504#
505# A new alternative FireWire stack is available with EXPERIMENTAL=y
506#
507# CONFIG_IEEE1394 is not set
508# CONFIG_I2O is not set
460# CONFIG_MACINTOSH_DRIVERS is not set 509# CONFIG_MACINTOSH_DRIVERS is not set
461CONFIG_NETDEVICES=y 510CONFIG_NETDEVICES=y
462# CONFIG_NETDEVICES_MULTIQUEUE is not set
463# CONFIG_DUMMY is not set 511# CONFIG_DUMMY is not set
464# CONFIG_BONDING is not set 512# CONFIG_BONDING is not set
465# CONFIG_EQUALIZER is not set 513# CONFIG_EQUALIZER is not set
466# CONFIG_TUN is not set 514# CONFIG_TUN is not set
467# CONFIG_VETH is not set 515# CONFIG_VETH is not set
516# CONFIG_ARCNET is not set
468CONFIG_PHYLIB=y 517CONFIG_PHYLIB=y
469 518
470# 519#
@@ -482,21 +531,59 @@ CONFIG_DAVICOM_PHY=y
482# CONFIG_REALTEK_PHY is not set 531# CONFIG_REALTEK_PHY is not set
483# CONFIG_FIXED_PHY is not set 532# CONFIG_FIXED_PHY is not set
484CONFIG_MDIO_BITBANG=y 533CONFIG_MDIO_BITBANG=y
534# CONFIG_MDIO_OF_GPIO is not set
485CONFIG_NET_ETHERNET=y 535CONFIG_NET_ETHERNET=y
486CONFIG_MII=y 536CONFIG_MII=y
537# CONFIG_MACE is not set
538# CONFIG_BMAC is not set
539# CONFIG_HAPPYMEAL is not set
540# CONFIG_SUNGEM is not set
541# CONFIG_CASSINI is not set
542# CONFIG_NET_VENDOR_3COM is not set
543# CONFIG_NET_TULIP is not set
544# CONFIG_HP100 is not set
487# CONFIG_IBM_NEW_EMAC_ZMII is not set 545# CONFIG_IBM_NEW_EMAC_ZMII is not set
488# CONFIG_IBM_NEW_EMAC_RGMII is not set 546# CONFIG_IBM_NEW_EMAC_RGMII is not set
489# CONFIG_IBM_NEW_EMAC_TAH is not set 547# CONFIG_IBM_NEW_EMAC_TAH is not set
490# CONFIG_IBM_NEW_EMAC_EMAC4 is not set 548# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
549# CONFIG_NET_PCI is not set
491# CONFIG_B44 is not set 550# CONFIG_B44 is not set
492CONFIG_FS_ENET=y 551CONFIG_FS_ENET=y
493# CONFIG_FS_ENET_HAS_SCC is not set 552# CONFIG_FS_ENET_HAS_SCC is not set
494CONFIG_FS_ENET_HAS_FCC=y 553CONFIG_FS_ENET_HAS_FCC=y
495# CONFIG_FS_ENET_MDIO_FCC is not set 554# CONFIG_FS_ENET_MDIO_FCC is not set
496CONFIG_NETDEV_1000=y 555CONFIG_NETDEV_1000=y
497# CONFIG_E1000E_ENABLED is not set 556# CONFIG_ACENIC is not set
557# CONFIG_DL2K is not set
558# CONFIG_E1000 is not set
559# CONFIG_E1000E is not set
560# CONFIG_IGB is not set
561# CONFIG_NS83820 is not set
562# CONFIG_HAMACHI is not set
563# CONFIG_R8169 is not set
564# CONFIG_SIS190 is not set
565# CONFIG_SKGE is not set
566# CONFIG_SKY2 is not set
567# CONFIG_VIA_VELOCITY is not set
568# CONFIG_TIGON3 is not set
569# CONFIG_BNX2 is not set
498# CONFIG_GIANFAR is not set 570# CONFIG_GIANFAR is not set
571# CONFIG_MV643XX_ETH is not set
572# CONFIG_QLA3XXX is not set
499CONFIG_NETDEV_10000=y 573CONFIG_NETDEV_10000=y
574# CONFIG_CHELSIO_T1 is not set
575# CONFIG_CHELSIO_T3 is not set
576# CONFIG_IXGBE is not set
577# CONFIG_IXGB is not set
578# CONFIG_S2IO is not set
579# CONFIG_MYRI10GE is not set
580# CONFIG_NETXEN_NIC is not set
581# CONFIG_NIU is not set
582# CONFIG_MLX4_CORE is not set
583# CONFIG_TEHUTI is not set
584# CONFIG_BNX2X is not set
585# CONFIG_SFC is not set
586# CONFIG_TR is not set
500 587
501# 588#
502# Wireless LAN 589# Wireless LAN
@@ -505,6 +592,7 @@ CONFIG_NETDEV_10000=y
505# CONFIG_WLAN_80211 is not set 592# CONFIG_WLAN_80211 is not set
506# CONFIG_IWLWIFI_LEDS is not set 593# CONFIG_IWLWIFI_LEDS is not set
507# CONFIG_WAN is not set 594# CONFIG_WAN is not set
595# CONFIG_FDDI is not set
508# CONFIG_PPP is not set 596# CONFIG_PPP is not set
509# CONFIG_SLIP is not set 597# CONFIG_SLIP is not set
510# CONFIG_NETPOLL is not set 598# CONFIG_NETPOLL is not set
@@ -541,6 +629,7 @@ CONFIG_DEVKMEM=y
541# CONFIG_SERIAL_UARTLITE is not set 629# CONFIG_SERIAL_UARTLITE is not set
542CONFIG_SERIAL_CORE=y 630CONFIG_SERIAL_CORE=y
543CONFIG_SERIAL_CORE_CONSOLE=y 631CONFIG_SERIAL_CORE_CONSOLE=y
632# CONFIG_SERIAL_PMACZILOG is not set
544CONFIG_SERIAL_CPM=y 633CONFIG_SERIAL_CPM=y
545CONFIG_SERIAL_CPM_CONSOLE=y 634CONFIG_SERIAL_CPM_CONSOLE=y
546CONFIG_SERIAL_CPM_SCC1=y 635CONFIG_SERIAL_CPM_SCC1=y
@@ -549,21 +638,44 @@ CONFIG_SERIAL_CPM_SCC1=y
549CONFIG_SERIAL_CPM_SCC4=y 638CONFIG_SERIAL_CPM_SCC4=y
550# CONFIG_SERIAL_CPM_SMC1 is not set 639# CONFIG_SERIAL_CPM_SMC1 is not set
551# CONFIG_SERIAL_CPM_SMC2 is not set 640# CONFIG_SERIAL_CPM_SMC2 is not set
641# CONFIG_SERIAL_JSM is not set
552CONFIG_UNIX98_PTYS=y 642CONFIG_UNIX98_PTYS=y
553CONFIG_LEGACY_PTYS=y 643CONFIG_LEGACY_PTYS=y
554CONFIG_LEGACY_PTY_COUNT=256 644CONFIG_LEGACY_PTY_COUNT=256
645# CONFIG_BRIQ_PANEL is not set
646# CONFIG_HVC_RTAS is not set
555# CONFIG_IPMI_HANDLER is not set 647# CONFIG_IPMI_HANDLER is not set
556CONFIG_HW_RANDOM=y 648CONFIG_HW_RANDOM=y
557# CONFIG_NVRAM is not set 649# CONFIG_NVRAM is not set
558# CONFIG_GEN_RTC is not set 650# CONFIG_GEN_RTC is not set
559# CONFIG_R3964 is not set 651# CONFIG_R3964 is not set
652# CONFIG_APPLICOM is not set
560# CONFIG_RAW_DRIVER is not set 653# CONFIG_RAW_DRIVER is not set
654CONFIG_DEVPORT=y
561# CONFIG_I2C is not set 655# CONFIG_I2C is not set
562# CONFIG_SPI is not set 656# CONFIG_SPI is not set
657CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
658CONFIG_ARCH_REQUIRE_GPIOLIB=y
659CONFIG_GPIOLIB=y
660# CONFIG_DEBUG_GPIO is not set
661
662#
663# I2C GPIO expanders:
664#
665
666#
667# PCI GPIO expanders:
668#
669# CONFIG_GPIO_BT8XX is not set
670
671#
672# SPI GPIO expanders:
673#
563# CONFIG_W1 is not set 674# CONFIG_W1 is not set
564# CONFIG_POWER_SUPPLY is not set 675# CONFIG_POWER_SUPPLY is not set
565# CONFIG_HWMON is not set 676# CONFIG_HWMON is not set
566# CONFIG_THERMAL is not set 677# CONFIG_THERMAL is not set
678# CONFIG_THERMAL_HWMON is not set
567# CONFIG_WATCHDOG is not set 679# CONFIG_WATCHDOG is not set
568 680
569# 681#
@@ -575,8 +687,10 @@ CONFIG_SSB_POSSIBLE=y
575# 687#
576# Multifunction device drivers 688# Multifunction device drivers
577# 689#
690# CONFIG_MFD_CORE is not set
578# CONFIG_MFD_SM501 is not set 691# CONFIG_MFD_SM501 is not set
579# CONFIG_HTC_PASIC3 is not set 692# CONFIG_HTC_PASIC3 is not set
693# CONFIG_MFD_TMIO is not set
580 694
581# 695#
582# Multimedia devices 696# Multimedia devices
@@ -597,6 +711,8 @@ CONFIG_DAB=y
597# 711#
598# Graphics support 712# Graphics support
599# 713#
714# CONFIG_AGP is not set
715# CONFIG_DRM is not set
600# CONFIG_VGASTATE is not set 716# CONFIG_VGASTATE is not set
601# CONFIG_VIDEO_OUTPUT_CONTROL is not set 717# CONFIG_VIDEO_OUTPUT_CONTROL is not set
602# CONFIG_FB is not set 718# CONFIG_FB is not set
@@ -606,16 +722,13 @@ CONFIG_DAB=y
606# Display device support 722# Display device support
607# 723#
608# CONFIG_DISPLAY_SUPPORT is not set 724# CONFIG_DISPLAY_SUPPORT is not set
609
610#
611# Sound
612#
613# CONFIG_SOUND is not set 725# CONFIG_SOUND is not set
614# CONFIG_USB_SUPPORT is not set 726# CONFIG_USB_SUPPORT is not set
615# CONFIG_MMC is not set 727# CONFIG_MMC is not set
616# CONFIG_MEMSTICK is not set 728# CONFIG_MEMSTICK is not set
617# CONFIG_NEW_LEDS is not set 729# CONFIG_NEW_LEDS is not set
618# CONFIG_ACCESSIBILITY is not set 730# CONFIG_ACCESSIBILITY is not set
731# CONFIG_INFINIBAND is not set
619# CONFIG_RTC_CLASS is not set 732# CONFIG_RTC_CLASS is not set
620# CONFIG_DMADEVICES is not set 733# CONFIG_DMADEVICES is not set
621# CONFIG_UIO is not set 734# CONFIG_UIO is not set
@@ -675,6 +788,7 @@ CONFIG_TMPFS=y
675CONFIG_CRAMFS=y 788CONFIG_CRAMFS=y
676# CONFIG_VXFS_FS is not set 789# CONFIG_VXFS_FS is not set
677# CONFIG_MINIX_FS is not set 790# CONFIG_MINIX_FS is not set
791# CONFIG_OMFS_FS is not set
678# CONFIG_HPFS_FS is not set 792# CONFIG_HPFS_FS is not set
679# CONFIG_QNX4FS_FS is not set 793# CONFIG_QNX4FS_FS is not set
680# CONFIG_ROMFS_FS is not set 794# CONFIG_ROMFS_FS is not set
@@ -684,8 +798,8 @@ CONFIG_NETWORK_FILESYSTEMS=y
684CONFIG_NFS_FS=y 798CONFIG_NFS_FS=y
685CONFIG_NFS_V3=y 799CONFIG_NFS_V3=y
686# CONFIG_NFS_V3_ACL is not set 800# CONFIG_NFS_V3_ACL is not set
687# CONFIG_NFSD is not set
688CONFIG_ROOT_NFS=y 801CONFIG_ROOT_NFS=y
802# CONFIG_NFSD is not set
689CONFIG_LOCKD=y 803CONFIG_LOCKD=y
690CONFIG_LOCKD_V4=y 804CONFIG_LOCKD_V4=y
691CONFIG_NFS_COMMON=y 805CONFIG_NFS_COMMON=y
@@ -763,6 +877,7 @@ CONFIG_NLS_UTF8=y
763# CONFIG_GENERIC_FIND_FIRST_BIT is not set 877# CONFIG_GENERIC_FIND_FIRST_BIT is not set
764# CONFIG_CRC_CCITT is not set 878# CONFIG_CRC_CCITT is not set
765# CONFIG_CRC16 is not set 879# CONFIG_CRC16 is not set
880# CONFIG_CRC_T10DIF is not set
766# CONFIG_CRC_ITU_T is not set 881# CONFIG_CRC_ITU_T is not set
767# CONFIG_CRC32 is not set 882# CONFIG_CRC32 is not set
768# CONFIG_CRC7 is not set 883# CONFIG_CRC7 is not set
@@ -804,19 +919,31 @@ CONFIG_DEBUG_BUGVERBOSE=y
804CONFIG_DEBUG_INFO=y 919CONFIG_DEBUG_INFO=y
805# CONFIG_DEBUG_VM is not set 920# CONFIG_DEBUG_VM is not set
806# CONFIG_DEBUG_WRITECOUNT is not set 921# CONFIG_DEBUG_WRITECOUNT is not set
922# CONFIG_DEBUG_MEMORY_INIT is not set
807# CONFIG_DEBUG_LIST is not set 923# CONFIG_DEBUG_LIST is not set
808# CONFIG_DEBUG_SG is not set 924# CONFIG_DEBUG_SG is not set
809# CONFIG_BOOT_PRINTK_DELAY is not set 925# CONFIG_BOOT_PRINTK_DELAY is not set
926# CONFIG_RCU_TORTURE_TEST is not set
810# CONFIG_BACKTRACE_SELF_TEST is not set 927# CONFIG_BACKTRACE_SELF_TEST is not set
811# CONFIG_FAULT_INJECTION is not set 928# CONFIG_FAULT_INJECTION is not set
929# CONFIG_LATENCYTOP is not set
930CONFIG_SYSCTL_SYSCALL_CHECK=y
931CONFIG_HAVE_FTRACE=y
932CONFIG_HAVE_DYNAMIC_FTRACE=y
933# CONFIG_FTRACE is not set
934# CONFIG_SCHED_TRACER is not set
935# CONFIG_CONTEXT_SWITCH_TRACER is not set
812# CONFIG_SAMPLES is not set 936# CONFIG_SAMPLES is not set
937CONFIG_HAVE_ARCH_KGDB=y
813# CONFIG_DEBUG_STACKOVERFLOW is not set 938# CONFIG_DEBUG_STACKOVERFLOW is not set
814# CONFIG_DEBUG_STACK_USAGE is not set 939# CONFIG_DEBUG_STACK_USAGE is not set
815# CONFIG_DEBUG_PAGEALLOC is not set 940# CONFIG_DEBUG_PAGEALLOC is not set
816# CONFIG_DEBUGGER is not set 941# CONFIG_CODE_PATCHING_SELFTEST is not set
817# CONFIG_KGDB_CONSOLE is not set 942# CONFIG_FTR_FIXUP_SELFTEST is not set
943# CONFIG_XMON is not set
818# CONFIG_IRQSTACKS is not set 944# CONFIG_IRQSTACKS is not set
819CONFIG_BDI_SWITCH=y 945CONFIG_BDI_SWITCH=y
946# CONFIG_BOOTX_TEXT is not set
820# CONFIG_PPC_EARLY_DEBUG is not set 947# CONFIG_PPC_EARLY_DEBUG is not set
821 948
822# 949#
@@ -824,6 +951,7 @@ CONFIG_BDI_SWITCH=y
824# 951#
825# CONFIG_KEYS is not set 952# CONFIG_KEYS is not set
826# CONFIG_SECURITY is not set 953# CONFIG_SECURITY is not set
954# CONFIG_SECURITY_FILE_CAPABILITIES is not set
827CONFIG_CRYPTO=y 955CONFIG_CRYPTO=y
828 956
829# 957#
@@ -864,6 +992,10 @@ CONFIG_CRYPTO_PCBC=y
864# CONFIG_CRYPTO_MD4 is not set 992# CONFIG_CRYPTO_MD4 is not set
865CONFIG_CRYPTO_MD5=y 993CONFIG_CRYPTO_MD5=y
866# CONFIG_CRYPTO_MICHAEL_MIC is not set 994# CONFIG_CRYPTO_MICHAEL_MIC is not set
995# CONFIG_CRYPTO_RMD128 is not set
996# CONFIG_CRYPTO_RMD160 is not set
997# CONFIG_CRYPTO_RMD256 is not set
998# CONFIG_CRYPTO_RMD320 is not set
867# CONFIG_CRYPTO_SHA1 is not set 999# CONFIG_CRYPTO_SHA1 is not set
868# CONFIG_CRYPTO_SHA256 is not set 1000# CONFIG_CRYPTO_SHA256 is not set
869# CONFIG_CRYPTO_SHA512 is not set 1001# CONFIG_CRYPTO_SHA512 is not set
@@ -894,6 +1026,6 @@ CONFIG_CRYPTO_DES=y
894# CONFIG_CRYPTO_DEFLATE is not set 1026# CONFIG_CRYPTO_DEFLATE is not set
895# CONFIG_CRYPTO_LZO is not set 1027# CONFIG_CRYPTO_LZO is not set
896# CONFIG_CRYPTO_HW is not set 1028# CONFIG_CRYPTO_HW is not set
897# CONFIG_PPC_CLOCK is not set 1029CONFIG_PPC_CLOCK=y
898CONFIG_PPC_LIB_RHEAP=y 1030CONFIG_PPC_LIB_RHEAP=y
899# CONFIG_VIRTUALIZATION is not set 1031# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/configs/ep88xc_defconfig b/arch/powerpc/configs/ep88xc_defconfig
index ac72b48542dc..480225be2f39 100644
--- a/arch/powerpc/configs/ep88xc_defconfig
+++ b/arch/powerpc/configs/ep88xc_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc5 3# Linux kernel version: 2.6.27-rc4
4# Mon Jun 9 08:52:09 2008 4# Thu Aug 21 00:52:04 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -29,6 +29,7 @@ CONFIG_GENERIC_HARDIRQS=y
29# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set 29# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
30CONFIG_IRQ_PER_CPU=y 30CONFIG_IRQ_PER_CPU=y
31CONFIG_STACKTRACE_SUPPORT=y 31CONFIG_STACKTRACE_SUPPORT=y
32CONFIG_HAVE_LATENCYTOP_SUPPORT=y
32CONFIG_LOCKDEP_SUPPORT=y 33CONFIG_LOCKDEP_SUPPORT=y
33CONFIG_RWSEM_XCHGADD_ALGORITHM=y 34CONFIG_RWSEM_XCHGADD_ALGORITHM=y
34CONFIG_ARCH_HAS_ILOG2_U32=y 35CONFIG_ARCH_HAS_ILOG2_U32=y
@@ -108,10 +109,16 @@ CONFIG_SLUB=y
108# CONFIG_PROFILING is not set 109# CONFIG_PROFILING is not set
109# CONFIG_MARKERS is not set 110# CONFIG_MARKERS is not set
110CONFIG_HAVE_OPROFILE=y 111CONFIG_HAVE_OPROFILE=y
112CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
113CONFIG_HAVE_IOREMAP_PROT=y
111CONFIG_HAVE_KPROBES=y 114CONFIG_HAVE_KPROBES=y
112CONFIG_HAVE_KRETPROBES=y 115CONFIG_HAVE_KRETPROBES=y
116CONFIG_HAVE_ARCH_TRACEHOOK=y
113# CONFIG_HAVE_DMA_ATTRS is not set 117# CONFIG_HAVE_DMA_ATTRS is not set
118# CONFIG_USE_GENERIC_SMP_HELPERS is not set
119CONFIG_HAVE_CLK=y
114CONFIG_PROC_PAGE_MONITOR=y 120CONFIG_PROC_PAGE_MONITOR=y
121# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
115CONFIG_SLABINFO=y 122CONFIG_SLABINFO=y
116# CONFIG_TINY_SHMEM is not set 123# CONFIG_TINY_SHMEM is not set
117CONFIG_BASE_SMALL=1 124CONFIG_BASE_SMALL=1
@@ -121,6 +128,7 @@ CONFIG_BLOCK=y
121# CONFIG_BLK_DEV_IO_TRACE is not set 128# CONFIG_BLK_DEV_IO_TRACE is not set
122# CONFIG_LSF is not set 129# CONFIG_LSF is not set
123# CONFIG_BLK_DEV_BSG is not set 130# CONFIG_BLK_DEV_BSG is not set
131# CONFIG_BLK_DEV_INTEGRITY is not set
124 132
125# 133#
126# IO Schedulers 134# IO Schedulers
@@ -139,8 +147,6 @@ CONFIG_CLASSIC_RCU=y
139# 147#
140# Platform support 148# Platform support
141# 149#
142# CONFIG_PPC_MPC512x is not set
143# CONFIG_PPC_MPC5121 is not set
144# CONFIG_PPC_CELL is not set 150# CONFIG_PPC_CELL is not set
145# CONFIG_PPC_CELL_NATIVE is not set 151# CONFIG_PPC_CELL_NATIVE is not set
146CONFIG_CPM1=y 152CONFIG_CPM1=y
@@ -158,6 +164,7 @@ CONFIG_PPC_EP88XC=y
158# Generic MPC8xx Options 164# Generic MPC8xx Options
159# 165#
160CONFIG_8xx_COPYBACK=y 166CONFIG_8xx_COPYBACK=y
167# CONFIG_8xx_GPIO is not set
161# CONFIG_8xx_CPU6 is not set 168# CONFIG_8xx_CPU6 is not set
162CONFIG_8xx_CPU15=y 169CONFIG_8xx_CPU15=y
163CONFIG_NO_UCODE_PATCH=y 170CONFIG_NO_UCODE_PATCH=y
@@ -176,7 +183,6 @@ CONFIG_NO_UCODE_PATCH=y
176# CONFIG_PPC_INDIRECT_IO is not set 183# CONFIG_PPC_INDIRECT_IO is not set
177# CONFIG_GENERIC_IOMAP is not set 184# CONFIG_GENERIC_IOMAP is not set
178# CONFIG_CPU_FREQ is not set 185# CONFIG_CPU_FREQ is not set
179CONFIG_PPC_CPM_NEW_BINDING=y
180# CONFIG_FSL_ULI1575 is not set 186# CONFIG_FSL_ULI1575 is not set
181CONFIG_CPM=y 187CONFIG_CPM=y
182 188
@@ -193,7 +199,7 @@ CONFIG_HZ_100=y
193# CONFIG_HZ_300 is not set 199# CONFIG_HZ_300 is not set
194# CONFIG_HZ_1000 is not set 200# CONFIG_HZ_1000 is not set
195CONFIG_HZ=100 201CONFIG_HZ=100
196# CONFIG_SCHED_HRTICK is not set 202CONFIG_SCHED_HRTICK=y
197CONFIG_PREEMPT_NONE=y 203CONFIG_PREEMPT_NONE=y
198# CONFIG_PREEMPT_VOLUNTARY is not set 204# CONFIG_PREEMPT_VOLUNTARY is not set
199# CONFIG_PREEMPT is not set 205# CONFIG_PREEMPT is not set
@@ -217,6 +223,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
217# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set 223# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
218CONFIG_PAGEFLAGS_EXTENDED=y 224CONFIG_PAGEFLAGS_EXTENDED=y
219CONFIG_SPLIT_PTLOCK_CPUS=4 225CONFIG_SPLIT_PTLOCK_CPUS=4
226CONFIG_MIGRATION=y
220# CONFIG_RESOURCES_64BIT is not set 227# CONFIG_RESOURCES_64BIT is not set
221CONFIG_ZONE_DMA_FLAG=1 228CONFIG_ZONE_DMA_FLAG=1
222CONFIG_BOUNCE=y 229CONFIG_BOUNCE=y
@@ -224,6 +231,7 @@ CONFIG_VIRT_TO_BUS=y
224CONFIG_FORCE_MAX_ZONEORDER=11 231CONFIG_FORCE_MAX_ZONEORDER=11
225CONFIG_PROC_DEVICETREE=y 232CONFIG_PROC_DEVICETREE=y
226# CONFIG_CMDLINE_BOOL is not set 233# CONFIG_CMDLINE_BOOL is not set
234CONFIG_EXTRA_TARGETS=""
227# CONFIG_PM is not set 235# CONFIG_PM is not set
228# CONFIG_SECCOMP is not set 236# CONFIG_SECCOMP is not set
229CONFIG_ISA_DMA_API=y 237CONFIG_ISA_DMA_API=y
@@ -256,10 +264,6 @@ CONFIG_PHYSICAL_START=0x00000000
256CONFIG_TASK_SIZE=0x80000000 264CONFIG_TASK_SIZE=0x80000000
257CONFIG_CONSISTENT_START=0xfd000000 265CONFIG_CONSISTENT_START=0xfd000000
258CONFIG_CONSISTENT_SIZE=0x00200000 266CONFIG_CONSISTENT_SIZE=0x00200000
259
260#
261# Networking
262#
263CONFIG_NET=y 267CONFIG_NET=y
264 268
265# 269#
@@ -442,7 +446,6 @@ CONFIG_HAVE_IDE=y
442# CONFIG_MD is not set 446# CONFIG_MD is not set
443# CONFIG_MACINTOSH_DRIVERS is not set 447# CONFIG_MACINTOSH_DRIVERS is not set
444CONFIG_NETDEVICES=y 448CONFIG_NETDEVICES=y
445# CONFIG_NETDEVICES_MULTIQUEUE is not set
446# CONFIG_DUMMY is not set 449# CONFIG_DUMMY is not set
447# CONFIG_BONDING is not set 450# CONFIG_BONDING is not set
448# CONFIG_MACVLAN is not set 451# CONFIG_MACVLAN is not set
@@ -544,10 +547,13 @@ CONFIG_GEN_RTC=y
544# CONFIG_TCG_TPM is not set 547# CONFIG_TCG_TPM is not set
545# CONFIG_I2C is not set 548# CONFIG_I2C is not set
546# CONFIG_SPI is not set 549# CONFIG_SPI is not set
550CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
551# CONFIG_GPIOLIB is not set
547# CONFIG_W1 is not set 552# CONFIG_W1 is not set
548# CONFIG_POWER_SUPPLY is not set 553# CONFIG_POWER_SUPPLY is not set
549# CONFIG_HWMON is not set 554# CONFIG_HWMON is not set
550# CONFIG_THERMAL is not set 555# CONFIG_THERMAL is not set
556# CONFIG_THERMAL_HWMON is not set
551# CONFIG_WATCHDOG is not set 557# CONFIG_WATCHDOG is not set
552 558
553# 559#
@@ -559,8 +565,10 @@ CONFIG_SSB_POSSIBLE=y
559# 565#
560# Multifunction device drivers 566# Multifunction device drivers
561# 567#
568# CONFIG_MFD_CORE is not set
562# CONFIG_MFD_SM501 is not set 569# CONFIG_MFD_SM501 is not set
563# CONFIG_HTC_PASIC3 is not set 570# CONFIG_HTC_PASIC3 is not set
571# CONFIG_MFD_TMIO is not set
564 572
565# 573#
566# Multimedia devices 574# Multimedia devices
@@ -590,10 +598,6 @@ CONFIG_DAB=y
590# Display device support 598# Display device support
591# 599#
592# CONFIG_DISPLAY_SUPPORT is not set 600# CONFIG_DISPLAY_SUPPORT is not set
593
594#
595# Sound
596#
597# CONFIG_SOUND is not set 601# CONFIG_SOUND is not set
598# CONFIG_USB_SUPPORT is not set 602# CONFIG_USB_SUPPORT is not set
599# CONFIG_MMC is not set 603# CONFIG_MMC is not set
@@ -662,6 +666,7 @@ CONFIG_TMPFS=y
662CONFIG_CRAMFS=y 666CONFIG_CRAMFS=y
663# CONFIG_VXFS_FS is not set 667# CONFIG_VXFS_FS is not set
664# CONFIG_MINIX_FS is not set 668# CONFIG_MINIX_FS is not set
669# CONFIG_OMFS_FS is not set
665# CONFIG_HPFS_FS is not set 670# CONFIG_HPFS_FS is not set
666# CONFIG_QNX4FS_FS is not set 671# CONFIG_QNX4FS_FS is not set
667# CONFIG_ROMFS_FS is not set 672# CONFIG_ROMFS_FS is not set
@@ -672,13 +677,12 @@ CONFIG_NFS_FS=y
672CONFIG_NFS_V3=y 677CONFIG_NFS_V3=y
673# CONFIG_NFS_V3_ACL is not set 678# CONFIG_NFS_V3_ACL is not set
674# CONFIG_NFS_V4 is not set 679# CONFIG_NFS_V4 is not set
675# CONFIG_NFSD is not set
676CONFIG_ROOT_NFS=y 680CONFIG_ROOT_NFS=y
681# CONFIG_NFSD is not set
677CONFIG_LOCKD=y 682CONFIG_LOCKD=y
678CONFIG_LOCKD_V4=y 683CONFIG_LOCKD_V4=y
679CONFIG_NFS_COMMON=y 684CONFIG_NFS_COMMON=y
680CONFIG_SUNRPC=y 685CONFIG_SUNRPC=y
681# CONFIG_SUNRPC_BIND34 is not set
682# CONFIG_RPCSEC_GSS_KRB5 is not set 686# CONFIG_RPCSEC_GSS_KRB5 is not set
683# CONFIG_RPCSEC_GSS_SPKM3 is not set 687# CONFIG_RPCSEC_GSS_SPKM3 is not set
684# CONFIG_SMB_FS is not set 688# CONFIG_SMB_FS is not set
@@ -717,6 +721,7 @@ CONFIG_MSDOS_PARTITION=y
717# CONFIG_GENERIC_FIND_FIRST_BIT is not set 721# CONFIG_GENERIC_FIND_FIRST_BIT is not set
718# CONFIG_CRC_CCITT is not set 722# CONFIG_CRC_CCITT is not set
719# CONFIG_CRC16 is not set 723# CONFIG_CRC16 is not set
724# CONFIG_CRC_T10DIF is not set
720# CONFIG_CRC_ITU_T is not set 725# CONFIG_CRC_ITU_T is not set
721# CONFIG_CRC32 is not set 726# CONFIG_CRC32 is not set
722# CONFIG_CRC7 is not set 727# CONFIG_CRC7 is not set
@@ -741,6 +746,8 @@ CONFIG_MAGIC_SYSRQ=y
741CONFIG_DEBUG_KERNEL=y 746CONFIG_DEBUG_KERNEL=y
742# CONFIG_DEBUG_SHIRQ is not set 747# CONFIG_DEBUG_SHIRQ is not set
743CONFIG_DETECT_SOFTLOCKUP=y 748CONFIG_DETECT_SOFTLOCKUP=y
749# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
750CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
744CONFIG_SCHED_DEBUG=y 751CONFIG_SCHED_DEBUG=y
745# CONFIG_SCHEDSTATS is not set 752# CONFIG_SCHEDSTATS is not set
746# CONFIG_TIMER_STATS is not set 753# CONFIG_TIMER_STATS is not set
@@ -756,16 +763,28 @@ CONFIG_DEBUG_BUGVERBOSE=y
756CONFIG_DEBUG_INFO=y 763CONFIG_DEBUG_INFO=y
757# CONFIG_DEBUG_VM is not set 764# CONFIG_DEBUG_VM is not set
758# CONFIG_DEBUG_WRITECOUNT is not set 765# CONFIG_DEBUG_WRITECOUNT is not set
766# CONFIG_DEBUG_MEMORY_INIT is not set
759# CONFIG_DEBUG_LIST is not set 767# CONFIG_DEBUG_LIST is not set
760# CONFIG_DEBUG_SG is not set 768# CONFIG_DEBUG_SG is not set
761# CONFIG_BOOT_PRINTK_DELAY is not set 769# CONFIG_BOOT_PRINTK_DELAY is not set
770# CONFIG_RCU_TORTURE_TEST is not set
762# CONFIG_BACKTRACE_SELF_TEST is not set 771# CONFIG_BACKTRACE_SELF_TEST is not set
763# CONFIG_FAULT_INJECTION is not set 772# CONFIG_FAULT_INJECTION is not set
773# CONFIG_LATENCYTOP is not set
774CONFIG_HAVE_FTRACE=y
775CONFIG_HAVE_DYNAMIC_FTRACE=y
776# CONFIG_FTRACE is not set
777# CONFIG_SCHED_TRACER is not set
778# CONFIG_CONTEXT_SWITCH_TRACER is not set
764# CONFIG_SAMPLES is not set 779# CONFIG_SAMPLES is not set
780CONFIG_HAVE_ARCH_KGDB=y
781# CONFIG_KGDB is not set
765# CONFIG_DEBUG_STACKOVERFLOW is not set 782# CONFIG_DEBUG_STACKOVERFLOW is not set
766# CONFIG_DEBUG_STACK_USAGE is not set 783# CONFIG_DEBUG_STACK_USAGE is not set
767# CONFIG_DEBUG_PAGEALLOC is not set 784# CONFIG_DEBUG_PAGEALLOC is not set
768# CONFIG_DEBUGGER is not set 785# CONFIG_CODE_PATCHING_SELFTEST is not set
786# CONFIG_FTR_FIXUP_SELFTEST is not set
787# CONFIG_XMON is not set
769# CONFIG_IRQSTACKS is not set 788# CONFIG_IRQSTACKS is not set
770# CONFIG_BDI_SWITCH is not set 789# CONFIG_BDI_SWITCH is not set
771# CONFIG_PPC_EARLY_DEBUG is not set 790# CONFIG_PPC_EARLY_DEBUG is not set
@@ -777,6 +796,6 @@ CONFIG_DEBUG_INFO=y
777# CONFIG_SECURITY is not set 796# CONFIG_SECURITY is not set
778# CONFIG_SECURITY_FILE_CAPABILITIES is not set 797# CONFIG_SECURITY_FILE_CAPABILITIES is not set
779# CONFIG_CRYPTO is not set 798# CONFIG_CRYPTO is not set
780# CONFIG_PPC_CLOCK is not set 799CONFIG_PPC_CLOCK=y
781CONFIG_PPC_LIB_RHEAP=y 800CONFIG_PPC_LIB_RHEAP=y
782# CONFIG_VIRTUALIZATION is not set 801# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/configs/g5_defconfig b/arch/powerpc/configs/g5_defconfig
index 0ccc6e493dcb..cfa5d053ee5e 100644
--- a/arch/powerpc/configs/g5_defconfig
+++ b/arch/powerpc/configs/g5_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc6 3# Linux kernel version: 2.6.27-rc4
4# Mon Jun 16 21:08:31 2008 4# Tue Aug 26 13:15:06 2008
5# 5#
6CONFIG_PPC64=y 6CONFIG_PPC64=y
7 7
@@ -13,6 +13,7 @@ CONFIG_POWER4=y
13# CONFIG_TUNE_CELL is not set 13# CONFIG_TUNE_CELL is not set
14CONFIG_PPC_FPU=y 14CONFIG_PPC_FPU=y
15CONFIG_ALTIVEC=y 15CONFIG_ALTIVEC=y
16# CONFIG_VSX is not set
16CONFIG_PPC_STD_MMU=y 17CONFIG_PPC_STD_MMU=y
17CONFIG_PPC_MM_SLICES=y 18CONFIG_PPC_MM_SLICES=y
18CONFIG_VIRT_CPU_ACCOUNTING=y 19CONFIG_VIRT_CPU_ACCOUNTING=y
@@ -30,6 +31,7 @@ CONFIG_GENERIC_HARDIRQS=y
30CONFIG_HAVE_SETUP_PER_CPU_AREA=y 31CONFIG_HAVE_SETUP_PER_CPU_AREA=y
31CONFIG_IRQ_PER_CPU=y 32CONFIG_IRQ_PER_CPU=y
32CONFIG_STACKTRACE_SUPPORT=y 33CONFIG_STACKTRACE_SUPPORT=y
34CONFIG_HAVE_LATENCYTOP_SUPPORT=y
33CONFIG_TRACE_IRQFLAGS_SUPPORT=y 35CONFIG_TRACE_IRQFLAGS_SUPPORT=y
34CONFIG_LOCKDEP_SUPPORT=y 36CONFIG_LOCKDEP_SUPPORT=y
35CONFIG_RWSEM_XCHGADD_ALGORITHM=y 37CONFIG_RWSEM_XCHGADD_ALGORITHM=y
@@ -94,9 +96,8 @@ CONFIG_CC_OPTIMIZE_FOR_SIZE=y
94CONFIG_SYSCTL=y 96CONFIG_SYSCTL=y
95# CONFIG_EMBEDDED is not set 97# CONFIG_EMBEDDED is not set
96CONFIG_SYSCTL_SYSCALL=y 98CONFIG_SYSCTL_SYSCALL=y
97CONFIG_SYSCTL_SYSCALL_CHECK=y
98CONFIG_KALLSYMS=y 99CONFIG_KALLSYMS=y
99# CONFIG_KALLSYMS_ALL is not set 100CONFIG_KALLSYMS_ALL=y
100# CONFIG_KALLSYMS_EXTRA_PASS is not set 101# CONFIG_KALLSYMS_EXTRA_PASS is not set
101CONFIG_HOTPLUG=y 102CONFIG_HOTPLUG=y
102CONFIG_PRINTK=y 103CONFIG_PRINTK=y
@@ -121,10 +122,16 @@ CONFIG_PROFILING=y
121CONFIG_OPROFILE=y 122CONFIG_OPROFILE=y
122CONFIG_HAVE_OPROFILE=y 123CONFIG_HAVE_OPROFILE=y
123# CONFIG_KPROBES is not set 124# CONFIG_KPROBES is not set
125CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
126CONFIG_HAVE_IOREMAP_PROT=y
124CONFIG_HAVE_KPROBES=y 127CONFIG_HAVE_KPROBES=y
125CONFIG_HAVE_KRETPROBES=y 128CONFIG_HAVE_KRETPROBES=y
126# CONFIG_HAVE_DMA_ATTRS is not set 129CONFIG_HAVE_ARCH_TRACEHOOK=y
130CONFIG_HAVE_DMA_ATTRS=y
131CONFIG_USE_GENERIC_SMP_HELPERS=y
132# CONFIG_HAVE_CLK is not set
127CONFIG_PROC_PAGE_MONITOR=y 133CONFIG_PROC_PAGE_MONITOR=y
134# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
128CONFIG_SLABINFO=y 135CONFIG_SLABINFO=y
129CONFIG_RT_MUTEXES=y 136CONFIG_RT_MUTEXES=y
130# CONFIG_TINY_SHMEM is not set 137# CONFIG_TINY_SHMEM is not set
@@ -140,6 +147,7 @@ CONFIG_STOP_MACHINE=y
140CONFIG_BLOCK=y 147CONFIG_BLOCK=y
141# CONFIG_BLK_DEV_IO_TRACE is not set 148# CONFIG_BLK_DEV_IO_TRACE is not set
142CONFIG_BLK_DEV_BSG=y 149CONFIG_BLK_DEV_BSG=y
150# CONFIG_BLK_DEV_INTEGRITY is not set
143CONFIG_BLOCK_COMPAT=y 151CONFIG_BLOCK_COMPAT=y
144 152
145# 153#
@@ -160,13 +168,8 @@ CONFIG_CLASSIC_RCU=y
160# Platform support 168# Platform support
161# 169#
162CONFIG_PPC_MULTIPLATFORM=y 170CONFIG_PPC_MULTIPLATFORM=y
163# CONFIG_PPC_82xx is not set
164# CONFIG_PPC_83xx is not set
165# CONFIG_PPC_86xx is not set
166# CONFIG_PPC_PSERIES is not set 171# CONFIG_PPC_PSERIES is not set
167# CONFIG_PPC_ISERIES is not set 172# CONFIG_PPC_ISERIES is not set
168# CONFIG_PPC_MPC512x is not set
169# CONFIG_PPC_MPC5121 is not set
170CONFIG_PPC_PMAC=y 173CONFIG_PPC_PMAC=y
171CONFIG_PPC_PMAC64=y 174CONFIG_PPC_PMAC64=y
172# CONFIG_PPC_MAPLE is not set 175# CONFIG_PPC_MAPLE is not set
@@ -224,7 +227,7 @@ CONFIG_HZ_250=y
224# CONFIG_HZ_300 is not set 227# CONFIG_HZ_300 is not set
225# CONFIG_HZ_1000 is not set 228# CONFIG_HZ_1000 is not set
226CONFIG_HZ=250 229CONFIG_HZ=250
227# CONFIG_SCHED_HRTICK is not set 230CONFIG_SCHED_HRTICK=y
228CONFIG_PREEMPT_NONE=y 231CONFIG_PREEMPT_NONE=y
229# CONFIG_PREEMPT_VOLUNTARY is not set 232# CONFIG_PREEMPT_VOLUNTARY is not set
230# CONFIG_PREEMPT is not set 233# CONFIG_PREEMPT is not set
@@ -256,6 +259,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
256CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y 259CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
257CONFIG_PAGEFLAGS_EXTENDED=y 260CONFIG_PAGEFLAGS_EXTENDED=y
258CONFIG_SPLIT_PTLOCK_CPUS=4 261CONFIG_SPLIT_PTLOCK_CPUS=4
262# CONFIG_MIGRATION is not set
259CONFIG_RESOURCES_64BIT=y 263CONFIG_RESOURCES_64BIT=y
260CONFIG_ZONE_DMA_FLAG=1 264CONFIG_ZONE_DMA_FLAG=1
261CONFIG_BOUNCE=y 265CONFIG_BOUNCE=y
@@ -265,6 +269,7 @@ CONFIG_FORCE_MAX_ZONEORDER=13
265# CONFIG_SCHED_SMT is not set 269# CONFIG_SCHED_SMT is not set
266CONFIG_PROC_DEVICETREE=y 270CONFIG_PROC_DEVICETREE=y
267# CONFIG_CMDLINE_BOOL is not set 271# CONFIG_CMDLINE_BOOL is not set
272CONFIG_EXTRA_TARGETS=""
268CONFIG_ARCH_WANTS_FREEZER_CONTROL=y 273CONFIG_ARCH_WANTS_FREEZER_CONTROL=y
269# CONFIG_PM is not set 274# CONFIG_PM is not set
270CONFIG_SECCOMP=y 275CONFIG_SECCOMP=y
@@ -290,10 +295,6 @@ CONFIG_PCI_MSI=y
290CONFIG_PAGE_OFFSET=0xc000000000000000 295CONFIG_PAGE_OFFSET=0xc000000000000000
291CONFIG_KERNEL_START=0xc000000000000000 296CONFIG_KERNEL_START=0xc000000000000000
292CONFIG_PHYSICAL_START=0x00000000 297CONFIG_PHYSICAL_START=0x00000000
293
294#
295# Networking
296#
297CONFIG_NET=y 298CONFIG_NET=y
298 299
299# 300#
@@ -307,6 +308,7 @@ CONFIG_XFRM_USER=m
307# CONFIG_XFRM_SUB_POLICY is not set 308# CONFIG_XFRM_SUB_POLICY is not set
308# CONFIG_XFRM_MIGRATE is not set 309# CONFIG_XFRM_MIGRATE is not set
309# CONFIG_XFRM_STATISTICS is not set 310# CONFIG_XFRM_STATISTICS is not set
311CONFIG_XFRM_IPCOMP=m
310CONFIG_NET_KEY=m 312CONFIG_NET_KEY=m
311# CONFIG_NET_KEY_MIGRATE is not set 313# CONFIG_NET_KEY_MIGRATE is not set
312CONFIG_INET=y 314CONFIG_INET=y
@@ -422,6 +424,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
422CONFIG_STANDALONE=y 424CONFIG_STANDALONE=y
423CONFIG_PREVENT_FIRMWARE_BUILD=y 425CONFIG_PREVENT_FIRMWARE_BUILD=y
424CONFIG_FW_LOADER=y 426CONFIG_FW_LOADER=y
427CONFIG_FIRMWARE_IN_KERNEL=y
428CONFIG_EXTRA_FIRMWARE=""
425# CONFIG_DEBUG_DRIVER is not set 429# CONFIG_DEBUG_DRIVER is not set
426# CONFIG_DEBUG_DEVRES is not set 430# CONFIG_DEBUG_DEVRES is not set
427# CONFIG_SYS_HYPERVISOR is not set 431# CONFIG_SYS_HYPERVISOR is not set
@@ -449,12 +453,14 @@ CONFIG_CDROM_PKTCDVD=m
449CONFIG_CDROM_PKTCDVD_BUFFERS=8 453CONFIG_CDROM_PKTCDVD_BUFFERS=8
450# CONFIG_CDROM_PKTCDVD_WCACHE is not set 454# CONFIG_CDROM_PKTCDVD_WCACHE is not set
451# CONFIG_ATA_OVER_ETH is not set 455# CONFIG_ATA_OVER_ETH is not set
456# CONFIG_BLK_DEV_HD is not set
452CONFIG_MISC_DEVICES=y 457CONFIG_MISC_DEVICES=y
453# CONFIG_PHANTOM is not set 458# CONFIG_PHANTOM is not set
454# CONFIG_EEPROM_93CX6 is not set 459# CONFIG_EEPROM_93CX6 is not set
455# CONFIG_SGI_IOC4 is not set 460# CONFIG_SGI_IOC4 is not set
456# CONFIG_TIFM_CORE is not set 461# CONFIG_TIFM_CORE is not set
457# CONFIG_ENCLOSURE_SERVICES is not set 462# CONFIG_ENCLOSURE_SERVICES is not set
463# CONFIG_HP_ILO is not set
458CONFIG_HAVE_IDE=y 464CONFIG_HAVE_IDE=y
459CONFIG_IDE=y 465CONFIG_IDE=y
460CONFIG_BLK_DEV_IDE=y 466CONFIG_BLK_DEV_IDE=y
@@ -462,6 +468,7 @@ CONFIG_BLK_DEV_IDE=y
462# 468#
463# Please see Documentation/ide/ide.txt for help/info on IDE drives 469# Please see Documentation/ide/ide.txt for help/info on IDE drives
464# 470#
471CONFIG_IDE_TIMINGS=y
465# CONFIG_BLK_DEV_IDE_SATA is not set 472# CONFIG_BLK_DEV_IDE_SATA is not set
466CONFIG_BLK_DEV_IDEDISK=y 473CONFIG_BLK_DEV_IDEDISK=y
467# CONFIG_IDEDISK_MULTI_MODE is not set 474# CONFIG_IDEDISK_MULTI_MODE is not set
@@ -492,10 +499,8 @@ CONFIG_BLK_DEV_IDEDMA_PCI=y
492# CONFIG_BLK_DEV_AMD74XX is not set 499# CONFIG_BLK_DEV_AMD74XX is not set
493# CONFIG_BLK_DEV_CMD64X is not set 500# CONFIG_BLK_DEV_CMD64X is not set
494# CONFIG_BLK_DEV_TRIFLEX is not set 501# CONFIG_BLK_DEV_TRIFLEX is not set
495# CONFIG_BLK_DEV_CY82C693 is not set
496# CONFIG_BLK_DEV_CS5520 is not set 502# CONFIG_BLK_DEV_CS5520 is not set
497# CONFIG_BLK_DEV_CS5530 is not set 503# CONFIG_BLK_DEV_CS5530 is not set
498# CONFIG_BLK_DEV_HPT34X is not set
499# CONFIG_BLK_DEV_HPT366 is not set 504# CONFIG_BLK_DEV_HPT366 is not set
500# CONFIG_BLK_DEV_JMICRON is not set 505# CONFIG_BLK_DEV_JMICRON is not set
501# CONFIG_BLK_DEV_SC1200 is not set 506# CONFIG_BLK_DEV_SC1200 is not set
@@ -516,8 +521,6 @@ CONFIG_BLK_DEV_IDE_PMAC=y
516CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST=y 521CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST=y
517CONFIG_BLK_DEV_IDEDMA_PMAC=y 522CONFIG_BLK_DEV_IDEDMA_PMAC=y
518CONFIG_BLK_DEV_IDEDMA=y 523CONFIG_BLK_DEV_IDEDMA=y
519# CONFIG_BLK_DEV_HD_ONLY is not set
520# CONFIG_BLK_DEV_HD is not set
521 524
522# 525#
523# SCSI device support 526# SCSI device support
@@ -592,6 +595,7 @@ CONFIG_SCSI_LOWLEVEL=y
592# CONFIG_SCSI_DC390T is not set 595# CONFIG_SCSI_DC390T is not set
593# CONFIG_SCSI_DEBUG is not set 596# CONFIG_SCSI_DEBUG is not set
594# CONFIG_SCSI_SRP is not set 597# CONFIG_SCSI_SRP is not set
598# CONFIG_SCSI_DH is not set
595CONFIG_ATA=y 599CONFIG_ATA=y
596# CONFIG_ATA_NONSTANDARD is not set 600# CONFIG_ATA_NONSTANDARD is not set
597CONFIG_SATA_PMP=y 601CONFIG_SATA_PMP=y
@@ -675,29 +679,21 @@ CONFIG_DM_ZERO=m
675# 679#
676# IEEE 1394 (FireWire) support 680# IEEE 1394 (FireWire) support
677# 681#
678# CONFIG_FIREWIRE is not set
679CONFIG_IEEE1394=y
680
681#
682# Subsystem Options
683#
684# CONFIG_IEEE1394_VERBOSEDEBUG is not set
685 682
686# 683#
687# Controllers 684# Enable only one of the two stacks, unless you know what you are doing
688# 685#
689# CONFIG_IEEE1394_PCILYNX is not set 686# CONFIG_FIREWIRE is not set
687CONFIG_IEEE1394=y
690CONFIG_IEEE1394_OHCI1394=y 688CONFIG_IEEE1394_OHCI1394=y
691 689# CONFIG_IEEE1394_PCILYNX is not set
692#
693# Protocols
694#
695CONFIG_IEEE1394_VIDEO1394=m
696CONFIG_IEEE1394_SBP2=m 690CONFIG_IEEE1394_SBP2=m
697CONFIG_IEEE1394_ETH1394_ROM_ENTRY=y 691CONFIG_IEEE1394_ETH1394_ROM_ENTRY=y
698CONFIG_IEEE1394_ETH1394=m 692CONFIG_IEEE1394_ETH1394=m
699CONFIG_IEEE1394_DV1394=m
700CONFIG_IEEE1394_RAWIO=y 693CONFIG_IEEE1394_RAWIO=y
694CONFIG_IEEE1394_VIDEO1394=m
695CONFIG_IEEE1394_DV1394=m
696# CONFIG_IEEE1394_VERBOSEDEBUG is not set
701# CONFIG_I2O is not set 697# CONFIG_I2O is not set
702CONFIG_MACINTOSH_DRIVERS=y 698CONFIG_MACINTOSH_DRIVERS=y
703CONFIG_ADB_PMU=y 699CONFIG_ADB_PMU=y
@@ -712,7 +708,6 @@ CONFIG_WINDFARM_PM112=y
712CONFIG_WINDFARM_PM121=y 708CONFIG_WINDFARM_PM121=y
713# CONFIG_PMAC_RACKMETER is not set 709# CONFIG_PMAC_RACKMETER is not set
714CONFIG_NETDEVICES=y 710CONFIG_NETDEVICES=y
715# CONFIG_NETDEVICES_MULTIQUEUE is not set
716CONFIG_DUMMY=m 711CONFIG_DUMMY=m
717CONFIG_BONDING=m 712CONFIG_BONDING=m
718# CONFIG_MACVLAN is not set 713# CONFIG_MACVLAN is not set
@@ -720,7 +715,23 @@ CONFIG_BONDING=m
720CONFIG_TUN=m 715CONFIG_TUN=m
721# CONFIG_VETH is not set 716# CONFIG_VETH is not set
722# CONFIG_ARCNET is not set 717# CONFIG_ARCNET is not set
723# CONFIG_PHYLIB is not set 718CONFIG_PHYLIB=y
719
720#
721# MII PHY device drivers
722#
723# CONFIG_MARVELL_PHY is not set
724# CONFIG_DAVICOM_PHY is not set
725# CONFIG_QSEMI_PHY is not set
726# CONFIG_LXT_PHY is not set
727# CONFIG_CICADA_PHY is not set
728# CONFIG_VITESSE_PHY is not set
729# CONFIG_SMSC_PHY is not set
730# CONFIG_BROADCOM_PHY is not set
731# CONFIG_ICPLUS_PHY is not set
732# CONFIG_REALTEK_PHY is not set
733# CONFIG_FIXED_PHY is not set
734# CONFIG_MDIO_BITBANG is not set
724CONFIG_NET_ETHERNET=y 735CONFIG_NET_ETHERNET=y
725CONFIG_MII=y 736CONFIG_MII=y
726# CONFIG_HAPPYMEAL is not set 737# CONFIG_HAPPYMEAL is not set
@@ -740,10 +751,8 @@ CONFIG_ACENIC=y
740CONFIG_ACENIC_OMIT_TIGON_I=y 751CONFIG_ACENIC_OMIT_TIGON_I=y
741# CONFIG_DL2K is not set 752# CONFIG_DL2K is not set
742CONFIG_E1000=y 753CONFIG_E1000=y
743# CONFIG_E1000_NAPI is not set
744# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set 754# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
745# CONFIG_E1000E is not set 755# CONFIG_E1000E is not set
746# CONFIG_E1000E_ENABLED is not set
747# CONFIG_IP1000 is not set 756# CONFIG_IP1000 is not set
748# CONFIG_IGB is not set 757# CONFIG_IGB is not set
749# CONFIG_NS83820 is not set 758# CONFIG_NS83820 is not set
@@ -758,6 +767,7 @@ CONFIG_TIGON3=y
758# CONFIG_BNX2 is not set 767# CONFIG_BNX2 is not set
759# CONFIG_QLA3XXX is not set 768# CONFIG_QLA3XXX is not set
760# CONFIG_ATL1 is not set 769# CONFIG_ATL1 is not set
770# CONFIG_ATL1E is not set
761CONFIG_NETDEV_10000=y 771CONFIG_NETDEV_10000=y
762# CONFIG_CHELSIO_T1 is not set 772# CONFIG_CHELSIO_T1 is not set
763# CONFIG_CHELSIO_T3 is not set 773# CONFIG_CHELSIO_T3 is not set
@@ -855,6 +865,7 @@ CONFIG_INPUT_MOUSE=y
855# CONFIG_MOUSE_PS2 is not set 865# CONFIG_MOUSE_PS2 is not set
856# CONFIG_MOUSE_SERIAL is not set 866# CONFIG_MOUSE_SERIAL is not set
857# CONFIG_MOUSE_APPLETOUCH is not set 867# CONFIG_MOUSE_APPLETOUCH is not set
868# CONFIG_MOUSE_BCM5974 is not set
858# CONFIG_MOUSE_VSXXXAA is not set 869# CONFIG_MOUSE_VSXXXAA is not set
859# CONFIG_INPUT_JOYSTICK is not set 870# CONFIG_INPUT_JOYSTICK is not set
860# CONFIG_INPUT_TABLET is not set 871# CONFIG_INPUT_TABLET is not set
@@ -869,12 +880,14 @@ CONFIG_SERIO=y
869# CONFIG_SERIO_SERPORT is not set 880# CONFIG_SERIO_SERPORT is not set
870# CONFIG_SERIO_PCIPS2 is not set 881# CONFIG_SERIO_PCIPS2 is not set
871# CONFIG_SERIO_RAW is not set 882# CONFIG_SERIO_RAW is not set
883# CONFIG_SERIO_XILINX_XPS_PS2 is not set
872# CONFIG_GAMEPORT is not set 884# CONFIG_GAMEPORT is not set
873 885
874# 886#
875# Character devices 887# Character devices
876# 888#
877CONFIG_VT=y 889CONFIG_VT=y
890CONFIG_CONSOLE_TRANSLATIONS=y
878CONFIG_VT_CONSOLE=y 891CONFIG_VT_CONSOLE=y
879CONFIG_HW_CONSOLE=y 892CONFIG_HW_CONSOLE=y
880# CONFIG_VT_HW_CONSOLE_BINDING is not set 893# CONFIG_VT_HW_CONSOLE_BINDING is not set
@@ -909,44 +922,69 @@ CONFIG_DEVPORT=y
909CONFIG_I2C=y 922CONFIG_I2C=y
910CONFIG_I2C_BOARDINFO=y 923CONFIG_I2C_BOARDINFO=y
911CONFIG_I2C_CHARDEV=y 924CONFIG_I2C_CHARDEV=y
925CONFIG_I2C_HELPER_AUTO=y
912CONFIG_I2C_ALGOBIT=y 926CONFIG_I2C_ALGOBIT=y
913 927
914# 928#
915# I2C Hardware Bus support 929# I2C Hardware Bus support
916# 930#
931
932#
933# PC SMBus host controller drivers
934#
917# CONFIG_I2C_ALI1535 is not set 935# CONFIG_I2C_ALI1535 is not set
918# CONFIG_I2C_ALI1563 is not set 936# CONFIG_I2C_ALI1563 is not set
919# CONFIG_I2C_ALI15X3 is not set 937# CONFIG_I2C_ALI15X3 is not set
920# CONFIG_I2C_AMD756 is not set 938# CONFIG_I2C_AMD756 is not set
921# CONFIG_I2C_AMD8111 is not set 939# CONFIG_I2C_AMD8111 is not set
922# CONFIG_I2C_I801 is not set 940# CONFIG_I2C_I801 is not set
923# CONFIG_I2C_I810 is not set 941# CONFIG_I2C_ISCH is not set
924# CONFIG_I2C_PIIX4 is not set 942# CONFIG_I2C_PIIX4 is not set
925CONFIG_I2C_POWERMAC=y
926# CONFIG_I2C_NFORCE2 is not set 943# CONFIG_I2C_NFORCE2 is not set
927# CONFIG_I2C_OCORES is not set
928# CONFIG_I2C_PARPORT_LIGHT is not set
929# CONFIG_I2C_PROSAVAGE is not set
930# CONFIG_I2C_SAVAGE4 is not set
931# CONFIG_I2C_SIMTEC is not set
932# CONFIG_I2C_SIS5595 is not set 944# CONFIG_I2C_SIS5595 is not set
933# CONFIG_I2C_SIS630 is not set 945# CONFIG_I2C_SIS630 is not set
934# CONFIG_I2C_SIS96X is not set 946# CONFIG_I2C_SIS96X is not set
935# CONFIG_I2C_TAOS_EVM is not set
936# CONFIG_I2C_STUB is not set
937# CONFIG_I2C_TINY_USB is not set
938# CONFIG_I2C_VIA is not set 947# CONFIG_I2C_VIA is not set
939# CONFIG_I2C_VIAPRO is not set 948# CONFIG_I2C_VIAPRO is not set
949
950#
951# Mac SMBus host controller drivers
952#
953CONFIG_I2C_POWERMAC=y
954
955#
956# I2C system bus drivers (mostly embedded / system-on-chip)
957#
958# CONFIG_I2C_OCORES is not set
959# CONFIG_I2C_SIMTEC is not set
960
961#
962# External I2C/SMBus adapter drivers
963#
964# CONFIG_I2C_PARPORT_LIGHT is not set
965# CONFIG_I2C_TAOS_EVM is not set
966# CONFIG_I2C_TINY_USB is not set
967
968#
969# Graphics adapter I2C/DDC channel drivers
970#
940# CONFIG_I2C_VOODOO3 is not set 971# CONFIG_I2C_VOODOO3 is not set
972
973#
974# Other I2C/SMBus bus drivers
975#
941# CONFIG_I2C_PCA_PLATFORM is not set 976# CONFIG_I2C_PCA_PLATFORM is not set
977# CONFIG_I2C_STUB is not set
942 978
943# 979#
944# Miscellaneous I2C Chip support 980# Miscellaneous I2C Chip support
945# 981#
946# CONFIG_DS1682 is not set 982# CONFIG_DS1682 is not set
983# CONFIG_AT24 is not set
947# CONFIG_SENSORS_EEPROM is not set 984# CONFIG_SENSORS_EEPROM is not set
948# CONFIG_SENSORS_PCF8574 is not set 985# CONFIG_SENSORS_PCF8574 is not set
949# CONFIG_PCF8575 is not set 986# CONFIG_PCF8575 is not set
987# CONFIG_SENSORS_PCA9539 is not set
950# CONFIG_SENSORS_PCF8591 is not set 988# CONFIG_SENSORS_PCF8591 is not set
951# CONFIG_SENSORS_MAX6875 is not set 989# CONFIG_SENSORS_MAX6875 is not set
952# CONFIG_SENSORS_TSL2550 is not set 990# CONFIG_SENSORS_TSL2550 is not set
@@ -955,10 +993,13 @@ CONFIG_I2C_POWERMAC=y
955# CONFIG_I2C_DEBUG_BUS is not set 993# CONFIG_I2C_DEBUG_BUS is not set
956# CONFIG_I2C_DEBUG_CHIP is not set 994# CONFIG_I2C_DEBUG_CHIP is not set
957# CONFIG_SPI is not set 995# CONFIG_SPI is not set
996CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
997# CONFIG_GPIOLIB is not set
958# CONFIG_W1 is not set 998# CONFIG_W1 is not set
959# CONFIG_POWER_SUPPLY is not set 999# CONFIG_POWER_SUPPLY is not set
960# CONFIG_HWMON is not set 1000# CONFIG_HWMON is not set
961# CONFIG_THERMAL is not set 1001# CONFIG_THERMAL is not set
1002# CONFIG_THERMAL_HWMON is not set
962# CONFIG_WATCHDOG is not set 1003# CONFIG_WATCHDOG is not set
963 1004
964# 1005#
@@ -970,8 +1011,10 @@ CONFIG_SSB_POSSIBLE=y
970# 1011#
971# Multifunction device drivers 1012# Multifunction device drivers
972# 1013#
1014# CONFIG_MFD_CORE is not set
973# CONFIG_MFD_SM501 is not set 1015# CONFIG_MFD_SM501 is not set
974# CONFIG_HTC_PASIC3 is not set 1016# CONFIG_HTC_PASIC3 is not set
1017# CONFIG_MFD_TMIO is not set
975 1018
976# 1019#
977# Multimedia devices 1020# Multimedia devices
@@ -1050,10 +1093,13 @@ CONFIG_FB_RADEON_BACKLIGHT=y
1050# CONFIG_FB_TRIDENT is not set 1093# CONFIG_FB_TRIDENT is not set
1051# CONFIG_FB_ARK is not set 1094# CONFIG_FB_ARK is not set
1052# CONFIG_FB_PM3 is not set 1095# CONFIG_FB_PM3 is not set
1096# CONFIG_FB_CARMINE is not set
1053# CONFIG_FB_IBM_GXT4500 is not set 1097# CONFIG_FB_IBM_GXT4500 is not set
1054# CONFIG_FB_VIRTUAL is not set 1098# CONFIG_FB_VIRTUAL is not set
1055CONFIG_BACKLIGHT_LCD_SUPPORT=y 1099CONFIG_BACKLIGHT_LCD_SUPPORT=y
1056CONFIG_LCD_CLASS_DEVICE=m 1100CONFIG_LCD_CLASS_DEVICE=m
1101# CONFIG_LCD_ILI9320 is not set
1102# CONFIG_LCD_PLATFORM is not set
1057CONFIG_BACKLIGHT_CLASS_DEVICE=y 1103CONFIG_BACKLIGHT_CLASS_DEVICE=y
1058# CONFIG_BACKLIGHT_CORGI is not set 1104# CONFIG_BACKLIGHT_CORGI is not set
1059 1105
@@ -1077,15 +1123,7 @@ CONFIG_LOGO=y
1077CONFIG_LOGO_LINUX_MONO=y 1123CONFIG_LOGO_LINUX_MONO=y
1078CONFIG_LOGO_LINUX_VGA16=y 1124CONFIG_LOGO_LINUX_VGA16=y
1079CONFIG_LOGO_LINUX_CLUT224=y 1125CONFIG_LOGO_LINUX_CLUT224=y
1080
1081#
1082# Sound
1083#
1084CONFIG_SOUND=m 1126CONFIG_SOUND=m
1085
1086#
1087# Advanced Linux Sound Architecture
1088#
1089CONFIG_SND=m 1127CONFIG_SND=m
1090CONFIG_SND_TIMER=m 1128CONFIG_SND_TIMER=m
1091CONFIG_SND_PCM=m 1129CONFIG_SND_PCM=m
@@ -1103,19 +1141,13 @@ CONFIG_SND_SUPPORT_OLD_API=y
1103CONFIG_SND_VERBOSE_PROCFS=y 1141CONFIG_SND_VERBOSE_PROCFS=y
1104# CONFIG_SND_VERBOSE_PRINTK is not set 1142# CONFIG_SND_VERBOSE_PRINTK is not set
1105# CONFIG_SND_DEBUG is not set 1143# CONFIG_SND_DEBUG is not set
1106 1144CONFIG_SND_DRIVERS=y
1107#
1108# Generic devices
1109#
1110# CONFIG_SND_DUMMY is not set 1145# CONFIG_SND_DUMMY is not set
1111# CONFIG_SND_VIRMIDI is not set 1146# CONFIG_SND_VIRMIDI is not set
1112# CONFIG_SND_MTPAV is not set 1147# CONFIG_SND_MTPAV is not set
1113# CONFIG_SND_SERIAL_U16550 is not set 1148# CONFIG_SND_SERIAL_U16550 is not set
1114# CONFIG_SND_MPU401 is not set 1149# CONFIG_SND_MPU401 is not set
1115 1150CONFIG_SND_PCI=y
1116#
1117# PCI devices
1118#
1119# CONFIG_SND_AD1889 is not set 1151# CONFIG_SND_AD1889 is not set
1120# CONFIG_SND_ALS300 is not set 1152# CONFIG_SND_ALS300 is not set
1121# CONFIG_SND_ALS4000 is not set 1153# CONFIG_SND_ALS4000 is not set
@@ -1177,20 +1209,9 @@ CONFIG_SND_VERBOSE_PROCFS=y
1177# CONFIG_SND_VIRTUOSO is not set 1209# CONFIG_SND_VIRTUOSO is not set
1178# CONFIG_SND_VX222 is not set 1210# CONFIG_SND_VX222 is not set
1179# CONFIG_SND_YMFPCI is not set 1211# CONFIG_SND_YMFPCI is not set
1180 1212CONFIG_SND_PPC=y
1181#
1182# ALSA PowerMac devices
1183#
1184CONFIG_SND_POWERMAC=m 1213CONFIG_SND_POWERMAC=m
1185CONFIG_SND_POWERMAC_AUTO_DRC=y 1214CONFIG_SND_POWERMAC_AUTO_DRC=y
1186
1187#
1188# ALSA PowerPC devices
1189#
1190
1191#
1192# Apple Onboard Audio driver
1193#
1194CONFIG_SND_AOA=m 1215CONFIG_SND_AOA=m
1195CONFIG_SND_AOA_FABRIC_LAYOUT=m 1216CONFIG_SND_AOA_FABRIC_LAYOUT=m
1196CONFIG_SND_AOA_ONYX=m 1217CONFIG_SND_AOA_ONYX=m
@@ -1198,30 +1219,11 @@ CONFIG_SND_AOA_TAS=m
1198CONFIG_SND_AOA_TOONIE=m 1219CONFIG_SND_AOA_TOONIE=m
1199CONFIG_SND_AOA_SOUNDBUS=m 1220CONFIG_SND_AOA_SOUNDBUS=m
1200CONFIG_SND_AOA_SOUNDBUS_I2S=m 1221CONFIG_SND_AOA_SOUNDBUS_I2S=m
1201 1222CONFIG_SND_USB=y
1202#
1203# USB devices
1204#
1205CONFIG_SND_USB_AUDIO=m 1223CONFIG_SND_USB_AUDIO=m
1206# CONFIG_SND_USB_USX2Y is not set 1224# CONFIG_SND_USB_USX2Y is not set
1207# CONFIG_SND_USB_CAIAQ is not set 1225# CONFIG_SND_USB_CAIAQ is not set
1208
1209#
1210# System on Chip audio support
1211#
1212# CONFIG_SND_SOC is not set 1226# CONFIG_SND_SOC is not set
1213
1214#
1215# ALSA SoC audio for Freescale SOCs
1216#
1217
1218#
1219# SoC Audio for the Texas Instruments OMAP
1220#
1221
1222#
1223# Open Sound System
1224#
1225# CONFIG_SOUND_PRIME is not set 1227# CONFIG_SOUND_PRIME is not set
1226CONFIG_HID_SUPPORT=y 1228CONFIG_HID_SUPPORT=y
1227CONFIG_HID=y 1229CONFIG_HID=y
@@ -1256,6 +1258,7 @@ CONFIG_USB_DEVICEFS=y
1256CONFIG_USB_DEVICE_CLASS=y 1258CONFIG_USB_DEVICE_CLASS=y
1257# CONFIG_USB_DYNAMIC_MINORS is not set 1259# CONFIG_USB_DYNAMIC_MINORS is not set
1258# CONFIG_USB_OTG is not set 1260# CONFIG_USB_OTG is not set
1261CONFIG_USB_MON=y
1259 1262
1260# 1263#
1261# USB Host Controller Drivers 1264# USB Host Controller Drivers
@@ -1306,6 +1309,7 @@ CONFIG_USB_STORAGE_JUMPSHOT=y
1306# CONFIG_USB_STORAGE_ALAUDA is not set 1309# CONFIG_USB_STORAGE_ALAUDA is not set
1307# CONFIG_USB_STORAGE_ONETOUCH is not set 1310# CONFIG_USB_STORAGE_ONETOUCH is not set
1308# CONFIG_USB_STORAGE_KARMA is not set 1311# CONFIG_USB_STORAGE_KARMA is not set
1312# CONFIG_USB_STORAGE_SIERRA is not set
1309# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set 1313# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
1310# CONFIG_USB_LIBUSUAL is not set 1314# CONFIG_USB_LIBUSUAL is not set
1311 1315
@@ -1314,7 +1318,6 @@ CONFIG_USB_STORAGE_JUMPSHOT=y
1314# 1318#
1315# CONFIG_USB_MDC800 is not set 1319# CONFIG_USB_MDC800 is not set
1316# CONFIG_USB_MICROTEK is not set 1320# CONFIG_USB_MICROTEK is not set
1317CONFIG_USB_MON=y
1318 1321
1319# 1322#
1320# USB port drivers 1323# USB port drivers
@@ -1323,7 +1326,6 @@ CONFIG_USB_SERIAL=m
1323CONFIG_USB_EZUSB=y 1326CONFIG_USB_EZUSB=y
1324CONFIG_USB_SERIAL_GENERIC=y 1327CONFIG_USB_SERIAL_GENERIC=y
1325# CONFIG_USB_SERIAL_AIRCABLE is not set 1328# CONFIG_USB_SERIAL_AIRCABLE is not set
1326# CONFIG_USB_SERIAL_AIRPRIME is not set
1327# CONFIG_USB_SERIAL_ARK3116 is not set 1329# CONFIG_USB_SERIAL_ARK3116 is not set
1328CONFIG_USB_SERIAL_BELKIN=m 1330CONFIG_USB_SERIAL_BELKIN=m
1329# CONFIG_USB_SERIAL_CH341 is not set 1331# CONFIG_USB_SERIAL_CH341 is not set
@@ -1383,7 +1385,6 @@ CONFIG_USB_SERIAL_OMNINET=m
1383# CONFIG_USB_EMI62 is not set 1385# CONFIG_USB_EMI62 is not set
1384# CONFIG_USB_EMI26 is not set 1386# CONFIG_USB_EMI26 is not set
1385# CONFIG_USB_ADUTUX is not set 1387# CONFIG_USB_ADUTUX is not set
1386# CONFIG_USB_AUERSWALD is not set
1387# CONFIG_USB_RIO500 is not set 1388# CONFIG_USB_RIO500 is not set
1388# CONFIG_USB_LEGOTOWER is not set 1389# CONFIG_USB_LEGOTOWER is not set
1389# CONFIG_USB_LCD is not set 1390# CONFIG_USB_LCD is not set
@@ -1497,6 +1498,7 @@ CONFIG_HFSPLUS_FS=m
1497CONFIG_CRAMFS=y 1498CONFIG_CRAMFS=y
1498# CONFIG_VXFS_FS is not set 1499# CONFIG_VXFS_FS is not set
1499# CONFIG_MINIX_FS is not set 1500# CONFIG_MINIX_FS is not set
1501# CONFIG_OMFS_FS is not set
1500# CONFIG_HPFS_FS is not set 1502# CONFIG_HPFS_FS is not set
1501# CONFIG_QNX4FS_FS is not set 1503# CONFIG_QNX4FS_FS is not set
1502# CONFIG_ROMFS_FS is not set 1504# CONFIG_ROMFS_FS is not set
@@ -1519,7 +1521,6 @@ CONFIG_NFS_ACL_SUPPORT=y
1519CONFIG_NFS_COMMON=y 1521CONFIG_NFS_COMMON=y
1520CONFIG_SUNRPC=y 1522CONFIG_SUNRPC=y
1521CONFIG_SUNRPC_GSS=y 1523CONFIG_SUNRPC_GSS=y
1522# CONFIG_SUNRPC_BIND34 is not set
1523CONFIG_RPCSEC_GSS_KRB5=y 1524CONFIG_RPCSEC_GSS_KRB5=y
1524# CONFIG_RPCSEC_GSS_SPKM3 is not set 1525# CONFIG_RPCSEC_GSS_SPKM3 is not set
1525# CONFIG_SMB_FS is not set 1526# CONFIG_SMB_FS is not set
@@ -1603,6 +1604,7 @@ CONFIG_BITREVERSE=y
1603# CONFIG_GENERIC_FIND_FIRST_BIT is not set 1604# CONFIG_GENERIC_FIND_FIRST_BIT is not set
1604CONFIG_CRC_CCITT=m 1605CONFIG_CRC_CCITT=m
1605# CONFIG_CRC16 is not set 1606# CONFIG_CRC16 is not set
1607CONFIG_CRC_T10DIF=y
1606CONFIG_CRC_ITU_T=m 1608CONFIG_CRC_ITU_T=m
1607CONFIG_CRC32=y 1609CONFIG_CRC32=y
1608# CONFIG_CRC7 is not set 1610# CONFIG_CRC7 is not set
@@ -1629,8 +1631,10 @@ CONFIG_DEBUG_FS=y
1629CONFIG_DEBUG_KERNEL=y 1631CONFIG_DEBUG_KERNEL=y
1630# CONFIG_DEBUG_SHIRQ is not set 1632# CONFIG_DEBUG_SHIRQ is not set
1631CONFIG_DETECT_SOFTLOCKUP=y 1633CONFIG_DETECT_SOFTLOCKUP=y
1634# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
1635CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
1632CONFIG_SCHED_DEBUG=y 1636CONFIG_SCHED_DEBUG=y
1633# CONFIG_SCHEDSTATS is not set 1637CONFIG_SCHEDSTATS=y
1634# CONFIG_TIMER_STATS is not set 1638# CONFIG_TIMER_STATS is not set
1635# CONFIG_DEBUG_OBJECTS is not set 1639# CONFIG_DEBUG_OBJECTS is not set
1636# CONFIG_SLUB_DEBUG_ON is not set 1640# CONFIG_SLUB_DEBUG_ON is not set
@@ -1644,22 +1648,37 @@ CONFIG_DEBUG_MUTEXES=y
1644# CONFIG_LOCK_STAT is not set 1648# CONFIG_LOCK_STAT is not set
1645# CONFIG_DEBUG_SPINLOCK_SLEEP is not set 1649# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1646# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set 1650# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1651CONFIG_STACKTRACE=y
1647# CONFIG_DEBUG_KOBJECT is not set 1652# CONFIG_DEBUG_KOBJECT is not set
1648CONFIG_DEBUG_BUGVERBOSE=y 1653CONFIG_DEBUG_BUGVERBOSE=y
1649# CONFIG_DEBUG_INFO is not set 1654# CONFIG_DEBUG_INFO is not set
1650# CONFIG_DEBUG_VM is not set 1655# CONFIG_DEBUG_VM is not set
1651# CONFIG_DEBUG_WRITECOUNT is not set 1656# CONFIG_DEBUG_WRITECOUNT is not set
1657CONFIG_DEBUG_MEMORY_INIT=y
1652# CONFIG_DEBUG_LIST is not set 1658# CONFIG_DEBUG_LIST is not set
1653# CONFIG_DEBUG_SG is not set 1659# CONFIG_DEBUG_SG is not set
1660CONFIG_FRAME_POINTER=y
1654# CONFIG_BOOT_PRINTK_DELAY is not set 1661# CONFIG_BOOT_PRINTK_DELAY is not set
1655# CONFIG_RCU_TORTURE_TEST is not set 1662# CONFIG_RCU_TORTURE_TEST is not set
1656# CONFIG_BACKTRACE_SELF_TEST is not set 1663# CONFIG_BACKTRACE_SELF_TEST is not set
1657# CONFIG_FAULT_INJECTION is not set 1664# CONFIG_FAULT_INJECTION is not set
1665CONFIG_LATENCYTOP=y
1666CONFIG_SYSCTL_SYSCALL_CHECK=y
1667CONFIG_HAVE_FTRACE=y
1668CONFIG_HAVE_DYNAMIC_FTRACE=y
1669# CONFIG_FTRACE is not set
1670# CONFIG_IRQSOFF_TRACER is not set
1671# CONFIG_SCHED_TRACER is not set
1672# CONFIG_CONTEXT_SWITCH_TRACER is not set
1658# CONFIG_SAMPLES is not set 1673# CONFIG_SAMPLES is not set
1674CONFIG_HAVE_ARCH_KGDB=y
1675# CONFIG_KGDB is not set
1659# CONFIG_DEBUG_STACKOVERFLOW is not set 1676# CONFIG_DEBUG_STACKOVERFLOW is not set
1660# CONFIG_DEBUG_STACK_USAGE is not set 1677# CONFIG_DEBUG_STACK_USAGE is not set
1661# CONFIG_DEBUG_PAGEALLOC is not set 1678# CONFIG_DEBUG_PAGEALLOC is not set
1662# CONFIG_DEBUGGER is not set 1679# CONFIG_CODE_PATCHING_SELFTEST is not set
1680# CONFIG_FTR_FIXUP_SELFTEST is not set
1681# CONFIG_XMON is not set
1663CONFIG_IRQSTACKS=y 1682CONFIG_IRQSTACKS=y
1664# CONFIG_VIRQ_DEBUG is not set 1683# CONFIG_VIRQ_DEBUG is not set
1665CONFIG_BOOTX_TEXT=y 1684CONFIG_BOOTX_TEXT=y
@@ -1718,6 +1737,10 @@ CONFIG_CRYPTO_CRC32C=m
1718CONFIG_CRYPTO_MD4=m 1737CONFIG_CRYPTO_MD4=m
1719CONFIG_CRYPTO_MD5=y 1738CONFIG_CRYPTO_MD5=y
1720CONFIG_CRYPTO_MICHAEL_MIC=m 1739CONFIG_CRYPTO_MICHAEL_MIC=m
1740# CONFIG_CRYPTO_RMD128 is not set
1741# CONFIG_CRYPTO_RMD160 is not set
1742# CONFIG_CRYPTO_RMD256 is not set
1743# CONFIG_CRYPTO_RMD320 is not set
1721CONFIG_CRYPTO_SHA1=m 1744CONFIG_CRYPTO_SHA1=m
1722CONFIG_CRYPTO_SHA256=m 1745CONFIG_CRYPTO_SHA256=m
1723CONFIG_CRYPTO_SHA512=m 1746CONFIG_CRYPTO_SHA512=m
diff --git a/arch/powerpc/configs/iseries_defconfig b/arch/powerpc/configs/iseries_defconfig
index 63f0bdb6340d..2c3f13577f4b 100644
--- a/arch/powerpc/configs/iseries_defconfig
+++ b/arch/powerpc/configs/iseries_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc3 3# Linux kernel version: 2.6.27-rc4
4# Tue May 20 20:01:36 2008 4# Tue Aug 26 13:15:49 2008
5# 5#
6CONFIG_PPC64=y 6CONFIG_PPC64=y
7 7
@@ -31,6 +31,7 @@ CONFIG_GENERIC_HARDIRQS=y
31CONFIG_HAVE_SETUP_PER_CPU_AREA=y 31CONFIG_HAVE_SETUP_PER_CPU_AREA=y
32CONFIG_IRQ_PER_CPU=y 32CONFIG_IRQ_PER_CPU=y
33CONFIG_STACKTRACE_SUPPORT=y 33CONFIG_STACKTRACE_SUPPORT=y
34CONFIG_HAVE_LATENCYTOP_SUPPORT=y
34CONFIG_TRACE_IRQFLAGS_SUPPORT=y 35CONFIG_TRACE_IRQFLAGS_SUPPORT=y
35CONFIG_LOCKDEP_SUPPORT=y 36CONFIG_LOCKDEP_SUPPORT=y
36CONFIG_RWSEM_XCHGADD_ALGORITHM=y 37CONFIG_RWSEM_XCHGADD_ALGORITHM=y
@@ -94,9 +95,8 @@ CONFIG_CC_OPTIMIZE_FOR_SIZE=y
94CONFIG_SYSCTL=y 95CONFIG_SYSCTL=y
95# CONFIG_EMBEDDED is not set 96# CONFIG_EMBEDDED is not set
96CONFIG_SYSCTL_SYSCALL=y 97CONFIG_SYSCTL_SYSCALL=y
97CONFIG_SYSCTL_SYSCALL_CHECK=y
98CONFIG_KALLSYMS=y 98CONFIG_KALLSYMS=y
99# CONFIG_KALLSYMS_ALL is not set 99CONFIG_KALLSYMS_ALL=y
100# CONFIG_KALLSYMS_EXTRA_PASS is not set 100# CONFIG_KALLSYMS_EXTRA_PASS is not set
101CONFIG_HOTPLUG=y 101CONFIG_HOTPLUG=y
102CONFIG_PRINTK=y 102CONFIG_PRINTK=y
@@ -120,10 +120,16 @@ CONFIG_SLUB=y
120# CONFIG_MARKERS is not set 120# CONFIG_MARKERS is not set
121CONFIG_HAVE_OPROFILE=y 121CONFIG_HAVE_OPROFILE=y
122# CONFIG_KPROBES is not set 122# CONFIG_KPROBES is not set
123CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
124CONFIG_HAVE_IOREMAP_PROT=y
123CONFIG_HAVE_KPROBES=y 125CONFIG_HAVE_KPROBES=y
124CONFIG_HAVE_KRETPROBES=y 126CONFIG_HAVE_KRETPROBES=y
125# CONFIG_HAVE_DMA_ATTRS is not set 127CONFIG_HAVE_ARCH_TRACEHOOK=y
128CONFIG_HAVE_DMA_ATTRS=y
129CONFIG_USE_GENERIC_SMP_HELPERS=y
130# CONFIG_HAVE_CLK is not set
126CONFIG_PROC_PAGE_MONITOR=y 131CONFIG_PROC_PAGE_MONITOR=y
132# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
127CONFIG_SLABINFO=y 133CONFIG_SLABINFO=y
128CONFIG_RT_MUTEXES=y 134CONFIG_RT_MUTEXES=y
129# CONFIG_TINY_SHMEM is not set 135# CONFIG_TINY_SHMEM is not set
@@ -139,6 +145,7 @@ CONFIG_STOP_MACHINE=y
139CONFIG_BLOCK=y 145CONFIG_BLOCK=y
140# CONFIG_BLK_DEV_IO_TRACE is not set 146# CONFIG_BLK_DEV_IO_TRACE is not set
141CONFIG_BLK_DEV_BSG=y 147CONFIG_BLK_DEV_BSG=y
148# CONFIG_BLK_DEV_INTEGRITY is not set
142CONFIG_BLOCK_COMPAT=y 149CONFIG_BLOCK_COMPAT=y
143 150
144# 151#
@@ -159,9 +166,6 @@ CONFIG_CLASSIC_RCU=y
159# Platform support 166# Platform support
160# 167#
161CONFIG_PPC_MULTIPLATFORM=y 168CONFIG_PPC_MULTIPLATFORM=y
162# CONFIG_PPC_82xx is not set
163# CONFIG_PPC_83xx is not set
164# CONFIG_PPC_86xx is not set
165# CONFIG_PPC_PSERIES is not set 169# CONFIG_PPC_PSERIES is not set
166CONFIG_LPARCFG=y 170CONFIG_LPARCFG=y
167CONFIG_PPC_ISERIES=y 171CONFIG_PPC_ISERIES=y
@@ -173,8 +177,6 @@ CONFIG_VIODASD=y
173CONFIG_VIOCD=m 177CONFIG_VIOCD=m
174CONFIG_VIOTAPE=m 178CONFIG_VIOTAPE=m
175CONFIG_VIOPATH=y 179CONFIG_VIOPATH=y
176# CONFIG_PPC_MPC512x is not set
177# CONFIG_PPC_MPC5121 is not set
178# CONFIG_PPC_PMAC is not set 180# CONFIG_PPC_PMAC is not set
179# CONFIG_PPC_MAPLE is not set 181# CONFIG_PPC_MAPLE is not set
180# CONFIG_PPC_PASEMI is not set 182# CONFIG_PPC_PASEMI is not set
@@ -211,7 +213,7 @@ CONFIG_HZ_250=y
211# CONFIG_HZ_300 is not set 213# CONFIG_HZ_300 is not set
212# CONFIG_HZ_1000 is not set 214# CONFIG_HZ_1000 is not set
213CONFIG_HZ=250 215CONFIG_HZ=250
214# CONFIG_SCHED_HRTICK is not set 216CONFIG_SCHED_HRTICK=y
215CONFIG_PREEMPT_NONE=y 217CONFIG_PREEMPT_NONE=y
216# CONFIG_PREEMPT_VOLUNTARY is not set 218# CONFIG_PREEMPT_VOLUNTARY is not set
217# CONFIG_PREEMPT is not set 219# CONFIG_PREEMPT is not set
@@ -241,6 +243,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
241CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y 243CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
242CONFIG_PAGEFLAGS_EXTENDED=y 244CONFIG_PAGEFLAGS_EXTENDED=y
243CONFIG_SPLIT_PTLOCK_CPUS=4 245CONFIG_SPLIT_PTLOCK_CPUS=4
246# CONFIG_MIGRATION is not set
244CONFIG_RESOURCES_64BIT=y 247CONFIG_RESOURCES_64BIT=y
245CONFIG_ZONE_DMA_FLAG=1 248CONFIG_ZONE_DMA_FLAG=1
246CONFIG_BOUNCE=y 249CONFIG_BOUNCE=y
@@ -250,6 +253,7 @@ CONFIG_FORCE_MAX_ZONEORDER=13
250# CONFIG_SCHED_SMT is not set 253# CONFIG_SCHED_SMT is not set
251CONFIG_PROC_DEVICETREE=y 254CONFIG_PROC_DEVICETREE=y
252# CONFIG_CMDLINE_BOOL is not set 255# CONFIG_CMDLINE_BOOL is not set
256CONFIG_EXTRA_TARGETS=""
253# CONFIG_PM is not set 257# CONFIG_PM is not set
254CONFIG_SECCOMP=y 258CONFIG_SECCOMP=y
255CONFIG_ISA_DMA_API=y 259CONFIG_ISA_DMA_API=y
@@ -274,10 +278,6 @@ CONFIG_ARCH_SUPPORTS_MSI=y
274CONFIG_PAGE_OFFSET=0xc000000000000000 278CONFIG_PAGE_OFFSET=0xc000000000000000
275CONFIG_KERNEL_START=0xc000000000000000 279CONFIG_KERNEL_START=0xc000000000000000
276CONFIG_PHYSICAL_START=0x00000000 280CONFIG_PHYSICAL_START=0x00000000
277
278#
279# Networking
280#
281CONFIG_NET=y 281CONFIG_NET=y
282 282
283# 283#
@@ -291,6 +291,7 @@ CONFIG_XFRM_USER=m
291CONFIG_XFRM_SUB_POLICY=y 291CONFIG_XFRM_SUB_POLICY=y
292# CONFIG_XFRM_MIGRATE is not set 292# CONFIG_XFRM_MIGRATE is not set
293# CONFIG_XFRM_STATISTICS is not set 293# CONFIG_XFRM_STATISTICS is not set
294CONFIG_XFRM_IPCOMP=m
294CONFIG_NET_KEY=m 295CONFIG_NET_KEY=m
295# CONFIG_NET_KEY_MIGRATE is not set 296# CONFIG_NET_KEY_MIGRATE is not set
296CONFIG_INET=y 297CONFIG_INET=y
@@ -480,7 +481,9 @@ CONFIG_NET_CLS_ROUTE=y
480CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 481CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
481CONFIG_STANDALONE=y 482CONFIG_STANDALONE=y
482CONFIG_PREVENT_FIRMWARE_BUILD=y 483CONFIG_PREVENT_FIRMWARE_BUILD=y
483CONFIG_FW_LOADER=m 484CONFIG_FW_LOADER=y
485CONFIG_FIRMWARE_IN_KERNEL=y
486CONFIG_EXTRA_FIRMWARE=""
484# CONFIG_DEBUG_DRIVER is not set 487# CONFIG_DEBUG_DRIVER is not set
485# CONFIG_DEBUG_DEVRES is not set 488# CONFIG_DEBUG_DEVRES is not set
486# CONFIG_SYS_HYPERVISOR is not set 489# CONFIG_SYS_HYPERVISOR is not set
@@ -504,12 +507,14 @@ CONFIG_BLK_DEV_RAM_SIZE=65536
504# CONFIG_BLK_DEV_XIP is not set 507# CONFIG_BLK_DEV_XIP is not set
505# CONFIG_CDROM_PKTCDVD is not set 508# CONFIG_CDROM_PKTCDVD is not set
506# CONFIG_ATA_OVER_ETH is not set 509# CONFIG_ATA_OVER_ETH is not set
510# CONFIG_BLK_DEV_HD is not set
507CONFIG_MISC_DEVICES=y 511CONFIG_MISC_DEVICES=y
508# CONFIG_PHANTOM is not set 512# CONFIG_PHANTOM is not set
509# CONFIG_EEPROM_93CX6 is not set 513# CONFIG_EEPROM_93CX6 is not set
510# CONFIG_SGI_IOC4 is not set 514# CONFIG_SGI_IOC4 is not set
511# CONFIG_TIFM_CORE is not set 515# CONFIG_TIFM_CORE is not set
512# CONFIG_ENCLOSURE_SERVICES is not set 516# CONFIG_ENCLOSURE_SERVICES is not set
517# CONFIG_HP_ILO is not set
513CONFIG_HAVE_IDE=y 518CONFIG_HAVE_IDE=y
514# CONFIG_IDE is not set 519# CONFIG_IDE is not set
515 520
@@ -588,6 +593,7 @@ CONFIG_SCSI_IBMVSCSI=m
588# CONFIG_SCSI_DC390T is not set 593# CONFIG_SCSI_DC390T is not set
589# CONFIG_SCSI_DEBUG is not set 594# CONFIG_SCSI_DEBUG is not set
590# CONFIG_SCSI_SRP is not set 595# CONFIG_SCSI_SRP is not set
596# CONFIG_SCSI_DH is not set
591# CONFIG_ATA is not set 597# CONFIG_ATA is not set
592CONFIG_MD=y 598CONFIG_MD=y
593CONFIG_BLK_DEV_MD=y 599CONFIG_BLK_DEV_MD=y
@@ -612,12 +618,15 @@ CONFIG_DM_ZERO=m
612# 618#
613# IEEE 1394 (FireWire) support 619# IEEE 1394 (FireWire) support
614# 620#
621
622#
623# Enable only one of the two stacks, unless you know what you are doing
624#
615# CONFIG_FIREWIRE is not set 625# CONFIG_FIREWIRE is not set
616# CONFIG_IEEE1394 is not set 626# CONFIG_IEEE1394 is not set
617# CONFIG_I2O is not set 627# CONFIG_I2O is not set
618# CONFIG_MACINTOSH_DRIVERS is not set 628# CONFIG_MACINTOSH_DRIVERS is not set
619CONFIG_NETDEVICES=y 629CONFIG_NETDEVICES=y
620# CONFIG_NETDEVICES_MULTIQUEUE is not set
621CONFIG_DUMMY=m 630CONFIG_DUMMY=m
622CONFIG_BONDING=m 631CONFIG_BONDING=m
623# CONFIG_MACVLAN is not set 632# CONFIG_MACVLAN is not set
@@ -655,6 +664,7 @@ CONFIG_E100=y
655# CONFIG_SIS900 is not set 664# CONFIG_SIS900 is not set
656# CONFIG_EPIC100 is not set 665# CONFIG_EPIC100 is not set
657# CONFIG_SUNDANCE is not set 666# CONFIG_SUNDANCE is not set
667# CONFIG_TLAN is not set
658# CONFIG_VIA_RHINE is not set 668# CONFIG_VIA_RHINE is not set
659# CONFIG_SC92031 is not set 669# CONFIG_SC92031 is not set
660CONFIG_NETDEV_1000=y 670CONFIG_NETDEV_1000=y
@@ -662,10 +672,8 @@ CONFIG_ACENIC=m
662# CONFIG_ACENIC_OMIT_TIGON_I is not set 672# CONFIG_ACENIC_OMIT_TIGON_I is not set
663# CONFIG_DL2K is not set 673# CONFIG_DL2K is not set
664CONFIG_E1000=m 674CONFIG_E1000=m
665# CONFIG_E1000_NAPI is not set
666# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set 675# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
667# CONFIG_E1000E is not set 676# CONFIG_E1000E is not set
668# CONFIG_E1000E_ENABLED is not set
669# CONFIG_IP1000 is not set 677# CONFIG_IP1000 is not set
670# CONFIG_IGB is not set 678# CONFIG_IGB is not set
671# CONFIG_NS83820 is not set 679# CONFIG_NS83820 is not set
@@ -680,6 +688,7 @@ CONFIG_E1000=m
680# CONFIG_BNX2 is not set 688# CONFIG_BNX2 is not set
681# CONFIG_QLA3XXX is not set 689# CONFIG_QLA3XXX is not set
682# CONFIG_ATL1 is not set 690# CONFIG_ATL1 is not set
691# CONFIG_ATL1E is not set
683CONFIG_NETDEV_10000=y 692CONFIG_NETDEV_10000=y
684# CONFIG_CHELSIO_T1 is not set 693# CONFIG_CHELSIO_T1 is not set
685# CONFIG_CHELSIO_T3 is not set 694# CONFIG_CHELSIO_T3 is not set
@@ -767,6 +776,7 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
767# Character devices 776# Character devices
768# 777#
769CONFIG_VT=y 778CONFIG_VT=y
779CONFIG_CONSOLE_TRANSLATIONS=y
770CONFIG_VT_CONSOLE=y 780CONFIG_VT_CONSOLE=y
771CONFIG_HW_CONSOLE=y 781CONFIG_HW_CONSOLE=y
772# CONFIG_VT_HW_CONSOLE_BINDING is not set 782# CONFIG_VT_HW_CONSOLE_BINDING is not set
@@ -789,6 +799,7 @@ CONFIG_UNIX98_PTYS=y
789CONFIG_LEGACY_PTYS=y 799CONFIG_LEGACY_PTYS=y
790CONFIG_LEGACY_PTY_COUNT=256 800CONFIG_LEGACY_PTY_COUNT=256
791CONFIG_HVC_DRIVER=y 801CONFIG_HVC_DRIVER=y
802CONFIG_HVC_IRQ=y
792CONFIG_HVC_ISERIES=y 803CONFIG_HVC_ISERIES=y
793# CONFIG_IPMI_HANDLER is not set 804# CONFIG_IPMI_HANDLER is not set
794# CONFIG_HW_RANDOM is not set 805# CONFIG_HW_RANDOM is not set
@@ -803,10 +814,13 @@ CONFIG_MAX_RAW_DEVS=256
803CONFIG_DEVPORT=y 814CONFIG_DEVPORT=y
804# CONFIG_I2C is not set 815# CONFIG_I2C is not set
805# CONFIG_SPI is not set 816# CONFIG_SPI is not set
817CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
818# CONFIG_GPIOLIB is not set
806# CONFIG_W1 is not set 819# CONFIG_W1 is not set
807# CONFIG_POWER_SUPPLY is not set 820# CONFIG_POWER_SUPPLY is not set
808# CONFIG_HWMON is not set 821# CONFIG_HWMON is not set
809# CONFIG_THERMAL is not set 822# CONFIG_THERMAL is not set
823# CONFIG_THERMAL_HWMON is not set
810# CONFIG_WATCHDOG is not set 824# CONFIG_WATCHDOG is not set
811 825
812# 826#
@@ -818,8 +832,10 @@ CONFIG_SSB_POSSIBLE=y
818# 832#
819# Multifunction device drivers 833# Multifunction device drivers
820# 834#
835# CONFIG_MFD_CORE is not set
821# CONFIG_MFD_SM501 is not set 836# CONFIG_MFD_SM501 is not set
822# CONFIG_HTC_PASIC3 is not set 837# CONFIG_HTC_PASIC3 is not set
838# CONFIG_MFD_TMIO is not set
823 839
824# 840#
825# Multimedia devices 841# Multimedia devices
@@ -858,10 +874,6 @@ CONFIG_SSB_POSSIBLE=y
858CONFIG_VGA_CONSOLE=y 874CONFIG_VGA_CONSOLE=y
859# CONFIG_VGACON_SOFT_SCROLLBACK is not set 875# CONFIG_VGACON_SOFT_SCROLLBACK is not set
860CONFIG_DUMMY_CONSOLE=y 876CONFIG_DUMMY_CONSOLE=y
861
862#
863# Sound
864#
865# CONFIG_SOUND is not set 877# CONFIG_SOUND is not set
866# CONFIG_HID_SUPPORT is not set 878# CONFIG_HID_SUPPORT is not set
867# CONFIG_USB_SUPPORT is not set 879# CONFIG_USB_SUPPORT is not set
@@ -910,7 +922,6 @@ CONFIG_XFS_POSIX_ACL=y
910# CONFIG_XFS_RT is not set 922# CONFIG_XFS_RT is not set
911# CONFIG_XFS_DEBUG is not set 923# CONFIG_XFS_DEBUG is not set
912CONFIG_GFS2_FS=m 924CONFIG_GFS2_FS=m
913CONFIG_GFS2_FS_LOCKING_NOLOCK=m
914CONFIG_GFS2_FS_LOCKING_DLM=m 925CONFIG_GFS2_FS_LOCKING_DLM=m
915# CONFIG_OCFS2_FS is not set 926# CONFIG_OCFS2_FS is not set
916CONFIG_DNOTIFY=y 927CONFIG_DNOTIFY=y
@@ -967,6 +978,7 @@ CONFIG_CONFIGFS_FS=m
967CONFIG_CRAMFS=y 978CONFIG_CRAMFS=y
968# CONFIG_VXFS_FS is not set 979# CONFIG_VXFS_FS is not set
969# CONFIG_MINIX_FS is not set 980# CONFIG_MINIX_FS is not set
981# CONFIG_OMFS_FS is not set
970# CONFIG_HPFS_FS is not set 982# CONFIG_HPFS_FS is not set
971# CONFIG_QNX4FS_FS is not set 983# CONFIG_QNX4FS_FS is not set
972# CONFIG_ROMFS_FS is not set 984# CONFIG_ROMFS_FS is not set
@@ -989,7 +1001,6 @@ CONFIG_NFS_ACL_SUPPORT=y
989CONFIG_NFS_COMMON=y 1001CONFIG_NFS_COMMON=y
990CONFIG_SUNRPC=y 1002CONFIG_SUNRPC=y
991CONFIG_SUNRPC_GSS=y 1003CONFIG_SUNRPC_GSS=y
992# CONFIG_SUNRPC_BIND34 is not set
993CONFIG_RPCSEC_GSS_KRB5=y 1004CONFIG_RPCSEC_GSS_KRB5=y
994CONFIG_RPCSEC_GSS_SPKM3=m 1005CONFIG_RPCSEC_GSS_SPKM3=m
995# CONFIG_SMB_FS is not set 1006# CONFIG_SMB_FS is not set
@@ -1059,6 +1070,7 @@ CONFIG_BITREVERSE=y
1059# CONFIG_GENERIC_FIND_FIRST_BIT is not set 1070# CONFIG_GENERIC_FIND_FIRST_BIT is not set
1060CONFIG_CRC_CCITT=m 1071CONFIG_CRC_CCITT=m
1061# CONFIG_CRC16 is not set 1072# CONFIG_CRC16 is not set
1073CONFIG_CRC_T10DIF=y
1062CONFIG_CRC_ITU_T=m 1074CONFIG_CRC_ITU_T=m
1063CONFIG_CRC32=y 1075CONFIG_CRC32=y
1064# CONFIG_CRC7 is not set 1076# CONFIG_CRC7 is not set
@@ -1089,8 +1101,10 @@ CONFIG_DEBUG_FS=y
1089CONFIG_DEBUG_KERNEL=y 1101CONFIG_DEBUG_KERNEL=y
1090# CONFIG_DEBUG_SHIRQ is not set 1102# CONFIG_DEBUG_SHIRQ is not set
1091CONFIG_DETECT_SOFTLOCKUP=y 1103CONFIG_DETECT_SOFTLOCKUP=y
1104# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
1105CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
1092CONFIG_SCHED_DEBUG=y 1106CONFIG_SCHED_DEBUG=y
1093# CONFIG_SCHEDSTATS is not set 1107CONFIG_SCHEDSTATS=y
1094# CONFIG_TIMER_STATS is not set 1108# CONFIG_TIMER_STATS is not set
1095# CONFIG_DEBUG_OBJECTS is not set 1109# CONFIG_DEBUG_OBJECTS is not set
1096# CONFIG_SLUB_DEBUG_ON is not set 1110# CONFIG_SLUB_DEBUG_ON is not set
@@ -1104,22 +1118,37 @@ CONFIG_SCHED_DEBUG=y
1104# CONFIG_LOCK_STAT is not set 1118# CONFIG_LOCK_STAT is not set
1105# CONFIG_DEBUG_SPINLOCK_SLEEP is not set 1119# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1106# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set 1120# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1121CONFIG_STACKTRACE=y
1107# CONFIG_DEBUG_KOBJECT is not set 1122# CONFIG_DEBUG_KOBJECT is not set
1108CONFIG_DEBUG_BUGVERBOSE=y 1123CONFIG_DEBUG_BUGVERBOSE=y
1109# CONFIG_DEBUG_INFO is not set 1124# CONFIG_DEBUG_INFO is not set
1110# CONFIG_DEBUG_VM is not set 1125# CONFIG_DEBUG_VM is not set
1111# CONFIG_DEBUG_WRITECOUNT is not set 1126# CONFIG_DEBUG_WRITECOUNT is not set
1127CONFIG_DEBUG_MEMORY_INIT=y
1112# CONFIG_DEBUG_LIST is not set 1128# CONFIG_DEBUG_LIST is not set
1113# CONFIG_DEBUG_SG is not set 1129# CONFIG_DEBUG_SG is not set
1130CONFIG_FRAME_POINTER=y
1114# CONFIG_BOOT_PRINTK_DELAY is not set 1131# CONFIG_BOOT_PRINTK_DELAY is not set
1115# CONFIG_RCU_TORTURE_TEST is not set 1132# CONFIG_RCU_TORTURE_TEST is not set
1116# CONFIG_BACKTRACE_SELF_TEST is not set 1133# CONFIG_BACKTRACE_SELF_TEST is not set
1117# CONFIG_FAULT_INJECTION is not set 1134# CONFIG_FAULT_INJECTION is not set
1135CONFIG_LATENCYTOP=y
1136CONFIG_SYSCTL_SYSCALL_CHECK=y
1137CONFIG_HAVE_FTRACE=y
1138CONFIG_HAVE_DYNAMIC_FTRACE=y
1139# CONFIG_FTRACE is not set
1140# CONFIG_IRQSOFF_TRACER is not set
1141# CONFIG_SCHED_TRACER is not set
1142# CONFIG_CONTEXT_SWITCH_TRACER is not set
1118# CONFIG_SAMPLES is not set 1143# CONFIG_SAMPLES is not set
1144CONFIG_HAVE_ARCH_KGDB=y
1145# CONFIG_KGDB is not set
1119CONFIG_DEBUG_STACKOVERFLOW=y 1146CONFIG_DEBUG_STACKOVERFLOW=y
1120CONFIG_DEBUG_STACK_USAGE=y 1147CONFIG_DEBUG_STACK_USAGE=y
1121# CONFIG_DEBUG_PAGEALLOC is not set 1148# CONFIG_DEBUG_PAGEALLOC is not set
1122# CONFIG_DEBUGGER is not set 1149# CONFIG_CODE_PATCHING_SELFTEST is not set
1150# CONFIG_FTR_FIXUP_SELFTEST is not set
1151# CONFIG_XMON is not set
1123CONFIG_IRQSTACKS=y 1152CONFIG_IRQSTACKS=y
1124# CONFIG_VIRQ_DEBUG is not set 1153# CONFIG_VIRQ_DEBUG is not set
1125# CONFIG_BOOTX_TEXT is not set 1154# CONFIG_BOOTX_TEXT is not set
@@ -1178,6 +1207,10 @@ CONFIG_CRYPTO_CRC32C=m
1178CONFIG_CRYPTO_MD4=m 1207CONFIG_CRYPTO_MD4=m
1179CONFIG_CRYPTO_MD5=y 1208CONFIG_CRYPTO_MD5=y
1180CONFIG_CRYPTO_MICHAEL_MIC=m 1209CONFIG_CRYPTO_MICHAEL_MIC=m
1210# CONFIG_CRYPTO_RMD128 is not set
1211# CONFIG_CRYPTO_RMD160 is not set
1212# CONFIG_CRYPTO_RMD256 is not set
1213# CONFIG_CRYPTO_RMD320 is not set
1181CONFIG_CRYPTO_SHA1=m 1214CONFIG_CRYPTO_SHA1=m
1182CONFIG_CRYPTO_SHA256=m 1215CONFIG_CRYPTO_SHA256=m
1183CONFIG_CRYPTO_SHA512=m 1216CONFIG_CRYPTO_SHA512=m
diff --git a/arch/powerpc/configs/linkstation_defconfig b/arch/powerpc/configs/linkstation_defconfig
index 48434c2c7628..6fc4c2127757 100644
--- a/arch/powerpc/configs/linkstation_defconfig
+++ b/arch/powerpc/configs/linkstation_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc5 3# Linux kernel version: 2.6.27-rc4
4# Mon Jun 9 08:52:10 2008 4# Thu Aug 21 00:52:05 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -32,6 +32,7 @@ CONFIG_GENERIC_HARDIRQS=y
32# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set 32# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
33CONFIG_IRQ_PER_CPU=y 33CONFIG_IRQ_PER_CPU=y
34CONFIG_STACKTRACE_SUPPORT=y 34CONFIG_STACKTRACE_SUPPORT=y
35CONFIG_HAVE_LATENCYTOP_SUPPORT=y
35CONFIG_LOCKDEP_SUPPORT=y 36CONFIG_LOCKDEP_SUPPORT=y
36CONFIG_RWSEM_XCHGADD_ALGORITHM=y 37CONFIG_RWSEM_XCHGADD_ALGORITHM=y
37CONFIG_ARCH_HAS_ILOG2_U32=y 38CONFIG_ARCH_HAS_ILOG2_U32=y
@@ -93,7 +94,6 @@ CONFIG_INITRAMFS_SOURCE=""
93CONFIG_SYSCTL=y 94CONFIG_SYSCTL=y
94# CONFIG_EMBEDDED is not set 95# CONFIG_EMBEDDED is not set
95CONFIG_SYSCTL_SYSCALL=y 96CONFIG_SYSCTL_SYSCALL=y
96CONFIG_SYSCTL_SYSCALL_CHECK=y
97CONFIG_KALLSYMS=y 97CONFIG_KALLSYMS=y
98# CONFIG_KALLSYMS_ALL is not set 98# CONFIG_KALLSYMS_ALL is not set
99# CONFIG_KALLSYMS_EXTRA_PASS is not set 99# CONFIG_KALLSYMS_EXTRA_PASS is not set
@@ -119,10 +119,16 @@ CONFIG_SLUB=y
119# CONFIG_MARKERS is not set 119# CONFIG_MARKERS is not set
120CONFIG_HAVE_OPROFILE=y 120CONFIG_HAVE_OPROFILE=y
121# CONFIG_KPROBES is not set 121# CONFIG_KPROBES is not set
122CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
123CONFIG_HAVE_IOREMAP_PROT=y
122CONFIG_HAVE_KPROBES=y 124CONFIG_HAVE_KPROBES=y
123CONFIG_HAVE_KRETPROBES=y 125CONFIG_HAVE_KRETPROBES=y
126CONFIG_HAVE_ARCH_TRACEHOOK=y
124# CONFIG_HAVE_DMA_ATTRS is not set 127# CONFIG_HAVE_DMA_ATTRS is not set
128# CONFIG_USE_GENERIC_SMP_HELPERS is not set
129# CONFIG_HAVE_CLK is not set
125CONFIG_PROC_PAGE_MONITOR=y 130CONFIG_PROC_PAGE_MONITOR=y
131# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
126CONFIG_SLABINFO=y 132CONFIG_SLABINFO=y
127CONFIG_RT_MUTEXES=y 133CONFIG_RT_MUTEXES=y
128# CONFIG_TINY_SHMEM is not set 134# CONFIG_TINY_SHMEM is not set
@@ -139,6 +145,7 @@ CONFIG_BLOCK=y
139# CONFIG_BLK_DEV_IO_TRACE is not set 145# CONFIG_BLK_DEV_IO_TRACE is not set
140# CONFIG_LSF is not set 146# CONFIG_LSF is not set
141# CONFIG_BLK_DEV_BSG is not set 147# CONFIG_BLK_DEV_BSG is not set
148# CONFIG_BLK_DEV_INTEGRITY is not set
142 149
143# 150#
144# IO Schedulers 151# IO Schedulers
@@ -158,25 +165,25 @@ CONFIG_CLASSIC_RCU=y
158# Platform support 165# Platform support
159# 166#
160CONFIG_PPC_MULTIPLATFORM=y 167CONFIG_PPC_MULTIPLATFORM=y
161# CONFIG_PPC_82xx is not set
162# CONFIG_PPC_83xx is not set
163# CONFIG_PPC_86xx is not set
164CONFIG_CLASSIC32=y 168CONFIG_CLASSIC32=y
165# CONFIG_PPC_CHRP is not set 169# CONFIG_PPC_CHRP is not set
166# CONFIG_PPC_MPC512x is not set
167# CONFIG_PPC_MPC5121 is not set
168# CONFIG_MPC5121_ADS is not set 170# CONFIG_MPC5121_ADS is not set
171# CONFIG_MPC5121_GENERIC is not set
169# CONFIG_PPC_MPC52xx is not set 172# CONFIG_PPC_MPC52xx is not set
170# CONFIG_PPC_PMAC is not set 173# CONFIG_PPC_PMAC is not set
171# CONFIG_PPC_CELL is not set 174# CONFIG_PPC_CELL is not set
172# CONFIG_PPC_CELL_NATIVE is not set 175# CONFIG_PPC_CELL_NATIVE is not set
176# CONFIG_PPC_82xx is not set
173# CONFIG_PQ2ADS is not set 177# CONFIG_PQ2ADS is not set
178# CONFIG_PPC_83xx is not set
179# CONFIG_PPC_86xx is not set
174CONFIG_EMBEDDED6xx=y 180CONFIG_EMBEDDED6xx=y
175CONFIG_LINKSTATION=y 181CONFIG_LINKSTATION=y
176# CONFIG_STORCENTER is not set 182# CONFIG_STORCENTER is not set
177# CONFIG_MPC7448HPC2 is not set 183# CONFIG_MPC7448HPC2 is not set
178# CONFIG_PPC_HOLLY is not set 184# CONFIG_PPC_HOLLY is not set
179# CONFIG_PPC_PRPMC2800 is not set 185# CONFIG_PPC_PRPMC2800 is not set
186# CONFIG_PPC_C2K is not set
180CONFIG_MPC10X_BRIDGE=y 187CONFIG_MPC10X_BRIDGE=y
181CONFIG_MPC10X_OPENPIC=y 188CONFIG_MPC10X_OPENPIC=y
182# CONFIG_MPC10X_STORE_GATHERING is not set 189# CONFIG_MPC10X_STORE_GATHERING is not set
@@ -207,7 +214,7 @@ CONFIG_HZ_100=y
207# CONFIG_HZ_300 is not set 214# CONFIG_HZ_300 is not set
208# CONFIG_HZ_1000 is not set 215# CONFIG_HZ_1000 is not set
209CONFIG_HZ=100 216CONFIG_HZ=100
210# CONFIG_SCHED_HRTICK is not set 217CONFIG_SCHED_HRTICK=y
211CONFIG_PREEMPT_NONE=y 218CONFIG_PREEMPT_NONE=y
212# CONFIG_PREEMPT_VOLUNTARY is not set 219# CONFIG_PREEMPT_VOLUNTARY is not set
213# CONFIG_PREEMPT is not set 220# CONFIG_PREEMPT is not set
@@ -230,6 +237,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
230# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set 237# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
231CONFIG_PAGEFLAGS_EXTENDED=y 238CONFIG_PAGEFLAGS_EXTENDED=y
232CONFIG_SPLIT_PTLOCK_CPUS=4 239CONFIG_SPLIT_PTLOCK_CPUS=4
240CONFIG_MIGRATION=y
233# CONFIG_RESOURCES_64BIT is not set 241# CONFIG_RESOURCES_64BIT is not set
234CONFIG_ZONE_DMA_FLAG=1 242CONFIG_ZONE_DMA_FLAG=1
235CONFIG_BOUNCE=y 243CONFIG_BOUNCE=y
@@ -237,6 +245,7 @@ CONFIG_VIRT_TO_BUS=y
237CONFIG_FORCE_MAX_ZONEORDER=11 245CONFIG_FORCE_MAX_ZONEORDER=11
238CONFIG_PROC_DEVICETREE=y 246CONFIG_PROC_DEVICETREE=y
239# CONFIG_CMDLINE_BOOL is not set 247# CONFIG_CMDLINE_BOOL is not set
248CONFIG_EXTRA_TARGETS=""
240# CONFIG_PM is not set 249# CONFIG_PM is not set
241CONFIG_SECCOMP=y 250CONFIG_SECCOMP=y
242CONFIG_ISA_DMA_API=y 251CONFIG_ISA_DMA_API=y
@@ -273,10 +282,6 @@ CONFIG_PAGE_OFFSET=0xc0000000
273CONFIG_KERNEL_START=0xc0000000 282CONFIG_KERNEL_START=0xc0000000
274CONFIG_PHYSICAL_START=0x00000000 283CONFIG_PHYSICAL_START=0x00000000
275CONFIG_TASK_SIZE=0xc0000000 284CONFIG_TASK_SIZE=0xc0000000
276
277#
278# Networking
279#
280CONFIG_NET=y 285CONFIG_NET=y
281 286
282# 287#
@@ -461,6 +466,7 @@ CONFIG_IP_NF_ARP_MANGLE=m
461# 466#
462# CONFIG_CFG80211 is not set 467# CONFIG_CFG80211 is not set
463CONFIG_WIRELESS_EXT=y 468CONFIG_WIRELESS_EXT=y
469CONFIG_WIRELESS_EXT_SYSFS=y
464# CONFIG_MAC80211 is not set 470# CONFIG_MAC80211 is not set
465CONFIG_IEEE80211=m 471CONFIG_IEEE80211=m
466CONFIG_IEEE80211_DEBUG=y 472CONFIG_IEEE80211_DEBUG=y
@@ -480,7 +486,9 @@ CONFIG_IEEE80211_CRYPT_TKIP=m
480CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 486CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
481CONFIG_STANDALONE=y 487CONFIG_STANDALONE=y
482CONFIG_PREVENT_FIRMWARE_BUILD=y 488CONFIG_PREVENT_FIRMWARE_BUILD=y
483CONFIG_FW_LOADER=m 489CONFIG_FW_LOADER=y
490CONFIG_FIRMWARE_IN_KERNEL=y
491CONFIG_EXTRA_FIRMWARE=""
484# CONFIG_DEBUG_DRIVER is not set 492# CONFIG_DEBUG_DRIVER is not set
485# CONFIG_DEBUG_DEVRES is not set 493# CONFIG_DEBUG_DEVRES is not set
486# CONFIG_SYS_HYPERVISOR is not set 494# CONFIG_SYS_HYPERVISOR is not set
@@ -592,12 +600,14 @@ CONFIG_BLK_DEV_RAM_SIZE=8192
592# CONFIG_BLK_DEV_XIP is not set 600# CONFIG_BLK_DEV_XIP is not set
593# CONFIG_CDROM_PKTCDVD is not set 601# CONFIG_CDROM_PKTCDVD is not set
594# CONFIG_ATA_OVER_ETH is not set 602# CONFIG_ATA_OVER_ETH is not set
603# CONFIG_BLK_DEV_HD is not set
595CONFIG_MISC_DEVICES=y 604CONFIG_MISC_DEVICES=y
596# CONFIG_PHANTOM is not set 605# CONFIG_PHANTOM is not set
597# CONFIG_EEPROM_93CX6 is not set 606# CONFIG_EEPROM_93CX6 is not set
598# CONFIG_SGI_IOC4 is not set 607# CONFIG_SGI_IOC4 is not set
599# CONFIG_TIFM_CORE is not set 608# CONFIG_TIFM_CORE is not set
600# CONFIG_ENCLOSURE_SERVICES is not set 609# CONFIG_ENCLOSURE_SERVICES is not set
610# CONFIG_HP_ILO is not set
601CONFIG_HAVE_IDE=y 611CONFIG_HAVE_IDE=y
602# CONFIG_IDE is not set 612# CONFIG_IDE is not set
603 613
@@ -676,6 +686,7 @@ CONFIG_SCSI_LOWLEVEL=y
676# CONFIG_SCSI_NSP32 is not set 686# CONFIG_SCSI_NSP32 is not set
677# CONFIG_SCSI_DEBUG is not set 687# CONFIG_SCSI_DEBUG is not set
678# CONFIG_SCSI_SRP is not set 688# CONFIG_SCSI_SRP is not set
689# CONFIG_SCSI_DH is not set
679CONFIG_ATA=y 690CONFIG_ATA=y
680# CONFIG_ATA_NONSTANDARD is not set 691# CONFIG_ATA_NONSTANDARD is not set
681CONFIG_SATA_PMP=y 692CONFIG_SATA_PMP=y
@@ -743,12 +754,15 @@ CONFIG_PATA_SIL680=y
743# 754#
744# IEEE 1394 (FireWire) support 755# IEEE 1394 (FireWire) support
745# 756#
757
758#
759# Enable only one of the two stacks, unless you know what you are doing
760#
746# CONFIG_FIREWIRE is not set 761# CONFIG_FIREWIRE is not set
747# CONFIG_IEEE1394 is not set 762# CONFIG_IEEE1394 is not set
748# CONFIG_I2O is not set 763# CONFIG_I2O is not set
749# CONFIG_MACINTOSH_DRIVERS is not set 764# CONFIG_MACINTOSH_DRIVERS is not set
750CONFIG_NETDEVICES=y 765CONFIG_NETDEVICES=y
751# CONFIG_NETDEVICES_MULTIQUEUE is not set
752# CONFIG_DUMMY is not set 766# CONFIG_DUMMY is not set
753# CONFIG_BONDING is not set 767# CONFIG_BONDING is not set
754# CONFIG_MACVLAN is not set 768# CONFIG_MACVLAN is not set
@@ -785,14 +799,12 @@ CONFIG_NETDEV_1000=y
785# CONFIG_DL2K is not set 799# CONFIG_DL2K is not set
786# CONFIG_E1000 is not set 800# CONFIG_E1000 is not set
787# CONFIG_E1000E is not set 801# CONFIG_E1000E is not set
788# CONFIG_E1000E_ENABLED is not set
789# CONFIG_IP1000 is not set 802# CONFIG_IP1000 is not set
790# CONFIG_IGB is not set 803# CONFIG_IGB is not set
791# CONFIG_NS83820 is not set 804# CONFIG_NS83820 is not set
792# CONFIG_HAMACHI is not set 805# CONFIG_HAMACHI is not set
793# CONFIG_YELLOWFIN is not set 806# CONFIG_YELLOWFIN is not set
794CONFIG_R8169=y 807CONFIG_R8169=y
795# CONFIG_R8169_NAPI is not set
796# CONFIG_SIS190 is not set 808# CONFIG_SIS190 is not set
797# CONFIG_SKGE is not set 809# CONFIG_SKGE is not set
798# CONFIG_SKY2 is not set 810# CONFIG_SKY2 is not set
@@ -803,6 +815,7 @@ CONFIG_R8169=y
803# CONFIG_MV643XX_ETH is not set 815# CONFIG_MV643XX_ETH is not set
804# CONFIG_QLA3XXX is not set 816# CONFIG_QLA3XXX is not set
805# CONFIG_ATL1 is not set 817# CONFIG_ATL1 is not set
818# CONFIG_ATL1E is not set
806CONFIG_NETDEV_10000=y 819CONFIG_NETDEV_10000=y
807# CONFIG_CHELSIO_T1 is not set 820# CONFIG_CHELSIO_T1 is not set
808# CONFIG_CHELSIO_T3 is not set 821# CONFIG_CHELSIO_T3 is not set
@@ -889,12 +902,14 @@ CONFIG_SERIO=y
889CONFIG_SERIO_SERPORT=y 902CONFIG_SERIO_SERPORT=y
890# CONFIG_SERIO_PCIPS2 is not set 903# CONFIG_SERIO_PCIPS2 is not set
891# CONFIG_SERIO_RAW is not set 904# CONFIG_SERIO_RAW is not set
905# CONFIG_SERIO_XILINX_XPS_PS2 is not set
892# CONFIG_GAMEPORT is not set 906# CONFIG_GAMEPORT is not set
893 907
894# 908#
895# Character devices 909# Character devices
896# 910#
897CONFIG_VT=y 911CONFIG_VT=y
912CONFIG_CONSOLE_TRANSLATIONS=y
898CONFIG_VT_CONSOLE=y 913CONFIG_VT_CONSOLE=y
899CONFIG_HW_CONSOLE=y 914CONFIG_HW_CONSOLE=y
900# CONFIG_VT_HW_CONSOLE_BINDING is not set 915# CONFIG_VT_HW_CONSOLE_BINDING is not set
@@ -934,43 +949,64 @@ CONFIG_DEVPORT=y
934CONFIG_I2C=y 949CONFIG_I2C=y
935CONFIG_I2C_BOARDINFO=y 950CONFIG_I2C_BOARDINFO=y
936CONFIG_I2C_CHARDEV=y 951CONFIG_I2C_CHARDEV=y
952CONFIG_I2C_HELPER_AUTO=y
937 953
938# 954#
939# I2C Hardware Bus support 955# I2C Hardware Bus support
940# 956#
957
958#
959# PC SMBus host controller drivers
960#
941# CONFIG_I2C_ALI1535 is not set 961# CONFIG_I2C_ALI1535 is not set
942# CONFIG_I2C_ALI1563 is not set 962# CONFIG_I2C_ALI1563 is not set
943# CONFIG_I2C_ALI15X3 is not set 963# CONFIG_I2C_ALI15X3 is not set
944# CONFIG_I2C_AMD756 is not set 964# CONFIG_I2C_AMD756 is not set
945# CONFIG_I2C_AMD8111 is not set 965# CONFIG_I2C_AMD8111 is not set
946# CONFIG_I2C_I801 is not set 966# CONFIG_I2C_I801 is not set
947# CONFIG_I2C_I810 is not set 967# CONFIG_I2C_ISCH is not set
948# CONFIG_I2C_PIIX4 is not set 968# CONFIG_I2C_PIIX4 is not set
949CONFIG_I2C_MPC=y
950# CONFIG_I2C_NFORCE2 is not set 969# CONFIG_I2C_NFORCE2 is not set
951# CONFIG_I2C_OCORES is not set
952# CONFIG_I2C_PARPORT_LIGHT is not set
953# CONFIG_I2C_PROSAVAGE is not set
954# CONFIG_I2C_SAVAGE4 is not set
955# CONFIG_I2C_SIMTEC is not set
956# CONFIG_I2C_SIS5595 is not set 970# CONFIG_I2C_SIS5595 is not set
957# CONFIG_I2C_SIS630 is not set 971# CONFIG_I2C_SIS630 is not set
958# CONFIG_I2C_SIS96X is not set 972# CONFIG_I2C_SIS96X is not set
959# CONFIG_I2C_TAOS_EVM is not set
960# CONFIG_I2C_STUB is not set
961# CONFIG_I2C_TINY_USB is not set
962# CONFIG_I2C_VIA is not set 973# CONFIG_I2C_VIA is not set
963# CONFIG_I2C_VIAPRO is not set 974# CONFIG_I2C_VIAPRO is not set
975
976#
977# I2C system bus drivers (mostly embedded / system-on-chip)
978#
979CONFIG_I2C_MPC=y
980# CONFIG_I2C_OCORES is not set
981# CONFIG_I2C_SIMTEC is not set
982
983#
984# External I2C/SMBus adapter drivers
985#
986# CONFIG_I2C_PARPORT_LIGHT is not set
987# CONFIG_I2C_TAOS_EVM is not set
988# CONFIG_I2C_TINY_USB is not set
989
990#
991# Graphics adapter I2C/DDC channel drivers
992#
964# CONFIG_I2C_VOODOO3 is not set 993# CONFIG_I2C_VOODOO3 is not set
994
995#
996# Other I2C/SMBus bus drivers
997#
965# CONFIG_I2C_PCA_PLATFORM is not set 998# CONFIG_I2C_PCA_PLATFORM is not set
999# CONFIG_I2C_STUB is not set
966 1000
967# 1001#
968# Miscellaneous I2C Chip support 1002# Miscellaneous I2C Chip support
969# 1003#
970# CONFIG_DS1682 is not set 1004# CONFIG_DS1682 is not set
1005# CONFIG_AT24 is not set
971CONFIG_SENSORS_EEPROM=m 1006CONFIG_SENSORS_EEPROM=m
972# CONFIG_SENSORS_PCF8574 is not set 1007# CONFIG_SENSORS_PCF8574 is not set
973# CONFIG_PCF8575 is not set 1008# CONFIG_PCF8575 is not set
1009# CONFIG_SENSORS_PCA9539 is not set
974# CONFIG_SENSORS_PCF8591 is not set 1010# CONFIG_SENSORS_PCF8591 is not set
975# CONFIG_SENSORS_MAX6875 is not set 1011# CONFIG_SENSORS_MAX6875 is not set
976# CONFIG_SENSORS_TSL2550 is not set 1012# CONFIG_SENSORS_TSL2550 is not set
@@ -979,10 +1015,13 @@ CONFIG_SENSORS_EEPROM=m
979# CONFIG_I2C_DEBUG_BUS is not set 1015# CONFIG_I2C_DEBUG_BUS is not set
980# CONFIG_I2C_DEBUG_CHIP is not set 1016# CONFIG_I2C_DEBUG_CHIP is not set
981# CONFIG_SPI is not set 1017# CONFIG_SPI is not set
1018CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
1019# CONFIG_GPIOLIB is not set
982# CONFIG_W1 is not set 1020# CONFIG_W1 is not set
983# CONFIG_POWER_SUPPLY is not set 1021# CONFIG_POWER_SUPPLY is not set
984CONFIG_HWMON=y 1022CONFIG_HWMON=y
985# CONFIG_HWMON_VID is not set 1023# CONFIG_HWMON_VID is not set
1024# CONFIG_SENSORS_AD7414 is not set
986# CONFIG_SENSORS_AD7418 is not set 1025# CONFIG_SENSORS_AD7418 is not set
987# CONFIG_SENSORS_ADM1021 is not set 1026# CONFIG_SENSORS_ADM1021 is not set
988# CONFIG_SENSORS_ADM1025 is not set 1027# CONFIG_SENSORS_ADM1025 is not set
@@ -1036,6 +1075,7 @@ CONFIG_HWMON=y
1036# CONFIG_SENSORS_W83627EHF is not set 1075# CONFIG_SENSORS_W83627EHF is not set
1037# CONFIG_HWMON_DEBUG_CHIP is not set 1076# CONFIG_HWMON_DEBUG_CHIP is not set
1038# CONFIG_THERMAL is not set 1077# CONFIG_THERMAL is not set
1078# CONFIG_THERMAL_HWMON is not set
1039# CONFIG_WATCHDOG is not set 1079# CONFIG_WATCHDOG is not set
1040 1080
1041# 1081#
@@ -1047,8 +1087,10 @@ CONFIG_SSB_POSSIBLE=y
1047# 1087#
1048# Multifunction device drivers 1088# Multifunction device drivers
1049# 1089#
1090# CONFIG_MFD_CORE is not set
1050# CONFIG_MFD_SM501 is not set 1091# CONFIG_MFD_SM501 is not set
1051# CONFIG_HTC_PASIC3 is not set 1092# CONFIG_HTC_PASIC3 is not set
1093# CONFIG_MFD_TMIO is not set
1052 1094
1053# 1095#
1054# Multimedia devices 1096# Multimedia devices
@@ -1086,10 +1128,6 @@ CONFIG_VIDEO_OUTPUT_CONTROL=m
1086# 1128#
1087# CONFIG_VGA_CONSOLE is not set 1129# CONFIG_VGA_CONSOLE is not set
1088CONFIG_DUMMY_CONSOLE=y 1130CONFIG_DUMMY_CONSOLE=y
1089
1090#
1091# Sound
1092#
1093# CONFIG_SOUND is not set 1131# CONFIG_SOUND is not set
1094CONFIG_HID_SUPPORT=y 1132CONFIG_HID_SUPPORT=y
1095CONFIG_HID=m 1133CONFIG_HID=m
@@ -1121,6 +1159,7 @@ CONFIG_USB_DEVICEFS=y
1121CONFIG_USB_DEVICE_CLASS=y 1159CONFIG_USB_DEVICE_CLASS=y
1122# CONFIG_USB_DYNAMIC_MINORS is not set 1160# CONFIG_USB_DYNAMIC_MINORS is not set
1123# CONFIG_USB_OTG is not set 1161# CONFIG_USB_OTG is not set
1162CONFIG_USB_MON=y
1124 1163
1125# 1164#
1126# USB Host Controller Drivers 1165# USB Host Controller Drivers
@@ -1172,6 +1211,7 @@ CONFIG_USB_STORAGE=m
1172# CONFIG_USB_STORAGE_ALAUDA is not set 1211# CONFIG_USB_STORAGE_ALAUDA is not set
1173# CONFIG_USB_STORAGE_ONETOUCH is not set 1212# CONFIG_USB_STORAGE_ONETOUCH is not set
1174# CONFIG_USB_STORAGE_KARMA is not set 1213# CONFIG_USB_STORAGE_KARMA is not set
1214# CONFIG_USB_STORAGE_SIERRA is not set
1175# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set 1215# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
1176# CONFIG_USB_LIBUSUAL is not set 1216# CONFIG_USB_LIBUSUAL is not set
1177 1217
@@ -1180,7 +1220,6 @@ CONFIG_USB_STORAGE=m
1180# 1220#
1181# CONFIG_USB_MDC800 is not set 1221# CONFIG_USB_MDC800 is not set
1182# CONFIG_USB_MICROTEK is not set 1222# CONFIG_USB_MICROTEK is not set
1183CONFIG_USB_MON=y
1184 1223
1185# 1224#
1186# USB port drivers 1225# USB port drivers
@@ -1190,7 +1229,6 @@ CONFIG_USB_SERIAL_CONSOLE=y
1190# CONFIG_USB_EZUSB is not set 1229# CONFIG_USB_EZUSB is not set
1191# CONFIG_USB_SERIAL_GENERIC is not set 1230# CONFIG_USB_SERIAL_GENERIC is not set
1192# CONFIG_USB_SERIAL_AIRCABLE is not set 1231# CONFIG_USB_SERIAL_AIRCABLE is not set
1193# CONFIG_USB_SERIAL_AIRPRIME is not set
1194# CONFIG_USB_SERIAL_ARK3116 is not set 1232# CONFIG_USB_SERIAL_ARK3116 is not set
1195# CONFIG_USB_SERIAL_BELKIN is not set 1233# CONFIG_USB_SERIAL_BELKIN is not set
1196# CONFIG_USB_SERIAL_CH341 is not set 1234# CONFIG_USB_SERIAL_CH341 is not set
@@ -1237,7 +1275,6 @@ CONFIG_USB_SERIAL_FTDI_SIO=y
1237# CONFIG_USB_EMI62 is not set 1275# CONFIG_USB_EMI62 is not set
1238# CONFIG_USB_EMI26 is not set 1276# CONFIG_USB_EMI26 is not set
1239# CONFIG_USB_ADUTUX is not set 1277# CONFIG_USB_ADUTUX is not set
1240# CONFIG_USB_AUERSWALD is not set
1241# CONFIG_USB_RIO500 is not set 1278# CONFIG_USB_RIO500 is not set
1242# CONFIG_USB_LEGOTOWER is not set 1279# CONFIG_USB_LEGOTOWER is not set
1243# CONFIG_USB_LCD is not set 1280# CONFIG_USB_LCD is not set
@@ -1291,6 +1328,7 @@ CONFIG_RTC_DRV_RS5C372=y
1291# CONFIG_RTC_DRV_PCF8583 is not set 1328# CONFIG_RTC_DRV_PCF8583 is not set
1292# CONFIG_RTC_DRV_M41T80 is not set 1329# CONFIG_RTC_DRV_M41T80 is not set
1293# CONFIG_RTC_DRV_S35390A is not set 1330# CONFIG_RTC_DRV_S35390A is not set
1331# CONFIG_RTC_DRV_FM3130 is not set
1294 1332
1295# 1333#
1296# SPI RTC drivers 1334# SPI RTC drivers
@@ -1392,6 +1430,7 @@ CONFIG_TMPFS=y
1392# CONFIG_CRAMFS is not set 1430# CONFIG_CRAMFS is not set
1393# CONFIG_VXFS_FS is not set 1431# CONFIG_VXFS_FS is not set
1394# CONFIG_MINIX_FS is not set 1432# CONFIG_MINIX_FS is not set
1433# CONFIG_OMFS_FS is not set
1395# CONFIG_HPFS_FS is not set 1434# CONFIG_HPFS_FS is not set
1396# CONFIG_QNX4FS_FS is not set 1435# CONFIG_QNX4FS_FS is not set
1397# CONFIG_ROMFS_FS is not set 1436# CONFIG_ROMFS_FS is not set
@@ -1402,11 +1441,11 @@ CONFIG_NFS_FS=y
1402CONFIG_NFS_V3=y 1441CONFIG_NFS_V3=y
1403CONFIG_NFS_V3_ACL=y 1442CONFIG_NFS_V3_ACL=y
1404CONFIG_NFS_V4=y 1443CONFIG_NFS_V4=y
1444CONFIG_ROOT_NFS=y
1405CONFIG_NFSD=m 1445CONFIG_NFSD=m
1406CONFIG_NFSD_V3=y 1446CONFIG_NFSD_V3=y
1407# CONFIG_NFSD_V3_ACL is not set 1447# CONFIG_NFSD_V3_ACL is not set
1408# CONFIG_NFSD_V4 is not set 1448# CONFIG_NFSD_V4 is not set
1409CONFIG_ROOT_NFS=y
1410CONFIG_LOCKD=y 1449CONFIG_LOCKD=y
1411CONFIG_LOCKD_V4=y 1450CONFIG_LOCKD_V4=y
1412CONFIG_EXPORTFS=m 1451CONFIG_EXPORTFS=m
@@ -1414,7 +1453,6 @@ CONFIG_NFS_ACL_SUPPORT=y
1414CONFIG_NFS_COMMON=y 1453CONFIG_NFS_COMMON=y
1415CONFIG_SUNRPC=y 1454CONFIG_SUNRPC=y
1416CONFIG_SUNRPC_GSS=y 1455CONFIG_SUNRPC_GSS=y
1417# CONFIG_SUNRPC_BIND34 is not set
1418CONFIG_RPCSEC_GSS_KRB5=y 1456CONFIG_RPCSEC_GSS_KRB5=y
1419# CONFIG_RPCSEC_GSS_SPKM3 is not set 1457# CONFIG_RPCSEC_GSS_SPKM3 is not set
1420# CONFIG_SMB_FS is not set 1458# CONFIG_SMB_FS is not set
@@ -1482,6 +1520,7 @@ CONFIG_BITREVERSE=y
1482# CONFIG_GENERIC_FIND_FIRST_BIT is not set 1520# CONFIG_GENERIC_FIND_FIRST_BIT is not set
1483CONFIG_CRC_CCITT=m 1521CONFIG_CRC_CCITT=m
1484# CONFIG_CRC16 is not set 1522# CONFIG_CRC16 is not set
1523CONFIG_CRC_T10DIF=y
1485CONFIG_CRC_ITU_T=m 1524CONFIG_CRC_ITU_T=m
1486CONFIG_CRC32=y 1525CONFIG_CRC32=y
1487# CONFIG_CRC7 is not set 1526# CONFIG_CRC7 is not set
@@ -1510,6 +1549,8 @@ CONFIG_MAGIC_SYSRQ=y
1510CONFIG_DEBUG_KERNEL=y 1549CONFIG_DEBUG_KERNEL=y
1511# CONFIG_DEBUG_SHIRQ is not set 1550# CONFIG_DEBUG_SHIRQ is not set
1512CONFIG_DETECT_SOFTLOCKUP=y 1551CONFIG_DETECT_SOFTLOCKUP=y
1552# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
1553CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
1513CONFIG_SCHED_DEBUG=y 1554CONFIG_SCHED_DEBUG=y
1514# CONFIG_SCHEDSTATS is not set 1555# CONFIG_SCHEDSTATS is not set
1515# CONFIG_TIMER_STATS is not set 1556# CONFIG_TIMER_STATS is not set
@@ -1527,17 +1568,29 @@ CONFIG_DEBUG_BUGVERBOSE=y
1527# CONFIG_DEBUG_INFO is not set 1568# CONFIG_DEBUG_INFO is not set
1528# CONFIG_DEBUG_VM is not set 1569# CONFIG_DEBUG_VM is not set
1529# CONFIG_DEBUG_WRITECOUNT is not set 1570# CONFIG_DEBUG_WRITECOUNT is not set
1571CONFIG_DEBUG_MEMORY_INIT=y
1530# CONFIG_DEBUG_LIST is not set 1572# CONFIG_DEBUG_LIST is not set
1531# CONFIG_DEBUG_SG is not set 1573# CONFIG_DEBUG_SG is not set
1532# CONFIG_BOOT_PRINTK_DELAY is not set 1574# CONFIG_BOOT_PRINTK_DELAY is not set
1533# CONFIG_RCU_TORTURE_TEST is not set 1575# CONFIG_RCU_TORTURE_TEST is not set
1534# CONFIG_BACKTRACE_SELF_TEST is not set 1576# CONFIG_BACKTRACE_SELF_TEST is not set
1535# CONFIG_FAULT_INJECTION is not set 1577# CONFIG_FAULT_INJECTION is not set
1578# CONFIG_LATENCYTOP is not set
1579CONFIG_SYSCTL_SYSCALL_CHECK=y
1580CONFIG_HAVE_FTRACE=y
1581CONFIG_HAVE_DYNAMIC_FTRACE=y
1582# CONFIG_FTRACE is not set
1583# CONFIG_SCHED_TRACER is not set
1584# CONFIG_CONTEXT_SWITCH_TRACER is not set
1536# CONFIG_SAMPLES is not set 1585# CONFIG_SAMPLES is not set
1586CONFIG_HAVE_ARCH_KGDB=y
1587# CONFIG_KGDB is not set
1537# CONFIG_DEBUG_STACKOVERFLOW is not set 1588# CONFIG_DEBUG_STACKOVERFLOW is not set
1538# CONFIG_DEBUG_STACK_USAGE is not set 1589# CONFIG_DEBUG_STACK_USAGE is not set
1539# CONFIG_DEBUG_PAGEALLOC is not set 1590# CONFIG_DEBUG_PAGEALLOC is not set
1540# CONFIG_DEBUGGER is not set 1591# CONFIG_CODE_PATCHING_SELFTEST is not set
1592# CONFIG_FTR_FIXUP_SELFTEST is not set
1593# CONFIG_XMON is not set
1541# CONFIG_IRQSTACKS is not set 1594# CONFIG_IRQSTACKS is not set
1542# CONFIG_BDI_SWITCH is not set 1595# CONFIG_BDI_SWITCH is not set
1543# CONFIG_BOOTX_TEXT is not set 1596# CONFIG_BOOTX_TEXT is not set
@@ -1556,6 +1609,7 @@ CONFIG_CRYPTO=y
1556# 1609#
1557CONFIG_CRYPTO_ALGAPI=y 1610CONFIG_CRYPTO_ALGAPI=y
1558CONFIG_CRYPTO_BLKCIPHER=y 1611CONFIG_CRYPTO_BLKCIPHER=y
1612CONFIG_CRYPTO_HASH=m
1559CONFIG_CRYPTO_MANAGER=y 1613CONFIG_CRYPTO_MANAGER=y
1560# CONFIG_CRYPTO_GF128MUL is not set 1614# CONFIG_CRYPTO_GF128MUL is not set
1561# CONFIG_CRYPTO_NULL is not set 1615# CONFIG_CRYPTO_NULL is not set
@@ -1594,6 +1648,10 @@ CONFIG_CRYPTO_CRC32C=m
1594CONFIG_CRYPTO_MD4=m 1648CONFIG_CRYPTO_MD4=m
1595CONFIG_CRYPTO_MD5=y 1649CONFIG_CRYPTO_MD5=y
1596CONFIG_CRYPTO_MICHAEL_MIC=m 1650CONFIG_CRYPTO_MICHAEL_MIC=m
1651# CONFIG_CRYPTO_RMD128 is not set
1652# CONFIG_CRYPTO_RMD160 is not set
1653# CONFIG_CRYPTO_RMD256 is not set
1654# CONFIG_CRYPTO_RMD320 is not set
1597CONFIG_CRYPTO_SHA1=m 1655CONFIG_CRYPTO_SHA1=m
1598# CONFIG_CRYPTO_SHA256 is not set 1656# CONFIG_CRYPTO_SHA256 is not set
1599# CONFIG_CRYPTO_SHA512 is not set 1657# CONFIG_CRYPTO_SHA512 is not set
@@ -1627,5 +1685,6 @@ CONFIG_CRYPTO_DEFLATE=m
1627# CONFIG_CRYPTO_LZO is not set 1685# CONFIG_CRYPTO_LZO is not set
1628CONFIG_CRYPTO_HW=y 1686CONFIG_CRYPTO_HW=y
1629# CONFIG_CRYPTO_DEV_HIFN_795X is not set 1687# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1688# CONFIG_CRYPTO_DEV_TALITOS is not set
1630# CONFIG_PPC_CLOCK is not set 1689# CONFIG_PPC_CLOCK is not set
1631# CONFIG_VIRTUALIZATION is not set 1690# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/configs/maple_defconfig b/arch/powerpc/configs/maple_defconfig
index 7a166a39d92d..1a3b6423222b 100644
--- a/arch/powerpc/configs/maple_defconfig
+++ b/arch/powerpc/configs/maple_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.24-rc4 3# Linux kernel version: 2.6.27-rc4
4# Thu Dec 6 16:48:26 2007 4# Tue Aug 26 13:18:58 2008
5# 5#
6CONFIG_PPC64=y 6CONFIG_PPC64=y
7 7
@@ -27,7 +27,12 @@ CONFIG_GENERIC_TIME=y
27CONFIG_GENERIC_TIME_VSYSCALL=y 27CONFIG_GENERIC_TIME_VSYSCALL=y
28CONFIG_GENERIC_CLOCKEVENTS=y 28CONFIG_GENERIC_CLOCKEVENTS=y
29CONFIG_GENERIC_HARDIRQS=y 29CONFIG_GENERIC_HARDIRQS=y
30CONFIG_HAVE_SETUP_PER_CPU_AREA=y
30CONFIG_IRQ_PER_CPU=y 31CONFIG_IRQ_PER_CPU=y
32CONFIG_STACKTRACE_SUPPORT=y
33CONFIG_HAVE_LATENCYTOP_SUPPORT=y
34CONFIG_TRACE_IRQFLAGS_SUPPORT=y
35CONFIG_LOCKDEP_SUPPORT=y
31CONFIG_RWSEM_XCHGADD_ALGORITHM=y 36CONFIG_RWSEM_XCHGADD_ALGORITHM=y
32CONFIG_ARCH_HAS_ILOG2_U32=y 37CONFIG_ARCH_HAS_ILOG2_U32=y
33CONFIG_ARCH_HAS_ILOG2_U64=y 38CONFIG_ARCH_HAS_ILOG2_U64=y
@@ -67,16 +72,20 @@ CONFIG_SYSVIPC_SYSCTL=y
67CONFIG_POSIX_MQUEUE=y 72CONFIG_POSIX_MQUEUE=y
68# CONFIG_BSD_PROCESS_ACCT is not set 73# CONFIG_BSD_PROCESS_ACCT is not set
69# CONFIG_TASKSTATS is not set 74# CONFIG_TASKSTATS is not set
70# CONFIG_USER_NS is not set
71# CONFIG_PID_NS is not set
72# CONFIG_AUDIT is not set 75# CONFIG_AUDIT is not set
73CONFIG_IKCONFIG=y 76CONFIG_IKCONFIG=y
74CONFIG_IKCONFIG_PROC=y 77CONFIG_IKCONFIG_PROC=y
75CONFIG_LOG_BUF_SHIFT=17 78CONFIG_LOG_BUF_SHIFT=17
76# CONFIG_CGROUPS is not set 79# CONFIG_CGROUPS is not set
77# CONFIG_FAIR_GROUP_SCHED is not set 80# CONFIG_GROUP_SCHED is not set
78CONFIG_SYSFS_DEPRECATED=y 81CONFIG_SYSFS_DEPRECATED=y
82CONFIG_SYSFS_DEPRECATED_V2=y
79# CONFIG_RELAY is not set 83# CONFIG_RELAY is not set
84CONFIG_NAMESPACES=y
85# CONFIG_UTS_NS is not set
86# CONFIG_IPC_NS is not set
87# CONFIG_USER_NS is not set
88# CONFIG_PID_NS is not set
80# CONFIG_BLK_DEV_INITRD is not set 89# CONFIG_BLK_DEV_INITRD is not set
81CONFIG_CC_OPTIMIZE_FOR_SIZE=y 90CONFIG_CC_OPTIMIZE_FOR_SIZE=y
82CONFIG_SYSCTL=y 91CONFIG_SYSCTL=y
@@ -89,11 +98,13 @@ CONFIG_HOTPLUG=y
89CONFIG_PRINTK=y 98CONFIG_PRINTK=y
90CONFIG_BUG=y 99CONFIG_BUG=y
91CONFIG_ELF_CORE=y 100CONFIG_ELF_CORE=y
101# CONFIG_COMPAT_BRK is not set
92CONFIG_BASE_FULL=y 102CONFIG_BASE_FULL=y
93CONFIG_FUTEX=y 103CONFIG_FUTEX=y
94CONFIG_ANON_INODES=y 104CONFIG_ANON_INODES=y
95CONFIG_EPOLL=y 105CONFIG_EPOLL=y
96CONFIG_SIGNALFD=y 106CONFIG_SIGNALFD=y
107CONFIG_TIMERFD=y
97CONFIG_EVENTFD=y 108CONFIG_EVENTFD=y
98CONFIG_SHMEM=y 109CONFIG_SHMEM=y
99CONFIG_VM_EVENT_COUNTERS=y 110CONFIG_VM_EVENT_COUNTERS=y
@@ -101,10 +112,28 @@ CONFIG_SLUB_DEBUG=y
101# CONFIG_SLAB is not set 112# CONFIG_SLAB is not set
102CONFIG_SLUB=y 113CONFIG_SLUB=y
103# CONFIG_SLOB is not set 114# CONFIG_SLOB is not set
115CONFIG_PROFILING=y
116# CONFIG_MARKERS is not set
117CONFIG_OPROFILE=m
118CONFIG_HAVE_OPROFILE=y
119CONFIG_KPROBES=y
120CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
121CONFIG_KRETPROBES=y
122CONFIG_HAVE_IOREMAP_PROT=y
123CONFIG_HAVE_KPROBES=y
124CONFIG_HAVE_KRETPROBES=y
125CONFIG_HAVE_ARCH_TRACEHOOK=y
126CONFIG_HAVE_DMA_ATTRS=y
127CONFIG_USE_GENERIC_SMP_HELPERS=y
128# CONFIG_HAVE_CLK is not set
129CONFIG_PROC_PAGE_MONITOR=y
130# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
131CONFIG_SLABINFO=y
104CONFIG_RT_MUTEXES=y 132CONFIG_RT_MUTEXES=y
105# CONFIG_TINY_SHMEM is not set 133# CONFIG_TINY_SHMEM is not set
106CONFIG_BASE_SMALL=0 134CONFIG_BASE_SMALL=0
107CONFIG_MODULES=y 135CONFIG_MODULES=y
136# CONFIG_MODULE_FORCE_LOAD is not set
108CONFIG_MODULE_UNLOAD=y 137CONFIG_MODULE_UNLOAD=y
109# CONFIG_MODULE_FORCE_UNLOAD is not set 138# CONFIG_MODULE_FORCE_UNLOAD is not set
110CONFIG_MODVERSIONS=y 139CONFIG_MODVERSIONS=y
@@ -114,6 +143,7 @@ CONFIG_STOP_MACHINE=y
114CONFIG_BLOCK=y 143CONFIG_BLOCK=y
115# CONFIG_BLK_DEV_IO_TRACE is not set 144# CONFIG_BLK_DEV_IO_TRACE is not set
116# CONFIG_BLK_DEV_BSG is not set 145# CONFIG_BLK_DEV_BSG is not set
146# CONFIG_BLK_DEV_INTEGRITY is not set
117CONFIG_BLOCK_COMPAT=y 147CONFIG_BLOCK_COMPAT=y
118 148
119# 149#
@@ -128,29 +158,26 @@ CONFIG_DEFAULT_AS=y
128# CONFIG_DEFAULT_CFQ is not set 158# CONFIG_DEFAULT_CFQ is not set
129# CONFIG_DEFAULT_NOOP is not set 159# CONFIG_DEFAULT_NOOP is not set
130CONFIG_DEFAULT_IOSCHED="anticipatory" 160CONFIG_DEFAULT_IOSCHED="anticipatory"
161CONFIG_CLASSIC_RCU=y
131 162
132# 163#
133# Platform support 164# Platform support
134# 165#
135CONFIG_PPC_MULTIPLATFORM=y 166CONFIG_PPC_MULTIPLATFORM=y
136# CONFIG_PPC_82xx is not set
137# CONFIG_PPC_83xx is not set
138# CONFIG_PPC_86xx is not set
139# CONFIG_PPC_PSERIES is not set 167# CONFIG_PPC_PSERIES is not set
140# CONFIG_PPC_ISERIES is not set 168# CONFIG_PPC_ISERIES is not set
141# CONFIG_PPC_MPC52xx is not set
142# CONFIG_PPC_MPC5200 is not set
143# CONFIG_PPC_PMAC is not set 169# CONFIG_PPC_PMAC is not set
144CONFIG_PPC_MAPLE=y 170CONFIG_PPC_MAPLE=y
145# CONFIG_PPC_PASEMI is not set 171# CONFIG_PPC_PASEMI is not set
146# CONFIG_PPC_CELLEB is not set
147# CONFIG_PPC_PS3 is not set 172# CONFIG_PPC_PS3 is not set
148# CONFIG_PPC_CELL is not set 173# CONFIG_PPC_CELL is not set
149# CONFIG_PPC_CELL_NATIVE is not set 174# CONFIG_PPC_CELL_NATIVE is not set
150# CONFIG_PPC_IBM_CELL_BLADE is not set 175# CONFIG_PPC_IBM_CELL_BLADE is not set
176# CONFIG_PPC_CELLEB is not set
151# CONFIG_PQ2ADS is not set 177# CONFIG_PQ2ADS is not set
152CONFIG_PPC_NATIVE=y 178CONFIG_PPC_NATIVE=y
153CONFIG_UDBG_RTAS_CONSOLE=y 179CONFIG_UDBG_RTAS_CONSOLE=y
180# CONFIG_IPIC is not set
154CONFIG_MPIC=y 181CONFIG_MPIC=y
155# CONFIG_MPIC_WEIRD is not set 182# CONFIG_MPIC_WEIRD is not set
156# CONFIG_PPC_I8259 is not set 183# CONFIG_PPC_I8259 is not set
@@ -166,7 +193,6 @@ CONFIG_PPC_970_NAP=y
166# CONFIG_PPC_INDIRECT_IO is not set 193# CONFIG_PPC_INDIRECT_IO is not set
167# CONFIG_GENERIC_IOMAP is not set 194# CONFIG_GENERIC_IOMAP is not set
168# CONFIG_CPU_FREQ is not set 195# CONFIG_CPU_FREQ is not set
169# CONFIG_CPM2 is not set
170# CONFIG_FSL_ULI1575 is not set 196# CONFIG_FSL_ULI1575 is not set
171 197
172# 198#
@@ -181,16 +207,19 @@ CONFIG_HZ_250=y
181# CONFIG_HZ_300 is not set 207# CONFIG_HZ_300 is not set
182# CONFIG_HZ_1000 is not set 208# CONFIG_HZ_1000 is not set
183CONFIG_HZ=250 209CONFIG_HZ=250
210CONFIG_SCHED_HRTICK=y
184CONFIG_PREEMPT_NONE=y 211CONFIG_PREEMPT_NONE=y
185# CONFIG_PREEMPT_VOLUNTARY is not set 212# CONFIG_PREEMPT_VOLUNTARY is not set
186# CONFIG_PREEMPT is not set 213# CONFIG_PREEMPT is not set
187# CONFIG_PREEMPT_BKL is not set
188CONFIG_BINFMT_ELF=y 214CONFIG_BINFMT_ELF=y
215CONFIG_COMPAT_BINFMT_ELF=y
189# CONFIG_BINFMT_MISC is not set 216# CONFIG_BINFMT_MISC is not set
190CONFIG_FORCE_MAX_ZONEORDER=13
191CONFIG_HUGETLB_PAGE_SIZE_VARIABLE=y 217CONFIG_HUGETLB_PAGE_SIZE_VARIABLE=y
192CONFIG_IOMMU_VMERGE=y 218CONFIG_IOMMU_VMERGE=y
219CONFIG_IOMMU_HELPER=y
193CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y 220CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
221CONFIG_ARCH_HAS_WALK_MEMORY=y
222CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
194CONFIG_KEXEC=y 223CONFIG_KEXEC=y
195# CONFIG_CRASH_DUMP is not set 224# CONFIG_CRASH_DUMP is not set
196CONFIG_IRQ_ALL_CPUS=y 225CONFIG_IRQ_ALL_CPUS=y
@@ -207,18 +236,21 @@ CONFIG_FLATMEM=y
207CONFIG_FLAT_NODE_MEM_MAP=y 236CONFIG_FLAT_NODE_MEM_MAP=y
208# CONFIG_SPARSEMEM_STATIC is not set 237# CONFIG_SPARSEMEM_STATIC is not set
209CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y 238CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
239CONFIG_PAGEFLAGS_EXTENDED=y
210CONFIG_SPLIT_PTLOCK_CPUS=4 240CONFIG_SPLIT_PTLOCK_CPUS=4
241# CONFIG_MIGRATION is not set
211CONFIG_RESOURCES_64BIT=y 242CONFIG_RESOURCES_64BIT=y
212CONFIG_ZONE_DMA_FLAG=1 243CONFIG_ZONE_DMA_FLAG=1
213CONFIG_BOUNCE=y 244CONFIG_BOUNCE=y
214# CONFIG_PPC_HAS_HASH_64K is not set 245# CONFIG_PPC_HAS_HASH_64K is not set
215# CONFIG_PPC_64K_PAGES is not set 246# CONFIG_PPC_64K_PAGES is not set
247CONFIG_FORCE_MAX_ZONEORDER=13
216# CONFIG_SCHED_SMT is not set 248# CONFIG_SCHED_SMT is not set
217CONFIG_PROC_DEVICETREE=y 249CONFIG_PROC_DEVICETREE=y
218# CONFIG_CMDLINE_BOOL is not set 250# CONFIG_CMDLINE_BOOL is not set
251CONFIG_EXTRA_TARGETS=""
219# CONFIG_PM is not set 252# CONFIG_PM is not set
220CONFIG_SECCOMP=y 253CONFIG_SECCOMP=y
221# CONFIG_WANT_DEVICE_TREE is not set
222CONFIG_ISA_DMA_API=y 254CONFIG_ISA_DMA_API=y
223 255
224# 256#
@@ -237,11 +269,10 @@ CONFIG_PCI_LEGACY=y
237# CONFIG_PCI_DEBUG is not set 269# CONFIG_PCI_DEBUG is not set
238# CONFIG_PCCARD is not set 270# CONFIG_PCCARD is not set
239# CONFIG_HOTPLUG_PCI is not set 271# CONFIG_HOTPLUG_PCI is not set
272# CONFIG_HAS_RAPIDIO is not set
273CONFIG_PAGE_OFFSET=0xc000000000000000
240CONFIG_KERNEL_START=0xc000000000000000 274CONFIG_KERNEL_START=0xc000000000000000
241 275CONFIG_PHYSICAL_START=0x00000000
242#
243# Networking
244#
245CONFIG_NET=y 276CONFIG_NET=y
246 277
247# 278#
@@ -254,6 +285,7 @@ CONFIG_XFRM=y
254CONFIG_XFRM_USER=m 285CONFIG_XFRM_USER=m
255# CONFIG_XFRM_SUB_POLICY is not set 286# CONFIG_XFRM_SUB_POLICY is not set
256# CONFIG_XFRM_MIGRATE is not set 287# CONFIG_XFRM_MIGRATE is not set
288# CONFIG_XFRM_STATISTICS is not set
257# CONFIG_NET_KEY is not set 289# CONFIG_NET_KEY is not set
258CONFIG_INET=y 290CONFIG_INET=y
259CONFIG_IP_MULTICAST=y 291CONFIG_IP_MULTICAST=y
@@ -284,8 +316,6 @@ CONFIG_TCP_CONG_CUBIC=y
284CONFIG_DEFAULT_TCP_CONG="cubic" 316CONFIG_DEFAULT_TCP_CONG="cubic"
285# CONFIG_TCP_MD5SIG is not set 317# CONFIG_TCP_MD5SIG is not set
286# CONFIG_IPV6 is not set 318# CONFIG_IPV6 is not set
287# CONFIG_INET6_XFRM_TUNNEL is not set
288# CONFIG_INET6_TUNNEL is not set
289# CONFIG_NETWORK_SECMARK is not set 319# CONFIG_NETWORK_SECMARK is not set
290# CONFIG_NETFILTER is not set 320# CONFIG_NETFILTER is not set
291# CONFIG_IP_DCCP is not set 321# CONFIG_IP_DCCP is not set
@@ -308,7 +338,9 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
308# Network testing 338# Network testing
309# 339#
310# CONFIG_NET_PKTGEN is not set 340# CONFIG_NET_PKTGEN is not set
341# CONFIG_NET_TCPPROBE is not set
311# CONFIG_HAMRADIO is not set 342# CONFIG_HAMRADIO is not set
343# CONFIG_CAN is not set
312# CONFIG_IRDA is not set 344# CONFIG_IRDA is not set
313# CONFIG_BT is not set 345# CONFIG_BT is not set
314# CONFIG_AF_RXRPC is not set 346# CONFIG_AF_RXRPC is not set
@@ -334,12 +366,15 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
334CONFIG_STANDALONE=y 366CONFIG_STANDALONE=y
335CONFIG_PREVENT_FIRMWARE_BUILD=y 367CONFIG_PREVENT_FIRMWARE_BUILD=y
336CONFIG_FW_LOADER=y 368CONFIG_FW_LOADER=y
369CONFIG_FIRMWARE_IN_KERNEL=y
370CONFIG_EXTRA_FIRMWARE=""
337# CONFIG_DEBUG_DRIVER is not set 371# CONFIG_DEBUG_DRIVER is not set
338# CONFIG_DEBUG_DEVRES is not set 372# CONFIG_DEBUG_DEVRES is not set
339# CONFIG_SYS_HYPERVISOR is not set 373# CONFIG_SYS_HYPERVISOR is not set
340# CONFIG_CONNECTOR is not set 374# CONFIG_CONNECTOR is not set
341# CONFIG_MTD is not set 375# CONFIG_MTD is not set
342CONFIG_OF_DEVICE=y 376CONFIG_OF_DEVICE=y
377CONFIG_OF_I2C=y
343# CONFIG_PARPORT is not set 378# CONFIG_PARPORT is not set
344CONFIG_BLK_DEV=y 379CONFIG_BLK_DEV=y
345# CONFIG_BLK_DEV_FD is not set 380# CONFIG_BLK_DEV_FD is not set
@@ -354,24 +389,30 @@ CONFIG_BLK_DEV=y
354CONFIG_BLK_DEV_RAM=y 389CONFIG_BLK_DEV_RAM=y
355CONFIG_BLK_DEV_RAM_COUNT=16 390CONFIG_BLK_DEV_RAM_COUNT=16
356CONFIG_BLK_DEV_RAM_SIZE=8192 391CONFIG_BLK_DEV_RAM_SIZE=8192
357CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 392# CONFIG_BLK_DEV_XIP is not set
358# CONFIG_CDROM_PKTCDVD is not set 393# CONFIG_CDROM_PKTCDVD is not set
359# CONFIG_ATA_OVER_ETH is not set 394# CONFIG_ATA_OVER_ETH is not set
395# CONFIG_BLK_DEV_HD is not set
360CONFIG_MISC_DEVICES=y 396CONFIG_MISC_DEVICES=y
361# CONFIG_PHANTOM is not set 397# CONFIG_PHANTOM is not set
362# CONFIG_EEPROM_93CX6 is not set 398# CONFIG_EEPROM_93CX6 is not set
363# CONFIG_SGI_IOC4 is not set 399# CONFIG_SGI_IOC4 is not set
364# CONFIG_TIFM_CORE is not set 400# CONFIG_TIFM_CORE is not set
401# CONFIG_ENCLOSURE_SERVICES is not set
402# CONFIG_HP_ILO is not set
403CONFIG_HAVE_IDE=y
365CONFIG_IDE=y 404CONFIG_IDE=y
366CONFIG_BLK_DEV_IDE=y 405CONFIG_BLK_DEV_IDE=y
367 406
368# 407#
369# Please see Documentation/ide.txt for help/info on IDE drives 408# Please see Documentation/ide/ide.txt for help/info on IDE drives
370# 409#
410CONFIG_IDE_TIMINGS=y
371# CONFIG_BLK_DEV_IDE_SATA is not set 411# CONFIG_BLK_DEV_IDE_SATA is not set
372CONFIG_BLK_DEV_IDEDISK=y 412CONFIG_BLK_DEV_IDEDISK=y
373# CONFIG_IDEDISK_MULTI_MODE is not set 413# CONFIG_IDEDISK_MULTI_MODE is not set
374CONFIG_BLK_DEV_IDECD=y 414CONFIG_BLK_DEV_IDECD=y
415CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y
375# CONFIG_BLK_DEV_IDETAPE is not set 416# CONFIG_BLK_DEV_IDETAPE is not set
376# CONFIG_BLK_DEV_IDEFLOPPY is not set 417# CONFIG_BLK_DEV_IDEFLOPPY is not set
377# CONFIG_BLK_DEV_IDESCSI is not set 418# CONFIG_BLK_DEV_IDESCSI is not set
@@ -381,14 +422,13 @@ CONFIG_IDE_PROC_FS=y
381# 422#
382# IDE chipset support/bugfixes 423# IDE chipset support/bugfixes
383# 424#
384CONFIG_IDE_GENERIC=y
385# CONFIG_BLK_DEV_PLATFORM is not set 425# CONFIG_BLK_DEV_PLATFORM is not set
426CONFIG_BLK_DEV_IDEDMA_SFF=y
386 427
387# 428#
388# PCI IDE chipsets support 429# PCI IDE chipsets support
389# 430#
390CONFIG_BLK_DEV_IDEPCI=y 431CONFIG_BLK_DEV_IDEPCI=y
391CONFIG_IDEPCI_SHARE_IRQ=y
392CONFIG_IDEPCI_PCIBUS_ORDER=y 432CONFIG_IDEPCI_PCIBUS_ORDER=y
393# CONFIG_BLK_DEV_OFFBOARD is not set 433# CONFIG_BLK_DEV_OFFBOARD is not set
394CONFIG_BLK_DEV_GENERIC=y 434CONFIG_BLK_DEV_GENERIC=y
@@ -399,10 +439,8 @@ CONFIG_BLK_DEV_IDEDMA_PCI=y
399CONFIG_BLK_DEV_AMD74XX=y 439CONFIG_BLK_DEV_AMD74XX=y
400# CONFIG_BLK_DEV_CMD64X is not set 440# CONFIG_BLK_DEV_CMD64X is not set
401# CONFIG_BLK_DEV_TRIFLEX is not set 441# CONFIG_BLK_DEV_TRIFLEX is not set
402# CONFIG_BLK_DEV_CY82C693 is not set
403# CONFIG_BLK_DEV_CS5520 is not set 442# CONFIG_BLK_DEV_CS5520 is not set
404# CONFIG_BLK_DEV_CS5530 is not set 443# CONFIG_BLK_DEV_CS5530 is not set
405# CONFIG_BLK_DEV_HPT34X is not set
406# CONFIG_BLK_DEV_HPT366 is not set 444# CONFIG_BLK_DEV_HPT366 is not set
407# CONFIG_BLK_DEV_JMICRON is not set 445# CONFIG_BLK_DEV_JMICRON is not set
408# CONFIG_BLK_DEV_SC1200 is not set 446# CONFIG_BLK_DEV_SC1200 is not set
@@ -419,10 +457,7 @@ CONFIG_BLK_DEV_AMD74XX=y
419# CONFIG_BLK_DEV_TRM290 is not set 457# CONFIG_BLK_DEV_TRM290 is not set
420# CONFIG_BLK_DEV_VIA82CXXX is not set 458# CONFIG_BLK_DEV_VIA82CXXX is not set
421# CONFIG_BLK_DEV_TC86C001 is not set 459# CONFIG_BLK_DEV_TC86C001 is not set
422# CONFIG_IDE_ARM is not set
423CONFIG_BLK_DEV_IDEDMA=y 460CONFIG_BLK_DEV_IDEDMA=y
424CONFIG_IDE_ARCH_OBSOLETE_INIT=y
425# CONFIG_BLK_DEV_HD is not set
426 461
427# 462#
428# SCSI device support 463# SCSI device support
@@ -483,6 +518,7 @@ CONFIG_SCSI_LOWLEVEL=y
483# CONFIG_SCSI_IPS is not set 518# CONFIG_SCSI_IPS is not set
484# CONFIG_SCSI_INITIO is not set 519# CONFIG_SCSI_INITIO is not set
485# CONFIG_SCSI_INIA100 is not set 520# CONFIG_SCSI_INIA100 is not set
521# CONFIG_SCSI_MVSAS is not set
486# CONFIG_SCSI_STEX is not set 522# CONFIG_SCSI_STEX is not set
487# CONFIG_SCSI_SYM53C8XX_2 is not set 523# CONFIG_SCSI_SYM53C8XX_2 is not set
488CONFIG_SCSI_IPR=y 524CONFIG_SCSI_IPR=y
@@ -496,9 +532,13 @@ CONFIG_SCSI_IPR_DUMP=y
496# CONFIG_SCSI_DC390T is not set 532# CONFIG_SCSI_DC390T is not set
497# CONFIG_SCSI_DEBUG is not set 533# CONFIG_SCSI_DEBUG is not set
498# CONFIG_SCSI_SRP is not set 534# CONFIG_SCSI_SRP is not set
535# CONFIG_SCSI_DH is not set
499CONFIG_ATA=y 536CONFIG_ATA=y
500CONFIG_ATA_NONSTANDARD=y 537CONFIG_ATA_NONSTANDARD=y
538CONFIG_SATA_PMP=y
501# CONFIG_SATA_AHCI is not set 539# CONFIG_SATA_AHCI is not set
540# CONFIG_SATA_SIL24 is not set
541CONFIG_ATA_SFF=y
502# CONFIG_SATA_SVW is not set 542# CONFIG_SATA_SVW is not set
503# CONFIG_ATA_PIIX is not set 543# CONFIG_ATA_PIIX is not set
504# CONFIG_SATA_MV is not set 544# CONFIG_SATA_MV is not set
@@ -508,7 +548,6 @@ CONFIG_ATA_NONSTANDARD=y
508# CONFIG_SATA_PROMISE is not set 548# CONFIG_SATA_PROMISE is not set
509# CONFIG_SATA_SX4 is not set 549# CONFIG_SATA_SX4 is not set
510# CONFIG_SATA_SIL is not set 550# CONFIG_SATA_SIL is not set
511# CONFIG_SATA_SIL24 is not set
512# CONFIG_SATA_SIS is not set 551# CONFIG_SATA_SIS is not set
513# CONFIG_SATA_ULI is not set 552# CONFIG_SATA_ULI is not set
514# CONFIG_SATA_VIA is not set 553# CONFIG_SATA_VIA is not set
@@ -537,6 +576,7 @@ CONFIG_ATA_NONSTANDARD=y
537# CONFIG_PATA_MPIIX is not set 576# CONFIG_PATA_MPIIX is not set
538# CONFIG_PATA_OLDPIIX is not set 577# CONFIG_PATA_OLDPIIX is not set
539# CONFIG_PATA_NETCELL is not set 578# CONFIG_PATA_NETCELL is not set
579# CONFIG_PATA_NINJA32 is not set
540# CONFIG_PATA_NS87410 is not set 580# CONFIG_PATA_NS87410 is not set
541# CONFIG_PATA_NS87415 is not set 581# CONFIG_PATA_NS87415 is not set
542# CONFIG_PATA_OPTI is not set 582# CONFIG_PATA_OPTI is not set
@@ -551,27 +591,47 @@ CONFIG_ATA_NONSTANDARD=y
551# CONFIG_PATA_SIS is not set 591# CONFIG_PATA_SIS is not set
552# CONFIG_PATA_VIA is not set 592# CONFIG_PATA_VIA is not set
553# CONFIG_PATA_WINBOND is not set 593# CONFIG_PATA_WINBOND is not set
594# CONFIG_PATA_PLATFORM is not set
595# CONFIG_PATA_SCH is not set
554# CONFIG_MD is not set 596# CONFIG_MD is not set
555# CONFIG_FUSION is not set 597# CONFIG_FUSION is not set
556 598
557# 599#
558# IEEE 1394 (FireWire) support 600# IEEE 1394 (FireWire) support
559# 601#
602
603#
604# Enable only one of the two stacks, unless you know what you are doing
605#
560# CONFIG_FIREWIRE is not set 606# CONFIG_FIREWIRE is not set
561# CONFIG_IEEE1394 is not set 607# CONFIG_IEEE1394 is not set
562# CONFIG_I2O is not set 608# CONFIG_I2O is not set
563# CONFIG_MACINTOSH_DRIVERS is not set 609# CONFIG_MACINTOSH_DRIVERS is not set
564CONFIG_NETDEVICES=y 610CONFIG_NETDEVICES=y
565# CONFIG_NETDEVICES_MULTIQUEUE is not set
566# CONFIG_DUMMY is not set 611# CONFIG_DUMMY is not set
567# CONFIG_BONDING is not set 612# CONFIG_BONDING is not set
568# CONFIG_MACVLAN is not set 613# CONFIG_MACVLAN is not set
569# CONFIG_EQUALIZER is not set 614# CONFIG_EQUALIZER is not set
570# CONFIG_TUN is not set 615# CONFIG_TUN is not set
571# CONFIG_VETH is not set 616# CONFIG_VETH is not set
572# CONFIG_IP1000 is not set
573# CONFIG_ARCNET is not set 617# CONFIG_ARCNET is not set
574# CONFIG_PHYLIB is not set 618CONFIG_PHYLIB=y
619
620#
621# MII PHY device drivers
622#
623# CONFIG_MARVELL_PHY is not set
624# CONFIG_DAVICOM_PHY is not set
625# CONFIG_QSEMI_PHY is not set
626# CONFIG_LXT_PHY is not set
627# CONFIG_CICADA_PHY is not set
628# CONFIG_VITESSE_PHY is not set
629# CONFIG_SMSC_PHY is not set
630# CONFIG_BROADCOM_PHY is not set
631# CONFIG_ICPLUS_PHY is not set
632# CONFIG_REALTEK_PHY is not set
633# CONFIG_FIXED_PHY is not set
634# CONFIG_MDIO_BITBANG is not set
575CONFIG_NET_ETHERNET=y 635CONFIG_NET_ETHERNET=y
576CONFIG_MII=y 636CONFIG_MII=y
577# CONFIG_HAPPYMEAL is not set 637# CONFIG_HAPPYMEAL is not set
@@ -587,7 +647,6 @@ CONFIG_MII=y
587CONFIG_NET_PCI=y 647CONFIG_NET_PCI=y
588# CONFIG_PCNET32 is not set 648# CONFIG_PCNET32 is not set
589CONFIG_AMD8111_ETH=y 649CONFIG_AMD8111_ETH=y
590# CONFIG_AMD8111E_NAPI is not set
591# CONFIG_ADAPTEC_STARFIRE is not set 650# CONFIG_ADAPTEC_STARFIRE is not set
592# CONFIG_B44 is not set 651# CONFIG_B44 is not set
593# CONFIG_FORCEDETH is not set 652# CONFIG_FORCEDETH is not set
@@ -598,18 +657,21 @@ CONFIG_AMD8111_ETH=y
598# CONFIG_NE2K_PCI is not set 657# CONFIG_NE2K_PCI is not set
599# CONFIG_8139CP is not set 658# CONFIG_8139CP is not set
600# CONFIG_8139TOO is not set 659# CONFIG_8139TOO is not set
660# CONFIG_R6040 is not set
601# CONFIG_SIS900 is not set 661# CONFIG_SIS900 is not set
602# CONFIG_EPIC100 is not set 662# CONFIG_EPIC100 is not set
603# CONFIG_SUNDANCE is not set 663# CONFIG_SUNDANCE is not set
664# CONFIG_TLAN is not set
604# CONFIG_VIA_RHINE is not set 665# CONFIG_VIA_RHINE is not set
605# CONFIG_SC92031 is not set 666# CONFIG_SC92031 is not set
606CONFIG_NETDEV_1000=y 667CONFIG_NETDEV_1000=y
607# CONFIG_ACENIC is not set 668# CONFIG_ACENIC is not set
608# CONFIG_DL2K is not set 669# CONFIG_DL2K is not set
609CONFIG_E1000=y 670CONFIG_E1000=y
610# CONFIG_E1000_NAPI is not set
611# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set 671# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
612# CONFIG_E1000E is not set 672# CONFIG_E1000E is not set
673# CONFIG_IP1000 is not set
674# CONFIG_IGB is not set
613# CONFIG_NS83820 is not set 675# CONFIG_NS83820 is not set
614# CONFIG_HAMACHI is not set 676# CONFIG_HAMACHI is not set
615# CONFIG_YELLOWFIN is not set 677# CONFIG_YELLOWFIN is not set
@@ -617,12 +679,12 @@ CONFIG_E1000=y
617# CONFIG_SIS190 is not set 679# CONFIG_SIS190 is not set
618# CONFIG_SKGE is not set 680# CONFIG_SKGE is not set
619# CONFIG_SKY2 is not set 681# CONFIG_SKY2 is not set
620# CONFIG_SK98LIN is not set
621# CONFIG_VIA_VELOCITY is not set 682# CONFIG_VIA_VELOCITY is not set
622CONFIG_TIGON3=y 683CONFIG_TIGON3=y
623# CONFIG_BNX2 is not set 684# CONFIG_BNX2 is not set
624# CONFIG_QLA3XXX is not set 685# CONFIG_QLA3XXX is not set
625# CONFIG_ATL1 is not set 686# CONFIG_ATL1 is not set
687# CONFIG_ATL1E is not set
626CONFIG_NETDEV_10000=y 688CONFIG_NETDEV_10000=y
627# CONFIG_CHELSIO_T1 is not set 689# CONFIG_CHELSIO_T1 is not set
628# CONFIG_CHELSIO_T3 is not set 690# CONFIG_CHELSIO_T3 is not set
@@ -632,9 +694,10 @@ CONFIG_NETDEV_10000=y
632# CONFIG_MYRI10GE is not set 694# CONFIG_MYRI10GE is not set
633# CONFIG_NETXEN_NIC is not set 695# CONFIG_NETXEN_NIC is not set
634# CONFIG_NIU is not set 696# CONFIG_NIU is not set
635# CONFIG_PASEMI_MAC is not set
636# CONFIG_MLX4_CORE is not set 697# CONFIG_MLX4_CORE is not set
637# CONFIG_TEHUTI is not set 698# CONFIG_TEHUTI is not set
699# CONFIG_BNX2X is not set
700# CONFIG_SFC is not set
638# CONFIG_TR is not set 701# CONFIG_TR is not set
639 702
640# 703#
@@ -642,6 +705,7 @@ CONFIG_NETDEV_10000=y
642# 705#
643# CONFIG_WLAN_PRE80211 is not set 706# CONFIG_WLAN_PRE80211 is not set
644# CONFIG_WLAN_80211 is not set 707# CONFIG_WLAN_80211 is not set
708# CONFIG_IWLWIFI_LEDS is not set
645 709
646# 710#
647# USB Network Adapters 711# USB Network Adapters
@@ -657,7 +721,6 @@ CONFIG_USB_PEGASUS=y
657# CONFIG_PPP is not set 721# CONFIG_PPP is not set
658# CONFIG_SLIP is not set 722# CONFIG_SLIP is not set
659# CONFIG_NET_FC is not set 723# CONFIG_NET_FC is not set
660# CONFIG_SHAPER is not set
661# CONFIG_NETCONSOLE is not set 724# CONFIG_NETCONSOLE is not set
662# CONFIG_NETPOLL is not set 725# CONFIG_NETPOLL is not set
663# CONFIG_NET_POLL_CONTROLLER is not set 726# CONFIG_NET_POLL_CONTROLLER is not set
@@ -702,10 +765,13 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=1200
702# Character devices 765# Character devices
703# 766#
704CONFIG_VT=y 767CONFIG_VT=y
768CONFIG_CONSOLE_TRANSLATIONS=y
705CONFIG_VT_CONSOLE=y 769CONFIG_VT_CONSOLE=y
706CONFIG_HW_CONSOLE=y 770CONFIG_HW_CONSOLE=y
707# CONFIG_VT_HW_CONSOLE_BINDING is not set 771# CONFIG_VT_HW_CONSOLE_BINDING is not set
772CONFIG_DEVKMEM=y
708# CONFIG_SERIAL_NONSTANDARD is not set 773# CONFIG_SERIAL_NONSTANDARD is not set
774# CONFIG_NOZOMI is not set
709 775
710# 776#
711# Serial drivers 777# Serial drivers
@@ -742,16 +808,14 @@ CONFIG_DEVPORT=y
742CONFIG_I2C=y 808CONFIG_I2C=y
743CONFIG_I2C_BOARDINFO=y 809CONFIG_I2C_BOARDINFO=y
744CONFIG_I2C_CHARDEV=y 810CONFIG_I2C_CHARDEV=y
811CONFIG_I2C_HELPER_AUTO=y
745 812
746# 813#
747# I2C Algorithms 814# I2C Hardware Bus support
748# 815#
749CONFIG_I2C_ALGOBIT=y
750# CONFIG_I2C_ALGOPCF is not set
751# CONFIG_I2C_ALGOPCA is not set
752 816
753# 817#
754# I2C Hardware Bus support 818# PC SMBus host controller drivers
755# 819#
756# CONFIG_I2C_ALI1535 is not set 820# CONFIG_I2C_ALI1535 is not set
757# CONFIG_I2C_ALI1563 is not set 821# CONFIG_I2C_ALI1563 is not set
@@ -759,32 +823,47 @@ CONFIG_I2C_ALGOBIT=y
759# CONFIG_I2C_AMD756 is not set 823# CONFIG_I2C_AMD756 is not set
760CONFIG_I2C_AMD8111=y 824CONFIG_I2C_AMD8111=y
761# CONFIG_I2C_I801 is not set 825# CONFIG_I2C_I801 is not set
762# CONFIG_I2C_I810 is not set 826# CONFIG_I2C_ISCH is not set
763# CONFIG_I2C_PIIX4 is not set 827# CONFIG_I2C_PIIX4 is not set
764# CONFIG_I2C_NFORCE2 is not set 828# CONFIG_I2C_NFORCE2 is not set
765# CONFIG_I2C_OCORES is not set
766# CONFIG_I2C_PARPORT_LIGHT is not set
767# CONFIG_I2C_PROSAVAGE is not set
768# CONFIG_I2C_SAVAGE4 is not set
769# CONFIG_I2C_SIMTEC is not set
770# CONFIG_I2C_SIS5595 is not set 829# CONFIG_I2C_SIS5595 is not set
771# CONFIG_I2C_SIS630 is not set 830# CONFIG_I2C_SIS630 is not set
772# CONFIG_I2C_SIS96X is not set 831# CONFIG_I2C_SIS96X is not set
773# CONFIG_I2C_TAOS_EVM is not set
774# CONFIG_I2C_STUB is not set
775# CONFIG_I2C_TINY_USB is not set
776# CONFIG_I2C_VIA is not set 832# CONFIG_I2C_VIA is not set
777# CONFIG_I2C_VIAPRO is not set 833# CONFIG_I2C_VIAPRO is not set
834
835#
836# I2C system bus drivers (mostly embedded / system-on-chip)
837#
838# CONFIG_I2C_OCORES is not set
839# CONFIG_I2C_SIMTEC is not set
840
841#
842# External I2C/SMBus adapter drivers
843#
844# CONFIG_I2C_PARPORT_LIGHT is not set
845# CONFIG_I2C_TAOS_EVM is not set
846# CONFIG_I2C_TINY_USB is not set
847
848#
849# Graphics adapter I2C/DDC channel drivers
850#
778# CONFIG_I2C_VOODOO3 is not set 851# CONFIG_I2C_VOODOO3 is not set
779 852
780# 853#
854# Other I2C/SMBus bus drivers
855#
856# CONFIG_I2C_PCA_PLATFORM is not set
857# CONFIG_I2C_STUB is not set
858
859#
781# Miscellaneous I2C Chip support 860# Miscellaneous I2C Chip support
782# 861#
783# CONFIG_SENSORS_DS1337 is not set
784# CONFIG_SENSORS_DS1374 is not set
785# CONFIG_DS1682 is not set 862# CONFIG_DS1682 is not set
863# CONFIG_AT24 is not set
786# CONFIG_SENSORS_EEPROM is not set 864# CONFIG_SENSORS_EEPROM is not set
787# CONFIG_SENSORS_PCF8574 is not set 865# CONFIG_SENSORS_PCF8574 is not set
866# CONFIG_PCF8575 is not set
788# CONFIG_SENSORS_PCA9539 is not set 867# CONFIG_SENSORS_PCA9539 is not set
789# CONFIG_SENSORS_PCF8591 is not set 868# CONFIG_SENSORS_PCF8591 is not set
790# CONFIG_SENSORS_MAX6875 is not set 869# CONFIG_SENSORS_MAX6875 is not set
@@ -793,15 +872,14 @@ CONFIG_I2C_AMD8111=y
793# CONFIG_I2C_DEBUG_ALGO is not set 872# CONFIG_I2C_DEBUG_ALGO is not set
794# CONFIG_I2C_DEBUG_BUS is not set 873# CONFIG_I2C_DEBUG_BUS is not set
795# CONFIG_I2C_DEBUG_CHIP is not set 874# CONFIG_I2C_DEBUG_CHIP is not set
796
797#
798# SPI support
799#
800# CONFIG_SPI is not set 875# CONFIG_SPI is not set
801# CONFIG_SPI_MASTER is not set 876CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
877# CONFIG_GPIOLIB is not set
802# CONFIG_W1 is not set 878# CONFIG_W1 is not set
803# CONFIG_POWER_SUPPLY is not set 879# CONFIG_POWER_SUPPLY is not set
804# CONFIG_HWMON is not set 880# CONFIG_HWMON is not set
881# CONFIG_THERMAL is not set
882# CONFIG_THERMAL_HWMON is not set
805# CONFIG_WATCHDOG is not set 883# CONFIG_WATCHDOG is not set
806 884
807# 885#
@@ -813,13 +891,25 @@ CONFIG_SSB_POSSIBLE=y
813# 891#
814# Multifunction device drivers 892# Multifunction device drivers
815# 893#
894# CONFIG_MFD_CORE is not set
816# CONFIG_MFD_SM501 is not set 895# CONFIG_MFD_SM501 is not set
896# CONFIG_HTC_PASIC3 is not set
897# CONFIG_MFD_TMIO is not set
817 898
818# 899#
819# Multimedia devices 900# Multimedia devices
820# 901#
902
903#
904# Multimedia core support
905#
821# CONFIG_VIDEO_DEV is not set 906# CONFIG_VIDEO_DEV is not set
822# CONFIG_DVB_CORE is not set 907# CONFIG_DVB_CORE is not set
908# CONFIG_VIDEO_MEDIA is not set
909
910#
911# Multimedia drivers
912#
823# CONFIG_DAB is not set 913# CONFIG_DAB is not set
824 914
825# 915#
@@ -842,10 +932,6 @@ CONFIG_SSB_POSSIBLE=y
842# 932#
843# CONFIG_VGA_CONSOLE is not set 933# CONFIG_VGA_CONSOLE is not set
844CONFIG_DUMMY_CONSOLE=y 934CONFIG_DUMMY_CONSOLE=y
845
846#
847# Sound
848#
849# CONFIG_SOUND is not set 935# CONFIG_SOUND is not set
850CONFIG_HID_SUPPORT=y 936CONFIG_HID_SUPPORT=y
851CONFIG_HID=y 937CONFIG_HID=y
@@ -865,6 +951,7 @@ CONFIG_USB_ARCH_HAS_OHCI=y
865CONFIG_USB_ARCH_HAS_EHCI=y 951CONFIG_USB_ARCH_HAS_EHCI=y
866CONFIG_USB=y 952CONFIG_USB=y
867# CONFIG_USB_DEBUG is not set 953# CONFIG_USB_DEBUG is not set
954# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
868 955
869# 956#
870# Miscellaneous USB options 957# Miscellaneous USB options
@@ -873,15 +960,18 @@ CONFIG_USB_DEVICEFS=y
873CONFIG_USB_DEVICE_CLASS=y 960CONFIG_USB_DEVICE_CLASS=y
874# CONFIG_USB_DYNAMIC_MINORS is not set 961# CONFIG_USB_DYNAMIC_MINORS is not set
875# CONFIG_USB_OTG is not set 962# CONFIG_USB_OTG is not set
963CONFIG_USB_MON=y
876 964
877# 965#
878# USB Host Controller Drivers 966# USB Host Controller Drivers
879# 967#
968# CONFIG_USB_C67X00_HCD is not set
880CONFIG_USB_EHCI_HCD=y 969CONFIG_USB_EHCI_HCD=y
881CONFIG_USB_EHCI_SPLIT_ISO=y
882CONFIG_USB_EHCI_ROOT_HUB_TT=y 970CONFIG_USB_EHCI_ROOT_HUB_TT=y
883# CONFIG_USB_EHCI_TT_NEWSCHED is not set 971# CONFIG_USB_EHCI_TT_NEWSCHED is not set
972# CONFIG_USB_EHCI_HCD_PPC_OF is not set
884# CONFIG_USB_ISP116X_HCD is not set 973# CONFIG_USB_ISP116X_HCD is not set
974# CONFIG_USB_ISP1760_HCD is not set
885CONFIG_USB_OHCI_HCD=y 975CONFIG_USB_OHCI_HCD=y
886# CONFIG_USB_OHCI_HCD_PPC_OF is not set 976# CONFIG_USB_OHCI_HCD_PPC_OF is not set
887# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set 977# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
@@ -896,6 +986,7 @@ CONFIG_USB_UHCI_HCD=y
896# 986#
897# CONFIG_USB_ACM is not set 987# CONFIG_USB_ACM is not set
898# CONFIG_USB_PRINTER is not set 988# CONFIG_USB_PRINTER is not set
989# CONFIG_USB_WDM is not set
899 990
900# 991#
901# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 992# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
@@ -912,20 +1003,15 @@ CONFIG_USB_UHCI_HCD=y
912# 1003#
913# CONFIG_USB_MDC800 is not set 1004# CONFIG_USB_MDC800 is not set
914# CONFIG_USB_MICROTEK is not set 1005# CONFIG_USB_MICROTEK is not set
915CONFIG_USB_MON=y
916 1006
917# 1007#
918# USB port drivers 1008# USB port drivers
919# 1009#
920
921#
922# USB Serial Converter support
923#
924CONFIG_USB_SERIAL=y 1010CONFIG_USB_SERIAL=y
925# CONFIG_USB_SERIAL_CONSOLE is not set 1011# CONFIG_USB_SERIAL_CONSOLE is not set
1012CONFIG_USB_EZUSB=y
926CONFIG_USB_SERIAL_GENERIC=y 1013CONFIG_USB_SERIAL_GENERIC=y
927# CONFIG_USB_SERIAL_AIRCABLE is not set 1014# CONFIG_USB_SERIAL_AIRCABLE is not set
928# CONFIG_USB_SERIAL_AIRPRIME is not set
929# CONFIG_USB_SERIAL_ARK3116 is not set 1015# CONFIG_USB_SERIAL_ARK3116 is not set
930# CONFIG_USB_SERIAL_BELKIN is not set 1016# CONFIG_USB_SERIAL_BELKIN is not set
931# CONFIG_USB_SERIAL_CH341 is not set 1017# CONFIG_USB_SERIAL_CH341 is not set
@@ -943,6 +1029,7 @@ CONFIG_USB_SERIAL_CYPRESS_M8=m
943# CONFIG_USB_SERIAL_EDGEPORT_TI is not set 1029# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
944CONFIG_USB_SERIAL_GARMIN=m 1030CONFIG_USB_SERIAL_GARMIN=m
945CONFIG_USB_SERIAL_IPW=m 1031CONFIG_USB_SERIAL_IPW=m
1032# CONFIG_USB_SERIAL_IUU is not set
946# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set 1033# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
947CONFIG_USB_SERIAL_KEYSPAN=y 1034CONFIG_USB_SERIAL_KEYSPAN=y
948CONFIG_USB_SERIAL_KEYSPAN_MPR=y 1035CONFIG_USB_SERIAL_KEYSPAN_MPR=y
@@ -962,9 +1049,11 @@ CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y
962# CONFIG_USB_SERIAL_MCT_U232 is not set 1049# CONFIG_USB_SERIAL_MCT_U232 is not set
963# CONFIG_USB_SERIAL_MOS7720 is not set 1050# CONFIG_USB_SERIAL_MOS7720 is not set
964# CONFIG_USB_SERIAL_MOS7840 is not set 1051# CONFIG_USB_SERIAL_MOS7840 is not set
1052# CONFIG_USB_SERIAL_MOTOROLA is not set
965# CONFIG_USB_SERIAL_NAVMAN is not set 1053# CONFIG_USB_SERIAL_NAVMAN is not set
966# CONFIG_USB_SERIAL_PL2303 is not set 1054# CONFIG_USB_SERIAL_PL2303 is not set
967# CONFIG_USB_SERIAL_OTI6858 is not set 1055# CONFIG_USB_SERIAL_OTI6858 is not set
1056# CONFIG_USB_SERIAL_SPCP8X5 is not set
968# CONFIG_USB_SERIAL_HP4X is not set 1057# CONFIG_USB_SERIAL_HP4X is not set
969# CONFIG_USB_SERIAL_SAFE is not set 1058# CONFIG_USB_SERIAL_SAFE is not set
970# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set 1059# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
@@ -974,7 +1063,6 @@ CONFIG_USB_SERIAL_TI=m
974# CONFIG_USB_SERIAL_OPTION is not set 1063# CONFIG_USB_SERIAL_OPTION is not set
975# CONFIG_USB_SERIAL_OMNINET is not set 1064# CONFIG_USB_SERIAL_OMNINET is not set
976# CONFIG_USB_SERIAL_DEBUG is not set 1065# CONFIG_USB_SERIAL_DEBUG is not set
977CONFIG_USB_EZUSB=y
978 1066
979# 1067#
980# USB Miscellaneous drivers 1068# USB Miscellaneous drivers
@@ -982,7 +1070,6 @@ CONFIG_USB_EZUSB=y
982# CONFIG_USB_EMI62 is not set 1070# CONFIG_USB_EMI62 is not set
983# CONFIG_USB_EMI26 is not set 1071# CONFIG_USB_EMI26 is not set
984# CONFIG_USB_ADUTUX is not set 1072# CONFIG_USB_ADUTUX is not set
985# CONFIG_USB_AUERSWALD is not set
986# CONFIG_USB_RIO500 is not set 1073# CONFIG_USB_RIO500 is not set
987# CONFIG_USB_LEGOTOWER is not set 1074# CONFIG_USB_LEGOTOWER is not set
988# CONFIG_USB_LCD is not set 1075# CONFIG_USB_LCD is not set
@@ -999,24 +1086,16 @@ CONFIG_USB_EZUSB=y
999# CONFIG_USB_TRANCEVIBRATOR is not set 1086# CONFIG_USB_TRANCEVIBRATOR is not set
1000# CONFIG_USB_IOWARRIOR is not set 1087# CONFIG_USB_IOWARRIOR is not set
1001# CONFIG_USB_TEST is not set 1088# CONFIG_USB_TEST is not set
1002 1089# CONFIG_USB_ISIGHTFW is not set
1003#
1004# USB DSL modem support
1005#
1006
1007#
1008# USB Gadget Support
1009#
1010# CONFIG_USB_GADGET is not set 1090# CONFIG_USB_GADGET is not set
1011# CONFIG_MMC is not set 1091# CONFIG_MMC is not set
1092# CONFIG_MEMSTICK is not set
1012# CONFIG_NEW_LEDS is not set 1093# CONFIG_NEW_LEDS is not set
1094# CONFIG_ACCESSIBILITY is not set
1013# CONFIG_INFINIBAND is not set 1095# CONFIG_INFINIBAND is not set
1014# CONFIG_EDAC is not set 1096# CONFIG_EDAC is not set
1015# CONFIG_RTC_CLASS is not set 1097# CONFIG_RTC_CLASS is not set
1016 1098# CONFIG_DMADEVICES is not set
1017#
1018# Userspace I/O
1019#
1020# CONFIG_UIO is not set 1099# CONFIG_UIO is not set
1021 1100
1022# 1101#
@@ -1037,12 +1116,10 @@ CONFIG_FS_POSIX_ACL=y
1037# CONFIG_XFS_FS is not set 1116# CONFIG_XFS_FS is not set
1038# CONFIG_GFS2_FS is not set 1117# CONFIG_GFS2_FS is not set
1039# CONFIG_OCFS2_FS is not set 1118# CONFIG_OCFS2_FS is not set
1040# CONFIG_MINIX_FS is not set 1119CONFIG_DNOTIFY=y
1041# CONFIG_ROMFS_FS is not set
1042CONFIG_INOTIFY=y 1120CONFIG_INOTIFY=y
1043CONFIG_INOTIFY_USER=y 1121CONFIG_INOTIFY_USER=y
1044# CONFIG_QUOTA is not set 1122# CONFIG_QUOTA is not set
1045CONFIG_DNOTIFY=y
1046# CONFIG_AUTOFS_FS is not set 1123# CONFIG_AUTOFS_FS is not set
1047# CONFIG_AUTOFS4_FS is not set 1124# CONFIG_AUTOFS4_FS is not set
1048# CONFIG_FUSE_FS is not set 1125# CONFIG_FUSE_FS is not set
@@ -1088,8 +1165,11 @@ CONFIG_HUGETLB_PAGE=y
1088# CONFIG_EFS_FS is not set 1165# CONFIG_EFS_FS is not set
1089CONFIG_CRAMFS=y 1166CONFIG_CRAMFS=y
1090# CONFIG_VXFS_FS is not set 1167# CONFIG_VXFS_FS is not set
1168# CONFIG_MINIX_FS is not set
1169# CONFIG_OMFS_FS is not set
1091# CONFIG_HPFS_FS is not set 1170# CONFIG_HPFS_FS is not set
1092# CONFIG_QNX4FS_FS is not set 1171# CONFIG_QNX4FS_FS is not set
1172# CONFIG_ROMFS_FS is not set
1093# CONFIG_SYSV_FS is not set 1173# CONFIG_SYSV_FS is not set
1094# CONFIG_UFS_FS is not set 1174# CONFIG_UFS_FS is not set
1095CONFIG_NETWORK_FILESYSTEMS=y 1175CONFIG_NETWORK_FILESYSTEMS=y
@@ -1097,16 +1177,14 @@ CONFIG_NFS_FS=y
1097CONFIG_NFS_V3=y 1177CONFIG_NFS_V3=y
1098CONFIG_NFS_V3_ACL=y 1178CONFIG_NFS_V3_ACL=y
1099CONFIG_NFS_V4=y 1179CONFIG_NFS_V4=y
1100# CONFIG_NFS_DIRECTIO is not set
1101# CONFIG_NFSD is not set
1102CONFIG_ROOT_NFS=y 1180CONFIG_ROOT_NFS=y
1181# CONFIG_NFSD is not set
1103CONFIG_LOCKD=y 1182CONFIG_LOCKD=y
1104CONFIG_LOCKD_V4=y 1183CONFIG_LOCKD_V4=y
1105CONFIG_NFS_ACL_SUPPORT=y 1184CONFIG_NFS_ACL_SUPPORT=y
1106CONFIG_NFS_COMMON=y 1185CONFIG_NFS_COMMON=y
1107CONFIG_SUNRPC=y 1186CONFIG_SUNRPC=y
1108CONFIG_SUNRPC_GSS=y 1187CONFIG_SUNRPC_GSS=y
1109# CONFIG_SUNRPC_BIND34 is not set
1110CONFIG_RPCSEC_GSS_KRB5=y 1188CONFIG_RPCSEC_GSS_KRB5=y
1111# CONFIG_RPCSEC_GSS_SPKM3 is not set 1189# CONFIG_RPCSEC_GSS_SPKM3 is not set
1112# CONFIG_SMB_FS is not set 1190# CONFIG_SMB_FS is not set
@@ -1177,14 +1255,15 @@ CONFIG_NLS_DEFAULT="utf-8"
1177# CONFIG_NLS_KOI8_U is not set 1255# CONFIG_NLS_KOI8_U is not set
1178CONFIG_NLS_UTF8=y 1256CONFIG_NLS_UTF8=y
1179# CONFIG_DLM is not set 1257# CONFIG_DLM is not set
1180# CONFIG_UCC_SLOW is not set
1181 1258
1182# 1259#
1183# Library routines 1260# Library routines
1184# 1261#
1185CONFIG_BITREVERSE=y 1262CONFIG_BITREVERSE=y
1263# CONFIG_GENERIC_FIND_FIRST_BIT is not set
1186CONFIG_CRC_CCITT=y 1264CONFIG_CRC_CCITT=y
1187# CONFIG_CRC16 is not set 1265# CONFIG_CRC16 is not set
1266CONFIG_CRC_T10DIF=y
1188# CONFIG_CRC_ITU_T is not set 1267# CONFIG_CRC_ITU_T is not set
1189CONFIG_CRC32=y 1268CONFIG_CRC32=y
1190# CONFIG_CRC7 is not set 1269# CONFIG_CRC7 is not set
@@ -1194,7 +1273,7 @@ CONFIG_PLIST=y
1194CONFIG_HAS_IOMEM=y 1273CONFIG_HAS_IOMEM=y
1195CONFIG_HAS_IOPORT=y 1274CONFIG_HAS_IOPORT=y
1196CONFIG_HAS_DMA=y 1275CONFIG_HAS_DMA=y
1197# CONFIG_INSTRUMENTATION is not set 1276CONFIG_HAVE_LMB=y
1198 1277
1199# 1278#
1200# Kernel hacking 1279# Kernel hacking
@@ -1202,6 +1281,7 @@ CONFIG_HAS_DMA=y
1202# CONFIG_PRINTK_TIME is not set 1281# CONFIG_PRINTK_TIME is not set
1203CONFIG_ENABLE_WARN_DEPRECATED=y 1282CONFIG_ENABLE_WARN_DEPRECATED=y
1204CONFIG_ENABLE_MUST_CHECK=y 1283CONFIG_ENABLE_MUST_CHECK=y
1284CONFIG_FRAME_WARN=2048
1205CONFIG_MAGIC_SYSRQ=y 1285CONFIG_MAGIC_SYSRQ=y
1206# CONFIG_UNUSED_SYMBOLS is not set 1286# CONFIG_UNUSED_SYMBOLS is not set
1207CONFIG_DEBUG_FS=y 1287CONFIG_DEBUG_FS=y
@@ -1209,34 +1289,59 @@ CONFIG_DEBUG_FS=y
1209CONFIG_DEBUG_KERNEL=y 1289CONFIG_DEBUG_KERNEL=y
1210# CONFIG_DEBUG_SHIRQ is not set 1290# CONFIG_DEBUG_SHIRQ is not set
1211CONFIG_DETECT_SOFTLOCKUP=y 1291CONFIG_DETECT_SOFTLOCKUP=y
1292# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
1293CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
1212CONFIG_SCHED_DEBUG=y 1294CONFIG_SCHED_DEBUG=y
1213# CONFIG_SCHEDSTATS is not set 1295CONFIG_SCHEDSTATS=y
1214# CONFIG_TIMER_STATS is not set 1296# CONFIG_TIMER_STATS is not set
1297# CONFIG_DEBUG_OBJECTS is not set
1215# CONFIG_SLUB_DEBUG_ON is not set 1298# CONFIG_SLUB_DEBUG_ON is not set
1299# CONFIG_SLUB_STATS is not set
1216# CONFIG_DEBUG_RT_MUTEXES is not set 1300# CONFIG_DEBUG_RT_MUTEXES is not set
1217# CONFIG_RT_MUTEX_TESTER is not set 1301# CONFIG_RT_MUTEX_TESTER is not set
1218# CONFIG_DEBUG_SPINLOCK is not set 1302# CONFIG_DEBUG_SPINLOCK is not set
1219# CONFIG_DEBUG_MUTEXES is not set 1303# CONFIG_DEBUG_MUTEXES is not set
1304# CONFIG_DEBUG_LOCK_ALLOC is not set
1305# CONFIG_PROVE_LOCKING is not set
1306# CONFIG_LOCK_STAT is not set
1220CONFIG_DEBUG_SPINLOCK_SLEEP=y 1307CONFIG_DEBUG_SPINLOCK_SLEEP=y
1221# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set 1308# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1309CONFIG_STACKTRACE=y
1222# CONFIG_DEBUG_KOBJECT is not set 1310# CONFIG_DEBUG_KOBJECT is not set
1223CONFIG_DEBUG_BUGVERBOSE=y 1311CONFIG_DEBUG_BUGVERBOSE=y
1224# CONFIG_DEBUG_INFO is not set 1312# CONFIG_DEBUG_INFO is not set
1225# CONFIG_DEBUG_VM is not set 1313# CONFIG_DEBUG_VM is not set
1314# CONFIG_DEBUG_WRITECOUNT is not set
1315CONFIG_DEBUG_MEMORY_INIT=y
1226# CONFIG_DEBUG_LIST is not set 1316# CONFIG_DEBUG_LIST is not set
1227# CONFIG_DEBUG_SG is not set 1317# CONFIG_DEBUG_SG is not set
1228# CONFIG_FORCED_INLINING is not set 1318CONFIG_FRAME_POINTER=y
1229# CONFIG_BOOT_PRINTK_DELAY is not set 1319# CONFIG_BOOT_PRINTK_DELAY is not set
1230# CONFIG_RCU_TORTURE_TEST is not set 1320# CONFIG_RCU_TORTURE_TEST is not set
1321# CONFIG_KPROBES_SANITY_TEST is not set
1322# CONFIG_BACKTRACE_SELF_TEST is not set
1323# CONFIG_LKDTM is not set
1231# CONFIG_FAULT_INJECTION is not set 1324# CONFIG_FAULT_INJECTION is not set
1325CONFIG_LATENCYTOP=y
1326# CONFIG_SYSCTL_SYSCALL_CHECK is not set
1327CONFIG_HAVE_FTRACE=y
1328CONFIG_HAVE_DYNAMIC_FTRACE=y
1329# CONFIG_FTRACE is not set
1330# CONFIG_IRQSOFF_TRACER is not set
1331# CONFIG_SCHED_TRACER is not set
1332# CONFIG_CONTEXT_SWITCH_TRACER is not set
1232# CONFIG_SAMPLES is not set 1333# CONFIG_SAMPLES is not set
1334CONFIG_HAVE_ARCH_KGDB=y
1335# CONFIG_KGDB is not set
1233CONFIG_DEBUG_STACKOVERFLOW=y 1336CONFIG_DEBUG_STACKOVERFLOW=y
1234CONFIG_DEBUG_STACK_USAGE=y 1337CONFIG_DEBUG_STACK_USAGE=y
1235# CONFIG_DEBUG_PAGEALLOC is not set 1338# CONFIG_DEBUG_PAGEALLOC is not set
1236CONFIG_DEBUGGER=y 1339# CONFIG_CODE_PATCHING_SELFTEST is not set
1340# CONFIG_FTR_FIXUP_SELFTEST is not set
1237CONFIG_XMON=y 1341CONFIG_XMON=y
1238CONFIG_XMON_DEFAULT=y 1342CONFIG_XMON_DEFAULT=y
1239CONFIG_XMON_DISASSEMBLY=y 1343CONFIG_XMON_DISASSEMBLY=y
1344CONFIG_DEBUGGER=y
1240# CONFIG_IRQSTACKS is not set 1345# CONFIG_IRQSTACKS is not set
1241# CONFIG_VIRQ_DEBUG is not set 1346# CONFIG_VIRQ_DEBUG is not set
1242CONFIG_BOOTX_TEXT=y 1347CONFIG_BOOTX_TEXT=y
@@ -1249,44 +1354,84 @@ CONFIG_BOOTX_TEXT=y
1249# CONFIG_SECURITY is not set 1354# CONFIG_SECURITY is not set
1250# CONFIG_SECURITY_FILE_CAPABILITIES is not set 1355# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1251CONFIG_CRYPTO=y 1356CONFIG_CRYPTO=y
1357
1358#
1359# Crypto core or helper
1360#
1252CONFIG_CRYPTO_ALGAPI=y 1361CONFIG_CRYPTO_ALGAPI=y
1253CONFIG_CRYPTO_BLKCIPHER=y 1362CONFIG_CRYPTO_BLKCIPHER=y
1254CONFIG_CRYPTO_MANAGER=y 1363CONFIG_CRYPTO_MANAGER=y
1364# CONFIG_CRYPTO_GF128MUL is not set
1365# CONFIG_CRYPTO_NULL is not set
1366# CONFIG_CRYPTO_CRYPTD is not set
1367# CONFIG_CRYPTO_AUTHENC is not set
1368# CONFIG_CRYPTO_TEST is not set
1369
1370#
1371# Authenticated Encryption with Associated Data
1372#
1373# CONFIG_CRYPTO_CCM is not set
1374# CONFIG_CRYPTO_GCM is not set
1375# CONFIG_CRYPTO_SEQIV is not set
1376
1377#
1378# Block modes
1379#
1380CONFIG_CRYPTO_CBC=y
1381# CONFIG_CRYPTO_CTR is not set
1382# CONFIG_CRYPTO_CTS is not set
1383CONFIG_CRYPTO_ECB=m
1384# CONFIG_CRYPTO_LRW is not set
1385CONFIG_CRYPTO_PCBC=m
1386# CONFIG_CRYPTO_XTS is not set
1387
1388#
1389# Hash modes
1390#
1255# CONFIG_CRYPTO_HMAC is not set 1391# CONFIG_CRYPTO_HMAC is not set
1256# CONFIG_CRYPTO_XCBC is not set 1392# CONFIG_CRYPTO_XCBC is not set
1257# CONFIG_CRYPTO_NULL is not set 1393
1394#
1395# Digest
1396#
1397# CONFIG_CRYPTO_CRC32C is not set
1258# CONFIG_CRYPTO_MD4 is not set 1398# CONFIG_CRYPTO_MD4 is not set
1259CONFIG_CRYPTO_MD5=y 1399CONFIG_CRYPTO_MD5=y
1400# CONFIG_CRYPTO_MICHAEL_MIC is not set
1401# CONFIG_CRYPTO_RMD128 is not set
1402# CONFIG_CRYPTO_RMD160 is not set
1403# CONFIG_CRYPTO_RMD256 is not set
1404# CONFIG_CRYPTO_RMD320 is not set
1260# CONFIG_CRYPTO_SHA1 is not set 1405# CONFIG_CRYPTO_SHA1 is not set
1261# CONFIG_CRYPTO_SHA256 is not set 1406# CONFIG_CRYPTO_SHA256 is not set
1262# CONFIG_CRYPTO_SHA512 is not set 1407# CONFIG_CRYPTO_SHA512 is not set
1263# CONFIG_CRYPTO_WP512 is not set
1264# CONFIG_CRYPTO_TGR192 is not set 1408# CONFIG_CRYPTO_TGR192 is not set
1265# CONFIG_CRYPTO_GF128MUL is not set 1409# CONFIG_CRYPTO_WP512 is not set
1266CONFIG_CRYPTO_ECB=m 1410
1267CONFIG_CRYPTO_CBC=y 1411#
1268CONFIG_CRYPTO_PCBC=m 1412# Ciphers
1269# CONFIG_CRYPTO_LRW is not set 1413#
1270# CONFIG_CRYPTO_XTS is not set
1271# CONFIG_CRYPTO_CRYPTD is not set
1272CONFIG_CRYPTO_DES=y
1273# CONFIG_CRYPTO_FCRYPT is not set
1274# CONFIG_CRYPTO_BLOWFISH is not set
1275# CONFIG_CRYPTO_TWOFISH is not set
1276# CONFIG_CRYPTO_SERPENT is not set
1277# CONFIG_CRYPTO_AES is not set 1414# CONFIG_CRYPTO_AES is not set
1415# CONFIG_CRYPTO_ANUBIS is not set
1416# CONFIG_CRYPTO_ARC4 is not set
1417# CONFIG_CRYPTO_BLOWFISH is not set
1418# CONFIG_CRYPTO_CAMELLIA is not set
1278# CONFIG_CRYPTO_CAST5 is not set 1419# CONFIG_CRYPTO_CAST5 is not set
1279# CONFIG_CRYPTO_CAST6 is not set 1420# CONFIG_CRYPTO_CAST6 is not set
1280# CONFIG_CRYPTO_TEA is not set 1421CONFIG_CRYPTO_DES=y
1281# CONFIG_CRYPTO_ARC4 is not set 1422# CONFIG_CRYPTO_FCRYPT is not set
1282# CONFIG_CRYPTO_KHAZAD is not set 1423# CONFIG_CRYPTO_KHAZAD is not set
1283# CONFIG_CRYPTO_ANUBIS is not set 1424# CONFIG_CRYPTO_SALSA20 is not set
1284# CONFIG_CRYPTO_SEED is not set 1425# CONFIG_CRYPTO_SEED is not set
1426# CONFIG_CRYPTO_SERPENT is not set
1427# CONFIG_CRYPTO_TEA is not set
1428# CONFIG_CRYPTO_TWOFISH is not set
1429
1430#
1431# Compression
1432#
1285# CONFIG_CRYPTO_DEFLATE is not set 1433# CONFIG_CRYPTO_DEFLATE is not set
1286# CONFIG_CRYPTO_MICHAEL_MIC is not set 1434# CONFIG_CRYPTO_LZO is not set
1287# CONFIG_CRYPTO_CRC32C is not set
1288# CONFIG_CRYPTO_CAMELLIA is not set
1289# CONFIG_CRYPTO_TEST is not set
1290# CONFIG_CRYPTO_AUTHENC is not set
1291# CONFIG_CRYPTO_HW is not set 1435# CONFIG_CRYPTO_HW is not set
1292# CONFIG_PPC_CLOCK is not set 1436# CONFIG_PPC_CLOCK is not set
1437# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/configs/mpc7448_hpc2_defconfig b/arch/powerpc/configs/mpc7448_hpc2_defconfig
index 066c583c1f8a..ab5199f26a24 100644
--- a/arch/powerpc/configs/mpc7448_hpc2_defconfig
+++ b/arch/powerpc/configs/mpc7448_hpc2_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc5 3# Linux kernel version: 2.6.27-rc4
4# Mon Jun 9 08:52:11 2008 4# Thu Aug 21 00:52:06 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -32,6 +32,7 @@ CONFIG_GENERIC_HARDIRQS=y
32# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set 32# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
33CONFIG_IRQ_PER_CPU=y 33CONFIG_IRQ_PER_CPU=y
34CONFIG_STACKTRACE_SUPPORT=y 34CONFIG_STACKTRACE_SUPPORT=y
35CONFIG_HAVE_LATENCYTOP_SUPPORT=y
35CONFIG_LOCKDEP_SUPPORT=y 36CONFIG_LOCKDEP_SUPPORT=y
36CONFIG_RWSEM_XCHGADD_ALGORITHM=y 37CONFIG_RWSEM_XCHGADD_ALGORITHM=y
37CONFIG_ARCH_HAS_ILOG2_U32=y 38CONFIG_ARCH_HAS_ILOG2_U32=y
@@ -88,7 +89,6 @@ CONFIG_INITRAMFS_SOURCE=""
88CONFIG_SYSCTL=y 89CONFIG_SYSCTL=y
89CONFIG_EMBEDDED=y 90CONFIG_EMBEDDED=y
90CONFIG_SYSCTL_SYSCALL=y 91CONFIG_SYSCTL_SYSCALL=y
91CONFIG_SYSCTL_SYSCALL_CHECK=y
92CONFIG_KALLSYMS=y 92CONFIG_KALLSYMS=y
93# CONFIG_KALLSYMS_EXTRA_PASS is not set 93# CONFIG_KALLSYMS_EXTRA_PASS is not set
94CONFIG_HOTPLUG=y 94CONFIG_HOTPLUG=y
@@ -112,10 +112,16 @@ CONFIG_SLUB=y
112# CONFIG_PROFILING is not set 112# CONFIG_PROFILING is not set
113# CONFIG_MARKERS is not set 113# CONFIG_MARKERS is not set
114CONFIG_HAVE_OPROFILE=y 114CONFIG_HAVE_OPROFILE=y
115CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
116CONFIG_HAVE_IOREMAP_PROT=y
115CONFIG_HAVE_KPROBES=y 117CONFIG_HAVE_KPROBES=y
116CONFIG_HAVE_KRETPROBES=y 118CONFIG_HAVE_KRETPROBES=y
119CONFIG_HAVE_ARCH_TRACEHOOK=y
117# CONFIG_HAVE_DMA_ATTRS is not set 120# CONFIG_HAVE_DMA_ATTRS is not set
121# CONFIG_USE_GENERIC_SMP_HELPERS is not set
122# CONFIG_HAVE_CLK is not set
118CONFIG_PROC_PAGE_MONITOR=y 123CONFIG_PROC_PAGE_MONITOR=y
124# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
119CONFIG_SLABINFO=y 125CONFIG_SLABINFO=y
120CONFIG_RT_MUTEXES=y 126CONFIG_RT_MUTEXES=y
121# CONFIG_TINY_SHMEM is not set 127# CONFIG_TINY_SHMEM is not set
@@ -126,6 +132,7 @@ CONFIG_LBD=y
126# CONFIG_BLK_DEV_IO_TRACE is not set 132# CONFIG_BLK_DEV_IO_TRACE is not set
127# CONFIG_LSF is not set 133# CONFIG_LSF is not set
128# CONFIG_BLK_DEV_BSG is not set 134# CONFIG_BLK_DEV_BSG is not set
135# CONFIG_BLK_DEV_INTEGRITY is not set
129 136
130# 137#
131# IO Schedulers 138# IO Schedulers
@@ -145,25 +152,25 @@ CONFIG_CLASSIC_RCU=y
145# Platform support 152# Platform support
146# 153#
147CONFIG_PPC_MULTIPLATFORM=y 154CONFIG_PPC_MULTIPLATFORM=y
148# CONFIG_PPC_82xx is not set
149# CONFIG_PPC_83xx is not set
150# CONFIG_PPC_86xx is not set
151CONFIG_CLASSIC32=y 155CONFIG_CLASSIC32=y
152# CONFIG_PPC_CHRP is not set 156# CONFIG_PPC_CHRP is not set
153# CONFIG_PPC_MPC512x is not set
154# CONFIG_PPC_MPC5121 is not set
155# CONFIG_MPC5121_ADS is not set 157# CONFIG_MPC5121_ADS is not set
158# CONFIG_MPC5121_GENERIC is not set
156# CONFIG_PPC_MPC52xx is not set 159# CONFIG_PPC_MPC52xx is not set
157# CONFIG_PPC_PMAC is not set 160# CONFIG_PPC_PMAC is not set
158# CONFIG_PPC_CELL is not set 161# CONFIG_PPC_CELL is not set
159# CONFIG_PPC_CELL_NATIVE is not set 162# CONFIG_PPC_CELL_NATIVE is not set
163# CONFIG_PPC_82xx is not set
160# CONFIG_PQ2ADS is not set 164# CONFIG_PQ2ADS is not set
165# CONFIG_PPC_83xx is not set
166# CONFIG_PPC_86xx is not set
161CONFIG_EMBEDDED6xx=y 167CONFIG_EMBEDDED6xx=y
162# CONFIG_LINKSTATION is not set 168# CONFIG_LINKSTATION is not set
163# CONFIG_STORCENTER is not set 169# CONFIG_STORCENTER is not set
164CONFIG_MPC7448HPC2=y 170CONFIG_MPC7448HPC2=y
165# CONFIG_PPC_HOLLY is not set 171# CONFIG_PPC_HOLLY is not set
166# CONFIG_PPC_PRPMC2800 is not set 172# CONFIG_PPC_PRPMC2800 is not set
173# CONFIG_PPC_C2K is not set
167CONFIG_TSI108_BRIDGE=y 174CONFIG_TSI108_BRIDGE=y
168# CONFIG_IPIC is not set 175# CONFIG_IPIC is not set
169CONFIG_MPIC=y 176CONFIG_MPIC=y
@@ -192,7 +199,7 @@ CONFIG_HZ_250=y
192# CONFIG_HZ_300 is not set 199# CONFIG_HZ_300 is not set
193# CONFIG_HZ_1000 is not set 200# CONFIG_HZ_1000 is not set
194CONFIG_HZ=250 201CONFIG_HZ=250
195# CONFIG_SCHED_HRTICK is not set 202CONFIG_SCHED_HRTICK=y
196CONFIG_PREEMPT_NONE=y 203CONFIG_PREEMPT_NONE=y
197# CONFIG_PREEMPT_VOLUNTARY is not set 204# CONFIG_PREEMPT_VOLUNTARY is not set
198# CONFIG_PREEMPT is not set 205# CONFIG_PREEMPT is not set
@@ -215,6 +222,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
215# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set 222# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
216CONFIG_PAGEFLAGS_EXTENDED=y 223CONFIG_PAGEFLAGS_EXTENDED=y
217CONFIG_SPLIT_PTLOCK_CPUS=4 224CONFIG_SPLIT_PTLOCK_CPUS=4
225CONFIG_MIGRATION=y
218# CONFIG_RESOURCES_64BIT is not set 226# CONFIG_RESOURCES_64BIT is not set
219CONFIG_ZONE_DMA_FLAG=1 227CONFIG_ZONE_DMA_FLAG=1
220CONFIG_BOUNCE=y 228CONFIG_BOUNCE=y
@@ -222,6 +230,7 @@ CONFIG_VIRT_TO_BUS=y
222CONFIG_FORCE_MAX_ZONEORDER=11 230CONFIG_FORCE_MAX_ZONEORDER=11
223CONFIG_PROC_DEVICETREE=y 231CONFIG_PROC_DEVICETREE=y
224# CONFIG_CMDLINE_BOOL is not set 232# CONFIG_CMDLINE_BOOL is not set
233CONFIG_EXTRA_TARGETS=""
225# CONFIG_PM is not set 234# CONFIG_PM is not set
226# CONFIG_SECCOMP is not set 235# CONFIG_SECCOMP is not set
227CONFIG_ISA_DMA_API=y 236CONFIG_ISA_DMA_API=y
@@ -256,10 +265,6 @@ CONFIG_PAGE_OFFSET=0xc0000000
256CONFIG_KERNEL_START=0xc0000000 265CONFIG_KERNEL_START=0xc0000000
257CONFIG_PHYSICAL_START=0x00000000 266CONFIG_PHYSICAL_START=0x00000000
258CONFIG_TASK_SIZE=0xc0000000 267CONFIG_TASK_SIZE=0xc0000000
259
260#
261# Networking
262#
263CONFIG_NET=y 268CONFIG_NET=y
264 269
265# 270#
@@ -374,12 +379,14 @@ CONFIG_BLK_DEV_RAM_SIZE=131072
374# CONFIG_BLK_DEV_XIP is not set 379# CONFIG_BLK_DEV_XIP is not set
375# CONFIG_CDROM_PKTCDVD is not set 380# CONFIG_CDROM_PKTCDVD is not set
376# CONFIG_ATA_OVER_ETH is not set 381# CONFIG_ATA_OVER_ETH is not set
382# CONFIG_BLK_DEV_HD is not set
377CONFIG_MISC_DEVICES=y 383CONFIG_MISC_DEVICES=y
378# CONFIG_PHANTOM is not set 384# CONFIG_PHANTOM is not set
379# CONFIG_EEPROM_93CX6 is not set 385# CONFIG_EEPROM_93CX6 is not set
380# CONFIG_SGI_IOC4 is not set 386# CONFIG_SGI_IOC4 is not set
381# CONFIG_TIFM_CORE is not set 387# CONFIG_TIFM_CORE is not set
382# CONFIG_ENCLOSURE_SERVICES is not set 388# CONFIG_ENCLOSURE_SERVICES is not set
389# CONFIG_HP_ILO is not set
383CONFIG_HAVE_IDE=y 390CONFIG_HAVE_IDE=y
384# CONFIG_IDE is not set 391# CONFIG_IDE is not set
385 392
@@ -457,6 +464,7 @@ CONFIG_SCSI_LOWLEVEL=y
457# CONFIG_SCSI_NSP32 is not set 464# CONFIG_SCSI_NSP32 is not set
458# CONFIG_SCSI_DEBUG is not set 465# CONFIG_SCSI_DEBUG is not set
459# CONFIG_SCSI_SRP is not set 466# CONFIG_SCSI_SRP is not set
467# CONFIG_SCSI_DH is not set
460CONFIG_ATA=y 468CONFIG_ATA=y
461# CONFIG_ATA_NONSTANDARD is not set 469# CONFIG_ATA_NONSTANDARD is not set
462CONFIG_SATA_PMP=y 470CONFIG_SATA_PMP=y
@@ -523,12 +531,15 @@ CONFIG_SATA_MV=y
523# 531#
524# IEEE 1394 (FireWire) support 532# IEEE 1394 (FireWire) support
525# 533#
534
535#
536# Enable only one of the two stacks, unless you know what you are doing
537#
526# CONFIG_FIREWIRE is not set 538# CONFIG_FIREWIRE is not set
527# CONFIG_IEEE1394 is not set 539# CONFIG_IEEE1394 is not set
528# CONFIG_I2O is not set 540# CONFIG_I2O is not set
529# CONFIG_MACINTOSH_DRIVERS is not set 541# CONFIG_MACINTOSH_DRIVERS is not set
530CONFIG_NETDEVICES=y 542CONFIG_NETDEVICES=y
531# CONFIG_NETDEVICES_MULTIQUEUE is not set
532# CONFIG_DUMMY is not set 543# CONFIG_DUMMY is not set
533# CONFIG_BONDING is not set 544# CONFIG_BONDING is not set
534# CONFIG_MACVLAN is not set 545# CONFIG_MACVLAN is not set
@@ -594,7 +605,6 @@ CONFIG_NETDEV_1000=y
594# CONFIG_DL2K is not set 605# CONFIG_DL2K is not set
595# CONFIG_E1000 is not set 606# CONFIG_E1000 is not set
596# CONFIG_E1000E is not set 607# CONFIG_E1000E is not set
597# CONFIG_E1000E_ENABLED is not set
598# CONFIG_IP1000 is not set 608# CONFIG_IP1000 is not set
599# CONFIG_IGB is not set 609# CONFIG_IGB is not set
600# CONFIG_NS83820 is not set 610# CONFIG_NS83820 is not set
@@ -611,6 +621,7 @@ CONFIG_TSI108_ETH=y
611# CONFIG_MV643XX_ETH is not set 621# CONFIG_MV643XX_ETH is not set
612# CONFIG_QLA3XXX is not set 622# CONFIG_QLA3XXX is not set
613# CONFIG_ATL1 is not set 623# CONFIG_ATL1 is not set
624# CONFIG_ATL1E is not set
614CONFIG_NETDEV_10000=y 625CONFIG_NETDEV_10000=y
615# CONFIG_CHELSIO_T1 is not set 626# CONFIG_CHELSIO_T1 is not set
616# CONFIG_CHELSIO_T3 is not set 627# CONFIG_CHELSIO_T3 is not set
@@ -716,6 +727,8 @@ CONFIG_GEN_RTC=y
716CONFIG_DEVPORT=y 727CONFIG_DEVPORT=y
717# CONFIG_I2C is not set 728# CONFIG_I2C is not set
718# CONFIG_SPI is not set 729# CONFIG_SPI is not set
730CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
731# CONFIG_GPIOLIB is not set
719# CONFIG_W1 is not set 732# CONFIG_W1 is not set
720# CONFIG_POWER_SUPPLY is not set 733# CONFIG_POWER_SUPPLY is not set
721CONFIG_HWMON=y 734CONFIG_HWMON=y
@@ -736,6 +749,7 @@ CONFIG_HWMON=y
736# CONFIG_SENSORS_W83627EHF is not set 749# CONFIG_SENSORS_W83627EHF is not set
737# CONFIG_HWMON_DEBUG_CHIP is not set 750# CONFIG_HWMON_DEBUG_CHIP is not set
738# CONFIG_THERMAL is not set 751# CONFIG_THERMAL is not set
752# CONFIG_THERMAL_HWMON is not set
739# CONFIG_WATCHDOG is not set 753# CONFIG_WATCHDOG is not set
740 754
741# 755#
@@ -747,8 +761,10 @@ CONFIG_SSB_POSSIBLE=y
747# 761#
748# Multifunction device drivers 762# Multifunction device drivers
749# 763#
764# CONFIG_MFD_CORE is not set
750# CONFIG_MFD_SM501 is not set 765# CONFIG_MFD_SM501 is not set
751# CONFIG_HTC_PASIC3 is not set 766# CONFIG_HTC_PASIC3 is not set
767# CONFIG_MFD_TMIO is not set
752 768
753# 769#
754# Multimedia devices 770# Multimedia devices
@@ -780,10 +796,6 @@ CONFIG_VIDEO_OUTPUT_CONTROL=y
780# Display device support 796# Display device support
781# 797#
782# CONFIG_DISPLAY_SUPPORT is not set 798# CONFIG_DISPLAY_SUPPORT is not set
783
784#
785# Sound
786#
787# CONFIG_SOUND is not set 799# CONFIG_SOUND is not set
788CONFIG_HID_SUPPORT=y 800CONFIG_HID_SUPPORT=y
789CONFIG_HID=y 801CONFIG_HID=y
@@ -798,6 +810,10 @@ CONFIG_USB_ARCH_HAS_EHCI=y
798# CONFIG_USB_OTG_BLACKLIST_HUB is not set 810# CONFIG_USB_OTG_BLACKLIST_HUB is not set
799 811
800# 812#
813# Enable Host or Gadget support to see Inventra options
814#
815
816#
801# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 817# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
802# 818#
803# CONFIG_USB_GADGET is not set 819# CONFIG_USB_GADGET is not set
@@ -875,6 +891,7 @@ CONFIG_TMPFS=y
875# CONFIG_CRAMFS is not set 891# CONFIG_CRAMFS is not set
876# CONFIG_VXFS_FS is not set 892# CONFIG_VXFS_FS is not set
877# CONFIG_MINIX_FS is not set 893# CONFIG_MINIX_FS is not set
894# CONFIG_OMFS_FS is not set
878# CONFIG_HPFS_FS is not set 895# CONFIG_HPFS_FS is not set
879# CONFIG_QNX4FS_FS is not set 896# CONFIG_QNX4FS_FS is not set
880# CONFIG_ROMFS_FS is not set 897# CONFIG_ROMFS_FS is not set
@@ -884,12 +901,11 @@ CONFIG_NETWORK_FILESYSTEMS=y
884CONFIG_NFS_FS=y 901CONFIG_NFS_FS=y
885# CONFIG_NFS_V3 is not set 902# CONFIG_NFS_V3 is not set
886# CONFIG_NFS_V4 is not set 903# CONFIG_NFS_V4 is not set
887# CONFIG_NFSD is not set
888CONFIG_ROOT_NFS=y 904CONFIG_ROOT_NFS=y
905# CONFIG_NFSD is not set
889CONFIG_LOCKD=y 906CONFIG_LOCKD=y
890CONFIG_NFS_COMMON=y 907CONFIG_NFS_COMMON=y
891CONFIG_SUNRPC=y 908CONFIG_SUNRPC=y
892# CONFIG_SUNRPC_BIND34 is not set
893# CONFIG_RPCSEC_GSS_KRB5 is not set 909# CONFIG_RPCSEC_GSS_KRB5 is not set
894# CONFIG_RPCSEC_GSS_SPKM3 is not set 910# CONFIG_RPCSEC_GSS_SPKM3 is not set
895# CONFIG_SMB_FS is not set 911# CONFIG_SMB_FS is not set
@@ -929,6 +945,7 @@ CONFIG_BITREVERSE=y
929# CONFIG_GENERIC_FIND_FIRST_BIT is not set 945# CONFIG_GENERIC_FIND_FIRST_BIT is not set
930# CONFIG_CRC_CCITT is not set 946# CONFIG_CRC_CCITT is not set
931# CONFIG_CRC16 is not set 947# CONFIG_CRC16 is not set
948CONFIG_CRC_T10DIF=y
932# CONFIG_CRC_ITU_T is not set 949# CONFIG_CRC_ITU_T is not set
933CONFIG_CRC32=y 950CONFIG_CRC32=y
934# CONFIG_CRC7 is not set 951# CONFIG_CRC7 is not set
@@ -954,7 +971,16 @@ CONFIG_FRAME_WARN=1024
954# CONFIG_SLUB_DEBUG_ON is not set 971# CONFIG_SLUB_DEBUG_ON is not set
955# CONFIG_SLUB_STATS is not set 972# CONFIG_SLUB_STATS is not set
956# CONFIG_DEBUG_BUGVERBOSE is not set 973# CONFIG_DEBUG_BUGVERBOSE is not set
974# CONFIG_DEBUG_MEMORY_INIT is not set
975# CONFIG_LATENCYTOP is not set
976CONFIG_SYSCTL_SYSCALL_CHECK=y
977CONFIG_HAVE_FTRACE=y
978CONFIG_HAVE_DYNAMIC_FTRACE=y
979# CONFIG_FTRACE is not set
980# CONFIG_SCHED_TRACER is not set
981# CONFIG_CONTEXT_SWITCH_TRACER is not set
957# CONFIG_SAMPLES is not set 982# CONFIG_SAMPLES is not set
983CONFIG_HAVE_ARCH_KGDB=y
958# CONFIG_IRQSTACKS is not set 984# CONFIG_IRQSTACKS is not set
959# CONFIG_BOOTX_TEXT is not set 985# CONFIG_BOOTX_TEXT is not set
960# CONFIG_PPC_EARLY_DEBUG is not set 986# CONFIG_PPC_EARLY_DEBUG is not set
@@ -1007,6 +1033,10 @@ CONFIG_CRYPTO=y
1007# CONFIG_CRYPTO_MD4 is not set 1033# CONFIG_CRYPTO_MD4 is not set
1008# CONFIG_CRYPTO_MD5 is not set 1034# CONFIG_CRYPTO_MD5 is not set
1009# CONFIG_CRYPTO_MICHAEL_MIC is not set 1035# CONFIG_CRYPTO_MICHAEL_MIC is not set
1036# CONFIG_CRYPTO_RMD128 is not set
1037# CONFIG_CRYPTO_RMD160 is not set
1038# CONFIG_CRYPTO_RMD256 is not set
1039# CONFIG_CRYPTO_RMD320 is not set
1010# CONFIG_CRYPTO_SHA1 is not set 1040# CONFIG_CRYPTO_SHA1 is not set
1011# CONFIG_CRYPTO_SHA256 is not set 1041# CONFIG_CRYPTO_SHA256 is not set
1012# CONFIG_CRYPTO_SHA512 is not set 1042# CONFIG_CRYPTO_SHA512 is not set
diff --git a/arch/powerpc/configs/mpc8272_ads_defconfig b/arch/powerpc/configs/mpc8272_ads_defconfig
index 30d7834b7db1..7c435c84c875 100644
--- a/arch/powerpc/configs/mpc8272_ads_defconfig
+++ b/arch/powerpc/configs/mpc8272_ads_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc5 3# Linux kernel version: 2.6.27-rc4
4# Mon Jun 9 08:52:12 2008 4# Thu Aug 21 00:52:07 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -15,6 +15,7 @@ CONFIG_6xx=y
15# CONFIG_44x is not set 15# CONFIG_44x is not set
16# CONFIG_E200 is not set 16# CONFIG_E200 is not set
17CONFIG_PPC_FPU=y 17CONFIG_PPC_FPU=y
18# CONFIG_ALTIVEC is not set
18CONFIG_PPC_STD_MMU=y 19CONFIG_PPC_STD_MMU=y
19CONFIG_PPC_STD_MMU_32=y 20CONFIG_PPC_STD_MMU_32=y
20# CONFIG_PPC_MM_SLICES is not set 21# CONFIG_PPC_MM_SLICES is not set
@@ -31,12 +32,14 @@ CONFIG_GENERIC_HARDIRQS=y
31# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set 32# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
32CONFIG_IRQ_PER_CPU=y 33CONFIG_IRQ_PER_CPU=y
33CONFIG_STACKTRACE_SUPPORT=y 34CONFIG_STACKTRACE_SUPPORT=y
35CONFIG_HAVE_LATENCYTOP_SUPPORT=y
34CONFIG_LOCKDEP_SUPPORT=y 36CONFIG_LOCKDEP_SUPPORT=y
35CONFIG_RWSEM_XCHGADD_ALGORITHM=y 37CONFIG_RWSEM_XCHGADD_ALGORITHM=y
36CONFIG_ARCH_HAS_ILOG2_U32=y 38CONFIG_ARCH_HAS_ILOG2_U32=y
37CONFIG_GENERIC_HWEIGHT=y 39CONFIG_GENERIC_HWEIGHT=y
38CONFIG_GENERIC_CALIBRATE_DELAY=y 40CONFIG_GENERIC_CALIBRATE_DELAY=y
39CONFIG_GENERIC_FIND_NEXT_BIT=y 41CONFIG_GENERIC_FIND_NEXT_BIT=y
42CONFIG_GENERIC_GPIO=y
40# CONFIG_ARCH_NO_VIRT_TO_BUS is not set 43# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
41CONFIG_PPC=y 44CONFIG_PPC=y
42CONFIG_EARLY_PRINTK=y 45CONFIG_EARLY_PRINTK=y
@@ -45,11 +48,13 @@ CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
45CONFIG_ARCH_MAY_HAVE_PC_FDC=y 48CONFIG_ARCH_MAY_HAVE_PC_FDC=y
46CONFIG_PPC_OF=y 49CONFIG_PPC_OF=y
47CONFIG_OF=y 50CONFIG_OF=y
48# CONFIG_PPC_UDBG_16550 is not set 51CONFIG_PPC_UDBG_16550=y
49# CONFIG_GENERIC_TBSYNC is not set 52# CONFIG_GENERIC_TBSYNC is not set
50CONFIG_AUDIT_ARCH=y 53CONFIG_AUDIT_ARCH=y
51CONFIG_GENERIC_BUG=y 54CONFIG_GENERIC_BUG=y
52CONFIG_DEFAULT_UIMAGE=y 55CONFIG_DEFAULT_UIMAGE=y
56CONFIG_HIBERNATE_32=y
57CONFIG_ARCH_HIBERNATION_POSSIBLE=y
53# CONFIG_PPC_DCR_NATIVE is not set 58# CONFIG_PPC_DCR_NATIVE is not set
54# CONFIG_PPC_DCR_MMIO is not set 59# CONFIG_PPC_DCR_MMIO is not set
55CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 60CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
@@ -81,7 +86,6 @@ CONFIG_CC_OPTIMIZE_FOR_SIZE=y
81CONFIG_SYSCTL=y 86CONFIG_SYSCTL=y
82CONFIG_EMBEDDED=y 87CONFIG_EMBEDDED=y
83CONFIG_SYSCTL_SYSCALL=y 88CONFIG_SYSCTL_SYSCALL=y
84CONFIG_SYSCTL_SYSCALL_CHECK=y
85CONFIG_KALLSYMS=y 89CONFIG_KALLSYMS=y
86CONFIG_KALLSYMS_ALL=y 90CONFIG_KALLSYMS_ALL=y
87# CONFIG_KALLSYMS_EXTRA_PASS is not set 91# CONFIG_KALLSYMS_EXTRA_PASS is not set
@@ -89,6 +93,7 @@ CONFIG_HOTPLUG=y
89CONFIG_PRINTK=y 93CONFIG_PRINTK=y
90CONFIG_BUG=y 94CONFIG_BUG=y
91CONFIG_ELF_CORE=y 95CONFIG_ELF_CORE=y
96CONFIG_PCSPKR_PLATFORM=y
92CONFIG_COMPAT_BRK=y 97CONFIG_COMPAT_BRK=y
93CONFIG_BASE_FULL=y 98CONFIG_BASE_FULL=y
94CONFIG_FUTEX=y 99CONFIG_FUTEX=y
@@ -106,10 +111,16 @@ CONFIG_SLUB=y
106# CONFIG_PROFILING is not set 111# CONFIG_PROFILING is not set
107# CONFIG_MARKERS is not set 112# CONFIG_MARKERS is not set
108CONFIG_HAVE_OPROFILE=y 113CONFIG_HAVE_OPROFILE=y
114CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
115CONFIG_HAVE_IOREMAP_PROT=y
109CONFIG_HAVE_KPROBES=y 116CONFIG_HAVE_KPROBES=y
110CONFIG_HAVE_KRETPROBES=y 117CONFIG_HAVE_KRETPROBES=y
118CONFIG_HAVE_ARCH_TRACEHOOK=y
111# CONFIG_HAVE_DMA_ATTRS is not set 119# CONFIG_HAVE_DMA_ATTRS is not set
120# CONFIG_USE_GENERIC_SMP_HELPERS is not set
121CONFIG_HAVE_CLK=y
112CONFIG_PROC_PAGE_MONITOR=y 122CONFIG_PROC_PAGE_MONITOR=y
123# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
113CONFIG_SLABINFO=y 124CONFIG_SLABINFO=y
114CONFIG_RT_MUTEXES=y 125CONFIG_RT_MUTEXES=y
115# CONFIG_TINY_SHMEM is not set 126# CONFIG_TINY_SHMEM is not set
@@ -119,6 +130,7 @@ CONFIG_BLOCK=y
119# CONFIG_LBD is not set 130# CONFIG_LBD is not set
120# CONFIG_BLK_DEV_IO_TRACE is not set 131# CONFIG_BLK_DEV_IO_TRACE is not set
121# CONFIG_LSF is not set 132# CONFIG_LSF is not set
133# CONFIG_BLK_DEV_INTEGRITY is not set
122 134
123# 135#
124# IO Schedulers 136# IO Schedulers
@@ -137,14 +149,16 @@ CONFIG_CLASSIC_RCU=y
137# 149#
138# Platform support 150# Platform support
139# 151#
140# CONFIG_PPC_MULTIPLATFORM is not set 152CONFIG_PPC_MULTIPLATFORM=y
141CONFIG_PPC_82xx=y 153CONFIG_CLASSIC32=y
142# CONFIG_PPC_83xx is not set 154CONFIG_PPC_CHRP=y
143# CONFIG_PPC_86xx is not set 155# CONFIG_MPC5121_ADS is not set
144# CONFIG_PPC_MPC512x is not set 156# CONFIG_MPC5121_GENERIC is not set
145# CONFIG_PPC_MPC5121 is not set 157# CONFIG_PPC_MPC52xx is not set
158CONFIG_PPC_PMAC=y
146# CONFIG_PPC_CELL is not set 159# CONFIG_PPC_CELL is not set
147# CONFIG_PPC_CELL_NATIVE is not set 160# CONFIG_PPC_CELL_NATIVE is not set
161CONFIG_PPC_82xx=y
148CONFIG_MPC8272_ADS=y 162CONFIG_MPC8272_ADS=y
149# CONFIG_PQ2FADS is not set 163# CONFIG_PQ2FADS is not set
150# CONFIG_EP8248E is not set 164# CONFIG_EP8248E is not set
@@ -152,19 +166,27 @@ CONFIG_PQ2ADS=y
152CONFIG_8260=y 166CONFIG_8260=y
153CONFIG_8272=y 167CONFIG_8272=y
154CONFIG_PQ2_ADS_PCI_PIC=y 168CONFIG_PQ2_ADS_PCI_PIC=y
169# CONFIG_PPC_83xx is not set
170# CONFIG_PPC_86xx is not set
171# CONFIG_EMBEDDED6xx is not set
172CONFIG_PPC_NATIVE=y
173# CONFIG_UDBG_RTAS_CONSOLE is not set
155# CONFIG_IPIC is not set 174# CONFIG_IPIC is not set
156# CONFIG_MPIC is not set 175CONFIG_MPIC=y
157# CONFIG_MPIC_WEIRD is not set 176# CONFIG_MPIC_WEIRD is not set
158# CONFIG_PPC_I8259 is not set 177CONFIG_PPC_I8259=y
159# CONFIG_PPC_RTAS is not set 178CONFIG_PPC_RTAS=y
179# CONFIG_RTAS_ERROR_LOGGING is not set
180CONFIG_RTAS_PROC=y
160# CONFIG_MMIO_NVRAM is not set 181# CONFIG_MMIO_NVRAM is not set
161# CONFIG_PPC_MPC106 is not set 182CONFIG_PPC_MPC106=y
162# CONFIG_PPC_970_NAP is not set 183# CONFIG_PPC_970_NAP is not set
163# CONFIG_PPC_INDIRECT_IO is not set 184# CONFIG_PPC_INDIRECT_IO is not set
164# CONFIG_GENERIC_IOMAP is not set 185# CONFIG_GENERIC_IOMAP is not set
165# CONFIG_CPU_FREQ is not set 186# CONFIG_CPU_FREQ is not set
187# CONFIG_PPC601_SYNC_FIX is not set
188# CONFIG_TAU is not set
166CONFIG_CPM2=y 189CONFIG_CPM2=y
167CONFIG_PPC_CPM_NEW_BINDING=y
168# CONFIG_FSL_ULI1575 is not set 190# CONFIG_FSL_ULI1575 is not set
169CONFIG_CPM=y 191CONFIG_CPM=y
170 192
@@ -181,7 +203,7 @@ CONFIG_HZ_250=y
181# CONFIG_HZ_300 is not set 203# CONFIG_HZ_300 is not set
182# CONFIG_HZ_1000 is not set 204# CONFIG_HZ_1000 is not set
183CONFIG_HZ=250 205CONFIG_HZ=250
184# CONFIG_SCHED_HRTICK is not set 206CONFIG_SCHED_HRTICK=y
185CONFIG_PREEMPT_NONE=y 207CONFIG_PREEMPT_NONE=y
186# CONFIG_PREEMPT_VOLUNTARY is not set 208# CONFIG_PREEMPT_VOLUNTARY is not set
187# CONFIG_PREEMPT is not set 209# CONFIG_PREEMPT is not set
@@ -199,6 +221,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
199# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set 221# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
200CONFIG_PAGEFLAGS_EXTENDED=y 222CONFIG_PAGEFLAGS_EXTENDED=y
201CONFIG_SPLIT_PTLOCK_CPUS=4 223CONFIG_SPLIT_PTLOCK_CPUS=4
224CONFIG_MIGRATION=y
202# CONFIG_RESOURCES_64BIT is not set 225# CONFIG_RESOURCES_64BIT is not set
203CONFIG_ZONE_DMA_FLAG=1 226CONFIG_ZONE_DMA_FLAG=1
204CONFIG_BOUNCE=y 227CONFIG_BOUNCE=y
@@ -206,6 +229,7 @@ CONFIG_VIRT_TO_BUS=y
206CONFIG_FORCE_MAX_ZONEORDER=11 229CONFIG_FORCE_MAX_ZONEORDER=11
207CONFIG_PROC_DEVICETREE=y 230CONFIG_PROC_DEVICETREE=y
208# CONFIG_CMDLINE_BOOL is not set 231# CONFIG_CMDLINE_BOOL is not set
232CONFIG_EXTRA_TARGETS=""
209# CONFIG_PM is not set 233# CONFIG_PM is not set
210CONFIG_SECCOMP=y 234CONFIG_SECCOMP=y
211CONFIG_ISA_DMA_API=y 235CONFIG_ISA_DMA_API=y
@@ -213,9 +237,11 @@ CONFIG_ISA_DMA_API=y
213# 237#
214# Bus options 238# Bus options
215# 239#
240# CONFIG_ISA is not set
216CONFIG_ZONE_DMA=y 241CONFIG_ZONE_DMA=y
217CONFIG_PPC_INDIRECT_PCI=y 242CONFIG_PPC_INDIRECT_PCI=y
218CONFIG_FSL_SOC=y 243CONFIG_FSL_SOC=y
244CONFIG_PPC_PCI_CHOICE=y
219CONFIG_PCI=y 245CONFIG_PCI=y
220CONFIG_PCI_DOMAINS=y 246CONFIG_PCI_DOMAINS=y
221CONFIG_PCI_SYSCALL=y 247CONFIG_PCI_SYSCALL=y
@@ -242,10 +268,6 @@ CONFIG_PAGE_OFFSET=0xc0000000
242CONFIG_KERNEL_START=0xc0000000 268CONFIG_KERNEL_START=0xc0000000
243CONFIG_PHYSICAL_START=0x00000000 269CONFIG_PHYSICAL_START=0x00000000
244CONFIG_TASK_SIZE=0xc0000000 270CONFIG_TASK_SIZE=0xc0000000
245
246#
247# Networking
248#
249CONFIG_NET=y 271CONFIG_NET=y
250 272
251# 273#
@@ -446,9 +468,11 @@ CONFIG_MTD_PHYSMAP_OF=y
446# 468#
447# CONFIG_MTD_UBI is not set 469# CONFIG_MTD_UBI is not set
448CONFIG_OF_DEVICE=y 470CONFIG_OF_DEVICE=y
471CONFIG_OF_GPIO=y
449# CONFIG_PARPORT is not set 472# CONFIG_PARPORT is not set
450CONFIG_BLK_DEV=y 473CONFIG_BLK_DEV=y
451# CONFIG_BLK_DEV_FD is not set 474# CONFIG_BLK_DEV_FD is not set
475# CONFIG_MAC_FLOPPY is not set
452# CONFIG_BLK_CPQ_DA is not set 476# CONFIG_BLK_CPQ_DA is not set
453# CONFIG_BLK_CPQ_CISS_DA is not set 477# CONFIG_BLK_CPQ_CISS_DA is not set
454# CONFIG_BLK_DEV_DAC960 is not set 478# CONFIG_BLK_DEV_DAC960 is not set
@@ -460,6 +484,7 @@ CONFIG_BLK_DEV_LOOP=y
460# CONFIG_BLK_DEV_RAM is not set 484# CONFIG_BLK_DEV_RAM is not set
461# CONFIG_CDROM_PKTCDVD is not set 485# CONFIG_CDROM_PKTCDVD is not set
462# CONFIG_ATA_OVER_ETH is not set 486# CONFIG_ATA_OVER_ETH is not set
487# CONFIG_BLK_DEV_HD is not set
463# CONFIG_MISC_DEVICES is not set 488# CONFIG_MISC_DEVICES is not set
464CONFIG_HAVE_IDE=y 489CONFIG_HAVE_IDE=y
465# CONFIG_IDE is not set 490# CONFIG_IDE is not set
@@ -480,13 +505,12 @@ CONFIG_HAVE_IDE=y
480# 505#
481 506
482# 507#
483# An alternative FireWire stack is available with EXPERIMENTAL=y 508# A new alternative FireWire stack is available with EXPERIMENTAL=y
484# 509#
485# CONFIG_IEEE1394 is not set 510# CONFIG_IEEE1394 is not set
486# CONFIG_I2O is not set 511# CONFIG_I2O is not set
487# CONFIG_MACINTOSH_DRIVERS is not set 512# CONFIG_MACINTOSH_DRIVERS is not set
488CONFIG_NETDEVICES=y 513CONFIG_NETDEVICES=y
489# CONFIG_NETDEVICES_MULTIQUEUE is not set
490# CONFIG_DUMMY is not set 514# CONFIG_DUMMY is not set
491# CONFIG_BONDING is not set 515# CONFIG_BONDING is not set
492# CONFIG_EQUALIZER is not set 516# CONFIG_EQUALIZER is not set
@@ -510,8 +534,11 @@ CONFIG_DAVICOM_PHY=y
510# CONFIG_REALTEK_PHY is not set 534# CONFIG_REALTEK_PHY is not set
511# CONFIG_FIXED_PHY is not set 535# CONFIG_FIXED_PHY is not set
512CONFIG_MDIO_BITBANG=y 536CONFIG_MDIO_BITBANG=y
537# CONFIG_MDIO_OF_GPIO is not set
513CONFIG_NET_ETHERNET=y 538CONFIG_NET_ETHERNET=y
514CONFIG_MII=y 539CONFIG_MII=y
540# CONFIG_MACE is not set
541# CONFIG_BMAC is not set
515# CONFIG_HAPPYMEAL is not set 542# CONFIG_HAPPYMEAL is not set
516# CONFIG_SUNGEM is not set 543# CONFIG_SUNGEM is not set
517# CONFIG_CASSINI is not set 544# CONFIG_CASSINI is not set
@@ -533,7 +560,6 @@ CONFIG_NETDEV_1000=y
533# CONFIG_DL2K is not set 560# CONFIG_DL2K is not set
534# CONFIG_E1000 is not set 561# CONFIG_E1000 is not set
535# CONFIG_E1000E is not set 562# CONFIG_E1000E is not set
536# CONFIG_E1000E_ENABLED is not set
537# CONFIG_IGB is not set 563# CONFIG_IGB is not set
538# CONFIG_NS83820 is not set 564# CONFIG_NS83820 is not set
539# CONFIG_HAMACHI is not set 565# CONFIG_HAMACHI is not set
@@ -545,6 +571,7 @@ CONFIG_NETDEV_1000=y
545# CONFIG_TIGON3 is not set 571# CONFIG_TIGON3 is not set
546# CONFIG_BNX2 is not set 572# CONFIG_BNX2 is not set
547# CONFIG_GIANFAR is not set 573# CONFIG_GIANFAR is not set
574# CONFIG_MV643XX_ETH is not set
548# CONFIG_QLA3XXX is not set 575# CONFIG_QLA3XXX is not set
549CONFIG_NETDEV_10000=y 576CONFIG_NETDEV_10000=y
550# CONFIG_CHELSIO_T1 is not set 577# CONFIG_CHELSIO_T1 is not set
@@ -610,6 +637,7 @@ CONFIG_KEYBOARD_ATKBD=y
610# CONFIG_KEYBOARD_XTKBD is not set 637# CONFIG_KEYBOARD_XTKBD is not set
611# CONFIG_KEYBOARD_NEWTON is not set 638# CONFIG_KEYBOARD_NEWTON is not set
612# CONFIG_KEYBOARD_STOWAWAY is not set 639# CONFIG_KEYBOARD_STOWAWAY is not set
640# CONFIG_KEYBOARD_GPIO is not set
613CONFIG_INPUT_MOUSE=y 641CONFIG_INPUT_MOUSE=y
614CONFIG_MOUSE_PS2=y 642CONFIG_MOUSE_PS2=y
615CONFIG_MOUSE_PS2_ALPS=y 643CONFIG_MOUSE_PS2_ALPS=y
@@ -620,6 +648,7 @@ CONFIG_MOUSE_PS2_TRACKPOINT=y
620# CONFIG_MOUSE_PS2_TOUCHKIT is not set 648# CONFIG_MOUSE_PS2_TOUCHKIT is not set
621# CONFIG_MOUSE_SERIAL is not set 649# CONFIG_MOUSE_SERIAL is not set
622# CONFIG_MOUSE_VSXXXAA is not set 650# CONFIG_MOUSE_VSXXXAA is not set
651# CONFIG_MOUSE_GPIO is not set
623# CONFIG_INPUT_JOYSTICK is not set 652# CONFIG_INPUT_JOYSTICK is not set
624# CONFIG_INPUT_TABLET is not set 653# CONFIG_INPUT_TABLET is not set
625# CONFIG_INPUT_TOUCHSCREEN is not set 654# CONFIG_INPUT_TOUCHSCREEN is not set
@@ -634,6 +663,7 @@ CONFIG_SERIO_SERPORT=y
634# CONFIG_SERIO_PCIPS2 is not set 663# CONFIG_SERIO_PCIPS2 is not set
635CONFIG_SERIO_LIBPS2=y 664CONFIG_SERIO_LIBPS2=y
636# CONFIG_SERIO_RAW is not set 665# CONFIG_SERIO_RAW is not set
666# CONFIG_SERIO_XILINX_XPS_PS2 is not set
637# CONFIG_GAMEPORT is not set 667# CONFIG_GAMEPORT is not set
638 668
639# 669#
@@ -654,6 +684,7 @@ CONFIG_DEVKMEM=y
654# CONFIG_SERIAL_UARTLITE is not set 684# CONFIG_SERIAL_UARTLITE is not set
655CONFIG_SERIAL_CORE=y 685CONFIG_SERIAL_CORE=y
656CONFIG_SERIAL_CORE_CONSOLE=y 686CONFIG_SERIAL_CORE_CONSOLE=y
687# CONFIG_SERIAL_PMACZILOG is not set
657CONFIG_SERIAL_CPM=y 688CONFIG_SERIAL_CPM=y
658CONFIG_SERIAL_CPM_CONSOLE=y 689CONFIG_SERIAL_CPM_CONSOLE=y
659CONFIG_SERIAL_CPM_SCC1=y 690CONFIG_SERIAL_CPM_SCC1=y
@@ -666,6 +697,8 @@ CONFIG_SERIAL_CPM_SCC4=y
666CONFIG_UNIX98_PTYS=y 697CONFIG_UNIX98_PTYS=y
667CONFIG_LEGACY_PTYS=y 698CONFIG_LEGACY_PTYS=y
668CONFIG_LEGACY_PTY_COUNT=256 699CONFIG_LEGACY_PTY_COUNT=256
700# CONFIG_BRIQ_PANEL is not set
701# CONFIG_HVC_RTAS is not set
669# CONFIG_IPMI_HANDLER is not set 702# CONFIG_IPMI_HANDLER is not set
670CONFIG_HW_RANDOM=y 703CONFIG_HW_RANDOM=y
671# CONFIG_NVRAM is not set 704# CONFIG_NVRAM is not set
@@ -676,10 +709,28 @@ CONFIG_HW_RANDOM=y
676CONFIG_DEVPORT=y 709CONFIG_DEVPORT=y
677# CONFIG_I2C is not set 710# CONFIG_I2C is not set
678# CONFIG_SPI is not set 711# CONFIG_SPI is not set
712CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
713CONFIG_ARCH_REQUIRE_GPIOLIB=y
714CONFIG_GPIOLIB=y
715# CONFIG_DEBUG_GPIO is not set
716
717#
718# I2C GPIO expanders:
719#
720
721#
722# PCI GPIO expanders:
723#
724# CONFIG_GPIO_BT8XX is not set
725
726#
727# SPI GPIO expanders:
728#
679# CONFIG_W1 is not set 729# CONFIG_W1 is not set
680# CONFIG_POWER_SUPPLY is not set 730# CONFIG_POWER_SUPPLY is not set
681# CONFIG_HWMON is not set 731# CONFIG_HWMON is not set
682# CONFIG_THERMAL is not set 732# CONFIG_THERMAL is not set
733# CONFIG_THERMAL_HWMON is not set
683# CONFIG_WATCHDOG is not set 734# CONFIG_WATCHDOG is not set
684 735
685# 736#
@@ -691,8 +742,10 @@ CONFIG_SSB_POSSIBLE=y
691# 742#
692# Multifunction device drivers 743# Multifunction device drivers
693# 744#
745# CONFIG_MFD_CORE is not set
694# CONFIG_MFD_SM501 is not set 746# CONFIG_MFD_SM501 is not set
695# CONFIG_HTC_PASIC3 is not set 747# CONFIG_HTC_PASIC3 is not set
748# CONFIG_MFD_TMIO is not set
696 749
697# 750#
698# Multimedia devices 751# Multimedia devices
@@ -724,10 +777,6 @@ CONFIG_DAB=y
724# Display device support 777# Display device support
725# 778#
726# CONFIG_DISPLAY_SUPPORT is not set 779# CONFIG_DISPLAY_SUPPORT is not set
727
728#
729# Sound
730#
731# CONFIG_SOUND is not set 780# CONFIG_SOUND is not set
732# CONFIG_HID_SUPPORT is not set 781# CONFIG_HID_SUPPORT is not set
733# CONFIG_USB_SUPPORT is not set 782# CONFIG_USB_SUPPORT is not set
@@ -798,6 +847,7 @@ CONFIG_TMPFS=y
798CONFIG_CRAMFS=y 847CONFIG_CRAMFS=y
799# CONFIG_VXFS_FS is not set 848# CONFIG_VXFS_FS is not set
800# CONFIG_MINIX_FS is not set 849# CONFIG_MINIX_FS is not set
850# CONFIG_OMFS_FS is not set
801# CONFIG_HPFS_FS is not set 851# CONFIG_HPFS_FS is not set
802# CONFIG_QNX4FS_FS is not set 852# CONFIG_QNX4FS_FS is not set
803# CONFIG_ROMFS_FS is not set 853# CONFIG_ROMFS_FS is not set
@@ -807,8 +857,8 @@ CONFIG_NETWORK_FILESYSTEMS=y
807CONFIG_NFS_FS=y 857CONFIG_NFS_FS=y
808CONFIG_NFS_V3=y 858CONFIG_NFS_V3=y
809CONFIG_NFS_V3_ACL=y 859CONFIG_NFS_V3_ACL=y
810# CONFIG_NFSD is not set
811CONFIG_ROOT_NFS=y 860CONFIG_ROOT_NFS=y
861# CONFIG_NFSD is not set
812CONFIG_LOCKD=y 862CONFIG_LOCKD=y
813CONFIG_LOCKD_V4=y 863CONFIG_LOCKD_V4=y
814CONFIG_NFS_ACL_SUPPORT=y 864CONFIG_NFS_ACL_SUPPORT=y
@@ -888,6 +938,7 @@ CONFIG_BITREVERSE=y
888# CONFIG_GENERIC_FIND_FIRST_BIT is not set 938# CONFIG_GENERIC_FIND_FIRST_BIT is not set
889CONFIG_CRC_CCITT=y 939CONFIG_CRC_CCITT=y
890# CONFIG_CRC16 is not set 940# CONFIG_CRC16 is not set
941# CONFIG_CRC_T10DIF is not set
891# CONFIG_CRC_ITU_T is not set 942# CONFIG_CRC_ITU_T is not set
892CONFIG_CRC32=y 943CONFIG_CRC32=y
893# CONFIG_CRC7 is not set 944# CONFIG_CRC7 is not set
@@ -914,6 +965,8 @@ CONFIG_MAGIC_SYSRQ=y
914CONFIG_DEBUG_KERNEL=y 965CONFIG_DEBUG_KERNEL=y
915# CONFIG_DEBUG_SHIRQ is not set 966# CONFIG_DEBUG_SHIRQ is not set
916CONFIG_DETECT_SOFTLOCKUP=y 967CONFIG_DETECT_SOFTLOCKUP=y
968# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
969CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
917CONFIG_SCHED_DEBUG=y 970CONFIG_SCHED_DEBUG=y
918# CONFIG_SCHEDSTATS is not set 971# CONFIG_SCHEDSTATS is not set
919# CONFIG_TIMER_STATS is not set 972# CONFIG_TIMER_STATS is not set
@@ -931,19 +984,31 @@ CONFIG_DEBUG_BUGVERBOSE=y
931CONFIG_DEBUG_INFO=y 984CONFIG_DEBUG_INFO=y
932# CONFIG_DEBUG_VM is not set 985# CONFIG_DEBUG_VM is not set
933# CONFIG_DEBUG_WRITECOUNT is not set 986# CONFIG_DEBUG_WRITECOUNT is not set
987# CONFIG_DEBUG_MEMORY_INIT is not set
934# CONFIG_DEBUG_LIST is not set 988# CONFIG_DEBUG_LIST is not set
935# CONFIG_DEBUG_SG is not set 989# CONFIG_DEBUG_SG is not set
936# CONFIG_BOOT_PRINTK_DELAY is not set 990# CONFIG_BOOT_PRINTK_DELAY is not set
991# CONFIG_RCU_TORTURE_TEST is not set
937# CONFIG_BACKTRACE_SELF_TEST is not set 992# CONFIG_BACKTRACE_SELF_TEST is not set
938# CONFIG_FAULT_INJECTION is not set 993# CONFIG_FAULT_INJECTION is not set
994# CONFIG_LATENCYTOP is not set
995CONFIG_SYSCTL_SYSCALL_CHECK=y
996CONFIG_HAVE_FTRACE=y
997CONFIG_HAVE_DYNAMIC_FTRACE=y
998# CONFIG_FTRACE is not set
999# CONFIG_SCHED_TRACER is not set
1000# CONFIG_CONTEXT_SWITCH_TRACER is not set
939# CONFIG_SAMPLES is not set 1001# CONFIG_SAMPLES is not set
1002CONFIG_HAVE_ARCH_KGDB=y
940# CONFIG_DEBUG_STACKOVERFLOW is not set 1003# CONFIG_DEBUG_STACKOVERFLOW is not set
941# CONFIG_DEBUG_STACK_USAGE is not set 1004# CONFIG_DEBUG_STACK_USAGE is not set
942# CONFIG_DEBUG_PAGEALLOC is not set 1005# CONFIG_DEBUG_PAGEALLOC is not set
943# CONFIG_DEBUGGER is not set 1006# CONFIG_CODE_PATCHING_SELFTEST is not set
944# CONFIG_KGDB_CONSOLE is not set 1007# CONFIG_FTR_FIXUP_SELFTEST is not set
1008# CONFIG_XMON is not set
945# CONFIG_IRQSTACKS is not set 1009# CONFIG_IRQSTACKS is not set
946CONFIG_BDI_SWITCH=y 1010CONFIG_BDI_SWITCH=y
1011# CONFIG_BOOTX_TEXT is not set
947# CONFIG_PPC_EARLY_DEBUG is not set 1012# CONFIG_PPC_EARLY_DEBUG is not set
948 1013
949# 1014#
@@ -951,6 +1016,7 @@ CONFIG_BDI_SWITCH=y
951# 1016#
952# CONFIG_KEYS is not set 1017# CONFIG_KEYS is not set
953# CONFIG_SECURITY is not set 1018# CONFIG_SECURITY is not set
1019# CONFIG_SECURITY_FILE_CAPABILITIES is not set
954CONFIG_CRYPTO=y 1020CONFIG_CRYPTO=y
955 1021
956# 1022#
@@ -991,6 +1057,10 @@ CONFIG_CRYPTO_PCBC=y
991# CONFIG_CRYPTO_MD4 is not set 1057# CONFIG_CRYPTO_MD4 is not set
992CONFIG_CRYPTO_MD5=y 1058CONFIG_CRYPTO_MD5=y
993# CONFIG_CRYPTO_MICHAEL_MIC is not set 1059# CONFIG_CRYPTO_MICHAEL_MIC is not set
1060# CONFIG_CRYPTO_RMD128 is not set
1061# CONFIG_CRYPTO_RMD160 is not set
1062# CONFIG_CRYPTO_RMD256 is not set
1063# CONFIG_CRYPTO_RMD320 is not set
994# CONFIG_CRYPTO_SHA1 is not set 1064# CONFIG_CRYPTO_SHA1 is not set
995# CONFIG_CRYPTO_SHA256 is not set 1065# CONFIG_CRYPTO_SHA256 is not set
996# CONFIG_CRYPTO_SHA512 is not set 1066# CONFIG_CRYPTO_SHA512 is not set
@@ -1021,6 +1091,6 @@ CONFIG_CRYPTO_DES=y
1021# CONFIG_CRYPTO_DEFLATE is not set 1091# CONFIG_CRYPTO_DEFLATE is not set
1022# CONFIG_CRYPTO_LZO is not set 1092# CONFIG_CRYPTO_LZO is not set
1023# CONFIG_CRYPTO_HW is not set 1093# CONFIG_CRYPTO_HW is not set
1024# CONFIG_PPC_CLOCK is not set 1094CONFIG_PPC_CLOCK=y
1025CONFIG_PPC_LIB_RHEAP=y 1095CONFIG_PPC_LIB_RHEAP=y
1026# CONFIG_VIRTUALIZATION is not set 1096# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/configs/mpc83xx_defconfig b/arch/powerpc/configs/mpc83xx_defconfig
index 4293c8be06e1..916e3df7cc45 100644
--- a/arch/powerpc/configs/mpc83xx_defconfig
+++ b/arch/powerpc/configs/mpc83xx_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc5 3# Linux kernel version: 2.6.27-rc4
4# Mon Jun 9 08:52:14 2008 4# Thu Aug 21 07:16:25 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -16,6 +16,7 @@ CONFIG_6xx=y
16# CONFIG_E200 is not set 16# CONFIG_E200 is not set
17CONFIG_PPC_FPU=y 17CONFIG_PPC_FPU=y
18# CONFIG_FSL_EMB_PERFMON is not set 18# CONFIG_FSL_EMB_PERFMON is not set
19# CONFIG_ALTIVEC is not set
19CONFIG_PPC_STD_MMU=y 20CONFIG_PPC_STD_MMU=y
20CONFIG_PPC_STD_MMU_32=y 21CONFIG_PPC_STD_MMU_32=y
21# CONFIG_PPC_MM_SLICES is not set 22# CONFIG_PPC_MM_SLICES is not set
@@ -32,12 +33,14 @@ CONFIG_GENERIC_HARDIRQS=y
32# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set 33# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
33CONFIG_IRQ_PER_CPU=y 34CONFIG_IRQ_PER_CPU=y
34CONFIG_STACKTRACE_SUPPORT=y 35CONFIG_STACKTRACE_SUPPORT=y
36CONFIG_HAVE_LATENCYTOP_SUPPORT=y
35CONFIG_LOCKDEP_SUPPORT=y 37CONFIG_LOCKDEP_SUPPORT=y
36CONFIG_RWSEM_XCHGADD_ALGORITHM=y 38CONFIG_RWSEM_XCHGADD_ALGORITHM=y
37CONFIG_ARCH_HAS_ILOG2_U32=y 39CONFIG_ARCH_HAS_ILOG2_U32=y
38CONFIG_GENERIC_HWEIGHT=y 40CONFIG_GENERIC_HWEIGHT=y
39CONFIG_GENERIC_CALIBRATE_DELAY=y 41CONFIG_GENERIC_CALIBRATE_DELAY=y
40CONFIG_GENERIC_FIND_NEXT_BIT=y 42CONFIG_GENERIC_FIND_NEXT_BIT=y
43CONFIG_GENERIC_GPIO=y
41# CONFIG_ARCH_NO_VIRT_TO_BUS is not set 44# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
42CONFIG_PPC=y 45CONFIG_PPC=y
43CONFIG_EARLY_PRINTK=y 46CONFIG_EARLY_PRINTK=y
@@ -51,6 +54,10 @@ CONFIG_PPC_UDBG_16550=y
51CONFIG_AUDIT_ARCH=y 54CONFIG_AUDIT_ARCH=y
52CONFIG_GENERIC_BUG=y 55CONFIG_GENERIC_BUG=y
53CONFIG_DEFAULT_UIMAGE=y 56CONFIG_DEFAULT_UIMAGE=y
57CONFIG_REDBOOT=y
58CONFIG_HIBERNATE_32=y
59CONFIG_ARCH_HIBERNATION_POSSIBLE=y
60CONFIG_ARCH_SUSPEND_POSSIBLE=y
54# CONFIG_PPC_DCR_NATIVE is not set 61# CONFIG_PPC_DCR_NATIVE is not set
55# CONFIG_PPC_DCR_MMIO is not set 62# CONFIG_PPC_DCR_MMIO is not set
56CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 63CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
@@ -88,13 +95,13 @@ CONFIG_INITRAMFS_SOURCE=""
88CONFIG_SYSCTL=y 95CONFIG_SYSCTL=y
89CONFIG_EMBEDDED=y 96CONFIG_EMBEDDED=y
90CONFIG_SYSCTL_SYSCALL=y 97CONFIG_SYSCTL_SYSCALL=y
91CONFIG_SYSCTL_SYSCALL_CHECK=y
92CONFIG_KALLSYMS=y 98CONFIG_KALLSYMS=y
93# CONFIG_KALLSYMS_EXTRA_PASS is not set 99# CONFIG_KALLSYMS_EXTRA_PASS is not set
94CONFIG_HOTPLUG=y 100CONFIG_HOTPLUG=y
95CONFIG_PRINTK=y 101CONFIG_PRINTK=y
96CONFIG_BUG=y 102CONFIG_BUG=y
97CONFIG_ELF_CORE=y 103CONFIG_ELF_CORE=y
104CONFIG_PCSPKR_PLATFORM=y
98CONFIG_COMPAT_BRK=y 105CONFIG_COMPAT_BRK=y
99CONFIG_BASE_FULL=y 106CONFIG_BASE_FULL=y
100CONFIG_FUTEX=y 107CONFIG_FUTEX=y
@@ -112,10 +119,16 @@ CONFIG_SLAB=y
112# CONFIG_MARKERS is not set 119# CONFIG_MARKERS is not set
113CONFIG_HAVE_OPROFILE=y 120CONFIG_HAVE_OPROFILE=y
114# CONFIG_KPROBES is not set 121# CONFIG_KPROBES is not set
122CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
123CONFIG_HAVE_IOREMAP_PROT=y
115CONFIG_HAVE_KPROBES=y 124CONFIG_HAVE_KPROBES=y
116CONFIG_HAVE_KRETPROBES=y 125CONFIG_HAVE_KRETPROBES=y
126CONFIG_HAVE_ARCH_TRACEHOOK=y
117# CONFIG_HAVE_DMA_ATTRS is not set 127# CONFIG_HAVE_DMA_ATTRS is not set
128# CONFIG_USE_GENERIC_SMP_HELPERS is not set
129# CONFIG_HAVE_CLK is not set
118CONFIG_PROC_PAGE_MONITOR=y 130CONFIG_PROC_PAGE_MONITOR=y
131# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
119CONFIG_SLABINFO=y 132CONFIG_SLABINFO=y
120CONFIG_RT_MUTEXES=y 133CONFIG_RT_MUTEXES=y
121# CONFIG_TINY_SHMEM is not set 134# CONFIG_TINY_SHMEM is not set
@@ -126,12 +139,13 @@ CONFIG_MODULE_UNLOAD=y
126# CONFIG_MODULE_FORCE_UNLOAD is not set 139# CONFIG_MODULE_FORCE_UNLOAD is not set
127# CONFIG_MODVERSIONS is not set 140# CONFIG_MODVERSIONS is not set
128# CONFIG_MODULE_SRCVERSION_ALL is not set 141# CONFIG_MODULE_SRCVERSION_ALL is not set
129# CONFIG_KMOD is not set 142CONFIG_KMOD=y
130CONFIG_BLOCK=y 143CONFIG_BLOCK=y
131# CONFIG_LBD is not set 144# CONFIG_LBD is not set
132# CONFIG_BLK_DEV_IO_TRACE is not set 145# CONFIG_BLK_DEV_IO_TRACE is not set
133# CONFIG_LSF is not set 146# CONFIG_LSF is not set
134# CONFIG_BLK_DEV_BSG is not set 147# CONFIG_BLK_DEV_BSG is not set
148# CONFIG_BLK_DEV_INTEGRITY is not set
135 149
136# 150#
137# IO Schedulers 151# IO Schedulers
@@ -150,40 +164,52 @@ CONFIG_CLASSIC_RCU=y
150# 164#
151# Platform support 165# Platform support
152# 166#
153# CONFIG_PPC_MULTIPLATFORM is not set 167CONFIG_PPC_MULTIPLATFORM=y
154# CONFIG_PPC_82xx is not set 168CONFIG_CLASSIC32=y
155CONFIG_PPC_83xx=y 169CONFIG_PPC_CHRP=y
156# CONFIG_PPC_86xx is not set 170# CONFIG_MPC5121_ADS is not set
157# CONFIG_PPC_MPC512x is not set 171# CONFIG_MPC5121_GENERIC is not set
158# CONFIG_PPC_MPC5121 is not set 172# CONFIG_PPC_MPC52xx is not set
173CONFIG_PPC_PMAC=y
159# CONFIG_PPC_CELL is not set 174# CONFIG_PPC_CELL is not set
160# CONFIG_PPC_CELL_NATIVE is not set 175# CONFIG_PPC_CELL_NATIVE is not set
176# CONFIG_PPC_82xx is not set
161# CONFIG_PQ2ADS is not set 177# CONFIG_PQ2ADS is not set
162CONFIG_MPC83xx=y 178CONFIG_PPC_83xx=y
163CONFIG_MPC831x_RDB=y 179CONFIG_MPC831x_RDB=y
164CONFIG_MPC832x_MDS=y 180CONFIG_MPC832x_MDS=y
165CONFIG_MPC832x_RDB=y 181CONFIG_MPC832x_RDB=y
166CONFIG_MPC834x_MDS=y 182CONFIG_MPC834x_MDS=y
167CONFIG_MPC834x_ITX=y 183CONFIG_MPC834x_ITX=y
168CONFIG_MPC836x_MDS=y 184CONFIG_MPC836x_MDS=y
185CONFIG_MPC836x_RDK=y
169CONFIG_MPC837x_MDS=y 186CONFIG_MPC837x_MDS=y
170CONFIG_MPC837x_RDB=y 187CONFIG_MPC837x_RDB=y
171CONFIG_SBC834x=y 188CONFIG_SBC834x=y
189CONFIG_ASP834x=y
172CONFIG_PPC_MPC831x=y 190CONFIG_PPC_MPC831x=y
173CONFIG_PPC_MPC832x=y 191CONFIG_PPC_MPC832x=y
174CONFIG_PPC_MPC834x=y 192CONFIG_PPC_MPC834x=y
175CONFIG_PPC_MPC837x=y 193CONFIG_PPC_MPC837x=y
194# CONFIG_PPC_86xx is not set
195# CONFIG_EMBEDDED6xx is not set
196CONFIG_PPC_NATIVE=y
197# CONFIG_UDBG_RTAS_CONSOLE is not set
176CONFIG_IPIC=y 198CONFIG_IPIC=y
177# CONFIG_MPIC is not set 199CONFIG_MPIC=y
178# CONFIG_MPIC_WEIRD is not set 200# CONFIG_MPIC_WEIRD is not set
179# CONFIG_PPC_I8259 is not set 201CONFIG_PPC_I8259=y
180# CONFIG_PPC_RTAS is not set 202CONFIG_PPC_RTAS=y
203# CONFIG_RTAS_ERROR_LOGGING is not set
204CONFIG_RTAS_PROC=y
181# CONFIG_MMIO_NVRAM is not set 205# CONFIG_MMIO_NVRAM is not set
182# CONFIG_PPC_MPC106 is not set 206CONFIG_PPC_MPC106=y
183# CONFIG_PPC_970_NAP is not set 207# CONFIG_PPC_970_NAP is not set
184# CONFIG_PPC_INDIRECT_IO is not set 208# CONFIG_PPC_INDIRECT_IO is not set
185# CONFIG_GENERIC_IOMAP is not set 209# CONFIG_GENERIC_IOMAP is not set
186# CONFIG_CPU_FREQ is not set 210# CONFIG_CPU_FREQ is not set
211# CONFIG_PPC601_SYNC_FIX is not set
212# CONFIG_TAU is not set
187CONFIG_QUICC_ENGINE=y 213CONFIG_QUICC_ENGINE=y
188# CONFIG_FSL_ULI1575 is not set 214# CONFIG_FSL_ULI1575 is not set
189 215
@@ -211,6 +237,7 @@ CONFIG_MATH_EMULATION=y
211CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y 237CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
212CONFIG_ARCH_HAS_WALK_MEMORY=y 238CONFIG_ARCH_HAS_WALK_MEMORY=y
213CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y 239CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
240# CONFIG_KEXEC is not set
214CONFIG_ARCH_FLATMEM_ENABLE=y 241CONFIG_ARCH_FLATMEM_ENABLE=y
215CONFIG_ARCH_POPULATES_NODE_MAP=y 242CONFIG_ARCH_POPULATES_NODE_MAP=y
216CONFIG_SELECT_MEMORY_MODEL=y 243CONFIG_SELECT_MEMORY_MODEL=y
@@ -223,6 +250,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
223# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set 250# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
224CONFIG_PAGEFLAGS_EXTENDED=y 251CONFIG_PAGEFLAGS_EXTENDED=y
225CONFIG_SPLIT_PTLOCK_CPUS=4 252CONFIG_SPLIT_PTLOCK_CPUS=4
253CONFIG_MIGRATION=y
226# CONFIG_RESOURCES_64BIT is not set 254# CONFIG_RESOURCES_64BIT is not set
227CONFIG_ZONE_DMA_FLAG=1 255CONFIG_ZONE_DMA_FLAG=1
228CONFIG_BOUNCE=y 256CONFIG_BOUNCE=y
@@ -230,6 +258,7 @@ CONFIG_VIRT_TO_BUS=y
230CONFIG_FORCE_MAX_ZONEORDER=11 258CONFIG_FORCE_MAX_ZONEORDER=11
231CONFIG_PROC_DEVICETREE=y 259CONFIG_PROC_DEVICETREE=y
232# CONFIG_CMDLINE_BOOL is not set 260# CONFIG_CMDLINE_BOOL is not set
261CONFIG_EXTRA_TARGETS=""
233# CONFIG_PM is not set 262# CONFIG_PM is not set
234CONFIG_SECCOMP=y 263CONFIG_SECCOMP=y
235CONFIG_ISA_DMA_API=y 264CONFIG_ISA_DMA_API=y
@@ -237,15 +266,24 @@ CONFIG_ISA_DMA_API=y
237# 266#
238# Bus options 267# Bus options
239# 268#
269# CONFIG_ISA is not set
240CONFIG_ZONE_DMA=y 270CONFIG_ZONE_DMA=y
241CONFIG_GENERIC_ISA_DMA=y 271CONFIG_GENERIC_ISA_DMA=y
242CONFIG_PPC_INDIRECT_PCI=y 272CONFIG_PPC_INDIRECT_PCI=y
243CONFIG_FSL_SOC=y 273CONFIG_FSL_SOC=y
244# CONFIG_PCI is not set 274CONFIG_FSL_PCI=y
245# CONFIG_PCI_DOMAINS is not set 275CONFIG_FSL_LBC=y
246# CONFIG_PCI_SYSCALL is not set 276CONFIG_FSL_GTM=y
247# CONFIG_ARCH_SUPPORTS_MSI is not set 277CONFIG_PPC_PCI_CHOICE=y
278CONFIG_PCI=y
279CONFIG_PCI_DOMAINS=y
280CONFIG_PCI_SYSCALL=y
281# CONFIG_PCIEPORTBUS is not set
282CONFIG_ARCH_SUPPORTS_MSI=y
283# CONFIG_PCI_MSI is not set
284CONFIG_PCI_LEGACY=y
248# CONFIG_PCCARD is not set 285# CONFIG_PCCARD is not set
286# CONFIG_HOTPLUG_PCI is not set
249# CONFIG_HAS_RAPIDIO is not set 287# CONFIG_HAS_RAPIDIO is not set
250 288
251# 289#
@@ -261,10 +299,6 @@ CONFIG_PAGE_OFFSET=0xc0000000
261CONFIG_KERNEL_START=0xc0000000 299CONFIG_KERNEL_START=0xc0000000
262CONFIG_PHYSICAL_START=0x00000000 300CONFIG_PHYSICAL_START=0x00000000
263CONFIG_TASK_SIZE=0xc0000000 301CONFIG_TASK_SIZE=0xc0000000
264
265#
266# Networking
267#
268CONFIG_NET=y 302CONFIG_NET=y
269 303
270# 304#
@@ -412,11 +446,13 @@ CONFIG_MTD_CFI_UTIL=y
412# CONFIG_MTD_COMPLEX_MAPPINGS is not set 446# CONFIG_MTD_COMPLEX_MAPPINGS is not set
413# CONFIG_MTD_PHYSMAP is not set 447# CONFIG_MTD_PHYSMAP is not set
414CONFIG_MTD_PHYSMAP_OF=y 448CONFIG_MTD_PHYSMAP_OF=y
449# CONFIG_MTD_INTEL_VR_NOR is not set
415# CONFIG_MTD_PLATRAM is not set 450# CONFIG_MTD_PLATRAM is not set
416 451
417# 452#
418# Self-contained MTD device drivers 453# Self-contained MTD device drivers
419# 454#
455# CONFIG_MTD_PMC551 is not set
420# CONFIG_MTD_SLRAM is not set 456# CONFIG_MTD_SLRAM is not set
421# CONFIG_MTD_PHRAM is not set 457# CONFIG_MTD_PHRAM is not set
422# CONFIG_MTD_MTDRAM is not set 458# CONFIG_MTD_MTDRAM is not set
@@ -434,10 +470,12 @@ CONFIG_MTD_NAND_VERIFY_WRITE=y
434# CONFIG_MTD_NAND_MUSEUM_IDS is not set 470# CONFIG_MTD_NAND_MUSEUM_IDS is not set
435CONFIG_MTD_NAND_IDS=y 471CONFIG_MTD_NAND_IDS=y
436# CONFIG_MTD_NAND_DISKONCHIP is not set 472# CONFIG_MTD_NAND_DISKONCHIP is not set
473# CONFIG_MTD_NAND_CAFE is not set
437# CONFIG_MTD_NAND_NANDSIM is not set 474# CONFIG_MTD_NAND_NANDSIM is not set
438# CONFIG_MTD_NAND_PLATFORM is not set 475# CONFIG_MTD_NAND_PLATFORM is not set
439# CONFIG_MTD_ALAUDA is not set 476# CONFIG_MTD_ALAUDA is not set
440CONFIG_MTD_NAND_FSL_ELBC=y 477CONFIG_MTD_NAND_FSL_ELBC=y
478# CONFIG_MTD_NAND_FSL_UPM is not set
441# CONFIG_MTD_ONENAND is not set 479# CONFIG_MTD_ONENAND is not set
442 480
443# 481#
@@ -445,14 +483,21 @@ CONFIG_MTD_NAND_FSL_ELBC=y
445# 483#
446# CONFIG_MTD_UBI is not set 484# CONFIG_MTD_UBI is not set
447CONFIG_OF_DEVICE=y 485CONFIG_OF_DEVICE=y
486CONFIG_OF_GPIO=y
448CONFIG_OF_I2C=y 487CONFIG_OF_I2C=y
449# CONFIG_PARPORT is not set 488# CONFIG_PARPORT is not set
450CONFIG_BLK_DEV=y 489CONFIG_BLK_DEV=y
451# CONFIG_BLK_DEV_FD is not set 490# CONFIG_BLK_DEV_FD is not set
491# CONFIG_MAC_FLOPPY is not set
492# CONFIG_BLK_CPQ_DA is not set
493# CONFIG_BLK_CPQ_CISS_DA is not set
494# CONFIG_BLK_DEV_DAC960 is not set
495# CONFIG_BLK_DEV_UMEM is not set
452# CONFIG_BLK_DEV_COW_COMMON is not set 496# CONFIG_BLK_DEV_COW_COMMON is not set
453CONFIG_BLK_DEV_LOOP=y 497CONFIG_BLK_DEV_LOOP=y
454# CONFIG_BLK_DEV_CRYPTOLOOP is not set 498# CONFIG_BLK_DEV_CRYPTOLOOP is not set
455# CONFIG_BLK_DEV_NBD is not set 499# CONFIG_BLK_DEV_NBD is not set
500# CONFIG_BLK_DEV_SX8 is not set
456# CONFIG_BLK_DEV_UB is not set 501# CONFIG_BLK_DEV_UB is not set
457CONFIG_BLK_DEV_RAM=y 502CONFIG_BLK_DEV_RAM=y
458CONFIG_BLK_DEV_RAM_COUNT=16 503CONFIG_BLK_DEV_RAM_COUNT=16
@@ -460,9 +505,14 @@ CONFIG_BLK_DEV_RAM_SIZE=32768
460# CONFIG_BLK_DEV_XIP is not set 505# CONFIG_BLK_DEV_XIP is not set
461# CONFIG_CDROM_PKTCDVD is not set 506# CONFIG_CDROM_PKTCDVD is not set
462# CONFIG_ATA_OVER_ETH is not set 507# CONFIG_ATA_OVER_ETH is not set
508# CONFIG_BLK_DEV_HD is not set
463CONFIG_MISC_DEVICES=y 509CONFIG_MISC_DEVICES=y
510# CONFIG_PHANTOM is not set
464# CONFIG_EEPROM_93CX6 is not set 511# CONFIG_EEPROM_93CX6 is not set
512# CONFIG_SGI_IOC4 is not set
513# CONFIG_TIFM_CORE is not set
465# CONFIG_ENCLOSURE_SERVICES is not set 514# CONFIG_ENCLOSURE_SERVICES is not set
515# CONFIG_HP_ILO is not set
466CONFIG_HAVE_IDE=y 516CONFIG_HAVE_IDE=y
467# CONFIG_IDE is not set 517# CONFIG_IDE is not set
468 518
@@ -505,24 +555,128 @@ CONFIG_SCSI_WAIT_SCAN=m
505# CONFIG_SCSI_SRP_ATTRS is not set 555# CONFIG_SCSI_SRP_ATTRS is not set
506CONFIG_SCSI_LOWLEVEL=y 556CONFIG_SCSI_LOWLEVEL=y
507# CONFIG_ISCSI_TCP is not set 557# CONFIG_ISCSI_TCP is not set
558# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
559# CONFIG_SCSI_3W_9XXX is not set
560# CONFIG_SCSI_ACARD is not set
561# CONFIG_SCSI_AACRAID is not set
562# CONFIG_SCSI_AIC7XXX is not set
563# CONFIG_SCSI_AIC7XXX_OLD is not set
564# CONFIG_SCSI_AIC79XX is not set
565# CONFIG_SCSI_AIC94XX is not set
566# CONFIG_SCSI_DPT_I2O is not set
567# CONFIG_SCSI_ADVANSYS is not set
568# CONFIG_SCSI_ARCMSR is not set
569# CONFIG_MEGARAID_NEWGEN is not set
570# CONFIG_MEGARAID_LEGACY is not set
571# CONFIG_MEGARAID_SAS is not set
572# CONFIG_SCSI_HPTIOP is not set
573# CONFIG_SCSI_BUSLOGIC is not set
574# CONFIG_SCSI_DMX3191D is not set
575# CONFIG_SCSI_EATA is not set
576# CONFIG_SCSI_FUTURE_DOMAIN is not set
577# CONFIG_SCSI_GDTH is not set
578# CONFIG_SCSI_IPS is not set
579# CONFIG_SCSI_INITIO is not set
580# CONFIG_SCSI_INIA100 is not set
581# CONFIG_SCSI_MVSAS is not set
582# CONFIG_SCSI_STEX is not set
583# CONFIG_SCSI_SYM53C8XX_2 is not set
584# CONFIG_SCSI_IPR is not set
585# CONFIG_SCSI_QLOGIC_1280 is not set
586# CONFIG_SCSI_QLA_FC is not set
587# CONFIG_SCSI_QLA_ISCSI is not set
588# CONFIG_SCSI_LPFC is not set
589# CONFIG_SCSI_DC395x is not set
590# CONFIG_SCSI_DC390T is not set
591# CONFIG_SCSI_NSP32 is not set
508# CONFIG_SCSI_DEBUG is not set 592# CONFIG_SCSI_DEBUG is not set
593# CONFIG_SCSI_MESH is not set
594# CONFIG_SCSI_MAC53C94 is not set
595# CONFIG_SCSI_SRP is not set
596# CONFIG_SCSI_DH is not set
509CONFIG_ATA=y 597CONFIG_ATA=y
510# CONFIG_ATA_NONSTANDARD is not set 598# CONFIG_ATA_NONSTANDARD is not set
511CONFIG_SATA_PMP=y 599CONFIG_SATA_PMP=y
600# CONFIG_SATA_AHCI is not set
601# CONFIG_SATA_SIL24 is not set
512CONFIG_SATA_FSL=y 602CONFIG_SATA_FSL=y
513CONFIG_ATA_SFF=y 603CONFIG_ATA_SFF=y
604# CONFIG_SATA_SVW is not set
605# CONFIG_ATA_PIIX is not set
514# CONFIG_SATA_MV is not set 606# CONFIG_SATA_MV is not set
607# CONFIG_SATA_NV is not set
608# CONFIG_PDC_ADMA is not set
609# CONFIG_SATA_QSTOR is not set
610# CONFIG_SATA_PROMISE is not set
611# CONFIG_SATA_SX4 is not set
612# CONFIG_SATA_SIL is not set
613# CONFIG_SATA_SIS is not set
614# CONFIG_SATA_ULI is not set
615# CONFIG_SATA_VIA is not set
616# CONFIG_SATA_VITESSE is not set
617# CONFIG_SATA_INIC162X is not set
618# CONFIG_PATA_ALI is not set
619# CONFIG_PATA_AMD is not set
620# CONFIG_PATA_ARTOP is not set
621# CONFIG_PATA_ATIIXP is not set
622# CONFIG_PATA_CMD640_PCI is not set
623# CONFIG_PATA_CMD64X is not set
624# CONFIG_PATA_CS5520 is not set
625# CONFIG_PATA_CS5530 is not set
626# CONFIG_PATA_CYPRESS is not set
627# CONFIG_PATA_EFAR is not set
628# CONFIG_ATA_GENERIC is not set
629# CONFIG_PATA_HPT366 is not set
630# CONFIG_PATA_HPT37X is not set
631# CONFIG_PATA_HPT3X2N is not set
632# CONFIG_PATA_HPT3X3 is not set
633# CONFIG_PATA_IT821X is not set
634# CONFIG_PATA_IT8213 is not set
635# CONFIG_PATA_JMICRON is not set
636# CONFIG_PATA_TRIFLEX is not set
637# CONFIG_PATA_MARVELL is not set
638# CONFIG_PATA_MPIIX is not set
639# CONFIG_PATA_OLDPIIX is not set
640# CONFIG_PATA_NETCELL is not set
641# CONFIG_PATA_NINJA32 is not set
642# CONFIG_PATA_NS87410 is not set
643# CONFIG_PATA_NS87415 is not set
644# CONFIG_PATA_OPTI is not set
645# CONFIG_PATA_OPTIDMA is not set
646# CONFIG_PATA_PDC_OLD is not set
647# CONFIG_PATA_RADISYS is not set
648# CONFIG_PATA_RZ1000 is not set
649# CONFIG_PATA_SC1200 is not set
650# CONFIG_PATA_SERVERWORKS is not set
651# CONFIG_PATA_PDC2027X is not set
652# CONFIG_PATA_SIL680 is not set
653# CONFIG_PATA_SIS is not set
654# CONFIG_PATA_VIA is not set
655# CONFIG_PATA_WINBOND is not set
515# CONFIG_PATA_PLATFORM is not set 656# CONFIG_PATA_PLATFORM is not set
657# CONFIG_PATA_SCH is not set
516# CONFIG_MD is not set 658# CONFIG_MD is not set
659# CONFIG_FUSION is not set
660
661#
662# IEEE 1394 (FireWire) support
663#
664
665#
666# Enable only one of the two stacks, unless you know what you are doing
667#
668# CONFIG_FIREWIRE is not set
669# CONFIG_IEEE1394 is not set
670# CONFIG_I2O is not set
517# CONFIG_MACINTOSH_DRIVERS is not set 671# CONFIG_MACINTOSH_DRIVERS is not set
518CONFIG_NETDEVICES=y 672CONFIG_NETDEVICES=y
519# CONFIG_NETDEVICES_MULTIQUEUE is not set
520# CONFIG_DUMMY is not set 673# CONFIG_DUMMY is not set
521# CONFIG_BONDING is not set 674# CONFIG_BONDING is not set
522# CONFIG_MACVLAN is not set 675# CONFIG_MACVLAN is not set
523# CONFIG_EQUALIZER is not set 676# CONFIG_EQUALIZER is not set
524# CONFIG_TUN is not set 677# CONFIG_TUN is not set
525# CONFIG_VETH is not set 678# CONFIG_VETH is not set
679# CONFIG_ARCNET is not set
526CONFIG_PHYLIB=y 680CONFIG_PHYLIB=y
527 681
528# 682#
@@ -542,21 +696,60 @@ CONFIG_ICPLUS_PHY=y
542# CONFIG_MDIO_BITBANG is not set 696# CONFIG_MDIO_BITBANG is not set
543CONFIG_NET_ETHERNET=y 697CONFIG_NET_ETHERNET=y
544CONFIG_MII=y 698CONFIG_MII=y
699# CONFIG_MACE is not set
700# CONFIG_BMAC is not set
701# CONFIG_HAPPYMEAL is not set
702# CONFIG_SUNGEM is not set
703# CONFIG_CASSINI is not set
704# CONFIG_NET_VENDOR_3COM is not set
705# CONFIG_NET_TULIP is not set
706# CONFIG_HP100 is not set
545# CONFIG_IBM_NEW_EMAC_ZMII is not set 707# CONFIG_IBM_NEW_EMAC_ZMII is not set
546# CONFIG_IBM_NEW_EMAC_RGMII is not set 708# CONFIG_IBM_NEW_EMAC_RGMII is not set
547# CONFIG_IBM_NEW_EMAC_TAH is not set 709# CONFIG_IBM_NEW_EMAC_TAH is not set
548# CONFIG_IBM_NEW_EMAC_EMAC4 is not set 710# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
711# CONFIG_NET_PCI is not set
549# CONFIG_B44 is not set 712# CONFIG_B44 is not set
550CONFIG_NETDEV_1000=y 713CONFIG_NETDEV_1000=y
551# CONFIG_E1000E_ENABLED is not set 714# CONFIG_ACENIC is not set
715# CONFIG_DL2K is not set
716# CONFIG_E1000 is not set
717# CONFIG_E1000E is not set
718# CONFIG_IP1000 is not set
719# CONFIG_IGB is not set
720# CONFIG_NS83820 is not set
721# CONFIG_HAMACHI is not set
722# CONFIG_YELLOWFIN is not set
723# CONFIG_R8169 is not set
724# CONFIG_SIS190 is not set
725# CONFIG_SKGE is not set
726# CONFIG_SKY2 is not set
727# CONFIG_VIA_VELOCITY is not set
728# CONFIG_TIGON3 is not set
729# CONFIG_BNX2 is not set
552CONFIG_GIANFAR=y 730CONFIG_GIANFAR=y
553# CONFIG_GFAR_NAPI is not set
554CONFIG_UCC_GETH=y 731CONFIG_UCC_GETH=y
555# CONFIG_UGETH_NAPI is not set
556# CONFIG_UGETH_MAGIC_PACKET is not set 732# CONFIG_UGETH_MAGIC_PACKET is not set
557# CONFIG_UGETH_FILTERING is not set 733# CONFIG_UGETH_FILTERING is not set
558# CONFIG_UGETH_TX_ON_DEMAND is not set 734# CONFIG_UGETH_TX_ON_DEMAND is not set
735# CONFIG_MV643XX_ETH is not set
736# CONFIG_QLA3XXX is not set
737# CONFIG_ATL1 is not set
738# CONFIG_ATL1E is not set
559CONFIG_NETDEV_10000=y 739CONFIG_NETDEV_10000=y
740# CONFIG_CHELSIO_T1 is not set
741# CONFIG_CHELSIO_T3 is not set
742# CONFIG_IXGBE is not set
743# CONFIG_IXGB is not set
744# CONFIG_S2IO is not set
745# CONFIG_MYRI10GE is not set
746# CONFIG_NETXEN_NIC is not set
747# CONFIG_NIU is not set
748# CONFIG_MLX4_CORE is not set
749# CONFIG_TEHUTI is not set
750# CONFIG_BNX2X is not set
751# CONFIG_SFC is not set
752# CONFIG_TR is not set
560 753
561# 754#
562# Wireless LAN 755# Wireless LAN
@@ -574,8 +767,11 @@ CONFIG_NETDEV_10000=y
574# CONFIG_USB_RTL8150 is not set 767# CONFIG_USB_RTL8150 is not set
575# CONFIG_USB_USBNET is not set 768# CONFIG_USB_USBNET is not set
576# CONFIG_WAN is not set 769# CONFIG_WAN is not set
770# CONFIG_FDDI is not set
771# CONFIG_HIPPI is not set
577# CONFIG_PPP is not set 772# CONFIG_PPP is not set
578# CONFIG_SLIP is not set 773# CONFIG_SLIP is not set
774# CONFIG_NET_FC is not set
579# CONFIG_NETCONSOLE is not set 775# CONFIG_NETCONSOLE is not set
580# CONFIG_NETPOLL is not set 776# CONFIG_NETPOLL is not set
581# CONFIG_NET_POLL_CONTROLLER is not set 777# CONFIG_NET_POLL_CONTROLLER is not set
@@ -619,12 +815,14 @@ CONFIG_INPUT=y
619# CONFIG_VT is not set 815# CONFIG_VT is not set
620CONFIG_DEVKMEM=y 816CONFIG_DEVKMEM=y
621# CONFIG_SERIAL_NONSTANDARD is not set 817# CONFIG_SERIAL_NONSTANDARD is not set
818# CONFIG_NOZOMI is not set
622 819
623# 820#
624# Serial drivers 821# Serial drivers
625# 822#
626CONFIG_SERIAL_8250=y 823CONFIG_SERIAL_8250=y
627CONFIG_SERIAL_8250_CONSOLE=y 824CONFIG_SERIAL_8250_CONSOLE=y
825CONFIG_SERIAL_8250_PCI=y
628CONFIG_SERIAL_8250_NR_UARTS=4 826CONFIG_SERIAL_8250_NR_UARTS=4
629CONFIG_SERIAL_8250_RUNTIME_UARTS=4 827CONFIG_SERIAL_8250_RUNTIME_UARTS=4
630# CONFIG_SERIAL_8250_EXTENDED is not set 828# CONFIG_SERIAL_8250_EXTENDED is not set
@@ -635,43 +833,95 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=4
635# CONFIG_SERIAL_UARTLITE is not set 833# CONFIG_SERIAL_UARTLITE is not set
636CONFIG_SERIAL_CORE=y 834CONFIG_SERIAL_CORE=y
637CONFIG_SERIAL_CORE_CONSOLE=y 835CONFIG_SERIAL_CORE_CONSOLE=y
836# CONFIG_SERIAL_PMACZILOG is not set
837# CONFIG_SERIAL_JSM is not set
638# CONFIG_SERIAL_OF_PLATFORM is not set 838# CONFIG_SERIAL_OF_PLATFORM is not set
639# CONFIG_SERIAL_QE is not set 839# CONFIG_SERIAL_QE is not set
640CONFIG_UNIX98_PTYS=y 840CONFIG_UNIX98_PTYS=y
641CONFIG_LEGACY_PTYS=y 841CONFIG_LEGACY_PTYS=y
642CONFIG_LEGACY_PTY_COUNT=256 842CONFIG_LEGACY_PTY_COUNT=256
843# CONFIG_BRIQ_PANEL is not set
844# CONFIG_HVC_RTAS is not set
643# CONFIG_IPMI_HANDLER is not set 845# CONFIG_IPMI_HANDLER is not set
644# CONFIG_HW_RANDOM is not set 846CONFIG_HW_RANDOM=y
645# CONFIG_NVRAM is not set 847# CONFIG_NVRAM is not set
646CONFIG_GEN_RTC=y 848CONFIG_GEN_RTC=y
647# CONFIG_GEN_RTC_X is not set 849# CONFIG_GEN_RTC_X is not set
648# CONFIG_R3964 is not set 850# CONFIG_R3964 is not set
851# CONFIG_APPLICOM is not set
649# CONFIG_RAW_DRIVER is not set 852# CONFIG_RAW_DRIVER is not set
650# CONFIG_TCG_TPM is not set 853# CONFIG_TCG_TPM is not set
854CONFIG_DEVPORT=y
651CONFIG_I2C=y 855CONFIG_I2C=y
652CONFIG_I2C_BOARDINFO=y 856CONFIG_I2C_BOARDINFO=y
653CONFIG_I2C_CHARDEV=y 857CONFIG_I2C_CHARDEV=y
858CONFIG_I2C_HELPER_AUTO=y
654 859
655# 860#
656# I2C Hardware Bus support 861# I2C Hardware Bus support
657# 862#
863
864#
865# PC SMBus host controller drivers
866#
867# CONFIG_I2C_ALI1535 is not set
868# CONFIG_I2C_ALI1563 is not set
869# CONFIG_I2C_ALI15X3 is not set
870# CONFIG_I2C_AMD756 is not set
871# CONFIG_I2C_AMD8111 is not set
872# CONFIG_I2C_I801 is not set
873# CONFIG_I2C_ISCH is not set
874# CONFIG_I2C_PIIX4 is not set
875# CONFIG_I2C_NFORCE2 is not set
876# CONFIG_I2C_SIS5595 is not set
877# CONFIG_I2C_SIS630 is not set
878# CONFIG_I2C_SIS96X is not set
879# CONFIG_I2C_VIA is not set
880# CONFIG_I2C_VIAPRO is not set
881
882#
883# Mac SMBus host controller drivers
884#
885# CONFIG_I2C_HYDRA is not set
886CONFIG_I2C_POWERMAC=y
887
888#
889# I2C system bus drivers (mostly embedded / system-on-chip)
890#
891# CONFIG_I2C_GPIO is not set
658CONFIG_I2C_MPC=y 892CONFIG_I2C_MPC=y
659# CONFIG_I2C_OCORES is not set 893# CONFIG_I2C_OCORES is not set
660# CONFIG_I2C_PARPORT_LIGHT is not set
661# CONFIG_I2C_SIMTEC is not set 894# CONFIG_I2C_SIMTEC is not set
895
896#
897# External I2C/SMBus adapter drivers
898#
899# CONFIG_I2C_PARPORT_LIGHT is not set
662# CONFIG_I2C_TAOS_EVM is not set 900# CONFIG_I2C_TAOS_EVM is not set
663# CONFIG_I2C_STUB is not set
664# CONFIG_I2C_TINY_USB is not set 901# CONFIG_I2C_TINY_USB is not set
902
903#
904# Graphics adapter I2C/DDC channel drivers
905#
906# CONFIG_I2C_VOODOO3 is not set
907
908#
909# Other I2C/SMBus bus drivers
910#
665# CONFIG_I2C_PCA_PLATFORM is not set 911# CONFIG_I2C_PCA_PLATFORM is not set
912# CONFIG_I2C_STUB is not set
666 913
667# 914#
668# Miscellaneous I2C Chip support 915# Miscellaneous I2C Chip support
669# 916#
670# CONFIG_DS1682 is not set 917# CONFIG_DS1682 is not set
918# CONFIG_AT24 is not set
671# CONFIG_SENSORS_EEPROM is not set 919# CONFIG_SENSORS_EEPROM is not set
672# CONFIG_SENSORS_PCF8574 is not set 920# CONFIG_SENSORS_PCF8574 is not set
673# CONFIG_PCF8575 is not set 921# CONFIG_PCF8575 is not set
922# CONFIG_SENSORS_PCA9539 is not set
674# CONFIG_SENSORS_PCF8591 is not set 923# CONFIG_SENSORS_PCF8591 is not set
924# CONFIG_TPS65010 is not set
675# CONFIG_SENSORS_MAX6875 is not set 925# CONFIG_SENSORS_MAX6875 is not set
676# CONFIG_SENSORS_TSL2550 is not set 926# CONFIG_SENSORS_TSL2550 is not set
677# CONFIG_I2C_DEBUG_CORE is not set 927# CONFIG_I2C_DEBUG_CORE is not set
@@ -679,10 +929,31 @@ CONFIG_I2C_MPC=y
679# CONFIG_I2C_DEBUG_BUS is not set 929# CONFIG_I2C_DEBUG_BUS is not set
680# CONFIG_I2C_DEBUG_CHIP is not set 930# CONFIG_I2C_DEBUG_CHIP is not set
681# CONFIG_SPI is not set 931# CONFIG_SPI is not set
932CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
933CONFIG_ARCH_REQUIRE_GPIOLIB=y
934CONFIG_GPIOLIB=y
935# CONFIG_GPIO_SYSFS is not set
936
937#
938# I2C GPIO expanders:
939#
940# CONFIG_GPIO_MAX732X is not set
941# CONFIG_GPIO_PCA953X is not set
942# CONFIG_GPIO_PCF857X is not set
943
944#
945# PCI GPIO expanders:
946#
947# CONFIG_GPIO_BT8XX is not set
948
949#
950# SPI GPIO expanders:
951#
682# CONFIG_W1 is not set 952# CONFIG_W1 is not set
683# CONFIG_POWER_SUPPLY is not set 953# CONFIG_POWER_SUPPLY is not set
684CONFIG_HWMON=y 954CONFIG_HWMON=y
685# CONFIG_HWMON_VID is not set 955# CONFIG_HWMON_VID is not set
956# CONFIG_SENSORS_AD7414 is not set
686# CONFIG_SENSORS_AD7418 is not set 957# CONFIG_SENSORS_AD7418 is not set
687# CONFIG_SENSORS_ADM1021 is not set 958# CONFIG_SENSORS_ADM1021 is not set
688# CONFIG_SENSORS_ADM1025 is not set 959# CONFIG_SENSORS_ADM1025 is not set
@@ -692,8 +963,10 @@ CONFIG_HWMON=y
692# CONFIG_SENSORS_ADM9240 is not set 963# CONFIG_SENSORS_ADM9240 is not set
693# CONFIG_SENSORS_ADT7470 is not set 964# CONFIG_SENSORS_ADT7470 is not set
694# CONFIG_SENSORS_ADT7473 is not set 965# CONFIG_SENSORS_ADT7473 is not set
966# CONFIG_SENSORS_AMS is not set
695# CONFIG_SENSORS_ATXP1 is not set 967# CONFIG_SENSORS_ATXP1 is not set
696# CONFIG_SENSORS_DS1621 is not set 968# CONFIG_SENSORS_DS1621 is not set
969# CONFIG_SENSORS_I5K_AMB is not set
697# CONFIG_SENSORS_F71805F is not set 970# CONFIG_SENSORS_F71805F is not set
698# CONFIG_SENSORS_F71882FG is not set 971# CONFIG_SENSORS_F71882FG is not set
699# CONFIG_SENSORS_F75375S is not set 972# CONFIG_SENSORS_F75375S is not set
@@ -715,13 +988,16 @@ CONFIG_HWMON=y
715# CONFIG_SENSORS_MAX6650 is not set 988# CONFIG_SENSORS_MAX6650 is not set
716# CONFIG_SENSORS_PC87360 is not set 989# CONFIG_SENSORS_PC87360 is not set
717# CONFIG_SENSORS_PC87427 is not set 990# CONFIG_SENSORS_PC87427 is not set
991# CONFIG_SENSORS_SIS5595 is not set
718# CONFIG_SENSORS_DME1737 is not set 992# CONFIG_SENSORS_DME1737 is not set
719# CONFIG_SENSORS_SMSC47M1 is not set 993# CONFIG_SENSORS_SMSC47M1 is not set
720# CONFIG_SENSORS_SMSC47M192 is not set 994# CONFIG_SENSORS_SMSC47M192 is not set
721# CONFIG_SENSORS_SMSC47B397 is not set 995# CONFIG_SENSORS_SMSC47B397 is not set
722# CONFIG_SENSORS_ADS7828 is not set 996# CONFIG_SENSORS_ADS7828 is not set
723# CONFIG_SENSORS_THMC50 is not set 997# CONFIG_SENSORS_THMC50 is not set
998# CONFIG_SENSORS_VIA686A is not set
724# CONFIG_SENSORS_VT1211 is not set 999# CONFIG_SENSORS_VT1211 is not set
1000# CONFIG_SENSORS_VT8231 is not set
725# CONFIG_SENSORS_W83781D is not set 1001# CONFIG_SENSORS_W83781D is not set
726# CONFIG_SENSORS_W83791D is not set 1002# CONFIG_SENSORS_W83791D is not set
727# CONFIG_SENSORS_W83792D is not set 1003# CONFIG_SENSORS_W83792D is not set
@@ -732,6 +1008,7 @@ CONFIG_HWMON=y
732# CONFIG_SENSORS_W83627EHF is not set 1008# CONFIG_SENSORS_W83627EHF is not set
733# CONFIG_HWMON_DEBUG_CHIP is not set 1009# CONFIG_HWMON_DEBUG_CHIP is not set
734# CONFIG_THERMAL is not set 1010# CONFIG_THERMAL is not set
1011# CONFIG_THERMAL_HWMON is not set
735CONFIG_WATCHDOG=y 1012CONFIG_WATCHDOG=y
736# CONFIG_WATCHDOG_NOWAYOUT is not set 1013# CONFIG_WATCHDOG_NOWAYOUT is not set
737 1014
@@ -739,7 +1016,15 @@ CONFIG_WATCHDOG=y
739# Watchdog Device Drivers 1016# Watchdog Device Drivers
740# 1017#
741# CONFIG_SOFT_WATCHDOG is not set 1018# CONFIG_SOFT_WATCHDOG is not set
742CONFIG_83xx_WDT=y 1019# CONFIG_ALIM7101_WDT is not set
1020# CONFIG_8xxx_WDT is not set
1021# CONFIG_WATCHDOG_RTAS is not set
1022
1023#
1024# PCI-based Watchdog Cards
1025#
1026# CONFIG_PCIPCWATCHDOG is not set
1027# CONFIG_WDTPCI is not set
743 1028
744# 1029#
745# USB-based Watchdog Cards 1030# USB-based Watchdog Cards
@@ -755,8 +1040,10 @@ CONFIG_SSB_POSSIBLE=y
755# 1040#
756# Multifunction device drivers 1041# Multifunction device drivers
757# 1042#
1043# CONFIG_MFD_CORE is not set
758# CONFIG_MFD_SM501 is not set 1044# CONFIG_MFD_SM501 is not set
759# CONFIG_HTC_PASIC3 is not set 1045# CONFIG_HTC_PASIC3 is not set
1046# CONFIG_MFD_TMIO is not set
760 1047
761# 1048#
762# Multimedia devices 1049# Multimedia devices
@@ -778,6 +1065,8 @@ CONFIG_DAB=y
778# 1065#
779# Graphics support 1066# Graphics support
780# 1067#
1068# CONFIG_AGP is not set
1069# CONFIG_DRM is not set
781# CONFIG_VGASTATE is not set 1070# CONFIG_VGASTATE is not set
782CONFIG_VIDEO_OUTPUT_CONTROL=m 1071CONFIG_VIDEO_OUTPUT_CONTROL=m
783# CONFIG_FB is not set 1072# CONFIG_FB is not set
@@ -787,10 +1076,6 @@ CONFIG_VIDEO_OUTPUT_CONTROL=m
787# Display device support 1076# Display device support
788# 1077#
789# CONFIG_DISPLAY_SUPPORT is not set 1078# CONFIG_DISPLAY_SUPPORT is not set
790
791#
792# Sound
793#
794# CONFIG_SOUND is not set 1079# CONFIG_SOUND is not set
795CONFIG_HID_SUPPORT=y 1080CONFIG_HID_SUPPORT=y
796CONFIG_HID=y 1081CONFIG_HID=y
@@ -806,7 +1091,7 @@ CONFIG_USB_HID=y
806# CONFIG_USB_HIDDEV is not set 1091# CONFIG_USB_HIDDEV is not set
807CONFIG_USB_SUPPORT=y 1092CONFIG_USB_SUPPORT=y
808CONFIG_USB_ARCH_HAS_HCD=y 1093CONFIG_USB_ARCH_HAS_HCD=y
809# CONFIG_USB_ARCH_HAS_OHCI is not set 1094CONFIG_USB_ARCH_HAS_OHCI=y
810CONFIG_USB_ARCH_HAS_EHCI=y 1095CONFIG_USB_ARCH_HAS_EHCI=y
811CONFIG_USB=y 1096CONFIG_USB=y
812# CONFIG_USB_DEBUG is not set 1097# CONFIG_USB_DEBUG is not set
@@ -821,6 +1106,7 @@ CONFIG_USB_DEVICE_CLASS=y
821# CONFIG_USB_OTG is not set 1106# CONFIG_USB_OTG is not set
822# CONFIG_USB_OTG_WHITELIST is not set 1107# CONFIG_USB_OTG_WHITELIST is not set
823# CONFIG_USB_OTG_BLACKLIST_HUB is not set 1108# CONFIG_USB_OTG_BLACKLIST_HUB is not set
1109CONFIG_USB_MON=y
824 1110
825# 1111#
826# USB Host Controller Drivers 1112# USB Host Controller Drivers
@@ -833,6 +1119,8 @@ CONFIG_USB_EHCI_FSL=y
833CONFIG_USB_EHCI_HCD_PPC_OF=y 1119CONFIG_USB_EHCI_HCD_PPC_OF=y
834# CONFIG_USB_ISP116X_HCD is not set 1120# CONFIG_USB_ISP116X_HCD is not set
835# CONFIG_USB_ISP1760_HCD is not set 1121# CONFIG_USB_ISP1760_HCD is not set
1122# CONFIG_USB_OHCI_HCD is not set
1123# CONFIG_USB_UHCI_HCD is not set
836# CONFIG_USB_SL811_HCD is not set 1124# CONFIG_USB_SL811_HCD is not set
837# CONFIG_USB_R8A66597_HCD is not set 1125# CONFIG_USB_R8A66597_HCD is not set
838 1126
@@ -858,7 +1146,6 @@ CONFIG_USB_EHCI_HCD_PPC_OF=y
858# 1146#
859# CONFIG_USB_MDC800 is not set 1147# CONFIG_USB_MDC800 is not set
860# CONFIG_USB_MICROTEK is not set 1148# CONFIG_USB_MICROTEK is not set
861CONFIG_USB_MON=y
862 1149
863# 1150#
864# USB port drivers 1151# USB port drivers
@@ -871,7 +1158,6 @@ CONFIG_USB_MON=y
871# CONFIG_USB_EMI62 is not set 1158# CONFIG_USB_EMI62 is not set
872# CONFIG_USB_EMI26 is not set 1159# CONFIG_USB_EMI26 is not set
873# CONFIG_USB_ADUTUX is not set 1160# CONFIG_USB_ADUTUX is not set
874# CONFIG_USB_AUERSWALD is not set
875# CONFIG_USB_RIO500 is not set 1161# CONFIG_USB_RIO500 is not set
876# CONFIG_USB_LEGOTOWER is not set 1162# CONFIG_USB_LEGOTOWER is not set
877# CONFIG_USB_LCD is not set 1163# CONFIG_USB_LCD is not set
@@ -893,6 +1179,7 @@ CONFIG_USB_MON=y
893# CONFIG_MEMSTICK is not set 1179# CONFIG_MEMSTICK is not set
894# CONFIG_NEW_LEDS is not set 1180# CONFIG_NEW_LEDS is not set
895# CONFIG_ACCESSIBILITY is not set 1181# CONFIG_ACCESSIBILITY is not set
1182# CONFIG_INFINIBAND is not set
896# CONFIG_EDAC is not set 1183# CONFIG_EDAC is not set
897# CONFIG_RTC_CLASS is not set 1184# CONFIG_RTC_CLASS is not set
898# CONFIG_DMADEVICES is not set 1185# CONFIG_DMADEVICES is not set
@@ -963,6 +1250,7 @@ CONFIG_TMPFS=y
963# CONFIG_CRAMFS is not set 1250# CONFIG_CRAMFS is not set
964# CONFIG_VXFS_FS is not set 1251# CONFIG_VXFS_FS is not set
965# CONFIG_MINIX_FS is not set 1252# CONFIG_MINIX_FS is not set
1253# CONFIG_OMFS_FS is not set
966# CONFIG_HPFS_FS is not set 1254# CONFIG_HPFS_FS is not set
967# CONFIG_QNX4FS_FS is not set 1255# CONFIG_QNX4FS_FS is not set
968# CONFIG_ROMFS_FS is not set 1256# CONFIG_ROMFS_FS is not set
@@ -973,14 +1261,13 @@ CONFIG_NFS_FS=y
973CONFIG_NFS_V3=y 1261CONFIG_NFS_V3=y
974# CONFIG_NFS_V3_ACL is not set 1262# CONFIG_NFS_V3_ACL is not set
975CONFIG_NFS_V4=y 1263CONFIG_NFS_V4=y
976# CONFIG_NFSD is not set
977CONFIG_ROOT_NFS=y 1264CONFIG_ROOT_NFS=y
1265# CONFIG_NFSD is not set
978CONFIG_LOCKD=y 1266CONFIG_LOCKD=y
979CONFIG_LOCKD_V4=y 1267CONFIG_LOCKD_V4=y
980CONFIG_NFS_COMMON=y 1268CONFIG_NFS_COMMON=y
981CONFIG_SUNRPC=y 1269CONFIG_SUNRPC=y
982CONFIG_SUNRPC_GSS=y 1270CONFIG_SUNRPC_GSS=y
983# CONFIG_SUNRPC_BIND34 is not set
984CONFIG_RPCSEC_GSS_KRB5=y 1271CONFIG_RPCSEC_GSS_KRB5=y
985# CONFIG_RPCSEC_GSS_SPKM3 is not set 1272# CONFIG_RPCSEC_GSS_SPKM3 is not set
986# CONFIG_SMB_FS is not set 1273# CONFIG_SMB_FS is not set
@@ -1014,6 +1301,7 @@ CONFIG_MSDOS_PARTITION=y
1014# CONFIG_DLM is not set 1301# CONFIG_DLM is not set
1015CONFIG_UCC_FAST=y 1302CONFIG_UCC_FAST=y
1016CONFIG_UCC=y 1303CONFIG_UCC=y
1304CONFIG_QE_GPIO=y
1017 1305
1018# 1306#
1019# Library routines 1307# Library routines
@@ -1022,6 +1310,7 @@ CONFIG_BITREVERSE=y
1022# CONFIG_GENERIC_FIND_FIRST_BIT is not set 1310# CONFIG_GENERIC_FIND_FIRST_BIT is not set
1023# CONFIG_CRC_CCITT is not set 1311# CONFIG_CRC_CCITT is not set
1024# CONFIG_CRC16 is not set 1312# CONFIG_CRC16 is not set
1313CONFIG_CRC_T10DIF=y
1025# CONFIG_CRC_ITU_T is not set 1314# CONFIG_CRC_ITU_T is not set
1026CONFIG_CRC32=y 1315CONFIG_CRC32=y
1027# CONFIG_CRC7 is not set 1316# CONFIG_CRC7 is not set
@@ -1045,8 +1334,18 @@ CONFIG_FRAME_WARN=1024
1045# CONFIG_HEADERS_CHECK is not set 1334# CONFIG_HEADERS_CHECK is not set
1046# CONFIG_DEBUG_KERNEL is not set 1335# CONFIG_DEBUG_KERNEL is not set
1047# CONFIG_DEBUG_BUGVERBOSE is not set 1336# CONFIG_DEBUG_BUGVERBOSE is not set
1337# CONFIG_DEBUG_MEMORY_INIT is not set
1338# CONFIG_LATENCYTOP is not set
1339CONFIG_SYSCTL_SYSCALL_CHECK=y
1340CONFIG_HAVE_FTRACE=y
1341CONFIG_HAVE_DYNAMIC_FTRACE=y
1342# CONFIG_FTRACE is not set
1343# CONFIG_SCHED_TRACER is not set
1344# CONFIG_CONTEXT_SWITCH_TRACER is not set
1048# CONFIG_SAMPLES is not set 1345# CONFIG_SAMPLES is not set
1346CONFIG_HAVE_ARCH_KGDB=y
1049# CONFIG_IRQSTACKS is not set 1347# CONFIG_IRQSTACKS is not set
1348# CONFIG_BOOTX_TEXT is not set
1050# CONFIG_PPC_EARLY_DEBUG is not set 1349# CONFIG_PPC_EARLY_DEBUG is not set
1051 1350
1052# 1351#
@@ -1061,12 +1360,14 @@ CONFIG_CRYPTO=y
1061# Crypto core or helper 1360# Crypto core or helper
1062# 1361#
1063CONFIG_CRYPTO_ALGAPI=y 1362CONFIG_CRYPTO_ALGAPI=y
1363CONFIG_CRYPTO_AEAD=y
1064CONFIG_CRYPTO_BLKCIPHER=y 1364CONFIG_CRYPTO_BLKCIPHER=y
1365CONFIG_CRYPTO_HASH=y
1065CONFIG_CRYPTO_MANAGER=y 1366CONFIG_CRYPTO_MANAGER=y
1066# CONFIG_CRYPTO_GF128MUL is not set 1367# CONFIG_CRYPTO_GF128MUL is not set
1067# CONFIG_CRYPTO_NULL is not set 1368# CONFIG_CRYPTO_NULL is not set
1068# CONFIG_CRYPTO_CRYPTD is not set 1369# CONFIG_CRYPTO_CRYPTD is not set
1069# CONFIG_CRYPTO_AUTHENC is not set 1370CONFIG_CRYPTO_AUTHENC=y
1070# CONFIG_CRYPTO_TEST is not set 1371# CONFIG_CRYPTO_TEST is not set
1071 1372
1072# 1373#
@@ -1100,6 +1401,10 @@ CONFIG_CRYPTO_PCBC=m
1100# CONFIG_CRYPTO_MD4 is not set 1401# CONFIG_CRYPTO_MD4 is not set
1101CONFIG_CRYPTO_MD5=y 1402CONFIG_CRYPTO_MD5=y
1102# CONFIG_CRYPTO_MICHAEL_MIC is not set 1403# CONFIG_CRYPTO_MICHAEL_MIC is not set
1404# CONFIG_CRYPTO_RMD128 is not set
1405# CONFIG_CRYPTO_RMD160 is not set
1406# CONFIG_CRYPTO_RMD256 is not set
1407# CONFIG_CRYPTO_RMD320 is not set
1103# CONFIG_CRYPTO_SHA1 is not set 1408# CONFIG_CRYPTO_SHA1 is not set
1104# CONFIG_CRYPTO_SHA256 is not set 1409# CONFIG_CRYPTO_SHA256 is not set
1105# CONFIG_CRYPTO_SHA512 is not set 1410# CONFIG_CRYPTO_SHA512 is not set
@@ -1131,6 +1436,8 @@ CONFIG_CRYPTO_DES=y
1131# CONFIG_CRYPTO_DEFLATE is not set 1436# CONFIG_CRYPTO_DEFLATE is not set
1132# CONFIG_CRYPTO_LZO is not set 1437# CONFIG_CRYPTO_LZO is not set
1133CONFIG_CRYPTO_HW=y 1438CONFIG_CRYPTO_HW=y
1439# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1440CONFIG_CRYPTO_DEV_TALITOS=y
1134# CONFIG_PPC_CLOCK is not set 1441# CONFIG_PPC_CLOCK is not set
1135CONFIG_PPC_LIB_RHEAP=y 1442CONFIG_PPC_LIB_RHEAP=y
1136# CONFIG_VIRTUALIZATION is not set 1443# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig
index fa0170504b88..f0a13bebf50c 100644
--- a/arch/powerpc/configs/mpc85xx_defconfig
+++ b/arch/powerpc/configs/mpc85xx_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc5 3# Linux kernel version: 2.6.27-rc4
4# Mon Jun 9 09:03:46 2008 4# Thu Aug 21 07:15:20 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -15,6 +15,7 @@ CONFIG_PPC_85xx=y
15# CONFIG_44x is not set 15# CONFIG_44x is not set
16# CONFIG_E200 is not set 16# CONFIG_E200 is not set
17CONFIG_E500=y 17CONFIG_E500=y
18# CONFIG_PPC_E500MC is not set
18CONFIG_BOOKE=y 19CONFIG_BOOKE=y
19CONFIG_FSL_BOOKE=y 20CONFIG_FSL_BOOKE=y
20CONFIG_FSL_EMB_PERFMON=y 21CONFIG_FSL_EMB_PERFMON=y
@@ -33,12 +34,14 @@ CONFIG_GENERIC_HARDIRQS=y
33# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set 34# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
34CONFIG_IRQ_PER_CPU=y 35CONFIG_IRQ_PER_CPU=y
35CONFIG_STACKTRACE_SUPPORT=y 36CONFIG_STACKTRACE_SUPPORT=y
37CONFIG_HAVE_LATENCYTOP_SUPPORT=y
36CONFIG_LOCKDEP_SUPPORT=y 38CONFIG_LOCKDEP_SUPPORT=y
37CONFIG_RWSEM_XCHGADD_ALGORITHM=y 39CONFIG_RWSEM_XCHGADD_ALGORITHM=y
38CONFIG_ARCH_HAS_ILOG2_U32=y 40CONFIG_ARCH_HAS_ILOG2_U32=y
39CONFIG_GENERIC_HWEIGHT=y 41CONFIG_GENERIC_HWEIGHT=y
40CONFIG_GENERIC_CALIBRATE_DELAY=y 42CONFIG_GENERIC_CALIBRATE_DELAY=y
41CONFIG_GENERIC_FIND_NEXT_BIT=y 43CONFIG_GENERIC_FIND_NEXT_BIT=y
44CONFIG_GENERIC_GPIO=y
42# CONFIG_ARCH_NO_VIRT_TO_BUS is not set 45# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
43CONFIG_PPC=y 46CONFIG_PPC=y
44CONFIG_EARLY_PRINTK=y 47CONFIG_EARLY_PRINTK=y
@@ -92,7 +95,6 @@ CONFIG_INITRAMFS_SOURCE=""
92CONFIG_SYSCTL=y 95CONFIG_SYSCTL=y
93CONFIG_EMBEDDED=y 96CONFIG_EMBEDDED=y
94CONFIG_SYSCTL_SYSCALL=y 97CONFIG_SYSCTL_SYSCALL=y
95CONFIG_SYSCTL_SYSCALL_CHECK=y
96CONFIG_KALLSYMS=y 98CONFIG_KALLSYMS=y
97CONFIG_KALLSYMS_ALL=y 99CONFIG_KALLSYMS_ALL=y
98CONFIG_KALLSYMS_EXTRA_PASS=y 100CONFIG_KALLSYMS_EXTRA_PASS=y
@@ -118,10 +120,16 @@ CONFIG_SLUB=y
118# CONFIG_MARKERS is not set 120# CONFIG_MARKERS is not set
119CONFIG_HAVE_OPROFILE=y 121CONFIG_HAVE_OPROFILE=y
120# CONFIG_KPROBES is not set 122# CONFIG_KPROBES is not set
123CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
124CONFIG_HAVE_IOREMAP_PROT=y
121CONFIG_HAVE_KPROBES=y 125CONFIG_HAVE_KPROBES=y
122CONFIG_HAVE_KRETPROBES=y 126CONFIG_HAVE_KRETPROBES=y
127CONFIG_HAVE_ARCH_TRACEHOOK=y
123# CONFIG_HAVE_DMA_ATTRS is not set 128# CONFIG_HAVE_DMA_ATTRS is not set
129# CONFIG_USE_GENERIC_SMP_HELPERS is not set
130CONFIG_HAVE_CLK=y
124CONFIG_PROC_PAGE_MONITOR=y 131CONFIG_PROC_PAGE_MONITOR=y
132# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
125CONFIG_SLABINFO=y 133CONFIG_SLABINFO=y
126CONFIG_RT_MUTEXES=y 134CONFIG_RT_MUTEXES=y
127# CONFIG_TINY_SHMEM is not set 135# CONFIG_TINY_SHMEM is not set
@@ -138,6 +146,7 @@ CONFIG_LBD=y
138# CONFIG_BLK_DEV_IO_TRACE is not set 146# CONFIG_BLK_DEV_IO_TRACE is not set
139# CONFIG_LSF is not set 147# CONFIG_LSF is not set
140# CONFIG_BLK_DEV_BSG is not set 148# CONFIG_BLK_DEV_BSG is not set
149# CONFIG_BLK_DEV_INTEGRITY is not set
141 150
142# 151#
143# IO Schedulers 152# IO Schedulers
@@ -156,8 +165,6 @@ CONFIG_CLASSIC_RCU=y
156# 165#
157# Platform support 166# Platform support
158# 167#
159# CONFIG_PPC_MPC512x is not set
160# CONFIG_PPC_MPC5121 is not set
161# CONFIG_PPC_CELL is not set 168# CONFIG_PPC_CELL is not set
162# CONFIG_PPC_CELL_NATIVE is not set 169# CONFIG_PPC_CELL_NATIVE is not set
163# CONFIG_PQ2ADS is not set 170# CONFIG_PQ2ADS is not set
@@ -166,11 +173,13 @@ CONFIG_MPC8540_ADS=y
166CONFIG_MPC8560_ADS=y 173CONFIG_MPC8560_ADS=y
167CONFIG_MPC85xx_CDS=y 174CONFIG_MPC85xx_CDS=y
168CONFIG_MPC85xx_MDS=y 175CONFIG_MPC85xx_MDS=y
176CONFIG_MPC8536_DS=y
169CONFIG_MPC85xx_DS=y 177CONFIG_MPC85xx_DS=y
170CONFIG_KSI8560=y 178CONFIG_KSI8560=y
171# CONFIG_STX_GP3 is not set 179# CONFIG_STX_GP3 is not set
172CONFIG_TQM8540=y 180CONFIG_TQM8540=y
173CONFIG_TQM8541=y 181CONFIG_TQM8541=y
182CONFIG_TQM8548=y
174CONFIG_TQM8555=y 183CONFIG_TQM8555=y
175CONFIG_TQM8560=y 184CONFIG_TQM8560=y
176CONFIG_SBC8548=y 185CONFIG_SBC8548=y
@@ -189,7 +198,6 @@ CONFIG_PPC_I8259=y
189# CONFIG_CPU_FREQ is not set 198# CONFIG_CPU_FREQ is not set
190CONFIG_QUICC_ENGINE=y 199CONFIG_QUICC_ENGINE=y
191CONFIG_CPM2=y 200CONFIG_CPM2=y
192CONFIG_PPC_CPM_NEW_BINDING=y
193CONFIG_FSL_ULI1575=y 201CONFIG_FSL_ULI1575=y
194CONFIG_CPM=y 202CONFIG_CPM=y
195 203
@@ -206,7 +214,7 @@ CONFIG_HZ_250=y
206# CONFIG_HZ_300 is not set 214# CONFIG_HZ_300 is not set
207# CONFIG_HZ_1000 is not set 215# CONFIG_HZ_1000 is not set
208CONFIG_HZ=250 216CONFIG_HZ=250
209# CONFIG_SCHED_HRTICK is not set 217CONFIG_SCHED_HRTICK=y
210CONFIG_PREEMPT_NONE=y 218CONFIG_PREEMPT_NONE=y
211# CONFIG_PREEMPT_VOLUNTARY is not set 219# CONFIG_PREEMPT_VOLUNTARY is not set
212# CONFIG_PREEMPT is not set 220# CONFIG_PREEMPT is not set
@@ -229,6 +237,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
229# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set 237# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
230CONFIG_PAGEFLAGS_EXTENDED=y 238CONFIG_PAGEFLAGS_EXTENDED=y
231CONFIG_SPLIT_PTLOCK_CPUS=4 239CONFIG_SPLIT_PTLOCK_CPUS=4
240CONFIG_MIGRATION=y
232# CONFIG_RESOURCES_64BIT is not set 241# CONFIG_RESOURCES_64BIT is not set
233CONFIG_ZONE_DMA_FLAG=1 242CONFIG_ZONE_DMA_FLAG=1
234CONFIG_BOUNCE=y 243CONFIG_BOUNCE=y
@@ -236,6 +245,7 @@ CONFIG_VIRT_TO_BUS=y
236CONFIG_FORCE_MAX_ZONEORDER=11 245CONFIG_FORCE_MAX_ZONEORDER=11
237CONFIG_PROC_DEVICETREE=y 246CONFIG_PROC_DEVICETREE=y
238# CONFIG_CMDLINE_BOOL is not set 247# CONFIG_CMDLINE_BOOL is not set
248CONFIG_EXTRA_TARGETS=""
239# CONFIG_PM is not set 249# CONFIG_PM is not set
240CONFIG_SECCOMP=y 250CONFIG_SECCOMP=y
241CONFIG_ISA_DMA_API=y 251CONFIG_ISA_DMA_API=y
@@ -248,6 +258,7 @@ CONFIG_GENERIC_ISA_DMA=y
248CONFIG_PPC_INDIRECT_PCI=y 258CONFIG_PPC_INDIRECT_PCI=y
249CONFIG_FSL_SOC=y 259CONFIG_FSL_SOC=y
250CONFIG_FSL_PCI=y 260CONFIG_FSL_PCI=y
261CONFIG_PPC_PCI_CHOICE=y
251CONFIG_PCI=y 262CONFIG_PCI=y
252CONFIG_PCI_DOMAINS=y 263CONFIG_PCI_DOMAINS=y
253CONFIG_PCI_SYSCALL=y 264CONFIG_PCI_SYSCALL=y
@@ -274,10 +285,6 @@ CONFIG_KERNEL_START=0xc0000000
274CONFIG_PHYSICAL_START=0x00000000 285CONFIG_PHYSICAL_START=0x00000000
275CONFIG_PHYSICAL_ALIGN=0x10000000 286CONFIG_PHYSICAL_ALIGN=0x10000000
276CONFIG_TASK_SIZE=0xc0000000 287CONFIG_TASK_SIZE=0xc0000000
277
278#
279# Networking
280#
281CONFIG_NET=y 288CONFIG_NET=y
282 289
283# 290#
@@ -403,12 +410,15 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
403CONFIG_STANDALONE=y 410CONFIG_STANDALONE=y
404CONFIG_PREVENT_FIRMWARE_BUILD=y 411CONFIG_PREVENT_FIRMWARE_BUILD=y
405CONFIG_FW_LOADER=y 412CONFIG_FW_LOADER=y
413CONFIG_FIRMWARE_IN_KERNEL=y
414CONFIG_EXTRA_FIRMWARE=""
406# CONFIG_DEBUG_DRIVER is not set 415# CONFIG_DEBUG_DRIVER is not set
407# CONFIG_DEBUG_DEVRES is not set 416# CONFIG_DEBUG_DEVRES is not set
408# CONFIG_SYS_HYPERVISOR is not set 417# CONFIG_SYS_HYPERVISOR is not set
409# CONFIG_CONNECTOR is not set 418# CONFIG_CONNECTOR is not set
410# CONFIG_MTD is not set 419# CONFIG_MTD is not set
411CONFIG_OF_DEVICE=y 420CONFIG_OF_DEVICE=y
421CONFIG_OF_GPIO=y
412CONFIG_OF_I2C=y 422CONFIG_OF_I2C=y
413# CONFIG_PARPORT is not set 423# CONFIG_PARPORT is not set
414CONFIG_BLK_DEV=y 424CONFIG_BLK_DEV=y
@@ -429,12 +439,14 @@ CONFIG_BLK_DEV_RAM_SIZE=131072
429# CONFIG_BLK_DEV_XIP is not set 439# CONFIG_BLK_DEV_XIP is not set
430# CONFIG_CDROM_PKTCDVD is not set 440# CONFIG_CDROM_PKTCDVD is not set
431# CONFIG_ATA_OVER_ETH is not set 441# CONFIG_ATA_OVER_ETH is not set
442# CONFIG_BLK_DEV_HD is not set
432CONFIG_MISC_DEVICES=y 443CONFIG_MISC_DEVICES=y
433# CONFIG_PHANTOM is not set 444# CONFIG_PHANTOM is not set
434# CONFIG_EEPROM_93CX6 is not set 445# CONFIG_EEPROM_93CX6 is not set
435# CONFIG_SGI_IOC4 is not set 446# CONFIG_SGI_IOC4 is not set
436# CONFIG_TIFM_CORE is not set 447# CONFIG_TIFM_CORE is not set
437# CONFIG_ENCLOSURE_SERVICES is not set 448# CONFIG_ENCLOSURE_SERVICES is not set
449# CONFIG_HP_ILO is not set
438CONFIG_HAVE_IDE=y 450CONFIG_HAVE_IDE=y
439# CONFIG_IDE is not set 451# CONFIG_IDE is not set
440 452
@@ -514,6 +526,7 @@ CONFIG_SCSI_LOWLEVEL=y
514# CONFIG_SCSI_NSP32 is not set 526# CONFIG_SCSI_NSP32 is not set
515# CONFIG_SCSI_DEBUG is not set 527# CONFIG_SCSI_DEBUG is not set
516# CONFIG_SCSI_SRP is not set 528# CONFIG_SCSI_SRP is not set
529# CONFIG_SCSI_DH is not set
517CONFIG_ATA=y 530CONFIG_ATA=y
518# CONFIG_ATA_NONSTANDARD is not set 531# CONFIG_ATA_NONSTANDARD is not set
519CONFIG_SATA_PMP=y 532CONFIG_SATA_PMP=y
@@ -581,12 +594,15 @@ CONFIG_PATA_ALI=y
581# 594#
582# IEEE 1394 (FireWire) support 595# IEEE 1394 (FireWire) support
583# 596#
597
598#
599# Enable only one of the two stacks, unless you know what you are doing
600#
584# CONFIG_FIREWIRE is not set 601# CONFIG_FIREWIRE is not set
585# CONFIG_IEEE1394 is not set 602# CONFIG_IEEE1394 is not set
586# CONFIG_I2O is not set 603# CONFIG_I2O is not set
587# CONFIG_MACINTOSH_DRIVERS is not set 604# CONFIG_MACINTOSH_DRIVERS is not set
588CONFIG_NETDEVICES=y 605CONFIG_NETDEVICES=y
589# CONFIG_NETDEVICES_MULTIQUEUE is not set
590CONFIG_DUMMY=y 606CONFIG_DUMMY=y
591# CONFIG_BONDING is not set 607# CONFIG_BONDING is not set
592# CONFIG_MACVLAN is not set 608# CONFIG_MACVLAN is not set
@@ -631,7 +647,6 @@ CONFIG_NETDEV_1000=y
631# CONFIG_DL2K is not set 647# CONFIG_DL2K is not set
632# CONFIG_E1000 is not set 648# CONFIG_E1000 is not set
633# CONFIG_E1000E is not set 649# CONFIG_E1000E is not set
634# CONFIG_E1000E_ENABLED is not set
635# CONFIG_IP1000 is not set 650# CONFIG_IP1000 is not set
636# CONFIG_IGB is not set 651# CONFIG_IGB is not set
637# CONFIG_NS83820 is not set 652# CONFIG_NS83820 is not set
@@ -645,10 +660,10 @@ CONFIG_NETDEV_1000=y
645# CONFIG_TIGON3 is not set 660# CONFIG_TIGON3 is not set
646# CONFIG_BNX2 is not set 661# CONFIG_BNX2 is not set
647CONFIG_GIANFAR=y 662CONFIG_GIANFAR=y
648CONFIG_GFAR_NAPI=y
649# CONFIG_UCC_GETH is not set 663# CONFIG_UCC_GETH is not set
650# CONFIG_QLA3XXX is not set 664# CONFIG_QLA3XXX is not set
651# CONFIG_ATL1 is not set 665# CONFIG_ATL1 is not set
666# CONFIG_ATL1E is not set
652CONFIG_NETDEV_10000=y 667CONFIG_NETDEV_10000=y
653# CONFIG_CHELSIO_T1 is not set 668# CONFIG_CHELSIO_T1 is not set
654# CONFIG_CHELSIO_T3 is not set 669# CONFIG_CHELSIO_T3 is not set
@@ -725,12 +740,14 @@ CONFIG_SERIO_SERPORT=y
725# CONFIG_SERIO_PCIPS2 is not set 740# CONFIG_SERIO_PCIPS2 is not set
726CONFIG_SERIO_LIBPS2=y 741CONFIG_SERIO_LIBPS2=y
727# CONFIG_SERIO_RAW is not set 742# CONFIG_SERIO_RAW is not set
743# CONFIG_SERIO_XILINX_XPS_PS2 is not set
728# CONFIG_GAMEPORT is not set 744# CONFIG_GAMEPORT is not set
729 745
730# 746#
731# Character devices 747# Character devices
732# 748#
733CONFIG_VT=y 749CONFIG_VT=y
750CONFIG_CONSOLE_TRANSLATIONS=y
734CONFIG_VT_CONSOLE=y 751CONFIG_VT_CONSOLE=y
735CONFIG_HW_CONSOLE=y 752CONFIG_HW_CONSOLE=y
736# CONFIG_VT_HW_CONSOLE_BINDING is not set 753# CONFIG_VT_HW_CONSOLE_BINDING is not set
@@ -776,44 +793,68 @@ CONFIG_DEVPORT=y
776CONFIG_I2C=y 793CONFIG_I2C=y
777CONFIG_I2C_BOARDINFO=y 794CONFIG_I2C_BOARDINFO=y
778# CONFIG_I2C_CHARDEV is not set 795# CONFIG_I2C_CHARDEV is not set
796CONFIG_I2C_HELPER_AUTO=y
779 797
780# 798#
781# I2C Hardware Bus support 799# I2C Hardware Bus support
782# 800#
801
802#
803# PC SMBus host controller drivers
804#
783# CONFIG_I2C_ALI1535 is not set 805# CONFIG_I2C_ALI1535 is not set
784# CONFIG_I2C_ALI1563 is not set 806# CONFIG_I2C_ALI1563 is not set
785# CONFIG_I2C_ALI15X3 is not set 807# CONFIG_I2C_ALI15X3 is not set
786# CONFIG_I2C_AMD756 is not set 808# CONFIG_I2C_AMD756 is not set
787# CONFIG_I2C_AMD8111 is not set 809# CONFIG_I2C_AMD8111 is not set
788# CONFIG_I2C_I801 is not set 810# CONFIG_I2C_I801 is not set
789# CONFIG_I2C_I810 is not set 811# CONFIG_I2C_ISCH is not set
790# CONFIG_I2C_PIIX4 is not set 812# CONFIG_I2C_PIIX4 is not set
791CONFIG_I2C_MPC=y
792# CONFIG_I2C_NFORCE2 is not set 813# CONFIG_I2C_NFORCE2 is not set
793# CONFIG_I2C_OCORES is not set
794# CONFIG_I2C_PARPORT_LIGHT is not set
795# CONFIG_I2C_PROSAVAGE is not set
796# CONFIG_I2C_SAVAGE4 is not set
797# CONFIG_I2C_SIMTEC is not set
798# CONFIG_I2C_SIS5595 is not set 814# CONFIG_I2C_SIS5595 is not set
799# CONFIG_I2C_SIS630 is not set 815# CONFIG_I2C_SIS630 is not set
800# CONFIG_I2C_SIS96X is not set 816# CONFIG_I2C_SIS96X is not set
801# CONFIG_I2C_TAOS_EVM is not set
802# CONFIG_I2C_STUB is not set
803# CONFIG_I2C_TINY_USB is not set
804# CONFIG_I2C_VIA is not set 817# CONFIG_I2C_VIA is not set
805# CONFIG_I2C_VIAPRO is not set 818# CONFIG_I2C_VIAPRO is not set
819
820#
821# I2C system bus drivers (mostly embedded / system-on-chip)
822#
823# CONFIG_I2C_CPM is not set
824# CONFIG_I2C_GPIO is not set
825CONFIG_I2C_MPC=y
826# CONFIG_I2C_OCORES is not set
827# CONFIG_I2C_SIMTEC is not set
828
829#
830# External I2C/SMBus adapter drivers
831#
832# CONFIG_I2C_PARPORT_LIGHT is not set
833# CONFIG_I2C_TAOS_EVM is not set
834# CONFIG_I2C_TINY_USB is not set
835
836#
837# Graphics adapter I2C/DDC channel drivers
838#
806# CONFIG_I2C_VOODOO3 is not set 839# CONFIG_I2C_VOODOO3 is not set
840
841#
842# Other I2C/SMBus bus drivers
843#
807# CONFIG_I2C_PCA_PLATFORM is not set 844# CONFIG_I2C_PCA_PLATFORM is not set
845# CONFIG_I2C_STUB is not set
808 846
809# 847#
810# Miscellaneous I2C Chip support 848# Miscellaneous I2C Chip support
811# 849#
812# CONFIG_DS1682 is not set 850# CONFIG_DS1682 is not set
851# CONFIG_AT24 is not set
813CONFIG_SENSORS_EEPROM=y 852CONFIG_SENSORS_EEPROM=y
814# CONFIG_SENSORS_PCF8574 is not set 853# CONFIG_SENSORS_PCF8574 is not set
815# CONFIG_PCF8575 is not set 854# CONFIG_PCF8575 is not set
855# CONFIG_SENSORS_PCA9539 is not set
816# CONFIG_SENSORS_PCF8591 is not set 856# CONFIG_SENSORS_PCF8591 is not set
857# CONFIG_TPS65010 is not set
817# CONFIG_SENSORS_MAX6875 is not set 858# CONFIG_SENSORS_MAX6875 is not set
818# CONFIG_SENSORS_TSL2550 is not set 859# CONFIG_SENSORS_TSL2550 is not set
819# CONFIG_I2C_DEBUG_CORE is not set 860# CONFIG_I2C_DEBUG_CORE is not set
@@ -821,10 +862,32 @@ CONFIG_SENSORS_EEPROM=y
821# CONFIG_I2C_DEBUG_BUS is not set 862# CONFIG_I2C_DEBUG_BUS is not set
822# CONFIG_I2C_DEBUG_CHIP is not set 863# CONFIG_I2C_DEBUG_CHIP is not set
823# CONFIG_SPI is not set 864# CONFIG_SPI is not set
865CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
866CONFIG_ARCH_REQUIRE_GPIOLIB=y
867CONFIG_GPIOLIB=y
868# CONFIG_DEBUG_GPIO is not set
869# CONFIG_GPIO_SYSFS is not set
870
871#
872# I2C GPIO expanders:
873#
874# CONFIG_GPIO_MAX732X is not set
875# CONFIG_GPIO_PCA953X is not set
876# CONFIG_GPIO_PCF857X is not set
877
878#
879# PCI GPIO expanders:
880#
881# CONFIG_GPIO_BT8XX is not set
882
883#
884# SPI GPIO expanders:
885#
824# CONFIG_W1 is not set 886# CONFIG_W1 is not set
825# CONFIG_POWER_SUPPLY is not set 887# CONFIG_POWER_SUPPLY is not set
826# CONFIG_HWMON is not set 888# CONFIG_HWMON is not set
827# CONFIG_THERMAL is not set 889# CONFIG_THERMAL is not set
890# CONFIG_THERMAL_HWMON is not set
828# CONFIG_WATCHDOG is not set 891# CONFIG_WATCHDOG is not set
829 892
830# 893#
@@ -836,8 +899,10 @@ CONFIG_SSB_POSSIBLE=y
836# 899#
837# Multifunction device drivers 900# Multifunction device drivers
838# 901#
902# CONFIG_MFD_CORE is not set
839# CONFIG_MFD_SM501 is not set 903# CONFIG_MFD_SM501 is not set
840# CONFIG_HTC_PASIC3 is not set 904# CONFIG_HTC_PASIC3 is not set
905# CONFIG_MFD_TMIO is not set
841 906
842# 907#
843# Multimedia devices 908# Multimedia devices
@@ -879,6 +944,7 @@ CONFIG_DVB_CAPTURE_DRIVERS=y
879# CONFIG_DVB_TTUSB_BUDGET is not set 944# CONFIG_DVB_TTUSB_BUDGET is not set
880# CONFIG_DVB_TTUSB_DEC is not set 945# CONFIG_DVB_TTUSB_DEC is not set
881# CONFIG_DVB_CINERGYT2 is not set 946# CONFIG_DVB_CINERGYT2 is not set
947# CONFIG_DVB_SIANO_SMS1XXX is not set
882 948
883# 949#
884# Supported FlexCopII (B2C2) Adapters 950# Supported FlexCopII (B2C2) Adapters
@@ -925,6 +991,7 @@ CONFIG_DVB_CAPTURE_DRIVERS=y
925# CONFIG_DVB_SP887X is not set 991# CONFIG_DVB_SP887X is not set
926# CONFIG_DVB_CX22700 is not set 992# CONFIG_DVB_CX22700 is not set
927# CONFIG_DVB_CX22702 is not set 993# CONFIG_DVB_CX22702 is not set
994# CONFIG_DVB_DRX397XD is not set
928# CONFIG_DVB_L64781 is not set 995# CONFIG_DVB_L64781 is not set
929# CONFIG_DVB_TDA1004X is not set 996# CONFIG_DVB_TDA1004X is not set
930# CONFIG_DVB_NXT6000 is not set 997# CONFIG_DVB_NXT6000 is not set
@@ -992,15 +1059,7 @@ CONFIG_VIDEO_OUTPUT_CONTROL=y
992CONFIG_VGA_CONSOLE=y 1059CONFIG_VGA_CONSOLE=y
993# CONFIG_VGACON_SOFT_SCROLLBACK is not set 1060# CONFIG_VGACON_SOFT_SCROLLBACK is not set
994CONFIG_DUMMY_CONSOLE=y 1061CONFIG_DUMMY_CONSOLE=y
995
996#
997# Sound
998#
999CONFIG_SOUND=y 1062CONFIG_SOUND=y
1000
1001#
1002# Advanced Linux Sound Architecture
1003#
1004CONFIG_SND=y 1063CONFIG_SND=y
1005CONFIG_SND_TIMER=y 1064CONFIG_SND_TIMER=y
1006CONFIG_SND_PCM=y 1065CONFIG_SND_PCM=y
@@ -1014,19 +1073,15 @@ CONFIG_SND_PCM_OSS_PLUGINS=y
1014CONFIG_SND_VERBOSE_PROCFS=y 1073CONFIG_SND_VERBOSE_PROCFS=y
1015# CONFIG_SND_VERBOSE_PRINTK is not set 1074# CONFIG_SND_VERBOSE_PRINTK is not set
1016# CONFIG_SND_DEBUG is not set 1075# CONFIG_SND_DEBUG is not set
1017 1076CONFIG_SND_VMASTER=y
1018#
1019# Generic devices
1020#
1021CONFIG_SND_AC97_CODEC=y 1077CONFIG_SND_AC97_CODEC=y
1078CONFIG_SND_DRIVERS=y
1022# CONFIG_SND_DUMMY is not set 1079# CONFIG_SND_DUMMY is not set
1023# CONFIG_SND_MTPAV is not set 1080# CONFIG_SND_MTPAV is not set
1024# CONFIG_SND_SERIAL_U16550 is not set 1081# CONFIG_SND_SERIAL_U16550 is not set
1025# CONFIG_SND_MPU401 is not set 1082# CONFIG_SND_MPU401 is not set
1026 1083# CONFIG_SND_AC97_POWER_SAVE is not set
1027# 1084CONFIG_SND_PCI=y
1028# PCI devices
1029#
1030# CONFIG_SND_AD1889 is not set 1085# CONFIG_SND_AD1889 is not set
1031# CONFIG_SND_ALS300 is not set 1086# CONFIG_SND_ALS300 is not set
1032# CONFIG_SND_ALS4000 is not set 1087# CONFIG_SND_ALS4000 is not set
@@ -1088,39 +1143,12 @@ CONFIG_SND_INTEL8X0=y
1088# CONFIG_SND_VIRTUOSO is not set 1143# CONFIG_SND_VIRTUOSO is not set
1089# CONFIG_SND_VX222 is not set 1144# CONFIG_SND_VX222 is not set
1090# CONFIG_SND_YMFPCI is not set 1145# CONFIG_SND_YMFPCI is not set
1091# CONFIG_SND_AC97_POWER_SAVE is not set 1146CONFIG_SND_PPC=y
1092 1147CONFIG_SND_USB=y
1093#
1094# ALSA PowerMac devices
1095#
1096
1097#
1098# ALSA PowerPC devices
1099#
1100
1101#
1102# USB devices
1103#
1104# CONFIG_SND_USB_AUDIO is not set 1148# CONFIG_SND_USB_AUDIO is not set
1105# CONFIG_SND_USB_USX2Y is not set 1149# CONFIG_SND_USB_USX2Y is not set
1106# CONFIG_SND_USB_CAIAQ is not set 1150# CONFIG_SND_USB_CAIAQ is not set
1107
1108#
1109# System on Chip audio support
1110#
1111# CONFIG_SND_SOC is not set 1151# CONFIG_SND_SOC is not set
1112
1113#
1114# ALSA SoC audio for Freescale SOCs
1115#
1116
1117#
1118# SoC Audio for the Texas Instruments OMAP
1119#
1120
1121#
1122# Open Sound System
1123#
1124# CONFIG_SOUND_PRIME is not set 1152# CONFIG_SOUND_PRIME is not set
1125CONFIG_AC97_BUS=y 1153CONFIG_AC97_BUS=y
1126CONFIG_HID_SUPPORT=y 1154CONFIG_HID_SUPPORT=y
@@ -1152,6 +1180,7 @@ CONFIG_USB_DEVICE_CLASS=y
1152# CONFIG_USB_OTG is not set 1180# CONFIG_USB_OTG is not set
1153# CONFIG_USB_OTG_WHITELIST is not set 1181# CONFIG_USB_OTG_WHITELIST is not set
1154# CONFIG_USB_OTG_BLACKLIST_HUB is not set 1182# CONFIG_USB_OTG_BLACKLIST_HUB is not set
1183CONFIG_USB_MON=y
1155 1184
1156# 1185#
1157# USB Host Controller Drivers 1186# USB Host Controller Drivers
@@ -1175,6 +1204,7 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y
1175# CONFIG_USB_UHCI_HCD is not set 1204# CONFIG_USB_UHCI_HCD is not set
1176# CONFIG_USB_SL811_HCD is not set 1205# CONFIG_USB_SL811_HCD is not set
1177# CONFIG_USB_R8A66597_HCD is not set 1206# CONFIG_USB_R8A66597_HCD is not set
1207# CONFIG_USB_MUSB_HDRC is not set
1178 1208
1179# 1209#
1180# USB Device Class drivers 1210# USB Device Class drivers
@@ -1203,6 +1233,7 @@ CONFIG_USB_STORAGE=y
1203# CONFIG_USB_STORAGE_ALAUDA is not set 1233# CONFIG_USB_STORAGE_ALAUDA is not set
1204# CONFIG_USB_STORAGE_ONETOUCH is not set 1234# CONFIG_USB_STORAGE_ONETOUCH is not set
1205# CONFIG_USB_STORAGE_KARMA is not set 1235# CONFIG_USB_STORAGE_KARMA is not set
1236# CONFIG_USB_STORAGE_SIERRA is not set
1206# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set 1237# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
1207# CONFIG_USB_LIBUSUAL is not set 1238# CONFIG_USB_LIBUSUAL is not set
1208 1239
@@ -1211,7 +1242,6 @@ CONFIG_USB_STORAGE=y
1211# 1242#
1212# CONFIG_USB_MDC800 is not set 1243# CONFIG_USB_MDC800 is not set
1213# CONFIG_USB_MICROTEK is not set 1244# CONFIG_USB_MICROTEK is not set
1214CONFIG_USB_MON=y
1215 1245
1216# 1246#
1217# USB port drivers 1247# USB port drivers
@@ -1224,7 +1254,6 @@ CONFIG_USB_MON=y
1224# CONFIG_USB_EMI62 is not set 1254# CONFIG_USB_EMI62 is not set
1225# CONFIG_USB_EMI26 is not set 1255# CONFIG_USB_EMI26 is not set
1226# CONFIG_USB_ADUTUX is not set 1256# CONFIG_USB_ADUTUX is not set
1227# CONFIG_USB_AUERSWALD is not set
1228# CONFIG_USB_RIO500 is not set 1257# CONFIG_USB_RIO500 is not set
1229# CONFIG_USB_LEGOTOWER is not set 1258# CONFIG_USB_LEGOTOWER is not set
1230# CONFIG_USB_LCD is not set 1259# CONFIG_USB_LCD is not set
@@ -1285,6 +1314,7 @@ CONFIG_RTC_INTF_DEV=y
1285# CONFIG_RTC_DRV_PCF8583 is not set 1314# CONFIG_RTC_DRV_PCF8583 is not set
1286# CONFIG_RTC_DRV_M41T80 is not set 1315# CONFIG_RTC_DRV_M41T80 is not set
1287# CONFIG_RTC_DRV_S35390A is not set 1316# CONFIG_RTC_DRV_S35390A is not set
1317# CONFIG_RTC_DRV_FM3130 is not set
1288 1318
1289# 1319#
1290# SPI RTC drivers 1320# SPI RTC drivers
@@ -1318,6 +1348,7 @@ CONFIG_DMA_ENGINE=y
1318# DMA Clients 1348# DMA Clients
1319# 1349#
1320# CONFIG_NET_DMA is not set 1350# CONFIG_NET_DMA is not set
1351# CONFIG_DMATEST is not set
1321# CONFIG_UIO is not set 1352# CONFIG_UIO is not set
1322 1353
1323# 1354#
@@ -1332,6 +1363,7 @@ CONFIG_EXT3_FS_XATTR=y
1332# CONFIG_EXT3_FS_SECURITY is not set 1363# CONFIG_EXT3_FS_SECURITY is not set
1333# CONFIG_EXT4DEV_FS is not set 1364# CONFIG_EXT4DEV_FS is not set
1334CONFIG_JBD=y 1365CONFIG_JBD=y
1366# CONFIG_JBD_DEBUG is not set
1335CONFIG_FS_MBCACHE=y 1367CONFIG_FS_MBCACHE=y
1336# CONFIG_REISERFS_FS is not set 1368# CONFIG_REISERFS_FS is not set
1337# CONFIG_JFS_FS is not set 1369# CONFIG_JFS_FS is not set
@@ -1394,6 +1426,7 @@ CONFIG_EFS_FS=m
1394CONFIG_CRAMFS=y 1426CONFIG_CRAMFS=y
1395CONFIG_VXFS_FS=m 1427CONFIG_VXFS_FS=m
1396# CONFIG_MINIX_FS is not set 1428# CONFIG_MINIX_FS is not set
1429# CONFIG_OMFS_FS is not set
1397CONFIG_HPFS_FS=m 1430CONFIG_HPFS_FS=m
1398CONFIG_QNX4FS_FS=m 1431CONFIG_QNX4FS_FS=m
1399# CONFIG_ROMFS_FS is not set 1432# CONFIG_ROMFS_FS is not set
@@ -1406,17 +1439,16 @@ CONFIG_NFS_FS=y
1406CONFIG_NFS_V3=y 1439CONFIG_NFS_V3=y
1407# CONFIG_NFS_V3_ACL is not set 1440# CONFIG_NFS_V3_ACL is not set
1408CONFIG_NFS_V4=y 1441CONFIG_NFS_V4=y
1442CONFIG_ROOT_NFS=y
1409CONFIG_NFSD=y 1443CONFIG_NFSD=y
1410# CONFIG_NFSD_V3 is not set 1444# CONFIG_NFSD_V3 is not set
1411# CONFIG_NFSD_V4 is not set 1445# CONFIG_NFSD_V4 is not set
1412CONFIG_ROOT_NFS=y
1413CONFIG_LOCKD=y 1446CONFIG_LOCKD=y
1414CONFIG_LOCKD_V4=y 1447CONFIG_LOCKD_V4=y
1415CONFIG_EXPORTFS=y 1448CONFIG_EXPORTFS=y
1416CONFIG_NFS_COMMON=y 1449CONFIG_NFS_COMMON=y
1417CONFIG_SUNRPC=y 1450CONFIG_SUNRPC=y
1418CONFIG_SUNRPC_GSS=y 1451CONFIG_SUNRPC_GSS=y
1419# CONFIG_SUNRPC_BIND34 is not set
1420CONFIG_RPCSEC_GSS_KRB5=y 1452CONFIG_RPCSEC_GSS_KRB5=y
1421# CONFIG_RPCSEC_GSS_SPKM3 is not set 1453# CONFIG_RPCSEC_GSS_SPKM3 is not set
1422# CONFIG_SMB_FS is not set 1454# CONFIG_SMB_FS is not set
@@ -1487,6 +1519,7 @@ CONFIG_NLS_DEFAULT="iso8859-1"
1487# CONFIG_NLS_KOI8_U is not set 1519# CONFIG_NLS_KOI8_U is not set
1488CONFIG_NLS_UTF8=m 1520CONFIG_NLS_UTF8=m
1489# CONFIG_DLM is not set 1521# CONFIG_DLM is not set
1522# CONFIG_QE_GPIO is not set
1490 1523
1491# 1524#
1492# Library routines 1525# Library routines
@@ -1495,6 +1528,7 @@ CONFIG_BITREVERSE=y
1495# CONFIG_GENERIC_FIND_FIRST_BIT is not set 1528# CONFIG_GENERIC_FIND_FIRST_BIT is not set
1496# CONFIG_CRC_CCITT is not set 1529# CONFIG_CRC_CCITT is not set
1497# CONFIG_CRC16 is not set 1530# CONFIG_CRC16 is not set
1531CONFIG_CRC_T10DIF=y
1498CONFIG_CRC_ITU_T=m 1532CONFIG_CRC_ITU_T=m
1499CONFIG_CRC32=y 1533CONFIG_CRC32=y
1500# CONFIG_CRC7 is not set 1534# CONFIG_CRC7 is not set
@@ -1515,11 +1549,13 @@ CONFIG_ENABLE_MUST_CHECK=y
1515CONFIG_FRAME_WARN=1024 1549CONFIG_FRAME_WARN=1024
1516# CONFIG_MAGIC_SYSRQ is not set 1550# CONFIG_MAGIC_SYSRQ is not set
1517# CONFIG_UNUSED_SYMBOLS is not set 1551# CONFIG_UNUSED_SYMBOLS is not set
1518# CONFIG_DEBUG_FS is not set 1552CONFIG_DEBUG_FS=y
1519# CONFIG_HEADERS_CHECK is not set 1553# CONFIG_HEADERS_CHECK is not set
1520CONFIG_DEBUG_KERNEL=y 1554CONFIG_DEBUG_KERNEL=y
1521# CONFIG_DEBUG_SHIRQ is not set 1555# CONFIG_DEBUG_SHIRQ is not set
1522CONFIG_DETECT_SOFTLOCKUP=y 1556CONFIG_DETECT_SOFTLOCKUP=y
1557# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
1558CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
1523CONFIG_SCHED_DEBUG=y 1559CONFIG_SCHED_DEBUG=y
1524# CONFIG_SCHEDSTATS is not set 1560# CONFIG_SCHEDSTATS is not set
1525# CONFIG_TIMER_STATS is not set 1561# CONFIG_TIMER_STATS is not set
@@ -1538,19 +1574,31 @@ CONFIG_SCHED_DEBUG=y
1538CONFIG_DEBUG_INFO=y 1574CONFIG_DEBUG_INFO=y
1539# CONFIG_DEBUG_VM is not set 1575# CONFIG_DEBUG_VM is not set
1540# CONFIG_DEBUG_WRITECOUNT is not set 1576# CONFIG_DEBUG_WRITECOUNT is not set
1577# CONFIG_DEBUG_MEMORY_INIT is not set
1541# CONFIG_DEBUG_LIST is not set 1578# CONFIG_DEBUG_LIST is not set
1542# CONFIG_DEBUG_SG is not set 1579# CONFIG_DEBUG_SG is not set
1543# CONFIG_BOOT_PRINTK_DELAY is not set 1580# CONFIG_BOOT_PRINTK_DELAY is not set
1544# CONFIG_RCU_TORTURE_TEST is not set 1581# CONFIG_RCU_TORTURE_TEST is not set
1545# CONFIG_BACKTRACE_SELF_TEST is not set 1582# CONFIG_BACKTRACE_SELF_TEST is not set
1546# CONFIG_FAULT_INJECTION is not set 1583# CONFIG_FAULT_INJECTION is not set
1584# CONFIG_LATENCYTOP is not set
1585CONFIG_SYSCTL_SYSCALL_CHECK=y
1586CONFIG_HAVE_FTRACE=y
1587CONFIG_HAVE_DYNAMIC_FTRACE=y
1588# CONFIG_FTRACE is not set
1589# CONFIG_SCHED_TRACER is not set
1590# CONFIG_CONTEXT_SWITCH_TRACER is not set
1547# CONFIG_SAMPLES is not set 1591# CONFIG_SAMPLES is not set
1592CONFIG_HAVE_ARCH_KGDB=y
1593# CONFIG_KGDB is not set
1548# CONFIG_DEBUG_STACKOVERFLOW is not set 1594# CONFIG_DEBUG_STACKOVERFLOW is not set
1549# CONFIG_DEBUG_STACK_USAGE is not set 1595# CONFIG_DEBUG_STACK_USAGE is not set
1550# CONFIG_DEBUG_PAGEALLOC is not set 1596# CONFIG_DEBUG_PAGEALLOC is not set
1551# CONFIG_DEBUGGER is not set 1597# CONFIG_CODE_PATCHING_SELFTEST is not set
1552# CONFIG_KGDB_CONSOLE is not set 1598# CONFIG_FTR_FIXUP_SELFTEST is not set
1599# CONFIG_XMON is not set
1553# CONFIG_IRQSTACKS is not set 1600# CONFIG_IRQSTACKS is not set
1601CONFIG_VIRQ_DEBUG=y
1554# CONFIG_BDI_SWITCH is not set 1602# CONFIG_BDI_SWITCH is not set
1555# CONFIG_PPC_EARLY_DEBUG is not set 1603# CONFIG_PPC_EARLY_DEBUG is not set
1556 1604
@@ -1606,6 +1654,10 @@ CONFIG_CRYPTO_HMAC=y
1606# CONFIG_CRYPTO_MD4 is not set 1654# CONFIG_CRYPTO_MD4 is not set
1607CONFIG_CRYPTO_MD5=y 1655CONFIG_CRYPTO_MD5=y
1608# CONFIG_CRYPTO_MICHAEL_MIC is not set 1656# CONFIG_CRYPTO_MICHAEL_MIC is not set
1657# CONFIG_CRYPTO_RMD128 is not set
1658# CONFIG_CRYPTO_RMD160 is not set
1659# CONFIG_CRYPTO_RMD256 is not set
1660# CONFIG_CRYPTO_RMD320 is not set
1609CONFIG_CRYPTO_SHA1=m 1661CONFIG_CRYPTO_SHA1=m
1610# CONFIG_CRYPTO_SHA256 is not set 1662# CONFIG_CRYPTO_SHA256 is not set
1611# CONFIG_CRYPTO_SHA512 is not set 1663# CONFIG_CRYPTO_SHA512 is not set
@@ -1638,6 +1690,7 @@ CONFIG_CRYPTO_DES=y
1638# CONFIG_CRYPTO_LZO is not set 1690# CONFIG_CRYPTO_LZO is not set
1639CONFIG_CRYPTO_HW=y 1691CONFIG_CRYPTO_HW=y
1640# CONFIG_CRYPTO_DEV_HIFN_795X is not set 1692# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1641# CONFIG_PPC_CLOCK is not set 1693# CONFIG_CRYPTO_DEV_TALITOS is not set
1694CONFIG_PPC_CLOCK=y
1642CONFIG_PPC_LIB_RHEAP=y 1695CONFIG_PPC_LIB_RHEAP=y
1643# CONFIG_VIRTUALIZATION is not set 1696# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/configs/mpc8610_hpcd_defconfig b/arch/powerpc/configs/mpc8610_hpcd_defconfig
index cdf98ae3682b..1a9990731eb0 100644
--- a/arch/powerpc/configs/mpc8610_hpcd_defconfig
+++ b/arch/powerpc/configs/mpc8610_hpcd_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26 3# Linux kernel version: 2.6.27-rc4
4# Tue Jul 15 08:31:01 2008 4# Thu Aug 21 00:52:10 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -32,6 +32,7 @@ CONFIG_GENERIC_HARDIRQS=y
32# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set 32# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
33CONFIG_IRQ_PER_CPU=y 33CONFIG_IRQ_PER_CPU=y
34CONFIG_STACKTRACE_SUPPORT=y 34CONFIG_STACKTRACE_SUPPORT=y
35CONFIG_HAVE_LATENCYTOP_SUPPORT=y
35CONFIG_LOCKDEP_SUPPORT=y 36CONFIG_LOCKDEP_SUPPORT=y
36CONFIG_RWSEM_XCHGADD_ALGORITHM=y 37CONFIG_RWSEM_XCHGADD_ALGORITHM=y
37CONFIG_ARCH_HAS_ILOG2_U32=y 38CONFIG_ARCH_HAS_ILOG2_U32=y
@@ -91,7 +92,6 @@ CONFIG_INITRAMFS_SOURCE=""
91CONFIG_SYSCTL=y 92CONFIG_SYSCTL=y
92CONFIG_EMBEDDED=y 93CONFIG_EMBEDDED=y
93CONFIG_SYSCTL_SYSCALL=y 94CONFIG_SYSCTL_SYSCALL=y
94CONFIG_SYSCTL_SYSCALL_CHECK=y
95CONFIG_KALLSYMS=y 95CONFIG_KALLSYMS=y
96# CONFIG_KALLSYMS_ALL is not set 96# CONFIG_KALLSYMS_ALL is not set
97CONFIG_KALLSYMS_EXTRA_PASS=y 97CONFIG_KALLSYMS_EXTRA_PASS=y
@@ -118,10 +118,16 @@ CONFIG_SLUB=y
118# CONFIG_MARKERS is not set 118# CONFIG_MARKERS is not set
119CONFIG_HAVE_OPROFILE=y 119CONFIG_HAVE_OPROFILE=y
120# CONFIG_KPROBES is not set 120# CONFIG_KPROBES is not set
121CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
122CONFIG_HAVE_IOREMAP_PROT=y
121CONFIG_HAVE_KPROBES=y 123CONFIG_HAVE_KPROBES=y
122CONFIG_HAVE_KRETPROBES=y 124CONFIG_HAVE_KRETPROBES=y
123CONFIG_HAVE_DMA_ATTRS=y 125CONFIG_HAVE_ARCH_TRACEHOOK=y
126# CONFIG_HAVE_DMA_ATTRS is not set
127# CONFIG_USE_GENERIC_SMP_HELPERS is not set
128# CONFIG_HAVE_CLK is not set
124CONFIG_PROC_PAGE_MONITOR=y 129CONFIG_PROC_PAGE_MONITOR=y
130# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
125CONFIG_SLABINFO=y 131CONFIG_SLABINFO=y
126CONFIG_RT_MUTEXES=y 132CONFIG_RT_MUTEXES=y
127# CONFIG_TINY_SHMEM is not set 133# CONFIG_TINY_SHMEM is not set
@@ -138,6 +144,7 @@ CONFIG_BLOCK=y
138# CONFIG_BLK_DEV_IO_TRACE is not set 144# CONFIG_BLK_DEV_IO_TRACE is not set
139# CONFIG_LSF is not set 145# CONFIG_LSF is not set
140# CONFIG_BLK_DEV_BSG is not set 146# CONFIG_BLK_DEV_BSG is not set
147# CONFIG_BLK_DEV_INTEGRITY is not set
141 148
142# 149#
143# IO Schedulers 150# IO Schedulers
@@ -159,9 +166,8 @@ CONFIG_CLASSIC_RCU=y
159CONFIG_PPC_MULTIPLATFORM=y 166CONFIG_PPC_MULTIPLATFORM=y
160CONFIG_CLASSIC32=y 167CONFIG_CLASSIC32=y
161CONFIG_PPC_CHRP=y 168CONFIG_PPC_CHRP=y
162# CONFIG_PPC_MPC512x is not set
163# CONFIG_PPC_MPC5121 is not set
164# CONFIG_MPC5121_ADS is not set 169# CONFIG_MPC5121_ADS is not set
170# CONFIG_MPC5121_GENERIC is not set
165# CONFIG_PPC_MPC52xx is not set 171# CONFIG_PPC_MPC52xx is not set
166CONFIG_PPC_PMAC=y 172CONFIG_PPC_PMAC=y
167# CONFIG_PPC_CELL is not set 173# CONFIG_PPC_CELL is not set
@@ -207,7 +213,7 @@ CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
207# CONFIG_HZ_300 is not set 213# CONFIG_HZ_300 is not set
208CONFIG_HZ_1000=y 214CONFIG_HZ_1000=y
209CONFIG_HZ=1000 215CONFIG_HZ=1000
210# CONFIG_SCHED_HRTICK is not set 216CONFIG_SCHED_HRTICK=y
211CONFIG_PREEMPT_NONE=y 217CONFIG_PREEMPT_NONE=y
212# CONFIG_PREEMPT_VOLUNTARY is not set 218# CONFIG_PREEMPT_VOLUNTARY is not set
213# CONFIG_PREEMPT is not set 219# CONFIG_PREEMPT is not set
@@ -230,6 +236,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
230# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set 236# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
231CONFIG_PAGEFLAGS_EXTENDED=y 237CONFIG_PAGEFLAGS_EXTENDED=y
232CONFIG_SPLIT_PTLOCK_CPUS=4 238CONFIG_SPLIT_PTLOCK_CPUS=4
239CONFIG_MIGRATION=y
233# CONFIG_RESOURCES_64BIT is not set 240# CONFIG_RESOURCES_64BIT is not set
234CONFIG_ZONE_DMA_FLAG=1 241CONFIG_ZONE_DMA_FLAG=1
235CONFIG_BOUNCE=y 242CONFIG_BOUNCE=y
@@ -237,6 +244,7 @@ CONFIG_VIRT_TO_BUS=y
237CONFIG_FORCE_MAX_ZONEORDER=12 244CONFIG_FORCE_MAX_ZONEORDER=12
238CONFIG_PROC_DEVICETREE=y 245CONFIG_PROC_DEVICETREE=y
239# CONFIG_CMDLINE_BOOL is not set 246# CONFIG_CMDLINE_BOOL is not set
247CONFIG_EXTRA_TARGETS=""
240# CONFIG_PM is not set 248# CONFIG_PM is not set
241# CONFIG_SECCOMP is not set 249# CONFIG_SECCOMP is not set
242CONFIG_ISA_DMA_API=y 250CONFIG_ISA_DMA_API=y
@@ -278,10 +286,6 @@ CONFIG_PAGE_OFFSET=0xc0000000
278CONFIG_KERNEL_START=0xc0000000 286CONFIG_KERNEL_START=0xc0000000
279CONFIG_PHYSICAL_START=0x00000000 287CONFIG_PHYSICAL_START=0x00000000
280CONFIG_TASK_SIZE=0xc0000000 288CONFIG_TASK_SIZE=0xc0000000
281
282#
283# Networking
284#
285CONFIG_NET=y 289CONFIG_NET=y
286 290
287# 291#
@@ -391,6 +395,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
391CONFIG_STANDALONE=y 395CONFIG_STANDALONE=y
392CONFIG_PREVENT_FIRMWARE_BUILD=y 396CONFIG_PREVENT_FIRMWARE_BUILD=y
393CONFIG_FW_LOADER=y 397CONFIG_FW_LOADER=y
398CONFIG_FIRMWARE_IN_KERNEL=y
399CONFIG_EXTRA_FIRMWARE=""
394# CONFIG_DEBUG_DRIVER is not set 400# CONFIG_DEBUG_DRIVER is not set
395# CONFIG_DEBUG_DEVRES is not set 401# CONFIG_DEBUG_DEVRES is not set
396# CONFIG_SYS_HYPERVISOR is not set 402# CONFIG_SYS_HYPERVISOR is not set
@@ -503,18 +509,17 @@ CONFIG_BLK_DEV_RAM_SIZE=131072
503# CONFIG_BLK_DEV_XIP is not set 509# CONFIG_BLK_DEV_XIP is not set
504# CONFIG_CDROM_PKTCDVD is not set 510# CONFIG_CDROM_PKTCDVD is not set
505# CONFIG_ATA_OVER_ETH is not set 511# CONFIG_ATA_OVER_ETH is not set
512# CONFIG_BLK_DEV_HD is not set
506CONFIG_MISC_DEVICES=y 513CONFIG_MISC_DEVICES=y
507# CONFIG_PHANTOM is not set 514# CONFIG_PHANTOM is not set
508# CONFIG_EEPROM_93CX6 is not set 515# CONFIG_EEPROM_93CX6 is not set
509# CONFIG_SGI_IOC4 is not set 516# CONFIG_SGI_IOC4 is not set
510# CONFIG_TIFM_CORE is not set 517# CONFIG_TIFM_CORE is not set
511# CONFIG_ENCLOSURE_SERVICES is not set 518# CONFIG_ENCLOSURE_SERVICES is not set
519# CONFIG_HP_ILO is not set
512CONFIG_HAVE_IDE=y 520CONFIG_HAVE_IDE=y
513CONFIG_IDE=y 521CONFIG_IDE=y
514CONFIG_IDE_MAX_HWIFS=4
515# CONFIG_BLK_DEV_IDE is not set 522# CONFIG_BLK_DEV_IDE is not set
516# CONFIG_BLK_DEV_HD_ONLY is not set
517# CONFIG_BLK_DEV_HD is not set
518 523
519# 524#
520# SCSI device support 525# SCSI device support
@@ -593,6 +598,7 @@ CONFIG_SCSI_LOWLEVEL=y
593# CONFIG_SCSI_MESH is not set 598# CONFIG_SCSI_MESH is not set
594# CONFIG_SCSI_MAC53C94 is not set 599# CONFIG_SCSI_MAC53C94 is not set
595# CONFIG_SCSI_SRP is not set 600# CONFIG_SCSI_SRP is not set
601# CONFIG_SCSI_DH is not set
596CONFIG_ATA=y 602CONFIG_ATA=y
597# CONFIG_ATA_NONSTANDARD is not set 603# CONFIG_ATA_NONSTANDARD is not set
598CONFIG_SATA_PMP=y 604CONFIG_SATA_PMP=y
@@ -669,7 +675,6 @@ CONFIG_PATA_ALI=y
669# CONFIG_I2O is not set 675# CONFIG_I2O is not set
670# CONFIG_MACINTOSH_DRIVERS is not set 676# CONFIG_MACINTOSH_DRIVERS is not set
671CONFIG_NETDEVICES=y 677CONFIG_NETDEVICES=y
672# CONFIG_NETDEVICES_MULTIQUEUE is not set
673CONFIG_DUMMY=y 678CONFIG_DUMMY=y
674# CONFIG_BONDING is not set 679# CONFIG_BONDING is not set
675# CONFIG_MACVLAN is not set 680# CONFIG_MACVLAN is not set
@@ -756,12 +761,14 @@ CONFIG_SERIO_SERPORT=y
756# CONFIG_SERIO_PCIPS2 is not set 761# CONFIG_SERIO_PCIPS2 is not set
757CONFIG_SERIO_LIBPS2=y 762CONFIG_SERIO_LIBPS2=y
758# CONFIG_SERIO_RAW is not set 763# CONFIG_SERIO_RAW is not set
764# CONFIG_SERIO_XILINX_XPS_PS2 is not set
759# CONFIG_GAMEPORT is not set 765# CONFIG_GAMEPORT is not set
760 766
761# 767#
762# Character devices 768# Character devices
763# 769#
764CONFIG_VT=y 770CONFIG_VT=y
771CONFIG_CONSOLE_TRANSLATIONS=y
765CONFIG_VT_CONSOLE=y 772CONFIG_VT_CONSOLE=y
766CONFIG_HW_CONSOLE=y 773CONFIG_HW_CONSOLE=y
767# CONFIG_VT_HW_CONSOLE_BINDING is not set 774# CONFIG_VT_HW_CONSOLE_BINDING is not set
@@ -807,44 +814,69 @@ CONFIG_DEVPORT=y
807CONFIG_I2C=y 814CONFIG_I2C=y
808CONFIG_I2C_BOARDINFO=y 815CONFIG_I2C_BOARDINFO=y
809# CONFIG_I2C_CHARDEV is not set 816# CONFIG_I2C_CHARDEV is not set
817CONFIG_I2C_HELPER_AUTO=y
810 818
811# 819#
812# I2C Hardware Bus support 820# I2C Hardware Bus support
813# 821#
822
823#
824# PC SMBus host controller drivers
825#
814# CONFIG_I2C_ALI1535 is not set 826# CONFIG_I2C_ALI1535 is not set
815# CONFIG_I2C_ALI1563 is not set 827# CONFIG_I2C_ALI1563 is not set
816# CONFIG_I2C_ALI15X3 is not set 828# CONFIG_I2C_ALI15X3 is not set
817# CONFIG_I2C_AMD756 is not set 829# CONFIG_I2C_AMD756 is not set
818# CONFIG_I2C_AMD8111 is not set 830# CONFIG_I2C_AMD8111 is not set
819# CONFIG_I2C_HYDRA is not set
820# CONFIG_I2C_I801 is not set 831# CONFIG_I2C_I801 is not set
821# CONFIG_I2C_I810 is not set 832# CONFIG_I2C_ISCH is not set
822# CONFIG_I2C_PIIX4 is not set 833# CONFIG_I2C_PIIX4 is not set
823CONFIG_I2C_POWERMAC=y
824CONFIG_I2C_MPC=y
825# CONFIG_I2C_NFORCE2 is not set 834# CONFIG_I2C_NFORCE2 is not set
826# CONFIG_I2C_OCORES is not set
827# CONFIG_I2C_PARPORT_LIGHT is not set
828# CONFIG_I2C_PROSAVAGE is not set
829# CONFIG_I2C_SAVAGE4 is not set
830# CONFIG_I2C_SIMTEC is not set
831# CONFIG_I2C_SIS5595 is not set 835# CONFIG_I2C_SIS5595 is not set
832# CONFIG_I2C_SIS630 is not set 836# CONFIG_I2C_SIS630 is not set
833# CONFIG_I2C_SIS96X is not set 837# CONFIG_I2C_SIS96X is not set
834# CONFIG_I2C_TAOS_EVM is not set
835# CONFIG_I2C_STUB is not set
836# CONFIG_I2C_VIA is not set 838# CONFIG_I2C_VIA is not set
837# CONFIG_I2C_VIAPRO is not set 839# CONFIG_I2C_VIAPRO is not set
840
841#
842# Mac SMBus host controller drivers
843#
844# CONFIG_I2C_HYDRA is not set
845CONFIG_I2C_POWERMAC=y
846
847#
848# I2C system bus drivers (mostly embedded / system-on-chip)
849#
850CONFIG_I2C_MPC=y
851# CONFIG_I2C_OCORES is not set
852# CONFIG_I2C_SIMTEC is not set
853
854#
855# External I2C/SMBus adapter drivers
856#
857# CONFIG_I2C_PARPORT_LIGHT is not set
858# CONFIG_I2C_TAOS_EVM is not set
859
860#
861# Graphics adapter I2C/DDC channel drivers
862#
838# CONFIG_I2C_VOODOO3 is not set 863# CONFIG_I2C_VOODOO3 is not set
864
865#
866# Other I2C/SMBus bus drivers
867#
839# CONFIG_I2C_PCA_PLATFORM is not set 868# CONFIG_I2C_PCA_PLATFORM is not set
869# CONFIG_I2C_STUB is not set
840 870
841# 871#
842# Miscellaneous I2C Chip support 872# Miscellaneous I2C Chip support
843# 873#
844# CONFIG_DS1682 is not set 874# CONFIG_DS1682 is not set
875# CONFIG_AT24 is not set
845# CONFIG_SENSORS_EEPROM is not set 876# CONFIG_SENSORS_EEPROM is not set
846# CONFIG_SENSORS_PCF8574 is not set 877# CONFIG_SENSORS_PCF8574 is not set
847# CONFIG_PCF8575 is not set 878# CONFIG_PCF8575 is not set
879# CONFIG_SENSORS_PCA9539 is not set
848# CONFIG_SENSORS_PCF8591 is not set 880# CONFIG_SENSORS_PCF8591 is not set
849# CONFIG_SENSORS_MAX6875 is not set 881# CONFIG_SENSORS_MAX6875 is not set
850# CONFIG_SENSORS_TSL2550 is not set 882# CONFIG_SENSORS_TSL2550 is not set
@@ -853,6 +885,8 @@ CONFIG_I2C_MPC=y
853# CONFIG_I2C_DEBUG_BUS is not set 885# CONFIG_I2C_DEBUG_BUS is not set
854# CONFIG_I2C_DEBUG_CHIP is not set 886# CONFIG_I2C_DEBUG_CHIP is not set
855# CONFIG_SPI is not set 887# CONFIG_SPI is not set
888CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
889# CONFIG_GPIOLIB is not set
856# CONFIG_W1 is not set 890# CONFIG_W1 is not set
857# CONFIG_POWER_SUPPLY is not set 891# CONFIG_POWER_SUPPLY is not set
858# CONFIG_HWMON is not set 892# CONFIG_HWMON is not set
@@ -869,8 +903,10 @@ CONFIG_SSB_POSSIBLE=y
869# 903#
870# Multifunction device drivers 904# Multifunction device drivers
871# 905#
906# CONFIG_MFD_CORE is not set
872# CONFIG_MFD_SM501 is not set 907# CONFIG_MFD_SM501 is not set
873# CONFIG_HTC_PASIC3 is not set 908# CONFIG_HTC_PASIC3 is not set
909# CONFIG_MFD_TMIO is not set
874 910
875# 911#
876# Multimedia devices 912# Multimedia devices
@@ -945,6 +981,7 @@ CONFIG_FB_CFB_IMAGEBLIT=y
945# CONFIG_FB_TRIDENT is not set 981# CONFIG_FB_TRIDENT is not set
946# CONFIG_FB_ARK is not set 982# CONFIG_FB_ARK is not set
947# CONFIG_FB_PM3 is not set 983# CONFIG_FB_PM3 is not set
984# CONFIG_FB_CARMINE is not set
948CONFIG_FB_FSL_DIU=y 985CONFIG_FB_FSL_DIU=y
949# CONFIG_FB_IBM_GXT4500 is not set 986# CONFIG_FB_IBM_GXT4500 is not set
950# CONFIG_FB_VIRTUAL is not set 987# CONFIG_FB_VIRTUAL is not set
@@ -963,15 +1000,7 @@ CONFIG_VGA_CONSOLE=y
963CONFIG_DUMMY_CONSOLE=y 1000CONFIG_DUMMY_CONSOLE=y
964# CONFIG_FRAMEBUFFER_CONSOLE is not set 1001# CONFIG_FRAMEBUFFER_CONSOLE is not set
965# CONFIG_LOGO is not set 1002# CONFIG_LOGO is not set
966
967#
968# Sound
969#
970CONFIG_SOUND=y 1003CONFIG_SOUND=y
971
972#
973# Advanced Linux Sound Architecture
974#
975CONFIG_SND=y 1004CONFIG_SND=y
976CONFIG_SND_TIMER=y 1005CONFIG_SND_TIMER=y
977CONFIG_SND_PCM=y 1006CONFIG_SND_PCM=y
@@ -985,18 +1014,12 @@ CONFIG_SND_PCM_OSS_PLUGINS=y
985CONFIG_SND_VERBOSE_PROCFS=y 1014CONFIG_SND_VERBOSE_PROCFS=y
986# CONFIG_SND_VERBOSE_PRINTK is not set 1015# CONFIG_SND_VERBOSE_PRINTK is not set
987# CONFIG_SND_DEBUG is not set 1016# CONFIG_SND_DEBUG is not set
988 1017CONFIG_SND_DRIVERS=y
989#
990# Generic devices
991#
992# CONFIG_SND_DUMMY is not set 1018# CONFIG_SND_DUMMY is not set
993# CONFIG_SND_MTPAV is not set 1019# CONFIG_SND_MTPAV is not set
994# CONFIG_SND_SERIAL_U16550 is not set 1020# CONFIG_SND_SERIAL_U16550 is not set
995# CONFIG_SND_MPU401 is not set 1021# CONFIG_SND_MPU401 is not set
996 1022CONFIG_SND_PCI=y
997#
998# PCI devices
999#
1000# CONFIG_SND_AD1889 is not set 1023# CONFIG_SND_AD1889 is not set
1001# CONFIG_SND_ALS300 is not set 1024# CONFIG_SND_ALS300 is not set
1002# CONFIG_SND_ALS4000 is not set 1025# CONFIG_SND_ALS4000 is not set
@@ -1058,42 +1081,14 @@ CONFIG_SND_VERBOSE_PROCFS=y
1058# CONFIG_SND_VIRTUOSO is not set 1081# CONFIG_SND_VIRTUOSO is not set
1059# CONFIG_SND_VX222 is not set 1082# CONFIG_SND_VX222 is not set
1060# CONFIG_SND_YMFPCI is not set 1083# CONFIG_SND_YMFPCI is not set
1061 1084CONFIG_SND_PPC=y
1062#
1063# ALSA PowerMac devices
1064#
1065# CONFIG_SND_POWERMAC is not set 1085# CONFIG_SND_POWERMAC is not set
1066
1067#
1068# ALSA PowerPC devices
1069#
1070
1071#
1072# Apple Onboard Audio driver
1073#
1074# CONFIG_SND_AOA is not set 1086# CONFIG_SND_AOA is not set
1075# CONFIG_SND_AOA_SOUNDBUS is not set
1076
1077#
1078# System on Chip audio support
1079#
1080CONFIG_SND_SOC=y 1087CONFIG_SND_SOC=y
1081
1082#
1083# ALSA SoC audio for Freescale SOCs
1084#
1085CONFIG_SND_SOC_MPC8610=y 1088CONFIG_SND_SOC_MPC8610=y
1086CONFIG_SND_SOC_MPC8610_HPCD=y 1089CONFIG_SND_SOC_MPC8610_HPCD=y
1087
1088#
1089# SoC Audio for the Texas Instruments OMAP
1090#
1091CONFIG_SND_SOC_CS4270=y 1090CONFIG_SND_SOC_CS4270=y
1092CONFIG_SND_SOC_CS4270_VD33_ERRATA=y 1091CONFIG_SND_SOC_CS4270_VD33_ERRATA=y
1093
1094#
1095# Open Sound System
1096#
1097# CONFIG_SOUND_PRIME is not set 1092# CONFIG_SOUND_PRIME is not set
1098CONFIG_HID_SUPPORT=y 1093CONFIG_HID_SUPPORT=y
1099CONFIG_HID=y 1094CONFIG_HID=y
@@ -1108,6 +1103,10 @@ CONFIG_USB_ARCH_HAS_EHCI=y
1108# CONFIG_USB_OTG_BLACKLIST_HUB is not set 1103# CONFIG_USB_OTG_BLACKLIST_HUB is not set
1109 1104
1110# 1105#
1106# Enable Host or Gadget support to see Inventra options
1107#
1108
1109#
1111# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 1110# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
1112# 1111#
1113# CONFIG_USB_GADGET is not set 1112# CONFIG_USB_GADGET is not set
@@ -1235,6 +1234,7 @@ CONFIG_TMPFS=y
1235# CONFIG_CRAMFS is not set 1234# CONFIG_CRAMFS is not set
1236# CONFIG_VXFS_FS is not set 1235# CONFIG_VXFS_FS is not set
1237# CONFIG_MINIX_FS is not set 1236# CONFIG_MINIX_FS is not set
1237# CONFIG_OMFS_FS is not set
1238# CONFIG_HPFS_FS is not set 1238# CONFIG_HPFS_FS is not set
1239# CONFIG_QNX4FS_FS is not set 1239# CONFIG_QNX4FS_FS is not set
1240# CONFIG_ROMFS_FS is not set 1240# CONFIG_ROMFS_FS is not set
@@ -1245,16 +1245,15 @@ CONFIG_NFS_FS=y
1245CONFIG_NFS_V3=y 1245CONFIG_NFS_V3=y
1246# CONFIG_NFS_V3_ACL is not set 1246# CONFIG_NFS_V3_ACL is not set
1247# CONFIG_NFS_V4 is not set 1247# CONFIG_NFS_V4 is not set
1248CONFIG_ROOT_NFS=y
1248CONFIG_NFSD=y 1249CONFIG_NFSD=y
1249# CONFIG_NFSD_V3 is not set 1250# CONFIG_NFSD_V3 is not set
1250# CONFIG_NFSD_V4 is not set 1251# CONFIG_NFSD_V4 is not set
1251CONFIG_ROOT_NFS=y
1252CONFIG_LOCKD=y 1252CONFIG_LOCKD=y
1253CONFIG_LOCKD_V4=y 1253CONFIG_LOCKD_V4=y
1254CONFIG_EXPORTFS=y 1254CONFIG_EXPORTFS=y
1255CONFIG_NFS_COMMON=y 1255CONFIG_NFS_COMMON=y
1256CONFIG_SUNRPC=y 1256CONFIG_SUNRPC=y
1257# CONFIG_SUNRPC_BIND34 is not set
1258# CONFIG_RPCSEC_GSS_KRB5 is not set 1257# CONFIG_RPCSEC_GSS_KRB5 is not set
1259# CONFIG_RPCSEC_GSS_SPKM3 is not set 1258# CONFIG_RPCSEC_GSS_SPKM3 is not set
1260# CONFIG_SMB_FS is not set 1259# CONFIG_SMB_FS is not set
@@ -1334,6 +1333,7 @@ CONFIG_BITREVERSE=y
1334# CONFIG_GENERIC_FIND_FIRST_BIT is not set 1333# CONFIG_GENERIC_FIND_FIRST_BIT is not set
1335# CONFIG_CRC_CCITT is not set 1334# CONFIG_CRC_CCITT is not set
1336# CONFIG_CRC16 is not set 1335# CONFIG_CRC16 is not set
1336CONFIG_CRC_T10DIF=y
1337# CONFIG_CRC_ITU_T is not set 1337# CONFIG_CRC_ITU_T is not set
1338CONFIG_CRC32=y 1338CONFIG_CRC32=y
1339# CONFIG_CRC7 is not set 1339# CONFIG_CRC7 is not set
@@ -1358,6 +1358,8 @@ CONFIG_FRAME_WARN=1024
1358CONFIG_DEBUG_KERNEL=y 1358CONFIG_DEBUG_KERNEL=y
1359CONFIG_DEBUG_SHIRQ=y 1359CONFIG_DEBUG_SHIRQ=y
1360CONFIG_DETECT_SOFTLOCKUP=y 1360CONFIG_DETECT_SOFTLOCKUP=y
1361# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
1362CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
1361CONFIG_SCHED_DEBUG=y 1363CONFIG_SCHED_DEBUG=y
1362# CONFIG_SCHEDSTATS is not set 1364# CONFIG_SCHEDSTATS is not set
1363# CONFIG_TIMER_STATS is not set 1365# CONFIG_TIMER_STATS is not set
@@ -1376,19 +1378,29 @@ CONFIG_DEBUG_BUGVERBOSE=y
1376CONFIG_DEBUG_INFO=y 1378CONFIG_DEBUG_INFO=y
1377# CONFIG_DEBUG_VM is not set 1379# CONFIG_DEBUG_VM is not set
1378# CONFIG_DEBUG_WRITECOUNT is not set 1380# CONFIG_DEBUG_WRITECOUNT is not set
1381# CONFIG_DEBUG_MEMORY_INIT is not set
1379# CONFIG_DEBUG_LIST is not set 1382# CONFIG_DEBUG_LIST is not set
1380# CONFIG_DEBUG_SG is not set 1383# CONFIG_DEBUG_SG is not set
1381# CONFIG_BOOT_PRINTK_DELAY is not set 1384# CONFIG_BOOT_PRINTK_DELAY is not set
1382# CONFIG_RCU_TORTURE_TEST is not set 1385# CONFIG_RCU_TORTURE_TEST is not set
1383# CONFIG_BACKTRACE_SELF_TEST is not set 1386# CONFIG_BACKTRACE_SELF_TEST is not set
1384# CONFIG_FAULT_INJECTION is not set 1387# CONFIG_FAULT_INJECTION is not set
1388# CONFIG_LATENCYTOP is not set
1389CONFIG_SYSCTL_SYSCALL_CHECK=y
1390CONFIG_HAVE_FTRACE=y
1391CONFIG_HAVE_DYNAMIC_FTRACE=y
1392# CONFIG_FTRACE is not set
1393# CONFIG_SCHED_TRACER is not set
1394# CONFIG_CONTEXT_SWITCH_TRACER is not set
1385# CONFIG_SAMPLES is not set 1395# CONFIG_SAMPLES is not set
1396CONFIG_HAVE_ARCH_KGDB=y
1397# CONFIG_KGDB is not set
1386# CONFIG_DEBUG_STACKOVERFLOW is not set 1398# CONFIG_DEBUG_STACKOVERFLOW is not set
1387# CONFIG_DEBUG_STACK_USAGE is not set 1399# CONFIG_DEBUG_STACK_USAGE is not set
1388# CONFIG_DEBUG_PAGEALLOC is not set 1400# CONFIG_DEBUG_PAGEALLOC is not set
1389# CONFIG_DEBUGGER is not set
1390# CONFIG_CODE_PATCHING_SELFTEST is not set 1401# CONFIG_CODE_PATCHING_SELFTEST is not set
1391# CONFIG_FTR_FIXUP_SELFTEST is not set 1402# CONFIG_FTR_FIXUP_SELFTEST is not set
1403# CONFIG_XMON is not set
1392# CONFIG_IRQSTACKS is not set 1404# CONFIG_IRQSTACKS is not set
1393# CONFIG_BDI_SWITCH is not set 1405# CONFIG_BDI_SWITCH is not set
1394# CONFIG_BOOTX_TEXT is not set 1406# CONFIG_BOOTX_TEXT is not set
@@ -1443,6 +1455,10 @@ CONFIG_CRYPTO=y
1443# CONFIG_CRYPTO_MD4 is not set 1455# CONFIG_CRYPTO_MD4 is not set
1444# CONFIG_CRYPTO_MD5 is not set 1456# CONFIG_CRYPTO_MD5 is not set
1445# CONFIG_CRYPTO_MICHAEL_MIC is not set 1457# CONFIG_CRYPTO_MICHAEL_MIC is not set
1458# CONFIG_CRYPTO_RMD128 is not set
1459# CONFIG_CRYPTO_RMD160 is not set
1460# CONFIG_CRYPTO_RMD256 is not set
1461# CONFIG_CRYPTO_RMD320 is not set
1446# CONFIG_CRYPTO_SHA1 is not set 1462# CONFIG_CRYPTO_SHA1 is not set
1447# CONFIG_CRYPTO_SHA256 is not set 1463# CONFIG_CRYPTO_SHA256 is not set
1448# CONFIG_CRYPTO_SHA512 is not set 1464# CONFIG_CRYPTO_SHA512 is not set
@@ -1475,6 +1491,7 @@ CONFIG_CRYPTO=y
1475# CONFIG_CRYPTO_LZO is not set 1491# CONFIG_CRYPTO_LZO is not set
1476CONFIG_CRYPTO_HW=y 1492CONFIG_CRYPTO_HW=y
1477# CONFIG_CRYPTO_DEV_HIFN_795X is not set 1493# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1494# CONFIG_CRYPTO_DEV_TALITOS is not set
1478# CONFIG_PPC_CLOCK is not set 1495# CONFIG_PPC_CLOCK is not set
1479CONFIG_PPC_LIB_RHEAP=y 1496CONFIG_PPC_LIB_RHEAP=y
1480# CONFIG_VIRTUALIZATION is not set 1497# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/configs/mpc8641_hpcn_defconfig b/arch/powerpc/configs/mpc8641_hpcn_defconfig
index 867b8c0215f3..ea09be31b6ea 100644
--- a/arch/powerpc/configs/mpc8641_hpcn_defconfig
+++ b/arch/powerpc/configs/mpc8641_hpcn_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc5 3# Linux kernel version: 2.6.27-rc4
4# Mon Jun 9 08:52:15 2008 4# Thu Aug 21 00:52:11 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -33,6 +33,7 @@ CONFIG_GENERIC_HARDIRQS=y
33# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set 33# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
34CONFIG_IRQ_PER_CPU=y 34CONFIG_IRQ_PER_CPU=y
35CONFIG_STACKTRACE_SUPPORT=y 35CONFIG_STACKTRACE_SUPPORT=y
36CONFIG_HAVE_LATENCYTOP_SUPPORT=y
36CONFIG_LOCKDEP_SUPPORT=y 37CONFIG_LOCKDEP_SUPPORT=y
37CONFIG_RWSEM_XCHGADD_ALGORITHM=y 38CONFIG_RWSEM_XCHGADD_ALGORITHM=y
38CONFIG_ARCH_HAS_ILOG2_U32=y 39CONFIG_ARCH_HAS_ILOG2_U32=y
@@ -92,7 +93,6 @@ CONFIG_INITRAMFS_SOURCE=""
92CONFIG_SYSCTL=y 93CONFIG_SYSCTL=y
93CONFIG_EMBEDDED=y 94CONFIG_EMBEDDED=y
94CONFIG_SYSCTL_SYSCALL=y 95CONFIG_SYSCTL_SYSCALL=y
95CONFIG_SYSCTL_SYSCALL_CHECK=y
96CONFIG_KALLSYMS=y 96CONFIG_KALLSYMS=y
97CONFIG_KALLSYMS_ALL=y 97CONFIG_KALLSYMS_ALL=y
98CONFIG_KALLSYMS_EXTRA_PASS=y 98CONFIG_KALLSYMS_EXTRA_PASS=y
@@ -100,6 +100,7 @@ CONFIG_HOTPLUG=y
100CONFIG_PRINTK=y 100CONFIG_PRINTK=y
101CONFIG_BUG=y 101CONFIG_BUG=y
102CONFIG_ELF_CORE=y 102CONFIG_ELF_CORE=y
103CONFIG_PCSPKR_PLATFORM=y
103CONFIG_COMPAT_BRK=y 104CONFIG_COMPAT_BRK=y
104CONFIG_BASE_FULL=y 105CONFIG_BASE_FULL=y
105CONFIG_FUTEX=y 106CONFIG_FUTEX=y
@@ -118,10 +119,16 @@ CONFIG_SLUB=y
118# CONFIG_MARKERS is not set 119# CONFIG_MARKERS is not set
119CONFIG_HAVE_OPROFILE=y 120CONFIG_HAVE_OPROFILE=y
120# CONFIG_KPROBES is not set 121# CONFIG_KPROBES is not set
122CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
123CONFIG_HAVE_IOREMAP_PROT=y
121CONFIG_HAVE_KPROBES=y 124CONFIG_HAVE_KPROBES=y
122CONFIG_HAVE_KRETPROBES=y 125CONFIG_HAVE_KRETPROBES=y
126CONFIG_HAVE_ARCH_TRACEHOOK=y
123# CONFIG_HAVE_DMA_ATTRS is not set 127# CONFIG_HAVE_DMA_ATTRS is not set
128CONFIG_USE_GENERIC_SMP_HELPERS=y
129# CONFIG_HAVE_CLK is not set
124CONFIG_PROC_PAGE_MONITOR=y 130CONFIG_PROC_PAGE_MONITOR=y
131# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
125CONFIG_SLABINFO=y 132CONFIG_SLABINFO=y
126CONFIG_RT_MUTEXES=y 133CONFIG_RT_MUTEXES=y
127# CONFIG_TINY_SHMEM is not set 134# CONFIG_TINY_SHMEM is not set
@@ -139,6 +146,7 @@ CONFIG_LBD=y
139# CONFIG_BLK_DEV_IO_TRACE is not set 146# CONFIG_BLK_DEV_IO_TRACE is not set
140# CONFIG_LSF is not set 147# CONFIG_LSF is not set
141# CONFIG_BLK_DEV_BSG is not set 148# CONFIG_BLK_DEV_BSG is not set
149# CONFIG_BLK_DEV_INTEGRITY is not set
142 150
143# 151#
144# IO Schedulers 152# IO Schedulers
@@ -157,30 +165,40 @@ CONFIG_CLASSIC_RCU=y
157# 165#
158# Platform support 166# Platform support
159# 167#
160# CONFIG_PPC_MULTIPLATFORM is not set 168CONFIG_PPC_MULTIPLATFORM=y
161# CONFIG_PPC_82xx is not set 169CONFIG_CLASSIC32=y
162# CONFIG_PPC_83xx is not set 170CONFIG_PPC_CHRP=y
163CONFIG_PPC_86xx=y 171# CONFIG_MPC5121_ADS is not set
164# CONFIG_PPC_MPC512x is not set 172# CONFIG_MPC5121_GENERIC is not set
165# CONFIG_PPC_MPC5121 is not set 173# CONFIG_PPC_MPC52xx is not set
174CONFIG_PPC_PMAC=y
166# CONFIG_PPC_CELL is not set 175# CONFIG_PPC_CELL is not set
167# CONFIG_PPC_CELL_NATIVE is not set 176# CONFIG_PPC_CELL_NATIVE is not set
177# CONFIG_PPC_82xx is not set
168# CONFIG_PQ2ADS is not set 178# CONFIG_PQ2ADS is not set
179# CONFIG_PPC_83xx is not set
180CONFIG_PPC_86xx=y
169CONFIG_MPC8641_HPCN=y 181CONFIG_MPC8641_HPCN=y
170# CONFIG_SBC8641D is not set 182# CONFIG_SBC8641D is not set
171# CONFIG_MPC8610_HPCD is not set 183# CONFIG_MPC8610_HPCD is not set
172CONFIG_MPC8641=y 184CONFIG_MPC8641=y
185CONFIG_PPC_NATIVE=y
186# CONFIG_UDBG_RTAS_CONSOLE is not set
173# CONFIG_IPIC is not set 187# CONFIG_IPIC is not set
174CONFIG_MPIC=y 188CONFIG_MPIC=y
175# CONFIG_MPIC_WEIRD is not set 189# CONFIG_MPIC_WEIRD is not set
176CONFIG_PPC_I8259=y 190CONFIG_PPC_I8259=y
177# CONFIG_PPC_RTAS is not set 191CONFIG_PPC_RTAS=y
192# CONFIG_RTAS_ERROR_LOGGING is not set
193CONFIG_RTAS_PROC=y
178# CONFIG_MMIO_NVRAM is not set 194# CONFIG_MMIO_NVRAM is not set
179# CONFIG_PPC_MPC106 is not set 195CONFIG_PPC_MPC106=y
180# CONFIG_PPC_970_NAP is not set 196# CONFIG_PPC_970_NAP is not set
181# CONFIG_PPC_INDIRECT_IO is not set 197# CONFIG_PPC_INDIRECT_IO is not set
182# CONFIG_GENERIC_IOMAP is not set 198# CONFIG_GENERIC_IOMAP is not set
183# CONFIG_CPU_FREQ is not set 199# CONFIG_CPU_FREQ is not set
200# CONFIG_PPC601_SYNC_FIX is not set
201# CONFIG_TAU is not set
184CONFIG_FSL_ULI1575=y 202CONFIG_FSL_ULI1575=y
185 203
186# 204#
@@ -196,16 +214,18 @@ CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
196# CONFIG_HZ_300 is not set 214# CONFIG_HZ_300 is not set
197CONFIG_HZ_1000=y 215CONFIG_HZ_1000=y
198CONFIG_HZ=1000 216CONFIG_HZ=1000
199# CONFIG_SCHED_HRTICK is not set 217CONFIG_SCHED_HRTICK=y
200CONFIG_PREEMPT_NONE=y 218CONFIG_PREEMPT_NONE=y
201# CONFIG_PREEMPT_VOLUNTARY is not set 219# CONFIG_PREEMPT_VOLUNTARY is not set
202# CONFIG_PREEMPT is not set 220# CONFIG_PREEMPT is not set
203CONFIG_BINFMT_ELF=y 221CONFIG_BINFMT_ELF=y
204CONFIG_BINFMT_MISC=m 222CONFIG_BINFMT_MISC=m
205# CONFIG_IOMMU_HELPER is not set 223# CONFIG_IOMMU_HELPER is not set
224# CONFIG_HOTPLUG_CPU is not set
206CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y 225CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
207CONFIG_ARCH_HAS_WALK_MEMORY=y 226CONFIG_ARCH_HAS_WALK_MEMORY=y
208CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y 227CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
228# CONFIG_KEXEC is not set
209# CONFIG_IRQ_ALL_CPUS is not set 229# CONFIG_IRQ_ALL_CPUS is not set
210CONFIG_ARCH_FLATMEM_ENABLE=y 230CONFIG_ARCH_FLATMEM_ENABLE=y
211CONFIG_ARCH_POPULATES_NODE_MAP=y 231CONFIG_ARCH_POPULATES_NODE_MAP=y
@@ -219,6 +239,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
219# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set 239# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
220CONFIG_PAGEFLAGS_EXTENDED=y 240CONFIG_PAGEFLAGS_EXTENDED=y
221CONFIG_SPLIT_PTLOCK_CPUS=4 241CONFIG_SPLIT_PTLOCK_CPUS=4
242CONFIG_MIGRATION=y
222# CONFIG_RESOURCES_64BIT is not set 243# CONFIG_RESOURCES_64BIT is not set
223CONFIG_ZONE_DMA_FLAG=1 244CONFIG_ZONE_DMA_FLAG=1
224CONFIG_BOUNCE=y 245CONFIG_BOUNCE=y
@@ -226,6 +247,7 @@ CONFIG_VIRT_TO_BUS=y
226CONFIG_FORCE_MAX_ZONEORDER=11 247CONFIG_FORCE_MAX_ZONEORDER=11
227CONFIG_PROC_DEVICETREE=y 248CONFIG_PROC_DEVICETREE=y
228# CONFIG_CMDLINE_BOOL is not set 249# CONFIG_CMDLINE_BOOL is not set
250CONFIG_EXTRA_TARGETS=""
229# CONFIG_PM is not set 251# CONFIG_PM is not set
230CONFIG_SECCOMP=y 252CONFIG_SECCOMP=y
231CONFIG_ISA_DMA_API=y 253CONFIG_ISA_DMA_API=y
@@ -233,11 +255,13 @@ CONFIG_ISA_DMA_API=y
233# 255#
234# Bus options 256# Bus options
235# 257#
258# CONFIG_ISA is not set
236CONFIG_ZONE_DMA=y 259CONFIG_ZONE_DMA=y
237CONFIG_GENERIC_ISA_DMA=y 260CONFIG_GENERIC_ISA_DMA=y
238CONFIG_PPC_INDIRECT_PCI=y 261CONFIG_PPC_INDIRECT_PCI=y
239CONFIG_FSL_SOC=y 262CONFIG_FSL_SOC=y
240CONFIG_FSL_PCI=y 263CONFIG_FSL_PCI=y
264CONFIG_PPC_PCI_CHOICE=y
241CONFIG_PCI=y 265CONFIG_PCI=y
242CONFIG_PCI_DOMAINS=y 266CONFIG_PCI_DOMAINS=y
243CONFIG_PCI_SYSCALL=y 267CONFIG_PCI_SYSCALL=y
@@ -264,10 +288,6 @@ CONFIG_PAGE_OFFSET=0xc0000000
264CONFIG_KERNEL_START=0xc0000000 288CONFIG_KERNEL_START=0xc0000000
265CONFIG_PHYSICAL_START=0x00000000 289CONFIG_PHYSICAL_START=0x00000000
266CONFIG_TASK_SIZE=0xc0000000 290CONFIG_TASK_SIZE=0xc0000000
267
268#
269# Networking
270#
271CONFIG_NET=y 291CONFIG_NET=y
272 292
273# 293#
@@ -393,6 +413,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
393CONFIG_STANDALONE=y 413CONFIG_STANDALONE=y
394CONFIG_PREVENT_FIRMWARE_BUILD=y 414CONFIG_PREVENT_FIRMWARE_BUILD=y
395CONFIG_FW_LOADER=y 415CONFIG_FW_LOADER=y
416CONFIG_FIRMWARE_IN_KERNEL=y
417CONFIG_EXTRA_FIRMWARE=""
396# CONFIG_DEBUG_DRIVER is not set 418# CONFIG_DEBUG_DRIVER is not set
397# CONFIG_DEBUG_DEVRES is not set 419# CONFIG_DEBUG_DEVRES is not set
398# CONFIG_SYS_HYPERVISOR is not set 420# CONFIG_SYS_HYPERVISOR is not set
@@ -403,6 +425,7 @@ CONFIG_OF_I2C=y
403# CONFIG_PARPORT is not set 425# CONFIG_PARPORT is not set
404CONFIG_BLK_DEV=y 426CONFIG_BLK_DEV=y
405# CONFIG_BLK_DEV_FD is not set 427# CONFIG_BLK_DEV_FD is not set
428# CONFIG_MAC_FLOPPY is not set
406# CONFIG_BLK_CPQ_DA is not set 429# CONFIG_BLK_CPQ_DA is not set
407# CONFIG_BLK_CPQ_CISS_DA is not set 430# CONFIG_BLK_CPQ_CISS_DA is not set
408# CONFIG_BLK_DEV_DAC960 is not set 431# CONFIG_BLK_DEV_DAC960 is not set
@@ -419,12 +442,14 @@ CONFIG_BLK_DEV_RAM_SIZE=131072
419# CONFIG_BLK_DEV_XIP is not set 442# CONFIG_BLK_DEV_XIP is not set
420# CONFIG_CDROM_PKTCDVD is not set 443# CONFIG_CDROM_PKTCDVD is not set
421# CONFIG_ATA_OVER_ETH is not set 444# CONFIG_ATA_OVER_ETH is not set
445# CONFIG_BLK_DEV_HD is not set
422CONFIG_MISC_DEVICES=y 446CONFIG_MISC_DEVICES=y
423# CONFIG_PHANTOM is not set 447# CONFIG_PHANTOM is not set
424# CONFIG_EEPROM_93CX6 is not set 448# CONFIG_EEPROM_93CX6 is not set
425# CONFIG_SGI_IOC4 is not set 449# CONFIG_SGI_IOC4 is not set
426# CONFIG_TIFM_CORE is not set 450# CONFIG_TIFM_CORE is not set
427# CONFIG_ENCLOSURE_SERVICES is not set 451# CONFIG_ENCLOSURE_SERVICES is not set
452# CONFIG_HP_ILO is not set
428CONFIG_HAVE_IDE=y 453CONFIG_HAVE_IDE=y
429# CONFIG_IDE is not set 454# CONFIG_IDE is not set
430 455
@@ -503,7 +528,10 @@ CONFIG_SCSI_LOWLEVEL=y
503# CONFIG_SCSI_DC390T is not set 528# CONFIG_SCSI_DC390T is not set
504# CONFIG_SCSI_NSP32 is not set 529# CONFIG_SCSI_NSP32 is not set
505# CONFIG_SCSI_DEBUG is not set 530# CONFIG_SCSI_DEBUG is not set
531# CONFIG_SCSI_MESH is not set
532# CONFIG_SCSI_MAC53C94 is not set
506# CONFIG_SCSI_SRP is not set 533# CONFIG_SCSI_SRP is not set
534# CONFIG_SCSI_DH is not set
507CONFIG_ATA=y 535CONFIG_ATA=y
508# CONFIG_ATA_NONSTANDARD is not set 536# CONFIG_ATA_NONSTANDARD is not set
509CONFIG_SATA_PMP=y 537CONFIG_SATA_PMP=y
@@ -571,12 +599,15 @@ CONFIG_PATA_ALI=y
571# 599#
572# IEEE 1394 (FireWire) support 600# IEEE 1394 (FireWire) support
573# 601#
602
603#
604# Enable only one of the two stacks, unless you know what you are doing
605#
574# CONFIG_FIREWIRE is not set 606# CONFIG_FIREWIRE is not set
575# CONFIG_IEEE1394 is not set 607# CONFIG_IEEE1394 is not set
576# CONFIG_I2O is not set 608# CONFIG_I2O is not set
577# CONFIG_MACINTOSH_DRIVERS is not set 609# CONFIG_MACINTOSH_DRIVERS is not set
578CONFIG_NETDEVICES=y 610CONFIG_NETDEVICES=y
579# CONFIG_NETDEVICES_MULTIQUEUE is not set
580CONFIG_DUMMY=y 611CONFIG_DUMMY=y
581# CONFIG_BONDING is not set 612# CONFIG_BONDING is not set
582# CONFIG_MACVLAN is not set 613# CONFIG_MACVLAN is not set
@@ -603,6 +634,8 @@ CONFIG_VITESSE_PHY=y
603# CONFIG_MDIO_BITBANG is not set 634# CONFIG_MDIO_BITBANG is not set
604CONFIG_NET_ETHERNET=y 635CONFIG_NET_ETHERNET=y
605CONFIG_MII=y 636CONFIG_MII=y
637# CONFIG_MACE is not set
638# CONFIG_BMAC is not set
606# CONFIG_HAPPYMEAL is not set 639# CONFIG_HAPPYMEAL is not set
607# CONFIG_SUNGEM is not set 640# CONFIG_SUNGEM is not set
608# CONFIG_CASSINI is not set 641# CONFIG_CASSINI is not set
@@ -620,7 +653,6 @@ CONFIG_NETDEV_1000=y
620# CONFIG_DL2K is not set 653# CONFIG_DL2K is not set
621# CONFIG_E1000 is not set 654# CONFIG_E1000 is not set
622# CONFIG_E1000E is not set 655# CONFIG_E1000E is not set
623# CONFIG_E1000E_ENABLED is not set
624# CONFIG_IP1000 is not set 656# CONFIG_IP1000 is not set
625# CONFIG_IGB is not set 657# CONFIG_IGB is not set
626# CONFIG_NS83820 is not set 658# CONFIG_NS83820 is not set
@@ -634,9 +666,10 @@ CONFIG_NETDEV_1000=y
634# CONFIG_TIGON3 is not set 666# CONFIG_TIGON3 is not set
635# CONFIG_BNX2 is not set 667# CONFIG_BNX2 is not set
636CONFIG_GIANFAR=y 668CONFIG_GIANFAR=y
637CONFIG_GFAR_NAPI=y 669# CONFIG_MV643XX_ETH is not set
638# CONFIG_QLA3XXX is not set 670# CONFIG_QLA3XXX is not set
639# CONFIG_ATL1 is not set 671# CONFIG_ATL1 is not set
672# CONFIG_ATL1E is not set
640CONFIG_NETDEV_10000=y 673CONFIG_NETDEV_10000=y
641# CONFIG_CHELSIO_T1 is not set 674# CONFIG_CHELSIO_T1 is not set
642# CONFIG_CHELSIO_T3 is not set 675# CONFIG_CHELSIO_T3 is not set
@@ -713,12 +746,14 @@ CONFIG_SERIO_SERPORT=y
713# CONFIG_SERIO_PCIPS2 is not set 746# CONFIG_SERIO_PCIPS2 is not set
714CONFIG_SERIO_LIBPS2=y 747CONFIG_SERIO_LIBPS2=y
715# CONFIG_SERIO_RAW is not set 748# CONFIG_SERIO_RAW is not set
749# CONFIG_SERIO_XILINX_XPS_PS2 is not set
716# CONFIG_GAMEPORT is not set 750# CONFIG_GAMEPORT is not set
717 751
718# 752#
719# Character devices 753# Character devices
720# 754#
721CONFIG_VT=y 755CONFIG_VT=y
756CONFIG_CONSOLE_TRANSLATIONS=y
722CONFIG_VT_CONSOLE=y 757CONFIG_VT_CONSOLE=y
723CONFIG_HW_CONSOLE=y 758CONFIG_HW_CONSOLE=y
724# CONFIG_VT_HW_CONSOLE_BINDING is not set 759# CONFIG_VT_HW_CONSOLE_BINDING is not set
@@ -746,11 +781,14 @@ CONFIG_SERIAL_8250_RSA=y
746# CONFIG_SERIAL_UARTLITE is not set 781# CONFIG_SERIAL_UARTLITE is not set
747CONFIG_SERIAL_CORE=y 782CONFIG_SERIAL_CORE=y
748CONFIG_SERIAL_CORE_CONSOLE=y 783CONFIG_SERIAL_CORE_CONSOLE=y
784# CONFIG_SERIAL_PMACZILOG is not set
749# CONFIG_SERIAL_JSM is not set 785# CONFIG_SERIAL_JSM is not set
750# CONFIG_SERIAL_OF_PLATFORM is not set 786# CONFIG_SERIAL_OF_PLATFORM is not set
751CONFIG_UNIX98_PTYS=y 787CONFIG_UNIX98_PTYS=y
752CONFIG_LEGACY_PTYS=y 788CONFIG_LEGACY_PTYS=y
753CONFIG_LEGACY_PTY_COUNT=256 789CONFIG_LEGACY_PTY_COUNT=256
790# CONFIG_BRIQ_PANEL is not set
791# CONFIG_HVC_RTAS is not set
754# CONFIG_IPMI_HANDLER is not set 792# CONFIG_IPMI_HANDLER is not set
755# CONFIG_HW_RANDOM is not set 793# CONFIG_HW_RANDOM is not set
756CONFIG_NVRAM=y 794CONFIG_NVRAM=y
@@ -762,43 +800,70 @@ CONFIG_DEVPORT=y
762CONFIG_I2C=y 800CONFIG_I2C=y
763CONFIG_I2C_BOARDINFO=y 801CONFIG_I2C_BOARDINFO=y
764# CONFIG_I2C_CHARDEV is not set 802# CONFIG_I2C_CHARDEV is not set
803CONFIG_I2C_HELPER_AUTO=y
765 804
766# 805#
767# I2C Hardware Bus support 806# I2C Hardware Bus support
768# 807#
808
809#
810# PC SMBus host controller drivers
811#
769# CONFIG_I2C_ALI1535 is not set 812# CONFIG_I2C_ALI1535 is not set
770# CONFIG_I2C_ALI1563 is not set 813# CONFIG_I2C_ALI1563 is not set
771# CONFIG_I2C_ALI15X3 is not set 814# CONFIG_I2C_ALI15X3 is not set
772# CONFIG_I2C_AMD756 is not set 815# CONFIG_I2C_AMD756 is not set
773# CONFIG_I2C_AMD8111 is not set 816# CONFIG_I2C_AMD8111 is not set
774# CONFIG_I2C_I801 is not set 817# CONFIG_I2C_I801 is not set
775# CONFIG_I2C_I810 is not set 818# CONFIG_I2C_ISCH is not set
776# CONFIG_I2C_PIIX4 is not set 819# CONFIG_I2C_PIIX4 is not set
777CONFIG_I2C_MPC=y
778# CONFIG_I2C_NFORCE2 is not set 820# CONFIG_I2C_NFORCE2 is not set
779# CONFIG_I2C_OCORES is not set
780# CONFIG_I2C_PARPORT_LIGHT is not set
781# CONFIG_I2C_PROSAVAGE is not set
782# CONFIG_I2C_SAVAGE4 is not set
783# CONFIG_I2C_SIMTEC is not set
784# CONFIG_I2C_SIS5595 is not set 821# CONFIG_I2C_SIS5595 is not set
785# CONFIG_I2C_SIS630 is not set 822# CONFIG_I2C_SIS630 is not set
786# CONFIG_I2C_SIS96X is not set 823# CONFIG_I2C_SIS96X is not set
787# CONFIG_I2C_TAOS_EVM is not set
788# CONFIG_I2C_STUB is not set
789# CONFIG_I2C_TINY_USB is not set
790# CONFIG_I2C_VIA is not set 824# CONFIG_I2C_VIA is not set
791# CONFIG_I2C_VIAPRO is not set 825# CONFIG_I2C_VIAPRO is not set
826
827#
828# Mac SMBus host controller drivers
829#
830# CONFIG_I2C_HYDRA is not set
831CONFIG_I2C_POWERMAC=y
832
833#
834# I2C system bus drivers (mostly embedded / system-on-chip)
835#
836CONFIG_I2C_MPC=y
837# CONFIG_I2C_OCORES is not set
838# CONFIG_I2C_SIMTEC is not set
839
840#
841# External I2C/SMBus adapter drivers
842#
843# CONFIG_I2C_PARPORT_LIGHT is not set
844# CONFIG_I2C_TAOS_EVM is not set
845# CONFIG_I2C_TINY_USB is not set
846
847#
848# Graphics adapter I2C/DDC channel drivers
849#
792# CONFIG_I2C_VOODOO3 is not set 850# CONFIG_I2C_VOODOO3 is not set
851
852#
853# Other I2C/SMBus bus drivers
854#
793# CONFIG_I2C_PCA_PLATFORM is not set 855# CONFIG_I2C_PCA_PLATFORM is not set
856# CONFIG_I2C_STUB is not set
794 857
795# 858#
796# Miscellaneous I2C Chip support 859# Miscellaneous I2C Chip support
797# 860#
798# CONFIG_DS1682 is not set 861# CONFIG_DS1682 is not set
862# CONFIG_AT24 is not set
799CONFIG_SENSORS_EEPROM=y 863CONFIG_SENSORS_EEPROM=y
800# CONFIG_SENSORS_PCF8574 is not set 864# CONFIG_SENSORS_PCF8574 is not set
801# CONFIG_PCF8575 is not set 865# CONFIG_PCF8575 is not set
866# CONFIG_SENSORS_PCA9539 is not set
802# CONFIG_SENSORS_PCF8591 is not set 867# CONFIG_SENSORS_PCF8591 is not set
803# CONFIG_SENSORS_MAX6875 is not set 868# CONFIG_SENSORS_MAX6875 is not set
804# CONFIG_SENSORS_TSL2550 is not set 869# CONFIG_SENSORS_TSL2550 is not set
@@ -807,10 +872,13 @@ CONFIG_SENSORS_EEPROM=y
807# CONFIG_I2C_DEBUG_BUS is not set 872# CONFIG_I2C_DEBUG_BUS is not set
808# CONFIG_I2C_DEBUG_CHIP is not set 873# CONFIG_I2C_DEBUG_CHIP is not set
809# CONFIG_SPI is not set 874# CONFIG_SPI is not set
875CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
876# CONFIG_GPIOLIB is not set
810# CONFIG_W1 is not set 877# CONFIG_W1 is not set
811# CONFIG_POWER_SUPPLY is not set 878# CONFIG_POWER_SUPPLY is not set
812# CONFIG_HWMON is not set 879# CONFIG_HWMON is not set
813# CONFIG_THERMAL is not set 880# CONFIG_THERMAL is not set
881# CONFIG_THERMAL_HWMON is not set
814# CONFIG_WATCHDOG is not set 882# CONFIG_WATCHDOG is not set
815 883
816# 884#
@@ -822,8 +890,10 @@ CONFIG_SSB_POSSIBLE=y
822# 890#
823# Multifunction device drivers 891# Multifunction device drivers
824# 892#
893# CONFIG_MFD_CORE is not set
825# CONFIG_MFD_SM501 is not set 894# CONFIG_MFD_SM501 is not set
826# CONFIG_HTC_PASIC3 is not set 895# CONFIG_HTC_PASIC3 is not set
896# CONFIG_MFD_TMIO is not set
827 897
828# 898#
829# Multimedia devices 899# Multimedia devices
@@ -865,6 +935,7 @@ CONFIG_DVB_CAPTURE_DRIVERS=y
865# CONFIG_DVB_TTUSB_BUDGET is not set 935# CONFIG_DVB_TTUSB_BUDGET is not set
866# CONFIG_DVB_TTUSB_DEC is not set 936# CONFIG_DVB_TTUSB_DEC is not set
867# CONFIG_DVB_CINERGYT2 is not set 937# CONFIG_DVB_CINERGYT2 is not set
938# CONFIG_DVB_SIANO_SMS1XXX is not set
868 939
869# 940#
870# Supported FlexCopII (B2C2) Adapters 941# Supported FlexCopII (B2C2) Adapters
@@ -911,6 +982,7 @@ CONFIG_DVB_CAPTURE_DRIVERS=y
911# CONFIG_DVB_SP887X is not set 982# CONFIG_DVB_SP887X is not set
912# CONFIG_DVB_CX22700 is not set 983# CONFIG_DVB_CX22700 is not set
913# CONFIG_DVB_CX22702 is not set 984# CONFIG_DVB_CX22702 is not set
985# CONFIG_DVB_DRX397XD is not set
914# CONFIG_DVB_L64781 is not set 986# CONFIG_DVB_L64781 is not set
915# CONFIG_DVB_TDA1004X is not set 987# CONFIG_DVB_TDA1004X is not set
916# CONFIG_DVB_NXT6000 is not set 988# CONFIG_DVB_NXT6000 is not set
@@ -978,15 +1050,7 @@ CONFIG_VIDEO_OUTPUT_CONTROL=y
978CONFIG_VGA_CONSOLE=y 1050CONFIG_VGA_CONSOLE=y
979# CONFIG_VGACON_SOFT_SCROLLBACK is not set 1051# CONFIG_VGACON_SOFT_SCROLLBACK is not set
980CONFIG_DUMMY_CONSOLE=y 1052CONFIG_DUMMY_CONSOLE=y
981
982#
983# Sound
984#
985CONFIG_SOUND=y 1053CONFIG_SOUND=y
986
987#
988# Advanced Linux Sound Architecture
989#
990CONFIG_SND=y 1054CONFIG_SND=y
991CONFIG_SND_TIMER=y 1055CONFIG_SND_TIMER=y
992CONFIG_SND_PCM=y 1056CONFIG_SND_PCM=y
@@ -1000,19 +1064,15 @@ CONFIG_SND_PCM_OSS_PLUGINS=y
1000CONFIG_SND_VERBOSE_PROCFS=y 1064CONFIG_SND_VERBOSE_PROCFS=y
1001# CONFIG_SND_VERBOSE_PRINTK is not set 1065# CONFIG_SND_VERBOSE_PRINTK is not set
1002# CONFIG_SND_DEBUG is not set 1066# CONFIG_SND_DEBUG is not set
1003 1067CONFIG_SND_VMASTER=y
1004#
1005# Generic devices
1006#
1007CONFIG_SND_AC97_CODEC=y 1068CONFIG_SND_AC97_CODEC=y
1069CONFIG_SND_DRIVERS=y
1008# CONFIG_SND_DUMMY is not set 1070# CONFIG_SND_DUMMY is not set
1009# CONFIG_SND_MTPAV is not set 1071# CONFIG_SND_MTPAV is not set
1010# CONFIG_SND_SERIAL_U16550 is not set 1072# CONFIG_SND_SERIAL_U16550 is not set
1011# CONFIG_SND_MPU401 is not set 1073# CONFIG_SND_MPU401 is not set
1012 1074# CONFIG_SND_AC97_POWER_SAVE is not set
1013# 1075CONFIG_SND_PCI=y
1014# PCI devices
1015#
1016# CONFIG_SND_AD1889 is not set 1076# CONFIG_SND_AD1889 is not set
1017# CONFIG_SND_ALS300 is not set 1077# CONFIG_SND_ALS300 is not set
1018# CONFIG_SND_ALS4000 is not set 1078# CONFIG_SND_ALS4000 is not set
@@ -1074,39 +1134,14 @@ CONFIG_SND_INTEL8X0=y
1074# CONFIG_SND_VIRTUOSO is not set 1134# CONFIG_SND_VIRTUOSO is not set
1075# CONFIG_SND_VX222 is not set 1135# CONFIG_SND_VX222 is not set
1076# CONFIG_SND_YMFPCI is not set 1136# CONFIG_SND_YMFPCI is not set
1077# CONFIG_SND_AC97_POWER_SAVE is not set 1137CONFIG_SND_PPC=y
1078 1138# CONFIG_SND_POWERMAC is not set
1079# 1139# CONFIG_SND_AOA is not set
1080# ALSA PowerMac devices 1140CONFIG_SND_USB=y
1081#
1082
1083#
1084# ALSA PowerPC devices
1085#
1086
1087#
1088# USB devices
1089#
1090# CONFIG_SND_USB_AUDIO is not set 1141# CONFIG_SND_USB_AUDIO is not set
1091# CONFIG_SND_USB_USX2Y is not set 1142# CONFIG_SND_USB_USX2Y is not set
1092# CONFIG_SND_USB_CAIAQ is not set 1143# CONFIG_SND_USB_CAIAQ is not set
1093
1094#
1095# System on Chip audio support
1096#
1097# CONFIG_SND_SOC is not set 1144# CONFIG_SND_SOC is not set
1098
1099#
1100# ALSA SoC audio for Freescale SOCs
1101#
1102
1103#
1104# SoC Audio for the Texas Instruments OMAP
1105#
1106
1107#
1108# Open Sound System
1109#
1110# CONFIG_SOUND_PRIME is not set 1145# CONFIG_SOUND_PRIME is not set
1111CONFIG_AC97_BUS=y 1146CONFIG_AC97_BUS=y
1112CONFIG_HID_SUPPORT=y 1147CONFIG_HID_SUPPORT=y
@@ -1138,6 +1173,7 @@ CONFIG_USB_DEVICE_CLASS=y
1138# CONFIG_USB_OTG is not set 1173# CONFIG_USB_OTG is not set
1139# CONFIG_USB_OTG_WHITELIST is not set 1174# CONFIG_USB_OTG_WHITELIST is not set
1140# CONFIG_USB_OTG_BLACKLIST_HUB is not set 1175# CONFIG_USB_OTG_BLACKLIST_HUB is not set
1176CONFIG_USB_MON=y
1141 1177
1142# 1178#
1143# USB Host Controller Drivers 1179# USB Host Controller Drivers
@@ -1189,6 +1225,7 @@ CONFIG_USB_STORAGE=y
1189# CONFIG_USB_STORAGE_ALAUDA is not set 1225# CONFIG_USB_STORAGE_ALAUDA is not set
1190# CONFIG_USB_STORAGE_ONETOUCH is not set 1226# CONFIG_USB_STORAGE_ONETOUCH is not set
1191# CONFIG_USB_STORAGE_KARMA is not set 1227# CONFIG_USB_STORAGE_KARMA is not set
1228# CONFIG_USB_STORAGE_SIERRA is not set
1192# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set 1229# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
1193# CONFIG_USB_LIBUSUAL is not set 1230# CONFIG_USB_LIBUSUAL is not set
1194 1231
@@ -1197,7 +1234,6 @@ CONFIG_USB_STORAGE=y
1197# 1234#
1198# CONFIG_USB_MDC800 is not set 1235# CONFIG_USB_MDC800 is not set
1199# CONFIG_USB_MICROTEK is not set 1236# CONFIG_USB_MICROTEK is not set
1200CONFIG_USB_MON=y
1201 1237
1202# 1238#
1203# USB port drivers 1239# USB port drivers
@@ -1210,7 +1246,6 @@ CONFIG_USB_MON=y
1210# CONFIG_USB_EMI62 is not set 1246# CONFIG_USB_EMI62 is not set
1211# CONFIG_USB_EMI26 is not set 1247# CONFIG_USB_EMI26 is not set
1212# CONFIG_USB_ADUTUX is not set 1248# CONFIG_USB_ADUTUX is not set
1213# CONFIG_USB_AUERSWALD is not set
1214# CONFIG_USB_RIO500 is not set 1249# CONFIG_USB_RIO500 is not set
1215# CONFIG_USB_LEGOTOWER is not set 1250# CONFIG_USB_LEGOTOWER is not set
1216# CONFIG_USB_LCD is not set 1251# CONFIG_USB_LCD is not set
@@ -1264,6 +1299,7 @@ CONFIG_RTC_INTF_DEV=y
1264# CONFIG_RTC_DRV_PCF8583 is not set 1299# CONFIG_RTC_DRV_PCF8583 is not set
1265# CONFIG_RTC_DRV_M41T80 is not set 1300# CONFIG_RTC_DRV_M41T80 is not set
1266# CONFIG_RTC_DRV_S35390A is not set 1301# CONFIG_RTC_DRV_S35390A is not set
1302# CONFIG_RTC_DRV_FM3130 is not set
1267 1303
1268# 1304#
1269# SPI RTC drivers 1305# SPI RTC drivers
@@ -1362,6 +1398,7 @@ CONFIG_EFS_FS=m
1362CONFIG_CRAMFS=y 1398CONFIG_CRAMFS=y
1363CONFIG_VXFS_FS=m 1399CONFIG_VXFS_FS=m
1364# CONFIG_MINIX_FS is not set 1400# CONFIG_MINIX_FS is not set
1401# CONFIG_OMFS_FS is not set
1365CONFIG_HPFS_FS=m 1402CONFIG_HPFS_FS=m
1366CONFIG_QNX4FS_FS=m 1403CONFIG_QNX4FS_FS=m
1367# CONFIG_ROMFS_FS is not set 1404# CONFIG_ROMFS_FS is not set
@@ -1374,17 +1411,16 @@ CONFIG_NFS_FS=y
1374CONFIG_NFS_V3=y 1411CONFIG_NFS_V3=y
1375# CONFIG_NFS_V3_ACL is not set 1412# CONFIG_NFS_V3_ACL is not set
1376CONFIG_NFS_V4=y 1413CONFIG_NFS_V4=y
1414CONFIG_ROOT_NFS=y
1377CONFIG_NFSD=y 1415CONFIG_NFSD=y
1378# CONFIG_NFSD_V3 is not set 1416# CONFIG_NFSD_V3 is not set
1379# CONFIG_NFSD_V4 is not set 1417# CONFIG_NFSD_V4 is not set
1380CONFIG_ROOT_NFS=y
1381CONFIG_LOCKD=y 1418CONFIG_LOCKD=y
1382CONFIG_LOCKD_V4=y 1419CONFIG_LOCKD_V4=y
1383CONFIG_EXPORTFS=y 1420CONFIG_EXPORTFS=y
1384CONFIG_NFS_COMMON=y 1421CONFIG_NFS_COMMON=y
1385CONFIG_SUNRPC=y 1422CONFIG_SUNRPC=y
1386CONFIG_SUNRPC_GSS=y 1423CONFIG_SUNRPC_GSS=y
1387# CONFIG_SUNRPC_BIND34 is not set
1388CONFIG_RPCSEC_GSS_KRB5=y 1424CONFIG_RPCSEC_GSS_KRB5=y
1389# CONFIG_RPCSEC_GSS_SPKM3 is not set 1425# CONFIG_RPCSEC_GSS_SPKM3 is not set
1390# CONFIG_SMB_FS is not set 1426# CONFIG_SMB_FS is not set
@@ -1463,6 +1499,7 @@ CONFIG_BITREVERSE=y
1463# CONFIG_GENERIC_FIND_FIRST_BIT is not set 1499# CONFIG_GENERIC_FIND_FIRST_BIT is not set
1464# CONFIG_CRC_CCITT is not set 1500# CONFIG_CRC_CCITT is not set
1465# CONFIG_CRC16 is not set 1501# CONFIG_CRC16 is not set
1502CONFIG_CRC_T10DIF=y
1466CONFIG_CRC_ITU_T=m 1503CONFIG_CRC_ITU_T=m
1467CONFIG_CRC32=y 1504CONFIG_CRC32=y
1468# CONFIG_CRC7 is not set 1505# CONFIG_CRC7 is not set
@@ -1488,6 +1525,8 @@ CONFIG_FRAME_WARN=1024
1488CONFIG_DEBUG_KERNEL=y 1525CONFIG_DEBUG_KERNEL=y
1489# CONFIG_DEBUG_SHIRQ is not set 1526# CONFIG_DEBUG_SHIRQ is not set
1490CONFIG_DETECT_SOFTLOCKUP=y 1527CONFIG_DETECT_SOFTLOCKUP=y
1528# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
1529CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
1491CONFIG_SCHED_DEBUG=y 1530CONFIG_SCHED_DEBUG=y
1492# CONFIG_SCHEDSTATS is not set 1531# CONFIG_SCHEDSTATS is not set
1493# CONFIG_TIMER_STATS is not set 1532# CONFIG_TIMER_STATS is not set
@@ -1506,19 +1545,32 @@ CONFIG_SCHED_DEBUG=y
1506CONFIG_DEBUG_INFO=y 1545CONFIG_DEBUG_INFO=y
1507# CONFIG_DEBUG_VM is not set 1546# CONFIG_DEBUG_VM is not set
1508# CONFIG_DEBUG_WRITECOUNT is not set 1547# CONFIG_DEBUG_WRITECOUNT is not set
1548# CONFIG_DEBUG_MEMORY_INIT is not set
1509# CONFIG_DEBUG_LIST is not set 1549# CONFIG_DEBUG_LIST is not set
1510# CONFIG_DEBUG_SG is not set 1550# CONFIG_DEBUG_SG is not set
1511# CONFIG_BOOT_PRINTK_DELAY is not set 1551# CONFIG_BOOT_PRINTK_DELAY is not set
1512# CONFIG_RCU_TORTURE_TEST is not set 1552# CONFIG_RCU_TORTURE_TEST is not set
1513# CONFIG_BACKTRACE_SELF_TEST is not set 1553# CONFIG_BACKTRACE_SELF_TEST is not set
1514# CONFIG_FAULT_INJECTION is not set 1554# CONFIG_FAULT_INJECTION is not set
1555# CONFIG_LATENCYTOP is not set
1556CONFIG_SYSCTL_SYSCALL_CHECK=y
1557CONFIG_HAVE_FTRACE=y
1558CONFIG_HAVE_DYNAMIC_FTRACE=y
1559# CONFIG_FTRACE is not set
1560# CONFIG_SCHED_TRACER is not set
1561# CONFIG_CONTEXT_SWITCH_TRACER is not set
1515# CONFIG_SAMPLES is not set 1562# CONFIG_SAMPLES is not set
1563CONFIG_HAVE_ARCH_KGDB=y
1564# CONFIG_KGDB is not set
1516# CONFIG_DEBUG_STACKOVERFLOW is not set 1565# CONFIG_DEBUG_STACKOVERFLOW is not set
1517# CONFIG_DEBUG_STACK_USAGE is not set 1566# CONFIG_DEBUG_STACK_USAGE is not set
1518# CONFIG_DEBUG_PAGEALLOC is not set 1567# CONFIG_DEBUG_PAGEALLOC is not set
1519# CONFIG_DEBUGGER is not set 1568# CONFIG_CODE_PATCHING_SELFTEST is not set
1569# CONFIG_FTR_FIXUP_SELFTEST is not set
1570# CONFIG_XMON is not set
1520# CONFIG_IRQSTACKS is not set 1571# CONFIG_IRQSTACKS is not set
1521# CONFIG_BDI_SWITCH is not set 1572# CONFIG_BDI_SWITCH is not set
1573# CONFIG_BOOTX_TEXT is not set
1522# CONFIG_PPC_EARLY_DEBUG is not set 1574# CONFIG_PPC_EARLY_DEBUG is not set
1523 1575
1524# 1576#
@@ -1573,6 +1625,10 @@ CONFIG_CRYPTO_HMAC=y
1573# CONFIG_CRYPTO_MD4 is not set 1625# CONFIG_CRYPTO_MD4 is not set
1574CONFIG_CRYPTO_MD5=y 1626CONFIG_CRYPTO_MD5=y
1575# CONFIG_CRYPTO_MICHAEL_MIC is not set 1627# CONFIG_CRYPTO_MICHAEL_MIC is not set
1628# CONFIG_CRYPTO_RMD128 is not set
1629# CONFIG_CRYPTO_RMD160 is not set
1630# CONFIG_CRYPTO_RMD256 is not set
1631# CONFIG_CRYPTO_RMD320 is not set
1576CONFIG_CRYPTO_SHA1=m 1632CONFIG_CRYPTO_SHA1=m
1577# CONFIG_CRYPTO_SHA256 is not set 1633# CONFIG_CRYPTO_SHA256 is not set
1578# CONFIG_CRYPTO_SHA512 is not set 1634# CONFIG_CRYPTO_SHA512 is not set
@@ -1605,5 +1661,6 @@ CONFIG_CRYPTO_DES=y
1605# CONFIG_CRYPTO_LZO is not set 1661# CONFIG_CRYPTO_LZO is not set
1606CONFIG_CRYPTO_HW=y 1662CONFIG_CRYPTO_HW=y
1607# CONFIG_CRYPTO_DEV_HIFN_795X is not set 1663# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1664# CONFIG_CRYPTO_DEV_TALITOS is not set
1608# CONFIG_PPC_CLOCK is not set 1665# CONFIG_PPC_CLOCK is not set
1609# CONFIG_VIRTUALIZATION is not set 1666# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/configs/mpc866_ads_defconfig b/arch/powerpc/configs/mpc866_ads_defconfig
index 46fffbcd3f99..1501c4336b3d 100644
--- a/arch/powerpc/configs/mpc866_ads_defconfig
+++ b/arch/powerpc/configs/mpc866_ads_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc5 3# Linux kernel version: 2.6.27-rc4
4# Mon Jun 9 08:52:16 2008 4# Thu Aug 21 00:52:11 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -29,6 +29,7 @@ CONFIG_GENERIC_HARDIRQS=y
29# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set 29# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
30CONFIG_IRQ_PER_CPU=y 30CONFIG_IRQ_PER_CPU=y
31CONFIG_STACKTRACE_SUPPORT=y 31CONFIG_STACKTRACE_SUPPORT=y
32CONFIG_HAVE_LATENCYTOP_SUPPORT=y
32CONFIG_LOCKDEP_SUPPORT=y 33CONFIG_LOCKDEP_SUPPORT=y
33CONFIG_RWSEM_XCHGADD_ALGORITHM=y 34CONFIG_RWSEM_XCHGADD_ALGORITHM=y
34CONFIG_ARCH_HAS_ILOG2_U32=y 35CONFIG_ARCH_HAS_ILOG2_U32=y
@@ -106,10 +107,16 @@ CONFIG_SLUB=y
106# CONFIG_PROFILING is not set 107# CONFIG_PROFILING is not set
107# CONFIG_MARKERS is not set 108# CONFIG_MARKERS is not set
108CONFIG_HAVE_OPROFILE=y 109CONFIG_HAVE_OPROFILE=y
110CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
111CONFIG_HAVE_IOREMAP_PROT=y
109CONFIG_HAVE_KPROBES=y 112CONFIG_HAVE_KPROBES=y
110CONFIG_HAVE_KRETPROBES=y 113CONFIG_HAVE_KRETPROBES=y
114CONFIG_HAVE_ARCH_TRACEHOOK=y
111# CONFIG_HAVE_DMA_ATTRS is not set 115# CONFIG_HAVE_DMA_ATTRS is not set
116# CONFIG_USE_GENERIC_SMP_HELPERS is not set
117CONFIG_HAVE_CLK=y
112CONFIG_PROC_PAGE_MONITOR=y 118CONFIG_PROC_PAGE_MONITOR=y
119# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
113CONFIG_SLABINFO=y 120CONFIG_SLABINFO=y
114CONFIG_RT_MUTEXES=y 121CONFIG_RT_MUTEXES=y
115# CONFIG_TINY_SHMEM is not set 122# CONFIG_TINY_SHMEM is not set
@@ -120,6 +127,7 @@ CONFIG_BLOCK=y
120# CONFIG_BLK_DEV_IO_TRACE is not set 127# CONFIG_BLK_DEV_IO_TRACE is not set
121# CONFIG_LSF is not set 128# CONFIG_LSF is not set
122# CONFIG_BLK_DEV_BSG is not set 129# CONFIG_BLK_DEV_BSG is not set
130# CONFIG_BLK_DEV_INTEGRITY is not set
123 131
124# 132#
125# IO Schedulers 133# IO Schedulers
@@ -138,8 +146,6 @@ CONFIG_CLASSIC_RCU=y
138# 146#
139# Platform support 147# Platform support
140# 148#
141# CONFIG_PPC_MPC512x is not set
142# CONFIG_PPC_MPC5121 is not set
143# CONFIG_PPC_CELL is not set 149# CONFIG_PPC_CELL is not set
144# CONFIG_PPC_CELL_NATIVE is not set 150# CONFIG_PPC_CELL_NATIVE is not set
145CONFIG_CPM1=y 151CONFIG_CPM1=y
@@ -157,6 +163,7 @@ CONFIG_MPC86XADS=y
157# Generic MPC8xx Options 163# Generic MPC8xx Options
158# 164#
159CONFIG_8xx_COPYBACK=y 165CONFIG_8xx_COPYBACK=y
166# CONFIG_8xx_GPIO is not set
160CONFIG_8xx_CPU6=y 167CONFIG_8xx_CPU6=y
161CONFIG_8xx_CPU15=y 168CONFIG_8xx_CPU15=y
162CONFIG_NO_UCODE_PATCH=y 169CONFIG_NO_UCODE_PATCH=y
@@ -175,7 +182,6 @@ CONFIG_NO_UCODE_PATCH=y
175# CONFIG_PPC_INDIRECT_IO is not set 182# CONFIG_PPC_INDIRECT_IO is not set
176# CONFIG_GENERIC_IOMAP is not set 183# CONFIG_GENERIC_IOMAP is not set
177# CONFIG_CPU_FREQ is not set 184# CONFIG_CPU_FREQ is not set
178CONFIG_PPC_CPM_NEW_BINDING=y
179# CONFIG_FSL_ULI1575 is not set 185# CONFIG_FSL_ULI1575 is not set
180CONFIG_CPM=y 186CONFIG_CPM=y
181 187
@@ -192,7 +198,7 @@ CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
192# CONFIG_HZ_300 is not set 198# CONFIG_HZ_300 is not set
193CONFIG_HZ_1000=y 199CONFIG_HZ_1000=y
194CONFIG_HZ=1000 200CONFIG_HZ=1000
195# CONFIG_SCHED_HRTICK is not set 201CONFIG_SCHED_HRTICK=y
196CONFIG_PREEMPT_NONE=y 202CONFIG_PREEMPT_NONE=y
197# CONFIG_PREEMPT_VOLUNTARY is not set 203# CONFIG_PREEMPT_VOLUNTARY is not set
198# CONFIG_PREEMPT is not set 204# CONFIG_PREEMPT is not set
@@ -215,6 +221,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
215# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set 221# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
216CONFIG_PAGEFLAGS_EXTENDED=y 222CONFIG_PAGEFLAGS_EXTENDED=y
217CONFIG_SPLIT_PTLOCK_CPUS=4 223CONFIG_SPLIT_PTLOCK_CPUS=4
224CONFIG_MIGRATION=y
218# CONFIG_RESOURCES_64BIT is not set 225# CONFIG_RESOURCES_64BIT is not set
219CONFIG_ZONE_DMA_FLAG=1 226CONFIG_ZONE_DMA_FLAG=1
220CONFIG_BOUNCE=y 227CONFIG_BOUNCE=y
@@ -222,6 +229,7 @@ CONFIG_VIRT_TO_BUS=y
222CONFIG_FORCE_MAX_ZONEORDER=11 229CONFIG_FORCE_MAX_ZONEORDER=11
223# CONFIG_PROC_DEVICETREE is not set 230# CONFIG_PROC_DEVICETREE is not set
224# CONFIG_CMDLINE_BOOL is not set 231# CONFIG_CMDLINE_BOOL is not set
232CONFIG_EXTRA_TARGETS=""
225# CONFIG_PM is not set 233# CONFIG_PM is not set
226# CONFIG_SECCOMP is not set 234# CONFIG_SECCOMP is not set
227CONFIG_ISA_DMA_API=y 235CONFIG_ISA_DMA_API=y
@@ -253,10 +261,6 @@ CONFIG_PHYSICAL_START=0x00000000
253CONFIG_TASK_SIZE=0x80000000 261CONFIG_TASK_SIZE=0x80000000
254CONFIG_CONSISTENT_START=0xfd000000 262CONFIG_CONSISTENT_START=0xfd000000
255CONFIG_CONSISTENT_SIZE=0x00200000 263CONFIG_CONSISTENT_SIZE=0x00200000
256
257#
258# Networking
259#
260CONFIG_NET=y 264CONFIG_NET=y
261 265
262# 266#
@@ -361,6 +365,7 @@ CONFIG_BLK_DEV_LOOP=y
361# CONFIG_BLK_DEV_RAM is not set 365# CONFIG_BLK_DEV_RAM is not set
362# CONFIG_CDROM_PKTCDVD is not set 366# CONFIG_CDROM_PKTCDVD is not set
363# CONFIG_ATA_OVER_ETH is not set 367# CONFIG_ATA_OVER_ETH is not set
368# CONFIG_BLK_DEV_HD is not set
364CONFIG_MISC_DEVICES=y 369CONFIG_MISC_DEVICES=y
365# CONFIG_EEPROM_93CX6 is not set 370# CONFIG_EEPROM_93CX6 is not set
366# CONFIG_ENCLOSURE_SERVICES is not set 371# CONFIG_ENCLOSURE_SERVICES is not set
@@ -378,7 +383,6 @@ CONFIG_HAVE_IDE=y
378# CONFIG_MD is not set 383# CONFIG_MD is not set
379# CONFIG_MACINTOSH_DRIVERS is not set 384# CONFIG_MACINTOSH_DRIVERS is not set
380CONFIG_NETDEVICES=y 385CONFIG_NETDEVICES=y
381# CONFIG_NETDEVICES_MULTIQUEUE is not set
382# CONFIG_DUMMY is not set 386# CONFIG_DUMMY is not set
383# CONFIG_BONDING is not set 387# CONFIG_BONDING is not set
384# CONFIG_MACVLAN is not set 388# CONFIG_MACVLAN is not set
@@ -414,7 +418,6 @@ CONFIG_FS_ENET_HAS_SCC=y
414CONFIG_FS_ENET_HAS_FEC=y 418CONFIG_FS_ENET_HAS_FEC=y
415CONFIG_FS_ENET_MDIO_FEC=y 419CONFIG_FS_ENET_MDIO_FEC=y
416CONFIG_NETDEV_1000=y 420CONFIG_NETDEV_1000=y
417# CONFIG_E1000E_ENABLED is not set
418# CONFIG_GIANFAR is not set 421# CONFIG_GIANFAR is not set
419CONFIG_NETDEV_10000=y 422CONFIG_NETDEV_10000=y
420 423
@@ -484,6 +487,7 @@ CONFIG_SERIO_I8042=y
484CONFIG_SERIO_SERPORT=y 487CONFIG_SERIO_SERPORT=y
485CONFIG_SERIO_LIBPS2=y 488CONFIG_SERIO_LIBPS2=y
486# CONFIG_SERIO_RAW is not set 489# CONFIG_SERIO_RAW is not set
490# CONFIG_SERIO_XILINX_XPS_PS2 is not set
487# CONFIG_GAMEPORT is not set 491# CONFIG_GAMEPORT is not set
488 492
489# 493#
@@ -524,6 +528,8 @@ CONFIG_GEN_RTC=y
524# CONFIG_TCG_TPM is not set 528# CONFIG_TCG_TPM is not set
525# CONFIG_I2C is not set 529# CONFIG_I2C is not set
526# CONFIG_SPI is not set 530# CONFIG_SPI is not set
531CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
532# CONFIG_GPIOLIB is not set
527# CONFIG_W1 is not set 533# CONFIG_W1 is not set
528# CONFIG_POWER_SUPPLY is not set 534# CONFIG_POWER_SUPPLY is not set
529CONFIG_HWMON=y 535CONFIG_HWMON=y
@@ -540,6 +546,7 @@ CONFIG_HWMON=y
540# CONFIG_SENSORS_W83627EHF is not set 546# CONFIG_SENSORS_W83627EHF is not set
541# CONFIG_HWMON_DEBUG_CHIP is not set 547# CONFIG_HWMON_DEBUG_CHIP is not set
542# CONFIG_THERMAL is not set 548# CONFIG_THERMAL is not set
549# CONFIG_THERMAL_HWMON is not set
543# CONFIG_WATCHDOG is not set 550# CONFIG_WATCHDOG is not set
544 551
545# 552#
@@ -551,8 +558,10 @@ CONFIG_SSB_POSSIBLE=y
551# 558#
552# Multifunction device drivers 559# Multifunction device drivers
553# 560#
561# CONFIG_MFD_CORE is not set
554# CONFIG_MFD_SM501 is not set 562# CONFIG_MFD_SM501 is not set
555# CONFIG_HTC_PASIC3 is not set 563# CONFIG_HTC_PASIC3 is not set
564# CONFIG_MFD_TMIO is not set
556 565
557# 566#
558# Multimedia devices 567# Multimedia devices
@@ -582,10 +591,6 @@ CONFIG_VIDEO_OUTPUT_CONTROL=y
582# Display device support 591# Display device support
583# 592#
584# CONFIG_DISPLAY_SUPPORT is not set 593# CONFIG_DISPLAY_SUPPORT is not set
585
586#
587# Sound
588#
589# CONFIG_SOUND is not set 594# CONFIG_SOUND is not set
590CONFIG_HID_SUPPORT=y 595CONFIG_HID_SUPPORT=y
591CONFIG_HID=y 596CONFIG_HID=y
@@ -599,6 +604,10 @@ CONFIG_USB_SUPPORT=y
599# CONFIG_USB_OTG_BLACKLIST_HUB is not set 604# CONFIG_USB_OTG_BLACKLIST_HUB is not set
600 605
601# 606#
607# Enable Host or Gadget support to see Inventra options
608#
609
610#
602# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 611# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
603# 612#
604# CONFIG_USB_GADGET is not set 613# CONFIG_USB_GADGET is not set
@@ -677,6 +686,7 @@ CONFIG_TMPFS=y
677CONFIG_CRAMFS=y 686CONFIG_CRAMFS=y
678# CONFIG_VXFS_FS is not set 687# CONFIG_VXFS_FS is not set
679# CONFIG_MINIX_FS is not set 688# CONFIG_MINIX_FS is not set
689# CONFIG_OMFS_FS is not set
680# CONFIG_HPFS_FS is not set 690# CONFIG_HPFS_FS is not set
681# CONFIG_QNX4FS_FS is not set 691# CONFIG_QNX4FS_FS is not set
682# CONFIG_ROMFS_FS is not set 692# CONFIG_ROMFS_FS is not set
@@ -687,13 +697,12 @@ CONFIG_NFS_FS=y
687CONFIG_NFS_V3=y 697CONFIG_NFS_V3=y
688# CONFIG_NFS_V3_ACL is not set 698# CONFIG_NFS_V3_ACL is not set
689# CONFIG_NFS_V4 is not set 699# CONFIG_NFS_V4 is not set
690# CONFIG_NFSD is not set
691CONFIG_ROOT_NFS=y 700CONFIG_ROOT_NFS=y
701# CONFIG_NFSD is not set
692CONFIG_LOCKD=y 702CONFIG_LOCKD=y
693CONFIG_LOCKD_V4=y 703CONFIG_LOCKD_V4=y
694CONFIG_NFS_COMMON=y 704CONFIG_NFS_COMMON=y
695CONFIG_SUNRPC=y 705CONFIG_SUNRPC=y
696# CONFIG_SUNRPC_BIND34 is not set
697# CONFIG_RPCSEC_GSS_KRB5 is not set 706# CONFIG_RPCSEC_GSS_KRB5 is not set
698# CONFIG_RPCSEC_GSS_SPKM3 is not set 707# CONFIG_RPCSEC_GSS_SPKM3 is not set
699# CONFIG_SMB_FS is not set 708# CONFIG_SMB_FS is not set
@@ -733,6 +742,7 @@ CONFIG_BITREVERSE=y
733# CONFIG_GENERIC_FIND_FIRST_BIT is not set 742# CONFIG_GENERIC_FIND_FIRST_BIT is not set
734CONFIG_CRC_CCITT=y 743CONFIG_CRC_CCITT=y
735# CONFIG_CRC16 is not set 744# CONFIG_CRC16 is not set
745# CONFIG_CRC_T10DIF is not set
736# CONFIG_CRC_ITU_T is not set 746# CONFIG_CRC_ITU_T is not set
737CONFIG_CRC32=y 747CONFIG_CRC32=y
738# CONFIG_CRC7 is not set 748# CONFIG_CRC7 is not set
@@ -758,7 +768,15 @@ CONFIG_FRAME_WARN=1024
758# CONFIG_DEBUG_KERNEL is not set 768# CONFIG_DEBUG_KERNEL is not set
759# CONFIG_SLUB_DEBUG_ON is not set 769# CONFIG_SLUB_DEBUG_ON is not set
760# CONFIG_SLUB_STATS is not set 770# CONFIG_SLUB_STATS is not set
771# CONFIG_DEBUG_MEMORY_INIT is not set
772# CONFIG_LATENCYTOP is not set
773CONFIG_HAVE_FTRACE=y
774CONFIG_HAVE_DYNAMIC_FTRACE=y
775# CONFIG_FTRACE is not set
776# CONFIG_SCHED_TRACER is not set
777# CONFIG_CONTEXT_SWITCH_TRACER is not set
761# CONFIG_SAMPLES is not set 778# CONFIG_SAMPLES is not set
779CONFIG_HAVE_ARCH_KGDB=y
762# CONFIG_IRQSTACKS is not set 780# CONFIG_IRQSTACKS is not set
763# CONFIG_PPC_EARLY_DEBUG is not set 781# CONFIG_PPC_EARLY_DEBUG is not set
764 782
@@ -810,6 +828,10 @@ CONFIG_CRYPTO=y
810# CONFIG_CRYPTO_MD4 is not set 828# CONFIG_CRYPTO_MD4 is not set
811# CONFIG_CRYPTO_MD5 is not set 829# CONFIG_CRYPTO_MD5 is not set
812# CONFIG_CRYPTO_MICHAEL_MIC is not set 830# CONFIG_CRYPTO_MICHAEL_MIC is not set
831# CONFIG_CRYPTO_RMD128 is not set
832# CONFIG_CRYPTO_RMD160 is not set
833# CONFIG_CRYPTO_RMD256 is not set
834# CONFIG_CRYPTO_RMD320 is not set
813# CONFIG_CRYPTO_SHA1 is not set 835# CONFIG_CRYPTO_SHA1 is not set
814# CONFIG_CRYPTO_SHA256 is not set 836# CONFIG_CRYPTO_SHA256 is not set
815# CONFIG_CRYPTO_SHA512 is not set 837# CONFIG_CRYPTO_SHA512 is not set
@@ -841,6 +863,7 @@ CONFIG_CRYPTO=y
841# CONFIG_CRYPTO_DEFLATE is not set 863# CONFIG_CRYPTO_DEFLATE is not set
842# CONFIG_CRYPTO_LZO is not set 864# CONFIG_CRYPTO_LZO is not set
843CONFIG_CRYPTO_HW=y 865CONFIG_CRYPTO_HW=y
844# CONFIG_PPC_CLOCK is not set 866# CONFIG_CRYPTO_DEV_TALITOS is not set
867CONFIG_PPC_CLOCK=y
845CONFIG_PPC_LIB_RHEAP=y 868CONFIG_PPC_LIB_RHEAP=y
846# CONFIG_VIRTUALIZATION is not set 869# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/configs/mpc885_ads_defconfig b/arch/powerpc/configs/mpc885_ads_defconfig
index 9df78973005e..fc3f6dc58126 100644
--- a/arch/powerpc/configs/mpc885_ads_defconfig
+++ b/arch/powerpc/configs/mpc885_ads_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc5 3# Linux kernel version: 2.6.27-rc4
4# Mon Jun 9 08:52:17 2008 4# Thu Aug 21 00:52:12 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -29,6 +29,7 @@ CONFIG_GENERIC_HARDIRQS=y
29# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set 29# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
30CONFIG_IRQ_PER_CPU=y 30CONFIG_IRQ_PER_CPU=y
31CONFIG_STACKTRACE_SUPPORT=y 31CONFIG_STACKTRACE_SUPPORT=y
32CONFIG_HAVE_LATENCYTOP_SUPPORT=y
32CONFIG_LOCKDEP_SUPPORT=y 33CONFIG_LOCKDEP_SUPPORT=y
33CONFIG_RWSEM_XCHGADD_ALGORITHM=y 34CONFIG_RWSEM_XCHGADD_ALGORITHM=y
34CONFIG_ARCH_HAS_ILOG2_U32=y 35CONFIG_ARCH_HAS_ILOG2_U32=y
@@ -108,10 +109,16 @@ CONFIG_SLUB=y
108# CONFIG_PROFILING is not set 109# CONFIG_PROFILING is not set
109# CONFIG_MARKERS is not set 110# CONFIG_MARKERS is not set
110CONFIG_HAVE_OPROFILE=y 111CONFIG_HAVE_OPROFILE=y
112CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
113CONFIG_HAVE_IOREMAP_PROT=y
111CONFIG_HAVE_KPROBES=y 114CONFIG_HAVE_KPROBES=y
112CONFIG_HAVE_KRETPROBES=y 115CONFIG_HAVE_KRETPROBES=y
116CONFIG_HAVE_ARCH_TRACEHOOK=y
113# CONFIG_HAVE_DMA_ATTRS is not set 117# CONFIG_HAVE_DMA_ATTRS is not set
118# CONFIG_USE_GENERIC_SMP_HELPERS is not set
119CONFIG_HAVE_CLK=y
114CONFIG_PROC_PAGE_MONITOR=y 120CONFIG_PROC_PAGE_MONITOR=y
121# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
115CONFIG_SLABINFO=y 122CONFIG_SLABINFO=y
116# CONFIG_TINY_SHMEM is not set 123# CONFIG_TINY_SHMEM is not set
117CONFIG_BASE_SMALL=1 124CONFIG_BASE_SMALL=1
@@ -121,6 +128,7 @@ CONFIG_BLOCK=y
121# CONFIG_BLK_DEV_IO_TRACE is not set 128# CONFIG_BLK_DEV_IO_TRACE is not set
122# CONFIG_LSF is not set 129# CONFIG_LSF is not set
123# CONFIG_BLK_DEV_BSG is not set 130# CONFIG_BLK_DEV_BSG is not set
131# CONFIG_BLK_DEV_INTEGRITY is not set
124 132
125# 133#
126# IO Schedulers 134# IO Schedulers
@@ -139,8 +147,6 @@ CONFIG_CLASSIC_RCU=y
139# 147#
140# Platform support 148# Platform support
141# 149#
142# CONFIG_PPC_MPC512x is not set
143# CONFIG_PPC_MPC5121 is not set
144# CONFIG_PPC_CELL is not set 150# CONFIG_PPC_CELL is not set
145# CONFIG_PPC_CELL_NATIVE is not set 151# CONFIG_PPC_CELL_NATIVE is not set
146CONFIG_CPM1=y 152CONFIG_CPM1=y
@@ -165,6 +171,7 @@ CONFIG_MPC8xx_SECOND_ETH_FEC2=y
165# Generic MPC8xx Options 171# Generic MPC8xx Options
166# 172#
167CONFIG_8xx_COPYBACK=y 173CONFIG_8xx_COPYBACK=y
174# CONFIG_8xx_GPIO is not set
168# CONFIG_8xx_CPU6 is not set 175# CONFIG_8xx_CPU6 is not set
169CONFIG_8xx_CPU15=y 176CONFIG_8xx_CPU15=y
170CONFIG_NO_UCODE_PATCH=y 177CONFIG_NO_UCODE_PATCH=y
@@ -183,7 +190,6 @@ CONFIG_NO_UCODE_PATCH=y
183# CONFIG_PPC_INDIRECT_IO is not set 190# CONFIG_PPC_INDIRECT_IO is not set
184# CONFIG_GENERIC_IOMAP is not set 191# CONFIG_GENERIC_IOMAP is not set
185# CONFIG_CPU_FREQ is not set 192# CONFIG_CPU_FREQ is not set
186CONFIG_PPC_CPM_NEW_BINDING=y
187# CONFIG_FSL_ULI1575 is not set 193# CONFIG_FSL_ULI1575 is not set
188CONFIG_CPM=y 194CONFIG_CPM=y
189 195
@@ -200,7 +206,7 @@ CONFIG_HZ_100=y
200# CONFIG_HZ_300 is not set 206# CONFIG_HZ_300 is not set
201# CONFIG_HZ_1000 is not set 207# CONFIG_HZ_1000 is not set
202CONFIG_HZ=100 208CONFIG_HZ=100
203# CONFIG_SCHED_HRTICK is not set 209CONFIG_SCHED_HRTICK=y
204CONFIG_PREEMPT_NONE=y 210CONFIG_PREEMPT_NONE=y
205# CONFIG_PREEMPT_VOLUNTARY is not set 211# CONFIG_PREEMPT_VOLUNTARY is not set
206# CONFIG_PREEMPT is not set 212# CONFIG_PREEMPT is not set
@@ -224,6 +230,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
224# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set 230# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
225CONFIG_PAGEFLAGS_EXTENDED=y 231CONFIG_PAGEFLAGS_EXTENDED=y
226CONFIG_SPLIT_PTLOCK_CPUS=4 232CONFIG_SPLIT_PTLOCK_CPUS=4
233CONFIG_MIGRATION=y
227# CONFIG_RESOURCES_64BIT is not set 234# CONFIG_RESOURCES_64BIT is not set
228CONFIG_ZONE_DMA_FLAG=1 235CONFIG_ZONE_DMA_FLAG=1
229CONFIG_BOUNCE=y 236CONFIG_BOUNCE=y
@@ -231,6 +238,7 @@ CONFIG_VIRT_TO_BUS=y
231CONFIG_FORCE_MAX_ZONEORDER=11 238CONFIG_FORCE_MAX_ZONEORDER=11
232CONFIG_PROC_DEVICETREE=y 239CONFIG_PROC_DEVICETREE=y
233# CONFIG_CMDLINE_BOOL is not set 240# CONFIG_CMDLINE_BOOL is not set
241CONFIG_EXTRA_TARGETS=""
234# CONFIG_PM is not set 242# CONFIG_PM is not set
235# CONFIG_SECCOMP is not set 243# CONFIG_SECCOMP is not set
236CONFIG_ISA_DMA_API=y 244CONFIG_ISA_DMA_API=y
@@ -263,10 +271,6 @@ CONFIG_PHYSICAL_START=0x00000000
263CONFIG_TASK_SIZE=0x80000000 271CONFIG_TASK_SIZE=0x80000000
264CONFIG_CONSISTENT_START=0xfd000000 272CONFIG_CONSISTENT_START=0xfd000000
265CONFIG_CONSISTENT_SIZE=0x00200000 273CONFIG_CONSISTENT_SIZE=0x00200000
266
267#
268# Networking
269#
270CONFIG_NET=y 274CONFIG_NET=y
271 275
272# 276#
@@ -453,7 +457,6 @@ CONFIG_HAVE_IDE=y
453# CONFIG_MD is not set 457# CONFIG_MD is not set
454# CONFIG_MACINTOSH_DRIVERS is not set 458# CONFIG_MACINTOSH_DRIVERS is not set
455CONFIG_NETDEVICES=y 459CONFIG_NETDEVICES=y
456# CONFIG_NETDEVICES_MULTIQUEUE is not set
457# CONFIG_DUMMY is not set 460# CONFIG_DUMMY is not set
458# CONFIG_BONDING is not set 461# CONFIG_BONDING is not set
459# CONFIG_MACVLAN is not set 462# CONFIG_MACVLAN is not set
@@ -555,10 +558,13 @@ CONFIG_GEN_RTC=y
555# CONFIG_TCG_TPM is not set 558# CONFIG_TCG_TPM is not set
556# CONFIG_I2C is not set 559# CONFIG_I2C is not set
557# CONFIG_SPI is not set 560# CONFIG_SPI is not set
561CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
562# CONFIG_GPIOLIB is not set
558# CONFIG_W1 is not set 563# CONFIG_W1 is not set
559# CONFIG_POWER_SUPPLY is not set 564# CONFIG_POWER_SUPPLY is not set
560# CONFIG_HWMON is not set 565# CONFIG_HWMON is not set
561# CONFIG_THERMAL is not set 566# CONFIG_THERMAL is not set
567# CONFIG_THERMAL_HWMON is not set
562# CONFIG_WATCHDOG is not set 568# CONFIG_WATCHDOG is not set
563 569
564# 570#
@@ -570,8 +576,10 @@ CONFIG_SSB_POSSIBLE=y
570# 576#
571# Multifunction device drivers 577# Multifunction device drivers
572# 578#
579# CONFIG_MFD_CORE is not set
573# CONFIG_MFD_SM501 is not set 580# CONFIG_MFD_SM501 is not set
574# CONFIG_HTC_PASIC3 is not set 581# CONFIG_HTC_PASIC3 is not set
582# CONFIG_MFD_TMIO is not set
575 583
576# 584#
577# Multimedia devices 585# Multimedia devices
@@ -601,10 +609,6 @@ CONFIG_DAB=y
601# Display device support 609# Display device support
602# 610#
603# CONFIG_DISPLAY_SUPPORT is not set 611# CONFIG_DISPLAY_SUPPORT is not set
604
605#
606# Sound
607#
608# CONFIG_SOUND is not set 612# CONFIG_SOUND is not set
609# CONFIG_USB_SUPPORT is not set 613# CONFIG_USB_SUPPORT is not set
610# CONFIG_MMC is not set 614# CONFIG_MMC is not set
@@ -673,6 +677,7 @@ CONFIG_TMPFS=y
673CONFIG_CRAMFS=y 677CONFIG_CRAMFS=y
674# CONFIG_VXFS_FS is not set 678# CONFIG_VXFS_FS is not set
675# CONFIG_MINIX_FS is not set 679# CONFIG_MINIX_FS is not set
680# CONFIG_OMFS_FS is not set
676# CONFIG_HPFS_FS is not set 681# CONFIG_HPFS_FS is not set
677# CONFIG_QNX4FS_FS is not set 682# CONFIG_QNX4FS_FS is not set
678# CONFIG_ROMFS_FS is not set 683# CONFIG_ROMFS_FS is not set
@@ -683,13 +688,12 @@ CONFIG_NFS_FS=y
683CONFIG_NFS_V3=y 688CONFIG_NFS_V3=y
684# CONFIG_NFS_V3_ACL is not set 689# CONFIG_NFS_V3_ACL is not set
685# CONFIG_NFS_V4 is not set 690# CONFIG_NFS_V4 is not set
686# CONFIG_NFSD is not set
687CONFIG_ROOT_NFS=y 691CONFIG_ROOT_NFS=y
692# CONFIG_NFSD is not set
688CONFIG_LOCKD=y 693CONFIG_LOCKD=y
689CONFIG_LOCKD_V4=y 694CONFIG_LOCKD_V4=y
690CONFIG_NFS_COMMON=y 695CONFIG_NFS_COMMON=y
691CONFIG_SUNRPC=y 696CONFIG_SUNRPC=y
692# CONFIG_SUNRPC_BIND34 is not set
693# CONFIG_RPCSEC_GSS_KRB5 is not set 697# CONFIG_RPCSEC_GSS_KRB5 is not set
694# CONFIG_RPCSEC_GSS_SPKM3 is not set 698# CONFIG_RPCSEC_GSS_SPKM3 is not set
695# CONFIG_SMB_FS is not set 699# CONFIG_SMB_FS is not set
@@ -728,6 +732,7 @@ CONFIG_MSDOS_PARTITION=y
728# CONFIG_GENERIC_FIND_FIRST_BIT is not set 732# CONFIG_GENERIC_FIND_FIRST_BIT is not set
729# CONFIG_CRC_CCITT is not set 733# CONFIG_CRC_CCITT is not set
730# CONFIG_CRC16 is not set 734# CONFIG_CRC16 is not set
735# CONFIG_CRC_T10DIF is not set
731# CONFIG_CRC_ITU_T is not set 736# CONFIG_CRC_ITU_T is not set
732# CONFIG_CRC32 is not set 737# CONFIG_CRC32 is not set
733# CONFIG_CRC7 is not set 738# CONFIG_CRC7 is not set
@@ -752,6 +757,8 @@ CONFIG_MAGIC_SYSRQ=y
752CONFIG_DEBUG_KERNEL=y 757CONFIG_DEBUG_KERNEL=y
753# CONFIG_DEBUG_SHIRQ is not set 758# CONFIG_DEBUG_SHIRQ is not set
754CONFIG_DETECT_SOFTLOCKUP=y 759CONFIG_DETECT_SOFTLOCKUP=y
760# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
761CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
755CONFIG_SCHED_DEBUG=y 762CONFIG_SCHED_DEBUG=y
756# CONFIG_SCHEDSTATS is not set 763# CONFIG_SCHEDSTATS is not set
757# CONFIG_TIMER_STATS is not set 764# CONFIG_TIMER_STATS is not set
@@ -767,16 +774,28 @@ CONFIG_DEBUG_BUGVERBOSE=y
767CONFIG_DEBUG_INFO=y 774CONFIG_DEBUG_INFO=y
768# CONFIG_DEBUG_VM is not set 775# CONFIG_DEBUG_VM is not set
769# CONFIG_DEBUG_WRITECOUNT is not set 776# CONFIG_DEBUG_WRITECOUNT is not set
777# CONFIG_DEBUG_MEMORY_INIT is not set
770# CONFIG_DEBUG_LIST is not set 778# CONFIG_DEBUG_LIST is not set
771# CONFIG_DEBUG_SG is not set 779# CONFIG_DEBUG_SG is not set
772# CONFIG_BOOT_PRINTK_DELAY is not set 780# CONFIG_BOOT_PRINTK_DELAY is not set
781# CONFIG_RCU_TORTURE_TEST is not set
773# CONFIG_BACKTRACE_SELF_TEST is not set 782# CONFIG_BACKTRACE_SELF_TEST is not set
774# CONFIG_FAULT_INJECTION is not set 783# CONFIG_FAULT_INJECTION is not set
784# CONFIG_LATENCYTOP is not set
785CONFIG_HAVE_FTRACE=y
786CONFIG_HAVE_DYNAMIC_FTRACE=y
787# CONFIG_FTRACE is not set
788# CONFIG_SCHED_TRACER is not set
789# CONFIG_CONTEXT_SWITCH_TRACER is not set
775# CONFIG_SAMPLES is not set 790# CONFIG_SAMPLES is not set
791CONFIG_HAVE_ARCH_KGDB=y
792# CONFIG_KGDB is not set
776# CONFIG_DEBUG_STACKOVERFLOW is not set 793# CONFIG_DEBUG_STACKOVERFLOW is not set
777# CONFIG_DEBUG_STACK_USAGE is not set 794# CONFIG_DEBUG_STACK_USAGE is not set
778# CONFIG_DEBUG_PAGEALLOC is not set 795# CONFIG_DEBUG_PAGEALLOC is not set
779# CONFIG_DEBUGGER is not set 796# CONFIG_CODE_PATCHING_SELFTEST is not set
797# CONFIG_FTR_FIXUP_SELFTEST is not set
798# CONFIG_XMON is not set
780# CONFIG_IRQSTACKS is not set 799# CONFIG_IRQSTACKS is not set
781# CONFIG_BDI_SWITCH is not set 800# CONFIG_BDI_SWITCH is not set
782# CONFIG_PPC_EARLY_DEBUG is not set 801# CONFIG_PPC_EARLY_DEBUG is not set
@@ -788,6 +807,6 @@ CONFIG_DEBUG_INFO=y
788# CONFIG_SECURITY is not set 807# CONFIG_SECURITY is not set
789# CONFIG_SECURITY_FILE_CAPABILITIES is not set 808# CONFIG_SECURITY_FILE_CAPABILITIES is not set
790# CONFIG_CRYPTO is not set 809# CONFIG_CRYPTO is not set
791# CONFIG_PPC_CLOCK is not set 810CONFIG_PPC_CLOCK=y
792CONFIG_PPC_LIB_RHEAP=y 811CONFIG_PPC_LIB_RHEAP=y
793# CONFIG_VIRTUALIZATION is not set 812# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/configs/pmac32_defconfig b/arch/powerpc/configs/pmac32_defconfig
index 3688e4bb6fc2..80481f270133 100644
--- a/arch/powerpc/configs/pmac32_defconfig
+++ b/arch/powerpc/configs/pmac32_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc3 3# Linux kernel version: 2.6.27-rc4
4# Tue May 20 20:02:24 2008 4# Tue Aug 26 13:20:26 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -32,6 +32,7 @@ CONFIG_GENERIC_HARDIRQS=y
32# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set 32# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
33CONFIG_IRQ_PER_CPU=y 33CONFIG_IRQ_PER_CPU=y
34CONFIG_STACKTRACE_SUPPORT=y 34CONFIG_STACKTRACE_SUPPORT=y
35CONFIG_HAVE_LATENCYTOP_SUPPORT=y
35CONFIG_LOCKDEP_SUPPORT=y 36CONFIG_LOCKDEP_SUPPORT=y
36CONFIG_RWSEM_XCHGADD_ALGORITHM=y 37CONFIG_RWSEM_XCHGADD_ALGORITHM=y
37CONFIG_ARCH_HAS_ILOG2_U32=y 38CONFIG_ARCH_HAS_ILOG2_U32=y
@@ -93,9 +94,8 @@ CONFIG_INITRAMFS_SOURCE=""
93CONFIG_SYSCTL=y 94CONFIG_SYSCTL=y
94# CONFIG_EMBEDDED is not set 95# CONFIG_EMBEDDED is not set
95CONFIG_SYSCTL_SYSCALL=y 96CONFIG_SYSCTL_SYSCALL=y
96CONFIG_SYSCTL_SYSCALL_CHECK=y
97CONFIG_KALLSYMS=y 97CONFIG_KALLSYMS=y
98# CONFIG_KALLSYMS_ALL is not set 98CONFIG_KALLSYMS_ALL=y
99# CONFIG_KALLSYMS_EXTRA_PASS is not set 99# CONFIG_KALLSYMS_EXTRA_PASS is not set
100CONFIG_HOTPLUG=y 100CONFIG_HOTPLUG=y
101CONFIG_PRINTK=y 101CONFIG_PRINTK=y
@@ -120,10 +120,16 @@ CONFIG_PROFILING=y
120CONFIG_OPROFILE=y 120CONFIG_OPROFILE=y
121CONFIG_HAVE_OPROFILE=y 121CONFIG_HAVE_OPROFILE=y
122# CONFIG_KPROBES is not set 122# CONFIG_KPROBES is not set
123CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
124CONFIG_HAVE_IOREMAP_PROT=y
123CONFIG_HAVE_KPROBES=y 125CONFIG_HAVE_KPROBES=y
124CONFIG_HAVE_KRETPROBES=y 126CONFIG_HAVE_KRETPROBES=y
127CONFIG_HAVE_ARCH_TRACEHOOK=y
125# CONFIG_HAVE_DMA_ATTRS is not set 128# CONFIG_HAVE_DMA_ATTRS is not set
129# CONFIG_USE_GENERIC_SMP_HELPERS is not set
130# CONFIG_HAVE_CLK is not set
126CONFIG_PROC_PAGE_MONITOR=y 131CONFIG_PROC_PAGE_MONITOR=y
132# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
127CONFIG_SLABINFO=y 133CONFIG_SLABINFO=y
128CONFIG_RT_MUTEXES=y 134CONFIG_RT_MUTEXES=y
129# CONFIG_TINY_SHMEM is not set 135# CONFIG_TINY_SHMEM is not set
@@ -140,6 +146,7 @@ CONFIG_LBD=y
140# CONFIG_BLK_DEV_IO_TRACE is not set 146# CONFIG_BLK_DEV_IO_TRACE is not set
141CONFIG_LSF=y 147CONFIG_LSF=y
142CONFIG_BLK_DEV_BSG=y 148CONFIG_BLK_DEV_BSG=y
149# CONFIG_BLK_DEV_INTEGRITY is not set
143 150
144# 151#
145# IO Schedulers 152# IO Schedulers
@@ -159,19 +166,18 @@ CONFIG_CLASSIC_RCU=y
159# Platform support 166# Platform support
160# 167#
161CONFIG_PPC_MULTIPLATFORM=y 168CONFIG_PPC_MULTIPLATFORM=y
162# CONFIG_PPC_82xx is not set
163# CONFIG_PPC_83xx is not set
164# CONFIG_PPC_86xx is not set
165CONFIG_CLASSIC32=y 169CONFIG_CLASSIC32=y
166# CONFIG_PPC_CHRP is not set 170# CONFIG_PPC_CHRP is not set
167# CONFIG_PPC_MPC512x is not set
168# CONFIG_PPC_MPC5121 is not set
169# CONFIG_MPC5121_ADS is not set 171# CONFIG_MPC5121_ADS is not set
172# CONFIG_MPC5121_GENERIC is not set
170# CONFIG_PPC_MPC52xx is not set 173# CONFIG_PPC_MPC52xx is not set
171CONFIG_PPC_PMAC=y 174CONFIG_PPC_PMAC=y
172# CONFIG_PPC_CELL is not set 175# CONFIG_PPC_CELL is not set
173# CONFIG_PPC_CELL_NATIVE is not set 176# CONFIG_PPC_CELL_NATIVE is not set
177# CONFIG_PPC_82xx is not set
174# CONFIG_PQ2ADS is not set 178# CONFIG_PQ2ADS is not set
179# CONFIG_PPC_83xx is not set
180# CONFIG_PPC_86xx is not set
175# CONFIG_EMBEDDED6xx is not set 181# CONFIG_EMBEDDED6xx is not set
176CONFIG_PPC_NATIVE=y 182CONFIG_PPC_NATIVE=y
177# CONFIG_IPIC is not set 183# CONFIG_IPIC is not set
@@ -221,7 +227,7 @@ CONFIG_HZ_250=y
221# CONFIG_HZ_300 is not set 227# CONFIG_HZ_300 is not set
222# CONFIG_HZ_1000 is not set 228# CONFIG_HZ_1000 is not set
223CONFIG_HZ=250 229CONFIG_HZ=250
224# CONFIG_SCHED_HRTICK is not set 230CONFIG_SCHED_HRTICK=y
225CONFIG_PREEMPT_NONE=y 231CONFIG_PREEMPT_NONE=y
226# CONFIG_PREEMPT_VOLUNTARY is not set 232# CONFIG_PREEMPT_VOLUNTARY is not set
227# CONFIG_PREEMPT is not set 233# CONFIG_PREEMPT is not set
@@ -244,6 +250,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
244# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set 250# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
245CONFIG_PAGEFLAGS_EXTENDED=y 251CONFIG_PAGEFLAGS_EXTENDED=y
246CONFIG_SPLIT_PTLOCK_CPUS=4 252CONFIG_SPLIT_PTLOCK_CPUS=4
253# CONFIG_MIGRATION is not set
247# CONFIG_RESOURCES_64BIT is not set 254# CONFIG_RESOURCES_64BIT is not set
248CONFIG_ZONE_DMA_FLAG=1 255CONFIG_ZONE_DMA_FLAG=1
249CONFIG_BOUNCE=y 256CONFIG_BOUNCE=y
@@ -251,6 +258,7 @@ CONFIG_VIRT_TO_BUS=y
251CONFIG_FORCE_MAX_ZONEORDER=11 258CONFIG_FORCE_MAX_ZONEORDER=11
252CONFIG_PROC_DEVICETREE=y 259CONFIG_PROC_DEVICETREE=y
253# CONFIG_CMDLINE_BOOL is not set 260# CONFIG_CMDLINE_BOOL is not set
261CONFIG_EXTRA_TARGETS=""
254CONFIG_ARCH_WANTS_FREEZER_CONTROL=y 262CONFIG_ARCH_WANTS_FREEZER_CONTROL=y
255CONFIG_PM=y 263CONFIG_PM=y
256CONFIG_PM_DEBUG=y 264CONFIG_PM_DEBUG=y
@@ -314,10 +322,6 @@ CONFIG_PAGE_OFFSET=0xc0000000
314CONFIG_KERNEL_START=0xc0000000 322CONFIG_KERNEL_START=0xc0000000
315CONFIG_PHYSICAL_START=0x00000000 323CONFIG_PHYSICAL_START=0x00000000
316CONFIG_TASK_SIZE=0xc0000000 324CONFIG_TASK_SIZE=0xc0000000
317
318#
319# Networking
320#
321CONFIG_NET=y 325CONFIG_NET=y
322 326
323# 327#
@@ -501,7 +505,6 @@ CONFIG_IP_DCCP_TFRC_LIB=m
501# CONFIG_WAN_ROUTER is not set 505# CONFIG_WAN_ROUTER is not set
502# CONFIG_NET_SCHED is not set 506# CONFIG_NET_SCHED is not set
503CONFIG_NET_CLS_ROUTE=y 507CONFIG_NET_CLS_ROUTE=y
504CONFIG_NET_SCH_FIFO=y
505 508
506# 509#
507# Network testing 510# Network testing
@@ -571,6 +574,7 @@ CONFIG_BT_HIDP=m
571# 574#
572CONFIG_BT_HCIUSB=m 575CONFIG_BT_HCIUSB=m
573# CONFIG_BT_HCIUSB_SCO is not set 576# CONFIG_BT_HCIUSB_SCO is not set
577# CONFIG_BT_HCIBTUSB is not set
574# CONFIG_BT_HCIUART is not set 578# CONFIG_BT_HCIUART is not set
575CONFIG_BT_HCIBCM203X=m 579CONFIG_BT_HCIBCM203X=m
576# CONFIG_BT_HCIBPA10X is not set 580# CONFIG_BT_HCIBPA10X is not set
@@ -588,27 +592,18 @@ CONFIG_BT_HCIBFUSB=m
588CONFIG_CFG80211=m 592CONFIG_CFG80211=m
589CONFIG_NL80211=y 593CONFIG_NL80211=y
590CONFIG_WIRELESS_EXT=y 594CONFIG_WIRELESS_EXT=y
595CONFIG_WIRELESS_EXT_SYSFS=y
591CONFIG_MAC80211=m 596CONFIG_MAC80211=m
592 597
593# 598#
594# Rate control algorithm selection 599# Rate control algorithm selection
595# 600#
601CONFIG_MAC80211_RC_PID=y
596CONFIG_MAC80211_RC_DEFAULT_PID=y 602CONFIG_MAC80211_RC_DEFAULT_PID=y
597# CONFIG_MAC80211_RC_DEFAULT_NONE is not set
598
599#
600# Selecting 'y' for an algorithm will
601#
602
603#
604# build the algorithm into mac80211.
605#
606CONFIG_MAC80211_RC_DEFAULT="pid" 603CONFIG_MAC80211_RC_DEFAULT="pid"
607CONFIG_MAC80211_RC_PID=y
608# CONFIG_MAC80211_MESH is not set 604# CONFIG_MAC80211_MESH is not set
609CONFIG_MAC80211_LEDS=y 605CONFIG_MAC80211_LEDS=y
610# CONFIG_MAC80211_DEBUG_PACKET_ALIGNMENT is not set 606# CONFIG_MAC80211_DEBUG_MENU is not set
611# CONFIG_MAC80211_DEBUG is not set
612CONFIG_IEEE80211=m 607CONFIG_IEEE80211=m
613# CONFIG_IEEE80211_DEBUG is not set 608# CONFIG_IEEE80211_DEBUG is not set
614CONFIG_IEEE80211_CRYPT_WEP=m 609CONFIG_IEEE80211_CRYPT_WEP=m
@@ -628,6 +623,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
628# CONFIG_STANDALONE is not set 623# CONFIG_STANDALONE is not set
629CONFIG_PREVENT_FIRMWARE_BUILD=y 624CONFIG_PREVENT_FIRMWARE_BUILD=y
630CONFIG_FW_LOADER=y 625CONFIG_FW_LOADER=y
626CONFIG_FIRMWARE_IN_KERNEL=y
627CONFIG_EXTRA_FIRMWARE=""
631# CONFIG_DEBUG_DRIVER is not set 628# CONFIG_DEBUG_DRIVER is not set
632# CONFIG_DEBUG_DEVRES is not set 629# CONFIG_DEBUG_DEVRES is not set
633# CONFIG_SYS_HYPERVISOR is not set 630# CONFIG_SYS_HYPERVISOR is not set
@@ -656,12 +653,14 @@ CONFIG_BLK_DEV_RAM_SIZE=4096
656# CONFIG_BLK_DEV_XIP is not set 653# CONFIG_BLK_DEV_XIP is not set
657# CONFIG_CDROM_PKTCDVD is not set 654# CONFIG_CDROM_PKTCDVD is not set
658# CONFIG_ATA_OVER_ETH is not set 655# CONFIG_ATA_OVER_ETH is not set
656# CONFIG_BLK_DEV_HD is not set
659CONFIG_MISC_DEVICES=y 657CONFIG_MISC_DEVICES=y
660# CONFIG_PHANTOM is not set 658# CONFIG_PHANTOM is not set
661# CONFIG_EEPROM_93CX6 is not set 659# CONFIG_EEPROM_93CX6 is not set
662# CONFIG_SGI_IOC4 is not set 660# CONFIG_SGI_IOC4 is not set
663# CONFIG_TIFM_CORE is not set 661# CONFIG_TIFM_CORE is not set
664# CONFIG_ENCLOSURE_SERVICES is not set 662# CONFIG_ENCLOSURE_SERVICES is not set
663# CONFIG_HP_ILO is not set
665CONFIG_HAVE_IDE=y 664CONFIG_HAVE_IDE=y
666CONFIG_IDE=y 665CONFIG_IDE=y
667CONFIG_BLK_DEV_IDE=y 666CONFIG_BLK_DEV_IDE=y
@@ -669,6 +668,8 @@ CONFIG_BLK_DEV_IDE=y
669# 668#
670# Please see Documentation/ide/ide.txt for help/info on IDE drives 669# Please see Documentation/ide/ide.txt for help/info on IDE drives
671# 670#
671CONFIG_IDE_TIMINGS=y
672CONFIG_IDE_ATAPI=y
672# CONFIG_BLK_DEV_IDE_SATA is not set 673# CONFIG_BLK_DEV_IDE_SATA is not set
673CONFIG_BLK_DEV_IDEDISK=y 674CONFIG_BLK_DEV_IDEDISK=y
674# CONFIG_IDEDISK_MULTI_MODE is not set 675# CONFIG_IDEDISK_MULTI_MODE is not set
@@ -685,7 +686,6 @@ CONFIG_IDE_PROC_FS=y
685# 686#
686# IDE chipset support/bugfixes 687# IDE chipset support/bugfixes
687# 688#
688# CONFIG_IDE_GENERIC is not set
689# CONFIG_BLK_DEV_PLATFORM is not set 689# CONFIG_BLK_DEV_PLATFORM is not set
690CONFIG_BLK_DEV_IDEDMA_SFF=y 690CONFIG_BLK_DEV_IDEDMA_SFF=y
691 691
@@ -703,10 +703,8 @@ CONFIG_BLK_DEV_IDEDMA_PCI=y
703# CONFIG_BLK_DEV_AMD74XX is not set 703# CONFIG_BLK_DEV_AMD74XX is not set
704# CONFIG_BLK_DEV_CMD64X is not set 704# CONFIG_BLK_DEV_CMD64X is not set
705# CONFIG_BLK_DEV_TRIFLEX is not set 705# CONFIG_BLK_DEV_TRIFLEX is not set
706# CONFIG_BLK_DEV_CY82C693 is not set
707# CONFIG_BLK_DEV_CS5520 is not set 706# CONFIG_BLK_DEV_CS5520 is not set
708# CONFIG_BLK_DEV_CS5530 is not set 707# CONFIG_BLK_DEV_CS5530 is not set
709# CONFIG_BLK_DEV_HPT34X is not set
710# CONFIG_BLK_DEV_HPT366 is not set 708# CONFIG_BLK_DEV_HPT366 is not set
711# CONFIG_BLK_DEV_JMICRON is not set 709# CONFIG_BLK_DEV_JMICRON is not set
712# CONFIG_BLK_DEV_SC1200 is not set 710# CONFIG_BLK_DEV_SC1200 is not set
@@ -727,8 +725,6 @@ CONFIG_BLK_DEV_IDE_PMAC=y
727CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST=y 725CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST=y
728CONFIG_BLK_DEV_IDEDMA_PMAC=y 726CONFIG_BLK_DEV_IDEDMA_PMAC=y
729CONFIG_BLK_DEV_IDEDMA=y 727CONFIG_BLK_DEV_IDEDMA=y
730# CONFIG_BLK_DEV_HD_ONLY is not set
731# CONFIG_BLK_DEV_HD is not set
732 728
733# 729#
734# SCSI device support 730# SCSI device support
@@ -820,6 +816,7 @@ CONFIG_SCSI_MESH_RESET_DELAY_MS=4000
820CONFIG_SCSI_MAC53C94=y 816CONFIG_SCSI_MAC53C94=y
821# CONFIG_SCSI_SRP is not set 817# CONFIG_SCSI_SRP is not set
822# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set 818# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
819# CONFIG_SCSI_DH is not set
823# CONFIG_ATA is not set 820# CONFIG_ATA is not set
824CONFIG_MD=y 821CONFIG_MD=y
825CONFIG_BLK_DEV_MD=m 822CONFIG_BLK_DEV_MD=m
@@ -844,30 +841,22 @@ CONFIG_DM_ZERO=m
844# 841#
845# IEEE 1394 (FireWire) support 842# IEEE 1394 (FireWire) support
846# 843#
847# CONFIG_FIREWIRE is not set
848CONFIG_IEEE1394=m
849
850#
851# Subsystem Options
852#
853# CONFIG_IEEE1394_VERBOSEDEBUG is not set
854 844
855# 845#
856# Controllers 846# Enable only one of the two stacks, unless you know what you are doing
857# 847#
858# CONFIG_IEEE1394_PCILYNX is not set 848# CONFIG_FIREWIRE is not set
849CONFIG_IEEE1394=m
859CONFIG_IEEE1394_OHCI1394=m 850CONFIG_IEEE1394_OHCI1394=m
860 851# CONFIG_IEEE1394_PCILYNX is not set
861#
862# Protocols
863#
864CONFIG_IEEE1394_VIDEO1394=m
865CONFIG_IEEE1394_SBP2=m 852CONFIG_IEEE1394_SBP2=m
866# CONFIG_IEEE1394_SBP2_PHYS_DMA is not set 853# CONFIG_IEEE1394_SBP2_PHYS_DMA is not set
867# CONFIG_IEEE1394_ETH1394_ROM_ENTRY is not set 854# CONFIG_IEEE1394_ETH1394_ROM_ENTRY is not set
868# CONFIG_IEEE1394_ETH1394 is not set 855# CONFIG_IEEE1394_ETH1394 is not set
869CONFIG_IEEE1394_DV1394=m
870CONFIG_IEEE1394_RAWIO=m 856CONFIG_IEEE1394_RAWIO=m
857CONFIG_IEEE1394_VIDEO1394=m
858CONFIG_IEEE1394_DV1394=m
859# CONFIG_IEEE1394_VERBOSEDEBUG is not set
871# CONFIG_I2O is not set 860# CONFIG_I2O is not set
872CONFIG_MACINTOSH_DRIVERS=y 861CONFIG_MACINTOSH_DRIVERS=y
873CONFIG_ADB=y 862CONFIG_ADB=y
@@ -887,7 +876,6 @@ CONFIG_THERM_ADT746X=m
887# CONFIG_ANSLCD is not set 876# CONFIG_ANSLCD is not set
888CONFIG_PMAC_RACKMETER=m 877CONFIG_PMAC_RACKMETER=m
889CONFIG_NETDEVICES=y 878CONFIG_NETDEVICES=y
890# CONFIG_NETDEVICES_MULTIQUEUE is not set
891CONFIG_DUMMY=m 879CONFIG_DUMMY=m
892# CONFIG_BONDING is not set 880# CONFIG_BONDING is not set
893# CONFIG_MACVLAN is not set 881# CONFIG_MACVLAN is not set
@@ -936,7 +924,6 @@ CONFIG_NETDEV_1000=y
936# CONFIG_DL2K is not set 924# CONFIG_DL2K is not set
937# CONFIG_E1000 is not set 925# CONFIG_E1000 is not set
938# CONFIG_E1000E is not set 926# CONFIG_E1000E is not set
939# CONFIG_E1000E_ENABLED is not set
940# CONFIG_IP1000 is not set 927# CONFIG_IP1000 is not set
941# CONFIG_IGB is not set 928# CONFIG_IGB is not set
942# CONFIG_NS83820 is not set 929# CONFIG_NS83820 is not set
@@ -952,6 +939,7 @@ CONFIG_NETDEV_1000=y
952# CONFIG_MV643XX_ETH is not set 939# CONFIG_MV643XX_ETH is not set
953# CONFIG_QLA3XXX is not set 940# CONFIG_QLA3XXX is not set
954# CONFIG_ATL1 is not set 941# CONFIG_ATL1 is not set
942# CONFIG_ATL1E is not set
955CONFIG_NETDEV_10000=y 943CONFIG_NETDEV_10000=y
956# CONFIG_CHELSIO_T1 is not set 944# CONFIG_CHELSIO_T1 is not set
957# CONFIG_CHELSIO_T3 is not set 945# CONFIG_CHELSIO_T3 is not set
@@ -994,13 +982,15 @@ CONFIG_PRISM54=m
994# CONFIG_RTL8180 is not set 982# CONFIG_RTL8180 is not set
995# CONFIG_RTL8187 is not set 983# CONFIG_RTL8187 is not set
996# CONFIG_ADM8211 is not set 984# CONFIG_ADM8211 is not set
985# CONFIG_MAC80211_HWSIM is not set
997CONFIG_P54_COMMON=m 986CONFIG_P54_COMMON=m
998# CONFIG_P54_USB is not set 987# CONFIG_P54_USB is not set
999# CONFIG_P54_PCI is not set 988# CONFIG_P54_PCI is not set
1000# CONFIG_ATH5K is not set 989# CONFIG_ATH5K is not set
990# CONFIG_ATH9K is not set
1001# CONFIG_IWLCORE is not set 991# CONFIG_IWLCORE is not set
1002# CONFIG_IWLWIFI_LEDS is not set 992# CONFIG_IWLWIFI_LEDS is not set
1003# CONFIG_IWL4965 is not set 993# CONFIG_IWLAGN is not set
1004# CONFIG_IWL3945 is not set 994# CONFIG_IWL3945 is not set
1005# CONFIG_HOSTAP is not set 995# CONFIG_HOSTAP is not set
1006CONFIG_B43=m 996CONFIG_B43=m
@@ -1095,6 +1085,7 @@ CONFIG_INPUT_MOUSE=y
1095# CONFIG_MOUSE_PS2 is not set 1085# CONFIG_MOUSE_PS2 is not set
1096# CONFIG_MOUSE_SERIAL is not set 1086# CONFIG_MOUSE_SERIAL is not set
1097# CONFIG_MOUSE_APPLETOUCH is not set 1087# CONFIG_MOUSE_APPLETOUCH is not set
1088# CONFIG_MOUSE_BCM5974 is not set
1098# CONFIG_MOUSE_VSXXXAA is not set 1089# CONFIG_MOUSE_VSXXXAA is not set
1099# CONFIG_INPUT_JOYSTICK is not set 1090# CONFIG_INPUT_JOYSTICK is not set
1100# CONFIG_INPUT_TABLET is not set 1091# CONFIG_INPUT_TABLET is not set
@@ -1109,12 +1100,14 @@ CONFIG_SERIO=y
1109# CONFIG_SERIO_SERPORT is not set 1100# CONFIG_SERIO_SERPORT is not set
1110# CONFIG_SERIO_PCIPS2 is not set 1101# CONFIG_SERIO_PCIPS2 is not set
1111# CONFIG_SERIO_RAW is not set 1102# CONFIG_SERIO_RAW is not set
1103# CONFIG_SERIO_XILINX_XPS_PS2 is not set
1112# CONFIG_GAMEPORT is not set 1104# CONFIG_GAMEPORT is not set
1113 1105
1114# 1106#
1115# Character devices 1107# Character devices
1116# 1108#
1117CONFIG_VT=y 1109CONFIG_VT=y
1110CONFIG_CONSOLE_TRANSLATIONS=y
1118CONFIG_VT_CONSOLE=y 1111CONFIG_VT_CONSOLE=y
1119CONFIG_HW_CONSOLE=y 1112CONFIG_HW_CONSOLE=y
1120# CONFIG_VT_HW_CONSOLE_BINDING is not set 1113# CONFIG_VT_HW_CONSOLE_BINDING is not set
@@ -1165,45 +1158,70 @@ CONFIG_DEVPORT=y
1165CONFIG_I2C=y 1158CONFIG_I2C=y
1166CONFIG_I2C_BOARDINFO=y 1159CONFIG_I2C_BOARDINFO=y
1167CONFIG_I2C_CHARDEV=m 1160CONFIG_I2C_CHARDEV=m
1161CONFIG_I2C_HELPER_AUTO=y
1168CONFIG_I2C_ALGOBIT=y 1162CONFIG_I2C_ALGOBIT=y
1169 1163
1170# 1164#
1171# I2C Hardware Bus support 1165# I2C Hardware Bus support
1172# 1166#
1167
1168#
1169# PC SMBus host controller drivers
1170#
1173# CONFIG_I2C_ALI1535 is not set 1171# CONFIG_I2C_ALI1535 is not set
1174# CONFIG_I2C_ALI1563 is not set 1172# CONFIG_I2C_ALI1563 is not set
1175# CONFIG_I2C_ALI15X3 is not set 1173# CONFIG_I2C_ALI15X3 is not set
1176# CONFIG_I2C_AMD756 is not set 1174# CONFIG_I2C_AMD756 is not set
1177# CONFIG_I2C_AMD8111 is not set 1175# CONFIG_I2C_AMD8111 is not set
1178# CONFIG_I2C_I801 is not set 1176# CONFIG_I2C_I801 is not set
1179# CONFIG_I2C_I810 is not set 1177# CONFIG_I2C_ISCH is not set
1180# CONFIG_I2C_PIIX4 is not set 1178# CONFIG_I2C_PIIX4 is not set
1181CONFIG_I2C_POWERMAC=y
1182# CONFIG_I2C_MPC is not set
1183# CONFIG_I2C_NFORCE2 is not set 1179# CONFIG_I2C_NFORCE2 is not set
1184# CONFIG_I2C_OCORES is not set
1185# CONFIG_I2C_PARPORT_LIGHT is not set
1186# CONFIG_I2C_PROSAVAGE is not set
1187# CONFIG_I2C_SAVAGE4 is not set
1188# CONFIG_I2C_SIMTEC is not set
1189# CONFIG_I2C_SIS5595 is not set 1180# CONFIG_I2C_SIS5595 is not set
1190# CONFIG_I2C_SIS630 is not set 1181# CONFIG_I2C_SIS630 is not set
1191# CONFIG_I2C_SIS96X is not set 1182# CONFIG_I2C_SIS96X is not set
1192# CONFIG_I2C_TAOS_EVM is not set
1193# CONFIG_I2C_STUB is not set
1194# CONFIG_I2C_TINY_USB is not set
1195# CONFIG_I2C_VIA is not set 1183# CONFIG_I2C_VIA is not set
1196# CONFIG_I2C_VIAPRO is not set 1184# CONFIG_I2C_VIAPRO is not set
1185
1186#
1187# Mac SMBus host controller drivers
1188#
1189CONFIG_I2C_POWERMAC=y
1190
1191#
1192# I2C system bus drivers (mostly embedded / system-on-chip)
1193#
1194# CONFIG_I2C_MPC is not set
1195# CONFIG_I2C_OCORES is not set
1196# CONFIG_I2C_SIMTEC is not set
1197
1198#
1199# External I2C/SMBus adapter drivers
1200#
1201# CONFIG_I2C_PARPORT_LIGHT is not set
1202# CONFIG_I2C_TAOS_EVM is not set
1203# CONFIG_I2C_TINY_USB is not set
1204
1205#
1206# Graphics adapter I2C/DDC channel drivers
1207#
1197# CONFIG_I2C_VOODOO3 is not set 1208# CONFIG_I2C_VOODOO3 is not set
1209
1210#
1211# Other I2C/SMBus bus drivers
1212#
1198# CONFIG_I2C_PCA_PLATFORM is not set 1213# CONFIG_I2C_PCA_PLATFORM is not set
1214# CONFIG_I2C_STUB is not set
1199 1215
1200# 1216#
1201# Miscellaneous I2C Chip support 1217# Miscellaneous I2C Chip support
1202# 1218#
1203# CONFIG_DS1682 is not set 1219# CONFIG_DS1682 is not set
1220# CONFIG_AT24 is not set
1204# CONFIG_SENSORS_EEPROM is not set 1221# CONFIG_SENSORS_EEPROM is not set
1205# CONFIG_SENSORS_PCF8574 is not set 1222# CONFIG_SENSORS_PCF8574 is not set
1206# CONFIG_PCF8575 is not set 1223# CONFIG_PCF8575 is not set
1224# CONFIG_SENSORS_PCA9539 is not set
1207# CONFIG_SENSORS_PCF8591 is not set 1225# CONFIG_SENSORS_PCF8591 is not set
1208# CONFIG_SENSORS_MAX6875 is not set 1226# CONFIG_SENSORS_MAX6875 is not set
1209# CONFIG_SENSORS_TSL2550 is not set 1227# CONFIG_SENSORS_TSL2550 is not set
@@ -1212,6 +1230,8 @@ CONFIG_I2C_POWERMAC=y
1212# CONFIG_I2C_DEBUG_BUS is not set 1230# CONFIG_I2C_DEBUG_BUS is not set
1213# CONFIG_I2C_DEBUG_CHIP is not set 1231# CONFIG_I2C_DEBUG_CHIP is not set
1214# CONFIG_SPI is not set 1232# CONFIG_SPI is not set
1233CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
1234# CONFIG_GPIOLIB is not set
1215# CONFIG_W1 is not set 1235# CONFIG_W1 is not set
1216CONFIG_POWER_SUPPLY=y 1236CONFIG_POWER_SUPPLY=y
1217# CONFIG_POWER_SUPPLY_DEBUG is not set 1237# CONFIG_POWER_SUPPLY_DEBUG is not set
@@ -1221,6 +1241,7 @@ CONFIG_APM_POWER=y
1221CONFIG_BATTERY_PMU=y 1241CONFIG_BATTERY_PMU=y
1222# CONFIG_HWMON is not set 1242# CONFIG_HWMON is not set
1223# CONFIG_THERMAL is not set 1243# CONFIG_THERMAL is not set
1244# CONFIG_THERMAL_HWMON is not set
1224# CONFIG_WATCHDOG is not set 1245# CONFIG_WATCHDOG is not set
1225 1246
1226# 1247#
@@ -1241,8 +1262,10 @@ CONFIG_SSB_DRIVER_PCICORE=y
1241# 1262#
1242# Multifunction device drivers 1263# Multifunction device drivers
1243# 1264#
1265# CONFIG_MFD_CORE is not set
1244# CONFIG_MFD_SM501 is not set 1266# CONFIG_MFD_SM501 is not set
1245# CONFIG_HTC_PASIC3 is not set 1267# CONFIG_HTC_PASIC3 is not set
1268# CONFIG_MFD_TMIO is not set
1246 1269
1247# 1270#
1248# Multimedia devices 1271# Multimedia devices
@@ -1343,10 +1366,13 @@ CONFIG_FB_3DFX=y
1343# CONFIG_FB_TRIDENT is not set 1366# CONFIG_FB_TRIDENT is not set
1344# CONFIG_FB_ARK is not set 1367# CONFIG_FB_ARK is not set
1345# CONFIG_FB_PM3 is not set 1368# CONFIG_FB_PM3 is not set
1369# CONFIG_FB_CARMINE is not set
1346# CONFIG_FB_IBM_GXT4500 is not set 1370# CONFIG_FB_IBM_GXT4500 is not set
1347# CONFIG_FB_VIRTUAL is not set 1371# CONFIG_FB_VIRTUAL is not set
1348CONFIG_BACKLIGHT_LCD_SUPPORT=y 1372CONFIG_BACKLIGHT_LCD_SUPPORT=y
1349CONFIG_LCD_CLASS_DEVICE=m 1373CONFIG_LCD_CLASS_DEVICE=m
1374# CONFIG_LCD_ILI9320 is not set
1375# CONFIG_LCD_PLATFORM is not set
1350CONFIG_BACKLIGHT_CLASS_DEVICE=y 1376CONFIG_BACKLIGHT_CLASS_DEVICE=y
1351# CONFIG_BACKLIGHT_CORGI is not set 1377# CONFIG_BACKLIGHT_CORGI is not set
1352 1378
@@ -1374,15 +1400,7 @@ CONFIG_LOGO=y
1374CONFIG_LOGO_LINUX_MONO=y 1400CONFIG_LOGO_LINUX_MONO=y
1375CONFIG_LOGO_LINUX_VGA16=y 1401CONFIG_LOGO_LINUX_VGA16=y
1376CONFIG_LOGO_LINUX_CLUT224=y 1402CONFIG_LOGO_LINUX_CLUT224=y
1377
1378#
1379# Sound
1380#
1381CONFIG_SOUND=m 1403CONFIG_SOUND=m
1382
1383#
1384# Advanced Linux Sound Architecture
1385#
1386CONFIG_SND=m 1404CONFIG_SND=m
1387CONFIG_SND_TIMER=m 1405CONFIG_SND_TIMER=m
1388CONFIG_SND_PCM=m 1406CONFIG_SND_PCM=m
@@ -1400,19 +1418,13 @@ CONFIG_SND_SUPPORT_OLD_API=y
1400CONFIG_SND_VERBOSE_PROCFS=y 1418CONFIG_SND_VERBOSE_PROCFS=y
1401# CONFIG_SND_VERBOSE_PRINTK is not set 1419# CONFIG_SND_VERBOSE_PRINTK is not set
1402# CONFIG_SND_DEBUG is not set 1420# CONFIG_SND_DEBUG is not set
1403 1421CONFIG_SND_DRIVERS=y
1404#
1405# Generic devices
1406#
1407CONFIG_SND_DUMMY=m 1422CONFIG_SND_DUMMY=m
1408# CONFIG_SND_VIRMIDI is not set 1423# CONFIG_SND_VIRMIDI is not set
1409# CONFIG_SND_MTPAV is not set 1424# CONFIG_SND_MTPAV is not set
1410# CONFIG_SND_SERIAL_U16550 is not set 1425# CONFIG_SND_SERIAL_U16550 is not set
1411# CONFIG_SND_MPU401 is not set 1426# CONFIG_SND_MPU401 is not set
1412 1427CONFIG_SND_PCI=y
1413#
1414# PCI devices
1415#
1416# CONFIG_SND_AD1889 is not set 1428# CONFIG_SND_AD1889 is not set
1417# CONFIG_SND_ALS300 is not set 1429# CONFIG_SND_ALS300 is not set
1418# CONFIG_SND_ALS4000 is not set 1430# CONFIG_SND_ALS4000 is not set
@@ -1474,20 +1486,9 @@ CONFIG_SND_DUMMY=m
1474# CONFIG_SND_VIRTUOSO is not set 1486# CONFIG_SND_VIRTUOSO is not set
1475# CONFIG_SND_VX222 is not set 1487# CONFIG_SND_VX222 is not set
1476# CONFIG_SND_YMFPCI is not set 1488# CONFIG_SND_YMFPCI is not set
1477 1489CONFIG_SND_PPC=y
1478#
1479# ALSA PowerMac devices
1480#
1481CONFIG_SND_POWERMAC=m 1490CONFIG_SND_POWERMAC=m
1482CONFIG_SND_POWERMAC_AUTO_DRC=y 1491CONFIG_SND_POWERMAC_AUTO_DRC=y
1483
1484#
1485# ALSA PowerPC devices
1486#
1487
1488#
1489# Apple Onboard Audio driver
1490#
1491CONFIG_SND_AOA=m 1492CONFIG_SND_AOA=m
1492CONFIG_SND_AOA_FABRIC_LAYOUT=m 1493CONFIG_SND_AOA_FABRIC_LAYOUT=m
1493CONFIG_SND_AOA_ONYX=m 1494CONFIG_SND_AOA_ONYX=m
@@ -1495,36 +1496,14 @@ CONFIG_SND_AOA_TAS=m
1495CONFIG_SND_AOA_TOONIE=m 1496CONFIG_SND_AOA_TOONIE=m
1496CONFIG_SND_AOA_SOUNDBUS=m 1497CONFIG_SND_AOA_SOUNDBUS=m
1497CONFIG_SND_AOA_SOUNDBUS_I2S=m 1498CONFIG_SND_AOA_SOUNDBUS_I2S=m
1498 1499CONFIG_SND_USB=y
1499#
1500# USB devices
1501#
1502CONFIG_SND_USB_AUDIO=m 1500CONFIG_SND_USB_AUDIO=m
1503# CONFIG_SND_USB_USX2Y is not set 1501# CONFIG_SND_USB_USX2Y is not set
1504# CONFIG_SND_USB_CAIAQ is not set 1502# CONFIG_SND_USB_CAIAQ is not set
1505 1503CONFIG_SND_PCMCIA=y
1506#
1507# PCMCIA devices
1508#
1509# CONFIG_SND_VXPOCKET is not set 1504# CONFIG_SND_VXPOCKET is not set
1510# CONFIG_SND_PDAUDIOCF is not set 1505# CONFIG_SND_PDAUDIOCF is not set
1511
1512#
1513# System on Chip audio support
1514#
1515# CONFIG_SND_SOC is not set 1506# CONFIG_SND_SOC is not set
1516
1517#
1518# ALSA SoC audio for Freescale SOCs
1519#
1520
1521#
1522# SoC Audio for the Texas Instruments OMAP
1523#
1524
1525#
1526# Open Sound System
1527#
1528# CONFIG_SOUND_PRIME is not set 1507# CONFIG_SOUND_PRIME is not set
1529CONFIG_HID_SUPPORT=y 1508CONFIG_HID_SUPPORT=y
1530CONFIG_HID=y 1509CONFIG_HID=y
@@ -1554,6 +1533,7 @@ CONFIG_USB_DEVICE_CLASS=y
1554CONFIG_USB_DYNAMIC_MINORS=y 1533CONFIG_USB_DYNAMIC_MINORS=y
1555# CONFIG_USB_SUSPEND is not set 1534# CONFIG_USB_SUSPEND is not set
1556# CONFIG_USB_OTG is not set 1535# CONFIG_USB_OTG is not set
1536CONFIG_USB_MON=y
1557 1537
1558# 1538#
1559# USB Host Controller Drivers 1539# USB Host Controller Drivers
@@ -1579,6 +1559,7 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y
1579# 1559#
1580CONFIG_USB_ACM=m 1560CONFIG_USB_ACM=m
1581CONFIG_USB_PRINTER=m 1561CONFIG_USB_PRINTER=m
1562# CONFIG_USB_WDM is not set
1582 1563
1583# 1564#
1584# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 1565# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
@@ -1600,6 +1581,7 @@ CONFIG_USB_STORAGE=m
1600# CONFIG_USB_STORAGE_ALAUDA is not set 1581# CONFIG_USB_STORAGE_ALAUDA is not set
1601CONFIG_USB_STORAGE_ONETOUCH=y 1582CONFIG_USB_STORAGE_ONETOUCH=y
1602# CONFIG_USB_STORAGE_KARMA is not set 1583# CONFIG_USB_STORAGE_KARMA is not set
1584# CONFIG_USB_STORAGE_SIERRA is not set
1603# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set 1585# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
1604# CONFIG_USB_LIBUSUAL is not set 1586# CONFIG_USB_LIBUSUAL is not set
1605 1587
@@ -1608,7 +1590,6 @@ CONFIG_USB_STORAGE_ONETOUCH=y
1608# 1590#
1609# CONFIG_USB_MDC800 is not set 1591# CONFIG_USB_MDC800 is not set
1610# CONFIG_USB_MICROTEK is not set 1592# CONFIG_USB_MICROTEK is not set
1611CONFIG_USB_MON=y
1612 1593
1613# 1594#
1614# USB port drivers 1595# USB port drivers
@@ -1617,7 +1598,6 @@ CONFIG_USB_SERIAL=m
1617CONFIG_USB_EZUSB=y 1598CONFIG_USB_EZUSB=y
1618# CONFIG_USB_SERIAL_GENERIC is not set 1599# CONFIG_USB_SERIAL_GENERIC is not set
1619# CONFIG_USB_SERIAL_AIRCABLE is not set 1600# CONFIG_USB_SERIAL_AIRCABLE is not set
1620# CONFIG_USB_SERIAL_AIRPRIME is not set
1621# CONFIG_USB_SERIAL_ARK3116 is not set 1601# CONFIG_USB_SERIAL_ARK3116 is not set
1622# CONFIG_USB_SERIAL_BELKIN is not set 1602# CONFIG_USB_SERIAL_BELKIN is not set
1623# CONFIG_USB_SERIAL_CH341 is not set 1603# CONFIG_USB_SERIAL_CH341 is not set
@@ -1676,7 +1656,6 @@ CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y
1676# CONFIG_USB_EMI62 is not set 1656# CONFIG_USB_EMI62 is not set
1677# CONFIG_USB_EMI26 is not set 1657# CONFIG_USB_EMI26 is not set
1678# CONFIG_USB_ADUTUX is not set 1658# CONFIG_USB_ADUTUX is not set
1679# CONFIG_USB_AUERSWALD is not set
1680# CONFIG_USB_RIO500 is not set 1659# CONFIG_USB_RIO500 is not set
1681# CONFIG_USB_LEGOTOWER is not set 1660# CONFIG_USB_LEGOTOWER is not set
1682# CONFIG_USB_LCD is not set 1661# CONFIG_USB_LCD is not set
@@ -1693,6 +1672,7 @@ CONFIG_USB_APPLEDISPLAY=m
1693# CONFIG_USB_TRANCEVIBRATOR is not set 1672# CONFIG_USB_TRANCEVIBRATOR is not set
1694# CONFIG_USB_IOWARRIOR is not set 1673# CONFIG_USB_IOWARRIOR is not set
1695# CONFIG_USB_TEST is not set 1674# CONFIG_USB_TEST is not set
1675# CONFIG_USB_ISIGHTFW is not set
1696# CONFIG_USB_GADGET is not set 1676# CONFIG_USB_GADGET is not set
1697# CONFIG_MMC is not set 1677# CONFIG_MMC is not set
1698# CONFIG_MEMSTICK is not set 1678# CONFIG_MEMSTICK is not set
@@ -1702,6 +1682,8 @@ CONFIG_LEDS_CLASS=y
1702# 1682#
1703# LED drivers 1683# LED drivers
1704# 1684#
1685# CONFIG_LEDS_PCA9532 is not set
1686# CONFIG_LEDS_PCA955X is not set
1705 1687
1706# 1688#
1707# LED Triggers 1689# LED Triggers
@@ -1789,6 +1771,7 @@ CONFIG_HFSPLUS_FS=m
1789# CONFIG_CRAMFS is not set 1771# CONFIG_CRAMFS is not set
1790# CONFIG_VXFS_FS is not set 1772# CONFIG_VXFS_FS is not set
1791# CONFIG_MINIX_FS is not set 1773# CONFIG_MINIX_FS is not set
1774# CONFIG_OMFS_FS is not set
1792# CONFIG_HPFS_FS is not set 1775# CONFIG_HPFS_FS is not set
1793# CONFIG_QNX4FS_FS is not set 1776# CONFIG_QNX4FS_FS is not set
1794# CONFIG_ROMFS_FS is not set 1777# CONFIG_ROMFS_FS is not set
@@ -1811,7 +1794,6 @@ CONFIG_NFS_ACL_SUPPORT=y
1811CONFIG_NFS_COMMON=y 1794CONFIG_NFS_COMMON=y
1812CONFIG_SUNRPC=y 1795CONFIG_SUNRPC=y
1813CONFIG_SUNRPC_GSS=y 1796CONFIG_SUNRPC_GSS=y
1814# CONFIG_SUNRPC_BIND34 is not set
1815CONFIG_RPCSEC_GSS_KRB5=y 1797CONFIG_RPCSEC_GSS_KRB5=y
1816# CONFIG_RPCSEC_GSS_SPKM3 is not set 1798# CONFIG_RPCSEC_GSS_SPKM3 is not set
1817CONFIG_SMB_FS=m 1799CONFIG_SMB_FS=m
@@ -1891,6 +1873,7 @@ CONFIG_BITREVERSE=y
1891# CONFIG_GENERIC_FIND_FIRST_BIT is not set 1873# CONFIG_GENERIC_FIND_FIRST_BIT is not set
1892CONFIG_CRC_CCITT=y 1874CONFIG_CRC_CCITT=y
1893CONFIG_CRC16=y 1875CONFIG_CRC16=y
1876CONFIG_CRC_T10DIF=y
1894CONFIG_CRC_ITU_T=m 1877CONFIG_CRC_ITU_T=m
1895CONFIG_CRC32=y 1878CONFIG_CRC32=y
1896# CONFIG_CRC7 is not set 1879# CONFIG_CRC7 is not set
@@ -1921,8 +1904,10 @@ CONFIG_MAGIC_SYSRQ=y
1921CONFIG_DEBUG_KERNEL=y 1904CONFIG_DEBUG_KERNEL=y
1922# CONFIG_DEBUG_SHIRQ is not set 1905# CONFIG_DEBUG_SHIRQ is not set
1923CONFIG_DETECT_SOFTLOCKUP=y 1906CONFIG_DETECT_SOFTLOCKUP=y
1907# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
1908CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
1924CONFIG_SCHED_DEBUG=y 1909CONFIG_SCHED_DEBUG=y
1925# CONFIG_SCHEDSTATS is not set 1910CONFIG_SCHEDSTATS=y
1926# CONFIG_TIMER_STATS is not set 1911# CONFIG_TIMER_STATS is not set
1927# CONFIG_DEBUG_OBJECTS is not set 1912# CONFIG_DEBUG_OBJECTS is not set
1928# CONFIG_SLUB_DEBUG_ON is not set 1913# CONFIG_SLUB_DEBUG_ON is not set
@@ -1933,24 +1918,38 @@ CONFIG_SCHED_DEBUG=y
1933# CONFIG_DEBUG_MUTEXES is not set 1918# CONFIG_DEBUG_MUTEXES is not set
1934# CONFIG_DEBUG_SPINLOCK_SLEEP is not set 1919# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1935# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set 1920# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1921CONFIG_STACKTRACE=y
1936# CONFIG_DEBUG_KOBJECT is not set 1922# CONFIG_DEBUG_KOBJECT is not set
1937CONFIG_DEBUG_BUGVERBOSE=y 1923CONFIG_DEBUG_BUGVERBOSE=y
1938# CONFIG_DEBUG_INFO is not set 1924# CONFIG_DEBUG_INFO is not set
1939# CONFIG_DEBUG_VM is not set 1925# CONFIG_DEBUG_VM is not set
1940# CONFIG_DEBUG_WRITECOUNT is not set 1926# CONFIG_DEBUG_WRITECOUNT is not set
1927CONFIG_DEBUG_MEMORY_INIT=y
1941# CONFIG_DEBUG_LIST is not set 1928# CONFIG_DEBUG_LIST is not set
1942# CONFIG_DEBUG_SG is not set 1929# CONFIG_DEBUG_SG is not set
1930CONFIG_FRAME_POINTER=y
1943# CONFIG_BOOT_PRINTK_DELAY is not set 1931# CONFIG_BOOT_PRINTK_DELAY is not set
1944# CONFIG_RCU_TORTURE_TEST is not set 1932# CONFIG_RCU_TORTURE_TEST is not set
1945# CONFIG_BACKTRACE_SELF_TEST is not set 1933# CONFIG_BACKTRACE_SELF_TEST is not set
1946# CONFIG_FAULT_INJECTION is not set 1934# CONFIG_FAULT_INJECTION is not set
1935CONFIG_LATENCYTOP=y
1936CONFIG_SYSCTL_SYSCALL_CHECK=y
1937CONFIG_HAVE_FTRACE=y
1938CONFIG_HAVE_DYNAMIC_FTRACE=y
1939# CONFIG_FTRACE is not set
1940# CONFIG_SCHED_TRACER is not set
1941# CONFIG_CONTEXT_SWITCH_TRACER is not set
1947# CONFIG_SAMPLES is not set 1942# CONFIG_SAMPLES is not set
1943CONFIG_HAVE_ARCH_KGDB=y
1944# CONFIG_KGDB is not set
1948# CONFIG_DEBUG_STACKOVERFLOW is not set 1945# CONFIG_DEBUG_STACKOVERFLOW is not set
1949# CONFIG_DEBUG_STACK_USAGE is not set 1946# CONFIG_DEBUG_STACK_USAGE is not set
1950CONFIG_DEBUGGER=y 1947# CONFIG_CODE_PATCHING_SELFTEST is not set
1948# CONFIG_FTR_FIXUP_SELFTEST is not set
1951CONFIG_XMON=y 1949CONFIG_XMON=y
1952CONFIG_XMON_DEFAULT=y 1950CONFIG_XMON_DEFAULT=y
1953CONFIG_XMON_DISASSEMBLY=y 1951CONFIG_XMON_DISASSEMBLY=y
1952CONFIG_DEBUGGER=y
1954CONFIG_IRQSTACKS=y 1953CONFIG_IRQSTACKS=y
1955# CONFIG_BDI_SWITCH is not set 1954# CONFIG_BDI_SWITCH is not set
1956CONFIG_BOOTX_TEXT=y 1955CONFIG_BOOTX_TEXT=y
@@ -2009,6 +2008,10 @@ CONFIG_CRYPTO_CRC32C=m
2009CONFIG_CRYPTO_MD4=m 2008CONFIG_CRYPTO_MD4=m
2010CONFIG_CRYPTO_MD5=y 2009CONFIG_CRYPTO_MD5=y
2011CONFIG_CRYPTO_MICHAEL_MIC=m 2010CONFIG_CRYPTO_MICHAEL_MIC=m
2011# CONFIG_CRYPTO_RMD128 is not set
2012# CONFIG_CRYPTO_RMD160 is not set
2013# CONFIG_CRYPTO_RMD256 is not set
2014# CONFIG_CRYPTO_RMD320 is not set
2012CONFIG_CRYPTO_SHA1=y 2015CONFIG_CRYPTO_SHA1=y
2013CONFIG_CRYPTO_SHA256=m 2016CONFIG_CRYPTO_SHA256=m
2014CONFIG_CRYPTO_SHA512=m 2017CONFIG_CRYPTO_SHA512=m
diff --git a/arch/powerpc/configs/ppc64_defconfig b/arch/powerpc/configs/ppc64_defconfig
index ce250bc98584..fc5930caeb5f 100644
--- a/arch/powerpc/configs/ppc64_defconfig
+++ b/arch/powerpc/configs/ppc64_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc6 3# Linux kernel version: 2.6.27-rc4
4# Mon Jun 16 21:11:19 2008 4# Tue Aug 26 13:22:03 2008
5# 5#
6CONFIG_PPC64=y 6CONFIG_PPC64=y
7 7
@@ -14,6 +14,7 @@ CONFIG_POWER4=y
14# CONFIG_TUNE_CELL is not set 14# CONFIG_TUNE_CELL is not set
15CONFIG_PPC_FPU=y 15CONFIG_PPC_FPU=y
16CONFIG_ALTIVEC=y 16CONFIG_ALTIVEC=y
17CONFIG_VSX=y
17CONFIG_PPC_STD_MMU=y 18CONFIG_PPC_STD_MMU=y
18CONFIG_PPC_MM_SLICES=y 19CONFIG_PPC_MM_SLICES=y
19CONFIG_VIRT_CPU_ACCOUNTING=y 20CONFIG_VIRT_CPU_ACCOUNTING=y
@@ -31,6 +32,7 @@ CONFIG_GENERIC_HARDIRQS=y
31CONFIG_HAVE_SETUP_PER_CPU_AREA=y 32CONFIG_HAVE_SETUP_PER_CPU_AREA=y
32CONFIG_IRQ_PER_CPU=y 33CONFIG_IRQ_PER_CPU=y
33CONFIG_STACKTRACE_SUPPORT=y 34CONFIG_STACKTRACE_SUPPORT=y
35CONFIG_HAVE_LATENCYTOP_SUPPORT=y
34CONFIG_TRACE_IRQFLAGS_SUPPORT=y 36CONFIG_TRACE_IRQFLAGS_SUPPORT=y
35CONFIG_LOCKDEP_SUPPORT=y 37CONFIG_LOCKDEP_SUPPORT=y
36CONFIG_RWSEM_XCHGADD_ALGORITHM=y 38CONFIG_RWSEM_XCHGADD_ALGORITHM=y
@@ -105,7 +107,6 @@ CONFIG_CC_OPTIMIZE_FOR_SIZE=y
105CONFIG_SYSCTL=y 107CONFIG_SYSCTL=y
106# CONFIG_EMBEDDED is not set 108# CONFIG_EMBEDDED is not set
107CONFIG_SYSCTL_SYSCALL=y 109CONFIG_SYSCTL_SYSCALL=y
108CONFIG_SYSCTL_SYSCALL_CHECK=y
109CONFIG_KALLSYMS=y 110CONFIG_KALLSYMS=y
110CONFIG_KALLSYMS_ALL=y 111CONFIG_KALLSYMS_ALL=y
111# CONFIG_KALLSYMS_EXTRA_PASS is not set 112# CONFIG_KALLSYMS_EXTRA_PASS is not set
@@ -129,14 +130,20 @@ CONFIG_SLUB_DEBUG=y
129CONFIG_SLUB=y 130CONFIG_SLUB=y
130# CONFIG_SLOB is not set 131# CONFIG_SLOB is not set
131CONFIG_PROFILING=y 132CONFIG_PROFILING=y
132# CONFIG_MARKERS is not set 133CONFIG_MARKERS=y
133CONFIG_OPROFILE=y 134CONFIG_OPROFILE=y
134CONFIG_HAVE_OPROFILE=y 135CONFIG_HAVE_OPROFILE=y
135# CONFIG_KPROBES is not set 136# CONFIG_KPROBES is not set
137CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
138CONFIG_HAVE_IOREMAP_PROT=y
136CONFIG_HAVE_KPROBES=y 139CONFIG_HAVE_KPROBES=y
137CONFIG_HAVE_KRETPROBES=y 140CONFIG_HAVE_KRETPROBES=y
138# CONFIG_HAVE_DMA_ATTRS is not set 141CONFIG_HAVE_ARCH_TRACEHOOK=y
142CONFIG_HAVE_DMA_ATTRS=y
143CONFIG_USE_GENERIC_SMP_HELPERS=y
144# CONFIG_HAVE_CLK is not set
139CONFIG_PROC_PAGE_MONITOR=y 145CONFIG_PROC_PAGE_MONITOR=y
146# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
140CONFIG_SLABINFO=y 147CONFIG_SLABINFO=y
141CONFIG_RT_MUTEXES=y 148CONFIG_RT_MUTEXES=y
142# CONFIG_TINY_SHMEM is not set 149# CONFIG_TINY_SHMEM is not set
@@ -152,6 +159,7 @@ CONFIG_STOP_MACHINE=y
152CONFIG_BLOCK=y 159CONFIG_BLOCK=y
153CONFIG_BLK_DEV_IO_TRACE=y 160CONFIG_BLK_DEV_IO_TRACE=y
154CONFIG_BLK_DEV_BSG=y 161CONFIG_BLK_DEV_BSG=y
162# CONFIG_BLK_DEV_INTEGRITY is not set
155CONFIG_BLOCK_COMPAT=y 163CONFIG_BLOCK_COMPAT=y
156 164
157# 165#
@@ -172,14 +180,13 @@ CONFIG_CLASSIC_RCU=y
172# Platform support 180# Platform support
173# 181#
174CONFIG_PPC_MULTIPLATFORM=y 182CONFIG_PPC_MULTIPLATFORM=y
175# CONFIG_PPC_82xx is not set
176# CONFIG_PPC_83xx is not set
177# CONFIG_PPC_86xx is not set
178CONFIG_PPC_PSERIES=y 183CONFIG_PPC_PSERIES=y
179CONFIG_PPC_SPLPAR=y 184CONFIG_PPC_SPLPAR=y
180CONFIG_EEH=y 185CONFIG_EEH=y
181CONFIG_SCANLOG=m 186CONFIG_SCANLOG=m
182CONFIG_LPARCFG=y 187CONFIG_LPARCFG=y
188CONFIG_PPC_SMLPAR=y
189CONFIG_CMM=y
183CONFIG_PPC_ISERIES=y 190CONFIG_PPC_ISERIES=y
184 191
185# 192#
@@ -189,8 +196,6 @@ CONFIG_VIODASD=y
189CONFIG_VIOCD=m 196CONFIG_VIOCD=m
190CONFIG_VIOTAPE=m 197CONFIG_VIOTAPE=m
191CONFIG_VIOPATH=y 198CONFIG_VIOPATH=y
192# CONFIG_PPC_MPC512x is not set
193# CONFIG_PPC_MPC5121 is not set
194CONFIG_PPC_PMAC=y 199CONFIG_PPC_PMAC=y
195CONFIG_PPC_PMAC64=y 200CONFIG_PPC_PMAC64=y
196CONFIG_PPC_MAPLE=y 201CONFIG_PPC_MAPLE=y
@@ -213,11 +218,15 @@ CONFIG_PPC_CELLEB=y
213# 218#
214CONFIG_SPU_FS=m 219CONFIG_SPU_FS=m
215CONFIG_SPU_FS_64K_LS=y 220CONFIG_SPU_FS_64K_LS=y
221# CONFIG_SPU_TRACE is not set
216CONFIG_SPU_BASE=y 222CONFIG_SPU_BASE=y
217CONFIG_CBE_RAS=y 223CONFIG_CBE_RAS=y
224CONFIG_PPC_IBM_CELL_RESETBUTTON=y
225CONFIG_PPC_IBM_CELL_POWERBUTTON=m
218CONFIG_CBE_THERM=m 226CONFIG_CBE_THERM=m
219CONFIG_CBE_CPUFREQ=m 227CONFIG_CBE_CPUFREQ=m
220CONFIG_CBE_CPUFREQ_PMI=m 228CONFIG_CBE_CPUFREQ_PMI=m
229CONFIG_CBE_CPUFREQ_SPU_GOVERNOR=m
221CONFIG_OPROFILE_CELL=y 230CONFIG_OPROFILE_CELL=y
222# CONFIG_PQ2ADS is not set 231# CONFIG_PQ2ADS is not set
223CONFIG_PPC_NATIVE=y 232CONFIG_PPC_NATIVE=y
@@ -279,7 +288,7 @@ CONFIG_HZ_250=y
279# CONFIG_HZ_300 is not set 288# CONFIG_HZ_300 is not set
280# CONFIG_HZ_1000 is not set 289# CONFIG_HZ_1000 is not set
281CONFIG_HZ=250 290CONFIG_HZ=250
282# CONFIG_SCHED_HRTICK is not set 291CONFIG_SCHED_HRTICK=y
283CONFIG_PREEMPT_NONE=y 292CONFIG_PREEMPT_NONE=y
284# CONFIG_PREEMPT_VOLUNTARY is not set 293# CONFIG_PREEMPT_VOLUNTARY is not set
285# CONFIG_PREEMPT is not set 294# CONFIG_PREEMPT is not set
@@ -315,8 +324,10 @@ CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
315CONFIG_SPARSEMEM_VMEMMAP=y 324CONFIG_SPARSEMEM_VMEMMAP=y
316CONFIG_MEMORY_HOTPLUG=y 325CONFIG_MEMORY_HOTPLUG=y
317CONFIG_MEMORY_HOTPLUG_SPARSE=y 326CONFIG_MEMORY_HOTPLUG_SPARSE=y
327CONFIG_MEMORY_HOTREMOVE=y
318CONFIG_PAGEFLAGS_EXTENDED=y 328CONFIG_PAGEFLAGS_EXTENDED=y
319CONFIG_SPLIT_PTLOCK_CPUS=4 329CONFIG_SPLIT_PTLOCK_CPUS=4
330CONFIG_MIGRATION=y
320CONFIG_RESOURCES_64BIT=y 331CONFIG_RESOURCES_64BIT=y
321CONFIG_ZONE_DMA_FLAG=1 332CONFIG_ZONE_DMA_FLAG=1
322CONFIG_BOUNCE=y 333CONFIG_BOUNCE=y
@@ -327,6 +338,7 @@ CONFIG_FORCE_MAX_ZONEORDER=13
327# CONFIG_SCHED_SMT is not set 338# CONFIG_SCHED_SMT is not set
328CONFIG_PROC_DEVICETREE=y 339CONFIG_PROC_DEVICETREE=y
329# CONFIG_CMDLINE_BOOL is not set 340# CONFIG_CMDLINE_BOOL is not set
341CONFIG_EXTRA_TARGETS=""
330CONFIG_ARCH_WANTS_FREEZER_CONTROL=y 342CONFIG_ARCH_WANTS_FREEZER_CONTROL=y
331# CONFIG_PM is not set 343# CONFIG_PM is not set
332CONFIG_SECCOMP=y 344CONFIG_SECCOMP=y
@@ -370,10 +382,6 @@ CONFIG_HOTPLUG_PCI_RPA_DLPAR=m
370CONFIG_PAGE_OFFSET=0xc000000000000000 382CONFIG_PAGE_OFFSET=0xc000000000000000
371CONFIG_KERNEL_START=0xc000000000000000 383CONFIG_KERNEL_START=0xc000000000000000
372CONFIG_PHYSICAL_START=0x00000000 384CONFIG_PHYSICAL_START=0x00000000
373
374#
375# Networking
376#
377CONFIG_NET=y 385CONFIG_NET=y
378 386
379# 387#
@@ -387,6 +395,7 @@ CONFIG_XFRM_USER=m
387# CONFIG_XFRM_SUB_POLICY is not set 395# CONFIG_XFRM_SUB_POLICY is not set
388# CONFIG_XFRM_MIGRATE is not set 396# CONFIG_XFRM_MIGRATE is not set
389# CONFIG_XFRM_STATISTICS is not set 397# CONFIG_XFRM_STATISTICS is not set
398CONFIG_XFRM_IPCOMP=m
390CONFIG_NET_KEY=m 399CONFIG_NET_KEY=m
391# CONFIG_NET_KEY_MIGRATE is not set 400# CONFIG_NET_KEY_MIGRATE is not set
392CONFIG_INET=y 401CONFIG_INET=y
@@ -578,6 +587,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
578CONFIG_STANDALONE=y 587CONFIG_STANDALONE=y
579CONFIG_PREVENT_FIRMWARE_BUILD=y 588CONFIG_PREVENT_FIRMWARE_BUILD=y
580CONFIG_FW_LOADER=y 589CONFIG_FW_LOADER=y
590CONFIG_FIRMWARE_IN_KERNEL=y
591CONFIG_EXTRA_FIRMWARE=""
581# CONFIG_DEBUG_DRIVER is not set 592# CONFIG_DEBUG_DRIVER is not set
582# CONFIG_DEBUG_DEVRES is not set 593# CONFIG_DEBUG_DEVRES is not set
583# CONFIG_SYS_HYPERVISOR is not set 594# CONFIG_SYS_HYPERVISOR is not set
@@ -603,12 +614,14 @@ CONFIG_BLK_DEV_RAM_SIZE=65536
603# CONFIG_BLK_DEV_XIP is not set 614# CONFIG_BLK_DEV_XIP is not set
604# CONFIG_CDROM_PKTCDVD is not set 615# CONFIG_CDROM_PKTCDVD is not set
605# CONFIG_ATA_OVER_ETH is not set 616# CONFIG_ATA_OVER_ETH is not set
617# CONFIG_BLK_DEV_HD is not set
606CONFIG_MISC_DEVICES=y 618CONFIG_MISC_DEVICES=y
607# CONFIG_PHANTOM is not set 619# CONFIG_PHANTOM is not set
608# CONFIG_EEPROM_93CX6 is not set 620# CONFIG_EEPROM_93CX6 is not set
609# CONFIG_SGI_IOC4 is not set 621# CONFIG_SGI_IOC4 is not set
610# CONFIG_TIFM_CORE is not set 622# CONFIG_TIFM_CORE is not set
611# CONFIG_ENCLOSURE_SERVICES is not set 623# CONFIG_ENCLOSURE_SERVICES is not set
624# CONFIG_HP_ILO is not set
612CONFIG_HAVE_IDE=y 625CONFIG_HAVE_IDE=y
613CONFIG_IDE=y 626CONFIG_IDE=y
614CONFIG_BLK_DEV_IDE=y 627CONFIG_BLK_DEV_IDE=y
@@ -616,6 +629,7 @@ CONFIG_BLK_DEV_IDE=y
616# 629#
617# Please see Documentation/ide/ide.txt for help/info on IDE drives 630# Please see Documentation/ide/ide.txt for help/info on IDE drives
618# 631#
632CONFIG_IDE_TIMINGS=y
619# CONFIG_BLK_DEV_IDE_SATA is not set 633# CONFIG_BLK_DEV_IDE_SATA is not set
620CONFIG_BLK_DEV_IDEDISK=y 634CONFIG_BLK_DEV_IDEDISK=y
621# CONFIG_IDEDISK_MULTI_MODE is not set 635# CONFIG_IDEDISK_MULTI_MODE is not set
@@ -649,10 +663,8 @@ CONFIG_BLK_DEV_IDEDMA_PCI=y
649CONFIG_BLK_DEV_AMD74XX=y 663CONFIG_BLK_DEV_AMD74XX=y
650# CONFIG_BLK_DEV_CMD64X is not set 664# CONFIG_BLK_DEV_CMD64X is not set
651# CONFIG_BLK_DEV_TRIFLEX is not set 665# CONFIG_BLK_DEV_TRIFLEX is not set
652# CONFIG_BLK_DEV_CY82C693 is not set
653# CONFIG_BLK_DEV_CS5520 is not set 666# CONFIG_BLK_DEV_CS5520 is not set
654# CONFIG_BLK_DEV_CS5530 is not set 667# CONFIG_BLK_DEV_CS5530 is not set
655# CONFIG_BLK_DEV_HPT34X is not set
656# CONFIG_BLK_DEV_HPT366 is not set 668# CONFIG_BLK_DEV_HPT366 is not set
657# CONFIG_BLK_DEV_JMICRON is not set 669# CONFIG_BLK_DEV_JMICRON is not set
658# CONFIG_BLK_DEV_SC1200 is not set 670# CONFIG_BLK_DEV_SC1200 is not set
@@ -674,8 +686,6 @@ CONFIG_BLK_DEV_IDE_PMAC=y
674CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST=y 686CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST=y
675CONFIG_BLK_DEV_IDEDMA_PMAC=y 687CONFIG_BLK_DEV_IDEDMA_PMAC=y
676CONFIG_BLK_DEV_IDEDMA=y 688CONFIG_BLK_DEV_IDEDMA=y
677# CONFIG_BLK_DEV_HD_ONLY is not set
678# CONFIG_BLK_DEV_HD is not set
679 689
680# 690#
681# SCSI device support 691# SCSI device support
@@ -737,6 +747,8 @@ CONFIG_SCSI_LOWLEVEL=y
737# CONFIG_SCSI_GDTH is not set 747# CONFIG_SCSI_GDTH is not set
738# CONFIG_SCSI_IPS is not set 748# CONFIG_SCSI_IPS is not set
739CONFIG_SCSI_IBMVSCSI=y 749CONFIG_SCSI_IBMVSCSI=y
750CONFIG_SCSI_IBMVFC=m
751CONFIG_SCSI_IBMVFC_TRACE=y
740# CONFIG_SCSI_INITIO is not set 752# CONFIG_SCSI_INITIO is not set
741# CONFIG_SCSI_INIA100 is not set 753# CONFIG_SCSI_INIA100 is not set
742# CONFIG_SCSI_MVSAS is not set 754# CONFIG_SCSI_MVSAS is not set
@@ -758,6 +770,7 @@ CONFIG_SCSI_LPFC=m
758CONFIG_SCSI_DEBUG=m 770CONFIG_SCSI_DEBUG=m
759# CONFIG_SCSI_SRP is not set 771# CONFIG_SCSI_SRP is not set
760# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set 772# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
773# CONFIG_SCSI_DH is not set
761CONFIG_ATA=y 774CONFIG_ATA=y
762CONFIG_ATA_NONSTANDARD=y 775CONFIG_ATA_NONSTANDARD=y
763CONFIG_SATA_PMP=y 776CONFIG_SATA_PMP=y
@@ -837,9 +850,6 @@ CONFIG_DM_SNAPSHOT=m
837CONFIG_DM_MIRROR=m 850CONFIG_DM_MIRROR=m
838CONFIG_DM_ZERO=m 851CONFIG_DM_ZERO=m
839CONFIG_DM_MULTIPATH=m 852CONFIG_DM_MULTIPATH=m
840CONFIG_DM_MULTIPATH_EMC=m
841# CONFIG_DM_MULTIPATH_RDAC is not set
842# CONFIG_DM_MULTIPATH_HP is not set
843# CONFIG_DM_DELAY is not set 853# CONFIG_DM_DELAY is not set
844# CONFIG_DM_UEVENT is not set 854# CONFIG_DM_UEVENT is not set
845# CONFIG_FUSION is not set 855# CONFIG_FUSION is not set
@@ -847,29 +857,21 @@ CONFIG_DM_MULTIPATH_EMC=m
847# 857#
848# IEEE 1394 (FireWire) support 858# IEEE 1394 (FireWire) support
849# 859#
850# CONFIG_FIREWIRE is not set
851CONFIG_IEEE1394=y
852
853#
854# Subsystem Options
855#
856# CONFIG_IEEE1394_VERBOSEDEBUG is not set
857 860
858# 861#
859# Controllers 862# Enable only one of the two stacks, unless you know what you are doing
860# 863#
861# CONFIG_IEEE1394_PCILYNX is not set 864# CONFIG_FIREWIRE is not set
865CONFIG_IEEE1394=y
862CONFIG_IEEE1394_OHCI1394=y 866CONFIG_IEEE1394_OHCI1394=y
863 867# CONFIG_IEEE1394_PCILYNX is not set
864#
865# Protocols
866#
867CONFIG_IEEE1394_VIDEO1394=m
868CONFIG_IEEE1394_SBP2=m 868CONFIG_IEEE1394_SBP2=m
869CONFIG_IEEE1394_ETH1394_ROM_ENTRY=y 869CONFIG_IEEE1394_ETH1394_ROM_ENTRY=y
870CONFIG_IEEE1394_ETH1394=m 870CONFIG_IEEE1394_ETH1394=m
871CONFIG_IEEE1394_DV1394=m
872CONFIG_IEEE1394_RAWIO=y 871CONFIG_IEEE1394_RAWIO=y
872CONFIG_IEEE1394_VIDEO1394=m
873CONFIG_IEEE1394_DV1394=m
874# CONFIG_IEEE1394_VERBOSEDEBUG is not set
873# CONFIG_I2O is not set 875# CONFIG_I2O is not set
874CONFIG_MACINTOSH_DRIVERS=y 876CONFIG_MACINTOSH_DRIVERS=y
875CONFIG_ADB_PMU=y 877CONFIG_ADB_PMU=y
@@ -884,7 +886,6 @@ CONFIG_WINDFARM_PM112=y
884CONFIG_WINDFARM_PM121=y 886CONFIG_WINDFARM_PM121=y
885# CONFIG_PMAC_RACKMETER is not set 887# CONFIG_PMAC_RACKMETER is not set
886CONFIG_NETDEVICES=y 888CONFIG_NETDEVICES=y
887# CONFIG_NETDEVICES_MULTIQUEUE is not set
888CONFIG_DUMMY=m 889CONFIG_DUMMY=m
889CONFIG_BONDING=m 890CONFIG_BONDING=m
890# CONFIG_MACVLAN is not set 891# CONFIG_MACVLAN is not set
@@ -942,6 +943,7 @@ CONFIG_E100=y
942# CONFIG_SIS900 is not set 943# CONFIG_SIS900 is not set
943# CONFIG_EPIC100 is not set 944# CONFIG_EPIC100 is not set
944# CONFIG_SUNDANCE is not set 945# CONFIG_SUNDANCE is not set
946# CONFIG_TLAN is not set
945# CONFIG_VIA_RHINE is not set 947# CONFIG_VIA_RHINE is not set
946# CONFIG_SC92031 is not set 948# CONFIG_SC92031 is not set
947CONFIG_NETDEV_1000=y 949CONFIG_NETDEV_1000=y
@@ -949,10 +951,8 @@ CONFIG_ACENIC=y
949CONFIG_ACENIC_OMIT_TIGON_I=y 951CONFIG_ACENIC_OMIT_TIGON_I=y
950# CONFIG_DL2K is not set 952# CONFIG_DL2K is not set
951CONFIG_E1000=y 953CONFIG_E1000=y
952# CONFIG_E1000_NAPI is not set
953# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set 954# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
954# CONFIG_E1000E is not set 955# CONFIG_E1000E is not set
955# CONFIG_E1000E_ENABLED is not set
956# CONFIG_IP1000 is not set 956# CONFIG_IP1000 is not set
957# CONFIG_IGB is not set 957# CONFIG_IGB is not set
958# CONFIG_NS83820 is not set 958# CONFIG_NS83820 is not set
@@ -968,13 +968,13 @@ CONFIG_TIGON3=y
968CONFIG_SPIDER_NET=m 968CONFIG_SPIDER_NET=m
969# CONFIG_QLA3XXX is not set 969# CONFIG_QLA3XXX is not set
970# CONFIG_ATL1 is not set 970# CONFIG_ATL1 is not set
971# CONFIG_ATL1E is not set
971CONFIG_NETDEV_10000=y 972CONFIG_NETDEV_10000=y
972# CONFIG_CHELSIO_T1 is not set 973# CONFIG_CHELSIO_T1 is not set
973# CONFIG_CHELSIO_T3 is not set 974# CONFIG_CHELSIO_T3 is not set
974CONFIG_EHEA=m 975CONFIG_EHEA=m
975# CONFIG_IXGBE is not set 976# CONFIG_IXGBE is not set
976CONFIG_IXGB=m 977CONFIG_IXGB=m
977# CONFIG_IXGB_NAPI is not set
978# CONFIG_S2IO is not set 978# CONFIG_S2IO is not set
979# CONFIG_MYRI10GE is not set 979# CONFIG_MYRI10GE is not set
980# CONFIG_NETXEN_NIC is not set 980# CONFIG_NETXEN_NIC is not set
@@ -1068,6 +1068,7 @@ CONFIG_MOUSE_PS2_TRACKPOINT=y
1068# CONFIG_MOUSE_PS2_TOUCHKIT is not set 1068# CONFIG_MOUSE_PS2_TOUCHKIT is not set
1069# CONFIG_MOUSE_SERIAL is not set 1069# CONFIG_MOUSE_SERIAL is not set
1070# CONFIG_MOUSE_APPLETOUCH is not set 1070# CONFIG_MOUSE_APPLETOUCH is not set
1071# CONFIG_MOUSE_BCM5974 is not set
1071# CONFIG_MOUSE_VSXXXAA is not set 1072# CONFIG_MOUSE_VSXXXAA is not set
1072# CONFIG_INPUT_JOYSTICK is not set 1073# CONFIG_INPUT_JOYSTICK is not set
1073# CONFIG_INPUT_TABLET is not set 1074# CONFIG_INPUT_TABLET is not set
@@ -1090,12 +1091,14 @@ CONFIG_SERIO_I8042=y
1090# CONFIG_SERIO_PCIPS2 is not set 1091# CONFIG_SERIO_PCIPS2 is not set
1091CONFIG_SERIO_LIBPS2=y 1092CONFIG_SERIO_LIBPS2=y
1092# CONFIG_SERIO_RAW is not set 1093# CONFIG_SERIO_RAW is not set
1094# CONFIG_SERIO_XILINX_XPS_PS2 is not set
1093# CONFIG_GAMEPORT is not set 1095# CONFIG_GAMEPORT is not set
1094 1096
1095# 1097#
1096# Character devices 1098# Character devices
1097# 1099#
1098CONFIG_VT=y 1100CONFIG_VT=y
1101CONFIG_CONSOLE_TRANSLATIONS=y
1099CONFIG_VT_CONSOLE=y 1102CONFIG_VT_CONSOLE=y
1100CONFIG_HW_CONSOLE=y 1103CONFIG_HW_CONSOLE=y
1101# CONFIG_VT_HW_CONSOLE_BINDING is not set 1104# CONFIG_VT_HW_CONSOLE_BINDING is not set
@@ -1131,11 +1134,13 @@ CONFIG_UNIX98_PTYS=y
1131CONFIG_LEGACY_PTYS=y 1134CONFIG_LEGACY_PTYS=y
1132CONFIG_LEGACY_PTY_COUNT=256 1135CONFIG_LEGACY_PTY_COUNT=256
1133CONFIG_HVC_DRIVER=y 1136CONFIG_HVC_DRIVER=y
1137CONFIG_HVC_IRQ=y
1134CONFIG_HVC_CONSOLE=y 1138CONFIG_HVC_CONSOLE=y
1135CONFIG_HVC_ISERIES=y 1139CONFIG_HVC_ISERIES=y
1136CONFIG_HVC_RTAS=y 1140CONFIG_HVC_RTAS=y
1137CONFIG_HVC_BEAT=y 1141CONFIG_HVC_BEAT=y
1138CONFIG_HVCS=m 1142CONFIG_HVCS=m
1143CONFIG_IBM_BSR=m
1139# CONFIG_IPMI_HANDLER is not set 1144# CONFIG_IPMI_HANDLER is not set
1140# CONFIG_HW_RANDOM is not set 1145# CONFIG_HW_RANDOM is not set
1141# CONFIG_R3964 is not set 1146# CONFIG_R3964 is not set
@@ -1156,45 +1161,70 @@ CONFIG_DEVPORT=y
1156CONFIG_I2C=y 1161CONFIG_I2C=y
1157CONFIG_I2C_BOARDINFO=y 1162CONFIG_I2C_BOARDINFO=y
1158CONFIG_I2C_CHARDEV=y 1163CONFIG_I2C_CHARDEV=y
1164CONFIG_I2C_HELPER_AUTO=y
1159CONFIG_I2C_ALGOBIT=y 1165CONFIG_I2C_ALGOBIT=y
1160 1166
1161# 1167#
1162# I2C Hardware Bus support 1168# I2C Hardware Bus support
1163# 1169#
1170
1171#
1172# PC SMBus host controller drivers
1173#
1164# CONFIG_I2C_ALI1535 is not set 1174# CONFIG_I2C_ALI1535 is not set
1165# CONFIG_I2C_ALI1563 is not set 1175# CONFIG_I2C_ALI1563 is not set
1166# CONFIG_I2C_ALI15X3 is not set 1176# CONFIG_I2C_ALI15X3 is not set
1167# CONFIG_I2C_AMD756 is not set 1177# CONFIG_I2C_AMD756 is not set
1168CONFIG_I2C_AMD8111=y 1178CONFIG_I2C_AMD8111=y
1169# CONFIG_I2C_I801 is not set 1179# CONFIG_I2C_I801 is not set
1170# CONFIG_I2C_I810 is not set 1180# CONFIG_I2C_ISCH is not set
1171# CONFIG_I2C_PIIX4 is not set 1181# CONFIG_I2C_PIIX4 is not set
1172CONFIG_I2C_POWERMAC=y
1173# CONFIG_I2C_NFORCE2 is not set 1182# CONFIG_I2C_NFORCE2 is not set
1174# CONFIG_I2C_OCORES is not set
1175# CONFIG_I2C_PARPORT_LIGHT is not set
1176CONFIG_I2C_PASEMI=y
1177# CONFIG_I2C_PROSAVAGE is not set
1178# CONFIG_I2C_SAVAGE4 is not set
1179# CONFIG_I2C_SIMTEC is not set
1180# CONFIG_I2C_SIS5595 is not set 1183# CONFIG_I2C_SIS5595 is not set
1181# CONFIG_I2C_SIS630 is not set 1184# CONFIG_I2C_SIS630 is not set
1182# CONFIG_I2C_SIS96X is not set 1185# CONFIG_I2C_SIS96X is not set
1183# CONFIG_I2C_TAOS_EVM is not set
1184# CONFIG_I2C_STUB is not set
1185# CONFIG_I2C_TINY_USB is not set
1186# CONFIG_I2C_VIA is not set 1186# CONFIG_I2C_VIA is not set
1187# CONFIG_I2C_VIAPRO is not set 1187# CONFIG_I2C_VIAPRO is not set
1188
1189#
1190# Mac SMBus host controller drivers
1191#
1192CONFIG_I2C_POWERMAC=y
1193
1194#
1195# I2C system bus drivers (mostly embedded / system-on-chip)
1196#
1197# CONFIG_I2C_OCORES is not set
1198CONFIG_I2C_PASEMI=y
1199# CONFIG_I2C_SIMTEC is not set
1200
1201#
1202# External I2C/SMBus adapter drivers
1203#
1204# CONFIG_I2C_PARPORT_LIGHT is not set
1205# CONFIG_I2C_TAOS_EVM is not set
1206# CONFIG_I2C_TINY_USB is not set
1207
1208#
1209# Graphics adapter I2C/DDC channel drivers
1210#
1188# CONFIG_I2C_VOODOO3 is not set 1211# CONFIG_I2C_VOODOO3 is not set
1212
1213#
1214# Other I2C/SMBus bus drivers
1215#
1189# CONFIG_I2C_PCA_PLATFORM is not set 1216# CONFIG_I2C_PCA_PLATFORM is not set
1217# CONFIG_I2C_STUB is not set
1190 1218
1191# 1219#
1192# Miscellaneous I2C Chip support 1220# Miscellaneous I2C Chip support
1193# 1221#
1194# CONFIG_DS1682 is not set 1222# CONFIG_DS1682 is not set
1223# CONFIG_AT24 is not set
1195# CONFIG_SENSORS_EEPROM is not set 1224# CONFIG_SENSORS_EEPROM is not set
1196# CONFIG_SENSORS_PCF8574 is not set 1225# CONFIG_SENSORS_PCF8574 is not set
1197# CONFIG_PCF8575 is not set 1226# CONFIG_PCF8575 is not set
1227# CONFIG_SENSORS_PCA9539 is not set
1198# CONFIG_SENSORS_PCF8591 is not set 1228# CONFIG_SENSORS_PCF8591 is not set
1199# CONFIG_SENSORS_MAX6875 is not set 1229# CONFIG_SENSORS_MAX6875 is not set
1200# CONFIG_SENSORS_TSL2550 is not set 1230# CONFIG_SENSORS_TSL2550 is not set
@@ -1203,10 +1233,13 @@ CONFIG_I2C_PASEMI=y
1203# CONFIG_I2C_DEBUG_BUS is not set 1233# CONFIG_I2C_DEBUG_BUS is not set
1204# CONFIG_I2C_DEBUG_CHIP is not set 1234# CONFIG_I2C_DEBUG_CHIP is not set
1205# CONFIG_SPI is not set 1235# CONFIG_SPI is not set
1236CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
1237# CONFIG_GPIOLIB is not set
1206# CONFIG_W1 is not set 1238# CONFIG_W1 is not set
1207# CONFIG_POWER_SUPPLY is not set 1239# CONFIG_POWER_SUPPLY is not set
1208# CONFIG_HWMON is not set 1240# CONFIG_HWMON is not set
1209# CONFIG_THERMAL is not set 1241# CONFIG_THERMAL is not set
1242# CONFIG_THERMAL_HWMON is not set
1210# CONFIG_WATCHDOG is not set 1243# CONFIG_WATCHDOG is not set
1211 1244
1212# 1245#
@@ -1218,8 +1251,10 @@ CONFIG_SSB_POSSIBLE=y
1218# 1251#
1219# Multifunction device drivers 1252# Multifunction device drivers
1220# 1253#
1254# CONFIG_MFD_CORE is not set
1221# CONFIG_MFD_SM501 is not set 1255# CONFIG_MFD_SM501 is not set
1222# CONFIG_HTC_PASIC3 is not set 1256# CONFIG_HTC_PASIC3 is not set
1257# CONFIG_MFD_TMIO is not set
1223 1258
1224# 1259#
1225# Multimedia devices 1260# Multimedia devices
@@ -1299,10 +1334,13 @@ CONFIG_FB_RADEON_BACKLIGHT=y
1299# CONFIG_FB_TRIDENT is not set 1334# CONFIG_FB_TRIDENT is not set
1300# CONFIG_FB_ARK is not set 1335# CONFIG_FB_ARK is not set
1301# CONFIG_FB_PM3 is not set 1336# CONFIG_FB_PM3 is not set
1337# CONFIG_FB_CARMINE is not set
1302CONFIG_FB_IBM_GXT4500=y 1338CONFIG_FB_IBM_GXT4500=y
1303# CONFIG_FB_VIRTUAL is not set 1339# CONFIG_FB_VIRTUAL is not set
1304CONFIG_BACKLIGHT_LCD_SUPPORT=y 1340CONFIG_BACKLIGHT_LCD_SUPPORT=y
1305CONFIG_LCD_CLASS_DEVICE=y 1341CONFIG_LCD_CLASS_DEVICE=y
1342# CONFIG_LCD_ILI9320 is not set
1343# CONFIG_LCD_PLATFORM is not set
1306CONFIG_BACKLIGHT_CLASS_DEVICE=y 1344CONFIG_BACKLIGHT_CLASS_DEVICE=y
1307# CONFIG_BACKLIGHT_CORGI is not set 1345# CONFIG_BACKLIGHT_CORGI is not set
1308 1346
@@ -1331,15 +1369,7 @@ CONFIG_FB_LOGO_EXTRA=y
1331CONFIG_LOGO_LINUX_MONO=y 1369CONFIG_LOGO_LINUX_MONO=y
1332CONFIG_LOGO_LINUX_VGA16=y 1370CONFIG_LOGO_LINUX_VGA16=y
1333CONFIG_LOGO_LINUX_CLUT224=y 1371CONFIG_LOGO_LINUX_CLUT224=y
1334
1335#
1336# Sound
1337#
1338CONFIG_SOUND=m 1372CONFIG_SOUND=m
1339
1340#
1341# Advanced Linux Sound Architecture
1342#
1343CONFIG_SND=m 1373CONFIG_SND=m
1344CONFIG_SND_TIMER=m 1374CONFIG_SND_TIMER=m
1345CONFIG_SND_PCM=m 1375CONFIG_SND_PCM=m
@@ -1355,19 +1385,13 @@ CONFIG_SND_SUPPORT_OLD_API=y
1355CONFIG_SND_VERBOSE_PROCFS=y 1385CONFIG_SND_VERBOSE_PROCFS=y
1356# CONFIG_SND_VERBOSE_PRINTK is not set 1386# CONFIG_SND_VERBOSE_PRINTK is not set
1357# CONFIG_SND_DEBUG is not set 1387# CONFIG_SND_DEBUG is not set
1358 1388CONFIG_SND_DRIVERS=y
1359#
1360# Generic devices
1361#
1362# CONFIG_SND_DUMMY is not set 1389# CONFIG_SND_DUMMY is not set
1363# CONFIG_SND_VIRMIDI is not set 1390# CONFIG_SND_VIRMIDI is not set
1364# CONFIG_SND_MTPAV is not set 1391# CONFIG_SND_MTPAV is not set
1365# CONFIG_SND_SERIAL_U16550 is not set 1392# CONFIG_SND_SERIAL_U16550 is not set
1366# CONFIG_SND_MPU401 is not set 1393# CONFIG_SND_MPU401 is not set
1367 1394CONFIG_SND_PCI=y
1368#
1369# PCI devices
1370#
1371# CONFIG_SND_AD1889 is not set 1395# CONFIG_SND_AD1889 is not set
1372# CONFIG_SND_ALS300 is not set 1396# CONFIG_SND_ALS300 is not set
1373# CONFIG_SND_ALS4000 is not set 1397# CONFIG_SND_ALS4000 is not set
@@ -1429,20 +1453,9 @@ CONFIG_SND_VERBOSE_PROCFS=y
1429# CONFIG_SND_VIRTUOSO is not set 1453# CONFIG_SND_VIRTUOSO is not set
1430# CONFIG_SND_VX222 is not set 1454# CONFIG_SND_VX222 is not set
1431# CONFIG_SND_YMFPCI is not set 1455# CONFIG_SND_YMFPCI is not set
1432 1456CONFIG_SND_PPC=y
1433#
1434# ALSA PowerMac devices
1435#
1436CONFIG_SND_POWERMAC=m 1457CONFIG_SND_POWERMAC=m
1437CONFIG_SND_POWERMAC_AUTO_DRC=y 1458CONFIG_SND_POWERMAC_AUTO_DRC=y
1438
1439#
1440# ALSA PowerPC devices
1441#
1442
1443#
1444# Apple Onboard Audio driver
1445#
1446CONFIG_SND_AOA=m 1459CONFIG_SND_AOA=m
1447CONFIG_SND_AOA_FABRIC_LAYOUT=m 1460CONFIG_SND_AOA_FABRIC_LAYOUT=m
1448CONFIG_SND_AOA_ONYX=m 1461CONFIG_SND_AOA_ONYX=m
@@ -1450,36 +1463,14 @@ CONFIG_SND_AOA_TAS=m
1450CONFIG_SND_AOA_TOONIE=m 1463CONFIG_SND_AOA_TOONIE=m
1451CONFIG_SND_AOA_SOUNDBUS=m 1464CONFIG_SND_AOA_SOUNDBUS=m
1452CONFIG_SND_AOA_SOUNDBUS_I2S=m 1465CONFIG_SND_AOA_SOUNDBUS_I2S=m
1453 1466CONFIG_SND_USB=y
1454#
1455# USB devices
1456#
1457# CONFIG_SND_USB_AUDIO is not set 1467# CONFIG_SND_USB_AUDIO is not set
1458# CONFIG_SND_USB_USX2Y is not set 1468# CONFIG_SND_USB_USX2Y is not set
1459# CONFIG_SND_USB_CAIAQ is not set 1469# CONFIG_SND_USB_CAIAQ is not set
1460 1470CONFIG_SND_PCMCIA=y
1461#
1462# PCMCIA devices
1463#
1464# CONFIG_SND_VXPOCKET is not set 1471# CONFIG_SND_VXPOCKET is not set
1465# CONFIG_SND_PDAUDIOCF is not set 1472# CONFIG_SND_PDAUDIOCF is not set
1466
1467#
1468# System on Chip audio support
1469#
1470# CONFIG_SND_SOC is not set 1473# CONFIG_SND_SOC is not set
1471
1472#
1473# ALSA SoC audio for Freescale SOCs
1474#
1475
1476#
1477# SoC Audio for the Texas Instruments OMAP
1478#
1479
1480#
1481# Open Sound System
1482#
1483# CONFIG_SOUND_PRIME is not set 1474# CONFIG_SOUND_PRIME is not set
1484CONFIG_HID_SUPPORT=y 1475CONFIG_HID_SUPPORT=y
1485CONFIG_HID=y 1476CONFIG_HID=y
@@ -1508,6 +1499,7 @@ CONFIG_USB_DEVICEFS=y
1508CONFIG_USB_DEVICE_CLASS=y 1499CONFIG_USB_DEVICE_CLASS=y
1509# CONFIG_USB_DYNAMIC_MINORS is not set 1500# CONFIG_USB_DYNAMIC_MINORS is not set
1510# CONFIG_USB_OTG is not set 1501# CONFIG_USB_OTG is not set
1502# CONFIG_USB_MON is not set
1511 1503
1512# 1504#
1513# USB Host Controller Drivers 1505# USB Host Controller Drivers
@@ -1556,6 +1548,7 @@ CONFIG_USB_STORAGE=m
1556# CONFIG_USB_STORAGE_ALAUDA is not set 1548# CONFIG_USB_STORAGE_ALAUDA is not set
1557# CONFIG_USB_STORAGE_ONETOUCH is not set 1549# CONFIG_USB_STORAGE_ONETOUCH is not set
1558# CONFIG_USB_STORAGE_KARMA is not set 1550# CONFIG_USB_STORAGE_KARMA is not set
1551# CONFIG_USB_STORAGE_SIERRA is not set
1559# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set 1552# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
1560# CONFIG_USB_LIBUSUAL is not set 1553# CONFIG_USB_LIBUSUAL is not set
1561 1554
@@ -1564,7 +1557,6 @@ CONFIG_USB_STORAGE=m
1564# 1557#
1565# CONFIG_USB_MDC800 is not set 1558# CONFIG_USB_MDC800 is not set
1566# CONFIG_USB_MICROTEK is not set 1559# CONFIG_USB_MICROTEK is not set
1567# CONFIG_USB_MON is not set
1568 1560
1569# 1561#
1570# USB port drivers 1562# USB port drivers
@@ -1577,7 +1569,6 @@ CONFIG_USB_STORAGE=m
1577# CONFIG_USB_EMI62 is not set 1569# CONFIG_USB_EMI62 is not set
1578# CONFIG_USB_EMI26 is not set 1570# CONFIG_USB_EMI26 is not set
1579# CONFIG_USB_ADUTUX is not set 1571# CONFIG_USB_ADUTUX is not set
1580# CONFIG_USB_AUERSWALD is not set
1581# CONFIG_USB_RIO500 is not set 1572# CONFIG_USB_RIO500 is not set
1582# CONFIG_USB_LEGOTOWER is not set 1573# CONFIG_USB_LEGOTOWER is not set
1583# CONFIG_USB_LCD is not set 1574# CONFIG_USB_LCD is not set
@@ -1769,6 +1760,7 @@ CONFIG_HFSPLUS_FS=m
1769CONFIG_CRAMFS=y 1760CONFIG_CRAMFS=y
1770# CONFIG_VXFS_FS is not set 1761# CONFIG_VXFS_FS is not set
1771# CONFIG_MINIX_FS is not set 1762# CONFIG_MINIX_FS is not set
1763# CONFIG_OMFS_FS is not set
1772# CONFIG_HPFS_FS is not set 1764# CONFIG_HPFS_FS is not set
1773# CONFIG_QNX4FS_FS is not set 1765# CONFIG_QNX4FS_FS is not set
1774# CONFIG_ROMFS_FS is not set 1766# CONFIG_ROMFS_FS is not set
@@ -1779,12 +1771,12 @@ CONFIG_NFS_FS=y
1779CONFIG_NFS_V3=y 1771CONFIG_NFS_V3=y
1780CONFIG_NFS_V3_ACL=y 1772CONFIG_NFS_V3_ACL=y
1781CONFIG_NFS_V4=y 1773CONFIG_NFS_V4=y
1774CONFIG_ROOT_NFS=y
1782CONFIG_NFSD=m 1775CONFIG_NFSD=m
1783CONFIG_NFSD_V2_ACL=y 1776CONFIG_NFSD_V2_ACL=y
1784CONFIG_NFSD_V3=y 1777CONFIG_NFSD_V3=y
1785CONFIG_NFSD_V3_ACL=y 1778CONFIG_NFSD_V3_ACL=y
1786CONFIG_NFSD_V4=y 1779CONFIG_NFSD_V4=y
1787CONFIG_ROOT_NFS=y
1788CONFIG_LOCKD=y 1780CONFIG_LOCKD=y
1789CONFIG_LOCKD_V4=y 1781CONFIG_LOCKD_V4=y
1790CONFIG_EXPORTFS=m 1782CONFIG_EXPORTFS=m
@@ -1793,7 +1785,6 @@ CONFIG_NFS_COMMON=y
1793CONFIG_SUNRPC=y 1785CONFIG_SUNRPC=y
1794CONFIG_SUNRPC_GSS=y 1786CONFIG_SUNRPC_GSS=y
1795CONFIG_SUNRPC_XPRT_RDMA=m 1787CONFIG_SUNRPC_XPRT_RDMA=m
1796# CONFIG_SUNRPC_BIND34 is not set
1797CONFIG_RPCSEC_GSS_KRB5=y 1788CONFIG_RPCSEC_GSS_KRB5=y
1798CONFIG_RPCSEC_GSS_SPKM3=m 1789CONFIG_RPCSEC_GSS_SPKM3=m
1799# CONFIG_SMB_FS is not set 1790# CONFIG_SMB_FS is not set
@@ -1878,6 +1869,7 @@ CONFIG_BITREVERSE=y
1878# CONFIG_GENERIC_FIND_FIRST_BIT is not set 1869# CONFIG_GENERIC_FIND_FIRST_BIT is not set
1879CONFIG_CRC_CCITT=m 1870CONFIG_CRC_CCITT=m
1880# CONFIG_CRC16 is not set 1871# CONFIG_CRC16 is not set
1872CONFIG_CRC_T10DIF=y
1881CONFIG_CRC_ITU_T=m 1873CONFIG_CRC_ITU_T=m
1882CONFIG_CRC32=y 1874CONFIG_CRC32=y
1883# CONFIG_CRC7 is not set 1875# CONFIG_CRC7 is not set
@@ -1910,8 +1902,10 @@ CONFIG_DEBUG_FS=y
1910CONFIG_DEBUG_KERNEL=y 1902CONFIG_DEBUG_KERNEL=y
1911# CONFIG_DEBUG_SHIRQ is not set 1903# CONFIG_DEBUG_SHIRQ is not set
1912CONFIG_DETECT_SOFTLOCKUP=y 1904CONFIG_DETECT_SOFTLOCKUP=y
1905# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
1906CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
1913CONFIG_SCHED_DEBUG=y 1907CONFIG_SCHED_DEBUG=y
1914# CONFIG_SCHEDSTATS is not set 1908CONFIG_SCHEDSTATS=y
1915# CONFIG_TIMER_STATS is not set 1909# CONFIG_TIMER_STATS is not set
1916# CONFIG_DEBUG_OBJECTS is not set 1910# CONFIG_DEBUG_OBJECTS is not set
1917# CONFIG_SLUB_DEBUG_ON is not set 1911# CONFIG_SLUB_DEBUG_ON is not set
@@ -1923,28 +1917,47 @@ CONFIG_DEBUG_MUTEXES=y
1923# CONFIG_DEBUG_LOCK_ALLOC is not set 1917# CONFIG_DEBUG_LOCK_ALLOC is not set
1924# CONFIG_PROVE_LOCKING is not set 1918# CONFIG_PROVE_LOCKING is not set
1925# CONFIG_LOCK_STAT is not set 1919# CONFIG_LOCK_STAT is not set
1920CONFIG_TRACE_IRQFLAGS=y
1926# CONFIG_DEBUG_SPINLOCK_SLEEP is not set 1921# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1927# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set 1922# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1923CONFIG_STACKTRACE=y
1928# CONFIG_DEBUG_KOBJECT is not set 1924# CONFIG_DEBUG_KOBJECT is not set
1929CONFIG_DEBUG_BUGVERBOSE=y 1925CONFIG_DEBUG_BUGVERBOSE=y
1930# CONFIG_DEBUG_INFO is not set 1926# CONFIG_DEBUG_INFO is not set
1931# CONFIG_DEBUG_VM is not set 1927# CONFIG_DEBUG_VM is not set
1932# CONFIG_DEBUG_WRITECOUNT is not set 1928# CONFIG_DEBUG_WRITECOUNT is not set
1929CONFIG_DEBUG_MEMORY_INIT=y
1933# CONFIG_DEBUG_LIST is not set 1930# CONFIG_DEBUG_LIST is not set
1934# CONFIG_DEBUG_SG is not set 1931# CONFIG_DEBUG_SG is not set
1932CONFIG_FRAME_POINTER=y
1935# CONFIG_BOOT_PRINTK_DELAY is not set 1933# CONFIG_BOOT_PRINTK_DELAY is not set
1936# CONFIG_RCU_TORTURE_TEST is not set 1934# CONFIG_RCU_TORTURE_TEST is not set
1937# CONFIG_BACKTRACE_SELF_TEST is not set 1935# CONFIG_BACKTRACE_SELF_TEST is not set
1938# CONFIG_FAULT_INJECTION is not set 1936# CONFIG_FAULT_INJECTION is not set
1937CONFIG_LATENCYTOP=y
1938CONFIG_SYSCTL_SYSCALL_CHECK=y
1939CONFIG_HAVE_FTRACE=y
1940CONFIG_HAVE_DYNAMIC_FTRACE=y
1941CONFIG_TRACER_MAX_TRACE=y
1942CONFIG_TRACING=y
1943# CONFIG_FTRACE is not set
1944CONFIG_IRQSOFF_TRACER=y
1945CONFIG_SCHED_TRACER=y
1946CONFIG_CONTEXT_SWITCH_TRACER=y
1947# CONFIG_FTRACE_STARTUP_TEST is not set
1939# CONFIG_SAMPLES is not set 1948# CONFIG_SAMPLES is not set
1949CONFIG_HAVE_ARCH_KGDB=y
1950# CONFIG_KGDB is not set
1940CONFIG_DEBUG_STACKOVERFLOW=y 1951CONFIG_DEBUG_STACKOVERFLOW=y
1941CONFIG_DEBUG_STACK_USAGE=y 1952CONFIG_DEBUG_STACK_USAGE=y
1942# CONFIG_DEBUG_PAGEALLOC is not set 1953# CONFIG_DEBUG_PAGEALLOC is not set
1943# CONFIG_HCALL_STATS is not set 1954# CONFIG_HCALL_STATS is not set
1944CONFIG_DEBUGGER=y 1955# CONFIG_CODE_PATCHING_SELFTEST is not set
1956# CONFIG_FTR_FIXUP_SELFTEST is not set
1945CONFIG_XMON=y 1957CONFIG_XMON=y
1946# CONFIG_XMON_DEFAULT is not set 1958# CONFIG_XMON_DEFAULT is not set
1947CONFIG_XMON_DISASSEMBLY=y 1959CONFIG_XMON_DISASSEMBLY=y
1960CONFIG_DEBUGGER=y
1948CONFIG_IRQSTACKS=y 1961CONFIG_IRQSTACKS=y
1949# CONFIG_VIRQ_DEBUG is not set 1962# CONFIG_VIRQ_DEBUG is not set
1950CONFIG_BOOTX_TEXT=y 1963CONFIG_BOOTX_TEXT=y
@@ -2007,6 +2020,10 @@ CONFIG_CRYPTO_CRC32C=m
2007CONFIG_CRYPTO_MD4=m 2020CONFIG_CRYPTO_MD4=m
2008CONFIG_CRYPTO_MD5=y 2021CONFIG_CRYPTO_MD5=y
2009CONFIG_CRYPTO_MICHAEL_MIC=m 2022CONFIG_CRYPTO_MICHAEL_MIC=m
2023# CONFIG_CRYPTO_RMD128 is not set
2024# CONFIG_CRYPTO_RMD160 is not set
2025# CONFIG_CRYPTO_RMD256 is not set
2026# CONFIG_CRYPTO_RMD320 is not set
2010CONFIG_CRYPTO_SHA1=m 2027CONFIG_CRYPTO_SHA1=m
2011CONFIG_CRYPTO_SHA256=m 2028CONFIG_CRYPTO_SHA256=m
2012CONFIG_CRYPTO_SHA512=m 2029CONFIG_CRYPTO_SHA512=m
diff --git a/arch/powerpc/configs/ppc6xx_defconfig b/arch/powerpc/configs/ppc6xx_defconfig
index e6e91c85da31..3c6dbdef56eb 100644
--- a/arch/powerpc/configs/ppc6xx_defconfig
+++ b/arch/powerpc/configs/ppc6xx_defconfig
@@ -1,8 +1,7 @@
1# powerpc
2# 1#
3# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
4# Linux kernel version: 2.6.26-git2 3# Linux kernel version: 2.6.27-rc4
5# Tue Jul 15 23:54:18 2008 4# Tue Aug 26 13:29:50 2008
6# 5#
7# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
8 7
@@ -112,7 +111,6 @@ CONFIG_CC_OPTIMIZE_FOR_SIZE=y
112CONFIG_SYSCTL=y 111CONFIG_SYSCTL=y
113# CONFIG_EMBEDDED is not set 112# CONFIG_EMBEDDED is not set
114CONFIG_SYSCTL_SYSCALL=y 113CONFIG_SYSCTL_SYSCALL=y
115CONFIG_SYSCTL_SYSCALL_CHECK=y
116CONFIG_KALLSYMS=y 114CONFIG_KALLSYMS=y
117CONFIG_KALLSYMS_ALL=y 115CONFIG_KALLSYMS_ALL=y
118CONFIG_KALLSYMS_EXTRA_PASS=y 116CONFIG_KALLSYMS_EXTRA_PASS=y
@@ -140,12 +138,17 @@ CONFIG_MARKERS=y
140CONFIG_OPROFILE=m 138CONFIG_OPROFILE=m
141CONFIG_HAVE_OPROFILE=y 139CONFIG_HAVE_OPROFILE=y
142CONFIG_KPROBES=y 140CONFIG_KPROBES=y
141CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
143CONFIG_KRETPROBES=y 142CONFIG_KRETPROBES=y
143CONFIG_HAVE_IOREMAP_PROT=y
144CONFIG_HAVE_KPROBES=y 144CONFIG_HAVE_KPROBES=y
145CONFIG_HAVE_KRETPROBES=y 145CONFIG_HAVE_KRETPROBES=y
146CONFIG_HAVE_ARCH_TRACEHOOK=y
146# CONFIG_HAVE_DMA_ATTRS is not set 147# CONFIG_HAVE_DMA_ATTRS is not set
147# CONFIG_USE_GENERIC_SMP_HELPERS is not set 148# CONFIG_USE_GENERIC_SMP_HELPERS is not set
149CONFIG_HAVE_CLK=y
148CONFIG_PROC_PAGE_MONITOR=y 150CONFIG_PROC_PAGE_MONITOR=y
151# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
149CONFIG_SLABINFO=y 152CONFIG_SLABINFO=y
150CONFIG_RT_MUTEXES=y 153CONFIG_RT_MUTEXES=y
151# CONFIG_TINY_SHMEM is not set 154# CONFIG_TINY_SHMEM is not set
@@ -266,7 +269,6 @@ CONFIG_TAU=y
266CONFIG_TAU_AVERAGE=y 269CONFIG_TAU_AVERAGE=y
267CONFIG_QUICC_ENGINE=y 270CONFIG_QUICC_ENGINE=y
268CONFIG_CPM2=y 271CONFIG_CPM2=y
269CONFIG_PPC_CPM_NEW_BINDING=y
270CONFIG_FSL_ULI1575=y 272CONFIG_FSL_ULI1575=y
271CONFIG_CPM=y 273CONFIG_CPM=y
272CONFIG_PPC_BESTCOMM=y 274CONFIG_PPC_BESTCOMM=y
@@ -287,7 +289,7 @@ CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
287# CONFIG_HZ_300 is not set 289# CONFIG_HZ_300 is not set
288CONFIG_HZ_1000=y 290CONFIG_HZ_1000=y
289CONFIG_HZ=1000 291CONFIG_HZ=1000
290# CONFIG_SCHED_HRTICK is not set 292CONFIG_SCHED_HRTICK=y
291# CONFIG_PREEMPT_NONE is not set 293# CONFIG_PREEMPT_NONE is not set
292CONFIG_PREEMPT_VOLUNTARY=y 294CONFIG_PREEMPT_VOLUNTARY=y
293# CONFIG_PREEMPT is not set 295# CONFIG_PREEMPT is not set
@@ -311,6 +313,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
311# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set 313# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
312CONFIG_PAGEFLAGS_EXTENDED=y 314CONFIG_PAGEFLAGS_EXTENDED=y
313CONFIG_SPLIT_PTLOCK_CPUS=4 315CONFIG_SPLIT_PTLOCK_CPUS=4
316# CONFIG_MIGRATION is not set
314CONFIG_RESOURCES_64BIT=y 317CONFIG_RESOURCES_64BIT=y
315CONFIG_ZONE_DMA_FLAG=1 318CONFIG_ZONE_DMA_FLAG=1
316CONFIG_BOUNCE=y 319CONFIG_BOUNCE=y
@@ -326,6 +329,7 @@ CONFIG_PM_DEBUG=y
326CONFIG_CAN_PM_TRACE=y 329CONFIG_CAN_PM_TRACE=y
327CONFIG_PM_SLEEP=y 330CONFIG_PM_SLEEP=y
328CONFIG_SUSPEND=y 331CONFIG_SUSPEND=y
332# CONFIG_PM_TEST_SUSPEND is not set
329CONFIG_SUSPEND_FREEZER=y 333CONFIG_SUSPEND_FREEZER=y
330CONFIG_HIBERNATION=y 334CONFIG_HIBERNATION=y
331CONFIG_PM_STD_PARTITION="" 335CONFIG_PM_STD_PARTITION=""
@@ -344,6 +348,7 @@ CONFIG_FSL_SOC=y
344CONFIG_FSL_PCI=y 348CONFIG_FSL_PCI=y
345CONFIG_FSL_LBC=y 349CONFIG_FSL_LBC=y
346CONFIG_FSL_GTM=y 350CONFIG_FSL_GTM=y
351CONFIG_PPC_PCI_CHOICE=y
347CONFIG_PCI=y 352CONFIG_PCI=y
348CONFIG_PCI_DOMAINS=y 353CONFIG_PCI_DOMAINS=y
349CONFIG_PCI_SYSCALL=y 354CONFIG_PCI_SYSCALL=y
@@ -395,10 +400,6 @@ CONFIG_KERNEL_START=0xc0000000
395CONFIG_PHYSICAL_START=0x00000000 400CONFIG_PHYSICAL_START=0x00000000
396# CONFIG_TASK_SIZE_BOOL is not set 401# CONFIG_TASK_SIZE_BOOL is not set
397CONFIG_TASK_SIZE=0xc0000000 402CONFIG_TASK_SIZE=0xc0000000
398
399#
400# Networking
401#
402CONFIG_NET=y 403CONFIG_NET=y
403 404
404# 405#
@@ -412,6 +413,7 @@ CONFIG_XFRM_USER=y
412CONFIG_XFRM_SUB_POLICY=y 413CONFIG_XFRM_SUB_POLICY=y
413CONFIG_XFRM_MIGRATE=y 414CONFIG_XFRM_MIGRATE=y
414CONFIG_XFRM_STATISTICS=y 415CONFIG_XFRM_STATISTICS=y
416CONFIG_XFRM_IPCOMP=m
415CONFIG_NET_KEY=m 417CONFIG_NET_KEY=m
416CONFIG_NET_KEY_MIGRATE=y 418CONFIG_NET_KEY_MIGRATE=y
417CONFIG_INET=y 419CONFIG_INET=y
@@ -602,6 +604,7 @@ CONFIG_IP_NF_TARGET_ECN=m
602CONFIG_IP_NF_TARGET_TTL=m 604CONFIG_IP_NF_TARGET_TTL=m
603CONFIG_IP_NF_TARGET_CLUSTERIP=m 605CONFIG_IP_NF_TARGET_CLUSTERIP=m
604CONFIG_IP_NF_RAW=m 606CONFIG_IP_NF_RAW=m
607CONFIG_IP_NF_SECURITY=m
605CONFIG_IP_NF_ARPTABLES=m 608CONFIG_IP_NF_ARPTABLES=m
606CONFIG_IP_NF_ARPFILTER=m 609CONFIG_IP_NF_ARPFILTER=m
607CONFIG_IP_NF_ARP_MANGLE=m 610CONFIG_IP_NF_ARP_MANGLE=m
@@ -626,6 +629,7 @@ CONFIG_IP6_NF_TARGET_REJECT=m
626CONFIG_IP6_NF_MANGLE=m 629CONFIG_IP6_NF_MANGLE=m
627CONFIG_IP6_NF_TARGET_HL=m 630CONFIG_IP6_NF_TARGET_HL=m
628CONFIG_IP6_NF_RAW=m 631CONFIG_IP6_NF_RAW=m
632CONFIG_IP6_NF_SECURITY=m
629 633
630# 634#
631# DECnet: Netfilter Configuration 635# DECnet: Netfilter Configuration
@@ -643,6 +647,7 @@ CONFIG_BRIDGE_EBT_802_3=m
643CONFIG_BRIDGE_EBT_AMONG=m 647CONFIG_BRIDGE_EBT_AMONG=m
644CONFIG_BRIDGE_EBT_ARP=m 648CONFIG_BRIDGE_EBT_ARP=m
645CONFIG_BRIDGE_EBT_IP=m 649CONFIG_BRIDGE_EBT_IP=m
650CONFIG_BRIDGE_EBT_IP6=m
646CONFIG_BRIDGE_EBT_LIMIT=m 651CONFIG_BRIDGE_EBT_LIMIT=m
647CONFIG_BRIDGE_EBT_MARK=m 652CONFIG_BRIDGE_EBT_MARK=m
648CONFIG_BRIDGE_EBT_PKTTYPE=m 653CONFIG_BRIDGE_EBT_PKTTYPE=m
@@ -691,8 +696,10 @@ CONFIG_ATM_LANE=m
691# CONFIG_ATM_MPOA is not set 696# CONFIG_ATM_MPOA is not set
692CONFIG_ATM_BR2684=m 697CONFIG_ATM_BR2684=m
693# CONFIG_ATM_BR2684_IPFILTER is not set 698# CONFIG_ATM_BR2684_IPFILTER is not set
699CONFIG_STP=m
694CONFIG_BRIDGE=m 700CONFIG_BRIDGE=m
695CONFIG_VLAN_8021Q=m 701CONFIG_VLAN_8021Q=m
702# CONFIG_VLAN_8021Q_GVRP is not set
696CONFIG_DECNET=m 703CONFIG_DECNET=m
697CONFIG_DECNET_ROUTER=y 704CONFIG_DECNET_ROUTER=y
698CONFIG_LLC=m 705CONFIG_LLC=m
@@ -832,6 +839,7 @@ CONFIG_BT_HIDP=m
832# 839#
833CONFIG_BT_HCIUSB=m 840CONFIG_BT_HCIUSB=m
834CONFIG_BT_HCIUSB_SCO=y 841CONFIG_BT_HCIUSB_SCO=y
842# CONFIG_BT_HCIBTUSB is not set
835CONFIG_BT_HCIUART=m 843CONFIG_BT_HCIUART=m
836CONFIG_BT_HCIUART_H4=y 844CONFIG_BT_HCIUART_H4=y
837CONFIG_BT_HCIUART_BCSP=y 845CONFIG_BT_HCIUART_BCSP=y
@@ -855,7 +863,6 @@ CONFIG_NL80211=y
855CONFIG_WIRELESS_EXT=y 863CONFIG_WIRELESS_EXT=y
856CONFIG_WIRELESS_EXT_SYSFS=y 864CONFIG_WIRELESS_EXT_SYSFS=y
857CONFIG_MAC80211=m 865CONFIG_MAC80211=m
858CONFIG_MAC80211_QOS=y
859 866
860# 867#
861# Rate control algorithm selection 868# Rate control algorithm selection
@@ -941,12 +948,14 @@ CONFIG_CDROM_PKTCDVD_BUFFERS=8
941# CONFIG_CDROM_PKTCDVD_WCACHE is not set 948# CONFIG_CDROM_PKTCDVD_WCACHE is not set
942# CONFIG_ATA_OVER_ETH is not set 949# CONFIG_ATA_OVER_ETH is not set
943CONFIG_VIRTIO_BLK=m 950CONFIG_VIRTIO_BLK=m
951CONFIG_BLK_DEV_HD=y
944CONFIG_MISC_DEVICES=y 952CONFIG_MISC_DEVICES=y
945# CONFIG_PHANTOM is not set 953# CONFIG_PHANTOM is not set
946CONFIG_EEPROM_93CX6=m 954CONFIG_EEPROM_93CX6=m
947# CONFIG_SGI_IOC4 is not set 955# CONFIG_SGI_IOC4 is not set
948# CONFIG_TIFM_CORE is not set 956# CONFIG_TIFM_CORE is not set
949CONFIG_ENCLOSURE_SERVICES=m 957CONFIG_ENCLOSURE_SERVICES=m
958# CONFIG_HP_ILO is not set
950CONFIG_HAVE_IDE=y 959CONFIG_HAVE_IDE=y
951CONFIG_IDE=y 960CONFIG_IDE=y
952CONFIG_BLK_DEV_IDE=y 961CONFIG_BLK_DEV_IDE=y
@@ -954,6 +963,7 @@ CONFIG_BLK_DEV_IDE=y
954# 963#
955# Please see Documentation/ide/ide.txt for help/info on IDE drives 964# Please see Documentation/ide/ide.txt for help/info on IDE drives
956# 965#
966CONFIG_IDE_TIMINGS=y
957CONFIG_IDE_ATAPI=y 967CONFIG_IDE_ATAPI=y
958# CONFIG_BLK_DEV_IDE_SATA is not set 968# CONFIG_BLK_DEV_IDE_SATA is not set
959CONFIG_BLK_DEV_IDEDISK=y 969CONFIG_BLK_DEV_IDEDISK=y
@@ -971,7 +981,6 @@ CONFIG_IDE_PROC_FS=y
971# 981#
972# IDE chipset support/bugfixes 982# IDE chipset support/bugfixes
973# 983#
974# CONFIG_IDE_GENERIC is not set
975# CONFIG_BLK_DEV_PLATFORM is not set 984# CONFIG_BLK_DEV_PLATFORM is not set
976# CONFIG_BLK_DEV_IDEPNP is not set 985# CONFIG_BLK_DEV_IDEPNP is not set
977CONFIG_BLK_DEV_IDEDMA_SFF=y 986CONFIG_BLK_DEV_IDEDMA_SFF=y
@@ -990,10 +999,8 @@ CONFIG_BLK_DEV_IDEDMA_PCI=y
990# CONFIG_BLK_DEV_AMD74XX is not set 999# CONFIG_BLK_DEV_AMD74XX is not set
991# CONFIG_BLK_DEV_CMD64X is not set 1000# CONFIG_BLK_DEV_CMD64X is not set
992# CONFIG_BLK_DEV_TRIFLEX is not set 1001# CONFIG_BLK_DEV_TRIFLEX is not set
993# CONFIG_BLK_DEV_CY82C693 is not set
994# CONFIG_BLK_DEV_CS5520 is not set 1002# CONFIG_BLK_DEV_CS5520 is not set
995# CONFIG_BLK_DEV_CS5530 is not set 1003# CONFIG_BLK_DEV_CS5530 is not set
996# CONFIG_BLK_DEV_HPT34X is not set
997# CONFIG_BLK_DEV_HPT366 is not set 1004# CONFIG_BLK_DEV_HPT366 is not set
998# CONFIG_BLK_DEV_JMICRON is not set 1005# CONFIG_BLK_DEV_JMICRON is not set
999# CONFIG_BLK_DEV_SC1200 is not set 1006# CONFIG_BLK_DEV_SC1200 is not set
@@ -1014,8 +1021,6 @@ CONFIG_BLK_DEV_IDE_PMAC=y
1014CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST=y 1021CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST=y
1015CONFIG_BLK_DEV_IDEDMA_PMAC=y 1022CONFIG_BLK_DEV_IDEDMA_PMAC=y
1016CONFIG_BLK_DEV_IDEDMA=y 1023CONFIG_BLK_DEV_IDEDMA=y
1017CONFIG_BLK_DEV_HD_ONLY=y
1018CONFIG_BLK_DEV_HD=y
1019 1024
1020# 1025#
1021# SCSI device support 1026# SCSI device support
@@ -1125,6 +1130,7 @@ CONFIG_SCSI_DH=y
1125CONFIG_SCSI_DH_RDAC=m 1130CONFIG_SCSI_DH_RDAC=m
1126CONFIG_SCSI_DH_HP_SW=m 1131CONFIG_SCSI_DH_HP_SW=m
1127CONFIG_SCSI_DH_EMC=m 1132CONFIG_SCSI_DH_EMC=m
1133# CONFIG_SCSI_DH_ALUA is not set
1128CONFIG_ATA=y 1134CONFIG_ATA=y
1129# CONFIG_ATA_NONSTANDARD is not set 1135# CONFIG_ATA_NONSTANDARD is not set
1130# CONFIG_SATA_PMP is not set 1136# CONFIG_SATA_PMP is not set
@@ -1246,7 +1252,6 @@ CONFIG_WINDFARM=y
1246# CONFIG_ANSLCD is not set 1252# CONFIG_ANSLCD is not set
1247CONFIG_PMAC_RACKMETER=m 1253CONFIG_PMAC_RACKMETER=m
1248CONFIG_NETDEVICES=y 1254CONFIG_NETDEVICES=y
1249CONFIG_NETDEVICES_MULTIQUEUE=y
1250CONFIG_IFB=m 1255CONFIG_IFB=m
1251CONFIG_DUMMY=m 1256CONFIG_DUMMY=m
1252CONFIG_BONDING=m 1257CONFIG_BONDING=m
@@ -1256,7 +1261,7 @@ CONFIG_TUN=m
1256CONFIG_VETH=m 1261CONFIG_VETH=m
1257CONFIG_NET_SB1000=m 1262CONFIG_NET_SB1000=m
1258# CONFIG_ARCNET is not set 1263# CONFIG_ARCNET is not set
1259CONFIG_PHYLIB=m 1264CONFIG_PHYLIB=y
1260 1265
1261# 1266#
1262# MII PHY device drivers 1267# MII PHY device drivers
@@ -1271,7 +1276,9 @@ CONFIG_SMSC_PHY=m
1271CONFIG_BROADCOM_PHY=m 1276CONFIG_BROADCOM_PHY=m
1272CONFIG_ICPLUS_PHY=m 1277CONFIG_ICPLUS_PHY=m
1273CONFIG_REALTEK_PHY=m 1278CONFIG_REALTEK_PHY=m
1279# CONFIG_FIXED_PHY is not set
1274CONFIG_MDIO_BITBANG=y 1280CONFIG_MDIO_BITBANG=y
1281# CONFIG_MDIO_OF_GPIO is not set
1275CONFIG_NET_ETHERNET=y 1282CONFIG_NET_ETHERNET=y
1276CONFIG_MII=m 1283CONFIG_MII=m
1277CONFIG_MACE=m 1284CONFIG_MACE=m
@@ -1328,9 +1335,7 @@ CONFIG_NE2000=m
1328CONFIG_NET_PCI=y 1335CONFIG_NET_PCI=y
1329CONFIG_PCNET32=m 1336CONFIG_PCNET32=m
1330CONFIG_AMD8111_ETH=m 1337CONFIG_AMD8111_ETH=m
1331CONFIG_AMD8111E_NAPI=y
1332CONFIG_ADAPTEC_STARFIRE=m 1338CONFIG_ADAPTEC_STARFIRE=m
1333CONFIG_ADAPTEC_STARFIRE_NAPI=y
1334# CONFIG_AC3200 is not set 1339# CONFIG_AC3200 is not set
1335# CONFIG_APRICOT is not set 1340# CONFIG_APRICOT is not set
1336CONFIG_B44=m 1341CONFIG_B44=m
@@ -1359,7 +1364,6 @@ CONFIG_SUNDANCE=m
1359CONFIG_TLAN=m 1364CONFIG_TLAN=m
1360CONFIG_VIA_RHINE=m 1365CONFIG_VIA_RHINE=m
1361CONFIG_VIA_RHINE_MMIO=y 1366CONFIG_VIA_RHINE_MMIO=y
1362CONFIG_VIA_RHINE_NAPI=y
1363CONFIG_SC92031=m 1367CONFIG_SC92031=m
1364CONFIG_NET_POCKET=y 1368CONFIG_NET_POCKET=y
1365CONFIG_DE600=m 1369CONFIG_DE600=m
@@ -1372,17 +1376,15 @@ CONFIG_ACENIC=m
1372# CONFIG_ACENIC_OMIT_TIGON_I is not set 1376# CONFIG_ACENIC_OMIT_TIGON_I is not set
1373CONFIG_DL2K=m 1377CONFIG_DL2K=m
1374CONFIG_E1000=m 1378CONFIG_E1000=m
1375CONFIG_E1000_NAPI=y
1376# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set 1379# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
1377CONFIG_E1000E=m 1380CONFIG_E1000E=m
1378CONFIG_E1000E_ENABLED=y
1379CONFIG_IP1000=m 1381CONFIG_IP1000=m
1380CONFIG_IGB=m 1382CONFIG_IGB=m
1383CONFIG_IGB_LRO=y
1381CONFIG_NS83820=m 1384CONFIG_NS83820=m
1382CONFIG_HAMACHI=m 1385CONFIG_HAMACHI=m
1383CONFIG_YELLOWFIN=m 1386CONFIG_YELLOWFIN=m
1384CONFIG_R8169=m 1387CONFIG_R8169=m
1385CONFIG_R8169_NAPI=y
1386CONFIG_R8169_VLAN=y 1388CONFIG_R8169_VLAN=y
1387CONFIG_SIS190=m 1389CONFIG_SIS190=m
1388CONFIG_SKGE=m 1390CONFIG_SKGE=m
@@ -1393,21 +1395,18 @@ CONFIG_VIA_VELOCITY=m
1393CONFIG_TIGON3=m 1395CONFIG_TIGON3=m
1394CONFIG_BNX2=m 1396CONFIG_BNX2=m
1395CONFIG_GIANFAR=m 1397CONFIG_GIANFAR=m
1396CONFIG_GFAR_NAPI=y
1397# CONFIG_UCC_GETH is not set 1398# CONFIG_UCC_GETH is not set
1398CONFIG_MV643XX_ETH=m 1399CONFIG_MV643XX_ETH=m
1399CONFIG_QLA3XXX=m 1400CONFIG_QLA3XXX=m
1400CONFIG_ATL1=m 1401CONFIG_ATL1=m
1402# CONFIG_ATL1E is not set
1401CONFIG_NETDEV_10000=y 1403CONFIG_NETDEV_10000=y
1402CONFIG_CHELSIO_T1=m 1404CONFIG_CHELSIO_T1=m
1403CONFIG_CHELSIO_T1_1G=y 1405CONFIG_CHELSIO_T1_1G=y
1404CONFIG_CHELSIO_T1_NAPI=y
1405CONFIG_CHELSIO_T3=m 1406CONFIG_CHELSIO_T3=m
1406CONFIG_IXGBE=m 1407CONFIG_IXGBE=m
1407CONFIG_IXGB=m 1408CONFIG_IXGB=m
1408CONFIG_IXGB_NAPI=y
1409CONFIG_S2IO=m 1409CONFIG_S2IO=m
1410CONFIG_S2IO_NAPI=y
1411CONFIG_MYRI10GE=m 1410CONFIG_MYRI10GE=m
1412CONFIG_NETXEN_NIC=m 1411CONFIG_NETXEN_NIC=m
1413CONFIG_NIU=m 1412CONFIG_NIU=m
@@ -1477,8 +1476,7 @@ CONFIG_ATM_IDT77252_USE_SUNI=y
1477# CONFIG_ATM_AMBASSADOR is not set 1476# CONFIG_ATM_AMBASSADOR is not set
1478# CONFIG_ATM_HORIZON is not set 1477# CONFIG_ATM_HORIZON is not set
1479# CONFIG_ATM_IA is not set 1478# CONFIG_ATM_IA is not set
1480CONFIG_ATM_FORE200E_MAYBE=m 1479# CONFIG_ATM_FORE200E is not set
1481# CONFIG_ATM_FORE200E_PCA is not set
1482CONFIG_ATM_HE=m 1480CONFIG_ATM_HE=m
1483# CONFIG_ATM_HE_USE_SUNI is not set 1481# CONFIG_ATM_HE_USE_SUNI is not set
1484CONFIG_FDDI=y 1482CONFIG_FDDI=y
@@ -1551,6 +1549,7 @@ CONFIG_MOUSE_PS2_TRACKPOINT=y
1551# CONFIG_MOUSE_PS2_TOUCHKIT is not set 1549# CONFIG_MOUSE_PS2_TOUCHKIT is not set
1552CONFIG_MOUSE_SERIAL=m 1550CONFIG_MOUSE_SERIAL=m
1553CONFIG_MOUSE_APPLETOUCH=m 1551CONFIG_MOUSE_APPLETOUCH=m
1552# CONFIG_MOUSE_BCM5974 is not set
1554# CONFIG_MOUSE_INPORT is not set 1553# CONFIG_MOUSE_INPORT is not set
1555# CONFIG_MOUSE_LOGIBM is not set 1554# CONFIG_MOUSE_LOGIBM is not set
1556# CONFIG_MOUSE_PC110PAD is not set 1555# CONFIG_MOUSE_PC110PAD is not set
@@ -1611,33 +1610,18 @@ CONFIG_SERIO_SERPORT=y
1611# CONFIG_SERIO_PCIPS2 is not set 1610# CONFIG_SERIO_PCIPS2 is not set
1612CONFIG_SERIO_LIBPS2=y 1611CONFIG_SERIO_LIBPS2=y
1613CONFIG_SERIO_RAW=m 1612CONFIG_SERIO_RAW=m
1613# CONFIG_SERIO_XILINX_XPS_PS2 is not set
1614CONFIG_GAMEPORT=m 1614CONFIG_GAMEPORT=m
1615CONFIG_GAMEPORT_NS558=m 1615CONFIG_GAMEPORT_NS558=m
1616CONFIG_GAMEPORT_L4=m 1616CONFIG_GAMEPORT_L4=m
1617CONFIG_GAMEPORT_EMU10K1=m 1617CONFIG_GAMEPORT_EMU10K1=m
1618CONFIG_GAMEPORT_FM801=m 1618CONFIG_GAMEPORT_FM801=m
1619CONFIG_INPUT_LIRC=y
1620CONFIG_LIRC_DEV=m
1621CONFIG_LIRC_ATIUSB=m
1622CONFIG_LIRC_BT829=m
1623CONFIG_LIRC_CMDIR=m
1624CONFIG_LIRC_I2C=m
1625CONFIG_LIRC_IGORPLUGUSB=m
1626CONFIG_LIRC_IMON=m
1627CONFIG_LIRC_IT87=m
1628CONFIG_LIRC_MCEUSB=m
1629CONFIG_LIRC_MCEUSB2=m
1630CONFIG_LIRC_PVR150=m
1631CONFIG_LIRC_PARALLEL=m
1632CONFIG_LIRC_SERIAL=m
1633CONFIG_LIRC_SIR=m
1634CONFIG_LIRC_STREAMZAP=m
1635CONFIG_LIRC_TTUSBIR=m
1636 1619
1637# 1620#
1638# Character devices 1621# Character devices
1639# 1622#
1640CONFIG_VT=y 1623CONFIG_VT=y
1624CONFIG_CONSOLE_TRANSLATIONS=y
1641CONFIG_VT_CONSOLE=y 1625CONFIG_VT_CONSOLE=y
1642CONFIG_HW_CONSOLE=y 1626CONFIG_HW_CONSOLE=y
1643CONFIG_VT_HW_CONSOLE_BINDING=y 1627CONFIG_VT_HW_CONSOLE_BINDING=y
@@ -1701,12 +1685,12 @@ CONFIG_SERIAL_OF_PLATFORM=y
1701# CONFIG_SERIAL_QE is not set 1685# CONFIG_SERIAL_QE is not set
1702CONFIG_UNIX98_PTYS=y 1686CONFIG_UNIX98_PTYS=y
1703# CONFIG_LEGACY_PTYS is not set 1687# CONFIG_LEGACY_PTYS is not set
1704# CONFIG_CRASH is not set
1705CONFIG_BRIQ_PANEL=m 1688CONFIG_BRIQ_PANEL=m
1706CONFIG_PRINTER=m 1689CONFIG_PRINTER=m
1707CONFIG_LP_CONSOLE=y 1690CONFIG_LP_CONSOLE=y
1708CONFIG_PPDEV=m 1691CONFIG_PPDEV=m
1709# CONFIG_HVC_RTAS is not set 1692# CONFIG_HVC_RTAS is not set
1693# CONFIG_VIRTIO_CONSOLE is not set
1710# CONFIG_IPMI_HANDLER is not set 1694# CONFIG_IPMI_HANDLER is not set
1711CONFIG_HW_RANDOM=y 1695CONFIG_HW_RANDOM=y
1712CONFIG_HW_RANDOM_VIRTIO=m 1696CONFIG_HW_RANDOM_VIRTIO=m
@@ -1728,6 +1712,7 @@ CONFIG_DEVPORT=y
1728CONFIG_I2C=y 1712CONFIG_I2C=y
1729CONFIG_I2C_BOARDINFO=y 1713CONFIG_I2C_BOARDINFO=y
1730CONFIG_I2C_CHARDEV=m 1714CONFIG_I2C_CHARDEV=m
1715CONFIG_I2C_HELPER_AUTO=y
1731CONFIG_I2C_ALGOBIT=y 1716CONFIG_I2C_ALGOBIT=y
1732CONFIG_I2C_ALGOPCA=m 1717CONFIG_I2C_ALGOPCA=m
1733 1718
@@ -1807,20 +1792,24 @@ CONFIG_SENSORS_TSL2550=m
1807# CONFIG_I2C_DEBUG_BUS is not set 1792# CONFIG_I2C_DEBUG_BUS is not set
1808# CONFIG_I2C_DEBUG_CHIP is not set 1793# CONFIG_I2C_DEBUG_CHIP is not set
1809# CONFIG_SPI is not set 1794# CONFIG_SPI is not set
1810CONFIG_HAVE_GPIO_LIB=y 1795CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
1811 1796CONFIG_ARCH_REQUIRE_GPIOLIB=y
1812# 1797CONFIG_GPIOLIB=y
1813# GPIO Support
1814#
1815# CONFIG_DEBUG_GPIO is not set 1798# CONFIG_DEBUG_GPIO is not set
1799CONFIG_GPIO_SYSFS=y
1816 1800
1817# 1801#
1818# I2C GPIO expanders: 1802# I2C GPIO expanders:
1819# 1803#
1804# CONFIG_GPIO_MAX732X is not set
1820# CONFIG_GPIO_PCA953X is not set 1805# CONFIG_GPIO_PCA953X is not set
1821# CONFIG_GPIO_PCF857X is not set 1806# CONFIG_GPIO_PCF857X is not set
1822 1807
1823# 1808#
1809# PCI GPIO expanders:
1810#
1811
1812#
1824# SPI GPIO expanders: 1813# SPI GPIO expanders:
1825# 1814#
1826CONFIG_W1=m 1815CONFIG_W1=m
@@ -1850,6 +1839,7 @@ CONFIG_APM_POWER=m
1850CONFIG_BATTERY_PMU=m 1839CONFIG_BATTERY_PMU=m
1851CONFIG_HWMON=m 1840CONFIG_HWMON=m
1852CONFIG_HWMON_VID=m 1841CONFIG_HWMON_VID=m
1842# CONFIG_SENSORS_AD7414 is not set
1853CONFIG_SENSORS_AD7418=m 1843CONFIG_SENSORS_AD7418=m
1854CONFIG_SENSORS_ADM1021=m 1844CONFIG_SENSORS_ADM1021=m
1855CONFIG_SENSORS_ADM1025=m 1845CONFIG_SENSORS_ADM1025=m
@@ -1913,8 +1903,9 @@ CONFIG_WATCHDOG=y
1913# Watchdog Device Drivers 1903# Watchdog Device Drivers
1914# 1904#
1915CONFIG_SOFT_WATCHDOG=m 1905CONFIG_SOFT_WATCHDOG=m
1906# CONFIG_ALIM7101_WDT is not set
1916# CONFIG_MPC5200_WDT is not set 1907# CONFIG_MPC5200_WDT is not set
1917CONFIG_83xx_WDT=m 1908# CONFIG_8xxx_WDT is not set
1918CONFIG_WATCHDOG_RTAS=m 1909CONFIG_WATCHDOG_RTAS=m
1919 1910
1920# 1911#
@@ -1953,8 +1944,10 @@ CONFIG_SSB_DRIVER_PCICORE=y
1953# 1944#
1954# Multifunction device drivers 1945# Multifunction device drivers
1955# 1946#
1947# CONFIG_MFD_CORE is not set
1956CONFIG_MFD_SM501=m 1948CONFIG_MFD_SM501=m
1957# CONFIG_HTC_PASIC3 is not set 1949# CONFIG_HTC_PASIC3 is not set
1950# CONFIG_MFD_TMIO is not set
1958 1951
1959# 1952#
1960# Multimedia devices 1953# Multimedia devices
@@ -1993,6 +1986,7 @@ CONFIG_MEDIA_TUNER_QT1010=m
1993CONFIG_MEDIA_TUNER_XC2028=m 1986CONFIG_MEDIA_TUNER_XC2028=m
1994CONFIG_MEDIA_TUNER_XC5000=m 1987CONFIG_MEDIA_TUNER_XC5000=m
1995CONFIG_MEDIA_TUNER_MXL5005S=m 1988CONFIG_MEDIA_TUNER_MXL5005S=m
1989CONFIG_MEDIA_TUNER_MXL5007T=m
1996CONFIG_VIDEO_V4L2=m 1990CONFIG_VIDEO_V4L2=m
1997CONFIG_VIDEO_V4L1=m 1991CONFIG_VIDEO_V4L1=m
1998CONFIG_VIDEOBUF_GEN=m 1992CONFIG_VIDEOBUF_GEN=m
@@ -2000,13 +1994,13 @@ CONFIG_VIDEOBUF_DMA_SG=m
2000CONFIG_VIDEOBUF_VMALLOC=m 1994CONFIG_VIDEOBUF_VMALLOC=m
2001CONFIG_VIDEOBUF_DVB=m 1995CONFIG_VIDEOBUF_DVB=m
2002CONFIG_VIDEO_BTCX=m 1996CONFIG_VIDEO_BTCX=m
2003CONFIG_VIDEO_IR_I2C=m
2004CONFIG_VIDEO_IR=m 1997CONFIG_VIDEO_IR=m
2005CONFIG_VIDEO_TVEEPROM=m 1998CONFIG_VIDEO_TVEEPROM=m
2006CONFIG_VIDEO_TUNER=m 1999CONFIG_VIDEO_TUNER=m
2007CONFIG_VIDEO_CAPTURE_DRIVERS=y 2000CONFIG_VIDEO_CAPTURE_DRIVERS=y
2008# CONFIG_VIDEO_ADV_DEBUG is not set 2001# CONFIG_VIDEO_ADV_DEBUG is not set
2009# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set 2002# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
2003CONFIG_VIDEO_IR_I2C=m
2010 2004
2011# 2005#
2012# Encoders/decoders and other helper chips 2006# Encoders/decoders and other helper chips
@@ -2108,6 +2102,8 @@ CONFIG_VIDEO_CX18=m
2108# CONFIG_VIDEO_CAFE_CCIC is not set 2102# CONFIG_VIDEO_CAFE_CCIC is not set
2109CONFIG_V4L_USB_DRIVERS=y 2103CONFIG_V4L_USB_DRIVERS=y
2110CONFIG_USB_VIDEO_CLASS=m 2104CONFIG_USB_VIDEO_CLASS=m
2105CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
2106CONFIG_USB_GSPCA=m
2111CONFIG_VIDEO_PVRUSB2=m 2107CONFIG_VIDEO_PVRUSB2=m
2112CONFIG_VIDEO_PVRUSB2_SYSFS=y 2108CONFIG_VIDEO_PVRUSB2_SYSFS=y
2113CONFIG_VIDEO_PVRUSB2_DVB=y 2109CONFIG_VIDEO_PVRUSB2_DVB=y
@@ -2133,11 +2129,14 @@ CONFIG_USB_PWC=m
2133# CONFIG_USB_PWC_DEBUG is not set 2129# CONFIG_USB_PWC_DEBUG is not set
2134CONFIG_USB_ZR364XX=m 2130CONFIG_USB_ZR364XX=m
2135CONFIG_USB_STKWEBCAM=m 2131CONFIG_USB_STKWEBCAM=m
2132# CONFIG_USB_S2255 is not set
2136CONFIG_SOC_CAMERA=m 2133CONFIG_SOC_CAMERA=m
2137CONFIG_SOC_CAMERA_MT9M001=m 2134CONFIG_SOC_CAMERA_MT9M001=m
2138# CONFIG_MT9M001_PCA9536_SWITCH is not set 2135# CONFIG_MT9M001_PCA9536_SWITCH is not set
2139CONFIG_SOC_CAMERA_MT9V022=m 2136CONFIG_SOC_CAMERA_MT9V022=m
2140# CONFIG_MT9V022_PCA9536_SWITCH is not set 2137# CONFIG_MT9V022_PCA9536_SWITCH is not set
2138# CONFIG_SOC_CAMERA_PLATFORM is not set
2139# CONFIG_VIDEO_SH_MOBILE_CEU is not set
2141CONFIG_RADIO_ADAPTERS=y 2140CONFIG_RADIO_ADAPTERS=y
2142# CONFIG_RADIO_CADET is not set 2141# CONFIG_RADIO_CADET is not set
2143# CONFIG_RADIO_RTRACK is not set 2142# CONFIG_RADIO_RTRACK is not set
@@ -2194,6 +2193,8 @@ CONFIG_DVB_USB_DTT200U=m
2194CONFIG_DVB_USB_OPERA1=m 2193CONFIG_DVB_USB_OPERA1=m
2195CONFIG_DVB_USB_AF9005=m 2194CONFIG_DVB_USB_AF9005=m
2196CONFIG_DVB_USB_AF9005_REMOTE=m 2195CONFIG_DVB_USB_AF9005_REMOTE=m
2196# CONFIG_DVB_USB_DW2102 is not set
2197# CONFIG_DVB_USB_ANYSEE is not set
2197CONFIG_DVB_TTUSB_BUDGET=m 2198CONFIG_DVB_TTUSB_BUDGET=m
2198CONFIG_DVB_TTUSB_DEC=m 2199CONFIG_DVB_TTUSB_DEC=m
2199CONFIG_DVB_CINERGYT2=m 2200CONFIG_DVB_CINERGYT2=m
@@ -2203,6 +2204,7 @@ CONFIG_DVB_CINERGYT2_STREAM_BUF_SIZE=512
2203CONFIG_DVB_CINERGYT2_QUERY_INTERVAL=250 2204CONFIG_DVB_CINERGYT2_QUERY_INTERVAL=250
2204CONFIG_DVB_CINERGYT2_ENABLE_RC_INPUT_DEVICE=y 2205CONFIG_DVB_CINERGYT2_ENABLE_RC_INPUT_DEVICE=y
2205CONFIG_DVB_CINERGYT2_RC_QUERY_INTERVAL=100 2206CONFIG_DVB_CINERGYT2_RC_QUERY_INTERVAL=100
2207# CONFIG_DVB_SIANO_SMS1XXX is not set
2206 2208
2207# 2209#
2208# Supported FlexCopII (B2C2) Adapters 2210# Supported FlexCopII (B2C2) Adapters
@@ -2253,6 +2255,7 @@ CONFIG_DVB_SP8870=m
2253CONFIG_DVB_SP887X=m 2255CONFIG_DVB_SP887X=m
2254CONFIG_DVB_CX22700=m 2256CONFIG_DVB_CX22700=m
2255CONFIG_DVB_CX22702=m 2257CONFIG_DVB_CX22702=m
2258# CONFIG_DVB_DRX397XD is not set
2256CONFIG_DVB_L64781=m 2259CONFIG_DVB_L64781=m
2257CONFIG_DVB_TDA1004X=m 2260CONFIG_DVB_TDA1004X=m
2258CONFIG_DVB_NXT6000=m 2261CONFIG_DVB_NXT6000=m
@@ -2389,12 +2392,15 @@ CONFIG_FB_TRIDENT=m
2389CONFIG_FB_TRIDENT_ACCEL=y 2392CONFIG_FB_TRIDENT_ACCEL=y
2390# CONFIG_FB_ARK is not set 2393# CONFIG_FB_ARK is not set
2391# CONFIG_FB_PM3 is not set 2394# CONFIG_FB_PM3 is not set
2395# CONFIG_FB_CARMINE is not set
2392# CONFIG_FB_FSL_DIU is not set 2396# CONFIG_FB_FSL_DIU is not set
2393CONFIG_FB_SM501=m 2397CONFIG_FB_SM501=m
2394CONFIG_FB_IBM_GXT4500=y 2398CONFIG_FB_IBM_GXT4500=y
2395# CONFIG_FB_VIRTUAL is not set 2399# CONFIG_FB_VIRTUAL is not set
2396CONFIG_BACKLIGHT_LCD_SUPPORT=y 2400CONFIG_BACKLIGHT_LCD_SUPPORT=y
2397CONFIG_LCD_CLASS_DEVICE=m 2401CONFIG_LCD_CLASS_DEVICE=m
2402# CONFIG_LCD_ILI9320 is not set
2403CONFIG_LCD_PLATFORM=m
2398CONFIG_BACKLIGHT_CLASS_DEVICE=y 2404CONFIG_BACKLIGHT_CLASS_DEVICE=y
2399# CONFIG_BACKLIGHT_CORGI is not set 2405# CONFIG_BACKLIGHT_CORGI is not set
2400 2406
@@ -2613,6 +2619,7 @@ CONFIG_USB_DEVICEFS=y
2613# CONFIG_USB_DYNAMIC_MINORS is not set 2619# CONFIG_USB_DYNAMIC_MINORS is not set
2614CONFIG_USB_SUSPEND=y 2620CONFIG_USB_SUSPEND=y
2615# CONFIG_USB_OTG is not set 2621# CONFIG_USB_OTG is not set
2622CONFIG_USB_MON=y
2616 2623
2617# 2624#
2618# USB Host Controller Drivers 2625# USB Host Controller Drivers
@@ -2640,6 +2647,7 @@ CONFIG_USB_U132_HCD=m
2640CONFIG_USB_SL811_HCD=m 2647CONFIG_USB_SL811_HCD=m
2641# CONFIG_USB_SL811_CS is not set 2648# CONFIG_USB_SL811_CS is not set
2642# CONFIG_USB_R8A66597_HCD is not set 2649# CONFIG_USB_R8A66597_HCD is not set
2650# CONFIG_USB_MUSB_HDRC is not set
2643 2651
2644# 2652#
2645# USB Device Class drivers 2653# USB Device Class drivers
@@ -2668,6 +2676,7 @@ CONFIG_USB_STORAGE_JUMPSHOT=y
2668CONFIG_USB_STORAGE_ALAUDA=y 2676CONFIG_USB_STORAGE_ALAUDA=y
2669CONFIG_USB_STORAGE_ONETOUCH=y 2677CONFIG_USB_STORAGE_ONETOUCH=y
2670CONFIG_USB_STORAGE_KARMA=y 2678CONFIG_USB_STORAGE_KARMA=y
2679# CONFIG_USB_STORAGE_SIERRA is not set
2671CONFIG_USB_STORAGE_CYPRESS_ATACB=y 2680CONFIG_USB_STORAGE_CYPRESS_ATACB=y
2672# CONFIG_USB_LIBUSUAL is not set 2681# CONFIG_USB_LIBUSUAL is not set
2673 2682
@@ -2676,7 +2685,6 @@ CONFIG_USB_STORAGE_CYPRESS_ATACB=y
2676# 2685#
2677CONFIG_USB_MDC800=m 2686CONFIG_USB_MDC800=m
2678CONFIG_USB_MICROTEK=m 2687CONFIG_USB_MICROTEK=m
2679CONFIG_USB_MON=y
2680 2688
2681# 2689#
2682# USB port drivers 2690# USB port drivers
@@ -2686,7 +2694,6 @@ CONFIG_USB_SERIAL=m
2686CONFIG_USB_EZUSB=y 2694CONFIG_USB_EZUSB=y
2687CONFIG_USB_SERIAL_GENERIC=y 2695CONFIG_USB_SERIAL_GENERIC=y
2688CONFIG_USB_SERIAL_AIRCABLE=m 2696CONFIG_USB_SERIAL_AIRCABLE=m
2689CONFIG_USB_SERIAL_AIRPRIME=m
2690CONFIG_USB_SERIAL_ARK3116=m 2697CONFIG_USB_SERIAL_ARK3116=m
2691CONFIG_USB_SERIAL_BELKIN=m 2698CONFIG_USB_SERIAL_BELKIN=m
2692CONFIG_USB_SERIAL_CH341=m 2699CONFIG_USB_SERIAL_CH341=m
@@ -2734,7 +2741,6 @@ CONFIG_USB_SERIAL_DEBUG=m
2734CONFIG_USB_EMI62=m 2741CONFIG_USB_EMI62=m
2735CONFIG_USB_EMI26=m 2742CONFIG_USB_EMI26=m
2736CONFIG_USB_ADUTUX=m 2743CONFIG_USB_ADUTUX=m
2737CONFIG_USB_AUERSWALD=m
2738# CONFIG_USB_RIO500 is not set 2744# CONFIG_USB_RIO500 is not set
2739CONFIG_USB_LEGOTOWER=m 2745CONFIG_USB_LEGOTOWER=m
2740CONFIG_USB_LCD=m 2746CONFIG_USB_LCD=m
@@ -2770,7 +2776,9 @@ CONFIG_LEDS_CLASS=y
2770# 2776#
2771# LED drivers 2777# LED drivers
2772# 2778#
2779# CONFIG_LEDS_PCA9532 is not set
2773# CONFIG_LEDS_GPIO is not set 2780# CONFIG_LEDS_GPIO is not set
2781# CONFIG_LEDS_PCA955X is not set
2774 2782
2775# 2783#
2776# LED Triggers 2784# LED Triggers
@@ -2853,6 +2861,7 @@ CONFIG_KS0108_PORT=0x378
2853CONFIG_KS0108_DELAY=2 2861CONFIG_KS0108_DELAY=2
2854CONFIG_UIO=m 2862CONFIG_UIO=m
2855CONFIG_UIO_CIF=m 2863CONFIG_UIO_CIF=m
2864CONFIG_UIO_PDRV=m
2856CONFIG_UIO_SMX=m 2865CONFIG_UIO_SMX=m
2857 2866
2858# 2867#
@@ -2899,6 +2908,7 @@ CONFIG_GFS2_FS_LOCKING_DLM=m
2899CONFIG_OCFS2_FS=m 2908CONFIG_OCFS2_FS=m
2900CONFIG_OCFS2_FS_O2CB=m 2909CONFIG_OCFS2_FS_O2CB=m
2901CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m 2910CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m
2911CONFIG_OCFS2_FS_STATS=y
2902# CONFIG_OCFS2_DEBUG_MASKLOG is not set 2912# CONFIG_OCFS2_DEBUG_MASKLOG is not set
2903# CONFIG_OCFS2_DEBUG_FS is not set 2913# CONFIG_OCFS2_DEBUG_FS is not set
2904CONFIG_DNOTIFY=y 2914CONFIG_DNOTIFY=y
@@ -2959,11 +2969,9 @@ CONFIG_BEFS_FS=m
2959CONFIG_BFS_FS=m 2969CONFIG_BFS_FS=m
2960CONFIG_EFS_FS=m 2970CONFIG_EFS_FS=m
2961CONFIG_CRAMFS=m 2971CONFIG_CRAMFS=m
2962CONFIG_SQUASHFS=m
2963# CONFIG_SQUASHFS_EMBEDDED is not set
2964CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
2965CONFIG_VXFS_FS=m 2972CONFIG_VXFS_FS=m
2966CONFIG_MINIX_FS=m 2973CONFIG_MINIX_FS=m
2974CONFIG_OMFS_FS=m
2967# CONFIG_HPFS_FS is not set 2975# CONFIG_HPFS_FS is not set
2968CONFIG_QNX4FS_FS=m 2976CONFIG_QNX4FS_FS=m
2969CONFIG_ROMFS_FS=m 2977CONFIG_ROMFS_FS=m
@@ -2988,7 +2996,6 @@ CONFIG_NFS_ACL_SUPPORT=m
2988CONFIG_NFS_COMMON=y 2996CONFIG_NFS_COMMON=y
2989CONFIG_SUNRPC=m 2997CONFIG_SUNRPC=m
2990CONFIG_SUNRPC_GSS=m 2998CONFIG_SUNRPC_GSS=m
2991CONFIG_SUNRPC_BIND34=y
2992CONFIG_RPCSEC_GSS_KRB5=m 2999CONFIG_RPCSEC_GSS_KRB5=m
2993CONFIG_RPCSEC_GSS_SPKM3=m 3000CONFIG_RPCSEC_GSS_SPKM3=m
2994# CONFIG_SMB_FS is not set 3001# CONFIG_SMB_FS is not set
@@ -3011,7 +3018,6 @@ CONFIG_NCPFS_SMALLDOS=y
3011CONFIG_NCPFS_NLS=y 3018CONFIG_NCPFS_NLS=y
3012CONFIG_NCPFS_EXTRAS=y 3019CONFIG_NCPFS_EXTRAS=y
3013CONFIG_CODA_FS=m 3020CONFIG_CODA_FS=m
3014# CONFIG_CODA_FS_OLD_API is not set
3015# CONFIG_AFS_FS is not set 3021# CONFIG_AFS_FS is not set
3016CONFIG_9P_FS=m 3022CONFIG_9P_FS=m
3017 3023
@@ -3087,7 +3093,7 @@ CONFIG_BITREVERSE=y
3087# CONFIG_GENERIC_FIND_FIRST_BIT is not set 3093# CONFIG_GENERIC_FIND_FIRST_BIT is not set
3088CONFIG_CRC_CCITT=m 3094CONFIG_CRC_CCITT=m
3089CONFIG_CRC16=m 3095CONFIG_CRC16=m
3090CONFIG_CRC_T10DIF=m 3096CONFIG_CRC_T10DIF=y
3091CONFIG_CRC_ITU_T=m 3097CONFIG_CRC_ITU_T=m
3092CONFIG_CRC32=y 3098CONFIG_CRC32=y
3093# CONFIG_CRC7 is not set 3099# CONFIG_CRC7 is not set
@@ -3120,6 +3126,8 @@ CONFIG_HEADERS_CHECK=y
3120CONFIG_DEBUG_KERNEL=y 3126CONFIG_DEBUG_KERNEL=y
3121CONFIG_DEBUG_SHIRQ=y 3127CONFIG_DEBUG_SHIRQ=y
3122CONFIG_DETECT_SOFTLOCKUP=y 3128CONFIG_DETECT_SOFTLOCKUP=y
3129# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
3130CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
3123CONFIG_SCHED_DEBUG=y 3131CONFIG_SCHED_DEBUG=y
3124CONFIG_SCHEDSTATS=y 3132CONFIG_SCHEDSTATS=y
3125CONFIG_TIMER_STATS=y 3133CONFIG_TIMER_STATS=y
@@ -3143,6 +3151,7 @@ CONFIG_DEBUG_BUGVERBOSE=y
3143CONFIG_DEBUG_INFO=y 3151CONFIG_DEBUG_INFO=y
3144CONFIG_DEBUG_VM=y 3152CONFIG_DEBUG_VM=y
3145CONFIG_DEBUG_WRITECOUNT=y 3153CONFIG_DEBUG_WRITECOUNT=y
3154CONFIG_DEBUG_MEMORY_INIT=y
3146CONFIG_DEBUG_LIST=y 3155CONFIG_DEBUG_LIST=y
3147CONFIG_DEBUG_SG=y 3156CONFIG_DEBUG_SG=y
3148CONFIG_FRAME_POINTER=y 3157CONFIG_FRAME_POINTER=y
@@ -3158,6 +3167,7 @@ CONFIG_FAIL_MAKE_REQUEST=y
3158CONFIG_FAULT_INJECTION_DEBUG_FS=y 3167CONFIG_FAULT_INJECTION_DEBUG_FS=y
3159CONFIG_FAULT_INJECTION_STACKTRACE_FILTER=y 3168CONFIG_FAULT_INJECTION_STACKTRACE_FILTER=y
3160CONFIG_LATENCYTOP=y 3169CONFIG_LATENCYTOP=y
3170CONFIG_SYSCTL_SYSCALL_CHECK=y
3161CONFIG_HAVE_FTRACE=y 3171CONFIG_HAVE_FTRACE=y
3162CONFIG_HAVE_DYNAMIC_FTRACE=y 3172CONFIG_HAVE_DYNAMIC_FTRACE=y
3163CONFIG_TRACER_MAX_TRACE=y 3173CONFIG_TRACER_MAX_TRACE=y
@@ -3168,16 +3178,18 @@ CONFIG_CONTEXT_SWITCH_TRACER=y
3168CONFIG_DYNAMIC_FTRACE=y 3178CONFIG_DYNAMIC_FTRACE=y
3169# CONFIG_FTRACE_STARTUP_TEST is not set 3179# CONFIG_FTRACE_STARTUP_TEST is not set
3170# CONFIG_FIREWIRE_OHCI_REMOTE_DMA is not set 3180# CONFIG_FIREWIRE_OHCI_REMOTE_DMA is not set
3181# CONFIG_BUILD_DOCSRC is not set
3171# CONFIG_SAMPLES is not set 3182# CONFIG_SAMPLES is not set
3183CONFIG_HAVE_ARCH_KGDB=y
3184# CONFIG_KGDB is not set
3172CONFIG_DEBUG_STACKOVERFLOW=y 3185CONFIG_DEBUG_STACKOVERFLOW=y
3173CONFIG_DEBUG_STACK_USAGE=y 3186CONFIG_DEBUG_STACK_USAGE=y
3174CONFIG_DEBUGGER=y
3175# CONFIG_CODE_PATCHING_SELFTEST is not set 3187# CONFIG_CODE_PATCHING_SELFTEST is not set
3176# CONFIG_FTR_FIXUP_SELFTEST is not set 3188# CONFIG_FTR_FIXUP_SELFTEST is not set
3177# CONFIG_KGDB_CONSOLE is not set
3178CONFIG_XMON=y 3189CONFIG_XMON=y
3179# CONFIG_XMON_DEFAULT is not set 3190# CONFIG_XMON_DEFAULT is not set
3180CONFIG_XMON_DISASSEMBLY=y 3191CONFIG_XMON_DISASSEMBLY=y
3192CONFIG_DEBUGGER=y
3181CONFIG_IRQSTACKS=y 3193CONFIG_IRQSTACKS=y
3182# CONFIG_VIRQ_DEBUG is not set 3194# CONFIG_VIRQ_DEBUG is not set
3183# CONFIG_BDI_SWITCH is not set 3195# CONFIG_BDI_SWITCH is not set
diff --git a/arch/powerpc/configs/pq2fads_defconfig b/arch/powerpc/configs/pq2fads_defconfig
index bc3bf62ddc2f..b390b7476649 100644
--- a/arch/powerpc/configs/pq2fads_defconfig
+++ b/arch/powerpc/configs/pq2fads_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc5 3# Linux kernel version: 2.6.27-rc4
4# Mon Jun 9 08:52:18 2008 4# Thu Aug 21 00:52:13 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -15,6 +15,7 @@ CONFIG_6xx=y
15# CONFIG_44x is not set 15# CONFIG_44x is not set
16# CONFIG_E200 is not set 16# CONFIG_E200 is not set
17CONFIG_PPC_FPU=y 17CONFIG_PPC_FPU=y
18# CONFIG_ALTIVEC is not set
18CONFIG_PPC_STD_MMU=y 19CONFIG_PPC_STD_MMU=y
19CONFIG_PPC_STD_MMU_32=y 20CONFIG_PPC_STD_MMU_32=y
20# CONFIG_PPC_MM_SLICES is not set 21# CONFIG_PPC_MM_SLICES is not set
@@ -31,12 +32,14 @@ CONFIG_GENERIC_HARDIRQS=y
31# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set 32# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
32CONFIG_IRQ_PER_CPU=y 33CONFIG_IRQ_PER_CPU=y
33CONFIG_STACKTRACE_SUPPORT=y 34CONFIG_STACKTRACE_SUPPORT=y
35CONFIG_HAVE_LATENCYTOP_SUPPORT=y
34CONFIG_LOCKDEP_SUPPORT=y 36CONFIG_LOCKDEP_SUPPORT=y
35CONFIG_RWSEM_XCHGADD_ALGORITHM=y 37CONFIG_RWSEM_XCHGADD_ALGORITHM=y
36CONFIG_ARCH_HAS_ILOG2_U32=y 38CONFIG_ARCH_HAS_ILOG2_U32=y
37CONFIG_GENERIC_HWEIGHT=y 39CONFIG_GENERIC_HWEIGHT=y
38CONFIG_GENERIC_CALIBRATE_DELAY=y 40CONFIG_GENERIC_CALIBRATE_DELAY=y
39CONFIG_GENERIC_FIND_NEXT_BIT=y 41CONFIG_GENERIC_FIND_NEXT_BIT=y
42CONFIG_GENERIC_GPIO=y
40# CONFIG_ARCH_NO_VIRT_TO_BUS is not set 43# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
41CONFIG_PPC=y 44CONFIG_PPC=y
42CONFIG_EARLY_PRINTK=y 45CONFIG_EARLY_PRINTK=y
@@ -45,11 +48,13 @@ CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
45CONFIG_ARCH_MAY_HAVE_PC_FDC=y 48CONFIG_ARCH_MAY_HAVE_PC_FDC=y
46CONFIG_PPC_OF=y 49CONFIG_PPC_OF=y
47CONFIG_OF=y 50CONFIG_OF=y
48# CONFIG_PPC_UDBG_16550 is not set 51CONFIG_PPC_UDBG_16550=y
49# CONFIG_GENERIC_TBSYNC is not set 52# CONFIG_GENERIC_TBSYNC is not set
50CONFIG_AUDIT_ARCH=y 53CONFIG_AUDIT_ARCH=y
51CONFIG_GENERIC_BUG=y 54CONFIG_GENERIC_BUG=y
52CONFIG_DEFAULT_UIMAGE=y 55CONFIG_DEFAULT_UIMAGE=y
56CONFIG_HIBERNATE_32=y
57CONFIG_ARCH_HIBERNATION_POSSIBLE=y
53# CONFIG_PPC_DCR_NATIVE is not set 58# CONFIG_PPC_DCR_NATIVE is not set
54# CONFIG_PPC_DCR_MMIO is not set 59# CONFIG_PPC_DCR_MMIO is not set
55CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 60CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
@@ -82,7 +87,6 @@ CONFIG_CC_OPTIMIZE_FOR_SIZE=y
82CONFIG_SYSCTL=y 87CONFIG_SYSCTL=y
83CONFIG_EMBEDDED=y 88CONFIG_EMBEDDED=y
84CONFIG_SYSCTL_SYSCALL=y 89CONFIG_SYSCTL_SYSCALL=y
85CONFIG_SYSCTL_SYSCALL_CHECK=y
86CONFIG_KALLSYMS=y 90CONFIG_KALLSYMS=y
87CONFIG_KALLSYMS_ALL=y 91CONFIG_KALLSYMS_ALL=y
88# CONFIG_KALLSYMS_EXTRA_PASS is not set 92# CONFIG_KALLSYMS_EXTRA_PASS is not set
@@ -90,6 +94,7 @@ CONFIG_HOTPLUG=y
90CONFIG_PRINTK=y 94CONFIG_PRINTK=y
91CONFIG_BUG=y 95CONFIG_BUG=y
92CONFIG_ELF_CORE=y 96CONFIG_ELF_CORE=y
97CONFIG_PCSPKR_PLATFORM=y
93CONFIG_COMPAT_BRK=y 98CONFIG_COMPAT_BRK=y
94CONFIG_BASE_FULL=y 99CONFIG_BASE_FULL=y
95CONFIG_FUTEX=y 100CONFIG_FUTEX=y
@@ -107,10 +112,16 @@ CONFIG_SLUB=y
107# CONFIG_PROFILING is not set 112# CONFIG_PROFILING is not set
108# CONFIG_MARKERS is not set 113# CONFIG_MARKERS is not set
109CONFIG_HAVE_OPROFILE=y 114CONFIG_HAVE_OPROFILE=y
115CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
116CONFIG_HAVE_IOREMAP_PROT=y
110CONFIG_HAVE_KPROBES=y 117CONFIG_HAVE_KPROBES=y
111CONFIG_HAVE_KRETPROBES=y 118CONFIG_HAVE_KRETPROBES=y
119CONFIG_HAVE_ARCH_TRACEHOOK=y
112# CONFIG_HAVE_DMA_ATTRS is not set 120# CONFIG_HAVE_DMA_ATTRS is not set
121# CONFIG_USE_GENERIC_SMP_HELPERS is not set
122CONFIG_HAVE_CLK=y
113CONFIG_PROC_PAGE_MONITOR=y 123CONFIG_PROC_PAGE_MONITOR=y
124# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
114CONFIG_SLABINFO=y 125CONFIG_SLABINFO=y
115CONFIG_RT_MUTEXES=y 126CONFIG_RT_MUTEXES=y
116# CONFIG_TINY_SHMEM is not set 127# CONFIG_TINY_SHMEM is not set
@@ -120,6 +131,7 @@ CONFIG_BLOCK=y
120# CONFIG_LBD is not set 131# CONFIG_LBD is not set
121# CONFIG_BLK_DEV_IO_TRACE is not set 132# CONFIG_BLK_DEV_IO_TRACE is not set
122# CONFIG_LSF is not set 133# CONFIG_LSF is not set
134# CONFIG_BLK_DEV_INTEGRITY is not set
123 135
124# 136#
125# IO Schedulers 137# IO Schedulers
@@ -138,33 +150,43 @@ CONFIG_CLASSIC_RCU=y
138# 150#
139# Platform support 151# Platform support
140# 152#
141# CONFIG_PPC_MULTIPLATFORM is not set 153CONFIG_PPC_MULTIPLATFORM=y
142CONFIG_PPC_82xx=y 154CONFIG_CLASSIC32=y
143# CONFIG_PPC_83xx is not set 155CONFIG_PPC_CHRP=y
144# CONFIG_PPC_86xx is not set 156# CONFIG_MPC5121_ADS is not set
145# CONFIG_PPC_MPC512x is not set 157# CONFIG_MPC5121_GENERIC is not set
146# CONFIG_PPC_MPC5121 is not set 158# CONFIG_PPC_MPC52xx is not set
159CONFIG_PPC_PMAC=y
147# CONFIG_PPC_CELL is not set 160# CONFIG_PPC_CELL is not set
148# CONFIG_PPC_CELL_NATIVE is not set 161# CONFIG_PPC_CELL_NATIVE is not set
162CONFIG_PPC_82xx=y
149# CONFIG_MPC8272_ADS is not set 163# CONFIG_MPC8272_ADS is not set
150CONFIG_PQ2FADS=y 164CONFIG_PQ2FADS=y
151# CONFIG_EP8248E is not set 165# CONFIG_EP8248E is not set
152CONFIG_PQ2ADS=y 166CONFIG_PQ2ADS=y
153CONFIG_8260=y 167CONFIG_8260=y
154CONFIG_PQ2_ADS_PCI_PIC=y 168CONFIG_PQ2_ADS_PCI_PIC=y
169# CONFIG_PPC_83xx is not set
170# CONFIG_PPC_86xx is not set
171# CONFIG_EMBEDDED6xx is not set
172CONFIG_PPC_NATIVE=y
173# CONFIG_UDBG_RTAS_CONSOLE is not set
155# CONFIG_IPIC is not set 174# CONFIG_IPIC is not set
156# CONFIG_MPIC is not set 175CONFIG_MPIC=y
157# CONFIG_MPIC_WEIRD is not set 176# CONFIG_MPIC_WEIRD is not set
158# CONFIG_PPC_I8259 is not set 177CONFIG_PPC_I8259=y
159# CONFIG_PPC_RTAS is not set 178CONFIG_PPC_RTAS=y
179# CONFIG_RTAS_ERROR_LOGGING is not set
180CONFIG_RTAS_PROC=y
160# CONFIG_MMIO_NVRAM is not set 181# CONFIG_MMIO_NVRAM is not set
161# CONFIG_PPC_MPC106 is not set 182CONFIG_PPC_MPC106=y
162# CONFIG_PPC_970_NAP is not set 183# CONFIG_PPC_970_NAP is not set
163# CONFIG_PPC_INDIRECT_IO is not set 184# CONFIG_PPC_INDIRECT_IO is not set
164# CONFIG_GENERIC_IOMAP is not set 185# CONFIG_GENERIC_IOMAP is not set
165# CONFIG_CPU_FREQ is not set 186# CONFIG_CPU_FREQ is not set
187# CONFIG_PPC601_SYNC_FIX is not set
188# CONFIG_TAU is not set
166CONFIG_CPM2=y 189CONFIG_CPM2=y
167CONFIG_PPC_CPM_NEW_BINDING=y
168# CONFIG_FSL_ULI1575 is not set 190# CONFIG_FSL_ULI1575 is not set
169CONFIG_CPM=y 191CONFIG_CPM=y
170 192
@@ -181,7 +203,7 @@ CONFIG_HZ_250=y
181# CONFIG_HZ_300 is not set 203# CONFIG_HZ_300 is not set
182# CONFIG_HZ_1000 is not set 204# CONFIG_HZ_1000 is not set
183CONFIG_HZ=250 205CONFIG_HZ=250
184# CONFIG_SCHED_HRTICK is not set 206CONFIG_SCHED_HRTICK=y
185CONFIG_PREEMPT_NONE=y 207CONFIG_PREEMPT_NONE=y
186# CONFIG_PREEMPT_VOLUNTARY is not set 208# CONFIG_PREEMPT_VOLUNTARY is not set
187# CONFIG_PREEMPT is not set 209# CONFIG_PREEMPT is not set
@@ -199,6 +221,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
199# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set 221# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
200CONFIG_PAGEFLAGS_EXTENDED=y 222CONFIG_PAGEFLAGS_EXTENDED=y
201CONFIG_SPLIT_PTLOCK_CPUS=4 223CONFIG_SPLIT_PTLOCK_CPUS=4
224CONFIG_MIGRATION=y
202# CONFIG_RESOURCES_64BIT is not set 225# CONFIG_RESOURCES_64BIT is not set
203CONFIG_ZONE_DMA_FLAG=1 226CONFIG_ZONE_DMA_FLAG=1
204CONFIG_BOUNCE=y 227CONFIG_BOUNCE=y
@@ -206,6 +229,7 @@ CONFIG_VIRT_TO_BUS=y
206CONFIG_FORCE_MAX_ZONEORDER=11 229CONFIG_FORCE_MAX_ZONEORDER=11
207CONFIG_PROC_DEVICETREE=y 230CONFIG_PROC_DEVICETREE=y
208# CONFIG_CMDLINE_BOOL is not set 231# CONFIG_CMDLINE_BOOL is not set
232CONFIG_EXTRA_TARGETS=""
209# CONFIG_PM is not set 233# CONFIG_PM is not set
210CONFIG_SECCOMP=y 234CONFIG_SECCOMP=y
211CONFIG_ISA_DMA_API=y 235CONFIG_ISA_DMA_API=y
@@ -213,9 +237,11 @@ CONFIG_ISA_DMA_API=y
213# 237#
214# Bus options 238# Bus options
215# 239#
240# CONFIG_ISA is not set
216CONFIG_ZONE_DMA=y 241CONFIG_ZONE_DMA=y
217CONFIG_PPC_INDIRECT_PCI=y 242CONFIG_PPC_INDIRECT_PCI=y
218CONFIG_FSL_SOC=y 243CONFIG_FSL_SOC=y
244CONFIG_PPC_PCI_CHOICE=y
219CONFIG_PCI=y 245CONFIG_PCI=y
220CONFIG_PCI_DOMAINS=y 246CONFIG_PCI_DOMAINS=y
221CONFIG_PCI_SYSCALL=y 247CONFIG_PCI_SYSCALL=y
@@ -243,10 +269,6 @@ CONFIG_PAGE_OFFSET=0xc0000000
243CONFIG_KERNEL_START=0xc0000000 269CONFIG_KERNEL_START=0xc0000000
244CONFIG_PHYSICAL_START=0x00000000 270CONFIG_PHYSICAL_START=0x00000000
245CONFIG_TASK_SIZE=0xc0000000 271CONFIG_TASK_SIZE=0xc0000000
246
247#
248# Networking
249#
250CONFIG_NET=y 272CONFIG_NET=y
251 273
252# 274#
@@ -447,9 +469,11 @@ CONFIG_MTD_PHYSMAP_OF=y
447# 469#
448# CONFIG_MTD_UBI is not set 470# CONFIG_MTD_UBI is not set
449CONFIG_OF_DEVICE=y 471CONFIG_OF_DEVICE=y
472CONFIG_OF_GPIO=y
450# CONFIG_PARPORT is not set 473# CONFIG_PARPORT is not set
451CONFIG_BLK_DEV=y 474CONFIG_BLK_DEV=y
452# CONFIG_BLK_DEV_FD is not set 475# CONFIG_BLK_DEV_FD is not set
476# CONFIG_MAC_FLOPPY is not set
453# CONFIG_BLK_CPQ_DA is not set 477# CONFIG_BLK_CPQ_DA is not set
454# CONFIG_BLK_CPQ_CISS_DA is not set 478# CONFIG_BLK_CPQ_CISS_DA is not set
455# CONFIG_BLK_DEV_DAC960 is not set 479# CONFIG_BLK_DEV_DAC960 is not set
@@ -461,14 +485,15 @@ CONFIG_BLK_DEV_LOOP=y
461# CONFIG_BLK_DEV_RAM is not set 485# CONFIG_BLK_DEV_RAM is not set
462# CONFIG_CDROM_PKTCDVD is not set 486# CONFIG_CDROM_PKTCDVD is not set
463# CONFIG_ATA_OVER_ETH is not set 487# CONFIG_ATA_OVER_ETH is not set
488# CONFIG_BLK_DEV_HD is not set
464CONFIG_MISC_DEVICES=y 489CONFIG_MISC_DEVICES=y
465# CONFIG_PHANTOM is not set 490# CONFIG_PHANTOM is not set
466# CONFIG_EEPROM_93CX6 is not set 491# CONFIG_EEPROM_93CX6 is not set
467# CONFIG_SGI_IOC4 is not set 492# CONFIG_SGI_IOC4 is not set
468# CONFIG_ENCLOSURE_SERVICES is not set 493# CONFIG_ENCLOSURE_SERVICES is not set
494# CONFIG_HP_ILO is not set
469CONFIG_HAVE_IDE=y 495CONFIG_HAVE_IDE=y
470CONFIG_IDE=y 496CONFIG_IDE=y
471CONFIG_IDE_MAX_HWIFS=4
472CONFIG_BLK_DEV_IDE=y 497CONFIG_BLK_DEV_IDE=y
473 498
474# 499#
@@ -486,7 +511,6 @@ CONFIG_IDE_PROC_FS=y
486# 511#
487# IDE chipset support/bugfixes 512# IDE chipset support/bugfixes
488# 513#
489# CONFIG_IDE_GENERIC is not set
490# CONFIG_BLK_DEV_PLATFORM is not set 514# CONFIG_BLK_DEV_PLATFORM is not set
491 515
492# 516#
@@ -498,9 +522,7 @@ CONFIG_IDE_PROC_FS=y
498# CONFIG_BLK_DEV_AMD74XX is not set 522# CONFIG_BLK_DEV_AMD74XX is not set
499# CONFIG_BLK_DEV_CMD64X is not set 523# CONFIG_BLK_DEV_CMD64X is not set
500# CONFIG_BLK_DEV_TRIFLEX is not set 524# CONFIG_BLK_DEV_TRIFLEX is not set
501# CONFIG_BLK_DEV_CY82C693 is not set
502# CONFIG_BLK_DEV_CS5530 is not set 525# CONFIG_BLK_DEV_CS5530 is not set
503# CONFIG_BLK_DEV_HPT34X is not set
504# CONFIG_BLK_DEV_HPT366 is not set 526# CONFIG_BLK_DEV_HPT366 is not set
505# CONFIG_BLK_DEV_JMICRON is not set 527# CONFIG_BLK_DEV_JMICRON is not set
506# CONFIG_BLK_DEV_SC1200 is not set 528# CONFIG_BLK_DEV_SC1200 is not set
@@ -517,9 +539,8 @@ CONFIG_IDE_PROC_FS=y
517# CONFIG_BLK_DEV_TRM290 is not set 539# CONFIG_BLK_DEV_TRM290 is not set
518# CONFIG_BLK_DEV_VIA82CXXX is not set 540# CONFIG_BLK_DEV_VIA82CXXX is not set
519# CONFIG_BLK_DEV_TC86C001 is not set 541# CONFIG_BLK_DEV_TC86C001 is not set
542# CONFIG_BLK_DEV_IDE_PMAC is not set
520# CONFIG_BLK_DEV_IDEDMA is not set 543# CONFIG_BLK_DEV_IDEDMA is not set
521# CONFIG_BLK_DEV_HD_ONLY is not set
522# CONFIG_BLK_DEV_HD is not set
523 544
524# 545#
525# SCSI device support 546# SCSI device support
@@ -537,13 +558,12 @@ CONFIG_IDE_PROC_FS=y
537# 558#
538 559
539# 560#
540# An alternative FireWire stack is available with EXPERIMENTAL=y 561# A new alternative FireWire stack is available with EXPERIMENTAL=y
541# 562#
542# CONFIG_IEEE1394 is not set 563# CONFIG_IEEE1394 is not set
543# CONFIG_I2O is not set 564# CONFIG_I2O is not set
544# CONFIG_MACINTOSH_DRIVERS is not set 565# CONFIG_MACINTOSH_DRIVERS is not set
545CONFIG_NETDEVICES=y 566CONFIG_NETDEVICES=y
546# CONFIG_NETDEVICES_MULTIQUEUE is not set
547# CONFIG_DUMMY is not set 567# CONFIG_DUMMY is not set
548# CONFIG_BONDING is not set 568# CONFIG_BONDING is not set
549# CONFIG_EQUALIZER is not set 569# CONFIG_EQUALIZER is not set
@@ -567,8 +587,11 @@ CONFIG_DAVICOM_PHY=y
567# CONFIG_REALTEK_PHY is not set 587# CONFIG_REALTEK_PHY is not set
568# CONFIG_FIXED_PHY is not set 588# CONFIG_FIXED_PHY is not set
569CONFIG_MDIO_BITBANG=y 589CONFIG_MDIO_BITBANG=y
590# CONFIG_MDIO_OF_GPIO is not set
570CONFIG_NET_ETHERNET=y 591CONFIG_NET_ETHERNET=y
571CONFIG_MII=y 592CONFIG_MII=y
593# CONFIG_MACE is not set
594# CONFIG_BMAC is not set
572# CONFIG_HAPPYMEAL is not set 595# CONFIG_HAPPYMEAL is not set
573# CONFIG_SUNGEM is not set 596# CONFIG_SUNGEM is not set
574# CONFIG_CASSINI is not set 597# CONFIG_CASSINI is not set
@@ -590,7 +613,6 @@ CONFIG_NETDEV_1000=y
590# CONFIG_DL2K is not set 613# CONFIG_DL2K is not set
591# CONFIG_E1000 is not set 614# CONFIG_E1000 is not set
592# CONFIG_E1000E is not set 615# CONFIG_E1000E is not set
593# CONFIG_E1000E_ENABLED is not set
594# CONFIG_IGB is not set 616# CONFIG_IGB is not set
595# CONFIG_NS83820 is not set 617# CONFIG_NS83820 is not set
596# CONFIG_HAMACHI is not set 618# CONFIG_HAMACHI is not set
@@ -602,6 +624,7 @@ CONFIG_NETDEV_1000=y
602# CONFIG_TIGON3 is not set 624# CONFIG_TIGON3 is not set
603# CONFIG_BNX2 is not set 625# CONFIG_BNX2 is not set
604# CONFIG_GIANFAR is not set 626# CONFIG_GIANFAR is not set
627# CONFIG_MV643XX_ETH is not set
605# CONFIG_QLA3XXX is not set 628# CONFIG_QLA3XXX is not set
606CONFIG_NETDEV_10000=y 629CONFIG_NETDEV_10000=y
607# CONFIG_CHELSIO_T1 is not set 630# CONFIG_CHELSIO_T1 is not set
@@ -667,6 +690,7 @@ CONFIG_KEYBOARD_ATKBD=y
667# CONFIG_KEYBOARD_XTKBD is not set 690# CONFIG_KEYBOARD_XTKBD is not set
668# CONFIG_KEYBOARD_NEWTON is not set 691# CONFIG_KEYBOARD_NEWTON is not set
669# CONFIG_KEYBOARD_STOWAWAY is not set 692# CONFIG_KEYBOARD_STOWAWAY is not set
693# CONFIG_KEYBOARD_GPIO is not set
670CONFIG_INPUT_MOUSE=y 694CONFIG_INPUT_MOUSE=y
671CONFIG_MOUSE_PS2=y 695CONFIG_MOUSE_PS2=y
672CONFIG_MOUSE_PS2_ALPS=y 696CONFIG_MOUSE_PS2_ALPS=y
@@ -677,7 +701,9 @@ CONFIG_MOUSE_PS2_TRACKPOINT=y
677# CONFIG_MOUSE_PS2_TOUCHKIT is not set 701# CONFIG_MOUSE_PS2_TOUCHKIT is not set
678# CONFIG_MOUSE_SERIAL is not set 702# CONFIG_MOUSE_SERIAL is not set
679# CONFIG_MOUSE_APPLETOUCH is not set 703# CONFIG_MOUSE_APPLETOUCH is not set
704# CONFIG_MOUSE_BCM5974 is not set
680# CONFIG_MOUSE_VSXXXAA is not set 705# CONFIG_MOUSE_VSXXXAA is not set
706# CONFIG_MOUSE_GPIO is not set
681# CONFIG_INPUT_JOYSTICK is not set 707# CONFIG_INPUT_JOYSTICK is not set
682# CONFIG_INPUT_TABLET is not set 708# CONFIG_INPUT_TABLET is not set
683# CONFIG_INPUT_TOUCHSCREEN is not set 709# CONFIG_INPUT_TOUCHSCREEN is not set
@@ -692,6 +718,7 @@ CONFIG_SERIO_SERPORT=y
692# CONFIG_SERIO_PCIPS2 is not set 718# CONFIG_SERIO_PCIPS2 is not set
693CONFIG_SERIO_LIBPS2=y 719CONFIG_SERIO_LIBPS2=y
694# CONFIG_SERIO_RAW is not set 720# CONFIG_SERIO_RAW is not set
721# CONFIG_SERIO_XILINX_XPS_PS2 is not set
695# CONFIG_GAMEPORT is not set 722# CONFIG_GAMEPORT is not set
696 723
697# 724#
@@ -712,6 +739,7 @@ CONFIG_DEVKMEM=y
712# CONFIG_SERIAL_UARTLITE is not set 739# CONFIG_SERIAL_UARTLITE is not set
713CONFIG_SERIAL_CORE=y 740CONFIG_SERIAL_CORE=y
714CONFIG_SERIAL_CORE_CONSOLE=y 741CONFIG_SERIAL_CORE_CONSOLE=y
742# CONFIG_SERIAL_PMACZILOG is not set
715CONFIG_SERIAL_CPM=y 743CONFIG_SERIAL_CPM=y
716CONFIG_SERIAL_CPM_CONSOLE=y 744CONFIG_SERIAL_CPM_CONSOLE=y
717CONFIG_SERIAL_CPM_SCC1=y 745CONFIG_SERIAL_CPM_SCC1=y
@@ -724,6 +752,8 @@ CONFIG_SERIAL_CPM_SCC4=y
724CONFIG_UNIX98_PTYS=y 752CONFIG_UNIX98_PTYS=y
725CONFIG_LEGACY_PTYS=y 753CONFIG_LEGACY_PTYS=y
726CONFIG_LEGACY_PTY_COUNT=256 754CONFIG_LEGACY_PTY_COUNT=256
755# CONFIG_BRIQ_PANEL is not set
756# CONFIG_HVC_RTAS is not set
727# CONFIG_IPMI_HANDLER is not set 757# CONFIG_IPMI_HANDLER is not set
728CONFIG_HW_RANDOM=y 758CONFIG_HW_RANDOM=y
729# CONFIG_NVRAM is not set 759# CONFIG_NVRAM is not set
@@ -734,10 +764,28 @@ CONFIG_HW_RANDOM=y
734CONFIG_DEVPORT=y 764CONFIG_DEVPORT=y
735# CONFIG_I2C is not set 765# CONFIG_I2C is not set
736# CONFIG_SPI is not set 766# CONFIG_SPI is not set
767CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
768CONFIG_ARCH_REQUIRE_GPIOLIB=y
769CONFIG_GPIOLIB=y
770# CONFIG_DEBUG_GPIO is not set
771
772#
773# I2C GPIO expanders:
774#
775
776#
777# PCI GPIO expanders:
778#
779# CONFIG_GPIO_BT8XX is not set
780
781#
782# SPI GPIO expanders:
783#
737# CONFIG_W1 is not set 784# CONFIG_W1 is not set
738# CONFIG_POWER_SUPPLY is not set 785# CONFIG_POWER_SUPPLY is not set
739# CONFIG_HWMON is not set 786# CONFIG_HWMON is not set
740# CONFIG_THERMAL is not set 787# CONFIG_THERMAL is not set
788# CONFIG_THERMAL_HWMON is not set
741# CONFIG_WATCHDOG is not set 789# CONFIG_WATCHDOG is not set
742 790
743# 791#
@@ -749,8 +797,10 @@ CONFIG_SSB_POSSIBLE=y
749# 797#
750# Multifunction device drivers 798# Multifunction device drivers
751# 799#
800# CONFIG_MFD_CORE is not set
752# CONFIG_MFD_SM501 is not set 801# CONFIG_MFD_SM501 is not set
753# CONFIG_HTC_PASIC3 is not set 802# CONFIG_HTC_PASIC3 is not set
803# CONFIG_MFD_TMIO is not set
754 804
755# 805#
756# Multimedia devices 806# Multimedia devices
@@ -782,10 +832,6 @@ CONFIG_VIDEO_OUTPUT_CONTROL=y
782# Display device support 832# Display device support
783# 833#
784# CONFIG_DISPLAY_SUPPORT is not set 834# CONFIG_DISPLAY_SUPPORT is not set
785
786#
787# Sound
788#
789# CONFIG_SOUND is not set 835# CONFIG_SOUND is not set
790# CONFIG_HID_SUPPORT is not set 836# CONFIG_HID_SUPPORT is not set
791CONFIG_USB_SUPPORT=y 837CONFIG_USB_SUPPORT=y
@@ -795,6 +841,8 @@ CONFIG_USB_ARCH_HAS_EHCI=y
795# CONFIG_USB is not set 841# CONFIG_USB is not set
796# CONFIG_USB_OTG_WHITELIST is not set 842# CONFIG_USB_OTG_WHITELIST is not set
797# CONFIG_USB_OTG_BLACKLIST_HUB is not set 843# CONFIG_USB_OTG_BLACKLIST_HUB is not set
844# CONFIG_USB_MUSB_HDRC is not set
845# CONFIG_USB_GADGET_MUSB_HDRC is not set
798 846
799# 847#
800# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 848# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
@@ -807,7 +855,7 @@ CONFIG_USB_GADGET_SELECTED=y
807# CONFIG_USB_GADGET_ATMEL_USBA is not set 855# CONFIG_USB_GADGET_ATMEL_USBA is not set
808# CONFIG_USB_GADGET_FSL_USB2 is not set 856# CONFIG_USB_GADGET_FSL_USB2 is not set
809# CONFIG_USB_GADGET_NET2280 is not set 857# CONFIG_USB_GADGET_NET2280 is not set
810# CONFIG_USB_GADGET_PXA2XX is not set 858# CONFIG_USB_GADGET_PXA25X is not set
811CONFIG_USB_GADGET_M66592=y 859CONFIG_USB_GADGET_M66592=y
812CONFIG_USB_M66592=y 860CONFIG_USB_M66592=y
813# CONFIG_USB_GADGET_PXA27X is not set 861# CONFIG_USB_GADGET_PXA27X is not set
@@ -826,6 +874,7 @@ CONFIG_USB_ETH_RNDIS=y
826# CONFIG_USB_G_SERIAL is not set 874# CONFIG_USB_G_SERIAL is not set
827# CONFIG_USB_MIDI_GADGET is not set 875# CONFIG_USB_MIDI_GADGET is not set
828# CONFIG_USB_G_PRINTER is not set 876# CONFIG_USB_G_PRINTER is not set
877# CONFIG_USB_CDC_COMPOSITE is not set
829# CONFIG_MMC is not set 878# CONFIG_MMC is not set
830# CONFIG_MEMSTICK is not set 879# CONFIG_MEMSTICK is not set
831# CONFIG_NEW_LEDS is not set 880# CONFIG_NEW_LEDS is not set
@@ -893,6 +942,7 @@ CONFIG_TMPFS=y
893CONFIG_CRAMFS=y 942CONFIG_CRAMFS=y
894# CONFIG_VXFS_FS is not set 943# CONFIG_VXFS_FS is not set
895# CONFIG_MINIX_FS is not set 944# CONFIG_MINIX_FS is not set
945# CONFIG_OMFS_FS is not set
896# CONFIG_HPFS_FS is not set 946# CONFIG_HPFS_FS is not set
897# CONFIG_QNX4FS_FS is not set 947# CONFIG_QNX4FS_FS is not set
898# CONFIG_ROMFS_FS is not set 948# CONFIG_ROMFS_FS is not set
@@ -902,8 +952,8 @@ CONFIG_NETWORK_FILESYSTEMS=y
902CONFIG_NFS_FS=y 952CONFIG_NFS_FS=y
903CONFIG_NFS_V3=y 953CONFIG_NFS_V3=y
904CONFIG_NFS_V3_ACL=y 954CONFIG_NFS_V3_ACL=y
905# CONFIG_NFSD is not set
906CONFIG_ROOT_NFS=y 955CONFIG_ROOT_NFS=y
956# CONFIG_NFSD is not set
907CONFIG_LOCKD=y 957CONFIG_LOCKD=y
908CONFIG_LOCKD_V4=y 958CONFIG_LOCKD_V4=y
909CONFIG_NFS_ACL_SUPPORT=y 959CONFIG_NFS_ACL_SUPPORT=y
@@ -983,6 +1033,7 @@ CONFIG_BITREVERSE=y
983# CONFIG_GENERIC_FIND_FIRST_BIT is not set 1033# CONFIG_GENERIC_FIND_FIRST_BIT is not set
984CONFIG_CRC_CCITT=y 1034CONFIG_CRC_CCITT=y
985# CONFIG_CRC16 is not set 1035# CONFIG_CRC16 is not set
1036# CONFIG_CRC_T10DIF is not set
986# CONFIG_CRC_ITU_T is not set 1037# CONFIG_CRC_ITU_T is not set
987CONFIG_CRC32=y 1038CONFIG_CRC32=y
988# CONFIG_CRC7 is not set 1039# CONFIG_CRC7 is not set
@@ -1009,6 +1060,8 @@ CONFIG_MAGIC_SYSRQ=y
1009CONFIG_DEBUG_KERNEL=y 1060CONFIG_DEBUG_KERNEL=y
1010# CONFIG_DEBUG_SHIRQ is not set 1061# CONFIG_DEBUG_SHIRQ is not set
1011CONFIG_DETECT_SOFTLOCKUP=y 1062CONFIG_DETECT_SOFTLOCKUP=y
1063# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
1064CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
1012# CONFIG_SCHED_DEBUG is not set 1065# CONFIG_SCHED_DEBUG is not set
1013# CONFIG_SCHEDSTATS is not set 1066# CONFIG_SCHEDSTATS is not set
1014# CONFIG_TIMER_STATS is not set 1067# CONFIG_TIMER_STATS is not set
@@ -1026,19 +1079,31 @@ CONFIG_DEBUG_BUGVERBOSE=y
1026CONFIG_DEBUG_INFO=y 1079CONFIG_DEBUG_INFO=y
1027# CONFIG_DEBUG_VM is not set 1080# CONFIG_DEBUG_VM is not set
1028# CONFIG_DEBUG_WRITECOUNT is not set 1081# CONFIG_DEBUG_WRITECOUNT is not set
1082# CONFIG_DEBUG_MEMORY_INIT is not set
1029# CONFIG_DEBUG_LIST is not set 1083# CONFIG_DEBUG_LIST is not set
1030# CONFIG_DEBUG_SG is not set 1084# CONFIG_DEBUG_SG is not set
1031# CONFIG_BOOT_PRINTK_DELAY is not set 1085# CONFIG_BOOT_PRINTK_DELAY is not set
1086# CONFIG_RCU_TORTURE_TEST is not set
1032# CONFIG_BACKTRACE_SELF_TEST is not set 1087# CONFIG_BACKTRACE_SELF_TEST is not set
1033# CONFIG_FAULT_INJECTION is not set 1088# CONFIG_FAULT_INJECTION is not set
1089# CONFIG_LATENCYTOP is not set
1090CONFIG_SYSCTL_SYSCALL_CHECK=y
1091CONFIG_HAVE_FTRACE=y
1092CONFIG_HAVE_DYNAMIC_FTRACE=y
1093# CONFIG_FTRACE is not set
1094# CONFIG_SCHED_TRACER is not set
1095# CONFIG_CONTEXT_SWITCH_TRACER is not set
1034# CONFIG_SAMPLES is not set 1096# CONFIG_SAMPLES is not set
1097CONFIG_HAVE_ARCH_KGDB=y
1035# CONFIG_DEBUG_STACKOVERFLOW is not set 1098# CONFIG_DEBUG_STACKOVERFLOW is not set
1036# CONFIG_DEBUG_STACK_USAGE is not set 1099# CONFIG_DEBUG_STACK_USAGE is not set
1037# CONFIG_DEBUG_PAGEALLOC is not set 1100# CONFIG_DEBUG_PAGEALLOC is not set
1038# CONFIG_DEBUGGER is not set 1101# CONFIG_CODE_PATCHING_SELFTEST is not set
1039# CONFIG_KGDB_CONSOLE is not set 1102# CONFIG_FTR_FIXUP_SELFTEST is not set
1103# CONFIG_XMON is not set
1040# CONFIG_IRQSTACKS is not set 1104# CONFIG_IRQSTACKS is not set
1041CONFIG_BDI_SWITCH=y 1105CONFIG_BDI_SWITCH=y
1106# CONFIG_BOOTX_TEXT is not set
1042# CONFIG_PPC_EARLY_DEBUG is not set 1107# CONFIG_PPC_EARLY_DEBUG is not set
1043 1108
1044# 1109#
@@ -1046,6 +1111,7 @@ CONFIG_BDI_SWITCH=y
1046# 1111#
1047# CONFIG_KEYS is not set 1112# CONFIG_KEYS is not set
1048# CONFIG_SECURITY is not set 1113# CONFIG_SECURITY is not set
1114# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1049CONFIG_CRYPTO=y 1115CONFIG_CRYPTO=y
1050 1116
1051# 1117#
@@ -1086,6 +1152,10 @@ CONFIG_CRYPTO_PCBC=y
1086# CONFIG_CRYPTO_MD4 is not set 1152# CONFIG_CRYPTO_MD4 is not set
1087CONFIG_CRYPTO_MD5=y 1153CONFIG_CRYPTO_MD5=y
1088# CONFIG_CRYPTO_MICHAEL_MIC is not set 1154# CONFIG_CRYPTO_MICHAEL_MIC is not set
1155# CONFIG_CRYPTO_RMD128 is not set
1156# CONFIG_CRYPTO_RMD160 is not set
1157# CONFIG_CRYPTO_RMD256 is not set
1158# CONFIG_CRYPTO_RMD320 is not set
1089# CONFIG_CRYPTO_SHA1 is not set 1159# CONFIG_CRYPTO_SHA1 is not set
1090# CONFIG_CRYPTO_SHA256 is not set 1160# CONFIG_CRYPTO_SHA256 is not set
1091# CONFIG_CRYPTO_SHA512 is not set 1161# CONFIG_CRYPTO_SHA512 is not set
@@ -1117,6 +1187,7 @@ CONFIG_CRYPTO_DES=y
1117# CONFIG_CRYPTO_LZO is not set 1187# CONFIG_CRYPTO_LZO is not set
1118CONFIG_CRYPTO_HW=y 1188CONFIG_CRYPTO_HW=y
1119# CONFIG_CRYPTO_DEV_HIFN_795X is not set 1189# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1120# CONFIG_PPC_CLOCK is not set 1190# CONFIG_CRYPTO_DEV_TALITOS is not set
1191CONFIG_PPC_CLOCK=y
1121CONFIG_PPC_LIB_RHEAP=y 1192CONFIG_PPC_LIB_RHEAP=y
1122# CONFIG_VIRTUALIZATION is not set 1193# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/configs/prpmc2800_defconfig b/arch/powerpc/configs/prpmc2800_defconfig
index c6b83577c055..01b54eac1ff6 100644
--- a/arch/powerpc/configs/prpmc2800_defconfig
+++ b/arch/powerpc/configs/prpmc2800_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc5 3# Linux kernel version: 2.6.27-rc4
4# Mon Jun 9 08:52:18 2008 4# Thu Aug 21 00:52:14 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -34,6 +34,7 @@ CONFIG_GENERIC_HARDIRQS=y
34# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set 34# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
35CONFIG_IRQ_PER_CPU=y 35CONFIG_IRQ_PER_CPU=y
36CONFIG_STACKTRACE_SUPPORT=y 36CONFIG_STACKTRACE_SUPPORT=y
37CONFIG_HAVE_LATENCYTOP_SUPPORT=y
37CONFIG_LOCKDEP_SUPPORT=y 38CONFIG_LOCKDEP_SUPPORT=y
38CONFIG_RWSEM_XCHGADD_ALGORITHM=y 39CONFIG_RWSEM_XCHGADD_ALGORITHM=y
39CONFIG_ARCH_HAS_ILOG2_U32=y 40CONFIG_ARCH_HAS_ILOG2_U32=y
@@ -94,7 +95,6 @@ CONFIG_INITRAMFS_SOURCE=""
94CONFIG_SYSCTL=y 95CONFIG_SYSCTL=y
95# CONFIG_EMBEDDED is not set 96# CONFIG_EMBEDDED is not set
96CONFIG_SYSCTL_SYSCALL=y 97CONFIG_SYSCTL_SYSCALL=y
97CONFIG_SYSCTL_SYSCALL_CHECK=y
98CONFIG_KALLSYMS=y 98CONFIG_KALLSYMS=y
99# CONFIG_KALLSYMS_EXTRA_PASS is not set 99# CONFIG_KALLSYMS_EXTRA_PASS is not set
100CONFIG_HOTPLUG=y 100CONFIG_HOTPLUG=y
@@ -118,10 +118,16 @@ CONFIG_SLUB=y
118# CONFIG_PROFILING is not set 118# CONFIG_PROFILING is not set
119# CONFIG_MARKERS is not set 119# CONFIG_MARKERS is not set
120CONFIG_HAVE_OPROFILE=y 120CONFIG_HAVE_OPROFILE=y
121CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
122CONFIG_HAVE_IOREMAP_PROT=y
121CONFIG_HAVE_KPROBES=y 123CONFIG_HAVE_KPROBES=y
122CONFIG_HAVE_KRETPROBES=y 124CONFIG_HAVE_KRETPROBES=y
125CONFIG_HAVE_ARCH_TRACEHOOK=y
123# CONFIG_HAVE_DMA_ATTRS is not set 126# CONFIG_HAVE_DMA_ATTRS is not set
127# CONFIG_USE_GENERIC_SMP_HELPERS is not set
128# CONFIG_HAVE_CLK is not set
124CONFIG_PROC_PAGE_MONITOR=y 129CONFIG_PROC_PAGE_MONITOR=y
130# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
125CONFIG_SLABINFO=y 131CONFIG_SLABINFO=y
126CONFIG_RT_MUTEXES=y 132CONFIG_RT_MUTEXES=y
127# CONFIG_TINY_SHMEM is not set 133# CONFIG_TINY_SHMEM is not set
@@ -132,6 +138,7 @@ CONFIG_LBD=y
132# CONFIG_BLK_DEV_IO_TRACE is not set 138# CONFIG_BLK_DEV_IO_TRACE is not set
133# CONFIG_LSF is not set 139# CONFIG_LSF is not set
134# CONFIG_BLK_DEV_BSG is not set 140# CONFIG_BLK_DEV_BSG is not set
141# CONFIG_BLK_DEV_INTEGRITY is not set
135 142
136# 143#
137# IO Schedulers 144# IO Schedulers
@@ -151,25 +158,25 @@ CONFIG_CLASSIC_RCU=y
151# Platform support 158# Platform support
152# 159#
153CONFIG_PPC_MULTIPLATFORM=y 160CONFIG_PPC_MULTIPLATFORM=y
154# CONFIG_PPC_82xx is not set
155# CONFIG_PPC_83xx is not set
156# CONFIG_PPC_86xx is not set
157CONFIG_CLASSIC32=y 161CONFIG_CLASSIC32=y
158# CONFIG_PPC_CHRP is not set 162# CONFIG_PPC_CHRP is not set
159# CONFIG_PPC_MPC512x is not set
160# CONFIG_PPC_MPC5121 is not set
161# CONFIG_MPC5121_ADS is not set 163# CONFIG_MPC5121_ADS is not set
164# CONFIG_MPC5121_GENERIC is not set
162# CONFIG_PPC_MPC52xx is not set 165# CONFIG_PPC_MPC52xx is not set
163# CONFIG_PPC_PMAC is not set 166# CONFIG_PPC_PMAC is not set
164# CONFIG_PPC_CELL is not set 167# CONFIG_PPC_CELL is not set
165# CONFIG_PPC_CELL_NATIVE is not set 168# CONFIG_PPC_CELL_NATIVE is not set
169# CONFIG_PPC_82xx is not set
166# CONFIG_PQ2ADS is not set 170# CONFIG_PQ2ADS is not set
171# CONFIG_PPC_83xx is not set
172# CONFIG_PPC_86xx is not set
167CONFIG_EMBEDDED6xx=y 173CONFIG_EMBEDDED6xx=y
168# CONFIG_LINKSTATION is not set 174# CONFIG_LINKSTATION is not set
169# CONFIG_STORCENTER is not set 175# CONFIG_STORCENTER is not set
170# CONFIG_MPC7448HPC2 is not set 176# CONFIG_MPC7448HPC2 is not set
171# CONFIG_PPC_HOLLY is not set 177# CONFIG_PPC_HOLLY is not set
172CONFIG_PPC_PRPMC2800=y 178CONFIG_PPC_PRPMC2800=y
179# CONFIG_PPC_C2K is not set
173CONFIG_MV64X60=y 180CONFIG_MV64X60=y
174# CONFIG_IPIC is not set 181# CONFIG_IPIC is not set
175# CONFIG_MPIC is not set 182# CONFIG_MPIC is not set
@@ -198,7 +205,7 @@ CONFIG_HZ_250=y
198# CONFIG_HZ_300 is not set 205# CONFIG_HZ_300 is not set
199# CONFIG_HZ_1000 is not set 206# CONFIG_HZ_1000 is not set
200CONFIG_HZ=250 207CONFIG_HZ=250
201# CONFIG_SCHED_HRTICK is not set 208CONFIG_SCHED_HRTICK=y
202CONFIG_PREEMPT_NONE=y 209CONFIG_PREEMPT_NONE=y
203# CONFIG_PREEMPT_VOLUNTARY is not set 210# CONFIG_PREEMPT_VOLUNTARY is not set
204# CONFIG_PREEMPT is not set 211# CONFIG_PREEMPT is not set
@@ -221,6 +228,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
221# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set 228# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
222CONFIG_PAGEFLAGS_EXTENDED=y 229CONFIG_PAGEFLAGS_EXTENDED=y
223CONFIG_SPLIT_PTLOCK_CPUS=4 230CONFIG_SPLIT_PTLOCK_CPUS=4
231CONFIG_MIGRATION=y
224# CONFIG_RESOURCES_64BIT is not set 232# CONFIG_RESOURCES_64BIT is not set
225CONFIG_ZONE_DMA_FLAG=1 233CONFIG_ZONE_DMA_FLAG=1
226CONFIG_BOUNCE=y 234CONFIG_BOUNCE=y
@@ -228,6 +236,7 @@ CONFIG_VIRT_TO_BUS=y
228CONFIG_FORCE_MAX_ZONEORDER=11 236CONFIG_FORCE_MAX_ZONEORDER=11
229CONFIG_PROC_DEVICETREE=y 237CONFIG_PROC_DEVICETREE=y
230# CONFIG_CMDLINE_BOOL is not set 238# CONFIG_CMDLINE_BOOL is not set
239CONFIG_EXTRA_TARGETS=""
231# CONFIG_PM is not set 240# CONFIG_PM is not set
232# CONFIG_SECCOMP is not set 241# CONFIG_SECCOMP is not set
233CONFIG_ISA_DMA_API=y 242CONFIG_ISA_DMA_API=y
@@ -264,10 +273,6 @@ CONFIG_PHYSICAL_START=0x00000000
264CONFIG_TASK_SIZE=0xc0000000 273CONFIG_TASK_SIZE=0xc0000000
265CONFIG_CONSISTENT_START=0xff100000 274CONFIG_CONSISTENT_START=0xff100000
266CONFIG_CONSISTENT_SIZE=0x00200000 275CONFIG_CONSISTENT_SIZE=0x00200000
267
268#
269# Networking
270#
271CONFIG_NET=y 276CONFIG_NET=y
272 277
273# 278#
@@ -359,7 +364,9 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
359CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 364CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
360CONFIG_STANDALONE=y 365CONFIG_STANDALONE=y
361CONFIG_PREVENT_FIRMWARE_BUILD=y 366CONFIG_PREVENT_FIRMWARE_BUILD=y
362# CONFIG_FW_LOADER is not set 367CONFIG_FW_LOADER=y
368CONFIG_FIRMWARE_IN_KERNEL=y
369CONFIG_EXTRA_FIRMWARE=""
363# CONFIG_SYS_HYPERVISOR is not set 370# CONFIG_SYS_HYPERVISOR is not set
364# CONFIG_CONNECTOR is not set 371# CONFIG_CONNECTOR is not set
365CONFIG_MTD=y 372CONFIG_MTD=y
@@ -461,12 +468,14 @@ CONFIG_BLK_DEV_RAM_SIZE=131072
461# CONFIG_BLK_DEV_XIP is not set 468# CONFIG_BLK_DEV_XIP is not set
462# CONFIG_CDROM_PKTCDVD is not set 469# CONFIG_CDROM_PKTCDVD is not set
463# CONFIG_ATA_OVER_ETH is not set 470# CONFIG_ATA_OVER_ETH is not set
471# CONFIG_BLK_DEV_HD is not set
464CONFIG_MISC_DEVICES=y 472CONFIG_MISC_DEVICES=y
465# CONFIG_PHANTOM is not set 473# CONFIG_PHANTOM is not set
466# CONFIG_EEPROM_93CX6 is not set 474# CONFIG_EEPROM_93CX6 is not set
467# CONFIG_SGI_IOC4 is not set 475# CONFIG_SGI_IOC4 is not set
468# CONFIG_TIFM_CORE is not set 476# CONFIG_TIFM_CORE is not set
469# CONFIG_ENCLOSURE_SERVICES is not set 477# CONFIG_ENCLOSURE_SERVICES is not set
478# CONFIG_HP_ILO is not set
470CONFIG_HAVE_IDE=y 479CONFIG_HAVE_IDE=y
471CONFIG_IDE=y 480CONFIG_IDE=y
472CONFIG_BLK_DEV_IDE=y 481CONFIG_BLK_DEV_IDE=y
@@ -487,7 +496,6 @@ CONFIG_IDE_PROC_FS=y
487# 496#
488# IDE chipset support/bugfixes 497# IDE chipset support/bugfixes
489# 498#
490CONFIG_IDE_GENERIC=y
491# CONFIG_BLK_DEV_PLATFORM is not set 499# CONFIG_BLK_DEV_PLATFORM is not set
492CONFIG_BLK_DEV_IDEDMA_SFF=y 500CONFIG_BLK_DEV_IDEDMA_SFF=y
493 501
@@ -505,10 +513,8 @@ CONFIG_BLK_DEV_IDEDMA_PCI=y
505# CONFIG_BLK_DEV_AMD74XX is not set 513# CONFIG_BLK_DEV_AMD74XX is not set
506# CONFIG_BLK_DEV_CMD64X is not set 514# CONFIG_BLK_DEV_CMD64X is not set
507# CONFIG_BLK_DEV_TRIFLEX is not set 515# CONFIG_BLK_DEV_TRIFLEX is not set
508# CONFIG_BLK_DEV_CY82C693 is not set
509# CONFIG_BLK_DEV_CS5520 is not set 516# CONFIG_BLK_DEV_CS5520 is not set
510# CONFIG_BLK_DEV_CS5530 is not set 517# CONFIG_BLK_DEV_CS5530 is not set
511# CONFIG_BLK_DEV_HPT34X is not set
512# CONFIG_BLK_DEV_HPT366 is not set 518# CONFIG_BLK_DEV_HPT366 is not set
513# CONFIG_BLK_DEV_JMICRON is not set 519# CONFIG_BLK_DEV_JMICRON is not set
514# CONFIG_BLK_DEV_SC1200 is not set 520# CONFIG_BLK_DEV_SC1200 is not set
@@ -526,8 +532,6 @@ CONFIG_BLK_DEV_PDC202XX_NEW=y
526# CONFIG_BLK_DEV_VIA82CXXX is not set 532# CONFIG_BLK_DEV_VIA82CXXX is not set
527# CONFIG_BLK_DEV_TC86C001 is not set 533# CONFIG_BLK_DEV_TC86C001 is not set
528CONFIG_BLK_DEV_IDEDMA=y 534CONFIG_BLK_DEV_IDEDMA=y
529# CONFIG_BLK_DEV_HD_ONLY is not set
530# CONFIG_BLK_DEV_HD is not set
531 535
532# 536#
533# SCSI device support 537# SCSI device support
@@ -603,6 +607,7 @@ CONFIG_SCSI_LOWLEVEL=y
603# CONFIG_SCSI_NSP32 is not set 607# CONFIG_SCSI_NSP32 is not set
604# CONFIG_SCSI_DEBUG is not set 608# CONFIG_SCSI_DEBUG is not set
605# CONFIG_SCSI_SRP is not set 609# CONFIG_SCSI_SRP is not set
610# CONFIG_SCSI_DH is not set
606CONFIG_ATA=y 611CONFIG_ATA=y
607# CONFIG_ATA_NONSTANDARD is not set 612# CONFIG_ATA_NONSTANDARD is not set
608CONFIG_SATA_PMP=y 613CONFIG_SATA_PMP=y
@@ -669,6 +674,10 @@ CONFIG_SATA_MV=y
669# 674#
670# IEEE 1394 (FireWire) support 675# IEEE 1394 (FireWire) support
671# 676#
677
678#
679# Enable only one of the two stacks, unless you know what you are doing
680#
672# CONFIG_FIREWIRE is not set 681# CONFIG_FIREWIRE is not set
673# CONFIG_IEEE1394 is not set 682# CONFIG_IEEE1394 is not set
674# CONFIG_I2O is not set 683# CONFIG_I2O is not set
@@ -676,7 +685,6 @@ CONFIG_MACINTOSH_DRIVERS=y
676# CONFIG_MAC_EMUMOUSEBTN is not set 685# CONFIG_MAC_EMUMOUSEBTN is not set
677# CONFIG_WINDFARM is not set 686# CONFIG_WINDFARM is not set
678CONFIG_NETDEVICES=y 687CONFIG_NETDEVICES=y
679# CONFIG_NETDEVICES_MULTIQUEUE is not set
680# CONFIG_DUMMY is not set 688# CONFIG_DUMMY is not set
681# CONFIG_BONDING is not set 689# CONFIG_BONDING is not set
682# CONFIG_MACVLAN is not set 690# CONFIG_MACVLAN is not set
@@ -741,10 +749,8 @@ CONFIG_NETDEV_1000=y
741# CONFIG_ACENIC is not set 749# CONFIG_ACENIC is not set
742# CONFIG_DL2K is not set 750# CONFIG_DL2K is not set
743CONFIG_E1000=y 751CONFIG_E1000=y
744# CONFIG_E1000_NAPI is not set
745# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set 752# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
746# CONFIG_E1000E is not set 753# CONFIG_E1000E is not set
747# CONFIG_E1000E_ENABLED is not set
748# CONFIG_IP1000 is not set 754# CONFIG_IP1000 is not set
749# CONFIG_IGB is not set 755# CONFIG_IGB is not set
750# CONFIG_NS83820 is not set 756# CONFIG_NS83820 is not set
@@ -760,6 +766,7 @@ CONFIG_E1000=y
760CONFIG_MV643XX_ETH=y 766CONFIG_MV643XX_ETH=y
761# CONFIG_QLA3XXX is not set 767# CONFIG_QLA3XXX is not set
762# CONFIG_ATL1 is not set 768# CONFIG_ATL1 is not set
769# CONFIG_ATL1E is not set
763CONFIG_NETDEV_10000=y 770CONFIG_NETDEV_10000=y
764# CONFIG_CHELSIO_T1 is not set 771# CONFIG_CHELSIO_T1 is not set
765# CONFIG_CHELSIO_T3 is not set 772# CONFIG_CHELSIO_T3 is not set
@@ -840,6 +847,7 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
840# Character devices 847# Character devices
841# 848#
842CONFIG_VT=y 849CONFIG_VT=y
850CONFIG_CONSOLE_TRANSLATIONS=y
843CONFIG_VT_CONSOLE=y 851CONFIG_VT_CONSOLE=y
844CONFIG_HW_CONSOLE=y 852CONFIG_HW_CONSOLE=y
845# CONFIG_VT_HW_CONSOLE_BINDING is not set 853# CONFIG_VT_HW_CONSOLE_BINDING is not set
@@ -875,43 +883,64 @@ CONFIG_DEVPORT=y
875CONFIG_I2C=y 883CONFIG_I2C=y
876CONFIG_I2C_BOARDINFO=y 884CONFIG_I2C_BOARDINFO=y
877CONFIG_I2C_CHARDEV=y 885CONFIG_I2C_CHARDEV=y
886CONFIG_I2C_HELPER_AUTO=y
878 887
879# 888#
880# I2C Hardware Bus support 889# I2C Hardware Bus support
881# 890#
891
892#
893# PC SMBus host controller drivers
894#
882# CONFIG_I2C_ALI1535 is not set 895# CONFIG_I2C_ALI1535 is not set
883# CONFIG_I2C_ALI1563 is not set 896# CONFIG_I2C_ALI1563 is not set
884# CONFIG_I2C_ALI15X3 is not set 897# CONFIG_I2C_ALI15X3 is not set
885# CONFIG_I2C_AMD756 is not set 898# CONFIG_I2C_AMD756 is not set
886# CONFIG_I2C_AMD8111 is not set 899# CONFIG_I2C_AMD8111 is not set
887# CONFIG_I2C_I801 is not set 900# CONFIG_I2C_I801 is not set
888# CONFIG_I2C_I810 is not set 901# CONFIG_I2C_ISCH is not set
889# CONFIG_I2C_PIIX4 is not set 902# CONFIG_I2C_PIIX4 is not set
890# CONFIG_I2C_MPC is not set
891# CONFIG_I2C_NFORCE2 is not set 903# CONFIG_I2C_NFORCE2 is not set
892# CONFIG_I2C_OCORES is not set
893# CONFIG_I2C_PARPORT_LIGHT is not set
894# CONFIG_I2C_PROSAVAGE is not set
895# CONFIG_I2C_SAVAGE4 is not set
896# CONFIG_I2C_SIMTEC is not set
897# CONFIG_I2C_SIS5595 is not set 904# CONFIG_I2C_SIS5595 is not set
898# CONFIG_I2C_SIS630 is not set 905# CONFIG_I2C_SIS630 is not set
899# CONFIG_I2C_SIS96X is not set 906# CONFIG_I2C_SIS96X is not set
900# CONFIG_I2C_TAOS_EVM is not set
901# CONFIG_I2C_TINY_USB is not set
902# CONFIG_I2C_VIA is not set 907# CONFIG_I2C_VIA is not set
903# CONFIG_I2C_VIAPRO is not set 908# CONFIG_I2C_VIAPRO is not set
909
910#
911# I2C system bus drivers (mostly embedded / system-on-chip)
912#
913# CONFIG_I2C_MPC is not set
914CONFIG_I2C_MV64XXX=y
915# CONFIG_I2C_OCORES is not set
916# CONFIG_I2C_SIMTEC is not set
917
918#
919# External I2C/SMBus adapter drivers
920#
921# CONFIG_I2C_PARPORT_LIGHT is not set
922# CONFIG_I2C_TAOS_EVM is not set
923# CONFIG_I2C_TINY_USB is not set
924
925#
926# Graphics adapter I2C/DDC channel drivers
927#
904# CONFIG_I2C_VOODOO3 is not set 928# CONFIG_I2C_VOODOO3 is not set
929
930#
931# Other I2C/SMBus bus drivers
932#
905# CONFIG_I2C_PCA_PLATFORM is not set 933# CONFIG_I2C_PCA_PLATFORM is not set
906CONFIG_I2C_MV64XXX=y
907 934
908# 935#
909# Miscellaneous I2C Chip support 936# Miscellaneous I2C Chip support
910# 937#
911# CONFIG_DS1682 is not set 938# CONFIG_DS1682 is not set
939# CONFIG_AT24 is not set
912# CONFIG_SENSORS_EEPROM is not set 940# CONFIG_SENSORS_EEPROM is not set
913# CONFIG_SENSORS_PCF8574 is not set 941# CONFIG_SENSORS_PCF8574 is not set
914# CONFIG_PCF8575 is not set 942# CONFIG_PCF8575 is not set
943# CONFIG_SENSORS_PCA9539 is not set
915# CONFIG_SENSORS_PCF8591 is not set 944# CONFIG_SENSORS_PCF8591 is not set
916# CONFIG_SENSORS_MAX6875 is not set 945# CONFIG_SENSORS_MAX6875 is not set
917# CONFIG_SENSORS_TSL2550 is not set 946# CONFIG_SENSORS_TSL2550 is not set
@@ -920,10 +949,13 @@ CONFIG_I2C_MV64XXX=y
920# CONFIG_I2C_DEBUG_BUS is not set 949# CONFIG_I2C_DEBUG_BUS is not set
921# CONFIG_I2C_DEBUG_CHIP is not set 950# CONFIG_I2C_DEBUG_CHIP is not set
922# CONFIG_SPI is not set 951# CONFIG_SPI is not set
952CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
953# CONFIG_GPIOLIB is not set
923# CONFIG_W1 is not set 954# CONFIG_W1 is not set
924# CONFIG_POWER_SUPPLY is not set 955# CONFIG_POWER_SUPPLY is not set
925CONFIG_HWMON=y 956CONFIG_HWMON=y
926# CONFIG_HWMON_VID is not set 957# CONFIG_HWMON_VID is not set
958# CONFIG_SENSORS_AD7414 is not set
927# CONFIG_SENSORS_AD7418 is not set 959# CONFIG_SENSORS_AD7418 is not set
928# CONFIG_SENSORS_ADM1021 is not set 960# CONFIG_SENSORS_ADM1021 is not set
929# CONFIG_SENSORS_ADM1025 is not set 961# CONFIG_SENSORS_ADM1025 is not set
@@ -977,6 +1009,7 @@ CONFIG_HWMON=y
977# CONFIG_SENSORS_W83627EHF is not set 1009# CONFIG_SENSORS_W83627EHF is not set
978# CONFIG_HWMON_DEBUG_CHIP is not set 1010# CONFIG_HWMON_DEBUG_CHIP is not set
979# CONFIG_THERMAL is not set 1011# CONFIG_THERMAL is not set
1012# CONFIG_THERMAL_HWMON is not set
980# CONFIG_WATCHDOG is not set 1013# CONFIG_WATCHDOG is not set
981 1014
982# 1015#
@@ -988,8 +1021,10 @@ CONFIG_SSB_POSSIBLE=y
988# 1021#
989# Multifunction device drivers 1022# Multifunction device drivers
990# 1023#
1024# CONFIG_MFD_CORE is not set
991# CONFIG_MFD_SM501 is not set 1025# CONFIG_MFD_SM501 is not set
992# CONFIG_HTC_PASIC3 is not set 1026# CONFIG_HTC_PASIC3 is not set
1027# CONFIG_MFD_TMIO is not set
993 1028
994# 1029#
995# Multimedia devices 1030# Multimedia devices
@@ -1028,10 +1063,6 @@ CONFIG_VIDEO_OUTPUT_CONTROL=y
1028CONFIG_VGA_CONSOLE=y 1063CONFIG_VGA_CONSOLE=y
1029# CONFIG_VGACON_SOFT_SCROLLBACK is not set 1064# CONFIG_VGACON_SOFT_SCROLLBACK is not set
1030CONFIG_DUMMY_CONSOLE=y 1065CONFIG_DUMMY_CONSOLE=y
1031
1032#
1033# Sound
1034#
1035# CONFIG_SOUND is not set 1066# CONFIG_SOUND is not set
1036CONFIG_HID_SUPPORT=y 1067CONFIG_HID_SUPPORT=y
1037CONFIG_HID=y 1068CONFIG_HID=y
@@ -1060,6 +1091,7 @@ CONFIG_USB_DEVICEFS=y
1060# CONFIG_USB_DEVICE_CLASS is not set 1091# CONFIG_USB_DEVICE_CLASS is not set
1061# CONFIG_USB_DYNAMIC_MINORS is not set 1092# CONFIG_USB_DYNAMIC_MINORS is not set
1062# CONFIG_USB_OTG is not set 1093# CONFIG_USB_OTG is not set
1094CONFIG_USB_MON=y
1063 1095
1064# 1096#
1065# USB Host Controller Drivers 1097# USB Host Controller Drivers
@@ -1102,7 +1134,6 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y
1102# 1134#
1103# CONFIG_USB_MDC800 is not set 1135# CONFIG_USB_MDC800 is not set
1104# CONFIG_USB_MICROTEK is not set 1136# CONFIG_USB_MICROTEK is not set
1105CONFIG_USB_MON=y
1106 1137
1107# 1138#
1108# USB port drivers 1139# USB port drivers
@@ -1115,7 +1146,6 @@ CONFIG_USB_MON=y
1115# CONFIG_USB_EMI62 is not set 1146# CONFIG_USB_EMI62 is not set
1116# CONFIG_USB_EMI26 is not set 1147# CONFIG_USB_EMI26 is not set
1117# CONFIG_USB_ADUTUX is not set 1148# CONFIG_USB_ADUTUX is not set
1118# CONFIG_USB_AUERSWALD is not set
1119# CONFIG_USB_RIO500 is not set 1149# CONFIG_USB_RIO500 is not set
1120# CONFIG_USB_LEGOTOWER is not set 1150# CONFIG_USB_LEGOTOWER is not set
1121# CONFIG_USB_LCD is not set 1151# CONFIG_USB_LCD is not set
@@ -1169,6 +1199,7 @@ CONFIG_RTC_DRV_MAX6900=y
1169# CONFIG_RTC_DRV_PCF8583 is not set 1199# CONFIG_RTC_DRV_PCF8583 is not set
1170# CONFIG_RTC_DRV_M41T80 is not set 1200# CONFIG_RTC_DRV_M41T80 is not set
1171# CONFIG_RTC_DRV_S35390A is not set 1201# CONFIG_RTC_DRV_S35390A is not set
1202# CONFIG_RTC_DRV_FM3130 is not set
1172 1203
1173# 1204#
1174# SPI RTC drivers 1205# SPI RTC drivers
@@ -1258,6 +1289,7 @@ CONFIG_TMPFS=y
1258# CONFIG_CRAMFS is not set 1289# CONFIG_CRAMFS is not set
1259# CONFIG_VXFS_FS is not set 1290# CONFIG_VXFS_FS is not set
1260# CONFIG_MINIX_FS is not set 1291# CONFIG_MINIX_FS is not set
1292# CONFIG_OMFS_FS is not set
1261# CONFIG_HPFS_FS is not set 1293# CONFIG_HPFS_FS is not set
1262# CONFIG_QNX4FS_FS is not set 1294# CONFIG_QNX4FS_FS is not set
1263# CONFIG_ROMFS_FS is not set 1295# CONFIG_ROMFS_FS is not set
@@ -1267,12 +1299,11 @@ CONFIG_NETWORK_FILESYSTEMS=y
1267CONFIG_NFS_FS=y 1299CONFIG_NFS_FS=y
1268# CONFIG_NFS_V3 is not set 1300# CONFIG_NFS_V3 is not set
1269# CONFIG_NFS_V4 is not set 1301# CONFIG_NFS_V4 is not set
1270# CONFIG_NFSD is not set
1271CONFIG_ROOT_NFS=y 1302CONFIG_ROOT_NFS=y
1303# CONFIG_NFSD is not set
1272CONFIG_LOCKD=y 1304CONFIG_LOCKD=y
1273CONFIG_NFS_COMMON=y 1305CONFIG_NFS_COMMON=y
1274CONFIG_SUNRPC=y 1306CONFIG_SUNRPC=y
1275# CONFIG_SUNRPC_BIND34 is not set
1276# CONFIG_RPCSEC_GSS_KRB5 is not set 1307# CONFIG_RPCSEC_GSS_KRB5 is not set
1277# CONFIG_RPCSEC_GSS_SPKM3 is not set 1308# CONFIG_RPCSEC_GSS_SPKM3 is not set
1278# CONFIG_SMB_FS is not set 1309# CONFIG_SMB_FS is not set
@@ -1312,6 +1343,7 @@ CONFIG_BITREVERSE=y
1312# CONFIG_GENERIC_FIND_FIRST_BIT is not set 1343# CONFIG_GENERIC_FIND_FIRST_BIT is not set
1313# CONFIG_CRC_CCITT is not set 1344# CONFIG_CRC_CCITT is not set
1314# CONFIG_CRC16 is not set 1345# CONFIG_CRC16 is not set
1346CONFIG_CRC_T10DIF=y
1315# CONFIG_CRC_ITU_T is not set 1347# CONFIG_CRC_ITU_T is not set
1316CONFIG_CRC32=y 1348CONFIG_CRC32=y
1317# CONFIG_CRC7 is not set 1349# CONFIG_CRC7 is not set
@@ -1337,7 +1369,16 @@ CONFIG_FRAME_WARN=1024
1337# CONFIG_SLUB_DEBUG_ON is not set 1369# CONFIG_SLUB_DEBUG_ON is not set
1338# CONFIG_SLUB_STATS is not set 1370# CONFIG_SLUB_STATS is not set
1339CONFIG_DEBUG_BUGVERBOSE=y 1371CONFIG_DEBUG_BUGVERBOSE=y
1372CONFIG_DEBUG_MEMORY_INIT=y
1373# CONFIG_LATENCYTOP is not set
1374CONFIG_SYSCTL_SYSCALL_CHECK=y
1375CONFIG_HAVE_FTRACE=y
1376CONFIG_HAVE_DYNAMIC_FTRACE=y
1377# CONFIG_FTRACE is not set
1378# CONFIG_SCHED_TRACER is not set
1379# CONFIG_CONTEXT_SWITCH_TRACER is not set
1340# CONFIG_SAMPLES is not set 1380# CONFIG_SAMPLES is not set
1381CONFIG_HAVE_ARCH_KGDB=y
1341# CONFIG_IRQSTACKS is not set 1382# CONFIG_IRQSTACKS is not set
1342# CONFIG_BOOTX_TEXT is not set 1383# CONFIG_BOOTX_TEXT is not set
1343# CONFIG_PPC_EARLY_DEBUG is not set 1384# CONFIG_PPC_EARLY_DEBUG is not set
@@ -1390,6 +1431,10 @@ CONFIG_CRYPTO=y
1390# CONFIG_CRYPTO_MD4 is not set 1431# CONFIG_CRYPTO_MD4 is not set
1391# CONFIG_CRYPTO_MD5 is not set 1432# CONFIG_CRYPTO_MD5 is not set
1392# CONFIG_CRYPTO_MICHAEL_MIC is not set 1433# CONFIG_CRYPTO_MICHAEL_MIC is not set
1434# CONFIG_CRYPTO_RMD128 is not set
1435# CONFIG_CRYPTO_RMD160 is not set
1436# CONFIG_CRYPTO_RMD256 is not set
1437# CONFIG_CRYPTO_RMD320 is not set
1393# CONFIG_CRYPTO_SHA1 is not set 1438# CONFIG_CRYPTO_SHA1 is not set
1394# CONFIG_CRYPTO_SHA256 is not set 1439# CONFIG_CRYPTO_SHA256 is not set
1395# CONFIG_CRYPTO_SHA512 is not set 1440# CONFIG_CRYPTO_SHA512 is not set
diff --git a/arch/powerpc/configs/ps3_defconfig b/arch/powerpc/configs/ps3_defconfig
index f9a3d3b394cf..b6eee7c93cdd 100644
--- a/arch/powerpc/configs/ps3_defconfig
+++ b/arch/powerpc/configs/ps3_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26 3# Linux kernel version: 2.6.27-rc3
4# Wed Jul 16 13:59:24 2008 4# Wed Aug 20 08:16:53 2008
5# 5#
6CONFIG_PPC64=y 6CONFIG_PPC64=y
7 7
@@ -92,7 +92,6 @@ CONFIG_CC_OPTIMIZE_FOR_SIZE=y
92CONFIG_SYSCTL=y 92CONFIG_SYSCTL=y
93# CONFIG_EMBEDDED is not set 93# CONFIG_EMBEDDED is not set
94CONFIG_SYSCTL_SYSCALL=y 94CONFIG_SYSCTL_SYSCALL=y
95CONFIG_SYSCTL_SYSCALL_CHECK=y
96CONFIG_KALLSYMS=y 95CONFIG_KALLSYMS=y
97CONFIG_KALLSYMS_ALL=y 96CONFIG_KALLSYMS_ALL=y
98CONFIG_KALLSYMS_EXTRA_PASS=y 97CONFIG_KALLSYMS_EXTRA_PASS=y
@@ -118,11 +117,16 @@ CONFIG_PROFILING=y
118CONFIG_OPROFILE=m 117CONFIG_OPROFILE=m
119CONFIG_HAVE_OPROFILE=y 118CONFIG_HAVE_OPROFILE=y
120# CONFIG_KPROBES is not set 119# CONFIG_KPROBES is not set
120CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
121CONFIG_HAVE_IOREMAP_PROT=y
121CONFIG_HAVE_KPROBES=y 122CONFIG_HAVE_KPROBES=y
122CONFIG_HAVE_KRETPROBES=y 123CONFIG_HAVE_KRETPROBES=y
124CONFIG_HAVE_ARCH_TRACEHOOK=y
123CONFIG_HAVE_DMA_ATTRS=y 125CONFIG_HAVE_DMA_ATTRS=y
124CONFIG_USE_GENERIC_SMP_HELPERS=y 126CONFIG_USE_GENERIC_SMP_HELPERS=y
127# CONFIG_HAVE_CLK is not set
125CONFIG_PROC_PAGE_MONITOR=y 128CONFIG_PROC_PAGE_MONITOR=y
129# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
126CONFIG_SLABINFO=y 130CONFIG_SLABINFO=y
127CONFIG_RT_MUTEXES=y 131CONFIG_RT_MUTEXES=y
128# CONFIG_TINY_SHMEM is not set 132# CONFIG_TINY_SHMEM is not set
@@ -179,6 +183,7 @@ CONFIG_PS3_STORAGE=y
179CONFIG_PS3_DISK=y 183CONFIG_PS3_DISK=y
180CONFIG_PS3_ROM=y 184CONFIG_PS3_ROM=y
181CONFIG_PS3_FLASH=y 185CONFIG_PS3_FLASH=y
186CONFIG_OPROFILE_PS3=y
182CONFIG_PS3_LPM=m 187CONFIG_PS3_LPM=m
183CONFIG_PPC_CELL=y 188CONFIG_PPC_CELL=y
184# CONFIG_PPC_CELL_NATIVE is not set 189# CONFIG_PPC_CELL_NATIVE is not set
@@ -218,7 +223,7 @@ CONFIG_HZ_250=y
218# CONFIG_HZ_300 is not set 223# CONFIG_HZ_300 is not set
219# CONFIG_HZ_1000 is not set 224# CONFIG_HZ_1000 is not set
220CONFIG_HZ=250 225CONFIG_HZ=250
221# CONFIG_SCHED_HRTICK is not set 226CONFIG_SCHED_HRTICK=y
222CONFIG_PREEMPT_NONE=y 227CONFIG_PREEMPT_NONE=y
223# CONFIG_PREEMPT_VOLUNTARY is not set 228# CONFIG_PREEMPT_VOLUNTARY is not set
224# CONFIG_PREEMPT is not set 229# CONFIG_PREEMPT is not set
@@ -252,8 +257,10 @@ CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
252# CONFIG_SPARSEMEM_VMEMMAP is not set 257# CONFIG_SPARSEMEM_VMEMMAP is not set
253CONFIG_MEMORY_HOTPLUG=y 258CONFIG_MEMORY_HOTPLUG=y
254CONFIG_MEMORY_HOTPLUG_SPARSE=y 259CONFIG_MEMORY_HOTPLUG_SPARSE=y
260# CONFIG_MEMORY_HOTREMOVE is not set
255CONFIG_PAGEFLAGS_EXTENDED=y 261CONFIG_PAGEFLAGS_EXTENDED=y
256CONFIG_SPLIT_PTLOCK_CPUS=4 262CONFIG_SPLIT_PTLOCK_CPUS=4
263CONFIG_MIGRATION=y
257CONFIG_RESOURCES_64BIT=y 264CONFIG_RESOURCES_64BIT=y
258CONFIG_ZONE_DMA_FLAG=1 265CONFIG_ZONE_DMA_FLAG=1
259CONFIG_BOUNCE=y 266CONFIG_BOUNCE=y
@@ -276,19 +283,17 @@ CONFIG_ISA_DMA_API=y
276# 283#
277CONFIG_ZONE_DMA=y 284CONFIG_ZONE_DMA=y
278CONFIG_GENERIC_ISA_DMA=y 285CONFIG_GENERIC_ISA_DMA=y
286CONFIG_PPC_PCI_CHOICE=y
279# CONFIG_PCI is not set 287# CONFIG_PCI is not set
280# CONFIG_PCI_DOMAINS is not set 288# CONFIG_PCI_DOMAINS is not set
281# CONFIG_PCI_SYSCALL is not set 289# CONFIG_PCI_SYSCALL is not set
282# CONFIG_ARCH_SUPPORTS_MSI is not set 290# CONFIG_ARCH_SUPPORTS_MSI is not set
283# CONFIG_PCCARD is not set 291# CONFIG_PCCARD is not set
284# CONFIG_HAS_RAPIDIO is not set 292# CONFIG_HAS_RAPIDIO is not set
293# CONFIG_RELOCATABLE is not set
285CONFIG_PAGE_OFFSET=0xc000000000000000 294CONFIG_PAGE_OFFSET=0xc000000000000000
286CONFIG_KERNEL_START=0xc000000000000000 295CONFIG_KERNEL_START=0xc000000000000000
287CONFIG_PHYSICAL_START=0x00000000 296CONFIG_PHYSICAL_START=0x00000000
288
289#
290# Networking
291#
292CONFIG_NET=y 297CONFIG_NET=y
293 298
294# 299#
@@ -399,9 +404,22 @@ CONFIG_BT_HCIUSB_SCO=y
399# 404#
400# Wireless 405# Wireless
401# 406#
402# CONFIG_CFG80211 is not set 407CONFIG_CFG80211=m
408CONFIG_NL80211=y
403CONFIG_WIRELESS_EXT=y 409CONFIG_WIRELESS_EXT=y
404# CONFIG_MAC80211 is not set 410# CONFIG_WIRELESS_EXT_SYSFS is not set
411CONFIG_MAC80211=m
412
413#
414# Rate control algorithm selection
415#
416CONFIG_MAC80211_RC_PID=y
417CONFIG_MAC80211_RC_DEFAULT_PID=y
418CONFIG_MAC80211_RC_DEFAULT="pid"
419# CONFIG_MAC80211_MESH is not set
420# CONFIG_MAC80211_LEDS is not set
421# CONFIG_MAC80211_DEBUGFS is not set
422# CONFIG_MAC80211_DEBUG_MENU is not set
405CONFIG_IEEE80211=m 423CONFIG_IEEE80211=m
406# CONFIG_IEEE80211_DEBUG is not set 424# CONFIG_IEEE80211_DEBUG is not set
407CONFIG_IEEE80211_CRYPT_WEP=m 425CONFIG_IEEE80211_CRYPT_WEP=m
@@ -420,14 +438,79 @@ CONFIG_IEEE80211_CRYPT_TKIP=m
420CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 438CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
421CONFIG_STANDALONE=y 439CONFIG_STANDALONE=y
422CONFIG_PREVENT_FIRMWARE_BUILD=y 440CONFIG_PREVENT_FIRMWARE_BUILD=y
423CONFIG_FW_LOADER=m 441CONFIG_FW_LOADER=y
424# CONFIG_FIRMWARE_IN_KERNEL is not set 442# CONFIG_FIRMWARE_IN_KERNEL is not set
425CONFIG_EXTRA_FIRMWARE="" 443CONFIG_EXTRA_FIRMWARE=""
426# CONFIG_DEBUG_DRIVER is not set 444# CONFIG_DEBUG_DRIVER is not set
427# CONFIG_DEBUG_DEVRES is not set 445# CONFIG_DEBUG_DEVRES is not set
428# CONFIG_SYS_HYPERVISOR is not set 446# CONFIG_SYS_HYPERVISOR is not set
429# CONFIG_CONNECTOR is not set 447# CONFIG_CONNECTOR is not set
430# CONFIG_MTD is not set 448CONFIG_MTD=y
449CONFIG_MTD_DEBUG=y
450CONFIG_MTD_DEBUG_VERBOSE=0
451# CONFIG_MTD_CONCAT is not set
452# CONFIG_MTD_PARTITIONS is not set
453
454#
455# User Modules And Translation Layers
456#
457# CONFIG_MTD_CHAR is not set
458CONFIG_MTD_BLKDEVS=y
459CONFIG_MTD_BLOCK=y
460# CONFIG_FTL is not set
461# CONFIG_NFTL is not set
462# CONFIG_INFTL is not set
463# CONFIG_RFD_FTL is not set
464# CONFIG_SSFDC is not set
465# CONFIG_MTD_OOPS is not set
466
467#
468# RAM/ROM/Flash chip drivers
469#
470# CONFIG_MTD_CFI is not set
471# CONFIG_MTD_JEDECPROBE is not set
472CONFIG_MTD_MAP_BANK_WIDTH_1=y
473CONFIG_MTD_MAP_BANK_WIDTH_2=y
474CONFIG_MTD_MAP_BANK_WIDTH_4=y
475# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
476# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
477# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
478CONFIG_MTD_CFI_I1=y
479CONFIG_MTD_CFI_I2=y
480# CONFIG_MTD_CFI_I4 is not set
481# CONFIG_MTD_CFI_I8 is not set
482# CONFIG_MTD_RAM is not set
483# CONFIG_MTD_ROM is not set
484# CONFIG_MTD_ABSENT is not set
485
486#
487# Mapping drivers for chip access
488#
489# CONFIG_MTD_COMPLEX_MAPPINGS is not set
490# CONFIG_MTD_PLATRAM is not set
491
492#
493# Self-contained MTD device drivers
494#
495# CONFIG_MTD_SLRAM is not set
496# CONFIG_MTD_PHRAM is not set
497CONFIG_MTD_PS3VRAM=y
498# CONFIG_MTD_MTDRAM is not set
499# CONFIG_MTD_BLOCK2MTD is not set
500
501#
502# Disk-On-Chip Device Drivers
503#
504# CONFIG_MTD_DOC2000 is not set
505# CONFIG_MTD_DOC2001 is not set
506# CONFIG_MTD_DOC2001PLUS is not set
507# CONFIG_MTD_NAND is not set
508# CONFIG_MTD_ONENAND is not set
509
510#
511# UBI - Unsorted block images
512#
513# CONFIG_MTD_UBI is not set
431CONFIG_OF_DEVICE=y 514CONFIG_OF_DEVICE=y
432# CONFIG_PARPORT is not set 515# CONFIG_PARPORT is not set
433CONFIG_BLK_DEV=y 516CONFIG_BLK_DEV=y
@@ -443,6 +526,7 @@ CONFIG_BLK_DEV_RAM_SIZE=65535
443# CONFIG_BLK_DEV_XIP is not set 526# CONFIG_BLK_DEV_XIP is not set
444# CONFIG_CDROM_PKTCDVD is not set 527# CONFIG_CDROM_PKTCDVD is not set
445# CONFIG_ATA_OVER_ETH is not set 528# CONFIG_ATA_OVER_ETH is not set
529# CONFIG_BLK_DEV_HD is not set
446CONFIG_MISC_DEVICES=y 530CONFIG_MISC_DEVICES=y
447# CONFIG_EEPROM_93CX6 is not set 531# CONFIG_EEPROM_93CX6 is not set
448# CONFIG_ENCLOSURE_SERVICES is not set 532# CONFIG_ENCLOSURE_SERVICES is not set
@@ -494,7 +578,6 @@ CONFIG_SCSI_WAIT_SCAN=m
494# CONFIG_MD is not set 578# CONFIG_MD is not set
495# CONFIG_MACINTOSH_DRIVERS is not set 579# CONFIG_MACINTOSH_DRIVERS is not set
496CONFIG_NETDEVICES=y 580CONFIG_NETDEVICES=y
497# CONFIG_NETDEVICES_MULTIQUEUE is not set
498# CONFIG_DUMMY is not set 581# CONFIG_DUMMY is not set
499# CONFIG_BONDING is not set 582# CONFIG_BONDING is not set
500# CONFIG_MACVLAN is not set 583# CONFIG_MACVLAN is not set
@@ -510,9 +593,9 @@ CONFIG_MII=m
510# CONFIG_IBM_NEW_EMAC_EMAC4 is not set 593# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
511# CONFIG_B44 is not set 594# CONFIG_B44 is not set
512CONFIG_NETDEV_1000=y 595CONFIG_NETDEV_1000=y
513# CONFIG_E1000E_ENABLED is not set
514CONFIG_GELIC_NET=y 596CONFIG_GELIC_NET=y
515CONFIG_GELIC_WIRELESS=y 597CONFIG_GELIC_WIRELESS=y
598CONFIG_GELIC_WIRELESS_OLD_PSK_INTERFACE=y
516# CONFIG_NETDEV_10000 is not set 599# CONFIG_NETDEV_10000 is not set
517 600
518# 601#
@@ -523,8 +606,22 @@ CONFIG_WLAN_80211=y
523# CONFIG_LIBERTAS is not set 606# CONFIG_LIBERTAS is not set
524# CONFIG_USB_ZD1201 is not set 607# CONFIG_USB_ZD1201 is not set
525# CONFIG_USB_NET_RNDIS_WLAN is not set 608# CONFIG_USB_NET_RNDIS_WLAN is not set
609# CONFIG_RTL8187 is not set
610# CONFIG_MAC80211_HWSIM is not set
611# CONFIG_P54_COMMON is not set
526# CONFIG_IWLWIFI_LEDS is not set 612# CONFIG_IWLWIFI_LEDS is not set
527# CONFIG_HOSTAP is not set 613# CONFIG_HOSTAP is not set
614# CONFIG_B43 is not set
615# CONFIG_B43LEGACY is not set
616CONFIG_ZD1211RW=m
617# CONFIG_ZD1211RW_DEBUG is not set
618CONFIG_RT2X00=m
619CONFIG_RT2X00_LIB=m
620CONFIG_RT2X00_LIB_USB=m
621CONFIG_RT2X00_LIB_FIRMWARE=y
622# CONFIG_RT2500USB is not set
623CONFIG_RT73USB=m
624# CONFIG_RT2X00_DEBUG is not set
528 625
529# 626#
530# USB Network Adapters 627# USB Network Adapters
@@ -622,6 +719,7 @@ CONFIG_INPUT_JOYSTICK=y
622# Character devices 719# Character devices
623# 720#
624CONFIG_VT=y 721CONFIG_VT=y
722CONFIG_CONSOLE_TRANSLATIONS=y
625CONFIG_VT_CONSOLE=y 723CONFIG_VT_CONSOLE=y
626CONFIG_HW_CONSOLE=y 724CONFIG_HW_CONSOLE=y
627CONFIG_VT_HW_CONSOLE_BINDING=y 725CONFIG_VT_HW_CONSOLE_BINDING=y
@@ -647,6 +745,8 @@ CONFIG_LEGACY_PTY_COUNT=16
647# CONFIG_TCG_TPM is not set 745# CONFIG_TCG_TPM is not set
648# CONFIG_I2C is not set 746# CONFIG_I2C is not set
649# CONFIG_SPI is not set 747# CONFIG_SPI is not set
748CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
749# CONFIG_GPIOLIB is not set
650# CONFIG_W1 is not set 750# CONFIG_W1 is not set
651# CONFIG_POWER_SUPPLY is not set 751# CONFIG_POWER_SUPPLY is not set
652# CONFIG_HWMON is not set 752# CONFIG_HWMON is not set
@@ -663,8 +763,10 @@ CONFIG_SSB_POSSIBLE=y
663# 763#
664# Multifunction device drivers 764# Multifunction device drivers
665# 765#
766# CONFIG_MFD_CORE is not set
666# CONFIG_MFD_SM501 is not set 767# CONFIG_MFD_SM501 is not set
667# CONFIG_HTC_PASIC3 is not set 768# CONFIG_HTC_PASIC3 is not set
769# CONFIG_MFD_TMIO is not set
668 770
669# 771#
670# Multimedia devices 772# Multimedia devices
@@ -796,6 +898,7 @@ CONFIG_USB_DEVICEFS=y
796# CONFIG_USB_DYNAMIC_MINORS is not set 898# CONFIG_USB_DYNAMIC_MINORS is not set
797CONFIG_USB_SUSPEND=y 899CONFIG_USB_SUSPEND=y
798# CONFIG_USB_OTG is not set 900# CONFIG_USB_OTG is not set
901CONFIG_USB_MON=y
799 902
800# 903#
801# USB Host Controller Drivers 904# USB Host Controller Drivers
@@ -817,6 +920,10 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y
817# CONFIG_USB_R8A66597_HCD is not set 920# CONFIG_USB_R8A66597_HCD is not set
818 921
819# 922#
923# Enable Host or Gadget support to see Inventra options
924#
925
926#
820# USB Device Class drivers 927# USB Device Class drivers
821# 928#
822# CONFIG_USB_ACM is not set 929# CONFIG_USB_ACM is not set
@@ -843,6 +950,7 @@ CONFIG_USB_STORAGE=m
843# CONFIG_USB_STORAGE_ALAUDA is not set 950# CONFIG_USB_STORAGE_ALAUDA is not set
844# CONFIG_USB_STORAGE_ONETOUCH is not set 951# CONFIG_USB_STORAGE_ONETOUCH is not set
845# CONFIG_USB_STORAGE_KARMA is not set 952# CONFIG_USB_STORAGE_KARMA is not set
953# CONFIG_USB_STORAGE_SIERRA is not set
846# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set 954# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
847# CONFIG_USB_LIBUSUAL is not set 955# CONFIG_USB_LIBUSUAL is not set
848 956
@@ -851,7 +959,6 @@ CONFIG_USB_STORAGE=m
851# 959#
852# CONFIG_USB_MDC800 is not set 960# CONFIG_USB_MDC800 is not set
853# CONFIG_USB_MICROTEK is not set 961# CONFIG_USB_MICROTEK is not set
854CONFIG_USB_MON=y
855 962
856# 963#
857# USB port drivers 964# USB port drivers
@@ -864,7 +971,6 @@ CONFIG_USB_MON=y
864# CONFIG_USB_EMI62 is not set 971# CONFIG_USB_EMI62 is not set
865# CONFIG_USB_EMI26 is not set 972# CONFIG_USB_EMI26 is not set
866# CONFIG_USB_ADUTUX is not set 973# CONFIG_USB_ADUTUX is not set
867# CONFIG_USB_AUERSWALD is not set
868# CONFIG_USB_RIO500 is not set 974# CONFIG_USB_RIO500 is not set
869# CONFIG_USB_LEGOTOWER is not set 975# CONFIG_USB_LEGOTOWER is not set
870# CONFIG_USB_LCD is not set 976# CONFIG_USB_LCD is not set
@@ -998,9 +1104,11 @@ CONFIG_HUGETLB_PAGE=y
998# CONFIG_BEFS_FS is not set 1104# CONFIG_BEFS_FS is not set
999# CONFIG_BFS_FS is not set 1105# CONFIG_BFS_FS is not set
1000# CONFIG_EFS_FS is not set 1106# CONFIG_EFS_FS is not set
1107# CONFIG_JFFS2_FS is not set
1001# CONFIG_CRAMFS is not set 1108# CONFIG_CRAMFS is not set
1002# CONFIG_VXFS_FS is not set 1109# CONFIG_VXFS_FS is not set
1003# CONFIG_MINIX_FS is not set 1110# CONFIG_MINIX_FS is not set
1111# CONFIG_OMFS_FS is not set
1004# CONFIG_HPFS_FS is not set 1112# CONFIG_HPFS_FS is not set
1005# CONFIG_QNX4FS_FS is not set 1113# CONFIG_QNX4FS_FS is not set
1006# CONFIG_ROMFS_FS is not set 1114# CONFIG_ROMFS_FS is not set
@@ -1011,14 +1119,13 @@ CONFIG_NFS_FS=y
1011CONFIG_NFS_V3=y 1119CONFIG_NFS_V3=y
1012# CONFIG_NFS_V3_ACL is not set 1120# CONFIG_NFS_V3_ACL is not set
1013CONFIG_NFS_V4=y 1121CONFIG_NFS_V4=y
1014# CONFIG_NFSD is not set
1015CONFIG_ROOT_NFS=y 1122CONFIG_ROOT_NFS=y
1123# CONFIG_NFSD is not set
1016CONFIG_LOCKD=y 1124CONFIG_LOCKD=y
1017CONFIG_LOCKD_V4=y 1125CONFIG_LOCKD_V4=y
1018CONFIG_NFS_COMMON=y 1126CONFIG_NFS_COMMON=y
1019CONFIG_SUNRPC=y 1127CONFIG_SUNRPC=y
1020CONFIG_SUNRPC_GSS=y 1128CONFIG_SUNRPC_GSS=y
1021# CONFIG_SUNRPC_BIND34 is not set
1022CONFIG_RPCSEC_GSS_KRB5=y 1129CONFIG_RPCSEC_GSS_KRB5=y
1023# CONFIG_RPCSEC_GSS_SPKM3 is not set 1130# CONFIG_RPCSEC_GSS_SPKM3 is not set
1024# CONFIG_SMB_FS is not set 1131# CONFIG_SMB_FS is not set
@@ -1086,7 +1193,7 @@ CONFIG_BITREVERSE=y
1086# CONFIG_GENERIC_FIND_FIRST_BIT is not set 1193# CONFIG_GENERIC_FIND_FIRST_BIT is not set
1087CONFIG_CRC_CCITT=m 1194CONFIG_CRC_CCITT=m
1088# CONFIG_CRC16 is not set 1195# CONFIG_CRC16 is not set
1089# CONFIG_CRC_T10DIF is not set 1196CONFIG_CRC_T10DIF=y
1090CONFIG_CRC_ITU_T=m 1197CONFIG_CRC_ITU_T=m
1091CONFIG_CRC32=y 1198CONFIG_CRC32=y
1092# CONFIG_CRC7 is not set 1199# CONFIG_CRC7 is not set
@@ -1115,6 +1222,8 @@ CONFIG_DEBUG_FS=y
1115CONFIG_DEBUG_KERNEL=y 1222CONFIG_DEBUG_KERNEL=y
1116# CONFIG_DEBUG_SHIRQ is not set 1223# CONFIG_DEBUG_SHIRQ is not set
1117CONFIG_DETECT_SOFTLOCKUP=y 1224CONFIG_DETECT_SOFTLOCKUP=y
1225# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
1226CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
1118CONFIG_SCHED_DEBUG=y 1227CONFIG_SCHED_DEBUG=y
1119# CONFIG_SCHEDSTATS is not set 1228# CONFIG_SCHEDSTATS is not set
1120# CONFIG_TIMER_STATS is not set 1229# CONFIG_TIMER_STATS is not set
@@ -1138,6 +1247,7 @@ CONFIG_DEBUG_BUGVERBOSE=y
1138CONFIG_DEBUG_INFO=y 1247CONFIG_DEBUG_INFO=y
1139# CONFIG_DEBUG_VM is not set 1248# CONFIG_DEBUG_VM is not set
1140CONFIG_DEBUG_WRITECOUNT=y 1249CONFIG_DEBUG_WRITECOUNT=y
1250CONFIG_DEBUG_MEMORY_INIT=y
1141CONFIG_DEBUG_LIST=y 1251CONFIG_DEBUG_LIST=y
1142# CONFIG_DEBUG_SG is not set 1252# CONFIG_DEBUG_SG is not set
1143CONFIG_FRAME_POINTER=y 1253CONFIG_FRAME_POINTER=y
@@ -1146,6 +1256,7 @@ CONFIG_FRAME_POINTER=y
1146# CONFIG_BACKTRACE_SELF_TEST is not set 1256# CONFIG_BACKTRACE_SELF_TEST is not set
1147# CONFIG_FAULT_INJECTION is not set 1257# CONFIG_FAULT_INJECTION is not set
1148# CONFIG_LATENCYTOP is not set 1258# CONFIG_LATENCYTOP is not set
1259CONFIG_SYSCTL_SYSCALL_CHECK=y
1149CONFIG_HAVE_FTRACE=y 1260CONFIG_HAVE_FTRACE=y
1150CONFIG_HAVE_DYNAMIC_FTRACE=y 1261CONFIG_HAVE_DYNAMIC_FTRACE=y
1151# CONFIG_FTRACE is not set 1262# CONFIG_FTRACE is not set
@@ -1153,12 +1264,14 @@ CONFIG_HAVE_DYNAMIC_FTRACE=y
1153# CONFIG_SCHED_TRACER is not set 1264# CONFIG_SCHED_TRACER is not set
1154# CONFIG_CONTEXT_SWITCH_TRACER is not set 1265# CONFIG_CONTEXT_SWITCH_TRACER is not set
1155# CONFIG_SAMPLES is not set 1266# CONFIG_SAMPLES is not set
1267CONFIG_HAVE_ARCH_KGDB=y
1268# CONFIG_KGDB is not set
1156CONFIG_DEBUG_STACKOVERFLOW=y 1269CONFIG_DEBUG_STACKOVERFLOW=y
1157# CONFIG_DEBUG_STACK_USAGE is not set 1270# CONFIG_DEBUG_STACK_USAGE is not set
1158# CONFIG_DEBUG_PAGEALLOC is not set 1271# CONFIG_DEBUG_PAGEALLOC is not set
1159# CONFIG_DEBUGGER is not set
1160# CONFIG_CODE_PATCHING_SELFTEST is not set 1272# CONFIG_CODE_PATCHING_SELFTEST is not set
1161# CONFIG_FTR_FIXUP_SELFTEST is not set 1273# CONFIG_FTR_FIXUP_SELFTEST is not set
1274# CONFIG_XMON is not set
1162CONFIG_IRQSTACKS=y 1275CONFIG_IRQSTACKS=y
1163# CONFIG_VIRQ_DEBUG is not set 1276# CONFIG_VIRQ_DEBUG is not set
1164# CONFIG_BOOTX_TEXT is not set 1277# CONFIG_BOOTX_TEXT is not set
diff --git a/arch/powerpc/configs/pseries_defconfig b/arch/powerpc/configs/pseries_defconfig
index fe6ffa683d78..e77c5e7a0be2 100644
--- a/arch/powerpc/configs/pseries_defconfig
+++ b/arch/powerpc/configs/pseries_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc3 3# Linux kernel version: 2.6.27-rc4
4# Tue May 20 20:03:28 2008 4# Tue Aug 26 13:31:07 2008
5# 5#
6CONFIG_PPC64=y 6CONFIG_PPC64=y
7 7
@@ -14,6 +14,7 @@ CONFIG_POWER4=y
14# CONFIG_TUNE_CELL is not set 14# CONFIG_TUNE_CELL is not set
15CONFIG_PPC_FPU=y 15CONFIG_PPC_FPU=y
16CONFIG_ALTIVEC=y 16CONFIG_ALTIVEC=y
17CONFIG_VSX=y
17CONFIG_PPC_STD_MMU=y 18CONFIG_PPC_STD_MMU=y
18CONFIG_PPC_MM_SLICES=y 19CONFIG_PPC_MM_SLICES=y
19CONFIG_VIRT_CPU_ACCOUNTING=y 20CONFIG_VIRT_CPU_ACCOUNTING=y
@@ -31,6 +32,7 @@ CONFIG_GENERIC_HARDIRQS=y
31CONFIG_HAVE_SETUP_PER_CPU_AREA=y 32CONFIG_HAVE_SETUP_PER_CPU_AREA=y
32CONFIG_IRQ_PER_CPU=y 33CONFIG_IRQ_PER_CPU=y
33CONFIG_STACKTRACE_SUPPORT=y 34CONFIG_STACKTRACE_SUPPORT=y
35CONFIG_HAVE_LATENCYTOP_SUPPORT=y
34CONFIG_TRACE_IRQFLAGS_SUPPORT=y 36CONFIG_TRACE_IRQFLAGS_SUPPORT=y
35CONFIG_LOCKDEP_SUPPORT=y 37CONFIG_LOCKDEP_SUPPORT=y
36CONFIG_RWSEM_XCHGADD_ALGORITHM=y 38CONFIG_RWSEM_XCHGADD_ALGORITHM=y
@@ -104,7 +106,6 @@ CONFIG_CC_OPTIMIZE_FOR_SIZE=y
104CONFIG_SYSCTL=y 106CONFIG_SYSCTL=y
105# CONFIG_EMBEDDED is not set 107# CONFIG_EMBEDDED is not set
106CONFIG_SYSCTL_SYSCALL=y 108CONFIG_SYSCTL_SYSCALL=y
107CONFIG_SYSCTL_SYSCALL_CHECK=y
108CONFIG_KALLSYMS=y 109CONFIG_KALLSYMS=y
109CONFIG_KALLSYMS_ALL=y 110CONFIG_KALLSYMS_ALL=y
110# CONFIG_KALLSYMS_EXTRA_PASS is not set 111# CONFIG_KALLSYMS_EXTRA_PASS is not set
@@ -132,11 +133,17 @@ CONFIG_MARKERS=y
132CONFIG_OPROFILE=y 133CONFIG_OPROFILE=y
133CONFIG_HAVE_OPROFILE=y 134CONFIG_HAVE_OPROFILE=y
134CONFIG_KPROBES=y 135CONFIG_KPROBES=y
136CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
135CONFIG_KRETPROBES=y 137CONFIG_KRETPROBES=y
138CONFIG_HAVE_IOREMAP_PROT=y
136CONFIG_HAVE_KPROBES=y 139CONFIG_HAVE_KPROBES=y
137CONFIG_HAVE_KRETPROBES=y 140CONFIG_HAVE_KRETPROBES=y
138# CONFIG_HAVE_DMA_ATTRS is not set 141CONFIG_HAVE_ARCH_TRACEHOOK=y
142CONFIG_HAVE_DMA_ATTRS=y
143CONFIG_USE_GENERIC_SMP_HELPERS=y
144# CONFIG_HAVE_CLK is not set
139CONFIG_PROC_PAGE_MONITOR=y 145CONFIG_PROC_PAGE_MONITOR=y
146# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
140CONFIG_SLABINFO=y 147CONFIG_SLABINFO=y
141CONFIG_RT_MUTEXES=y 148CONFIG_RT_MUTEXES=y
142# CONFIG_TINY_SHMEM is not set 149# CONFIG_TINY_SHMEM is not set
@@ -152,6 +159,7 @@ CONFIG_STOP_MACHINE=y
152CONFIG_BLOCK=y 159CONFIG_BLOCK=y
153# CONFIG_BLK_DEV_IO_TRACE is not set 160# CONFIG_BLK_DEV_IO_TRACE is not set
154CONFIG_BLK_DEV_BSG=y 161CONFIG_BLK_DEV_BSG=y
162# CONFIG_BLK_DEV_INTEGRITY is not set
155CONFIG_BLOCK_COMPAT=y 163CONFIG_BLOCK_COMPAT=y
156 164
157# 165#
@@ -172,17 +180,14 @@ CONFIG_CLASSIC_RCU=y
172# Platform support 180# Platform support
173# 181#
174CONFIG_PPC_MULTIPLATFORM=y 182CONFIG_PPC_MULTIPLATFORM=y
175# CONFIG_PPC_82xx is not set
176# CONFIG_PPC_83xx is not set
177# CONFIG_PPC_86xx is not set
178CONFIG_PPC_PSERIES=y 183CONFIG_PPC_PSERIES=y
179CONFIG_PPC_SPLPAR=y 184CONFIG_PPC_SPLPAR=y
180CONFIG_EEH=y 185CONFIG_EEH=y
181CONFIG_SCANLOG=m 186CONFIG_SCANLOG=m
182CONFIG_LPARCFG=y 187CONFIG_LPARCFG=y
188CONFIG_PPC_SMLPAR=y
189CONFIG_CMM=y
183# CONFIG_PPC_ISERIES is not set 190# CONFIG_PPC_ISERIES is not set
184# CONFIG_PPC_MPC512x is not set
185# CONFIG_PPC_MPC5121 is not set
186# CONFIG_PPC_PMAC is not set 191# CONFIG_PPC_PMAC is not set
187# CONFIG_PPC_MAPLE is not set 192# CONFIG_PPC_MAPLE is not set
188# CONFIG_PPC_PASEMI is not set 193# CONFIG_PPC_PASEMI is not set
@@ -226,7 +231,7 @@ CONFIG_HZ_250=y
226# CONFIG_HZ_300 is not set 231# CONFIG_HZ_300 is not set
227# CONFIG_HZ_1000 is not set 232# CONFIG_HZ_1000 is not set
228CONFIG_HZ=250 233CONFIG_HZ=250
229# CONFIG_SCHED_HRTICK is not set 234CONFIG_SCHED_HRTICK=y
230CONFIG_PREEMPT_NONE=y 235CONFIG_PREEMPT_NONE=y
231# CONFIG_PREEMPT_VOLUNTARY is not set 236# CONFIG_PREEMPT_VOLUNTARY is not set
232# CONFIG_PREEMPT is not set 237# CONFIG_PREEMPT is not set
@@ -275,6 +280,7 @@ CONFIG_FORCE_MAX_ZONEORDER=13
275CONFIG_SCHED_SMT=y 280CONFIG_SCHED_SMT=y
276CONFIG_PROC_DEVICETREE=y 281CONFIG_PROC_DEVICETREE=y
277# CONFIG_CMDLINE_BOOL is not set 282# CONFIG_CMDLINE_BOOL is not set
283CONFIG_EXTRA_TARGETS=""
278# CONFIG_PM is not set 284# CONFIG_PM is not set
279CONFIG_SECCOMP=y 285CONFIG_SECCOMP=y
280CONFIG_ISA_DMA_API=y 286CONFIG_ISA_DMA_API=y
@@ -304,10 +310,6 @@ CONFIG_HOTPLUG_PCI_RPA_DLPAR=m
304CONFIG_PAGE_OFFSET=0xc000000000000000 310CONFIG_PAGE_OFFSET=0xc000000000000000
305CONFIG_KERNEL_START=0xc000000000000000 311CONFIG_KERNEL_START=0xc000000000000000
306CONFIG_PHYSICAL_START=0x00000000 312CONFIG_PHYSICAL_START=0x00000000
307
308#
309# Networking
310#
311CONFIG_NET=y 313CONFIG_NET=y
312 314
313# 315#
@@ -321,6 +323,7 @@ CONFIG_XFRM_USER=m
321# CONFIG_XFRM_SUB_POLICY is not set 323# CONFIG_XFRM_SUB_POLICY is not set
322# CONFIG_XFRM_MIGRATE is not set 324# CONFIG_XFRM_MIGRATE is not set
323# CONFIG_XFRM_STATISTICS is not set 325# CONFIG_XFRM_STATISTICS is not set
326CONFIG_XFRM_IPCOMP=m
324CONFIG_NET_KEY=m 327CONFIG_NET_KEY=m
325# CONFIG_NET_KEY_MIGRATE is not set 328# CONFIG_NET_KEY_MIGRATE is not set
326CONFIG_INET=y 329CONFIG_INET=y
@@ -498,6 +501,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
498CONFIG_STANDALONE=y 501CONFIG_STANDALONE=y
499CONFIG_PREVENT_FIRMWARE_BUILD=y 502CONFIG_PREVENT_FIRMWARE_BUILD=y
500CONFIG_FW_LOADER=y 503CONFIG_FW_LOADER=y
504CONFIG_FIRMWARE_IN_KERNEL=y
505CONFIG_EXTRA_FIRMWARE=""
501# CONFIG_DEBUG_DRIVER is not set 506# CONFIG_DEBUG_DRIVER is not set
502# CONFIG_DEBUG_DEVRES is not set 507# CONFIG_DEBUG_DEVRES is not set
503# CONFIG_SYS_HYPERVISOR is not set 508# CONFIG_SYS_HYPERVISOR is not set
@@ -531,12 +536,14 @@ CONFIG_BLK_DEV_RAM_SIZE=65536
531# CONFIG_BLK_DEV_XIP is not set 536# CONFIG_BLK_DEV_XIP is not set
532# CONFIG_CDROM_PKTCDVD is not set 537# CONFIG_CDROM_PKTCDVD is not set
533# CONFIG_ATA_OVER_ETH is not set 538# CONFIG_ATA_OVER_ETH is not set
539# CONFIG_BLK_DEV_HD is not set
534CONFIG_MISC_DEVICES=y 540CONFIG_MISC_DEVICES=y
535# CONFIG_PHANTOM is not set 541# CONFIG_PHANTOM is not set
536# CONFIG_EEPROM_93CX6 is not set 542# CONFIG_EEPROM_93CX6 is not set
537# CONFIG_SGI_IOC4 is not set 543# CONFIG_SGI_IOC4 is not set
538# CONFIG_TIFM_CORE is not set 544# CONFIG_TIFM_CORE is not set
539# CONFIG_ENCLOSURE_SERVICES is not set 545# CONFIG_ENCLOSURE_SERVICES is not set
546# CONFIG_HP_ILO is not set
540CONFIG_HAVE_IDE=y 547CONFIG_HAVE_IDE=y
541CONFIG_IDE=y 548CONFIG_IDE=y
542CONFIG_BLK_DEV_IDE=y 549CONFIG_BLK_DEV_IDE=y
@@ -544,6 +551,7 @@ CONFIG_BLK_DEV_IDE=y
544# 551#
545# Please see Documentation/ide/ide.txt for help/info on IDE drives 552# Please see Documentation/ide/ide.txt for help/info on IDE drives
546# 553#
554CONFIG_IDE_TIMINGS=y
547# CONFIG_BLK_DEV_IDE_SATA is not set 555# CONFIG_BLK_DEV_IDE_SATA is not set
548CONFIG_BLK_DEV_IDEDISK=y 556CONFIG_BLK_DEV_IDEDISK=y
549# CONFIG_IDEDISK_MULTI_MODE is not set 557# CONFIG_IDEDISK_MULTI_MODE is not set
@@ -575,10 +583,8 @@ CONFIG_BLK_DEV_IDEDMA_PCI=y
575CONFIG_BLK_DEV_AMD74XX=y 583CONFIG_BLK_DEV_AMD74XX=y
576# CONFIG_BLK_DEV_CMD64X is not set 584# CONFIG_BLK_DEV_CMD64X is not set
577# CONFIG_BLK_DEV_TRIFLEX is not set 585# CONFIG_BLK_DEV_TRIFLEX is not set
578# CONFIG_BLK_DEV_CY82C693 is not set
579# CONFIG_BLK_DEV_CS5520 is not set 586# CONFIG_BLK_DEV_CS5520 is not set
580# CONFIG_BLK_DEV_CS5530 is not set 587# CONFIG_BLK_DEV_CS5530 is not set
581# CONFIG_BLK_DEV_HPT34X is not set
582# CONFIG_BLK_DEV_HPT366 is not set 588# CONFIG_BLK_DEV_HPT366 is not set
583# CONFIG_BLK_DEV_JMICRON is not set 589# CONFIG_BLK_DEV_JMICRON is not set
584# CONFIG_BLK_DEV_SC1200 is not set 590# CONFIG_BLK_DEV_SC1200 is not set
@@ -596,8 +602,6 @@ CONFIG_BLK_DEV_AMD74XX=y
596# CONFIG_BLK_DEV_VIA82CXXX is not set 602# CONFIG_BLK_DEV_VIA82CXXX is not set
597# CONFIG_BLK_DEV_TC86C001 is not set 603# CONFIG_BLK_DEV_TC86C001 is not set
598CONFIG_BLK_DEV_IDEDMA=y 604CONFIG_BLK_DEV_IDEDMA=y
599# CONFIG_BLK_DEV_HD_ONLY is not set
600# CONFIG_BLK_DEV_HD is not set
601 605
602# 606#
603# SCSI device support 607# SCSI device support
@@ -659,6 +663,8 @@ CONFIG_SCSI_LOWLEVEL=y
659# CONFIG_SCSI_GDTH is not set 663# CONFIG_SCSI_GDTH is not set
660# CONFIG_SCSI_IPS is not set 664# CONFIG_SCSI_IPS is not set
661CONFIG_SCSI_IBMVSCSI=y 665CONFIG_SCSI_IBMVSCSI=y
666CONFIG_SCSI_IBMVFC=m
667CONFIG_SCSI_IBMVFC_TRACE=y
662# CONFIG_SCSI_INITIO is not set 668# CONFIG_SCSI_INITIO is not set
663# CONFIG_SCSI_INIA100 is not set 669# CONFIG_SCSI_INIA100 is not set
664# CONFIG_SCSI_PPA is not set 670# CONFIG_SCSI_PPA is not set
@@ -681,6 +687,7 @@ CONFIG_SCSI_LPFC=m
681# CONFIG_SCSI_DC390T is not set 687# CONFIG_SCSI_DC390T is not set
682# CONFIG_SCSI_DEBUG is not set 688# CONFIG_SCSI_DEBUG is not set
683# CONFIG_SCSI_SRP is not set 689# CONFIG_SCSI_SRP is not set
690# CONFIG_SCSI_DH is not set
684CONFIG_ATA=y 691CONFIG_ATA=y
685# CONFIG_ATA_NONSTANDARD is not set 692# CONFIG_ATA_NONSTANDARD is not set
686CONFIG_SATA_PMP=y 693CONFIG_SATA_PMP=y
@@ -703,9 +710,6 @@ CONFIG_DM_SNAPSHOT=m
703CONFIG_DM_MIRROR=m 710CONFIG_DM_MIRROR=m
704CONFIG_DM_ZERO=m 711CONFIG_DM_ZERO=m
705CONFIG_DM_MULTIPATH=m 712CONFIG_DM_MULTIPATH=m
706CONFIG_DM_MULTIPATH_EMC=m
707# CONFIG_DM_MULTIPATH_RDAC is not set
708# CONFIG_DM_MULTIPATH_HP is not set
709# CONFIG_DM_DELAY is not set 713# CONFIG_DM_DELAY is not set
710# CONFIG_DM_UEVENT is not set 714# CONFIG_DM_UEVENT is not set
711# CONFIG_FUSION is not set 715# CONFIG_FUSION is not set
@@ -713,12 +717,15 @@ CONFIG_DM_MULTIPATH_EMC=m
713# 717#
714# IEEE 1394 (FireWire) support 718# IEEE 1394 (FireWire) support
715# 719#
720
721#
722# Enable only one of the two stacks, unless you know what you are doing
723#
716# CONFIG_FIREWIRE is not set 724# CONFIG_FIREWIRE is not set
717# CONFIG_IEEE1394 is not set 725# CONFIG_IEEE1394 is not set
718# CONFIG_I2O is not set 726# CONFIG_I2O is not set
719# CONFIG_MACINTOSH_DRIVERS is not set 727# CONFIG_MACINTOSH_DRIVERS is not set
720CONFIG_NETDEVICES=y 728CONFIG_NETDEVICES=y
721# CONFIG_NETDEVICES_MULTIQUEUE is not set
722CONFIG_DUMMY=m 729CONFIG_DUMMY=m
723CONFIG_BONDING=m 730CONFIG_BONDING=m
724# CONFIG_MACVLAN is not set 731# CONFIG_MACVLAN is not set
@@ -726,7 +733,23 @@ CONFIG_BONDING=m
726CONFIG_TUN=m 733CONFIG_TUN=m
727# CONFIG_VETH is not set 734# CONFIG_VETH is not set
728# CONFIG_ARCNET is not set 735# CONFIG_ARCNET is not set
729# CONFIG_PHYLIB is not set 736CONFIG_PHYLIB=y
737
738#
739# MII PHY device drivers
740#
741# CONFIG_MARVELL_PHY is not set
742# CONFIG_DAVICOM_PHY is not set
743# CONFIG_QSEMI_PHY is not set
744# CONFIG_LXT_PHY is not set
745# CONFIG_CICADA_PHY is not set
746# CONFIG_VITESSE_PHY is not set
747# CONFIG_SMSC_PHY is not set
748# CONFIG_BROADCOM_PHY is not set
749# CONFIG_ICPLUS_PHY is not set
750# CONFIG_REALTEK_PHY is not set
751# CONFIG_FIXED_PHY is not set
752# CONFIG_MDIO_BITBANG is not set
730CONFIG_NET_ETHERNET=y 753CONFIG_NET_ETHERNET=y
731CONFIG_MII=y 754CONFIG_MII=y
732# CONFIG_HAPPYMEAL is not set 755# CONFIG_HAPPYMEAL is not set
@@ -759,6 +782,7 @@ CONFIG_E100=y
759# CONFIG_SIS900 is not set 782# CONFIG_SIS900 is not set
760# CONFIG_EPIC100 is not set 783# CONFIG_EPIC100 is not set
761# CONFIG_SUNDANCE is not set 784# CONFIG_SUNDANCE is not set
785# CONFIG_TLAN is not set
762# CONFIG_VIA_RHINE is not set 786# CONFIG_VIA_RHINE is not set
763# CONFIG_SC92031 is not set 787# CONFIG_SC92031 is not set
764# CONFIG_NET_POCKET is not set 788# CONFIG_NET_POCKET is not set
@@ -767,10 +791,8 @@ CONFIG_ACENIC=y
767CONFIG_ACENIC_OMIT_TIGON_I=y 791CONFIG_ACENIC_OMIT_TIGON_I=y
768# CONFIG_DL2K is not set 792# CONFIG_DL2K is not set
769CONFIG_E1000=y 793CONFIG_E1000=y
770# CONFIG_E1000_NAPI is not set
771# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set 794# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
772# CONFIG_E1000E is not set 795# CONFIG_E1000E is not set
773# CONFIG_E1000E_ENABLED is not set
774# CONFIG_IP1000 is not set 796# CONFIG_IP1000 is not set
775# CONFIG_IGB is not set 797# CONFIG_IGB is not set
776# CONFIG_NS83820 is not set 798# CONFIG_NS83820 is not set
@@ -785,14 +807,14 @@ CONFIG_TIGON3=y
785# CONFIG_BNX2 is not set 807# CONFIG_BNX2 is not set
786# CONFIG_QLA3XXX is not set 808# CONFIG_QLA3XXX is not set
787# CONFIG_ATL1 is not set 809# CONFIG_ATL1 is not set
810# CONFIG_ATL1E is not set
788CONFIG_NETDEV_10000=y 811CONFIG_NETDEV_10000=y
789# CONFIG_CHELSIO_T1 is not set 812# CONFIG_CHELSIO_T1 is not set
790# CONFIG_CHELSIO_T3 is not set 813# CONFIG_CHELSIO_T3 is not set
814CONFIG_EHEA=y
791# CONFIG_IXGBE is not set 815# CONFIG_IXGBE is not set
792CONFIG_IXGB=m 816CONFIG_IXGB=m
793# CONFIG_IXGB_NAPI is not set
794CONFIG_S2IO=m 817CONFIG_S2IO=m
795# CONFIG_S2IO_NAPI is not set
796# CONFIG_MYRI10GE is not set 818# CONFIG_MYRI10GE is not set
797# CONFIG_NETXEN_NIC is not set 819# CONFIG_NETXEN_NIC is not set
798# CONFIG_NIU is not set 820# CONFIG_NIU is not set
@@ -883,6 +905,7 @@ CONFIG_MOUSE_PS2_TRACKPOINT=y
883# CONFIG_MOUSE_PS2_TOUCHKIT is not set 905# CONFIG_MOUSE_PS2_TOUCHKIT is not set
884# CONFIG_MOUSE_SERIAL is not set 906# CONFIG_MOUSE_SERIAL is not set
885# CONFIG_MOUSE_APPLETOUCH is not set 907# CONFIG_MOUSE_APPLETOUCH is not set
908# CONFIG_MOUSE_BCM5974 is not set
886# CONFIG_MOUSE_VSXXXAA is not set 909# CONFIG_MOUSE_VSXXXAA is not set
887# CONFIG_INPUT_JOYSTICK is not set 910# CONFIG_INPUT_JOYSTICK is not set
888# CONFIG_INPUT_TABLET is not set 911# CONFIG_INPUT_TABLET is not set
@@ -906,12 +929,14 @@ CONFIG_SERIO_I8042=y
906# CONFIG_SERIO_PCIPS2 is not set 929# CONFIG_SERIO_PCIPS2 is not set
907CONFIG_SERIO_LIBPS2=y 930CONFIG_SERIO_LIBPS2=y
908# CONFIG_SERIO_RAW is not set 931# CONFIG_SERIO_RAW is not set
932# CONFIG_SERIO_XILINX_XPS_PS2 is not set
909# CONFIG_GAMEPORT is not set 933# CONFIG_GAMEPORT is not set
910 934
911# 935#
912# Character devices 936# Character devices
913# 937#
914CONFIG_VT=y 938CONFIG_VT=y
939CONFIG_CONSOLE_TRANSLATIONS=y
915CONFIG_VT_CONSOLE=y 940CONFIG_VT_CONSOLE=y
916CONFIG_HW_CONSOLE=y 941CONFIG_HW_CONSOLE=y
917# CONFIG_VT_HW_CONSOLE_BINDING is not set 942# CONFIG_VT_HW_CONSOLE_BINDING is not set
@@ -943,6 +968,7 @@ CONFIG_LEGACY_PTY_COUNT=256
943# CONFIG_PRINTER is not set 968# CONFIG_PRINTER is not set
944# CONFIG_PPDEV is not set 969# CONFIG_PPDEV is not set
945CONFIG_HVC_DRIVER=y 970CONFIG_HVC_DRIVER=y
971CONFIG_HVC_IRQ=y
946CONFIG_HVC_CONSOLE=y 972CONFIG_HVC_CONSOLE=y
947CONFIG_HVC_RTAS=y 973CONFIG_HVC_RTAS=y
948CONFIG_HVCS=m 974CONFIG_HVCS=m
@@ -961,44 +987,65 @@ CONFIG_DEVPORT=y
961CONFIG_I2C=y 987CONFIG_I2C=y
962CONFIG_I2C_BOARDINFO=y 988CONFIG_I2C_BOARDINFO=y
963# CONFIG_I2C_CHARDEV is not set 989# CONFIG_I2C_CHARDEV is not set
990CONFIG_I2C_HELPER_AUTO=y
964CONFIG_I2C_ALGOBIT=y 991CONFIG_I2C_ALGOBIT=y
965 992
966# 993#
967# I2C Hardware Bus support 994# I2C Hardware Bus support
968# 995#
996
997#
998# PC SMBus host controller drivers
999#
969# CONFIG_I2C_ALI1535 is not set 1000# CONFIG_I2C_ALI1535 is not set
970# CONFIG_I2C_ALI1563 is not set 1001# CONFIG_I2C_ALI1563 is not set
971# CONFIG_I2C_ALI15X3 is not set 1002# CONFIG_I2C_ALI15X3 is not set
972# CONFIG_I2C_AMD756 is not set 1003# CONFIG_I2C_AMD756 is not set
973# CONFIG_I2C_AMD8111 is not set 1004# CONFIG_I2C_AMD8111 is not set
974# CONFIG_I2C_I801 is not set 1005# CONFIG_I2C_I801 is not set
975# CONFIG_I2C_I810 is not set 1006# CONFIG_I2C_ISCH is not set
976# CONFIG_I2C_PIIX4 is not set 1007# CONFIG_I2C_PIIX4 is not set
977# CONFIG_I2C_NFORCE2 is not set 1008# CONFIG_I2C_NFORCE2 is not set
978# CONFIG_I2C_OCORES is not set
979# CONFIG_I2C_PARPORT is not set
980# CONFIG_I2C_PARPORT_LIGHT is not set
981# CONFIG_I2C_PROSAVAGE is not set
982# CONFIG_I2C_SAVAGE4 is not set
983# CONFIG_I2C_SIMTEC is not set
984# CONFIG_I2C_SIS5595 is not set 1009# CONFIG_I2C_SIS5595 is not set
985# CONFIG_I2C_SIS630 is not set 1010# CONFIG_I2C_SIS630 is not set
986# CONFIG_I2C_SIS96X is not set 1011# CONFIG_I2C_SIS96X is not set
987# CONFIG_I2C_TAOS_EVM is not set
988# CONFIG_I2C_STUB is not set
989# CONFIG_I2C_TINY_USB is not set
990# CONFIG_I2C_VIA is not set 1012# CONFIG_I2C_VIA is not set
991# CONFIG_I2C_VIAPRO is not set 1013# CONFIG_I2C_VIAPRO is not set
1014
1015#
1016# I2C system bus drivers (mostly embedded / system-on-chip)
1017#
1018# CONFIG_I2C_OCORES is not set
1019# CONFIG_I2C_SIMTEC is not set
1020
1021#
1022# External I2C/SMBus adapter drivers
1023#
1024# CONFIG_I2C_PARPORT is not set
1025# CONFIG_I2C_PARPORT_LIGHT is not set
1026# CONFIG_I2C_TAOS_EVM is not set
1027# CONFIG_I2C_TINY_USB is not set
1028
1029#
1030# Graphics adapter I2C/DDC channel drivers
1031#
992# CONFIG_I2C_VOODOO3 is not set 1032# CONFIG_I2C_VOODOO3 is not set
1033
1034#
1035# Other I2C/SMBus bus drivers
1036#
993# CONFIG_I2C_PCA_PLATFORM is not set 1037# CONFIG_I2C_PCA_PLATFORM is not set
1038# CONFIG_I2C_STUB is not set
994 1039
995# 1040#
996# Miscellaneous I2C Chip support 1041# Miscellaneous I2C Chip support
997# 1042#
998# CONFIG_DS1682 is not set 1043# CONFIG_DS1682 is not set
1044# CONFIG_AT24 is not set
999# CONFIG_SENSORS_EEPROM is not set 1045# CONFIG_SENSORS_EEPROM is not set
1000# CONFIG_SENSORS_PCF8574 is not set 1046# CONFIG_SENSORS_PCF8574 is not set
1001# CONFIG_PCF8575 is not set 1047# CONFIG_PCF8575 is not set
1048# CONFIG_SENSORS_PCA9539 is not set
1002# CONFIG_SENSORS_PCF8591 is not set 1049# CONFIG_SENSORS_PCF8591 is not set
1003# CONFIG_SENSORS_MAX6875 is not set 1050# CONFIG_SENSORS_MAX6875 is not set
1004# CONFIG_SENSORS_TSL2550 is not set 1051# CONFIG_SENSORS_TSL2550 is not set
@@ -1007,10 +1054,13 @@ CONFIG_I2C_ALGOBIT=y
1007# CONFIG_I2C_DEBUG_BUS is not set 1054# CONFIG_I2C_DEBUG_BUS is not set
1008# CONFIG_I2C_DEBUG_CHIP is not set 1055# CONFIG_I2C_DEBUG_CHIP is not set
1009# CONFIG_SPI is not set 1056# CONFIG_SPI is not set
1057CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
1058# CONFIG_GPIOLIB is not set
1010# CONFIG_W1 is not set 1059# CONFIG_W1 is not set
1011# CONFIG_POWER_SUPPLY is not set 1060# CONFIG_POWER_SUPPLY is not set
1012# CONFIG_HWMON is not set 1061# CONFIG_HWMON is not set
1013# CONFIG_THERMAL is not set 1062# CONFIG_THERMAL is not set
1063# CONFIG_THERMAL_HWMON is not set
1014# CONFIG_WATCHDOG is not set 1064# CONFIG_WATCHDOG is not set
1015 1065
1016# 1066#
@@ -1022,8 +1072,10 @@ CONFIG_SSB_POSSIBLE=y
1022# 1072#
1023# Multifunction device drivers 1073# Multifunction device drivers
1024# 1074#
1075# CONFIG_MFD_CORE is not set
1025# CONFIG_MFD_SM501 is not set 1076# CONFIG_MFD_SM501 is not set
1026# CONFIG_HTC_PASIC3 is not set 1077# CONFIG_HTC_PASIC3 is not set
1078# CONFIG_MFD_TMIO is not set
1027 1079
1028# 1080#
1029# Multimedia devices 1081# Multimedia devices
@@ -1102,10 +1154,13 @@ CONFIG_FB_RADEON_BACKLIGHT=y
1102# CONFIG_FB_TRIDENT is not set 1154# CONFIG_FB_TRIDENT is not set
1103# CONFIG_FB_ARK is not set 1155# CONFIG_FB_ARK is not set
1104# CONFIG_FB_PM3 is not set 1156# CONFIG_FB_PM3 is not set
1157# CONFIG_FB_CARMINE is not set
1105CONFIG_FB_IBM_GXT4500=y 1158CONFIG_FB_IBM_GXT4500=y
1106# CONFIG_FB_VIRTUAL is not set 1159# CONFIG_FB_VIRTUAL is not set
1107CONFIG_BACKLIGHT_LCD_SUPPORT=y 1160CONFIG_BACKLIGHT_LCD_SUPPORT=y
1108CONFIG_LCD_CLASS_DEVICE=m 1161CONFIG_LCD_CLASS_DEVICE=m
1162# CONFIG_LCD_ILI9320 is not set
1163CONFIG_LCD_PLATFORM=m
1109CONFIG_BACKLIGHT_CLASS_DEVICE=y 1164CONFIG_BACKLIGHT_CLASS_DEVICE=y
1110# CONFIG_BACKLIGHT_CORGI is not set 1165# CONFIG_BACKLIGHT_CORGI is not set
1111 1166
@@ -1133,10 +1188,6 @@ CONFIG_LOGO=y
1133CONFIG_LOGO_LINUX_MONO=y 1188CONFIG_LOGO_LINUX_MONO=y
1134CONFIG_LOGO_LINUX_VGA16=y 1189CONFIG_LOGO_LINUX_VGA16=y
1135CONFIG_LOGO_LINUX_CLUT224=y 1190CONFIG_LOGO_LINUX_CLUT224=y
1136
1137#
1138# Sound
1139#
1140# CONFIG_SOUND is not set 1191# CONFIG_SOUND is not set
1141CONFIG_HID_SUPPORT=y 1192CONFIG_HID_SUPPORT=y
1142CONFIG_HID=y 1193CONFIG_HID=y
@@ -1165,6 +1216,7 @@ CONFIG_USB_DEVICEFS=y
1165CONFIG_USB_DEVICE_CLASS=y 1216CONFIG_USB_DEVICE_CLASS=y
1166# CONFIG_USB_DYNAMIC_MINORS is not set 1217# CONFIG_USB_DYNAMIC_MINORS is not set
1167# CONFIG_USB_OTG is not set 1218# CONFIG_USB_OTG is not set
1219CONFIG_USB_MON=y
1168 1220
1169# 1221#
1170# USB Host Controller Drivers 1222# USB Host Controller Drivers
@@ -1190,6 +1242,7 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y
1190# 1242#
1191# CONFIG_USB_ACM is not set 1243# CONFIG_USB_ACM is not set
1192# CONFIG_USB_PRINTER is not set 1244# CONFIG_USB_PRINTER is not set
1245# CONFIG_USB_WDM is not set
1193 1246
1194# 1247#
1195# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 1248# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
@@ -1211,6 +1264,7 @@ CONFIG_USB_STORAGE=y
1211# CONFIG_USB_STORAGE_ALAUDA is not set 1264# CONFIG_USB_STORAGE_ALAUDA is not set
1212CONFIG_USB_STORAGE_ONETOUCH=y 1265CONFIG_USB_STORAGE_ONETOUCH=y
1213# CONFIG_USB_STORAGE_KARMA is not set 1266# CONFIG_USB_STORAGE_KARMA is not set
1267# CONFIG_USB_STORAGE_SIERRA is not set
1214# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set 1268# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
1215# CONFIG_USB_LIBUSUAL is not set 1269# CONFIG_USB_LIBUSUAL is not set
1216 1270
@@ -1219,7 +1273,6 @@ CONFIG_USB_STORAGE_ONETOUCH=y
1219# 1273#
1220# CONFIG_USB_MDC800 is not set 1274# CONFIG_USB_MDC800 is not set
1221# CONFIG_USB_MICROTEK is not set 1275# CONFIG_USB_MICROTEK is not set
1222CONFIG_USB_MON=y
1223 1276
1224# 1277#
1225# USB port drivers 1278# USB port drivers
@@ -1233,7 +1286,6 @@ CONFIG_USB_MON=y
1233# CONFIG_USB_EMI62 is not set 1286# CONFIG_USB_EMI62 is not set
1234# CONFIG_USB_EMI26 is not set 1287# CONFIG_USB_EMI26 is not set
1235# CONFIG_USB_ADUTUX is not set 1288# CONFIG_USB_ADUTUX is not set
1236# CONFIG_USB_AUERSWALD is not set
1237# CONFIG_USB_RIO500 is not set 1289# CONFIG_USB_RIO500 is not set
1238# CONFIG_USB_LEGOTOWER is not set 1290# CONFIG_USB_LEGOTOWER is not set
1239# CONFIG_USB_LCD is not set 1291# CONFIG_USB_LCD is not set
@@ -1250,6 +1302,7 @@ CONFIG_USB_MON=y
1250# CONFIG_USB_TRANCEVIBRATOR is not set 1302# CONFIG_USB_TRANCEVIBRATOR is not set
1251# CONFIG_USB_IOWARRIOR is not set 1303# CONFIG_USB_IOWARRIOR is not set
1252# CONFIG_USB_TEST is not set 1304# CONFIG_USB_TEST is not set
1305# CONFIG_USB_ISIGHTFW is not set
1253# CONFIG_USB_GADGET is not set 1306# CONFIG_USB_GADGET is not set
1254# CONFIG_MMC is not set 1307# CONFIG_MMC is not set
1255# CONFIG_MEMSTICK is not set 1308# CONFIG_MEMSTICK is not set
@@ -1316,6 +1369,7 @@ CONFIG_XFS_POSIX_ACL=y
1316# CONFIG_GFS2_FS is not set 1369# CONFIG_GFS2_FS is not set
1317CONFIG_OCFS2_FS=m 1370CONFIG_OCFS2_FS=m
1318CONFIG_OCFS2_FS_O2CB=m 1371CONFIG_OCFS2_FS_O2CB=m
1372CONFIG_OCFS2_FS_STATS=y
1319CONFIG_OCFS2_DEBUG_MASKLOG=y 1373CONFIG_OCFS2_DEBUG_MASKLOG=y
1320# CONFIG_OCFS2_DEBUG_FS is not set 1374# CONFIG_OCFS2_DEBUG_FS is not set
1321CONFIG_DNOTIFY=y 1375CONFIG_DNOTIFY=y
@@ -1371,6 +1425,7 @@ CONFIG_CONFIGFS_FS=m
1371CONFIG_CRAMFS=y 1425CONFIG_CRAMFS=y
1372# CONFIG_VXFS_FS is not set 1426# CONFIG_VXFS_FS is not set
1373# CONFIG_MINIX_FS is not set 1427# CONFIG_MINIX_FS is not set
1428# CONFIG_OMFS_FS is not set
1374# CONFIG_HPFS_FS is not set 1429# CONFIG_HPFS_FS is not set
1375# CONFIG_QNX4FS_FS is not set 1430# CONFIG_QNX4FS_FS is not set
1376# CONFIG_ROMFS_FS is not set 1431# CONFIG_ROMFS_FS is not set
@@ -1394,7 +1449,6 @@ CONFIG_NFS_COMMON=y
1394CONFIG_SUNRPC=y 1449CONFIG_SUNRPC=y
1395CONFIG_SUNRPC_GSS=y 1450CONFIG_SUNRPC_GSS=y
1396CONFIG_SUNRPC_XPRT_RDMA=m 1451CONFIG_SUNRPC_XPRT_RDMA=m
1397# CONFIG_SUNRPC_BIND34 is not set
1398CONFIG_RPCSEC_GSS_KRB5=y 1452CONFIG_RPCSEC_GSS_KRB5=y
1399CONFIG_RPCSEC_GSS_SPKM3=m 1453CONFIG_RPCSEC_GSS_SPKM3=m
1400# CONFIG_SMB_FS is not set 1454# CONFIG_SMB_FS is not set
@@ -1463,6 +1517,7 @@ CONFIG_BITREVERSE=y
1463# CONFIG_GENERIC_FIND_FIRST_BIT is not set 1517# CONFIG_GENERIC_FIND_FIRST_BIT is not set
1464CONFIG_CRC_CCITT=m 1518CONFIG_CRC_CCITT=m
1465# CONFIG_CRC16 is not set 1519# CONFIG_CRC16 is not set
1520CONFIG_CRC_T10DIF=y
1466CONFIG_CRC_ITU_T=m 1521CONFIG_CRC_ITU_T=m
1467CONFIG_CRC32=y 1522CONFIG_CRC32=y
1468# CONFIG_CRC7 is not set 1523# CONFIG_CRC7 is not set
@@ -1495,8 +1550,10 @@ CONFIG_DEBUG_FS=y
1495CONFIG_DEBUG_KERNEL=y 1550CONFIG_DEBUG_KERNEL=y
1496# CONFIG_DEBUG_SHIRQ is not set 1551# CONFIG_DEBUG_SHIRQ is not set
1497CONFIG_DETECT_SOFTLOCKUP=y 1552CONFIG_DETECT_SOFTLOCKUP=y
1553# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
1554CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
1498CONFIG_SCHED_DEBUG=y 1555CONFIG_SCHED_DEBUG=y
1499# CONFIG_SCHEDSTATS is not set 1556CONFIG_SCHEDSTATS=y
1500# CONFIG_TIMER_STATS is not set 1557# CONFIG_TIMER_STATS is not set
1501# CONFIG_DEBUG_OBJECTS is not set 1558# CONFIG_DEBUG_OBJECTS is not set
1502# CONFIG_SLUB_DEBUG_ON is not set 1559# CONFIG_SLUB_DEBUG_ON is not set
@@ -1508,30 +1565,49 @@ CONFIG_SCHED_DEBUG=y
1508# CONFIG_DEBUG_LOCK_ALLOC is not set 1565# CONFIG_DEBUG_LOCK_ALLOC is not set
1509# CONFIG_PROVE_LOCKING is not set 1566# CONFIG_PROVE_LOCKING is not set
1510# CONFIG_LOCK_STAT is not set 1567# CONFIG_LOCK_STAT is not set
1568CONFIG_TRACE_IRQFLAGS=y
1511# CONFIG_DEBUG_SPINLOCK_SLEEP is not set 1569# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1512# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set 1570# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1571CONFIG_STACKTRACE=y
1513# CONFIG_DEBUG_KOBJECT is not set 1572# CONFIG_DEBUG_KOBJECT is not set
1514CONFIG_DEBUG_BUGVERBOSE=y 1573CONFIG_DEBUG_BUGVERBOSE=y
1515# CONFIG_DEBUG_INFO is not set 1574# CONFIG_DEBUG_INFO is not set
1516# CONFIG_DEBUG_VM is not set 1575# CONFIG_DEBUG_VM is not set
1517# CONFIG_DEBUG_WRITECOUNT is not set 1576# CONFIG_DEBUG_WRITECOUNT is not set
1577CONFIG_DEBUG_MEMORY_INIT=y
1518# CONFIG_DEBUG_LIST is not set 1578# CONFIG_DEBUG_LIST is not set
1519# CONFIG_DEBUG_SG is not set 1579# CONFIG_DEBUG_SG is not set
1580CONFIG_FRAME_POINTER=y
1520# CONFIG_BOOT_PRINTK_DELAY is not set 1581# CONFIG_BOOT_PRINTK_DELAY is not set
1521# CONFIG_RCU_TORTURE_TEST is not set 1582# CONFIG_RCU_TORTURE_TEST is not set
1522# CONFIG_KPROBES_SANITY_TEST is not set 1583# CONFIG_KPROBES_SANITY_TEST is not set
1523# CONFIG_BACKTRACE_SELF_TEST is not set 1584# CONFIG_BACKTRACE_SELF_TEST is not set
1524# CONFIG_LKDTM is not set 1585# CONFIG_LKDTM is not set
1525# CONFIG_FAULT_INJECTION is not set 1586# CONFIG_FAULT_INJECTION is not set
1587CONFIG_LATENCYTOP=y
1588CONFIG_SYSCTL_SYSCALL_CHECK=y
1589CONFIG_HAVE_FTRACE=y
1590CONFIG_HAVE_DYNAMIC_FTRACE=y
1591CONFIG_TRACER_MAX_TRACE=y
1592CONFIG_TRACING=y
1593# CONFIG_FTRACE is not set
1594CONFIG_IRQSOFF_TRACER=y
1595CONFIG_SCHED_TRACER=y
1596CONFIG_CONTEXT_SWITCH_TRACER=y
1597# CONFIG_FTRACE_STARTUP_TEST is not set
1526# CONFIG_SAMPLES is not set 1598# CONFIG_SAMPLES is not set
1599CONFIG_HAVE_ARCH_KGDB=y
1600# CONFIG_KGDB is not set
1527CONFIG_DEBUG_STACKOVERFLOW=y 1601CONFIG_DEBUG_STACKOVERFLOW=y
1528# CONFIG_DEBUG_STACK_USAGE is not set 1602# CONFIG_DEBUG_STACK_USAGE is not set
1529# CONFIG_DEBUG_PAGEALLOC is not set 1603# CONFIG_DEBUG_PAGEALLOC is not set
1530CONFIG_HCALL_STATS=y 1604CONFIG_HCALL_STATS=y
1531CONFIG_DEBUGGER=y 1605# CONFIG_CODE_PATCHING_SELFTEST is not set
1606# CONFIG_FTR_FIXUP_SELFTEST is not set
1532CONFIG_XMON=y 1607CONFIG_XMON=y
1533CONFIG_XMON_DEFAULT=y 1608CONFIG_XMON_DEFAULT=y
1534CONFIG_XMON_DISASSEMBLY=y 1609CONFIG_XMON_DISASSEMBLY=y
1610CONFIG_DEBUGGER=y
1535CONFIG_IRQSTACKS=y 1611CONFIG_IRQSTACKS=y
1536CONFIG_VIRQ_DEBUG=y 1612CONFIG_VIRQ_DEBUG=y
1537# CONFIG_BOOTX_TEXT is not set 1613# CONFIG_BOOTX_TEXT is not set
@@ -1590,6 +1666,10 @@ CONFIG_CRYPTO_CRC32C=m
1590CONFIG_CRYPTO_MD4=m 1666CONFIG_CRYPTO_MD4=m
1591CONFIG_CRYPTO_MD5=y 1667CONFIG_CRYPTO_MD5=y
1592CONFIG_CRYPTO_MICHAEL_MIC=m 1668CONFIG_CRYPTO_MICHAEL_MIC=m
1669# CONFIG_CRYPTO_RMD128 is not set
1670# CONFIG_CRYPTO_RMD160 is not set
1671# CONFIG_CRYPTO_RMD256 is not set
1672# CONFIG_CRYPTO_RMD320 is not set
1593CONFIG_CRYPTO_SHA1=m 1673CONFIG_CRYPTO_SHA1=m
1594CONFIG_CRYPTO_SHA256=m 1674CONFIG_CRYPTO_SHA256=m
1595CONFIG_CRYPTO_SHA512=m 1675CONFIG_CRYPTO_SHA512=m
diff --git a/arch/powerpc/configs/sbc8641d_defconfig b/arch/powerpc/configs/sbc8641d_defconfig
index 8227510b41a9..f545421f9857 100644
--- a/arch/powerpc/configs/sbc8641d_defconfig
+++ b/arch/powerpc/configs/sbc8641d_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc5 3# Linux kernel version: 2.6.27-rc4
4# Mon Jun 9 08:52:19 2008 4# Thu Aug 21 00:52:15 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -33,6 +33,7 @@ CONFIG_GENERIC_HARDIRQS=y
33# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set 33# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
34CONFIG_IRQ_PER_CPU=y 34CONFIG_IRQ_PER_CPU=y
35CONFIG_STACKTRACE_SUPPORT=y 35CONFIG_STACKTRACE_SUPPORT=y
36CONFIG_HAVE_LATENCYTOP_SUPPORT=y
36CONFIG_LOCKDEP_SUPPORT=y 37CONFIG_LOCKDEP_SUPPORT=y
37CONFIG_RWSEM_XCHGADD_ALGORITHM=y 38CONFIG_RWSEM_XCHGADD_ALGORITHM=y
38CONFIG_GENERIC_LOCKBREAK=y 39CONFIG_GENERIC_LOCKBREAK=y
@@ -92,7 +93,6 @@ CONFIG_INITRAMFS_SOURCE=""
92CONFIG_SYSCTL=y 93CONFIG_SYSCTL=y
93CONFIG_EMBEDDED=y 94CONFIG_EMBEDDED=y
94CONFIG_SYSCTL_SYSCALL=y 95CONFIG_SYSCTL_SYSCALL=y
95CONFIG_SYSCTL_SYSCALL_CHECK=y
96CONFIG_KALLSYMS=y 96CONFIG_KALLSYMS=y
97# CONFIG_KALLSYMS_ALL is not set 97# CONFIG_KALLSYMS_ALL is not set
98# CONFIG_KALLSYMS_EXTRA_PASS is not set 98# CONFIG_KALLSYMS_EXTRA_PASS is not set
@@ -100,6 +100,7 @@ CONFIG_HOTPLUG=y
100CONFIG_PRINTK=y 100CONFIG_PRINTK=y
101CONFIG_BUG=y 101CONFIG_BUG=y
102CONFIG_ELF_CORE=y 102CONFIG_ELF_CORE=y
103CONFIG_PCSPKR_PLATFORM=y
103CONFIG_COMPAT_BRK=y 104CONFIG_COMPAT_BRK=y
104CONFIG_BASE_FULL=y 105CONFIG_BASE_FULL=y
105CONFIG_FUTEX=y 106CONFIG_FUTEX=y
@@ -117,10 +118,16 @@ CONFIG_SLAB=y
117# CONFIG_MARKERS is not set 118# CONFIG_MARKERS is not set
118CONFIG_HAVE_OPROFILE=y 119CONFIG_HAVE_OPROFILE=y
119# CONFIG_KPROBES is not set 120# CONFIG_KPROBES is not set
121CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
122CONFIG_HAVE_IOREMAP_PROT=y
120CONFIG_HAVE_KPROBES=y 123CONFIG_HAVE_KPROBES=y
121CONFIG_HAVE_KRETPROBES=y 124CONFIG_HAVE_KRETPROBES=y
125CONFIG_HAVE_ARCH_TRACEHOOK=y
122# CONFIG_HAVE_DMA_ATTRS is not set 126# CONFIG_HAVE_DMA_ATTRS is not set
127CONFIG_USE_GENERIC_SMP_HELPERS=y
128# CONFIG_HAVE_CLK is not set
123CONFIG_PROC_PAGE_MONITOR=y 129CONFIG_PROC_PAGE_MONITOR=y
130# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
124CONFIG_SLABINFO=y 131CONFIG_SLABINFO=y
125CONFIG_RT_MUTEXES=y 132CONFIG_RT_MUTEXES=y
126# CONFIG_TINY_SHMEM is not set 133# CONFIG_TINY_SHMEM is not set
@@ -138,6 +145,7 @@ CONFIG_BLOCK=y
138# CONFIG_BLK_DEV_IO_TRACE is not set 145# CONFIG_BLK_DEV_IO_TRACE is not set
139# CONFIG_LSF is not set 146# CONFIG_LSF is not set
140# CONFIG_BLK_DEV_BSG is not set 147# CONFIG_BLK_DEV_BSG is not set
148# CONFIG_BLK_DEV_INTEGRITY is not set
141 149
142# 150#
143# IO Schedulers 151# IO Schedulers
@@ -156,30 +164,40 @@ CONFIG_CLASSIC_RCU=y
156# 164#
157# Platform support 165# Platform support
158# 166#
159# CONFIG_PPC_MULTIPLATFORM is not set 167CONFIG_PPC_MULTIPLATFORM=y
160# CONFIG_PPC_82xx is not set 168CONFIG_CLASSIC32=y
161# CONFIG_PPC_83xx is not set 169CONFIG_PPC_CHRP=y
162CONFIG_PPC_86xx=y 170# CONFIG_MPC5121_ADS is not set
163# CONFIG_PPC_MPC512x is not set 171# CONFIG_MPC5121_GENERIC is not set
164# CONFIG_PPC_MPC5121 is not set 172# CONFIG_PPC_MPC52xx is not set
173CONFIG_PPC_PMAC=y
165# CONFIG_PPC_CELL is not set 174# CONFIG_PPC_CELL is not set
166# CONFIG_PPC_CELL_NATIVE is not set 175# CONFIG_PPC_CELL_NATIVE is not set
176# CONFIG_PPC_82xx is not set
167# CONFIG_PQ2ADS is not set 177# CONFIG_PQ2ADS is not set
178# CONFIG_PPC_83xx is not set
179CONFIG_PPC_86xx=y
168# CONFIG_MPC8641_HPCN is not set 180# CONFIG_MPC8641_HPCN is not set
169CONFIG_SBC8641D=y 181CONFIG_SBC8641D=y
170# CONFIG_MPC8610_HPCD is not set 182# CONFIG_MPC8610_HPCD is not set
171CONFIG_MPC8641=y 183CONFIG_MPC8641=y
184CONFIG_PPC_NATIVE=y
185# CONFIG_UDBG_RTAS_CONSOLE is not set
172# CONFIG_IPIC is not set 186# CONFIG_IPIC is not set
173CONFIG_MPIC=y 187CONFIG_MPIC=y
174# CONFIG_MPIC_WEIRD is not set 188# CONFIG_MPIC_WEIRD is not set
175# CONFIG_PPC_I8259 is not set 189CONFIG_PPC_I8259=y
176# CONFIG_PPC_RTAS is not set 190CONFIG_PPC_RTAS=y
191# CONFIG_RTAS_ERROR_LOGGING is not set
192CONFIG_RTAS_PROC=y
177# CONFIG_MMIO_NVRAM is not set 193# CONFIG_MMIO_NVRAM is not set
178# CONFIG_PPC_MPC106 is not set 194CONFIG_PPC_MPC106=y
179# CONFIG_PPC_970_NAP is not set 195# CONFIG_PPC_970_NAP is not set
180# CONFIG_PPC_INDIRECT_IO is not set 196# CONFIG_PPC_INDIRECT_IO is not set
181# CONFIG_GENERIC_IOMAP is not set 197# CONFIG_GENERIC_IOMAP is not set
182# CONFIG_CPU_FREQ is not set 198# CONFIG_CPU_FREQ is not set
199# CONFIG_PPC601_SYNC_FIX is not set
200# CONFIG_TAU is not set
183# CONFIG_FSL_ULI1575 is not set 201# CONFIG_FSL_ULI1575 is not set
184 202
185# 203#
@@ -195,7 +213,7 @@ CONFIG_HZ_250=y
195# CONFIG_HZ_300 is not set 213# CONFIG_HZ_300 is not set
196# CONFIG_HZ_1000 is not set 214# CONFIG_HZ_1000 is not set
197CONFIG_HZ=250 215CONFIG_HZ=250
198# CONFIG_SCHED_HRTICK is not set 216CONFIG_SCHED_HRTICK=y
199# CONFIG_PREEMPT_NONE is not set 217# CONFIG_PREEMPT_NONE is not set
200# CONFIG_PREEMPT_VOLUNTARY is not set 218# CONFIG_PREEMPT_VOLUNTARY is not set
201CONFIG_PREEMPT=y 219CONFIG_PREEMPT=y
@@ -203,9 +221,11 @@ CONFIG_PREEMPT=y
203CONFIG_BINFMT_ELF=y 221CONFIG_BINFMT_ELF=y
204CONFIG_BINFMT_MISC=m 222CONFIG_BINFMT_MISC=m
205# CONFIG_IOMMU_HELPER is not set 223# CONFIG_IOMMU_HELPER is not set
224# CONFIG_HOTPLUG_CPU is not set
206CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y 225CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
207CONFIG_ARCH_HAS_WALK_MEMORY=y 226CONFIG_ARCH_HAS_WALK_MEMORY=y
208CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y 227CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
228# CONFIG_KEXEC is not set
209CONFIG_IRQ_ALL_CPUS=y 229CONFIG_IRQ_ALL_CPUS=y
210CONFIG_ARCH_FLATMEM_ENABLE=y 230CONFIG_ARCH_FLATMEM_ENABLE=y
211CONFIG_ARCH_POPULATES_NODE_MAP=y 231CONFIG_ARCH_POPULATES_NODE_MAP=y
@@ -219,6 +239,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
219# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set 239# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
220CONFIG_PAGEFLAGS_EXTENDED=y 240CONFIG_PAGEFLAGS_EXTENDED=y
221CONFIG_SPLIT_PTLOCK_CPUS=4 241CONFIG_SPLIT_PTLOCK_CPUS=4
242CONFIG_MIGRATION=y
222# CONFIG_RESOURCES_64BIT is not set 243# CONFIG_RESOURCES_64BIT is not set
223CONFIG_ZONE_DMA_FLAG=1 244CONFIG_ZONE_DMA_FLAG=1
224CONFIG_BOUNCE=y 245CONFIG_BOUNCE=y
@@ -226,6 +247,7 @@ CONFIG_VIRT_TO_BUS=y
226CONFIG_FORCE_MAX_ZONEORDER=11 247CONFIG_FORCE_MAX_ZONEORDER=11
227# CONFIG_PROC_DEVICETREE is not set 248# CONFIG_PROC_DEVICETREE is not set
228# CONFIG_CMDLINE_BOOL is not set 249# CONFIG_CMDLINE_BOOL is not set
250CONFIG_EXTRA_TARGETS=""
229# CONFIG_PM is not set 251# CONFIG_PM is not set
230CONFIG_SECCOMP=y 252CONFIG_SECCOMP=y
231CONFIG_ISA_DMA_API=y 253CONFIG_ISA_DMA_API=y
@@ -233,11 +255,13 @@ CONFIG_ISA_DMA_API=y
233# 255#
234# Bus options 256# Bus options
235# 257#
258# CONFIG_ISA is not set
236CONFIG_ZONE_DMA=y 259CONFIG_ZONE_DMA=y
237CONFIG_GENERIC_ISA_DMA=y 260CONFIG_GENERIC_ISA_DMA=y
238CONFIG_PPC_INDIRECT_PCI=y 261CONFIG_PPC_INDIRECT_PCI=y
239CONFIG_FSL_SOC=y 262CONFIG_FSL_SOC=y
240CONFIG_FSL_PCI=y 263CONFIG_FSL_PCI=y
264CONFIG_PPC_PCI_CHOICE=y
241CONFIG_PCI=y 265CONFIG_PCI=y
242CONFIG_PCI_DOMAINS=y 266CONFIG_PCI_DOMAINS=y
243CONFIG_PCI_SYSCALL=y 267CONFIG_PCI_SYSCALL=y
@@ -265,10 +289,6 @@ CONFIG_PAGE_OFFSET=0xc0000000
265CONFIG_KERNEL_START=0xc0000000 289CONFIG_KERNEL_START=0xc0000000
266CONFIG_PHYSICAL_START=0x00000000 290CONFIG_PHYSICAL_START=0x00000000
267CONFIG_TASK_SIZE=0xc0000000 291CONFIG_TASK_SIZE=0xc0000000
268
269#
270# Networking
271#
272CONFIG_NET=y 292CONFIG_NET=y
273 293
274# 294#
@@ -282,6 +302,7 @@ CONFIG_XFRM_USER=m
282# CONFIG_XFRM_SUB_POLICY is not set 302# CONFIG_XFRM_SUB_POLICY is not set
283# CONFIG_XFRM_MIGRATE is not set 303# CONFIG_XFRM_MIGRATE is not set
284# CONFIG_XFRM_STATISTICS is not set 304# CONFIG_XFRM_STATISTICS is not set
305CONFIG_XFRM_IPCOMP=m
285CONFIG_NET_KEY=m 306CONFIG_NET_KEY=m
286# CONFIG_NET_KEY_MIGRATE is not set 307# CONFIG_NET_KEY_MIGRATE is not set
287CONFIG_INET=y 308CONFIG_INET=y
@@ -406,6 +427,7 @@ CONFIG_IP_NF_MANGLE=m
406CONFIG_IP_NF_TARGET_ECN=m 427CONFIG_IP_NF_TARGET_ECN=m
407# CONFIG_IP_NF_TARGET_TTL is not set 428# CONFIG_IP_NF_TARGET_TTL is not set
408CONFIG_IP_NF_RAW=m 429CONFIG_IP_NF_RAW=m
430# CONFIG_IP_NF_SECURITY is not set
409CONFIG_IP_NF_ARPTABLES=m 431CONFIG_IP_NF_ARPTABLES=m
410CONFIG_IP_NF_ARPFILTER=m 432CONFIG_IP_NF_ARPFILTER=m
411CONFIG_IP_NF_ARP_MANGLE=m 433CONFIG_IP_NF_ARP_MANGLE=m
@@ -429,6 +451,7 @@ CONFIG_IP6_NF_TARGET_LOG=m
429CONFIG_IP6_NF_MANGLE=m 451CONFIG_IP6_NF_MANGLE=m
430# CONFIG_IP6_NF_TARGET_HL is not set 452# CONFIG_IP6_NF_TARGET_HL is not set
431CONFIG_IP6_NF_RAW=m 453CONFIG_IP6_NF_RAW=m
454# CONFIG_IP6_NF_SECURITY is not set
432 455
433# 456#
434# Bridge: Netfilter Configuration 457# Bridge: Netfilter Configuration
@@ -451,8 +474,10 @@ CONFIG_ATM_LANE=m
451CONFIG_ATM_MPOA=m 474CONFIG_ATM_MPOA=m
452CONFIG_ATM_BR2684=m 475CONFIG_ATM_BR2684=m
453# CONFIG_ATM_BR2684_IPFILTER is not set 476# CONFIG_ATM_BR2684_IPFILTER is not set
477CONFIG_STP=m
454CONFIG_BRIDGE=m 478CONFIG_BRIDGE=m
455CONFIG_VLAN_8021Q=m 479CONFIG_VLAN_8021Q=m
480# CONFIG_VLAN_8021Q_GVRP is not set
456# CONFIG_DECNET is not set 481# CONFIG_DECNET is not set
457CONFIG_LLC=m 482CONFIG_LLC=m
458# CONFIG_LLC2 is not set 483# CONFIG_LLC2 is not set
@@ -472,7 +497,6 @@ CONFIG_NET_SCH_HTB=m
472CONFIG_NET_SCH_HFSC=m 497CONFIG_NET_SCH_HFSC=m
473CONFIG_NET_SCH_ATM=m 498CONFIG_NET_SCH_ATM=m
474CONFIG_NET_SCH_PRIO=m 499CONFIG_NET_SCH_PRIO=m
475# CONFIG_NET_SCH_RR is not set
476CONFIG_NET_SCH_RED=m 500CONFIG_NET_SCH_RED=m
477CONFIG_NET_SCH_SFQ=m 501CONFIG_NET_SCH_SFQ=m
478CONFIG_NET_SCH_TEQL=m 502CONFIG_NET_SCH_TEQL=m
@@ -625,6 +649,7 @@ CONFIG_OF_I2C=y
625# CONFIG_PARPORT is not set 649# CONFIG_PARPORT is not set
626CONFIG_BLK_DEV=y 650CONFIG_BLK_DEV=y
627# CONFIG_BLK_DEV_FD is not set 651# CONFIG_BLK_DEV_FD is not set
652# CONFIG_MAC_FLOPPY is not set
628# CONFIG_BLK_CPQ_DA is not set 653# CONFIG_BLK_CPQ_DA is not set
629# CONFIG_BLK_CPQ_CISS_DA is not set 654# CONFIG_BLK_CPQ_CISS_DA is not set
630# CONFIG_BLK_DEV_DAC960 is not set 655# CONFIG_BLK_DEV_DAC960 is not set
@@ -640,12 +665,14 @@ CONFIG_BLK_DEV_RAM_SIZE=4096
640# CONFIG_BLK_DEV_XIP is not set 665# CONFIG_BLK_DEV_XIP is not set
641# CONFIG_CDROM_PKTCDVD is not set 666# CONFIG_CDROM_PKTCDVD is not set
642# CONFIG_ATA_OVER_ETH is not set 667# CONFIG_ATA_OVER_ETH is not set
668# CONFIG_BLK_DEV_HD is not set
643CONFIG_MISC_DEVICES=y 669CONFIG_MISC_DEVICES=y
644# CONFIG_PHANTOM is not set 670# CONFIG_PHANTOM is not set
645# CONFIG_EEPROM_93CX6 is not set 671# CONFIG_EEPROM_93CX6 is not set
646# CONFIG_SGI_IOC4 is not set 672# CONFIG_SGI_IOC4 is not set
647# CONFIG_TIFM_CORE is not set 673# CONFIG_TIFM_CORE is not set
648# CONFIG_ENCLOSURE_SERVICES is not set 674# CONFIG_ENCLOSURE_SERVICES is not set
675# CONFIG_HP_ILO is not set
649CONFIG_HAVE_IDE=y 676CONFIG_HAVE_IDE=y
650# CONFIG_IDE is not set 677# CONFIG_IDE is not set
651 678
@@ -680,12 +707,15 @@ CONFIG_DM_ZERO=y
680# 707#
681# IEEE 1394 (FireWire) support 708# IEEE 1394 (FireWire) support
682# 709#
710
711#
712# Enable only one of the two stacks, unless you know what you are doing
713#
683# CONFIG_FIREWIRE is not set 714# CONFIG_FIREWIRE is not set
684# CONFIG_IEEE1394 is not set 715# CONFIG_IEEE1394 is not set
685# CONFIG_I2O is not set 716# CONFIG_I2O is not set
686# CONFIG_MACINTOSH_DRIVERS is not set 717# CONFIG_MACINTOSH_DRIVERS is not set
687CONFIG_NETDEVICES=y 718CONFIG_NETDEVICES=y
688# CONFIG_NETDEVICES_MULTIQUEUE is not set
689CONFIG_DUMMY=m 719CONFIG_DUMMY=m
690CONFIG_BONDING=m 720CONFIG_BONDING=m
691# CONFIG_MACVLAN is not set 721# CONFIG_MACVLAN is not set
@@ -712,6 +742,8 @@ CONFIG_BROADCOM_PHY=y
712# CONFIG_MDIO_BITBANG is not set 742# CONFIG_MDIO_BITBANG is not set
713CONFIG_NET_ETHERNET=y 743CONFIG_NET_ETHERNET=y
714CONFIG_MII=y 744CONFIG_MII=y
745# CONFIG_MACE is not set
746# CONFIG_BMAC is not set
715# CONFIG_HAPPYMEAL is not set 747# CONFIG_HAPPYMEAL is not set
716# CONFIG_SUNGEM is not set 748# CONFIG_SUNGEM is not set
717# CONFIG_CASSINI is not set 749# CONFIG_CASSINI is not set
@@ -729,7 +761,6 @@ CONFIG_NETDEV_1000=y
729# CONFIG_DL2K is not set 761# CONFIG_DL2K is not set
730# CONFIG_E1000 is not set 762# CONFIG_E1000 is not set
731# CONFIG_E1000E is not set 763# CONFIG_E1000E is not set
732# CONFIG_E1000E_ENABLED is not set
733# CONFIG_IP1000 is not set 764# CONFIG_IP1000 is not set
734# CONFIG_IGB is not set 765# CONFIG_IGB is not set
735# CONFIG_NS83820 is not set 766# CONFIG_NS83820 is not set
@@ -743,9 +774,10 @@ CONFIG_NETDEV_1000=y
743# CONFIG_TIGON3 is not set 774# CONFIG_TIGON3 is not set
744# CONFIG_BNX2 is not set 775# CONFIG_BNX2 is not set
745CONFIG_GIANFAR=y 776CONFIG_GIANFAR=y
746# CONFIG_GFAR_NAPI is not set 777# CONFIG_MV643XX_ETH is not set
747# CONFIG_QLA3XXX is not set 778# CONFIG_QLA3XXX is not set
748# CONFIG_ATL1 is not set 779# CONFIG_ATL1 is not set
780# CONFIG_ATL1E is not set
749# CONFIG_NETDEV_10000 is not set 781# CONFIG_NETDEV_10000 is not set
750# CONFIG_TR is not set 782# CONFIG_TR is not set
751 783
@@ -768,7 +800,7 @@ CONFIG_ATM_DRIVERS=y
768# CONFIG_ATM_AMBASSADOR is not set 800# CONFIG_ATM_AMBASSADOR is not set
769# CONFIG_ATM_HORIZON is not set 801# CONFIG_ATM_HORIZON is not set
770# CONFIG_ATM_IA is not set 802# CONFIG_ATM_IA is not set
771# CONFIG_ATM_FORE200E_MAYBE is not set 803# CONFIG_ATM_FORE200E is not set
772# CONFIG_ATM_HE is not set 804# CONFIG_ATM_HE is not set
773# CONFIG_FDDI is not set 805# CONFIG_FDDI is not set
774# CONFIG_HIPPI is not set 806# CONFIG_HIPPI is not set
@@ -834,6 +866,7 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
834# Character devices 866# Character devices
835# 867#
836CONFIG_VT=y 868CONFIG_VT=y
869CONFIG_CONSOLE_TRANSLATIONS=y
837CONFIG_VT_CONSOLE=y 870CONFIG_VT_CONSOLE=y
838CONFIG_HW_CONSOLE=y 871CONFIG_HW_CONSOLE=y
839# CONFIG_VT_HW_CONSOLE_BINDING is not set 872# CONFIG_VT_HW_CONSOLE_BINDING is not set
@@ -857,11 +890,14 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=2
857# CONFIG_SERIAL_UARTLITE is not set 890# CONFIG_SERIAL_UARTLITE is not set
858CONFIG_SERIAL_CORE=y 891CONFIG_SERIAL_CORE=y
859CONFIG_SERIAL_CORE_CONSOLE=y 892CONFIG_SERIAL_CORE_CONSOLE=y
893# CONFIG_SERIAL_PMACZILOG is not set
860# CONFIG_SERIAL_JSM is not set 894# CONFIG_SERIAL_JSM is not set
861# CONFIG_SERIAL_OF_PLATFORM is not set 895# CONFIG_SERIAL_OF_PLATFORM is not set
862CONFIG_UNIX98_PTYS=y 896CONFIG_UNIX98_PTYS=y
863CONFIG_LEGACY_PTYS=y 897CONFIG_LEGACY_PTYS=y
864CONFIG_LEGACY_PTY_COUNT=256 898CONFIG_LEGACY_PTY_COUNT=256
899# CONFIG_BRIQ_PANEL is not set
900# CONFIG_HVC_RTAS is not set
865# CONFIG_IPMI_HANDLER is not set 901# CONFIG_IPMI_HANDLER is not set
866CONFIG_HW_RANDOM=m 902CONFIG_HW_RANDOM=m
867# CONFIG_NVRAM is not set 903# CONFIG_NVRAM is not set
@@ -874,42 +910,69 @@ CONFIG_DEVPORT=y
874CONFIG_I2C=y 910CONFIG_I2C=y
875CONFIG_I2C_BOARDINFO=y 911CONFIG_I2C_BOARDINFO=y
876CONFIG_I2C_CHARDEV=y 912CONFIG_I2C_CHARDEV=y
913CONFIG_I2C_HELPER_AUTO=y
877 914
878# 915#
879# I2C Hardware Bus support 916# I2C Hardware Bus support
880# 917#
918
919#
920# PC SMBus host controller drivers
921#
881# CONFIG_I2C_ALI1535 is not set 922# CONFIG_I2C_ALI1535 is not set
882# CONFIG_I2C_ALI1563 is not set 923# CONFIG_I2C_ALI1563 is not set
883# CONFIG_I2C_ALI15X3 is not set 924# CONFIG_I2C_ALI15X3 is not set
884# CONFIG_I2C_AMD756 is not set 925# CONFIG_I2C_AMD756 is not set
885# CONFIG_I2C_AMD8111 is not set 926# CONFIG_I2C_AMD8111 is not set
886# CONFIG_I2C_I801 is not set 927# CONFIG_I2C_I801 is not set
887# CONFIG_I2C_I810 is not set 928# CONFIG_I2C_ISCH is not set
888# CONFIG_I2C_PIIX4 is not set 929# CONFIG_I2C_PIIX4 is not set
889CONFIG_I2C_MPC=y
890# CONFIG_I2C_NFORCE2 is not set 930# CONFIG_I2C_NFORCE2 is not set
891# CONFIG_I2C_OCORES is not set
892# CONFIG_I2C_PARPORT_LIGHT is not set
893# CONFIG_I2C_PROSAVAGE is not set
894# CONFIG_I2C_SAVAGE4 is not set
895# CONFIG_I2C_SIMTEC is not set
896# CONFIG_I2C_SIS5595 is not set 931# CONFIG_I2C_SIS5595 is not set
897# CONFIG_I2C_SIS630 is not set 932# CONFIG_I2C_SIS630 is not set
898# CONFIG_I2C_SIS96X is not set 933# CONFIG_I2C_SIS96X is not set
899# CONFIG_I2C_TAOS_EVM is not set
900# CONFIG_I2C_STUB is not set
901# CONFIG_I2C_VIA is not set 934# CONFIG_I2C_VIA is not set
902# CONFIG_I2C_VIAPRO is not set 935# CONFIG_I2C_VIAPRO is not set
936
937#
938# Mac SMBus host controller drivers
939#
940# CONFIG_I2C_HYDRA is not set
941CONFIG_I2C_POWERMAC=y
942
943#
944# I2C system bus drivers (mostly embedded / system-on-chip)
945#
946CONFIG_I2C_MPC=y
947# CONFIG_I2C_OCORES is not set
948# CONFIG_I2C_SIMTEC is not set
949
950#
951# External I2C/SMBus adapter drivers
952#
953# CONFIG_I2C_PARPORT_LIGHT is not set
954# CONFIG_I2C_TAOS_EVM is not set
955
956#
957# Graphics adapter I2C/DDC channel drivers
958#
903# CONFIG_I2C_VOODOO3 is not set 959# CONFIG_I2C_VOODOO3 is not set
960
961#
962# Other I2C/SMBus bus drivers
963#
904# CONFIG_I2C_PCA_PLATFORM is not set 964# CONFIG_I2C_PCA_PLATFORM is not set
965# CONFIG_I2C_STUB is not set
905 966
906# 967#
907# Miscellaneous I2C Chip support 968# Miscellaneous I2C Chip support
908# 969#
909# CONFIG_DS1682 is not set 970# CONFIG_DS1682 is not set
971# CONFIG_AT24 is not set
910# CONFIG_SENSORS_EEPROM is not set 972# CONFIG_SENSORS_EEPROM is not set
911# CONFIG_SENSORS_PCF8574 is not set 973# CONFIG_SENSORS_PCF8574 is not set
912# CONFIG_PCF8575 is not set 974# CONFIG_PCF8575 is not set
975# CONFIG_SENSORS_PCA9539 is not set
913# CONFIG_SENSORS_PCF8591 is not set 976# CONFIG_SENSORS_PCF8591 is not set
914# CONFIG_SENSORS_MAX6875 is not set 977# CONFIG_SENSORS_MAX6875 is not set
915# CONFIG_SENSORS_TSL2550 is not set 978# CONFIG_SENSORS_TSL2550 is not set
@@ -918,10 +981,13 @@ CONFIG_I2C_MPC=y
918# CONFIG_I2C_DEBUG_BUS is not set 981# CONFIG_I2C_DEBUG_BUS is not set
919# CONFIG_I2C_DEBUG_CHIP is not set 982# CONFIG_I2C_DEBUG_CHIP is not set
920# CONFIG_SPI is not set 983# CONFIG_SPI is not set
984CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
985# CONFIG_GPIOLIB is not set
921# CONFIG_W1 is not set 986# CONFIG_W1 is not set
922# CONFIG_POWER_SUPPLY is not set 987# CONFIG_POWER_SUPPLY is not set
923CONFIG_HWMON=y 988CONFIG_HWMON=y
924# CONFIG_HWMON_VID is not set 989# CONFIG_HWMON_VID is not set
990# CONFIG_SENSORS_AD7414 is not set
925# CONFIG_SENSORS_AD7418 is not set 991# CONFIG_SENSORS_AD7418 is not set
926# CONFIG_SENSORS_ADM1021 is not set 992# CONFIG_SENSORS_ADM1021 is not set
927# CONFIG_SENSORS_ADM1025 is not set 993# CONFIG_SENSORS_ADM1025 is not set
@@ -931,6 +997,7 @@ CONFIG_HWMON=y
931# CONFIG_SENSORS_ADM9240 is not set 997# CONFIG_SENSORS_ADM9240 is not set
932# CONFIG_SENSORS_ADT7470 is not set 998# CONFIG_SENSORS_ADT7470 is not set
933# CONFIG_SENSORS_ADT7473 is not set 999# CONFIG_SENSORS_ADT7473 is not set
1000# CONFIG_SENSORS_AMS is not set
934# CONFIG_SENSORS_ATXP1 is not set 1001# CONFIG_SENSORS_ATXP1 is not set
935# CONFIG_SENSORS_DS1621 is not set 1002# CONFIG_SENSORS_DS1621 is not set
936# CONFIG_SENSORS_I5K_AMB is not set 1003# CONFIG_SENSORS_I5K_AMB is not set
@@ -975,6 +1042,7 @@ CONFIG_HWMON=y
975# CONFIG_SENSORS_W83627EHF is not set 1042# CONFIG_SENSORS_W83627EHF is not set
976# CONFIG_HWMON_DEBUG_CHIP is not set 1043# CONFIG_HWMON_DEBUG_CHIP is not set
977# CONFIG_THERMAL is not set 1044# CONFIG_THERMAL is not set
1045# CONFIG_THERMAL_HWMON is not set
978CONFIG_WATCHDOG=y 1046CONFIG_WATCHDOG=y
979# CONFIG_WATCHDOG_NOWAYOUT is not set 1047# CONFIG_WATCHDOG_NOWAYOUT is not set
980 1048
@@ -982,6 +1050,9 @@ CONFIG_WATCHDOG=y
982# Watchdog Device Drivers 1050# Watchdog Device Drivers
983# 1051#
984CONFIG_SOFT_WATCHDOG=m 1052CONFIG_SOFT_WATCHDOG=m
1053# CONFIG_ALIM7101_WDT is not set
1054# CONFIG_8xxx_WDT is not set
1055# CONFIG_WATCHDOG_RTAS is not set
985 1056
986# 1057#
987# PCI-based Watchdog Cards 1058# PCI-based Watchdog Cards
@@ -998,8 +1069,10 @@ CONFIG_SSB_POSSIBLE=y
998# 1069#
999# Multifunction device drivers 1070# Multifunction device drivers
1000# 1071#
1072# CONFIG_MFD_CORE is not set
1001# CONFIG_MFD_SM501 is not set 1073# CONFIG_MFD_SM501 is not set
1002# CONFIG_HTC_PASIC3 is not set 1074# CONFIG_HTC_PASIC3 is not set
1075# CONFIG_MFD_TMIO is not set
1003 1076
1004# 1077#
1005# Multimedia devices 1078# Multimedia devices
@@ -1038,10 +1111,6 @@ CONFIG_VIDEO_OUTPUT_CONTROL=m
1038CONFIG_VGA_CONSOLE=y 1111CONFIG_VGA_CONSOLE=y
1039# CONFIG_VGACON_SOFT_SCROLLBACK is not set 1112# CONFIG_VGACON_SOFT_SCROLLBACK is not set
1040CONFIG_DUMMY_CONSOLE=y 1113CONFIG_DUMMY_CONSOLE=y
1041
1042#
1043# Sound
1044#
1045# CONFIG_SOUND is not set 1114# CONFIG_SOUND is not set
1046CONFIG_HID_SUPPORT=y 1115CONFIG_HID_SUPPORT=y
1047CONFIG_HID=y 1116CONFIG_HID=y
@@ -1056,6 +1125,10 @@ CONFIG_USB_ARCH_HAS_EHCI=y
1056# CONFIG_USB_OTG_BLACKLIST_HUB is not set 1125# CONFIG_USB_OTG_BLACKLIST_HUB is not set
1057 1126
1058# 1127#
1128# Enable Host or Gadget support to see Inventra options
1129#
1130
1131#
1059# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 1132# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
1060# 1133#
1061# CONFIG_USB_GADGET is not set 1134# CONFIG_USB_GADGET is not set
@@ -1096,6 +1169,7 @@ CONFIG_FS_POSIX_ACL=y
1096# CONFIG_XFS_FS is not set 1169# CONFIG_XFS_FS is not set
1097CONFIG_OCFS2_FS=m 1170CONFIG_OCFS2_FS=m
1098CONFIG_OCFS2_FS_O2CB=m 1171CONFIG_OCFS2_FS_O2CB=m
1172CONFIG_OCFS2_FS_STATS=y
1099CONFIG_OCFS2_DEBUG_MASKLOG=y 1173CONFIG_OCFS2_DEBUG_MASKLOG=y
1100# CONFIG_OCFS2_DEBUG_FS is not set 1174# CONFIG_OCFS2_DEBUG_FS is not set
1101CONFIG_DNOTIFY=y 1175CONFIG_DNOTIFY=y
@@ -1145,6 +1219,7 @@ CONFIG_CONFIGFS_FS=m
1145# CONFIG_CRAMFS is not set 1219# CONFIG_CRAMFS is not set
1146# CONFIG_VXFS_FS is not set 1220# CONFIG_VXFS_FS is not set
1147CONFIG_MINIX_FS=m 1221CONFIG_MINIX_FS=m
1222# CONFIG_OMFS_FS is not set
1148# CONFIG_HPFS_FS is not set 1223# CONFIG_HPFS_FS is not set
1149# CONFIG_QNX4FS_FS is not set 1224# CONFIG_QNX4FS_FS is not set
1150CONFIG_ROMFS_FS=m 1225CONFIG_ROMFS_FS=m
@@ -1155,14 +1230,13 @@ CONFIG_NFS_FS=y
1155CONFIG_NFS_V3=y 1230CONFIG_NFS_V3=y
1156# CONFIG_NFS_V3_ACL is not set 1231# CONFIG_NFS_V3_ACL is not set
1157CONFIG_NFS_V4=y 1232CONFIG_NFS_V4=y
1158# CONFIG_NFSD is not set
1159CONFIG_ROOT_NFS=y 1233CONFIG_ROOT_NFS=y
1234# CONFIG_NFSD is not set
1160CONFIG_LOCKD=y 1235CONFIG_LOCKD=y
1161CONFIG_LOCKD_V4=y 1236CONFIG_LOCKD_V4=y
1162CONFIG_NFS_COMMON=y 1237CONFIG_NFS_COMMON=y
1163CONFIG_SUNRPC=y 1238CONFIG_SUNRPC=y
1164CONFIG_SUNRPC_GSS=y 1239CONFIG_SUNRPC_GSS=y
1165# CONFIG_SUNRPC_BIND34 is not set
1166CONFIG_RPCSEC_GSS_KRB5=y 1240CONFIG_RPCSEC_GSS_KRB5=y
1167# CONFIG_RPCSEC_GSS_SPKM3 is not set 1241# CONFIG_RPCSEC_GSS_SPKM3 is not set
1168CONFIG_SMB_FS=m 1242CONFIG_SMB_FS=m
@@ -1183,6 +1257,7 @@ CONFIG_CIFS_POSIX=y
1183# Partition Types 1257# Partition Types
1184# 1258#
1185# CONFIG_PARTITION_ADVANCED is not set 1259# CONFIG_PARTITION_ADVANCED is not set
1260CONFIG_MAC_PARTITION=y
1186CONFIG_MSDOS_PARTITION=y 1261CONFIG_MSDOS_PARTITION=y
1187CONFIG_NLS=m 1262CONFIG_NLS=m
1188CONFIG_NLS_DEFAULT="iso8859-1" 1263CONFIG_NLS_DEFAULT="iso8859-1"
@@ -1233,6 +1308,7 @@ CONFIG_BITREVERSE=y
1233# CONFIG_GENERIC_FIND_FIRST_BIT is not set 1308# CONFIG_GENERIC_FIND_FIRST_BIT is not set
1234CONFIG_CRC_CCITT=m 1309CONFIG_CRC_CCITT=m
1235# CONFIG_CRC16 is not set 1310# CONFIG_CRC16 is not set
1311# CONFIG_CRC_T10DIF is not set
1236# CONFIG_CRC_ITU_T is not set 1312# CONFIG_CRC_ITU_T is not set
1237CONFIG_CRC32=y 1313CONFIG_CRC32=y
1238# CONFIG_CRC7 is not set 1314# CONFIG_CRC7 is not set
@@ -1259,6 +1335,8 @@ CONFIG_DEBUG_FS=y
1259CONFIG_DEBUG_KERNEL=y 1335CONFIG_DEBUG_KERNEL=y
1260# CONFIG_DEBUG_SHIRQ is not set 1336# CONFIG_DEBUG_SHIRQ is not set
1261CONFIG_DETECT_SOFTLOCKUP=y 1337CONFIG_DETECT_SOFTLOCKUP=y
1338# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
1339CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
1262CONFIG_SCHED_DEBUG=y 1340CONFIG_SCHED_DEBUG=y
1263# CONFIG_SCHEDSTATS is not set 1341# CONFIG_SCHEDSTATS is not set
1264# CONFIG_TIMER_STATS is not set 1342# CONFIG_TIMER_STATS is not set
@@ -1275,21 +1353,34 @@ CONFIG_SCHED_DEBUG=y
1275CONFIG_DEBUG_INFO=y 1353CONFIG_DEBUG_INFO=y
1276# CONFIG_DEBUG_VM is not set 1354# CONFIG_DEBUG_VM is not set
1277# CONFIG_DEBUG_WRITECOUNT is not set 1355# CONFIG_DEBUG_WRITECOUNT is not set
1356# CONFIG_DEBUG_MEMORY_INIT is not set
1278# CONFIG_DEBUG_LIST is not set 1357# CONFIG_DEBUG_LIST is not set
1279# CONFIG_DEBUG_SG is not set 1358# CONFIG_DEBUG_SG is not set
1280# CONFIG_BOOT_PRINTK_DELAY is not set 1359# CONFIG_BOOT_PRINTK_DELAY is not set
1281# CONFIG_RCU_TORTURE_TEST is not set 1360# CONFIG_RCU_TORTURE_TEST is not set
1282# CONFIG_BACKTRACE_SELF_TEST is not set 1361# CONFIG_BACKTRACE_SELF_TEST is not set
1283# CONFIG_FAULT_INJECTION is not set 1362# CONFIG_FAULT_INJECTION is not set
1363# CONFIG_LATENCYTOP is not set
1364CONFIG_SYSCTL_SYSCALL_CHECK=y
1365CONFIG_HAVE_FTRACE=y
1366CONFIG_HAVE_DYNAMIC_FTRACE=y
1367# CONFIG_FTRACE is not set
1368# CONFIG_PREEMPT_TRACER is not set
1369# CONFIG_SCHED_TRACER is not set
1370# CONFIG_CONTEXT_SWITCH_TRACER is not set
1284# CONFIG_SAMPLES is not set 1371# CONFIG_SAMPLES is not set
1372CONFIG_HAVE_ARCH_KGDB=y
1373# CONFIG_KGDB is not set
1285# CONFIG_DEBUG_STACKOVERFLOW is not set 1374# CONFIG_DEBUG_STACKOVERFLOW is not set
1286# CONFIG_DEBUG_STACK_USAGE is not set 1375# CONFIG_DEBUG_STACK_USAGE is not set
1287# CONFIG_DEBUG_PAGEALLOC is not set 1376# CONFIG_DEBUG_PAGEALLOC is not set
1288CONFIG_DEBUGGER=y 1377# CONFIG_CODE_PATCHING_SELFTEST is not set
1378# CONFIG_FTR_FIXUP_SELFTEST is not set
1289# CONFIG_XMON is not set 1379# CONFIG_XMON is not set
1290# CONFIG_IRQSTACKS is not set 1380# CONFIG_IRQSTACKS is not set
1291# CONFIG_VIRQ_DEBUG is not set 1381# CONFIG_VIRQ_DEBUG is not set
1292# CONFIG_BDI_SWITCH is not set 1382# CONFIG_BDI_SWITCH is not set
1383# CONFIG_BOOTX_TEXT is not set
1293# CONFIG_PPC_EARLY_DEBUG is not set 1384# CONFIG_PPC_EARLY_DEBUG is not set
1294 1385
1295# 1386#
@@ -1299,7 +1390,6 @@ CONFIG_DEBUGGER=y
1299CONFIG_SECURITY=y 1390CONFIG_SECURITY=y
1300CONFIG_SECURITY_NETWORK=y 1391CONFIG_SECURITY_NETWORK=y
1301# CONFIG_SECURITY_NETWORK_XFRM is not set 1392# CONFIG_SECURITY_NETWORK_XFRM is not set
1302CONFIG_SECURITY_CAPABILITIES=y
1303# CONFIG_SECURITY_FILE_CAPABILITIES is not set 1393# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1304CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0 1394CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0
1305CONFIG_CRYPTO=y 1395CONFIG_CRYPTO=y
@@ -1349,6 +1439,10 @@ CONFIG_CRYPTO_CRC32C=m
1349CONFIG_CRYPTO_MD4=m 1439CONFIG_CRYPTO_MD4=m
1350CONFIG_CRYPTO_MD5=y 1440CONFIG_CRYPTO_MD5=y
1351CONFIG_CRYPTO_MICHAEL_MIC=m 1441CONFIG_CRYPTO_MICHAEL_MIC=m
1442# CONFIG_CRYPTO_RMD128 is not set
1443# CONFIG_CRYPTO_RMD160 is not set
1444# CONFIG_CRYPTO_RMD256 is not set
1445# CONFIG_CRYPTO_RMD320 is not set
1352CONFIG_CRYPTO_SHA1=m 1446CONFIG_CRYPTO_SHA1=m
1353CONFIG_CRYPTO_SHA256=m 1447CONFIG_CRYPTO_SHA256=m
1354CONFIG_CRYPTO_SHA512=m 1448CONFIG_CRYPTO_SHA512=m
@@ -1382,5 +1476,6 @@ CONFIG_CRYPTO_DEFLATE=m
1382# CONFIG_CRYPTO_LZO is not set 1476# CONFIG_CRYPTO_LZO is not set
1383CONFIG_CRYPTO_HW=y 1477CONFIG_CRYPTO_HW=y
1384# CONFIG_CRYPTO_DEV_HIFN_795X is not set 1478# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1479# CONFIG_CRYPTO_DEV_TALITOS is not set
1385# CONFIG_PPC_CLOCK is not set 1480# CONFIG_PPC_CLOCK is not set
1386# CONFIG_VIRTUALIZATION is not set 1481# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/configs/storcenter_defconfig b/arch/powerpc/configs/storcenter_defconfig
index 88f6aa8273be..4340cc1c5b6a 100644
--- a/arch/powerpc/configs/storcenter_defconfig
+++ b/arch/powerpc/configs/storcenter_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc5 3# Linux kernel version: 2.6.27-rc4
4# Mon Jun 9 08:52:20 2008 4# Thu Aug 21 00:52:16 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -32,6 +32,7 @@ CONFIG_GENERIC_HARDIRQS=y
32# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set 32# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
33CONFIG_IRQ_PER_CPU=y 33CONFIG_IRQ_PER_CPU=y
34CONFIG_STACKTRACE_SUPPORT=y 34CONFIG_STACKTRACE_SUPPORT=y
35CONFIG_HAVE_LATENCYTOP_SUPPORT=y
35CONFIG_LOCKDEP_SUPPORT=y 36CONFIG_LOCKDEP_SUPPORT=y
36CONFIG_RWSEM_XCHGADD_ALGORITHM=y 37CONFIG_RWSEM_XCHGADD_ALGORITHM=y
37CONFIG_ARCH_HAS_ILOG2_U32=y 38CONFIG_ARCH_HAS_ILOG2_U32=y
@@ -87,7 +88,6 @@ CONFIG_CC_OPTIMIZE_FOR_SIZE=y
87CONFIG_SYSCTL=y 88CONFIG_SYSCTL=y
88CONFIG_EMBEDDED=y 89CONFIG_EMBEDDED=y
89CONFIG_SYSCTL_SYSCALL=y 90CONFIG_SYSCTL_SYSCALL=y
90CONFIG_SYSCTL_SYSCALL_CHECK=y
91# CONFIG_KALLSYMS is not set 91# CONFIG_KALLSYMS is not set
92CONFIG_HOTPLUG=y 92CONFIG_HOTPLUG=y
93CONFIG_PRINTK=y 93CONFIG_PRINTK=y
@@ -110,10 +110,16 @@ CONFIG_SLUB=y
110# CONFIG_PROFILING is not set 110# CONFIG_PROFILING is not set
111# CONFIG_MARKERS is not set 111# CONFIG_MARKERS is not set
112CONFIG_HAVE_OPROFILE=y 112CONFIG_HAVE_OPROFILE=y
113CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
114CONFIG_HAVE_IOREMAP_PROT=y
113CONFIG_HAVE_KPROBES=y 115CONFIG_HAVE_KPROBES=y
114CONFIG_HAVE_KRETPROBES=y 116CONFIG_HAVE_KRETPROBES=y
117CONFIG_HAVE_ARCH_TRACEHOOK=y
115# CONFIG_HAVE_DMA_ATTRS is not set 118# CONFIG_HAVE_DMA_ATTRS is not set
119# CONFIG_USE_GENERIC_SMP_HELPERS is not set
120# CONFIG_HAVE_CLK is not set
116CONFIG_PROC_PAGE_MONITOR=y 121CONFIG_PROC_PAGE_MONITOR=y
122# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
117CONFIG_SLABINFO=y 123CONFIG_SLABINFO=y
118CONFIG_RT_MUTEXES=y 124CONFIG_RT_MUTEXES=y
119# CONFIG_TINY_SHMEM is not set 125# CONFIG_TINY_SHMEM is not set
@@ -130,6 +136,7 @@ CONFIG_LBD=y
130# CONFIG_BLK_DEV_IO_TRACE is not set 136# CONFIG_BLK_DEV_IO_TRACE is not set
131# CONFIG_LSF is not set 137# CONFIG_LSF is not set
132# CONFIG_BLK_DEV_BSG is not set 138# CONFIG_BLK_DEV_BSG is not set
139# CONFIG_BLK_DEV_INTEGRITY is not set
133 140
134# 141#
135# IO Schedulers 142# IO Schedulers
@@ -149,25 +156,25 @@ CONFIG_CLASSIC_RCU=y
149# Platform support 156# Platform support
150# 157#
151CONFIG_PPC_MULTIPLATFORM=y 158CONFIG_PPC_MULTIPLATFORM=y
152# CONFIG_PPC_82xx is not set
153# CONFIG_PPC_83xx is not set
154# CONFIG_PPC_86xx is not set
155CONFIG_CLASSIC32=y 159CONFIG_CLASSIC32=y
156# CONFIG_PPC_CHRP is not set 160# CONFIG_PPC_CHRP is not set
157# CONFIG_PPC_MPC512x is not set
158# CONFIG_PPC_MPC5121 is not set
159# CONFIG_MPC5121_ADS is not set 161# CONFIG_MPC5121_ADS is not set
162# CONFIG_MPC5121_GENERIC is not set
160# CONFIG_PPC_MPC52xx is not set 163# CONFIG_PPC_MPC52xx is not set
161# CONFIG_PPC_PMAC is not set 164# CONFIG_PPC_PMAC is not set
162# CONFIG_PPC_CELL is not set 165# CONFIG_PPC_CELL is not set
163# CONFIG_PPC_CELL_NATIVE is not set 166# CONFIG_PPC_CELL_NATIVE is not set
167# CONFIG_PPC_82xx is not set
164# CONFIG_PQ2ADS is not set 168# CONFIG_PQ2ADS is not set
169# CONFIG_PPC_83xx is not set
170# CONFIG_PPC_86xx is not set
165CONFIG_EMBEDDED6xx=y 171CONFIG_EMBEDDED6xx=y
166# CONFIG_LINKSTATION is not set 172# CONFIG_LINKSTATION is not set
167CONFIG_STORCENTER=y 173CONFIG_STORCENTER=y
168# CONFIG_MPC7448HPC2 is not set 174# CONFIG_MPC7448HPC2 is not set
169# CONFIG_PPC_HOLLY is not set 175# CONFIG_PPC_HOLLY is not set
170# CONFIG_PPC_PRPMC2800 is not set 176# CONFIG_PPC_PRPMC2800 is not set
177# CONFIG_PPC_C2K is not set
171CONFIG_MPC10X_BRIDGE=y 178CONFIG_MPC10X_BRIDGE=y
172CONFIG_MPC10X_OPENPIC=y 179CONFIG_MPC10X_OPENPIC=y
173# CONFIG_MPC10X_STORE_GATHERING is not set 180# CONFIG_MPC10X_STORE_GATHERING is not set
@@ -221,6 +228,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
221# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set 228# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
222CONFIG_PAGEFLAGS_EXTENDED=y 229CONFIG_PAGEFLAGS_EXTENDED=y
223CONFIG_SPLIT_PTLOCK_CPUS=4 230CONFIG_SPLIT_PTLOCK_CPUS=4
231CONFIG_MIGRATION=y
224# CONFIG_RESOURCES_64BIT is not set 232# CONFIG_RESOURCES_64BIT is not set
225CONFIG_ZONE_DMA_FLAG=1 233CONFIG_ZONE_DMA_FLAG=1
226CONFIG_BOUNCE=y 234CONFIG_BOUNCE=y
@@ -229,6 +237,7 @@ CONFIG_FORCE_MAX_ZONEORDER=11
229CONFIG_PROC_DEVICETREE=y 237CONFIG_PROC_DEVICETREE=y
230CONFIG_CMDLINE_BOOL=y 238CONFIG_CMDLINE_BOOL=y
231CONFIG_CMDLINE="console=ttyS0,115200" 239CONFIG_CMDLINE="console=ttyS0,115200"
240CONFIG_EXTRA_TARGETS=""
232# CONFIG_PM is not set 241# CONFIG_PM is not set
233# CONFIG_SECCOMP is not set 242# CONFIG_SECCOMP is not set
234CONFIG_ISA_DMA_API=y 243CONFIG_ISA_DMA_API=y
@@ -264,10 +273,6 @@ CONFIG_PAGE_OFFSET=0xc0000000
264CONFIG_KERNEL_START=0xc0000000 273CONFIG_KERNEL_START=0xc0000000
265CONFIG_PHYSICAL_START=0x00000000 274CONFIG_PHYSICAL_START=0x00000000
266CONFIG_TASK_SIZE=0xc0000000 275CONFIG_TASK_SIZE=0xc0000000
267
268#
269# Networking
270#
271CONFIG_NET=y 276CONFIG_NET=y
272 277
273# 278#
@@ -456,20 +461,22 @@ CONFIG_BLK_DEV=y
456# CONFIG_BLK_DEV_RAM is not set 461# CONFIG_BLK_DEV_RAM is not set
457# CONFIG_CDROM_PKTCDVD is not set 462# CONFIG_CDROM_PKTCDVD is not set
458# CONFIG_ATA_OVER_ETH is not set 463# CONFIG_ATA_OVER_ETH is not set
464# CONFIG_BLK_DEV_HD is not set
459CONFIG_MISC_DEVICES=y 465CONFIG_MISC_DEVICES=y
460# CONFIG_PHANTOM is not set 466# CONFIG_PHANTOM is not set
461# CONFIG_EEPROM_93CX6 is not set 467# CONFIG_EEPROM_93CX6 is not set
462# CONFIG_SGI_IOC4 is not set 468# CONFIG_SGI_IOC4 is not set
463# CONFIG_TIFM_CORE is not set 469# CONFIG_TIFM_CORE is not set
464# CONFIG_ENCLOSURE_SERVICES is not set 470# CONFIG_ENCLOSURE_SERVICES is not set
471# CONFIG_HP_ILO is not set
465CONFIG_HAVE_IDE=y 472CONFIG_HAVE_IDE=y
466CONFIG_IDE=y 473CONFIG_IDE=y
467CONFIG_IDE_MAX_HWIFS=4
468CONFIG_BLK_DEV_IDE=y 474CONFIG_BLK_DEV_IDE=y
469 475
470# 476#
471# Please see Documentation/ide/ide.txt for help/info on IDE drives 477# Please see Documentation/ide/ide.txt for help/info on IDE drives
472# 478#
479CONFIG_IDE_TIMINGS=y
473# CONFIG_BLK_DEV_IDE_SATA is not set 480# CONFIG_BLK_DEV_IDE_SATA is not set
474CONFIG_BLK_DEV_IDEDISK=y 481CONFIG_BLK_DEV_IDEDISK=y
475CONFIG_IDEDISK_MULTI_MODE=y 482CONFIG_IDEDISK_MULTI_MODE=y
@@ -483,7 +490,6 @@ CONFIG_IDE_PROC_FS=y
483# 490#
484# IDE chipset support/bugfixes 491# IDE chipset support/bugfixes
485# 492#
486CONFIG_IDE_GENERIC=y
487# CONFIG_BLK_DEV_PLATFORM is not set 493# CONFIG_BLK_DEV_PLATFORM is not set
488CONFIG_BLK_DEV_IDEDMA_SFF=y 494CONFIG_BLK_DEV_IDEDMA_SFF=y
489 495
@@ -500,10 +506,8 @@ CONFIG_BLK_DEV_IDEDMA_PCI=y
500# CONFIG_BLK_DEV_AMD74XX is not set 506# CONFIG_BLK_DEV_AMD74XX is not set
501# CONFIG_BLK_DEV_CMD64X is not set 507# CONFIG_BLK_DEV_CMD64X is not set
502# CONFIG_BLK_DEV_TRIFLEX is not set 508# CONFIG_BLK_DEV_TRIFLEX is not set
503# CONFIG_BLK_DEV_CY82C693 is not set
504# CONFIG_BLK_DEV_CS5520 is not set 509# CONFIG_BLK_DEV_CS5520 is not set
505# CONFIG_BLK_DEV_CS5530 is not set 510# CONFIG_BLK_DEV_CS5530 is not set
506# CONFIG_BLK_DEV_HPT34X is not set
507# CONFIG_BLK_DEV_HPT366 is not set 511# CONFIG_BLK_DEV_HPT366 is not set
508# CONFIG_BLK_DEV_JMICRON is not set 512# CONFIG_BLK_DEV_JMICRON is not set
509# CONFIG_BLK_DEV_SC1200 is not set 513# CONFIG_BLK_DEV_SC1200 is not set
@@ -521,8 +525,6 @@ CONFIG_BLK_DEV_IDEDMA_PCI=y
521CONFIG_BLK_DEV_VIA82CXXX=y 525CONFIG_BLK_DEV_VIA82CXXX=y
522# CONFIG_BLK_DEV_TC86C001 is not set 526# CONFIG_BLK_DEV_TC86C001 is not set
523CONFIG_BLK_DEV_IDEDMA=y 527CONFIG_BLK_DEV_IDEDMA=y
524# CONFIG_BLK_DEV_HD_ONLY is not set
525# CONFIG_BLK_DEV_HD is not set
526 528
527# 529#
528# SCSI device support 530# SCSI device support
@@ -599,6 +601,7 @@ CONFIG_SCSI_LOWLEVEL=y
599# CONFIG_SCSI_NSP32 is not set 601# CONFIG_SCSI_NSP32 is not set
600# CONFIG_SCSI_DEBUG is not set 602# CONFIG_SCSI_DEBUG is not set
601# CONFIG_SCSI_SRP is not set 603# CONFIG_SCSI_SRP is not set
604# CONFIG_SCSI_DH is not set
602# CONFIG_ATA is not set 605# CONFIG_ATA is not set
603CONFIG_MD=y 606CONFIG_MD=y
604CONFIG_BLK_DEV_MD=y 607CONFIG_BLK_DEV_MD=y
@@ -616,12 +619,15 @@ CONFIG_MD_RAID5_RESHAPE=y
616# 619#
617# IEEE 1394 (FireWire) support 620# IEEE 1394 (FireWire) support
618# 621#
622
623#
624# Enable only one of the two stacks, unless you know what you are doing
625#
619# CONFIG_FIREWIRE is not set 626# CONFIG_FIREWIRE is not set
620# CONFIG_IEEE1394 is not set 627# CONFIG_IEEE1394 is not set
621# CONFIG_I2O is not set 628# CONFIG_I2O is not set
622# CONFIG_MACINTOSH_DRIVERS is not set 629# CONFIG_MACINTOSH_DRIVERS is not set
623CONFIG_NETDEVICES=y 630CONFIG_NETDEVICES=y
624# CONFIG_NETDEVICES_MULTIQUEUE is not set
625CONFIG_DUMMY=m 631CONFIG_DUMMY=m
626# CONFIG_BONDING is not set 632# CONFIG_BONDING is not set
627# CONFIG_MACVLAN is not set 633# CONFIG_MACVLAN is not set
@@ -635,14 +641,12 @@ CONFIG_NETDEV_1000=y
635# CONFIG_DL2K is not set 641# CONFIG_DL2K is not set
636# CONFIG_E1000 is not set 642# CONFIG_E1000 is not set
637# CONFIG_E1000E is not set 643# CONFIG_E1000E is not set
638# CONFIG_E1000E_ENABLED is not set
639# CONFIG_IP1000 is not set 644# CONFIG_IP1000 is not set
640# CONFIG_IGB is not set 645# CONFIG_IGB is not set
641# CONFIG_NS83820 is not set 646# CONFIG_NS83820 is not set
642# CONFIG_HAMACHI is not set 647# CONFIG_HAMACHI is not set
643# CONFIG_YELLOWFIN is not set 648# CONFIG_YELLOWFIN is not set
644CONFIG_R8169=y 649CONFIG_R8169=y
645# CONFIG_R8169_NAPI is not set
646# CONFIG_SIS190 is not set 650# CONFIG_SIS190 is not set
647# CONFIG_SKGE is not set 651# CONFIG_SKGE is not set
648# CONFIG_SKY2 is not set 652# CONFIG_SKY2 is not set
@@ -653,6 +657,7 @@ CONFIG_R8169=y
653# CONFIG_MV643XX_ETH is not set 657# CONFIG_MV643XX_ETH is not set
654# CONFIG_QLA3XXX is not set 658# CONFIG_QLA3XXX is not set
655# CONFIG_ATL1 is not set 659# CONFIG_ATL1 is not set
660# CONFIG_ATL1E is not set
656# CONFIG_NETDEV_10000 is not set 661# CONFIG_NETDEV_10000 is not set
657# CONFIG_TR is not set 662# CONFIG_TR is not set
658 663
@@ -734,43 +739,64 @@ CONFIG_DEVPORT=y
734CONFIG_I2C=y 739CONFIG_I2C=y
735CONFIG_I2C_BOARDINFO=y 740CONFIG_I2C_BOARDINFO=y
736CONFIG_I2C_CHARDEV=y 741CONFIG_I2C_CHARDEV=y
742CONFIG_I2C_HELPER_AUTO=y
737 743
738# 744#
739# I2C Hardware Bus support 745# I2C Hardware Bus support
740# 746#
747
748#
749# PC SMBus host controller drivers
750#
741# CONFIG_I2C_ALI1535 is not set 751# CONFIG_I2C_ALI1535 is not set
742# CONFIG_I2C_ALI1563 is not set 752# CONFIG_I2C_ALI1563 is not set
743# CONFIG_I2C_ALI15X3 is not set 753# CONFIG_I2C_ALI15X3 is not set
744# CONFIG_I2C_AMD756 is not set 754# CONFIG_I2C_AMD756 is not set
745# CONFIG_I2C_AMD8111 is not set 755# CONFIG_I2C_AMD8111 is not set
746# CONFIG_I2C_I801 is not set 756# CONFIG_I2C_I801 is not set
747# CONFIG_I2C_I810 is not set 757# CONFIG_I2C_ISCH is not set
748# CONFIG_I2C_PIIX4 is not set 758# CONFIG_I2C_PIIX4 is not set
749CONFIG_I2C_MPC=y
750# CONFIG_I2C_NFORCE2 is not set 759# CONFIG_I2C_NFORCE2 is not set
751# CONFIG_I2C_OCORES is not set
752# CONFIG_I2C_PARPORT_LIGHT is not set
753# CONFIG_I2C_PROSAVAGE is not set
754# CONFIG_I2C_SAVAGE4 is not set
755# CONFIG_I2C_SIMTEC is not set
756# CONFIG_I2C_SIS5595 is not set 760# CONFIG_I2C_SIS5595 is not set
757# CONFIG_I2C_SIS630 is not set 761# CONFIG_I2C_SIS630 is not set
758# CONFIG_I2C_SIS96X is not set 762# CONFIG_I2C_SIS96X is not set
759# CONFIG_I2C_TAOS_EVM is not set
760# CONFIG_I2C_STUB is not set
761# CONFIG_I2C_TINY_USB is not set
762# CONFIG_I2C_VIA is not set 763# CONFIG_I2C_VIA is not set
763# CONFIG_I2C_VIAPRO is not set 764# CONFIG_I2C_VIAPRO is not set
765
766#
767# I2C system bus drivers (mostly embedded / system-on-chip)
768#
769CONFIG_I2C_MPC=y
770# CONFIG_I2C_OCORES is not set
771# CONFIG_I2C_SIMTEC is not set
772
773#
774# External I2C/SMBus adapter drivers
775#
776# CONFIG_I2C_PARPORT_LIGHT is not set
777# CONFIG_I2C_TAOS_EVM is not set
778# CONFIG_I2C_TINY_USB is not set
779
780#
781# Graphics adapter I2C/DDC channel drivers
782#
764# CONFIG_I2C_VOODOO3 is not set 783# CONFIG_I2C_VOODOO3 is not set
784
785#
786# Other I2C/SMBus bus drivers
787#
765# CONFIG_I2C_PCA_PLATFORM is not set 788# CONFIG_I2C_PCA_PLATFORM is not set
789# CONFIG_I2C_STUB is not set
766 790
767# 791#
768# Miscellaneous I2C Chip support 792# Miscellaneous I2C Chip support
769# 793#
770# CONFIG_DS1682 is not set 794# CONFIG_DS1682 is not set
795# CONFIG_AT24 is not set
771# CONFIG_SENSORS_EEPROM is not set 796# CONFIG_SENSORS_EEPROM is not set
772# CONFIG_SENSORS_PCF8574 is not set 797# CONFIG_SENSORS_PCF8574 is not set
773# CONFIG_PCF8575 is not set 798# CONFIG_PCF8575 is not set
799# CONFIG_SENSORS_PCA9539 is not set
774# CONFIG_SENSORS_PCF8591 is not set 800# CONFIG_SENSORS_PCF8591 is not set
775# CONFIG_SENSORS_MAX6875 is not set 801# CONFIG_SENSORS_MAX6875 is not set
776# CONFIG_SENSORS_TSL2550 is not set 802# CONFIG_SENSORS_TSL2550 is not set
@@ -779,10 +805,13 @@ CONFIG_I2C_MPC=y
779# CONFIG_I2C_DEBUG_BUS is not set 805# CONFIG_I2C_DEBUG_BUS is not set
780# CONFIG_I2C_DEBUG_CHIP is not set 806# CONFIG_I2C_DEBUG_CHIP is not set
781# CONFIG_SPI is not set 807# CONFIG_SPI is not set
808CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
809# CONFIG_GPIOLIB is not set
782# CONFIG_W1 is not set 810# CONFIG_W1 is not set
783# CONFIG_POWER_SUPPLY is not set 811# CONFIG_POWER_SUPPLY is not set
784# CONFIG_HWMON is not set 812# CONFIG_HWMON is not set
785# CONFIG_THERMAL is not set 813# CONFIG_THERMAL is not set
814# CONFIG_THERMAL_HWMON is not set
786# CONFIG_WATCHDOG is not set 815# CONFIG_WATCHDOG is not set
787 816
788# 817#
@@ -794,8 +823,10 @@ CONFIG_SSB_POSSIBLE=y
794# 823#
795# Multifunction device drivers 824# Multifunction device drivers
796# 825#
826# CONFIG_MFD_CORE is not set
797# CONFIG_MFD_SM501 is not set 827# CONFIG_MFD_SM501 is not set
798# CONFIG_HTC_PASIC3 is not set 828# CONFIG_HTC_PASIC3 is not set
829# CONFIG_MFD_TMIO is not set
799 830
800# 831#
801# Multimedia devices 832# Multimedia devices
@@ -827,10 +858,6 @@ CONFIG_SSB_POSSIBLE=y
827# Display device support 858# Display device support
828# 859#
829# CONFIG_DISPLAY_SUPPORT is not set 860# CONFIG_DISPLAY_SUPPORT is not set
830
831#
832# Sound
833#
834# CONFIG_SOUND is not set 861# CONFIG_SOUND is not set
835CONFIG_USB_SUPPORT=y 862CONFIG_USB_SUPPORT=y
836CONFIG_USB_ARCH_HAS_HCD=y 863CONFIG_USB_ARCH_HAS_HCD=y
@@ -849,6 +876,7 @@ CONFIG_USB_DEVICE_CLASS=y
849# CONFIG_USB_OTG is not set 876# CONFIG_USB_OTG is not set
850# CONFIG_USB_OTG_WHITELIST is not set 877# CONFIG_USB_OTG_WHITELIST is not set
851# CONFIG_USB_OTG_BLACKLIST_HUB is not set 878# CONFIG_USB_OTG_BLACKLIST_HUB is not set
879# CONFIG_USB_MON is not set
852 880
853# 881#
854# USB Host Controller Drivers 882# USB Host Controller Drivers
@@ -896,6 +924,7 @@ CONFIG_USB_STORAGE=y
896# CONFIG_USB_STORAGE_JUMPSHOT is not set 924# CONFIG_USB_STORAGE_JUMPSHOT is not set
897# CONFIG_USB_STORAGE_ALAUDA is not set 925# CONFIG_USB_STORAGE_ALAUDA is not set
898# CONFIG_USB_STORAGE_KARMA is not set 926# CONFIG_USB_STORAGE_KARMA is not set
927# CONFIG_USB_STORAGE_SIERRA is not set
899# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set 928# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
900# CONFIG_USB_LIBUSUAL is not set 929# CONFIG_USB_LIBUSUAL is not set
901 930
@@ -904,7 +933,6 @@ CONFIG_USB_STORAGE=y
904# 933#
905# CONFIG_USB_MDC800 is not set 934# CONFIG_USB_MDC800 is not set
906# CONFIG_USB_MICROTEK is not set 935# CONFIG_USB_MICROTEK is not set
907# CONFIG_USB_MON is not set
908 936
909# 937#
910# USB port drivers 938# USB port drivers
@@ -917,7 +945,6 @@ CONFIG_USB_STORAGE=y
917# CONFIG_USB_EMI62 is not set 945# CONFIG_USB_EMI62 is not set
918# CONFIG_USB_EMI26 is not set 946# CONFIG_USB_EMI26 is not set
919# CONFIG_USB_ADUTUX is not set 947# CONFIG_USB_ADUTUX is not set
920# CONFIG_USB_AUERSWALD is not set
921# CONFIG_USB_RIO500 is not set 948# CONFIG_USB_RIO500 is not set
922# CONFIG_USB_LEGOTOWER is not set 949# CONFIG_USB_LEGOTOWER is not set
923# CONFIG_USB_LCD is not set 950# CONFIG_USB_LCD is not set
@@ -971,6 +998,7 @@ CONFIG_RTC_DRV_DS1307=y
971# CONFIG_RTC_DRV_PCF8583 is not set 998# CONFIG_RTC_DRV_PCF8583 is not set
972# CONFIG_RTC_DRV_M41T80 is not set 999# CONFIG_RTC_DRV_M41T80 is not set
973# CONFIG_RTC_DRV_S35390A is not set 1000# CONFIG_RTC_DRV_S35390A is not set
1001# CONFIG_RTC_DRV_FM3130 is not set
974 1002
975# 1003#
976# SPI RTC drivers 1004# SPI RTC drivers
@@ -1074,6 +1102,7 @@ CONFIG_JFFS2_RTIME=y
1074# CONFIG_CRAMFS is not set 1102# CONFIG_CRAMFS is not set
1075# CONFIG_VXFS_FS is not set 1103# CONFIG_VXFS_FS is not set
1076# CONFIG_MINIX_FS is not set 1104# CONFIG_MINIX_FS is not set
1105# CONFIG_OMFS_FS is not set
1077# CONFIG_HPFS_FS is not set 1106# CONFIG_HPFS_FS is not set
1078# CONFIG_QNX4FS_FS is not set 1107# CONFIG_QNX4FS_FS is not set
1079# CONFIG_ROMFS_FS is not set 1108# CONFIG_ROMFS_FS is not set
@@ -1151,6 +1180,7 @@ CONFIG_BITREVERSE=y
1151# CONFIG_GENERIC_FIND_FIRST_BIT is not set 1180# CONFIG_GENERIC_FIND_FIRST_BIT is not set
1152# CONFIG_CRC_CCITT is not set 1181# CONFIG_CRC_CCITT is not set
1153# CONFIG_CRC16 is not set 1182# CONFIG_CRC16 is not set
1183CONFIG_CRC_T10DIF=y
1154# CONFIG_CRC_ITU_T is not set 1184# CONFIG_CRC_ITU_T is not set
1155CONFIG_CRC32=y 1185CONFIG_CRC32=y
1156# CONFIG_CRC7 is not set 1186# CONFIG_CRC7 is not set
@@ -1178,7 +1208,16 @@ CONFIG_FRAME_WARN=1024
1178# CONFIG_SLUB_DEBUG_ON is not set 1208# CONFIG_SLUB_DEBUG_ON is not set
1179# CONFIG_SLUB_STATS is not set 1209# CONFIG_SLUB_STATS is not set
1180# CONFIG_DEBUG_BUGVERBOSE is not set 1210# CONFIG_DEBUG_BUGVERBOSE is not set
1211# CONFIG_DEBUG_MEMORY_INIT is not set
1212# CONFIG_LATENCYTOP is not set
1213CONFIG_SYSCTL_SYSCALL_CHECK=y
1214CONFIG_HAVE_FTRACE=y
1215CONFIG_HAVE_DYNAMIC_FTRACE=y
1216# CONFIG_FTRACE is not set
1217# CONFIG_SCHED_TRACER is not set
1218# CONFIG_CONTEXT_SWITCH_TRACER is not set
1181# CONFIG_SAMPLES is not set 1219# CONFIG_SAMPLES is not set
1220CONFIG_HAVE_ARCH_KGDB=y
1182# CONFIG_IRQSTACKS is not set 1221# CONFIG_IRQSTACKS is not set
1183# CONFIG_BOOTX_TEXT is not set 1222# CONFIG_BOOTX_TEXT is not set
1184# CONFIG_PPC_EARLY_DEBUG is not set 1223# CONFIG_PPC_EARLY_DEBUG is not set
diff --git a/arch/powerpc/include/asm/cpm2.h b/arch/powerpc/include/asm/cpm2.h
index 2a6fa0183ac9..0f5e8ff59a85 100644
--- a/arch/powerpc/include/asm/cpm2.h
+++ b/arch/powerpc/include/asm/cpm2.h
@@ -337,6 +337,11 @@ typedef struct scc_param {
337 uint scc_tcrc; /* Internal */ 337 uint scc_tcrc; /* Internal */
338} sccp_t; 338} sccp_t;
339 339
340/* Function code bits.
341*/
342#define SCC_EB ((u_char) 0x10) /* Set big endian byte order */
343#define SCC_GBL ((u_char) 0x20) /* Snooping enabled */
344
340/* CPM Ethernet through SCC1. 345/* CPM Ethernet through SCC1.
341 */ 346 */
342typedef struct scc_enet { 347typedef struct scc_enet {
diff --git a/arch/powerpc/platforms/ps3/htab.c b/arch/powerpc/platforms/ps3/htab.c
index 1cf901fa9031..6eb1d4d182c9 100644
--- a/arch/powerpc/platforms/ps3/htab.c
+++ b/arch/powerpc/platforms/ps3/htab.c
@@ -29,138 +29,75 @@
29 29
30#include "platform.h" 30#include "platform.h"
31 31
32#if defined(DEBUG) 32/**
33#define DBG udbg_printf 33 * enum lpar_vas_id - id of LPAR virtual address space.
34#else 34 * @lpar_vas_id_current: Current selected virtual address space
35#define DBG pr_debug 35 *
36#endif 36 * Identify the target LPAR address space.
37 37 */
38static struct hash_pte *htab; 38
39static unsigned long htab_addr; 39enum ps3_lpar_vas_id {
40static unsigned char *bolttab; 40 PS3_LPAR_VAS_ID_CURRENT = 0,
41static unsigned char *inusetab; 41};
42 42
43static DEFINE_SPINLOCK(ps3_bolttab_lock); 43
44 44static DEFINE_SPINLOCK(ps3_htab_lock);
45#define debug_dump_hpte(_a, _b, _c, _d, _e, _f, _g) \
46 _debug_dump_hpte(_a, _b, _c, _d, _e, _f, _g, __func__, __LINE__)
47static void _debug_dump_hpte(unsigned long pa, unsigned long va,
48 unsigned long group, unsigned long bitmap, struct hash_pte lhpte,
49 int psize, unsigned long slot, const char* func, int line)
50{
51 DBG("%s:%d: pa = %lxh\n", func, line, pa);
52 DBG("%s:%d: lpar = %lxh\n", func, line,
53 ps3_mm_phys_to_lpar(pa));
54 DBG("%s:%d: va = %lxh\n", func, line, va);
55 DBG("%s:%d: group = %lxh\n", func, line, group);
56 DBG("%s:%d: bitmap = %lxh\n", func, line, bitmap);
57 DBG("%s:%d: hpte.v = %lxh\n", func, line, lhpte.v);
58 DBG("%s:%d: hpte.r = %lxh\n", func, line, lhpte.r);
59 DBG("%s:%d: psize = %xh\n", func, line, psize);
60 DBG("%s:%d: slot = %lxh\n", func, line, slot);
61}
62 45
63static long ps3_hpte_insert(unsigned long hpte_group, unsigned long va, 46static long ps3_hpte_insert(unsigned long hpte_group, unsigned long va,
64 unsigned long pa, unsigned long rflags, unsigned long vflags, 47 unsigned long pa, unsigned long rflags, unsigned long vflags,
65 int psize, int ssize) 48 int psize, int ssize)
66{ 49{
67 unsigned long slot; 50 int result;
68 struct hash_pte lhpte; 51 u64 hpte_v, hpte_r;
69 int secondary = 0; 52 u64 inserted_index;
70 unsigned long result; 53 u64 evicted_v, evicted_r;
71 unsigned long bitmap; 54 u64 hpte_v_array[4], hpte_rs;
72 unsigned long flags; 55 unsigned long flags;
73 unsigned long p_pteg, s_pteg, b_index, b_mask, cb, ci; 56 long ret = -1;
74
75 vflags &= ~HPTE_V_SECONDARY; /* this bit is ignored */
76
77 lhpte.v = hpte_encode_v(va, psize, MMU_SEGSIZE_256M) |
78 vflags | HPTE_V_VALID;
79 lhpte.r = hpte_encode_r(ps3_mm_phys_to_lpar(pa), psize) | rflags;
80
81 p_pteg = hpte_group / HPTES_PER_GROUP;
82 s_pteg = ~p_pteg & htab_hash_mask;
83
84 spin_lock_irqsave(&ps3_bolttab_lock, flags);
85
86 BUG_ON(bolttab[p_pteg] == 0xff && bolttab[s_pteg] == 0xff);
87 57
88 bitmap = (inusetab[p_pteg] << 8) | inusetab[s_pteg]; 58 /*
59 * lv1_insert_htab_entry() will search for victim
60 * entry in both primary and secondary pte group
61 */
62 vflags &= ~HPTE_V_SECONDARY;
89 63
90 if (bitmap == 0xffff) { 64 hpte_v = hpte_encode_v(va, psize, ssize) | vflags | HPTE_V_VALID;
91 /* 65 hpte_r = hpte_encode_r(ps3_mm_phys_to_lpar(pa), psize) | rflags;
92 * PTEG is full. Search for victim.
93 */
94 bitmap &= ~((bolttab[p_pteg] << 8) | bolttab[s_pteg]);
95 do {
96 ci = mftb() & 15;
97 cb = 0x8000UL >> ci;
98 } while ((cb & bitmap) == 0);
99 } else {
100 /*
101 * search free slot in hardware order
102 * [primary] 0, 2, 4, 6, 1, 3, 5, 7
103 * [secondary] 0, 2, 4, 6, 1, 3, 5, 7
104 */
105 for (ci = 0; ci < HPTES_PER_GROUP; ci += 2) {
106 cb = 0x8000UL >> ci;
107 if ((cb & bitmap) == 0)
108 goto found;
109 }
110 for (ci = 1; ci < HPTES_PER_GROUP; ci += 2) {
111 cb = 0x8000UL >> ci;
112 if ((cb & bitmap) == 0)
113 goto found;
114 }
115 for (ci = HPTES_PER_GROUP; ci < HPTES_PER_GROUP*2; ci += 2) {
116 cb = 0x8000UL >> ci;
117 if ((cb & bitmap) == 0)
118 goto found;
119 }
120 for (ci = HPTES_PER_GROUP+1; ci < HPTES_PER_GROUP*2; ci += 2) {
121 cb = 0x8000UL >> ci;
122 if ((cb & bitmap) == 0)
123 goto found;
124 }
125 }
126 66
127found: 67 spin_lock_irqsave(&ps3_htab_lock, flags);
128 if (ci < HPTES_PER_GROUP) {
129 slot = p_pteg * HPTES_PER_GROUP + ci;
130 } else {
131 slot = s_pteg * HPTES_PER_GROUP + (ci & 7);
132 /* lhpte.dw0.dw0.h = 1; */
133 vflags |= HPTE_V_SECONDARY;
134 lhpte.v |= HPTE_V_SECONDARY;
135 }
136 68
137 result = lv1_write_htab_entry(0, slot, lhpte.v, lhpte.r); 69 /* talk hvc to replace entries BOLTED == 0 */
70 result = lv1_insert_htab_entry(PS3_LPAR_VAS_ID_CURRENT, hpte_group,
71 hpte_v, hpte_r,
72 HPTE_V_BOLTED, 0,
73 &inserted_index,
74 &evicted_v, &evicted_r);
138 75
139 if (result) { 76 if (result) {
140 debug_dump_hpte(pa, va, hpte_group, bitmap, lhpte, psize, slot); 77 /* all entries bolted !*/
78 pr_info("%s:result=%d va=%lx pa=%lx ix=%lx v=%lx r=%lx\n",
79 __func__, result, va, pa, hpte_group, hpte_v, hpte_r);
141 BUG(); 80 BUG();
142 } 81 }
143 82
144 /* 83 /*
145 * If used slot is not in primary HPTE group, 84 * see if the entry is inserted into secondary pteg
146 * the slot should be in secondary HPTE group.
147 */ 85 */
86 result = lv1_read_htab_entries(PS3_LPAR_VAS_ID_CURRENT,
87 inserted_index & ~0x3UL,
88 &hpte_v_array[0], &hpte_v_array[1],
89 &hpte_v_array[2], &hpte_v_array[3],
90 &hpte_rs);
91 BUG_ON(result);
148 92
149 if ((hpte_group ^ slot) & ~(HPTES_PER_GROUP - 1)) { 93 if (hpte_v_array[inserted_index % 4] & HPTE_V_SECONDARY)
150 secondary = 1; 94 ret = (inserted_index & 7) | (1 << 3);
151 b_index = s_pteg; 95 else
152 } else { 96 ret = inserted_index & 7;
153 secondary = 0;
154 b_index = p_pteg;
155 }
156 97
157 b_mask = (lhpte.v & HPTE_V_BOLTED) ? 1 << 7 : 0 << 7; 98 spin_unlock_irqrestore(&ps3_htab_lock, flags);
158 bolttab[b_index] |= b_mask >> (slot & 7);
159 b_mask = 1 << 7;
160 inusetab[b_index] |= b_mask >> (slot & 7);
161 spin_unlock_irqrestore(&ps3_bolttab_lock, flags);
162 99
163 return (slot & 7) | (secondary << 3); 100 return ret;
164} 101}
165 102
166static long ps3_hpte_remove(unsigned long hpte_group) 103static long ps3_hpte_remove(unsigned long hpte_group)
@@ -172,39 +109,48 @@ static long ps3_hpte_remove(unsigned long hpte_group)
172static long ps3_hpte_updatepp(unsigned long slot, unsigned long newpp, 109static long ps3_hpte_updatepp(unsigned long slot, unsigned long newpp,
173 unsigned long va, int psize, int ssize, int local) 110 unsigned long va, int psize, int ssize, int local)
174{ 111{
112 int result;
113 u64 hpte_v, want_v, hpte_rs;
114 u64 hpte_v_array[4];
175 unsigned long flags; 115 unsigned long flags;
176 unsigned long result; 116 long ret;
177 unsigned long pteg, bit;
178 unsigned long hpte_v, want_v;
179 117
180 want_v = hpte_encode_v(va, psize, MMU_SEGSIZE_256M); 118 want_v = hpte_encode_v(va, psize, ssize);
181 119
182 spin_lock_irqsave(&ps3_bolttab_lock, flags); 120 spin_lock_irqsave(&ps3_htab_lock, flags);
183 121
184 hpte_v = htab[slot].v; 122 result = lv1_read_htab_entries(PS3_LPAR_VAS_ID_CURRENT, slot & ~0x3UL,
185 if (!HPTE_V_COMPARE(hpte_v, want_v) || !(hpte_v & HPTE_V_VALID)) { 123 &hpte_v_array[0], &hpte_v_array[1],
186 spin_unlock_irqrestore(&ps3_bolttab_lock, flags); 124 &hpte_v_array[2], &hpte_v_array[3],
187 125 &hpte_rs);
188 /* ps3_hpte_insert() will be used to update PTE */
189 return -1;
190 }
191
192 result = lv1_write_htab_entry(0, slot, 0, 0);
193 126
194 if (result) { 127 if (result) {
195 DBG("%s: va=%lx slot=%lx psize=%d result = %ld (0x%lx)\n", 128 pr_info("%s: res=%d read va=%lx slot=%lx psize=%d\n",
196 __func__, va, slot, psize, result, result); 129 __func__, result, va, slot, psize);
197 BUG(); 130 BUG();
198 } 131 }
199 132
200 pteg = slot / HPTES_PER_GROUP; 133 hpte_v = hpte_v_array[slot % 4];
201 bit = slot % HPTES_PER_GROUP;
202 inusetab[pteg] &= ~(0x80 >> bit);
203 134
204 spin_unlock_irqrestore(&ps3_bolttab_lock, flags); 135 /*
136 * As lv1_read_htab_entries() does not give us the RPN, we can
137 * not synthesize the new hpte_r value here, and therefore can
138 * not update the hpte with lv1_insert_htab_entry(), so we
139 * insted invalidate it and ask the caller to update it via
140 * ps3_hpte_insert() by returning a -1 value.
141 */
142 if (!HPTE_V_COMPARE(hpte_v, want_v) || !(hpte_v & HPTE_V_VALID)) {
143 /* not found */
144 ret = -1;
145 } else {
146 /* entry found, just invalidate it */
147 result = lv1_write_htab_entry(PS3_LPAR_VAS_ID_CURRENT,
148 slot, 0, 0);
149 ret = -1;
150 }
205 151
206 /* ps3_hpte_insert() will be used to update PTE */ 152 spin_unlock_irqrestore(&ps3_htab_lock, flags);
207 return -1; 153 return ret;
208} 154}
209 155
210static void ps3_hpte_updateboltedpp(unsigned long newpp, unsigned long ea, 156static void ps3_hpte_updateboltedpp(unsigned long newpp, unsigned long ea,
@@ -217,45 +163,35 @@ static void ps3_hpte_invalidate(unsigned long slot, unsigned long va,
217 int psize, int ssize, int local) 163 int psize, int ssize, int local)
218{ 164{
219 unsigned long flags; 165 unsigned long flags;
220 unsigned long result; 166 int result;
221 unsigned long pteg, bit; 167
168 spin_lock_irqsave(&ps3_htab_lock, flags);
222 169
223 spin_lock_irqsave(&ps3_bolttab_lock, flags); 170 result = lv1_write_htab_entry(PS3_LPAR_VAS_ID_CURRENT, slot, 0, 0);
224 result = lv1_write_htab_entry(0, slot, 0, 0);
225 171
226 if (result) { 172 if (result) {
227 DBG("%s: va=%lx slot=%lx psize=%d result = %ld (0x%lx)\n", 173 pr_info("%s: res=%d va=%lx slot=%lx psize=%d\n",
228 __func__, va, slot, psize, result, result); 174 __func__, result, va, slot, psize);
229 BUG(); 175 BUG();
230 } 176 }
231 177
232 pteg = slot / HPTES_PER_GROUP; 178 spin_unlock_irqrestore(&ps3_htab_lock, flags);
233 bit = slot % HPTES_PER_GROUP;
234 inusetab[pteg] &= ~(0x80 >> bit);
235 spin_unlock_irqrestore(&ps3_bolttab_lock, flags);
236} 179}
237 180
238static void ps3_hpte_clear(void) 181static void ps3_hpte_clear(void)
239{ 182{
240 int result; 183 unsigned long hpte_count = (1UL << ppc64_pft_size) >> 4;
241 184 u64 i;
242 DBG(" -> %s:%d\n", __func__, __LINE__);
243 185
244 result = lv1_unmap_htab(htab_addr); 186 for (i = 0; i < hpte_count; i++)
245 BUG_ON(result); 187 lv1_write_htab_entry(PS3_LPAR_VAS_ID_CURRENT, i, 0, 0);
246 188
247 ps3_mm_shutdown(); 189 ps3_mm_shutdown();
248 ps3_mm_vas_destroy(); 190 ps3_mm_vas_destroy();
249
250 DBG(" <- %s:%d\n", __func__, __LINE__);
251} 191}
252 192
253void __init ps3_hpte_init(unsigned long htab_size) 193void __init ps3_hpte_init(unsigned long htab_size)
254{ 194{
255 long bitmap_size;
256
257 DBG(" -> %s:%d\n", __func__, __LINE__);
258
259 ppc_md.hpte_invalidate = ps3_hpte_invalidate; 195 ppc_md.hpte_invalidate = ps3_hpte_invalidate;
260 ppc_md.hpte_updatepp = ps3_hpte_updatepp; 196 ppc_md.hpte_updatepp = ps3_hpte_updatepp;
261 ppc_md.hpte_updateboltedpp = ps3_hpte_updateboltedpp; 197 ppc_md.hpte_updateboltedpp = ps3_hpte_updateboltedpp;
@@ -264,28 +200,5 @@ void __init ps3_hpte_init(unsigned long htab_size)
264 ppc_md.hpte_clear_all = ps3_hpte_clear; 200 ppc_md.hpte_clear_all = ps3_hpte_clear;
265 201
266 ppc64_pft_size = __ilog2(htab_size); 202 ppc64_pft_size = __ilog2(htab_size);
267
268 bitmap_size = htab_size / sizeof(struct hash_pte) / 8;
269
270 bolttab = __va(lmb_alloc(bitmap_size, 1));
271 inusetab = __va(lmb_alloc(bitmap_size, 1));
272
273 memset(bolttab, 0, bitmap_size);
274 memset(inusetab, 0, bitmap_size);
275
276 DBG(" <- %s:%d\n", __func__, __LINE__);
277} 203}
278 204
279void __init ps3_map_htab(void)
280{
281 long result;
282 unsigned long htab_size = (1UL << ppc64_pft_size);
283
284 result = lv1_map_htab(0, &htab_addr);
285
286 htab = (__force struct hash_pte *)ioremap_flags(htab_addr, htab_size,
287 pgprot_val(PAGE_READONLY_X));
288
289 DBG("%s:%d: lpar %016lxh, virt %016lxh\n", __func__, __LINE__,
290 htab_addr, (unsigned long)htab);
291}
diff --git a/arch/powerpc/platforms/ps3/setup.c b/arch/powerpc/platforms/ps3/setup.c
index a413abbd4123..77bc330263c4 100644
--- a/arch/powerpc/platforms/ps3/setup.c
+++ b/arch/powerpc/platforms/ps3/setup.c
@@ -201,7 +201,6 @@ static void __init ps3_setup_arch(void)
201 ps3_firmware_version.rev); 201 ps3_firmware_version.rev);
202 202
203 ps3_spu_set_platform(); 203 ps3_spu_set_platform();
204 ps3_map_htab();
205 204
206#ifdef CONFIG_SMP 205#ifdef CONFIG_SMP
207 smp_init_ps3(); 206 smp_init_ps3();
diff --git a/arch/powerpc/platforms/ps3/spu.c b/arch/powerpc/platforms/ps3/spu.c
index d135cef9ed6a..ccae3d446b98 100644
--- a/arch/powerpc/platforms/ps3/spu.c
+++ b/arch/powerpc/platforms/ps3/spu.c
@@ -186,14 +186,24 @@ static void spu_unmap(struct spu *spu)
186 iounmap(spu_pdata(spu)->shadow); 186 iounmap(spu_pdata(spu)->shadow);
187} 187}
188 188
189/**
190 * setup_areas - Map the spu regions into the address space.
191 *
192 * The current HV requires the spu shadow regs to be mapped with the
193 * PTE page protection bits set as read-only (PP=3). This implementation
194 * uses the low level __ioremap() to bypass the page protection settings
195 * inforced by ioremap_flags() to get the needed PTE bits set for the
196 * shadow regs.
197 */
198
189static int __init setup_areas(struct spu *spu) 199static int __init setup_areas(struct spu *spu)
190{ 200{
191 struct table {char* name; unsigned long addr; unsigned long size;}; 201 struct table {char* name; unsigned long addr; unsigned long size;};
202 static const unsigned long shadow_flags = _PAGE_NO_CACHE | 3;
192 203
193 spu_pdata(spu)->shadow = ioremap_flags(spu_pdata(spu)->shadow_addr, 204 spu_pdata(spu)->shadow = __ioremap(spu_pdata(spu)->shadow_addr,
194 sizeof(struct spe_shadow), 205 sizeof(struct spe_shadow),
195 pgprot_val(PAGE_READONLY) | 206 shadow_flags);
196 _PAGE_NO_CACHE);
197 if (!spu_pdata(spu)->shadow) { 207 if (!spu_pdata(spu)->shadow) {
198 pr_debug("%s:%d: ioremap shadow failed\n", __func__, __LINE__); 208 pr_debug("%s:%d: ioremap shadow failed\n", __func__, __LINE__);
199 goto fail_ioremap; 209 goto fail_ioremap;
diff --git a/arch/powerpc/platforms/pseries/setup.c b/arch/powerpc/platforms/pseries/setup.c
index 3ce8a139b85d..7b01d67b4e48 100644
--- a/arch/powerpc/platforms/pseries/setup.c
+++ b/arch/powerpc/platforms/pseries/setup.c
@@ -71,6 +71,7 @@
71int CMO_PrPSP = -1; 71int CMO_PrPSP = -1;
72int CMO_SecPSP = -1; 72int CMO_SecPSP = -1;
73unsigned long CMO_PageSize = (ASM_CONST(1) << IOMMU_PAGE_SHIFT); 73unsigned long CMO_PageSize = (ASM_CONST(1) << IOMMU_PAGE_SHIFT);
74EXPORT_SYMBOL(CMO_PageSize);
74 75
75int fwnmi_active; /* TRUE if an FWNMI handler is present */ 76int fwnmi_active; /* TRUE if an FWNMI handler is present */
76 77
diff --git a/arch/powerpc/sysdev/cpm_common.c b/arch/powerpc/sysdev/cpm_common.c
index 53da8a079f96..00d3d17c84a3 100644
--- a/arch/powerpc/sysdev/cpm_common.c
+++ b/arch/powerpc/sysdev/cpm_common.c
@@ -254,15 +254,11 @@ static int cpm2_gpio32_get(struct gpio_chip *gc, unsigned int gpio)
254 return !!(in_be32(&iop->dat) & pin_mask); 254 return !!(in_be32(&iop->dat) & pin_mask);
255} 255}
256 256
257static void cpm2_gpio32_set(struct gpio_chip *gc, unsigned int gpio, int value) 257static void __cpm2_gpio32_set(struct of_mm_gpio_chip *mm_gc, u32 pin_mask,
258 int value)
258{ 259{
259 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
260 struct cpm2_gpio32_chip *cpm2_gc = to_cpm2_gpio32_chip(mm_gc); 260 struct cpm2_gpio32_chip *cpm2_gc = to_cpm2_gpio32_chip(mm_gc);
261 struct cpm2_ioports __iomem *iop = mm_gc->regs; 261 struct cpm2_ioports __iomem *iop = mm_gc->regs;
262 unsigned long flags;
263 u32 pin_mask = 1 << (31 - gpio);
264
265 spin_lock_irqsave(&cpm2_gc->lock, flags);
266 262
267 if (value) 263 if (value)
268 cpm2_gc->cpdata |= pin_mask; 264 cpm2_gc->cpdata |= pin_mask;
@@ -270,6 +266,18 @@ static void cpm2_gpio32_set(struct gpio_chip *gc, unsigned int gpio, int value)
270 cpm2_gc->cpdata &= ~pin_mask; 266 cpm2_gc->cpdata &= ~pin_mask;
271 267
272 out_be32(&iop->dat, cpm2_gc->cpdata); 268 out_be32(&iop->dat, cpm2_gc->cpdata);
269}
270
271static void cpm2_gpio32_set(struct gpio_chip *gc, unsigned int gpio, int value)
272{
273 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
274 struct cpm2_gpio32_chip *cpm2_gc = to_cpm2_gpio32_chip(mm_gc);
275 unsigned long flags;
276 u32 pin_mask = 1 << (31 - gpio);
277
278 spin_lock_irqsave(&cpm2_gc->lock, flags);
279
280 __cpm2_gpio32_set(mm_gc, pin_mask, value);
273 281
274 spin_unlock_irqrestore(&cpm2_gc->lock, flags); 282 spin_unlock_irqrestore(&cpm2_gc->lock, flags);
275} 283}
@@ -277,14 +285,17 @@ static void cpm2_gpio32_set(struct gpio_chip *gc, unsigned int gpio, int value)
277static int cpm2_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) 285static int cpm2_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
278{ 286{
279 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 287 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
288 struct cpm2_gpio32_chip *cpm2_gc = to_cpm2_gpio32_chip(mm_gc);
280 struct cpm2_ioports __iomem *iop = mm_gc->regs; 289 struct cpm2_ioports __iomem *iop = mm_gc->regs;
281 u32 pin_mask; 290 unsigned long flags;
291 u32 pin_mask = 1 << (31 - gpio);
282 292
283 pin_mask = 1 << (31 - gpio); 293 spin_lock_irqsave(&cpm2_gc->lock, flags);
284 294
285 setbits32(&iop->dir, pin_mask); 295 setbits32(&iop->dir, pin_mask);
296 __cpm2_gpio32_set(mm_gc, pin_mask, val);
286 297
287 cpm2_gpio32_set(gc, gpio, val); 298 spin_unlock_irqrestore(&cpm2_gc->lock, flags);
288 299
289 return 0; 300 return 0;
290} 301}
@@ -292,13 +303,17 @@ static int cpm2_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
292static int cpm2_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio) 303static int cpm2_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio)
293{ 304{
294 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 305 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
306 struct cpm2_gpio32_chip *cpm2_gc = to_cpm2_gpio32_chip(mm_gc);
295 struct cpm2_ioports __iomem *iop = mm_gc->regs; 307 struct cpm2_ioports __iomem *iop = mm_gc->regs;
296 u32 pin_mask; 308 unsigned long flags;
309 u32 pin_mask = 1 << (31 - gpio);
297 310
298 pin_mask = 1 << (31 - gpio); 311 spin_lock_irqsave(&cpm2_gc->lock, flags);
299 312
300 clrbits32(&iop->dir, pin_mask); 313 clrbits32(&iop->dir, pin_mask);
301 314
315 spin_unlock_irqrestore(&cpm2_gc->lock, flags);
316
302 return 0; 317 return 0;
303} 318}
304 319
diff --git a/arch/powerpc/sysdev/qe_lib/ucc_fast.c b/arch/powerpc/sysdev/qe_lib/ucc_fast.c
index 1aecb075a72e..25fbbfaa837d 100644
--- a/arch/powerpc/sysdev/qe_lib/ucc_fast.c
+++ b/arch/powerpc/sysdev/qe_lib/ucc_fast.c
@@ -208,6 +208,7 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
208 uccf->uf_regs = ioremap(uf_info->regs, sizeof(struct ucc_fast)); 208 uccf->uf_regs = ioremap(uf_info->regs, sizeof(struct ucc_fast));
209 if (uccf->uf_regs == NULL) { 209 if (uccf->uf_regs == NULL) {
210 printk(KERN_ERR "%s: Cannot map UCC registers\n", __func__); 210 printk(KERN_ERR "%s: Cannot map UCC registers\n", __func__);
211 kfree(uccf);
211 return -ENOMEM; 212 return -ENOMEM;
212 } 213 }
213 214
@@ -355,6 +356,9 @@ void ucc_fast_free(struct ucc_fast_private * uccf)
355 if (uccf->ucc_fast_rx_virtual_fifo_base_offset) 356 if (uccf->ucc_fast_rx_virtual_fifo_base_offset)
356 qe_muram_free(uccf->ucc_fast_rx_virtual_fifo_base_offset); 357 qe_muram_free(uccf->ucc_fast_rx_virtual_fifo_base_offset);
357 358
359 if (uccf->uf_regs)
360 iounmap(uccf->uf_regs);
361
358 kfree(uccf); 362 kfree(uccf);
359} 363}
360EXPORT_SYMBOL(ucc_fast_free); 364EXPORT_SYMBOL(ucc_fast_free);
diff --git a/arch/powerpc/sysdev/qe_lib/ucc_slow.c b/arch/powerpc/sysdev/qe_lib/ucc_slow.c
index a578bc77b9d5..e1d6a1340157 100644
--- a/arch/powerpc/sysdev/qe_lib/ucc_slow.c
+++ b/arch/powerpc/sysdev/qe_lib/ucc_slow.c
@@ -171,6 +171,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
171 uccs->us_regs = ioremap(us_info->regs, sizeof(struct ucc_slow)); 171 uccs->us_regs = ioremap(us_info->regs, sizeof(struct ucc_slow));
172 if (uccs->us_regs == NULL) { 172 if (uccs->us_regs == NULL) {
173 printk(KERN_ERR "%s: Cannot map UCC registers\n", __func__); 173 printk(KERN_ERR "%s: Cannot map UCC registers\n", __func__);
174 kfree(uccs);
174 return -ENOMEM; 175 return -ENOMEM;
175 } 176 }
176 177
@@ -367,10 +368,11 @@ void ucc_slow_free(struct ucc_slow_private * uccs)
367 if (uccs->tx_base_offset) 368 if (uccs->tx_base_offset)
368 qe_muram_free(uccs->tx_base_offset); 369 qe_muram_free(uccs->tx_base_offset);
369 370
370 if (uccs->us_pram) { 371 if (uccs->us_pram)
371 qe_muram_free(uccs->us_pram_offset); 372 qe_muram_free(uccs->us_pram_offset);
372 uccs->us_pram = NULL; 373
373 } 374 if (uccs->us_regs)
375 iounmap(uccs->us_regs);
374 376
375 kfree(uccs); 377 kfree(uccs);
376} 378}
diff --git a/arch/s390/kernel/vmlinux.lds.S b/arch/s390/kernel/vmlinux.lds.S
index 76c1e60c92f3..607bd67a18ce 100644
--- a/arch/s390/kernel/vmlinux.lds.S
+++ b/arch/s390/kernel/vmlinux.lds.S
@@ -55,7 +55,7 @@ SECTIONS
55 __start___ex_table = .; 55 __start___ex_table = .;
56 *(__ex_table) 56 *(__ex_table)
57 __stop___ex_table = .; 57 __stop___ex_table = .;
58 } 58 } :data
59 59
60 .data : { /* Data */ 60 .data : { /* Data */
61 DATA_DATA 61 DATA_DATA
diff --git a/arch/sparc/Makefile b/arch/sparc/Makefile
index 6668e6037af6..9592889a6fd0 100644
--- a/arch/sparc/Makefile
+++ b/arch/sparc/Makefile
@@ -52,20 +52,24 @@ endif
52export INIT_Y CORE_Y DRIVERS_Y NET_Y LIBS_Y HEAD_Y kallsyms.o 52export INIT_Y CORE_Y DRIVERS_Y NET_Y LIBS_Y HEAD_Y kallsyms.o
53 53
54# Default target 54# Default target
55all: image 55all: zImage
56 56
57boot := arch/sparc/boot 57boot := arch/sparc/boot
58 58
59image tftpboot.img: vmlinux 59image zImage tftpboot.img: vmlinux
60 $(Q)$(MAKE) $(build)=$(boot) $(boot)/$@ 60 $(Q)$(MAKE) $(build)=$(boot) $(boot)/$@
61 61
62archclean: 62archclean:
63 $(Q)$(MAKE) $(clean)=$(boot) 63 $(Q)$(MAKE) $(clean)=$(boot)
64 64
65# This is the image used for packaging
66KBUILD_IMAGE := $(boot)/zImage
67
65CLEAN_FILES += arch/$(ARCH)/boot/System.map 68CLEAN_FILES += arch/$(ARCH)/boot/System.map
66 69
67# Don't use tabs in echo arguments. 70# Don't use tabs in echo arguments.
68define archhelp 71define archhelp
69 echo '* image - kernel image ($(boot)/image)' 72 echo '* image - kernel image ($(boot)/image)'
73 echo '* zImage - stripped kernel image ($(boot)/zImage)'
70 echo ' tftpboot.img - image prepared for tftp' 74 echo ' tftpboot.img - image prepared for tftp'
71endef 75endef
diff --git a/arch/sparc/boot/Makefile b/arch/sparc/boot/Makefile
index 22d331e1e941..3e77a9f52248 100644
--- a/arch/sparc/boot/Makefile
+++ b/arch/sparc/boot/Makefile
@@ -19,6 +19,9 @@ quiet_cmd_sysmap = SYSMAP $(obj)/System.map
19 cmd_sysmap = $(CONFIG_SHELL) $(srctree)/scripts/mksysmap 19 cmd_sysmap = $(CONFIG_SHELL) $(srctree)/scripts/mksysmap
20quiet_cmd_image = LD $@ 20quiet_cmd_image = LD $@
21 cmd_image = $(LD) $(LDFLAGS) $(EXTRA_LDFLAGS) $(LDFLAGS_$(@F)) -o $@ 21 cmd_image = $(LD) $(LDFLAGS) $(EXTRA_LDFLAGS) $(LDFLAGS_$(@F)) -o $@
22quiet_cmd_strip = STRIP $@
23 cmd_strip = $(STRIP) -R .comment -R .note -K sun4u_init -K _end -K _start $(obj)/image -o $@
24
22 25
23define rule_image 26define rule_image
24 $(if $($(quiet)cmd_image), \ 27 $(if $($(quiet)cmd_image), \
@@ -49,6 +52,9 @@ LDFLAGS_image := -T arch/sparc/kernel/vmlinux.lds $(BTOBJS) \
49$(obj)/image: $(obj)/btfix.o FORCE 52$(obj)/image: $(obj)/btfix.o FORCE
50 $(call if_changed_rule,image) 53 $(call if_changed_rule,image)
51 54
55$(obj)/zImage: $(obj)/image
56 $(call if_changed,strip)
57
52$(obj)/tftpboot.img: $(obj)/piggyback $(obj)/System.map $(obj)/image FORCE 58$(obj)/tftpboot.img: $(obj)/piggyback $(obj)/System.map $(obj)/image FORCE
53 $(call if_changed,elftoaout) 59 $(call if_changed,elftoaout)
54 $(call if_changed,piggy) 60 $(call if_changed,piggy)
diff --git a/arch/sparc/include/asm/smp_32.h b/arch/sparc/include/asm/smp_32.h
index 7201752cf934..a8180e546a48 100644
--- a/arch/sparc/include/asm/smp_32.h
+++ b/arch/sparc/include/asm/smp_32.h
@@ -50,27 +50,24 @@ struct seq_file;
50void smp_bogo(struct seq_file *); 50void smp_bogo(struct seq_file *);
51void smp_info(struct seq_file *); 51void smp_info(struct seq_file *);
52 52
53BTFIXUPDEF_CALL(void, smp_cross_call, smpfunc_t, unsigned long, unsigned long, unsigned long, unsigned long, unsigned long) 53BTFIXUPDEF_CALL(void, smp_cross_call, smpfunc_t, cpumask_t, unsigned long, unsigned long, unsigned long, unsigned long)
54BTFIXUPDEF_CALL(int, __hard_smp_processor_id, void) 54BTFIXUPDEF_CALL(int, __hard_smp_processor_id, void)
55BTFIXUPDEF_BLACKBOX(hard_smp_processor_id) 55BTFIXUPDEF_BLACKBOX(hard_smp_processor_id)
56BTFIXUPDEF_BLACKBOX(load_current) 56BTFIXUPDEF_BLACKBOX(load_current)
57 57
58#define smp_cross_call(func,arg1,arg2,arg3,arg4,arg5) BTFIXUP_CALL(smp_cross_call)(func,arg1,arg2,arg3,arg4,arg5) 58#define smp_cross_call(func,mask,arg1,arg2,arg3,arg4) BTFIXUP_CALL(smp_cross_call)(func,mask,arg1,arg2,arg3,arg4)
59 59
60static inline void xc0(smpfunc_t func) { smp_cross_call(func, 0, 0, 0, 0, 0); } 60static inline void xc0(smpfunc_t func) { smp_cross_call(func, cpu_online_map, 0, 0, 0, 0); }
61static inline void xc1(smpfunc_t func, unsigned long arg1) 61static inline void xc1(smpfunc_t func, unsigned long arg1)
62{ smp_cross_call(func, arg1, 0, 0, 0, 0); } 62{ smp_cross_call(func, cpu_online_map, arg1, 0, 0, 0); }
63static inline void xc2(smpfunc_t func, unsigned long arg1, unsigned long arg2) 63static inline void xc2(smpfunc_t func, unsigned long arg1, unsigned long arg2)
64{ smp_cross_call(func, arg1, arg2, 0, 0, 0); } 64{ smp_cross_call(func, cpu_online_map, arg1, arg2, 0, 0); }
65static inline void xc3(smpfunc_t func, unsigned long arg1, unsigned long arg2, 65static inline void xc3(smpfunc_t func, unsigned long arg1, unsigned long arg2,
66 unsigned long arg3) 66 unsigned long arg3)
67{ smp_cross_call(func, arg1, arg2, arg3, 0, 0); } 67{ smp_cross_call(func, cpu_online_map, arg1, arg2, arg3, 0); }
68static inline void xc4(smpfunc_t func, unsigned long arg1, unsigned long arg2, 68static inline void xc4(smpfunc_t func, unsigned long arg1, unsigned long arg2,
69 unsigned long arg3, unsigned long arg4) 69 unsigned long arg3, unsigned long arg4)
70{ smp_cross_call(func, arg1, arg2, arg3, arg4, 0); } 70{ smp_cross_call(func, cpu_online_map, arg1, arg2, arg3, arg4); }
71static inline void xc5(smpfunc_t func, unsigned long arg1, unsigned long arg2,
72 unsigned long arg3, unsigned long arg4, unsigned long arg5)
73{ smp_cross_call(func, arg1, arg2, arg3, arg4, arg5); }
74 71
75static inline int smp_call_function(void (*func)(void *info), void *info, int wait) 72static inline int smp_call_function(void (*func)(void *info), void *info, int wait)
76{ 73{
@@ -78,6 +75,14 @@ static inline int smp_call_function(void (*func)(void *info), void *info, int wa
78 return 0; 75 return 0;
79} 76}
80 77
78static inline int smp_call_function_single(int cpuid, void (*func) (void *info),
79 void *info, int wait)
80{
81 smp_cross_call((smpfunc_t)func, cpumask_of_cpu(cpuid),
82 (unsigned long) info, 0, 0, 0);
83 return 0;
84}
85
81static inline int cpu_logical_map(int cpu) 86static inline int cpu_logical_map(int cpu)
82{ 87{
83 return cpu; 88 return cpu;
diff --git a/arch/sparc/kernel/of_device.c b/arch/sparc/kernel/of_device.c
index cc4c235c4f59..c481d45f97b7 100644
--- a/arch/sparc/kernel/of_device.c
+++ b/arch/sparc/kernel/of_device.c
@@ -70,7 +70,7 @@ struct of_bus {
70 int *addrc, int *sizec); 70 int *addrc, int *sizec);
71 int (*map)(u32 *addr, const u32 *range, 71 int (*map)(u32 *addr, const u32 *range,
72 int na, int ns, int pna); 72 int na, int ns, int pna);
73 unsigned int (*get_flags)(const u32 *addr); 73 unsigned long (*get_flags)(const u32 *addr, unsigned long);
74}; 74};
75 75
76/* 76/*
@@ -130,8 +130,10 @@ static int of_bus_default_map(u32 *addr, const u32 *range,
130 return 0; 130 return 0;
131} 131}
132 132
133static unsigned int of_bus_default_get_flags(const u32 *addr) 133static unsigned long of_bus_default_get_flags(const u32 *addr, unsigned long flags)
134{ 134{
135 if (flags)
136 return flags;
135 return IORESOURCE_MEM; 137 return IORESOURCE_MEM;
136} 138}
137 139
@@ -194,17 +196,21 @@ static int of_bus_pci_map(u32 *addr, const u32 *range,
194 return 0; 196 return 0;
195} 197}
196 198
197static unsigned int of_bus_pci_get_flags(const u32 *addr) 199static unsigned long of_bus_pci_get_flags(const u32 *addr, unsigned long flags)
198{ 200{
199 unsigned int flags = 0;
200 u32 w = addr[0]; 201 u32 w = addr[0];
201 202
203 /* For PCI, we override whatever child busses may have used. */
204 flags = 0;
202 switch((w >> 24) & 0x03) { 205 switch((w >> 24) & 0x03) {
203 case 0x01: 206 case 0x01:
204 flags |= IORESOURCE_IO; 207 flags |= IORESOURCE_IO;
208 break;
209
205 case 0x02: /* 32 bits */ 210 case 0x02: /* 32 bits */
206 case 0x03: /* 64 bits */ 211 case 0x03: /* 64 bits */
207 flags |= IORESOURCE_MEM; 212 flags |= IORESOURCE_MEM;
213 break;
208 } 214 }
209 if (w & 0x40000000) 215 if (w & 0x40000000)
210 flags |= IORESOURCE_PREFETCH; 216 flags |= IORESOURCE_PREFETCH;
@@ -362,10 +368,11 @@ static void __init build_device_resources(struct of_device *op,
362 int pna, pns; 368 int pna, pns;
363 369
364 size = of_read_addr(reg + na, ns); 370 size = of_read_addr(reg + na, ns);
365 flags = bus->get_flags(reg);
366 371
367 memcpy(addr, reg, na * 4); 372 memcpy(addr, reg, na * 4);
368 373
374 flags = bus->get_flags(reg, 0);
375
369 /* If the immediate parent has no ranges property to apply, 376 /* If the immediate parent has no ranges property to apply,
370 * just use a 1<->1 mapping. 377 * just use a 1<->1 mapping.
371 */ 378 */
@@ -393,6 +400,8 @@ static void __init build_device_resources(struct of_device *op,
393 dna, dns, pna)) 400 dna, dns, pna))
394 break; 401 break;
395 402
403 flags = pbus->get_flags(addr, flags);
404
396 dna = pna; 405 dna = pna;
397 dns = pns; 406 dns = pns;
398 dbus = pbus; 407 dbus = pbus;
diff --git a/arch/sparc/kernel/sun4d_smp.c b/arch/sparc/kernel/sun4d_smp.c
index dfde77ff0848..69596402a500 100644
--- a/arch/sparc/kernel/sun4d_smp.c
+++ b/arch/sparc/kernel/sun4d_smp.c
@@ -262,8 +262,9 @@ static struct smp_funcall {
262static DEFINE_SPINLOCK(cross_call_lock); 262static DEFINE_SPINLOCK(cross_call_lock);
263 263
264/* Cross calls must be serialized, at least currently. */ 264/* Cross calls must be serialized, at least currently. */
265void smp4d_cross_call(smpfunc_t func, unsigned long arg1, unsigned long arg2, 265static void smp4d_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1,
266 unsigned long arg3, unsigned long arg4, unsigned long arg5) 266 unsigned long arg2, unsigned long arg3,
267 unsigned long arg4)
267{ 268{
268 if(smp_processors_ready) { 269 if(smp_processors_ready) {
269 register int high = smp_highest_cpu; 270 register int high = smp_highest_cpu;
@@ -278,7 +279,7 @@ void smp4d_cross_call(smpfunc_t func, unsigned long arg1, unsigned long arg2,
278 register unsigned long a2 asm("i2") = arg2; 279 register unsigned long a2 asm("i2") = arg2;
279 register unsigned long a3 asm("i3") = arg3; 280 register unsigned long a3 asm("i3") = arg3;
280 register unsigned long a4 asm("i4") = arg4; 281 register unsigned long a4 asm("i4") = arg4;
281 register unsigned long a5 asm("i5") = arg5; 282 register unsigned long a5 asm("i5") = 0;
282 283
283 __asm__ __volatile__( 284 __asm__ __volatile__(
284 "std %0, [%6]\n\t" 285 "std %0, [%6]\n\t"
@@ -290,11 +291,10 @@ void smp4d_cross_call(smpfunc_t func, unsigned long arg1, unsigned long arg2,
290 291
291 /* Init receive/complete mapping, plus fire the IPI's off. */ 292 /* Init receive/complete mapping, plus fire the IPI's off. */
292 { 293 {
293 cpumask_t mask;
294 register int i; 294 register int i;
295 295
296 mask = cpumask_of_cpu(hard_smp4d_processor_id()); 296 cpu_clear(smp_processor_id(), mask);
297 cpus_andnot(mask, cpu_online_map, mask); 297 cpus_and(mask, cpu_online_map, mask);
298 for(i = 0; i <= high; i++) { 298 for(i = 0; i <= high; i++) {
299 if (cpu_isset(i, mask)) { 299 if (cpu_isset(i, mask)) {
300 ccall_info.processors_in[i] = 0; 300 ccall_info.processors_in[i] = 0;
@@ -309,12 +309,16 @@ void smp4d_cross_call(smpfunc_t func, unsigned long arg1, unsigned long arg2,
309 309
310 i = 0; 310 i = 0;
311 do { 311 do {
312 if (!cpu_isset(i, mask))
313 continue;
312 while(!ccall_info.processors_in[i]) 314 while(!ccall_info.processors_in[i])
313 barrier(); 315 barrier();
314 } while(++i <= high); 316 } while(++i <= high);
315 317
316 i = 0; 318 i = 0;
317 do { 319 do {
320 if (!cpu_isset(i, mask))
321 continue;
318 while(!ccall_info.processors_out[i]) 322 while(!ccall_info.processors_out[i])
319 barrier(); 323 barrier();
320 } while(++i <= high); 324 } while(++i <= high);
diff --git a/arch/sparc/kernel/sun4m_smp.c b/arch/sparc/kernel/sun4m_smp.c
index 406ac1abc83a..a14a76ac7f36 100644
--- a/arch/sparc/kernel/sun4m_smp.c
+++ b/arch/sparc/kernel/sun4m_smp.c
@@ -244,9 +244,9 @@ static struct smp_funcall {
244static DEFINE_SPINLOCK(cross_call_lock); 244static DEFINE_SPINLOCK(cross_call_lock);
245 245
246/* Cross calls must be serialized, at least currently. */ 246/* Cross calls must be serialized, at least currently. */
247static void smp4m_cross_call(smpfunc_t func, unsigned long arg1, 247static void smp4m_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1,
248 unsigned long arg2, unsigned long arg3, 248 unsigned long arg2, unsigned long arg3,
249 unsigned long arg4, unsigned long arg5) 249 unsigned long arg4)
250{ 250{
251 register int ncpus = SUN4M_NCPUS; 251 register int ncpus = SUN4M_NCPUS;
252 unsigned long flags; 252 unsigned long flags;
@@ -259,14 +259,14 @@ static void smp4m_cross_call(smpfunc_t func, unsigned long arg1,
259 ccall_info.arg2 = arg2; 259 ccall_info.arg2 = arg2;
260 ccall_info.arg3 = arg3; 260 ccall_info.arg3 = arg3;
261 ccall_info.arg4 = arg4; 261 ccall_info.arg4 = arg4;
262 ccall_info.arg5 = arg5; 262 ccall_info.arg5 = 0;
263 263
264 /* Init receive/complete mapping, plus fire the IPI's off. */ 264 /* Init receive/complete mapping, plus fire the IPI's off. */
265 { 265 {
266 cpumask_t mask = cpu_online_map;
267 register int i; 266 register int i;
268 267
269 cpu_clear(smp_processor_id(), mask); 268 cpu_clear(smp_processor_id(), mask);
269 cpus_and(mask, cpu_online_map, mask);
270 for(i = 0; i < ncpus; i++) { 270 for(i = 0; i < ncpus; i++) {
271 if (cpu_isset(i, mask)) { 271 if (cpu_isset(i, mask)) {
272 ccall_info.processors_in[i] = 0; 272 ccall_info.processors_in[i] = 0;
@@ -284,12 +284,16 @@ static void smp4m_cross_call(smpfunc_t func, unsigned long arg1,
284 284
285 i = 0; 285 i = 0;
286 do { 286 do {
287 if (!cpu_isset(i, mask))
288 continue;
287 while(!ccall_info.processors_in[i]) 289 while(!ccall_info.processors_in[i])
288 barrier(); 290 barrier();
289 } while(++i < ncpus); 291 } while(++i < ncpus);
290 292
291 i = 0; 293 i = 0;
292 do { 294 do {
295 if (!cpu_isset(i, mask))
296 continue;
293 while(!ccall_info.processors_out[i]) 297 while(!ccall_info.processors_out[i])
294 barrier(); 298 barrier();
295 } while(++i < ncpus); 299 } while(++i < ncpus);
diff --git a/arch/sparc64/Kconfig b/arch/sparc64/Kconfig
index 923a98959fa7..36b4b7ab9cfb 100644
--- a/arch/sparc64/Kconfig
+++ b/arch/sparc64/Kconfig
@@ -231,6 +231,7 @@ endmenu
231 231
232config NUMA 232config NUMA
233 bool "NUMA support" 233 bool "NUMA support"
234 depends on SMP
234 235
235config NODES_SHIFT 236config NODES_SHIFT
236 int 237 int
diff --git a/arch/sparc64/kernel/of_device.c b/arch/sparc64/kernel/of_device.c
index f8b50cbf4bf7..f845f150f565 100644
--- a/arch/sparc64/kernel/of_device.c
+++ b/arch/sparc64/kernel/of_device.c
@@ -96,7 +96,7 @@ struct of_bus {
96 int *addrc, int *sizec); 96 int *addrc, int *sizec);
97 int (*map)(u32 *addr, const u32 *range, 97 int (*map)(u32 *addr, const u32 *range,
98 int na, int ns, int pna); 98 int na, int ns, int pna);
99 unsigned int (*get_flags)(const u32 *addr); 99 unsigned long (*get_flags)(const u32 *addr, unsigned long);
100}; 100};
101 101
102/* 102/*
@@ -156,8 +156,10 @@ static int of_bus_default_map(u32 *addr, const u32 *range,
156 return 0; 156 return 0;
157} 157}
158 158
159static unsigned int of_bus_default_get_flags(const u32 *addr) 159static unsigned long of_bus_default_get_flags(const u32 *addr, unsigned long flags)
160{ 160{
161 if (flags)
162 return flags;
161 return IORESOURCE_MEM; 163 return IORESOURCE_MEM;
162} 164}
163 165
@@ -249,17 +251,21 @@ static int of_bus_pci_map(u32 *addr, const u32 *range,
249 return 0; 251 return 0;
250} 252}
251 253
252static unsigned int of_bus_pci_get_flags(const u32 *addr) 254static unsigned long of_bus_pci_get_flags(const u32 *addr, unsigned long flags)
253{ 255{
254 unsigned int flags = 0;
255 u32 w = addr[0]; 256 u32 w = addr[0];
256 257
258 /* For PCI, we override whatever child busses may have used. */
259 flags = 0;
257 switch((w >> 24) & 0x03) { 260 switch((w >> 24) & 0x03) {
258 case 0x01: 261 case 0x01:
259 flags |= IORESOURCE_IO; 262 flags |= IORESOURCE_IO;
263 break;
264
260 case 0x02: /* 32 bits */ 265 case 0x02: /* 32 bits */
261 case 0x03: /* 64 bits */ 266 case 0x03: /* 64 bits */
262 flags |= IORESOURCE_MEM; 267 flags |= IORESOURCE_MEM;
268 break;
263 } 269 }
264 if (w & 0x40000000) 270 if (w & 0x40000000)
265 flags |= IORESOURCE_PREFETCH; 271 flags |= IORESOURCE_PREFETCH;
@@ -478,10 +484,10 @@ static void __init build_device_resources(struct of_device *op,
478 int pna, pns; 484 int pna, pns;
479 485
480 size = of_read_addr(reg + na, ns); 486 size = of_read_addr(reg + na, ns);
481 flags = bus->get_flags(reg);
482
483 memcpy(addr, reg, na * 4); 487 memcpy(addr, reg, na * 4);
484 488
489 flags = bus->get_flags(addr, 0);
490
485 if (use_1to1_mapping(pp)) { 491 if (use_1to1_mapping(pp)) {
486 result = of_read_addr(addr, na); 492 result = of_read_addr(addr, na);
487 goto build_res; 493 goto build_res;
@@ -506,6 +512,8 @@ static void __init build_device_resources(struct of_device *op,
506 dna, dns, pna)) 512 dna, dns, pna))
507 break; 513 break;
508 514
515 flags = pbus->get_flags(addr, flags);
516
509 dna = pna; 517 dna = pna;
510 dns = pns; 518 dns = pns;
511 dbus = pbus; 519 dbus = pbus;
diff --git a/arch/sparc64/mm/init.c b/arch/sparc64/mm/init.c
index b4aeb0f696dc..a41df7bef035 100644
--- a/arch/sparc64/mm/init.c
+++ b/arch/sparc64/mm/init.c
@@ -1843,7 +1843,7 @@ static int pavail_rescan_ents __initdata;
1843 * memory list again, and make sure it provides at least as much 1843 * memory list again, and make sure it provides at least as much
1844 * memory as 'pavail' does. 1844 * memory as 'pavail' does.
1845 */ 1845 */
1846static void setup_valid_addr_bitmap_from_pavail(void) 1846static void __init setup_valid_addr_bitmap_from_pavail(void)
1847{ 1847{
1848 int i; 1848 int i;
1849 1849
diff --git a/arch/x86/configs/i386_defconfig b/arch/x86/configs/i386_defconfig
index 4d73f53287b6..104275e191a8 100644
--- a/arch/x86/configs/i386_defconfig
+++ b/arch/x86/configs/i386_defconfig
@@ -1,13 +1,13 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc1 3# Linux kernel version: 2.6.27-rc4
4# Sun May 4 19:59:02 2008 4# Mon Aug 25 15:04:00 2008
5# 5#
6# CONFIG_64BIT is not set 6# CONFIG_64BIT is not set
7CONFIG_X86_32=y 7CONFIG_X86_32=y
8# CONFIG_X86_64 is not set 8# CONFIG_X86_64 is not set
9CONFIG_X86=y 9CONFIG_X86=y
10CONFIG_DEFCONFIG_LIST="arch/x86/configs/i386_defconfig" 10CONFIG_ARCH_DEFCONFIG="arch/x86/configs/i386_defconfig"
11# CONFIG_GENERIC_LOCKBREAK is not set 11# CONFIG_GENERIC_LOCKBREAK is not set
12CONFIG_GENERIC_TIME=y 12CONFIG_GENERIC_TIME=y
13CONFIG_GENERIC_CMOS_UPDATE=y 13CONFIG_GENERIC_CMOS_UPDATE=y
@@ -53,6 +53,7 @@ CONFIG_X86_HT=y
53CONFIG_X86_BIOS_REBOOT=y 53CONFIG_X86_BIOS_REBOOT=y
54CONFIG_X86_TRAMPOLINE=y 54CONFIG_X86_TRAMPOLINE=y
55CONFIG_KTIME_SCALAR=y 55CONFIG_KTIME_SCALAR=y
56CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
56 57
57# 58#
58# General setup 59# General setup
@@ -82,6 +83,7 @@ CONFIG_CGROUPS=y
82CONFIG_CGROUP_NS=y 83CONFIG_CGROUP_NS=y
83# CONFIG_CGROUP_DEVICE is not set 84# CONFIG_CGROUP_DEVICE is not set
84CONFIG_CPUSETS=y 85CONFIG_CPUSETS=y
86CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y
85CONFIG_GROUP_SCHED=y 87CONFIG_GROUP_SCHED=y
86CONFIG_FAIR_GROUP_SCHED=y 88CONFIG_FAIR_GROUP_SCHED=y
87# CONFIG_RT_GROUP_SCHED is not set 89# CONFIG_RT_GROUP_SCHED is not set
@@ -105,7 +107,6 @@ CONFIG_SYSCTL=y
105# CONFIG_EMBEDDED is not set 107# CONFIG_EMBEDDED is not set
106CONFIG_UID16=y 108CONFIG_UID16=y
107CONFIG_SYSCTL_SYSCALL=y 109CONFIG_SYSCTL_SYSCALL=y
108CONFIG_SYSCTL_SYSCALL_CHECK=y
109CONFIG_KALLSYMS=y 110CONFIG_KALLSYMS=y
110CONFIG_KALLSYMS_ALL=y 111CONFIG_KALLSYMS_ALL=y
111CONFIG_KALLSYMS_EXTRA_PASS=y 112CONFIG_KALLSYMS_EXTRA_PASS=y
@@ -113,6 +114,7 @@ CONFIG_HOTPLUG=y
113CONFIG_PRINTK=y 114CONFIG_PRINTK=y
114CONFIG_BUG=y 115CONFIG_BUG=y
115CONFIG_ELF_CORE=y 116CONFIG_ELF_CORE=y
117CONFIG_PCSPKR_PLATFORM=y
116# CONFIG_COMPAT_BRK is not set 118# CONFIG_COMPAT_BRK is not set
117CONFIG_BASE_FULL=y 119CONFIG_BASE_FULL=y
118CONFIG_FUTEX=y 120CONFIG_FUTEX=y
@@ -132,27 +134,35 @@ CONFIG_MARKERS=y
132# CONFIG_OPROFILE is not set 134# CONFIG_OPROFILE is not set
133CONFIG_HAVE_OPROFILE=y 135CONFIG_HAVE_OPROFILE=y
134CONFIG_KPROBES=y 136CONFIG_KPROBES=y
137CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
135CONFIG_KRETPROBES=y 138CONFIG_KRETPROBES=y
139CONFIG_HAVE_IOREMAP_PROT=y
136CONFIG_HAVE_KPROBES=y 140CONFIG_HAVE_KPROBES=y
137CONFIG_HAVE_KRETPROBES=y 141CONFIG_HAVE_KRETPROBES=y
142# CONFIG_HAVE_ARCH_TRACEHOOK is not set
138# CONFIG_HAVE_DMA_ATTRS is not set 143# CONFIG_HAVE_DMA_ATTRS is not set
144CONFIG_USE_GENERIC_SMP_HELPERS=y
145# CONFIG_HAVE_CLK is not set
139CONFIG_PROC_PAGE_MONITOR=y 146CONFIG_PROC_PAGE_MONITOR=y
147CONFIG_HAVE_GENERIC_DMA_COHERENT=y
140CONFIG_SLABINFO=y 148CONFIG_SLABINFO=y
141CONFIG_RT_MUTEXES=y 149CONFIG_RT_MUTEXES=y
142# CONFIG_TINY_SHMEM is not set 150# CONFIG_TINY_SHMEM is not set
143CONFIG_BASE_SMALL=0 151CONFIG_BASE_SMALL=0
144CONFIG_MODULES=y 152CONFIG_MODULES=y
153# CONFIG_MODULE_FORCE_LOAD is not set
145CONFIG_MODULE_UNLOAD=y 154CONFIG_MODULE_UNLOAD=y
146CONFIG_MODULE_FORCE_UNLOAD=y 155CONFIG_MODULE_FORCE_UNLOAD=y
147# CONFIG_MODVERSIONS is not set 156# CONFIG_MODVERSIONS is not set
148# CONFIG_MODULE_SRCVERSION_ALL is not set 157# CONFIG_MODULE_SRCVERSION_ALL is not set
149# CONFIG_KMOD is not set 158CONFIG_KMOD=y
150CONFIG_STOP_MACHINE=y 159CONFIG_STOP_MACHINE=y
151CONFIG_BLOCK=y 160CONFIG_BLOCK=y
152# CONFIG_LBD is not set 161# CONFIG_LBD is not set
153CONFIG_BLK_DEV_IO_TRACE=y 162CONFIG_BLK_DEV_IO_TRACE=y
154# CONFIG_LSF is not set 163# CONFIG_LSF is not set
155CONFIG_BLK_DEV_BSG=y 164CONFIG_BLK_DEV_BSG=y
165# CONFIG_BLK_DEV_INTEGRITY is not set
156 166
157# 167#
158# IO Schedulers 168# IO Schedulers
@@ -176,19 +186,17 @@ CONFIG_NO_HZ=y
176CONFIG_HIGH_RES_TIMERS=y 186CONFIG_HIGH_RES_TIMERS=y
177CONFIG_GENERIC_CLOCKEVENTS_BUILD=y 187CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
178CONFIG_SMP=y 188CONFIG_SMP=y
189CONFIG_X86_FIND_SMP_CONFIG=y
190CONFIG_X86_MPPARSE=y
179CONFIG_X86_PC=y 191CONFIG_X86_PC=y
180# CONFIG_X86_ELAN is not set 192# CONFIG_X86_ELAN is not set
181# CONFIG_X86_VOYAGER is not set 193# CONFIG_X86_VOYAGER is not set
182# CONFIG_X86_NUMAQ is not set
183# CONFIG_X86_SUMMIT is not set
184# CONFIG_X86_BIGSMP is not set
185# CONFIG_X86_VISWS is not set
186# CONFIG_X86_GENERICARCH is not set 194# CONFIG_X86_GENERICARCH is not set
187# CONFIG_X86_ES7000 is not set
188# CONFIG_X86_RDC321X is not set
189# CONFIG_X86_VSMP is not set 195# CONFIG_X86_VSMP is not set
196# CONFIG_X86_RDC321X is not set
190CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 197CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
191# CONFIG_PARAVIRT_GUEST is not set 198# CONFIG_PARAVIRT_GUEST is not set
199# CONFIG_MEMTEST is not set
192# CONFIG_M386 is not set 200# CONFIG_M386 is not set
193# CONFIG_M486 is not set 201# CONFIG_M486 is not set
194# CONFIG_M586 is not set 202# CONFIG_M586 is not set
@@ -215,21 +223,19 @@ CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
215# CONFIG_MPSC is not set 223# CONFIG_MPSC is not set
216CONFIG_MCORE2=y 224CONFIG_MCORE2=y
217# CONFIG_GENERIC_CPU is not set 225# CONFIG_GENERIC_CPU is not set
218# CONFIG_X86_GENERIC is not set 226CONFIG_X86_GENERIC=y
219CONFIG_X86_CPU=y 227CONFIG_X86_CPU=y
220CONFIG_X86_CMPXCHG=y 228CONFIG_X86_CMPXCHG=y
221CONFIG_X86_L1_CACHE_SHIFT=6 229CONFIG_X86_L1_CACHE_SHIFT=7
222CONFIG_X86_XADD=y 230CONFIG_X86_XADD=y
223CONFIG_X86_WP_WORKS_OK=y 231CONFIG_X86_WP_WORKS_OK=y
224CONFIG_X86_INVLPG=y 232CONFIG_X86_INVLPG=y
225CONFIG_X86_BSWAP=y 233CONFIG_X86_BSWAP=y
226CONFIG_X86_POPAD_OK=y 234CONFIG_X86_POPAD_OK=y
227CONFIG_X86_GOOD_APIC=y
228CONFIG_X86_INTEL_USERCOPY=y 235CONFIG_X86_INTEL_USERCOPY=y
229CONFIG_X86_USE_PPRO_CHECKSUM=y 236CONFIG_X86_USE_PPRO_CHECKSUM=y
230CONFIG_X86_P6_NOP=y
231CONFIG_X86_TSC=y 237CONFIG_X86_TSC=y
232CONFIG_X86_MINIMUM_CPU_FAMILY=6 238CONFIG_X86_MINIMUM_CPU_FAMILY=4
233CONFIG_X86_DEBUGCTLMSR=y 239CONFIG_X86_DEBUGCTLMSR=y
234CONFIG_HPET_TIMER=y 240CONFIG_HPET_TIMER=y
235CONFIG_HPET_EMULATE_RTC=y 241CONFIG_HPET_EMULATE_RTC=y
@@ -247,7 +253,7 @@ CONFIG_X86_IO_APIC=y
247CONFIG_VM86=y 253CONFIG_VM86=y
248# CONFIG_TOSHIBA is not set 254# CONFIG_TOSHIBA is not set
249# CONFIG_I8K is not set 255# CONFIG_I8K is not set
250# CONFIG_X86_REBOOTFIXUPS is not set 256CONFIG_X86_REBOOTFIXUPS=y
251# CONFIG_MICROCODE is not set 257# CONFIG_MICROCODE is not set
252CONFIG_X86_MSR=y 258CONFIG_X86_MSR=y
253CONFIG_X86_CPUID=y 259CONFIG_X86_CPUID=y
@@ -256,32 +262,28 @@ CONFIG_HIGHMEM4G=y
256# CONFIG_HIGHMEM64G is not set 262# CONFIG_HIGHMEM64G is not set
257CONFIG_PAGE_OFFSET=0xC0000000 263CONFIG_PAGE_OFFSET=0xC0000000
258CONFIG_HIGHMEM=y 264CONFIG_HIGHMEM=y
259CONFIG_NEED_NODE_MEMMAP_SIZE=y
260CONFIG_ARCH_FLATMEM_ENABLE=y 265CONFIG_ARCH_FLATMEM_ENABLE=y
261CONFIG_ARCH_SPARSEMEM_ENABLE=y 266CONFIG_ARCH_SPARSEMEM_ENABLE=y
262CONFIG_ARCH_SELECT_MEMORY_MODEL=y 267CONFIG_ARCH_SELECT_MEMORY_MODEL=y
263CONFIG_SELECT_MEMORY_MODEL=y 268CONFIG_SELECT_MEMORY_MODEL=y
264# CONFIG_FLATMEM_MANUAL is not set 269CONFIG_FLATMEM_MANUAL=y
265# CONFIG_DISCONTIGMEM_MANUAL is not set 270# CONFIG_DISCONTIGMEM_MANUAL is not set
266CONFIG_SPARSEMEM_MANUAL=y 271# CONFIG_SPARSEMEM_MANUAL is not set
267CONFIG_SPARSEMEM=y 272CONFIG_FLATMEM=y
268CONFIG_HAVE_MEMORY_PRESENT=y 273CONFIG_FLAT_NODE_MEM_MAP=y
269CONFIG_SPARSEMEM_STATIC=y 274CONFIG_SPARSEMEM_STATIC=y
270# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set 275# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
271
272#
273# Memory hotplug is currently incompatible with Software Suspend
274#
275CONFIG_PAGEFLAGS_EXTENDED=y 276CONFIG_PAGEFLAGS_EXTENDED=y
276CONFIG_SPLIT_PTLOCK_CPUS=4 277CONFIG_SPLIT_PTLOCK_CPUS=4
277CONFIG_RESOURCES_64BIT=y 278CONFIG_RESOURCES_64BIT=y
278CONFIG_ZONE_DMA_FLAG=1 279CONFIG_ZONE_DMA_FLAG=1
279CONFIG_BOUNCE=y 280CONFIG_BOUNCE=y
280CONFIG_VIRT_TO_BUS=y 281CONFIG_VIRT_TO_BUS=y
281# CONFIG_HIGHPTE is not set 282CONFIG_HIGHPTE=y
282# CONFIG_MATH_EMULATION is not set 283# CONFIG_MATH_EMULATION is not set
283CONFIG_MTRR=y 284CONFIG_MTRR=y
284# CONFIG_X86_PAT is not set 285# CONFIG_MTRR_SANITIZER is not set
286CONFIG_X86_PAT=y
285CONFIG_EFI=y 287CONFIG_EFI=y
286# CONFIG_IRQBALANCE is not set 288# CONFIG_IRQBALANCE is not set
287CONFIG_SECCOMP=y 289CONFIG_SECCOMP=y
@@ -293,6 +295,7 @@ CONFIG_HZ=1000
293CONFIG_SCHED_HRTICK=y 295CONFIG_SCHED_HRTICK=y
294CONFIG_KEXEC=y 296CONFIG_KEXEC=y
295CONFIG_CRASH_DUMP=y 297CONFIG_CRASH_DUMP=y
298# CONFIG_KEXEC_JUMP is not set
296CONFIG_PHYSICAL_START=0x1000000 299CONFIG_PHYSICAL_START=0x1000000
297CONFIG_RELOCATABLE=y 300CONFIG_RELOCATABLE=y
298CONFIG_PHYSICAL_ALIGN=0x200000 301CONFIG_PHYSICAL_ALIGN=0x200000
@@ -312,6 +315,7 @@ CONFIG_PM_TRACE_RTC=y
312CONFIG_PM_SLEEP_SMP=y 315CONFIG_PM_SLEEP_SMP=y
313CONFIG_PM_SLEEP=y 316CONFIG_PM_SLEEP=y
314CONFIG_SUSPEND=y 317CONFIG_SUSPEND=y
318# CONFIG_PM_TEST_SUSPEND is not set
315CONFIG_SUSPEND_FREEZER=y 319CONFIG_SUSPEND_FREEZER=y
316CONFIG_HIBERNATION=y 320CONFIG_HIBERNATION=y
317CONFIG_PM_STD_PARTITION="" 321CONFIG_PM_STD_PARTITION=""
@@ -337,6 +341,7 @@ CONFIG_ACPI_THERMAL=y
337CONFIG_ACPI_BLACKLIST_YEAR=0 341CONFIG_ACPI_BLACKLIST_YEAR=0
338# CONFIG_ACPI_DEBUG is not set 342# CONFIG_ACPI_DEBUG is not set
339CONFIG_ACPI_EC=y 343CONFIG_ACPI_EC=y
344# CONFIG_ACPI_PCI_SLOT is not set
340CONFIG_ACPI_POWER=y 345CONFIG_ACPI_POWER=y
341CONFIG_ACPI_SYSTEM=y 346CONFIG_ACPI_SYSTEM=y
342CONFIG_X86_PM_TIMER=y 347CONFIG_X86_PM_TIMER=y
@@ -395,8 +400,8 @@ CONFIG_PCI=y
395# CONFIG_PCI_GOBIOS is not set 400# CONFIG_PCI_GOBIOS is not set
396# CONFIG_PCI_GOMMCONFIG is not set 401# CONFIG_PCI_GOMMCONFIG is not set
397# CONFIG_PCI_GODIRECT is not set 402# CONFIG_PCI_GODIRECT is not set
398CONFIG_PCI_GOANY=y
399# CONFIG_PCI_GOOLPC is not set 403# CONFIG_PCI_GOOLPC is not set
404CONFIG_PCI_GOANY=y
400CONFIG_PCI_BIOS=y 405CONFIG_PCI_BIOS=y
401CONFIG_PCI_DIRECT=y 406CONFIG_PCI_DIRECT=y
402CONFIG_PCI_MMCONFIG=y 407CONFIG_PCI_MMCONFIG=y
@@ -448,10 +453,6 @@ CONFIG_HOTPLUG_PCI=y
448CONFIG_BINFMT_ELF=y 453CONFIG_BINFMT_ELF=y
449# CONFIG_BINFMT_AOUT is not set 454# CONFIG_BINFMT_AOUT is not set
450CONFIG_BINFMT_MISC=y 455CONFIG_BINFMT_MISC=y
451
452#
453# Networking
454#
455CONFIG_NET=y 456CONFIG_NET=y
456 457
457# 458#
@@ -475,7 +476,10 @@ CONFIG_IP_FIB_HASH=y
475CONFIG_IP_MULTIPLE_TABLES=y 476CONFIG_IP_MULTIPLE_TABLES=y
476CONFIG_IP_ROUTE_MULTIPATH=y 477CONFIG_IP_ROUTE_MULTIPATH=y
477CONFIG_IP_ROUTE_VERBOSE=y 478CONFIG_IP_ROUTE_VERBOSE=y
478# CONFIG_IP_PNP is not set 479CONFIG_IP_PNP=y
480CONFIG_IP_PNP_DHCP=y
481CONFIG_IP_PNP_BOOTP=y
482CONFIG_IP_PNP_RARP=y
479# CONFIG_NET_IPIP is not set 483# CONFIG_NET_IPIP is not set
480# CONFIG_NET_IPGRE is not set 484# CONFIG_NET_IPGRE is not set
481CONFIG_IP_MROUTE=y 485CONFIG_IP_MROUTE=y
@@ -618,7 +622,6 @@ CONFIG_NET_SCHED=y
618# CONFIG_NET_SCH_HTB is not set 622# CONFIG_NET_SCH_HTB is not set
619# CONFIG_NET_SCH_HFSC is not set 623# CONFIG_NET_SCH_HFSC is not set
620# CONFIG_NET_SCH_PRIO is not set 624# CONFIG_NET_SCH_PRIO is not set
621# CONFIG_NET_SCH_RR is not set
622# CONFIG_NET_SCH_RED is not set 625# CONFIG_NET_SCH_RED is not set
623# CONFIG_NET_SCH_SFQ is not set 626# CONFIG_NET_SCH_SFQ is not set
624# CONFIG_NET_SCH_TEQL is not set 627# CONFIG_NET_SCH_TEQL is not set
@@ -680,28 +683,19 @@ CONFIG_FIB_RULES=y
680CONFIG_CFG80211=y 683CONFIG_CFG80211=y
681CONFIG_NL80211=y 684CONFIG_NL80211=y
682CONFIG_WIRELESS_EXT=y 685CONFIG_WIRELESS_EXT=y
686CONFIG_WIRELESS_EXT_SYSFS=y
683CONFIG_MAC80211=y 687CONFIG_MAC80211=y
684 688
685# 689#
686# Rate control algorithm selection 690# Rate control algorithm selection
687# 691#
692CONFIG_MAC80211_RC_PID=y
688CONFIG_MAC80211_RC_DEFAULT_PID=y 693CONFIG_MAC80211_RC_DEFAULT_PID=y
689# CONFIG_MAC80211_RC_DEFAULT_NONE is not set
690
691#
692# Selecting 'y' for an algorithm will
693#
694
695#
696# build the algorithm into mac80211.
697#
698CONFIG_MAC80211_RC_DEFAULT="pid" 694CONFIG_MAC80211_RC_DEFAULT="pid"
699CONFIG_MAC80211_RC_PID=y
700# CONFIG_MAC80211_MESH is not set 695# CONFIG_MAC80211_MESH is not set
701CONFIG_MAC80211_LEDS=y 696CONFIG_MAC80211_LEDS=y
702# CONFIG_MAC80211_DEBUGFS is not set 697# CONFIG_MAC80211_DEBUGFS is not set
703# CONFIG_MAC80211_DEBUG_PACKET_ALIGNMENT is not set 698# CONFIG_MAC80211_DEBUG_MENU is not set
704# CONFIG_MAC80211_DEBUG is not set
705# CONFIG_IEEE80211 is not set 699# CONFIG_IEEE80211 is not set
706# CONFIG_RFKILL is not set 700# CONFIG_RFKILL is not set
707# CONFIG_NET_9P is not set 701# CONFIG_NET_9P is not set
@@ -717,6 +711,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
717CONFIG_STANDALONE=y 711CONFIG_STANDALONE=y
718CONFIG_PREVENT_FIRMWARE_BUILD=y 712CONFIG_PREVENT_FIRMWARE_BUILD=y
719CONFIG_FW_LOADER=y 713CONFIG_FW_LOADER=y
714CONFIG_FIRMWARE_IN_KERNEL=y
715CONFIG_EXTRA_FIRMWARE=""
720# CONFIG_DEBUG_DRIVER is not set 716# CONFIG_DEBUG_DRIVER is not set
721CONFIG_DEBUG_DEVRES=y 717CONFIG_DEBUG_DEVRES=y
722# CONFIG_SYS_HYPERVISOR is not set 718# CONFIG_SYS_HYPERVISOR is not set
@@ -749,6 +745,7 @@ CONFIG_BLK_DEV_RAM_SIZE=16384
749# CONFIG_BLK_DEV_XIP is not set 745# CONFIG_BLK_DEV_XIP is not set
750# CONFIG_CDROM_PKTCDVD is not set 746# CONFIG_CDROM_PKTCDVD is not set
751# CONFIG_ATA_OVER_ETH is not set 747# CONFIG_ATA_OVER_ETH is not set
748# CONFIG_BLK_DEV_HD is not set
752CONFIG_MISC_DEVICES=y 749CONFIG_MISC_DEVICES=y
753# CONFIG_IBM_ASM is not set 750# CONFIG_IBM_ASM is not set
754# CONFIG_PHANTOM is not set 751# CONFIG_PHANTOM is not set
@@ -760,10 +757,12 @@ CONFIG_MISC_DEVICES=y
760# CONFIG_FUJITSU_LAPTOP is not set 757# CONFIG_FUJITSU_LAPTOP is not set
761# CONFIG_TC1100_WMI is not set 758# CONFIG_TC1100_WMI is not set
762# CONFIG_MSI_LAPTOP is not set 759# CONFIG_MSI_LAPTOP is not set
760# CONFIG_COMPAL_LAPTOP is not set
763# CONFIG_SONY_LAPTOP is not set 761# CONFIG_SONY_LAPTOP is not set
764# CONFIG_THINKPAD_ACPI is not set 762# CONFIG_THINKPAD_ACPI is not set
765# CONFIG_INTEL_MENLOW is not set 763# CONFIG_INTEL_MENLOW is not set
766# CONFIG_ENCLOSURE_SERVICES is not set 764# CONFIG_ENCLOSURE_SERVICES is not set
765# CONFIG_HP_ILO is not set
767CONFIG_HAVE_IDE=y 766CONFIG_HAVE_IDE=y
768# CONFIG_IDE is not set 767# CONFIG_IDE is not set
769 768
@@ -802,12 +801,13 @@ CONFIG_SCSI_WAIT_SCAN=m
802# 801#
803CONFIG_SCSI_SPI_ATTRS=y 802CONFIG_SCSI_SPI_ATTRS=y
804# CONFIG_SCSI_FC_ATTRS is not set 803# CONFIG_SCSI_FC_ATTRS is not set
805# CONFIG_SCSI_ISCSI_ATTRS is not set 804CONFIG_SCSI_ISCSI_ATTRS=y
806# CONFIG_SCSI_SAS_ATTRS is not set 805# CONFIG_SCSI_SAS_ATTRS is not set
807# CONFIG_SCSI_SAS_LIBSAS is not set 806# CONFIG_SCSI_SAS_LIBSAS is not set
808# CONFIG_SCSI_SRP_ATTRS is not set 807# CONFIG_SCSI_SRP_ATTRS is not set
809# CONFIG_SCSI_LOWLEVEL is not set 808# CONFIG_SCSI_LOWLEVEL is not set
810# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set 809# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
810# CONFIG_SCSI_DH is not set
811CONFIG_ATA=y 811CONFIG_ATA=y
812# CONFIG_ATA_NONSTANDARD is not set 812# CONFIG_ATA_NONSTANDARD is not set
813CONFIG_ATA_ACPI=y 813CONFIG_ATA_ACPI=y
@@ -842,7 +842,7 @@ CONFIG_PATA_AMD=y
842# CONFIG_PATA_CS5536 is not set 842# CONFIG_PATA_CS5536 is not set
843# CONFIG_PATA_CYPRESS is not set 843# CONFIG_PATA_CYPRESS is not set
844# CONFIG_PATA_EFAR is not set 844# CONFIG_PATA_EFAR is not set
845# CONFIG_ATA_GENERIC is not set 845CONFIG_ATA_GENERIC=y
846# CONFIG_PATA_HPT366 is not set 846# CONFIG_PATA_HPT366 is not set
847# CONFIG_PATA_HPT37X is not set 847# CONFIG_PATA_HPT37X is not set
848# CONFIG_PATA_HPT3X2N is not set 848# CONFIG_PATA_HPT3X2N is not set
@@ -852,7 +852,7 @@ CONFIG_PATA_AMD=y
852# CONFIG_PATA_JMICRON is not set 852# CONFIG_PATA_JMICRON is not set
853# CONFIG_PATA_TRIFLEX is not set 853# CONFIG_PATA_TRIFLEX is not set
854# CONFIG_PATA_MARVELL is not set 854# CONFIG_PATA_MARVELL is not set
855# CONFIG_PATA_MPIIX is not set 855CONFIG_PATA_MPIIX=y
856CONFIG_PATA_OLDPIIX=y 856CONFIG_PATA_OLDPIIX=y
857# CONFIG_PATA_NETCELL is not set 857# CONFIG_PATA_NETCELL is not set
858# CONFIG_PATA_NINJA32 is not set 858# CONFIG_PATA_NINJA32 is not set
@@ -871,6 +871,7 @@ CONFIG_PATA_OLDPIIX=y
871# CONFIG_PATA_SIS is not set 871# CONFIG_PATA_SIS is not set
872# CONFIG_PATA_VIA is not set 872# CONFIG_PATA_VIA is not set
873# CONFIG_PATA_WINBOND is not set 873# CONFIG_PATA_WINBOND is not set
874CONFIG_PATA_SCH=y
874CONFIG_MD=y 875CONFIG_MD=y
875CONFIG_BLK_DEV_MD=y 876CONFIG_BLK_DEV_MD=y
876# CONFIG_MD_LINEAR is not set 877# CONFIG_MD_LINEAR is not set
@@ -894,13 +895,16 @@ CONFIG_DM_ZERO=y
894# 895#
895# IEEE 1394 (FireWire) support 896# IEEE 1394 (FireWire) support
896# 897#
898
899#
900# Enable only one of the two stacks, unless you know what you are doing
901#
897# CONFIG_FIREWIRE is not set 902# CONFIG_FIREWIRE is not set
898# CONFIG_IEEE1394 is not set 903# CONFIG_IEEE1394 is not set
899# CONFIG_I2O is not set 904# CONFIG_I2O is not set
900CONFIG_MACINTOSH_DRIVERS=y 905CONFIG_MACINTOSH_DRIVERS=y
901CONFIG_MAC_EMUMOUSEBTN=y 906CONFIG_MAC_EMUMOUSEBTN=y
902CONFIG_NETDEVICES=y 907CONFIG_NETDEVICES=y
903# CONFIG_NETDEVICES_MULTIQUEUE is not set
904# CONFIG_IFB is not set 908# CONFIG_IFB is not set
905# CONFIG_DUMMY is not set 909# CONFIG_DUMMY is not set
906# CONFIG_BONDING is not set 910# CONFIG_BONDING is not set
@@ -910,7 +914,23 @@ CONFIG_NETDEVICES=y
910# CONFIG_VETH is not set 914# CONFIG_VETH is not set
911# CONFIG_NET_SB1000 is not set 915# CONFIG_NET_SB1000 is not set
912# CONFIG_ARCNET is not set 916# CONFIG_ARCNET is not set
913# CONFIG_PHYLIB is not set 917CONFIG_PHYLIB=y
918
919#
920# MII PHY device drivers
921#
922# CONFIG_MARVELL_PHY is not set
923# CONFIG_DAVICOM_PHY is not set
924# CONFIG_QSEMI_PHY is not set
925# CONFIG_LXT_PHY is not set
926# CONFIG_CICADA_PHY is not set
927# CONFIG_VITESSE_PHY is not set
928# CONFIG_SMSC_PHY is not set
929# CONFIG_BROADCOM_PHY is not set
930# CONFIG_ICPLUS_PHY is not set
931# CONFIG_REALTEK_PHY is not set
932# CONFIG_FIXED_PHY is not set
933# CONFIG_MDIO_BITBANG is not set
914CONFIG_NET_ETHERNET=y 934CONFIG_NET_ETHERNET=y
915CONFIG_MII=y 935CONFIG_MII=y
916# CONFIG_HAPPYMEAL is not set 936# CONFIG_HAPPYMEAL is not set
@@ -943,10 +963,10 @@ CONFIG_FORCEDETH=y
943CONFIG_E100=y 963CONFIG_E100=y
944# CONFIG_FEALNX is not set 964# CONFIG_FEALNX is not set
945# CONFIG_NATSEMI is not set 965# CONFIG_NATSEMI is not set
946# CONFIG_NE2K_PCI is not set 966CONFIG_NE2K_PCI=y
947# CONFIG_8139CP is not set 967# CONFIG_8139CP is not set
948CONFIG_8139TOO=y 968CONFIG_8139TOO=y
949CONFIG_8139TOO_PIO=y 969# CONFIG_8139TOO_PIO is not set
950# CONFIG_8139TOO_TUNE_TWISTER is not set 970# CONFIG_8139TOO_TUNE_TWISTER is not set
951# CONFIG_8139TOO_8129 is not set 971# CONFIG_8139TOO_8129 is not set
952# CONFIG_8139_OLD_RX_RESET is not set 972# CONFIG_8139_OLD_RX_RESET is not set
@@ -961,25 +981,24 @@ CONFIG_NETDEV_1000=y
961# CONFIG_ACENIC is not set 981# CONFIG_ACENIC is not set
962# CONFIG_DL2K is not set 982# CONFIG_DL2K is not set
963CONFIG_E1000=y 983CONFIG_E1000=y
964# CONFIG_E1000_NAPI is not set
965# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set 984# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
966# CONFIG_E1000E is not set 985CONFIG_E1000E=y
967# CONFIG_E1000E_ENABLED is not set
968# CONFIG_IP1000 is not set 986# CONFIG_IP1000 is not set
969# CONFIG_IGB is not set 987# CONFIG_IGB is not set
970# CONFIG_NS83820 is not set 988# CONFIG_NS83820 is not set
971# CONFIG_HAMACHI is not set 989# CONFIG_HAMACHI is not set
972# CONFIG_YELLOWFIN is not set 990# CONFIG_YELLOWFIN is not set
973# CONFIG_R8169 is not set 991CONFIG_R8169=y
974# CONFIG_SIS190 is not set 992# CONFIG_SIS190 is not set
975# CONFIG_SKGE is not set 993# CONFIG_SKGE is not set
976CONFIG_SKY2=y 994CONFIG_SKY2=y
977# CONFIG_SKY2_DEBUG is not set 995# CONFIG_SKY2_DEBUG is not set
978# CONFIG_VIA_VELOCITY is not set 996# CONFIG_VIA_VELOCITY is not set
979CONFIG_TIGON3=y 997CONFIG_TIGON3=y
980# CONFIG_BNX2 is not set 998CONFIG_BNX2=y
981# CONFIG_QLA3XXX is not set 999# CONFIG_QLA3XXX is not set
982# CONFIG_ATL1 is not set 1000# CONFIG_ATL1 is not set
1001# CONFIG_ATL1E is not set
983CONFIG_NETDEV_10000=y 1002CONFIG_NETDEV_10000=y
984# CONFIG_CHELSIO_T1 is not set 1003# CONFIG_CHELSIO_T1 is not set
985# CONFIG_CHELSIO_T3 is not set 1004# CONFIG_CHELSIO_T3 is not set
@@ -1019,13 +1038,14 @@ CONFIG_WLAN_80211=y
1019# CONFIG_RTL8180 is not set 1038# CONFIG_RTL8180 is not set
1020# CONFIG_RTL8187 is not set 1039# CONFIG_RTL8187 is not set
1021# CONFIG_ADM8211 is not set 1040# CONFIG_ADM8211 is not set
1041# CONFIG_MAC80211_HWSIM is not set
1022# CONFIG_P54_COMMON is not set 1042# CONFIG_P54_COMMON is not set
1023CONFIG_ATH5K=y 1043CONFIG_ATH5K=y
1024# CONFIG_ATH5K_DEBUG is not set 1044# CONFIG_ATH5K_DEBUG is not set
1025# CONFIG_IWLWIFI is not set 1045# CONFIG_ATH9K is not set
1026# CONFIG_IWLCORE is not set 1046# CONFIG_IWLCORE is not set
1027# CONFIG_IWLWIFI_LEDS is not set 1047# CONFIG_IWLWIFI_LEDS is not set
1028# CONFIG_IWL4965 is not set 1048# CONFIG_IWLAGN is not set
1029# CONFIG_IWL3945 is not set 1049# CONFIG_IWL3945 is not set
1030# CONFIG_HOSTAP is not set 1050# CONFIG_HOSTAP is not set
1031# CONFIG_B43 is not set 1051# CONFIG_B43 is not set
@@ -1105,6 +1125,7 @@ CONFIG_MOUSE_PS2_TRACKPOINT=y
1105# CONFIG_MOUSE_PS2_TOUCHKIT is not set 1125# CONFIG_MOUSE_PS2_TOUCHKIT is not set
1106# CONFIG_MOUSE_SERIAL is not set 1126# CONFIG_MOUSE_SERIAL is not set
1107# CONFIG_MOUSE_APPLETOUCH is not set 1127# CONFIG_MOUSE_APPLETOUCH is not set
1128# CONFIG_MOUSE_BCM5974 is not set
1108# CONFIG_MOUSE_VSXXXAA is not set 1129# CONFIG_MOUSE_VSXXXAA is not set
1109CONFIG_INPUT_JOYSTICK=y 1130CONFIG_INPUT_JOYSTICK=y
1110# CONFIG_JOYSTICK_ANALOG is not set 1131# CONFIG_JOYSTICK_ANALOG is not set
@@ -1139,12 +1160,14 @@ CONFIG_INPUT_TOUCHSCREEN=y
1139# CONFIG_TOUCHSCREEN_GUNZE is not set 1160# CONFIG_TOUCHSCREEN_GUNZE is not set
1140# CONFIG_TOUCHSCREEN_ELO is not set 1161# CONFIG_TOUCHSCREEN_ELO is not set
1141# CONFIG_TOUCHSCREEN_MTOUCH is not set 1162# CONFIG_TOUCHSCREEN_MTOUCH is not set
1163# CONFIG_TOUCHSCREEN_INEXIO is not set
1142# CONFIG_TOUCHSCREEN_MK712 is not set 1164# CONFIG_TOUCHSCREEN_MK712 is not set
1143# CONFIG_TOUCHSCREEN_PENMOUNT is not set 1165# CONFIG_TOUCHSCREEN_PENMOUNT is not set
1144# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set 1166# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
1145# CONFIG_TOUCHSCREEN_TOUCHWIN is not set 1167# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
1146# CONFIG_TOUCHSCREEN_UCB1400 is not set 1168# CONFIG_TOUCHSCREEN_UCB1400 is not set
1147# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set 1169# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
1170# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
1148CONFIG_INPUT_MISC=y 1171CONFIG_INPUT_MISC=y
1149# CONFIG_INPUT_PCSPKR is not set 1172# CONFIG_INPUT_PCSPKR is not set
1150# CONFIG_INPUT_APANEL is not set 1173# CONFIG_INPUT_APANEL is not set
@@ -1173,6 +1196,7 @@ CONFIG_SERIO_LIBPS2=y
1173# Character devices 1196# Character devices
1174# 1197#
1175CONFIG_VT=y 1198CONFIG_VT=y
1199CONFIG_CONSOLE_TRANSLATIONS=y
1176CONFIG_VT_CONSOLE=y 1200CONFIG_VT_CONSOLE=y
1177CONFIG_HW_CONSOLE=y 1201CONFIG_HW_CONSOLE=y
1178CONFIG_VT_HW_CONSOLE_BINDING=y 1202CONFIG_VT_HW_CONSOLE_BINDING=y
@@ -1223,8 +1247,8 @@ CONFIG_UNIX98_PTYS=y
1223# CONFIG_LEGACY_PTYS is not set 1247# CONFIG_LEGACY_PTYS is not set
1224# CONFIG_IPMI_HANDLER is not set 1248# CONFIG_IPMI_HANDLER is not set
1225CONFIG_HW_RANDOM=y 1249CONFIG_HW_RANDOM=y
1226# CONFIG_HW_RANDOM_INTEL is not set 1250CONFIG_HW_RANDOM_INTEL=y
1227# CONFIG_HW_RANDOM_AMD is not set 1251CONFIG_HW_RANDOM_AMD=y
1228CONFIG_HW_RANDOM_GEODE=y 1252CONFIG_HW_RANDOM_GEODE=y
1229CONFIG_HW_RANDOM_VIA=y 1253CONFIG_HW_RANDOM_VIA=y
1230CONFIG_NVRAM=y 1254CONFIG_NVRAM=y
@@ -1245,7 +1269,6 @@ CONFIG_NVRAM=y
1245# CONFIG_CS5535_GPIO is not set 1269# CONFIG_CS5535_GPIO is not set
1246# CONFIG_RAW_DRIVER is not set 1270# CONFIG_RAW_DRIVER is not set
1247CONFIG_HPET=y 1271CONFIG_HPET=y
1248# CONFIG_HPET_RTC_IRQ is not set
1249# CONFIG_HPET_MMAP is not set 1272# CONFIG_HPET_MMAP is not set
1250# CONFIG_HANGCHECK_TIMER is not set 1273# CONFIG_HANGCHECK_TIMER is not set
1251# CONFIG_TCG_TPM is not set 1274# CONFIG_TCG_TPM is not set
@@ -1254,43 +1277,64 @@ CONFIG_DEVPORT=y
1254CONFIG_I2C=y 1277CONFIG_I2C=y
1255CONFIG_I2C_BOARDINFO=y 1278CONFIG_I2C_BOARDINFO=y
1256# CONFIG_I2C_CHARDEV is not set 1279# CONFIG_I2C_CHARDEV is not set
1280CONFIG_I2C_HELPER_AUTO=y
1257 1281
1258# 1282#
1259# I2C Hardware Bus support 1283# I2C Hardware Bus support
1260# 1284#
1285
1286#
1287# PC SMBus host controller drivers
1288#
1261# CONFIG_I2C_ALI1535 is not set 1289# CONFIG_I2C_ALI1535 is not set
1262# CONFIG_I2C_ALI1563 is not set 1290# CONFIG_I2C_ALI1563 is not set
1263# CONFIG_I2C_ALI15X3 is not set 1291# CONFIG_I2C_ALI15X3 is not set
1264# CONFIG_I2C_AMD756 is not set 1292# CONFIG_I2C_AMD756 is not set
1265# CONFIG_I2C_AMD8111 is not set 1293# CONFIG_I2C_AMD8111 is not set
1266CONFIG_I2C_I801=y 1294CONFIG_I2C_I801=y
1267# CONFIG_I2C_I810 is not set 1295# CONFIG_I2C_ISCH is not set
1268# CONFIG_I2C_PIIX4 is not set 1296# CONFIG_I2C_PIIX4 is not set
1269# CONFIG_I2C_NFORCE2 is not set 1297# CONFIG_I2C_NFORCE2 is not set
1270# CONFIG_I2C_OCORES is not set
1271# CONFIG_I2C_PARPORT_LIGHT is not set
1272# CONFIG_I2C_PROSAVAGE is not set
1273# CONFIG_I2C_SAVAGE4 is not set
1274# CONFIG_I2C_SIMTEC is not set
1275# CONFIG_SCx200_ACB is not set
1276# CONFIG_I2C_SIS5595 is not set 1298# CONFIG_I2C_SIS5595 is not set
1277# CONFIG_I2C_SIS630 is not set 1299# CONFIG_I2C_SIS630 is not set
1278# CONFIG_I2C_SIS96X is not set 1300# CONFIG_I2C_SIS96X is not set
1279# CONFIG_I2C_TAOS_EVM is not set
1280# CONFIG_I2C_STUB is not set
1281# CONFIG_I2C_TINY_USB is not set
1282# CONFIG_I2C_VIA is not set 1301# CONFIG_I2C_VIA is not set
1283# CONFIG_I2C_VIAPRO is not set 1302# CONFIG_I2C_VIAPRO is not set
1303
1304#
1305# I2C system bus drivers (mostly embedded / system-on-chip)
1306#
1307# CONFIG_I2C_OCORES is not set
1308# CONFIG_I2C_SIMTEC is not set
1309
1310#
1311# External I2C/SMBus adapter drivers
1312#
1313# CONFIG_I2C_PARPORT_LIGHT is not set
1314# CONFIG_I2C_TAOS_EVM is not set
1315# CONFIG_I2C_TINY_USB is not set
1316
1317#
1318# Graphics adapter I2C/DDC channel drivers
1319#
1284# CONFIG_I2C_VOODOO3 is not set 1320# CONFIG_I2C_VOODOO3 is not set
1321
1322#
1323# Other I2C/SMBus bus drivers
1324#
1285# CONFIG_I2C_PCA_PLATFORM is not set 1325# CONFIG_I2C_PCA_PLATFORM is not set
1326# CONFIG_I2C_STUB is not set
1327# CONFIG_SCx200_ACB is not set
1286 1328
1287# 1329#
1288# Miscellaneous I2C Chip support 1330# Miscellaneous I2C Chip support
1289# 1331#
1290# CONFIG_DS1682 is not set 1332# CONFIG_DS1682 is not set
1333# CONFIG_AT24 is not set
1291# CONFIG_SENSORS_EEPROM is not set 1334# CONFIG_SENSORS_EEPROM is not set
1292# CONFIG_SENSORS_PCF8574 is not set 1335# CONFIG_SENSORS_PCF8574 is not set
1293# CONFIG_PCF8575 is not set 1336# CONFIG_PCF8575 is not set
1337# CONFIG_SENSORS_PCA9539 is not set
1294# CONFIG_SENSORS_PCF8591 is not set 1338# CONFIG_SENSORS_PCF8591 is not set
1295# CONFIG_SENSORS_MAX6875 is not set 1339# CONFIG_SENSORS_MAX6875 is not set
1296# CONFIG_SENSORS_TSL2550 is not set 1340# CONFIG_SENSORS_TSL2550 is not set
@@ -1299,6 +1343,8 @@ CONFIG_I2C_I801=y
1299# CONFIG_I2C_DEBUG_BUS is not set 1343# CONFIG_I2C_DEBUG_BUS is not set
1300# CONFIG_I2C_DEBUG_CHIP is not set 1344# CONFIG_I2C_DEBUG_CHIP is not set
1301# CONFIG_SPI is not set 1345# CONFIG_SPI is not set
1346CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
1347# CONFIG_GPIOLIB is not set
1302# CONFIG_W1 is not set 1348# CONFIG_W1 is not set
1303CONFIG_POWER_SUPPLY=y 1349CONFIG_POWER_SUPPLY=y
1304# CONFIG_POWER_SUPPLY_DEBUG is not set 1350# CONFIG_POWER_SUPPLY_DEBUG is not set
@@ -1360,8 +1406,10 @@ CONFIG_SSB_POSSIBLE=y
1360# 1406#
1361# Multifunction device drivers 1407# Multifunction device drivers
1362# 1408#
1409# CONFIG_MFD_CORE is not set
1363# CONFIG_MFD_SM501 is not set 1410# CONFIG_MFD_SM501 is not set
1364# CONFIG_HTC_PASIC3 is not set 1411# CONFIG_HTC_PASIC3 is not set
1412# CONFIG_MFD_TMIO is not set
1365 1413
1366# 1414#
1367# Multimedia devices 1415# Multimedia devices
@@ -1372,6 +1420,7 @@ CONFIG_SSB_POSSIBLE=y
1372# 1420#
1373# CONFIG_VIDEO_DEV is not set 1421# CONFIG_VIDEO_DEV is not set
1374# CONFIG_DVB_CORE is not set 1422# CONFIG_DVB_CORE is not set
1423# CONFIG_VIDEO_MEDIA is not set
1375 1424
1376# 1425#
1377# Multimedia drivers 1426# Multimedia drivers
@@ -1418,7 +1467,6 @@ CONFIG_FB_CFB_IMAGEBLIT=y
1418# CONFIG_FB_SYS_IMAGEBLIT is not set 1467# CONFIG_FB_SYS_IMAGEBLIT is not set
1419# CONFIG_FB_FOREIGN_ENDIAN is not set 1468# CONFIG_FB_FOREIGN_ENDIAN is not set
1420# CONFIG_FB_SYS_FOPS is not set 1469# CONFIG_FB_SYS_FOPS is not set
1421CONFIG_FB_DEFERRED_IO=y
1422# CONFIG_FB_SVGALIB is not set 1470# CONFIG_FB_SVGALIB is not set
1423# CONFIG_FB_MACMODES is not set 1471# CONFIG_FB_MACMODES is not set
1424# CONFIG_FB_BACKLIGHT is not set 1472# CONFIG_FB_BACKLIGHT is not set
@@ -1463,6 +1511,7 @@ CONFIG_FB_EFI=y
1463# CONFIG_FB_TRIDENT is not set 1511# CONFIG_FB_TRIDENT is not set
1464# CONFIG_FB_ARK is not set 1512# CONFIG_FB_ARK is not set
1465# CONFIG_FB_PM3 is not set 1513# CONFIG_FB_PM3 is not set
1514# CONFIG_FB_CARMINE is not set
1466# CONFIG_FB_GEODE is not set 1515# CONFIG_FB_GEODE is not set
1467# CONFIG_FB_VIRTUAL is not set 1516# CONFIG_FB_VIRTUAL is not set
1468CONFIG_BACKLIGHT_LCD_SUPPORT=y 1517CONFIG_BACKLIGHT_LCD_SUPPORT=y
@@ -1470,6 +1519,7 @@ CONFIG_BACKLIGHT_LCD_SUPPORT=y
1470CONFIG_BACKLIGHT_CLASS_DEVICE=y 1519CONFIG_BACKLIGHT_CLASS_DEVICE=y
1471# CONFIG_BACKLIGHT_CORGI is not set 1520# CONFIG_BACKLIGHT_CORGI is not set
1472# CONFIG_BACKLIGHT_PROGEAR is not set 1521# CONFIG_BACKLIGHT_PROGEAR is not set
1522# CONFIG_BACKLIGHT_MBP_NVIDIA is not set
1473 1523
1474# 1524#
1475# Display device support 1525# Display device support
@@ -1489,15 +1539,7 @@ CONFIG_LOGO=y
1489# CONFIG_LOGO_LINUX_MONO is not set 1539# CONFIG_LOGO_LINUX_MONO is not set
1490# CONFIG_LOGO_LINUX_VGA16 is not set 1540# CONFIG_LOGO_LINUX_VGA16 is not set
1491CONFIG_LOGO_LINUX_CLUT224=y 1541CONFIG_LOGO_LINUX_CLUT224=y
1492
1493#
1494# Sound
1495#
1496CONFIG_SOUND=y 1542CONFIG_SOUND=y
1497
1498#
1499# Advanced Linux Sound Architecture
1500#
1501CONFIG_SND=y 1543CONFIG_SND=y
1502CONFIG_SND_TIMER=y 1544CONFIG_SND_TIMER=y
1503CONFIG_SND_PCM=y 1545CONFIG_SND_PCM=y
@@ -1515,20 +1557,14 @@ CONFIG_SND_VERBOSE_PROCFS=y
1515# CONFIG_SND_VERBOSE_PRINTK is not set 1557# CONFIG_SND_VERBOSE_PRINTK is not set
1516# CONFIG_SND_DEBUG is not set 1558# CONFIG_SND_DEBUG is not set
1517CONFIG_SND_VMASTER=y 1559CONFIG_SND_VMASTER=y
1518 1560CONFIG_SND_DRIVERS=y
1519#
1520# Generic devices
1521#
1522# CONFIG_SND_PCSP is not set 1561# CONFIG_SND_PCSP is not set
1523# CONFIG_SND_DUMMY is not set 1562# CONFIG_SND_DUMMY is not set
1524# CONFIG_SND_VIRMIDI is not set 1563# CONFIG_SND_VIRMIDI is not set
1525# CONFIG_SND_MTPAV is not set 1564# CONFIG_SND_MTPAV is not set
1526# CONFIG_SND_SERIAL_U16550 is not set 1565# CONFIG_SND_SERIAL_U16550 is not set
1527# CONFIG_SND_MPU401 is not set 1566# CONFIG_SND_MPU401 is not set
1528 1567CONFIG_SND_PCI=y
1529#
1530# PCI devices
1531#
1532# CONFIG_SND_AD1889 is not set 1568# CONFIG_SND_AD1889 is not set
1533# CONFIG_SND_ALS300 is not set 1569# CONFIG_SND_ALS300 is not set
1534# CONFIG_SND_ALS4000 is not set 1570# CONFIG_SND_ALS4000 is not set
@@ -1603,36 +1639,14 @@ CONFIG_SND_HDA_GENERIC=y
1603# CONFIG_SND_VIRTUOSO is not set 1639# CONFIG_SND_VIRTUOSO is not set
1604# CONFIG_SND_VX222 is not set 1640# CONFIG_SND_VX222 is not set
1605# CONFIG_SND_YMFPCI is not set 1641# CONFIG_SND_YMFPCI is not set
1606 1642CONFIG_SND_USB=y
1607#
1608# USB devices
1609#
1610# CONFIG_SND_USB_AUDIO is not set 1643# CONFIG_SND_USB_AUDIO is not set
1611# CONFIG_SND_USB_USX2Y is not set 1644# CONFIG_SND_USB_USX2Y is not set
1612# CONFIG_SND_USB_CAIAQ is not set 1645# CONFIG_SND_USB_CAIAQ is not set
1613 1646CONFIG_SND_PCMCIA=y
1614#
1615# PCMCIA devices
1616#
1617# CONFIG_SND_VXPOCKET is not set 1647# CONFIG_SND_VXPOCKET is not set
1618# CONFIG_SND_PDAUDIOCF is not set 1648# CONFIG_SND_PDAUDIOCF is not set
1619
1620#
1621# System on Chip audio support
1622#
1623# CONFIG_SND_SOC is not set 1649# CONFIG_SND_SOC is not set
1624
1625#
1626# ALSA SoC audio for Freescale SOCs
1627#
1628
1629#
1630# SoC Audio for the Texas Instruments OMAP
1631#
1632
1633#
1634# Open Sound System
1635#
1636# CONFIG_SOUND_PRIME is not set 1650# CONFIG_SOUND_PRIME is not set
1637CONFIG_HID_SUPPORT=y 1651CONFIG_HID_SUPPORT=y
1638CONFIG_HID=y 1652CONFIG_HID=y
@@ -1668,6 +1682,7 @@ CONFIG_USB_DEVICEFS=y
1668# CONFIG_USB_DYNAMIC_MINORS is not set 1682# CONFIG_USB_DYNAMIC_MINORS is not set
1669CONFIG_USB_SUSPEND=y 1683CONFIG_USB_SUSPEND=y
1670# CONFIG_USB_OTG is not set 1684# CONFIG_USB_OTG is not set
1685CONFIG_USB_MON=y
1671 1686
1672# 1687#
1673# USB Host Controller Drivers 1688# USB Host Controller Drivers
@@ -1691,6 +1706,7 @@ CONFIG_USB_UHCI_HCD=y
1691# 1706#
1692# CONFIG_USB_ACM is not set 1707# CONFIG_USB_ACM is not set
1693CONFIG_USB_PRINTER=y 1708CONFIG_USB_PRINTER=y
1709# CONFIG_USB_WDM is not set
1694 1710
1695# 1711#
1696# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 1712# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
@@ -1712,6 +1728,7 @@ CONFIG_USB_STORAGE=y
1712# CONFIG_USB_STORAGE_ALAUDA is not set 1728# CONFIG_USB_STORAGE_ALAUDA is not set
1713# CONFIG_USB_STORAGE_ONETOUCH is not set 1729# CONFIG_USB_STORAGE_ONETOUCH is not set
1714# CONFIG_USB_STORAGE_KARMA is not set 1730# CONFIG_USB_STORAGE_KARMA is not set
1731# CONFIG_USB_STORAGE_SIERRA is not set
1715# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set 1732# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
1716CONFIG_USB_LIBUSUAL=y 1733CONFIG_USB_LIBUSUAL=y
1717 1734
@@ -1720,7 +1737,6 @@ CONFIG_USB_LIBUSUAL=y
1720# 1737#
1721# CONFIG_USB_MDC800 is not set 1738# CONFIG_USB_MDC800 is not set
1722# CONFIG_USB_MICROTEK is not set 1739# CONFIG_USB_MICROTEK is not set
1723CONFIG_USB_MON=y
1724 1740
1725# 1741#
1726# USB port drivers 1742# USB port drivers
@@ -1733,7 +1749,6 @@ CONFIG_USB_MON=y
1733# CONFIG_USB_EMI62 is not set 1749# CONFIG_USB_EMI62 is not set
1734# CONFIG_USB_EMI26 is not set 1750# CONFIG_USB_EMI26 is not set
1735# CONFIG_USB_ADUTUX is not set 1751# CONFIG_USB_ADUTUX is not set
1736# CONFIG_USB_AUERSWALD is not set
1737# CONFIG_USB_RIO500 is not set 1752# CONFIG_USB_RIO500 is not set
1738# CONFIG_USB_LEGOTOWER is not set 1753# CONFIG_USB_LEGOTOWER is not set
1739# CONFIG_USB_LCD is not set 1754# CONFIG_USB_LCD is not set
@@ -1750,6 +1765,7 @@ CONFIG_USB_MON=y
1750# CONFIG_USB_TRANCEVIBRATOR is not set 1765# CONFIG_USB_TRANCEVIBRATOR is not set
1751# CONFIG_USB_IOWARRIOR is not set 1766# CONFIG_USB_IOWARRIOR is not set
1752# CONFIG_USB_TEST is not set 1767# CONFIG_USB_TEST is not set
1768# CONFIG_USB_ISIGHTFW is not set
1753# CONFIG_USB_GADGET is not set 1769# CONFIG_USB_GADGET is not set
1754# CONFIG_MMC is not set 1770# CONFIG_MMC is not set
1755# CONFIG_MEMSTICK is not set 1771# CONFIG_MEMSTICK is not set
@@ -1759,7 +1775,9 @@ CONFIG_LEDS_CLASS=y
1759# 1775#
1760# LED drivers 1776# LED drivers
1761# 1777#
1778# CONFIG_LEDS_PCA9532 is not set
1762# CONFIG_LEDS_CLEVO_MAIL is not set 1779# CONFIG_LEDS_CLEVO_MAIL is not set
1780# CONFIG_LEDS_PCA955X is not set
1763 1781
1764# 1782#
1765# LED Triggers 1783# LED Triggers
@@ -1805,6 +1823,7 @@ CONFIG_RTC_INTF_DEV=y
1805# CONFIG_RTC_DRV_PCF8583 is not set 1823# CONFIG_RTC_DRV_PCF8583 is not set
1806# CONFIG_RTC_DRV_M41T80 is not set 1824# CONFIG_RTC_DRV_M41T80 is not set
1807# CONFIG_RTC_DRV_S35390A is not set 1825# CONFIG_RTC_DRV_S35390A is not set
1826# CONFIG_RTC_DRV_FM3130 is not set
1808 1827
1809# 1828#
1810# SPI RTC drivers 1829# SPI RTC drivers
@@ -1837,11 +1856,13 @@ CONFIG_DMADEVICES=y
1837# Firmware Drivers 1856# Firmware Drivers
1838# 1857#
1839# CONFIG_EDD is not set 1858# CONFIG_EDD is not set
1859CONFIG_FIRMWARE_MEMMAP=y
1840CONFIG_EFI_VARS=y 1860CONFIG_EFI_VARS=y
1841# CONFIG_DELL_RBU is not set 1861# CONFIG_DELL_RBU is not set
1842# CONFIG_DCDBAS is not set 1862# CONFIG_DCDBAS is not set
1843CONFIG_DMIID=y 1863CONFIG_DMIID=y
1844# CONFIG_ISCSI_IBFT_FIND is not set 1864CONFIG_ISCSI_IBFT_FIND=y
1865CONFIG_ISCSI_IBFT=y
1845 1866
1846# 1867#
1847# File systems 1868# File systems
@@ -1920,14 +1941,27 @@ CONFIG_HUGETLB_PAGE=y
1920# CONFIG_CRAMFS is not set 1941# CONFIG_CRAMFS is not set
1921# CONFIG_VXFS_FS is not set 1942# CONFIG_VXFS_FS is not set
1922# CONFIG_MINIX_FS is not set 1943# CONFIG_MINIX_FS is not set
1944# CONFIG_OMFS_FS is not set
1923# CONFIG_HPFS_FS is not set 1945# CONFIG_HPFS_FS is not set
1924# CONFIG_QNX4FS_FS is not set 1946# CONFIG_QNX4FS_FS is not set
1925# CONFIG_ROMFS_FS is not set 1947# CONFIG_ROMFS_FS is not set
1926# CONFIG_SYSV_FS is not set 1948# CONFIG_SYSV_FS is not set
1927# CONFIG_UFS_FS is not set 1949# CONFIG_UFS_FS is not set
1928CONFIG_NETWORK_FILESYSTEMS=y 1950CONFIG_NETWORK_FILESYSTEMS=y
1929# CONFIG_NFS_FS is not set 1951CONFIG_NFS_FS=y
1952CONFIG_NFS_V3=y
1953CONFIG_NFS_V3_ACL=y
1954CONFIG_NFS_V4=y
1955CONFIG_ROOT_NFS=y
1930# CONFIG_NFSD is not set 1956# CONFIG_NFSD is not set
1957CONFIG_LOCKD=y
1958CONFIG_LOCKD_V4=y
1959CONFIG_NFS_ACL_SUPPORT=y
1960CONFIG_NFS_COMMON=y
1961CONFIG_SUNRPC=y
1962CONFIG_SUNRPC_GSS=y
1963CONFIG_RPCSEC_GSS_KRB5=y
1964# CONFIG_RPCSEC_GSS_SPKM3 is not set
1931# CONFIG_SMB_FS is not set 1965# CONFIG_SMB_FS is not set
1932# CONFIG_CIFS is not set 1966# CONFIG_CIFS is not set
1933# CONFIG_NCP_FS is not set 1967# CONFIG_NCP_FS is not set
@@ -2001,9 +2035,9 @@ CONFIG_NLS_UTF8=y
2001# Kernel hacking 2035# Kernel hacking
2002# 2036#
2003CONFIG_TRACE_IRQFLAGS_SUPPORT=y 2037CONFIG_TRACE_IRQFLAGS_SUPPORT=y
2004# CONFIG_PRINTK_TIME is not set 2038CONFIG_PRINTK_TIME=y
2005# CONFIG_ENABLE_WARN_DEPRECATED is not set 2039CONFIG_ENABLE_WARN_DEPRECATED=y
2006# CONFIG_ENABLE_MUST_CHECK is not set 2040CONFIG_ENABLE_MUST_CHECK=y
2007CONFIG_FRAME_WARN=2048 2041CONFIG_FRAME_WARN=2048
2008CONFIG_MAGIC_SYSRQ=y 2042CONFIG_MAGIC_SYSRQ=y
2009# CONFIG_UNUSED_SYMBOLS is not set 2043# CONFIG_UNUSED_SYMBOLS is not set
@@ -2033,6 +2067,7 @@ CONFIG_DEBUG_BUGVERBOSE=y
2033# CONFIG_DEBUG_INFO is not set 2067# CONFIG_DEBUG_INFO is not set
2034# CONFIG_DEBUG_VM is not set 2068# CONFIG_DEBUG_VM is not set
2035# CONFIG_DEBUG_WRITECOUNT is not set 2069# CONFIG_DEBUG_WRITECOUNT is not set
2070CONFIG_DEBUG_MEMORY_INIT=y
2036# CONFIG_DEBUG_LIST is not set 2071# CONFIG_DEBUG_LIST is not set
2037# CONFIG_DEBUG_SG is not set 2072# CONFIG_DEBUG_SG is not set
2038CONFIG_FRAME_POINTER=y 2073CONFIG_FRAME_POINTER=y
@@ -2043,23 +2078,32 @@ CONFIG_FRAME_POINTER=y
2043# CONFIG_LKDTM is not set 2078# CONFIG_LKDTM is not set
2044# CONFIG_FAULT_INJECTION is not set 2079# CONFIG_FAULT_INJECTION is not set
2045# CONFIG_LATENCYTOP is not set 2080# CONFIG_LATENCYTOP is not set
2081CONFIG_SYSCTL_SYSCALL_CHECK=y
2082CONFIG_HAVE_FTRACE=y
2083CONFIG_HAVE_DYNAMIC_FTRACE=y
2084# CONFIG_FTRACE is not set
2085# CONFIG_IRQSOFF_TRACER is not set
2086# CONFIG_SYSPROF_TRACER is not set
2087# CONFIG_SCHED_TRACER is not set
2088# CONFIG_CONTEXT_SWITCH_TRACER is not set
2046CONFIG_PROVIDE_OHCI1394_DMA_INIT=y 2089CONFIG_PROVIDE_OHCI1394_DMA_INIT=y
2047# CONFIG_SAMPLES is not set 2090# CONFIG_SAMPLES is not set
2048# CONFIG_KGDB is not set
2049CONFIG_HAVE_ARCH_KGDB=y 2091CONFIG_HAVE_ARCH_KGDB=y
2092# CONFIG_KGDB is not set
2050# CONFIG_STRICT_DEVMEM is not set 2093# CONFIG_STRICT_DEVMEM is not set
2094CONFIG_X86_VERBOSE_BOOTUP=y
2051CONFIG_EARLY_PRINTK=y 2095CONFIG_EARLY_PRINTK=y
2052CONFIG_DEBUG_STACKOVERFLOW=y 2096CONFIG_DEBUG_STACKOVERFLOW=y
2053CONFIG_DEBUG_STACK_USAGE=y 2097CONFIG_DEBUG_STACK_USAGE=y
2054# CONFIG_DEBUG_PAGEALLOC is not set 2098# CONFIG_DEBUG_PAGEALLOC is not set
2099# CONFIG_DEBUG_PER_CPU_MAPS is not set
2055# CONFIG_X86_PTDUMP is not set 2100# CONFIG_X86_PTDUMP is not set
2056CONFIG_DEBUG_RODATA=y 2101CONFIG_DEBUG_RODATA=y
2057# CONFIG_DEBUG_RODATA_TEST is not set 2102# CONFIG_DEBUG_RODATA_TEST is not set
2058CONFIG_DEBUG_NX_TEST=m 2103CONFIG_DEBUG_NX_TEST=m
2059# CONFIG_4KSTACKS is not set 2104# CONFIG_4KSTACKS is not set
2060CONFIG_X86_FIND_SMP_CONFIG=y
2061CONFIG_X86_MPPARSE=y
2062CONFIG_DOUBLEFAULT=y 2105CONFIG_DOUBLEFAULT=y
2106# CONFIG_MMIOTRACE is not set
2063CONFIG_IO_DELAY_TYPE_0X80=0 2107CONFIG_IO_DELAY_TYPE_0X80=0
2064CONFIG_IO_DELAY_TYPE_0XED=1 2108CONFIG_IO_DELAY_TYPE_0XED=1
2065CONFIG_IO_DELAY_TYPE_UDELAY=2 2109CONFIG_IO_DELAY_TYPE_UDELAY=2
@@ -2071,6 +2115,7 @@ CONFIG_IO_DELAY_0X80=y
2071CONFIG_DEFAULT_IO_DELAY_TYPE=0 2115CONFIG_DEFAULT_IO_DELAY_TYPE=0
2072CONFIG_DEBUG_BOOT_PARAMS=y 2116CONFIG_DEBUG_BOOT_PARAMS=y
2073# CONFIG_CPA_DEBUG is not set 2117# CONFIG_CPA_DEBUG is not set
2118# CONFIG_OPTIMIZE_INLINING is not set
2074 2119
2075# 2120#
2076# Security options 2121# Security options
@@ -2080,7 +2125,6 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
2080CONFIG_SECURITY=y 2125CONFIG_SECURITY=y
2081CONFIG_SECURITY_NETWORK=y 2126CONFIG_SECURITY_NETWORK=y
2082# CONFIG_SECURITY_NETWORK_XFRM is not set 2127# CONFIG_SECURITY_NETWORK_XFRM is not set
2083CONFIG_SECURITY_CAPABILITIES=y
2084CONFIG_SECURITY_FILE_CAPABILITIES=y 2128CONFIG_SECURITY_FILE_CAPABILITIES=y
2085# CONFIG_SECURITY_ROOTPLUG is not set 2129# CONFIG_SECURITY_ROOTPLUG is not set
2086CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=65536 2130CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=65536
@@ -2141,6 +2185,10 @@ CONFIG_CRYPTO_HMAC=y
2141# CONFIG_CRYPTO_MD4 is not set 2185# CONFIG_CRYPTO_MD4 is not set
2142CONFIG_CRYPTO_MD5=y 2186CONFIG_CRYPTO_MD5=y
2143# CONFIG_CRYPTO_MICHAEL_MIC is not set 2187# CONFIG_CRYPTO_MICHAEL_MIC is not set
2188# CONFIG_CRYPTO_RMD128 is not set
2189# CONFIG_CRYPTO_RMD160 is not set
2190# CONFIG_CRYPTO_RMD256 is not set
2191# CONFIG_CRYPTO_RMD320 is not set
2144CONFIG_CRYPTO_SHA1=y 2192CONFIG_CRYPTO_SHA1=y
2145# CONFIG_CRYPTO_SHA256 is not set 2193# CONFIG_CRYPTO_SHA256 is not set
2146# CONFIG_CRYPTO_SHA512 is not set 2194# CONFIG_CRYPTO_SHA512 is not set
@@ -2151,7 +2199,7 @@ CONFIG_CRYPTO_SHA1=y
2151# Ciphers 2199# Ciphers
2152# 2200#
2153CONFIG_CRYPTO_AES=y 2201CONFIG_CRYPTO_AES=y
2154# CONFIG_CRYPTO_AES_586 is not set 2202CONFIG_CRYPTO_AES_586=y
2155# CONFIG_CRYPTO_ANUBIS is not set 2203# CONFIG_CRYPTO_ANUBIS is not set
2156CONFIG_CRYPTO_ARC4=y 2204CONFIG_CRYPTO_ARC4=y
2157# CONFIG_CRYPTO_BLOWFISH is not set 2205# CONFIG_CRYPTO_BLOWFISH is not set
@@ -2193,6 +2241,7 @@ CONFIG_GENERIC_FIND_FIRST_BIT=y
2193CONFIG_GENERIC_FIND_NEXT_BIT=y 2241CONFIG_GENERIC_FIND_NEXT_BIT=y
2194# CONFIG_CRC_CCITT is not set 2242# CONFIG_CRC_CCITT is not set
2195# CONFIG_CRC16 is not set 2243# CONFIG_CRC16 is not set
2244CONFIG_CRC_T10DIF=y
2196# CONFIG_CRC_ITU_T is not set 2245# CONFIG_CRC_ITU_T is not set
2197CONFIG_CRC32=y 2246CONFIG_CRC32=y
2198# CONFIG_CRC7 is not set 2247# CONFIG_CRC7 is not set
diff --git a/arch/x86/configs/x86_64_defconfig b/arch/x86/configs/x86_64_defconfig
index a40452429625..678c8acefe04 100644
--- a/arch/x86/configs/x86_64_defconfig
+++ b/arch/x86/configs/x86_64_defconfig
@@ -1,13 +1,13 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc1 3# Linux kernel version: 2.6.27-rc4
4# Sun May 4 19:59:57 2008 4# Mon Aug 25 14:40:46 2008
5# 5#
6CONFIG_64BIT=y 6CONFIG_64BIT=y
7# CONFIG_X86_32 is not set 7# CONFIG_X86_32 is not set
8CONFIG_X86_64=y 8CONFIG_X86_64=y
9CONFIG_X86=y 9CONFIG_X86=y
10CONFIG_DEFCONFIG_LIST="arch/x86/configs/x86_64_defconfig" 10CONFIG_ARCH_DEFCONFIG="arch/x86/configs/x86_64_defconfig"
11# CONFIG_GENERIC_LOCKBREAK is not set 11# CONFIG_GENERIC_LOCKBREAK is not set
12CONFIG_GENERIC_TIME=y 12CONFIG_GENERIC_TIME=y
13CONFIG_GENERIC_CMOS_UPDATE=y 13CONFIG_GENERIC_CMOS_UPDATE=y
@@ -53,6 +53,7 @@ CONFIG_X86_HT=y
53CONFIG_X86_BIOS_REBOOT=y 53CONFIG_X86_BIOS_REBOOT=y
54CONFIG_X86_TRAMPOLINE=y 54CONFIG_X86_TRAMPOLINE=y
55# CONFIG_KTIME_SCALAR is not set 55# CONFIG_KTIME_SCALAR is not set
56CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
56 57
57# 58#
58# General setup 59# General setup
@@ -82,6 +83,7 @@ CONFIG_CGROUPS=y
82CONFIG_CGROUP_NS=y 83CONFIG_CGROUP_NS=y
83# CONFIG_CGROUP_DEVICE is not set 84# CONFIG_CGROUP_DEVICE is not set
84CONFIG_CPUSETS=y 85CONFIG_CPUSETS=y
86CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y
85CONFIG_GROUP_SCHED=y 87CONFIG_GROUP_SCHED=y
86CONFIG_FAIR_GROUP_SCHED=y 88CONFIG_FAIR_GROUP_SCHED=y
87# CONFIG_RT_GROUP_SCHED is not set 89# CONFIG_RT_GROUP_SCHED is not set
@@ -105,7 +107,6 @@ CONFIG_SYSCTL=y
105# CONFIG_EMBEDDED is not set 107# CONFIG_EMBEDDED is not set
106CONFIG_UID16=y 108CONFIG_UID16=y
107CONFIG_SYSCTL_SYSCALL=y 109CONFIG_SYSCTL_SYSCALL=y
108CONFIG_SYSCTL_SYSCALL_CHECK=y
109CONFIG_KALLSYMS=y 110CONFIG_KALLSYMS=y
110CONFIG_KALLSYMS_ALL=y 111CONFIG_KALLSYMS_ALL=y
111CONFIG_KALLSYMS_EXTRA_PASS=y 112CONFIG_KALLSYMS_EXTRA_PASS=y
@@ -113,6 +114,7 @@ CONFIG_HOTPLUG=y
113CONFIG_PRINTK=y 114CONFIG_PRINTK=y
114CONFIG_BUG=y 115CONFIG_BUG=y
115CONFIG_ELF_CORE=y 116CONFIG_ELF_CORE=y
117CONFIG_PCSPKR_PLATFORM=y
116# CONFIG_COMPAT_BRK is not set 118# CONFIG_COMPAT_BRK is not set
117CONFIG_BASE_FULL=y 119CONFIG_BASE_FULL=y
118CONFIG_FUTEX=y 120CONFIG_FUTEX=y
@@ -132,25 +134,33 @@ CONFIG_MARKERS=y
132# CONFIG_OPROFILE is not set 134# CONFIG_OPROFILE is not set
133CONFIG_HAVE_OPROFILE=y 135CONFIG_HAVE_OPROFILE=y
134CONFIG_KPROBES=y 136CONFIG_KPROBES=y
137CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
135CONFIG_KRETPROBES=y 138CONFIG_KRETPROBES=y
139CONFIG_HAVE_IOREMAP_PROT=y
136CONFIG_HAVE_KPROBES=y 140CONFIG_HAVE_KPROBES=y
137CONFIG_HAVE_KRETPROBES=y 141CONFIG_HAVE_KRETPROBES=y
142# CONFIG_HAVE_ARCH_TRACEHOOK is not set
138# CONFIG_HAVE_DMA_ATTRS is not set 143# CONFIG_HAVE_DMA_ATTRS is not set
144CONFIG_USE_GENERIC_SMP_HELPERS=y
145# CONFIG_HAVE_CLK is not set
139CONFIG_PROC_PAGE_MONITOR=y 146CONFIG_PROC_PAGE_MONITOR=y
147# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
140CONFIG_SLABINFO=y 148CONFIG_SLABINFO=y
141CONFIG_RT_MUTEXES=y 149CONFIG_RT_MUTEXES=y
142# CONFIG_TINY_SHMEM is not set 150# CONFIG_TINY_SHMEM is not set
143CONFIG_BASE_SMALL=0 151CONFIG_BASE_SMALL=0
144CONFIG_MODULES=y 152CONFIG_MODULES=y
153# CONFIG_MODULE_FORCE_LOAD is not set
145CONFIG_MODULE_UNLOAD=y 154CONFIG_MODULE_UNLOAD=y
146CONFIG_MODULE_FORCE_UNLOAD=y 155CONFIG_MODULE_FORCE_UNLOAD=y
147# CONFIG_MODVERSIONS is not set 156# CONFIG_MODVERSIONS is not set
148# CONFIG_MODULE_SRCVERSION_ALL is not set 157# CONFIG_MODULE_SRCVERSION_ALL is not set
149# CONFIG_KMOD is not set 158CONFIG_KMOD=y
150CONFIG_STOP_MACHINE=y 159CONFIG_STOP_MACHINE=y
151CONFIG_BLOCK=y 160CONFIG_BLOCK=y
152CONFIG_BLK_DEV_IO_TRACE=y 161CONFIG_BLK_DEV_IO_TRACE=y
153CONFIG_BLK_DEV_BSG=y 162CONFIG_BLK_DEV_BSG=y
163# CONFIG_BLK_DEV_INTEGRITY is not set
154CONFIG_BLOCK_COMPAT=y 164CONFIG_BLOCK_COMPAT=y
155 165
156# 166#
@@ -175,20 +185,15 @@ CONFIG_NO_HZ=y
175CONFIG_HIGH_RES_TIMERS=y 185CONFIG_HIGH_RES_TIMERS=y
176CONFIG_GENERIC_CLOCKEVENTS_BUILD=y 186CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
177CONFIG_SMP=y 187CONFIG_SMP=y
188CONFIG_X86_FIND_SMP_CONFIG=y
189CONFIG_X86_MPPARSE=y
178CONFIG_X86_PC=y 190CONFIG_X86_PC=y
179# CONFIG_X86_ELAN is not set 191# CONFIG_X86_ELAN is not set
180# CONFIG_X86_VOYAGER is not set 192# CONFIG_X86_VOYAGER is not set
181# CONFIG_X86_NUMAQ is not set
182# CONFIG_X86_SUMMIT is not set
183# CONFIG_X86_BIGSMP is not set
184# CONFIG_X86_VISWS is not set
185# CONFIG_X86_GENERICARCH is not set 193# CONFIG_X86_GENERICARCH is not set
186# CONFIG_X86_ES7000 is not set
187# CONFIG_X86_RDC321X is not set
188# CONFIG_X86_VSMP is not set 194# CONFIG_X86_VSMP is not set
189# CONFIG_PARAVIRT_GUEST is not set 195# CONFIG_PARAVIRT_GUEST is not set
190CONFIG_MEMTEST_BOOTPARAM=y 196# CONFIG_MEMTEST is not set
191CONFIG_MEMTEST_BOOTPARAM_VALUE=0
192# CONFIG_M386 is not set 197# CONFIG_M386 is not set
193# CONFIG_M486 is not set 198# CONFIG_M486 is not set
194# CONFIG_M586 is not set 199# CONFIG_M586 is not set
@@ -220,11 +225,12 @@ CONFIG_X86_L1_CACHE_BYTES=64
220CONFIG_X86_INTERNODE_CACHE_BYTES=64 225CONFIG_X86_INTERNODE_CACHE_BYTES=64
221CONFIG_X86_CMPXCHG=y 226CONFIG_X86_CMPXCHG=y
222CONFIG_X86_L1_CACHE_SHIFT=6 227CONFIG_X86_L1_CACHE_SHIFT=6
223CONFIG_X86_GOOD_APIC=y 228CONFIG_X86_WP_WORKS_OK=y
224CONFIG_X86_INTEL_USERCOPY=y 229CONFIG_X86_INTEL_USERCOPY=y
225CONFIG_X86_USE_PPRO_CHECKSUM=y 230CONFIG_X86_USE_PPRO_CHECKSUM=y
226CONFIG_X86_P6_NOP=y 231CONFIG_X86_P6_NOP=y
227CONFIG_X86_TSC=y 232CONFIG_X86_TSC=y
233CONFIG_X86_CMPXCHG64=y
228CONFIG_X86_CMOV=y 234CONFIG_X86_CMOV=y
229CONFIG_X86_MINIMUM_CPU_FAMILY=64 235CONFIG_X86_MINIMUM_CPU_FAMILY=64
230CONFIG_X86_DEBUGCTLMSR=y 236CONFIG_X86_DEBUGCTLMSR=y
@@ -234,8 +240,10 @@ CONFIG_DMI=y
234CONFIG_GART_IOMMU=y 240CONFIG_GART_IOMMU=y
235CONFIG_CALGARY_IOMMU=y 241CONFIG_CALGARY_IOMMU=y
236CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT=y 242CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT=y
243CONFIG_AMD_IOMMU=y
237CONFIG_SWIOTLB=y 244CONFIG_SWIOTLB=y
238CONFIG_IOMMU_HELPER=y 245CONFIG_IOMMU_HELPER=y
246# CONFIG_MAXSMP is not set
239CONFIG_NR_CPUS=4 247CONFIG_NR_CPUS=4
240# CONFIG_SCHED_SMT is not set 248# CONFIG_SCHED_SMT is not set
241CONFIG_SCHED_MC=y 249CONFIG_SCHED_MC=y
@@ -281,6 +289,7 @@ CONFIG_ZONE_DMA_FLAG=1
281CONFIG_BOUNCE=y 289CONFIG_BOUNCE=y
282CONFIG_VIRT_TO_BUS=y 290CONFIG_VIRT_TO_BUS=y
283CONFIG_MTRR=y 291CONFIG_MTRR=y
292# CONFIG_MTRR_SANITIZER is not set
284# CONFIG_X86_PAT is not set 293# CONFIG_X86_PAT is not set
285CONFIG_EFI=y 294CONFIG_EFI=y
286CONFIG_SECCOMP=y 295CONFIG_SECCOMP=y
@@ -313,6 +322,7 @@ CONFIG_PM_TRACE_RTC=y
313CONFIG_PM_SLEEP_SMP=y 322CONFIG_PM_SLEEP_SMP=y
314CONFIG_PM_SLEEP=y 323CONFIG_PM_SLEEP=y
315CONFIG_SUSPEND=y 324CONFIG_SUSPEND=y
325# CONFIG_PM_TEST_SUSPEND is not set
316CONFIG_SUSPEND_FREEZER=y 326CONFIG_SUSPEND_FREEZER=y
317CONFIG_HIBERNATION=y 327CONFIG_HIBERNATION=y
318CONFIG_PM_STD_PARTITION="" 328CONFIG_PM_STD_PARTITION=""
@@ -339,6 +349,7 @@ CONFIG_ACPI_NUMA=y
339CONFIG_ACPI_BLACKLIST_YEAR=0 349CONFIG_ACPI_BLACKLIST_YEAR=0
340# CONFIG_ACPI_DEBUG is not set 350# CONFIG_ACPI_DEBUG is not set
341CONFIG_ACPI_EC=y 351CONFIG_ACPI_EC=y
352# CONFIG_ACPI_PCI_SLOT is not set
342CONFIG_ACPI_POWER=y 353CONFIG_ACPI_POWER=y
343CONFIG_ACPI_SYSTEM=y 354CONFIG_ACPI_SYSTEM=y
344CONFIG_X86_PM_TIMER=y 355CONFIG_X86_PM_TIMER=y
@@ -437,10 +448,6 @@ CONFIG_IA32_EMULATION=y
437CONFIG_COMPAT=y 448CONFIG_COMPAT=y
438CONFIG_COMPAT_FOR_U64_ALIGNMENT=y 449CONFIG_COMPAT_FOR_U64_ALIGNMENT=y
439CONFIG_SYSVIPC_COMPAT=y 450CONFIG_SYSVIPC_COMPAT=y
440
441#
442# Networking
443#
444CONFIG_NET=y 451CONFIG_NET=y
445 452
446# 453#
@@ -464,7 +471,10 @@ CONFIG_IP_FIB_HASH=y
464CONFIG_IP_MULTIPLE_TABLES=y 471CONFIG_IP_MULTIPLE_TABLES=y
465CONFIG_IP_ROUTE_MULTIPATH=y 472CONFIG_IP_ROUTE_MULTIPATH=y
466CONFIG_IP_ROUTE_VERBOSE=y 473CONFIG_IP_ROUTE_VERBOSE=y
467# CONFIG_IP_PNP is not set 474CONFIG_IP_PNP=y
475CONFIG_IP_PNP_DHCP=y
476CONFIG_IP_PNP_BOOTP=y
477CONFIG_IP_PNP_RARP=y
468# CONFIG_NET_IPIP is not set 478# CONFIG_NET_IPIP is not set
469# CONFIG_NET_IPGRE is not set 479# CONFIG_NET_IPGRE is not set
470CONFIG_IP_MROUTE=y 480CONFIG_IP_MROUTE=y
@@ -607,7 +617,6 @@ CONFIG_NET_SCHED=y
607# CONFIG_NET_SCH_HTB is not set 617# CONFIG_NET_SCH_HTB is not set
608# CONFIG_NET_SCH_HFSC is not set 618# CONFIG_NET_SCH_HFSC is not set
609# CONFIG_NET_SCH_PRIO is not set 619# CONFIG_NET_SCH_PRIO is not set
610# CONFIG_NET_SCH_RR is not set
611# CONFIG_NET_SCH_RED is not set 620# CONFIG_NET_SCH_RED is not set
612# CONFIG_NET_SCH_SFQ is not set 621# CONFIG_NET_SCH_SFQ is not set
613# CONFIG_NET_SCH_TEQL is not set 622# CONFIG_NET_SCH_TEQL is not set
@@ -669,28 +678,19 @@ CONFIG_FIB_RULES=y
669CONFIG_CFG80211=y 678CONFIG_CFG80211=y
670CONFIG_NL80211=y 679CONFIG_NL80211=y
671CONFIG_WIRELESS_EXT=y 680CONFIG_WIRELESS_EXT=y
681CONFIG_WIRELESS_EXT_SYSFS=y
672CONFIG_MAC80211=y 682CONFIG_MAC80211=y
673 683
674# 684#
675# Rate control algorithm selection 685# Rate control algorithm selection
676# 686#
687CONFIG_MAC80211_RC_PID=y
677CONFIG_MAC80211_RC_DEFAULT_PID=y 688CONFIG_MAC80211_RC_DEFAULT_PID=y
678# CONFIG_MAC80211_RC_DEFAULT_NONE is not set
679
680#
681# Selecting 'y' for an algorithm will
682#
683
684#
685# build the algorithm into mac80211.
686#
687CONFIG_MAC80211_RC_DEFAULT="pid" 689CONFIG_MAC80211_RC_DEFAULT="pid"
688CONFIG_MAC80211_RC_PID=y
689# CONFIG_MAC80211_MESH is not set 690# CONFIG_MAC80211_MESH is not set
690CONFIG_MAC80211_LEDS=y 691CONFIG_MAC80211_LEDS=y
691# CONFIG_MAC80211_DEBUGFS is not set 692# CONFIG_MAC80211_DEBUGFS is not set
692# CONFIG_MAC80211_DEBUG_PACKET_ALIGNMENT is not set 693# CONFIG_MAC80211_DEBUG_MENU is not set
693# CONFIG_MAC80211_DEBUG is not set
694# CONFIG_IEEE80211 is not set 694# CONFIG_IEEE80211 is not set
695# CONFIG_RFKILL is not set 695# CONFIG_RFKILL is not set
696# CONFIG_NET_9P is not set 696# CONFIG_NET_9P is not set
@@ -706,6 +706,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
706CONFIG_STANDALONE=y 706CONFIG_STANDALONE=y
707CONFIG_PREVENT_FIRMWARE_BUILD=y 707CONFIG_PREVENT_FIRMWARE_BUILD=y
708CONFIG_FW_LOADER=y 708CONFIG_FW_LOADER=y
709CONFIG_FIRMWARE_IN_KERNEL=y
710CONFIG_EXTRA_FIRMWARE=""
709# CONFIG_DEBUG_DRIVER is not set 711# CONFIG_DEBUG_DRIVER is not set
710CONFIG_DEBUG_DEVRES=y 712CONFIG_DEBUG_DEVRES=y
711# CONFIG_SYS_HYPERVISOR is not set 713# CONFIG_SYS_HYPERVISOR is not set
@@ -738,6 +740,7 @@ CONFIG_BLK_DEV_RAM_SIZE=16384
738# CONFIG_BLK_DEV_XIP is not set 740# CONFIG_BLK_DEV_XIP is not set
739# CONFIG_CDROM_PKTCDVD is not set 741# CONFIG_CDROM_PKTCDVD is not set
740# CONFIG_ATA_OVER_ETH is not set 742# CONFIG_ATA_OVER_ETH is not set
743# CONFIG_BLK_DEV_HD is not set
741CONFIG_MISC_DEVICES=y 744CONFIG_MISC_DEVICES=y
742# CONFIG_IBM_ASM is not set 745# CONFIG_IBM_ASM is not set
743# CONFIG_PHANTOM is not set 746# CONFIG_PHANTOM is not set
@@ -748,10 +751,14 @@ CONFIG_MISC_DEVICES=y
748# CONFIG_ASUS_LAPTOP is not set 751# CONFIG_ASUS_LAPTOP is not set
749# CONFIG_FUJITSU_LAPTOP is not set 752# CONFIG_FUJITSU_LAPTOP is not set
750# CONFIG_MSI_LAPTOP is not set 753# CONFIG_MSI_LAPTOP is not set
754# CONFIG_COMPAL_LAPTOP is not set
751# CONFIG_SONY_LAPTOP is not set 755# CONFIG_SONY_LAPTOP is not set
752# CONFIG_THINKPAD_ACPI is not set 756# CONFIG_THINKPAD_ACPI is not set
753# CONFIG_INTEL_MENLOW is not set 757# CONFIG_INTEL_MENLOW is not set
754# CONFIG_ENCLOSURE_SERVICES is not set 758# CONFIG_ENCLOSURE_SERVICES is not set
759# CONFIG_SGI_XP is not set
760# CONFIG_HP_ILO is not set
761# CONFIG_SGI_GRU is not set
755CONFIG_HAVE_IDE=y 762CONFIG_HAVE_IDE=y
756# CONFIG_IDE is not set 763# CONFIG_IDE is not set
757 764
@@ -790,12 +797,13 @@ CONFIG_SCSI_WAIT_SCAN=m
790# 797#
791CONFIG_SCSI_SPI_ATTRS=y 798CONFIG_SCSI_SPI_ATTRS=y
792# CONFIG_SCSI_FC_ATTRS is not set 799# CONFIG_SCSI_FC_ATTRS is not set
793# CONFIG_SCSI_ISCSI_ATTRS is not set 800CONFIG_SCSI_ISCSI_ATTRS=y
794# CONFIG_SCSI_SAS_ATTRS is not set 801# CONFIG_SCSI_SAS_ATTRS is not set
795# CONFIG_SCSI_SAS_LIBSAS is not set 802# CONFIG_SCSI_SAS_LIBSAS is not set
796# CONFIG_SCSI_SRP_ATTRS is not set 803# CONFIG_SCSI_SRP_ATTRS is not set
797# CONFIG_SCSI_LOWLEVEL is not set 804# CONFIG_SCSI_LOWLEVEL is not set
798# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set 805# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
806# CONFIG_SCSI_DH is not set
799CONFIG_ATA=y 807CONFIG_ATA=y
800# CONFIG_ATA_NONSTANDARD is not set 808# CONFIG_ATA_NONSTANDARD is not set
801CONFIG_ATA_ACPI=y 809CONFIG_ATA_ACPI=y
@@ -857,6 +865,7 @@ CONFIG_PATA_OLDPIIX=y
857# CONFIG_PATA_SIS is not set 865# CONFIG_PATA_SIS is not set
858# CONFIG_PATA_VIA is not set 866# CONFIG_PATA_VIA is not set
859# CONFIG_PATA_WINBOND is not set 867# CONFIG_PATA_WINBOND is not set
868CONFIG_PATA_SCH=y
860CONFIG_MD=y 869CONFIG_MD=y
861CONFIG_BLK_DEV_MD=y 870CONFIG_BLK_DEV_MD=y
862# CONFIG_MD_LINEAR is not set 871# CONFIG_MD_LINEAR is not set
@@ -880,13 +889,16 @@ CONFIG_DM_ZERO=y
880# 889#
881# IEEE 1394 (FireWire) support 890# IEEE 1394 (FireWire) support
882# 891#
892
893#
894# Enable only one of the two stacks, unless you know what you are doing
895#
883# CONFIG_FIREWIRE is not set 896# CONFIG_FIREWIRE is not set
884# CONFIG_IEEE1394 is not set 897# CONFIG_IEEE1394 is not set
885# CONFIG_I2O is not set 898# CONFIG_I2O is not set
886CONFIG_MACINTOSH_DRIVERS=y 899CONFIG_MACINTOSH_DRIVERS=y
887CONFIG_MAC_EMUMOUSEBTN=y 900CONFIG_MAC_EMUMOUSEBTN=y
888CONFIG_NETDEVICES=y 901CONFIG_NETDEVICES=y
889# CONFIG_NETDEVICES_MULTIQUEUE is not set
890# CONFIG_IFB is not set 902# CONFIG_IFB is not set
891# CONFIG_DUMMY is not set 903# CONFIG_DUMMY is not set
892# CONFIG_BONDING is not set 904# CONFIG_BONDING is not set
@@ -896,7 +908,23 @@ CONFIG_NETDEVICES=y
896# CONFIG_VETH is not set 908# CONFIG_VETH is not set
897# CONFIG_NET_SB1000 is not set 909# CONFIG_NET_SB1000 is not set
898# CONFIG_ARCNET is not set 910# CONFIG_ARCNET is not set
899# CONFIG_PHYLIB is not set 911CONFIG_PHYLIB=y
912
913#
914# MII PHY device drivers
915#
916# CONFIG_MARVELL_PHY is not set
917# CONFIG_DAVICOM_PHY is not set
918# CONFIG_QSEMI_PHY is not set
919# CONFIG_LXT_PHY is not set
920# CONFIG_CICADA_PHY is not set
921# CONFIG_VITESSE_PHY is not set
922# CONFIG_SMSC_PHY is not set
923# CONFIG_BROADCOM_PHY is not set
924# CONFIG_ICPLUS_PHY is not set
925# CONFIG_REALTEK_PHY is not set
926# CONFIG_FIXED_PHY is not set
927# CONFIG_MDIO_BITBANG is not set
900CONFIG_NET_ETHERNET=y 928CONFIG_NET_ETHERNET=y
901CONFIG_MII=y 929CONFIG_MII=y
902# CONFIG_HAPPYMEAL is not set 930# CONFIG_HAPPYMEAL is not set
@@ -940,16 +968,15 @@ CONFIG_8139TOO_PIO=y
940# CONFIG_SIS900 is not set 968# CONFIG_SIS900 is not set
941# CONFIG_EPIC100 is not set 969# CONFIG_EPIC100 is not set
942# CONFIG_SUNDANCE is not set 970# CONFIG_SUNDANCE is not set
971# CONFIG_TLAN is not set
943# CONFIG_VIA_RHINE is not set 972# CONFIG_VIA_RHINE is not set
944# CONFIG_SC92031 is not set 973# CONFIG_SC92031 is not set
945CONFIG_NETDEV_1000=y 974CONFIG_NETDEV_1000=y
946# CONFIG_ACENIC is not set 975# CONFIG_ACENIC is not set
947# CONFIG_DL2K is not set 976# CONFIG_DL2K is not set
948CONFIG_E1000=y 977CONFIG_E1000=y
949# CONFIG_E1000_NAPI is not set
950# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set 978# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
951# CONFIG_E1000E is not set 979# CONFIG_E1000E is not set
952# CONFIG_E1000E_ENABLED is not set
953# CONFIG_IP1000 is not set 980# CONFIG_IP1000 is not set
954# CONFIG_IGB is not set 981# CONFIG_IGB is not set
955# CONFIG_NS83820 is not set 982# CONFIG_NS83820 is not set
@@ -965,6 +992,7 @@ CONFIG_TIGON3=y
965# CONFIG_BNX2 is not set 992# CONFIG_BNX2 is not set
966# CONFIG_QLA3XXX is not set 993# CONFIG_QLA3XXX is not set
967# CONFIG_ATL1 is not set 994# CONFIG_ATL1 is not set
995# CONFIG_ATL1E is not set
968CONFIG_NETDEV_10000=y 996CONFIG_NETDEV_10000=y
969# CONFIG_CHELSIO_T1 is not set 997# CONFIG_CHELSIO_T1 is not set
970# CONFIG_CHELSIO_T3 is not set 998# CONFIG_CHELSIO_T3 is not set
@@ -1003,13 +1031,14 @@ CONFIG_WLAN_80211=y
1003# CONFIG_RTL8180 is not set 1031# CONFIG_RTL8180 is not set
1004# CONFIG_RTL8187 is not set 1032# CONFIG_RTL8187 is not set
1005# CONFIG_ADM8211 is not set 1033# CONFIG_ADM8211 is not set
1034# CONFIG_MAC80211_HWSIM is not set
1006# CONFIG_P54_COMMON is not set 1035# CONFIG_P54_COMMON is not set
1007CONFIG_ATH5K=y 1036CONFIG_ATH5K=y
1008# CONFIG_ATH5K_DEBUG is not set 1037# CONFIG_ATH5K_DEBUG is not set
1009# CONFIG_IWLWIFI is not set 1038# CONFIG_ATH9K is not set
1010# CONFIG_IWLCORE is not set 1039# CONFIG_IWLCORE is not set
1011# CONFIG_IWLWIFI_LEDS is not set 1040# CONFIG_IWLWIFI_LEDS is not set
1012# CONFIG_IWL4965 is not set 1041# CONFIG_IWLAGN is not set
1013# CONFIG_IWL3945 is not set 1042# CONFIG_IWL3945 is not set
1014# CONFIG_HOSTAP is not set 1043# CONFIG_HOSTAP is not set
1015# CONFIG_B43 is not set 1044# CONFIG_B43 is not set
@@ -1088,6 +1117,7 @@ CONFIG_MOUSE_PS2_TRACKPOINT=y
1088# CONFIG_MOUSE_PS2_TOUCHKIT is not set 1117# CONFIG_MOUSE_PS2_TOUCHKIT is not set
1089# CONFIG_MOUSE_SERIAL is not set 1118# CONFIG_MOUSE_SERIAL is not set
1090# CONFIG_MOUSE_APPLETOUCH is not set 1119# CONFIG_MOUSE_APPLETOUCH is not set
1120# CONFIG_MOUSE_BCM5974 is not set
1091# CONFIG_MOUSE_VSXXXAA is not set 1121# CONFIG_MOUSE_VSXXXAA is not set
1092CONFIG_INPUT_JOYSTICK=y 1122CONFIG_INPUT_JOYSTICK=y
1093# CONFIG_JOYSTICK_ANALOG is not set 1123# CONFIG_JOYSTICK_ANALOG is not set
@@ -1122,12 +1152,14 @@ CONFIG_INPUT_TOUCHSCREEN=y
1122# CONFIG_TOUCHSCREEN_GUNZE is not set 1152# CONFIG_TOUCHSCREEN_GUNZE is not set
1123# CONFIG_TOUCHSCREEN_ELO is not set 1153# CONFIG_TOUCHSCREEN_ELO is not set
1124# CONFIG_TOUCHSCREEN_MTOUCH is not set 1154# CONFIG_TOUCHSCREEN_MTOUCH is not set
1155# CONFIG_TOUCHSCREEN_INEXIO is not set
1125# CONFIG_TOUCHSCREEN_MK712 is not set 1156# CONFIG_TOUCHSCREEN_MK712 is not set
1126# CONFIG_TOUCHSCREEN_PENMOUNT is not set 1157# CONFIG_TOUCHSCREEN_PENMOUNT is not set
1127# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set 1158# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
1128# CONFIG_TOUCHSCREEN_TOUCHWIN is not set 1159# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
1129# CONFIG_TOUCHSCREEN_UCB1400 is not set 1160# CONFIG_TOUCHSCREEN_UCB1400 is not set
1130# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set 1161# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
1162# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
1131CONFIG_INPUT_MISC=y 1163CONFIG_INPUT_MISC=y
1132# CONFIG_INPUT_PCSPKR is not set 1164# CONFIG_INPUT_PCSPKR is not set
1133# CONFIG_INPUT_APANEL is not set 1165# CONFIG_INPUT_APANEL is not set
@@ -1155,6 +1187,7 @@ CONFIG_SERIO_LIBPS2=y
1155# Character devices 1187# Character devices
1156# 1188#
1157CONFIG_VT=y 1189CONFIG_VT=y
1190CONFIG_CONSOLE_TRANSLATIONS=y
1158CONFIG_VT_CONSOLE=y 1191CONFIG_VT_CONSOLE=y
1159CONFIG_HW_CONSOLE=y 1192CONFIG_HW_CONSOLE=y
1160CONFIG_VT_HW_CONSOLE_BINDING=y 1193CONFIG_VT_HW_CONSOLE_BINDING=y
@@ -1222,7 +1255,6 @@ CONFIG_NVRAM=y
1222# CONFIG_PC8736x_GPIO is not set 1255# CONFIG_PC8736x_GPIO is not set
1223# CONFIG_RAW_DRIVER is not set 1256# CONFIG_RAW_DRIVER is not set
1224CONFIG_HPET=y 1257CONFIG_HPET=y
1225# CONFIG_HPET_RTC_IRQ is not set
1226# CONFIG_HPET_MMAP is not set 1258# CONFIG_HPET_MMAP is not set
1227# CONFIG_HANGCHECK_TIMER is not set 1259# CONFIG_HANGCHECK_TIMER is not set
1228# CONFIG_TCG_TPM is not set 1260# CONFIG_TCG_TPM is not set
@@ -1231,42 +1263,63 @@ CONFIG_DEVPORT=y
1231CONFIG_I2C=y 1263CONFIG_I2C=y
1232CONFIG_I2C_BOARDINFO=y 1264CONFIG_I2C_BOARDINFO=y
1233# CONFIG_I2C_CHARDEV is not set 1265# CONFIG_I2C_CHARDEV is not set
1266CONFIG_I2C_HELPER_AUTO=y
1234 1267
1235# 1268#
1236# I2C Hardware Bus support 1269# I2C Hardware Bus support
1237# 1270#
1271
1272#
1273# PC SMBus host controller drivers
1274#
1238# CONFIG_I2C_ALI1535 is not set 1275# CONFIG_I2C_ALI1535 is not set
1239# CONFIG_I2C_ALI1563 is not set 1276# CONFIG_I2C_ALI1563 is not set
1240# CONFIG_I2C_ALI15X3 is not set 1277# CONFIG_I2C_ALI15X3 is not set
1241# CONFIG_I2C_AMD756 is not set 1278# CONFIG_I2C_AMD756 is not set
1242# CONFIG_I2C_AMD8111 is not set 1279# CONFIG_I2C_AMD8111 is not set
1243CONFIG_I2C_I801=y 1280CONFIG_I2C_I801=y
1244# CONFIG_I2C_I810 is not set 1281# CONFIG_I2C_ISCH is not set
1245# CONFIG_I2C_PIIX4 is not set 1282# CONFIG_I2C_PIIX4 is not set
1246# CONFIG_I2C_NFORCE2 is not set 1283# CONFIG_I2C_NFORCE2 is not set
1247# CONFIG_I2C_OCORES is not set
1248# CONFIG_I2C_PARPORT_LIGHT is not set
1249# CONFIG_I2C_PROSAVAGE is not set
1250# CONFIG_I2C_SAVAGE4 is not set
1251# CONFIG_I2C_SIMTEC is not set
1252# CONFIG_I2C_SIS5595 is not set 1284# CONFIG_I2C_SIS5595 is not set
1253# CONFIG_I2C_SIS630 is not set 1285# CONFIG_I2C_SIS630 is not set
1254# CONFIG_I2C_SIS96X is not set 1286# CONFIG_I2C_SIS96X is not set
1255# CONFIG_I2C_TAOS_EVM is not set
1256# CONFIG_I2C_STUB is not set
1257# CONFIG_I2C_TINY_USB is not set
1258# CONFIG_I2C_VIA is not set 1287# CONFIG_I2C_VIA is not set
1259# CONFIG_I2C_VIAPRO is not set 1288# CONFIG_I2C_VIAPRO is not set
1289
1290#
1291# I2C system bus drivers (mostly embedded / system-on-chip)
1292#
1293# CONFIG_I2C_OCORES is not set
1294# CONFIG_I2C_SIMTEC is not set
1295
1296#
1297# External I2C/SMBus adapter drivers
1298#
1299# CONFIG_I2C_PARPORT_LIGHT is not set
1300# CONFIG_I2C_TAOS_EVM is not set
1301# CONFIG_I2C_TINY_USB is not set
1302
1303#
1304# Graphics adapter I2C/DDC channel drivers
1305#
1260# CONFIG_I2C_VOODOO3 is not set 1306# CONFIG_I2C_VOODOO3 is not set
1307
1308#
1309# Other I2C/SMBus bus drivers
1310#
1261# CONFIG_I2C_PCA_PLATFORM is not set 1311# CONFIG_I2C_PCA_PLATFORM is not set
1312# CONFIG_I2C_STUB is not set
1262 1313
1263# 1314#
1264# Miscellaneous I2C Chip support 1315# Miscellaneous I2C Chip support
1265# 1316#
1266# CONFIG_DS1682 is not set 1317# CONFIG_DS1682 is not set
1318# CONFIG_AT24 is not set
1267# CONFIG_SENSORS_EEPROM is not set 1319# CONFIG_SENSORS_EEPROM is not set
1268# CONFIG_SENSORS_PCF8574 is not set 1320# CONFIG_SENSORS_PCF8574 is not set
1269# CONFIG_PCF8575 is not set 1321# CONFIG_PCF8575 is not set
1322# CONFIG_SENSORS_PCA9539 is not set
1270# CONFIG_SENSORS_PCF8591 is not set 1323# CONFIG_SENSORS_PCF8591 is not set
1271# CONFIG_SENSORS_MAX6875 is not set 1324# CONFIG_SENSORS_MAX6875 is not set
1272# CONFIG_SENSORS_TSL2550 is not set 1325# CONFIG_SENSORS_TSL2550 is not set
@@ -1275,6 +1328,8 @@ CONFIG_I2C_I801=y
1275# CONFIG_I2C_DEBUG_BUS is not set 1328# CONFIG_I2C_DEBUG_BUS is not set
1276# CONFIG_I2C_DEBUG_CHIP is not set 1329# CONFIG_I2C_DEBUG_CHIP is not set
1277# CONFIG_SPI is not set 1330# CONFIG_SPI is not set
1331CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
1332# CONFIG_GPIOLIB is not set
1278# CONFIG_W1 is not set 1333# CONFIG_W1 is not set
1279CONFIG_POWER_SUPPLY=y 1334CONFIG_POWER_SUPPLY=y
1280# CONFIG_POWER_SUPPLY_DEBUG is not set 1335# CONFIG_POWER_SUPPLY_DEBUG is not set
@@ -1335,8 +1390,10 @@ CONFIG_SSB_POSSIBLE=y
1335# 1390#
1336# Multifunction device drivers 1391# Multifunction device drivers
1337# 1392#
1393# CONFIG_MFD_CORE is not set
1338# CONFIG_MFD_SM501 is not set 1394# CONFIG_MFD_SM501 is not set
1339# CONFIG_HTC_PASIC3 is not set 1395# CONFIG_HTC_PASIC3 is not set
1396# CONFIG_MFD_TMIO is not set
1340 1397
1341# 1398#
1342# Multimedia devices 1399# Multimedia devices
@@ -1347,6 +1404,7 @@ CONFIG_SSB_POSSIBLE=y
1347# 1404#
1348# CONFIG_VIDEO_DEV is not set 1405# CONFIG_VIDEO_DEV is not set
1349# CONFIG_DVB_CORE is not set 1406# CONFIG_DVB_CORE is not set
1407# CONFIG_VIDEO_MEDIA is not set
1350 1408
1351# 1409#
1352# Multimedia drivers 1410# Multimedia drivers
@@ -1387,7 +1445,6 @@ CONFIG_FB_CFB_IMAGEBLIT=y
1387# CONFIG_FB_SYS_IMAGEBLIT is not set 1445# CONFIG_FB_SYS_IMAGEBLIT is not set
1388# CONFIG_FB_FOREIGN_ENDIAN is not set 1446# CONFIG_FB_FOREIGN_ENDIAN is not set
1389# CONFIG_FB_SYS_FOPS is not set 1447# CONFIG_FB_SYS_FOPS is not set
1390CONFIG_FB_DEFERRED_IO=y
1391# CONFIG_FB_SVGALIB is not set 1448# CONFIG_FB_SVGALIB is not set
1392# CONFIG_FB_MACMODES is not set 1449# CONFIG_FB_MACMODES is not set
1393# CONFIG_FB_BACKLIGHT is not set 1450# CONFIG_FB_BACKLIGHT is not set
@@ -1430,6 +1487,7 @@ CONFIG_FB_EFI=y
1430# CONFIG_FB_TRIDENT is not set 1487# CONFIG_FB_TRIDENT is not set
1431# CONFIG_FB_ARK is not set 1488# CONFIG_FB_ARK is not set
1432# CONFIG_FB_PM3 is not set 1489# CONFIG_FB_PM3 is not set
1490# CONFIG_FB_CARMINE is not set
1433# CONFIG_FB_GEODE is not set 1491# CONFIG_FB_GEODE is not set
1434# CONFIG_FB_VIRTUAL is not set 1492# CONFIG_FB_VIRTUAL is not set
1435CONFIG_BACKLIGHT_LCD_SUPPORT=y 1493CONFIG_BACKLIGHT_LCD_SUPPORT=y
@@ -1437,6 +1495,7 @@ CONFIG_BACKLIGHT_LCD_SUPPORT=y
1437CONFIG_BACKLIGHT_CLASS_DEVICE=y 1495CONFIG_BACKLIGHT_CLASS_DEVICE=y
1438# CONFIG_BACKLIGHT_CORGI is not set 1496# CONFIG_BACKLIGHT_CORGI is not set
1439# CONFIG_BACKLIGHT_PROGEAR is not set 1497# CONFIG_BACKLIGHT_PROGEAR is not set
1498# CONFIG_BACKLIGHT_MBP_NVIDIA is not set
1440 1499
1441# 1500#
1442# Display device support 1501# Display device support
@@ -1456,15 +1515,7 @@ CONFIG_LOGO=y
1456# CONFIG_LOGO_LINUX_MONO is not set 1515# CONFIG_LOGO_LINUX_MONO is not set
1457# CONFIG_LOGO_LINUX_VGA16 is not set 1516# CONFIG_LOGO_LINUX_VGA16 is not set
1458CONFIG_LOGO_LINUX_CLUT224=y 1517CONFIG_LOGO_LINUX_CLUT224=y
1459
1460#
1461# Sound
1462#
1463CONFIG_SOUND=y 1518CONFIG_SOUND=y
1464
1465#
1466# Advanced Linux Sound Architecture
1467#
1468CONFIG_SND=y 1519CONFIG_SND=y
1469CONFIG_SND_TIMER=y 1520CONFIG_SND_TIMER=y
1470CONFIG_SND_PCM=y 1521CONFIG_SND_PCM=y
@@ -1482,20 +1533,14 @@ CONFIG_SND_VERBOSE_PROCFS=y
1482# CONFIG_SND_VERBOSE_PRINTK is not set 1533# CONFIG_SND_VERBOSE_PRINTK is not set
1483# CONFIG_SND_DEBUG is not set 1534# CONFIG_SND_DEBUG is not set
1484CONFIG_SND_VMASTER=y 1535CONFIG_SND_VMASTER=y
1485 1536CONFIG_SND_DRIVERS=y
1486#
1487# Generic devices
1488#
1489# CONFIG_SND_PCSP is not set 1537# CONFIG_SND_PCSP is not set
1490# CONFIG_SND_DUMMY is not set 1538# CONFIG_SND_DUMMY is not set
1491# CONFIG_SND_VIRMIDI is not set 1539# CONFIG_SND_VIRMIDI is not set
1492# CONFIG_SND_MTPAV is not set 1540# CONFIG_SND_MTPAV is not set
1493# CONFIG_SND_SERIAL_U16550 is not set 1541# CONFIG_SND_SERIAL_U16550 is not set
1494# CONFIG_SND_MPU401 is not set 1542# CONFIG_SND_MPU401 is not set
1495 1543CONFIG_SND_PCI=y
1496#
1497# PCI devices
1498#
1499# CONFIG_SND_AD1889 is not set 1544# CONFIG_SND_AD1889 is not set
1500# CONFIG_SND_ALS300 is not set 1545# CONFIG_SND_ALS300 is not set
1501# CONFIG_SND_ALS4000 is not set 1546# CONFIG_SND_ALS4000 is not set
@@ -1568,36 +1613,14 @@ CONFIG_SND_HDA_GENERIC=y
1568# CONFIG_SND_VIRTUOSO is not set 1613# CONFIG_SND_VIRTUOSO is not set
1569# CONFIG_SND_VX222 is not set 1614# CONFIG_SND_VX222 is not set
1570# CONFIG_SND_YMFPCI is not set 1615# CONFIG_SND_YMFPCI is not set
1571 1616CONFIG_SND_USB=y
1572#
1573# USB devices
1574#
1575# CONFIG_SND_USB_AUDIO is not set 1617# CONFIG_SND_USB_AUDIO is not set
1576# CONFIG_SND_USB_USX2Y is not set 1618# CONFIG_SND_USB_USX2Y is not set
1577# CONFIG_SND_USB_CAIAQ is not set 1619# CONFIG_SND_USB_CAIAQ is not set
1578 1620CONFIG_SND_PCMCIA=y
1579#
1580# PCMCIA devices
1581#
1582# CONFIG_SND_VXPOCKET is not set 1621# CONFIG_SND_VXPOCKET is not set
1583# CONFIG_SND_PDAUDIOCF is not set 1622# CONFIG_SND_PDAUDIOCF is not set
1584
1585#
1586# System on Chip audio support
1587#
1588# CONFIG_SND_SOC is not set 1623# CONFIG_SND_SOC is not set
1589
1590#
1591# ALSA SoC audio for Freescale SOCs
1592#
1593
1594#
1595# SoC Audio for the Texas Instruments OMAP
1596#
1597
1598#
1599# Open Sound System
1600#
1601# CONFIG_SOUND_PRIME is not set 1624# CONFIG_SOUND_PRIME is not set
1602CONFIG_HID_SUPPORT=y 1625CONFIG_HID_SUPPORT=y
1603CONFIG_HID=y 1626CONFIG_HID=y
@@ -1633,6 +1656,7 @@ CONFIG_USB_DEVICEFS=y
1633# CONFIG_USB_DYNAMIC_MINORS is not set 1656# CONFIG_USB_DYNAMIC_MINORS is not set
1634CONFIG_USB_SUSPEND=y 1657CONFIG_USB_SUSPEND=y
1635# CONFIG_USB_OTG is not set 1658# CONFIG_USB_OTG is not set
1659CONFIG_USB_MON=y
1636 1660
1637# 1661#
1638# USB Host Controller Drivers 1662# USB Host Controller Drivers
@@ -1656,6 +1680,7 @@ CONFIG_USB_UHCI_HCD=y
1656# 1680#
1657# CONFIG_USB_ACM is not set 1681# CONFIG_USB_ACM is not set
1658CONFIG_USB_PRINTER=y 1682CONFIG_USB_PRINTER=y
1683# CONFIG_USB_WDM is not set
1659 1684
1660# 1685#
1661# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 1686# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
@@ -1677,6 +1702,7 @@ CONFIG_USB_STORAGE=y
1677# CONFIG_USB_STORAGE_ALAUDA is not set 1702# CONFIG_USB_STORAGE_ALAUDA is not set
1678# CONFIG_USB_STORAGE_ONETOUCH is not set 1703# CONFIG_USB_STORAGE_ONETOUCH is not set
1679# CONFIG_USB_STORAGE_KARMA is not set 1704# CONFIG_USB_STORAGE_KARMA is not set
1705# CONFIG_USB_STORAGE_SIERRA is not set
1680# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set 1706# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
1681CONFIG_USB_LIBUSUAL=y 1707CONFIG_USB_LIBUSUAL=y
1682 1708
@@ -1685,7 +1711,6 @@ CONFIG_USB_LIBUSUAL=y
1685# 1711#
1686# CONFIG_USB_MDC800 is not set 1712# CONFIG_USB_MDC800 is not set
1687# CONFIG_USB_MICROTEK is not set 1713# CONFIG_USB_MICROTEK is not set
1688CONFIG_USB_MON=y
1689 1714
1690# 1715#
1691# USB port drivers 1716# USB port drivers
@@ -1698,7 +1723,6 @@ CONFIG_USB_MON=y
1698# CONFIG_USB_EMI62 is not set 1723# CONFIG_USB_EMI62 is not set
1699# CONFIG_USB_EMI26 is not set 1724# CONFIG_USB_EMI26 is not set
1700# CONFIG_USB_ADUTUX is not set 1725# CONFIG_USB_ADUTUX is not set
1701# CONFIG_USB_AUERSWALD is not set
1702# CONFIG_USB_RIO500 is not set 1726# CONFIG_USB_RIO500 is not set
1703# CONFIG_USB_LEGOTOWER is not set 1727# CONFIG_USB_LEGOTOWER is not set
1704# CONFIG_USB_LCD is not set 1728# CONFIG_USB_LCD is not set
@@ -1715,6 +1739,7 @@ CONFIG_USB_MON=y
1715# CONFIG_USB_TRANCEVIBRATOR is not set 1739# CONFIG_USB_TRANCEVIBRATOR is not set
1716# CONFIG_USB_IOWARRIOR is not set 1740# CONFIG_USB_IOWARRIOR is not set
1717# CONFIG_USB_TEST is not set 1741# CONFIG_USB_TEST is not set
1742# CONFIG_USB_ISIGHTFW is not set
1718# CONFIG_USB_GADGET is not set 1743# CONFIG_USB_GADGET is not set
1719# CONFIG_MMC is not set 1744# CONFIG_MMC is not set
1720# CONFIG_MEMSTICK is not set 1745# CONFIG_MEMSTICK is not set
@@ -1724,7 +1749,9 @@ CONFIG_LEDS_CLASS=y
1724# 1749#
1725# LED drivers 1750# LED drivers
1726# 1751#
1752# CONFIG_LEDS_PCA9532 is not set
1727# CONFIG_LEDS_CLEVO_MAIL is not set 1753# CONFIG_LEDS_CLEVO_MAIL is not set
1754# CONFIG_LEDS_PCA955X is not set
1728 1755
1729# 1756#
1730# LED Triggers 1757# LED Triggers
@@ -1770,6 +1797,7 @@ CONFIG_RTC_INTF_DEV=y
1770# CONFIG_RTC_DRV_PCF8583 is not set 1797# CONFIG_RTC_DRV_PCF8583 is not set
1771# CONFIG_RTC_DRV_M41T80 is not set 1798# CONFIG_RTC_DRV_M41T80 is not set
1772# CONFIG_RTC_DRV_S35390A is not set 1799# CONFIG_RTC_DRV_S35390A is not set
1800# CONFIG_RTC_DRV_FM3130 is not set
1773 1801
1774# 1802#
1775# SPI RTC drivers 1803# SPI RTC drivers
@@ -1802,11 +1830,13 @@ CONFIG_DMADEVICES=y
1802# Firmware Drivers 1830# Firmware Drivers
1803# 1831#
1804# CONFIG_EDD is not set 1832# CONFIG_EDD is not set
1833CONFIG_FIRMWARE_MEMMAP=y
1805CONFIG_EFI_VARS=y 1834CONFIG_EFI_VARS=y
1806# CONFIG_DELL_RBU is not set 1835# CONFIG_DELL_RBU is not set
1807# CONFIG_DCDBAS is not set 1836# CONFIG_DCDBAS is not set
1808CONFIG_DMIID=y 1837CONFIG_DMIID=y
1809# CONFIG_ISCSI_IBFT_FIND is not set 1838CONFIG_ISCSI_IBFT_FIND=y
1839CONFIG_ISCSI_IBFT=y
1810 1840
1811# 1841#
1812# File systems 1842# File systems
@@ -1886,14 +1916,27 @@ CONFIG_HUGETLB_PAGE=y
1886# CONFIG_CRAMFS is not set 1916# CONFIG_CRAMFS is not set
1887# CONFIG_VXFS_FS is not set 1917# CONFIG_VXFS_FS is not set
1888# CONFIG_MINIX_FS is not set 1918# CONFIG_MINIX_FS is not set
1919# CONFIG_OMFS_FS is not set
1889# CONFIG_HPFS_FS is not set 1920# CONFIG_HPFS_FS is not set
1890# CONFIG_QNX4FS_FS is not set 1921# CONFIG_QNX4FS_FS is not set
1891# CONFIG_ROMFS_FS is not set 1922# CONFIG_ROMFS_FS is not set
1892# CONFIG_SYSV_FS is not set 1923# CONFIG_SYSV_FS is not set
1893# CONFIG_UFS_FS is not set 1924# CONFIG_UFS_FS is not set
1894CONFIG_NETWORK_FILESYSTEMS=y 1925CONFIG_NETWORK_FILESYSTEMS=y
1895# CONFIG_NFS_FS is not set 1926CONFIG_NFS_FS=y
1927CONFIG_NFS_V3=y
1928CONFIG_NFS_V3_ACL=y
1929CONFIG_NFS_V4=y
1930CONFIG_ROOT_NFS=y
1896# CONFIG_NFSD is not set 1931# CONFIG_NFSD is not set
1932CONFIG_LOCKD=y
1933CONFIG_LOCKD_V4=y
1934CONFIG_NFS_ACL_SUPPORT=y
1935CONFIG_NFS_COMMON=y
1936CONFIG_SUNRPC=y
1937CONFIG_SUNRPC_GSS=y
1938CONFIG_RPCSEC_GSS_KRB5=y
1939# CONFIG_RPCSEC_GSS_SPKM3 is not set
1897# CONFIG_SMB_FS is not set 1940# CONFIG_SMB_FS is not set
1898# CONFIG_CIFS is not set 1941# CONFIG_CIFS is not set
1899# CONFIG_NCP_FS is not set 1942# CONFIG_NCP_FS is not set
@@ -1967,9 +2010,9 @@ CONFIG_NLS_UTF8=y
1967# Kernel hacking 2010# Kernel hacking
1968# 2011#
1969CONFIG_TRACE_IRQFLAGS_SUPPORT=y 2012CONFIG_TRACE_IRQFLAGS_SUPPORT=y
1970# CONFIG_PRINTK_TIME is not set 2013CONFIG_PRINTK_TIME=y
1971# CONFIG_ENABLE_WARN_DEPRECATED is not set 2014CONFIG_ENABLE_WARN_DEPRECATED=y
1972# CONFIG_ENABLE_MUST_CHECK is not set 2015CONFIG_ENABLE_MUST_CHECK=y
1973CONFIG_FRAME_WARN=2048 2016CONFIG_FRAME_WARN=2048
1974CONFIG_MAGIC_SYSRQ=y 2017CONFIG_MAGIC_SYSRQ=y
1975# CONFIG_UNUSED_SYMBOLS is not set 2018# CONFIG_UNUSED_SYMBOLS is not set
@@ -1998,6 +2041,7 @@ CONFIG_DEBUG_BUGVERBOSE=y
1998# CONFIG_DEBUG_INFO is not set 2041# CONFIG_DEBUG_INFO is not set
1999# CONFIG_DEBUG_VM is not set 2042# CONFIG_DEBUG_VM is not set
2000# CONFIG_DEBUG_WRITECOUNT is not set 2043# CONFIG_DEBUG_WRITECOUNT is not set
2044CONFIG_DEBUG_MEMORY_INIT=y
2001# CONFIG_DEBUG_LIST is not set 2045# CONFIG_DEBUG_LIST is not set
2002# CONFIG_DEBUG_SG is not set 2046# CONFIG_DEBUG_SG is not set
2003CONFIG_FRAME_POINTER=y 2047CONFIG_FRAME_POINTER=y
@@ -2008,11 +2052,20 @@ CONFIG_FRAME_POINTER=y
2008# CONFIG_LKDTM is not set 2052# CONFIG_LKDTM is not set
2009# CONFIG_FAULT_INJECTION is not set 2053# CONFIG_FAULT_INJECTION is not set
2010# CONFIG_LATENCYTOP is not set 2054# CONFIG_LATENCYTOP is not set
2055CONFIG_SYSCTL_SYSCALL_CHECK=y
2056CONFIG_HAVE_FTRACE=y
2057CONFIG_HAVE_DYNAMIC_FTRACE=y
2058# CONFIG_FTRACE is not set
2059# CONFIG_IRQSOFF_TRACER is not set
2060# CONFIG_SYSPROF_TRACER is not set
2061# CONFIG_SCHED_TRACER is not set
2062# CONFIG_CONTEXT_SWITCH_TRACER is not set
2011CONFIG_PROVIDE_OHCI1394_DMA_INIT=y 2063CONFIG_PROVIDE_OHCI1394_DMA_INIT=y
2012# CONFIG_SAMPLES is not set 2064# CONFIG_SAMPLES is not set
2013# CONFIG_KGDB is not set
2014CONFIG_HAVE_ARCH_KGDB=y 2065CONFIG_HAVE_ARCH_KGDB=y
2066# CONFIG_KGDB is not set
2015# CONFIG_STRICT_DEVMEM is not set 2067# CONFIG_STRICT_DEVMEM is not set
2068CONFIG_X86_VERBOSE_BOOTUP=y
2016CONFIG_EARLY_PRINTK=y 2069CONFIG_EARLY_PRINTK=y
2017CONFIG_DEBUG_STACKOVERFLOW=y 2070CONFIG_DEBUG_STACKOVERFLOW=y
2018CONFIG_DEBUG_STACK_USAGE=y 2071CONFIG_DEBUG_STACK_USAGE=y
@@ -2023,8 +2076,8 @@ CONFIG_DEBUG_RODATA=y
2023# CONFIG_DIRECT_GBPAGES is not set 2076# CONFIG_DIRECT_GBPAGES is not set
2024# CONFIG_DEBUG_RODATA_TEST is not set 2077# CONFIG_DEBUG_RODATA_TEST is not set
2025CONFIG_DEBUG_NX_TEST=m 2078CONFIG_DEBUG_NX_TEST=m
2026CONFIG_X86_MPPARSE=y
2027# CONFIG_IOMMU_DEBUG is not set 2079# CONFIG_IOMMU_DEBUG is not set
2080# CONFIG_MMIOTRACE is not set
2028CONFIG_IO_DELAY_TYPE_0X80=0 2081CONFIG_IO_DELAY_TYPE_0X80=0
2029CONFIG_IO_DELAY_TYPE_0XED=1 2082CONFIG_IO_DELAY_TYPE_0XED=1
2030CONFIG_IO_DELAY_TYPE_UDELAY=2 2083CONFIG_IO_DELAY_TYPE_UDELAY=2
@@ -2036,6 +2089,7 @@ CONFIG_IO_DELAY_0X80=y
2036CONFIG_DEFAULT_IO_DELAY_TYPE=0 2089CONFIG_DEFAULT_IO_DELAY_TYPE=0
2037CONFIG_DEBUG_BOOT_PARAMS=y 2090CONFIG_DEBUG_BOOT_PARAMS=y
2038# CONFIG_CPA_DEBUG is not set 2091# CONFIG_CPA_DEBUG is not set
2092# CONFIG_OPTIMIZE_INLINING is not set
2039 2093
2040# 2094#
2041# Security options 2095# Security options
@@ -2045,7 +2099,6 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
2045CONFIG_SECURITY=y 2099CONFIG_SECURITY=y
2046CONFIG_SECURITY_NETWORK=y 2100CONFIG_SECURITY_NETWORK=y
2047# CONFIG_SECURITY_NETWORK_XFRM is not set 2101# CONFIG_SECURITY_NETWORK_XFRM is not set
2048CONFIG_SECURITY_CAPABILITIES=y
2049CONFIG_SECURITY_FILE_CAPABILITIES=y 2102CONFIG_SECURITY_FILE_CAPABILITIES=y
2050# CONFIG_SECURITY_ROOTPLUG is not set 2103# CONFIG_SECURITY_ROOTPLUG is not set
2051CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=65536 2104CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=65536
@@ -2106,6 +2159,10 @@ CONFIG_CRYPTO_HMAC=y
2106# CONFIG_CRYPTO_MD4 is not set 2159# CONFIG_CRYPTO_MD4 is not set
2107CONFIG_CRYPTO_MD5=y 2160CONFIG_CRYPTO_MD5=y
2108# CONFIG_CRYPTO_MICHAEL_MIC is not set 2161# CONFIG_CRYPTO_MICHAEL_MIC is not set
2162# CONFIG_CRYPTO_RMD128 is not set
2163# CONFIG_CRYPTO_RMD160 is not set
2164# CONFIG_CRYPTO_RMD256 is not set
2165# CONFIG_CRYPTO_RMD320 is not set
2109CONFIG_CRYPTO_SHA1=y 2166CONFIG_CRYPTO_SHA1=y
2110# CONFIG_CRYPTO_SHA256 is not set 2167# CONFIG_CRYPTO_SHA256 is not set
2111# CONFIG_CRYPTO_SHA512 is not set 2168# CONFIG_CRYPTO_SHA512 is not set
@@ -2155,6 +2212,7 @@ CONFIG_GENERIC_FIND_FIRST_BIT=y
2155CONFIG_GENERIC_FIND_NEXT_BIT=y 2212CONFIG_GENERIC_FIND_NEXT_BIT=y
2156# CONFIG_CRC_CCITT is not set 2213# CONFIG_CRC_CCITT is not set
2157# CONFIG_CRC16 is not set 2214# CONFIG_CRC16 is not set
2215CONFIG_CRC_T10DIF=y
2158# CONFIG_CRC_ITU_T is not set 2216# CONFIG_CRC_ITU_T is not set
2159CONFIG_CRC32=y 2217CONFIG_CRC32=y
2160# CONFIG_CRC7 is not set 2218# CONFIG_CRC7 is not set
diff --git a/arch/x86/kernel/cpuid.c b/arch/x86/kernel/cpuid.c
index 14b11b3be31c..8e9cd6a8ec12 100644
--- a/arch/x86/kernel/cpuid.c
+++ b/arch/x86/kernel/cpuid.c
@@ -89,6 +89,8 @@ static ssize_t cpuid_read(struct file *file, char __user *buf,
89 struct cpuid_regs cmd; 89 struct cpuid_regs cmd;
90 int cpu = iminor(file->f_path.dentry->d_inode); 90 int cpu = iminor(file->f_path.dentry->d_inode);
91 u64 pos = *ppos; 91 u64 pos = *ppos;
92 ssize_t bytes = 0;
93 int err = 0;
92 94
93 if (count % 16) 95 if (count % 16)
94 return -EINVAL; /* Invalid chunk size */ 96 return -EINVAL; /* Invalid chunk size */
@@ -96,14 +98,19 @@ static ssize_t cpuid_read(struct file *file, char __user *buf,
96 for (; count; count -= 16) { 98 for (; count; count -= 16) {
97 cmd.eax = pos; 99 cmd.eax = pos;
98 cmd.ecx = pos >> 32; 100 cmd.ecx = pos >> 32;
99 smp_call_function_single(cpu, cpuid_smp_cpuid, &cmd, 1); 101 err = smp_call_function_single(cpu, cpuid_smp_cpuid, &cmd, 1);
100 if (copy_to_user(tmp, &cmd, 16)) 102 if (err)
101 return -EFAULT; 103 break;
104 if (copy_to_user(tmp, &cmd, 16)) {
105 err = -EFAULT;
106 break;
107 }
102 tmp += 16; 108 tmp += 16;
109 bytes += 16;
103 *ppos = ++pos; 110 *ppos = ++pos;
104 } 111 }
105 112
106 return tmp - buf; 113 return bytes ? bytes : err;
107} 114}
108 115
109static int cpuid_open(struct inode *inode, struct file *file) 116static int cpuid_open(struct inode *inode, struct file *file)
diff --git a/arch/x86/kernel/msr.c b/arch/x86/kernel/msr.c
index e43938086885..2e2af5d18191 100644
--- a/arch/x86/kernel/msr.c
+++ b/arch/x86/kernel/msr.c
@@ -72,21 +72,28 @@ static ssize_t msr_read(struct file *file, char __user *buf,
72 u32 data[2]; 72 u32 data[2];
73 u32 reg = *ppos; 73 u32 reg = *ppos;
74 int cpu = iminor(file->f_path.dentry->d_inode); 74 int cpu = iminor(file->f_path.dentry->d_inode);
75 int err; 75 int err = 0;
76 ssize_t bytes = 0;
76 77
77 if (count % 8) 78 if (count % 8)
78 return -EINVAL; /* Invalid chunk size */ 79 return -EINVAL; /* Invalid chunk size */
79 80
80 for (; count; count -= 8) { 81 for (; count; count -= 8) {
81 err = rdmsr_safe_on_cpu(cpu, reg, &data[0], &data[1]); 82 err = rdmsr_safe_on_cpu(cpu, reg, &data[0], &data[1]);
82 if (err) 83 if (err) {
83 return -EIO; 84 if (err == -EFAULT) /* Fix idiotic error code */
84 if (copy_to_user(tmp, &data, 8)) 85 err = -EIO;
85 return -EFAULT; 86 break;
87 }
88 if (copy_to_user(tmp, &data, 8)) {
89 err = -EFAULT;
90 break;
91 }
86 tmp += 2; 92 tmp += 2;
93 bytes += 8;
87 } 94 }
88 95
89 return ((char __user *)tmp) - buf; 96 return bytes ? bytes : err;
90} 97}
91 98
92static ssize_t msr_write(struct file *file, const char __user *buf, 99static ssize_t msr_write(struct file *file, const char __user *buf,
@@ -96,21 +103,28 @@ static ssize_t msr_write(struct file *file, const char __user *buf,
96 u32 data[2]; 103 u32 data[2];
97 u32 reg = *ppos; 104 u32 reg = *ppos;
98 int cpu = iminor(file->f_path.dentry->d_inode); 105 int cpu = iminor(file->f_path.dentry->d_inode);
99 int err; 106 int err = 0;
107 ssize_t bytes = 0;
100 108
101 if (count % 8) 109 if (count % 8)
102 return -EINVAL; /* Invalid chunk size */ 110 return -EINVAL; /* Invalid chunk size */
103 111
104 for (; count; count -= 8) { 112 for (; count; count -= 8) {
105 if (copy_from_user(&data, tmp, 8)) 113 if (copy_from_user(&data, tmp, 8)) {
106 return -EFAULT; 114 err = -EFAULT;
115 break;
116 }
107 err = wrmsr_safe_on_cpu(cpu, reg, data[0], data[1]); 117 err = wrmsr_safe_on_cpu(cpu, reg, data[0], data[1]);
108 if (err) 118 if (err) {
109 return -EIO; 119 if (err == -EFAULT) /* Fix idiotic error code */
120 err = -EIO;
121 break;
122 }
110 tmp += 2; 123 tmp += 2;
124 bytes += 8;
111 } 125 }
112 126
113 return ((char __user *)tmp) - buf; 127 return bytes ? bytes : err;
114} 128}
115 129
116static int msr_open(struct inode *inode, struct file *file) 130static int msr_open(struct inode *inode, struct file *file)
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index 8e786b0d665a..ac79bd143da8 100644
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -127,75 +127,202 @@ static u64 tsc_read_refs(u64 *pm, u64 *hpet)
127 */ 127 */
128unsigned long native_calibrate_tsc(void) 128unsigned long native_calibrate_tsc(void)
129{ 129{
130 unsigned long flags; 130 u64 tsc1, tsc2, tr1, tr2, tsc, delta, pm1, pm2, hpet1, hpet2;
131 u64 tsc1, tsc2, tr1, tr2, delta, pm1, pm2, hpet1, hpet2; 131 unsigned long tsc_pit_min = ULONG_MAX, tsc_ref_min = ULONG_MAX;
132 int hpet = is_hpet_enabled(); 132 unsigned long flags, tscmin, tscmax;
133 unsigned int tsc_khz_val = 0; 133 int hpet = is_hpet_enabled(), pitcnt, i;
134 134
135 local_irq_save(flags); 135 /*
136 136 * Run 5 calibration loops to get the lowest frequency value
137 tsc1 = tsc_read_refs(&pm1, hpet ? &hpet1 : NULL); 137 * (the best estimate). We use two different calibration modes
138 138 * here:
139 outb((inb(0x61) & ~0x02) | 0x01, 0x61); 139 *
140 140 * 1) PIT loop. We set the PIT Channel 2 to oneshot mode and
141 outb(0xb0, 0x43); 141 * load a timeout of 50ms. We read the time right after we
142 outb((CLOCK_TICK_RATE / (1000 / 50)) & 0xff, 0x42); 142 * started the timer and wait until the PIT count down reaches
143 outb((CLOCK_TICK_RATE / (1000 / 50)) >> 8, 0x42); 143 * zero. In each wait loop iteration we read the TSC and check
144 tr1 = get_cycles(); 144 * the delta to the previous read. We keep track of the min
145 while ((inb(0x61) & 0x20) == 0); 145 * and max values of that delta. The delta is mostly defined
146 tr2 = get_cycles(); 146 * by the IO time of the PIT access, so we can detect when a
147 147 * SMI/SMM disturbance happend between the two reads. If the
148 tsc2 = tsc_read_refs(&pm2, hpet ? &hpet2 : NULL); 148 * maximum time is significantly larger than the minimum time,
149 149 * then we discard the result and have another try.
150 local_irq_restore(flags); 150 *
151 * 2) Reference counter. If available we use the HPET or the
152 * PMTIMER as a reference to check the sanity of that value.
153 * We use separate TSC readouts and check inside of the
154 * reference read for a SMI/SMM disturbance. We dicard
155 * disturbed values here as well. We do that around the PIT
156 * calibration delay loop as we have to wait for a certain
157 * amount of time anyway.
158 */
159 for (i = 0; i < 5; i++) {
160
161 tscmin = ULONG_MAX;
162 tscmax = 0;
163 pitcnt = 0;
164
165 local_irq_save(flags);
166
167 /*
168 * Read the start value and the reference count of
169 * hpet/pmtimer when available:
170 */
171 tsc1 = tsc_read_refs(&pm1, hpet ? &hpet1 : NULL);
172
173 /* Set the Gate high, disable speaker */
174 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
175
176 /*
177 * Setup CTC channel 2* for mode 0, (interrupt on terminal
178 * count mode), binary count. Set the latch register to 50ms
179 * (LSB then MSB) to begin countdown.
180 *
181 * Some devices need a delay here.
182 */
183 outb(0xb0, 0x43);
184 outb((CLOCK_TICK_RATE / (1000 / 50)) & 0xff, 0x42);
185 outb((CLOCK_TICK_RATE / (1000 / 50)) >> 8, 0x42);
186
187 tsc = tr1 = tr2 = get_cycles();
188
189 while ((inb(0x61) & 0x20) == 0) {
190 tr2 = get_cycles();
191 delta = tr2 - tsc;
192 tsc = tr2;
193 if ((unsigned int) delta < tscmin)
194 tscmin = (unsigned int) delta;
195 if ((unsigned int) delta > tscmax)
196 tscmax = (unsigned int) delta;
197 pitcnt++;
198 }
199
200 /*
201 * We waited at least 50ms above. Now read
202 * pmtimer/hpet reference again
203 */
204 tsc2 = tsc_read_refs(&pm2, hpet ? &hpet2 : NULL);
205
206 local_irq_restore(flags);
207
208 /*
209 * Sanity checks:
210 *
211 * If we were not able to read the PIT more than 5000
212 * times, then we have been hit by a massive SMI
213 *
214 * If the maximum is 10 times larger than the minimum,
215 * then we got hit by an SMI as well.
216 */
217 if (pitcnt > 5000 && tscmax < 10 * tscmin) {
218
219 /* Calculate the PIT value */
220 delta = tr2 - tr1;
221 do_div(delta, 50);
222
223 /* We take the smallest value into account */
224 tsc_pit_min = min(tsc_pit_min, (unsigned long) delta);
225 }
226
227 /* hpet or pmtimer available ? */
228 if (!hpet && !pm1 && !pm2)
229 continue;
230
231 /* Check, whether the sampling was disturbed by an SMI */
232 if (tsc1 == ULLONG_MAX || tsc2 == ULLONG_MAX)
233 continue;
234
235 tsc2 = (tsc2 - tsc1) * 1000000LL;
236
237 if (hpet) {
238 if (hpet2 < hpet1)
239 hpet2 += 0x100000000ULL;
240 hpet2 -= hpet1;
241 tsc1 = ((u64)hpet2 * hpet_readl(HPET_PERIOD));
242 do_div(tsc1, 1000000);
243 } else {
244 if (pm2 < pm1)
245 pm2 += (u64)ACPI_PM_OVRRUN;
246 pm2 -= pm1;
247 tsc1 = pm2 * 1000000000LL;
248 do_div(tsc1, PMTMR_TICKS_PER_SEC);
249 }
250
251 do_div(tsc2, tsc1);
252 tsc_ref_min = min(tsc_ref_min, (unsigned long) tsc2);
253 }
151 254
152 /* 255 /*
153 * Preset the result with the raw and inaccurate PIT 256 * Now check the results.
154 * calibration value
155 */ 257 */
156 delta = (tr2 - tr1); 258 if (tsc_pit_min == ULONG_MAX) {
157 do_div(delta, 50); 259 /* PIT gave no useful value */
158 tsc_khz_val = delta; 260 printk(KERN_WARNING "TSC: PIT calibration failed due to "
261 "SMI disturbance.\n");
262
263 /* We don't have an alternative source, disable TSC */
264 if (!hpet && !pm1 && !pm2) {
265 printk("TSC: No reference (HPET/PMTIMER) available\n");
266 return 0;
267 }
268
269 /* The alternative source failed as well, disable TSC */
270 if (tsc_ref_min == ULONG_MAX) {
271 printk(KERN_WARNING "TSC: HPET/PMTIMER calibration "
272 "failed due to SMI disturbance.\n");
273 return 0;
274 }
275
276 /* Use the alternative source */
277 printk(KERN_INFO "TSC: using %s reference calibration\n",
278 hpet ? "HPET" : "PMTIMER");
279
280 return tsc_ref_min;
281 }
159 282
160 /* hpet or pmtimer available ? */ 283 /* We don't have an alternative source, use the PIT calibration value */
161 if (!hpet && !pm1 && !pm2) { 284 if (!hpet && !pm1 && !pm2) {
162 printk(KERN_INFO "TSC calibrated against PIT\n"); 285 printk(KERN_INFO "TSC: Using PIT calibration value\n");
163 goto out; 286 return tsc_pit_min;
164 } 287 }
165 288
166 /* Check, whether the sampling was disturbed by an SMI */ 289 /* The alternative source failed, use the PIT calibration value */
167 if (tsc1 == ULLONG_MAX || tsc2 == ULLONG_MAX) { 290 if (tsc_ref_min == ULONG_MAX) {
168 printk(KERN_WARNING "TSC calibration disturbed by SMI, " 291 printk(KERN_WARNING "TSC: HPET/PMTIMER calibration failed due "
169 "using PIT calibration result\n"); 292 "to SMI disturbance. Using PIT calibration\n");
170 goto out; 293 return tsc_pit_min;
171 } 294 }
172 295
173 tsc2 = (tsc2 - tsc1) * 1000000LL; 296 /* Check the reference deviation */
174 297 delta = ((u64) tsc_pit_min) * 100;
175 if (hpet) { 298 do_div(delta, tsc_ref_min);
176 printk(KERN_INFO "TSC calibrated against HPET\n"); 299
177 if (hpet2 < hpet1) 300 /*
178 hpet2 += 0x100000000ULL; 301 * If both calibration results are inside a 5% window, the we
179 hpet2 -= hpet1; 302 * use the lower frequency of those as it is probably the
180 tsc1 = ((u64)hpet2 * hpet_readl(HPET_PERIOD)); 303 * closest estimate.
181 do_div(tsc1, 1000000); 304 */
182 } else { 305 if (delta >= 95 && delta <= 105) {
183 printk(KERN_INFO "TSC calibrated against PM_TIMER\n"); 306 printk(KERN_INFO "TSC: PIT calibration confirmed by %s.\n",
184 if (pm2 < pm1) 307 hpet ? "HPET" : "PMTIMER");
185 pm2 += (u64)ACPI_PM_OVRRUN; 308 printk(KERN_INFO "TSC: using %s calibration value\n",
186 pm2 -= pm1; 309 tsc_pit_min <= tsc_ref_min ? "PIT" :
187 tsc1 = pm2 * 1000000000LL; 310 hpet ? "HPET" : "PMTIMER");
188 do_div(tsc1, PMTMR_TICKS_PER_SEC); 311 return tsc_pit_min <= tsc_ref_min ? tsc_pit_min : tsc_ref_min;
189 } 312 }
190 313
191 do_div(tsc2, tsc1); 314 printk(KERN_WARNING "TSC: PIT calibration deviates from %s: %lu %lu.\n",
192 tsc_khz_val = tsc2; 315 hpet ? "HPET" : "PMTIMER", tsc_pit_min, tsc_ref_min);
193 316
194out: 317 /*
195 return tsc_khz_val; 318 * The calibration values differ too much. In doubt, we use
319 * the PIT value as we know that there are PMTIMERs around
320 * running at double speed.
321 */
322 printk(KERN_INFO "TSC: Using PIT calibration value\n");
323 return tsc_pit_min;
196} 324}
197 325
198
199#ifdef CONFIG_X86_32 326#ifdef CONFIG_X86_32
200/* Only called from the Powernow K7 cpu freq driver */ 327/* Only called from the Powernow K7 cpu freq driver */
201int recalibrate_cpu_khz(void) 328int recalibrate_cpu_khz(void)
diff --git a/arch/x86/lib/msr-on-cpu.c b/arch/x86/lib/msr-on-cpu.c
index d5a2b39f882b..01b868ba82f8 100644
--- a/arch/x86/lib/msr-on-cpu.c
+++ b/arch/x86/lib/msr-on-cpu.c
@@ -30,10 +30,11 @@ static int _rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h, int safe)
30 30
31 rv.msr_no = msr_no; 31 rv.msr_no = msr_no;
32 if (safe) { 32 if (safe) {
33 smp_call_function_single(cpu, __rdmsr_safe_on_cpu, &rv, 1); 33 err = smp_call_function_single(cpu, __rdmsr_safe_on_cpu,
34 err = rv.err; 34 &rv, 1);
35 err = err ? err : rv.err;
35 } else { 36 } else {
36 smp_call_function_single(cpu, __rdmsr_on_cpu, &rv, 1); 37 err = smp_call_function_single(cpu, __rdmsr_on_cpu, &rv, 1);
37 } 38 }
38 *l = rv.l; 39 *l = rv.l;
39 *h = rv.h; 40 *h = rv.h;
@@ -64,23 +65,24 @@ static int _wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h, int safe)
64 rv.l = l; 65 rv.l = l;
65 rv.h = h; 66 rv.h = h;
66 if (safe) { 67 if (safe) {
67 smp_call_function_single(cpu, __wrmsr_safe_on_cpu, &rv, 1); 68 err = smp_call_function_single(cpu, __wrmsr_safe_on_cpu,
68 err = rv.err; 69 &rv, 1);
70 err = err ? err : rv.err;
69 } else { 71 } else {
70 smp_call_function_single(cpu, __wrmsr_on_cpu, &rv, 1); 72 err = smp_call_function_single(cpu, __wrmsr_on_cpu, &rv, 1);
71 } 73 }
72 74
73 return err; 75 return err;
74} 76}
75 77
76void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) 78int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
77{ 79{
78 _wrmsr_on_cpu(cpu, msr_no, l, h, 0); 80 return _wrmsr_on_cpu(cpu, msr_no, l, h, 0);
79} 81}
80 82
81void rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h) 83int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h)
82{ 84{
83 _rdmsr_on_cpu(cpu, msr_no, l, h, 0); 85 return _rdmsr_on_cpu(cpu, msr_no, l, h, 0);
84} 86}
85 87
86/* These "safe" variants are slower and should be used when the target MSR 88/* These "safe" variants are slower and should be used when the target MSR
diff --git a/arch/x86/pci/i386.c b/arch/x86/pci/i386.c
index d765da913842..8791fc55e715 100644
--- a/arch/x86/pci/i386.c
+++ b/arch/x86/pci/i386.c
@@ -31,11 +31,8 @@
31#include <linux/ioport.h> 31#include <linux/ioport.h>
32#include <linux/errno.h> 32#include <linux/errno.h>
33#include <linux/bootmem.h> 33#include <linux/bootmem.h>
34#include <linux/acpi.h>
35 34
36#include <asm/pat.h> 35#include <asm/pat.h>
37#include <asm/hpet.h>
38#include <asm/io_apic.h>
39 36
40#include "pci.h" 37#include "pci.h"
41 38
@@ -80,77 +77,6 @@ pcibios_align_resource(void *data, struct resource *res,
80} 77}
81EXPORT_SYMBOL(pcibios_align_resource); 78EXPORT_SYMBOL(pcibios_align_resource);
82 79
83static int check_res_with_valid(struct pci_dev *dev, struct resource *res)
84{
85 unsigned long base;
86 unsigned long size;
87 int i;
88
89 base = res->start;
90 size = (res->start == 0 && res->end == res->start) ? 0 :
91 (res->end - res->start + 1);
92
93 if (!base || !size)
94 return 0;
95
96#ifdef CONFIG_HPET_TIMER
97 /* for hpet */
98 if (base == hpet_address && (res->flags & IORESOURCE_MEM)) {
99 dev_info(&dev->dev, "BAR has HPET at %08lx-%08lx\n",
100 base, base + size - 1);
101 return 1;
102 }
103#endif
104
105#ifdef CONFIG_X86_IO_APIC
106 for (i = 0; i < nr_ioapics; i++) {
107 unsigned long ioapic_phys = mp_ioapics[i].mp_apicaddr;
108
109 if (base == ioapic_phys && (res->flags & IORESOURCE_MEM)) {
110 dev_info(&dev->dev, "BAR has ioapic at %08lx-%08lx\n",
111 base, base + size - 1);
112 return 1;
113 }
114 }
115#endif
116
117#ifdef CONFIG_PCI_MMCONFIG
118 for (i = 0; i < pci_mmcfg_config_num; i++) {
119 unsigned long addr;
120
121 addr = pci_mmcfg_config[i].address;
122 if (base == addr && (res->flags & IORESOURCE_MEM)) {
123 dev_info(&dev->dev, "BAR has MMCONFIG at %08lx-%08lx\n",
124 base, base + size - 1);
125 return 1;
126 }
127 }
128#endif
129
130 return 0;
131}
132
133static int check_platform(struct pci_dev *dev, struct resource *res)
134{
135 struct resource *root = NULL;
136
137 /*
138 * forcibly insert it into the
139 * resource tree
140 */
141 if (res->flags & IORESOURCE_MEM)
142 root = &iomem_resource;
143 else if (res->flags & IORESOURCE_IO)
144 root = &ioport_resource;
145
146 if (root && check_res_with_valid(dev, res)) {
147 insert_resource(root, res);
148
149 return 1;
150 }
151
152 return 0;
153}
154/* 80/*
155 * Handle resources of PCI devices. If the world were perfect, we could 81 * Handle resources of PCI devices. If the world were perfect, we could
156 * just allocate all the resource regions and do nothing more. It isn't. 82 * just allocate all the resource regions and do nothing more. It isn't.
@@ -202,10 +128,7 @@ static void __init pcibios_allocate_bus_resources(struct list_head *bus_list)
202 pr = pci_find_parent_resource(dev, r); 128 pr = pci_find_parent_resource(dev, r);
203 if (!r->start || !pr || 129 if (!r->start || !pr ||
204 request_resource(pr, r) < 0) { 130 request_resource(pr, r) < 0) {
205 if (check_platform(dev, r)) 131 dev_err(&dev->dev, "BAR %d: can't allocate resource\n", idx);
206 continue;
207 dev_err(&dev->dev, "BAR %d: can't "
208 "allocate resource\n", idx);
209 /* 132 /*
210 * Something is wrong with the region. 133 * Something is wrong with the region.
211 * Invalidate the resource to prevent 134 * Invalidate the resource to prevent
@@ -240,17 +163,13 @@ static void __init pcibios_allocate_resources(int pass)
240 else 163 else
241 disabled = !(command & PCI_COMMAND_MEMORY); 164 disabled = !(command & PCI_COMMAND_MEMORY);
242 if (pass == disabled) { 165 if (pass == disabled) {
243 dev_dbg(&dev->dev, "resource %#08llx-%#08llx " 166 dev_dbg(&dev->dev, "resource %#08llx-%#08llx (f=%lx, d=%d, p=%d)\n",
244 "(f=%lx, d=%d, p=%d)\n",
245 (unsigned long long) r->start, 167 (unsigned long long) r->start,
246 (unsigned long long) r->end, 168 (unsigned long long) r->end,
247 r->flags, disabled, pass); 169 r->flags, disabled, pass);
248 pr = pci_find_parent_resource(dev, r); 170 pr = pci_find_parent_resource(dev, r);
249 if (!pr || request_resource(pr, r) < 0) { 171 if (!pr || request_resource(pr, r) < 0) {
250 if (check_platform(dev, r)) 172 dev_err(&dev->dev, "BAR %d: can't allocate resource\n", idx);
251 continue;
252 dev_err(&dev->dev, "BAR %d: can't "
253 "allocate resource\n", idx);
254 /* We'll assign a new address later */ 173 /* We'll assign a new address later */
255 r->end -= r->start; 174 r->end -= r->start;
256 r->start = 0; 175 r->start = 0;