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authorMagnus Damm <damm@igel.co.jp>2009-06-04 03:35:25 -0400
committerPaul Mundt <lethal@linux-sh.org>2009-06-11 02:15:07 -0400
commit4ed37394842e5f9c0c4ea087e8716d4458d03bfb (patch)
tree3457f44f8ba87e6f7ecd37de0f7861e72b015fb6 /arch
parentbc49b6eaac6eff86f902a36d846c310e1e0beedf (diff)
sh: sh7366 clock framework rewrite
This patch rewrites the sh7366 clock framework code. The new code makes use of the recently merged div4, div6 and mstp32 helper code. Both extal and dll are supported as input clocks to the pll. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/sh/Kconfig2
-rw-r--r--arch/sh/kernel/cpu/sh4a/Makefile2
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7366.c211
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7722.c42
4 files changed, 214 insertions, 43 deletions
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index 39807146d259..dbc10ff495a9 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -516,7 +516,7 @@ config SH_CLK_CPG
516 516
517config SH_CLK_CPG_LEGACY 517config SH_CLK_CPG_LEGACY
518 depends on SH_CLK_CPG 518 depends on SH_CLK_CPG
519 def_bool y if !CPU_SUBTYPE_SH7785 && !CPU_SUBTYPE_SH7723 && !CPU_SUBTYPE_SH7724 && !CPU_SUBTYPE_SH7343 519 def_bool y if !CPU_SUBTYPE_SH7785 && !CPU_SUBTYPE_SH7723 && !CPU_SUBTYPE_SH7724 && !CPU_SUBTYPE_SH7343 && !CPU_SUBTYPE_SH7366
520 520
521config SH_CLK_MD 521config SH_CLK_MD
522 int "CPU Mode Pin Setting" 522 int "CPU Mode Pin Setting"
diff --git a/arch/sh/kernel/cpu/sh4a/Makefile b/arch/sh/kernel/cpu/sh4a/Makefile
index f4415f9ebac7..96ea09ca8cc1 100644
--- a/arch/sh/kernel/cpu/sh4a/Makefile
+++ b/arch/sh/kernel/cpu/sh4a/Makefile
@@ -28,7 +28,7 @@ clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7343.o
28clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o 28clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o
29clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7723.o 29clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7723.o
30clock-$(CONFIG_CPU_SUBTYPE_SH7724) := clock-sh7724.o 30clock-$(CONFIG_CPU_SUBTYPE_SH7724) := clock-sh7724.o
31clock-$(CONFIG_CPU_SUBTYPE_SH7366) := clock-sh7722.o 31clock-$(CONFIG_CPU_SUBTYPE_SH7366) := clock-sh7366.o
32clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o 32clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o
33 33
34# Pinmux setup 34# Pinmux setup
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7366.c b/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
new file mode 100644
index 000000000000..a95ebaba095c
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
@@ -0,0 +1,211 @@
1/*
2 * arch/sh/kernel/cpu/sh4a/clock-sh7366.c
3 *
4 * SH7366 clock framework support
5 *
6 * Copyright (C) 2009 Magnus Damm
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#include <linux/init.h>
22#include <linux/kernel.h>
23#include <linux/io.h>
24#include <asm/clock.h>
25
26/* SH7366 registers */
27#define FRQCR 0xa4150000
28#define VCLKCR 0xa4150004
29#define SCLKACR 0xa4150008
30#define SCLKBCR 0xa415000c
31#define PLLCR 0xa4150024
32#define MSTPCR0 0xa4150030
33#define MSTPCR1 0xa4150034
34#define MSTPCR2 0xa4150038
35#define DLLFRQ 0xa4150050
36
37/* Fixed 32 KHz root clock for RTC and Power Management purposes */
38static struct clk r_clk = {
39 .name = "rclk",
40 .id = -1,
41 .rate = 32768,
42};
43
44/*
45 * Default rate for the root input clock, reset this with clk_set_rate()
46 * from the platform code.
47 */
48struct clk extal_clk = {
49 .name = "extal",
50 .id = -1,
51 .rate = 33333333,
52};
53
54/* The dll block multiplies the 32khz r_clk, may be used instead of extal */
55static unsigned long dll_recalc(struct clk *clk)
56{
57 unsigned long mult;
58
59 if (__raw_readl(PLLCR) & 0x1000)
60 mult = __raw_readl(DLLFRQ);
61 else
62 mult = 0;
63
64 return clk->parent->rate * mult;
65}
66
67static struct clk_ops dll_clk_ops = {
68 .recalc = dll_recalc,
69};
70
71static struct clk dll_clk = {
72 .name = "dll_clk",
73 .id = -1,
74 .ops = &dll_clk_ops,
75 .parent = &r_clk,
76 .flags = CLK_ENABLE_ON_INIT,
77};
78
79static unsigned long pll_recalc(struct clk *clk)
80{
81 unsigned long mult = 1;
82 unsigned long div = 1;
83
84 if (__raw_readl(PLLCR) & 0x4000)
85 mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1);
86 else
87 div = 2;
88
89 return (clk->parent->rate * mult) / div;
90}
91
92static struct clk_ops pll_clk_ops = {
93 .recalc = pll_recalc,
94};
95
96static struct clk pll_clk = {
97 .name = "pll_clk",
98 .id = -1,
99 .ops = &pll_clk_ops,
100 .flags = CLK_ENABLE_ON_INIT,
101};
102
103struct clk *main_clks[] = {
104 &r_clk,
105 &extal_clk,
106 &dll_clk,
107 &pll_clk,
108};
109
110static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
111static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
112
113static struct clk_div_mult_table div4_table = {
114 .divisors = divisors,
115 .nr_divisors = ARRAY_SIZE(divisors),
116 .multipliers = multipliers,
117 .nr_multipliers = ARRAY_SIZE(multipliers),
118};
119
120enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,
121 DIV4_SIUA, DIV4_SIUB, DIV4_NR };
122
123#define DIV4(_str, _reg, _bit, _mask, _flags) \
124 SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
125
126struct clk div4_clks[DIV4_NR] = {
127 [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
128 [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
129 [DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
130 [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
131 [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
132 [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0),
133 [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0),
134 [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0),
135};
136
137struct clk div6_clks[] = {
138 SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0),
139};
140
141#define MSTP(_str, _parent, _reg, _bit, _flags) \
142 SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _flags)
143
144static struct clk mstp_clks[] = {
145 /* See page 52 of Datasheet V0.40: Overview -> Block Diagram */
146 MSTP("tlb0", &div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
147 MSTP("ic0", &div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
148 MSTP("oc0", &div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
149 MSTP("rsmem0", &div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
150 MSTP("xymem0", &div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
151 MSTP("intc3", &div4_clks[DIV4_P], MSTPCR0, 23, 0),
152 MSTP("intc0", &div4_clks[DIV4_P], MSTPCR0, 22, 0),
153 MSTP("dmac0", &div4_clks[DIV4_P], MSTPCR0, 21, 0),
154 MSTP("sh0", &div4_clks[DIV4_P], MSTPCR0, 20, 0),
155 MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0),
156 MSTP("ubc0", &div4_clks[DIV4_P], MSTPCR0, 17, 0),
157 MSTP("tmu0", &div4_clks[DIV4_P], MSTPCR0, 15, 0),
158 MSTP("cmt0", &r_clk, MSTPCR0, 14, 0),
159 MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0),
160 MSTP("mfi0", &div4_clks[DIV4_P], MSTPCR0, 11, 0),
161 MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0),
162 MSTP("scif0", &div4_clks[DIV4_P], MSTPCR0, 7, 0),
163 MSTP("scif1", &div4_clks[DIV4_P], MSTPCR0, 6, 0),
164 MSTP("scif2", &div4_clks[DIV4_P], MSTPCR0, 5, 0),
165 MSTP("msiof0", &div4_clks[DIV4_P], MSTPCR0, 2, 0),
166 MSTP("sbr0", &div4_clks[DIV4_P], MSTPCR0, 1, 0),
167
168 MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0),
169
170 MSTP("icb0", &div4_clks[DIV4_P], MSTPCR2, 27, 0),
171 MSTP("meram0", &div4_clks[DIV4_P], MSTPCR2, 26, 0),
172 MSTP("dacy1", &div4_clks[DIV4_P], MSTPCR2, 24, 0),
173 MSTP("dacy0", &div4_clks[DIV4_P], MSTPCR2, 23, 0),
174 MSTP("tsif0", &div4_clks[DIV4_P], MSTPCR2, 22, 0),
175 MSTP("sdhi0", &div4_clks[DIV4_P], MSTPCR2, 18, 0),
176 MSTP("mmcif0", &div4_clks[DIV4_P], MSTPCR2, 17, 0),
177 MSTP("usbf0", &div4_clks[DIV4_P], MSTPCR2, 11, 0),
178 MSTP("siu0", &div4_clks[DIV4_B], MSTPCR2, 9, 0),
179 MSTP("veu1", &div4_clks[DIV4_B], MSTPCR2, 7, CLK_ENABLE_ON_INIT),
180 MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0),
181 MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0),
182 MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0),
183 MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT),
184 MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT),
185 MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0),
186};
187
188int __init arch_clk_init(void)
189{
190 int k, ret = 0;
191
192 /* autodetect extal or dll configuration */
193 if (__raw_readl(PLLCR) & 0x1000)
194 pll_clk.parent = &dll_clk;
195 else
196 pll_clk.parent = &extal_clk;
197
198 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
199 ret = clk_register(main_clks[k]);
200
201 if (!ret)
202 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
203
204 if (!ret)
205 ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks));
206
207 if (!ret)
208 ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks));
209
210 return ret;
211}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
index 8aaaac240ada..6ca7c745580d 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * arch/sh/kernel/cpu/sh4a/clock-sh7722.c 2 * arch/sh/kernel/cpu/sh4a/clock-sh7722.c
3 * 3 *
4 * SH7722 & SH7366 support for the clock framework 4 * SH7722 support for the clock framework
5 * 5 *
6 * Copyright (c) 2006-2007 Nomad Global Solutions Inc 6 * Copyright (c) 2006-2007 Nomad Global Solutions Inc
7 * Based on code for sh7343 by Paul Mundt 7 * Based on code for sh7343 by Paul Mundt
@@ -654,46 +654,6 @@ static struct clk sh7722_mstpcr_clocks[] = {
654 MSTPCR("vpu0", "bus_clk", 2, 1, CLK_ENABLE_ON_INIT), 654 MSTPCR("vpu0", "bus_clk", 2, 1, CLK_ENABLE_ON_INIT),
655 MSTPCR("lcdc0", "bus_clk", 2, 0, 0), 655 MSTPCR("lcdc0", "bus_clk", 2, 0, 0),
656#endif 656#endif
657#if defined(CONFIG_CPU_SUBTYPE_SH7366)
658 /* See page 52 of Datasheet V0.40: Overview -> Block Diagram */
659 MSTPCR("tlb0", "cpu_clk", 0, 31, 0),
660 MSTPCR("ic0", "cpu_clk", 0, 30, 0),
661 MSTPCR("oc0", "cpu_clk", 0, 29, 0),
662 MSTPCR("rsmem0", "sh_clk", 0, 28, CLK_ENABLE_ON_INIT),
663 MSTPCR("xymem0", "cpu_clk", 0, 26, CLK_ENABLE_ON_INIT),
664 MSTPCR("intc30", "peripheral_clk", 0, 23, 0),
665 MSTPCR("intc0", "peripheral_clk", 0, 22, 0),
666 MSTPCR("dmac0", "bus_clk", 0, 21, 0),
667 MSTPCR("sh0", "sh_clk", 0, 20, 0),
668 MSTPCR("hudi0", "peripheral_clk", 0, 19, 0),
669 MSTPCR("ubc0", "cpu_clk", 0, 17, 0),
670 MSTPCR("tmu0", "peripheral_clk", 0, 15, 0),
671 MSTPCR("cmt0", "r_clk", 0, 14, 0),
672 MSTPCR("rwdt0", "r_clk", 0, 13, 0),
673 MSTPCR("flctl0", "peripheral_clk", 0, 10, 0),
674 MSTPCR("scif0", "peripheral_clk", 0, 7, 0),
675 MSTPCR("scif1", "bus_clk", 0, 6, 0),
676 MSTPCR("scif2", "bus_clk", 0, 5, 0),
677 MSTPCR("msiof0", "peripheral_clk", 0, 2, 0),
678 MSTPCR("sbr0", "peripheral_clk", 0, 1, 0),
679 MSTPCR("i2c0", "peripheral_clk", 1, 9, 0),
680 MSTPCR("icb0", "bus_clk", 2, 27, 0),
681 MSTPCR("meram0", "sh_clk", 2, 26, 0),
682 MSTPCR("dacc0", "peripheral_clk", 2, 24, 0),
683 MSTPCR("dacy0", "peripheral_clk", 2, 23, 0),
684 MSTPCR("tsif0", "bus_clk", 2, 22, 0),
685 MSTPCR("sdhi0", "bus_clk", 2, 18, 0),
686 MSTPCR("mmcif0", "bus_clk", 2, 17, 0),
687 MSTPCR("usb0", "bus_clk", 2, 11, 0),
688 MSTPCR("siu0", "bus_clk", 2, 8, 0),
689 MSTPCR("veu1", "bus_clk", 2, 7, CLK_ENABLE_ON_INIT),
690 MSTPCR("vou0", "bus_clk", 2, 5, 0),
691 MSTPCR("beu0", "bus_clk", 2, 4, 0),
692 MSTPCR("ceu0", "bus_clk", 2, 3, 0),
693 MSTPCR("veu0", "bus_clk", 2, 2, CLK_ENABLE_ON_INIT),
694 MSTPCR("vpu0", "bus_clk", 2, 1, CLK_ENABLE_ON_INIT),
695 MSTPCR("lcdc0", "bus_clk", 2, 0, 0),
696#endif
697}; 657};
698 658
699static struct clk *sh7722_clocks[] = { 659static struct clk *sh7722_clocks[] = {