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authorJoakim Tjernlund <joakim.tjernlund@transmode.se>2009-11-19 19:21:07 -0500
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2009-12-09 01:10:36 -0500
commit4a280a413c0c0da03936483384c9e5142966635e (patch)
tree1f7856a0ac635f845194692c26c79caa5e8bf3ef /arch
parent0a2ab51ffb8dfdf51402dcfb446629648c96bc78 (diff)
powerpc/8xx: Add missing Guarded setting in DTLB Error.
only DTLB Miss did set this bit, DTLB Error needs too otherwise the setting is lost when the page becomes dirty. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/kernel/head_8xx.S13
1 files changed, 10 insertions, 3 deletions
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index c00120d56f8f..1a28ee8ca318 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -552,9 +552,16 @@ DARFixed:/* Return from dcbx instruction bug workaround, r10 holds value of DAR
552 */ 552 */
553 ori r11, r11, 1 /* Set valid bit in physical L2 page */ 553 ori r11, r11, 1 /* Set valid bit in physical L2 page */
554 DO_8xx_CPU6(0x3b80, r3) 554 DO_8xx_CPU6(0x3b80, r3)
555 mtspr SPRN_MD_TWC, r11 /* Load pte table base address */ 555 mtspr SPRN_MD_TWC, r11 /* Load pte table base address */
556 mfspr r11, SPRN_MD_TWC /* ....and get the pte address */ 556 mfspr r10, SPRN_MD_TWC /* ....and get the pte address */
557 lwz r10, 0(r11) /* Get the pte */ 557 lwz r10, 0(r10) /* Get the pte */
558 /* Insert the Guarded flag into the TWC from the Linux PTE.
559 * It is bit 27 of both the Linux PTE and the TWC
560 */
561 rlwimi r11, r10, 0, 27, 27
562 DO_8xx_CPU6(0x3b80, r3)
563 mtspr SPRN_MD_TWC, r11
564 mfspr r11, SPRN_MD_TWC /* get the pte address again */
558 565
559 ori r10, r10, _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_HWWRITE 566 ori r10, r10, _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_HWWRITE
560 stw r10, 0(r11) /* and update pte in table */ 567 stw r10, 0(r11) /* and update pte in table */