[IA64-SGI] disable TIOCA GART TLB prefetching

Patch to disable SGI TIOCA GART TLB prefetching due to hw bug.

Signed-off-by: Mark Maule <maule@sgi.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>

1 files changed, 3 insertions, 3 deletions

diff --git a/arch/ia64/sn/pci/tioca_provider.c b/arch/ia64/sn/pci/tioca_provider.c
index 2234d61cdd4b..54a0dd447e76 100644
--- a/arch/ia64/sn/pci/tioca_provider.c
+++ b/arch/ia64/sn/pci/tioca_provider.c
@@ -171,15 +171,15 @@ tioca_gart_init(struct tioca_kernel *tioca_kern)
          *      use agp op-combining
          *      use GET semantics to fetch memory
          *      participate in coherency domain
-         *      prefetch TLB entries
+         *      DISABLE GART PREFETCHING due to hw bug tracked in SGI PV930029
          */
 
         ca_base->ca_control1 |= CA_AGPDMA_OP_ENB_COMBDELAY;     /* PV895469 ? */
         ca_base->ca_control2 &= ~(CA_GART_MEM_PARAM);
         ca_base->ca_control2 |= (0x2ull << CA_GART_MEM_PARAM_SHFT);
         tioca_kern->ca_gart_iscoherent = 1;
-        ca_base->ca_control2 |=
-            (CA_GART_WR_PREFETCH_ENB | CA_GART_RD_PREFETCH_ENB);
+        ca_base->ca_control2 &=
+            ~(CA_GART_WR_PREFETCH_ENB | CA_GART_RD_PREFETCH_ENB);
 
         /*
          * Unmask GART fetch error interrupts.  Clear residual errors first.