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authorRoman Tereshonkov <roman.tereshonkov@nokia.com>2008-03-13 15:35:09 -0400
committerTony Lindgren <tony@atomide.com>2008-04-14 13:29:39 -0400
commit3760d31f11bfbd0ead9eaeb8573e0602437a9d7c (patch)
treefdb1d97cec8ed3f8d40bbcdabdca55fcbd26ce21 /arch
parent02e19a960a519224a74da4d190965201044c1583 (diff)
ARM: OMAP2: New DPLL clock framework
These changes is the result of the discussion with Paul Walmsley. His ideas are included into this patch. Remove DPLL output divider handling from DPLLs and CLKOUTX2 clocks, and place it into specific DPLL output divider clocks (e.g., dpll3_m2_clk). omap2_get_dpll_rate() now returns the correct DPLL rate, as represented by the DPLL's CLKOUT output. Also add MPU and IVA2 subsystem clocks, along with high-frequency bypass support. Add support for DPLLs function in locked and bypass clock modes. Signed-off-by: Roman Tereshonkov <roman.tereshonkov@nokia.com> Acked-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-omap2/clock.c8
-rw-r--r--arch/arm/mach-omap2/clock34xx.c4
-rw-r--r--arch/arm/mach-omap2/clock34xx.h503
-rw-r--r--arch/arm/mach-omap2/cm-regbits-34xx.h4
4 files changed, 410 insertions, 109 deletions
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index a5b9564ea78e..b57ffb5a22a5 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -111,14 +111,6 @@ u32 omap2_get_dpll_rate(struct clk *clk)
111 dpll_clk = (long long)clk->parent->rate * dpll_mult; 111 dpll_clk = (long long)clk->parent->rate * dpll_mult;
112 do_div(dpll_clk, dpll_div + 1); 112 do_div(dpll_clk, dpll_div + 1);
113 113
114 /* 34XX only */
115 if (dd->div2_reg) {
116 dpll = __raw_readl(dd->div2_reg);
117 dpll_div = dpll & dd->div2_mask;
118 dpll_div >>= __ffs(dd->div2_mask);
119 do_div(dpll_clk, dpll_div + 1);
120 }
121
122 return dpll_clk; 114 return dpll_clk;
123} 115}
124 116
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index f6c82a333815..b42bdd6079a5 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -212,10 +212,10 @@ int __init omap2_clk_init(void)
212 212
213 recalculate_root_clocks(); 213 recalculate_root_clocks();
214 214
215 printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): " 215 printk(KERN_INFO "Clocking rate (Crystal/DPLL/ARM core): "
216 "%ld.%01ld/%ld/%ld MHz\n", 216 "%ld.%01ld/%ld/%ld MHz\n",
217 (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10, 217 (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
218 (core_ck.rate / 1000000), (dpll1_fck.rate / 1000000)) ; 218 (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
219 219
220 /* 220 /*
221 * Only enable those clocks we will need, let the drivers 221 * Only enable those clocks we will need, let the drivers
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index e4d73455f4c1..cf4644a94b9b 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -1,6 +1,10 @@
1/* 1/*
2 * OMAP3 clock framework 2 * OMAP3 clock framework
3 * 3 *
4 * Virtual clocks are introduced as a convenient tools.
5 * They are sources for other clocks and not supposed
6 * to be requested from drivers directly.
7 *
4 * Copyright (C) 2007-2008 Texas Instruments, Inc. 8 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2008 Nokia Corporation 9 * Copyright (C) 2007-2008 Nokia Corporation
6 * 10 *
@@ -203,6 +207,36 @@ static struct clk sys_clkout1 = {
203 207
204/* CM CLOCKS */ 208/* CM CLOCKS */
205 209
210static const struct clksel_rate dpll_bypass_rates[] = {
211 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
212 { .div = 0 }
213};
214
215static const struct clksel_rate dpll_locked_rates[] = {
216 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
217 { .div = 0 }
218};
219
220static const struct clksel_rate div16_dpll_rates[] = {
221 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
222 { .div = 2, .val = 2, .flags = RATE_IN_343X },
223 { .div = 3, .val = 3, .flags = RATE_IN_343X },
224 { .div = 4, .val = 4, .flags = RATE_IN_343X },
225 { .div = 5, .val = 5, .flags = RATE_IN_343X },
226 { .div = 6, .val = 6, .flags = RATE_IN_343X },
227 { .div = 7, .val = 7, .flags = RATE_IN_343X },
228 { .div = 8, .val = 8, .flags = RATE_IN_343X },
229 { .div = 9, .val = 9, .flags = RATE_IN_343X },
230 { .div = 10, .val = 10, .flags = RATE_IN_343X },
231 { .div = 11, .val = 11, .flags = RATE_IN_343X },
232 { .div = 12, .val = 12, .flags = RATE_IN_343X },
233 { .div = 13, .val = 13, .flags = RATE_IN_343X },
234 { .div = 14, .val = 14, .flags = RATE_IN_343X },
235 { .div = 15, .val = 15, .flags = RATE_IN_343X },
236 { .div = 16, .val = 16, .flags = RATE_IN_343X },
237 { .div = 0 }
238};
239
206/* DPLL1 */ 240/* DPLL1 */
207/* MPU clock source */ 241/* MPU clock source */
208/* Type: DPLL */ 242/* Type: DPLL */
@@ -210,8 +244,6 @@ static const struct dpll_data dpll1_dd = {
210 .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), 244 .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
211 .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK, 245 .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK,
212 .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK, 246 .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK,
213 .div2_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
214 .div2_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
215 .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL), 247 .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
216 .enable_mask = OMAP3430_EN_MPU_DPLL_MASK, 248 .enable_mask = OMAP3430_EN_MPU_DPLL_MASK,
217 .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT, 249 .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
@@ -228,15 +260,37 @@ static struct clk dpll1_ck = {
228}; 260};
229 261
230/* 262/*
231 * REVISIT: This clock is never specifically defined in the 3430 TRM, 263 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
232 * although it is referenced - so this is a guess 264 * DPLL isn't bypassed.
233 */ 265 */
234static struct clk emu_mpu_alwon_ck = { 266static struct clk dpll1_x2_ck = {
235 .name = "emu_mpu_alwon_ck", 267 .name = "dpll1_x2_ck",
236 .parent = &dpll1_ck, 268 .parent = &dpll1_ck,
237 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 269 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
238 PARENT_CONTROLS_CLOCK, 270 PARENT_CONTROLS_CLOCK,
239 .recalc = &followparent_recalc, 271 .recalc = &omap3_clkoutx2_recalc,
272};
273
274/* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
275static const struct clksel div16_dpll1_x2m2_clksel[] = {
276 { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
277 { .parent = NULL }
278};
279
280/*
281 * Does not exist in the TRM - needed to separate the M2 divider from
282 * bypass selection in mpu_ck
283 */
284static struct clk dpll1_x2m2_ck = {
285 .name = "dpll1_x2m2_ck",
286 .parent = &dpll1_x2_ck,
287 .init = &omap2_init_clksel_parent,
288 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
289 .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
290 .clksel = div16_dpll1_x2m2_clksel,
291 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
292 PARENT_CONTROLS_CLOCK,
293 .recalc = &omap2_clksel_recalc,
240}; 294};
241 295
242/* DPLL2 */ 296/* DPLL2 */
@@ -247,8 +301,6 @@ static const struct dpll_data dpll2_dd = {
247 .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), 301 .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
248 .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK, 302 .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK,
249 .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK, 303 .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK,
250 .div2_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL2_PLL),
251 .div2_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
252 .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL), 304 .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
253 .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK, 305 .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK,
254 .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT, 306 .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
@@ -264,6 +316,28 @@ static struct clk dpll2_ck = {
264 .recalc = &omap3_dpll_recalc, 316 .recalc = &omap3_dpll_recalc,
265}; 317};
266 318
319static const struct clksel div16_dpll2_m2x2_clksel[] = {
320 { .parent = &dpll2_ck, .rates = div16_dpll_rates },
321 { .parent = NULL }
322};
323
324/*
325 * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
326 * or CLKOUTX2. CLKOUT seems most plausible.
327 */
328static struct clk dpll2_m2_ck = {
329 .name = "dpll2_m2_ck",
330 .parent = &dpll2_ck,
331 .init = &omap2_init_clksel_parent,
332 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
333 OMAP3430_CM_CLKSEL2_PLL),
334 .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
335 .clksel = div16_dpll2_m2x2_clksel,
336 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
337 PARENT_CONTROLS_CLOCK,
338 .recalc = &omap2_clksel_recalc,
339};
340
267/* DPLL3 */ 341/* DPLL3 */
268/* Source clock for all interfaces and for some device fclks */ 342/* Source clock for all interfaces and for some device fclks */
269/* Type: DPLL */ 343/* Type: DPLL */
@@ -271,8 +345,6 @@ static const struct dpll_data dpll3_dd = {
271 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 345 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
272 .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK, 346 .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK,
273 .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK, 347 .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK,
274 .div2_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
275 .div2_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
276 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 348 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
277 .enable_mask = OMAP3430_EN_CORE_DPLL_MASK, 349 .enable_mask = OMAP3430_EN_CORE_DPLL_MASK,
278 .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT, 350 .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
@@ -288,24 +360,16 @@ static struct clk dpll3_ck = {
288 .recalc = &omap3_dpll_recalc, 360 .recalc = &omap3_dpll_recalc,
289}; 361};
290 362
291static const struct clksel_rate div16_dpll_rates[] = { 363/*
292 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 364 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
293 { .div = 2, .val = 2, .flags = RATE_IN_343X }, 365 * DPLL isn't bypassed
294 { .div = 3, .val = 3, .flags = RATE_IN_343X }, 366 */
295 { .div = 4, .val = 4, .flags = RATE_IN_343X }, 367static struct clk dpll3_x2_ck = {
296 { .div = 5, .val = 5, .flags = RATE_IN_343X }, 368 .name = "dpll3_x2_ck",
297 { .div = 6, .val = 6, .flags = RATE_IN_343X }, 369 .parent = &dpll3_ck,
298 { .div = 7, .val = 7, .flags = RATE_IN_343X }, 370 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
299 { .div = 8, .val = 8, .flags = RATE_IN_343X }, 371 PARENT_CONTROLS_CLOCK,
300 { .div = 9, .val = 9, .flags = RATE_IN_343X }, 372 .recalc = &omap3_clkoutx2_recalc,
301 { .div = 10, .val = 10, .flags = RATE_IN_343X },
302 { .div = 11, .val = 11, .flags = RATE_IN_343X },
303 { .div = 12, .val = 12, .flags = RATE_IN_343X },
304 { .div = 13, .val = 13, .flags = RATE_IN_343X },
305 { .div = 14, .val = 14, .flags = RATE_IN_343X },
306 { .div = 15, .val = 15, .flags = RATE_IN_343X },
307 { .div = 16, .val = 16, .flags = RATE_IN_343X },
308 { .div = 0 }
309}; 373};
310 374
311static const struct clksel_rate div31_dpll3_rates[] = { 375static const struct clksel_rate div31_dpll3_rates[] = {
@@ -349,9 +413,9 @@ static const struct clksel div31_dpll3m2_clksel[] = {
349}; 413};
350 414
351/* 415/*
352 * REVISIT: Not sure what to do about clksel & these M2 divider clocks. 416 * DPLL3 output M2
353 * Shouldn't they be changed in SRAM? 417 * REVISIT: This DPLL output divider must be changed in SRAM, so until
354 * This should probably remain a 'read-only' clksel clock. 418 * that code is ready, this should remain a 'read-only' clksel clock.
355 */ 419 */
356static struct clk dpll3_m2_ck = { 420static struct clk dpll3_m2_ck = {
357 .name = "dpll3_m2_ck", 421 .name = "dpll3_m2_ck",
@@ -365,58 +429,85 @@ static struct clk dpll3_m2_ck = {
365 .recalc = &omap2_clksel_recalc, 429 .recalc = &omap2_clksel_recalc,
366}; 430};
367 431
432static const struct clksel core_ck_clksel[] = {
433 { .parent = &sys_ck, .rates = dpll_bypass_rates },
434 { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates },
435 { .parent = NULL }
436};
437
368static struct clk core_ck = { 438static struct clk core_ck = {
369 .name = "core_ck", 439 .name = "core_ck",
370 .parent = &dpll3_m2_ck, 440 .init = &omap2_init_clksel_parent,
441 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
442 .clksel_mask = OMAP3430_ST_CORE_CLK,
443 .clksel = core_ck_clksel,
371 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 444 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
372 PARENT_CONTROLS_CLOCK, 445 PARENT_CONTROLS_CLOCK,
373 .recalc = &followparent_recalc, 446 .recalc = &omap2_clksel_recalc,
374}; 447};
375 448
376/* 449static const struct clksel dpll3_m2x2_ck_clksel[] = {
377 * This virtual clock provides the CLKOUTX2 output from the DPLL if the 450 { .parent = &sys_ck, .rates = dpll_bypass_rates },
378 * DPLL isn't bypassed 451 { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates },
379 */ 452 { .parent = NULL }
380static struct clk dpll3_x2_ck = {
381 .name = "dpll3_x2_ck",
382 .parent = &core_ck,
383 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
384 PARENT_CONTROLS_CLOCK,
385 .recalc = &omap3_clkoutx2_recalc,
386}; 453};
387 454
388static struct clk dpll3_m2x2_ck = { 455static struct clk dpll3_m2x2_ck = {
389 .name = "dpll3_m2x2_ck", 456 .name = "dpll3_m2x2_ck",
390 .parent = &dpll3_x2_ck, 457 .init = &omap2_init_clksel_parent,
458 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
459 .clksel_mask = OMAP3430_ST_CORE_CLK,
460 .clksel = dpll3_m2x2_ck_clksel,
391 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 461 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
392 PARENT_CONTROLS_CLOCK, 462 PARENT_CONTROLS_CLOCK,
393 .recalc = &followparent_recalc, 463 .recalc = &omap2_clksel_recalc,
464};
465
466/* The PWRDN bit is apparently only available on 3430ES2 and above */
467static const struct clksel div16_dpll3_clksel[] = {
468 { .parent = &dpll3_ck, .rates = div16_dpll_rates },
469 { .parent = NULL }
470};
471
472/* This virtual clock is the source for dpll3_m3x2_ck */
473static struct clk dpll3_m3_ck = {
474 .name = "dpll3_m3_ck",
475 .parent = &dpll3_ck,
476 .init = &omap2_init_clksel_parent,
477 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
478 .clksel_mask = OMAP3430_DIV_DPLL3_MASK,
479 .clksel = div16_dpll3_clksel,
480 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
481 PARENT_CONTROLS_CLOCK,
482 .recalc = &omap2_clksel_recalc,
394}; 483};
395 484
396/* The PWRDN bit is apparently only available on 3430ES2 and above */ 485/* The PWRDN bit is apparently only available on 3430ES2 and above */
397static struct clk dpll3_m3x2_ck = { 486static struct clk dpll3_m3x2_ck = {
398 .name = "dpll3_m3x2_ck", 487 .name = "dpll3_m3x2_ck",
399 .parent = &dpll3_x2_ck, 488 .parent = &dpll3_m3_ck,
400 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 489 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
401 .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT, 490 .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT,
402 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, 491 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
403 .recalc = &followparent_recalc, 492 .recalc = &omap3_clkoutx2_recalc,
404}; 493};
405 494
406static const struct clksel div16_dpll3_clksel[] = { 495static const struct clksel emu_core_alwon_ck_clksel[] = {
407 { .parent = &dpll3_x2_ck, .rates = div16_dpll_rates }, 496 { .parent = &sys_ck, .rates = dpll_bypass_rates },
497 { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates },
408 { .parent = NULL } 498 { .parent = NULL }
409}; 499};
410 500
411static struct clk emu_core_alwon_ck = { 501static struct clk emu_core_alwon_ck = {
412 .name = "emu_core_alwon_ck", 502 .name = "emu_core_alwon_ck",
413 .parent = &dpll3_x2_ck, 503 .parent = &dpll3_m3x2_ck,
414 .init = &omap2_init_clksel_parent, 504 .init = &omap2_init_clksel_parent,
415 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), 505 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
416 .clksel_mask = OMAP3430_DIV_DPLL3_MASK, 506 .clksel_mask = OMAP3430_ST_CORE_CLK,
417 .clksel = div16_dpll3_clksel, 507 .clksel = emu_core_alwon_ck_clksel,
418 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 508 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
419 .recalc = &followparent_recalc, 509 PARENT_CONTROLS_CLOCK,
510 .recalc = &omap2_clksel_recalc,
420}; 511};
421 512
422/* DPLL4 */ 513/* DPLL4 */
@@ -443,7 +534,8 @@ static struct clk dpll4_ck = {
443 534
444/* 535/*
445 * This virtual clock provides the CLKOUTX2 output from the DPLL if the 536 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
446 * DPLL isn't bypassed 537 * DPLL isn't bypassed --
538 * XXX does this serve any downstream clocks?
447 */ 539 */
448static struct clk dpll4_x2_ck = { 540static struct clk dpll4_x2_ck = {
449 .name = "dpll4_x2_ck", 541 .name = "dpll4_x2_ck",
@@ -454,30 +546,49 @@ static struct clk dpll4_x2_ck = {
454}; 546};
455 547
456static const struct clksel div16_dpll4_clksel[] = { 548static const struct clksel div16_dpll4_clksel[] = {
457 { .parent = &dpll4_x2_ck, .rates = div16_dpll_rates }, 549 { .parent = &dpll4_ck, .rates = div16_dpll_rates },
458 { .parent = NULL } 550 { .parent = NULL }
459}; 551};
460 552
553/* This virtual clock is the source for dpll4_m2x2_ck */
554static struct clk dpll4_m2_ck = {
555 .name = "dpll4_m2_ck",
556 .parent = &dpll4_ck,
557 .init = &omap2_init_clksel_parent,
558 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
559 .clksel_mask = OMAP3430_DIV_96M_MASK,
560 .clksel = div16_dpll4_clksel,
561 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
562 PARENT_CONTROLS_CLOCK,
563 .recalc = &omap2_clksel_recalc,
564};
565
461/* The PWRDN bit is apparently only available on 3430ES2 and above */ 566/* The PWRDN bit is apparently only available on 3430ES2 and above */
462static struct clk dpll4_m2x2_ck = { 567static struct clk dpll4_m2x2_ck = {
463 .name = "dpll4_m2x2_ck", 568 .name = "dpll4_m2x2_ck",
464 .parent = &dpll4_x2_ck, 569 .parent = &dpll4_m2_ck,
465 .init = &omap2_init_clksel_parent,
466 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 570 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
467 .enable_bit = OMAP3430_PWRDN_96M_SHIFT, 571 .enable_bit = OMAP3430_PWRDN_96M_SHIFT,
468 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
469 .clksel_mask = OMAP3430_DIV_96M_MASK,
470 .clksel = div16_dpll4_clksel,
471 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, 572 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
472 .recalc = &omap2_clksel_recalc, 573 .recalc = &omap3_clkoutx2_recalc,
574};
575
576static const struct clksel omap_96m_alwon_fck_clksel[] = {
577 { .parent = &sys_ck, .rates = dpll_bypass_rates },
578 { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
579 { .parent = NULL }
473}; 580};
474 581
475static struct clk omap_96m_alwon_fck = { 582static struct clk omap_96m_alwon_fck = {
476 .name = "omap_96m_alwon_fck", 583 .name = "omap_96m_alwon_fck",
477 .parent = &dpll4_m2x2_ck, 584 .parent = &dpll4_m2x2_ck,
585 .init = &omap2_init_clksel_parent,
586 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
587 .clksel_mask = OMAP3430_ST_PERIPH_CLK,
588 .clksel = omap_96m_alwon_fck_clksel,
478 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 589 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
479 PARENT_CONTROLS_CLOCK, 590 PARENT_CONTROLS_CLOCK,
480 .recalc = &followparent_recalc, 591 .recalc = &omap2_clksel_recalc,
481}; 592};
482 593
483static struct clk omap_96m_fck = { 594static struct clk omap_96m_fck = {
@@ -488,25 +599,63 @@ static struct clk omap_96m_fck = {
488 .recalc = &followparent_recalc, 599 .recalc = &followparent_recalc,
489}; 600};
490 601
602static const struct clksel cm_96m_fck_clksel[] = {
603 { .parent = &sys_ck, .rates = dpll_bypass_rates },
604 { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
605 { .parent = NULL }
606};
607
491static struct clk cm_96m_fck = { 608static struct clk cm_96m_fck = {
492 .name = "cm_96m_fck", 609 .name = "cm_96m_fck",
493 .parent = &dpll4_m2x2_ck, 610 .parent = &dpll4_m2x2_ck,
611 .init = &omap2_init_clksel_parent,
612 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
613 .clksel_mask = OMAP3430_ST_PERIPH_CLK,
614 .clksel = cm_96m_fck_clksel,
494 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 615 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
495 PARENT_CONTROLS_CLOCK, 616 PARENT_CONTROLS_CLOCK,
496 .recalc = &followparent_recalc, 617 .recalc = &omap2_clksel_recalc,
618};
619
620/* This virtual clock is the source for dpll4_m3x2_ck */
621static struct clk dpll4_m3_ck = {
622 .name = "dpll4_m3_ck",
623 .parent = &dpll4_ck,
624 .init = &omap2_init_clksel_parent,
625 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
626 .clksel_mask = OMAP3430_CLKSEL_TV_MASK,
627 .clksel = div16_dpll4_clksel,
628 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
629 PARENT_CONTROLS_CLOCK,
630 .recalc = &omap2_clksel_recalc,
497}; 631};
498 632
499/* The PWRDN bit is apparently only available on 3430ES2 and above */ 633/* The PWRDN bit is apparently only available on 3430ES2 and above */
500static struct clk dpll4_m3x2_ck = { 634static struct clk dpll4_m3x2_ck = {
501 .name = "dpll4_m3x2_ck", 635 .name = "dpll4_m3x2_ck",
502 .parent = &dpll4_x2_ck, 636 .parent = &dpll4_m3_ck,
503 .init = &omap2_init_clksel_parent, 637 .init = &omap2_init_clksel_parent,
504 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 638 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
505 .enable_bit = OMAP3430_PWRDN_TV_SHIFT, 639 .enable_bit = OMAP3430_PWRDN_TV_SHIFT,
506 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
507 .clksel_mask = OMAP3430_CLKSEL_TV_MASK,
508 .clksel = div16_dpll4_clksel,
509 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, 640 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
641 .recalc = &omap3_clkoutx2_recalc,
642};
643
644static const struct clksel virt_omap_54m_fck_clksel[] = {
645 { .parent = &sys_ck, .rates = dpll_bypass_rates },
646 { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates },
647 { .parent = NULL }
648};
649
650static struct clk virt_omap_54m_fck = {
651 .name = "virt_omap_54m_fck",
652 .parent = &dpll4_m3x2_ck,
653 .init = &omap2_init_clksel_parent,
654 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
655 .clksel_mask = OMAP3430_ST_PERIPH_CLK,
656 .clksel = virt_omap_54m_fck_clksel,
657 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
658 PARENT_CONTROLS_CLOCK,
510 .recalc = &omap2_clksel_recalc, 659 .recalc = &omap2_clksel_recalc,
511}; 660};
512 661
@@ -521,7 +670,7 @@ static const struct clksel_rate omap_54m_alt_rates[] = {
521}; 670};
522 671
523static const struct clksel omap_54m_clksel[] = { 672static const struct clksel omap_54m_clksel[] = {
524 { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates }, 673 { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates },
525 { .parent = &sys_altclk, .rates = omap_54m_alt_rates }, 674 { .parent = &sys_altclk, .rates = omap_54m_alt_rates },
526 { .parent = NULL } 675 { .parent = NULL }
527}; 676};
@@ -573,46 +722,74 @@ static struct clk omap_12m_fck = {
573 .recalc = &omap2_fixed_divisor_recalc, 722 .recalc = &omap2_fixed_divisor_recalc,
574}; 723};
575 724
725/* This virstual clock is the source for dpll4_m4x2_ck */
726static struct clk dpll4_m4_ck = {
727 .name = "dpll4_m4_ck",
728 .parent = &dpll4_ck,
729 .init = &omap2_init_clksel_parent,
730 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
731 .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK,
732 .clksel = div16_dpll4_clksel,
733 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
734 PARENT_CONTROLS_CLOCK,
735 .recalc = &omap2_clksel_recalc,
736};
737
576/* The PWRDN bit is apparently only available on 3430ES2 and above */ 738/* The PWRDN bit is apparently only available on 3430ES2 and above */
577static struct clk dpll4_m4x2_ck = { 739static struct clk dpll4_m4x2_ck = {
578 .name = "dpll4_m4x2_ck", 740 .name = "dpll4_m4x2_ck",
579 .parent = &dpll4_x2_ck, 741 .parent = &dpll4_m4_ck,
580 .init = &omap2_init_clksel_parent,
581 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 742 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
582 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, 743 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
583 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
584 .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK,
585 .clksel = div16_dpll4_clksel,
586 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, 744 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
745 .recalc = &omap3_clkoutx2_recalc,
746};
747
748/* This virtual clock is the source for dpll4_m5x2_ck */
749static struct clk dpll4_m5_ck = {
750 .name = "dpll4_m5_ck",
751 .parent = &dpll4_ck,
752 .init = &omap2_init_clksel_parent,
753 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
754 .clksel_mask = OMAP3430_CLKSEL_CAM_MASK,
755 .clksel = div16_dpll4_clksel,
756 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
757 PARENT_CONTROLS_CLOCK,
587 .recalc = &omap2_clksel_recalc, 758 .recalc = &omap2_clksel_recalc,
588}; 759};
589 760
590/* The PWRDN bit is apparently only available on 3430ES2 and above */ 761/* The PWRDN bit is apparently only available on 3430ES2 and above */
591static struct clk dpll4_m5x2_ck = { 762static struct clk dpll4_m5x2_ck = {
592 .name = "dpll4_m5x2_ck", 763 .name = "dpll4_m5x2_ck",
593 .parent = &dpll4_x2_ck, 764 .parent = &dpll4_m5_ck,
594 .init = &omap2_init_clksel_parent,
595 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 765 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
596 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, 766 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
597 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
598 .clksel_mask = OMAP3430_CLKSEL_CAM_MASK,
599 .clksel = div16_dpll4_clksel,
600 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, 767 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
768 .recalc = &omap3_clkoutx2_recalc,
769};
770
771/* This virtual clock is the source for dpll4_m6x2_ck */
772static struct clk dpll4_m6_ck = {
773 .name = "dpll4_m6_ck",
774 .parent = &dpll4_ck,
775 .init = &omap2_init_clksel_parent,
776 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
777 .clksel_mask = OMAP3430_DIV_DPLL4_MASK,
778 .clksel = div16_dpll4_clksel,
779 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
780 PARENT_CONTROLS_CLOCK,
601 .recalc = &omap2_clksel_recalc, 781 .recalc = &omap2_clksel_recalc,
602}; 782};
603 783
604/* The PWRDN bit is apparently only available on 3430ES2 and above */ 784/* The PWRDN bit is apparently only available on 3430ES2 and above */
605static struct clk dpll4_m6x2_ck = { 785static struct clk dpll4_m6x2_ck = {
606 .name = "dpll4_m6x2_ck", 786 .name = "dpll4_m6x2_ck",
607 .parent = &dpll4_x2_ck, 787 .parent = &dpll4_m6_ck,
608 .init = &omap2_init_clksel_parent, 788 .init = &omap2_init_clksel_parent,
609 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 789 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
610 .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT, 790 .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
611 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
612 .clksel_mask = OMAP3430_DIV_DPLL4_MASK,
613 .clksel = div16_dpll4_clksel,
614 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, 791 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
615 .recalc = &omap2_clksel_recalc, 792 .recalc = &omap3_clkoutx2_recalc,
616}; 793};
617 794
618static struct clk emu_per_alwon_ck = { 795static struct clk emu_per_alwon_ck = {
@@ -647,7 +824,7 @@ static struct clk dpll5_ck = {
647 .recalc = &omap3_dpll_recalc, 824 .recalc = &omap3_dpll_recalc,
648}; 825};
649 826
650static const struct clksel div16_dpll5m2_clksel[] = { 827static const struct clksel div16_dpll5_clksel[] = {
651 { .parent = &dpll5_ck, .rates = div16_dpll_rates }, 828 { .parent = &dpll5_ck, .rates = div16_dpll_rates },
652 { .parent = NULL } 829 { .parent = NULL }
653}; 830};
@@ -658,16 +835,27 @@ static struct clk dpll5_m2_ck = {
658 .init = &omap2_init_clksel_parent, 835 .init = &omap2_init_clksel_parent,
659 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5), 836 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
660 .clksel_mask = OMAP3430ES2_DIV_120M_MASK, 837 .clksel_mask = OMAP3430ES2_DIV_120M_MASK,
661 .clksel = div16_dpll5m2_clksel, 838 .clksel = div16_dpll5_clksel,
662 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES, 839 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
663 .recalc = &omap2_clksel_recalc, 840 .recalc = &omap2_clksel_recalc,
664}; 841};
665 842
843static const struct clksel omap_120m_fck_clksel[] = {
844 { .parent = &sys_ck, .rates = dpll_bypass_rates },
845 { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates },
846 { .parent = NULL }
847};
848
666static struct clk omap_120m_fck = { 849static struct clk omap_120m_fck = {
667 .name = "omap_120m_fck", 850 .name = "omap_120m_fck",
668 .parent = &dpll5_m2_ck, 851 .parent = &dpll5_m2_ck,
669 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES, 852 .init = &omap2_init_clksel_parent,
670 .recalc = &followparent_recalc, 853 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
854 .clksel_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
855 .clksel = omap_120m_fck_clksel,
856 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
857 PARENT_CONTROLS_CLOCK,
858 .recalc = &omap2_clksel_recalc,
671}; 859};
672 860
673/* CM EXTERNAL CLOCK OUTPUTS */ 861/* CM EXTERNAL CLOCK OUTPUTS */
@@ -753,10 +941,10 @@ static const struct clksel div2_core_clksel[] = {
753 { .parent = NULL } 941 { .parent = NULL }
754}; 942};
755 943
756/* TRM s. 4.7.7.4 lists the input for these two clocks as CORE_CK, 944/*
757 but presuming that is an error, or at least an overgeneralization */ 945 * REVISIT: Are these in DPLL power domain or CM power domain? docs
758/* REVISIT: Are these in DPLL power domain or CM power domain? docs 946 * may be inconsistent here?
759 may be inconsistent here? */ 947 */
760static struct clk dpll1_fck = { 948static struct clk dpll1_fck = {
761 .name = "dpll1_fck", 949 .name = "dpll1_fck",
762 .parent = &core_ck, 950 .parent = &core_ck,
@@ -769,6 +957,66 @@ static struct clk dpll1_fck = {
769 .recalc = &omap2_clksel_recalc, 957 .recalc = &omap2_clksel_recalc,
770}; 958};
771 959
960/*
961 * MPU clksel:
962 * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck
963 * derives from the high-frequency bypass clock originating from DPLL3,
964 * called 'dpll1_fck'
965 */
966static const struct clksel mpu_clksel[] = {
967 { .parent = &dpll1_fck, .rates = dpll_bypass_rates },
968 { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates },
969 { .parent = NULL }
970};
971
972static struct clk mpu_ck = {
973 .name = "mpu_ck",
974 .parent = &dpll1_x2m2_ck,
975 .init = &omap2_init_clksel_parent,
976 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
977 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
978 .clksel = mpu_clksel,
979 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
980 PARENT_CONTROLS_CLOCK,
981 .recalc = &omap2_clksel_recalc,
982};
983
984/* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
985static const struct clksel_rate arm_fck_rates[] = {
986 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
987 { .div = 2, .val = 1, .flags = RATE_IN_343X },
988 { .div = 0 },
989};
990
991static const struct clksel arm_fck_clksel[] = {
992 { .parent = &mpu_ck, .rates = arm_fck_rates },
993 { .parent = NULL }
994};
995
996static struct clk arm_fck = {
997 .name = "arm_fck",
998 .parent = &mpu_ck,
999 .init = &omap2_init_clksel_parent,
1000 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1001 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
1002 .clksel = arm_fck_clksel,
1003 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1004 PARENT_CONTROLS_CLOCK,
1005 .recalc = &omap2_clksel_recalc,
1006};
1007
1008/*
1009 * REVISIT: This clock is never specifically defined in the 3430 TRM,
1010 * although it is referenced - so this is a guess
1011 */
1012static struct clk emu_mpu_alwon_ck = {
1013 .name = "emu_mpu_alwon_ck",
1014 .parent = &mpu_ck,
1015 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1016 PARENT_CONTROLS_CLOCK,
1017 .recalc = &followparent_recalc,
1018};
1019
772static struct clk dpll2_fck = { 1020static struct clk dpll2_fck = {
773 .name = "dpll2_fck", 1021 .name = "dpll2_fck",
774 .parent = &core_ck, 1022 .parent = &core_ck,
@@ -781,6 +1029,32 @@ static struct clk dpll2_fck = {
781 .recalc = &omap2_clksel_recalc, 1029 .recalc = &omap2_clksel_recalc,
782}; 1030};
783 1031
1032/*
1033 * IVA2 clksel:
1034 * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck
1035 * derives from the high-frequency bypass clock originating from DPLL3,
1036 * called 'dpll2_fck'
1037 */
1038
1039static const struct clksel iva2_clksel[] = {
1040 { .parent = &dpll2_fck, .rates = dpll_bypass_rates },
1041 { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates },
1042 { .parent = NULL }
1043};
1044
1045static struct clk iva2_ck = {
1046 .name = "iva2_ck",
1047 .parent = &dpll2_m2_ck,
1048 .init = &omap2_init_clksel_parent,
1049 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
1050 OMAP3430_CM_IDLEST_PLL),
1051 .clksel_mask = OMAP3430_ST_IVA2_CLK_MASK,
1052 .clksel = iva2_clksel,
1053 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1054 PARENT_CONTROLS_CLOCK,
1055 .recalc = &omap2_clksel_recalc,
1056};
1057
784/* Common interface clocks */ 1058/* Common interface clocks */
785 1059
786static struct clk l3_ick = { 1060static struct clk l3_ick = {
@@ -831,7 +1105,7 @@ static struct clk rm_ick = {
831 1105
832/* GFX power domain */ 1106/* GFX power domain */
833 1107
834/* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */ 1108/* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
835 1109
836static const struct clksel gfx_l3_clksel[] = { 1110static const struct clksel gfx_l3_clksel[] = {
837 { .parent = &l3_ick, .rates = gfx_l3_rates }, 1111 { .parent = &l3_ick, .rates = gfx_l3_rates },
@@ -1645,14 +1919,23 @@ static struct clk des1_ick = {
1645}; 1919};
1646 1920
1647/* DSS */ 1921/* DSS */
1922static const struct clksel dss1_alwon_fck_clksel[] = {
1923 { .parent = &sys_ck, .rates = dpll_bypass_rates },
1924 { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates },
1925 { .parent = NULL }
1926};
1648 1927
1649static struct clk dss1_alwon_fck = { 1928static struct clk dss1_alwon_fck = {
1650 .name = "dss1_alwon_fck", 1929 .name = "dss1_alwon_fck",
1651 .parent = &dpll4_m4x2_ck, 1930 .parent = &dpll4_m4x2_ck,
1931 .init = &omap2_init_clksel_parent,
1652 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), 1932 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1653 .enable_bit = OMAP3430_EN_DSS1_SHIFT, 1933 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
1934 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
1935 .clksel_mask = OMAP3430_ST_PERIPH_CLK,
1936 .clksel = dss1_alwon_fck_clksel,
1654 .flags = CLOCK_IN_OMAP343X, 1937 .flags = CLOCK_IN_OMAP343X,
1655 .recalc = &followparent_recalc, 1938 .recalc = &omap2_clksel_recalc,
1656}; 1939};
1657 1940
1658static struct clk dss_tv_fck = { 1941static struct clk dss_tv_fck = {
@@ -1694,13 +1977,23 @@ static struct clk dss_ick = {
1694 1977
1695/* CAM */ 1978/* CAM */
1696 1979
1980static const struct clksel cam_mclk_clksel[] = {
1981 { .parent = &sys_ck, .rates = dpll_bypass_rates },
1982 { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates },
1983 { .parent = NULL }
1984};
1985
1697static struct clk cam_mclk = { 1986static struct clk cam_mclk = {
1698 .name = "cam_mclk", 1987 .name = "cam_mclk",
1699 .parent = &dpll4_m5x2_ck, 1988 .parent = &dpll4_m5x2_ck,
1989 .init = &omap2_init_clksel_parent,
1990 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
1991 .clksel_mask = OMAP3430_ST_PERIPH_CLK,
1992 .clksel = cam_mclk_clksel,
1700 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), 1993 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
1701 .enable_bit = OMAP3430_EN_CAM_SHIFT, 1994 .enable_bit = OMAP3430_EN_CAM_SHIFT,
1702 .flags = CLOCK_IN_OMAP343X, 1995 .flags = CLOCK_IN_OMAP343X,
1703 .recalc = &followparent_recalc, 1996 .recalc = &omap2_clksel_recalc,
1704}; 1997};
1705 1998
1706static struct clk cam_l3_ick = { 1999static struct clk cam_l3_ick = {
@@ -2497,7 +2790,6 @@ static struct clk wdt1_fck = {
2497 .recalc = &followparent_recalc, 2790 .recalc = &followparent_recalc,
2498}; 2791};
2499 2792
2500
2501static struct clk *onchip_34xx_clks[] __initdata = { 2793static struct clk *onchip_34xx_clks[] __initdata = {
2502 &omap_32k_fck, 2794 &omap_32k_fck,
2503 &virt_12m_ck, 2795 &virt_12m_ck,
@@ -2512,13 +2804,16 @@ static struct clk *onchip_34xx_clks[] __initdata = {
2512 &mcbsp_clks, 2804 &mcbsp_clks,
2513 &sys_clkout1, 2805 &sys_clkout1,
2514 &dpll1_ck, 2806 &dpll1_ck,
2515 &emu_mpu_alwon_ck, 2807 &dpll1_x2_ck,
2808 &dpll1_x2m2_ck,
2516 &dpll2_ck, 2809 &dpll2_ck,
2810 &dpll2_m2_ck,
2517 &dpll3_ck, 2811 &dpll3_ck,
2518 &core_ck, 2812 &core_ck,
2519 &dpll3_x2_ck, 2813 &dpll3_x2_ck,
2520 &dpll3_m2_ck, 2814 &dpll3_m2_ck,
2521 &dpll3_m2x2_ck, 2815 &dpll3_m2x2_ck,
2816 &dpll3_m3_ck,
2522 &dpll3_m3x2_ck, 2817 &dpll3_m3x2_ck,
2523 &emu_core_alwon_ck, 2818 &emu_core_alwon_ck,
2524 &dpll4_ck, 2819 &dpll4_ck,
@@ -2526,13 +2821,19 @@ static struct clk *onchip_34xx_clks[] __initdata = {
2526 &omap_96m_alwon_fck, 2821 &omap_96m_alwon_fck,
2527 &omap_96m_fck, 2822 &omap_96m_fck,
2528 &cm_96m_fck, 2823 &cm_96m_fck,
2824 &virt_omap_54m_fck,
2529 &omap_54m_fck, 2825 &omap_54m_fck,
2530 &omap_48m_fck, 2826 &omap_48m_fck,
2531 &omap_12m_fck, 2827 &omap_12m_fck,
2828 &dpll4_m2_ck,
2532 &dpll4_m2x2_ck, 2829 &dpll4_m2x2_ck,
2830 &dpll4_m3_ck,
2533 &dpll4_m3x2_ck, 2831 &dpll4_m3x2_ck,
2832 &dpll4_m4_ck,
2534 &dpll4_m4x2_ck, 2833 &dpll4_m4x2_ck,
2834 &dpll4_m5_ck,
2535 &dpll4_m5x2_ck, 2835 &dpll4_m5x2_ck,
2836 &dpll4_m6_ck,
2536 &dpll4_m6x2_ck, 2837 &dpll4_m6x2_ck,
2537 &emu_per_alwon_ck, 2838 &emu_per_alwon_ck,
2538 &dpll5_ck, 2839 &dpll5_ck,
@@ -2542,7 +2843,11 @@ static struct clk *onchip_34xx_clks[] __initdata = {
2542 &sys_clkout2, 2843 &sys_clkout2,
2543 &corex2_fck, 2844 &corex2_fck,
2544 &dpll1_fck, 2845 &dpll1_fck,
2846 &mpu_ck,
2847 &arm_fck,
2848 &emu_mpu_alwon_ck,
2545 &dpll2_fck, 2849 &dpll2_fck,
2850 &iva2_ck,
2546 &l3_ick, 2851 &l3_ick,
2547 &l4_ick, 2852 &l4_ick,
2548 &rm_ick, 2853 &rm_ick,
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index 317040887152..9249129a5f46 100644
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -115,6 +115,10 @@
115 115
116/* CM_IDLEST_PLL_MPU */ 116/* CM_IDLEST_PLL_MPU */
117#define OMAP3430_ST_MPU_CLK (1 << 0) 117#define OMAP3430_ST_MPU_CLK (1 << 0)
118#define OMAP3430_ST_IVA2_CLK_MASK (1 << 0)
119
120/* CM_IDLEST_PLL_MPU */
121#define OMAP3430_ST_MPU_CLK_MASK (1 << 0)
118 122
119/* CM_AUTOIDLE_PLL_MPU */ 123/* CM_AUTOIDLE_PLL_MPU */
120#define OMAP3430_AUTO_MPU_DPLL_SHIFT 0 124#define OMAP3430_AUTO_MPU_DPLL_SHIFT 0