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authorLinus Torvalds <torvalds@g5.osdl.org>2006-06-28 19:20:49 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2006-06-28 19:20:49 -0400
commit27d68a36c4f1ca2fc6be82620843493462c08c51 (patch)
treea06b451e19c25a77595c918ca81bbb30f0ec9ebf /arch
parent76a22271fd14e3fe7660f8646db12f0780fa4fd2 (diff)
parent583e7f5d36547f0d84caf71d43b71f0530a47766 (diff)
Merge branch 'nommu' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'nommu' of master.kernel.org:/home/rmk/linux-2.6-arm: [ARM] nommu: backtrace code must not reference a discarded section [ARM] nommu: Initial uCLinux support for MMU-based CPUs [ARM] nommu: prevent Xscale-based machines being selected [ARM] nommu: export flush_dcache_page() [ARM] nommu: remove fault-armv, mmap and mm-armv files from nommu build [ARM] Remove TABLE_SIZE, and several unused function prototypes [ARM] nommu: Provide a simple flush_dcache_page implementation [ARM] nommu: add arch/arm/Kconfig-nommu to Kconfig files [ARM] nommu: add stubs for ioremap and friends [ARM] nommu: avoid selecting TLB and CPU specific copy code [ARM] nommu: uaccess tweaks [ARM] nommu: adjust headers for !MMU ARM systems [ARM] nommu: we need the TLS register emulation for nommu mode
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/Kconfig9
-rw-r--r--arch/arm/kernel/armksyms.c7
-rw-r--r--arch/arm/kernel/vmlinux.lds.S8
-rw-r--r--arch/arm/lib/Makefile13
-rw-r--r--arch/arm/lib/backtrace.S5
-rw-r--r--arch/arm/mm/Kconfig67
-rw-r--r--arch/arm/mm/Makefile10
-rw-r--r--arch/arm/mm/init.c2
-rw-r--r--arch/arm/mm/iomap.c55
-rw-r--r--arch/arm/mm/ioremap.c47
-rw-r--r--arch/arm/mm/nommu.c39
-rw-r--r--arch/arm/mm/proc-arm1020.S9
-rw-r--r--arch/arm/mm/proc-arm1020e.S9
-rw-r--r--arch/arm/mm/proc-arm1022.S9
-rw-r--r--arch/arm/mm/proc-arm1026.S9
-rw-r--r--arch/arm/mm/proc-arm6_7.S15
-rw-r--r--arch/arm/mm/proc-arm720.S12
-rw-r--r--arch/arm/mm/proc-arm920.S9
-rw-r--r--arch/arm/mm/proc-arm922.S9
-rw-r--r--arch/arm/mm/proc-arm925.S10
-rw-r--r--arch/arm/mm/proc-arm926.S9
-rw-r--r--arch/arm/mm/proc-sa110.S11
-rw-r--r--arch/arm/mm/proc-sa1100.S11
-rw-r--r--arch/arm/mm/proc-v6.S7
24 files changed, 297 insertions, 94 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 3d1a3fb7d5fc..f123c7c9fc98 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -188,23 +188,27 @@ config ARCH_IMX
188 188
189config ARCH_IOP3XX 189config ARCH_IOP3XX
190 bool "IOP3xx-based" 190 bool "IOP3xx-based"
191 depends on MMU
191 select PCI 192 select PCI
192 help 193 help
193 Support for Intel's IOP3XX (XScale) family of processors. 194 Support for Intel's IOP3XX (XScale) family of processors.
194 195
195config ARCH_IXP4XX 196config ARCH_IXP4XX
196 bool "IXP4xx-based" 197 bool "IXP4xx-based"
198 depends on MMU
197 help 199 help
198 Support for Intel's IXP4XX (XScale) family of processors. 200 Support for Intel's IXP4XX (XScale) family of processors.
199 201
200config ARCH_IXP2000 202config ARCH_IXP2000
201 bool "IXP2400/2800-based" 203 bool "IXP2400/2800-based"
204 depends on MMU
202 select PCI 205 select PCI
203 help 206 help
204 Support for Intel's IXP2400/2800 (XScale) family of processors. 207 Support for Intel's IXP2400/2800 (XScale) family of processors.
205 208
206config ARCH_IXP23XX 209config ARCH_IXP23XX
207 bool "IXP23XX-based" 210 bool "IXP23XX-based"
211 depends on MMU
208 select PCI 212 select PCI
209 help 213 help
210 Support for Intel's IXP23xx (XScale) family of processors. 214 Support for Intel's IXP23xx (XScale) family of processors.
@@ -229,6 +233,7 @@ config ARCH_PNX4008
229 233
230config ARCH_PXA 234config ARCH_PXA
231 bool "PXA2xx-based" 235 bool "PXA2xx-based"
236 depends on MMU
232 select ARCH_MTD_XIP 237 select ARCH_MTD_XIP
233 help 238 help
234 Support for Intel's PXA2XX processor line. 239 Support for Intel's PXA2XX processor line.
@@ -339,6 +344,10 @@ config XSCALE_PMU
339 depends on CPU_XSCALE && !XSCALE_PMU_TIMER 344 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
340 default y 345 default y
341 346
347if !MMU
348source "arch/arm/Kconfig-nommu"
349endif
350
342endmenu 351endmenu
343 352
344source "arch/arm/common/Kconfig" 353source "arch/arm/common/Kconfig"
diff --git a/arch/arm/kernel/armksyms.c b/arch/arm/kernel/armksyms.c
index f8bb7abd3e9b..da69e660574b 100644
--- a/arch/arm/kernel/armksyms.c
+++ b/arch/arm/kernel/armksyms.c
@@ -109,11 +109,13 @@ EXPORT_SYMBOL(memchr);
109EXPORT_SYMBOL(__memzero); 109EXPORT_SYMBOL(__memzero);
110 110
111 /* user mem (segment) */ 111 /* user mem (segment) */
112EXPORT_SYMBOL(__strnlen_user);
113EXPORT_SYMBOL(__strncpy_from_user);
114
115#ifdef CONFIG_MMU
112EXPORT_SYMBOL(__copy_from_user); 116EXPORT_SYMBOL(__copy_from_user);
113EXPORT_SYMBOL(__copy_to_user); 117EXPORT_SYMBOL(__copy_to_user);
114EXPORT_SYMBOL(__clear_user); 118EXPORT_SYMBOL(__clear_user);
115EXPORT_SYMBOL(__strnlen_user);
116EXPORT_SYMBOL(__strncpy_from_user);
117 119
118EXPORT_SYMBOL(__get_user_1); 120EXPORT_SYMBOL(__get_user_1);
119EXPORT_SYMBOL(__get_user_2); 121EXPORT_SYMBOL(__get_user_2);
@@ -123,6 +125,7 @@ EXPORT_SYMBOL(__put_user_1);
123EXPORT_SYMBOL(__put_user_2); 125EXPORT_SYMBOL(__put_user_2);
124EXPORT_SYMBOL(__put_user_4); 126EXPORT_SYMBOL(__put_user_4);
125EXPORT_SYMBOL(__put_user_8); 127EXPORT_SYMBOL(__put_user_8);
128#endif
126 129
127 /* crypto hash */ 130 /* crypto hash */
128EXPORT_SYMBOL(sha_transform); 131EXPORT_SYMBOL(sha_transform);
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index 2b254e88595c..2df9688a7028 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -80,6 +80,10 @@ SECTIONS
80 *(.exit.text) 80 *(.exit.text)
81 *(.exit.data) 81 *(.exit.data)
82 *(.exitcall.exit) 82 *(.exitcall.exit)
83#ifndef CONFIG_MMU
84 *(.fixup)
85 *(__ex_table)
86#endif
83 } 87 }
84 88
85 .text : { /* Real text segment */ 89 .text : { /* Real text segment */
@@ -87,7 +91,9 @@ SECTIONS
87 *(.text) 91 *(.text)
88 SCHED_TEXT 92 SCHED_TEXT
89 LOCK_TEXT 93 LOCK_TEXT
94#ifdef CONFIG_MMU
90 *(.fixup) 95 *(.fixup)
96#endif
91 *(.gnu.warning) 97 *(.gnu.warning)
92 *(.rodata) 98 *(.rodata)
93 *(.rodata.*) 99 *(.rodata.*)
@@ -142,7 +148,9 @@ SECTIONS
142 */ 148 */
143 . = ALIGN(32); 149 . = ALIGN(32);
144 __start___ex_table = .; 150 __start___ex_table = .;
151#ifdef CONFIG_MMU
145 *(__ex_table) 152 *(__ex_table)
153#endif
146 __stop___ex_table = .; 154 __stop___ex_table = .;
147 155
148 /* 156 /*
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 7b726b627ea5..30351cd4560d 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -6,28 +6,31 @@
6 6
7lib-y := backtrace.o changebit.o csumipv6.o csumpartial.o \ 7lib-y := backtrace.o changebit.o csumipv6.o csumpartial.o \
8 csumpartialcopy.o csumpartialcopyuser.o clearbit.o \ 8 csumpartialcopy.o csumpartialcopyuser.o clearbit.o \
9 copy_page.o delay.o findbit.o memchr.o memcpy.o \ 9 delay.o findbit.o memchr.o memcpy.o \
10 memmove.o memset.o memzero.o setbit.o \ 10 memmove.o memset.o memzero.o setbit.o \
11 strncpy_from_user.o strnlen_user.o \ 11 strncpy_from_user.o strnlen_user.o \
12 strchr.o strrchr.o \ 12 strchr.o strrchr.o \
13 testchangebit.o testclearbit.o testsetbit.o \ 13 testchangebit.o testclearbit.o testsetbit.o \
14 getuser.o putuser.o clear_user.o \
15 ashldi3.o ashrdi3.o lshrdi3.o muldi3.o \ 14 ashldi3.o ashrdi3.o lshrdi3.o muldi3.o \
16 ucmpdi2.o lib1funcs.o div64.o sha1.o \ 15 ucmpdi2.o lib1funcs.o div64.o sha1.o \
17 io-readsb.o io-writesb.o io-readsl.o io-writesl.o 16 io-readsb.o io-writesb.o io-readsl.o io-writesl.o
18 17
18mmu-y := clear_user.o copy_page.o getuser.o putuser.o
19
19# the code in uaccess.S is not preemption safe and 20# the code in uaccess.S is not preemption safe and
20# probably faster on ARMv3 only 21# probably faster on ARMv3 only
21ifeq ($(CONFIG_PREEMPT),y) 22ifeq ($(CONFIG_PREEMPT),y)
22 lib-y += copy_from_user.o copy_to_user.o 23 mmu-y += copy_from_user.o copy_to_user.o
23else 24else
24ifneq ($(CONFIG_CPU_32v3),y) 25ifneq ($(CONFIG_CPU_32v3),y)
25 lib-y += copy_from_user.o copy_to_user.o 26 mmu-y += copy_from_user.o copy_to_user.o
26else 27else
27 lib-y += uaccess.o 28 mmu-y += uaccess.o
28endif 29endif
29endif 30endif
30 31
32lib-$(CONFIG_MMU) += $(mmu-y)
33
31ifeq ($(CONFIG_CPU_32v3),y) 34ifeq ($(CONFIG_CPU_32v3),y)
32 lib-y += io-readsw-armv3.o io-writesw-armv3.o 35 lib-y += io-readsw-armv3.o io-writesw-armv3.o
33else 36else
diff --git a/arch/arm/lib/backtrace.S b/arch/arm/lib/backtrace.S
index 058b80d72aa1..91f993f2e9db 100644
--- a/arch/arm/lib/backtrace.S
+++ b/arch/arm/lib/backtrace.S
@@ -97,16 +97,13 @@ ENTRY(c_backtrace)
97 b 1007f 97 b 1007f
98 98
99/* 99/*
100 * Fixup for LDMDB 100 * Fixup for LDMDB. Note that this must not be in the fixup section.
101 */ 101 */
102 .section .fixup,"ax"
103 .align 0
1041007: ldr r0, =.Lbad 1021007: ldr r0, =.Lbad
105 mov r1, frame 103 mov r1, frame
106 bl printk 104 bl printk
107 ldmfd sp!, {r4 - r8, pc} 105 ldmfd sp!, {r4 - r8, pc}
108 .ltorg 106 .ltorg
109 .previous
110 107
111 .section __ex_table,"a" 108 .section __ex_table,"a"
112 .align 3 109 .align 3
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index ecf5e232a6fc..c4bca753165b 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -15,8 +15,8 @@ config CPU_ARM610
15 select CPU_32v3 15 select CPU_32v3
16 select CPU_CACHE_V3 16 select CPU_CACHE_V3
17 select CPU_CACHE_VIVT 17 select CPU_CACHE_VIVT
18 select CPU_COPY_V3 18 select CPU_COPY_V3 if MMU
19 select CPU_TLB_V3 19 select CPU_TLB_V3 if MMU
20 help 20 help
21 The ARM610 is the successor to the ARM3 processor 21 The ARM610 is the successor to the ARM3 processor
22 and was produced by VLSI Technology Inc. 22 and was produced by VLSI Technology Inc.
@@ -31,8 +31,8 @@ config CPU_ARM710
31 select CPU_32v3 31 select CPU_32v3
32 select CPU_CACHE_V3 32 select CPU_CACHE_V3
33 select CPU_CACHE_VIVT 33 select CPU_CACHE_VIVT
34 select CPU_COPY_V3 34 select CPU_COPY_V3 if MMU
35 select CPU_TLB_V3 35 select CPU_TLB_V3 if MMU
36 help 36 help
37 A 32-bit RISC microprocessor based on the ARM7 processor core 37 A 32-bit RISC microprocessor based on the ARM7 processor core
38 designed by Advanced RISC Machines Ltd. The ARM710 is the 38 designed by Advanced RISC Machines Ltd. The ARM710 is the
@@ -50,8 +50,8 @@ config CPU_ARM720T
50 select CPU_ABRT_LV4T 50 select CPU_ABRT_LV4T
51 select CPU_CACHE_V4 51 select CPU_CACHE_V4
52 select CPU_CACHE_VIVT 52 select CPU_CACHE_VIVT
53 select CPU_COPY_V4WT 53 select CPU_COPY_V4WT if MMU
54 select CPU_TLB_V4WT 54 select CPU_TLB_V4WT if MMU
55 help 55 help
56 A 32-bit RISC processor with 8kByte Cache, Write Buffer and 56 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
57 MMU built around an ARM7TDMI core. 57 MMU built around an ARM7TDMI core.
@@ -68,8 +68,8 @@ config CPU_ARM920T
68 select CPU_ABRT_EV4T 68 select CPU_ABRT_EV4T
69 select CPU_CACHE_V4WT 69 select CPU_CACHE_V4WT
70 select CPU_CACHE_VIVT 70 select CPU_CACHE_VIVT
71 select CPU_COPY_V4WB 71 select CPU_COPY_V4WB if MMU
72 select CPU_TLB_V4WBI 72 select CPU_TLB_V4WBI if MMU
73 help 73 help
74 The ARM920T is licensed to be produced by numerous vendors, 74 The ARM920T is licensed to be produced by numerous vendors,
75 and is used in the Maverick EP9312 and the Samsung S3C2410. 75 and is used in the Maverick EP9312 and the Samsung S3C2410.
@@ -89,8 +89,8 @@ config CPU_ARM922T
89 select CPU_ABRT_EV4T 89 select CPU_ABRT_EV4T
90 select CPU_CACHE_V4WT 90 select CPU_CACHE_V4WT
91 select CPU_CACHE_VIVT 91 select CPU_CACHE_VIVT
92 select CPU_COPY_V4WB 92 select CPU_COPY_V4WB if MMU
93 select CPU_TLB_V4WBI 93 select CPU_TLB_V4WBI if MMU
94 help 94 help
95 The ARM922T is a version of the ARM920T, but with smaller 95 The ARM922T is a version of the ARM920T, but with smaller
96 instruction and data caches. It is used in Altera's 96 instruction and data caches. It is used in Altera's
@@ -108,8 +108,8 @@ config CPU_ARM925T
108 select CPU_ABRT_EV4T 108 select CPU_ABRT_EV4T
109 select CPU_CACHE_V4WT 109 select CPU_CACHE_V4WT
110 select CPU_CACHE_VIVT 110 select CPU_CACHE_VIVT
111 select CPU_COPY_V4WB 111 select CPU_COPY_V4WB if MMU
112 select CPU_TLB_V4WBI 112 select CPU_TLB_V4WBI if MMU
113 help 113 help
114 The ARM925T is a mix between the ARM920T and ARM926T, but with 114 The ARM925T is a mix between the ARM920T and ARM926T, but with
115 different instruction and data caches. It is used in TI's OMAP 115 different instruction and data caches. It is used in TI's OMAP
@@ -126,8 +126,8 @@ config CPU_ARM926T
126 select CPU_32v5 126 select CPU_32v5
127 select CPU_ABRT_EV5TJ 127 select CPU_ABRT_EV5TJ
128 select CPU_CACHE_VIVT 128 select CPU_CACHE_VIVT
129 select CPU_COPY_V4WB 129 select CPU_COPY_V4WB if MMU
130 select CPU_TLB_V4WBI 130 select CPU_TLB_V4WBI if MMU
131 help 131 help
132 This is a variant of the ARM920. It has slightly different 132 This is a variant of the ARM920. It has slightly different
133 instruction sequences for cache and TLB operations. Curiously, 133 instruction sequences for cache and TLB operations. Curiously,
@@ -144,8 +144,8 @@ config CPU_ARM1020
144 select CPU_ABRT_EV4T 144 select CPU_ABRT_EV4T
145 select CPU_CACHE_V4WT 145 select CPU_CACHE_V4WT
146 select CPU_CACHE_VIVT 146 select CPU_CACHE_VIVT
147 select CPU_COPY_V4WB 147 select CPU_COPY_V4WB if MMU
148 select CPU_TLB_V4WBI 148 select CPU_TLB_V4WBI if MMU
149 help 149 help
150 The ARM1020 is the 32K cached version of the ARM10 processor, 150 The ARM1020 is the 32K cached version of the ARM10 processor,
151 with an addition of a floating-point unit. 151 with an addition of a floating-point unit.
@@ -161,8 +161,8 @@ config CPU_ARM1020E
161 select CPU_ABRT_EV4T 161 select CPU_ABRT_EV4T
162 select CPU_CACHE_V4WT 162 select CPU_CACHE_V4WT
163 select CPU_CACHE_VIVT 163 select CPU_CACHE_VIVT
164 select CPU_COPY_V4WB 164 select CPU_COPY_V4WB if MMU
165 select CPU_TLB_V4WBI 165 select CPU_TLB_V4WBI if MMU
166 depends on n 166 depends on n
167 167
168# ARM1022E 168# ARM1022E
@@ -172,8 +172,8 @@ config CPU_ARM1022
172 select CPU_32v5 172 select CPU_32v5
173 select CPU_ABRT_EV4T 173 select CPU_ABRT_EV4T
174 select CPU_CACHE_VIVT 174 select CPU_CACHE_VIVT
175 select CPU_COPY_V4WB # can probably do better 175 select CPU_COPY_V4WB if MMU # can probably do better
176 select CPU_TLB_V4WBI 176 select CPU_TLB_V4WBI if MMU
177 help 177 help
178 The ARM1022E is an implementation of the ARMv5TE architecture 178 The ARM1022E is an implementation of the ARMv5TE architecture
179 based upon the ARM10 integer core with a 16KiB L1 Harvard cache, 179 based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
@@ -189,8 +189,8 @@ config CPU_ARM1026
189 select CPU_32v5 189 select CPU_32v5
190 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10 190 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
191 select CPU_CACHE_VIVT 191 select CPU_CACHE_VIVT
192 select CPU_COPY_V4WB # can probably do better 192 select CPU_COPY_V4WB if MMU # can probably do better
193 select CPU_TLB_V4WBI 193 select CPU_TLB_V4WBI if MMU
194 help 194 help
195 The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture 195 The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
196 based upon the ARM10 integer core. 196 based upon the ARM10 integer core.
@@ -207,8 +207,8 @@ config CPU_SA110
207 select CPU_ABRT_EV4 207 select CPU_ABRT_EV4
208 select CPU_CACHE_V4WB 208 select CPU_CACHE_V4WB
209 select CPU_CACHE_VIVT 209 select CPU_CACHE_VIVT
210 select CPU_COPY_V4WB 210 select CPU_COPY_V4WB if MMU
211 select CPU_TLB_V4WB 211 select CPU_TLB_V4WB if MMU
212 help 212 help
213 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and 213 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
214 is available at five speeds ranging from 100 MHz to 233 MHz. 214 is available at five speeds ranging from 100 MHz to 233 MHz.
@@ -227,7 +227,7 @@ config CPU_SA1100
227 select CPU_ABRT_EV4 227 select CPU_ABRT_EV4
228 select CPU_CACHE_V4WB 228 select CPU_CACHE_V4WB
229 select CPU_CACHE_VIVT 229 select CPU_CACHE_VIVT
230 select CPU_TLB_V4WB 230 select CPU_TLB_V4WB if MMU
231 231
232# XScale 232# XScale
233config CPU_XSCALE 233config CPU_XSCALE
@@ -237,7 +237,7 @@ config CPU_XSCALE
237 select CPU_32v5 237 select CPU_32v5
238 select CPU_ABRT_EV5T 238 select CPU_ABRT_EV5T
239 select CPU_CACHE_VIVT 239 select CPU_CACHE_VIVT
240 select CPU_TLB_V4WBI 240 select CPU_TLB_V4WBI if MMU
241 241
242# XScale Core Version 3 242# XScale Core Version 3
243config CPU_XSC3 243config CPU_XSC3
@@ -247,7 +247,7 @@ config CPU_XSC3
247 select CPU_32v5 247 select CPU_32v5
248 select CPU_ABRT_EV5T 248 select CPU_ABRT_EV5T
249 select CPU_CACHE_VIVT 249 select CPU_CACHE_VIVT
250 select CPU_TLB_V4WBI 250 select CPU_TLB_V4WBI if MMU
251 select IO_36 251 select IO_36
252 252
253# ARMv6 253# ARMv6
@@ -258,8 +258,8 @@ config CPU_V6
258 select CPU_ABRT_EV6 258 select CPU_ABRT_EV6
259 select CPU_CACHE_V6 259 select CPU_CACHE_V6
260 select CPU_CACHE_VIPT 260 select CPU_CACHE_VIPT
261 select CPU_COPY_V6 261 select CPU_COPY_V6 if MMU
262 select CPU_TLB_V6 262 select CPU_TLB_V6 if MMU
263 263
264# ARMv6k 264# ARMv6k
265config CPU_32v6K 265config CPU_32v6K
@@ -277,17 +277,17 @@ config CPU_32v6K
277# This defines the compiler instruction set which depends on the machine type. 277# This defines the compiler instruction set which depends on the machine type.
278config CPU_32v3 278config CPU_32v3
279 bool 279 bool
280 select TLS_REG_EMUL if SMP 280 select TLS_REG_EMUL if SMP || !MMU
281 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP 281 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
282 282
283config CPU_32v4 283config CPU_32v4
284 bool 284 bool
285 select TLS_REG_EMUL if SMP 285 select TLS_REG_EMUL if SMP || !MMU
286 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP 286 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
287 287
288config CPU_32v5 288config CPU_32v5
289 bool 289 bool
290 select TLS_REG_EMUL if SMP 290 select TLS_REG_EMUL if SMP || !MMU
291 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP 291 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
292 292
293config CPU_32v6 293config CPU_32v6
@@ -334,6 +334,7 @@ config CPU_CACHE_VIVT
334config CPU_CACHE_VIPT 334config CPU_CACHE_VIPT
335 bool 335 bool
336 336
337if MMU
337# The copy-page model 338# The copy-page model
338config CPU_COPY_V3 339config CPU_COPY_V3
339 bool 340 bool
@@ -372,6 +373,8 @@ config CPU_TLB_V4WBI
372config CPU_TLB_V6 373config CPU_TLB_V6
373 bool 374 bool
374 375
376endif
377
375# 378#
376# CPU supports 36-bit I/O 379# CPU supports 36-bit I/O
377# 380#
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index 07a538505784..21a2770226ee 100644
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -2,10 +2,16 @@
2# Makefile for the linux arm-specific parts of the memory manager. 2# Makefile for the linux arm-specific parts of the memory manager.
3# 3#
4 4
5obj-y := consistent.o extable.o fault-armv.o \ 5obj-y := consistent.o extable.o fault.o init.o \
6 fault.o flush.o init.o ioremap.o mmap.o \ 6 iomap.o
7
8obj-$(CONFIG_MMU) += fault-armv.o flush.o ioremap.o mmap.o \
7 mm-armv.o 9 mm-armv.o
8 10
11ifneq ($(CONFIG_MMU),y)
12obj-y += nommu.o
13endif
14
9obj-$(CONFIG_MODULES) += proc-syms.o 15obj-$(CONFIG_MODULES) += proc-syms.o
10 16
11obj-$(CONFIG_ALIGNMENT_TRAP) += alignment.o 17obj-$(CONFIG_ALIGNMENT_TRAP) += alignment.o
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 9ea1f87a7079..989fd681c822 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -26,8 +26,6 @@
26#include <asm/mach/arch.h> 26#include <asm/mach/arch.h>
27#include <asm/mach/map.h> 27#include <asm/mach/map.h>
28 28
29#define TABLE_SIZE (2 * PTRS_PER_PTE * sizeof(pte_t))
30
31DEFINE_PER_CPU(struct mmu_gather, mmu_gathers); 29DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
32 30
33extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; 31extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
diff --git a/arch/arm/mm/iomap.c b/arch/arm/mm/iomap.c
new file mode 100644
index 000000000000..62066f3020c8
--- /dev/null
+++ b/arch/arm/mm/iomap.c
@@ -0,0 +1,55 @@
1/*
2 * linux/arch/arm/mm/iomap.c
3 *
4 * Map IO port and PCI memory spaces so that {read,write}[bwl] can
5 * be used to access this memory.
6 */
7#include <linux/module.h>
8#include <linux/pci.h>
9#include <linux/ioport.h>
10
11#include <asm/io.h>
12
13#ifdef __io
14void __iomem *ioport_map(unsigned long port, unsigned int nr)
15{
16 return __io(port);
17}
18EXPORT_SYMBOL(ioport_map);
19
20void ioport_unmap(void __iomem *addr)
21{
22}
23EXPORT_SYMBOL(ioport_unmap);
24#endif
25
26#ifdef CONFIG_PCI
27void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
28{
29 unsigned long start = pci_resource_start(dev, bar);
30 unsigned long len = pci_resource_len(dev, bar);
31 unsigned long flags = pci_resource_flags(dev, bar);
32
33 if (!len || !start)
34 return NULL;
35 if (maxlen && len > maxlen)
36 len = maxlen;
37 if (flags & IORESOURCE_IO)
38 return ioport_map(start, len);
39 if (flags & IORESOURCE_MEM) {
40 if (flags & IORESOURCE_CACHEABLE)
41 return ioremap(start, len);
42 return ioremap_nocache(start, len);
43 }
44 return NULL;
45}
46EXPORT_SYMBOL(pci_iomap);
47
48void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
49{
50 if ((unsigned long)addr >= VMALLOC_START &&
51 (unsigned long)addr < VMALLOC_END)
52 iounmap(addr);
53}
54EXPORT_SYMBOL(pci_iounmap);
55#endif
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index c1f7180c7bed..7691cfdba567 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -176,50 +176,3 @@ void __iounmap(void __iomem *addr)
176 vunmap((void *)(PAGE_MASK & (unsigned long)addr)); 176 vunmap((void *)(PAGE_MASK & (unsigned long)addr));
177} 177}
178EXPORT_SYMBOL(__iounmap); 178EXPORT_SYMBOL(__iounmap);
179
180#ifdef __io
181void __iomem *ioport_map(unsigned long port, unsigned int nr)
182{
183 return __io(port);
184}
185EXPORT_SYMBOL(ioport_map);
186
187void ioport_unmap(void __iomem *addr)
188{
189}
190EXPORT_SYMBOL(ioport_unmap);
191#endif
192
193#ifdef CONFIG_PCI
194#include <linux/pci.h>
195#include <linux/ioport.h>
196
197void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
198{
199 unsigned long start = pci_resource_start(dev, bar);
200 unsigned long len = pci_resource_len(dev, bar);
201 unsigned long flags = pci_resource_flags(dev, bar);
202
203 if (!len || !start)
204 return NULL;
205 if (maxlen && len > maxlen)
206 len = maxlen;
207 if (flags & IORESOURCE_IO)
208 return ioport_map(start, len);
209 if (flags & IORESOURCE_MEM) {
210 if (flags & IORESOURCE_CACHEABLE)
211 return ioremap(start, len);
212 return ioremap_nocache(start, len);
213 }
214 return NULL;
215}
216EXPORT_SYMBOL(pci_iomap);
217
218void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
219{
220 if ((unsigned long)addr >= VMALLOC_START &&
221 (unsigned long)addr < VMALLOC_END)
222 iounmap(addr);
223}
224EXPORT_SYMBOL(pci_iounmap);
225#endif
diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c
new file mode 100644
index 000000000000..1464ed817b5d
--- /dev/null
+++ b/arch/arm/mm/nommu.c
@@ -0,0 +1,39 @@
1/*
2 * linux/arch/arm/mm/nommu.c
3 *
4 * ARM uCLinux supporting functions.
5 */
6#include <linux/module.h>
7#include <linux/mm.h>
8#include <linux/pagemap.h>
9
10#include <asm/cacheflush.h>
11#include <asm/io.h>
12#include <asm/page.h>
13
14void flush_dcache_page(struct page *page)
15{
16 __cpuc_flush_dcache_page(page_address(page));
17}
18EXPORT_SYMBOL(flush_dcache_page);
19
20void __iomem *__ioremap_pfn(unsigned long pfn, unsigned long offset,
21 size_t size, unsigned long flags)
22{
23 if (pfn >= (0x100000000ULL >> PAGE_SHIFT))
24 return NULL;
25 return (void __iomem *) (offset + (pfn << PAGE_SHIFT));
26}
27EXPORT_SYMBOL(__ioremap_pfn);
28
29void __iomem *__ioremap(unsigned long phys_addr, size_t size,
30 unsigned long flags)
31{
32 return (void __iomem *)phys_addr;
33}
34EXPORT_SYMBOL(__ioremap);
35
36void __iounmap(void __iomem *addr)
37{
38}
39EXPORT_SYMBOL(__iounmap);
diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
index 959588884fa5..b9abbafca812 100644
--- a/arch/arm/mm/proc-arm1020.S
+++ b/arch/arm/mm/proc-arm1020.S
@@ -3,6 +3,7 @@
3 * 3 *
4 * Copyright (C) 2000 ARM Limited 4 * Copyright (C) 2000 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd. 5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
6 * hacked for non-paged-MM by Hyok S. Choi, 2003.
6 * 7 *
7 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by 9 * it under the terms of the GNU General Public License as published by
@@ -101,7 +102,9 @@ ENTRY(cpu_arm1020_reset)
101 mov ip, #0 102 mov ip, #0
102 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 103 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
103 mcr p15, 0, ip, c7, c10, 4 @ drain WB 104 mcr p15, 0, ip, c7, c10, 4 @ drain WB
105#ifdef CONFIG_MMU
104 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 106 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
107#endif
105 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 108 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
106 bic ip, ip, #0x000f @ ............wcam 109 bic ip, ip, #0x000f @ ............wcam
107 bic ip, ip, #0x1100 @ ...i...s........ 110 bic ip, ip, #0x1100 @ ...i...s........
@@ -359,6 +362,7 @@ ENTRY(cpu_arm1020_dcache_clean_area)
359 */ 362 */
360 .align 5 363 .align 5
361ENTRY(cpu_arm1020_switch_mm) 364ENTRY(cpu_arm1020_switch_mm)
365#ifdef CONFIG_MMU
362#ifndef CONFIG_CPU_DCACHE_DISABLE 366#ifndef CONFIG_CPU_DCACHE_DISABLE
363 mcr p15, 0, r3, c7, c10, 4 367 mcr p15, 0, r3, c7, c10, 4
364 mov r1, #0xF @ 16 segments 368 mov r1, #0xF @ 16 segments
@@ -383,6 +387,7 @@ ENTRY(cpu_arm1020_switch_mm)
383 mcr p15, 0, r1, c7, c10, 4 @ drain WB 387 mcr p15, 0, r1, c7, c10, 4 @ drain WB
384 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 388 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
385 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs 389 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
390#endif /* CONFIG_MMU */
386 mov pc, lr 391 mov pc, lr
387 392
388/* 393/*
@@ -392,6 +397,7 @@ ENTRY(cpu_arm1020_switch_mm)
392 */ 397 */
393 .align 5 398 .align 5
394ENTRY(cpu_arm1020_set_pte) 399ENTRY(cpu_arm1020_set_pte)
400#ifdef CONFIG_MMU
395 str r1, [r0], #-2048 @ linux version 401 str r1, [r0], #-2048 @ linux version
396 402
397 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY 403 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
@@ -421,6 +427,7 @@ ENTRY(cpu_arm1020_set_pte)
421 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 427 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
422#endif 428#endif
423 mcr p15, 0, r0, c7, c10, 4 @ drain WB 429 mcr p15, 0, r0, c7, c10, 4 @ drain WB
430#endif /* CONFIG_MMU */
424 mov pc, lr 431 mov pc, lr
425 432
426 __INIT 433 __INIT
@@ -430,7 +437,9 @@ __arm1020_setup:
430 mov r0, #0 437 mov r0, #0
431 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 438 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
432 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 439 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
440#ifdef CONFIG_MMU
433 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 441 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
442#endif
434 mrc p15, 0, r0, c1, c0 @ get control register v4 443 mrc p15, 0, r0, c1, c0 @ get control register v4
435 ldr r5, arm1020_cr1_clear 444 ldr r5, arm1020_cr1_clear
436 bic r0, r0, r5 445 bic r0, r0, r5
diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S
index be6d081ff2b7..bcd5ee022e00 100644
--- a/arch/arm/mm/proc-arm1020e.S
+++ b/arch/arm/mm/proc-arm1020e.S
@@ -3,6 +3,7 @@
3 * 3 *
4 * Copyright (C) 2000 ARM Limited 4 * Copyright (C) 2000 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd. 5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
6 * hacked for non-paged-MM by Hyok S. Choi, 2003.
6 * 7 *
7 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by 9 * it under the terms of the GNU General Public License as published by
@@ -101,7 +102,9 @@ ENTRY(cpu_arm1020e_reset)
101 mov ip, #0 102 mov ip, #0
102 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 103 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
103 mcr p15, 0, ip, c7, c10, 4 @ drain WB 104 mcr p15, 0, ip, c7, c10, 4 @ drain WB
105#ifdef CONFIG_MMU
104 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 106 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
107#endif
105 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 108 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
106 bic ip, ip, #0x000f @ ............wcam 109 bic ip, ip, #0x000f @ ............wcam
107 bic ip, ip, #0x1100 @ ...i...s........ 110 bic ip, ip, #0x1100 @ ...i...s........
@@ -344,6 +347,7 @@ ENTRY(cpu_arm1020e_dcache_clean_area)
344 */ 347 */
345 .align 5 348 .align 5
346ENTRY(cpu_arm1020e_switch_mm) 349ENTRY(cpu_arm1020e_switch_mm)
350#ifdef CONFIG_MMU
347#ifndef CONFIG_CPU_DCACHE_DISABLE 351#ifndef CONFIG_CPU_DCACHE_DISABLE
348 mcr p15, 0, r3, c7, c10, 4 352 mcr p15, 0, r3, c7, c10, 4
349 mov r1, #0xF @ 16 segments 353 mov r1, #0xF @ 16 segments
@@ -367,6 +371,7 @@ ENTRY(cpu_arm1020e_switch_mm)
367 mcr p15, 0, r1, c7, c10, 4 @ drain WB 371 mcr p15, 0, r1, c7, c10, 4 @ drain WB
368 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 372 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
369 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs 373 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
374#endif
370 mov pc, lr 375 mov pc, lr
371 376
372/* 377/*
@@ -376,6 +381,7 @@ ENTRY(cpu_arm1020e_switch_mm)
376 */ 381 */
377 .align 5 382 .align 5
378ENTRY(cpu_arm1020e_set_pte) 383ENTRY(cpu_arm1020e_set_pte)
384#ifdef CONFIG_MMU
379 str r1, [r0], #-2048 @ linux version 385 str r1, [r0], #-2048 @ linux version
380 386
381 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY 387 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
@@ -403,6 +409,7 @@ ENTRY(cpu_arm1020e_set_pte)
403#ifndef CONFIG_CPU_DCACHE_DISABLE 409#ifndef CONFIG_CPU_DCACHE_DISABLE
404 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 410 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
405#endif 411#endif
412#endif /* CONFIG_MMU */
406 mov pc, lr 413 mov pc, lr
407 414
408 __INIT 415 __INIT
@@ -412,7 +419,9 @@ __arm1020e_setup:
412 mov r0, #0 419 mov r0, #0
413 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 420 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
414 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 421 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
422#ifdef CONFIG_MMU
415 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 423 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
424#endif
416 mrc p15, 0, r0, c1, c0 @ get control register v4 425 mrc p15, 0, r0, c1, c0 @ get control register v4
417 ldr r5, arm1020e_cr1_clear 426 ldr r5, arm1020e_cr1_clear
418 bic r0, r0, r5 427 bic r0, r0, r5
diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S
index f778545d57a2..b0ccff4fadd2 100644
--- a/arch/arm/mm/proc-arm1022.S
+++ b/arch/arm/mm/proc-arm1022.S
@@ -3,6 +3,7 @@
3 * 3 *
4 * Copyright (C) 2000 ARM Limited 4 * Copyright (C) 2000 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd. 5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
6 * hacked for non-paged-MM by Hyok S. Choi, 2003.
6 * 7 *
7 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by 9 * it under the terms of the GNU General Public License as published by
@@ -90,7 +91,9 @@ ENTRY(cpu_arm1022_reset)
90 mov ip, #0 91 mov ip, #0
91 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 92 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
92 mcr p15, 0, ip, c7, c10, 4 @ drain WB 93 mcr p15, 0, ip, c7, c10, 4 @ drain WB
94#ifdef CONFIG_MMU
93 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 95 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
96#endif
94 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 97 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
95 bic ip, ip, #0x000f @ ............wcam 98 bic ip, ip, #0x000f @ ............wcam
96 bic ip, ip, #0x1100 @ ...i...s........ 99 bic ip, ip, #0x1100 @ ...i...s........
@@ -333,6 +336,7 @@ ENTRY(cpu_arm1022_dcache_clean_area)
333 */ 336 */
334 .align 5 337 .align 5
335ENTRY(cpu_arm1022_switch_mm) 338ENTRY(cpu_arm1022_switch_mm)
339#ifdef CONFIG_MMU
336#ifndef CONFIG_CPU_DCACHE_DISABLE 340#ifndef CONFIG_CPU_DCACHE_DISABLE
337 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments 341 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments
3381: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries 3421: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
@@ -349,6 +353,7 @@ ENTRY(cpu_arm1022_switch_mm)
349 mcr p15, 0, r1, c7, c10, 4 @ drain WB 353 mcr p15, 0, r1, c7, c10, 4 @ drain WB
350 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 354 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
351 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs 355 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
356#endif
352 mov pc, lr 357 mov pc, lr
353 358
354/* 359/*
@@ -358,6 +363,7 @@ ENTRY(cpu_arm1022_switch_mm)
358 */ 363 */
359 .align 5 364 .align 5
360ENTRY(cpu_arm1022_set_pte) 365ENTRY(cpu_arm1022_set_pte)
366#ifdef CONFIG_MMU
361 str r1, [r0], #-2048 @ linux version 367 str r1, [r0], #-2048 @ linux version
362 368
363 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY 369 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
@@ -385,6 +391,7 @@ ENTRY(cpu_arm1022_set_pte)
385#ifndef CONFIG_CPU_DCACHE_DISABLE 391#ifndef CONFIG_CPU_DCACHE_DISABLE
386 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 392 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
387#endif 393#endif
394#endif /* CONFIG_MMU */
388 mov pc, lr 395 mov pc, lr
389 396
390 __INIT 397 __INIT
@@ -394,7 +401,9 @@ __arm1022_setup:
394 mov r0, #0 401 mov r0, #0
395 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 402 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
396 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 403 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
404#ifdef CONFIG_MMU
397 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 405 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
406#endif
398 mrc p15, 0, r0, c1, c0 @ get control register v4 407 mrc p15, 0, r0, c1, c0 @ get control register v4
399 ldr r5, arm1022_cr1_clear 408 ldr r5, arm1022_cr1_clear
400 bic r0, r0, r5 409 bic r0, r0, r5
diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S
index 148c111fde73..abe850c9a641 100644
--- a/arch/arm/mm/proc-arm1026.S
+++ b/arch/arm/mm/proc-arm1026.S
@@ -3,6 +3,7 @@
3 * 3 *
4 * Copyright (C) 2000 ARM Limited 4 * Copyright (C) 2000 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd. 5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
6 * hacked for non-paged-MM by Hyok S. Choi, 2003.
6 * 7 *
7 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by 9 * it under the terms of the GNU General Public License as published by
@@ -90,7 +91,9 @@ ENTRY(cpu_arm1026_reset)
90 mov ip, #0 91 mov ip, #0
91 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 92 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
92 mcr p15, 0, ip, c7, c10, 4 @ drain WB 93 mcr p15, 0, ip, c7, c10, 4 @ drain WB
94#ifdef CONFIG_MMU
93 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 95 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
96#endif
94 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 97 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
95 bic ip, ip, #0x000f @ ............wcam 98 bic ip, ip, #0x000f @ ............wcam
96 bic ip, ip, #0x1100 @ ...i...s........ 99 bic ip, ip, #0x1100 @ ...i...s........
@@ -327,6 +330,7 @@ ENTRY(cpu_arm1026_dcache_clean_area)
327 */ 330 */
328 .align 5 331 .align 5
329ENTRY(cpu_arm1026_switch_mm) 332ENTRY(cpu_arm1026_switch_mm)
333#ifdef CONFIG_MMU
330 mov r1, #0 334 mov r1, #0
331#ifndef CONFIG_CPU_DCACHE_DISABLE 335#ifndef CONFIG_CPU_DCACHE_DISABLE
3321: mrc p15, 0, r15, c7, c14, 3 @ test, clean, invalidate 3361: mrc p15, 0, r15, c7, c14, 3 @ test, clean, invalidate
@@ -338,6 +342,7 @@ ENTRY(cpu_arm1026_switch_mm)
338 mcr p15, 0, r1, c7, c10, 4 @ drain WB 342 mcr p15, 0, r1, c7, c10, 4 @ drain WB
339 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 343 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
340 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs 344 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
345#endif
341 mov pc, lr 346 mov pc, lr
342 347
343/* 348/*
@@ -347,6 +352,7 @@ ENTRY(cpu_arm1026_switch_mm)
347 */ 352 */
348 .align 5 353 .align 5
349ENTRY(cpu_arm1026_set_pte) 354ENTRY(cpu_arm1026_set_pte)
355#ifdef CONFIG_MMU
350 str r1, [r0], #-2048 @ linux version 356 str r1, [r0], #-2048 @ linux version
351 357
352 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY 358 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
@@ -374,6 +380,7 @@ ENTRY(cpu_arm1026_set_pte)
374#ifndef CONFIG_CPU_DCACHE_DISABLE 380#ifndef CONFIG_CPU_DCACHE_DISABLE
375 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 381 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
376#endif 382#endif
383#endif /* CONFIG_MMU */
377 mov pc, lr 384 mov pc, lr
378 385
379 386
@@ -384,8 +391,10 @@ __arm1026_setup:
384 mov r0, #0 391 mov r0, #0
385 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 392 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
386 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 393 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
394#ifdef CONFIG_MMU
387 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 395 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
388 mcr p15, 0, r4, c2, c0 @ load page table pointer 396 mcr p15, 0, r4, c2, c0 @ load page table pointer
397#endif
389#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH 398#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
390 mov r0, #4 @ explicitly disable writeback 399 mov r0, #4 @ explicitly disable writeback
391 mcr p15, 7, r0, c15, c0, 0 400 mcr p15, 7, r0, c15, c0, 0
diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S
index 540359b475d0..7a705edfa4b2 100644
--- a/arch/arm/mm/proc-arm6_7.S
+++ b/arch/arm/mm/proc-arm6_7.S
@@ -2,6 +2,7 @@
2 * linux/arch/arm/mm/proc-arm6,7.S 2 * linux/arch/arm/mm/proc-arm6,7.S
3 * 3 *
4 * Copyright (C) 1997-2000 Russell King 4 * Copyright (C) 1997-2000 Russell King
5 * hacked for non-paged-MM by Hyok S. Choi, 2003.
5 * 6 *
6 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 8 * it under the terms of the GNU General Public License version 2 as
@@ -199,10 +200,12 @@ ENTRY(cpu_arm7_do_idle)
199 */ 200 */
200ENTRY(cpu_arm6_switch_mm) 201ENTRY(cpu_arm6_switch_mm)
201ENTRY(cpu_arm7_switch_mm) 202ENTRY(cpu_arm7_switch_mm)
203#ifdef CONFIG_MMU
202 mov r1, #0 204 mov r1, #0
203 mcr p15, 0, r1, c7, c0, 0 @ flush cache 205 mcr p15, 0, r1, c7, c0, 0 @ flush cache
204 mcr p15, 0, r0, c2, c0, 0 @ update page table ptr 206 mcr p15, 0, r0, c2, c0, 0 @ update page table ptr
205 mcr p15, 0, r1, c5, c0, 0 @ flush TLBs 207 mcr p15, 0, r1, c5, c0, 0 @ flush TLBs
208#endif
206 mov pc, lr 209 mov pc, lr
207 210
208/* 211/*
@@ -214,6 +217,7 @@ ENTRY(cpu_arm7_switch_mm)
214 .align 5 217 .align 5
215ENTRY(cpu_arm6_set_pte) 218ENTRY(cpu_arm6_set_pte)
216ENTRY(cpu_arm7_set_pte) 219ENTRY(cpu_arm7_set_pte)
220#ifdef CONFIG_MMU
217 str r1, [r0], #-2048 @ linux version 221 str r1, [r0], #-2048 @ linux version
218 222
219 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY 223 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
@@ -232,6 +236,7 @@ ENTRY(cpu_arm7_set_pte)
232 movne r2, #0 236 movne r2, #0
233 237
234 str r2, [r0] @ hardware version 238 str r2, [r0] @ hardware version
239#endif /* CONFIG_MMU */
235 mov pc, lr 240 mov pc, lr
236 241
237/* 242/*
@@ -243,7 +248,9 @@ ENTRY(cpu_arm6_reset)
243ENTRY(cpu_arm7_reset) 248ENTRY(cpu_arm7_reset)
244 mov r1, #0 249 mov r1, #0
245 mcr p15, 0, r1, c7, c0, 0 @ flush cache 250 mcr p15, 0, r1, c7, c0, 0 @ flush cache
251#ifdef CONFIG_MMU
246 mcr p15, 0, r1, c5, c0, 0 @ flush TLB 252 mcr p15, 0, r1, c5, c0, 0 @ flush TLB
253#endif
247 mov r1, #0x30 254 mov r1, #0x30
248 mcr p15, 0, r1, c1, c0, 0 @ turn off MMU etc 255 mcr p15, 0, r1, c1, c0, 0 @ turn off MMU etc
249 mov pc, r0 256 mov pc, r0
@@ -253,19 +260,27 @@ ENTRY(cpu_arm7_reset)
253 .type __arm6_setup, #function 260 .type __arm6_setup, #function
254__arm6_setup: mov r0, #0 261__arm6_setup: mov r0, #0
255 mcr p15, 0, r0, c7, c0 @ flush caches on v3 262 mcr p15, 0, r0, c7, c0 @ flush caches on v3
263#ifdef CONFIG_MMU
256 mcr p15, 0, r0, c5, c0 @ flush TLBs on v3 264 mcr p15, 0, r0, c5, c0 @ flush TLBs on v3
257 mov r0, #0x3d @ . ..RS BLDP WCAM 265 mov r0, #0x3d @ . ..RS BLDP WCAM
258 orr r0, r0, #0x100 @ . ..01 0011 1101 266 orr r0, r0, #0x100 @ . ..01 0011 1101
267#else
268 mov r0, #0x3c @ . ..RS BLDP WCA.
269#endif
259 mov pc, lr 270 mov pc, lr
260 .size __arm6_setup, . - __arm6_setup 271 .size __arm6_setup, . - __arm6_setup
261 272
262 .type __arm7_setup, #function 273 .type __arm7_setup, #function
263__arm7_setup: mov r0, #0 274__arm7_setup: mov r0, #0
264 mcr p15, 0, r0, c7, c0 @ flush caches on v3 275 mcr p15, 0, r0, c7, c0 @ flush caches on v3
276#ifdef CONFIG_MMU
265 mcr p15, 0, r0, c5, c0 @ flush TLBs on v3 277 mcr p15, 0, r0, c5, c0 @ flush TLBs on v3
266 mcr p15, 0, r0, c3, c0 @ load domain access register 278 mcr p15, 0, r0, c3, c0 @ load domain access register
267 mov r0, #0x7d @ . ..RS BLDP WCAM 279 mov r0, #0x7d @ . ..RS BLDP WCAM
268 orr r0, r0, #0x100 @ . ..01 0111 1101 280 orr r0, r0, #0x100 @ . ..01 0111 1101
281#else
282 mov r0, #0x7c @ . ..RS BLDP WCA.
283#endif
269 mov pc, lr 284 mov pc, lr
270 .size __arm7_setup, . - __arm7_setup 285 .size __arm7_setup, . - __arm7_setup
271 286
diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S
index 26f00ee2ad9a..86102467d37f 100644
--- a/arch/arm/mm/proc-arm720.S
+++ b/arch/arm/mm/proc-arm720.S
@@ -4,6 +4,7 @@
4 * Copyright (C) 2000 Steve Hill (sjhill@cotw.com) 4 * Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
5 * Rob Scott (rscott@mtrob.fdns.net) 5 * Rob Scott (rscott@mtrob.fdns.net)
6 * Copyright (C) 2000 ARM Limited, Deep Blue Solutions Ltd. 6 * Copyright (C) 2000 ARM Limited, Deep Blue Solutions Ltd.
7 * hacked for non-paged-MM by Hyok S. Choi, 2004.
7 * 8 *
8 * This program is free software; you can redistribute it and/or modify 9 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by 10 * it under the terms of the GNU General Public License as published by
@@ -29,6 +30,7 @@
29 * out of 'proc-arm6,7.S' per RMK discussion 30 * out of 'proc-arm6,7.S' per RMK discussion
30 * 07-25-2000 SJH Added idle function. 31 * 07-25-2000 SJH Added idle function.
31 * 08-25-2000 DBS Updated for integration of ARM Ltd version. 32 * 08-25-2000 DBS Updated for integration of ARM Ltd version.
33 * 04-20-2004 HSC modified for non-paged memory management mode.
32 */ 34 */
33#include <linux/linkage.h> 35#include <linux/linkage.h>
34#include <linux/init.h> 36#include <linux/init.h>
@@ -75,10 +77,12 @@ ENTRY(cpu_arm720_do_idle)
75 * the new. 77 * the new.
76 */ 78 */
77ENTRY(cpu_arm720_switch_mm) 79ENTRY(cpu_arm720_switch_mm)
80#ifdef CONFIG_MMU
78 mov r1, #0 81 mov r1, #0
79 mcr p15, 0, r1, c7, c7, 0 @ invalidate cache 82 mcr p15, 0, r1, c7, c7, 0 @ invalidate cache
80 mcr p15, 0, r0, c2, c0, 0 @ update page table ptr 83 mcr p15, 0, r0, c2, c0, 0 @ update page table ptr
81 mcr p15, 0, r1, c8, c7, 0 @ flush TLB (v4) 84 mcr p15, 0, r1, c8, c7, 0 @ flush TLB (v4)
85#endif
82 mov pc, lr 86 mov pc, lr
83 87
84/* 88/*
@@ -89,6 +93,7 @@ ENTRY(cpu_arm720_switch_mm)
89 */ 93 */
90 .align 5 94 .align 5
91ENTRY(cpu_arm720_set_pte) 95ENTRY(cpu_arm720_set_pte)
96#ifdef CONFIG_MMU
92 str r1, [r0], #-2048 @ linux version 97 str r1, [r0], #-2048 @ linux version
93 98
94 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY 99 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
@@ -107,6 +112,7 @@ ENTRY(cpu_arm720_set_pte)
107 movne r2, #0 112 movne r2, #0
108 113
109 str r2, [r0] @ hardware version 114 str r2, [r0] @ hardware version
115#endif
110 mov pc, lr 116 mov pc, lr
111 117
112/* 118/*
@@ -117,7 +123,9 @@ ENTRY(cpu_arm720_set_pte)
117ENTRY(cpu_arm720_reset) 123ENTRY(cpu_arm720_reset)
118 mov ip, #0 124 mov ip, #0
119 mcr p15, 0, ip, c7, c7, 0 @ invalidate cache 125 mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
126#ifdef CONFIG_MMU
120 mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4) 127 mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
128#endif
121 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register 129 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
122 bic ip, ip, #0x000f @ ............wcam 130 bic ip, ip, #0x000f @ ............wcam
123 bic ip, ip, #0x2100 @ ..v....s........ 131 bic ip, ip, #0x2100 @ ..v....s........
@@ -130,7 +138,9 @@ ENTRY(cpu_arm720_reset)
130__arm710_setup: 138__arm710_setup:
131 mov r0, #0 139 mov r0, #0
132 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches 140 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
141#ifdef CONFIG_MMU
133 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4) 142 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
143#endif
134 mrc p15, 0, r0, c1, c0 @ get control register 144 mrc p15, 0, r0, c1, c0 @ get control register
135 ldr r5, arm710_cr1_clear 145 ldr r5, arm710_cr1_clear
136 bic r0, r0, r5 146 bic r0, r0, r5
@@ -156,7 +166,9 @@ arm710_cr1_set:
156__arm720_setup: 166__arm720_setup:
157 mov r0, #0 167 mov r0, #0
158 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches 168 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
169#ifdef CONFIG_MMU
159 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4) 170 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
171#endif
160 mrc p15, 0, r0, c1, c0 @ get control register 172 mrc p15, 0, r0, c1, c0 @ get control register
161 ldr r5, arm720_cr1_clear 173 ldr r5, arm720_cr1_clear
162 bic r0, r0, r5 174 bic r0, r0, r5
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
index a17f79e0199c..31dc839ba07c 100644
--- a/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@ -3,6 +3,7 @@
3 * 3 *
4 * Copyright (C) 1999,2000 ARM Limited 4 * Copyright (C) 1999,2000 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd. 5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
6 * hacked for non-paged-MM by Hyok S. Choi, 2003.
6 * 7 *
7 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by 9 * it under the terms of the GNU General Public License as published by
@@ -97,7 +98,9 @@ ENTRY(cpu_arm920_reset)
97 mov ip, #0 98 mov ip, #0
98 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 99 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
99 mcr p15, 0, ip, c7, c10, 4 @ drain WB 100 mcr p15, 0, ip, c7, c10, 4 @ drain WB
101#ifdef CONFIG_MMU
100 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 102 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
103#endif
101 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 104 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
102 bic ip, ip, #0x000f @ ............wcam 105 bic ip, ip, #0x000f @ ............wcam
103 bic ip, ip, #0x1100 @ ...i...s........ 106 bic ip, ip, #0x1100 @ ...i...s........
@@ -317,6 +320,7 @@ ENTRY(cpu_arm920_dcache_clean_area)
317 */ 320 */
318 .align 5 321 .align 5
319ENTRY(cpu_arm920_switch_mm) 322ENTRY(cpu_arm920_switch_mm)
323#ifdef CONFIG_MMU
320 mov ip, #0 324 mov ip, #0
321#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH 325#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
322 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 326 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
@@ -337,6 +341,7 @@ ENTRY(cpu_arm920_switch_mm)
337 mcr p15, 0, ip, c7, c10, 4 @ drain WB 341 mcr p15, 0, ip, c7, c10, 4 @ drain WB
338 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 342 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
339 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 343 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
344#endif
340 mov pc, lr 345 mov pc, lr
341 346
342/* 347/*
@@ -346,6 +351,7 @@ ENTRY(cpu_arm920_switch_mm)
346 */ 351 */
347 .align 5 352 .align 5
348ENTRY(cpu_arm920_set_pte) 353ENTRY(cpu_arm920_set_pte)
354#ifdef CONFIG_MMU
349 str r1, [r0], #-2048 @ linux version 355 str r1, [r0], #-2048 @ linux version
350 356
351 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY 357 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
@@ -372,6 +378,7 @@ ENTRY(cpu_arm920_set_pte)
372 mov r0, r0 378 mov r0, r0
373 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 379 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
374 mcr p15, 0, r0, c7, c10, 4 @ drain WB 380 mcr p15, 0, r0, c7, c10, 4 @ drain WB
381#endif /* CONFIG_MMU */
375 mov pc, lr 382 mov pc, lr
376 383
377 __INIT 384 __INIT
@@ -381,7 +388,9 @@ __arm920_setup:
381 mov r0, #0 388 mov r0, #0
382 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 389 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
383 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 390 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
391#ifdef CONFIG_MMU
384 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 392 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
393#endif
385 mrc p15, 0, r0, c1, c0 @ get control register v4 394 mrc p15, 0, r0, c1, c0 @ get control register v4
386 ldr r5, arm920_cr1_clear 395 ldr r5, arm920_cr1_clear
387 bic r0, r0, r5 396 bic r0, r0, r5
diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S
index bbde4a024a48..9e57c34f5c09 100644
--- a/arch/arm/mm/proc-arm922.S
+++ b/arch/arm/mm/proc-arm922.S
@@ -4,6 +4,7 @@
4 * Copyright (C) 1999,2000 ARM Limited 4 * Copyright (C) 1999,2000 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd. 5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
6 * Copyright (C) 2001 Altera Corporation 6 * Copyright (C) 2001 Altera Corporation
7 * hacked for non-paged-MM by Hyok S. Choi, 2003.
7 * 8 *
8 * This program is free software; you can redistribute it and/or modify 9 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by 10 * it under the terms of the GNU General Public License as published by
@@ -99,7 +100,9 @@ ENTRY(cpu_arm922_reset)
99 mov ip, #0 100 mov ip, #0
100 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 101 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
101 mcr p15, 0, ip, c7, c10, 4 @ drain WB 102 mcr p15, 0, ip, c7, c10, 4 @ drain WB
103#ifdef CONFIG_MMU
102 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 104 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
105#endif
103 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 106 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
104 bic ip, ip, #0x000f @ ............wcam 107 bic ip, ip, #0x000f @ ............wcam
105 bic ip, ip, #0x1100 @ ...i...s........ 108 bic ip, ip, #0x1100 @ ...i...s........
@@ -321,6 +324,7 @@ ENTRY(cpu_arm922_dcache_clean_area)
321 */ 324 */
322 .align 5 325 .align 5
323ENTRY(cpu_arm922_switch_mm) 326ENTRY(cpu_arm922_switch_mm)
327#ifdef CONFIG_MMU
324 mov ip, #0 328 mov ip, #0
325#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH 329#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
326 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 330 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
@@ -341,6 +345,7 @@ ENTRY(cpu_arm922_switch_mm)
341 mcr p15, 0, ip, c7, c10, 4 @ drain WB 345 mcr p15, 0, ip, c7, c10, 4 @ drain WB
342 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 346 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
343 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 347 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
348#endif
344 mov pc, lr 349 mov pc, lr
345 350
346/* 351/*
@@ -350,6 +355,7 @@ ENTRY(cpu_arm922_switch_mm)
350 */ 355 */
351 .align 5 356 .align 5
352ENTRY(cpu_arm922_set_pte) 357ENTRY(cpu_arm922_set_pte)
358#ifdef CONFIG_MMU
353 str r1, [r0], #-2048 @ linux version 359 str r1, [r0], #-2048 @ linux version
354 360
355 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY 361 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
@@ -376,6 +382,7 @@ ENTRY(cpu_arm922_set_pte)
376 mov r0, r0 382 mov r0, r0
377 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 383 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
378 mcr p15, 0, r0, c7, c10, 4 @ drain WB 384 mcr p15, 0, r0, c7, c10, 4 @ drain WB
385#endif /* CONFIG_MMU */
379 mov pc, lr 386 mov pc, lr
380 387
381 __INIT 388 __INIT
@@ -385,7 +392,9 @@ __arm922_setup:
385 mov r0, #0 392 mov r0, #0
386 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 393 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
387 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 394 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
395#ifdef CONFIG_MMU
388 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 396 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
397#endif
389 mrc p15, 0, r0, c1, c0 @ get control register v4 398 mrc p15, 0, r0, c1, c0 @ get control register v4
390 ldr r5, arm922_cr1_clear 399 ldr r5, arm922_cr1_clear
391 bic r0, r0, r5 400 bic r0, r0, r5
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index 224ce226a01b..8d47c9f3f931 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -9,6 +9,8 @@
9 * Update for Linux-2.6 and cache flush improvements 9 * Update for Linux-2.6 and cache flush improvements
10 * Copyright (C) 2004 Nokia Corporation by Tony Lindgren <tony@atomide.com> 10 * Copyright (C) 2004 Nokia Corporation by Tony Lindgren <tony@atomide.com>
11 * 11 *
12 * hacked for non-paged-MM by Hyok S. Choi, 2004.
13 *
12 * This program is free software; you can redistribute it and/or modify 14 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by 15 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or 16 * the Free Software Foundation; either version 2 of the License, or
@@ -122,7 +124,9 @@ ENTRY(cpu_arm925_reset)
122 mov ip, #0 124 mov ip, #0
123 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 125 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
124 mcr p15, 0, ip, c7, c10, 4 @ drain WB 126 mcr p15, 0, ip, c7, c10, 4 @ drain WB
127#ifdef CONFIG_MMU
125 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 128 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
129#endif
126 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 130 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
127 bic ip, ip, #0x000f @ ............wcam 131 bic ip, ip, #0x000f @ ............wcam
128 bic ip, ip, #0x1100 @ ...i...s........ 132 bic ip, ip, #0x1100 @ ...i...s........
@@ -369,6 +373,7 @@ ENTRY(cpu_arm925_dcache_clean_area)
369 */ 373 */
370 .align 5 374 .align 5
371ENTRY(cpu_arm925_switch_mm) 375ENTRY(cpu_arm925_switch_mm)
376#ifdef CONFIG_MMU
372 mov ip, #0 377 mov ip, #0
373#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH 378#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
374 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 379 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
@@ -383,6 +388,7 @@ ENTRY(cpu_arm925_switch_mm)
383 mcr p15, 0, ip, c7, c10, 4 @ drain WB 388 mcr p15, 0, ip, c7, c10, 4 @ drain WB
384 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 389 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
385 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 390 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
391#endif
386 mov pc, lr 392 mov pc, lr
387 393
388/* 394/*
@@ -392,6 +398,7 @@ ENTRY(cpu_arm925_switch_mm)
392 */ 398 */
393 .align 5 399 .align 5
394ENTRY(cpu_arm925_set_pte) 400ENTRY(cpu_arm925_set_pte)
401#ifdef CONFIG_MMU
395 str r1, [r0], #-2048 @ linux version 402 str r1, [r0], #-2048 @ linux version
396 403
397 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY 404 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
@@ -420,6 +427,7 @@ ENTRY(cpu_arm925_set_pte)
420 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 427 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
421#endif 428#endif
422 mcr p15, 0, r0, c7, c10, 4 @ drain WB 429 mcr p15, 0, r0, c7, c10, 4 @ drain WB
430#endif /* CONFIG_MMU */
423 mov pc, lr 431 mov pc, lr
424 432
425 __INIT 433 __INIT
@@ -438,7 +446,9 @@ __arm925_setup:
438 mov r0, #0 446 mov r0, #0
439 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 447 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
440 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 448 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
449#ifdef CONFIG_MMU
441 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 450 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
451#endif
442 452
443#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH 453#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
444 mov r0, #4 @ disable write-back on caches explicitly 454 mov r0, #4 @ disable write-back on caches explicitly
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 4e2a087cf388..cb4d8f33d2a3 100644
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -3,6 +3,7 @@
3 * 3 *
4 * Copyright (C) 1999-2001 ARM Limited 4 * Copyright (C) 1999-2001 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd. 5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
6 * hacked for non-paged-MM by Hyok S. Choi, 2003.
6 * 7 *
7 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by 9 * it under the terms of the GNU General Public License as published by
@@ -85,7 +86,9 @@ ENTRY(cpu_arm926_reset)
85 mov ip, #0 86 mov ip, #0
86 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 87 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
87 mcr p15, 0, ip, c7, c10, 4 @ drain WB 88 mcr p15, 0, ip, c7, c10, 4 @ drain WB
89#ifdef CONFIG_MMU
88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 90 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
91#endif
89 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 92 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
90 bic ip, ip, #0x000f @ ............wcam 93 bic ip, ip, #0x000f @ ............wcam
91 bic ip, ip, #0x1100 @ ...i...s........ 94 bic ip, ip, #0x1100 @ ...i...s........
@@ -329,6 +332,7 @@ ENTRY(cpu_arm926_dcache_clean_area)
329 */ 332 */
330 .align 5 333 .align 5
331ENTRY(cpu_arm926_switch_mm) 334ENTRY(cpu_arm926_switch_mm)
335#ifdef CONFIG_MMU
332 mov ip, #0 336 mov ip, #0
333#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH 337#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
334 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 338 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
@@ -341,6 +345,7 @@ ENTRY(cpu_arm926_switch_mm)
341 mcr p15, 0, ip, c7, c10, 4 @ drain WB 345 mcr p15, 0, ip, c7, c10, 4 @ drain WB
342 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 346 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
343 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 347 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
348#endif
344 mov pc, lr 349 mov pc, lr
345 350
346/* 351/*
@@ -350,6 +355,7 @@ ENTRY(cpu_arm926_switch_mm)
350 */ 355 */
351 .align 5 356 .align 5
352ENTRY(cpu_arm926_set_pte) 357ENTRY(cpu_arm926_set_pte)
358#ifdef CONFIG_MMU
353 str r1, [r0], #-2048 @ linux version 359 str r1, [r0], #-2048 @ linux version
354 360
355 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY 361 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
@@ -378,6 +384,7 @@ ENTRY(cpu_arm926_set_pte)
378 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 384 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
379#endif 385#endif
380 mcr p15, 0, r0, c7, c10, 4 @ drain WB 386 mcr p15, 0, r0, c7, c10, 4 @ drain WB
387#endif
381 mov pc, lr 388 mov pc, lr
382 389
383 __INIT 390 __INIT
@@ -387,7 +394,9 @@ __arm926_setup:
387 mov r0, #0 394 mov r0, #0
388 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 395 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
389 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 396 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
397#ifdef CONFIG_MMU
390 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 398 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
399#endif
391 400
392 401
393#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH 402#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S
index a2dd5ae1077d..5a760a2c629c 100644
--- a/arch/arm/mm/proc-sa110.S
+++ b/arch/arm/mm/proc-sa110.S
@@ -2,6 +2,7 @@
2 * linux/arch/arm/mm/proc-sa110.S 2 * linux/arch/arm/mm/proc-sa110.S
3 * 3 *
4 * Copyright (C) 1997-2002 Russell King 4 * Copyright (C) 1997-2002 Russell King
5 * hacked for non-paged-MM by Hyok S. Choi, 2003.
5 * 6 *
6 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 8 * it under the terms of the GNU General Public License version 2 as
@@ -67,7 +68,9 @@ ENTRY(cpu_sa110_reset)
67 mov ip, #0 68 mov ip, #0
68 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 69 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
69 mcr p15, 0, ip, c7, c10, 4 @ drain WB 70 mcr p15, 0, ip, c7, c10, 4 @ drain WB
71#ifdef CONFIG_MMU
70 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 72 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
73#endif
71 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 74 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
72 bic ip, ip, #0x000f @ ............wcam 75 bic ip, ip, #0x000f @ ............wcam
73 bic ip, ip, #0x1100 @ ...i...s........ 76 bic ip, ip, #0x1100 @ ...i...s........
@@ -130,11 +133,15 @@ ENTRY(cpu_sa110_dcache_clean_area)
130 */ 133 */
131 .align 5 134 .align 5
132ENTRY(cpu_sa110_switch_mm) 135ENTRY(cpu_sa110_switch_mm)
136#ifdef CONFIG_MMU
133 str lr, [sp, #-4]! 137 str lr, [sp, #-4]!
134 bl v4wb_flush_kern_cache_all @ clears IP 138 bl v4wb_flush_kern_cache_all @ clears IP
135 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 139 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
136 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 140 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
137 ldr pc, [sp], #4 141 ldr pc, [sp], #4
142#else
143 mov pc, lr
144#endif
138 145
139/* 146/*
140 * cpu_sa110_set_pte(ptep, pte) 147 * cpu_sa110_set_pte(ptep, pte)
@@ -143,6 +150,7 @@ ENTRY(cpu_sa110_switch_mm)
143 */ 150 */
144 .align 5 151 .align 5
145ENTRY(cpu_sa110_set_pte) 152ENTRY(cpu_sa110_set_pte)
153#ifdef CONFIG_MMU
146 str r1, [r0], #-2048 @ linux version 154 str r1, [r0], #-2048 @ linux version
147 155
148 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY 156 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
@@ -164,6 +172,7 @@ ENTRY(cpu_sa110_set_pte)
164 mov r0, r0 172 mov r0, r0
165 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 173 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
166 mcr p15, 0, r0, c7, c10, 4 @ drain WB 174 mcr p15, 0, r0, c7, c10, 4 @ drain WB
175#endif
167 mov pc, lr 176 mov pc, lr
168 177
169 __INIT 178 __INIT
@@ -173,7 +182,9 @@ __sa110_setup:
173 mov r10, #0 182 mov r10, #0
174 mcr p15, 0, r10, c7, c7 @ invalidate I,D caches on v4 183 mcr p15, 0, r10, c7, c7 @ invalidate I,D caches on v4
175 mcr p15, 0, r10, c7, c10, 4 @ drain write buffer on v4 184 mcr p15, 0, r10, c7, c10, 4 @ drain write buffer on v4
185#ifdef CONFIG_MMU
176 mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4 186 mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4
187#endif
177 mrc p15, 0, r0, c1, c0 @ get control register v4 188 mrc p15, 0, r0, c1, c0 @ get control register v4
178 ldr r5, sa110_cr1_clear 189 ldr r5, sa110_cr1_clear
179 bic r0, r0, r5 190 bic r0, r0, r5
diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S
index 777ad99c1439..0a2107ad4c32 100644
--- a/arch/arm/mm/proc-sa1100.S
+++ b/arch/arm/mm/proc-sa1100.S
@@ -2,6 +2,7 @@
2 * linux/arch/arm/mm/proc-sa1100.S 2 * linux/arch/arm/mm/proc-sa1100.S
3 * 3 *
4 * Copyright (C) 1997-2002 Russell King 4 * Copyright (C) 1997-2002 Russell King
5 * hacked for non-paged-MM by Hyok S. Choi, 2003.
5 * 6 *
6 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 8 * it under the terms of the GNU General Public License version 2 as
@@ -77,7 +78,9 @@ ENTRY(cpu_sa1100_reset)
77 mov ip, #0 78 mov ip, #0
78 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 79 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
79 mcr p15, 0, ip, c7, c10, 4 @ drain WB 80 mcr p15, 0, ip, c7, c10, 4 @ drain WB
81#ifdef CONFIG_MMU
80 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 82 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
83#endif
81 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 84 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
82 bic ip, ip, #0x000f @ ............wcam 85 bic ip, ip, #0x000f @ ............wcam
83 bic ip, ip, #0x1100 @ ...i...s........ 86 bic ip, ip, #0x1100 @ ...i...s........
@@ -142,12 +145,16 @@ ENTRY(cpu_sa1100_dcache_clean_area)
142 */ 145 */
143 .align 5 146 .align 5
144ENTRY(cpu_sa1100_switch_mm) 147ENTRY(cpu_sa1100_switch_mm)
148#ifdef CONFIG_MMU
145 str lr, [sp, #-4]! 149 str lr, [sp, #-4]!
146 bl v4wb_flush_kern_cache_all @ clears IP 150 bl v4wb_flush_kern_cache_all @ clears IP
147 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB 151 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB
148 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 152 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
149 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 153 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
150 ldr pc, [sp], #4 154 ldr pc, [sp], #4
155#else
156 mov pc, lr
157#endif
151 158
152/* 159/*
153 * cpu_sa1100_set_pte(ptep, pte) 160 * cpu_sa1100_set_pte(ptep, pte)
@@ -156,6 +163,7 @@ ENTRY(cpu_sa1100_switch_mm)
156 */ 163 */
157 .align 5 164 .align 5
158ENTRY(cpu_sa1100_set_pte) 165ENTRY(cpu_sa1100_set_pte)
166#ifdef CONFIG_MMU
159 str r1, [r0], #-2048 @ linux version 167 str r1, [r0], #-2048 @ linux version
160 168
161 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY 169 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
@@ -177,6 +185,7 @@ ENTRY(cpu_sa1100_set_pte)
177 mov r0, r0 185 mov r0, r0
178 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 186 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
179 mcr p15, 0, r0, c7, c10, 4 @ drain WB 187 mcr p15, 0, r0, c7, c10, 4 @ drain WB
188#endif
180 mov pc, lr 189 mov pc, lr
181 190
182 __INIT 191 __INIT
@@ -186,7 +195,9 @@ __sa1100_setup:
186 mov r0, #0 195 mov r0, #0
187 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 196 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
188 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 197 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
198#ifdef CONFIG_MMU
189 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 199 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
200#endif
190 mrc p15, 0, r0, c1, c0 @ get control register v4 201 mrc p15, 0, r0, c1, c0 @ get control register v4
191 ldr r5, sa1100_cr1_clear 202 ldr r5, sa1100_cr1_clear
192 bic r0, r0, r5 203 bic r0, r0, r5
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 09b1a41a6de8..ca13d4d05f65 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -2,6 +2,7 @@
2 * linux/arch/arm/mm/proc-v6.S 2 * linux/arch/arm/mm/proc-v6.S
3 * 3 *
4 * Copyright (C) 2001 Deep Blue Solutions Ltd. 4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
5 * Modified by Catalin Marinas for noMMU support
5 * 6 *
6 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 8 * it under the terms of the GNU General Public License version 2 as
@@ -88,6 +89,7 @@ ENTRY(cpu_v6_dcache_clean_area)
88 * - we are not using split page tables 89 * - we are not using split page tables
89 */ 90 */
90ENTRY(cpu_v6_switch_mm) 91ENTRY(cpu_v6_switch_mm)
92#ifdef CONFIG_MMU
91 mov r2, #0 93 mov r2, #0
92 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id 94 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
93#ifdef CONFIG_SMP 95#ifdef CONFIG_SMP
@@ -97,6 +99,7 @@ ENTRY(cpu_v6_switch_mm)
97 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer 99 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
98 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 100 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
99 mcr p15, 0, r1, c13, c0, 1 @ set context ID 101 mcr p15, 0, r1, c13, c0, 1 @ set context ID
102#endif
100 mov pc, lr 103 mov pc, lr
101 104
102/* 105/*
@@ -119,6 +122,7 @@ ENTRY(cpu_v6_switch_mm)
119 * 1111 0 1 1 r/w r/w 122 * 1111 0 1 1 r/w r/w
120 */ 123 */
121ENTRY(cpu_v6_set_pte) 124ENTRY(cpu_v6_set_pte)
125#ifdef CONFIG_MMU
122 str r1, [r0], #-2048 @ linux version 126 str r1, [r0], #-2048 @ linux version
123 127
124 bic r2, r1, #0x000003f0 128 bic r2, r1, #0x000003f0
@@ -145,6 +149,7 @@ ENTRY(cpu_v6_set_pte)
145 149
146 str r2, [r0] 150 str r2, [r0]
147 mcr p15, 0, r0, c7, c10, 1 @ flush_pte 151 mcr p15, 0, r0, c7, c10, 1 @ flush_pte
152#endif
148 mov pc, lr 153 mov pc, lr
149 154
150 155
@@ -194,12 +199,14 @@ __v6_setup:
194 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 199 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
195 mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache 200 mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache
196 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 201 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
202#ifdef CONFIG_MMU
197 mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs 203 mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs
198 mcr p15, 0, r0, c2, c0, 2 @ TTB control register 204 mcr p15, 0, r0, c2, c0, 2 @ TTB control register
199#ifdef CONFIG_SMP 205#ifdef CONFIG_SMP
200 orr r4, r4, #TTB_RGN_WBWA|TTB_S @ mark PTWs shared, outer cacheable 206 orr r4, r4, #TTB_RGN_WBWA|TTB_S @ mark PTWs shared, outer cacheable
201#endif 207#endif
202 mcr p15, 0, r4, c2, c0, 1 @ load TTB1 208 mcr p15, 0, r4, c2, c0, 1 @ load TTB1
209#endif /* CONFIG_MMU */
203#ifdef CONFIG_VFP 210#ifdef CONFIG_VFP
204 mrc p15, 0, r0, c1, c0, 2 211 mrc p15, 0, r0, c1, c0, 2
205 orr r0, r0, #(0xf << 20) 212 orr r0, r0, #(0xf << 20)
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-24 05:23:37 -0400