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authorJesper Nilsson <jespern@stork.se.axis.com>2007-11-29 11:03:41 -0500
committerJesper Nilsson <jesper.nilsson@axis.com>2008-02-08 05:06:22 -0500
commit18a1e013cdd94d1ade2c07acdbac61d533c7fc60 (patch)
tree8c393918dc41ac3aea6c46e2c61de2ec4574fb21 /arch
parent923dd2a46349bb1bb94aa894b7ff61093618d68a (diff)
CRIS v32: Add new driver files for Artpec-3.
Adds gpio and nandflash handling for Artpec-3.
Diffstat (limited to 'arch')
-rw-r--r--arch/cris/arch-v32/drivers/mach-a3/Makefile6
-rw-r--r--arch/cris/arch-v32/drivers/mach-a3/gpio.c984
-rw-r--r--arch/cris/arch-v32/drivers/mach-a3/nandflash.c178
3 files changed, 1168 insertions, 0 deletions
diff --git a/arch/cris/arch-v32/drivers/mach-a3/Makefile b/arch/cris/arch-v32/drivers/mach-a3/Makefile
new file mode 100644
index 000000000000..5c6d2a2a080e
--- /dev/null
+++ b/arch/cris/arch-v32/drivers/mach-a3/Makefile
@@ -0,0 +1,6 @@
1#
2# Makefile for Etrax-specific drivers
3#
4
5obj-$(CONFIG_ETRAX_NANDFLASH) += nandflash.o
6obj-$(CONFIG_ETRAX_GPIO) += gpio.o
diff --git a/arch/cris/arch-v32/drivers/mach-a3/gpio.c b/arch/cris/arch-v32/drivers/mach-a3/gpio.c
new file mode 100644
index 000000000000..4c48065ce78a
--- /dev/null
+++ b/arch/cris/arch-v32/drivers/mach-a3/gpio.c
@@ -0,0 +1,984 @@
1/*
2 * Artec-3 general port I/O device
3 *
4 * Copyright (c) 2007 Axis Communications AB
5 *
6 * Authors: Bjorn Wesen (initial version)
7 * Ola Knutsson (LED handling)
8 * Johan Adolfsson (read/set directions, write, port G,
9 * port to ETRAX FS.
10 * Ricard Wanderlof (PWM for Artpec-3)
11 *
12 */
13
14#include <linux/module.h>
15#include <linux/sched.h>
16#include <linux/slab.h>
17#include <linux/ioport.h>
18#include <linux/errno.h>
19#include <linux/kernel.h>
20#include <linux/fs.h>
21#include <linux/string.h>
22#include <linux/poll.h>
23#include <linux/init.h>
24#include <linux/interrupt.h>
25#include <linux/spinlock.h>
26
27#include <asm/etraxgpio.h>
28#include <hwregs/reg_map.h>
29#include <hwregs/reg_rdwr.h>
30#include <hwregs/gio_defs.h>
31#include <hwregs/intr_vect_defs.h>
32#include <asm/io.h>
33#include <asm/system.h>
34#include <asm/irq.h>
35#include <asm/arch/mach/pinmux.h>
36
37#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
38#include "../i2c.h"
39
40#define VIRT_I2C_ADDR 0x40
41#endif
42
43/* The following gio ports on ARTPEC-3 is available:
44 * pa 32 bits
45 * pb 32 bits
46 * pc 16 bits
47 * each port has a rw_px_dout, r_px_din and rw_px_oe register.
48 */
49
50#define GPIO_MAJOR 120 /* experimental MAJOR number */
51
52#define I2C_INTERRUPT_BITS 0x300 /* i2c0_done and i2c1_done bits */
53
54#define D(x)
55
56#if 0
57static int dp_cnt;
58#define DP(x) \
59 do { \
60 dp_cnt++; \
61 if (dp_cnt % 1000 == 0) \
62 x; \
63 } while (0)
64#else
65#define DP(x)
66#endif
67
68static char gpio_name[] = "etrax gpio";
69
70#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
71static int virtual_gpio_ioctl(struct file *file, unsigned int cmd,
72 unsigned long arg);
73#endif
74static int gpio_ioctl(struct inode *inode, struct file *file,
75 unsigned int cmd, unsigned long arg);
76static ssize_t gpio_write(struct file *file, const char *buf, size_t count,
77 loff_t *off);
78static int gpio_open(struct inode *inode, struct file *filp);
79static int gpio_release(struct inode *inode, struct file *filp);
80static unsigned int gpio_poll(struct file *filp,
81 struct poll_table_struct *wait);
82
83/* private data per open() of this driver */
84
85struct gpio_private {
86 struct gpio_private *next;
87 /* The IO_CFG_WRITE_MODE_VALUE only support 8 bits: */
88 unsigned char clk_mask;
89 unsigned char data_mask;
90 unsigned char write_msb;
91 unsigned char pad1;
92 /* These fields are generic */
93 unsigned long highalarm, lowalarm;
94 wait_queue_head_t alarm_wq;
95 int minor;
96};
97
98static void gpio_set_alarm(struct gpio_private *priv);
99
100/* linked list of alarms to check for */
101
102static struct gpio_private *alarmlist;
103
104static int wanted_interrupts;
105
106static DEFINE_SPINLOCK(alarm_lock);
107
108#define NUM_PORTS (GPIO_MINOR_LAST+1)
109#define GIO_REG_RD_ADDR(reg) \
110 (volatile unsigned long *)(regi_gio + REG_RD_ADDR_gio_##reg)
111#define GIO_REG_WR_ADDR(reg) \
112 (volatile unsigned long *)(regi_gio + REG_WR_ADDR_gio_##reg)
113unsigned long led_dummy;
114unsigned long port_d_dummy; /* Only input on Artpec-3 */
115unsigned long port_e_dummy; /* Non existent on Artpec-3 */
116#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
117static unsigned long virtual_dummy;
118static unsigned long virtual_rw_pv_oe = CONFIG_ETRAX_DEF_GIO_PV_OE;
119static unsigned short cached_virtual_gpio_read;
120#endif
121
122static volatile unsigned long *data_out[NUM_PORTS] = {
123 GIO_REG_WR_ADDR(rw_pa_dout),
124 GIO_REG_WR_ADDR(rw_pb_dout),
125 &led_dummy,
126 GIO_REG_WR_ADDR(rw_pc_dout),
127 &port_d_dummy,
128#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
129 &port_e_dummy,
130 &virtual_dummy,
131#endif
132};
133
134static volatile unsigned long *data_in[NUM_PORTS] = {
135 GIO_REG_RD_ADDR(r_pa_din),
136 GIO_REG_RD_ADDR(r_pb_din),
137 &led_dummy,
138 GIO_REG_RD_ADDR(r_pc_din),
139 GIO_REG_RD_ADDR(r_pd_din),
140#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
141 &port_e_dummy,
142 &virtual_dummy,
143#endif
144};
145
146static unsigned long changeable_dir[NUM_PORTS] = {
147 CONFIG_ETRAX_PA_CHANGEABLE_DIR,
148 CONFIG_ETRAX_PB_CHANGEABLE_DIR,
149 0,
150 CONFIG_ETRAX_PC_CHANGEABLE_DIR,
151 0,
152#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
153 0,
154 CONFIG_ETRAX_PV_CHANGEABLE_DIR,
155#endif
156};
157
158static unsigned long changeable_bits[NUM_PORTS] = {
159 CONFIG_ETRAX_PA_CHANGEABLE_BITS,
160 CONFIG_ETRAX_PB_CHANGEABLE_BITS,
161 0,
162 CONFIG_ETRAX_PC_CHANGEABLE_BITS,
163 0,
164#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
165 0,
166 CONFIG_ETRAX_PV_CHANGEABLE_BITS,
167#endif
168};
169
170static volatile unsigned long *dir_oe[NUM_PORTS] = {
171 GIO_REG_WR_ADDR(rw_pa_oe),
172 GIO_REG_WR_ADDR(rw_pb_oe),
173 &led_dummy,
174 GIO_REG_WR_ADDR(rw_pc_oe),
175 &port_d_dummy,
176#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
177 &port_e_dummy,
178 &virtual_rw_pv_oe,
179#endif
180};
181
182static void
183gpio_set_alarm(struct gpio_private *priv)
184{
185 int bit;
186 int intr_cfg;
187 int mask;
188 int pins;
189 unsigned long flags;
190
191 local_irq_save(flags);
192 intr_cfg = REG_RD_INT(gio, regi_gio, rw_intr_cfg);
193 pins = REG_RD_INT(gio, regi_gio, rw_intr_pins);
194 mask = REG_RD_INT(gio, regi_gio, rw_intr_mask) & I2C_INTERRUPT_BITS;
195
196 for (bit = 0; bit < 32; bit++) {
197 int intr = bit % 8;
198 int pin = bit / 8;
199 if (priv->minor < GPIO_MINOR_LEDS)
200 pin += priv->minor * 4;
201 else
202 pin += (priv->minor - 1) * 4;
203
204 if (priv->highalarm & (1<<bit)) {
205 intr_cfg |= (regk_gio_hi << (intr * 3));
206 mask |= 1 << intr;
207 wanted_interrupts = mask & 0xff;
208 pins |= pin << (intr * 4);
209 } else if (priv->lowalarm & (1<<bit)) {
210 intr_cfg |= (regk_gio_lo << (intr * 3));
211 mask |= 1 << intr;
212 wanted_interrupts = mask & 0xff;
213 pins |= pin << (intr * 4);
214 }
215 }
216
217 REG_WR_INT(gio, regi_gio, rw_intr_cfg, intr_cfg);
218 REG_WR_INT(gio, regi_gio, rw_intr_pins, pins);
219 REG_WR_INT(gio, regi_gio, rw_intr_mask, mask);
220
221 local_irq_restore(flags);
222}
223
224static unsigned int
225gpio_poll(struct file *file, struct poll_table_struct *wait)
226{
227 unsigned int mask = 0;
228 struct gpio_private *priv = (struct gpio_private *)file->private_data;
229 unsigned long data;
230 unsigned long tmp;
231
232 if (priv->minor >= GPIO_MINOR_PWM0 &&
233 priv->minor <= GPIO_MINOR_LAST_PWM)
234 return 0;
235
236 poll_wait(file, &priv->alarm_wq, wait);
237 if (priv->minor <= GPIO_MINOR_D) {
238 data = *data_in[priv->minor];
239 REG_WR_INT(gio, regi_gio, rw_ack_intr, wanted_interrupts);
240 tmp = REG_RD_INT(gio, regi_gio, rw_intr_mask);
241 tmp &= I2C_INTERRUPT_BITS;
242 tmp |= wanted_interrupts;
243 REG_WR_INT(gio, regi_gio, rw_intr_mask, tmp);
244 } else
245 return 0;
246
247 if ((data & priv->highalarm) || (~data & priv->lowalarm))
248 mask = POLLIN|POLLRDNORM;
249
250 DP(printk(KERN_DEBUG "gpio_poll ready: mask 0x%08X\n", mask));
251 return mask;
252}
253
254static irqreturn_t
255gpio_interrupt(int irq, void *dev_id)
256{
257 reg_gio_rw_intr_mask intr_mask;
258 reg_gio_r_masked_intr masked_intr;
259 reg_gio_rw_ack_intr ack_intr;
260 unsigned long tmp;
261 unsigned long tmp2;
262#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
263 unsigned char enable_gpiov_ack = 0;
264#endif
265
266 /* Find what PA interrupts are active */
267 masked_intr = REG_RD(gio, regi_gio, r_masked_intr);
268 tmp = REG_TYPE_CONV(unsigned long, reg_gio_r_masked_intr, masked_intr);
269
270 /* Find those that we have enabled */
271 spin_lock(&alarm_lock);
272 tmp &= wanted_interrupts;
273 spin_unlock(&alarm_lock);
274
275#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
276 /* Something changed on virtual GPIO. Interrupt is acked by
277 * reading the device.
278 */
279 if (tmp & (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN)) {
280 i2c_read(VIRT_I2C_ADDR, (void *)&cached_virtual_gpio_read,
281 sizeof(cached_virtual_gpio_read));
282 enable_gpiov_ack = 1;
283 }
284#endif
285
286 /* Ack them */
287 ack_intr = REG_TYPE_CONV(reg_gio_rw_ack_intr, unsigned long, tmp);
288 REG_WR(gio, regi_gio, rw_ack_intr, ack_intr);
289
290 /* Disable those interrupts.. */
291 intr_mask = REG_RD(gio, regi_gio, rw_intr_mask);
292 tmp2 = REG_TYPE_CONV(unsigned long, reg_gio_rw_intr_mask, intr_mask);
293 tmp2 &= ~tmp;
294#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
295 /* Do not disable interrupt on virtual GPIO. Changes on virtual
296 * pins are only noticed by an interrupt.
297 */
298 if (enable_gpiov_ack)
299 tmp2 |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN);
300#endif
301 intr_mask = REG_TYPE_CONV(reg_gio_rw_intr_mask, unsigned long, tmp2);
302 REG_WR(gio, regi_gio, rw_intr_mask, intr_mask);
303
304 return IRQ_RETVAL(tmp);
305}
306
307
308static ssize_t gpio_write(struct file *file, const char *buf, size_t count,
309 loff_t *off)
310{
311 struct gpio_private *priv = (struct gpio_private *)file->private_data;
312 unsigned char data, clk_mask, data_mask, write_msb;
313 unsigned long flags;
314 unsigned long shadow;
315 volatile unsigned long *port;
316 ssize_t retval = count;
317 /* Only bits 0-7 may be used for write operations but allow all
318 devices except leds... */
319#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
320 if (priv->minor == GPIO_MINOR_V)
321 return -EFAULT;
322#endif
323 if (priv->minor == GPIO_MINOR_LEDS)
324 return -EFAULT;
325
326 if (priv->minor >= GPIO_MINOR_PWM0 &&
327 priv->minor <= GPIO_MINOR_LAST_PWM)
328 return -EFAULT;
329
330 if (!access_ok(VERIFY_READ, buf, count))
331 return -EFAULT;
332
333 clk_mask = priv->clk_mask;
334 data_mask = priv->data_mask;
335 /* It must have been configured using the IO_CFG_WRITE_MODE */
336 /* Perhaps a better error code? */
337 if (clk_mask == 0 || data_mask == 0)
338 return -EPERM;
339
340 write_msb = priv->write_msb;
341 D(printk(KERN_DEBUG "gpio_write: %lu to data 0x%02X clk 0x%02X "
342 "msb: %i\n",
343 count, data_mask, clk_mask, write_msb));
344 port = data_out[priv->minor];
345
346 while (count--) {
347 int i;
348 data = *buf++;
349 if (priv->write_msb) {
350 for (i = 7; i >= 0; i--) {
351 local_irq_save(flags);
352 shadow = *port;
353 *port = shadow &= ~clk_mask;
354 if (data & 1<<i)
355 *port = shadow |= data_mask;
356 else
357 *port = shadow &= ~data_mask;
358 /* For FPGA: min 5.0ns (DCC) before CCLK high */
359 *port = shadow |= clk_mask;
360 local_irq_restore(flags);
361 }
362 } else {
363 for (i = 0; i <= 7; i++) {
364 local_irq_save(flags);
365 shadow = *port;
366 *port = shadow &= ~clk_mask;
367 if (data & 1<<i)
368 *port = shadow |= data_mask;
369 else
370 *port = shadow &= ~data_mask;
371 /* For FPGA: min 5.0ns (DCC) before CCLK high */
372 *port = shadow |= clk_mask;
373 local_irq_restore(flags);
374 }
375 }
376 }
377 return retval;
378}
379
380static int
381gpio_open(struct inode *inode, struct file *filp)
382{
383 struct gpio_private *priv;
384 int p = iminor(inode);
385
386 if (p > GPIO_MINOR_LAST_PWM ||
387 (p > GPIO_MINOR_LAST && p < GPIO_MINOR_PWM0))
388 return -EINVAL;
389
390 priv = kmalloc(sizeof(struct gpio_private), GFP_KERNEL);
391
392 if (!priv)
393 return -ENOMEM;
394 memset(priv, 0, sizeof(*priv));
395
396 priv->minor = p;
397 filp->private_data = (void *)priv;
398
399 /* initialize the io/alarm struct, not for PWM ports though */
400 if (p <= GPIO_MINOR_LAST) {
401
402 priv->clk_mask = 0;
403 priv->data_mask = 0;
404 priv->highalarm = 0;
405 priv->lowalarm = 0;
406
407 init_waitqueue_head(&priv->alarm_wq);
408
409 /* link it into our alarmlist */
410 spin_lock_irq(&alarm_lock);
411 priv->next = alarmlist;
412 alarmlist = priv;
413 spin_unlock_irq(&alarm_lock);
414 }
415
416 return 0;
417}
418
419static int
420gpio_release(struct inode *inode, struct file *filp)
421{
422 struct gpio_private *p;
423 struct gpio_private *todel;
424 /* local copies while updating them: */
425 unsigned long a_high, a_low;
426
427 /* prepare to free private structure */
428 todel = (struct gpio_private *)filp->private_data;
429
430 /* unlink from alarmlist - only for non-PWM ports though */
431 if (todel->minor <= GPIO_MINOR_LAST) {
432 spin_lock_irq(&alarm_lock);
433 p = alarmlist;
434
435 if (p == todel)
436 alarmlist = todel->next;
437 else {
438 while (p->next != todel)
439 p = p->next;
440 p->next = todel->next;
441 }
442
443 /* Check if there are still any alarms set */
444 p = alarmlist;
445 a_high = 0;
446 a_low = 0;
447 while (p) {
448 if (p->minor == GPIO_MINOR_A) {
449#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
450 p->lowalarm |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN);
451#endif
452 a_high |= p->highalarm;
453 a_low |= p->lowalarm;
454 }
455
456 p = p->next;
457 }
458
459#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
460 /* Variable 'a_low' needs to be set here again
461 * to ensure that interrupt for virtual GPIO is handled.
462 */
463 a_low |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN);
464#endif
465
466 spin_unlock_irq(&alarm_lock);
467 }
468 kfree(todel);
469
470 return 0;
471}
472
473/* Main device API. ioctl's to read/set/clear bits, as well as to
474 * set alarms to wait for using a subsequent select().
475 */
476
477inline unsigned long setget_input(struct gpio_private *priv, unsigned long arg)
478{
479 /* Set direction 0=unchanged 1=input,
480 * return mask with 1=input
481 */
482 unsigned long flags;
483 unsigned long dir_shadow;
484
485 local_irq_save(flags);
486 dir_shadow = *dir_oe[priv->minor];
487 dir_shadow &= ~(arg & changeable_dir[priv->minor]);
488 *dir_oe[priv->minor] = dir_shadow;
489 local_irq_restore(flags);
490
491 if (priv->minor == GPIO_MINOR_C)
492 dir_shadow ^= 0xFFFF; /* Only 16 bits */
493#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
494 else if (priv->minor == GPIO_MINOR_V)
495 dir_shadow ^= 0xFFFF; /* Only 16 bits */
496#endif
497 else
498 dir_shadow ^= 0xFFFFFFFF; /* PA, PB and PD 32 bits */
499
500 return dir_shadow;
501
502} /* setget_input */
503
504inline unsigned long setget_output(struct gpio_private *priv, unsigned long arg)
505{
506 unsigned long flags;
507 unsigned long dir_shadow;
508
509 local_irq_save(flags);
510 dir_shadow = *dir_oe[priv->minor];
511 dir_shadow |= (arg & changeable_dir[priv->minor]);
512 *dir_oe[priv->minor] = dir_shadow;
513 local_irq_restore(flags);
514 return dir_shadow;
515} /* setget_output */
516
517static int
518gpio_leds_ioctl(unsigned int cmd, unsigned long arg);
519
520static int
521gpio_pwm_ioctl(struct gpio_private *priv, unsigned int cmd, unsigned long arg);
522
523static int
524gpio_ioctl(struct inode *inode, struct file *file,
525 unsigned int cmd, unsigned long arg)
526{
527 unsigned long flags;
528 unsigned long val;
529 unsigned long shadow;
530 struct gpio_private *priv = (struct gpio_private *)file->private_data;
531
532 if (_IOC_TYPE(cmd) != ETRAXGPIO_IOCTYPE)
533 return -EINVAL;
534
535 /* Check for special ioctl handlers first */
536
537#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
538 if (priv->minor == GPIO_MINOR_V)
539 return virtual_gpio_ioctl(file, cmd, arg);
540#endif
541
542 if (priv->minor == GPIO_MINOR_LEDS)
543 return gpio_leds_ioctl(cmd, arg);
544
545 if (priv->minor >= GPIO_MINOR_PWM0 &&
546 priv->minor <= GPIO_MINOR_LAST_PWM)
547 return gpio_pwm_ioctl(priv, cmd, arg);
548
549 switch (_IOC_NR(cmd)) {
550 case IO_READBITS: /* Use IO_READ_INBITS and IO_READ_OUTBITS instead */
551 /* Read the port. */
552 return *data_in[priv->minor];
553 break;
554 case IO_SETBITS:
555 local_irq_save(flags);
556 /* Set changeable bits with a 1 in arg. */
557 shadow = *data_out[priv->minor];
558 shadow |= (arg & changeable_bits[priv->minor]);
559 *data_out[priv->minor] = shadow;
560 local_irq_restore(flags);
561 break;
562 case IO_CLRBITS:
563 local_irq_save(flags);
564 /* Clear changeable bits with a 1 in arg. */
565 shadow = *data_out[priv->minor];
566 shadow &= ~(arg & changeable_bits[priv->minor]);
567 *data_out[priv->minor] = shadow;
568 local_irq_restore(flags);
569 break;
570 case IO_HIGHALARM:
571 /* Set alarm when bits with 1 in arg go high. */
572 priv->highalarm |= arg;
573 gpio_set_alarm(priv);
574 break;
575 case IO_LOWALARM:
576 /* Set alarm when bits with 1 in arg go low. */
577 priv->lowalarm |= arg;
578 gpio_set_alarm(priv);
579 break;
580 case IO_CLRALARM:
581 /* Clear alarm for bits with 1 in arg. */
582 priv->highalarm &= ~arg;
583 priv->lowalarm &= ~arg;
584 gpio_set_alarm(priv);
585 break;
586 case IO_READDIR: /* Use IO_SETGET_INPUT/OUTPUT instead! */
587 /* Read direction 0=input 1=output */
588 return *dir_oe[priv->minor];
589 case IO_SETINPUT: /* Use IO_SETGET_INPUT instead! */
590 /* Set direction 0=unchanged 1=input,
591 * return mask with 1=input
592 */
593 return setget_input(priv, arg);
594 break;
595 case IO_SETOUTPUT: /* Use IO_SETGET_OUTPUT instead! */
596 /* Set direction 0=unchanged 1=output,
597 * return mask with 1=output
598 */
599 return setget_output(priv, arg);
600
601 case IO_CFG_WRITE_MODE:
602 {
603 unsigned long dir_shadow;
604 dir_shadow = *dir_oe[priv->minor];
605
606 priv->clk_mask = arg & 0xFF;
607 priv->data_mask = (arg >> 8) & 0xFF;
608 priv->write_msb = (arg >> 16) & 0x01;
609 /* Check if we're allowed to change the bits and
610 * the direction is correct
611 */
612 if (!((priv->clk_mask & changeable_bits[priv->minor]) &&
613 (priv->data_mask & changeable_bits[priv->minor]) &&
614 (priv->clk_mask & dir_shadow) &&
615 (priv->data_mask & dir_shadow))) {
616 priv->clk_mask = 0;
617 priv->data_mask = 0;
618 return -EPERM;
619 }
620 break;
621 }
622 case IO_READ_INBITS:
623 /* *arg is result of reading the input pins */
624 val = *data_in[priv->minor];
625 if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
626 return -EFAULT;
627 return 0;
628 break;
629 case IO_READ_OUTBITS:
630 /* *arg is result of reading the output shadow */
631 val = *data_out[priv->minor];
632 if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
633 return -EFAULT;
634 break;
635 case IO_SETGET_INPUT:
636 /* bits set in *arg is set to input,
637 * *arg updated with current input pins.
638 */
639 if (copy_from_user(&val, (unsigned long *)arg, sizeof(val)))
640 return -EFAULT;
641 val = setget_input(priv, val);
642 if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
643 return -EFAULT;
644 break;
645 case IO_SETGET_OUTPUT:
646 /* bits set in *arg is set to output,
647 * *arg updated with current output pins.
648 */
649 if (copy_from_user(&val, (unsigned long *)arg, sizeof(val)))
650 return -EFAULT;
651 val = setget_output(priv, val);
652 if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
653 return -EFAULT;
654 break;
655 default:
656 return -EINVAL;
657 } /* switch */
658
659 return 0;
660}
661
662#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
663static int
664virtual_gpio_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
665{
666 unsigned long flags;
667 unsigned short val;
668 unsigned short shadow;
669 struct gpio_private *priv = (struct gpio_private *)file->private_data;
670
671 switch (_IOC_NR(cmd)) {
672 case IO_SETBITS:
673 local_irq_save(flags);
674 /* Set changeable bits with a 1 in arg. */
675 i2c_read(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
676 shadow |= ~*dir_oe[priv->minor];
677 shadow |= (arg & changeable_bits[priv->minor]);
678 i2c_write(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
679 local_irq_restore(flags);
680 break;
681 case IO_CLRBITS:
682 local_irq_save(flags);
683 /* Clear changeable bits with a 1 in arg. */
684 i2c_read(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
685 shadow |= ~*dir_oe[priv->minor];
686 shadow &= ~(arg & changeable_bits[priv->minor]);
687 i2c_write(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
688 local_irq_restore(flags);
689 break;
690 case IO_HIGHALARM:
691 /* Set alarm when bits with 1 in arg go high. */
692 priv->highalarm |= arg;
693 break;
694 case IO_LOWALARM:
695 /* Set alarm when bits with 1 in arg go low. */
696 priv->lowalarm |= arg;
697 break;
698 case IO_CLRALARM:
699 /* Clear alarm for bits with 1 in arg. */
700 priv->highalarm &= ~arg;
701 priv->lowalarm &= ~arg;
702 break;
703 case IO_CFG_WRITE_MODE:
704 {
705 unsigned long dir_shadow;
706 dir_shadow = *dir_oe[priv->minor];
707
708 priv->clk_mask = arg & 0xFF;
709 priv->data_mask = (arg >> 8) & 0xFF;
710 priv->write_msb = (arg >> 16) & 0x01;
711 /* Check if we're allowed to change the bits and
712 * the direction is correct
713 */
714 if (!((priv->clk_mask & changeable_bits[priv->minor]) &&
715 (priv->data_mask & changeable_bits[priv->minor]) &&
716 (priv->clk_mask & dir_shadow) &&
717 (priv->data_mask & dir_shadow))) {
718 priv->clk_mask = 0;
719 priv->data_mask = 0;
720 return -EPERM;
721 }
722 break;
723 }
724 case IO_READ_INBITS:
725 /* *arg is result of reading the input pins */
726 val = cached_virtual_gpio_read;
727 val &= ~*dir_oe[priv->minor];
728 if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
729 return -EFAULT;
730 return 0;
731 break;
732 case IO_READ_OUTBITS:
733 /* *arg is result of reading the output shadow */
734 i2c_read(VIRT_I2C_ADDR, (void *)&val, sizeof(val));
735 val &= *dir_oe[priv->minor];
736 if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
737 return -EFAULT;
738 break;
739 case IO_SETGET_INPUT:
740 {
741 /* bits set in *arg is set to input,
742 * *arg updated with current input pins.
743 */
744 unsigned short input_mask = ~*dir_oe[priv->minor];
745 if (copy_from_user(&val, (unsigned long *)arg, sizeof(val)))
746 return -EFAULT;
747 val = setget_input(priv, val);
748 if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
749 return -EFAULT;
750 if ((input_mask & val) != input_mask) {
751 /* Input pins changed. All ports desired as input
752 * should be set to logic 1.
753 */
754 unsigned short change = input_mask ^ val;
755 i2c_read(VIRT_I2C_ADDR, (void *)&shadow,
756 sizeof(shadow));
757 shadow &= ~change;
758 shadow |= val;
759 i2c_write(VIRT_I2C_ADDR, (void *)&shadow,
760 sizeof(shadow));
761 }
762 break;
763 }
764 case IO_SETGET_OUTPUT:
765 /* bits set in *arg is set to output,
766 * *arg updated with current output pins.
767 */
768 if (copy_from_user(&val, (unsigned long *)arg, sizeof(val)))
769 return -EFAULT;
770 val = setget_output(priv, val);
771 if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
772 return -EFAULT;
773 break;
774 default:
775 return -EINVAL;
776 } /* switch */
777 return 0;
778}
779#endif /* CONFIG_ETRAX_VIRTUAL_GPIO */
780
781static int
782gpio_leds_ioctl(unsigned int cmd, unsigned long arg)
783{
784 unsigned char green;
785 unsigned char red;
786
787 switch (_IOC_NR(cmd)) {
788 case IO_LEDACTIVE_SET:
789 green = ((unsigned char) arg) & 1;
790 red = (((unsigned char) arg) >> 1) & 1;
791 LED_ACTIVE_SET_G(green);
792 LED_ACTIVE_SET_R(red);
793 break;
794
795 default:
796 return -EINVAL;
797 } /* switch */
798
799 return 0;
800}
801
802static int gpio_pwm_set_mode(unsigned long arg, int pwm_port)
803{
804 int pinmux_pwm = pinmux_pwm0 + pwm_port;
805 int mode;
806 reg_gio_rw_pwm0_ctrl rw_pwm_ctrl = {
807 .ccd_val = 0,
808 .ccd_override = regk_gio_no,
809 .mode = regk_gio_no
810 };
811 int allocstatus;
812
813 if (get_user(mode, &((struct io_pwm_set_mode *) arg)->mode))
814 return -EFAULT;
815 rw_pwm_ctrl.mode = mode;
816 if (mode != PWM_OFF)
817 allocstatus = crisv32_pinmux_alloc_fixed(pinmux_pwm);
818 else
819 allocstatus = crisv32_pinmux_dealloc_fixed(pinmux_pwm);
820 if (allocstatus)
821 return allocstatus;
822 REG_WRITE(reg_gio_rw_pwm0_ctrl, REG_ADDR(gio, regi_gio, rw_pwm0_ctrl) +
823 12 * pwm_port, rw_pwm_ctrl);
824 return 0;
825}
826
827static int gpio_pwm_set_period(unsigned long arg, int pwm_port)
828{
829 struct io_pwm_set_period periods;
830 reg_gio_rw_pwm0_var rw_pwm_widths;
831
832 if (copy_from_user(&periods, (struct io_pwm_set_period *) arg,
833 sizeof(periods)))
834 return -EFAULT;
835 if (periods.lo > 8191 || periods.hi > 8191)
836 return -EINVAL;
837 rw_pwm_widths.lo = periods.lo;
838 rw_pwm_widths.hi = periods.hi;
839 REG_WRITE(reg_gio_rw_pwm0_var, REG_ADDR(gio, regi_gio, rw_pwm0_var) +
840 12 * pwm_port, rw_pwm_widths);
841 return 0;
842}
843
844static int gpio_pwm_set_duty(unsigned long arg, int pwm_port)
845{
846 unsigned int duty;
847 reg_gio_rw_pwm0_data rw_pwm_duty;
848
849 if (get_user(duty, &((struct io_pwm_set_duty *) arg)->duty))
850 return -EFAULT;
851 if (duty > 255)
852 return -EINVAL;
853 rw_pwm_duty.data = duty;
854 REG_WRITE(reg_gio_rw_pwm0_data, REG_ADDR(gio, regi_gio, rw_pwm0_data) +
855 12 * pwm_port, rw_pwm_duty);
856 return 0;
857}
858
859static int
860gpio_pwm_ioctl(struct gpio_private *priv, unsigned int cmd, unsigned long arg)
861{
862 int pwm_port = priv->minor - GPIO_MINOR_PWM0;
863
864 switch (_IOC_NR(cmd)) {
865 case IO_PWM_SET_MODE:
866 return gpio_pwm_set_mode(arg, pwm_port);
867 case IO_PWM_SET_PERIOD:
868 return gpio_pwm_set_period(arg, pwm_port);
869 case IO_PWM_SET_DUTY:
870 return gpio_pwm_set_duty(arg, pwm_port);
871 default:
872 return -EINVAL;
873 }
874 return 0;
875}
876
877struct file_operations gpio_fops = {
878 .owner = THIS_MODULE,
879 .poll = gpio_poll,
880 .ioctl = gpio_ioctl,
881 .write = gpio_write,
882 .open = gpio_open,
883 .release = gpio_release,
884};
885
886#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
887static void
888virtual_gpio_init(void)
889{
890 reg_gio_rw_intr_cfg intr_cfg;
891 reg_gio_rw_intr_mask intr_mask;
892 unsigned short shadow;
893
894 shadow = ~virtual_rw_pv_oe; /* Input ports should be set to logic 1 */
895 shadow |= CONFIG_ETRAX_DEF_GIO_PV_OUT;
896 i2c_write(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
897
898 /* Set interrupt mask and on what state the interrupt shall trigger.
899 * For virtual gpio the interrupt shall trigger on logic '0'.
900 */
901 intr_cfg = REG_RD(gio, regi_gio, rw_intr_cfg);
902 intr_mask = REG_RD(gio, regi_gio, rw_intr_mask);
903
904 switch (CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN) {
905 case 0:
906 intr_cfg.pa0 = regk_gio_lo;
907 intr_mask.pa0 = regk_gio_yes;
908 break;
909 case 1:
910 intr_cfg.pa1 = regk_gio_lo;
911 intr_mask.pa1 = regk_gio_yes;
912 break;
913 case 2:
914 intr_cfg.pa2 = regk_gio_lo;
915 intr_mask.pa2 = regk_gio_yes;
916 break;
917 case 3:
918 intr_cfg.pa3 = regk_gio_lo;
919 intr_mask.pa3 = regk_gio_yes;
920 break;
921 case 4:
922 intr_cfg.pa4 = regk_gio_lo;
923 intr_mask.pa4 = regk_gio_yes;
924 break;
925 case 5:
926 intr_cfg.pa5 = regk_gio_lo;
927 intr_mask.pa5 = regk_gio_yes;
928 break;
929 case 6:
930 intr_cfg.pa6 = regk_gio_lo;
931 intr_mask.pa6 = regk_gio_yes;
932 break;
933 case 7:
934 intr_cfg.pa7 = regk_gio_lo;
935 intr_mask.pa7 = regk_gio_yes;
936 break;
937 }
938
939 REG_WR(gio, regi_gio, rw_intr_cfg, intr_cfg);
940 REG_WR(gio, regi_gio, rw_intr_mask, intr_mask);
941}
942#endif
943
944/* main driver initialization routine, called from mem.c */
945
946static __init int
947gpio_init(void)
948{
949 int res;
950
951 /* do the formalities */
952
953 res = register_chrdev(GPIO_MAJOR, gpio_name, &gpio_fops);
954 if (res < 0) {
955 printk(KERN_ERR "gpio: couldn't get a major number.\n");
956 return res;
957 }
958
959 /* Clear all leds */
960 LED_NETWORK_GRP0_SET(0);
961 LED_NETWORK_GRP1_SET(0);
962 LED_ACTIVE_SET(0);
963 LED_DISK_READ(0);
964 LED_DISK_WRITE(0);
965
966 printk(KERN_INFO "ETRAX FS GPIO driver v2.6, (c) 2003-2007 "
967 "Axis Communications AB\n");
968 if (request_irq(GIO_INTR_VECT, gpio_interrupt,
969 IRQF_SHARED | IRQF_DISABLED, "gpio", &alarmlist))
970 printk(KERN_ERR "err: irq for gpio\n");
971
972 /* No IRQs by default. */
973 REG_WR_INT(gio, regi_gio, rw_intr_pins, 0);
974
975#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
976 virtual_gpio_init();
977#endif
978
979 return res;
980}
981
982/* this makes sure that gpio_init is called during kernel boot */
983
984module_init(gpio_init);
diff --git a/arch/cris/arch-v32/drivers/mach-a3/nandflash.c b/arch/cris/arch-v32/drivers/mach-a3/nandflash.c
new file mode 100644
index 000000000000..2fda3db0249d
--- /dev/null
+++ b/arch/cris/arch-v32/drivers/mach-a3/nandflash.c
@@ -0,0 +1,178 @@
1/*
2 * arch/cris/arch-v32/drivers/nandflash.c
3 *
4 * Copyright (c) 2007
5 *
6 * Derived from drivers/mtd/nand/spia.c
7 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 */
14
15#include <linux/slab.h>
16#include <linux/init.h>
17#include <linux/module.h>
18#include <linux/mtd/mtd.h>
19#include <linux/mtd/nand.h>
20#include <linux/mtd/partitions.h>
21#include <asm/arch/memmap.h>
22#include <hwregs/reg_map.h>
23#include <hwregs/reg_rdwr.h>
24#include <hwregs/pio_defs.h>
25#include <pinmux.h>
26#include <asm/io.h>
27
28#define MANUAL_ALE_CLE_CONTROL 1
29
30#define regf_ALE a0
31#define regf_CLE a1
32#define regf_NCE ce0_n
33
34#define CLE_BIT 10
35#define ALE_BIT 11
36#define CE_BIT 12
37
38/* Bitmask for control pins */
39#define PIN_BITMASK ((1 << CE_BIT) | (1 << CLE_BIT) | (1 << ALE_BIT))
40
41static struct mtd_info *crisv32_mtd;
42/*
43 * hardware specific access to control-lines
44 */
45static void crisv32_hwcontrol(struct mtd_info *mtd, int cmd,
46 unsigned int ctrl)
47{
48 unsigned long flags;
49 reg_pio_rw_dout dout;
50 struct nand_chip *this = mtd->priv;
51
52 local_irq_save(flags);
53
54 /* control bits change */
55 if (ctrl & NAND_CTRL_CHANGE) {
56 dout = REG_RD(pio, regi_pio, rw_dout);
57 dout.regf_NCE = (ctrl & NAND_NCE) ? 0 : 1;
58
59#if !MANUAL_ALE_CLE_CONTROL
60 if (ctrl & NAND_ALE) {
61 /* A0 = ALE high */
62 this->IO_ADDR_W = (void __iomem *)REG_ADDR(pio,
63 regi_pio, rw_io_access1);
64 } else if (ctrl & NAND_CLE) {
65 /* A1 = CLE high */
66 this->IO_ADDR_W = (void __iomem *)REG_ADDR(pio,
67 regi_pio, rw_io_access2);
68 } else {
69 /* A1 = CLE and A0 = ALE low */
70 this->IO_ADDR_W = (void __iomem *)REG_ADDR(pio,
71 regi_pio, rw_io_access0);
72 }
73#else
74
75 dout.regf_CLE = (ctrl & NAND_CLE) ? 1 : 0;
76 dout.regf_ALE = (ctrl & NAND_ALE) ? 1 : 0;
77#endif
78 REG_WR(pio, regi_pio, rw_dout, dout);
79 }
80
81 /* command to chip */
82 if (cmd != NAND_CMD_NONE)
83 writeb(cmd, this->IO_ADDR_W);
84
85 local_irq_restore(flags);
86}
87
88/*
89* read device ready pin
90*/
91int crisv32_device_ready(struct mtd_info *mtd)
92{
93 reg_pio_r_din din = REG_RD(pio, regi_pio, r_din);
94 return din.rdy;
95}
96
97/*
98 * Main initialization routine
99 */
100struct mtd_info *__init crisv32_nand_flash_probe(void)
101{
102 void __iomem *read_cs;
103 void __iomem *write_cs;
104
105 struct nand_chip *this;
106 int err = 0;
107
108 reg_pio_rw_man_ctrl man_ctrl = {
109 .regf_NCE = regk_pio_yes,
110#if MANUAL_ALE_CLE_CONTROL
111 .regf_ALE = regk_pio_yes,
112 .regf_CLE = regk_pio_yes
113#endif
114 };
115 reg_pio_rw_oe oe = {
116 .regf_NCE = regk_pio_yes,
117#if MANUAL_ALE_CLE_CONTROL
118 .regf_ALE = regk_pio_yes,
119 .regf_CLE = regk_pio_yes
120#endif
121 };
122 reg_pio_rw_dout dout = { .regf_NCE = 1 };
123
124 /* Allocate pio pins to pio */
125 crisv32_pinmux_alloc_fixed(pinmux_pio);
126 /* Set up CE, ALE, CLE (ce0_n, a0, a1) for manual control and output */
127 REG_WR(pio, regi_pio, rw_man_ctrl, man_ctrl);
128 REG_WR(pio, regi_pio, rw_dout, dout);
129 REG_WR(pio, regi_pio, rw_oe, oe);
130
131 /* Allocate memory for MTD device structure and private data */
132 crisv32_mtd = kmalloc(sizeof(struct mtd_info) +
133 sizeof(struct nand_chip), GFP_KERNEL);
134 if (!crisv32_mtd) {
135 printk(KERN_ERR "Unable to allocate CRISv32 NAND MTD "
136 "device structure.\n");
137 err = -ENOMEM;
138 return NULL;
139 }
140
141 read_cs = write_cs = (void __iomem *)REG_ADDR(pio, regi_pio,
142 rw_io_access0);
143
144 /* Get pointer to private data */
145 this = (struct nand_chip *) (&crisv32_mtd[1]);
146
147 /* Initialize structures */
148 memset((char *) crisv32_mtd, 0, sizeof(struct mtd_info));
149 memset((char *) this, 0, sizeof(struct nand_chip));
150
151 /* Link the private data with the MTD structure */
152 crisv32_mtd->priv = this;
153
154 /* Set address of NAND IO lines */
155 this->IO_ADDR_R = read_cs;
156 this->IO_ADDR_W = write_cs;
157 this->cmd_ctrl = crisv32_hwcontrol;
158 this->dev_ready = crisv32_device_ready;
159 /* 20 us command delay time */
160 this->chip_delay = 20;
161 this->ecc.mode = NAND_ECC_SOFT;
162
163 /* Enable the following for a flash based bad block table */
164 /* this->options = NAND_USE_FLASH_BBT; */
165
166 /* Scan to find existance of the device */
167 if (nand_scan(crisv32_mtd, 1)) {
168 err = -ENXIO;
169 goto out_mtd;
170 }
171
172 return crisv32_mtd;
173
174out_mtd:
175 kfree(crisv32_mtd);
176 return NULL;
177}
178
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-28 01:31:13 -0400