diff options
author | Roland Stigge <stigge@antcom.de> | 2012-02-27 11:28:02 -0500 |
---|---|---|
committer | Roland Stigge <stigge@antcom.de> | 2012-02-27 11:28:02 -0500 |
commit | f6737055c1c432a9628a9a731f9881ad8e0a9eee (patch) | |
tree | d601200aac8c13adf74126157baa3bb55cd78180 /arch | |
parent | 6b21d18ed50c7d145220b0724ea7f2613abf0f95 (diff) |
ARM: LPC32xx: Fix irq on GPI_28
The GPI_28 IRQ was not registered properly. The registration of
IRQ_LPC32XX_GPI_28 was added and the (wrong) IRQ_LPC32XX_GPI_11 at
LPC32XX_SIC1_IRQ(4) was replaced by IRQ_LPC32XX_GPI_28 (see manual of
LPC32xx / interrupt controller).
Signed-off-by: Roland Stigge <stigge@antcom.de>
Cc: stable@vger.kernel.org
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/mach-lpc32xx/include/mach/irqs.h | 2 | ||||
-rw-r--r-- | arch/arm/mach-lpc32xx/irq.c | 4 |
2 files changed, 5 insertions, 1 deletions
diff --git a/arch/arm/mach-lpc32xx/include/mach/irqs.h b/arch/arm/mach-lpc32xx/include/mach/irqs.h index 2667f52e3b04..9e3b90df32e1 100644 --- a/arch/arm/mach-lpc32xx/include/mach/irqs.h +++ b/arch/arm/mach-lpc32xx/include/mach/irqs.h | |||
@@ -61,7 +61,7 @@ | |||
61 | */ | 61 | */ |
62 | #define IRQ_LPC32XX_JTAG_COMM_TX LPC32XX_SIC1_IRQ(1) | 62 | #define IRQ_LPC32XX_JTAG_COMM_TX LPC32XX_SIC1_IRQ(1) |
63 | #define IRQ_LPC32XX_JTAG_COMM_RX LPC32XX_SIC1_IRQ(2) | 63 | #define IRQ_LPC32XX_JTAG_COMM_RX LPC32XX_SIC1_IRQ(2) |
64 | #define IRQ_LPC32XX_GPI_11 LPC32XX_SIC1_IRQ(4) | 64 | #define IRQ_LPC32XX_GPI_28 LPC32XX_SIC1_IRQ(4) |
65 | #define IRQ_LPC32XX_TS_P LPC32XX_SIC1_IRQ(6) | 65 | #define IRQ_LPC32XX_TS_P LPC32XX_SIC1_IRQ(6) |
66 | #define IRQ_LPC32XX_TS_IRQ LPC32XX_SIC1_IRQ(7) | 66 | #define IRQ_LPC32XX_TS_IRQ LPC32XX_SIC1_IRQ(7) |
67 | #define IRQ_LPC32XX_TS_AUX LPC32XX_SIC1_IRQ(8) | 67 | #define IRQ_LPC32XX_TS_AUX LPC32XX_SIC1_IRQ(8) |
diff --git a/arch/arm/mach-lpc32xx/irq.c b/arch/arm/mach-lpc32xx/irq.c index 4eae566dfdc7..ce4b5570bd62 100644 --- a/arch/arm/mach-lpc32xx/irq.c +++ b/arch/arm/mach-lpc32xx/irq.c | |||
@@ -118,6 +118,10 @@ static const struct lpc32xx_event_info lpc32xx_events[NR_IRQS] = { | |||
118 | .event_group = &lpc32xx_event_pin_regs, | 118 | .event_group = &lpc32xx_event_pin_regs, |
119 | .mask = LPC32XX_CLKPWR_EXTSRC_GPI_06_BIT, | 119 | .mask = LPC32XX_CLKPWR_EXTSRC_GPI_06_BIT, |
120 | }, | 120 | }, |
121 | [IRQ_LPC32XX_GPI_28] = { | ||
122 | .event_group = &lpc32xx_event_pin_regs, | ||
123 | .mask = LPC32XX_CLKPWR_EXTSRC_GPI_28_BIT, | ||
124 | }, | ||
121 | [IRQ_LPC32XX_GPIO_00] = { | 125 | [IRQ_LPC32XX_GPIO_00] = { |
122 | .event_group = &lpc32xx_event_int_regs, | 126 | .event_group = &lpc32xx_event_int_regs, |
123 | .mask = LPC32XX_CLKPWR_INTSRC_GPIO_00_BIT, | 127 | .mask = LPC32XX_CLKPWR_INTSRC_GPIO_00_BIT, |