x86, bts: DS and BTS initialization

Impact: widen BTS/PEBS ptrace enablement to more CPU models

Move BTS initialisation out of an #ifdef CONFIG_X86_64 guard.

Assume core2 BTS and DS layout for future models of family 6 processors.

Signed-off-by: Markus Metzger <markus.t.metzger@intel.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>

3 files changed, 9 insertions, 12 deletions

diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index cce0b6118d55..816f27f289b1 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -307,12 +307,11 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
                 set_cpu_cap(c, X86_FEATURE_P4);
         if (c->x86 == 6)
                 set_cpu_cap(c, X86_FEATURE_P3);
+#endif
 
         if (cpu_has_bts)
                 ptrace_bts_init_intel(c);
 
-#endif
-
         detect_extended_topology(c);
         if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
                 /*
diff --git a/arch/x86/kernel/ds.c b/arch/x86/kernel/ds.c
index 2b69994fd3a8..c570252905a1 100644
--- a/arch/x86/kernel/ds.c
+++ b/arch/x86/kernel/ds.c
@@ -821,17 +821,16 @@ void __cpuinit ds_init_intel(struct cpuinfo_x86 *c)
         switch (c->x86) {
         case 0x6:
                 switch (c->x86_model) {
+                case 0 ... 0xC:
+                        /* sorry, don't know about them */
+                        break;
                 case 0xD:
                 case 0xE: /* Pentium M */
                         ds_configure(&ds_cfg_var);
                         break;
-                case 0xF: /* Core2 */
-                case 0x1C: /* Atom */
+                default: /* Core2, Atom, ... */
                         ds_configure(&ds_cfg_64);
                         break;
-                default:
-                        /* sorry, don't know about them */
-                        break;
                 }
                 break;
         case 0xF:
diff --git a/arch/x86/kernel/ptrace.c b/arch/x86/kernel/ptrace.c
index 0a6d8c12e10d..06180dff5b2e 100644
--- a/arch/x86/kernel/ptrace.c
+++ b/arch/x86/kernel/ptrace.c
@@ -929,17 +929,16 @@ void __cpuinit ptrace_bts_init_intel(struct cpuinfo_x86 *c)
         switch (c->x86) {
         case 0x6:
                 switch (c->x86_model) {
+                case 0 ... 0xC:
+                        /* sorry, don't know about them */
+                        break;
                 case 0xD:
                 case 0xE: /* Pentium M */
                         bts_configure(&bts_cfg_pentium_m);
                         break;
-                case 0xF: /* Core2 */
-        case 0x1C: /* Atom */
+                default: /* Core2, Atom, ... */
                         bts_configure(&bts_cfg_core2);
                         break;
-                default:
-                        /* sorry, don't know about them */
-                        break;
                 }
                 break;
         case 0xF: