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authorThomas Gleixner <tglx@linutronix.de>2011-03-24 08:35:09 -0400
committerThomas Gleixner <tglx@linutronix.de>2011-03-29 08:47:58 -0400
commitf38c02f3b338651e145aac2889ba976baf6b28b3 (patch)
tree30cfbf42ccff4a9dc26d95e9058ec76f5fde78bb /arch
parent9323f26186403433293e87e717a7785f74f75d80 (diff)
arm: Fold irq_set_chip/irq_set_handler
Use irq_set_chip_and_handler() instead. Converted with coccinelle. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/common/gic.c3
-rw-r--r--arch/arm/common/it8152.c4
-rw-r--r--arch/arm/common/locomo.c3
-rw-r--r--arch/arm/common/sa1111.c8
-rw-r--r--arch/arm/common/vic.c4
-rw-r--r--arch/arm/kernel/ecard.c4
-rw-r--r--arch/arm/mach-at91/gpio.c4
-rw-r--r--arch/arm/mach-at91/irq.c3
-rw-r--r--arch/arm/mach-clps711x/irq.c8
-rw-r--r--arch/arm/mach-dove/irq.c3
-rw-r--r--arch/arm/mach-ebsa110/core.c4
-rw-r--r--arch/arm/mach-ep93xx/gpio.c4
-rw-r--r--arch/arm/mach-exynos4/irq-combiner.c3
-rw-r--r--arch/arm/mach-exynos4/irq-eint.c4
-rw-r--r--arch/arm/mach-footbridge/common.c3
-rw-r--r--arch/arm/mach-footbridge/isa-irq.c8
-rw-r--r--arch/arm/mach-gemini/gpio.c4
-rw-r--r--arch/arm/mach-h720x/common.c12
-rw-r--r--arch/arm/mach-h720x/cpu-h7202.c4
-rw-r--r--arch/arm/mach-iop32x/irq.c3
-rw-r--r--arch/arm/mach-iop33x/irq.c6
-rw-r--r--arch/arm/mach-ixp2000/core.c16
-rw-r--r--arch/arm/mach-ixp2000/ixdp2x00.c4
-rw-r--r--arch/arm/mach-ixp2000/ixdp2x01.c4
-rw-r--r--arch/arm/mach-ixp23xx/core.c12
-rw-r--r--arch/arm/mach-ixp23xx/ixdp2351.c8
-rw-r--r--arch/arm/mach-ixp4xx/common.c4
-rw-r--r--arch/arm/mach-ks8695/irq.c18
-rw-r--r--arch/arm/mach-lpc32xx/irq.c4
-rw-r--r--arch/arm/mach-mmp/irq-pxa168.c3
-rw-r--r--arch/arm/mach-msm/board-trout-gpio.c4
-rw-r--r--arch/arm/mach-msm/gpio-v2.c4
-rw-r--r--arch/arm/mach-msm/gpio.c4
-rw-r--r--arch/arm/mach-msm/irq-vic.c3
-rw-r--r--arch/arm/mach-msm/irq.c3
-rw-r--r--arch/arm/mach-msm/sirc.c3
-rw-r--r--arch/arm/mach-mx3/mach-mx31ads.c3
-rw-r--r--arch/arm/mach-mxs/gpio.c4
-rw-r--r--arch/arm/mach-mxs/icoll.c3
-rw-r--r--arch/arm/mach-netx/generic.c4
-rw-r--r--arch/arm/mach-ns9xxx/board-a9m9750dev.c4
-rw-r--r--arch/arm/mach-ns9xxx/irq.c3
-rw-r--r--arch/arm/mach-nuc93x/irq.c4
-rw-r--r--arch/arm/mach-omap1/irq.c4
-rw-r--r--arch/arm/mach-omap2/irq.c3
-rw-r--r--arch/arm/mach-pxa/balloon3.c4
-rw-r--r--arch/arm/mach-pxa/irq.c8
-rw-r--r--arch/arm/mach-pxa/lpd270.c4
-rw-r--r--arch/arm/mach-pxa/lubbock.c4
-rw-r--r--arch/arm/mach-pxa/mainstone.c4
-rw-r--r--arch/arm/mach-pxa/pcm990-baseboard.c4
-rw-r--r--arch/arm/mach-pxa/pxa3xx.c4
-rw-r--r--arch/arm/mach-pxa/viper.c4
-rw-r--r--arch/arm/mach-pxa/zeus.c4
-rw-r--r--arch/arm/mach-rpc/irq.c12
-rw-r--r--arch/arm/mach-s3c2410/bast-irq.c4
-rw-r--r--arch/arm/mach-s3c2412/irq.c8
-rw-r--r--arch/arm/mach-s3c2416/irq.c6
-rw-r--r--arch/arm/mach-s3c2440/irq.c8
-rw-r--r--arch/arm/mach-s3c2440/s3c244x-irq.c12
-rw-r--r--arch/arm/mach-s3c2443/irq.c6
-rw-r--r--arch/arm/mach-s3c64xx/irq-eint.c3
-rw-r--r--arch/arm/mach-sa1100/irq.c12
-rw-r--r--arch/arm/mach-shark/irq.c3
-rw-r--r--arch/arm/mach-tegra/gpio.c4
-rw-r--r--arch/arm/mach-tegra/irq.c3
-rw-r--r--arch/arm/mach-ux500/modem-irq-db5500.c3
-rw-r--r--arch/arm/mach-vt8500/irq.c8
-rw-r--r--arch/arm/mach-w90x900/irq.c4
-rw-r--r--arch/arm/plat-mxc/3ds_debugboard.c3
-rw-r--r--arch/arm/plat-mxc/avic.c4
-rw-r--r--arch/arm/plat-mxc/gpio.c4
-rw-r--r--arch/arm/plat-mxc/tzic.c4
-rw-r--r--arch/arm/plat-nomadik/gpio.c4
-rw-r--r--arch/arm/plat-orion/gpio.c4
-rw-r--r--arch/arm/plat-orion/irq.c4
-rw-r--r--arch/arm/plat-pxa/gpio.c4
-rw-r--r--arch/arm/plat-s3c24xx/irq.c31
-rw-r--r--arch/arm/plat-s5p/irq-eint.c3
-rw-r--r--arch/arm/plat-samsung/irq-uart.c3
-rw-r--r--arch/arm/plat-spear/shirq.c4
-rw-r--r--arch/arm/plat-stmp3xxx/irq.c3
-rw-r--r--arch/arm/plat-stmp3xxx/pinmux.c4
-rw-r--r--arch/arm/plat-versatile/fpga-irq.c4
84 files changed, 209 insertions, 235 deletions
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index 630d46b5ab82..f70ec7dadebb 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -319,8 +319,7 @@ static void __init gic_dist_init(struct gic_chip_data *gic,
319 * Setup the Linux IRQ subsystem. 319 * Setup the Linux IRQ subsystem.
320 */ 320 */
321 for (i = irq_start; i < irq_limit; i++) { 321 for (i = irq_start; i < irq_limit; i++) {
322 irq_set_chip(i, &gic_chip); 322 irq_set_chip_and_handler(i, &gic_chip, handle_level_irq);
323 irq_set_handler(i, handle_level_irq);
324 irq_set_chip_data(i, gic); 323 irq_set_chip_data(i, gic);
325 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 324 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
326 } 325 }
diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c
index c815d00eb349..7a21927c52e1 100644
--- a/arch/arm/common/it8152.c
+++ b/arch/arm/common/it8152.c
@@ -88,8 +88,8 @@ void it8152_init_irq(void)
88 __raw_writel((0), IT8152_INTC_LDCNIRR); 88 __raw_writel((0), IT8152_INTC_LDCNIRR);
89 89
90 for (irq = IT8152_IRQ(0); irq <= IT8152_LAST_IRQ; irq++) { 90 for (irq = IT8152_IRQ(0); irq <= IT8152_LAST_IRQ; irq++) {
91 irq_set_chip(irq, &it8152_irq_chip); 91 irq_set_chip_and_handler(irq, &it8152_irq_chip,
92 irq_set_handler(irq, handle_level_irq); 92 handle_level_irq);
93 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 93 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
94 } 94 }
95} 95}
diff --git a/arch/arm/common/locomo.c b/arch/arm/common/locomo.c
index 54d91f8607e7..b55c3625d7ee 100644
--- a/arch/arm/common/locomo.c
+++ b/arch/arm/common/locomo.c
@@ -203,8 +203,7 @@ static void locomo_setup_irq(struct locomo *lchip)
203 203
204 /* Install handlers for IRQ_LOCOMO_* */ 204 /* Install handlers for IRQ_LOCOMO_* */
205 for ( ; irq <= lchip->irq_base + 3; irq++) { 205 for ( ; irq <= lchip->irq_base + 3; irq++) {
206 irq_set_chip(irq, &locomo_chip); 206 irq_set_chip_and_handler(irq, &locomo_chip, handle_level_irq);
207 irq_set_handler(irq, handle_level_irq);
208 irq_set_chip_data(irq, lchip); 207 irq_set_chip_data(irq, lchip);
209 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 208 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
210 } 209 }
diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c
index f098f5c9fa3e..a12b33c0dc42 100644
--- a/arch/arm/common/sa1111.c
+++ b/arch/arm/common/sa1111.c
@@ -472,15 +472,15 @@ static void sa1111_setup_irq(struct sa1111 *sachip)
472 sa1111_writel(~0, irqbase + SA1111_INTSTATCLR1); 472 sa1111_writel(~0, irqbase + SA1111_INTSTATCLR1);
473 473
474 for (irq = IRQ_GPAIN0; irq <= SSPROR; irq++) { 474 for (irq = IRQ_GPAIN0; irq <= SSPROR; irq++) {
475 irq_set_chip(irq, &sa1111_low_chip); 475 irq_set_chip_and_handler(irq, &sa1111_low_chip,
476 irq_set_handler(irq, handle_edge_irq); 476 handle_edge_irq);
477 irq_set_chip_data(irq, sachip); 477 irq_set_chip_data(irq, sachip);
478 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 478 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
479 } 479 }
480 480
481 for (irq = AUDXMTDMADONEA; irq <= IRQ_S1_BVD1_STSCHG; irq++) { 481 for (irq = AUDXMTDMADONEA; irq <= IRQ_S1_BVD1_STSCHG; irq++) {
482 irq_set_chip(irq, &sa1111_high_chip); 482 irq_set_chip_and_handler(irq, &sa1111_high_chip,
483 irq_set_handler(irq, handle_edge_irq); 483 handle_edge_irq);
484 irq_set_chip_data(irq, sachip); 484 irq_set_chip_data(irq, sachip);
485 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 485 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
486 } 486 }
diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c
index e282fd1a436a..113085a77123 100644
--- a/arch/arm/common/vic.c
+++ b/arch/arm/common/vic.c
@@ -305,8 +305,8 @@ static void __init vic_set_irq_sources(void __iomem *base,
305 if (vic_sources & (1 << i)) { 305 if (vic_sources & (1 << i)) {
306 unsigned int irq = irq_start + i; 306 unsigned int irq = irq_start + i;
307 307
308 irq_set_chip(irq, &vic_chip); 308 irq_set_chip_and_handler(irq, &vic_chip,
309 irq_set_handler(irq, handle_level_irq); 309 handle_level_irq);
310 irq_set_chip_data(irq, base); 310 irq_set_chip_data(irq, base);
311 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 311 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
312 } 312 }
diff --git a/arch/arm/kernel/ecard.c b/arch/arm/kernel/ecard.c
index a9690f1c28e2..d16500110ee9 100644
--- a/arch/arm/kernel/ecard.c
+++ b/arch/arm/kernel/ecard.c
@@ -1043,8 +1043,8 @@ ecard_probe(int slot, card_type_t type)
1043 */ 1043 */
1044 if (slot < 8) { 1044 if (slot < 8) {
1045 ec->irq = 32 + slot; 1045 ec->irq = 32 + slot;
1046 irq_set_chip(ec->irq, &ecard_chip); 1046 irq_set_chip_and_handler(ec->irq, &ecard_chip,
1047 irq_set_handler(ec->irq, handle_level_irq); 1047 handle_level_irq);
1048 set_irq_flags(ec->irq, IRQF_VALID); 1048 set_irq_flags(ec->irq, IRQF_VALID);
1049 } 1049 }
1050 1050
diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
index 8512b796e653..4615528205c8 100644
--- a/arch/arm/mach-at91/gpio.c
+++ b/arch/arm/mach-at91/gpio.c
@@ -511,8 +511,8 @@ void __init at91_gpio_irq_setup(void)
511 * Can use the "simple" and not "edge" handler since it's 511 * Can use the "simple" and not "edge" handler since it's
512 * shorter, and the AIC handles interrupts sanely. 512 * shorter, and the AIC handles interrupts sanely.
513 */ 513 */
514 irq_set_chip(pin, &gpio_irqchip); 514 irq_set_chip_and_handler(pin, &gpio_irqchip,
515 irq_set_handler(pin, handle_simple_irq); 515 handle_simple_irq);
516 set_irq_flags(pin, IRQF_VALID); 516 set_irq_flags(pin, IRQF_VALID);
517 } 517 }
518 518
diff --git a/arch/arm/mach-at91/irq.c b/arch/arm/mach-at91/irq.c
index 566cec1d9073..9665265ec757 100644
--- a/arch/arm/mach-at91/irq.c
+++ b/arch/arm/mach-at91/irq.c
@@ -143,8 +143,7 @@ void __init at91_aic_init(unsigned int priority[NR_AIC_IRQS])
143 /* Active Low interrupt, with the specified priority */ 143 /* Active Low interrupt, with the specified priority */
144 at91_sys_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]); 144 at91_sys_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]);
145 145
146 irq_set_chip(i, &at91_aic_chip); 146 irq_set_chip_and_handler(i, &at91_aic_chip, handle_level_irq);
147 irq_set_handler(i, handle_level_irq);
148 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 147 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
149 148
150 /* Perform 8 End Of Interrupt Command to make sure AIC will not Lock out nIRQ */ 149 /* Perform 8 End Of Interrupt Command to make sure AIC will not Lock out nIRQ */
diff --git a/arch/arm/mach-clps711x/irq.c b/arch/arm/mach-clps711x/irq.c
index 5c5ec01d8972..c2eceee645e3 100644
--- a/arch/arm/mach-clps711x/irq.c
+++ b/arch/arm/mach-clps711x/irq.c
@@ -112,13 +112,13 @@ void __init clps711x_init_irq(void)
112 112
113 for (i = 0; i < NR_IRQS; i++) { 113 for (i = 0; i < NR_IRQS; i++) {
114 if (INT1_IRQS & (1 << i)) { 114 if (INT1_IRQS & (1 << i)) {
115 irq_set_handler(i, handle_level_irq); 115 irq_set_chip_and_handler(i, &int1_chip,
116 irq_set_chip(i, &int1_chip); 116 handle_level_irq);
117 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 117 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
118 } 118 }
119 if (INT2_IRQS & (1 << i)) { 119 if (INT2_IRQS & (1 << i)) {
120 irq_set_handler(i, handle_level_irq); 120 irq_set_chip_and_handler(i, &int2_chip,
121 irq_set_chip(i, &int2_chip); 121 handle_level_irq);
122 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 122 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
123 } 123 }
124 } 124 }
diff --git a/arch/arm/mach-dove/irq.c b/arch/arm/mach-dove/irq.c
index f038a19f4c6e..f07fd16e0c9b 100644
--- a/arch/arm/mach-dove/irq.c
+++ b/arch/arm/mach-dove/irq.c
@@ -121,8 +121,7 @@ void __init dove_init_irq(void)
121 writel(0, PMU_INTERRUPT_CAUSE); 121 writel(0, PMU_INTERRUPT_CAUSE);
122 122
123 for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) { 123 for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) {
124 irq_set_chip(i, &pmu_irq_chip); 124 irq_set_chip_and_handler(i, &pmu_irq_chip, handle_level_irq);
125 irq_set_handler(i, handle_level_irq);
126 irq_set_status_flags(i, IRQ_LEVEL); 125 irq_set_status_flags(i, IRQ_LEVEL);
127 set_irq_flags(i, IRQF_VALID); 126 set_irq_flags(i, IRQF_VALID);
128 } 127 }
diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c
index caf6cbac33e0..087bc771ac23 100644
--- a/arch/arm/mach-ebsa110/core.c
+++ b/arch/arm/mach-ebsa110/core.c
@@ -66,8 +66,8 @@ static void __init ebsa110_init_irq(void)
66 local_irq_restore(flags); 66 local_irq_restore(flags);
67 67
68 for (irq = 0; irq < NR_IRQS; irq++) { 68 for (irq = 0; irq < NR_IRQS; irq++) {
69 irq_set_chip(irq, &ebsa110_irq_chip); 69 irq_set_chip_and_handler(irq, &ebsa110_irq_chip,
70 irq_set_handler(irq, handle_level_irq); 70 handle_level_irq);
71 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 71 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
72 } 72 }
73} 73}
diff --git a/arch/arm/mach-ep93xx/gpio.c b/arch/arm/mach-ep93xx/gpio.c
index 7da0a5cefa5f..180b8a9d0d21 100644
--- a/arch/arm/mach-ep93xx/gpio.c
+++ b/arch/arm/mach-ep93xx/gpio.c
@@ -231,8 +231,8 @@ void __init ep93xx_gpio_init_irq(void)
231 231
232 for (gpio_irq = gpio_to_irq(0); 232 for (gpio_irq = gpio_to_irq(0);
233 gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) { 233 gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
234 irq_set_chip(gpio_irq, &ep93xx_gpio_irq_chip); 234 irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip,
235 irq_set_handler(gpio_irq, handle_level_irq); 235 handle_level_irq);
236 set_irq_flags(gpio_irq, IRQF_VALID); 236 set_irq_flags(gpio_irq, IRQF_VALID);
237 } 237 }
238 238
diff --git a/arch/arm/mach-exynos4/irq-combiner.c b/arch/arm/mach-exynos4/irq-combiner.c
index 3a217be718f8..f488b66d6806 100644
--- a/arch/arm/mach-exynos4/irq-combiner.c
+++ b/arch/arm/mach-exynos4/irq-combiner.c
@@ -119,8 +119,7 @@ void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
119 119
120 for (i = irq_start; i < combiner_data[combiner_nr].irq_offset 120 for (i = irq_start; i < combiner_data[combiner_nr].irq_offset
121 + MAX_IRQ_IN_COMBINER; i++) { 121 + MAX_IRQ_IN_COMBINER; i++) {
122 irq_set_chip(i, &combiner_chip); 122 irq_set_chip_and_handler(i, &combiner_chip, handle_level_irq);
123 irq_set_handler(i, handle_level_irq);
124 irq_set_chip_data(i, &combiner_data[combiner_nr]); 123 irq_set_chip_data(i, &combiner_data[combiner_nr]);
125 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 124 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
126 } 125 }
diff --git a/arch/arm/mach-exynos4/irq-eint.c b/arch/arm/mach-exynos4/irq-eint.c
index 0441dfc7c924..9d87d2ac7f68 100644
--- a/arch/arm/mach-exynos4/irq-eint.c
+++ b/arch/arm/mach-exynos4/irq-eint.c
@@ -208,8 +208,8 @@ int __init exynos4_init_irq_eint(void)
208 int irq; 208 int irq;
209 209
210 for (irq = 0 ; irq <= 31 ; irq++) { 210 for (irq = 0 ; irq <= 31 ; irq++) {
211 irq_set_chip(IRQ_EINT(irq), &exynos4_irq_eint); 211 irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint,
212 irq_set_handler(IRQ_EINT(irq), handle_level_irq); 212 handle_level_irq);
213 set_irq_flags(IRQ_EINT(irq), IRQF_VALID); 213 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
214 } 214 }
215 215
diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c
index 06239f9a7afb..38a44f9b9da2 100644
--- a/arch/arm/mach-footbridge/common.c
+++ b/arch/arm/mach-footbridge/common.c
@@ -102,8 +102,7 @@ static void __init __fb_init_irq(void)
102 *CSR_FIQ_DISABLE = -1; 102 *CSR_FIQ_DISABLE = -1;
103 103
104 for (irq = _DC21285_IRQ(0); irq < _DC21285_IRQ(20); irq++) { 104 for (irq = _DC21285_IRQ(0); irq < _DC21285_IRQ(20); irq++) {
105 irq_set_chip(irq, &fb_chip); 105 irq_set_chip_and_handler(irq, &fb_chip, handle_level_irq);
106 irq_set_handler(irq, handle_level_irq);
107 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 106 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
108 } 107 }
109} 108}
diff --git a/arch/arm/mach-footbridge/isa-irq.c b/arch/arm/mach-footbridge/isa-irq.c
index 0bc528e6cb23..c3a0abbc9049 100644
--- a/arch/arm/mach-footbridge/isa-irq.c
+++ b/arch/arm/mach-footbridge/isa-irq.c
@@ -151,14 +151,14 @@ void __init isa_init_irq(unsigned int host_irq)
151 151
152 if (host_irq != (unsigned int)-1) { 152 if (host_irq != (unsigned int)-1) {
153 for (irq = _ISA_IRQ(0); irq < _ISA_IRQ(8); irq++) { 153 for (irq = _ISA_IRQ(0); irq < _ISA_IRQ(8); irq++) {
154 irq_set_chip(irq, &isa_lo_chip); 154 irq_set_chip_and_handler(irq, &isa_lo_chip,
155 irq_set_handler(irq, handle_level_irq); 155 handle_level_irq);
156 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 156 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
157 } 157 }
158 158
159 for (irq = _ISA_IRQ(8); irq < _ISA_IRQ(16); irq++) { 159 for (irq = _ISA_IRQ(8); irq < _ISA_IRQ(16); irq++) {
160 irq_set_chip(irq, &isa_hi_chip); 160 irq_set_chip_and_handler(irq, &isa_hi_chip,
161 irq_set_handler(irq, handle_level_irq); 161 handle_level_irq);
162 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 162 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
163 } 163 }
164 164
diff --git a/arch/arm/mach-gemini/gpio.c b/arch/arm/mach-gemini/gpio.c
index 0e7b56ea6295..fdc7ef1391d3 100644
--- a/arch/arm/mach-gemini/gpio.c
+++ b/arch/arm/mach-gemini/gpio.c
@@ -217,8 +217,8 @@ void __init gemini_gpio_init(void)
217 217
218 for (j = GPIO_IRQ_BASE + i * 32; 218 for (j = GPIO_IRQ_BASE + i * 32;
219 j < GPIO_IRQ_BASE + (i + 1) * 32; j++) { 219 j < GPIO_IRQ_BASE + (i + 1) * 32; j++) {
220 irq_set_chip(j, &gpio_irq_chip); 220 irq_set_chip_and_handler(j, &gpio_irq_chip,
221 irq_set_handler(j, handle_edge_irq); 221 handle_edge_irq);
222 set_irq_flags(j, IRQF_VALID); 222 set_irq_flags(j, IRQF_VALID);
223 } 223 }
224 224
diff --git a/arch/arm/mach-h720x/common.c b/arch/arm/mach-h720x/common.c
index f118182a99ca..51d4e44ab973 100644
--- a/arch/arm/mach-h720x/common.c
+++ b/arch/arm/mach-h720x/common.c
@@ -199,15 +199,15 @@ void __init h720x_init_irq (void)
199 199
200 /* Initialize global IRQ's, fast path */ 200 /* Initialize global IRQ's, fast path */
201 for (irq = 0; irq < NR_GLBL_IRQS; irq++) { 201 for (irq = 0; irq < NR_GLBL_IRQS; irq++) {
202 irq_set_chip(irq, &h720x_global_chip); 202 irq_set_chip_and_handler(irq, &h720x_global_chip,
203 irq_set_handler(irq, handle_level_irq); 203 handle_level_irq);
204 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 204 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
205 } 205 }
206 206
207 /* Initialize multiplexed IRQ's, slow path */ 207 /* Initialize multiplexed IRQ's, slow path */
208 for (irq = IRQ_CHAINED_GPIOA(0) ; irq <= IRQ_CHAINED_GPIOD(31); irq++) { 208 for (irq = IRQ_CHAINED_GPIOA(0) ; irq <= IRQ_CHAINED_GPIOD(31); irq++) {
209 irq_set_chip(irq, &h720x_gpio_chip); 209 irq_set_chip_and_handler(irq, &h720x_gpio_chip,
210 irq_set_handler(irq, handle_edge_irq); 210 handle_edge_irq);
211 set_irq_flags(irq, IRQF_VALID ); 211 set_irq_flags(irq, IRQF_VALID );
212 } 212 }
213 irq_set_chained_handler(IRQ_GPIOA, h720x_gpioa_demux_handler); 213 irq_set_chained_handler(IRQ_GPIOA, h720x_gpioa_demux_handler);
@@ -217,8 +217,8 @@ void __init h720x_init_irq (void)
217 217
218#ifdef CONFIG_CPU_H7202 218#ifdef CONFIG_CPU_H7202
219 for (irq = IRQ_CHAINED_GPIOE(0) ; irq <= IRQ_CHAINED_GPIOE(31); irq++) { 219 for (irq = IRQ_CHAINED_GPIOE(0) ; irq <= IRQ_CHAINED_GPIOE(31); irq++) {
220 irq_set_chip(irq, &h720x_gpio_chip); 220 irq_set_chip_and_handler(irq, &h720x_gpio_chip,
221 irq_set_handler(irq, handle_edge_irq); 221 handle_edge_irq);
222 set_irq_flags(irq, IRQF_VALID ); 222 set_irq_flags(irq, IRQF_VALID );
223 } 223 }
224 irq_set_chained_handler(IRQ_GPIOE, h720x_gpioe_demux_handler); 224 irq_set_chained_handler(IRQ_GPIOE, h720x_gpioe_demux_handler);
diff --git a/arch/arm/mach-h720x/cpu-h7202.c b/arch/arm/mach-h720x/cpu-h7202.c
index dd5c72a75dad..c37d570b852d 100644
--- a/arch/arm/mach-h720x/cpu-h7202.c
+++ b/arch/arm/mach-h720x/cpu-h7202.c
@@ -202,8 +202,8 @@ void __init h7202_init_irq (void)
202 for (irq = IRQ_TIMER1; 202 for (irq = IRQ_TIMER1;
203 irq < IRQ_CHAINED_TIMERX(NR_TIMERX_IRQS); irq++) { 203 irq < IRQ_CHAINED_TIMERX(NR_TIMERX_IRQS); irq++) {
204 __mask_timerx_irq(irq); 204 __mask_timerx_irq(irq);
205 irq_set_chip(irq, &h7202_timerx_chip); 205 irq_set_chip_and_handler(irq, &h7202_timerx_chip,
206 irq_set_handler(irq, handle_edge_irq); 206 handle_edge_irq);
207 set_irq_flags(irq, IRQF_VALID ); 207 set_irq_flags(irq, IRQF_VALID );
208 } 208 }
209 irq_set_chained_handler(IRQ_TIMERX, h7202_timerx_demux_handler); 209 irq_set_chained_handler(IRQ_TIMERX, h7202_timerx_demux_handler);
diff --git a/arch/arm/mach-iop32x/irq.c b/arch/arm/mach-iop32x/irq.c
index 226604633d66..d7ee2789d890 100644
--- a/arch/arm/mach-iop32x/irq.c
+++ b/arch/arm/mach-iop32x/irq.c
@@ -68,8 +68,7 @@ void __init iop32x_init_irq(void)
68 *IOP3XX_PCIIRSR = 0x0f; 68 *IOP3XX_PCIIRSR = 0x0f;
69 69
70 for (i = 0; i < NR_IRQS; i++) { 70 for (i = 0; i < NR_IRQS; i++) {
71 irq_set_chip(i, &ext_chip); 71 irq_set_chip_and_handler(i, &ext_chip, handle_level_irq);
72 irq_set_handler(i, handle_level_irq);
73 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 72 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
74 } 73 }
75} 74}
diff --git a/arch/arm/mach-iop33x/irq.c b/arch/arm/mach-iop33x/irq.c
index 7b205e990298..f7f5d3e451c7 100644
--- a/arch/arm/mach-iop33x/irq.c
+++ b/arch/arm/mach-iop33x/irq.c
@@ -110,9 +110,9 @@ void __init iop33x_init_irq(void)
110 *IOP3XX_PCIIRSR = 0x0f; 110 *IOP3XX_PCIIRSR = 0x0f;
111 111
112 for (i = 0; i < NR_IRQS; i++) { 112 for (i = 0; i < NR_IRQS; i++) {
113 irq_set_chip(i, 113 irq_set_chip_and_handler(i,
114 (i < 32) ? &iop33x_irqchip1 : &iop33x_irqchip2); 114 (i < 32) ? &iop33x_irqchip1 : &iop33x_irqchip2,
115 irq_set_handler(i, handle_level_irq); 115 handle_level_irq);
116 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 116 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
117 } 117 }
118} 118}
diff --git a/arch/arm/mach-ixp2000/core.c b/arch/arm/mach-ixp2000/core.c
index 98956a136b94..4068166c8993 100644
--- a/arch/arm/mach-ixp2000/core.c
+++ b/arch/arm/mach-ixp2000/core.c
@@ -476,8 +476,8 @@ void __init ixp2000_init_irq(void)
476 */ 476 */
477 for (irq = IRQ_IXP2000_SOFT_INT; irq <= IRQ_IXP2000_THDB3; irq++) { 477 for (irq = IRQ_IXP2000_SOFT_INT; irq <= IRQ_IXP2000_THDB3; irq++) {
478 if ((1 << irq) & IXP2000_VALID_IRQ_MASK) { 478 if ((1 << irq) & IXP2000_VALID_IRQ_MASK) {
479 irq_set_chip(irq, &ixp2000_irq_chip); 479 irq_set_chip_and_handler(irq, &ixp2000_irq_chip,
480 irq_set_handler(irq, handle_level_irq); 480 handle_level_irq);
481 set_irq_flags(irq, IRQF_VALID); 481 set_irq_flags(irq, IRQF_VALID);
482 } else set_irq_flags(irq, 0); 482 } else set_irq_flags(irq, 0);
483 } 483 }
@@ -485,8 +485,8 @@ void __init ixp2000_init_irq(void)
485 for (irq = IRQ_IXP2000_DRAM0_MIN_ERR; irq <= IRQ_IXP2000_SP_INT; irq++) { 485 for (irq = IRQ_IXP2000_DRAM0_MIN_ERR; irq <= IRQ_IXP2000_SP_INT; irq++) {
486 if((1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)) & 486 if((1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)) &
487 IXP2000_VALID_ERR_IRQ_MASK) { 487 IXP2000_VALID_ERR_IRQ_MASK) {
488 irq_set_chip(irq, &ixp2000_err_irq_chip); 488 irq_set_chip_and_handler(irq, &ixp2000_err_irq_chip,
489 irq_set_handler(irq, handle_level_irq); 489 handle_level_irq);
490 set_irq_flags(irq, IRQF_VALID); 490 set_irq_flags(irq, IRQF_VALID);
491 } 491 }
492 else 492 else
@@ -495,8 +495,8 @@ void __init ixp2000_init_irq(void)
495 irq_set_chained_handler(IRQ_IXP2000_ERRSUM, ixp2000_err_irq_handler); 495 irq_set_chained_handler(IRQ_IXP2000_ERRSUM, ixp2000_err_irq_handler);
496 496
497 for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) { 497 for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) {
498 irq_set_chip(irq, &ixp2000_GPIO_irq_chip); 498 irq_set_chip_and_handler(irq, &ixp2000_GPIO_irq_chip,
499 irq_set_handler(irq, handle_level_irq); 499 handle_level_irq);
500 set_irq_flags(irq, IRQF_VALID); 500 set_irq_flags(irq, IRQF_VALID);
501 } 501 }
502 irq_set_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler); 502 irq_set_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler);
@@ -508,8 +508,8 @@ void __init ixp2000_init_irq(void)
508 */ 508 */
509 ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI)); 509 ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI));
510 for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) { 510 for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) {
511 irq_set_chip(irq, &ixp2000_pci_irq_chip); 511 irq_set_chip_and_handler(irq, &ixp2000_pci_irq_chip,
512 irq_set_handler(irq, handle_level_irq); 512 handle_level_irq);
513 set_irq_flags(irq, IRQF_VALID); 513 set_irq_flags(irq, IRQF_VALID);
514 } 514 }
515} 515}
diff --git a/arch/arm/mach-ixp2000/ixdp2x00.c b/arch/arm/mach-ixp2000/ixdp2x00.c
index 52f88648522f..235638f800e5 100644
--- a/arch/arm/mach-ixp2000/ixdp2x00.c
+++ b/arch/arm/mach-ixp2000/ixdp2x00.c
@@ -158,8 +158,8 @@ void __init ixdp2x00_init_irq(volatile unsigned long *stat_reg, volatile unsigne
158 *board_irq_mask = 0xffffffff; 158 *board_irq_mask = 0xffffffff;
159 159
160 for(irq = IXP2000_BOARD_IRQ(0); irq < IXP2000_BOARD_IRQ(board_irq_count); irq++) { 160 for(irq = IXP2000_BOARD_IRQ(0); irq < IXP2000_BOARD_IRQ(board_irq_count); irq++) {
161 irq_set_chip(irq, &ixdp2x00_cpld_irq_chip); 161 irq_set_chip_and_handler(irq, &ixdp2x00_cpld_irq_chip,
162 irq_set_handler(irq, handle_level_irq); 162 handle_level_irq);
163 set_irq_flags(irq, IRQF_VALID); 163 set_irq_flags(irq, IRQF_VALID);
164 } 164 }
165 165
diff --git a/arch/arm/mach-ixp2000/ixdp2x01.c b/arch/arm/mach-ixp2000/ixdp2x01.c
index f1ff50ba6c9a..84835b209557 100644
--- a/arch/arm/mach-ixp2000/ixdp2x01.c
+++ b/arch/arm/mach-ixp2000/ixdp2x01.c
@@ -115,8 +115,8 @@ void __init ixdp2x01_init_irq(void)
115 115
116 for (irq = NR_IXP2000_IRQS; irq < NR_IXDP2X01_IRQS; irq++) { 116 for (irq = NR_IXP2000_IRQS; irq < NR_IXDP2X01_IRQS; irq++) {
117 if (irq & valid_irq_mask) { 117 if (irq & valid_irq_mask) {
118 irq_set_chip(irq, &ixdp2x01_irq_chip); 118 irq_set_chip_and_handler(irq, &ixdp2x01_irq_chip,
119 irq_set_handler(irq, handle_level_irq); 119 handle_level_irq);
120 set_irq_flags(irq, IRQF_VALID); 120 set_irq_flags(irq, IRQF_VALID);
121 } else { 121 } else {
122 set_irq_flags(irq, 0); 122 set_irq_flags(irq, 0);
diff --git a/arch/arm/mach-ixp23xx/core.c b/arch/arm/mach-ixp23xx/core.c
index f2039722bace..a1bee33d183e 100644
--- a/arch/arm/mach-ixp23xx/core.c
+++ b/arch/arm/mach-ixp23xx/core.c
@@ -289,12 +289,12 @@ static void ixp23xx_config_irq(unsigned int irq, enum ixp23xx_irq_type type)
289{ 289{
290 switch (type) { 290 switch (type) {
291 case IXP23XX_IRQ_LEVEL: 291 case IXP23XX_IRQ_LEVEL:
292 irq_set_chip(irq, &ixp23xx_irq_level_chip); 292 irq_set_chip_and_handler(irq, &ixp23xx_irq_level_chip,
293 irq_set_handler(irq, handle_level_irq); 293 handle_level_irq);
294 break; 294 break;
295 case IXP23XX_IRQ_EDGE: 295 case IXP23XX_IRQ_EDGE:
296 irq_set_chip(irq, &ixp23xx_irq_edge_chip); 296 irq_set_chip_and_handler(irq, &ixp23xx_irq_edge_chip,
297 irq_set_handler(irq, handle_edge_irq); 297 handle_edge_irq);
298 break; 298 break;
299 } 299 }
300 set_irq_flags(irq, IRQF_VALID); 300 set_irq_flags(irq, IRQF_VALID);
@@ -324,8 +324,8 @@ void __init ixp23xx_init_irq(void)
324 } 324 }
325 325
326 for (irq = IRQ_IXP23XX_INTA; irq <= IRQ_IXP23XX_INTB; irq++) { 326 for (irq = IRQ_IXP23XX_INTA; irq <= IRQ_IXP23XX_INTB; irq++) {
327 irq_set_chip(irq, &ixp23xx_pci_irq_chip); 327 irq_set_chip_and_handler(irq, &ixp23xx_pci_irq_chip,
328 irq_set_handler(irq, handle_level_irq); 328 handle_level_irq);
329 set_irq_flags(irq, IRQF_VALID); 329 set_irq_flags(irq, IRQF_VALID);
330 } 330 }
331 331
diff --git a/arch/arm/mach-ixp23xx/ixdp2351.c b/arch/arm/mach-ixp23xx/ixdp2351.c
index 720befb0a402..8dcba17c81e7 100644
--- a/arch/arm/mach-ixp23xx/ixdp2351.c
+++ b/arch/arm/mach-ixp23xx/ixdp2351.c
@@ -136,8 +136,8 @@ void __init ixdp2351_init_irq(void)
136 irq++) { 136 irq++) {
137 if (IXDP2351_INTA_IRQ_MASK(irq) & IXDP2351_INTA_IRQ_VALID) { 137 if (IXDP2351_INTA_IRQ_MASK(irq) & IXDP2351_INTA_IRQ_VALID) {
138 set_irq_flags(irq, IRQF_VALID); 138 set_irq_flags(irq, IRQF_VALID);
139 irq_set_handler(irq, handle_level_irq); 139 irq_set_chip_and_handler(irq, &ixdp2351_inta_chip,
140 irq_set_chip(irq, &ixdp2351_inta_chip); 140 handle_level_irq);
141 } 141 }
142 } 142 }
143 143
@@ -147,8 +147,8 @@ void __init ixdp2351_init_irq(void)
147 irq++) { 147 irq++) {
148 if (IXDP2351_INTB_IRQ_MASK(irq) & IXDP2351_INTB_IRQ_VALID) { 148 if (IXDP2351_INTB_IRQ_MASK(irq) & IXDP2351_INTB_IRQ_VALID) {
149 set_irq_flags(irq, IRQF_VALID); 149 set_irq_flags(irq, IRQF_VALID);
150 irq_set_handler(irq, handle_level_irq); 150 irq_set_chip_and_handler(irq, &ixdp2351_intb_chip,
151 irq_set_chip(irq, &ixdp2351_intb_chip); 151 handle_level_irq);
152 } 152 }
153 } 153 }
154 154
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index eca559071185..ed19bc314318 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -252,8 +252,8 @@ void __init ixp4xx_init_irq(void)
252 252
253 /* Default to all level triggered */ 253 /* Default to all level triggered */
254 for(i = 0; i < NR_IRQS; i++) { 254 for(i = 0; i < NR_IRQS; i++) {
255 irq_set_chip(i, &ixp4xx_irq_chip); 255 irq_set_chip_and_handler(i, &ixp4xx_irq_chip,
256 irq_set_handler(i, handle_level_irq); 256 handle_level_irq);
257 set_irq_flags(i, IRQF_VALID); 257 set_irq_flags(i, IRQF_VALID);
258 } 258 }
259} 259}
diff --git a/arch/arm/mach-ks8695/irq.c b/arch/arm/mach-ks8695/irq.c
index da54a5d19237..a78092dcd6fb 100644
--- a/arch/arm/mach-ks8695/irq.c
+++ b/arch/arm/mach-ks8695/irq.c
@@ -115,12 +115,12 @@ static int ks8695_irq_set_type(struct irq_data *d, unsigned int type)
115 } 115 }
116 116
117 if (level_triggered) { 117 if (level_triggered) {
118 irq_set_chip(d->irq, &ks8695_irq_level_chip); 118 irq_set_chip_and_handler(d->irq, &ks8695_irq_level_chip,
119 irq_set_handler(d->irq, handle_level_irq); 119 handle_level_irq);
120 } 120 }
121 else { 121 else {
122 irq_set_chip(d->irq, &ks8695_irq_edge_chip); 122 irq_set_chip_and_handler(d->irq, &ks8695_irq_edge_chip,
123 irq_set_handler(d->irq, handle_edge_irq); 123 handle_edge_irq);
124 } 124 }
125 125
126 __raw_writel(ctrl, KS8695_GPIO_VA + KS8695_IOPC); 126 __raw_writel(ctrl, KS8695_GPIO_VA + KS8695_IOPC);
@@ -158,16 +158,18 @@ void __init ks8695_init_irq(void)
158 case KS8695_IRQ_UART_RX: 158 case KS8695_IRQ_UART_RX:
159 case KS8695_IRQ_COMM_TX: 159 case KS8695_IRQ_COMM_TX:
160 case KS8695_IRQ_COMM_RX: 160 case KS8695_IRQ_COMM_RX:
161 irq_set_chip(irq, &ks8695_irq_level_chip); 161 irq_set_chip_and_handler(irq,
162 irq_set_handler(irq, handle_level_irq); 162 &ks8695_irq_level_chip,
163 handle_level_irq);
163 break; 164 break;
164 165
165 /* Edge-triggered interrupts */ 166 /* Edge-triggered interrupts */
166 default: 167 default:
167 /* clear pending bit */ 168 /* clear pending bit */
168 ks8695_irq_ack(irq_get_irq_data(irq)); 169 ks8695_irq_ack(irq_get_irq_data(irq));
169 irq_set_chip(irq, &ks8695_irq_edge_chip); 170 irq_set_chip_and_handler(irq,
170 irq_set_handler(irq, handle_edge_irq); 171 &ks8695_irq_edge_chip,
172 handle_edge_irq);
171 } 173 }
172 174
173 set_irq_flags(irq, IRQF_VALID); 175 set_irq_flags(irq, IRQF_VALID);
diff --git a/arch/arm/mach-lpc32xx/irq.c b/arch/arm/mach-lpc32xx/irq.c
index 3088ca328666..4eae566dfdc7 100644
--- a/arch/arm/mach-lpc32xx/irq.c
+++ b/arch/arm/mach-lpc32xx/irq.c
@@ -390,8 +390,8 @@ void __init lpc32xx_init_irq(void)
390 390
391 /* Configure supported IRQ's */ 391 /* Configure supported IRQ's */
392 for (i = 0; i < NR_IRQS; i++) { 392 for (i = 0; i < NR_IRQS; i++) {
393 irq_set_chip(i, &lpc32xx_irq_chip); 393 irq_set_chip_and_handler(i, &lpc32xx_irq_chip,
394 irq_set_handler(i, handle_level_irq); 394 handle_level_irq);
395 set_irq_flags(i, IRQF_VALID); 395 set_irq_flags(i, IRQF_VALID);
396 } 396 }
397 397
diff --git a/arch/arm/mach-mmp/irq-pxa168.c b/arch/arm/mach-mmp/irq-pxa168.c
index 6a8676205e6e..89706a0d08f1 100644
--- a/arch/arm/mach-mmp/irq-pxa168.c
+++ b/arch/arm/mach-mmp/irq-pxa168.c
@@ -48,8 +48,7 @@ void __init icu_init_irq(void)
48 48
49 for (irq = 0; irq < 64; irq++) { 49 for (irq = 0; irq < 64; irq++) {
50 icu_mask_irq(irq_get_irq_data(irq)); 50 icu_mask_irq(irq_get_irq_data(irq));
51 irq_set_chip(irq, &icu_irq_chip); 51 irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq);
52 irq_set_handler(irq, handle_level_irq);
53 set_irq_flags(irq, IRQF_VALID); 52 set_irq_flags(irq, IRQF_VALID);
54 } 53 }
55} 54}
diff --git a/arch/arm/mach-msm/board-trout-gpio.c b/arch/arm/mach-msm/board-trout-gpio.c
index ffcd4f3c63ee..87e1d01edecc 100644
--- a/arch/arm/mach-msm/board-trout-gpio.c
+++ b/arch/arm/mach-msm/board-trout-gpio.c
@@ -214,8 +214,8 @@ int __init trout_init_gpio(void)
214{ 214{
215 int i; 215 int i;
216 for(i = TROUT_INT_START; i <= TROUT_INT_END; i++) { 216 for(i = TROUT_INT_START; i <= TROUT_INT_END; i++) {
217 irq_set_chip(i, &trout_gpio_irq_chip); 217 irq_set_chip_and_handler(i, &trout_gpio_irq_chip,
218 irq_set_handler(i, handle_edge_irq); 218 handle_edge_irq);
219 set_irq_flags(i, IRQF_VALID); 219 set_irq_flags(i, IRQF_VALID);
220 } 220 }
221 221
diff --git a/arch/arm/mach-msm/gpio-v2.c b/arch/arm/mach-msm/gpio-v2.c
index 997ded1270bf..56a964e52ad3 100644
--- a/arch/arm/mach-msm/gpio-v2.c
+++ b/arch/arm/mach-msm/gpio-v2.c
@@ -362,8 +362,8 @@ static int __devinit msm_gpio_probe(struct platform_device *dev)
362 362
363 for (i = 0; i < msm_gpio.gpio_chip.ngpio; ++i) { 363 for (i = 0; i < msm_gpio.gpio_chip.ngpio; ++i) {
364 irq = msm_gpio_to_irq(&msm_gpio.gpio_chip, i); 364 irq = msm_gpio_to_irq(&msm_gpio.gpio_chip, i);
365 irq_set_chip(irq, &msm_gpio_irq_chip); 365 irq_set_chip_and_handler(irq, &msm_gpio_irq_chip,
366 irq_set_handler(irq, handle_level_irq); 366 handle_level_irq);
367 set_irq_flags(irq, IRQF_VALID); 367 set_irq_flags(irq, IRQF_VALID);
368 } 368 }
369 369
diff --git a/arch/arm/mach-msm/gpio.c b/arch/arm/mach-msm/gpio.c
index c9e0c616545c..5ea273b00da8 100644
--- a/arch/arm/mach-msm/gpio.c
+++ b/arch/arm/mach-msm/gpio.c
@@ -355,8 +355,8 @@ static int __init msm_init_gpio(void)
355 msm_gpio_chips[j].chip.ngpio) 355 msm_gpio_chips[j].chip.ngpio)
356 j++; 356 j++;
357 irq_set_chip_data(i, &msm_gpio_chips[j]); 357 irq_set_chip_data(i, &msm_gpio_chips[j]);
358 irq_set_chip(i, &msm_gpio_irq_chip); 358 irq_set_chip_and_handler(i, &msm_gpio_irq_chip,
359 irq_set_handler(i, handle_edge_irq); 359 handle_edge_irq);
360 set_irq_flags(i, IRQF_VALID); 360 set_irq_flags(i, IRQF_VALID);
361 } 361 }
362 362
diff --git a/arch/arm/mach-msm/irq-vic.c b/arch/arm/mach-msm/irq-vic.c
index 7a805bec32af..1b54f807c2d0 100644
--- a/arch/arm/mach-msm/irq-vic.c
+++ b/arch/arm/mach-msm/irq-vic.c
@@ -357,8 +357,7 @@ void __init msm_init_irq(void)
357 writel(3, VIC_INT_MASTEREN); 357 writel(3, VIC_INT_MASTEREN);
358 358
359 for (n = 0; n < NR_MSM_IRQS; n++) { 359 for (n = 0; n < NR_MSM_IRQS; n++) {
360 irq_set_chip(n, &msm_irq_chip); 360 irq_set_chip_and_handler(n, &msm_irq_chip, handle_level_irq);
361 irq_set_handler(n, handle_level_irq);
362 set_irq_flags(n, IRQF_VALID); 361 set_irq_flags(n, IRQF_VALID);
363 } 362 }
364} 363}
diff --git a/arch/arm/mach-msm/irq.c b/arch/arm/mach-msm/irq.c
index 782e8054539e..ea514be390c6 100644
--- a/arch/arm/mach-msm/irq.c
+++ b/arch/arm/mach-msm/irq.c
@@ -145,8 +145,7 @@ void __init msm_init_irq(void)
145 writel(1, VIC_INT_MASTEREN); 145 writel(1, VIC_INT_MASTEREN);
146 146
147 for (n = 0; n < NR_MSM_IRQS; n++) { 147 for (n = 0; n < NR_MSM_IRQS; n++) {
148 irq_set_chip(n, &msm_irq_chip); 148 irq_set_chip_and_handler(n, &msm_irq_chip, handle_level_irq);
149 irq_set_handler(n, handle_level_irq);
150 set_irq_flags(n, IRQF_VALID); 149 set_irq_flags(n, IRQF_VALID);
151 } 150 }
152} 151}
diff --git a/arch/arm/mach-msm/sirc.c b/arch/arm/mach-msm/sirc.c
index 276f91899ff3..689e78c95f38 100644
--- a/arch/arm/mach-msm/sirc.c
+++ b/arch/arm/mach-msm/sirc.c
@@ -158,8 +158,7 @@ void __init msm_init_sirc(void)
158 wake_enable = 0; 158 wake_enable = 0;
159 159
160 for (i = FIRST_SIRC_IRQ; i < LAST_SIRC_IRQ; i++) { 160 for (i = FIRST_SIRC_IRQ; i < LAST_SIRC_IRQ; i++) {
161 irq_set_chip(i, &sirc_irq_chip); 161 irq_set_chip_and_handler(i, &sirc_irq_chip, handle_edge_irq);
162 irq_set_handler(i, handle_edge_irq);
163 set_irq_flags(i, IRQF_VALID); 162 set_irq_flags(i, IRQF_VALID);
164 } 163 }
165 164
diff --git a/arch/arm/mach-mx3/mach-mx31ads.c b/arch/arm/mach-mx3/mach-mx31ads.c
index de494525ec7e..3d095d69bc68 100644
--- a/arch/arm/mach-mx3/mach-mx31ads.c
+++ b/arch/arm/mach-mx3/mach-mx31ads.c
@@ -199,8 +199,7 @@ static void __init mx31ads_init_expio(void)
199 __raw_writew(0xFFFF, PBC_INTSTATUS_REG); 199 __raw_writew(0xFFFF, PBC_INTSTATUS_REG);
200 for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); 200 for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
201 i++) { 201 i++) {
202 irq_set_chip(i, &expio_irq_chip); 202 irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq);
203 irq_set_handler(i, handle_level_irq);
204 set_irq_flags(i, IRQF_VALID); 203 set_irq_flags(i, IRQF_VALID);
205 } 204 }
206 irq_set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_HIGH); 205 irq_set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_HIGH);
diff --git a/arch/arm/mach-mxs/gpio.c b/arch/arm/mach-mxs/gpio.c
index a1e01dd4a4ff..2c950fef71a8 100644
--- a/arch/arm/mach-mxs/gpio.c
+++ b/arch/arm/mach-mxs/gpio.c
@@ -265,8 +265,8 @@ int __init mxs_gpio_init(struct mxs_gpio_port *port, int cnt)
265 265
266 for (j = port[i].virtual_irq_start; 266 for (j = port[i].virtual_irq_start;
267 j < port[i].virtual_irq_start + 32; j++) { 267 j < port[i].virtual_irq_start + 32; j++) {
268 irq_set_chip(j, &gpio_irq_chip); 268 irq_set_chip_and_handler(j, &gpio_irq_chip,
269 irq_set_handler(j, handle_level_irq); 269 handle_level_irq);
270 set_irq_flags(j, IRQF_VALID); 270 set_irq_flags(j, IRQF_VALID);
271 } 271 }
272 272
diff --git a/arch/arm/mach-mxs/icoll.c b/arch/arm/mach-mxs/icoll.c
index ae8a0d98f995..23ca9d083b2c 100644
--- a/arch/arm/mach-mxs/icoll.c
+++ b/arch/arm/mach-mxs/icoll.c
@@ -74,8 +74,7 @@ void __init icoll_init_irq(void)
74 mxs_reset_block(icoll_base + HW_ICOLL_CTRL); 74 mxs_reset_block(icoll_base + HW_ICOLL_CTRL);
75 75
76 for (i = 0; i < MXS_INTERNAL_IRQS; i++) { 76 for (i = 0; i < MXS_INTERNAL_IRQS; i++) {
77 irq_set_chip(i, &mxs_icoll_chip); 77 irq_set_chip_and_handler(i, &mxs_icoll_chip, handle_level_irq);
78 irq_set_handler(i, handle_level_irq);
79 set_irq_flags(i, IRQF_VALID); 78 set_irq_flags(i, IRQF_VALID);
80 } 79 }
81} 80}
diff --git a/arch/arm/mach-netx/generic.c b/arch/arm/mach-netx/generic.c
index 783e327892dc..00023b5cf12b 100644
--- a/arch/arm/mach-netx/generic.c
+++ b/arch/arm/mach-netx/generic.c
@@ -171,8 +171,8 @@ void __init netx_init_irq(void)
171 vic_init(__io(io_p2v(NETX_PA_VIC)), 0, ~0, 0); 171 vic_init(__io(io_p2v(NETX_PA_VIC)), 0, ~0, 0);
172 172
173 for (irq = NETX_IRQ_HIF_CHAINED(0); irq <= NETX_IRQ_HIF_LAST; irq++) { 173 for (irq = NETX_IRQ_HIF_CHAINED(0); irq <= NETX_IRQ_HIF_LAST; irq++) {
174 irq_set_chip(irq, &netx_hif_chip); 174 irq_set_chip_and_handler(irq, &netx_hif_chip,
175 irq_set_handler(irq, handle_level_irq); 175 handle_level_irq);
176 set_irq_flags(irq, IRQF_VALID); 176 set_irq_flags(irq, IRQF_VALID);
177 } 177 }
178 178
diff --git a/arch/arm/mach-ns9xxx/board-a9m9750dev.c b/arch/arm/mach-ns9xxx/board-a9m9750dev.c
index 7e29e4ae03ee..e27687d53504 100644
--- a/arch/arm/mach-ns9xxx/board-a9m9750dev.c
+++ b/arch/arm/mach-ns9xxx/board-a9m9750dev.c
@@ -107,8 +107,8 @@ void __init board_a9m9750dev_init_irq(void)
107 __func__); 107 __func__);
108 108
109 for (i = FPGA_IRQ(0); i <= FPGA_IRQ(7); ++i) { 109 for (i = FPGA_IRQ(0); i <= FPGA_IRQ(7); ++i) {
110 irq_set_chip(i, &a9m9750dev_fpga_chip); 110 irq_set_chip_and_handler(i, &a9m9750dev_fpga_chip,
111 irq_set_handler(i, handle_level_irq); 111 handle_level_irq);
112 set_irq_flags(i, IRQF_VALID); 112 set_irq_flags(i, IRQF_VALID);
113 } 113 }
114 114
diff --git a/arch/arm/mach-ns9xxx/irq.c b/arch/arm/mach-ns9xxx/irq.c
index 14997e9fdb7a..37ab0a2b83ad 100644
--- a/arch/arm/mach-ns9xxx/irq.c
+++ b/arch/arm/mach-ns9xxx/irq.c
@@ -67,8 +67,7 @@ void __init ns9xxx_init_irq(void)
67 __raw_writel(prio2irq(i), SYS_IVA(i)); 67 __raw_writel(prio2irq(i), SYS_IVA(i));
68 68
69 for (i = 0; i <= 31; ++i) { 69 for (i = 0; i <= 31; ++i) {
70 irq_set_chip(i, &ns9xxx_chip); 70 irq_set_chip_and_handler(i, &ns9xxx_chip, handle_fasteoi_irq);
71 irq_set_handler(i, handle_fasteoi_irq);
72 set_irq_flags(i, IRQF_VALID); 71 set_irq_flags(i, IRQF_VALID);
73 irq_set_status_flags(i, IRQ_LEVEL); 72 irq_set_status_flags(i, IRQ_LEVEL);
74 } 73 }
diff --git a/arch/arm/mach-nuc93x/irq.c b/arch/arm/mach-nuc93x/irq.c
index fcf1212d9706..aa279f23e342 100644
--- a/arch/arm/mach-nuc93x/irq.c
+++ b/arch/arm/mach-nuc93x/irq.c
@@ -59,8 +59,8 @@ void __init nuc93x_init_irq(void)
59 __raw_writel(0xFFFFFFFE, REG_AIC_MDCR); 59 __raw_writel(0xFFFFFFFE, REG_AIC_MDCR);
60 60
61 for (irqno = IRQ_WDT; irqno <= NR_IRQS; irqno++) { 61 for (irqno = IRQ_WDT; irqno <= NR_IRQS; irqno++) {
62 irq_set_chip(irqno, &nuc93x_irq_chip); 62 irq_set_chip_and_handler(irqno, &nuc93x_irq_chip,
63 irq_set_handler(irqno, handle_level_irq); 63 handle_level_irq);
64 set_irq_flags(irqno, IRQF_VALID); 64 set_irq_flags(irqno, IRQF_VALID);
65 } 65 }
66} 66}
diff --git a/arch/arm/mach-omap1/irq.c b/arch/arm/mach-omap1/irq.c
index 53dbb5d7efdc..5d3da7a63af3 100644
--- a/arch/arm/mach-omap1/irq.c
+++ b/arch/arm/mach-omap1/irq.c
@@ -230,8 +230,8 @@ void __init omap_init_irq(void)
230 irq_trigger = irq_banks[i].trigger_map >> IRQ_BIT(j); 230 irq_trigger = irq_banks[i].trigger_map >> IRQ_BIT(j);
231 omap_irq_set_cfg(j, 0, 0, irq_trigger); 231 omap_irq_set_cfg(j, 0, 0, irq_trigger);
232 232
233 irq_set_chip(j, &omap_irq_chip); 233 irq_set_chip_and_handler(j, &omap_irq_chip,
234 irq_set_handler(j, handle_level_irq); 234 handle_level_irq);
235 set_irq_flags(j, IRQF_VALID); 235 set_irq_flags(j, IRQF_VALID);
236 } 236 }
237 } 237 }
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 4fff5e3270d8..237e4530abf2 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -223,8 +223,7 @@ void __init omap_init_irq(void)
223 nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : ""); 223 nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
224 224
225 for (i = 0; i < nr_of_irqs; i++) { 225 for (i = 0; i < nr_of_irqs; i++) {
226 irq_set_chip(i, &omap_irq_chip); 226 irq_set_chip_and_handler(i, &omap_irq_chip, handle_level_irq);
227 irq_set_handler(i, handle_level_irq);
228 set_irq_flags(i, IRQF_VALID); 227 set_irq_flags(i, IRQF_VALID);
229 } 228 }
230} 229}
diff --git a/arch/arm/mach-pxa/balloon3.c b/arch/arm/mach-pxa/balloon3.c
index a773b730e432..38dea05df7f8 100644
--- a/arch/arm/mach-pxa/balloon3.c
+++ b/arch/arm/mach-pxa/balloon3.c
@@ -527,8 +527,8 @@ static void __init balloon3_init_irq(void)
527 pxa27x_init_irq(); 527 pxa27x_init_irq();
528 /* setup extra Balloon3 irqs */ 528 /* setup extra Balloon3 irqs */
529 for (irq = BALLOON3_IRQ(0); irq <= BALLOON3_IRQ(7); irq++) { 529 for (irq = BALLOON3_IRQ(0); irq <= BALLOON3_IRQ(7); irq++) {
530 irq_set_chip(irq, &balloon3_irq_chip); 530 irq_set_chip_and_handler(irq, &balloon3_irq_chip,
531 irq_set_handler(irq, handle_level_irq); 531 handle_level_irq);
532 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 532 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
533 } 533 }
534 534
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c
index 70344cc75743..6251e3f5c62c 100644
--- a/arch/arm/mach-pxa/irq.c
+++ b/arch/arm/mach-pxa/irq.c
@@ -137,8 +137,8 @@ static void __init pxa_init_low_gpio_irq(set_wake_t fn)
137 GEDR0 = 0x3; 137 GEDR0 = 0x3;
138 138
139 for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) { 139 for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) {
140 irq_set_chip(irq, &pxa_low_gpio_chip); 140 irq_set_chip_and_handler(irq, &pxa_low_gpio_chip,
141 irq_set_handler(irq, handle_edge_irq); 141 handle_edge_irq);
142 irq_set_chip_data(irq, irq_base(0)); 142 irq_set_chip_data(irq, irq_base(0));
143 set_irq_flags(irq, IRQF_VALID); 143 set_irq_flags(irq, IRQF_VALID);
144 } 144 }
@@ -165,8 +165,8 @@ void __init pxa_init_irq(int irq_nr, set_wake_t fn)
165 __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i)); 165 __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i));
166 166
167 irq = PXA_IRQ(i); 167 irq = PXA_IRQ(i);
168 irq_set_chip(irq, &pxa_internal_irq_chip); 168 irq_set_chip_and_handler(irq, &pxa_internal_irq_chip,
169 irq_set_handler(irq, handle_level_irq); 169 handle_level_irq);
170 irq_set_chip_data(irq, base); 170 irq_set_chip_data(irq, base);
171 set_irq_flags(irq, IRQF_VALID); 171 set_irq_flags(irq, IRQF_VALID);
172 } 172 }
diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c
index a1b094223e31..6307f70ae22a 100644
--- a/arch/arm/mach-pxa/lpd270.c
+++ b/arch/arm/mach-pxa/lpd270.c
@@ -149,8 +149,8 @@ static void __init lpd270_init_irq(void)
149 149
150 /* setup extra LogicPD PXA270 irqs */ 150 /* setup extra LogicPD PXA270 irqs */
151 for (irq = LPD270_IRQ(2); irq <= LPD270_IRQ(4); irq++) { 151 for (irq = LPD270_IRQ(2); irq <= LPD270_IRQ(4); irq++) {
152 irq_set_chip(irq, &lpd270_irq_chip); 152 irq_set_chip_and_handler(irq, &lpd270_irq_chip,
153 irq_set_handler(irq, handle_level_irq); 153 handle_level_irq);
154 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 154 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
155 } 155 }
156 irq_set_chained_handler(IRQ_GPIO(0), lpd270_irq_handler); 156 irq_set_chained_handler(IRQ_GPIO(0), lpd270_irq_handler);
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c
index 061d01b50094..0fea945dd6f2 100644
--- a/arch/arm/mach-pxa/lubbock.c
+++ b/arch/arm/mach-pxa/lubbock.c
@@ -165,8 +165,8 @@ static void __init lubbock_init_irq(void)
165 165
166 /* setup extra lubbock irqs */ 166 /* setup extra lubbock irqs */
167 for (irq = LUBBOCK_IRQ(0); irq <= LUBBOCK_LAST_IRQ; irq++) { 167 for (irq = LUBBOCK_IRQ(0); irq <= LUBBOCK_LAST_IRQ; irq++) {
168 irq_set_chip(irq, &lubbock_irq_chip); 168 irq_set_chip_and_handler(irq, &lubbock_irq_chip,
169 irq_set_handler(irq, handle_level_irq); 169 handle_level_irq);
170 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 170 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
171 } 171 }
172 172
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index 9ee703225ab8..29b6e7a94e11 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -166,8 +166,8 @@ static void __init mainstone_init_irq(void)
166 166
167 /* setup extra Mainstone irqs */ 167 /* setup extra Mainstone irqs */
168 for(irq = MAINSTONE_IRQ(0); irq <= MAINSTONE_IRQ(15); irq++) { 168 for(irq = MAINSTONE_IRQ(0); irq <= MAINSTONE_IRQ(15); irq++) {
169 irq_set_chip(irq, &mainstone_irq_chip); 169 irq_set_chip_and_handler(irq, &mainstone_irq_chip,
170 irq_set_handler(irq, handle_level_irq); 170 handle_level_irq);
171 if (irq == MAINSTONE_IRQ(10) || irq == MAINSTONE_IRQ(14)) 171 if (irq == MAINSTONE_IRQ(10) || irq == MAINSTONE_IRQ(14))
172 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN); 172 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN);
173 else 173 else
diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c
index 6c02b589d143..4d0120540124 100644
--- a/arch/arm/mach-pxa/pcm990-baseboard.c
+++ b/arch/arm/mach-pxa/pcm990-baseboard.c
@@ -281,8 +281,8 @@ static void __init pcm990_init_irq(void)
281 281
282 /* setup extra PCM990 irqs */ 282 /* setup extra PCM990 irqs */
283 for (irq = PCM027_IRQ(0); irq <= PCM027_IRQ(3); irq++) { 283 for (irq = PCM027_IRQ(0); irq <= PCM027_IRQ(3); irq++) {
284 irq_set_chip(irq, &pcm990_irq_chip); 284 irq_set_chip_and_handler(irq, &pcm990_irq_chip,
285 irq_set_handler(irq, handle_level_irq); 285 handle_level_irq);
286 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 286 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
287 } 287 }
288 288
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index 8abe93f4e519..8dd107391157 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -362,8 +362,8 @@ static void __init pxa_init_ext_wakeup_irq(set_wake_t fn)
362 int irq; 362 int irq;
363 363
364 for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) { 364 for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) {
365 irq_set_chip(irq, &pxa_ext_wakeup_chip); 365 irq_set_chip_and_handler(irq, &pxa_ext_wakeup_chip,
366 irq_set_handler(irq, handle_edge_irq); 366 handle_edge_irq);
367 set_irq_flags(irq, IRQF_VALID); 367 set_irq_flags(irq, IRQF_VALID);
368 } 368 }
369 369
diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c
index 26facf1cef65..aa70331c0805 100644
--- a/arch/arm/mach-pxa/viper.c
+++ b/arch/arm/mach-pxa/viper.c
@@ -310,8 +310,8 @@ static void __init viper_init_irq(void)
310 /* setup ISA IRQs */ 310 /* setup ISA IRQs */
311 for (level = 0; level < ARRAY_SIZE(viper_isa_irqs); level++) { 311 for (level = 0; level < ARRAY_SIZE(viper_isa_irqs); level++) {
312 isa_irq = viper_bit_to_irq(level); 312 isa_irq = viper_bit_to_irq(level);
313 irq_set_chip(isa_irq, &viper_irq_chip); 313 irq_set_chip_and_handler(isa_irq, &viper_irq_chip,
314 irq_set_handler(isa_irq, handle_edge_irq); 314 handle_edge_irq);
315 set_irq_flags(isa_irq, IRQF_VALID | IRQF_PROBE); 315 set_irq_flags(isa_irq, IRQF_VALID | IRQF_PROBE);
316 } 316 }
317 317
diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c
index a7cdc4a83d40..139aa7f2ed90 100644
--- a/arch/arm/mach-pxa/zeus.c
+++ b/arch/arm/mach-pxa/zeus.c
@@ -146,8 +146,8 @@ static void __init zeus_init_irq(void)
146 /* Setup ISA IRQs */ 146 /* Setup ISA IRQs */
147 for (level = 0; level < ARRAY_SIZE(zeus_isa_irqs); level++) { 147 for (level = 0; level < ARRAY_SIZE(zeus_isa_irqs); level++) {
148 isa_irq = zeus_bit_to_irq(level); 148 isa_irq = zeus_bit_to_irq(level);
149 irq_set_chip(isa_irq, &zeus_irq_chip); 149 irq_set_chip_and_handler(isa_irq, &zeus_irq_chip,
150 irq_set_handler(isa_irq, handle_edge_irq); 150 handle_edge_irq);
151 set_irq_flags(isa_irq, IRQF_VALID | IRQF_PROBE); 151 set_irq_flags(isa_irq, IRQF_VALID | IRQF_PROBE);
152 } 152 }
153 153
diff --git a/arch/arm/mach-rpc/irq.c b/arch/arm/mach-rpc/irq.c
index 49fb9886f56c..2e1b5309fbab 100644
--- a/arch/arm/mach-rpc/irq.c
+++ b/arch/arm/mach-rpc/irq.c
@@ -133,20 +133,20 @@ void __init rpc_init_irq(void)
133 133
134 switch (irq) { 134 switch (irq) {
135 case 0 ... 7: 135 case 0 ... 7:
136 irq_set_chip(irq, &iomd_a_chip); 136 irq_set_chip_and_handler(irq, &iomd_a_chip,
137 irq_set_handler(irq, handle_level_irq); 137 handle_level_irq);
138 set_irq_flags(irq, flags); 138 set_irq_flags(irq, flags);
139 break; 139 break;
140 140
141 case 8 ... 15: 141 case 8 ... 15:
142 irq_set_chip(irq, &iomd_b_chip); 142 irq_set_chip_and_handler(irq, &iomd_b_chip,
143 irq_set_handler(irq, handle_level_irq); 143 handle_level_irq);
144 set_irq_flags(irq, flags); 144 set_irq_flags(irq, flags);
145 break; 145 break;
146 146
147 case 16 ... 21: 147 case 16 ... 21:
148 irq_set_chip(irq, &iomd_dma_chip); 148 irq_set_chip_and_handler(irq, &iomd_dma_chip,
149 irq_set_handler(irq, handle_level_irq); 149 handle_level_irq);
150 set_irq_flags(irq, flags); 150 set_irq_flags(irq, flags);
151 break; 151 break;
152 152
diff --git a/arch/arm/mach-s3c2410/bast-irq.c b/arch/arm/mach-s3c2410/bast-irq.c
index 4139f5f0b418..bc53d2d16d1a 100644
--- a/arch/arm/mach-s3c2410/bast-irq.c
+++ b/arch/arm/mach-s3c2410/bast-irq.c
@@ -154,8 +154,8 @@ static __init int bast_irq_init(void)
154 for (i = 0; i < 4; i++) { 154 for (i = 0; i < 4; i++) {
155 unsigned int irqno = bast_pc104_irqs[i]; 155 unsigned int irqno = bast_pc104_irqs[i];
156 156
157 irq_set_chip(irqno, &bast_pc104_chip); 157 irq_set_chip_and_handler(irqno, &bast_pc104_chip,
158 irq_set_handler(irqno, handle_level_irq); 158 handle_level_irq);
159 set_irq_flags(irqno, IRQF_VALID); 159 set_irq_flags(irqno, IRQF_VALID);
160 } 160 }
161 } 161 }
diff --git a/arch/arm/mach-s3c2412/irq.c b/arch/arm/mach-s3c2412/irq.c
index 30f79ae03289..f3355d2ec634 100644
--- a/arch/arm/mach-s3c2412/irq.c
+++ b/arch/arm/mach-s3c2412/irq.c
@@ -175,8 +175,8 @@ static int s3c2412_irq_add(struct sys_device *sysdev)
175 unsigned int irqno; 175 unsigned int irqno;
176 176
177 for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) { 177 for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
178 irq_set_chip(irqno, &s3c2412_irq_eint0t4); 178 irq_set_chip_and_handler(irqno, &s3c2412_irq_eint0t4,
179 irq_set_handler(irqno, handle_edge_irq); 179 handle_edge_irq);
180 set_irq_flags(irqno, IRQF_VALID); 180 set_irq_flags(irqno, IRQF_VALID);
181 } 181 }
182 182
@@ -185,8 +185,8 @@ static int s3c2412_irq_add(struct sys_device *sysdev)
185 irq_set_chained_handler(IRQ_S3C2412_CFSDI, s3c2412_irq_demux_cfsdi); 185 irq_set_chained_handler(IRQ_S3C2412_CFSDI, s3c2412_irq_demux_cfsdi);
186 186
187 for (irqno = IRQ_S3C2412_SDI; irqno <= IRQ_S3C2412_CF; irqno++) { 187 for (irqno = IRQ_S3C2412_SDI; irqno <= IRQ_S3C2412_CF; irqno++) {
188 irq_set_chip(irqno, &s3c2412_irq_cfsdi); 188 irq_set_chip_and_handler(irqno, &s3c2412_irq_cfsdi,
189 irq_set_handler(irqno, handle_level_irq); 189 handle_level_irq);
190 set_irq_flags(irqno, IRQF_VALID); 190 set_irq_flags(irqno, IRQF_VALID);
191 } 191 }
192 192
diff --git a/arch/arm/mach-s3c2416/irq.c b/arch/arm/mach-s3c2416/irq.c
index de21c841b56d..77b38f2381c1 100644
--- a/arch/arm/mach-s3c2416/irq.c
+++ b/arch/arm/mach-s3c2416/irq.c
@@ -202,13 +202,11 @@ static int __init s3c2416_add_sub(unsigned int base,
202{ 202{
203 unsigned int irqno; 203 unsigned int irqno;
204 204
205 irq_set_chip(base, &s3c_irq_level_chip); 205 irq_set_chip_and_handler(base, &s3c_irq_level_chip, handle_level_irq);
206 irq_set_handler(base, handle_level_irq);
207 irq_set_chained_handler(base, demux); 206 irq_set_chained_handler(base, demux);
208 207
209 for (irqno = start; irqno <= end; irqno++) { 208 for (irqno = start; irqno <= end; irqno++) {
210 irq_set_chip(irqno, chip); 209 irq_set_chip_and_handler(irqno, chip, handle_level_irq);
211 irq_set_handler(irqno, handle_level_irq);
212 set_irq_flags(irqno, IRQF_VALID); 210 set_irq_flags(irqno, IRQF_VALID);
213 } 211 }
214 212
diff --git a/arch/arm/mach-s3c2440/irq.c b/arch/arm/mach-s3c2440/irq.c
index 0c564b149a46..eb1cc0f0705e 100644
--- a/arch/arm/mach-s3c2440/irq.c
+++ b/arch/arm/mach-s3c2440/irq.c
@@ -100,13 +100,13 @@ static int s3c2440_irq_add(struct sys_device *sysdev)
100 100
101 /* add new chained handler for wdt, ac7 */ 101 /* add new chained handler for wdt, ac7 */
102 102
103 irq_set_chip(IRQ_WDT, &s3c_irq_level_chip); 103 irq_set_chip_and_handler(IRQ_WDT, &s3c_irq_level_chip,
104 irq_set_handler(IRQ_WDT, handle_level_irq); 104 handle_level_irq);
105 irq_set_chained_handler(IRQ_WDT, s3c_irq_demux_wdtac97); 105 irq_set_chained_handler(IRQ_WDT, s3c_irq_demux_wdtac97);
106 106
107 for (irqno = IRQ_S3C2440_WDT; irqno <= IRQ_S3C2440_AC97; irqno++) { 107 for (irqno = IRQ_S3C2440_WDT; irqno <= IRQ_S3C2440_AC97; irqno++) {
108 irq_set_chip(irqno, &s3c_irq_wdtac97); 108 irq_set_chip_and_handler(irqno, &s3c_irq_wdtac97,
109 irq_set_handler(irqno, handle_level_irq); 109 handle_level_irq);
110 set_irq_flags(irqno, IRQF_VALID); 110 set_irq_flags(irqno, IRQF_VALID);
111 } 111 }
112 112
diff --git a/arch/arm/mach-s3c2440/s3c244x-irq.c b/arch/arm/mach-s3c2440/s3c244x-irq.c
index 5a48881c4508..de07c2feaa32 100644
--- a/arch/arm/mach-s3c2440/s3c244x-irq.c
+++ b/arch/arm/mach-s3c2440/s3c244x-irq.c
@@ -95,19 +95,19 @@ static int s3c244x_irq_add(struct sys_device *sysdev)
95{ 95{
96 unsigned int irqno; 96 unsigned int irqno;
97 97
98 irq_set_chip(IRQ_NFCON, &s3c_irq_level_chip); 98 irq_set_chip_and_handler(IRQ_NFCON, &s3c_irq_level_chip,
99 irq_set_handler(IRQ_NFCON, handle_level_irq); 99 handle_level_irq);
100 set_irq_flags(IRQ_NFCON, IRQF_VALID); 100 set_irq_flags(IRQ_NFCON, IRQF_VALID);
101 101
102 /* add chained handler for camera */ 102 /* add chained handler for camera */
103 103
104 irq_set_chip(IRQ_CAM, &s3c_irq_level_chip); 104 irq_set_chip_and_handler(IRQ_CAM, &s3c_irq_level_chip,
105 irq_set_handler(IRQ_CAM, handle_level_irq); 105 handle_level_irq);
106 irq_set_chained_handler(IRQ_CAM, s3c_irq_demux_cam); 106 irq_set_chained_handler(IRQ_CAM, s3c_irq_demux_cam);
107 107
108 for (irqno = IRQ_S3C2440_CAM_C; irqno <= IRQ_S3C2440_CAM_P; irqno++) { 108 for (irqno = IRQ_S3C2440_CAM_C; irqno <= IRQ_S3C2440_CAM_P; irqno++) {
109 irq_set_chip(irqno, &s3c_irq_cam); 109 irq_set_chip_and_handler(irqno, &s3c_irq_cam,
110 irq_set_handler(irqno, handle_level_irq); 110 handle_level_irq);
111 set_irq_flags(irqno, IRQF_VALID); 111 set_irq_flags(irqno, IRQF_VALID);
112 } 112 }
113 113
diff --git a/arch/arm/mach-s3c2443/irq.c b/arch/arm/mach-s3c2443/irq.c
index b12431fae263..83ecb1173fb1 100644
--- a/arch/arm/mach-s3c2443/irq.c
+++ b/arch/arm/mach-s3c2443/irq.c
@@ -230,13 +230,11 @@ static int __init s3c2443_add_sub(unsigned int base,
230{ 230{
231 unsigned int irqno; 231 unsigned int irqno;
232 232
233 irq_set_chip(base, &s3c_irq_level_chip); 233 irq_set_chip_and_handler(base, &s3c_irq_level_chip, handle_level_irq);
234 irq_set_handler(base, handle_level_irq);
235 irq_set_chained_handler(base, demux); 234 irq_set_chained_handler(base, demux);
236 235
237 for (irqno = start; irqno <= end; irqno++) { 236 for (irqno = start; irqno <= end; irqno++) {
238 irq_set_chip(irqno, chip); 237 irq_set_chip_and_handler(irqno, chip, handle_level_irq);
239 irq_set_handler(irqno, handle_level_irq);
240 set_irq_flags(irqno, IRQF_VALID); 238 set_irq_flags(irqno, IRQF_VALID);
241 } 239 }
242 240
diff --git a/arch/arm/mach-s3c64xx/irq-eint.c b/arch/arm/mach-s3c64xx/irq-eint.c
index 6d703487cb8c..4d203be1f4c3 100644
--- a/arch/arm/mach-s3c64xx/irq-eint.c
+++ b/arch/arm/mach-s3c64xx/irq-eint.c
@@ -197,8 +197,7 @@ static int __init s3c64xx_init_irq_eint(void)
197 int irq; 197 int irq;
198 198
199 for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) { 199 for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) {
200 irq_set_chip(irq, &s3c_irq_eint); 200 irq_set_chip_and_handler(irq, &s3c_irq_eint, handle_level_irq);
201 irq_set_handler(irq, handle_level_irq);
202 irq_set_chip_data(irq, (void *)eint_irq_to_bit(irq)); 201 irq_set_chip_data(irq, (void *)eint_irq_to_bit(irq));
203 set_irq_flags(irq, IRQF_VALID); 202 set_irq_flags(irq, IRQF_VALID);
204 } 203 }
diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c
index 0f109e179cbb..423ddb3d65e9 100644
--- a/arch/arm/mach-sa1100/irq.c
+++ b/arch/arm/mach-sa1100/irq.c
@@ -323,20 +323,20 @@ void __init sa1100_init_irq(void)
323 ICCR = 1; 323 ICCR = 1;
324 324
325 for (irq = 0; irq <= 10; irq++) { 325 for (irq = 0; irq <= 10; irq++) {
326 irq_set_chip(irq, &sa1100_low_gpio_chip); 326 irq_set_chip_and_handler(irq, &sa1100_low_gpio_chip,
327 irq_set_handler(irq, handle_edge_irq); 327 handle_edge_irq);
328 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 328 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
329 } 329 }
330 330
331 for (irq = 12; irq <= 31; irq++) { 331 for (irq = 12; irq <= 31; irq++) {
332 irq_set_chip(irq, &sa1100_normal_chip); 332 irq_set_chip_and_handler(irq, &sa1100_normal_chip,
333 irq_set_handler(irq, handle_level_irq); 333 handle_level_irq);
334 set_irq_flags(irq, IRQF_VALID); 334 set_irq_flags(irq, IRQF_VALID);
335 } 335 }
336 336
337 for (irq = 32; irq <= 48; irq++) { 337 for (irq = 32; irq <= 48; irq++) {
338 irq_set_chip(irq, &sa1100_high_gpio_chip); 338 irq_set_chip_and_handler(irq, &sa1100_high_gpio_chip,
339 irq_set_handler(irq, handle_edge_irq); 339 handle_edge_irq);
340 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 340 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
341 } 341 }
342 342
diff --git a/arch/arm/mach-shark/irq.c b/arch/arm/mach-shark/irq.c
index 2e6da5fe1859..5dce13e429f3 100644
--- a/arch/arm/mach-shark/irq.c
+++ b/arch/arm/mach-shark/irq.c
@@ -80,8 +80,7 @@ void __init shark_init_irq(void)
80 int irq; 80 int irq;
81 81
82 for (irq = 0; irq < NR_IRQS; irq++) { 82 for (irq = 0; irq < NR_IRQS; irq++) {
83 irq_set_chip(irq, &fb_chip); 83 irq_set_chip_and_handler(irq, &fb_chip, handle_edge_irq);
84 irq_set_handler(irq, handle_edge_irq);
85 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 84 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
86 } 85 }
87 86
diff --git a/arch/arm/mach-tegra/gpio.c b/arch/arm/mach-tegra/gpio.c
index 4148048c4191..76a3f654220f 100644
--- a/arch/arm/mach-tegra/gpio.c
+++ b/arch/arm/mach-tegra/gpio.c
@@ -342,8 +342,8 @@ static int __init tegra_gpio_init(void)
342 342
343 irq_set_lockdep_class(i, &gpio_lock_class); 343 irq_set_lockdep_class(i, &gpio_lock_class);
344 irq_set_chip_data(i, bank); 344 irq_set_chip_data(i, bank);
345 irq_set_chip(i, &tegra_gpio_irq_chip); 345 irq_set_chip_and_handler(i, &tegra_gpio_irq_chip,
346 irq_set_handler(i, handle_simple_irq); 346 handle_simple_irq);
347 set_irq_flags(i, IRQF_VALID); 347 set_irq_flags(i, IRQF_VALID);
348 } 348 }
349 349
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index 6b5c8b8abe02..4330d8995b27 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -154,8 +154,7 @@ void __init tegra_init_irq(void)
154 154
155 for (i = 0; i < INT_MAIN_NR; i++) { 155 for (i = 0; i < INT_MAIN_NR; i++) {
156 irq = INT_PRI_BASE + i; 156 irq = INT_PRI_BASE + i;
157 irq_set_chip(irq, &tegra_irq); 157 irq_set_chip_and_handler(irq, &tegra_irq, handle_level_irq);
158 irq_set_handler(irq, handle_level_irq);
159 set_irq_flags(irq, IRQF_VALID); 158 set_irq_flags(irq, IRQF_VALID);
160 } 159 }
161} 160}
diff --git a/arch/arm/mach-ux500/modem-irq-db5500.c b/arch/arm/mach-ux500/modem-irq-db5500.c
index 5f2322e6c108..6b86416c94c9 100644
--- a/arch/arm/mach-ux500/modem-irq-db5500.c
+++ b/arch/arm/mach-ux500/modem-irq-db5500.c
@@ -90,8 +90,7 @@ static irqreturn_t modem_cpu_irq_handler(int irq, void *data)
90 90
91static void create_virtual_irq(int irq, struct irq_chip *modem_irq_chip) 91static void create_virtual_irq(int irq, struct irq_chip *modem_irq_chip)
92{ 92{
93 irq_set_chip(irq, modem_irq_chip); 93 irq_set_chip_and_handler(irq, modem_irq_chip, handle_simple_irq);
94 irq_set_handler(irq, handle_simple_irq);
95 set_irq_flags(irq, IRQF_VALID); 94 set_irq_flags(irq, IRQF_VALID);
96 95
97 pr_debug("modem_irq: Created virtual IRQ %d\n", irq); 96 pr_debug("modem_irq: Created virtual IRQ %d\n", irq);
diff --git a/arch/arm/mach-vt8500/irq.c b/arch/arm/mach-vt8500/irq.c
index e495c014fefd..245140c0df10 100644
--- a/arch/arm/mach-vt8500/irq.c
+++ b/arch/arm/mach-vt8500/irq.c
@@ -136,8 +136,8 @@ void __init vt8500_init_irq(void)
136 /* Disable all interrupts and route them to IRQ */ 136 /* Disable all interrupts and route them to IRQ */
137 writeb(0x00, ic_regbase + VT8500_IC_DCTR + i); 137 writeb(0x00, ic_regbase + VT8500_IC_DCTR + i);
138 138
139 irq_set_chip(i, &vt8500_irq_chip); 139 irq_set_chip_and_handler(i, &vt8500_irq_chip,
140 irq_set_handler(i, handle_level_irq); 140 handle_level_irq);
141 set_irq_flags(i, IRQF_VALID); 141 set_irq_flags(i, IRQF_VALID);
142 } 142 }
143 } else { 143 } else {
@@ -167,8 +167,8 @@ void __init wm8505_init_irq(void)
167 writeb(0x00, sic_regbase + VT8500_IC_DCTR 167 writeb(0x00, sic_regbase + VT8500_IC_DCTR
168 + i - 64); 168 + i - 64);
169 169
170 irq_set_chip(i, &vt8500_irq_chip); 170 irq_set_chip_and_handler(i, &vt8500_irq_chip,
171 irq_set_handler(i, handle_level_irq); 171 handle_level_irq);
172 set_irq_flags(i, IRQF_VALID); 172 set_irq_flags(i, IRQF_VALID);
173 } 173 }
174 } else { 174 } else {
diff --git a/arch/arm/mach-w90x900/irq.c b/arch/arm/mach-w90x900/irq.c
index 5947d1f630d2..7bf143c443f1 100644
--- a/arch/arm/mach-w90x900/irq.c
+++ b/arch/arm/mach-w90x900/irq.c
@@ -207,8 +207,8 @@ void __init nuc900_init_irq(void)
207 __raw_writel(0xFFFFFFFE, REG_AIC_MDCR); 207 __raw_writel(0xFFFFFFFE, REG_AIC_MDCR);
208 208
209 for (irqno = IRQ_WDT; irqno <= IRQ_ADC; irqno++) { 209 for (irqno = IRQ_WDT; irqno <= IRQ_ADC; irqno++) {
210 irq_set_chip(irqno, &nuc900_irq_chip); 210 irq_set_chip_and_handler(irqno, &nuc900_irq_chip,
211 irq_set_handler(irqno, handle_level_irq); 211 handle_level_irq);
212 set_irq_flags(irqno, IRQF_VALID); 212 set_irq_flags(irqno, IRQF_VALID);
213 } 213 }
214} 214}
diff --git a/arch/arm/plat-mxc/3ds_debugboard.c b/arch/arm/plat-mxc/3ds_debugboard.c
index 9d424ce93354..f0ba0726306c 100644
--- a/arch/arm/plat-mxc/3ds_debugboard.c
+++ b/arch/arm/plat-mxc/3ds_debugboard.c
@@ -181,8 +181,7 @@ int __init mxc_expio_init(u32 base, u32 p_irq)
181 __raw_writew(0x1F, brd_io + INTR_MASK_REG); 181 __raw_writew(0x1F, brd_io + INTR_MASK_REG);
182 for (i = MXC_EXP_IO_BASE; 182 for (i = MXC_EXP_IO_BASE;
183 i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); i++) { 183 i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); i++) {
184 irq_set_chip(i, &expio_irq_chip); 184 irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq);
185 irq_set_handler(i, handle_level_irq);
186 set_irq_flags(i, IRQF_VALID); 185 set_irq_flags(i, IRQF_VALID);
187 } 186 }
188 irq_set_irq_type(p_irq, IRQF_TRIGGER_LOW); 187 irq_set_irq_type(p_irq, IRQF_TRIGGER_LOW);
diff --git a/arch/arm/plat-mxc/avic.c b/arch/arm/plat-mxc/avic.c
index 8b30c83a2ab1..09e2bd0fcdca 100644
--- a/arch/arm/plat-mxc/avic.c
+++ b/arch/arm/plat-mxc/avic.c
@@ -139,8 +139,8 @@ void __init mxc_init_irq(void __iomem *irqbase)
139 __raw_writel(0, avic_base + AVIC_INTTYPEH); 139 __raw_writel(0, avic_base + AVIC_INTTYPEH);
140 __raw_writel(0, avic_base + AVIC_INTTYPEL); 140 __raw_writel(0, avic_base + AVIC_INTTYPEL);
141 for (i = 0; i < MXC_INTERNAL_IRQS; i++) { 141 for (i = 0; i < MXC_INTERNAL_IRQS; i++) {
142 irq_set_chip(i, &mxc_avic_chip.base); 142 irq_set_chip_and_handler(i, &mxc_avic_chip.base,
143 irq_set_handler(i, handle_level_irq); 143 handle_level_irq);
144 set_irq_flags(i, IRQF_VALID); 144 set_irq_flags(i, IRQF_VALID);
145 } 145 }
146 146
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
index 2ff0b3f9b46d..7a107246fd98 100644
--- a/arch/arm/plat-mxc/gpio.c
+++ b/arch/arm/plat-mxc/gpio.c
@@ -311,8 +311,8 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
311 __raw_writel(~0, port[i].base + GPIO_ISR); 311 __raw_writel(~0, port[i].base + GPIO_ISR);
312 for (j = port[i].virtual_irq_start; 312 for (j = port[i].virtual_irq_start;
313 j < port[i].virtual_irq_start + 32; j++) { 313 j < port[i].virtual_irq_start + 32; j++) {
314 irq_set_chip(j, &gpio_irq_chip); 314 irq_set_chip_and_handler(j, &gpio_irq_chip,
315 irq_set_handler(j, handle_level_irq); 315 handle_level_irq);
316 set_irq_flags(j, IRQF_VALID); 316 set_irq_flags(j, IRQF_VALID);
317 } 317 }
318 318
diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c
index c299152e0841..57f9395f87ce 100644
--- a/arch/arm/plat-mxc/tzic.c
+++ b/arch/arm/plat-mxc/tzic.c
@@ -167,8 +167,8 @@ void __init tzic_init_irq(void __iomem *irqbase)
167 /* all IRQ no FIQ Warning :: No selection */ 167 /* all IRQ no FIQ Warning :: No selection */
168 168
169 for (i = 0; i < MXC_INTERNAL_IRQS; i++) { 169 for (i = 0; i < MXC_INTERNAL_IRQS; i++) {
170 irq_set_chip(i, &mxc_tzic_chip.base); 170 irq_set_chip_and_handler(i, &mxc_tzic_chip.base,
171 irq_set_handler(i, handle_level_irq); 171 handle_level_irq);
172 set_irq_flags(i, IRQF_VALID); 172 set_irq_flags(i, IRQF_VALID);
173 } 173 }
174 174
diff --git a/arch/arm/plat-nomadik/gpio.c b/arch/arm/plat-nomadik/gpio.c
index 63adc4d417fe..f49748eca1a3 100644
--- a/arch/arm/plat-nomadik/gpio.c
+++ b/arch/arm/plat-nomadik/gpio.c
@@ -725,8 +725,8 @@ static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip)
725 725
726 first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base); 726 first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base);
727 for (i = first_irq; i < first_irq + nmk_chip->chip.ngpio; i++) { 727 for (i = first_irq; i < first_irq + nmk_chip->chip.ngpio; i++) {
728 irq_set_chip(i, &nmk_gpio_irq_chip); 728 irq_set_chip_and_handler(i, &nmk_gpio_irq_chip,
729 irq_set_handler(i, handle_edge_irq); 729 handle_edge_irq);
730 set_irq_flags(i, IRQF_VALID); 730 set_irq_flags(i, IRQF_VALID);
731 irq_set_chip_data(i, nmk_chip); 731 irq_set_chip_data(i, nmk_chip);
732 irq_set_irq_type(i, IRQ_TYPE_EDGE_FALLING); 732 irq_set_irq_type(i, IRQ_TYPE_EDGE_FALLING);
diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c
index 9ea0ae4b782f..a431a138f402 100644
--- a/arch/arm/plat-orion/gpio.c
+++ b/arch/arm/plat-orion/gpio.c
@@ -474,8 +474,8 @@ void __init orion_gpio_init(int gpio_base, int ngpio,
474 for (i = 0; i < ngpio; i++) { 474 for (i = 0; i < ngpio; i++) {
475 unsigned int irq = secondary_irq_base + i; 475 unsigned int irq = secondary_irq_base + i;
476 476
477 irq_set_chip(irq, &orion_gpio_irq_chip); 477 irq_set_chip_and_handler(irq, &orion_gpio_irq_chip,
478 irq_set_handler(irq, handle_level_irq); 478 handle_level_irq);
479 irq_set_chip_data(irq, ochip); 479 irq_set_chip_data(irq, ochip);
480 irq_set_status_flags(irq, IRQ_LEVEL); 480 irq_set_status_flags(irq, IRQ_LEVEL);
481 set_irq_flags(irq, IRQF_VALID); 481 set_irq_flags(irq, IRQF_VALID);
diff --git a/arch/arm/plat-orion/irq.c b/arch/arm/plat-orion/irq.c
index f533bdeaa72b..d8d638e09f8f 100644
--- a/arch/arm/plat-orion/irq.c
+++ b/arch/arm/plat-orion/irq.c
@@ -56,8 +56,8 @@ void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)
56 for (i = 0; i < 32; i++) { 56 for (i = 0; i < 32; i++) {
57 unsigned int irq = irq_start + i; 57 unsigned int irq = irq_start + i;
58 58
59 irq_set_chip(irq, &orion_irq_chip); 59 irq_set_chip_and_handler(irq, &orion_irq_chip,
60 irq_set_handler(irq, handle_level_irq); 60 handle_level_irq);
61 irq_set_chip_data(irq, maskaddr); 61 irq_set_chip_data(irq, maskaddr);
62 irq_set_status_flags(irq, IRQ_LEVEL); 62 irq_set_status_flags(irq, IRQ_LEVEL);
63 set_irq_flags(irq, IRQF_VALID); 63 set_irq_flags(irq, IRQF_VALID);
diff --git a/arch/arm/plat-pxa/gpio.c b/arch/arm/plat-pxa/gpio.c
index 5e05467eec3d..dce088f45678 100644
--- a/arch/arm/plat-pxa/gpio.c
+++ b/arch/arm/plat-pxa/gpio.c
@@ -284,8 +284,8 @@ void __init pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn)
284 } 284 }
285 285
286 for (irq = gpio_to_irq(start); irq <= gpio_to_irq(end); irq++) { 286 for (irq = gpio_to_irq(start); irq <= gpio_to_irq(end); irq++) {
287 irq_set_chip(irq, &pxa_muxed_gpio_chip); 287 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
288 irq_set_handler(irq, handle_edge_irq); 288 handle_edge_irq);
289 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 289 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
290 } 290 }
291 291
diff --git a/arch/arm/plat-s3c24xx/irq.c b/arch/arm/plat-s3c24xx/irq.c
index c2a42d526635..9aee7e1668b1 100644
--- a/arch/arm/plat-s3c24xx/irq.c
+++ b/arch/arm/plat-s3c24xx/irq.c
@@ -592,8 +592,8 @@ void __init s3c24xx_init_irq(void)
592 case IRQ_UART1: 592 case IRQ_UART1:
593 case IRQ_UART2: 593 case IRQ_UART2:
594 case IRQ_ADCPARENT: 594 case IRQ_ADCPARENT:
595 irq_set_chip(irqno, &s3c_irq_level_chip); 595 irq_set_chip_and_handler(irqno, &s3c_irq_level_chip,
596 irq_set_handler(irqno, handle_level_irq); 596 handle_level_irq);
597 break; 597 break;
598 598
599 case IRQ_RESERVED6: 599 case IRQ_RESERVED6:
@@ -603,8 +603,8 @@ void __init s3c24xx_init_irq(void)
603 603
604 default: 604 default:
605 //irqdbf("registering irq %d (s3c irq)\n", irqno); 605 //irqdbf("registering irq %d (s3c irq)\n", irqno);
606 irq_set_chip(irqno, &s3c_irq_chip); 606 irq_set_chip_and_handler(irqno, &s3c_irq_chip,
607 irq_set_handler(irqno, handle_edge_irq); 607 handle_edge_irq);
608 set_irq_flags(irqno, IRQF_VALID); 608 set_irq_flags(irqno, IRQF_VALID);
609 } 609 }
610 } 610 }
@@ -623,15 +623,15 @@ void __init s3c24xx_init_irq(void)
623 623
624 for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) { 624 for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
625 irqdbf("registering irq %d (ext int)\n", irqno); 625 irqdbf("registering irq %d (ext int)\n", irqno);
626 irq_set_chip(irqno, &s3c_irq_eint0t4); 626 irq_set_chip_and_handler(irqno, &s3c_irq_eint0t4,
627 irq_set_handler(irqno, handle_edge_irq); 627 handle_edge_irq);
628 set_irq_flags(irqno, IRQF_VALID); 628 set_irq_flags(irqno, IRQF_VALID);
629 } 629 }
630 630
631 for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) { 631 for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) {
632 irqdbf("registering irq %d (extended s3c irq)\n", irqno); 632 irqdbf("registering irq %d (extended s3c irq)\n", irqno);
633 irq_set_chip(irqno, &s3c_irqext_chip); 633 irq_set_chip_and_handler(irqno, &s3c_irqext_chip,
634 irq_set_handler(irqno, handle_edge_irq); 634 handle_edge_irq);
635 set_irq_flags(irqno, IRQF_VALID); 635 set_irq_flags(irqno, IRQF_VALID);
636 } 636 }
637 637
@@ -641,29 +641,28 @@ void __init s3c24xx_init_irq(void)
641 641
642 for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) { 642 for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) {
643 irqdbf("registering irq %d (s3c uart0 irq)\n", irqno); 643 irqdbf("registering irq %d (s3c uart0 irq)\n", irqno);
644 irq_set_chip(irqno, &s3c_irq_uart0); 644 irq_set_chip_and_handler(irqno, &s3c_irq_uart0,
645 irq_set_handler(irqno, handle_level_irq); 645 handle_level_irq);
646 set_irq_flags(irqno, IRQF_VALID); 646 set_irq_flags(irqno, IRQF_VALID);
647 } 647 }
648 648
649 for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) { 649 for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) {
650 irqdbf("registering irq %d (s3c uart1 irq)\n", irqno); 650 irqdbf("registering irq %d (s3c uart1 irq)\n", irqno);
651 irq_set_chip(irqno, &s3c_irq_uart1); 651 irq_set_chip_and_handler(irqno, &s3c_irq_uart1,
652 irq_set_handler(irqno, handle_level_irq); 652 handle_level_irq);
653 set_irq_flags(irqno, IRQF_VALID); 653 set_irq_flags(irqno, IRQF_VALID);
654 } 654 }
655 655
656 for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) { 656 for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) {
657 irqdbf("registering irq %d (s3c uart2 irq)\n", irqno); 657 irqdbf("registering irq %d (s3c uart2 irq)\n", irqno);
658 irq_set_chip(irqno, &s3c_irq_uart2); 658 irq_set_chip_and_handler(irqno, &s3c_irq_uart2,
659 irq_set_handler(irqno, handle_level_irq); 659 handle_level_irq);
660 set_irq_flags(irqno, IRQF_VALID); 660 set_irq_flags(irqno, IRQF_VALID);
661 } 661 }
662 662
663 for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) { 663 for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) {
664 irqdbf("registering irq %d (s3c adc irq)\n", irqno); 664 irqdbf("registering irq %d (s3c adc irq)\n", irqno);
665 irq_set_chip(irqno, &s3c_irq_adc); 665 irq_set_chip_and_handler(irqno, &s3c_irq_adc, handle_edge_irq);
666 irq_set_handler(irqno, handle_edge_irq);
667 set_irq_flags(irqno, IRQF_VALID); 666 set_irq_flags(irqno, IRQF_VALID);
668 } 667 }
669 668
diff --git a/arch/arm/plat-s5p/irq-eint.c b/arch/arm/plat-s5p/irq-eint.c
index f3d15e8c02c1..b5bb774985b0 100644
--- a/arch/arm/plat-s5p/irq-eint.c
+++ b/arch/arm/plat-s5p/irq-eint.c
@@ -208,8 +208,7 @@ int __init s5p_init_irq_eint(void)
208 irq_set_chip(irq, &s5p_irq_vic_eint); 208 irq_set_chip(irq, &s5p_irq_vic_eint);
209 209
210 for (irq = IRQ_EINT(16); irq <= IRQ_EINT(31); irq++) { 210 for (irq = IRQ_EINT(16); irq <= IRQ_EINT(31); irq++) {
211 irq_set_chip(irq, &s5p_irq_eint); 211 irq_set_chip_and_handler(irq, &s5p_irq_eint, handle_level_irq);
212 irq_set_handler(irq, handle_level_irq);
213 set_irq_flags(irq, IRQF_VALID); 212 set_irq_flags(irq, IRQF_VALID);
214 } 213 }
215 214
diff --git a/arch/arm/plat-samsung/irq-uart.c b/arch/arm/plat-samsung/irq-uart.c
index 9dbad70bdd09..4d4e571af553 100644
--- a/arch/arm/plat-samsung/irq-uart.c
+++ b/arch/arm/plat-samsung/irq-uart.c
@@ -117,8 +117,7 @@ static void __init s3c_init_uart_irq(struct s3c_uart_irq *uirq)
117 for (offs = 0; offs < 3; offs++) { 117 for (offs = 0; offs < 3; offs++) {
118 irq = uirq->base_irq + offs; 118 irq = uirq->base_irq + offs;
119 119
120 irq_set_chip(irq, &s3c_irq_uart); 120 irq_set_chip_and_handler(irq, &s3c_irq_uart, handle_level_irq);
121 irq_set_handler(irq, handle_level_irq);
122 irq_set_chip_data(irq, uirq); 121 irq_set_chip_data(irq, uirq);
123 set_irq_flags(irq, IRQF_VALID); 122 set_irq_flags(irq, IRQF_VALID);
124 } 123 }
diff --git a/arch/arm/plat-spear/shirq.c b/arch/arm/plat-spear/shirq.c
index b4294cc140fa..961fb7261243 100644
--- a/arch/arm/plat-spear/shirq.c
+++ b/arch/arm/plat-spear/shirq.c
@@ -107,8 +107,8 @@ int spear_shirq_register(struct spear_shirq *shirq)
107 107
108 irq_set_chained_handler(shirq->irq, shirq_handler); 108 irq_set_chained_handler(shirq->irq, shirq_handler);
109 for (i = 0; i < shirq->dev_count; i++) { 109 for (i = 0; i < shirq->dev_count; i++) {
110 irq_set_chip(shirq->dev_config[i].virq, &shirq_chip); 110 irq_set_chip_and_handler(shirq->dev_config[i].virq,
111 irq_set_handler(shirq->dev_config[i].virq, handle_simple_irq); 111 &shirq_chip, handle_simple_irq);
112 set_irq_flags(shirq->dev_config[i].virq, IRQF_VALID); 112 set_irq_flags(shirq->dev_config[i].virq, IRQF_VALID);
113 irq_set_chip_data(shirq->dev_config[i].virq, shirq); 113 irq_set_chip_data(shirq->dev_config[i].virq, shirq);
114 } 114 }
diff --git a/arch/arm/plat-stmp3xxx/irq.c b/arch/arm/plat-stmp3xxx/irq.c
index fc2e76488c16..6fdf9acf82ed 100644
--- a/arch/arm/plat-stmp3xxx/irq.c
+++ b/arch/arm/plat-stmp3xxx/irq.c
@@ -35,8 +35,7 @@ void __init stmp3xxx_init_irq(struct irq_chip *chip)
35 /* Disable all interrupts initially */ 35 /* Disable all interrupts initially */
36 for (i = 0; i < NR_REAL_IRQS; i++) { 36 for (i = 0; i < NR_REAL_IRQS; i++) {
37 chip->irq_mask(irq_get_irq_data(i)); 37 chip->irq_mask(irq_get_irq_data(i));
38 irq_set_chip(i, chip); 38 irq_set_chip_and_handler(i, chip, handle_level_irq);
39 irq_set_handler(i, handle_level_irq);
40 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 39 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
41 } 40 }
42 41
diff --git a/arch/arm/plat-stmp3xxx/pinmux.c b/arch/arm/plat-stmp3xxx/pinmux.c
index 9057d932799a..3def03b3217d 100644
--- a/arch/arm/plat-stmp3xxx/pinmux.c
+++ b/arch/arm/plat-stmp3xxx/pinmux.c
@@ -533,8 +533,8 @@ int __init stmp3xxx_pinmux_init(int virtual_irq_start)
533 533
534 for (virq = pm->virq; virq < pm->virq; virq++) { 534 for (virq = pm->virq; virq < pm->virq; virq++) {
535 gpio_irq_chip.irq_mask(irq_get_irq_data(virq)); 535 gpio_irq_chip.irq_mask(irq_get_irq_data(virq));
536 irq_set_chip(virq, &gpio_irq_chip); 536 irq_set_chip_and_handler(virq, &gpio_irq_chip,
537 irq_set_handler(virq, handle_level_irq); 537 handle_level_irq);
538 set_irq_flags(virq, IRQF_VALID); 538 set_irq_flags(virq, IRQF_VALID);
539 } 539 }
540 r = gpiochip_add(&pm->chip); 540 r = gpiochip_add(&pm->chip);
diff --git a/arch/arm/plat-versatile/fpga-irq.c b/arch/arm/plat-versatile/fpga-irq.c
index f21d838044c8..f0cc8e19b094 100644
--- a/arch/arm/plat-versatile/fpga-irq.c
+++ b/arch/arm/plat-versatile/fpga-irq.c
@@ -64,8 +64,8 @@ void __init fpga_irq_init(int parent_irq, u32 valid, struct fpga_irq_data *f)
64 unsigned int irq = f->irq_start + i; 64 unsigned int irq = f->irq_start + i;
65 65
66 irq_set_chip_data(irq, f); 66 irq_set_chip_data(irq, f);
67 irq_set_chip(irq, &f->chip); 67 irq_set_chip_and_handler(irq, &f->chip,
68 irq_set_handler(irq, handle_level_irq); 68 handle_level_irq);
69 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 69 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
70 } 70 }
71 } 71 }