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authorThomas Abraham <thomas.ab@samsung.com>2011-06-14 06:12:26 -0400
committerKukjin Kim <kgene.kim@samsung.com>2011-07-20 06:11:29 -0400
commite83626f2fd48fa53ece85760c7e0b4ec4a996a91 (patch)
tree8f89557b9e9f1e39314d9eabda7454b34a15b8a1 /arch
parentf86c6660927614fcda257e083569bfb252fcf85e (diff)
ARM: S3C24XX: Add clkdev support
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/Kconfig1
-rw-r--r--arch/arm/mach-s3c2412/clock.c36
-rw-r--r--arch/arm/mach-s3c2416/clock.c10
-rw-r--r--arch/arm/mach-s3c2440/clock.c3
-rw-r--r--arch/arm/mach-s3c2443/clock.c16
-rw-r--r--arch/arm/plat-s3c24xx/clock-dclk.c4
-rw-r--r--arch/arm/plat-s3c24xx/s3c2410-clock.c21
-rw-r--r--arch/arm/plat-s3c24xx/s3c2443-clock.c39
-rw-r--r--arch/arm/plat-samsung/clock.c10
-rw-r--r--arch/arm/plat-samsung/pwm-clock.c10
-rw-r--r--arch/arm/plat-samsung/time.c2
11 files changed, 32 insertions, 120 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9adc278a22ab..3f31f3256c69 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -682,6 +682,7 @@ config ARCH_S3C2410
682 select GENERIC_GPIO 682 select GENERIC_GPIO
683 select ARCH_HAS_CPUFREQ 683 select ARCH_HAS_CPUFREQ
684 select HAVE_CLK 684 select HAVE_CLK
685 select CLKDEV_LOOKUP
685 select ARCH_USES_GETTIMEOFFSET 686 select ARCH_USES_GETTIMEOFFSET
686 select HAVE_S3C2410_I2C if I2C 687 select HAVE_S3C2410_I2C if I2C
687 help 688 help
diff --git a/arch/arm/mach-s3c2412/clock.c b/arch/arm/mach-s3c2412/clock.c
index 0c0505b025cb..140711db6c89 100644
--- a/arch/arm/mach-s3c2412/clock.c
+++ b/arch/arm/mach-s3c2412/clock.c
@@ -95,12 +95,10 @@ static int s3c2412_upll_enable(struct clk *clk, int enable)
95 95
96static struct clk clk_erefclk = { 96static struct clk clk_erefclk = {
97 .name = "erefclk", 97 .name = "erefclk",
98 .id = -1,
99}; 98};
100 99
101static struct clk clk_urefclk = { 100static struct clk clk_urefclk = {
102 .name = "urefclk", 101 .name = "urefclk",
103 .id = -1,
104}; 102};
105 103
106static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent) 104static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent)
@@ -122,7 +120,6 @@ static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent)
122 120
123static struct clk clk_usysclk = { 121static struct clk clk_usysclk = {
124 .name = "usysclk", 122 .name = "usysclk",
125 .id = -1,
126 .parent = &clk_xtal, 123 .parent = &clk_xtal,
127 .ops = &(struct clk_ops) { 124 .ops = &(struct clk_ops) {
128 .set_parent = s3c2412_setparent_usysclk, 125 .set_parent = s3c2412_setparent_usysclk,
@@ -132,13 +129,11 @@ static struct clk clk_usysclk = {
132static struct clk clk_mrefclk = { 129static struct clk clk_mrefclk = {
133 .name = "mrefclk", 130 .name = "mrefclk",
134 .parent = &clk_xtal, 131 .parent = &clk_xtal,
135 .id = -1,
136}; 132};
137 133
138static struct clk clk_mdivclk = { 134static struct clk clk_mdivclk = {
139 .name = "mdivclk", 135 .name = "mdivclk",
140 .parent = &clk_xtal, 136 .parent = &clk_xtal,
141 .id = -1,
142}; 137};
143 138
144static int s3c2412_setparent_usbsrc(struct clk *clk, struct clk *parent) 139static int s3c2412_setparent_usbsrc(struct clk *clk, struct clk *parent)
@@ -200,7 +195,6 @@ static int s3c2412_setrate_usbsrc(struct clk *clk, unsigned long rate)
200 195
201static struct clk clk_usbsrc = { 196static struct clk clk_usbsrc = {
202 .name = "usbsrc", 197 .name = "usbsrc",
203 .id = -1,
204 .ops = &(struct clk_ops) { 198 .ops = &(struct clk_ops) {
205 .get_rate = s3c2412_getrate_usbsrc, 199 .get_rate = s3c2412_getrate_usbsrc,
206 .set_rate = s3c2412_setrate_usbsrc, 200 .set_rate = s3c2412_setrate_usbsrc,
@@ -228,7 +222,6 @@ static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent)
228 222
229static struct clk clk_msysclk = { 223static struct clk clk_msysclk = {
230 .name = "msysclk", 224 .name = "msysclk",
231 .id = -1,
232 .ops = &(struct clk_ops) { 225 .ops = &(struct clk_ops) {
233 .set_parent = s3c2412_setparent_msysclk, 226 .set_parent = s3c2412_setparent_msysclk,
234 }, 227 },
@@ -268,7 +261,6 @@ static int s3c2412_setparent_armclk(struct clk *clk, struct clk *parent)
268 261
269static struct clk clk_armclk = { 262static struct clk clk_armclk = {
270 .name = "armclk", 263 .name = "armclk",
271 .id = -1,
272 .parent = &clk_msysclk, 264 .parent = &clk_msysclk,
273 .ops = &(struct clk_ops) { 265 .ops = &(struct clk_ops) {
274 .set_parent = s3c2412_setparent_armclk, 266 .set_parent = s3c2412_setparent_armclk,
@@ -344,7 +336,6 @@ static int s3c2412_setrate_uart(struct clk *clk, unsigned long rate)
344 336
345static struct clk clk_uart = { 337static struct clk clk_uart = {
346 .name = "uartclk", 338 .name = "uartclk",
347 .id = -1,
348 .ops = &(struct clk_ops) { 339 .ops = &(struct clk_ops) {
349 .get_rate = s3c2412_getrate_uart, 340 .get_rate = s3c2412_getrate_uart,
350 .set_rate = s3c2412_setrate_uart, 341 .set_rate = s3c2412_setrate_uart,
@@ -397,7 +388,6 @@ static int s3c2412_setrate_i2s(struct clk *clk, unsigned long rate)
397 388
398static struct clk clk_i2s = { 389static struct clk clk_i2s = {
399 .name = "i2sclk", 390 .name = "i2sclk",
400 .id = -1,
401 .ops = &(struct clk_ops) { 391 .ops = &(struct clk_ops) {
402 .get_rate = s3c2412_getrate_i2s, 392 .get_rate = s3c2412_getrate_i2s,
403 .set_rate = s3c2412_setrate_i2s, 393 .set_rate = s3c2412_setrate_i2s,
@@ -449,7 +439,6 @@ static int s3c2412_setrate_cam(struct clk *clk, unsigned long rate)
449 439
450static struct clk clk_cam = { 440static struct clk clk_cam = {
451 .name = "camif-upll", /* same as 2440 name */ 441 .name = "camif-upll", /* same as 2440 name */
452 .id = -1,
453 .ops = &(struct clk_ops) { 442 .ops = &(struct clk_ops) {
454 .get_rate = s3c2412_getrate_cam, 443 .get_rate = s3c2412_getrate_cam,
455 .set_rate = s3c2412_setrate_cam, 444 .set_rate = s3c2412_setrate_cam,
@@ -463,37 +452,31 @@ static struct clk clk_cam = {
463static struct clk init_clocks_disable[] = { 452static struct clk init_clocks_disable[] = {
464 { 453 {
465 .name = "nand", 454 .name = "nand",
466 .id = -1,
467 .parent = &clk_h, 455 .parent = &clk_h,
468 .enable = s3c2412_clkcon_enable, 456 .enable = s3c2412_clkcon_enable,
469 .ctrlbit = S3C2412_CLKCON_NAND, 457 .ctrlbit = S3C2412_CLKCON_NAND,
470 }, { 458 }, {
471 .name = "sdi", 459 .name = "sdi",
472 .id = -1,
473 .parent = &clk_p, 460 .parent = &clk_p,
474 .enable = s3c2412_clkcon_enable, 461 .enable = s3c2412_clkcon_enable,
475 .ctrlbit = S3C2412_CLKCON_SDI, 462 .ctrlbit = S3C2412_CLKCON_SDI,
476 }, { 463 }, {
477 .name = "adc", 464 .name = "adc",
478 .id = -1,
479 .parent = &clk_p, 465 .parent = &clk_p,
480 .enable = s3c2412_clkcon_enable, 466 .enable = s3c2412_clkcon_enable,
481 .ctrlbit = S3C2412_CLKCON_ADC, 467 .ctrlbit = S3C2412_CLKCON_ADC,
482 }, { 468 }, {
483 .name = "i2c", 469 .name = "i2c",
484 .id = -1,
485 .parent = &clk_p, 470 .parent = &clk_p,
486 .enable = s3c2412_clkcon_enable, 471 .enable = s3c2412_clkcon_enable,
487 .ctrlbit = S3C2412_CLKCON_IIC, 472 .ctrlbit = S3C2412_CLKCON_IIC,
488 }, { 473 }, {
489 .name = "iis", 474 .name = "iis",
490 .id = -1,
491 .parent = &clk_p, 475 .parent = &clk_p,
492 .enable = s3c2412_clkcon_enable, 476 .enable = s3c2412_clkcon_enable,
493 .ctrlbit = S3C2412_CLKCON_IIS, 477 .ctrlbit = S3C2412_CLKCON_IIS,
494 }, { 478 }, {
495 .name = "spi", 479 .name = "spi",
496 .id = -1,
497 .parent = &clk_p, 480 .parent = &clk_p,
498 .enable = s3c2412_clkcon_enable, 481 .enable = s3c2412_clkcon_enable,
499 .ctrlbit = S3C2412_CLKCON_SPI, 482 .ctrlbit = S3C2412_CLKCON_SPI,
@@ -503,96 +486,83 @@ static struct clk init_clocks_disable[] = {
503static struct clk init_clocks[] = { 486static struct clk init_clocks[] = {
504 { 487 {
505 .name = "dma", 488 .name = "dma",
506 .id = 0,
507 .parent = &clk_h, 489 .parent = &clk_h,
508 .enable = s3c2412_clkcon_enable, 490 .enable = s3c2412_clkcon_enable,
509 .ctrlbit = S3C2412_CLKCON_DMA0, 491 .ctrlbit = S3C2412_CLKCON_DMA0,
510 }, { 492 }, {
511 .name = "dma", 493 .name = "dma",
512 .id = 1,
513 .parent = &clk_h, 494 .parent = &clk_h,
514 .enable = s3c2412_clkcon_enable, 495 .enable = s3c2412_clkcon_enable,
515 .ctrlbit = S3C2412_CLKCON_DMA1, 496 .ctrlbit = S3C2412_CLKCON_DMA1,
516 }, { 497 }, {
517 .name = "dma", 498 .name = "dma",
518 .id = 2,
519 .parent = &clk_h, 499 .parent = &clk_h,
520 .enable = s3c2412_clkcon_enable, 500 .enable = s3c2412_clkcon_enable,
521 .ctrlbit = S3C2412_CLKCON_DMA2, 501 .ctrlbit = S3C2412_CLKCON_DMA2,
522 }, { 502 }, {
523 .name = "dma", 503 .name = "dma",
524 .id = 3,
525 .parent = &clk_h, 504 .parent = &clk_h,
526 .enable = s3c2412_clkcon_enable, 505 .enable = s3c2412_clkcon_enable,
527 .ctrlbit = S3C2412_CLKCON_DMA3, 506 .ctrlbit = S3C2412_CLKCON_DMA3,
528 }, { 507 }, {
529 .name = "lcd", 508 .name = "lcd",
530 .id = -1,
531 .parent = &clk_h, 509 .parent = &clk_h,
532 .enable = s3c2412_clkcon_enable, 510 .enable = s3c2412_clkcon_enable,
533 .ctrlbit = S3C2412_CLKCON_LCDC, 511 .ctrlbit = S3C2412_CLKCON_LCDC,
534 }, { 512 }, {
535 .name = "gpio", 513 .name = "gpio",
536 .id = -1,
537 .parent = &clk_p, 514 .parent = &clk_p,
538 .enable = s3c2412_clkcon_enable, 515 .enable = s3c2412_clkcon_enable,
539 .ctrlbit = S3C2412_CLKCON_GPIO, 516 .ctrlbit = S3C2412_CLKCON_GPIO,
540 }, { 517 }, {
541 .name = "usb-host", 518 .name = "usb-host",
542 .id = -1,
543 .parent = &clk_h, 519 .parent = &clk_h,
544 .enable = s3c2412_clkcon_enable, 520 .enable = s3c2412_clkcon_enable,
545 .ctrlbit = S3C2412_CLKCON_USBH, 521 .ctrlbit = S3C2412_CLKCON_USBH,
546 }, { 522 }, {
547 .name = "usb-device", 523 .name = "usb-device",
548 .id = -1,
549 .parent = &clk_h, 524 .parent = &clk_h,
550 .enable = s3c2412_clkcon_enable, 525 .enable = s3c2412_clkcon_enable,
551 .ctrlbit = S3C2412_CLKCON_USBD, 526 .ctrlbit = S3C2412_CLKCON_USBD,
552 }, { 527 }, {
553 .name = "timers", 528 .name = "timers",
554 .id = -1,
555 .parent = &clk_p, 529 .parent = &clk_p,
556 .enable = s3c2412_clkcon_enable, 530 .enable = s3c2412_clkcon_enable,
557 .ctrlbit = S3C2412_CLKCON_PWMT, 531 .ctrlbit = S3C2412_CLKCON_PWMT,
558 }, { 532 }, {
559 .name = "uart", 533 .name = "uart",
560 .id = 0, 534 .devname = "s3c2412-uart.0",
561 .parent = &clk_p, 535 .parent = &clk_p,
562 .enable = s3c2412_clkcon_enable, 536 .enable = s3c2412_clkcon_enable,
563 .ctrlbit = S3C2412_CLKCON_UART0, 537 .ctrlbit = S3C2412_CLKCON_UART0,
564 }, { 538 }, {
565 .name = "uart", 539 .name = "uart",
566 .id = 1, 540 .devname = "s3c2412-uart.1",
567 .parent = &clk_p, 541 .parent = &clk_p,
568 .enable = s3c2412_clkcon_enable, 542 .enable = s3c2412_clkcon_enable,
569 .ctrlbit = S3C2412_CLKCON_UART1, 543 .ctrlbit = S3C2412_CLKCON_UART1,
570 }, { 544 }, {
571 .name = "uart", 545 .name = "uart",
572 .id = 2, 546 .devname = "s3c2412-uart.2",
573 .parent = &clk_p, 547 .parent = &clk_p,
574 .enable = s3c2412_clkcon_enable, 548 .enable = s3c2412_clkcon_enable,
575 .ctrlbit = S3C2412_CLKCON_UART2, 549 .ctrlbit = S3C2412_CLKCON_UART2,
576 }, { 550 }, {
577 .name = "rtc", 551 .name = "rtc",
578 .id = -1,
579 .parent = &clk_p, 552 .parent = &clk_p,
580 .enable = s3c2412_clkcon_enable, 553 .enable = s3c2412_clkcon_enable,
581 .ctrlbit = S3C2412_CLKCON_RTC, 554 .ctrlbit = S3C2412_CLKCON_RTC,
582 }, { 555 }, {
583 .name = "watchdog", 556 .name = "watchdog",
584 .id = -1,
585 .parent = &clk_p, 557 .parent = &clk_p,
586 .ctrlbit = 0, 558 .ctrlbit = 0,
587 }, { 559 }, {
588 .name = "usb-bus-gadget", 560 .name = "usb-bus-gadget",
589 .id = -1,
590 .parent = &clk_usb_bus, 561 .parent = &clk_usb_bus,
591 .enable = s3c2412_clkcon_enable, 562 .enable = s3c2412_clkcon_enable,
592 .ctrlbit = S3C2412_CLKCON_USB_DEV48, 563 .ctrlbit = S3C2412_CLKCON_USB_DEV48,
593 }, { 564 }, {
594 .name = "usb-bus-host", 565 .name = "usb-bus-host",
595 .id = -1,
596 .parent = &clk_usb_bus, 566 .parent = &clk_usb_bus,
597 .enable = s3c2412_clkcon_enable, 567 .enable = s3c2412_clkcon_enable,
598 .ctrlbit = S3C2412_CLKCON_USB_HOST48, 568 .ctrlbit = S3C2412_CLKCON_USB_HOST48,
diff --git a/arch/arm/mach-s3c2416/clock.c b/arch/arm/mach-s3c2416/clock.c
index 3b02d8506e25..21a5e81f0ab5 100644
--- a/arch/arm/mach-s3c2416/clock.c
+++ b/arch/arm/mach-s3c2416/clock.c
@@ -42,7 +42,7 @@ static struct clksrc_clk hsmmc_div[] = {
42 [0] = { 42 [0] = {
43 .clk = { 43 .clk = {
44 .name = "hsmmc-div", 44 .name = "hsmmc-div",
45 .id = 0, 45 .devname = "s3c-sdhci.0",
46 .parent = &clk_esysclk.clk, 46 .parent = &clk_esysclk.clk,
47 }, 47 },
48 .reg_div = { .reg = S3C2416_CLKDIV2, .size = 2, .shift = 6 }, 48 .reg_div = { .reg = S3C2416_CLKDIV2, .size = 2, .shift = 6 },
@@ -50,7 +50,7 @@ static struct clksrc_clk hsmmc_div[] = {
50 [1] = { 50 [1] = {
51 .clk = { 51 .clk = {
52 .name = "hsmmc-div", 52 .name = "hsmmc-div",
53 .id = 1, 53 .devname = "s3c-sdhci.1",
54 .parent = &clk_esysclk.clk, 54 .parent = &clk_esysclk.clk,
55 }, 55 },
56 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 }, 56 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
@@ -60,8 +60,8 @@ static struct clksrc_clk hsmmc_div[] = {
60static struct clksrc_clk hsmmc_mux[] = { 60static struct clksrc_clk hsmmc_mux[] = {
61 [0] = { 61 [0] = {
62 .clk = { 62 .clk = {
63 .id = 0,
64 .name = "hsmmc-if", 63 .name = "hsmmc-if",
64 .devname = "s3c-sdhci.0",
65 .ctrlbit = (1 << 6), 65 .ctrlbit = (1 << 6),
66 .enable = s3c2443_clkcon_enable_s, 66 .enable = s3c2443_clkcon_enable_s,
67 }, 67 },
@@ -76,8 +76,8 @@ static struct clksrc_clk hsmmc_mux[] = {
76 }, 76 },
77 [1] = { 77 [1] = {
78 .clk = { 78 .clk = {
79 .id = 1,
80 .name = "hsmmc-if", 79 .name = "hsmmc-if",
80 .devname = "s3c-sdhci.1",
81 .ctrlbit = (1 << 12), 81 .ctrlbit = (1 << 12),
82 .enable = s3c2443_clkcon_enable_s, 82 .enable = s3c2443_clkcon_enable_s,
83 }, 83 },
@@ -94,7 +94,7 @@ static struct clksrc_clk hsmmc_mux[] = {
94 94
95static struct clk hsmmc0_clk = { 95static struct clk hsmmc0_clk = {
96 .name = "hsmmc", 96 .name = "hsmmc",
97 .id = 0, 97 .devname = "s3c-sdhci.0",
98 .parent = &clk_h, 98 .parent = &clk_h,
99 .enable = s3c2443_clkcon_enable_h, 99 .enable = s3c2443_clkcon_enable_h,
100 .ctrlbit = S3C2416_HCLKCON_HSMMC0, 100 .ctrlbit = S3C2416_HCLKCON_HSMMC0,
diff --git a/arch/arm/mach-s3c2440/clock.c b/arch/arm/mach-s3c2440/clock.c
index 3dc2426e2345..554e0d3ec70b 100644
--- a/arch/arm/mach-s3c2440/clock.c
+++ b/arch/arm/mach-s3c2440/clock.c
@@ -90,14 +90,12 @@ static int s3c2440_camif_upll_setrate(struct clk *clk, unsigned long rate)
90 90
91static struct clk s3c2440_clk_cam = { 91static struct clk s3c2440_clk_cam = {
92 .name = "camif", 92 .name = "camif",
93 .id = -1,
94 .enable = s3c2410_clkcon_enable, 93 .enable = s3c2410_clkcon_enable,
95 .ctrlbit = S3C2440_CLKCON_CAMERA, 94 .ctrlbit = S3C2440_CLKCON_CAMERA,
96}; 95};
97 96
98static struct clk s3c2440_clk_cam_upll = { 97static struct clk s3c2440_clk_cam_upll = {
99 .name = "camif-upll", 98 .name = "camif-upll",
100 .id = -1,
101 .ops = &(struct clk_ops) { 99 .ops = &(struct clk_ops) {
102 .set_rate = s3c2440_camif_upll_setrate, 100 .set_rate = s3c2440_camif_upll_setrate,
103 .round_rate = s3c2440_camif_upll_round, 101 .round_rate = s3c2440_camif_upll_round,
@@ -106,7 +104,6 @@ static struct clk s3c2440_clk_cam_upll = {
106 104
107static struct clk s3c2440_clk_ac97 = { 105static struct clk s3c2440_clk_ac97 = {
108 .name = "ac97", 106 .name = "ac97",
109 .id = -1,
110 .enable = s3c2410_clkcon_enable, 107 .enable = s3c2410_clkcon_enable,
111 .ctrlbit = S3C2440_CLKCON_CAMERA, 108 .ctrlbit = S3C2440_CLKCON_CAMERA,
112}; 109};
diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c
index f4ec6d5715c8..a1a7176675b9 100644
--- a/arch/arm/mach-s3c2443/clock.c
+++ b/arch/arm/mach-s3c2443/clock.c
@@ -59,7 +59,6 @@
59 59
60static struct clk clk_i2s_ext = { 60static struct clk clk_i2s_ext = {
61 .name = "i2s-ext", 61 .name = "i2s-ext",
62 .id = -1,
63}; 62};
64 63
65/* armdiv 64/* armdiv
@@ -139,7 +138,6 @@ static int s3c2443_armclk_setrate(struct clk *clk, unsigned long rate)
139 138
140static struct clk clk_armdiv = { 139static struct clk clk_armdiv = {
141 .name = "armdiv", 140 .name = "armdiv",
142 .id = -1,
143 .parent = &clk_msysclk.clk, 141 .parent = &clk_msysclk.clk,
144 .ops = &(struct clk_ops) { 142 .ops = &(struct clk_ops) {
145 .round_rate = s3c2443_armclk_roundrate, 143 .round_rate = s3c2443_armclk_roundrate,
@@ -160,7 +158,6 @@ static struct clk *clk_arm_sources[] = {
160static struct clksrc_clk clk_arm = { 158static struct clksrc_clk clk_arm = {
161 .clk = { 159 .clk = {
162 .name = "armclk", 160 .name = "armclk",
163 .id = -1,
164 }, 161 },
165 .sources = &(struct clksrc_sources) { 162 .sources = &(struct clksrc_sources) {
166 .sources = clk_arm_sources, 163 .sources = clk_arm_sources,
@@ -177,7 +174,6 @@ static struct clksrc_clk clk_arm = {
177static struct clksrc_clk clk_hsspi = { 174static struct clksrc_clk clk_hsspi = {
178 .clk = { 175 .clk = {
179 .name = "hsspi", 176 .name = "hsspi",
180 .id = -1,
181 .parent = &clk_esysclk.clk, 177 .parent = &clk_esysclk.clk,
182 .ctrlbit = S3C2443_SCLKCON_HSSPICLK, 178 .ctrlbit = S3C2443_SCLKCON_HSSPICLK,
183 .enable = s3c2443_clkcon_enable_s, 179 .enable = s3c2443_clkcon_enable_s,
@@ -196,7 +192,7 @@ static struct clksrc_clk clk_hsspi = {
196static struct clksrc_clk clk_hsmmc_div = { 192static struct clksrc_clk clk_hsmmc_div = {
197 .clk = { 193 .clk = {
198 .name = "hsmmc-div", 194 .name = "hsmmc-div",
199 .id = 1, 195 .devname = "s3c-sdhci.1",
200 .parent = &clk_esysclk.clk, 196 .parent = &clk_esysclk.clk,
201 }, 197 },
202 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 }, 198 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
@@ -231,7 +227,7 @@ static int s3c2443_enable_hsmmc(struct clk *clk, int enable)
231 227
232static struct clk clk_hsmmc = { 228static struct clk clk_hsmmc = {
233 .name = "hsmmc-if", 229 .name = "hsmmc-if",
234 .id = 1, 230 .devname = "s3c-sdhci.1",
235 .parent = &clk_hsmmc_div.clk, 231 .parent = &clk_hsmmc_div.clk,
236 .enable = s3c2443_enable_hsmmc, 232 .enable = s3c2443_enable_hsmmc,
237 .ops = &(struct clk_ops) { 233 .ops = &(struct clk_ops) {
@@ -248,7 +244,6 @@ static struct clk clk_hsmmc = {
248static struct clksrc_clk clk_i2s_eplldiv = { 244static struct clksrc_clk clk_i2s_eplldiv = {
249 .clk = { 245 .clk = {
250 .name = "i2s-eplldiv", 246 .name = "i2s-eplldiv",
251 .id = -1,
252 .parent = &clk_esysclk.clk, 247 .parent = &clk_esysclk.clk,
253 }, 248 },
254 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 12, }, 249 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 12, },
@@ -271,7 +266,6 @@ struct clk *clk_i2s_srclist[] = {
271static struct clksrc_clk clk_i2s = { 266static struct clksrc_clk clk_i2s = {
272 .clk = { 267 .clk = {
273 .name = "i2s-if", 268 .name = "i2s-if",
274 .id = -1,
275 .ctrlbit = S3C2443_SCLKCON_I2SCLK, 269 .ctrlbit = S3C2443_SCLKCON_I2SCLK,
276 .enable = s3c2443_clkcon_enable_s, 270 .enable = s3c2443_clkcon_enable_s,
277 271
@@ -288,25 +282,23 @@ static struct clksrc_clk clk_i2s = {
288static struct clk init_clocks_off[] = { 282static struct clk init_clocks_off[] = {
289 { 283 {
290 .name = "sdi", 284 .name = "sdi",
291 .id = -1,
292 .parent = &clk_p, 285 .parent = &clk_p,
293 .enable = s3c2443_clkcon_enable_p, 286 .enable = s3c2443_clkcon_enable_p,
294 .ctrlbit = S3C2443_PCLKCON_SDI, 287 .ctrlbit = S3C2443_PCLKCON_SDI,
295 }, { 288 }, {
296 .name = "iis", 289 .name = "iis",
297 .id = -1,
298 .parent = &clk_p, 290 .parent = &clk_p,
299 .enable = s3c2443_clkcon_enable_p, 291 .enable = s3c2443_clkcon_enable_p,
300 .ctrlbit = S3C2443_PCLKCON_IIS, 292 .ctrlbit = S3C2443_PCLKCON_IIS,
301 }, { 293 }, {
302 .name = "spi", 294 .name = "spi",
303 .id = 0, 295 .devname = "s3c2410-spi.0",
304 .parent = &clk_p, 296 .parent = &clk_p,
305 .enable = s3c2443_clkcon_enable_p, 297 .enable = s3c2443_clkcon_enable_p,
306 .ctrlbit = S3C2443_PCLKCON_SPI0, 298 .ctrlbit = S3C2443_PCLKCON_SPI0,
307 }, { 299 }, {
308 .name = "spi", 300 .name = "spi",
309 .id = 1, 301 .devname = "s3c2410-spi.1",
310 .parent = &clk_p, 302 .parent = &clk_p,
311 .enable = s3c2443_clkcon_enable_p, 303 .enable = s3c2443_clkcon_enable_p,
312 .ctrlbit = S3C2443_PCLKCON_SPI1, 304 .ctrlbit = S3C2443_PCLKCON_SPI1,
diff --git a/arch/arm/plat-s3c24xx/clock-dclk.c b/arch/arm/plat-s3c24xx/clock-dclk.c
index cf97caafe56b..f95d3268ae1f 100644
--- a/arch/arm/plat-s3c24xx/clock-dclk.c
+++ b/arch/arm/plat-s3c24xx/clock-dclk.c
@@ -169,7 +169,6 @@ static struct clk_ops dclk_ops = {
169 169
170struct clk s3c24xx_dclk0 = { 170struct clk s3c24xx_dclk0 = {
171 .name = "dclk0", 171 .name = "dclk0",
172 .id = -1,
173 .ctrlbit = S3C2410_DCLKCON_DCLK0EN, 172 .ctrlbit = S3C2410_DCLKCON_DCLK0EN,
174 .enable = s3c24xx_dclk_enable, 173 .enable = s3c24xx_dclk_enable,
175 .ops = &dclk_ops, 174 .ops = &dclk_ops,
@@ -177,7 +176,6 @@ struct clk s3c24xx_dclk0 = {
177 176
178struct clk s3c24xx_dclk1 = { 177struct clk s3c24xx_dclk1 = {
179 .name = "dclk1", 178 .name = "dclk1",
180 .id = -1,
181 .ctrlbit = S3C2410_DCLKCON_DCLK1EN, 179 .ctrlbit = S3C2410_DCLKCON_DCLK1EN,
182 .enable = s3c24xx_dclk_enable, 180 .enable = s3c24xx_dclk_enable,
183 .ops = &dclk_ops, 181 .ops = &dclk_ops,
@@ -189,12 +187,10 @@ static struct clk_ops clkout_ops = {
189 187
190struct clk s3c24xx_clkout0 = { 188struct clk s3c24xx_clkout0 = {
191 .name = "clkout0", 189 .name = "clkout0",
192 .id = -1,
193 .ops = &clkout_ops, 190 .ops = &clkout_ops,
194}; 191};
195 192
196struct clk s3c24xx_clkout1 = { 193struct clk s3c24xx_clkout1 = {
197 .name = "clkout1", 194 .name = "clkout1",
198 .id = -1,
199 .ops = &clkout_ops, 195 .ops = &clkout_ops,
200}; 196};
diff --git a/arch/arm/plat-s3c24xx/s3c2410-clock.c b/arch/arm/plat-s3c24xx/s3c2410-clock.c
index 9ecc5d913679..def76aa3825a 100644
--- a/arch/arm/plat-s3c24xx/s3c2410-clock.c
+++ b/arch/arm/plat-s3c24xx/s3c2410-clock.c
@@ -90,37 +90,31 @@ static int s3c2410_upll_enable(struct clk *clk, int enable)
90static struct clk init_clocks_off[] = { 90static struct clk init_clocks_off[] = {
91 { 91 {
92 .name = "nand", 92 .name = "nand",
93 .id = -1,
94 .parent = &clk_h, 93 .parent = &clk_h,
95 .enable = s3c2410_clkcon_enable, 94 .enable = s3c2410_clkcon_enable,
96 .ctrlbit = S3C2410_CLKCON_NAND, 95 .ctrlbit = S3C2410_CLKCON_NAND,
97 }, { 96 }, {
98 .name = "sdi", 97 .name = "sdi",
99 .id = -1,
100 .parent = &clk_p, 98 .parent = &clk_p,
101 .enable = s3c2410_clkcon_enable, 99 .enable = s3c2410_clkcon_enable,
102 .ctrlbit = S3C2410_CLKCON_SDI, 100 .ctrlbit = S3C2410_CLKCON_SDI,
103 }, { 101 }, {
104 .name = "adc", 102 .name = "adc",
105 .id = -1,
106 .parent = &clk_p, 103 .parent = &clk_p,
107 .enable = s3c2410_clkcon_enable, 104 .enable = s3c2410_clkcon_enable,
108 .ctrlbit = S3C2410_CLKCON_ADC, 105 .ctrlbit = S3C2410_CLKCON_ADC,
109 }, { 106 }, {
110 .name = "i2c", 107 .name = "i2c",
111 .id = -1,
112 .parent = &clk_p, 108 .parent = &clk_p,
113 .enable = s3c2410_clkcon_enable, 109 .enable = s3c2410_clkcon_enable,
114 .ctrlbit = S3C2410_CLKCON_IIC, 110 .ctrlbit = S3C2410_CLKCON_IIC,
115 }, { 111 }, {
116 .name = "iis", 112 .name = "iis",
117 .id = -1,
118 .parent = &clk_p, 113 .parent = &clk_p,
119 .enable = s3c2410_clkcon_enable, 114 .enable = s3c2410_clkcon_enable,
120 .ctrlbit = S3C2410_CLKCON_IIS, 115 .ctrlbit = S3C2410_CLKCON_IIS,
121 }, { 116 }, {
122 .name = "spi", 117 .name = "spi",
123 .id = -1,
124 .parent = &clk_p, 118 .parent = &clk_p,
125 .enable = s3c2410_clkcon_enable, 119 .enable = s3c2410_clkcon_enable,
126 .ctrlbit = S3C2410_CLKCON_SPI, 120 .ctrlbit = S3C2410_CLKCON_SPI,
@@ -130,70 +124,61 @@ static struct clk init_clocks_off[] = {
130static struct clk init_clocks[] = { 124static struct clk init_clocks[] = {
131 { 125 {
132 .name = "lcd", 126 .name = "lcd",
133 .id = -1,
134 .parent = &clk_h, 127 .parent = &clk_h,
135 .enable = s3c2410_clkcon_enable, 128 .enable = s3c2410_clkcon_enable,
136 .ctrlbit = S3C2410_CLKCON_LCDC, 129 .ctrlbit = S3C2410_CLKCON_LCDC,
137 }, { 130 }, {
138 .name = "gpio", 131 .name = "gpio",
139 .id = -1,
140 .parent = &clk_p, 132 .parent = &clk_p,
141 .enable = s3c2410_clkcon_enable, 133 .enable = s3c2410_clkcon_enable,
142 .ctrlbit = S3C2410_CLKCON_GPIO, 134 .ctrlbit = S3C2410_CLKCON_GPIO,
143 }, { 135 }, {
144 .name = "usb-host", 136 .name = "usb-host",
145 .id = -1,
146 .parent = &clk_h, 137 .parent = &clk_h,
147 .enable = s3c2410_clkcon_enable, 138 .enable = s3c2410_clkcon_enable,
148 .ctrlbit = S3C2410_CLKCON_USBH, 139 .ctrlbit = S3C2410_CLKCON_USBH,
149 }, { 140 }, {
150 .name = "usb-device", 141 .name = "usb-device",
151 .id = -1,
152 .parent = &clk_h, 142 .parent = &clk_h,
153 .enable = s3c2410_clkcon_enable, 143 .enable = s3c2410_clkcon_enable,
154 .ctrlbit = S3C2410_CLKCON_USBD, 144 .ctrlbit = S3C2410_CLKCON_USBD,
155 }, { 145 }, {
156 .name = "timers", 146 .name = "timers",
157 .id = -1,
158 .parent = &clk_p, 147 .parent = &clk_p,
159 .enable = s3c2410_clkcon_enable, 148 .enable = s3c2410_clkcon_enable,
160 .ctrlbit = S3C2410_CLKCON_PWMT, 149 .ctrlbit = S3C2410_CLKCON_PWMT,
161 }, { 150 }, {
162 .name = "uart", 151 .name = "uart",
163 .id = 0, 152 .devname = "s3c2410-uart.0",
164 .parent = &clk_p, 153 .parent = &clk_p,
165 .enable = s3c2410_clkcon_enable, 154 .enable = s3c2410_clkcon_enable,
166 .ctrlbit = S3C2410_CLKCON_UART0, 155 .ctrlbit = S3C2410_CLKCON_UART0,
167 }, { 156 }, {
168 .name = "uart", 157 .name = "uart",
169 .id = 1, 158 .devname = "s3c2410-uart.1",
170 .parent = &clk_p, 159 .parent = &clk_p,
171 .enable = s3c2410_clkcon_enable, 160 .enable = s3c2410_clkcon_enable,
172 .ctrlbit = S3C2410_CLKCON_UART1, 161 .ctrlbit = S3C2410_CLKCON_UART1,
173 }, { 162 }, {
174 .name = "uart", 163 .name = "uart",
175 .id = 2, 164 .devname = "s3c2410-uart.2",
176 .parent = &clk_p, 165 .parent = &clk_p,
177 .enable = s3c2410_clkcon_enable, 166 .enable = s3c2410_clkcon_enable,
178 .ctrlbit = S3C2410_CLKCON_UART2, 167 .ctrlbit = S3C2410_CLKCON_UART2,
179 }, { 168 }, {
180 .name = "rtc", 169 .name = "rtc",
181 .id = -1,
182 .parent = &clk_p, 170 .parent = &clk_p,
183 .enable = s3c2410_clkcon_enable, 171 .enable = s3c2410_clkcon_enable,
184 .ctrlbit = S3C2410_CLKCON_RTC, 172 .ctrlbit = S3C2410_CLKCON_RTC,
185 }, { 173 }, {
186 .name = "watchdog", 174 .name = "watchdog",
187 .id = -1,
188 .parent = &clk_p, 175 .parent = &clk_p,
189 .ctrlbit = 0, 176 .ctrlbit = 0,
190 }, { 177 }, {
191 .name = "usb-bus-host", 178 .name = "usb-bus-host",
192 .id = -1,
193 .parent = &clk_usb_bus, 179 .parent = &clk_usb_bus,
194 }, { 180 }, {
195 .name = "usb-bus-gadget", 181 .name = "usb-bus-gadget",
196 .id = -1,
197 .parent = &clk_usb_bus, 182 .parent = &clk_usb_bus,
198 }, 183 },
199}; 184};
diff --git a/arch/arm/plat-s3c24xx/s3c2443-clock.c b/arch/arm/plat-s3c24xx/s3c2443-clock.c
index 82f2d4a39291..59552c0ea5fb 100644
--- a/arch/arm/plat-s3c24xx/s3c2443-clock.c
+++ b/arch/arm/plat-s3c24xx/s3c2443-clock.c
@@ -56,7 +56,6 @@ int s3c2443_clkcon_enable_s(struct clk *clk, int enable)
56struct clk clk_mpllref = { 56struct clk clk_mpllref = {
57 .name = "mpllref", 57 .name = "mpllref",
58 .parent = &clk_xtal, 58 .parent = &clk_xtal,
59 .id = -1,
60}; 59};
61 60
62static struct clk *clk_epllref_sources[] = { 61static struct clk *clk_epllref_sources[] = {
@@ -69,7 +68,6 @@ static struct clk *clk_epllref_sources[] = {
69struct clksrc_clk clk_epllref = { 68struct clksrc_clk clk_epllref = {
70 .clk = { 69 .clk = {
71 .name = "epllref", 70 .name = "epllref",
72 .id = -1,
73 }, 71 },
74 .sources = &(struct clksrc_sources) { 72 .sources = &(struct clksrc_sources) {
75 .sources = clk_epllref_sources, 73 .sources = clk_epllref_sources,
@@ -92,7 +90,6 @@ struct clksrc_clk clk_esysclk = {
92 .clk = { 90 .clk = {
93 .name = "esysclk", 91 .name = "esysclk",
94 .parent = &clk_epll, 92 .parent = &clk_epll,
95 .id = -1,
96 }, 93 },
97 .sources = &(struct clksrc_sources) { 94 .sources = &(struct clksrc_sources) {
98 .sources = clk_sysclk_sources, 95 .sources = clk_sysclk_sources,
@@ -115,7 +112,6 @@ static unsigned long s3c2443_getrate_mdivclk(struct clk *clk)
115static struct clk clk_mdivclk = { 112static struct clk clk_mdivclk = {
116 .name = "mdivclk", 113 .name = "mdivclk",
117 .parent = &clk_mpllref, 114 .parent = &clk_mpllref,
118 .id = -1,
119 .ops = &(struct clk_ops) { 115 .ops = &(struct clk_ops) {
120 .get_rate = s3c2443_getrate_mdivclk, 116 .get_rate = s3c2443_getrate_mdivclk,
121 }, 117 },
@@ -132,7 +128,6 @@ struct clksrc_clk clk_msysclk = {
132 .clk = { 128 .clk = {
133 .name = "msysclk", 129 .name = "msysclk",
134 .parent = &clk_xtal, 130 .parent = &clk_xtal,
135 .id = -1,
136 }, 131 },
137 .sources = &(struct clksrc_sources) { 132 .sources = &(struct clksrc_sources) {
138 .sources = clk_msysclk_sources, 133 .sources = clk_msysclk_sources,
@@ -159,7 +154,6 @@ static unsigned long s3c2443_prediv_getrate(struct clk *clk)
159 154
160static struct clk clk_prediv = { 155static struct clk clk_prediv = {
161 .name = "prediv", 156 .name = "prediv",
162 .id = -1,
163 .parent = &clk_msysclk.clk, 157 .parent = &clk_msysclk.clk,
164 .ops = &(struct clk_ops) { 158 .ops = &(struct clk_ops) {
165 .get_rate = s3c2443_prediv_getrate, 159 .get_rate = s3c2443_prediv_getrate,
@@ -174,7 +168,6 @@ static struct clk clk_prediv = {
174static struct clksrc_clk clk_usb_bus_host = { 168static struct clksrc_clk clk_usb_bus_host = {
175 .clk = { 169 .clk = {
176 .name = "usb-bus-host-parent", 170 .name = "usb-bus-host-parent",
177 .id = -1,
178 .parent = &clk_esysclk.clk, 171 .parent = &clk_esysclk.clk,
179 .ctrlbit = S3C2443_SCLKCON_USBHOST, 172 .ctrlbit = S3C2443_SCLKCON_USBHOST,
180 .enable = s3c2443_clkcon_enable_s, 173 .enable = s3c2443_clkcon_enable_s,
@@ -189,7 +182,6 @@ static struct clksrc_clk clksrc_clks[] = {
189 /* ART baud-rate clock sourced from esysclk via a divisor */ 182 /* ART baud-rate clock sourced from esysclk via a divisor */
190 .clk = { 183 .clk = {
191 .name = "uartclk", 184 .name = "uartclk",
192 .id = -1,
193 .parent = &clk_esysclk.clk, 185 .parent = &clk_esysclk.clk,
194 }, 186 },
195 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 }, 187 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 },
@@ -197,7 +189,6 @@ static struct clksrc_clk clksrc_clks[] = {
197 /* camera interface bus-clock, divided down from esysclk */ 189 /* camera interface bus-clock, divided down from esysclk */
198 .clk = { 190 .clk = {
199 .name = "camif-upll", /* same as 2440 name */ 191 .name = "camif-upll", /* same as 2440 name */
200 .id = -1,
201 .parent = &clk_esysclk.clk, 192 .parent = &clk_esysclk.clk,
202 .ctrlbit = S3C2443_SCLKCON_CAMCLK, 193 .ctrlbit = S3C2443_SCLKCON_CAMCLK,
203 .enable = s3c2443_clkcon_enable_s, 194 .enable = s3c2443_clkcon_enable_s,
@@ -206,7 +197,6 @@ static struct clksrc_clk clksrc_clks[] = {
206 }, { 197 }, {
207 .clk = { 198 .clk = {
208 .name = "display-if", 199 .name = "display-if",
209 .id = -1,
210 .parent = &clk_esysclk.clk, 200 .parent = &clk_esysclk.clk,
211 .ctrlbit = S3C2443_SCLKCON_DISPCLK, 201 .ctrlbit = S3C2443_SCLKCON_DISPCLK,
212 .enable = s3c2443_clkcon_enable_s, 202 .enable = s3c2443_clkcon_enable_s,
@@ -219,13 +209,11 @@ static struct clksrc_clk clksrc_clks[] = {
219static struct clk init_clocks_off[] = { 209static struct clk init_clocks_off[] = {
220 { 210 {
221 .name = "adc", 211 .name = "adc",
222 .id = -1,
223 .parent = &clk_p, 212 .parent = &clk_p,
224 .enable = s3c2443_clkcon_enable_p, 213 .enable = s3c2443_clkcon_enable_p,
225 .ctrlbit = S3C2443_PCLKCON_ADC, 214 .ctrlbit = S3C2443_PCLKCON_ADC,
226 }, { 215 }, {
227 .name = "i2c", 216 .name = "i2c",
228 .id = -1,
229 .parent = &clk_p, 217 .parent = &clk_p,
230 .enable = s3c2443_clkcon_enable_p, 218 .enable = s3c2443_clkcon_enable_p,
231 .ctrlbit = S3C2443_PCLKCON_IIC, 219 .ctrlbit = S3C2443_PCLKCON_IIC,
@@ -235,136 +223,117 @@ static struct clk init_clocks_off[] = {
235static struct clk init_clocks[] = { 223static struct clk init_clocks[] = {
236 { 224 {
237 .name = "dma", 225 .name = "dma",
238 .id = 0,
239 .parent = &clk_h, 226 .parent = &clk_h,
240 .enable = s3c2443_clkcon_enable_h, 227 .enable = s3c2443_clkcon_enable_h,
241 .ctrlbit = S3C2443_HCLKCON_DMA0, 228 .ctrlbit = S3C2443_HCLKCON_DMA0,
242 }, { 229 }, {
243 .name = "dma", 230 .name = "dma",
244 .id = 1,
245 .parent = &clk_h, 231 .parent = &clk_h,
246 .enable = s3c2443_clkcon_enable_h, 232 .enable = s3c2443_clkcon_enable_h,
247 .ctrlbit = S3C2443_HCLKCON_DMA1, 233 .ctrlbit = S3C2443_HCLKCON_DMA1,
248 }, { 234 }, {
249 .name = "dma", 235 .name = "dma",
250 .id = 2,
251 .parent = &clk_h, 236 .parent = &clk_h,
252 .enable = s3c2443_clkcon_enable_h, 237 .enable = s3c2443_clkcon_enable_h,
253 .ctrlbit = S3C2443_HCLKCON_DMA2, 238 .ctrlbit = S3C2443_HCLKCON_DMA2,
254 }, { 239 }, {
255 .name = "dma", 240 .name = "dma",
256 .id = 3,
257 .parent = &clk_h, 241 .parent = &clk_h,
258 .enable = s3c2443_clkcon_enable_h, 242 .enable = s3c2443_clkcon_enable_h,
259 .ctrlbit = S3C2443_HCLKCON_DMA3, 243 .ctrlbit = S3C2443_HCLKCON_DMA3,
260 }, { 244 }, {
261 .name = "dma", 245 .name = "dma",
262 .id = 4,
263 .parent = &clk_h, 246 .parent = &clk_h,
264 .enable = s3c2443_clkcon_enable_h, 247 .enable = s3c2443_clkcon_enable_h,
265 .ctrlbit = S3C2443_HCLKCON_DMA4, 248 .ctrlbit = S3C2443_HCLKCON_DMA4,
266 }, { 249 }, {
267 .name = "dma", 250 .name = "dma",
268 .id = 5,
269 .parent = &clk_h, 251 .parent = &clk_h,
270 .enable = s3c2443_clkcon_enable_h, 252 .enable = s3c2443_clkcon_enable_h,
271 .ctrlbit = S3C2443_HCLKCON_DMA5, 253 .ctrlbit = S3C2443_HCLKCON_DMA5,
272 }, { 254 }, {
273 .name = "hsmmc", 255 .name = "hsmmc",
274 .id = 1,
275 .parent = &clk_h, 256 .parent = &clk_h,
276 .enable = s3c2443_clkcon_enable_h, 257 .enable = s3c2443_clkcon_enable_h,
277 .ctrlbit = S3C2443_HCLKCON_HSMMC, 258 .ctrlbit = S3C2443_HCLKCON_HSMMC,
278 }, { 259 }, {
279 .name = "gpio", 260 .name = "gpio",
280 .id = -1,
281 .parent = &clk_p, 261 .parent = &clk_p,
282 .enable = s3c2443_clkcon_enable_p, 262 .enable = s3c2443_clkcon_enable_p,
283 .ctrlbit = S3C2443_PCLKCON_GPIO, 263 .ctrlbit = S3C2443_PCLKCON_GPIO,
284 }, { 264 }, {
285 .name = "usb-host", 265 .name = "usb-host",
286 .id = -1,
287 .parent = &clk_h, 266 .parent = &clk_h,
288 .enable = s3c2443_clkcon_enable_h, 267 .enable = s3c2443_clkcon_enable_h,
289 .ctrlbit = S3C2443_HCLKCON_USBH, 268 .ctrlbit = S3C2443_HCLKCON_USBH,
290 }, { 269 }, {
291 .name = "usb-device", 270 .name = "usb-device",
292 .id = -1,
293 .parent = &clk_h, 271 .parent = &clk_h,
294 .enable = s3c2443_clkcon_enable_h, 272 .enable = s3c2443_clkcon_enable_h,
295 .ctrlbit = S3C2443_HCLKCON_USBD, 273 .ctrlbit = S3C2443_HCLKCON_USBD,
296 }, { 274 }, {
297 .name = "lcd", 275 .name = "lcd",
298 .id = -1,
299 .parent = &clk_h, 276 .parent = &clk_h,
300 .enable = s3c2443_clkcon_enable_h, 277 .enable = s3c2443_clkcon_enable_h,
301 .ctrlbit = S3C2443_HCLKCON_LCDC, 278 .ctrlbit = S3C2443_HCLKCON_LCDC,
302 279
303 }, { 280 }, {
304 .name = "timers", 281 .name = "timers",
305 .id = -1,
306 .parent = &clk_p, 282 .parent = &clk_p,
307 .enable = s3c2443_clkcon_enable_p, 283 .enable = s3c2443_clkcon_enable_p,
308 .ctrlbit = S3C2443_PCLKCON_PWMT, 284 .ctrlbit = S3C2443_PCLKCON_PWMT,
309 }, { 285 }, {
310 .name = "cfc", 286 .name = "cfc",
311 .id = -1,
312 .parent = &clk_h, 287 .parent = &clk_h,
313 .enable = s3c2443_clkcon_enable_h, 288 .enable = s3c2443_clkcon_enable_h,
314 .ctrlbit = S3C2443_HCLKCON_CFC, 289 .ctrlbit = S3C2443_HCLKCON_CFC,
315 }, { 290 }, {
316 .name = "ssmc", 291 .name = "ssmc",
317 .id = -1,
318 .parent = &clk_h, 292 .parent = &clk_h,
319 .enable = s3c2443_clkcon_enable_h, 293 .enable = s3c2443_clkcon_enable_h,
320 .ctrlbit = S3C2443_HCLKCON_SSMC, 294 .ctrlbit = S3C2443_HCLKCON_SSMC,
321 }, { 295 }, {
322 .name = "uart", 296 .name = "uart",
323 .id = 0, 297 .devname = "s3c2440-uart.0",
324 .parent = &clk_p, 298 .parent = &clk_p,
325 .enable = s3c2443_clkcon_enable_p, 299 .enable = s3c2443_clkcon_enable_p,
326 .ctrlbit = S3C2443_PCLKCON_UART0, 300 .ctrlbit = S3C2443_PCLKCON_UART0,
327 }, { 301 }, {
328 .name = "uart", 302 .name = "uart",
329 .id = 1, 303 .devname = "s3c2440-uart.1",
330 .parent = &clk_p, 304 .parent = &clk_p,
331 .enable = s3c2443_clkcon_enable_p, 305 .enable = s3c2443_clkcon_enable_p,
332 .ctrlbit = S3C2443_PCLKCON_UART1, 306 .ctrlbit = S3C2443_PCLKCON_UART1,
333 }, { 307 }, {
334 .name = "uart", 308 .name = "uart",
335 .id = 2, 309 .devname = "s3c2440-uart.2",
336 .parent = &clk_p, 310 .parent = &clk_p,
337 .enable = s3c2443_clkcon_enable_p, 311 .enable = s3c2443_clkcon_enable_p,
338 .ctrlbit = S3C2443_PCLKCON_UART2, 312 .ctrlbit = S3C2443_PCLKCON_UART2,
339 }, { 313 }, {
340 .name = "uart", 314 .name = "uart",
341 .id = 3, 315 .devname = "s3c2440-uart.3",
342 .parent = &clk_p, 316 .parent = &clk_p,
343 .enable = s3c2443_clkcon_enable_p, 317 .enable = s3c2443_clkcon_enable_p,
344 .ctrlbit = S3C2443_PCLKCON_UART3, 318 .ctrlbit = S3C2443_PCLKCON_UART3,
345 }, { 319 }, {
346 .name = "rtc", 320 .name = "rtc",
347 .id = -1,
348 .parent = &clk_p, 321 .parent = &clk_p,
349 .enable = s3c2443_clkcon_enable_p, 322 .enable = s3c2443_clkcon_enable_p,
350 .ctrlbit = S3C2443_PCLKCON_RTC, 323 .ctrlbit = S3C2443_PCLKCON_RTC,
351 }, { 324 }, {
352 .name = "watchdog", 325 .name = "watchdog",
353 .id = -1,
354 .parent = &clk_p, 326 .parent = &clk_p,
355 .ctrlbit = S3C2443_PCLKCON_WDT, 327 .ctrlbit = S3C2443_PCLKCON_WDT,
356 }, { 328 }, {
357 .name = "ac97", 329 .name = "ac97",
358 .id = -1,
359 .parent = &clk_p, 330 .parent = &clk_p,
360 .ctrlbit = S3C2443_PCLKCON_AC97, 331 .ctrlbit = S3C2443_PCLKCON_AC97,
361 }, { 332 }, {
362 .name = "nand", 333 .name = "nand",
363 .id = -1,
364 .parent = &clk_h, 334 .parent = &clk_h,
365 }, { 335 }, {
366 .name = "usb-bus-host", 336 .name = "usb-bus-host",
367 .id = -1,
368 .parent = &clk_usb_bus_host.clk, 337 .parent = &clk_usb_bus_host.clk,
369 } 338 }
370}; 339};
diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c
index e30bd4591a30..aecf9e90d4fc 100644
--- a/arch/arm/plat-samsung/clock.c
+++ b/arch/arm/plat-samsung/clock.c
@@ -195,7 +195,6 @@ struct clk_ops clk_ops_def_setrate = {
195 195
196struct clk clk_xtal = { 196struct clk clk_xtal = {
197 .name = "xtal", 197 .name = "xtal",
198 .id = -1,
199 .rate = 0, 198 .rate = 0,
200 .parent = NULL, 199 .parent = NULL,
201 .ctrlbit = 0, 200 .ctrlbit = 0,
@@ -203,30 +202,25 @@ struct clk clk_xtal = {
203 202
204struct clk clk_ext = { 203struct clk clk_ext = {
205 .name = "ext", 204 .name = "ext",
206 .id = -1,
207}; 205};
208 206
209struct clk clk_epll = { 207struct clk clk_epll = {
210 .name = "epll", 208 .name = "epll",
211 .id = -1,
212}; 209};
213 210
214struct clk clk_mpll = { 211struct clk clk_mpll = {
215 .name = "mpll", 212 .name = "mpll",
216 .id = -1,
217 .ops = &clk_ops_def_setrate, 213 .ops = &clk_ops_def_setrate,
218}; 214};
219 215
220struct clk clk_upll = { 216struct clk clk_upll = {
221 .name = "upll", 217 .name = "upll",
222 .id = -1,
223 .parent = NULL, 218 .parent = NULL,
224 .ctrlbit = 0, 219 .ctrlbit = 0,
225}; 220};
226 221
227struct clk clk_f = { 222struct clk clk_f = {
228 .name = "fclk", 223 .name = "fclk",
229 .id = -1,
230 .rate = 0, 224 .rate = 0,
231 .parent = &clk_mpll, 225 .parent = &clk_mpll,
232 .ctrlbit = 0, 226 .ctrlbit = 0,
@@ -234,7 +228,6 @@ struct clk clk_f = {
234 228
235struct clk clk_h = { 229struct clk clk_h = {
236 .name = "hclk", 230 .name = "hclk",
237 .id = -1,
238 .rate = 0, 231 .rate = 0,
239 .parent = NULL, 232 .parent = NULL,
240 .ctrlbit = 0, 233 .ctrlbit = 0,
@@ -243,7 +236,6 @@ struct clk clk_h = {
243 236
244struct clk clk_p = { 237struct clk clk_p = {
245 .name = "pclk", 238 .name = "pclk",
246 .id = -1,
247 .rate = 0, 239 .rate = 0,
248 .parent = NULL, 240 .parent = NULL,
249 .ctrlbit = 0, 241 .ctrlbit = 0,
@@ -252,7 +244,6 @@ struct clk clk_p = {
252 244
253struct clk clk_usb_bus = { 245struct clk clk_usb_bus = {
254 .name = "usb-bus", 246 .name = "usb-bus",
255 .id = -1,
256 .rate = 0, 247 .rate = 0,
257 .parent = &clk_upll, 248 .parent = &clk_upll,
258}; 249};
@@ -260,7 +251,6 @@ struct clk clk_usb_bus = {
260 251
261struct clk s3c24xx_uclk = { 252struct clk s3c24xx_uclk = {
262 .name = "uclk", 253 .name = "uclk",
263 .id = -1,
264}; 254};
265 255
266/* initialise the clock system */ 256/* initialise the clock system */
diff --git a/arch/arm/plat-samsung/pwm-clock.c b/arch/arm/plat-samsung/pwm-clock.c
index 46c9381e083b..f1bba88ed2f5 100644
--- a/arch/arm/plat-samsung/pwm-clock.c
+++ b/arch/arm/plat-samsung/pwm-clock.c
@@ -268,6 +268,7 @@ static struct pwm_tdiv_clk clk_timer_tdiv[] = {
268 [0] = { 268 [0] = {
269 .clk = { 269 .clk = {
270 .name = "pwm-tdiv", 270 .name = "pwm-tdiv",
271 .devname = "s3c24xx-pwm.0",
271 .ops = &clk_tdiv_ops, 272 .ops = &clk_tdiv_ops,
272 .parent = &clk_timer_scaler[0], 273 .parent = &clk_timer_scaler[0],
273 }, 274 },
@@ -275,6 +276,7 @@ static struct pwm_tdiv_clk clk_timer_tdiv[] = {
275 [1] = { 276 [1] = {
276 .clk = { 277 .clk = {
277 .name = "pwm-tdiv", 278 .name = "pwm-tdiv",
279 .devname = "s3c24xx-pwm.1",
278 .ops = &clk_tdiv_ops, 280 .ops = &clk_tdiv_ops,
279 .parent = &clk_timer_scaler[0], 281 .parent = &clk_timer_scaler[0],
280 } 282 }
@@ -282,6 +284,7 @@ static struct pwm_tdiv_clk clk_timer_tdiv[] = {
282 [2] = { 284 [2] = {
283 .clk = { 285 .clk = {
284 .name = "pwm-tdiv", 286 .name = "pwm-tdiv",
287 .devname = "s3c24xx-pwm.2",
285 .ops = &clk_tdiv_ops, 288 .ops = &clk_tdiv_ops,
286 .parent = &clk_timer_scaler[1], 289 .parent = &clk_timer_scaler[1],
287 }, 290 },
@@ -289,6 +292,7 @@ static struct pwm_tdiv_clk clk_timer_tdiv[] = {
289 [3] = { 292 [3] = {
290 .clk = { 293 .clk = {
291 .name = "pwm-tdiv", 294 .name = "pwm-tdiv",
295 .devname = "s3c24xx-pwm.3",
292 .ops = &clk_tdiv_ops, 296 .ops = &clk_tdiv_ops,
293 .parent = &clk_timer_scaler[1], 297 .parent = &clk_timer_scaler[1],
294 }, 298 },
@@ -296,6 +300,7 @@ static struct pwm_tdiv_clk clk_timer_tdiv[] = {
296 [4] = { 300 [4] = {
297 .clk = { 301 .clk = {
298 .name = "pwm-tdiv", 302 .name = "pwm-tdiv",
303 .devname = "s3c24xx-pwm.4",
299 .ops = &clk_tdiv_ops, 304 .ops = &clk_tdiv_ops,
300 .parent = &clk_timer_scaler[1], 305 .parent = &clk_timer_scaler[1],
301 }, 306 },
@@ -361,26 +366,31 @@ static struct clk_ops clk_tin_ops = {
361static struct clk clk_tin[] = { 366static struct clk clk_tin[] = {
362 [0] = { 367 [0] = {
363 .name = "pwm-tin", 368 .name = "pwm-tin",
369 .devname = "s3c24xx-pwm.0",
364 .id = 0, 370 .id = 0,
365 .ops = &clk_tin_ops, 371 .ops = &clk_tin_ops,
366 }, 372 },
367 [1] = { 373 [1] = {
368 .name = "pwm-tin", 374 .name = "pwm-tin",
375 .devname = "s3c24xx-pwm.1",
369 .id = 1, 376 .id = 1,
370 .ops = &clk_tin_ops, 377 .ops = &clk_tin_ops,
371 }, 378 },
372 [2] = { 379 [2] = {
373 .name = "pwm-tin", 380 .name = "pwm-tin",
381 .devname = "s3c24xx-pwm.2",
374 .id = 2, 382 .id = 2,
375 .ops = &clk_tin_ops, 383 .ops = &clk_tin_ops,
376 }, 384 },
377 [3] = { 385 [3] = {
378 .name = "pwm-tin", 386 .name = "pwm-tin",
387 .devname = "s3c24xx-pwm.3",
379 .id = 3, 388 .id = 3,
380 .ops = &clk_tin_ops, 389 .ops = &clk_tin_ops,
381 }, 390 },
382 [4] = { 391 [4] = {
383 .name = "pwm-tin", 392 .name = "pwm-tin",
393 .devname = "s3c24xx-pwm.4",
384 .id = 4, 394 .id = 4,
385 .ops = &clk_tin_ops, 395 .ops = &clk_tin_ops,
386 }, 396 },
diff --git a/arch/arm/plat-samsung/time.c b/arch/arm/plat-samsung/time.c
index 2231d80ad817..e3bb806bbafe 100644
--- a/arch/arm/plat-samsung/time.c
+++ b/arch/arm/plat-samsung/time.c
@@ -259,6 +259,8 @@ static void __init s3c2410_timer_resources(void)
259 clk_enable(timerclk); 259 clk_enable(timerclk);
260 260
261 if (!use_tclk1_12()) { 261 if (!use_tclk1_12()) {
262 tmpdev.id = 4;
263 tmpdev.dev.init_name = "s3c24xx-pwm.4";
262 tin = clk_get(&tmpdev.dev, "pwm-tin"); 264 tin = clk_get(&tmpdev.dev, "pwm-tin");
263 if (IS_ERR(tin)) 265 if (IS_ERR(tin))
264 panic("failed to get pwm-tin clock for system timer"); 266 panic("failed to get pwm-tin clock for system timer");
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 11:19:03 -0500