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authorMichael Ellerman <michael@ellerman.id.au>2012-10-30 12:09:56 -0400
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2012-11-14 21:00:36 -0500
commitda111957796515755d95ec6773dc714350724a4e (patch)
tree4854509b69457adb40f1a82fb853920208c99238 /arch
parentbb29b719372742939af05457aff1b59608764e89 (diff)
powerpc/perf: Add missing L2 constraint handling in Power7 PMU
If we have two cache events that require different settings of the L2SEL bits in MMCR1 then we can not schedule those events simultaneously. Add logic to the constraint handling to express that. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/perf/power7-pmu.c17
1 files changed, 14 insertions, 3 deletions
diff --git a/arch/powerpc/perf/power7-pmu.c b/arch/powerpc/perf/power7-pmu.c
index 441af08edf43..2ee01e38d5e2 100644
--- a/arch/powerpc/perf/power7-pmu.c
+++ b/arch/powerpc/perf/power7-pmu.c
@@ -54,8 +54,10 @@
54 * Layout of constraint bits: 54 * Layout of constraint bits:
55 * 6666555555555544444444443333333333222222222211111111110000000000 55 * 6666555555555544444444443333333333222222222211111111110000000000
56 * 3210987654321098765432109876543210987654321098765432109876543210 56 * 3210987654321098765432109876543210987654321098765432109876543210
57 * [ ><><><><><><> 57 * < >< ><><><><><><>
58 * NC P6P5P4P3P2P1 58 * L2 NC P6P5P4P3P2P1
59 *
60 * L2 - 16-18 - Required L2SEL value (select field)
59 * 61 *
60 * NC - number of counters 62 * NC - number of counters
61 * 15: NC error 0x8000 63 * 15: NC error 0x8000
@@ -72,7 +74,7 @@
72static int power7_get_constraint(u64 event, unsigned long *maskp, 74static int power7_get_constraint(u64 event, unsigned long *maskp,
73 unsigned long *valp) 75 unsigned long *valp)
74{ 76{
75 int pmc, sh; 77 int pmc, sh, unit;
76 unsigned long mask = 0, value = 0; 78 unsigned long mask = 0, value = 0;
77 79
78 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; 80 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
@@ -90,6 +92,15 @@ static int power7_get_constraint(u64 event, unsigned long *maskp,
90 mask |= 0x8000; 92 mask |= 0x8000;
91 value |= 0x1000; 93 value |= 0x1000;
92 } 94 }
95
96 unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
97 if (unit == 6) {
98 /* L2SEL must be identical across events */
99 int l2sel = (event >> PM_L2SEL_SH) & PM_L2SEL_MSK;
100 mask |= 0x7 << 16;
101 value |= l2sel << 16;
102 }
103
93 *maskp = mask; 104 *maskp = mask;
94 *valp = value; 105 *valp = value;
95 return 0; 106 return 0;