aboutsummaryrefslogtreecommitdiffstats
path: root/arch
diff options
context:
space:
mode:
authorRussell King <rmk@dyn-67.arm.linux.org.uk>2009-01-18 18:03:15 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2009-02-08 12:50:13 -0500
commitd7e8f1f9d655af2c7ea90738bf567aa6990159b3 (patch)
tree6ee9ce41a078c8f6501236c258a52ca0ed8c355d /arch
parentdbb674d57b5851a4fe3122ff4280e4cf87209198 (diff)
[ARM] omap: convert OMAP1 to use clkdev
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-omap1/clock.c117
-rw-r--r--arch/arm/mach-omap1/clock.h164
-rw-r--r--arch/arm/plat-omap/Kconfig1
-rw-r--r--arch/arm/plat-omap/clock.c4
-rw-r--r--arch/arm/plat-omap/include/mach/clkdev.h13
-rw-r--r--arch/arm/plat-omap/include/mach/clock.h6
6 files changed, 145 insertions, 160 deletions
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
index 6b17da120e5f..829b9b845b85 100644
--- a/arch/arm/mach-omap1/clock.c
+++ b/arch/arm/mach-omap1/clock.c
@@ -20,6 +20,7 @@
20#include <linux/io.h> 20#include <linux/io.h>
21 21
22#include <asm/mach-types.h> 22#include <asm/mach-types.h>
23#include <asm/clkdev.h>
23 24
24#include <mach/cpu.h> 25#include <mach/cpu.h>
25#include <mach/usb.h> 26#include <mach/usb.h>
@@ -32,6 +33,83 @@ static const struct clkops clkops_dspck;
32 33
33#include "clock.h" 34#include "clock.h"
34 35
36struct omap_clk {
37 u32 cpu;
38 struct clk_lookup lk;
39};
40
41#define CLK(dev, con, ck, cp) \
42 { \
43 .cpu = cp, \
44 .lk = { \
45 .dev_id = dev, \
46 .con_id = con, \
47 .clk = ck, \
48 }, \
49 }
50
51#define CK_310 (1 << 0)
52#define CK_730 (1 << 1)
53#define CK_1510 (1 << 2)
54#define CK_16XX (1 << 3)
55
56static struct omap_clk omap_clks[] = {
57 /* non-ULPD clocks */
58 CLK(NULL, "ck_ref", &ck_ref, CK_16XX | CK_1510 | CK_310),
59 CLK(NULL, "ck_dpll1", &ck_dpll1, CK_16XX | CK_1510 | CK_310),
60 /* CK_GEN1 clocks */
61 CLK(NULL, "ck_dpll1out", &ck_dpll1out.clk, CK_16XX),
62 CLK(NULL, "ck_sossi", &sossi_ck, CK_16XX),
63 CLK(NULL, "arm_ck", &arm_ck, CK_16XX | CK_1510 | CK_310),
64 CLK(NULL, "armper_ck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
65 CLK(NULL, "arm_gpio_ck", &arm_gpio_ck, CK_1510 | CK_310),
66 CLK(NULL, "armxor_ck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310),
67 CLK(NULL, "armtim_ck", &armtim_ck.clk, CK_16XX | CK_1510 | CK_310),
68 CLK(NULL, "armwdt_ck", &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310),
69 CLK(NULL, "arminth_ck", &arminth_ck1510, CK_1510 | CK_310),
70 CLK(NULL, "arminth_ck", &arminth_ck16xx, CK_16XX),
71 /* CK_GEN2 clocks */
72 CLK(NULL, "dsp_ck", &dsp_ck, CK_16XX | CK_1510 | CK_310),
73 CLK(NULL, "dspmmu_ck", &dspmmu_ck, CK_16XX | CK_1510 | CK_310),
74 CLK(NULL, "dspper_ck", &dspper_ck, CK_16XX | CK_1510 | CK_310),
75 CLK(NULL, "dspxor_ck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
76 CLK(NULL, "dsptim_ck", &dsptim_ck, CK_16XX | CK_1510 | CK_310),
77 /* CK_GEN3 clocks */
78 CLK(NULL, "tc_ck", &tc_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_730),
79 CLK(NULL, "tipb_ck", &tipb_ck, CK_1510 | CK_310),
80 CLK(NULL, "l3_ocpi_ck", &l3_ocpi_ck, CK_16XX),
81 CLK(NULL, "tc1_ck", &tc1_ck, CK_16XX),
82 CLK(NULL, "tc2_ck", &tc2_ck, CK_16XX),
83 CLK(NULL, "dma_ck", &dma_ck, CK_16XX | CK_1510 | CK_310),
84 CLK(NULL, "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX),
85 CLK(NULL, "api_ck", &api_ck.clk, CK_16XX | CK_1510 | CK_310),
86 CLK(NULL, "lb_ck", &lb_ck.clk, CK_1510 | CK_310),
87 CLK(NULL, "rhea1_ck", &rhea1_ck, CK_16XX),
88 CLK(NULL, "rhea2_ck", &rhea2_ck, CK_16XX),
89 CLK(NULL, "lcd_ck", &lcd_ck_16xx, CK_16XX | CK_730),
90 CLK(NULL, "lcd_ck", &lcd_ck_1510.clk, CK_1510 | CK_310),
91 /* ULPD clocks */
92 CLK(NULL, "uart1_ck", &uart1_1510, CK_1510 | CK_310),
93 CLK(NULL, "uart1_ck", &uart1_16xx.clk, CK_16XX),
94 CLK(NULL, "uart2_ck", &uart2_ck, CK_16XX | CK_1510 | CK_310),
95 CLK(NULL, "uart3_ck", &uart3_1510, CK_1510 | CK_310),
96 CLK(NULL, "uart3_ck", &uart3_16xx.clk, CK_16XX),
97 CLK(NULL, "usb_clko", &usb_clko, CK_16XX | CK_1510 | CK_310),
98 CLK(NULL, "usb_hhc_ck", &usb_hhc_ck1510, CK_1510 | CK_310),
99 CLK(NULL, "usb_hhc_ck", &usb_hhc_ck16xx, CK_16XX),
100 CLK(NULL, "usb_dc_ck", &usb_dc_ck, CK_16XX),
101 CLK(NULL, "mclk", &mclk_1510, CK_1510 | CK_310),
102 CLK(NULL, "mclk", &mclk_16xx, CK_16XX),
103 CLK(NULL, "bclk", &bclk_1510, CK_1510 | CK_310),
104 CLK(NULL, "bclk", &bclk_16xx, CK_16XX),
105 CLK("mmci-omap.0", "mmc_ck", &mmc1_ck, CK_16XX | CK_1510 | CK_310),
106 CLK("mmci-omap.1", "mmc_ck", &mmc2_ck, CK_16XX),
107 /* Virtual clocks */
108 CLK(NULL, "mpu", &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310),
109 CLK("i2c_omap.1", "i2c_fck", &i2c_fck, CK_16XX | CK_1510 | CK_310),
110 CLK("i2c_omap.1", "i2c_ick", &i2c_ick, CK_16XX),
111};
112
35static int omap1_clk_enable_generic(struct clk * clk); 113static int omap1_clk_enable_generic(struct clk * clk);
36static int omap1_clk_enable(struct clk *clk); 114static int omap1_clk_enable(struct clk *clk);
37static void omap1_clk_disable_generic(struct clk * clk); 115static void omap1_clk_disable_generic(struct clk * clk);
@@ -677,10 +755,10 @@ static struct clk_functions omap1_clk_functions = {
677 755
678int __init omap1_clk_init(void) 756int __init omap1_clk_init(void)
679{ 757{
680 struct clk ** clkp; 758 struct omap_clk *c;
681 const struct omap_clock_config *info; 759 const struct omap_clock_config *info;
682 int crystal_type = 0; /* Default 12 MHz */ 760 int crystal_type = 0; /* Default 12 MHz */
683 u32 reg; 761 u32 reg, cpu_mask;
684 762
685#ifdef CONFIG_DEBUG_LL 763#ifdef CONFIG_DEBUG_LL
686 /* Resets some clocks that may be left on from bootloader, 764 /* Resets some clocks that may be left on from bootloader,
@@ -700,27 +778,21 @@ int __init omap1_clk_init(void)
700 /* By default all idlect1 clocks are allowed to idle */ 778 /* By default all idlect1 clocks are allowed to idle */
701 arm_idlect1_mask = ~0; 779 arm_idlect1_mask = ~0;
702 780
703 for (clkp = onchip_clks; clkp < onchip_clks+ARRAY_SIZE(onchip_clks); clkp++) { 781 cpu_mask = 0;
704 if (((*clkp)->flags &CLOCK_IN_OMAP1510) && cpu_is_omap1510()) { 782 if (cpu_is_omap16xx())
705 clk_register(*clkp); 783 cpu_mask |= CK_16XX;
706 continue; 784 if (cpu_is_omap1510())
707 } 785 cpu_mask |= CK_1510;
708 786 if (cpu_is_omap730())
709 if (((*clkp)->flags &CLOCK_IN_OMAP16XX) && cpu_is_omap16xx()) { 787 cpu_mask |= CK_730;
710 clk_register(*clkp); 788 if (cpu_is_omap310())
711 continue; 789 cpu_mask |= CK_310;
712 } 790
713 791 for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
714 if (((*clkp)->flags &CLOCK_IN_OMAP730) && cpu_is_omap730()) { 792 if (c->cpu & cpu_mask) {
715 clk_register(*clkp); 793 clkdev_add(&c->lk);
716 continue; 794 clk_register(c->lk.clk);
717 }
718
719 if (((*clkp)->flags &CLOCK_IN_OMAP310) && cpu_is_omap310()) {
720 clk_register(*clkp);
721 continue;
722 } 795 }
723 }
724 796
725 info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config); 797 info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
726 if (info != NULL) { 798 if (info != NULL) {
@@ -831,4 +903,3 @@ int __init omap1_clk_init(void)
831 903
832 return 0; 904 return 0;
833} 905}
834
diff --git a/arch/arm/mach-omap1/clock.h b/arch/arm/mach-omap1/clock.h
index aa7b3d604ee9..ed343af5f121 100644
--- a/arch/arm/mach-omap1/clock.h
+++ b/arch/arm/mach-omap1/clock.h
@@ -149,16 +149,13 @@ static struct clk ck_ref = {
149 .name = "ck_ref", 149 .name = "ck_ref",
150 .ops = &clkops_null, 150 .ops = &clkops_null,
151 .rate = 12000000, 151 .rate = 12000000,
152 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
153 CLOCK_IN_OMAP310,
154}; 152};
155 153
156static struct clk ck_dpll1 = { 154static struct clk ck_dpll1 = {
157 .name = "ck_dpll1", 155 .name = "ck_dpll1",
158 .ops = &clkops_null, 156 .ops = &clkops_null,
159 .parent = &ck_ref, 157 .parent = &ck_ref,
160 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 158 .flags = RATE_PROPAGATES,
161 CLOCK_IN_OMAP310 | RATE_PROPAGATES,
162}; 159};
163 160
164static struct arm_idlect1_clk ck_dpll1out = { 161static struct arm_idlect1_clk ck_dpll1out = {
@@ -166,7 +163,7 @@ static struct arm_idlect1_clk ck_dpll1out = {
166 .name = "ck_dpll1out", 163 .name = "ck_dpll1out",
167 .ops = &clkops_generic, 164 .ops = &clkops_generic,
168 .parent = &ck_dpll1, 165 .parent = &ck_dpll1,
169 .flags = CLOCK_IN_OMAP16XX | CLOCK_IDLE_CONTROL | 166 .flags = CLOCK_IDLE_CONTROL |
170 ENABLE_REG_32BIT | RATE_PROPAGATES, 167 ENABLE_REG_32BIT | RATE_PROPAGATES,
171 .enable_reg = (void __iomem *)ARM_IDLECT2, 168 .enable_reg = (void __iomem *)ARM_IDLECT2,
172 .enable_bit = EN_CKOUT_ARM, 169 .enable_bit = EN_CKOUT_ARM,
@@ -179,8 +176,7 @@ static struct clk sossi_ck = {
179 .name = "ck_sossi", 176 .name = "ck_sossi",
180 .ops = &clkops_generic, 177 .ops = &clkops_generic,
181 .parent = &ck_dpll1out.clk, 178 .parent = &ck_dpll1out.clk,
182 .flags = CLOCK_IN_OMAP16XX | CLOCK_NO_IDLE_PARENT | 179 .flags = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT,
183 ENABLE_REG_32BIT,
184 .enable_reg = (void __iomem *)MOD_CONF_CTRL_1, 180 .enable_reg = (void __iomem *)MOD_CONF_CTRL_1,
185 .enable_bit = 16, 181 .enable_bit = 16,
186 .recalc = &omap1_sossi_recalc, 182 .recalc = &omap1_sossi_recalc,
@@ -191,8 +187,7 @@ static struct clk arm_ck = {
191 .name = "arm_ck", 187 .name = "arm_ck",
192 .ops = &clkops_null, 188 .ops = &clkops_null,
193 .parent = &ck_dpll1, 189 .parent = &ck_dpll1,
194 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 190 .flags = RATE_PROPAGATES,
195 CLOCK_IN_OMAP310 | RATE_PROPAGATES,
196 .rate_offset = CKCTL_ARMDIV_OFFSET, 191 .rate_offset = CKCTL_ARMDIV_OFFSET,
197 .recalc = &omap1_ckctl_recalc, 192 .recalc = &omap1_ckctl_recalc,
198 .round_rate = omap1_clk_round_rate_ckctl_arm, 193 .round_rate = omap1_clk_round_rate_ckctl_arm,
@@ -204,8 +199,7 @@ static struct arm_idlect1_clk armper_ck = {
204 .name = "armper_ck", 199 .name = "armper_ck",
205 .ops = &clkops_generic, 200 .ops = &clkops_generic,
206 .parent = &ck_dpll1, 201 .parent = &ck_dpll1,
207 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 202 .flags = CLOCK_IDLE_CONTROL,
208 CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
209 .enable_reg = (void __iomem *)ARM_IDLECT2, 203 .enable_reg = (void __iomem *)ARM_IDLECT2,
210 .enable_bit = EN_PERCK, 204 .enable_bit = EN_PERCK,
211 .rate_offset = CKCTL_PERDIV_OFFSET, 205 .rate_offset = CKCTL_PERDIV_OFFSET,
@@ -220,7 +214,6 @@ static struct clk arm_gpio_ck = {
220 .name = "arm_gpio_ck", 214 .name = "arm_gpio_ck",
221 .ops = &clkops_generic, 215 .ops = &clkops_generic,
222 .parent = &ck_dpll1, 216 .parent = &ck_dpll1,
223 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
224 .enable_reg = (void __iomem *)ARM_IDLECT2, 217 .enable_reg = (void __iomem *)ARM_IDLECT2,
225 .enable_bit = EN_GPIOCK, 218 .enable_bit = EN_GPIOCK,
226 .recalc = &followparent_recalc, 219 .recalc = &followparent_recalc,
@@ -231,8 +224,7 @@ static struct arm_idlect1_clk armxor_ck = {
231 .name = "armxor_ck", 224 .name = "armxor_ck",
232 .ops = &clkops_generic, 225 .ops = &clkops_generic,
233 .parent = &ck_ref, 226 .parent = &ck_ref,
234 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 227 .flags = CLOCK_IDLE_CONTROL,
235 CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
236 .enable_reg = (void __iomem *)ARM_IDLECT2, 228 .enable_reg = (void __iomem *)ARM_IDLECT2,
237 .enable_bit = EN_XORPCK, 229 .enable_bit = EN_XORPCK,
238 .recalc = &followparent_recalc, 230 .recalc = &followparent_recalc,
@@ -245,8 +237,7 @@ static struct arm_idlect1_clk armtim_ck = {
245 .name = "armtim_ck", 237 .name = "armtim_ck",
246 .ops = &clkops_generic, 238 .ops = &clkops_generic,
247 .parent = &ck_ref, 239 .parent = &ck_ref,
248 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 240 .flags = CLOCK_IDLE_CONTROL,
249 CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
250 .enable_reg = (void __iomem *)ARM_IDLECT2, 241 .enable_reg = (void __iomem *)ARM_IDLECT2,
251 .enable_bit = EN_TIMCK, 242 .enable_bit = EN_TIMCK,
252 .recalc = &followparent_recalc, 243 .recalc = &followparent_recalc,
@@ -259,8 +250,7 @@ static struct arm_idlect1_clk armwdt_ck = {
259 .name = "armwdt_ck", 250 .name = "armwdt_ck",
260 .ops = &clkops_generic, 251 .ops = &clkops_generic,
261 .parent = &ck_ref, 252 .parent = &ck_ref,
262 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 253 .flags = CLOCK_IDLE_CONTROL,
263 CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
264 .enable_reg = (void __iomem *)ARM_IDLECT2, 254 .enable_reg = (void __iomem *)ARM_IDLECT2,
265 .enable_bit = EN_WDTCK, 255 .enable_bit = EN_WDTCK,
266 .recalc = &omap1_watchdog_recalc, 256 .recalc = &omap1_watchdog_recalc,
@@ -272,7 +262,6 @@ static struct clk arminth_ck16xx = {
272 .name = "arminth_ck", 262 .name = "arminth_ck",
273 .ops = &clkops_null, 263 .ops = &clkops_null,
274 .parent = &arm_ck, 264 .parent = &arm_ck,
275 .flags = CLOCK_IN_OMAP16XX,
276 .recalc = &followparent_recalc, 265 .recalc = &followparent_recalc,
277 /* Note: On 16xx the frequency can be divided by 2 by programming 266 /* Note: On 16xx the frequency can be divided by 2 by programming
278 * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1 267 * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
@@ -285,7 +274,6 @@ static struct clk dsp_ck = {
285 .name = "dsp_ck", 274 .name = "dsp_ck",
286 .ops = &clkops_generic, 275 .ops = &clkops_generic,
287 .parent = &ck_dpll1, 276 .parent = &ck_dpll1,
288 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
289 .enable_reg = (void __iomem *)ARM_CKCTL, 277 .enable_reg = (void __iomem *)ARM_CKCTL,
290 .enable_bit = EN_DSPCK, 278 .enable_bit = EN_DSPCK,
291 .rate_offset = CKCTL_DSPDIV_OFFSET, 279 .rate_offset = CKCTL_DSPDIV_OFFSET,
@@ -298,7 +286,6 @@ static struct clk dspmmu_ck = {
298 .name = "dspmmu_ck", 286 .name = "dspmmu_ck",
299 .ops = &clkops_null, 287 .ops = &clkops_null,
300 .parent = &ck_dpll1, 288 .parent = &ck_dpll1,
301 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
302 .rate_offset = CKCTL_DSPMMUDIV_OFFSET, 289 .rate_offset = CKCTL_DSPMMUDIV_OFFSET,
303 .recalc = &omap1_ckctl_recalc, 290 .recalc = &omap1_ckctl_recalc,
304 .round_rate = omap1_clk_round_rate_ckctl_arm, 291 .round_rate = omap1_clk_round_rate_ckctl_arm,
@@ -309,8 +296,7 @@ static struct clk dspper_ck = {
309 .name = "dspper_ck", 296 .name = "dspper_ck",
310 .ops = &clkops_dspck, 297 .ops = &clkops_dspck,
311 .parent = &ck_dpll1, 298 .parent = &ck_dpll1,
312 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 299 .flags = VIRTUAL_IO_ADDRESS,
313 VIRTUAL_IO_ADDRESS,
314 .enable_reg = DSP_IDLECT2, 300 .enable_reg = DSP_IDLECT2,
315 .enable_bit = EN_PERCK, 301 .enable_bit = EN_PERCK,
316 .rate_offset = CKCTL_PERDIV_OFFSET, 302 .rate_offset = CKCTL_PERDIV_OFFSET,
@@ -323,8 +309,7 @@ static struct clk dspxor_ck = {
323 .name = "dspxor_ck", 309 .name = "dspxor_ck",
324 .ops = &clkops_dspck, 310 .ops = &clkops_dspck,
325 .parent = &ck_ref, 311 .parent = &ck_ref,
326 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 312 .flags = VIRTUAL_IO_ADDRESS,
327 VIRTUAL_IO_ADDRESS,
328 .enable_reg = DSP_IDLECT2, 313 .enable_reg = DSP_IDLECT2,
329 .enable_bit = EN_XORPCK, 314 .enable_bit = EN_XORPCK,
330 .recalc = &followparent_recalc, 315 .recalc = &followparent_recalc,
@@ -334,8 +319,7 @@ static struct clk dsptim_ck = {
334 .name = "dsptim_ck", 319 .name = "dsptim_ck",
335 .ops = &clkops_dspck, 320 .ops = &clkops_dspck,
336 .parent = &ck_ref, 321 .parent = &ck_ref,
337 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 322 .flags = VIRTUAL_IO_ADDRESS,
338 VIRTUAL_IO_ADDRESS,
339 .enable_reg = DSP_IDLECT2, 323 .enable_reg = DSP_IDLECT2,
340 .enable_bit = EN_DSPTIMCK, 324 .enable_bit = EN_DSPTIMCK,
341 .recalc = &followparent_recalc, 325 .recalc = &followparent_recalc,
@@ -347,9 +331,7 @@ static struct arm_idlect1_clk tc_ck = {
347 .name = "tc_ck", 331 .name = "tc_ck",
348 .ops = &clkops_null, 332 .ops = &clkops_null,
349 .parent = &ck_dpll1, 333 .parent = &ck_dpll1,
350 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 334 .flags = RATE_PROPAGATES | CLOCK_IDLE_CONTROL,
351 CLOCK_IN_OMAP730 | CLOCK_IN_OMAP310 |
352 RATE_PROPAGATES | CLOCK_IDLE_CONTROL,
353 .rate_offset = CKCTL_TCDIV_OFFSET, 335 .rate_offset = CKCTL_TCDIV_OFFSET,
354 .recalc = &omap1_ckctl_recalc, 336 .recalc = &omap1_ckctl_recalc,
355 .round_rate = omap1_clk_round_rate_ckctl_arm, 337 .round_rate = omap1_clk_round_rate_ckctl_arm,
@@ -362,7 +344,6 @@ static struct clk arminth_ck1510 = {
362 .name = "arminth_ck", 344 .name = "arminth_ck",
363 .ops = &clkops_null, 345 .ops = &clkops_null,
364 .parent = &tc_ck.clk, 346 .parent = &tc_ck.clk,
365 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
366 .recalc = &followparent_recalc, 347 .recalc = &followparent_recalc,
367 /* Note: On 1510 the frequency follows TC_CK 348 /* Note: On 1510 the frequency follows TC_CK
368 * 349 *
@@ -375,7 +356,6 @@ static struct clk tipb_ck = {
375 .name = "tipb_ck", 356 .name = "tipb_ck",
376 .ops = &clkops_null, 357 .ops = &clkops_null,
377 .parent = &tc_ck.clk, 358 .parent = &tc_ck.clk,
378 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
379 .recalc = &followparent_recalc, 359 .recalc = &followparent_recalc,
380}; 360};
381 361
@@ -384,7 +364,6 @@ static struct clk l3_ocpi_ck = {
384 .name = "l3_ocpi_ck", 364 .name = "l3_ocpi_ck",
385 .ops = &clkops_generic, 365 .ops = &clkops_generic,
386 .parent = &tc_ck.clk, 366 .parent = &tc_ck.clk,
387 .flags = CLOCK_IN_OMAP16XX,
388 .enable_reg = (void __iomem *)ARM_IDLECT3, 367 .enable_reg = (void __iomem *)ARM_IDLECT3,
389 .enable_bit = EN_OCPI_CK, 368 .enable_bit = EN_OCPI_CK,
390 .recalc = &followparent_recalc, 369 .recalc = &followparent_recalc,
@@ -394,7 +373,6 @@ static struct clk tc1_ck = {
394 .name = "tc1_ck", 373 .name = "tc1_ck",
395 .ops = &clkops_generic, 374 .ops = &clkops_generic,
396 .parent = &tc_ck.clk, 375 .parent = &tc_ck.clk,
397 .flags = CLOCK_IN_OMAP16XX,
398 .enable_reg = (void __iomem *)ARM_IDLECT3, 376 .enable_reg = (void __iomem *)ARM_IDLECT3,
399 .enable_bit = EN_TC1_CK, 377 .enable_bit = EN_TC1_CK,
400 .recalc = &followparent_recalc, 378 .recalc = &followparent_recalc,
@@ -404,7 +382,6 @@ static struct clk tc2_ck = {
404 .name = "tc2_ck", 382 .name = "tc2_ck",
405 .ops = &clkops_generic, 383 .ops = &clkops_generic,
406 .parent = &tc_ck.clk, 384 .parent = &tc_ck.clk,
407 .flags = CLOCK_IN_OMAP16XX,
408 .enable_reg = (void __iomem *)ARM_IDLECT3, 385 .enable_reg = (void __iomem *)ARM_IDLECT3,
409 .enable_bit = EN_TC2_CK, 386 .enable_bit = EN_TC2_CK,
410 .recalc = &followparent_recalc, 387 .recalc = &followparent_recalc,
@@ -415,8 +392,6 @@ static struct clk dma_ck = {
415 .name = "dma_ck", 392 .name = "dma_ck",
416 .ops = &clkops_null, 393 .ops = &clkops_null,
417 .parent = &tc_ck.clk, 394 .parent = &tc_ck.clk,
418 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
419 CLOCK_IN_OMAP310,
420 .recalc = &followparent_recalc, 395 .recalc = &followparent_recalc,
421}; 396};
422 397
@@ -424,7 +399,6 @@ static struct clk dma_lcdfree_ck = {
424 .name = "dma_lcdfree_ck", 399 .name = "dma_lcdfree_ck",
425 .ops = &clkops_null, 400 .ops = &clkops_null,
426 .parent = &tc_ck.clk, 401 .parent = &tc_ck.clk,
427 .flags = CLOCK_IN_OMAP16XX,
428 .recalc = &followparent_recalc, 402 .recalc = &followparent_recalc,
429}; 403};
430 404
@@ -433,8 +407,7 @@ static struct arm_idlect1_clk api_ck = {
433 .name = "api_ck", 407 .name = "api_ck",
434 .ops = &clkops_generic, 408 .ops = &clkops_generic,
435 .parent = &tc_ck.clk, 409 .parent = &tc_ck.clk,
436 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 410 .flags = CLOCK_IDLE_CONTROL,
437 CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
438 .enable_reg = (void __iomem *)ARM_IDLECT2, 411 .enable_reg = (void __iomem *)ARM_IDLECT2,
439 .enable_bit = EN_APICK, 412 .enable_bit = EN_APICK,
440 .recalc = &followparent_recalc, 413 .recalc = &followparent_recalc,
@@ -447,8 +420,7 @@ static struct arm_idlect1_clk lb_ck = {
447 .name = "lb_ck", 420 .name = "lb_ck",
448 .ops = &clkops_generic, 421 .ops = &clkops_generic,
449 .parent = &tc_ck.clk, 422 .parent = &tc_ck.clk,
450 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | 423 .flags = CLOCK_IDLE_CONTROL,
451 CLOCK_IDLE_CONTROL,
452 .enable_reg = (void __iomem *)ARM_IDLECT2, 424 .enable_reg = (void __iomem *)ARM_IDLECT2,
453 .enable_bit = EN_LBCK, 425 .enable_bit = EN_LBCK,
454 .recalc = &followparent_recalc, 426 .recalc = &followparent_recalc,
@@ -460,7 +432,6 @@ static struct clk rhea1_ck = {
460 .name = "rhea1_ck", 432 .name = "rhea1_ck",
461 .ops = &clkops_null, 433 .ops = &clkops_null,
462 .parent = &tc_ck.clk, 434 .parent = &tc_ck.clk,
463 .flags = CLOCK_IN_OMAP16XX,
464 .recalc = &followparent_recalc, 435 .recalc = &followparent_recalc,
465}; 436};
466 437
@@ -468,7 +439,6 @@ static struct clk rhea2_ck = {
468 .name = "rhea2_ck", 439 .name = "rhea2_ck",
469 .ops = &clkops_null, 440 .ops = &clkops_null,
470 .parent = &tc_ck.clk, 441 .parent = &tc_ck.clk,
471 .flags = CLOCK_IN_OMAP16XX,
472 .recalc = &followparent_recalc, 442 .recalc = &followparent_recalc,
473}; 443};
474 444
@@ -476,7 +446,6 @@ static struct clk lcd_ck_16xx = {
476 .name = "lcd_ck", 446 .name = "lcd_ck",
477 .ops = &clkops_generic, 447 .ops = &clkops_generic,
478 .parent = &ck_dpll1, 448 .parent = &ck_dpll1,
479 .flags = CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730,
480 .enable_reg = (void __iomem *)ARM_IDLECT2, 449 .enable_reg = (void __iomem *)ARM_IDLECT2,
481 .enable_bit = EN_LCDCK, 450 .enable_bit = EN_LCDCK,
482 .rate_offset = CKCTL_LCDDIV_OFFSET, 451 .rate_offset = CKCTL_LCDDIV_OFFSET,
@@ -490,8 +459,7 @@ static struct arm_idlect1_clk lcd_ck_1510 = {
490 .name = "lcd_ck", 459 .name = "lcd_ck",
491 .ops = &clkops_generic, 460 .ops = &clkops_generic,
492 .parent = &ck_dpll1, 461 .parent = &ck_dpll1,
493 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | 462 .flags = CLOCK_IDLE_CONTROL,
494 CLOCK_IDLE_CONTROL,
495 .enable_reg = (void __iomem *)ARM_IDLECT2, 463 .enable_reg = (void __iomem *)ARM_IDLECT2,
496 .enable_bit = EN_LCDCK, 464 .enable_bit = EN_LCDCK,
497 .rate_offset = CKCTL_LCDDIV_OFFSET, 465 .rate_offset = CKCTL_LCDDIV_OFFSET,
@@ -508,8 +476,7 @@ static struct clk uart1_1510 = {
508 /* Direct from ULPD, no real parent */ 476 /* Direct from ULPD, no real parent */
509 .parent = &armper_ck.clk, 477 .parent = &armper_ck.clk,
510 .rate = 12000000, 478 .rate = 12000000,
511 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | 479 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
512 ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
513 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, 480 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
514 .enable_bit = 29, /* Chooses between 12MHz and 48MHz */ 481 .enable_bit = 29, /* Chooses between 12MHz and 48MHz */
515 .set_rate = &omap1_set_uart_rate, 482 .set_rate = &omap1_set_uart_rate,
@@ -523,8 +490,8 @@ static struct uart_clk uart1_16xx = {
523 /* Direct from ULPD, no real parent */ 490 /* Direct from ULPD, no real parent */
524 .parent = &armper_ck.clk, 491 .parent = &armper_ck.clk,
525 .rate = 48000000, 492 .rate = 48000000,
526 .flags = CLOCK_IN_OMAP16XX | RATE_FIXED | 493 .flags = RATE_FIXED | ENABLE_REG_32BIT |
527 ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, 494 CLOCK_NO_IDLE_PARENT,
528 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, 495 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
529 .enable_bit = 29, 496 .enable_bit = 29,
530 }, 497 },
@@ -537,9 +504,7 @@ static struct clk uart2_ck = {
537 /* Direct from ULPD, no real parent */ 504 /* Direct from ULPD, no real parent */
538 .parent = &armper_ck.clk, 505 .parent = &armper_ck.clk,
539 .rate = 12000000, 506 .rate = 12000000,
540 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 507 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
541 CLOCK_IN_OMAP310 | ENABLE_REG_32BIT |
542 CLOCK_NO_IDLE_PARENT,
543 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, 508 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
544 .enable_bit = 30, /* Chooses between 12MHz and 48MHz */ 509 .enable_bit = 30, /* Chooses between 12MHz and 48MHz */
545 .set_rate = &omap1_set_uart_rate, 510 .set_rate = &omap1_set_uart_rate,
@@ -552,8 +517,7 @@ static struct clk uart3_1510 = {
552 /* Direct from ULPD, no real parent */ 517 /* Direct from ULPD, no real parent */
553 .parent = &armper_ck.clk, 518 .parent = &armper_ck.clk,
554 .rate = 12000000, 519 .rate = 12000000,
555 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | 520 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
556 ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
557 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, 521 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
558 .enable_bit = 31, /* Chooses between 12MHz and 48MHz */ 522 .enable_bit = 31, /* Chooses between 12MHz and 48MHz */
559 .set_rate = &omap1_set_uart_rate, 523 .set_rate = &omap1_set_uart_rate,
@@ -567,8 +531,8 @@ static struct uart_clk uart3_16xx = {
567 /* Direct from ULPD, no real parent */ 531 /* Direct from ULPD, no real parent */
568 .parent = &armper_ck.clk, 532 .parent = &armper_ck.clk,
569 .rate = 48000000, 533 .rate = 48000000,
570 .flags = CLOCK_IN_OMAP16XX | RATE_FIXED | 534 .flags = RATE_FIXED | ENABLE_REG_32BIT |
571 ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, 535 CLOCK_NO_IDLE_PARENT,
572 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, 536 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
573 .enable_bit = 31, 537 .enable_bit = 31,
574 }, 538 },
@@ -580,8 +544,7 @@ static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */
580 .ops = &clkops_generic, 544 .ops = &clkops_generic,
581 /* Direct from ULPD, no parent */ 545 /* Direct from ULPD, no parent */
582 .rate = 6000000, 546 .rate = 6000000,
583 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 547 .flags = RATE_FIXED | ENABLE_REG_32BIT,
584 CLOCK_IN_OMAP310 | RATE_FIXED | ENABLE_REG_32BIT,
585 .enable_reg = (void __iomem *)ULPD_CLOCK_CTRL, 548 .enable_reg = (void __iomem *)ULPD_CLOCK_CTRL,
586 .enable_bit = USB_MCLK_EN_BIT, 549 .enable_bit = USB_MCLK_EN_BIT,
587}; 550};
@@ -591,8 +554,7 @@ static struct clk usb_hhc_ck1510 = {
591 .ops = &clkops_generic, 554 .ops = &clkops_generic,
592 /* Direct from ULPD, no parent */ 555 /* Direct from ULPD, no parent */
593 .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */ 556 .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
594 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | 557 .flags = RATE_FIXED | ENABLE_REG_32BIT,
595 RATE_FIXED | ENABLE_REG_32BIT,
596 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, 558 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
597 .enable_bit = USB_HOST_HHC_UHOST_EN, 559 .enable_bit = USB_HOST_HHC_UHOST_EN,
598}; 560};
@@ -603,8 +565,7 @@ static struct clk usb_hhc_ck16xx = {
603 /* Direct from ULPD, no parent */ 565 /* Direct from ULPD, no parent */
604 .rate = 48000000, 566 .rate = 48000000,
605 /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */ 567 /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
606 .flags = CLOCK_IN_OMAP16XX | 568 .flags = RATE_FIXED | ENABLE_REG_32BIT,
607 RATE_FIXED | ENABLE_REG_32BIT,
608 .enable_reg = (void __iomem *)OTG_BASE + 0x08 /* OTG_SYSCON_2 */, 569 .enable_reg = (void __iomem *)OTG_BASE + 0x08 /* OTG_SYSCON_2 */,
609 .enable_bit = 8 /* UHOST_EN */, 570 .enable_bit = 8 /* UHOST_EN */,
610}; 571};
@@ -614,7 +575,7 @@ static struct clk usb_dc_ck = {
614 .ops = &clkops_generic, 575 .ops = &clkops_generic,
615 /* Direct from ULPD, no parent */ 576 /* Direct from ULPD, no parent */
616 .rate = 48000000, 577 .rate = 48000000,
617 .flags = CLOCK_IN_OMAP16XX | RATE_FIXED, 578 .flags = RATE_FIXED,
618 .enable_reg = (void __iomem *)SOFT_REQ_REG, 579 .enable_reg = (void __iomem *)SOFT_REQ_REG,
619 .enable_bit = 4, 580 .enable_bit = 4,
620}; 581};
@@ -624,7 +585,7 @@ static struct clk mclk_1510 = {
624 .ops = &clkops_generic, 585 .ops = &clkops_generic,
625 /* Direct from ULPD, no parent. May be enabled by ext hardware. */ 586 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
626 .rate = 12000000, 587 .rate = 12000000,
627 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | RATE_FIXED, 588 .flags = RATE_FIXED,
628 .enable_reg = (void __iomem *)SOFT_REQ_REG, 589 .enable_reg = (void __iomem *)SOFT_REQ_REG,
629 .enable_bit = 6, 590 .enable_bit = 6,
630}; 591};
@@ -633,7 +594,6 @@ static struct clk mclk_16xx = {
633 .name = "mclk", 594 .name = "mclk",
634 .ops = &clkops_generic, 595 .ops = &clkops_generic,
635 /* Direct from ULPD, no parent. May be enabled by ext hardware. */ 596 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
636 .flags = CLOCK_IN_OMAP16XX,
637 .enable_reg = (void __iomem *)COM_CLK_DIV_CTRL_SEL, 597 .enable_reg = (void __iomem *)COM_CLK_DIV_CTRL_SEL,
638 .enable_bit = COM_ULPD_PLL_CLK_REQ, 598 .enable_bit = COM_ULPD_PLL_CLK_REQ,
639 .set_rate = &omap1_set_ext_clk_rate, 599 .set_rate = &omap1_set_ext_clk_rate,
@@ -646,14 +606,13 @@ static struct clk bclk_1510 = {
646 .ops = &clkops_generic, 606 .ops = &clkops_generic,
647 /* Direct from ULPD, no parent. May be enabled by ext hardware. */ 607 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
648 .rate = 12000000, 608 .rate = 12000000,
649 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | RATE_FIXED, 609 .flags = RATE_FIXED,
650}; 610};
651 611
652static struct clk bclk_16xx = { 612static struct clk bclk_16xx = {
653 .name = "bclk", 613 .name = "bclk",
654 .ops = &clkops_generic, 614 .ops = &clkops_generic,
655 /* Direct from ULPD, no parent. May be enabled by ext hardware. */ 615 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
656 .flags = CLOCK_IN_OMAP16XX,
657 .enable_reg = (void __iomem *)SWD_CLK_DIV_CTRL_SEL, 616 .enable_reg = (void __iomem *)SWD_CLK_DIV_CTRL_SEL,
658 .enable_bit = SWD_ULPD_PLL_CLK_REQ, 617 .enable_bit = SWD_ULPD_PLL_CLK_REQ,
659 .set_rate = &omap1_set_ext_clk_rate, 618 .set_rate = &omap1_set_ext_clk_rate,
@@ -667,9 +626,7 @@ static struct clk mmc1_ck = {
667 /* Functional clock is direct from ULPD, interface clock is ARMPER */ 626 /* Functional clock is direct from ULPD, interface clock is ARMPER */
668 .parent = &armper_ck.clk, 627 .parent = &armper_ck.clk,
669 .rate = 48000000, 628 .rate = 48000000,
670 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 629 .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
671 CLOCK_IN_OMAP310 | RATE_FIXED | ENABLE_REG_32BIT |
672 CLOCK_NO_IDLE_PARENT,
673 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, 630 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
674 .enable_bit = 23, 631 .enable_bit = 23,
675}; 632};
@@ -681,8 +638,7 @@ static struct clk mmc2_ck = {
681 /* Functional clock is direct from ULPD, interface clock is ARMPER */ 638 /* Functional clock is direct from ULPD, interface clock is ARMPER */
682 .parent = &armper_ck.clk, 639 .parent = &armper_ck.clk,
683 .rate = 48000000, 640 .rate = 48000000,
684 .flags = CLOCK_IN_OMAP16XX | 641 .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
685 RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
686 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, 642 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
687 .enable_bit = 20, 643 .enable_bit = 20,
688}; 644};
@@ -690,8 +646,6 @@ static struct clk mmc2_ck = {
690static struct clk virtual_ck_mpu = { 646static struct clk virtual_ck_mpu = {
691 .name = "mpu", 647 .name = "mpu",
692 .ops = &clkops_null, 648 .ops = &clkops_null,
693 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
694 CLOCK_IN_OMAP310,
695 .parent = &arm_ck, /* Is smarter alias for */ 649 .parent = &arm_ck, /* Is smarter alias for */
696 .recalc = &followparent_recalc, 650 .recalc = &followparent_recalc,
697 .set_rate = &omap1_select_table_rate, 651 .set_rate = &omap1_select_table_rate,
@@ -704,8 +658,7 @@ static struct clk i2c_fck = {
704 .name = "i2c_fck", 658 .name = "i2c_fck",
705 .id = 1, 659 .id = 1,
706 .ops = &clkops_null, 660 .ops = &clkops_null,
707 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 661 .flags = CLOCK_NO_IDLE_PARENT,
708 CLOCK_NO_IDLE_PARENT,
709 .parent = &armxor_ck.clk, 662 .parent = &armxor_ck.clk,
710 .recalc = &followparent_recalc, 663 .recalc = &followparent_recalc,
711}; 664};
@@ -714,62 +667,9 @@ static struct clk i2c_ick = {
714 .name = "i2c_ick", 667 .name = "i2c_ick",
715 .id = 1, 668 .id = 1,
716 .ops = &clkops_null, 669 .ops = &clkops_null,
717 .flags = CLOCK_IN_OMAP16XX | CLOCK_NO_IDLE_PARENT, 670 .flags = CLOCK_NO_IDLE_PARENT,
718 .parent = &armper_ck.clk, 671 .parent = &armper_ck.clk,
719 .recalc = &followparent_recalc, 672 .recalc = &followparent_recalc,
720}; 673};
721 674
722static struct clk * onchip_clks[] = {
723 /* non-ULPD clocks */
724 &ck_ref,
725 &ck_dpll1,
726 /* CK_GEN1 clocks */
727 &ck_dpll1out.clk,
728 &sossi_ck,
729 &arm_ck,
730 &armper_ck.clk,
731 &arm_gpio_ck,
732 &armxor_ck.clk,
733 &armtim_ck.clk,
734 &armwdt_ck.clk,
735 &arminth_ck1510, &arminth_ck16xx,
736 /* CK_GEN2 clocks */
737 &dsp_ck,
738 &dspmmu_ck,
739 &dspper_ck,
740 &dspxor_ck,
741 &dsptim_ck,
742 /* CK_GEN3 clocks */
743 &tc_ck.clk,
744 &tipb_ck,
745 &l3_ocpi_ck,
746 &tc1_ck,
747 &tc2_ck,
748 &dma_ck,
749 &dma_lcdfree_ck,
750 &api_ck.clk,
751 &lb_ck.clk,
752 &rhea1_ck,
753 &rhea2_ck,
754 &lcd_ck_16xx,
755 &lcd_ck_1510.clk,
756 /* ULPD clocks */
757 &uart1_1510,
758 &uart1_16xx.clk,
759 &uart2_ck,
760 &uart3_1510,
761 &uart3_16xx.clk,
762 &usb_clko,
763 &usb_hhc_ck1510, &usb_hhc_ck16xx,
764 &usb_dc_ck,
765 &mclk_1510, &mclk_16xx,
766 &bclk_1510, &bclk_16xx,
767 &mmc1_ck,
768 &mmc2_ck,
769 /* Virtual clocks */
770 &virtual_ck_mpu,
771 &i2c_fck,
772 &i2c_ick,
773};
774
775#endif 675#endif
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index 46d3b0b9ce69..fc7b6831f3eb 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -11,6 +11,7 @@ choice
11 11
12config ARCH_OMAP1 12config ARCH_OMAP1
13 bool "TI OMAP1" 13 bool "TI OMAP1"
14 select COMMON_CLKDEV
14 15
15config ARCH_OMAP2 16config ARCH_OMAP2
16 bool "TI OMAP2" 17 bool "TI OMAP2"
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index 6b3ef2a0b04e..6b88f7878a51 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -36,6 +36,7 @@ static struct clk_functions *arch_clock;
36 * Standard clock functions defined in include/linux/clk.h 36 * Standard clock functions defined in include/linux/clk.h
37 *-------------------------------------------------------------------------*/ 37 *-------------------------------------------------------------------------*/
38 38
39#ifndef CONFIG_COMMON_CLKDEV
39/* 40/*
40 * Returns a clock. Note that we first try to use device id on the bus 41 * Returns a clock. Note that we first try to use device id on the bus
41 * and clock name. If this fails, we try to use clock name only. 42 * and clock name. If this fails, we try to use clock name only.
@@ -72,6 +73,7 @@ found:
72 return clk; 73 return clk;
73} 74}
74EXPORT_SYMBOL(clk_get); 75EXPORT_SYMBOL(clk_get);
76#endif
75 77
76int clk_enable(struct clk *clk) 78int clk_enable(struct clk *clk)
77{ 79{
@@ -145,10 +147,12 @@ unsigned long clk_get_rate(struct clk *clk)
145} 147}
146EXPORT_SYMBOL(clk_get_rate); 148EXPORT_SYMBOL(clk_get_rate);
147 149
150#ifndef CONFIG_COMMON_CLKDEV
148void clk_put(struct clk *clk) 151void clk_put(struct clk *clk)
149{ 152{
150} 153}
151EXPORT_SYMBOL(clk_put); 154EXPORT_SYMBOL(clk_put);
155#endif
152 156
153/*------------------------------------------------------------------------- 157/*-------------------------------------------------------------------------
154 * Optional clock functions defined in include/linux/clk.h 158 * Optional clock functions defined in include/linux/clk.h
diff --git a/arch/arm/plat-omap/include/mach/clkdev.h b/arch/arm/plat-omap/include/mach/clkdev.h
new file mode 100644
index 000000000000..730c49d1ebd8
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/clkdev.h
@@ -0,0 +1,13 @@
1#ifndef __MACH_CLKDEV_H
2#define __MACH_CLKDEV_H
3
4static inline int __clk_get(struct clk *clk)
5{
6 return 1;
7}
8
9static inline void __clk_put(struct clk *clk)
10{
11}
12
13#endif
diff --git a/arch/arm/plat-omap/include/mach/clock.h b/arch/arm/plat-omap/include/mach/clock.h
index 5a7411e71f20..2af4bc24cfe9 100644
--- a/arch/arm/plat-omap/include/mach/clock.h
+++ b/arch/arm/plat-omap/include/mach/clock.h
@@ -136,11 +136,7 @@ extern const struct clkops clkops_null;
136#define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */ 136#define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */
137#define ENABLE_ON_INIT (1 << 11) /* Enable upon framework init */ 137#define ENABLE_ON_INIT (1 << 11) /* Enable upon framework init */
138#define INVERT_ENABLE (1 << 12) /* 0 enables, 1 disables */ 138#define INVERT_ENABLE (1 << 12) /* 0 enables, 1 disables */
139/* bits 13-20 are currently free */ 139/* bits 13-24 are currently free */
140#define CLOCK_IN_OMAP310 (1 << 21)
141#define CLOCK_IN_OMAP730 (1 << 22)
142#define CLOCK_IN_OMAP1510 (1 << 23)
143#define CLOCK_IN_OMAP16XX (1 << 24)
144#define CLOCK_IN_OMAP242X (1 << 25) 140#define CLOCK_IN_OMAP242X (1 << 25)
145#define CLOCK_IN_OMAP243X (1 << 26) 141#define CLOCK_IN_OMAP243X (1 << 26)
146#define CLOCK_IN_OMAP343X (1 << 27) /* clocks common to all 343X */ 142#define CLOCK_IN_OMAP343X (1 << 27) /* clocks common to all 343X */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-06 12:35:44 -0500