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authorSonic Zhang <sonic.zhang@analog.com>2009-04-07 11:52:26 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2009-04-07 11:44:05 -0400
commitd307d36adeaa70074773b3e5eab8d7e1beb008a4 (patch)
tree2a51257927be7c1a99ffb38b4752e0a4b56edc2a /arch
parent6f95570e407d03c5140a220e054f9b18abdc7041 (diff)
tty: Blackin CTS/RTS
Both software emulated and hardware based CTS and RTS are enabled in serial driver. The CTS RTS PIN connection on BF548 UART port is defined as a modem device not as a host device. In order to test it under Linux, please nake a cross UART cable to exchange CTS and RTS signal. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Bryan Wu <cooloney@kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Alan Cox <alan@lxorguk.ukuu.org.uk> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h10
-rw-r--r--arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h10
-rw-r--r--arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h9
-rw-r--r--arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h10
-rw-r--r--arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h10
-rw-r--r--arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h72
-rw-r--r--arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h9
7 files changed, 72 insertions, 58 deletions
diff --git a/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h
index e21c1c3e4ec7..0fb2ce5d840e 100644
--- a/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h
@@ -53,9 +53,9 @@
53#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0) 53#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
54#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0) 54#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
55 55
56#define UART_GET_CTS(x) gpio_get_value(x->cts_pin) 56#define UART_GET_CTS(x) (!gpio_get_value(x->cts_pin))
57#define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1) 57#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
58#define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0) 58#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
59#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v) 59#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
60#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0) 60#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
61 61
@@ -87,6 +87,7 @@
87struct bfin_serial_port { 87struct bfin_serial_port {
88 struct uart_port port; 88 struct uart_port port;
89 unsigned int old_status; 89 unsigned int old_status;
90 int status_irq;
90 unsigned int lsr; 91 unsigned int lsr;
91#ifdef CONFIG_SERIAL_BFIN_DMA 92#ifdef CONFIG_SERIAL_BFIN_DMA
92 int tx_done; 93 int tx_done;
@@ -125,6 +126,7 @@ static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
125struct bfin_serial_res { 126struct bfin_serial_res {
126 unsigned long uart_base_addr; 127 unsigned long uart_base_addr;
127 int uart_irq; 128 int uart_irq;
129 int uart_status_irq;
128#ifdef CONFIG_SERIAL_BFIN_DMA 130#ifdef CONFIG_SERIAL_BFIN_DMA
129 unsigned int uart_tx_dma_channel; 131 unsigned int uart_tx_dma_channel;
130 unsigned int uart_rx_dma_channel; 132 unsigned int uart_rx_dma_channel;
@@ -140,6 +142,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
140 { 142 {
141 0xFFC00400, 143 0xFFC00400,
142 IRQ_UART0_RX, 144 IRQ_UART0_RX,
145 IRQ_UART0_ERROR,
143#ifdef CONFIG_SERIAL_BFIN_DMA 146#ifdef CONFIG_SERIAL_BFIN_DMA
144 CH_UART0_TX, 147 CH_UART0_TX,
145 CH_UART0_RX, 148 CH_UART0_RX,
@@ -154,6 +157,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
154 { 157 {
155 0xFFC02000, 158 0xFFC02000,
156 IRQ_UART1_RX, 159 IRQ_UART1_RX,
160 IRQ_UART1_ERROR,
157#ifdef CONFIG_SERIAL_BFIN_DMA 161#ifdef CONFIG_SERIAL_BFIN_DMA
158 CH_UART1_TX, 162 CH_UART1_TX,
159 CH_UART1_RX, 163 CH_UART1_RX,
diff --git a/arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h
index d2b160c14f04..a625659dd67f 100644
--- a/arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h
@@ -53,9 +53,9 @@
53#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0) 53#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
54#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0) 54#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
55 55
56#define UART_GET_CTS(x) gpio_get_value(x->cts_pin) 56#define UART_GET_CTS(x) (!gpio_get_value(x->cts_pin))
57#define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1) 57#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
58#define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0) 58#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
59#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v) 59#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
60#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0) 60#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
61 61
@@ -87,6 +87,7 @@
87struct bfin_serial_port { 87struct bfin_serial_port {
88 struct uart_port port; 88 struct uart_port port;
89 unsigned int old_status; 89 unsigned int old_status;
90 int status_irq;
90 unsigned int lsr; 91 unsigned int lsr;
91#ifdef CONFIG_SERIAL_BFIN_DMA 92#ifdef CONFIG_SERIAL_BFIN_DMA
92 int tx_done; 93 int tx_done;
@@ -125,6 +126,7 @@ static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
125struct bfin_serial_res { 126struct bfin_serial_res {
126 unsigned long uart_base_addr; 127 unsigned long uart_base_addr;
127 int uart_irq; 128 int uart_irq;
129 int uart_status_irq;
128#ifdef CONFIG_SERIAL_BFIN_DMA 130#ifdef CONFIG_SERIAL_BFIN_DMA
129 unsigned int uart_tx_dma_channel; 131 unsigned int uart_tx_dma_channel;
130 unsigned int uart_rx_dma_channel; 132 unsigned int uart_rx_dma_channel;
@@ -140,6 +142,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
140 { 142 {
141 0xFFC00400, 143 0xFFC00400,
142 IRQ_UART0_RX, 144 IRQ_UART0_RX,
145 IRQ_UART0_ERROR,
143#ifdef CONFIG_SERIAL_BFIN_DMA 146#ifdef CONFIG_SERIAL_BFIN_DMA
144 CH_UART0_TX, 147 CH_UART0_TX,
145 CH_UART0_RX, 148 CH_UART0_RX,
@@ -154,6 +157,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
154 { 157 {
155 0xFFC02000, 158 0xFFC02000,
156 IRQ_UART1_RX, 159 IRQ_UART1_RX,
160 IRQ_UART1_ERROR,
157#ifdef CONFIG_SERIAL_BFIN_DMA 161#ifdef CONFIG_SERIAL_BFIN_DMA
158 CH_UART1_TX, 162 CH_UART1_TX,
159 CH_UART1_RX, 163 CH_UART1_RX,
diff --git a/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h
index 70356ddf8509..a3789d7ccf8c 100644
--- a/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h
@@ -53,9 +53,9 @@
53#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0) 53#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
54#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0) 54#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
55 55
56#define UART_GET_CTS(x) gpio_get_value(x->cts_pin) 56#define UART_GET_CTS(x) (!gpio_get_value(x->cts_pin))
57#define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1) 57#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
58#define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0) 58#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
59#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v) 59#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
60#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0) 60#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
61 61
@@ -74,6 +74,7 @@
74struct bfin_serial_port { 74struct bfin_serial_port {
75 struct uart_port port; 75 struct uart_port port;
76 unsigned int old_status; 76 unsigned int old_status;
77 int status_irq;
77 unsigned int lsr; 78 unsigned int lsr;
78#ifdef CONFIG_SERIAL_BFIN_DMA 79#ifdef CONFIG_SERIAL_BFIN_DMA
79 int tx_done; 80 int tx_done;
@@ -116,6 +117,7 @@ static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
116struct bfin_serial_res { 117struct bfin_serial_res {
117 unsigned long uart_base_addr; 118 unsigned long uart_base_addr;
118 int uart_irq; 119 int uart_irq;
120 int uart_status_irq;
119#ifdef CONFIG_SERIAL_BFIN_DMA 121#ifdef CONFIG_SERIAL_BFIN_DMA
120 unsigned int uart_tx_dma_channel; 122 unsigned int uart_tx_dma_channel;
121 unsigned int uart_rx_dma_channel; 123 unsigned int uart_rx_dma_channel;
@@ -130,6 +132,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
130 { 132 {
131 0xFFC00400, 133 0xFFC00400,
132 IRQ_UART_RX, 134 IRQ_UART_RX,
135 IRQ_UART_ERROR,
133#ifdef CONFIG_SERIAL_BFIN_DMA 136#ifdef CONFIG_SERIAL_BFIN_DMA
134 CH_UART_TX, 137 CH_UART_TX,
135 CH_UART_RX, 138 CH_UART_RX,
diff --git a/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h
index d46fc4f50cf2..b86662fb9de7 100644
--- a/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h
@@ -53,9 +53,9 @@
53#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0) 53#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
54#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0) 54#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
55 55
56#define UART_GET_CTS(x) gpio_get_value(x->cts_pin) 56#define UART_GET_CTS(x) (!gpio_get_value(x->cts_pin))
57#define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1) 57#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
58#define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0) 58#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
59#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v) 59#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
60#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0) 60#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
61 61
@@ -87,6 +87,7 @@
87struct bfin_serial_port { 87struct bfin_serial_port {
88 struct uart_port port; 88 struct uart_port port;
89 unsigned int old_status; 89 unsigned int old_status;
90 int status_irq;
90 unsigned int lsr; 91 unsigned int lsr;
91#ifdef CONFIG_SERIAL_BFIN_DMA 92#ifdef CONFIG_SERIAL_BFIN_DMA
92 int tx_done; 93 int tx_done;
@@ -124,6 +125,7 @@ static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
124struct bfin_serial_res { 125struct bfin_serial_res {
125 unsigned long uart_base_addr; 126 unsigned long uart_base_addr;
126 int uart_irq; 127 int uart_irq;
128 int uart_status_irq;
127#ifdef CONFIG_SERIAL_BFIN_DMA 129#ifdef CONFIG_SERIAL_BFIN_DMA
128 unsigned int uart_tx_dma_channel; 130 unsigned int uart_tx_dma_channel;
129 unsigned int uart_rx_dma_channel; 131 unsigned int uart_rx_dma_channel;
@@ -139,6 +141,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
139 { 141 {
140 0xFFC00400, 142 0xFFC00400,
141 IRQ_UART0_RX, 143 IRQ_UART0_RX,
144 IRQ_UART0_ERROR,
142#ifdef CONFIG_SERIAL_BFIN_DMA 145#ifdef CONFIG_SERIAL_BFIN_DMA
143 CH_UART0_TX, 146 CH_UART0_TX,
144 CH_UART0_RX, 147 CH_UART0_RX,
@@ -153,6 +156,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
153 { 156 {
154 0xFFC02000, 157 0xFFC02000,
155 IRQ_UART1_RX, 158 IRQ_UART1_RX,
159 IRQ_UART1_ERROR,
156#ifdef CONFIG_SERIAL_BFIN_DMA 160#ifdef CONFIG_SERIAL_BFIN_DMA
157 CH_UART1_TX, 161 CH_UART1_TX,
158 CH_UART1_RX, 162 CH_UART1_RX,
diff --git a/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h
index 3c2811ebecdd..c536551eb4b8 100644
--- a/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h
@@ -53,9 +53,9 @@
53#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0) 53#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
54#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0) 54#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
55 55
56#define UART_GET_CTS(x) gpio_get_value(x->cts_pin) 56#define UART_GET_CTS(x) (!gpio_get_value(x->cts_pin))
57#define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1) 57#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
58#define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0) 58#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
59#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v) 59#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
60#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0) 60#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
61 61
@@ -87,6 +87,7 @@
87struct bfin_serial_port { 87struct bfin_serial_port {
88 struct uart_port port; 88 struct uart_port port;
89 unsigned int old_status; 89 unsigned int old_status;
90 int status_irq;
90 unsigned int lsr; 91 unsigned int lsr;
91#ifdef CONFIG_SERIAL_BFIN_DMA 92#ifdef CONFIG_SERIAL_BFIN_DMA
92 int tx_done; 93 int tx_done;
@@ -125,6 +126,7 @@ static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
125struct bfin_serial_res { 126struct bfin_serial_res {
126 unsigned long uart_base_addr; 127 unsigned long uart_base_addr;
127 int uart_irq; 128 int uart_irq;
129 int uart_status_irq;
128#ifdef CONFIG_SERIAL_BFIN_DMA 130#ifdef CONFIG_SERIAL_BFIN_DMA
129 unsigned int uart_tx_dma_channel; 131 unsigned int uart_tx_dma_channel;
130 unsigned int uart_rx_dma_channel; 132 unsigned int uart_rx_dma_channel;
@@ -140,6 +142,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
140 { 142 {
141 0xFFC00400, 143 0xFFC00400,
142 IRQ_UART0_RX, 144 IRQ_UART0_RX,
145 IRQ_UART0_ERROR,
143#ifdef CONFIG_SERIAL_BFIN_DMA 146#ifdef CONFIG_SERIAL_BFIN_DMA
144 CH_UART0_TX, 147 CH_UART0_TX,
145 CH_UART0_RX, 148 CH_UART0_RX,
@@ -154,6 +157,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
154 { 157 {
155 0xFFC02000, 158 0xFFC02000,
156 IRQ_UART1_RX, 159 IRQ_UART1_RX,
160 IRQ_UART1_ERROR,
157#ifdef CONFIG_SERIAL_BFIN_DMA 161#ifdef CONFIG_SERIAL_BFIN_DMA
158 CH_UART1_TX, 162 CH_UART1_TX,
159 CH_UART1_RX, 163 CH_UART1_RX,
diff --git a/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h
index 388e2328aeba..2d1b5fa3cca0 100644
--- a/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h
@@ -46,41 +46,27 @@
46#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v) 46#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
47#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v) 47#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
48#define UART_SET_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER_SET),v) 48#define UART_SET_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER_SET),v)
49#define UART_CLEAR_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER_CLEAR),v) 49#define UART_CLEAR_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER_CLEAR),v)
50#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v) 50#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
51#define UART_PUT_LSR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LSR),v) 51#define UART_PUT_LSR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LSR),v)
52#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v) 52#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
53#define UART_CLEAR_LSR(uart) bfin_write16(((uart)->port.membase + OFFSET_LSR), -1) 53#define UART_CLEAR_LSR(uart) bfin_write16(((uart)->port.membase + OFFSET_LSR), -1)
54#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v) 54#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
55#define UART_PUT_MCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_MCR),v) 55#define UART_PUT_MCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_MCR),v)
56#define UART_CLEAR_SCTS(uart) bfin_write16(((uart)->port.membase + OFFSET_MSR),SCTS)
56 57
57#define UART_SET_DLAB(uart) /* MMRs not muxed on BF54x */ 58#define UART_SET_DLAB(uart) /* MMRs not muxed on BF54x */
58#define UART_CLEAR_DLAB(uart) /* MMRs not muxed on BF54x */ 59#define UART_CLEAR_DLAB(uart) /* MMRs not muxed on BF54x */
59 60
60#define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS) 61#define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS)
61#define UART_SET_RTS(x) (UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS)) 62#define UART_DISABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) & ~(ARTS|MRTS))
62#define UART_CLEAR_RTS(x) (UART_PUT_MCR(x, UART_GET_MCR(x) & ~MRTS)) 63#define UART_ENABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS | ARTS)
63#define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v) 64#define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v)
64#define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF) 65#define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF)
65 66
66#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART2_CTSRTS) 67#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) || \
67# define CONFIG_SERIAL_BFIN_CTSRTS 68 defined(CONFIG_BFIN_UART2_CTSRTS) || defined(CONFIG_BFIN_UART3_CTSRTS)
68 69# define CONFIG_SERIAL_BFIN_HARD_CTSRTS
69# ifndef CONFIG_UART0_CTS_PIN
70# define CONFIG_UART0_CTS_PIN -1
71# endif
72
73# ifndef CONFIG_UART0_RTS_PIN
74# define CONFIG_UART0_RTS_PIN -1
75# endif
76
77# ifndef CONFIG_UART2_CTS_PIN
78# define CONFIG_UART2_CTS_PIN -1
79# endif
80
81# ifndef CONFIG_UART2_RTS_PIN
82# define CONFIG_UART2_RTS_PIN -1
83# endif
84#endif 70#endif
85 71
86#define BFIN_UART_TX_FIFO_SIZE 2 72#define BFIN_UART_TX_FIFO_SIZE 2
@@ -91,6 +77,7 @@
91struct bfin_serial_port { 77struct bfin_serial_port {
92 struct uart_port port; 78 struct uart_port port;
93 unsigned int old_status; 79 unsigned int old_status;
80 int status_irq;
94#ifdef CONFIG_SERIAL_BFIN_DMA 81#ifdef CONFIG_SERIAL_BFIN_DMA
95 int tx_done; 82 int tx_done;
96 int tx_count; 83 int tx_count;
@@ -101,23 +88,24 @@ struct bfin_serial_port {
101 unsigned int rx_dma_channel; 88 unsigned int rx_dma_channel;
102 struct work_struct tx_dma_workqueue; 89 struct work_struct tx_dma_workqueue;
103#endif 90#endif
104#ifdef CONFIG_SERIAL_BFIN_CTSRTS 91#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
105 struct timer_list cts_timer; 92 int scts;
106 int cts_pin; 93 int cts_pin;
107 int rts_pin; 94 int rts_pin;
108#endif 95#endif
109}; 96};
110 97
111struct bfin_serial_res { 98struct bfin_serial_res {
112 unsigned long uart_base_addr; 99 unsigned long uart_base_addr;
113 int uart_irq; 100 int uart_irq;
101 int uart_status_irq;
114#ifdef CONFIG_SERIAL_BFIN_DMA 102#ifdef CONFIG_SERIAL_BFIN_DMA
115 unsigned int uart_tx_dma_channel; 103 unsigned int uart_tx_dma_channel;
116 unsigned int uart_rx_dma_channel; 104 unsigned int uart_rx_dma_channel;
117#endif 105#endif
118#ifdef CONFIG_SERIAL_BFIN_CTSRTS 106#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
119 int uart_cts_pin; 107 int uart_cts_pin;
120 int uart_rts_pin; 108 int uart_rts_pin;
121#endif 109#endif
122}; 110};
123 111
@@ -126,13 +114,14 @@ struct bfin_serial_res bfin_serial_resource[] = {
126 { 114 {
127 0xFFC00400, 115 0xFFC00400,
128 IRQ_UART0_RX, 116 IRQ_UART0_RX,
117 IRQ_UART0_ERROR,
129#ifdef CONFIG_SERIAL_BFIN_DMA 118#ifdef CONFIG_SERIAL_BFIN_DMA
130 CH_UART0_TX, 119 CH_UART0_TX,
131 CH_UART0_RX, 120 CH_UART0_RX,
132#endif 121#endif
133#ifdef CONFIG_SERIAL_BFIN_CTSRTS 122#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
134 CONFIG_UART0_CTS_PIN, 123 0,
135 CONFIG_UART0_RTS_PIN, 124 0,
136#endif 125#endif
137 }, 126 },
138#endif 127#endif
@@ -140,13 +129,14 @@ struct bfin_serial_res bfin_serial_resource[] = {
140 { 129 {
141 0xFFC02000, 130 0xFFC02000,
142 IRQ_UART1_RX, 131 IRQ_UART1_RX,
132 IRQ_UART1_ERROR,
143#ifdef CONFIG_SERIAL_BFIN_DMA 133#ifdef CONFIG_SERIAL_BFIN_DMA
144 CH_UART1_TX, 134 CH_UART1_TX,
145 CH_UART1_RX, 135 CH_UART1_RX,
146#endif 136#endif
147#ifdef CONFIG_SERIAL_BFIN_CTSRTS 137#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
148 0, 138 GPIO_PE10,
149 0, 139 GPIO_PE9,
150#endif 140#endif
151 }, 141 },
152#endif 142#endif
@@ -154,13 +144,14 @@ struct bfin_serial_res bfin_serial_resource[] = {
154 { 144 {
155 0xFFC02100, 145 0xFFC02100,
156 IRQ_UART2_RX, 146 IRQ_UART2_RX,
147 IRQ_UART2_ERROR,
157#ifdef CONFIG_SERIAL_BFIN_DMA 148#ifdef CONFIG_SERIAL_BFIN_DMA
158 CH_UART2_TX, 149 CH_UART2_TX,
159 CH_UART2_RX, 150 CH_UART2_RX,
160#endif 151#endif
161#ifdef CONFIG_SERIAL_BFIN_CTSRTS 152#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
162 CONFIG_UART2_CTS_PIN, 153 0,
163 CONFIG_UART2_RTS_PIN, 154 0,
164#endif 155#endif
165 }, 156 },
166#endif 157#endif
@@ -168,13 +159,14 @@ struct bfin_serial_res bfin_serial_resource[] = {
168 { 159 {
169 0xFFC03100, 160 0xFFC03100,
170 IRQ_UART3_RX, 161 IRQ_UART3_RX,
162 IRQ_UART3_ERROR,
171#ifdef CONFIG_SERIAL_BFIN_DMA 163#ifdef CONFIG_SERIAL_BFIN_DMA
172 CH_UART3_TX, 164 CH_UART3_TX,
173 CH_UART3_RX, 165 CH_UART3_RX,
174#endif 166#endif
175#ifdef CONFIG_SERIAL_BFIN_CTSRTS 167#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
176 0, 168 GPIO_PB3,
177 0, 169 GPIO_PB2,
178#endif 170#endif
179 }, 171 },
180#endif 172#endif
diff --git a/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h
index d0469e3e16d8..a1b50878553f 100644
--- a/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h
@@ -53,9 +53,9 @@
53#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0) 53#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
54#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0) 54#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
55 55
56#define UART_GET_CTS(x) gpio_get_value(x->cts_pin) 56#define UART_GET_CTS(x) (!gpio_get_value(x->cts_pin))
57#define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1) 57#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
58#define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0) 58#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
59#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v) 59#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
60#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0) 60#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
61 61
@@ -74,6 +74,7 @@
74struct bfin_serial_port { 74struct bfin_serial_port {
75 struct uart_port port; 75 struct uart_port port;
76 unsigned int old_status; 76 unsigned int old_status;
77 int status_irq;
77 unsigned int lsr; 78 unsigned int lsr;
78#ifdef CONFIG_SERIAL_BFIN_DMA 79#ifdef CONFIG_SERIAL_BFIN_DMA
79 int tx_done; 80 int tx_done;
@@ -116,6 +117,7 @@ static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
116struct bfin_serial_res { 117struct bfin_serial_res {
117 unsigned long uart_base_addr; 118 unsigned long uart_base_addr;
118 int uart_irq; 119 int uart_irq;
120 int uart_status_irq;
119#ifdef CONFIG_SERIAL_BFIN_DMA 121#ifdef CONFIG_SERIAL_BFIN_DMA
120 unsigned int uart_tx_dma_channel; 122 unsigned int uart_tx_dma_channel;
121 unsigned int uart_rx_dma_channel; 123 unsigned int uart_rx_dma_channel;
@@ -130,6 +132,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
130 { 132 {
131 0xFFC00400, 133 0xFFC00400,
132 IRQ_UART_RX, 134 IRQ_UART_RX,
135 IRQ_UART_ERROR,
133#ifdef CONFIG_SERIAL_BFIN_DMA 136#ifdef CONFIG_SERIAL_BFIN_DMA
134 CH_UART_TX, 137 CH_UART_TX,
135 CH_UART_RX, 138 CH_UART_RX,
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-04 13:17:16 -0500