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authorAmit Daniel Kachhap <amit.kachhap@linaro.org>2012-03-08 05:09:06 -0500
committerKukjin Kim <kgene.kim@samsung.com>2012-03-09 10:04:50 -0500
commitd0341c61a2f641c4f90f4ed4b0d538c9bcb63d18 (patch)
tree29ac86abbe44650958bf99b3dcba7bc47b5d87eb /arch
parentb756a50f7f47e1dee70921399dcb338e4d3bc183 (diff)
ARM: EXYNOS: remove useless code to save/restore L2
Following the merge of CPU PM notifiers and L2 resume code, this patch removes useless code to save and restore L2 registers. This is now automatically covered by suspend calls which integrated CPU PM notifiers and new sleep code that allows to resume L2 before MMU is turned on. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Amit Daniel Kachhap <amit.kachhap@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-exynos/pm.c15
1 files changed, 0 insertions, 15 deletions
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index a4f61a43c7ba..2dd55a191abd 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -155,13 +155,6 @@ static struct sleep_save exynos4_core_save[] = {
155 SAVE_ITEM(S5P_SROM_BC3), 155 SAVE_ITEM(S5P_SROM_BC3),
156}; 156};
157 157
158static struct sleep_save exynos4_l2cc_save[] = {
159 SAVE_ITEM(S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL),
160 SAVE_ITEM(S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL),
161 SAVE_ITEM(S5P_VA_L2CC + L2X0_PREFETCH_CTRL),
162 SAVE_ITEM(S5P_VA_L2CC + L2X0_POWER_CTRL),
163 SAVE_ITEM(S5P_VA_L2CC + L2X0_AUX_CTRL),
164};
165 158
166/* For Cortex-A9 Diagnostic and Power control register */ 159/* For Cortex-A9 Diagnostic and Power control register */
167static unsigned int save_arm_register[2]; 160static unsigned int save_arm_register[2];
@@ -182,7 +175,6 @@ static void exynos4_pm_prepare(void)
182 u32 tmp; 175 u32 tmp;
183 176
184 s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save)); 177 s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
185 s3c_pm_do_save(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
186 s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save)); 178 s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save));
187 s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save)); 179 s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save));
188 180
@@ -386,13 +378,6 @@ static void exynos4_pm_resume(void)
386 378
387 scu_enable(S5P_VA_SCU); 379 scu_enable(S5P_VA_SCU);
388 380
389#ifdef CONFIG_CACHE_L2X0
390 s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
391 outer_inv_all();
392 /* enable L2X0*/
393 writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL);
394#endif
395
396early_wakeup: 381early_wakeup:
397 return; 382 return;
398} 383}