diff options
author | Olof Johansson <olof@lixom.net> | 2012-03-10 12:11:31 -0500 |
---|---|---|
committer | Olof Johansson <olof@lixom.net> | 2012-03-10 12:11:31 -0500 |
commit | cdc3df6f44f72c5924a16a47e1663c3fb0e57820 (patch) | |
tree | 834f1c4423899e605dc3d226282910e67f1ce260 /arch | |
parent | a58f67e70a6cad021ceebd1c8919b898dd5d5de3 (diff) | |
parent | 328ae2cb50af2f96b6061eb462aa92966a462bbc (diff) |
Merge branch 'dt-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt
* 'dt-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
arm/dts: mt_ventoux: very basic support for TeeJet Mt.Ventoux board
ARM: OMAP2+: Remove extra ifdefs for board-generic
ARM: OMAP2+: Fix build error when only ARCH_OMAP2/3 or 4 is selected
ARM: OMAP2+: board-generic: Use of_irq_init API
arm/dts: OMAP3: Add interrupt-controller bindings for INTC
ARM: OMAP2/3: intc: Add DT support for TI interrupt controller
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/boot/dts/am3517_mt_ventoux.dts | 27 | ||||
-rw-r--r-- | arch/arm/boot/dts/omap3.dtsi | 6 | ||||
-rw-r--r-- | arch/arm/mach-omap2/board-generic.c | 99 | ||||
-rw-r--r-- | arch/arm/mach-omap2/common.h | 12 | ||||
-rw-r--r-- | arch/arm/mach-omap2/irq.c | 60 |
5 files changed, 141 insertions, 63 deletions
diff --git a/arch/arm/boot/dts/am3517_mt_ventoux.dts b/arch/arm/boot/dts/am3517_mt_ventoux.dts new file mode 100644 index 000000000000..5eb26d7d9b4e --- /dev/null +++ b/arch/arm/boot/dts/am3517_mt_ventoux.dts | |||
@@ -0,0 +1,27 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2011 Ilya Yanok, EmCraft Systems | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify | ||
5 | * it under the terms of the GNU General Public License version 2 as | ||
6 | * published by the Free Software Foundation. | ||
7 | */ | ||
8 | /dts-v1/; | ||
9 | |||
10 | /include/ "omap3.dtsi" | ||
11 | |||
12 | / { | ||
13 | model = "TeeJet Mt.Ventoux"; | ||
14 | compatible = "teejet,mt_ventoux", "ti,omap3"; | ||
15 | |||
16 | memory { | ||
17 | device_type = "memory"; | ||
18 | reg = <0x80000000 0x10000000>; /* 256 MB */ | ||
19 | }; | ||
20 | |||
21 | /* AM35xx doesn't have IVA */ | ||
22 | soc { | ||
23 | iva { | ||
24 | status = "disabled"; | ||
25 | }; | ||
26 | }; | ||
27 | }; | ||
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index e69806432874..c6121357c1eb 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi | |||
@@ -61,10 +61,12 @@ | |||
61 | ranges; | 61 | ranges; |
62 | ti,hwmods = "l3_main"; | 62 | ti,hwmods = "l3_main"; |
63 | 63 | ||
64 | intc: interrupt-controller@1 { | 64 | intc: interrupt-controller@48200000 { |
65 | compatible = "ti,omap3-intc"; | 65 | compatible = "ti,omap2-intc"; |
66 | interrupt-controller; | 66 | interrupt-controller; |
67 | #interrupt-cells = <1>; | 67 | #interrupt-cells = <1>; |
68 | ti,intc-size = <96>; | ||
69 | reg = <0x48200000 0x1000>; | ||
68 | }; | 70 | }; |
69 | 71 | ||
70 | uart1: serial@4806a000 { | 72 | uart1: serial@4806a000 { |
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index 02d7e828a14b..74e1687b5170 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c | |||
@@ -12,6 +12,7 @@ | |||
12 | * published by the Free Software Foundation. | 12 | * published by the Free Software Foundation. |
13 | */ | 13 | */ |
14 | #include <linux/io.h> | 14 | #include <linux/io.h> |
15 | #include <linux/of_irq.h> | ||
15 | #include <linux/of_platform.h> | 16 | #include <linux/of_platform.h> |
16 | #include <linux/irqdomain.h> | 17 | #include <linux/irqdomain.h> |
17 | #include <linux/i2c/twl.h> | 18 | #include <linux/i2c/twl.h> |
@@ -24,33 +25,23 @@ | |||
24 | #include "common.h" | 25 | #include "common.h" |
25 | #include "common-board-devices.h" | 26 | #include "common-board-devices.h" |
26 | 27 | ||
27 | /* | 28 | #if !(defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)) |
28 | * XXX: Still needed to boot until the i2c & twl driver is adapted to | 29 | #define omap_intc_of_init NULL |
29 | * device-tree | 30 | #endif |
30 | */ | 31 | #ifndef CONFIG_ARCH_OMAP4 |
31 | #ifdef CONFIG_ARCH_OMAP4 | 32 | #define gic_of_init NULL |
32 | static struct twl4030_platform_data sdp4430_twldata = { | ||
33 | .irq_base = TWL6030_IRQ_BASE, | ||
34 | .irq_end = TWL6030_IRQ_END, | ||
35 | }; | ||
36 | |||
37 | static void __init omap4_i2c_init(void) | ||
38 | { | ||
39 | omap4_pmic_init("twl6030", &sdp4430_twldata); | ||
40 | } | ||
41 | #endif | 33 | #endif |
42 | 34 | ||
43 | #ifdef CONFIG_ARCH_OMAP3 | 35 | static struct of_device_id irq_match[] __initdata = { |
44 | static struct twl4030_platform_data beagle_twldata = { | 36 | { .compatible = "ti,omap2-intc", .data = omap_intc_of_init, }, |
45 | .irq_base = TWL4030_IRQ_BASE, | 37 | { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, }, |
46 | .irq_end = TWL4030_IRQ_END, | 38 | { } |
47 | }; | 39 | }; |
48 | 40 | ||
49 | static void __init omap3_i2c_init(void) | 41 | static void __init omap_init_irq(void) |
50 | { | 42 | { |
51 | omap3_pmic_init("twl4030", &beagle_twldata); | 43 | of_irq_init(irq_match); |
52 | } | 44 | } |
53 | #endif | ||
54 | 45 | ||
55 | static struct of_device_id omap_dt_match_table[] __initdata = { | 46 | static struct of_device_id omap_dt_match_table[] __initdata = { |
56 | { .compatible = "simple-bus", }, | 47 | { .compatible = "simple-bus", }, |
@@ -58,39 +49,13 @@ static struct of_device_id omap_dt_match_table[] __initdata = { | |||
58 | { } | 49 | { } |
59 | }; | 50 | }; |
60 | 51 | ||
61 | static struct of_device_id intc_match[] __initdata = { | ||
62 | { .compatible = "ti,omap3-intc", }, | ||
63 | { .compatible = "arm,cortex-a9-gic", }, | ||
64 | { } | ||
65 | }; | ||
66 | |||
67 | static void __init omap_generic_init(void) | 52 | static void __init omap_generic_init(void) |
68 | { | 53 | { |
69 | struct device_node *node = of_find_matching_node(NULL, intc_match); | ||
70 | if (node) | ||
71 | irq_domain_add_legacy(node, 32, 0, 0, &irq_domain_simple_ops, NULL); | ||
72 | |||
73 | omap_sdrc_init(NULL, NULL); | 54 | omap_sdrc_init(NULL, NULL); |
74 | 55 | ||
75 | of_platform_populate(NULL, omap_dt_match_table, NULL, NULL); | 56 | of_platform_populate(NULL, omap_dt_match_table, NULL, NULL); |
76 | } | 57 | } |
77 | 58 | ||
78 | #ifdef CONFIG_ARCH_OMAP4 | ||
79 | static void __init omap4_init(void) | ||
80 | { | ||
81 | omap4_i2c_init(); | ||
82 | omap_generic_init(); | ||
83 | } | ||
84 | #endif | ||
85 | |||
86 | #ifdef CONFIG_ARCH_OMAP3 | ||
87 | static void __init omap3_init(void) | ||
88 | { | ||
89 | omap3_i2c_init(); | ||
90 | omap_generic_init(); | ||
91 | } | ||
92 | #endif | ||
93 | |||
94 | #ifdef CONFIG_SOC_OMAP2420 | 59 | #ifdef CONFIG_SOC_OMAP2420 |
95 | static const char *omap242x_boards_compat[] __initdata = { | 60 | static const char *omap242x_boards_compat[] __initdata = { |
96 | "ti,omap2420", | 61 | "ti,omap2420", |
@@ -101,7 +66,7 @@ DT_MACHINE_START(OMAP242X_DT, "Generic OMAP2420 (Flattened Device Tree)") | |||
101 | .reserve = omap_reserve, | 66 | .reserve = omap_reserve, |
102 | .map_io = omap242x_map_io, | 67 | .map_io = omap242x_map_io, |
103 | .init_early = omap2420_init_early, | 68 | .init_early = omap2420_init_early, |
104 | .init_irq = omap2_init_irq, | 69 | .init_irq = omap_init_irq, |
105 | .handle_irq = omap2_intc_handle_irq, | 70 | .handle_irq = omap2_intc_handle_irq, |
106 | .init_machine = omap_generic_init, | 71 | .init_machine = omap_generic_init, |
107 | .timer = &omap2_timer, | 72 | .timer = &omap2_timer, |
@@ -120,7 +85,7 @@ DT_MACHINE_START(OMAP243X_DT, "Generic OMAP2430 (Flattened Device Tree)") | |||
120 | .reserve = omap_reserve, | 85 | .reserve = omap_reserve, |
121 | .map_io = omap243x_map_io, | 86 | .map_io = omap243x_map_io, |
122 | .init_early = omap2430_init_early, | 87 | .init_early = omap2430_init_early, |
123 | .init_irq = omap2_init_irq, | 88 | .init_irq = omap_init_irq, |
124 | .handle_irq = omap2_intc_handle_irq, | 89 | .handle_irq = omap2_intc_handle_irq, |
125 | .init_machine = omap_generic_init, | 90 | .init_machine = omap_generic_init, |
126 | .timer = &omap2_timer, | 91 | .timer = &omap2_timer, |
@@ -130,6 +95,22 @@ MACHINE_END | |||
130 | #endif | 95 | #endif |
131 | 96 | ||
132 | #ifdef CONFIG_ARCH_OMAP3 | 97 | #ifdef CONFIG_ARCH_OMAP3 |
98 | static struct twl4030_platform_data beagle_twldata = { | ||
99 | .irq_base = TWL4030_IRQ_BASE, | ||
100 | .irq_end = TWL4030_IRQ_END, | ||
101 | }; | ||
102 | |||
103 | static void __init omap3_i2c_init(void) | ||
104 | { | ||
105 | omap3_pmic_init("twl4030", &beagle_twldata); | ||
106 | } | ||
107 | |||
108 | static void __init omap3_init(void) | ||
109 | { | ||
110 | omap3_i2c_init(); | ||
111 | omap_generic_init(); | ||
112 | } | ||
113 | |||
133 | static const char *omap3_boards_compat[] __initdata = { | 114 | static const char *omap3_boards_compat[] __initdata = { |
134 | "ti,omap3", | 115 | "ti,omap3", |
135 | NULL, | 116 | NULL, |
@@ -139,7 +120,7 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)") | |||
139 | .reserve = omap_reserve, | 120 | .reserve = omap_reserve, |
140 | .map_io = omap3_map_io, | 121 | .map_io = omap3_map_io, |
141 | .init_early = omap3430_init_early, | 122 | .init_early = omap3430_init_early, |
142 | .init_irq = omap3_init_irq, | 123 | .init_irq = omap_init_irq, |
143 | .handle_irq = omap3_intc_handle_irq, | 124 | .handle_irq = omap3_intc_handle_irq, |
144 | .init_machine = omap3_init, | 125 | .init_machine = omap3_init, |
145 | .timer = &omap3_timer, | 126 | .timer = &omap3_timer, |
@@ -149,6 +130,22 @@ MACHINE_END | |||
149 | #endif | 130 | #endif |
150 | 131 | ||
151 | #ifdef CONFIG_ARCH_OMAP4 | 132 | #ifdef CONFIG_ARCH_OMAP4 |
133 | static struct twl4030_platform_data sdp4430_twldata = { | ||
134 | .irq_base = TWL6030_IRQ_BASE, | ||
135 | .irq_end = TWL6030_IRQ_END, | ||
136 | }; | ||
137 | |||
138 | static void __init omap4_i2c_init(void) | ||
139 | { | ||
140 | omap4_pmic_init("twl6030", &sdp4430_twldata); | ||
141 | } | ||
142 | |||
143 | static void __init omap4_init(void) | ||
144 | { | ||
145 | omap4_i2c_init(); | ||
146 | omap_generic_init(); | ||
147 | } | ||
148 | |||
152 | static const char *omap4_boards_compat[] __initdata = { | 149 | static const char *omap4_boards_compat[] __initdata = { |
153 | "ti,omap4", | 150 | "ti,omap4", |
154 | NULL, | 151 | NULL, |
@@ -158,7 +155,7 @@ DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)") | |||
158 | .reserve = omap_reserve, | 155 | .reserve = omap_reserve, |
159 | .map_io = omap4_map_io, | 156 | .map_io = omap4_map_io, |
160 | .init_early = omap4430_init_early, | 157 | .init_early = omap4430_init_early, |
161 | .init_irq = gic_init_irq, | 158 | .init_irq = omap_init_irq, |
162 | .handle_irq = gic_handle_irq, | 159 | .handle_irq = gic_handle_irq, |
163 | .init_machine = omap4_init, | 160 | .init_machine = omap4_init, |
164 | .timer = &omap4_timer, | 161 | .timer = &omap4_timer, |
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h index 7e9338e8d684..99604d364305 100644 --- a/arch/arm/mach-omap2/common.h +++ b/arch/arm/mach-omap2/common.h | |||
@@ -175,6 +175,18 @@ void omap3_intc_handle_irq(struct pt_regs *regs); | |||
175 | extern void __iomem *omap4_get_l2cache_base(void); | 175 | extern void __iomem *omap4_get_l2cache_base(void); |
176 | #endif | 176 | #endif |
177 | 177 | ||
178 | struct device_node; | ||
179 | #ifdef CONFIG_OF | ||
180 | int __init omap_intc_of_init(struct device_node *node, | ||
181 | struct device_node *parent); | ||
182 | #else | ||
183 | int __init omap_intc_of_init(struct device_node *node, | ||
184 | struct device_node *parent) | ||
185 | { | ||
186 | return 0; | ||
187 | } | ||
188 | #endif | ||
189 | |||
178 | #ifdef CONFIG_SMP | 190 | #ifdef CONFIG_SMP |
179 | extern void __iomem *omap4_get_scu_base(void); | 191 | extern void __iomem *omap4_get_scu_base(void); |
180 | #else | 192 | #else |
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c index 1fef061f7927..26eaf37ce4d9 100644 --- a/arch/arm/mach-omap2/irq.c +++ b/arch/arm/mach-omap2/irq.c | |||
@@ -11,12 +11,16 @@ | |||
11 | * for more details. | 11 | * for more details. |
12 | */ | 12 | */ |
13 | #include <linux/kernel.h> | 13 | #include <linux/kernel.h> |
14 | #include <linux/module.h> | ||
14 | #include <linux/init.h> | 15 | #include <linux/init.h> |
15 | #include <linux/interrupt.h> | 16 | #include <linux/interrupt.h> |
16 | #include <linux/io.h> | 17 | #include <linux/io.h> |
17 | #include <mach/hardware.h> | 18 | #include <mach/hardware.h> |
18 | #include <asm/exception.h> | 19 | #include <asm/exception.h> |
19 | #include <asm/mach/irq.h> | 20 | #include <asm/mach/irq.h> |
21 | #include <linux/irqdomain.h> | ||
22 | #include <linux/of.h> | ||
23 | #include <linux/of_address.h> | ||
20 | 24 | ||
21 | 25 | ||
22 | /* selected INTC register offsets */ | 26 | /* selected INTC register offsets */ |
@@ -57,6 +61,8 @@ static struct omap_irq_bank { | |||
57 | }, | 61 | }, |
58 | }; | 62 | }; |
59 | 63 | ||
64 | static struct irq_domain *domain; | ||
65 | |||
60 | /* Structure to save interrupt controller context */ | 66 | /* Structure to save interrupt controller context */ |
61 | struct omap3_intc_regs { | 67 | struct omap3_intc_regs { |
62 | u32 sysconfig; | 68 | u32 sysconfig; |
@@ -147,17 +153,27 @@ omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num) | |||
147 | IRQ_NOREQUEST | IRQ_NOPROBE, 0); | 153 | IRQ_NOREQUEST | IRQ_NOPROBE, 0); |
148 | } | 154 | } |
149 | 155 | ||
150 | static void __init omap_init_irq(u32 base, int nr_irqs) | 156 | static void __init omap_init_irq(u32 base, int nr_irqs, |
157 | struct device_node *node) | ||
151 | { | 158 | { |
152 | void __iomem *omap_irq_base; | 159 | void __iomem *omap_irq_base; |
153 | unsigned long nr_of_irqs = 0; | 160 | unsigned long nr_of_irqs = 0; |
154 | unsigned int nr_banks = 0; | 161 | unsigned int nr_banks = 0; |
155 | int i, j; | 162 | int i, j, irq_base; |
156 | 163 | ||
157 | omap_irq_base = ioremap(base, SZ_4K); | 164 | omap_irq_base = ioremap(base, SZ_4K); |
158 | if (WARN_ON(!omap_irq_base)) | 165 | if (WARN_ON(!omap_irq_base)) |
159 | return; | 166 | return; |
160 | 167 | ||
168 | irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0); | ||
169 | if (irq_base < 0) { | ||
170 | pr_warn("Couldn't allocate IRQ numbers\n"); | ||
171 | irq_base = 0; | ||
172 | } | ||
173 | |||
174 | domain = irq_domain_add_legacy(node, nr_irqs, irq_base, 0, | ||
175 | &irq_domain_simple_ops, NULL); | ||
176 | |||
161 | for (i = 0; i < ARRAY_SIZE(irq_banks); i++) { | 177 | for (i = 0; i < ARRAY_SIZE(irq_banks); i++) { |
162 | struct omap_irq_bank *bank = irq_banks + i; | 178 | struct omap_irq_bank *bank = irq_banks + i; |
163 | 179 | ||
@@ -166,36 +182,36 @@ static void __init omap_init_irq(u32 base, int nr_irqs) | |||
166 | /* Static mapping, never released */ | 182 | /* Static mapping, never released */ |
167 | bank->base_reg = ioremap(base, SZ_4K); | 183 | bank->base_reg = ioremap(base, SZ_4K); |
168 | if (!bank->base_reg) { | 184 | if (!bank->base_reg) { |
169 | printk(KERN_ERR "Could not ioremap irq bank%i\n", i); | 185 | pr_err("Could not ioremap irq bank%i\n", i); |
170 | continue; | 186 | continue; |
171 | } | 187 | } |
172 | 188 | ||
173 | omap_irq_bank_init_one(bank); | 189 | omap_irq_bank_init_one(bank); |
174 | 190 | ||
175 | for (j = 0; j < bank->nr_irqs; j += 32) | 191 | for (j = 0; j < bank->nr_irqs; j += 32) |
176 | omap_alloc_gc(bank->base_reg + j, j, 32); | 192 | omap_alloc_gc(bank->base_reg + j, j + irq_base, 32); |
177 | 193 | ||
178 | nr_of_irqs += bank->nr_irqs; | 194 | nr_of_irqs += bank->nr_irqs; |
179 | nr_banks++; | 195 | nr_banks++; |
180 | } | 196 | } |
181 | 197 | ||
182 | printk(KERN_INFO "Total of %ld interrupts on %d active controller%s\n", | 198 | pr_info("Total of %ld interrupts on %d active controller%s\n", |
183 | nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : ""); | 199 | nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : ""); |
184 | } | 200 | } |
185 | 201 | ||
186 | void __init omap2_init_irq(void) | 202 | void __init omap2_init_irq(void) |
187 | { | 203 | { |
188 | omap_init_irq(OMAP24XX_IC_BASE, 96); | 204 | omap_init_irq(OMAP24XX_IC_BASE, 96, NULL); |
189 | } | 205 | } |
190 | 206 | ||
191 | void __init omap3_init_irq(void) | 207 | void __init omap3_init_irq(void) |
192 | { | 208 | { |
193 | omap_init_irq(OMAP34XX_IC_BASE, 96); | 209 | omap_init_irq(OMAP34XX_IC_BASE, 96, NULL); |
194 | } | 210 | } |
195 | 211 | ||
196 | void __init ti81xx_init_irq(void) | 212 | void __init ti81xx_init_irq(void) |
197 | { | 213 | { |
198 | omap_init_irq(OMAP34XX_IC_BASE, 128); | 214 | omap_init_irq(OMAP34XX_IC_BASE, 128, NULL); |
199 | } | 215 | } |
200 | 216 | ||
201 | static inline void omap_intc_handle_irq(void __iomem *base_addr, struct pt_regs *regs) | 217 | static inline void omap_intc_handle_irq(void __iomem *base_addr, struct pt_regs *regs) |
@@ -225,8 +241,10 @@ out: | |||
225 | irqnr = readl_relaxed(base_addr + INTCPS_SIR_IRQ_OFFSET); | 241 | irqnr = readl_relaxed(base_addr + INTCPS_SIR_IRQ_OFFSET); |
226 | irqnr &= ACTIVEIRQ_MASK; | 242 | irqnr &= ACTIVEIRQ_MASK; |
227 | 243 | ||
228 | if (irqnr) | 244 | if (irqnr) { |
245 | irqnr = irq_find_mapping(domain, irqnr); | ||
229 | handle_IRQ(irqnr, regs); | 246 | handle_IRQ(irqnr, regs); |
247 | } | ||
230 | } while (irqnr); | 248 | } while (irqnr); |
231 | } | 249 | } |
232 | 250 | ||
@@ -236,6 +254,28 @@ asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs | |||
236 | omap_intc_handle_irq(base_addr, regs); | 254 | omap_intc_handle_irq(base_addr, regs); |
237 | } | 255 | } |
238 | 256 | ||
257 | int __init omap_intc_of_init(struct device_node *node, | ||
258 | struct device_node *parent) | ||
259 | { | ||
260 | struct resource res; | ||
261 | u32 nr_irqs = 96; | ||
262 | |||
263 | if (WARN_ON(!node)) | ||
264 | return -ENODEV; | ||
265 | |||
266 | if (of_address_to_resource(node, 0, &res)) { | ||
267 | WARN(1, "unable to get intc registers\n"); | ||
268 | return -EINVAL; | ||
269 | } | ||
270 | |||
271 | if (of_property_read_u32(node, "ti,intc-size", &nr_irqs)) | ||
272 | pr_warn("unable to get intc-size, default to %d\n", nr_irqs); | ||
273 | |||
274 | omap_init_irq(res.start, nr_irqs, of_node_get(node)); | ||
275 | |||
276 | return 0; | ||
277 | } | ||
278 | |||
239 | #ifdef CONFIG_ARCH_OMAP3 | 279 | #ifdef CONFIG_ARCH_OMAP3 |
240 | static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)]; | 280 | static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)]; |
241 | 281 | ||