diff options
author | Sascha Hauer <s.hauer@pengutronix.de> | 2012-05-16 06:01:40 -0400 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2012-05-16 06:38:39 -0400 |
commit | c040be003f16a1bdd7997cc4ab7fc5fd43acb03b (patch) | |
tree | 4f112e5313b786f56f96aa12682ab113301acd5a /arch | |
parent | 4f5a9fd341e8ffd825ecf56155df6fe6c3d732b1 (diff) |
ARM i.MX5: fix gpt peripheral clock path
- The gpt peripheral clk parent is per_root, not ipg
- The register for selectin per_lp_apm and per_root is
MXC_CCM_CBCMR, not MXC_CCM_CBCDR
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/mach-imx/clk-imx51-imx53.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c index b8a382defb23..1e7828d6be95 100644 --- a/arch/arm/mach-imx/clk-imx51-imx53.c +++ b/arch/arm/mach-imx/clk-imx51-imx53.c | |||
@@ -94,12 +94,12 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil, | |||
94 | periph_apm_sel, ARRAY_SIZE(periph_apm_sel)); | 94 | periph_apm_sel, ARRAY_SIZE(periph_apm_sel)); |
95 | clk[main_bus] = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1, | 95 | clk[main_bus] = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1, |
96 | main_bus_sel, ARRAY_SIZE(main_bus_sel)); | 96 | main_bus_sel, ARRAY_SIZE(main_bus_sel)); |
97 | clk[per_lp_apm] = imx_clk_mux("per_lp_apm", MXC_CCM_CBCDR, 1, 1, | 97 | clk[per_lp_apm] = imx_clk_mux("per_lp_apm", MXC_CCM_CBCMR, 1, 1, |
98 | per_lp_apm_sel, ARRAY_SIZE(per_lp_apm_sel)); | 98 | per_lp_apm_sel, ARRAY_SIZE(per_lp_apm_sel)); |
99 | clk[per_pred1] = imx_clk_divider("per_pred1", "per_lp_apm", MXC_CCM_CBCDR, 6, 2); | 99 | clk[per_pred1] = imx_clk_divider("per_pred1", "per_lp_apm", MXC_CCM_CBCDR, 6, 2); |
100 | clk[per_pred2] = imx_clk_divider("per_pred2", "per_pred1", MXC_CCM_CBCDR, 3, 3); | 100 | clk[per_pred2] = imx_clk_divider("per_pred2", "per_pred1", MXC_CCM_CBCDR, 3, 3); |
101 | clk[per_podf] = imx_clk_divider("per_podf", "per_pred2", MXC_CCM_CBCDR, 0, 3); | 101 | clk[per_podf] = imx_clk_divider("per_podf", "per_pred2", MXC_CCM_CBCDR, 0, 3); |
102 | clk[per_root] = imx_clk_mux("per_root", MXC_CCM_CBCDR, 1, 0, | 102 | clk[per_root] = imx_clk_mux("per_root", MXC_CCM_CBCMR, 0, 1, |
103 | per_root_sel, ARRAY_SIZE(per_root_sel)); | 103 | per_root_sel, ARRAY_SIZE(per_root_sel)); |
104 | clk[ahb] = imx_clk_divider("ahb", "main_bus", MXC_CCM_CBCDR, 10, 3); | 104 | clk[ahb] = imx_clk_divider("ahb", "main_bus", MXC_CCM_CBCDR, 10, 3); |
105 | clk[ahb_max] = imx_clk_gate2("ahb_max", "ahb", MXC_CCM_CCGR0, 28); | 105 | clk[ahb_max] = imx_clk_gate2("ahb_max", "ahb", MXC_CCM_CCGR0, 28); |
@@ -162,7 +162,7 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil, | |||
162 | clk[pwm1_hf_gate] = imx_clk_gate2("pwm1_hf_gate", "ipg", MXC_CCM_CCGR2, 12); | 162 | clk[pwm1_hf_gate] = imx_clk_gate2("pwm1_hf_gate", "ipg", MXC_CCM_CCGR2, 12); |
163 | clk[pwm2_ipg_gate] = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14); | 163 | clk[pwm2_ipg_gate] = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14); |
164 | clk[pwm2_hf_gate] = imx_clk_gate2("pwm2_hf_gate", "ipg", MXC_CCM_CCGR2, 16); | 164 | clk[pwm2_hf_gate] = imx_clk_gate2("pwm2_hf_gate", "ipg", MXC_CCM_CCGR2, 16); |
165 | clk[gpt_gate] = imx_clk_gate2("gpt_gate", "ipg", MXC_CCM_CCGR2, 18); | 165 | clk[gpt_gate] = imx_clk_gate2("gpt_gate", "per_root", MXC_CCM_CCGR2, 18); |
166 | clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2, 24); | 166 | clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2, 24); |
167 | clk[usboh3_gate] = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2, 26); | 167 | clk[usboh3_gate] = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2, 26); |
168 | clk[usboh3_per_gate] = imx_clk_gate2("usboh3_per_gate", "usboh3_podf", MXC_CCM_CCGR2, 28); | 168 | clk[usboh3_per_gate] = imx_clk_gate2("usboh3_per_gate", "usboh3_podf", MXC_CCM_CCGR2, 28); |