Merge branch 'ppi-irq-core-for-rmk' of git://github.com/mzyngier/arm-platforms into devel-stable

38 files changed, 465 insertions, 272 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index c8d5ec8a9391..2686959319a0 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1420,6 +1420,31 @@ config SMP_ON_UP
 
           If you don't know what to do here, say Y.
 
+config ARM_CPU_TOPOLOGY
+        bool "Support cpu topology definition"
+        depends on SMP && CPU_V7
+        default y
+        help
+          Support ARM cpu topology definition. The MPIDR register defines
+          affinity between processors which is then used to describe the cpu
+          topology of an ARM System.
+
+config SCHED_MC
+        bool "Multi-core scheduler support"
+        depends on ARM_CPU_TOPOLOGY
+        help
+          Multi-core scheduler support improves the CPU scheduler's decision
+          making when dealing with multi-core CPU chips at a cost of slightly
+          increased overhead in some places. If unsure say N here.
+
+config SCHED_SMT
+        bool "SMT scheduler support"
+        depends on ARM_CPU_TOPOLOGY
+        help
+          Improves the CPU scheduler's decision making when dealing with
+          MultiThreading at a cost of slightly increased overhead in some
+          places. If unsure say N here.
+
 config HAVE_ARM_SCU
         bool
         help
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index 734db99eaee7..016c1aeb847c 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -29,6 +29,9 @@
 #include <linux/cpu_pm.h>
 #include <linux/cpumask.h>
 #include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/percpu.h>
+#include <linux/slab.h>
 
 #include <asm/irq.h>
 #include <asm/mach/irq.h>
@@ -181,7 +184,7 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
                 return -EINVAL;
 
         mask = 0xff << shift;
-        bit = 1 << (cpu + shift);
+        bit = 1 << (cpu_logical_map(cpu) + shift);
 
         spin_lock(&irq_controller_lock);
         val = readl_relaxed(reg) & ~mask;
@@ -260,9 +263,16 @@ static void __init gic_dist_init(struct gic_chip_data *gic,
         unsigned int irq_start)
 {
         unsigned int gic_irqs, irq_limit, i;
+        u32 cpumask;
         void __iomem *base = gic->dist_base;
-        u32 cpumask = 1 << smp_processor_id();
+        u32 cpu = 0;
+        u32 nrppis = 0, ppi_base = 0;
 
+#ifdef CONFIG_SMP
+        cpu = cpu_logical_map(smp_processor_id());
+#endif
+
+        cpumask = 1 << cpu;
         cpumask |= cpumask << 8;
         cpumask |= cpumask << 16;
 
@@ -280,6 +290,23 @@ static void __init gic_dist_init(struct gic_chip_data *gic,
         gic->gic_irqs = gic_irqs;
 
         /*
+         * Nobody would be insane enough to use PPIs on a secondary
+         * GIC, right?
+         */
+        if (gic == &gic_data[0]) {
+                nrppis = (32 - irq_start) & 31;
+
+                /* The GIC only supports up to 16 PPIs. */
+                if (nrppis > 16)
+                        BUG();
+
+                ppi_base = gic->irq_offset + 32 - nrppis;
+        }
+
+        pr_info("Configuring GIC with %d sources (%d PPIs)\n",
+                gic_irqs, (gic == &gic_data[0]) ? nrppis : 0);
+
+        /*
          * Set all global interrupts to be level triggered, active low.
          */
         for (i = 32; i < gic_irqs; i += 16)
@@ -314,7 +341,17 @@ static void __init gic_dist_init(struct gic_chip_data *gic,
         /*
          * Setup the Linux IRQ subsystem.
          */
-        for (i = irq_start; i < irq_limit; i++) {
+        for (i = 0; i < nrppis; i++) {
+                int ppi = i + ppi_base;
+
+                irq_set_percpu_devid(ppi);
+                irq_set_chip_and_handler(ppi, &gic_chip,
+                                         handle_percpu_devid_irq);
+                irq_set_chip_data(ppi, gic);
+                set_irq_flags(ppi, IRQF_VALID | IRQF_NOAUTOEN);
+        }
+
+        for (i = irq_start + nrppis; i < irq_limit; i++) {
                 irq_set_chip_and_handler(i, &gic_chip, handle_fasteoi_irq);
                 irq_set_chip_data(i, gic);
                 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
@@ -557,20 +594,15 @@ void __cpuinit gic_secondary_init(unsigned int gic_nr)
         gic_cpu_init(&gic_data[gic_nr]);
 }
 
-void __cpuinit gic_enable_ppi(unsigned int irq)
-{
-        unsigned long flags;
-
-        local_irq_save(flags);
-        irq_set_status_flags(irq, IRQ_NOPROBE);
-        gic_unmask_irq(irq_get_irq_data(irq));
-        local_irq_restore(flags);
-}
-
 #ifdef CONFIG_SMP
 void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
 {
-        unsigned long map = *cpus_addr(*mask);
+        int cpu;
+        unsigned long map = 0;
+
+        /* Convert our logical CPU mask into a physical one. */
+        for_each_cpu(cpu, mask)
+                map |= 1 << cpu_logical_map(cpu);
 
         /*
          * Ensure that stores to Normal memory are visible to the
diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index cd4458f64171..cb47d28cbe1f 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -8,6 +8,7 @@
 #define CPUID_CACHETYPE 1
 #define CPUID_TCM       2
 #define CPUID_TLBTYPE   3
+#define CPUID_MPIDR     5
 
 #define CPUID_EXT_PFR0  "c1, 0"
 #define CPUID_EXT_PFR1  "c1, 1"
@@ -70,6 +71,11 @@ static inline unsigned int __attribute_const__ read_cpuid_tcmstatus(void)
         return read_cpuid(CPUID_TCM);
 }
 
+static inline unsigned int __attribute_const__ read_cpuid_mpidr(void)
+{
+        return read_cpuid(CPUID_MPIDR);
+}
+
 /*
  * Intel's XScale3 core supports some v6 features (supersections, L2)
  * but advertises itself as v5 as it does not support the v6 ISA.  For
diff --git a/arch/arm/include/asm/entry-macro-multi.S b/arch/arm/include/asm/entry-macro-multi.S
index 2f1e2098dfe7..88d61815f0c0 100644
--- a/arch/arm/include/asm/entry-macro-multi.S
+++ b/arch/arm/include/asm/entry-macro-multi.S
@@ -25,13 +25,6 @@
         movne   r1, sp
         adrne   lr, BSYM(1b)
         bne     do_IPI
-
-#ifdef CONFIG_LOCAL_TIMERS
-        test_for_ltirq r0, r2, r6, lr
-        movne   r0, sp
-        adrne   lr, BSYM(1b)
-        bne     do_local_timer
-#endif
 #endif
 9997:
         .endm
diff --git a/arch/arm/include/asm/exception.h b/arch/arm/include/asm/exception.h
new file mode 100644
index 000000000000..5abaf5bbd985
--- /dev/null
+++ b/arch/arm/include/asm/exception.h
@@ -0,0 +1,19 @@
+/*
+ * Annotations for marking C functions as exception handlers.
+ *
+ * These should only be used for C functions that are called from the low
+ * level exception entry code and not any intervening C code.
+ */
+#ifndef __ASM_ARM_EXCEPTION_H
+#define __ASM_ARM_EXCEPTION_H
+
+#include <linux/ftrace.h>
+
+#define __exception     __attribute__((section(".exception.text")))
+#ifdef CONFIG_FUNCTION_GRAPH_TRACER
+#define __exception_irq_entry   __irq_entry
+#else
+#define __exception_irq_entry   __exception
+#endif
+
+#endif /* __ASM_ARM_EXCEPTION_H */
diff --git a/arch/arm/include/asm/hardirq.h b/arch/arm/include/asm/hardirq.h
index 89ad1805e579..ddf07a92a6c8 100644
--- a/arch/arm/include/asm/hardirq.h
+++ b/arch/arm/include/asm/hardirq.h
@@ -9,9 +9,6 @@
 
 typedef struct {
         unsigned int __softirq_pending;
-#ifdef CONFIG_LOCAL_TIMERS
-        unsigned int local_timer_irqs;
-#endif
 #ifdef CONFIG_SMP
         unsigned int ipi_irqs[NR_IPI];
 #endif
diff --git a/arch/arm/include/asm/hardware/entry-macro-gic.S b/arch/arm/include/asm/hardware/entry-macro-gic.S
index c115b82fe80a..74ebc803904d 100644
--- a/arch/arm/include/asm/hardware/entry-macro-gic.S
+++ b/arch/arm/include/asm/hardware/entry-macro-gic.S
@@ -22,15 +22,11 @@
  * interrupt controller spec.  To wit:
  *
  * Interrupts 0-15 are IPI
- * 16-28 are reserved
- * 29-31 are local.  We allow 30 to be used for the watchdog.
+ * 16-31 are local.  We allow 30 to be used for the watchdog.
  * 32-1020 are global
  * 1021-1022 are reserved
  * 1023 is "spurious" (no interrupt)
  *
- * For now, we ignore all local interrupts so only return an interrupt if it's
- * between 30 and 1020.  The test_for_ipi routine below will pick up on IPIs.
- *
  * A simple read from the controller will tell us the number of the highest
  * priority enabled interrupt.  We then just need to check whether it is in the
  * valid range for an IRQ (30-1020 inclusive).
@@ -43,7 +39,7 @@
 
         ldr     \tmp, =1021
         bic     \irqnr, \irqstat, #0x1c00
-        cmp     \irqnr, #29
+        cmp     \irqnr, #15
         cmpcc   \irqnr, \irqnr
         cmpne   \irqnr, \tmp
         cmpcs   \irqnr, \irqnr
@@ -62,14 +58,3 @@
         strcc   \irqstat, [\base, #GIC_CPU_EOI]
         cmpcs   \irqnr, \irqnr
         .endm
-
-/* As above, this assumes that irqstat and base are preserved.. */
-
-        .macro test_for_ltirq, irqnr, irqstat, base, tmp
-        bic     \irqnr, \irqstat, #0x1c00
-        mov     \tmp, #0
-        cmp     \irqnr, #29
-        moveq   \tmp, #1
-        streq   \irqstat, [\base, #GIC_CPU_EOI]
-        cmp     \tmp, #0
-        .endm
diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h
index c5627057b1c7..14867e12f205 100644
--- a/arch/arm/include/asm/hardware/gic.h
+++ b/arch/arm/include/asm/hardware/gic.h
@@ -40,7 +40,6 @@ void gic_init(unsigned int, unsigned int, void __iomem *, void __iomem *);
 void gic_secondary_init(unsigned int);
 void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
 void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);
-void gic_enable_ppi(unsigned int);
 
 struct gic_chip_data {
         unsigned int irq_offset;
diff --git a/arch/arm/include/asm/localtimer.h b/arch/arm/include/asm/localtimer.h
index 080d74f8128d..f5e1cec7e35c 100644
--- a/arch/arm/include/asm/localtimer.h
+++ b/arch/arm/include/asm/localtimer.h
@@ -10,6 +10,8 @@
 #ifndef __ASM_ARM_LOCALTIMER_H
 #define __ASM_ARM_LOCALTIMER_H
 
+#include <linux/interrupt.h>
+
 struct clock_event_device;
 
 /*
@@ -17,27 +19,20 @@ struct clock_event_device;
  */
 void percpu_timer_setup(void);
 
-/*
- * Called from assembly, this is the local timer IRQ handler
- */
-asmlinkage void do_local_timer(struct pt_regs *);
-
-
 #ifdef CONFIG_LOCAL_TIMERS
 
 #ifdef CONFIG_HAVE_ARM_TWD
 
 #include "smp_twd.h"
 
-#define local_timer_ack()       twd_timer_ack()
+#define local_timer_stop(c)     twd_timer_stop((c))
 
 #else
 
 /*
- * Platform provides this to acknowledge a local timer IRQ.
- * Returns true if the local timer IRQ is to be processed.
+ * Stop the local timer
  */
-int local_timer_ack(void);
+void local_timer_stop(struct clock_event_device *);
 
 #endif
 
@@ -52,6 +47,10 @@ static inline int local_timer_setup(struct clock_event_device *evt)
 {
         return -ENXIO;
 }
+
+static inline void local_timer_stop(struct clock_event_device *evt)
+{
+}
 #endif
 
 #endif
diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h
index e42d96a45d3e..1e5717afc4ac 100644
--- a/arch/arm/include/asm/smp.h
+++ b/arch/arm/include/asm/smp.h
@@ -33,6 +33,11 @@ extern void show_ipi_list(struct seq_file *, int);
 asmlinkage void do_IPI(int ipinr, struct pt_regs *regs);
 
 /*
+ * Called from C code, this handles an IPI.
+ */
+void handle_IPI(int ipinr, struct pt_regs *regs);
+
+/*
  * Setup the set of possible CPUs (via set_cpu_possible)
  */
 extern void smp_init_cpus(void);
@@ -66,6 +71,12 @@ extern void platform_secondary_init(unsigned int cpu);
 extern void platform_smp_prepare_cpus(unsigned int);
 
 /*
+ * Logical CPU mapping.
+ */
+extern int __cpu_logical_map[NR_CPUS];
+#define cpu_logical_map(cpu)    __cpu_logical_map[cpu]
+
+/*
  * Initial data for bringing up a secondary CPU.
  */
 struct secondary_data {
@@ -88,9 +99,4 @@ extern void platform_cpu_enable(unsigned int cpu);
 extern void arch_send_call_function_single_ipi(int cpu);
 extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
 
-/*
- * show local interrupt info
- */
-extern void show_local_irqs(struct seq_file *, int);
-
 #endif /* ifndef __ASM_ARM_SMP_H */
diff --git a/arch/arm/include/asm/smp_twd.h b/arch/arm/include/asm/smp_twd.h
index fed9981fba08..ef9ffba97ad8 100644
--- a/arch/arm/include/asm/smp_twd.h
+++ b/arch/arm/include/asm/smp_twd.h
@@ -22,7 +22,7 @@ struct clock_event_device;
 
 extern void __iomem *twd_base;
 
-int twd_timer_ack(void);
 void twd_timer_setup(struct clock_event_device *);
+void twd_timer_stop(struct clock_event_device *);
 
 #endif
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 832888d0c20c..ed6b0499a106 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -62,13 +62,6 @@
 
 #include <asm/outercache.h>
 
-#define __exception     __attribute__((section(".exception.text")))
-#ifdef CONFIG_FUNCTION_GRAPH_TRACER
-#define __exception_irq_entry   __irq_entry
-#else
-#define __exception_irq_entry   __exception
-#endif
-
 struct thread_info;
 struct task_struct;
 
diff --git a/arch/arm/include/asm/topology.h b/arch/arm/include/asm/topology.h
index accbd7cad9b5..a7e457ed27c3 100644
--- a/arch/arm/include/asm/topology.h
+++ b/arch/arm/include/asm/topology.h
@@ -1,6 +1,39 @@
 #ifndef _ASM_ARM_TOPOLOGY_H
 #define _ASM_ARM_TOPOLOGY_H
 
+#ifdef CONFIG_ARM_CPU_TOPOLOGY
+
+#include <linux/cpumask.h>
+
+struct cputopo_arm {
+        int thread_id;
+        int core_id;
+        int socket_id;
+        cpumask_t thread_sibling;
+        cpumask_t core_sibling;
+};
+
+extern struct cputopo_arm cpu_topology[NR_CPUS];
+
+#define topology_physical_package_id(cpu)       (cpu_topology[cpu].socket_id)
+#define topology_core_id(cpu)           (cpu_topology[cpu].core_id)
+#define topology_core_cpumask(cpu)      (&cpu_topology[cpu].core_sibling)
+#define topology_thread_cpumask(cpu)    (&cpu_topology[cpu].thread_sibling)
+
+#define mc_capable()    (cpu_topology[0].socket_id != -1)
+#define smt_capable()   (cpu_topology[0].thread_id != -1)
+
+void init_cpu_topology(void);
+void store_cpu_topology(unsigned int cpuid);
+const struct cpumask *cpu_coregroup_mask(unsigned int cpu);
+
+#else
+
+static inline void init_cpu_topology(void) { }
+static inline void store_cpu_topology(unsigned int cpuid) { }
+
+#endif
+
 #include <asm-generic/topology.h>
 
 #endif /* _ASM_ARM_TOPOLOGY_H */
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 8fa83f54c967..7cac26c5f502 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -73,6 +73,7 @@ obj-$(CONFIG_IWMMXT)		+= iwmmxt.o
 obj-$(CONFIG_CPU_HAS_PMU)       += pmu.o
 obj-$(CONFIG_HW_PERF_EVENTS)    += perf_event.o
 AFLAGS_iwmmxt.o                 := -Wa,-mcpu=iwmmxt
+obj-$(CONFIG_ARM_CPU_TOPOLOGY)  += topology.o
 
 ifneq ($(CONFIG_ARCH_EBSA110),y)
   obj-y         += io.o
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index de3dcab8610b..7cb29261249a 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -35,8 +35,8 @@
 #include <linux/list.h>
 #include <linux/kallsyms.h>
 #include <linux/proc_fs.h>
-#include <linux/ftrace.h>
 
+#include <asm/exception.h>
 #include <asm/system.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/irq.h>
@@ -59,9 +59,6 @@ int arch_show_interrupts(struct seq_file *p, int prec)
 #ifdef CONFIG_SMP
         show_ipi_list(p, prec);
 #endif
-#ifdef CONFIG_LOCAL_TIMERS
-        show_local_irqs(p, prec);
-#endif
         seq_printf(p, "%*s: %10lu\n", prec, "Err", irq_err_count);
         return 0;
 }
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index d88ff0230e82..a96c08cd6125 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -16,7 +16,6 @@
 #include <linux/cache.h>
 #include <linux/profile.h>
 #include <linux/errno.h>
-#include <linux/ftrace.h>
 #include <linux/mm.h>
 #include <linux/err.h>
 #include <linux/cpu.h>
@@ -31,6 +30,8 @@
 #include <asm/cacheflush.h>
 #include <asm/cpu.h>
 #include <asm/cputype.h>
+#include <asm/exception.h>
+#include <asm/topology.h>
 #include <asm/mmu_context.h>
 #include <asm/pgtable.h>
 #include <asm/pgalloc.h>
@@ -39,6 +40,7 @@
 #include <asm/tlbflush.h>
 #include <asm/ptrace.h>
 #include <asm/localtimer.h>
+#include <asm/smp_plat.h>
 
 /*
  * as from 2.5, kernels no longer have an init_tasks structure
@@ -259,6 +261,20 @@ void __ref cpu_die(void)
 }
 #endif /* CONFIG_HOTPLUG_CPU */
 
+int __cpu_logical_map[NR_CPUS];
+
+void __init smp_setup_processor_id(void)
+{
+        int i;
+        u32 cpu = is_smp() ? read_cpuid_mpidr() & 0xff : 0;
+
+        cpu_logical_map(0) = cpu;
+        for (i = 1; i < NR_CPUS; ++i)
+                cpu_logical_map(i) = i == cpu ? 0 : i;
+
+        printk(KERN_INFO "Booting Linux on physical CPU %d\n", cpu);
+}
+
 /*
  * Called by both boot and secondaries to move global data into
  * per-processor storage.
@@ -268,6 +284,8 @@ static void __cpuinit smp_store_cpu_info(unsigned int cpuid)
         struct cpuinfo_arm *cpu_info = &per_cpu(cpu_data, cpuid);
 
         cpu_info->loops_per_jiffy = loops_per_jiffy;
+
+        store_cpu_topology(cpuid);
 }
 
 /*
@@ -358,6 +376,8 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
 {
         unsigned int ncores = num_possible_cpus();
 
+        init_cpu_topology();
+
         smp_store_cpu_info(smp_processor_id());
 
         /*
@@ -437,10 +457,6 @@ u64 smp_irq_stat_cpu(unsigned int cpu)
         for (i = 0; i < NR_IPI; i++)
                 sum += __get_irq_stat(cpu, ipi_irqs[i]);
 
-#ifdef CONFIG_LOCAL_TIMERS
-        sum += __get_irq_stat(cpu, local_timer_irqs);
-#endif
-
         return sum;
 }
 
@@ -457,33 +473,6 @@ static void ipi_timer(void)
         irq_exit();
 }
 
-#ifdef CONFIG_LOCAL_TIMERS
-asmlinkage void __exception_irq_entry do_local_timer(struct pt_regs *regs)
-{
-        struct pt_regs *old_regs = set_irq_regs(regs);
-        int cpu = smp_processor_id();
-
-        if (local_timer_ack()) {
-                __inc_irq_stat(cpu, local_timer_irqs);
-                ipi_timer();
-        }
-
-        set_irq_regs(old_regs);
-}
-
-void show_local_irqs(struct seq_file *p, int prec)
-{
-        unsigned int cpu;
-
-        seq_printf(p, "%*s: ", prec, "LOC");
-
-        for_each_present_cpu(cpu)
-                seq_printf(p, "%10u ", __get_irq_stat(cpu, local_timer_irqs));
-
-        seq_printf(p, " Local timer interrupts\n");
-}
-#endif
-
 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
 static void smp_timer_broadcast(const struct cpumask *mask)
 {
@@ -534,7 +523,7 @@ static void percpu_timer_stop(void)
         unsigned int cpu = smp_processor_id();
         struct clock_event_device *evt = &per_cpu(percpu_clockevent, cpu);
 
-        evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
+        local_timer_stop(evt);
 }
 #endif
 
@@ -567,6 +556,11 @@ static void ipi_cpu_stop(unsigned int cpu)
  */
 asmlinkage void __exception_irq_entry do_IPI(int ipinr, struct pt_regs *regs)
 {
+        handle_IPI(ipinr, regs);
+}
+
+void handle_IPI(int ipinr, struct pt_regs *regs)
+{
         unsigned int cpu = smp_processor_id();
         struct pt_regs *old_regs = set_irq_regs(regs);
 
diff --git a/arch/arm/kernel/smp_scu.c b/arch/arm/kernel/smp_scu.c
index 79ed5e7f204a..5b6d536cbfe3 100644
--- a/arch/arm/kernel/smp_scu.c
+++ b/arch/arm/kernel/smp_scu.c
@@ -33,7 +33,7 @@ unsigned int __init scu_get_core_count(void __iomem *scu_base)
 /*
  * Enable the SCU
  */
-void __init scu_enable(void __iomem *scu_base)
+void scu_enable(void __iomem *scu_base)
 {
         u32 scu_ctrl;
 
diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c
index 01c186222f3b..a8a6682d6b52 100644
--- a/arch/arm/kernel/smp_twd.c
+++ b/arch/arm/kernel/smp_twd.c
@@ -19,6 +19,7 @@
 #include <linux/io.h>
 
 #include <asm/smp_twd.h>
+#include <asm/localtimer.h>
 #include <asm/hardware/gic.h>
 
 /* set up by the platform code */
@@ -26,6 +27,8 @@ void __iomem *twd_base;
 
 static unsigned long twd_timer_rate;
 
+static struct clock_event_device __percpu **twd_evt;
+
 static void twd_set_mode(enum clock_event_mode mode,
                         struct clock_event_device *clk)
 {
@@ -80,6 +83,12 @@ int twd_timer_ack(void)
         return 0;
 }
 
+void twd_timer_stop(struct clock_event_device *clk)
+{
+        twd_set_mode(CLOCK_EVT_MODE_UNUSED, clk);
+        disable_percpu_irq(clk->irq);
+}
+
 static void __cpuinit twd_calibrate_rate(void)
 {
         unsigned long count;
@@ -119,11 +128,43 @@ static void __cpuinit twd_calibrate_rate(void)
         }
 }
 
+static irqreturn_t twd_handler(int irq, void *dev_id)
+{
+        struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
+
+        if (twd_timer_ack()) {
+                evt->event_handler(evt);
+                return IRQ_HANDLED;
+        }
+
+        return IRQ_NONE;
+}
+
 /*
  * Setup the local clock events for a CPU.
  */
 void __cpuinit twd_timer_setup(struct clock_event_device *clk)
 {
+        struct clock_event_device **this_cpu_clk;
+
+        if (!twd_evt) {
+                int err;
+
+                twd_evt = alloc_percpu(struct clock_event_device *);
+                if (!twd_evt) {
+                        pr_err("twd: can't allocate memory\n");
+                        return;
+                }
+
+                err = request_percpu_irq(clk->irq, twd_handler,
+                                         "twd", twd_evt);
+                if (err) {
+                        pr_err("twd: can't register interrupt %d (%d)\n",
+                               clk->irq, err);
+                        return;
+                }
+        }
+
         twd_calibrate_rate();
 
         clk->name = "local_timer";
@@ -137,8 +178,10 @@ void __cpuinit twd_timer_setup(struct clock_event_device *clk)
         clk->max_delta_ns = clockevent_delta2ns(0xffffffff, clk);
         clk->min_delta_ns = clockevent_delta2ns(0xf, clk);
 
+        this_cpu_clk = __this_cpu_ptr(twd_evt);
+        *this_cpu_clk = clk;
+
         clockevents_register_device(clk);
 
-        /* Make sure our local interrupt controller has this enabled */
-        gic_enable_ppi(clk->irq);
+        enable_percpu_irq(clk->irq, 0);
 }
diff --git a/arch/arm/kernel/topology.c b/arch/arm/kernel/topology.c
new file mode 100644
index 000000000000..1040c00405d0
--- /dev/null
+++ b/arch/arm/kernel/topology.c
@@ -0,0 +1,148 @@
+/*
+ * arch/arm/kernel/topology.c
+ *
+ * Copyright (C) 2011 Linaro Limited.
+ * Written by: Vincent Guittot
+ *
+ * based on arch/sh/kernel/topology.c
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/cpu.h>
+#include <linux/cpumask.h>
+#include <linux/init.h>
+#include <linux/percpu.h>
+#include <linux/node.h>
+#include <linux/nodemask.h>
+#include <linux/sched.h>
+
+#include <asm/cputype.h>
+#include <asm/topology.h>
+
+#define MPIDR_SMP_BITMASK (0x3 << 30)
+#define MPIDR_SMP_VALUE (0x2 << 30)
+
+#define MPIDR_MT_BITMASK (0x1 << 24)
+
+/*
+ * These masks reflect the current use of the affinity levels.
+ * The affinity level can be up to 16 bits according to ARM ARM
+ */
+
+#define MPIDR_LEVEL0_MASK 0x3
+#define MPIDR_LEVEL0_SHIFT 0
+
+#define MPIDR_LEVEL1_MASK 0xF
+#define MPIDR_LEVEL1_SHIFT 8
+
+#define MPIDR_LEVEL2_MASK 0xFF
+#define MPIDR_LEVEL2_SHIFT 16
+
+struct cputopo_arm cpu_topology[NR_CPUS];
+
+const struct cpumask *cpu_coregroup_mask(unsigned int cpu)
+{
+        return &cpu_topology[cpu].core_sibling;
+}
+
+/*
+ * store_cpu_topology is called at boot when only one cpu is running
+ * and with the mutex cpu_hotplug.lock locked, when several cpus have booted,
+ * which prevents simultaneous write access to cpu_topology array
+ */
+void store_cpu_topology(unsigned int cpuid)
+{
+        struct cputopo_arm *cpuid_topo = &cpu_topology[cpuid];
+        unsigned int mpidr;
+        unsigned int cpu;
+
+        /* If the cpu topology has been already set, just return */
+        if (cpuid_topo->core_id != -1)
+                return;
+
+        mpidr = read_cpuid_mpidr();
+
+        /* create cpu topology mapping */
+        if ((mpidr & MPIDR_SMP_BITMASK) == MPIDR_SMP_VALUE) {
+                /*
+                 * This is a multiprocessor system
+                 * multiprocessor format & multiprocessor mode field are set
+                 */
+
+                if (mpidr & MPIDR_MT_BITMASK) {
+                        /* core performance interdependency */
+                        cpuid_topo->thread_id = (mpidr >> MPIDR_LEVEL0_SHIFT)
+                                & MPIDR_LEVEL0_MASK;
+                        cpuid_topo->core_id = (mpidr >> MPIDR_LEVEL1_SHIFT)
+                                & MPIDR_LEVEL1_MASK;
+                        cpuid_topo->socket_id = (mpidr >> MPIDR_LEVEL2_SHIFT)
+                                & MPIDR_LEVEL2_MASK;
+                } else {
+                        /* largely independent cores */
+                        cpuid_topo->thread_id = -1;
+                        cpuid_topo->core_id = (mpidr >> MPIDR_LEVEL0_SHIFT)
+                                & MPIDR_LEVEL0_MASK;
+                        cpuid_topo->socket_id = (mpidr >> MPIDR_LEVEL1_SHIFT)
+                                & MPIDR_LEVEL1_MASK;
+                }
+        } else {
+                /*
+                 * This is an uniprocessor system
+                 * we are in multiprocessor format but uniprocessor system
+                 * or in the old uniprocessor format
+                 */
+                cpuid_topo->thread_id = -1;
+                cpuid_topo->core_id = 0;
+                cpuid_topo->socket_id = -1;
+        }
+
+        /* update core and thread sibling masks */
+        for_each_possible_cpu(cpu) {
+                struct cputopo_arm *cpu_topo = &cpu_topology[cpu];
+
+                if (cpuid_topo->socket_id == cpu_topo->socket_id) {
+                        cpumask_set_cpu(cpuid, &cpu_topo->core_sibling);
+                        if (cpu != cpuid)
+                                cpumask_set_cpu(cpu,
+                                        &cpuid_topo->core_sibling);
+
+                        if (cpuid_topo->core_id == cpu_topo->core_id) {
+                                cpumask_set_cpu(cpuid,
+                                        &cpu_topo->thread_sibling);
+                                if (cpu != cpuid)
+                                        cpumask_set_cpu(cpu,
+                                                &cpuid_topo->thread_sibling);
+                        }
+                }
+        }
+        smp_wmb();
+
+        printk(KERN_INFO "CPU%u: thread %d, cpu %d, socket %d, mpidr %x\n",
+                cpuid, cpu_topology[cpuid].thread_id,
+                cpu_topology[cpuid].core_id,
+                cpu_topology[cpuid].socket_id, mpidr);
+}
+
+/*
+ * init_cpu_topology is called at boot when only one cpu is running
+ * which prevent simultaneous write access to cpu_topology array
+ */
+void init_cpu_topology(void)
+{
+        unsigned int cpu;
+
+        /* init core mask */
+        for_each_possible_cpu(cpu) {
+                struct cputopo_arm *cpu_topo = &(cpu_topology[cpu]);
+
+                cpu_topo->thread_id = -1;
+                cpu_topo->core_id =  -1;
+                cpu_topo->socket_id = -1;
+                cpumask_clear(&cpu_topo->core_sibling);
+                cpumask_clear(&cpu_topo->thread_sibling);
+        }
+        smp_wmb();
+}
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index bc9f9da782cb..210382555af1 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -27,6 +27,7 @@
 
 #include <linux/atomic.h>
 #include <asm/cacheflush.h>
+#include <asm/exception.h>
 #include <asm/system.h>
 #include <asm/unistd.h>
 #include <asm/traps.h>
diff --git a/arch/arm/mach-exynos4/include/mach/entry-macro.S b/arch/arm/mach-exynos4/include/mach/entry-macro.S
index d7a1e281ce7a..006a4f4c65c6 100644
--- a/arch/arm/mach-exynos4/include/mach/entry-macro.S
+++ b/arch/arm/mach-exynos4/include/mach/entry-macro.S
@@ -55,7 +55,7 @@
 
                 bic     \irqnr, \irqstat, #0x1c00
 
-                cmp     \irqnr, #29
+                cmp     \irqnr, #15
                 cmpcc   \irqnr, \irqnr
                 cmpne   \irqnr, \tmp
                 cmpcs   \irqnr, \irqnr
@@ -76,8 +76,3 @@
                 strcc   \irqstat, [\base, #GIC_CPU_EOI]
                 cmpcs   \irqnr, \irqnr
                 .endm
-
-                /* As above, this assumes that irqstat and base are preserved.. */
-
-                .macro test_for_ltirq, irqnr, irqstat, base, tmp
-                .endm
diff --git a/arch/arm/mach-exynos4/mct.c b/arch/arm/mach-exynos4/mct.c
index 1ae059b7ad7b..85a1bb79f11c 100644
--- a/arch/arm/mach-exynos4/mct.c
+++ b/arch/arm/mach-exynos4/mct.c
@@ -380,9 +380,11 @@ static void exynos4_mct_tick_init(struct clock_event_device *evt)
 
         if (cpu == 0) {
                 mct_tick0_event_irq.dev_id = &mct_tick[cpu];
+                evt->irq = IRQ_MCT_L0;
                 setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq);
         } else {
                 mct_tick1_event_irq.dev_id = &mct_tick[cpu];
+                evt->irq = IRQ_MCT_L1;
                 setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq);
                 irq_set_affinity(IRQ_MCT_L1, cpumask_of(1));
         }
@@ -394,9 +396,10 @@ void __cpuinit local_timer_setup(struct clock_event_device *evt)
         exynos4_mct_tick_init(evt);
 }
 
-int local_timer_ack(void)
+void local_timer_stop(struct clock_event_device *evt)
 {
-        return 0;
+        evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
+        disable_irq(evt->irq);
 }
 
 #endif /* CONFIG_LOCAL_TIMERS */
diff --git a/arch/arm/mach-exynos4/platsmp.c b/arch/arm/mach-exynos4/platsmp.c
index 7c2282c6ba81..a08c536923f9 100644
--- a/arch/arm/mach-exynos4/platsmp.c
+++ b/arch/arm/mach-exynos4/platsmp.c
@@ -191,12 +191,10 @@ void __init smp_init_cpus(void)
         ncores = scu_base ? scu_get_core_count(scu_base) : 1;
 
         /* sanity check */
-        if (ncores > NR_CPUS) {
-                printk(KERN_WARNING
-                       "EXYNOS4: no. of cores (%d) greater than configured "
-                       "maximum of %d - clipping\n",
-                       ncores, NR_CPUS);
-                ncores = NR_CPUS;
+        if (ncores > nr_cpu_ids) {
+                pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
+                        ncores, nr_cpu_ids);
+                ncores = nr_cpu_ids;
         }
 
         for (i = 0; i < ncores; i++)
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
index 9221f54778be..106170fb1844 100644
--- a/arch/arm/mach-msm/board-msm8x60.c
+++ b/arch/arm/mach-msm/board-msm8x60.c
@@ -53,8 +53,6 @@ static void __init msm8x60_map_io(void)
 
 static void __init msm8x60_init_irq(void)
 {
-        unsigned int i;
-
         gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
                  (void *)MSM_QGIC_CPU_BASE);
 
@@ -66,15 +64,6 @@ static void __init msm8x60_init_irq(void)
          */
         if (!machine_is_msm8x60_sim())
                 writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET);
-
-        /* FIXME: Not installing AVS_SVICINT and AVS_SVICINTSWDONE yet
-         * as they are configured as level, which does not play nice with
-         * handle_percpu_irq.
-         */
-        for (i = GIC_PPI_START; i < GIC_SPI_START; i++) {
-                if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE)
-                        irq_set_handler(i, handle_percpu_irq);
-        }
 }
 
 static void __init msm8x60_init(void)
diff --git a/arch/arm/mach-msm/include/mach/entry-macro-qgic.S b/arch/arm/mach-msm/include/mach/entry-macro-qgic.S
index 12467157afb9..717076f3ca73 100644
--- a/arch/arm/mach-msm/include/mach/entry-macro-qgic.S
+++ b/arch/arm/mach-msm/include/mach/entry-macro-qgic.S
@@ -8,81 +8,10 @@
  * warranty of any kind, whether express or implied.
  */
 
-#include <mach/hardware.h>
-#include <asm/hardware/gic.h>
+#include <asm/hardware/entry-macro-gic.S>
 
         .macro  disable_fiq
         .endm
 
-        .macro  get_irqnr_preamble, base, tmp
-        ldr     \base, =gic_cpu_base_addr
-        ldr     \base, [\base]
-        .endm
-
         .macro  arch_ret_to_user, tmp1, tmp2
         .endm
-
-        /*
-         * The interrupt numbering scheme is defined in the
-         * interrupt controller spec.  To wit:
-         *
-         * Migrated the code from ARM MP port to be more consistent
-         * with interrupt processing , the following still holds true
-         * however, all interrupts are treated the same regardless of
-         * if they are local IPI or PPI
-         *
-         * Interrupts 0-15 are IPI
-         * 16-31 are PPI
-         *   (16-18 are the timers)
-         * 32-1020 are global
-         * 1021-1022 are reserved
-         * 1023 is "spurious" (no interrupt)
-         *
-         * A simple read from the controller will tell us the number of the
-         * highest priority enabled interrupt.  We then just need to check
-         * whether it is in the valid range for an IRQ (0-1020 inclusive).
-         *
-         * Base ARM code assumes that the local (private) peripheral interrupts
-         * are not valid, we treat them differently, in that the privates are
-         * handled like normal shared interrupts with the exception that only
-         * one processor can register the interrupt and the handler must be
-         * the same for all processors.
-         */
-
-        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-
-        ldr  \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 =srcCPU,
-                                                   9-0 =int # */
-
-        bic     \irqnr, \irqstat, #0x1c00       @mask src
-        cmp     \irqnr, #15
-        ldr             \tmp, =1021
-        cmpcc   \irqnr, \irqnr
-        cmpne   \irqnr, \tmp
-        cmpcs   \irqnr, \irqnr
-
-        .endm
-
-        /* We assume that irqstat (the raw value of the IRQ acknowledge
-         * register) is preserved from the macro above.
-         * If there is an IPI, we immediately signal end of interrupt on the
-         * controller, since this requires the original irqstat value which
-         * we won't easily be able to recreate later.
-         */
-        .macro test_for_ipi, irqnr, irqstat, base, tmp
-    bic \irqnr, \irqstat, #0x1c00
-    cmp \irqnr, #16
-    strcc   \irqstat, [\base, #GIC_CPU_EOI]
-    cmpcs   \irqnr, \irqnr
-        .endm
-
-        /* As above, this assumes that irqstat and base are preserved.. */
-
-        .macro test_for_ltirq, irqnr, irqstat, base, tmp
-    bic \irqnr, \irqstat, #0x1c00
-    mov     \tmp, #0
-    cmp \irqnr, #16
-    moveq   \tmp, #1
-    streq   \irqstat, [\base, #GIC_CPU_EOI]
-    cmp \tmp, #0
-        .endm
diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c
index 1a1af9e56250..727659520912 100644
--- a/arch/arm/mach-msm/platsmp.c
+++ b/arch/arm/mach-msm/platsmp.c
@@ -156,6 +156,12 @@ void __init smp_init_cpus(void)
 {
         unsigned int i, ncores = get_core_count();
 
+        if (ncores > nr_cpu_ids) {
+                pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
+                        ncores, nr_cpu_ids);
+                ncores = nr_cpu_ids;
+        }
+
         for (i = 0; i < ncores; i++)
                 set_cpu_possible(i, true);
 
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index 63621f152c98..afeeca52fc66 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -71,12 +71,16 @@ enum timer_location {
 struct msm_clock {
         struct clock_event_device   clockevent;
         struct clocksource          clocksource;
-        struct irqaction            irq;
+        unsigned int                irq;
         void __iomem                *regbase;
         uint32_t                    freq;
         uint32_t                    shift;
         void __iomem                *global_counter;
         void __iomem                *local_counter;
+        union {
+                struct clock_event_device               *evt;
+                struct clock_event_device __percpu      **percpu_evt;
+        };              
 };
 
 enum {
@@ -87,13 +91,10 @@ enum {
 
 
 static struct msm_clock msm_clocks[];
-static struct clock_event_device *local_clock_event;
 
 static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
 {
-        struct clock_event_device *evt = dev_id;
-        if (smp_processor_id() != 0)
-                evt = local_clock_event;
+        struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
         if (evt->event_handler == NULL)
                 return IRQ_HANDLED;
         evt->event_handler(evt);
@@ -171,13 +172,7 @@ static struct msm_clock msm_clocks[] = {
                         .mask           = CLOCKSOURCE_MASK(32),
                         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
                 },
-                .irq = {
-                        .name    = "gp_timer",
-                        .flags   = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_RISING,
-                        .handler = msm_timer_interrupt,
-                        .dev_id  = &msm_clocks[0].clockevent,
-                        .irq     = INT_GP_TIMER_EXP
-                },
+                .irq = INT_GP_TIMER_EXP,
                 .freq = GPT_HZ,
         },
         [MSM_CLOCK_DGT] = {
@@ -196,13 +191,7 @@ static struct msm_clock msm_clocks[] = {
                         .mask           = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT)),
                         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
                 },
-                .irq = {
-                        .name    = "dg_timer",
-                        .flags   = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_RISING,
-                        .handler = msm_timer_interrupt,
-                        .dev_id  = &msm_clocks[1].clockevent,
-                        .irq     = INT_DEBUG_TIMER_EXP
-                },
+                .irq = INT_DEBUG_TIMER_EXP,
                 .freq = DGT_HZ >> MSM_DGT_SHIFT,
                 .shift = MSM_DGT_SHIFT,
         }
@@ -261,10 +250,30 @@ static void __init msm_timer_init(void)
                         printk(KERN_ERR "msm_timer_init: clocksource_register "
                                "failed for %s\n", cs->name);
 
-                res = setup_irq(clock->irq.irq, &clock->irq);
+                ce->irq = clock->irq;
+                if (cpu_is_msm8x60() || cpu_is_msm8960()) {
+                        clock->percpu_evt = alloc_percpu(struct clock_event_device *);
+                        if (!clock->percpu_evt) {
+                                pr_err("msm_timer_init: memory allocation "
+                                       "failed for %s\n", ce->name);
+                                continue;
+                        }
+
+                        *__this_cpu_ptr(clock->percpu_evt) = ce;
+                        res = request_percpu_irq(ce->irq, msm_timer_interrupt,
+                                                 ce->name, clock->percpu_evt);
+                        if (!res)
+                                enable_percpu_irq(ce->irq, 0);
+                } else {
+                        clock->evt = ce;
+                        res = request_irq(ce->irq, msm_timer_interrupt,
+                                          IRQF_TIMER | IRQF_NOBALANCING | IRQF_TRIGGER_RISING,
+                                          ce->name, &clock->evt);
+                }
+
                 if (res)
-                        printk(KERN_ERR "msm_timer_init: setup_irq "
-                               "failed for %s\n", cs->name);
+                        pr_err("msm_timer_init: request_irq failed for %s\n",
+                               ce->name);
 
                 clockevents_register_device(ce);
         }
@@ -273,6 +282,7 @@ static void __init msm_timer_init(void)
 #ifdef CONFIG_SMP
 int __cpuinit local_timer_setup(struct clock_event_device *evt)
 {
+        static bool local_timer_inited;
         struct msm_clock *clock = &msm_clocks[MSM_GLOBAL_TIMER];
 
         /* Use existing clock_event for cpu 0 */
@@ -281,12 +291,13 @@ int __cpuinit local_timer_setup(struct clock_event_device *evt)
 
         writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
 
-        if (!local_clock_event) {
+        if (!local_timer_inited) {
                 writel(0, clock->regbase  + TIMER_ENABLE);
                 writel(0, clock->regbase + TIMER_CLEAR);
                 writel(~0, clock->regbase + TIMER_MATCH_VAL);
+                local_timer_inited = true;
         }
-        evt->irq = clock->irq.irq;
+        evt->irq = clock->irq;
         evt->name = "local_timer";
         evt->features = CLOCK_EVT_FEAT_ONESHOT;
         evt->rating = clock->clockevent.rating;
@@ -298,17 +309,17 @@ int __cpuinit local_timer_setup(struct clock_event_device *evt)
                 clockevent_delta2ns(0xf0000000 >> clock->shift, evt);
         evt->min_delta_ns = clockevent_delta2ns(4, evt);
 
-        local_clock_event = evt;
-
-        gic_enable_ppi(clock->irq.irq);
+        *__this_cpu_ptr(clock->percpu_evt) = evt;
+        enable_percpu_irq(evt->irq, 0);
 
         clockevents_register_device(evt);
         return 0;
 }
 
-inline int local_timer_ack(void)
+void local_timer_stop(struct clock_event_device *evt)
 {
-        return 1;
+        evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
+        disable_percpu_irq(evt->irq);
 }
 
 #endif
diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S
index ceb8b7e593d7..feb90a10945a 100644
--- a/arch/arm/mach-omap2/include/mach/entry-macro.S
+++ b/arch/arm/mach-omap2/include/mach/entry-macro.S
@@ -78,7 +78,7 @@
 4401:           ldr     \irqstat, [\base, #GIC_CPU_INTACK]
                 ldr     \tmp, =1021
                 bic     \irqnr, \irqstat, #0x1c00
-                cmp     \irqnr, #29
+                cmp     \irqnr, #15
                 cmpcc   \irqnr, \irqnr
                 cmpne   \irqnr, \tmp
                 cmpcs   \irqnr, \irqnr
@@ -101,18 +101,6 @@
                 it      cs
                 cmpcs   \irqnr, \irqnr
                 .endm
-
-                /* As above, this assumes that irqstat and base are preserved */
-
-                .macro test_for_ltirq, irqnr, irqstat, base, tmp
-                bic     \irqnr, \irqstat, #0x1c00
-                mov     \tmp, #0
-                cmp     \irqnr, #29
-                itt     eq
-                moveq   \tmp, #1
-                streq   \irqstat, [\base, #GIC_CPU_EOI]
-                cmp     \tmp, #0
-                .endm
 #endif  /* CONFIG_SMP */
 
 #else   /* MULTI_OMAP2 */
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index ce65e9329c7b..889464dc7b2d 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -109,12 +109,10 @@ void __init smp_init_cpus(void)
         ncores = scu_get_core_count(scu_base);
 
         /* sanity check */
-        if (ncores > NR_CPUS) {
-                printk(KERN_WARNING
-                       "OMAP4: no. of cores (%d) greater than configured "
-                       "maximum of %d - clipping\n",
-                       ncores, NR_CPUS);
-                ncores = NR_CPUS;
+        if (ncores > nr_cpu_ids) {
+                pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
+                        ncores, nr_cpu_ids);
+                ncores = nr_cpu_ids;
         }
 
         for (i = 0; i < ncores; i++)
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c
index b09e848eb6c6..ca6075717824 100644
--- a/arch/arm/mach-pxa/irq.c
+++ b/arch/arm/mach-pxa/irq.c
@@ -19,6 +19,8 @@
 #include <linux/io.h>
 #include <linux/irq.h>
 
+#include <asm/exception.h>
+
 #include <mach/hardware.h>
 #include <mach/irqs.h>
 #include <mach/gpio.h>
diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c
index 4ae943bafa92..e83c654a58d0 100644
--- a/arch/arm/mach-realview/platsmp.c
+++ b/arch/arm/mach-realview/platsmp.c
@@ -52,12 +52,10 @@ void __init smp_init_cpus(void)
         ncores = scu_base ? scu_get_core_count(scu_base) : 1;
 
         /* sanity check */
-        if (ncores > NR_CPUS) {
-                printk(KERN_WARNING
-                       "Realview: no. of cores (%d) greater than configured "
-                       "maximum of %d - clipping\n",
-                       ncores, NR_CPUS);
-                ncores = NR_CPUS;
+        if (ncores > nr_cpu_ids) {
+                pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
+                        ncores, nr_cpu_ids);
+                ncores = nr_cpu_ids;
         }
 
         for (i = 0; i < ncores; i++)
diff --git a/arch/arm/mach-shmobile/entry-intc.S b/arch/arm/mach-shmobile/entry-intc.S
index cac0a7ae2084..1a1c00ca39a2 100644
--- a/arch/arm/mach-shmobile/entry-intc.S
+++ b/arch/arm/mach-shmobile/entry-intc.S
@@ -51,7 +51,4 @@
         .macro  test_for_ipi, irqnr, irqstat, base, tmp
         .endm
 
-        .macro  test_for_ltirq, irqnr, irqstat, base, tmp
-        .endm
-
         arch_irq_handler shmobile_handle_irq_intc
diff --git a/arch/arm/mach-shmobile/include/mach/entry-macro.S b/arch/arm/mach-shmobile/include/mach/entry-macro.S
index d791f10eeac7..8d4a416d4285 100644
--- a/arch/arm/mach-shmobile/include/mach/entry-macro.S
+++ b/arch/arm/mach-shmobile/include/mach/entry-macro.S
@@ -27,8 +27,5 @@
         .macro  test_for_ipi, irqnr, irqstat, base, tmp
         .endm
 
-        .macro  test_for_ltirq, irqnr, irqstat, base, tmp
-        .endm
-
         .macro  arch_ret_to_user, tmp1, tmp2
         .endm
diff --git a/arch/arm/mach-shmobile/platsmp.c b/arch/arm/mach-shmobile/platsmp.c
index 66f980625a33..e4e485fa2532 100644
--- a/arch/arm/mach-shmobile/platsmp.c
+++ b/arch/arm/mach-shmobile/platsmp.c
@@ -56,6 +56,12 @@ void __init smp_init_cpus(void)
         unsigned int ncores = shmobile_smp_get_core_count();
         unsigned int i;
 
+        if (ncores > nr_cpu_ids) {
+                pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
+                        ncores, nr_cpu_ids);
+                ncores = nr_cpu_ids;
+        }
+
         for (i = 0; i < ncores; i++)
                 set_cpu_possible(i, true);
 
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index 0886cbccddee..7d2b5d03c1df 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -114,10 +114,10 @@ void __init smp_init_cpus(void)
 {
         unsigned int i, ncores = scu_get_core_count(scu_base);
 
-        if (ncores > NR_CPUS) {
-                printk(KERN_ERR "Tegra: no. of cores (%u) greater than configured (%u), clipping\n",
-                        ncores, NR_CPUS);
-                ncores = NR_CPUS;
+        if (ncores > nr_cpu_ids) {
+                pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
+                        ncores, nr_cpu_ids);
+                ncores = nr_cpu_ids;
         }
 
         for (i = 0; i < ncores; i++)
diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c
index a33df5f4c27a..eb5199102cfa 100644
--- a/arch/arm/mach-ux500/platsmp.c
+++ b/arch/arm/mach-ux500/platsmp.c
@@ -156,12 +156,10 @@ void __init smp_init_cpus(void)
         ncores = scu_base ? scu_get_core_count(scu_base) : 1;
 
         /* sanity check */
-        if (ncores > NR_CPUS) {
-                printk(KERN_WARNING
-                       "U8500: no. of cores (%d) greater than configured "
-                       "maximum of %d - clipping\n",
-                       ncores, NR_CPUS);
-                ncores = NR_CPUS;
+        if (ncores > nr_cpu_ids) {
+                pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
+                        ncores, nr_cpu_ids);
+                ncores = nr_cpu_ids;
         }
 
         for (i = 0; i < ncores; i++)
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c
index bfd32f52c2db..2b1e836a76ed 100644
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@ -221,6 +221,12 @@ static void ct_ca9x4_init_cpu_map(void)
 {
         int i, ncores = scu_get_core_count(MMIO_P2V(A9_MPCORE_SCU));
 
+        if (ncores > nr_cpu_ids) {
+                pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
+                        ncores, nr_cpu_ids);
+                ncores = nr_cpu_ids;
+        }
+
         for (i = 0; i < ncores; ++i)
                 set_cpu_possible(i, true);
 
diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
index 3b5ea68acbb8..aa33949fef60 100644
--- a/arch/arm/mm/fault.c
+++ b/arch/arm/mm/fault.c
@@ -20,6 +20,7 @@
 #include <linux/highmem.h>
 #include <linux/perf_event.h>
 
+#include <asm/exception.h>
 #include <asm/system.h>
 #include <asm/pgtable.h>
 #include <asm/tlbflush.h>