Merge branch 'tegra/cleanup' into next/cleanup

43 files changed, 274 insertions, 131 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 2ad79b288b69..9277237810e9 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1285,6 +1285,20 @@ config ARM_ERRATA_364296
           processor into full low interrupt latency mode. ARM11MPCore
           is not affected.
 
+config ARM_ERRATA_764369
+        bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
+        depends on CPU_V7 && SMP
+        help
+          This option enables the workaround for erratum 764369
+          affecting Cortex-A9 MPCore with two or more processors (all
+          current revisions). Under certain timing circumstances, a data
+          cache line maintenance operation by MVA targeting an Inner
+          Shareable memory region may fail to proceed up to either the
+          Point of Coherency or to the Point of Unification of the
+          system. This workaround adds a DSB instruction before the
+          relevant cache maintenance functions and sets a specific bit
+          in the diagnostic control register of the SCU.
+
 endmenu
 
 source "arch/arm/common/Kconfig"
diff --git a/arch/arm/include/asm/futex.h b/arch/arm/include/asm/futex.h
index 8c73900da9ed..253cc86318bf 100644
--- a/arch/arm/include/asm/futex.h
+++ b/arch/arm/include/asm/futex.h
@@ -25,17 +25,17 @@
 
 #ifdef CONFIG_SMP
 
-#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg)      \
+#define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \
         smp_mb();                                               \
         __asm__ __volatile__(                                   \
-        "1:     ldrex   %1, [%2]\n"                             \
+        "1:     ldrex   %1, [%3]\n"                             \
         "       " insn "\n"                                     \
-        "2:     strex   %1, %0, [%2]\n"                         \
-        "       teq     %1, #0\n"                               \
+        "2:     strex   %2, %0, [%3]\n"                         \
+        "       teq     %2, #0\n"                               \
         "       bne     1b\n"                                   \
         "       mov     %0, #0\n"                               \
-        __futex_atomic_ex_table("%4")                           \
-        : "=&r" (ret), "=&r" (oldval)                           \
+        __futex_atomic_ex_table("%5")                           \
+        : "=&r" (ret), "=&r" (oldval), "=&r" (tmp)              \
         : "r" (uaddr), "r" (oparg), "Ir" (-EFAULT)              \
         : "cc", "memory")
 
@@ -73,14 +73,14 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
 #include <linux/preempt.h>
 #include <asm/domain.h>
 
-#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg)      \
+#define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \
         __asm__ __volatile__(                                   \
-        "1:     " T(ldr) "      %1, [%2]\n"                     \
+        "1:     " T(ldr) "      %1, [%3]\n"                     \
         "       " insn "\n"                                     \
-        "2:     " T(str) "      %0, [%2]\n"                     \
+        "2:     " T(str) "      %0, [%3]\n"                     \
         "       mov     %0, #0\n"                               \
-        __futex_atomic_ex_table("%4")                           \
-        : "=&r" (ret), "=&r" (oldval)                           \
+        __futex_atomic_ex_table("%5")                           \
+        : "=&r" (ret), "=&r" (oldval), "=&r" (tmp)              \
         : "r" (uaddr), "r" (oparg), "Ir" (-EFAULT)              \
         : "cc", "memory")
 
@@ -117,7 +117,7 @@ futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr)
         int cmp = (encoded_op >> 24) & 15;
         int oparg = (encoded_op << 8) >> 20;
         int cmparg = (encoded_op << 20) >> 20;
-        int oldval = 0, ret;
+        int oldval = 0, ret, tmp;
 
         if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
                 oparg = 1 << oparg;
@@ -129,19 +129,19 @@ futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr)
 
         switch (op) {
         case FUTEX_OP_SET:
-                __futex_atomic_op("mov  %0, %3", ret, oldval, uaddr, oparg);
+                __futex_atomic_op("mov  %0, %4", ret, oldval, tmp, uaddr, oparg);
                 break;
         case FUTEX_OP_ADD:
-                __futex_atomic_op("add  %0, %1, %3", ret, oldval, uaddr, oparg);
+                __futex_atomic_op("add  %0, %1, %4", ret, oldval, tmp, uaddr, oparg);
                 break;
         case FUTEX_OP_OR:
-                __futex_atomic_op("orr  %0, %1, %3", ret, oldval, uaddr, oparg);
+                __futex_atomic_op("orr  %0, %1, %4", ret, oldval, tmp, uaddr, oparg);
                 break;
         case FUTEX_OP_ANDN:
-                __futex_atomic_op("and  %0, %1, %3", ret, oldval, uaddr, ~oparg);
+                __futex_atomic_op("and  %0, %1, %4", ret, oldval, tmp, uaddr, ~oparg);
                 break;
         case FUTEX_OP_XOR:
-                __futex_atomic_op("eor  %0, %1, %3", ret, oldval, uaddr, oparg);
+                __futex_atomic_op("eor  %0, %1, %4", ret, oldval, tmp, uaddr, oparg);
                 break;
         default:
                 ret = -ENOSYS;
diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h
index 2c04ed5efeb5..c60a2944f95b 100644
--- a/arch/arm/include/asm/unistd.h
+++ b/arch/arm/include/asm/unistd.h
@@ -478,8 +478,8 @@
 /*
  * Unimplemented (or alternatively implemented) syscalls
  */
-#define __IGNORE_fadvise64_64           1
-#define __IGNORE_migrate_pages          1
+#define __IGNORE_fadvise64_64
+#define __IGNORE_migrate_pages
 
 #endif /* __KERNEL__ */
 #endif /* __ASM_ARM_UNISTD_H */
diff --git a/arch/arm/kernel/smp_scu.c b/arch/arm/kernel/smp_scu.c
index 79ed5e7f204a..7fcddb75c877 100644
--- a/arch/arm/kernel/smp_scu.c
+++ b/arch/arm/kernel/smp_scu.c
@@ -13,6 +13,7 @@
 
 #include <asm/smp_scu.h>
 #include <asm/cacheflush.h>
+#include <asm/cputype.h>
 
 #define SCU_CTRL                0x00
 #define SCU_CONFIG              0x04
@@ -37,6 +38,15 @@ void __init scu_enable(void __iomem *scu_base)
 {
         u32 scu_ctrl;
 
+#ifdef CONFIG_ARM_ERRATA_764369
+        /* Cortex-A9 only */
+        if ((read_cpuid(CPUID_ID) & 0xff0ffff0) == 0x410fc090) {
+                scu_ctrl = __raw_readl(scu_base + 0x30);
+                if (!(scu_ctrl & 1))
+                        __raw_writel(scu_ctrl | 0x1, scu_base + 0x30);
+        }
+#endif
+
         scu_ctrl = __raw_readl(scu_base + SCU_CTRL);
         /* already enabled? */
         if (scu_ctrl & 1)
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index bf977f8514f6..4e66f62b8d41 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -23,8 +23,10 @@
 
 #if defined(CONFIG_SMP_ON_UP) && !defined(CONFIG_DEBUG_SPINLOCK)
 #define ARM_EXIT_KEEP(x)        x
+#define ARM_EXIT_DISCARD(x)
 #else
 #define ARM_EXIT_KEEP(x)
+#define ARM_EXIT_DISCARD(x)     x
 #endif
 
 OUTPUT_ARCH(arm)
@@ -39,6 +41,11 @@ jiffies = jiffies_64 + 4;
 SECTIONS
 {
         /*
+         * XXX: The linker does not define how output sections are
+         * assigned to input sections when there are multiple statements
+         * matching the same input section name.  There is no documented
+         * order of matching.
+         *
          * unwind exit sections must be discarded before the rest of the
          * unwind sections get included.
          */
@@ -47,6 +54,9 @@ SECTIONS
                 *(.ARM.extab.exit.text)
                 ARM_CPU_DISCARD(*(.ARM.exidx.cpuexit.text))
                 ARM_CPU_DISCARD(*(.ARM.extab.cpuexit.text))
+                ARM_EXIT_DISCARD(EXIT_TEXT)
+                ARM_EXIT_DISCARD(EXIT_DATA)
+                EXIT_CALL
 #ifndef CONFIG_HOTPLUG
                 *(.ARM.exidx.devexit.text)
                 *(.ARM.extab.devexit.text)
@@ -58,6 +68,8 @@ SECTIONS
 #ifndef CONFIG_SMP_ON_UP
                 *(.alt.smp.init)
 #endif
+                *(.discard)
+                *(.discard.*)
         }
 
 #ifdef CONFIG_XIP_KERNEL
@@ -279,9 +291,6 @@ SECTIONS
 
         STABS_DEBUG
         .comment 0 : { *(.comment) }
-
-        /* Default discards */
-        DISCARDS
 }
 
 /*
diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c
index 79d6cd0c8e7b..86964d2e9e1b 100644
--- a/arch/arm/mach-exynos4/clock.c
+++ b/arch/arm/mach-exynos4/clock.c
@@ -899,8 +899,7 @@ static struct clksrc_clk clksrcs[] = {
                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 },
         }, {
                 .clk            = {
-                        .name           = "sclk_cam",
-                        .devname        = "exynos4-fimc.0",
+                        .name           = "sclk_cam0",
                         .enable         = exynos4_clksrc_mask_cam_ctrl,
                         .ctrlbit        = (1 << 16),
                 },
@@ -909,8 +908,7 @@ static struct clksrc_clk clksrcs[] = {
                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
         }, {
                 .clk            = {
-                        .name           = "sclk_cam",
-                        .devname        = "exynos4-fimc.1",
+                        .name           = "sclk_cam1",
                         .enable         = exynos4_clksrc_mask_cam_ctrl,
                         .ctrlbit        = (1 << 20),
                 },
diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c
index a1a7176675b9..38058af48972 100644
--- a/arch/arm/mach-s3c2443/clock.c
+++ b/arch/arm/mach-s3c2443/clock.c
@@ -128,7 +128,7 @@ static int s3c2443_armclk_setrate(struct clk *clk, unsigned long rate)
                 unsigned long clkcon0;
 
                 clkcon0 = __raw_readl(S3C2443_CLKDIV0);
-                clkcon0 &= S3C2443_CLKDIV0_ARMDIV_MASK;
+                clkcon0 &= ~S3C2443_CLKDIV0_ARMDIV_MASK;
                 clkcon0 |= val << S3C2443_CLKDIV0_ARMDIV_SHIFT;
                 __raw_writel(clkcon0, S3C2443_CLKDIV0);
         }
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index 52a8e607bcc2..f5f8fa89679c 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -815,8 +815,7 @@ static struct clksrc_clk clksrcs[] = {
                 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 },
         }, {
                 .clk            = {
-                        .name           = "sclk_cam",
-                        .devname        = "s5pv210-fimc.0",
+                        .name           = "sclk_cam0",
                         .enable         = s5pv210_clk_mask0_ctrl,
                         .ctrlbit        = (1 << 3),
                 },
@@ -825,8 +824,7 @@ static struct clksrc_clk clksrcs[] = {
                 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 },
         }, {
                 .clk            = {
-                        .name           = "sclk_cam",
-                        .devname        = "s5pv210-fimc.1",
+                        .name           = "sclk_cam1",
                         .enable         = s5pv210_clk_mask0_ctrl,
                         .ctrlbit        = (1 << 4),
                 },
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index d5e3f89b05af..690b888be506 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -61,7 +61,7 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
         { NULL,         NULL,           0,              0},
 };
 
-void __init tegra_init_cache(void)
+static void __init tegra_init_cache(void)
 {
 #ifdef CONFIG_CACHE_L2X0
         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
diff --git a/arch/arm/mach-tegra/cpu-tegra.c b/arch/arm/mach-tegra/cpu-tegra.c
index 0e1016a827ac..b2647ec709d4 100644
--- a/arch/arm/mach-tegra/cpu-tegra.c
+++ b/arch/arm/mach-tegra/cpu-tegra.c
@@ -57,12 +57,12 @@ static unsigned long target_cpu_speed[NUM_CPUS];
 static DEFINE_MUTEX(tegra_cpu_lock);
 static bool is_suspended;
 
-int tegra_verify_speed(struct cpufreq_policy *policy)
+static int tegra_verify_speed(struct cpufreq_policy *policy)
 {
         return cpufreq_frequency_table_verify(policy, freq_table);
 }
 
-unsigned int tegra_getspeed(unsigned int cpu)
+static unsigned int tegra_getspeed(unsigned int cpu)
 {
         unsigned long rate;
 
@@ -130,7 +130,7 @@ static int tegra_target(struct cpufreq_policy *policy,
                        unsigned int target_freq,
                        unsigned int relation)
 {
-        int idx;
+        unsigned int idx;
         unsigned int freq;
         int ret = 0;
 
diff --git a/arch/arm/mach-tegra/devices.c b/arch/arm/mach-tegra/devices.c
index 57e35d20c24c..489e82b5282a 100644
--- a/arch/arm/mach-tegra/devices.c
+++ b/arch/arm/mach-tegra/devices.c
@@ -29,7 +29,9 @@
 #include <mach/iomap.h>
 #include <mach/dma.h>
 #include <mach/usb_phy.h>
+
 #include "gpio-names.h"
+#include "devices.h"
 
 static struct resource i2c_resource1[] = {
         [0] = {
diff --git a/arch/arm/mach-tegra/dma.c b/arch/arm/mach-tegra/dma.c
index f4ef5eb317bd..c0cf967e47d3 100644
--- a/arch/arm/mach-tegra/dma.c
+++ b/arch/arm/mach-tegra/dma.c
@@ -105,13 +105,17 @@
 
 #define NV_DMA_MAX_TRASFER_SIZE 0x10000
 
-const unsigned int ahb_addr_wrap_table[8] = {
+static const unsigned int ahb_addr_wrap_table[8] = {
         0, 32, 64, 128, 256, 512, 1024, 2048
 };
 
-const unsigned int apb_addr_wrap_table[8] = {0, 1, 2, 4, 8, 16, 32, 64};
+static const unsigned int apb_addr_wrap_table[8] = {
+        0, 1, 2, 4, 8, 16, 32, 64
+};
 
-const unsigned int bus_width_table[5] = {8, 16, 32, 64, 128};
+static const unsigned int bus_width_table[5] = {
+        8, 16, 32, 64, 128
+};
 
 #define TEGRA_DMA_NAME_SIZE 16
 struct tegra_dma_channel {
@@ -157,7 +161,7 @@ void tegra_dma_dequeue(struct tegra_dma_channel *ch)
         return;
 }
 
-void tegra_dma_stop(struct tegra_dma_channel *ch)
+static void tegra_dma_stop(struct tegra_dma_channel *ch)
 {
         u32 csr;
         u32 status;
@@ -174,7 +178,7 @@ void tegra_dma_stop(struct tegra_dma_channel *ch)
                 writel(status, ch->addr + APB_DMA_CHAN_STA);
 }
 
-int tegra_dma_cancel(struct tegra_dma_channel *ch)
+static int tegra_dma_cancel(struct tegra_dma_channel *ch)
 {
         u32 csr;
         unsigned long irq_flags;
diff --git a/arch/arm/mach-tegra/include/mach/io.h b/arch/arm/mach-tegra/include/mach/io.h
index 4cea2230c8dc..35a011fbc42d 100644
--- a/arch/arm/mach-tegra/include/mach/io.h
+++ b/arch/arm/mach-tegra/include/mach/io.h
@@ -33,20 +33,26 @@
  *
  */
 
+#ifdef __ASSEMBLY__
+#define IOMEM(x)        (x)
+#else
+#define IOMEM(x)        ((void __force __iomem *)(x))
+#endif
+
 #define IO_IRAM_PHYS    0x40000000
-#define IO_IRAM_VIRT    0xFE400000
+#define IO_IRAM_VIRT    IOMEM(0xFE400000)
 #define IO_IRAM_SIZE    SZ_256K
 
 #define IO_CPU_PHYS     0x50040000
-#define IO_CPU_VIRT     0xFE000000
+#define IO_CPU_VIRT     IOMEM(0xFE000000)
 #define IO_CPU_SIZE     SZ_16K
 
 #define IO_PPSB_PHYS    0x60000000
-#define IO_PPSB_VIRT    0xFE200000
+#define IO_PPSB_VIRT    IOMEM(0xFE200000)
 #define IO_PPSB_SIZE    SZ_1M
 
 #define IO_APB_PHYS     0x70000000
-#define IO_APB_VIRT     0xFE300000
+#define IO_APB_VIRT     IOMEM(0xFE300000)
 #define IO_APB_SIZE     SZ_1M
 
 #define IO_TO_VIRT_BETWEEN(p, st, sz)   ((p) >= (st) && (p) < ((st) + (sz)))
@@ -61,7 +67,7 @@
                 IO_TO_VIRT_XLATE((n), IO_CPU_PHYS, IO_CPU_VIRT) :       \
         IO_TO_VIRT_BETWEEN((n), IO_IRAM_PHYS, IO_IRAM_SIZE) ?           \
                 IO_TO_VIRT_XLATE((n), IO_IRAM_PHYS, IO_IRAM_VIRT) :     \
-        0)
+        NULL)
 
 #ifndef __ASSEMBLER__
 
@@ -71,7 +77,7 @@
 void __iomem *tegra_ioremap(unsigned long phys, size_t size, unsigned int type);
 void tegra_iounmap(volatile void __iomem *addr);
 
-#define IO_ADDRESS(n) ((void __iomem *) IO_TO_VIRT(n))
+#define IO_ADDRESS(n) (IO_TO_VIRT(n))
 
 #ifdef CONFIG_TEGRA_PCI
 extern void __iomem *tegra_pcie_io_base;
diff --git a/arch/arm/mach-tegra/include/mach/powergate.h b/arch/arm/mach-tegra/include/mach/powergate.h
index 401d1b725291..39c396d2ddb0 100644
--- a/arch/arm/mach-tegra/include/mach/powergate.h
+++ b/arch/arm/mach-tegra/include/mach/powergate.h
@@ -31,7 +31,6 @@
 
 int tegra_powergate_power_on(int id);
 int tegra_powergate_power_off(int id);
-bool tegra_powergate_is_powered(int id);
 int tegra_powergate_remove_clamping(int id);
 
 /* Must be called with clk disabled, and returns with clk enabled */
diff --git a/arch/arm/mach-tegra/io.c b/arch/arm/mach-tegra/io.c
index ea50fe28cf6a..5489f8b5d6ad 100644
--- a/arch/arm/mach-tegra/io.c
+++ b/arch/arm/mach-tegra/io.c
@@ -31,25 +31,25 @@
 
 static struct map_desc tegra_io_desc[] __initdata = {
         {
-                .virtual = IO_PPSB_VIRT,
+                .virtual = (unsigned long)IO_PPSB_VIRT,
                 .pfn = __phys_to_pfn(IO_PPSB_PHYS),
                 .length = IO_PPSB_SIZE,
                 .type = MT_DEVICE,
         },
         {
-                .virtual = IO_APB_VIRT,
+                .virtual = (unsigned long)IO_APB_VIRT,
                 .pfn = __phys_to_pfn(IO_APB_PHYS),
                 .length = IO_APB_SIZE,
                 .type = MT_DEVICE,
         },
         {
-                .virtual = IO_CPU_VIRT,
+                .virtual = (unsigned long)IO_CPU_VIRT,
                 .pfn = __phys_to_pfn(IO_CPU_PHYS),
                 .length = IO_CPU_SIZE,
                 .type = MT_DEVICE,
         },
         {
-                .virtual = IO_IRAM_VIRT,
+                .virtual = (unsigned long)IO_IRAM_VIRT,
                 .pfn = __phys_to_pfn(IO_IRAM_PHYS),
                 .length = IO_IRAM_SIZE,
                 .type = MT_DEVICE,
diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index f1f699d86c32..f5aa173c26b3 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -41,6 +41,8 @@
 #include <mach/clk.h>
 #include <mach/powergate.h>
 
+#include "board.h"
+
 /* register definitions */
 #define AFI_OFFSET      0x3800
 #define PADS_OFFSET     0x3000
@@ -150,9 +152,9 @@
 static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
 
 #define pmc_writel(value, reg) \
-        __raw_writel(value, (u32)reg_pmc_base + (reg))
+        __raw_writel(value, reg_pmc_base + (reg))
 #define pmc_readl(reg) \
-        __raw_readl((u32)reg_pmc_base + (reg))
+        __raw_readl(reg_pmc_base + (reg))
 
 /*
  * Tegra2 defines 1GB in the AXI address map for PCIe.
@@ -460,7 +462,7 @@ static struct pci_bus __init *tegra_pcie_scan_bus(int nr,
         struct tegra_pcie_port *pp;
 
         if (nr >= tegra_pcie.num_ports)
-                return 0;
+                return NULL;
 
         pp = tegra_pcie.port + nr;
         pp->root_bus_nr = sys->busnr;
diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c
index 3cee9aa1f2c8..948306491a59 100644
--- a/arch/arm/mach-tegra/powergate.c
+++ b/arch/arm/mach-tegra/powergate.c
@@ -89,12 +89,11 @@ int tegra_powergate_power_off(int id)
         return tegra_powergate_set(id, false);
 }
 
-bool tegra_powergate_is_powered(int id)
+static bool tegra_powergate_is_powered(int id)
 {
         u32 status;
 
-        if (id < 0 || id >= TEGRA_NUM_POWERGATE)
-                return -EINVAL;
+        WARN_ON(id < 0 || id >= TEGRA_NUM_POWERGATE);
 
         status = pmc_read(PWRGATE_STATUS) & (1 << id);
         return !!status;
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
index 0fe9b3ee2947..371869d8ea01 100644
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -166,13 +166,13 @@ static DEFINE_SPINLOCK(clock_register_lock);
 static int tegra_periph_clk_enable_refcount[3 * 32];
 
 #define clk_writel(value, reg) \
-        __raw_writel(value, (u32)reg_clk_base + (reg))
+        __raw_writel(value, reg_clk_base + (reg))
 #define clk_readl(reg) \
-        __raw_readl((u32)reg_clk_base + (reg))
+        __raw_readl(reg_clk_base + (reg))
 #define pmc_writel(value, reg) \
-        __raw_writel(value, (u32)reg_pmc_base + (reg))
+        __raw_writel(value, reg_pmc_base + (reg))
 #define pmc_readl(reg) \
-        __raw_readl((u32)reg_pmc_base + (reg))
+        __raw_readl(reg_pmc_base + (reg))
 
 unsigned long clk_measure_input_freq(void)
 {
@@ -918,7 +918,7 @@ static struct clk_ops tegra_pll_div_ops = {
 static void tegra2_periph_clk_init(struct clk *c)
 {
         u32 val = clk_readl(c->reg);
-        const struct clk_mux_sel *mux = 0;
+        const struct clk_mux_sel *mux = NULL;
         const struct clk_mux_sel *sel;
         if (c->flags & MUX) {
                 for (sel = c->inputs; sel->input != NULL; sel++) {
@@ -1459,7 +1459,7 @@ static struct clk tegra_pll_s = {
 static struct clk_mux_sel tegra_clk_m_sel[] = {
         { .input = &tegra_clk_32k, .value = 0},
         { .input = &tegra_pll_s,  .value = 1},
-        { 0, 0},
+        { NULL , 0},
 };
 
 static struct clk tegra_clk_m = {
@@ -1861,7 +1861,7 @@ static const struct audio_sources {
         { .name = "ext_audio_clk1", .value = 6 },
         { .name = "ext_vimclk", .value = 7 },
 #endif
-        { 0, 0 }
+        { NULL, 0 }
 };
 
 static struct clk tegra_clk_audio = {
@@ -1885,7 +1885,7 @@ static struct clk tegra_clk_audio_2x = {
         },
 };
 
-struct clk_lookup tegra_audio_clk_lookups[] = {
+static struct clk_lookup tegra_audio_clk_lookups[] = {
         { .con_id = "audio", .clk = &tegra_clk_audio },
         { .con_id = "audio_2x", .clk = &tegra_clk_audio_2x }
 };
@@ -1926,7 +1926,7 @@ static struct clk_mux_sel mux_cclk[] = {
         { .input = &tegra_pll_p_out3,   .value = 6},
         { .input = &tegra_clk_d,        .value = 7},
         { .input = &tegra_pll_x,        .value = 8},
-        { 0, 0},
+        { NULL, 0},
 };
 
 static struct clk_mux_sel mux_sclk[] = {
@@ -1938,7 +1938,7 @@ static struct clk_mux_sel mux_sclk[] = {
         { .input = &tegra_clk_d,        .value = 5},
         { .input = &tegra_clk_32k,      .value = 6},
         { .input = &tegra_pll_m_out1,   .value = 7},
-        { 0, 0},
+        { NULL, 0},
 };
 
 static struct clk tegra_clk_cclk = {
@@ -2009,7 +2009,7 @@ static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = {
         { .input = &tegra_pll_c, .value = 1},
         { .input = &tegra_pll_p, .value = 2},
         { .input = &tegra_pll_a_out0, .value = 3},
-        { 0, 0},
+        { NULL, 0},
 };
 
 static struct clk_mux_sel mux_pllm_pllc_pllp_clkm[] = {
@@ -2017,7 +2017,7 @@ static struct clk_mux_sel mux_pllm_pllc_pllp_clkm[] = {
         { .input = &tegra_pll_c, .value = 1},
         { .input = &tegra_pll_p, .value = 2},
         { .input = &tegra_clk_m, .value = 3},
-        { 0, 0},
+        { NULL, 0},
 };
 
 static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
@@ -2025,7 +2025,7 @@ static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
         { .input = &tegra_pll_c, .value = 1},
         { .input = &tegra_pll_m, .value = 2},
         { .input = &tegra_clk_m, .value = 3},
-        { 0, 0},
+        { NULL, 0},
 };
 
 static struct clk_mux_sel mux_pllaout0_audio2x_pllp_clkm[] = {
@@ -2033,7 +2033,7 @@ static struct clk_mux_sel mux_pllaout0_audio2x_pllp_clkm[] = {
         {.input = &tegra_clk_audio_2x, .value = 1},
         {.input = &tegra_pll_p, .value = 2},
         {.input = &tegra_clk_m, .value = 3},
-        { 0, 0},
+        { NULL, 0},
 };
 
 static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = {
@@ -2041,7 +2041,7 @@ static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = {
         {.input = &tegra_pll_d_out0, .value = 1},
         {.input = &tegra_pll_c, .value = 2},
         {.input = &tegra_clk_m, .value = 3},
-        { 0, 0},
+        { NULL, 0},
 };
 
 static struct clk_mux_sel mux_pllp_pllc_audio_clkm_clk32[] = {
@@ -2050,39 +2050,39 @@ static struct clk_mux_sel mux_pllp_pllc_audio_clkm_clk32[] = {
         {.input = &tegra_clk_audio,     .value = 2},
         {.input = &tegra_clk_m,     .value = 3},
         {.input = &tegra_clk_32k,   .value = 4},
-        { 0, 0},
+        { NULL, 0},
 };
 
 static struct clk_mux_sel mux_pllp_pllc_pllm[] = {
         {.input = &tegra_pll_p,     .value = 0},
         {.input = &tegra_pll_c,     .value = 1},
         {.input = &tegra_pll_m,     .value = 2},
-        { 0, 0},
+        { NULL, 0},
 };
 
 static struct clk_mux_sel mux_clk_m[] = {
         { .input = &tegra_clk_m, .value = 0},
-        { 0, 0},
+        { NULL, 0},
 };
 
 static struct clk_mux_sel mux_pllp_out3[] = {
         { .input = &tegra_pll_p_out3, .value = 0},
-        { 0, 0},
+        { NULL, 0},
 };
 
 static struct clk_mux_sel mux_plld[] = {
         { .input = &tegra_pll_d, .value = 0},
-        { 0, 0},
+        { NULL, 0},
 };
 
 static struct clk_mux_sel mux_clk_32k[] = {
         { .input = &tegra_clk_32k, .value = 0},
-        { 0, 0},
+        { NULL, 0},
 };
 
 static struct clk_mux_sel mux_pclk[] = {
         { .input = &tegra_clk_pclk, .value = 0},
-        { 0, 0},
+        { NULL, 0},
 };
 
 static struct clk tegra_clk_emc = {
@@ -2125,7 +2125,7 @@ static struct clk tegra_clk_emc = {
                 .parent = _parent,                      \
         }
 
-struct clk tegra_list_clks[] = {
+static struct clk tegra_list_clks[] = {
         PERIPH_CLK("apbdma",    "tegra-dma",            NULL,   34,     0,      108000000, mux_pclk,                    0),
         PERIPH_CLK("rtc",       "rtc-tegra",            NULL,   4,      0,      32768,     mux_clk_32k,                 PERIPH_NO_RESET),
         PERIPH_CLK("timer",     "timer",                NULL,   5,      0,      26000000,  mux_clk_m,                   0),
@@ -2221,7 +2221,7 @@ struct clk tegra_list_clks[] = {
  * configuration.  List those here to register them twice in the clock lookup
  * table under two names.
  */
-struct clk_duplicate tegra_clk_duplicates[] = {
+static struct clk_duplicate tegra_clk_duplicates[] = {
         CLK_DUPLICATE("uarta",  "tegra_uart.0", NULL),
         CLK_DUPLICATE("uartb",  "tegra_uart.1", NULL),
         CLK_DUPLICATE("uartc",  "tegra_uart.2", NULL),
@@ -2252,7 +2252,7 @@ struct clk_duplicate tegra_clk_duplicates[] = {
                 .clk = ck,      \
         }
 
-struct clk *tegra_ptr_clks[] = {
+static struct clk *tegra_ptr_clks[] = {
         &tegra_clk_32k,
         &tegra_pll_s,
         &tegra_clk_m,
diff --git a/arch/arm/mach-tegra/timer.c b/arch/arm/mach-tegra/timer.c
index 90350420c4e9..e2272d263a83 100644
--- a/arch/arm/mach-tegra/timer.c
+++ b/arch/arm/mach-tegra/timer.c
@@ -62,9 +62,9 @@ static struct timespec persistent_ts;
 static u64 persistent_ms, last_persistent_ms;
 
 #define timer_writel(value, reg) \
-        __raw_writel(value, (u32)timer_reg_base + (reg))
+        __raw_writel(value, timer_reg_base + (reg))
 #define timer_readl(reg) \
-        __raw_readl((u32)timer_reg_base + (reg))
+        __raw_readl(timer_reg_base + (reg))
 
 static int tegra_timer_set_next_event(unsigned long cycles,
                                          struct clock_event_device *evt)
@@ -133,7 +133,7 @@ static void notrace tegra_update_sched_clock(void)
  * tegra_rtc driver could be executing to avoid race conditions
  * on the RTC shadow register
  */
-u64 tegra_rtc_read_ms(void)
+static u64 tegra_rtc_read_ms(void)
 {
         u32 ms = readl(rtc_base + RTC_MILLISECONDS);
         u32 s = readl(rtc_base + RTC_SHADOW_SECONDS);
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 3b24bfa3b828..07c4bc8ea0a4 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -174,6 +174,10 @@ ENTRY(v7_coherent_user_range)
         dcache_line_size r2, r3
         sub     r3, r2, #1
         bic     r12, r0, r3
+#ifdef CONFIG_ARM_ERRATA_764369
+        ALT_SMP(W(dsb))
+        ALT_UP(W(nop))
+#endif
 1:
  USER(  mcr     p15, 0, r12, c7, c11, 1 )       @ clean D line to the point of unification
         add     r12, r12, r2
@@ -223,6 +227,10 @@ ENTRY(v7_flush_kern_dcache_area)
         add     r1, r0, r1
         sub     r3, r2, #1
         bic     r0, r0, r3
+#ifdef CONFIG_ARM_ERRATA_764369
+        ALT_SMP(W(dsb))
+        ALT_UP(W(nop))
+#endif
 1:
         mcr     p15, 0, r0, c7, c14, 1          @ clean & invalidate D line / unified line
         add     r0, r0, r2
@@ -247,6 +255,10 @@ v7_dma_inv_range:
         sub     r3, r2, #1
         tst     r0, r3
         bic     r0, r0, r3
+#ifdef CONFIG_ARM_ERRATA_764369
+        ALT_SMP(W(dsb))
+        ALT_UP(W(nop))
+#endif
         mcrne   p15, 0, r0, c7, c14, 1          @ clean & invalidate D / U line
 
         tst     r1, r3
@@ -270,6 +282,10 @@ v7_dma_clean_range:
         dcache_line_size r2, r3
         sub     r3, r2, #1
         bic     r0, r0, r3
+#ifdef CONFIG_ARM_ERRATA_764369
+        ALT_SMP(W(dsb))
+        ALT_UP(W(nop))
+#endif
 1:
         mcr     p15, 0, r0, c7, c10, 1          @ clean D / U line
         add     r0, r0, r2
@@ -288,6 +304,10 @@ ENTRY(v7_dma_flush_range)
         dcache_line_size r2, r3
         sub     r3, r2, #1
         bic     r0, r0, r3
+#ifdef CONFIG_ARM_ERRATA_764369
+        ALT_SMP(W(dsb))
+        ALT_UP(W(nop))
+#endif
 1:
         mcr     p15, 0, r0, c7, c14, 1          @ clean & invalidate D / U line
         add     r0, r0, r2
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 50be842e89fd..01f5987eb1ad 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -347,6 +347,8 @@ __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp,
 
         if (addr)
                 *handle = pfn_to_dma(dev, page_to_pfn(page));
+        else
+                __dma_free_buffer(page, size);
 
         return addr;
 }
diff --git a/arch/arm/plat-s5p/irq-gpioint.c b/arch/arm/plat-s5p/irq-gpioint.c
index f71078ef6bb5..f88216d23991 100644
--- a/arch/arm/plat-s5p/irq-gpioint.c
+++ b/arch/arm/plat-s5p/irq-gpioint.c
@@ -114,17 +114,18 @@ static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip)
 {
         static int used_gpioint_groups = 0;
         int group = chip->group;
-        struct s5p_gpioint_bank *bank = NULL;
+        struct s5p_gpioint_bank *b, *bank = NULL;
         struct irq_chip_generic *gc;
         struct irq_chip_type *ct;
 
         if (used_gpioint_groups >= S5P_GPIOINT_GROUP_COUNT)
                 return -ENOMEM;
 
-        list_for_each_entry(bank, &banks, list) {
-                if (group >= bank->start &&
-                    group < bank->start + bank->nr_groups)
+        list_for_each_entry(b, &banks, list) {
+                if (group >= b->start && group < b->start + b->nr_groups) {
+                        bank = b;
                         break;
+                }
         }
         if (!bank)
                 return -EINVAL;
diff --git a/arch/powerpc/platforms/powermac/pci.c b/arch/powerpc/platforms/powermac/pci.c
index 5cc83851ad06..31a7d3a7ce25 100644
--- a/arch/powerpc/platforms/powermac/pci.c
+++ b/arch/powerpc/platforms/powermac/pci.c
@@ -561,6 +561,20 @@ static struct pci_ops u4_pcie_pci_ops =
         .write = u4_pcie_write_config,
 };
 
+static void __devinit pmac_pci_fixup_u4_of_node(struct pci_dev *dev)
+{
+        /* Apple's device-tree "hides" the root complex virtual P2P bridge
+         * on U4. However, Linux sees it, causing the PCI <-> OF matching
+         * code to fail to properly match devices below it. This works around
+         * it by setting the node of the bridge to point to the PHB node,
+         * which is not entirely correct but fixes the matching code and
+         * doesn't break anything else. It's also the simplest possible fix.
+         */
+        if (dev->dev.of_node == NULL)
+                dev->dev.of_node = pcibios_get_phb_of_node(dev->bus);
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_APPLE, 0x5b, pmac_pci_fixup_u4_of_node);
+
 #endif /* CONFIG_PPC64 */
 
 #ifdef CONFIG_PPC32
diff --git a/arch/s390/include/asm/elf.h b/arch/s390/include/asm/elf.h
index 64b61bf72e93..547f1a6a35d4 100644
--- a/arch/s390/include/asm/elf.h
+++ b/arch/s390/include/asm/elf.h
@@ -188,7 +188,8 @@ extern char elf_platform[];
 #define SET_PERSONALITY(ex)                                     \
 do {                                                            \
         if (personality(current->personality) != PER_LINUX32)   \
-                set_personality(PER_LINUX);                     \
+                set_personality(PER_LINUX |                     \
+                        (current->personality & ~PER_MASK));    \
         if ((ex).e_ident[EI_CLASS] == ELFCLASS32)               \
                 set_thread_flag(TIF_31BIT);                     \
         else                                                    \
diff --git a/arch/s390/include/asm/pgtable.h b/arch/s390/include/asm/pgtable.h
index 519eb5f187ef..c0cb794bb365 100644
--- a/arch/s390/include/asm/pgtable.h
+++ b/arch/s390/include/asm/pgtable.h
@@ -658,12 +658,14 @@ static inline void pgste_set_pte(pte_t *ptep, pgste_t pgste)
  * struct gmap_struct - guest address space
  * @mm: pointer to the parent mm_struct
  * @table: pointer to the page directory
+ * @asce: address space control element for gmap page table
  * @crst_list: list of all crst tables used in the guest address space
  */
 struct gmap {
         struct list_head list;
         struct mm_struct *mm;
         unsigned long *table;
+        unsigned long asce;
         struct list_head crst_list;
 };
 
diff --git a/arch/s390/kernel/asm-offsets.c b/arch/s390/kernel/asm-offsets.c
index 532fd4322156..2b45591e1582 100644
--- a/arch/s390/kernel/asm-offsets.c
+++ b/arch/s390/kernel/asm-offsets.c
@@ -10,6 +10,7 @@
 #include <linux/sched.h>
 #include <asm/vdso.h>
 #include <asm/sigp.h>
+#include <asm/pgtable.h>
 
 /*
  * Make sure that the compiler is new enough. We want a compiler that
@@ -126,6 +127,7 @@ int main(void)
         DEFINE(__LC_KERNEL_STACK, offsetof(struct _lowcore, kernel_stack));
         DEFINE(__LC_ASYNC_STACK, offsetof(struct _lowcore, async_stack));
         DEFINE(__LC_PANIC_STACK, offsetof(struct _lowcore, panic_stack));
+        DEFINE(__LC_USER_ASCE, offsetof(struct _lowcore, user_asce));
         DEFINE(__LC_INT_CLOCK, offsetof(struct _lowcore, int_clock));
         DEFINE(__LC_MCCK_CLOCK, offsetof(struct _lowcore, mcck_clock));
         DEFINE(__LC_MACHINE_FLAGS, offsetof(struct _lowcore, machine_flags));
@@ -151,6 +153,7 @@ int main(void)
         DEFINE(__LC_VDSO_PER_CPU, offsetof(struct _lowcore, vdso_per_cpu_data));
         DEFINE(__LC_GMAP, offsetof(struct _lowcore, gmap));
         DEFINE(__LC_CMF_HPP, offsetof(struct _lowcore, cmf_hpp));
+        DEFINE(__GMAP_ASCE, offsetof(struct gmap, asce));
 #endif /* CONFIG_32BIT */
         return 0;
 }
diff --git a/arch/s390/kernel/entry64.S b/arch/s390/kernel/entry64.S
index 5f729d627cef..713da0760538 100644
--- a/arch/s390/kernel/entry64.S
+++ b/arch/s390/kernel/entry64.S
@@ -1076,6 +1076,11 @@ sie_loop:
         lg      %r14,__LC_THREAD_INFO           # pointer thread_info struct
         tm      __TI_flags+7(%r14),_TIF_EXIT_SIE
         jnz     sie_exit
+        lg      %r14,__LC_GMAP                  # get gmap pointer
+        ltgr    %r14,%r14
+        jz      sie_gmap
+        lctlg   %c1,%c1,__GMAP_ASCE(%r14)       # load primary asce
+sie_gmap:
         lg      %r14,__SF_EMPTY(%r15)           # get control block pointer
         SPP     __SF_EMPTY(%r15)                # set guest id
         sie     0(%r14)
@@ -1083,6 +1088,7 @@ sie_done:
         SPP     __LC_CMF_HPP                    # set host id
         lg      %r14,__LC_THREAD_INFO           # pointer thread_info struct
 sie_exit:
+        lctlg   %c1,%c1,__LC_USER_ASCE          # load primary asce
         ni      __TI_flags+6(%r14),255-(_TIF_SIE>>8)
         lg      %r14,__SF_EMPTY+8(%r15)         # load guest register save area
         stmg    %r0,%r13,0(%r14)                # save guest gprs 0-13
diff --git a/arch/s390/kvm/kvm-s390.c b/arch/s390/kvm/kvm-s390.c
index f17296e4fc89..dc2b580e27bc 100644
--- a/arch/s390/kvm/kvm-s390.c
+++ b/arch/s390/kvm/kvm-s390.c
@@ -123,6 +123,7 @@ int kvm_dev_ioctl_check_extension(long ext)
 
         switch (ext) {
         case KVM_CAP_S390_PSW:
+        case KVM_CAP_S390_GMAP:
                 r = 1;
                 break;
         default:
@@ -263,10 +264,12 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
         vcpu->arch.guest_fpregs.fpc &= FPC_VALID_MASK;
         restore_fp_regs(&vcpu->arch.guest_fpregs);
         restore_access_regs(vcpu->arch.guest_acrs);
+        gmap_enable(vcpu->arch.gmap);
 }
 
 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
 {
+        gmap_disable(vcpu->arch.gmap);
         save_fp_regs(&vcpu->arch.guest_fpregs);
         save_access_regs(vcpu->arch.guest_acrs);
         restore_fp_regs(&vcpu->arch.host_fpregs);
@@ -461,7 +464,6 @@ static void __vcpu_run(struct kvm_vcpu *vcpu)
         local_irq_disable();
         kvm_guest_enter();
         local_irq_enable();
-        gmap_enable(vcpu->arch.gmap);
         VCPU_EVENT(vcpu, 6, "entering sie flags %x",
                    atomic_read(&vcpu->arch.sie_block->cpuflags));
         if (sie64a(vcpu->arch.sie_block, vcpu->arch.guest_gprs)) {
@@ -470,7 +472,6 @@ static void __vcpu_run(struct kvm_vcpu *vcpu)
         }
         VCPU_EVENT(vcpu, 6, "exit sie icptcode %d",
                    vcpu->arch.sie_block->icptcode);
-        gmap_disable(vcpu->arch.gmap);
         local_irq_disable();
         kvm_guest_exit();
         local_irq_enable();
diff --git a/arch/s390/mm/pgtable.c b/arch/s390/mm/pgtable.c
index 4d1f2bce87b3..5d56c2b95b14 100644
--- a/arch/s390/mm/pgtable.c
+++ b/arch/s390/mm/pgtable.c
@@ -160,6 +160,8 @@ struct gmap *gmap_alloc(struct mm_struct *mm)
         table = (unsigned long *) page_to_phys(page);
         crst_table_init(table, _REGION1_ENTRY_EMPTY);
         gmap->table = table;
+        gmap->asce = _ASCE_TYPE_REGION1 | _ASCE_TABLE_LENGTH |
+                     _ASCE_USER_BITS | __pa(table);
         list_add(&gmap->list, &mm->context.gmap_list);
         return gmap;
 
@@ -240,10 +242,6 @@ EXPORT_SYMBOL_GPL(gmap_free);
  */
 void gmap_enable(struct gmap *gmap)
 {
-        /* Load primary space page table origin. */
-        S390_lowcore.user_asce = _ASCE_TYPE_REGION1 | _ASCE_TABLE_LENGTH |
-                                 _ASCE_USER_BITS | __pa(gmap->table);
-        asm volatile("lctlg 1,1,%0\n" : : "m" (S390_lowcore.user_asce) );
         S390_lowcore.gmap = (unsigned long) gmap;
 }
 EXPORT_SYMBOL_GPL(gmap_enable);
@@ -254,10 +252,6 @@ EXPORT_SYMBOL_GPL(gmap_enable);
  */
 void gmap_disable(struct gmap *gmap)
 {
-        /* Load primary space page table origin. */
-        S390_lowcore.user_asce =
-                gmap->mm->context.asce_bits | __pa(gmap->mm->pgd);
-        asm volatile("lctlg 1,1,%0\n" : : "m" (S390_lowcore.user_asce) );
         S390_lowcore.gmap = 0UL;
 }
 EXPORT_SYMBOL_GPL(gmap_disable);
@@ -309,15 +303,15 @@ int gmap_unmap_segment(struct gmap *gmap, unsigned long to, unsigned long len)
                 /* Walk the guest addr space page table */
                 table = gmap->table + (((to + off) >> 53) & 0x7ff);
                 if (*table & _REGION_ENTRY_INV)
-                        return 0;
+                        goto out;
                 table = (unsigned long *)(*table & _REGION_ENTRY_ORIGIN);
                 table = table + (((to + off) >> 42) & 0x7ff);
                 if (*table & _REGION_ENTRY_INV)
-                        return 0;
+                        goto out;
                 table = (unsigned long *)(*table & _REGION_ENTRY_ORIGIN);
                 table = table + (((to + off) >> 31) & 0x7ff);
                 if (*table & _REGION_ENTRY_INV)
-                        return 0;
+                        goto out;
                 table = (unsigned long *)(*table & _REGION_ENTRY_ORIGIN);
                 table = table + (((to + off) >> 20) & 0x7ff);
 
@@ -325,6 +319,7 @@ int gmap_unmap_segment(struct gmap *gmap, unsigned long to, unsigned long len)
                 flush |= gmap_unlink_segment(gmap, table);
                 *table = _SEGMENT_ENTRY_INV;
         }
+out:
         up_read(&gmap->mm->mmap_sem);
         if (flush)
                 gmap_flush_tlb(gmap);
diff --git a/arch/sparc/include/asm/spitfire.h b/arch/sparc/include/asm/spitfire.h
index 55a17c6efeb8..d06a26601753 100644
--- a/arch/sparc/include/asm/spitfire.h
+++ b/arch/sparc/include/asm/spitfire.h
@@ -43,6 +43,8 @@
 #define SUN4V_CHIP_NIAGARA1     0x01
 #define SUN4V_CHIP_NIAGARA2     0x02
 #define SUN4V_CHIP_NIAGARA3     0x03
+#define SUN4V_CHIP_NIAGARA4     0x04
+#define SUN4V_CHIP_NIAGARA5     0x05
 #define SUN4V_CHIP_UNKNOWN      0xff
 
 #ifndef __ASSEMBLY__
diff --git a/arch/sparc/include/asm/xor_64.h b/arch/sparc/include/asm/xor_64.h
index 9ed6ff679ab7..ee8edc68423e 100644
--- a/arch/sparc/include/asm/xor_64.h
+++ b/arch/sparc/include/asm/xor_64.h
@@ -66,6 +66,8 @@ static struct xor_block_template xor_block_niagara = {
         ((tlb_type == hypervisor && \
           (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 || \
            sun4v_chip_type == SUN4V_CHIP_NIAGARA2 || \
-           sun4v_chip_type == SUN4V_CHIP_NIAGARA3)) ? \
+           sun4v_chip_type == SUN4V_CHIP_NIAGARA3 || \
+           sun4v_chip_type == SUN4V_CHIP_NIAGARA4 || \
+           sun4v_chip_type == SUN4V_CHIP_NIAGARA5)) ? \
          &xor_block_niagara : \
          &xor_block_VIS)
diff --git a/arch/sparc/kernel/cpu.c b/arch/sparc/kernel/cpu.c
index 9810fd881058..ba9b1cec4e6b 100644
--- a/arch/sparc/kernel/cpu.c
+++ b/arch/sparc/kernel/cpu.c
@@ -481,6 +481,18 @@ static void __init sun4v_cpu_probe(void)
                 sparc_pmu_type = "niagara3";
                 break;
 
+        case SUN4V_CHIP_NIAGARA4:
+                sparc_cpu_type = "UltraSparc T4 (Niagara4)";
+                sparc_fpu_type = "UltraSparc T4 integrated FPU";
+                sparc_pmu_type = "niagara4";
+                break;
+
+        case SUN4V_CHIP_NIAGARA5:
+                sparc_cpu_type = "UltraSparc T5 (Niagara5)";
+                sparc_fpu_type = "UltraSparc T5 integrated FPU";
+                sparc_pmu_type = "niagara5";
+                break;
+
         default:
                 printk(KERN_WARNING "CPU: Unknown sun4v cpu type [%s]\n",
                        prom_cpu_compatible);
diff --git a/arch/sparc/kernel/cpumap.c b/arch/sparc/kernel/cpumap.c
index 4197e8d62d4c..9323eafccb93 100644
--- a/arch/sparc/kernel/cpumap.c
+++ b/arch/sparc/kernel/cpumap.c
@@ -325,6 +325,8 @@ static int iterate_cpu(struct cpuinfo_tree *t, unsigned int root_index)
         case SUN4V_CHIP_NIAGARA1:
         case SUN4V_CHIP_NIAGARA2:
         case SUN4V_CHIP_NIAGARA3:
+        case SUN4V_CHIP_NIAGARA4:
+        case SUN4V_CHIP_NIAGARA5:
                 rover_inc_table = niagara_iterate_method;
                 break;
         default:
diff --git a/arch/sparc/kernel/head_64.S b/arch/sparc/kernel/head_64.S
index 0eac1b2fc53d..0d810c2f1d00 100644
--- a/arch/sparc/kernel/head_64.S
+++ b/arch/sparc/kernel/head_64.S
@@ -133,7 +133,7 @@ prom_sun4v_name:
 prom_niagara_prefix:
         .asciz  "SUNW,UltraSPARC-T"
 prom_sparc_prefix:
-        .asciz  "SPARC-T"
+        .asciz  "SPARC-"
         .align  4
 prom_root_compatible:
         .skip   64
@@ -396,7 +396,7 @@ sun4v_chip_type:
         or      %g1, %lo(prom_cpu_compatible), %g1
         sethi   %hi(prom_sparc_prefix), %g7
         or      %g7, %lo(prom_sparc_prefix), %g7
-        mov     7, %g3
+        mov     6, %g3
 90:     ldub    [%g7], %g2
         ldub    [%g1], %g4
         cmp     %g2, %g4
@@ -408,10 +408,23 @@ sun4v_chip_type:
 
         sethi   %hi(prom_cpu_compatible), %g1
         or      %g1, %lo(prom_cpu_compatible), %g1
-        ldub    [%g1 + 7], %g2
+        ldub    [%g1 + 6], %g2
+        cmp     %g2, 'T'
+        be,pt   %xcc, 70f
+         cmp    %g2, 'M'
+        bne,pn  %xcc, 4f
+         nop
+
+70:     ldub    [%g1 + 7], %g2
         cmp     %g2, '3'
         be,pt   %xcc, 5f
          mov    SUN4V_CHIP_NIAGARA3, %g4
+        cmp     %g2, '4'
+        be,pt   %xcc, 5f
+         mov    SUN4V_CHIP_NIAGARA4, %g4
+        cmp     %g2, '5'
+        be,pt   %xcc, 5f
+         mov    SUN4V_CHIP_NIAGARA5, %g4
         ba,pt   %xcc, 4f
          nop
 
@@ -545,6 +558,12 @@ niagara_tlb_fixup:
         cmp     %g1, SUN4V_CHIP_NIAGARA3
         be,pt   %xcc, niagara2_patch
          nop
+        cmp     %g1, SUN4V_CHIP_NIAGARA4
+        be,pt   %xcc, niagara2_patch
+         nop
+        cmp     %g1, SUN4V_CHIP_NIAGARA5
+        be,pt   %xcc, niagara2_patch
+         nop
 
         call    generic_patch_copyops
          nop
diff --git a/arch/sparc/kernel/process_32.c b/arch/sparc/kernel/process_32.c
index c8cc461ff75f..f793742eec2b 100644
--- a/arch/sparc/kernel/process_32.c
+++ b/arch/sparc/kernel/process_32.c
@@ -380,8 +380,7 @@ void flush_thread(void)
 #endif
         }
 
-        /* Now, this task is no longer a kernel thread. */
-        current->thread.current_ds = USER_DS;
+        /* This task is no longer a kernel thread. */
         if (current->thread.flags & SPARC_FLAG_KTHREAD) {
                 current->thread.flags &= ~SPARC_FLAG_KTHREAD;
 
diff --git a/arch/sparc/kernel/process_64.c b/arch/sparc/kernel/process_64.c
index c158a95ec664..d959cd0a4aa4 100644
--- a/arch/sparc/kernel/process_64.c
+++ b/arch/sparc/kernel/process_64.c
@@ -368,9 +368,6 @@ void flush_thread(void)
 
         /* Clear FPU register state. */
         t->fpsaved[0] = 0;
-        
-        if (get_thread_current_ds() != ASI_AIUS)
-                set_fs(USER_DS);
 }
 
 /* It's a bit more tricky when 64-bit tasks are involved... */
diff --git a/arch/sparc/kernel/setup_32.c b/arch/sparc/kernel/setup_32.c
index d26e1f6c717a..3e3e2914c70b 100644
--- a/arch/sparc/kernel/setup_32.c
+++ b/arch/sparc/kernel/setup_32.c
@@ -137,7 +137,7 @@ static void __init process_switch(char c)
                 prom_halt();
                 break;
         case 'p':
-                /* Just ignore, this behavior is now the default.  */
+                prom_early_console.flags &= ~CON_BOOT;
                 break;
         default:
                 printk("Unknown boot switch (-%c)\n", c);
diff --git a/arch/sparc/kernel/setup_64.c b/arch/sparc/kernel/setup_64.c
index 3c5bb784214f..c965595aa7e9 100644
--- a/arch/sparc/kernel/setup_64.c
+++ b/arch/sparc/kernel/setup_64.c
@@ -106,7 +106,7 @@ static void __init process_switch(char c)
                 prom_halt();
                 break;
         case 'p':
-                /* Just ignore, this behavior is now the default.  */
+                prom_early_console.flags &= ~CON_BOOT;
                 break;
         case 'P':
                 /* Force UltraSPARC-III P-Cache on. */
@@ -425,10 +425,14 @@ static void __init init_sparc64_elf_hwcap(void)
         else if (tlb_type == hypervisor) {
                 if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 ||
                     sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
-                    sun4v_chip_type == SUN4V_CHIP_NIAGARA3)
+                    sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
+                    sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
+                    sun4v_chip_type == SUN4V_CHIP_NIAGARA5)
                         cap |= HWCAP_SPARC_BLKINIT;
                 if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
-                    sun4v_chip_type == SUN4V_CHIP_NIAGARA3)
+                    sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
+                    sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
+                    sun4v_chip_type == SUN4V_CHIP_NIAGARA5)
                         cap |= HWCAP_SPARC_N2;
         }
 
@@ -452,11 +456,15 @@ static void __init init_sparc64_elf_hwcap(void)
                         if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1)
                                 cap |= AV_SPARC_ASI_BLK_INIT;
                         if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
-                            sun4v_chip_type == SUN4V_CHIP_NIAGARA3)
+                            sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
+                            sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
+                            sun4v_chip_type == SUN4V_CHIP_NIAGARA5)
                                 cap |= (AV_SPARC_VIS | AV_SPARC_VIS2 |
                                         AV_SPARC_ASI_BLK_INIT |
                                         AV_SPARC_POPC);
-                        if (sun4v_chip_type == SUN4V_CHIP_NIAGARA3)
+                        if (sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
+                            sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
+                            sun4v_chip_type == SUN4V_CHIP_NIAGARA5)
                                 cap |= (AV_SPARC_VIS3 | AV_SPARC_HPC |
                                         AV_SPARC_FMAF);
                 }
diff --git a/arch/sparc/mm/init_64.c b/arch/sparc/mm/init_64.c
index 581531dbc8b5..8e073d802139 100644
--- a/arch/sparc/mm/init_64.c
+++ b/arch/sparc/mm/init_64.c
@@ -511,6 +511,11 @@ static void __init read_obp_translations(void)
                 for (i = 0; i < prom_trans_ents; i++)
                         prom_trans[i].data &= ~0x0003fe0000000000UL;
         }
+
+        /* Force execute bit on.  */
+        for (i = 0; i < prom_trans_ents; i++)
+                prom_trans[i].data |= (tlb_type == hypervisor ?
+                                       _PAGE_EXEC_4V : _PAGE_EXEC_4U);
 }
 
 static void __init hypervisor_tlb_lock(unsigned long vaddr,
diff --git a/arch/x86/kernel/rtc.c b/arch/x86/kernel/rtc.c
index 3f2ad2640d85..ccdbc16b8941 100644
--- a/arch/x86/kernel/rtc.c
+++ b/arch/x86/kernel/rtc.c
@@ -42,8 +42,11 @@ int mach_set_rtc_mmss(unsigned long nowtime)
 {
         int real_seconds, real_minutes, cmos_minutes;
         unsigned char save_control, save_freq_select;
+        unsigned long flags;
         int retval = 0;
 
+        spin_lock_irqsave(&rtc_lock, flags);
+
          /* tell the clock it's being set */
         save_control = CMOS_READ(RTC_CONTROL);
         CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL);
@@ -93,12 +96,17 @@ int mach_set_rtc_mmss(unsigned long nowtime)
         CMOS_WRITE(save_control, RTC_CONTROL);
         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
 
+        spin_unlock_irqrestore(&rtc_lock, flags);
+
         return retval;
 }
 
 unsigned long mach_get_cmos_time(void)
 {
         unsigned int status, year, mon, day, hour, min, sec, century = 0;
+        unsigned long flags;
+
+        spin_lock_irqsave(&rtc_lock, flags);
 
         /*
          * If UIP is clear, then we have >= 244 microseconds before
@@ -125,6 +133,8 @@ unsigned long mach_get_cmos_time(void)
         status = CMOS_READ(RTC_CONTROL);
         WARN_ON_ONCE(RTC_ALWAYS_BCD && (status & RTC_DM_BINARY));
 
+        spin_unlock_irqrestore(&rtc_lock, flags);
+
         if (RTC_ALWAYS_BCD || !(status & RTC_DM_BINARY)) {
                 sec = bcd2bin(sec);
                 min = bcd2bin(min);
@@ -169,24 +179,15 @@ EXPORT_SYMBOL(rtc_cmos_write);
 
 int update_persistent_clock(struct timespec now)
 {
-        unsigned long flags;
-        int retval;
-
-        spin_lock_irqsave(&rtc_lock, flags);
-        retval = x86_platform.set_wallclock(now.tv_sec);
-        spin_unlock_irqrestore(&rtc_lock, flags);
-
-        return retval;
+        return x86_platform.set_wallclock(now.tv_sec);
 }
 
 /* not static: needed by APM */
 void read_persistent_clock(struct timespec *ts)
 {
-        unsigned long retval, flags;
+        unsigned long retval;
 
-        spin_lock_irqsave(&rtc_lock, flags);
         retval = x86_platform.get_wallclock();
-        spin_unlock_irqrestore(&rtc_lock, flags);
 
         ts->tv_sec = retval;
         ts->tv_nsec = 0;
diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c
index 6f08bc940fa8..8b4cc5f067de 100644
--- a/arch/x86/kvm/emulate.c
+++ b/arch/x86/kvm/emulate.c
@@ -3603,7 +3603,7 @@ done_prefixes:
                 break;
         case Src2CL:
                 ctxt->src2.bytes = 1;
-                ctxt->src2.val = ctxt->regs[VCPU_REGS_RCX] & 0x8;
+                ctxt->src2.val = ctxt->regs[VCPU_REGS_RCX] & 0xff;
                 break;
         case Src2ImmByte:
                 rc = decode_imm(ctxt, &ctxt->src2, 1, true);
diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c
index 1c5b69373a00..8e8da7960dbe 100644
--- a/arch/x86/kvm/mmu.c
+++ b/arch/x86/kvm/mmu.c
@@ -400,7 +400,8 @@ static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
 
         /* xchg acts as a barrier before the setting of the high bits */
         orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
-        orig.spte_high = ssptep->spte_high = sspte.spte_high;
+        orig.spte_high = ssptep->spte_high;
+        ssptep->spte_high = sspte.spte_high;
         count_spte_clear(sptep, spte);
 
         return orig.spte;
diff --git a/arch/x86/platform/mrst/vrtc.c b/arch/x86/platform/mrst/vrtc.c
index 73d70d65e76e..6d5dbcdd444a 100644
--- a/arch/x86/platform/mrst/vrtc.c
+++ b/arch/x86/platform/mrst/vrtc.c
@@ -58,8 +58,11 @@ EXPORT_SYMBOL_GPL(vrtc_cmos_write);
 unsigned long vrtc_get_time(void)
 {
         u8 sec, min, hour, mday, mon;
+        unsigned long flags;
         u32 year;
 
+        spin_lock_irqsave(&rtc_lock, flags);
+
         while ((vrtc_cmos_read(RTC_FREQ_SELECT) & RTC_UIP))
                 cpu_relax();
 
@@ -70,6 +73,8 @@ unsigned long vrtc_get_time(void)
         mon = vrtc_cmos_read(RTC_MONTH);
         year = vrtc_cmos_read(RTC_YEAR);
 
+        spin_unlock_irqrestore(&rtc_lock, flags);
+
         /* vRTC YEAR reg contains the offset to 1960 */
         year += 1960;
 
@@ -83,8 +88,10 @@ unsigned long vrtc_get_time(void)
 int vrtc_set_mmss(unsigned long nowtime)
 {
         int real_sec, real_min;
+        unsigned long flags;
         int vrtc_min;
 
+        spin_lock_irqsave(&rtc_lock, flags);
         vrtc_min = vrtc_cmos_read(RTC_MINUTES);
 
         real_sec = nowtime % 60;
@@ -95,6 +102,8 @@ int vrtc_set_mmss(unsigned long nowtime)
 
         vrtc_cmos_write(real_sec, RTC_SECONDS);
         vrtc_cmos_write(real_min, RTC_MINUTES);
+        spin_unlock_irqrestore(&rtc_lock, flags);
+
         return 0;
 }