perf/x86: disable PEBS on a guest entry.

If PMU counter has PEBS enabled it is not enough to disable counter
on a guest entry since PEBS memory write can overshoot guest entry
and corrupt guest memory. Disabling PEBS during guest entry solves
the problem.

Tested-by: David Ahern <dsahern@gmail.com>
Signed-off-by: Gleb Natapov <gleb@redhat.com>
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Link: http://lkml.kernel.org/r/20120809085234.GI3341@redhat.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>

1 files changed, 9 insertions, 1 deletions

diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index 382366977d4c..7f2739e03e79 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -1522,8 +1522,16 @@ static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr)
         arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;
         arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask;
         arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask;
+        /*
+         * If PMU counter has PEBS enabled it is not enough to disable counter
+         * on a guest entry since PEBS memory write can overshoot guest entry
+         * and corrupt guest memory. Disabling PEBS solves the problem.
+         */
+        arr[1].msr = MSR_IA32_PEBS_ENABLE;
+        arr[1].host = cpuc->pebs_enabled;
+        arr[1].guest = 0;
 
-        *nr = 1;
+        *nr = 2;
         return arr;
 }