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authorArnd Bergmann <arnd@arndb.de>2012-05-14 09:59:18 -0400
committerArnd Bergmann <arnd@arndb.de>2012-05-14 11:35:50 -0400
commit090a80cba39f2763a488b6f7c65e38922d5aa17a (patch)
treeba3797eeca74c42be95bc592ed2db1be99e329d2 /arch
parent36be50515fe2aef61533b516fa2576a2c7fe7664 (diff)
parenteb3f995d7e73fd78b8fcdc55cfbf01a74a09a6e8 (diff)
Merge branch 'spear/13xx' into next/soc2
* spear/13xx: pinctrl: SPEAr1310: Fix pin numbers for clcd_high_res SPEAr: Update MAINTAINERS and Documentation SPEAr13xx: Add defconfig SPEAr13xx: Add compilation support SPEAr13xx: Add dts and dtsi files pinctrl: Add SPEAr13xx pinctrl drivers pinctrl: SPEAr: Create macro for declaring GPIO PINS SPEAr13xx: Add common clock framework support SPEAr13xx: Add source files SPEAr13xx: Add header files Depends on clock, pinctrl and dt branches to go first. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/Kconfig1
-rw-r--r--arch/arm/Makefile2
-rw-r--r--arch/arm/boot/dts/spear1310-evb.dts292
-rw-r--r--arch/arm/boot/dts/spear1310.dtsi184
-rw-r--r--arch/arm/boot/dts/spear1340-evb.dts308
-rw-r--r--arch/arm/boot/dts/spear1340.dtsi56
-rw-r--r--arch/arm/boot/dts/spear13xx.dtsi262
-rw-r--r--arch/arm/boot/dts/spear300-evb.dts246
-rw-r--r--arch/arm/boot/dts/spear300.dtsi77
-rw-r--r--arch/arm/boot/dts/spear310-evb.dts188
-rw-r--r--arch/arm/boot/dts/spear310.dtsi80
-rw-r--r--arch/arm/boot/dts/spear320-evb.dts198
-rw-r--r--arch/arm/boot/dts/spear320.dtsi95
-rw-r--r--arch/arm/boot/dts/spear3xx.dtsi150
-rw-r--r--arch/arm/boot/dts/spear600-evb.dts33
-rw-r--r--arch/arm/boot/dts/spear600.dtsi14
-rw-r--r--arch/arm/configs/spear13xx_defconfig95
-rw-r--r--arch/arm/configs/spear3xx_defconfig56
-rw-r--r--arch/arm/configs/spear6xx_defconfig44
-rw-r--r--arch/arm/mach-spear13xx/Kconfig20
-rw-r--r--arch/arm/mach-spear13xx/Makefile10
-rw-r--r--arch/arm/mach-spear13xx/Makefile.boot6
-rw-r--r--arch/arm/mach-spear13xx/headsmp.S47
-rw-r--r--arch/arm/mach-spear13xx/hotplug.c119
-rw-r--r--arch/arm/mach-spear13xx/include/mach/debug-macro.S14
-rw-r--r--arch/arm/mach-spear13xx/include/mach/dma.h128
-rw-r--r--arch/arm/mach-spear13xx/include/mach/generic.h49
-rw-r--r--arch/arm/mach-spear13xx/include/mach/gpio.h19
-rw-r--r--arch/arm/mach-spear13xx/include/mach/hardware.h1
-rw-r--r--arch/arm/mach-spear13xx/include/mach/irqs.h20
-rw-r--r--arch/arm/mach-spear13xx/include/mach/spear.h62
-rw-r--r--arch/arm/mach-spear13xx/include/mach/spear1310_misc_regs.h0
-rw-r--r--arch/arm/mach-spear13xx/include/mach/spear1340_misc_regs.h0
-rw-r--r--arch/arm/mach-spear13xx/include/mach/timex.h19
-rw-r--r--arch/arm/mach-spear13xx/include/mach/uncompress.h19
-rw-r--r--arch/arm/mach-spear13xx/platsmp.c127
-rw-r--r--arch/arm/mach-spear13xx/spear1310.c88
-rw-r--r--arch/arm/mach-spear13xx/spear1340.c192
-rw-r--r--arch/arm/mach-spear13xx/spear13xx.c197
-rw-r--r--arch/arm/mach-spear3xx/Kconfig37
-rw-r--r--arch/arm/mach-spear3xx/Makefile13
-rw-r--r--arch/arm/mach-spear3xx/Makefile.boot4
-rw-r--r--arch/arm/mach-spear3xx/clock.c760
-rw-r--r--arch/arm/mach-spear3xx/include/mach/generic.h175
-rw-r--r--arch/arm/mach-spear3xx/include/mach/hardware.h24
-rw-r--r--arch/arm/mach-spear3xx/include/mach/irqs.h131
-rw-r--r--arch/arm/mach-spear3xx/include/mach/misc_regs.h144
-rw-r--r--arch/arm/mach-spear3xx/include/mach/spear.h59
-rw-r--r--arch/arm/mach-spear3xx/include/mach/spear300.h54
-rw-r--r--arch/arm/mach-spear3xx/include/mach/spear310.h58
-rw-r--r--arch/arm/mach-spear3xx/include/mach/spear320.h67
-rw-r--r--arch/arm/mach-spear3xx/spear300.c653
-rw-r--r--arch/arm/mach-spear3xx/spear300_evb.c75
-rw-r--r--arch/arm/mach-spear3xx/spear310.c475
-rw-r--r--arch/arm/mach-spear3xx/spear310_evb.c81
-rw-r--r--arch/arm/mach-spear3xx/spear320.c733
-rw-r--r--arch/arm/mach-spear3xx/spear320_evb.c79
-rw-r--r--arch/arm/mach-spear3xx/spear3xx.c549
-rw-r--r--arch/arm/mach-spear6xx/Makefile2
-rw-r--r--arch/arm/mach-spear6xx/Makefile.boot2
-rw-r--r--arch/arm/mach-spear6xx/clock.c683
-rw-r--r--arch/arm/mach-spear6xx/include/mach/generic.h29
-rw-r--r--arch/arm/mach-spear6xx/include/mach/hardware.h24
-rw-r--r--arch/arm/mach-spear6xx/include/mach/irqs.h76
-rw-r--r--arch/arm/mach-spear6xx/include/mach/misc_regs.h154
-rw-r--r--arch/arm/mach-spear6xx/include/mach/spear.h56
-rw-r--r--arch/arm/mach-spear6xx/include/mach/spear600.h21
-rw-r--r--arch/arm/mach-spear6xx/spear6xx.c422
-rw-r--r--arch/arm/plat-spear/Kconfig16
-rw-r--r--arch/arm/plat-spear/Makefile5
-rw-r--r--arch/arm/plat-spear/clock.c1005
-rw-r--r--arch/arm/plat-spear/include/plat/clock.h249
-rw-r--r--arch/arm/plat-spear/include/plat/debug-macro.S2
-rw-r--r--arch/arm/plat-spear/include/plat/hardware.h17
-rw-r--r--arch/arm/plat-spear/include/plat/padmux.h92
-rw-r--r--arch/arm/plat-spear/include/plat/pl080.h21
-rw-r--r--arch/arm/plat-spear/include/plat/uncompress.h2
-rw-r--r--arch/arm/plat-spear/padmux.c164
-rw-r--r--arch/arm/plat-spear/pl080.c80
-rw-r--r--arch/arm/plat-spear/restart.c7
-rw-r--r--arch/arm/plat-spear/time.c48
81 files changed, 5119 insertions, 5747 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 36586dba6fa6..75066ed1f649 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -980,6 +980,7 @@ config PLAT_SPEAR
980 select ARM_AMBA 980 select ARM_AMBA
981 select ARCH_REQUIRE_GPIOLIB 981 select ARCH_REQUIRE_GPIOLIB
982 select CLKDEV_LOOKUP 982 select CLKDEV_LOOKUP
983 select COMMON_CLK
983 select CLKSRC_MMIO 984 select CLKSRC_MMIO
984 select GENERIC_CLOCKEVENTS 985 select GENERIC_CLOCKEVENTS
985 select HAVE_CLK 986 select HAVE_CLK
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 047a20780fc1..2aa75b58bf12 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -192,6 +192,8 @@ machine-$(CONFIG_ARCH_VEXPRESS) := vexpress
192machine-$(CONFIG_ARCH_VT8500) := vt8500 192machine-$(CONFIG_ARCH_VT8500) := vt8500
193machine-$(CONFIG_ARCH_W90X900) := w90x900 193machine-$(CONFIG_ARCH_W90X900) := w90x900
194machine-$(CONFIG_FOOTBRIDGE) := footbridge 194machine-$(CONFIG_FOOTBRIDGE) := footbridge
195machine-$(CONFIG_MACH_SPEAR1310) := spear13xx
196machine-$(CONFIG_MACH_SPEAR1340) := spear13xx
195machine-$(CONFIG_MACH_SPEAR300) := spear3xx 197machine-$(CONFIG_MACH_SPEAR300) := spear3xx
196machine-$(CONFIG_MACH_SPEAR310) := spear3xx 198machine-$(CONFIG_MACH_SPEAR310) := spear3xx
197machine-$(CONFIG_MACH_SPEAR320) := spear3xx 199machine-$(CONFIG_MACH_SPEAR320) := spear3xx
diff --git a/arch/arm/boot/dts/spear1310-evb.dts b/arch/arm/boot/dts/spear1310-evb.dts
new file mode 100644
index 000000000000..8314e4171884
--- /dev/null
+++ b/arch/arm/boot/dts/spear1310-evb.dts
@@ -0,0 +1,292 @@
1/*
2 * DTS file for SPEAr1310 Evaluation Baord
3 *
4 * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/dts-v1/;
15/include/ "spear1310.dtsi"
16
17/ {
18 model = "ST SPEAr1310 Evaluation Board";
19 compatible = "st,spear1310-evb", "st,spear1310";
20 #address-cells = <1>;
21 #size-cells = <1>;
22
23 memory {
24 reg = <0 0x40000000>;
25 };
26
27 ahb {
28 pinmux@e0700000 {
29 pinctrl-names = "default";
30 pinctrl-0 = <&state_default>;
31
32 state_default: pinmux {
33 i2c0-pmx {
34 st,pins = "i2c0_grp";
35 st,function = "i2c0";
36 };
37 i2s1 {
38 st,pins = "i2s1_grp";
39 st,function = "i2s1";
40 };
41 gpio {
42 st,pins = "arm_gpio_grp";
43 st,function = "arm_gpio";
44 };
45 eth {
46 st,pins = "gmii_grp";
47 st,function = "gmii";
48 };
49 ssp0 {
50 st,pins = "ssp0_grp";
51 st,function = "ssp0";
52 };
53 kbd {
54 st,pins = "keyboard_6x6_grp";
55 st,function = "keyboard";
56 };
57 sdhci {
58 st,pins = "sdhci_grp";
59 st,function = "sdhci";
60 };
61 smi-pmx {
62 st,pins = "smi_2_chips_grp";
63 st,function = "smi";
64 };
65 uart0 {
66 st,pins = "uart0_grp";
67 st,function = "uart0";
68 };
69 rs485 {
70 st,pins = "rs485_0_1_tdm_0_1_grp";
71 st,function = "rs485_0_1_tdm_0_1";
72 };
73 i2c1_2 {
74 st,pins = "i2c_1_2_grp";
75 st,function = "i2c_1_2";
76 };
77 pci {
78 st,pins = "pcie0_grp","pcie1_grp",
79 "pcie2_grp";
80 st,function = "pci";
81 };
82 smii {
83 st,pins = "smii_0_1_2_grp";
84 st,function = "smii_0_1_2";
85 };
86 nand {
87 st,pins = "nand_8bit_grp",
88 "nand_16bit_grp";
89 st,function = "nand";
90 };
91 };
92 };
93
94 ahci@b1000000 {
95 status = "okay";
96 };
97
98 cf@b2800000 {
99 status = "okay";
100 };
101
102 dma@ea800000 {
103 status = "okay";
104 };
105
106 dma@eb000000 {
107 status = "okay";
108 };
109
110 fsmc: flash@b0000000 {
111 status = "okay";
112 };
113
114 gmac0: eth@e2000000 {
115 status = "okay";
116 };
117
118 sdhci@b3000000 {
119 status = "okay";
120 };
121
122 smi: flash@ea000000 {
123 status = "okay";
124 clock-rate=<50000000>;
125
126 flash@e6000000 {
127 #address-cells = <1>;
128 #size-cells = <1>;
129 reg = <0xe6000000 0x800000>;
130 st,smi-fast-mode;
131
132 partition@0 {
133 label = "xloader";
134 reg = <0x0 0x10000>;
135 };
136 partition@10000 {
137 label = "u-boot";
138 reg = <0x10000 0x40000>;
139 };
140 partition@50000 {
141 label = "linux";
142 reg = <0x50000 0x2c0000>;
143 };
144 partition@310000 {
145 label = "rootfs";
146 reg = <0x310000 0x4f0000>;
147 };
148 };
149 };
150
151 spi0: spi@e0100000 {
152 status = "okay";
153 };
154
155 ehci@e4800000 {
156 status = "okay";
157 };
158
159 ehci@e5800000 {
160 status = "okay";
161 };
162
163 ohci@e4000000 {
164 status = "okay";
165 };
166
167 ohci@e5000000 {
168 status = "okay";
169 };
170
171 apb {
172 adc@e0080000 {
173 status = "okay";
174 };
175
176 gpio0: gpio@e0600000 {
177 status = "okay";
178 };
179
180 gpio1: gpio@e0680000 {
181 status = "okay";
182 };
183
184 i2c0: i2c@e0280000 {
185 status = "okay";
186 };
187
188 i2c1: i2c@5cd00000 {
189 status = "okay";
190 };
191
192 kbd@e0300000 {
193 linux,keymap = < 0x00000001
194 0x00010002
195 0x00020003
196 0x00030004
197 0x00040005
198 0x00050006
199 0x00060007
200 0x00070008
201 0x00080009
202 0x0100000a
203 0x0101000c
204 0x0102000d
205 0x0103000e
206 0x0104000f
207 0x01050010
208 0x01060011
209 0x01070012
210 0x01080013
211 0x02000014
212 0x02010015
213 0x02020016
214 0x02030017
215 0x02040018
216 0x02050019
217 0x0206001a
218 0x0207001b
219 0x0208001c
220 0x0300001d
221 0x0301001e
222 0x0302001f
223 0x03030020
224 0x03040021
225 0x03050022
226 0x03060023
227 0x03070024
228 0x03080025
229 0x04000026
230 0x04010027
231 0x04020028
232 0x04030029
233 0x0404002a
234 0x0405002b
235 0x0406002c
236 0x0407002d
237 0x0408002e
238 0x0500002f
239 0x05010030
240 0x05020031
241 0x05030032
242 0x05040033
243 0x05050034
244 0x05060035
245 0x05070036
246 0x05080037
247 0x06000038
248 0x06010039
249 0x0602003a
250 0x0603003b
251 0x0604003c
252 0x0605003d
253 0x0606003e
254 0x0607003f
255 0x06080040
256 0x07000041
257 0x07010042
258 0x07020043
259 0x07030044
260 0x07040045
261 0x07050046
262 0x07060047
263 0x07070048
264 0x07080049
265 0x0800004a
266 0x0801004b
267 0x0802004c
268 0x0803004d
269 0x0804004e
270 0x0805004f
271 0x08060050
272 0x08070051
273 0x08080052 >;
274 autorepeat;
275 st,mode = <0>;
276 status = "okay";
277 };
278
279 rtc@e0580000 {
280 status = "okay";
281 };
282
283 serial@e0000000 {
284 status = "okay";
285 };
286
287 wdt@ec800620 {
288 status = "okay";
289 };
290 };
291 };
292};
diff --git a/arch/arm/boot/dts/spear1310.dtsi b/arch/arm/boot/dts/spear1310.dtsi
new file mode 100644
index 000000000000..9e61da404d57
--- /dev/null
+++ b/arch/arm/boot/dts/spear1310.dtsi
@@ -0,0 +1,184 @@
1/*
2 * DTS file for all SPEAr1310 SoCs
3 *
4 * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/include/ "spear13xx.dtsi"
15
16/ {
17 compatible = "st,spear1310";
18
19 ahb {
20 ahci@b1000000 {
21 compatible = "snps,spear-ahci";
22 reg = <0xb1000000 0x10000>;
23 interrupts = <0 68 0x4>;
24 status = "disabled";
25 };
26
27 ahci@b1800000 {
28 compatible = "snps,spear-ahci";
29 reg = <0xb1800000 0x10000>;
30 interrupts = <0 69 0x4>;
31 status = "disabled";
32 };
33
34 ahci@b4000000 {
35 compatible = "snps,spear-ahci";
36 reg = <0xb4000000 0x10000>;
37 interrupts = <0 70 0x4>;
38 status = "disabled";
39 };
40
41 gmac1: eth@5c400000 {
42 compatible = "st,spear600-gmac";
43 reg = <0x5c400000 0x8000>;
44 interrupts = <0 95 0x4>;
45 interrupt-names = "macirq";
46 status = "disabled";
47 };
48
49 gmac2: eth@5c500000 {
50 compatible = "st,spear600-gmac";
51 reg = <0x5c500000 0x8000>;
52 interrupts = <0 96 0x4>;
53 interrupt-names = "macirq";
54 status = "disabled";
55 };
56
57 gmac3: eth@5c600000 {
58 compatible = "st,spear600-gmac";
59 reg = <0x5c600000 0x8000>;
60 interrupts = <0 97 0x4>;
61 interrupt-names = "macirq";
62 status = "disabled";
63 };
64
65 gmac4: eth@5c700000 {
66 compatible = "st,spear600-gmac";
67 reg = <0x5c700000 0x8000>;
68 interrupts = <0 98 0x4>;
69 interrupt-names = "macirq";
70 status = "disabled";
71 };
72
73 spi1: spi@5d400000 {
74 compatible = "arm,pl022", "arm,primecell";
75 reg = <0x5d400000 0x1000>;
76 interrupts = <0 99 0x4>;
77 status = "disabled";
78 };
79
80 apb {
81 i2c1: i2c@5cd00000 {
82 #address-cells = <1>;
83 #size-cells = <0>;
84 compatible = "snps,designware-i2c";
85 reg = <0x5cd00000 0x1000>;
86 interrupts = <0 87 0x4>;
87 status = "disabled";
88 };
89
90 i2c2: i2c@5ce00000 {
91 #address-cells = <1>;
92 #size-cells = <0>;
93 compatible = "snps,designware-i2c";
94 reg = <0x5ce00000 0x1000>;
95 interrupts = <0 88 0x4>;
96 status = "disabled";
97 };
98
99 i2c3: i2c@5cf00000 {
100 #address-cells = <1>;
101 #size-cells = <0>;
102 compatible = "snps,designware-i2c";
103 reg = <0x5cf00000 0x1000>;
104 interrupts = <0 89 0x4>;
105 status = "disabled";
106 };
107
108 i2c4: i2c@5d000000 {
109 #address-cells = <1>;
110 #size-cells = <0>;
111 compatible = "snps,designware-i2c";
112 reg = <0x5d000000 0x1000>;
113 interrupts = <0 90 0x4>;
114 status = "disabled";
115 };
116
117 i2c5: i2c@5d100000 {
118 #address-cells = <1>;
119 #size-cells = <0>;
120 compatible = "snps,designware-i2c";
121 reg = <0x5d100000 0x1000>;
122 interrupts = <0 91 0x4>;
123 status = "disabled";
124 };
125
126 i2c6: i2c@5d200000 {
127 #address-cells = <1>;
128 #size-cells = <0>;
129 compatible = "snps,designware-i2c";
130 reg = <0x5d200000 0x1000>;
131 interrupts = <0 92 0x4>;
132 status = "disabled";
133 };
134
135 i2c7: i2c@5d300000 {
136 #address-cells = <1>;
137 #size-cells = <0>;
138 compatible = "snps,designware-i2c";
139 reg = <0x5d300000 0x1000>;
140 interrupts = <0 93 0x4>;
141 status = "disabled";
142 };
143
144 serial@5c800000 {
145 compatible = "arm,pl011", "arm,primecell";
146 reg = <0x5c800000 0x1000>;
147 interrupts = <0 82 0x4>;
148 status = "disabled";
149 };
150
151 serial@5c900000 {
152 compatible = "arm,pl011", "arm,primecell";
153 reg = <0x5c900000 0x1000>;
154 interrupts = <0 83 0x4>;
155 status = "disabled";
156 };
157
158 serial@5ca00000 {
159 compatible = "arm,pl011", "arm,primecell";
160 reg = <0x5ca00000 0x1000>;
161 interrupts = <0 84 0x4>;
162 status = "disabled";
163 };
164
165 serial@5cb00000 {
166 compatible = "arm,pl011", "arm,primecell";
167 reg = <0x5cb00000 0x1000>;
168 interrupts = <0 85 0x4>;
169 status = "disabled";
170 };
171
172 serial@5cc00000 {
173 compatible = "arm,pl011", "arm,primecell";
174 reg = <0x5cc00000 0x1000>;
175 interrupts = <0 86 0x4>;
176 status = "disabled";
177 };
178
179 thermal@e07008c4 {
180 st,thermal-flags = <0x7000>;
181 };
182 };
183 };
184};
diff --git a/arch/arm/boot/dts/spear1340-evb.dts b/arch/arm/boot/dts/spear1340-evb.dts
new file mode 100644
index 000000000000..0d8472e5ab9f
--- /dev/null
+++ b/arch/arm/boot/dts/spear1340-evb.dts
@@ -0,0 +1,308 @@
1/*
2 * DTS file for SPEAr1340 Evaluation Baord
3 *
4 * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/dts-v1/;
15/include/ "spear1340.dtsi"
16
17/ {
18 model = "ST SPEAr1340 Evaluation Board";
19 compatible = "st,spear1340-evb", "st,spear1340";
20 #address-cells = <1>;
21 #size-cells = <1>;
22
23 memory {
24 reg = <0 0x40000000>;
25 };
26
27 ahb {
28 pinmux@e0700000 {
29 pinctrl-names = "default";
30 pinctrl-0 = <&state_default>;
31
32 state_default: pinmux {
33 pads_as_gpio {
34 st,pins = "pads_as_gpio_grp";
35 st,function = "pads_as_gpio";
36 };
37 fsmc {
38 st,pins = "fsmc_8bit_grp";
39 st,function = "fsmc";
40 };
41 kbd {
42 st,pins = "keyboard_row_col_grp",
43 "keyboard_col5_grp";
44 st,function = "keyboard";
45 };
46 uart0 {
47 st,pins = "uart0_grp", "uart0_enh_grp";
48 st,function = "uart0";
49 };
50 i2c0-pmx {
51 st,pins = "i2c0_grp";
52 st,function = "i2c0";
53 };
54 i2c1-pmx {
55 st,pins = "i2c1_grp";
56 st,function = "i2c1";
57 };
58 spdif-in {
59 st,pins = "spdif_in_grp";
60 st,function = "spdif_in";
61 };
62 spdif-out {
63 st,pins = "spdif_out_grp";
64 st,function = "spdif_out";
65 };
66 ssp0 {
67 st,pins = "ssp0_grp", "ssp0_cs1_grp",
68 "ssp0_cs3_grp";
69 st,function = "ssp0";
70 };
71 pwm {
72 st,pins = "pwm2_grp", "pwm3_grp";
73 st,function = "pwm";
74 };
75 smi-pmx {
76 st,pins = "smi_grp";
77 st,function = "smi";
78 };
79 i2s {
80 st,pins = "i2s_in_grp", "i2s_out_grp";
81 st,function = "i2s";
82 };
83 gmac {
84 st,pins = "gmii_grp", "rgmii_grp";
85 st,function = "gmac";
86 };
87 cam3 {
88 st,pins = "cam3_grp";
89 st,function = "cam3";
90 };
91 cec0 {
92 st,pins = "cec0_grp";
93 st,function = "cec0";
94 };
95 cec1 {
96 st,pins = "cec1_grp";
97 st,function = "cec1";
98 };
99 sdhci {
100 st,pins = "sdhci_grp";
101 st,function = "sdhci";
102 };
103 clcd {
104 st,pins = "clcd_grp";
105 st,function = "clcd";
106 };
107 sata {
108 st,pins = "sata_grp";
109 st,function = "sata";
110 };
111 };
112 };
113
114 dma@ea800000 {
115 status = "okay";
116 };
117
118 dma@eb000000 {
119 status = "okay";
120 };
121
122 fsmc: flash@b0000000 {
123 status = "okay";
124 };
125
126 gmac0: eth@e2000000 {
127 status = "okay";
128 };
129
130 sdhci@b3000000 {
131 status = "okay";
132 };
133
134 smi: flash@ea000000 {
135 status = "okay";
136 clock-rate=<50000000>;
137
138 flash@e6000000 {
139 #address-cells = <1>;
140 #size-cells = <1>;
141 reg = <0xe6000000 0x800000>;
142 st,smi-fast-mode;
143
144 partition@0 {
145 label = "xloader";
146 reg = <0x0 0x10000>;
147 };
148 partition@10000 {
149 label = "u-boot";
150 reg = <0x10000 0x40000>;
151 };
152 partition@50000 {
153 label = "linux";
154 reg = <0x50000 0x2c0000>;
155 };
156 partition@310000 {
157 label = "rootfs";
158 reg = <0x310000 0x4f0000>;
159 };
160 };
161 };
162
163 spi0: spi@e0100000 {
164 status = "okay";
165 };
166
167 ehci@e4800000 {
168 status = "okay";
169 };
170
171 ehci@e5800000 {
172 status = "okay";
173 };
174
175 ohci@e4000000 {
176 status = "okay";
177 };
178
179 ohci@e5000000 {
180 status = "okay";
181 };
182
183 apb {
184 adc@e0080000 {
185 status = "okay";
186 };
187
188 gpio0: gpio@e0600000 {
189 status = "okay";
190 };
191
192 gpio1: gpio@e0680000 {
193 status = "okay";
194 };
195
196 i2c0: i2c@e0280000 {
197 status = "okay";
198 };
199
200 i2c1: i2c@b4000000 {
201 status = "okay";
202 };
203
204 kbd@e0300000 {
205 linux,keymap = < 0x00000001
206 0x00010002
207 0x00020003
208 0x00030004
209 0x00040005
210 0x00050006
211 0x00060007
212 0x00070008
213 0x00080009
214 0x0100000a
215 0x0101000c
216 0x0102000d
217 0x0103000e
218 0x0104000f
219 0x01050010
220 0x01060011
221 0x01070012
222 0x01080013
223 0x02000014
224 0x02010015
225 0x02020016
226 0x02030017
227 0x02040018
228 0x02050019
229 0x0206001a
230 0x0207001b
231 0x0208001c
232 0x0300001d
233 0x0301001e
234 0x0302001f
235 0x03030020
236 0x03040021
237 0x03050022
238 0x03060023
239 0x03070024
240 0x03080025
241 0x04000026
242 0x04010027
243 0x04020028
244 0x04030029
245 0x0404002a
246 0x0405002b
247 0x0406002c
248 0x0407002d
249 0x0408002e
250 0x0500002f
251 0x05010030
252 0x05020031
253 0x05030032
254 0x05040033
255 0x05050034
256 0x05060035
257 0x05070036
258 0x05080037
259 0x06000038
260 0x06010039
261 0x0602003a
262 0x0603003b
263 0x0604003c
264 0x0605003d
265 0x0606003e
266 0x0607003f
267 0x06080040
268 0x07000041
269 0x07010042
270 0x07020043
271 0x07030044
272 0x07040045
273 0x07050046
274 0x07060047
275 0x07070048
276 0x07080049
277 0x0800004a
278 0x0801004b
279 0x0802004c
280 0x0803004d
281 0x0804004e
282 0x0805004f
283 0x08060050
284 0x08070051
285 0x08080052 >;
286 autorepeat;
287 st,mode = <0>;
288 status = "okay";
289 };
290
291 rtc@e0580000 {
292 status = "okay";
293 };
294
295 serial@e0000000 {
296 status = "okay";
297 };
298
299 serial@b4100000 {
300 status = "okay";
301 };
302
303 wdt@ec800620 {
304 status = "okay";
305 };
306 };
307 };
308};
diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi
new file mode 100644
index 000000000000..a26fc47a55e8
--- /dev/null
+++ b/arch/arm/boot/dts/spear1340.dtsi
@@ -0,0 +1,56 @@
1/*
2 * DTS file for all SPEAr1340 SoCs
3 *
4 * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/include/ "spear13xx.dtsi"
15
16/ {
17 compatible = "st,spear1340";
18
19 ahb {
20 ahci@b1000000 {
21 compatible = "snps,spear-ahci";
22 reg = <0xb1000000 0x10000>;
23 interrupts = <0 72 0x4>;
24 status = "disabled";
25 };
26
27 spi1: spi@5d400000 {
28 compatible = "arm,pl022", "arm,primecell";
29 reg = <0x5d400000 0x1000>;
30 interrupts = <0 99 0x4>;
31 status = "disabled";
32 };
33
34 apb {
35 i2c1: i2c@b4000000 {
36 #address-cells = <1>;
37 #size-cells = <0>;
38 compatible = "snps,designware-i2c";
39 reg = <0xb4000000 0x1000>;
40 interrupts = <0 104 0x4>;
41 status = "disabled";
42 };
43
44 serial@b4100000 {
45 compatible = "arm,pl011", "arm,primecell";
46 reg = <0xb4100000 0x1000>;
47 interrupts = <0 105 0x4>;
48 status = "disabled";
49 };
50
51 thermal@e07008c4 {
52 st,thermal-flags = <0x2a00>;
53 };
54 };
55 };
56};
diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
new file mode 100644
index 000000000000..1f8e1e1481df
--- /dev/null
+++ b/arch/arm/boot/dts/spear13xx.dtsi
@@ -0,0 +1,262 @@
1/*
2 * DTS file for all SPEAr13xx SoCs
3 *
4 * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/include/ "skeleton.dtsi"
15
16/ {
17 interrupt-parent = <&gic>;
18
19 cpus {
20 #address-cells = <1>;
21 #size-cells = <0>;
22
23 cpu@0 {
24 compatible = "arm,cortex-a9";
25 reg = <0>;
26 next-level-cache = <&L2>;
27 };
28
29 cpu@1 {
30 compatible = "arm,cortex-a9";
31 reg = <1>;
32 next-level-cache = <&L2>;
33 };
34 };
35
36 gic: interrupt-controller@ec801000 {
37 compatible = "arm,cortex-a9-gic";
38 interrupt-controller;
39 #interrupt-cells = <3>;
40 reg = < 0xec801000 0x1000 >,
41 < 0xec800100 0x0100 >;
42 };
43
44 pmu {
45 compatible = "arm,cortex-a9-pmu";
46 interrupts = <0 8 0x04
47 0 9 0x04>;
48 };
49
50 L2: l2-cache {
51 compatible = "arm,pl310-cache";
52 reg = <0xed000000 0x1000>;
53 cache-unified;
54 cache-level = <2>;
55 };
56
57 memory {
58 name = "memory";
59 device_type = "memory";
60 reg = <0 0x40000000>;
61 };
62
63 chosen {
64 bootargs = "console=ttyAMA0,115200";
65 };
66
67 ahb {
68 #address-cells = <1>;
69 #size-cells = <1>;
70 compatible = "simple-bus";
71 ranges = <0x50000000 0x50000000 0x10000000
72 0xb0000000 0xb0000000 0x10000000
73 0xe0000000 0xe0000000 0x10000000>;
74
75 sdhci@b3000000 {
76 compatible = "st,sdhci-spear";
77 reg = <0xb3000000 0x100>;
78 interrupts = <0 28 0x4>;
79 status = "disabled";
80 };
81
82 cf@b2800000 {
83 compatible = "arasan,cf-spear1340";
84 reg = <0xb2800000 0x100>;
85 interrupts = <0 29 0x4>;
86 status = "disabled";
87 };
88
89 dma@ea800000 {
90 compatible = "snps,dma-spear1340";
91 reg = <0xea800000 0x1000>;
92 interrupts = <0 19 0x4>;
93 status = "disabled";
94 };
95
96 dma@eb000000 {
97 compatible = "snps,dma-spear1340";
98 reg = <0xeb000000 0x1000>;
99 interrupts = <0 59 0x4>;
100 status = "disabled";
101 };
102
103 fsmc: flash@b0000000 {
104 compatible = "st,spear600-fsmc-nand";
105 #address-cells = <1>;
106 #size-cells = <1>;
107 reg = <0xb0000000 0x1000 /* FSMC Register */
108 0xb0800000 0x0010>; /* NAND Base */
109 reg-names = "fsmc_regs", "nand_data";
110 interrupts = <0 20 0x4
111 0 21 0x4
112 0 22 0x4
113 0 23 0x4>;
114 st,ale-off = <0x20000>;
115 st,cle-off = <0x10000>;
116 status = "disabled";
117 };
118
119 gmac0: eth@e2000000 {
120 compatible = "st,spear600-gmac";
121 reg = <0xe2000000 0x8000>;
122 interrupts = <0 23 0x4
123 0 24 0x4>;
124 interrupt-names = "macirq", "eth_wake_irq";
125 status = "disabled";
126 };
127
128 smi: flash@ea000000 {
129 compatible = "st,spear600-smi";
130 #address-cells = <1>;
131 #size-cells = <1>;
132 reg = <0xea000000 0x1000>;
133 interrupts = <0 30 0x4>;
134 status = "disabled";
135 };
136
137 spi0: spi@e0100000 {
138 compatible = "arm,pl022", "arm,primecell";
139 reg = <0xe0100000 0x1000>;
140 interrupts = <0 31 0x4>;
141 status = "disabled";
142 };
143
144 ehci@e4800000 {
145 compatible = "st,spear600-ehci", "usb-ehci";
146 reg = <0xe4800000 0x1000>;
147 interrupts = <0 64 0x4>;
148 status = "disabled";
149 };
150
151 ehci@e5800000 {
152 compatible = "st,spear600-ehci", "usb-ehci";
153 reg = <0xe5800000 0x1000>;
154 interrupts = <0 66 0x4>;
155 status = "disabled";
156 };
157
158 ohci@e4000000 {
159 compatible = "st,spear600-ohci", "usb-ohci";
160 reg = <0xe4000000 0x1000>;
161 interrupts = <0 65 0x4>;
162 status = "disabled";
163 };
164
165 ohci@e5000000 {
166 compatible = "st,spear600-ohci", "usb-ohci";
167 reg = <0xe5000000 0x1000>;
168 interrupts = <0 67 0x4>;
169 status = "disabled";
170 };
171
172 apb {
173 #address-cells = <1>;
174 #size-cells = <1>;
175 compatible = "simple-bus";
176 ranges = <0x50000000 0x50000000 0x10000000
177 0xb0000000 0xb0000000 0x10000000
178 0xe0000000 0xe0000000 0x10000000>;
179
180 gpio0: gpio@e0600000 {
181 compatible = "arm,pl061", "arm,primecell";
182 reg = <0xe0600000 0x1000>;
183 interrupts = <0 24 0x4>;
184 gpio-controller;
185 #gpio-cells = <2>;
186 interrupt-controller;
187 #interrupt-cells = <2>;
188 status = "disabled";
189 };
190
191 gpio1: gpio@e0680000 {
192 compatible = "arm,pl061", "arm,primecell";
193 reg = <0xe0680000 0x1000>;
194 interrupts = <0 25 0x4>;
195 gpio-controller;
196 #gpio-cells = <2>;
197 interrupt-controller;
198 #interrupt-cells = <2>;
199 status = "disabled";
200 };
201
202 kbd@e0300000 {
203 compatible = "st,spear300-kbd";
204 reg = <0xe0300000 0x1000>;
205 status = "disabled";
206 };
207
208 i2c0: i2c@e0280000 {
209 #address-cells = <1>;
210 #size-cells = <0>;
211 compatible = "snps,designware-i2c";
212 reg = <0xe0280000 0x1000>;
213 interrupts = <0 41 0x4>;
214 status = "disabled";
215 };
216
217 rtc@e0580000 {
218 compatible = "st,spear-rtc";
219 reg = <0xe0580000 0x1000>;
220 interrupts = <0 36 0x4>;
221 status = "disabled";
222 };
223
224 serial@e0000000 {
225 compatible = "arm,pl011", "arm,primecell";
226 reg = <0xe0000000 0x1000>;
227 interrupts = <0 36 0x4>;
228 status = "disabled";
229 };
230
231 adc@e0080000 {
232 compatible = "st,spear600-adc";
233 reg = <0xe0080000 0x1000>;
234 interrupts = <0 44 0x4>;
235 status = "disabled";
236 };
237
238 timer@e0380000 {
239 compatible = "st,spear-timer";
240 reg = <0xe0380000 0x400>;
241 interrupts = <0 37 0x4>;
242 };
243
244 timer@ec800600 {
245 compatible = "arm,cortex-a9-twd-timer";
246 reg = <0xec800600 0x20>;
247 interrupts = <1 13 0x301>;
248 };
249
250 wdt@ec800620 {
251 compatible = "arm,cortex-a9-twd-wdt";
252 reg = <0xec800620 0x20>;
253 status = "disabled";
254 };
255
256 thermal@e07008c4 {
257 compatible = "st,thermal-spear1340";
258 reg = <0xe07008c4 0x4>;
259 };
260 };
261 };
262};
diff --git a/arch/arm/boot/dts/spear300-evb.dts b/arch/arm/boot/dts/spear300-evb.dts
new file mode 100644
index 000000000000..fc82b1a26458
--- /dev/null
+++ b/arch/arm/boot/dts/spear300-evb.dts
@@ -0,0 +1,246 @@
1/*
2 * DTS file for SPEAr300 Evaluation Baord
3 *
4 * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/dts-v1/;
15/include/ "spear300.dtsi"
16
17/ {
18 model = "ST SPEAr300 Evaluation Board";
19 compatible = "st,spear300-evb", "st,spear300";
20 #address-cells = <1>;
21 #size-cells = <1>;
22
23 memory {
24 reg = <0 0x40000000>;
25 };
26
27 ahb {
28 pinmux@99000000 {
29 st,pinmux-mode = <2>;
30 pinctrl-names = "default";
31 pinctrl-0 = <&state_default>;
32
33 state_default: pinmux {
34 i2c0 {
35 st,pins = "i2c0_grp";
36 st,function = "i2c0";
37 };
38 ssp0 {
39 st,pins = "ssp0_grp";
40 st,function = "ssp0";
41 };
42 mii0 {
43 st,pins = "mii0_grp";
44 st,function = "mii0";
45 };
46 uart0 {
47 st,pins = "uart0_grp";
48 st,function = "uart0";
49 };
50 clcd {
51 st,pins = "clcd_pfmode_grp";
52 st,function = "clcd";
53 };
54 sdhci {
55 st,pins = "sdhci_4bit_grp";
56 st,function = "sdhci";
57 };
58 gpio1 {
59 st,pins = "gpio1_4_to_7_grp",
60 "gpio1_0_to_3_grp";
61 st,function = "gpio1";
62 };
63 };
64 };
65
66 clcd@60000000 {
67 status = "okay";
68 };
69
70 dma@fc400000 {
71 status = "okay";
72 };
73
74 fsmc: flash@94000000 {
75 status = "okay";
76 };
77
78 gmac: eth@e0800000 {
79 status = "okay";
80 };
81
82 sdhci@70000000 {
83 int-gpio = <&gpio1 0 0>;
84 power-gpio = <&gpio1 2 1>;
85 status = "okay";
86 };
87
88 smi: flash@fc000000 {
89 status = "okay";
90 clock-rate=<50000000>;
91
92 flash@f8000000 {
93 #address-cells = <1>;
94 #size-cells = <1>;
95 reg = <0xf8000000 0x800000>;
96 st,smi-fast-mode;
97
98 partition@0 {
99 label = "xloader";
100 reg = <0x0 0x10000>;
101 };
102 partition@10000 {
103 label = "u-boot";
104 reg = <0x10000 0x40000>;
105 };
106 partition@50000 {
107 label = "linux";
108 reg = <0x50000 0x2c0000>;
109 };
110 partition@310000 {
111 label = "rootfs";
112 reg = <0x310000 0x4f0000>;
113 };
114 };
115 };
116
117 spi0: spi@d0100000 {
118 status = "okay";
119 };
120
121 ehci@e1800000 {
122 status = "okay";
123 };
124
125 ohci@e1900000 {
126 status = "okay";
127 };
128
129 ohci@e2100000 {
130 status = "okay";
131 };
132
133 apb {
134 gpio0: gpio@fc980000 {
135 status = "okay";
136 };
137
138 gpio1: gpio@a9000000 {
139 status = "okay";
140 };
141
142 i2c0: i2c@d0180000 {
143 status = "okay";
144 };
145
146 kbd@a0000000 {
147 linux,keymap = < 0x00000001
148 0x00010002
149 0x00020003
150 0x00030004
151 0x00040005
152 0x00050006
153 0x00060007
154 0x00070008
155 0x00080009
156 0x0100000a
157 0x0101000c
158 0x0102000d
159 0x0103000e
160 0x0104000f
161 0x01050010
162 0x01060011
163 0x01070012
164 0x01080013
165 0x02000014
166 0x02010015
167 0x02020016
168 0x02030017
169 0x02040018
170 0x02050019
171 0x0206001a
172 0x0207001b
173 0x0208001c
174 0x0300001d
175 0x0301001e
176 0x0302001f
177 0x03030020
178 0x03040021
179 0x03050022
180 0x03060023
181 0x03070024
182 0x03080025
183 0x04000026
184 0x04010027
185 0x04020028
186 0x04030029
187 0x0404002a
188 0x0405002b
189 0x0406002c
190 0x0407002d
191 0x0408002e
192 0x0500002f
193 0x05010030
194 0x05020031
195 0x05030032
196 0x05040033
197 0x05050034
198 0x05060035
199 0x05070036
200 0x05080037
201 0x06000038
202 0x06010039
203 0x0602003a
204 0x0603003b
205 0x0604003c
206 0x0605003d
207 0x0606003e
208 0x0607003f
209 0x06080040
210 0x07000041
211 0x07010042
212 0x07020043
213 0x07030044
214 0x07040045
215 0x07050046
216 0x07060047
217 0x07070048
218 0x07080049
219 0x0800004a
220 0x0801004b
221 0x0802004c
222 0x0803004d
223 0x0804004e
224 0x0805004f
225 0x08060050
226 0x08070051
227 0x08080052 >;
228 autorepeat;
229 st,mode = <0>;
230 status = "okay";
231 };
232
233 rtc@fc900000 {
234 status = "okay";
235 };
236
237 serial@d0000000 {
238 status = "okay";
239 };
240
241 wdt@fc880000 {
242 status = "okay";
243 };
244 };
245 };
246};
diff --git a/arch/arm/boot/dts/spear300.dtsi b/arch/arm/boot/dts/spear300.dtsi
new file mode 100644
index 000000000000..01c5e358fdb2
--- /dev/null
+++ b/arch/arm/boot/dts/spear300.dtsi
@@ -0,0 +1,77 @@
1/*
2 * DTS file for SPEAr300 SoC
3 *
4 * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/include/ "spear3xx.dtsi"
15
16/ {
17 ahb {
18 #address-cells = <1>;
19 #size-cells = <1>;
20 compatible = "simple-bus";
21 ranges = <0x60000000 0x60000000 0x50000000
22 0xd0000000 0xd0000000 0x30000000>;
23
24 pinmux@99000000 {
25 compatible = "st,spear300-pinmux";
26 reg = <0x99000000 0x1000>;
27 };
28
29 clcd@60000000 {
30 compatible = "arm,clcd-pl110", "arm,primecell";
31 reg = <0x60000000 0x1000>;
32 interrupts = <30>;
33 status = "disabled";
34 };
35
36 fsmc: flash@94000000 {
37 compatible = "st,spear600-fsmc-nand";
38 #address-cells = <1>;
39 #size-cells = <1>;
40 reg = <0x94000000 0x1000 /* FSMC Register */
41 0x80000000 0x0010>; /* NAND Base */
42 reg-names = "fsmc_regs", "nand_data";
43 st,ale-off = <0x20000>;
44 st,cle-off = <0x10000>;
45 status = "disabled";
46 };
47
48 sdhci@70000000 {
49 compatible = "st,sdhci-spear";
50 reg = <0x70000000 0x100>;
51 interrupts = <1>;
52 status = "disabled";
53 };
54
55 apb {
56 #address-cells = <1>;
57 #size-cells = <1>;
58 compatible = "simple-bus";
59 ranges = <0xa0000000 0xa0000000 0x10000000
60 0xd0000000 0xd0000000 0x30000000>;
61
62 gpio1: gpio@a9000000 {
63 #gpio-cells = <2>;
64 compatible = "arm,pl061", "arm,primecell";
65 gpio-controller;
66 reg = <0xa9000000 0x1000>;
67 status = "disabled";
68 };
69
70 kbd@a0000000 {
71 compatible = "st,spear300-kbd";
72 reg = <0xa0000000 0x1000>;
73 status = "disabled";
74 };
75 };
76 };
77};
diff --git a/arch/arm/boot/dts/spear310-evb.dts b/arch/arm/boot/dts/spear310-evb.dts
new file mode 100644
index 000000000000..dc5e2d445a93
--- /dev/null
+++ b/arch/arm/boot/dts/spear310-evb.dts
@@ -0,0 +1,188 @@
1/*
2 * DTS file for SPEAr310 Evaluation Baord
3 *
4 * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/dts-v1/;
15/include/ "spear310.dtsi"
16
17/ {
18 model = "ST SPEAr310 Evaluation Board";
19 compatible = "st,spear310-evb", "st,spear310";
20 #address-cells = <1>;
21 #size-cells = <1>;
22
23 memory {
24 reg = <0 0x40000000>;
25 };
26
27 ahb {
28 pinmux@b4000000 {
29 pinctrl-names = "default";
30 pinctrl-0 = <&state_default>;
31
32 state_default: pinmux {
33 gpio0 {
34 st,pins = "gpio0_pin0_grp",
35 "gpio0_pin1_grp",
36 "gpio0_pin2_grp",
37 "gpio0_pin3_grp",
38 "gpio0_pin4_grp",
39 "gpio0_pin5_grp";
40 st,function = "gpio0";
41 };
42 i2c0 {
43 st,pins = "i2c0_grp";
44 st,function = "i2c0";
45 };
46 mii0 {
47 st,pins = "mii0_grp";
48 st,function = "mii0";
49 };
50 ssp0 {
51 st,pins = "ssp0_grp";
52 st,function = "ssp0";
53 };
54 uart0 {
55 st,pins = "uart0_grp";
56 st,function = "uart0";
57 };
58 emi {
59 st,pins = "emi_cs_0_to_5_grp";
60 st,function = "emi";
61 };
62 fsmc {
63 st,pins = "fsmc_grp";
64 st,function = "fsmc";
65 };
66 uart1 {
67 st,pins = "uart1_grp";
68 st,function = "uart1";
69 };
70 uart2 {
71 st,pins = "uart2_grp";
72 st,function = "uart2";
73 };
74 uart3 {
75 st,pins = "uart3_grp";
76 st,function = "uart3";
77 };
78 uart4 {
79 st,pins = "uart4_grp";
80 st,function = "uart4";
81 };
82 uart5 {
83 st,pins = "uart5_grp";
84 st,function = "uart5";
85 };
86 };
87 };
88
89 dma@fc400000 {
90 status = "okay";
91 };
92
93 fsmc: flash@44000000 {
94 status = "okay";
95 };
96
97 gmac: eth@e0800000 {
98 status = "okay";
99 };
100
101 smi: flash@fc000000 {
102 status = "okay";
103 clock-rate=<50000000>;
104
105 flash@f8000000 {
106 #address-cells = <1>;
107 #size-cells = <1>;
108 reg = <0xf8000000 0x800000>;
109 st,smi-fast-mode;
110
111 partition@0 {
112 label = "xloader";
113 reg = <0x0 0x10000>;
114 };
115 partition@10000 {
116 label = "u-boot";
117 reg = <0x10000 0x40000>;
118 };
119 partition@50000 {
120 label = "linux";
121 reg = <0x50000 0x2c0000>;
122 };
123 partition@310000 {
124 label = "rootfs";
125 reg = <0x310000 0x4f0000>;
126 };
127 };
128 };
129
130 spi0: spi@d0100000 {
131 status = "okay";
132 };
133
134 ehci@e1800000 {
135 status = "okay";
136 };
137
138 ohci@e1900000 {
139 status = "okay";
140 };
141
142 ohci@e2100000 {
143 status = "okay";
144 };
145
146 apb {
147 gpio0: gpio@fc980000 {
148 status = "okay";
149 };
150
151 i2c0: i2c@d0180000 {
152 status = "okay";
153 };
154
155 rtc@fc900000 {
156 status = "okay";
157 };
158
159 serial@d0000000 {
160 status = "okay";
161 };
162
163 serial@b2000000 {
164 status = "okay";
165 };
166
167 serial@b2080000 {
168 status = "okay";
169 };
170
171 serial@b2100000 {
172 status = "okay";
173 };
174
175 serial@b2180000 {
176 status = "okay";
177 };
178
179 serial@b2200000 {
180 status = "okay";
181 };
182
183 wdt@fc880000 {
184 status = "okay";
185 };
186 };
187 };
188};
diff --git a/arch/arm/boot/dts/spear310.dtsi b/arch/arm/boot/dts/spear310.dtsi
new file mode 100644
index 000000000000..e47081c494d9
--- /dev/null
+++ b/arch/arm/boot/dts/spear310.dtsi
@@ -0,0 +1,80 @@
1/*
2 * DTS file for SPEAr310 SoC
3 *
4 * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/include/ "spear3xx.dtsi"
15
16/ {
17 ahb {
18 #address-cells = <1>;
19 #size-cells = <1>;
20 compatible = "simple-bus";
21 ranges = <0x40000000 0x40000000 0x10000000
22 0xb0000000 0xb0000000 0x10000000
23 0xd0000000 0xd0000000 0x30000000>;
24
25 pinmux@b4000000 {
26 compatible = "st,spear310-pinmux";
27 reg = <0xb4000000 0x1000>;
28 };
29
30 fsmc: flash@44000000 {
31 compatible = "st,spear600-fsmc-nand";
32 #address-cells = <1>;
33 #size-cells = <1>;
34 reg = <0x44000000 0x1000 /* FSMC Register */
35 0x40000000 0x0010>; /* NAND Base */
36 reg-names = "fsmc_regs", "nand_data";
37 st,ale-off = <0x10000>;
38 st,cle-off = <0x20000>;
39 status = "disabled";
40 };
41
42 apb {
43 #address-cells = <1>;
44 #size-cells = <1>;
45 compatible = "simple-bus";
46 ranges = <0xb0000000 0xb0000000 0x10000000
47 0xd0000000 0xd0000000 0x30000000>;
48
49 serial@b2000000 {
50 compatible = "arm,pl011", "arm,primecell";
51 reg = <0xb2000000 0x1000>;
52 status = "disabled";
53 };
54
55 serial@b2080000 {
56 compatible = "arm,pl011", "arm,primecell";
57 reg = <0xb2080000 0x1000>;
58 status = "disabled";
59 };
60
61 serial@b2100000 {
62 compatible = "arm,pl011", "arm,primecell";
63 reg = <0xb2100000 0x1000>;
64 status = "disabled";
65 };
66
67 serial@b2180000 {
68 compatible = "arm,pl011", "arm,primecell";
69 reg = <0xb2180000 0x1000>;
70 status = "disabled";
71 };
72
73 serial@b2200000 {
74 compatible = "arm,pl011", "arm,primecell";
75 reg = <0xb2200000 0x1000>;
76 status = "disabled";
77 };
78 };
79 };
80};
diff --git a/arch/arm/boot/dts/spear320-evb.dts b/arch/arm/boot/dts/spear320-evb.dts
new file mode 100644
index 000000000000..6308fa3bec1e
--- /dev/null
+++ b/arch/arm/boot/dts/spear320-evb.dts
@@ -0,0 +1,198 @@
1/*
2 * DTS file for SPEAr320 Evaluation Baord
3 *
4 * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/dts-v1/;
15/include/ "spear320.dtsi"
16
17/ {
18 model = "ST SPEAr300 Evaluation Board";
19 compatible = "st,spear300-evb", "st,spear300";
20 #address-cells = <1>;
21 #size-cells = <1>;
22
23 memory {
24 reg = <0 0x40000000>;
25 };
26
27 ahb {
28 pinmux@b3000000 {
29 st,pinmux-mode = <3>;
30 pinctrl-names = "default";
31 pinctrl-0 = <&state_default>;
32
33 state_default: pinmux {
34 i2c0 {
35 st,pins = "i2c0_grp";
36 st,function = "i2c0";
37 };
38 mii0 {
39 st,pins = "mii0_grp";
40 st,function = "mii0";
41 };
42 ssp0 {
43 st,pins = "ssp0_grp";
44 st,function = "ssp0";
45 };
46 uart0 {
47 st,pins = "uart0_grp";
48 st,function = "uart0";
49 };
50 sdhci {
51 st,pins = "sdhci_cd_51_grp";
52 st,function = "sdhci";
53 };
54 i2s {
55 st,pins = "i2s_grp";
56 st,function = "i2s";
57 };
58 uart1 {
59 st,pins = "uart1_grp";
60 st,function = "uart1";
61 };
62 uart2 {
63 st,pins = "uart2_grp";
64 st,function = "uart2";
65 };
66 can0 {
67 st,pins = "can0_grp";
68 st,function = "can0";
69 };
70 can1 {
71 st,pins = "can1_grp";
72 st,function = "can1";
73 };
74 mii2 {
75 st,pins = "mii2_grp";
76 st,function = "mii2";
77 };
78 pwm0_1 {
79 st,pins = "pwm0_1_pin_14_15_grp";
80 st,function = "pwm0_1";
81 };
82 pwm2 {
83 st,pins = "pwm2_pin_13_grp";
84 st,function = "pwm2";
85 };
86 };
87 };
88
89 clcd@90000000 {
90 status = "okay";
91 };
92
93 dma@fc400000 {
94 status = "okay";
95 };
96
97 fsmc: flash@4c000000 {
98 status = "okay";
99 };
100
101 gmac: eth@e0800000 {
102 status = "okay";
103 };
104
105 sdhci@70000000 {
106 power-gpio = <&gpio0 2 1>;
107 power_always_enb;
108 status = "okay";
109 };
110
111 smi: flash@fc000000 {
112 status = "okay";
113 clock-rate=<50000000>;
114
115 flash@f8000000 {
116 #address-cells = <1>;
117 #size-cells = <1>;
118 reg = <0xf8000000 0x800000>;
119 st,smi-fast-mode;
120
121 partition@0 {
122 label = "xloader";
123 reg = <0x0 0x10000>;
124 };
125 partition@10000 {
126 label = "u-boot";
127 reg = <0x10000 0x40000>;
128 };
129 partition@50000 {
130 label = "linux";
131 reg = <0x50000 0x2c0000>;
132 };
133 partition@310000 {
134 label = "rootfs";
135 reg = <0x310000 0x4f0000>;
136 };
137 };
138 };
139
140 spi0: spi@d0100000 {
141 status = "okay";
142 };
143
144 spi1: spi@a5000000 {
145 status = "okay";
146 };
147
148 spi2: spi@a6000000 {
149 status = "okay";
150 };
151
152 ehci@e1800000 {
153 status = "okay";
154 };
155
156 ohci@e1900000 {
157 status = "okay";
158 };
159
160 ohci@e2100000 {
161 status = "okay";
162 };
163
164 apb {
165 gpio0: gpio@fc980000 {
166 status = "okay";
167 };
168
169 i2c0: i2c@d0180000 {
170 status = "okay";
171 };
172
173 i2c1: i2c@a7000000 {
174 status = "okay";
175 };
176
177 rtc@fc900000 {
178 status = "okay";
179 };
180
181 serial@d0000000 {
182 status = "okay";
183 };
184
185 serial@a3000000 {
186 status = "okay";
187 };
188
189 serial@a4000000 {
190 status = "okay";
191 };
192
193 wdt@fc880000 {
194 status = "okay";
195 };
196 };
197 };
198};
diff --git a/arch/arm/boot/dts/spear320.dtsi b/arch/arm/boot/dts/spear320.dtsi
new file mode 100644
index 000000000000..5372ca399b1f
--- /dev/null
+++ b/arch/arm/boot/dts/spear320.dtsi
@@ -0,0 +1,95 @@
1/*
2 * DTS file for SPEAr320 SoC
3 *
4 * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/include/ "spear3xx.dtsi"
15
16/ {
17 ahb {
18 #address-cells = <1>;
19 #size-cells = <1>;
20 compatible = "simple-bus";
21 ranges = <0x40000000 0x40000000 0x80000000
22 0xd0000000 0xd0000000 0x30000000>;
23
24 pinmux@b3000000 {
25 compatible = "st,spear320-pinmux";
26 reg = <0xb3000000 0x1000>;
27 };
28
29 clcd@90000000 {
30 compatible = "arm,clcd-pl110", "arm,primecell";
31 reg = <0x90000000 0x1000>;
32 interrupts = <33>;
33 status = "disabled";
34 };
35
36 fsmc: flash@4c000000 {
37 compatible = "st,spear600-fsmc-nand";
38 #address-cells = <1>;
39 #size-cells = <1>;
40 reg = <0x4c000000 0x1000 /* FSMC Register */
41 0x50000000 0x0010>; /* NAND Base */
42 reg-names = "fsmc_regs", "nand_data";
43 st,ale-off = <0x20000>;
44 st,cle-off = <0x10000>;
45 status = "disabled";
46 };
47
48 sdhci@70000000 {
49 compatible = "st,sdhci-spear";
50 reg = <0x70000000 0x100>;
51 interrupts = <29>;
52 status = "disabled";
53 };
54
55 spi1: spi@a5000000 {
56 compatible = "arm,pl022", "arm,primecell";
57 reg = <0xa5000000 0x1000>;
58 status = "disabled";
59 };
60
61 spi2: spi@a6000000 {
62 compatible = "arm,pl022", "arm,primecell";
63 reg = <0xa6000000 0x1000>;
64 status = "disabled";
65 };
66
67 apb {
68 #address-cells = <1>;
69 #size-cells = <1>;
70 compatible = "simple-bus";
71 ranges = <0xa0000000 0xa0000000 0x10000000
72 0xd0000000 0xd0000000 0x30000000>;
73
74 i2c1: i2c@a7000000 {
75 #address-cells = <1>;
76 #size-cells = <0>;
77 compatible = "snps,designware-i2c";
78 reg = <0xa7000000 0x1000>;
79 status = "disabled";
80 };
81
82 serial@a3000000 {
83 compatible = "arm,pl011", "arm,primecell";
84 reg = <0xa3000000 0x1000>;
85 status = "disabled";
86 };
87
88 serial@a4000000 {
89 compatible = "arm,pl011", "arm,primecell";
90 reg = <0xa4000000 0x1000>;
91 status = "disabled";
92 };
93 };
94 };
95};
diff --git a/arch/arm/boot/dts/spear3xx.dtsi b/arch/arm/boot/dts/spear3xx.dtsi
new file mode 100644
index 000000000000..91072553963f
--- /dev/null
+++ b/arch/arm/boot/dts/spear3xx.dtsi
@@ -0,0 +1,150 @@
1/*
2 * DTS file for all SPEAr3xx SoCs
3 *
4 * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/include/ "skeleton.dtsi"
15
16/ {
17 interrupt-parent = <&vic>;
18
19 cpus {
20 cpu@0 {
21 compatible = "arm,arm926ejs";
22 };
23 };
24
25 memory {
26 device_type = "memory";
27 reg = <0 0x40000000>;
28 };
29
30 ahb {
31 #address-cells = <1>;
32 #size-cells = <1>;
33 compatible = "simple-bus";
34 ranges = <0xd0000000 0xd0000000 0x30000000>;
35
36 vic: interrupt-controller@f1100000 {
37 compatible = "arm,pl190-vic";
38 interrupt-controller;
39 reg = <0xf1100000 0x1000>;
40 #interrupt-cells = <1>;
41 };
42
43 dma@fc400000 {
44 compatible = "arm,pl080", "arm,primecell";
45 reg = <0xfc400000 0x1000>;
46 interrupt-parent = <&vic>;
47 interrupts = <8>;
48 status = "disabled";
49 };
50
51 gmac: eth@e0800000 {
52 compatible = "st,spear600-gmac";
53 reg = <0xe0800000 0x8000>;
54 interrupts = <23 22>;
55 interrupt-names = "macirq", "eth_wake_irq";
56 status = "disabled";
57 };
58
59 smi: flash@fc000000 {
60 compatible = "st,spear600-smi";
61 #address-cells = <1>;
62 #size-cells = <1>;
63 reg = <0xfc000000 0x1000>;
64 interrupts = <9>;
65 status = "disabled";
66 };
67
68 spi0: spi@d0100000 {
69 compatible = "arm,pl022", "arm,primecell";
70 reg = <0xd0100000 0x1000>;
71 interrupts = <20>;
72 status = "disabled";
73 };
74
75 ehci@e1800000 {
76 compatible = "st,spear600-ehci", "usb-ehci";
77 reg = <0xe1800000 0x1000>;
78 interrupts = <26>;
79 status = "disabled";
80 };
81
82 ohci@e1900000 {
83 compatible = "st,spear600-ohci", "usb-ohci";
84 reg = <0xe1900000 0x1000>;
85 interrupts = <25>;
86 status = "disabled";
87 };
88
89 ohci@e2100000 {
90 compatible = "st,spear600-ohci", "usb-ohci";
91 reg = <0xe2100000 0x1000>;
92 interrupts = <27>;
93 status = "disabled";
94 };
95
96 apb {
97 #address-cells = <1>;
98 #size-cells = <1>;
99 compatible = "simple-bus";
100 ranges = <0xd0000000 0xd0000000 0x30000000>;
101
102 gpio0: gpio@fc980000 {
103 compatible = "arm,pl061", "arm,primecell";
104 reg = <0xfc980000 0x1000>;
105 interrupts = <11>;
106 gpio-controller;
107 #gpio-cells = <2>;
108 interrupt-controller;
109 #interrupt-cells = <2>;
110 status = "disabled";
111 };
112
113 i2c0: i2c@d0180000 {
114 #address-cells = <1>;
115 #size-cells = <0>;
116 compatible = "snps,designware-i2c";
117 reg = <0xd0180000 0x1000>;
118 interrupts = <21>;
119 status = "disabled";
120 };
121
122 rtc@fc900000 {
123 compatible = "st,spear-rtc";
124 reg = <0xfc900000 0x1000>;
125 interrupts = <10>;
126 status = "disabled";
127 };
128
129 serial@d0000000 {
130 compatible = "arm,pl011", "arm,primecell";
131 reg = <0xd0000000 0x1000>;
132 interrupts = <19>;
133 status = "disabled";
134 };
135
136 wdt@fc880000 {
137 compatible = "arm,sp805", "arm,primecell";
138 reg = <0xfc880000 0x1000>;
139 interrupts = <12>;
140 status = "disabled";
141 };
142
143 timer@f0000000 {
144 compatible = "st,spear-timer";
145 reg = <0xf0000000 0x400>;
146 interrupts = <2>;
147 };
148 };
149 };
150};
diff --git a/arch/arm/boot/dts/spear600-evb.dts b/arch/arm/boot/dts/spear600-evb.dts
index 636292e18c90..1119c22c9a82 100644
--- a/arch/arm/boot/dts/spear600-evb.dts
+++ b/arch/arm/boot/dts/spear600-evb.dts
@@ -24,11 +24,44 @@
24 }; 24 };
25 25
26 ahb { 26 ahb {
27 dma@fc400000 {
28 status = "okay";
29 };
30
27 gmac: ethernet@e0800000 { 31 gmac: ethernet@e0800000 {
28 phy-mode = "gmii"; 32 phy-mode = "gmii";
29 status = "okay"; 33 status = "okay";
30 }; 34 };
31 35
36 smi: flash@fc000000 {
37 status = "okay";
38 clock-rate=<50000000>;
39
40 flash@f8000000 {
41 #address-cells = <1>;
42 #size-cells = <1>;
43 reg = <0xf8000000 0x800000>;
44 st,smi-fast-mode;
45
46 partition@0 {
47 label = "xloader";
48 reg = <0x0 0x10000>;
49 };
50 partition@10000 {
51 label = "u-boot";
52 reg = <0x10000 0x40000>;
53 };
54 partition@50000 {
55 label = "linux";
56 reg = <0x50000 0x2c0000>;
57 };
58 partition@310000 {
59 label = "rootfs";
60 reg = <0x310000 0x4f0000>;
61 };
62 };
63 };
64
32 apb { 65 apb {
33 serial@d0000000 { 66 serial@d0000000 {
34 status = "okay"; 67 status = "okay";
diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi
index ebe0885a2b98..089f0a42c50e 100644
--- a/arch/arm/boot/dts/spear600.dtsi
+++ b/arch/arm/boot/dts/spear600.dtsi
@@ -45,6 +45,14 @@
45 #interrupt-cells = <1>; 45 #interrupt-cells = <1>;
46 }; 46 };
47 47
48 dma@fc400000 {
49 compatible = "arm,pl080", "arm,primecell";
50 reg = <0xfc400000 0x1000>;
51 interrupt-parent = <&vic1>;
52 interrupts = <10>;
53 status = "disabled";
54 };
55
48 gmac: ethernet@e0800000 { 56 gmac: ethernet@e0800000 {
49 compatible = "st,spear600-gmac"; 57 compatible = "st,spear600-gmac";
50 reg = <0xe0800000 0x8000>; 58 reg = <0xe0800000 0x8000>;
@@ -169,6 +177,12 @@
169 interrupts = <28>; 177 interrupts = <28>;
170 status = "disabled"; 178 status = "disabled";
171 }; 179 };
180
181 timer@f0000000 {
182 compatible = "st,spear-timer";
183 reg = <0xf0000000 0x400>;
184 interrupts = <16>;
185 };
172 }; 186 };
173 }; 187 };
174}; 188};
diff --git a/arch/arm/configs/spear13xx_defconfig b/arch/arm/configs/spear13xx_defconfig
new file mode 100644
index 000000000000..1fdb82694ca2
--- /dev/null
+++ b/arch/arm/configs/spear13xx_defconfig
@@ -0,0 +1,95 @@
1CONFIG_EXPERIMENTAL=y
2CONFIG_SYSVIPC=y
3CONFIG_BSD_PROCESS_ACCT=y
4CONFIG_BLK_DEV_INITRD=y
5CONFIG_MODULES=y
6CONFIG_MODULE_UNLOAD=y
7CONFIG_MODVERSIONS=y
8CONFIG_PARTITION_ADVANCED=y
9CONFIG_PLAT_SPEAR=y
10CONFIG_ARCH_SPEAR13XX=y
11CONFIG_MACH_SPEAR1310=y
12CONFIG_MACH_SPEAR1340=y
13# CONFIG_SWP_EMULATE is not set
14CONFIG_SMP=y
15# CONFIG_SMP_ON_UP is not set
16# CONFIG_ARM_CPU_TOPOLOGY is not set
17CONFIG_ARM_APPENDED_DTB=y
18CONFIG_ARM_ATAG_DTB_COMPAT=y
19CONFIG_BINFMT_MISC=y
20CONFIG_NET=y
21CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
22CONFIG_MTD=y
23CONFIG_MTD_OF_PARTS=y
24CONFIG_MTD_CHAR=y
25CONFIG_MTD_BLOCK=y
26CONFIG_MTD_NAND=y
27CONFIG_MTD_NAND_FSMC=y
28CONFIG_BLK_DEV_RAM=y
29CONFIG_BLK_DEV_RAM_SIZE=16384
30CONFIG_ATA=y
31# CONFIG_SATA_PMP is not set
32CONFIG_SATA_AHCI_PLATFORM=y
33CONFIG_PATA_ARASAN_CF=y
34CONFIG_NETDEVICES=y
35# CONFIG_NET_VENDOR_BROADCOM is not set
36# CONFIG_NET_VENDOR_CIRRUS is not set
37# CONFIG_NET_VENDOR_FARADAY is not set
38# CONFIG_NET_VENDOR_INTEL is not set
39# CONFIG_NET_VENDOR_MICREL is not set
40# CONFIG_NET_VENDOR_NATSEMI is not set
41# CONFIG_NET_VENDOR_SEEQ is not set
42# CONFIG_NET_VENDOR_SMSC is not set
43CONFIG_STMMAC_ETH=y
44# CONFIG_WLAN is not set
45CONFIG_INPUT_FF_MEMLESS=y
46# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
47# CONFIG_KEYBOARD_ATKBD is not set
48CONFIG_KEYBOARD_SPEAR=y
49# CONFIG_INPUT_MOUSE is not set
50# CONFIG_LEGACY_PTYS is not set
51CONFIG_SERIAL_AMBA_PL011=y
52CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
53# CONFIG_HW_RANDOM is not set
54CONFIG_RAW_DRIVER=y
55CONFIG_MAX_RAW_DEVS=8192
56CONFIG_I2C=y
57CONFIG_I2C_DESIGNWARE_PLATFORM=y
58CONFIG_SPI=y
59CONFIG_SPI_PL022=y
60CONFIG_GPIO_SYSFS=y
61CONFIG_GPIO_PL061=y
62# CONFIG_HWMON is not set
63CONFIG_WATCHDOG=y
64CONFIG_MPCORE_WATCHDOG=y
65# CONFIG_HID_SUPPORT is not set
66CONFIG_USB=y
67# CONFIG_USB_DEVICE_CLASS is not set
68CONFIG_USB_EHCI_HCD=y
69CONFIG_USB_OHCI_HCD=y
70CONFIG_MMC=y
71CONFIG_MMC_SDHCI=y
72CONFIG_MMC_SDHCI_SPEAR=y
73CONFIG_RTC_CLASS=y
74CONFIG_DMADEVICES=y
75CONFIG_DW_DMAC=y
76CONFIG_DMATEST=m
77CONFIG_EXT2_FS=y
78CONFIG_EXT2_FS_XATTR=y
79CONFIG_EXT2_FS_SECURITY=y
80CONFIG_EXT3_FS=y
81CONFIG_EXT3_FS_SECURITY=y
82CONFIG_AUTOFS4_FS=m
83CONFIG_MSDOS_FS=m
84CONFIG_VFAT_FS=m
85CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
86CONFIG_TMPFS=y
87CONFIG_JFFS2_FS=y
88CONFIG_NLS_DEFAULT="utf8"
89CONFIG_NLS_CODEPAGE_437=y
90CONFIG_NLS_ASCII=m
91CONFIG_MAGIC_SYSRQ=y
92CONFIG_DEBUG_FS=y
93CONFIG_DEBUG_KERNEL=y
94CONFIG_DEBUG_SPINLOCK=y
95CONFIG_DEBUG_INFO=y
diff --git a/arch/arm/configs/spear3xx_defconfig b/arch/arm/configs/spear3xx_defconfig
index fea7e1f026a3..865980c5f212 100644
--- a/arch/arm/configs/spear3xx_defconfig
+++ b/arch/arm/configs/spear3xx_defconfig
@@ -2,33 +2,70 @@ CONFIG_EXPERIMENTAL=y
2CONFIG_SYSVIPC=y 2CONFIG_SYSVIPC=y
3CONFIG_BSD_PROCESS_ACCT=y 3CONFIG_BSD_PROCESS_ACCT=y
4CONFIG_BLK_DEV_INITRD=y 4CONFIG_BLK_DEV_INITRD=y
5CONFIG_KALLSYMS_EXTRA_PASS=y
6CONFIG_MODULES=y 5CONFIG_MODULES=y
7CONFIG_MODULE_UNLOAD=y 6CONFIG_MODULE_UNLOAD=y
8CONFIG_MODVERSIONS=y 7CONFIG_MODVERSIONS=y
8CONFIG_PARTITION_ADVANCED=y
9CONFIG_PLAT_SPEAR=y 9CONFIG_PLAT_SPEAR=y
10CONFIG_BOARD_SPEAR300_EVB=y 10CONFIG_MACH_SPEAR300=y
11CONFIG_BOARD_SPEAR310_EVB=y 11CONFIG_MACH_SPEAR310=y
12CONFIG_BOARD_SPEAR320_EVB=y 12CONFIG_MACH_SPEAR320=y
13CONFIG_BINFMT_MISC=y 13CONFIG_BINFMT_MISC=y
14CONFIG_NET=y
14CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 15CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
16CONFIG_MTD=y
17CONFIG_MTD_OF_PARTS=y
18CONFIG_MTD_CHAR=y
19CONFIG_MTD_BLOCK=y
20CONFIG_MTD_NAND=y
21CONFIG_MTD_NAND_FSMC=y
15CONFIG_BLK_DEV_RAM=y 22CONFIG_BLK_DEV_RAM=y
16CONFIG_BLK_DEV_RAM_SIZE=16384 23CONFIG_BLK_DEV_RAM_SIZE=16384
24CONFIG_NETDEVICES=y
25# CONFIG_NET_VENDOR_BROADCOM is not set
26# CONFIG_NET_VENDOR_CIRRUS is not set
27# CONFIG_NET_VENDOR_FARADAY is not set
28# CONFIG_NET_VENDOR_INTEL is not set
29# CONFIG_NET_VENDOR_MICREL is not set
30# CONFIG_NET_VENDOR_NATSEMI is not set
31# CONFIG_NET_VENDOR_SEEQ is not set
32# CONFIG_NET_VENDOR_SMSC is not set
33CONFIG_STMMAC_ETH=y
34# CONFIG_WLAN is not set
17CONFIG_INPUT_FF_MEMLESS=y 35CONFIG_INPUT_FF_MEMLESS=y
18# CONFIG_INPUT_MOUSEDEV_PSAUX is not set 36# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
19# CONFIG_INPUT_KEYBOARD is not set 37# CONFIG_KEYBOARD_ATKBD is not set
38CONFIG_KEYBOARD_SPEAR=y
20# CONFIG_INPUT_MOUSE is not set 39# CONFIG_INPUT_MOUSE is not set
40# CONFIG_LEGACY_PTYS is not set
21CONFIG_SERIAL_AMBA_PL011=y 41CONFIG_SERIAL_AMBA_PL011=y
22CONFIG_SERIAL_AMBA_PL011_CONSOLE=y 42CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
23# CONFIG_LEGACY_PTYS is not set
24# CONFIG_HW_RANDOM is not set 43# CONFIG_HW_RANDOM is not set
25CONFIG_RAW_DRIVER=y 44CONFIG_RAW_DRIVER=y
26CONFIG_MAX_RAW_DEVS=8192 45CONFIG_MAX_RAW_DEVS=8192
46CONFIG_I2C=y
47CONFIG_I2C_DESIGNWARE_PLATFORM=y
48CONFIG_SPI=y
49CONFIG_SPI_PL022=y
27CONFIG_GPIO_SYSFS=y 50CONFIG_GPIO_SYSFS=y
28CONFIG_GPIO_PL061=y 51CONFIG_GPIO_PL061=y
29# CONFIG_HWMON is not set 52# CONFIG_HWMON is not set
53CONFIG_WATCHDOG=y
54CONFIG_ARM_SP805_WATCHDOG=y
55CONFIG_FB=y
56CONFIG_FB_ARMCLCD=y
30# CONFIG_HID_SUPPORT is not set 57# CONFIG_HID_SUPPORT is not set
31# CONFIG_USB_SUPPORT is not set 58CONFIG_USB=y
59# CONFIG_USB_DEVICE_CLASS is not set
60CONFIG_USB_EHCI_HCD=y
61CONFIG_USB_OHCI_HCD=y
62CONFIG_MMC=y
63CONFIG_MMC_SDHCI=y
64CONFIG_MMC_SDHCI_SPEAR=y
65CONFIG_RTC_CLASS=y
66CONFIG_DMADEVICES=y
67CONFIG_AMBA_PL08X=y
68CONFIG_DMATEST=m
32CONFIG_EXT2_FS=y 69CONFIG_EXT2_FS=y
33CONFIG_EXT2_FS_XATTR=y 70CONFIG_EXT2_FS_XATTR=y
34CONFIG_EXT2_FS_SECURITY=y 71CONFIG_EXT2_FS_SECURITY=y
@@ -39,8 +76,7 @@ CONFIG_MSDOS_FS=m
39CONFIG_VFAT_FS=m 76CONFIG_VFAT_FS=m
40CONFIG_FAT_DEFAULT_IOCHARSET="ascii" 77CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
41CONFIG_TMPFS=y 78CONFIG_TMPFS=y
42CONFIG_PARTITION_ADVANCED=y 79CONFIG_JFFS2_FS=y
43CONFIG_NLS=y
44CONFIG_NLS_DEFAULT="utf8" 80CONFIG_NLS_DEFAULT="utf8"
45CONFIG_NLS_CODEPAGE_437=y 81CONFIG_NLS_CODEPAGE_437=y
46CONFIG_NLS_ASCII=m 82CONFIG_NLS_ASCII=m
@@ -48,6 +84,4 @@ CONFIG_MAGIC_SYSRQ=y
48CONFIG_DEBUG_FS=y 84CONFIG_DEBUG_FS=y
49CONFIG_DEBUG_KERNEL=y 85CONFIG_DEBUG_KERNEL=y
50CONFIG_DEBUG_SPINLOCK=y 86CONFIG_DEBUG_SPINLOCK=y
51CONFIG_DEBUG_SPINLOCK_SLEEP=y
52CONFIG_DEBUG_INFO=y 87CONFIG_DEBUG_INFO=y
53# CONFIG_CRC32 is not set
diff --git a/arch/arm/configs/spear6xx_defconfig b/arch/arm/configs/spear6xx_defconfig
index cef2e836afd2..a2a1265f86b6 100644
--- a/arch/arm/configs/spear6xx_defconfig
+++ b/arch/arm/configs/spear6xx_defconfig
@@ -2,29 +2,60 @@ CONFIG_EXPERIMENTAL=y
2CONFIG_SYSVIPC=y 2CONFIG_SYSVIPC=y
3CONFIG_BSD_PROCESS_ACCT=y 3CONFIG_BSD_PROCESS_ACCT=y
4CONFIG_BLK_DEV_INITRD=y 4CONFIG_BLK_DEV_INITRD=y
5CONFIG_KALLSYMS_EXTRA_PASS=y
6CONFIG_MODULES=y 5CONFIG_MODULES=y
7CONFIG_MODULE_UNLOAD=y 6CONFIG_MODULE_UNLOAD=y
8CONFIG_MODVERSIONS=y 7CONFIG_MODVERSIONS=y
8CONFIG_PARTITION_ADVANCED=y
9CONFIG_PLAT_SPEAR=y 9CONFIG_PLAT_SPEAR=y
10CONFIG_ARCH_SPEAR6XX=y 10CONFIG_ARCH_SPEAR6XX=y
11CONFIG_BOARD_SPEAR600_EVB=y
12CONFIG_BINFMT_MISC=y 11CONFIG_BINFMT_MISC=y
12CONFIG_NET=y
13CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 13CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
14CONFIG_MTD=y
15CONFIG_MTD_OF_PARTS=y
16CONFIG_MTD_CHAR=y
17CONFIG_MTD_BLOCK=y
18CONFIG_MTD_NAND=y
19CONFIG_MTD_NAND_FSMC=y
14CONFIG_BLK_DEV_RAM=y 20CONFIG_BLK_DEV_RAM=y
15CONFIG_BLK_DEV_RAM_SIZE=16384 21CONFIG_BLK_DEV_RAM_SIZE=16384
22CONFIG_NETDEVICES=y
23# CONFIG_NET_VENDOR_BROADCOM is not set
24# CONFIG_NET_VENDOR_CIRRUS is not set
25# CONFIG_NET_VENDOR_FARADAY is not set
26# CONFIG_NET_VENDOR_INTEL is not set
27# CONFIG_NET_VENDOR_MICREL is not set
28# CONFIG_NET_VENDOR_NATSEMI is not set
29# CONFIG_NET_VENDOR_SEEQ is not set
30# CONFIG_NET_VENDOR_SMSC is not set
31CONFIG_STMMAC_ETH=y
32# CONFIG_WLAN is not set
16CONFIG_INPUT_FF_MEMLESS=y 33CONFIG_INPUT_FF_MEMLESS=y
17# CONFIG_INPUT_MOUSEDEV_PSAUX is not set 34# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
35# CONFIG_INPUT_KEYBOARD is not set
36# CONFIG_INPUT_MOUSE is not set
37# CONFIG_LEGACY_PTYS is not set
18CONFIG_SERIAL_AMBA_PL011=y 38CONFIG_SERIAL_AMBA_PL011=y
19CONFIG_SERIAL_AMBA_PL011_CONSOLE=y 39CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
20# CONFIG_LEGACY_PTYS is not set
21CONFIG_RAW_DRIVER=y 40CONFIG_RAW_DRIVER=y
22CONFIG_MAX_RAW_DEVS=8192 41CONFIG_MAX_RAW_DEVS=8192
42CONFIG_I2C=y
43CONFIG_I2C_DESIGNWARE_PLATFORM=y
44CONFIG_SPI=y
45CONFIG_SPI_PL022=y
23CONFIG_GPIO_SYSFS=y 46CONFIG_GPIO_SYSFS=y
24CONFIG_GPIO_PL061=y 47CONFIG_GPIO_PL061=y
25# CONFIG_HWMON is not set 48# CONFIG_HWMON is not set
49CONFIG_WATCHDOG=y
50CONFIG_ARM_SP805_WATCHDOG=y
26# CONFIG_HID_SUPPORT is not set 51# CONFIG_HID_SUPPORT is not set
27# CONFIG_USB_SUPPORT is not set 52CONFIG_USB=y
53CONFIG_USB_EHCI_HCD=y
54CONFIG_USB_OHCI_HCD=y
55CONFIG_RTC_CLASS=y
56CONFIG_DMADEVICES=y
57CONFIG_AMBA_PL08X=y
58CONFIG_DMATEST=m
28CONFIG_EXT2_FS=y 59CONFIG_EXT2_FS=y
29CONFIG_EXT2_FS_XATTR=y 60CONFIG_EXT2_FS_XATTR=y
30CONFIG_EXT2_FS_SECURITY=y 61CONFIG_EXT2_FS_SECURITY=y
@@ -35,8 +66,7 @@ CONFIG_MSDOS_FS=m
35CONFIG_VFAT_FS=m 66CONFIG_VFAT_FS=m
36CONFIG_FAT_DEFAULT_IOCHARSET="ascii" 67CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
37CONFIG_TMPFS=y 68CONFIG_TMPFS=y
38CONFIG_PARTITION_ADVANCED=y 69CONFIG_JFFS2_FS=y
39CONFIG_NLS=y
40CONFIG_NLS_DEFAULT="utf8" 70CONFIG_NLS_DEFAULT="utf8"
41CONFIG_NLS_CODEPAGE_437=y 71CONFIG_NLS_CODEPAGE_437=y
42CONFIG_NLS_ASCII=m 72CONFIG_NLS_ASCII=m
@@ -44,6 +74,4 @@ CONFIG_MAGIC_SYSRQ=y
44CONFIG_DEBUG_FS=y 74CONFIG_DEBUG_FS=y
45CONFIG_DEBUG_KERNEL=y 75CONFIG_DEBUG_KERNEL=y
46CONFIG_DEBUG_SPINLOCK=y 76CONFIG_DEBUG_SPINLOCK=y
47CONFIG_DEBUG_SPINLOCK_SLEEP=y
48CONFIG_DEBUG_INFO=y 77CONFIG_DEBUG_INFO=y
49# CONFIG_CRC32 is not set
diff --git a/arch/arm/mach-spear13xx/Kconfig b/arch/arm/mach-spear13xx/Kconfig
new file mode 100644
index 000000000000..eaadc66d96b3
--- /dev/null
+++ b/arch/arm/mach-spear13xx/Kconfig
@@ -0,0 +1,20 @@
1#
2# SPEAr13XX Machine configuration file
3#
4
5if ARCH_SPEAR13XX
6
7menu "SPEAr13xx Implementations"
8config MACH_SPEAR1310
9 bool "SPEAr1310 Machine support with Device Tree"
10 select PINCTRL_SPEAR1310
11 help
12 Supports ST SPEAr1310 machine configured via the device-tree
13
14config MACH_SPEAR1340
15 bool "SPEAr1340 Machine support with Device Tree"
16 select PINCTRL_SPEAR1340
17 help
18 Supports ST SPEAr1340 machine configured via the device-tree
19endmenu
20endif #ARCH_SPEAR13XX
diff --git a/arch/arm/mach-spear13xx/Makefile b/arch/arm/mach-spear13xx/Makefile
new file mode 100644
index 000000000000..3435ea78c15d
--- /dev/null
+++ b/arch/arm/mach-spear13xx/Makefile
@@ -0,0 +1,10 @@
1#
2# Makefile for SPEAr13XX machine series
3#
4
5obj-$(CONFIG_SMP) += headsmp.o platsmp.o
6obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
7
8obj-$(CONFIG_ARCH_SPEAR13XX) += spear13xx.o
9obj-$(CONFIG_MACH_SPEAR1310) += spear1310.o
10obj-$(CONFIG_MACH_SPEAR1340) += spear1340.o
diff --git a/arch/arm/mach-spear13xx/Makefile.boot b/arch/arm/mach-spear13xx/Makefile.boot
new file mode 100644
index 000000000000..403efd7e6d27
--- /dev/null
+++ b/arch/arm/mach-spear13xx/Makefile.boot
@@ -0,0 +1,6 @@
1zreladdr-y += 0x00008000
2params_phys-y := 0x00000100
3initrd_phys-y := 0x00800000
4
5dtb-$(CONFIG_MACH_SPEAR1310) += spear1310-evb.dtb
6dtb-$(CONFIG_MACH_SPEAR1340) += spear1340-evb.dtb
diff --git a/arch/arm/mach-spear13xx/headsmp.S b/arch/arm/mach-spear13xx/headsmp.S
new file mode 100644
index 000000000000..ed85473a047f
--- /dev/null
+++ b/arch/arm/mach-spear13xx/headsmp.S
@@ -0,0 +1,47 @@
1/*
2 * arch/arm/mach-spear13XX/headsmp.S
3 *
4 * Picked from realview
5 * Copyright (c) 2012 ST Microelectronics Limited
6 * Shiraz Hashim <shiraz.hashim@st.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/linkage.h>
14#include <linux/init.h>
15
16 __INIT
17
18/*
19 * spear13xx specific entry point for secondary CPUs. This provides
20 * a "holding pen" into which all secondary cores are held until we're
21 * ready for them to initialise.
22 */
23ENTRY(spear13xx_secondary_startup)
24 mrc p15, 0, r0, c0, c0, 5
25 and r0, r0, #15
26 adr r4, 1f
27 ldmia r4, {r5, r6}
28 sub r4, r4, r5
29 add r6, r6, r4
30pen: ldr r7, [r6]
31 cmp r7, r0
32 bne pen
33
34 /* re-enable coherency */
35 mrc p15, 0, r0, c1, c0, 1
36 orr r0, r0, #(1 << 6) | (1 << 0)
37 mcr p15, 0, r0, c1, c0, 1
38 /*
39 * we've been released from the holding pen: secondary_stack
40 * should now contain the SVC stack for this core
41 */
42 b secondary_startup
43
44 .align
451: .long .
46 .long pen_release
47ENDPROC(spear13xx_secondary_startup)
diff --git a/arch/arm/mach-spear13xx/hotplug.c b/arch/arm/mach-spear13xx/hotplug.c
new file mode 100644
index 000000000000..5c6867b46d09
--- /dev/null
+++ b/arch/arm/mach-spear13xx/hotplug.c
@@ -0,0 +1,119 @@
1/*
2 * linux/arch/arm/mach-spear13xx/hotplug.c
3 *
4 * Copyright (C) 2012 ST Microelectronics Ltd.
5 * Deepak Sikri <deepak.sikri@st.com>
6 *
7 * based upon linux/arch/arm/mach-realview/hotplug.c
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#include <linux/kernel.h>
14#include <linux/errno.h>
15#include <linux/smp.h>
16#include <asm/cacheflush.h>
17#include <asm/cp15.h>
18#include <asm/smp_plat.h>
19
20extern volatile int pen_release;
21
22static inline void cpu_enter_lowpower(void)
23{
24 unsigned int v;
25
26 flush_cache_all();
27 asm volatile(
28 " mcr p15, 0, %1, c7, c5, 0\n"
29 " dsb\n"
30 /*
31 * Turn off coherency
32 */
33 " mrc p15, 0, %0, c1, c0, 1\n"
34 " bic %0, %0, #0x20\n"
35 " mcr p15, 0, %0, c1, c0, 1\n"
36 " mrc p15, 0, %0, c1, c0, 0\n"
37 " bic %0, %0, %2\n"
38 " mcr p15, 0, %0, c1, c0, 0\n"
39 : "=&r" (v)
40 : "r" (0), "Ir" (CR_C)
41 : "cc", "memory");
42}
43
44static inline void cpu_leave_lowpower(void)
45{
46 unsigned int v;
47
48 asm volatile("mrc p15, 0, %0, c1, c0, 0\n"
49 " orr %0, %0, %1\n"
50 " mcr p15, 0, %0, c1, c0, 0\n"
51 " mrc p15, 0, %0, c1, c0, 1\n"
52 " orr %0, %0, #0x20\n"
53 " mcr p15, 0, %0, c1, c0, 1\n"
54 : "=&r" (v)
55 : "Ir" (CR_C)
56 : "cc");
57}
58
59static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
60{
61 for (;;) {
62 wfi();
63
64 if (pen_release == cpu) {
65 /*
66 * OK, proper wakeup, we're done
67 */
68 break;
69 }
70
71 /*
72 * Getting here, means that we have come out of WFI without
73 * having been woken up - this shouldn't happen
74 *
75 * Just note it happening - when we're woken, we can report
76 * its occurrence.
77 */
78 (*spurious)++;
79 }
80}
81
82int platform_cpu_kill(unsigned int cpu)
83{
84 return 1;
85}
86
87/*
88 * platform-specific code to shutdown a CPU
89 *
90 * Called with IRQs disabled
91 */
92void __cpuinit platform_cpu_die(unsigned int cpu)
93{
94 int spurious = 0;
95
96 /*
97 * we're ready for shutdown now, so do it
98 */
99 cpu_enter_lowpower();
100 platform_do_lowpower(cpu, &spurious);
101
102 /*
103 * bring this CPU back into the world of cache
104 * coherency, and then restore interrupts
105 */
106 cpu_leave_lowpower();
107
108 if (spurious)
109 pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
110}
111
112int platform_cpu_disable(unsigned int cpu)
113{
114 /*
115 * we don't allow CPU 0 to be shutdown (it is still too special
116 * e.g. clock tick interrupts)
117 */
118 return cpu == 0 ? -EPERM : 0;
119}
diff --git a/arch/arm/mach-spear13xx/include/mach/debug-macro.S b/arch/arm/mach-spear13xx/include/mach/debug-macro.S
new file mode 100644
index 000000000000..ea1564609bd4
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/debug-macro.S
@@ -0,0 +1,14 @@
1/*
2 * arch/arm/mach-spear13xx/include/mach/debug-macro.S
3 *
4 * Debugging macro include header spear13xx machine family
5 *
6 * Copyright (C) 2012 ST Microelectronics
7 * Viresh Kumar <viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <plat/debug-macro.S>
diff --git a/arch/arm/mach-spear13xx/include/mach/dma.h b/arch/arm/mach-spear13xx/include/mach/dma.h
new file mode 100644
index 000000000000..383ab04dc6c9
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/dma.h
@@ -0,0 +1,128 @@
1/*
2 * arch/arm/mach-spear13xx/include/mach/dma.h
3 *
4 * DMA information for SPEAr13xx machine family
5 *
6 * Copyright (C) 2012 ST Microelectronics
7 * Viresh Kumar <viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __MACH_DMA_H
15#define __MACH_DMA_H
16
17/* request id of all the peripherals */
18enum dma_master_info {
19 /* Accessible from only one master */
20 DMA_MASTER_MCIF = 0,
21 DMA_MASTER_FSMC = 1,
22 /* Accessible from both 0 & 1 */
23 DMA_MASTER_MEMORY = 0,
24 DMA_MASTER_ADC = 0,
25 DMA_MASTER_UART0 = 0,
26 DMA_MASTER_SSP0 = 0,
27 DMA_MASTER_I2C0 = 0,
28
29#ifdef CONFIG_MACH_SPEAR1310
30 /* Accessible from only one master */
31 SPEAR1310_DMA_MASTER_JPEG = 1,
32
33 /* Accessible from both 0 & 1 */
34 SPEAR1310_DMA_MASTER_I2S = 0,
35 SPEAR1310_DMA_MASTER_UART1 = 0,
36 SPEAR1310_DMA_MASTER_UART2 = 0,
37 SPEAR1310_DMA_MASTER_UART3 = 0,
38 SPEAR1310_DMA_MASTER_UART4 = 0,
39 SPEAR1310_DMA_MASTER_UART5 = 0,
40 SPEAR1310_DMA_MASTER_I2C1 = 0,
41 SPEAR1310_DMA_MASTER_I2C2 = 0,
42 SPEAR1310_DMA_MASTER_I2C3 = 0,
43 SPEAR1310_DMA_MASTER_I2C4 = 0,
44 SPEAR1310_DMA_MASTER_I2C5 = 0,
45 SPEAR1310_DMA_MASTER_I2C6 = 0,
46 SPEAR1310_DMA_MASTER_I2C7 = 0,
47 SPEAR1310_DMA_MASTER_SSP1 = 0,
48#endif
49
50#ifdef CONFIG_MACH_SPEAR1340
51 /* Accessible from only one master */
52 SPEAR1340_DMA_MASTER_I2S_PLAY = 1,
53 SPEAR1340_DMA_MASTER_I2S_REC = 1,
54 SPEAR1340_DMA_MASTER_I2C1 = 1,
55 SPEAR1340_DMA_MASTER_UART1 = 1,
56
57 /* following are accessible from both master 0 & 1 */
58 SPEAR1340_DMA_MASTER_SPDIF = 0,
59 SPEAR1340_DMA_MASTER_CAM = 1,
60 SPEAR1340_DMA_MASTER_VIDEO_IN = 0,
61 SPEAR1340_DMA_MASTER_MALI = 0,
62#endif
63};
64
65enum request_id {
66 DMA_REQ_ADC = 0,
67 DMA_REQ_SSP0_TX = 4,
68 DMA_REQ_SSP0_RX = 5,
69 DMA_REQ_UART0_TX = 6,
70 DMA_REQ_UART0_RX = 7,
71 DMA_REQ_I2C0_TX = 8,
72 DMA_REQ_I2C0_RX = 9,
73
74#ifdef CONFIG_MACH_SPEAR1310
75 SPEAR1310_DMA_REQ_FROM_JPEG = 2,
76 SPEAR1310_DMA_REQ_TO_JPEG = 3,
77 SPEAR1310_DMA_REQ_I2S_TX = 10,
78 SPEAR1310_DMA_REQ_I2S_RX = 11,
79
80 SPEAR1310_DMA_REQ_I2C1_RX = 0,
81 SPEAR1310_DMA_REQ_I2C1_TX = 1,
82 SPEAR1310_DMA_REQ_I2C2_RX = 2,
83 SPEAR1310_DMA_REQ_I2C2_TX = 3,
84 SPEAR1310_DMA_REQ_I2C3_RX = 4,
85 SPEAR1310_DMA_REQ_I2C3_TX = 5,
86 SPEAR1310_DMA_REQ_I2C4_RX = 6,
87 SPEAR1310_DMA_REQ_I2C4_TX = 7,
88 SPEAR1310_DMA_REQ_I2C5_RX = 8,
89 SPEAR1310_DMA_REQ_I2C5_TX = 9,
90 SPEAR1310_DMA_REQ_I2C6_RX = 10,
91 SPEAR1310_DMA_REQ_I2C6_TX = 11,
92 SPEAR1310_DMA_REQ_UART1_RX = 12,
93 SPEAR1310_DMA_REQ_UART1_TX = 13,
94 SPEAR1310_DMA_REQ_UART2_RX = 14,
95 SPEAR1310_DMA_REQ_UART2_TX = 15,
96 SPEAR1310_DMA_REQ_UART5_RX = 16,
97 SPEAR1310_DMA_REQ_UART5_TX = 17,
98 SPEAR1310_DMA_REQ_SSP1_RX = 18,
99 SPEAR1310_DMA_REQ_SSP1_TX = 19,
100 SPEAR1310_DMA_REQ_I2C7_RX = 20,
101 SPEAR1310_DMA_REQ_I2C7_TX = 21,
102 SPEAR1310_DMA_REQ_UART3_RX = 28,
103 SPEAR1310_DMA_REQ_UART3_TX = 29,
104 SPEAR1310_DMA_REQ_UART4_RX = 30,
105 SPEAR1310_DMA_REQ_UART4_TX = 31,
106#endif
107
108#ifdef CONFIG_MACH_SPEAR1340
109 SPEAR1340_DMA_REQ_SPDIF_TX = 2,
110 SPEAR1340_DMA_REQ_SPDIF_RX = 3,
111 SPEAR1340_DMA_REQ_I2S_TX = 10,
112 SPEAR1340_DMA_REQ_I2S_RX = 11,
113 SPEAR1340_DMA_REQ_UART1_TX = 12,
114 SPEAR1340_DMA_REQ_UART1_RX = 13,
115 SPEAR1340_DMA_REQ_I2C1_TX = 14,
116 SPEAR1340_DMA_REQ_I2C1_RX = 15,
117 SPEAR1340_DMA_REQ_CAM0_EVEN = 0,
118 SPEAR1340_DMA_REQ_CAM0_ODD = 1,
119 SPEAR1340_DMA_REQ_CAM1_EVEN = 2,
120 SPEAR1340_DMA_REQ_CAM1_ODD = 3,
121 SPEAR1340_DMA_REQ_CAM2_EVEN = 4,
122 SPEAR1340_DMA_REQ_CAM2_ODD = 5,
123 SPEAR1340_DMA_REQ_CAM3_EVEN = 6,
124 SPEAR1340_DMA_REQ_CAM3_ODD = 7,
125#endif
126};
127
128#endif /* __MACH_DMA_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/generic.h b/arch/arm/mach-spear13xx/include/mach/generic.h
new file mode 100644
index 000000000000..6d8c45b9f298
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/generic.h
@@ -0,0 +1,49 @@
1/*
2 * arch/arm/mach-spear13xx/include/mach/generic.h
3 *
4 * spear13xx machine family generic header file
5 *
6 * Copyright (C) 2012 ST Microelectronics
7 * Viresh Kumar <viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __MACH_GENERIC_H
15#define __MACH_GENERIC_H
16
17#include <linux/dmaengine.h>
18#include <asm/mach/time.h>
19
20/* Add spear13xx structure declarations here */
21extern struct sys_timer spear13xx_timer;
22extern struct pl022_ssp_controller pl022_plat_data;
23extern struct dw_dma_platform_data dmac_plat_data;
24extern struct dw_dma_slave cf_dma_priv;
25extern struct dw_dma_slave nand_read_dma_priv;
26extern struct dw_dma_slave nand_write_dma_priv;
27
28/* Add spear13xx family function declarations here */
29void __init spear_setup_of_timer(void);
30void __init spear13xx_map_io(void);
31void __init spear13xx_dt_init_irq(void);
32void __init spear13xx_l2x0_init(void);
33bool dw_dma_filter(struct dma_chan *chan, void *slave);
34void spear_restart(char, const char *);
35void spear13xx_secondary_startup(void);
36
37#ifdef CONFIG_MACH_SPEAR1310
38void __init spear1310_clk_init(void);
39#else
40static inline void spear1310_clk_init(void) {}
41#endif
42
43#ifdef CONFIG_MACH_SPEAR1340
44void __init spear1340_clk_init(void);
45#else
46static inline void spear1340_clk_init(void) {}
47#endif
48
49#endif /* __MACH_GENERIC_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/gpio.h b/arch/arm/mach-spear13xx/include/mach/gpio.h
new file mode 100644
index 000000000000..cd6f4f86a56b
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/gpio.h
@@ -0,0 +1,19 @@
1/*
2 * arch/arm/mach-spear13xx/include/mach/gpio.h
3 *
4 * GPIO macros for SPEAr13xx machine family
5 *
6 * Copyright (C) 2012 ST Microelectronics
7 * Viresh Kumar <viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __MACH_GPIO_H
15#define __MACH_GPIO_H
16
17#include <plat/gpio.h>
18
19#endif /* __MACH_GPIO_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/hardware.h b/arch/arm/mach-spear13xx/include/mach/hardware.h
new file mode 100644
index 000000000000..40a8c178f10d
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/hardware.h
@@ -0,0 +1 @@
/* empty */
diff --git a/arch/arm/mach-spear13xx/include/mach/irqs.h b/arch/arm/mach-spear13xx/include/mach/irqs.h
new file mode 100644
index 000000000000..f542a24aa5f2
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/irqs.h
@@ -0,0 +1,20 @@
1/*
2 * arch/arm/mach-spear13xx/include/mach/irqs.h
3 *
4 * IRQ helper macros for spear13xx machine family
5 *
6 * Copyright (C) 2012 ST Microelectronics
7 * Viresh Kumar <viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __MACH_IRQS_H
15#define __MACH_IRQS_H
16
17#define IRQ_GIC_END 160
18#define NR_IRQS IRQ_GIC_END
19
20#endif /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/spear.h b/arch/arm/mach-spear13xx/include/mach/spear.h
new file mode 100644
index 000000000000..30c57ef72686
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/spear.h
@@ -0,0 +1,62 @@
1/*
2 * arch/arm/mach-spear13xx/include/mach/spear.h
3 *
4 * spear13xx Machine family specific definition
5 *
6 * Copyright (C) 2012 ST Microelectronics
7 * Viresh Kumar <viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __MACH_SPEAR13XX_H
15#define __MACH_SPEAR13XX_H
16
17#include <asm/memory.h>
18
19#define PERIP_GRP2_BASE UL(0xB3000000)
20#define VA_PERIP_GRP2_BASE UL(0xFE000000)
21#define MCIF_SDHCI_BASE UL(0xB3000000)
22#define SYSRAM0_BASE UL(0xB3800000)
23#define VA_SYSRAM0_BASE UL(0xFE800000)
24#define SYS_LOCATION (VA_SYSRAM0_BASE + 0x600)
25
26#define PERIP_GRP1_BASE UL(0xE0000000)
27#define VA_PERIP_GRP1_BASE UL(0xFD000000)
28#define UART_BASE UL(0xE0000000)
29#define VA_UART_BASE UL(0xFD000000)
30#define SSP_BASE UL(0xE0100000)
31#define MISC_BASE UL(0xE0700000)
32#define VA_MISC_BASE IOMEM(UL(0xFD700000))
33
34#define A9SM_AND_MPMC_BASE UL(0xEC000000)
35#define VA_A9SM_AND_MPMC_BASE UL(0xFC000000)
36
37/* A9SM peripheral offsets */
38#define A9SM_PERIP_BASE UL(0xEC800000)
39#define VA_A9SM_PERIP_BASE UL(0xFC800000)
40#define VA_SCU_BASE (VA_A9SM_PERIP_BASE + 0x00)
41
42#define L2CC_BASE UL(0xED000000)
43#define VA_L2CC_BASE IOMEM(UL(0xFB000000))
44
45/* others */
46#define DMAC0_BASE UL(0xEA800000)
47#define DMAC1_BASE UL(0xEB000000)
48#define MCIF_CF_BASE UL(0xB2800000)
49
50/* Devices present in SPEAr1310 */
51#ifdef CONFIG_MACH_SPEAR1310
52#define SPEAR1310_RAS_GRP1_BASE UL(0xD8000000)
53#define VA_SPEAR1310_RAS_GRP1_BASE UL(0xFA000000)
54#define SPEAR1310_RAS_BASE UL(0xD8400000)
55#define VA_SPEAR1310_RAS_BASE IOMEM(UL(0xFA400000))
56#endif /* CONFIG_MACH_SPEAR1310 */
57
58/* Debug uart for linux, will be used for debug and uncompress messages */
59#define SPEAR_DBG_UART_BASE UART_BASE
60#define VA_SPEAR_DBG_UART_BASE VA_UART_BASE
61
62#endif /* __MACH_SPEAR13XX_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/spear1310_misc_regs.h b/arch/arm/mach-spear13xx/include/mach/spear1310_misc_regs.h
new file mode 100644
index 000000000000..e69de29bb2d1
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/spear1310_misc_regs.h
diff --git a/arch/arm/mach-spear13xx/include/mach/spear1340_misc_regs.h b/arch/arm/mach-spear13xx/include/mach/spear1340_misc_regs.h
new file mode 100644
index 000000000000..e69de29bb2d1
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/spear1340_misc_regs.h
diff --git a/arch/arm/mach-spear13xx/include/mach/timex.h b/arch/arm/mach-spear13xx/include/mach/timex.h
new file mode 100644
index 000000000000..31af3e8d976e
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/timex.h
@@ -0,0 +1,19 @@
1/*
2 * arch/arm/mach-spear3xx/include/mach/timex.h
3 *
4 * SPEAr3XX machine family specific timex definitions
5 *
6 * Copyright (C) 2012 ST Microelectronics
7 * Viresh Kumar <viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __MACH_TIMEX_H
15#define __MACH_TIMEX_H
16
17#include <plat/timex.h>
18
19#endif /* __MACH_TIMEX_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/uncompress.h b/arch/arm/mach-spear13xx/include/mach/uncompress.h
new file mode 100644
index 000000000000..c7840896ae6e
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/uncompress.h
@@ -0,0 +1,19 @@
1/*
2 * arch/arm/mach-spear13xx/include/mach/uncompress.h
3 *
4 * Serial port stubs for kernel decompress status messages
5 *
6 * Copyright (C) 2012 ST Microelectronics
7 * Viresh Kumar <viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __MACH_UNCOMPRESS_H
15#define __MACH_UNCOMPRESS_H
16
17#include <plat/uncompress.h>
18
19#endif /* __MACH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-spear13xx/platsmp.c b/arch/arm/mach-spear13xx/platsmp.c
new file mode 100644
index 000000000000..f5d07f2663d7
--- /dev/null
+++ b/arch/arm/mach-spear13xx/platsmp.c
@@ -0,0 +1,127 @@
1/*
2 * arch/arm/mach-spear13xx/platsmp.c
3 *
4 * based upon linux/arch/arm/mach-realview/platsmp.c
5 *
6 * Copyright (C) 2012 ST Microelectronics Ltd.
7 * Shiraz Hashim <shiraz.hashim@st.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/delay.h>
15#include <linux/jiffies.h>
16#include <linux/io.h>
17#include <linux/smp.h>
18#include <asm/cacheflush.h>
19#include <asm/hardware/gic.h>
20#include <asm/smp_scu.h>
21#include <mach/spear.h>
22
23/*
24 * control for which core is the next to come out of the secondary
25 * boot "holding pen"
26 */
27volatile int __cpuinitdata pen_release = -1;
28static DEFINE_SPINLOCK(boot_lock);
29
30static void __iomem *scu_base = IOMEM(VA_SCU_BASE);
31extern void spear13xx_secondary_startup(void);
32
33void __cpuinit platform_secondary_init(unsigned int cpu)
34{
35 /*
36 * if any interrupts are already enabled for the primary
37 * core (e.g. timer irq), then they will not have been enabled
38 * for us: do so
39 */
40 gic_secondary_init(0);
41
42 /*
43 * let the primary processor know we're out of the
44 * pen, then head off into the C entry point
45 */
46 pen_release = -1;
47 smp_wmb();
48
49 /*
50 * Synchronise with the boot thread.
51 */
52 spin_lock(&boot_lock);
53 spin_unlock(&boot_lock);
54}
55
56int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
57{
58 unsigned long timeout;
59
60 /*
61 * set synchronisation state between this boot processor
62 * and the secondary one
63 */
64 spin_lock(&boot_lock);
65
66 /*
67 * The secondary processor is waiting to be released from
68 * the holding pen - release it, then wait for it to flag
69 * that it has been released by resetting pen_release.
70 *
71 * Note that "pen_release" is the hardware CPU ID, whereas
72 * "cpu" is Linux's internal ID.
73 */
74 pen_release = cpu;
75 flush_cache_all();
76 outer_flush_all();
77
78 timeout = jiffies + (1 * HZ);
79 while (time_before(jiffies, timeout)) {
80 smp_rmb();
81 if (pen_release == -1)
82 break;
83
84 udelay(10);
85 }
86
87 /*
88 * now the secondary core is starting up let it run its
89 * calibrations, then wait for it to finish
90 */
91 spin_unlock(&boot_lock);
92
93 return pen_release != -1 ? -ENOSYS : 0;
94}
95
96/*
97 * Initialise the CPU possible map early - this describes the CPUs
98 * which may be present or become present in the system.
99 */
100void __init smp_init_cpus(void)
101{
102 unsigned int i, ncores = scu_get_core_count(scu_base);
103
104 if (ncores > nr_cpu_ids) {
105 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
106 ncores, nr_cpu_ids);
107 ncores = nr_cpu_ids;
108 }
109
110 for (i = 0; i < ncores; i++)
111 set_cpu_possible(i, true);
112
113 set_smp_cross_call(gic_raise_softirq);
114}
115
116void __init platform_smp_prepare_cpus(unsigned int max_cpus)
117{
118
119 scu_enable(scu_base);
120
121 /*
122 * Write the address of secondary startup into the system-wide location
123 * (presently it is in SRAM). The BootMonitor waits until it receives a
124 * soft interrupt, and then the secondary CPU branches to this address.
125 */
126 __raw_writel(virt_to_phys(spear13xx_secondary_startup), SYS_LOCATION);
127}
diff --git a/arch/arm/mach-spear13xx/spear1310.c b/arch/arm/mach-spear13xx/spear1310.c
new file mode 100644
index 000000000000..fefd15b2f380
--- /dev/null
+++ b/arch/arm/mach-spear13xx/spear1310.c
@@ -0,0 +1,88 @@
1/*
2 * arch/arm/mach-spear13xx/spear1310.c
3 *
4 * SPEAr1310 machine source file
5 *
6 * Copyright (C) 2012 ST Microelectronics
7 * Viresh Kumar <viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#define pr_fmt(fmt) "SPEAr1310: " fmt
15
16#include <linux/amba/pl022.h>
17#include <linux/of_platform.h>
18#include <asm/hardware/gic.h>
19#include <asm/mach/arch.h>
20#include <asm/mach/map.h>
21#include <mach/generic.h>
22#include <mach/spear.h>
23
24/* Base addresses */
25#define SPEAR1310_SSP1_BASE UL(0x5D400000)
26#define SPEAR1310_SATA0_BASE UL(0xB1000000)
27#define SPEAR1310_SATA1_BASE UL(0xB1800000)
28#define SPEAR1310_SATA2_BASE UL(0xB4000000)
29
30/* ssp device registration */
31static struct pl022_ssp_controller ssp1_plat_data = {
32 .bus_id = 0,
33 .enable_dma = 0,
34 .num_chipselect = 3,
35};
36
37/* Add SPEAr1310 auxdata to pass platform data */
38static struct of_dev_auxdata spear1310_auxdata_lookup[] __initdata = {
39 OF_DEV_AUXDATA("arasan,cf-spear1340", MCIF_CF_BASE, NULL, &cf_dma_priv),
40 OF_DEV_AUXDATA("snps,dma-spear1340", DMAC0_BASE, NULL, &dmac_plat_data),
41 OF_DEV_AUXDATA("snps,dma-spear1340", DMAC1_BASE, NULL, &dmac_plat_data),
42 OF_DEV_AUXDATA("arm,pl022", SSP_BASE, NULL, &pl022_plat_data),
43
44 OF_DEV_AUXDATA("arm,pl022", SPEAR1310_SSP1_BASE, NULL, &ssp1_plat_data),
45 {}
46};
47
48static void __init spear1310_dt_init(void)
49{
50 of_platform_populate(NULL, of_default_bus_match_table,
51 spear1310_auxdata_lookup, NULL);
52}
53
54static const char * const spear1310_dt_board_compat[] = {
55 "st,spear1310",
56 "st,spear1310-evb",
57 NULL,
58};
59
60/*
61 * Following will create 16MB static virtual/physical mappings
62 * PHYSICAL VIRTUAL
63 * 0xD8000000 0xFA000000
64 */
65struct map_desc spear1310_io_desc[] __initdata = {
66 {
67 .virtual = VA_SPEAR1310_RAS_GRP1_BASE,
68 .pfn = __phys_to_pfn(SPEAR1310_RAS_GRP1_BASE),
69 .length = SZ_16M,
70 .type = MT_DEVICE
71 },
72};
73
74static void __init spear1310_map_io(void)
75{
76 iotable_init(spear1310_io_desc, ARRAY_SIZE(spear1310_io_desc));
77 spear13xx_map_io();
78}
79
80DT_MACHINE_START(SPEAR1310_DT, "ST SPEAr1310 SoC with Flattened Device Tree")
81 .map_io = spear1310_map_io,
82 .init_irq = spear13xx_dt_init_irq,
83 .handle_irq = gic_handle_irq,
84 .timer = &spear13xx_timer,
85 .init_machine = spear1310_dt_init,
86 .restart = spear_restart,
87 .dt_compat = spear1310_dt_board_compat,
88MACHINE_END
diff --git a/arch/arm/mach-spear13xx/spear1340.c b/arch/arm/mach-spear13xx/spear1340.c
new file mode 100644
index 000000000000..ee38cbc56869
--- /dev/null
+++ b/arch/arm/mach-spear13xx/spear1340.c
@@ -0,0 +1,192 @@
1/*
2 * arch/arm/mach-spear13xx/spear1340.c
3 *
4 * SPEAr1340 machine source file
5 *
6 * Copyright (C) 2012 ST Microelectronics
7 * Viresh Kumar <viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#define pr_fmt(fmt) "SPEAr1340: " fmt
15
16#include <linux/ahci_platform.h>
17#include <linux/amba/serial.h>
18#include <linux/delay.h>
19#include <linux/dw_dmac.h>
20#include <linux/of_platform.h>
21#include <asm/hardware/gic.h>
22#include <asm/mach/arch.h>
23#include <mach/dma.h>
24#include <mach/generic.h>
25#include <mach/spear.h>
26
27/* Base addresses */
28#define SPEAR1340_SATA_BASE UL(0xB1000000)
29#define SPEAR1340_UART1_BASE UL(0xB4100000)
30
31/* Power Management Registers */
32#define SPEAR1340_PCM_CFG (VA_MISC_BASE + 0x100)
33#define SPEAR1340_PCM_WKUP_CFG (VA_MISC_BASE + 0x104)
34#define SPEAR1340_SWITCH_CTR (VA_MISC_BASE + 0x108)
35
36#define SPEAR1340_PERIP1_SW_RST (VA_MISC_BASE + 0x318)
37#define SPEAR1340_PERIP2_SW_RST (VA_MISC_BASE + 0x31C)
38#define SPEAR1340_PERIP3_SW_RST (VA_MISC_BASE + 0x320)
39
40/* PCIE - SATA configuration registers */
41#define SPEAR1340_PCIE_SATA_CFG (VA_MISC_BASE + 0x424)
42 /* PCIE CFG MASks */
43 #define SPEAR1340_PCIE_CFG_DEVICE_PRESENT (1 << 11)
44 #define SPEAR1340_PCIE_CFG_POWERUP_RESET (1 << 10)
45 #define SPEAR1340_PCIE_CFG_CORE_CLK_EN (1 << 9)
46 #define SPEAR1340_PCIE_CFG_AUX_CLK_EN (1 << 8)
47 #define SPEAR1340_SATA_CFG_TX_CLK_EN (1 << 4)
48 #define SPEAR1340_SATA_CFG_RX_CLK_EN (1 << 3)
49 #define SPEAR1340_SATA_CFG_POWERUP_RESET (1 << 2)
50 #define SPEAR1340_SATA_CFG_PM_CLK_EN (1 << 1)
51 #define SPEAR1340_PCIE_SATA_SEL_PCIE (0)
52 #define SPEAR1340_PCIE_SATA_SEL_SATA (1)
53 #define SPEAR1340_SATA_PCIE_CFG_MASK 0xF1F
54 #define SPEAR1340_PCIE_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_PCIE | \
55 SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
56 SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
57 SPEAR1340_PCIE_CFG_POWERUP_RESET | \
58 SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
59 #define SPEAR1340_SATA_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_SATA | \
60 SPEAR1340_SATA_CFG_PM_CLK_EN | \
61 SPEAR1340_SATA_CFG_POWERUP_RESET | \
62 SPEAR1340_SATA_CFG_RX_CLK_EN | \
63 SPEAR1340_SATA_CFG_TX_CLK_EN)
64
65#define SPEAR1340_PCIE_MIPHY_CFG (VA_MISC_BASE + 0x428)
66 #define SPEAR1340_MIPHY_OSC_BYPASS_EXT (1 << 31)
67 #define SPEAR1340_MIPHY_CLK_REF_DIV2 (1 << 27)
68 #define SPEAR1340_MIPHY_CLK_REF_DIV4 (2 << 27)
69 #define SPEAR1340_MIPHY_CLK_REF_DIV8 (3 << 27)
70 #define SPEAR1340_MIPHY_PLL_RATIO_TOP(x) (x << 0)
71 #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
72 (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
73 SPEAR1340_MIPHY_CLK_REF_DIV2 | \
74 SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
75 #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
76 (SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
77 #define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
78 (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
79 SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
80
81static struct dw_dma_slave uart1_dma_param[] = {
82 {
83 /* Tx */
84 .cfg_hi = DWC_CFGH_DST_PER(SPEAR1340_DMA_REQ_UART1_TX),
85 .cfg_lo = 0,
86 .src_master = DMA_MASTER_MEMORY,
87 .dst_master = SPEAR1340_DMA_MASTER_UART1,
88 }, {
89 /* Rx */
90 .cfg_hi = DWC_CFGH_SRC_PER(SPEAR1340_DMA_REQ_UART1_RX),
91 .cfg_lo = 0,
92 .src_master = SPEAR1340_DMA_MASTER_UART1,
93 .dst_master = DMA_MASTER_MEMORY,
94 }
95};
96
97static struct amba_pl011_data uart1_data = {
98 .dma_filter = dw_dma_filter,
99 .dma_tx_param = &uart1_dma_param[0],
100 .dma_rx_param = &uart1_dma_param[1],
101};
102
103/* SATA device registration */
104static int sata_miphy_init(struct device *dev, void __iomem *addr)
105{
106 writel(SPEAR1340_SATA_CFG_VAL, SPEAR1340_PCIE_SATA_CFG);
107 writel(SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK,
108 SPEAR1340_PCIE_MIPHY_CFG);
109 /* Switch on sata power domain */
110 writel((readl(SPEAR1340_PCM_CFG) | (0x800)), SPEAR1340_PCM_CFG);
111 msleep(20);
112 /* Disable PCIE SATA Controller reset */
113 writel((readl(SPEAR1340_PERIP1_SW_RST) & (~0x1000)),
114 SPEAR1340_PERIP1_SW_RST);
115 msleep(20);
116
117 return 0;
118}
119
120void sata_miphy_exit(struct device *dev)
121{
122 writel(0, SPEAR1340_PCIE_SATA_CFG);
123 writel(0, SPEAR1340_PCIE_MIPHY_CFG);
124
125 /* Enable PCIE SATA Controller reset */
126 writel((readl(SPEAR1340_PERIP1_SW_RST) | (0x1000)),
127 SPEAR1340_PERIP1_SW_RST);
128 msleep(20);
129 /* Switch off sata power domain */
130 writel((readl(SPEAR1340_PCM_CFG) & (~0x800)), SPEAR1340_PCM_CFG);
131 msleep(20);
132}
133
134int sata_suspend(struct device *dev)
135{
136 if (dev->power.power_state.event == PM_EVENT_FREEZE)
137 return 0;
138
139 sata_miphy_exit(dev);
140
141 return 0;
142}
143
144int sata_resume(struct device *dev)
145{
146 if (dev->power.power_state.event == PM_EVENT_THAW)
147 return 0;
148
149 return sata_miphy_init(dev, NULL);
150}
151
152static struct ahci_platform_data sata_pdata = {
153 .init = sata_miphy_init,
154 .exit = sata_miphy_exit,
155 .suspend = sata_suspend,
156 .resume = sata_resume,
157};
158
159/* Add SPEAr1340 auxdata to pass platform data */
160static struct of_dev_auxdata spear1340_auxdata_lookup[] __initdata = {
161 OF_DEV_AUXDATA("arasan,cf-spear1340", MCIF_CF_BASE, NULL, &cf_dma_priv),
162 OF_DEV_AUXDATA("snps,dma-spear1340", DMAC0_BASE, NULL, &dmac_plat_data),
163 OF_DEV_AUXDATA("snps,dma-spear1340", DMAC1_BASE, NULL, &dmac_plat_data),
164 OF_DEV_AUXDATA("arm,pl022", SSP_BASE, NULL, &pl022_plat_data),
165
166 OF_DEV_AUXDATA("snps,spear-ahci", SPEAR1340_SATA_BASE, NULL,
167 &sata_pdata),
168 OF_DEV_AUXDATA("arm,pl011", SPEAR1340_UART1_BASE, NULL, &uart1_data),
169 {}
170};
171
172static void __init spear1340_dt_init(void)
173{
174 of_platform_populate(NULL, of_default_bus_match_table,
175 spear1340_auxdata_lookup, NULL);
176}
177
178static const char * const spear1340_dt_board_compat[] = {
179 "st,spear1340",
180 "st,spear1340-evb",
181 NULL,
182};
183
184DT_MACHINE_START(SPEAR1340_DT, "ST SPEAr1340 SoC with Flattened Device Tree")
185 .map_io = spear13xx_map_io,
186 .init_irq = spear13xx_dt_init_irq,
187 .handle_irq = gic_handle_irq,
188 .timer = &spear13xx_timer,
189 .init_machine = spear1340_dt_init,
190 .restart = spear_restart,
191 .dt_compat = spear1340_dt_board_compat,
192MACHINE_END
diff --git a/arch/arm/mach-spear13xx/spear13xx.c b/arch/arm/mach-spear13xx/spear13xx.c
new file mode 100644
index 000000000000..50b349ae863d
--- /dev/null
+++ b/arch/arm/mach-spear13xx/spear13xx.c
@@ -0,0 +1,197 @@
1/*
2 * arch/arm/mach-spear13xx/spear13xx.c
3 *
4 * SPEAr13XX machines common source file
5 *
6 * Copyright (C) 2012 ST Microelectronics
7 * Viresh Kumar <viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#define pr_fmt(fmt) "SPEAr13xx: " fmt
15
16#include <linux/amba/pl022.h>
17#include <linux/clk.h>
18#include <linux/dw_dmac.h>
19#include <linux/err.h>
20#include <linux/of_irq.h>
21#include <asm/hardware/cache-l2x0.h>
22#include <asm/hardware/gic.h>
23#include <asm/mach/map.h>
24#include <asm/smp_twd.h>
25#include <mach/dma.h>
26#include <mach/generic.h>
27#include <mach/spear.h>
28
29/* common dw_dma filter routine to be used by peripherals */
30bool dw_dma_filter(struct dma_chan *chan, void *slave)
31{
32 struct dw_dma_slave *dws = (struct dw_dma_slave *)slave;
33
34 if (chan->device->dev == dws->dma_dev) {
35 chan->private = slave;
36 return true;
37 } else {
38 return false;
39 }
40}
41
42/* ssp device registration */
43static struct dw_dma_slave ssp_dma_param[] = {
44 {
45 /* Tx */
46 .cfg_hi = DWC_CFGH_DST_PER(DMA_REQ_SSP0_TX),
47 .cfg_lo = 0,
48 .src_master = DMA_MASTER_MEMORY,
49 .dst_master = DMA_MASTER_SSP0,
50 }, {
51 /* Rx */
52 .cfg_hi = DWC_CFGH_SRC_PER(DMA_REQ_SSP0_RX),
53 .cfg_lo = 0,
54 .src_master = DMA_MASTER_SSP0,
55 .dst_master = DMA_MASTER_MEMORY,
56 }
57};
58
59struct pl022_ssp_controller pl022_plat_data = {
60 .bus_id = 0,
61 .enable_dma = 1,
62 .dma_filter = dw_dma_filter,
63 .dma_rx_param = &ssp_dma_param[1],
64 .dma_tx_param = &ssp_dma_param[0],
65 .num_chipselect = 3,
66};
67
68/* CF device registration */
69struct dw_dma_slave cf_dma_priv = {
70 .cfg_hi = 0,
71 .cfg_lo = 0,
72 .src_master = 0,
73 .dst_master = 0,
74};
75
76/* dmac device registeration */
77struct dw_dma_platform_data dmac_plat_data = {
78 .nr_channels = 8,
79 .chan_allocation_order = CHAN_ALLOCATION_DESCENDING,
80 .chan_priority = CHAN_PRIORITY_DESCENDING,
81};
82
83void __init spear13xx_l2x0_init(void)
84{
85 /*
86 * 512KB (64KB/way), 8-way associativity, parity supported
87 *
88 * FIXME: 9th bit, of Auxillary Controller register must be set
89 * for some spear13xx devices for stable L2 operation.
90 *
91 * Enable Early BRESP, L2 prefetch for Instruction and Data,
92 * write alloc and 'Full line of zero' options
93 *
94 */
95
96 writel_relaxed(0x06, VA_L2CC_BASE + L2X0_PREFETCH_CTRL);
97
98 /*
99 * Program following latencies in order to make
100 * SPEAr1340 work at 600 MHz
101 */
102 writel_relaxed(0x221, VA_L2CC_BASE + L2X0_TAG_LATENCY_CTRL);
103 writel_relaxed(0x441, VA_L2CC_BASE + L2X0_DATA_LATENCY_CTRL);
104 l2x0_init(VA_L2CC_BASE, 0x70A60001, 0xfe00ffff);
105}
106
107/*
108 * Following will create 16MB static virtual/physical mappings
109 * PHYSICAL VIRTUAL
110 * 0xB3000000 0xFE000000
111 * 0xE0000000 0xFD000000
112 * 0xEC000000 0xFC000000
113 * 0xED000000 0xFB000000
114 */
115struct map_desc spear13xx_io_desc[] __initdata = {
116 {
117 .virtual = VA_PERIP_GRP2_BASE,
118 .pfn = __phys_to_pfn(PERIP_GRP2_BASE),
119 .length = SZ_16M,
120 .type = MT_DEVICE
121 }, {
122 .virtual = VA_PERIP_GRP1_BASE,
123 .pfn = __phys_to_pfn(PERIP_GRP1_BASE),
124 .length = SZ_16M,
125 .type = MT_DEVICE
126 }, {
127 .virtual = VA_A9SM_AND_MPMC_BASE,
128 .pfn = __phys_to_pfn(A9SM_AND_MPMC_BASE),
129 .length = SZ_16M,
130 .type = MT_DEVICE
131 }, {
132 .virtual = (unsigned long)VA_L2CC_BASE,
133 .pfn = __phys_to_pfn(L2CC_BASE),
134 .length = SZ_4K,
135 .type = MT_DEVICE
136 },
137};
138
139/* This will create static memory mapping for selected devices */
140void __init spear13xx_map_io(void)
141{
142 iotable_init(spear13xx_io_desc, ARRAY_SIZE(spear13xx_io_desc));
143}
144
145static void __init spear13xx_clk_init(void)
146{
147 if (of_machine_is_compatible("st,spear1310"))
148 spear1310_clk_init();
149 else if (of_machine_is_compatible("st,spear1340"))
150 spear1340_clk_init();
151 else
152 pr_err("%s: Unknown machine\n", __func__);
153}
154
155static void __init spear13xx_timer_init(void)
156{
157 char pclk_name[] = "osc_24m_clk";
158 struct clk *gpt_clk, *pclk;
159
160 spear13xx_clk_init();
161
162 /* get the system timer clock */
163 gpt_clk = clk_get_sys("gpt0", NULL);
164 if (IS_ERR(gpt_clk)) {
165 pr_err("%s:couldn't get clk for gpt\n", __func__);
166 BUG();
167 }
168
169 /* get the suitable parent clock for timer*/
170 pclk = clk_get(NULL, pclk_name);
171 if (IS_ERR(pclk)) {
172 pr_err("%s:couldn't get %s as parent for gpt\n", __func__,
173 pclk_name);
174 BUG();
175 }
176
177 clk_set_parent(gpt_clk, pclk);
178 clk_put(gpt_clk);
179 clk_put(pclk);
180
181 spear_setup_of_timer();
182 twd_local_timer_of_register();
183}
184
185struct sys_timer spear13xx_timer = {
186 .init = spear13xx_timer_init,
187};
188
189static const struct of_device_id gic_of_match[] __initconst = {
190 { .compatible = "arm,cortex-a9-gic", .data = gic_of_init },
191 { /* Sentinel */ }
192};
193
194void __init spear13xx_dt_init_irq(void)
195{
196 of_irq_init(gic_of_match);
197}
diff --git a/arch/arm/mach-spear3xx/Kconfig b/arch/arm/mach-spear3xx/Kconfig
index 2cee6b0de371..8bd37291fa4f 100644
--- a/arch/arm/mach-spear3xx/Kconfig
+++ b/arch/arm/mach-spear3xx/Kconfig
@@ -5,39 +5,22 @@
5if ARCH_SPEAR3XX 5if ARCH_SPEAR3XX
6 6
7menu "SPEAr3xx Implementations" 7menu "SPEAr3xx Implementations"
8config BOARD_SPEAR300_EVB
9 bool "SPEAr300 Evaluation Board"
10 select MACH_SPEAR300
11 help
12 Supports ST SPEAr300 Evaluation Board
13
14config BOARD_SPEAR310_EVB
15 bool "SPEAr310 Evaluation Board"
16 select MACH_SPEAR310
17 help
18 Supports ST SPEAr310 Evaluation Board
19
20config BOARD_SPEAR320_EVB
21 bool "SPEAr320 Evaluation Board"
22 select MACH_SPEAR320
23 help
24 Supports ST SPEAr320 Evaluation Board
25
26endmenu
27
28config MACH_SPEAR300 8config MACH_SPEAR300
29 bool "SPEAr300" 9 bool "SPEAr300 Machine support with Device Tree"
10 select PINCTRL_SPEAR300
30 help 11 help
31 Supports ST SPEAr300 Machine 12 Supports ST SPEAr300 machine configured via the device-tree
32 13
33config MACH_SPEAR310 14config MACH_SPEAR310
34 bool "SPEAr310" 15 bool "SPEAr310 Machine support with Device Tree"
16 select PINCTRL_SPEAR310
35 help 17 help
36 Supports ST SPEAr310 Machine 18 Supports ST SPEAr310 machine configured via the device-tree
37 19
38config MACH_SPEAR320 20config MACH_SPEAR320
39 bool "SPEAr320" 21 bool "SPEAr320 Machine support with Device Tree"
22 select PINCTRL_SPEAR320
40 help 23 help
41 Supports ST SPEAr320 Machine 24 Supports ST SPEAr320 machine configured via the device-tree
42 25endmenu
43endif #ARCH_SPEAR3XX 26endif #ARCH_SPEAR3XX
diff --git a/arch/arm/mach-spear3xx/Makefile b/arch/arm/mach-spear3xx/Makefile
index b24862489704..8d12faa178fd 100644
--- a/arch/arm/mach-spear3xx/Makefile
+++ b/arch/arm/mach-spear3xx/Makefile
@@ -3,24 +3,13 @@
3# 3#
4 4
5# common files 5# common files
6obj-y += spear3xx.o clock.o 6obj-$(CONFIG_ARCH_SPEAR3XX) += spear3xx.o
7 7
8# spear300 specific files 8# spear300 specific files
9obj-$(CONFIG_MACH_SPEAR300) += spear300.o 9obj-$(CONFIG_MACH_SPEAR300) += spear300.o
10 10
11# spear300 boards files
12obj-$(CONFIG_BOARD_SPEAR300_EVB) += spear300_evb.o
13
14
15# spear310 specific files 11# spear310 specific files
16obj-$(CONFIG_MACH_SPEAR310) += spear310.o 12obj-$(CONFIG_MACH_SPEAR310) += spear310.o
17 13
18# spear310 boards files
19obj-$(CONFIG_BOARD_SPEAR310_EVB) += spear310_evb.o
20
21
22# spear320 specific files 14# spear320 specific files
23obj-$(CONFIG_MACH_SPEAR320) += spear320.o 15obj-$(CONFIG_MACH_SPEAR320) += spear320.o
24
25# spear320 boards files
26obj-$(CONFIG_BOARD_SPEAR320_EVB) += spear320_evb.o
diff --git a/arch/arm/mach-spear3xx/Makefile.boot b/arch/arm/mach-spear3xx/Makefile.boot
index 4674a4c221db..d93e2177e6ec 100644
--- a/arch/arm/mach-spear3xx/Makefile.boot
+++ b/arch/arm/mach-spear3xx/Makefile.boot
@@ -1,3 +1,7 @@
1zreladdr-y += 0x00008000 1zreladdr-y += 0x00008000
2params_phys-y := 0x00000100 2params_phys-y := 0x00000100
3initrd_phys-y := 0x00800000 3initrd_phys-y := 0x00800000
4
5dtb-$(CONFIG_MACH_SPEAR300) += spear300-evb.dtb
6dtb-$(CONFIG_MACH_SPEAR310) += spear310-evb.dtb
7dtb-$(CONFIG_MACH_SPEAR320) += spear320-evb.dtb
diff --git a/arch/arm/mach-spear3xx/clock.c b/arch/arm/mach-spear3xx/clock.c
deleted file mode 100644
index 6c4841f55223..000000000000
--- a/arch/arm/mach-spear3xx/clock.c
+++ /dev/null
@@ -1,760 +0,0 @@
1/*
2 * arch/arm/mach-spear3xx/clock.c
3 *
4 * SPEAr3xx machines clock framework source file
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <linux/init.h>
15#include <linux/io.h>
16#include <linux/kernel.h>
17#include <asm/mach-types.h>
18#include <plat/clock.h>
19#include <mach/misc_regs.h>
20
21/* root clks */
22/* 32 KHz oscillator clock */
23static struct clk osc_32k_clk = {
24 .flags = ALWAYS_ENABLED,
25 .rate = 32000,
26};
27
28/* 24 MHz oscillator clock */
29static struct clk osc_24m_clk = {
30 .flags = ALWAYS_ENABLED,
31 .rate = 24000000,
32};
33
34/* clock derived from 32 KHz osc clk */
35/* rtc clock */
36static struct clk rtc_clk = {
37 .pclk = &osc_32k_clk,
38 .en_reg = PERIP1_CLK_ENB,
39 .en_reg_bit = RTC_CLK_ENB,
40 .recalc = &follow_parent,
41};
42
43/* clock derived from 24 MHz osc clk */
44/* pll masks structure */
45static struct pll_clk_masks pll1_masks = {
46 .mode_mask = PLL_MODE_MASK,
47 .mode_shift = PLL_MODE_SHIFT,
48 .norm_fdbk_m_mask = PLL_NORM_FDBK_M_MASK,
49 .norm_fdbk_m_shift = PLL_NORM_FDBK_M_SHIFT,
50 .dith_fdbk_m_mask = PLL_DITH_FDBK_M_MASK,
51 .dith_fdbk_m_shift = PLL_DITH_FDBK_M_SHIFT,
52 .div_p_mask = PLL_DIV_P_MASK,
53 .div_p_shift = PLL_DIV_P_SHIFT,
54 .div_n_mask = PLL_DIV_N_MASK,
55 .div_n_shift = PLL_DIV_N_SHIFT,
56};
57
58/* pll1 configuration structure */
59static struct pll_clk_config pll1_config = {
60 .mode_reg = PLL1_CTR,
61 .cfg_reg = PLL1_FRQ,
62 .masks = &pll1_masks,
63};
64
65/* pll rate configuration table, in ascending order of rates */
66struct pll_rate_tbl pll_rtbl[] = {
67 {.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* 266 MHz */
68 {.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* 332 MHz */
69};
70
71/* PLL1 clock */
72static struct clk pll1_clk = {
73 .flags = ENABLED_ON_INIT,
74 .pclk = &osc_24m_clk,
75 .en_reg = PLL1_CTR,
76 .en_reg_bit = PLL_ENABLE,
77 .calc_rate = &pll_calc_rate,
78 .recalc = &pll_clk_recalc,
79 .set_rate = &pll_clk_set_rate,
80 .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 1},
81 .private_data = &pll1_config,
82};
83
84/* PLL3 48 MHz clock */
85static struct clk pll3_48m_clk = {
86 .flags = ALWAYS_ENABLED,
87 .pclk = &osc_24m_clk,
88 .rate = 48000000,
89};
90
91/* watch dog timer clock */
92static struct clk wdt_clk = {
93 .flags = ALWAYS_ENABLED,
94 .pclk = &osc_24m_clk,
95 .recalc = &follow_parent,
96};
97
98/* clock derived from pll1 clk */
99/* cpu clock */
100static struct clk cpu_clk = {
101 .flags = ALWAYS_ENABLED,
102 .pclk = &pll1_clk,
103 .recalc = &follow_parent,
104};
105
106/* ahb masks structure */
107static struct bus_clk_masks ahb_masks = {
108 .mask = PLL_HCLK_RATIO_MASK,
109 .shift = PLL_HCLK_RATIO_SHIFT,
110};
111
112/* ahb configuration structure */
113static struct bus_clk_config ahb_config = {
114 .reg = CORE_CLK_CFG,
115 .masks = &ahb_masks,
116};
117
118/* ahb rate configuration table, in ascending order of rates */
119struct bus_rate_tbl bus_rtbl[] = {
120 {.div = 3}, /* == parent divided by 4 */
121 {.div = 2}, /* == parent divided by 3 */
122 {.div = 1}, /* == parent divided by 2 */
123 {.div = 0}, /* == parent divided by 1 */
124};
125
126/* ahb clock */
127static struct clk ahb_clk = {
128 .flags = ALWAYS_ENABLED,
129 .pclk = &pll1_clk,
130 .calc_rate = &bus_calc_rate,
131 .recalc = &bus_clk_recalc,
132 .set_rate = &bus_clk_set_rate,
133 .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
134 .private_data = &ahb_config,
135};
136
137/* auxiliary synthesizers masks */
138static struct aux_clk_masks aux_masks = {
139 .eq_sel_mask = AUX_EQ_SEL_MASK,
140 .eq_sel_shift = AUX_EQ_SEL_SHIFT,
141 .eq1_mask = AUX_EQ1_SEL,
142 .eq2_mask = AUX_EQ2_SEL,
143 .xscale_sel_mask = AUX_XSCALE_MASK,
144 .xscale_sel_shift = AUX_XSCALE_SHIFT,
145 .yscale_sel_mask = AUX_YSCALE_MASK,
146 .yscale_sel_shift = AUX_YSCALE_SHIFT,
147};
148
149/* uart synth configurations */
150static struct aux_clk_config uart_synth_config = {
151 .synth_reg = UART_CLK_SYNT,
152 .masks = &aux_masks,
153};
154
155/* aux rate configuration table, in ascending order of rates */
156struct aux_rate_tbl aux_rtbl[] = {
157 /* For PLL1 = 332 MHz */
158 {.xscale = 1, .yscale = 8, .eq = 1}, /* 41.5 MHz */
159 {.xscale = 1, .yscale = 4, .eq = 1}, /* 83 MHz */
160 {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
161};
162
163/* uart synth clock */
164static struct clk uart_synth_clk = {
165 .en_reg = UART_CLK_SYNT,
166 .en_reg_bit = AUX_SYNT_ENB,
167 .pclk = &pll1_clk,
168 .calc_rate = &aux_calc_rate,
169 .recalc = &aux_clk_recalc,
170 .set_rate = &aux_clk_set_rate,
171 .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 1},
172 .private_data = &uart_synth_config,
173};
174
175/* uart parents */
176static struct pclk_info uart_pclk_info[] = {
177 {
178 .pclk = &uart_synth_clk,
179 .pclk_val = AUX_CLK_PLL1_VAL,
180 }, {
181 .pclk = &pll3_48m_clk,
182 .pclk_val = AUX_CLK_PLL3_VAL,
183 },
184};
185
186/* uart parent select structure */
187static struct pclk_sel uart_pclk_sel = {
188 .pclk_info = uart_pclk_info,
189 .pclk_count = ARRAY_SIZE(uart_pclk_info),
190 .pclk_sel_reg = PERIP_CLK_CFG,
191 .pclk_sel_mask = UART_CLK_MASK,
192};
193
194/* uart clock */
195static struct clk uart_clk = {
196 .en_reg = PERIP1_CLK_ENB,
197 .en_reg_bit = UART_CLK_ENB,
198 .pclk_sel = &uart_pclk_sel,
199 .pclk_sel_shift = UART_CLK_SHIFT,
200 .recalc = &follow_parent,
201};
202
203/* firda configurations */
204static struct aux_clk_config firda_synth_config = {
205 .synth_reg = FIRDA_CLK_SYNT,
206 .masks = &aux_masks,
207};
208
209/* firda synth clock */
210static struct clk firda_synth_clk = {
211 .en_reg = FIRDA_CLK_SYNT,
212 .en_reg_bit = AUX_SYNT_ENB,
213 .pclk = &pll1_clk,
214 .calc_rate = &aux_calc_rate,
215 .recalc = &aux_clk_recalc,
216 .set_rate = &aux_clk_set_rate,
217 .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 1},
218 .private_data = &firda_synth_config,
219};
220
221/* firda parents */
222static struct pclk_info firda_pclk_info[] = {
223 {
224 .pclk = &firda_synth_clk,
225 .pclk_val = AUX_CLK_PLL1_VAL,
226 }, {
227 .pclk = &pll3_48m_clk,
228 .pclk_val = AUX_CLK_PLL3_VAL,
229 },
230};
231
232/* firda parent select structure */
233static struct pclk_sel firda_pclk_sel = {
234 .pclk_info = firda_pclk_info,
235 .pclk_count = ARRAY_SIZE(firda_pclk_info),
236 .pclk_sel_reg = PERIP_CLK_CFG,
237 .pclk_sel_mask = FIRDA_CLK_MASK,
238};
239
240/* firda clock */
241static struct clk firda_clk = {
242 .en_reg = PERIP1_CLK_ENB,
243 .en_reg_bit = FIRDA_CLK_ENB,
244 .pclk_sel = &firda_pclk_sel,
245 .pclk_sel_shift = FIRDA_CLK_SHIFT,
246 .recalc = &follow_parent,
247};
248
249/* gpt synthesizer masks */
250static struct gpt_clk_masks gpt_masks = {
251 .mscale_sel_mask = GPT_MSCALE_MASK,
252 .mscale_sel_shift = GPT_MSCALE_SHIFT,
253 .nscale_sel_mask = GPT_NSCALE_MASK,
254 .nscale_sel_shift = GPT_NSCALE_SHIFT,
255};
256
257/* gpt rate configuration table, in ascending order of rates */
258struct gpt_rate_tbl gpt_rtbl[] = {
259 /* For pll1 = 332 MHz */
260 {.mscale = 4, .nscale = 0}, /* 41.5 MHz */
261 {.mscale = 2, .nscale = 0}, /* 55.3 MHz */
262 {.mscale = 1, .nscale = 0}, /* 83 MHz */
263};
264
265/* gpt0 synth clk config*/
266static struct gpt_clk_config gpt0_synth_config = {
267 .synth_reg = PRSC1_CLK_CFG,
268 .masks = &gpt_masks,
269};
270
271/* gpt synth clock */
272static struct clk gpt0_synth_clk = {
273 .flags = ALWAYS_ENABLED,
274 .pclk = &pll1_clk,
275 .calc_rate = &gpt_calc_rate,
276 .recalc = &gpt_clk_recalc,
277 .set_rate = &gpt_clk_set_rate,
278 .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
279 .private_data = &gpt0_synth_config,
280};
281
282/* gpt parents */
283static struct pclk_info gpt0_pclk_info[] = {
284 {
285 .pclk = &gpt0_synth_clk,
286 .pclk_val = AUX_CLK_PLL1_VAL,
287 }, {
288 .pclk = &pll3_48m_clk,
289 .pclk_val = AUX_CLK_PLL3_VAL,
290 },
291};
292
293/* gpt parent select structure */
294static struct pclk_sel gpt0_pclk_sel = {
295 .pclk_info = gpt0_pclk_info,
296 .pclk_count = ARRAY_SIZE(gpt0_pclk_info),
297 .pclk_sel_reg = PERIP_CLK_CFG,
298 .pclk_sel_mask = GPT_CLK_MASK,
299};
300
301/* gpt0 timer clock */
302static struct clk gpt0_clk = {
303 .flags = ALWAYS_ENABLED,
304 .pclk_sel = &gpt0_pclk_sel,
305 .pclk_sel_shift = GPT0_CLK_SHIFT,
306 .recalc = &follow_parent,
307};
308
309/* gpt1 synth clk configurations */
310static struct gpt_clk_config gpt1_synth_config = {
311 .synth_reg = PRSC2_CLK_CFG,
312 .masks = &gpt_masks,
313};
314
315/* gpt1 synth clock */
316static struct clk gpt1_synth_clk = {
317 .flags = ALWAYS_ENABLED,
318 .pclk = &pll1_clk,
319 .calc_rate = &gpt_calc_rate,
320 .recalc = &gpt_clk_recalc,
321 .set_rate = &gpt_clk_set_rate,
322 .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
323 .private_data = &gpt1_synth_config,
324};
325
326static struct pclk_info gpt1_pclk_info[] = {
327 {
328 .pclk = &gpt1_synth_clk,
329 .pclk_val = AUX_CLK_PLL1_VAL,
330 }, {
331 .pclk = &pll3_48m_clk,
332 .pclk_val = AUX_CLK_PLL3_VAL,
333 },
334};
335
336/* gpt parent select structure */
337static struct pclk_sel gpt1_pclk_sel = {
338 .pclk_info = gpt1_pclk_info,
339 .pclk_count = ARRAY_SIZE(gpt1_pclk_info),
340 .pclk_sel_reg = PERIP_CLK_CFG,
341 .pclk_sel_mask = GPT_CLK_MASK,
342};
343
344/* gpt1 timer clock */
345static struct clk gpt1_clk = {
346 .en_reg = PERIP1_CLK_ENB,
347 .en_reg_bit = GPT1_CLK_ENB,
348 .pclk_sel = &gpt1_pclk_sel,
349 .pclk_sel_shift = GPT1_CLK_SHIFT,
350 .recalc = &follow_parent,
351};
352
353/* gpt2 synth clk configurations */
354static struct gpt_clk_config gpt2_synth_config = {
355 .synth_reg = PRSC3_CLK_CFG,
356 .masks = &gpt_masks,
357};
358
359/* gpt1 synth clock */
360static struct clk gpt2_synth_clk = {
361 .flags = ALWAYS_ENABLED,
362 .pclk = &pll1_clk,
363 .calc_rate = &gpt_calc_rate,
364 .recalc = &gpt_clk_recalc,
365 .set_rate = &gpt_clk_set_rate,
366 .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
367 .private_data = &gpt2_synth_config,
368};
369
370static struct pclk_info gpt2_pclk_info[] = {
371 {
372 .pclk = &gpt2_synth_clk,
373 .pclk_val = AUX_CLK_PLL1_VAL,
374 }, {
375 .pclk = &pll3_48m_clk,
376 .pclk_val = AUX_CLK_PLL3_VAL,
377 },
378};
379
380/* gpt parent select structure */
381static struct pclk_sel gpt2_pclk_sel = {
382 .pclk_info = gpt2_pclk_info,
383 .pclk_count = ARRAY_SIZE(gpt2_pclk_info),
384 .pclk_sel_reg = PERIP_CLK_CFG,
385 .pclk_sel_mask = GPT_CLK_MASK,
386};
387
388/* gpt2 timer clock */
389static struct clk gpt2_clk = {
390 .en_reg = PERIP1_CLK_ENB,
391 .en_reg_bit = GPT2_CLK_ENB,
392 .pclk_sel = &gpt2_pclk_sel,
393 .pclk_sel_shift = GPT2_CLK_SHIFT,
394 .recalc = &follow_parent,
395};
396
397/* clock derived from pll3 clk */
398/* usbh clock */
399static struct clk usbh_clk = {
400 .pclk = &pll3_48m_clk,
401 .en_reg = PERIP1_CLK_ENB,
402 .en_reg_bit = USBH_CLK_ENB,
403 .recalc = &follow_parent,
404};
405
406/* usbd clock */
407static struct clk usbd_clk = {
408 .pclk = &pll3_48m_clk,
409 .en_reg = PERIP1_CLK_ENB,
410 .en_reg_bit = USBD_CLK_ENB,
411 .recalc = &follow_parent,
412};
413
414/* clock derived from ahb clk */
415/* apb masks structure */
416static struct bus_clk_masks apb_masks = {
417 .mask = HCLK_PCLK_RATIO_MASK,
418 .shift = HCLK_PCLK_RATIO_SHIFT,
419};
420
421/* apb configuration structure */
422static struct bus_clk_config apb_config = {
423 .reg = CORE_CLK_CFG,
424 .masks = &apb_masks,
425};
426
427/* apb clock */
428static struct clk apb_clk = {
429 .flags = ALWAYS_ENABLED,
430 .pclk = &ahb_clk,
431 .calc_rate = &bus_calc_rate,
432 .recalc = &bus_clk_recalc,
433 .set_rate = &bus_clk_set_rate,
434 .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
435 .private_data = &apb_config,
436};
437
438/* i2c clock */
439static struct clk i2c_clk = {
440 .pclk = &ahb_clk,
441 .en_reg = PERIP1_CLK_ENB,
442 .en_reg_bit = I2C_CLK_ENB,
443 .recalc = &follow_parent,
444};
445
446/* dma clock */
447static struct clk dma_clk = {
448 .pclk = &ahb_clk,
449 .en_reg = PERIP1_CLK_ENB,
450 .en_reg_bit = DMA_CLK_ENB,
451 .recalc = &follow_parent,
452};
453
454/* jpeg clock */
455static struct clk jpeg_clk = {
456 .pclk = &ahb_clk,
457 .en_reg = PERIP1_CLK_ENB,
458 .en_reg_bit = JPEG_CLK_ENB,
459 .recalc = &follow_parent,
460};
461
462/* gmac clock */
463static struct clk gmac_clk = {
464 .pclk = &ahb_clk,
465 .en_reg = PERIP1_CLK_ENB,
466 .en_reg_bit = GMAC_CLK_ENB,
467 .recalc = &follow_parent,
468};
469
470/* smi clock */
471static struct clk smi_clk = {
472 .pclk = &ahb_clk,
473 .en_reg = PERIP1_CLK_ENB,
474 .en_reg_bit = SMI_CLK_ENB,
475 .recalc = &follow_parent,
476};
477
478/* c3 clock */
479static struct clk c3_clk = {
480 .pclk = &ahb_clk,
481 .en_reg = PERIP1_CLK_ENB,
482 .en_reg_bit = C3_CLK_ENB,
483 .recalc = &follow_parent,
484};
485
486/* clock derived from apb clk */
487/* adc clock */
488static struct clk adc_clk = {
489 .pclk = &apb_clk,
490 .en_reg = PERIP1_CLK_ENB,
491 .en_reg_bit = ADC_CLK_ENB,
492 .recalc = &follow_parent,
493};
494
495#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
496/* emi clock */
497static struct clk emi_clk = {
498 .flags = ALWAYS_ENABLED,
499 .pclk = &ahb_clk,
500 .recalc = &follow_parent,
501};
502#endif
503
504/* ssp clock */
505static struct clk ssp0_clk = {
506 .pclk = &apb_clk,
507 .en_reg = PERIP1_CLK_ENB,
508 .en_reg_bit = SSP_CLK_ENB,
509 .recalc = &follow_parent,
510};
511
512/* gpio clock */
513static struct clk gpio_clk = {
514 .pclk = &apb_clk,
515 .en_reg = PERIP1_CLK_ENB,
516 .en_reg_bit = GPIO_CLK_ENB,
517 .recalc = &follow_parent,
518};
519
520static struct clk dummy_apb_pclk;
521
522#if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR310) || \
523 defined(CONFIG_MACH_SPEAR320)
524/* fsmc clock */
525static struct clk fsmc_clk = {
526 .flags = ALWAYS_ENABLED,
527 .pclk = &ahb_clk,
528 .recalc = &follow_parent,
529};
530#endif
531
532/* common clocks to spear310 and spear320 */
533#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
534/* uart1 clock */
535static struct clk uart1_clk = {
536 .flags = ALWAYS_ENABLED,
537 .pclk = &apb_clk,
538 .recalc = &follow_parent,
539};
540
541/* uart2 clock */
542static struct clk uart2_clk = {
543 .flags = ALWAYS_ENABLED,
544 .pclk = &apb_clk,
545 .recalc = &follow_parent,
546};
547#endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */
548
549/* common clocks to spear300 and spear320 */
550#if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR320)
551/* clcd clock */
552static struct clk clcd_clk = {
553 .flags = ALWAYS_ENABLED,
554 .pclk = &pll3_48m_clk,
555 .recalc = &follow_parent,
556};
557
558/* sdhci clock */
559static struct clk sdhci_clk = {
560 .flags = ALWAYS_ENABLED,
561 .pclk = &ahb_clk,
562 .recalc = &follow_parent,
563};
564#endif /* CONFIG_MACH_SPEAR300 || CONFIG_MACH_SPEAR320 */
565
566/* spear300 machine specific clock structures */
567#ifdef CONFIG_MACH_SPEAR300
568/* gpio1 clock */
569static struct clk gpio1_clk = {
570 .flags = ALWAYS_ENABLED,
571 .pclk = &apb_clk,
572 .recalc = &follow_parent,
573};
574
575/* keyboard clock */
576static struct clk kbd_clk = {
577 .flags = ALWAYS_ENABLED,
578 .pclk = &apb_clk,
579 .recalc = &follow_parent,
580};
581
582#endif
583
584/* spear310 machine specific clock structures */
585#ifdef CONFIG_MACH_SPEAR310
586/* uart3 clock */
587static struct clk uart3_clk = {
588 .flags = ALWAYS_ENABLED,
589 .pclk = &apb_clk,
590 .recalc = &follow_parent,
591};
592
593/* uart4 clock */
594static struct clk uart4_clk = {
595 .flags = ALWAYS_ENABLED,
596 .pclk = &apb_clk,
597 .recalc = &follow_parent,
598};
599
600/* uart5 clock */
601static struct clk uart5_clk = {
602 .flags = ALWAYS_ENABLED,
603 .pclk = &apb_clk,
604 .recalc = &follow_parent,
605};
606#endif
607
608/* spear320 machine specific clock structures */
609#ifdef CONFIG_MACH_SPEAR320
610/* can0 clock */
611static struct clk can0_clk = {
612 .flags = ALWAYS_ENABLED,
613 .pclk = &apb_clk,
614 .recalc = &follow_parent,
615};
616
617/* can1 clock */
618static struct clk can1_clk = {
619 .flags = ALWAYS_ENABLED,
620 .pclk = &apb_clk,
621 .recalc = &follow_parent,
622};
623
624/* i2c1 clock */
625static struct clk i2c1_clk = {
626 .flags = ALWAYS_ENABLED,
627 .pclk = &ahb_clk,
628 .recalc = &follow_parent,
629};
630
631/* ssp1 clock */
632static struct clk ssp1_clk = {
633 .flags = ALWAYS_ENABLED,
634 .pclk = &apb_clk,
635 .recalc = &follow_parent,
636};
637
638/* ssp2 clock */
639static struct clk ssp2_clk = {
640 .flags = ALWAYS_ENABLED,
641 .pclk = &apb_clk,
642 .recalc = &follow_parent,
643};
644
645/* pwm clock */
646static struct clk pwm_clk = {
647 .flags = ALWAYS_ENABLED,
648 .pclk = &apb_clk,
649 .recalc = &follow_parent,
650};
651#endif
652
653/* array of all spear 3xx clock lookups */
654static struct clk_lookup spear_clk_lookups[] = {
655 { .con_id = "apb_pclk", .clk = &dummy_apb_pclk},
656 /* root clks */
657 { .con_id = "osc_32k_clk", .clk = &osc_32k_clk},
658 { .con_id = "osc_24m_clk", .clk = &osc_24m_clk},
659 /* clock derived from 32 KHz osc clk */
660 { .dev_id = "rtc-spear", .clk = &rtc_clk},
661 /* clock derived from 24 MHz osc clk */
662 { .con_id = "pll1_clk", .clk = &pll1_clk},
663 { .con_id = "pll3_48m_clk", .clk = &pll3_48m_clk},
664 { .dev_id = "wdt", .clk = &wdt_clk},
665 /* clock derived from pll1 clk */
666 { .con_id = "cpu_clk", .clk = &cpu_clk},
667 { .con_id = "ahb_clk", .clk = &ahb_clk},
668 { .con_id = "uart_synth_clk", .clk = &uart_synth_clk},
669 { .con_id = "firda_synth_clk", .clk = &firda_synth_clk},
670 { .con_id = "gpt0_synth_clk", .clk = &gpt0_synth_clk},
671 { .con_id = "gpt1_synth_clk", .clk = &gpt1_synth_clk},
672 { .con_id = "gpt2_synth_clk", .clk = &gpt2_synth_clk},
673 { .dev_id = "uart", .clk = &uart_clk},
674 { .dev_id = "firda", .clk = &firda_clk},
675 { .dev_id = "gpt0", .clk = &gpt0_clk},
676 { .dev_id = "gpt1", .clk = &gpt1_clk},
677 { .dev_id = "gpt2", .clk = &gpt2_clk},
678 /* clock derived from pll3 clk */
679 { .dev_id = "designware_udc", .clk = &usbd_clk},
680 { .con_id = "usbh_clk", .clk = &usbh_clk},
681 /* clock derived from ahb clk */
682 { .con_id = "apb_clk", .clk = &apb_clk},
683 { .dev_id = "i2c_designware.0", .clk = &i2c_clk},
684 { .dev_id = "dma", .clk = &dma_clk},
685 { .dev_id = "jpeg", .clk = &jpeg_clk},
686 { .dev_id = "gmac", .clk = &gmac_clk},
687 { .dev_id = "smi", .clk = &smi_clk},
688 { .dev_id = "c3", .clk = &c3_clk},
689 /* clock derived from apb clk */
690 { .dev_id = "adc", .clk = &adc_clk},
691 { .dev_id = "ssp-pl022.0", .clk = &ssp0_clk},
692 { .dev_id = "gpio", .clk = &gpio_clk},
693};
694
695/* array of all spear 300 clock lookups */
696#ifdef CONFIG_MACH_SPEAR300
697static struct clk_lookup spear300_clk_lookups[] = {
698 { .dev_id = "clcd", .clk = &clcd_clk},
699 { .con_id = "fsmc", .clk = &fsmc_clk},
700 { .dev_id = "gpio1", .clk = &gpio1_clk},
701 { .dev_id = "keyboard", .clk = &kbd_clk},
702 { .dev_id = "sdhci", .clk = &sdhci_clk},
703};
704#endif
705
706/* array of all spear 310 clock lookups */
707#ifdef CONFIG_MACH_SPEAR310
708static struct clk_lookup spear310_clk_lookups[] = {
709 { .con_id = "fsmc", .clk = &fsmc_clk},
710 { .con_id = "emi", .clk = &emi_clk},
711 { .dev_id = "uart1", .clk = &uart1_clk},
712 { .dev_id = "uart2", .clk = &uart2_clk},
713 { .dev_id = "uart3", .clk = &uart3_clk},
714 { .dev_id = "uart4", .clk = &uart4_clk},
715 { .dev_id = "uart5", .clk = &uart5_clk},
716};
717#endif
718
719/* array of all spear 320 clock lookups */
720#ifdef CONFIG_MACH_SPEAR320
721static struct clk_lookup spear320_clk_lookups[] = {
722 { .dev_id = "clcd", .clk = &clcd_clk},
723 { .con_id = "fsmc", .clk = &fsmc_clk},
724 { .dev_id = "i2c_designware.1", .clk = &i2c1_clk},
725 { .con_id = "emi", .clk = &emi_clk},
726 { .dev_id = "pwm", .clk = &pwm_clk},
727 { .dev_id = "sdhci", .clk = &sdhci_clk},
728 { .dev_id = "c_can_platform.0", .clk = &can0_clk},
729 { .dev_id = "c_can_platform.1", .clk = &can1_clk},
730 { .dev_id = "ssp-pl022.1", .clk = &ssp1_clk},
731 { .dev_id = "ssp-pl022.2", .clk = &ssp2_clk},
732 { .dev_id = "uart1", .clk = &uart1_clk},
733 { .dev_id = "uart2", .clk = &uart2_clk},
734};
735#endif
736
737void __init spear3xx_clk_init(void)
738{
739 int i, cnt;
740 struct clk_lookup *lookups;
741
742 if (machine_is_spear300()) {
743 cnt = ARRAY_SIZE(spear300_clk_lookups);
744 lookups = spear300_clk_lookups;
745 } else if (machine_is_spear310()) {
746 cnt = ARRAY_SIZE(spear310_clk_lookups);
747 lookups = spear310_clk_lookups;
748 } else {
749 cnt = ARRAY_SIZE(spear320_clk_lookups);
750 lookups = spear320_clk_lookups;
751 }
752
753 for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
754 clk_register(&spear_clk_lookups[i]);
755
756 for (i = 0; i < cnt; i++)
757 clk_register(&lookups[i]);
758
759 clk_init();
760}
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index 14276e5a98d2..4a95b9453c2a 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -14,189 +14,24 @@
14#ifndef __MACH_GENERIC_H 14#ifndef __MACH_GENERIC_H
15#define __MACH_GENERIC_H 15#define __MACH_GENERIC_H
16 16
17#include <linux/amba/pl08x.h>
17#include <linux/init.h> 18#include <linux/init.h>
18#include <linux/platform_device.h> 19#include <linux/platform_device.h>
19#include <linux/amba/bus.h> 20#include <linux/amba/bus.h>
20#include <asm/mach/time.h> 21#include <asm/mach/time.h>
21#include <asm/mach/map.h> 22#include <asm/mach/map.h>
22#include <plat/padmux.h>
23
24/* spear3xx declarations */
25/*
26 * Each GPT has 2 timer channels
27 * Following GPT channels will be used as clock source and clockevent
28 */
29#define SPEAR_GPT0_BASE SPEAR3XX_ML1_TMR_BASE
30#define SPEAR_GPT0_CHAN0_IRQ SPEAR3XX_IRQ_CPU_GPT1_1
31#define SPEAR_GPT0_CHAN1_IRQ SPEAR3XX_IRQ_CPU_GPT1_2
32 23
33/* Add spear3xx family device structure declarations here */ 24/* Add spear3xx family device structure declarations here */
34extern struct amba_device spear3xx_gpio_device;
35extern struct amba_device spear3xx_uart_device;
36extern struct sys_timer spear3xx_timer; 25extern struct sys_timer spear3xx_timer;
26extern struct pl022_ssp_controller pl022_plat_data;
27extern struct pl08x_platform_data pl080_plat_data;
37 28
38/* Add spear3xx family function declarations here */ 29/* Add spear3xx family function declarations here */
30void __init spear_setup_of_timer(void);
39void __init spear3xx_clk_init(void); 31void __init spear3xx_clk_init(void);
40void __init spear_setup_timer(void);
41void __init spear3xx_map_io(void); 32void __init spear3xx_map_io(void);
42void __init spear3xx_init_irq(void); 33void __init spear3xx_dt_init_irq(void);
43void __init spear3xx_init(void);
44 34
45void spear_restart(char, const char *); 35void spear_restart(char, const char *);
46 36
47/* pad mux declarations */
48#define PMX_FIRDA_MASK (1 << 14)
49#define PMX_I2C_MASK (1 << 13)
50#define PMX_SSP_CS_MASK (1 << 12)
51#define PMX_SSP_MASK (1 << 11)
52#define PMX_MII_MASK (1 << 10)
53#define PMX_GPIO_PIN0_MASK (1 << 9)
54#define PMX_GPIO_PIN1_MASK (1 << 8)
55#define PMX_GPIO_PIN2_MASK (1 << 7)
56#define PMX_GPIO_PIN3_MASK (1 << 6)
57#define PMX_GPIO_PIN4_MASK (1 << 5)
58#define PMX_GPIO_PIN5_MASK (1 << 4)
59#define PMX_UART0_MODEM_MASK (1 << 3)
60#define PMX_UART0_MASK (1 << 2)
61#define PMX_TIMER_3_4_MASK (1 << 1)
62#define PMX_TIMER_1_2_MASK (1 << 0)
63
64/* pad mux devices */
65extern struct pmx_dev spear3xx_pmx_firda;
66extern struct pmx_dev spear3xx_pmx_i2c;
67extern struct pmx_dev spear3xx_pmx_ssp_cs;
68extern struct pmx_dev spear3xx_pmx_ssp;
69extern struct pmx_dev spear3xx_pmx_mii;
70extern struct pmx_dev spear3xx_pmx_gpio_pin0;
71extern struct pmx_dev spear3xx_pmx_gpio_pin1;
72extern struct pmx_dev spear3xx_pmx_gpio_pin2;
73extern struct pmx_dev spear3xx_pmx_gpio_pin3;
74extern struct pmx_dev spear3xx_pmx_gpio_pin4;
75extern struct pmx_dev spear3xx_pmx_gpio_pin5;
76extern struct pmx_dev spear3xx_pmx_uart0_modem;
77extern struct pmx_dev spear3xx_pmx_uart0;
78extern struct pmx_dev spear3xx_pmx_timer_3_4;
79extern struct pmx_dev spear3xx_pmx_timer_1_2;
80
81#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
82/* padmux plgpio devices */
83extern struct pmx_dev spear3xx_pmx_plgpio_0_1;
84extern struct pmx_dev spear3xx_pmx_plgpio_2_3;
85extern struct pmx_dev spear3xx_pmx_plgpio_4_5;
86extern struct pmx_dev spear3xx_pmx_plgpio_6_9;
87extern struct pmx_dev spear3xx_pmx_plgpio_10_27;
88extern struct pmx_dev spear3xx_pmx_plgpio_28;
89extern struct pmx_dev spear3xx_pmx_plgpio_29;
90extern struct pmx_dev spear3xx_pmx_plgpio_30;
91extern struct pmx_dev spear3xx_pmx_plgpio_31;
92extern struct pmx_dev spear3xx_pmx_plgpio_32;
93extern struct pmx_dev spear3xx_pmx_plgpio_33;
94extern struct pmx_dev spear3xx_pmx_plgpio_34_36;
95extern struct pmx_dev spear3xx_pmx_plgpio_37_42;
96extern struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48;
97extern struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50;
98#endif
99
100/* spear300 declarations */
101#ifdef CONFIG_MACH_SPEAR300
102/* Add spear300 machine device structure declarations here */
103extern struct amba_device spear300_gpio1_device;
104
105/* pad mux modes */
106extern struct pmx_mode spear300_nand_mode;
107extern struct pmx_mode spear300_nor_mode;
108extern struct pmx_mode spear300_photo_frame_mode;
109extern struct pmx_mode spear300_lend_ip_phone_mode;
110extern struct pmx_mode spear300_hend_ip_phone_mode;
111extern struct pmx_mode spear300_lend_wifi_phone_mode;
112extern struct pmx_mode spear300_hend_wifi_phone_mode;
113extern struct pmx_mode spear300_ata_pabx_wi2s_mode;
114extern struct pmx_mode spear300_ata_pabx_i2s_mode;
115extern struct pmx_mode spear300_caml_lcdw_mode;
116extern struct pmx_mode spear300_camu_lcd_mode;
117extern struct pmx_mode spear300_camu_wlcd_mode;
118extern struct pmx_mode spear300_caml_lcd_mode;
119
120/* pad mux devices */
121extern struct pmx_dev spear300_pmx_fsmc_2_chips;
122extern struct pmx_dev spear300_pmx_fsmc_4_chips;
123extern struct pmx_dev spear300_pmx_keyboard;
124extern struct pmx_dev spear300_pmx_clcd;
125extern struct pmx_dev spear300_pmx_telecom_gpio;
126extern struct pmx_dev spear300_pmx_telecom_tdm;
127extern struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk;
128extern struct pmx_dev spear300_pmx_telecom_camera;
129extern struct pmx_dev spear300_pmx_telecom_dac;
130extern struct pmx_dev spear300_pmx_telecom_i2s;
131extern struct pmx_dev spear300_pmx_telecom_boot_pins;
132extern struct pmx_dev spear300_pmx_telecom_sdhci_4bit;
133extern struct pmx_dev spear300_pmx_telecom_sdhci_8bit;
134extern struct pmx_dev spear300_pmx_gpio1;
135
136/* Add spear300 machine function declarations here */
137void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
138 u8 pmx_dev_count);
139
140#endif /* CONFIG_MACH_SPEAR300 */
141
142/* spear310 declarations */
143#ifdef CONFIG_MACH_SPEAR310
144/* Add spear310 machine device structure declarations here */
145
146/* pad mux devices */
147extern struct pmx_dev spear310_pmx_emi_cs_0_1_4_5;
148extern struct pmx_dev spear310_pmx_emi_cs_2_3;
149extern struct pmx_dev spear310_pmx_uart1;
150extern struct pmx_dev spear310_pmx_uart2;
151extern struct pmx_dev spear310_pmx_uart3_4_5;
152extern struct pmx_dev spear310_pmx_fsmc;
153extern struct pmx_dev spear310_pmx_rs485_0_1;
154extern struct pmx_dev spear310_pmx_tdm0;
155
156/* Add spear310 machine function declarations here */
157void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
158 u8 pmx_dev_count);
159
160#endif /* CONFIG_MACH_SPEAR310 */
161
162/* spear320 declarations */
163#ifdef CONFIG_MACH_SPEAR320
164/* Add spear320 machine device structure declarations here */
165
166/* pad mux modes */
167extern struct pmx_mode spear320_auto_net_smii_mode;
168extern struct pmx_mode spear320_auto_net_mii_mode;
169extern struct pmx_mode spear320_auto_exp_mode;
170extern struct pmx_mode spear320_small_printers_mode;
171
172/* pad mux devices */
173extern struct pmx_dev spear320_pmx_clcd;
174extern struct pmx_dev spear320_pmx_emi;
175extern struct pmx_dev spear320_pmx_fsmc;
176extern struct pmx_dev spear320_pmx_spp;
177extern struct pmx_dev spear320_pmx_sdhci;
178extern struct pmx_dev spear320_pmx_i2s;
179extern struct pmx_dev spear320_pmx_uart1;
180extern struct pmx_dev spear320_pmx_uart1_modem;
181extern struct pmx_dev spear320_pmx_uart2;
182extern struct pmx_dev spear320_pmx_touchscreen;
183extern struct pmx_dev spear320_pmx_can;
184extern struct pmx_dev spear320_pmx_sdhci_led;
185extern struct pmx_dev spear320_pmx_pwm0;
186extern struct pmx_dev spear320_pmx_pwm1;
187extern struct pmx_dev spear320_pmx_pwm2;
188extern struct pmx_dev spear320_pmx_pwm3;
189extern struct pmx_dev spear320_pmx_ssp1;
190extern struct pmx_dev spear320_pmx_ssp2;
191extern struct pmx_dev spear320_pmx_mii1;
192extern struct pmx_dev spear320_pmx_smii0;
193extern struct pmx_dev spear320_pmx_smii1;
194extern struct pmx_dev spear320_pmx_i2c1;
195
196/* Add spear320 machine function declarations here */
197void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
198 u8 pmx_dev_count);
199
200#endif /* CONFIG_MACH_SPEAR320 */
201
202#endif /* __MACH_GENERIC_H */ 37#endif /* __MACH_GENERIC_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/hardware.h b/arch/arm/mach-spear3xx/include/mach/hardware.h
index 4660c0d8ec0d..40a8c178f10d 100644
--- a/arch/arm/mach-spear3xx/include/mach/hardware.h
+++ b/arch/arm/mach-spear3xx/include/mach/hardware.h
@@ -1,23 +1 @@
1/* /* empty */
2 * arch/arm/mach-spear3xx/include/mach/hardware.h
3 *
4 * Hardware definitions for SPEAr3xx machine family
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __MACH_HARDWARE_H
15#define __MACH_HARDWARE_H
16
17#include <plat/hardware.h>
18#include <mach/spear.h>
19
20/* Vitual to physical translation of statically mapped space */
21#define IO_ADDRESS(x) (x | 0xF0000000)
22
23#endif /* __MACH_HARDWARE_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/irqs.h b/arch/arm/mach-spear3xx/include/mach/irqs.h
index 6e265442808e..51bd62a0254c 100644
--- a/arch/arm/mach-spear3xx/include/mach/irqs.h
+++ b/arch/arm/mach-spear3xx/include/mach/irqs.h
@@ -14,141 +14,14 @@
14#ifndef __MACH_IRQS_H 14#ifndef __MACH_IRQS_H
15#define __MACH_IRQS_H 15#define __MACH_IRQS_H
16 16
17/* SPEAr3xx IRQ definitions */ 17/* FIXME: probe all these from DT */
18#define SPEAR3XX_IRQ_HW_ACCEL_MOD_0 0
19#define SPEAR3XX_IRQ_INTRCOMM_RAS_ARM 1 18#define SPEAR3XX_IRQ_INTRCOMM_RAS_ARM 1
20#define SPEAR3XX_IRQ_CPU_GPT1_1 2
21#define SPEAR3XX_IRQ_CPU_GPT1_2 3
22#define SPEAR3XX_IRQ_BASIC_GPT1_1 4
23#define SPEAR3XX_IRQ_BASIC_GPT1_2 5
24#define SPEAR3XX_IRQ_BASIC_GPT2_1 6
25#define SPEAR3XX_IRQ_BASIC_GPT2_2 7
26#define SPEAR3XX_IRQ_BASIC_DMA 8
27#define SPEAR3XX_IRQ_BASIC_SMI 9
28#define SPEAR3XX_IRQ_BASIC_RTC 10
29#define SPEAR3XX_IRQ_BASIC_GPIO 11
30#define SPEAR3XX_IRQ_BASIC_WDT 12
31#define SPEAR3XX_IRQ_DDR_CONTROLLER 13
32#define SPEAR3XX_IRQ_SYS_ERROR 14
33#define SPEAR3XX_IRQ_WAKEUP_RCV 15
34#define SPEAR3XX_IRQ_JPEG 16
35#define SPEAR3XX_IRQ_IRDA 17
36#define SPEAR3XX_IRQ_ADC 18
37#define SPEAR3XX_IRQ_UART 19
38#define SPEAR3XX_IRQ_SSP 20
39#define SPEAR3XX_IRQ_I2C 21
40#define SPEAR3XX_IRQ_MAC_1 22
41#define SPEAR3XX_IRQ_MAC_2 23
42#define SPEAR3XX_IRQ_USB_DEV 24
43#define SPEAR3XX_IRQ_USB_H_OHCI_0 25
44#define SPEAR3XX_IRQ_USB_H_EHCI_0 26
45#define SPEAR3XX_IRQ_USB_H_EHCI_1 SPEAR3XX_IRQ_USB_H_EHCI_0
46#define SPEAR3XX_IRQ_USB_H_OHCI_1 27
47#define SPEAR3XX_IRQ_GEN_RAS_1 28 19#define SPEAR3XX_IRQ_GEN_RAS_1 28
48#define SPEAR3XX_IRQ_GEN_RAS_2 29 20#define SPEAR3XX_IRQ_GEN_RAS_2 29
49#define SPEAR3XX_IRQ_GEN_RAS_3 30 21#define SPEAR3XX_IRQ_GEN_RAS_3 30
50#define SPEAR3XX_IRQ_HW_ACCEL_MOD_1 31
51#define SPEAR3XX_IRQ_VIC_END 32 22#define SPEAR3XX_IRQ_VIC_END 32
52
53#define SPEAR3XX_VIRQ_START SPEAR3XX_IRQ_VIC_END 23#define SPEAR3XX_VIRQ_START SPEAR3XX_IRQ_VIC_END
54 24
55/* SPEAr300 Virtual irq definitions */ 25#define NR_IRQS 160
56/* IRQs sharing IRQ_GEN_RAS_1 */
57#define SPEAR300_VIRQ_IT_PERS_S (SPEAR3XX_VIRQ_START + 0)
58#define SPEAR300_VIRQ_IT_CHANGE_S (SPEAR3XX_VIRQ_START + 1)
59#define SPEAR300_VIRQ_I2S (SPEAR3XX_VIRQ_START + 2)
60#define SPEAR300_VIRQ_TDM (SPEAR3XX_VIRQ_START + 3)
61#define SPEAR300_VIRQ_CAMERA_L (SPEAR3XX_VIRQ_START + 4)
62#define SPEAR300_VIRQ_CAMERA_F (SPEAR3XX_VIRQ_START + 5)
63#define SPEAR300_VIRQ_CAMERA_V (SPEAR3XX_VIRQ_START + 6)
64#define SPEAR300_VIRQ_KEYBOARD (SPEAR3XX_VIRQ_START + 7)
65#define SPEAR300_VIRQ_GPIO1 (SPEAR3XX_VIRQ_START + 8)
66
67/* IRQs sharing IRQ_GEN_RAS_3 */
68#define SPEAR300_IRQ_CLCD SPEAR3XX_IRQ_GEN_RAS_3
69
70/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
71#define SPEAR300_IRQ_SDHCI SPEAR3XX_IRQ_INTRCOMM_RAS_ARM
72
73/* SPEAr310 Virtual irq definitions */
74/* IRQs sharing IRQ_GEN_RAS_1 */
75#define SPEAR310_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 0)
76#define SPEAR310_VIRQ_SMII1 (SPEAR3XX_VIRQ_START + 1)
77#define SPEAR310_VIRQ_SMII2 (SPEAR3XX_VIRQ_START + 2)
78#define SPEAR310_VIRQ_SMII3 (SPEAR3XX_VIRQ_START + 3)
79#define SPEAR310_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 4)
80#define SPEAR310_VIRQ_WAKEUP_SMII1 (SPEAR3XX_VIRQ_START + 5)
81#define SPEAR310_VIRQ_WAKEUP_SMII2 (SPEAR3XX_VIRQ_START + 6)
82#define SPEAR310_VIRQ_WAKEUP_SMII3 (SPEAR3XX_VIRQ_START + 7)
83
84/* IRQs sharing IRQ_GEN_RAS_2 */
85#define SPEAR310_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
86#define SPEAR310_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
87#define SPEAR310_VIRQ_UART3 (SPEAR3XX_VIRQ_START + 10)
88#define SPEAR310_VIRQ_UART4 (SPEAR3XX_VIRQ_START + 11)
89#define SPEAR310_VIRQ_UART5 (SPEAR3XX_VIRQ_START + 12)
90
91/* IRQs sharing IRQ_GEN_RAS_3 */
92#define SPEAR310_VIRQ_EMI (SPEAR3XX_VIRQ_START + 13)
93#define SPEAR310_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 14)
94
95/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
96#define SPEAR310_VIRQ_TDM_HDLC (SPEAR3XX_VIRQ_START + 15)
97#define SPEAR310_VIRQ_RS485_0 (SPEAR3XX_VIRQ_START + 16)
98#define SPEAR310_VIRQ_RS485_1 (SPEAR3XX_VIRQ_START + 17)
99
100/* SPEAr320 Virtual irq definitions */
101/* IRQs sharing IRQ_GEN_RAS_1 */
102#define SPEAR320_VIRQ_EMI (SPEAR3XX_VIRQ_START + 0)
103#define SPEAR320_VIRQ_CLCD (SPEAR3XX_VIRQ_START + 1)
104#define SPEAR320_VIRQ_SPP (SPEAR3XX_VIRQ_START + 2)
105
106/* IRQs sharing IRQ_GEN_RAS_2 */
107#define SPEAR320_IRQ_SDHCI SPEAR3XX_IRQ_GEN_RAS_2
108
109/* IRQs sharing IRQ_GEN_RAS_3 */
110#define SPEAR320_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 3)
111#define SPEAR320_VIRQ_I2S_PLAY (SPEAR3XX_VIRQ_START + 4)
112#define SPEAR320_VIRQ_I2S_REC (SPEAR3XX_VIRQ_START + 5)
113
114/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
115#define SPEAR320_VIRQ_CANU (SPEAR3XX_VIRQ_START + 6)
116#define SPEAR320_VIRQ_CANL (SPEAR3XX_VIRQ_START + 7)
117#define SPEAR320_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
118#define SPEAR320_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
119#define SPEAR320_VIRQ_SSP1 (SPEAR3XX_VIRQ_START + 10)
120#define SPEAR320_VIRQ_SSP2 (SPEAR3XX_VIRQ_START + 11)
121#define SPEAR320_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 12)
122#define SPEAR320_VIRQ_MII1_SMII1 (SPEAR3XX_VIRQ_START + 13)
123#define SPEAR320_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 14)
124#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1 (SPEAR3XX_VIRQ_START + 15)
125#define SPEAR320_VIRQ_I2C1 (SPEAR3XX_VIRQ_START + 16)
126
127/*
128 * GPIO pins virtual irqs
129 * Use the lowest number for the GPIO virtual IRQs base on which subarchs
130 * we have compiled in
131 */
132#if defined(CONFIG_MACH_SPEAR310)
133#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 18)
134#elif defined(CONFIG_MACH_SPEAR320)
135#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 17)
136#else
137#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 9)
138#endif
139
140#define SPEAR300_GPIO1_INT_BASE (SPEAR3XX_GPIO_INT_BASE + 8)
141#define SPEAR3XX_PLGPIO_COUNT 102
142
143#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
144#define SPEAR3XX_PLGPIO_INT_BASE (SPEAR3XX_GPIO_INT_BASE + 8)
145#define SPEAR3XX_GPIO_INT_END (SPEAR3XX_PLGPIO_INT_BASE + \
146 SPEAR3XX_PLGPIO_COUNT)
147#else
148#define SPEAR3XX_GPIO_INT_END (SPEAR300_GPIO1_INT_BASE + 8)
149#endif
150
151#define SPEAR3XX_VIRQ_END SPEAR3XX_GPIO_INT_END
152#define NR_IRQS SPEAR3XX_VIRQ_END
153 26
154#endif /* __MACH_IRQS_H */ 27#endif /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/misc_regs.h b/arch/arm/mach-spear3xx/include/mach/misc_regs.h
index 5bd8cd8d4852..18e2ac576f25 100644
--- a/arch/arm/mach-spear3xx/include/mach/misc_regs.h
+++ b/arch/arm/mach-spear3xx/include/mach/misc_regs.h
@@ -14,151 +14,9 @@
14#ifndef __MACH_MISC_REGS_H 14#ifndef __MACH_MISC_REGS_H
15#define __MACH_MISC_REGS_H 15#define __MACH_MISC_REGS_H
16 16
17#include <mach/hardware.h> 17#include <mach/spear.h>
18 18
19#define MISC_BASE IOMEM(VA_SPEAR3XX_ICM3_MISC_REG_BASE) 19#define MISC_BASE IOMEM(VA_SPEAR3XX_ICM3_MISC_REG_BASE)
20
21#define SOC_CFG_CTR (MISC_BASE + 0x000)
22#define DIAG_CFG_CTR (MISC_BASE + 0x004)
23#define PLL1_CTR (MISC_BASE + 0x008)
24#define PLL1_FRQ (MISC_BASE + 0x00C)
25#define PLL1_MOD (MISC_BASE + 0x010)
26#define PLL2_CTR (MISC_BASE + 0x014)
27/* PLL_CTR register masks */
28#define PLL_ENABLE 2
29#define PLL_MODE_SHIFT 4
30#define PLL_MODE_MASK 0x3
31#define PLL_MODE_NORMAL 0
32#define PLL_MODE_FRACTION 1
33#define PLL_MODE_DITH_DSB 2
34#define PLL_MODE_DITH_SSB 3
35
36#define PLL2_FRQ (MISC_BASE + 0x018)
37/* PLL FRQ register masks */
38#define PLL_DIV_N_SHIFT 0
39#define PLL_DIV_N_MASK 0xFF
40#define PLL_DIV_P_SHIFT 8
41#define PLL_DIV_P_MASK 0x7
42#define PLL_NORM_FDBK_M_SHIFT 24
43#define PLL_NORM_FDBK_M_MASK 0xFF
44#define PLL_DITH_FDBK_M_SHIFT 16
45#define PLL_DITH_FDBK_M_MASK 0xFFFF
46
47#define PLL2_MOD (MISC_BASE + 0x01C)
48#define PLL_CLK_CFG (MISC_BASE + 0x020)
49#define CORE_CLK_CFG (MISC_BASE + 0x024)
50/* CORE CLK CFG register masks */
51#define PLL_HCLK_RATIO_SHIFT 10
52#define PLL_HCLK_RATIO_MASK 0x3
53#define HCLK_PCLK_RATIO_SHIFT 8
54#define HCLK_PCLK_RATIO_MASK 0x3
55
56#define PERIP_CLK_CFG (MISC_BASE + 0x028)
57/* PERIP_CLK_CFG register masks */
58#define UART_CLK_SHIFT 4
59#define UART_CLK_MASK 0x1
60#define FIRDA_CLK_SHIFT 5
61#define FIRDA_CLK_MASK 0x3
62#define GPT0_CLK_SHIFT 8
63#define GPT1_CLK_SHIFT 11
64#define GPT2_CLK_SHIFT 12
65#define GPT_CLK_MASK 0x1
66#define AUX_CLK_PLL3_VAL 0
67#define AUX_CLK_PLL1_VAL 1
68
69#define PERIP1_CLK_ENB (MISC_BASE + 0x02C)
70/* PERIP1_CLK_ENB register masks */
71#define UART_CLK_ENB 3
72#define SSP_CLK_ENB 5
73#define I2C_CLK_ENB 7
74#define JPEG_CLK_ENB 8
75#define FIRDA_CLK_ENB 10
76#define GPT1_CLK_ENB 11
77#define GPT2_CLK_ENB 12
78#define ADC_CLK_ENB 15
79#define RTC_CLK_ENB 17
80#define GPIO_CLK_ENB 18
81#define DMA_CLK_ENB 19
82#define SMI_CLK_ENB 21
83#define GMAC_CLK_ENB 23
84#define USBD_CLK_ENB 24
85#define USBH_CLK_ENB 25
86#define C3_CLK_ENB 31
87
88#define SOC_CORE_ID (MISC_BASE + 0x030)
89#define RAS_CLK_ENB (MISC_BASE + 0x034)
90#define PERIP1_SOF_RST (MISC_BASE + 0x038)
91/* PERIP1_SOF_RST register masks */
92#define JPEG_SOF_RST 8
93
94#define SOC_USER_ID (MISC_BASE + 0x03C)
95#define RAS_SOF_RST (MISC_BASE + 0x040)
96#define PRSC1_CLK_CFG (MISC_BASE + 0x044)
97#define PRSC2_CLK_CFG (MISC_BASE + 0x048)
98#define PRSC3_CLK_CFG (MISC_BASE + 0x04C)
99/* gpt synthesizer register masks */
100#define GPT_MSCALE_SHIFT 0
101#define GPT_MSCALE_MASK 0xFFF
102#define GPT_NSCALE_SHIFT 12
103#define GPT_NSCALE_MASK 0xF
104
105#define AMEM_CLK_CFG (MISC_BASE + 0x050)
106#define EXPI_CLK_CFG (MISC_BASE + 0x054)
107#define CLCD_CLK_SYNT (MISC_BASE + 0x05C)
108#define FIRDA_CLK_SYNT (MISC_BASE + 0x060)
109#define UART_CLK_SYNT (MISC_BASE + 0x064)
110#define GMAC_CLK_SYNT (MISC_BASE + 0x068)
111#define RAS1_CLK_SYNT (MISC_BASE + 0x06C)
112#define RAS2_CLK_SYNT (MISC_BASE + 0x070)
113#define RAS3_CLK_SYNT (MISC_BASE + 0x074)
114#define RAS4_CLK_SYNT (MISC_BASE + 0x078)
115/* aux clk synthesiser register masks for irda to ras4 */
116#define AUX_SYNT_ENB 31
117#define AUX_EQ_SEL_SHIFT 30
118#define AUX_EQ_SEL_MASK 1
119#define AUX_EQ1_SEL 0
120#define AUX_EQ2_SEL 1
121#define AUX_XSCALE_SHIFT 16
122#define AUX_XSCALE_MASK 0xFFF
123#define AUX_YSCALE_SHIFT 0
124#define AUX_YSCALE_MASK 0xFFF
125
126#define ICM1_ARB_CFG (MISC_BASE + 0x07C)
127#define ICM2_ARB_CFG (MISC_BASE + 0x080)
128#define ICM3_ARB_CFG (MISC_BASE + 0x084)
129#define ICM4_ARB_CFG (MISC_BASE + 0x088)
130#define ICM5_ARB_CFG (MISC_BASE + 0x08C)
131#define ICM6_ARB_CFG (MISC_BASE + 0x090)
132#define ICM7_ARB_CFG (MISC_BASE + 0x094)
133#define ICM8_ARB_CFG (MISC_BASE + 0x098)
134#define ICM9_ARB_CFG (MISC_BASE + 0x09C)
135#define DMA_CHN_CFG (MISC_BASE + 0x0A0) 20#define DMA_CHN_CFG (MISC_BASE + 0x0A0)
136#define USB2_PHY_CFG (MISC_BASE + 0x0A4)
137#define GMAC_CFG_CTR (MISC_BASE + 0x0A8)
138#define EXPI_CFG_CTR (MISC_BASE + 0x0AC)
139#define PRC1_LOCK_CTR (MISC_BASE + 0x0C0)
140#define PRC2_LOCK_CTR (MISC_BASE + 0x0C4)
141#define PRC3_LOCK_CTR (MISC_BASE + 0x0C8)
142#define PRC4_LOCK_CTR (MISC_BASE + 0x0CC)
143#define PRC1_IRQ_CTR (MISC_BASE + 0x0D0)
144#define PRC2_IRQ_CTR (MISC_BASE + 0x0D4)
145#define PRC3_IRQ_CTR (MISC_BASE + 0x0D8)
146#define PRC4_IRQ_CTR (MISC_BASE + 0x0DC)
147#define PWRDOWN_CFG_CTR (MISC_BASE + 0x0E0)
148#define COMPSSTL_1V8_CFG (MISC_BASE + 0x0E4)
149#define COMPSSTL_2V5_CFG (MISC_BASE + 0x0E8)
150#define COMPCOR_3V3_CFG (MISC_BASE + 0x0EC)
151#define SSTLPAD_CFG_CTR (MISC_BASE + 0x0F0)
152#define BIST1_CFG_CTR (MISC_BASE + 0x0F4)
153#define BIST2_CFG_CTR (MISC_BASE + 0x0F8)
154#define BIST3_CFG_CTR (MISC_BASE + 0x0FC)
155#define BIST4_CFG_CTR (MISC_BASE + 0x100)
156#define BIST5_CFG_CTR (MISC_BASE + 0x104)
157#define BIST1_STS_RES (MISC_BASE + 0x108)
158#define BIST2_STS_RES (MISC_BASE + 0x10C)
159#define BIST3_STS_RES (MISC_BASE + 0x110)
160#define BIST4_STS_RES (MISC_BASE + 0x114)
161#define BIST5_STS_RES (MISC_BASE + 0x118)
162#define SYSERR_CFG_CTR (MISC_BASE + 0x11C)
163 21
164#endif /* __MACH_MISC_REGS_H */ 22#endif /* __MACH_MISC_REGS_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear.h b/arch/arm/mach-spear3xx/include/mach/spear.h
index 63fd98356919..51eb953148a9 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear.h
@@ -15,60 +15,26 @@
15#define __MACH_SPEAR3XX_H 15#define __MACH_SPEAR3XX_H
16 16
17#include <asm/memory.h> 17#include <asm/memory.h>
18#include <mach/spear300.h>
19#include <mach/spear310.h>
20#include <mach/spear320.h>
21
22#define SPEAR3XX_ML_SDRAM_BASE UL(0x00000000)
23
24#define SPEAR3XX_ICM9_BASE UL(0xC0000000)
25 18
26/* ICM1 - Low speed connection */ 19/* ICM1 - Low speed connection */
27#define SPEAR3XX_ICM1_2_BASE UL(0xD0000000) 20#define SPEAR3XX_ICM1_2_BASE UL(0xD0000000)
21#define VA_SPEAR3XX_ICM1_2_BASE UL(0xFD000000)
28#define SPEAR3XX_ICM1_UART_BASE UL(0xD0000000) 22#define SPEAR3XX_ICM1_UART_BASE UL(0xD0000000)
29#define VA_SPEAR3XX_ICM1_UART_BASE IO_ADDRESS(SPEAR3XX_ICM1_UART_BASE) 23#define VA_SPEAR3XX_ICM1_UART_BASE (VA_SPEAR3XX_ICM1_2_BASE | SPEAR3XX_ICM1_UART_BASE)
30#define SPEAR3XX_ICM1_ADC_BASE UL(0xD0080000)
31#define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000) 24#define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000)
32#define SPEAR3XX_ICM1_I2C_BASE UL(0xD0180000)
33#define SPEAR3XX_ICM1_JPEG_BASE UL(0xD0800000)
34#define SPEAR3XX_ICM1_IRDA_BASE UL(0xD1000000)
35#define SPEAR3XX_ICM1_SRAM_BASE UL(0xD2800000)
36
37/* ICM2 - Application Subsystem */
38#define SPEAR3XX_ICM2_HWACCEL0_BASE UL(0xD8800000)
39#define SPEAR3XX_ICM2_HWACCEL1_BASE UL(0xD9000000)
40
41/* ICM4 - High Speed Connection */
42#define SPEAR3XX_ICM4_BASE UL(0xE0000000)
43#define SPEAR3XX_ICM4_MII_BASE UL(0xE0800000)
44#define SPEAR3XX_ICM4_USBD_FIFO_BASE UL(0xE1000000)
45#define SPEAR3XX_ICM4_USBD_CSR_BASE UL(0xE1100000)
46#define SPEAR3XX_ICM4_USBD_PLDT_BASE UL(0xE1200000)
47#define SPEAR3XX_ICM4_USB_EHCI0_1_BASE UL(0xE1800000)
48#define SPEAR3XX_ICM4_USB_OHCI0_BASE UL(0xE1900000)
49#define SPEAR3XX_ICM4_USB_OHCI1_BASE UL(0xE2100000)
50#define SPEAR3XX_ICM4_USB_ARB_BASE UL(0xE2800000)
51 25
52/* ML1 - Multi Layer CPU Subsystem */ 26/* ML1 - Multi Layer CPU Subsystem */
53#define SPEAR3XX_ICM3_ML1_2_BASE UL(0xF0000000) 27#define SPEAR3XX_ICM3_ML1_2_BASE UL(0xF0000000)
54#define SPEAR3XX_ML1_TMR_BASE UL(0xF0000000) 28#define VA_SPEAR6XX_ML_CPU_BASE UL(0xF0000000)
55#define SPEAR3XX_ML1_VIC_BASE UL(0xF1100000)
56#define VA_SPEAR3XX_ML1_VIC_BASE IO_ADDRESS(SPEAR3XX_ML1_VIC_BASE)
57 29
58/* ICM3 - Basic Subsystem */ 30/* ICM3 - Basic Subsystem */
59#define SPEAR3XX_ICM3_SMEM_BASE UL(0xF8000000)
60#define SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000) 31#define SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
32#define VA_SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
61#define SPEAR3XX_ICM3_DMA_BASE UL(0xFC400000) 33#define SPEAR3XX_ICM3_DMA_BASE UL(0xFC400000)
62#define SPEAR3XX_ICM3_SDRAM_CTRL_BASE UL(0xFC600000)
63#define SPEAR3XX_ICM3_TMR0_BASE UL(0xFC800000)
64#define SPEAR3XX_ICM3_WDT_BASE UL(0xFC880000)
65#define SPEAR3XX_ICM3_RTC_BASE UL(0xFC900000)
66#define SPEAR3XX_ICM3_GPIO_BASE UL(0xFC980000)
67#define SPEAR3XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000) 34#define SPEAR3XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000)
68#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR3XX_ICM3_SYS_CTRL_BASE) 35#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_SYS_CTRL_BASE)
69#define SPEAR3XX_ICM3_MISC_REG_BASE UL(0xFCA80000) 36#define SPEAR3XX_ICM3_MISC_REG_BASE UL(0xFCA80000)
70#define VA_SPEAR3XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR3XX_ICM3_MISC_REG_BASE) 37#define VA_SPEAR3XX_ICM3_MISC_REG_BASE (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_MISC_REG_BASE)
71#define SPEAR3XX_ICM3_TMR1_BASE UL(0xFCB00000)
72 38
73/* Debug uart for linux, will be used for debug and uncompress messages */ 39/* Debug uart for linux, will be used for debug and uncompress messages */
74#define SPEAR_DBG_UART_BASE SPEAR3XX_ICM1_UART_BASE 40#define SPEAR_DBG_UART_BASE SPEAR3XX_ICM1_UART_BASE
@@ -78,4 +44,17 @@
78#define SPEAR_SYS_CTRL_BASE SPEAR3XX_ICM3_SYS_CTRL_BASE 44#define SPEAR_SYS_CTRL_BASE SPEAR3XX_ICM3_SYS_CTRL_BASE
79#define VA_SPEAR_SYS_CTRL_BASE VA_SPEAR3XX_ICM3_SYS_CTRL_BASE 45#define VA_SPEAR_SYS_CTRL_BASE VA_SPEAR3XX_ICM3_SYS_CTRL_BASE
80 46
47/* SPEAr320 Macros */
48#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000)
49#define VA_SPEAR320_SOC_CONFIG_BASE UL(0xFE000000)
50#define SPEAR320_CONTROL_REG IOMEM(VA_SPEAR320_SOC_CONFIG_BASE)
51#define SPEAR320_EXT_CTRL_REG IOMEM(VA_SPEAR320_SOC_CONFIG_BASE + 0x0018)
52 #define SPEAR320_UARTX_PCLK_MASK 0x1
53 #define SPEAR320_UART2_PCLK_SHIFT 8
54 #define SPEAR320_UART3_PCLK_SHIFT 9
55 #define SPEAR320_UART4_PCLK_SHIFT 10
56 #define SPEAR320_UART5_PCLK_SHIFT 11
57 #define SPEAR320_UART6_PCLK_SHIFT 12
58 #define SPEAR320_RS485_PCLK_SHIFT 13
59
81#endif /* __MACH_SPEAR3XX_H */ 60#endif /* __MACH_SPEAR3XX_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear300.h b/arch/arm/mach-spear3xx/include/mach/spear300.h
deleted file mode 100644
index 3b6ea0729040..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/spear300.h
+++ /dev/null
@@ -1,54 +0,0 @@
1/*
2 * arch/arm/mach-spear3xx/include/mach/spear300.h
3 *
4 * SPEAr300 Machine specific definition
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifdef CONFIG_MACH_SPEAR300
15
16#ifndef __MACH_SPEAR300_H
17#define __MACH_SPEAR300_H
18
19/* Base address of various IPs */
20#define SPEAR300_TELECOM_BASE UL(0x50000000)
21
22/* Interrupt registers offsets and masks */
23#define SPEAR300_INT_ENB_MASK_REG 0x54
24#define SPEAR300_INT_STS_MASK_REG 0x58
25#define SPEAR300_IT_PERS_S_IRQ_MASK (1 << 0)
26#define SPEAR300_IT_CHANGE_S_IRQ_MASK (1 << 1)
27#define SPEAR300_I2S_IRQ_MASK (1 << 2)
28#define SPEAR300_TDM_IRQ_MASK (1 << 3)
29#define SPEAR300_CAMERA_L_IRQ_MASK (1 << 4)
30#define SPEAR300_CAMERA_F_IRQ_MASK (1 << 5)
31#define SPEAR300_CAMERA_V_IRQ_MASK (1 << 6)
32#define SPEAR300_KEYBOARD_IRQ_MASK (1 << 7)
33#define SPEAR300_GPIO1_IRQ_MASK (1 << 8)
34
35#define SPEAR300_SHIRQ_RAS1_MASK 0x1FF
36
37#define SPEAR300_CLCD_BASE UL(0x60000000)
38#define SPEAR300_SDHCI_BASE UL(0x70000000)
39#define SPEAR300_NAND_0_BASE UL(0x80000000)
40#define SPEAR300_NAND_1_BASE UL(0x84000000)
41#define SPEAR300_NAND_2_BASE UL(0x88000000)
42#define SPEAR300_NAND_3_BASE UL(0x8c000000)
43#define SPEAR300_NOR_0_BASE UL(0x90000000)
44#define SPEAR300_NOR_1_BASE UL(0x91000000)
45#define SPEAR300_NOR_2_BASE UL(0x92000000)
46#define SPEAR300_NOR_3_BASE UL(0x93000000)
47#define SPEAR300_FSMC_BASE UL(0x94000000)
48#define SPEAR300_SOC_CONFIG_BASE UL(0x99000000)
49#define SPEAR300_KEYBOARD_BASE UL(0xA0000000)
50#define SPEAR300_GPIO_BASE UL(0xA9000000)
51
52#endif /* __MACH_SPEAR300_H */
53
54#endif /* CONFIG_MACH_SPEAR300 */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear310.h b/arch/arm/mach-spear3xx/include/mach/spear310.h
deleted file mode 100644
index 1567d0da725f..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/spear310.h
+++ /dev/null
@@ -1,58 +0,0 @@
1/*
2 * arch/arm/mach-spear3xx/include/mach/spear310.h
3 *
4 * SPEAr310 Machine specific definition
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifdef CONFIG_MACH_SPEAR310
15
16#ifndef __MACH_SPEAR310_H
17#define __MACH_SPEAR310_H
18
19#define SPEAR310_NAND_BASE UL(0x40000000)
20#define SPEAR310_FSMC_BASE UL(0x44000000)
21#define SPEAR310_UART1_BASE UL(0xB2000000)
22#define SPEAR310_UART2_BASE UL(0xB2080000)
23#define SPEAR310_UART3_BASE UL(0xB2100000)
24#define SPEAR310_UART4_BASE UL(0xB2180000)
25#define SPEAR310_UART5_BASE UL(0xB2200000)
26#define SPEAR310_HDLC_BASE UL(0xB2800000)
27#define SPEAR310_RS485_0_BASE UL(0xB3000000)
28#define SPEAR310_RS485_1_BASE UL(0xB3800000)
29#define SPEAR310_SOC_CONFIG_BASE UL(0xB4000000)
30
31/* Interrupt registers offsets and masks */
32#define SPEAR310_INT_STS_MASK_REG 0x04
33#define SPEAR310_SMII0_IRQ_MASK (1 << 0)
34#define SPEAR310_SMII1_IRQ_MASK (1 << 1)
35#define SPEAR310_SMII2_IRQ_MASK (1 << 2)
36#define SPEAR310_SMII3_IRQ_MASK (1 << 3)
37#define SPEAR310_WAKEUP_SMII0_IRQ_MASK (1 << 4)
38#define SPEAR310_WAKEUP_SMII1_IRQ_MASK (1 << 5)
39#define SPEAR310_WAKEUP_SMII2_IRQ_MASK (1 << 6)
40#define SPEAR310_WAKEUP_SMII3_IRQ_MASK (1 << 7)
41#define SPEAR310_UART1_IRQ_MASK (1 << 8)
42#define SPEAR310_UART2_IRQ_MASK (1 << 9)
43#define SPEAR310_UART3_IRQ_MASK (1 << 10)
44#define SPEAR310_UART4_IRQ_MASK (1 << 11)
45#define SPEAR310_UART5_IRQ_MASK (1 << 12)
46#define SPEAR310_EMI_IRQ_MASK (1 << 13)
47#define SPEAR310_TDM_HDLC_IRQ_MASK (1 << 14)
48#define SPEAR310_RS485_0_IRQ_MASK (1 << 15)
49#define SPEAR310_RS485_1_IRQ_MASK (1 << 16)
50
51#define SPEAR310_SHIRQ_RAS1_MASK 0x000FF
52#define SPEAR310_SHIRQ_RAS2_MASK 0x01F00
53#define SPEAR310_SHIRQ_RAS3_MASK 0x02000
54#define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK 0x1C000
55
56#endif /* __MACH_SPEAR310_H */
57
58#endif /* CONFIG_MACH_SPEAR310 */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear320.h b/arch/arm/mach-spear3xx/include/mach/spear320.h
deleted file mode 100644
index 8cfa83fa1296..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/spear320.h
+++ /dev/null
@@ -1,67 +0,0 @@
1/*
2 * arch/arm/mach-spear3xx/include/mach/spear320.h
3 *
4 * SPEAr320 Machine specific definition
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifdef CONFIG_MACH_SPEAR320
15
16#ifndef __MACH_SPEAR320_H
17#define __MACH_SPEAR320_H
18
19#define SPEAR320_EMI_CTRL_BASE UL(0x40000000)
20#define SPEAR320_FSMC_BASE UL(0x4C000000)
21#define SPEAR320_NAND_BASE UL(0x50000000)
22#define SPEAR320_I2S_BASE UL(0x60000000)
23#define SPEAR320_SDHCI_BASE UL(0x70000000)
24#define SPEAR320_CLCD_BASE UL(0x90000000)
25#define SPEAR320_PAR_PORT_BASE UL(0xA0000000)
26#define SPEAR320_CAN0_BASE UL(0xA1000000)
27#define SPEAR320_CAN1_BASE UL(0xA2000000)
28#define SPEAR320_UART1_BASE UL(0xA3000000)
29#define SPEAR320_UART2_BASE UL(0xA4000000)
30#define SPEAR320_SSP0_BASE UL(0xA5000000)
31#define SPEAR320_SSP1_BASE UL(0xA6000000)
32#define SPEAR320_I2C_BASE UL(0xA7000000)
33#define SPEAR320_PWM_BASE UL(0xA8000000)
34#define SPEAR320_SMII0_BASE UL(0xAA000000)
35#define SPEAR320_SMII1_BASE UL(0xAB000000)
36#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000)
37
38/* Interrupt registers offsets and masks */
39#define SPEAR320_INT_STS_MASK_REG 0x04
40#define SPEAR320_INT_CLR_MASK_REG 0x04
41#define SPEAR320_INT_ENB_MASK_REG 0x08
42#define SPEAR320_GPIO_IRQ_MASK (1 << 0)
43#define SPEAR320_I2S_PLAY_IRQ_MASK (1 << 1)
44#define SPEAR320_I2S_REC_IRQ_MASK (1 << 2)
45#define SPEAR320_EMI_IRQ_MASK (1 << 7)
46#define SPEAR320_CLCD_IRQ_MASK (1 << 8)
47#define SPEAR320_SPP_IRQ_MASK (1 << 9)
48#define SPEAR320_SDHCI_IRQ_MASK (1 << 10)
49#define SPEAR320_CAN_U_IRQ_MASK (1 << 11)
50#define SPEAR320_CAN_L_IRQ_MASK (1 << 12)
51#define SPEAR320_UART1_IRQ_MASK (1 << 13)
52#define SPEAR320_UART2_IRQ_MASK (1 << 14)
53#define SPEAR320_SSP1_IRQ_MASK (1 << 15)
54#define SPEAR320_SSP2_IRQ_MASK (1 << 16)
55#define SPEAR320_SMII0_IRQ_MASK (1 << 17)
56#define SPEAR320_MII1_SMII1_IRQ_MASK (1 << 18)
57#define SPEAR320_WAKEUP_SMII0_IRQ_MASK (1 << 19)
58#define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK (1 << 20)
59#define SPEAR320_I2C1_IRQ_MASK (1 << 21)
60
61#define SPEAR320_SHIRQ_RAS1_MASK 0x000380
62#define SPEAR320_SHIRQ_RAS3_MASK 0x000007
63#define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK 0x3FF800
64
65#endif /* __MACH_SPEAR320_H */
66
67#endif /* CONFIG_MACH_SPEAR320 */
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index f7db66812abb..f74a05bdb829 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -3,372 +3,62 @@
3 * 3 *
4 * SPEAr300 machine source file 4 * SPEAr300 machine source file
5 * 5 *
6 * Copyright (C) 2009 ST Microelectronics 6 * Copyright (C) 2009-2012 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com> 7 * Viresh Kumar <viresh.kumar@st.com>
8 * 8 *
9 * This file is licensed under the terms of the GNU General Public 9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any 10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied. 11 * warranty of any kind, whether express or implied.
12 */ 12 */
13 13
14#include <linux/types.h> 14#define pr_fmt(fmt) "SPEAr300: " fmt
15#include <linux/amba/pl061.h> 15
16#include <linux/ptrace.h> 16#include <linux/amba/pl08x.h>
17#include <asm/irq.h> 17#include <linux/of_platform.h>
18#include <asm/hardware/vic.h>
19#include <asm/mach/arch.h>
18#include <plat/shirq.h> 20#include <plat/shirq.h>
19#include <mach/generic.h> 21#include <mach/generic.h>
20#include <mach/hardware.h> 22#include <mach/spear.h>
21 23
22/* pad multiplexing support */ 24/* Base address of various IPs */
23/* muxing registers */ 25#define SPEAR300_TELECOM_BASE UL(0x50000000)
24#define PAD_MUX_CONFIG_REG 0x00 26
25#define MODE_CONFIG_REG 0x04 27/* Interrupt registers offsets and masks */
26 28#define SPEAR300_INT_ENB_MASK_REG 0x54
27/* modes */ 29#define SPEAR300_INT_STS_MASK_REG 0x58
28#define NAND_MODE (1 << 0) 30#define SPEAR300_IT_PERS_S_IRQ_MASK (1 << 0)
29#define NOR_MODE (1 << 1) 31#define SPEAR300_IT_CHANGE_S_IRQ_MASK (1 << 1)
30#define PHOTO_FRAME_MODE (1 << 2) 32#define SPEAR300_I2S_IRQ_MASK (1 << 2)
31#define LEND_IP_PHONE_MODE (1 << 3) 33#define SPEAR300_TDM_IRQ_MASK (1 << 3)
32#define HEND_IP_PHONE_MODE (1 << 4) 34#define SPEAR300_CAMERA_L_IRQ_MASK (1 << 4)
33#define LEND_WIFI_PHONE_MODE (1 << 5) 35#define SPEAR300_CAMERA_F_IRQ_MASK (1 << 5)
34#define HEND_WIFI_PHONE_MODE (1 << 6) 36#define SPEAR300_CAMERA_V_IRQ_MASK (1 << 6)
35#define ATA_PABX_WI2S_MODE (1 << 7) 37#define SPEAR300_KEYBOARD_IRQ_MASK (1 << 7)
36#define ATA_PABX_I2S_MODE (1 << 8) 38#define SPEAR300_GPIO1_IRQ_MASK (1 << 8)
37#define CAML_LCDW_MODE (1 << 9) 39
38#define CAMU_LCD_MODE (1 << 10) 40#define SPEAR300_SHIRQ_RAS1_MASK 0x1FF
39#define CAMU_WLCD_MODE (1 << 11) 41
40#define CAML_LCD_MODE (1 << 12) 42#define SPEAR300_SOC_CONFIG_BASE UL(0x99000000)
41#define ALL_MODES 0x1FFF 43
42 44
43struct pmx_mode spear300_nand_mode = { 45/* SPEAr300 Virtual irq definitions */
44 .id = NAND_MODE, 46/* IRQs sharing IRQ_GEN_RAS_1 */
45 .name = "nand mode", 47#define SPEAR300_VIRQ_IT_PERS_S (SPEAR3XX_VIRQ_START + 0)
46 .mask = 0x00, 48#define SPEAR300_VIRQ_IT_CHANGE_S (SPEAR3XX_VIRQ_START + 1)
47}; 49#define SPEAR300_VIRQ_I2S (SPEAR3XX_VIRQ_START + 2)
48 50#define SPEAR300_VIRQ_TDM (SPEAR3XX_VIRQ_START + 3)
49struct pmx_mode spear300_nor_mode = { 51#define SPEAR300_VIRQ_CAMERA_L (SPEAR3XX_VIRQ_START + 4)
50 .id = NOR_MODE, 52#define SPEAR300_VIRQ_CAMERA_F (SPEAR3XX_VIRQ_START + 5)
51 .name = "nor mode", 53#define SPEAR300_VIRQ_CAMERA_V (SPEAR3XX_VIRQ_START + 6)
52 .mask = 0x01, 54#define SPEAR300_VIRQ_KEYBOARD (SPEAR3XX_VIRQ_START + 7)
53}; 55#define SPEAR300_VIRQ_GPIO1 (SPEAR3XX_VIRQ_START + 8)
54 56
55struct pmx_mode spear300_photo_frame_mode = { 57/* IRQs sharing IRQ_GEN_RAS_3 */
56 .id = PHOTO_FRAME_MODE, 58#define SPEAR300_IRQ_CLCD SPEAR3XX_IRQ_GEN_RAS_3
57 .name = "photo frame mode", 59
58 .mask = 0x02, 60/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
59}; 61#define SPEAR300_IRQ_SDHCI SPEAR3XX_IRQ_INTRCOMM_RAS_ARM
60
61struct pmx_mode spear300_lend_ip_phone_mode = {
62 .id = LEND_IP_PHONE_MODE,
63 .name = "lend ip phone mode",
64 .mask = 0x03,
65};
66
67struct pmx_mode spear300_hend_ip_phone_mode = {
68 .id = HEND_IP_PHONE_MODE,
69 .name = "hend ip phone mode",
70 .mask = 0x04,
71};
72
73struct pmx_mode spear300_lend_wifi_phone_mode = {
74 .id = LEND_WIFI_PHONE_MODE,
75 .name = "lend wifi phone mode",
76 .mask = 0x05,
77};
78
79struct pmx_mode spear300_hend_wifi_phone_mode = {
80 .id = HEND_WIFI_PHONE_MODE,
81 .name = "hend wifi phone mode",
82 .mask = 0x06,
83};
84
85struct pmx_mode spear300_ata_pabx_wi2s_mode = {
86 .id = ATA_PABX_WI2S_MODE,
87 .name = "ata pabx wi2s mode",
88 .mask = 0x07,
89};
90
91struct pmx_mode spear300_ata_pabx_i2s_mode = {
92 .id = ATA_PABX_I2S_MODE,
93 .name = "ata pabx i2s mode",
94 .mask = 0x08,
95};
96
97struct pmx_mode spear300_caml_lcdw_mode = {
98 .id = CAML_LCDW_MODE,
99 .name = "caml lcdw mode",
100 .mask = 0x0C,
101};
102
103struct pmx_mode spear300_camu_lcd_mode = {
104 .id = CAMU_LCD_MODE,
105 .name = "camu lcd mode",
106 .mask = 0x0D,
107};
108
109struct pmx_mode spear300_camu_wlcd_mode = {
110 .id = CAMU_WLCD_MODE,
111 .name = "camu wlcd mode",
112 .mask = 0x0E,
113};
114
115struct pmx_mode spear300_caml_lcd_mode = {
116 .id = CAML_LCD_MODE,
117 .name = "caml lcd mode",
118 .mask = 0x0F,
119};
120
121/* devices */
122static struct pmx_dev_mode pmx_fsmc_2_chips_modes[] = {
123 {
124 .ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
125 ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
126 .mask = PMX_FIRDA_MASK,
127 },
128};
129
130struct pmx_dev spear300_pmx_fsmc_2_chips = {
131 .name = "fsmc_2_chips",
132 .modes = pmx_fsmc_2_chips_modes,
133 .mode_count = ARRAY_SIZE(pmx_fsmc_2_chips_modes),
134 .enb_on_reset = 1,
135};
136
137static struct pmx_dev_mode pmx_fsmc_4_chips_modes[] = {
138 {
139 .ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
140 ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
141 .mask = PMX_FIRDA_MASK | PMX_UART0_MASK,
142 },
143};
144
145struct pmx_dev spear300_pmx_fsmc_4_chips = {
146 .name = "fsmc_4_chips",
147 .modes = pmx_fsmc_4_chips_modes,
148 .mode_count = ARRAY_SIZE(pmx_fsmc_4_chips_modes),
149 .enb_on_reset = 1,
150};
151
152static struct pmx_dev_mode pmx_keyboard_modes[] = {
153 {
154 .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
155 LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
156 CAML_LCDW_MODE | CAMU_LCD_MODE | CAMU_WLCD_MODE |
157 CAML_LCD_MODE,
158 .mask = 0x0,
159 },
160};
161
162struct pmx_dev spear300_pmx_keyboard = {
163 .name = "keyboard",
164 .modes = pmx_keyboard_modes,
165 .mode_count = ARRAY_SIZE(pmx_keyboard_modes),
166 .enb_on_reset = 1,
167};
168
169static struct pmx_dev_mode pmx_clcd_modes[] = {
170 {
171 .ids = PHOTO_FRAME_MODE,
172 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK ,
173 }, {
174 .ids = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE |
175 CAMU_LCD_MODE | CAML_LCD_MODE,
176 .mask = PMX_TIMER_3_4_MASK,
177 },
178};
179
180struct pmx_dev spear300_pmx_clcd = {
181 .name = "clcd",
182 .modes = pmx_clcd_modes,
183 .mode_count = ARRAY_SIZE(pmx_clcd_modes),
184 .enb_on_reset = 1,
185};
186
187static struct pmx_dev_mode pmx_telecom_gpio_modes[] = {
188 {
189 .ids = PHOTO_FRAME_MODE | CAMU_LCD_MODE | CAML_LCD_MODE,
190 .mask = PMX_MII_MASK,
191 }, {
192 .ids = LEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE,
193 .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
194 }, {
195 .ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_WLCD_MODE,
196 .mask = PMX_MII_MASK | PMX_TIMER_3_4_MASK,
197 }, {
198 .ids = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE,
199 .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK,
200 }, {
201 .ids = ATA_PABX_WI2S_MODE,
202 .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK
203 | PMX_UART0_MODEM_MASK,
204 },
205};
206
207struct pmx_dev spear300_pmx_telecom_gpio = {
208 .name = "telecom_gpio",
209 .modes = pmx_telecom_gpio_modes,
210 .mode_count = ARRAY_SIZE(pmx_telecom_gpio_modes),
211 .enb_on_reset = 1,
212};
213
214static struct pmx_dev_mode pmx_telecom_tdm_modes[] = {
215 {
216 .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
217 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE
218 | HEND_WIFI_PHONE_MODE | ATA_PABX_WI2S_MODE
219 | ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
220 | CAMU_WLCD_MODE | CAML_LCD_MODE,
221 .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK,
222 },
223};
224
225struct pmx_dev spear300_pmx_telecom_tdm = {
226 .name = "telecom_tdm",
227 .modes = pmx_telecom_tdm_modes,
228 .mode_count = ARRAY_SIZE(pmx_telecom_tdm_modes),
229 .enb_on_reset = 1,
230};
231
232static struct pmx_dev_mode pmx_telecom_spi_cs_i2c_clk_modes[] = {
233 {
234 .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
235 LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE
236 | ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE |
237 CAML_LCDW_MODE | CAML_LCD_MODE,
238 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
239 },
240};
241
242struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk = {
243 .name = "telecom_spi_cs_i2c_clk",
244 .modes = pmx_telecom_spi_cs_i2c_clk_modes,
245 .mode_count = ARRAY_SIZE(pmx_telecom_spi_cs_i2c_clk_modes),
246 .enb_on_reset = 1,
247};
248
249static struct pmx_dev_mode pmx_telecom_camera_modes[] = {
250 {
251 .ids = CAML_LCDW_MODE | CAML_LCD_MODE,
252 .mask = PMX_MII_MASK,
253 }, {
254 .ids = CAMU_LCD_MODE | CAMU_WLCD_MODE,
255 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK | PMX_MII_MASK,
256 },
257};
258
259struct pmx_dev spear300_pmx_telecom_camera = {
260 .name = "telecom_camera",
261 .modes = pmx_telecom_camera_modes,
262 .mode_count = ARRAY_SIZE(pmx_telecom_camera_modes),
263 .enb_on_reset = 1,
264};
265
266static struct pmx_dev_mode pmx_telecom_dac_modes[] = {
267 {
268 .ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
269 | CAMU_WLCD_MODE | CAML_LCD_MODE,
270 .mask = PMX_TIMER_1_2_MASK,
271 },
272};
273
274struct pmx_dev spear300_pmx_telecom_dac = {
275 .name = "telecom_dac",
276 .modes = pmx_telecom_dac_modes,
277 .mode_count = ARRAY_SIZE(pmx_telecom_dac_modes),
278 .enb_on_reset = 1,
279};
280
281static struct pmx_dev_mode pmx_telecom_i2s_modes[] = {
282 {
283 .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE
284 | LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
285 ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
286 | CAMU_WLCD_MODE | CAML_LCD_MODE,
287 .mask = PMX_UART0_MODEM_MASK,
288 },
289};
290
291struct pmx_dev spear300_pmx_telecom_i2s = {
292 .name = "telecom_i2s",
293 .modes = pmx_telecom_i2s_modes,
294 .mode_count = ARRAY_SIZE(pmx_telecom_i2s_modes),
295 .enb_on_reset = 1,
296};
297
298static struct pmx_dev_mode pmx_telecom_boot_pins_modes[] = {
299 {
300 .ids = NAND_MODE | NOR_MODE,
301 .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK |
302 PMX_TIMER_3_4_MASK,
303 },
304};
305
306struct pmx_dev spear300_pmx_telecom_boot_pins = {
307 .name = "telecom_boot_pins",
308 .modes = pmx_telecom_boot_pins_modes,
309 .mode_count = ARRAY_SIZE(pmx_telecom_boot_pins_modes),
310 .enb_on_reset = 1,
311};
312
313static struct pmx_dev_mode pmx_telecom_sdhci_4bit_modes[] = {
314 {
315 .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
316 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
317 HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
318 CAMU_WLCD_MODE | CAML_LCD_MODE | ATA_PABX_WI2S_MODE |
319 ATA_PABX_I2S_MODE,
320 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
321 PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
322 PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
323 },
324};
325
326struct pmx_dev spear300_pmx_telecom_sdhci_4bit = {
327 .name = "telecom_sdhci_4bit",
328 .modes = pmx_telecom_sdhci_4bit_modes,
329 .mode_count = ARRAY_SIZE(pmx_telecom_sdhci_4bit_modes),
330 .enb_on_reset = 1,
331};
332
333static struct pmx_dev_mode pmx_telecom_sdhci_8bit_modes[] = {
334 {
335 .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
336 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
337 HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
338 CAMU_WLCD_MODE | CAML_LCD_MODE,
339 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
340 PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
341 PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK | PMX_MII_MASK,
342 },
343};
344
345struct pmx_dev spear300_pmx_telecom_sdhci_8bit = {
346 .name = "telecom_sdhci_8bit",
347 .modes = pmx_telecom_sdhci_8bit_modes,
348 .mode_count = ARRAY_SIZE(pmx_telecom_sdhci_8bit_modes),
349 .enb_on_reset = 1,
350};
351
352static struct pmx_dev_mode pmx_gpio1_modes[] = {
353 {
354 .ids = PHOTO_FRAME_MODE,
355 .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK |
356 PMX_TIMER_3_4_MASK,
357 },
358};
359
360struct pmx_dev spear300_pmx_gpio1 = {
361 .name = "arm gpio1",
362 .modes = pmx_gpio1_modes,
363 .mode_count = ARRAY_SIZE(pmx_gpio1_modes),
364 .enb_on_reset = 1,
365};
366
367/* pmx driver structure */
368static struct pmx_driver pmx_driver = {
369 .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x0000000f},
370 .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
371};
372 62
373/* spear3xx shared irq */ 63/* spear3xx shared irq */
374static struct shirq_dev_config shirq_ras1_config[] = { 64static struct shirq_dev_config shirq_ras1_config[] = {
@@ -423,45 +113,238 @@ static struct spear_shirq shirq_ras1 = {
423 }, 113 },
424}; 114};
425 115
426/* Add spear300 specific devices here */ 116/* DMAC platform data's slave info */
427/* arm gpio1 device registration */ 117struct pl08x_channel_data spear300_dma_info[] = {
428static struct pl061_platform_data gpio1_plat_data = { 118 {
429 .gpio_base = 8, 119 .bus_id = "uart0_rx",
430 .irq_base = SPEAR300_GPIO1_INT_BASE, 120 .min_signal = 2,
121 .max_signal = 2,
122 .muxval = 0,
123 .cctl = 0,
124 .periph_buses = PL08X_AHB1,
125 }, {
126 .bus_id = "uart0_tx",
127 .min_signal = 3,
128 .max_signal = 3,
129 .muxval = 0,
130 .cctl = 0,
131 .periph_buses = PL08X_AHB1,
132 }, {
133 .bus_id = "ssp0_rx",
134 .min_signal = 8,
135 .max_signal = 8,
136 .muxval = 0,
137 .cctl = 0,
138 .periph_buses = PL08X_AHB1,
139 }, {
140 .bus_id = "ssp0_tx",
141 .min_signal = 9,
142 .max_signal = 9,
143 .muxval = 0,
144 .cctl = 0,
145 .periph_buses = PL08X_AHB1,
146 }, {
147 .bus_id = "i2c_rx",
148 .min_signal = 10,
149 .max_signal = 10,
150 .muxval = 0,
151 .cctl = 0,
152 .periph_buses = PL08X_AHB1,
153 }, {
154 .bus_id = "i2c_tx",
155 .min_signal = 11,
156 .max_signal = 11,
157 .muxval = 0,
158 .cctl = 0,
159 .periph_buses = PL08X_AHB1,
160 }, {
161 .bus_id = "irda",
162 .min_signal = 12,
163 .max_signal = 12,
164 .muxval = 0,
165 .cctl = 0,
166 .periph_buses = PL08X_AHB1,
167 }, {
168 .bus_id = "adc",
169 .min_signal = 13,
170 .max_signal = 13,
171 .muxval = 0,
172 .cctl = 0,
173 .periph_buses = PL08X_AHB1,
174 }, {
175 .bus_id = "to_jpeg",
176 .min_signal = 14,
177 .max_signal = 14,
178 .muxval = 0,
179 .cctl = 0,
180 .periph_buses = PL08X_AHB1,
181 }, {
182 .bus_id = "from_jpeg",
183 .min_signal = 15,
184 .max_signal = 15,
185 .muxval = 0,
186 .cctl = 0,
187 .periph_buses = PL08X_AHB1,
188 }, {
189 .bus_id = "ras0_rx",
190 .min_signal = 0,
191 .max_signal = 0,
192 .muxval = 1,
193 .cctl = 0,
194 .periph_buses = PL08X_AHB1,
195 }, {
196 .bus_id = "ras0_tx",
197 .min_signal = 1,
198 .max_signal = 1,
199 .muxval = 1,
200 .cctl = 0,
201 .periph_buses = PL08X_AHB1,
202 }, {
203 .bus_id = "ras1_rx",
204 .min_signal = 2,
205 .max_signal = 2,
206 .muxval = 1,
207 .cctl = 0,
208 .periph_buses = PL08X_AHB1,
209 }, {
210 .bus_id = "ras1_tx",
211 .min_signal = 3,
212 .max_signal = 3,
213 .muxval = 1,
214 .cctl = 0,
215 .periph_buses = PL08X_AHB1,
216 }, {
217 .bus_id = "ras2_rx",
218 .min_signal = 4,
219 .max_signal = 4,
220 .muxval = 1,
221 .cctl = 0,
222 .periph_buses = PL08X_AHB1,
223 }, {
224 .bus_id = "ras2_tx",
225 .min_signal = 5,
226 .max_signal = 5,
227 .muxval = 1,
228 .cctl = 0,
229 .periph_buses = PL08X_AHB1,
230 }, {
231 .bus_id = "ras3_rx",
232 .min_signal = 6,
233 .max_signal = 6,
234 .muxval = 1,
235 .cctl = 0,
236 .periph_buses = PL08X_AHB1,
237 }, {
238 .bus_id = "ras3_tx",
239 .min_signal = 7,
240 .max_signal = 7,
241 .muxval = 1,
242 .cctl = 0,
243 .periph_buses = PL08X_AHB1,
244 }, {
245 .bus_id = "ras4_rx",
246 .min_signal = 8,
247 .max_signal = 8,
248 .muxval = 1,
249 .cctl = 0,
250 .periph_buses = PL08X_AHB1,
251 }, {
252 .bus_id = "ras4_tx",
253 .min_signal = 9,
254 .max_signal = 9,
255 .muxval = 1,
256 .cctl = 0,
257 .periph_buses = PL08X_AHB1,
258 }, {
259 .bus_id = "ras5_rx",
260 .min_signal = 10,
261 .max_signal = 10,
262 .muxval = 1,
263 .cctl = 0,
264 .periph_buses = PL08X_AHB1,
265 }, {
266 .bus_id = "ras5_tx",
267 .min_signal = 11,
268 .max_signal = 11,
269 .muxval = 1,
270 .cctl = 0,
271 .periph_buses = PL08X_AHB1,
272 }, {
273 .bus_id = "ras6_rx",
274 .min_signal = 12,
275 .max_signal = 12,
276 .muxval = 1,
277 .cctl = 0,
278 .periph_buses = PL08X_AHB1,
279 }, {
280 .bus_id = "ras6_tx",
281 .min_signal = 13,
282 .max_signal = 13,
283 .muxval = 1,
284 .cctl = 0,
285 .periph_buses = PL08X_AHB1,
286 }, {
287 .bus_id = "ras7_rx",
288 .min_signal = 14,
289 .max_signal = 14,
290 .muxval = 1,
291 .cctl = 0,
292 .periph_buses = PL08X_AHB1,
293 }, {
294 .bus_id = "ras7_tx",
295 .min_signal = 15,
296 .max_signal = 15,
297 .muxval = 1,
298 .cctl = 0,
299 .periph_buses = PL08X_AHB1,
300 },
431}; 301};
432 302
433AMBA_APB_DEVICE(spear300_gpio1, "gpio1", 0, SPEAR300_GPIO_BASE, 303/* Add SPEAr300 auxdata to pass platform data */
434 {SPEAR300_VIRQ_GPIO1}, &gpio1_plat_data); 304static struct of_dev_auxdata spear300_auxdata_lookup[] __initdata = {
305 OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
306 &pl022_plat_data),
307 OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
308 &pl080_plat_data),
309 {}
310};
435 311
436/* spear300 routines */ 312static void __init spear300_dt_init(void)
437void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
438 u8 pmx_dev_count)
439{ 313{
440 int ret = 0; 314 int ret;
315
316 pl080_plat_data.slave_channels = spear300_dma_info;
317 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear300_dma_info);
441 318
442 /* call spear3xx family common init function */ 319 of_platform_populate(NULL, of_default_bus_match_table,
443 spear3xx_init(); 320 spear300_auxdata_lookup, NULL);
444 321
445 /* shared irq registration */ 322 /* shared irq registration */
446 shirq_ras1.regs.base = ioremap(SPEAR300_TELECOM_BASE, SZ_4K); 323 shirq_ras1.regs.base = ioremap(SPEAR300_TELECOM_BASE, SZ_4K);
447 if (shirq_ras1.regs.base) { 324 if (shirq_ras1.regs.base) {
448 ret = spear_shirq_register(&shirq_ras1); 325 ret = spear_shirq_register(&shirq_ras1);
449 if (ret) 326 if (ret)
450 printk(KERN_ERR "Error registering Shared IRQ\n"); 327 pr_err("Error registering Shared IRQ\n");
451 } 328 }
329}
452 330
453 /* pmx initialization */ 331static const char * const spear300_dt_board_compat[] = {
454 pmx_driver.mode = pmx_mode; 332 "st,spear300",
455 pmx_driver.devs = pmx_devs; 333 "st,spear300-evb",
456 pmx_driver.devs_count = pmx_dev_count; 334 NULL,
335};
457 336
458 pmx_driver.base = ioremap(SPEAR300_SOC_CONFIG_BASE, SZ_4K); 337static void __init spear300_map_io(void)
459 if (pmx_driver.base) { 338{
460 ret = pmx_register(&pmx_driver); 339 spear3xx_map_io();
461 if (ret)
462 printk(KERN_ERR "padmux: registration failed. err no"
463 ": %d\n", ret);
464 /* Free Mapping, device selection already done */
465 iounmap(pmx_driver.base);
466 }
467} 340}
341
342DT_MACHINE_START(SPEAR300_DT, "ST SPEAr300 SoC with Flattened Device Tree")
343 .map_io = spear300_map_io,
344 .init_irq = spear3xx_dt_init_irq,
345 .handle_irq = vic_handle_irq,
346 .timer = &spear3xx_timer,
347 .init_machine = spear300_dt_init,
348 .restart = spear_restart,
349 .dt_compat = spear300_dt_board_compat,
350MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear300_evb.c b/arch/arm/mach-spear3xx/spear300_evb.c
deleted file mode 100644
index 3462ab9d6122..000000000000
--- a/arch/arm/mach-spear3xx/spear300_evb.c
+++ /dev/null
@@ -1,75 +0,0 @@
1/*
2 * arch/arm/mach-spear3xx/spear300_evb.c
3 *
4 * SPEAr300 evaluation board source file
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <asm/hardware/vic.h>
15#include <asm/mach/arch.h>
16#include <asm/mach-types.h>
17#include <mach/generic.h>
18#include <mach/hardware.h>
19
20/* padmux devices to enable */
21static struct pmx_dev *pmx_devs[] = {
22 /* spear3xx specific devices */
23 &spear3xx_pmx_i2c,
24 &spear3xx_pmx_ssp_cs,
25 &spear3xx_pmx_ssp,
26 &spear3xx_pmx_mii,
27 &spear3xx_pmx_uart0,
28
29 /* spear300 specific devices */
30 &spear300_pmx_fsmc_2_chips,
31 &spear300_pmx_clcd,
32 &spear300_pmx_telecom_sdhci_4bit,
33 &spear300_pmx_gpio1,
34};
35
36static struct amba_device *amba_devs[] __initdata = {
37 /* spear3xx specific devices */
38 &spear3xx_gpio_device,
39 &spear3xx_uart_device,
40
41 /* spear300 specific devices */
42 &spear300_gpio1_device,
43};
44
45static struct platform_device *plat_devs[] __initdata = {
46 /* spear3xx specific devices */
47
48 /* spear300 specific devices */
49};
50
51static void __init spear300_evb_init(void)
52{
53 unsigned int i;
54
55 /* call spear300 machine init function */
56 spear300_init(&spear300_photo_frame_mode, pmx_devs,
57 ARRAY_SIZE(pmx_devs));
58
59 /* Add Platform Devices */
60 platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
61
62 /* Add Amba Devices */
63 for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
64 amba_device_register(amba_devs[i], &iomem_resource);
65}
66
67MACHINE_START(SPEAR300, "ST-SPEAR300-EVB")
68 .atag_offset = 0x100,
69 .map_io = spear3xx_map_io,
70 .init_irq = spear3xx_init_irq,
71 .handle_irq = vic_handle_irq,
72 .timer = &spear3xx_timer,
73 .init_machine = spear300_evb_init,
74 .restart = spear_restart,
75MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index febaa6fcfb6a..84dfb0900747 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -3,141 +3,84 @@
3 * 3 *
4 * SPEAr310 machine source file 4 * SPEAr310 machine source file
5 * 5 *
6 * Copyright (C) 2009 ST Microelectronics 6 * Copyright (C) 2009-2012 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com> 7 * Viresh Kumar <viresh.kumar@st.com>
8 * 8 *
9 * This file is licensed under the terms of the GNU General Public 9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any 10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied. 11 * warranty of any kind, whether express or implied.
12 */ 12 */
13 13
14#include <linux/ptrace.h> 14#define pr_fmt(fmt) "SPEAr310: " fmt
15#include <asm/irq.h> 15
16#include <linux/amba/pl08x.h>
17#include <linux/amba/serial.h>
18#include <linux/of_platform.h>
19#include <asm/hardware/vic.h>
20#include <asm/mach/arch.h>
16#include <plat/shirq.h> 21#include <plat/shirq.h>
17#include <mach/generic.h> 22#include <mach/generic.h>
18#include <mach/hardware.h> 23#include <mach/spear.h>
19 24
20/* pad multiplexing support */ 25#define SPEAR310_UART1_BASE UL(0xB2000000)
21/* muxing registers */ 26#define SPEAR310_UART2_BASE UL(0xB2080000)
22#define PAD_MUX_CONFIG_REG 0x08 27#define SPEAR310_UART3_BASE UL(0xB2100000)
23 28#define SPEAR310_UART4_BASE UL(0xB2180000)
24/* devices */ 29#define SPEAR310_UART5_BASE UL(0xB2200000)
25static struct pmx_dev_mode pmx_emi_cs_0_1_4_5_modes[] = { 30#define SPEAR310_SOC_CONFIG_BASE UL(0xB4000000)
26 { 31
27 .ids = 0x00, 32/* Interrupt registers offsets and masks */
28 .mask = PMX_TIMER_3_4_MASK, 33#define SPEAR310_INT_STS_MASK_REG 0x04
29 }, 34#define SPEAR310_SMII0_IRQ_MASK (1 << 0)
30}; 35#define SPEAR310_SMII1_IRQ_MASK (1 << 1)
31 36#define SPEAR310_SMII2_IRQ_MASK (1 << 2)
32struct pmx_dev spear310_pmx_emi_cs_0_1_4_5 = { 37#define SPEAR310_SMII3_IRQ_MASK (1 << 3)
33 .name = "emi_cs_0_1_4_5", 38#define SPEAR310_WAKEUP_SMII0_IRQ_MASK (1 << 4)
34 .modes = pmx_emi_cs_0_1_4_5_modes, 39#define SPEAR310_WAKEUP_SMII1_IRQ_MASK (1 << 5)
35 .mode_count = ARRAY_SIZE(pmx_emi_cs_0_1_4_5_modes), 40#define SPEAR310_WAKEUP_SMII2_IRQ_MASK (1 << 6)
36 .enb_on_reset = 1, 41#define SPEAR310_WAKEUP_SMII3_IRQ_MASK (1 << 7)
37}; 42#define SPEAR310_UART1_IRQ_MASK (1 << 8)
38 43#define SPEAR310_UART2_IRQ_MASK (1 << 9)
39static struct pmx_dev_mode pmx_emi_cs_2_3_modes[] = { 44#define SPEAR310_UART3_IRQ_MASK (1 << 10)
40 { 45#define SPEAR310_UART4_IRQ_MASK (1 << 11)
41 .ids = 0x00, 46#define SPEAR310_UART5_IRQ_MASK (1 << 12)
42 .mask = PMX_TIMER_1_2_MASK, 47#define SPEAR310_EMI_IRQ_MASK (1 << 13)
43 }, 48#define SPEAR310_TDM_HDLC_IRQ_MASK (1 << 14)
44}; 49#define SPEAR310_RS485_0_IRQ_MASK (1 << 15)
45 50#define SPEAR310_RS485_1_IRQ_MASK (1 << 16)
46struct pmx_dev spear310_pmx_emi_cs_2_3 = { 51
47 .name = "emi_cs_2_3", 52#define SPEAR310_SHIRQ_RAS1_MASK 0x000FF
48 .modes = pmx_emi_cs_2_3_modes, 53#define SPEAR310_SHIRQ_RAS2_MASK 0x01F00
49 .mode_count = ARRAY_SIZE(pmx_emi_cs_2_3_modes), 54#define SPEAR310_SHIRQ_RAS3_MASK 0x02000
50 .enb_on_reset = 1, 55#define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK 0x1C000
51}; 56
52 57/* SPEAr310 Virtual irq definitions */
53static struct pmx_dev_mode pmx_uart1_modes[] = { 58/* IRQs sharing IRQ_GEN_RAS_1 */
54 { 59#define SPEAR310_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 0)
55 .ids = 0x00, 60#define SPEAR310_VIRQ_SMII1 (SPEAR3XX_VIRQ_START + 1)
56 .mask = PMX_FIRDA_MASK, 61#define SPEAR310_VIRQ_SMII2 (SPEAR3XX_VIRQ_START + 2)
57 }, 62#define SPEAR310_VIRQ_SMII3 (SPEAR3XX_VIRQ_START + 3)
58}; 63#define SPEAR310_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 4)
59 64#define SPEAR310_VIRQ_WAKEUP_SMII1 (SPEAR3XX_VIRQ_START + 5)
60struct pmx_dev spear310_pmx_uart1 = { 65#define SPEAR310_VIRQ_WAKEUP_SMII2 (SPEAR3XX_VIRQ_START + 6)
61 .name = "uart1", 66#define SPEAR310_VIRQ_WAKEUP_SMII3 (SPEAR3XX_VIRQ_START + 7)
62 .modes = pmx_uart1_modes, 67
63 .mode_count = ARRAY_SIZE(pmx_uart1_modes), 68/* IRQs sharing IRQ_GEN_RAS_2 */
64 .enb_on_reset = 1, 69#define SPEAR310_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
65}; 70#define SPEAR310_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
66 71#define SPEAR310_VIRQ_UART3 (SPEAR3XX_VIRQ_START + 10)
67static struct pmx_dev_mode pmx_uart2_modes[] = { 72#define SPEAR310_VIRQ_UART4 (SPEAR3XX_VIRQ_START + 11)
68 { 73#define SPEAR310_VIRQ_UART5 (SPEAR3XX_VIRQ_START + 12)
69 .ids = 0x00, 74
70 .mask = PMX_TIMER_1_2_MASK, 75/* IRQs sharing IRQ_GEN_RAS_3 */
71 }, 76#define SPEAR310_VIRQ_EMI (SPEAR3XX_VIRQ_START + 13)
72}; 77#define SPEAR310_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 14)
73 78
74struct pmx_dev spear310_pmx_uart2 = { 79/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
75 .name = "uart2", 80#define SPEAR310_VIRQ_TDM_HDLC (SPEAR3XX_VIRQ_START + 15)
76 .modes = pmx_uart2_modes, 81#define SPEAR310_VIRQ_RS485_0 (SPEAR3XX_VIRQ_START + 16)
77 .mode_count = ARRAY_SIZE(pmx_uart2_modes), 82#define SPEAR310_VIRQ_RS485_1 (SPEAR3XX_VIRQ_START + 17)
78 .enb_on_reset = 1,
79};
80
81static struct pmx_dev_mode pmx_uart3_4_5_modes[] = {
82 {
83 .ids = 0x00,
84 .mask = PMX_UART0_MODEM_MASK,
85 },
86};
87
88struct pmx_dev spear310_pmx_uart3_4_5 = {
89 .name = "uart3_4_5",
90 .modes = pmx_uart3_4_5_modes,
91 .mode_count = ARRAY_SIZE(pmx_uart3_4_5_modes),
92 .enb_on_reset = 1,
93};
94
95static struct pmx_dev_mode pmx_fsmc_modes[] = {
96 {
97 .ids = 0x00,
98 .mask = PMX_SSP_CS_MASK,
99 },
100};
101
102struct pmx_dev spear310_pmx_fsmc = {
103 .name = "fsmc",
104 .modes = pmx_fsmc_modes,
105 .mode_count = ARRAY_SIZE(pmx_fsmc_modes),
106 .enb_on_reset = 1,
107};
108
109static struct pmx_dev_mode pmx_rs485_0_1_modes[] = {
110 {
111 .ids = 0x00,
112 .mask = PMX_MII_MASK,
113 },
114};
115
116struct pmx_dev spear310_pmx_rs485_0_1 = {
117 .name = "rs485_0_1",
118 .modes = pmx_rs485_0_1_modes,
119 .mode_count = ARRAY_SIZE(pmx_rs485_0_1_modes),
120 .enb_on_reset = 1,
121};
122
123static struct pmx_dev_mode pmx_tdm0_modes[] = {
124 {
125 .ids = 0x00,
126 .mask = PMX_MII_MASK,
127 },
128};
129
130struct pmx_dev spear310_pmx_tdm0 = {
131 .name = "tdm0",
132 .modes = pmx_tdm0_modes,
133 .mode_count = ARRAY_SIZE(pmx_tdm0_modes),
134 .enb_on_reset = 1,
135};
136 83
137/* pmx driver structure */
138static struct pmx_driver pmx_driver = {
139 .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
140};
141 84
142/* spear3xx shared irq */ 85/* spear3xx shared irq */
143static struct shirq_dev_config shirq_ras1_config[] = { 86static struct shirq_dev_config shirq_ras1_config[] = {
@@ -255,17 +198,247 @@ static struct spear_shirq shirq_intrcomm_ras = {
255 }, 198 },
256}; 199};
257 200
258/* Add spear310 specific devices here */ 201/* DMAC platform data's slave info */
202struct pl08x_channel_data spear310_dma_info[] = {
203 {
204 .bus_id = "uart0_rx",
205 .min_signal = 2,
206 .max_signal = 2,
207 .muxval = 0,
208 .cctl = 0,
209 .periph_buses = PL08X_AHB1,
210 }, {
211 .bus_id = "uart0_tx",
212 .min_signal = 3,
213 .max_signal = 3,
214 .muxval = 0,
215 .cctl = 0,
216 .periph_buses = PL08X_AHB1,
217 }, {
218 .bus_id = "ssp0_rx",
219 .min_signal = 8,
220 .max_signal = 8,
221 .muxval = 0,
222 .cctl = 0,
223 .periph_buses = PL08X_AHB1,
224 }, {
225 .bus_id = "ssp0_tx",
226 .min_signal = 9,
227 .max_signal = 9,
228 .muxval = 0,
229 .cctl = 0,
230 .periph_buses = PL08X_AHB1,
231 }, {
232 .bus_id = "i2c_rx",
233 .min_signal = 10,
234 .max_signal = 10,
235 .muxval = 0,
236 .cctl = 0,
237 .periph_buses = PL08X_AHB1,
238 }, {
239 .bus_id = "i2c_tx",
240 .min_signal = 11,
241 .max_signal = 11,
242 .muxval = 0,
243 .cctl = 0,
244 .periph_buses = PL08X_AHB1,
245 }, {
246 .bus_id = "irda",
247 .min_signal = 12,
248 .max_signal = 12,
249 .muxval = 0,
250 .cctl = 0,
251 .periph_buses = PL08X_AHB1,
252 }, {
253 .bus_id = "adc",
254 .min_signal = 13,
255 .max_signal = 13,
256 .muxval = 0,
257 .cctl = 0,
258 .periph_buses = PL08X_AHB1,
259 }, {
260 .bus_id = "to_jpeg",
261 .min_signal = 14,
262 .max_signal = 14,
263 .muxval = 0,
264 .cctl = 0,
265 .periph_buses = PL08X_AHB1,
266 }, {
267 .bus_id = "from_jpeg",
268 .min_signal = 15,
269 .max_signal = 15,
270 .muxval = 0,
271 .cctl = 0,
272 .periph_buses = PL08X_AHB1,
273 }, {
274 .bus_id = "uart1_rx",
275 .min_signal = 0,
276 .max_signal = 0,
277 .muxval = 1,
278 .cctl = 0,
279 .periph_buses = PL08X_AHB1,
280 }, {
281 .bus_id = "uart1_tx",
282 .min_signal = 1,
283 .max_signal = 1,
284 .muxval = 1,
285 .cctl = 0,
286 .periph_buses = PL08X_AHB1,
287 }, {
288 .bus_id = "uart2_rx",
289 .min_signal = 2,
290 .max_signal = 2,
291 .muxval = 1,
292 .cctl = 0,
293 .periph_buses = PL08X_AHB1,
294 }, {
295 .bus_id = "uart2_tx",
296 .min_signal = 3,
297 .max_signal = 3,
298 .muxval = 1,
299 .cctl = 0,
300 .periph_buses = PL08X_AHB1,
301 }, {
302 .bus_id = "uart3_rx",
303 .min_signal = 4,
304 .max_signal = 4,
305 .muxval = 1,
306 .cctl = 0,
307 .periph_buses = PL08X_AHB1,
308 }, {
309 .bus_id = "uart3_tx",
310 .min_signal = 5,
311 .max_signal = 5,
312 .muxval = 1,
313 .cctl = 0,
314 .periph_buses = PL08X_AHB1,
315 }, {
316 .bus_id = "uart4_rx",
317 .min_signal = 6,
318 .max_signal = 6,
319 .muxval = 1,
320 .cctl = 0,
321 .periph_buses = PL08X_AHB1,
322 }, {
323 .bus_id = "uart4_tx",
324 .min_signal = 7,
325 .max_signal = 7,
326 .muxval = 1,
327 .cctl = 0,
328 .periph_buses = PL08X_AHB1,
329 }, {
330 .bus_id = "uart5_rx",
331 .min_signal = 8,
332 .max_signal = 8,
333 .muxval = 1,
334 .cctl = 0,
335 .periph_buses = PL08X_AHB1,
336 }, {
337 .bus_id = "uart5_tx",
338 .min_signal = 9,
339 .max_signal = 9,
340 .muxval = 1,
341 .cctl = 0,
342 .periph_buses = PL08X_AHB1,
343 }, {
344 .bus_id = "ras5_rx",
345 .min_signal = 10,
346 .max_signal = 10,
347 .muxval = 1,
348 .cctl = 0,
349 .periph_buses = PL08X_AHB1,
350 }, {
351 .bus_id = "ras5_tx",
352 .min_signal = 11,
353 .max_signal = 11,
354 .muxval = 1,
355 .cctl = 0,
356 .periph_buses = PL08X_AHB1,
357 }, {
358 .bus_id = "ras6_rx",
359 .min_signal = 12,
360 .max_signal = 12,
361 .muxval = 1,
362 .cctl = 0,
363 .periph_buses = PL08X_AHB1,
364 }, {
365 .bus_id = "ras6_tx",
366 .min_signal = 13,
367 .max_signal = 13,
368 .muxval = 1,
369 .cctl = 0,
370 .periph_buses = PL08X_AHB1,
371 }, {
372 .bus_id = "ras7_rx",
373 .min_signal = 14,
374 .max_signal = 14,
375 .muxval = 1,
376 .cctl = 0,
377 .periph_buses = PL08X_AHB1,
378 }, {
379 .bus_id = "ras7_tx",
380 .min_signal = 15,
381 .max_signal = 15,
382 .muxval = 1,
383 .cctl = 0,
384 .periph_buses = PL08X_AHB1,
385 },
386};
259 387
260/* spear310 routines */ 388/* uart devices plat data */
261void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs, 389static struct amba_pl011_data spear310_uart_data[] = {
262 u8 pmx_dev_count) 390 {
391 .dma_filter = pl08x_filter_id,
392 .dma_tx_param = "uart1_tx",
393 .dma_rx_param = "uart1_rx",
394 }, {
395 .dma_filter = pl08x_filter_id,
396 .dma_tx_param = "uart2_tx",
397 .dma_rx_param = "uart2_rx",
398 }, {
399 .dma_filter = pl08x_filter_id,
400 .dma_tx_param = "uart3_tx",
401 .dma_rx_param = "uart3_rx",
402 }, {
403 .dma_filter = pl08x_filter_id,
404 .dma_tx_param = "uart4_tx",
405 .dma_rx_param = "uart4_rx",
406 }, {
407 .dma_filter = pl08x_filter_id,
408 .dma_tx_param = "uart5_tx",
409 .dma_rx_param = "uart5_rx",
410 },
411};
412
413/* Add SPEAr310 auxdata to pass platform data */
414static struct of_dev_auxdata spear310_auxdata_lookup[] __initdata = {
415 OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
416 &pl022_plat_data),
417 OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
418 &pl080_plat_data),
419 OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART1_BASE, NULL,
420 &spear310_uart_data[0]),
421 OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART2_BASE, NULL,
422 &spear310_uart_data[1]),
423 OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART3_BASE, NULL,
424 &spear310_uart_data[2]),
425 OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART4_BASE, NULL,
426 &spear310_uart_data[3]),
427 OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART5_BASE, NULL,
428 &spear310_uart_data[4]),
429 {}
430};
431
432static void __init spear310_dt_init(void)
263{ 433{
264 void __iomem *base; 434 void __iomem *base;
265 int ret = 0; 435 int ret;
266 436
267 /* call spear3xx family common init function */ 437 pl080_plat_data.slave_channels = spear310_dma_info;
268 spear3xx_init(); 438 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear310_dma_info);
439
440 of_platform_populate(NULL, of_default_bus_match_table,
441 spear310_auxdata_lookup, NULL);
269 442
270 /* shared irq registration */ 443 /* shared irq registration */
271 base = ioremap(SPEAR310_SOC_CONFIG_BASE, SZ_4K); 444 base = ioremap(SPEAR310_SOC_CONFIG_BASE, SZ_4K);
@@ -274,35 +447,45 @@ void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
274 shirq_ras1.regs.base = base; 447 shirq_ras1.regs.base = base;
275 ret = spear_shirq_register(&shirq_ras1); 448 ret = spear_shirq_register(&shirq_ras1);
276 if (ret) 449 if (ret)
277 printk(KERN_ERR "Error registering Shared IRQ 1\n"); 450 pr_err("Error registering Shared IRQ 1\n");
278 451
279 /* shirq 2 */ 452 /* shirq 2 */
280 shirq_ras2.regs.base = base; 453 shirq_ras2.regs.base = base;
281 ret = spear_shirq_register(&shirq_ras2); 454 ret = spear_shirq_register(&shirq_ras2);
282 if (ret) 455 if (ret)
283 printk(KERN_ERR "Error registering Shared IRQ 2\n"); 456 pr_err("Error registering Shared IRQ 2\n");
284 457
285 /* shirq 3 */ 458 /* shirq 3 */
286 shirq_ras3.regs.base = base; 459 shirq_ras3.regs.base = base;
287 ret = spear_shirq_register(&shirq_ras3); 460 ret = spear_shirq_register(&shirq_ras3);
288 if (ret) 461 if (ret)
289 printk(KERN_ERR "Error registering Shared IRQ 3\n"); 462 pr_err("Error registering Shared IRQ 3\n");
290 463
291 /* shirq 4 */ 464 /* shirq 4 */
292 shirq_intrcomm_ras.regs.base = base; 465 shirq_intrcomm_ras.regs.base = base;
293 ret = spear_shirq_register(&shirq_intrcomm_ras); 466 ret = spear_shirq_register(&shirq_intrcomm_ras);
294 if (ret) 467 if (ret)
295 printk(KERN_ERR "Error registering Shared IRQ 4\n"); 468 pr_err("Error registering Shared IRQ 4\n");
296 } 469 }
470}
297 471
298 /* pmx initialization */ 472static const char * const spear310_dt_board_compat[] = {
299 pmx_driver.base = base; 473 "st,spear310",
300 pmx_driver.mode = pmx_mode; 474 "st,spear310-evb",
301 pmx_driver.devs = pmx_devs; 475 NULL,
302 pmx_driver.devs_count = pmx_dev_count; 476};
303 477
304 ret = pmx_register(&pmx_driver); 478static void __init spear310_map_io(void)
305 if (ret) 479{
306 printk(KERN_ERR "padmux: registration failed. err no: %d\n", 480 spear3xx_map_io();
307 ret);
308} 481}
482
483DT_MACHINE_START(SPEAR310_DT, "ST SPEAr310 SoC with Flattened Device Tree")
484 .map_io = spear310_map_io,
485 .init_irq = spear3xx_dt_init_irq,
486 .handle_irq = vic_handle_irq,
487 .timer = &spear3xx_timer,
488 .init_machine = spear310_dt_init,
489 .restart = spear_restart,
490 .dt_compat = spear310_dt_board_compat,
491MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear310_evb.c b/arch/arm/mach-spear3xx/spear310_evb.c
deleted file mode 100644
index f92c4993f65a..000000000000
--- a/arch/arm/mach-spear3xx/spear310_evb.c
+++ /dev/null
@@ -1,81 +0,0 @@
1/*
2 * arch/arm/mach-spear3xx/spear310_evb.c
3 *
4 * SPEAr310 evaluation board source file
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <asm/hardware/vic.h>
15#include <asm/mach/arch.h>
16#include <asm/mach-types.h>
17#include <mach/generic.h>
18#include <mach/hardware.h>
19
20/* padmux devices to enable */
21static struct pmx_dev *pmx_devs[] = {
22 /* spear3xx specific devices */
23 &spear3xx_pmx_i2c,
24 &spear3xx_pmx_ssp,
25 &spear3xx_pmx_gpio_pin0,
26 &spear3xx_pmx_gpio_pin1,
27 &spear3xx_pmx_gpio_pin2,
28 &spear3xx_pmx_gpio_pin3,
29 &spear3xx_pmx_gpio_pin4,
30 &spear3xx_pmx_gpio_pin5,
31 &spear3xx_pmx_uart0,
32
33 /* spear310 specific devices */
34 &spear310_pmx_emi_cs_0_1_4_5,
35 &spear310_pmx_emi_cs_2_3,
36 &spear310_pmx_uart1,
37 &spear310_pmx_uart2,
38 &spear310_pmx_uart3_4_5,
39 &spear310_pmx_fsmc,
40 &spear310_pmx_rs485_0_1,
41 &spear310_pmx_tdm0,
42};
43
44static struct amba_device *amba_devs[] __initdata = {
45 /* spear3xx specific devices */
46 &spear3xx_gpio_device,
47 &spear3xx_uart_device,
48
49 /* spear310 specific devices */
50};
51
52static struct platform_device *plat_devs[] __initdata = {
53 /* spear3xx specific devices */
54
55 /* spear310 specific devices */
56};
57
58static void __init spear310_evb_init(void)
59{
60 unsigned int i;
61
62 /* call spear310 machine init function */
63 spear310_init(NULL, pmx_devs, ARRAY_SIZE(pmx_devs));
64
65 /* Add Platform Devices */
66 platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
67
68 /* Add Amba Devices */
69 for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
70 amba_device_register(amba_devs[i], &iomem_resource);
71}
72
73MACHINE_START(SPEAR310, "ST-SPEAR310-EVB")
74 .atag_offset = 0x100,
75 .map_io = spear3xx_map_io,
76 .init_irq = spear3xx_init_irq,
77 .handle_irq = vic_handle_irq,
78 .timer = &spear3xx_timer,
79 .init_machine = spear310_evb_init,
80 .restart = spear_restart,
81MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index deaaf199612c..a88fa841d29d 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -3,386 +3,84 @@
3 * 3 *
4 * SPEAr320 machine source file 4 * SPEAr320 machine source file
5 * 5 *
6 * Copyright (C) 2009 ST Microelectronics 6 * Copyright (C) 2009-2012 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com> 7 * Viresh Kumar <viresh.kumar@st.com>
8 * 8 *
9 * This file is licensed under the terms of the GNU General Public 9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any 10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied. 11 * warranty of any kind, whether express or implied.
12 */ 12 */
13 13
14#include <linux/ptrace.h> 14#define pr_fmt(fmt) "SPEAr320: " fmt
15#include <asm/irq.h> 15
16#include <linux/amba/pl022.h>
17#include <linux/amba/pl08x.h>
18#include <linux/amba/serial.h>
19#include <linux/of_platform.h>
20#include <asm/hardware/vic.h>
21#include <asm/mach/arch.h>
16#include <plat/shirq.h> 22#include <plat/shirq.h>
17#include <mach/generic.h> 23#include <mach/generic.h>
18#include <mach/hardware.h> 24#include <mach/spear.h>
19 25
20/* pad multiplexing support */ 26#define SPEAR320_UART1_BASE UL(0xA3000000)
21/* muxing registers */ 27#define SPEAR320_UART2_BASE UL(0xA4000000)
22#define PAD_MUX_CONFIG_REG 0x0C 28#define SPEAR320_SSP0_BASE UL(0xA5000000)
23#define MODE_CONFIG_REG 0x10 29#define SPEAR320_SSP1_BASE UL(0xA6000000)
24 30
25/* modes */ 31/* Interrupt registers offsets and masks */
26#define AUTO_NET_SMII_MODE (1 << 0) 32#define SPEAR320_INT_STS_MASK_REG 0x04
27#define AUTO_NET_MII_MODE (1 << 1) 33#define SPEAR320_INT_CLR_MASK_REG 0x04
28#define AUTO_EXP_MODE (1 << 2) 34#define SPEAR320_INT_ENB_MASK_REG 0x08
29#define SMALL_PRINTERS_MODE (1 << 3) 35#define SPEAR320_GPIO_IRQ_MASK (1 << 0)
30#define ALL_MODES 0xF 36#define SPEAR320_I2S_PLAY_IRQ_MASK (1 << 1)
31 37#define SPEAR320_I2S_REC_IRQ_MASK (1 << 2)
32struct pmx_mode spear320_auto_net_smii_mode = { 38#define SPEAR320_EMI_IRQ_MASK (1 << 7)
33 .id = AUTO_NET_SMII_MODE, 39#define SPEAR320_CLCD_IRQ_MASK (1 << 8)
34 .name = "Automation Networking SMII Mode", 40#define SPEAR320_SPP_IRQ_MASK (1 << 9)
35 .mask = 0x00, 41#define SPEAR320_SDHCI_IRQ_MASK (1 << 10)
36}; 42#define SPEAR320_CAN_U_IRQ_MASK (1 << 11)
37 43#define SPEAR320_CAN_L_IRQ_MASK (1 << 12)
38struct pmx_mode spear320_auto_net_mii_mode = { 44#define SPEAR320_UART1_IRQ_MASK (1 << 13)
39 .id = AUTO_NET_MII_MODE, 45#define SPEAR320_UART2_IRQ_MASK (1 << 14)
40 .name = "Automation Networking MII Mode", 46#define SPEAR320_SSP1_IRQ_MASK (1 << 15)
41 .mask = 0x01, 47#define SPEAR320_SSP2_IRQ_MASK (1 << 16)
42}; 48#define SPEAR320_SMII0_IRQ_MASK (1 << 17)
43 49#define SPEAR320_MII1_SMII1_IRQ_MASK (1 << 18)
44struct pmx_mode spear320_auto_exp_mode = { 50#define SPEAR320_WAKEUP_SMII0_IRQ_MASK (1 << 19)
45 .id = AUTO_EXP_MODE, 51#define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK (1 << 20)
46 .name = "Automation Expanded Mode", 52#define SPEAR320_I2C1_IRQ_MASK (1 << 21)
47 .mask = 0x02, 53
48}; 54#define SPEAR320_SHIRQ_RAS1_MASK 0x000380
49 55#define SPEAR320_SHIRQ_RAS3_MASK 0x000007
50struct pmx_mode spear320_small_printers_mode = { 56#define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK 0x3FF800
51 .id = SMALL_PRINTERS_MODE, 57
52 .name = "Small Printers Mode", 58/* SPEAr320 Virtual irq definitions */
53 .mask = 0x03, 59/* IRQs sharing IRQ_GEN_RAS_1 */
54}; 60#define SPEAR320_VIRQ_EMI (SPEAR3XX_VIRQ_START + 0)
55 61#define SPEAR320_VIRQ_CLCD (SPEAR3XX_VIRQ_START + 1)
56/* devices */ 62#define SPEAR320_VIRQ_SPP (SPEAR3XX_VIRQ_START + 2)
57static struct pmx_dev_mode pmx_clcd_modes[] = { 63
58 { 64/* IRQs sharing IRQ_GEN_RAS_2 */
59 .ids = AUTO_NET_SMII_MODE, 65#define SPEAR320_IRQ_SDHCI SPEAR3XX_IRQ_GEN_RAS_2
60 .mask = 0x0, 66
61 }, 67/* IRQs sharing IRQ_GEN_RAS_3 */
62}; 68#define SPEAR320_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 3)
63 69#define SPEAR320_VIRQ_I2S_PLAY (SPEAR3XX_VIRQ_START + 4)
64struct pmx_dev spear320_pmx_clcd = { 70#define SPEAR320_VIRQ_I2S_REC (SPEAR3XX_VIRQ_START + 5)
65 .name = "clcd", 71
66 .modes = pmx_clcd_modes, 72/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
67 .mode_count = ARRAY_SIZE(pmx_clcd_modes), 73#define SPEAR320_VIRQ_CANU (SPEAR3XX_VIRQ_START + 6)
68 .enb_on_reset = 1, 74#define SPEAR320_VIRQ_CANL (SPEAR3XX_VIRQ_START + 7)
69}; 75#define SPEAR320_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
70 76#define SPEAR320_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
71static struct pmx_dev_mode pmx_emi_modes[] = { 77#define SPEAR320_VIRQ_SSP1 (SPEAR3XX_VIRQ_START + 10)
72 { 78#define SPEAR320_VIRQ_SSP2 (SPEAR3XX_VIRQ_START + 11)
73 .ids = AUTO_EXP_MODE, 79#define SPEAR320_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 12)
74 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK, 80#define SPEAR320_VIRQ_MII1_SMII1 (SPEAR3XX_VIRQ_START + 13)
75 }, 81#define SPEAR320_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 14)
76}; 82#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1 (SPEAR3XX_VIRQ_START + 15)
77 83#define SPEAR320_VIRQ_I2C1 (SPEAR3XX_VIRQ_START + 16)
78struct pmx_dev spear320_pmx_emi = {
79 .name = "emi",
80 .modes = pmx_emi_modes,
81 .mode_count = ARRAY_SIZE(pmx_emi_modes),
82 .enb_on_reset = 1,
83};
84
85static struct pmx_dev_mode pmx_fsmc_modes[] = {
86 {
87 .ids = ALL_MODES,
88 .mask = 0x0,
89 },
90};
91
92struct pmx_dev spear320_pmx_fsmc = {
93 .name = "fsmc",
94 .modes = pmx_fsmc_modes,
95 .mode_count = ARRAY_SIZE(pmx_fsmc_modes),
96 .enb_on_reset = 1,
97};
98
99static struct pmx_dev_mode pmx_spp_modes[] = {
100 {
101 .ids = SMALL_PRINTERS_MODE,
102 .mask = 0x0,
103 },
104};
105
106struct pmx_dev spear320_pmx_spp = {
107 .name = "spp",
108 .modes = pmx_spp_modes,
109 .mode_count = ARRAY_SIZE(pmx_spp_modes),
110 .enb_on_reset = 1,
111};
112
113static struct pmx_dev_mode pmx_sdhci_modes[] = {
114 {
115 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE |
116 SMALL_PRINTERS_MODE,
117 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
118 },
119};
120
121struct pmx_dev spear320_pmx_sdhci = {
122 .name = "sdhci",
123 .modes = pmx_sdhci_modes,
124 .mode_count = ARRAY_SIZE(pmx_sdhci_modes),
125 .enb_on_reset = 1,
126};
127
128static struct pmx_dev_mode pmx_i2s_modes[] = {
129 {
130 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
131 .mask = PMX_UART0_MODEM_MASK,
132 },
133};
134
135struct pmx_dev spear320_pmx_i2s = {
136 .name = "i2s",
137 .modes = pmx_i2s_modes,
138 .mode_count = ARRAY_SIZE(pmx_i2s_modes),
139 .enb_on_reset = 1,
140};
141
142static struct pmx_dev_mode pmx_uart1_modes[] = {
143 {
144 .ids = ALL_MODES,
145 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK,
146 },
147};
148
149struct pmx_dev spear320_pmx_uart1 = {
150 .name = "uart1",
151 .modes = pmx_uart1_modes,
152 .mode_count = ARRAY_SIZE(pmx_uart1_modes),
153 .enb_on_reset = 1,
154};
155
156static struct pmx_dev_mode pmx_uart1_modem_modes[] = {
157 {
158 .ids = AUTO_EXP_MODE,
159 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK |
160 PMX_SSP_CS_MASK,
161 }, {
162 .ids = SMALL_PRINTERS_MODE,
163 .mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK |
164 PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK,
165 },
166};
167
168struct pmx_dev spear320_pmx_uart1_modem = {
169 .name = "uart1_modem",
170 .modes = pmx_uart1_modem_modes,
171 .mode_count = ARRAY_SIZE(pmx_uart1_modem_modes),
172 .enb_on_reset = 1,
173};
174
175static struct pmx_dev_mode pmx_uart2_modes[] = {
176 {
177 .ids = ALL_MODES,
178 .mask = PMX_FIRDA_MASK,
179 },
180};
181
182struct pmx_dev spear320_pmx_uart2 = {
183 .name = "uart2",
184 .modes = pmx_uart2_modes,
185 .mode_count = ARRAY_SIZE(pmx_uart2_modes),
186 .enb_on_reset = 1,
187};
188
189static struct pmx_dev_mode pmx_touchscreen_modes[] = {
190 {
191 .ids = AUTO_NET_SMII_MODE,
192 .mask = PMX_SSP_CS_MASK,
193 },
194};
195
196struct pmx_dev spear320_pmx_touchscreen = {
197 .name = "touchscreen",
198 .modes = pmx_touchscreen_modes,
199 .mode_count = ARRAY_SIZE(pmx_touchscreen_modes),
200 .enb_on_reset = 1,
201};
202
203static struct pmx_dev_mode pmx_can_modes[] = {
204 {
205 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE,
206 .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
207 PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
208 },
209};
210
211struct pmx_dev spear320_pmx_can = {
212 .name = "can",
213 .modes = pmx_can_modes,
214 .mode_count = ARRAY_SIZE(pmx_can_modes),
215 .enb_on_reset = 1,
216};
217
218static struct pmx_dev_mode pmx_sdhci_led_modes[] = {
219 {
220 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
221 .mask = PMX_SSP_CS_MASK,
222 },
223};
224
225struct pmx_dev spear320_pmx_sdhci_led = {
226 .name = "sdhci_led",
227 .modes = pmx_sdhci_led_modes,
228 .mode_count = ARRAY_SIZE(pmx_sdhci_led_modes),
229 .enb_on_reset = 1,
230};
231
232static struct pmx_dev_mode pmx_pwm0_modes[] = {
233 {
234 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
235 .mask = PMX_UART0_MODEM_MASK,
236 }, {
237 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
238 .mask = PMX_MII_MASK,
239 },
240};
241
242struct pmx_dev spear320_pmx_pwm0 = {
243 .name = "pwm0",
244 .modes = pmx_pwm0_modes,
245 .mode_count = ARRAY_SIZE(pmx_pwm0_modes),
246 .enb_on_reset = 1,
247};
248
249static struct pmx_dev_mode pmx_pwm1_modes[] = {
250 {
251 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
252 .mask = PMX_UART0_MODEM_MASK,
253 }, {
254 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
255 .mask = PMX_MII_MASK,
256 },
257};
258
259struct pmx_dev spear320_pmx_pwm1 = {
260 .name = "pwm1",
261 .modes = pmx_pwm1_modes,
262 .mode_count = ARRAY_SIZE(pmx_pwm1_modes),
263 .enb_on_reset = 1,
264};
265
266static struct pmx_dev_mode pmx_pwm2_modes[] = {
267 {
268 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
269 .mask = PMX_SSP_CS_MASK,
270 }, {
271 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
272 .mask = PMX_MII_MASK,
273 },
274};
275
276struct pmx_dev spear320_pmx_pwm2 = {
277 .name = "pwm2",
278 .modes = pmx_pwm2_modes,
279 .mode_count = ARRAY_SIZE(pmx_pwm2_modes),
280 .enb_on_reset = 1,
281};
282
283static struct pmx_dev_mode pmx_pwm3_modes[] = {
284 {
285 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
286 .mask = PMX_MII_MASK,
287 },
288};
289
290struct pmx_dev spear320_pmx_pwm3 = {
291 .name = "pwm3",
292 .modes = pmx_pwm3_modes,
293 .mode_count = ARRAY_SIZE(pmx_pwm3_modes),
294 .enb_on_reset = 1,
295};
296
297static struct pmx_dev_mode pmx_ssp1_modes[] = {
298 {
299 .ids = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
300 .mask = PMX_MII_MASK,
301 },
302};
303
304struct pmx_dev spear320_pmx_ssp1 = {
305 .name = "ssp1",
306 .modes = pmx_ssp1_modes,
307 .mode_count = ARRAY_SIZE(pmx_ssp1_modes),
308 .enb_on_reset = 1,
309};
310
311static struct pmx_dev_mode pmx_ssp2_modes[] = {
312 {
313 .ids = AUTO_NET_SMII_MODE,
314 .mask = PMX_MII_MASK,
315 },
316};
317
318struct pmx_dev spear320_pmx_ssp2 = {
319 .name = "ssp2",
320 .modes = pmx_ssp2_modes,
321 .mode_count = ARRAY_SIZE(pmx_ssp2_modes),
322 .enb_on_reset = 1,
323};
324
325static struct pmx_dev_mode pmx_mii1_modes[] = {
326 {
327 .ids = AUTO_NET_MII_MODE,
328 .mask = 0x0,
329 },
330};
331
332struct pmx_dev spear320_pmx_mii1 = {
333 .name = "mii1",
334 .modes = pmx_mii1_modes,
335 .mode_count = ARRAY_SIZE(pmx_mii1_modes),
336 .enb_on_reset = 1,
337};
338
339static struct pmx_dev_mode pmx_smii0_modes[] = {
340 {
341 .ids = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
342 .mask = PMX_MII_MASK,
343 },
344};
345
346struct pmx_dev spear320_pmx_smii0 = {
347 .name = "smii0",
348 .modes = pmx_smii0_modes,
349 .mode_count = ARRAY_SIZE(pmx_smii0_modes),
350 .enb_on_reset = 1,
351};
352
353static struct pmx_dev_mode pmx_smii1_modes[] = {
354 {
355 .ids = AUTO_NET_SMII_MODE | SMALL_PRINTERS_MODE,
356 .mask = PMX_MII_MASK,
357 },
358};
359
360struct pmx_dev spear320_pmx_smii1 = {
361 .name = "smii1",
362 .modes = pmx_smii1_modes,
363 .mode_count = ARRAY_SIZE(pmx_smii1_modes),
364 .enb_on_reset = 1,
365};
366
367static struct pmx_dev_mode pmx_i2c1_modes[] = {
368 {
369 .ids = AUTO_EXP_MODE,
370 .mask = 0x0,
371 },
372};
373
374struct pmx_dev spear320_pmx_i2c1 = {
375 .name = "i2c1",
376 .modes = pmx_i2c1_modes,
377 .mode_count = ARRAY_SIZE(pmx_i2c1_modes),
378 .enb_on_reset = 1,
379};
380
381/* pmx driver structure */
382static struct pmx_driver pmx_driver = {
383 .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x00000007},
384 .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
385};
386 84
387/* spear3xx shared irq */ 85/* spear3xx shared irq */
388static struct shirq_dev_config shirq_ras1_config[] = { 86static struct shirq_dev_config shirq_ras1_config[] = {
@@ -508,17 +206,250 @@ static struct spear_shirq shirq_intrcomm_ras = {
508 }, 206 },
509}; 207};
510 208
511/* Add spear320 specific devices here */ 209/* DMAC platform data's slave info */
210struct pl08x_channel_data spear320_dma_info[] = {
211 {
212 .bus_id = "uart0_rx",
213 .min_signal = 2,
214 .max_signal = 2,
215 .muxval = 0,
216 .cctl = 0,
217 .periph_buses = PL08X_AHB1,
218 }, {
219 .bus_id = "uart0_tx",
220 .min_signal = 3,
221 .max_signal = 3,
222 .muxval = 0,
223 .cctl = 0,
224 .periph_buses = PL08X_AHB1,
225 }, {
226 .bus_id = "ssp0_rx",
227 .min_signal = 8,
228 .max_signal = 8,
229 .muxval = 0,
230 .cctl = 0,
231 .periph_buses = PL08X_AHB1,
232 }, {
233 .bus_id = "ssp0_tx",
234 .min_signal = 9,
235 .max_signal = 9,
236 .muxval = 0,
237 .cctl = 0,
238 .periph_buses = PL08X_AHB1,
239 }, {
240 .bus_id = "i2c0_rx",
241 .min_signal = 10,
242 .max_signal = 10,
243 .muxval = 0,
244 .cctl = 0,
245 .periph_buses = PL08X_AHB1,
246 }, {
247 .bus_id = "i2c0_tx",
248 .min_signal = 11,
249 .max_signal = 11,
250 .muxval = 0,
251 .cctl = 0,
252 .periph_buses = PL08X_AHB1,
253 }, {
254 .bus_id = "irda",
255 .min_signal = 12,
256 .max_signal = 12,
257 .muxval = 0,
258 .cctl = 0,
259 .periph_buses = PL08X_AHB1,
260 }, {
261 .bus_id = "adc",
262 .min_signal = 13,
263 .max_signal = 13,
264 .muxval = 0,
265 .cctl = 0,
266 .periph_buses = PL08X_AHB1,
267 }, {
268 .bus_id = "to_jpeg",
269 .min_signal = 14,
270 .max_signal = 14,
271 .muxval = 0,
272 .cctl = 0,
273 .periph_buses = PL08X_AHB1,
274 }, {
275 .bus_id = "from_jpeg",
276 .min_signal = 15,
277 .max_signal = 15,
278 .muxval = 0,
279 .cctl = 0,
280 .periph_buses = PL08X_AHB1,
281 }, {
282 .bus_id = "ssp1_rx",
283 .min_signal = 0,
284 .max_signal = 0,
285 .muxval = 1,
286 .cctl = 0,
287 .periph_buses = PL08X_AHB2,
288 }, {
289 .bus_id = "ssp1_tx",
290 .min_signal = 1,
291 .max_signal = 1,
292 .muxval = 1,
293 .cctl = 0,
294 .periph_buses = PL08X_AHB2,
295 }, {
296 .bus_id = "ssp2_rx",
297 .min_signal = 2,
298 .max_signal = 2,
299 .muxval = 1,
300 .cctl = 0,
301 .periph_buses = PL08X_AHB2,
302 }, {
303 .bus_id = "ssp2_tx",
304 .min_signal = 3,
305 .max_signal = 3,
306 .muxval = 1,
307 .cctl = 0,
308 .periph_buses = PL08X_AHB2,
309 }, {
310 .bus_id = "uart1_rx",
311 .min_signal = 4,
312 .max_signal = 4,
313 .muxval = 1,
314 .cctl = 0,
315 .periph_buses = PL08X_AHB2,
316 }, {
317 .bus_id = "uart1_tx",
318 .min_signal = 5,
319 .max_signal = 5,
320 .muxval = 1,
321 .cctl = 0,
322 .periph_buses = PL08X_AHB2,
323 }, {
324 .bus_id = "uart2_rx",
325 .min_signal = 6,
326 .max_signal = 6,
327 .muxval = 1,
328 .cctl = 0,
329 .periph_buses = PL08X_AHB2,
330 }, {
331 .bus_id = "uart2_tx",
332 .min_signal = 7,
333 .max_signal = 7,
334 .muxval = 1,
335 .cctl = 0,
336 .periph_buses = PL08X_AHB2,
337 }, {
338 .bus_id = "i2c1_rx",
339 .min_signal = 8,
340 .max_signal = 8,
341 .muxval = 1,
342 .cctl = 0,
343 .periph_buses = PL08X_AHB2,
344 }, {
345 .bus_id = "i2c1_tx",
346 .min_signal = 9,
347 .max_signal = 9,
348 .muxval = 1,
349 .cctl = 0,
350 .periph_buses = PL08X_AHB2,
351 }, {
352 .bus_id = "i2c2_rx",
353 .min_signal = 10,
354 .max_signal = 10,
355 .muxval = 1,
356 .cctl = 0,
357 .periph_buses = PL08X_AHB2,
358 }, {
359 .bus_id = "i2c2_tx",
360 .min_signal = 11,
361 .max_signal = 11,
362 .muxval = 1,
363 .cctl = 0,
364 .periph_buses = PL08X_AHB2,
365 }, {
366 .bus_id = "i2s_rx",
367 .min_signal = 12,
368 .max_signal = 12,
369 .muxval = 1,
370 .cctl = 0,
371 .periph_buses = PL08X_AHB2,
372 }, {
373 .bus_id = "i2s_tx",
374 .min_signal = 13,
375 .max_signal = 13,
376 .muxval = 1,
377 .cctl = 0,
378 .periph_buses = PL08X_AHB2,
379 }, {
380 .bus_id = "rs485_rx",
381 .min_signal = 14,
382 .max_signal = 14,
383 .muxval = 1,
384 .cctl = 0,
385 .periph_buses = PL08X_AHB2,
386 }, {
387 .bus_id = "rs485_tx",
388 .min_signal = 15,
389 .max_signal = 15,
390 .muxval = 1,
391 .cctl = 0,
392 .periph_buses = PL08X_AHB2,
393 },
394};
395
396static struct pl022_ssp_controller spear320_ssp_data[] = {
397 {
398 .bus_id = 1,
399 .enable_dma = 1,
400 .dma_filter = pl08x_filter_id,
401 .dma_tx_param = "ssp1_tx",
402 .dma_rx_param = "ssp1_rx",
403 .num_chipselect = 2,
404 }, {
405 .bus_id = 2,
406 .enable_dma = 1,
407 .dma_filter = pl08x_filter_id,
408 .dma_tx_param = "ssp2_tx",
409 .dma_rx_param = "ssp2_rx",
410 .num_chipselect = 2,
411 }
412};
413
414static struct amba_pl011_data spear320_uart_data[] = {
415 {
416 .dma_filter = pl08x_filter_id,
417 .dma_tx_param = "uart1_tx",
418 .dma_rx_param = "uart1_rx",
419 }, {
420 .dma_filter = pl08x_filter_id,
421 .dma_tx_param = "uart2_tx",
422 .dma_rx_param = "uart2_rx",
423 },
424};
512 425
513/* spear320 routines */ 426/* Add SPEAr310 auxdata to pass platform data */
514void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs, 427static struct of_dev_auxdata spear320_auxdata_lookup[] __initdata = {
515 u8 pmx_dev_count) 428 OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
429 &pl022_plat_data),
430 OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
431 &pl080_plat_data),
432 OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP0_BASE, NULL,
433 &spear320_ssp_data[0]),
434 OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP1_BASE, NULL,
435 &spear320_ssp_data[1]),
436 OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART1_BASE, NULL,
437 &spear320_uart_data[0]),
438 OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART2_BASE, NULL,
439 &spear320_uart_data[1]),
440 {}
441};
442
443static void __init spear320_dt_init(void)
516{ 444{
517 void __iomem *base; 445 void __iomem *base;
518 int ret = 0; 446 int ret;
519 447
520 /* call spear3xx family common init function */ 448 pl080_plat_data.slave_channels = spear320_dma_info;
521 spear3xx_init(); 449 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info);
450
451 of_platform_populate(NULL, of_default_bus_match_table,
452 spear320_auxdata_lookup, NULL);
522 453
523 /* shared irq registration */ 454 /* shared irq registration */
524 base = ioremap(SPEAR320_SOC_CONFIG_BASE, SZ_4K); 455 base = ioremap(SPEAR320_SOC_CONFIG_BASE, SZ_4K);
@@ -527,29 +458,49 @@ void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
527 shirq_ras1.regs.base = base; 458 shirq_ras1.regs.base = base;
528 ret = spear_shirq_register(&shirq_ras1); 459 ret = spear_shirq_register(&shirq_ras1);
529 if (ret) 460 if (ret)
530 printk(KERN_ERR "Error registering Shared IRQ 1\n"); 461 pr_err("Error registering Shared IRQ 1\n");
531 462
532 /* shirq 3 */ 463 /* shirq 3 */
533 shirq_ras3.regs.base = base; 464 shirq_ras3.regs.base = base;
534 ret = spear_shirq_register(&shirq_ras3); 465 ret = spear_shirq_register(&shirq_ras3);
535 if (ret) 466 if (ret)
536 printk(KERN_ERR "Error registering Shared IRQ 3\n"); 467 pr_err("Error registering Shared IRQ 3\n");
537 468
538 /* shirq 4 */ 469 /* shirq 4 */
539 shirq_intrcomm_ras.regs.base = base; 470 shirq_intrcomm_ras.regs.base = base;
540 ret = spear_shirq_register(&shirq_intrcomm_ras); 471 ret = spear_shirq_register(&shirq_intrcomm_ras);
541 if (ret) 472 if (ret)
542 printk(KERN_ERR "Error registering Shared IRQ 4\n"); 473 pr_err("Error registering Shared IRQ 4\n");
543 } 474 }
475}
476
477static const char * const spear320_dt_board_compat[] = {
478 "st,spear320",
479 "st,spear320-evb",
480 NULL,
481};
544 482
545 /* pmx initialization */ 483struct map_desc spear320_io_desc[] __initdata = {
546 pmx_driver.base = base; 484 {
547 pmx_driver.mode = pmx_mode; 485 .virtual = VA_SPEAR320_SOC_CONFIG_BASE,
548 pmx_driver.devs = pmx_devs; 486 .pfn = __phys_to_pfn(SPEAR320_SOC_CONFIG_BASE),
549 pmx_driver.devs_count = pmx_dev_count; 487 .length = SZ_16M,
488 .type = MT_DEVICE
489 },
490};
550 491
551 ret = pmx_register(&pmx_driver); 492static void __init spear320_map_io(void)
552 if (ret) 493{
553 printk(KERN_ERR "padmux: registration failed. err no: %d\n", 494 iotable_init(spear320_io_desc, ARRAY_SIZE(spear320_io_desc));
554 ret); 495 spear3xx_map_io();
555} 496}
497
498DT_MACHINE_START(SPEAR320_DT, "ST SPEAr320 SoC with Flattened Device Tree")
499 .map_io = spear320_map_io,
500 .init_irq = spear3xx_dt_init_irq,
501 .handle_irq = vic_handle_irq,
502 .timer = &spear3xx_timer,
503 .init_machine = spear320_dt_init,
504 .restart = spear_restart,
505 .dt_compat = spear320_dt_board_compat,
506MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c
deleted file mode 100644
index 105334ab7021..000000000000
--- a/arch/arm/mach-spear3xx/spear320_evb.c
+++ /dev/null
@@ -1,79 +0,0 @@
1/*
2 * arch/arm/mach-spear3xx/spear320_evb.c
3 *
4 * SPEAr320 evaluation board source file
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <asm/hardware/vic.h>
15#include <asm/mach/arch.h>
16#include <asm/mach-types.h>
17#include <mach/generic.h>
18#include <mach/hardware.h>
19
20/* padmux devices to enable */
21static struct pmx_dev *pmx_devs[] = {
22 /* spear3xx specific devices */
23 &spear3xx_pmx_i2c,
24 &spear3xx_pmx_ssp,
25 &spear3xx_pmx_mii,
26 &spear3xx_pmx_uart0,
27
28 /* spear320 specific devices */
29 &spear320_pmx_fsmc,
30 &spear320_pmx_sdhci,
31 &spear320_pmx_i2s,
32 &spear320_pmx_uart1,
33 &spear320_pmx_uart2,
34 &spear320_pmx_can,
35 &spear320_pmx_pwm0,
36 &spear320_pmx_pwm1,
37 &spear320_pmx_pwm2,
38 &spear320_pmx_mii1,
39};
40
41static struct amba_device *amba_devs[] __initdata = {
42 /* spear3xx specific devices */
43 &spear3xx_gpio_device,
44 &spear3xx_uart_device,
45
46 /* spear320 specific devices */
47};
48
49static struct platform_device *plat_devs[] __initdata = {
50 /* spear3xx specific devices */
51
52 /* spear320 specific devices */
53};
54
55static void __init spear320_evb_init(void)
56{
57 unsigned int i;
58
59 /* call spear320 machine init function */
60 spear320_init(&spear320_auto_net_mii_mode, pmx_devs,
61 ARRAY_SIZE(pmx_devs));
62
63 /* Add Platform Devices */
64 platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
65
66 /* Add Amba Devices */
67 for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
68 amba_device_register(amba_devs[i], &iomem_resource);
69}
70
71MACHINE_START(SPEAR320, "ST-SPEAR320-EVB")
72 .atag_offset = 0x100,
73 .map_io = spear3xx_map_io,
74 .init_irq = spear3xx_init_irq,
75 .handle_irq = vic_handle_irq,
76 .timer = &spear3xx_timer,
77 .init_machine = spear320_evb_init,
78 .restart = spear_restart,
79MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index b1733c37f209..f22419ed74a8 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -3,71 +3,78 @@
3 * 3 *
4 * SPEAr3XX machines common source file 4 * SPEAr3XX machines common source file
5 * 5 *
6 * Copyright (C) 2009 ST Microelectronics 6 * Copyright (C) 2009-2012 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com> 7 * Viresh Kumar <viresh.kumar@st.com>
8 * 8 *
9 * This file is licensed under the terms of the GNU General Public 9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any 10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied. 11 * warranty of any kind, whether express or implied.
12 */ 12 */
13 13
14#include <linux/types.h> 14#define pr_fmt(fmt) "SPEAr3xx: " fmt
15#include <linux/amba/pl061.h> 15
16#include <linux/ptrace.h> 16#include <linux/amba/pl022.h>
17#include <linux/amba/pl08x.h>
18#include <linux/of_irq.h>
17#include <linux/io.h> 19#include <linux/io.h>
20#include <asm/hardware/pl080.h>
18#include <asm/hardware/vic.h> 21#include <asm/hardware/vic.h>
19#include <asm/irq.h> 22#include <plat/pl080.h>
20#include <asm/mach/arch.h>
21#include <mach/generic.h> 23#include <mach/generic.h>
22#include <mach/hardware.h> 24#include <mach/spear.h>
23 25
24/* Add spear3xx machines common devices here */ 26/* ssp device registration */
25/* gpio device registration */ 27struct pl022_ssp_controller pl022_plat_data = {
26static struct pl061_platform_data gpio_plat_data = { 28 .bus_id = 0,
27 .gpio_base = 0, 29 .enable_dma = 1,
28 .irq_base = SPEAR3XX_GPIO_INT_BASE, 30 .dma_filter = pl08x_filter_id,
31 .dma_tx_param = "ssp0_tx",
32 .dma_rx_param = "ssp0_rx",
33 /*
34 * This is number of spi devices that can be connected to spi. There are
35 * two type of chipselects on which slave devices can work. One is chip
36 * select provided by spi masters other is controlled through external
37 * gpio's. We can't use chipselect provided from spi master (because as
38 * soon as FIFO becomes empty, CS is disabled and transfer ends). So
39 * this number now depends on number of gpios available for spi. each
40 * slave on each master requires a separate gpio pin.
41 */
42 .num_chipselect = 2,
43};
44
45/* dmac device registration */
46struct pl08x_platform_data pl080_plat_data = {
47 .memcpy_channel = {
48 .bus_id = "memcpy",
49 .cctl = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
50 PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
51 PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
52 PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
53 PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \
54 PL080_CONTROL_PROT_SYS),
55 },
56 .lli_buses = PL08X_AHB1,
57 .mem_buses = PL08X_AHB1,
58 .get_signal = pl080_get_signal,
59 .put_signal = pl080_put_signal,
29}; 60};
30 61
31AMBA_APB_DEVICE(spear3xx_gpio, "gpio", 0, SPEAR3XX_ICM3_GPIO_BASE, 62/*
32 {SPEAR3XX_IRQ_BASIC_GPIO}, &gpio_plat_data); 63 * Following will create 16MB static virtual/physical mappings
33 64 * PHYSICAL VIRTUAL
34/* uart device registration */ 65 * 0xD0000000 0xFD000000
35AMBA_APB_DEVICE(spear3xx_uart, "uart", 0, SPEAR3XX_ICM1_UART_BASE, 66 * 0xFC000000 0xFC000000
36 {SPEAR3XX_IRQ_UART}, NULL); 67 */
37
38/* Do spear3xx familiy common initialization part here */
39void __init spear3xx_init(void)
40{
41 /* nothing to do for now */
42}
43
44/* This will initialize vic */
45void __init spear3xx_init_irq(void)
46{
47 vic_init((void __iomem *)VA_SPEAR3XX_ML1_VIC_BASE, 0, ~0, 0);
48}
49
50/* Following will create static virtual/physical mappings */
51struct map_desc spear3xx_io_desc[] __initdata = { 68struct map_desc spear3xx_io_desc[] __initdata = {
52 { 69 {
53 .virtual = VA_SPEAR3XX_ICM1_UART_BASE, 70 .virtual = VA_SPEAR3XX_ICM1_2_BASE,
54 .pfn = __phys_to_pfn(SPEAR3XX_ICM1_UART_BASE), 71 .pfn = __phys_to_pfn(SPEAR3XX_ICM1_2_BASE),
55 .length = SZ_4K, 72 .length = SZ_16M,
56 .type = MT_DEVICE
57 }, {
58 .virtual = VA_SPEAR3XX_ML1_VIC_BASE,
59 .pfn = __phys_to_pfn(SPEAR3XX_ML1_VIC_BASE),
60 .length = SZ_4K,
61 .type = MT_DEVICE
62 }, {
63 .virtual = VA_SPEAR3XX_ICM3_SYS_CTRL_BASE,
64 .pfn = __phys_to_pfn(SPEAR3XX_ICM3_SYS_CTRL_BASE),
65 .length = SZ_4K,
66 .type = MT_DEVICE 73 .type = MT_DEVICE
67 }, { 74 }, {
68 .virtual = VA_SPEAR3XX_ICM3_MISC_REG_BASE, 75 .virtual = VA_SPEAR3XX_ICM3_SMI_CTRL_BASE,
69 .pfn = __phys_to_pfn(SPEAR3XX_ICM3_MISC_REG_BASE), 76 .pfn = __phys_to_pfn(SPEAR3XX_ICM3_SMI_CTRL_BASE),
70 .length = SZ_4K, 77 .length = SZ_16M,
71 .type = MT_DEVICE 78 .type = MT_DEVICE
72 }, 79 },
73}; 80};
@@ -76,441 +83,15 @@ struct map_desc spear3xx_io_desc[] __initdata = {
76void __init spear3xx_map_io(void) 83void __init spear3xx_map_io(void)
77{ 84{
78 iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc)); 85 iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc));
79
80 /* This will initialize clock framework */
81 spear3xx_clk_init();
82} 86}
83 87
84/* pad multiplexing support */
85/* devices */
86static struct pmx_dev_mode pmx_firda_modes[] = {
87 {
88 .ids = 0xffffffff,
89 .mask = PMX_FIRDA_MASK,
90 },
91};
92
93struct pmx_dev spear3xx_pmx_firda = {
94 .name = "firda",
95 .modes = pmx_firda_modes,
96 .mode_count = ARRAY_SIZE(pmx_firda_modes),
97 .enb_on_reset = 0,
98};
99
100static struct pmx_dev_mode pmx_i2c_modes[] = {
101 {
102 .ids = 0xffffffff,
103 .mask = PMX_I2C_MASK,
104 },
105};
106
107struct pmx_dev spear3xx_pmx_i2c = {
108 .name = "i2c",
109 .modes = pmx_i2c_modes,
110 .mode_count = ARRAY_SIZE(pmx_i2c_modes),
111 .enb_on_reset = 0,
112};
113
114static struct pmx_dev_mode pmx_ssp_cs_modes[] = {
115 {
116 .ids = 0xffffffff,
117 .mask = PMX_SSP_CS_MASK,
118 },
119};
120
121struct pmx_dev spear3xx_pmx_ssp_cs = {
122 .name = "ssp_chip_selects",
123 .modes = pmx_ssp_cs_modes,
124 .mode_count = ARRAY_SIZE(pmx_ssp_cs_modes),
125 .enb_on_reset = 0,
126};
127
128static struct pmx_dev_mode pmx_ssp_modes[] = {
129 {
130 .ids = 0xffffffff,
131 .mask = PMX_SSP_MASK,
132 },
133};
134
135struct pmx_dev spear3xx_pmx_ssp = {
136 .name = "ssp",
137 .modes = pmx_ssp_modes,
138 .mode_count = ARRAY_SIZE(pmx_ssp_modes),
139 .enb_on_reset = 0,
140};
141
142static struct pmx_dev_mode pmx_mii_modes[] = {
143 {
144 .ids = 0xffffffff,
145 .mask = PMX_MII_MASK,
146 },
147};
148
149struct pmx_dev spear3xx_pmx_mii = {
150 .name = "mii",
151 .modes = pmx_mii_modes,
152 .mode_count = ARRAY_SIZE(pmx_mii_modes),
153 .enb_on_reset = 0,
154};
155
156static struct pmx_dev_mode pmx_gpio_pin0_modes[] = {
157 {
158 .ids = 0xffffffff,
159 .mask = PMX_GPIO_PIN0_MASK,
160 },
161};
162
163struct pmx_dev spear3xx_pmx_gpio_pin0 = {
164 .name = "gpio_pin0",
165 .modes = pmx_gpio_pin0_modes,
166 .mode_count = ARRAY_SIZE(pmx_gpio_pin0_modes),
167 .enb_on_reset = 0,
168};
169
170static struct pmx_dev_mode pmx_gpio_pin1_modes[] = {
171 {
172 .ids = 0xffffffff,
173 .mask = PMX_GPIO_PIN1_MASK,
174 },
175};
176
177struct pmx_dev spear3xx_pmx_gpio_pin1 = {
178 .name = "gpio_pin1",
179 .modes = pmx_gpio_pin1_modes,
180 .mode_count = ARRAY_SIZE(pmx_gpio_pin1_modes),
181 .enb_on_reset = 0,
182};
183
184static struct pmx_dev_mode pmx_gpio_pin2_modes[] = {
185 {
186 .ids = 0xffffffff,
187 .mask = PMX_GPIO_PIN2_MASK,
188 },
189};
190
191struct pmx_dev spear3xx_pmx_gpio_pin2 = {
192 .name = "gpio_pin2",
193 .modes = pmx_gpio_pin2_modes,
194 .mode_count = ARRAY_SIZE(pmx_gpio_pin2_modes),
195 .enb_on_reset = 0,
196};
197
198static struct pmx_dev_mode pmx_gpio_pin3_modes[] = {
199 {
200 .ids = 0xffffffff,
201 .mask = PMX_GPIO_PIN3_MASK,
202 },
203};
204
205struct pmx_dev spear3xx_pmx_gpio_pin3 = {
206 .name = "gpio_pin3",
207 .modes = pmx_gpio_pin3_modes,
208 .mode_count = ARRAY_SIZE(pmx_gpio_pin3_modes),
209 .enb_on_reset = 0,
210};
211
212static struct pmx_dev_mode pmx_gpio_pin4_modes[] = {
213 {
214 .ids = 0xffffffff,
215 .mask = PMX_GPIO_PIN4_MASK,
216 },
217};
218
219struct pmx_dev spear3xx_pmx_gpio_pin4 = {
220 .name = "gpio_pin4",
221 .modes = pmx_gpio_pin4_modes,
222 .mode_count = ARRAY_SIZE(pmx_gpio_pin4_modes),
223 .enb_on_reset = 0,
224};
225
226static struct pmx_dev_mode pmx_gpio_pin5_modes[] = {
227 {
228 .ids = 0xffffffff,
229 .mask = PMX_GPIO_PIN5_MASK,
230 },
231};
232
233struct pmx_dev spear3xx_pmx_gpio_pin5 = {
234 .name = "gpio_pin5",
235 .modes = pmx_gpio_pin5_modes,
236 .mode_count = ARRAY_SIZE(pmx_gpio_pin5_modes),
237 .enb_on_reset = 0,
238};
239
240static struct pmx_dev_mode pmx_uart0_modem_modes[] = {
241 {
242 .ids = 0xffffffff,
243 .mask = PMX_UART0_MODEM_MASK,
244 },
245};
246
247struct pmx_dev spear3xx_pmx_uart0_modem = {
248 .name = "uart0_modem",
249 .modes = pmx_uart0_modem_modes,
250 .mode_count = ARRAY_SIZE(pmx_uart0_modem_modes),
251 .enb_on_reset = 0,
252};
253
254static struct pmx_dev_mode pmx_uart0_modes[] = {
255 {
256 .ids = 0xffffffff,
257 .mask = PMX_UART0_MASK,
258 },
259};
260
261struct pmx_dev spear3xx_pmx_uart0 = {
262 .name = "uart0",
263 .modes = pmx_uart0_modes,
264 .mode_count = ARRAY_SIZE(pmx_uart0_modes),
265 .enb_on_reset = 0,
266};
267
268static struct pmx_dev_mode pmx_timer_3_4_modes[] = {
269 {
270 .ids = 0xffffffff,
271 .mask = PMX_TIMER_3_4_MASK,
272 },
273};
274
275struct pmx_dev spear3xx_pmx_timer_3_4 = {
276 .name = "timer_3_4",
277 .modes = pmx_timer_3_4_modes,
278 .mode_count = ARRAY_SIZE(pmx_timer_3_4_modes),
279 .enb_on_reset = 0,
280};
281
282static struct pmx_dev_mode pmx_timer_1_2_modes[] = {
283 {
284 .ids = 0xffffffff,
285 .mask = PMX_TIMER_1_2_MASK,
286 },
287};
288
289struct pmx_dev spear3xx_pmx_timer_1_2 = {
290 .name = "timer_1_2",
291 .modes = pmx_timer_1_2_modes,
292 .mode_count = ARRAY_SIZE(pmx_timer_1_2_modes),
293 .enb_on_reset = 0,
294};
295
296#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
297/* plgpios devices */
298static struct pmx_dev_mode pmx_plgpio_0_1_modes[] = {
299 {
300 .ids = 0x00,
301 .mask = PMX_FIRDA_MASK,
302 },
303};
304
305struct pmx_dev spear3xx_pmx_plgpio_0_1 = {
306 .name = "plgpio 0 and 1",
307 .modes = pmx_plgpio_0_1_modes,
308 .mode_count = ARRAY_SIZE(pmx_plgpio_0_1_modes),
309 .enb_on_reset = 1,
310};
311
312static struct pmx_dev_mode pmx_plgpio_2_3_modes[] = {
313 {
314 .ids = 0x00,
315 .mask = PMX_UART0_MASK,
316 },
317};
318
319struct pmx_dev spear3xx_pmx_plgpio_2_3 = {
320 .name = "plgpio 2 and 3",
321 .modes = pmx_plgpio_2_3_modes,
322 .mode_count = ARRAY_SIZE(pmx_plgpio_2_3_modes),
323 .enb_on_reset = 1,
324};
325
326static struct pmx_dev_mode pmx_plgpio_4_5_modes[] = {
327 {
328 .ids = 0x00,
329 .mask = PMX_I2C_MASK,
330 },
331};
332
333struct pmx_dev spear3xx_pmx_plgpio_4_5 = {
334 .name = "plgpio 4 and 5",
335 .modes = pmx_plgpio_4_5_modes,
336 .mode_count = ARRAY_SIZE(pmx_plgpio_4_5_modes),
337 .enb_on_reset = 1,
338};
339
340static struct pmx_dev_mode pmx_plgpio_6_9_modes[] = {
341 {
342 .ids = 0x00,
343 .mask = PMX_SSP_MASK,
344 },
345};
346
347struct pmx_dev spear3xx_pmx_plgpio_6_9 = {
348 .name = "plgpio 6 to 9",
349 .modes = pmx_plgpio_6_9_modes,
350 .mode_count = ARRAY_SIZE(pmx_plgpio_6_9_modes),
351 .enb_on_reset = 1,
352};
353
354static struct pmx_dev_mode pmx_plgpio_10_27_modes[] = {
355 {
356 .ids = 0x00,
357 .mask = PMX_MII_MASK,
358 },
359};
360
361struct pmx_dev spear3xx_pmx_plgpio_10_27 = {
362 .name = "plgpio 10 to 27",
363 .modes = pmx_plgpio_10_27_modes,
364 .mode_count = ARRAY_SIZE(pmx_plgpio_10_27_modes),
365 .enb_on_reset = 1,
366};
367
368static struct pmx_dev_mode pmx_plgpio_28_modes[] = {
369 {
370 .ids = 0x00,
371 .mask = PMX_GPIO_PIN0_MASK,
372 },
373};
374
375struct pmx_dev spear3xx_pmx_plgpio_28 = {
376 .name = "plgpio 28",
377 .modes = pmx_plgpio_28_modes,
378 .mode_count = ARRAY_SIZE(pmx_plgpio_28_modes),
379 .enb_on_reset = 1,
380};
381
382static struct pmx_dev_mode pmx_plgpio_29_modes[] = {
383 {
384 .ids = 0x00,
385 .mask = PMX_GPIO_PIN1_MASK,
386 },
387};
388
389struct pmx_dev spear3xx_pmx_plgpio_29 = {
390 .name = "plgpio 29",
391 .modes = pmx_plgpio_29_modes,
392 .mode_count = ARRAY_SIZE(pmx_plgpio_29_modes),
393 .enb_on_reset = 1,
394};
395
396static struct pmx_dev_mode pmx_plgpio_30_modes[] = {
397 {
398 .ids = 0x00,
399 .mask = PMX_GPIO_PIN2_MASK,
400 },
401};
402
403struct pmx_dev spear3xx_pmx_plgpio_30 = {
404 .name = "plgpio 30",
405 .modes = pmx_plgpio_30_modes,
406 .mode_count = ARRAY_SIZE(pmx_plgpio_30_modes),
407 .enb_on_reset = 1,
408};
409
410static struct pmx_dev_mode pmx_plgpio_31_modes[] = {
411 {
412 .ids = 0x00,
413 .mask = PMX_GPIO_PIN3_MASK,
414 },
415};
416
417struct pmx_dev spear3xx_pmx_plgpio_31 = {
418 .name = "plgpio 31",
419 .modes = pmx_plgpio_31_modes,
420 .mode_count = ARRAY_SIZE(pmx_plgpio_31_modes),
421 .enb_on_reset = 1,
422};
423
424static struct pmx_dev_mode pmx_plgpio_32_modes[] = {
425 {
426 .ids = 0x00,
427 .mask = PMX_GPIO_PIN4_MASK,
428 },
429};
430
431struct pmx_dev spear3xx_pmx_plgpio_32 = {
432 .name = "plgpio 32",
433 .modes = pmx_plgpio_32_modes,
434 .mode_count = ARRAY_SIZE(pmx_plgpio_32_modes),
435 .enb_on_reset = 1,
436};
437
438static struct pmx_dev_mode pmx_plgpio_33_modes[] = {
439 {
440 .ids = 0x00,
441 .mask = PMX_GPIO_PIN5_MASK,
442 },
443};
444
445struct pmx_dev spear3xx_pmx_plgpio_33 = {
446 .name = "plgpio 33",
447 .modes = pmx_plgpio_33_modes,
448 .mode_count = ARRAY_SIZE(pmx_plgpio_33_modes),
449 .enb_on_reset = 1,
450};
451
452static struct pmx_dev_mode pmx_plgpio_34_36_modes[] = {
453 {
454 .ids = 0x00,
455 .mask = PMX_SSP_CS_MASK,
456 },
457};
458
459struct pmx_dev spear3xx_pmx_plgpio_34_36 = {
460 .name = "plgpio 34 to 36",
461 .modes = pmx_plgpio_34_36_modes,
462 .mode_count = ARRAY_SIZE(pmx_plgpio_34_36_modes),
463 .enb_on_reset = 1,
464};
465
466static struct pmx_dev_mode pmx_plgpio_37_42_modes[] = {
467 {
468 .ids = 0x00,
469 .mask = PMX_UART0_MODEM_MASK,
470 },
471};
472
473struct pmx_dev spear3xx_pmx_plgpio_37_42 = {
474 .name = "plgpio 37 to 42",
475 .modes = pmx_plgpio_37_42_modes,
476 .mode_count = ARRAY_SIZE(pmx_plgpio_37_42_modes),
477 .enb_on_reset = 1,
478};
479
480static struct pmx_dev_mode pmx_plgpio_43_44_47_48_modes[] = {
481 {
482 .ids = 0x00,
483 .mask = PMX_TIMER_1_2_MASK,
484 },
485};
486
487struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48 = {
488 .name = "plgpio 43, 44, 47 and 48",
489 .modes = pmx_plgpio_43_44_47_48_modes,
490 .mode_count = ARRAY_SIZE(pmx_plgpio_43_44_47_48_modes),
491 .enb_on_reset = 1,
492};
493
494static struct pmx_dev_mode pmx_plgpio_45_46_49_50_modes[] = {
495 {
496 .ids = 0x00,
497 .mask = PMX_TIMER_3_4_MASK,
498 },
499};
500
501struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50 = {
502 .name = "plgpio 45, 46, 49 and 50",
503 .modes = pmx_plgpio_45_46_49_50_modes,
504 .mode_count = ARRAY_SIZE(pmx_plgpio_45_46_49_50_modes),
505 .enb_on_reset = 1,
506};
507#endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */
508
509static void __init spear3xx_timer_init(void) 88static void __init spear3xx_timer_init(void)
510{ 89{
511 char pclk_name[] = "pll3_48m_clk"; 90 char pclk_name[] = "pll3_48m_clk";
512 struct clk *gpt_clk, *pclk; 91 struct clk *gpt_clk, *pclk;
513 92
93 spear3xx_clk_init();
94
514 /* get the system timer clock */ 95 /* get the system timer clock */
515 gpt_clk = clk_get_sys("gpt0", NULL); 96 gpt_clk = clk_get_sys("gpt0", NULL);
516 if (IS_ERR(gpt_clk)) { 97 if (IS_ERR(gpt_clk)) {
@@ -530,9 +111,19 @@ static void __init spear3xx_timer_init(void)
530 clk_put(gpt_clk); 111 clk_put(gpt_clk);
531 clk_put(pclk); 112 clk_put(pclk);
532 113
533 spear_setup_timer(); 114 spear_setup_of_timer();
534} 115}
535 116
536struct sys_timer spear3xx_timer = { 117struct sys_timer spear3xx_timer = {
537 .init = spear3xx_timer_init, 118 .init = spear3xx_timer_init,
538}; 119};
120
121static const struct of_device_id vic_of_match[] __initconst = {
122 { .compatible = "arm,pl190-vic", .data = vic_of_init, },
123 { /* Sentinel */ }
124};
125
126void __init spear3xx_dt_init_irq(void)
127{
128 of_irq_init(vic_of_match);
129}
diff --git a/arch/arm/mach-spear6xx/Makefile b/arch/arm/mach-spear6xx/Makefile
index 76e5750552fc..898831d93f37 100644
--- a/arch/arm/mach-spear6xx/Makefile
+++ b/arch/arm/mach-spear6xx/Makefile
@@ -3,4 +3,4 @@
3# 3#
4 4
5# common files 5# common files
6obj-y += clock.o spear6xx.o 6obj-y += spear6xx.o
diff --git a/arch/arm/mach-spear6xx/Makefile.boot b/arch/arm/mach-spear6xx/Makefile.boot
index 4674a4c221db..af493da37ab6 100644
--- a/arch/arm/mach-spear6xx/Makefile.boot
+++ b/arch/arm/mach-spear6xx/Makefile.boot
@@ -1,3 +1,5 @@
1zreladdr-y += 0x00008000 1zreladdr-y += 0x00008000
2params_phys-y := 0x00000100 2params_phys-y := 0x00000100
3initrd_phys-y := 0x00800000 3initrd_phys-y := 0x00800000
4
5dtb-$(CONFIG_BOARD_SPEAR600_DT) += spear600-evb.dtb
diff --git a/arch/arm/mach-spear6xx/clock.c b/arch/arm/mach-spear6xx/clock.c
deleted file mode 100644
index a86499a8a15f..000000000000
--- a/arch/arm/mach-spear6xx/clock.c
+++ /dev/null
@@ -1,683 +0,0 @@
1/*
2 * arch/arm/mach-spear6xx/clock.c
3 *
4 * SPEAr6xx machines clock framework source file
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <linux/init.h>
15#include <linux/io.h>
16#include <linux/kernel.h>
17#include <plat/clock.h>
18#include <mach/misc_regs.h>
19
20/* root clks */
21/* 32 KHz oscillator clock */
22static struct clk osc_32k_clk = {
23 .flags = ALWAYS_ENABLED,
24 .rate = 32000,
25};
26
27/* 30 MHz oscillator clock */
28static struct clk osc_30m_clk = {
29 .flags = ALWAYS_ENABLED,
30 .rate = 30000000,
31};
32
33/* clock derived from 32 KHz osc clk */
34/* rtc clock */
35static struct clk rtc_clk = {
36 .pclk = &osc_32k_clk,
37 .en_reg = PERIP1_CLK_ENB,
38 .en_reg_bit = RTC_CLK_ENB,
39 .recalc = &follow_parent,
40};
41
42/* clock derived from 30 MHz osc clk */
43/* pll masks structure */
44static struct pll_clk_masks pll1_masks = {
45 .mode_mask = PLL_MODE_MASK,
46 .mode_shift = PLL_MODE_SHIFT,
47 .norm_fdbk_m_mask = PLL_NORM_FDBK_M_MASK,
48 .norm_fdbk_m_shift = PLL_NORM_FDBK_M_SHIFT,
49 .dith_fdbk_m_mask = PLL_DITH_FDBK_M_MASK,
50 .dith_fdbk_m_shift = PLL_DITH_FDBK_M_SHIFT,
51 .div_p_mask = PLL_DIV_P_MASK,
52 .div_p_shift = PLL_DIV_P_SHIFT,
53 .div_n_mask = PLL_DIV_N_MASK,
54 .div_n_shift = PLL_DIV_N_SHIFT,
55};
56
57/* pll1 configuration structure */
58static struct pll_clk_config pll1_config = {
59 .mode_reg = PLL1_CTR,
60 .cfg_reg = PLL1_FRQ,
61 .masks = &pll1_masks,
62};
63
64/* pll rate configuration table, in ascending order of rates */
65struct pll_rate_tbl pll_rtbl[] = {
66 {.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* 266 MHz */
67 {.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* 332 MHz */
68};
69
70/* PLL1 clock */
71static struct clk pll1_clk = {
72 .flags = ENABLED_ON_INIT,
73 .pclk = &osc_30m_clk,
74 .en_reg = PLL1_CTR,
75 .en_reg_bit = PLL_ENABLE,
76 .calc_rate = &pll_calc_rate,
77 .recalc = &pll_clk_recalc,
78 .set_rate = &pll_clk_set_rate,
79 .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 1},
80 .private_data = &pll1_config,
81};
82
83/* PLL3 48 MHz clock */
84static struct clk pll3_48m_clk = {
85 .flags = ALWAYS_ENABLED,
86 .pclk = &osc_30m_clk,
87 .rate = 48000000,
88};
89
90/* watch dog timer clock */
91static struct clk wdt_clk = {
92 .flags = ALWAYS_ENABLED,
93 .pclk = &osc_30m_clk,
94 .recalc = &follow_parent,
95};
96
97/* clock derived from pll1 clk */
98/* cpu clock */
99static struct clk cpu_clk = {
100 .flags = ALWAYS_ENABLED,
101 .pclk = &pll1_clk,
102 .recalc = &follow_parent,
103};
104
105/* ahb masks structure */
106static struct bus_clk_masks ahb_masks = {
107 .mask = PLL_HCLK_RATIO_MASK,
108 .shift = PLL_HCLK_RATIO_SHIFT,
109};
110
111/* ahb configuration structure */
112static struct bus_clk_config ahb_config = {
113 .reg = CORE_CLK_CFG,
114 .masks = &ahb_masks,
115};
116
117/* ahb rate configuration table, in ascending order of rates */
118struct bus_rate_tbl bus_rtbl[] = {
119 {.div = 3}, /* == parent divided by 4 */
120 {.div = 2}, /* == parent divided by 3 */
121 {.div = 1}, /* == parent divided by 2 */
122 {.div = 0}, /* == parent divided by 1 */
123};
124
125/* ahb clock */
126static struct clk ahb_clk = {
127 .flags = ALWAYS_ENABLED,
128 .pclk = &pll1_clk,
129 .calc_rate = &bus_calc_rate,
130 .recalc = &bus_clk_recalc,
131 .set_rate = &bus_clk_set_rate,
132 .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
133 .private_data = &ahb_config,
134};
135
136/* auxiliary synthesizers masks */
137static struct aux_clk_masks aux_masks = {
138 .eq_sel_mask = AUX_EQ_SEL_MASK,
139 .eq_sel_shift = AUX_EQ_SEL_SHIFT,
140 .eq1_mask = AUX_EQ1_SEL,
141 .eq2_mask = AUX_EQ2_SEL,
142 .xscale_sel_mask = AUX_XSCALE_MASK,
143 .xscale_sel_shift = AUX_XSCALE_SHIFT,
144 .yscale_sel_mask = AUX_YSCALE_MASK,
145 .yscale_sel_shift = AUX_YSCALE_SHIFT,
146};
147
148/* uart configurations */
149static struct aux_clk_config uart_synth_config = {
150 .synth_reg = UART_CLK_SYNT,
151 .masks = &aux_masks,
152};
153
154/* aux rate configuration table, in ascending order of rates */
155struct aux_rate_tbl aux_rtbl[] = {
156 /* For PLL1 = 332 MHz */
157 {.xscale = 1, .yscale = 8, .eq = 1}, /* 41.5 MHz */
158 {.xscale = 1, .yscale = 4, .eq = 1}, /* 83 MHz */
159 {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
160};
161
162/* uart synth clock */
163static struct clk uart_synth_clk = {
164 .en_reg = UART_CLK_SYNT,
165 .en_reg_bit = AUX_SYNT_ENB,
166 .pclk = &pll1_clk,
167 .calc_rate = &aux_calc_rate,
168 .recalc = &aux_clk_recalc,
169 .set_rate = &aux_clk_set_rate,
170 .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 2},
171 .private_data = &uart_synth_config,
172};
173
174/* uart parents */
175static struct pclk_info uart_pclk_info[] = {
176 {
177 .pclk = &uart_synth_clk,
178 .pclk_val = AUX_CLK_PLL1_VAL,
179 }, {
180 .pclk = &pll3_48m_clk,
181 .pclk_val = AUX_CLK_PLL3_VAL,
182 },
183};
184
185/* uart parent select structure */
186static struct pclk_sel uart_pclk_sel = {
187 .pclk_info = uart_pclk_info,
188 .pclk_count = ARRAY_SIZE(uart_pclk_info),
189 .pclk_sel_reg = PERIP_CLK_CFG,
190 .pclk_sel_mask = UART_CLK_MASK,
191};
192
193/* uart0 clock */
194static struct clk uart0_clk = {
195 .en_reg = PERIP1_CLK_ENB,
196 .en_reg_bit = UART0_CLK_ENB,
197 .pclk_sel = &uart_pclk_sel,
198 .pclk_sel_shift = UART_CLK_SHIFT,
199 .recalc = &follow_parent,
200};
201
202/* uart1 clock */
203static struct clk uart1_clk = {
204 .en_reg = PERIP1_CLK_ENB,
205 .en_reg_bit = UART1_CLK_ENB,
206 .pclk_sel = &uart_pclk_sel,
207 .pclk_sel_shift = UART_CLK_SHIFT,
208 .recalc = &follow_parent,
209};
210
211/* firda configurations */
212static struct aux_clk_config firda_synth_config = {
213 .synth_reg = FIRDA_CLK_SYNT,
214 .masks = &aux_masks,
215};
216
217/* firda synth clock */
218static struct clk firda_synth_clk = {
219 .en_reg = FIRDA_CLK_SYNT,
220 .en_reg_bit = AUX_SYNT_ENB,
221 .pclk = &pll1_clk,
222 .calc_rate = &aux_calc_rate,
223 .recalc = &aux_clk_recalc,
224 .set_rate = &aux_clk_set_rate,
225 .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 2},
226 .private_data = &firda_synth_config,
227};
228
229/* firda parents */
230static struct pclk_info firda_pclk_info[] = {
231 {
232 .pclk = &firda_synth_clk,
233 .pclk_val = AUX_CLK_PLL1_VAL,
234 }, {
235 .pclk = &pll3_48m_clk,
236 .pclk_val = AUX_CLK_PLL3_VAL,
237 },
238};
239
240/* firda parent select structure */
241static struct pclk_sel firda_pclk_sel = {
242 .pclk_info = firda_pclk_info,
243 .pclk_count = ARRAY_SIZE(firda_pclk_info),
244 .pclk_sel_reg = PERIP_CLK_CFG,
245 .pclk_sel_mask = FIRDA_CLK_MASK,
246};
247
248/* firda clock */
249static struct clk firda_clk = {
250 .en_reg = PERIP1_CLK_ENB,
251 .en_reg_bit = FIRDA_CLK_ENB,
252 .pclk_sel = &firda_pclk_sel,
253 .pclk_sel_shift = FIRDA_CLK_SHIFT,
254 .recalc = &follow_parent,
255};
256
257/* clcd configurations */
258static struct aux_clk_config clcd_synth_config = {
259 .synth_reg = CLCD_CLK_SYNT,
260 .masks = &aux_masks,
261};
262
263/* firda synth clock */
264static struct clk clcd_synth_clk = {
265 .en_reg = CLCD_CLK_SYNT,
266 .en_reg_bit = AUX_SYNT_ENB,
267 .pclk = &pll1_clk,
268 .calc_rate = &aux_calc_rate,
269 .recalc = &aux_clk_recalc,
270 .set_rate = &aux_clk_set_rate,
271 .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 2},
272 .private_data = &clcd_synth_config,
273};
274
275/* clcd parents */
276static struct pclk_info clcd_pclk_info[] = {
277 {
278 .pclk = &clcd_synth_clk,
279 .pclk_val = AUX_CLK_PLL1_VAL,
280 }, {
281 .pclk = &pll3_48m_clk,
282 .pclk_val = AUX_CLK_PLL3_VAL,
283 },
284};
285
286/* clcd parent select structure */
287static struct pclk_sel clcd_pclk_sel = {
288 .pclk_info = clcd_pclk_info,
289 .pclk_count = ARRAY_SIZE(clcd_pclk_info),
290 .pclk_sel_reg = PERIP_CLK_CFG,
291 .pclk_sel_mask = CLCD_CLK_MASK,
292};
293
294/* clcd clock */
295static struct clk clcd_clk = {
296 .en_reg = PERIP1_CLK_ENB,
297 .en_reg_bit = CLCD_CLK_ENB,
298 .pclk_sel = &clcd_pclk_sel,
299 .pclk_sel_shift = CLCD_CLK_SHIFT,
300 .recalc = &follow_parent,
301};
302
303/* gpt synthesizer masks */
304static struct gpt_clk_masks gpt_masks = {
305 .mscale_sel_mask = GPT_MSCALE_MASK,
306 .mscale_sel_shift = GPT_MSCALE_SHIFT,
307 .nscale_sel_mask = GPT_NSCALE_MASK,
308 .nscale_sel_shift = GPT_NSCALE_SHIFT,
309};
310
311/* gpt rate configuration table, in ascending order of rates */
312struct gpt_rate_tbl gpt_rtbl[] = {
313 /* For pll1 = 332 MHz */
314 {.mscale = 4, .nscale = 0}, /* 41.5 MHz */
315 {.mscale = 2, .nscale = 0}, /* 55.3 MHz */
316 {.mscale = 1, .nscale = 0}, /* 83 MHz */
317};
318
319/* gpt0 synth clk config*/
320static struct gpt_clk_config gpt0_synth_config = {
321 .synth_reg = PRSC1_CLK_CFG,
322 .masks = &gpt_masks,
323};
324
325/* gpt synth clock */
326static struct clk gpt0_synth_clk = {
327 .flags = ALWAYS_ENABLED,
328 .pclk = &pll1_clk,
329 .calc_rate = &gpt_calc_rate,
330 .recalc = &gpt_clk_recalc,
331 .set_rate = &gpt_clk_set_rate,
332 .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
333 .private_data = &gpt0_synth_config,
334};
335
336/* gpt parents */
337static struct pclk_info gpt0_pclk_info[] = {
338 {
339 .pclk = &gpt0_synth_clk,
340 .pclk_val = AUX_CLK_PLL1_VAL,
341 }, {
342 .pclk = &pll3_48m_clk,
343 .pclk_val = AUX_CLK_PLL3_VAL,
344 },
345};
346
347/* gpt parent select structure */
348static struct pclk_sel gpt0_pclk_sel = {
349 .pclk_info = gpt0_pclk_info,
350 .pclk_count = ARRAY_SIZE(gpt0_pclk_info),
351 .pclk_sel_reg = PERIP_CLK_CFG,
352 .pclk_sel_mask = GPT_CLK_MASK,
353};
354
355/* gpt0 ARM1 subsystem timer clock */
356static struct clk gpt0_clk = {
357 .flags = ALWAYS_ENABLED,
358 .pclk_sel = &gpt0_pclk_sel,
359 .pclk_sel_shift = GPT0_CLK_SHIFT,
360 .recalc = &follow_parent,
361};
362
363
364/* Note: gpt0 and gpt1 share same parent clocks */
365/* gpt parent select structure */
366static struct pclk_sel gpt1_pclk_sel = {
367 .pclk_info = gpt0_pclk_info,
368 .pclk_count = ARRAY_SIZE(gpt0_pclk_info),
369 .pclk_sel_reg = PERIP_CLK_CFG,
370 .pclk_sel_mask = GPT_CLK_MASK,
371};
372
373/* gpt1 timer clock */
374static struct clk gpt1_clk = {
375 .flags = ALWAYS_ENABLED,
376 .pclk_sel = &gpt1_pclk_sel,
377 .pclk_sel_shift = GPT1_CLK_SHIFT,
378 .recalc = &follow_parent,
379};
380
381/* gpt2 synth clk config*/
382static struct gpt_clk_config gpt2_synth_config = {
383 .synth_reg = PRSC2_CLK_CFG,
384 .masks = &gpt_masks,
385};
386
387/* gpt synth clock */
388static struct clk gpt2_synth_clk = {
389 .flags = ALWAYS_ENABLED,
390 .pclk = &pll1_clk,
391 .calc_rate = &gpt_calc_rate,
392 .recalc = &gpt_clk_recalc,
393 .set_rate = &gpt_clk_set_rate,
394 .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
395 .private_data = &gpt2_synth_config,
396};
397
398/* gpt parents */
399static struct pclk_info gpt2_pclk_info[] = {
400 {
401 .pclk = &gpt2_synth_clk,
402 .pclk_val = AUX_CLK_PLL1_VAL,
403 }, {
404 .pclk = &pll3_48m_clk,
405 .pclk_val = AUX_CLK_PLL3_VAL,
406 },
407};
408
409/* gpt parent select structure */
410static struct pclk_sel gpt2_pclk_sel = {
411 .pclk_info = gpt2_pclk_info,
412 .pclk_count = ARRAY_SIZE(gpt2_pclk_info),
413 .pclk_sel_reg = PERIP_CLK_CFG,
414 .pclk_sel_mask = GPT_CLK_MASK,
415};
416
417/* gpt2 timer clock */
418static struct clk gpt2_clk = {
419 .flags = ALWAYS_ENABLED,
420 .pclk_sel = &gpt2_pclk_sel,
421 .pclk_sel_shift = GPT2_CLK_SHIFT,
422 .recalc = &follow_parent,
423};
424
425/* gpt3 synth clk config*/
426static struct gpt_clk_config gpt3_synth_config = {
427 .synth_reg = PRSC3_CLK_CFG,
428 .masks = &gpt_masks,
429};
430
431/* gpt synth clock */
432static struct clk gpt3_synth_clk = {
433 .flags = ALWAYS_ENABLED,
434 .pclk = &pll1_clk,
435 .calc_rate = &gpt_calc_rate,
436 .recalc = &gpt_clk_recalc,
437 .set_rate = &gpt_clk_set_rate,
438 .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
439 .private_data = &gpt3_synth_config,
440};
441
442/* gpt parents */
443static struct pclk_info gpt3_pclk_info[] = {
444 {
445 .pclk = &gpt3_synth_clk,
446 .pclk_val = AUX_CLK_PLL1_VAL,
447 }, {
448 .pclk = &pll3_48m_clk,
449 .pclk_val = AUX_CLK_PLL3_VAL,
450 },
451};
452
453/* gpt parent select structure */
454static struct pclk_sel gpt3_pclk_sel = {
455 .pclk_info = gpt3_pclk_info,
456 .pclk_count = ARRAY_SIZE(gpt3_pclk_info),
457 .pclk_sel_reg = PERIP_CLK_CFG,
458 .pclk_sel_mask = GPT_CLK_MASK,
459};
460
461/* gpt3 timer clock */
462static struct clk gpt3_clk = {
463 .flags = ALWAYS_ENABLED,
464 .pclk_sel = &gpt3_pclk_sel,
465 .pclk_sel_shift = GPT3_CLK_SHIFT,
466 .recalc = &follow_parent,
467};
468
469/* clock derived from pll3 clk */
470/* usbh0 clock */
471static struct clk usbh0_clk = {
472 .pclk = &pll3_48m_clk,
473 .en_reg = PERIP1_CLK_ENB,
474 .en_reg_bit = USBH0_CLK_ENB,
475 .recalc = &follow_parent,
476};
477
478/* usbh1 clock */
479static struct clk usbh1_clk = {
480 .pclk = &pll3_48m_clk,
481 .en_reg = PERIP1_CLK_ENB,
482 .en_reg_bit = USBH1_CLK_ENB,
483 .recalc = &follow_parent,
484};
485
486/* usbd clock */
487static struct clk usbd_clk = {
488 .pclk = &pll3_48m_clk,
489 .en_reg = PERIP1_CLK_ENB,
490 .en_reg_bit = USBD_CLK_ENB,
491 .recalc = &follow_parent,
492};
493
494/* clock derived from ahb clk */
495/* apb masks structure */
496static struct bus_clk_masks apb_masks = {
497 .mask = HCLK_PCLK_RATIO_MASK,
498 .shift = HCLK_PCLK_RATIO_SHIFT,
499};
500
501/* apb configuration structure */
502static struct bus_clk_config apb_config = {
503 .reg = CORE_CLK_CFG,
504 .masks = &apb_masks,
505};
506
507/* apb clock */
508static struct clk apb_clk = {
509 .flags = ALWAYS_ENABLED,
510 .pclk = &ahb_clk,
511 .calc_rate = &bus_calc_rate,
512 .recalc = &bus_clk_recalc,
513 .set_rate = &bus_clk_set_rate,
514 .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
515 .private_data = &apb_config,
516};
517
518/* i2c clock */
519static struct clk i2c_clk = {
520 .pclk = &ahb_clk,
521 .en_reg = PERIP1_CLK_ENB,
522 .en_reg_bit = I2C_CLK_ENB,
523 .recalc = &follow_parent,
524};
525
526/* dma clock */
527static struct clk dma_clk = {
528 .pclk = &ahb_clk,
529 .en_reg = PERIP1_CLK_ENB,
530 .en_reg_bit = DMA_CLK_ENB,
531 .recalc = &follow_parent,
532};
533
534/* jpeg clock */
535static struct clk jpeg_clk = {
536 .pclk = &ahb_clk,
537 .en_reg = PERIP1_CLK_ENB,
538 .en_reg_bit = JPEG_CLK_ENB,
539 .recalc = &follow_parent,
540};
541
542/* gmac clock */
543static struct clk gmac_clk = {
544 .pclk = &ahb_clk,
545 .en_reg = PERIP1_CLK_ENB,
546 .en_reg_bit = GMAC_CLK_ENB,
547 .recalc = &follow_parent,
548};
549
550/* smi clock */
551static struct clk smi_clk = {
552 .pclk = &ahb_clk,
553 .en_reg = PERIP1_CLK_ENB,
554 .en_reg_bit = SMI_CLK_ENB,
555 .recalc = &follow_parent,
556};
557
558/* fsmc clock */
559static struct clk fsmc_clk = {
560 .pclk = &ahb_clk,
561 .en_reg = PERIP1_CLK_ENB,
562 .en_reg_bit = FSMC_CLK_ENB,
563 .recalc = &follow_parent,
564};
565
566/* clock derived from apb clk */
567/* adc clock */
568static struct clk adc_clk = {
569 .pclk = &apb_clk,
570 .en_reg = PERIP1_CLK_ENB,
571 .en_reg_bit = ADC_CLK_ENB,
572 .recalc = &follow_parent,
573};
574
575/* ssp0 clock */
576static struct clk ssp0_clk = {
577 .pclk = &apb_clk,
578 .en_reg = PERIP1_CLK_ENB,
579 .en_reg_bit = SSP0_CLK_ENB,
580 .recalc = &follow_parent,
581};
582
583/* ssp1 clock */
584static struct clk ssp1_clk = {
585 .pclk = &apb_clk,
586 .en_reg = PERIP1_CLK_ENB,
587 .en_reg_bit = SSP1_CLK_ENB,
588 .recalc = &follow_parent,
589};
590
591/* ssp2 clock */
592static struct clk ssp2_clk = {
593 .pclk = &apb_clk,
594 .en_reg = PERIP1_CLK_ENB,
595 .en_reg_bit = SSP2_CLK_ENB,
596 .recalc = &follow_parent,
597};
598
599/* gpio0 ARM subsystem clock */
600static struct clk gpio0_clk = {
601 .flags = ALWAYS_ENABLED,
602 .pclk = &apb_clk,
603 .recalc = &follow_parent,
604};
605
606/* gpio1 clock */
607static struct clk gpio1_clk = {
608 .pclk = &apb_clk,
609 .en_reg = PERIP1_CLK_ENB,
610 .en_reg_bit = GPIO1_CLK_ENB,
611 .recalc = &follow_parent,
612};
613
614/* gpio2 clock */
615static struct clk gpio2_clk = {
616 .pclk = &apb_clk,
617 .en_reg = PERIP1_CLK_ENB,
618 .en_reg_bit = GPIO2_CLK_ENB,
619 .recalc = &follow_parent,
620};
621
622static struct clk dummy_apb_pclk;
623
624/* array of all spear 6xx clock lookups */
625static struct clk_lookup spear_clk_lookups[] = {
626 { .con_id = "apb_pclk", .clk = &dummy_apb_pclk},
627 /* root clks */
628 { .con_id = "osc_32k_clk", .clk = &osc_32k_clk},
629 { .con_id = "osc_30m_clk", .clk = &osc_30m_clk},
630 /* clock derived from 32 KHz os clk */
631 { .dev_id = "rtc-spear", .clk = &rtc_clk},
632 /* clock derived from 30 MHz os clk */
633 { .con_id = "pll1_clk", .clk = &pll1_clk},
634 { .con_id = "pll3_48m_clk", .clk = &pll3_48m_clk},
635 { .dev_id = "wdt", .clk = &wdt_clk},
636 /* clock derived from pll1 clk */
637 { .con_id = "cpu_clk", .clk = &cpu_clk},
638 { .con_id = "ahb_clk", .clk = &ahb_clk},
639 { .con_id = "uart_synth_clk", .clk = &uart_synth_clk},
640 { .con_id = "firda_synth_clk", .clk = &firda_synth_clk},
641 { .con_id = "clcd_synth_clk", .clk = &clcd_synth_clk},
642 { .con_id = "gpt0_synth_clk", .clk = &gpt0_synth_clk},
643 { .con_id = "gpt2_synth_clk", .clk = &gpt2_synth_clk},
644 { .con_id = "gpt3_synth_clk", .clk = &gpt3_synth_clk},
645 { .dev_id = "d0000000.serial", .clk = &uart0_clk},
646 { .dev_id = "d0080000.serial", .clk = &uart1_clk},
647 { .dev_id = "firda", .clk = &firda_clk},
648 { .dev_id = "clcd", .clk = &clcd_clk},
649 { .dev_id = "gpt0", .clk = &gpt0_clk},
650 { .dev_id = "gpt1", .clk = &gpt1_clk},
651 { .dev_id = "gpt2", .clk = &gpt2_clk},
652 { .dev_id = "gpt3", .clk = &gpt3_clk},
653 /* clock derived from pll3 clk */
654 { .dev_id = "designware_udc", .clk = &usbd_clk},
655 { .con_id = "usbh.0_clk", .clk = &usbh0_clk},
656 { .con_id = "usbh.1_clk", .clk = &usbh1_clk},
657 /* clock derived from ahb clk */
658 { .con_id = "apb_clk", .clk = &apb_clk},
659 { .dev_id = "d0200000.i2c", .clk = &i2c_clk},
660 { .dev_id = "dma", .clk = &dma_clk},
661 { .dev_id = "jpeg", .clk = &jpeg_clk},
662 { .dev_id = "gmac", .clk = &gmac_clk},
663 { .dev_id = "smi", .clk = &smi_clk},
664 { .dev_id = "fsmc-nand", .clk = &fsmc_clk},
665 /* clock derived from apb clk */
666 { .dev_id = "adc", .clk = &adc_clk},
667 { .dev_id = "ssp-pl022.0", .clk = &ssp0_clk},
668 { .dev_id = "ssp-pl022.1", .clk = &ssp1_clk},
669 { .dev_id = "ssp-pl022.2", .clk = &ssp2_clk},
670 { .dev_id = "f0100000.gpio", .clk = &gpio0_clk},
671 { .dev_id = "fc980000.gpio", .clk = &gpio1_clk},
672 { .dev_id = "d8100000.gpio", .clk = &gpio2_clk},
673};
674
675void __init spear6xx_clk_init(void)
676{
677 int i;
678
679 for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
680 clk_register(&spear_clk_lookups[i]);
681
682 clk_init();
683}
diff --git a/arch/arm/mach-spear6xx/include/mach/generic.h b/arch/arm/mach-spear6xx/include/mach/generic.h
index 116b99301cf5..65514b159370 100644
--- a/arch/arm/mach-spear6xx/include/mach/generic.h
+++ b/arch/arm/mach-spear6xx/include/mach/generic.h
@@ -15,34 +15,9 @@
15#define __MACH_GENERIC_H 15#define __MACH_GENERIC_H
16 16
17#include <linux/init.h> 17#include <linux/init.h>
18#include <linux/platform_device.h>
19#include <linux/amba/bus.h>
20#include <asm/mach/time.h>
21#include <asm/mach/map.h>
22
23/*
24 * Each GPT has 2 timer channels
25 * Following GPT channels will be used as clock source and clockevent
26 */
27#define SPEAR_GPT0_BASE SPEAR6XX_CPU_TMR_BASE
28#define SPEAR_GPT0_CHAN0_IRQ IRQ_CPU_GPT1_1
29#define SPEAR_GPT0_CHAN1_IRQ IRQ_CPU_GPT1_2
30
31/* Add spear6xx family device structure declarations here */
32extern struct amba_device gpio_device[];
33extern struct amba_device uart_device[];
34extern struct sys_timer spear6xx_timer;
35
36/* Add spear6xx family function declarations here */
37void __init spear_setup_timer(void);
38void __init spear6xx_map_io(void);
39void __init spear6xx_init_irq(void);
40void __init spear6xx_init(void);
41void __init spear600_init(void);
42void __init spear6xx_clk_init(void);
43 18
19void __init spear_setup_of_timer(void);
44void spear_restart(char, const char *); 20void spear_restart(char, const char *);
45 21void __init spear6xx_clk_init(void);
46/* Add spear600 machine device structure declarations here */
47 22
48#endif /* __MACH_GENERIC_H */ 23#endif /* __MACH_GENERIC_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/hardware.h b/arch/arm/mach-spear6xx/include/mach/hardware.h
index 0b3f96ae2848..40a8c178f10d 100644
--- a/arch/arm/mach-spear6xx/include/mach/hardware.h
+++ b/arch/arm/mach-spear6xx/include/mach/hardware.h
@@ -1,23 +1 @@
1/* /* empty */
2 * arch/arm/mach-spear6xx/include/mach/hardware.h
3 *
4 * Hardware definitions for SPEAr6xx machine family
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Rajeev Kumar<rajeev-dlh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __MACH_HARDWARE_H
15#define __MACH_HARDWARE_H
16
17#include <plat/hardware.h>
18#include <mach/spear.h>
19
20/* Vitual to physical translation of statically mapped space */
21#define IO_ADDRESS(x) (x | 0xF0000000)
22
23#endif /* __MACH_HARDWARE_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/irqs.h b/arch/arm/mach-spear6xx/include/mach/irqs.h
index 8f214b03d75d..37a5c411a866 100644
--- a/arch/arm/mach-spear6xx/include/mach/irqs.h
+++ b/arch/arm/mach-spear6xx/include/mach/irqs.h
@@ -16,82 +16,10 @@
16 16
17/* IRQ definitions */ 17/* IRQ definitions */
18/* VIC 1 */ 18/* VIC 1 */
19#define IRQ_INTRCOMM_SW_IRQ 0
20#define IRQ_INTRCOMM_CPU_1 1
21#define IRQ_INTRCOMM_CPU_2 2
22#define IRQ_INTRCOMM_RAS2A11_1 3
23#define IRQ_INTRCOMM_RAS2A11_2 4
24#define IRQ_INTRCOMM_RAS2A12_1 5
25#define IRQ_INTRCOMM_RAS2A12_2 6
26#define IRQ_GEN_RAS_0 7
27#define IRQ_GEN_RAS_1 8
28#define IRQ_GEN_RAS_2 9
29#define IRQ_GEN_RAS_3 10
30#define IRQ_GEN_RAS_4 11
31#define IRQ_GEN_RAS_5 12
32#define IRQ_GEN_RAS_6 13
33#define IRQ_GEN_RAS_7 14
34#define IRQ_GEN_RAS_8 15
35#define IRQ_CPU_GPT1_1 16
36#define IRQ_CPU_GPT1_2 17
37#define IRQ_LOCAL_GPIO 18
38#define IRQ_PLL_UNLOCK 19
39#define IRQ_JPEG 20
40#define IRQ_FSMC 21
41#define IRQ_IRDA 22
42#define IRQ_RESERVED 23
43#define IRQ_UART_0 24
44#define IRQ_UART_1 25
45#define IRQ_SSP_1 26
46#define IRQ_SSP_2 27
47#define IRQ_I2C 28
48#define IRQ_GEN_RAS_9 29
49#define IRQ_GEN_RAS_10 30
50#define IRQ_GEN_RAS_11 31
51
52/* VIC 2 */
53#define IRQ_APPL_GPT1_1 32
54#define IRQ_APPL_GPT1_2 33
55#define IRQ_APPL_GPT2_1 34
56#define IRQ_APPL_GPT2_2 35
57#define IRQ_APPL_GPIO 36
58#define IRQ_APPL_SSP 37
59#define IRQ_APPL_ADC 38
60#define IRQ_APPL_RESERVED 39
61#define IRQ_AHB_EXP_MASTER 40
62#define IRQ_DDR_CONTROLLER 41
63#define IRQ_BASIC_DMA 42
64#define IRQ_BASIC_RESERVED1 43
65#define IRQ_BASIC_SMI 44
66#define IRQ_BASIC_CLCD 45
67#define IRQ_EXP_AHB_1 46
68#define IRQ_EXP_AHB_2 47
69#define IRQ_BASIC_GPT1_1 48
70#define IRQ_BASIC_GPT1_2 49
71#define IRQ_BASIC_RTC 50
72#define IRQ_BASIC_GPIO 51
73#define IRQ_BASIC_WDT 52
74#define IRQ_BASIC_RESERVED 53
75#define IRQ_AHB_EXP_SLAVE 54
76#define IRQ_GMAC_1 55
77#define IRQ_GMAC_2 56
78#define IRQ_USB_DEV 57
79#define IRQ_USB_H_OHCI_0 58
80#define IRQ_USB_H_EHCI_0 59
81#define IRQ_USB_H_OHCI_1 60
82#define IRQ_USB_H_EHCI_1 61
83#define IRQ_EXP_AHB_3 62
84#define IRQ_EXP_AHB_4 63
85
86#define IRQ_VIC_END 64 19#define IRQ_VIC_END 64
87 20
88/* GPIO pins virtual irqs */ 21/* GPIO pins virtual irqs */
89#define SPEAR_GPIO_INT_BASE IRQ_VIC_END 22#define VIRTUAL_IRQS 24
90#define SPEAR_GPIO0_INT_BASE SPEAR_GPIO_INT_BASE 23#define NR_IRQS (IRQ_VIC_END + VIRTUAL_IRQS)
91#define SPEAR_GPIO1_INT_BASE (SPEAR_GPIO0_INT_BASE + 8)
92#define SPEAR_GPIO2_INT_BASE (SPEAR_GPIO1_INT_BASE + 8)
93#define SPEAR_GPIO_INT_END (SPEAR_GPIO2_INT_BASE + 8)
94#define VIRTUAL_IRQS (SPEAR_GPIO_INT_END - IRQ_VIC_END)
95#define NR_IRQS (IRQ_VIC_END + VIRTUAL_IRQS)
96 24
97#endif /* __MACH_IRQS_H */ 25#endif /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/misc_regs.h b/arch/arm/mach-spear6xx/include/mach/misc_regs.h
index 68c20a007b0d..179e45774b3a 100644
--- a/arch/arm/mach-spear6xx/include/mach/misc_regs.h
+++ b/arch/arm/mach-spear6xx/include/mach/misc_regs.h
@@ -14,161 +14,9 @@
14#ifndef __MACH_MISC_REGS_H 14#ifndef __MACH_MISC_REGS_H
15#define __MACH_MISC_REGS_H 15#define __MACH_MISC_REGS_H
16 16
17#include <mach/hardware.h> 17#include <mach/spear.h>
18 18
19#define MISC_BASE IOMEM(VA_SPEAR6XX_ICM3_MISC_REG_BASE) 19#define MISC_BASE IOMEM(VA_SPEAR6XX_ICM3_MISC_REG_BASE)
20
21#define SOC_CFG_CTR (MISC_BASE + 0x000)
22#define DIAG_CFG_CTR (MISC_BASE + 0x004)
23#define PLL1_CTR (MISC_BASE + 0x008)
24#define PLL1_FRQ (MISC_BASE + 0x00C)
25#define PLL1_MOD (MISC_BASE + 0x010)
26#define PLL2_CTR (MISC_BASE + 0x014)
27/* PLL_CTR register masks */
28#define PLL_ENABLE 2
29#define PLL_MODE_SHIFT 4
30#define PLL_MODE_MASK 0x3
31#define PLL_MODE_NORMAL 0
32#define PLL_MODE_FRACTION 1
33#define PLL_MODE_DITH_DSB 2
34#define PLL_MODE_DITH_SSB 3
35
36#define PLL2_FRQ (MISC_BASE + 0x018)
37/* PLL FRQ register masks */
38#define PLL_DIV_N_SHIFT 0
39#define PLL_DIV_N_MASK 0xFF
40#define PLL_DIV_P_SHIFT 8
41#define PLL_DIV_P_MASK 0x7
42#define PLL_NORM_FDBK_M_SHIFT 24
43#define PLL_NORM_FDBK_M_MASK 0xFF
44#define PLL_DITH_FDBK_M_SHIFT 16
45#define PLL_DITH_FDBK_M_MASK 0xFFFF
46
47#define PLL2_MOD (MISC_BASE + 0x01C)
48#define PLL_CLK_CFG (MISC_BASE + 0x020)
49#define CORE_CLK_CFG (MISC_BASE + 0x024)
50/* CORE CLK CFG register masks */
51#define PLL_HCLK_RATIO_SHIFT 10
52#define PLL_HCLK_RATIO_MASK 0x3
53#define HCLK_PCLK_RATIO_SHIFT 8
54#define HCLK_PCLK_RATIO_MASK 0x3
55
56#define PERIP_CLK_CFG (MISC_BASE + 0x028)
57/* PERIP_CLK_CFG register masks */
58#define CLCD_CLK_SHIFT 2
59#define CLCD_CLK_MASK 0x3
60#define UART_CLK_SHIFT 4
61#define UART_CLK_MASK 0x1
62#define FIRDA_CLK_SHIFT 5
63#define FIRDA_CLK_MASK 0x3
64#define GPT0_CLK_SHIFT 8
65#define GPT1_CLK_SHIFT 10
66#define GPT2_CLK_SHIFT 11
67#define GPT3_CLK_SHIFT 12
68#define GPT_CLK_MASK 0x1
69#define AUX_CLK_PLL3_VAL 0
70#define AUX_CLK_PLL1_VAL 1
71
72#define PERIP1_CLK_ENB (MISC_BASE + 0x02C)
73/* PERIP1_CLK_ENB register masks */
74#define UART0_CLK_ENB 3
75#define UART1_CLK_ENB 4
76#define SSP0_CLK_ENB 5
77#define SSP1_CLK_ENB 6
78#define I2C_CLK_ENB 7
79#define JPEG_CLK_ENB 8
80#define FSMC_CLK_ENB 9
81#define FIRDA_CLK_ENB 10
82#define GPT2_CLK_ENB 11
83#define GPT3_CLK_ENB 12
84#define GPIO2_CLK_ENB 13
85#define SSP2_CLK_ENB 14
86#define ADC_CLK_ENB 15
87#define GPT1_CLK_ENB 11
88#define RTC_CLK_ENB 17
89#define GPIO1_CLK_ENB 18
90#define DMA_CLK_ENB 19
91#define SMI_CLK_ENB 21
92#define CLCD_CLK_ENB 22
93#define GMAC_CLK_ENB 23
94#define USBD_CLK_ENB 24
95#define USBH0_CLK_ENB 25
96#define USBH1_CLK_ENB 26
97
98#define SOC_CORE_ID (MISC_BASE + 0x030)
99#define RAS_CLK_ENB (MISC_BASE + 0x034)
100#define PERIP1_SOF_RST (MISC_BASE + 0x038)
101/* PERIP1_SOF_RST register masks */
102#define JPEG_SOF_RST 8
103
104#define SOC_USER_ID (MISC_BASE + 0x03C)
105#define RAS_SOF_RST (MISC_BASE + 0x040)
106#define PRSC1_CLK_CFG (MISC_BASE + 0x044)
107#define PRSC2_CLK_CFG (MISC_BASE + 0x048)
108#define PRSC3_CLK_CFG (MISC_BASE + 0x04C)
109/* gpt synthesizer register masks */
110#define GPT_MSCALE_SHIFT 0
111#define GPT_MSCALE_MASK 0xFFF
112#define GPT_NSCALE_SHIFT 12
113#define GPT_NSCALE_MASK 0xF
114
115#define AMEM_CLK_CFG (MISC_BASE + 0x050)
116#define EXPI_CLK_CFG (MISC_BASE + 0x054)
117#define CLCD_CLK_SYNT (MISC_BASE + 0x05C)
118#define FIRDA_CLK_SYNT (MISC_BASE + 0x060)
119#define UART_CLK_SYNT (MISC_BASE + 0x064)
120#define GMAC_CLK_SYNT (MISC_BASE + 0x068)
121#define RAS1_CLK_SYNT (MISC_BASE + 0x06C)
122#define RAS2_CLK_SYNT (MISC_BASE + 0x070)
123#define RAS3_CLK_SYNT (MISC_BASE + 0x074)
124#define RAS4_CLK_SYNT (MISC_BASE + 0x078)
125/* aux clk synthesiser register masks for irda to ras4 */
126#define AUX_SYNT_ENB 31
127#define AUX_EQ_SEL_SHIFT 30
128#define AUX_EQ_SEL_MASK 1
129#define AUX_EQ1_SEL 0
130#define AUX_EQ2_SEL 1
131#define AUX_XSCALE_SHIFT 16
132#define AUX_XSCALE_MASK 0xFFF
133#define AUX_YSCALE_SHIFT 0
134#define AUX_YSCALE_MASK 0xFFF
135
136#define ICM1_ARB_CFG (MISC_BASE + 0x07C)
137#define ICM2_ARB_CFG (MISC_BASE + 0x080)
138#define ICM3_ARB_CFG (MISC_BASE + 0x084)
139#define ICM4_ARB_CFG (MISC_BASE + 0x088)
140#define ICM5_ARB_CFG (MISC_BASE + 0x08C)
141#define ICM6_ARB_CFG (MISC_BASE + 0x090)
142#define ICM7_ARB_CFG (MISC_BASE + 0x094)
143#define ICM8_ARB_CFG (MISC_BASE + 0x098)
144#define ICM9_ARB_CFG (MISC_BASE + 0x09C)
145#define DMA_CHN_CFG (MISC_BASE + 0x0A0) 20#define DMA_CHN_CFG (MISC_BASE + 0x0A0)
146#define USB2_PHY_CFG (MISC_BASE + 0x0A4)
147#define GMAC_CFG_CTR (MISC_BASE + 0x0A8)
148#define EXPI_CFG_CTR (MISC_BASE + 0x0AC)
149#define PRC1_LOCK_CTR (MISC_BASE + 0x0C0)
150#define PRC2_LOCK_CTR (MISC_BASE + 0x0C4)
151#define PRC3_LOCK_CTR (MISC_BASE + 0x0C8)
152#define PRC4_LOCK_CTR (MISC_BASE + 0x0CC)
153#define PRC1_IRQ_CTR (MISC_BASE + 0x0D0)
154#define PRC2_IRQ_CTR (MISC_BASE + 0x0D4)
155#define PRC3_IRQ_CTR (MISC_BASE + 0x0D8)
156#define PRC4_IRQ_CTR (MISC_BASE + 0x0DC)
157#define PWRDOWN_CFG_CTR (MISC_BASE + 0x0E0)
158#define COMPSSTL_1V8_CFG (MISC_BASE + 0x0E4)
159#define COMPSSTL_2V5_CFG (MISC_BASE + 0x0E8)
160#define COMPCOR_3V3_CFG (MISC_BASE + 0x0EC)
161#define SSTLPAD_CFG_CTR (MISC_BASE + 0x0F0)
162#define BIST1_CFG_CTR (MISC_BASE + 0x0F4)
163#define BIST2_CFG_CTR (MISC_BASE + 0x0F8)
164#define BIST3_CFG_CTR (MISC_BASE + 0x0FC)
165#define BIST4_CFG_CTR (MISC_BASE + 0x100)
166#define BIST5_CFG_CTR (MISC_BASE + 0x104)
167#define BIST1_STS_RES (MISC_BASE + 0x108)
168#define BIST2_STS_RES (MISC_BASE + 0x10C)
169#define BIST3_STS_RES (MISC_BASE + 0x110)
170#define BIST4_STS_RES (MISC_BASE + 0x114)
171#define BIST5_STS_RES (MISC_BASE + 0x118)
172#define SYSERR_CFG_CTR (MISC_BASE + 0x11C)
173 21
174#endif /* __MACH_MISC_REGS_H */ 22#endif /* __MACH_MISC_REGS_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/spear.h b/arch/arm/mach-spear6xx/include/mach/spear.h
index 7fd621532def..cb8ed2f4dc85 100644
--- a/arch/arm/mach-spear6xx/include/mach/spear.h
+++ b/arch/arm/mach-spear6xx/include/mach/spear.h
@@ -15,69 +15,25 @@
15#define __MACH_SPEAR6XX_H 15#define __MACH_SPEAR6XX_H
16 16
17#include <asm/memory.h> 17#include <asm/memory.h>
18#include <mach/spear600.h>
19 18
20#define SPEAR6XX_ML_SDRAM_BASE UL(0x00000000)
21/* ICM1 - Low speed connection */ 19/* ICM1 - Low speed connection */
22#define SPEAR6XX_ICM1_BASE UL(0xD0000000) 20#define SPEAR6XX_ICM1_BASE UL(0xD0000000)
23 21#define VA_SPEAR6XX_ICM1_BASE UL(0xFD000000)
24#define SPEAR6XX_ICM1_UART0_BASE UL(0xD0000000) 22#define SPEAR6XX_ICM1_UART0_BASE UL(0xD0000000)
25#define VA_SPEAR6XX_ICM1_UART0_BASE IO_ADDRESS(SPEAR6XX_ICM1_UART0_BASE) 23#define VA_SPEAR6XX_ICM1_UART0_BASE (VA_SPEAR6XX_ICM1_2_BASE | SPEAR6XX_ICM1_UART0_BASE)
26
27#define SPEAR6XX_ICM1_UART1_BASE UL(0xD0080000)
28#define SPEAR6XX_ICM1_SSP0_BASE UL(0xD0100000)
29#define SPEAR6XX_ICM1_SSP1_BASE UL(0xD0180000)
30#define SPEAR6XX_ICM1_I2C_BASE UL(0xD0200000)
31#define SPEAR6XX_ICM1_JPEG_BASE UL(0xD0800000)
32#define SPEAR6XX_ICM1_IRDA_BASE UL(0xD1000000)
33#define SPEAR6XX_ICM1_FSMC_BASE UL(0xD1800000)
34#define SPEAR6XX_ICM1_NAND_BASE UL(0xD2000000)
35#define SPEAR6XX_ICM1_SRAM_BASE UL(0xD2800000)
36
37/* ICM2 - Application Subsystem */
38#define SPEAR6XX_ICM2_BASE UL(0xD8000000)
39#define SPEAR6XX_ICM2_TMR0_BASE UL(0xD8000000)
40#define SPEAR6XX_ICM2_TMR1_BASE UL(0xD8080000)
41#define SPEAR6XX_ICM2_GPIO_BASE UL(0xD8100000)
42#define SPEAR6XX_ICM2_SSP2_BASE UL(0xD8180000)
43#define SPEAR6XX_ICM2_ADC_BASE UL(0xD8200000)
44 24
45/* ML-1, 2 - Multi Layer CPU Subsystem */ 25/* ML-1, 2 - Multi Layer CPU Subsystem */
46#define SPEAR6XX_ML_CPU_BASE UL(0xF0000000) 26#define SPEAR6XX_ML_CPU_BASE UL(0xF0000000)
47#define SPEAR6XX_CPU_TMR_BASE UL(0xF0000000) 27#define VA_SPEAR6XX_ML_CPU_BASE UL(0xF0000000)
48#define SPEAR6XX_CPU_GPIO_BASE UL(0xF0100000)
49#define SPEAR6XX_CPU_VIC_SEC_BASE UL(0xF1000000)
50#define VA_SPEAR6XX_CPU_VIC_SEC_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_SEC_BASE)
51#define SPEAR6XX_CPU_VIC_PRI_BASE UL(0xF1100000)
52#define VA_SPEAR6XX_CPU_VIC_PRI_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_PRI_BASE)
53 28
54/* ICM3 - Basic Subsystem */ 29/* ICM3 - Basic Subsystem */
55#define SPEAR6XX_ICM3_BASE UL(0xF8000000)
56#define SPEAR6XX_ICM3_SMEM_BASE UL(0xF8000000)
57#define SPEAR6XX_ICM3_SMI_CTRL_BASE UL(0xFC000000) 30#define SPEAR6XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
58#define SPEAR6XX_ICM3_CLCD_BASE UL(0xFC200000) 31#define VA_SPEAR6XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
59#define SPEAR6XX_ICM3_DMA_BASE UL(0xFC400000) 32#define SPEAR6XX_ICM3_DMA_BASE UL(0xFC400000)
60#define SPEAR6XX_ICM3_SDRAM_CTRL_BASE UL(0xFC600000)
61#define SPEAR6XX_ICM3_TMR_BASE UL(0xFC800000)
62#define SPEAR6XX_ICM3_WDT_BASE UL(0xFC880000)
63#define SPEAR6XX_ICM3_RTC_BASE UL(0xFC900000)
64#define SPEAR6XX_ICM3_GPIO_BASE UL(0xFC980000)
65#define SPEAR6XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000) 33#define SPEAR6XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000)
66#define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR6XX_ICM3_SYS_CTRL_BASE) 34#define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE (VA_SPEAR6XX_ICM3_SMI_CTRL_BASE | SPEAR6XX_ICM3_SYS_CTRL_BASE)
67#define SPEAR6XX_ICM3_MISC_REG_BASE UL(0xFCA80000) 35#define SPEAR6XX_ICM3_MISC_REG_BASE UL(0xFCA80000)
68#define VA_SPEAR6XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR6XX_ICM3_MISC_REG_BASE) 36#define VA_SPEAR6XX_ICM3_MISC_REG_BASE (VA_SPEAR6XX_ICM3_SMI_CTRL_BASE | SPEAR6XX_ICM3_MISC_REG_BASE)
69
70/* ICM4 - High Speed Connection */
71#define SPEAR6XX_ICM4_BASE UL(0xE0000000)
72#define SPEAR6XX_ICM4_GMAC_BASE UL(0xE0800000)
73#define SPEAR6XX_ICM4_USBD_FIFO_BASE UL(0xE1000000)
74#define SPEAR6XX_ICM4_USBD_CSR_BASE UL(0xE1100000)
75#define SPEAR6XX_ICM4_USBD_PLDT_BASE UL(0xE1200000)
76#define SPEAR6XX_ICM4_USB_EHCI0_BASE UL(0xE1800000)
77#define SPEAR6XX_ICM4_USB_OHCI0_BASE UL(0xE1900000)
78#define SPEAR6XX_ICM4_USB_EHCI1_BASE UL(0xE2000000)
79#define SPEAR6XX_ICM4_USB_OHCI1_BASE UL(0xE2100000)
80#define SPEAR6XX_ICM4_USB_ARB_BASE UL(0xE2800000)
81 37
82/* Debug uart for linux, will be used for debug and uncompress messages */ 38/* Debug uart for linux, will be used for debug and uncompress messages */
83#define SPEAR_DBG_UART_BASE SPEAR6XX_ICM1_UART0_BASE 39#define SPEAR_DBG_UART_BASE SPEAR6XX_ICM1_UART0_BASE
diff --git a/arch/arm/mach-spear6xx/include/mach/spear600.h b/arch/arm/mach-spear6xx/include/mach/spear600.h
deleted file mode 100644
index c068cc50b0fb..000000000000
--- a/arch/arm/mach-spear6xx/include/mach/spear600.h
+++ /dev/null
@@ -1,21 +0,0 @@
1/*
2 * arch/arm/mach-spear66xx/include/mach/spear600.h
3 *
4 * SPEAr600 Machine specific definition
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifdef CONFIG_MACH_SPEAR600
15
16#ifndef __MACH_SPEAR600_H
17#define __MACH_SPEAR600_H
18
19#endif /* __MACH_SPEAR600_H */
20
21#endif /* CONFIG_MACH_SPEAR600 */
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
index 2ed8b14c82c8..2e2e3596583e 100644
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear6xx/spear6xx.c
@@ -13,41 +13,404 @@
13 * warranty of any kind, whether express or implied. 13 * warranty of any kind, whether express or implied.
14 */ 14 */
15 15
16#include <linux/amba/pl08x.h>
17#include <linux/clk.h>
18#include <linux/err.h>
16#include <linux/of.h> 19#include <linux/of.h>
17#include <linux/of_address.h> 20#include <linux/of_address.h>
18#include <linux/of_irq.h> 21#include <linux/of_irq.h>
19#include <linux/of_platform.h> 22#include <linux/of_platform.h>
23#include <asm/hardware/pl080.h>
20#include <asm/hardware/vic.h> 24#include <asm/hardware/vic.h>
21#include <asm/mach/arch.h> 25#include <asm/mach/arch.h>
26#include <asm/mach/time.h>
27#include <asm/mach/map.h>
28#include <plat/pl080.h>
22#include <mach/generic.h> 29#include <mach/generic.h>
23#include <mach/hardware.h> 30#include <mach/spear.h>
24 31
25/* Following will create static virtual/physical mappings */ 32/* dmac device registration */
26static struct map_desc spear6xx_io_desc[] __initdata = { 33static struct pl08x_channel_data spear600_dma_info[] = {
27 { 34 {
28 .virtual = VA_SPEAR6XX_ICM1_UART0_BASE, 35 .bus_id = "ssp1_rx",
29 .pfn = __phys_to_pfn(SPEAR6XX_ICM1_UART0_BASE), 36 .min_signal = 0,
30 .length = SZ_4K, 37 .max_signal = 0,
31 .type = MT_DEVICE 38 .muxval = 0,
39 .cctl = 0,
40 .periph_buses = PL08X_AHB1,
32 }, { 41 }, {
33 .virtual = VA_SPEAR6XX_CPU_VIC_PRI_BASE, 42 .bus_id = "ssp1_tx",
34 .pfn = __phys_to_pfn(SPEAR6XX_CPU_VIC_PRI_BASE), 43 .min_signal = 1,
35 .length = SZ_4K, 44 .max_signal = 1,
36 .type = MT_DEVICE 45 .muxval = 0,
46 .cctl = 0,
47 .periph_buses = PL08X_AHB1,
37 }, { 48 }, {
38 .virtual = VA_SPEAR6XX_CPU_VIC_SEC_BASE, 49 .bus_id = "uart0_rx",
39 .pfn = __phys_to_pfn(SPEAR6XX_CPU_VIC_SEC_BASE), 50 .min_signal = 2,
40 .length = SZ_4K, 51 .max_signal = 2,
41 .type = MT_DEVICE 52 .muxval = 0,
53 .cctl = 0,
54 .periph_buses = PL08X_AHB1,
55 }, {
56 .bus_id = "uart0_tx",
57 .min_signal = 3,
58 .max_signal = 3,
59 .muxval = 0,
60 .cctl = 0,
61 .periph_buses = PL08X_AHB1,
62 }, {
63 .bus_id = "uart1_rx",
64 .min_signal = 4,
65 .max_signal = 4,
66 .muxval = 0,
67 .cctl = 0,
68 .periph_buses = PL08X_AHB1,
69 }, {
70 .bus_id = "uart1_tx",
71 .min_signal = 5,
72 .max_signal = 5,
73 .muxval = 0,
74 .cctl = 0,
75 .periph_buses = PL08X_AHB1,
76 }, {
77 .bus_id = "ssp2_rx",
78 .min_signal = 6,
79 .max_signal = 6,
80 .muxval = 0,
81 .cctl = 0,
82 .periph_buses = PL08X_AHB2,
83 }, {
84 .bus_id = "ssp2_tx",
85 .min_signal = 7,
86 .max_signal = 7,
87 .muxval = 0,
88 .cctl = 0,
89 .periph_buses = PL08X_AHB2,
90 }, {
91 .bus_id = "ssp0_rx",
92 .min_signal = 8,
93 .max_signal = 8,
94 .muxval = 0,
95 .cctl = 0,
96 .periph_buses = PL08X_AHB1,
97 }, {
98 .bus_id = "ssp0_tx",
99 .min_signal = 9,
100 .max_signal = 9,
101 .muxval = 0,
102 .cctl = 0,
103 .periph_buses = PL08X_AHB1,
104 }, {
105 .bus_id = "i2c_rx",
106 .min_signal = 10,
107 .max_signal = 10,
108 .muxval = 0,
109 .cctl = 0,
110 .periph_buses = PL08X_AHB1,
111 }, {
112 .bus_id = "i2c_tx",
113 .min_signal = 11,
114 .max_signal = 11,
115 .muxval = 0,
116 .cctl = 0,
117 .periph_buses = PL08X_AHB1,
118 }, {
119 .bus_id = "irda",
120 .min_signal = 12,
121 .max_signal = 12,
122 .muxval = 0,
123 .cctl = 0,
124 .periph_buses = PL08X_AHB1,
125 }, {
126 .bus_id = "adc",
127 .min_signal = 13,
128 .max_signal = 13,
129 .muxval = 0,
130 .cctl = 0,
131 .periph_buses = PL08X_AHB2,
132 }, {
133 .bus_id = "to_jpeg",
134 .min_signal = 14,
135 .max_signal = 14,
136 .muxval = 0,
137 .cctl = 0,
138 .periph_buses = PL08X_AHB1,
139 }, {
140 .bus_id = "from_jpeg",
141 .min_signal = 15,
142 .max_signal = 15,
143 .muxval = 0,
144 .cctl = 0,
145 .periph_buses = PL08X_AHB1,
146 }, {
147 .bus_id = "ras0_rx",
148 .min_signal = 0,
149 .max_signal = 0,
150 .muxval = 1,
151 .cctl = 0,
152 .periph_buses = PL08X_AHB1,
153 }, {
154 .bus_id = "ras0_tx",
155 .min_signal = 1,
156 .max_signal = 1,
157 .muxval = 1,
158 .cctl = 0,
159 .periph_buses = PL08X_AHB1,
160 }, {
161 .bus_id = "ras1_rx",
162 .min_signal = 2,
163 .max_signal = 2,
164 .muxval = 1,
165 .cctl = 0,
166 .periph_buses = PL08X_AHB1,
167 }, {
168 .bus_id = "ras1_tx",
169 .min_signal = 3,
170 .max_signal = 3,
171 .muxval = 1,
172 .cctl = 0,
173 .periph_buses = PL08X_AHB1,
174 }, {
175 .bus_id = "ras2_rx",
176 .min_signal = 4,
177 .max_signal = 4,
178 .muxval = 1,
179 .cctl = 0,
180 .periph_buses = PL08X_AHB1,
181 }, {
182 .bus_id = "ras2_tx",
183 .min_signal = 5,
184 .max_signal = 5,
185 .muxval = 1,
186 .cctl = 0,
187 .periph_buses = PL08X_AHB1,
188 }, {
189 .bus_id = "ras3_rx",
190 .min_signal = 6,
191 .max_signal = 6,
192 .muxval = 1,
193 .cctl = 0,
194 .periph_buses = PL08X_AHB1,
195 }, {
196 .bus_id = "ras3_tx",
197 .min_signal = 7,
198 .max_signal = 7,
199 .muxval = 1,
200 .cctl = 0,
201 .periph_buses = PL08X_AHB1,
202 }, {
203 .bus_id = "ras4_rx",
204 .min_signal = 8,
205 .max_signal = 8,
206 .muxval = 1,
207 .cctl = 0,
208 .periph_buses = PL08X_AHB1,
209 }, {
210 .bus_id = "ras4_tx",
211 .min_signal = 9,
212 .max_signal = 9,
213 .muxval = 1,
214 .cctl = 0,
215 .periph_buses = PL08X_AHB1,
216 }, {
217 .bus_id = "ras5_rx",
218 .min_signal = 10,
219 .max_signal = 10,
220 .muxval = 1,
221 .cctl = 0,
222 .periph_buses = PL08X_AHB1,
223 }, {
224 .bus_id = "ras5_tx",
225 .min_signal = 11,
226 .max_signal = 11,
227 .muxval = 1,
228 .cctl = 0,
229 .periph_buses = PL08X_AHB1,
230 }, {
231 .bus_id = "ras6_rx",
232 .min_signal = 12,
233 .max_signal = 12,
234 .muxval = 1,
235 .cctl = 0,
236 .periph_buses = PL08X_AHB1,
237 }, {
238 .bus_id = "ras6_tx",
239 .min_signal = 13,
240 .max_signal = 13,
241 .muxval = 1,
242 .cctl = 0,
243 .periph_buses = PL08X_AHB1,
244 }, {
245 .bus_id = "ras7_rx",
246 .min_signal = 14,
247 .max_signal = 14,
248 .muxval = 1,
249 .cctl = 0,
250 .periph_buses = PL08X_AHB1,
251 }, {
252 .bus_id = "ras7_tx",
253 .min_signal = 15,
254 .max_signal = 15,
255 .muxval = 1,
256 .cctl = 0,
257 .periph_buses = PL08X_AHB1,
42 }, { 258 }, {
43 .virtual = VA_SPEAR6XX_ICM3_SYS_CTRL_BASE, 259 .bus_id = "ext0_rx",
44 .pfn = __phys_to_pfn(SPEAR6XX_ICM3_SYS_CTRL_BASE), 260 .min_signal = 0,
45 .length = SZ_4K, 261 .max_signal = 0,
262 .muxval = 2,
263 .cctl = 0,
264 .periph_buses = PL08X_AHB2,
265 }, {
266 .bus_id = "ext0_tx",
267 .min_signal = 1,
268 .max_signal = 1,
269 .muxval = 2,
270 .cctl = 0,
271 .periph_buses = PL08X_AHB2,
272 }, {
273 .bus_id = "ext1_rx",
274 .min_signal = 2,
275 .max_signal = 2,
276 .muxval = 2,
277 .cctl = 0,
278 .periph_buses = PL08X_AHB2,
279 }, {
280 .bus_id = "ext1_tx",
281 .min_signal = 3,
282 .max_signal = 3,
283 .muxval = 2,
284 .cctl = 0,
285 .periph_buses = PL08X_AHB2,
286 }, {
287 .bus_id = "ext2_rx",
288 .min_signal = 4,
289 .max_signal = 4,
290 .muxval = 2,
291 .cctl = 0,
292 .periph_buses = PL08X_AHB2,
293 }, {
294 .bus_id = "ext2_tx",
295 .min_signal = 5,
296 .max_signal = 5,
297 .muxval = 2,
298 .cctl = 0,
299 .periph_buses = PL08X_AHB2,
300 }, {
301 .bus_id = "ext3_rx",
302 .min_signal = 6,
303 .max_signal = 6,
304 .muxval = 2,
305 .cctl = 0,
306 .periph_buses = PL08X_AHB2,
307 }, {
308 .bus_id = "ext3_tx",
309 .min_signal = 7,
310 .max_signal = 7,
311 .muxval = 2,
312 .cctl = 0,
313 .periph_buses = PL08X_AHB2,
314 }, {
315 .bus_id = "ext4_rx",
316 .min_signal = 8,
317 .max_signal = 8,
318 .muxval = 2,
319 .cctl = 0,
320 .periph_buses = PL08X_AHB2,
321 }, {
322 .bus_id = "ext4_tx",
323 .min_signal = 9,
324 .max_signal = 9,
325 .muxval = 2,
326 .cctl = 0,
327 .periph_buses = PL08X_AHB2,
328 }, {
329 .bus_id = "ext5_rx",
330 .min_signal = 10,
331 .max_signal = 10,
332 .muxval = 2,
333 .cctl = 0,
334 .periph_buses = PL08X_AHB2,
335 }, {
336 .bus_id = "ext5_tx",
337 .min_signal = 11,
338 .max_signal = 11,
339 .muxval = 2,
340 .cctl = 0,
341 .periph_buses = PL08X_AHB2,
342 }, {
343 .bus_id = "ext6_rx",
344 .min_signal = 12,
345 .max_signal = 12,
346 .muxval = 2,
347 .cctl = 0,
348 .periph_buses = PL08X_AHB2,
349 }, {
350 .bus_id = "ext6_tx",
351 .min_signal = 13,
352 .max_signal = 13,
353 .muxval = 2,
354 .cctl = 0,
355 .periph_buses = PL08X_AHB2,
356 }, {
357 .bus_id = "ext7_rx",
358 .min_signal = 14,
359 .max_signal = 14,
360 .muxval = 2,
361 .cctl = 0,
362 .periph_buses = PL08X_AHB2,
363 }, {
364 .bus_id = "ext7_tx",
365 .min_signal = 15,
366 .max_signal = 15,
367 .muxval = 2,
368 .cctl = 0,
369 .periph_buses = PL08X_AHB2,
370 },
371};
372
373struct pl08x_platform_data pl080_plat_data = {
374 .memcpy_channel = {
375 .bus_id = "memcpy",
376 .cctl = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
377 PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
378 PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
379 PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
380 PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \
381 PL080_CONTROL_PROT_SYS),
382 },
383 .lli_buses = PL08X_AHB1,
384 .mem_buses = PL08X_AHB1,
385 .get_signal = pl080_get_signal,
386 .put_signal = pl080_put_signal,
387 .slave_channels = spear600_dma_info,
388 .num_slave_channels = ARRAY_SIZE(spear600_dma_info),
389};
390
391/*
392 * Following will create 16MB static virtual/physical mappings
393 * PHYSICAL VIRTUAL
394 * 0xF0000000 0xF0000000
395 * 0xF1000000 0xF1000000
396 * 0xD0000000 0xFD000000
397 * 0xFC000000 0xFC000000
398 */
399struct map_desc spear6xx_io_desc[] __initdata = {
400 {
401 .virtual = VA_SPEAR6XX_ML_CPU_BASE,
402 .pfn = __phys_to_pfn(SPEAR6XX_ML_CPU_BASE),
403 .length = 2 * SZ_16M,
404 .type = MT_DEVICE
405 }, {
406 .virtual = VA_SPEAR6XX_ICM1_BASE,
407 .pfn = __phys_to_pfn(SPEAR6XX_ICM1_BASE),
408 .length = SZ_16M,
46 .type = MT_DEVICE 409 .type = MT_DEVICE
47 }, { 410 }, {
48 .virtual = VA_SPEAR6XX_ICM3_MISC_REG_BASE, 411 .virtual = VA_SPEAR6XX_ICM3_SMI_CTRL_BASE,
49 .pfn = __phys_to_pfn(SPEAR6XX_ICM3_MISC_REG_BASE), 412 .pfn = __phys_to_pfn(SPEAR6XX_ICM3_SMI_CTRL_BASE),
50 .length = SZ_4K, 413 .length = SZ_16M,
51 .type = MT_DEVICE 414 .type = MT_DEVICE
52 }, 415 },
53}; 416};
@@ -56,9 +419,6 @@ static struct map_desc spear6xx_io_desc[] __initdata = {
56void __init spear6xx_map_io(void) 419void __init spear6xx_map_io(void)
57{ 420{
58 iotable_init(spear6xx_io_desc, ARRAY_SIZE(spear6xx_io_desc)); 421 iotable_init(spear6xx_io_desc, ARRAY_SIZE(spear6xx_io_desc));
59
60 /* This will initialize clock framework */
61 spear6xx_clk_init();
62} 422}
63 423
64static void __init spear6xx_timer_init(void) 424static void __init spear6xx_timer_init(void)
@@ -66,6 +426,8 @@ static void __init spear6xx_timer_init(void)
66 char pclk_name[] = "pll3_48m_clk"; 426 char pclk_name[] = "pll3_48m_clk";
67 struct clk *gpt_clk, *pclk; 427 struct clk *gpt_clk, *pclk;
68 428
429 spear6xx_clk_init();
430
69 /* get the system timer clock */ 431 /* get the system timer clock */
70 gpt_clk = clk_get_sys("gpt0", NULL); 432 gpt_clk = clk_get_sys("gpt0", NULL);
71 if (IS_ERR(gpt_clk)) { 433 if (IS_ERR(gpt_clk)) {
@@ -85,16 +447,24 @@ static void __init spear6xx_timer_init(void)
85 clk_put(gpt_clk); 447 clk_put(gpt_clk);
86 clk_put(pclk); 448 clk_put(pclk);
87 449
88 spear_setup_timer(); 450 spear_setup_of_timer();
89} 451}
90 452
91struct sys_timer spear6xx_timer = { 453struct sys_timer spear6xx_timer = {
92 .init = spear6xx_timer_init, 454 .init = spear6xx_timer_init,
93}; 455};
94 456
457/* Add auxdata to pass platform data */
458struct of_dev_auxdata spear6xx_auxdata_lookup[] __initdata = {
459 OF_DEV_AUXDATA("arm,pl080", SPEAR6XX_ICM3_DMA_BASE, NULL,
460 &pl080_plat_data),
461 {}
462};
463
95static void __init spear600_dt_init(void) 464static void __init spear600_dt_init(void)
96{ 465{
97 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 466 of_platform_populate(NULL, of_default_bus_match_table,
467 spear6xx_auxdata_lookup, NULL);
98} 468}
99 469
100static const char *spear600_dt_board_compat[] = { 470static const char *spear600_dt_board_compat[] = {
diff --git a/arch/arm/plat-spear/Kconfig b/arch/arm/plat-spear/Kconfig
index 1bb3dbce8810..4404f82d5979 100644
--- a/arch/arm/plat-spear/Kconfig
+++ b/arch/arm/plat-spear/Kconfig
@@ -8,10 +8,23 @@ choice
8 prompt "ST SPEAr Family" 8 prompt "ST SPEAr Family"
9 default ARCH_SPEAR3XX 9 default ARCH_SPEAR3XX
10 10
11config ARCH_SPEAR13XX
12 bool "ST SPEAr13xx with Device Tree"
13 select ARM_GIC
14 select CPU_V7
15 select USE_OF
16 select HAVE_SMP
17 select MIGHT_HAVE_CACHE_L2X0
18 select PINCTRL
19 help
20 Supports for ARM's SPEAR13XX family
21
11config ARCH_SPEAR3XX 22config ARCH_SPEAR3XX
12 bool "SPEAr3XX" 23 bool "ST SPEAr3xx with Device Tree"
13 select ARM_VIC 24 select ARM_VIC
14 select CPU_ARM926T 25 select CPU_ARM926T
26 select USE_OF
27 select PINCTRL
15 help 28 help
16 Supports for ARM's SPEAR3XX family 29 Supports for ARM's SPEAR3XX family
17 30
@@ -25,6 +38,7 @@ config ARCH_SPEAR6XX
25endchoice 38endchoice
26 39
27# Adding SPEAr machine specific configuration files 40# Adding SPEAr machine specific configuration files
41source "arch/arm/mach-spear13xx/Kconfig"
28source "arch/arm/mach-spear3xx/Kconfig" 42source "arch/arm/mach-spear3xx/Kconfig"
29source "arch/arm/mach-spear6xx/Kconfig" 43source "arch/arm/mach-spear6xx/Kconfig"
30 44
diff --git a/arch/arm/plat-spear/Makefile b/arch/arm/plat-spear/Makefile
index e0f2e5b9530c..2607bd05c525 100644
--- a/arch/arm/plat-spear/Makefile
+++ b/arch/arm/plat-spear/Makefile
@@ -3,6 +3,7 @@
3# 3#
4 4
5# Common support 5# Common support
6obj-y := clock.o restart.o time.o 6obj-y := restart.o time.o
7 7
8obj-$(CONFIG_ARCH_SPEAR3XX) += shirq.o padmux.o 8obj-$(CONFIG_ARCH_SPEAR3XX) += pl080.o shirq.o
9obj-$(CONFIG_ARCH_SPEAR6XX) += pl080.o
diff --git a/arch/arm/plat-spear/clock.c b/arch/arm/plat-spear/clock.c
deleted file mode 100644
index 67dd00381ea6..000000000000
--- a/arch/arm/plat-spear/clock.c
+++ /dev/null
@@ -1,1005 +0,0 @@
1/*
2 * arch/arm/plat-spear/clock.c
3 *
4 * Clock framework for SPEAr platform
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <linux/bug.h>
15#include <linux/clk.h>
16#include <linux/debugfs.h>
17#include <linux/err.h>
18#include <linux/io.h>
19#include <linux/list.h>
20#include <linux/module.h>
21#include <linux/spinlock.h>
22#include <plat/clock.h>
23
24static DEFINE_SPINLOCK(clocks_lock);
25static LIST_HEAD(root_clks);
26#ifdef CONFIG_DEBUG_FS
27static LIST_HEAD(clocks);
28#endif
29
30static void propagate_rate(struct clk *, int on_init);
31#ifdef CONFIG_DEBUG_FS
32static int clk_debugfs_reparent(struct clk *);
33#endif
34
35static int generic_clk_enable(struct clk *clk)
36{
37 unsigned int val;
38
39 if (!clk->en_reg)
40 return -EFAULT;
41
42 val = readl(clk->en_reg);
43 if (unlikely(clk->flags & RESET_TO_ENABLE))
44 val &= ~(1 << clk->en_reg_bit);
45 else
46 val |= 1 << clk->en_reg_bit;
47
48 writel(val, clk->en_reg);
49
50 return 0;
51}
52
53static void generic_clk_disable(struct clk *clk)
54{
55 unsigned int val;
56
57 if (!clk->en_reg)
58 return;
59
60 val = readl(clk->en_reg);
61 if (unlikely(clk->flags & RESET_TO_ENABLE))
62 val |= 1 << clk->en_reg_bit;
63 else
64 val &= ~(1 << clk->en_reg_bit);
65
66 writel(val, clk->en_reg);
67}
68
69/* generic clk ops */
70static struct clkops generic_clkops = {
71 .enable = generic_clk_enable,
72 .disable = generic_clk_disable,
73};
74
75/* returns current programmed clocks clock info structure */
76static struct pclk_info *pclk_info_get(struct clk *clk)
77{
78 unsigned int val, i;
79 struct pclk_info *info = NULL;
80
81 val = (readl(clk->pclk_sel->pclk_sel_reg) >> clk->pclk_sel_shift)
82 & clk->pclk_sel->pclk_sel_mask;
83
84 for (i = 0; i < clk->pclk_sel->pclk_count; i++) {
85 if (clk->pclk_sel->pclk_info[i].pclk_val == val)
86 info = &clk->pclk_sel->pclk_info[i];
87 }
88
89 return info;
90}
91
92/*
93 * Set Update pclk, and pclk_info of clk and add clock sibling node to current
94 * parents children list
95 */
96static void clk_reparent(struct clk *clk, struct pclk_info *pclk_info)
97{
98 unsigned long flags;
99
100 spin_lock_irqsave(&clocks_lock, flags);
101 list_del(&clk->sibling);
102 list_add(&clk->sibling, &pclk_info->pclk->children);
103
104 clk->pclk = pclk_info->pclk;
105 spin_unlock_irqrestore(&clocks_lock, flags);
106
107#ifdef CONFIG_DEBUG_FS
108 clk_debugfs_reparent(clk);
109#endif
110}
111
112static void do_clk_disable(struct clk *clk)
113{
114 if (!clk)
115 return;
116
117 if (!clk->usage_count) {
118 WARN_ON(1);
119 return;
120 }
121
122 clk->usage_count--;
123
124 if (clk->usage_count == 0) {
125 /*
126 * Surely, there are no active childrens or direct users
127 * of this clock
128 */
129 if (clk->pclk)
130 do_clk_disable(clk->pclk);
131
132 if (clk->ops && clk->ops->disable)
133 clk->ops->disable(clk);
134 }
135}
136
137static int do_clk_enable(struct clk *clk)
138{
139 int ret = 0;
140
141 if (!clk)
142 return -EFAULT;
143
144 if (clk->usage_count == 0) {
145 if (clk->pclk) {
146 ret = do_clk_enable(clk->pclk);
147 if (ret)
148 goto err;
149 }
150 if (clk->ops && clk->ops->enable) {
151 ret = clk->ops->enable(clk);
152 if (ret) {
153 if (clk->pclk)
154 do_clk_disable(clk->pclk);
155 goto err;
156 }
157 }
158 /*
159 * Since the clock is going to be used for the first
160 * time please reclac
161 */
162 if (clk->recalc) {
163 ret = clk->recalc(clk);
164 if (ret)
165 goto err;
166 }
167 }
168 clk->usage_count++;
169err:
170 return ret;
171}
172
173/*
174 * clk_enable - inform the system when the clock source should be running.
175 * @clk: clock source
176 *
177 * If the clock can not be enabled/disabled, this should return success.
178 *
179 * Returns success (0) or negative errno.
180 */
181int clk_enable(struct clk *clk)
182{
183 unsigned long flags;
184 int ret = 0;
185
186 spin_lock_irqsave(&clocks_lock, flags);
187 ret = do_clk_enable(clk);
188 spin_unlock_irqrestore(&clocks_lock, flags);
189 return ret;
190}
191EXPORT_SYMBOL(clk_enable);
192
193/*
194 * clk_disable - inform the system when the clock source is no longer required.
195 * @clk: clock source
196 *
197 * Inform the system that a clock source is no longer required by
198 * a driver and may be shut down.
199 *
200 * Implementation detail: if the clock source is shared between
201 * multiple drivers, clk_enable() calls must be balanced by the
202 * same number of clk_disable() calls for the clock source to be
203 * disabled.
204 */
205void clk_disable(struct clk *clk)
206{
207 unsigned long flags;
208
209 spin_lock_irqsave(&clocks_lock, flags);
210 do_clk_disable(clk);
211 spin_unlock_irqrestore(&clocks_lock, flags);
212}
213EXPORT_SYMBOL(clk_disable);
214
215/**
216 * clk_get_rate - obtain the current clock rate (in Hz) for a clock source.
217 * This is only valid once the clock source has been enabled.
218 * @clk: clock source
219 */
220unsigned long clk_get_rate(struct clk *clk)
221{
222 unsigned long flags, rate;
223
224 spin_lock_irqsave(&clocks_lock, flags);
225 rate = clk->rate;
226 spin_unlock_irqrestore(&clocks_lock, flags);
227
228 return rate;
229}
230EXPORT_SYMBOL(clk_get_rate);
231
232/**
233 * clk_set_parent - set the parent clock source for this clock
234 * @clk: clock source
235 * @parent: parent clock source
236 *
237 * Returns success (0) or negative errno.
238 */
239int clk_set_parent(struct clk *clk, struct clk *parent)
240{
241 int i, found = 0, val = 0;
242 unsigned long flags;
243
244 if (!clk || !parent)
245 return -EFAULT;
246 if (clk->pclk == parent)
247 return 0;
248 if (!clk->pclk_sel)
249 return -EPERM;
250
251 /* check if requested parent is in clk parent list */
252 for (i = 0; i < clk->pclk_sel->pclk_count; i++) {
253 if (clk->pclk_sel->pclk_info[i].pclk == parent) {
254 found = 1;
255 break;
256 }
257 }
258
259 if (!found)
260 return -EINVAL;
261
262 spin_lock_irqsave(&clocks_lock, flags);
263 /* reflect parent change in hardware */
264 val = readl(clk->pclk_sel->pclk_sel_reg);
265 val &= ~(clk->pclk_sel->pclk_sel_mask << clk->pclk_sel_shift);
266 val |= clk->pclk_sel->pclk_info[i].pclk_val << clk->pclk_sel_shift;
267 writel(val, clk->pclk_sel->pclk_sel_reg);
268 spin_unlock_irqrestore(&clocks_lock, flags);
269
270 /* reflect parent change in software */
271 clk_reparent(clk, &clk->pclk_sel->pclk_info[i]);
272
273 propagate_rate(clk, 0);
274 return 0;
275}
276EXPORT_SYMBOL(clk_set_parent);
277
278/**
279 * clk_set_rate - set the clock rate for a clock source
280 * @clk: clock source
281 * @rate: desired clock rate in Hz
282 *
283 * Returns success (0) or negative errno.
284 */
285int clk_set_rate(struct clk *clk, unsigned long rate)
286{
287 unsigned long flags;
288 int ret = -EINVAL;
289
290 if (!clk || !rate)
291 return -EFAULT;
292
293 if (clk->set_rate) {
294 spin_lock_irqsave(&clocks_lock, flags);
295 ret = clk->set_rate(clk, rate);
296 if (!ret)
297 /* if successful -> propagate */
298 propagate_rate(clk, 0);
299 spin_unlock_irqrestore(&clocks_lock, flags);
300 } else if (clk->pclk) {
301 u32 mult = clk->div_factor ? clk->div_factor : 1;
302 ret = clk_set_rate(clk->pclk, mult * rate);
303 }
304
305 return ret;
306}
307EXPORT_SYMBOL(clk_set_rate);
308
309/* registers clock in platform clock framework */
310void clk_register(struct clk_lookup *cl)
311{
312 struct clk *clk;
313 unsigned long flags;
314
315 if (!cl || !cl->clk)
316 return;
317 clk = cl->clk;
318
319 spin_lock_irqsave(&clocks_lock, flags);
320
321 INIT_LIST_HEAD(&clk->children);
322 if (clk->flags & ALWAYS_ENABLED)
323 clk->ops = NULL;
324 else if (!clk->ops)
325 clk->ops = &generic_clkops;
326
327 /* root clock don't have any parents */
328 if (!clk->pclk && !clk->pclk_sel) {
329 list_add(&clk->sibling, &root_clks);
330 } else if (clk->pclk && !clk->pclk_sel) {
331 /* add clocks with only one parent to parent's children list */
332 list_add(&clk->sibling, &clk->pclk->children);
333 } else {
334 /* clocks with more than one parent */
335 struct pclk_info *pclk_info;
336
337 pclk_info = pclk_info_get(clk);
338 if (!pclk_info) {
339 pr_err("CLKDEV: invalid pclk info of clk with"
340 " %s dev_id and %s con_id\n",
341 cl->dev_id, cl->con_id);
342 } else {
343 clk->pclk = pclk_info->pclk;
344 list_add(&clk->sibling, &pclk_info->pclk->children);
345 }
346 }
347
348 spin_unlock_irqrestore(&clocks_lock, flags);
349
350 /* debugfs specific */
351#ifdef CONFIG_DEBUG_FS
352 list_add(&clk->node, &clocks);
353 clk->cl = cl;
354#endif
355
356 /* add clock to arm clockdev framework */
357 clkdev_add(cl);
358}
359
360/**
361 * propagate_rate - recalculate and propagate all clocks to children
362 * @pclk: parent clock required to be propogated
363 * @on_init: flag for enabling clocks which are ENABLED_ON_INIT.
364 *
365 * Recalculates all children clocks
366 */
367void propagate_rate(struct clk *pclk, int on_init)
368{
369 struct clk *clk, *_temp;
370 int ret = 0;
371
372 list_for_each_entry_safe(clk, _temp, &pclk->children, sibling) {
373 if (clk->recalc) {
374 ret = clk->recalc(clk);
375 /*
376 * recalc will return error if clk out is not programmed
377 * In this case configure default rate.
378 */
379 if (ret && clk->set_rate)
380 clk->set_rate(clk, 0);
381 }
382 propagate_rate(clk, on_init);
383
384 if (!on_init)
385 continue;
386
387 /* Enable clks enabled on init, in software view */
388 if (clk->flags & ENABLED_ON_INIT)
389 do_clk_enable(clk);
390 }
391}
392
393/**
394 * round_rate_index - return closest programmable rate index in rate_config tbl
395 * @clk: ptr to clock structure
396 * @drate: desired rate
397 * @rate: final rate will be returned in this variable only.
398 *
399 * Finds index in rate_config for highest clk rate which is less than
400 * requested rate. If there is no clk rate lesser than requested rate then
401 * -EINVAL is returned. This routine assumes that rate_config is written
402 * in incrementing order of clk rates.
403 * If drate passed is zero then default rate is programmed.
404 */
405static int
406round_rate_index(struct clk *clk, unsigned long drate, unsigned long *rate)
407{
408 unsigned long tmp = 0, prev_rate = 0;
409 int index;
410
411 if (!clk->calc_rate)
412 return -EFAULT;
413
414 if (!drate)
415 return -EINVAL;
416
417 /*
418 * This loops ends on two conditions:
419 * - as soon as clk is found with rate greater than requested rate.
420 * - if all clks in rate_config are smaller than requested rate.
421 */
422 for (index = 0; index < clk->rate_config.count; index++) {
423 prev_rate = tmp;
424 tmp = clk->calc_rate(clk, index);
425 if (drate < tmp) {
426 index--;
427 break;
428 }
429 }
430 /* return if can't find suitable clock */
431 if (index < 0) {
432 index = -EINVAL;
433 *rate = 0;
434 } else if (index == clk->rate_config.count) {
435 /* program with highest clk rate possible */
436 index = clk->rate_config.count - 1;
437 *rate = tmp;
438 } else
439 *rate = prev_rate;
440
441 return index;
442}
443
444/**
445 * clk_round_rate - adjust a rate to the exact rate a clock can provide
446 * @clk: clock source
447 * @rate: desired clock rate in Hz
448 *
449 * Returns rounded clock rate in Hz, or negative errno.
450 */
451long clk_round_rate(struct clk *clk, unsigned long drate)
452{
453 long rate = 0;
454 int index;
455
456 /*
457 * propagate call to parent who supports calc_rate. Similar approach is
458 * used in clk_set_rate.
459 */
460 if (!clk->calc_rate) {
461 u32 mult;
462 if (!clk->pclk)
463 return clk->rate;
464
465 mult = clk->div_factor ? clk->div_factor : 1;
466 return clk_round_rate(clk->pclk, mult * drate) / mult;
467 }
468
469 index = round_rate_index(clk, drate, &rate);
470 if (index >= 0)
471 return rate;
472 else
473 return index;
474}
475EXPORT_SYMBOL(clk_round_rate);
476
477/*All below functions are called with lock held */
478
479/*
480 * Calculates pll clk rate for specific value of mode, m, n and p
481 *
482 * In normal mode
483 * rate = (2 * M[15:8] * Fin)/(N * 2^P)
484 *
485 * In Dithered mode
486 * rate = (2 * M[15:0] * Fin)/(256 * N * 2^P)
487 */
488unsigned long pll_calc_rate(struct clk *clk, int index)
489{
490 unsigned long rate = clk->pclk->rate;
491 struct pll_rate_tbl *tbls = clk->rate_config.tbls;
492 unsigned int mode;
493
494 mode = tbls[index].mode ? 256 : 1;
495 return (((2 * rate / 10000) * tbls[index].m) /
496 (mode * tbls[index].n * (1 << tbls[index].p))) * 10000;
497}
498
499/*
500 * calculates current programmed rate of pll1
501 *
502 * In normal mode
503 * rate = (2 * M[15:8] * Fin)/(N * 2^P)
504 *
505 * In Dithered mode
506 * rate = (2 * M[15:0] * Fin)/(256 * N * 2^P)
507 */
508int pll_clk_recalc(struct clk *clk)
509{
510 struct pll_clk_config *config = clk->private_data;
511 unsigned int num = 2, den = 0, val, mode = 0;
512
513 mode = (readl(config->mode_reg) >> config->masks->mode_shift) &
514 config->masks->mode_mask;
515
516 val = readl(config->cfg_reg);
517 /* calculate denominator */
518 den = (val >> config->masks->div_p_shift) & config->masks->div_p_mask;
519 den = 1 << den;
520 den *= (val >> config->masks->div_n_shift) & config->masks->div_n_mask;
521
522 /* calculate numerator & denominator */
523 if (!mode) {
524 /* Normal mode */
525 num *= (val >> config->masks->norm_fdbk_m_shift) &
526 config->masks->norm_fdbk_m_mask;
527 } else {
528 /* Dithered mode */
529 num *= (val >> config->masks->dith_fdbk_m_shift) &
530 config->masks->dith_fdbk_m_mask;
531 den *= 256;
532 }
533
534 if (!den)
535 return -EINVAL;
536
537 clk->rate = (((clk->pclk->rate/10000) * num) / den) * 10000;
538 return 0;
539}
540
541/*
542 * Configures new clock rate of pll
543 */
544int pll_clk_set_rate(struct clk *clk, unsigned long desired_rate)
545{
546 struct pll_rate_tbl *tbls = clk->rate_config.tbls;
547 struct pll_clk_config *config = clk->private_data;
548 unsigned long val, rate;
549 int i;
550
551 i = round_rate_index(clk, desired_rate, &rate);
552 if (i < 0)
553 return i;
554
555 val = readl(config->mode_reg) &
556 ~(config->masks->mode_mask << config->masks->mode_shift);
557 val |= (tbls[i].mode & config->masks->mode_mask) <<
558 config->masks->mode_shift;
559 writel(val, config->mode_reg);
560
561 val = readl(config->cfg_reg) &
562 ~(config->masks->div_p_mask << config->masks->div_p_shift);
563 val |= (tbls[i].p & config->masks->div_p_mask) <<
564 config->masks->div_p_shift;
565 val &= ~(config->masks->div_n_mask << config->masks->div_n_shift);
566 val |= (tbls[i].n & config->masks->div_n_mask) <<
567 config->masks->div_n_shift;
568 val &= ~(config->masks->dith_fdbk_m_mask <<
569 config->masks->dith_fdbk_m_shift);
570 if (tbls[i].mode)
571 val |= (tbls[i].m & config->masks->dith_fdbk_m_mask) <<
572 config->masks->dith_fdbk_m_shift;
573 else
574 val |= (tbls[i].m & config->masks->norm_fdbk_m_mask) <<
575 config->masks->norm_fdbk_m_shift;
576
577 writel(val, config->cfg_reg);
578
579 clk->rate = rate;
580
581 return 0;
582}
583
584/*
585 * Calculates ahb, apb clk rate for specific value of div
586 */
587unsigned long bus_calc_rate(struct clk *clk, int index)
588{
589 unsigned long rate = clk->pclk->rate;
590 struct bus_rate_tbl *tbls = clk->rate_config.tbls;
591
592 return rate / (tbls[index].div + 1);
593}
594
595/* calculates current programmed rate of ahb or apb bus */
596int bus_clk_recalc(struct clk *clk)
597{
598 struct bus_clk_config *config = clk->private_data;
599 unsigned int div;
600
601 div = ((readl(config->reg) >> config->masks->shift) &
602 config->masks->mask) + 1;
603
604 if (!div)
605 return -EINVAL;
606
607 clk->rate = (unsigned long)clk->pclk->rate / div;
608 return 0;
609}
610
611/* Configures new clock rate of AHB OR APB bus */
612int bus_clk_set_rate(struct clk *clk, unsigned long desired_rate)
613{
614 struct bus_rate_tbl *tbls = clk->rate_config.tbls;
615 struct bus_clk_config *config = clk->private_data;
616 unsigned long val, rate;
617 int i;
618
619 i = round_rate_index(clk, desired_rate, &rate);
620 if (i < 0)
621 return i;
622
623 val = readl(config->reg) &
624 ~(config->masks->mask << config->masks->shift);
625 val |= (tbls[i].div & config->masks->mask) << config->masks->shift;
626 writel(val, config->reg);
627
628 clk->rate = rate;
629
630 return 0;
631}
632
633/*
634 * gives rate for different values of eq, x and y
635 *
636 * Fout from synthesizer can be given from two equations:
637 * Fout1 = (Fin * X/Y)/2 EQ1
638 * Fout2 = Fin * X/Y EQ2
639 */
640unsigned long aux_calc_rate(struct clk *clk, int index)
641{
642 unsigned long rate = clk->pclk->rate;
643 struct aux_rate_tbl *tbls = clk->rate_config.tbls;
644 u8 eq = tbls[index].eq ? 1 : 2;
645
646 return (((rate/10000) * tbls[index].xscale) /
647 (tbls[index].yscale * eq)) * 10000;
648}
649
650/*
651 * calculates current programmed rate of auxiliary synthesizers
652 * used by: UART, FIRDA
653 *
654 * Fout from synthesizer can be given from two equations:
655 * Fout1 = (Fin * X/Y)/2
656 * Fout2 = Fin * X/Y
657 *
658 * Selection of eqn 1 or 2 is programmed in register
659 */
660int aux_clk_recalc(struct clk *clk)
661{
662 struct aux_clk_config *config = clk->private_data;
663 unsigned int num = 1, den = 1, val, eqn;
664
665 val = readl(config->synth_reg);
666
667 eqn = (val >> config->masks->eq_sel_shift) &
668 config->masks->eq_sel_mask;
669 if (eqn == config->masks->eq1_mask)
670 den *= 2;
671
672 /* calculate numerator */
673 num = (val >> config->masks->xscale_sel_shift) &
674 config->masks->xscale_sel_mask;
675
676 /* calculate denominator */
677 den *= (val >> config->masks->yscale_sel_shift) &
678 config->masks->yscale_sel_mask;
679
680 if (!den)
681 return -EINVAL;
682
683 clk->rate = (((clk->pclk->rate/10000) * num) / den) * 10000;
684 return 0;
685}
686
687/* Configures new clock rate of auxiliary synthesizers used by: UART, FIRDA*/
688int aux_clk_set_rate(struct clk *clk, unsigned long desired_rate)
689{
690 struct aux_rate_tbl *tbls = clk->rate_config.tbls;
691 struct aux_clk_config *config = clk->private_data;
692 unsigned long val, rate;
693 int i;
694
695 i = round_rate_index(clk, desired_rate, &rate);
696 if (i < 0)
697 return i;
698
699 val = readl(config->synth_reg) &
700 ~(config->masks->eq_sel_mask << config->masks->eq_sel_shift);
701 val |= (tbls[i].eq & config->masks->eq_sel_mask) <<
702 config->masks->eq_sel_shift;
703 val &= ~(config->masks->xscale_sel_mask <<
704 config->masks->xscale_sel_shift);
705 val |= (tbls[i].xscale & config->masks->xscale_sel_mask) <<
706 config->masks->xscale_sel_shift;
707 val &= ~(config->masks->yscale_sel_mask <<
708 config->masks->yscale_sel_shift);
709 val |= (tbls[i].yscale & config->masks->yscale_sel_mask) <<
710 config->masks->yscale_sel_shift;
711 writel(val, config->synth_reg);
712
713 clk->rate = rate;
714
715 return 0;
716}
717
718/*
719 * Calculates gpt clk rate for different values of mscale and nscale
720 *
721 * Fout= Fin/((2 ^ (N+1)) * (M+1))
722 */
723unsigned long gpt_calc_rate(struct clk *clk, int index)
724{
725 unsigned long rate = clk->pclk->rate;
726 struct gpt_rate_tbl *tbls = clk->rate_config.tbls;
727
728 return rate / ((1 << (tbls[index].nscale + 1)) *
729 (tbls[index].mscale + 1));
730}
731
732/*
733 * calculates current programmed rate of gpt synthesizers
734 * Fout from synthesizer can be given from below equations:
735 * Fout= Fin/((2 ^ (N+1)) * (M+1))
736 */
737int gpt_clk_recalc(struct clk *clk)
738{
739 struct gpt_clk_config *config = clk->private_data;
740 unsigned int div = 1, val;
741
742 val = readl(config->synth_reg);
743 div += (val >> config->masks->mscale_sel_shift) &
744 config->masks->mscale_sel_mask;
745 div *= 1 << (((val >> config->masks->nscale_sel_shift) &
746 config->masks->nscale_sel_mask) + 1);
747
748 if (!div)
749 return -EINVAL;
750
751 clk->rate = (unsigned long)clk->pclk->rate / div;
752 return 0;
753}
754
755/* Configures new clock rate of gptiliary synthesizers used by: UART, FIRDA*/
756int gpt_clk_set_rate(struct clk *clk, unsigned long desired_rate)
757{
758 struct gpt_rate_tbl *tbls = clk->rate_config.tbls;
759 struct gpt_clk_config *config = clk->private_data;
760 unsigned long val, rate;
761 int i;
762
763 i = round_rate_index(clk, desired_rate, &rate);
764 if (i < 0)
765 return i;
766
767 val = readl(config->synth_reg) & ~(config->masks->mscale_sel_mask <<
768 config->masks->mscale_sel_shift);
769 val |= (tbls[i].mscale & config->masks->mscale_sel_mask) <<
770 config->masks->mscale_sel_shift;
771 val &= ~(config->masks->nscale_sel_mask <<
772 config->masks->nscale_sel_shift);
773 val |= (tbls[i].nscale & config->masks->nscale_sel_mask) <<
774 config->masks->nscale_sel_shift;
775 writel(val, config->synth_reg);
776
777 clk->rate = rate;
778
779 return 0;
780}
781
782/*
783 * Calculates clcd clk rate for different values of div
784 *
785 * Fout from synthesizer can be given from below equation:
786 * Fout= Fin/2*div (division factor)
787 * div is 17 bits:-
788 * 0-13 (fractional part)
789 * 14-16 (integer part)
790 * To calculate Fout we left shift val by 14 bits and divide Fin by
791 * complete div (including fractional part) and then right shift the
792 * result by 14 places.
793 */
794unsigned long clcd_calc_rate(struct clk *clk, int index)
795{
796 unsigned long rate = clk->pclk->rate;
797 struct clcd_rate_tbl *tbls = clk->rate_config.tbls;
798
799 rate /= 1000;
800 rate <<= 12;
801 rate /= (2 * tbls[index].div);
802 rate >>= 12;
803 rate *= 1000;
804
805 return rate;
806}
807
808/*
809 * calculates current programmed rate of clcd synthesizer
810 * Fout from synthesizer can be given from below equation:
811 * Fout= Fin/2*div (division factor)
812 * div is 17 bits:-
813 * 0-13 (fractional part)
814 * 14-16 (integer part)
815 * To calculate Fout we left shift val by 14 bits and divide Fin by
816 * complete div (including fractional part) and then right shift the
817 * result by 14 places.
818 */
819int clcd_clk_recalc(struct clk *clk)
820{
821 struct clcd_clk_config *config = clk->private_data;
822 unsigned int div = 1;
823 unsigned long prate;
824 unsigned int val;
825
826 val = readl(config->synth_reg);
827 div = (val >> config->masks->div_factor_shift) &
828 config->masks->div_factor_mask;
829
830 if (!div)
831 return -EINVAL;
832
833 prate = clk->pclk->rate / 1000; /* first level division, make it KHz */
834
835 clk->rate = (((unsigned long)prate << 12) / (2 * div)) >> 12;
836 clk->rate *= 1000;
837 return 0;
838}
839
840/* Configures new clock rate of auxiliary synthesizers used by: UART, FIRDA*/
841int clcd_clk_set_rate(struct clk *clk, unsigned long desired_rate)
842{
843 struct clcd_rate_tbl *tbls = clk->rate_config.tbls;
844 struct clcd_clk_config *config = clk->private_data;
845 unsigned long val, rate;
846 int i;
847
848 i = round_rate_index(clk, desired_rate, &rate);
849 if (i < 0)
850 return i;
851
852 val = readl(config->synth_reg) & ~(config->masks->div_factor_mask <<
853 config->masks->div_factor_shift);
854 val |= (tbls[i].div & config->masks->div_factor_mask) <<
855 config->masks->div_factor_shift;
856 writel(val, config->synth_reg);
857
858 clk->rate = rate;
859
860 return 0;
861}
862
863/*
864 * Used for clocks that always have value as the parent clock divided by a
865 * fixed divisor
866 */
867int follow_parent(struct clk *clk)
868{
869 unsigned int div_factor = (clk->div_factor < 1) ? 1 : clk->div_factor;
870
871 clk->rate = clk->pclk->rate/div_factor;
872 return 0;
873}
874
875/**
876 * recalc_root_clocks - recalculate and propagate all root clocks
877 *
878 * Recalculates all root clocks (clocks with no parent), which if the
879 * clock's .recalc is set correctly, should also propagate their rates.
880 */
881void recalc_root_clocks(void)
882{
883 struct clk *pclk;
884 unsigned long flags;
885 int ret = 0;
886
887 spin_lock_irqsave(&clocks_lock, flags);
888 list_for_each_entry(pclk, &root_clks, sibling) {
889 if (pclk->recalc) {
890 ret = pclk->recalc(pclk);
891 /*
892 * recalc will return error if clk out is not programmed
893 * In this case configure default clock.
894 */
895 if (ret && pclk->set_rate)
896 pclk->set_rate(pclk, 0);
897 }
898 propagate_rate(pclk, 1);
899 /* Enable clks enabled on init, in software view */
900 if (pclk->flags & ENABLED_ON_INIT)
901 do_clk_enable(pclk);
902 }
903 spin_unlock_irqrestore(&clocks_lock, flags);
904}
905
906void __init clk_init(void)
907{
908 recalc_root_clocks();
909}
910
911#ifdef CONFIG_DEBUG_FS
912/*
913 * debugfs support to trace clock tree hierarchy and attributes
914 */
915static struct dentry *clk_debugfs_root;
916static int clk_debugfs_register_one(struct clk *c)
917{
918 int err;
919 struct dentry *d;
920 struct clk *pa = c->pclk;
921 char s[255];
922 char *p = s;
923
924 if (c) {
925 if (c->cl->con_id)
926 p += sprintf(p, "%s", c->cl->con_id);
927 if (c->cl->dev_id)
928 p += sprintf(p, "%s", c->cl->dev_id);
929 }
930 d = debugfs_create_dir(s, pa ? pa->dent : clk_debugfs_root);
931 if (!d)
932 return -ENOMEM;
933 c->dent = d;
934
935 d = debugfs_create_u32("usage_count", S_IRUGO, c->dent,
936 (u32 *)&c->usage_count);
937 if (!d) {
938 err = -ENOMEM;
939 goto err_out;
940 }
941 d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate);
942 if (!d) {
943 err = -ENOMEM;
944 goto err_out;
945 }
946 d = debugfs_create_x32("flags", S_IRUGO, c->dent, (u32 *)&c->flags);
947 if (!d) {
948 err = -ENOMEM;
949 goto err_out;
950 }
951 return 0;
952
953err_out:
954 debugfs_remove_recursive(c->dent);
955 return err;
956}
957
958static int clk_debugfs_register(struct clk *c)
959{
960 int err;
961 struct clk *pa = c->pclk;
962
963 if (pa && !pa->dent) {
964 err = clk_debugfs_register(pa);
965 if (err)
966 return err;
967 }
968
969 if (!c->dent) {
970 err = clk_debugfs_register_one(c);
971 if (err)
972 return err;
973 }
974 return 0;
975}
976
977static int __init clk_debugfs_init(void)
978{
979 struct clk *c;
980 struct dentry *d;
981 int err;
982
983 d = debugfs_create_dir("clock", NULL);
984 if (!d)
985 return -ENOMEM;
986 clk_debugfs_root = d;
987
988 list_for_each_entry(c, &clocks, node) {
989 err = clk_debugfs_register(c);
990 if (err)
991 goto err_out;
992 }
993 return 0;
994err_out:
995 debugfs_remove_recursive(clk_debugfs_root);
996 return err;
997}
998late_initcall(clk_debugfs_init);
999
1000static int clk_debugfs_reparent(struct clk *c)
1001{
1002 debugfs_remove(c->dent);
1003 return clk_debugfs_register_one(c);
1004}
1005#endif /* CONFIG_DEBUG_FS */
diff --git a/arch/arm/plat-spear/include/plat/clock.h b/arch/arm/plat-spear/include/plat/clock.h
deleted file mode 100644
index 0062bafef12d..000000000000
--- a/arch/arm/plat-spear/include/plat/clock.h
+++ /dev/null
@@ -1,249 +0,0 @@
1/*
2 * arch/arm/plat-spear/include/plat/clock.h
3 *
4 * Clock framework definitions for SPEAr platform
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __PLAT_CLOCK_H
15#define __PLAT_CLOCK_H
16
17#include <linux/list.h>
18#include <linux/clkdev.h>
19#include <linux/types.h>
20
21/* clk structure flags */
22#define ALWAYS_ENABLED (1 << 0) /* clock always enabled */
23#define RESET_TO_ENABLE (1 << 1) /* reset register bit to enable clk */
24#define ENABLED_ON_INIT (1 << 2) /* clocks enabled at init */
25
26/**
27 * struct clkops - clock operations
28 * @enable: pointer to clock enable function
29 * @disable: pointer to clock disable function
30 */
31struct clkops {
32 int (*enable) (struct clk *);
33 void (*disable) (struct clk *);
34};
35
36/**
37 * struct pclk_info - parents info
38 * @pclk: pointer to parent clk
39 * @pclk_val: value to be written for selecting this parent
40 */
41struct pclk_info {
42 struct clk *pclk;
43 u8 pclk_val;
44};
45
46/**
47 * struct pclk_sel - parents selection configuration
48 * @pclk_info: pointer to array of parent clock info
49 * @pclk_count: number of parents
50 * @pclk_sel_reg: register for selecting a parent
51 * @pclk_sel_mask: mask for selecting parent (can be used to clear bits also)
52 */
53struct pclk_sel {
54 struct pclk_info *pclk_info;
55 u8 pclk_count;
56 void __iomem *pclk_sel_reg;
57 unsigned int pclk_sel_mask;
58};
59
60/**
61 * struct rate_config - clk rate configurations
62 * @tbls: array of device specific clk rate tables, in ascending order of rates
63 * @count: size of tbls array
64 * @default_index: default setting when originally disabled
65 */
66struct rate_config {
67 void *tbls;
68 u8 count;
69 u8 default_index;
70};
71
72/**
73 * struct clk - clock structure
74 * @usage_count: num of users who enabled this clock
75 * @flags: flags for clock properties
76 * @rate: programmed clock rate in Hz
77 * @en_reg: clk enable/disable reg
78 * @en_reg_bit: clk enable/disable bit
79 * @ops: clk enable/disable ops - generic_clkops selected if NULL
80 * @recalc: pointer to clock rate recalculate function
81 * @set_rate: pointer to clock set rate function
82 * @calc_rate: pointer to clock get rate function for index
83 * @rate_config: rate configuration information, used by set_rate
84 * @div_factor: division factor to parent clock.
85 * @pclk: current parent clk
86 * @pclk_sel: pointer to parent selection structure
87 * @pclk_sel_shift: register shift for selecting parent of this clock
88 * @children: list for childrens or this clock
89 * @sibling: node for list of clocks having same parents
90 * @private_data: clock specific private data
91 * @node: list to maintain clocks linearly
92 * @cl: clocklook up associated with this clock
93 * @dent: object for debugfs
94 */
95struct clk {
96 unsigned int usage_count;
97 unsigned int flags;
98 unsigned long rate;
99 void __iomem *en_reg;
100 u8 en_reg_bit;
101 const struct clkops *ops;
102 int (*recalc) (struct clk *);
103 int (*set_rate) (struct clk *, unsigned long rate);
104 unsigned long (*calc_rate)(struct clk *, int index);
105 struct rate_config rate_config;
106 unsigned int div_factor;
107
108 struct clk *pclk;
109 struct pclk_sel *pclk_sel;
110 unsigned int pclk_sel_shift;
111
112 struct list_head children;
113 struct list_head sibling;
114 void *private_data;
115#ifdef CONFIG_DEBUG_FS
116 struct list_head node;
117 struct clk_lookup *cl;
118 struct dentry *dent;
119#endif
120};
121
122/* pll configuration structure */
123struct pll_clk_masks {
124 u32 mode_mask;
125 u32 mode_shift;
126
127 u32 norm_fdbk_m_mask;
128 u32 norm_fdbk_m_shift;
129 u32 dith_fdbk_m_mask;
130 u32 dith_fdbk_m_shift;
131 u32 div_p_mask;
132 u32 div_p_shift;
133 u32 div_n_mask;
134 u32 div_n_shift;
135};
136
137struct pll_clk_config {
138 void __iomem *mode_reg;
139 void __iomem *cfg_reg;
140 struct pll_clk_masks *masks;
141};
142
143/* pll clk rate config structure */
144struct pll_rate_tbl {
145 u8 mode;
146 u16 m;
147 u8 n;
148 u8 p;
149};
150
151/* ahb and apb bus configuration structure */
152struct bus_clk_masks {
153 u32 mask;
154 u32 shift;
155};
156
157struct bus_clk_config {
158 void __iomem *reg;
159 struct bus_clk_masks *masks;
160};
161
162/* ahb and apb clk bus rate config structure */
163struct bus_rate_tbl {
164 u8 div;
165};
166
167/* Aux clk configuration structure: applicable to UART and FIRDA */
168struct aux_clk_masks {
169 u32 eq_sel_mask;
170 u32 eq_sel_shift;
171 u32 eq1_mask;
172 u32 eq2_mask;
173 u32 xscale_sel_mask;
174 u32 xscale_sel_shift;
175 u32 yscale_sel_mask;
176 u32 yscale_sel_shift;
177};
178
179struct aux_clk_config {
180 void __iomem *synth_reg;
181 struct aux_clk_masks *masks;
182};
183
184/* aux clk rate config structure */
185struct aux_rate_tbl {
186 u16 xscale;
187 u16 yscale;
188 u8 eq;
189};
190
191/* GPT clk configuration structure */
192struct gpt_clk_masks {
193 u32 mscale_sel_mask;
194 u32 mscale_sel_shift;
195 u32 nscale_sel_mask;
196 u32 nscale_sel_shift;
197};
198
199struct gpt_clk_config {
200 void __iomem *synth_reg;
201 struct gpt_clk_masks *masks;
202};
203
204/* gpt clk rate config structure */
205struct gpt_rate_tbl {
206 u16 mscale;
207 u16 nscale;
208};
209
210/* clcd clk configuration structure */
211struct clcd_synth_masks {
212 u32 div_factor_mask;
213 u32 div_factor_shift;
214};
215
216struct clcd_clk_config {
217 void __iomem *synth_reg;
218 struct clcd_synth_masks *masks;
219};
220
221/* clcd clk rate config structure */
222struct clcd_rate_tbl {
223 u16 div;
224};
225
226/* platform specific clock functions */
227void __init clk_init(void);
228void clk_register(struct clk_lookup *cl);
229void recalc_root_clocks(void);
230
231/* clock recalc & set rate functions */
232int follow_parent(struct clk *clk);
233unsigned long pll_calc_rate(struct clk *clk, int index);
234int pll_clk_recalc(struct clk *clk);
235int pll_clk_set_rate(struct clk *clk, unsigned long desired_rate);
236unsigned long bus_calc_rate(struct clk *clk, int index);
237int bus_clk_recalc(struct clk *clk);
238int bus_clk_set_rate(struct clk *clk, unsigned long desired_rate);
239unsigned long gpt_calc_rate(struct clk *clk, int index);
240int gpt_clk_recalc(struct clk *clk);
241int gpt_clk_set_rate(struct clk *clk, unsigned long desired_rate);
242unsigned long aux_calc_rate(struct clk *clk, int index);
243int aux_clk_recalc(struct clk *clk);
244int aux_clk_set_rate(struct clk *clk, unsigned long desired_rate);
245unsigned long clcd_calc_rate(struct clk *clk, int index);
246int clcd_clk_recalc(struct clk *clk);
247int clcd_clk_set_rate(struct clk *clk, unsigned long desired_rate);
248
249#endif /* __PLAT_CLOCK_H */
diff --git a/arch/arm/plat-spear/include/plat/debug-macro.S b/arch/arm/plat-spear/include/plat/debug-macro.S
index 02b160a1ec9b..ab3de721c5db 100644
--- a/arch/arm/plat-spear/include/plat/debug-macro.S
+++ b/arch/arm/plat-spear/include/plat/debug-macro.S
@@ -12,7 +12,7 @@
12 */ 12 */
13 13
14#include <linux/amba/serial.h> 14#include <linux/amba/serial.h>
15#include <mach/hardware.h> 15#include <mach/spear.h>
16 16
17 .macro addruart, rp, rv, tmp 17 .macro addruart, rp, rv, tmp
18 mov \rp, #SPEAR_DBG_UART_BASE @ Physical base 18 mov \rp, #SPEAR_DBG_UART_BASE @ Physical base
diff --git a/arch/arm/plat-spear/include/plat/hardware.h b/arch/arm/plat-spear/include/plat/hardware.h
deleted file mode 100644
index 70187d763e26..000000000000
--- a/arch/arm/plat-spear/include/plat/hardware.h
+++ /dev/null
@@ -1,17 +0,0 @@
1/*
2 * arch/arm/plat-spear/include/plat/hardware.h
3 *
4 * Hardware definitions for SPEAr
5 *
6 * Copyright (C) 2010 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __PLAT_HARDWARE_H
15#define __PLAT_HARDWARE_H
16
17#endif /* __PLAT_HARDWARE_H */
diff --git a/arch/arm/plat-spear/include/plat/padmux.h b/arch/arm/plat-spear/include/plat/padmux.h
deleted file mode 100644
index 877f3adcf610..000000000000
--- a/arch/arm/plat-spear/include/plat/padmux.h
+++ /dev/null
@@ -1,92 +0,0 @@
1/*
2 * arch/arm/plat-spear/include/plat/padmux.h
3 *
4 * SPEAr platform specific gpio pads muxing file
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __PLAT_PADMUX_H
15#define __PLAT_PADMUX_H
16
17#include <linux/types.h>
18
19/*
20 * struct pmx_reg: configuration structure for mode reg and mux reg
21 *
22 * offset: offset of mode reg
23 * mask: mask of mode reg
24 */
25struct pmx_reg {
26 u32 offset;
27 u32 mask;
28};
29
30/*
31 * struct pmx_dev_mode: configuration structure every group of modes of a device
32 *
33 * ids: all modes for this configuration
34 * mask: mask for supported mode
35 */
36struct pmx_dev_mode {
37 u32 ids;
38 u32 mask;
39};
40
41/*
42 * struct pmx_mode: mode definition structure
43 *
44 * name: mode name
45 * mask: mode mask
46 */
47struct pmx_mode {
48 char *name;
49 u32 id;
50 u32 mask;
51};
52
53/*
54 * struct pmx_dev: device definition structure
55 *
56 * name: device name
57 * modes: device configuration array for different modes supported
58 * mode_count: size of modes array
59 * is_active: is peripheral active/enabled
60 * enb_on_reset: if 1, mask bits to be cleared in reg otherwise to be set in reg
61 */
62struct pmx_dev {
63 char *name;
64 struct pmx_dev_mode *modes;
65 u8 mode_count;
66 bool is_active;
67 bool enb_on_reset;
68};
69
70/*
71 * struct pmx_driver: driver definition structure
72 *
73 * mode: mode to be set
74 * devs: array of pointer to pmx devices
75 * devs_count: ARRAY_SIZE of devs
76 * base: base address of soc config registers
77 * mode_reg: structure of mode config register
78 * mux_reg: structure of device mux config register
79 */
80struct pmx_driver {
81 struct pmx_mode *mode;
82 struct pmx_dev **devs;
83 u8 devs_count;
84 u32 *base;
85 struct pmx_reg mode_reg;
86 struct pmx_reg mux_reg;
87};
88
89/* pmx functions */
90int pmx_register(struct pmx_driver *driver);
91
92#endif /* __PLAT_PADMUX_H */
diff --git a/arch/arm/plat-spear/include/plat/pl080.h b/arch/arm/plat-spear/include/plat/pl080.h
new file mode 100644
index 000000000000..e14a3e4932f9
--- /dev/null
+++ b/arch/arm/plat-spear/include/plat/pl080.h
@@ -0,0 +1,21 @@
1/*
2 * arch/arm/plat-spear/include/plat/pl080.h
3 *
4 * DMAC pl080 definitions for SPEAr platform
5 *
6 * Copyright (C) 2012 ST Microelectronics
7 * Viresh Kumar <viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __PLAT_PL080_H
15#define __PLAT_PL080_H
16
17struct pl08x_dma_chan;
18int pl080_get_signal(struct pl08x_dma_chan *ch);
19void pl080_put_signal(struct pl08x_dma_chan *ch);
20
21#endif /* __PLAT_PL080_H */
diff --git a/arch/arm/plat-spear/include/plat/uncompress.h b/arch/arm/plat-spear/include/plat/uncompress.h
index 1bf84527aee4..6dd455bafdfd 100644
--- a/arch/arm/plat-spear/include/plat/uncompress.h
+++ b/arch/arm/plat-spear/include/plat/uncompress.h
@@ -13,7 +13,7 @@
13 13
14#include <linux/io.h> 14#include <linux/io.h>
15#include <linux/amba/serial.h> 15#include <linux/amba/serial.h>
16#include <mach/hardware.h> 16#include <mach/spear.h>
17 17
18#ifndef __PLAT_UNCOMPRESS_H 18#ifndef __PLAT_UNCOMPRESS_H
19#define __PLAT_UNCOMPRESS_H 19#define __PLAT_UNCOMPRESS_H
diff --git a/arch/arm/plat-spear/padmux.c b/arch/arm/plat-spear/padmux.c
deleted file mode 100644
index 555eec6dc1cb..000000000000
--- a/arch/arm/plat-spear/padmux.c
+++ /dev/null
@@ -1,164 +0,0 @@
1/*
2 * arch/arm/plat-spear/include/plat/padmux.c
3 *
4 * SPEAr platform specific gpio pads muxing source file
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <linux/err.h>
15#include <linux/io.h>
16#include <linux/slab.h>
17#include <plat/padmux.h>
18
19/*
20 * struct pmx: pmx definition structure
21 *
22 * base: base address of configuration registers
23 * mode_reg: mode configurations
24 * mux_reg: muxing configurations
25 * active_mode: pointer to current active mode
26 */
27struct pmx {
28 u32 base;
29 struct pmx_reg mode_reg;
30 struct pmx_reg mux_reg;
31 struct pmx_mode *active_mode;
32};
33
34static struct pmx *pmx;
35
36/**
37 * pmx_mode_set - Enables an multiplexing mode
38 * @mode - pointer to pmx mode
39 *
40 * It will set mode of operation in hardware.
41 * Returns -ve on Err otherwise 0
42 */
43static int pmx_mode_set(struct pmx_mode *mode)
44{
45 u32 val;
46
47 if (!mode->name)
48 return -EFAULT;
49
50 pmx->active_mode = mode;
51
52 val = readl(pmx->base + pmx->mode_reg.offset);
53 val &= ~pmx->mode_reg.mask;
54 val |= mode->mask & pmx->mode_reg.mask;
55 writel(val, pmx->base + pmx->mode_reg.offset);
56
57 return 0;
58}
59
60/**
61 * pmx_devs_enable - Enables list of devices
62 * @devs - pointer to pmx device array
63 * @count - number of devices to enable
64 *
65 * It will enable pads for all required peripherals once and only once.
66 * If peripheral is not supported by current mode then request is rejected.
67 * Conflicts between peripherals are not handled and peripherals will be
68 * enabled in the order they are present in pmx_dev array.
69 * In case of conflicts last peripheral enabled will be present.
70 * Returns -ve on Err otherwise 0
71 */
72static int pmx_devs_enable(struct pmx_dev **devs, u8 count)
73{
74 u32 val, i, mask;
75
76 if (!count)
77 return -EINVAL;
78
79 val = readl(pmx->base + pmx->mux_reg.offset);
80 for (i = 0; i < count; i++) {
81 u8 j = 0;
82
83 if (!devs[i]->name || !devs[i]->modes) {
84 printk(KERN_ERR "padmux: dev name or modes is null\n");
85 continue;
86 }
87 /* check if peripheral exists in active mode */
88 if (pmx->active_mode) {
89 bool found = false;
90 for (j = 0; j < devs[i]->mode_count; j++) {
91 if (devs[i]->modes[j].ids &
92 pmx->active_mode->id) {
93 found = true;
94 break;
95 }
96 }
97 if (found == false) {
98 printk(KERN_ERR "%s device not available in %s"\
99 "mode\n", devs[i]->name,
100 pmx->active_mode->name);
101 continue;
102 }
103 }
104
105 /* enable peripheral */
106 mask = devs[i]->modes[j].mask & pmx->mux_reg.mask;
107 if (devs[i]->enb_on_reset)
108 val &= ~mask;
109 else
110 val |= mask;
111
112 devs[i]->is_active = true;
113 }
114 writel(val, pmx->base + pmx->mux_reg.offset);
115 kfree(pmx);
116
117 /* this will ensure that multiplexing can't be changed now */
118 pmx = (struct pmx *)-1;
119
120 return 0;
121}
122
123/**
124 * pmx_register - registers a platform requesting pad mux feature
125 * @driver - pointer to driver structure containing driver specific parameters
126 *
127 * Also this must be called only once. This will allocate memory for pmx
128 * structure, will call pmx_mode_set, will call pmx_devs_enable.
129 * Returns -ve on Err otherwise 0
130 */
131int pmx_register(struct pmx_driver *driver)
132{
133 int ret = 0;
134
135 if (pmx)
136 return -EPERM;
137 if (!driver->base || !driver->devs)
138 return -EFAULT;
139
140 pmx = kzalloc(sizeof(*pmx), GFP_KERNEL);
141 if (!pmx)
142 return -ENOMEM;
143
144 pmx->base = (u32)driver->base;
145 pmx->mode_reg.offset = driver->mode_reg.offset;
146 pmx->mode_reg.mask = driver->mode_reg.mask;
147 pmx->mux_reg.offset = driver->mux_reg.offset;
148 pmx->mux_reg.mask = driver->mux_reg.mask;
149
150 /* choose mode to enable */
151 if (driver->mode) {
152 ret = pmx_mode_set(driver->mode);
153 if (ret)
154 goto pmx_fail;
155 }
156 ret = pmx_devs_enable(driver->devs, driver->devs_count);
157 if (ret)
158 goto pmx_fail;
159
160 return 0;
161
162pmx_fail:
163 return ret;
164}
diff --git a/arch/arm/plat-spear/pl080.c b/arch/arm/plat-spear/pl080.c
new file mode 100644
index 000000000000..a56a067717c1
--- /dev/null
+++ b/arch/arm/plat-spear/pl080.c
@@ -0,0 +1,80 @@
1/*
2 * arch/arm/plat-spear/pl080.c
3 *
4 * DMAC pl080 definitions for SPEAr platform
5 *
6 * Copyright (C) 2012 ST Microelectronics
7 * Viresh Kumar <viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <linux/amba/pl08x.h>
15#include <linux/amba/bus.h>
16#include <linux/bug.h>
17#include <linux/err.h>
18#include <linux/io.h>
19#include <linux/spinlock_types.h>
20#include <mach/spear.h>
21#include <mach/misc_regs.h>
22
23static spinlock_t lock = __SPIN_LOCK_UNLOCKED(x);
24
25struct {
26 unsigned char busy;
27 unsigned char val;
28} signals[16] = {{0, 0}, };
29
30int pl080_get_signal(struct pl08x_dma_chan *ch)
31{
32 const struct pl08x_channel_data *cd = ch->cd;
33 unsigned int signal = cd->min_signal, val;
34 unsigned long flags;
35
36 spin_lock_irqsave(&lock, flags);
37
38 /* Return if signal is already acquired by somebody else */
39 if (signals[signal].busy &&
40 (signals[signal].val != cd->muxval)) {
41 spin_unlock_irqrestore(&lock, flags);
42 return -EBUSY;
43 }
44
45 /* If acquiring for the first time, configure it */
46 if (!signals[signal].busy) {
47 val = readl(DMA_CHN_CFG);
48
49 /*
50 * Each request line has two bits in DMA_CHN_CFG register. To
51 * goto the bits of current request line, do left shift of
52 * value by 2 * signal number.
53 */
54 val &= ~(0x3 << (signal * 2));
55 val |= cd->muxval << (signal * 2);
56 writel(val, DMA_CHN_CFG);
57 }
58
59 signals[signal].busy++;
60 signals[signal].val = cd->muxval;
61 spin_unlock_irqrestore(&lock, flags);
62
63 return signal;
64}
65
66void pl080_put_signal(struct pl08x_dma_chan *ch)
67{
68 const struct pl08x_channel_data *cd = ch->cd;
69 unsigned long flags;
70
71 spin_lock_irqsave(&lock, flags);
72
73 /* if signal is not used */
74 if (!signals[cd->min_signal].busy)
75 BUG();
76
77 signals[cd->min_signal].busy--;
78
79 spin_unlock_irqrestore(&lock, flags);
80}
diff --git a/arch/arm/plat-spear/restart.c b/arch/arm/plat-spear/restart.c
index 16f203e78d89..ea0a61302b7e 100644
--- a/arch/arm/plat-spear/restart.c
+++ b/arch/arm/plat-spear/restart.c
@@ -13,9 +13,10 @@
13#include <linux/io.h> 13#include <linux/io.h>
14#include <asm/system_misc.h> 14#include <asm/system_misc.h>
15#include <asm/hardware/sp810.h> 15#include <asm/hardware/sp810.h>
16#include <mach/hardware.h> 16#include <mach/spear.h>
17#include <mach/generic.h> 17#include <mach/generic.h>
18 18
19#define SPEAR13XX_SYS_SW_RES (VA_MISC_BASE + 0x204)
19void spear_restart(char mode, const char *cmd) 20void spear_restart(char mode, const char *cmd)
20{ 21{
21 if (mode == 's') { 22 if (mode == 's') {
@@ -23,6 +24,10 @@ void spear_restart(char mode, const char *cmd)
23 soft_restart(0); 24 soft_restart(0);
24 } else { 25 } else {
25 /* hardware reset, Use on-chip reset capability */ 26 /* hardware reset, Use on-chip reset capability */
27#ifdef CONFIG_ARCH_SPEAR13XX
28 writel_relaxed(0x01, SPEAR13XX_SYS_SW_RES);
29#else
26 sysctl_soft_reset((void __iomem *)VA_SPEAR_SYS_CTRL_BASE); 30 sysctl_soft_reset((void __iomem *)VA_SPEAR_SYS_CTRL_BASE);
31#endif
27 } 32 }
28} 33}
diff --git a/arch/arm/plat-spear/time.c b/arch/arm/plat-spear/time.c
index abb5bdecd509..03321af5de9f 100644
--- a/arch/arm/plat-spear/time.c
+++ b/arch/arm/plat-spear/time.c
@@ -15,14 +15,15 @@
15#include <linux/err.h> 15#include <linux/err.h>
16#include <linux/init.h> 16#include <linux/init.h>
17#include <linux/interrupt.h> 17#include <linux/interrupt.h>
18#include <linux/ioport.h>
18#include <linux/io.h> 19#include <linux/io.h>
19#include <linux/kernel.h> 20#include <linux/kernel.h>
21#include <linux/of_irq.h>
22#include <linux/of_address.h>
20#include <linux/time.h> 23#include <linux/time.h>
21#include <linux/irq.h> 24#include <linux/irq.h>
22#include <asm/mach/time.h> 25#include <asm/mach/time.h>
23#include <mach/generic.h> 26#include <mach/generic.h>
24#include <mach/hardware.h>
25#include <mach/irqs.h>
26 27
27/* 28/*
28 * We would use TIMER0 and TIMER1 as clockevent and clocksource. 29 * We would use TIMER0 and TIMER1 as clockevent and clocksource.
@@ -175,7 +176,7 @@ static struct irqaction spear_timer_irq = {
175 .handler = spear_timer_interrupt 176 .handler = spear_timer_interrupt
176}; 177};
177 178
178static void __init spear_clockevent_init(void) 179static void __init spear_clockevent_init(int irq)
179{ 180{
180 u32 tick_rate; 181 u32 tick_rate;
181 182
@@ -195,22 +196,35 @@ static void __init spear_clockevent_init(void)
195 196
196 clockevents_register_device(&clkevt); 197 clockevents_register_device(&clkevt);
197 198
198 setup_irq(SPEAR_GPT0_CHAN0_IRQ, &spear_timer_irq); 199 setup_irq(irq, &spear_timer_irq);
199} 200}
200 201
201void __init spear_setup_timer(void) 202const static struct of_device_id timer_of_match[] __initconst = {
203 { .compatible = "st,spear-timer", },
204 { },
205};
206
207void __init spear_setup_of_timer(void)
202{ 208{
203 int ret; 209 struct device_node *np;
210 int irq, ret;
211
212 np = of_find_matching_node(NULL, timer_of_match);
213 if (!np) {
214 pr_err("%s: No timer passed via DT\n", __func__);
215 return;
216 }
204 217
205 if (!request_mem_region(SPEAR_GPT0_BASE, SZ_1K, "gpt0")) { 218 irq = irq_of_parse_and_map(np, 0);
206 pr_err("%s:cannot get IO addr\n", __func__); 219 if (!irq) {
220 pr_err("%s: No irq passed for timer via DT\n", __func__);
207 return; 221 return;
208 } 222 }
209 223
210 gpt_base = (void __iomem *)ioremap(SPEAR_GPT0_BASE, SZ_1K); 224 gpt_base = of_iomap(np, 0);
211 if (!gpt_base) { 225 if (!gpt_base) {
212 pr_err("%s:ioremap failed for gpt\n", __func__); 226 pr_err("%s: of iomap failed\n", __func__);
213 goto err_mem; 227 return;
214 } 228 }
215 229
216 gpt_clk = clk_get_sys("gpt0", NULL); 230 gpt_clk = clk_get_sys("gpt0", NULL);
@@ -219,21 +233,19 @@ void __init spear_setup_timer(void)
219 goto err_iomap; 233 goto err_iomap;
220 } 234 }
221 235
222 ret = clk_enable(gpt_clk); 236 ret = clk_prepare_enable(gpt_clk);
223 if (ret < 0) { 237 if (ret < 0) {
224 pr_err("%s:couldn't enable gpt clock\n", __func__); 238 pr_err("%s:couldn't prepare-enable gpt clock\n", __func__);
225 goto err_clk; 239 goto err_prepare_enable_clk;
226 } 240 }
227 241
228 spear_clockevent_init(); 242 spear_clockevent_init(irq);
229 spear_clocksource_init(); 243 spear_clocksource_init();
230 244
231 return; 245 return;
232 246
233err_clk: 247err_prepare_enable_clk:
234 clk_put(gpt_clk); 248 clk_put(gpt_clk);
235err_iomap: 249err_iomap:
236 iounmap(gpt_base); 250 iounmap(gpt_base);
237err_mem:
238 release_mem_region(SPEAR_GPT0_BASE, SZ_1K);
239} 251}
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-11 09:14:09 -0400