Merge branch 'for_2.6.39/pm-misc' of ssh://master.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm into omap-for-linus

82 files changed, 760 insertions, 549 deletions

diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig
index 47f63d480141..cc31bec2e316 100644
--- a/arch/alpha/Kconfig
+++ b/arch/alpha/Kconfig
@@ -11,6 +11,7 @@ config ALPHA
         select HAVE_GENERIC_HARDIRQS
         select GENERIC_IRQ_PROBE
         select AUTO_IRQ_AFFINITY if SMP
+        select GENERIC_HARDIRQS_NO_DEPRECATED
         help
           The Alpha is a 64-bit general-purpose processor designed and
           marketed by the Digital Equipment Corporation of blessed memory,
diff --git a/arch/alpha/kernel/irq.c b/arch/alpha/kernel/irq.c
index 9ab234f48dd8..a19d60082299 100644
--- a/arch/alpha/kernel/irq.c
+++ b/arch/alpha/kernel/irq.c
@@ -44,11 +44,16 @@ static char irq_user_affinity[NR_IRQS];
 
 int irq_select_affinity(unsigned int irq)
 {
-        struct irq_desc *desc = irq_to_desc[irq];
+        struct irq_data *data = irq_get_irq_data(irq);
+        struct irq_chip *chip;
         static int last_cpu;
         int cpu = last_cpu + 1;
 
-        if (!desc || !get_irq_desc_chip(desc)->set_affinity || irq_user_affinity[irq])
+        if (!data)
+                return 1;
+        chip = irq_data_get_irq_chip(data);
+
+        if (!chip->irq_set_affinity || irq_user_affinity[irq])
                 return 1;
 
         while (!cpu_possible(cpu) ||
@@ -56,8 +61,8 @@ int irq_select_affinity(unsigned int irq)
                 cpu = (cpu < (NR_CPUS-1) ? cpu + 1 : 0);
         last_cpu = cpu;
 
-        cpumask_copy(desc->affinity, cpumask_of(cpu));
-        get_irq_desc_chip(desc)->set_affinity(irq, cpumask_of(cpu));
+        cpumask_copy(data->affinity, cpumask_of(cpu));
+        chip->irq_set_affinity(data, cpumask_of(cpu), false);
         return 0;
 }
 #endif /* CONFIG_SMP */
diff --git a/arch/alpha/kernel/irq_alpha.c b/arch/alpha/kernel/irq_alpha.c
index 2d0679b60939..411ca11d0a18 100644
--- a/arch/alpha/kernel/irq_alpha.c
+++ b/arch/alpha/kernel/irq_alpha.c
@@ -228,14 +228,9 @@ struct irqaction timer_irqaction = {
 void __init
 init_rtc_irq(void)
 {
-        struct irq_desc *desc = irq_to_desc(RTC_IRQ);
-
-        if (desc) {
-                desc->status |= IRQ_DISABLED;
-                set_irq_chip_and_handler_name(RTC_IRQ, &no_irq_chip,
-                        handle_simple_irq, "RTC");
-                setup_irq(RTC_IRQ, &timer_irqaction);
-        }
+        set_irq_chip_and_handler_name(RTC_IRQ, &no_irq_chip,
+                                      handle_simple_irq, "RTC");
+        setup_irq(RTC_IRQ, &timer_irqaction);
 }
 
 /* Dummy irqactions.  */
diff --git a/arch/alpha/kernel/irq_i8259.c b/arch/alpha/kernel/irq_i8259.c
index 956ea0ed1694..c7cc9813e45f 100644
--- a/arch/alpha/kernel/irq_i8259.c
+++ b/arch/alpha/kernel/irq_i8259.c
@@ -33,10 +33,10 @@ i8259_update_irq_hw(unsigned int irq, unsigned long mask)
 }
 
 inline void
-i8259a_enable_irq(unsigned int irq)
+i8259a_enable_irq(struct irq_data *d)
 {
         spin_lock(&i8259_irq_lock);
-        i8259_update_irq_hw(irq, cached_irq_mask &= ~(1 << irq));
+        i8259_update_irq_hw(d->irq, cached_irq_mask &= ~(1 << d->irq));
         spin_unlock(&i8259_irq_lock);
 }
 
@@ -47,16 +47,18 @@ __i8259a_disable_irq(unsigned int irq)
 }
 
 void
-i8259a_disable_irq(unsigned int irq)
+i8259a_disable_irq(struct irq_data *d)
 {
         spin_lock(&i8259_irq_lock);
-        __i8259a_disable_irq(irq);
+        __i8259a_disable_irq(d->irq);
         spin_unlock(&i8259_irq_lock);
 }
 
 void
-i8259a_mask_and_ack_irq(unsigned int irq)
+i8259a_mask_and_ack_irq(struct irq_data *d)
 {
+        unsigned int irq = d->irq;
+
         spin_lock(&i8259_irq_lock);
         __i8259a_disable_irq(irq);
 
@@ -71,9 +73,9 @@ i8259a_mask_and_ack_irq(unsigned int irq)
 
 struct irq_chip i8259a_irq_type = {
         .name           = "XT-PIC",
-        .unmask         = i8259a_enable_irq,
-        .mask           = i8259a_disable_irq,
-        .mask_ack       = i8259a_mask_and_ack_irq,
+        .irq_unmask     = i8259a_enable_irq,
+        .irq_mask       = i8259a_disable_irq,
+        .irq_mask_ack   = i8259a_mask_and_ack_irq,
 };
 
 void __init
diff --git a/arch/alpha/kernel/irq_impl.h b/arch/alpha/kernel/irq_impl.h
index b63ccd7386f1..d507a234b05d 100644
--- a/arch/alpha/kernel/irq_impl.h
+++ b/arch/alpha/kernel/irq_impl.h
@@ -31,11 +31,9 @@ extern void init_rtc_irq(void);
 
 extern void common_init_isa_dma(void);
 
-extern void i8259a_enable_irq(unsigned int);
-extern void i8259a_disable_irq(unsigned int);
-extern void i8259a_mask_and_ack_irq(unsigned int);
-extern unsigned int i8259a_startup_irq(unsigned int);
-extern void i8259a_end_irq(unsigned int);
+extern void i8259a_enable_irq(struct irq_data *d);
+extern void i8259a_disable_irq(struct irq_data *d);
+extern void i8259a_mask_and_ack_irq(struct irq_data *d);
 extern struct irq_chip i8259a_irq_type;
 extern void init_i8259a_irqs(void);
 
diff --git a/arch/alpha/kernel/irq_pyxis.c b/arch/alpha/kernel/irq_pyxis.c
index 2863458c853e..b30227fa7f5f 100644
--- a/arch/alpha/kernel/irq_pyxis.c
+++ b/arch/alpha/kernel/irq_pyxis.c
@@ -29,21 +29,21 @@ pyxis_update_irq_hw(unsigned long mask)
 }
 
 static inline void
-pyxis_enable_irq(unsigned int irq)
+pyxis_enable_irq(struct irq_data *d)
 {
-        pyxis_update_irq_hw(cached_irq_mask |= 1UL << (irq - 16));
+        pyxis_update_irq_hw(cached_irq_mask |= 1UL << (d->irq - 16));
 }
 
 static void
-pyxis_disable_irq(unsigned int irq)
+pyxis_disable_irq(struct irq_data *d)
 {
-        pyxis_update_irq_hw(cached_irq_mask &= ~(1UL << (irq - 16)));
+        pyxis_update_irq_hw(cached_irq_mask &= ~(1UL << (d->irq - 16)));
 }
 
 static void
-pyxis_mask_and_ack_irq(unsigned int irq)
+pyxis_mask_and_ack_irq(struct irq_data *d)
 {
-        unsigned long bit = 1UL << (irq - 16);
+        unsigned long bit = 1UL << (d->irq - 16);
         unsigned long mask = cached_irq_mask &= ~bit;
 
         /* Disable the interrupt.  */
@@ -58,9 +58,9 @@ pyxis_mask_and_ack_irq(unsigned int irq)
 
 static struct irq_chip pyxis_irq_type = {
         .name           = "PYXIS",
-        .mask_ack       = pyxis_mask_and_ack_irq,
-        .mask           = pyxis_disable_irq,
-        .unmask         = pyxis_enable_irq,
+        .irq_mask_ack   = pyxis_mask_and_ack_irq,
+        .irq_mask       = pyxis_disable_irq,
+        .irq_unmask     = pyxis_enable_irq,
 };
 
 void 
@@ -103,7 +103,7 @@ init_pyxis_irqs(unsigned long ignore_mask)
                 if ((ignore_mask >> i) & 1)
                         continue;
                 set_irq_chip_and_handler(i, &pyxis_irq_type, handle_level_irq);
-                irq_to_desc(i)->status |= IRQ_LEVEL;
+                irq_set_status_flags(i, IRQ_LEVEL);
         }
 
         setup_irq(16+7, &isa_cascade_irqaction);
diff --git a/arch/alpha/kernel/irq_srm.c b/arch/alpha/kernel/irq_srm.c
index 0e57e828b413..82a47bba41c4 100644
--- a/arch/alpha/kernel/irq_srm.c
+++ b/arch/alpha/kernel/irq_srm.c
@@ -18,27 +18,27 @@
 DEFINE_SPINLOCK(srm_irq_lock);
 
 static inline void
-srm_enable_irq(unsigned int irq)
+srm_enable_irq(struct irq_data *d)
 {
         spin_lock(&srm_irq_lock);
-        cserve_ena(irq - 16);
+        cserve_ena(d->irq - 16);
         spin_unlock(&srm_irq_lock);
 }
 
 static void
-srm_disable_irq(unsigned int irq)
+srm_disable_irq(struct irq_data *d)
 {
         spin_lock(&srm_irq_lock);
-        cserve_dis(irq - 16);
+        cserve_dis(d->irq - 16);
         spin_unlock(&srm_irq_lock);
 }
 
 /* Handle interrupts from the SRM, assuming no additional weirdness.  */
 static struct irq_chip srm_irq_type = {
         .name           = "SRM",
-        .unmask         = srm_enable_irq,
-        .mask           = srm_disable_irq,
-        .mask_ack       = srm_disable_irq,
+        .irq_unmask     = srm_enable_irq,
+        .irq_mask       = srm_disable_irq,
+        .irq_mask_ack   = srm_disable_irq,
 };
 
 void __init
@@ -52,7 +52,7 @@ init_srm_irqs(long max, unsigned long ignore_mask)
                 if (i < 64 && ((ignore_mask >> i) & 1))
                         continue;
                 set_irq_chip_and_handler(i, &srm_irq_type, handle_level_irq);
-                irq_to_desc(i)->status |= IRQ_LEVEL;
+                irq_set_status_flags(i, IRQ_LEVEL);
         }
 }
 
diff --git a/arch/alpha/kernel/sys_alcor.c b/arch/alpha/kernel/sys_alcor.c
index 7bef61768236..88d95e872f55 100644
--- a/arch/alpha/kernel/sys_alcor.c
+++ b/arch/alpha/kernel/sys_alcor.c
@@ -44,31 +44,31 @@ alcor_update_irq_hw(unsigned long mask)
 }
 
 static inline void
-alcor_enable_irq(unsigned int irq)
+alcor_enable_irq(struct irq_data *d)
 {
-        alcor_update_irq_hw(cached_irq_mask |= 1UL << (irq - 16));
+        alcor_update_irq_hw(cached_irq_mask |= 1UL << (d->irq - 16));
 }
 
 static void
-alcor_disable_irq(unsigned int irq)
+alcor_disable_irq(struct irq_data *d)
 {
-        alcor_update_irq_hw(cached_irq_mask &= ~(1UL << (irq - 16)));
+        alcor_update_irq_hw(cached_irq_mask &= ~(1UL << (d->irq - 16)));
 }
 
 static void
-alcor_mask_and_ack_irq(unsigned int irq)
+alcor_mask_and_ack_irq(struct irq_data *d)
 {
-        alcor_disable_irq(irq);
+        alcor_disable_irq(d);
 
         /* On ALCOR/XLT, need to dismiss interrupt via GRU. */
-        *(vuip)GRU_INT_CLEAR = 1 << (irq - 16); mb();
+        *(vuip)GRU_INT_CLEAR = 1 << (d->irq - 16); mb();
         *(vuip)GRU_INT_CLEAR = 0; mb();
 }
 
 static void
-alcor_isa_mask_and_ack_irq(unsigned int irq)
+alcor_isa_mask_and_ack_irq(struct irq_data *d)
 {
-        i8259a_mask_and_ack_irq(irq);
+        i8259a_mask_and_ack_irq(d);
 
         /* On ALCOR/XLT, need to dismiss interrupt via GRU. */
         *(vuip)GRU_INT_CLEAR = 0x80000000; mb();
@@ -77,9 +77,9 @@ alcor_isa_mask_and_ack_irq(unsigned int irq)
 
 static struct irq_chip alcor_irq_type = {
         .name           = "ALCOR",
-        .unmask         = alcor_enable_irq,
-        .mask           = alcor_disable_irq,
-        .mask_ack       = alcor_mask_and_ack_irq,
+        .irq_unmask     = alcor_enable_irq,
+        .irq_mask       = alcor_disable_irq,
+        .irq_mask_ack   = alcor_mask_and_ack_irq,
 };
 
 static void
@@ -126,9 +126,9 @@ alcor_init_irq(void)
                 if (i >= 16+20 && i <= 16+30)
                         continue;
                 set_irq_chip_and_handler(i, &alcor_irq_type, handle_level_irq);
-                irq_to_desc(i)->status |= IRQ_LEVEL;
+                irq_set_status_flags(i, IRQ_LEVEL);
         }
-        i8259a_irq_type.ack = alcor_isa_mask_and_ack_irq;
+        i8259a_irq_type.irq_ack = alcor_isa_mask_and_ack_irq;
 
         init_i8259a_irqs();
         common_init_isa_dma();
diff --git a/arch/alpha/kernel/sys_cabriolet.c b/arch/alpha/kernel/sys_cabriolet.c
index b0c916493aea..57eb6307bc27 100644
--- a/arch/alpha/kernel/sys_cabriolet.c
+++ b/arch/alpha/kernel/sys_cabriolet.c
@@ -46,22 +46,22 @@ cabriolet_update_irq_hw(unsigned int irq, unsigned long mask)
 }
 
 static inline void
-cabriolet_enable_irq(unsigned int irq)
+cabriolet_enable_irq(struct irq_data *d)
 {
-        cabriolet_update_irq_hw(irq, cached_irq_mask &= ~(1UL << irq));
+        cabriolet_update_irq_hw(d->irq, cached_irq_mask &= ~(1UL << d->irq));
 }
 
 static void
-cabriolet_disable_irq(unsigned int irq)
+cabriolet_disable_irq(struct irq_data *d)
 {
-        cabriolet_update_irq_hw(irq, cached_irq_mask |= 1UL << irq);
+        cabriolet_update_irq_hw(d->irq, cached_irq_mask |= 1UL << d->irq);
 }
 
 static struct irq_chip cabriolet_irq_type = {
         .name           = "CABRIOLET",
-        .unmask         = cabriolet_enable_irq,
-        .mask           = cabriolet_disable_irq,
-        .mask_ack       = cabriolet_disable_irq,
+        .irq_unmask     = cabriolet_enable_irq,
+        .irq_mask       = cabriolet_disable_irq,
+        .irq_mask_ack   = cabriolet_disable_irq,
 };
 
 static void 
@@ -107,7 +107,7 @@ common_init_irq(void (*srm_dev_int)(unsigned long v))
                 for (i = 16; i < 35; ++i) {
                         set_irq_chip_and_handler(i, &cabriolet_irq_type,
                                 handle_level_irq);
-                        irq_to_desc(i)->status |= IRQ_LEVEL;
+                        irq_set_status_flags(i, IRQ_LEVEL);
                 }
         }
 
diff --git a/arch/alpha/kernel/sys_dp264.c b/arch/alpha/kernel/sys_dp264.c
index edad5f759ccd..481df4ecb651 100644
--- a/arch/alpha/kernel/sys_dp264.c
+++ b/arch/alpha/kernel/sys_dp264.c
@@ -98,37 +98,37 @@ tsunami_update_irq_hw(unsigned long mask)
 }
 
 static void
-dp264_enable_irq(unsigned int irq)
+dp264_enable_irq(struct irq_data *d)
 {
         spin_lock(&dp264_irq_lock);
-        cached_irq_mask |= 1UL << irq;
+        cached_irq_mask |= 1UL << d->irq;
         tsunami_update_irq_hw(cached_irq_mask);
         spin_unlock(&dp264_irq_lock);
 }
 
 static void
-dp264_disable_irq(unsigned int irq)
+dp264_disable_irq(struct irq_data *d)
 {
         spin_lock(&dp264_irq_lock);
-        cached_irq_mask &= ~(1UL << irq);
+        cached_irq_mask &= ~(1UL << d->irq);
         tsunami_update_irq_hw(cached_irq_mask);
         spin_unlock(&dp264_irq_lock);
 }
 
 static void
-clipper_enable_irq(unsigned int irq)
+clipper_enable_irq(struct irq_data *d)
 {
         spin_lock(&dp264_irq_lock);
-        cached_irq_mask |= 1UL << (irq - 16);
+        cached_irq_mask |= 1UL << (d->irq - 16);
         tsunami_update_irq_hw(cached_irq_mask);
         spin_unlock(&dp264_irq_lock);
 }
 
 static void
-clipper_disable_irq(unsigned int irq)
+clipper_disable_irq(struct irq_data *d)
 {
         spin_lock(&dp264_irq_lock);
-        cached_irq_mask &= ~(1UL << (irq - 16));
+        cached_irq_mask &= ~(1UL << (d->irq - 16));
         tsunami_update_irq_hw(cached_irq_mask);
         spin_unlock(&dp264_irq_lock);
 }
@@ -149,10 +149,11 @@ cpu_set_irq_affinity(unsigned int irq, cpumask_t affinity)
 }
 
 static int
-dp264_set_affinity(unsigned int irq, const struct cpumask *affinity)
-{ 
+dp264_set_affinity(struct irq_data *d, const struct cpumask *affinity,
+                   bool force)
+{
         spin_lock(&dp264_irq_lock);
-        cpu_set_irq_affinity(irq, *affinity);
+        cpu_set_irq_affinity(d->irq, *affinity);
         tsunami_update_irq_hw(cached_irq_mask);
         spin_unlock(&dp264_irq_lock);
 
@@ -160,10 +161,11 @@ dp264_set_affinity(unsigned int irq, const struct cpumask *affinity)
 }
 
 static int
-clipper_set_affinity(unsigned int irq, const struct cpumask *affinity)
-{ 
+clipper_set_affinity(struct irq_data *d, const struct cpumask *affinity,
+                     bool force)
+{
         spin_lock(&dp264_irq_lock);
-        cpu_set_irq_affinity(irq - 16, *affinity);
+        cpu_set_irq_affinity(d->irq - 16, *affinity);
         tsunami_update_irq_hw(cached_irq_mask);
         spin_unlock(&dp264_irq_lock);
 
@@ -171,19 +173,19 @@ clipper_set_affinity(unsigned int irq, const struct cpumask *affinity)
 }
 
 static struct irq_chip dp264_irq_type = {
-        .name           = "DP264",
-        .unmask         = dp264_enable_irq,
-        .mask           = dp264_disable_irq,
-        .mask_ack       = dp264_disable_irq,
-        .set_affinity   = dp264_set_affinity,
+        .name                   = "DP264",
+        .irq_unmask             = dp264_enable_irq,
+        .irq_mask               = dp264_disable_irq,
+        .irq_mask_ack           = dp264_disable_irq,
+        .irq_set_affinity       = dp264_set_affinity,
 };
 
 static struct irq_chip clipper_irq_type = {
-        .name           = "CLIPPER",
-        .unmask         = clipper_enable_irq,
-        .mask           = clipper_disable_irq,
-        .mask_ack       = clipper_disable_irq,
-        .set_affinity   = clipper_set_affinity,
+        .name                   = "CLIPPER",
+        .irq_unmask             = clipper_enable_irq,
+        .irq_mask               = clipper_disable_irq,
+        .irq_mask_ack           = clipper_disable_irq,
+        .irq_set_affinity       = clipper_set_affinity,
 };
 
 static void
@@ -268,8 +270,8 @@ init_tsunami_irqs(struct irq_chip * ops, int imin, int imax)
 {
         long i;
         for (i = imin; i <= imax; ++i) {
-                irq_to_desc(i)->status |= IRQ_LEVEL;
                 set_irq_chip_and_handler(i, ops, handle_level_irq);
+                irq_set_status_flags(i, IRQ_LEVEL);
         }
 }
 
diff --git a/arch/alpha/kernel/sys_eb64p.c b/arch/alpha/kernel/sys_eb64p.c
index ae5f29d127b0..402e908ffb3e 100644
--- a/arch/alpha/kernel/sys_eb64p.c
+++ b/arch/alpha/kernel/sys_eb64p.c
@@ -44,22 +44,22 @@ eb64p_update_irq_hw(unsigned int irq, unsigned long mask)
 }
 
 static inline void
-eb64p_enable_irq(unsigned int irq)
+eb64p_enable_irq(struct irq_data *d)
 {
-        eb64p_update_irq_hw(irq, cached_irq_mask &= ~(1 << irq));
+        eb64p_update_irq_hw(d->irq, cached_irq_mask &= ~(1 << d->irq));
 }
 
 static void
-eb64p_disable_irq(unsigned int irq)
+eb64p_disable_irq(struct irq_data *d)
 {
-        eb64p_update_irq_hw(irq, cached_irq_mask |= 1 << irq);
+        eb64p_update_irq_hw(d->irq, cached_irq_mask |= 1 << d->irq);
 }
 
 static struct irq_chip eb64p_irq_type = {
         .name           = "EB64P",
-        .unmask         = eb64p_enable_irq,
-        .mask           = eb64p_disable_irq,
-        .mask_ack       = eb64p_disable_irq,
+        .irq_unmask     = eb64p_enable_irq,
+        .irq_mask       = eb64p_disable_irq,
+        .irq_mask_ack   = eb64p_disable_irq,
 };
 
 static void 
@@ -118,9 +118,9 @@ eb64p_init_irq(void)
         init_i8259a_irqs();
 
         for (i = 16; i < 32; ++i) {
-                irq_to_desc(i)->status |= IRQ_LEVEL;
                 set_irq_chip_and_handler(i, &eb64p_irq_type, handle_level_irq);
-        }               
+                irq_set_status_flags(i, IRQ_LEVEL);
+        }
 
         common_init_isa_dma();
         setup_irq(16+5, &isa_cascade_irqaction);
diff --git a/arch/alpha/kernel/sys_eiger.c b/arch/alpha/kernel/sys_eiger.c
index 1121bc5c6c6c..0b44a54c1522 100644
--- a/arch/alpha/kernel/sys_eiger.c
+++ b/arch/alpha/kernel/sys_eiger.c
@@ -51,16 +51,18 @@ eiger_update_irq_hw(unsigned long irq, unsigned long mask)
 }
 
 static inline void
-eiger_enable_irq(unsigned int irq)
+eiger_enable_irq(struct irq_data *d)
 {
+        unsigned int irq = d->irq;
         unsigned long mask;
         mask = (cached_irq_mask[irq >= 64] &= ~(1UL << (irq & 63)));
         eiger_update_irq_hw(irq, mask);
 }
 
 static void
-eiger_disable_irq(unsigned int irq)
+eiger_disable_irq(struct irq_data *d)
 {
+        unsigned int irq = d->irq;
         unsigned long mask;
         mask = (cached_irq_mask[irq >= 64] |= 1UL << (irq & 63));
         eiger_update_irq_hw(irq, mask);
@@ -68,9 +70,9 @@ eiger_disable_irq(unsigned int irq)
 
 static struct irq_chip eiger_irq_type = {
         .name           = "EIGER",
-        .unmask         = eiger_enable_irq,
-        .mask           = eiger_disable_irq,
-        .mask_ack       = eiger_disable_irq,
+        .irq_unmask     = eiger_enable_irq,
+        .irq_mask       = eiger_disable_irq,
+        .irq_mask_ack   = eiger_disable_irq,
 };
 
 static void
@@ -136,8 +138,8 @@ eiger_init_irq(void)
         init_i8259a_irqs();
 
         for (i = 16; i < 128; ++i) {
-                irq_to_desc(i)->status |= IRQ_LEVEL;
                 set_irq_chip_and_handler(i, &eiger_irq_type, handle_level_irq);
+                irq_set_status_flags(i, IRQ_LEVEL);
         }
 }
 
diff --git a/arch/alpha/kernel/sys_jensen.c b/arch/alpha/kernel/sys_jensen.c
index 34f55e03d331..00341b75c8b2 100644
--- a/arch/alpha/kernel/sys_jensen.c
+++ b/arch/alpha/kernel/sys_jensen.c
@@ -63,34 +63,34 @@
  */
 
 static void
-jensen_local_enable(unsigned int irq)
+jensen_local_enable(struct irq_data *d)
 {
         /* the parport is really hw IRQ 1, silly Jensen.  */
-        if (irq == 7)
-                i8259a_enable_irq(1);
+        if (d->irq == 7)
+                i8259a_enable_irq(d);
 }
 
 static void
-jensen_local_disable(unsigned int irq)
+jensen_local_disable(struct irq_data *d)
 {
         /* the parport is really hw IRQ 1, silly Jensen.  */
-        if (irq == 7)
-                i8259a_disable_irq(1);
+        if (d->irq == 7)
+                i8259a_disable_irq(d);
 }
 
 static void
-jensen_local_mask_ack(unsigned int irq)
+jensen_local_mask_ack(struct irq_data *d)
 {
         /* the parport is really hw IRQ 1, silly Jensen.  */
-        if (irq == 7)
-                i8259a_mask_and_ack_irq(1);
+        if (d->irq == 7)
+                i8259a_mask_and_ack_irq(d);
 }
 
 static struct irq_chip jensen_local_irq_type = {
         .name           = "LOCAL",
-        .unmask         = jensen_local_enable,
-        .mask           = jensen_local_disable,
-        .mask_ack       = jensen_local_mask_ack,
+        .irq_unmask     = jensen_local_enable,
+        .irq_mask       = jensen_local_disable,
+        .irq_mask_ack   = jensen_local_mask_ack,
 };
 
 static void 
diff --git a/arch/alpha/kernel/sys_marvel.c b/arch/alpha/kernel/sys_marvel.c
index 2bfc9f1b1ddc..e61910734e41 100644
--- a/arch/alpha/kernel/sys_marvel.c
+++ b/arch/alpha/kernel/sys_marvel.c
@@ -104,9 +104,10 @@ io7_get_irq_ctl(unsigned int irq, struct io7 **pio7)
 }
 
 static void
-io7_enable_irq(unsigned int irq)
+io7_enable_irq(struct irq_data *d)
 {
         volatile unsigned long *ctl;
+        unsigned int irq = d->irq;
         struct io7 *io7;
 
         ctl = io7_get_irq_ctl(irq, &io7);
@@ -115,7 +116,7 @@ io7_enable_irq(unsigned int irq)
                        __func__, irq);
                 return;
         }
-                
+
         spin_lock(&io7->irq_lock);
         *ctl |= 1UL << 24;
         mb();
@@ -124,9 +125,10 @@ io7_enable_irq(unsigned int irq)
 }
 
 static void
-io7_disable_irq(unsigned int irq)
+io7_disable_irq(struct irq_data *d)
 {
         volatile unsigned long *ctl;
+        unsigned int irq = d->irq;
         struct io7 *io7;
 
         ctl = io7_get_irq_ctl(irq, &io7);
@@ -135,7 +137,7 @@ io7_disable_irq(unsigned int irq)
                        __func__, irq);
                 return;
         }
-                
+
         spin_lock(&io7->irq_lock);
         *ctl &= ~(1UL << 24);
         mb();
@@ -144,35 +146,29 @@ io7_disable_irq(unsigned int irq)
 }
 
 static void
-marvel_irq_noop(unsigned int irq) 
-{ 
-        return; 
-}
-
-static unsigned int
-marvel_irq_noop_return(unsigned int irq) 
-{ 
-        return 0; 
+marvel_irq_noop(struct irq_data *d)
+{
+        return;
 }
 
 static struct irq_chip marvel_legacy_irq_type = {
         .name           = "LEGACY",
-        .mask           = marvel_irq_noop,
-        .unmask         = marvel_irq_noop,
+        .irq_mask       = marvel_irq_noop,
+        .irq_unmask     = marvel_irq_noop,
 };
 
 static struct irq_chip io7_lsi_irq_type = {
         .name           = "LSI",
-        .unmask         = io7_enable_irq,
-        .mask           = io7_disable_irq,
-        .mask_ack       = io7_disable_irq,
+        .irq_unmask     = io7_enable_irq,
+        .irq_mask       = io7_disable_irq,
+        .irq_mask_ack   = io7_disable_irq,
 };
 
 static struct irq_chip io7_msi_irq_type = {
         .name           = "MSI",
-        .unmask         = io7_enable_irq,
-        .mask           = io7_disable_irq,
-        .ack            = marvel_irq_noop,
+        .irq_unmask     = io7_enable_irq,
+        .irq_mask       = io7_disable_irq,
+        .irq_ack        = marvel_irq_noop,
 };
 
 static void
@@ -280,8 +276,8 @@ init_io7_irqs(struct io7 *io7,
 
         /* Set up the lsi irqs.  */
         for (i = 0; i < 128; ++i) {
-                irq_to_desc(base + i)->status |= IRQ_LEVEL;
                 set_irq_chip_and_handler(base + i, lsi_ops, handle_level_irq);
+                irq_set_status_flags(i, IRQ_LEVEL);
         }
 
         /* Disable the implemented irqs in hardware.  */
@@ -294,8 +290,8 @@ init_io7_irqs(struct io7 *io7,
 
         /* Set up the msi irqs.  */
         for (i = 128; i < (128 + 512); ++i) {
-                irq_to_desc(base + i)->status |= IRQ_LEVEL;
                 set_irq_chip_and_handler(base + i, msi_ops, handle_level_irq);
+                irq_set_status_flags(i, IRQ_LEVEL);
         }
 
         for (i = 0; i < 16; ++i)
diff --git a/arch/alpha/kernel/sys_mikasa.c b/arch/alpha/kernel/sys_mikasa.c
index bcc1639e8efb..cf7f43dd3147 100644
--- a/arch/alpha/kernel/sys_mikasa.c
+++ b/arch/alpha/kernel/sys_mikasa.c
@@ -43,22 +43,22 @@ mikasa_update_irq_hw(int mask)
 }
 
 static inline void
-mikasa_enable_irq(unsigned int irq)
+mikasa_enable_irq(struct irq_data *d)
 {
-        mikasa_update_irq_hw(cached_irq_mask |= 1 << (irq - 16));
+        mikasa_update_irq_hw(cached_irq_mask |= 1 << (d->irq - 16));
 }
 
 static void
-mikasa_disable_irq(unsigned int irq)
+mikasa_disable_irq(struct irq_data *d)
 {
-        mikasa_update_irq_hw(cached_irq_mask &= ~(1 << (irq - 16)));
+        mikasa_update_irq_hw(cached_irq_mask &= ~(1 << (d->irq - 16)));
 }
 
 static struct irq_chip mikasa_irq_type = {
         .name           = "MIKASA",
-        .unmask         = mikasa_enable_irq,
-        .mask           = mikasa_disable_irq,
-        .mask_ack       = mikasa_disable_irq,
+        .irq_unmask     = mikasa_enable_irq,
+        .irq_mask       = mikasa_disable_irq,
+        .irq_mask_ack   = mikasa_disable_irq,
 };
 
 static void 
@@ -98,8 +98,8 @@ mikasa_init_irq(void)
         mikasa_update_irq_hw(0);
 
         for (i = 16; i < 32; ++i) {
-                irq_to_desc(i)->status |= IRQ_LEVEL;
                 set_irq_chip_and_handler(i, &mikasa_irq_type, handle_level_irq);
+                irq_set_status_flags(i, IRQ_LEVEL);
         }
 
         init_i8259a_irqs();
diff --git a/arch/alpha/kernel/sys_noritake.c b/arch/alpha/kernel/sys_noritake.c
index e88f4ae1260e..92bc188e94a9 100644
--- a/arch/alpha/kernel/sys_noritake.c
+++ b/arch/alpha/kernel/sys_noritake.c
@@ -48,22 +48,22 @@ noritake_update_irq_hw(int irq, int mask)
 }
 
 static void
-noritake_enable_irq(unsigned int irq)
+noritake_enable_irq(struct irq_data *d)
 {
-        noritake_update_irq_hw(irq, cached_irq_mask |= 1 << (irq - 16));
+        noritake_update_irq_hw(d->irq, cached_irq_mask |= 1 << (d->irq - 16));
 }
 
 static void
-noritake_disable_irq(unsigned int irq)
+noritake_disable_irq(struct irq_data *d)
 {
-        noritake_update_irq_hw(irq, cached_irq_mask &= ~(1 << (irq - 16)));
+        noritake_update_irq_hw(d->irq, cached_irq_mask &= ~(1 << (d->irq - 16)));
 }
 
 static struct irq_chip noritake_irq_type = {
         .name           = "NORITAKE",
-        .unmask         = noritake_enable_irq,
-        .mask           = noritake_disable_irq,
-        .mask_ack       = noritake_disable_irq,
+        .irq_unmask     = noritake_enable_irq,
+        .irq_mask       = noritake_disable_irq,
+        .irq_mask_ack   = noritake_disable_irq,
 };
 
 static void 
@@ -127,8 +127,8 @@ noritake_init_irq(void)
         outw(0, 0x54c);
 
         for (i = 16; i < 48; ++i) {
-                irq_to_desc(i)->status |= IRQ_LEVEL;
                 set_irq_chip_and_handler(i, &noritake_irq_type, handle_level_irq);
+                irq_set_status_flags(i, IRQ_LEVEL);
         }
 
         init_i8259a_irqs();
diff --git a/arch/alpha/kernel/sys_rawhide.c b/arch/alpha/kernel/sys_rawhide.c
index 6a51364dd1cc..936d4140ed5f 100644
--- a/arch/alpha/kernel/sys_rawhide.c
+++ b/arch/alpha/kernel/sys_rawhide.c
@@ -56,9 +56,10 @@ rawhide_update_irq_hw(int hose, int mask)
   (((h) < MCPCIA_MAX_HOSES) && (cached_irq_masks[(h)] != 0))
 
 static inline void 
-rawhide_enable_irq(unsigned int irq)
+rawhide_enable_irq(struct irq_data *d)
 {
         unsigned int mask, hose;
+        unsigned int irq = d->irq;
 
         irq -= 16;
         hose = irq / 24;
@@ -76,9 +77,10 @@ rawhide_enable_irq(unsigned int irq)
 }
 
 static void 
-rawhide_disable_irq(unsigned int irq)
+rawhide_disable_irq(struct irq_data *d)
 {
         unsigned int mask, hose;
+        unsigned int irq = d->irq;
 
         irq -= 16;
         hose = irq / 24;
@@ -96,9 +98,10 @@ rawhide_disable_irq(unsigned int irq)
 }
 
 static void
-rawhide_mask_and_ack_irq(unsigned int irq)
+rawhide_mask_and_ack_irq(struct irq_data *d)
 {
         unsigned int mask, mask1, hose;
+        unsigned int irq = d->irq;
 
         irq -= 16;
         hose = irq / 24;
@@ -123,9 +126,9 @@ rawhide_mask_and_ack_irq(unsigned int irq)
 
 static struct irq_chip rawhide_irq_type = {
         .name           = "RAWHIDE",
-        .unmask         = rawhide_enable_irq,
-        .mask           = rawhide_disable_irq,
-        .mask_ack       = rawhide_mask_and_ack_irq,
+        .irq_unmask     = rawhide_enable_irq,
+        .irq_mask       = rawhide_disable_irq,
+        .irq_mask_ack   = rawhide_mask_and_ack_irq,
 };
 
 static void 
@@ -177,8 +180,8 @@ rawhide_init_irq(void)
         }
 
         for (i = 16; i < 128; ++i) {
-                irq_to_desc(i)->status |= IRQ_LEVEL;
                 set_irq_chip_and_handler(i, &rawhide_irq_type, handle_level_irq);
+                irq_set_status_flags(i, IRQ_LEVEL);
         }
 
         init_i8259a_irqs();
diff --git a/arch/alpha/kernel/sys_rx164.c b/arch/alpha/kernel/sys_rx164.c
index 89e7e37ec84c..cea22a62913b 100644
--- a/arch/alpha/kernel/sys_rx164.c
+++ b/arch/alpha/kernel/sys_rx164.c
@@ -47,22 +47,22 @@ rx164_update_irq_hw(unsigned long mask)
 }
 
 static inline void
-rx164_enable_irq(unsigned int irq)
+rx164_enable_irq(struct irq_data *d)
 {
-        rx164_update_irq_hw(cached_irq_mask |= 1UL << (irq - 16));
+        rx164_update_irq_hw(cached_irq_mask |= 1UL << (d->irq - 16));
 }
 
 static void
-rx164_disable_irq(unsigned int irq)
+rx164_disable_irq(struct irq_data *d)
 {
-        rx164_update_irq_hw(cached_irq_mask &= ~(1UL << (irq - 16)));
+        rx164_update_irq_hw(cached_irq_mask &= ~(1UL << (d->irq - 16)));
 }
 
 static struct irq_chip rx164_irq_type = {
         .name           = "RX164",
-        .unmask         = rx164_enable_irq,
-        .mask           = rx164_disable_irq,
-        .mask_ack       = rx164_disable_irq,
+        .irq_unmask     = rx164_enable_irq,
+        .irq_mask       = rx164_disable_irq,
+        .irq_mask_ack   = rx164_disable_irq,
 };
 
 static void 
@@ -99,8 +99,8 @@ rx164_init_irq(void)
 
         rx164_update_irq_hw(0);
         for (i = 16; i < 40; ++i) {
-                irq_to_desc(i)->status |= IRQ_LEVEL;
                 set_irq_chip_and_handler(i, &rx164_irq_type, handle_level_irq);
+                irq_set_status_flags(i, IRQ_LEVEL);
         }
 
         init_i8259a_irqs();
diff --git a/arch/alpha/kernel/sys_sable.c b/arch/alpha/kernel/sys_sable.c
index 5c4423d1b06c..a349538aabc9 100644
--- a/arch/alpha/kernel/sys_sable.c
+++ b/arch/alpha/kernel/sys_sable.c
@@ -443,11 +443,11 @@ lynx_swizzle(struct pci_dev *dev, u8 *pinp)
 /* GENERIC irq routines */
 
 static inline void
-sable_lynx_enable_irq(unsigned int irq)
+sable_lynx_enable_irq(struct irq_data *d)
 {
         unsigned long bit, mask;
 
-        bit = sable_lynx_irq_swizzle->irq_to_mask[irq];
+        bit = sable_lynx_irq_swizzle->irq_to_mask[d->irq];
         spin_lock(&sable_lynx_irq_lock);
         mask = sable_lynx_irq_swizzle->shadow_mask &= ~(1UL << bit);
         sable_lynx_irq_swizzle->update_irq_hw(bit, mask);
@@ -459,11 +459,11 @@ sable_lynx_enable_irq(unsigned int irq)
 }
 
 static void
-sable_lynx_disable_irq(unsigned int irq)
+sable_lynx_disable_irq(struct irq_data *d)
 {
         unsigned long bit, mask;
 
-        bit = sable_lynx_irq_swizzle->irq_to_mask[irq];
+        bit = sable_lynx_irq_swizzle->irq_to_mask[d->irq];
         spin_lock(&sable_lynx_irq_lock);
         mask = sable_lynx_irq_swizzle->shadow_mask |= 1UL << bit;
         sable_lynx_irq_swizzle->update_irq_hw(bit, mask);
@@ -475,11 +475,11 @@ sable_lynx_disable_irq(unsigned int irq)
 }
 
 static void
-sable_lynx_mask_and_ack_irq(unsigned int irq)
+sable_lynx_mask_and_ack_irq(struct irq_data *d)
 {
         unsigned long bit, mask;
 
-        bit = sable_lynx_irq_swizzle->irq_to_mask[irq];
+        bit = sable_lynx_irq_swizzle->irq_to_mask[d->irq];
         spin_lock(&sable_lynx_irq_lock);
         mask = sable_lynx_irq_swizzle->shadow_mask |= 1UL << bit;
         sable_lynx_irq_swizzle->update_irq_hw(bit, mask);
@@ -489,9 +489,9 @@ sable_lynx_mask_and_ack_irq(unsigned int irq)
 
 static struct irq_chip sable_lynx_irq_type = {
         .name           = "SABLE/LYNX",
-        .unmask         = sable_lynx_enable_irq,
-        .mask           = sable_lynx_disable_irq,
-        .mask_ack       = sable_lynx_mask_and_ack_irq,
+        .irq_unmask     = sable_lynx_enable_irq,
+        .irq_mask       = sable_lynx_disable_irq,
+        .irq_mask_ack   = sable_lynx_mask_and_ack_irq,
 };
 
 static void 
@@ -518,9 +518,9 @@ sable_lynx_init_irq(int nr_of_irqs)
         long i;
 
         for (i = 0; i < nr_of_irqs; ++i) {
-                irq_to_desc(i)->status |= IRQ_LEVEL;
                 set_irq_chip_and_handler(i, &sable_lynx_irq_type,
                         handle_level_irq);
+                irq_set_status_flags(i, IRQ_LEVEL);
         }
 
         common_init_isa_dma();
diff --git a/arch/alpha/kernel/sys_takara.c b/arch/alpha/kernel/sys_takara.c
index f8a1e8a862fb..42a5331f13c4 100644
--- a/arch/alpha/kernel/sys_takara.c
+++ b/arch/alpha/kernel/sys_takara.c
@@ -45,16 +45,18 @@ takara_update_irq_hw(unsigned long irq, unsigned long mask)
 }
 
 static inline void
-takara_enable_irq(unsigned int irq)
+takara_enable_irq(struct irq_data *d)
 {
+        unsigned int irq = d->irq;
         unsigned long mask;
         mask = (cached_irq_mask[irq >= 64] &= ~(1UL << (irq & 63)));
         takara_update_irq_hw(irq, mask);
 }
 
 static void
-takara_disable_irq(unsigned int irq)
+takara_disable_irq(struct irq_data *d)
 {
+        unsigned int irq = d->irq;
         unsigned long mask;
         mask = (cached_irq_mask[irq >= 64] |= 1UL << (irq & 63));
         takara_update_irq_hw(irq, mask);
@@ -62,9 +64,9 @@ takara_disable_irq(unsigned int irq)
 
 static struct irq_chip takara_irq_type = {
         .name           = "TAKARA",
-        .unmask         = takara_enable_irq,
-        .mask           = takara_disable_irq,
-        .mask_ack       = takara_disable_irq,
+        .irq_unmask     = takara_enable_irq,
+        .irq_mask       = takara_disable_irq,
+        .irq_mask_ack   = takara_disable_irq,
 };
 
 static void
@@ -136,8 +138,8 @@ takara_init_irq(void)
                 takara_update_irq_hw(i, -1);
 
         for (i = 16; i < 128; ++i) {
-                irq_to_desc(i)->status |= IRQ_LEVEL;
                 set_irq_chip_and_handler(i, &takara_irq_type, handle_level_irq);
+                irq_set_status_flags(i, IRQ_LEVEL);
         }
 
         common_init_isa_dma();
diff --git a/arch/alpha/kernel/sys_titan.c b/arch/alpha/kernel/sys_titan.c
index e02494bf5ef3..f6c108a3d673 100644
--- a/arch/alpha/kernel/sys_titan.c
+++ b/arch/alpha/kernel/sys_titan.c
@@ -112,8 +112,9 @@ titan_update_irq_hw(unsigned long mask)
 }
 
 static inline void
-titan_enable_irq(unsigned int irq)
+titan_enable_irq(struct irq_data *d)
 {
+        unsigned int irq = d->irq;
         spin_lock(&titan_irq_lock);
         titan_cached_irq_mask |= 1UL << (irq - 16);
         titan_update_irq_hw(titan_cached_irq_mask);
@@ -121,8 +122,9 @@ titan_enable_irq(unsigned int irq)
 }
 
 static inline void
-titan_disable_irq(unsigned int irq)
+titan_disable_irq(struct irq_data *d)
 {
+        unsigned int irq = d->irq;
         spin_lock(&titan_irq_lock);
         titan_cached_irq_mask &= ~(1UL << (irq - 16));
         titan_update_irq_hw(titan_cached_irq_mask);
@@ -144,7 +146,8 @@ titan_cpu_set_irq_affinity(unsigned int irq, cpumask_t affinity)
 }
 
 static int
-titan_set_irq_affinity(unsigned int irq, const struct cpumask *affinity)
+titan_set_irq_affinity(struct irq_data *d, const struct cpumask *affinity,
+                       bool force)
 { 
         spin_lock(&titan_irq_lock);
         titan_cpu_set_irq_affinity(irq - 16, *affinity);
@@ -175,17 +178,17 @@ init_titan_irqs(struct irq_chip * ops, int imin, int imax)
 {
         long i;
         for (i = imin; i <= imax; ++i) {
-                irq_to_desc(i)->status |= IRQ_LEVEL;
                 set_irq_chip_and_handler(i, ops, handle_level_irq);
+                irq_set_status_flags(i, IRQ_LEVEL);
         }
 }
 
 static struct irq_chip titan_irq_type = {
-       .name            = "TITAN",
-       .unmask          = titan_enable_irq,
-       .mask            = titan_disable_irq,
-       .mask_ack        = titan_disable_irq,
-       .set_affinity    = titan_set_irq_affinity,
+       .name                    = "TITAN",
+       .irq_unmask              = titan_enable_irq,
+       .irq_mask                = titan_disable_irq,
+       .irq_mask_ack            = titan_disable_irq,
+       .irq_set_affinity        = titan_set_irq_affinity,
 };
 
 static irqreturn_t
diff --git a/arch/alpha/kernel/sys_wildfire.c b/arch/alpha/kernel/sys_wildfire.c
index eec52594d410..ca60a387ef0a 100644
--- a/arch/alpha/kernel/sys_wildfire.c
+++ b/arch/alpha/kernel/sys_wildfire.c
@@ -104,10 +104,12 @@ wildfire_init_irq_hw(void)
 }
 
 static void
-wildfire_enable_irq(unsigned int irq)
+wildfire_enable_irq(struct irq_data *d)
 {
+        unsigned int irq = d->irq;
+
         if (irq < 16)
-                i8259a_enable_irq(irq);
+                i8259a_enable_irq(d);
 
         spin_lock(&wildfire_irq_lock);
         set_bit(irq, &cached_irq_mask);
@@ -116,10 +118,12 @@ wildfire_enable_irq(unsigned int irq)
 }
 
 static void
-wildfire_disable_irq(unsigned int irq)
+wildfire_disable_irq(struct irq_data *d)
 {
+        unsigned int irq = d->irq;
+
         if (irq < 16)
-                i8259a_disable_irq(irq);
+                i8259a_disable_irq(d);
 
         spin_lock(&wildfire_irq_lock);
         clear_bit(irq, &cached_irq_mask);
@@ -128,10 +132,12 @@ wildfire_disable_irq(unsigned int irq)
 }
 
 static void
-wildfire_mask_and_ack_irq(unsigned int irq)
+wildfire_mask_and_ack_irq(struct irq_data *d)
 {
+        unsigned int irq = d->irq;
+
         if (irq < 16)
-                i8259a_mask_and_ack_irq(irq);
+                i8259a_mask_and_ack_irq(d);
 
         spin_lock(&wildfire_irq_lock);
         clear_bit(irq, &cached_irq_mask);
@@ -141,9 +147,9 @@ wildfire_mask_and_ack_irq(unsigned int irq)
 
 static struct irq_chip wildfire_irq_type = {
         .name           = "WILDFIRE",
-        .unmask         = wildfire_enable_irq,
-        .mask           = wildfire_disable_irq,
-        .mask_ack       = wildfire_mask_and_ack_irq,
+        .irq_unmask     = wildfire_enable_irq,
+        .irq_mask       = wildfire_disable_irq,
+        .irq_mask_ack   = wildfire_mask_and_ack_irq,
 };
 
 static void __init
@@ -177,21 +183,21 @@ wildfire_init_irq_per_pca(int qbbno, int pcano)
         for (i = 0; i < 16; ++i) {
                 if (i == 2)
                         continue;
-                irq_to_desc(i+irq_bias)->status |= IRQ_LEVEL;
                 set_irq_chip_and_handler(i+irq_bias, &wildfire_irq_type,
                         handle_level_irq);
+                irq_set_status_flags(i + irq_bias, IRQ_LEVEL);
         }
 
-        irq_to_desc(36+irq_bias)->status |= IRQ_LEVEL;
         set_irq_chip_and_handler(36+irq_bias, &wildfire_irq_type,
                 handle_level_irq);
+        irq_set_status_flags(36 + irq_bias, IRQ_LEVEL);
         for (i = 40; i < 64; ++i) {
-                irq_to_desc(i+irq_bias)->status |= IRQ_LEVEL;
                 set_irq_chip_and_handler(i+irq_bias, &wildfire_irq_type,
                         handle_level_irq);
+                irq_set_status_flags(i + irq_bias, IRQ_LEVEL);
         }
 
-        setup_irq(32+irq_bias, &isa_enable);    
+        setup_irq(32+irq_bias, &isa_enable);
 }
 
 static void __init
diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig
index 778655f0257a..ea5ee4d067f3 100644
--- a/arch/arm/common/Kconfig
+++ b/arch/arm/common/Kconfig
@@ -6,6 +6,8 @@ config ARM_VIC
 
 config ARM_VIC_NR
         int
+        default 4 if ARCH_S5PV210
+        default 3 if ARCH_S5P6442 || ARCH_S5PC100
         default 2
         depends on ARM_VIC
         help
diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index 3a0893a76a3b..bf13b814c1b8 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -15,10 +15,6 @@ struct meminfo;
 struct sys_timer;
 
 struct machine_desc {
-        /*
-         * Note! The first two elements are used
-         * by assembler code in head.S, head-common.S
-         */
         unsigned int            nr;             /* architecture number  */
         const char              *name;          /* architecture name    */
         unsigned long           boot_params;    /* tagged list          */
diff --git a/arch/arm/include/asm/pgalloc.h b/arch/arm/include/asm/pgalloc.h
index 9763be04f77e..22de005f159c 100644
--- a/arch/arm/include/asm/pgalloc.h
+++ b/arch/arm/include/asm/pgalloc.h
@@ -10,6 +10,8 @@
 #ifndef _ASMARM_PGALLOC_H
 #define _ASMARM_PGALLOC_H
 
+#include <linux/pagemap.h>
+
 #include <asm/domain.h>
 #include <asm/pgtable-hwdef.h>
 #include <asm/processor.h>
diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c
index d600bd350704..44b84fe6e1b0 100644
--- a/arch/arm/kernel/hw_breakpoint.c
+++ b/arch/arm/kernel/hw_breakpoint.c
@@ -836,9 +836,11 @@ static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr,
 /*
  * One-time initialisation.
  */
-static void reset_ctrl_regs(void *unused)
+static void reset_ctrl_regs(void *info)
 {
-        int i;
+        int i, cpu = smp_processor_id();
+        u32 dbg_power;
+        cpumask_t *cpumask = info;
 
         /*
          * v7 debug contains save and restore registers so that debug state
@@ -850,6 +852,17 @@ static void reset_ctrl_regs(void *unused)
          */
         if (debug_arch >= ARM_DEBUG_ARCH_V7_ECP14) {
                 /*
+                 * Ensure sticky power-down is clear (i.e. debug logic is
+                 * powered up).
+                 */
+                asm volatile("mrc p14, 0, %0, c1, c5, 4" : "=r" (dbg_power));
+                if ((dbg_power & 0x1) == 0) {
+                        pr_warning("CPU %d debug is powered down!\n", cpu);
+                        cpumask_or(cpumask, cpumask, cpumask_of(cpu));
+                        return;
+                }
+
+                /*
                  * Unconditionally clear the lock by writing a value
                  * other than 0xC5ACCE55 to the access register.
                  */
@@ -887,6 +900,7 @@ static struct notifier_block __cpuinitdata dbg_reset_nb = {
 static int __init arch_hw_breakpoint_init(void)
 {
         u32 dscr;
+        cpumask_t cpumask = { CPU_BITS_NONE };
 
         debug_arch = get_debug_arch();
 
@@ -911,7 +925,13 @@ static int __init arch_hw_breakpoint_init(void)
          * Reset the breakpoint resources. We assume that a halting
          * debugger will leave the world in a nice state for us.
          */
-        on_each_cpu(reset_ctrl_regs, NULL, 1);
+        on_each_cpu(reset_ctrl_regs, &cpumask, 1);
+        if (!cpumask_empty(&cpumask)) {
+                core_num_brps = 0;
+                core_num_reserved_brps = 0;
+                core_num_wrps = 0;
+                return 0;
+        }
 
         ARM_DBG_READ(c1, 0, dscr);
         if (dscr & ARM_DSCR_HDBGEN) {
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index 19c6816db61e..b13e70f63d71 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -996,10 +996,10 @@ static int ptrace_gethbpregs(struct task_struct *tsk, long num,
                 while (!(arch_ctrl.len & 0x1))
                         arch_ctrl.len >>= 1;
 
-                if (idx & 0x1)
-                        reg = encode_ctrl_reg(arch_ctrl);
-                else
+                if (num & 0x1)
                         reg = bp->attr.bp_addr;
+                else
+                        reg = encode_ctrl_reg(arch_ctrl);
         }
 
 put:
diff --git a/arch/arm/mach-davinci/cpufreq.c b/arch/arm/mach-davinci/cpufreq.c
index 343de73161fa..4a68c2b1ec11 100644
--- a/arch/arm/mach-davinci/cpufreq.c
+++ b/arch/arm/mach-davinci/cpufreq.c
@@ -132,7 +132,7 @@ out:
         return ret;
 }
 
-static int __init davinci_cpu_init(struct cpufreq_policy *policy)
+static int davinci_cpu_init(struct cpufreq_policy *policy)
 {
         int result = 0;
         struct davinci_cpufreq_config *pdata = cpufreq.dev->platform_data;
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index 9eec63070e0c..beda8a4133a0 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -480,8 +480,15 @@ static struct platform_device da850_mcasp_device = {
         .resource       = da850_mcasp_resources,
 };
 
+struct platform_device davinci_pcm_device = {
+        .name   = "davinci-pcm-audio",
+        .id     = -1,
+};
+
 void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
 {
+        platform_device_register(&davinci_pcm_device);
+
         /* DA830/OMAP-L137 has 3 instances of McASP */
         if (cpu_is_davinci_da830() && id == 1) {
                 da830_mcasp1_device.dev.platform_data = pdata;
diff --git a/arch/arm/mach-davinci/gpio-tnetv107x.c b/arch/arm/mach-davinci/gpio-tnetv107x.c
index d10298620e2c..3fa3e2867e19 100644
--- a/arch/arm/mach-davinci/gpio-tnetv107x.c
+++ b/arch/arm/mach-davinci/gpio-tnetv107x.c
@@ -58,7 +58,7 @@ static int tnetv107x_gpio_request(struct gpio_chip *chip, unsigned offset)
 
         spin_lock_irqsave(&ctlr->lock, flags);
 
-        gpio_reg_set_bit(&regs->enable, gpio);
+        gpio_reg_set_bit(regs->enable, gpio);
 
         spin_unlock_irqrestore(&ctlr->lock, flags);
 
@@ -74,7 +74,7 @@ static void tnetv107x_gpio_free(struct gpio_chip *chip, unsigned offset)
 
         spin_lock_irqsave(&ctlr->lock, flags);
 
-        gpio_reg_clear_bit(&regs->enable, gpio);
+        gpio_reg_clear_bit(regs->enable, gpio);
 
         spin_unlock_irqrestore(&ctlr->lock, flags);
 }
@@ -88,7 +88,7 @@ static int tnetv107x_gpio_dir_in(struct gpio_chip *chip, unsigned offset)
 
         spin_lock_irqsave(&ctlr->lock, flags);
 
-        gpio_reg_set_bit(&regs->direction, gpio);
+        gpio_reg_set_bit(regs->direction, gpio);
 
         spin_unlock_irqrestore(&ctlr->lock, flags);
 
@@ -106,11 +106,11 @@ static int tnetv107x_gpio_dir_out(struct gpio_chip *chip,
         spin_lock_irqsave(&ctlr->lock, flags);
 
         if (value)
-                gpio_reg_set_bit(&regs->data_out, gpio);
+                gpio_reg_set_bit(regs->data_out, gpio);
         else
-                gpio_reg_clear_bit(&regs->data_out, gpio);
+                gpio_reg_clear_bit(regs->data_out, gpio);
 
-        gpio_reg_clear_bit(&regs->direction, gpio);
+        gpio_reg_clear_bit(regs->direction, gpio);
 
         spin_unlock_irqrestore(&ctlr->lock, flags);
 
@@ -124,7 +124,7 @@ static int tnetv107x_gpio_get(struct gpio_chip *chip, unsigned offset)
         unsigned gpio = chip->base + offset;
         int ret;
 
-        ret = gpio_reg_get_bit(&regs->data_in, gpio);
+        ret = gpio_reg_get_bit(regs->data_in, gpio);
 
         return ret ? 1 : 0;
 }
@@ -140,9 +140,9 @@ static void tnetv107x_gpio_set(struct gpio_chip *chip,
         spin_lock_irqsave(&ctlr->lock, flags);
 
         if (value)
-                gpio_reg_set_bit(&regs->data_out, gpio);
+                gpio_reg_set_bit(regs->data_out, gpio);
         else
-                gpio_reg_clear_bit(&regs->data_out, gpio);
+                gpio_reg_clear_bit(regs->data_out, gpio);
 
         spin_unlock_irqrestore(&ctlr->lock, flags);
 }
diff --git a/arch/arm/mach-davinci/include/mach/clkdev.h b/arch/arm/mach-davinci/include/mach/clkdev.h
index 730c49d1ebd8..14a504887189 100644
--- a/arch/arm/mach-davinci/include/mach/clkdev.h
+++ b/arch/arm/mach-davinci/include/mach/clkdev.h
@@ -1,6 +1,8 @@
 #ifndef __MACH_CLKDEV_H
 #define __MACH_CLKDEV_H
 
+struct clk;
+
 static inline int __clk_get(struct clk *clk)
 {
         return 1;
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index b6752ac5b97e..20c5dbea8953 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -23,6 +23,7 @@
 #include <linux/gpio.h>
 #include <linux/input.h>
 #include <linux/gpio_keys.h>
+#include <linux/opp.h>
 
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
@@ -45,10 +46,12 @@
 #include <plat/gpmc.h>
 #include <plat/nand.h>
 #include <plat/usb.h>
+#include <plat/omap_device.h>
 
 #include "mux.h"
 #include "hsmmc.h"
 #include "timer-gp.h"
+#include "pm.h"
 
 #define NAND_BLOCK_SIZE         SZ_128K
 
@@ -603,6 +606,52 @@ static struct omap_musb_board_data musb_board_data = {
         .power                  = 100,
 };
 
+static void __init beagle_opp_init(void)
+{
+        int r = 0;
+
+        /* Initialize the omap3 opp table */
+        if (omap3_opp_init()) {
+                pr_err("%s: opp default init failed\n", __func__);
+                return;
+        }
+
+        /* Custom OPP enabled for XM */
+        if (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_XM) {
+                struct omap_hwmod *mh = omap_hwmod_lookup("mpu");
+                struct omap_hwmod *dh = omap_hwmod_lookup("iva");
+                struct device *dev;
+
+                if (!mh || !dh) {
+                        pr_err("%s: Aiee.. no mpu/dsp devices? %p %p\n",
+                                __func__, mh, dh);
+                        return;
+                }
+                /* Enable MPU 1GHz and lower opps */
+                dev = &mh->od->pdev.dev;
+                r = opp_enable(dev, 800000000);
+                /* TODO: MPU 1GHz needs SR and ABB */
+
+                /* Enable IVA 800MHz and lower opps */
+                dev = &dh->od->pdev.dev;
+                r |= opp_enable(dev, 660000000);
+                /* TODO: DSP 800MHz needs SR and ABB */
+                if (r) {
+                        pr_err("%s: failed to enable higher opp %d\n",
+                                __func__, r);
+                        /*
+                         * Cleanup - disable the higher freqs - we dont care
+                         * about the results
+                         */
+                        dev = &mh->od->pdev.dev;
+                        opp_disable(dev, 800000000);
+                        dev = &dh->od->pdev.dev;
+                        opp_disable(dev, 660000000);
+                }
+        }
+        return;
+}
+
 static void __init omap3_beagle_init(void)
 {
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
@@ -627,6 +676,7 @@ static void __init omap3_beagle_init(void)
         omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
 
         beagle_display_init();
+        beagle_opp_init();
 }
 
 MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")
diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c
index 48de4513de49..3f20cbb9967b 100644
--- a/arch/arm/mach-omap2/common.c
+++ b/arch/arm/mach-omap2/common.c
@@ -50,9 +50,6 @@ static struct omap_globals omap242x_globals = {
         .ctrl   = OMAP242X_CTRL_BASE,
         .prm    = OMAP2420_PRM_BASE,
         .cm     = OMAP2420_CM_BASE,
-        .uart1_phys     = OMAP2_UART1_BASE,
-        .uart2_phys     = OMAP2_UART2_BASE,
-        .uart3_phys     = OMAP2_UART3_BASE,
 };
 
 void __init omap2_set_globals_242x(void)
@@ -71,9 +68,6 @@ static struct omap_globals omap243x_globals = {
         .ctrl   = OMAP243X_CTRL_BASE,
         .prm    = OMAP2430_PRM_BASE,
         .cm     = OMAP2430_CM_BASE,
-        .uart1_phys     = OMAP2_UART1_BASE,
-        .uart2_phys     = OMAP2_UART2_BASE,
-        .uart3_phys     = OMAP2_UART3_BASE,
 };
 
 void __init omap2_set_globals_243x(void)
@@ -92,10 +86,6 @@ static struct omap_globals omap3_globals = {
         .ctrl   = OMAP343X_CTRL_BASE,
         .prm    = OMAP3430_PRM_BASE,
         .cm     = OMAP3430_CM_BASE,
-        .uart1_phys     = OMAP3_UART1_BASE,
-        .uart2_phys     = OMAP3_UART2_BASE,
-        .uart3_phys     = OMAP3_UART3_BASE,
-        .uart4_phys     = OMAP3_UART4_BASE,     /* Only on 3630 */
 };
 
 void __init omap2_set_globals_3xxx(void)
@@ -140,10 +130,6 @@ static struct omap_globals omap4_globals = {
         .prm    = OMAP4430_PRM_BASE,
         .cm     = OMAP4430_CM_BASE,
         .cm2    = OMAP4430_CM2_BASE,
-        .uart1_phys     = OMAP4_UART1_BASE,
-        .uart2_phys     = OMAP4_UART2_BASE,
-        .uart3_phys     = OMAP4_UART3_BASE,
-        .uart4_phys     = OMAP4_UART4_BASE,
 };
 
 void __init omap2_set_globals_443x(void)
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index f7b22a16f385..cba437dd002b 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -58,6 +58,7 @@ struct omap3_processor_cx {
         u32 core_state;
         u32 threshold;
         u32 flags;
+        const char *desc;
 };
 
 struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES];
@@ -365,6 +366,7 @@ void omap_init_power_states(void)
         omap3_power_states[OMAP3_STATE_C1].mpu_state = PWRDM_POWER_ON;
         omap3_power_states[OMAP3_STATE_C1].core_state = PWRDM_POWER_ON;
         omap3_power_states[OMAP3_STATE_C1].flags = CPUIDLE_FLAG_TIME_VALID;
+        omap3_power_states[OMAP3_STATE_C1].desc = "MPU ON + CORE ON";
 
         /* C2 . MPU WFI + Core inactive */
         omap3_power_states[OMAP3_STATE_C2].valid =
@@ -380,6 +382,7 @@ void omap_init_power_states(void)
         omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_ON;
         omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID |
                                 CPUIDLE_FLAG_CHECK_BM;
+        omap3_power_states[OMAP3_STATE_C2].desc = "MPU ON + CORE ON";
 
         /* C3 . MPU CSWR + Core inactive */
         omap3_power_states[OMAP3_STATE_C3].valid =
@@ -395,6 +398,7 @@ void omap_init_power_states(void)
         omap3_power_states[OMAP3_STATE_C3].core_state = PWRDM_POWER_ON;
         omap3_power_states[OMAP3_STATE_C3].flags = CPUIDLE_FLAG_TIME_VALID |
                                 CPUIDLE_FLAG_CHECK_BM;
+        omap3_power_states[OMAP3_STATE_C3].desc = "MPU RET + CORE ON";
 
         /* C4 . MPU OFF + Core inactive */
         omap3_power_states[OMAP3_STATE_C4].valid =
@@ -410,6 +414,7 @@ void omap_init_power_states(void)
         omap3_power_states[OMAP3_STATE_C4].core_state = PWRDM_POWER_ON;
         omap3_power_states[OMAP3_STATE_C4].flags = CPUIDLE_FLAG_TIME_VALID |
                                 CPUIDLE_FLAG_CHECK_BM;
+        omap3_power_states[OMAP3_STATE_C4].desc = "MPU OFF + CORE ON";
 
         /* C5 . MPU CSWR + Core CSWR*/
         omap3_power_states[OMAP3_STATE_C5].valid =
@@ -425,6 +430,7 @@ void omap_init_power_states(void)
         omap3_power_states[OMAP3_STATE_C5].core_state = PWRDM_POWER_RET;
         omap3_power_states[OMAP3_STATE_C5].flags = CPUIDLE_FLAG_TIME_VALID |
                                 CPUIDLE_FLAG_CHECK_BM;
+        omap3_power_states[OMAP3_STATE_C5].desc = "MPU RET + CORE RET";
 
         /* C6 . MPU OFF + Core CSWR */
         omap3_power_states[OMAP3_STATE_C6].valid =
@@ -440,6 +446,7 @@ void omap_init_power_states(void)
         omap3_power_states[OMAP3_STATE_C6].core_state = PWRDM_POWER_RET;
         omap3_power_states[OMAP3_STATE_C6].flags = CPUIDLE_FLAG_TIME_VALID |
                                 CPUIDLE_FLAG_CHECK_BM;
+        omap3_power_states[OMAP3_STATE_C6].desc = "MPU OFF + CORE RET";
 
         /* C7 . MPU OFF + Core OFF */
         omap3_power_states[OMAP3_STATE_C7].valid =
@@ -455,6 +462,7 @@ void omap_init_power_states(void)
         omap3_power_states[OMAP3_STATE_C7].core_state = PWRDM_POWER_OFF;
         omap3_power_states[OMAP3_STATE_C7].flags = CPUIDLE_FLAG_TIME_VALID |
                                 CPUIDLE_FLAG_CHECK_BM;
+        omap3_power_states[OMAP3_STATE_C7].desc = "MPU OFF + CORE OFF";
 
         /*
          * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
@@ -464,7 +472,7 @@ void omap_init_power_states(void)
         if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) {
                 omap3_power_states[OMAP3_STATE_C7].valid = 0;
                 cpuidle_params_table[OMAP3_STATE_C7].valid = 0;
-                WARN_ONCE(1, "%s: core off state C7 disabled due to i583\n",
+                pr_warn("%s: core off state C7 disabled due to i583\n",
                                 __func__);
         }
 }
@@ -512,6 +520,7 @@ int __init omap3_idle_init(void)
                 if (cx->type == OMAP3_STATE_C1)
                         dev->safe_state = state;
                 sprintf(state->name, "C%d", count+1);
+                strncpy(state->desc, cx->desc, CPUIDLE_DESC_LEN);
                 count++;
         }
 
diff --git a/arch/arm/mach-omap2/include/mach/omap4-common.h b/arch/arm/mach-omap2/include/mach/omap4-common.h
index 5b0270b28934..de441c05a6a6 100644
--- a/arch/arm/mach-omap2/include/mach/omap4-common.h
+++ b/arch/arm/mach-omap2/include/mach/omap4-common.h
@@ -17,8 +17,12 @@
  * wfi used in low power code. Directly opcode is used instead
  * of instruction to avoid mulit-omap build break
  */
+#ifdef CONFIG_THUMB2_KERNEL
+#define do_wfi() __asm__ __volatile__ ("wfi" : : : "memory")
+#else
 #define do_wfi()                        \
                 __asm__ __volatile__ (".word    0xe320f003" : : : "memory")
+#endif
 
 #ifdef CONFIG_CACHE_L2X0
 extern void __iomem *l2cache_base;
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index 6e15e3d7c65e..86d564a640bb 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -138,10 +138,12 @@ static void omap2_mbox_disable_irq(struct omap_mbox *mbox,
                 omap_mbox_type_t irq)
 {
         struct omap_mbox2_priv *p = mbox->priv;
-        u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
-        l = mbox_read_reg(p->irqdisable);
-        l &= ~bit;
-        mbox_write_reg(l, p->irqdisable);
+        u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
+
+        if (!cpu_is_omap44xx())
+                bit = mbox_read_reg(p->irqdisable) & ~bit;
+
+        mbox_write_reg(bit, p->irqdisable);
 }
 
 static void omap2_mbox_ack_irq(struct omap_mbox *mbox,
diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S
index 6ae937a06cc1..4ee6aeca885a 100644
--- a/arch/arm/mach-omap2/omap-headsmp.S
+++ b/arch/arm/mach-omap2/omap-headsmp.S
@@ -45,5 +45,5 @@ hold:	ldr	r12,=0x103
          * should now contain the SVC stack for this core
          */
         b       secondary_startup
-END(omap_secondary_startup)
+ENDPROC(omap_secondary_startup)
 
diff --git a/arch/arm/mach-omap2/omap44xx-smc.S b/arch/arm/mach-omap2/omap44xx-smc.S
index 1980dc31a1a2..e69d37d95204 100644
--- a/arch/arm/mach-omap2/omap44xx-smc.S
+++ b/arch/arm/mach-omap2/omap44xx-smc.S
@@ -29,7 +29,7 @@ ENTRY(omap_smc1)
         dsb
         smc     #0
         ldmfd   sp!, {r2-r12, pc}
-END(omap_smc1)
+ENDPROC(omap_smc1)
 
 ENTRY(omap_modify_auxcoreboot0)
         stmfd   sp!, {r1-r12, lr}
@@ -37,7 +37,7 @@ ENTRY(omap_modify_auxcoreboot0)
         dsb
         smc     #0
         ldmfd   sp!, {r1-r12, pc}
-END(omap_modify_auxcoreboot0)
+ENDPROC(omap_modify_auxcoreboot0)
 
 ENTRY(omap_auxcoreboot_addr)
         stmfd   sp!, {r2-r12, lr}
@@ -45,7 +45,7 @@ ENTRY(omap_auxcoreboot_addr)
         dsb
         smc     #0
         ldmfd   sp!, {r2-r12, pc}
-END(omap_auxcoreboot_addr)
+ENDPROC(omap_auxcoreboot_addr)
 
 ENTRY(omap_read_auxcoreboot0)
         stmfd   sp!, {r2-r12, lr}
@@ -54,4 +54,4 @@ ENTRY(omap_read_auxcoreboot0)
         smc     #0
         mov     r0, r0, lsr #9
         ldmfd   sp!, {r2-r12, pc}
-END(omap_read_auxcoreboot0)
+ENDPROC(omap_read_auxcoreboot0)
diff --git a/arch/arm/mach-omap2/omap_twl.c b/arch/arm/mach-omap2/omap_twl.c
index 00e1d2b53683..b341c36a93f3 100644
--- a/arch/arm/mach-omap2/omap_twl.c
+++ b/arch/arm/mach-omap2/omap_twl.c
@@ -59,8 +59,15 @@
 
 static bool is_offset_valid;
 static u8 smps_offset;
+/*
+ * Flag to ensure Smartreflex bit in TWL
+ * being cleared in board file is not overwritten.
+ */
+static bool __initdata twl_sr_enable_autoinit;
 
+#define TWL4030_DCDC_GLOBAL_CFG        0x06
 #define REG_SMPS_OFFSET         0xE0
+#define SMARTREFLEX_ENABLE     BIT(3)
 
 static unsigned long twl4030_vsel_to_uv(const u8 vsel)
 {
@@ -269,6 +276,18 @@ int __init omap3_twl_init(void)
                 omap3_core_volt_info.vp_vddmax = OMAP3630_VP2_VLIMITTO_VDDMAX;
         }
 
+        /*
+         * The smartreflex bit on twl4030 specifies if the setting of voltage
+         * is done over the I2C_SR path. Since this setting is independent of
+         * the actual usage of smartreflex AVS module, we enable TWL SR bit
+         * by default irrespective of whether smartreflex AVS module is enabled
+         * on the OMAP side or not. This is because without this bit enabled,
+         * the voltage scaling through vp forceupdate/bypass mechanism of
+         * voltage scaling will not function on TWL over I2C_SR.
+         */
+        if (!twl_sr_enable_autoinit)
+                omap3_twl_set_sr_bit(true);
+
         voltdm = omap_voltage_domain_lookup("mpu");
         omap_voltage_register_pmic(voltdm, &omap3_mpu_volt_info);
 
@@ -277,3 +296,44 @@ int __init omap3_twl_init(void)
 
         return 0;
 }
+
+/**
+ * omap3_twl_set_sr_bit() - Set/Clear SR bit on TWL
+ * @enable: enable SR mode in twl or not
+ *
+ * If 'enable' is true, enables Smartreflex bit on TWL 4030 to make sure
+ * voltage scaling through OMAP SR works. Else, the smartreflex bit
+ * on twl4030 is cleared as there are platforms which use OMAP3 and T2 but
+ * use Synchronized Scaling Hardware Strategy (ENABLE_VMODE=1) and Direct
+ * Strategy Software Scaling Mode (ENABLE_VMODE=0), for setting the voltages,
+ * in those scenarios this bit is to be cleared (enable = false).
+ *
+ * Returns 0 on sucess, error is returned if I2C read/write fails.
+ */
+int __init omap3_twl_set_sr_bit(bool enable)
+{
+        u8 temp;
+        int ret;
+        if (twl_sr_enable_autoinit)
+                pr_warning("%s: unexpected multiple calls\n", __func__);
+
+        ret = twl_i2c_read_u8(TWL4030_MODULE_PM_RECEIVER, &temp,
+                                        TWL4030_DCDC_GLOBAL_CFG);
+        if (ret)
+                goto err;
+
+        if (enable)
+                temp |= SMARTREFLEX_ENABLE;
+        else
+                temp &= ~SMARTREFLEX_ENABLE;
+
+        ret = twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, temp,
+                                TWL4030_DCDC_GLOBAL_CFG);
+        if (!ret) {
+                twl_sr_enable_autoinit = true;
+                return 0;
+        }
+err:
+        pr_err("%s: Error access to TWL4030 (%d)\n", __func__, ret);
+        return ret;
+}
diff --git a/arch/arm/mach-omap2/opp3xxx_data.c b/arch/arm/mach-omap2/opp3xxx_data.c
index 0486fce8a92c..fd3a1af8d51e 100644
--- a/arch/arm/mach-omap2/opp3xxx_data.c
+++ b/arch/arm/mach-omap2/opp3xxx_data.c
@@ -21,6 +21,7 @@
 #include <plat/cpu.h>
 
 #include "omap_opp_data.h"
+#include "pm.h"
 
 static struct omap_opp_def __initdata omap34xx_opp_def_list[] = {
         /* MPU OPP1 */
@@ -88,7 +89,7 @@ static struct omap_opp_def __initdata omap36xx_opp_def_list[] = {
 /**
  * omap3_opp_init() - initialize omap3 opp table
  */
-static int __init omap3_opp_init(void)
+int __init omap3_opp_init(void)
 {
         int r = -ENODEV;
 
diff --git a/arch/arm/mach-omap2/opp4xxx_data.c b/arch/arm/mach-omap2/opp4xxx_data.c
index a11fa566d8ee..f0e9939a7217 100644
--- a/arch/arm/mach-omap2/opp4xxx_data.c
+++ b/arch/arm/mach-omap2/opp4xxx_data.c
@@ -22,6 +22,7 @@
 #include <plat/cpu.h>
 
 #include "omap_opp_data.h"
+#include "pm.h"
 
 static struct omap_opp_def __initdata omap44xx_opp_def_list[] = {
         /* MPU OPP1 - OPP50 */
@@ -42,7 +43,7 @@ static struct omap_opp_def __initdata omap44xx_opp_def_list[] = {
 /**
  * omap4_opp_init() - initialize omap4 opp table
  */
-static int __init omap4_opp_init(void)
+int __init omap4_opp_init(void)
 {
         int r = -ENODEV;
 
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index d5a102c71989..6e4eb7ff95a8 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -83,7 +83,9 @@ static int _init_omap_device(char *name, struct device **new_dev)
 static void omap2_init_processor_devices(void)
 {
         _init_omap_device("mpu", &mpu_dev);
-        _init_omap_device("iva", &iva_dev);
+        if (omap3_has_iva())
+                _init_omap_device("iva", &iva_dev);
+
         if (cpu_is_omap44xx()) {
                 _init_omap_device("l3_main_1", &l3_dev);
                 _init_omap_device("dsp", &dsp_dev);
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 1c1b0ab5b978..f4a5f716422b 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -127,6 +127,7 @@ static inline void omap_enable_smartreflex_on_init(void) {}
 #ifdef CONFIG_TWL4030_CORE
 extern int omap3_twl_init(void);
 extern int omap4_twl_init(void);
+extern int omap3_twl_set_sr_bit(bool enable);
 #else
 static inline int omap3_twl_init(void)
 {
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index 97feb3ab6a69..10f8747ba572 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -363,9 +363,6 @@ static const struct platform_suspend_ops __initdata omap_pm_ops;
 /* XXX This function should be shareable between OMAP2xxx and OMAP3 */
 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
 {
-        clkdm_clear_all_wkdeps(clkdm);
-        clkdm_clear_all_sleepdeps(clkdm);
-
         if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
                 omap2_clkdm_allow_idle(clkdm);
         else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
@@ -411,10 +408,7 @@ static void __init prcm_setup_regs(void)
         pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
         omap2_clkdm_sleep(gfx_clkdm);
 
-        /*
-         * Clear clockdomain wakeup dependencies and enable
-         * hardware-supervised idle for all clkdms
-         */
+        /* Enable hardware-supervised idle for all clkdms */
         clkdm_for_each(clkdms_setup, NULL);
         clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
 
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 2f864e4b085d..1883a464aace 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -311,11 +311,6 @@ static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
         return IRQ_HANDLED;
 }
 
-static void restore_control_register(u32 val)
-{
-        __asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val));
-}
-
 /* Function to restore the table entry that was modified for enabling MMU */
 static void restore_table_entry(void)
 {
@@ -337,7 +332,7 @@ static void restore_table_entry(void)
         control_reg_value = __raw_readl(scratchpad_address
                                         + OMAP343X_CONTROL_REG_VALUE_OFFSET);
         /* This will enable caches and prediction */
-        restore_control_register(control_reg_value);
+        set_cr(control_reg_value);
 }
 
 void omap_sram_idle(void)
@@ -695,21 +690,6 @@ static void __init prcm_setup_regs(void)
         u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
                                         OMAP3630_GRPSEL_UART4_MASK : 0;
 
-
-        /* XXX Reset all wkdeps. This should be done when initializing
-         * powerdomains */
-        omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
-        omap2_prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
-        omap2_prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
-        omap2_prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
-        omap2_prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
-        omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
-        if (omap_rev() > OMAP3430_REV_ES1_0) {
-                omap2_prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
-                omap2_prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
-        } else
-                omap2_prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
-
         /*
          * Enable interface clock autoidle for all modules.
          * Note that in the long run this should be done by clockfw
@@ -928,8 +908,7 @@ void omap3_pm_off_mode_enable(int enable)
                                 pwrst->pwrdm == core_pwrdm &&
                                 state == PWRDM_POWER_OFF) {
                         pwrst->next_state = PWRDM_POWER_RET;
-                        WARN_ONCE(1,
-                                "%s: Core OFF disabled due to errata i583\n",
+                        pr_warn("%s: Core OFF disabled due to errata i583\n",
                                 __func__);
                 } else {
                         pwrst->next_state = state;
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index 98d8232808b8..e60ac1f71bd4 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -64,6 +64,11 @@
 #define SDRC_DLLA_STATUS_V      OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
 #define SDRC_DLLA_CTRL_V        OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
 
+/*
+ * This file needs be built unconditionally as ARM to interoperate correctly
+ * with non-Thumb-2-capable firmware.
+ */
+        .arm
 
 /*
  * API functions
@@ -82,6 +87,8 @@ ENTRY(get_restore_pointer)
         stmfd   sp!, {lr}       @ save registers on stack
         adr     r0, restore
         ldmfd   sp!, {pc}       @ restore regs and return
+ENDPROC(get_restore_pointer)
+        .align
 ENTRY(get_restore_pointer_sz)
         .word   . - get_restore_pointer
 
@@ -91,6 +98,8 @@ ENTRY(get_omap3630_restore_pointer)
         stmfd   sp!, {lr}       @ save registers on stack
         adr     r0, restore_3630
         ldmfd   sp!, {pc}       @ restore regs and return
+ENDPROC(get_omap3630_restore_pointer)
+        .align
 ENTRY(get_omap3630_restore_pointer_sz)
         .word   . - get_omap3630_restore_pointer
 
@@ -100,6 +109,8 @@ ENTRY(get_es3_restore_pointer)
         stmfd   sp!, {lr}       @ save registers on stack
         adr     r0, restore_es3
         ldmfd   sp!, {pc}       @ restore regs and return
+ENDPROC(get_es3_restore_pointer)
+        .align
 ENTRY(get_es3_restore_pointer_sz)
         .word   . - get_es3_restore_pointer
 
@@ -113,8 +124,10 @@ ENTRY(enable_omap3630_toggle_l2_on_restore)
         stmfd   sp!, {lr}       @ save registers on stack
         /* Setup so that we will disable and enable l2 */
         mov     r1, #0x1
-        str     r1, l2dis_3630
+        adrl    r2, l2dis_3630  @ may be too distant for plain adr
+        str     r1, [r2]
         ldmfd   sp!, {pc}       @ restore regs and return
+ENDPROC(enable_omap3630_toggle_l2_on_restore)
 
         .text
 /* Function to call rom code to save secure ram context */
@@ -131,20 +144,22 @@ ENTRY(save_secure_ram_context)
         mov     r1, #0                  @ set task id for ROM code in r1
         mov     r2, #4                  @ set some flags in r2, r6
         mov     r6, #0xff
-        mcr     p15, 0, r0, c7, c10, 4  @ data write barrier
-        mcr     p15, 0, r0, c7, c10, 5  @ data memory barrier
-        .word   0xE1600071              @ call SMI monitor (smi #1)
+        dsb                             @ data write barrier
+        dmb                             @ data memory barrier
+        smc     #1                      @ call SMI monitor (smi #1)
         nop
         nop
         nop
         nop
         ldmfd   sp!, {r1-r12, pc}
+        .align
 sram_phy_addr_mask:
         .word   SRAM_BASE_P
 high_mask:
         .word   0xffff
 api_params:
         .word   0x4, 0x0, 0x0, 0x1, 0x1
+ENDPROC(save_secure_ram_context)
 ENTRY(save_secure_ram_context_sz)
         .word   . - save_secure_ram_context
 
@@ -173,12 +188,12 @@ ENTRY(omap34xx_cpu_suspend)
         stmfd   sp!, {r0-r12, lr}       @ save registers on stack
 
         /*
-         * r0 contains restore pointer in sdram
+         * r0 contains CPU context save/restore pointer in sdram
          * r1 contains information about saving context:
          *   0 - No context lost
          *   1 - Only L1 and logic lost
-         *   2 - Only L2 lost
-         *   3 - Both L1 and L2 lost
+         *   2 - Only L2 lost (Even L1 is retained we clean it along with L2)
+         *   3 - Both L1 and L2 lost and logic lost
          */
 
         /* Directly jump to WFI is the context save is not required */
@@ -199,89 +214,74 @@ save_context_wfi:
         beq     clean_caches
 
 l1_logic_lost:
-        /* Store sp and spsr to SDRAM */
-        mov     r4, sp
-        mrs     r5, spsr
-        mov     r6, lr
+        mov     r4, sp                  @ Store sp
+        mrs     r5, spsr                @ Store spsr
+        mov     r6, lr                  @ Store lr
         stmia   r8!, {r4-r6}
-        /* Save all ARM registers */
-        /* Coprocessor access control register */
-        mrc     p15, 0, r6, c1, c0, 2
-        stmia   r8!, {r6}
-        /* TTBR0, TTBR1 and Translation table base control */
-        mrc     p15, 0, r4, c2, c0, 0
-        mrc     p15, 0, r5, c2, c0, 1
-        mrc     p15, 0, r6, c2, c0, 2
-        stmia   r8!, {r4-r6}
-        /*
-         * Domain access control register, data fault status register,
-         * and instruction fault status register
-         */
-        mrc     p15, 0, r4, c3, c0, 0
-        mrc     p15, 0, r5, c5, c0, 0
-        mrc     p15, 0, r6, c5, c0, 1
-        stmia   r8!, {r4-r6}
-        /*
-         * Data aux fault status register, instruction aux fault status,
-         * data fault address register and instruction fault address register
-         */
-        mrc     p15, 0, r4, c5, c1, 0
-        mrc     p15, 0, r5, c5, c1, 1
-        mrc     p15, 0, r6, c6, c0, 0
-        mrc     p15, 0, r7, c6, c0, 2
-        stmia   r8!, {r4-r7}
-        /*
-         * user r/w thread and process ID, user r/o thread and process ID,
-         * priv only thread and process ID, cache size selection
-         */
-        mrc     p15, 0, r4, c13, c0, 2
-        mrc     p15, 0, r5, c13, c0, 3
-        mrc     p15, 0, r6, c13, c0, 4
-        mrc     p15, 2, r7, c0, c0, 0
+
+        mrc     p15, 0, r4, c1, c0, 2   @ Coprocessor access control register
+        mrc     p15, 0, r5, c2, c0, 0   @ TTBR0
+        mrc     p15, 0, r6, c2, c0, 1   @ TTBR1
+        mrc     p15, 0, r7, c2, c0, 2   @ TTBCR
         stmia   r8!, {r4-r7}
-        /* Data TLB lockdown, instruction TLB lockdown registers */
-        mrc     p15, 0, r5, c10, c0, 0
-        mrc     p15, 0, r6, c10, c0, 1
-        stmia   r8!, {r5-r6}
-        /* Secure or non secure vector base address, FCSE PID, Context PID*/
-        mrc     p15, 0, r4, c12, c0, 0
-        mrc     p15, 0, r5, c13, c0, 0
-        mrc     p15, 0, r6, c13, c0, 1
-        stmia   r8!, {r4-r6}
-        /* Primary remap, normal remap registers */
-        mrc     p15, 0, r4, c10, c2, 0
-        mrc     p15, 0, r5, c10, c2, 1
-        stmia   r8!,{r4-r5}
 
-        /* Store current cpsr*/
-        mrs     r2, cpsr
-        stmia   r8!, {r2}
+        mrc     p15, 0, r4, c3, c0, 0   @ Domain access Control Register
+        mrc     p15, 0, r5, c10, c2, 0  @ PRRR
+        mrc     p15, 0, r6, c10, c2, 1  @ NMRR
+        stmia   r8!,{r4-r6}
 
-        mrc     p15, 0, r4, c1, c0, 0
-        /* save control register */
+        mrc     p15, 0, r4, c13, c0, 1  @ Context ID
+        mrc     p15, 0, r5, c13, c0, 2  @ User r/w thread and process ID
+        mrc     p15, 0, r6, c12, c0, 0  @ Secure or NS vector base address
+        mrs     r7, cpsr                @ Store current cpsr
+        stmia   r8!, {r4-r7}
+
+        mrc     p15, 0, r4, c1, c0, 0   @ save control register
         stmia   r8!, {r4}
 
 clean_caches:
         /*
-         * Clean Data or unified cache to POU
-         * How to invalidate only L1 cache???? - #FIX_ME#
-         * mcr  p15, 0, r11, c7, c11, 1
-         */
-        cmp     r1, #0x1                @ Check whether L2 inval is required
-        beq     omap3_do_wfi
-
-clean_l2:
-        /*
          * jump out to kernel flush routine
          *  - reuse that code is better
          *  - it executes in a cached space so is faster than refetch per-block
          *  - should be faster and will change with kernel
          *  - 'might' have to copy address, load and jump to it
+         * Flush all data from the L1 data cache before disabling
+         * SCTLR.C bit.
          */
         ldr     r1, kernel_flush
         mov     lr, pc
         bx      r1
 
+        /*
+         * Clear the SCTLR.C bit to prevent further data cache
+         * allocation. Clearing SCTLR.C would make all the data accesses
+         * strongly ordered and would not hit the cache.
+         */
+        mrc     p15, 0, r0, c1, c0, 0
+        bic     r0, r0, #(1 << 2)       @ Disable the C bit
+        mcr     p15, 0, r0, c1, c0, 0
+        isb
+
+        /*
+         * Invalidate L1 data cache. Even though only invalidate is
+         * necessary exported flush API is used here. Doing clean
+         * on already clean cache would be almost NOP.
+         */
+        ldr     r1, kernel_flush
+        blx     r1
+        /*
+         * The kernel doesn't interwork: v7_flush_dcache_all in particluar will
+         * always return in Thumb state when CONFIG_THUMB2_KERNEL is enabled.
+         * This sequence switches back to ARM.  Note that .align may insert a
+         * nop: bx pc needs to be word-aligned in order to work.
+         */
+ THUMB( .thumb          )
+ THUMB( .align          )
+ THUMB( bx      pc      )
+ THUMB( nop             )
+        .arm
+
 omap3_do_wfi:
         ldr     r4, sdrc_power          @ read the SDRC_POWER register
         ldr     r5, [r4]                @ read the contents of SDRC_POWER
@@ -289,9 +289,8 @@ omap3_do_wfi:
         str     r5, [r4]                @ write back to SDRC_POWER register
 
         /* Data memory barrier and Data sync barrier */
-        mov     r1, #0
-        mcr     p15, 0, r1, c7, c10, 4
-        mcr     p15, 0, r1, c7, c10, 5
+        dsb
+        dmb
 
 /*
  * ===================================
@@ -317,6 +316,12 @@ omap3_do_wfi:
         nop
         bl wait_sdrc_ok
 
+        mrc     p15, 0, r0, c1, c0, 0
+        tst     r0, #(1 << 2)           @ Check C bit enabled?
+        orreq   r0, r0, #(1 << 2)       @ Enable the C bit if cleared
+        mcreq   p15, 0, r0, c1, c0, 0
+        isb
+
 /*
  * ===================================
  * == Exit point from non-OFF modes ==
@@ -406,9 +411,9 @@ skipl2dis:
         mov     r2, #4                  @ set some flags in r2, r6
         mov     r6, #0xff
         adr     r3, l2_inv_api_params   @ r3 points to dummy parameters
-        mcr     p15, 0, r0, c7, c10, 4  @ data write barrier
-        mcr     p15, 0, r0, c7, c10, 5  @ data memory barrier
-        .word   0xE1600071              @ call SMI monitor (smi #1)
+        dsb                             @ data write barrier
+        dmb                             @ data memory barrier
+        smc     #1                      @ call SMI monitor (smi #1)
         /* Write to Aux control register to set some bits */
         mov     r0, #42                 @ set service ID for PPA
         mov     r12, r0                 @ copy secure Service ID in r12
@@ -417,9 +422,9 @@ skipl2dis:
         mov     r6, #0xff
         ldr     r4, scratchpad_base
         ldr     r3, [r4, #0xBC]         @ r3 points to parameters
-        mcr     p15, 0, r0, c7, c10, 4  @ data write barrier
-        mcr     p15, 0, r0, c7, c10, 5  @ data memory barrier
-        .word   0xE1600071              @ call SMI monitor (smi #1)
+        dsb                             @ data write barrier
+        dmb                             @ data memory barrier
+        smc     #1                      @ call SMI monitor (smi #1)
 
 #ifdef CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE
         /* Restore L2 aux control register */
@@ -432,29 +437,30 @@ skipl2dis:
         ldr     r4, scratchpad_base
         ldr     r3, [r4, #0xBC]
         adds    r3, r3, #8              @ r3 points to parameters
-        mcr     p15, 0, r0, c7, c10, 4  @ data write barrier
-        mcr     p15, 0, r0, c7, c10, 5  @ data memory barrier
-        .word   0xE1600071              @ call SMI monitor (smi #1)
+        dsb                             @ data write barrier
+        dmb                             @ data memory barrier
+        smc     #1                      @ call SMI monitor (smi #1)
 #endif
         b       logic_l1_restore
 
+        .align
 l2_inv_api_params:
         .word   0x1, 0x00
 l2_inv_gp:
         /* Execute smi to invalidate L2 cache */
         mov r12, #0x1                   @ set up to invalidate L2
-        .word 0xE1600070                @ Call SMI monitor (smieq)
+        smc     #0                      @ Call SMI monitor (smieq)
         /* Write to Aux control register to set some bits */
         ldr     r4, scratchpad_base
         ldr     r3, [r4,#0xBC]
         ldr     r0, [r3,#4]
         mov     r12, #0x3
-        .word   0xE1600070              @ Call SMI monitor (smieq)
+        smc     #0                      @ Call SMI monitor (smieq)
         ldr     r4, scratchpad_base
         ldr     r3, [r4,#0xBC]
         ldr     r0, [r3,#12]
         mov     r12, #0x2
-        .word   0xE1600070              @ Call SMI monitor (smieq)
+        smc     #0                      @ Call SMI monitor (smieq)
 logic_l1_restore:
         ldr     r1, l2dis_3630
         cmp     r1, #0x1                @ Test if L2 re-enable needed on 3630
@@ -473,68 +479,29 @@ skipl2reen:
         ldr     r4, scratchpad_base
         ldr     r3, [r4,#0xBC]
         adds    r3, r3, #16
+
         ldmia   r3!, {r4-r6}
-        mov     sp, r4
-        msr     spsr_cxsf, r5
-        mov     lr, r6
-
-        ldmia   r3!, {r4-r9}
-        /* Coprocessor access Control Register */
-        mcr p15, 0, r4, c1, c0, 2
-
-        /* TTBR0 */
-        MCR p15, 0, r5, c2, c0, 0
-        /* TTBR1 */
-        MCR p15, 0, r6, c2, c0, 1
-        /* Translation table base control register */
-        MCR p15, 0, r7, c2, c0, 2
-        /* Domain access Control Register */
-        MCR p15, 0, r8, c3, c0, 0
-        /* Data fault status Register */
-        MCR p15, 0, r9, c5, c0, 0
-
-        ldmia   r3!,{r4-r8}
-        /* Instruction fault status Register */
-        MCR p15, 0, r4, c5, c0, 1
-        /* Data Auxiliary Fault Status Register */
-        MCR p15, 0, r5, c5, c1, 0
-        /* Instruction Auxiliary Fault Status Register*/
-        MCR p15, 0, r6, c5, c1, 1
-        /* Data Fault Address Register */
-        MCR p15, 0, r7, c6, c0, 0
-        /* Instruction Fault Address Register*/
-        MCR p15, 0, r8, c6, c0, 2
-        ldmia   r3!,{r4-r7}
+        mov     sp, r4                  @ Restore sp
+        msr     spsr_cxsf, r5           @ Restore spsr
+        mov     lr, r6                  @ Restore lr
+
+        ldmia   r3!, {r4-r7}
+        mcr     p15, 0, r4, c1, c0, 2   @ Coprocessor access Control Register
+        mcr     p15, 0, r5, c2, c0, 0   @ TTBR0
+        mcr     p15, 0, r6, c2, c0, 1   @ TTBR1
+        mcr     p15, 0, r7, c2, c0, 2   @ TTBCR
+
+        ldmia   r3!,{r4-r6}
+        mcr     p15, 0, r4, c3, c0, 0   @ Domain access Control Register
+        mcr     p15, 0, r5, c10, c2, 0  @ PRRR
+        mcr     p15, 0, r6, c10, c2, 1  @ NMRR
+
 
-        /* User r/w thread and process ID */
-        MCR p15, 0, r4, c13, c0, 2
-        /* User ro thread and process ID */
-        MCR p15, 0, r5, c13, c0, 3
-        /* Privileged only thread and process ID */
-        MCR p15, 0, r6, c13, c0, 4
-        /* Cache size selection */
-        MCR p15, 2, r7, c0, c0, 0
-        ldmia   r3!,{r4-r8}
-        /* Data TLB lockdown registers */
-        MCR p15, 0, r4, c10, c0, 0
-        /* Instruction TLB lockdown registers */
-        MCR p15, 0, r5, c10, c0, 1
-        /* Secure or Nonsecure Vector Base Address */
-        MCR p15, 0, r6, c12, c0, 0
-        /* FCSE PID */
-        MCR p15, 0, r7, c13, c0, 0
-        /* Context PID */
-        MCR p15, 0, r8, c13, c0, 1
-
-        ldmia   r3!,{r4-r5}
-        /* Primary memory remap register */
-        MCR p15, 0, r4, c10, c2, 0
-        /* Normal memory remap register */
-        MCR p15, 0, r5, c10, c2, 1
-
-        /* Restore cpsr */
-        ldmia   r3!,{r4}                @ load CPSR from SDRAM
-        msr     cpsr, r4                @ store cpsr
+        ldmia   r3!,{r4-r7}
+        mcr     p15, 0, r4, c13, c0, 1  @ Context ID
+        mcr     p15, 0, r5, c13, c0, 2  @ User r/w thread and process ID
+        mrc     p15, 0, r6, c12, c0, 0  @ Secure or NS vector base address
+        msr     cpsr, r7                @ store cpsr
 
         /* Enabling MMU here */
         mrc     p15, 0, r7, c2, c0, 2   @ Read TTBRControl
@@ -592,12 +559,17 @@ usettbr0:
         ldr     r2, cache_pred_disable_mask
         and     r4, r2
         mcr     p15, 0, r4, c1, c0, 0
+        dsb
+        isb
+        ldr     r0, =restoremmu_on
+        bx      r0
 
 /*
  * ==============================
  * == Exit point from OFF mode ==
  * ==============================
  */
+restoremmu_on:
         ldmfd   sp!, {r0-r12, pc}       @ restore regs and return
 
 
@@ -607,6 +579,7 @@ usettbr0:
 
 /* This function implements the erratum ID i443 WA, applies to 34xx >= ES3.0 */
         .text
+        .align  3
 ENTRY(es3_sdrc_fix)
         ldr     r4, sdrc_syscfg         @ get config addr
         ldr     r5, [r4]                @ get value
@@ -634,6 +607,7 @@ ENTRY(es3_sdrc_fix)
         str     r5, [r4]                @ kick off refreshes
         bx      lr
 
+        .align
 sdrc_syscfg:
         .word   SDRC_SYSCONFIG_P
 sdrc_mr_0:
@@ -648,6 +622,7 @@ sdrc_emr2_1:
         .word   SDRC_EMR2_1_P
 sdrc_manual_1:
         .word   SDRC_MANUAL_1_P
+ENDPROC(es3_sdrc_fix)
 ENTRY(es3_sdrc_fix_sz)
         .word   . - es3_sdrc_fix
 
@@ -682,6 +657,12 @@ wait_sdrc_ready:
         bic     r5, r5, #0x40
         str     r5, [r4]
 
+/*
+ * PC-relative stores lead to undefined behaviour in Thumb-2: use a r7 as a
+ * base instead.
+ * Be careful not to clobber r7 when maintaing this code.
+ */
+
 is_dll_in_lock_mode:
         /* Is dll in lock mode? */
         ldr     r4, sdrc_dlla_ctrl
@@ -689,10 +670,11 @@ is_dll_in_lock_mode:
         tst     r5, #0x4
         bxne    lr                      @ Return if locked
         /* wait till dll locks */
+        adr     r7, kick_counter
 wait_dll_lock_timed:
         ldr     r4, wait_dll_lock_counter
         add     r4, r4, #1
-        str     r4, wait_dll_lock_counter
+        str     r4, [r7, #wait_dll_lock_counter - kick_counter]
         ldr     r4, sdrc_dlla_status
         /* Wait 20uS for lock */
         mov     r6, #8
@@ -718,9 +700,10 @@ kick_dll:
         dsb
         ldr     r4, kick_counter
         add     r4, r4, #1
-        str     r4, kick_counter
+        str     r4, [r7]                @ kick_counter
         b       wait_dll_lock_timed
 
+        .align
 cm_idlest1_core:
         .word   CM_IDLEST1_CORE_V
 cm_idlest_ckgen:
@@ -763,6 +746,7 @@ kick_counter:
         .word   0
 wait_dll_lock_counter:
         .word   0
+ENDPROC(omap34xx_cpu_suspend)
 
 ENTRY(omap34xx_cpu_suspend_sz)
         .word   . - omap34xx_cpu_suspend
diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
index 95ac336fe3f7..0ab4dd5081ee 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -54,6 +54,7 @@ struct omap_sr {
         struct list_head                node;
         struct omap_sr_nvalue_table     *nvalue_table;
         struct voltagedomain            *voltdm;
+        struct dentry                   *dbg_dir;
 };
 
 /* sr_list contains all the instances of smartreflex module */
@@ -260,9 +261,11 @@ static int sr_late_init(struct omap_sr *sr_info)
         if (sr_class->class_type == SR_CLASS2 &&
                 sr_class->notify_flags && sr_info->irq) {
 
-                name = kzalloc(SMARTREFLEX_NAME_LEN + 1, GFP_KERNEL);
-                strcpy(name, "sr_");
-                strcat(name, sr_info->voltdm->name);
+                name = kasprintf(GFP_KERNEL, "sr_%s", sr_info->voltdm->name);
+                if (name == NULL) {
+                        ret = -ENOMEM;
+                        goto error;
+                }
                 ret = request_irq(sr_info->irq, sr_interrupt,
                                 0, name, (void *)sr_info);
                 if (ret)
@@ -282,6 +285,7 @@ error:
                 dev_err(&sr_info->pdev->dev, "%s: ERROR in registering"
                         "interrupt handler. Smartreflex will"
                         "not function as desired\n", __func__);
+                kfree(name);
                 kfree(sr_info);
                 return ret;
 }
@@ -820,7 +824,7 @@ static int __init omap_sr_probe(struct platform_device *pdev)
         struct omap_sr *sr_info = kzalloc(sizeof(struct omap_sr), GFP_KERNEL);
         struct omap_sr_data *pdata = pdev->dev.platform_data;
         struct resource *mem, *irq;
-        struct dentry *vdd_dbg_dir, *dbg_dir, *nvalue_dir;
+        struct dentry *vdd_dbg_dir, *nvalue_dir;
         struct omap_volt_data *volt_data;
         int i, ret = 0;
 
@@ -879,7 +883,7 @@ static int __init omap_sr_probe(struct platform_device *pdev)
                 ret = sr_late_init(sr_info);
                 if (ret) {
                         pr_warning("%s: Error in SR late init\n", __func__);
-                        return ret;
+                        goto err_release_region;
                 }
         }
 
@@ -890,30 +894,34 @@ static int __init omap_sr_probe(struct platform_device *pdev)
          * not try to create rest of the debugfs entries.
          */
         vdd_dbg_dir = omap_voltage_get_dbgdir(sr_info->voltdm);
-        if (!vdd_dbg_dir)
-                return -EINVAL;
+        if (!vdd_dbg_dir) {
+                ret = -EINVAL;
+                goto err_release_region;
+        }
 
-        dbg_dir = debugfs_create_dir("smartreflex", vdd_dbg_dir);
-        if (IS_ERR(dbg_dir)) {
+        sr_info->dbg_dir = debugfs_create_dir("smartreflex", vdd_dbg_dir);
+        if (IS_ERR(sr_info->dbg_dir)) {
                 dev_err(&pdev->dev, "%s: Unable to create debugfs directory\n",
                         __func__);
-                return PTR_ERR(dbg_dir);
+                ret = PTR_ERR(sr_info->dbg_dir);
+                goto err_release_region;
         }
 
-        (void) debugfs_create_file("autocomp", S_IRUGO | S_IWUSR, dbg_dir,
-                                (void *)sr_info, &pm_sr_fops);
-        (void) debugfs_create_x32("errweight", S_IRUGO, dbg_dir,
+        (void) debugfs_create_file("autocomp", S_IRUGO | S_IWUSR,
+                        sr_info->dbg_dir, (void *)sr_info, &pm_sr_fops);
+        (void) debugfs_create_x32("errweight", S_IRUGO, sr_info->dbg_dir,
                         &sr_info->err_weight);
-        (void) debugfs_create_x32("errmaxlimit", S_IRUGO, dbg_dir,
+        (void) debugfs_create_x32("errmaxlimit", S_IRUGO, sr_info->dbg_dir,
                         &sr_info->err_maxlimit);
-        (void) debugfs_create_x32("errminlimit", S_IRUGO, dbg_dir,
+        (void) debugfs_create_x32("errminlimit", S_IRUGO, sr_info->dbg_dir,
                         &sr_info->err_minlimit);
 
-        nvalue_dir = debugfs_create_dir("nvalue", dbg_dir);
+        nvalue_dir = debugfs_create_dir("nvalue", sr_info->dbg_dir);
         if (IS_ERR(nvalue_dir)) {
                 dev_err(&pdev->dev, "%s: Unable to create debugfs directory"
                         "for n-values\n", __func__);
-                return PTR_ERR(nvalue_dir);
+                ret = PTR_ERR(nvalue_dir);
+                goto err_release_region;
         }
 
         omap_voltage_get_volttable(sr_info->voltdm, &volt_data);
@@ -922,23 +930,15 @@ static int __init omap_sr_probe(struct platform_device *pdev)
                         " corresponding vdd vdd_%s. Cannot create debugfs"
                         "entries for n-values\n",
                         __func__, sr_info->voltdm->name);
-                return -ENODATA;
+                ret = -ENODATA;
+                goto err_release_region;
         }
 
         for (i = 0; i < sr_info->nvalue_count; i++) {
-                char *name;
-                char volt_name[32];
-
-                name = kzalloc(NVALUE_NAME_LEN + 1, GFP_KERNEL);
-                if (!name) {
-                        dev_err(&pdev->dev, "%s: Unable to allocate memory"
-                                " for n-value directory name\n",  __func__);
-                        return -ENOMEM;
-                }
+                char name[NVALUE_NAME_LEN + 1];
 
-                strcpy(name, "volt_");
-                sprintf(volt_name, "%d", volt_data[i].volt_nominal);
-                strcat(name, volt_name);
+                snprintf(name, sizeof(name), "volt_%d",
+                         volt_data[i].volt_nominal);
                 (void) debugfs_create_x32(name, S_IRUGO | S_IWUSR, nvalue_dir,
                                 &(sr_info->nvalue_table[i].nvalue));
         }
@@ -973,6 +973,8 @@ static int __devexit omap_sr_remove(struct platform_device *pdev)
 
         if (sr_info->autocomp_active)
                 sr_stop_vddautocomp(sr_info);
+        if (sr_info->dbg_dir)
+                debugfs_remove_recursive(sr_info->dbg_dir);
 
         list_del(&sr_info->node);
         iounmap(sr_info->base);
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index 7f893a29d500..1078bfbc25c7 100644
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -34,6 +34,12 @@
 #include "sdrc.h"
 #include "cm2xxx_3xxx.h"
 
+/*
+ * This file needs be built unconditionally as ARM to interoperate correctly
+ * with non-Thumb-2-capable firmware.
+ */
+        .arm
+
         .text
 
 /* r1 parameters */
@@ -116,24 +122,36 @@ ENTRY(omap3_sram_configure_core_dpll)
 
                                         @ pull the extra args off the stack
                                         @  and store them in SRAM
+
+/*
+ * PC-relative stores are deprecated in ARMv7 and lead to undefined behaviour
+ * in Thumb-2: use a r7 as a base instead.
+ * Be careful not to clobber r7 when maintaing this file.
+ */
+ THUMB( adr     r7, omap3_sram_configure_core_dpll                      )
+        .macro strtext Rt:req, label:req
+ ARM(   str     \Rt, \label                                             )
+ THUMB( str     \Rt, [r7, \label - omap3_sram_configure_core_dpll]      )
+        .endm
+
         ldr     r4, [sp, #52]
-        str     r4, omap_sdrc_rfr_ctrl_0_val
+        strtext r4, omap_sdrc_rfr_ctrl_0_val
         ldr     r4, [sp, #56]
-        str     r4, omap_sdrc_actim_ctrl_a_0_val
+        strtext r4, omap_sdrc_actim_ctrl_a_0_val
         ldr     r4, [sp, #60]
-        str     r4, omap_sdrc_actim_ctrl_b_0_val
+        strtext r4, omap_sdrc_actim_ctrl_b_0_val
         ldr     r4, [sp, #64]
-        str     r4, omap_sdrc_mr_0_val
+        strtext r4, omap_sdrc_mr_0_val
         ldr     r4, [sp, #68]
-        str     r4, omap_sdrc_rfr_ctrl_1_val
+        strtext r4, omap_sdrc_rfr_ctrl_1_val
         cmp     r4, #0                  @ if SDRC_RFR_CTRL_1 is 0,
         beq     skip_cs1_params         @  do not use cs1 params
         ldr     r4, [sp, #72]
-        str     r4, omap_sdrc_actim_ctrl_a_1_val
+        strtext r4, omap_sdrc_actim_ctrl_a_1_val
         ldr     r4, [sp, #76]
-        str     r4, omap_sdrc_actim_ctrl_b_1_val
+        strtext r4, omap_sdrc_actim_ctrl_b_1_val
         ldr     r4, [sp, #80]
-        str     r4, omap_sdrc_mr_1_val
+        strtext r4, omap_sdrc_mr_1_val
 skip_cs1_params:
         mrc     p15, 0, r8, c1, c0, 0   @ read ctrl register
         bic     r10, r8, #0x800         @ clear Z-bit, disable branch prediction
@@ -271,6 +289,7 @@ skip_cs1_prog:
         ldr     r12, [r11]              @ posted-write barrier for SDRC
         bx      lr
 
+        .align
 omap3_sdrc_power:
         .word OMAP34XX_SDRC_REGADDR(SDRC_POWER)
 omap3_cm_clksel1_pll:
@@ -319,6 +338,7 @@ omap3_sdrc_dlla_ctrl:
         .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
 core_m2_mask_val:
         .word 0x07FFFFFF
+ENDPROC(omap3_sram_configure_core_dpll)
 
 ENTRY(omap3_sram_configure_core_dpll_sz)
         .word   . - omap3_sram_configure_core_dpll
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index fbc5b775f895..b166b1d845d7 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -347,6 +347,7 @@ static struct platform_device *pxa25x_devices[] __initdata = {
         &pxa25x_device_assp,
         &pxa25x_device_pwm0,
         &pxa25x_device_pwm1,
+        &pxa_device_asoc_platform,
 };
 
 static struct sys_device pxa25x_sysdev[] = {
diff --git a/arch/arm/mach-pxa/tosa-bt.c b/arch/arm/mach-pxa/tosa-bt.c
index c31e601eb49c..b9b1e5c2b290 100644
--- a/arch/arm/mach-pxa/tosa-bt.c
+++ b/arch/arm/mach-pxa/tosa-bt.c
@@ -81,8 +81,6 @@ static int tosa_bt_probe(struct platform_device *dev)
                 goto err_rfk_alloc;
         }
 
-        rfkill_set_led_trigger_name(rfk, "tosa-bt");
-
         rc = rfkill_register(rfk);
         if (rc)
                 goto err_rfkill;
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index af152e70cfcf..f2582ec300d9 100644
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -875,6 +875,11 @@ static struct platform_device sharpsl_rom_device = {
         .dev.platform_data = &sharpsl_rom_data,
 };
 
+static struct platform_device wm9712_device = {
+        .name   = "wm9712-codec",
+        .id     = -1,
+};
+
 static struct platform_device *devices[] __initdata = {
         &tosascoop_device,
         &tosascoop_jc_device,
@@ -885,6 +890,7 @@ static struct platform_device *devices[] __initdata = {
         &tosaled_device,
         &tosa_bt_device,
         &sharpsl_rom_device,
+        &wm9712_device,
 };
 
 static void tosa_poweroff(void)
diff --git a/arch/arm/mach-s3c2440/Kconfig b/arch/arm/mach-s3c2440/Kconfig
index a0cb2581894f..50825a3f91cc 100644
--- a/arch/arm/mach-s3c2440/Kconfig
+++ b/arch/arm/mach-s3c2440/Kconfig
@@ -99,6 +99,7 @@ config MACH_NEO1973_GTA02
         select POWER_SUPPLY
         select MACH_NEO1973
         select S3C2410_PWM
+        select S3C_DEV_USB_HOST
         help
            Say Y here if you are using the Openmoko GTA02 / Freerunner GSM Phone
 
diff --git a/arch/arm/mach-s3c2440/include/mach/gta02.h b/arch/arm/mach-s3c2440/include/mach/gta02.h
index 953331d8d56a..3a56a229cac6 100644
--- a/arch/arm/mach-s3c2440/include/mach/gta02.h
+++ b/arch/arm/mach-s3c2440/include/mach/gta02.h
@@ -44,19 +44,19 @@
 #define GTA02v3_GPIO_nUSB_FLT   S3C2410_GPG(10) /* v3 + v4 only */
 #define GTA02v3_GPIO_nGSM_OC    S3C2410_GPG(11) /* v3 + v4 only */
 
-#define GTA02_GPIO_AMP_SHUT     S3C2440_GPJ1    /* v2 + v3 + v4 only */
-#define GTA02v1_GPIO_WLAN_GPIO10        S3C2440_GPJ2
-#define GTA02_GPIO_HP_IN        S3C2440_GPJ2    /* v2 + v3 + v4 only */
-#define GTA02_GPIO_INT0         S3C2440_GPJ3    /* v2 + v3 + v4 only */
-#define GTA02_GPIO_nGSM_EN      S3C2440_GPJ4
-#define GTA02_GPIO_3D_RESET     S3C2440_GPJ5
-#define GTA02_GPIO_nDL_GSM      S3C2440_GPJ6    /* v4 + v5 only */
-#define GTA02_GPIO_WLAN_GPIO0   S3C2440_GPJ7
-#define GTA02v1_GPIO_BAT_ID     S3C2440_GPJ8
-#define GTA02_GPIO_KEEPACT      S3C2440_GPJ8
-#define GTA02v1_GPIO_HP_IN      S3C2440_GPJ10
-#define GTA02_CHIP_PWD          S3C2440_GPJ11   /* v2 + v3 + v4 only */
-#define GTA02_GPIO_nWLAN_RESET  S3C2440_GPJ12   /* v2 + v3 + v4 only */
+#define GTA02_GPIO_AMP_SHUT     S3C2410_GPJ(1)  /* v2 + v3 + v4 only */
+#define GTA02v1_GPIO_WLAN_GPIO10        S3C2410_GPJ(2)
+#define GTA02_GPIO_HP_IN        S3C2410_GPJ(2)  /* v2 + v3 + v4 only */
+#define GTA02_GPIO_INT0         S3C2410_GPJ(3)  /* v2 + v3 + v4 only */
+#define GTA02_GPIO_nGSM_EN      S3C2410_GPJ(4)
+#define GTA02_GPIO_3D_RESET     S3C2410_GPJ(5)
+#define GTA02_GPIO_nDL_GSM      S3C2410_GPJ(6)  /* v4 + v5 only */
+#define GTA02_GPIO_WLAN_GPIO0   S3C2410_GPJ(7)
+#define GTA02v1_GPIO_BAT_ID     S3C2410_GPJ(8)
+#define GTA02_GPIO_KEEPACT      S3C2410_GPJ(8)
+#define GTA02v1_GPIO_HP_IN      S3C2410_GPJ(10)
+#define GTA02_CHIP_PWD          S3C2410_GPJ(11) /* v2 + v3 + v4 only */
+#define GTA02_GPIO_nWLAN_RESET  S3C2410_GPJ(12) /* v2 + v3 + v4 only */
 
 #define GTA02_IRQ_GSENSOR_1     IRQ_EINT0
 #define GTA02_IRQ_MODEM         IRQ_EINT1
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index dd3782064508..fdfc4d5e37a1 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -151,6 +151,12 @@ static struct clk init_clocks_off[] = {
                 .enable         = s3c64xx_pclk_ctrl,
                 .ctrlbit        = S3C_CLKCON_PCLK_IIC,
         }, {
+                .name           = "i2c",
+                .id             = 1,
+                .parent         = &clk_p,
+                .enable         = s3c64xx_pclk_ctrl,
+                .ctrlbit        = S3C6410_CLKCON_PCLK_I2C1,
+        }, {
                 .name           = "iis",
                 .id             = 0,
                 .parent         = &clk_p,
diff --git a/arch/arm/mach-s3c64xx/dma.c b/arch/arm/mach-s3c64xx/dma.c
index 135db1b41252..c35585cf8c4f 100644
--- a/arch/arm/mach-s3c64xx/dma.c
+++ b/arch/arm/mach-s3c64xx/dma.c
@@ -690,12 +690,12 @@ static int s3c64xx_dma_init1(int chno, enum dma_ch chbase,
 
         regptr = regs + PL080_Cx_BASE(0);
 
-        for (ch = 0; ch < 8; ch++, chno++, chptr++) {
-                printk(KERN_INFO "%s: registering DMA %d (%p)\n",
-                       __func__, chno, regptr);
+        for (ch = 0; ch < 8; ch++, chptr++) {
+                pr_debug("%s: registering DMA %d (%p)\n",
+                         __func__, chno + ch, regptr);
 
                 chptr->bit = 1 << ch;
-                chptr->number = chno;
+                chptr->number = chno + ch;
                 chptr->dmac = dmac;
                 chptr->regs = regptr;
                 regptr += PL080_Cx_STRIDE;
@@ -704,7 +704,8 @@ static int s3c64xx_dma_init1(int chno, enum dma_ch chbase,
         /* for the moment, permanently enable the controller */
         writel(PL080_CONFIG_ENABLE, regs + PL080_CONFIG);
 
-        printk(KERN_INFO "PL080: IRQ %d, at %p\n", irq, regs);
+        printk(KERN_INFO "PL080: IRQ %d, at %p, channels %d..%d\n",
+               irq, regs, chno, chno+8);
 
         return 0;
 
diff --git a/arch/arm/mach-s3c64xx/gpiolib.c b/arch/arm/mach-s3c64xx/gpiolib.c
index fd99a82e82c4..92b09085caaa 100644
--- a/arch/arm/mach-s3c64xx/gpiolib.c
+++ b/arch/arm/mach-s3c64xx/gpiolib.c
@@ -72,7 +72,7 @@ static struct s3c_gpio_cfg gpio_4bit_cfg_eint0011 = {
         .get_pull       = s3c_gpio_getpull_updown,
 };
 
-int s3c64xx_gpio2int_gpm(struct gpio_chip *chip, unsigned pin)
+static int s3c64xx_gpio2int_gpm(struct gpio_chip *chip, unsigned pin)
 {
         return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO;
 }
@@ -138,7 +138,7 @@ static struct s3c_gpio_chip gpio_4bit[] = {
         },
 };
 
-int s3c64xx_gpio2int_gpl(struct gpio_chip *chip, unsigned pin)
+static int s3c64xx_gpio2int_gpl(struct gpio_chip *chip, unsigned pin)
 {
         return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO;
 }
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index e85192a86fbe..a80a3163dd30 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -28,6 +28,7 @@
 #include <linux/delay.h>
 #include <linux/smsc911x.h>
 #include <linux/regulator/fixed.h>
+#include <linux/regulator/machine.h>
 
 #ifdef CONFIG_SMDK6410_WM1190_EV1
 #include <linux/mfd/wm8350/core.h>
@@ -351,7 +352,7 @@ static struct regulator_init_data smdk6410_vddpll = {
 /* VDD_UH_MMC, LDO5 on J5 */
 static struct regulator_init_data smdk6410_vdduh_mmc = {
         .constraints = {
-                .name = "PVDD_UH/PVDD_MMC",
+                .name = "PVDD_UH+PVDD_MMC",
                 .always_on = 1,
         },
 };
@@ -417,7 +418,7 @@ static struct regulator_init_data smdk6410_vddaudio = {
 /* S3C64xx internal logic & PLL */
 static struct regulator_init_data wm8350_dcdc1_data = {
         .constraints = {
-                .name = "PVDD_INT/PVDD_PLL",
+                .name = "PVDD_INT+PVDD_PLL",
                 .min_uV = 1200000,
                 .max_uV = 1200000,
                 .always_on = 1,
@@ -452,7 +453,7 @@ static struct regulator_consumer_supply wm8350_dcdc4_consumers[] = {
 
 static struct regulator_init_data wm8350_dcdc4_data = {
         .constraints = {
-                .name = "PVDD_HI/PVDD_EXT/PVDD_SYS/PVCCM2MTV",
+                .name = "PVDD_HI+PVDD_EXT+PVDD_SYS+PVCCM2MTV",
                 .min_uV = 3000000,
                 .max_uV = 3000000,
                 .always_on = 1,
@@ -464,7 +465,7 @@ static struct regulator_init_data wm8350_dcdc4_data = {
 /* OTGi/1190-EV1 HPVDD & AVDD */
 static struct regulator_init_data wm8350_ldo4_data = {
         .constraints = {
-                .name = "PVDD_OTGI/HPVDD/AVDD",
+                .name = "PVDD_OTGI+HPVDD+AVDD",
                 .min_uV = 1200000,
                 .max_uV = 1200000,
                 .apply_uV = 1,
@@ -552,7 +553,7 @@ static struct wm831x_backlight_pdata wm1192_backlight_pdata = {
 
 static struct regulator_init_data wm1192_dcdc3 = {
         .constraints = {
-                .name = "PVDD_MEM/PVDD_GPS",
+                .name = "PVDD_MEM+PVDD_GPS",
                 .always_on = 1,
         },
 };
@@ -563,7 +564,7 @@ static struct regulator_consumer_supply wm1192_ldo1_consumers[] = {
 
 static struct regulator_init_data wm1192_ldo1 = {
         .constraints = {
-                .name = "PVDD_LCD/PVDD_EXT",
+                .name = "PVDD_LCD+PVDD_EXT",
                 .always_on = 1,
         },
         .consumer_supplies = wm1192_ldo1_consumers,
diff --git a/arch/arm/mach-s3c64xx/setup-keypad.c b/arch/arm/mach-s3c64xx/setup-keypad.c
index f8ed0d22db70..1d4d0ee9e870 100644
--- a/arch/arm/mach-s3c64xx/setup-keypad.c
+++ b/arch/arm/mach-s3c64xx/setup-keypad.c
@@ -17,7 +17,7 @@
 void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols)
 {
         /* Set all the necessary GPK pins to special-function 3: KP_ROW[x] */
-        s3c_gpio_cfgrange_nopull(S3C64XX_GPK(8), 8 + rows, S3C_GPIO_SFN(3));
+        s3c_gpio_cfgrange_nopull(S3C64XX_GPK(8), rows, S3C_GPIO_SFN(3));
 
         /* Set all the necessary GPL pins to special-function 3: KP_COL[x] */
         s3c_gpio_cfgrange_nopull(S3C64XX_GPL(0), cols, S3C_GPIO_SFN(3));
diff --git a/arch/arm/mach-s3c64xx/setup-sdhci.c b/arch/arm/mach-s3c64xx/setup-sdhci.c
index 1a942037c4ef..f344a222bc84 100644
--- a/arch/arm/mach-s3c64xx/setup-sdhci.c
+++ b/arch/arm/mach-s3c64xx/setup-sdhci.c
@@ -56,7 +56,7 @@ void s3c6400_setup_sdhci_cfg_card(struct platform_device *dev,
         else
                 ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
 
-        printk(KERN_INFO "%s: CTRL 2=%08x, 3=%08x\n", __func__, ctrl2, ctrl3);
+        pr_debug("%s: CTRL 2=%08x, 3=%08x\n", __func__, ctrl2, ctrl3);
         writel(ctrl2, r + S3C_SDHCI_CONTROL2);
         writel(ctrl3, r + S3C_SDHCI_CONTROL3);
 }
diff --git a/arch/arm/mach-s5p64x0/include/mach/gpio.h b/arch/arm/mach-s5p64x0/include/mach/gpio.h
index 5486c8f01f1d..adb5f298ead8 100644
--- a/arch/arm/mach-s5p64x0/include/mach/gpio.h
+++ b/arch/arm/mach-s5p64x0/include/mach/gpio.h
@@ -23,7 +23,7 @@
 #define S5P6440_GPIO_A_NR       (6)
 #define S5P6440_GPIO_B_NR       (7)
 #define S5P6440_GPIO_C_NR       (8)
-#define S5P6440_GPIO_F_NR       (2)
+#define S5P6440_GPIO_F_NR       (16)
 #define S5P6440_GPIO_G_NR       (7)
 #define S5P6440_GPIO_H_NR       (10)
 #define S5P6440_GPIO_I_NR       (16)
@@ -36,7 +36,7 @@
 #define S5P6450_GPIO_B_NR       (7)
 #define S5P6450_GPIO_C_NR       (8)
 #define S5P6450_GPIO_D_NR       (8)
-#define S5P6450_GPIO_F_NR       (2)
+#define S5P6450_GPIO_F_NR       (16)
 #define S5P6450_GPIO_G_NR       (14)
 #define S5P6450_GPIO_H_NR       (10)
 #define S5P6450_GPIO_I_NR       (16)
diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c
index 2123b96b5638..4303a86e6e38 100644
--- a/arch/arm/mach-shmobile/board-ag5evm.c
+++ b/arch/arm/mach-shmobile/board-ag5evm.c
@@ -454,6 +454,7 @@ static void __init ag5evm_init(void)
         gpio_direction_output(GPIO_PORT217, 0);
         mdelay(1);
         gpio_set_value(GPIO_PORT217, 1);
+        mdelay(100);
 
         /* LCD backlight controller */
         gpio_request(GPIO_PORT235, NULL); /* RESET */
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index 3cf0951caa2d..81d6536552a9 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -1303,7 +1303,7 @@ static void __init ap4evb_init(void)
 
         lcdc_info.clock_source                  = LCDC_CLK_BUS;
         lcdc_info.ch[0].interface_type          = RGB18;
-        lcdc_info.ch[0].clock_divider           = 2;
+        lcdc_info.ch[0].clock_divider           = 3;
         lcdc_info.ch[0].flags                   = 0;
         lcdc_info.ch[0].lcd_size_cfg.width      = 152;
         lcdc_info.ch[0].lcd_size_cfg.height     = 91;
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index fb4213a4e15a..1657eac5dde2 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -303,7 +303,7 @@ static struct sh_mobile_lcdc_info lcdc_info = {
                 .lcd_cfg = mackerel_lcdc_modes,
                 .num_cfg = ARRAY_SIZE(mackerel_lcdc_modes),
                 .interface_type         = RGB24,
-                .clock_divider          = 2,
+                .clock_divider          = 3,
                 .flags                  = 0,
                 .lcd_size_cfg.width     = 152,
                 .lcd_size_cfg.height    = 91,
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index ddd4a1b775f0..7e58904c1c8c 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -263,7 +263,7 @@ static struct clk div6_clks[DIV6_NR] = {
 };
 
 enum { MSTP001,
-        MSTP125, MSTP118, MSTP116, MSTP100,
+        MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, MSTP118, MSTP116, MSTP100,
         MSTP219,
         MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
         MSTP331, MSTP329, MSTP325, MSTP323, MSTP312,
@@ -275,6 +275,10 @@ enum { MSTP001,
 
 static struct clk mstp_clks[MSTP_NR] = {
         [MSTP001] = MSTP(&div4_clks[DIV4_HP], SMSTPCR0, 1, 0), /* IIC2 */
+        [MSTP129] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 29, 0), /* CEU1 */
+        [MSTP128] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 28, 0), /* CSI2-RX1 */
+        [MSTP127] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 27, 0), /* CEU0 */
+        [MSTP126] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 26, 0), /* CSI2-RX0 */
         [MSTP125] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
         [MSTP118] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX0 */
         [MSTP116] = MSTP(&div4_clks[DIV4_HP], SMSTPCR1, 16, 0), /* IIC0 */
@@ -306,6 +310,9 @@ static struct clk_lookup lookups[] = {
         CLKDEV_CON_ID("r_clk", &r_clk),
 
         /* DIV6 clocks */
+        CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
+        CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]),
+        CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]),
         CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSIT]),
         CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSIT]),
         CLKDEV_ICK_ID("dsi0p_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]),
@@ -313,11 +320,15 @@ static struct clk_lookup lookups[] = {
 
         /* MSTP32 clocks */
         CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* I2C2 */
-        CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]), /* LCDC0 */
+        CLKDEV_DEV_ID("sh_mobile_ceu.1", &mstp_clks[MSTP129]), /* CEU1 */
+        CLKDEV_DEV_ID("sh-mobile-csi2.1", &mstp_clks[MSTP128]), /* CSI2-RX1 */
+        CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[MSTP127]), /* CEU0 */
+        CLKDEV_DEV_ID("sh-mobile-csi2.0", &mstp_clks[MSTP126]), /* CSI2-RX0 */
         CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]), /* TMU00 */
         CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP125]), /* TMU01 */
-        CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* I2C0 */
         CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX */
+        CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* I2C0 */
+        CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]), /* LCDC0 */
         CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP219]), /* SCIFA7 */
         CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
         CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]), /* SCIFB */
diff --git a/arch/arm/mach-shmobile/include/mach/head-ap4evb.txt b/arch/arm/mach-shmobile/include/mach/head-ap4evb.txt
index efd3687ba190..3029aba38688 100644
--- a/arch/arm/mach-shmobile/include/mach/head-ap4evb.txt
+++ b/arch/arm/mach-shmobile/include/mach/head-ap4evb.txt
@@ -6,13 +6,10 @@ LIST "RWT Setting"
 EW 0xE6020004, 0xA500
 EW 0xE6030004, 0xA500
 
-DD 0x01001000, 0x01001000
-
 LIST "GPIO Setting"
 EB 0xE6051013, 0xA2
 
 LIST "CPG"
-ED 0xE6150080, 0x00000180
 ED 0xE61500C0, 0x00000002
 
 WAIT 1, 0xFE40009C
@@ -37,6 +34,9 @@ ED 0xE615002C, 0x93000040
 
 WAIT 1, 0xFE40009C
 
+LIST "SUB/USBClk"
+ED 0xE6150080, 0x00000180
+
 LIST "BSC"
 ED 0xFEC10000, 0x00E0001B
 
@@ -53,7 +53,7 @@ ED 0xFE400048, 0x20C18505
 ED 0xFE40004C, 0x00110209
 ED 0xFE400010, 0x00000087
 
-WAIT 10, 0xFE40009C
+WAIT 30, 0xFE40009C
 
 ED 0xFE400084, 0x0000003F
 EB 0xFE500000, 0x00
@@ -84,7 +84,7 @@ ED 0xE6150004, 0x80331050
 
 WAIT 1, 0xFE40009C
 
-ED 0xE6150354, 0x00000002
+ED 0xFE400354, 0x01AD8002
 
 LIST "SCIF0 - Serial port for earlyprintk"
 EB 0xE6053098, 0x11
diff --git a/arch/arm/mach-shmobile/include/mach/head-mackerel.txt b/arch/arm/mach-shmobile/include/mach/head-mackerel.txt
index efd3687ba190..3029aba38688 100644
--- a/arch/arm/mach-shmobile/include/mach/head-mackerel.txt
+++ b/arch/arm/mach-shmobile/include/mach/head-mackerel.txt
@@ -6,13 +6,10 @@ LIST "RWT Setting"
 EW 0xE6020004, 0xA500
 EW 0xE6030004, 0xA500
 
-DD 0x01001000, 0x01001000
-
 LIST "GPIO Setting"
 EB 0xE6051013, 0xA2
 
 LIST "CPG"
-ED 0xE6150080, 0x00000180
 ED 0xE61500C0, 0x00000002
 
 WAIT 1, 0xFE40009C
@@ -37,6 +34,9 @@ ED 0xE615002C, 0x93000040
 
 WAIT 1, 0xFE40009C
 
+LIST "SUB/USBClk"
+ED 0xE6150080, 0x00000180
+
 LIST "BSC"
 ED 0xFEC10000, 0x00E0001B
 
@@ -53,7 +53,7 @@ ED 0xFE400048, 0x20C18505
 ED 0xFE40004C, 0x00110209
 ED 0xFE400010, 0x00000087
 
-WAIT 10, 0xFE40009C
+WAIT 30, 0xFE40009C
 
 ED 0xFE400084, 0x0000003F
 EB 0xFE500000, 0x00
@@ -84,7 +84,7 @@ ED 0xE6150004, 0x80331050
 
 WAIT 1, 0xFE40009C
 
-ED 0xE6150354, 0x00000002
+ED 0xFE400354, 0x01AD8002
 
 LIST "SCIF0 - Serial port for earlyprintk"
 EB 0xE6053098, 0x11
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
index 1dd97e7461c9..5288130be96e 100644
--- a/arch/arm/plat-omap/include/plat/common.h
+++ b/arch/arm/plat-omap/include/plat/common.h
@@ -56,10 +56,6 @@ struct omap_globals {
         unsigned long   prm;            /* Power and Reset Management */
         unsigned long   cm;             /* Clock Management */
         unsigned long   cm2;
-        unsigned long   uart1_phys;
-        unsigned long   uart2_phys;
-        unsigned long   uart3_phys;
-        unsigned long   uart4_phys;
 };
 
 void omap2_set_globals_242x(void);
diff --git a/arch/arm/plat-samsung/dev-uart.c b/arch/arm/plat-samsung/dev-uart.c
index 3776cd952450..5928105490fa 100644
--- a/arch/arm/plat-samsung/dev-uart.c
+++ b/arch/arm/plat-samsung/dev-uart.c
@@ -15,6 +15,8 @@
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
 
+#include <plat/devs.h>
+
 /* uart devices */
 
 static struct platform_device s3c24xx_uart_device0 = {
diff --git a/arch/blackfin/lib/outs.S b/arch/blackfin/lib/outs.S
index 250f4d4b9436..06a5e674401f 100644
--- a/arch/blackfin/lib/outs.S
+++ b/arch/blackfin/lib/outs.S
@@ -13,6 +13,8 @@
 .align 2
 
 ENTRY(_outsl)
+        CC = R2 == 0;
+        IF CC JUMP 1f;
         P0 = R0;        /* P0 = port */
         P1 = R1;        /* P1 = address */
         P2 = R2;        /* P2 = count */
@@ -20,10 +22,12 @@ ENTRY(_outsl)
         LSETUP( .Llong_loop_s, .Llong_loop_e) LC0 = P2;
 .Llong_loop_s: R0 = [P1++];
 .Llong_loop_e: [P0] = R0;
-        RTS;
+1:      RTS;
 ENDPROC(_outsl)
 
 ENTRY(_outsw)
+        CC = R2 == 0;
+        IF CC JUMP 1f;
         P0 = R0;        /* P0 = port */
         P1 = R1;        /* P1 = address */
         P2 = R2;        /* P2 = count */
@@ -31,10 +35,12 @@ ENTRY(_outsw)
         LSETUP( .Lword_loop_s, .Lword_loop_e) LC0 = P2;
 .Lword_loop_s: R0 = W[P1++];
 .Lword_loop_e: W[P0] = R0;
-        RTS;
+1:      RTS;
 ENDPROC(_outsw)
 
 ENTRY(_outsb)
+        CC = R2 == 0;
+        IF CC JUMP 1f;
         P0 = R0;        /* P0 = port */
         P1 = R1;        /* P1 = address */
         P2 = R2;        /* P2 = count */
@@ -42,10 +48,12 @@ ENTRY(_outsb)
         LSETUP( .Lbyte_loop_s, .Lbyte_loop_e) LC0 = P2;
 .Lbyte_loop_s: R0 = B[P1++];
 .Lbyte_loop_e: B[P0] = R0;
-        RTS;
+1:      RTS;
 ENDPROC(_outsb)
 
 ENTRY(_outsw_8)
+        CC = R2 == 0;
+        IF CC JUMP 1f;
         P0 = R0;        /* P0 = port */
         P1 = R1;        /* P1 = address */
         P2 = R2;        /* P2 = count */
@@ -56,5 +64,5 @@ ENTRY(_outsw_8)
                 R0 = R0 << 8;
                 R0 = R0 + R1;
 .Lword8_loop_e: W[P0] = R0;
-        RTS;
+1:      RTS;
 ENDPROC(_outsw_8)
diff --git a/arch/blackfin/mach-common/cache.S b/arch/blackfin/mach-common/cache.S
index 790c767ca95a..ab4a925a443e 100644
--- a/arch/blackfin/mach-common/cache.S
+++ b/arch/blackfin/mach-common/cache.S
@@ -58,6 +58,8 @@
 1:
 .ifeqs "\flushins", BROK_FLUSH_INST
         \flushins [P0++];
+        nop;
+        nop;
 2:      nop;
 .else
 2:      \flushins [P0++];
diff --git a/arch/powerpc/include/asm/machdep.h b/arch/powerpc/include/asm/machdep.h
index 991d5998d6be..fe56a23e1ff0 100644
--- a/arch/powerpc/include/asm/machdep.h
+++ b/arch/powerpc/include/asm/machdep.h
@@ -240,6 +240,12 @@ struct machdep_calls {
          * claims to support kexec.
          */
         int (*machine_kexec_prepare)(struct kimage *image);
+
+        /* Called to perform the _real_ kexec.
+         * Do NOT allocate memory or fail here. We are past the point of
+         * no return.
+         */
+        void (*machine_kexec)(struct kimage *image);
 #endif /* CONFIG_KEXEC */
 
 #ifdef CONFIG_SUSPEND
diff --git a/arch/powerpc/kernel/machine_kexec.c b/arch/powerpc/kernel/machine_kexec.c
index 49a170af8145..a5f8672eeff3 100644
--- a/arch/powerpc/kernel/machine_kexec.c
+++ b/arch/powerpc/kernel/machine_kexec.c
@@ -87,7 +87,10 @@ void machine_kexec(struct kimage *image)
 
         save_ftrace_enabled = __ftrace_enabled_save();
 
-        default_machine_kexec(image);
+        if (ppc_md.machine_kexec)
+                ppc_md.machine_kexec(image);
+        else
+                default_machine_kexec(image);
 
         __ftrace_enabled_restore(save_ftrace_enabled);
 
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index 7a1d5cb76932..8303a6c65ef7 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -353,6 +353,7 @@ static void switch_booke_debug_regs(struct thread_struct *new_thread)
                         prime_debug_regs(new_thread);
 }
 #else   /* !CONFIG_PPC_ADV_DEBUG_REGS */
+#ifndef CONFIG_HAVE_HW_BREAKPOINT
 static void set_debug_reg_defaults(struct thread_struct *thread)
 {
         if (thread->dabr) {
@@ -360,6 +361,7 @@ static void set_debug_reg_defaults(struct thread_struct *thread)
                 set_dabr(0);
         }
 }
+#endif /* !CONFIG_HAVE_HW_BREAKPOINT */
 #endif  /* CONFIG_PPC_ADV_DEBUG_REGS */
 
 int set_dabr(unsigned long dabr)
@@ -670,11 +672,11 @@ void flush_thread(void)
 {
         discard_lazy_cpu_state();
 
-#ifdef CONFIG_HAVE_HW_BREAKPOINTS
+#ifdef CONFIG_HAVE_HW_BREAKPOINT
         flush_ptrace_hw_breakpoint(current);
-#else /* CONFIG_HAVE_HW_BREAKPOINTS */
+#else /* CONFIG_HAVE_HW_BREAKPOINT */
         set_debug_reg_defaults(&current->thread);
-#endif /* CONFIG_HAVE_HW_BREAKPOINTS */
+#endif /* CONFIG_HAVE_HW_BREAKPOINT */
 }
 
 void
diff --git a/arch/powerpc/mm/tlb_hash64.c b/arch/powerpc/mm/tlb_hash64.c
index 1ec06576f619..c14d09f614f3 100644
--- a/arch/powerpc/mm/tlb_hash64.c
+++ b/arch/powerpc/mm/tlb_hash64.c
@@ -38,13 +38,11 @@ DEFINE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch);
  * neesd to be flushed. This function will either perform the flush
  * immediately or will batch it up if the current CPU has an active
  * batch on it.
- *
- * Must be called from within some kind of spinlock/non-preempt region...
  */
 void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
                      pte_t *ptep, unsigned long pte, int huge)
 {
-        struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
+        struct ppc64_tlb_batch *batch = &get_cpu_var(ppc64_tlb_batch);
         unsigned long vsid, vaddr;
         unsigned int psize;
         int ssize;
@@ -99,6 +97,7 @@ void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
          */
         if (!batch->active) {
                 flush_hash_page(vaddr, rpte, psize, ssize, 0);
+                put_cpu_var(ppc64_tlb_batch);
                 return;
         }
 
@@ -127,6 +126,7 @@ void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
         batch->index = ++i;
         if (i >= PPC64_TLB_BATCH_NR)
                 __flush_tlb_pending(batch);
+        put_cpu_var(ppc64_tlb_batch);
 }
 
 /*
diff --git a/arch/sh/include/asm/sections.h b/arch/sh/include/asm/sections.h
index a78701da775b..4a5350037c8f 100644
--- a/arch/sh/include/asm/sections.h
+++ b/arch/sh/include/asm/sections.h
@@ -3,7 +3,7 @@
 
 #include <asm-generic/sections.h>
 
-extern void __nosave_begin, __nosave_end;
+extern long __nosave_begin, __nosave_end;
 extern long __machvec_start, __machvec_end;
 extern char __uncached_start, __uncached_end;
 extern char _ebss[];
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7750.c b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
index 672944f5b19c..e53b4b38bd11 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7750.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
@@ -14,7 +14,7 @@
 #include <linux/io.h>
 #include <linux/sh_timer.h>
 #include <linux/serial_sci.h>
-#include <asm/machtypes.h>
+#include <generated/machtypes.h>
 
 static struct resource rtc_resources[] = {
         [0] = {
@@ -255,12 +255,17 @@ static struct platform_device *sh7750_early_devices[] __initdata = {
 
 void __init plat_early_device_setup(void)
 {
+        struct platform_device *dev[1];
+
         if (mach_is_rts7751r2d()) {
                 scif_platform_data.scscr |= SCSCR_CKE1;
-                early_platform_add_devices(&scif_device, 1);
+                dev[0] = &scif_device;
+                early_platform_add_devices(dev, 1);
         } else {
-                early_platform_add_devices(&sci_device, 1);
-                early_platform_add_devices(&scif_device, 1);
+                dev[0] = &sci_device;
+                early_platform_add_devices(dev, 1);
+                dev[0] = &scif_device;
+                early_platform_add_devices(dev, 1);
         }
 
         early_platform_add_devices(sh7750_early_devices,
diff --git a/arch/sh/lib/delay.c b/arch/sh/lib/delay.c
index faa8f86c0db4..0901b2f14e15 100644
--- a/arch/sh/lib/delay.c
+++ b/arch/sh/lib/delay.c
@@ -10,6 +10,16 @@
 void __delay(unsigned long loops)
 {
         __asm__ __volatile__(
+                /*
+                 * ST40-300 appears to have an issue with this code,
+                 * normally taking two cycles each loop, as with all
+                 * other SH variants. If however the branch and the
+                 * delay slot straddle an 8 byte boundary, this increases
+                 * to 3 cycles.
+                 * This align directive ensures this doesn't occur.
+                 */
+                ".balign 8\n\t"
+
                 "tst    %0, %0\n\t"
                 "1:\t"
                 "bf/s   1b\n\t"
diff --git a/arch/sh/mm/cache.c b/arch/sh/mm/cache.c
index 88d3dc3d30d5..5a580ea04429 100644
--- a/arch/sh/mm/cache.c
+++ b/arch/sh/mm/cache.c
@@ -108,7 +108,8 @@ void copy_user_highpage(struct page *to, struct page *from,
                 kunmap_atomic(vfrom, KM_USER0);
         }
 
-        if (pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
+        if (pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK) ||
+            (vma->vm_flags & VM_EXEC))
                 __flush_purge_region(vto, PAGE_SIZE);
 
         kunmap_atomic(vto, KM_USER1);
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 4d0dfa0d998e..43a18c77676d 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -36,6 +36,11 @@
 #define MSR_IA32_PERFCTR1               0x000000c2
 #define MSR_FSB_FREQ                    0x000000cd
 
+#define MSR_NHM_SNB_PKG_CST_CFG_CTL     0x000000e2
+#define NHM_C3_AUTO_DEMOTE              (1UL << 25)
+#define NHM_C1_AUTO_DEMOTE              (1UL << 26)
+#define ATM_LNC_C6_AUTO_DEMOTE          (1UL << 25)
+
 #define MSR_MTRRcap                     0x000000fe
 #define MSR_IA32_BBL_CR_CTL             0x00000119
 
diff --git a/arch/x86/kernel/cpu/cpufreq/p4-clockmod.c b/arch/x86/kernel/cpu/cpufreq/p4-clockmod.c
index bd1cac747f67..52c93648e492 100644
--- a/arch/x86/kernel/cpu/cpufreq/p4-clockmod.c
+++ b/arch/x86/kernel/cpu/cpufreq/p4-clockmod.c
@@ -158,9 +158,9 @@ static unsigned int cpufreq_p4_get_frequency(struct cpuinfo_x86 *c)
 {
         if (c->x86 == 0x06) {
                 if (cpu_has(c, X86_FEATURE_EST))
-                        printk(KERN_WARNING PFX "Warning: EST-capable CPU "
-                               "detected. The acpi-cpufreq module offers "
-                               "voltage scaling in addition of frequency "
+                        printk_once(KERN_WARNING PFX "Warning: EST-capable "
+                               "CPU detected. The acpi-cpufreq module offers "
+                               "voltage scaling in addition to frequency "
                                "scaling. You should use that instead of "
                                "p4-clockmod, if possible.\n");
                 switch (c->x86_model) {
diff --git a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
index 35c7e65e59be..c567dec854f6 100644
--- a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
+++ b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
@@ -1537,6 +1537,7 @@ static struct notifier_block cpb_nb = {
 static int __cpuinit powernowk8_init(void)
 {
         unsigned int i, supported_cpus = 0, cpu;
+        int rv;
 
         for_each_online_cpu(i) {
                 int rc;
@@ -1555,14 +1556,14 @@ static int __cpuinit powernowk8_init(void)
 
                 cpb_capable = true;
 
-                register_cpu_notifier(&cpb_nb);
-
                 msrs = msrs_alloc();
                 if (!msrs) {
                         printk(KERN_ERR "%s: Error allocating msrs!\n", __func__);
                         return -ENOMEM;
                 }
 
+                register_cpu_notifier(&cpb_nb);
+
                 rdmsr_on_cpus(cpu_online_mask, MSR_K7_HWCR, msrs);
 
                 for_each_cpu(cpu, cpu_online_mask) {
@@ -1574,7 +1575,13 @@ static int __cpuinit powernowk8_init(void)
                         (cpb_enabled ? "on" : "off"));
         }
 
-        return cpufreq_register_driver(&cpufreq_amd64_driver);
+        rv = cpufreq_register_driver(&cpufreq_amd64_driver);
+        if (rv < 0 && boot_cpu_has(X86_FEATURE_CPB)) {
+                unregister_cpu_notifier(&cpb_nb);
+                msrs_free(msrs);
+                msrs = NULL;
+        }
+        return rv;
 }
 
 /* driver entry point for term */
diff --git a/arch/x86/platform/olpc/olpc_dt.c b/arch/x86/platform/olpc/olpc_dt.c
index dab874647530..044bda5b3174 100644
--- a/arch/x86/platform/olpc/olpc_dt.c
+++ b/arch/x86/platform/olpc/olpc_dt.c
@@ -140,8 +140,7 @@ void * __init prom_early_alloc(unsigned long size)
                  * wasted bootmem) and hand off chunks of it to callers.
                  */
                 res = alloc_bootmem(chunk_size);
-                if (!res)
-                        return NULL;
+                BUG_ON(!res);
                 prom_early_allocated += chunk_size;
                 memset(res, 0, chunk_size);
                 free_mem = chunk_size;