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authorJuergen Beisert <j.beisert@pengutronix.de>2008-07-05 04:02:57 -0400
committerRobert Schwebel <r.schwebel@pengutronix.de>2008-07-05 04:02:57 -0400
commitfc80a5e3d0480d416e4f53b0680aaf525b5076d8 (patch)
treee058d92028489487af27582fb076c915c4ad6cee /arch
parent32dc80c9cb13a7ce686bcc26efcf39e35719b466 (diff)
i.MX2 family: Add basic device support
This patch adds a few on-chip devices for i.MX21/i.MX27 procesors. Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-mx2/Makefile2
-rw-r--r--arch/arm/mach-mx2/devices.c231
2 files changed, 232 insertions, 1 deletions
diff --git a/arch/arm/mach-mx2/Makefile b/arch/arm/mach-mx2/Makefile
index 937192dc57a7..db4d9c6f2738 100644
--- a/arch/arm/mach-mx2/Makefile
+++ b/arch/arm/mach-mx2/Makefile
@@ -4,4 +4,4 @@
4 4
5# Object file lists. 5# Object file lists.
6 6
7obj-y := system.o generic.o 7obj-y := system.o generic.o devices.o
diff --git a/arch/arm/mach-mx2/devices.c b/arch/arm/mach-mx2/devices.c
new file mode 100644
index 000000000000..a1f44c3c5315
--- /dev/null
+++ b/arch/arm/mach-mx2/devices.c
@@ -0,0 +1,231 @@
1/*
2 * Author: MontaVista Software, Inc.
3 * <source@mvista.com>
4 *
5 * Based on the OMAP devices.c
6 *
7 * 2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 *
12 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
13 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version 2
18 * of the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
27 * MA 02110-1301, USA.
28 */
29#include <linux/module.h>
30#include <linux/kernel.h>
31#include <linux/init.h>
32#include <linux/platform_device.h>
33#include <linux/gpio.h>
34
35#include <asm/hardware.h>
36
37/*
38 * Resource definition for the MXC IrDA
39 */
40static struct resource mxc_irda_resources[] = {
41 [0] = {
42 .start = UART3_BASE_ADDR,
43 .end = UART3_BASE_ADDR + SZ_4K - 1,
44 .flags = IORESOURCE_MEM,
45 },
46 [1] = {
47 .start = MXC_INT_UART3,
48 .end = MXC_INT_UART3,
49 .flags = IORESOURCE_IRQ,
50 },
51};
52
53/* Platform Data for MXC IrDA */
54struct platform_device mxc_irda_device = {
55 .name = "mxc_irda",
56 .id = 0,
57 .num_resources = ARRAY_SIZE(mxc_irda_resources),
58 .resource = mxc_irda_resources,
59};
60
61/*
62 * General Purpose Timer
63 * - i.MX1: 2 timer (slighly different register handling)
64 * - i.MX21: 3 timer
65 * - i.MX27: 6 timer
66 */
67
68/* We use gpt0 as system timer, so do not add a device for this one */
69
70static struct resource timer1_resources[] = {
71 [0] = {
72 .start = GPT2_BASE_ADDR,
73 .end = GPT2_BASE_ADDR + 0x17,
74 .flags = IORESOURCE_MEM
75 },
76 [1] = {
77 .start = MXC_INT_GPT2,
78 .end = MXC_INT_GPT2,
79 .flags = IORESOURCE_IRQ,
80 }
81};
82
83struct platform_device mxc_gpt1 = {
84 .name = "imx_gpt",
85 .id = 1,
86 .num_resources = ARRAY_SIZE(timer1_resources),
87 .resource = timer1_resources
88};
89
90static struct resource timer2_resources[] = {
91 [0] = {
92 .start = GPT3_BASE_ADDR,
93 .end = GPT3_BASE_ADDR + 0x17,
94 .flags = IORESOURCE_MEM
95 },
96 [1] = {
97 .start = MXC_INT_GPT3,
98 .end = MXC_INT_GPT3,
99 .flags = IORESOURCE_IRQ,
100 }
101};
102
103struct platform_device mxc_gpt2 = {
104 .name = "imx_gpt",
105 .id = 2,
106 .num_resources = ARRAY_SIZE(timer2_resources),
107 .resource = timer2_resources
108};
109
110#ifdef CONFIG_MACH_MX27
111static struct resource timer3_resources[] = {
112 [0] = {
113 .start = GPT4_BASE_ADDR,
114 .end = GPT4_BASE_ADDR + 0x17,
115 .flags = IORESOURCE_MEM
116 },
117 [1] = {
118 .start = MXC_INT_GPT4,
119 .end = MXC_INT_GPT4,
120 .flags = IORESOURCE_IRQ,
121 }
122};
123
124struct platform_device mxc_gpt3 = {
125 .name = "imx_gpt",
126 .id = 3,
127 .num_resources = ARRAY_SIZE(timer3_resources),
128 .resource = timer3_resources
129};
130
131static struct resource timer4_resources[] = {
132 [0] = {
133 .start = GPT5_BASE_ADDR,
134 .end = GPT5_BASE_ADDR + 0x17,
135 .flags = IORESOURCE_MEM
136 },
137 [1] = {
138 .start = MXC_INT_GPT5,
139 .end = MXC_INT_GPT5,
140 .flags = IORESOURCE_IRQ,
141 }
142};
143
144struct platform_device mxc_gpt4 = {
145 .name = "imx_gpt",
146 .id = 4,
147 .num_resources = ARRAY_SIZE(timer4_resources),
148 .resource = timer4_resources
149};
150
151static struct resource timer5_resources[] = {
152 [0] = {
153 .start = GPT6_BASE_ADDR,
154 .end = GPT6_BASE_ADDR + 0x17,
155 .flags = IORESOURCE_MEM
156 },
157 [1] = {
158 .start = MXC_INT_GPT6,
159 .end = MXC_INT_GPT6,
160 .flags = IORESOURCE_IRQ,
161 }
162};
163
164struct platform_device mxc_gpt5 = {
165 .name = "imx_gpt",
166 .id = 5,
167 .num_resources = ARRAY_SIZE(timer5_resources),
168 .resource = timer5_resources
169};
170#endif
171
172/*
173 * Watchdog:
174 * - i.MX1
175 * - i.MX21
176 * - i.MX27
177 */
178static struct resource mxc_wdt_resources[] = {
179 {
180 .start = WDOG_BASE_ADDR,
181 .end = WDOG_BASE_ADDR + 0x30,
182 .flags = IORESOURCE_MEM,
183 },
184};
185
186struct platform_device mxc_wdt = {
187 .name = "mxc_wdt",
188 .id = 0,
189 .num_resources = ARRAY_SIZE(mxc_wdt_resources),
190 .resource = mxc_wdt_resources,
191};
192
193/* GPIO port description */
194static struct mxc_gpio_port imx_gpio_ports[] = {
195 [0] = {
196 .chip.label = "gpio-0",
197 .irq = MXC_INT_GPIO,
198 .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 0),
199 .virtual_irq_start = MXC_MAX_INT_LINES,
200 },
201 [1] = {
202 .chip.label = "gpio-1",
203 .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 1),
204 .virtual_irq_start = MXC_MAX_INT_LINES + 32,
205 },
206 [2] = {
207 .chip.label = "gpio-2",
208 .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 2),
209 .virtual_irq_start = MXC_MAX_INT_LINES + 64,
210 },
211 [3] = {
212 .chip.label = "gpio-3",
213 .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 3),
214 .virtual_irq_start = MXC_MAX_INT_LINES + 96,
215 },
216 [4] = {
217 .chip.label = "gpio-4",
218 .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 4),
219 .virtual_irq_start = MXC_MAX_INT_LINES + 128,
220 },
221 [5] = {
222 .chip.label = "gpio-5",
223 .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 5),
224 .virtual_irq_start = MXC_MAX_INT_LINES + 160,
225 }
226};
227
228int __init mxc_register_gpios(void)
229{
230 return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
231}