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authorPaul Walmsley <paul@pwsan.com>2008-08-19 04:08:43 -0400
committerTony Lindgren <tony@atomide.com>2008-08-19 04:08:43 -0400
commitecb24aa129c6d4b2152571f856320aa7dea41676 (patch)
tree9028db53fc4636b77b0ef27d4e26cb2d140a5876 /arch
parentfe6a58f8f50500a4c9a82da4a9bdae41c1500fa0 (diff)
ARM: OMAP: Powerdomain: Add OMAP3 powerdomains
Add OMAP3-specific powerdomains. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-omap2/powerdomains.h30
-rw-r--r--arch/arm/mach-omap2/powerdomains34xx.h327
-rw-r--r--arch/arm/mach-omap2/prcm-common.h3
-rw-r--r--arch/arm/mach-omap2/prm-regbits-34xx.h11
4 files changed, 364 insertions, 7 deletions
diff --git a/arch/arm/mach-omap2/powerdomains.h b/arch/arm/mach-omap2/powerdomains.h
index 325e2ba04067..1e151faebbd3 100644
--- a/arch/arm/mach-omap2/powerdomains.h
+++ b/arch/arm/mach-omap2/powerdomains.h
@@ -98,16 +98,28 @@ static struct pwrdm_dep gfx_sgx_wkdeps[] = {
98 { NULL }, 98 { NULL },
99}; 99};
100 100
101/*
102 * 3430: CM_SLEEPDEP_CAM: MPU
103 * 3430ES1: CM_SLEEPDEP_GFX: MPU
104 * 3430ES2: CM_SLEEPDEP_SGX: MPU
105 */
106static struct pwrdm_dep cam_gfx_sleepdeps[] = {
107 {
108 .pwrdm_name = "mpu_pwrdm",
109 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
110 },
111 { NULL },
112};
113
101 114
102#include "powerdomains24xx.h" 115#include "powerdomains24xx.h"
116#include "powerdomains34xx.h"
103 117
104 118
105/* 119/*
106 * OMAP2/3 common powerdomains 120 * OMAP2/3 common powerdomains
107 */ 121 */
108 122
109/* XXX add sleepdeps for this powerdomain : 3430 */
110
111/* 123/*
112 * The GFX powerdomain is not present on 3430ES2, but currently we do not 124 * The GFX powerdomain is not present on 3430ES2, but currently we do not
113 * have a macro to filter it out at compile-time. 125 * have a macro to filter it out at compile-time.
@@ -118,6 +130,7 @@ static struct powerdomain gfx_pwrdm = {
118 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | 130 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
119 CHIP_IS_OMAP3430ES1), 131 CHIP_IS_OMAP3430ES1),
120 .wkdep_srcs = gfx_sgx_wkdeps, 132 .wkdep_srcs = gfx_sgx_wkdeps,
133 .sleepdep_srcs = cam_gfx_sleepdeps,
121 .pwrsts = PWRSTS_OFF_RET_ON, 134 .pwrsts = PWRSTS_OFF_RET_ON,
122 .pwrsts_logic_ret = PWRDM_POWER_RET, 135 .pwrsts_logic_ret = PWRDM_POWER_RET,
123 .banks = 1, 136 .banks = 1,
@@ -154,6 +167,19 @@ static struct powerdomain *powerdomains_omap[] __initdata = {
154 &mdm_pwrdm, 167 &mdm_pwrdm,
155#endif 168#endif
156 169
170#ifdef CONFIG_ARCH_OMAP34XX
171 &iva2_pwrdm,
172 &mpu_34xx_pwrdm,
173 &neon_pwrdm,
174 &core_34xx_pwrdm,
175 &cam_pwrdm,
176 &dss_pwrdm,
177 &per_pwrdm,
178 &emu_pwrdm,
179 &sgx_pwrdm,
180 &usbhost_pwrdm,
181#endif
182
157 NULL 183 NULL
158}; 184};
159 185
diff --git a/arch/arm/mach-omap2/powerdomains34xx.h b/arch/arm/mach-omap2/powerdomains34xx.h
new file mode 100644
index 000000000000..f573f7108398
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomains34xx.h
@@ -0,0 +1,327 @@
1/*
2 * OMAP34XX powerdomain definitions
3 *
4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2008 Nokia Corporation
6 *
7 * Written by Paul Walmsley
8 * Debugging and integration fixes by Jouni Högander
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#ifndef ARCH_ARM_MACH_OMAP2_POWERDOMAINS34XX
16#define ARCH_ARM_MACH_OMAP2_POWERDOMAINS34XX
17
18/*
19 * N.B. If powerdomains are added or removed from this file, update
20 * the array in mach-omap2/powerdomains.h.
21 */
22
23#include <mach/powerdomain.h>
24
25#include "prcm-common.h"
26#include "prm.h"
27#include "prm-regbits-34xx.h"
28#include "cm.h"
29#include "cm-regbits-34xx.h"
30
31/*
32 * 34XX-specific powerdomains, dependencies
33 */
34
35#ifdef CONFIG_ARCH_OMAP34XX
36
37/*
38 * 3430: PM_WKDEP_{PER,USBHOST}: CORE, IVA2, MPU, WKUP
39 * (USBHOST is ES2 only)
40 */
41static struct pwrdm_dep per_usbhost_wkdeps[] = {
42 {
43 .pwrdm_name = "core_pwrdm",
44 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
45 },
46 {
47 .pwrdm_name = "iva2_pwrdm",
48 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
49 },
50 {
51 .pwrdm_name = "mpu_pwrdm",
52 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
53 },
54 {
55 .pwrdm_name = "wkup_pwrdm",
56 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
57 },
58 { NULL },
59};
60
61/*
62 * 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER
63 */
64static struct pwrdm_dep mpu_34xx_wkdeps[] = {
65 {
66 .pwrdm_name = "core_pwrdm",
67 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
68 },
69 {
70 .pwrdm_name = "iva2_pwrdm",
71 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
72 },
73 {
74 .pwrdm_name = "dss_pwrdm",
75 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
76 },
77 {
78 .pwrdm_name = "per_pwrdm",
79 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
80 },
81 { NULL },
82};
83
84/*
85 * 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER
86 */
87static struct pwrdm_dep iva2_wkdeps[] = {
88 {
89 .pwrdm_name = "core_pwrdm",
90 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
91 },
92 {
93 .pwrdm_name = "mpu_pwrdm",
94 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
95 },
96 {
97 .pwrdm_name = "wkup_pwrdm",
98 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
99 },
100 {
101 .pwrdm_name = "dss_pwrdm",
102 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
103 },
104 {
105 .pwrdm_name = "per_pwrdm",
106 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
107 },
108 { NULL },
109};
110
111
112/* 3430 PM_WKDEP_{CAM,DSS}: IVA2, MPU, WKUP */
113static struct pwrdm_dep cam_dss_wkdeps[] = {
114 {
115 .pwrdm_name = "iva2_pwrdm",
116 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
117 },
118 {
119 .pwrdm_name = "mpu_pwrdm",
120 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
121 },
122 {
123 .pwrdm_name = "wkup_pwrdm",
124 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
125 },
126 { NULL },
127};
128
129/* 3430: PM_WKDEP_NEON: MPU */
130static struct pwrdm_dep neon_wkdeps[] = {
131 {
132 .pwrdm_name = "mpu_pwrdm",
133 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
134 },
135 { NULL },
136};
137
138
139/* Sleep dependency source arrays for 34xx-specific pwrdms - 34XX only */
140
141/*
142 * 3430: CM_SLEEPDEP_{DSS,PER}: MPU, IVA
143 * 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA
144 */
145static struct pwrdm_dep dss_per_usbhost_sleepdeps[] = {
146 {
147 .pwrdm_name = "mpu_pwrdm",
148 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
149 },
150 {
151 .pwrdm_name = "iva2_pwrdm",
152 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
153 },
154 { NULL },
155};
156
157
158/*
159 * Powerdomains
160 */
161
162static struct powerdomain iva2_pwrdm = {
163 .name = "iva2_pwrdm",
164 .prcm_offs = OMAP3430_IVA2_MOD,
165 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
166 .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT,
167 .wkdep_srcs = iva2_wkdeps,
168 .pwrsts = PWRSTS_OFF_RET_ON,
169 .pwrsts_logic_ret = PWRSTS_OFF_RET,
170 .banks = 4,
171 .pwrsts_mem_ret = {
172 [0] = PWRSTS_OFF_RET,
173 [1] = PWRSTS_OFF_RET,
174 [2] = PWRSTS_OFF_RET,
175 [3] = PWRSTS_OFF_RET,
176 },
177 .pwrsts_mem_on = {
178 [0] = PWRDM_POWER_ON,
179 [1] = PWRDM_POWER_ON,
180 [2] = PWRSTS_OFF_ON,
181 [3] = PWRDM_POWER_ON,
182 },
183};
184
185static struct powerdomain mpu_34xx_pwrdm = {
186 .name = "mpu_pwrdm",
187 .prcm_offs = MPU_MOD,
188 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
189 .dep_bit = OMAP3430_EN_MPU_SHIFT,
190 .wkdep_srcs = mpu_34xx_wkdeps,
191 .pwrsts = PWRSTS_OFF_RET_ON,
192 .pwrsts_logic_ret = PWRSTS_OFF_RET,
193 .banks = 1,
194 .pwrsts_mem_ret = {
195 [0] = PWRSTS_OFF_RET,
196 },
197 .pwrsts_mem_on = {
198 [0] = PWRSTS_OFF_ON,
199 },
200};
201
202/* No wkdeps or sleepdeps for 34xx core apparently */
203static struct powerdomain core_34xx_pwrdm = {
204 .name = "core_pwrdm",
205 .prcm_offs = CORE_MOD,
206 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
207 .pwrsts = PWRSTS_OFF_RET_ON,
208 .dep_bit = OMAP3430_EN_CORE_SHIFT,
209 .banks = 2,
210 .pwrsts_mem_ret = {
211 [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
212 [1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */
213 },
214 .pwrsts_mem_on = {
215 [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
216 [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
217 },
218};
219
220/* Another case of bit name collisions between several registers: EN_DSS */
221static struct powerdomain dss_pwrdm = {
222 .name = "dss_pwrdm",
223 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
224 .prcm_offs = OMAP3430_DSS_MOD,
225 .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT,
226 .wkdep_srcs = cam_dss_wkdeps,
227 .sleepdep_srcs = dss_per_usbhost_sleepdeps,
228 .pwrsts = PWRSTS_OFF_RET_ON,
229 .pwrsts_logic_ret = PWRDM_POWER_RET,
230 .banks = 1,
231 .pwrsts_mem_ret = {
232 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
233 },
234 .pwrsts_mem_on = {
235 [0] = PWRDM_POWER_ON, /* MEMONSTATE */
236 },
237};
238
239static struct powerdomain sgx_pwrdm = {
240 .name = "sgx_pwrdm",
241 .prcm_offs = OMAP3430ES2_SGX_MOD,
242 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
243 .wkdep_srcs = gfx_sgx_wkdeps,
244 .sleepdep_srcs = cam_gfx_sleepdeps,
245 /* XXX This is accurate for 3430 SGX, but what about GFX? */
246 .pwrsts = PWRSTS_OFF_RET_ON,
247 .pwrsts_logic_ret = PWRDM_POWER_RET,
248 .banks = 1,
249 .pwrsts_mem_ret = {
250 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
251 },
252 .pwrsts_mem_on = {
253 [0] = PWRDM_POWER_ON, /* MEMONSTATE */
254 },
255};
256
257static struct powerdomain cam_pwrdm = {
258 .name = "cam_pwrdm",
259 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
260 .prcm_offs = OMAP3430_CAM_MOD,
261 .wkdep_srcs = cam_dss_wkdeps,
262 .sleepdep_srcs = cam_gfx_sleepdeps,
263 .pwrsts = PWRSTS_OFF_RET_ON,
264 .pwrsts_logic_ret = PWRDM_POWER_RET,
265 .banks = 1,
266 .pwrsts_mem_ret = {
267 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
268 },
269 .pwrsts_mem_on = {
270 [0] = PWRDM_POWER_ON, /* MEMONSTATE */
271 },
272};
273
274static struct powerdomain per_pwrdm = {
275 .name = "per_pwrdm",
276 .prcm_offs = OMAP3430_PER_MOD,
277 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
278 .dep_bit = OMAP3430_EN_PER_SHIFT,
279 .wkdep_srcs = per_usbhost_wkdeps,
280 .sleepdep_srcs = dss_per_usbhost_sleepdeps,
281 .pwrsts = PWRSTS_OFF_RET_ON,
282 .pwrsts_logic_ret = PWRSTS_OFF_RET,
283 .banks = 1,
284 .pwrsts_mem_ret = {
285 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
286 },
287 .pwrsts_mem_on = {
288 [0] = PWRDM_POWER_ON, /* MEMONSTATE */
289 },
290};
291
292static struct powerdomain emu_pwrdm = {
293 .name = "emu_pwrdm",
294 .prcm_offs = OMAP3430_EMU_MOD,
295 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
296};
297
298static struct powerdomain neon_pwrdm = {
299 .name = "neon_pwrdm",
300 .prcm_offs = OMAP3430_NEON_MOD,
301 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
302 .wkdep_srcs = neon_wkdeps,
303 .pwrsts = PWRSTS_OFF_RET_ON,
304 .pwrsts_logic_ret = PWRDM_POWER_RET,
305};
306
307static struct powerdomain usbhost_pwrdm = {
308 .name = "usbhost_pwrdm",
309 .prcm_offs = OMAP3430ES2_USBHOST_MOD,
310 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
311 .wkdep_srcs = per_usbhost_wkdeps,
312 .sleepdep_srcs = dss_per_usbhost_sleepdeps,
313 .pwrsts = PWRSTS_OFF_RET_ON,
314 .pwrsts_logic_ret = PWRDM_POWER_RET,
315 .banks = 1,
316 .pwrsts_mem_ret = {
317 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
318 },
319 .pwrsts_mem_on = {
320 [0] = PWRDM_POWER_ON, /* MEMONSTATE */
321 },
322};
323
324#endif /* CONFIG_ARCH_OMAP34XX */
325
326
327#endif
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index 54c32f482131..4a32822ff3fc 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -312,7 +312,8 @@
312#define OMAP3430_ST_GPT2 (1 << 3) 312#define OMAP3430_ST_GPT2 (1 << 3)
313 313
314/* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */ 314/* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */
315#define OMAP3430_EN_CORE (1 << 0) 315#define OMAP3430_EN_CORE_SHIFT 0
316#define OMAP3430_EN_CORE_MASK (1 << 0)
316 317
317#endif 318#endif
318 319
diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h
index b4686bc345ca..5b5ecfe6c999 100644
--- a/arch/arm/mach-omap2/prm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-34xx.h
@@ -68,7 +68,8 @@
68#define OMAP3430_VPINIDLE (1 << 0) 68#define OMAP3430_VPINIDLE (1 << 0)
69 69
70/* PM_WKDEP_IVA2, PM_WKDEP_MPU shared bits */ 70/* PM_WKDEP_IVA2, PM_WKDEP_MPU shared bits */
71#define OMAP3430_EN_PER (1 << 7) 71#define OMAP3430_EN_PER_SHIFT 7
72#define OMAP3430_EN_PER_MASK (1 << 7)
72 73
73/* PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE shared bits */ 74/* PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE shared bits */
74#define OMAP3430_MEMORYCHANGE (1 << 3) 75#define OMAP3430_MEMORYCHANGE (1 << 3)
@@ -77,7 +78,7 @@
77#define OMAP3430_LOGICSTATEST (1 << 2) 78#define OMAP3430_LOGICSTATEST (1 << 2)
78 79
79/* PM_PREPWSTST_IVA2, PM_PREPWSTST_CORE shared bits */ 80/* PM_PREPWSTST_IVA2, PM_PREPWSTST_CORE shared bits */
80#define OMAP3430_LASTLOGICSTATEENTERED (1 << 2) 81#define OMAP3430_LASTLOGICSTATEENTERED (1 << 2)
81 82
82/* 83/*
83 * PM_PREPWSTST_IVA2, PM_PREPWSTST_MPU, PM_PREPWSTST_CORE, 84 * PM_PREPWSTST_IVA2, PM_PREPWSTST_MPU, PM_PREPWSTST_CORE,
@@ -278,8 +279,10 @@
278#define OMAP3430_EMULATION_MPU_RST (1 << 11) 279#define OMAP3430_EMULATION_MPU_RST (1 << 11)
279 280
280/* PM_WKDEP_MPU specific bits */ 281/* PM_WKDEP_MPU specific bits */
281#define OMAP3430_PM_WKDEP_MPU_EN_DSS (1 << 5) 282#define OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT 5
282#define OMAP3430_PM_WKDEP_MPU_EN_IVA2 (1 << 2) 283#define OMAP3430_PM_WKDEP_MPU_EN_DSS_MASK (1 << 5)
284#define OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT 2
285#define OMAP3430_PM_WKDEP_MPU_EN_IVA2_MASK (1 << 2)
283 286
284/* PM_EVGENCTRL_MPU */ 287/* PM_EVGENCTRL_MPU */
285#define OMAP3430_OFFLOADMODE_SHIFT 3 288#define OMAP3430_OFFLOADMODE_SHIFT 3
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-18 10:12:33 -0500