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authorRob Herring <rob.herring@calxeda.com>2012-03-31 00:37:53 -0400
committerRob Herring <rob.herring@calxeda.com>2012-04-06 09:26:18 -0400
commitc65f2abf54a6d07260f1fa64773154e1d7047961 (patch)
tree5ebc35115ba1f4d46727cc6db0b4f70ec3f9b437 /arch
parentdd775ae2549217d3ae09363e3edb305d0fa19928 (diff)
ARM: remove ixp23xx and ixp2000 platforms
ixp2xxx platforms have had no real changes since ~2006 and the maintainer has said on irc that they can be removed: 13:05 < nico> do you still care about ixp2000? 13:22 < lennert> not really, no 13:58 < nico> do you think we could remove it from the kernel tree? 14:01 < lennert> go for it, and remove ixp23xx too while you're at it Removing will help simplify ARM consolidation in general and PCI re-work specifically. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Cc: Randy Dunlap <rdunlap@xenotime.net> Acked-by: Lennert Buytenhek <buytenh@wantstofly.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/Kconfig26
-rw-r--r--arch/arm/Makefile2
-rw-r--r--arch/arm/boot/compressed/head-xscale.S7
-rw-r--r--arch/arm/common/Makefile2
-rw-r--r--arch/arm/common/uengine.c507
-rw-r--r--arch/arm/configs/ixp2000_defconfig99
-rw-r--r--arch/arm/configs/ixp23xx_defconfig105
-rw-r--r--arch/arm/include/asm/hardware/uengine.h62
-rw-r--r--arch/arm/mach-ixp2000/Kconfig72
-rw-r--r--arch/arm/mach-ixp2000/Makefile14
-rw-r--r--arch/arm/mach-ixp2000/Makefile.boot3
-rw-r--r--arch/arm/mach-ixp2000/core.c520
-rw-r--r--arch/arm/mach-ixp2000/enp2611.c265
-rw-r--r--arch/arm/mach-ixp2000/include/mach/debug-macro.S25
-rw-r--r--arch/arm/mach-ixp2000/include/mach/enp2611.h46
-rw-r--r--arch/arm/mach-ixp2000/include/mach/entry-macro.S54
-rw-r--r--arch/arm/mach-ixp2000/include/mach/gpio-ixp2000.h48
-rw-r--r--arch/arm/mach-ixp2000/include/mach/hardware.h36
-rw-r--r--arch/arm/mach-ixp2000/include/mach/io.h133
-rw-r--r--arch/arm/mach-ixp2000/include/mach/irqs.h207
-rw-r--r--arch/arm/mach-ixp2000/include/mach/ixdp2x00.h92
-rw-r--r--arch/arm/mach-ixp2000/include/mach/ixdp2x01.h57
-rw-r--r--arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h451
-rw-r--r--arch/arm/mach-ixp2000/include/mach/memory.h31
-rw-r--r--arch/arm/mach-ixp2000/include/mach/platform.h153
-rw-r--r--arch/arm/mach-ixp2000/include/mach/timex.h13
-rw-r--r--arch/arm/mach-ixp2000/include/mach/uncompress.h47
-rw-r--r--arch/arm/mach-ixp2000/ixdp2400.c180
-rw-r--r--arch/arm/mach-ixp2000/ixdp2800.c295
-rw-r--r--arch/arm/mach-ixp2000/ixdp2x00.c306
-rw-r--r--arch/arm/mach-ixp2000/ixdp2x01.c483
-rw-r--r--arch/arm/mach-ixp2000/pci.c252
-rw-r--r--arch/arm/mach-ixp23xx/Kconfig25
-rw-r--r--arch/arm/mach-ixp23xx/Makefile11
-rw-r--r--arch/arm/mach-ixp23xx/Makefile.boot2
-rw-r--r--arch/arm/mach-ixp23xx/core.c455
-rw-r--r--arch/arm/mach-ixp23xx/espresso.c93
-rw-r--r--arch/arm/mach-ixp23xx/include/mach/debug-macro.S25
-rw-r--r--arch/arm/mach-ixp23xx/include/mach/entry-macro.S31
-rw-r--r--arch/arm/mach-ixp23xx/include/mach/hardware.h32
-rw-r--r--arch/arm/mach-ixp23xx/include/mach/io.h22
-rw-r--r--arch/arm/mach-ixp23xx/include/mach/irqs.h223
-rw-r--r--arch/arm/mach-ixp23xx/include/mach/ixdp2351.h89
-rw-r--r--arch/arm/mach-ixp23xx/include/mach/ixp23xx.h298
-rw-r--r--arch/arm/mach-ixp23xx/include/mach/memory.h34
-rw-r--r--arch/arm/mach-ixp23xx/include/mach/platform.h58
-rw-r--r--arch/arm/mach-ixp23xx/include/mach/time.h3
-rw-r--r--arch/arm/mach-ixp23xx/include/mach/timex.h7
-rw-r--r--arch/arm/mach-ixp23xx/include/mach/uncompress.h40
-rw-r--r--arch/arm/mach-ixp23xx/ixdp2351.c347
-rw-r--r--arch/arm/mach-ixp23xx/pci.c294
-rw-r--r--arch/arm/mach-ixp23xx/roadrunner.c180
52 files changed, 0 insertions, 6862 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 93180845ae16..6b242f431e32 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -527,28 +527,6 @@ config ARCH_IOP33X
527 help 527 help
528 Support for Intel's IOP33X (XScale) family of processors. 528 Support for Intel's IOP33X (XScale) family of processors.
529 529
530config ARCH_IXP23XX
531 bool "IXP23XX-based"
532 depends on MMU
533 select CPU_XSC3
534 select PCI
535 select ARCH_USES_GETTIMEOFFSET
536 select NEED_MACH_IO_H
537 select NEED_MACH_MEMORY_H
538 help
539 Support for Intel's IXP23xx (XScale) family of processors.
540
541config ARCH_IXP2000
542 bool "IXP2400/2800-based"
543 depends on MMU
544 select CPU_XSCALE
545 select PCI
546 select ARCH_USES_GETTIMEOFFSET
547 select NEED_MACH_IO_H
548 select NEED_MACH_MEMORY_H
549 help
550 Support for Intel's IXP2400/2800 (XScale) family of processors.
551
552config ARCH_IXP4XX 530config ARCH_IXP4XX
553 bool "IXP4xx-based" 531 bool "IXP4xx-based"
554 depends on MMU 532 depends on MMU
@@ -1045,10 +1023,6 @@ source "arch/arm/mach-iop13xx/Kconfig"
1045 1023
1046source "arch/arm/mach-ixp4xx/Kconfig" 1024source "arch/arm/mach-ixp4xx/Kconfig"
1047 1025
1048source "arch/arm/mach-ixp2000/Kconfig"
1049
1050source "arch/arm/mach-ixp23xx/Kconfig"
1051
1052source "arch/arm/mach-kirkwood/Kconfig" 1026source "arch/arm/mach-kirkwood/Kconfig"
1053 1027
1054source "arch/arm/mach-ks8695/Kconfig" 1028source "arch/arm/mach-ks8695/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 047a20780fc1..a0c40a0986cd 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -149,8 +149,6 @@ machine-$(CONFIG_ARCH_INTEGRATOR) := integrator
149machine-$(CONFIG_ARCH_IOP13XX) := iop13xx 149machine-$(CONFIG_ARCH_IOP13XX) := iop13xx
150machine-$(CONFIG_ARCH_IOP32X) := iop32x 150machine-$(CONFIG_ARCH_IOP32X) := iop32x
151machine-$(CONFIG_ARCH_IOP33X) := iop33x 151machine-$(CONFIG_ARCH_IOP33X) := iop33x
152machine-$(CONFIG_ARCH_IXP2000) := ixp2000
153machine-$(CONFIG_ARCH_IXP23XX) := ixp23xx
154machine-$(CONFIG_ARCH_IXP4XX) := ixp4xx 152machine-$(CONFIG_ARCH_IXP4XX) := ixp4xx
155machine-$(CONFIG_ARCH_KIRKWOOD) := kirkwood 153machine-$(CONFIG_ARCH_KIRKWOOD) := kirkwood
156machine-$(CONFIG_ARCH_KS8695) := ks8695 154machine-$(CONFIG_ARCH_KS8695) := ks8695
diff --git a/arch/arm/boot/compressed/head-xscale.S b/arch/arm/boot/compressed/head-xscale.S
index aa5ee49c5c5a..6ab0599c02dd 100644
--- a/arch/arm/boot/compressed/head-xscale.S
+++ b/arch/arm/boot/compressed/head-xscale.S
@@ -32,10 +32,3 @@ __XScale_start:
32 bic r0, r0, #0x1000 @ clear Icache 32 bic r0, r0, #0x1000 @ clear Icache
33 mcr p15, 0, r0, c1, c0, 0 33 mcr p15, 0, r0, c1, c0, 0
34 34
35#ifdef CONFIG_ARCH_IXP2000
36 mov r1, #-1
37 mov r0, #0xd6000000
38 str r1, [r0, #0x14]
39 str r1, [r0, #0x18]
40#endif
41
diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
index 215816f1775f..e8a4e58f1b82 100644
--- a/arch/arm/common/Makefile
+++ b/arch/arm/common/Makefile
@@ -11,7 +11,5 @@ obj-$(CONFIG_DMABOUNCE) += dmabounce.o
11obj-$(CONFIG_SHARP_LOCOMO) += locomo.o 11obj-$(CONFIG_SHARP_LOCOMO) += locomo.o
12obj-$(CONFIG_SHARP_PARAM) += sharpsl_param.o 12obj-$(CONFIG_SHARP_PARAM) += sharpsl_param.o
13obj-$(CONFIG_SHARP_SCOOP) += scoop.o 13obj-$(CONFIG_SHARP_SCOOP) += scoop.o
14obj-$(CONFIG_ARCH_IXP2000) += uengine.o
15obj-$(CONFIG_ARCH_IXP23XX) += uengine.o
16obj-$(CONFIG_PCI_HOST_ITE8152) += it8152.o 14obj-$(CONFIG_PCI_HOST_ITE8152) += it8152.o
17obj-$(CONFIG_ARM_TIMER_SP804) += timer-sp.o 15obj-$(CONFIG_ARM_TIMER_SP804) += timer-sp.o
diff --git a/arch/arm/common/uengine.c b/arch/arm/common/uengine.c
deleted file mode 100644
index bef408f3d76c..000000000000
--- a/arch/arm/common/uengine.c
+++ /dev/null
@@ -1,507 +0,0 @@
1/*
2 * Generic library functions for the microengines found on the Intel
3 * IXP2000 series of network processors.
4 *
5 * Copyright (C) 2004, 2005 Lennert Buytenhek <buytenh@wantstofly.org>
6 * Dedicated to Marija Kulikova.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU Lesser General Public License as
10 * published by the Free Software Foundation; either version 2.1 of the
11 * License, or (at your option) any later version.
12 */
13
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/slab.h>
17#include <linux/module.h>
18#include <linux/string.h>
19#include <linux/io.h>
20#include <mach/hardware.h>
21#include <asm/hardware/uengine.h>
22
23#if defined(CONFIG_ARCH_IXP2000)
24#define IXP_UENGINE_CSR_VIRT_BASE IXP2000_UENGINE_CSR_VIRT_BASE
25#define IXP_PRODUCT_ID IXP2000_PRODUCT_ID
26#define IXP_MISC_CONTROL IXP2000_MISC_CONTROL
27#define IXP_RESET1 IXP2000_RESET1
28#else
29#if defined(CONFIG_ARCH_IXP23XX)
30#define IXP_UENGINE_CSR_VIRT_BASE IXP23XX_UENGINE_CSR_VIRT_BASE
31#define IXP_PRODUCT_ID IXP23XX_PRODUCT_ID
32#define IXP_MISC_CONTROL IXP23XX_MISC_CONTROL
33#define IXP_RESET1 IXP23XX_RESET1
34#else
35#error unknown platform
36#endif
37#endif
38
39#define USTORE_ADDRESS 0x000
40#define USTORE_DATA_LOWER 0x004
41#define USTORE_DATA_UPPER 0x008
42#define CTX_ENABLES 0x018
43#define CC_ENABLE 0x01c
44#define CSR_CTX_POINTER 0x020
45#define INDIRECT_CTX_STS 0x040
46#define ACTIVE_CTX_STS 0x044
47#define INDIRECT_CTX_SIG_EVENTS 0x048
48#define INDIRECT_CTX_WAKEUP_EVENTS 0x050
49#define NN_PUT 0x080
50#define NN_GET 0x084
51#define TIMESTAMP_LOW 0x0c0
52#define TIMESTAMP_HIGH 0x0c4
53#define T_INDEX_BYTE_INDEX 0x0f4
54#define LOCAL_CSR_STATUS 0x180
55
56u32 ixp2000_uengine_mask;
57
58static void *ixp2000_uengine_csr_area(int uengine)
59{
60 return ((void *)IXP_UENGINE_CSR_VIRT_BASE) + (uengine << 10);
61}
62
63/*
64 * LOCAL_CSR_STATUS=1 after a read or write to a microengine's CSR
65 * space means that the microengine we tried to access was also trying
66 * to access its own CSR space on the same clock cycle as we did. When
67 * this happens, we lose the arbitration process by default, and the
68 * read or write we tried to do was not actually performed, so we try
69 * again until it succeeds.
70 */
71u32 ixp2000_uengine_csr_read(int uengine, int offset)
72{
73 void *uebase;
74 u32 *local_csr_status;
75 u32 *reg;
76 u32 value;
77
78 uebase = ixp2000_uengine_csr_area(uengine);
79
80 local_csr_status = (u32 *)(uebase + LOCAL_CSR_STATUS);
81 reg = (u32 *)(uebase + offset);
82 do {
83 value = ixp2000_reg_read(reg);
84 } while (ixp2000_reg_read(local_csr_status) & 1);
85
86 return value;
87}
88EXPORT_SYMBOL(ixp2000_uengine_csr_read);
89
90void ixp2000_uengine_csr_write(int uengine, int offset, u32 value)
91{
92 void *uebase;
93 u32 *local_csr_status;
94 u32 *reg;
95
96 uebase = ixp2000_uengine_csr_area(uengine);
97
98 local_csr_status = (u32 *)(uebase + LOCAL_CSR_STATUS);
99 reg = (u32 *)(uebase + offset);
100 do {
101 ixp2000_reg_write(reg, value);
102 } while (ixp2000_reg_read(local_csr_status) & 1);
103}
104EXPORT_SYMBOL(ixp2000_uengine_csr_write);
105
106void ixp2000_uengine_reset(u32 uengine_mask)
107{
108 u32 value;
109
110 value = ixp2000_reg_read(IXP_RESET1) & ~ixp2000_uengine_mask;
111
112 uengine_mask &= ixp2000_uengine_mask;
113 ixp2000_reg_wrb(IXP_RESET1, value | uengine_mask);
114 ixp2000_reg_wrb(IXP_RESET1, value);
115}
116EXPORT_SYMBOL(ixp2000_uengine_reset);
117
118void ixp2000_uengine_set_mode(int uengine, u32 mode)
119{
120 /*
121 * CTL_STR_PAR_EN: unconditionally enable parity checking on
122 * control store.
123 */
124 mode |= 0x10000000;
125 ixp2000_uengine_csr_write(uengine, CTX_ENABLES, mode);
126
127 /*
128 * Enable updating of condition codes.
129 */
130 ixp2000_uengine_csr_write(uengine, CC_ENABLE, 0x00002000);
131
132 /*
133 * Initialise other per-microengine registers.
134 */
135 ixp2000_uengine_csr_write(uengine, NN_PUT, 0x00);
136 ixp2000_uengine_csr_write(uengine, NN_GET, 0x00);
137 ixp2000_uengine_csr_write(uengine, T_INDEX_BYTE_INDEX, 0);
138}
139EXPORT_SYMBOL(ixp2000_uengine_set_mode);
140
141static int make_even_parity(u32 x)
142{
143 return hweight32(x) & 1;
144}
145
146static void ustore_write(int uengine, u64 insn)
147{
148 /*
149 * Generate even parity for top and bottom 20 bits.
150 */
151 insn |= (u64)make_even_parity((insn >> 20) & 0x000fffff) << 41;
152 insn |= (u64)make_even_parity(insn & 0x000fffff) << 40;
153
154 /*
155 * Write to microstore. The second write auto-increments
156 * the USTORE_ADDRESS index register.
157 */
158 ixp2000_uengine_csr_write(uengine, USTORE_DATA_LOWER, (u32)insn);
159 ixp2000_uengine_csr_write(uengine, USTORE_DATA_UPPER, (u32)(insn >> 32));
160}
161
162void ixp2000_uengine_load_microcode(int uengine, u8 *ucode, int insns)
163{
164 int i;
165
166 /*
167 * Start writing to microstore at address 0.
168 */
169 ixp2000_uengine_csr_write(uengine, USTORE_ADDRESS, 0x80000000);
170 for (i = 0; i < insns; i++) {
171 u64 insn;
172
173 insn = (((u64)ucode[0]) << 32) |
174 (((u64)ucode[1]) << 24) |
175 (((u64)ucode[2]) << 16) |
176 (((u64)ucode[3]) << 8) |
177 ((u64)ucode[4]);
178 ucode += 5;
179
180 ustore_write(uengine, insn);
181 }
182
183 /*
184 * Pad with a few NOPs at the end (to avoid the microengine
185 * aborting as it prefetches beyond the last instruction), unless
186 * we run off the end of the instruction store first, at which
187 * point the address register will wrap back to zero.
188 */
189 for (i = 0; i < 4; i++) {
190 u32 addr;
191
192 addr = ixp2000_uengine_csr_read(uengine, USTORE_ADDRESS);
193 if (addr == 0x80000000)
194 break;
195 ustore_write(uengine, 0xf0000c0300ULL);
196 }
197
198 /*
199 * End programming.
200 */
201 ixp2000_uengine_csr_write(uengine, USTORE_ADDRESS, 0x00000000);
202}
203EXPORT_SYMBOL(ixp2000_uengine_load_microcode);
204
205void ixp2000_uengine_init_context(int uengine, int context, int pc)
206{
207 /*
208 * Select the right context for indirect access.
209 */
210 ixp2000_uengine_csr_write(uengine, CSR_CTX_POINTER, context);
211
212 /*
213 * Initialise signal masks to immediately go to Ready state.
214 */
215 ixp2000_uengine_csr_write(uengine, INDIRECT_CTX_SIG_EVENTS, 1);
216 ixp2000_uengine_csr_write(uengine, INDIRECT_CTX_WAKEUP_EVENTS, 1);
217
218 /*
219 * Set program counter.
220 */
221 ixp2000_uengine_csr_write(uengine, INDIRECT_CTX_STS, pc);
222}
223EXPORT_SYMBOL(ixp2000_uengine_init_context);
224
225void ixp2000_uengine_start_contexts(int uengine, u8 ctx_mask)
226{
227 u32 mask;
228
229 /*
230 * Enable the specified context to go to Executing state.
231 */
232 mask = ixp2000_uengine_csr_read(uengine, CTX_ENABLES);
233 mask |= ctx_mask << 8;
234 ixp2000_uengine_csr_write(uengine, CTX_ENABLES, mask);
235}
236EXPORT_SYMBOL(ixp2000_uengine_start_contexts);
237
238void ixp2000_uengine_stop_contexts(int uengine, u8 ctx_mask)
239{
240 u32 mask;
241
242 /*
243 * Disable the Ready->Executing transition. Note that this
244 * does not stop the context until it voluntarily yields.
245 */
246 mask = ixp2000_uengine_csr_read(uengine, CTX_ENABLES);
247 mask &= ~(ctx_mask << 8);
248 ixp2000_uengine_csr_write(uengine, CTX_ENABLES, mask);
249}
250EXPORT_SYMBOL(ixp2000_uengine_stop_contexts);
251
252static int check_ixp_type(struct ixp2000_uengine_code *c)
253{
254 u32 product_id;
255 u32 rev;
256
257 product_id = ixp2000_reg_read(IXP_PRODUCT_ID);
258 if (((product_id >> 16) & 0x1f) != 0)
259 return 0;
260
261 switch ((product_id >> 8) & 0xff) {
262#ifdef CONFIG_ARCH_IXP2000
263 case 0: /* IXP2800 */
264 if (!(c->cpu_model_bitmask & 4))
265 return 0;
266 break;
267
268 case 1: /* IXP2850 */
269 if (!(c->cpu_model_bitmask & 8))
270 return 0;
271 break;
272
273 case 2: /* IXP2400 */
274 if (!(c->cpu_model_bitmask & 2))
275 return 0;
276 break;
277#endif
278
279#ifdef CONFIG_ARCH_IXP23XX
280 case 4: /* IXP23xx */
281 if (!(c->cpu_model_bitmask & 0x3f0))
282 return 0;
283 break;
284#endif
285
286 default:
287 return 0;
288 }
289
290 rev = product_id & 0xff;
291 if (rev < c->cpu_min_revision || rev > c->cpu_max_revision)
292 return 0;
293
294 return 1;
295}
296
297static void generate_ucode(u8 *ucode, u32 *gpr_a, u32 *gpr_b)
298{
299 int offset;
300 int i;
301
302 offset = 0;
303
304 for (i = 0; i < 128; i++) {
305 u8 b3;
306 u8 b2;
307 u8 b1;
308 u8 b0;
309
310 b3 = (gpr_a[i] >> 24) & 0xff;
311 b2 = (gpr_a[i] >> 16) & 0xff;
312 b1 = (gpr_a[i] >> 8) & 0xff;
313 b0 = gpr_a[i] & 0xff;
314
315 /* immed[@ai, (b1 << 8) | b0] */
316 /* 11110000 0000VVVV VVVV11VV VVVVVV00 1IIIIIII */
317 ucode[offset++] = 0xf0;
318 ucode[offset++] = (b1 >> 4);
319 ucode[offset++] = (b1 << 4) | 0x0c | (b0 >> 6);
320 ucode[offset++] = (b0 << 2);
321 ucode[offset++] = 0x80 | i;
322
323 /* immed_w1[@ai, (b3 << 8) | b2] */
324 /* 11110100 0100VVVV VVVV11VV VVVVVV00 1IIIIIII */
325 ucode[offset++] = 0xf4;
326 ucode[offset++] = 0x40 | (b3 >> 4);
327 ucode[offset++] = (b3 << 4) | 0x0c | (b2 >> 6);
328 ucode[offset++] = (b2 << 2);
329 ucode[offset++] = 0x80 | i;
330 }
331
332 for (i = 0; i < 128; i++) {
333 u8 b3;
334 u8 b2;
335 u8 b1;
336 u8 b0;
337
338 b3 = (gpr_b[i] >> 24) & 0xff;
339 b2 = (gpr_b[i] >> 16) & 0xff;
340 b1 = (gpr_b[i] >> 8) & 0xff;
341 b0 = gpr_b[i] & 0xff;
342
343 /* immed[@bi, (b1 << 8) | b0] */
344 /* 11110000 0000VVVV VVVV001I IIIIII11 VVVVVVVV */
345 ucode[offset++] = 0xf0;
346 ucode[offset++] = (b1 >> 4);
347 ucode[offset++] = (b1 << 4) | 0x02 | (i >> 6);
348 ucode[offset++] = (i << 2) | 0x03;
349 ucode[offset++] = b0;
350
351 /* immed_w1[@bi, (b3 << 8) | b2] */
352 /* 11110100 0100VVVV VVVV001I IIIIII11 VVVVVVVV */
353 ucode[offset++] = 0xf4;
354 ucode[offset++] = 0x40 | (b3 >> 4);
355 ucode[offset++] = (b3 << 4) | 0x02 | (i >> 6);
356 ucode[offset++] = (i << 2) | 0x03;
357 ucode[offset++] = b2;
358 }
359
360 /* ctx_arb[kill] */
361 ucode[offset++] = 0xe0;
362 ucode[offset++] = 0x00;
363 ucode[offset++] = 0x01;
364 ucode[offset++] = 0x00;
365 ucode[offset++] = 0x00;
366}
367
368static int set_initial_registers(int uengine, struct ixp2000_uengine_code *c)
369{
370 int per_ctx_regs;
371 u32 *gpr_a;
372 u32 *gpr_b;
373 u8 *ucode;
374 int i;
375
376 gpr_a = kzalloc(128 * sizeof(u32), GFP_KERNEL);
377 gpr_b = kzalloc(128 * sizeof(u32), GFP_KERNEL);
378 ucode = kmalloc(513 * 5, GFP_KERNEL);
379 if (gpr_a == NULL || gpr_b == NULL || ucode == NULL) {
380 kfree(ucode);
381 kfree(gpr_b);
382 kfree(gpr_a);
383 return 1;
384 }
385
386 per_ctx_regs = 16;
387 if (c->uengine_parameters & IXP2000_UENGINE_4_CONTEXTS)
388 per_ctx_regs = 32;
389
390 for (i = 0; i < 256; i++) {
391 struct ixp2000_reg_value *r = c->initial_reg_values + i;
392 u32 *bank;
393 int inc;
394 int j;
395
396 if (r->reg == -1)
397 break;
398
399 bank = (r->reg & 0x400) ? gpr_b : gpr_a;
400 inc = (r->reg & 0x80) ? 128 : per_ctx_regs;
401
402 j = r->reg & 0x7f;
403 while (j < 128) {
404 bank[j] = r->value;
405 j += inc;
406 }
407 }
408
409 generate_ucode(ucode, gpr_a, gpr_b);
410 ixp2000_uengine_load_microcode(uengine, ucode, 513);
411 ixp2000_uengine_init_context(uengine, 0, 0);
412 ixp2000_uengine_start_contexts(uengine, 0x01);
413 for (i = 0; i < 100; i++) {
414 u32 status;
415
416 status = ixp2000_uengine_csr_read(uengine, ACTIVE_CTX_STS);
417 if (!(status & 0x80000000))
418 break;
419 }
420 ixp2000_uengine_stop_contexts(uengine, 0x01);
421
422 kfree(ucode);
423 kfree(gpr_b);
424 kfree(gpr_a);
425
426 return !!(i == 100);
427}
428
429int ixp2000_uengine_load(int uengine, struct ixp2000_uengine_code *c)
430{
431 int ctx;
432
433 if (!check_ixp_type(c))
434 return 1;
435
436 if (!(ixp2000_uengine_mask & (1 << uengine)))
437 return 1;
438
439 ixp2000_uengine_reset(1 << uengine);
440 ixp2000_uengine_set_mode(uengine, c->uengine_parameters);
441 if (set_initial_registers(uengine, c))
442 return 1;
443 ixp2000_uengine_load_microcode(uengine, c->insns, c->num_insns);
444
445 for (ctx = 0; ctx < 8; ctx++)
446 ixp2000_uengine_init_context(uengine, ctx, 0);
447
448 return 0;
449}
450EXPORT_SYMBOL(ixp2000_uengine_load);
451
452
453static int __init ixp2000_uengine_init(void)
454{
455 int uengine;
456 u32 value;
457
458 /*
459 * Determine number of microengines present.
460 */
461 switch ((ixp2000_reg_read(IXP_PRODUCT_ID) >> 8) & 0x1fff) {
462#ifdef CONFIG_ARCH_IXP2000
463 case 0: /* IXP2800 */
464 case 1: /* IXP2850 */
465 ixp2000_uengine_mask = 0x00ff00ff;
466 break;
467
468 case 2: /* IXP2400 */
469 ixp2000_uengine_mask = 0x000f000f;
470 break;
471#endif
472
473#ifdef CONFIG_ARCH_IXP23XX
474 case 4: /* IXP23xx */
475 ixp2000_uengine_mask = (*IXP23XX_EXP_CFG_FUSE >> 8) & 0xf;
476 break;
477#endif
478
479 default:
480 printk(KERN_INFO "Detected unknown IXP2000 model (%.8x)\n",
481 (unsigned int)ixp2000_reg_read(IXP_PRODUCT_ID));
482 ixp2000_uengine_mask = 0x00000000;
483 break;
484 }
485
486 /*
487 * Reset microengines.
488 */
489 ixp2000_uengine_reset(ixp2000_uengine_mask);
490
491 /*
492 * Synchronise timestamp counters across all microengines.
493 */
494 value = ixp2000_reg_read(IXP_MISC_CONTROL);
495 ixp2000_reg_wrb(IXP_MISC_CONTROL, value & ~0x80);
496 for (uengine = 0; uengine < 32; uengine++) {
497 if (ixp2000_uengine_mask & (1 << uengine)) {
498 ixp2000_uengine_csr_write(uengine, TIMESTAMP_LOW, 0);
499 ixp2000_uengine_csr_write(uengine, TIMESTAMP_HIGH, 0);
500 }
501 }
502 ixp2000_reg_wrb(IXP_MISC_CONTROL, value | 0x80);
503
504 return 0;
505}
506
507subsys_initcall(ixp2000_uengine_init);
diff --git a/arch/arm/configs/ixp2000_defconfig b/arch/arm/configs/ixp2000_defconfig
deleted file mode 100644
index 8405aded97a3..000000000000
--- a/arch/arm/configs/ixp2000_defconfig
+++ /dev/null
@@ -1,99 +0,0 @@
1CONFIG_EXPERIMENTAL=y
2CONFIG_SYSVIPC=y
3CONFIG_BSD_PROCESS_ACCT=y
4CONFIG_LOG_BUF_SHIFT=14
5CONFIG_BLK_DEV_INITRD=y
6CONFIG_EXPERT=y
7# CONFIG_HOTPLUG is not set
8CONFIG_SLAB=y
9CONFIG_MODULES=y
10CONFIG_MODULE_UNLOAD=y
11CONFIG_ARCH_IXP2000=y
12CONFIG_ARCH_ENP2611=y
13CONFIG_ARCH_IXDP2400=y
14CONFIG_ARCH_IXDP2800=y
15CONFIG_ARCH_IXDP2401=y
16CONFIG_ARCH_IXDP2801=y
17# CONFIG_IXP2000_SUPPORT_BROKEN_PCI_IO is not set
18# CONFIG_ARM_THUMB is not set
19CONFIG_CPU_BIG_ENDIAN=y
20CONFIG_ZBOOT_ROM_TEXT=0x0
21CONFIG_ZBOOT_ROM_BSS=0x0
22CONFIG_CMDLINE="console=ttyS0,57600 root=/dev/nfs ip=bootp mem=64M@0x0"
23CONFIG_FPE_NWFPE=y
24CONFIG_FPE_NWFPE_XP=y
25CONFIG_NET=y
26CONFIG_PACKET=y
27CONFIG_UNIX=y
28CONFIG_INET=y
29CONFIG_IP_PNP=y
30CONFIG_IP_PNP_DHCP=y
31CONFIG_IP_PNP_BOOTP=y
32CONFIG_SYN_COOKIES=y
33CONFIG_IPV6=y
34# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
35# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
36# CONFIG_INET6_XFRM_MODE_BEET is not set
37# CONFIG_IPV6_SIT is not set
38# CONFIG_PREVENT_FIRMWARE_BUILD is not set
39CONFIG_MTD=y
40CONFIG_MTD_PARTITIONS=y
41CONFIG_MTD_REDBOOT_PARTS=y
42CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
43CONFIG_MTD_REDBOOT_PARTS_READONLY=y
44CONFIG_MTD_CHAR=y
45CONFIG_MTD_BLOCK=y
46CONFIG_MTD_CFI=y
47CONFIG_MTD_CFI_INTELEXT=y
48CONFIG_MTD_COMPLEX_MAPPINGS=y
49CONFIG_MTD_IXP2000=y
50CONFIG_BLK_DEV_LOOP=y
51CONFIG_BLK_DEV_NBD=y
52CONFIG_BLK_DEV_RAM=y
53CONFIG_BLK_DEV_RAM_SIZE=8192
54CONFIG_EEPROM_LEGACY=y
55CONFIG_NETDEVICES=y
56CONFIG_DUMMY=y
57CONFIG_NET_ETHERNET=y
58CONFIG_NET_PCI=y
59CONFIG_CS89x0=y
60CONFIG_E100=y
61CONFIG_ENP2611_MSF_NET=y
62CONFIG_WAN=y
63CONFIG_HDLC=y
64CONFIG_HDLC_RAW=y
65CONFIG_HDLC_CISCO=y
66CONFIG_HDLC_FR=y
67CONFIG_HDLC_PPP=y
68CONFIG_DLCI=y
69# CONFIG_INPUT_KEYBOARD is not set
70# CONFIG_INPUT_MOUSE is not set
71# CONFIG_SERIO is not set
72# CONFIG_VT is not set
73CONFIG_SERIAL_8250=y
74CONFIG_SERIAL_8250_CONSOLE=y
75CONFIG_SERIAL_8250_NR_UARTS=3
76# CONFIG_HW_RANDOM is not set
77CONFIG_I2C=y
78CONFIG_I2C_CHARDEV=y
79CONFIG_I2C_IXP2000=y
80CONFIG_WATCHDOG=y
81CONFIG_IXP2000_WATCHDOG=y
82CONFIG_EXT2_FS=y
83CONFIG_EXT2_FS_XATTR=y
84CONFIG_EXT2_FS_POSIX_ACL=y
85CONFIG_EXT3_FS=y
86CONFIG_EXT3_FS_POSIX_ACL=y
87CONFIG_INOTIFY=y
88CONFIG_TMPFS=y
89CONFIG_JFFS2_FS=y
90CONFIG_NFS_FS=y
91CONFIG_NFS_V3=y
92CONFIG_ROOT_NFS=y
93CONFIG_PARTITION_ADVANCED=y
94CONFIG_MAGIC_SYSRQ=y
95CONFIG_DEBUG_KERNEL=y
96CONFIG_DEBUG_MUTEXES=y
97CONFIG_DEBUG_USER=y
98CONFIG_DEBUG_ERRORS=y
99CONFIG_DEBUG_LL=y
diff --git a/arch/arm/configs/ixp23xx_defconfig b/arch/arm/configs/ixp23xx_defconfig
deleted file mode 100644
index 688717612e91..000000000000
--- a/arch/arm/configs/ixp23xx_defconfig
+++ /dev/null
@@ -1,105 +0,0 @@
1CONFIG_EXPERIMENTAL=y
2CONFIG_SYSVIPC=y
3CONFIG_BSD_PROCESS_ACCT=y
4CONFIG_LOG_BUF_SHIFT=14
5CONFIG_BLK_DEV_INITRD=y
6CONFIG_EXPERT=y
7CONFIG_SLAB=y
8CONFIG_MODULES=y
9CONFIG_MODULE_UNLOAD=y
10CONFIG_ARCH_IXP23XX=y
11CONFIG_MACH_ESPRESSO=y
12CONFIG_MACH_IXDP2351=y
13CONFIG_MACH_ROADRUNNER=y
14# CONFIG_ARM_THUMB is not set
15CONFIG_CPU_BIG_ENDIAN=y
16CONFIG_ZBOOT_ROM_TEXT=0x0
17CONFIG_ZBOOT_ROM_BSS=0x0
18CONFIG_CMDLINE="console=ttyS0,115200 root=/dev/nfs ip=bootp"
19CONFIG_FPE_NWFPE=y
20CONFIG_FPE_NWFPE_XP=y
21CONFIG_NET=y
22CONFIG_PACKET=y
23CONFIG_UNIX=y
24CONFIG_INET=y
25CONFIG_IP_PNP=y
26CONFIG_IP_PNP_DHCP=y
27CONFIG_IP_PNP_BOOTP=y
28CONFIG_SYN_COOKIES=y
29CONFIG_IPV6=y
30# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
31# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
32# CONFIG_INET6_XFRM_MODE_BEET is not set
33# CONFIG_IPV6_SIT is not set
34# CONFIG_PREVENT_FIRMWARE_BUILD is not set
35# CONFIG_FW_LOADER is not set
36CONFIG_MTD=y
37CONFIG_MTD_PARTITIONS=y
38CONFIG_MTD_REDBOOT_PARTS=y
39CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
40CONFIG_MTD_REDBOOT_PARTS_READONLY=y
41CONFIG_MTD_CHAR=y
42CONFIG_MTD_BLOCK=y
43CONFIG_MTD_CFI=y
44CONFIG_MTD_CFI_INTELEXT=y
45CONFIG_MTD_COMPLEX_MAPPINGS=y
46CONFIG_MTD_PHYSMAP=y
47CONFIG_BLK_DEV_LOOP=y
48CONFIG_BLK_DEV_NBD=y
49CONFIG_BLK_DEV_RAM=y
50CONFIG_BLK_DEV_RAM_SIZE=8192
51CONFIG_EEPROM_LEGACY=y
52CONFIG_IDE=y
53CONFIG_BLK_DEV_SIIMAGE=y
54CONFIG_SCSI=y
55CONFIG_BLK_DEV_SD=y
56CONFIG_NETDEVICES=y
57CONFIG_DUMMY=y
58CONFIG_NET_ETHERNET=y
59CONFIG_NET_PCI=y
60CONFIG_E100=y
61CONFIG_E1000=y
62CONFIG_WAN=y
63CONFIG_HDLC=y
64CONFIG_HDLC_RAW=y
65CONFIG_HDLC_CISCO=y
66CONFIG_HDLC_FR=y
67CONFIG_HDLC_PPP=y
68CONFIG_DLCI=y
69# CONFIG_INPUT_KEYBOARD is not set
70# CONFIG_INPUT_MOUSE is not set
71# CONFIG_SERIO is not set
72# CONFIG_VT is not set
73CONFIG_SERIAL_8250=y
74CONFIG_SERIAL_8250_CONSOLE=y
75# CONFIG_HW_RANDOM is not set
76CONFIG_I2C=y
77CONFIG_I2C_CHARDEV=y
78CONFIG_WATCHDOG=y
79# CONFIG_USB_HID is not set
80CONFIG_USB=y
81CONFIG_USB_MON=y
82CONFIG_USB_EHCI_HCD=y
83CONFIG_USB_OHCI_HCD=y
84CONFIG_USB_UHCI_HCD=y
85CONFIG_USB_STORAGE=y
86CONFIG_EXT2_FS=y
87CONFIG_EXT2_FS_XATTR=y
88CONFIG_EXT2_FS_POSIX_ACL=y
89CONFIG_EXT3_FS=y
90CONFIG_EXT3_FS_POSIX_ACL=y
91CONFIG_INOTIFY=y
92CONFIG_MSDOS_FS=y
93CONFIG_TMPFS=y
94CONFIG_JFFS2_FS=y
95CONFIG_NFS_FS=y
96CONFIG_NFS_V3=y
97CONFIG_ROOT_NFS=y
98CONFIG_PARTITION_ADVANCED=y
99CONFIG_NLS_CODEPAGE_437=y
100CONFIG_MAGIC_SYSRQ=y
101CONFIG_DEBUG_KERNEL=y
102CONFIG_DEBUG_MUTEXES=y
103CONFIG_DEBUG_USER=y
104CONFIG_DEBUG_ERRORS=y
105CONFIG_DEBUG_LL=y
diff --git a/arch/arm/include/asm/hardware/uengine.h b/arch/arm/include/asm/hardware/uengine.h
deleted file mode 100644
index b442d65c6593..000000000000
--- a/arch/arm/include/asm/hardware/uengine.h
+++ /dev/null
@@ -1,62 +0,0 @@
1/*
2 * Generic library functions for the microengines found on the Intel
3 * IXP2000 series of network processors.
4 *
5 * Copyright (C) 2004, 2005 Lennert Buytenhek <buytenh@wantstofly.org>
6 * Dedicated to Marija Kulikova.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU Lesser General Public License as
10 * published by the Free Software Foundation; either version 2.1 of the
11 * License, or (at your option) any later version.
12 */
13
14#ifndef __IXP2000_UENGINE_H
15#define __IXP2000_UENGINE_H
16
17extern u32 ixp2000_uengine_mask;
18
19struct ixp2000_uengine_code
20{
21 u32 cpu_model_bitmask;
22 u8 cpu_min_revision;
23 u8 cpu_max_revision;
24
25 u32 uengine_parameters;
26
27 struct ixp2000_reg_value {
28 int reg;
29 u32 value;
30 } *initial_reg_values;
31
32 int num_insns;
33 u8 *insns;
34};
35
36u32 ixp2000_uengine_csr_read(int uengine, int offset);
37void ixp2000_uengine_csr_write(int uengine, int offset, u32 value);
38void ixp2000_uengine_reset(u32 uengine_mask);
39void ixp2000_uengine_set_mode(int uengine, u32 mode);
40void ixp2000_uengine_load_microcode(int uengine, u8 *ucode, int insns);
41void ixp2000_uengine_init_context(int uengine, int context, int pc);
42void ixp2000_uengine_start_contexts(int uengine, u8 ctx_mask);
43void ixp2000_uengine_stop_contexts(int uengine, u8 ctx_mask);
44int ixp2000_uengine_load(int uengine, struct ixp2000_uengine_code *c);
45
46#define IXP2000_UENGINE_8_CONTEXTS 0x00000000
47#define IXP2000_UENGINE_4_CONTEXTS 0x80000000
48#define IXP2000_UENGINE_PRN_UPDATE_EVERY 0x40000000
49#define IXP2000_UENGINE_PRN_UPDATE_ON_ACCESS 0x00000000
50#define IXP2000_UENGINE_NN_FROM_SELF 0x00100000
51#define IXP2000_UENGINE_NN_FROM_PREVIOUS 0x00000000
52#define IXP2000_UENGINE_ASSERT_EMPTY_AT_3 0x000c0000
53#define IXP2000_UENGINE_ASSERT_EMPTY_AT_2 0x00080000
54#define IXP2000_UENGINE_ASSERT_EMPTY_AT_1 0x00040000
55#define IXP2000_UENGINE_ASSERT_EMPTY_AT_0 0x00000000
56#define IXP2000_UENGINE_LM_ADDR1_GLOBAL 0x00020000
57#define IXP2000_UENGINE_LM_ADDR1_PER_CONTEXT 0x00000000
58#define IXP2000_UENGINE_LM_ADDR0_GLOBAL 0x00010000
59#define IXP2000_UENGINE_LM_ADDR0_PER_CONTEXT 0x00000000
60
61
62#endif
diff --git a/arch/arm/mach-ixp2000/Kconfig b/arch/arm/mach-ixp2000/Kconfig
deleted file mode 100644
index 08d2707f6ca8..000000000000
--- a/arch/arm/mach-ixp2000/Kconfig
+++ /dev/null
@@ -1,72 +0,0 @@
1
2if ARCH_IXP2000
3
4config ARCH_SUPPORTS_BIG_ENDIAN
5 bool
6 default y
7
8menu "Intel IXP2400/2800 Implementation Options"
9
10comment "IXP2400/2800 Platforms"
11
12config ARCH_ENP2611
13 bool "Support Radisys ENP-2611"
14 help
15 Say 'Y' here if you want your kernel to support the Radisys
16 ENP2611 PCI network processing card. For more information on
17 this card, see <file:Documentation/arm/IXP2000>.
18
19config ARCH_IXDP2400
20 bool "Support Intel IXDP2400"
21 help
22 Say 'Y' here if you want your kernel to support the Intel
23 IXDP2400 reference platform. For more information on
24 this platform, see <file:Documentation/arm/IXP2000>.
25
26config ARCH_IXDP2800
27 bool "Support Intel IXDP2800"
28 help
29 Say 'Y' here if you want your kernel to support the Intel
30 IXDP2800 reference platform. For more information on
31 this platform, see <file:Documentation/arm/IXP2000>.
32
33config ARCH_IXDP2X00
34 bool
35 depends on ARCH_IXDP2400 || ARCH_IXDP2800
36 default y
37
38config ARCH_IXDP2401
39 bool "Support Intel IXDP2401"
40 help
41 Say 'Y' here if you want your kernel to support the Intel
42 IXDP2401 reference platform. For more information on
43 this platform, see <file:Documentation/arm/IXP2000>.
44
45config ARCH_IXDP2801
46 bool "Support Intel IXDP2801 and IXDP28x5"
47 help
48 Say 'Y' here if you want your kernel to support the Intel
49 IXDP2801/2805/2855 reference platforms. For more information on
50 this platform, see <file:Documentation/arm/IXP2000>.
51
52config MACH_IXDP28X5
53 bool
54 depends on ARCH_IXDP2801
55 default y
56
57config ARCH_IXDP2X01
58 bool
59 depends on ARCH_IXDP2401 || ARCH_IXDP2801
60 default y
61
62config IXP2000_SUPPORT_BROKEN_PCI_IO
63 bool "Support broken PCI I/O on older IXP2000s"
64 default y
65 help
66 Say 'N' here if you only intend to run your kernel on an
67 IXP2000 B0 or later model and do not need the PCI I/O
68 byteswap workaround. Say 'Y' otherwise.
69
70endmenu
71
72endif
diff --git a/arch/arm/mach-ixp2000/Makefile b/arch/arm/mach-ixp2000/Makefile
deleted file mode 100644
index 1e6139d42a92..000000000000
--- a/arch/arm/mach-ixp2000/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
1#
2# Makefile for the linux kernel.
3#
4obj-y := core.o pci.o
5obj-m :=
6obj-n :=
7obj- :=
8
9obj-$(CONFIG_ARCH_ENP2611) += enp2611.o
10obj-$(CONFIG_ARCH_IXDP2400) += ixdp2400.o
11obj-$(CONFIG_ARCH_IXDP2800) += ixdp2800.o
12obj-$(CONFIG_ARCH_IXDP2X00) += ixdp2x00.o
13obj-$(CONFIG_ARCH_IXDP2X01) += ixdp2x01.o
14
diff --git a/arch/arm/mach-ixp2000/Makefile.boot b/arch/arm/mach-ixp2000/Makefile.boot
deleted file mode 100644
index 9c7af91d93da..000000000000
--- a/arch/arm/mach-ixp2000/Makefile.boot
+++ /dev/null
@@ -1,3 +0,0 @@
1 zreladdr-y += 0x00008000
2params_phys-y := 0x00000100
3
diff --git a/arch/arm/mach-ixp2000/core.c b/arch/arm/mach-ixp2000/core.c
deleted file mode 100644
index f214cdff01cb..000000000000
--- a/arch/arm/mach-ixp2000/core.c
+++ /dev/null
@@ -1,520 +0,0 @@
1/*
2 * arch/arm/mach-ixp2000/core.c
3 *
4 * Common routines used by all IXP2400/2800 based platforms.
5 *
6 * Author: Deepak Saxena <dsaxena@plexity.net>
7 *
8 * Copyright 2004 (C) MontaVista Software, Inc.
9 *
10 * Based on work Copyright (C) 2002-2003 Intel Corporation
11 *
12 * This file is licensed under the terms of the GNU General Public
13 * License version 2. This program is licensed "as is" without any
14 * warranty of any kind, whether express or implied.
15 */
16#include <linux/gpio.h>
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/spinlock.h>
20#include <linux/sched.h>
21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/serial.h>
24#include <linux/tty.h>
25#include <linux/bitops.h>
26#include <linux/serial_8250.h>
27#include <linux/mm.h>
28#include <linux/export.h>
29
30#include <asm/types.h>
31#include <asm/setup.h>
32#include <asm/memory.h>
33#include <mach/hardware.h>
34#include <asm/irq.h>
35#include <asm/tlbflush.h>
36#include <asm/pgtable.h>
37
38#include <asm/mach/map.h>
39#include <asm/mach/time.h>
40#include <asm/mach/irq.h>
41
42#include <mach/gpio-ixp2000.h>
43
44static DEFINE_SPINLOCK(ixp2000_slowport_lock);
45static unsigned long ixp2000_slowport_irq_flags;
46
47/*************************************************************************
48 * Slowport access routines
49 *************************************************************************/
50void ixp2000_acquire_slowport(struct slowport_cfg *new_cfg, struct slowport_cfg *old_cfg)
51{
52 spin_lock_irqsave(&ixp2000_slowport_lock, ixp2000_slowport_irq_flags);
53
54 old_cfg->CCR = *IXP2000_SLOWPORT_CCR;
55 old_cfg->WTC = *IXP2000_SLOWPORT_WTC2;
56 old_cfg->RTC = *IXP2000_SLOWPORT_RTC2;
57 old_cfg->PCR = *IXP2000_SLOWPORT_PCR;
58 old_cfg->ADC = *IXP2000_SLOWPORT_ADC;
59
60 ixp2000_reg_write(IXP2000_SLOWPORT_CCR, new_cfg->CCR);
61 ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, new_cfg->WTC);
62 ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, new_cfg->RTC);
63 ixp2000_reg_write(IXP2000_SLOWPORT_PCR, new_cfg->PCR);
64 ixp2000_reg_wrb(IXP2000_SLOWPORT_ADC, new_cfg->ADC);
65}
66
67void ixp2000_release_slowport(struct slowport_cfg *old_cfg)
68{
69 ixp2000_reg_write(IXP2000_SLOWPORT_CCR, old_cfg->CCR);
70 ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, old_cfg->WTC);
71 ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, old_cfg->RTC);
72 ixp2000_reg_write(IXP2000_SLOWPORT_PCR, old_cfg->PCR);
73 ixp2000_reg_wrb(IXP2000_SLOWPORT_ADC, old_cfg->ADC);
74
75 spin_unlock_irqrestore(&ixp2000_slowport_lock,
76 ixp2000_slowport_irq_flags);
77}
78
79/*************************************************************************
80 * Chip specific mappings shared by all IXP2000 systems
81 *************************************************************************/
82static struct map_desc ixp2000_io_desc[] __initdata = {
83 {
84 .virtual = IXP2000_CAP_VIRT_BASE,
85 .pfn = __phys_to_pfn(IXP2000_CAP_PHYS_BASE),
86 .length = IXP2000_CAP_SIZE,
87 .type = MT_DEVICE,
88 }, {
89 .virtual = IXP2000_INTCTL_VIRT_BASE,
90 .pfn = __phys_to_pfn(IXP2000_INTCTL_PHYS_BASE),
91 .length = IXP2000_INTCTL_SIZE,
92 .type = MT_DEVICE,
93 }, {
94 .virtual = IXP2000_PCI_CREG_VIRT_BASE,
95 .pfn = __phys_to_pfn(IXP2000_PCI_CREG_PHYS_BASE),
96 .length = IXP2000_PCI_CREG_SIZE,
97 .type = MT_DEVICE,
98 }, {
99 .virtual = IXP2000_PCI_CSR_VIRT_BASE,
100 .pfn = __phys_to_pfn(IXP2000_PCI_CSR_PHYS_BASE),
101 .length = IXP2000_PCI_CSR_SIZE,
102 .type = MT_DEVICE,
103 }, {
104 .virtual = IXP2000_MSF_VIRT_BASE,
105 .pfn = __phys_to_pfn(IXP2000_MSF_PHYS_BASE),
106 .length = IXP2000_MSF_SIZE,
107 .type = MT_DEVICE,
108 }, {
109 .virtual = IXP2000_SCRATCH_RING_VIRT_BASE,
110 .pfn = __phys_to_pfn(IXP2000_SCRATCH_RING_PHYS_BASE),
111 .length = IXP2000_SCRATCH_RING_SIZE,
112 .type = MT_DEVICE,
113 }, {
114 .virtual = IXP2000_SRAM0_VIRT_BASE,
115 .pfn = __phys_to_pfn(IXP2000_SRAM0_PHYS_BASE),
116 .length = IXP2000_SRAM0_SIZE,
117 .type = MT_DEVICE,
118 }, {
119 .virtual = IXP2000_PCI_IO_VIRT_BASE,
120 .pfn = __phys_to_pfn(IXP2000_PCI_IO_PHYS_BASE),
121 .length = IXP2000_PCI_IO_SIZE,
122 .type = MT_DEVICE,
123 }, {
124 .virtual = IXP2000_PCI_CFG0_VIRT_BASE,
125 .pfn = __phys_to_pfn(IXP2000_PCI_CFG0_PHYS_BASE),
126 .length = IXP2000_PCI_CFG0_SIZE,
127 .type = MT_DEVICE,
128 }, {
129 .virtual = IXP2000_PCI_CFG1_VIRT_BASE,
130 .pfn = __phys_to_pfn(IXP2000_PCI_CFG1_PHYS_BASE),
131 .length = IXP2000_PCI_CFG1_SIZE,
132 .type = MT_DEVICE,
133 }
134};
135
136void __init ixp2000_map_io(void)
137{
138 iotable_init(ixp2000_io_desc, ARRAY_SIZE(ixp2000_io_desc));
139
140 /* Set slowport to 8-bit mode. */
141 ixp2000_reg_wrb(IXP2000_SLOWPORT_FRM, 1);
142}
143
144
145/*************************************************************************
146 * Serial port support for IXP2000
147 *************************************************************************/
148static struct plat_serial8250_port ixp2000_serial_port[] = {
149 {
150 .mapbase = IXP2000_UART_PHYS_BASE,
151 .membase = (char *)(IXP2000_UART_VIRT_BASE + 3),
152 .irq = IRQ_IXP2000_UART,
153 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
154 .iotype = UPIO_MEM,
155 .regshift = 2,
156 .uartclk = 50000000,
157 },
158 { },
159};
160
161static struct resource ixp2000_uart_resource = {
162 .start = IXP2000_UART_PHYS_BASE,
163 .end = IXP2000_UART_PHYS_BASE + 0x1f,
164 .flags = IORESOURCE_MEM,
165};
166
167static struct platform_device ixp2000_serial_device = {
168 .name = "serial8250",
169 .id = PLAT8250_DEV_PLATFORM,
170 .dev = {
171 .platform_data = ixp2000_serial_port,
172 },
173 .num_resources = 1,
174 .resource = &ixp2000_uart_resource,
175};
176
177void __init ixp2000_uart_init(void)
178{
179 platform_device_register(&ixp2000_serial_device);
180}
181
182
183/*************************************************************************
184 * Timer-tick functions for IXP2000
185 *************************************************************************/
186static unsigned ticks_per_jiffy;
187static unsigned ticks_per_usec;
188static unsigned next_jiffy_time;
189static volatile unsigned long *missing_jiffy_timer_csr;
190
191unsigned long ixp2000_gettimeoffset (void)
192{
193 unsigned long offset;
194
195 offset = next_jiffy_time - *missing_jiffy_timer_csr;
196
197 return offset / ticks_per_usec;
198}
199
200static irqreturn_t ixp2000_timer_interrupt(int irq, void *dev_id)
201{
202 /* clear timer 1 */
203 ixp2000_reg_wrb(IXP2000_T1_CLR, 1);
204
205 while ((signed long)(next_jiffy_time - *missing_jiffy_timer_csr)
206 >= ticks_per_jiffy) {
207 timer_tick();
208 next_jiffy_time -= ticks_per_jiffy;
209 }
210
211 return IRQ_HANDLED;
212}
213
214static struct irqaction ixp2000_timer_irq = {
215 .name = "IXP2000 Timer Tick",
216 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
217 .handler = ixp2000_timer_interrupt,
218};
219
220void __init ixp2000_init_time(unsigned long tick_rate)
221{
222 ticks_per_jiffy = (tick_rate + HZ/2) / HZ;
223 ticks_per_usec = tick_rate / 1000000;
224
225 /*
226 * We use timer 1 as our timer interrupt.
227 */
228 ixp2000_reg_write(IXP2000_T1_CLR, 0);
229 ixp2000_reg_write(IXP2000_T1_CLD, ticks_per_jiffy - 1);
230 ixp2000_reg_write(IXP2000_T1_CTL, (1 << 7));
231
232 /*
233 * We use a second timer as a monotonic counter for tracking
234 * missed jiffies. The IXP2000 has four timers, but if we're
235 * on an A-step IXP2800, timer 2 and 3 don't work, so on those
236 * chips we use timer 4. Timer 4 is the only timer that can
237 * be used for the watchdog, so we use timer 2 if we're on a
238 * non-buggy chip.
239 */
240 if ((*IXP2000_PRODUCT_ID & 0x001ffef0) == 0x00000000) {
241 printk(KERN_INFO "Enabling IXP2800 erratum #25 workaround\n");
242
243 ixp2000_reg_write(IXP2000_T4_CLR, 0);
244 ixp2000_reg_write(IXP2000_T4_CLD, -1);
245 ixp2000_reg_wrb(IXP2000_T4_CTL, (1 << 7));
246 missing_jiffy_timer_csr = IXP2000_T4_CSR;
247 } else {
248 ixp2000_reg_write(IXP2000_T2_CLR, 0);
249 ixp2000_reg_write(IXP2000_T2_CLD, -1);
250 ixp2000_reg_wrb(IXP2000_T2_CTL, (1 << 7));
251 missing_jiffy_timer_csr = IXP2000_T2_CSR;
252 }
253 next_jiffy_time = 0xffffffff;
254
255 /* register for interrupt */
256 setup_irq(IRQ_IXP2000_TIMER1, &ixp2000_timer_irq);
257}
258
259/*************************************************************************
260 * GPIO helpers
261 *************************************************************************/
262static unsigned long GPIO_IRQ_falling_edge;
263static unsigned long GPIO_IRQ_rising_edge;
264static unsigned long GPIO_IRQ_level_low;
265static unsigned long GPIO_IRQ_level_high;
266
267static void update_gpio_int_csrs(void)
268{
269 ixp2000_reg_write(IXP2000_GPIO_FEDR, GPIO_IRQ_falling_edge);
270 ixp2000_reg_write(IXP2000_GPIO_REDR, GPIO_IRQ_rising_edge);
271 ixp2000_reg_write(IXP2000_GPIO_LSLR, GPIO_IRQ_level_low);
272 ixp2000_reg_wrb(IXP2000_GPIO_LSHR, GPIO_IRQ_level_high);
273}
274
275void gpio_line_config(int line, int direction)
276{
277 unsigned long flags;
278
279 local_irq_save(flags);
280 if (direction == GPIO_OUT) {
281 /* if it's an output, it ain't an interrupt anymore */
282 GPIO_IRQ_falling_edge &= ~(1 << line);
283 GPIO_IRQ_rising_edge &= ~(1 << line);
284 GPIO_IRQ_level_low &= ~(1 << line);
285 GPIO_IRQ_level_high &= ~(1 << line);
286 update_gpio_int_csrs();
287
288 ixp2000_reg_wrb(IXP2000_GPIO_PDSR, 1 << line);
289 } else if (direction == GPIO_IN) {
290 ixp2000_reg_wrb(IXP2000_GPIO_PDCR, 1 << line);
291 }
292 local_irq_restore(flags);
293}
294EXPORT_SYMBOL(gpio_line_config);
295
296
297/*************************************************************************
298 * IRQ handling IXP2000
299 *************************************************************************/
300static void ixp2000_GPIO_irq_handler(unsigned int irq, struct irq_desc *desc)
301{
302 int i;
303 unsigned long status = *IXP2000_GPIO_INST;
304
305 for (i = 0; i <= 7; i++) {
306 if (status & (1<<i)) {
307 generic_handle_irq(i + IRQ_IXP2000_GPIO0);
308 }
309 }
310}
311
312static int ixp2000_GPIO_irq_type(struct irq_data *d, unsigned int type)
313{
314 int line = d->irq - IRQ_IXP2000_GPIO0;
315
316 /*
317 * First, configure this GPIO line as an input.
318 */
319 ixp2000_reg_write(IXP2000_GPIO_PDCR, 1 << line);
320
321 /*
322 * Then, set the proper trigger type.
323 */
324 if (type & IRQ_TYPE_EDGE_FALLING)
325 GPIO_IRQ_falling_edge |= 1 << line;
326 else
327 GPIO_IRQ_falling_edge &= ~(1 << line);
328 if (type & IRQ_TYPE_EDGE_RISING)
329 GPIO_IRQ_rising_edge |= 1 << line;
330 else
331 GPIO_IRQ_rising_edge &= ~(1 << line);
332 if (type & IRQ_TYPE_LEVEL_LOW)
333 GPIO_IRQ_level_low |= 1 << line;
334 else
335 GPIO_IRQ_level_low &= ~(1 << line);
336 if (type & IRQ_TYPE_LEVEL_HIGH)
337 GPIO_IRQ_level_high |= 1 << line;
338 else
339 GPIO_IRQ_level_high &= ~(1 << line);
340 update_gpio_int_csrs();
341
342 return 0;
343}
344
345static void ixp2000_GPIO_irq_mask_ack(struct irq_data *d)
346{
347 unsigned int irq = d->irq;
348
349 ixp2000_reg_write(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
350
351 ixp2000_reg_write(IXP2000_GPIO_EDSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
352 ixp2000_reg_write(IXP2000_GPIO_LDSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
353 ixp2000_reg_wrb(IXP2000_GPIO_INST, (1 << (irq - IRQ_IXP2000_GPIO0)));
354}
355
356static void ixp2000_GPIO_irq_mask(struct irq_data *d)
357{
358 unsigned int irq = d->irq;
359
360 ixp2000_reg_wrb(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
361}
362
363static void ixp2000_GPIO_irq_unmask(struct irq_data *d)
364{
365 unsigned int irq = d->irq;
366
367 ixp2000_reg_write(IXP2000_GPIO_INSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
368}
369
370static struct irq_chip ixp2000_GPIO_irq_chip = {
371 .irq_ack = ixp2000_GPIO_irq_mask_ack,
372 .irq_mask = ixp2000_GPIO_irq_mask,
373 .irq_unmask = ixp2000_GPIO_irq_unmask,
374 .irq_set_type = ixp2000_GPIO_irq_type,
375};
376
377static void ixp2000_pci_irq_mask(struct irq_data *d)
378{
379 unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
380 if (d->irq == IRQ_IXP2000_PCIA)
381 ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 26)));
382 else if (d->irq == IRQ_IXP2000_PCIB)
383 ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 27)));
384}
385
386static void ixp2000_pci_irq_unmask(struct irq_data *d)
387{
388 unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
389 if (d->irq == IRQ_IXP2000_PCIA)
390 ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 26)));
391 else if (d->irq == IRQ_IXP2000_PCIB)
392 ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 27)));
393}
394
395/*
396 * Error interrupts. These are used extensively by the microengine drivers
397 */
398static void ixp2000_err_irq_handler(unsigned int irq, struct irq_desc *desc)
399{
400 int i;
401 unsigned long status = *IXP2000_IRQ_ERR_STATUS;
402
403 for(i = 31; i >= 0; i--) {
404 if(status & (1 << i)) {
405 generic_handle_irq(IRQ_IXP2000_DRAM0_MIN_ERR + i);
406 }
407 }
408}
409
410static void ixp2000_err_irq_mask(struct irq_data *d)
411{
412 ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_CLR,
413 (1 << (d->irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
414}
415
416static void ixp2000_err_irq_unmask(struct irq_data *d)
417{
418 ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_SET,
419 (1 << (d->irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
420}
421
422static struct irq_chip ixp2000_err_irq_chip = {
423 .irq_ack = ixp2000_err_irq_mask,
424 .irq_mask = ixp2000_err_irq_mask,
425 .irq_unmask = ixp2000_err_irq_unmask
426};
427
428static struct irq_chip ixp2000_pci_irq_chip = {
429 .irq_ack = ixp2000_pci_irq_mask,
430 .irq_mask = ixp2000_pci_irq_mask,
431 .irq_unmask = ixp2000_pci_irq_unmask
432};
433
434static void ixp2000_irq_mask(struct irq_data *d)
435{
436 ixp2000_reg_wrb(IXP2000_IRQ_ENABLE_CLR, (1 << d->irq));
437}
438
439static void ixp2000_irq_unmask(struct irq_data *d)
440{
441 ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << d->irq));
442}
443
444static struct irq_chip ixp2000_irq_chip = {
445 .irq_ack = ixp2000_irq_mask,
446 .irq_mask = ixp2000_irq_mask,
447 .irq_unmask = ixp2000_irq_unmask
448};
449
450void __init ixp2000_init_irq(void)
451{
452 int irq;
453
454 /*
455 * Mask all sources
456 */
457 ixp2000_reg_write(IXP2000_IRQ_ENABLE_CLR, 0xffffffff);
458 ixp2000_reg_write(IXP2000_FIQ_ENABLE_CLR, 0xffffffff);
459
460 /* clear all GPIO edge/level detects */
461 ixp2000_reg_write(IXP2000_GPIO_REDR, 0);
462 ixp2000_reg_write(IXP2000_GPIO_FEDR, 0);
463 ixp2000_reg_write(IXP2000_GPIO_LSHR, 0);
464 ixp2000_reg_write(IXP2000_GPIO_LSLR, 0);
465 ixp2000_reg_write(IXP2000_GPIO_INCR, -1);
466
467 /* clear PCI interrupt sources */
468 ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, 0);
469
470 /*
471 * Certain bits in the IRQ status register of the
472 * IXP2000 are reserved. Instead of trying to map
473 * things non 1:1 from bit position to IRQ number,
474 * we mark the reserved IRQs as invalid. This makes
475 * our mask/unmask code much simpler.
476 */
477 for (irq = IRQ_IXP2000_SOFT_INT; irq <= IRQ_IXP2000_THDB3; irq++) {
478 if ((1 << irq) & IXP2000_VALID_IRQ_MASK) {
479 irq_set_chip_and_handler(irq, &ixp2000_irq_chip,
480 handle_level_irq);
481 set_irq_flags(irq, IRQF_VALID);
482 } else set_irq_flags(irq, 0);
483 }
484
485 for (irq = IRQ_IXP2000_DRAM0_MIN_ERR; irq <= IRQ_IXP2000_SP_INT; irq++) {
486 if((1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)) &
487 IXP2000_VALID_ERR_IRQ_MASK) {
488 irq_set_chip_and_handler(irq, &ixp2000_err_irq_chip,
489 handle_level_irq);
490 set_irq_flags(irq, IRQF_VALID);
491 }
492 else
493 set_irq_flags(irq, 0);
494 }
495 irq_set_chained_handler(IRQ_IXP2000_ERRSUM, ixp2000_err_irq_handler);
496
497 for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) {
498 irq_set_chip_and_handler(irq, &ixp2000_GPIO_irq_chip,
499 handle_level_irq);
500 set_irq_flags(irq, IRQF_VALID);
501 }
502 irq_set_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler);
503
504 /*
505 * Enable PCI irqs. The actual PCI[AB] decoding is done in
506 * entry-macro.S, so we don't need a chained handler for the
507 * PCI interrupt source.
508 */
509 ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI));
510 for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) {
511 irq_set_chip_and_handler(irq, &ixp2000_pci_irq_chip,
512 handle_level_irq);
513 set_irq_flags(irq, IRQF_VALID);
514 }
515}
516
517void ixp2000_restart(char mode, const char *cmd)
518{
519 ixp2000_reg_wrb(IXP2000_RESET0, RSTALL);
520}
diff --git a/arch/arm/mach-ixp2000/enp2611.c b/arch/arm/mach-ixp2000/enp2611.c
deleted file mode 100644
index 4867f408617c..000000000000
--- a/arch/arm/mach-ixp2000/enp2611.c
+++ /dev/null
@@ -1,265 +0,0 @@
1/*
2 * arch/arm/mach-ixp2000/enp2611.c
3 *
4 * Radisys ENP-2611 support.
5 *
6 * Created 2004 by Lennert Buytenhek from the ixdp2x01 code. The
7 * original version carries the following notices:
8 *
9 * Original Author: Andrzej Mialkowski <andrzej.mialkowski@intel.com>
10 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
11 *
12 * Copyright (C) 2002-2003 Intel Corp.
13 * Copyright (C) 2003-2004 MontaVista Software, Inc.
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 */
20
21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/mm.h>
24#include <linux/sched.h>
25#include <linux/interrupt.h>
26#include <linux/bitops.h>
27#include <linux/pci.h>
28#include <linux/ioport.h>
29#include <linux/delay.h>
30#include <linux/serial.h>
31#include <linux/tty.h>
32#include <linux/serial_core.h>
33#include <linux/platform_device.h>
34#include <linux/io.h>
35
36#include <asm/irq.h>
37#include <asm/pgtable.h>
38#include <asm/page.h>
39#include <mach/hardware.h>
40#include <asm/mach-types.h>
41
42#include <asm/mach/pci.h>
43#include <asm/mach/map.h>
44#include <asm/mach/irq.h>
45#include <asm/mach/time.h>
46#include <asm/mach/arch.h>
47#include <asm/mach/flash.h>
48
49/*************************************************************************
50 * ENP-2611 timer tick configuration
51 *************************************************************************/
52static void __init enp2611_timer_init(void)
53{
54 ixp2000_init_time(50 * 1000 * 1000);
55}
56
57static struct sys_timer enp2611_timer = {
58 .init = enp2611_timer_init,
59 .offset = ixp2000_gettimeoffset,
60};
61
62
63/*************************************************************************
64 * ENP-2611 I/O
65 *************************************************************************/
66static struct map_desc enp2611_io_desc[] __initdata = {
67 {
68 .virtual = ENP2611_CALEB_VIRT_BASE,
69 .pfn = __phys_to_pfn(ENP2611_CALEB_PHYS_BASE),
70 .length = ENP2611_CALEB_SIZE,
71 .type = MT_DEVICE,
72 }, {
73 .virtual = ENP2611_PM3386_0_VIRT_BASE,
74 .pfn = __phys_to_pfn(ENP2611_PM3386_0_PHYS_BASE),
75 .length = ENP2611_PM3386_0_SIZE,
76 .type = MT_DEVICE,
77 }, {
78 .virtual = ENP2611_PM3386_1_VIRT_BASE,
79 .pfn = __phys_to_pfn(ENP2611_PM3386_1_PHYS_BASE),
80 .length = ENP2611_PM3386_1_SIZE,
81 .type = MT_DEVICE,
82 }
83};
84
85void __init enp2611_map_io(void)
86{
87 ixp2000_map_io();
88 iotable_init(enp2611_io_desc, ARRAY_SIZE(enp2611_io_desc));
89}
90
91
92/*************************************************************************
93 * ENP-2611 PCI
94 *************************************************************************/
95static int enp2611_pci_setup(int nr, struct pci_sys_data *sys)
96{
97 sys->mem_offset = 0xe0000000;
98 ixp2000_pci_setup(nr, sys);
99 return 1;
100}
101
102static void __init enp2611_pci_preinit(void)
103{
104 ixp2000_reg_write(IXP2000_PCI_ADDR_EXT, 0x00100000);
105 ixp2000_pci_preinit();
106 pcibios_setup("firmware");
107}
108
109static inline int enp2611_pci_valid_device(struct pci_bus *bus,
110 unsigned int devfn)
111{
112 /* The 82559 ethernet controller appears at both PCI:1:0:0 and
113 * PCI:1:2:0, so let's pretend the second one isn't there.
114 */
115 if (bus->number == 0x01 && devfn == 0x10)
116 return 0;
117
118 return 1;
119}
120
121static int enp2611_pci_read_config(struct pci_bus *bus, unsigned int devfn,
122 int where, int size, u32 *value)
123{
124 if (enp2611_pci_valid_device(bus, devfn))
125 return ixp2000_pci_read_config(bus, devfn, where, size, value);
126
127 return PCIBIOS_DEVICE_NOT_FOUND;
128}
129
130static int enp2611_pci_write_config(struct pci_bus *bus, unsigned int devfn,
131 int where, int size, u32 value)
132{
133 if (enp2611_pci_valid_device(bus, devfn))
134 return ixp2000_pci_write_config(bus, devfn, where, size, value);
135
136 return PCIBIOS_DEVICE_NOT_FOUND;
137}
138
139static struct pci_ops enp2611_pci_ops = {
140 .read = enp2611_pci_read_config,
141 .write = enp2611_pci_write_config
142};
143
144static struct pci_bus * __init enp2611_pci_scan_bus(int nr,
145 struct pci_sys_data *sys)
146{
147 return pci_scan_root_bus(NULL, sys->busnr, &enp2611_pci_ops, sys,
148 &sys->resources);
149}
150
151static int __init enp2611_pci_map_irq(const struct pci_dev *dev, u8 slot,
152 u8 pin)
153{
154 int irq;
155
156 if (dev->bus->number == 0 && PCI_SLOT(dev->devfn) == 0) {
157 /* IXP2400. */
158 irq = IRQ_IXP2000_PCIA;
159 } else if (dev->bus->number == 0 && PCI_SLOT(dev->devfn) == 1) {
160 /* 21555 non-transparent bridge. */
161 irq = IRQ_IXP2000_PCIB;
162 } else if (dev->bus->number == 0 && PCI_SLOT(dev->devfn) == 4) {
163 /* PCI2050B transparent bridge. */
164 irq = -1;
165 } else if (dev->bus->number == 1 && PCI_SLOT(dev->devfn) == 0) {
166 /* 82559 ethernet. */
167 irq = IRQ_IXP2000_PCIA;
168 } else if (dev->bus->number == 1 && PCI_SLOT(dev->devfn) == 1) {
169 /* SPI-3 option board. */
170 irq = IRQ_IXP2000_PCIB;
171 } else {
172 printk(KERN_ERR "enp2611_pci_map_irq() called for unknown "
173 "device PCI:%d:%d:%d\n", dev->bus->number,
174 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
175 irq = -1;
176 }
177
178 return irq;
179}
180
181struct hw_pci enp2611_pci __initdata = {
182 .nr_controllers = 1,
183 .setup = enp2611_pci_setup,
184 .preinit = enp2611_pci_preinit,
185 .scan = enp2611_pci_scan_bus,
186 .map_irq = enp2611_pci_map_irq,
187};
188
189int __init enp2611_pci_init(void)
190{
191 if (machine_is_enp2611())
192 pci_common_init(&enp2611_pci);
193
194 return 0;
195}
196
197subsys_initcall(enp2611_pci_init);
198
199
200/*************************************************************************
201 * ENP-2611 Machine Initialization
202 *************************************************************************/
203static struct flash_platform_data enp2611_flash_platform_data = {
204 .map_name = "cfi_probe",
205 .width = 1,
206};
207
208static struct ixp2000_flash_data enp2611_flash_data = {
209 .platform_data = &enp2611_flash_platform_data,
210 .nr_banks = 1
211};
212
213static struct resource enp2611_flash_resource = {
214 .start = 0xc4000000,
215 .end = 0xc4000000 + 0x00ffffff,
216 .flags = IORESOURCE_MEM,
217};
218
219static struct platform_device enp2611_flash = {
220 .name = "IXP2000-Flash",
221 .id = 0,
222 .dev = {
223 .platform_data = &enp2611_flash_data,
224 },
225 .num_resources = 1,
226 .resource = &enp2611_flash_resource,
227};
228
229static struct ixp2000_i2c_pins enp2611_i2c_gpio_pins = {
230 .sda_pin = ENP2611_GPIO_SDA,
231 .scl_pin = ENP2611_GPIO_SCL,
232};
233
234static struct platform_device enp2611_i2c_controller = {
235 .name = "IXP2000-I2C",
236 .id = 0,
237 .dev = {
238 .platform_data = &enp2611_i2c_gpio_pins
239 },
240 .num_resources = 0
241};
242
243static struct platform_device *enp2611_devices[] __initdata = {
244 &enp2611_flash,
245 &enp2611_i2c_controller
246};
247
248static void __init enp2611_init_machine(void)
249{
250 platform_add_devices(enp2611_devices, ARRAY_SIZE(enp2611_devices));
251 ixp2000_uart_init();
252}
253
254
255MACHINE_START(ENP2611, "Radisys ENP-2611 PCI network processor board")
256 /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
257 .atag_offset = 0x100,
258 .map_io = enp2611_map_io,
259 .init_irq = ixp2000_init_irq,
260 .timer = &enp2611_timer,
261 .init_machine = enp2611_init_machine,
262 .restart = ixp2000_restart,
263MACHINE_END
264
265
diff --git a/arch/arm/mach-ixp2000/include/mach/debug-macro.S b/arch/arm/mach-ixp2000/include/mach/debug-macro.S
deleted file mode 100644
index bdd3ccdc2890..000000000000
--- a/arch/arm/mach-ixp2000/include/mach/debug-macro.S
+++ /dev/null
@@ -1,25 +0,0 @@
1/* arch/arm/mach-ixp2000/include/mach/debug-macro.S
2 *
3 * Debugging macro include header
4 *
5 * Copyright (C) 1994-1999 Russell King
6 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14 .macro addruart, rp, rv, tmp
15 mov \rp, #0x00030000
16#ifdef __ARMEB__
17 orr \rp, \rp, #0x00000003
18#endif
19 orr \rv, \rp, #0xfe000000 @ virtual base
20 orr \rv, \rv, #0x00f00000
21 orr \rp, \rp, #0xc0000000 @ Physical base
22 .endm
23
24#define UART_SHIFT 2
25#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-ixp2000/include/mach/enp2611.h b/arch/arm/mach-ixp2000/include/mach/enp2611.h
deleted file mode 100644
index 9ce3690061d5..000000000000
--- a/arch/arm/mach-ixp2000/include/mach/enp2611.h
+++ /dev/null
@@ -1,46 +0,0 @@
1/*
2 * arch/arm/mach-ixp2000/include/mach/enp2611.h
3 *
4 * Register and other defines for Radisys ENP-2611
5 *
6 * Created 2004 by Lennert Buytenhek from the ixdp2x01 code. The
7 * original version carries the following notices:
8 *
9 * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
10 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
11 *
12 * Copyright (C) 2002 Intel Corp.
13 * Copyright (C) 2003-2004 MontaVista Software, Inc.
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 */
20
21#ifndef __ENP2611_H
22#define __ENP2611_H
23
24#define ENP2611_CALEB_PHYS_BASE 0xc5000000
25#define ENP2611_CALEB_VIRT_BASE 0xfe000000
26#define ENP2611_CALEB_SIZE 0x00100000
27
28#define ENP2611_PM3386_0_PHYS_BASE 0xc6000000
29#define ENP2611_PM3386_0_VIRT_BASE 0xfe100000
30#define ENP2611_PM3386_0_SIZE 0x00100000
31
32#define ENP2611_PM3386_1_PHYS_BASE 0xc6400000
33#define ENP2611_PM3386_1_VIRT_BASE 0xfe200000
34#define ENP2611_PM3386_1_SIZE 0x00100000
35
36#define ENP2611_GPIO_SCL 7
37#define ENP2611_GPIO_SDA 6
38
39#define IRQ_ENP2611_THERMAL IRQ_IXP2000_GPIO4
40#define IRQ_ENP2611_OPTION_BOARD IRQ_IXP2000_GPIO3
41#define IRQ_ENP2611_CALEB IRQ_IXP2000_GPIO2
42#define IRQ_ENP2611_PM3386_1 IRQ_IXP2000_GPIO1
43#define IRQ_ENP2611_PM3386_0 IRQ_IXP2000_GPIO0
44
45
46#endif
diff --git a/arch/arm/mach-ixp2000/include/mach/entry-macro.S b/arch/arm/mach-ixp2000/include/mach/entry-macro.S
deleted file mode 100644
index c4444dff9202..000000000000
--- a/arch/arm/mach-ixp2000/include/mach/entry-macro.S
+++ /dev/null
@@ -1,54 +0,0 @@
1/*
2 * arch/arm/mach-ixp2000/include/mach/entry-macro.S
3 *
4 * Low-level IRQ helper macros for IXP2000-based platforms
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10#include <mach/irqs.h>
11
12 .macro get_irqnr_preamble, base, tmp
13 .endm
14
15 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
16
17 mov \irqnr, #0x0 @clear out irqnr as default
18 mov \base, #0xfe000000
19 orr \base, \base, #0x00e00000
20 orr \base, \base, #0x08
21 ldr \irqstat, [\base] @ get interrupts
22
23 cmp \irqstat, #0
24 beq 1001f
25
26 clz \irqnr, \irqstat
27 mov \base, #31
28 subs \irqnr, \base, \irqnr
29
30 /*
31 * We handle PCIA and PCIB here so we don't have an
32 * extra layer of code just to check these two bits.
33 */
34 cmp \irqnr, #IRQ_IXP2000_PCI
35 bne 1001f
36
37 mov \base, #0xfe000000
38 orr \base, \base, #0x00c00000
39 orr \base, \base, #0x00000100
40 orr \base, \base, #0x00000058
41 ldr \irqstat, [\base]
42
43 mov \tmp, #(1<<26)
44 tst \irqstat, \tmp
45 movne \irqnr, #IRQ_IXP2000_PCIA
46 bne 1001f
47
48 mov \tmp, #(1<<27)
49 tst \irqstat, \tmp
50 movne \irqnr, #IRQ_IXP2000_PCIB
51
521001:
53 .endm
54
diff --git a/arch/arm/mach-ixp2000/include/mach/gpio-ixp2000.h b/arch/arm/mach-ixp2000/include/mach/gpio-ixp2000.h
deleted file mode 100644
index af836c76c3f1..000000000000
--- a/arch/arm/mach-ixp2000/include/mach/gpio-ixp2000.h
+++ /dev/null
@@ -1,48 +0,0 @@
1/*
2 * arch/arm/mach-ixp2000/include/mach/gpio.h
3 *
4 * Copyright (C) 2002 Intel Corporation.
5 *
6 * This program is free software, you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11/*
12 * IXP2000 GPIO in/out, edge/level detection for IRQs:
13 * IRQs are generated on Falling-edge, Rising-Edge, Level-low, Level-High
14 * or both Falling-edge and Rising-edge.
15 * This must be called *before* the corresponding IRQ is registerd.
16 * Use this instead of directly setting the GPIO registers.
17 * GPIOs may also be used as GPIOs (e.g. for emulating i2c/smb)
18 */
19#ifndef __ASM_ARCH_GPIO_H
20#define __ASM_ARCH_GPIO_H
21
22#ifndef __ASSEMBLY__
23
24#define GPIO_IN 0
25#define GPIO_OUT 1
26
27#define IXP2000_GPIO_LOW 0
28#define IXP2000_GPIO_HIGH 1
29
30extern void gpio_line_config(int line, int direction);
31
32static inline int gpio_line_get(int line)
33{
34 return (((*IXP2000_GPIO_PLR) >> line) & 1);
35}
36
37static inline void gpio_line_set(int line, int value)
38{
39 if (value == IXP2000_GPIO_HIGH) {
40 ixp2000_reg_write(IXP2000_GPIO_POSR, 1 << line);
41 } else if (value == IXP2000_GPIO_LOW) {
42 ixp2000_reg_write(IXP2000_GPIO_POCR, 1 << line);
43 }
44}
45
46#endif /* !__ASSEMBLY__ */
47
48#endif /* ASM_ARCH_IXP2000_GPIO_H_ */
diff --git a/arch/arm/mach-ixp2000/include/mach/hardware.h b/arch/arm/mach-ixp2000/include/mach/hardware.h
deleted file mode 100644
index cdaf1db84003..000000000000
--- a/arch/arm/mach-ixp2000/include/mach/hardware.h
+++ /dev/null
@@ -1,36 +0,0 @@
1/*
2 * arch/arm/mach-ixp2000/include/mach/hardware.h
3 *
4 * Hardware definitions for IXP2400/2800 based systems
5 *
6 * Original Author: Naeem M Afzal <naeem.m.afzal@intel.com>
7 *
8 * Maintainer: Deepak Saxena <dsaxena@mvista.com>
9 *
10 * Copyright (C) 2001-2002 Intel Corp.
11 * Copyright (C) 2003-2004 MontaVista Software, Inc.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 */
18
19#ifndef __ASM_ARCH_HARDWARE_H__
20#define __ASM_ARCH_HARDWARE_H__
21
22#include "ixp2000-regs.h" /* Chipset Registers */
23
24/*
25 * Platform helper functions
26 */
27#include "platform.h"
28
29/*
30 * Platform-specific bits
31 */
32#include "enp2611.h" /* ENP-2611 */
33#include "ixdp2x00.h" /* IXDP2400/2800 */
34#include "ixdp2x01.h" /* IXDP2401/2801 */
35
36#endif /* _ASM_ARCH_HARDWARE_H__ */
diff --git a/arch/arm/mach-ixp2000/include/mach/io.h b/arch/arm/mach-ixp2000/include/mach/io.h
deleted file mode 100644
index f6552d6f35ab..000000000000
--- a/arch/arm/mach-ixp2000/include/mach/io.h
+++ /dev/null
@@ -1,133 +0,0 @@
1/*
2 * arch/arm/mach-ixp2000/include/mach/io.h
3 *
4 * Original Author: Naeem M Afzal <naeem.m.afzal@intel.com>
5 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
6 *
7 * Copyright (C) 2002 Intel Corp.
8 * Copyrgiht (C) 2003-2004 MontaVista Software, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#ifndef __ASM_ARM_ARCH_IO_H
16#define __ASM_ARM_ARCH_IO_H
17
18#include <mach/hardware.h>
19
20#define IO_SPACE_LIMIT 0xffffffff
21
22/*
23 * The A? revisions of the IXP2000s assert byte lanes for PCI I/O
24 * transactions the other way round (MEM transactions don't have this
25 * issue), so if we want to support those models, we need to override
26 * the standard I/O functions.
27 *
28 * B0 and later have a bit that can be set to 1 to get the proper
29 * behavior for I/O transactions, which then allows us to use the
30 * standard I/O functions. This is what we do if the user does not
31 * explicitly ask for support for pre-B0.
32 */
33#ifdef CONFIG_IXP2000_SUPPORT_BROKEN_PCI_IO
34#define ___io(p) ((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE))
35
36#define alignb(addr) (void __iomem *)((unsigned long)(addr) ^ 3)
37#define alignw(addr) (void __iomem *)((unsigned long)(addr) ^ 2)
38
39#define outb(v,p) __raw_writeb((v),alignb(___io(p)))
40#define outw(v,p) __raw_writew((v),alignw(___io(p)))
41#define outl(v,p) __raw_writel((v),___io(p))
42
43#define inb(p) ({ unsigned int __v = __raw_readb(alignb(___io(p))); __v; })
44#define inw(p) \
45 ({ unsigned int __v = (__raw_readw(alignw(___io(p)))); __v; })
46#define inl(p) \
47 ({ unsigned int __v = (__raw_readl(___io(p))); __v; })
48
49#define outsb(p,d,l) __raw_writesb(alignb(___io(p)),d,l)
50#define outsw(p,d,l) __raw_writesw(alignw(___io(p)),d,l)
51#define outsl(p,d,l) __raw_writesl(___io(p),d,l)
52
53#define insb(p,d,l) __raw_readsb(alignb(___io(p)),d,l)
54#define insw(p,d,l) __raw_readsw(alignw(___io(p)),d,l)
55#define insl(p,d,l) __raw_readsl(___io(p),d,l)
56
57#define __is_io_address(p) ((((unsigned long)(p)) & ~(IXP2000_PCI_IO_SIZE - 1)) == IXP2000_PCI_IO_VIRT_BASE)
58
59#define ioread8(p) \
60 ({ \
61 unsigned int __v; \
62 \
63 if (__is_io_address(p)) { \
64 __v = __raw_readb(alignb(p)); \
65 } else { \
66 __v = __raw_readb(p); \
67 } \
68 \
69 __v; \
70 }) \
71
72#define ioread16(p) \
73 ({ \
74 unsigned int __v; \
75 \
76 if (__is_io_address(p)) { \
77 __v = __raw_readw(alignw(p)); \
78 } else { \
79 __v = le16_to_cpu(__raw_readw(p)); \
80 } \
81 \
82 __v; \
83 })
84
85#define ioread32(p) \
86 ({ \
87 unsigned int __v; \
88 \
89 if (__is_io_address(p)) { \
90 __v = __raw_readl(p); \
91 } else { \
92 __v = le32_to_cpu(__raw_readl(p)); \
93 } \
94 \
95 __v; \
96 })
97
98#define iowrite8(v,p) \
99 ({ \
100 if (__is_io_address(p)) { \
101 __raw_writeb((v), alignb(p)); \
102 } else { \
103 __raw_writeb((v), p); \
104 } \
105 })
106
107#define iowrite16(v,p) \
108 ({ \
109 if (__is_io_address(p)) { \
110 __raw_writew((v), alignw(p)); \
111 } else { \
112 __raw_writew(cpu_to_le16(v), p); \
113 } \
114 })
115
116#define iowrite32(v,p) \
117 ({ \
118 if (__is_io_address(p)) { \
119 __raw_writel((v), p); \
120 } else { \
121 __raw_writel(cpu_to_le32(v), p); \
122 } \
123 })
124
125#define ioport_map(port, nr) ___io(port)
126
127#define ioport_unmap(addr)
128#else
129#define __io(p) ((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE))
130#endif
131
132
133#endif
diff --git a/arch/arm/mach-ixp2000/include/mach/irqs.h b/arch/arm/mach-ixp2000/include/mach/irqs.h
deleted file mode 100644
index bee96bcafdca..000000000000
--- a/arch/arm/mach-ixp2000/include/mach/irqs.h
+++ /dev/null
@@ -1,207 +0,0 @@
1/*
2 * arch/arm/mach-ixp2000/include/mach/irqs.h
3 *
4 * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
5 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
6 *
7 * Copyright (C) 2002 Intel Corp.
8 * Copyright (C) 2003-2004 MontaVista Software, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#ifndef _IRQS_H
16#define _IRQS_H
17
18/*
19 * Do NOT add #ifdef MACHINE_FOO in here.
20 * Simpy add your machine IRQs here and increase NR_IRQS if needed to
21 * hold your machine's IRQ table.
22 */
23
24/*
25 * Some interrupt numbers go unused b/c the IRQ mask/ummask/status
26 * register has those bit reserved. We just mark those interrupts
27 * as invalid and this allows us to do mask/unmask with a single
28 * shift operation instead of having to map the IRQ number to
29 * a HW IRQ number.
30 */
31#define IRQ_IXP2000_SOFT_INT 0 /* soft interrupt */
32#define IRQ_IXP2000_ERRSUM 1 /* OR of all bits in ErrorStatus reg*/
33#define IRQ_IXP2000_UART 2
34#define IRQ_IXP2000_GPIO 3
35#define IRQ_IXP2000_TIMER1 4
36#define IRQ_IXP2000_TIMER2 5
37#define IRQ_IXP2000_TIMER3 6
38#define IRQ_IXP2000_TIMER4 7
39#define IRQ_IXP2000_PMU 8
40#define IRQ_IXP2000_SPF 9 /* Slow port framer IRQ */
41#define IRQ_IXP2000_DMA1 10
42#define IRQ_IXP2000_DMA2 11
43#define IRQ_IXP2000_DMA3 12
44#define IRQ_IXP2000_PCI_DOORBELL 13
45#define IRQ_IXP2000_ME_ATTN 14
46#define IRQ_IXP2000_PCI 15 /* PCI INTA or INTB */
47#define IRQ_IXP2000_THDA0 16 /* thread 0-31A */
48#define IRQ_IXP2000_THDA1 17 /* thread 32-63A, IXP2800 only */
49#define IRQ_IXP2000_THDA2 18 /* thread 64-95A */
50#define IRQ_IXP2000_THDA3 19 /* thread 96-127A, IXP2800 only */
51#define IRQ_IXP2000_THDB0 24 /* thread 0-31B */
52#define IRQ_IXP2000_THDB1 25 /* thread 32-63B, IXP2800 only */
53#define IRQ_IXP2000_THDB2 26 /* thread 64-95B */
54#define IRQ_IXP2000_THDB3 27 /* thread 96-127B, IXP2800 only */
55
56/* define generic GPIOs */
57#define IRQ_IXP2000_GPIO0 32
58#define IRQ_IXP2000_GPIO1 33
59#define IRQ_IXP2000_GPIO2 34
60#define IRQ_IXP2000_GPIO3 35
61#define IRQ_IXP2000_GPIO4 36
62#define IRQ_IXP2000_GPIO5 37
63#define IRQ_IXP2000_GPIO6 38
64#define IRQ_IXP2000_GPIO7 39
65
66/* split off the 2 PCI sources */
67#define IRQ_IXP2000_PCIA 40
68#define IRQ_IXP2000_PCIB 41
69
70/* Int sources from IRQ_ERROR_STATUS */
71#define IRQ_IXP2000_DRAM0_MIN_ERR 42
72#define IRQ_IXP2000_DRAM0_MAJ_ERR 43
73#define IRQ_IXP2000_DRAM1_MIN_ERR 44
74#define IRQ_IXP2000_DRAM1_MAJ_ERR 45
75#define IRQ_IXP2000_DRAM2_MIN_ERR 46
76#define IRQ_IXP2000_DRAM2_MAJ_ERR 47
77/* 48-57 reserved */
78#define IRQ_IXP2000_SRAM0_ERR 58
79#define IRQ_IXP2000_SRAM1_ERR 59
80#define IRQ_IXP2000_SRAM2_ERR 60
81#define IRQ_IXP2000_SRAM3_ERR 61
82/* 62-65 reserved */
83#define IRQ_IXP2000_MEDIA_ERR 66
84#define IRQ_IXP2000_PCI_ERR 67
85#define IRQ_IXP2000_SP_INT 68
86
87#define NR_IXP2000_IRQS 69
88
89#define IXP2000_BOARD_IRQ(x) (NR_IXP2000_IRQS + (x))
90
91#define IXP2000_BOARD_IRQ_MASK(irq) (1 << (irq - NR_IXP2000_IRQS))
92
93#define IXP2000_ERR_IRQ_MASK(irq) ( 1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR))
94#define IXP2000_VALID_ERR_IRQ_MASK (\
95 IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM0_MIN_ERR) | \
96 IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM0_MAJ_ERR) | \
97 IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM1_MIN_ERR) | \
98 IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM1_MAJ_ERR) | \
99 IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM2_MIN_ERR) | \
100 IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM2_MAJ_ERR) | \
101 IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM0_ERR) | \
102 IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM1_ERR) | \
103 IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM2_ERR) | \
104 IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM3_ERR) | \
105 IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_MEDIA_ERR) | \
106 IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_PCI_ERR) | \
107 IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SP_INT) )
108
109/*
110 * This allows for all the on-chip sources plus up to 32 CPLD based
111 * IRQs. Should be more than enough.
112 */
113#define IXP2000_BOARD_IRQS 32
114#define NR_IRQS (NR_IXP2000_IRQS + IXP2000_BOARD_IRQS)
115
116
117/*
118 * IXDP2400 specific IRQs
119 */
120#define IRQ_IXDP2400_INGRESS_NPU IXP2000_BOARD_IRQ(0)
121#define IRQ_IXDP2400_ENET IXP2000_BOARD_IRQ(1)
122#define IRQ_IXDP2400_MEDIA_PCI IXP2000_BOARD_IRQ(2)
123#define IRQ_IXDP2400_MEDIA_SP IXP2000_BOARD_IRQ(3)
124#define IRQ_IXDP2400_SF_PCI IXP2000_BOARD_IRQ(4)
125#define IRQ_IXDP2400_SF_SP IXP2000_BOARD_IRQ(5)
126#define IRQ_IXDP2400_PMC IXP2000_BOARD_IRQ(6)
127#define IRQ_IXDP2400_TVM IXP2000_BOARD_IRQ(7)
128
129#define NR_IXDP2400_IRQS ((IRQ_IXDP2400_TVM)+1)
130#define IXDP2400_NR_IRQS NR_IXDP2400_IRQS - NR_IXP2000_IRQS
131
132/* IXDP2800 specific IRQs */
133#define IRQ_IXDP2800_EGRESS_ENET IXP2000_BOARD_IRQ(0)
134#define IRQ_IXDP2800_INGRESS_NPU IXP2000_BOARD_IRQ(1)
135#define IRQ_IXDP2800_PMC IXP2000_BOARD_IRQ(2)
136#define IRQ_IXDP2800_FABRIC_PCI IXP2000_BOARD_IRQ(3)
137#define IRQ_IXDP2800_FABRIC IXP2000_BOARD_IRQ(4)
138#define IRQ_IXDP2800_MEDIA IXP2000_BOARD_IRQ(5)
139
140#define NR_IXDP2800_IRQS ((IRQ_IXDP2800_MEDIA)+1)
141#define IXDP2800_NR_IRQS NR_IXDP2800_IRQS - NR_IXP2000_IRQS
142
143/*
144 * IRQs on both IXDP2x01 boards
145 */
146#define IRQ_IXDP2X01_SPCI_DB_0 IXP2000_BOARD_IRQ(2)
147#define IRQ_IXDP2X01_SPCI_DB_1 IXP2000_BOARD_IRQ(3)
148#define IRQ_IXDP2X01_SPCI_PMC_INTA IXP2000_BOARD_IRQ(4)
149#define IRQ_IXDP2X01_SPCI_PMC_INTB IXP2000_BOARD_IRQ(5)
150#define IRQ_IXDP2X01_SPCI_PMC_INTC IXP2000_BOARD_IRQ(6)
151#define IRQ_IXDP2X01_SPCI_PMC_INTD IXP2000_BOARD_IRQ(7)
152#define IRQ_IXDP2X01_SPCI_FIC_INT IXP2000_BOARD_IRQ(8)
153#define IRQ_IXDP2X01_IPMI_FROM IXP2000_BOARD_IRQ(16)
154#define IRQ_IXDP2X01_125US IXP2000_BOARD_IRQ(17)
155#define IRQ_IXDP2X01_DB_0_ADD IXP2000_BOARD_IRQ(18)
156#define IRQ_IXDP2X01_DB_1_ADD IXP2000_BOARD_IRQ(19)
157#define IRQ_IXDP2X01_UART1 IXP2000_BOARD_IRQ(21)
158#define IRQ_IXDP2X01_UART2 IXP2000_BOARD_IRQ(22)
159#define IRQ_IXDP2X01_FIC_ADD_INT IXP2000_BOARD_IRQ(24)
160#define IRQ_IXDP2X01_CS8900 IXP2000_BOARD_IRQ(25)
161#define IRQ_IXDP2X01_BBSRAM IXP2000_BOARD_IRQ(26)
162
163#define IXDP2X01_VALID_IRQ_MASK ( \
164 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_DB_0) | \
165 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_DB_1) | \
166 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTA) | \
167 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTB) | \
168 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTC) | \
169 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTD) | \
170 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_FIC_INT) | \
171 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_IPMI_FROM) | \
172 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_125US) | \
173 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_DB_0_ADD) | \
174 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_DB_1_ADD) | \
175 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_UART1) | \
176 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_UART2) | \
177 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_FIC_ADD_INT) | \
178 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_CS8900) | \
179 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_BBSRAM) )
180
181/*
182 * IXDP2401 specific IRQs
183 */
184#define IRQ_IXDP2401_INTA_82546 IXP2000_BOARD_IRQ(0)
185#define IRQ_IXDP2401_INTB_82546 IXP2000_BOARD_IRQ(1)
186
187#define IXDP2401_VALID_IRQ_MASK ( \
188 IXDP2X01_VALID_IRQ_MASK | \
189 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2401_INTA_82546) |\
190 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2401_INTB_82546))
191
192/*
193 * IXDP2801-specific IRQs
194 */
195#define IRQ_IXDP2801_RIV IXP2000_BOARD_IRQ(0)
196#define IRQ_IXDP2801_CNFG_MEDIA IXP2000_BOARD_IRQ(27)
197#define IRQ_IXDP2801_CLOCK_REF IXP2000_BOARD_IRQ(28)
198
199#define IXDP2801_VALID_IRQ_MASK ( \
200 IXDP2X01_VALID_IRQ_MASK | \
201 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2801_RIV) |\
202 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2801_CNFG_MEDIA) |\
203 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2801_CLOCK_REF))
204
205#define NR_IXDP2X01_IRQS ((IRQ_IXDP2801_CLOCK_REF) + 1)
206
207#endif /*_IRQS_H*/
diff --git a/arch/arm/mach-ixp2000/include/mach/ixdp2x00.h b/arch/arm/mach-ixp2000/include/mach/ixdp2x00.h
deleted file mode 100644
index 5df8479d9481..000000000000
--- a/arch/arm/mach-ixp2000/include/mach/ixdp2x00.h
+++ /dev/null
@@ -1,92 +0,0 @@
1/*
2 * arch/arm/mach-ixp2000/include/mach/ixdp2x00.h
3 *
4 * Register and other defines for IXDP2[48]00 platforms
5 *
6 * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
7 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
8 *
9 * Copyright (C) 2002 Intel Corp.
10 * Copyright (C) 2003-2004 MontaVista Software, Inc.
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17#ifndef _IXDP2X00_H_
18#define _IXDP2X00_H_
19
20/*
21 * On board CPLD memory map
22 */
23#define IXDP2X00_PHYS_CPLD_BASE 0xc7000000
24#define IXDP2X00_VIRT_CPLD_BASE 0xfe000000
25#define IXDP2X00_CPLD_SIZE 0x00100000
26
27
28#define IXDP2X00_CPLD_REG(x) \
29 (volatile unsigned long *)(IXDP2X00_VIRT_CPLD_BASE | x)
30
31/*
32 * IXDP2400 CPLD registers
33 */
34#define IXDP2400_CPLD_SYSLED IXDP2X00_CPLD_REG(0x0)
35#define IXDP2400_CPLD_DISP_DATA IXDP2X00_CPLD_REG(0x4)
36#define IXDP2400_CPLD_CLOCK_SPEED IXDP2X00_CPLD_REG(0x8)
37#define IXDP2400_CPLD_INT_STAT IXDP2X00_CPLD_REG(0xc)
38#define IXDP2400_CPLD_REV IXDP2X00_CPLD_REG(0x10)
39#define IXDP2400_CPLD_SYS_CLK_M IXDP2X00_CPLD_REG(0x14)
40#define IXDP2400_CPLD_SYS_CLK_N IXDP2X00_CPLD_REG(0x18)
41#define IXDP2400_CPLD_INT_MASK IXDP2X00_CPLD_REG(0x48)
42
43/*
44 * IXDP2800 CPLD registers
45 */
46#define IXDP2800_CPLD_INT_STAT IXDP2X00_CPLD_REG(0x0)
47#define IXDP2800_CPLD_INT_MASK IXDP2X00_CPLD_REG(0x140)
48
49
50#define IXDP2X00_GPIO_I2C_ENABLE 0x02
51#define IXDP2X00_GPIO_SCL 0x07
52#define IXDP2X00_GPIO_SDA 0x06
53
54/*
55 * PCI devfns for on-board devices. We need these to be able to
56 * properly translate IRQs and for device removal.
57 */
58#define IXDP2400_SLAVE_ENET_DEVFN 0x18 /* Bus 1 */
59#define IXDP2400_MASTER_ENET_DEVFN 0x20 /* Bus 1 */
60#define IXDP2400_MEDIA_DEVFN 0x28 /* Bus 1 */
61#define IXDP2400_SWITCH_FABRIC_DEVFN 0x30 /* Bus 1 */
62
63#define IXDP2800_SLAVE_ENET_DEVFN 0x20 /* Bus 1 */
64#define IXDP2800_MASTER_ENET_DEVFN 0x18 /* Bus 1 */
65#define IXDP2800_SWITCH_FABRIC_DEVFN 0x30 /* Bus 1 */
66
67#define IXDP2X00_P2P_DEVFN 0x20 /* Bus 0 */
68#define IXDP2X00_21555_DEVFN 0x30 /* Bus 0 */
69#define IXDP2X00_SLAVE_NPU_DEVFN 0x28 /* Bus 1 */
70#define IXDP2X00_PMC_DEVFN 0x38 /* Bus 1 */
71#define IXDP2X00_MASTER_NPU_DEVFN 0x38 /* Bus 1 */
72
73#ifndef __ASSEMBLY__
74/*
75 * The master NPU is always PCI master.
76 */
77static inline unsigned int ixdp2x00_master_npu(void)
78{
79 return !!ixp2000_is_pcimaster();
80}
81
82/*
83 * Helper functions used by ixdp2400 and ixdp2800 specific code
84 */
85void ixdp2x00_init_irq(volatile unsigned long*, volatile unsigned long *, unsigned long);
86void ixdp2x00_slave_pci_postinit(void);
87void ixdp2x00_init_machine(void);
88void ixdp2x00_map_io(void);
89
90#endif
91
92#endif /*_IXDP2X00_H_ */
diff --git a/arch/arm/mach-ixp2000/include/mach/ixdp2x01.h b/arch/arm/mach-ixp2000/include/mach/ixdp2x01.h
deleted file mode 100644
index 4c1f04083e54..000000000000
--- a/arch/arm/mach-ixp2000/include/mach/ixdp2x01.h
+++ /dev/null
@@ -1,57 +0,0 @@
1/*
2 * arch/arm/mach-ixp2000/include/mach/ixdp2x01.h
3 *
4 * Platform definitions for IXDP2X01 && IXDP2801 systems
5 *
6 * Author: Deepak Saxena <dsaxena@plexity.net>
7 *
8 * Copyright 2004 (c) MontaVista Software, Inc.
9 *
10 * Based on original code Copyright (c) 2002-2003 Intel Corporation
11 *
12 * This file is licensed under the terms of the GNU General Public
13 * License version 2. This program is licensed "as is" without any
14 * warranty of any kind, whether express or implied.
15 */
16
17#ifndef __IXDP2X01_H__
18#define __IXDP2X01_H__
19
20#define IXDP2X01_PHYS_CPLD_BASE 0xc6024000
21#define IXDP2X01_VIRT_CPLD_BASE 0xfe000000
22#define IXDP2X01_CPLD_REGION_SIZE 0x00100000
23
24#define IXDP2X01_CPLD_VIRT_REG(reg) (volatile unsigned long*)(IXDP2X01_VIRT_CPLD_BASE | reg)
25#define IXDP2X01_CPLD_PHYS_REG(reg) (IXDP2X01_PHYS_CPLD_BASE | reg)
26
27#define IXDP2X01_UART1_VIRT_BASE IXDP2X01_CPLD_VIRT_REG(0x40)
28#define IXDP2X01_UART1_PHYS_BASE IXDP2X01_CPLD_PHYS_REG(0x40)
29
30#define IXDP2X01_UART2_VIRT_BASE IXDP2X01_CPLD_VIRT_REG(0x60)
31#define IXDP2X01_UART2_PHYS_BASE IXDP2X01_CPLD_PHYS_REG(0x60)
32
33#define IXDP2X01_CS8900_VIRT_BASE IXDP2X01_CPLD_VIRT_REG(0x80)
34#define IXDP2X01_CS8900_VIRT_END (IXDP2X01_CS8900_VIRT_BASE + 16)
35
36#define IXDP2X01_CPLD_RESET_REG IXDP2X01_CPLD_VIRT_REG(0x00)
37#define IXDP2X01_INT_MASK_SET_REG IXDP2X01_CPLD_VIRT_REG(0x08)
38#define IXDP2X01_INT_STAT_REG IXDP2X01_CPLD_VIRT_REG(0x0C)
39#define IXDP2X01_INT_RAW_REG IXDP2X01_CPLD_VIRT_REG(0x10)
40#define IXDP2X01_INT_MASK_CLR_REG IXDP2X01_INT_RAW_REG
41#define IXDP2X01_INT_SIM_REG IXDP2X01_CPLD_VIRT_REG(0x14)
42
43#define IXDP2X01_CPLD_FLASH_REG IXDP2X01_CPLD_VIRT_REG(0x20)
44
45#define IXDP2X01_CPLD_FLASH_INTERN 0x8000
46#define IXDP2X01_CPLD_FLASH_BANK_MASK 0xF
47#define IXDP2X01_FLASH_WINDOW_BITS 25
48#define IXDP2X01_FLASH_WINDOW_SIZE (1 << IXDP2X01_FLASH_WINDOW_BITS)
49#define IXDP2X01_FLASH_WINDOW_MASK (IXDP2X01_FLASH_WINDOW_SIZE - 1)
50
51#define IXDP2X01_UART_CLK 1843200
52
53#define IXDP2X01_GPIO_I2C_ENABLE 0x02
54#define IXDP2X01_GPIO_SCL 0x07
55#define IXDP2X01_GPIO_SDA 0x06
56
57#endif /* __IXDP2x01_H__ */
diff --git a/arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h b/arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h
deleted file mode 100644
index 822f63f2f4a2..000000000000
--- a/arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h
+++ /dev/null
@@ -1,451 +0,0 @@
1/*
2 * arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h
3 *
4 * Chipset register definitions for IXP2400/2800 based systems.
5 *
6 * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
7 *
8 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
9 *
10 * Copyright (C) 2002 Intel Corp.
11 * Copyright (C) 2003-2004 MontaVista Software, Inc.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 */
18#ifndef _IXP2000_REGS_H_
19#define _IXP2000_REGS_H_
20
21/*
22 * IXP2000 linux memory map:
23 *
24 * virt phys size
25 * fb000000 db000000 16M PCI CFG1
26 * fc000000 da000000 16M PCI CFG0
27 * fd000000 d8000000 16M PCI I/O
28 * fe[0-7]00000 8M per-platform mappings
29 * fe900000 80000000 1M SRAM #0 (first MB)
30 * fea00000 cb400000 1M SCRATCH ring get/put
31 * feb00000 c8000000 1M MSF
32 * fec00000 df000000 1M PCI CSRs
33 * fed00000 de000000 1M PCI CREG
34 * fee00000 d6000000 1M INTCTL
35 * fef00000 c0000000 1M CAP
36 */
37
38/*
39 * Static I/O regions.
40 *
41 * Most of the registers are clumped in 4K regions spread throughout
42 * the 0xc0000000 -> 0xc0100000 address range, but we just map in
43 * the whole range using a single 1 MB section instead of small
44 * 4K pages.
45 *
46 * CAP stands for CSR Access Proxy.
47 *
48 * If you change the virtual address of this mapping, please propagate
49 * the change to arch/arm/kernel/debug.S, which hardcodes the virtual
50 * address of the UART located in this region.
51 */
52
53#define IXP2000_CAP_PHYS_BASE 0xc0000000
54#define IXP2000_CAP_VIRT_BASE 0xfef00000
55#define IXP2000_CAP_SIZE 0x00100000
56
57/*
58 * Addresses for specific on-chip peripherals.
59 */
60#define IXP2000_SLOWPORT_CSR_VIRT_BASE 0xfef80000
61#define IXP2000_GLOBAL_REG_VIRT_BASE 0xfef04000
62#define IXP2000_UART_PHYS_BASE 0xc0030000
63#define IXP2000_UART_VIRT_BASE 0xfef30000
64#define IXP2000_TIMER_VIRT_BASE 0xfef20000
65#define IXP2000_UENGINE_CSR_VIRT_BASE 0xfef18000
66#define IXP2000_GPIO_VIRT_BASE 0xfef10000
67
68/*
69 * Devices outside of the 0xc0000000 -> 0xc0100000 range. The virtual
70 * addresses of the INTCTL and PCI_CSR mappings are hardcoded in
71 * entry-macro.S, so if you ever change these please propagate
72 * the change.
73 */
74#define IXP2000_INTCTL_PHYS_BASE 0xd6000000
75#define IXP2000_INTCTL_VIRT_BASE 0xfee00000
76#define IXP2000_INTCTL_SIZE 0x00100000
77
78#define IXP2000_PCI_CREG_PHYS_BASE 0xde000000
79#define IXP2000_PCI_CREG_VIRT_BASE 0xfed00000
80#define IXP2000_PCI_CREG_SIZE 0x00100000
81
82#define IXP2000_PCI_CSR_PHYS_BASE 0xdf000000
83#define IXP2000_PCI_CSR_VIRT_BASE 0xfec00000
84#define IXP2000_PCI_CSR_SIZE 0x00100000
85
86#define IXP2000_MSF_PHYS_BASE 0xc8000000
87#define IXP2000_MSF_VIRT_BASE 0xfeb00000
88#define IXP2000_MSF_SIZE 0x00100000
89
90#define IXP2000_SCRATCH_RING_PHYS_BASE 0xcb400000
91#define IXP2000_SCRATCH_RING_VIRT_BASE 0xfea00000
92#define IXP2000_SCRATCH_RING_SIZE 0x00100000
93
94#define IXP2000_SRAM0_PHYS_BASE 0x80000000
95#define IXP2000_SRAM0_VIRT_BASE 0xfe900000
96#define IXP2000_SRAM0_SIZE 0x00100000
97
98#define IXP2000_PCI_IO_PHYS_BASE 0xd8000000
99#define IXP2000_PCI_IO_VIRT_BASE 0xfd000000
100#define IXP2000_PCI_IO_SIZE 0x01000000
101
102#define IXP2000_PCI_CFG0_PHYS_BASE 0xda000000
103#define IXP2000_PCI_CFG0_VIRT_BASE 0xfc000000
104#define IXP2000_PCI_CFG0_SIZE 0x01000000
105
106#define IXP2000_PCI_CFG1_PHYS_BASE 0xdb000000
107#define IXP2000_PCI_CFG1_VIRT_BASE 0xfb000000
108#define IXP2000_PCI_CFG1_SIZE 0x01000000
109
110/*
111 * Timers
112 */
113#define IXP2000_TIMER_REG(x) ((volatile unsigned long*)(IXP2000_TIMER_VIRT_BASE | (x)))
114/* Timer control */
115#define IXP2000_T1_CTL IXP2000_TIMER_REG(0x00)
116#define IXP2000_T2_CTL IXP2000_TIMER_REG(0x04)
117#define IXP2000_T3_CTL IXP2000_TIMER_REG(0x08)
118#define IXP2000_T4_CTL IXP2000_TIMER_REG(0x0c)
119/* Store initial value */
120#define IXP2000_T1_CLD IXP2000_TIMER_REG(0x10)
121#define IXP2000_T2_CLD IXP2000_TIMER_REG(0x14)
122#define IXP2000_T3_CLD IXP2000_TIMER_REG(0x18)
123#define IXP2000_T4_CLD IXP2000_TIMER_REG(0x1c)
124/* Read current value */
125#define IXP2000_T1_CSR IXP2000_TIMER_REG(0x20)
126#define IXP2000_T2_CSR IXP2000_TIMER_REG(0x24)
127#define IXP2000_T3_CSR IXP2000_TIMER_REG(0x28)
128#define IXP2000_T4_CSR IXP2000_TIMER_REG(0x2c)
129/* Clear associated timer interrupt */
130#define IXP2000_T1_CLR IXP2000_TIMER_REG(0x30)
131#define IXP2000_T2_CLR IXP2000_TIMER_REG(0x34)
132#define IXP2000_T3_CLR IXP2000_TIMER_REG(0x38)
133#define IXP2000_T4_CLR IXP2000_TIMER_REG(0x3c)
134/* Timer watchdog enable for T4 */
135#define IXP2000_TWDE IXP2000_TIMER_REG(0x40)
136
137#define WDT_ENABLE 0x00000001
138#define TIMER_DIVIDER_256 0x00000008
139#define TIMER_ENABLE 0x00000080
140#define IRQ_MASK_TIMER1 (1 << 4)
141
142/*
143 * Interrupt controller registers
144 */
145#define IXP2000_INTCTL_REG(x) (volatile unsigned long*)(IXP2000_INTCTL_VIRT_BASE | (x))
146#define IXP2000_IRQ_STATUS IXP2000_INTCTL_REG(0x08)
147#define IXP2000_IRQ_ENABLE IXP2000_INTCTL_REG(0x10)
148#define IXP2000_IRQ_ENABLE_SET IXP2000_INTCTL_REG(0x10)
149#define IXP2000_IRQ_ENABLE_CLR IXP2000_INTCTL_REG(0x18)
150#define IXP2000_FIQ_ENABLE_CLR IXP2000_INTCTL_REG(0x14)
151#define IXP2000_IRQ_ERR_STATUS IXP2000_INTCTL_REG(0x24)
152#define IXP2000_IRQ_ERR_ENABLE_SET IXP2000_INTCTL_REG(0x2c)
153#define IXP2000_FIQ_ERR_ENABLE_CLR IXP2000_INTCTL_REG(0x30)
154#define IXP2000_IRQ_ERR_ENABLE_CLR IXP2000_INTCTL_REG(0x34)
155#define IXP2000_IRQ_THD_RAW_STATUS_A_0 IXP2000_INTCTL_REG(0x60)
156#define IXP2000_IRQ_THD_RAW_STATUS_A_1 IXP2000_INTCTL_REG(0x64)
157#define IXP2000_IRQ_THD_RAW_STATUS_A_2 IXP2000_INTCTL_REG(0x68)
158#define IXP2000_IRQ_THD_RAW_STATUS_A_3 IXP2000_INTCTL_REG(0x6c)
159#define IXP2000_IRQ_THD_RAW_STATUS_B_0 IXP2000_INTCTL_REG(0x80)
160#define IXP2000_IRQ_THD_RAW_STATUS_B_1 IXP2000_INTCTL_REG(0x84)
161#define IXP2000_IRQ_THD_RAW_STATUS_B_2 IXP2000_INTCTL_REG(0x88)
162#define IXP2000_IRQ_THD_RAW_STATUS_B_3 IXP2000_INTCTL_REG(0x8c)
163#define IXP2000_IRQ_THD_STATUS_A_0 IXP2000_INTCTL_REG(0xe0)
164#define IXP2000_IRQ_THD_STATUS_A_1 IXP2000_INTCTL_REG(0xe4)
165#define IXP2000_IRQ_THD_STATUS_A_2 IXP2000_INTCTL_REG(0xe8)
166#define IXP2000_IRQ_THD_STATUS_A_3 IXP2000_INTCTL_REG(0xec)
167#define IXP2000_IRQ_THD_STATUS_B_0 IXP2000_INTCTL_REG(0x100)
168#define IXP2000_IRQ_THD_STATUS_B_1 IXP2000_INTCTL_REG(0x104)
169#define IXP2000_IRQ_THD_STATUS_B_2 IXP2000_INTCTL_REG(0x108)
170#define IXP2000_IRQ_THD_STATUS_B_3 IXP2000_INTCTL_REG(0x10c)
171#define IXP2000_IRQ_THD_ENABLE_SET_A_0 IXP2000_INTCTL_REG(0x160)
172#define IXP2000_IRQ_THD_ENABLE_SET_A_1 IXP2000_INTCTL_REG(0x164)
173#define IXP2000_IRQ_THD_ENABLE_SET_A_2 IXP2000_INTCTL_REG(0x168)
174#define IXP2000_IRQ_THD_ENABLE_SET_A_3 IXP2000_INTCTL_REG(0x16c)
175#define IXP2000_IRQ_THD_ENABLE_SET_B_0 IXP2000_INTCTL_REG(0x180)
176#define IXP2000_IRQ_THD_ENABLE_SET_B_1 IXP2000_INTCTL_REG(0x184)
177#define IXP2000_IRQ_THD_ENABLE_SET_B_2 IXP2000_INTCTL_REG(0x188)
178#define IXP2000_IRQ_THD_ENABLE_SET_B_3 IXP2000_INTCTL_REG(0x18c)
179#define IXP2000_IRQ_THD_ENABLE_CLEAR_A_0 IXP2000_INTCTL_REG(0x1e0)
180#define IXP2000_IRQ_THD_ENABLE_CLEAR_A_1 IXP2000_INTCTL_REG(0x1e4)
181#define IXP2000_IRQ_THD_ENABLE_CLEAR_A_2 IXP2000_INTCTL_REG(0x1e8)
182#define IXP2000_IRQ_THD_ENABLE_CLEAR_A_3 IXP2000_INTCTL_REG(0x1ec)
183#define IXP2000_IRQ_THD_ENABLE_CLEAR_B_0 IXP2000_INTCTL_REG(0x200)
184#define IXP2000_IRQ_THD_ENABLE_CLEAR_B_1 IXP2000_INTCTL_REG(0x204)
185#define IXP2000_IRQ_THD_ENABLE_CLEAR_B_2 IXP2000_INTCTL_REG(0x208)
186#define IXP2000_IRQ_THD_ENABLE_CLEAR_B_3 IXP2000_INTCTL_REG(0x20c)
187
188/*
189 * Mask of valid IRQs in the 32-bit IRQ register. We use
190 * this to mark certain IRQs as being invalid.
191 */
192#define IXP2000_VALID_IRQ_MASK 0x0f0fffff
193
194/*
195 * PCI config register access from core
196 */
197#define IXP2000_PCI_CREG(x) (volatile unsigned long*)(IXP2000_PCI_CREG_VIRT_BASE | (x))
198#define IXP2000_PCI_CMDSTAT IXP2000_PCI_CREG(0x04)
199#define IXP2000_PCI_CSR_BAR IXP2000_PCI_CREG(0x10)
200#define IXP2000_PCI_SRAM_BAR IXP2000_PCI_CREG(0x14)
201#define IXP2000_PCI_SDRAM_BAR IXP2000_PCI_CREG(0x18)
202
203/*
204 * PCI CSRs
205 */
206#define IXP2000_PCI_CSR(x) (volatile unsigned long*)(IXP2000_PCI_CSR_VIRT_BASE | (x))
207
208/*
209 * PCI outbound interrupts
210 */
211#define IXP2000_PCI_OUT_INT_STATUS IXP2000_PCI_CSR(0x30)
212#define IXP2000_PCI_OUT_INT_MASK IXP2000_PCI_CSR(0x34)
213/*
214 * PCI communications
215 */
216#define IXP2000_PCI_MAILBOX0 IXP2000_PCI_CSR(0x50)
217#define IXP2000_PCI_MAILBOX1 IXP2000_PCI_CSR(0x54)
218#define IXP2000_PCI_MAILBOX2 IXP2000_PCI_CSR(0x58)
219#define IXP2000_PCI_MAILBOX3 IXP2000_PCI_CSR(0x5C)
220#define IXP2000_XSCALE_DOORBELL IXP2000_PCI_CSR(0x60)
221#define IXP2000_XSCALE_DOORBELL_SETUP IXP2000_PCI_CSR(0x64)
222#define IXP2000_PCI_DOORBELL IXP2000_PCI_CSR(0x70)
223#define IXP2000_PCI_DOORBELL_SETUP IXP2000_PCI_CSR(0x74)
224
225/*
226 * DMA engines
227 */
228#define IXP2000_PCI_CH1_BYTE_CNT IXP2000_PCI_CSR(0x80)
229#define IXP2000_PCI_CH1_ADDR IXP2000_PCI_CSR(0x84)
230#define IXP2000_PCI_CH1_DRAM_ADDR IXP2000_PCI_CSR(0x88)
231#define IXP2000_PCI_CH1_DESC_PTR IXP2000_PCI_CSR(0x8C)
232#define IXP2000_PCI_CH1_CNTRL IXP2000_PCI_CSR(0x90)
233#define IXP2000_PCI_CH1_ME_PARAM IXP2000_PCI_CSR(0x94)
234#define IXP2000_PCI_CH2_BYTE_CNT IXP2000_PCI_CSR(0xA0)
235#define IXP2000_PCI_CH2_ADDR IXP2000_PCI_CSR(0xA4)
236#define IXP2000_PCI_CH2_DRAM_ADDR IXP2000_PCI_CSR(0xA8)
237#define IXP2000_PCI_CH2_DESC_PTR IXP2000_PCI_CSR(0xAC)
238#define IXP2000_PCI_CH2_CNTRL IXP2000_PCI_CSR(0xB0)
239#define IXP2000_PCI_CH2_ME_PARAM IXP2000_PCI_CSR(0xB4)
240#define IXP2000_PCI_CH3_BYTE_CNT IXP2000_PCI_CSR(0xC0)
241#define IXP2000_PCI_CH3_ADDR IXP2000_PCI_CSR(0xC4)
242#define IXP2000_PCI_CH3_DRAM_ADDR IXP2000_PCI_CSR(0xC8)
243#define IXP2000_PCI_CH3_DESC_PTR IXP2000_PCI_CSR(0xCC)
244#define IXP2000_PCI_CH3_CNTRL IXP2000_PCI_CSR(0xD0)
245#define IXP2000_PCI_CH3_ME_PARAM IXP2000_PCI_CSR(0xD4)
246#define IXP2000_DMA_INF_MODE IXP2000_PCI_CSR(0xE0)
247/*
248 * Size masks for BARs
249 */
250#define IXP2000_PCI_SRAM_BASE_ADDR_MASK IXP2000_PCI_CSR(0xFC)
251#define IXP2000_PCI_DRAM_BASE_ADDR_MASK IXP2000_PCI_CSR(0x100)
252/*
253 * Control and uEngine related
254 */
255#define IXP2000_PCI_CONTROL IXP2000_PCI_CSR(0x13C)
256#define IXP2000_PCI_ADDR_EXT IXP2000_PCI_CSR(0x140)
257#define IXP2000_PCI_ME_PUSH_STATUS IXP2000_PCI_CSR(0x148)
258#define IXP2000_PCI_ME_PUSH_EN IXP2000_PCI_CSR(0x14C)
259#define IXP2000_PCI_ERR_STATUS IXP2000_PCI_CSR(0x150)
260#define IXP2000_PCI_ERR_ENABLE IXP2000_PCI_CSR(0x154)
261/*
262 * Inbound PCI interrupt control
263 */
264#define IXP2000_PCI_XSCALE_INT_STATUS IXP2000_PCI_CSR(0x158)
265#define IXP2000_PCI_XSCALE_INT_ENABLE IXP2000_PCI_CSR(0x15C)
266
267#define IXP2000_PCICNTL_PNR (1<<17) /* PCI not Reset bit of PCI_CONTROL */
268#define IXP2000_PCICNTL_PCF (1<<28) /* PCI Central function bit */
269#define IXP2000_XSCALE_INT (1<<1) /* Interrupt from XScale to PCI */
270
271/* These are from the IRQ register in the PCI ISR register */
272#define PCI_CONTROL_BE_DEO (1 << 22) /* Big Endian Data Enable Out */
273#define PCI_CONTROL_BE_DEI (1 << 21) /* Big Endian Data Enable In */
274#define PCI_CONTROL_BE_BEO (1 << 20) /* Big Endian Byte Enable Out */
275#define PCI_CONTROL_BE_BEI (1 << 19) /* Big Endian Byte Enable In */
276#define PCI_CONTROL_IEE (1 << 17) /* I/O cycle Endian swap Enable */
277
278#define IXP2000_PCI_RST_REL (1 << 2)
279#define CFG_RST_DIR (*IXP2000_PCI_CONTROL & IXP2000_PCICNTL_PCF)
280#define CFG_PCI_BOOT_HOST (1 << 2)
281#define CFG_BOOT_PROM (1 << 1)
282
283/*
284 * SlowPort CSRs
285 *
286 * The slowport is used to access things like flash, SONET framer control
287 * ports, slave microprocessors, CPLDs, and others of chip memory mapped
288 * peripherals.
289 */
290#define SLOWPORT_CSR(x) (volatile unsigned long*)(IXP2000_SLOWPORT_CSR_VIRT_BASE | (x))
291
292#define IXP2000_SLOWPORT_CCR SLOWPORT_CSR(0x00)
293#define IXP2000_SLOWPORT_WTC1 SLOWPORT_CSR(0x04)
294#define IXP2000_SLOWPORT_WTC2 SLOWPORT_CSR(0x08)
295#define IXP2000_SLOWPORT_RTC1 SLOWPORT_CSR(0x0c)
296#define IXP2000_SLOWPORT_RTC2 SLOWPORT_CSR(0x10)
297#define IXP2000_SLOWPORT_FSR SLOWPORT_CSR(0x14)
298#define IXP2000_SLOWPORT_PCR SLOWPORT_CSR(0x18)
299#define IXP2000_SLOWPORT_ADC SLOWPORT_CSR(0x1C)
300#define IXP2000_SLOWPORT_FAC SLOWPORT_CSR(0x20)
301#define IXP2000_SLOWPORT_FRM SLOWPORT_CSR(0x24)
302#define IXP2000_SLOWPORT_FIN SLOWPORT_CSR(0x28)
303
304/*
305 * CCR values.
306 * The CCR configures the clock division for the slowport interface.
307 */
308#define SLOWPORT_CCR_DIV_1 0x00
309#define SLOWPORT_CCR_DIV_2 0x01
310#define SLOWPORT_CCR_DIV_4 0x02
311#define SLOWPORT_CCR_DIV_6 0x03
312#define SLOWPORT_CCR_DIV_8 0x04
313#define SLOWPORT_CCR_DIV_10 0x05
314#define SLOWPORT_CCR_DIV_12 0x06
315#define SLOWPORT_CCR_DIV_14 0x07
316#define SLOWPORT_CCR_DIV_16 0x08
317#define SLOWPORT_CCR_DIV_18 0x09
318#define SLOWPORT_CCR_DIV_20 0x0a
319#define SLOWPORT_CCR_DIV_22 0x0b
320#define SLOWPORT_CCR_DIV_24 0x0c
321#define SLOWPORT_CCR_DIV_26 0x0d
322#define SLOWPORT_CCR_DIV_28 0x0e
323#define SLOWPORT_CCR_DIV_30 0x0f
324
325/*
326 * PCR values. PCR configure the mode of the interface.
327 */
328#define SLOWPORT_MODE_FLASH 0x00
329#define SLOWPORT_MODE_LUCENT 0x01
330#define SLOWPORT_MODE_PMC_SIERRA 0x02
331#define SLOWPORT_MODE_INTEL_UP 0x03
332#define SLOWPORT_MODE_MOTOROLA_UP 0x04
333
334/*
335 * ADC values. Defines data and address bus widths.
336 */
337#define SLOWPORT_ADDR_WIDTH_8 0x00
338#define SLOWPORT_ADDR_WIDTH_16 0x01
339#define SLOWPORT_ADDR_WIDTH_24 0x02
340#define SLOWPORT_ADDR_WIDTH_32 0x03
341#define SLOWPORT_DATA_WIDTH_8 0x00
342#define SLOWPORT_DATA_WIDTH_16 0x10
343#define SLOWPORT_DATA_WIDTH_24 0x20
344#define SLOWPORT_DATA_WIDTH_32 0x30
345
346/*
347 * Masks and shifts for various fields in the WTC and RTC registers.
348 */
349#define SLOWPORT_WRTC_MASK_HD 0x0003
350#define SLOWPORT_WRTC_MASK_PW 0x003c
351#define SLOWPORT_WRTC_MASK_SU 0x03c0
352
353#define SLOWPORT_WRTC_SHIFT_HD 0x00
354#define SLOWPORT_WRTC_SHIFT_SU 0x02
355#define SLOWPORT_WRTC_SHFIT_PW 0x06
356
357
358/*
359 * GPIO registers & GPIO interface.
360 */
361#define IXP2000_GPIO_REG(x) ((volatile unsigned long*)(IXP2000_GPIO_VIRT_BASE+(x)))
362#define IXP2000_GPIO_PLR IXP2000_GPIO_REG(0x00)
363#define IXP2000_GPIO_PDPR IXP2000_GPIO_REG(0x04)
364#define IXP2000_GPIO_PDSR IXP2000_GPIO_REG(0x08)
365#define IXP2000_GPIO_PDCR IXP2000_GPIO_REG(0x0c)
366#define IXP2000_GPIO_POPR IXP2000_GPIO_REG(0x10)
367#define IXP2000_GPIO_POSR IXP2000_GPIO_REG(0x14)
368#define IXP2000_GPIO_POCR IXP2000_GPIO_REG(0x18)
369#define IXP2000_GPIO_REDR IXP2000_GPIO_REG(0x1c)
370#define IXP2000_GPIO_FEDR IXP2000_GPIO_REG(0x20)
371#define IXP2000_GPIO_EDSR IXP2000_GPIO_REG(0x24)
372#define IXP2000_GPIO_LSHR IXP2000_GPIO_REG(0x28)
373#define IXP2000_GPIO_LSLR IXP2000_GPIO_REG(0x2c)
374#define IXP2000_GPIO_LDSR IXP2000_GPIO_REG(0x30)
375#define IXP2000_GPIO_INER IXP2000_GPIO_REG(0x34)
376#define IXP2000_GPIO_INSR IXP2000_GPIO_REG(0x38)
377#define IXP2000_GPIO_INCR IXP2000_GPIO_REG(0x3c)
378#define IXP2000_GPIO_INST IXP2000_GPIO_REG(0x40)
379
380/*
381 * "Global" registers...whatever that's supposed to mean.
382 */
383#define GLOBAL_REG_BASE (IXP2000_GLOBAL_REG_VIRT_BASE + 0x0a00)
384#define GLOBAL_REG(x) (volatile unsigned long*)(GLOBAL_REG_BASE | (x))
385
386#define IXP2000_MAJ_PROD_TYPE_MASK 0x001F0000
387#define IXP2000_MAJ_PROD_TYPE_IXP2000 0x00000000
388#define IXP2000_MIN_PROD_TYPE_MASK 0x0000FF00
389#define IXP2000_MIN_PROD_TYPE_IXP2400 0x00000200
390#define IXP2000_MIN_PROD_TYPE_IXP2850 0x00000100
391#define IXP2000_MIN_PROD_TYPE_IXP2800 0x00000000
392#define IXP2000_MAJ_REV_MASK 0x000000F0
393#define IXP2000_MIN_REV_MASK 0x0000000F
394#define IXP2000_PROD_ID_MASK 0xFFFFFFFF
395
396#define IXP2000_PRODUCT_ID GLOBAL_REG(0x00)
397#define IXP2000_MISC_CONTROL GLOBAL_REG(0x04)
398#define IXP2000_MSF_CLK_CNTRL GLOBAL_REG(0x08)
399#define IXP2000_RESET0 GLOBAL_REG(0x0c)
400#define IXP2000_RESET1 GLOBAL_REG(0x10)
401#define IXP2000_CCR GLOBAL_REG(0x14)
402#define IXP2000_STRAP_OPTIONS GLOBAL_REG(0x18)
403
404#define RSTALL (1 << 16)
405#define WDT_RESET_ENABLE 0x01000000
406
407
408/*
409 * MSF registers. The IXP2400 and IXP2800 have somewhat different MSF
410 * units, but the registers that differ between the two don't overlap,
411 * so we can have one register list for both.
412 */
413#define IXP2000_MSF_REG(x) ((volatile unsigned long*)(IXP2000_MSF_VIRT_BASE + (x)))
414#define IXP2000_MSF_RX_CONTROL IXP2000_MSF_REG(0x0000)
415#define IXP2000_MSF_TX_CONTROL IXP2000_MSF_REG(0x0004)
416#define IXP2000_MSF_INTERRUPT_STATUS IXP2000_MSF_REG(0x0008)
417#define IXP2000_MSF_INTERRUPT_ENABLE IXP2000_MSF_REG(0x000c)
418#define IXP2000_MSF_CSIX_TYPE_MAP IXP2000_MSF_REG(0x0010)
419#define IXP2000_MSF_FC_EGRESS_STATUS IXP2000_MSF_REG(0x0014)
420#define IXP2000_MSF_FC_INGRESS_STATUS IXP2000_MSF_REG(0x0018)
421#define IXP2000_MSF_HWM_CONTROL IXP2000_MSF_REG(0x0024)
422#define IXP2000_MSF_FC_STATUS_OVERRIDE IXP2000_MSF_REG(0x0028)
423#define IXP2000_MSF_CLOCK_CONTROL IXP2000_MSF_REG(0x002c)
424#define IXP2000_MSF_RX_PORT_MAP IXP2000_MSF_REG(0x0040)
425#define IXP2000_MSF_RBUF_ELEMENT_DONE IXP2000_MSF_REG(0x0044)
426#define IXP2000_MSF_RX_MPHY_POLL_LIMIT IXP2000_MSF_REG(0x0048)
427#define IXP2000_MSF_RX_CALENDAR_LENGTH IXP2000_MSF_REG(0x0048)
428#define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_0 IXP2000_MSF_REG(0x0050)
429#define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_1 IXP2000_MSF_REG(0x0054)
430#define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_2 IXP2000_MSF_REG(0x0058)
431#define IXP2000_MSF_TX_SEQUENCE_0 IXP2000_MSF_REG(0x0060)
432#define IXP2000_MSF_TX_SEQUENCE_1 IXP2000_MSF_REG(0x0064)
433#define IXP2000_MSF_TX_SEQUENCE_2 IXP2000_MSF_REG(0x0068)
434#define IXP2000_MSF_TX_MPHY_POLL_LIMIT IXP2000_MSF_REG(0x0070)
435#define IXP2000_MSF_TX_CALENDAR_LENGTH IXP2000_MSF_REG(0x0070)
436#define IXP2000_MSF_RX_UP_CONTROL_0 IXP2000_MSF_REG(0x0080)
437#define IXP2000_MSF_RX_UP_CONTROL_1 IXP2000_MSF_REG(0x0084)
438#define IXP2000_MSF_RX_UP_CONTROL_2 IXP2000_MSF_REG(0x0088)
439#define IXP2000_MSF_RX_UP_CONTROL_3 IXP2000_MSF_REG(0x008c)
440#define IXP2000_MSF_TX_UP_CONTROL_0 IXP2000_MSF_REG(0x0090)
441#define IXP2000_MSF_TX_UP_CONTROL_1 IXP2000_MSF_REG(0x0094)
442#define IXP2000_MSF_TX_UP_CONTROL_2 IXP2000_MSF_REG(0x0098)
443#define IXP2000_MSF_TX_UP_CONTROL_3 IXP2000_MSF_REG(0x009c)
444#define IXP2000_MSF_TRAIN_DATA IXP2000_MSF_REG(0x00a0)
445#define IXP2000_MSF_TRAIN_CALENDAR IXP2000_MSF_REG(0x00a4)
446#define IXP2000_MSF_TRAIN_FLOW_CONTROL IXP2000_MSF_REG(0x00a8)
447#define IXP2000_MSF_TX_CALENDAR_0 IXP2000_MSF_REG(0x1000)
448#define IXP2000_MSF_RX_PORT_CALENDAR_STATUS IXP2000_MSF_REG(0x1400)
449
450
451#endif /* _IXP2000_H_ */
diff --git a/arch/arm/mach-ixp2000/include/mach/memory.h b/arch/arm/mach-ixp2000/include/mach/memory.h
deleted file mode 100644
index 5f0c4fd4076a..000000000000
--- a/arch/arm/mach-ixp2000/include/mach/memory.h
+++ /dev/null
@@ -1,31 +0,0 @@
1/*
2 * arch/arm/mach-ixp2000/include/mach/memory.h
3 *
4 * Copyright (c) 2002 Intel Corp.
5 * Copyright (c) 2003-2004 MontaVista Software, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#ifndef __ASM_ARCH_MEMORY_H
14#define __ASM_ARCH_MEMORY_H
15
16#define PLAT_PHYS_OFFSET UL(0x00000000)
17
18#include <mach/ixp2000-regs.h>
19
20#define IXP2000_PCI_SDRAM_OFFSET (*IXP2000_PCI_SDRAM_BAR & 0xfffffff0)
21
22#define __phys_to_bus(x) ((x) + (IXP2000_PCI_SDRAM_OFFSET - PHYS_OFFSET))
23#define __bus_to_phys(x) ((x) - (IXP2000_PCI_SDRAM_OFFSET - PHYS_OFFSET))
24
25#define __virt_to_bus(v) __phys_to_bus(__virt_to_phys(v))
26#define __bus_to_virt(b) __phys_to_virt(__bus_to_phys(b))
27#define __pfn_to_bus(p) __phys_to_bus(__pfn_to_phys(p))
28#define __bus_to_pfn(b) __phys_to_pfn(__bus_to_phys(b))
29
30#endif
31
diff --git a/arch/arm/mach-ixp2000/include/mach/platform.h b/arch/arm/mach-ixp2000/include/mach/platform.h
deleted file mode 100644
index bb0f8dcf9ee1..000000000000
--- a/arch/arm/mach-ixp2000/include/mach/platform.h
+++ /dev/null
@@ -1,153 +0,0 @@
1/*
2 * arch/arm/mach-ixp2000/include/mach/platform.h
3 *
4 * Various bits of code used by platform-level code.
5 *
6 * Author: Deepak Saxena <dsaxena@plexity.net>
7 *
8 * Copyright 2004 (c) MontaVista Software, Inc.
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15
16#ifndef __ASSEMBLY__
17
18static inline unsigned long ixp2000_reg_read(volatile void *reg)
19{
20 return *((volatile unsigned long *)reg);
21}
22
23static inline void ixp2000_reg_write(volatile void *reg, unsigned long val)
24{
25 *((volatile unsigned long *)reg) = val;
26}
27
28/*
29 * On the IXP2400, we can't use XCB=000 due to chip bugs. We use
30 * XCB=101 instead, but that makes all I/O accesses bufferable. This
31 * is not a problem in general, but we do have to be slightly more
32 * careful because I/O writes are no longer automatically flushed out
33 * of the write buffer.
34 *
35 * In cases where we want to make sure that a write has been flushed
36 * out of the write buffer before we proceed, for example when masking
37 * a device interrupt before re-enabling IRQs in CPSR, we can use this
38 * function, ixp2000_reg_wrb, which performs a write, a readback, and
39 * issues a dummy instruction dependent on the value of the readback
40 * (mov rX, rX) to make sure that the readback has completed before we
41 * continue.
42 */
43static inline void ixp2000_reg_wrb(volatile void *reg, unsigned long val)
44{
45 unsigned long dummy;
46
47 *((volatile unsigned long *)reg) = val;
48
49 dummy = *((volatile unsigned long *)reg);
50 __asm__ __volatile__("mov %0, %0" : "+r" (dummy));
51}
52
53/*
54 * Boards may multiplex different devices on the 2nd channel of
55 * the slowport interface that each need different configuration
56 * settings. For example, the IXDP2400 uses channel 2 on the interface
57 * to access the CPLD, the switch fabric card, and the media card. Each
58 * one needs a different mode so drivers must save/restore the mode
59 * before and after each operation.
60 *
61 * acquire_slowport(&your_config);
62 * ...
63 * do slowport operations
64 * ...
65 * release_slowport();
66 *
67 * Note that while you have the slowport, you are holding a spinlock,
68 * so your code should be written as if you explicitly acquired a lock.
69 *
70 * The configuration only affects device 2 on the slowport, so the
71 * MTD map driver does not acquire/release the slowport.
72 */
73struct slowport_cfg {
74 unsigned long CCR; /* Clock divide */
75 unsigned long WTC; /* Write Timing Control */
76 unsigned long RTC; /* Read Timing Control */
77 unsigned long PCR; /* Protocol Control Register */
78 unsigned long ADC; /* Address/Data Width Control */
79};
80
81
82void ixp2000_acquire_slowport(struct slowport_cfg *, struct slowport_cfg *);
83void ixp2000_release_slowport(struct slowport_cfg *);
84
85/*
86 * IXP2400 A0/A1 and IXP2800 A0/A1/A2 have broken slowport that requires
87 * tweaking of addresses in the MTD driver.
88 */
89static inline unsigned ixp2000_has_broken_slowport(void)
90{
91 unsigned long id = *IXP2000_PRODUCT_ID;
92 unsigned long id_prod = id & (IXP2000_MAJ_PROD_TYPE_MASK |
93 IXP2000_MIN_PROD_TYPE_MASK);
94 return (((id_prod ==
95 /* fixed in IXP2400-B0 */
96 (IXP2000_MAJ_PROD_TYPE_IXP2000 |
97 IXP2000_MIN_PROD_TYPE_IXP2400)) &&
98 ((id & IXP2000_MAJ_REV_MASK) == 0)) ||
99 ((id_prod ==
100 /* fixed in IXP2800-B0 */
101 (IXP2000_MAJ_PROD_TYPE_IXP2000 |
102 IXP2000_MIN_PROD_TYPE_IXP2800)) &&
103 ((id & IXP2000_MAJ_REV_MASK) == 0)) ||
104 ((id_prod ==
105 /* fixed in IXP2850-B0 */
106 (IXP2000_MAJ_PROD_TYPE_IXP2000 |
107 IXP2000_MIN_PROD_TYPE_IXP2850)) &&
108 ((id & IXP2000_MAJ_REV_MASK) == 0)));
109}
110
111static inline unsigned int ixp2000_has_flash(void)
112{
113 return ((*IXP2000_STRAP_OPTIONS) & (CFG_BOOT_PROM));
114}
115
116static inline unsigned int ixp2000_is_pcimaster(void)
117{
118 return ((*IXP2000_STRAP_OPTIONS) & (CFG_PCI_BOOT_HOST));
119}
120
121void ixp2000_map_io(void);
122void ixp2000_uart_init(void);
123void ixp2000_init_irq(void);
124void ixp2000_init_time(unsigned long);
125void ixp2000_restart(char, const char *);
126unsigned long ixp2000_gettimeoffset(void);
127
128struct pci_sys_data;
129
130u32 *ixp2000_pci_config_addr(unsigned int bus, unsigned int devfn, int where);
131void ixp2000_pci_preinit(void);
132int ixp2000_pci_setup(int, struct pci_sys_data*);
133struct pci_bus* ixp2000_pci_scan_bus(int, struct pci_sys_data*);
134int ixp2000_pci_read_config(struct pci_bus*, unsigned int, int, int, u32 *);
135int ixp2000_pci_write_config(struct pci_bus*, unsigned int, int, int, u32);
136
137/*
138 * Several of the IXP2000 systems have banked flash so we need to extend the
139 * flash_platform_data structure with some private pointers
140 */
141struct ixp2000_flash_data {
142 struct flash_platform_data *platform_data;
143 int nr_banks;
144 unsigned long (*bank_setup)(unsigned long);
145};
146
147struct ixp2000_i2c_pins {
148 unsigned long sda_pin;
149 unsigned long scl_pin;
150};
151
152
153#endif /* !__ASSEMBLY__ */
diff --git a/arch/arm/mach-ixp2000/include/mach/timex.h b/arch/arm/mach-ixp2000/include/mach/timex.h
deleted file mode 100644
index 835e659f93d4..000000000000
--- a/arch/arm/mach-ixp2000/include/mach/timex.h
+++ /dev/null
@@ -1,13 +0,0 @@
1/*
2 * arch/arm/mach-ixp2000/include/mach/timex.h
3 *
4 * IXP2000 architecture timex specifications
5 */
6
7
8/*
9 * Default clock is 50MHz APB, but platform code can override this
10 */
11#define CLOCK_TICK_RATE 50000000
12
13
diff --git a/arch/arm/mach-ixp2000/include/mach/uncompress.h b/arch/arm/mach-ixp2000/include/mach/uncompress.h
deleted file mode 100644
index ce363087df78..000000000000
--- a/arch/arm/mach-ixp2000/include/mach/uncompress.h
+++ /dev/null
@@ -1,47 +0,0 @@
1/*
2 * arch/arm/mach-ixp2000/include/mach/uncompress.h
3 *
4 *
5 * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
6 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
7 *
8 * Copyright 2002 Intel Corp.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 */
16
17#include <linux/serial_reg.h>
18
19#define UART_BASE 0xc0030000
20
21#define PHYS(x) ((volatile unsigned long *)(UART_BASE + x))
22
23#define UARTDR PHYS(0x00) /* Transmit reg dlab=0 */
24#define UARTDLL PHYS(0x00) /* Divisor Latch reg dlab=1*/
25#define UARTDLM PHYS(0x04) /* Divisor Latch reg dlab=1*/
26#define UARTIER PHYS(0x04) /* Interrupt enable reg */
27#define UARTFCR PHYS(0x08) /* FIFO control reg dlab =0*/
28#define UARTLCR PHYS(0x0c) /* Control reg */
29#define UARTSR PHYS(0x14) /* Status reg */
30
31
32static inline void putc(int c)
33{
34 int j = 0x1000;
35
36 while (--j && !(*UARTSR & UART_LSR_THRE))
37 barrier();
38
39 *UARTDR = c;
40}
41
42static inline void flush(void)
43{
44}
45
46#define arch_decomp_setup()
47#define arch_decomp_wdog()
diff --git a/arch/arm/mach-ixp2000/ixdp2400.c b/arch/arm/mach-ixp2000/ixdp2400.c
deleted file mode 100644
index 915ad49e3b8f..000000000000
--- a/arch/arm/mach-ixp2000/ixdp2400.c
+++ /dev/null
@@ -1,180 +0,0 @@
1/*
2 * arch/arm/mach-ixp2000/ixdp2400.c
3 *
4 * IXDP2400 platform support
5 *
6 * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
7 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
8 *
9 * Copyright (C) 2002 Intel Corp.
10 * Copyright (C) 2003-2004 MontaVista Software, Inc.
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/mm.h>
20#include <linux/sched.h>
21#include <linux/interrupt.h>
22#include <linux/device.h>
23#include <linux/bitops.h>
24#include <linux/pci.h>
25#include <linux/ioport.h>
26#include <linux/delay.h>
27#include <linux/io.h>
28
29#include <asm/irq.h>
30#include <asm/pgtable.h>
31#include <asm/page.h>
32#include <mach/hardware.h>
33#include <asm/mach-types.h>
34
35#include <asm/mach/pci.h>
36#include <asm/mach/map.h>
37#include <asm/mach/irq.h>
38#include <asm/mach/time.h>
39#include <asm/mach/flash.h>
40#include <asm/mach/arch.h>
41
42/*************************************************************************
43 * IXDP2400 timer tick
44 *************************************************************************/
45static void __init ixdp2400_timer_init(void)
46{
47 int numerator, denominator;
48 int denom_array[] = {2, 4, 8, 16, 1, 2, 4, 8};
49
50 numerator = (*(IXDP2400_CPLD_SYS_CLK_M) & 0xFF) *2;
51 denominator = denom_array[(*(IXDP2400_CPLD_SYS_CLK_N) & 0x7)];
52
53 ixp2000_init_time(((3125000 * numerator) / (denominator)) / 2);
54}
55
56static struct sys_timer ixdp2400_timer = {
57 .init = ixdp2400_timer_init,
58 .offset = ixp2000_gettimeoffset,
59};
60
61/*************************************************************************
62 * IXDP2400 PCI
63 *************************************************************************/
64void __init ixdp2400_pci_preinit(void)
65{
66 ixp2000_reg_write(IXP2000_PCI_ADDR_EXT, 0x00100000);
67 ixp2000_pci_preinit();
68 pcibios_setup("firmware");
69}
70
71int ixdp2400_pci_setup(int nr, struct pci_sys_data *sys)
72{
73 sys->mem_offset = 0xe0000000;
74
75 ixp2000_pci_setup(nr, sys);
76
77 return 1;
78}
79
80static int __init ixdp2400_pci_map_irq(const struct pci_dev *dev, u8 slot,
81 u8 pin)
82{
83 if (ixdp2x00_master_npu()) {
84
85 /*
86 * Root bus devices. Slave NPU is only one with interrupt.
87 * Everything else, we just return -1 b/c nothing else
88 * on the root bus has interrupts.
89 */
90 if(!dev->bus->self) {
91 if(dev->devfn == IXDP2X00_SLAVE_NPU_DEVFN )
92 return IRQ_IXDP2400_INGRESS_NPU;
93
94 return -1;
95 }
96
97 /*
98 * Bridge behind the PMC slot.
99 * NOTE: Only INTA from the PMC slot is routed. VERY BAD.
100 */
101 if(dev->bus->self->devfn == IXDP2X00_PMC_DEVFN &&
102 dev->bus->parent->self->devfn == IXDP2X00_P2P_DEVFN &&
103 !dev->bus->parent->self->bus->parent)
104 return IRQ_IXDP2400_PMC;
105
106 /*
107 * Device behind the first bridge
108 */
109 if(dev->bus->self->devfn == IXDP2X00_P2P_DEVFN) {
110 switch(dev->devfn) {
111 case IXDP2400_MASTER_ENET_DEVFN:
112 return IRQ_IXDP2400_ENET;
113
114 case IXDP2400_MEDIA_DEVFN:
115 return IRQ_IXDP2400_MEDIA_PCI;
116
117 case IXDP2400_SWITCH_FABRIC_DEVFN:
118 return IRQ_IXDP2400_SF_PCI;
119
120 case IXDP2X00_PMC_DEVFN:
121 return IRQ_IXDP2400_PMC;
122 }
123 }
124
125 return -1;
126 } else return IRQ_IXP2000_PCIB; /* Slave NIC interrupt */
127}
128
129
130static void ixdp2400_pci_postinit(void)
131{
132 struct pci_dev *dev;
133
134 if (ixdp2x00_master_npu()) {
135 dev = pci_get_bus_and_slot(1, IXDP2400_SLAVE_ENET_DEVFN);
136 pci_stop_and_remove_bus_device(dev);
137 pci_dev_put(dev);
138 } else {
139 dev = pci_get_bus_and_slot(1, IXDP2400_MASTER_ENET_DEVFN);
140 pci_stop_and_remove_bus_device(dev);
141 pci_dev_put(dev);
142
143 ixdp2x00_slave_pci_postinit();
144 }
145}
146
147static struct hw_pci ixdp2400_pci __initdata = {
148 .nr_controllers = 1,
149 .setup = ixdp2400_pci_setup,
150 .preinit = ixdp2400_pci_preinit,
151 .postinit = ixdp2400_pci_postinit,
152 .scan = ixp2000_pci_scan_bus,
153 .map_irq = ixdp2400_pci_map_irq,
154};
155
156int __init ixdp2400_pci_init(void)
157{
158 if (machine_is_ixdp2400())
159 pci_common_init(&ixdp2400_pci);
160
161 return 0;
162}
163
164subsys_initcall(ixdp2400_pci_init);
165
166void __init ixdp2400_init_irq(void)
167{
168 ixdp2x00_init_irq(IXDP2400_CPLD_INT_STAT, IXDP2400_CPLD_INT_MASK, IXDP2400_NR_IRQS);
169}
170
171MACHINE_START(IXDP2400, "Intel IXDP2400 Development Platform")
172 /* Maintainer: MontaVista Software, Inc. */
173 .atag_offset = 0x100,
174 .map_io = ixdp2x00_map_io,
175 .init_irq = ixdp2400_init_irq,
176 .timer = &ixdp2400_timer,
177 .init_machine = ixdp2x00_init_machine,
178 .restart = ixp2000_restart,
179MACHINE_END
180
diff --git a/arch/arm/mach-ixp2000/ixdp2800.c b/arch/arm/mach-ixp2000/ixdp2800.c
deleted file mode 100644
index a9f1819ea049..000000000000
--- a/arch/arm/mach-ixp2000/ixdp2800.c
+++ /dev/null
@@ -1,295 +0,0 @@
1/*
2 * arch/arm/mach-ixp2000/ixdp2800.c
3 *
4 * IXDP2800 platform support
5 *
6 * Original Author: Jeffrey Daly <jeffrey.daly@intel.com>
7 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
8 *
9 * Copyright (C) 2002 Intel Corp.
10 * Copyright (C) 2003-2004 MontaVista Software, Inc.
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/mm.h>
20#include <linux/sched.h>
21#include <linux/interrupt.h>
22#include <linux/device.h>
23#include <linux/bitops.h>
24#include <linux/pci.h>
25#include <linux/ioport.h>
26#include <linux/delay.h>
27#include <linux/io.h>
28
29#include <asm/irq.h>
30#include <asm/pgtable.h>
31#include <asm/page.h>
32#include <mach/hardware.h>
33#include <asm/mach-types.h>
34
35#include <asm/mach/pci.h>
36#include <asm/mach/map.h>
37#include <asm/mach/irq.h>
38#include <asm/mach/time.h>
39#include <asm/mach/flash.h>
40#include <asm/mach/arch.h>
41
42/*************************************************************************
43 * IXDP2800 timer tick
44 *************************************************************************/
45
46static void __init ixdp2800_timer_init(void)
47{
48 ixp2000_init_time(50000000);
49}
50
51static struct sys_timer ixdp2800_timer = {
52 .init = ixdp2800_timer_init,
53 .offset = ixp2000_gettimeoffset,
54};
55
56/*************************************************************************
57 * IXDP2800 PCI
58 *************************************************************************/
59static void __init ixdp2800_slave_disable_pci_master(void)
60{
61 *IXP2000_PCI_CMDSTAT &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
62}
63
64static void __init ixdp2800_master_wait_for_slave(void)
65{
66 volatile u32 *addr;
67
68 printk(KERN_INFO "IXDP2800: waiting for slave NPU to configure "
69 "its BAR sizes\n");
70
71 addr = ixp2000_pci_config_addr(0, IXDP2X00_SLAVE_NPU_DEVFN,
72 PCI_BASE_ADDRESS_1);
73 do {
74 *addr = 0xffffffff;
75 cpu_relax();
76 } while (*addr != 0xfe000008);
77
78 addr = ixp2000_pci_config_addr(0, IXDP2X00_SLAVE_NPU_DEVFN,
79 PCI_BASE_ADDRESS_2);
80 do {
81 *addr = 0xffffffff;
82 cpu_relax();
83 } while (*addr != 0xc0000008);
84
85 /*
86 * Configure the slave's SDRAM BAR by hand.
87 */
88 *addr = 0x40000008;
89}
90
91static void __init ixdp2800_slave_wait_for_master_enable(void)
92{
93 printk(KERN_INFO "IXDP2800: waiting for master NPU to enable us\n");
94
95 while ((*IXP2000_PCI_CMDSTAT & PCI_COMMAND_MASTER) == 0)
96 cpu_relax();
97}
98
99void __init ixdp2800_pci_preinit(void)
100{
101 printk("ixdp2x00_pci_preinit called\n");
102
103 *IXP2000_PCI_ADDR_EXT = 0x0001e000;
104
105 if (!ixdp2x00_master_npu())
106 ixdp2800_slave_disable_pci_master();
107
108 *IXP2000_PCI_SRAM_BASE_ADDR_MASK = (0x2000000 - 1) & ~0x3ffff;
109 *IXP2000_PCI_DRAM_BASE_ADDR_MASK = (0x40000000 - 1) & ~0xfffff;
110
111 ixp2000_pci_preinit();
112
113 if (ixdp2x00_master_npu()) {
114 /*
115 * Wait until the slave set its SRAM/SDRAM BAR sizes
116 * correctly before we proceed to scan and enumerate
117 * the bus.
118 */
119 ixdp2800_master_wait_for_slave();
120
121 /*
122 * We configure the SDRAM BARs by hand because they
123 * are 1G and fall outside of the regular allocated
124 * PCI address space.
125 */
126 *IXP2000_PCI_SDRAM_BAR = 0x00000008;
127 } else {
128 /*
129 * Wait for the master to complete scanning the bus
130 * and assigning resources before we proceed to scan
131 * the bus ourselves. Set pci=firmware to honor the
132 * master's resource assignment.
133 */
134 ixdp2800_slave_wait_for_master_enable();
135 pcibios_setup("firmware");
136 }
137}
138
139/*
140 * We assign the SDRAM BARs for the two IXP2800 CPUs by hand, outside
141 * of the regular PCI window, because there's only 512M of outbound PCI
142 * memory window on each IXP, while we need 1G for each of the BARs.
143 */
144static void __devinit ixp2800_pci_fixup(struct pci_dev *dev)
145{
146 if (machine_is_ixdp2800()) {
147 dev->resource[2].start = 0;
148 dev->resource[2].end = 0;
149 dev->resource[2].flags = 0;
150 }
151}
152DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IXP2800, ixp2800_pci_fixup);
153
154static int __init ixdp2800_pci_setup(int nr, struct pci_sys_data *sys)
155{
156 sys->mem_offset = 0x00000000;
157
158 ixp2000_pci_setup(nr, sys);
159
160 return 1;
161}
162
163static int __init ixdp2800_pci_map_irq(const struct pci_dev *dev, u8 slot,
164 u8 pin)
165{
166 if (ixdp2x00_master_npu()) {
167
168 /*
169 * Root bus devices. Slave NPU is only one with interrupt.
170 * Everything else, we just return -1 which is invalid.
171 */
172 if(!dev->bus->self) {
173 if(dev->devfn == IXDP2X00_SLAVE_NPU_DEVFN )
174 return IRQ_IXDP2800_INGRESS_NPU;
175
176 return -1;
177 }
178
179 /*
180 * Bridge behind the PMC slot.
181 */
182 if(dev->bus->self->devfn == IXDP2X00_PMC_DEVFN &&
183 dev->bus->parent->self->devfn == IXDP2X00_P2P_DEVFN &&
184 !dev->bus->parent->self->bus->parent)
185 return IRQ_IXDP2800_PMC;
186
187 /*
188 * Device behind the first bridge
189 */
190 if(dev->bus->self->devfn == IXDP2X00_P2P_DEVFN) {
191 switch(dev->devfn) {
192 case IXDP2X00_PMC_DEVFN:
193 return IRQ_IXDP2800_PMC;
194
195 case IXDP2800_MASTER_ENET_DEVFN:
196 return IRQ_IXDP2800_EGRESS_ENET;
197
198 case IXDP2800_SWITCH_FABRIC_DEVFN:
199 return IRQ_IXDP2800_FABRIC;
200 }
201 }
202
203 return -1;
204 } else return IRQ_IXP2000_PCIB; /* Slave NIC interrupt */
205}
206
207static void __init ixdp2800_master_enable_slave(void)
208{
209 volatile u32 *addr;
210
211 printk(KERN_INFO "IXDP2800: enabling slave NPU\n");
212
213 addr = (volatile u32 *)ixp2000_pci_config_addr(0,
214 IXDP2X00_SLAVE_NPU_DEVFN,
215 PCI_COMMAND);
216
217 *addr |= PCI_COMMAND_MASTER;
218}
219
220static void __init ixdp2800_master_wait_for_slave_bus_scan(void)
221{
222 volatile u32 *addr;
223
224 printk(KERN_INFO "IXDP2800: waiting for slave to finish bus scan\n");
225
226 addr = (volatile u32 *)ixp2000_pci_config_addr(0,
227 IXDP2X00_SLAVE_NPU_DEVFN,
228 PCI_COMMAND);
229 while ((*addr & PCI_COMMAND_MEMORY) == 0)
230 cpu_relax();
231}
232
233static void __init ixdp2800_slave_signal_bus_scan_completion(void)
234{
235 printk(KERN_INFO "IXDP2800: bus scan done, signaling master\n");
236 *IXP2000_PCI_CMDSTAT |= PCI_COMMAND_MEMORY;
237}
238
239static void __init ixdp2800_pci_postinit(void)
240{
241 if (!ixdp2x00_master_npu()) {
242 ixdp2x00_slave_pci_postinit();
243 ixdp2800_slave_signal_bus_scan_completion();
244 }
245}
246
247struct __initdata hw_pci ixdp2800_pci __initdata = {
248 .nr_controllers = 1,
249 .setup = ixdp2800_pci_setup,
250 .preinit = ixdp2800_pci_preinit,
251 .postinit = ixdp2800_pci_postinit,
252 .scan = ixp2000_pci_scan_bus,
253 .map_irq = ixdp2800_pci_map_irq,
254};
255
256int __init ixdp2800_pci_init(void)
257{
258 if (machine_is_ixdp2800()) {
259 struct pci_dev *dev;
260
261 pci_common_init(&ixdp2800_pci);
262 if (ixdp2x00_master_npu()) {
263 dev = pci_get_bus_and_slot(1, IXDP2800_SLAVE_ENET_DEVFN);
264 pci_stop_and_remove_bus_device(dev);
265 pci_dev_put(dev);
266
267 ixdp2800_master_enable_slave();
268 ixdp2800_master_wait_for_slave_bus_scan();
269 } else {
270 dev = pci_get_bus_and_slot(1, IXDP2800_MASTER_ENET_DEVFN);
271 pci_stop_and_remove_bus_device(dev);
272 pci_dev_put(dev);
273 }
274 }
275
276 return 0;
277}
278
279subsys_initcall(ixdp2800_pci_init);
280
281void __init ixdp2800_init_irq(void)
282{
283 ixdp2x00_init_irq(IXDP2800_CPLD_INT_STAT, IXDP2800_CPLD_INT_MASK, IXDP2800_NR_IRQS);
284}
285
286MACHINE_START(IXDP2800, "Intel IXDP2800 Development Platform")
287 /* Maintainer: MontaVista Software, Inc. */
288 .atag_offset = 0x100,
289 .map_io = ixdp2x00_map_io,
290 .init_irq = ixdp2800_init_irq,
291 .timer = &ixdp2800_timer,
292 .init_machine = ixdp2x00_init_machine,
293 .restart = ixp2000_restart,
294MACHINE_END
295
diff --git a/arch/arm/mach-ixp2000/ixdp2x00.c b/arch/arm/mach-ixp2000/ixdp2x00.c
deleted file mode 100644
index 421e38dc0fac..000000000000
--- a/arch/arm/mach-ixp2000/ixdp2x00.c
+++ /dev/null
@@ -1,306 +0,0 @@
1/*
2 * arch/arm/mach-ixp2000/ixdp2x00.c
3 *
4 * Code common to IXDP2400 and IXDP2800 platforms.
5 *
6 * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
7 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
8 *
9 * Copyright (C) 2002 Intel Corp.
10 * Copyright (C) 2003-2004 MontaVista Software, Inc.
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17#include <linux/gpio.h>
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/mm.h>
21#include <linux/sched.h>
22#include <linux/interrupt.h>
23#include <linux/platform_device.h>
24#include <linux/bitops.h>
25#include <linux/pci.h>
26#include <linux/ioport.h>
27#include <linux/delay.h>
28#include <linux/io.h>
29
30#include <asm/irq.h>
31#include <asm/pgtable.h>
32#include <asm/page.h>
33#include <mach/hardware.h>
34#include <asm/mach-types.h>
35
36#include <asm/mach/pci.h>
37#include <asm/mach/map.h>
38#include <asm/mach/irq.h>
39#include <asm/mach/time.h>
40#include <asm/mach/flash.h>
41#include <asm/mach/arch.h>
42
43#include <mach/gpio-ixp2000.h>
44
45/*************************************************************************
46 * IXDP2x00 IRQ Initialization
47 *************************************************************************/
48static volatile unsigned long *board_irq_mask;
49static volatile unsigned long *board_irq_stat;
50static unsigned long board_irq_count;
51
52#ifdef CONFIG_ARCH_IXDP2400
53/*
54 * Slowport configuration for accessing CPLD registers on IXDP2x00
55 */
56static struct slowport_cfg slowport_cpld_cfg = {
57 .CCR = SLOWPORT_CCR_DIV_2,
58 .WTC = 0x00000070,
59 .RTC = 0x00000070,
60 .PCR = SLOWPORT_MODE_FLASH,
61 .ADC = SLOWPORT_ADDR_WIDTH_24 | SLOWPORT_DATA_WIDTH_8
62};
63#endif
64
65static void ixdp2x00_irq_mask(struct irq_data *d)
66{
67 unsigned long dummy;
68 static struct slowport_cfg old_cfg;
69
70 /*
71 * This is ugly in common code but really don't know
72 * of a better way to handle it. :(
73 */
74#ifdef CONFIG_ARCH_IXDP2400
75 if (machine_is_ixdp2400())
76 ixp2000_acquire_slowport(&slowport_cpld_cfg, &old_cfg);
77#endif
78
79 dummy = *board_irq_mask;
80 dummy |= IXP2000_BOARD_IRQ_MASK(d->irq);
81 ixp2000_reg_wrb(board_irq_mask, dummy);
82
83#ifdef CONFIG_ARCH_IXDP2400
84 if (machine_is_ixdp2400())
85 ixp2000_release_slowport(&old_cfg);
86#endif
87}
88
89static void ixdp2x00_irq_unmask(struct irq_data *d)
90{
91 unsigned long dummy;
92 static struct slowport_cfg old_cfg;
93
94#ifdef CONFIG_ARCH_IXDP2400
95 if (machine_is_ixdp2400())
96 ixp2000_acquire_slowport(&slowport_cpld_cfg, &old_cfg);
97#endif
98
99 dummy = *board_irq_mask;
100 dummy &= ~IXP2000_BOARD_IRQ_MASK(d->irq);
101 ixp2000_reg_wrb(board_irq_mask, dummy);
102
103 if (machine_is_ixdp2400())
104 ixp2000_release_slowport(&old_cfg);
105}
106
107static void ixdp2x00_irq_handler(unsigned int irq, struct irq_desc *desc)
108{
109 volatile u32 ex_interrupt = 0;
110 static struct slowport_cfg old_cfg;
111 int i;
112
113 desc->irq_data.chip->irq_mask(&desc->irq_data);
114
115#ifdef CONFIG_ARCH_IXDP2400
116 if (machine_is_ixdp2400())
117 ixp2000_acquire_slowport(&slowport_cpld_cfg, &old_cfg);
118#endif
119 ex_interrupt = *board_irq_stat & 0xff;
120 if (machine_is_ixdp2400())
121 ixp2000_release_slowport(&old_cfg);
122
123 if(!ex_interrupt) {
124 printk(KERN_ERR "Spurious IXDP2x00 CPLD interrupt!\n");
125 return;
126 }
127
128 for(i = 0; i < board_irq_count; i++) {
129 if(ex_interrupt & (1 << i)) {
130 int cpld_irq = IXP2000_BOARD_IRQ(0) + i;
131 generic_handle_irq(cpld_irq);
132 }
133 }
134
135 desc->irq_data.chip->irq_unmask(&desc->irq_data);
136}
137
138static struct irq_chip ixdp2x00_cpld_irq_chip = {
139 .irq_ack = ixdp2x00_irq_mask,
140 .irq_mask = ixdp2x00_irq_mask,
141 .irq_unmask = ixdp2x00_irq_unmask
142};
143
144void __init ixdp2x00_init_irq(volatile unsigned long *stat_reg, volatile unsigned long *mask_reg, unsigned long nr_of_irqs)
145{
146 unsigned int irq;
147
148 ixp2000_init_irq();
149
150 if (!ixdp2x00_master_npu())
151 return;
152
153 board_irq_stat = stat_reg;
154 board_irq_mask = mask_reg;
155 board_irq_count = nr_of_irqs;
156
157 *board_irq_mask = 0xffffffff;
158
159 for(irq = IXP2000_BOARD_IRQ(0); irq < IXP2000_BOARD_IRQ(board_irq_count); irq++) {
160 irq_set_chip_and_handler(irq, &ixdp2x00_cpld_irq_chip,
161 handle_level_irq);
162 set_irq_flags(irq, IRQF_VALID);
163 }
164
165 /* Hook into PCI interrupt */
166 irq_set_chained_handler(IRQ_IXP2000_PCIB, ixdp2x00_irq_handler);
167}
168
169/*************************************************************************
170 * IXDP2x00 memory map
171 *************************************************************************/
172static struct map_desc ixdp2x00_io_desc __initdata = {
173 .virtual = IXDP2X00_VIRT_CPLD_BASE,
174 .pfn = __phys_to_pfn(IXDP2X00_PHYS_CPLD_BASE),
175 .length = IXDP2X00_CPLD_SIZE,
176 .type = MT_DEVICE
177};
178
179void __init ixdp2x00_map_io(void)
180{
181 ixp2000_map_io();
182
183 iotable_init(&ixdp2x00_io_desc, 1);
184}
185
186/*************************************************************************
187 * IXDP2x00-common PCI init
188 *
189 * The IXDP2[48]00 has a horrid PCI bus layout. Basically the board
190 * contains two NPUs (ingress and egress) connected over PCI, both running
191 * instances of the kernel. So far so good. Peers on the PCI bus running
192 * Linux is a common design in telecom systems. The problem is that instead
193 * of all the devices being controlled by a single host, different
194 * devices are controlled by different NPUs on the same bus, leading to
195 * multiple hosts on the bus. The exact bus layout looks like:
196 *
197 * Bus 0
198 * Master NPU <-------------------+-------------------> Slave NPU
199 * |
200 * |
201 * P2P
202 * |
203 *
204 * Bus 1 |
205 * <--+------+---------+---------+------+-->
206 * | | | | |
207 * | | | | |
208 * ... Dev PMC Media Eth0 Eth1 ...
209 *
210 * The master controls all but Eth1, which is controlled by the
211 * slave. What this means is that the both the master and the slave
212 * have to scan the bus, but only one of them can enumerate the bus.
213 * In addition, after the bus is scanned, each kernel must remove
214 * the device(s) it does not control from the PCI dev list otherwise
215 * a driver on each NPU will try to manage it and we will have horrible
216 * conflicts. Oh..and the slave NPU needs to see the master NPU
217 * for Intel's drivers to work properly. Closed source drivers...
218 *
219 * The way we deal with this is fairly simple but ugly:
220 *
221 * 1) Let master scan and enumerate the bus completely.
222 * 2) Master deletes Eth1 from device list.
223 * 3) Slave scans bus and then deletes all but Eth1 (Eth0 on slave)
224 * from device list.
225 * 4) Find HW designers and LART them.
226 *
227 * The boards also do not do normal PCI IRQ routing, or any sort of
228 * sensical swizzling, so we just need to check where on the bus a
229 * device sits and figure out to which CPLD pin the interrupt is routed.
230 * See ixdp2[48]00.c files.
231 *
232 *************************************************************************/
233void ixdp2x00_slave_pci_postinit(void)
234{
235 struct pci_dev *dev;
236
237 /*
238 * Remove PMC device is there is one
239 */
240 if((dev = pci_get_bus_and_slot(1, IXDP2X00_PMC_DEVFN))) {
241 pci_stop_and_remove_bus_device(dev);
242 pci_dev_put(dev);
243 }
244
245 dev = pci_get_bus_and_slot(0, IXDP2X00_21555_DEVFN);
246 pci_stop_and_remove_bus_device(dev);
247 pci_dev_put(dev);
248}
249
250/**************************************************************************
251 * IXDP2x00 Machine Setup
252 *************************************************************************/
253static struct flash_platform_data ixdp2x00_platform_data = {
254 .map_name = "cfi_probe",
255 .width = 1,
256};
257
258static struct ixp2000_flash_data ixdp2x00_flash_data = {
259 .platform_data = &ixdp2x00_platform_data,
260 .nr_banks = 1
261};
262
263static struct resource ixdp2x00_flash_resource = {
264 .start = 0xc4000000,
265 .end = 0xc4000000 + 0x00ffffff,
266 .flags = IORESOURCE_MEM,
267};
268
269static struct platform_device ixdp2x00_flash = {
270 .name = "IXP2000-Flash",
271 .id = 0,
272 .dev = {
273 .platform_data = &ixdp2x00_flash_data,
274 },
275 .num_resources = 1,
276 .resource = &ixdp2x00_flash_resource,
277};
278
279static struct ixp2000_i2c_pins ixdp2x00_i2c_gpio_pins = {
280 .sda_pin = IXDP2X00_GPIO_SDA,
281 .scl_pin = IXDP2X00_GPIO_SCL,
282};
283
284static struct platform_device ixdp2x00_i2c_controller = {
285 .name = "IXP2000-I2C",
286 .id = 0,
287 .dev = {
288 .platform_data = &ixdp2x00_i2c_gpio_pins,
289 },
290 .num_resources = 0
291};
292
293static struct platform_device *ixdp2x00_devices[] __initdata = {
294 &ixdp2x00_flash,
295 &ixdp2x00_i2c_controller
296};
297
298void __init ixdp2x00_init_machine(void)
299{
300 gpio_line_set(IXDP2X00_GPIO_I2C_ENABLE, 1);
301 gpio_line_config(IXDP2X00_GPIO_I2C_ENABLE, GPIO_OUT);
302
303 platform_add_devices(ixdp2x00_devices, ARRAY_SIZE(ixdp2x00_devices));
304 ixp2000_uart_init();
305}
306
diff --git a/arch/arm/mach-ixp2000/ixdp2x01.c b/arch/arm/mach-ixp2000/ixdp2x01.c
deleted file mode 100644
index 5196c39cdba4..000000000000
--- a/arch/arm/mach-ixp2000/ixdp2x01.c
+++ /dev/null
@@ -1,483 +0,0 @@
1/*
2 * arch/arm/mach-ixp2000/ixdp2x01.c
3 *
4 * Code common to Intel IXDP2401 and IXDP2801 platforms
5 *
6 * Original Author: Andrzej Mialkowski <andrzej.mialkowski@intel.com>
7 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
8 *
9 * Copyright (C) 2002-2003 Intel Corp.
10 * Copyright (C) 2003-2004 MontaVista Software, Inc.
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/mm.h>
21#include <linux/sched.h>
22#include <linux/interrupt.h>
23#include <linux/bitops.h>
24#include <linux/pci.h>
25#include <linux/ioport.h>
26#include <linux/delay.h>
27#include <linux/serial.h>
28#include <linux/tty.h>
29#include <linux/serial_core.h>
30#include <linux/platform_device.h>
31#include <linux/serial_8250.h>
32#include <linux/io.h>
33
34#include <asm/irq.h>
35#include <asm/pgtable.h>
36#include <asm/page.h>
37#include <mach/hardware.h>
38#include <asm/mach-types.h>
39
40#include <asm/mach/pci.h>
41#include <asm/mach/map.h>
42#include <asm/mach/irq.h>
43#include <asm/mach/time.h>
44#include <asm/mach/arch.h>
45#include <asm/mach/flash.h>
46
47/*************************************************************************
48 * IXDP2x01 IRQ Handling
49 *************************************************************************/
50static void ixdp2x01_irq_mask(struct irq_data *d)
51{
52 ixp2000_reg_wrb(IXDP2X01_INT_MASK_SET_REG,
53 IXP2000_BOARD_IRQ_MASK(d->irq));
54}
55
56static void ixdp2x01_irq_unmask(struct irq_data *d)
57{
58 ixp2000_reg_write(IXDP2X01_INT_MASK_CLR_REG,
59 IXP2000_BOARD_IRQ_MASK(d->irq));
60}
61
62static u32 valid_irq_mask;
63
64static void ixdp2x01_irq_handler(unsigned int irq, struct irq_desc *desc)
65{
66 u32 ex_interrupt;
67 int i;
68
69 desc->irq_data.chip->irq_mask(&desc->irq_data);
70
71 ex_interrupt = *IXDP2X01_INT_STAT_REG & valid_irq_mask;
72
73 if (!ex_interrupt) {
74 printk(KERN_ERR "Spurious IXDP2X01 CPLD interrupt!\n");
75 return;
76 }
77
78 for (i = 0; i < IXP2000_BOARD_IRQS; i++) {
79 if (ex_interrupt & (1 << i)) {
80 int cpld_irq = IXP2000_BOARD_IRQ(0) + i;
81 generic_handle_irq(cpld_irq);
82 }
83 }
84
85 desc->irq_data.chip->irq_unmask(&desc->irq_data);
86}
87
88static struct irq_chip ixdp2x01_irq_chip = {
89 .irq_mask = ixdp2x01_irq_mask,
90 .irq_ack = ixdp2x01_irq_mask,
91 .irq_unmask = ixdp2x01_irq_unmask
92};
93
94/*
95 * We only do anything if we are the master NPU on the board.
96 * The slave NPU only has the ethernet chip going directly to
97 * the PCIB interrupt input.
98 */
99void __init ixdp2x01_init_irq(void)
100{
101 int irq = 0;
102
103 /* initialize chip specific interrupts */
104 ixp2000_init_irq();
105
106 if (machine_is_ixdp2401())
107 valid_irq_mask = IXDP2401_VALID_IRQ_MASK;
108 else
109 valid_irq_mask = IXDP2801_VALID_IRQ_MASK;
110
111 /* Mask all interrupts from CPLD, disable simulation */
112 ixp2000_reg_write(IXDP2X01_INT_MASK_SET_REG, 0xffffffff);
113 ixp2000_reg_wrb(IXDP2X01_INT_SIM_REG, 0);
114
115 for (irq = NR_IXP2000_IRQS; irq < NR_IXDP2X01_IRQS; irq++) {
116 if (irq & valid_irq_mask) {
117 irq_set_chip_and_handler(irq, &ixdp2x01_irq_chip,
118 handle_level_irq);
119 set_irq_flags(irq, IRQF_VALID);
120 } else {
121 set_irq_flags(irq, 0);
122 }
123 }
124
125 /* Hook into PCI interrupts */
126 irq_set_chained_handler(IRQ_IXP2000_PCIB, ixdp2x01_irq_handler);
127}
128
129
130/*************************************************************************
131 * IXDP2x01 memory map
132 *************************************************************************/
133static struct map_desc ixdp2x01_io_desc __initdata = {
134 .virtual = IXDP2X01_VIRT_CPLD_BASE,
135 .pfn = __phys_to_pfn(IXDP2X01_PHYS_CPLD_BASE),
136 .length = IXDP2X01_CPLD_REGION_SIZE,
137 .type = MT_DEVICE
138};
139
140static void __init ixdp2x01_map_io(void)
141{
142 ixp2000_map_io();
143 iotable_init(&ixdp2x01_io_desc, 1);
144}
145
146
147/*************************************************************************
148 * IXDP2x01 serial ports
149 *************************************************************************/
150static struct plat_serial8250_port ixdp2x01_serial_port1[] = {
151 {
152 .mapbase = (unsigned long)IXDP2X01_UART1_PHYS_BASE,
153 .membase = (char *)IXDP2X01_UART1_VIRT_BASE,
154 .irq = IRQ_IXDP2X01_UART1,
155 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
156 .iotype = UPIO_MEM32,
157 .regshift = 2,
158 .uartclk = IXDP2X01_UART_CLK,
159 },
160 { }
161};
162
163static struct resource ixdp2x01_uart_resource1 = {
164 .start = IXDP2X01_UART1_PHYS_BASE,
165 .end = IXDP2X01_UART1_PHYS_BASE + 0xffff,
166 .flags = IORESOURCE_MEM,
167};
168
169static struct platform_device ixdp2x01_serial_device1 = {
170 .name = "serial8250",
171 .id = PLAT8250_DEV_PLATFORM1,
172 .dev = {
173 .platform_data = ixdp2x01_serial_port1,
174 },
175 .num_resources = 1,
176 .resource = &ixdp2x01_uart_resource1,
177};
178
179static struct plat_serial8250_port ixdp2x01_serial_port2[] = {
180 {
181 .mapbase = (unsigned long)IXDP2X01_UART2_PHYS_BASE,
182 .membase = (char *)IXDP2X01_UART2_VIRT_BASE,
183 .irq = IRQ_IXDP2X01_UART2,
184 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
185 .iotype = UPIO_MEM32,
186 .regshift = 2,
187 .uartclk = IXDP2X01_UART_CLK,
188 },
189 { }
190};
191
192static struct resource ixdp2x01_uart_resource2 = {
193 .start = IXDP2X01_UART2_PHYS_BASE,
194 .end = IXDP2X01_UART2_PHYS_BASE + 0xffff,
195 .flags = IORESOURCE_MEM,
196};
197
198static struct platform_device ixdp2x01_serial_device2 = {
199 .name = "serial8250",
200 .id = PLAT8250_DEV_PLATFORM2,
201 .dev = {
202 .platform_data = ixdp2x01_serial_port2,
203 },
204 .num_resources = 1,
205 .resource = &ixdp2x01_uart_resource2,
206};
207
208static void ixdp2x01_uart_init(void)
209{
210 platform_device_register(&ixdp2x01_serial_device1);
211 platform_device_register(&ixdp2x01_serial_device2);
212}
213
214
215/*************************************************************************
216 * IXDP2x01 timer tick configuration
217 *************************************************************************/
218static unsigned int ixdp2x01_clock;
219
220static int __init ixdp2x01_clock_setup(char *str)
221{
222 ixdp2x01_clock = simple_strtoul(str, NULL, 10);
223
224 return 1;
225}
226
227__setup("ixdp2x01_clock=", ixdp2x01_clock_setup);
228
229static void __init ixdp2x01_timer_init(void)
230{
231 if (!ixdp2x01_clock)
232 ixdp2x01_clock = 50000000;
233
234 ixp2000_init_time(ixdp2x01_clock);
235}
236
237static struct sys_timer ixdp2x01_timer = {
238 .init = ixdp2x01_timer_init,
239 .offset = ixp2000_gettimeoffset,
240};
241
242/*************************************************************************
243 * IXDP2x01 PCI
244 *************************************************************************/
245void __init ixdp2x01_pci_preinit(void)
246{
247 ixp2000_reg_write(IXP2000_PCI_ADDR_EXT, 0x00000000);
248 ixp2000_pci_preinit();
249 pcibios_setup("firmware");
250}
251
252#define DEVPIN(dev, pin) ((pin) | ((dev) << 3))
253
254static int __init ixdp2x01_pci_map_irq(const struct pci_dev *dev, u8 slot,
255 u8 pin)
256{
257 u8 bus = dev->bus->number;
258 u32 devpin = DEVPIN(PCI_SLOT(dev->devfn), pin);
259 struct pci_bus *tmp_bus = dev->bus;
260
261 /* Primary bus, no interrupts here */
262 if (bus == 0) {
263 return -1;
264 }
265
266 /* Lookup first leaf in bus tree */
267 while ((tmp_bus->parent != NULL) && (tmp_bus->parent->parent != NULL)) {
268 tmp_bus = tmp_bus->parent;
269 }
270
271 /* Select between known bridges */
272 switch (tmp_bus->self->devfn | (tmp_bus->self->bus->number << 8)) {
273 /* Device is located after first MB bridge */
274 case 0x0008:
275 if (tmp_bus == dev->bus) {
276 /* Device is located directly after first MB bridge */
277 switch (devpin) {
278 case DEVPIN(1, 1): /* Onboard 82546 ch 0 */
279 if (machine_is_ixdp2401())
280 return IRQ_IXDP2401_INTA_82546;
281 return -1;
282 case DEVPIN(1, 2): /* Onboard 82546 ch 1 */
283 if (machine_is_ixdp2401())
284 return IRQ_IXDP2401_INTB_82546;
285 return -1;
286 case DEVPIN(0, 1): /* PMC INTA# */
287 return IRQ_IXDP2X01_SPCI_PMC_INTA;
288 case DEVPIN(0, 2): /* PMC INTB# */
289 return IRQ_IXDP2X01_SPCI_PMC_INTB;
290 case DEVPIN(0, 3): /* PMC INTC# */
291 return IRQ_IXDP2X01_SPCI_PMC_INTC;
292 case DEVPIN(0, 4): /* PMC INTD# */
293 return IRQ_IXDP2X01_SPCI_PMC_INTD;
294 }
295 }
296 break;
297 case 0x0010:
298 if (tmp_bus == dev->bus) {
299 /* Device is located directly after second MB bridge */
300 /* Secondary bus of second bridge */
301 switch (devpin) {
302 case DEVPIN(0, 1): /* DB#0 */
303 return IRQ_IXDP2X01_SPCI_DB_0;
304 case DEVPIN(1, 1): /* DB#1 */
305 return IRQ_IXDP2X01_SPCI_DB_1;
306 }
307 } else {
308 /* Device is located indirectly after second MB bridge */
309 /* Not supported now */
310 }
311 break;
312 }
313
314 return -1;
315}
316
317
318static int ixdp2x01_pci_setup(int nr, struct pci_sys_data *sys)
319{
320 sys->mem_offset = 0xe0000000;
321
322 if (machine_is_ixdp2801() || machine_is_ixdp28x5())
323 sys->mem_offset -= ((*IXP2000_PCI_ADDR_EXT & 0xE000) << 16);
324
325 return ixp2000_pci_setup(nr, sys);
326}
327
328struct hw_pci ixdp2x01_pci __initdata = {
329 .nr_controllers = 1,
330 .setup = ixdp2x01_pci_setup,
331 .preinit = ixdp2x01_pci_preinit,
332 .scan = ixp2000_pci_scan_bus,
333 .map_irq = ixdp2x01_pci_map_irq,
334};
335
336int __init ixdp2x01_pci_init(void)
337{
338 if (machine_is_ixdp2401() || machine_is_ixdp2801() ||\
339 machine_is_ixdp28x5())
340 pci_common_init(&ixdp2x01_pci);
341
342 return 0;
343}
344
345subsys_initcall(ixdp2x01_pci_init);
346
347/*************************************************************************
348 * IXDP2x01 Machine Initialization
349 *************************************************************************/
350static struct flash_platform_data ixdp2x01_flash_platform_data = {
351 .map_name = "cfi_probe",
352 .width = 1,
353};
354
355static unsigned long ixdp2x01_flash_bank_setup(unsigned long ofs)
356{
357 ixp2000_reg_wrb(IXDP2X01_CPLD_FLASH_REG,
358 ((ofs >> IXDP2X01_FLASH_WINDOW_BITS) | IXDP2X01_CPLD_FLASH_INTERN));
359 return (ofs & IXDP2X01_FLASH_WINDOW_MASK);
360}
361
362static struct ixp2000_flash_data ixdp2x01_flash_data = {
363 .platform_data = &ixdp2x01_flash_platform_data,
364 .bank_setup = ixdp2x01_flash_bank_setup
365};
366
367static struct resource ixdp2x01_flash_resource = {
368 .start = 0xc4000000,
369 .end = 0xc4000000 + 0x01ffffff,
370 .flags = IORESOURCE_MEM,
371};
372
373static struct platform_device ixdp2x01_flash = {
374 .name = "IXP2000-Flash",
375 .id = 0,
376 .dev = {
377 .platform_data = &ixdp2x01_flash_data,
378 },
379 .num_resources = 1,
380 .resource = &ixdp2x01_flash_resource,
381};
382
383static struct ixp2000_i2c_pins ixdp2x01_i2c_gpio_pins = {
384 .sda_pin = IXDP2X01_GPIO_SDA,
385 .scl_pin = IXDP2X01_GPIO_SCL,
386};
387
388static struct platform_device ixdp2x01_i2c_controller = {
389 .name = "IXP2000-I2C",
390 .id = 0,
391 .dev = {
392 .platform_data = &ixdp2x01_i2c_gpio_pins,
393 },
394 .num_resources = 0
395};
396
397static struct platform_device *ixdp2x01_devices[] __initdata = {
398 &ixdp2x01_flash,
399 &ixdp2x01_i2c_controller
400};
401
402static void __init ixdp2x01_init_machine(void)
403{
404 ixp2000_reg_wrb(IXDP2X01_CPLD_FLASH_REG,
405 (IXDP2X01_CPLD_FLASH_BANK_MASK | IXDP2X01_CPLD_FLASH_INTERN));
406
407 ixdp2x01_flash_data.nr_banks =
408 ((*IXDP2X01_CPLD_FLASH_REG & IXDP2X01_CPLD_FLASH_BANK_MASK) + 1);
409
410 platform_add_devices(ixdp2x01_devices, ARRAY_SIZE(ixdp2x01_devices));
411 ixp2000_uart_init();
412 ixdp2x01_uart_init();
413}
414
415static void ixdp2401_restart(char mode, const char *cmd)
416{
417 /*
418 * Reset flash banking register so that we are pointing at
419 * RedBoot bank.
420 */
421 ixp2000_reg_write(IXDP2X01_CPLD_FLASH_REG,
422 ((0 >> IXDP2X01_FLASH_WINDOW_BITS)
423 | IXDP2X01_CPLD_FLASH_INTERN));
424 ixp2000_reg_wrb(IXDP2X01_CPLD_RESET_REG, 0xffffffff);
425
426 ixp2000_restart(mode, cmd);
427}
428
429static void ixdp280x_restart(char mode, const char *cmd)
430{
431 /*
432 * On IXDP2801 we need to write this magic sequence to the CPLD
433 * to cause a complete reset of the CPU and all external devices
434 * and move the flash bank register back to 0.
435 */
436 unsigned long reset_reg = *IXDP2X01_CPLD_RESET_REG;
437
438 reset_reg = 0x55AA0000 | (reset_reg & 0x0000FFFF);
439 ixp2000_reg_write(IXDP2X01_CPLD_RESET_REG, reset_reg);
440 ixp2000_reg_wrb(IXDP2X01_CPLD_RESET_REG, 0x80000000);
441
442 ixp2000_restart(mode, cmd);
443}
444
445#ifdef CONFIG_ARCH_IXDP2401
446MACHINE_START(IXDP2401, "Intel IXDP2401 Development Platform")
447 /* Maintainer: MontaVista Software, Inc. */
448 .atag_offset = 0x100,
449 .map_io = ixdp2x01_map_io,
450 .init_irq = ixdp2x01_init_irq,
451 .timer = &ixdp2x01_timer,
452 .init_machine = ixdp2x01_init_machine,
453 .restart = ixdp2401_restart,
454MACHINE_END
455#endif
456
457#ifdef CONFIG_ARCH_IXDP2801
458MACHINE_START(IXDP2801, "Intel IXDP2801 Development Platform")
459 /* Maintainer: MontaVista Software, Inc. */
460 .atag_offset = 0x100,
461 .map_io = ixdp2x01_map_io,
462 .init_irq = ixdp2x01_init_irq,
463 .timer = &ixdp2x01_timer,
464 .init_machine = ixdp2x01_init_machine,
465 .restart = ixdp280x_restart,
466MACHINE_END
467
468/*
469 * IXDP28x5 is basically an IXDP2801 with a different CPU but Intel
470 * changed the machine ID in the bootloader
471 */
472MACHINE_START(IXDP28X5, "Intel IXDP2805/2855 Development Platform")
473 /* Maintainer: MontaVista Software, Inc. */
474 .atag_offset = 0x100,
475 .map_io = ixdp2x01_map_io,
476 .init_irq = ixdp2x01_init_irq,
477 .timer = &ixdp2x01_timer,
478 .init_machine = ixdp2x01_init_machine,
479 .restart = ixdp280x_restart,
480MACHINE_END
481#endif
482
483
diff --git a/arch/arm/mach-ixp2000/pci.c b/arch/arm/mach-ixp2000/pci.c
deleted file mode 100644
index 9c02de932fac..000000000000
--- a/arch/arm/mach-ixp2000/pci.c
+++ /dev/null
@@ -1,252 +0,0 @@
1/*
2 * arch/arm/mach-ixp2000/pci.c
3 *
4 * PCI routines for IXDP2400/IXDP2800 boards
5 *
6 * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
7 * Maintained by: Deepak Saxena <dsaxena@plexity.net>
8 *
9 * Copyright 2002 Intel Corp.
10 * Copyright (C) 2003-2004 MontaVista Software, Inc.
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17
18#include <linux/sched.h>
19#include <linux/kernel.h>
20#include <linux/pci.h>
21#include <linux/interrupt.h>
22#include <linux/mm.h>
23#include <linux/init.h>
24#include <linux/ioport.h>
25#include <linux/delay.h>
26#include <linux/io.h>
27
28#include <asm/irq.h>
29#include <mach/hardware.h>
30
31#include <asm/mach/pci.h>
32
33static volatile int pci_master_aborts = 0;
34
35static int clear_master_aborts(void);
36
37u32 *
38ixp2000_pci_config_addr(unsigned int bus_nr, unsigned int devfn, int where)
39{
40 u32 *paddress;
41
42 if (PCI_SLOT(devfn) > 7)
43 return 0;
44
45 /* Must be dword aligned */
46 where &= ~3;
47
48 /*
49 * For top bus, generate type 0, else type 1
50 */
51 if (!bus_nr) {
52 /* only bits[23:16] are used for IDSEL */
53 paddress = (u32 *) (IXP2000_PCI_CFG0_VIRT_BASE
54 | (1 << (PCI_SLOT(devfn) + 16))
55 | (PCI_FUNC(devfn) << 8) | where);
56 } else {
57 paddress = (u32 *) (IXP2000_PCI_CFG1_VIRT_BASE
58 | (bus_nr << 16)
59 | (PCI_SLOT(devfn) << 11)
60 | (PCI_FUNC(devfn) << 8) | where);
61 }
62
63 return paddress;
64}
65
66/*
67 * Mask table, bits to mask for quantity of size 1, 2 or 4 bytes.
68 * 0 and 3 are not valid indexes...
69 */
70static u32 bytemask[] = {
71 /*0*/ 0,
72 /*1*/ 0xff,
73 /*2*/ 0xffff,
74 /*3*/ 0,
75 /*4*/ 0xffffffff,
76};
77
78
79int ixp2000_pci_read_config(struct pci_bus *bus, unsigned int devfn, int where,
80 int size, u32 *value)
81{
82 u32 n;
83 u32 *addr;
84
85 n = where % 4;
86
87 addr = ixp2000_pci_config_addr(bus->number, devfn, where);
88 if (!addr)
89 return PCIBIOS_DEVICE_NOT_FOUND;
90
91 pci_master_aborts = 0;
92 *value = (*addr >> (8*n)) & bytemask[size];
93 if (pci_master_aborts) {
94 pci_master_aborts = 0;
95 *value = 0xffffffff;
96 return PCIBIOS_DEVICE_NOT_FOUND;
97 }
98
99 return PCIBIOS_SUCCESSFUL;
100}
101
102/*
103 * We don't do error checks by calling clear_master_aborts() b/c the
104 * assumption is that the caller did a read first to make sure a device
105 * exists.
106 */
107int ixp2000_pci_write_config(struct pci_bus *bus, unsigned int devfn, int where,
108 int size, u32 value)
109{
110 u32 mask;
111 u32 *addr;
112 u32 temp;
113
114 mask = ~(bytemask[size] << ((where % 0x4) * 8));
115 addr = ixp2000_pci_config_addr(bus->number, devfn, where);
116 if (!addr)
117 return PCIBIOS_DEVICE_NOT_FOUND;
118 temp = (u32) (value) << ((where % 0x4) * 8);
119 *addr = (*addr & mask) | temp;
120
121 clear_master_aborts();
122
123 return PCIBIOS_SUCCESSFUL;
124}
125
126
127static struct pci_ops ixp2000_pci_ops = {
128 .read = ixp2000_pci_read_config,
129 .write = ixp2000_pci_write_config
130};
131
132struct pci_bus *ixp2000_pci_scan_bus(int nr, struct pci_sys_data *sysdata)
133{
134 return pci_scan_root_bus(NULL, sysdata->busnr, &ixp2000_pci_ops,
135 sysdata, &sysdata->resources);
136}
137
138
139int ixp2000_pci_abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
140{
141
142 volatile u32 temp;
143 unsigned long flags;
144
145 pci_master_aborts = 1;
146
147 local_irq_save(flags);
148 temp = *(IXP2000_PCI_CONTROL);
149 if (temp & ((1 << 8) | (1 << 5))) {
150 ixp2000_reg_wrb(IXP2000_PCI_CONTROL, temp);
151 }
152
153 temp = *(IXP2000_PCI_CMDSTAT);
154 if (temp & (1 << 29)) {
155 while (temp & (1 << 29)) {
156 ixp2000_reg_write(IXP2000_PCI_CMDSTAT, temp);
157 temp = *(IXP2000_PCI_CMDSTAT);
158 }
159 }
160 local_irq_restore(flags);
161
162 /*
163 * If it was an imprecise abort, then we need to correct the
164 * return address to be _after_ the instruction.
165 */
166 if (fsr & (1 << 10))
167 regs->ARM_pc += 4;
168
169 return 0;
170}
171
172int
173clear_master_aborts(void)
174{
175 volatile u32 temp;
176 unsigned long flags;
177
178 local_irq_save(flags);
179 temp = *(IXP2000_PCI_CONTROL);
180 if (temp & ((1 << 8) | (1 << 5))) {
181 ixp2000_reg_wrb(IXP2000_PCI_CONTROL, temp);
182 }
183
184 temp = *(IXP2000_PCI_CMDSTAT);
185 if (temp & (1 << 29)) {
186 while (temp & (1 << 29)) {
187 ixp2000_reg_write(IXP2000_PCI_CMDSTAT, temp);
188 temp = *(IXP2000_PCI_CMDSTAT);
189 }
190 }
191 local_irq_restore(flags);
192
193 return 0;
194}
195
196void __init
197ixp2000_pci_preinit(void)
198{
199 pci_set_flags(0);
200
201 pcibios_min_io = 0;
202 pcibios_min_mem = 0;
203
204#ifndef CONFIG_IXP2000_SUPPORT_BROKEN_PCI_IO
205 /*
206 * Configure the PCI unit to properly byteswap I/O transactions,
207 * and verify that it worked.
208 */
209 ixp2000_reg_write(IXP2000_PCI_CONTROL,
210 (*IXP2000_PCI_CONTROL | PCI_CONTROL_IEE));
211
212 if ((*IXP2000_PCI_CONTROL & PCI_CONTROL_IEE) == 0)
213 panic("IXP2000: PCI I/O is broken on this ixp model, and "
214 "the needed workaround has not been configured in");
215#endif
216
217 hook_fault_code(16+6, ixp2000_pci_abort_handler, SIGBUS, 0,
218 "PCI config cycle to non-existent device");
219}
220
221
222/*
223 * IXP2000 systems often have large resource requirements, so we just
224 * use our own resource space.
225 */
226static struct resource ixp2000_pci_mem_space = {
227 .start = 0xe0000000,
228 .end = 0xffffffff,
229 .flags = IORESOURCE_MEM,
230 .name = "PCI Mem Space"
231};
232
233static struct resource ixp2000_pci_io_space = {
234 .start = 0x00010000,
235 .end = 0x0001ffff,
236 .flags = IORESOURCE_IO,
237 .name = "PCI I/O Space"
238};
239
240int ixp2000_pci_setup(int nr, struct pci_sys_data *sys)
241{
242 if (nr >= 1)
243 return 0;
244
245 pci_add_resource_offset(&sys->resources,
246 &ixp2000_pci_io_space, sys->io_offset);
247 pci_add_resource_offset(&sys->resources,
248 &ixp2000_pci_mem_space, sys->mem_offset);
249
250 return 1;
251}
252
diff --git a/arch/arm/mach-ixp23xx/Kconfig b/arch/arm/mach-ixp23xx/Kconfig
deleted file mode 100644
index 982670ec3866..000000000000
--- a/arch/arm/mach-ixp23xx/Kconfig
+++ /dev/null
@@ -1,25 +0,0 @@
1if ARCH_IXP23XX
2
3config ARCH_SUPPORTS_BIG_ENDIAN
4 bool
5 default y
6
7menu "Intel IXP23xx Implementation Options"
8
9comment "IXP23xx Platforms"
10
11config MACH_ESPRESSO
12 bool "Support IP Fabrics Double Espresso platform"
13 help
14
15config MACH_IXDP2351
16 bool "Support Intel IXDP2351 platform"
17 help
18
19config MACH_ROADRUNNER
20 bool "Support ADI RoadRunner platform"
21 help
22
23endmenu
24
25endif
diff --git a/arch/arm/mach-ixp23xx/Makefile b/arch/arm/mach-ixp23xx/Makefile
deleted file mode 100644
index 288b371b6d03..000000000000
--- a/arch/arm/mach-ixp23xx/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
1#
2# Makefile for the linux kernel.
3#
4obj-y := core.o pci.o
5obj-m :=
6obj-n :=
7obj- :=
8
9obj-$(CONFIG_MACH_ESPRESSO) += espresso.o
10obj-$(CONFIG_MACH_IXDP2351) += ixdp2351.o
11obj-$(CONFIG_MACH_ROADRUNNER) += roadrunner.o
diff --git a/arch/arm/mach-ixp23xx/Makefile.boot b/arch/arm/mach-ixp23xx/Makefile.boot
deleted file mode 100644
index 44fb4a717c3f..000000000000
--- a/arch/arm/mach-ixp23xx/Makefile.boot
+++ /dev/null
@@ -1,2 +0,0 @@
1 zreladdr-y += 0x00008000
2params_phys-y := 0x00000100
diff --git a/arch/arm/mach-ixp23xx/core.c b/arch/arm/mach-ixp23xx/core.c
deleted file mode 100644
index d34542425990..000000000000
--- a/arch/arm/mach-ixp23xx/core.c
+++ /dev/null
@@ -1,455 +0,0 @@
1/*
2 * arch/arm/mach-ixp23xx/core.c
3 *
4 * Core routines for IXP23xx chips
5 *
6 * Author: Deepak Saxena <dsaxena@plexity.net>
7 *
8 * Copyright 2005 (c) MontaVista Software, Inc.
9 *
10 * Based on 2.4 code Copyright 2004 (c) Intel Corporation
11 *
12 * This file is licensed under the terms of the GNU General Public
13 * License version 2. This program is licensed "as is" without any
14 * warranty of any kind, whether express or implied.
15 */
16
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/spinlock.h>
20#include <linux/sched.h>
21#include <linux/interrupt.h>
22#include <linux/serial.h>
23#include <linux/tty.h>
24#include <linux/bitops.h>
25#include <linux/serial_8250.h>
26#include <linux/serial_core.h>
27#include <linux/device.h>
28#include <linux/mm.h>
29#include <linux/time.h>
30#include <linux/timex.h>
31
32#include <asm/types.h>
33#include <asm/setup.h>
34#include <asm/memory.h>
35#include <mach/hardware.h>
36#include <asm/irq.h>
37#include <asm/tlbflush.h>
38#include <asm/pgtable.h>
39#include <asm/system_misc.h>
40
41#include <asm/mach/map.h>
42#include <asm/mach/time.h>
43#include <asm/mach/irq.h>
44#include <asm/mach/arch.h>
45
46
47/*************************************************************************
48 * Chip specific mappings shared by all IXP23xx systems
49 *************************************************************************/
50static struct map_desc ixp23xx_io_desc[] __initdata = {
51 { /* XSI-CPP CSRs */
52 .virtual = IXP23XX_XSI2CPP_CSR_VIRT,
53 .pfn = __phys_to_pfn(IXP23XX_XSI2CPP_CSR_PHYS),
54 .length = IXP23XX_XSI2CPP_CSR_SIZE,
55 .type = MT_DEVICE,
56 }, { /* Expansion Bus Config */
57 .virtual = IXP23XX_EXP_CFG_VIRT,
58 .pfn = __phys_to_pfn(IXP23XX_EXP_CFG_PHYS),
59 .length = IXP23XX_EXP_CFG_SIZE,
60 .type = MT_DEVICE,
61 }, { /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACS,.... */
62 .virtual = IXP23XX_PERIPHERAL_VIRT,
63 .pfn = __phys_to_pfn(IXP23XX_PERIPHERAL_PHYS),
64 .length = IXP23XX_PERIPHERAL_SIZE,
65 .type = MT_DEVICE,
66 }, { /* CAP CSRs */
67 .virtual = IXP23XX_CAP_CSR_VIRT,
68 .pfn = __phys_to_pfn(IXP23XX_CAP_CSR_PHYS),
69 .length = IXP23XX_CAP_CSR_SIZE,
70 .type = MT_DEVICE,
71 }, { /* MSF CSRs */
72 .virtual = IXP23XX_MSF_CSR_VIRT,
73 .pfn = __phys_to_pfn(IXP23XX_MSF_CSR_PHYS),
74 .length = IXP23XX_MSF_CSR_SIZE,
75 .type = MT_DEVICE,
76 }, { /* PCI I/O Space */
77 .virtual = IXP23XX_PCI_IO_VIRT,
78 .pfn = __phys_to_pfn(IXP23XX_PCI_IO_PHYS),
79 .length = IXP23XX_PCI_IO_SIZE,
80 .type = MT_DEVICE,
81 }, { /* PCI Config Space */
82 .virtual = IXP23XX_PCI_CFG_VIRT,
83 .pfn = __phys_to_pfn(IXP23XX_PCI_CFG_PHYS),
84 .length = IXP23XX_PCI_CFG_SIZE,
85 .type = MT_DEVICE,
86 }, { /* PCI local CFG CSRs */
87 .virtual = IXP23XX_PCI_CREG_VIRT,
88 .pfn = __phys_to_pfn(IXP23XX_PCI_CREG_PHYS),
89 .length = IXP23XX_PCI_CREG_SIZE,
90 .type = MT_DEVICE,
91 }, { /* PCI MEM Space */
92 .virtual = IXP23XX_PCI_MEM_VIRT,
93 .pfn = __phys_to_pfn(IXP23XX_PCI_MEM_PHYS),
94 .length = IXP23XX_PCI_MEM_SIZE,
95 .type = MT_DEVICE,
96 }
97};
98
99void __init ixp23xx_map_io(void)
100{
101 iotable_init(ixp23xx_io_desc, ARRAY_SIZE(ixp23xx_io_desc));
102}
103
104
105/***************************************************************************
106 * IXP23xx Interrupt Handling
107 ***************************************************************************/
108enum ixp23xx_irq_type {
109 IXP23XX_IRQ_LEVEL, IXP23XX_IRQ_EDGE
110};
111
112static void ixp23xx_config_irq(unsigned int, enum ixp23xx_irq_type);
113
114static int ixp23xx_irq_set_type(struct irq_data *d, unsigned int type)
115{
116 int line = d->irq - IRQ_IXP23XX_GPIO6 + 6;
117 u32 int_style;
118 enum ixp23xx_irq_type irq_type;
119 volatile u32 *int_reg;
120
121 /*
122 * Only GPIOs 6-15 are wired to interrupts on IXP23xx
123 */
124 if (line < 6 || line > 15)
125 return -EINVAL;
126
127 switch (type) {
128 case IRQ_TYPE_EDGE_BOTH:
129 int_style = IXP23XX_GPIO_STYLE_TRANSITIONAL;
130 irq_type = IXP23XX_IRQ_EDGE;
131 break;
132 case IRQ_TYPE_EDGE_RISING:
133 int_style = IXP23XX_GPIO_STYLE_RISING_EDGE;
134 irq_type = IXP23XX_IRQ_EDGE;
135 break;
136 case IRQ_TYPE_EDGE_FALLING:
137 int_style = IXP23XX_GPIO_STYLE_FALLING_EDGE;
138 irq_type = IXP23XX_IRQ_EDGE;
139 break;
140 case IRQ_TYPE_LEVEL_HIGH:
141 int_style = IXP23XX_GPIO_STYLE_ACTIVE_HIGH;
142 irq_type = IXP23XX_IRQ_LEVEL;
143 break;
144 case IRQ_TYPE_LEVEL_LOW:
145 int_style = IXP23XX_GPIO_STYLE_ACTIVE_LOW;
146 irq_type = IXP23XX_IRQ_LEVEL;
147 break;
148 default:
149 return -EINVAL;
150 }
151
152 ixp23xx_config_irq(d->irq, irq_type);
153
154 if (line >= 8) { /* pins 8-15 */
155 line -= 8;
156 int_reg = (volatile u32 *)IXP23XX_GPIO_GPIT2R;
157 } else { /* pins 0-7 */
158 int_reg = (volatile u32 *)IXP23XX_GPIO_GPIT1R;
159 }
160
161 /*
162 * Clear pending interrupts
163 */
164 *IXP23XX_GPIO_GPISR = (1 << line);
165
166 /* Clear the style for the appropriate pin */
167 *int_reg &= ~(IXP23XX_GPIO_STYLE_MASK <<
168 (line * IXP23XX_GPIO_STYLE_SIZE));
169
170 /* Set the new style */
171 *int_reg |= (int_style << (line * IXP23XX_GPIO_STYLE_SIZE));
172
173 return 0;
174}
175
176static void ixp23xx_irq_mask(struct irq_data *d)
177{
178 volatile unsigned long *intr_reg;
179 unsigned int irq = d->irq;
180
181 if (irq >= 56)
182 irq += 8;
183
184 intr_reg = IXP23XX_INTR_EN1 + (irq / 32);
185 *intr_reg &= ~(1 << (irq % 32));
186}
187
188static void ixp23xx_irq_ack(struct irq_data *d)
189{
190 int line = d->irq - IRQ_IXP23XX_GPIO6 + 6;
191
192 if ((line < 6) || (line > 15))
193 return;
194
195 *IXP23XX_GPIO_GPISR = (1 << line);
196}
197
198/*
199 * Level triggered interrupts on GPIO lines can only be cleared when the
200 * interrupt condition disappears.
201 */
202static void ixp23xx_irq_level_unmask(struct irq_data *d)
203{
204 volatile unsigned long *intr_reg;
205 unsigned int irq = d->irq;
206
207 ixp23xx_irq_ack(d);
208
209 if (irq >= 56)
210 irq += 8;
211
212 intr_reg = IXP23XX_INTR_EN1 + (irq / 32);
213 *intr_reg |= (1 << (irq % 32));
214}
215
216static void ixp23xx_irq_edge_unmask(struct irq_data *d)
217{
218 volatile unsigned long *intr_reg;
219 unsigned int irq = d->irq;
220
221 if (irq >= 56)
222 irq += 8;
223
224 intr_reg = IXP23XX_INTR_EN1 + (irq / 32);
225 *intr_reg |= (1 << (irq % 32));
226}
227
228static struct irq_chip ixp23xx_irq_level_chip = {
229 .irq_ack = ixp23xx_irq_mask,
230 .irq_mask = ixp23xx_irq_mask,
231 .irq_unmask = ixp23xx_irq_level_unmask,
232 .irq_set_type = ixp23xx_irq_set_type
233};
234
235static struct irq_chip ixp23xx_irq_edge_chip = {
236 .irq_ack = ixp23xx_irq_ack,
237 .irq_mask = ixp23xx_irq_mask,
238 .irq_unmask = ixp23xx_irq_edge_unmask,
239 .irq_set_type = ixp23xx_irq_set_type
240};
241
242static void ixp23xx_pci_irq_mask(struct irq_data *d)
243{
244 unsigned int irq = d->irq;
245
246 *IXP23XX_PCI_XSCALE_INT_ENABLE &= ~(1 << (IRQ_IXP23XX_INTA + 27 - irq));
247}
248
249static void ixp23xx_pci_irq_unmask(struct irq_data *d)
250{
251 unsigned int irq = d->irq;
252
253 *IXP23XX_PCI_XSCALE_INT_ENABLE |= (1 << (IRQ_IXP23XX_INTA + 27 - irq));
254}
255
256/*
257 * TODO: Should this just be done at ASM level?
258 */
259static void pci_handler(unsigned int irq, struct irq_desc *desc)
260{
261 u32 pci_interrupt;
262 unsigned int irqno;
263
264 pci_interrupt = *IXP23XX_PCI_XSCALE_INT_STATUS;
265
266 desc->irq_data.chip->irq_ack(&desc->irq_data);
267
268 /* See which PCI_INTA, or PCI_INTB interrupted */
269 if (pci_interrupt & (1 << 26)) {
270 irqno = IRQ_IXP23XX_INTB;
271 } else if (pci_interrupt & (1 << 27)) {
272 irqno = IRQ_IXP23XX_INTA;
273 } else {
274 BUG();
275 }
276
277 generic_handle_irq(irqno);
278
279 desc->irq_data.chip->irq_unmask(&desc->irq_data);
280}
281
282static struct irq_chip ixp23xx_pci_irq_chip = {
283 .irq_ack = ixp23xx_pci_irq_mask,
284 .irq_mask = ixp23xx_pci_irq_mask,
285 .irq_unmask = ixp23xx_pci_irq_unmask
286};
287
288static void ixp23xx_config_irq(unsigned int irq, enum ixp23xx_irq_type type)
289{
290 switch (type) {
291 case IXP23XX_IRQ_LEVEL:
292 irq_set_chip_and_handler(irq, &ixp23xx_irq_level_chip,
293 handle_level_irq);
294 break;
295 case IXP23XX_IRQ_EDGE:
296 irq_set_chip_and_handler(irq, &ixp23xx_irq_edge_chip,
297 handle_edge_irq);
298 break;
299 }
300 set_irq_flags(irq, IRQF_VALID);
301}
302
303void __init ixp23xx_init_irq(void)
304{
305 int irq;
306
307 /* Route everything to IRQ */
308 *IXP23XX_INTR_SEL1 = 0x0;
309 *IXP23XX_INTR_SEL2 = 0x0;
310 *IXP23XX_INTR_SEL3 = 0x0;
311 *IXP23XX_INTR_SEL4 = 0x0;
312
313 /* Mask all sources */
314 *IXP23XX_INTR_EN1 = 0x0;
315 *IXP23XX_INTR_EN2 = 0x0;
316 *IXP23XX_INTR_EN3 = 0x0;
317 *IXP23XX_INTR_EN4 = 0x0;
318
319 /*
320 * Configure all IRQs for level-sensitive operation
321 */
322 for (irq = 0; irq <= NUM_IXP23XX_RAW_IRQS; irq++) {
323 ixp23xx_config_irq(irq, IXP23XX_IRQ_LEVEL);
324 }
325
326 for (irq = IRQ_IXP23XX_INTA; irq <= IRQ_IXP23XX_INTB; irq++) {
327 irq_set_chip_and_handler(irq, &ixp23xx_pci_irq_chip,
328 handle_level_irq);
329 set_irq_flags(irq, IRQF_VALID);
330 }
331
332 irq_set_chained_handler(IRQ_IXP23XX_PCI_INT_RPH, pci_handler);
333}
334
335
336/*************************************************************************
337 * Timer-tick functions for IXP23xx
338 *************************************************************************/
339#define CLOCK_TICKS_PER_USEC (CLOCK_TICK_RATE / USEC_PER_SEC)
340
341static unsigned long next_jiffy_time;
342
343static unsigned long
344ixp23xx_gettimeoffset(void)
345{
346 unsigned long elapsed;
347
348 elapsed = *IXP23XX_TIMER_CONT - (next_jiffy_time - LATCH);
349
350 return elapsed / CLOCK_TICKS_PER_USEC;
351}
352
353static irqreturn_t
354ixp23xx_timer_interrupt(int irq, void *dev_id)
355{
356 /* Clear Pending Interrupt by writing '1' to it */
357 *IXP23XX_TIMER_STATUS = IXP23XX_TIMER1_INT_PEND;
358 while ((signed long)(*IXP23XX_TIMER_CONT - next_jiffy_time) >= LATCH) {
359 timer_tick();
360 next_jiffy_time += LATCH;
361 }
362
363 return IRQ_HANDLED;
364}
365
366static struct irqaction ixp23xx_timer_irq = {
367 .name = "IXP23xx Timer Tick",
368 .handler = ixp23xx_timer_interrupt,
369 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
370};
371
372void __init ixp23xx_init_timer(void)
373{
374 /* Clear Pending Interrupt by writing '1' to it */
375 *IXP23XX_TIMER_STATUS = IXP23XX_TIMER1_INT_PEND;
376
377 /* Setup the Timer counter value */
378 *IXP23XX_TIMER1_RELOAD =
379 (LATCH & ~IXP23XX_TIMER_RELOAD_MASK) | IXP23XX_TIMER_ENABLE;
380
381 *IXP23XX_TIMER_CONT = 0;
382 next_jiffy_time = LATCH;
383
384 /* Connect the interrupt handler and enable the interrupt */
385 setup_irq(IRQ_IXP23XX_TIMER1, &ixp23xx_timer_irq);
386}
387
388struct sys_timer ixp23xx_timer = {
389 .init = ixp23xx_init_timer,
390 .offset = ixp23xx_gettimeoffset,
391};
392
393
394/*************************************************************************
395 * IXP23xx Platform Initialization
396 *************************************************************************/
397static struct resource ixp23xx_uart_resources[] = {
398 {
399 .start = IXP23XX_UART1_PHYS,
400 .end = IXP23XX_UART1_PHYS + 0x0fff,
401 .flags = IORESOURCE_MEM
402 }, {
403 .start = IXP23XX_UART2_PHYS,
404 .end = IXP23XX_UART2_PHYS + 0x0fff,
405 .flags = IORESOURCE_MEM
406 }
407};
408
409static struct plat_serial8250_port ixp23xx_uart_data[] = {
410 {
411 .mapbase = IXP23XX_UART1_PHYS,
412 .membase = (char *)(IXP23XX_UART1_VIRT + 3),
413 .irq = IRQ_IXP23XX_UART1,
414 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
415 .iotype = UPIO_MEM,
416 .regshift = 2,
417 .uartclk = IXP23XX_UART_XTAL,
418 }, {
419 .mapbase = IXP23XX_UART2_PHYS,
420 .membase = (char *)(IXP23XX_UART2_VIRT + 3),
421 .irq = IRQ_IXP23XX_UART2,
422 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
423 .iotype = UPIO_MEM,
424 .regshift = 2,
425 .uartclk = IXP23XX_UART_XTAL,
426 },
427 { },
428};
429
430static struct platform_device ixp23xx_uart = {
431 .name = "serial8250",
432 .id = 0,
433 .dev.platform_data = ixp23xx_uart_data,
434 .num_resources = 2,
435 .resource = ixp23xx_uart_resources,
436};
437
438static struct platform_device *ixp23xx_devices[] __initdata = {
439 &ixp23xx_uart,
440};
441
442void __init ixp23xx_sys_init(void)
443{
444 /* by default, the idle code is disabled */
445 disable_hlt();
446
447 *IXP23XX_EXP_UNIT_FUSE |= 0xf;
448 platform_add_devices(ixp23xx_devices, ARRAY_SIZE(ixp23xx_devices));
449}
450
451void ixp23xx_restart(char mode, const char *cmd)
452{
453 /* Use on-chip reset capability */
454 *IXP23XX_RESET0 |= IXP23XX_RST_ALL;
455}
diff --git a/arch/arm/mach-ixp23xx/espresso.c b/arch/arm/mach-ixp23xx/espresso.c
deleted file mode 100644
index d142d45dea12..000000000000
--- a/arch/arm/mach-ixp23xx/espresso.c
+++ /dev/null
@@ -1,93 +0,0 @@
1/*
2 * arch/arm/mach-ixp23xx/espresso.c
3 *
4 * Double Espresso-specific routines
5 *
6 * Author: Lennert Buytenhek <buytenh@wantstofly.org>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/spinlock.h>
16#include <linux/sched.h>
17#include <linux/interrupt.h>
18#include <linux/serial.h>
19#include <linux/tty.h>
20#include <linux/bitops.h>
21#include <linux/ioport.h>
22#include <linux/serial_8250.h>
23#include <linux/serial_core.h>
24#include <linux/device.h>
25#include <linux/mm.h>
26#include <linux/pci.h>
27#include <linux/mtd/physmap.h>
28
29#include <asm/types.h>
30#include <asm/setup.h>
31#include <asm/memory.h>
32#include <mach/hardware.h>
33#include <asm/mach-types.h>
34#include <asm/irq.h>
35#include <asm/tlbflush.h>
36#include <asm/pgtable.h>
37
38#include <asm/mach/map.h>
39#include <asm/mach/irq.h>
40#include <asm/mach/arch.h>
41#include <asm/mach/pci.h>
42
43static int __init espresso_pci_init(void)
44{
45 if (machine_is_espresso())
46 ixp23xx_pci_slave_init();
47
48 return 0;
49};
50subsys_initcall(espresso_pci_init);
51
52static struct physmap_flash_data espresso_flash_data = {
53 .width = 2,
54};
55
56static struct resource espresso_flash_resource = {
57 .start = 0x90000000,
58 .end = 0x91ffffff,
59 .flags = IORESOURCE_MEM,
60};
61
62static struct platform_device espresso_flash = {
63 .name = "physmap-flash",
64 .id = 0,
65 .dev = {
66 .platform_data = &espresso_flash_data,
67 },
68 .num_resources = 1,
69 .resource = &espresso_flash_resource,
70};
71
72static void __init espresso_init(void)
73{
74 platform_device_register(&espresso_flash);
75
76 /*
77 * Mark flash as writeable.
78 */
79 IXP23XX_EXP_CS0[0] |= IXP23XX_FLASH_WRITABLE;
80 IXP23XX_EXP_CS0[1] |= IXP23XX_FLASH_WRITABLE;
81
82 ixp23xx_sys_init();
83}
84
85MACHINE_START(ESPRESSO, "IP Fabrics Double Espresso")
86 /* Maintainer: Lennert Buytenhek */
87 .map_io = ixp23xx_map_io,
88 .init_irq = ixp23xx_init_irq,
89 .timer = &ixp23xx_timer,
90 .atag_offset = 0x100,
91 .init_machine = espresso_init,
92 .restart = ixp23xx_restart,
93MACHINE_END
diff --git a/arch/arm/mach-ixp23xx/include/mach/debug-macro.S b/arch/arm/mach-ixp23xx/include/mach/debug-macro.S
deleted file mode 100644
index 5ff524c13744..000000000000
--- a/arch/arm/mach-ixp23xx/include/mach/debug-macro.S
+++ /dev/null
@@ -1,25 +0,0 @@
1/*
2 * arch/arm/mach-ixp23xx/include/mach/debug-macro.S
3 *
4 * Debugging macro include header
5 *
6 * Copyright (C) 1994-1999 Russell King
7 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#include <mach/ixp23xx.h>
14
15 .macro addruart, rp, rv, tmp
16 ldr \rp, =IXP23XX_PERIPHERAL_PHYS @ physical
17 ldr \rv, =IXP23XX_PERIPHERAL_VIRT @ virtual
18#ifdef __ARMEB__
19 orr \rp, \rp, #0x00000003
20 orr \rv, \rv, #0x00000003
21#endif
22 .endm
23
24#define UART_SHIFT 2
25#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-ixp23xx/include/mach/entry-macro.S b/arch/arm/mach-ixp23xx/include/mach/entry-macro.S
deleted file mode 100644
index 3fd2cb984e42..000000000000
--- a/arch/arm/mach-ixp23xx/include/mach/entry-macro.S
+++ /dev/null
@@ -1,31 +0,0 @@
1/*
2 * arch/arm/mach-ixp23xx/include/mach/entry-macro.S
3 */
4
5 .macro get_irqnr_preamble, base, tmp
6 .endm
7
8 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
9 ldr \irqnr, =(IXP23XX_INTC_VIRT + IXP23XX_INTR_IRQ_ENC_ST_OFFSET)
10 ldr \irqnr, [\irqnr] @ get interrupt number
11 cmp \irqnr, #0x0 @ spurious interrupt ?
12 movne \irqnr, \irqnr, lsr #2 @ skip unwanted low order bits
13 subne \irqnr, \irqnr, #1 @ convert to 0 based
14
15#if 0
16 cmp \irqnr, #IRQ_IXP23XX_PCI_INT_RPH
17 bne 1001f
18 mov \irqnr, #IRQ_IXP23XX_INTA
19
20 ldr \irqnr, =0xf5000030
21
22 mov \tmp, #(1<<26)
23 tst \irqnr, \tmp
24 movne \irqnr, #IRQ_IXP23XX_INTB
25
26 mov \tmp, #(1<<27)
27 tst \irqnr, \tmp
28 movne \irqnr, #IRQ_IXP23XX_INTA
291001:
30#endif
31 .endm
diff --git a/arch/arm/mach-ixp23xx/include/mach/hardware.h b/arch/arm/mach-ixp23xx/include/mach/hardware.h
deleted file mode 100644
index 60e55fa10238..000000000000
--- a/arch/arm/mach-ixp23xx/include/mach/hardware.h
+++ /dev/null
@@ -1,32 +0,0 @@
1/*
2 * arch/arm/mach-ixp23xx/include/mach/hardware.h
3 *
4 * Copyright (C) 2002-2004 Intel Corporation.
5 * Copyricht (C) 2005 MontaVista Software, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Hardware definitions for IXP23XX based systems
12 */
13
14#ifndef __ASM_ARCH_HARDWARE_H
15#define __ASM_ARCH_HARDWARE_H
16
17/* PCI IO info */
18
19#include "ixp23xx.h"
20
21/*
22 * Platform helper functions
23 */
24#include "platform.h"
25
26/*
27 * Platform-specific headers
28 */
29#include "ixdp2351.h"
30
31
32#endif
diff --git a/arch/arm/mach-ixp23xx/include/mach/io.h b/arch/arm/mach-ixp23xx/include/mach/io.h
deleted file mode 100644
index a7aceb55c130..000000000000
--- a/arch/arm/mach-ixp23xx/include/mach/io.h
+++ /dev/null
@@ -1,22 +0,0 @@
1/*
2 * arch/arm/mach-ixp23xx/include/mach/io.h
3 *
4 * Original Author: Naeem M Afzal <naeem.m.afzal@intel.com>
5 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
6 *
7 * Copyright (C) 2003-2005 Intel Corp.
8 * Copyright (C) 2005 MontaVista Software, Inc
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#ifndef __ASM_ARCH_IO_H
16#define __ASM_ARCH_IO_H
17
18#define IO_SPACE_LIMIT 0xffffffff
19
20#define __io(p) ((void __iomem*)((p) + IXP23XX_PCI_IO_VIRT))
21
22#endif
diff --git a/arch/arm/mach-ixp23xx/include/mach/irqs.h b/arch/arm/mach-ixp23xx/include/mach/irqs.h
deleted file mode 100644
index 3af33a04b8a2..000000000000
--- a/arch/arm/mach-ixp23xx/include/mach/irqs.h
+++ /dev/null
@@ -1,223 +0,0 @@
1/*
2 * arch/arm/mach-ixp23xx/include/mach/irqs.h
3 *
4 * IRQ definitions for IXP23XX based systems
5 *
6 * Author: Naeem Afzal <naeem.m.afzal@intel.com>
7 *
8 * Copyright (C) 2003-2004 Intel Corporation.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#ifndef __ASM_ARCH_IRQS_H
16#define __ASM_ARCH_IRQS_H
17
18#define NR_IXP23XX_IRQS IRQ_IXP23XX_INTB+1
19#define IRQ_IXP23XX_EXTIRQS NR_IXP23XX_IRQS
20
21
22#define IRQ_IXP23XX_DBG0 0 /* Debug/Execution/MBox */
23#define IRQ_IXP23XX_DBG1 1 /* Debug/Execution/MBox */
24#define IRQ_IXP23XX_NPE_TRG 2 /* npe_trigger */
25#define IRQ_IXP23XX_TIMER1 3 /* Timer[0] */
26#define IRQ_IXP23XX_TIMER2 4 /* Timer[1] */
27#define IRQ_IXP23XX_TIMESTAMP 5 /* Timer[2], Time-stamp */
28#define IRQ_IXP23XX_WDOG 6 /* Time[3], Watchdog Timer */
29#define IRQ_IXP23XX_PCI_DBELL 7 /* PCI Doorbell */
30#define IRQ_IXP23XX_PCI_DMA1 8 /* PCI DMA Channel 1 */
31#define IRQ_IXP23XX_PCI_DMA2 9 /* PCI DMA Channel 2 */
32#define IRQ_IXP23XX_PCI_DMA3 10 /* PCI DMA Channel 3 */
33#define IRQ_IXP23XX_PCI_INT_RPH 11 /* pcxg_pci_int_rph */
34#define IRQ_IXP23XX_CPP_PMU 12 /* xpxg_pm_int_rpl */
35#define IRQ_IXP23XX_SWINT0 13 /* S/W Interrupt0 */
36#define IRQ_IXP23XX_SWINT1 14 /* S/W Interrupt1 */
37#define IRQ_IXP23XX_UART2 15 /* UART1 Interrupt */
38#define IRQ_IXP23XX_UART1 16 /* UART0 Interrupt */
39#define IRQ_IXP23XX_XSI_PMU_ROLLOVER 17 /* AHB Performance M. Unit counter rollover */
40#define IRQ_IXP23XX_XSI_AHB_PM0 18 /* intr_pm_o */
41#define IRQ_IXP23XX_XSI_AHB_ECE0 19 /* intr_ece_o */
42#define IRQ_IXP23XX_XSI_AHB_GASKET 20 /* gas_intr_o */
43#define IRQ_IXP23XX_XSI_CPP 21 /* xsi2cpp_int */
44#define IRQ_IXP23XX_CPP_XSI 22 /* cpp2xsi_int */
45#define IRQ_IXP23XX_ME_ATTN0 23 /* ME_ATTN */
46#define IRQ_IXP23XX_ME_ATTN1 24 /* ME_ATTN */
47#define IRQ_IXP23XX_ME_ATTN2 25 /* ME_ATTN */
48#define IRQ_IXP23XX_ME_ATTN3 26 /* ME_ATTN */
49#define IRQ_IXP23XX_PCI_ERR_RPH 27 /* PCXG_PCI_ERR_RPH */
50#define IRQ_IXP23XX_D0XG_ECC_CORR 28 /* D0XG_DRAM_ECC_CORR */
51#define IRQ_IXP23XX_D0XG_ECC_UNCORR 29 /* D0XG_DRAM_ECC_UNCORR */
52#define IRQ_IXP23XX_SRAM_ERR1 30 /* SRAM1_ERR */
53#define IRQ_IXP23XX_SRAM_ERR0 31 /* SRAM0_ERR */
54#define IRQ_IXP23XX_MEDIA_ERR 32 /* MEDIA_ERR */
55#define IRQ_IXP23XX_STH_DRAM_ECC_MAJ 33 /* STH_DRAM0_ECC_MAJ */
56#define IRQ_IXP23XX_GPIO6 34 /* GPIO0 interrupts */
57#define IRQ_IXP23XX_GPIO7 35 /* GPIO1 interrupts */
58#define IRQ_IXP23XX_GPIO8 36 /* GPIO2 interrupts */
59#define IRQ_IXP23XX_GPIO9 37 /* GPIO3 interrupts */
60#define IRQ_IXP23XX_GPIO10 38 /* GPIO4 interrupts */
61#define IRQ_IXP23XX_GPIO11 39 /* GPIO5 interrupts */
62#define IRQ_IXP23XX_GPIO12 40 /* GPIO6 interrupts */
63#define IRQ_IXP23XX_GPIO13 41 /* GPIO7 interrupts */
64#define IRQ_IXP23XX_GPIO14 42 /* GPIO8 interrupts */
65#define IRQ_IXP23XX_GPIO15 43 /* GPIO9 interrupts */
66#define IRQ_IXP23XX_SHAC_RING0 44 /* SHAC Ring Full */
67#define IRQ_IXP23XX_SHAC_RING1 45 /* SHAC Ring Full */
68#define IRQ_IXP23XX_SHAC_RING2 46 /* SHAC Ring Full */
69#define IRQ_IXP23XX_SHAC_RING3 47 /* SHAC Ring Full */
70#define IRQ_IXP23XX_SHAC_RING4 48 /* SHAC Ring Full */
71#define IRQ_IXP23XX_SHAC_RING5 49 /* SHAC Ring Full */
72#define IRQ_IXP23XX_SHAC_RING6 50 /* SHAC RING Full */
73#define IRQ_IXP23XX_SHAC_RING7 51 /* SHAC Ring Full */
74#define IRQ_IXP23XX_SHAC_RING8 52 /* SHAC Ring Full */
75#define IRQ_IXP23XX_SHAC_RING9 53 /* SHAC Ring Full */
76#define IRQ_IXP23XX_SHAC_RING10 54 /* SHAC Ring Full */
77#define IRQ_IXP23XX_SHAC_RING11 55 /* SHAC Ring Full */
78#define IRQ_IXP23XX_ME_THREAD_A0_ME0 56 /* ME_THREAD_A */
79#define IRQ_IXP23XX_ME_THREAD_A1_ME0 57 /* ME_THREAD_A */
80#define IRQ_IXP23XX_ME_THREAD_A2_ME0 58 /* ME_THREAD_A */
81#define IRQ_IXP23XX_ME_THREAD_A3_ME0 59 /* ME_THREAD_A */
82#define IRQ_IXP23XX_ME_THREAD_A4_ME0 60 /* ME_THREAD_A */
83#define IRQ_IXP23XX_ME_THREAD_A5_ME0 61 /* ME_THREAD_A */
84#define IRQ_IXP23XX_ME_THREAD_A6_ME0 62 /* ME_THREAD_A */
85#define IRQ_IXP23XX_ME_THREAD_A7_ME0 63 /* ME_THREAD_A */
86#define IRQ_IXP23XX_ME_THREAD_A8_ME1 64 /* ME_THREAD_A */
87#define IRQ_IXP23XX_ME_THREAD_A9_ME1 65 /* ME_THREAD_A */
88#define IRQ_IXP23XX_ME_THREAD_A10_ME1 66 /* ME_THREAD_A */
89#define IRQ_IXP23XX_ME_THREAD_A11_ME1 67 /* ME_THREAD_A */
90#define IRQ_IXP23XX_ME_THREAD_A12_ME1 68 /* ME_THREAD_A */
91#define IRQ_IXP23XX_ME_THREAD_A13_ME1 69 /* ME_THREAD_A */
92#define IRQ_IXP23XX_ME_THREAD_A14_ME1 70 /* ME_THREAD_A */
93#define IRQ_IXP23XX_ME_THREAD_A15_ME1 71 /* ME_THREAD_A */
94#define IRQ_IXP23XX_ME_THREAD_A16_ME2 72 /* ME_THREAD_A */
95#define IRQ_IXP23XX_ME_THREAD_A17_ME2 73 /* ME_THREAD_A */
96#define IRQ_IXP23XX_ME_THREAD_A18_ME2 74 /* ME_THREAD_A */
97#define IRQ_IXP23XX_ME_THREAD_A19_ME2 75 /* ME_THREAD_A */
98#define IRQ_IXP23XX_ME_THREAD_A20_ME2 76 /* ME_THREAD_A */
99#define IRQ_IXP23XX_ME_THREAD_A21_ME2 77 /* ME_THREAD_A */
100#define IRQ_IXP23XX_ME_THREAD_A22_ME2 78 /* ME_THREAD_A */
101#define IRQ_IXP23XX_ME_THREAD_A23_ME2 79 /* ME_THREAD_A */
102#define IRQ_IXP23XX_ME_THREAD_A24_ME3 80 /* ME_THREAD_A */
103#define IRQ_IXP23XX_ME_THREAD_A25_ME3 81 /* ME_THREAD_A */
104#define IRQ_IXP23XX_ME_THREAD_A26_ME3 82 /* ME_THREAD_A */
105#define IRQ_IXP23XX_ME_THREAD_A27_ME3 83 /* ME_THREAD_A */
106#define IRQ_IXP23XX_ME_THREAD_A28_ME3 84 /* ME_THREAD_A */
107#define IRQ_IXP23XX_ME_THREAD_A29_ME3 85 /* ME_THREAD_A */
108#define IRQ_IXP23XX_ME_THREAD_A30_ME3 86 /* ME_THREAD_A */
109#define IRQ_IXP23XX_ME_THREAD_A31_ME3 87 /* ME_THREAD_A */
110#define IRQ_IXP23XX_ME_THREAD_B0_ME0 88 /* ME_THREAD_B */
111#define IRQ_IXP23XX_ME_THREAD_B1_ME0 89 /* ME_THREAD_B */
112#define IRQ_IXP23XX_ME_THREAD_B2_ME0 90 /* ME_THREAD_B */
113#define IRQ_IXP23XX_ME_THREAD_B3_ME0 91 /* ME_THREAD_B */
114#define IRQ_IXP23XX_ME_THREAD_B4_ME0 92 /* ME_THREAD_B */
115#define IRQ_IXP23XX_ME_THREAD_B5_ME0 93 /* ME_THREAD_B */
116#define IRQ_IXP23XX_ME_THREAD_B6_ME0 94 /* ME_THREAD_B */
117#define IRQ_IXP23XX_ME_THREAD_B7_ME0 95 /* ME_THREAD_B */
118#define IRQ_IXP23XX_ME_THREAD_B8_ME1 96 /* ME_THREAD_B */
119#define IRQ_IXP23XX_ME_THREAD_B9_ME1 97 /* ME_THREAD_B */
120#define IRQ_IXP23XX_ME_THREAD_B10_ME1 98 /* ME_THREAD_B */
121#define IRQ_IXP23XX_ME_THREAD_B11_ME1 99 /* ME_THREAD_B */
122#define IRQ_IXP23XX_ME_THREAD_B12_ME1 100 /* ME_THREAD_B */
123#define IRQ_IXP23XX_ME_THREAD_B13_ME1 101 /* ME_THREAD_B */
124#define IRQ_IXP23XX_ME_THREAD_B14_ME1 102 /* ME_THREAD_B */
125#define IRQ_IXP23XX_ME_THREAD_B15_ME1 103 /* ME_THREAD_B */
126#define IRQ_IXP23XX_ME_THREAD_B16_ME2 104 /* ME_THREAD_B */
127#define IRQ_IXP23XX_ME_THREAD_B17_ME2 105 /* ME_THREAD_B */
128#define IRQ_IXP23XX_ME_THREAD_B18_ME2 106 /* ME_THREAD_B */
129#define IRQ_IXP23XX_ME_THREAD_B19_ME2 107 /* ME_THREAD_B */
130#define IRQ_IXP23XX_ME_THREAD_B20_ME2 108 /* ME_THREAD_B */
131#define IRQ_IXP23XX_ME_THREAD_B21_ME2 109 /* ME_THREAD_B */
132#define IRQ_IXP23XX_ME_THREAD_B22_ME2 110 /* ME_THREAD_B */
133#define IRQ_IXP23XX_ME_THREAD_B23_ME2 111 /* ME_THREAD_B */
134#define IRQ_IXP23XX_ME_THREAD_B24_ME3 112 /* ME_THREAD_B */
135#define IRQ_IXP23XX_ME_THREAD_B25_ME3 113 /* ME_THREAD_B */
136#define IRQ_IXP23XX_ME_THREAD_B26_ME3 114 /* ME_THREAD_B */
137#define IRQ_IXP23XX_ME_THREAD_B27_ME3 115 /* ME_THREAD_B */
138#define IRQ_IXP23XX_ME_THREAD_B28_ME3 116 /* ME_THREAD_B */
139#define IRQ_IXP23XX_ME_THREAD_B29_ME3 117 /* ME_THREAD_B */
140#define IRQ_IXP23XX_ME_THREAD_B30_ME3 118 /* ME_THREAD_B */
141#define IRQ_IXP23XX_ME_THREAD_B31_ME3 119 /* ME_THREAD_B */
142
143#define NUM_IXP23XX_RAW_IRQS 120
144
145#define IRQ_IXP23XX_INTA 120 /* Indirect pcxg_pci_int_rph */
146#define IRQ_IXP23XX_INTB 121 /* Indirect pcxg_pci_int_rph */
147
148#define NR_IXP23XX_IRQ (IRQ_IXP23XX_INTB + 1)
149
150/*
151 * We default to 32 per-board IRQs. Increase this number if you need
152 * more, but keep it realistic.
153 */
154#define NR_IXP23XX_MACH_IRQS 32
155
156#define NR_IRQS (NR_IXP23XX_IRQS + NR_IXP23XX_MACH_IRQS)
157
158#define IXP23XX_MACH_IRQ(irq) (NR_IXP23XX_IRQ + (irq))
159
160
161/*
162 * IXDP2351-specific interrupts
163 */
164
165/*
166 * External PCI interrupts signaled through INTB
167 *
168 */
169#define IXDP2351_INTB_IRQ_BASE 0
170#define IRQ_IXDP2351_INTA_82546 IXP23XX_MACH_IRQ(0)
171#define IRQ_IXDP2351_INTB_82546 IXP23XX_MACH_IRQ(1)
172#define IRQ_IXDP2351_SPCI_DB_0 IXP23XX_MACH_IRQ(2)
173#define IRQ_IXDP2351_SPCI_DB_1 IXP23XX_MACH_IRQ(3)
174#define IRQ_IXDP2351_SPCI_PMC_INTA IXP23XX_MACH_IRQ(4)
175#define IRQ_IXDP2351_SPCI_PMC_INTB IXP23XX_MACH_IRQ(5)
176#define IRQ_IXDP2351_SPCI_PMC_INTC IXP23XX_MACH_IRQ(6)
177#define IRQ_IXDP2351_SPCI_PMC_INTD IXP23XX_MACH_IRQ(7)
178#define IRQ_IXDP2351_SPCI_FIC IXP23XX_MACH_IRQ(8)
179
180#define IXDP2351_INTB_IRQ_BIT(irq) (irq - IXP23XX_MACH_IRQ(0))
181#define IXDP2351_INTB_IRQ_MASK(irq) (1 << IXDP2351_INTB_IRQ_BIT(irq))
182#define IXDP2351_INTB_IRQ_VALID 0x01FF
183#define IXDP2351_INTB_IRQ_NUM 16
184
185/*
186 * Other external interrupts signaled through INTA
187 */
188#define IXDP2351_INTA_IRQ_BASE 16
189#define IRQ_IXDP2351_IPMI_FROM IXP23XX_MACH_IRQ(16)
190#define IRQ_IXDP2351_125US IXP23XX_MACH_IRQ(17)
191#define IRQ_IXDP2351_DB_0_ADD IXP23XX_MACH_IRQ(18)
192#define IRQ_IXDP2351_DB_1_ADD IXP23XX_MACH_IRQ(19)
193#define IRQ_IXDP2351_DEBUG1 IXP23XX_MACH_IRQ(20)
194#define IRQ_IXDP2351_ADD_UART IXP23XX_MACH_IRQ(21)
195#define IRQ_IXDP2351_FIC_ADD IXP23XX_MACH_IRQ(24)
196#define IRQ_IXDP2351_CS8900 IXP23XX_MACH_IRQ(25)
197#define IRQ_IXDP2351_BBSRAM IXP23XX_MACH_IRQ(26)
198#define IRQ_IXDP2351_CONFIG_MEDIA IXP23XX_MACH_IRQ(27)
199#define IRQ_IXDP2351_CLOCK_REF IXP23XX_MACH_IRQ(28)
200#define IRQ_IXDP2351_A10_NP IXP23XX_MACH_IRQ(29)
201#define IRQ_IXDP2351_A11_NP IXP23XX_MACH_IRQ(30)
202#define IRQ_IXDP2351_DEBUG_NP IXP23XX_MACH_IRQ(31)
203
204#define IXDP2351_INTA_IRQ_BIT(irq) (irq - IXP23XX_MACH_IRQ(16))
205#define IXDP2351_INTA_IRQ_MASK(irq) (1 << IXDP2351_INTA_IRQ_BIT(irq))
206#define IXDP2351_INTA_IRQ_VALID 0xFF3F
207#define IXDP2351_INTA_IRQ_NUM 16
208
209
210/*
211 * ADI RoadRunner IRQs
212 */
213#define IRQ_ROADRUNNER_PCI_INTA IRQ_IXP23XX_INTA
214#define IRQ_ROADRUNNER_PCI_INTB IRQ_IXP23XX_INTB
215#define IRQ_ROADRUNNER_PCI_INTC IRQ_IXP23XX_GPIO11
216#define IRQ_ROADRUNNER_PCI_INTD IRQ_IXP23XX_GPIO12
217
218/*
219 * Put new board definitions here
220 */
221
222
223#endif
diff --git a/arch/arm/mach-ixp23xx/include/mach/ixdp2351.h b/arch/arm/mach-ixp23xx/include/mach/ixdp2351.h
deleted file mode 100644
index 663951027de5..000000000000
--- a/arch/arm/mach-ixp23xx/include/mach/ixdp2351.h
+++ /dev/null
@@ -1,89 +0,0 @@
1/*
2 * arch/arm/mach-ixp23xx/include/mach/ixdp2351.h
3 *
4 * Register and other defines for IXDP2351
5 *
6 * Copyright (c) 2002-2004 Intel Corp.
7 * Copytight (c) 2005 MontaVista Software, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15#ifndef __ASM_ARCH_IXDP2351_H
16#define __ASM_ARCH_IXDP2351_H
17
18/*
19 * NP module memory map
20 */
21#define IXDP2351_NP_PHYS_BASE (IXP23XX_EXP_BUS_CS4_BASE)
22#define IXDP2351_NP_PHYS_SIZE 0x00100000
23#define IXDP2351_NP_VIRT_BASE 0xeff00000
24
25#define IXDP2351_VIRT_CS8900_BASE (IXDP2351_NP_VIRT_BASE)
26#define IXDP2351_VIRT_CS8900_END (IXDP2351_VIRT_CS8900_BASE + 16)
27
28#define IXDP2351_VIRT_NP_CPLD_BASE (IXP23XX_EXP_BUS_CS4_BASE_VIRT + 0x00010000)
29
30#define IXDP2351_NP_CPLD_REG(reg) ((volatile u16 *)(IXDP2351_VIRT_NP_CPLD_BASE + reg))
31
32#define IXDP2351_NP_CPLD_RESET1_REG IXDP2351_NP_CPLD_REG(0x00)
33#define IXDP2351_NP_CPLD_LED_REG IXDP2351_NP_CPLD_REG(0x02)
34#define IXDP2351_NP_CPLD_VERSION_REG IXDP2351_NP_CPLD_REG(0x04)
35
36/*
37 * Base board module memory map
38 */
39
40#define IXDP2351_BB_BASE_PHYS (IXP23XX_EXP_BUS_CS5_BASE)
41#define IXDP2351_BB_SIZE 0x01000000
42#define IXDP2351_BB_BASE_VIRT (0xee000000)
43
44#define IXDP2351_BB_AREA_BASE(offset) (IXDP2351_BB_BASE_VIRT + offset)
45
46#define IXDP2351_VIRT_NVRAM_BASE IXDP2351_BB_AREA_BASE(0x0)
47#define IXDP2351_NVRAM_SIZE (0x20000)
48
49#define IXDP2351_VIRT_MB_IXF1104_BASE IXDP2351_BB_AREA_BASE(0x00020000)
50#define IXDP2351_VIRT_ADD_UART_BASE IXDP2351_BB_AREA_BASE(0x000240C0)
51#define IXDP2351_VIRT_FIC_BASE IXDP2351_BB_AREA_BASE(0x00200000)
52#define IXDP2351_VIRT_DB0_BASE IXDP2351_BB_AREA_BASE(0x00400000)
53#define IXDP2351_VIRT_DB1_BASE IXDP2351_BB_AREA_BASE(0x00600000)
54#define IXDP2351_VIRT_CPLD_BASE IXDP2351_BB_AREA_BASE(0x00024000)
55
56/*
57 * On board CPLD registers
58 */
59#define IXDP2351_CPLD_BB_REG(reg) ((volatile u16 *)(IXDP2351_VIRT_CPLD_BASE + reg))
60
61#define IXDP2351_CPLD_RESET0_REG IXDP2351_CPLD_BB_REG(0x00)
62#define IXDP2351_CPLD_RESET1_REG IXDP2351_CPLD_BB_REG(0x04)
63
64#define IXDP2351_CPLD_RESET1_MAGIC 0x55AA
65#define IXDP2351_CPLD_RESET1_ENABLE 0x8000
66
67#define IXDP2351_CPLD_FPGA_CONFIG_REG IXDP2351_CPLD_BB_REG(0x08)
68#define IXDP2351_CPLD_INTB_MASK_SET_REG IXDP2351_CPLD_BB_REG(0x10)
69#define IXDP2351_CPLD_INTA_MASK_SET_REG IXDP2351_CPLD_BB_REG(0x14)
70#define IXDP2351_CPLD_INTB_STAT_REG IXDP2351_CPLD_BB_REG(0x18)
71#define IXDP2351_CPLD_INTA_STAT_REG IXDP2351_CPLD_BB_REG(0x1C)
72#define IXDP2351_CPLD_INTB_RAW_REG IXDP2351_CPLD_BB_REG(0x20) /* read */
73#define IXDP2351_CPLD_INTA_RAW_REG IXDP2351_CPLD_BB_REG(0x24) /* read */
74#define IXDP2351_CPLD_INTB_MASK_CLR_REG IXDP2351_CPLD_INTB_RAW_REG /* write */
75#define IXDP2351_CPLD_INTA_MASK_CLR_REG IXDP2351_CPLD_INTA_RAW_REG /* write */
76#define IXDP2351_CPLD_INTB_SIM_REG IXDP2351_CPLD_BB_REG(0x28)
77#define IXDP2351_CPLD_INTA_SIM_REG IXDP2351_CPLD_BB_REG(0x2C)
78 /* Interrupt bits are defined in irqs.h */
79#define IXDP2351_CPLD_BB_GBE0_REG IXDP2351_CPLD_BB_REG(0x30)
80#define IXDP2351_CPLD_BB_GBE1_REG IXDP2351_CPLD_BB_REG(0x34)
81
82/* #define IXDP2351_CPLD_BB_MISC_REG IXDP2351_CPLD_REG(0x1C) */
83/* #define IXDP2351_CPLD_BB_MISC_REV_MASK 0xFF */
84/* #define IXDP2351_CPLD_BB_GDXCS0_REG IXDP2351_CPLD_REG(0x24) */
85/* #define IXDP2351_CPLD_BB_GDXCS1_REG IXDP2351_CPLD_REG(0x28) */
86/* #define IXDP2351_CPLD_BB_CLOCK_REG IXDP2351_CPLD_REG(0x04) */
87
88
89#endif
diff --git a/arch/arm/mach-ixp23xx/include/mach/ixp23xx.h b/arch/arm/mach-ixp23xx/include/mach/ixp23xx.h
deleted file mode 100644
index 6d02481b1d6d..000000000000
--- a/arch/arm/mach-ixp23xx/include/mach/ixp23xx.h
+++ /dev/null
@@ -1,298 +0,0 @@
1/*
2 * arch/arm/mach-ixp23xx/include/mach/ixp23xx.h
3 *
4 * Register definitions for IXP23XX
5 *
6 * Copyright (C) 2003-2005 Intel Corporation.
7 * Copyright (C) 2005 MontaVista Software, Inc.
8 *
9 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#ifndef __ASM_ARCH_IXP23XX_H
17#define __ASM_ARCH_IXP23XX_H
18
19/*
20 * IXP2300 linux memory map:
21 *
22 * virt phys size
23 * fffd0000 a0000000 64K XSI2CPP_CSR
24 * fffc0000 c4000000 4K EXP_CFG
25 * fff00000 c8000000 64K PERIPHERAL
26 * fe000000 1c0000000 16M CAP_CSR
27 * fd000000 1c8000000 16M MSF_CSR
28 * fb000000 16M ---
29 * fa000000 1d8000000 32M PCI_IO
30 * f8000000 1da000000 32M PCI_CFG
31 * f6000000 1de000000 32M PCI_CREG
32 * f4000000 32M ---
33 * f0000000 1e0000000 64M PCI_MEM
34 * e[c-f]000000 per-platform mappings
35 */
36
37
38/****************************************************************************
39 * Static mappings.
40 ****************************************************************************/
41#define IXP23XX_XSI2CPP_CSR_PHYS 0xa0000000
42#define IXP23XX_XSI2CPP_CSR_VIRT 0xfffd0000
43#define IXP23XX_XSI2CPP_CSR_SIZE 0x00010000
44
45#define IXP23XX_EXP_CFG_PHYS 0xc4000000
46#define IXP23XX_EXP_CFG_VIRT 0xfffc0000
47#define IXP23XX_EXP_CFG_SIZE 0x00001000
48
49#define IXP23XX_PERIPHERAL_PHYS 0xc8000000
50#define IXP23XX_PERIPHERAL_VIRT 0xfff00000
51#define IXP23XX_PERIPHERAL_SIZE 0x00010000
52
53#define IXP23XX_CAP_CSR_PHYS 0x1c0000000ULL
54#define IXP23XX_CAP_CSR_VIRT 0xfe000000
55#define IXP23XX_CAP_CSR_SIZE 0x01000000
56
57#define IXP23XX_MSF_CSR_PHYS 0x1c8000000ULL
58#define IXP23XX_MSF_CSR_VIRT 0xfd000000
59#define IXP23XX_MSF_CSR_SIZE 0x01000000
60
61#define IXP23XX_PCI_IO_PHYS 0x1d8000000ULL
62#define IXP23XX_PCI_IO_VIRT 0xfa000000
63#define IXP23XX_PCI_IO_SIZE 0x02000000
64
65#define IXP23XX_PCI_CFG_PHYS 0x1da000000ULL
66#define IXP23XX_PCI_CFG_VIRT 0xf8000000
67#define IXP23XX_PCI_CFG_SIZE 0x02000000
68#define IXP23XX_PCI_CFG0_VIRT IXP23XX_PCI_CFG_VIRT
69#define IXP23XX_PCI_CFG1_VIRT (IXP23XX_PCI_CFG_VIRT + 0x01000000)
70
71#define IXP23XX_PCI_CREG_PHYS 0x1de000000ULL
72#define IXP23XX_PCI_CREG_VIRT 0xf6000000
73#define IXP23XX_PCI_CREG_SIZE 0x02000000
74#define IXP23XX_PCI_CSR_VIRT (IXP23XX_PCI_CREG_VIRT + 0x01000000)
75
76#define IXP23XX_PCI_MEM_START 0xe0000000
77#define IXP23XX_PCI_MEM_PHYS 0x1e0000000ULL
78#define IXP23XX_PCI_MEM_VIRT 0xf0000000
79#define IXP23XX_PCI_MEM_SIZE 0x04000000
80
81
82/****************************************************************************
83 * XSI2CPP CSRs.
84 ****************************************************************************/
85#define IXP23XX_XSI2CPP_REG(x) ((volatile unsigned long *)(IXP23XX_XSI2CPP_CSR_VIRT + (x)))
86#define IXP23XX_CPP2XSI_CURR_XFER_REG3 IXP23XX_XSI2CPP_REG(0xf8)
87#define IXP23XX_CPP2XSI_ADDR_31 (1 << 19)
88#define IXP23XX_CPP2XSI_PSH_OFF (1 << 20)
89#define IXP23XX_CPP2XSI_COH_OFF (1 << 21)
90
91
92/****************************************************************************
93 * Expansion Bus Config.
94 ****************************************************************************/
95#define IXP23XX_EXP_CFG_REG(x) ((volatile unsigned long *)(IXP23XX_EXP_CFG_VIRT + (x)))
96#define IXP23XX_EXP_CS0 IXP23XX_EXP_CFG_REG(0x00)
97#define IXP23XX_EXP_CS1 IXP23XX_EXP_CFG_REG(0x04)
98#define IXP23XX_EXP_CS2 IXP23XX_EXP_CFG_REG(0x08)
99#define IXP23XX_EXP_CS3 IXP23XX_EXP_CFG_REG(0x0c)
100#define IXP23XX_EXP_CS4 IXP23XX_EXP_CFG_REG(0x10)
101#define IXP23XX_EXP_CS5 IXP23XX_EXP_CFG_REG(0x14)
102#define IXP23XX_EXP_CS6 IXP23XX_EXP_CFG_REG(0x18)
103#define IXP23XX_EXP_CS7 IXP23XX_EXP_CFG_REG(0x1c)
104#define IXP23XX_FLASH_WRITABLE (0x2)
105#define IXP23XX_FLASH_BUS8 (0x1)
106
107#define IXP23XX_EXP_CFG0 IXP23XX_EXP_CFG_REG(0x20)
108#define IXP23XX_EXP_CFG1 IXP23XX_EXP_CFG_REG(0x24)
109#define IXP23XX_EXP_CFG0_MEM_MAP (1 << 31)
110#define IXP23XX_EXP_CFG0_XSCALE_SPEED_SEL (3 << 22)
111#define IXP23XX_EXP_CFG0_XSCALE_SPEED_EN (1 << 21)
112#define IXP23XX_EXP_CFG0_CPP_SPEED_SEL (3 << 19)
113#define IXP23XX_EXP_CFG0_CPP_SPEED_EN (1 << 18)
114#define IXP23XX_EXP_CFG0_PCI_SWIN (3 << 16)
115#define IXP23XX_EXP_CFG0_PCI_DWIN (3 << 14)
116#define IXP23XX_EXP_CFG0_PCI33_MODE (1 << 13)
117#define IXP23XX_EXP_CFG0_QDR_SPEED_SEL (1 << 12)
118#define IXP23XX_EXP_CFG0_CPP_DIV_SEL (1 << 5)
119#define IXP23XX_EXP_CFG0_XSI_NOT_PRES (1 << 4)
120#define IXP23XX_EXP_CFG0_PROM_BOOT (1 << 3)
121#define IXP23XX_EXP_CFG0_PCI_ARB (1 << 2)
122#define IXP23XX_EXP_CFG0_PCI_HOST (1 << 1)
123#define IXP23XX_EXP_CFG0_FLASH_WIDTH (1 << 0)
124
125#define IXP23XX_EXP_UNIT_FUSE IXP23XX_EXP_CFG_REG(0x28)
126#define IXP23XX_EXP_MSF_MUX IXP23XX_EXP_CFG_REG(0x30)
127#define IXP23XX_EXP_CFG_FUSE IXP23XX_EXP_CFG_REG(0x34)
128
129#define IXP23XX_EXP_BUS_PHYS 0x90000000
130#define IXP23XX_EXP_BUS_WINDOW_SIZE 0x01000000
131
132#define IXP23XX_EXP_BUS_CS0_BASE (IXP23XX_EXP_BUS_PHYS + 0x00000000)
133#define IXP23XX_EXP_BUS_CS1_BASE (IXP23XX_EXP_BUS_PHYS + 0x01000000)
134#define IXP23XX_EXP_BUS_CS2_BASE (IXP23XX_EXP_BUS_PHYS + 0x02000000)
135#define IXP23XX_EXP_BUS_CS3_BASE (IXP23XX_EXP_BUS_PHYS + 0x03000000)
136#define IXP23XX_EXP_BUS_CS4_BASE (IXP23XX_EXP_BUS_PHYS + 0x04000000)
137#define IXP23XX_EXP_BUS_CS5_BASE (IXP23XX_EXP_BUS_PHYS + 0x05000000)
138#define IXP23XX_EXP_BUS_CS6_BASE (IXP23XX_EXP_BUS_PHYS + 0x06000000)
139#define IXP23XX_EXP_BUS_CS7_BASE (IXP23XX_EXP_BUS_PHYS + 0x07000000)
140
141
142/****************************************************************************
143 * Peripherals.
144 ****************************************************************************/
145#define IXP23XX_UART1_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x0000)
146#define IXP23XX_UART2_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x1000)
147#define IXP23XX_PMU_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x2000)
148#define IXP23XX_INTC_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x3000)
149#define IXP23XX_GPIO_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x4000)
150#define IXP23XX_TIMER_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x5000)
151#define IXP23XX_NPE0_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x6000)
152#define IXP23XX_DSR_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x7000)
153#define IXP23XX_NPE1_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x8000)
154#define IXP23XX_ETH0_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x9000)
155#define IXP23XX_ETH1_VIRT (IXP23XX_PERIPHERAL_VIRT + 0xA000)
156#define IXP23XX_GIG0_VIRT (IXP23XX_PERIPHERAL_VIRT + 0xB000)
157#define IXP23XX_GIG1_VIRT (IXP23XX_PERIPHERAL_VIRT + 0xC000)
158#define IXP23XX_DDRS_VIRT (IXP23XX_PERIPHERAL_VIRT + 0xD000)
159
160#define IXP23XX_UART1_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x0000)
161#define IXP23XX_UART2_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x1000)
162#define IXP23XX_PMU_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x2000)
163#define IXP23XX_INTC_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x3000)
164#define IXP23XX_GPIO_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x4000)
165#define IXP23XX_TIMER_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x5000)
166#define IXP23XX_NPE0_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x6000)
167#define IXP23XX_DSR_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x7000)
168#define IXP23XX_NPE1_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x8000)
169#define IXP23XX_ETH0_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x9000)
170#define IXP23XX_ETH1_PHYS (IXP23XX_PERIPHERAL_PHYS + 0xA000)
171#define IXP23XX_GIG0_PHYS (IXP23XX_PERIPHERAL_PHYS + 0xB000)
172#define IXP23XX_GIG1_PHYS (IXP23XX_PERIPHERAL_PHYS + 0xC000)
173#define IXP23XX_DDRS_PHYS (IXP23XX_PERIPHERAL_PHYS + 0xD000)
174
175
176/****************************************************************************
177 * Interrupt controller.
178 ****************************************************************************/
179#define IXP23XX_INTC_REG(x) ((volatile unsigned long *)(IXP23XX_INTC_VIRT + (x)))
180#define IXP23XX_INTR_ST1 IXP23XX_INTC_REG(0x00)
181#define IXP23XX_INTR_ST2 IXP23XX_INTC_REG(0x04)
182#define IXP23XX_INTR_ST3 IXP23XX_INTC_REG(0x08)
183#define IXP23XX_INTR_ST4 IXP23XX_INTC_REG(0x0c)
184#define IXP23XX_INTR_EN1 IXP23XX_INTC_REG(0x10)
185#define IXP23XX_INTR_EN2 IXP23XX_INTC_REG(0x14)
186#define IXP23XX_INTR_EN3 IXP23XX_INTC_REG(0x18)
187#define IXP23XX_INTR_EN4 IXP23XX_INTC_REG(0x1c)
188#define IXP23XX_INTR_SEL1 IXP23XX_INTC_REG(0x20)
189#define IXP23XX_INTR_SEL2 IXP23XX_INTC_REG(0x24)
190#define IXP23XX_INTR_SEL3 IXP23XX_INTC_REG(0x28)
191#define IXP23XX_INTR_SEL4 IXP23XX_INTC_REG(0x2c)
192#define IXP23XX_INTR_IRQ_ST1 IXP23XX_INTC_REG(0x30)
193#define IXP23XX_INTR_IRQ_ST2 IXP23XX_INTC_REG(0x34)
194#define IXP23XX_INTR_IRQ_ST3 IXP23XX_INTC_REG(0x38)
195#define IXP23XX_INTR_IRQ_ST4 IXP23XX_INTC_REG(0x3c)
196#define IXP23XX_INTR_IRQ_ENC_ST_OFFSET 0x54
197
198
199/****************************************************************************
200 * GPIO.
201 ****************************************************************************/
202#define IXP23XX_GPIO_REG(x) ((volatile unsigned long *)(IXP23XX_GPIO_VIRT + (x)))
203#define IXP23XX_GPIO_GPOUTR IXP23XX_GPIO_REG(0x00)
204#define IXP23XX_GPIO_GPOER IXP23XX_GPIO_REG(0x04)
205#define IXP23XX_GPIO_GPINR IXP23XX_GPIO_REG(0x08)
206#define IXP23XX_GPIO_GPISR IXP23XX_GPIO_REG(0x0c)
207#define IXP23XX_GPIO_GPIT1R IXP23XX_GPIO_REG(0x10)
208#define IXP23XX_GPIO_GPIT2R IXP23XX_GPIO_REG(0x14)
209#define IXP23XX_GPIO_GPCLKR IXP23XX_GPIO_REG(0x18)
210#define IXP23XX_GPIO_GPDBSELR IXP23XX_GPIO_REG(0x1c)
211
212#define IXP23XX_GPIO_STYLE_MASK 0x7
213#define IXP23XX_GPIO_STYLE_ACTIVE_HIGH 0x0
214#define IXP23XX_GPIO_STYLE_ACTIVE_LOW 0x1
215#define IXP23XX_GPIO_STYLE_RISING_EDGE 0x2
216#define IXP23XX_GPIO_STYLE_FALLING_EDGE 0x3
217#define IXP23XX_GPIO_STYLE_TRANSITIONAL 0x4
218
219#define IXP23XX_GPIO_STYLE_SIZE 3
220
221
222/****************************************************************************
223 * Timer.
224 ****************************************************************************/
225#define IXP23XX_TIMER_REG(x) ((volatile unsigned long *)(IXP23XX_TIMER_VIRT + (x)))
226#define IXP23XX_TIMER_CONT IXP23XX_TIMER_REG(0x00)
227#define IXP23XX_TIMER1_TIMESTAMP IXP23XX_TIMER_REG(0x04)
228#define IXP23XX_TIMER1_RELOAD IXP23XX_TIMER_REG(0x08)
229#define IXP23XX_TIMER2_TIMESTAMP IXP23XX_TIMER_REG(0x0c)
230#define IXP23XX_TIMER2_RELOAD IXP23XX_TIMER_REG(0x10)
231#define IXP23XX_TIMER_WDOG IXP23XX_TIMER_REG(0x14)
232#define IXP23XX_TIMER_WDOG_EN IXP23XX_TIMER_REG(0x18)
233#define IXP23XX_TIMER_WDOG_KEY IXP23XX_TIMER_REG(0x1c)
234#define IXP23XX_TIMER_WDOG_KEY_MAGIC 0x482e
235#define IXP23XX_TIMER_STATUS IXP23XX_TIMER_REG(0x20)
236#define IXP23XX_TIMER_SOFT_RESET IXP23XX_TIMER_REG(0x24)
237#define IXP23XX_TIMER_SOFT_RESET_EN IXP23XX_TIMER_REG(0x28)
238
239#define IXP23XX_TIMER_ENABLE (1 << 0)
240#define IXP23XX_TIMER_ONE_SHOT (1 << 1)
241/* Low order bits of reload value ignored */
242#define IXP23XX_TIMER_RELOAD_MASK (0x3)
243#define IXP23XX_TIMER_DISABLED (0x0)
244#define IXP23XX_TIMER1_INT_PEND (1 << 0)
245#define IXP23XX_TIMER2_INT_PEND (1 << 1)
246#define IXP23XX_TIMER_STATUS_TS_PEND (1 << 2)
247#define IXP23XX_TIMER_STATUS_WDOG_PEND (1 << 3)
248#define IXP23XX_TIMER_STATUS_WARM_RESET (1 << 4)
249
250
251/****************************************************************************
252 * CAP CSRs.
253 ****************************************************************************/
254#define IXP23XX_GLOBAL_REG(x) ((volatile unsigned long *)(IXP23XX_CAP_CSR_VIRT + 0x4a00 + (x)))
255#define IXP23XX_PRODUCT_ID IXP23XX_GLOBAL_REG(0x00)
256#define IXP23XX_MISC_CONTROL IXP23XX_GLOBAL_REG(0x04)
257#define IXP23XX_MSF_CLK_CNTRL IXP23XX_GLOBAL_REG(0x08)
258#define IXP23XX_RESET0 IXP23XX_GLOBAL_REG(0x0c)
259#define IXP23XX_RESET1 IXP23XX_GLOBAL_REG(0x10)
260#define IXP23XX_STRAP_OPTIONS IXP23XX_GLOBAL_REG(0x18)
261
262#define IXP23XX_ENABLE_WATCHDOG (1 << 24)
263#define IXP23XX_SHPC_INIT_COMP (1 << 21)
264#define IXP23XX_RST_ALL (1 << 16)
265#define IXP23XX_RESET_PCI (1 << 2)
266#define IXP23XX_PCI_UNIT_RESET (1 << 1)
267#define IXP23XX_XSCALE_RESET (1 << 0)
268
269#define IXP23XX_UENGINE_CSR_VIRT_BASE (IXP23XX_CAP_CSR_VIRT + 0x18000)
270
271
272/****************************************************************************
273 * PCI CSRs.
274 ****************************************************************************/
275#define IXP23XX_PCI_CREG(x) ((volatile unsigned long *)(IXP23XX_PCI_CREG_VIRT + (x)))
276#define IXP23XX_PCI_CMDSTAT IXP23XX_PCI_CREG(0x04)
277#define IXP23XX_PCI_SRAM_BAR IXP23XX_PCI_CREG(0x14)
278#define IXP23XX_PCI_SDRAM_BAR IXP23XX_PCI_CREG(0x18)
279
280
281#define IXP23XX_PCI_CSR(x) ((volatile unsigned long *)(IXP23XX_PCI_CREG_VIRT + 0x01000000 + (x)))
282#define IXP23XX_PCI_OUT_INT_STATUS IXP23XX_PCI_CSR(0x0030)
283#define IXP23XX_PCI_OUT_INT_MASK IXP23XX_PCI_CSR(0x0034)
284#define IXP23XX_PCI_SRAM_BASE_ADDR_MASK IXP23XX_PCI_CSR(0x00fc)
285#define IXP23XX_PCI_DRAM_BASE_ADDR_MASK IXP23XX_PCI_CSR(0x0100)
286#define IXP23XX_PCI_CONTROL IXP23XX_PCI_CSR(0x013c)
287#define IXP23XX_PCI_ADDR_EXT IXP23XX_PCI_CSR(0x0140)
288#define IXP23XX_PCI_ME_PUSH_STATUS IXP23XX_PCI_CSR(0x0148)
289#define IXP23XX_PCI_ME_PUSH_EN IXP23XX_PCI_CSR(0x014c)
290#define IXP23XX_PCI_ERR_STATUS IXP23XX_PCI_CSR(0x0150)
291#define IXP23XX_PCI_ERROR_STATUS IXP23XX_PCI_CSR(0x0150)
292#define IXP23XX_PCI_ERR_ENABLE IXP23XX_PCI_CSR(0x0154)
293#define IXP23XX_PCI_XSCALE_INT_STATUS IXP23XX_PCI_CSR(0x0158)
294#define IXP23XX_PCI_XSCALE_INT_ENABLE IXP23XX_PCI_CSR(0x015c)
295#define IXP23XX_PCI_CPP_ADDR_BITS IXP23XX_PCI_CSR(0x0160)
296
297
298#endif
diff --git a/arch/arm/mach-ixp23xx/include/mach/memory.h b/arch/arm/mach-ixp23xx/include/mach/memory.h
deleted file mode 100644
index 6cf0704e946a..000000000000
--- a/arch/arm/mach-ixp23xx/include/mach/memory.h
+++ /dev/null
@@ -1,34 +0,0 @@
1/*
2 * arch/arm/mach-ixp23xx/include/mach/memory.h
3 *
4 * Copyright (c) 2003-2004 Intel Corp.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12#ifndef __ASM_ARCH_MEMORY_H
13#define __ASM_ARCH_MEMORY_H
14
15#include <mach/hardware.h>
16
17/*
18 * Physical DRAM offset.
19 */
20#define PLAT_PHYS_OFFSET (0x00000000)
21
22#define IXP23XX_PCI_SDRAM_OFFSET (*((volatile int *)IXP23XX_PCI_SDRAM_BAR) & 0xfffffff0)
23
24#define __phys_to_bus(x) ((x) + (IXP23XX_PCI_SDRAM_OFFSET - PHYS_OFFSET))
25#define __bus_to_phys(x) ((x) - (IXP23XX_PCI_SDRAM_OFFSET - PHYS_OFFSET))
26
27#define __virt_to_bus(v) __phys_to_bus(__virt_to_phys(v))
28#define __bus_to_virt(b) __phys_to_virt(__bus_to_phys(b))
29#define __pfn_to_bus(p) __phys_to_bus(__pfn_to_phys(p))
30#define __bus_to_pfn(b) __phys_to_pfn(__bus_to_phys(b))
31
32#define arch_is_coherent() 1
33
34#endif
diff --git a/arch/arm/mach-ixp23xx/include/mach/platform.h b/arch/arm/mach-ixp23xx/include/mach/platform.h
deleted file mode 100644
index 50de558e722e..000000000000
--- a/arch/arm/mach-ixp23xx/include/mach/platform.h
+++ /dev/null
@@ -1,58 +0,0 @@
1/*
2 * arch/arm/mach-ixp23xx/include/mach/platform.h
3 *
4 * Various bits of code used by platform-level code.
5 *
6 * Author: Deepak Saxena <dsaxena@plexity.net>
7 *
8 * Copyright 2005 (c) MontaVista Software, Inc.
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15#ifndef __ASSEMBLY__
16
17static inline unsigned long ixp2000_reg_read(volatile void *reg)
18{
19 return *((volatile unsigned long *)reg);
20}
21
22static inline void ixp2000_reg_write(volatile void *reg, unsigned long val)
23{
24 *((volatile unsigned long *)reg) = val;
25}
26
27static inline void ixp2000_reg_wrb(volatile void *reg, unsigned long val)
28{
29 *((volatile unsigned long *)reg) = val;
30}
31
32struct pci_sys_data;
33
34void ixp23xx_map_io(void);
35void ixp23xx_init_irq(void);
36void ixp23xx_sys_init(void);
37void ixp23xx_restart(char, const char *);
38int ixp23xx_pci_setup(int, struct pci_sys_data *);
39void ixp23xx_pci_preinit(void);
40struct pci_bus *ixp23xx_pci_scan_bus(int, struct pci_sys_data*);
41void ixp23xx_pci_slave_init(void);
42
43extern struct sys_timer ixp23xx_timer;
44
45#define IXP23XX_UART_XTAL 14745600
46
47#ifndef __ASSEMBLY__
48/*
49 * Is system memory on the XSI or CPP bus?
50 */
51static inline unsigned ixp23xx_cpp_boot(void)
52{
53 return (*IXP23XX_EXP_CFG0 & IXP23XX_EXP_CFG0_XSI_NOT_PRES);
54}
55#endif
56
57
58#endif
diff --git a/arch/arm/mach-ixp23xx/include/mach/time.h b/arch/arm/mach-ixp23xx/include/mach/time.h
deleted file mode 100644
index b61dafc884ac..000000000000
--- a/arch/arm/mach-ixp23xx/include/mach/time.h
+++ /dev/null
@@ -1,3 +0,0 @@
1/*
2 * arch/arm/mach-ixp23xx/include/mach/time.h
3 */
diff --git a/arch/arm/mach-ixp23xx/include/mach/timex.h b/arch/arm/mach-ixp23xx/include/mach/timex.h
deleted file mode 100644
index e341e9cf9c37..000000000000
--- a/arch/arm/mach-ixp23xx/include/mach/timex.h
+++ /dev/null
@@ -1,7 +0,0 @@
1/*
2 * arch/arm/mach-ixp23xx/include/mach/timex.h
3 *
4 * XScale architecture timex specifications
5 */
6
7#define CLOCK_TICK_RATE 75000000
diff --git a/arch/arm/mach-ixp23xx/include/mach/uncompress.h b/arch/arm/mach-ixp23xx/include/mach/uncompress.h
deleted file mode 100644
index 8b4c358d2c04..000000000000
--- a/arch/arm/mach-ixp23xx/include/mach/uncompress.h
+++ /dev/null
@@ -1,40 +0,0 @@
1/*
2 * arch/arm/mach-ixp23xx/include/mach/uncompress.h
3 *
4 * Copyright (C) 2002-2004 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_UNCOMPRESS_H
12#define __ASM_ARCH_UNCOMPRESS_H
13
14#include <mach/ixp23xx.h>
15#include <linux/serial_reg.h>
16
17#define UART_BASE ((volatile u32 *)IXP23XX_UART1_PHYS)
18
19static inline void putc(char c)
20{
21 int j;
22
23 for (j = 0; j < 0x1000; j++) {
24 if (UART_BASE[UART_LSR] & UART_LSR_THRE)
25 break;
26 barrier();
27 }
28
29 UART_BASE[UART_TX] = c;
30}
31
32static inline void flush(void)
33{
34}
35
36#define arch_decomp_setup()
37#define arch_decomp_wdog()
38
39
40#endif
diff --git a/arch/arm/mach-ixp23xx/ixdp2351.c b/arch/arm/mach-ixp23xx/ixdp2351.c
deleted file mode 100644
index b0e07db5ceaf..000000000000
--- a/arch/arm/mach-ixp23xx/ixdp2351.c
+++ /dev/null
@@ -1,347 +0,0 @@
1/*
2 * arch/arm/mach-ixp23xx/ixdp2351.c
3 *
4 * IXDP2351 board-specific routines
5 *
6 * Author: Deepak Saxena <dsaxena@plexity.net>
7 *
8 * Copyright 2005 (c) MontaVista Software, Inc.
9 *
10 * Based on 2.4 code Copyright 2004 (c) Intel Corporation
11 *
12 * This file is licensed under the terms of the GNU General Public
13 * License version 2. This program is licensed "as is" without any
14 * warranty of any kind, whether express or implied.
15 */
16
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/spinlock.h>
20#include <linux/sched.h>
21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/serial.h>
24#include <linux/tty.h>
25#include <linux/bitops.h>
26#include <linux/ioport.h>
27#include <linux/serial_8250.h>
28#include <linux/serial_core.h>
29#include <linux/device.h>
30#include <linux/mm.h>
31#include <linux/pci.h>
32#include <linux/mtd/physmap.h>
33
34#include <asm/types.h>
35#include <asm/setup.h>
36#include <asm/memory.h>
37#include <mach/hardware.h>
38#include <asm/mach-types.h>
39#include <asm/tlbflush.h>
40#include <asm/pgtable.h>
41
42#include <asm/mach/map.h>
43#include <asm/mach/irq.h>
44#include <asm/mach/arch.h>
45#include <asm/mach/pci.h>
46
47/*
48 * IXDP2351 Interrupt Handling
49 */
50static void ixdp2351_inta_mask(struct irq_data *d)
51{
52 *IXDP2351_CPLD_INTA_MASK_SET_REG = IXDP2351_INTA_IRQ_MASK(d->irq);
53}
54
55static void ixdp2351_inta_unmask(struct irq_data *d)
56{
57 *IXDP2351_CPLD_INTA_MASK_CLR_REG = IXDP2351_INTA_IRQ_MASK(d->irq);
58}
59
60static void ixdp2351_inta_handler(unsigned int irq, struct irq_desc *desc)
61{
62 u16 ex_interrupt =
63 *IXDP2351_CPLD_INTA_STAT_REG & IXDP2351_INTA_IRQ_VALID;
64 int i;
65
66 desc->irq_data.chip->irq_mask(&desc->irq_data);
67
68 for (i = 0; i < IXDP2351_INTA_IRQ_NUM; i++) {
69 if (ex_interrupt & (1 << i)) {
70 int cpld_irq =
71 IXP23XX_MACH_IRQ(IXDP2351_INTA_IRQ_BASE + i);
72 generic_handle_irq(cpld_irq);
73 }
74 }
75
76 desc->irq_data.chip->irq_unmask(&desc->irq_data);
77}
78
79static struct irq_chip ixdp2351_inta_chip = {
80 .irq_ack = ixdp2351_inta_mask,
81 .irq_mask = ixdp2351_inta_mask,
82 .irq_unmask = ixdp2351_inta_unmask
83};
84
85static void ixdp2351_intb_mask(struct irq_data *d)
86{
87 *IXDP2351_CPLD_INTB_MASK_SET_REG = IXDP2351_INTB_IRQ_MASK(d->irq);
88}
89
90static void ixdp2351_intb_unmask(struct irq_data *d)
91{
92 *IXDP2351_CPLD_INTB_MASK_CLR_REG = IXDP2351_INTB_IRQ_MASK(d->irq);
93}
94
95static void ixdp2351_intb_handler(unsigned int irq, struct irq_desc *desc)
96{
97 u16 ex_interrupt =
98 *IXDP2351_CPLD_INTB_STAT_REG & IXDP2351_INTB_IRQ_VALID;
99 int i;
100
101 desc->irq_data.chip->irq_ack(&desc->irq_data);
102
103 for (i = 0; i < IXDP2351_INTB_IRQ_NUM; i++) {
104 if (ex_interrupt & (1 << i)) {
105 int cpld_irq =
106 IXP23XX_MACH_IRQ(IXDP2351_INTB_IRQ_BASE + i);
107 generic_handle_irq(cpld_irq);
108 }
109 }
110
111 desc->irq_data.chip->irq_unmask(&desc->irq_data);
112}
113
114static struct irq_chip ixdp2351_intb_chip = {
115 .irq_ack = ixdp2351_intb_mask,
116 .irq_mask = ixdp2351_intb_mask,
117 .irq_unmask = ixdp2351_intb_unmask
118};
119
120void __init ixdp2351_init_irq(void)
121{
122 int irq;
123
124 /* Mask all interrupts from CPLD, disable simulation */
125 *IXDP2351_CPLD_INTA_MASK_SET_REG = (u16) -1;
126 *IXDP2351_CPLD_INTB_MASK_SET_REG = (u16) -1;
127 *IXDP2351_CPLD_INTA_SIM_REG = 0;
128 *IXDP2351_CPLD_INTB_SIM_REG = 0;
129
130 ixp23xx_init_irq();
131
132 for (irq = IXP23XX_MACH_IRQ(IXDP2351_INTA_IRQ_BASE);
133 irq <
134 IXP23XX_MACH_IRQ(IXDP2351_INTA_IRQ_BASE + IXDP2351_INTA_IRQ_NUM);
135 irq++) {
136 if (IXDP2351_INTA_IRQ_MASK(irq) & IXDP2351_INTA_IRQ_VALID) {
137 set_irq_flags(irq, IRQF_VALID);
138 irq_set_chip_and_handler(irq, &ixdp2351_inta_chip,
139 handle_level_irq);
140 }
141 }
142
143 for (irq = IXP23XX_MACH_IRQ(IXDP2351_INTB_IRQ_BASE);
144 irq <
145 IXP23XX_MACH_IRQ(IXDP2351_INTB_IRQ_BASE + IXDP2351_INTB_IRQ_NUM);
146 irq++) {
147 if (IXDP2351_INTB_IRQ_MASK(irq) & IXDP2351_INTB_IRQ_VALID) {
148 set_irq_flags(irq, IRQF_VALID);
149 irq_set_chip_and_handler(irq, &ixdp2351_intb_chip,
150 handle_level_irq);
151 }
152 }
153
154 irq_set_chained_handler(IRQ_IXP23XX_INTA, ixdp2351_inta_handler);
155 irq_set_chained_handler(IRQ_IXP23XX_INTB, ixdp2351_intb_handler);
156}
157
158/*
159 * IXDP2351 PCI
160 */
161
162/*
163 * This board does not do normal PCI IRQ routing, or any
164 * sort of swizzling, so we just need to check where on the
165 * bus the device is and figure out what CPLD pin it is
166 * being routed to.
167 */
168#define DEVPIN(dev, pin) ((pin) | ((dev) << 3))
169
170static int __init ixdp2351_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
171{
172 u8 bus = dev->bus->number;
173 u32 devpin = DEVPIN(PCI_SLOT(dev->devfn), pin);
174 struct pci_bus *tmp_bus = dev->bus;
175
176 /* Primary bus, no interrupts here */
177 if (!bus)
178 return -1;
179
180 /* Lookup first leaf in bus tree */
181 while ((tmp_bus->parent != NULL) && (tmp_bus->parent->parent != NULL))
182 tmp_bus = tmp_bus->parent;
183
184 /* Select between known bridges */
185 switch (tmp_bus->self->devfn | (tmp_bus->self->bus->number << 8)) {
186 /* Device is located after first bridge */
187 case 0x0008:
188 if (tmp_bus == dev->bus) {
189 /* Device is located directy after first bridge */
190 switch (devpin) {
191 /* Onboard 82546 */
192 case DEVPIN(1, 1): /* Onboard 82546 ch 0 */
193 return IRQ_IXDP2351_INTA_82546;
194 case DEVPIN(1, 2): /* Onboard 82546 ch 1 */
195 return IRQ_IXDP2351_INTB_82546;
196 /* PMC SLOT */
197 case DEVPIN(0, 1): /* PMCP INTA# */
198 case DEVPIN(2, 4): /* PMCS INTD# */
199 return IRQ_IXDP2351_SPCI_PMC_INTA;
200 case DEVPIN(0, 2): /* PMCP INTB# */
201 case DEVPIN(2, 1): /* PMCS INTA# */
202 return IRQ_IXDP2351_SPCI_PMC_INTB;
203 case DEVPIN(0, 3): /* PMCP INTC# */
204 case DEVPIN(2, 2): /* PMCS INTB# */
205 return IRQ_IXDP2351_SPCI_PMC_INTC;
206 case DEVPIN(0, 4): /* PMCP INTD# */
207 case DEVPIN(2, 3): /* PMCS INTC# */
208 return IRQ_IXDP2351_SPCI_PMC_INTD;
209 }
210 } else {
211 /* Device is located indirectly after first bridge */
212 /* Not supported now */
213 return -1;
214 }
215 break;
216 case 0x0010:
217 if (tmp_bus == dev->bus) {
218 /* Device is located directy after second bridge */
219 /* Secondary bus of second bridge */
220 switch (devpin) {
221 case DEVPIN(0, 1): /* DB#0 */
222 case DEVPIN(0, 2):
223 case DEVPIN(0, 3):
224 case DEVPIN(0, 4):
225 return IRQ_IXDP2351_SPCI_DB_0;
226 case DEVPIN(1, 1): /* DB#1 */
227 case DEVPIN(1, 2):
228 case DEVPIN(1, 3):
229 case DEVPIN(1, 4):
230 return IRQ_IXDP2351_SPCI_DB_1;
231 case DEVPIN(2, 1): /* FIC1 */
232 case DEVPIN(2, 2):
233 case DEVPIN(2, 3):
234 case DEVPIN(2, 4):
235 case DEVPIN(3, 1): /* FIC2 */
236 case DEVPIN(3, 2):
237 case DEVPIN(3, 3):
238 case DEVPIN(3, 4):
239 return IRQ_IXDP2351_SPCI_FIC;
240 }
241 } else {
242 /* Device is located indirectly after second bridge */
243 /* Not supported now */
244 return -1;
245 }
246 break;
247 }
248
249 return -1;
250}
251
252struct hw_pci ixdp2351_pci __initdata = {
253 .nr_controllers = 1,
254 .preinit = ixp23xx_pci_preinit,
255 .setup = ixp23xx_pci_setup,
256 .scan = ixp23xx_pci_scan_bus,
257 .map_irq = ixdp2351_map_irq,
258};
259
260int __init ixdp2351_pci_init(void)
261{
262 if (machine_is_ixdp2351())
263 pci_common_init(&ixdp2351_pci);
264
265 return 0;
266}
267
268subsys_initcall(ixdp2351_pci_init);
269
270/*
271 * IXDP2351 Static Mapped I/O
272 */
273static struct map_desc ixdp2351_io_desc[] __initdata = {
274 {
275 .virtual = IXDP2351_NP_VIRT_BASE,
276 .pfn = __phys_to_pfn((u64)IXDP2351_NP_PHYS_BASE),
277 .length = IXDP2351_NP_PHYS_SIZE,
278 .type = MT_DEVICE
279 }, {
280 .virtual = IXDP2351_BB_BASE_VIRT,
281 .pfn = __phys_to_pfn((u64)IXDP2351_BB_BASE_PHYS),
282 .length = IXDP2351_BB_SIZE,
283 .type = MT_DEVICE
284 }
285};
286
287static void __init ixdp2351_map_io(void)
288{
289 ixp23xx_map_io();
290 iotable_init(ixdp2351_io_desc, ARRAY_SIZE(ixdp2351_io_desc));
291}
292
293static struct physmap_flash_data ixdp2351_flash_data = {
294 .width = 1,
295};
296
297static struct resource ixdp2351_flash_resource = {
298 .start = 0x90000000,
299 .end = 0x93ffffff,
300 .flags = IORESOURCE_MEM,
301};
302
303static struct platform_device ixdp2351_flash = {
304 .name = "physmap-flash",
305 .id = 0,
306 .dev = {
307 .platform_data = &ixdp2351_flash_data,
308 },
309 .num_resources = 1,
310 .resource = &ixdp2351_flash_resource,
311};
312
313static void __init ixdp2351_init(void)
314{
315 platform_device_register(&ixdp2351_flash);
316
317 /*
318 * Mark flash as writeable
319 */
320 IXP23XX_EXP_CS0[0] |= IXP23XX_FLASH_WRITABLE;
321 IXP23XX_EXP_CS0[1] |= IXP23XX_FLASH_WRITABLE;
322 IXP23XX_EXP_CS0[2] |= IXP23XX_FLASH_WRITABLE;
323 IXP23XX_EXP_CS0[3] |= IXP23XX_FLASH_WRITABLE;
324
325 ixp23xx_sys_init();
326}
327
328static void ixdp2351_restart(char mode, const char *cmd)
329{
330 /* First try machine specific support */
331
332 *IXDP2351_CPLD_RESET1_REG = IXDP2351_CPLD_RESET1_MAGIC;
333 (void) *IXDP2351_CPLD_RESET1_REG;
334 *IXDP2351_CPLD_RESET1_REG = IXDP2351_CPLD_RESET1_ENABLE;
335
336 ixp23xx_restart(mode, cmd);
337}
338
339MACHINE_START(IXDP2351, "Intel IXDP2351 Development Platform")
340 /* Maintainer: MontaVista Software, Inc. */
341 .map_io = ixdp2351_map_io,
342 .init_irq = ixdp2351_init_irq,
343 .timer = &ixp23xx_timer,
344 .atag_offset = 0x100,
345 .init_machine = ixdp2351_init,
346 .restart = ixdp2351_restart,
347MACHINE_END
diff --git a/arch/arm/mach-ixp23xx/pci.c b/arch/arm/mach-ixp23xx/pci.c
deleted file mode 100644
index 911f5a58e006..000000000000
--- a/arch/arm/mach-ixp23xx/pci.c
+++ /dev/null
@@ -1,294 +0,0 @@
1/*
2 * arch/arm/mach-ixp23xx/pci.c
3 *
4 * PCI routines for IXP23XX based systems
5 *
6 * Copyright (c) 2005 MontaVista Software, Inc.
7 *
8 * based on original code:
9 *
10 * Author: Naeem Afzal <naeem.m.afzal@intel.com>
11 * Copyright 2002-2005 Intel Corp.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 */
18
19#include <linux/sched.h>
20#include <linux/kernel.h>
21#include <linux/pci.h>
22#include <linux/interrupt.h>
23#include <linux/mm.h>
24#include <linux/init.h>
25#include <linux/ioport.h>
26#include <linux/delay.h>
27#include <linux/io.h>
28
29#include <asm/irq.h>
30#include <asm/sizes.h>
31#include <asm/mach/pci.h>
32#include <mach/hardware.h>
33
34extern int (*external_fault) (unsigned long, struct pt_regs *);
35
36static volatile int pci_master_aborts = 0;
37
38#ifdef DEBUG
39#define DBG(x...) printk(x)
40#else
41#define DBG(x...)
42#endif
43
44int clear_master_aborts(void);
45
46static u32
47*ixp23xx_pci_config_addr(unsigned int bus_nr, unsigned int devfn, int where)
48{
49 u32 *paddress;
50
51 /*
52 * Must be dword aligned
53 */
54 where &= ~3;
55
56 /*
57 * For top bus, generate type 0, else type 1
58 */
59 if (!bus_nr) {
60 if (PCI_SLOT(devfn) >= 8)
61 return 0;
62
63 paddress = (u32 *) (IXP23XX_PCI_CFG0_VIRT
64 | (1 << (PCI_SLOT(devfn) + 16))
65 | (PCI_FUNC(devfn) << 8) | where);
66 } else {
67 paddress = (u32 *) (IXP23XX_PCI_CFG1_VIRT
68 | (bus_nr << 16)
69 | (PCI_SLOT(devfn) << 11)
70 | (PCI_FUNC(devfn) << 8) | where);
71 }
72
73 return paddress;
74}
75
76/*
77 * Mask table, bits to mask for quantity of size 1, 2 or 4 bytes.
78 * 0 and 3 are not valid indexes...
79 */
80static u32 bytemask[] = {
81 /*0*/ 0,
82 /*1*/ 0xff,
83 /*2*/ 0xffff,
84 /*3*/ 0,
85 /*4*/ 0xffffffff,
86};
87
88static int ixp23xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
89 int where, int size, u32 *value)
90{
91 u32 n;
92 u32 *addr;
93
94 n = where % 4;
95
96 DBG("In config_read(%d) %d from dev %d:%d:%d\n", size, where,
97 bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
98
99 addr = ixp23xx_pci_config_addr(bus->number, devfn, where);
100 if (!addr)
101 return PCIBIOS_DEVICE_NOT_FOUND;
102
103 pci_master_aborts = 0;
104 *value = (*addr >> (8*n)) & bytemask[size];
105 if (pci_master_aborts) {
106 pci_master_aborts = 0;
107 *value = 0xffffffff;
108 return PCIBIOS_DEVICE_NOT_FOUND;
109 }
110
111 return PCIBIOS_SUCCESSFUL;
112}
113
114/*
115 * We don't do error checking on the address for writes.
116 * It's assumed that the user checked for the device existing first
117 * by doing a read first.
118 */
119static int ixp23xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
120 int where, int size, u32 value)
121{
122 u32 mask;
123 u32 *addr;
124 u32 temp;
125
126 mask = ~(bytemask[size] << ((where % 0x4) * 8));
127 addr = ixp23xx_pci_config_addr(bus->number, devfn, where);
128 if (!addr)
129 return PCIBIOS_DEVICE_NOT_FOUND;
130 temp = (u32) (value) << ((where % 0x4) * 8);
131 *addr = (*addr & mask) | temp;
132
133 clear_master_aborts();
134
135 return PCIBIOS_SUCCESSFUL;
136}
137
138struct pci_ops ixp23xx_pci_ops = {
139 .read = ixp23xx_pci_read_config,
140 .write = ixp23xx_pci_write_config,
141};
142
143struct pci_bus *ixp23xx_pci_scan_bus(int nr, struct pci_sys_data *sysdata)
144{
145 return pci_scan_root_bus(NULL, sysdata->busnr, &ixp23xx_pci_ops,
146 sysdata, &sysdata->resources);
147}
148
149int ixp23xx_pci_abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
150{
151 volatile unsigned long temp;
152 unsigned long flags;
153
154 pci_master_aborts = 1;
155
156 local_irq_save(flags);
157 temp = *IXP23XX_PCI_CONTROL;
158
159 /*
160 * master abort and cmd tgt err
161 */
162 if (temp & ((1 << 8) | (1 << 5)))
163 *IXP23XX_PCI_CONTROL = temp;
164
165 temp = *IXP23XX_PCI_CMDSTAT;
166
167 if (temp & (1 << 29))
168 *IXP23XX_PCI_CMDSTAT = temp;
169 local_irq_restore(flags);
170
171 /*
172 * If it was an imprecise abort, then we need to correct the
173 * return address to be _after_ the instruction.
174 */
175 if (fsr & (1 << 10))
176 regs->ARM_pc += 4;
177
178 return 0;
179}
180
181int clear_master_aborts(void)
182{
183 volatile u32 temp;
184
185 temp = *IXP23XX_PCI_CONTROL;
186
187 /*
188 * master abort and cmd tgt err
189 */
190 if (temp & ((1 << 8) | (1 << 5)))
191 *IXP23XX_PCI_CONTROL = temp;
192
193 temp = *IXP23XX_PCI_CMDSTAT;
194
195 if (temp & (1 << 29))
196 *IXP23XX_PCI_CMDSTAT = temp;
197
198 return 0;
199}
200
201static void __init ixp23xx_pci_common_init(void)
202{
203#ifdef __ARMEB__
204 *IXP23XX_PCI_CONTROL |= 0x20000; /* set I/O swapping */
205#endif
206 /*
207 * ADDR_31 needs to be clear for PCI memory access to CPP memory
208 */
209 *IXP23XX_CPP2XSI_CURR_XFER_REG3 &= ~IXP23XX_CPP2XSI_ADDR_31;
210 *IXP23XX_CPP2XSI_CURR_XFER_REG3 |= IXP23XX_CPP2XSI_PSH_OFF;
211
212 /*
213 * Select correct memory for PCI inbound transactions
214 */
215 if (ixp23xx_cpp_boot()) {
216 *IXP23XX_PCI_CPP_ADDR_BITS &= ~(1 << 1);
217 } else {
218 *IXP23XX_PCI_CPP_ADDR_BITS |= (1 << 1);
219
220 /*
221 * Enable coherency on A2 silicon.
222 */
223 if (arch_is_coherent())
224 *IXP23XX_CPP2XSI_CURR_XFER_REG3 &= ~IXP23XX_CPP2XSI_COH_OFF;
225 }
226}
227
228void __init ixp23xx_pci_preinit(void)
229{
230 pcibios_min_io = 0;
231 pcibios_min_mem = 0xe0000000;
232
233 pci_set_flags(0);
234
235 ixp23xx_pci_common_init();
236
237 hook_fault_code(16+6, ixp23xx_pci_abort_handler, SIGBUS, 0,
238 "PCI config cycle to non-existent device");
239
240 *IXP23XX_PCI_ADDR_EXT = 0x0000e000;
241}
242
243/*
244 * Prevent PCI layer from seeing the inbound host-bridge resources
245 */
246static void __devinit pci_fixup_ixp23xx(struct pci_dev *dev)
247{
248 int i;
249
250 dev->class &= 0xff;
251 dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
252 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
253 dev->resource[i].start = 0;
254 dev->resource[i].end = 0;
255 dev->resource[i].flags = 0;
256 }
257}
258DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9002, pci_fixup_ixp23xx);
259
260/*
261 * IXP2300 systems often have large resource requirements, so we just
262 * use our own resource space.
263 */
264static struct resource ixp23xx_pci_mem_space = {
265 .start = IXP23XX_PCI_MEM_START,
266 .end = IXP23XX_PCI_MEM_START + IXP23XX_PCI_MEM_SIZE - 1,
267 .flags = IORESOURCE_MEM,
268 .name = "PCI Mem Space"
269};
270
271static struct resource ixp23xx_pci_io_space = {
272 .start = 0x00000100,
273 .end = 0x01ffffff,
274 .flags = IORESOURCE_IO,
275 .name = "PCI I/O Space"
276};
277
278int ixp23xx_pci_setup(int nr, struct pci_sys_data *sys)
279{
280 if (nr >= 1)
281 return 0;
282
283 pci_add_resource_offset(&sys->resources,
284 &ixp23xx_pci_io_space, sys->io_offset);
285 pci_add_resource_offset(&sys->resources,
286 &ixp23xx_pci_mem_space, sys->mem_offset);
287
288 return 1;
289}
290
291void __init ixp23xx_pci_slave_init(void)
292{
293 ixp23xx_pci_common_init();
294}
diff --git a/arch/arm/mach-ixp23xx/roadrunner.c b/arch/arm/mach-ixp23xx/roadrunner.c
deleted file mode 100644
index eaaa3fa9fd05..000000000000
--- a/arch/arm/mach-ixp23xx/roadrunner.c
+++ /dev/null
@@ -1,180 +0,0 @@
1/*
2 * arch/arm/mach-ixp23xx/roadrunner.c
3 *
4 * RoadRunner board-specific routines
5 *
6 * Author: Deepak Saxena <dsaxena@plexity.net>
7 *
8 * Copyright 2005 (c) MontaVista Software, Inc.
9 *
10 * Based on 2.4 code Copyright 2005 (c) ADI Engineering Corporation
11 *
12 * This file is licensed under the terms of the GNU General Public
13 * License version 2. This program is licensed "as is" without any
14 * warranty of any kind, whether express or implied.
15 */
16
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/spinlock.h>
20#include <linux/sched.h>
21#include <linux/interrupt.h>
22#include <linux/serial.h>
23#include <linux/tty.h>
24#include <linux/bitops.h>
25#include <linux/ioport.h>
26#include <linux/serial_8250.h>
27#include <linux/serial_core.h>
28#include <linux/device.h>
29#include <linux/mm.h>
30#include <linux/pci.h>
31#include <linux/mtd/physmap.h>
32
33#include <asm/types.h>
34#include <asm/setup.h>
35#include <asm/memory.h>
36#include <mach/hardware.h>
37#include <asm/mach-types.h>
38#include <asm/irq.h>
39#include <asm/tlbflush.h>
40#include <asm/pgtable.h>
41
42#include <asm/mach/map.h>
43#include <asm/mach/irq.h>
44#include <asm/mach/arch.h>
45#include <asm/mach/pci.h>
46
47/*
48 * Interrupt mapping
49 */
50#define INTA IRQ_ROADRUNNER_PCI_INTA
51#define INTB IRQ_ROADRUNNER_PCI_INTB
52#define INTC IRQ_ROADRUNNER_PCI_INTC
53#define INTD IRQ_ROADRUNNER_PCI_INTD
54
55#define INTC_PIN IXP23XX_GPIO_PIN_11
56#define INTD_PIN IXP23XX_GPIO_PIN_12
57
58static int __init roadrunner_map_irq(const struct pci_dev *dev, u8 idsel,
59 u8 pin)
60{
61 static int pci_card_slot_irq[] = {INTB, INTC, INTD, INTA};
62 static int pmc_card_slot_irq[] = {INTA, INTB, INTC, INTD};
63 static int usb_irq[] = {INTB, INTC, INTD, -1};
64 static int mini_pci_1_irq[] = {INTB, INTC, -1, -1};
65 static int mini_pci_2_irq[] = {INTC, INTD, -1, -1};
66
67 switch(dev->bus->number) {
68 case 0:
69 switch(dev->devfn) {
70 case 0x0: // PCI-PCI bridge
71 break;
72 case 0x8: // PCI Card Slot
73 return pci_card_slot_irq[pin - 1];
74 case 0x10: // PMC Slot
75 return pmc_card_slot_irq[pin - 1];
76 case 0x18: // PMC Slot Secondary Agent
77 break;
78 case 0x20: // IXP Processor
79 break;
80 default:
81 return NO_IRQ;
82 }
83 break;
84
85 case 1:
86 switch(dev->devfn) {
87 case 0x0: // IDE Controller
88 return (pin == 1) ? INTC : -1;
89 case 0x8: // USB fun 0
90 case 0x9: // USB fun 1
91 case 0xa: // USB fun 2
92 return usb_irq[pin - 1];
93 case 0x10: // Mini PCI 1
94 return mini_pci_1_irq[pin-1];
95 case 0x18: // Mini PCI 2
96 return mini_pci_2_irq[pin-1];
97 case 0x20: // MEM slot
98 return (pin == 1) ? INTA : -1;
99 default:
100 return NO_IRQ;
101 }
102 break;
103
104 default:
105 return NO_IRQ;
106 }
107
108 return NO_IRQ;
109}
110
111static void __init roadrunner_pci_preinit(void)
112{
113 irq_set_irq_type(IRQ_ROADRUNNER_PCI_INTC, IRQ_TYPE_LEVEL_LOW);
114 irq_set_irq_type(IRQ_ROADRUNNER_PCI_INTD, IRQ_TYPE_LEVEL_LOW);
115
116 ixp23xx_pci_preinit();
117}
118
119static struct hw_pci roadrunner_pci __initdata = {
120 .nr_controllers = 1,
121 .preinit = roadrunner_pci_preinit,
122 .setup = ixp23xx_pci_setup,
123 .scan = ixp23xx_pci_scan_bus,
124 .map_irq = roadrunner_map_irq,
125};
126
127static int __init roadrunner_pci_init(void)
128{
129 if (machine_is_roadrunner())
130 pci_common_init(&roadrunner_pci);
131
132 return 0;
133};
134
135subsys_initcall(roadrunner_pci_init);
136
137static struct physmap_flash_data roadrunner_flash_data = {
138 .width = 2,
139};
140
141static struct resource roadrunner_flash_resource = {
142 .start = 0x90000000,
143 .end = 0x93ffffff,
144 .flags = IORESOURCE_MEM,
145};
146
147static struct platform_device roadrunner_flash = {
148 .name = "physmap-flash",
149 .id = 0,
150 .dev = {
151 .platform_data = &roadrunner_flash_data,
152 },
153 .num_resources = 1,
154 .resource = &roadrunner_flash_resource,
155};
156
157static void __init roadrunner_init(void)
158{
159 platform_device_register(&roadrunner_flash);
160
161 /*
162 * Mark flash as writeable
163 */
164 IXP23XX_EXP_CS0[0] |= IXP23XX_FLASH_WRITABLE;
165 IXP23XX_EXP_CS0[1] |= IXP23XX_FLASH_WRITABLE;
166 IXP23XX_EXP_CS0[2] |= IXP23XX_FLASH_WRITABLE;
167 IXP23XX_EXP_CS0[3] |= IXP23XX_FLASH_WRITABLE;
168
169 ixp23xx_sys_init();
170}
171
172MACHINE_START(ROADRUNNER, "ADI Engineering RoadRunner Development Platform")
173 /* Maintainer: Deepak Saxena */
174 .map_io = ixp23xx_map_io,
175 .init_irq = ixp23xx_init_irq,
176 .timer = &ixp23xx_timer,
177 .atag_offset = 0x100,
178 .init_machine = roadrunner_init,
179 .restart = ixp23xx_restart,
180MACHINE_END
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-31 22:40:41 -0400