diff options
author | Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> | 2007-07-29 22:54:41 -0400 |
---|---|---|
committer | Tony Luck <tony.luck@intel.com> | 2007-07-30 19:29:47 -0400 |
commit | c4c376f7e16deeba8f0542eabcaca19b712e7be1 (patch) | |
tree | 96a3d14bcfd6742093d5eaa2ca7d79b613978a5b /arch | |
parent | 1b30859b8d42b3161954a81da7f96055a4617220 (diff) |
[IA64] Fix registered interrupt check
Fix the problem that interrupts are not initialized correctly at PCI
hotplug or driver reloading time.
By vector domain change, the iosapic_rte_info structure was changed to
be on the iosapic_intr_info[irq].rtes list even after the interrupts
are unregistered. So iosapic_intr_info[irq].rtes list must not be
checked to see if there are registered interrupts (RTEs) on the
irq. We must check iosapic_intr_info[irq].count counter instead.
Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/ia64/kernel/iosapic.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/ia64/kernel/iosapic.c b/arch/ia64/kernel/iosapic.c index f4bd285effe6..5f6d98e866ea 100644 --- a/arch/ia64/kernel/iosapic.c +++ b/arch/ia64/kernel/iosapic.c | |||
@@ -142,7 +142,7 @@ struct iosapic_rte_info { | |||
142 | static struct iosapic_intr_info { | 142 | static struct iosapic_intr_info { |
143 | struct list_head rtes; /* RTEs using this vector (empty => | 143 | struct list_head rtes; /* RTEs using this vector (empty => |
144 | * not an IOSAPIC interrupt) */ | 144 | * not an IOSAPIC interrupt) */ |
145 | int count; /* # of RTEs that shares this vector */ | 145 | int count; /* # of registered RTEs */ |
146 | u32 low32; /* current value of low word of | 146 | u32 low32; /* current value of low word of |
147 | * Redirection table entry */ | 147 | * Redirection table entry */ |
148 | unsigned int dest; /* destination CPU physical ID */ | 148 | unsigned int dest; /* destination CPU physical ID */ |
@@ -313,7 +313,7 @@ mask_irq (unsigned int irq) | |||
313 | int rte_index; | 313 | int rte_index; |
314 | struct iosapic_rte_info *rte; | 314 | struct iosapic_rte_info *rte; |
315 | 315 | ||
316 | if (list_empty(&iosapic_intr_info[irq].rtes)) | 316 | if (!iosapic_intr_info[irq].count) |
317 | return; /* not an IOSAPIC interrupt! */ | 317 | return; /* not an IOSAPIC interrupt! */ |
318 | 318 | ||
319 | /* set only the mask bit */ | 319 | /* set only the mask bit */ |
@@ -331,7 +331,7 @@ unmask_irq (unsigned int irq) | |||
331 | int rte_index; | 331 | int rte_index; |
332 | struct iosapic_rte_info *rte; | 332 | struct iosapic_rte_info *rte; |
333 | 333 | ||
334 | if (list_empty(&iosapic_intr_info[irq].rtes)) | 334 | if (!iosapic_intr_info[irq].count) |
335 | return; /* not an IOSAPIC interrupt! */ | 335 | return; /* not an IOSAPIC interrupt! */ |
336 | 336 | ||
337 | low32 = iosapic_intr_info[irq].low32 &= ~IOSAPIC_MASK; | 337 | low32 = iosapic_intr_info[irq].low32 &= ~IOSAPIC_MASK; |
@@ -363,7 +363,7 @@ iosapic_set_affinity (unsigned int irq, cpumask_t mask) | |||
363 | 363 | ||
364 | dest = cpu_physical_id(first_cpu(mask)); | 364 | dest = cpu_physical_id(first_cpu(mask)); |
365 | 365 | ||
366 | if (list_empty(&iosapic_intr_info[irq].rtes)) | 366 | if (!iosapic_intr_info[irq].count) |
367 | return; /* not an IOSAPIC interrupt */ | 367 | return; /* not an IOSAPIC interrupt */ |
368 | 368 | ||
369 | set_irq_affinity_info(irq, dest, redir); | 369 | set_irq_affinity_info(irq, dest, redir); |
@@ -542,7 +542,7 @@ iosapic_reassign_vector (int irq) | |||
542 | { | 542 | { |
543 | int new_irq; | 543 | int new_irq; |
544 | 544 | ||
545 | if (!list_empty(&iosapic_intr_info[irq].rtes)) { | 545 | if (iosapic_intr_info[irq].count) { |
546 | new_irq = create_irq(); | 546 | new_irq = create_irq(); |
547 | if (new_irq < 0) | 547 | if (new_irq < 0) |
548 | panic("%s: out of interrupt vectors!\n", __FUNCTION__); | 548 | panic("%s: out of interrupt vectors!\n", __FUNCTION__); |
@@ -677,7 +677,7 @@ get_target_cpu (unsigned int gsi, int irq) | |||
677 | * In case of vector shared by multiple RTEs, all RTEs that | 677 | * In case of vector shared by multiple RTEs, all RTEs that |
678 | * share the vector need to use the same destination CPU. | 678 | * share the vector need to use the same destination CPU. |
679 | */ | 679 | */ |
680 | if (!list_empty(&iosapic_intr_info[irq].rtes)) | 680 | if (iosapic_intr_info[irq].count) |
681 | return iosapic_intr_info[irq].dest; | 681 | return iosapic_intr_info[irq].dest; |
682 | 682 | ||
683 | /* | 683 | /* |