aboutsummaryrefslogtreecommitdiffstats
path: root/arch
diff options
context:
space:
mode:
authorJames Hogan <james.hogan@imgtec.com>2012-12-05 06:03:52 -0500
committerJames Hogan <james.hogan@imgtec.com>2013-03-02 15:09:16 -0500
commitaf8a10493e35c6c53c21ff33fd36c0ce789bd000 (patch)
treeab45d08cdad8ede4405a0fd3f2d0eb442d5613a5 /arch
parent1228594528faf432ddc3eb51bccaf6a0d80bfc27 (diff)
metag: Headers for core arch constants
Add a couple of header files containing core architecture constants. The first (<asm/metag_isa.h>) contains some constants relating to the instruction set, such as values to give to the CACHEW and CACHER instructions. The second (<asm/metag_regs.h>) contains constants for the core register units directly accessible to various instructions, and for the registers, fields, and bits in those units. The main units described are the control unit (CT.*), the trigger unit (TR.*), and the run-time trace unit (TT.*). Signed-off-by: James Hogan <james.hogan@imgtec.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/metag/include/asm/metag_isa.h81
-rw-r--r--arch/metag/include/asm/metag_regs.h1180
2 files changed, 1261 insertions, 0 deletions
diff --git a/arch/metag/include/asm/metag_isa.h b/arch/metag/include/asm/metag_isa.h
new file mode 100644
index 000000000000..c8aa2ae3899f
--- /dev/null
+++ b/arch/metag/include/asm/metag_isa.h
@@ -0,0 +1,81 @@
1/*
2 * asm/metag_isa.h
3 *
4 * Copyright (C) 2000-2007, 2012 Imagination Technologies.
5 *
6 * This program is free software; you can redistribute it and/or modify it under
7 * the terms of the GNU General Public License version 2 as published by the
8 * Free Software Foundation.
9 *
10 * Various defines for Meta instruction set.
11 */
12
13#ifndef _ASM_METAG_ISA_H_
14#define _ASM_METAG_ISA_H_
15
16
17/* L1 cache layout */
18
19/* Data cache line size as bytes and shift */
20#define DCACHE_LINE_BYTES 64
21#define DCACHE_LINE_S 6
22
23/* Number of ways in the data cache */
24#define DCACHE_WAYS 4
25
26/* Instruction cache line size as bytes and shift */
27#define ICACHE_LINE_BYTES 64
28#define ICACHE_LINE_S 6
29
30/* Number of ways in the instruction cache */
31#define ICACHE_WAYS 4
32
33
34/*
35 * CACHEWD/CACHEWL instructions use the bottom 8 bits of the data presented to
36 * control the operation actually achieved.
37 */
38/* Use of these two bits should be discouraged since the bits dont have
39 * consistent meanings
40 */
41#define CACHEW_ICACHE_BIT 0x01
42#define CACHEW_TLBFLUSH_BIT 0x02
43
44#define CACHEW_FLUSH_L1D_L2 0x0
45#define CACHEW_INVALIDATE_L1I 0x1
46#define CACHEW_INVALIDATE_L1DTLB 0x2
47#define CACHEW_INVALIDATE_L1ITLB 0x3
48#define CACHEW_WRITEBACK_L1D_L2 0x4
49#define CACHEW_INVALIDATE_L1D 0x8
50#define CACHEW_INVALIDATE_L1D_L2 0xC
51
52/*
53 * CACHERD/CACHERL instructions use bits 3:5 of the address presented to
54 * control the operation achieved and hence the specific result.
55 */
56#define CACHER_ADDR_BITS 0xFFFFFFC0
57#define CACHER_OPER_BITS 0x00000030
58#define CACHER_OPER_S 4
59#define CACHER_OPER_LINPHY 0
60#define CACHER_ICACHE_BIT 0x00000008
61#define CACHER_ICACHE_S 3
62
63/*
64 * CACHERD/CACHERL LINPHY Oper result is one/two 32-bit words
65 *
66 * If CRLINPHY0_VAL_BIT (Bit 0) set then,
67 * Lower 32-bits corresponds to MMCU_ENTRY_* above.
68 * Upper 32-bits corresponds to CRLINPHY1_* values below (if requested).
69 * else
70 * Lower 32-bits corresponds to CRLINPHY0_* values below.
71 * Upper 32-bits undefined.
72 */
73#define CRLINPHY0_VAL_BIT 0x00000001
74#define CRLINPHY0_FIRST_BIT 0x00000004 /* Set if VAL=0 due to first level */
75
76#define CRLINPHY1_READ_BIT 0x00000001 /* Set if reads permitted */
77#define CRLINPHY1_SINGLE_BIT 0x00000004 /* Set if TLB does not cache entry */
78#define CRLINPHY1_PAGEMSK_BITS 0x0000FFF0 /* Set to ((2^n-1)>>12) value */
79#define CRLINPHY1_PAGEMSK_S 4
80
81#endif /* _ASM_METAG_ISA_H_ */
diff --git a/arch/metag/include/asm/metag_regs.h b/arch/metag/include/asm/metag_regs.h
new file mode 100644
index 000000000000..022fcad768f7
--- /dev/null
+++ b/arch/metag/include/asm/metag_regs.h
@@ -0,0 +1,1180 @@
1/*
2 * asm/metag_regs.h
3 *
4 * Copyright (C) 2000-2007, 2012 Imagination Technologies.
5 *
6 * This program is free software; you can redistribute it and/or modify it under
7 * the terms of the GNU General Public License version 2 as published by the
8 * Free Software Foundation.
9 *
10 * Various defines for Meta core (non memory-mapped) registers.
11 */
12
13#ifndef _ASM_METAG_REGS_H_
14#define _ASM_METAG_REGS_H_
15
16/*
17 * CHIP Unit Identifiers and Valid/Global register number masks
18 * ------------------------------------------------------------
19 */
20#define TXUCT_ID 0x0 /* Control unit regs */
21#ifdef METAC_1_2
22#define TXUCT_MASK 0xFF0FFFFF /* Valid regs 0..31 */
23#else
24#define TXUCT_MASK 0xFF1FFFFF /* Valid regs 0..31 */
25#endif
26#define TGUCT_MASK 0x00000000 /* No global regs */
27#define TXUD0_ID 0x1 /* Data unit regs */
28#define TXUD1_ID 0x2
29#define TXUDX_MASK 0xFFFFFFFF /* Valid regs 0..31 */
30#define TGUDX_MASK 0xFFFF0000 /* Global regs for base inst */
31#define TXUDXDSP_MASK 0x0F0FFFFF /* Valid DSP regs */
32#define TGUDXDSP_MASK 0x0E0E0000 /* Global DSP ACC regs */
33#define TXUA0_ID 0x3 /* Address unit regs */
34#define TXUA1_ID 0x4
35#define TXUAX_MASK 0x0000FFFF /* Valid regs 0-15 */
36#define TGUAX_MASK 0x0000FF00 /* Global regs 8-15 */
37#define TXUPC_ID 0x5 /* PC registers */
38#define TXUPC_MASK 0x00000003 /* Valid regs 0- 1 */
39#define TGUPC_MASK 0x00000000 /* No global regs */
40#define TXUPORT_ID 0x6 /* Ports are not registers */
41#define TXUTR_ID 0x7
42#define TXUTR_MASK 0x0000005F /* Valid regs 0-3,4,6 */
43#define TGUTR_MASK 0x00000000 /* No global regs */
44#ifdef METAC_2_1
45#define TXUTT_ID 0x8
46#define TXUTT_MASK 0x0000000F /* Valid regs 0-3 */
47#define TGUTT_MASK 0x00000010 /* Global reg 4 */
48#define TXUFP_ID 0x9 /* FPU regs */
49#define TXUFP_MASK 0x0000FFFF /* Valid regs 0-15 */
50#define TGUFP_MASK 0x00000000 /* No global regs */
51#endif /* METAC_2_1 */
52
53#ifdef METAC_1_2
54#define TXUXX_MASKS { TXUCT_MASK, TXUDX_MASK, TXUDX_MASK, TXUAX_MASK, \
55 TXUAX_MASK, TXUPC_MASK, 0, TXUTR_MASK, \
56 0, 0, 0, 0, 0, 0, 0, 0 }
57#define TGUXX_MASKS { TGUCT_MASK, TGUDX_MASK, TGUDX_MASK, TGUAX_MASK, \
58 TGUAX_MASK, TGUPC_MASK, 0, TGUTR_MASK, \
59 0, 0, 0, 0, 0, 0, 0, 0 }
60#else /* METAC_1_2 */
61#define TXUXX_MASKS { TXUCT_MASK, TXUDX_MASK, TXUDX_MASK, TXUAX_MASK, \
62 TXUAX_MASK, TXUPC_MASK, 0, TXUTR_MASK, \
63 TXUTT_MASK, TXUFP_MASK, 0, 0, \
64 0, 0, 0, 0 }
65#define TGUXX_MASKS { TGUCT_MASK, TGUDX_MASK, TGUDX_MASK, TGUAX_MASK, \
66 TGUAX_MASK, TGUPC_MASK, 0, TGUTR_MASK, \
67 TGUTT_MASK, TGUFP_MASK, 0, 0, \
68 0, 0, 0, 0 }
69#endif /* !METAC_1_2 */
70
71#define TXUXXDSP_MASKS { 0, TXUDXDSP_MASK, TXUDXDSP_MASK, 0, 0, 0, 0, 0, \
72 0, 0, 0, 0, 0, 0, 0, 0 }
73#define TGUXXDSP_MASKS { 0, TGUDXDSP_MASK, TGUDXDSP_MASK, 0, 0, 0, 0, 0, \
74 0, 0, 0, 0, 0, 0, 0, 0 }
75
76/* -------------------------------------------------------------------------
77; DATA AND ADDRESS UNIT REGISTERS
78; -----------------------------------------------------------------------*/
79/*
80 Thread local D0 registers
81 */
82/* D0.0 ; Holds 32-bit result, can be used as scratch */
83#define D0Re0 D0.0
84/* D0.1 ; Used to pass Arg6_32 */
85#define D0Ar6 D0.1
86/* D0.2 ; Used to pass Arg4_32 */
87#define D0Ar4 D0.2
88/* D0.3 ; Used to pass Arg2_32 to a called routine (see D1.3 below) */
89#define D0Ar2 D0.3
90/* D0.4 ; Can be used as scratch; used to save A0FrP in entry sequences */
91#define D0FrT D0.4
92/* D0.5 ; C compiler assumes preservation, save with D1.5 if used */
93/* D0.6 ; C compiler assumes preservation, save with D1.6 if used */
94/* D0.7 ; C compiler assumes preservation, save with D1.7 if used */
95/* D0.8 ; Use of D0.8 and above is not encouraged */
96/* D0.9 */
97/* D0.10 */
98/* D0.11 */
99/* D0.12 */
100/* D0.13 */
101/* D0.14 */
102/* D0.15 */
103/*
104 Thread local D1 registers
105 */
106/* D1.0 ; Holds top 32-bits of 64-bit result, can be used as scratch */
107#define D1Re0 D1.0
108/* D1.1 ; Used to pass Arg5_32 */
109#define D1Ar5 D1.1
110/* D1.2 ; Used to pass Arg3_32 */
111#define D1Ar3 D1.2
112/* D1.3 ; Used to pass Arg1_32 (first 32-bit argument) to a called routine */
113#define D1Ar1 D1.3
114/* D1.4 ; Used for Return Pointer, save during entry with A0FrP (via D0.4) */
115#define D1RtP D1.4
116/* D1.5 ; C compiler assumes preservation, save if used */
117/* D1.6 ; C compiler assumes preservation, save if used */
118/* D1.7 ; C compiler assumes preservation, save if used */
119/* D1.8 ; Use of D1.8 and above is not encouraged */
120/* D1.9 */
121/* D1.10 */
122/* D1.11 */
123/* D1.12 */
124/* D1.13 */
125/* D1.14 */
126/* D1.15 */
127/*
128 Thread local A0 registers
129 */
130/* A0.0 ; Primary stack pointer */
131#define A0StP A0.0
132/* A0.1 ; Used as local frame pointer in C, save if used (via D0.4) */
133#define A0FrP A0.1
134/* A0.2 */
135/* A0.3 */
136/* A0.4 ; Use of A0.4 and above is not encouraged */
137/* A0.5 */
138/* A0.6 */
139/* A0.7 */
140/*
141 Thread local A1 registers
142 */
143/* A1.0 ; Global static chain pointer - do not modify */
144#define A1GbP A1.0
145/* A1.1 ; Local static chain pointer in C, can be used as scratch */
146#define A1LbP A1.1
147/* A1.2 */
148/* A1.3 */
149/* A1.4 ; Use of A1.4 and above is not encouraged */
150/* A1.5 */
151/* A1.6 */
152/* A1.7 */
153#ifdef METAC_2_1
154/* Renameable registers for use with Fast Interrupts */
155/* The interrupt stack pointer (usually a global register) */
156#define A0IStP A0IReg
157/* The interrupt global pointer (usually a global register) */
158#define A1IGbP A1IReg
159#endif
160/*
161 Further registers may be globally allocated via linkage/loading tools,
162 normally they are not used.
163 */
164/*-------------------------------------------------------------------------
165; STACK STRUCTURE and CALLING CONVENTION
166; -----------------------------------------------------------------------*/
167/*
168; Calling convention indicates that the following is the state of the
169; stack frame at the start of a routine-
170;
171; Arg9_32 [A0StP+#-12]
172; Arg8_32 [A0StP+#- 8]
173; Arg7_32 [A0StP+#- 4]
174; A0StP->
175;
176; Registers D1.3, D0.3, ..., to D0.1 are used to pass Arg1_32 to Arg6_32
177; respectively. If a routine needs to store them on the stack in order
178; to make sub-calls or because of the general complexity of the routine it
179; is best to dump these registers immediately at the start of a routine
180; using a MSETL or SETL instruction-
181;
182; MSETL [A0StP],D0Ar6,D0Ar4,D0Ar2; Only dump argments expected
183;or SETL [A0StP+#8++],D0Ar2 ; Up to two 32-bit args expected
184;
185; For non-leaf routines it is always necessary to save and restore at least
186; the return address value D1RtP on the stack. Also by convention if the
187; frame is saved then a new A0FrP value must be set-up. So for non-leaf
188; routines at this point both these registers must be saved onto the stack
189; using a SETL instruction and the new A0FrP value is then set-up-
190;
191; MOV D0FrT,A0FrP
192; ADD A0FrP,A0StP,#0
193; SETL [A0StP+#8++],D0FrT,D1RtP
194;
195; Registers D0.5, D1.5, to D1.7 are assumed to be preserved across calls so
196; a SETL or MSETL instruction can be used to save the current state
197; of these registers if they are modified by the current routine-
198;
199; MSETL [A0StP],D0.5,D0.6,D0.7 ; Only save registers modified
200;or SETL [A0StP+#8++],D0.5 ; Only D0.5 and/or D1.5 modified
201;
202; All of the above sequences can be combined into one maximal case-
203;
204; MOV D0FrT,A0FrP ; Save and calculate new frame pointer
205; ADD A0FrP,A0StP,#(ARS)
206; MSETL [A0StP],D0Ar6,D0Ar4,D0Ar2,D0FrT,D0.5,D0.6,D0.7
207;
208; Having completed the above sequence the only remaining task on routine
209; entry is to reserve any local and outgoing argment storage space on the
210; stack. This instruction may be omitted if the size of this region is zero-
211;
212; ADD A0StP,A0StP,#(LCS)
213;
214; LCS is the first example use of one of a number of standard local defined
215; values that can be created to make assembler code more readable and
216; potentially more robust-
217;
218; #define ARS 0x18 ; Register arg bytes saved on stack
219; #define FRS 0x20 ; Frame save area size in bytes
220; #define LCS 0x00 ; Locals and Outgoing arg size
221; #define ARO (LCS+FRS) ; Stack offset to access args
222;
223; All of the above defines should be undefined (#undef) at the end of each
224; routine to avoid accidental use in the next routine.
225;
226; Given all of the above the following stack structure is expected during
227; the body of a routine if all args passed in registers are saved during
228; entry-
229;
230; ; 'Incoming args area'
231; Arg10_32 [A0StP+#-((10*4)+ARO)] Arg9_32 [A0StP+#-(( 9*4)+ARO)]
232; Arg8_32 [A0StP+#-(( 8*4)+ARO)] Arg7_32 [A0StP+#-(( 7*4)+ARO)]
233;--- Call point
234; D0Ar6= Arg6_32 [A0StP+#-(( 6*4)+ARO)] D1Ar5=Arg5_32 [A0StP+#-(( 5*4)+ARO)]
235; D0Ar4= Arg4_32 [A0StP+#-(( 4*4)+ARO)] D1Ar3=Arg3_32 [A0StP+#-(( 3*4)+ARO)]
236; D0Ar2= Arg2_32 [A0StP+#-(( 2*4)+ARO)] D1Ar2=Arg1_32 [A0StP+#-(( 1*4)+ARO)]
237; ; 'Frame area'
238; A0FrP-> D0FrT, D1RtP,
239; D0.5, D1.5,
240; D0.6, D1.6,
241; D0.7, D1.7,
242; ; 'Locals area'
243; Loc0_32 [A0StP+# (( 0*4)-LCS)], Loc1_32 [A0StP+# (( 1*4)-LCS)]
244; .... other locals
245; Locn_32 [A0StP+# (( n*4)-LCS)]
246; ; 'Outgoing args area'
247; Outm_32 [A0StP+#- ( m*4)] .... other outgoing args
248; Out8_32 [A0StP+#- ( 1*4)] Out7_32 [A0StP+#- ( 1*4)]
249; A0StP-> (Out1_32-Out6_32 in regs D1Ar1-D0Ar6)
250;
251; The exit sequence for a non-leaf routine can use the frame pointer created
252; in the entry sequence to optimise the recovery of the full state-
253;
254; MGETL D0FrT,D0.5,D0.6,D0.7,[A0FrP]
255; SUB A0StP,A0FrP,#(ARS+FRS)
256; MOV A0FrP,D0FrT
257; MOV PC,D1RtP
258;
259; Having described the most complex non-leaf case above, it is worth noting
260; that if a routine is a leaf and does not use any of the caller-preserved
261; state. The routine can be implemented as-
262;
263; ADD A0StP,A0StP,#LCS
264; .... body of routine
265; SUB A0StP,A0StP,#LCS
266; MOV PC,D1RtP
267;
268; The stack adjustments can also be omitted if no local storage is required.
269;
270; Another exit sequence structure is more applicable if for a leaf routine
271; with no local frame pointer saved/generated in which the call saved
272; registers need to be saved and restored-
273;
274; MSETL [A0StP],D0.5,D0.6,D0.7 ; Hence FRS is 0x18, ARS is 0x00
275; ADD A0StP,A0StP,#LCS
276; .... body of routine
277; GETL D0.5,D1.5,[A0StP+#((0*8)-(FRS+LCS))]
278; GETL D0.6,D1.6,[A0StP+#((1*8)-(FRS+LCS))]
279; GETL D0.7,D1.7,[A0StP+#((2*8)-(FRS+LCS))]
280; SUB A0StP,A0StP,#(ARS+FRS+LCS)
281; MOV PC,D1RtP
282;
283; Lastly, to support profiling assembler code should use a fixed entry/exit
284; sequence if the trigger define _GMON_ASM is defined-
285;
286; #ifndef _GMON_ASM
287; ... optimised entry code
288; #else
289; ; Profiling entry case
290; MOV D0FrT,A0FrP ; Save and calculate new frame pointer
291; ADD A0FrP,A0StP,#(ARS)
292; MSETL [A0StP],...,D0FrT,... or SETL [A0FrP],D0FrT,D1RtP
293; CALLR D0FrT,_mcount_wrapper
294; #endif
295; ... body of routine
296; #ifndef _GMON_ASM
297; ... optimised exit code
298; #else
299; ; Profiling exit case
300; MGETL D0FrT,...,[A0FrP] or GETL D0FrT,D1RtP,[A0FrP++]
301; SUB A0StP,A0FrP,#(ARS+FRS)
302; MOV A0FrP,D0FrT
303; MOV PC,D1RtP
304; #endif
305
306
307; -------------------------------------------------------------------------
308; CONTROL UNIT REGISTERS
309; -------------------------------------------------------------------------
310;
311; See the assembler guide, hardware documentation, or the field values
312; defined below for some details of the use of these registers.
313*/
314#define TXENABLE CT.0 /* Need to define bit-field values in these */
315#define TXMODE CT.1
316#define TXSTATUS CT.2 /* DEFAULT 0x00020000 */
317#define TXRPT CT.3
318#define TXTIMER CT.4
319#define TXL1START CT.5
320#define TXL1END CT.6
321#define TXL1COUNT CT.7
322#define TXL2START CT.8
323#define TXL2END CT.9
324#define TXL2COUNT CT.10
325#define TXBPOBITS CT.11
326#define TXMRSIZE CT.12
327#define TXTIMERI CT.13
328#define TXDRCTRL CT.14 /* DEFAULT 0x0XXXF0F0 */
329#define TXDRSIZE CT.15
330#define TXCATCH0 CT.16
331#define TXCATCH1 CT.17
332#define TXCATCH2 CT.18
333#define TXCATCH3 CT.19
334
335#ifdef METAC_2_1
336#define TXDEFR CT.20
337#define TXCPRS CT.21
338#endif
339
340#define TXINTERN0 CT.23
341#define TXAMAREG0 CT.24
342#define TXAMAREG1 CT.25
343#define TXAMAREG2 CT.26
344#define TXAMAREG3 CT.27
345#define TXDIVTIME CT.28 /* DEFAULT 0x00000001 */
346#define TXPRIVEXT CT.29 /* DEFAULT 0x003B0000 */
347#define TXTACTCYC CT.30
348#define TXIDLECYC CT.31
349
350/*****************************************************************************
351 * CONTROL UNIT REGISTER BITS
352 ****************************************************************************/
353/*
354 * The following registers and where appropriate the sub-fields of those
355 * registers are defined for pervasive use in controlling program flow.
356 */
357
358/*
359 * TXENABLE register fields - only the thread id is routinely useful
360 */
361#define TXENABLE_REGNUM 0
362#define TXENABLE_THREAD_BITS 0x00000700
363#define TXENABLE_THREAD_S 8
364#define TXENABLE_REV_STEP_BITS 0x000000F0
365#define TXENABLE_REV_STEP_S 4
366
367/*
368 * TXMODE register - controls extensions of the instruction set
369 */
370#define TXMODE_REGNUM 1
371#define TXMODE_DEFAULT 0 /* All fields default to zero */
372
373/*
374 * TXSTATUS register - contains a couple of stable bits that can be used
375 * to determine the privilege processing level and interrupt
376 * processing level of the current thread.
377 */
378#define TXSTATUS_REGNUM 2
379#define TXSTATUS_PSTAT_BIT 0x00020000 /* -> Privilege active */
380#define TXSTATUS_PSTAT_S 17
381#define TXSTATUS_ISTAT_BIT 0x00010000 /* -> In interrupt state */
382#define TXSTATUS_ISTAT_S 16
383
384/*
385 * These are all relatively boring registers, mostly full 32-bit
386 */
387#define TXRPT_REGNUM 3 /* Repeat counter for XFR... instructions */
388#define TXTIMER_REGNUM 4 /* Timer-- causes timer trigger on overflow */
389#define TXL1START_REGNUM 5 /* Hardware Loop 1 Start-PC/End-PC/Count */
390#define TXL1END_REGNUM 6
391#define TXL1COUNT_REGNUM 7
392#define TXL2START_REGNUM 8 /* Hardware Loop 2 Start-PC/End-PC/Count */
393#define TXL2END_REGNUM 9
394#define TXL2COUNT_REGNUM 10
395#define TXBPOBITS_REGNUM 11 /* Branch predict override bits - tune perf */
396#define TXTIMERI_REGNUM 13 /* Timer-- time based interrupt trigger */
397
398/*
399 * TXDIVTIME register is routinely read to calculate the time-base for
400 * the TXTIMER register.
401 */
402#define TXDIVTIME_REGNUM 28
403#define TXDIVTIME_DIV_BITS 0x000000FF
404#define TXDIVTIME_DIV_S 0
405#define TXDIVTIME_DIV_MIN 0x00000001 /* Maximum resolution */
406#define TXDIVTIME_DIV_MAX 0x00000100 /* 1/1 -> 1/256 resolution */
407#define TXDIVTIME_BASE_HZ 1000000 /* Timers run at 1Mhz @1/1 */
408
409/*
410 * TXPRIVEXT register can be consulted to decide if write access to a
411 * part of the threads register set is not permitted when in
412 * unprivileged mode (PSTAT == 0).
413 */
414#define TXPRIVEXT_REGNUM 29
415#define TXPRIVEXT_COPRO_BITS 0xFF000000 /* Co-processor 0-7 */
416#define TXPRIVEXT_COPRO_S 24
417#define TXPRIVEXT_TXTRIGGER_BIT 0x00020000 /* TXSTAT|TXMASK|TXPOLL */
418#define TXPRIVEXT_TXGBLCREG_BIT 0x00010000 /* Global common regs */
419#define TXPRIVEXT_CBPRIV_BIT 0x00008000 /* Mem i/f dump priv */
420#define TXPRIVEXT_ILOCK_BIT 0x00004000 /* LOCK inst priv */
421#define TXPRIVEXT_TXITACCYC_BIT 0x00002000 /* TXIDLECYC|TXTACTCYC */
422#define TXPRIVEXT_TXDIVTIME_BIT 0x00001000 /* TXDIVTIME priv */
423#define TXPRIVEXT_TXAMAREGX_BIT 0x00000800 /* TXAMAREGX priv */
424#define TXPRIVEXT_TXTIMERI_BIT 0x00000400 /* TXTIMERI priv */
425#define TXPRIVEXT_TXSTATUS_BIT 0x00000200 /* TXSTATUS priv */
426#define TXPRIVEXT_TXDISABLE_BIT 0x00000100 /* TXENABLE priv */
427#ifndef METAC_1_2
428#define TXPRIVEXT_MINIMON_BIT 0x00000080 /* Enable Minim features */
429#define TXPRIVEXT_OLDBCCON_BIT 0x00000020 /* Restore Static predictions */
430#define TXPRIVEXT_ALIGNREW_BIT 0x00000010 /* Align & precise checks */
431#endif
432#define TXPRIVEXT_KEEPPRI_BIT 0x00000008 /* Use AMA_Priority if ISTAT=1*/
433#define TXPRIVEXT_TXTOGGLEI_BIT 0x00000001 /* TX.....I priv */
434
435/*
436 * TXTACTCYC register - counts instructions issued for this thread
437 */
438#define TXTACTCYC_REGNUM 30
439#define TXTACTCYC_COUNT_MASK 0x00FFFFFF
440
441/*
442 * TXIDLECYC register - counts idle cycles
443 */
444#define TXIDLECYC_REGNUM 31
445#define TXIDLECYC_COUNT_MASK 0x00FFFFFF
446
447/*****************************************************************************
448 * DSP EXTENSIONS
449 ****************************************************************************/
450/*
451 * The following values relate to fields and controls that only a program
452 * using the DSP extensions of the META instruction set need to know.
453 */
454
455
456#ifndef METAC_1_2
457/*
458 * Allow co-processor hardware to replace the read pipeline data source in
459 * appropriate cases.
460 */
461#define TXMODE_RDCPEN_BIT 0x00800000
462#endif
463
464/*
465 * Address unit addressing modes
466 */
467#define TXMODE_A1ADDR_BITS 0x00007000
468#define TXMODE_A1ADDR_S 12
469#define TXMODE_A0ADDR_BITS 0x00000700
470#define TXMODE_A0ADDR_S 8
471#define TXMODE_AXADDR_MODULO 3
472#define TXMODE_AXADDR_REVB 4
473#define TXMODE_AXADDR_REVW 5
474#define TXMODE_AXADDR_REVD 6
475#define TXMODE_AXADDR_REVL 7
476
477/*
478 * Data unit OverScale select (default 0 -> normal, 1 -> top 16 bits)
479 */
480#define TXMODE_DXOVERSCALE_BIT 0x00000080
481
482/*
483 * Data unit MX mode select (default 0 -> MX16, 1 -> MX8)
484 */
485#define TXMODE_M8_BIT 0x00000040
486
487/*
488 * Data unit accumulator saturation point (default -> 40 bit accumulator)
489 */
490#define TXMODE_DXACCSAT_BIT 0x00000020 /* Set for 32-bit accumulator */
491
492/*
493 * Data unit accumulator saturation enable (default 0 -> no saturation)
494 */
495#define TXMODE_DXSAT_BIT 0x00000010
496
497/*
498 * Data unit master rounding control (default 0 -> normal, 1 -> convergent)
499 */
500#define TXMODE_DXROUNDING_BIT 0x00000008
501
502/*
503 * Data unit product shift for fractional arithmetic (default off)
504 */
505#define TXMODE_DXPRODSHIFT_BIT 0x00000004
506
507/*
508 * Select the arithmetic mode (multiply mostly) for both data units
509 */
510#define TXMODE_DXARITH_BITS 0x00000003
511#define TXMODE_DXARITH_32 3
512#define TXMODE_DXARITH_32H 2
513#define TXMODE_DXARITH_S16 1
514#define TXMODE_DXARITH_16 0
515
516/*
517 * TXMRSIZE register value only relevant when DSP modulo addressing active
518 */
519#define TXMRSIZE_REGNUM 12
520#define TXMRSIZE_MIN 0x0002 /* 0, 1 -> normal addressing logic */
521#define TXMRSIZE_MAX 0xFFFF
522
523/*
524 * TXDRCTRL register can be used to detect the actaul size of the DSP RAM
525 * partitions allocated to this thread.
526 */
527#define TXDRCTRL_REGNUM 14
528#define TXDRCTRL_SINESIZE_BITS 0x0F000000
529#define TXDRCTRL_SINESIZE_S 24
530#define TXDRCTRL_RAMSZPOW_BITS 0x001F0000 /* Limit = (1<<RAMSZPOW)-1 */
531#define TXDRCTRL_RAMSZPOW_S 16
532#define TXDRCTRL_D1RSZAND_BITS 0x0000F000 /* Mask top 4 bits - D1 */
533#define TXDRCTRL_D1RSZAND_S 12
534#define TXDRCTRL_D0RSZAND_BITS 0x000000F0 /* Mask top 4 bits - D0 */
535#define TXDRCTRL_D0RSZAND_S 4
536/* Given extracted RAMSZPOW and DnRSZAND fields this returns the size */
537#define TXDRCTRL_DXSIZE(Pow, AndBits) \
538 ((((~(AndBits)) & 0x0f) + 1) << ((Pow)-4))
539
540/*
541 * TXDRSIZE register provides modulo addressing options for each DSP RAM
542 */
543#define TXDRSIZE_REGNUM 15
544#define TXDRSIZE_R1MOD_BITS 0xFFFF0000
545#define TXDRSIZE_R1MOD_S 16
546#define TXDRSIZE_R0MOD_BITS 0x0000FFFF
547#define TXDRSIZE_R0MOD_S 0
548
549#define TXDRSIZE_RBRAD_SCALE_BITS 0x70000000
550#define TXDRSIZE_RBRAD_SCALE_S 28
551#define TXDRSIZE_RBMODSIZE_BITS 0x0FFF0000
552#define TXDRSIZE_RBMODSIZE_S 16
553#define TXDRSIZE_RARAD_SCALE_BITS 0x00007000
554#define TXDRSIZE_RARAD_SCALE_S 12
555#define TXDRSIZE_RAMODSIZE_BITS 0x00000FFF
556#define TXDRSIZE_RAMODSIZE_S 0
557
558/*****************************************************************************
559 * DEFERRED and BUS ERROR EXTENSION
560 ****************************************************************************/
561
562/*
563 * TXDEFR register - Deferred exception control
564 */
565#define TXDEFR_REGNUM 20
566#define TXDEFR_DEFAULT 0 /* All fields default to zero */
567
568/*
569 * Bus error state is a multi-bit positive/negative event notification from
570 * the bus infrastructure.
571 */
572#define TXDEFR_BUS_ERR_BIT 0x80000000 /* Set if error (LSB STATE) */
573#define TXDEFR_BUS_ERRI_BIT 0x40000000 /* Fetch returned error */
574#define TXDEFR_BUS_STATE_BITS 0x3F000000 /* Bus event/state data */
575#define TXDEFR_BUS_STATE_S 24
576#define TXDEFR_BUS_TRIG_BIT 0x00800000 /* Set when bus error seen */
577
578/*
579 * Bus events are collected by background code in a deferred manner unless
580 * selected to trigger an extended interrupt HALT trigger when they occur.
581 */
582#define TXDEFR_BUS_ICTRL_BIT 0x00000080 /* Enable interrupt trigger */
583
584/*
585 * CHIP Automatic Mips Allocation control registers
586 * ------------------------------------------------
587 */
588
589/* CT Bank AMA Registers */
590#define TXAMAREG0_REGNUM 24
591#ifdef METAC_1_2
592#define TXAMAREG0_CTRL_BITS 0x07000000
593#else /* METAC_1_2 */
594#define TXAMAREG0_RCOFF_BIT 0x08000000
595#define TXAMAREG0_DLINEHLT_BIT 0x04000000
596#define TXAMAREG0_DLINEDIS_BIT 0x02000000
597#define TXAMAREG0_CYCSTRICT_BIT 0x01000000
598#define TXAMAREG0_CTRL_BITS (TXAMAREG0_RCOFF_BIT | \
599 TXAMAREG0_DLINEHLT_BIT | \
600 TXAMAREG0_DLINEDIS_BIT | \
601 TXAMAREG0_CYCSTRICT_BIT)
602#endif /* !METAC_1_2 */
603#define TXAMAREG0_CTRL_S 24
604#define TXAMAREG0_MDM_BIT 0x00400000
605#define TXAMAREG0_MPF_BIT 0x00200000
606#define TXAMAREG0_MPE_BIT 0x00100000
607#define TXAMAREG0_MASK_BITS (TXAMAREG0_MDM_BIT | \
608 TXAMAREG0_MPF_BIT | \
609 TXAMAREG0_MPE_BIT)
610#define TXAMAREG0_MASK_S 20
611#define TXAMAREG0_SDM_BIT 0x00040000
612#define TXAMAREG0_SPF_BIT 0x00020000
613#define TXAMAREG0_SPE_BIT 0x00010000
614#define TXAMAREG0_STATUS_BITS (TXAMAREG0_SDM_BIT | \
615 TXAMAREG0_SPF_BIT | \
616 TXAMAREG0_SPE_BIT)
617#define TXAMAREG0_STATUS_S 16
618#define TXAMAREG0_PRIORITY_BITS 0x0000FF00
619#define TXAMAREG0_PRIORITY_S 8
620#define TXAMAREG0_BVALUE_BITS 0x000000FF
621#define TXAMAREG0_BVALUE_S 0
622
623#define TXAMAREG1_REGNUM 25
624#define TXAMAREG1_DELAYC_BITS 0x07FFFFFF
625#define TXAMAREG1_DELAYC_S 0
626
627#define TXAMAREG2_REGNUM 26
628#ifdef METAC_1_2
629#define TXAMAREG2_DLINEC_BITS 0x00FFFFFF
630#define TXAMAREG2_DLINEC_S 0
631#else /* METAC_1_2 */
632#define TXAMAREG2_IRQPRIORITY_BIT 0xFF000000
633#define TXAMAREG2_IRQPRIORITY_S 24
634#define TXAMAREG2_DLINEC_BITS 0x00FFFFF0
635#define TXAMAREG2_DLINEC_S 4
636#endif /* !METAC_1_2 */
637
638#define TXAMAREG3_REGNUM 27
639#define TXAMAREG2_AMABLOCK_BIT 0x00080000
640#define TXAMAREG2_AMAC_BITS 0x0000FFFF
641#define TXAMAREG2_AMAC_S 0
642
643/*****************************************************************************
644 * FPU EXTENSIONS
645 ****************************************************************************/
646/*
647 * The following registers only exist in FPU enabled cores.
648 */
649
650/*
651 * TXMODE register - FPU rounding mode control/status fields
652 */
653#define TXMODE_FPURMODE_BITS 0x00030000
654#define TXMODE_FPURMODE_S 16
655#define TXMODE_FPURMODEWRITE_BIT 0x00040000 /* Set to change FPURMODE */
656
657/*
658 * TXDEFR register - FPU exception handling/state is a significant source
659 * of deferrable errors. Run-time S/W can move handling to interrupt level
660 * using DEFR instruction to collect state.
661 */
662#define TXDEFR_FPE_FE_BITS 0x003F0000 /* Set by FPU_FE events */
663#define TXDEFR_FPE_FE_S 16
664
665#define TXDEFR_FPE_INEXACT_FE_BIT 0x010000
666#define TXDEFR_FPE_UNDERFLOW_FE_BIT 0x020000
667#define TXDEFR_FPE_OVERFLOW_FE_BIT 0x040000
668#define TXDEFR_FPE_DIVBYZERO_FE_BIT 0x080000
669#define TXDEFR_FPE_INVALID_FE_BIT 0x100000
670#define TXDEFR_FPE_DENORMAL_FE_BIT 0x200000
671
672#define TXDEFR_FPE_ICTRL_BITS 0x000003F /* Route to interrupts */
673#define TXDEFR_FPE_ICTRL_S 0
674
675#define TXDEFR_FPE_INEXACT_ICTRL_BIT 0x01
676#define TXDEFR_FPE_UNDERFLOW_ICTRL_BIT 0x02
677#define TXDEFR_FPE_OVERFLOW_ICTRL_BIT 0x04
678#define TXDEFR_FPE_DIVBYZERO_ICTRL_BIT 0x08
679#define TXDEFR_FPE_INVALID_ICTRL_BIT 0x10
680#define TXDEFR_FPE_DENORMAL_ICTRL_BIT 0x20
681
682/*
683 * DETAILED FPU RELATED VALUES
684 * ---------------------------
685 */
686
687/*
688 * Rounding mode field in TXMODE can hold a number of logical values
689 */
690#define METAG_FPURMODE_TONEAREST 0x0 /* Default */
691#define METAG_FPURMODE_TOWARDZERO 0x1
692#define METAG_FPURMODE_UPWARD 0x2
693#define METAG_FPURMODE_DOWNWARD 0x3
694
695/*
696 * In order to set the TXMODE register field that controls the rounding mode
697 * an extra bit must be set in the value written versus that read in order
698 * to gate writes to the rounding mode field. This allows other non-FPU code
699 * to modify TXMODE without knowledge of the FPU units presence and not
700 * influence the FPU rounding mode. This macro adds the required bit so new
701 * rounding modes are accepted.
702 */
703#define TXMODE_FPURMODE_SET(FPURMode) \
704 (TXMODE_FPURMODEWRITE_BIT + ((FPURMode)<<TXMODE_FPURMODE_S))
705
706/*
707 * To successfully restore TXMODE to zero at the end of the function the
708 * following value (rather than zero) must be used.
709 */
710#define TXMODE_FPURMODE_RESET (TXMODE_FPURMODEWRITE_BIT)
711
712/*
713 * In TXSTATUS a special bit exists to indicate if FPU H/W has been accessed
714 * since it was last reset.
715 */
716#define TXSTATUS_FPACTIVE_BIT 0x01000000
717
718/*
719 * Exception state (see TXDEFR_FPU_FE_*) and enabling (for interrupt
720 * level processing (see TXDEFR_FPU_ICTRL_*) are controlled by similar
721 * bit mask locations within each field.
722 */
723#define METAG_FPU_FE_INEXACT 0x01
724#define METAG_FPU_FE_UNDERFLOW 0x02
725#define METAG_FPU_FE_OVERFLOW 0x04
726#define METAG_FPU_FE_DIVBYZERO 0x08
727#define METAG_FPU_FE_INVALID 0x10
728#define METAG_FPU_FE_DENORMAL 0x20
729#define METAG_FPU_FE_ALL_EXCEPT (METAG_FPU_FE_INEXACT | \
730 METAG_FPU_FE_UNDERFLOW | \
731 METAG_FPU_FE_OVERFLOW | \
732 METAG_FPU_FE_DIVBYZERO | \
733 METAG_FPU_FE_INVALID | \
734 METAG_FPU_FE_DENORMAL)
735
736/*****************************************************************************
737 * THREAD CONTROL, ERROR, OR INTERRUPT STATE EXTENSIONS
738 ****************************************************************************/
739/*
740 * The following values are only relevant to code that externally controls
741 * threads, handles errors/interrupts, and/or set-up interrupt/error handlers
742 * for subsequent use.
743 */
744
745/*
746 * TXENABLE register fields - only ENABLE_BIT is potentially read/write
747 */
748#define TXENABLE_MAJOR_REV_BITS 0xFF000000
749#define TXENABLE_MAJOR_REV_S 24
750#define TXENABLE_MINOR_REV_BITS 0x00FF0000
751#define TXENABLE_MINOR_REV_S 16
752#define TXENABLE_CLASS_BITS 0x0000F000
753#define TXENABLE_CLASS_S 12
754#define TXENABLE_CLASS_DSP 0x0 /* -> DSP Thread */
755#define TXENABLE_CLASS_LDSP 0x8 /* -> DSP LITE Thread */
756#define TXENABLE_CLASS_GP 0xC /* -> General Purpose Thread */
757#define TXENABLE_CLASSALT_LFPU 0x2 /* Set to indicate LITE FPU */
758#define TXENABLE_CLASSALT_FPUR8 0x1 /* Set to indicate 8xFPU regs */
759#define TXENABLE_MTXARCH_BIT 0x00000800
760#define TXENABLE_STEP_REV_BITS 0x000000F0
761#define TXENABLE_STEP_REV_S 4
762#define TXENABLE_STOPPED_BIT 0x00000004 /* TXOFF due to ENABLE->0 */
763#define TXENABLE_OFF_BIT 0x00000002 /* Thread is in off state */
764#define TXENABLE_ENABLE_BIT 0x00000001 /* Set if running */
765
766/*
767 * TXSTATUS register - used by external/internal interrupt/error handler
768 */
769#define TXSTATUS_CB1MARKER_BIT 0x00800000 /* -> int level mem state */
770#define TXSTATUS_CBMARKER_BIT 0x00400000 /* -> mem i/f state dumped */
771#define TXSTATUS_MEM_FAULT_BITS 0x00300000
772#define TXSTATUS_MEM_FAULT_S 20
773#define TXSTATUS_MEMFAULT_NONE 0x0 /* -> No memory fault */
774#define TXSTATUS_MEMFAULT_GEN 0x1 /* -> General fault */
775#define TXSTATUS_MEMFAULT_PF 0x2 /* -> Page fault */
776#define TXSTATUS_MEMFAULT_RO 0x3 /* -> Read only fault */
777#define TXSTATUS_MAJOR_HALT_BITS 0x000C0000
778#define TXSTATUS_MAJOR_HALT_S 18
779#define TXSTATUS_MAJHALT_TRAP 0x0 /* -> SWITCH inst used */
780#define TXSTATUS_MAJHALT_INST 0x1 /* -> Unknown inst or fetch */
781#define TXSTATUS_MAJHALT_PRIV 0x2 /* -> Internal privilege */
782#define TXSTATUS_MAJHALT_MEM 0x3 /* -> Memory i/f fault */
783#define TXSTATUS_L_STEP_BITS 0x00000800 /* -> Progress of L oper */
784#define TXSTATUS_LSM_STEP_BITS 0x00000700 /* -> Progress of L/S mult */
785#define TXSTATUS_LSM_STEP_S 8
786#define TXSTATUS_FLAG_BITS 0x0000001F /* -> All the flags */
787#define TXSTATUS_SCC_BIT 0x00000010 /* -> Split-16 flags ... */
788#define TXSTATUS_SCF_LZ_BIT 0x00000008 /* -> Split-16 Low Z flag */
789#define TXSTATUS_SCF_HZ_BIT 0x00000004 /* -> Split-16 High Z flag */
790#define TXSTATUS_SCF_HC_BIT 0x00000002 /* -> Split-16 High C flag */
791#define TXSTATUS_SCF_LC_BIT 0x00000001 /* -> Split-16 Low C flag */
792#define TXSTATUS_CF_Z_BIT 0x00000008 /* -> Condition Z flag */
793#define TXSTATUS_CF_N_BIT 0x00000004 /* -> Condition N flag */
794#define TXSTATUS_CF_O_BIT 0x00000002 /* -> Condition O flag */
795#define TXSTATUS_CF_C_BIT 0x00000001 /* -> Condition C flag */
796
797/*
798 * TXCATCH0-3 register contents may store information on a memory operation
799 * that has failed if the bit TXSTATUS_CBMARKER_BIT is set.
800 */
801#define TXCATCH0_REGNUM 16
802#define TXCATCH1_REGNUM 17
803#define TXCATCH1_ADDR_BITS 0xFFFFFFFF /* TXCATCH1 is Addr 0-31 */
804#define TXCATCH1_ADDR_S 0
805#define TXCATCH2_REGNUM 18
806#define TXCATCH2_DATA0_BITS 0xFFFFFFFF /* TXCATCH2 is Data 0-31 */
807#define TXCATCH2_DATA0_S 0
808#define TXCATCH3_REGNUM 19
809#define TXCATCH3_DATA1_BITS 0xFFFFFFFF /* TXCATCH3 is Data 32-63 */
810#define TXCATCH3_DATA1_S 0
811
812/*
813 * Detailed catch state information
814 * --------------------------------
815 */
816
817/* Contents of TXCATCH0 register */
818#define TXCATCH0_LDRXX_BITS 0xF8000000 /* Load destination reg 0-31 */
819#define TXCATCH0_LDRXX_S 27
820#define TXCATCH0_LDDST_BITS 0x07FF0000 /* Load destination bits */
821#define TXCATCH0_LDDST_S 16
822#define TXCATCH0_LDDST_D1DSP 0x400 /* One bit set if it's a LOAD */
823#define TXCATCH0_LDDST_D0DSP 0x200
824#define TXCATCH0_LDDST_TMPLT 0x100
825#define TXCATCH0_LDDST_TR 0x080
826#ifdef METAC_2_1
827#define TXCATCH0_LDDST_FPU 0x040
828#endif
829#define TXCATCH0_LDDST_PC 0x020
830#define TXCATCH0_LDDST_A1 0x010
831#define TXCATCH0_LDDST_A0 0x008
832#define TXCATCH0_LDDST_D1 0x004
833#define TXCATCH0_LDDST_D0 0x002
834#define TXCATCH0_LDDST_CT 0x001
835#ifdef METAC_2_1
836#define TXCATCH0_WATCHSTOP_BIT 0x00004000 /* Set if Data Watch set fault */
837#endif
838#define TXCATCH0_WATCHS_BIT 0x00004000 /* Set if Data Watch set fault */
839#define TXCATCH0_WATCH1_BIT 0x00002000 /* Set if Data Watch 1 matches */
840#define TXCATCH0_WATCH0_BIT 0x00001000 /* Set if Data Watch 0 matches */
841#define TXCATCH0_FAULT_BITS 0x00000C00 /* See TXSTATUS_MEMFAULT_* */
842#define TXCATCH0_FAULT_S 10
843#define TXCATCH0_PRIV_BIT 0x00000200 /* Privilege of transaction */
844#define TXCATCH0_READ_BIT 0x00000100 /* Set for Read or Load cases */
845
846#ifdef METAC_2_1
847/* LNKGET Marker bit in TXCATCH0 */
848#define TXCATCH0_LNKGET_MARKER_BIT 0x00000008
849#define TXCATCH0_PREPROC_BIT 0x00000004
850#endif
851
852/* Loads are indicated by one of the LDDST bits being set */
853#define TXCATCH0_LDM16_BIT 0x00000004 /* Load M16 flag */
854#define TXCATCH0_LDL2L1_BITS 0x00000003 /* Load data size L2,L1 */
855#define TXCATCH0_LDL2L1_S 0
856
857/* Reads are indicated by the READ bit being set without LDDST bits */
858#define TXCATCH0_RAXX_BITS 0x0000001F /* RAXX issue port for read */
859#define TXCATCH0_RAXX_S 0
860
861/* Write operations are all that remain if READ bit is not set */
862#define TXCATCH0_WMASK_BITS 0x000000FF /* Write byte lane mask */
863#define TXCATCH0_WMASK_S 0
864
865#ifdef METAC_2_1
866
867/* When a FPU exception is signalled then FPUSPEC == FPUSPEC_TAG */
868#define TXCATCH0_FPURDREG_BITS 0xF8000000
869#define TXCATCH0_FPURDREG_S 27
870#define TXCATCH0_FPUR1REG_BITS 0x07C00000
871#define TXCATCH0_FPUR1REG_S 22
872#define TXCATCH0_FPUSPEC_BITS 0x000F0000
873#define TXCATCH0_FPUSPEC_S 16
874#define TXCATCH0_FPUSPEC_TAG 0xF
875#define TXCATCH0_FPUINSTA_BIT 0x00001000
876#define TXCATCH0_FPUINSTQ_BIT 0x00000800
877#define TXCATCH0_FPUINSTZ_BIT 0x00000400
878#define TXCATCH0_FPUINSTN_BIT 0x00000200
879#define TXCATCH0_FPUINSTO3O_BIT 0x00000100
880#define TXCATCH0_FPUWIDTH_BITS 0x000000C0
881#define TXCATCH0_FPUWIDTH_S 6
882#define TXCATCH0_FPUWIDTH_FLOAT 0
883#define TXCATCH0_FPUWIDTH_DOUBLE 1
884#define TXCATCH0_FPUWIDTH_PAIRED 2
885#define TXCATCH0_FPUOPENC_BITS 0x0000003F
886#define TXCATCH0_FPUOPENC_S 0
887#define TXCATCH0_FPUOPENC_ADD 0 /* rop1=Rs1, rop3=Rs2 */
888#define TXCATCH0_FPUOPENC_SUB 1 /* rop1=Rs1, rop3=Rs2 */
889#define TXCATCH0_FPUOPENC_MUL 2 /* rop1=Rs1, rop2=Rs2 */
890#define TXCATCH0_FPUOPENC_ATOI 3 /* rop3=Rs */
891#define TXCATCH0_FPUOPENC_ATOX 4 /* rop3=Rs, uses #Imm */
892#define TXCATCH0_FPUOPENC_ITOA 5 /* rop3=Rs */
893#define TXCATCH0_FPUOPENC_XTOA 6 /* rop3=Rs, uses #Imm */
894#define TXCATCH0_FPUOPENC_ATOH 7 /* rop2=Rs */
895#define TXCATCH0_FPUOPENC_HTOA 8 /* rop2=Rs */
896#define TXCATCH0_FPUOPENC_DTOF 9 /* rop3=Rs */
897#define TXCATCH0_FPUOPENC_FTOD 10 /* rop3=Rs */
898#define TXCATCH0_FPUOPENC_DTOL 11 /* rop3=Rs */
899#define TXCATCH0_FPUOPENC_LTOD 12 /* rop3=Rs */
900#define TXCATCH0_FPUOPENC_DTOXL 13 /* rop3=Rs, uses #imm */
901#define TXCATCH0_FPUOPENC_XLTOD 14 /* rop3=Rs, uses #imm */
902#define TXCATCH0_FPUOPENC_CMP 15 /* rop1=Rs1, rop2=Rs2 */
903#define TXCATCH0_FPUOPENC_MIN 16 /* rop1=Rs1, rop2=Rs2 */
904#define TXCATCH0_FPUOPENC_MAX 17 /* rop1=Rs1, rop2=Rs2 */
905#define TXCATCH0_FPUOPENC_ADDRE 18 /* rop1=Rs1, rop3=Rs2 */
906#define TXCATCH0_FPUOPENC_SUBRE 19 /* rop1=Rs1, rop3=Rs2 */
907#define TXCATCH0_FPUOPENC_MULRE 20 /* rop1=Rs1, rop2=Rs2 */
908#define TXCATCH0_FPUOPENC_MXA 21 /* rop1=Rs1, rop2=Rs2, rop3=Rs3*/
909#define TXCATCH0_FPUOPENC_MXAS 22 /* rop1=Rs1, rop2=Rs2, rop3=Rs3*/
910#define TXCATCH0_FPUOPENC_MAR 23 /* rop1=Rs1, rop2=Rs2 */
911#define TXCATCH0_FPUOPENC_MARS 24 /* rop1=Rs1, rop2=Rs2 */
912#define TXCATCH0_FPUOPENC_MUZ 25 /* rop1=Rs1, rop2=Rs2, rop3=Rs3*/
913#define TXCATCH0_FPUOPENC_MUZS 26 /* rop1=Rs1, rop2=Rs2, rop3=Rs3*/
914#define TXCATCH0_FPUOPENC_RCP 27 /* rop2=Rs */
915#define TXCATCH0_FPUOPENC_RSQ 28 /* rop2=Rs */
916
917/* For floating point exceptions TXCATCH1 is used to carry extra data */
918#define TXCATCH1_FPUR2REG_BITS 0xF8000000
919#define TXCATCH1_FPUR2REG_S 27
920#define TXCATCH1_FPUR3REG_BITS 0x07C00000 /* Undefined if O3O set */
921#define TXCATCH1_FPUR3REG_S 22
922#define TXCATCH1_FPUIMM16_BITS 0x0000FFFF
923#define TXCATCH1_FPUIMM16_S 0
924
925#endif /* METAC_2_1 */
926
927/*
928 * TXDIVTIME register used to hold the partial base address of memory i/f
929 * state dump area. Now deprecated.
930 */
931#define TXDIVTIME_CBBASE_MASK 0x03FFFE00
932#define TXDIVTIME_CBBASE_LINBASE 0x80000000
933#define TXDIVTIME_CBBASE_LINBOFF 0x00000000 /* BGnd state */
934#define TXDIVTIME_CBBASE_LINIOFF 0x00000100 /* Int state */
935
936/*
937 * TXDIVTIME register used to indicate if the read pipeline was dirty when a
938 * thread was interrupted, halted, or generated an exception. It is invalid
939 * to attempt to issue a further pipeline read address while the read
940 * pipeline is in the dirty state.
941 */
942#define TXDIVTIME_RPDIRTY_BIT 0x80000000
943
944/*
945 * Further bits in the TXDIVTIME register allow interrupt handling code to
946 * short-cut the discovery the most significant bit last read from TXSTATI.
947 *
948 * This is the bit number of the trigger line that a low level interrupt
949 * handler should acknowledge and then perhaps the index of a corresponding
950 * handler function.
951 */
952#define TXDIVTIME_IRQENC_BITS 0x0F000000
953#define TXDIVTIME_IRQENC_S 24
954
955/*
956 * If TXDIVTIME_RPVALID_BIT is set the read pipeline contained significant
957 * information when the thread was interrupted|halted|exceptioned. Each slot
958 * containing data is indicated by a one bit in the corresponding
959 * TXDIVTIME_RPMASK_BITS bit (least significance bit relates to first
960 * location in read pipeline - most likely to have the 1 state). Empty slots
961 * contain zeroes with no interlock applied on reads if RPDIRTY is currently
962 * set with RPMASK itself being read-only state.
963 */
964#define TXDIVTIME_RPMASK_BITS 0x003F0000 /* -> Full (1) Empty (0) */
965#define TXDIVTIME_RPMASK_S 16
966
967/*
968 * TXPRIVEXT register can be used to single step thread execution and
969 * enforce synchronous memory i/f address checking for debugging purposes.
970 */
971#define TXPRIVEXT_TXSTEP_BIT 0x00000004
972#define TXPRIVEXT_MEMCHECK_BIT 0x00000002
973
974/*
975 * TXINTERNx registers holds internal state information for H/W debugging only
976 */
977#define TXINTERN0_REGNUM 23
978#define TXINTERN0_LOCK2_BITS 0xF0000000
979#define TXINTERN0_LOCK2_S 28
980#define TXINTERN0_LOCK1_BITS 0x0F000000
981#define TXINTERN0_LOCK1_S 24
982#define TXINTERN0_TIFDF_BITS 0x0000F000
983#define TXINTERN0_TIFDF_S 12
984#define TXINTERN0_TIFIB_BITS 0x00000F00
985#define TXINTERN0_TIFIB_S 8
986#define TXINTERN0_TIFAF_BITS 0x000000F0
987#define TXINTERN0_TIFAF_S 4
988#define TXINTERN0_MSTATE_BITS 0x0000000F
989#define TXINTERN0_MSTATE_S 0
990
991/*
992 * TXSTAT, TXMASK, TXPOLL, TXSTATI, TXMASKI, TXPOLLI registers from trigger
993 * bank all have similar contents (upper kick count bits not in MASK regs)
994 */
995#define TXSTAT_REGNUM 0
996#define TXSTAT_TIMER_BIT 0x00000001
997#define TXSTAT_TIMER_S 0
998#define TXSTAT_KICK_BIT 0x00000002
999#define TXSTAT_KICK_S 1
1000#define TXSTAT_DEFER_BIT 0x00000008
1001#define TXSTAT_DEFER_S 3
1002#define TXSTAT_EXTTRIG_BITS 0x0000FFF0
1003#define TXSTAT_EXTTRIG_S 4
1004#define TXSTAT_FPE_BITS 0x003F0000
1005#define TXSTAT_FPE_S 16
1006#define TXSTAT_FPE_DENORMAL_BIT 0x00200000
1007#define TXSTAT_FPE_DENORMAL_S 21
1008#define TXSTAT_FPE_INVALID_BIT 0x00100000
1009#define TXSTAT_FPE_INVALID_S 20
1010#define TXSTAT_FPE_DIVBYZERO_BIT 0x00080000
1011#define TXSTAT_FPE_DIVBYZERO_S 19
1012#define TXSTAT_FPE_OVERFLOW_BIT 0x00040000
1013#define TXSTAT_FPE_OVERFLOW_S 18
1014#define TXSTAT_FPE_UNDERFLOW_BIT 0x00020000
1015#define TXSTAT_FPE_UNDERFLOW_S 17
1016#define TXSTAT_FPE_INEXACT_BIT 0x00010000
1017#define TXSTAT_FPE_INEXACT_S 16
1018#define TXSTAT_BUSERR_BIT 0x00800000 /* Set if bus error/ack state */
1019#define TXSTAT_BUSERR_S 23
1020#define TXSTAT_BUSSTATE_BITS 0xFF000000 /* Read only */
1021#define TXSTAT_BUSSTATE_S 24
1022#define TXSTAT_KICKCNT_BITS 0xFFFF0000
1023#define TXSTAT_KICKCNT_S 16
1024#define TXMASK_REGNUM 1
1025#define TXSTATI_REGNUM 2
1026#define TXSTATI_BGNDHALT_BIT 0x00000004
1027#define TXMASKI_REGNUM 3
1028#define TXPOLL_REGNUM 4
1029#define TXPOLLI_REGNUM 6
1030
1031/*
1032 * TXDRCTRL register can be used to partition the DSP RAM space available to
1033 * this thread at startup. This is achieved by offsetting the region allocated
1034 * to each thread.
1035 */
1036#define TXDRCTRL_D1PARTOR_BITS 0x00000F00 /* OR's into top 4 bits */
1037#define TXDRCTRL_D1PARTOR_S 8
1038#define TXDRCTRL_D0PARTOR_BITS 0x0000000F /* OR's into top 4 bits */
1039#define TXDRCTRL_D0PARTOR_S 0
1040/* Given extracted Pow and Or fields this is threads base within DSP RAM */
1041#define TXDRCTRL_DXBASE(Pow, Or) ((Or)<<((Pow)-4))
1042
1043/*****************************************************************************
1044 * RUN TIME TRACE CONTROL REGISTERS
1045 ****************************************************************************/
1046/*
1047 * The following values are only relevant to code that implements run-time
1048 * trace features within the META Core
1049 */
1050#define TTEXEC TT.0
1051#define TTCTRL TT.1
1052#define TTMARK TT.2
1053#define TTREC TT.3
1054#define GTEXEC TT.4
1055
1056#define TTEXEC_REGNUM 0
1057#define TTEXEC_EXTTRIGAND_BITS 0x7F000000
1058#define TTEXEC_EXTTRIGAND_S 24
1059#define TTEXEC_EXTTRIGEN_BIT 0x00008000
1060#define TTEXEC_EXTTRIGMATCH_BITS 0x00007F00
1061#define TTEXEC_EXTTRIGMATCH_S 8
1062#define TTEXEC_TCMODE_BITS 0x00000003
1063#define TTEXEC_TCMODE_S 0
1064
1065#define TTCTRL_REGNUM 1
1066#define TTCTRL_TRACETT_BITS 0x00008000
1067#define TTCTRL_TRACETT_S 15
1068#define TTCTRL_TRACEALL_BITS 0x00002000
1069#define TTCTRL_TRACEALL_S 13
1070#ifdef METAC_2_1
1071#define TTCTRL_TRACEALLTAG_BITS 0x00000400
1072#define TTCTRL_TRACEALLTAG_S 10
1073#endif /* METAC_2_1 */
1074#define TTCTRL_TRACETAG_BITS 0x00000200
1075#define TTCTRL_TRACETAG_S 9
1076#define TTCTRL_TRACETTPC_BITS 0x00000080
1077#define TTCTRL_TRACETTPC_S 7
1078#define TTCTRL_TRACEMPC_BITS 0x00000020
1079#define TTCTRL_TRACEMPC_S 5
1080#define TTCTRL_TRACEEN_BITS 0x00000008
1081#define TTCTRL_TRACEEN_S 3
1082#define TTCTRL_TRACEEN1_BITS 0x00000004
1083#define TTCTRL_TRACEEN1_S 2
1084#define TTCTRL_TRACEPC_BITS 0x00000002
1085#define TTCTRL_TRACEPC_S 1
1086
1087#ifdef METAC_2_1
1088#define TTMARK_REGNUM 2
1089#define TTMARK_BITS 0xFFFFFFFF
1090#define TTMARK_S 0x0
1091
1092#define TTREC_REGNUM 3
1093#define TTREC_BITS 0xFFFFFFFFFFFFFFFF
1094#define TTREC_S 0x0
1095#endif /* METAC_2_1 */
1096
1097#define GTEXEC_REGNUM 4
1098#define GTEXEC_DCRUN_BITS 0x80000000
1099#define GTEXEC_DCRUN_S 31
1100#define GTEXEC_ICMODE_BITS 0x0C000000
1101#define GTEXEC_ICMODE_S 26
1102#define GTEXEC_TCMODE_BITS 0x03000000
1103#define GTEXEC_TCMODE_S 24
1104#define GTEXEC_PERF1CMODE_BITS 0x00040000
1105#define GTEXEC_PERF1CMODE_S 18
1106#define GTEXEC_PERF0CMODE_BITS 0x00010000
1107#define GTEXEC_PERF0CMODE_S 16
1108#define GTEXEC_REFMSEL_BITS 0x0000F000
1109#define GTEXEC_REFMSEL_S 12
1110#define GTEXEC_METRICTH_BITS 0x000003FF
1111#define GTEXEC_METRICTH_S 0
1112
1113#ifdef METAC_2_1
1114/*
1115 * Clock Control registers
1116 * -----------------------
1117 */
1118#define TXCLKCTRL_REGNUM 22
1119
1120/*
1121 * Default setting is with clocks always on (DEFON), turning all clocks off
1122 * can only be done from external devices (OFF), enabling automatic clock
1123 * gating will allow clocks to stop as units fall idle.
1124 */
1125#define TXCLKCTRL_ALL_OFF 0x02222222
1126#define TXCLKCTRL_ALL_DEFON 0x01111111
1127#define TXCLKCTRL_ALL_AUTO 0x02222222
1128
1129/*
1130 * Individual fields control caches, floating point and main data/addr units
1131 */
1132#define TXCLKCTRL_CLOCKIC_BITS 0x03000000
1133#define TXCLKCTRL_CLOCKIC_S 24
1134#define TXCLKCTRL_CLOCKDC_BITS 0x00300000
1135#define TXCLKCTRL_CLOCKDC_S 20
1136#define TXCLKCTRL_CLOCKFP_BITS 0x00030000
1137#define TXCLKCTRL_CLOCKFP_S 16
1138#define TXCLKCTRL_CLOCKD1_BITS 0x00003000
1139#define TXCLKCTRL_CLOCKD1_S 12
1140#define TXCLKCTRL_CLOCKD0_BITS 0x00000300
1141#define TXCLKCTRL_CLOCKD0_S 8
1142#define TXCLKCTRL_CLOCKA1_BITS 0x00000030
1143#define TXCLKCTRL_CLOCKA1_S 4
1144#define TXCLKCTRL_CLOCKA0_BITS 0x00000003
1145#define TXCLKCTRL_CLOCKA0_S 0
1146
1147/*
1148 * Individual settings for each field are common
1149 */
1150#define TXCLKCTRL_CLOCKxx_OFF 0
1151#define TXCLKCTRL_CLOCKxx_DEFON 1
1152#define TXCLKCTRL_CLOCKxx_AUTO 2
1153
1154#endif /* METAC_2_1 */
1155
1156#ifdef METAC_2_1
1157/*
1158 * Fast interrupt new bits
1159 * ------------------------------------
1160 */
1161#define TXSTATUS_IPTOGGLE_BIT 0x80000000 /* Prev PToggle of TXPRIVEXT */
1162#define TXSTATUS_ISTATE_BIT 0x40000000 /* IState bit */
1163#define TXSTATUS_IWAIT_BIT 0x20000000 /* wait indefinitely in decision step*/
1164#define TXSTATUS_IEXCEPT_BIT 0x10000000 /* Indicate an exception occured */
1165#define TXSTATUS_IRPCOUNT_BITS 0x0E000000 /* Number of 'dirty' date entries*/
1166#define TXSTATUS_IRPCOUNT_S 25
1167#define TXSTATUS_IRQSTAT_BITS 0x0000F000 /* IRQEnc bits, trigger or interrupts */
1168#define TXSTATUS_IRQSTAT_S 12
1169#define TXSTATUS_LNKSETOK_BIT 0x00000020 /* LNKSetOK bit, successful LNKSET */
1170
1171/* New fields in TXDE for fast interrupt system */
1172#define TXDIVTIME_IACTIVE_BIT 0x00008000 /* Enable new interrupt system */
1173#define TXDIVTIME_INONEST_BIT 0x00004000 /* Gate nested interrupt */
1174#define TXDIVTIME_IREGIDXGATE_BIT 0x00002000 /* gate of the IRegIdex field */
1175#define TXDIVTIME_IREGIDX_BITS 0x00001E00 /* Index of A0.0/1 replaces */
1176#define TXDIVTIME_IREGIDX_S 9
1177#define TXDIVTIME_NOST_BIT 0x00000100 /* disable superthreading bit */
1178#endif
1179
1180#endif /* _ASM_METAG_REGS_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-14 13:47:42 -0500