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authorKumar Gala <galak@kernel.crashing.org>2011-10-26 02:01:54 -0400
committerKumar Gala <galak@kernel.crashing.org>2011-11-24 03:01:38 -0500
commitab827d97bd5c7aa3ccf637161d22a6329fb24a02 (patch)
treee6a3c13c666d96c35a7869d34e46e451c5dc76f8 /arch
parentffeb33d20c6217bb8f0ab46d3f1396021c00c24f (diff)
powerpc/85xx: Rework P1022DS device tree
Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Changed GPIO compatiable from 'fsl,mpc8572-gpio' to 'fsl,pq3-gpio' as the 'mpc8572' compatiable is to deal with a 'mpc8572' specific to an erratum * Updated spi node to new espi binding specification * Renamed SDHC node from 'sdhci' to 'sdhc' * Added usb node for 2nd usb controller * Dropping "fsl,p1022-IP..." from compatibles for standard blocks * Fixed bug in local bus range node for CS2, was maping to 0x0 0x0xffa00000 instead of 0xf 0xffa00000 * Fixed localbus reg property should have been 0xf 0xffe05000 Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Tested-by: Timur Tabi <timur@freescale.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/boot/dts/fsl/p1022si-post.dtsi235
-rw-r--r--arch/powerpc/boot/dts/fsl/p1022si-pre.dtsi68
-rw-r--r--arch/powerpc/boot/dts/p1022ds.dts435
3 files changed, 320 insertions, 418 deletions
diff --git a/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi
new file mode 100644
index 000000000000..16239b199d0a
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi
@@ -0,0 +1,235 @@
1/*
2 * P1022/P1013 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&lbc {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,p1022-elbc", "fsl,elbc", "simple-bus";
39 interrupts = <19 2 0 0>;
40};
41
42/* controller at 0x9000 */
43&pci0 {
44 compatible = "fsl,p1022-pcie";
45 device_type = "pci";
46 #size-cells = <2>;
47 #address-cells = <3>;
48 bus-range = <0 255>;
49 clock-frequency = <33333333>;
50 interrupts = <16 2 0 0>;
51
52 pcie@0 {
53 reg = <0 0 0 0 0>;
54 #interrupt-cells = <1>;
55 #size-cells = <2>;
56 #address-cells = <3>;
57 device_type = "pci";
58 interrupts = <16 2 0 0>;
59 interrupt-map-mask = <0xf800 0 0 7>;
60 interrupt-map = <
61 /* IDSEL 0x0 */
62 0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
63 0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
64 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
65 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
66 >;
67 };
68};
69
70/* controller at 0xa000 */
71&pci1 {
72 compatible = "fsl,p1022-pcie";
73 device_type = "pci";
74 #size-cells = <2>;
75 #address-cells = <3>;
76 bus-range = <0 255>;
77 clock-frequency = <33333333>;
78 interrupts = <16 2 0 0>;
79
80 pcie@0 {
81 reg = <0 0 0 0 0>;
82 #interrupt-cells = <1>;
83 #size-cells = <2>;
84 #address-cells = <3>;
85 device_type = "pci";
86 interrupts = <16 2 0 0>;
87 interrupt-map-mask = <0xf800 0 0 7>;
88
89 interrupt-map = <
90 /* IDSEL 0x0 */
91 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
92 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
93 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
94 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
95 >;
96 };
97};
98
99/* controller at 0xb000 */
100&pci2 {
101 compatible = "fsl,p1022-pcie";
102 device_type = "pci";
103 #size-cells = <2>;
104 #address-cells = <3>;
105 bus-range = <0 255>;
106 clock-frequency = <33333333>;
107 interrupts = <16 2 0 0>;
108
109 pcie@0 {
110 reg = <0 0 0 0 0>;
111 #interrupt-cells = <1>;
112 #size-cells = <2>;
113 #address-cells = <3>;
114 device_type = "pci";
115 interrupts = <16 2 0 0>;
116 interrupt-map-mask = <0xf800 0 0 7>;
117
118 interrupt-map = <
119 /* IDSEL 0x0 */
120 0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0
121 0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0
122 0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0
123 0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0
124 >;
125 };
126};
127
128&soc {
129 #address-cells = <1>;
130 #size-cells = <1>;
131 device_type = "soc";
132 compatible = "fsl,p1022-immr", "simple-bus";
133 bus-frequency = <0>; // Filled out by uboot.
134
135 ecm-law@0 {
136 compatible = "fsl,ecm-law";
137 reg = <0x0 0x1000>;
138 fsl,num-laws = <12>;
139 };
140
141 ecm@1000 {
142 compatible = "fsl,p1022-ecm", "fsl,ecm";
143 reg = <0x1000 0x1000>;
144 interrupts = <16 2 0 0>;
145 };
146
147 memory-controller@2000 {
148 compatible = "fsl,p1022-memory-controller";
149 reg = <0x2000 0x1000>;
150 interrupts = <16 2 0 0>;
151 };
152
153/include/ "pq3-i2c-0.dtsi"
154/include/ "pq3-i2c-1.dtsi"
155/include/ "pq3-duart-0.dtsi"
156/include/ "pq3-espi-0.dtsi"
157 spi@7000 {
158 fsl,espi-num-chipselects = <4>;
159 };
160
161/include/ "pq3-dma-1.dtsi"
162 dma@c300 {
163 dma00: dma-channel@0 {
164 compatible = "fsl,ssi-dma-channel";
165 };
166 dma01: dma-channel@80 {
167 compatible = "fsl,ssi-dma-channel";
168 };
169 };
170
171/include/ "pq3-gpio-0.dtsi"
172
173 display@10000 {
174 compatible = "fsl,diu", "fsl,p1022-diu";
175 reg = <0x10000 1000>;
176 interrupts = <64 2 0 0>;
177 };
178
179 ssi@15000 {
180 compatible = "fsl,mpc8610-ssi";
181 cell-index = <0>;
182 reg = <0x15000 0x100>;
183 interrupts = <75 2 0 0>;
184 fsl,playback-dma = <&dma00>;
185 fsl,capture-dma = <&dma01>;
186 fsl,fifo-depth = <15>;
187 };
188
189/include/ "pq3-sata2-0.dtsi"
190/include/ "pq3-sata2-1.dtsi"
191
192 L2: l2-cache-controller@20000 {
193 compatible = "fsl,p1022-l2-cache-controller";
194 reg = <0x20000 0x1000>;
195 cache-line-size = <32>; // 32 bytes
196 cache-size = <0x40000>; // L2,256K
197 interrupts = <16 2 0 0>;
198 };
199
200/include/ "pq3-dma-0.dtsi"
201/include/ "pq3-usb2-dr-0.dtsi"
202/include/ "pq3-usb2-dr-1.dtsi"
203
204/include/ "pq3-esdhc-0.dtsi"
205 sdhc@2e000 {
206 fsl,sdhci-auto-cmd12;
207 };
208
209/include/ "pq3-sec3.3-0.dtsi"
210/include/ "pq3-mpic.dtsi"
211/include/ "pq3-mpic-timer-B.dtsi"
212
213/include/ "pq3-etsec2-0.dtsi"
214 enet0: enet0_grp2: ethernet@b0000 {
215 };
216
217/include/ "pq3-etsec2-1.dtsi"
218 enet1: enet1_grp2: ethernet@b1000 {
219 };
220
221 global-utilities@e0000 {
222 compatible = "fsl,p1022-guts";
223 reg = <0xe0000 0x1000>;
224 fsl,has-rstcr;
225 };
226
227 power@e0070{
228 compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc";
229 reg = <0xe0070 0x20>;
230 };
231
232};
233
234/include/ "pq3-etsec2-grp2-0.dtsi"
235/include/ "pq3-etsec2-grp2-1.dtsi"
diff --git a/arch/powerpc/boot/dts/fsl/p1022si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p1022si-pre.dtsi
new file mode 100644
index 000000000000..e930f4f7ca89
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p1022si-pre.dtsi
@@ -0,0 +1,68 @@
1/*
2 * P1022/P1013 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36/ {
37 compatible = "fsl,P1022";
38 #address-cells = <2>;
39 #size-cells = <2>;
40 interrupt-parent = <&mpic>;
41
42 aliases {
43 serial0 = &serial0;
44 serial1 = &serial1;
45 ethernet0 = &enet0;
46 ethernet1 = &enet1;
47 pci0 = &pci0;
48 pci1 = &pci1;
49 pci2 = &pci2;
50 };
51
52 cpus {
53 #address-cells = <1>;
54 #size-cells = <0>;
55
56 PowerPC,P1022@0 {
57 device_type = "cpu";
58 reg = <0x0>;
59 next-level-cache = <&L2>;
60 };
61
62 PowerPC,P1022@1 {
63 device_type = "cpu";
64 reg = <0x1>;
65 next-level-cache = <&L2>;
66 };
67 };
68};
diff --git a/arch/powerpc/boot/dts/p1022ds.dts b/arch/powerpc/boot/dts/p1022ds.dts
index b9b8719a6204..24a73e978f82 100644
--- a/arch/powerpc/boot/dts/p1022ds.dts
+++ b/arch/powerpc/boot/dts/p1022ds.dts
@@ -8,55 +8,20 @@
8 * kind, whether express or implied. 8 * kind, whether express or implied.
9 */ 9 */
10 10
11/dts-v1/; 11/include/ "fsl/p1022si-pre.dtsi"
12/ { 12/ {
13 model = "fsl,P1022"; 13 model = "fsl,P1022DS";
14 compatible = "fsl,P1022DS"; 14 compatible = "fsl,P1022DS";
15 #address-cells = <2>;
16 #size-cells = <2>;
17 interrupt-parent = <&mpic>;
18
19 aliases {
20 ethernet0 = &enet0;
21 ethernet1 = &enet1;
22 serial0 = &serial0;
23 serial1 = &serial1;
24 pci0 = &pci0;
25 pci1 = &pci1;
26 pci2 = &pci2;
27 };
28
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 PowerPC,P1022@0 {
34 device_type = "cpu";
35 reg = <0x0>;
36 next-level-cache = <&L2>;
37 };
38
39 PowerPC,P1022@1 {
40 device_type = "cpu";
41 reg = <0x1>;
42 next-level-cache = <&L2>;
43 };
44 };
45 15
46 memory { 16 memory {
47 device_type = "memory"; 17 device_type = "memory";
48 }; 18 };
49 19
50 localbus@fffe05000 { 20 lbc: localbus@fffe05000 {
51 #address-cells = <2>; 21 reg = <0xf 0xffe05000 0 0x1000>;
52 #size-cells = <1>;
53 compatible = "fsl,p1022-elbc", "fsl,elbc", "simple-bus";
54 reg = <0 0xffe05000 0 0x1000>;
55 interrupts = <19 2 0 0>;
56
57 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000 22 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
58 0x1 0x0 0xf 0xe0000000 0x08000000 23 0x1 0x0 0xf 0xe0000000 0x08000000
59 0x2 0x0 0x0 0xffa00000 0x00040000 24 0x2 0x0 0xf 0xffa00000 0x00040000
60 0x3 0x0 0xf 0xffdf0000 0x00008000>; 25 0x3 0x0 0xf 0xffdf0000 0x00008000>;
61 26
62 nor@0,0 { 27 nor@0,0 {
@@ -161,51 +126,10 @@
161 }; 126 };
162 }; 127 };
163 128
164 soc@fffe00000 { 129 soc: soc@fffe00000 {
165 #address-cells = <1>;
166 #size-cells = <1>;
167 device_type = "soc";
168 compatible = "fsl,p1022-immr", "simple-bus";
169 ranges = <0x0 0xf 0xffe00000 0x100000>; 130 ranges = <0x0 0xf 0xffe00000 0x100000>;
170 bus-frequency = <0>; // Filled out by uboot.
171
172 ecm-law@0 {
173 compatible = "fsl,ecm-law";
174 reg = <0x0 0x1000>;
175 fsl,num-laws = <12>;
176 };
177
178 ecm@1000 {
179 compatible = "fsl,p1022-ecm", "fsl,ecm";
180 reg = <0x1000 0x1000>;
181 interrupts = <16 2 0 0>;
182 };
183
184 memory-controller@2000 {
185 compatible = "fsl,p1022-memory-controller";
186 reg = <0x2000 0x1000>;
187 interrupts = <16 2 0 0>;
188 };
189
190 i2c@3000 {
191 #address-cells = <1>;
192 #size-cells = <0>;
193 cell-index = <0>;
194 compatible = "fsl-i2c";
195 reg = <0x3000 0x100>;
196 interrupts = <43 2 0 0>;
197 dfsrr;
198 };
199 131
200 i2c@3100 { 132 i2c@3100 {
201 #address-cells = <1>;
202 #size-cells = <0>;
203 cell-index = <1>;
204 compatible = "fsl-i2c";
205 reg = <0x3100 0x100>;
206 interrupts = <43 2 0 0>;
207 dfsrr;
208
209 wm8776:codec@1a { 133 wm8776:codec@1a {
210 compatible = "wlf,wm8776"; 134 compatible = "wlf,wm8776";
211 reg = <0x1a>; 135 reg = <0x1a>;
@@ -216,41 +140,14 @@
216 }; 140 };
217 }; 141 };
218 142
219 serial0: serial@4500 {
220 cell-index = <0>;
221 device_type = "serial";
222 compatible = "ns16550";
223 reg = <0x4500 0x100>;
224 clock-frequency = <0>;
225 interrupts = <42 2 0 0>;
226 };
227
228 serial1: serial@4600 {
229 cell-index = <1>;
230 device_type = "serial";
231 compatible = "ns16550";
232 reg = <0x4600 0x100>;
233 clock-frequency = <0>;
234 interrupts = <42 2 0 0>;
235 };
236
237 spi@7000 { 143 spi@7000 {
238 cell-index = <0>; 144 flash@0 {
239 #address-cells = <1>;
240 #size-cells = <0>;
241 compatible = "fsl,espi";
242 reg = <0x7000 0x1000>;
243 interrupts = <59 0x2 0 0>;
244 espi,num-ss-bits = <4>;
245 mode = "cpu";
246
247 fsl_m25p80@0 {
248 #address-cells = <1>; 145 #address-cells = <1>;
249 #size-cells = <1>; 146 #size-cells = <1>;
250 compatible = "fsl,espi-flash"; 147 compatible = "spansion,s25sl12801";
251 reg = <0>; 148 reg = <0>;
252 linux,modalias = "fsl_m25p80";
253 spi-max-frequency = <40000000>; /* input clock */ 149 spi-max-frequency = <40000000>; /* input clock */
150
254 partition@0 { 151 partition@0 {
255 label = "u-boot-spi"; 152 label = "u-boot-spi";
256 reg = <0x00000000 0x00100000>; 153 reg = <0x00000000 0x00100000>;
@@ -274,115 +171,20 @@
274 }; 171 };
275 172
276 ssi@15000 { 173 ssi@15000 {
277 compatible = "fsl,mpc8610-ssi";
278 cell-index = <0>;
279 reg = <0x15000 0x100>;
280 interrupts = <75 2 0 0>;
281 fsl,mode = "i2s-slave"; 174 fsl,mode = "i2s-slave";
282 codec-handle = <&wm8776>; 175 codec-handle = <&wm8776>;
283 fsl,playback-dma = <&dma00>;
284 fsl,capture-dma = <&dma01>;
285 fsl,fifo-depth = <15>;
286 fsl,ssi-asynchronous; 176 fsl,ssi-asynchronous;
287 }; 177 };
288 178
289 dma@c300 {
290 #address-cells = <1>;
291 #size-cells = <1>;
292 compatible = "fsl,eloplus-dma";
293 reg = <0xc300 0x4>;
294 ranges = <0x0 0xc100 0x200>;
295 cell-index = <1>;
296 dma00: dma-channel@0 {
297 compatible = "fsl,ssi-dma-channel";
298 reg = <0x0 0x80>;
299 cell-index = <0>;
300 interrupts = <76 2 0 0>;
301 };
302 dma01: dma-channel@80 {
303 compatible = "fsl,ssi-dma-channel";
304 reg = <0x80 0x80>;
305 cell-index = <1>;
306 interrupts = <77 2 0 0>;
307 };
308 dma-channel@100 {
309 compatible = "fsl,eloplus-dma-channel";
310 reg = <0x100 0x80>;
311 cell-index = <2>;
312 interrupts = <78 2 0 0>;
313 };
314 dma-channel@180 {
315 compatible = "fsl,eloplus-dma-channel";
316 reg = <0x180 0x80>;
317 cell-index = <3>;
318 interrupts = <79 2 0 0>;
319 };
320 };
321
322 gpio: gpio-controller@f000 {
323 #gpio-cells = <2>;
324 compatible = "fsl,mpc8572-gpio";
325 reg = <0xf000 0x100>;
326 interrupts = <47 0x2 0 0>;
327 gpio-controller;
328 };
329
330 L2: l2-cache-controller@20000 {
331 compatible = "fsl,p1022-l2-cache-controller";
332 reg = <0x20000 0x1000>;
333 cache-line-size = <32>; // 32 bytes
334 cache-size = <0x40000>; // L2, 256K
335 interrupts = <16 2 0 0>;
336 };
337
338 dma@21300 {
339 #address-cells = <1>;
340 #size-cells = <1>;
341 compatible = "fsl,eloplus-dma";
342 reg = <0x21300 0x4>;
343 ranges = <0x0 0x21100 0x200>;
344 cell-index = <0>;
345 dma-channel@0 {
346 compatible = "fsl,eloplus-dma-channel";
347 reg = <0x0 0x80>;
348 cell-index = <0>;
349 interrupts = <20 2 0 0>;
350 };
351 dma-channel@80 {
352 compatible = "fsl,eloplus-dma-channel";
353 reg = <0x80 0x80>;
354 cell-index = <1>;
355 interrupts = <21 2 0 0>;
356 };
357 dma-channel@100 {
358 compatible = "fsl,eloplus-dma-channel";
359 reg = <0x100 0x80>;
360 cell-index = <2>;
361 interrupts = <22 2 0 0>;
362 };
363 dma-channel@180 {
364 compatible = "fsl,eloplus-dma-channel";
365 reg = <0x180 0x80>;
366 cell-index = <3>;
367 interrupts = <23 2 0 0>;
368 };
369 };
370
371 usb@22000 { 179 usb@22000 {
372 #address-cells = <1>;
373 #size-cells = <0>;
374 compatible = "fsl-usb2-dr";
375 reg = <0x22000 0x1000>;
376 interrupts = <28 0x2 0 0>;
377 phy_type = "ulpi"; 180 phy_type = "ulpi";
378 }; 181 };
379 182
380 mdio@24000 { 183 usb@23000 {
381 #address-cells = <1>; 184 status = "disabled";
382 #size-cells = <0>; 185 };
383 compatible = "fsl,etsec2-mdio";
384 reg = <0x24000 0x1000 0xb0030 0x4>;
385 186
187 mdio@24000 {
386 phy0: ethernet-phy@0 { 188 phy0: ethernet-phy@0 {
387 interrupts = <3 1 0 0>; 189 interrupts = <3 1 0 0>;
388 reg = <0x1>; 190 reg = <0x1>;
@@ -393,187 +195,22 @@
393 }; 195 };
394 }; 196 };
395 197
396 mdio@25000 { 198 ethernet@b0000 {
397 #address-cells = <1>;
398 #size-cells = <0>;
399 compatible = "fsl,etsec2-mdio";
400 reg = <0x25000 0x1000 0xb1030 0x4>;
401 };
402
403 enet0: ethernet@B0000 {
404 #address-cells = <1>;
405 #size-cells = <1>;
406 cell-index = <0>;
407 device_type = "network";
408 model = "eTSEC";
409 compatible = "fsl,etsec2";
410 fsl,num_rx_queues = <0x8>;
411 fsl,num_tx_queues = <0x8>;
412 fsl,magic-packet;
413 fsl,wake-on-filer;
414 local-mac-address = [ 00 00 00 00 00 00 ];
415 phy-handle = <&phy0>; 199 phy-handle = <&phy0>;
416 phy-connection-type = "rgmii-id"; 200 phy-connection-type = "rgmii-id";
417 queue-group@0{
418 #address-cells = <1>;
419 #size-cells = <1>;
420 reg = <0xB0000 0x1000>;
421 interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
422 };
423 queue-group@1{
424 #address-cells = <1>;
425 #size-cells = <1>;
426 reg = <0xB4000 0x1000>;
427 interrupts = <17 2 0 0 18 2 0 0 24 2 0 0>;
428 };
429 }; 201 };
430 202
431 enet1: ethernet@B1000 { 203 ethernet@b1000 {
432 #address-cells = <1>;
433 #size-cells = <1>;
434 cell-index = <0>;
435 device_type = "network";
436 model = "eTSEC";
437 compatible = "fsl,etsec2";
438 fsl,num_rx_queues = <0x8>;
439 fsl,num_tx_queues = <0x8>;
440 local-mac-address = [ 00 00 00 00 00 00 ];
441 phy-handle = <&phy1>; 204 phy-handle = <&phy1>;
442 phy-connection-type = "rgmii-id"; 205 phy-connection-type = "rgmii-id";
443 queue-group@0{
444 #address-cells = <1>;
445 #size-cells = <1>;
446 reg = <0xB1000 0x1000>;
447 interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>;
448 };
449 queue-group@1{
450 #address-cells = <1>;
451 #size-cells = <1>;
452 reg = <0xB5000 0x1000>;
453 interrupts = <51 2 0 0 52 2 0 0 67 2 0 0>;
454 };
455 };
456
457 sdhci@2e000 {
458 compatible = "fsl,p1022-esdhc", "fsl,esdhc";
459 reg = <0x2e000 0x1000>;
460 interrupts = <72 0x2 0 0>;
461 fsl,sdhci-auto-cmd12;
462 /* Filled in by U-Boot */
463 clock-frequency = <0>;
464 };
465
466 crypto@30000 {
467 compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0",
468 "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1",
469 "fsl,sec2.0";
470 reg = <0x30000 0x10000>;
471 interrupts = <45 2 0 0 58 2 0 0>;
472 fsl,num-channels = <4>;
473 fsl,channel-fifo-len = <24>;
474 fsl,exec-units-mask = <0x97c>;
475 fsl,descriptor-types-mask = <0x3a30abf>;
476 };
477
478 sata@18000 {
479 compatible = "fsl,p1022-sata", "fsl,pq-sata-v2";
480 reg = <0x18000 0x1000>;
481 cell-index = <1>;
482 interrupts = <74 0x2 0 0>;
483 };
484
485 sata@19000 {
486 compatible = "fsl,p1022-sata", "fsl,pq-sata-v2";
487 reg = <0x19000 0x1000>;
488 cell-index = <2>;
489 interrupts = <41 0x2 0 0>;
490 };
491
492 power@e0070{
493 compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc";
494 reg = <0xe0070 0x20>;
495 };
496
497 display@10000 {
498 compatible = "fsl,diu", "fsl,p1022-diu";
499 reg = <0x10000 1000>;
500 interrupts = <64 2 0 0>;
501 };
502
503 timer@41100 {
504 compatible = "fsl,mpic-global-timer";
505 reg = <0x41100 0x100 0x41300 4>;
506 interrupts = <0 0 3 0
507 1 0 3 0
508 2 0 3 0
509 3 0 3 0>;
510 };
511
512 timer@42100 {
513 compatible = "fsl,mpic-global-timer";
514 reg = <0x42100 0x100 0x42300 4>;
515 interrupts = <4 0 3 0
516 5 0 3 0
517 6 0 3 0
518 7 0 3 0>;
519 };
520
521 mpic: pic@40000 {
522 interrupt-controller;
523 #address-cells = <0>;
524 #interrupt-cells = <4>;
525 reg = <0x40000 0x40000>;
526 compatible = "fsl,mpic";
527 device_type = "open-pic";
528 };
529
530 msi@41600 {
531 compatible = "fsl,p1022-msi", "fsl,mpic-msi";
532 reg = <0x41600 0x80>;
533 msi-available-ranges = <0 0x100>;
534 interrupts = <
535 0xe0 0 0 0
536 0xe1 0 0 0
537 0xe2 0 0 0
538 0xe3 0 0 0
539 0xe4 0 0 0
540 0xe5 0 0 0
541 0xe6 0 0 0
542 0xe7 0 0 0>;
543 };
544
545 global-utilities@e0000 { //global utilities block
546 compatible = "fsl,p1022-guts";
547 reg = <0xe0000 0x1000>;
548 fsl,has-rstcr;
549 }; 206 };
550 }; 207 };
551 208
552 pci0: pcie@fffe09000 { 209 pci0: pcie@fffe09000 {
553 compatible = "fsl,p1022-pcie";
554 device_type = "pci";
555 #interrupt-cells = <1>;
556 #size-cells = <2>;
557 #address-cells = <3>;
558 reg = <0xf 0xffe09000 0 0x1000>; 210 reg = <0xf 0xffe09000 0 0x1000>;
559 bus-range = <0 255>;
560 ranges = <0x2000000 0x0 0xa0000000 0xc 0x20000000 0x0 0x20000000 211 ranges = <0x2000000 0x0 0xa0000000 0xc 0x20000000 0x0 0x20000000
561 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>; 212 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
562 clock-frequency = <33333333>;
563 interrupts = <16 2 0 0>;
564 interrupt-map-mask = <0xf800 0 0 7>;
565 interrupt-map = <
566 /* IDSEL 0x0 */
567 0000 0 0 1 &mpic 4 1
568 0000 0 0 2 &mpic 5 1
569 0000 0 0 3 &mpic 6 1
570 0000 0 0 4 &mpic 7 1
571 >;
572 pcie@0 { 213 pcie@0 {
573 reg = <0x0 0x0 0x0 0x0 0x0>;
574 #size-cells = <2>;
575 #address-cells = <3>;
576 device_type = "pci";
577 ranges = <0x2000000 0x0 0xe0000000 214 ranges = <0x2000000 0x0 0xe0000000
578 0x2000000 0x0 0xe0000000 215 0x2000000 0x0 0xe0000000
579 0x0 0x20000000 216 0x0 0x20000000
@@ -585,30 +222,11 @@
585 }; 222 };
586 223
587 pci1: pcie@fffe0a000 { 224 pci1: pcie@fffe0a000 {
588 compatible = "fsl,p1022-pcie";
589 device_type = "pci";
590 #interrupt-cells = <1>;
591 #size-cells = <2>;
592 #address-cells = <3>;
593 reg = <0xf 0xffe0a000 0 0x1000>; 225 reg = <0xf 0xffe0a000 0 0x1000>;
594 bus-range = <0 255>;
595 ranges = <0x2000000 0x0 0xc0000000 0xc 0x40000000 0x0 0x20000000 226 ranges = <0x2000000 0x0 0xc0000000 0xc 0x40000000 0x0 0x20000000
596 0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x10000>; 227 0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x10000>;
597 clock-frequency = <33333333>;
598 interrupts = <16 2 0 0>;
599 interrupt-map-mask = <0xf800 0 0 7>;
600 interrupt-map = <
601 /* IDSEL 0x0 */
602 0000 0 0 1 &mpic 0 1
603 0000 0 0 2 &mpic 1 1
604 0000 0 0 3 &mpic 2 1
605 0000 0 0 4 &mpic 3 1
606 >;
607 pcie@0 { 228 pcie@0 {
608 reg = <0x0 0x0 0x0 0x0 0x0>; 229 reg = <0x0 0x0 0x0 0x0 0x0>;
609 #size-cells = <2>;
610 #address-cells = <3>;
611 device_type = "pci";
612 ranges = <0x2000000 0x0 0xe0000000 230 ranges = <0x2000000 0x0 0xe0000000
613 0x2000000 0x0 0xe0000000 231 0x2000000 0x0 0xe0000000
614 0x0 0x20000000 232 0x0 0x20000000
@@ -619,32 +237,11 @@
619 }; 237 };
620 }; 238 };
621 239
622
623 pci2: pcie@fffe0b000 { 240 pci2: pcie@fffe0b000 {
624 compatible = "fsl,p1022-pcie";
625 device_type = "pci";
626 #interrupt-cells = <1>;
627 #size-cells = <2>;
628 #address-cells = <3>;
629 reg = <0xf 0xffe0b000 0 0x1000>; 241 reg = <0xf 0xffe0b000 0 0x1000>;
630 bus-range = <0 255>;
631 ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000 242 ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000
632 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>; 243 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
633 clock-frequency = <33333333>;
634 interrupts = <16 2 0 0>;
635 interrupt-map-mask = <0xf800 0 0 7>;
636 interrupt-map = <
637 /* IDSEL 0x0 */
638 0000 0 0 1 &mpic 8 1
639 0000 0 0 2 &mpic 9 1
640 0000 0 0 3 &mpic 10 1
641 0000 0 0 4 &mpic 11 1
642 >;
643 pcie@0 { 244 pcie@0 {
644 reg = <0x0 0x0 0x0 0x0 0x0>;
645 #size-cells = <2>;
646 #address-cells = <3>;
647 device_type = "pci";
648 ranges = <0x2000000 0x0 0xe0000000 245 ranges = <0x2000000 0x0 0xe0000000
649 0x2000000 0x0 0xe0000000 246 0x2000000 0x0 0xe0000000
650 0x0 0x20000000 247 0x0 0x20000000
@@ -655,3 +252,5 @@
655 }; 252 };
656 }; 253 };
657}; 254};
255
256/include/ "fsl/p1022si-post.dtsi"
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-14 16:59:22 -0500