diff options
author | bjorn.helgaas@hp.com <bjorn.helgaas@hp.com> | 2007-12-17 16:09:40 -0500 |
---|---|---|
committer | Greg Kroah-Hartman <gregkh@suse.de> | 2008-02-01 18:04:27 -0500 |
commit | 9ed885541bc57a0810798ec1607a23a24a0e1b93 (patch) | |
tree | b8080d9d2cba2e64659876c0690392b5fc42cbdb /arch | |
parent | f0fda801daaa95ad5ccf59e92e0688c34b37c627 (diff) |
PCI: use dev_printk in x86 quirk messages
Convert quirk printks to dev_printk().
Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/x86/kernel/quirks.c | 43 | ||||
-rw-r--r-- | arch/x86/pci/fixup.c | 22 |
2 files changed, 34 insertions, 31 deletions
diff --git a/arch/x86/kernel/quirks.c b/arch/x86/kernel/quirks.c index 150ba29a0d33..3cd7a2dcd4fe 100644 --- a/arch/x86/kernel/quirks.c +++ b/arch/x86/kernel/quirks.c | |||
@@ -30,8 +30,8 @@ static void __devinit quirk_intel_irqbalance(struct pci_dev *dev) | |||
30 | raw_pci_ops->read(0, 0, 0x40, 0x4c, 2, &word); | 30 | raw_pci_ops->read(0, 0, 0x40, 0x4c, 2, &word); |
31 | 31 | ||
32 | if (!(word & (1 << 13))) { | 32 | if (!(word & (1 << 13))) { |
33 | printk(KERN_INFO "Intel E7520/7320/7525 detected. " | 33 | dev_info(&dev->dev, "Intel E7520/7320/7525 detected; " |
34 | "Disabling irq balancing and affinity\n"); | 34 | "disabling irq balancing and affinity\n"); |
35 | #ifdef CONFIG_IRQBALANCE | 35 | #ifdef CONFIG_IRQBALANCE |
36 | irqbalance_disable(""); | 36 | irqbalance_disable(""); |
37 | #endif | 37 | #endif |
@@ -104,14 +104,16 @@ static void ich_force_enable_hpet(struct pci_dev *dev) | |||
104 | pci_read_config_dword(dev, 0xF0, &rcba); | 104 | pci_read_config_dword(dev, 0xF0, &rcba); |
105 | rcba &= 0xFFFFC000; | 105 | rcba &= 0xFFFFC000; |
106 | if (rcba == 0) { | 106 | if (rcba == 0) { |
107 | printk(KERN_DEBUG "RCBA disabled. Cannot force enable HPET\n"); | 107 | dev_printk(KERN_DEBUG, &dev->dev, "RCBA disabled; " |
108 | "cannot force enable HPET\n"); | ||
108 | return; | 109 | return; |
109 | } | 110 | } |
110 | 111 | ||
111 | /* use bits 31:14, 16 kB aligned */ | 112 | /* use bits 31:14, 16 kB aligned */ |
112 | rcba_base = ioremap_nocache(rcba, 0x4000); | 113 | rcba_base = ioremap_nocache(rcba, 0x4000); |
113 | if (rcba_base == NULL) { | 114 | if (rcba_base == NULL) { |
114 | printk(KERN_DEBUG "ioremap failed. Cannot force enable HPET\n"); | 115 | dev_printk(KERN_DEBUG, &dev->dev, "ioremap failed; " |
116 | "cannot force enable HPET\n"); | ||
115 | return; | 117 | return; |
116 | } | 118 | } |
117 | 119 | ||
@@ -122,8 +124,8 @@ static void ich_force_enable_hpet(struct pci_dev *dev) | |||
122 | /* HPET is enabled in HPTC. Just not reported by BIOS */ | 124 | /* HPET is enabled in HPTC. Just not reported by BIOS */ |
123 | val = val & 0x3; | 125 | val = val & 0x3; |
124 | force_hpet_address = 0xFED00000 | (val << 12); | 126 | force_hpet_address = 0xFED00000 | (val << 12); |
125 | printk(KERN_DEBUG "Force enabled HPET at base address 0x%lx\n", | 127 | dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at " |
126 | force_hpet_address); | 128 | "0x%lx\n", force_hpet_address); |
127 | iounmap(rcba_base); | 129 | iounmap(rcba_base); |
128 | return; | 130 | return; |
129 | } | 131 | } |
@@ -142,11 +144,12 @@ static void ich_force_enable_hpet(struct pci_dev *dev) | |||
142 | if (err) { | 144 | if (err) { |
143 | force_hpet_address = 0; | 145 | force_hpet_address = 0; |
144 | iounmap(rcba_base); | 146 | iounmap(rcba_base); |
145 | printk(KERN_DEBUG "Failed to force enable HPET\n"); | 147 | dev_printk(KERN_DEBUG, &dev->dev, |
148 | "Failed to force enable HPET\n"); | ||
146 | } else { | 149 | } else { |
147 | force_hpet_resume_type = ICH_FORCE_HPET_RESUME; | 150 | force_hpet_resume_type = ICH_FORCE_HPET_RESUME; |
148 | printk(KERN_DEBUG "Force enabled HPET at base address 0x%lx\n", | 151 | dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at " |
149 | force_hpet_address); | 152 | "0x%lx\n", force_hpet_address); |
150 | } | 153 | } |
151 | } | 154 | } |
152 | 155 | ||
@@ -208,8 +211,8 @@ static void old_ich_force_enable_hpet(struct pci_dev *dev) | |||
208 | if (val & 0x4) { | 211 | if (val & 0x4) { |
209 | val &= 0x3; | 212 | val &= 0x3; |
210 | force_hpet_address = 0xFED00000 | (val << 12); | 213 | force_hpet_address = 0xFED00000 | (val << 12); |
211 | printk(KERN_DEBUG "HPET at base address 0x%lx\n", | 214 | dev_printk(KERN_DEBUG, &dev->dev, "HPET at 0x%lx\n", |
212 | force_hpet_address); | 215 | force_hpet_address); |
213 | return; | 216 | return; |
214 | } | 217 | } |
215 | 218 | ||
@@ -229,14 +232,14 @@ static void old_ich_force_enable_hpet(struct pci_dev *dev) | |||
229 | /* HPET is enabled in HPTC. Just not reported by BIOS */ | 232 | /* HPET is enabled in HPTC. Just not reported by BIOS */ |
230 | val &= 0x3; | 233 | val &= 0x3; |
231 | force_hpet_address = 0xFED00000 | (val << 12); | 234 | force_hpet_address = 0xFED00000 | (val << 12); |
232 | printk(KERN_DEBUG "Force enabled HPET at base address 0x%lx\n", | 235 | dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at " |
233 | force_hpet_address); | 236 | "0x%lx\n", force_hpet_address); |
234 | cached_dev = dev; | 237 | cached_dev = dev; |
235 | force_hpet_resume_type = OLD_ICH_FORCE_HPET_RESUME; | 238 | force_hpet_resume_type = OLD_ICH_FORCE_HPET_RESUME; |
236 | return; | 239 | return; |
237 | } | 240 | } |
238 | 241 | ||
239 | printk(KERN_DEBUG "Failed to force enable HPET\n"); | 242 | dev_printk(KERN_DEBUG, &dev->dev, "Failed to force enable HPET\n"); |
240 | } | 243 | } |
241 | 244 | ||
242 | /* | 245 | /* |
@@ -294,8 +297,8 @@ static void vt8237_force_enable_hpet(struct pci_dev *dev) | |||
294 | */ | 297 | */ |
295 | if (val & 0x80) { | 298 | if (val & 0x80) { |
296 | force_hpet_address = (val & ~0x3ff); | 299 | force_hpet_address = (val & ~0x3ff); |
297 | printk(KERN_DEBUG "HPET at base address 0x%lx\n", | 300 | dev_printk(KERN_DEBUG, &dev->dev, "HPET at 0x%lx\n", |
298 | force_hpet_address); | 301 | force_hpet_address); |
299 | return; | 302 | return; |
300 | } | 303 | } |
301 | 304 | ||
@@ -309,14 +312,14 @@ static void vt8237_force_enable_hpet(struct pci_dev *dev) | |||
309 | pci_read_config_dword(dev, 0x68, &val); | 312 | pci_read_config_dword(dev, 0x68, &val); |
310 | if (val & 0x80) { | 313 | if (val & 0x80) { |
311 | force_hpet_address = (val & ~0x3ff); | 314 | force_hpet_address = (val & ~0x3ff); |
312 | printk(KERN_DEBUG "Force enabled HPET at base address 0x%lx\n", | 315 | dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at " |
313 | force_hpet_address); | 316 | "0x%lx\n", force_hpet_address); |
314 | cached_dev = dev; | 317 | cached_dev = dev; |
315 | force_hpet_resume_type = VT8237_FORCE_HPET_RESUME; | 318 | force_hpet_resume_type = VT8237_FORCE_HPET_RESUME; |
316 | return; | 319 | return; |
317 | } | 320 | } |
318 | 321 | ||
319 | printk(KERN_DEBUG "Failed to force enable HPET\n"); | 322 | dev_printk(KERN_DEBUG, &dev->dev, "Failed to force enable HPET\n"); |
320 | } | 323 | } |
321 | 324 | ||
322 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, | 325 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, |
@@ -344,7 +347,7 @@ static void nvidia_force_enable_hpet(struct pci_dev *dev) | |||
344 | pci_read_config_dword(dev, 0x44, &val); | 347 | pci_read_config_dword(dev, 0x44, &val); |
345 | force_hpet_address = val & 0xfffffffe; | 348 | force_hpet_address = val & 0xfffffffe; |
346 | force_hpet_resume_type = NVIDIA_FORCE_HPET_RESUME; | 349 | force_hpet_resume_type = NVIDIA_FORCE_HPET_RESUME; |
347 | printk(KERN_DEBUG "Force enabled HPET at base address 0x%lx\n", | 350 | dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at 0x%lx\n", |
348 | force_hpet_address); | 351 | force_hpet_address); |
349 | cached_dev = dev; | 352 | cached_dev = dev; |
350 | return; | 353 | return; |
diff --git a/arch/x86/pci/fixup.c b/arch/x86/pci/fixup.c index cb63007e20b2..74d30ff33c49 100644 --- a/arch/x86/pci/fixup.c +++ b/arch/x86/pci/fixup.c | |||
@@ -17,7 +17,7 @@ static void __devinit pci_fixup_i450nx(struct pci_dev *d) | |||
17 | int pxb, reg; | 17 | int pxb, reg; |
18 | u8 busno, suba, subb; | 18 | u8 busno, suba, subb; |
19 | 19 | ||
20 | printk(KERN_WARNING "PCI: Searching for i450NX host bridges on %s\n", pci_name(d)); | 20 | dev_warn(&d->dev, "Searching for i450NX host bridges\n"); |
21 | reg = 0xd0; | 21 | reg = 0xd0; |
22 | for(pxb = 0; pxb < 2; pxb++) { | 22 | for(pxb = 0; pxb < 2; pxb++) { |
23 | pci_read_config_byte(d, reg++, &busno); | 23 | pci_read_config_byte(d, reg++, &busno); |
@@ -41,7 +41,7 @@ static void __devinit pci_fixup_i450gx(struct pci_dev *d) | |||
41 | */ | 41 | */ |
42 | u8 busno; | 42 | u8 busno; |
43 | pci_read_config_byte(d, 0x4a, &busno); | 43 | pci_read_config_byte(d, 0x4a, &busno); |
44 | printk(KERN_INFO "PCI: i440KX/GX host bridge %s: secondary bus %02x\n", pci_name(d), busno); | 44 | dev_info(&d->dev, "i440KX/GX host bridge; secondary bus %02x\n", busno); |
45 | pci_scan_bus_with_sysdata(busno); | 45 | pci_scan_bus_with_sysdata(busno); |
46 | pcibios_last_bus = -1; | 46 | pcibios_last_bus = -1; |
47 | } | 47 | } |
@@ -55,7 +55,7 @@ static void __devinit pci_fixup_umc_ide(struct pci_dev *d) | |||
55 | */ | 55 | */ |
56 | int i; | 56 | int i; |
57 | 57 | ||
58 | printk(KERN_WARNING "PCI: Fixing base address flags for device %s\n", pci_name(d)); | 58 | dev_warn(&d->dev, "Fixing base address flags\n"); |
59 | for(i = 0; i < 4; i++) | 59 | for(i = 0; i < 4; i++) |
60 | d->resource[i].flags |= PCI_BASE_ADDRESS_SPACE_IO; | 60 | d->resource[i].flags |= PCI_BASE_ADDRESS_SPACE_IO; |
61 | } | 61 | } |
@@ -68,7 +68,7 @@ static void __devinit pci_fixup_ncr53c810(struct pci_dev *d) | |||
68 | * Fix class to be PCI_CLASS_STORAGE_SCSI | 68 | * Fix class to be PCI_CLASS_STORAGE_SCSI |
69 | */ | 69 | */ |
70 | if (!d->class) { | 70 | if (!d->class) { |
71 | printk(KERN_WARNING "PCI: fixing NCR 53C810 class code for %s\n", pci_name(d)); | 71 | dev_warn(&d->dev, "Fixing NCR 53C810 class code\n"); |
72 | d->class = PCI_CLASS_STORAGE_SCSI << 8; | 72 | d->class = PCI_CLASS_STORAGE_SCSI << 8; |
73 | } | 73 | } |
74 | } | 74 | } |
@@ -80,7 +80,7 @@ static void __devinit pci_fixup_latency(struct pci_dev *d) | |||
80 | * SiS 5597 and 5598 chipsets require latency timer set to | 80 | * SiS 5597 and 5598 chipsets require latency timer set to |
81 | * at most 32 to avoid lockups. | 81 | * at most 32 to avoid lockups. |
82 | */ | 82 | */ |
83 | DBG("PCI: Setting max latency to 32\n"); | 83 | dev_dbg(&d->dev, "Setting max latency to 32\n"); |
84 | pcibios_max_latency = 32; | 84 | pcibios_max_latency = 32; |
85 | } | 85 | } |
86 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, pci_fixup_latency); | 86 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, pci_fixup_latency); |
@@ -138,7 +138,7 @@ static void pci_fixup_via_northbridge_bug(struct pci_dev *d) | |||
138 | 138 | ||
139 | pci_read_config_byte(d, where, &v); | 139 | pci_read_config_byte(d, where, &v); |
140 | if (v & ~mask) { | 140 | if (v & ~mask) { |
141 | printk(KERN_WARNING "Disabling VIA memory write queue (PCI ID %04x, rev %02x): [%02x] %02x & %02x -> %02x\n", \ | 141 | dev_warn(&d->dev, "Disabling VIA memory write queue (PCI ID %04x, rev %02x): [%02x] %02x & %02x -> %02x\n", \ |
142 | d->device, d->revision, where, v, mask, v & mask); | 142 | d->device, d->revision, where, v, mask, v & mask); |
143 | v &= mask; | 143 | v &= mask; |
144 | pci_write_config_byte(d, where, v); | 144 | pci_write_config_byte(d, where, v); |
@@ -200,7 +200,7 @@ static void pci_fixup_nforce2(struct pci_dev *dev) | |||
200 | * Apply fixup if needed, but don't touch disconnect state | 200 | * Apply fixup if needed, but don't touch disconnect state |
201 | */ | 201 | */ |
202 | if ((val & 0x00FF0000) != 0x00010000) { | 202 | if ((val & 0x00FF0000) != 0x00010000) { |
203 | printk(KERN_WARNING "PCI: nForce2 C1 Halt Disconnect fixup\n"); | 203 | dev_warn(&dev->dev, "nForce2 C1 Halt Disconnect fixup\n"); |
204 | pci_write_config_dword(dev, 0x6c, (val & 0xFF00FFFF) | 0x00010000); | 204 | pci_write_config_dword(dev, 0x6c, (val & 0xFF00FFFF) | 0x00010000); |
205 | } | 205 | } |
206 | } | 206 | } |
@@ -348,7 +348,7 @@ static void __devinit pci_fixup_video(struct pci_dev *pdev) | |||
348 | pci_read_config_word(pdev, PCI_COMMAND, &config); | 348 | pci_read_config_word(pdev, PCI_COMMAND, &config); |
349 | if (config & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) { | 349 | if (config & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) { |
350 | pdev->resource[PCI_ROM_RESOURCE].flags |= IORESOURCE_ROM_SHADOW; | 350 | pdev->resource[PCI_ROM_RESOURCE].flags |= IORESOURCE_ROM_SHADOW; |
351 | printk(KERN_DEBUG "Boot video device is %s\n", pci_name(pdev)); | 351 | dev_printk(KERN_DEBUG, &pdev->dev, "Boot video device\n"); |
352 | } | 352 | } |
353 | } | 353 | } |
354 | DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_video); | 354 | DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_video); |
@@ -388,11 +388,11 @@ static void __devinit pci_fixup_msi_k8t_onboard_sound(struct pci_dev *dev) | |||
388 | /* verify the change for status output */ | 388 | /* verify the change for status output */ |
389 | pci_read_config_byte(dev, 0x50, &val); | 389 | pci_read_config_byte(dev, 0x50, &val); |
390 | if (val & 0x40) | 390 | if (val & 0x40) |
391 | printk(KERN_INFO "PCI: Detected MSI K8T Neo2-FIR, " | 391 | dev_info(&dev->dev, "Detected MSI K8T Neo2-FIR; " |
392 | "can't enable onboard soundcard!\n"); | 392 | "can't enable onboard soundcard!\n"); |
393 | else | 393 | else |
394 | printk(KERN_INFO "PCI: Detected MSI K8T Neo2-FIR, " | 394 | dev_info(&dev->dev, "Detected MSI K8T Neo2-FIR; " |
395 | "enabled onboard soundcard.\n"); | 395 | "enabled onboard soundcard\n"); |
396 | } | 396 | } |
397 | } | 397 | } |
398 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, | 398 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, |