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authorMichael Cree <mcree@orcon.net.nz>2010-08-09 20:20:07 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2010-08-09 23:45:04 -0400
commit92484f10ca8f7d36f0bfad92b66a20aa03120cc0 (patch)
treed323dd83db710a4512ca0bf40608fb18d66d096f /arch
parent65d920646a1c720c5ba95b7643ab1b46167d9e6a (diff)
alpha: add wrperfmon.h header file to aid use of wrperfmon PALcall
Signed-off-by: Michael Cree <mcree@orcon.net.nz> Cc: Richard Henderson <rth@twiddle.net> Cc: Ivan Kokshaysky <ink@jurassic.park.msu.ru> Cc: Matt Turner <mattst88@gmail.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Ingo Molnar <mingo@elte.hu> Cc: Jay Estabrook <jay.estabrook@hp.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/alpha/include/asm/wrperfmon.h93
1 files changed, 93 insertions, 0 deletions
diff --git a/arch/alpha/include/asm/wrperfmon.h b/arch/alpha/include/asm/wrperfmon.h
new file mode 100644
index 000000000000..319bf6788d87
--- /dev/null
+++ b/arch/alpha/include/asm/wrperfmon.h
@@ -0,0 +1,93 @@
1/*
2 * Definitions for use with the Alpha wrperfmon PAL call.
3 */
4
5#ifndef __ALPHA_WRPERFMON_H
6#define __ALPHA_WRPERFMON_H
7
8/* Following commands are implemented on all CPUs */
9#define PERFMON_CMD_DISABLE 0
10#define PERFMON_CMD_ENABLE 1
11#define PERFMON_CMD_DESIRED_EVENTS 2
12#define PERFMON_CMD_LOGGING_OPTIONS 3
13/* Following commands on EV5/EV56/PCA56 only */
14#define PERFMON_CMD_INT_FREQ 4
15#define PERFMON_CMD_ENABLE_CLEAR 7
16/* Following commands are on EV5 and better CPUs */
17#define PERFMON_CMD_READ 5
18#define PERFMON_CMD_WRITE 6
19/* Following command are on EV6 and better CPUs */
20#define PERFMON_CMD_ENABLE_WRITE 7
21/* Following command are on EV67 and better CPUs */
22#define PERFMON_CMD_I_STAT 8
23#define PERFMON_CMD_PMPC 9
24
25
26/* EV5/EV56/PCA56 Counters */
27#define EV5_PCTR_0 (1UL<<0)
28#define EV5_PCTR_1 (1UL<<1)
29#define EV5_PCTR_2 (1UL<<2)
30
31#define EV5_PCTR_0_COUNT_SHIFT 48
32#define EV5_PCTR_1_COUNT_SHIFT 32
33#define EV5_PCTR_2_COUNT_SHIFT 16
34
35#define EV5_PCTR_0_COUNT_MASK 0xffffUL
36#define EV5_PCTR_1_COUNT_MASK 0xffffUL
37#define EV5_PCTR_2_COUNT_MASK 0x3fffUL
38
39/* EV6 Counters */
40#define EV6_PCTR_0 (1UL<<0)
41#define EV6_PCTR_1 (1UL<<1)
42
43#define EV6_PCTR_0_COUNT_SHIFT 28
44#define EV6_PCTR_1_COUNT_SHIFT 6
45
46#define EV6_PCTR_0_COUNT_MASK 0xfffffUL
47#define EV6_PCTR_1_COUNT_MASK 0xfffffUL
48
49/* EV67 (and subsequent) counters */
50#define EV67_PCTR_0 (1UL<<0)
51#define EV67_PCTR_1 (1UL<<1)
52
53#define EV67_PCTR_0_COUNT_SHIFT 28
54#define EV67_PCTR_1_COUNT_SHIFT 6
55
56#define EV67_PCTR_0_COUNT_MASK 0xfffffUL
57#define EV67_PCTR_1_COUNT_MASK 0xfffffUL
58
59
60/*
61 * The Alpha Architecure Handbook, vers. 4 (1998) appears to have a misprint
62 * in Table E-23 regarding the bits that set the event PCTR 1 counts.
63 * Hopefully what we have here is correct.
64 */
65#define EV6_PCTR_0_EVENT_MASK 0x10UL
66#define EV6_PCTR_1_EVENT_MASK 0x0fUL
67
68/* EV6 Events */
69#define EV6_PCTR_0_CYCLES (0UL << 4)
70#define EV6_PCTR_0_INSTRUCTIONS (1UL << 4)
71
72#define EV6_PCTR_1_CYCLES 0
73#define EV6_PCTR_1_BRANCHES 1
74#define EV6_PCTR_1_BRANCH_MISPREDICTS 2
75#define EV6_PCTR_1_DTB_SINGLE_MISSES 3
76#define EV6_PCTR_1_DTB_DOUBLE_MISSES 4
77#define EV6_PCTR_1_ITB_MISSES 5
78#define EV6_PCTR_1_UNALIGNED_TRAPS 6
79#define EV6_PCTR_1_REPLY_TRAPS 7
80
81/* From the Alpha Architecture Reference Manual, 4th edn., 2002 */
82#define EV67_PCTR_MODE_MASK 0x10UL
83#define EV67_PCTR_EVENT_MASK 0x0CUL
84
85#define EV67_PCTR_MODE_PROFILEME (1UL<<4)
86#define EV67_PCTR_MODE_AGGREGATE (0UL<<4)
87
88#define EV67_PCTR_INSTR_CYCLES (0UL<<2)
89#define EV67_PCTR_CYCLES_UNDEF (1UL<<2)
90#define EV67_PCTR_INSTR_BCACHEMISS (2UL<<2)
91#define EV67_PCTR_CYCLES_MBOX (3UL<<2)
92
93#endif