diff options
author | Hirokazu Takata <takata@linux-m32r.org> | 2006-04-19 01:21:20 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-04-19 12:13:50 -0400 |
commit | 8e8ff02c0b61d9b7c15c7996a2eddbedf51a105b (patch) | |
tree | dde7fcedee5d8720f5cc95da5ed4629fd3369bc8 /arch | |
parent | efe87d2b822e42975b4da958c9d321cf89bfeb5a (diff) |
[PATCH] m32r: Fix pt_regs for !COFNIG_ISA_DSP_LEVEL2 target
This modification is required to fix debugging function for m32r targets
with !CONFIG_ISA_DSP_LEVEL2, by unifying 'struct pt_regs' and 'struct
sigcontext' size for all M32R ISA.
Some m32r processor core with !CONFIG_ISA_DSP_LEVEL2 configuration has only
single accumulator a0 (ex. VDEC2 core, M32102 core, etc.), the others with
CONFIG_ISA_DSP_LEVEL2 has two accumulators, a0 and a1.
This means there are two variations of thread context. So far, we reduced
and changed stackframe size at a syscall for their context size. However,
this causes a problem that a GDB for processors with CONFIG_ISA_DSP_LEVEL2
cannot be used for processors with !CONFIG_ISA_DSP_LEVEL2.
From the viewpoint of GDB support, we should reduce such variation of
stackframe size for simplicity.
In this patch, dummy members are added to 'struct pt_regs' and 'struct
sigcontext' to adjust their size for !CONFIG_ISA_DSP_LEVEL2.
This modification is also a one step for a GDB update in future.
Currently, on the m32r, GDB can access process's context by using ptrace
functions in a simple way of register by register access. By unifying
stackframe size, we have a possibility to make use of ptrace functions of
not only a single register access but also block register access,
PTRACE_{GETREGS,PUTREGS}.
However, for this purpose, we might have to modify stackframe structure
some more; for example, PSW (processor status word) register should be
pre-processed before pushing to stack at a syscall, and so on. In this
case, we must update carefully both kernel and GDB at a time...
Signed-off-by: Hayato Fujiwara <fujiwara@linux-m32r.org>
Signed-off-by: Hirokazu Takata <takata@linux-m32r.org>
Cc: Kei Sakamoto <ksakamot@linux-m32r.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/m32r/kernel/entry.S | 49 | ||||
-rw-r--r-- | arch/m32r/kernel/signal.c | 4 |
2 files changed, 23 insertions, 30 deletions
diff --git a/arch/m32r/kernel/entry.S b/arch/m32r/kernel/entry.S index 3871b65f0c82..5e4a0c8a5d3c 100644 --- a/arch/m32r/kernel/entry.S +++ b/arch/m32r/kernel/entry.S | |||
@@ -20,7 +20,7 @@ | |||
20 | * Stack layout in 'ret_from_system_call': | 20 | * Stack layout in 'ret_from_system_call': |
21 | * ptrace needs to have all regs on the stack. | 21 | * ptrace needs to have all regs on the stack. |
22 | * if the order here is changed, it needs to be | 22 | * if the order here is changed, it needs to be |
23 | * updated in fork.c:copy_process, signal.c:do_signal, | 23 | * updated in fork.c:copy_thread, signal.c:do_signal, |
24 | * ptrace.c and ptrace.h | 24 | * ptrace.c and ptrace.h |
25 | * | 25 | * |
26 | * M32Rx/M32R2 M32R | 26 | * M32Rx/M32R2 M32R |
@@ -41,18 +41,17 @@ | |||
41 | * @(0x38,sp) - syscall_nr ditto | 41 | * @(0x38,sp) - syscall_nr ditto |
42 | * @(0x3c,sp) - acc0h @(0x3c,sp) - acch | 42 | * @(0x3c,sp) - acc0h @(0x3c,sp) - acch |
43 | * @(0x40,sp) - acc0l @(0x40,sp) - accl | 43 | * @(0x40,sp) - acc0l @(0x40,sp) - accl |
44 | * @(0x44,sp) - acc1h @(0x44,sp) - psw | 44 | * @(0x44,sp) - acc1h @(0x44,sp) - dummy_acc1h |
45 | * @(0x48,sp) - acc1l @(0x48,sp) - bpc | 45 | * @(0x48,sp) - acc1l @(0x48,sp) - dummy_acc1l |
46 | * @(0x4c,sp) - psw @(0x4c,sp) - bbpsw | 46 | * @(0x4c,sp) - psw ditto |
47 | * @(0x50,sp) - bpc @(0x50,sp) - bbpc | 47 | * @(0x50,sp) - bpc ditto |
48 | * @(0x54,sp) - bbpsw @(0x54,sp) - spu (cr3) | 48 | * @(0x54,sp) - bbpsw ditto |
49 | * @(0x58,sp) - bbpc @(0x58,sp) - fp (r13) | 49 | * @(0x58,sp) - bbpc ditto |
50 | * @(0x5c,sp) - spu (cr3) @(0x5c,sp) - lr (r14) | 50 | * @(0x5c,sp) - spu (cr3) ditto |
51 | * @(0x60,sp) - fp (r13) @(0x60,sp) - spi (cr12) | 51 | * @(0x60,sp) - fp (r13) ditto |
52 | * @(0x64,sp) - lr (r14) @(0x64,sp) - orig_r0 | 52 | * @(0x64,sp) - lr (r14) ditto |
53 | * @(0x68,sp) - spi (cr2) | 53 | * @(0x68,sp) - spi (cr2) ditto |
54 | * @(0x6c,sp) - orig_r0 | 54 | * @(0x6c,sp) - orig_r0 ditto |
55 | * | ||
56 | */ | 55 | */ |
57 | 56 | ||
58 | #include <linux/config.h> | 57 | #include <linux/config.h> |
@@ -102,6 +101,12 @@ | |||
102 | #define ACC0L(reg) @(0x40,reg) | 101 | #define ACC0L(reg) @(0x40,reg) |
103 | #define ACC1H(reg) @(0x44,reg) | 102 | #define ACC1H(reg) @(0x44,reg) |
104 | #define ACC1L(reg) @(0x48,reg) | 103 | #define ACC1L(reg) @(0x48,reg) |
104 | #elif defined(CONFIG_ISA_M32R2) || defined(CONFIG_ISA_M32R) | ||
105 | #define ACCH(reg) @(0x3C,reg) | ||
106 | #define ACCL(reg) @(0x40,reg) | ||
107 | #else | ||
108 | #error unknown isa configuration | ||
109 | #endif | ||
105 | #define PSW(reg) @(0x4C,reg) | 110 | #define PSW(reg) @(0x4C,reg) |
106 | #define BPC(reg) @(0x50,reg) | 111 | #define BPC(reg) @(0x50,reg) |
107 | #define BBPSW(reg) @(0x54,reg) | 112 | #define BBPSW(reg) @(0x54,reg) |
@@ -111,21 +116,6 @@ | |||
111 | #define LR(reg) @(0x64,reg) | 116 | #define LR(reg) @(0x64,reg) |
112 | #define SP(reg) @(0x68,reg) | 117 | #define SP(reg) @(0x68,reg) |
113 | #define ORIG_R0(reg) @(0x6C,reg) | 118 | #define ORIG_R0(reg) @(0x6C,reg) |
114 | #elif defined(CONFIG_ISA_M32R2) || defined(CONFIG_ISA_M32R) | ||
115 | #define ACCH(reg) @(0x3C,reg) | ||
116 | #define ACCL(reg) @(0x40,reg) | ||
117 | #define PSW(reg) @(0x44,reg) | ||
118 | #define BPC(reg) @(0x48,reg) | ||
119 | #define BBPSW(reg) @(0x4C,reg) | ||
120 | #define BBPC(reg) @(0x50,reg) | ||
121 | #define SPU(reg) @(0x54,reg) | ||
122 | #define FP(reg) @(0x58,reg) /* FP = R13 */ | ||
123 | #define LR(reg) @(0x5C,reg) | ||
124 | #define SP(reg) @(0x60,reg) | ||
125 | #define ORIG_R0(reg) @(0x64,reg) | ||
126 | #else | ||
127 | #error unknown isa configuration | ||
128 | #endif | ||
129 | 119 | ||
130 | CF_MASK = 0x00000001 | 120 | CF_MASK = 0x00000001 |
131 | TF_MASK = 0x00000100 | 121 | TF_MASK = 0x00000100 |
@@ -231,7 +221,7 @@ restore_all: | |||
231 | RESTORE_ALL | 221 | RESTORE_ALL |
232 | 222 | ||
233 | # perform work that needs to be done immediately before resumption | 223 | # perform work that needs to be done immediately before resumption |
234 | # r9 : frags | 224 | # r9 : flags |
235 | ALIGN | 225 | ALIGN |
236 | work_pending: | 226 | work_pending: |
237 | and3 r4, r9, #_TIF_NEED_RESCHED | 227 | and3 r4, r9, #_TIF_NEED_RESCHED |
@@ -1015,4 +1005,3 @@ ENTRY(sys_call_table) | |||
1015 | .long sys_waitid | 1005 | .long sys_waitid |
1016 | 1006 | ||
1017 | syscall_table_size=(.-sys_call_table) | 1007 | syscall_table_size=(.-sys_call_table) |
1018 | |||
diff --git a/arch/m32r/kernel/signal.c b/arch/m32r/kernel/signal.c index cb33097fefc4..6498ee70bb73 100644 --- a/arch/m32r/kernel/signal.c +++ b/arch/m32r/kernel/signal.c | |||
@@ -118,6 +118,8 @@ restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc, | |||
118 | #elif defined(CONFIG_ISA_M32R2) || defined(CONFIG_ISA_M32R) | 118 | #elif defined(CONFIG_ISA_M32R2) || defined(CONFIG_ISA_M32R) |
119 | COPY(acch); | 119 | COPY(acch); |
120 | COPY(accl); | 120 | COPY(accl); |
121 | COPY(dummy_acc1h); | ||
122 | COPY(dummy_acc1l); | ||
121 | #else | 123 | #else |
122 | #error unknown isa configuration | 124 | #error unknown isa configuration |
123 | #endif | 125 | #endif |
@@ -203,6 +205,8 @@ setup_sigcontext(struct sigcontext __user *sc, struct pt_regs *regs, | |||
203 | #elif defined(CONFIG_ISA_M32R2) || defined(CONFIG_ISA_M32R) | 205 | #elif defined(CONFIG_ISA_M32R2) || defined(CONFIG_ISA_M32R) |
204 | COPY(acch); | 206 | COPY(acch); |
205 | COPY(accl); | 207 | COPY(accl); |
208 | COPY(dummy_acc1h); | ||
209 | COPY(dummy_acc1l); | ||
206 | #else | 210 | #else |
207 | #error unknown isa configuration | 211 | #error unknown isa configuration |
208 | #endif | 212 | #endif |