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authorRob Herring <rob.herring@calxeda.com>2012-11-20 22:21:40 -0500
committerRob Herring <rob.herring@calxeda.com>2013-01-12 11:47:31 -0500
commit81243e444c6e9d1625073e4a3d3bc244c8a545f0 (patch)
tree533a545705d110cfa990e0ffcbc5c4c0c2abec86 /arch
parent1d5cc604f42ff1acdec0407247b2f720135ba0c2 (diff)
irqchip: Move ARM GIC to drivers/irqchip
Now that we have drivers/irqchip, move GIC irqchip to drivers/irqchip. This is necessary to share the GIC with arm and arm64. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/common/Kconfig8
-rw-r--r--arch/arm/common/Makefile1
-rw-r--r--arch/arm/common/gic.c817
3 files changed, 0 insertions, 826 deletions
diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig
index 45ceeb0e93e0..7bf52b2b7d33 100644
--- a/arch/arm/common/Kconfig
+++ b/arch/arm/common/Kconfig
@@ -1,11 +1,3 @@
1config ARM_GIC
2 bool
3 select IRQ_DOMAIN
4 select MULTI_IRQ_HANDLER
5
6config GIC_NON_BANKED
7 bool
8
9config ARM_VIC 1config ARM_VIC
10 bool 2 bool
11 select IRQ_DOMAIN 3 select IRQ_DOMAIN
diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
index e8a4e58f1b82..4104b821f860 100644
--- a/arch/arm/common/Makefile
+++ b/arch/arm/common/Makefile
@@ -2,7 +2,6 @@
2# Makefile for the linux kernel. 2# Makefile for the linux kernel.
3# 3#
4 4
5obj-$(CONFIG_ARM_GIC) += gic.o
6obj-$(CONFIG_ARM_VIC) += vic.o 5obj-$(CONFIG_ARM_VIC) += vic.o
7obj-$(CONFIG_ICST) += icst.o 6obj-$(CONFIG_ICST) += icst.o
8obj-$(CONFIG_SA1111) += sa1111.o 7obj-$(CONFIG_SA1111) += sa1111.o
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
deleted file mode 100644
index 90eebfeae039..000000000000
--- a/arch/arm/common/gic.c
+++ /dev/null
@@ -1,817 +0,0 @@
1/*
2 * linux/arch/arm/common/gic.c
3 *
4 * Copyright (C) 2002 ARM Limited, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Interrupt architecture for the GIC:
11 *
12 * o There is one Interrupt Distributor, which receives interrupts
13 * from system devices and sends them to the Interrupt Controllers.
14 *
15 * o There is one CPU Interface per CPU, which sends interrupts sent
16 * by the Distributor, and interrupts generated locally, to the
17 * associated CPU. The base address of the CPU interface is usually
18 * aliased so that the same address points to different chips depending
19 * on the CPU it is accessed from.
20 *
21 * Note that IRQs 0-31 are special - they are local to each CPU.
22 * As such, the enable set/clear, pending set/clear and active bit
23 * registers are banked per-cpu for these sources.
24 */
25#include <linux/init.h>
26#include <linux/kernel.h>
27#include <linux/err.h>
28#include <linux/module.h>
29#include <linux/list.h>
30#include <linux/smp.h>
31#include <linux/cpu_pm.h>
32#include <linux/cpumask.h>
33#include <linux/io.h>
34#include <linux/of.h>
35#include <linux/of_address.h>
36#include <linux/of_irq.h>
37#include <linux/irqdomain.h>
38#include <linux/interrupt.h>
39#include <linux/percpu.h>
40#include <linux/slab.h>
41
42#include <asm/irq.h>
43#include <asm/exception.h>
44#include <asm/smp_plat.h>
45#include <asm/mach/irq.h>
46#include <asm/hardware/gic.h>
47
48union gic_base {
49 void __iomem *common_base;
50 void __percpu __iomem **percpu_base;
51};
52
53struct gic_chip_data {
54 union gic_base dist_base;
55 union gic_base cpu_base;
56#ifdef CONFIG_CPU_PM
57 u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
58 u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
59 u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
60 u32 __percpu *saved_ppi_enable;
61 u32 __percpu *saved_ppi_conf;
62#endif
63 struct irq_domain *domain;
64 unsigned int gic_irqs;
65#ifdef CONFIG_GIC_NON_BANKED
66 void __iomem *(*get_base)(union gic_base *);
67#endif
68};
69
70static DEFINE_RAW_SPINLOCK(irq_controller_lock);
71
72/*
73 * The GIC mapping of CPU interfaces does not necessarily match
74 * the logical CPU numbering. Let's use a mapping as returned
75 * by the GIC itself.
76 */
77#define NR_GIC_CPU_IF 8
78static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
79
80/*
81 * Supported arch specific GIC irq extension.
82 * Default make them NULL.
83 */
84struct irq_chip gic_arch_extn = {
85 .irq_eoi = NULL,
86 .irq_mask = NULL,
87 .irq_unmask = NULL,
88 .irq_retrigger = NULL,
89 .irq_set_type = NULL,
90 .irq_set_wake = NULL,
91};
92
93#ifndef MAX_GIC_NR
94#define MAX_GIC_NR 1
95#endif
96
97static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly;
98
99#ifdef CONFIG_GIC_NON_BANKED
100static void __iomem *gic_get_percpu_base(union gic_base *base)
101{
102 return *__this_cpu_ptr(base->percpu_base);
103}
104
105static void __iomem *gic_get_common_base(union gic_base *base)
106{
107 return base->common_base;
108}
109
110static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data)
111{
112 return data->get_base(&data->dist_base);
113}
114
115static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data)
116{
117 return data->get_base(&data->cpu_base);
118}
119
120static inline void gic_set_base_accessor(struct gic_chip_data *data,
121 void __iomem *(*f)(union gic_base *))
122{
123 data->get_base = f;
124}
125#else
126#define gic_data_dist_base(d) ((d)->dist_base.common_base)
127#define gic_data_cpu_base(d) ((d)->cpu_base.common_base)
128#define gic_set_base_accessor(d,f)
129#endif
130
131static inline void __iomem *gic_dist_base(struct irq_data *d)
132{
133 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
134 return gic_data_dist_base(gic_data);
135}
136
137static inline void __iomem *gic_cpu_base(struct irq_data *d)
138{
139 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
140 return gic_data_cpu_base(gic_data);
141}
142
143static inline unsigned int gic_irq(struct irq_data *d)
144{
145 return d->hwirq;
146}
147
148/*
149 * Routines to acknowledge, disable and enable interrupts
150 */
151static void gic_mask_irq(struct irq_data *d)
152{
153 u32 mask = 1 << (gic_irq(d) % 32);
154
155 raw_spin_lock(&irq_controller_lock);
156 writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4);
157 if (gic_arch_extn.irq_mask)
158 gic_arch_extn.irq_mask(d);
159 raw_spin_unlock(&irq_controller_lock);
160}
161
162static void gic_unmask_irq(struct irq_data *d)
163{
164 u32 mask = 1 << (gic_irq(d) % 32);
165
166 raw_spin_lock(&irq_controller_lock);
167 if (gic_arch_extn.irq_unmask)
168 gic_arch_extn.irq_unmask(d);
169 writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4);
170 raw_spin_unlock(&irq_controller_lock);
171}
172
173static void gic_eoi_irq(struct irq_data *d)
174{
175 if (gic_arch_extn.irq_eoi) {
176 raw_spin_lock(&irq_controller_lock);
177 gic_arch_extn.irq_eoi(d);
178 raw_spin_unlock(&irq_controller_lock);
179 }
180
181 writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
182}
183
184static int gic_set_type(struct irq_data *d, unsigned int type)
185{
186 void __iomem *base = gic_dist_base(d);
187 unsigned int gicirq = gic_irq(d);
188 u32 enablemask = 1 << (gicirq % 32);
189 u32 enableoff = (gicirq / 32) * 4;
190 u32 confmask = 0x2 << ((gicirq % 16) * 2);
191 u32 confoff = (gicirq / 16) * 4;
192 bool enabled = false;
193 u32 val;
194
195 /* Interrupt configuration for SGIs can't be changed */
196 if (gicirq < 16)
197 return -EINVAL;
198
199 if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
200 return -EINVAL;
201
202 raw_spin_lock(&irq_controller_lock);
203
204 if (gic_arch_extn.irq_set_type)
205 gic_arch_extn.irq_set_type(d, type);
206
207 val = readl_relaxed(base + GIC_DIST_CONFIG + confoff);
208 if (type == IRQ_TYPE_LEVEL_HIGH)
209 val &= ~confmask;
210 else if (type == IRQ_TYPE_EDGE_RISING)
211 val |= confmask;
212
213 /*
214 * As recommended by the spec, disable the interrupt before changing
215 * the configuration
216 */
217 if (readl_relaxed(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) {
218 writel_relaxed(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff);
219 enabled = true;
220 }
221
222 writel_relaxed(val, base + GIC_DIST_CONFIG + confoff);
223
224 if (enabled)
225 writel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff);
226
227 raw_spin_unlock(&irq_controller_lock);
228
229 return 0;
230}
231
232static int gic_retrigger(struct irq_data *d)
233{
234 if (gic_arch_extn.irq_retrigger)
235 return gic_arch_extn.irq_retrigger(d);
236
237 return -ENXIO;
238}
239
240#ifdef CONFIG_SMP
241static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
242 bool force)
243{
244 void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3);
245 unsigned int shift = (gic_irq(d) % 4) * 8;
246 unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask);
247 u32 val, mask, bit;
248
249 if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)
250 return -EINVAL;
251
252 mask = 0xff << shift;
253 bit = gic_cpu_map[cpu] << shift;
254
255 raw_spin_lock(&irq_controller_lock);
256 val = readl_relaxed(reg) & ~mask;
257 writel_relaxed(val | bit, reg);
258 raw_spin_unlock(&irq_controller_lock);
259
260 return IRQ_SET_MASK_OK;
261}
262#endif
263
264#ifdef CONFIG_PM
265static int gic_set_wake(struct irq_data *d, unsigned int on)
266{
267 int ret = -ENXIO;
268
269 if (gic_arch_extn.irq_set_wake)
270 ret = gic_arch_extn.irq_set_wake(d, on);
271
272 return ret;
273}
274
275#else
276#define gic_set_wake NULL
277#endif
278
279static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
280{
281 u32 irqstat, irqnr;
282 struct gic_chip_data *gic = &gic_data[0];
283 void __iomem *cpu_base = gic_data_cpu_base(gic);
284
285 do {
286 irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
287 irqnr = irqstat & ~0x1c00;
288
289 if (likely(irqnr > 15 && irqnr < 1021)) {
290 irqnr = irq_find_mapping(gic->domain, irqnr);
291 handle_IRQ(irqnr, regs);
292 continue;
293 }
294 if (irqnr < 16) {
295 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
296#ifdef CONFIG_SMP
297 handle_IPI(irqnr, regs);
298#endif
299 continue;
300 }
301 break;
302 } while (1);
303}
304
305static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
306{
307 struct gic_chip_data *chip_data = irq_get_handler_data(irq);
308 struct irq_chip *chip = irq_get_chip(irq);
309 unsigned int cascade_irq, gic_irq;
310 unsigned long status;
311
312 chained_irq_enter(chip, desc);
313
314 raw_spin_lock(&irq_controller_lock);
315 status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK);
316 raw_spin_unlock(&irq_controller_lock);
317
318 gic_irq = (status & 0x3ff);
319 if (gic_irq == 1023)
320 goto out;
321
322 cascade_irq = irq_find_mapping(chip_data->domain, gic_irq);
323 if (unlikely(gic_irq < 32 || gic_irq > 1020))
324 do_bad_IRQ(cascade_irq, desc);
325 else
326 generic_handle_irq(cascade_irq);
327
328 out:
329 chained_irq_exit(chip, desc);
330}
331
332static struct irq_chip gic_chip = {
333 .name = "GIC",
334 .irq_mask = gic_mask_irq,
335 .irq_unmask = gic_unmask_irq,
336 .irq_eoi = gic_eoi_irq,
337 .irq_set_type = gic_set_type,
338 .irq_retrigger = gic_retrigger,
339#ifdef CONFIG_SMP
340 .irq_set_affinity = gic_set_affinity,
341#endif
342 .irq_set_wake = gic_set_wake,
343};
344
345void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
346{
347 if (gic_nr >= MAX_GIC_NR)
348 BUG();
349 if (irq_set_handler_data(irq, &gic_data[gic_nr]) != 0)
350 BUG();
351 irq_set_chained_handler(irq, gic_handle_cascade_irq);
352}
353
354static void __init gic_dist_init(struct gic_chip_data *gic)
355{
356 unsigned int i;
357 u32 cpumask;
358 unsigned int gic_irqs = gic->gic_irqs;
359 void __iomem *base = gic_data_dist_base(gic);
360
361 writel_relaxed(0, base + GIC_DIST_CTRL);
362
363 /*
364 * Set all global interrupts to be level triggered, active low.
365 */
366 for (i = 32; i < gic_irqs; i += 16)
367 writel_relaxed(0, base + GIC_DIST_CONFIG + i * 4 / 16);
368
369 /*
370 * Set all global interrupts to this CPU only.
371 */
372 cpumask = readl_relaxed(base + GIC_DIST_TARGET + 0);
373 for (i = 32; i < gic_irqs; i += 4)
374 writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
375
376 /*
377 * Set priority on all global interrupts.
378 */
379 for (i = 32; i < gic_irqs; i += 4)
380 writel_relaxed(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);
381
382 /*
383 * Disable all interrupts. Leave the PPI and SGIs alone
384 * as these enables are banked registers.
385 */
386 for (i = 32; i < gic_irqs; i += 32)
387 writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
388
389 writel_relaxed(1, base + GIC_DIST_CTRL);
390}
391
392static void __cpuinit gic_cpu_init(struct gic_chip_data *gic)
393{
394 void __iomem *dist_base = gic_data_dist_base(gic);
395 void __iomem *base = gic_data_cpu_base(gic);
396 unsigned int cpu_mask, cpu = smp_processor_id();
397 int i;
398
399 /*
400 * Get what the GIC says our CPU mask is.
401 */
402 BUG_ON(cpu >= NR_GIC_CPU_IF);
403 cpu_mask = readl_relaxed(dist_base + GIC_DIST_TARGET + 0);
404 gic_cpu_map[cpu] = cpu_mask;
405
406 /*
407 * Clear our mask from the other map entries in case they're
408 * still undefined.
409 */
410 for (i = 0; i < NR_GIC_CPU_IF; i++)
411 if (i != cpu)
412 gic_cpu_map[i] &= ~cpu_mask;
413
414 /*
415 * Deal with the banked PPI and SGI interrupts - disable all
416 * PPI interrupts, ensure all SGI interrupts are enabled.
417 */
418 writel_relaxed(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
419 writel_relaxed(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
420
421 /*
422 * Set priority on PPI and SGI interrupts
423 */
424 for (i = 0; i < 32; i += 4)
425 writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
426
427 writel_relaxed(0xf0, base + GIC_CPU_PRIMASK);
428 writel_relaxed(1, base + GIC_CPU_CTRL);
429}
430
431#ifdef CONFIG_CPU_PM
432/*
433 * Saves the GIC distributor registers during suspend or idle. Must be called
434 * with interrupts disabled but before powering down the GIC. After calling
435 * this function, no interrupts will be delivered by the GIC, and another
436 * platform-specific wakeup source must be enabled.
437 */
438static void gic_dist_save(unsigned int gic_nr)
439{
440 unsigned int gic_irqs;
441 void __iomem *dist_base;
442 int i;
443
444 if (gic_nr >= MAX_GIC_NR)
445 BUG();
446
447 gic_irqs = gic_data[gic_nr].gic_irqs;
448 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
449
450 if (!dist_base)
451 return;
452
453 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
454 gic_data[gic_nr].saved_spi_conf[i] =
455 readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
456
457 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
458 gic_data[gic_nr].saved_spi_target[i] =
459 readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
460
461 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
462 gic_data[gic_nr].saved_spi_enable[i] =
463 readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
464}
465
466/*
467 * Restores the GIC distributor registers during resume or when coming out of
468 * idle. Must be called before enabling interrupts. If a level interrupt
469 * that occured while the GIC was suspended is still present, it will be
470 * handled normally, but any edge interrupts that occured will not be seen by
471 * the GIC and need to be handled by the platform-specific wakeup source.
472 */
473static void gic_dist_restore(unsigned int gic_nr)
474{
475 unsigned int gic_irqs;
476 unsigned int i;
477 void __iomem *dist_base;
478
479 if (gic_nr >= MAX_GIC_NR)
480 BUG();
481
482 gic_irqs = gic_data[gic_nr].gic_irqs;
483 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
484
485 if (!dist_base)
486 return;
487
488 writel_relaxed(0, dist_base + GIC_DIST_CTRL);
489
490 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
491 writel_relaxed(gic_data[gic_nr].saved_spi_conf[i],
492 dist_base + GIC_DIST_CONFIG + i * 4);
493
494 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
495 writel_relaxed(0xa0a0a0a0,
496 dist_base + GIC_DIST_PRI + i * 4);
497
498 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
499 writel_relaxed(gic_data[gic_nr].saved_spi_target[i],
500 dist_base + GIC_DIST_TARGET + i * 4);
501
502 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
503 writel_relaxed(gic_data[gic_nr].saved_spi_enable[i],
504 dist_base + GIC_DIST_ENABLE_SET + i * 4);
505
506 writel_relaxed(1, dist_base + GIC_DIST_CTRL);
507}
508
509static void gic_cpu_save(unsigned int gic_nr)
510{
511 int i;
512 u32 *ptr;
513 void __iomem *dist_base;
514 void __iomem *cpu_base;
515
516 if (gic_nr >= MAX_GIC_NR)
517 BUG();
518
519 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
520 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
521
522 if (!dist_base || !cpu_base)
523 return;
524
525 ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_enable);
526 for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
527 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
528
529 ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_conf);
530 for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
531 ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
532
533}
534
535static void gic_cpu_restore(unsigned int gic_nr)
536{
537 int i;
538 u32 *ptr;
539 void __iomem *dist_base;
540 void __iomem *cpu_base;
541
542 if (gic_nr >= MAX_GIC_NR)
543 BUG();
544
545 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
546 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
547
548 if (!dist_base || !cpu_base)
549 return;
550
551 ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_enable);
552 for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
553 writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4);
554
555 ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_conf);
556 for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
557 writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4);
558
559 for (i = 0; i < DIV_ROUND_UP(32, 4); i++)
560 writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4);
561
562 writel_relaxed(0xf0, cpu_base + GIC_CPU_PRIMASK);
563 writel_relaxed(1, cpu_base + GIC_CPU_CTRL);
564}
565
566static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v)
567{
568 int i;
569
570 for (i = 0; i < MAX_GIC_NR; i++) {
571#ifdef CONFIG_GIC_NON_BANKED
572 /* Skip over unused GICs */
573 if (!gic_data[i].get_base)
574 continue;
575#endif
576 switch (cmd) {
577 case CPU_PM_ENTER:
578 gic_cpu_save(i);
579 break;
580 case CPU_PM_ENTER_FAILED:
581 case CPU_PM_EXIT:
582 gic_cpu_restore(i);
583 break;
584 case CPU_CLUSTER_PM_ENTER:
585 gic_dist_save(i);
586 break;
587 case CPU_CLUSTER_PM_ENTER_FAILED:
588 case CPU_CLUSTER_PM_EXIT:
589 gic_dist_restore(i);
590 break;
591 }
592 }
593
594 return NOTIFY_OK;
595}
596
597static struct notifier_block gic_notifier_block = {
598 .notifier_call = gic_notifier,
599};
600
601static void __init gic_pm_init(struct gic_chip_data *gic)
602{
603 gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
604 sizeof(u32));
605 BUG_ON(!gic->saved_ppi_enable);
606
607 gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4,
608 sizeof(u32));
609 BUG_ON(!gic->saved_ppi_conf);
610
611 if (gic == &gic_data[0])
612 cpu_pm_register_notifier(&gic_notifier_block);
613}
614#else
615static void __init gic_pm_init(struct gic_chip_data *gic)
616{
617}
618#endif
619
620#ifdef CONFIG_SMP
621void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
622{
623 int cpu;
624 unsigned long map = 0;
625
626 /* Convert our logical CPU mask into a physical one. */
627 for_each_cpu(cpu, mask)
628 map |= 1 << cpu_logical_map(cpu);
629
630 /*
631 * Ensure that stores to Normal memory are visible to the
632 * other CPUs before issuing the IPI.
633 */
634 dsb();
635
636 /* this always happens on GIC0 */
637 writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
638}
639#endif
640
641static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
642 irq_hw_number_t hw)
643{
644 if (hw < 32) {
645 irq_set_percpu_devid(irq);
646 irq_set_chip_and_handler(irq, &gic_chip,
647 handle_percpu_devid_irq);
648 set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);
649 } else {
650 irq_set_chip_and_handler(irq, &gic_chip,
651 handle_fasteoi_irq);
652 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
653 }
654 irq_set_chip_data(irq, d->host_data);
655 return 0;
656}
657
658static int gic_irq_domain_xlate(struct irq_domain *d,
659 struct device_node *controller,
660 const u32 *intspec, unsigned int intsize,
661 unsigned long *out_hwirq, unsigned int *out_type)
662{
663 if (d->of_node != controller)
664 return -EINVAL;
665 if (intsize < 3)
666 return -EINVAL;
667
668 /* Get the interrupt number and add 16 to skip over SGIs */
669 *out_hwirq = intspec[1] + 16;
670
671 /* For SPIs, we need to add 16 more to get the GIC irq ID number */
672 if (!intspec[0])
673 *out_hwirq += 16;
674
675 *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
676 return 0;
677}
678
679const struct irq_domain_ops gic_irq_domain_ops = {
680 .map = gic_irq_domain_map,
681 .xlate = gic_irq_domain_xlate,
682};
683
684void __init gic_init_bases(unsigned int gic_nr, int irq_start,
685 void __iomem *dist_base, void __iomem *cpu_base,
686 u32 percpu_offset, struct device_node *node)
687{
688 irq_hw_number_t hwirq_base;
689 struct gic_chip_data *gic;
690 int gic_irqs, irq_base, i;
691
692 BUG_ON(gic_nr >= MAX_GIC_NR);
693
694 gic = &gic_data[gic_nr];
695#ifdef CONFIG_GIC_NON_BANKED
696 if (percpu_offset) { /* Frankein-GIC without banked registers... */
697 unsigned int cpu;
698
699 gic->dist_base.percpu_base = alloc_percpu(void __iomem *);
700 gic->cpu_base.percpu_base = alloc_percpu(void __iomem *);
701 if (WARN_ON(!gic->dist_base.percpu_base ||
702 !gic->cpu_base.percpu_base)) {
703 free_percpu(gic->dist_base.percpu_base);
704 free_percpu(gic->cpu_base.percpu_base);
705 return;
706 }
707
708 for_each_possible_cpu(cpu) {
709 unsigned long offset = percpu_offset * cpu_logical_map(cpu);
710 *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = dist_base + offset;
711 *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = cpu_base + offset;
712 }
713
714 gic_set_base_accessor(gic, gic_get_percpu_base);
715 } else
716#endif
717 { /* Normal, sane GIC... */
718 WARN(percpu_offset,
719 "GIC_NON_BANKED not enabled, ignoring %08x offset!",
720 percpu_offset);
721 gic->dist_base.common_base = dist_base;
722 gic->cpu_base.common_base = cpu_base;
723 gic_set_base_accessor(gic, gic_get_common_base);
724 }
725
726 /*
727 * Initialize the CPU interface map to all CPUs.
728 * It will be refined as each CPU probes its ID.
729 */
730 for (i = 0; i < NR_GIC_CPU_IF; i++)
731 gic_cpu_map[i] = 0xff;
732
733 /*
734 * For primary GICs, skip over SGIs.
735 * For secondary GICs, skip over PPIs, too.
736 */
737 if (gic_nr == 0 && (irq_start & 31) > 0) {
738 hwirq_base = 16;
739 if (irq_start != -1)
740 irq_start = (irq_start & ~31) + 16;
741 } else {
742 hwirq_base = 32;
743 }
744
745 /*
746 * Find out how many interrupts are supported.
747 * The GIC only supports up to 1020 interrupt sources.
748 */
749 gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f;
750 gic_irqs = (gic_irqs + 1) * 32;
751 if (gic_irqs > 1020)
752 gic_irqs = 1020;
753 gic->gic_irqs = gic_irqs;
754
755 gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */
756 irq_base = irq_alloc_descs(irq_start, 16, gic_irqs, numa_node_id());
757 if (IS_ERR_VALUE(irq_base)) {
758 WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n",
759 irq_start);
760 irq_base = irq_start;
761 }
762 gic->domain = irq_domain_add_legacy(node, gic_irqs, irq_base,
763 hwirq_base, &gic_irq_domain_ops, gic);
764 if (WARN_ON(!gic->domain))
765 return;
766
767#ifdef CONFIG_SMP
768 set_smp_cross_call(gic_raise_softirq);
769#endif
770
771 set_handle_irq(gic_handle_irq);
772
773 gic_chip.flags |= gic_arch_extn.flags;
774 gic_dist_init(gic);
775 gic_cpu_init(gic);
776 gic_pm_init(gic);
777}
778
779void __cpuinit gic_secondary_init(unsigned int gic_nr)
780{
781 BUG_ON(gic_nr >= MAX_GIC_NR);
782
783 gic_cpu_init(&gic_data[gic_nr]);
784}
785
786#ifdef CONFIG_OF
787static int gic_cnt __initdata = 0;
788
789int __init gic_of_init(struct device_node *node, struct device_node *parent)
790{
791 void __iomem *cpu_base;
792 void __iomem *dist_base;
793 u32 percpu_offset;
794 int irq;
795
796 if (WARN_ON(!node))
797 return -ENODEV;
798
799 dist_base = of_iomap(node, 0);
800 WARN(!dist_base, "unable to map gic dist registers\n");
801
802 cpu_base = of_iomap(node, 1);
803 WARN(!cpu_base, "unable to map gic cpu registers\n");
804
805 if (of_property_read_u32(node, "cpu-offset", &percpu_offset))
806 percpu_offset = 0;
807
808 gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset, node);
809
810 if (parent) {
811 irq = irq_of_parse_and_map(node, 0);
812 gic_cascade_irq(gic_cnt, irq);
813 }
814 gic_cnt++;
815 return 0;
816}
817#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-17 21:17:05 -0500