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authorSAN People <andrew@sanpeople.com>2006-01-09 12:05:41 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2006-01-09 12:05:41 -0500
commit73a59c1c4af06c675a168d698d3ebfbb3270ddbe (patch)
treefa1708e19cf89a6bd13c8f7725a9cc67cc4ae6fd /arch
parent50365c57860cd931c2d806057e0987634797e9af (diff)
[ARM] 3240/2: AT91RM9200 support for 2.6 (Core)
Patch from SAN People Following changes were made to clock.c: 1) Replaced <asm/hardware/clock.h> with <linux/clk.h> 2) Removed old unused clk_enable & clk_disable. 3) Replaced clk_use/clk_unuse with clk_enable/clk_disable. Otherwise it's the same as the previous patch. Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/Kconfig11
-rw-r--r--arch/arm/Makefile1
-rw-r--r--arch/arm/boot/compressed/Makefile4
-rw-r--r--arch/arm/boot/compressed/head-at91rm9200.S57
-rw-r--r--arch/arm/mach-at91rm9200/Kconfig54
-rw-r--r--arch/arm/mach-at91rm9200/Makefile27
-rw-r--r--arch/arm/mach-at91rm9200/Makefile.boot9
-rw-r--r--arch/arm/mach-at91rm9200/clock.c620
-rw-r--r--arch/arm/mach-at91rm9200/common.c115
-rw-r--r--arch/arm/mach-at91rm9200/devices.c291
-rw-r--r--arch/arm/mach-at91rm9200/generic.h18
-rw-r--r--arch/arm/mach-at91rm9200/gpio.c302
-rw-r--r--arch/arm/mach-at91rm9200/irq.c170
-rw-r--r--arch/arm/mach-at91rm9200/time.c127
-rw-r--r--arch/arm/mm/Kconfig4
15 files changed, 1807 insertions, 3 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 70f388d168db..e149f152e70b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -210,6 +210,12 @@ config ARCH_AAEC2000
210 help 210 help
211 This enables support for systems based on the Agilent AAEC-2000 211 This enables support for systems based on the Agilent AAEC-2000
212 212
213config ARCH_AT91RM9200
214 bool "AT91RM9200"
215 help
216 Say Y here if you intend to run this kernel on an AT91RM9200-based
217 board.
218
213endchoice 219endchoice
214 220
215source "arch/arm/mach-clps711x/Kconfig" 221source "arch/arm/mach-clps711x/Kconfig"
@@ -248,6 +254,8 @@ source "arch/arm/mach-aaec2000/Kconfig"
248 254
249source "arch/arm/mach-realview/Kconfig" 255source "arch/arm/mach-realview/Kconfig"
250 256
257source "arch/arm/mach-at91rm9200/Kconfig"
258
251# Definitions to make life easier 259# Definitions to make life easier
252config ARCH_ACORN 260config ARCH_ACORN
253 bool 261 bool
@@ -413,7 +421,8 @@ config LEDS
413 ARCH_EBSA285 || ARCH_IMX || ARCH_INTEGRATOR || \ 421 ARCH_EBSA285 || ARCH_IMX || ARCH_INTEGRATOR || \
414 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \ 422 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
415 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \ 423 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
416 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE 424 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
425 ARCH_AT91RM9200
417 help 426 help
418 If you say Y here, the LEDs on your machine will be used 427 If you say Y here, the LEDs on your machine will be used
419 to provide useful information about your current system status. 428 to provide useful information about your current system status.
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 1c056d631153..1fa2a1011584 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -99,6 +99,7 @@ endif
99 machine-$(CONFIG_ARCH_H720X) := h720x 99 machine-$(CONFIG_ARCH_H720X) := h720x
100 machine-$(CONFIG_ARCH_AAEC2000) := aaec2000 100 machine-$(CONFIG_ARCH_AAEC2000) := aaec2000
101 machine-$(CONFIG_ARCH_REALVIEW) := realview 101 machine-$(CONFIG_ARCH_REALVIEW) := realview
102 machine-$(CONFIG_ARCH_AT91RM9200) := at91rm9200
102 103
103ifeq ($(CONFIG_ARCH_EBSA110),y) 104ifeq ($(CONFIG_ARCH_EBSA110),y)
104# This is what happens if you forget the IOCS16 line. 105# This is what happens if you forget the IOCS16 line.
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index 0009a80498cc..35ffe0f4ece7 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -46,6 +46,10 @@ ifeq ($(CONFIG_PXA_SHARPSL),y)
46OBJS += head-sharpsl.o 46OBJS += head-sharpsl.o
47endif 47endif
48 48
49ifeq ($(CONFIG_ARCH_AT91RM9200),y)
50OBJS += head-at91rm9200.o
51endif
52
49ifeq ($(CONFIG_DEBUG_ICEDCC),y) 53ifeq ($(CONFIG_DEBUG_ICEDCC),y)
50OBJS += ice-dcc.o 54OBJS += ice-dcc.o
51endif 55endif
diff --git a/arch/arm/boot/compressed/head-at91rm9200.S b/arch/arm/boot/compressed/head-at91rm9200.S
new file mode 100644
index 000000000000..2119ea62b547
--- /dev/null
+++ b/arch/arm/boot/compressed/head-at91rm9200.S
@@ -0,0 +1,57 @@
1/*
2 * linux/arch/arm/boot/compressed/head-at91rm9200.S
3 *
4 * Copyright (C) 2003 SAN People
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12#include <asm/mach-types.h>
13
14 .section ".start", "ax"
15
16 @ Atmel AT91RM9200-DK : 262
17 mov r3, #(MACH_TYPE_AT91RM9200DK & 0xff)
18 orr r3, r3, #(MACH_TYPE_AT91RM9200DK & 0xff00)
19 cmp r7, r3
20 beq 99f
21
22 @ Cogent CSB337 : 399
23 mov r3, #(MACH_TYPE_CSB337 & 0xff)
24 orr r3, r3, #(MACH_TYPE_CSB337 & 0xff00)
25 cmp r7, r3
26 beq 99f
27
28 @ Cogent CSB637 : 648
29 mov r3, #(MACH_TYPE_CSB637 & 0xff)
30 orr r3, r3, #(MACH_TYPE_CSB637 & 0xff00)
31 cmp r7, r3
32 beq 99f
33
34 @ Atmel AT91RM9200-EK : 705
35 mov r3, #(MACH_TYPE_AT91RM9200EK & 0xff)
36 orr r3, r3, #(MACH_TYPE_AT91RM9200EK & 0xff00)
37 cmp r7, r3
38 beq 99f
39
40 @ Conitec Carmeva : 769
41 mov r3, #(MACH_TYPE_CARMEVA & 0xff)
42 orr r3, r3, #(MACH_TYPE_CARMEVA & 0xff00)
43 cmp r7, r3
44 beq 99f
45
46 @ KwikByte KB920x : 612
47 mov r3, #(MACH_TYPE_KB9200 & 0xff)
48 orr r3, r3, #(MACH_TYPE_KB9200 & 0xff00)
49 cmp r7, r3
50 beq 99f
51
52 @ Unknown board, use the AT91RM9200DK board
53 @ mov r7, #MACH_TYPE_AT91RM9200
54 mov r7, #(MACH_TYPE_AT91RM9200DK & 0xff)
55 orr r7, r7, #(MACH_TYPE_AT91RM9200DK & 0xff00)
56
5799:
diff --git a/arch/arm/mach-at91rm9200/Kconfig b/arch/arm/mach-at91rm9200/Kconfig
new file mode 100644
index 000000000000..4b7218fc3eb1
--- /dev/null
+++ b/arch/arm/mach-at91rm9200/Kconfig
@@ -0,0 +1,54 @@
1if ARCH_AT91RM9200
2
3menu "AT91RM9200 Implementations"
4
5comment "AT91RM9200 Board Type"
6
7config ARCH_AT91RM9200DK
8 bool "Atmel AT91RM9200-DK Development board"
9 depends on ARCH_AT91RM9200
10 help
11 Select this if you are using Atmel's AT91RM9200-DK Development board
12
13config MACH_AT91RM9200EK
14 bool "Atmel AT91RM9200-EK Evaluation Kit"
15 depends on ARCH_AT91RM9200
16 help
17 Select this if you are using Atmel's AT91RM9200-EK Evaluation Kit
18
19config MACH_CSB337
20 bool "Cogent CSB337 board"
21 depends on ARCH_AT91RM9200
22 help
23 Select this if you are using Cogent's CSB337 board
24
25config MACH_CSB637
26 bool "Cogent CSB637 board"
27 depends on ARCH_AT91RM9200
28 help
29 Select this if you are using Cogent's CSB637 board
30
31config MACH_CARMEVA
32 bool "Conitec's ARM&EVA"
33 depends on ARCH_AT91RM9200
34 help
35 Select this if you are using Conitec's AT91RM9200-MCU-Module
36
37config MACH_KB9200
38 bool "KwikByte's KB920x"
39 depends on ARCH_AT91RM9200
40 help
41 Select this if you are using KwikByte's KB920x board
42
43
44comment "AT91RM9200 Feature Selections"
45
46config AT91_PROGRAMMABLE_CLOCKS
47 bool "Programmable Clocks"
48 help
49 Select this if you need to program one or more of the PCK0..PCK3
50 programmable clock outputs.
51
52endmenu
53
54endif
diff --git a/arch/arm/mach-at91rm9200/Makefile b/arch/arm/mach-at91rm9200/Makefile
new file mode 100644
index 000000000000..1f2805ca6e21
--- /dev/null
+++ b/arch/arm/mach-at91rm9200/Makefile
@@ -0,0 +1,27 @@
1#
2# Makefile for the linux kernel.
3#
4
5obj-y := clock.o irq.o time.o gpio.o common.o devices.o
6obj-m :=
7obj-n :=
8obj- :=
9
10# Board-specific support
11#obj-$(CONFIG_ARCH_AT91RM9200DK) += board-dk.o
12#obj-$(CONFIG_MACH_AT91RM9200EK) += board-ek.o
13#obj-$(CONFIG_MACH_CSB337) += board-csb337.o
14#obj-$(CONFIG_MACH_CSB637) += board-csb637.o
15#obj-$(CONFIG_MACH_CARMEVA) += board-carmeva.o
16#obj-$(CONFIG_MACH_KB9200) += board-kb9202.o
17
18# LEDs support
19#led-$(CONFIG_ARCH_AT91RM9200DK) += leds.o
20#led-$(CONFIG_MACH_AT91RM9200EK) += leds.o
21#led-$(CONFIG_MACH_CSB337) += leds.o
22#led-$(CONFIG_MACH_CSB637) += leds.o
23#led-$(CONFIG_MACH_KB9200) += leds.o
24obj-$(CONFIG_LEDS) += $(led-y)
25
26# VGA support
27#obj-$(CONFIG_FB_S1D13XXX) += ics1523.o
diff --git a/arch/arm/mach-at91rm9200/Makefile.boot b/arch/arm/mach-at91rm9200/Makefile.boot
new file mode 100644
index 000000000000..e667dcc7cd34
--- /dev/null
+++ b/arch/arm/mach-at91rm9200/Makefile.boot
@@ -0,0 +1,9 @@
1# Note: the following conditions must always be true:
2# ZRELADDR == virt_to_phys(TEXTADDR)
3# PARAMS_PHYS must be within 4MB of ZRELADDR
4# INITRD_PHYS must be in RAM
5
6 zreladdr-y := 0x20008000
7params_phys-y := 0x20000100
8initrd_phys-y := 0x20410000
9
diff --git a/arch/arm/mach-at91rm9200/clock.c b/arch/arm/mach-at91rm9200/clock.c
new file mode 100644
index 000000000000..ec8195a2a3cc
--- /dev/null
+++ b/arch/arm/mach-at91rm9200/clock.c
@@ -0,0 +1,620 @@
1/*
2 * linux/arch/arm/mach-at91rm9200/clock.c
3 *
4 * Copyright (C) 2005 David Brownell
5 * Copyright (C) 2005 Ivan Kokshaysky
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/fs.h>
17#include <linux/debugfs.h>
18#include <linux/seq_file.h>
19#include <linux/list.h>
20#include <linux/errno.h>
21#include <linux/err.h>
22#include <linux/spinlock.h>
23#include <linux/delay.h>
24#include <linux/clk.h>
25
26#include <asm/semaphore.h>
27#include <asm/io.h>
28#include <asm/mach-types.h>
29
30#include <asm/arch/hardware.h>
31#include <asm/arch/board.h> /* for master clock global */
32
33#include "generic.h"
34
35#undef DEBUG
36
37/*
38 * There's a lot more which can be done with clocks, including cpufreq
39 * integration, slow clock mode support (for system suspend), letting
40 * PLLB be used at other rates (on boards that don't need USB), etc.
41 */
42
43struct clk {
44 const char *name;
45 unsigned long rate_hz;
46 struct clk *parent;
47 u32 pmc_mask;
48 void (*mode)(struct clk *, int);
49 unsigned id:2; /* PCK0..3, or 32k/main/a/b */
50 unsigned primary:1;
51 unsigned pll:1;
52 unsigned programmable:1;
53 u16 users;
54};
55
56static spinlock_t clk_lock;
57static u32 at91_pllb_usb_init;
58
59/*
60 * Four primary clock sources: two crystal oscillators (32K, main), and
61 * two PLLs. PLLA usually runs the master clock; and PLLB must run at
62 * 48 MHz (unless no USB function clocks are needed). The main clock and
63 * both PLLs are turned off to run in "slow clock mode" (system suspend).
64 */
65static struct clk clk32k = {
66 .name = "clk32k",
67 .rate_hz = AT91_SLOW_CLOCK,
68 .users = 1, /* always on */
69 .id = 0,
70 .primary = 1,
71};
72static struct clk main_clk = {
73 .name = "main",
74 .pmc_mask = 1 << 0, /* in PMC_SR */
75 .users = 1,
76 .id = 1,
77 .primary = 1,
78};
79static struct clk plla = {
80 .name = "plla",
81 .parent = &main_clk,
82 .pmc_mask = 1 << 1, /* in PMC_SR */
83 .id = 2,
84 .primary = 1,
85 .pll = 1,
86};
87
88static void pllb_mode(struct clk *clk, int is_on)
89{
90 u32 value;
91
92 if (is_on) {
93 is_on = AT91_PMC_LOCKB;
94 value = at91_pllb_usb_init;
95 } else
96 value = 0;
97
98 at91_sys_write(AT91_CKGR_PLLBR, value);
99
100 do {
101 cpu_relax();
102 } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on);
103}
104
105static struct clk pllb = {
106 .name = "pllb",
107 .parent = &main_clk,
108 .pmc_mask = 1 << 2, /* in PMC_SR */
109 .mode = pllb_mode,
110 .id = 3,
111 .primary = 1,
112 .pll = 1,
113};
114
115static void pmc_sys_mode(struct clk *clk, int is_on)
116{
117 if (is_on)
118 at91_sys_write(AT91_PMC_SCER, clk->pmc_mask);
119 else
120 at91_sys_write(AT91_PMC_SCDR, clk->pmc_mask);
121}
122
123/* USB function clocks (PLLB must be 48 MHz) */
124static struct clk udpck = {
125 .name = "udpck",
126 .parent = &pllb,
127 .pmc_mask = AT91_PMC_UDP,
128 .mode = pmc_sys_mode,
129};
130static struct clk uhpck = {
131 .name = "uhpck",
132 .parent = &pllb,
133 .pmc_mask = AT91_PMC_UHP,
134 .mode = pmc_sys_mode,
135};
136
137#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
138/*
139 * The four programmable clocks can be parented by any primary clock.
140 * You must configure pin multiplexing to bring these signals out.
141 */
142static struct clk pck0 = {
143 .name = "pck0",
144 .pmc_mask = AT91_PMC_PCK0,
145 .mode = pmc_sys_mode,
146 .programmable = 1,
147 .id = 0,
148};
149static struct clk pck1 = {
150 .name = "pck1",
151 .pmc_mask = AT91_PMC_PCK1,
152 .mode = pmc_sys_mode,
153 .programmable = 1,
154 .id = 1,
155};
156static struct clk pck2 = {
157 .name = "pck2",
158 .pmc_mask = AT91_PMC_PCK2,
159 .mode = pmc_sys_mode,
160 .programmable = 1,
161 .id = 2,
162};
163static struct clk pck3 = {
164 .name = "pck3",
165 .pmc_mask = AT91_PMC_PCK3,
166 .mode = pmc_sys_mode,
167 .programmable = 1,
168 .id = 3,
169};
170#endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
171
172
173/*
174 * The master clock is divided from the CPU clock (by 1-4). It's used for
175 * memory, interfaces to on-chip peripherals, the AIC, and sometimes more
176 * (e.g baud rate generation). It's sourced from one of the primary clocks.
177 */
178static struct clk mck = {
179 .name = "mck",
180 .pmc_mask = 1 << 3, /* in PMC_SR */
181 .users = 1, /* (must be) always on */
182};
183
184static void pmc_periph_mode(struct clk *clk, int is_on)
185{
186 if (is_on)
187 at91_sys_write(AT91_PMC_PCER, clk->pmc_mask);
188 else
189 at91_sys_write(AT91_PMC_PCDR, clk->pmc_mask);
190}
191
192static struct clk udc_clk = {
193 .name = "udc_clk",
194 .parent = &mck,
195 .pmc_mask = 1 << AT91_ID_UDP,
196 .mode = pmc_periph_mode,
197};
198static struct clk ohci_clk = {
199 .name = "ohci_clk",
200 .parent = &mck,
201 .pmc_mask = 1 << AT91_ID_UHP,
202 .mode = pmc_periph_mode,
203};
204
205static struct clk *const clock_list[] = {
206 /* four primary clocks -- MUST BE FIRST! */
207 &clk32k,
208 &main_clk,
209 &plla,
210 &pllb,
211
212 /* PLLB children (USB) */
213 &udpck,
214 &uhpck,
215
216#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
217 /* programmable clocks */
218 &pck0,
219 &pck1,
220 &pck2,
221 &pck3,
222#endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
223
224 /* MCK and peripherals */
225 &mck,
226 // usart0..usart3
227 // mmc
228 &udc_clk,
229 // i2c
230 // spi
231 // ssc0..ssc2
232 // tc0..tc5
233 &ohci_clk,
234 // ether
235};
236
237
238/* clocks are all static for now; no refcounting necessary */
239struct clk *clk_get(struct device *dev, const char *id)
240{
241 int i;
242
243 for (i = 0; i < ARRAY_SIZE(clock_list); i++) {
244 if (strcmp(id, clock_list[i]->name) == 0)
245 return clock_list[i];
246 }
247
248 return ERR_PTR(-ENOENT);
249}
250EXPORT_SYMBOL(clk_get);
251
252void clk_put(struct clk *clk)
253{
254}
255EXPORT_SYMBOL(clk_put);
256
257static void __clk_enable(struct clk *clk)
258{
259 if (clk->parent)
260 __clk_enable(clk->parent);
261 if (clk->users++ == 0 && clk->mode)
262 clk->mode(clk, 1);
263}
264
265int clk_enable(struct clk *clk)
266{
267 unsigned long flags;
268
269 spin_lock_irqsave(&clk_lock, flags);
270 __clk_enable(clk);
271 spin_unlock_irqrestore(&clk_lock, flags);
272 return 0;
273}
274EXPORT_SYMBOL(clk_enable);
275
276static void __clk_disable(struct clk *clk)
277{
278 BUG_ON(clk->users == 0);
279 if (--clk->users == 0 && clk->mode)
280 clk->mode(clk, 0);
281 if (clk->parent)
282 __clk_disable(clk->parent);
283}
284
285void clk_disable(struct clk *clk)
286{
287 unsigned long flags;
288
289 spin_lock_irqsave(&clk_lock, flags);
290 __clk_disable(clk);
291 spin_unlock_irqrestore(&clk_lock, flags);
292}
293EXPORT_SYMBOL(clk_disable);
294
295unsigned long clk_get_rate(struct clk *clk)
296{
297 unsigned long flags;
298 unsigned long rate;
299
300 spin_lock_irqsave(&clk_lock, flags);
301 for (;;) {
302 rate = clk->rate_hz;
303 if (rate || !clk->parent)
304 break;
305 clk = clk->parent;
306 }
307 spin_unlock_irqrestore(&clk_lock, flags);
308 return rate;
309}
310EXPORT_SYMBOL(clk_get_rate);
311
312/*------------------------------------------------------------------------*/
313
314#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
315
316/*
317 * For now, only the programmable clocks support reparenting (MCK could
318 * do this too, with care) or rate changing (the PLLs could do this too,
319 * ditto MCK but that's more for cpufreq). Drivers may reparent to get
320 * a better rate match; we don't.
321 */
322
323long clk_round_rate(struct clk *clk, unsigned long rate)
324{
325 unsigned long flags;
326 unsigned prescale;
327 unsigned long actual;
328
329 if (!clk->programmable)
330 return -EINVAL;
331 spin_lock_irqsave(&clk_lock, flags);
332
333 actual = clk->parent->rate_hz;
334 for (prescale = 0; prescale < 7; prescale++) {
335 if (actual && actual <= rate)
336 break;
337 actual >>= 1;
338 }
339
340 spin_unlock_irqrestore(&clk_lock, flags);
341 return (prescale < 7) ? actual : -ENOENT;
342}
343EXPORT_SYMBOL(clk_round_rate);
344
345int clk_set_rate(struct clk *clk, unsigned long rate)
346{
347 unsigned long flags;
348 unsigned prescale;
349 unsigned long actual;
350
351 if (!clk->programmable)
352 return -EINVAL;
353 if (clk->users)
354 return -EBUSY;
355 spin_lock_irqsave(&clk_lock, flags);
356
357 actual = clk->parent->rate_hz;
358 for (prescale = 0; prescale < 7; prescale++) {
359 if (actual && actual <= rate) {
360 u32 pckr;
361
362 pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
363 pckr &= 0x03;
364 pckr |= prescale << 2;
365 at91_sys_write(AT91_PMC_PCKR(clk->id), pckr);
366 clk->rate_hz = actual;
367 break;
368 }
369 actual >>= 1;
370 }
371
372 spin_unlock_irqrestore(&clk_lock, flags);
373 return (prescale < 7) ? actual : -ENOENT;
374}
375EXPORT_SYMBOL(clk_set_rate);
376
377struct clk *clk_get_parent(struct clk *clk)
378{
379 return clk->parent;
380}
381EXPORT_SYMBOL(clk_get_parent);
382
383int clk_set_parent(struct clk *clk, struct clk *parent)
384{
385 unsigned long flags;
386
387 if (clk->users)
388 return -EBUSY;
389 if (!parent->primary || !clk->programmable)
390 return -EINVAL;
391 spin_lock_irqsave(&clk_lock, flags);
392
393 clk->rate_hz = parent->rate_hz;
394 clk->parent = parent;
395 at91_sys_write(AT91_PMC_PCKR(clk->id), parent->id);
396
397 spin_unlock_irqrestore(&clk_lock, flags);
398 return 0;
399}
400EXPORT_SYMBOL(clk_set_parent);
401
402#endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
403
404/*------------------------------------------------------------------------*/
405
406#ifdef CONFIG_DEBUG_FS
407
408static int at91_clk_show(struct seq_file *s, void *unused)
409{
410 u32 scsr, pcsr, sr;
411 unsigned i;
412
413 seq_printf(s, "SCSR = %8x\n", scsr = at91_sys_read(AT91_PMC_SCSR));
414 seq_printf(s, "PCSR = %8x\n", pcsr = at91_sys_read(AT91_PMC_PCSR));
415
416 seq_printf(s, "MOR = %8x\n", at91_sys_read(AT91_CKGR_MOR));
417 seq_printf(s, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR));
418 seq_printf(s, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR));
419 seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR));
420
421 seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR));
422 for (i = 0; i < 4; i++)
423 seq_printf(s, "PCK%d = %8x\n", i, at91_sys_read(AT91_PMC_PCKR(i)));
424 seq_printf(s, "SR = %8x\n", sr = at91_sys_read(AT91_PMC_SR));
425
426 seq_printf(s, "\n");
427
428 for (i = 0; i < ARRAY_SIZE(clock_list); i++) {
429 char *state;
430 struct clk *clk = clock_list[i];
431
432 if (clk->mode == pmc_sys_mode)
433 state = (scsr & clk->pmc_mask) ? "on" : "off";
434 else if (clk->mode == pmc_periph_mode)
435 state = (pcsr & clk->pmc_mask) ? "on" : "off";
436 else if (clk->pmc_mask)
437 state = (sr & clk->pmc_mask) ? "on" : "off";
438 else if (clk == &clk32k || clk == &main_clk)
439 state = "on";
440 else
441 state = "";
442
443 seq_printf(s, "%-10s users=%d %-3s %9ld Hz %s\n",
444 clk->name, clk->users, state, clk_get_rate(clk),
445 clk->parent ? clk->parent->name : "");
446 }
447 return 0;
448}
449
450static int at91_clk_open(struct inode *inode, struct file *file)
451{
452 return single_open(file, at91_clk_show, NULL);
453}
454
455static struct file_operations at91_clk_operations = {
456 .open = at91_clk_open,
457 .read = seq_read,
458 .llseek = seq_lseek,
459 .release = single_release,
460};
461
462static int __init at91_clk_debugfs_init(void)
463{
464 /* /sys/kernel/debug/at91_clk */
465 (void) debugfs_create_file("at91_clk", S_IFREG | S_IRUGO, NULL, NULL, &at91_clk_operations);
466
467 return 0;
468}
469postcore_initcall(at91_clk_debugfs_init);
470
471#endif
472
473/*------------------------------------------------------------------------*/
474
475static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg)
476{
477 unsigned mul, div;
478
479 div = reg & 0xff;
480 mul = (reg >> 16) & 0x7ff;
481 if (div && mul) {
482 freq /= div;
483 freq *= mul + 1;
484 } else
485 freq = 0;
486 if (pll == &pllb && (reg & (1 << 28)))
487 freq /= 2;
488 return freq;
489}
490
491static unsigned __init at91_pll_calc(unsigned main_freq, unsigned out_freq)
492{
493 unsigned i, div = 0, mul = 0, diff = 1 << 30;
494 unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
495
496 /* PLL output max 240 MHz (or 180 MHz per errata) */
497 if (out_freq > 240000000)
498 goto fail;
499
500 for (i = 1; i < 256; i++) {
501 int diff1;
502 unsigned input, mul1;
503
504 /*
505 * PLL input between 1MHz and 32MHz per spec, but lower
506 * frequences seem necessary in some cases so allow 100K.
507 */
508 input = main_freq / i;
509 if (input < 100000)
510 continue;
511 if (input > 32000000)
512 continue;
513
514 mul1 = out_freq / input;
515 if (mul1 > 2048)
516 continue;
517 if (mul1 < 2)
518 goto fail;
519
520 diff1 = out_freq - input * mul1;
521 if (diff1 < 0)
522 diff1 = -diff1;
523 if (diff > diff1) {
524 diff = diff1;
525 div = i;
526 mul = mul1;
527 if (diff == 0)
528 break;
529 }
530 }
531 if (i == 256 && diff > (out_freq >> 5))
532 goto fail;
533 return ret | ((mul - 1) << 16) | div;
534fail:
535 return 0;
536}
537
538int __init at91_clock_init(unsigned long main_clock)
539{
540 unsigned tmp, freq, mckr;
541
542 spin_lock_init(&clk_lock);
543
544 /*
545 * When the bootloader initialized the main oscillator correctly,
546 * there's no problem using the cycle counter. But if it didn't,
547 * or when using oscillator bypass mode, we must be told the speed
548 * of the main clock.
549 */
550 if (!main_clock) {
551 do {
552 tmp = at91_sys_read(AT91_CKGR_MCFR);
553 } while (!(tmp & 0x10000));
554 main_clock = (tmp & 0xffff) * (AT91_SLOW_CLOCK / 16);
555 }
556 main_clk.rate_hz = main_clock;
557
558 /* report if PLLA is more than mildly overclocked */
559 plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
560 if (plla.rate_hz > 209000000)
561 pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
562
563 /*
564 * USB clock init: choose 48 MHz PLLB value, turn all clocks off,
565 * disable 48MHz clock during usb peripheral suspend.
566 *
567 * REVISIT: assumes MCK doesn't derive from PLLB!
568 */
569 at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | 0x10000000;
570 pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
571 at91_sys_write(AT91_PMC_PCDR, (1 << AT91_ID_UHP) | (1 << AT91_ID_UDP));
572 at91_sys_write(AT91_PMC_SCDR, AT91_PMC_UHP | AT91_PMC_UDP);
573 at91_sys_write(AT91_CKGR_PLLBR, 0);
574 at91_sys_write(AT91_PMC_SCER, AT91_PMC_MCKUDP);
575
576 /*
577 * MCK and CPU derive from one of those primary clocks.
578 * For now, assume this parentage won't change.
579 */
580 mckr = at91_sys_read(AT91_PMC_MCKR);
581 mck.parent = clock_list[mckr & AT91_PMC_CSS];
582 mck.parent->users++;
583 freq = mck.parent->rate_hz;
584 freq /= (1 << ((mckr >> 2) & 3)); /* prescale */
585 mck.rate_hz = freq / (1 + ((mckr >> 8) & 3)); /* mdiv */
586
587 printk("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
588 freq / 1000000, (unsigned) mck.rate_hz / 1000000,
589 (unsigned) main_clock / 1000000,
590 ((unsigned) main_clock % 1000000) / 1000);
591
592 /* FIXME get rid of master_clock global */
593 at91_master_clock = mck.rate_hz;
594
595#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
596 /* establish PCK0..PCK3 parentage */
597 for (tmp = 0; tmp < ARRAY_SIZE(clock_list); tmp++) {
598 struct clk *clk = clock_list[tmp], *parent;
599 u32 pckr;
600
601 if (!clk->programmable)
602 continue;
603
604 pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
605 parent = clock_list[pckr & 3];
606 clk->parent = parent;
607 clk->rate_hz = parent->rate_hz / (1 << ((pckr >> 2) & 3));
608 }
609#else
610 /* disable unused clocks */
611 at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK0 | AT91_PMC_PCK1 | AT91_PMC_PCK2 | AT91_PMC_PCK3);
612#endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
613
614 /* FIXME several unused clocks may still be active... provide
615 * a CONFIG option to turn off all unused clocks at some point
616 * before driver init starts.
617 */
618
619 return 0;
620}
diff --git a/arch/arm/mach-at91rm9200/common.c b/arch/arm/mach-at91rm9200/common.c
new file mode 100644
index 000000000000..3848fd2d5596
--- /dev/null
+++ b/arch/arm/mach-at91rm9200/common.c
@@ -0,0 +1,115 @@
1/*
2 * arch/arm/mach-at91rm9200/common.c
3 *
4 * Copyright (C) 2005 SAN People
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12
13#include <linux/config.h>
14#include <linux/module.h>
15
16#include <asm/mach/arch.h>
17#include <asm/mach/map.h>
18
19#include <asm/arch/hardware.h>
20
21static struct map_desc at91rm9200_io_desc[] __initdata = {
22 {
23 .virtual = AT91_VA_BASE_SYS,
24 .pfn = __phys_to_pfn(AT91_BASE_SYS),
25 .length = SZ_4K,
26 .type = MT_DEVICE,
27 }, {
28 .virtual = AT91_VA_BASE_SPI,
29 .pfn = __phys_to_pfn(AT91_BASE_SPI),
30 .length = SZ_16K,
31 .type = MT_DEVICE,
32 }, {
33 .virtual = AT91_VA_BASE_SSC2,
34 .pfn = __phys_to_pfn(AT91_BASE_SSC2),
35 .length = SZ_16K,
36 .type = MT_DEVICE,
37 }, {
38 .virtual = AT91_VA_BASE_SSC1,
39 .pfn = __phys_to_pfn(AT91_BASE_SSC1),
40 .length = SZ_16K,
41 .type = MT_DEVICE,
42 }, {
43 .virtual = AT91_VA_BASE_SSC0,
44 .pfn = __phys_to_pfn(AT91_BASE_SSC0),
45 .length = SZ_16K,
46 .type = MT_DEVICE,
47 }, {
48 .virtual = AT91_VA_BASE_US3,
49 .pfn = __phys_to_pfn(AT91_BASE_US3),
50 .length = SZ_16K,
51 .type = MT_DEVICE,
52 }, {
53 .virtual = AT91_VA_BASE_US2,
54 .pfn = __phys_to_pfn(AT91_BASE_US2),
55 .length = SZ_16K,
56 .type = MT_DEVICE,
57 }, {
58 .virtual = AT91_VA_BASE_US1,
59 .pfn = __phys_to_pfn(AT91_BASE_US1),
60 .length = SZ_16K,
61 .type = MT_DEVICE,
62 }, {
63 .virtual = AT91_VA_BASE_US0,
64 .pfn = __phys_to_pfn(AT91_BASE_US0),
65 .length = SZ_16K,
66 .type = MT_DEVICE,
67 }, {
68 .virtual = AT91_VA_BASE_EMAC,
69 .pfn = __phys_to_pfn(AT91_BASE_EMAC),
70 .length = SZ_16K,
71 .type = MT_DEVICE,
72 }, {
73 .virtual = AT91_VA_BASE_TWI,
74 .pfn = __phys_to_pfn(AT91_BASE_TWI),
75 .length = SZ_16K,
76 .type = MT_DEVICE,
77 }, {
78 .virtual = AT91_VA_BASE_MCI,
79 .pfn = __phys_to_pfn(AT91_BASE_MCI),
80 .length = SZ_16K,
81 .type = MT_DEVICE,
82 }, {
83 .virtual = AT91_VA_BASE_UDP,
84 .pfn = __phys_to_pfn(AT91_BASE_UDP),
85 .length = SZ_16K,
86 .type = MT_DEVICE,
87 }, {
88 .virtual = AT91_VA_BASE_TCB1,
89 .pfn = __phys_to_pfn(AT91_BASE_TCB1),
90 .length = SZ_16K,
91 .type = MT_DEVICE,
92 }, {
93 .virtual = AT91_VA_BASE_TCB0,
94 .pfn = __phys_to_pfn(AT91_BASE_TCB0),
95 .length = SZ_16K,
96 .type = MT_DEVICE,
97 },
98};
99
100void __init at91rm9200_map_io(void)
101{
102 iotable_init(at91rm9200_io_desc, ARRAY_SIZE(at91rm9200_io_desc));
103}
104
105
106unsigned long at91_master_clock;
107
108EXPORT_SYMBOL(at91_master_clock);
109
110
111int at91_serial_map[AT91_NR_UART];
112int at91_console_port;
113
114EXPORT_SYMBOL(at91_serial_map);
115EXPORT_SYMBOL(at91_console_port);
diff --git a/arch/arm/mach-at91rm9200/devices.c b/arch/arm/mach-at91rm9200/devices.c
new file mode 100644
index 000000000000..8df3e5245651
--- /dev/null
+++ b/arch/arm/mach-at91rm9200/devices.c
@@ -0,0 +1,291 @@
1/*
2 * arch/arm/mach-at91rm9200/devices.c
3 *
4 * Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org>
5 * Copyright (C) 2005 David Brownell
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 */
13#include <asm/mach/arch.h>
14#include <asm/mach/map.h>
15
16#include <linux/config.h>
17#include <linux/platform_device.h>
18
19#include <asm/arch/board.h>
20#include <asm/arch/pio.h>
21
22
23/* --------------------------------------------------------------------
24 * USB Host
25 * -------------------------------------------------------------------- */
26
27#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
28static u64 ohci_dmamask = 0xffffffffUL;
29static struct at91_usbh_data usbh_data;
30
31static struct resource at91rm9200_usbh_resource[] = {
32 [0] = {
33 .start = AT91_UHP_BASE,
34 .end = AT91_UHP_BASE + SZ_1M -1,
35 .flags = IORESOURCE_MEM,
36 },
37 [1] = {
38 .start = AT91_ID_UHP,
39 .end = AT91_ID_UHP,
40 .flags = IORESOURCE_IRQ,
41 },
42};
43
44static struct platform_device at91rm9200_usbh_device = {
45 .name = "at91rm9200-ohci",
46 .id = -1,
47 .dev = {
48 .dma_mask = &ohci_dmamask,
49 .coherent_dma_mask = 0xffffffff,
50 .platform_data = &usbh_data,
51 },
52 .resource = at91rm9200_usbh_resource,
53 .num_resources = ARRAY_SIZE(at91rm9200_usbh_resource),
54};
55
56void __init at91_add_device_usbh(struct at91_usbh_data *data)
57{
58 if (!data)
59 return;
60
61 usbh_data = *data;
62 platform_device_register(&at91rm9200_usbh_device);
63}
64#else
65void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
66#endif
67
68
69/* --------------------------------------------------------------------
70 * USB Device (Gadget)
71 * -------------------------------------------------------------------- */
72
73#ifdef CONFIG_USB_GADGET_AT91
74static struct at91_udc_data udc_data;
75
76static struct resource at91_udc_resources[] = {
77 {
78 .start = AT91_BASE_UDP,
79 .end = AT91_BASE_UDP + SZ_16K - 1,
80 .flags = IORESOURCE_MEM,
81 }
82};
83
84static struct platform_device at91rm9200_udc_device = {
85 .name = "at91_udc",
86 .id = -1,
87 .dev = {
88 .platform_data = &udc_data,
89 },
90 .resource = at91_udc_resources,
91 .num_resources = ARRAY_SIZE(at91_udc_resources),
92};
93
94void __init at91_add_device_udc(struct at91_udc_data *data)
95{
96 if (!data)
97 return;
98
99 if (data->vbus_pin) {
100 at91_set_gpio_input(data->vbus_pin, 0);
101 at91_set_deglitch(data->vbus_pin, 1);
102 }
103 if (data->pullup_pin)
104 at91_set_gpio_output(data->pullup_pin, 0);
105
106 udc_data = *data;
107 platform_device_register(&at91rm9200_udc_device);
108}
109#else
110void __init at91_add_device_udc(struct at91_udc_data *data) {}
111#endif
112
113
114/* --------------------------------------------------------------------
115 * Ethernet
116 * -------------------------------------------------------------------- */
117
118#if defined(CONFIG_ARM_AT91_ETHER) || defined(CONFIG_ARM_AT91_ETHER_MODULE)
119static u64 eth_dmamask = 0xffffffffUL;
120static struct at91_eth_data eth_data;
121
122static struct platform_device at91rm9200_eth_device = {
123 .name = "at91_ether",
124 .id = -1,
125 .dev = {
126 .dma_mask = &eth_dmamask,
127 .coherent_dma_mask = 0xffffffff,
128 .platform_data = &eth_data,
129 },
130 .num_resources = 0,
131};
132
133void __init at91_add_device_eth(struct at91_eth_data *data)
134{
135 if (!data)
136 return;
137
138 if (data->phy_irq_pin) {
139 at91_set_gpio_input(data->phy_irq_pin, 0);
140 at91_set_deglitch(data->phy_irq_pin, 1);
141 }
142
143 /* Pins used for MII and RMII */
144 at91_set_A_periph(AT91_PIN_PA16, 0); /* EMDIO */
145 at91_set_A_periph(AT91_PIN_PA15, 0); /* EMDC */
146 at91_set_A_periph(AT91_PIN_PA14, 0); /* ERXER */
147 at91_set_A_periph(AT91_PIN_PA13, 0); /* ERX1 */
148 at91_set_A_periph(AT91_PIN_PA12, 0); /* ERX0 */
149 at91_set_A_periph(AT91_PIN_PA11, 0); /* ECRS_ECRSDV */
150 at91_set_A_periph(AT91_PIN_PA10, 0); /* ETX1 */
151 at91_set_A_periph(AT91_PIN_PA9, 0); /* ETX0 */
152 at91_set_A_periph(AT91_PIN_PA8, 0); /* ETXEN */
153 at91_set_A_periph(AT91_PIN_PA7, 0); /* ETXCK_EREFCK */
154
155 if (!data->is_rmii) {
156 at91_set_B_periph(AT91_PIN_PB19, 0); /* ERXCK */
157 at91_set_B_periph(AT91_PIN_PB18, 0); /* ECOL */
158 at91_set_B_periph(AT91_PIN_PB17, 0); /* ERXDV */
159 at91_set_B_periph(AT91_PIN_PB16, 0); /* ERX3 */
160 at91_set_B_periph(AT91_PIN_PB15, 0); /* ERX2 */
161 at91_set_B_periph(AT91_PIN_PB14, 0); /* ETXER */
162 at91_set_B_periph(AT91_PIN_PB13, 0); /* ETX3 */
163 at91_set_B_periph(AT91_PIN_PB12, 0); /* ETX2 */
164 }
165
166 eth_data = *data;
167 platform_device_register(&at91rm9200_eth_device);
168}
169#else
170void __init at91_add_device_eth(struct at91_eth_data *data) {}
171#endif
172
173
174/* --------------------------------------------------------------------
175 * Compact Flash / PCMCIA
176 * -------------------------------------------------------------------- */
177
178#if defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE)
179static struct at91_cf_data cf_data;
180
181static struct platform_device at91rm9200_cf_device = {
182 .name = "at91_cf",
183 .id = -1,
184 .dev = {
185 .platform_data = &cf_data,
186 },
187 .num_resources = 0,
188};
189
190void __init at91_add_device_cf(struct at91_cf_data *data)
191{
192 if (!data)
193 return;
194
195 /* input/irq */
196 if (data->irq_pin) {
197 at91_set_gpio_input(data->irq_pin, 1);
198 at91_set_deglitch(data->irq_pin, 1);
199 }
200 at91_set_gpio_input(data->det_pin, 1);
201 at91_set_deglitch(data->det_pin, 1);
202
203 /* outputs, initially off */
204 if (data->vcc_pin)
205 at91_set_gpio_output(data->vcc_pin, 0);
206 at91_set_gpio_output(data->rst_pin, 0);
207
208 cf_data = *data;
209 platform_device_register(&at91rm9200_cf_device);
210}
211#else
212void __init at91_add_device_cf(struct at91_cf_data *data) {}
213#endif
214
215
216/* --------------------------------------------------------------------
217 * MMC / SD
218 * -------------------------------------------------------------------- */
219
220#if defined(CONFIG_MMC_AT91RM9200) || defined(CONFIG_MMC_AT91RM9200_MODULE)
221static u64 mmc_dmamask = 0xffffffffUL;
222static struct at91_mmc_data mmc_data;
223
224static struct resource at91_mmc_resources[] = {
225 {
226 .start = AT91_BASE_MCI,
227 .end = AT91_BASE_MCI + SZ_16K - 1,
228 .flags = IORESOURCE_MEM,
229 }
230};
231
232static struct platform_device at91rm9200_mmc_device = {
233 .name = "at91rm9200_mci",
234 .id = -1,
235 .dev = {
236 .dma_mask = &mmc_dmamask,
237 .coherent_dma_mask = 0xffffffff,
238 .platform_data = &mmc_data,
239 },
240 .resource = at91_mmc_resources,
241 .num_resources = ARRAY_SIZE(at91_mmc_resources),
242};
243
244void __init at91_add_device_mmc(struct at91_mmc_data *data)
245{
246 if (!data)
247 return;
248
249 /* input/irq */
250 if (data->det_pin) {
251 at91_set_gpio_input(data->det_pin, 1);
252 at91_set_deglitch(data->det_pin, 1);
253 }
254 if (data->wp_pin)
255 at91_set_gpio_input(data->wp_pin, 1);
256
257 /* CLK */
258 at91_set_A_periph(AT91_PIN_PA27, 0);
259
260 if (data->is_b) {
261 /* CMD */
262 at91_set_B_periph(AT91_PIN_PA8, 0);
263
264 /* DAT0, maybe DAT1..DAT3 */
265 at91_set_B_periph(AT91_PIN_PA9, 0);
266 if (data->wire4) {
267 at91_set_B_periph(AT91_PIN_PA10, 0);
268 at91_set_B_periph(AT91_PIN_PA11, 0);
269 at91_set_B_periph(AT91_PIN_PA12, 0);
270 }
271 } else {
272 /* CMD */
273 at91_set_A_periph(AT91_PIN_PA28, 0);
274
275 /* DAT0, maybe DAT1..DAT3 */
276 at91_set_A_periph(AT91_PIN_PA29, 0);
277 if (data->wire4) {
278 at91_set_B_periph(AT91_PIN_PB3, 0);
279 at91_set_B_periph(AT91_PIN_PB4, 0);
280 at91_set_B_periph(AT91_PIN_PB5, 0);
281 }
282 }
283
284 mmc_data = *data;
285 platform_device_register(&at91rm9200_mmc_device);
286}
287#else
288void __init at91_add_device_mmc(struct at91_mmc_data *data) {}
289#endif
290
291/* -------------------------------------------------------------------- */
diff --git a/arch/arm/mach-at91rm9200/generic.h b/arch/arm/mach-at91rm9200/generic.h
new file mode 100644
index 000000000000..9bd541eba0a0
--- /dev/null
+++ b/arch/arm/mach-at91rm9200/generic.h
@@ -0,0 +1,18 @@
1/*
2 * linux/arch/arm/mach-at91rm9200/generic.h
3 *
4 * Copyright (C) 2005 David Brownell
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11void at91_gpio_irq_setup(unsigned banks);
12
13struct sys_timer;
14extern struct sys_timer at91rm9200_timer;
15
16extern void __init at91rm9200_map_io(void);
17
18extern int __init at91_clock_init(unsigned long main_clock);
diff --git a/arch/arm/mach-at91rm9200/gpio.c b/arch/arm/mach-at91rm9200/gpio.c
new file mode 100644
index 000000000000..2fd2ef583e4d
--- /dev/null
+++ b/arch/arm/mach-at91rm9200/gpio.c
@@ -0,0 +1,302 @@
1/*
2 * linux/arch/arm/mach-at91rm9200/gpio.c
3 *
4 * Copyright (C) 2005 HP Labs
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#include <linux/errno.h>
13#include <linux/kernel.h>
14#include <linux/list.h>
15#include <linux/module.h>
16
17#include <asm/io.h>
18#include <asm/mach/irq.h>
19#include <asm/arch/hardware.h>
20#include <asm/arch/gpio.h>
21
22static const u32 pio_controller_offset[4] = {
23 AT91_PIOA,
24 AT91_PIOB,
25 AT91_PIOC,
26 AT91_PIOD,
27};
28
29static inline void __iomem *pin_to_controller(unsigned pin)
30{
31 void __iomem *sys_base = (void __iomem *) AT91_VA_BASE_SYS;
32
33 pin -= PIN_BASE;
34 pin /= 32;
35 if (likely(pin < BGA_GPIO_BANKS))
36 return sys_base + pio_controller_offset[pin];
37
38 return NULL;
39}
40
41static inline unsigned pin_to_mask(unsigned pin)
42{
43 pin -= PIN_BASE;
44 return 1 << (pin % 32);
45}
46
47
48/*--------------------------------------------------------------------------*/
49
50/* Not all hardware capabilities are exposed through these calls; they
51 * only encapsulate the most common features and modes. (So if you
52 * want to change signals in groups, do it directly.)
53 *
54 * Bootloaders will usually handle some of the pin multiplexing setup.
55 * The intent is certainly that by the time Linux is fully booted, all
56 * pins should have been fully initialized. These setup calls should
57 * only be used by board setup routines, or possibly in driver probe().
58 *
59 * For bootloaders doing all that setup, these calls could be inlined
60 * as NOPs so Linux won't duplicate any setup code
61 */
62
63
64/*
65 * mux the pin to the "A" internal peripheral role.
66 */
67int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup)
68{
69 void __iomem *pio = pin_to_controller(pin);
70 unsigned mask = pin_to_mask(pin);
71
72 if (!pio)
73 return -EINVAL;
74
75 __raw_writel(mask, pio + PIO_IDR);
76 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
77 __raw_writel(mask, pio + PIO_ASR);
78 __raw_writel(mask, pio + PIO_PDR);
79 return 0;
80}
81EXPORT_SYMBOL(at91_set_A_periph);
82
83
84/*
85 * mux the pin to the "B" internal peripheral role.
86 */
87int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup)
88{
89 void __iomem *pio = pin_to_controller(pin);
90 unsigned mask = pin_to_mask(pin);
91
92 if (!pio)
93 return -EINVAL;
94
95 __raw_writel(mask, pio + PIO_IDR);
96 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
97 __raw_writel(mask, pio + PIO_BSR);
98 __raw_writel(mask, pio + PIO_PDR);
99 return 0;
100}
101EXPORT_SYMBOL(at91_set_B_periph);
102
103
104/*
105 * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
106 * configure it for an input.
107 */
108int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup)
109{
110 void __iomem *pio = pin_to_controller(pin);
111 unsigned mask = pin_to_mask(pin);
112
113 if (!pio)
114 return -EINVAL;
115
116 __raw_writel(mask, pio + PIO_IDR);
117 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
118 __raw_writel(mask, pio + PIO_ODR);
119 __raw_writel(mask, pio + PIO_PER);
120 return 0;
121}
122EXPORT_SYMBOL(at91_set_gpio_input);
123
124
125/*
126 * mux the pin to the gpio controller (instead of "A" or "B" peripheral),
127 * and configure it for an output.
128 */
129int __init_or_module at91_set_gpio_output(unsigned pin, int value)
130{
131 void __iomem *pio = pin_to_controller(pin);
132 unsigned mask = pin_to_mask(pin);
133
134 if (!pio)
135 return -EINVAL;
136
137 __raw_writel(mask, pio + PIO_IDR);
138 __raw_writel(mask, pio + PIO_PUDR);
139 __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
140 __raw_writel(mask, pio + PIO_OER);
141 __raw_writel(mask, pio + PIO_PER);
142 return 0;
143}
144EXPORT_SYMBOL(at91_set_gpio_output);
145
146
147/*
148 * enable/disable the glitch filter; mostly used with IRQ handling.
149 */
150int __init_or_module at91_set_deglitch(unsigned pin, int is_on)
151{
152 void __iomem *pio = pin_to_controller(pin);
153 unsigned mask = pin_to_mask(pin);
154
155 if (!pio)
156 return -EINVAL;
157 __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
158 return 0;
159}
160EXPORT_SYMBOL(at91_set_deglitch);
161
162/*--------------------------------------------------------------------------*/
163
164
165/*
166 * assuming the pin is muxed as a gpio output, set its value.
167 */
168int at91_set_gpio_value(unsigned pin, int value)
169{
170 void __iomem *pio = pin_to_controller(pin);
171 unsigned mask = pin_to_mask(pin);
172
173 if (!pio)
174 return -EINVAL;
175 __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
176 return 0;
177}
178EXPORT_SYMBOL(at91_set_gpio_value);
179
180
181/*
182 * read the pin's value (works even if it's not muxed as a gpio).
183 */
184int at91_get_gpio_value(unsigned pin)
185{
186 void __iomem *pio = pin_to_controller(pin);
187 unsigned mask = pin_to_mask(pin);
188 u32 pdsr;
189
190 if (!pio)
191 return -EINVAL;
192 pdsr = __raw_readl(pio + PIO_PDSR);
193 return (pdsr & mask) != 0;
194}
195EXPORT_SYMBOL(at91_get_gpio_value);
196
197/*--------------------------------------------------------------------------*/
198
199
200/* Several AIC controller irqs are dispatched through this GPIO handler.
201 * To use any AT91_PIN_* as an externally triggered IRQ, first call
202 * at91_set_gpio_input() then maybe enable its glitch filter.
203 * Then just request_irq() with the pin ID; it works like any ARM IRQ
204 * handler, though it always triggers on rising and falling edges.
205 *
206 * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
207 * configuring them with at91_set_a_periph() or at91_set_b_periph().
208 * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
209 */
210
211static void gpio_irq_mask(unsigned pin)
212{
213 void __iomem *pio = pin_to_controller(pin);
214 unsigned mask = pin_to_mask(pin);
215
216 if (pio)
217 __raw_writel(mask, pio + PIO_IDR);
218}
219
220static void gpio_irq_unmask(unsigned pin)
221{
222 void __iomem *pio = pin_to_controller(pin);
223 unsigned mask = pin_to_mask(pin);
224
225 if (pio)
226 __raw_writel(mask, pio + PIO_IER);
227}
228
229static int gpio_irq_type(unsigned pin, unsigned type)
230{
231 return (type == IRQT_BOTHEDGE) ? 0 : -EINVAL;
232}
233
234static struct irqchip gpio_irqchip = {
235 .mask = gpio_irq_mask,
236 .unmask = gpio_irq_unmask,
237 .set_type = gpio_irq_type,
238};
239
240static void gpio_irq_handler(unsigned irq, struct irqdesc *desc, struct pt_regs *regs)
241{
242 unsigned pin;
243 struct irqdesc *gpio;
244 void __iomem *pio;
245 u32 isr;
246
247 pio = (void __force __iomem *) desc->chipdata;
248
249 /* temporarily mask (level sensitive) parent IRQ */
250 desc->chip->ack(irq);
251 for (;;) {
252 isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR);
253 if (!isr)
254 break;
255
256 pin = (unsigned) desc->data;
257 gpio = &irq_desc[pin];
258
259 while (isr) {
260 if (isr & 1)
261 gpio->handle(pin, gpio, regs);
262 pin++;
263 gpio++;
264 isr >>= 1;
265 }
266 }
267 desc->chip->unmask(irq);
268 /* now it may re-trigger */
269}
270
271/* call this from board-specific init_irq */
272void __init at91_gpio_irq_setup(unsigned banks)
273{
274 unsigned pioc, pin, id;
275
276 if (banks > 4)
277 banks = 4;
278 for (pioc = 0, pin = PIN_BASE, id = AT91_ID_PIOA;
279 pioc < banks;
280 pioc++, id++) {
281 void __iomem *controller;
282 unsigned i;
283
284 controller = (void __iomem *) AT91_VA_BASE_SYS + pio_controller_offset[pioc];
285 __raw_writel(~0, controller + PIO_IDR);
286
287 set_irq_data(id, (void *) pin);
288 set_irq_chipdata(id, (void __force *) controller);
289
290 for (i = 0; i < 32; i++, pin++) {
291 set_irq_chip(pin, &gpio_irqchip);
292 set_irq_handler(pin, do_simple_IRQ);
293 set_irq_flags(pin, IRQF_VALID);
294 }
295
296 set_irq_chained_handler(id, gpio_irq_handler);
297
298 /* enable the PIO peripheral clock */
299 at91_sys_write(AT91_PMC_PCER, 1 << id);
300 }
301 pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, banks);
302}
diff --git a/arch/arm/mach-at91rm9200/irq.c b/arch/arm/mach-at91rm9200/irq.c
new file mode 100644
index 000000000000..cb62bc83a1dd
--- /dev/null
+++ b/arch/arm/mach-at91rm9200/irq.c
@@ -0,0 +1,170 @@
1/*
2 * linux/arch/arm/mach-at91rm9200/irq.c
3 *
4 * Copyright (C) 2004 SAN People
5 * Copyright (C) 2004 ATMEL
6 * Copyright (C) Rick Bronson
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#include <linux/config.h>
24#include <linux/init.h>
25#include <linux/module.h>
26#include <linux/mm.h>
27#include <linux/types.h>
28
29#include <asm/hardware.h>
30#include <asm/irq.h>
31#include <asm/mach-types.h>
32#include <asm/setup.h>
33
34#include <asm/mach/arch.h>
35#include <asm/mach/irq.h>
36#include <asm/mach/map.h>
37
38#include "generic.h"
39
40/*
41 * The default interrupt priority levels (0 = lowest, 7 = highest).
42 */
43static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = {
44 7, /* Advanced Interrupt Controller */
45 7, /* System Peripheral */
46 0, /* Parallel IO Controller A */
47 0, /* Parallel IO Controller B */
48 0, /* Parallel IO Controller C */
49 0, /* Parallel IO Controller D */
50 6, /* USART 0 */
51 6, /* USART 1 */
52 6, /* USART 2 */
53 6, /* USART 3 */
54 0, /* Multimedia Card Interface */
55 4, /* USB Device Port */
56 0, /* Two-Wire Interface */
57 6, /* Serial Peripheral Interface */
58 5, /* Serial Synchronous Controller */
59 5, /* Serial Synchronous Controller */
60 5, /* Serial Synchronous Controller */
61 0, /* Timer Counter 0 */
62 0, /* Timer Counter 1 */
63 0, /* Timer Counter 2 */
64 0, /* Timer Counter 3 */
65 0, /* Timer Counter 4 */
66 0, /* Timer Counter 5 */
67 3, /* USB Host port */
68 3, /* Ethernet MAC */
69 0, /* Advanced Interrupt Controller */
70 0, /* Advanced Interrupt Controller */
71 0, /* Advanced Interrupt Controller */
72 0, /* Advanced Interrupt Controller */
73 0, /* Advanced Interrupt Controller */
74 0, /* Advanced Interrupt Controller */
75 0 /* Advanced Interrupt Controller */
76};
77
78
79static void at91rm9200_mask_irq(unsigned int irq)
80{
81 /* Disable interrupt on AIC */
82 at91_sys_write(AT91_AIC_IDCR, 1 << irq);
83}
84
85static void at91rm9200_unmask_irq(unsigned int irq)
86{
87 /* Enable interrupt on AIC */
88 at91_sys_write(AT91_AIC_IECR, 1 << irq);
89}
90
91static int at91rm9200_irq_type(unsigned irq, unsigned type)
92{
93 unsigned int smr, srctype;
94
95 /* change triggering only for FIQ and external IRQ0..IRQ6 */
96 if ((irq < AT91_ID_IRQ0) && (irq != AT91_ID_FIQ))
97 return -EINVAL;
98
99 switch (type) {
100 case IRQT_HIGH:
101 srctype = AT91_AIC_SRCTYPE_HIGH;
102 break;
103 case IRQT_RISING:
104 srctype = AT91_AIC_SRCTYPE_RISING;
105 break;
106 case IRQT_LOW:
107 srctype = AT91_AIC_SRCTYPE_LOW;
108 break;
109 case IRQT_FALLING:
110 srctype = AT91_AIC_SRCTYPE_FALLING;
111 break;
112 default:
113 return -EINVAL;
114 }
115
116 smr = at91_sys_read(AT91_AIC_SMR(irq)) & ~AT91_AIC_SRCTYPE;
117 at91_sys_write(AT91_AIC_SMR(irq), smr | srctype);
118 return 0;
119}
120
121static struct irqchip at91rm9200_irq_chip = {
122 .ack = at91rm9200_mask_irq,
123 .mask = at91rm9200_mask_irq,
124 .unmask = at91rm9200_unmask_irq,
125 .set_type = at91rm9200_irq_type,
126};
127
128/*
129 * Initialize the AIC interrupt controller.
130 */
131void __init at91rm9200_init_irq(unsigned int priority[NR_AIC_IRQS])
132{
133 unsigned int i;
134
135 /* No priority list specified for this board -> use defaults */
136 if (priority == NULL)
137 priority = at91rm9200_default_irq_priority;
138
139 /*
140 * The IVR is used by macro get_irqnr_and_base to read and verify.
141 * The irq number is NR_AIC_IRQS when a spurious interrupt has occurred.
142 */
143 for (i = 0; i < NR_AIC_IRQS; i++) {
144 /* Put irq number in Source Vector Register: */
145 at91_sys_write(AT91_AIC_SVR(i), i);
146 /* Store the Source Mode Register as defined in table above */
147 at91_sys_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]);
148
149 set_irq_chip(i, &at91rm9200_irq_chip);
150 set_irq_handler(i, do_level_IRQ);
151 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
152
153 /* Perform 8 End Of Interrupt Command to make sure AIC will not Lock out nIRQ */
154 if (i < 8)
155 at91_sys_write(AT91_AIC_EOICR, 0);
156 }
157
158 /*
159 * Spurious Interrupt ID in Spurious Vector Register is NR_AIC_IRQS
160 * When there is no current interrupt, the IRQ Vector Register reads the value stored in AIC_SPU
161 */
162 at91_sys_write(AT91_AIC_SPU, NR_AIC_IRQS);
163
164 /* No debugging in AIC: Debug (Protect) Control Register */
165 at91_sys_write(AT91_AIC_DCR, 0);
166
167 /* Disable and clear all interrupts initially */
168 at91_sys_write(AT91_AIC_IDCR, 0xFFFFFFFF);
169 at91_sys_write(AT91_AIC_ICCR, 0xFFFFFFFF);
170}
diff --git a/arch/arm/mach-at91rm9200/time.c b/arch/arm/mach-at91rm9200/time.c
new file mode 100644
index 000000000000..1b6dd2deeb22
--- /dev/null
+++ b/arch/arm/mach-at91rm9200/time.c
@@ -0,0 +1,127 @@
1/*
2 * linux/arch/arm/mach-at91rm9200/time.c
3 *
4 * Copyright (C) 2003 SAN People
5 * Copyright (C) 2003 ATMEL
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <linux/config.h>
23#include <linux/init.h>
24#include <linux/interrupt.h>
25#include <linux/kernel.h>
26#include <linux/sched.h>
27#include <linux/time.h>
28
29#include <asm/hardware.h>
30#include <asm/io.h>
31#include <asm/irq.h>
32#include <asm/mach/time.h>
33
34/*
35 * The ST_CRTR is updated asynchronously to the master clock. It is therefore
36 * necessary to read it twice (with the same value) to ensure accuracy.
37 */
38static inline unsigned long read_CRTR(void) {
39 unsigned long x1, x2;
40
41 do {
42 x1 = at91_sys_read(AT91_ST_CRTR);
43 x2 = at91_sys_read(AT91_ST_CRTR);
44 } while (x1 != x2);
45
46 return x1;
47}
48
49/*
50 * Returns number of microseconds since last timer interrupt. Note that interrupts
51 * will have been disabled by do_gettimeofday()
52 * 'LATCH' is hwclock ticks (see CLOCK_TICK_RATE in timex.h) per jiffy.
53 * 'tick' is usecs per jiffy (linux/timex.h).
54 */
55static unsigned long at91rm9200_gettimeoffset(void)
56{
57 unsigned long elapsed;
58
59 elapsed = (read_CRTR() - at91_sys_read(AT91_ST_RTAR)) & AT91_ST_ALMV;
60
61 return (unsigned long)(elapsed * (tick_nsec / 1000)) / LATCH;
62}
63
64/*
65 * IRQ handler for the timer.
66 */
67static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
68{
69 unsigned long rtar;
70
71 if (at91_sys_read(AT91_ST_SR) & AT91_ST_PITS) { /* This is a shared interrupt */
72 write_seqlock(&xtime_lock);
73
74 do {
75 timer_tick(regs);
76 rtar = (at91_sys_read(AT91_ST_RTAR) + LATCH) & AT91_ST_ALMV;
77 at91_sys_write(AT91_ST_RTAR, rtar);
78 } while (((read_CRTR() - at91_sys_read(AT91_ST_RTAR)) & AT91_ST_ALMV) >= LATCH);
79
80 write_sequnlock(&xtime_lock);
81
82 return IRQ_HANDLED;
83 }
84 else
85 return IRQ_NONE; /* not handled */
86}
87
88static struct irqaction at91rm9200_timer_irq = {
89 .name = "at91_tick",
90 .flags = SA_SHIRQ | SA_INTERRUPT,
91 .handler = at91rm9200_timer_interrupt
92};
93
94/*
95 * Set up timer interrupt.
96 */
97void __init at91rm9200_timer_init(void)
98{
99 /* Disable all timer interrupts */
100 at91_sys_write(AT91_ST_IDR, AT91_ST_PITS | AT91_ST_WDOVF | AT91_ST_RTTINC | AT91_ST_ALMS);
101 (void) at91_sys_read(AT91_ST_SR); /* Clear any pending interrupts */
102
103 /*
104 * Make IRQs happen for the system timer.
105 */
106 setup_irq(AT91_ID_SYS, &at91rm9200_timer_irq);
107
108 /* Set initial alarm to 0 */
109 at91_sys_write(AT91_ST_RTAR, 0);
110
111 /* Real time counter incremented every 30.51758 microseconds */
112 at91_sys_write(AT91_ST_RTMR, 1);
113
114 /* Set Period Interval timer */
115 at91_sys_write(AT91_ST_PIMR, LATCH);
116
117 /* Change the kernel's 'tick' value to 10009 usec. (the default is 10000) */
118 tick_usec = (LATCH * 1000000) / CLOCK_TICK_RATE;
119
120 /* Enable Period Interval Timer interrupt */
121 at91_sys_write(AT91_ST_IER, AT91_ST_PITS);
122}
123
124struct sys_timer at91rm9200_timer = {
125 .init = at91rm9200_timer_init,
126 .offset = at91rm9200_gettimeoffset,
127};
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 04cf0557e54b..3b79d0e23455 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -62,8 +62,8 @@ config CPU_ARM720T
62# ARM920T 62# ARM920T
63config CPU_ARM920T 63config CPU_ARM920T
64 bool "Support ARM920T processor" if !ARCH_S3C2410 64 bool "Support ARM920T processor" if !ARCH_S3C2410
65 depends on ARCH_INTEGRATOR || ARCH_S3C2410 || ARCH_IMX || ARCH_AAEC2000 65 depends on ARCH_INTEGRATOR || ARCH_S3C2410 || ARCH_IMX || ARCH_AAEC2000 || ARCH_AT91RM9200
66 default y if ARCH_S3C2410 66 default y if ARCH_S3C2410 || ARCH_AT91RM9200
67 select CPU_32v4 67 select CPU_32v4
68 select CPU_ABRT_EV4T 68 select CPU_ABRT_EV4T
69 select CPU_CACHE_V4WT 69 select CPU_CACHE_V4WT
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-12 04:41:16 -0500