Merge branch 'next-spi' of git://git.secretlab.ca/git/linux-2.6

* 'next-spi' of git://git.secretlab.ca/git/linux-2.6: (53 commits)
  spi/omap2_mcspi: Verify TX reg is empty after TX only xfer with DMA
  spi/omap2_mcspi: disable channel after TX_ONLY transfer in PIO mode
  spi/bfin_spi: namespace local structs
  spi/bfin_spi: init early
  spi/bfin_spi: check per-transfer bits_per_word
  spi/bfin_spi: warn when CS is driven by hardware (CPHA=0)
  spi/bfin_spi: cs should be always low when a new transfer begins
  spi/bfin_spi: fix typo in comment
  spi/bfin_spi: reject unsupported SPI modes
  spi/bfin_spi: use dma_disable_irq_nosync() in irq handler
  spi/bfin_spi: combine duplicate SPI_CTL read/write logic
  spi/bfin_spi: reset ctl_reg bits when setup is run again on a device
  spi/bfin_spi: push all size checks into the transfer function
  spi/bfin_spi: use nosync when disabling the IRQ from the IRQ handler
  spi/bfin_spi: sync hardware state before reprogramming everything
  spi/bfin_spi: save/restore state when suspending/resuming
  spi/bfin_spi: redo GPIO CS handling
  Blackfin: SPI: expand SPI bitmasks
  spi/bfin_spi: use the SPI namespaced bit names
  spi/bfin_spi: drop extra memory we don't need
  ...

8 files changed, 72 insertions, 105 deletions

diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c
index bc9a42da2145..0c936cf5675a 100644
--- a/arch/arm/mach-lpc32xx/phy3250.c
+++ b/arch/arm/mach-lpc32xx/phy3250.c
@@ -172,18 +172,12 @@ static void phy3250_spi_cs_set(u32 control)
 }
 
 static struct pl022_config_chip spi0_chip_info = {
-        .lbm                    = LOOPBACK_DISABLED,
         .com_mode               = INTERRUPT_TRANSFER,
         .iface                  = SSP_INTERFACE_MOTOROLA_SPI,
         .hierarchy              = SSP_MASTER,
         .slave_tx_disable       = 0,
-        .endian_tx              = SSP_TX_LSB,
-        .endian_rx              = SSP_RX_LSB,
-        .data_size              = SSP_DATA_BITS_8,
         .rx_lev_trig            = SSP_RX_4_OR_MORE_ELEM,
         .tx_lev_trig            = SSP_TX_4_OR_MORE_EMPTY_LOC,
-        .clk_phase              = SSP_CLK_FIRST_EDGE,
-        .clk_pol                = SSP_CLK_POL_IDLE_LOW,
         .ctrl_len               = SSP_BITS_8,
         .wait_state             = SSP_MWIRE_WAIT_ZERO,
         .duplex                 = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
@@ -239,6 +233,7 @@ static int __init phy3250_spi_board_register(void)
                         .max_speed_hz = 5000000,
                         .bus_num = 0,
                         .chip_select = 0,
+                        .mode = SPI_MODE_0,
                         .platform_data = &eeprom,
                         .controller_data = &spi0_chip_info,
                 },
diff --git a/arch/arm/mach-u300/dummyspichip.c b/arch/arm/mach-u300/dummyspichip.c
index 5f55012b7c9e..03f793612594 100644
--- a/arch/arm/mach-u300/dummyspichip.c
+++ b/arch/arm/mach-u300/dummyspichip.c
@@ -46,7 +46,6 @@ static ssize_t dummy_looptest(struct device *dev,
          * struct, this is just used here to alter the behaviour of the chip
          * in order to perform tests.
          */
-        struct pl022_config_chip *chip_info = spi->controller_data;
         int status;
         u8 txbuf[14] = {0xDE, 0xAD, 0xBE, 0xEF, 0x2B, 0xAD,
                         0xCA, 0xFE, 0xBA, 0xBE, 0xB1, 0x05,
@@ -72,7 +71,7 @@ static ssize_t dummy_looptest(struct device *dev,
          * Force chip to 8 bit mode
          * WARNING: NEVER DO THIS IN REAL DRIVER CODE, THIS SHOULD BE STATIC!
          */
-        chip_info->data_size = SSP_DATA_BITS_8;
+        spi->bits_per_word = 8;
         /* You should NOT DO THIS EITHER */
         spi->master->setup(spi);
 
@@ -159,7 +158,7 @@ static ssize_t dummy_looptest(struct device *dev,
          * Force chip to 16 bit mode
          * WARNING: NEVER DO THIS IN REAL DRIVER CODE, THIS SHOULD BE STATIC!
          */
-        chip_info->data_size = SSP_DATA_BITS_16;
+        spi->bits_per_word = 16;
         /* You should NOT DO THIS EITHER */
         spi->master->setup(spi);
 
diff --git a/arch/arm/mach-u300/spi.c b/arch/arm/mach-u300/spi.c
index f0e887bea30e..edb2c0d255c2 100644
--- a/arch/arm/mach-u300/spi.c
+++ b/arch/arm/mach-u300/spi.c
@@ -30,8 +30,6 @@ static void select_dummy_chip(u32 chipselect)
 }
 
 struct pl022_config_chip dummy_chip_info = {
-        /* Nominally this is LOOPBACK_DISABLED, but this is our dummy chip! */
-        .lbm = LOOPBACK_ENABLED,
         /*
          * available POLLING_TRANSFER and INTERRUPT_TRANSFER,
          * DMA_TRANSFER does not work
@@ -42,14 +40,8 @@ struct pl022_config_chip dummy_chip_info = {
         .hierarchy = SSP_MASTER,
         /* 0 = drive TX even as slave, 1 = do not drive TX as slave */
         .slave_tx_disable = 0,
-        /* LSB first */
-        .endian_tx = SSP_TX_LSB,
-        .endian_rx = SSP_RX_LSB,
-        .data_size = SSP_DATA_BITS_8, /* used to be 12 in some default */
         .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM,
         .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC,
-        .clk_phase = SSP_CLK_SECOND_EDGE,
-        .clk_pol = SSP_CLK_POL_IDLE_LOW,
         .ctrl_len = SSP_BITS_12,
         .wait_state = SSP_MWIRE_WAIT_ZERO,
         .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
@@ -75,7 +67,7 @@ static struct spi_board_info u300_spi_devices[] = {
                 .bus_num        = 0, /* Only one bus on this chip */
                 .chip_select    = 0,
                 /* Means SPI_CS_HIGH, change if e.g low CS */
-                .mode           = 0,
+                .mode           = SPI_MODE_1 | SPI_LSB_FIRST | SPI_LOOP,
         },
 #endif
 };
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 0e8fd135a57d..219ae0ca4eef 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -55,19 +55,13 @@ static void ab4500_spi_cs_control(u32 command)
 }
 
 struct pl022_config_chip ab4500_chip_info = {
-        .lbm = LOOPBACK_DISABLED,
         .com_mode = INTERRUPT_TRANSFER,
         .iface = SSP_INTERFACE_MOTOROLA_SPI,
         /* we can act as master only */
         .hierarchy = SSP_MASTER,
         .slave_tx_disable = 0,
-        .endian_rx = SSP_RX_MSB,
-        .endian_tx = SSP_TX_MSB,
-        .data_size = SSP_DATA_BITS_24,
         .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM,
         .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC,
-        .clk_phase = SSP_CLK_SECOND_EDGE,
-        .clk_pol = SSP_CLK_POL_IDLE_HIGH,
         .cs_control = ab4500_spi_cs_control,
 };
 
@@ -83,7 +77,7 @@ static struct spi_board_info u8500_spi_devices[] = {
                 .max_speed_hz = 12000000,
                 .bus_num = 0,
                 .chip_select = 0,
-                .mode = SPI_MODE_0,
+                .mode = SPI_MODE_3,
                 .irq = IRQ_DB8500_AB8500,
         },
 };
diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
index e5aba8f95b79..b226f7405e6b 100644
--- a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
+++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
@@ -32,6 +32,8 @@ struct s3c64xx_spi_csinfo {
  * struct s3c64xx_spi_info - SPI Controller defining structure
  * @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field.
  * @src_clk_name: Platform name of the corresponding clock.
+ * @clk_from_cmu: If the SPI clock/prescalar control block is present
+ *     by the platform's clock-management-unit and not in SPI controller.
  * @num_cs: Number of CS this controller emulates.
  * @cfg_gpio: Configure pins for this SPI controller.
  * @fifo_lvl_mask: All tx fifo_lvl fields start at offset-6
@@ -41,6 +43,7 @@ struct s3c64xx_spi_csinfo {
 struct s3c64xx_spi_info {
         int src_clk_nr;
         char *src_clk_name;
+        bool clk_from_cmu;
 
         int num_cs;
 
diff --git a/arch/blackfin/include/asm/bfin5xx_spi.h b/arch/blackfin/include/asm/bfin5xx_spi.h
index ed4f8c6db0cd..4223cf08ce83 100644
--- a/arch/blackfin/include/asm/bfin5xx_spi.h
+++ b/arch/blackfin/include/asm/bfin5xx_spi.h
@@ -11,26 +11,17 @@
 
 #define MIN_SPI_BAUD_VAL        2
 
-#define SPI_READ              0
-#define SPI_WRITE             1
-
-#define SPI_CTRL_OFF            0x0
-#define SPI_FLAG_OFF            0x4
-#define SPI_STAT_OFF            0x8
-#define SPI_TXBUFF_OFF          0xc
-#define SPI_RXBUFF_OFF          0x10
-#define SPI_BAUD_OFF            0x14
-#define SPI_SHAW_OFF            0x18
-
-
 #define BIT_CTL_ENABLE      0x4000
 #define BIT_CTL_OPENDRAIN   0x2000
 #define BIT_CTL_MASTER      0x1000
-#define BIT_CTL_POLAR       0x0800
-#define BIT_CTL_PHASE       0x0400
-#define BIT_CTL_BITORDER    0x0200
+#define BIT_CTL_CPOL        0x0800
+#define BIT_CTL_CPHA        0x0400
+#define BIT_CTL_LSBF        0x0200
 #define BIT_CTL_WORDSIZE    0x0100
-#define BIT_CTL_MISOENABLE  0x0020
+#define BIT_CTL_EMISO       0x0020
+#define BIT_CTL_PSSE        0x0010
+#define BIT_CTL_GM          0x0008
+#define BIT_CTL_SZ          0x0004
 #define BIT_CTL_RXMOD       0x0000
 #define BIT_CTL_TXMOD       0x0001
 #define BIT_CTL_TIMOD_DMA_TX 0x0003
@@ -50,61 +41,7 @@
 #define BIT_STU_SENDOVER    0x0001
 #define BIT_STU_RECVFULL    0x0020
 
-#define CFG_SPI_ENABLE      1
-#define CFG_SPI_DISABLE     0
-
-#define CFG_SPI_OUTENABLE   1
-#define CFG_SPI_OUTDISABLE  0
-
-#define CFG_SPI_ACTLOW      1
-#define CFG_SPI_ACTHIGH     0
-
-#define CFG_SPI_PHASESTART  1
-#define CFG_SPI_PHASEMID    0
-
-#define CFG_SPI_MASTER      1
-#define CFG_SPI_SLAVE       0
-
-#define CFG_SPI_SENELAST    0
-#define CFG_SPI_SENDZERO    1
-
-#define CFG_SPI_RCVFLUSH    1
-#define CFG_SPI_RCVDISCARD  0
-
-#define CFG_SPI_LSBFIRST    1
-#define CFG_SPI_MSBFIRST    0
-
-#define CFG_SPI_WORDSIZE16  1
-#define CFG_SPI_WORDSIZE8   0
-
-#define CFG_SPI_MISOENABLE   1
-#define CFG_SPI_MISODISABLE  0
-
-#define CFG_SPI_READ      0x00
-#define CFG_SPI_WRITE     0x01
-#define CFG_SPI_DMAREAD   0x02
-#define CFG_SPI_DMAWRITE  0x03
-
-#define CFG_SPI_CSCLEARALL  0
-#define CFG_SPI_CHIPSEL1    1
-#define CFG_SPI_CHIPSEL2    2
-#define CFG_SPI_CHIPSEL3    3
-#define CFG_SPI_CHIPSEL4    4
-#define CFG_SPI_CHIPSEL5    5
-#define CFG_SPI_CHIPSEL6    6
-#define CFG_SPI_CHIPSEL7    7
-
-#define CFG_SPI_CS1VALUE    1
-#define CFG_SPI_CS2VALUE    2
-#define CFG_SPI_CS3VALUE    3
-#define CFG_SPI_CS4VALUE    4
-#define CFG_SPI_CS5VALUE    5
-#define CFG_SPI_CS6VALUE    6
-#define CFG_SPI_CS7VALUE    7
-
-#define CMD_SPI_SET_BAUDRATE  2
-#define CMD_SPI_GET_SYSTEMCLOCK   25
-#define CMD_SPI_SET_WRITECONTINUOUS     26
+#define MAX_CTRL_CS          8  /* cs in spi controller */
 
 /* device.platform_data for SSP controller devices */
 struct bfin5xx_spi_master {
@@ -120,9 +57,7 @@ struct bfin5xx_spi_chip {
         u16 ctl_reg;
         u8 enable_dma;
         u8 bits_per_word;
-        u8 cs_change_per_word;
         u16 cs_chg_udelay; /* Some devices require 16-bit delays */
-        u32 cs_gpio;
         /* Value to send if no TX value is supplied, usually 0x0 or 0xFFFF */
         u16 idle_tx_val;
         u8 pio_interrupt; /* Enable spi data irq */
diff --git a/arch/powerpc/boot/dts/mpc8536ds.dts b/arch/powerpc/boot/dts/mpc8536ds.dts
index 815cebb2e3e5..a75c10eed269 100644
--- a/arch/powerpc/boot/dts/mpc8536ds.dts
+++ b/arch/powerpc/boot/dts/mpc8536ds.dts
@@ -108,6 +108,58 @@
                         };
                 };
 
+                spi@7000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "fsl,mpc8536-espi";
+                        reg = <0x7000 0x1000>;
+                        interrupts = <59 0x2>;
+                        interrupt-parent = <&mpic>;
+                        fsl,espi-num-chipselects = <4>;
+
+                        flash@0 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                compatible = "spansion,s25sl12801";
+                                reg = <0>;
+                                spi-max-frequency = <40000000>;
+                                partition@u-boot {
+                                        label = "u-boot";
+                                        reg = <0x00000000 0x00100000>;
+                                        read-only;
+                                };
+                                partition@kernel {
+                                        label = "kernel";
+                                        reg = <0x00100000 0x00500000>;
+                                        read-only;
+                                };
+                                partition@dtb {
+                                        label = "dtb";
+                                        reg = <0x00600000 0x00100000>;
+                                        read-only;
+                                };
+                                partition@fs {
+                                        label = "file system";
+                                        reg = <0x00700000 0x00900000>;
+                                };
+                        };
+                        flash@1 {
+                                compatible = "spansion,s25sl12801";
+                                reg = <1>;
+                                spi-max-frequency = <40000000>;
+                        };
+                        flash@2 {
+                                compatible = "spansion,s25sl12801";
+                                reg = <2>;
+                                spi-max-frequency = <40000000>;
+                        };
+                        flash@3 {
+                                compatible = "spansion,s25sl12801";
+                                reg = <3>;
+                                spi-max-frequency = <40000000>;
+                        };
+                };
+
                 dma@21300 {
                         #address-cells = <1>;
                         #size-cells = <1>;
diff --git a/arch/powerpc/boot/dts/p4080ds.dts b/arch/powerpc/boot/dts/p4080ds.dts
index 2f0de24e3822..5b7fc29dd6cf 100644
--- a/arch/powerpc/boot/dts/p4080ds.dts
+++ b/arch/powerpc/boot/dts/p4080ds.dts
@@ -236,22 +236,19 @@
                 };
 
                 spi@110000 {
-                        cell-index = <0>;
                         #address-cells = <1>;
                         #size-cells = <0>;
-                        compatible = "fsl,espi";
+                        compatible = "fsl,p4080-espi", "fsl,mpc8536-espi";
                         reg = <0x110000 0x1000>;
                         interrupts = <53 0x2>;
                         interrupt-parent = <&mpic>;
-                        espi,num-ss-bits = <4>;
-                        mode = "cpu";
+                        fsl,espi-num-chipselects = <4>;
 
-                        fsl_m25p80@0 {
+                        flash@0 {
                                 #address-cells = <1>;
                                 #size-cells = <1>;
-                                compatible = "fsl,espi-flash";
+                                compatible = "spansion,s25sl12801";
                                 reg = <0>;
-                                linux,modalias = "fsl_m25p80";
                                 spi-max-frequency = <40000000>; /* input clock */
                                 partition@u-boot {
                                         label = "u-boot";