diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2010-10-21 17:37:00 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2010-10-21 17:37:00 -0400 |
commit | 70ada77920723fbc2b35e9b301022fb1e166b41b (patch) | |
tree | f30f24135eff89020d8ae21d6c7a83cf5c812585 /arch | |
parent | b22793f7fdc38d73c4bb4299a313deef56dcfe66 (diff) | |
parent | 2764c500be0c1f057349ee6c81557239de060f87 (diff) |
Merge branch 'next-spi' of git://git.secretlab.ca/git/linux-2.6
* 'next-spi' of git://git.secretlab.ca/git/linux-2.6: (53 commits)
spi/omap2_mcspi: Verify TX reg is empty after TX only xfer with DMA
spi/omap2_mcspi: disable channel after TX_ONLY transfer in PIO mode
spi/bfin_spi: namespace local structs
spi/bfin_spi: init early
spi/bfin_spi: check per-transfer bits_per_word
spi/bfin_spi: warn when CS is driven by hardware (CPHA=0)
spi/bfin_spi: cs should be always low when a new transfer begins
spi/bfin_spi: fix typo in comment
spi/bfin_spi: reject unsupported SPI modes
spi/bfin_spi: use dma_disable_irq_nosync() in irq handler
spi/bfin_spi: combine duplicate SPI_CTL read/write logic
spi/bfin_spi: reset ctl_reg bits when setup is run again on a device
spi/bfin_spi: push all size checks into the transfer function
spi/bfin_spi: use nosync when disabling the IRQ from the IRQ handler
spi/bfin_spi: sync hardware state before reprogramming everything
spi/bfin_spi: save/restore state when suspending/resuming
spi/bfin_spi: redo GPIO CS handling
Blackfin: SPI: expand SPI bitmasks
spi/bfin_spi: use the SPI namespaced bit names
spi/bfin_spi: drop extra memory we don't need
...
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/mach-lpc32xx/phy3250.c | 7 | ||||
-rw-r--r-- | arch/arm/mach-u300/dummyspichip.c | 5 | ||||
-rw-r--r-- | arch/arm/mach-u300/spi.c | 10 | ||||
-rw-r--r-- | arch/arm/mach-ux500/board-mop500.c | 8 | ||||
-rw-r--r-- | arch/arm/plat-samsung/include/plat/s3c64xx-spi.h | 3 | ||||
-rw-r--r-- | arch/blackfin/include/asm/bfin5xx_spi.h | 81 | ||||
-rw-r--r-- | arch/powerpc/boot/dts/mpc8536ds.dts | 52 | ||||
-rw-r--r-- | arch/powerpc/boot/dts/p4080ds.dts | 11 |
8 files changed, 72 insertions, 105 deletions
diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c index bc9a42da2145..0c936cf5675a 100644 --- a/arch/arm/mach-lpc32xx/phy3250.c +++ b/arch/arm/mach-lpc32xx/phy3250.c | |||
@@ -172,18 +172,12 @@ static void phy3250_spi_cs_set(u32 control) | |||
172 | } | 172 | } |
173 | 173 | ||
174 | static struct pl022_config_chip spi0_chip_info = { | 174 | static struct pl022_config_chip spi0_chip_info = { |
175 | .lbm = LOOPBACK_DISABLED, | ||
176 | .com_mode = INTERRUPT_TRANSFER, | 175 | .com_mode = INTERRUPT_TRANSFER, |
177 | .iface = SSP_INTERFACE_MOTOROLA_SPI, | 176 | .iface = SSP_INTERFACE_MOTOROLA_SPI, |
178 | .hierarchy = SSP_MASTER, | 177 | .hierarchy = SSP_MASTER, |
179 | .slave_tx_disable = 0, | 178 | .slave_tx_disable = 0, |
180 | .endian_tx = SSP_TX_LSB, | ||
181 | .endian_rx = SSP_RX_LSB, | ||
182 | .data_size = SSP_DATA_BITS_8, | ||
183 | .rx_lev_trig = SSP_RX_4_OR_MORE_ELEM, | 179 | .rx_lev_trig = SSP_RX_4_OR_MORE_ELEM, |
184 | .tx_lev_trig = SSP_TX_4_OR_MORE_EMPTY_LOC, | 180 | .tx_lev_trig = SSP_TX_4_OR_MORE_EMPTY_LOC, |
185 | .clk_phase = SSP_CLK_FIRST_EDGE, | ||
186 | .clk_pol = SSP_CLK_POL_IDLE_LOW, | ||
187 | .ctrl_len = SSP_BITS_8, | 181 | .ctrl_len = SSP_BITS_8, |
188 | .wait_state = SSP_MWIRE_WAIT_ZERO, | 182 | .wait_state = SSP_MWIRE_WAIT_ZERO, |
189 | .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, | 183 | .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, |
@@ -239,6 +233,7 @@ static int __init phy3250_spi_board_register(void) | |||
239 | .max_speed_hz = 5000000, | 233 | .max_speed_hz = 5000000, |
240 | .bus_num = 0, | 234 | .bus_num = 0, |
241 | .chip_select = 0, | 235 | .chip_select = 0, |
236 | .mode = SPI_MODE_0, | ||
242 | .platform_data = &eeprom, | 237 | .platform_data = &eeprom, |
243 | .controller_data = &spi0_chip_info, | 238 | .controller_data = &spi0_chip_info, |
244 | }, | 239 | }, |
diff --git a/arch/arm/mach-u300/dummyspichip.c b/arch/arm/mach-u300/dummyspichip.c index 5f55012b7c9e..03f793612594 100644 --- a/arch/arm/mach-u300/dummyspichip.c +++ b/arch/arm/mach-u300/dummyspichip.c | |||
@@ -46,7 +46,6 @@ static ssize_t dummy_looptest(struct device *dev, | |||
46 | * struct, this is just used here to alter the behaviour of the chip | 46 | * struct, this is just used here to alter the behaviour of the chip |
47 | * in order to perform tests. | 47 | * in order to perform tests. |
48 | */ | 48 | */ |
49 | struct pl022_config_chip *chip_info = spi->controller_data; | ||
50 | int status; | 49 | int status; |
51 | u8 txbuf[14] = {0xDE, 0xAD, 0xBE, 0xEF, 0x2B, 0xAD, | 50 | u8 txbuf[14] = {0xDE, 0xAD, 0xBE, 0xEF, 0x2B, 0xAD, |
52 | 0xCA, 0xFE, 0xBA, 0xBE, 0xB1, 0x05, | 51 | 0xCA, 0xFE, 0xBA, 0xBE, 0xB1, 0x05, |
@@ -72,7 +71,7 @@ static ssize_t dummy_looptest(struct device *dev, | |||
72 | * Force chip to 8 bit mode | 71 | * Force chip to 8 bit mode |
73 | * WARNING: NEVER DO THIS IN REAL DRIVER CODE, THIS SHOULD BE STATIC! | 72 | * WARNING: NEVER DO THIS IN REAL DRIVER CODE, THIS SHOULD BE STATIC! |
74 | */ | 73 | */ |
75 | chip_info->data_size = SSP_DATA_BITS_8; | 74 | spi->bits_per_word = 8; |
76 | /* You should NOT DO THIS EITHER */ | 75 | /* You should NOT DO THIS EITHER */ |
77 | spi->master->setup(spi); | 76 | spi->master->setup(spi); |
78 | 77 | ||
@@ -159,7 +158,7 @@ static ssize_t dummy_looptest(struct device *dev, | |||
159 | * Force chip to 16 bit mode | 158 | * Force chip to 16 bit mode |
160 | * WARNING: NEVER DO THIS IN REAL DRIVER CODE, THIS SHOULD BE STATIC! | 159 | * WARNING: NEVER DO THIS IN REAL DRIVER CODE, THIS SHOULD BE STATIC! |
161 | */ | 160 | */ |
162 | chip_info->data_size = SSP_DATA_BITS_16; | 161 | spi->bits_per_word = 16; |
163 | /* You should NOT DO THIS EITHER */ | 162 | /* You should NOT DO THIS EITHER */ |
164 | spi->master->setup(spi); | 163 | spi->master->setup(spi); |
165 | 164 | ||
diff --git a/arch/arm/mach-u300/spi.c b/arch/arm/mach-u300/spi.c index f0e887bea30e..edb2c0d255c2 100644 --- a/arch/arm/mach-u300/spi.c +++ b/arch/arm/mach-u300/spi.c | |||
@@ -30,8 +30,6 @@ static void select_dummy_chip(u32 chipselect) | |||
30 | } | 30 | } |
31 | 31 | ||
32 | struct pl022_config_chip dummy_chip_info = { | 32 | struct pl022_config_chip dummy_chip_info = { |
33 | /* Nominally this is LOOPBACK_DISABLED, but this is our dummy chip! */ | ||
34 | .lbm = LOOPBACK_ENABLED, | ||
35 | /* | 33 | /* |
36 | * available POLLING_TRANSFER and INTERRUPT_TRANSFER, | 34 | * available POLLING_TRANSFER and INTERRUPT_TRANSFER, |
37 | * DMA_TRANSFER does not work | 35 | * DMA_TRANSFER does not work |
@@ -42,14 +40,8 @@ struct pl022_config_chip dummy_chip_info = { | |||
42 | .hierarchy = SSP_MASTER, | 40 | .hierarchy = SSP_MASTER, |
43 | /* 0 = drive TX even as slave, 1 = do not drive TX as slave */ | 41 | /* 0 = drive TX even as slave, 1 = do not drive TX as slave */ |
44 | .slave_tx_disable = 0, | 42 | .slave_tx_disable = 0, |
45 | /* LSB first */ | ||
46 | .endian_tx = SSP_TX_LSB, | ||
47 | .endian_rx = SSP_RX_LSB, | ||
48 | .data_size = SSP_DATA_BITS_8, /* used to be 12 in some default */ | ||
49 | .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM, | 43 | .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM, |
50 | .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC, | 44 | .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC, |
51 | .clk_phase = SSP_CLK_SECOND_EDGE, | ||
52 | .clk_pol = SSP_CLK_POL_IDLE_LOW, | ||
53 | .ctrl_len = SSP_BITS_12, | 45 | .ctrl_len = SSP_BITS_12, |
54 | .wait_state = SSP_MWIRE_WAIT_ZERO, | 46 | .wait_state = SSP_MWIRE_WAIT_ZERO, |
55 | .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, | 47 | .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, |
@@ -75,7 +67,7 @@ static struct spi_board_info u300_spi_devices[] = { | |||
75 | .bus_num = 0, /* Only one bus on this chip */ | 67 | .bus_num = 0, /* Only one bus on this chip */ |
76 | .chip_select = 0, | 68 | .chip_select = 0, |
77 | /* Means SPI_CS_HIGH, change if e.g low CS */ | 69 | /* Means SPI_CS_HIGH, change if e.g low CS */ |
78 | .mode = 0, | 70 | .mode = SPI_MODE_1 | SPI_LSB_FIRST | SPI_LOOP, |
79 | }, | 71 | }, |
80 | #endif | 72 | #endif |
81 | }; | 73 | }; |
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c index 0e8fd135a57d..219ae0ca4eef 100644 --- a/arch/arm/mach-ux500/board-mop500.c +++ b/arch/arm/mach-ux500/board-mop500.c | |||
@@ -55,19 +55,13 @@ static void ab4500_spi_cs_control(u32 command) | |||
55 | } | 55 | } |
56 | 56 | ||
57 | struct pl022_config_chip ab4500_chip_info = { | 57 | struct pl022_config_chip ab4500_chip_info = { |
58 | .lbm = LOOPBACK_DISABLED, | ||
59 | .com_mode = INTERRUPT_TRANSFER, | 58 | .com_mode = INTERRUPT_TRANSFER, |
60 | .iface = SSP_INTERFACE_MOTOROLA_SPI, | 59 | .iface = SSP_INTERFACE_MOTOROLA_SPI, |
61 | /* we can act as master only */ | 60 | /* we can act as master only */ |
62 | .hierarchy = SSP_MASTER, | 61 | .hierarchy = SSP_MASTER, |
63 | .slave_tx_disable = 0, | 62 | .slave_tx_disable = 0, |
64 | .endian_rx = SSP_RX_MSB, | ||
65 | .endian_tx = SSP_TX_MSB, | ||
66 | .data_size = SSP_DATA_BITS_24, | ||
67 | .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM, | 63 | .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM, |
68 | .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC, | 64 | .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC, |
69 | .clk_phase = SSP_CLK_SECOND_EDGE, | ||
70 | .clk_pol = SSP_CLK_POL_IDLE_HIGH, | ||
71 | .cs_control = ab4500_spi_cs_control, | 65 | .cs_control = ab4500_spi_cs_control, |
72 | }; | 66 | }; |
73 | 67 | ||
@@ -83,7 +77,7 @@ static struct spi_board_info u8500_spi_devices[] = { | |||
83 | .max_speed_hz = 12000000, | 77 | .max_speed_hz = 12000000, |
84 | .bus_num = 0, | 78 | .bus_num = 0, |
85 | .chip_select = 0, | 79 | .chip_select = 0, |
86 | .mode = SPI_MODE_0, | 80 | .mode = SPI_MODE_3, |
87 | .irq = IRQ_DB8500_AB8500, | 81 | .irq = IRQ_DB8500_AB8500, |
88 | }, | 82 | }, |
89 | }; | 83 | }; |
diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h index e5aba8f95b79..b226f7405e6b 100644 --- a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h +++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h | |||
@@ -32,6 +32,8 @@ struct s3c64xx_spi_csinfo { | |||
32 | * struct s3c64xx_spi_info - SPI Controller defining structure | 32 | * struct s3c64xx_spi_info - SPI Controller defining structure |
33 | * @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field. | 33 | * @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field. |
34 | * @src_clk_name: Platform name of the corresponding clock. | 34 | * @src_clk_name: Platform name of the corresponding clock. |
35 | * @clk_from_cmu: If the SPI clock/prescalar control block is present | ||
36 | * by the platform's clock-management-unit and not in SPI controller. | ||
35 | * @num_cs: Number of CS this controller emulates. | 37 | * @num_cs: Number of CS this controller emulates. |
36 | * @cfg_gpio: Configure pins for this SPI controller. | 38 | * @cfg_gpio: Configure pins for this SPI controller. |
37 | * @fifo_lvl_mask: All tx fifo_lvl fields start at offset-6 | 39 | * @fifo_lvl_mask: All tx fifo_lvl fields start at offset-6 |
@@ -41,6 +43,7 @@ struct s3c64xx_spi_csinfo { | |||
41 | struct s3c64xx_spi_info { | 43 | struct s3c64xx_spi_info { |
42 | int src_clk_nr; | 44 | int src_clk_nr; |
43 | char *src_clk_name; | 45 | char *src_clk_name; |
46 | bool clk_from_cmu; | ||
44 | 47 | ||
45 | int num_cs; | 48 | int num_cs; |
46 | 49 | ||
diff --git a/arch/blackfin/include/asm/bfin5xx_spi.h b/arch/blackfin/include/asm/bfin5xx_spi.h index ed4f8c6db0cd..4223cf08ce83 100644 --- a/arch/blackfin/include/asm/bfin5xx_spi.h +++ b/arch/blackfin/include/asm/bfin5xx_spi.h | |||
@@ -11,26 +11,17 @@ | |||
11 | 11 | ||
12 | #define MIN_SPI_BAUD_VAL 2 | 12 | #define MIN_SPI_BAUD_VAL 2 |
13 | 13 | ||
14 | #define SPI_READ 0 | ||
15 | #define SPI_WRITE 1 | ||
16 | |||
17 | #define SPI_CTRL_OFF 0x0 | ||
18 | #define SPI_FLAG_OFF 0x4 | ||
19 | #define SPI_STAT_OFF 0x8 | ||
20 | #define SPI_TXBUFF_OFF 0xc | ||
21 | #define SPI_RXBUFF_OFF 0x10 | ||
22 | #define SPI_BAUD_OFF 0x14 | ||
23 | #define SPI_SHAW_OFF 0x18 | ||
24 | |||
25 | |||
26 | #define BIT_CTL_ENABLE 0x4000 | 14 | #define BIT_CTL_ENABLE 0x4000 |
27 | #define BIT_CTL_OPENDRAIN 0x2000 | 15 | #define BIT_CTL_OPENDRAIN 0x2000 |
28 | #define BIT_CTL_MASTER 0x1000 | 16 | #define BIT_CTL_MASTER 0x1000 |
29 | #define BIT_CTL_POLAR 0x0800 | 17 | #define BIT_CTL_CPOL 0x0800 |
30 | #define BIT_CTL_PHASE 0x0400 | 18 | #define BIT_CTL_CPHA 0x0400 |
31 | #define BIT_CTL_BITORDER 0x0200 | 19 | #define BIT_CTL_LSBF 0x0200 |
32 | #define BIT_CTL_WORDSIZE 0x0100 | 20 | #define BIT_CTL_WORDSIZE 0x0100 |
33 | #define BIT_CTL_MISOENABLE 0x0020 | 21 | #define BIT_CTL_EMISO 0x0020 |
22 | #define BIT_CTL_PSSE 0x0010 | ||
23 | #define BIT_CTL_GM 0x0008 | ||
24 | #define BIT_CTL_SZ 0x0004 | ||
34 | #define BIT_CTL_RXMOD 0x0000 | 25 | #define BIT_CTL_RXMOD 0x0000 |
35 | #define BIT_CTL_TXMOD 0x0001 | 26 | #define BIT_CTL_TXMOD 0x0001 |
36 | #define BIT_CTL_TIMOD_DMA_TX 0x0003 | 27 | #define BIT_CTL_TIMOD_DMA_TX 0x0003 |
@@ -50,61 +41,7 @@ | |||
50 | #define BIT_STU_SENDOVER 0x0001 | 41 | #define BIT_STU_SENDOVER 0x0001 |
51 | #define BIT_STU_RECVFULL 0x0020 | 42 | #define BIT_STU_RECVFULL 0x0020 |
52 | 43 | ||
53 | #define CFG_SPI_ENABLE 1 | 44 | #define MAX_CTRL_CS 8 /* cs in spi controller */ |
54 | #define CFG_SPI_DISABLE 0 | ||
55 | |||
56 | #define CFG_SPI_OUTENABLE 1 | ||
57 | #define CFG_SPI_OUTDISABLE 0 | ||
58 | |||
59 | #define CFG_SPI_ACTLOW 1 | ||
60 | #define CFG_SPI_ACTHIGH 0 | ||
61 | |||
62 | #define CFG_SPI_PHASESTART 1 | ||
63 | #define CFG_SPI_PHASEMID 0 | ||
64 | |||
65 | #define CFG_SPI_MASTER 1 | ||
66 | #define CFG_SPI_SLAVE 0 | ||
67 | |||
68 | #define CFG_SPI_SENELAST 0 | ||
69 | #define CFG_SPI_SENDZERO 1 | ||
70 | |||
71 | #define CFG_SPI_RCVFLUSH 1 | ||
72 | #define CFG_SPI_RCVDISCARD 0 | ||
73 | |||
74 | #define CFG_SPI_LSBFIRST 1 | ||
75 | #define CFG_SPI_MSBFIRST 0 | ||
76 | |||
77 | #define CFG_SPI_WORDSIZE16 1 | ||
78 | #define CFG_SPI_WORDSIZE8 0 | ||
79 | |||
80 | #define CFG_SPI_MISOENABLE 1 | ||
81 | #define CFG_SPI_MISODISABLE 0 | ||
82 | |||
83 | #define CFG_SPI_READ 0x00 | ||
84 | #define CFG_SPI_WRITE 0x01 | ||
85 | #define CFG_SPI_DMAREAD 0x02 | ||
86 | #define CFG_SPI_DMAWRITE 0x03 | ||
87 | |||
88 | #define CFG_SPI_CSCLEARALL 0 | ||
89 | #define CFG_SPI_CHIPSEL1 1 | ||
90 | #define CFG_SPI_CHIPSEL2 2 | ||
91 | #define CFG_SPI_CHIPSEL3 3 | ||
92 | #define CFG_SPI_CHIPSEL4 4 | ||
93 | #define CFG_SPI_CHIPSEL5 5 | ||
94 | #define CFG_SPI_CHIPSEL6 6 | ||
95 | #define CFG_SPI_CHIPSEL7 7 | ||
96 | |||
97 | #define CFG_SPI_CS1VALUE 1 | ||
98 | #define CFG_SPI_CS2VALUE 2 | ||
99 | #define CFG_SPI_CS3VALUE 3 | ||
100 | #define CFG_SPI_CS4VALUE 4 | ||
101 | #define CFG_SPI_CS5VALUE 5 | ||
102 | #define CFG_SPI_CS6VALUE 6 | ||
103 | #define CFG_SPI_CS7VALUE 7 | ||
104 | |||
105 | #define CMD_SPI_SET_BAUDRATE 2 | ||
106 | #define CMD_SPI_GET_SYSTEMCLOCK 25 | ||
107 | #define CMD_SPI_SET_WRITECONTINUOUS 26 | ||
108 | 45 | ||
109 | /* device.platform_data for SSP controller devices */ | 46 | /* device.platform_data for SSP controller devices */ |
110 | struct bfin5xx_spi_master { | 47 | struct bfin5xx_spi_master { |
@@ -120,9 +57,7 @@ struct bfin5xx_spi_chip { | |||
120 | u16 ctl_reg; | 57 | u16 ctl_reg; |
121 | u8 enable_dma; | 58 | u8 enable_dma; |
122 | u8 bits_per_word; | 59 | u8 bits_per_word; |
123 | u8 cs_change_per_word; | ||
124 | u16 cs_chg_udelay; /* Some devices require 16-bit delays */ | 60 | u16 cs_chg_udelay; /* Some devices require 16-bit delays */ |
125 | u32 cs_gpio; | ||
126 | /* Value to send if no TX value is supplied, usually 0x0 or 0xFFFF */ | 61 | /* Value to send if no TX value is supplied, usually 0x0 or 0xFFFF */ |
127 | u16 idle_tx_val; | 62 | u16 idle_tx_val; |
128 | u8 pio_interrupt; /* Enable spi data irq */ | 63 | u8 pio_interrupt; /* Enable spi data irq */ |
diff --git a/arch/powerpc/boot/dts/mpc8536ds.dts b/arch/powerpc/boot/dts/mpc8536ds.dts index 815cebb2e3e5..a75c10eed269 100644 --- a/arch/powerpc/boot/dts/mpc8536ds.dts +++ b/arch/powerpc/boot/dts/mpc8536ds.dts | |||
@@ -108,6 +108,58 @@ | |||
108 | }; | 108 | }; |
109 | }; | 109 | }; |
110 | 110 | ||
111 | spi@7000 { | ||
112 | #address-cells = <1>; | ||
113 | #size-cells = <0>; | ||
114 | compatible = "fsl,mpc8536-espi"; | ||
115 | reg = <0x7000 0x1000>; | ||
116 | interrupts = <59 0x2>; | ||
117 | interrupt-parent = <&mpic>; | ||
118 | fsl,espi-num-chipselects = <4>; | ||
119 | |||
120 | flash@0 { | ||
121 | #address-cells = <1>; | ||
122 | #size-cells = <1>; | ||
123 | compatible = "spansion,s25sl12801"; | ||
124 | reg = <0>; | ||
125 | spi-max-frequency = <40000000>; | ||
126 | partition@u-boot { | ||
127 | label = "u-boot"; | ||
128 | reg = <0x00000000 0x00100000>; | ||
129 | read-only; | ||
130 | }; | ||
131 | partition@kernel { | ||
132 | label = "kernel"; | ||
133 | reg = <0x00100000 0x00500000>; | ||
134 | read-only; | ||
135 | }; | ||
136 | partition@dtb { | ||
137 | label = "dtb"; | ||
138 | reg = <0x00600000 0x00100000>; | ||
139 | read-only; | ||
140 | }; | ||
141 | partition@fs { | ||
142 | label = "file system"; | ||
143 | reg = <0x00700000 0x00900000>; | ||
144 | }; | ||
145 | }; | ||
146 | flash@1 { | ||
147 | compatible = "spansion,s25sl12801"; | ||
148 | reg = <1>; | ||
149 | spi-max-frequency = <40000000>; | ||
150 | }; | ||
151 | flash@2 { | ||
152 | compatible = "spansion,s25sl12801"; | ||
153 | reg = <2>; | ||
154 | spi-max-frequency = <40000000>; | ||
155 | }; | ||
156 | flash@3 { | ||
157 | compatible = "spansion,s25sl12801"; | ||
158 | reg = <3>; | ||
159 | spi-max-frequency = <40000000>; | ||
160 | }; | ||
161 | }; | ||
162 | |||
111 | dma@21300 { | 163 | dma@21300 { |
112 | #address-cells = <1>; | 164 | #address-cells = <1>; |
113 | #size-cells = <1>; | 165 | #size-cells = <1>; |
diff --git a/arch/powerpc/boot/dts/p4080ds.dts b/arch/powerpc/boot/dts/p4080ds.dts index 2f0de24e3822..5b7fc29dd6cf 100644 --- a/arch/powerpc/boot/dts/p4080ds.dts +++ b/arch/powerpc/boot/dts/p4080ds.dts | |||
@@ -236,22 +236,19 @@ | |||
236 | }; | 236 | }; |
237 | 237 | ||
238 | spi@110000 { | 238 | spi@110000 { |
239 | cell-index = <0>; | ||
240 | #address-cells = <1>; | 239 | #address-cells = <1>; |
241 | #size-cells = <0>; | 240 | #size-cells = <0>; |
242 | compatible = "fsl,espi"; | 241 | compatible = "fsl,p4080-espi", "fsl,mpc8536-espi"; |
243 | reg = <0x110000 0x1000>; | 242 | reg = <0x110000 0x1000>; |
244 | interrupts = <53 0x2>; | 243 | interrupts = <53 0x2>; |
245 | interrupt-parent = <&mpic>; | 244 | interrupt-parent = <&mpic>; |
246 | espi,num-ss-bits = <4>; | 245 | fsl,espi-num-chipselects = <4>; |
247 | mode = "cpu"; | ||
248 | 246 | ||
249 | fsl_m25p80@0 { | 247 | flash@0 { |
250 | #address-cells = <1>; | 248 | #address-cells = <1>; |
251 | #size-cells = <1>; | 249 | #size-cells = <1>; |
252 | compatible = "fsl,espi-flash"; | 250 | compatible = "spansion,s25sl12801"; |
253 | reg = <0>; | 251 | reg = <0>; |
254 | linux,modalias = "fsl_m25p80"; | ||
255 | spi-max-frequency = <40000000>; /* input clock */ | 252 | spi-max-frequency = <40000000>; /* input clock */ |
256 | partition@u-boot { | 253 | partition@u-boot { |
257 | label = "u-boot"; | 254 | label = "u-boot"; |