avr32: at32ap700x: specify DMA src and dst masters

Now that the dw_dmac DMA driver supports configurable source and
destination masters we need to specify which ones to use. This was
previously hardcoded to 0 and 1 respectively in the driver.

Acked-by: Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
Signed-off-by: Jamie Iles <jamie@jamieiles.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>

1 files changed, 6 insertions, 0 deletions

diff --git a/arch/avr32/mach-at32ap/at32ap700x.c b/arch/avr32/mach-at32ap/at32ap700x.c
index e67c99945428..2747cde8c9a7 100644
--- a/arch/avr32/mach-at32ap/at32ap700x.c
+++ b/arch/avr32/mach-at32ap/at32ap700x.c
@@ -2048,6 +2048,8 @@ at32_add_device_ac97c(unsigned int id, struct ac97c_platform_data *data,
                 rx_dws->reg_width = DW_DMA_SLAVE_WIDTH_16BIT;
                 rx_dws->cfg_hi = DWC_CFGH_SRC_PER(3);
                 rx_dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL);
+                rx_dws->src_master = 0;
+                rx_dws->dst_master = 1;
         }
 
         /* Check if DMA slave interface for playback should be configured. */
@@ -2056,6 +2058,8 @@ at32_add_device_ac97c(unsigned int id, struct ac97c_platform_data *data,
                 tx_dws->reg_width = DW_DMA_SLAVE_WIDTH_16BIT;
                 tx_dws->cfg_hi = DWC_CFGH_DST_PER(4);
                 tx_dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL);
+                rx_dws->src_master = 0;
+                rx_dws->dst_master = 1;
         }
 
         if (platform_device_add_data(pdev, data,
@@ -2128,6 +2132,8 @@ at32_add_device_abdac(unsigned int id, struct atmel_abdac_pdata *data)
         dws->reg_width = DW_DMA_SLAVE_WIDTH_32BIT;
         dws->cfg_hi = DWC_CFGH_DST_PER(2);
         dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL);
+        dws->src_master = 0;
+        dws->dst_master = 1;
 
         if (platform_device_add_data(pdev, data,
                                 sizeof(struct atmel_abdac_pdata)))