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authorBenoit Cousson <b-cousson@ti.com>2011-08-16 05:49:08 -0400
committerBenoit Cousson <b-cousson@ti.com>2011-10-04 16:29:40 -0400
commit476b679a5d785d1244f6b43ad26877acf278cd18 (patch)
treec3f93d9742c4654c9d10af829db1122bac0b6f6f /arch
parentad8dfac66fb1995014060302bda19a15bc62bd6d (diff)
arm/dts: OMAP3+: Add mpu, dsp and iva nodes
Add nodes for devices used by PM code (mpu, dsp, iva). Add a cpus node as well as recommended in the DT spec. Remove mpu, dsp, iva devices init if is populated. Signed-off-by: Benoit Cousson <b-cousson@ti.com> Acked-by: Grant Likely <grant.likely@secretlab.ca> Cc: Kevin Hilman <khilman@ti.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/boot/dts/omap3.dtsi19
-rw-r--r--arch/arm/boot/dts/omap4.dtsi23
-rw-r--r--arch/arm/mach-omap2/pm.c3
3 files changed, 44 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index d558785c8b2c..d202bb5ec7ef 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -13,12 +13,31 @@
13/ { 13/ {
14 compatible = "ti,omap3430", "ti,omap3"; 14 compatible = "ti,omap3430", "ti,omap3";
15 15
16 cpus {
17 cpu@0 {
18 compatible = "arm,cortex-a8";
19 };
20 };
21
16 /* 22 /*
17 * The soc node represents the soc top level view. It is uses for IPs 23 * The soc node represents the soc top level view. It is uses for IPs
18 * that are not memory mapped in the MPU view or for the MPU itself. 24 * that are not memory mapped in the MPU view or for the MPU itself.
19 */ 25 */
20 soc { 26 soc {
21 compatible = "ti,omap-infra"; 27 compatible = "ti,omap-infra";
28 mpu {
29 compatible = "ti,omap3-mpu";
30 ti,hwmods = "mpu";
31 };
32
33 iva {
34 compatible = "ti,iva2.2";
35 ti,hwmods = "iva";
36
37 dsp {
38 compatible = "ti,omap3-c64";
39 };
40 };
22 }; 41 };
23 42
24 /* 43 /*
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index b85a39debbea..4c61c829043a 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -23,12 +23,35 @@
23 aliases { 23 aliases {
24 }; 24 };
25 25
26 cpus {
27 cpu@0 {
28 compatible = "arm,cortex-a9";
29 };
30 cpu@1 {
31 compatible = "arm,cortex-a9";
32 };
33 };
34
26 /* 35 /*
27 * The soc node represents the soc top level view. It is uses for IPs 36 * The soc node represents the soc top level view. It is uses for IPs
28 * that are not memory mapped in the MPU view or for the MPU itself. 37 * that are not memory mapped in the MPU view or for the MPU itself.
29 */ 38 */
30 soc { 39 soc {
31 compatible = "ti,omap-infra"; 40 compatible = "ti,omap-infra";
41 mpu {
42 compatible = "ti,omap4-mpu";
43 ti,hwmods = "mpu";
44 };
45
46 dsp {
47 compatible = "ti,omap3-c64";
48 ti,hwmods = "dsp";
49 };
50
51 iva {
52 compatible = "ti,ivahd";
53 ti,hwmods = "iva";
54 };
32 }; 55 };
33 56
34 /* 57 /*
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 9e78261fbfba..2ab7a9e17fe2 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -215,7 +215,8 @@ static void __init omap4_init_voltages(void)
215 215
216static int __init omap2_common_pm_init(void) 216static int __init omap2_common_pm_init(void)
217{ 217{
218 omap2_init_processor_devices(); 218 if (!of_have_populated_dt())
219 omap2_init_processor_devices();
219 omap_pm_if_init(); 220 omap_pm_if_init();
220 221
221 return 0; 222 return 0;