Merge commit '85082fd7cbe3173198aac0eb5e85ab1edcc6352c' into test-build

Manual fixup of:

	arch/powerpc/Kconfig

615 files changed, 60409 insertions, 19881 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index b786e68914d4..258f1369fb0c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -14,6 +14,8 @@ config ARM
         select HAVE_OPROFILE
         select HAVE_KPROBES if (!XIP_KERNEL)
         select HAVE_KRETPROBES if (HAVE_KPROBES)
+        select HAVE_FTRACE if (!XIP_KERNEL)
+        select HAVE_DYNAMIC_FTRACE if (HAVE_FTRACE)
         help
           The ARM series is a line of low-power-consumption RISC chip designs
           licensed by ARM Ltd and targeted at embedded applications and
@@ -22,6 +24,9 @@ config ARM
           Europe.  There is an ARM Linux project with a web page at
           <http://www.arm.linux.org.uk/>.
 
+config HAVE_PWM
+        bool
+
 config SYS_SUPPORTS_APM_EMULATION
         bool
 
@@ -84,6 +89,11 @@ config STACKTRACE_SUPPORT
         bool
         default y
 
+config HAVE_LATENCYTOP_SUPPORT
+        bool
+        depends on !SMP
+        default y
+
 config LOCKDEP_SUPPORT
         bool
         default y
@@ -147,6 +157,10 @@ config FIQ
 config ARCH_MTD_XIP
         bool
 
+config GENERIC_HARDIRQS_NO__DO_IRQ
+        bool
+        def_bool y
+
 if OPROFILE
 
 config OPROFILE_ARMV6
@@ -232,13 +246,6 @@ config ARCH_CLPS711X
         help
           Support for Cirrus Logic 711x/721x based boards.
 
-config ARCH_CO285
-        bool "Co-EBSA285"
-        select FOOTBRIDGE
-        select FOOTBRIDGE_ADDIN
-        help
-          Support for Intel's EBSA285 companion chip.
-
 config ARCH_EBSA110
         bool "EBSA-110"
         select ISA
@@ -299,6 +306,8 @@ config ARCH_IOP32X
         depends on MMU
         select PLAT_IOP
         select PCI
+        select GENERIC_GPIO
+        select HAVE_GPIO_LIB
         help
           Support for Intel's 80219 and IOP32X (XScale) family of
           processors.
@@ -308,6 +317,8 @@ config ARCH_IOP33X
         depends on MMU
         select PLAT_IOP
         select PCI
+        select GENERIC_GPIO
+        select HAVE_GPIO_LIB
         help
           Support for Intel's IOP33X (XScale) family of processors.
 
@@ -347,6 +358,16 @@ config ARCH_L7200
           If you have any questions or comments about the Linux kernel port
           to this board, send e-mail to <sjhill@cotw.com>.
 
+config ARCH_KIRKWOOD
+        bool "Marvell Kirkwood"
+        select PCI
+        select GENERIC_TIME
+        select GENERIC_CLOCKEVENTS
+        select PLAT_ORION
+        help
+          Support for the following Marvell Kirkwood series SoCs:
+          88F6180, 88F6192 and 88F6281.
+
 config ARCH_KS8695
         bool "Micrel/Kendin KS8695"
         select GENERIC_GPIO
@@ -365,9 +386,31 @@ config ARCH_NS9XXX
 
           <http://www.digi.com/products/microprocessors/index.jsp>
 
+config ARCH_LOKI
+        bool "Marvell Loki (88RC8480)"
+        select GENERIC_TIME
+        select GENERIC_CLOCKEVENTS
+        select PLAT_ORION
+        help
+          Support for the Marvell Loki (88RC8480) SoC.
+
+config ARCH_MV78XX0
+        bool "Marvell MV78xx0"
+        select PCI
+        select GENERIC_TIME
+        select GENERIC_CLOCKEVENTS
+        select PLAT_ORION
+        help
+          Support for the following Marvell MV78xx0 series SoCs:
+          MV781x0, MV782x0.
+
 config ARCH_MXC
         bool "Freescale MXC/iMX-based"
+        select GENERIC_TIME
+        select GENERIC_CLOCKEVENTS
         select ARCH_MTD_XIP
+        select GENERIC_GPIO
+        select HAVE_GPIO_LIB
         help
           Support for Freescale MXC/iMX-based family of processors
 
@@ -381,7 +424,8 @@ config ARCH_ORION5X
         select PLAT_ORION
         help
           Support for the following Marvell Orion 5x series SoCs:
-          Orion-1 (5181), Orion-NAS (5182), Orion-2 (5281.)
+          Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
+          Orion-2 (5281).
 
 config ARCH_PNX4008
         bool "Philips Nexperia PNX4008 Mobile"
@@ -406,6 +450,7 @@ config ARCH_RPC
         select FIQ
         select TIMER_ACORN
         select ARCH_MAY_HAVE_PC_FDC
+        select HAVE_PATA_PLATFORM
         select ISA_DMA_API
         select NO_IOPORT
         help
@@ -502,6 +547,10 @@ source "arch/arm/mach-ixp2000/Kconfig"
 
 source "arch/arm/mach-ixp23xx/Kconfig"
 
+source "arch/arm/mach-loki/Kconfig"
+
+source "arch/arm/mach-mv78xx0/Kconfig"
+
 source "arch/arm/mach-pxa/Kconfig"
 
 source "arch/arm/mach-sa1100/Kconfig"
@@ -514,6 +563,8 @@ source "arch/arm/mach-omap2/Kconfig"
 
 source "arch/arm/mach-orion5x/Kconfig"
 
+source "arch/arm/mach-kirkwood/Kconfig"
+
 source "arch/arm/plat-s3c24xx/Kconfig"
 source "arch/arm/plat-s3c/Kconfig"
 
@@ -703,27 +754,6 @@ config PREEMPT
           Say Y here if you are building a kernel for a desktop, embedded
           or real-time system.  Say N if you are unsure.
 
-config NO_IDLE_HZ
-        bool "Dynamic tick timer"
-        depends on !GENERIC_CLOCKEVENTS
-        help
-          Select this option if you want to disable continuous timer ticks
-          and have them programmed to occur as required. This option saves
-          power as the system can remain in idle state for longer.
-
-          By default dynamic tick is disabled during the boot, and can be
-          manually enabled with:
-
-            echo 1 > /sys/devices/system/timer/timer0/dyn_tick
-
-          Alternatively, if you want dynamic tick automatically enabled
-          during boot, pass "dyntick=enable" via the kernel command string.
-
-          Please note that dynamic tick may affect the accuracy of
-          timekeeping on some platforms depending on the implementation.
-          Currently at least OMAP, PXA2xx and SA11x0 platforms are known
-          to have accurate timekeeping with dynamic tick.
-
 config HZ
         int
         default 128 if ARCH_L7200
@@ -789,7 +819,7 @@ source "mm/Kconfig"
 
 config LEDS
         bool "Timer and CPU usage LEDs"
-        depends on ARCH_CDB89712 || ARCH_CO285 || ARCH_EBSA110 || \
+        depends on ARCH_CDB89712 || ARCH_EBSA110 || \
                    ARCH_EBSA285 || ARCH_IMX || ARCH_INTEGRATOR || \
                    ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
                    ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index e72db27e0ba0..b20995a82e04 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -100,8 +100,6 @@ textofs-y	:= 0x00008000
   incdir-$(CONFIG_ARCH_CLPS7500)   := cl7500
  machine-$(CONFIG_FOOTBRIDGE)      := footbridge
   incdir-$(CONFIG_FOOTBRIDGE)      := ebsa285
- machine-$(CONFIG_ARCH_CO285)      := footbridge
-  incdir-$(CONFIG_ARCH_CO285)      := ebsa285
  machine-$(CONFIG_ARCH_SHARK)      := shark
  machine-$(CONFIG_ARCH_SA1100)     := sa1100
 ifeq ($(CONFIG_ARCH_SA1100),y)
@@ -135,11 +133,15 @@ endif
  machine-$(CONFIG_ARCH_NETX)       := netx
  machine-$(CONFIG_ARCH_NS9XXX)     := ns9xxx
  machine-$(CONFIG_ARCH_DAVINCI)    := davinci
+ machine-$(CONFIG_ARCH_KIRKWOOD)   := kirkwood
  machine-$(CONFIG_ARCH_KS8695)     := ks8695
   incdir-$(CONFIG_ARCH_MXC)        := mxc
+ machine-$(CONFIG_ARCH_MX2)        := mx2
  machine-$(CONFIG_ARCH_MX3)        := mx3
  machine-$(CONFIG_ARCH_ORION5X)    := orion5x
  machine-$(CONFIG_ARCH_MSM7X00A)   := msm
+ machine-$(CONFIG_ARCH_LOKI)       := loki
+ machine-$(CONFIG_ARCH_MV78XX0)    := mv78xx0
 
 ifeq ($(CONFIG_ARCH_EBSA110),y)
 # This is what happens if you forget the IOCS16 line.
@@ -190,8 +192,6 @@ core-$(CONFIG_PLAT_S3C24XX)		+= arch/arm/plat-s3c24xx/
 core-$(CONFIG_ARCH_MXC)         += arch/arm/plat-mxc/
 
 drivers-$(CONFIG_OPROFILE)      += arch/arm/oprofile/
-drivers-$(CONFIG_ARCH_CLPS7500) += drivers/acorn/char/
-drivers-$(CONFIG_ARCH_L7200)    += drivers/acorn/char/
 
 libs-y                          := arch/arm/lib/ $(libs-y)
 
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index de9d9ee50958..95baac4939e0 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -69,6 +69,12 @@ SEDFLAGS	= s/TEXT_START/$(ZTEXTADDR)/;s/BSS_START/$(ZBSSADDR)/
 
 targets       := vmlinux vmlinux.lds piggy.gz piggy.o font.o font.c \
                  head.o misc.o $(OBJS)
+
+ifeq ($(CONFIG_FTRACE),y)
+ORIG_CFLAGS := $(KBUILD_CFLAGS)
+KBUILD_CFLAGS = $(subst -pg, , $(ORIG_CFLAGS))
+endif
+
 EXTRA_CFLAGS  := -fpic -fno-builtin
 EXTRA_AFLAGS  :=
 
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 3c2c8f2a1dc4..de41daeab5e9 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -623,8 +623,8 @@ proc_types:
                 b       __armv4_mmu_cache_off
                 b       __armv4_mmu_cache_flush
 
-                .word   0x56055310              @ Feroceon
-                .word   0xfffffff0
+                .word   0x56050000              @ Feroceon
+                .word   0xff0f0000
                 b       __armv4_mmu_cache_on
                 b       __armv4_mmu_cache_off
                 b       __armv5tej_mmu_cache_flush
diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
index 3d0b9fa42f84..325e4b6a6afb 100644
--- a/arch/arm/common/Makefile
+++ b/arch/arm/common/Makefile
@@ -2,7 +2,6 @@
 # Makefile for the linux kernel.
 #
 
-obj-y                           += rtctime.o
 obj-$(CONFIG_ARM_GIC)           += gic.o
 obj-$(CONFIG_ARM_VIC)           += vic.o
 obj-$(CONFIG_ICST525)           += icst525.o
diff --git a/arch/arm/common/rtctime.c b/arch/arm/common/rtctime.c
deleted file mode 100644
index aa8f7739c822..000000000000
--- a/arch/arm/common/rtctime.c
+++ /dev/null
@@ -1,434 +0,0 @@
-/*
- *  linux/arch/arm/common/rtctime.c
- *
- *  Copyright (C) 2003 Deep Blue Solutions Ltd.
- *  Based on sa1100-rtc.c, Nils Faerber, CIH, Nicolas Pitre.
- *  Based on rtc.c by Paul Gortmaker
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/time.h>
-#include <linux/rtc.h>
-#include <linux/poll.h>
-#include <linux/proc_fs.h>
-#include <linux/miscdevice.h>
-#include <linux/spinlock.h>
-#include <linux/capability.h>
-#include <linux/device.h>
-#include <linux/mutex.h>
-
-#include <asm/rtc.h>
-
-static DECLARE_WAIT_QUEUE_HEAD(rtc_wait);
-static struct fasync_struct *rtc_async_queue;
-
-/*
- * rtc_lock protects rtc_irq_data
- */
-static DEFINE_SPINLOCK(rtc_lock);
-static unsigned long rtc_irq_data;
-
-/*
- * rtc_sem protects rtc_inuse and rtc_ops
- */
-static DEFINE_MUTEX(rtc_mutex);
-static unsigned long rtc_inuse;
-static struct rtc_ops *rtc_ops;
-
-#define rtc_epoch 1900UL
-
-/*
- * Calculate the next alarm time given the requested alarm time mask
- * and the current time.
- */
-void rtc_next_alarm_time(struct rtc_time *next, struct rtc_time *now, struct rtc_time *alrm)
-{
-        unsigned long next_time;
-        unsigned long now_time;
-
-        next->tm_year = now->tm_year;
-        next->tm_mon = now->tm_mon;
-        next->tm_mday = now->tm_mday;
-        next->tm_hour = alrm->tm_hour;
-        next->tm_min = alrm->tm_min;
-        next->tm_sec = alrm->tm_sec;
-
-        rtc_tm_to_time(now, &now_time);
-        rtc_tm_to_time(next, &next_time);
-
-        if (next_time < now_time) {
-                /* Advance one day */
-                next_time += 60 * 60 * 24;
-                rtc_time_to_tm(next_time, next);
-        }
-}
-EXPORT_SYMBOL(rtc_next_alarm_time);
-
-static inline int rtc_arm_read_time(struct rtc_ops *ops, struct rtc_time *tm)
-{
-        memset(tm, 0, sizeof(struct rtc_time));
-        return ops->read_time(tm);
-}
-
-static inline int rtc_arm_set_time(struct rtc_ops *ops, struct rtc_time *tm)
-{
-        int ret;
-
-        ret = rtc_valid_tm(tm);
-        if (ret == 0)
-                ret = ops->set_time(tm);
-
-        return ret;
-}
-
-static inline int rtc_arm_read_alarm(struct rtc_ops *ops, struct rtc_wkalrm *alrm)
-{
-        int ret = -EINVAL;
-        if (ops->read_alarm) {
-                memset(alrm, 0, sizeof(struct rtc_wkalrm));
-                ret = ops->read_alarm(alrm);
-        }
-        return ret;
-}
-
-static inline int rtc_arm_set_alarm(struct rtc_ops *ops, struct rtc_wkalrm *alrm)
-{
-        int ret = -EINVAL;
-        if (ops->set_alarm)
-                ret = ops->set_alarm(alrm);
-        return ret;
-}
-
-void rtc_update(unsigned long num, unsigned long events)
-{
-        spin_lock(&rtc_lock);
-        rtc_irq_data = (rtc_irq_data + (num << 8)) | events;
-        spin_unlock(&rtc_lock);
-
-        wake_up_interruptible(&rtc_wait);
-        kill_fasync(&rtc_async_queue, SIGIO, POLL_IN);
-}
-EXPORT_SYMBOL(rtc_update);
-
-
-static ssize_t
-rtc_read(struct file *file, char __user *buf, size_t count, loff_t *ppos)
-{
-        DECLARE_WAITQUEUE(wait, current);
-        unsigned long data;
-        ssize_t ret;
-
-        if (count < sizeof(unsigned long))
-                return -EINVAL;
-
-        add_wait_queue(&rtc_wait, &wait);
-        do {
-                __set_current_state(TASK_INTERRUPTIBLE);
-
-                spin_lock_irq(&rtc_lock);
-                data = rtc_irq_data;
-                rtc_irq_data = 0;
-                spin_unlock_irq(&rtc_lock);
-
-                if (data != 0) {
-                        ret = 0;
-                        break;
-                }
-                if (file->f_flags & O_NONBLOCK) {
-                        ret = -EAGAIN;
-                        break;
-                }
-                if (signal_pending(current)) {
-                        ret = -ERESTARTSYS;
-                        break;
-                }
-                schedule();
-        } while (1);
-        set_current_state(TASK_RUNNING);
-        remove_wait_queue(&rtc_wait, &wait);
-
-        if (ret == 0) {
-                ret = put_user(data, (unsigned long __user *)buf);
-                if (ret == 0)
-                        ret = sizeof(unsigned long);
-        }
-        return ret;
-}
-
-static unsigned int rtc_poll(struct file *file, poll_table *wait)
-{
-        unsigned long data;
-
-        poll_wait(file, &rtc_wait, wait);
-
-        spin_lock_irq(&rtc_lock);
-        data = rtc_irq_data;
-        spin_unlock_irq(&rtc_lock);
-
-        return data != 0 ? POLLIN | POLLRDNORM : 0;
-}
-
-static int rtc_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
-                     unsigned long arg)
-{
-        struct rtc_ops *ops = file->private_data;
-        struct rtc_time tm;
-        struct rtc_wkalrm alrm;
-        void __user *uarg = (void __user *)arg;
-        int ret = -EINVAL;
-
-        switch (cmd) {
-        case RTC_ALM_READ:
-                ret = rtc_arm_read_alarm(ops, &alrm);
-                if (ret)
-                        break;
-                ret = copy_to_user(uarg, &alrm.time, sizeof(tm));
-                if (ret)
-                        ret = -EFAULT;
-                break;
-
-        case RTC_ALM_SET:
-                ret = copy_from_user(&alrm.time, uarg, sizeof(tm));
-                if (ret) {
-                        ret = -EFAULT;
-                        break;
-                }
-                alrm.enabled = 0;
-                alrm.pending = 0;
-                alrm.time.tm_mday = -1;
-                alrm.time.tm_mon = -1;
-                alrm.time.tm_year = -1;
-                alrm.time.tm_wday = -1;
-                alrm.time.tm_yday = -1;
-                alrm.time.tm_isdst = -1;
-                ret = rtc_arm_set_alarm(ops, &alrm);
-                break;
-
-        case RTC_RD_TIME:
-                ret = rtc_arm_read_time(ops, &tm);
-                if (ret)
-                        break;
-                ret = copy_to_user(uarg, &tm, sizeof(tm));
-                if (ret)
-                        ret = -EFAULT;
-                break;
-
-        case RTC_SET_TIME:
-                if (!capable(CAP_SYS_TIME)) {
-                        ret = -EACCES;
-                        break;
-                }
-                ret = copy_from_user(&tm, uarg, sizeof(tm));
-                if (ret) {
-                        ret = -EFAULT;
-                        break;
-                }
-                ret = rtc_arm_set_time(ops, &tm);
-                break;
-
-        case RTC_EPOCH_SET:
-#ifndef rtc_epoch
-                /*
-                 * There were no RTC clocks before 1900.
-                 */
-                if (arg < 1900) {
-                        ret = -EINVAL;
-                        break;
-                }
-                if (!capable(CAP_SYS_TIME)) {
-                        ret = -EACCES;
-                        break;
-                }
-                rtc_epoch = arg;
-                ret = 0;
-#endif
-                break;
-
-        case RTC_EPOCH_READ:
-                ret = put_user(rtc_epoch, (unsigned long __user *)uarg);
-                break;
-
-        case RTC_WKALM_SET:
-                ret = copy_from_user(&alrm, uarg, sizeof(alrm));
-                if (ret) {
-                        ret = -EFAULT;
-                        break;
-                }
-                ret = rtc_arm_set_alarm(ops, &alrm);
-                break;
-
-        case RTC_WKALM_RD:
-                ret = rtc_arm_read_alarm(ops, &alrm);
-                if (ret)
-                        break;
-                ret = copy_to_user(uarg, &alrm, sizeof(alrm));
-                if (ret)
-                        ret = -EFAULT;
-                break;
-
-        default:
-                if (ops->ioctl)
-                        ret = ops->ioctl(cmd, arg);
-                break;
-        }
-        return ret;
-}
-
-static int rtc_open(struct inode *inode, struct file *file)
-{
-        int ret;
-
-        mutex_lock(&rtc_mutex);
-
-        if (rtc_inuse) {
-                ret = -EBUSY;
-        } else if (!rtc_ops || !try_module_get(rtc_ops->owner)) {
-                ret = -ENODEV;
-        } else {
-                file->private_data = rtc_ops;
-
-                ret = rtc_ops->open ? rtc_ops->open() : 0;
-                if (ret == 0) {
-                        spin_lock_irq(&rtc_lock);
-                        rtc_irq_data = 0;
-                        spin_unlock_irq(&rtc_lock);
-
-                        rtc_inuse = 1;
-                }
-        }
-        mutex_unlock(&rtc_mutex);
-
-        return ret;
-}
-
-static int rtc_release(struct inode *inode, struct file *file)
-{
-        struct rtc_ops *ops = file->private_data;
-
-        if (ops->release)
-                ops->release();
-
-        spin_lock_irq(&rtc_lock);
-        rtc_irq_data = 0;
-        spin_unlock_irq(&rtc_lock);
-
-        module_put(rtc_ops->owner);
-        rtc_inuse = 0;
-
-        return 0;
-}
-
-static int rtc_fasync(int fd, struct file *file, int on)
-{
-        return fasync_helper(fd, file, on, &rtc_async_queue);
-}
-
-static const struct file_operations rtc_fops = {
-        .owner          = THIS_MODULE,
-        .llseek         = no_llseek,
-        .read           = rtc_read,
-        .poll           = rtc_poll,
-        .ioctl          = rtc_ioctl,
-        .open           = rtc_open,
-        .release        = rtc_release,
-        .fasync         = rtc_fasync,
-};
-
-static struct miscdevice rtc_miscdev = {
-        .minor          = RTC_MINOR,
-        .name           = "rtc",
-        .fops           = &rtc_fops,
-};
-
-
-static int rtc_read_proc(char *page, char **start, off_t off, int count, int *eof, void *data)
-{
-        struct rtc_ops *ops = data;
-        struct rtc_wkalrm alrm;
-        struct rtc_time tm;
-        char *p = page;
-
-        if (rtc_arm_read_time(ops, &tm) == 0) {
-                p += sprintf(p,
-                        "rtc_time\t: %02d:%02d:%02d\n"
-                        "rtc_date\t: %04d-%02d-%02d\n"
-                        "rtc_epoch\t: %04lu\n",
-                        tm.tm_hour, tm.tm_min, tm.tm_sec,
-                        tm.tm_year + 1900, tm.tm_mon + 1, tm.tm_mday,
-                        rtc_epoch);
-        }
-
-        if (rtc_arm_read_alarm(ops, &alrm) == 0) {
-                p += sprintf(p, "alrm_time\t: ");
-                if ((unsigned int)alrm.time.tm_hour <= 24)
-                        p += sprintf(p, "%02d:", alrm.time.tm_hour);
-                else
-                        p += sprintf(p, "**:");
-                if ((unsigned int)alrm.time.tm_min <= 59)
-                        p += sprintf(p, "%02d:", alrm.time.tm_min);
-                else
-                        p += sprintf(p, "**:");
-                if ((unsigned int)alrm.time.tm_sec <= 59)
-                        p += sprintf(p, "%02d\n", alrm.time.tm_sec);
-                else
-                        p += sprintf(p, "**\n");
-
-                p += sprintf(p, "alrm_date\t: ");
-                if ((unsigned int)alrm.time.tm_year <= 200)
-                        p += sprintf(p, "%04d-", alrm.time.tm_year + 1900);
-                else
-                        p += sprintf(p, "****-");
-                if ((unsigned int)alrm.time.tm_mon <= 11)
-                        p += sprintf(p, "%02d-", alrm.time.tm_mon + 1);
-                else
-                        p += sprintf(p, "**-");
-                if ((unsigned int)alrm.time.tm_mday <= 31)
-                        p += sprintf(p, "%02d\n", alrm.time.tm_mday);
-                else
-                        p += sprintf(p, "**\n");
-                p += sprintf(p, "alrm_wakeup\t: %s\n",
-                             alrm.enabled ? "yes" : "no");
-                p += sprintf(p, "alrm_pending\t: %s\n",
-                             alrm.pending ? "yes" : "no");
-        }
-
-        if (ops->proc)
-                p += ops->proc(p);
-
-        return p - page;
-}
-
-int register_rtc(struct rtc_ops *ops)
-{
-        int ret = -EBUSY;
-
-        mutex_lock(&rtc_mutex);
-        if (rtc_ops == NULL) {
-                rtc_ops = ops;
-
-                ret = misc_register(&rtc_miscdev);
-                if (ret == 0)
-                        create_proc_read_entry("driver/rtc", 0, NULL,
-                                               rtc_read_proc, ops);
-        }
-        mutex_unlock(&rtc_mutex);
-
-        return ret;
-}
-EXPORT_SYMBOL(register_rtc);
-
-void unregister_rtc(struct rtc_ops *rtc)
-{
-        mutex_lock(&rtc_mutex);
-        if (rtc == rtc_ops) {
-                remove_proc_entry("driver/rtc", NULL);
-                misc_deregister(&rtc_miscdev);
-                rtc_ops = NULL;
-        }
-        mutex_unlock(&rtc_mutex);
-}
-EXPORT_SYMBOL(unregister_rtc);
diff --git a/arch/arm/common/sharpsl_pm.c b/arch/arm/common/sharpsl_pm.c
index 5bba5255b119..8822b684d474 100644
--- a/arch/arm/common/sharpsl_pm.c
+++ b/arch/arm/common/sharpsl_pm.c
@@ -31,6 +31,7 @@
 #include <asm/irq.h>
 #include <asm/arch/pm.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-regs.h>
 #include <asm/arch/sharpsl.h>
 #include <asm/hardware/sharpsl_pm.h>
 
@@ -157,6 +158,7 @@ static void sharpsl_battery_thread(struct work_struct *private_)
         dev_dbg(sharpsl_pm.dev, "Battery: voltage: %d, status: %d, percentage: %d, time: %ld\n", voltage,
                         sharpsl_pm.battstat.mainbat_status, sharpsl_pm.battstat.mainbat_percent, jiffies);
 
+#ifdef CONFIG_BACKLIGHT_CORGI
         /* If battery is low. limit backlight intensity to save power. */
         if ((sharpsl_pm.battstat.ac_status != APM_AC_ONLINE)
                         && ((sharpsl_pm.battstat.mainbat_status == APM_BATTERY_STATUS_LOW) ||
@@ -169,6 +171,7 @@ static void sharpsl_battery_thread(struct work_struct *private_)
                 sharpsl_pm.machinfo->backlight_limit(0);
                 sharpsl_pm.flags &= ~SHARPSL_BL_LIMIT;
         }
+#endif
 
         /* Suspend if critical battery level */
         if ((sharpsl_pm.battstat.ac_status != APM_AC_ONLINE)
diff --git a/arch/arm/configs/at91cap9adk_defconfig b/arch/arm/configs/at91cap9adk_defconfig
index e32e73648129..be2b2f38fd94 100644
--- a/arch/arm/configs/at91cap9adk_defconfig
+++ b/arch/arm/configs/at91cap9adk_defconfig
@@ -213,7 +213,6 @@ CONFIG_CPU_CP15_MMU=y
 #
 # CONFIG_TICK_ONESHOT is not set
 # CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
 CONFIG_AEABI=y
 CONFIG_OABI_COMPAT=y
@@ -907,7 +906,32 @@ CONFIG_USB_MON=y
 #
 # USB Gadget Support
 #
-# CONFIG_USB_GADGET is not set
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+CONFIG_USB_GADGET_ATMEL_USBA=y
+CONFIG_USB_ATMEL_USBA=y
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_PXA2XX is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+# CONFIG_USB_ZERO is not set
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_GADGETFS is not set
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
 CONFIG_MMC=y
 # CONFIG_MMC_DEBUG is not set
 # CONFIG_MMC_UNSAFE_RESUME is not set
@@ -926,7 +950,59 @@ CONFIG_MMC_AT91=y
 # CONFIG_MMC_SPI is not set
 # CONFIG_NEW_LEDS is not set
 CONFIG_RTC_LIB=y
-# CONFIG_RTC_CLASS is not set
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_AT91SAM9=y
+CONFIG_RTC_DRV_AT91SAM9_RTT=0
+CONFIG_RTC_DRV_AT91SAM9_GPBR=0
 
 #
 # File systems
diff --git a/arch/arm/configs/at91rm9200dk_defconfig b/arch/arm/configs/at91rm9200dk_defconfig
index 2dbbbc3d4ac3..868fb7b9530b 100644
--- a/arch/arm/configs/at91rm9200dk_defconfig
+++ b/arch/arm/configs/at91rm9200dk_defconfig
@@ -169,7 +169,6 @@ CONFIG_AT91_CF=y
 # Kernel Features
 #
 # CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
 CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_FLATMEM_MANUAL=y
diff --git a/arch/arm/configs/at91rm9200ek_defconfig b/arch/arm/configs/at91rm9200ek_defconfig
index 6e994f7820c6..de43fc675616 100644
--- a/arch/arm/configs/at91rm9200ek_defconfig
+++ b/arch/arm/configs/at91rm9200ek_defconfig
@@ -160,7 +160,6 @@ CONFIG_ISA_DMA_API=y
 # Kernel Features
 #
 # CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
 CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_FLATMEM_MANUAL=y
diff --git a/arch/arm/configs/at91sam9260ek_defconfig b/arch/arm/configs/at91sam9260ek_defconfig
index f659c938473f..2011adfa6758 100644
--- a/arch/arm/configs/at91sam9260ek_defconfig
+++ b/arch/arm/configs/at91sam9260ek_defconfig
@@ -220,7 +220,6 @@ CONFIG_CPU_CP15_MMU=y
 #
 # CONFIG_TICK_ONESHOT is not set
 # CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
 # CONFIG_AEABI is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/at91sam9261ek_defconfig b/arch/arm/configs/at91sam9261ek_defconfig
index 3802e85f7483..4049768962d2 100644
--- a/arch/arm/configs/at91sam9261ek_defconfig
+++ b/arch/arm/configs/at91sam9261ek_defconfig
@@ -213,7 +213,6 @@ CONFIG_CPU_CP15_MMU=y
 #
 # CONFIG_TICK_ONESHOT is not set
 # CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
 # CONFIG_AEABI is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/at91sam9263ek_defconfig b/arch/arm/configs/at91sam9263ek_defconfig
index 32a0d74e0c89..fa1c5aecb5a8 100644
--- a/arch/arm/configs/at91sam9263ek_defconfig
+++ b/arch/arm/configs/at91sam9263ek_defconfig
@@ -213,7 +213,6 @@ CONFIG_CPU_CP15_MMU=y
 #
 # CONFIG_TICK_ONESHOT is not set
 # CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
 # CONFIG_AEABI is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/em_x270_defconfig b/arch/arm/configs/at91sam9g20ek_defconfig
index 6bea0901bdf0..c06863847364 100644
--- a/arch/arm/configs/em_x270_defconfig
+++ b/arch/arm/configs/at91sam9g20ek_defconfig
@@ -1,13 +1,13 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.22
-# Mon Jul  9 15:18:20 2007
+# Linux kernel version: 2.6.24
+# Tue Jun 10 15:51:52 2008
 #
 CONFIG_ARM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
 CONFIG_GENERIC_GPIO=y
 CONFIG_GENERIC_TIME=y
-# CONFIG_GENERIC_CLOCKEVENTS is not set
+CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_MMU=y
 # CONFIG_NO_IOPORT is not set
 CONFIG_GENERIC_HARDIRQS=y
@@ -22,45 +22,40 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
 CONFIG_ZONE_DMA=y
-CONFIG_ARCH_MTD_XIP=y
 CONFIG_VECTORS_BASE=0xffff0000
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 
 #
-# Code maturity level options
+# General setup
 #
 CONFIG_EXPERIMENTAL=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
-CONFIG_LOCALVERSION="-em-x270"
+CONFIG_LOCALVERSION=""
 # CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_SWAP=y
+# CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
-# CONFIG_IPC_NS is not set
 CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
-# CONFIG_UTS_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
 # CONFIG_AUDIT is not set
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=17
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+# CONFIG_FAIR_GROUP_SCHED is not set
 CONFIG_SYSFS_DEPRECATED=y
 # CONFIG_RELAY is not set
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_SYSCTL=y
-CONFIG_EMBEDDED=y
+# CONFIG_EMBEDDED is not set
 CONFIG_UID16=y
 CONFIG_SYSCTL_SYSCALL=y
 CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_ALL is not set
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
 CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
@@ -71,42 +66,35 @@ CONFIG_FUTEX=y
 CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
 CONFIG_SIGNALFD=y
-CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
 CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
+CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
-
-#
-# Loadable module support
-#
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_KMOD=y
-
-#
-# Block layer
-#
 CONFIG_BLOCK=y
 # CONFIG_LBD is not set
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
 
 #
 # IO Schedulers
 #
 CONFIG_IOSCHED_NOOP=y
 CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
 CONFIG_DEFAULT_AS=y
 # CONFIG_DEFAULT_DEADLINE is not set
 # CONFIG_DEFAULT_CFQ is not set
@@ -120,7 +108,7 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
 # CONFIG_ARCH_INTEGRATOR is not set
 # CONFIG_ARCH_REALVIEW is not set
 # CONFIG_ARCH_VERSATILE is not set
-# CONFIG_ARCH_AT91 is not set
+CONFIG_ARCH_AT91=y
 # CONFIG_ARCH_CLPS7500 is not set
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_CO285 is not set
@@ -139,8 +127,9 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
 # CONFIG_ARCH_L7200 is not set
 # CONFIG_ARCH_KS8695 is not set
 # CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
 # CONFIG_ARCH_PNX4008 is not set
-CONFIG_ARCH_PXA=y
+# CONFIG_ARCH_PXA is not set
 # CONFIG_ARCH_RPC is not set
 # CONFIG_ARCH_SA1100 is not set
 # CONFIG_ARCH_S3C2410 is not set
@@ -150,25 +139,60 @@ CONFIG_ARCH_PXA=y
 # CONFIG_ARCH_OMAP is not set
 
 #
-# Intel PXA2xx Implementations
+# Boot options
+#
+
+#
+# Power management
 #
-# CONFIG_ARCH_LUBBOCK is not set
-# CONFIG_MACH_LOGICPD_PXA270 is not set
-# CONFIG_MACH_MAINSTONE is not set
-# CONFIG_ARCH_PXA_IDP is not set
-# CONFIG_PXA_SHARPSL is not set
-# CONFIG_MACH_TRIZEPS4 is not set
-CONFIG_MACH_EM_X270=y
-CONFIG_PXA27x=y
+
+#
+# Atmel AT91 System-on-Chip
+#
+# CONFIG_ARCH_AT91RM9200 is not set
+# CONFIG_ARCH_AT91SAM9260 is not set
+# CONFIG_ARCH_AT91SAM9261 is not set
+# CONFIG_ARCH_AT91SAM9263 is not set
+# CONFIG_ARCH_AT91SAM9RL is not set
+CONFIG_ARCH_AT91SAM9G20=y
+# CONFIG_ARCH_AT91CAP9 is not set
+# CONFIG_ARCH_AT91X40 is not set
+CONFIG_AT91_PMC_UNIT=y
+
+#
+# AT91SAM9G20 Board Type
+#
+CONFIG_MACH_AT91SAM9G20EK=y
+
+#
+# AT91 Board Options
+#
+# CONFIG_MTD_AT91_DATAFLASH_CARD is not set
+# CONFIG_MTD_NAND_AT91_BUSWIDTH_16 is not set
+
+#
+# AT91 Feature Selections
+#
+CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
+# CONFIG_AT91_SLOW_CLOCK is not set
+CONFIG_AT91_TIMER_HZ=100
+CONFIG_AT91_EARLY_DBGU=y
+# CONFIG_AT91_EARLY_USART0 is not set
+# CONFIG_AT91_EARLY_USART1 is not set
+# CONFIG_AT91_EARLY_USART2 is not set
+# CONFIG_AT91_EARLY_USART3 is not set
+# CONFIG_AT91_EARLY_USART4 is not set
+# CONFIG_AT91_EARLY_USART5 is not set
 
 #
 # Processor Type
 #
 CONFIG_CPU_32=y
-CONFIG_CPU_XSCALE=y
+CONFIG_CPU_ARM926T=y
 CONFIG_CPU_32v5=y
-CONFIG_CPU_ABRT_EV5T=y
+CONFIG_CPU_ABRT_EV5TJ=y
 CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
 CONFIG_CPU_TLB_V4WBI=y
 CONFIG_CPU_CP15=y
 CONFIG_CPU_CP15_MMU=y
@@ -176,28 +200,28 @@ CONFIG_CPU_CP15_MMU=y
 #
 # Processor Features
 #
-CONFIG_ARM_THUMB=y
+# CONFIG_ARM_THUMB is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
 # CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
 # CONFIG_OUTER_CACHE is not set
-CONFIG_IWMMXT=y
-CONFIG_XSCALE_PMU=y
 
 #
 # Bus support
 #
+# CONFIG_PCI_SYSCALL is not set
 # CONFIG_ARCH_SUPPORTS_MSI is not set
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
 # CONFIG_PCCARD is not set
 
 #
 # Kernel Features
 #
 # CONFIG_TICK_ONESHOT is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
 # CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
 CONFIG_AEABI=y
 CONFIG_OABI_COMPAT=y
@@ -209,9 +233,14 @@ CONFIG_FLATMEM_MANUAL=y
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
 # CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
 CONFIG_SPLIT_PTLOCK_CPUS=4096
 # CONFIG_RESOURCES_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_LEDS=y
+CONFIG_LEDS_CPU=y
 CONFIG_ALIGNMENT_TRAP=y
 
 #
@@ -219,7 +248,7 @@ CONFIG_ALIGNMENT_TRAP=y
 #
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE=""
+CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw"
 # CONFIG_XIP_KERNEL is not set
 # CONFIG_KEXEC is not set
 
@@ -233,6 +262,7 @@ CONFIG_CMDLINE=""
 CONFIG_FPE_NWFPE=y
 # CONFIG_FPE_NWFPE_XP is not set
 # CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
 
 #
 # Userspace binary formats
@@ -245,10 +275,12 @@ CONFIG_BINFMT_ELF=y
 # Power management options
 #
 CONFIG_PM=y
-CONFIG_PM_LEGACY=y
+# CONFIG_PM_LEGACY is not set
 # CONFIG_PM_DEBUG is not set
-# CONFIG_PM_SYSFS_DEPRECATED is not set
-CONFIG_APM_EMULATION=m
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND_UP_POSSIBLE=y
+CONFIG_SUSPEND=y
+# CONFIG_APM_EMULATION is not set
 
 #
 # Networking
@@ -261,17 +293,13 @@ CONFIG_NET=y
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
 CONFIG_UNIX=y
-CONFIG_XFRM=y
-# CONFIG_XFRM_USER is not set
-# CONFIG_XFRM_SUB_POLICY is not set
-# CONFIG_XFRM_MIGRATE is not set
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
 # CONFIG_IP_MULTICAST is not set
 # CONFIG_IP_ADVANCED_ROUTER is not set
 CONFIG_IP_FIB_HASH=y
 CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_DHCP is not set
 CONFIG_IP_PNP_BOOTP=y
 # CONFIG_IP_PNP_RARP is not set
 # CONFIG_NET_IPIP is not set
@@ -283,9 +311,10 @@ CONFIG_IP_PNP_BOOTP=y
 # CONFIG_INET_IPCOMP is not set
 # CONFIG_INET_XFRM_TUNNEL is not set
 # CONFIG_INET_TUNNEL is not set
-CONFIG_INET_XFRM_MODE_TRANSPORT=y
-CONFIG_INET_XFRM_MODE_TUNNEL=y
-CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
 CONFIG_INET_DIAG=y
 CONFIG_INET_TCP_DIAG=y
 # CONFIG_TCP_CONG_ADVANCED is not set
@@ -311,10 +340,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
 # CONFIG_NET_SCHED is not set
 
 #
@@ -323,28 +348,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_NET_PKTGEN is not set
 # CONFIG_HAMRADIO is not set
 # CONFIG_IRDA is not set
-CONFIG_BT=m
-CONFIG_BT_L2CAP=m
-CONFIG_BT_SCO=m
-CONFIG_BT_RFCOMM=m
-# CONFIG_BT_RFCOMM_TTY is not set
-CONFIG_BT_BNEP=m
-# CONFIG_BT_BNEP_MC_FILTER is not set
-# CONFIG_BT_BNEP_PROTO_FILTER is not set
-CONFIG_BT_HIDP=m
-
-#
-# Bluetooth device drivers
-#
-CONFIG_BT_HCIUSB=m
-# CONFIG_BT_HCIUSB_SCO is not set
-CONFIG_BT_HCIUART=m
-# CONFIG_BT_HCIUART_H4 is not set
-# CONFIG_BT_HCIUART_BCSP is not set
-CONFIG_BT_HCIBCM203X=m
-CONFIG_BT_HCIBPA10X=m
-CONFIG_BT_HCIBFUSB=m
-# CONFIG_BT_HCIVHCI is not set
+# CONFIG_BT is not set
 # CONFIG_AF_RXRPC is not set
 
 #
@@ -353,13 +357,9 @@ CONFIG_BT_HCIBFUSB=m
 # CONFIG_CFG80211 is not set
 # CONFIG_WIRELESS_EXT is not set
 # CONFIG_MAC80211 is not set
-CONFIG_IEEE80211=m
-# CONFIG_IEEE80211_DEBUG is not set
-CONFIG_IEEE80211_CRYPT_WEP=m
-CONFIG_IEEE80211_CRYPT_CCMP=m
-# CONFIG_IEEE80211_CRYPT_TKIP is not set
-# CONFIG_IEEE80211_SOFTMAC is not set
+# CONFIG_IEEE80211 is not set
 # CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
 
 #
 # Device Drivers
@@ -368,23 +368,18 @@ CONFIG_IEEE80211_CRYPT_CCMP=m
 #
 # Generic Driver Options
 #
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=y
-# CONFIG_DEBUG_DRIVER is not set
-# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_FW_LOADER is not set
 # CONFIG_SYS_HYPERVISOR is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
 # CONFIG_CONNECTOR is not set
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
 CONFIG_MTD_CONCAT=y
 CONFIG_MTD_PARTITIONS=y
 # CONFIG_MTD_REDBOOT_PARTS is not set
-# CONFIG_MTD_CMDLINE_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
 # CONFIG_MTD_AFS_PARTS is not set
 
 #
@@ -398,15 +393,13 @@ CONFIG_MTD_BLOCK=y
 # CONFIG_INFTL is not set
 # CONFIG_RFD_FTL is not set
 # CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
 
 #
 # RAM/ROM/Flash chip drivers
 #
 # CONFIG_MTD_CFI is not set
 # CONFIG_MTD_JEDECPROBE is not set
-# CONFIG_MTD_CFI_NOSWAP is not set
-# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
-# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
 CONFIG_MTD_MAP_BANK_WIDTH_1=y
 CONFIG_MTD_MAP_BANK_WIDTH_2=y
 CONFIG_MTD_MAP_BANK_WIDTH_4=y
@@ -425,12 +418,13 @@ CONFIG_MTD_CFI_I2=y
 # Mapping drivers for chip access
 #
 # CONFIG_MTD_COMPLEX_MAPPINGS is not set
-# CONFIG_MTD_SHARP_SL is not set
 # CONFIG_MTD_PLATRAM is not set
 
 #
 # Self-contained MTD device drivers
 #
+CONFIG_MTD_DATAFLASH=y
+# CONFIG_MTD_M25P80 is not set
 # CONFIG_MTD_SLRAM is not set
 # CONFIG_MTD_PHRAM is not set
 # CONFIG_MTD_MTDRAM is not set
@@ -446,32 +440,23 @@ CONFIG_MTD_NAND=y
 # CONFIG_MTD_NAND_VERIFY_WRITE is not set
 # CONFIG_MTD_NAND_ECC_SMC is not set
 # CONFIG_MTD_NAND_MUSEUM_IDS is not set
-# CONFIG_MTD_NAND_H1900 is not set
 CONFIG_MTD_NAND_IDS=y
 # CONFIG_MTD_NAND_DISKONCHIP is not set
-# CONFIG_MTD_NAND_SHARPSL is not set
+CONFIG_MTD_NAND_AT91=y
+CONFIG_MTD_NAND_AT91_ECC_SOFT=y
+# CONFIG_MTD_NAND_AT91_ECC_HW is not set
+# CONFIG_MTD_NAND_AT91_ECC_NONE is not set
 # CONFIG_MTD_NAND_NANDSIM is not set
-CONFIG_MTD_NAND_PLATFORM=y
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
 # CONFIG_MTD_ONENAND is not set
 
 #
 # UBI - Unsorted block images
 #
 # CONFIG_MTD_UBI is not set
-
-#
-# Parallel port support
-#
 # CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-# CONFIG_PNPACPI is not set
-
-#
-# Block devices
-#
+CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_COW_COMMON is not set
 CONFIG_BLK_DEV_LOOP=y
 # CONFIG_BLK_DEV_CRYPTOLOOP is not set
@@ -479,20 +464,24 @@ CONFIG_BLK_DEV_LOOP=y
 # CONFIG_BLK_DEV_UB is not set
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=12000
+CONFIG_BLK_DEV_RAM_SIZE=8192
 CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
-# CONFIG_IDE is not set
+CONFIG_MISC_DEVICES=y
+CONFIG_ATMEL_PWM=y
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_ATMEL_SSC=y
 
 #
 # SCSI device support
 #
 # CONFIG_RAID_ATTRS is not set
 CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
 # CONFIG_SCSI_TGT is not set
 # CONFIG_SCSI_NETLINK is not set
-# CONFIG_SCSI_PROC_FS is not set
+CONFIG_SCSI_PROC_FS=y
 
 #
 # SCSI support type (disk, tape, CD-ROM)
@@ -507,7 +496,7 @@ CONFIG_BLK_DEV_SD=y
 #
 # Some SCSI devices (e.g. CD jukebox) support multiple LUNs
 #
-# CONFIG_SCSI_MULTI_LUN is not set
+CONFIG_SCSI_MULTI_LUN=y
 # CONFIG_SCSI_CONSTANTS is not set
 # CONFIG_SCSI_LOGGING is not set
 # CONFIG_SCSI_SCAN_ASYNC is not set
@@ -519,39 +508,46 @@ CONFIG_SCSI_WAIT_SCAN=m
 # CONFIG_SCSI_SPI_ATTRS is not set
 # CONFIG_SCSI_FC_ATTRS is not set
 # CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_ATTRS is not set
 # CONFIG_SCSI_SAS_LIBSAS is not set
-
-#
-# SCSI low-level drivers
-#
-# CONFIG_ISCSI_TCP is not set
-# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
 # CONFIG_ATA is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
 # CONFIG_MD is not set
-
-#
-# Network device support
-#
 CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
-# CONFIG_PHYLIB is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
 CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
+CONFIG_MACB=y
+# CONFIG_AX88796 is not set
 # CONFIG_SMC91X is not set
-CONFIG_DM9000=y
-# CONFIG_SMC911X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
 # CONFIG_NETDEV_1000 is not set
 # CONFIG_NETDEV_10000 is not set
 
@@ -568,7 +564,6 @@ CONFIG_DM9000=y
 # CONFIG_USB_KAWETH is not set
 # CONFIG_USB_PEGASUS is not set
 # CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET_MII is not set
 # CONFIG_USB_USBNET is not set
 # CONFIG_WAN is not set
 # CONFIG_PPP is not set
@@ -577,10 +572,6 @@ CONFIG_DM9000=y
 # CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
-
-#
-# ISDN subsystem
-#
 # CONFIG_ISDN is not set
 
 #
@@ -595,10 +586,9 @@ CONFIG_INPUT=y
 #
 CONFIG_INPUT_MOUSEDEV=y
 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=320
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240
 # CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
 CONFIG_INPUT_EVDEV=y
 # CONFIG_INPUT_EVBUG is not set
 
@@ -612,29 +602,18 @@ CONFIG_INPUT_KEYBOARD=y
 # CONFIG_KEYBOARD_XTKBD is not set
 # CONFIG_KEYBOARD_NEWTON is not set
 # CONFIG_KEYBOARD_STOWAWAY is not set
-CONFIG_KEYBOARD_PXA27x=m
-# CONFIG_KEYBOARD_GPIO is not set
+CONFIG_KEYBOARD_GPIO=y
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_INPUT_JOYSTICK is not set
 # CONFIG_INPUT_TABLET is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-# CONFIG_TOUCHSCREEN_GUNZE is not set
-# CONFIG_TOUCHSCREEN_ELO is not set
-# CONFIG_TOUCHSCREEN_MTOUCH is not set
-# CONFIG_TOUCHSCREEN_MK712 is not set
-# CONFIG_TOUCHSCREEN_PENMOUNT is not set
-# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
-# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
-# CONFIG_TOUCHSCREEN_UCB1400 is not set
-# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
 # CONFIG_INPUT_MISC is not set
 
 #
 # Hardware I/O ports
 #
 CONFIG_SERIO=y
-# CONFIG_SERIO_SERPORT is not set
-CONFIG_SERIO_LIBPS2=y
+CONFIG_SERIO_SERPORT=y
 # CONFIG_SERIO_RAW is not set
 # CONFIG_GAMEPORT is not set
 
@@ -655,45 +634,50 @@ CONFIG_HW_CONSOLE=y
 #
 # Non-8250 serial port support
 #
-CONFIG_SERIAL_PXA=y
-CONFIG_SERIAL_PXA_CONSOLE=y
+CONFIG_SERIAL_ATMEL=y
+CONFIG_SERIAL_ATMEL_CONSOLE=y
+# CONFIG_SERIAL_ATMEL_TTYAT is not set
 CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
 CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
+CONFIG_LEGACY_PTY_COUNT=16
 # CONFIG_IPMI_HANDLER is not set
-# CONFIG_WATCHDOG is not set
-CONFIG_HW_RANDOM=m
+CONFIG_HW_RANDOM=y
 # CONFIG_NVRAM is not set
 # CONFIG_R3964 is not set
 # CONFIG_RAW_DRIVER is not set
-
-#
-# TPM devices
-#
 # CONFIG_TCG_TPM is not set
 # CONFIG_I2C is not set
 
 #
 # SPI support
 #
-# CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
 
 #
-# Dallas's 1-wire bus
+# SPI Master Controller Drivers
 #
+CONFIG_SPI_ATMEL=y
+# CONFIG_SPI_BITBANG is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_AT25 is not set
+CONFIG_SPI_SPIDEV=y
+# CONFIG_SPI_TLE62X0 is not set
 # CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
+# CONFIG_WATCHDOG is not set
 
 #
-# Misc devices
+# Sonics Silicon Backplane
 #
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
 
 #
 # Multifunction device drivers
@@ -701,19 +685,6 @@ CONFIG_HW_RANDOM=m
 # CONFIG_MFD_SM501 is not set
 
 #
-# LED devices
-#
-# CONFIG_NEW_LEDS is not set
-
-#
-# LED drivers
-#
-
-#
-# LED Triggers
-#
-
-#
 # Multimedia devices
 #
 # CONFIG_VIDEO_DEV is not set
@@ -723,81 +694,51 @@ CONFIG_HW_RANDOM=m
 #
 # Graphics support
 #
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
 # CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 
 #
 # Display device support
 #
 # CONFIG_DISPLAY_SUPPORT is not set
-# CONFIG_VGASTATE is not set
-CONFIG_FB=y
-# CONFIG_FIRMWARE_EDID is not set
-# CONFIG_FB_DDC is not set
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-# CONFIG_FB_SYS_FILLRECT is not set
-# CONFIG_FB_SYS_COPYAREA is not set
-# CONFIG_FB_SYS_IMAGEBLIT is not set
-# CONFIG_FB_SYS_FOPS is not set
-CONFIG_FB_DEFERRED_IO=y
-# CONFIG_FB_SVGALIB is not set
-# CONFIG_FB_MACMODES is not set
-# CONFIG_FB_BACKLIGHT is not set
-# CONFIG_FB_MODE_HELPERS is not set
-# CONFIG_FB_TILEBLITTING is not set
-
-#
-# Frame buffer hardware drivers
-#
-# CONFIG_FB_S1D13XXX is not set
-CONFIG_FB_PXA=y
-# CONFIG_FB_PXA_PARAMETERS is not set
-# CONFIG_FB_MBX is not set
-# CONFIG_FB_VIRTUAL is not set
 
 #
 # Console display driver support
 #
 # CONFIG_VGA_CONSOLE is not set
 CONFIG_DUMMY_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
-# CONFIG_FONTS is not set
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-CONFIG_LOGO=y
-CONFIG_LOGO_LINUX_MONO=y
-CONFIG_LOGO_LINUX_VGA16=y
-CONFIG_LOGO_LINUX_CLUT224=y
 
 #
 # Sound
 #
-CONFIG_SOUND=m
+CONFIG_SOUND=y
 
 #
 # Advanced Linux Sound Architecture
 #
-CONFIG_SND=m
-CONFIG_SND_TIMER=m
-CONFIG_SND_PCM=m
-# CONFIG_SND_SEQUENCER is not set
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_SEQUENCER=y
+# CONFIG_SND_SEQ_DUMMY is not set
 CONFIG_SND_OSSEMUL=y
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
+CONFIG_SND_MIXER_OSS=y
+CONFIG_SND_PCM_OSS=y
 CONFIG_SND_PCM_OSS_PLUGINS=y
+CONFIG_SND_SEQUENCER_OSS=y
 # CONFIG_SND_DYNAMIC_MINORS is not set
 CONFIG_SND_SUPPORT_OLD_API=y
-CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PROCFS is not set
 # CONFIG_SND_VERBOSE_PRINTK is not set
 # CONFIG_SND_DEBUG is not set
 
 #
 # Generic devices
 #
-CONFIG_SND_AC97_CODEC=m
 # CONFIG_SND_DUMMY is not set
+# CONFIG_SND_VIRMIDI is not set
 # CONFIG_SND_MTPAV is not set
 # CONFIG_SND_SERIAL_U16550 is not set
 # CONFIG_SND_MPU401 is not set
@@ -805,8 +746,13 @@ CONFIG_SND_AC97_CODEC=m
 #
 # ALSA ARM devices
 #
-CONFIG_SND_PXA2XX_PCM=m
-CONFIG_SND_PXA2XX_AC97=m
+# CONFIG_SND_AT91_AC97 is not set
+
+#
+# SPI devices
+#
+CONFIG_SND_AT73C213=y
+CONFIG_SND_AT73C213_TARGET_BITRATE=48000
 
 #
 # USB devices
@@ -820,16 +766,17 @@ CONFIG_SND_PXA2XX_AC97=m
 # CONFIG_SND_SOC is not set
 
 #
-# Open Sound System
+# SoC Audio support for SuperH
 #
-# CONFIG_SOUND_PRIME is not set
-CONFIG_AC97_BUS=m
 
 #
-# HID Devices
+# Open Sound System
 #
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
 CONFIG_HID=y
 # CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
 
 #
 # USB Input Devices
@@ -838,10 +785,7 @@ CONFIG_USB_HID=y
 # CONFIG_USB_HIDINPUT_POWERBOOK is not set
 # CONFIG_HID_FF is not set
 # CONFIG_USB_HIDDEV is not set
-
-#
-# USB support
-#
+CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
 CONFIG_USB_ARCH_HAS_OHCI=y
 # CONFIG_USB_ARCH_HAS_EHCI is not set
@@ -855,6 +799,7 @@ CONFIG_USB_DEVICEFS=y
 # CONFIG_USB_DEVICE_CLASS is not set
 # CONFIG_USB_DYNAMIC_MINORS is not set
 # CONFIG_USB_SUSPEND is not set
+# CONFIG_USB_PERSIST is not set
 # CONFIG_USB_OTG is not set
 
 #
@@ -866,6 +811,7 @@ CONFIG_USB_OHCI_HCD=y
 # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
 CONFIG_USB_OHCI_LITTLE_ENDIAN=y
 # CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
 
 #
 # USB Device Class drivers
@@ -884,6 +830,7 @@ CONFIG_USB_STORAGE=y
 # CONFIG_USB_STORAGE_DEBUG is not set
 # CONFIG_USB_STORAGE_DATAFAB is not set
 # CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
 # CONFIG_USB_STORAGE_DPCM is not set
 # CONFIG_USB_STORAGE_USBAT is not set
 # CONFIG_USB_STORAGE_SDDR09 is not set
@@ -898,7 +845,7 @@ CONFIG_USB_STORAGE=y
 #
 # CONFIG_USB_MDC800 is not set
 # CONFIG_USB_MICROTEK is not set
-# CONFIG_USB_MON is not set
+CONFIG_USB_MON=y
 
 #
 # USB port drivers
@@ -939,26 +886,66 @@ CONFIG_USB_STORAGE=y
 #
 # USB Gadget Support
 #
-# CONFIG_USB_GADGET is not set
-CONFIG_MMC=m
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_PXA2XX is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+CONFIG_USB_GADGET_AT91=y
+CONFIG_USB_AT91=y
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+# CONFIG_USB_GADGET_DUALSPEED is not set
+CONFIG_USB_ZERO=m
+# CONFIG_USB_ETH is not set
+CONFIG_USB_GADGETFS=m
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+CONFIG_USB_G_SERIAL=m
+# CONFIG_USB_MIDI_GADGET is not set
+CONFIG_MMC=y
 # CONFIG_MMC_DEBUG is not set
 # CONFIG_MMC_UNSAFE_RESUME is not set
 
 #
 # MMC/SD Card Drivers
 #
-CONFIG_MMC_BLOCK=m
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
 
 #
 # MMC/SD Host Controller Drivers
 #
-CONFIG_MMC_PXA=m
+CONFIG_MMC_AT91=y
+# CONFIG_MMC_SPI is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
 
 #
-# Real Time Clock
+# LED drivers
 #
+CONFIG_LEDS_ATMEL_PWM=y
+CONFIG_LEDS_GPIO=y
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_RTC_LIB=y
-CONFIG_RTC_CLASS=m
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
 
 #
 # RTC interfaces
@@ -970,26 +957,28 @@ CONFIG_RTC_INTF_DEV=y
 # CONFIG_RTC_DRV_TEST is not set
 
 #
-# I2C RTC drivers
-#
-
-#
 # SPI RTC drivers
 #
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
 
 #
 # Platform RTC drivers
 #
 # CONFIG_RTC_DRV_CMOS is not set
 # CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
 # CONFIG_RTC_DRV_DS1742 is not set
 # CONFIG_RTC_DRV_M48T86 is not set
-CONFIG_RTC_DRV_V3020=m
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_V3020 is not set
 
 #
 # on-CPU RTC drivers
 #
-CONFIG_RTC_DRV_SA1100=m
+CONFIG_RTC_DRV_AT91SAM9=y
+CONFIG_RTC_DRV_AT91SAM9_RTT=0
+CONFIG_RTC_DRV_AT91SAM9_GPBR=0
 
 #
 # File systems
@@ -997,14 +986,8 @@ CONFIG_RTC_DRV_SA1100=m
 CONFIG_EXT2_FS=y
 # CONFIG_EXT2_FS_XATTR is not set
 # CONFIG_EXT2_FS_XIP is not set
-CONFIG_EXT3_FS=y
-CONFIG_EXT3_FS_XATTR=y
-# CONFIG_EXT3_FS_POSIX_ACL is not set
-# CONFIG_EXT3_FS_SECURITY is not set
+# CONFIG_EXT3_FS is not set
 # CONFIG_EXT4DEV_FS is not set
-CONFIG_JBD=y
-# CONFIG_JBD_DEBUG is not set
-CONFIG_FS_MBCACHE=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
@@ -1046,7 +1029,6 @@ CONFIG_SYSFS=y
 CONFIG_TMPFS=y
 # CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
 # CONFIG_CONFIGFS_FS is not set
 
 #
@@ -1062,22 +1044,21 @@ CONFIG_RAMFS=y
 CONFIG_JFFS2_FS=y
 CONFIG_JFFS2_FS_DEBUG=0
 CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
 CONFIG_JFFS2_SUMMARY=y
 # CONFIG_JFFS2_FS_XATTR is not set
 # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
 CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
 CONFIG_JFFS2_RTIME=y
 # CONFIG_JFFS2_RUBIN is not set
-# CONFIG_CRAMFS is not set
+CONFIG_CRAMFS=y
 # CONFIG_VXFS_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
+CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
 # CONFIG_NFS_V3_ACL is not set
@@ -1092,29 +1073,23 @@ CONFIG_SUNRPC=y
 # CONFIG_SUNRPC_BIND34 is not set
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
-CONFIG_SMB_FS=y
-# CONFIG_SMB_NLS_DEFAULT is not set
+# CONFIG_SMB_FS is not set
 # CONFIG_CIFS is not set
 # CONFIG_NCP_FS is not set
 # CONFIG_CODA_FS is not set
 # CONFIG_AFS_FS is not set
-# CONFIG_9P_FS is not set
 
 #
 # Partition Types
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
 CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="iso8859-1"
 CONFIG_NLS_CODEPAGE_437=y
 # CONFIG_NLS_CODEPAGE_737 is not set
 # CONFIG_NLS_CODEPAGE_775 is not set
-# CONFIG_NLS_CODEPAGE_850 is not set
+CONFIG_NLS_CODEPAGE_850=y
 # CONFIG_NLS_CODEPAGE_852 is not set
 # CONFIG_NLS_CODEPAGE_855 is not set
 # CONFIG_NLS_CODEPAGE_857 is not set
@@ -1145,108 +1120,36 @@ CONFIG_NLS_ISO8859_1=y
 # CONFIG_NLS_ISO8859_9 is not set
 # CONFIG_NLS_ISO8859_13 is not set
 # CONFIG_NLS_ISO8859_14 is not set
-# CONFIG_NLS_ISO8859_15 is not set
+CONFIG_NLS_ISO8859_15=y
 # CONFIG_NLS_KOI8_R is not set
 # CONFIG_NLS_KOI8_U is not set
 CONFIG_NLS_UTF8=y
-
-#
-# Distributed Lock Manager
-#
 # CONFIG_DLM is not set
-
-#
-# Profiling support
-#
-# CONFIG_PROFILING is not set
+# CONFIG_INSTRUMENTATION is not set
 
 #
 # Kernel hacking
 #
 # CONFIG_PRINTK_TIME is not set
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
 CONFIG_ENABLE_MUST_CHECK=y
-CONFIG_MAGIC_SYSRQ=y
+# CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_UNUSED_SYMBOLS is not set
 # CONFIG_DEBUG_FS is not set
 # CONFIG_HEADERS_CHECK is not set
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_SHIRQ is not set
-# CONFIG_DETECT_SOFTLOCKUP is not set
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_TIMER_STATS is not set
-# CONFIG_DEBUG_SLAB is not set
-# CONFIG_DEBUG_RT_MUTEXES is not set
-# CONFIG_RT_MUTEX_TESTER is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_MUTEXES is not set
-# CONFIG_DEBUG_LOCK_ALLOC is not set
-# CONFIG_PROVE_LOCKING is not set
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-# CONFIG_DEBUG_KOBJECT is not set
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_INFO=y
-# CONFIG_DEBUG_VM is not set
-# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_KERNEL is not set
+CONFIG_DEBUG_BUGVERBOSE=y
 CONFIG_FRAME_POINTER=y
-CONFIG_FORCED_INLINING=y
-# CONFIG_RCU_TORTURE_TEST is not set
-# CONFIG_FAULT_INJECTION is not set
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_ERRORS=y
-CONFIG_DEBUG_LL=y
-# CONFIG_DEBUG_ICEDCC is not set
+# CONFIG_SAMPLES is not set
+# CONFIG_DEBUG_USER is not set
 
 #
 # Security options
 #
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
-CONFIG_CRYPTO=y
-CONFIG_CRYPTO_ALGAPI=m
-CONFIG_CRYPTO_BLKCIPHER=m
-CONFIG_CRYPTO_MANAGER=m
-# CONFIG_CRYPTO_HMAC is not set
-# CONFIG_CRYPTO_XCBC is not set
-# CONFIG_CRYPTO_NULL is not set
-# CONFIG_CRYPTO_MD4 is not set
-# CONFIG_CRYPTO_MD5 is not set
-# CONFIG_CRYPTO_SHA1 is not set
-# CONFIG_CRYPTO_SHA256 is not set
-# CONFIG_CRYPTO_SHA512 is not set
-# CONFIG_CRYPTO_WP512 is not set
-# CONFIG_CRYPTO_TGR192 is not set
-# CONFIG_CRYPTO_GF128MUL is not set
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_CBC=m
-CONFIG_CRYPTO_PCBC=m
-# CONFIG_CRYPTO_LRW is not set
-# CONFIG_CRYPTO_CRYPTD is not set
-# CONFIG_CRYPTO_DES is not set
-# CONFIG_CRYPTO_FCRYPT is not set
-# CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_TWOFISH is not set
-# CONFIG_CRYPTO_SERPENT is not set
-CONFIG_CRYPTO_AES=m
-# CONFIG_CRYPTO_CAST5 is not set
-# CONFIG_CRYPTO_CAST6 is not set
-# CONFIG_CRYPTO_TEA is not set
-CONFIG_CRYPTO_ARC4=m
-# CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_ANUBIS is not set
-# CONFIG_CRYPTO_DEFLATE is not set
-# CONFIG_CRYPTO_MICHAEL_MIC is not set
-# CONFIG_CRYPTO_CRC32C is not set
-# CONFIG_CRYPTO_CAMELLIA is not set
-# CONFIG_CRYPTO_TEST is not set
-
-#
-# Hardware crypto devices
-#
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_CRYPTO is not set
 
 #
 # Library routines
@@ -1256,10 +1159,10 @@ CONFIG_BITREVERSE=y
 # CONFIG_CRC16 is not set
 # CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
 CONFIG_ZLIB_DEFLATE=y
 CONFIG_PLIST=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
-CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/at91sam9rlek_defconfig b/arch/arm/configs/at91sam9rlek_defconfig
index 98e6746d02be..d8ec5f9ca6ec 100644
--- a/arch/arm/configs/at91sam9rlek_defconfig
+++ b/arch/arm/configs/at91sam9rlek_defconfig
@@ -211,7 +211,6 @@ CONFIG_CPU_CP15_MMU=y
 #
 # CONFIG_TICK_ONESHOT is not set
 # CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
 # CONFIG_AEABI is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/ateb9200_defconfig b/arch/arm/configs/ateb9200_defconfig
index d846a492e5ce..85c80f723d8e 100644
--- a/arch/arm/configs/ateb9200_defconfig
+++ b/arch/arm/configs/ateb9200_defconfig
@@ -171,7 +171,6 @@ CONFIG_AT91_CF=m
 # Kernel Features
 #
 CONFIG_PREEMPT=y
-CONFIG_NO_IDLE_HZ=y
 CONFIG_HZ=100
 # CONFIG_AEABI is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/collie_defconfig b/arch/arm/configs/collie_defconfig
index 4264e273202d..f7622e658163 100644
--- a/arch/arm/configs/collie_defconfig
+++ b/arch/arm/configs/collie_defconfig
@@ -166,7 +166,6 @@ CONFIG_PCMCIA_SA1100=y
 # Kernel Features
 #
 # CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
 # CONFIG_AEABI is not set
 CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
diff --git a/arch/arm/configs/corgi_defconfig b/arch/arm/configs/corgi_defconfig
index e8980a9bb893..9b8748a8d9dd 100644
--- a/arch/arm/configs/corgi_defconfig
+++ b/arch/arm/configs/corgi_defconfig
@@ -165,7 +165,6 @@ CONFIG_PCMCIA_PXA2XX=y
 # Kernel Features
 #
 CONFIG_PREEMPT=y
-# CONFIG_NO_IDLE_HZ is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
 CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_FLATMEM_MANUAL=y
diff --git a/arch/arm/configs/ecbat91_defconfig b/arch/arm/configs/ecbat91_defconfig
index 90ed214e3673..cfeb817ad21a 100644
--- a/arch/arm/configs/ecbat91_defconfig
+++ b/arch/arm/configs/ecbat91_defconfig
@@ -230,7 +230,6 @@ CONFIG_AT91_CF=y
 #
 # CONFIG_TICK_ONESHOT is not set
 CONFIG_PREEMPT=y
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
 # CONFIG_AEABI is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/ep93xx_defconfig b/arch/arm/configs/ep93xx_defconfig
index 24a701ab33e5..21aa013793c6 100644
--- a/arch/arm/configs/ep93xx_defconfig
+++ b/arch/arm/configs/ep93xx_defconfig
@@ -184,7 +184,6 @@ CONFIG_ARM_AMBA=y
 # Kernel Features
 #
 # CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
 # CONFIG_AEABI is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/eseries_pxa_defconfig b/arch/arm/configs/eseries_pxa_defconfig
index ed487b90dbed..493ecee24f94 100644
--- a/arch/arm/configs/eseries_pxa_defconfig
+++ b/arch/arm/configs/eseries_pxa_defconfig
@@ -251,7 +251,6 @@ CONFIG_PCMCIA_PXA2XX=m
 # Kernel Features
 #
 # CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
 CONFIG_AEABI=y
 CONFIG_OABI_COMPAT=y
diff --git a/arch/arm/configs/imx27ads_defconfig b/arch/arm/configs/imx27ads_defconfig
new file mode 100644
index 000000000000..bcd95b8dd2df
--- /dev/null
+++ b/arch/arm/configs/imx27ads_defconfig
@@ -0,0 +1,826 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.26-rc6
+# Fri Jun 20 16:29:34 2008
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_ZONE_DMA=y
+CONFIG_ARCH_MTD_XIP=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+# CONFIG_GROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+# CONFIG_HAVE_DMA_ATTRS is not set
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+# CONFIG_KMOD is not set
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+CONFIG_DEFAULT_NOOP=y
+CONFIG_DEFAULT_IOSCHED="noop"
+CONFIG_CLASSIC_RCU=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+CONFIG_ARCH_MXC=y
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM7X00A is not set
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# Freescale MXC Implementations
+#
+CONFIG_ARCH_MX2=y
+# CONFIG_ARCH_MX3 is not set
+
+#
+# MX2 family CPU support
+#
+CONFIG_MACH_MX27=y
+
+#
+# MX2 Platforms
+#
+CONFIG_MACH_MX27ADS=y
+# CONFIG_MACH_PCM038 is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE=""
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+CONFIG_MTD_CFI_GEOMETRY=y
+# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+# CONFIG_MTD_CFI_I2 is not set
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_OTP is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_XIP is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_START=0x00000000
+CONFIG_MTD_PHYSMAP_LEN=0x0
+CONFIG_MTD_PHYSMAP_BANKWIDTH=2
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+# CONFIG_MII is not set
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+# CONFIG_FEC_OLD is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_UCB1400 is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_IMX is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+CONFIG_HAVE_GPIO_LIB=y
+
+#
+# GPIO Support
+#
+
+#
+# I2C GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_MMC is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_UIO is not set
+
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4DEV_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY is not set
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=m
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+CONFIG_NLS_CODEPAGE_850=m
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+CONFIG_NLS_ISO8859_15=m
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_SAMPLES is not set
+# CONFIG_DEBUG_USER is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_CRYPTO is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+# CONFIG_GENERIC_FIND_NEXT_BIT is not set
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/iop13xx_defconfig b/arch/arm/configs/iop13xx_defconfig
index 988b4d13e76f..482e57061053 100644
--- a/arch/arm/configs/iop13xx_defconfig
+++ b/arch/arm/configs/iop13xx_defconfig
@@ -197,7 +197,6 @@ CONFIG_PCI_LEGACY=y
 #
 # CONFIG_TICK_ONESHOT is not set
 # CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
 # CONFIG_AEABI is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/iop32x_defconfig b/arch/arm/configs/iop32x_defconfig
index 83f40d4041a6..8612f58e1056 100644
--- a/arch/arm/configs/iop32x_defconfig
+++ b/arch/arm/configs/iop32x_defconfig
@@ -201,7 +201,6 @@ CONFIG_PCI_LEGACY=y
 #
 # CONFIG_TICK_ONESHOT is not set
 # CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
 # CONFIG_AEABI is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/iop33x_defconfig b/arch/arm/configs/iop33x_defconfig
index 917afb5ccfac..8b0098d19d08 100644
--- a/arch/arm/configs/iop33x_defconfig
+++ b/arch/arm/configs/iop33x_defconfig
@@ -197,7 +197,6 @@ CONFIG_PCI_LEGACY=y
 #
 # CONFIG_TICK_ONESHOT is not set
 # CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
 # CONFIG_AEABI is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/ixp2000_defconfig b/arch/arm/configs/ixp2000_defconfig
index f8f9793b526f..84680db6c615 100644
--- a/arch/arm/configs/ixp2000_defconfig
+++ b/arch/arm/configs/ixp2000_defconfig
@@ -184,7 +184,6 @@ CONFIG_PCI=y
 # Kernel Features
 #
 # CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
 # CONFIG_AEABI is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/ixp23xx_defconfig b/arch/arm/configs/ixp23xx_defconfig
index 27cf022dd807..4a2f7b2372db 100644
--- a/arch/arm/configs/ixp23xx_defconfig
+++ b/arch/arm/configs/ixp23xx_defconfig
@@ -180,7 +180,6 @@ CONFIG_PCI=y
 # Kernel Features
 #
 # CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
 # CONFIG_AEABI is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/ixp4xx_defconfig b/arch/arm/configs/ixp4xx_defconfig
index efa0485d2f7e..fc14932e3abd 100644
--- a/arch/arm/configs/ixp4xx_defconfig
+++ b/arch/arm/configs/ixp4xx_defconfig
@@ -165,6 +165,7 @@ CONFIG_ARCH_PRPMC1100=y
 CONFIG_MACH_NAS100D=y
 CONFIG_MACH_DSMG600=y
 CONFIG_ARCH_IXDP4XX=y
+CONFIG_MACH_FSG=y
 CONFIG_CPU_IXP46X=y
 CONFIG_CPU_IXP43X=y
 CONFIG_MACH_GTWX5715=y
@@ -770,7 +771,7 @@ CONFIG_ATA=y
 # CONFIG_SATA_SIL24 is not set
 # CONFIG_SATA_SIS is not set
 # CONFIG_SATA_ULI is not set
-# CONFIG_SATA_VIA is not set
+CONFIG_SATA_VIA=y
 # CONFIG_SATA_VITESSE is not set
 # CONFIG_SATA_INIC162X is not set
 # CONFIG_PATA_ALI is not set
@@ -1143,7 +1144,7 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_VIA686A is not set
 # CONFIG_SENSORS_VT1211 is not set
 # CONFIG_SENSORS_VT8231 is not set
-# CONFIG_SENSORS_W83781D is not set
+CONFIG_SENSORS_W83781D=y
 # CONFIG_SENSORS_W83791D is not set
 # CONFIG_SENSORS_W83792D is not set
 # CONFIG_SENSORS_W83793 is not set
@@ -1334,8 +1335,8 @@ CONFIG_LEDS_CLASS=y
 #
 # LED drivers
 #
-# CONFIG_LEDS_IXP4XX is not set
 CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_FSG=y
 
 #
 # LED Triggers
@@ -1367,7 +1368,7 @@ CONFIG_RTC_INTF_DEV=y
 # CONFIG_RTC_DRV_DS1672 is not set
 # CONFIG_RTC_DRV_MAX6900 is not set
 # CONFIG_RTC_DRV_RS5C372 is not set
-# CONFIG_RTC_DRV_ISL1208 is not set
+CONFIG_RTC_DRV_ISL1208=y
 CONFIG_RTC_DRV_X1205=y
 CONFIG_RTC_DRV_PCF8563=y
 # CONFIG_RTC_DRV_PCF8583 is not set
diff --git a/arch/arm/configs/kafa_defconfig b/arch/arm/configs/kafa_defconfig
index ae51a40db6f9..6dd95a2c8d5d 100644
--- a/arch/arm/configs/kafa_defconfig
+++ b/arch/arm/configs/kafa_defconfig
@@ -162,7 +162,6 @@ CONFIG_CPU_TLB_V4WBI=y
 # Kernel Features
 #
 CONFIG_PREEMPT=y
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
 # CONFIG_AEABI is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/kb9202_defconfig b/arch/arm/configs/kb9202_defconfig
index c16537d9d67a..8e74c66f239d 100644
--- a/arch/arm/configs/kb9202_defconfig
+++ b/arch/arm/configs/kb9202_defconfig
@@ -126,7 +126,6 @@ CONFIG_ISA_DMA_API=y
 #
 # Kernel Features
 #
-# CONFIG_NO_IDLE_HZ is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig
new file mode 100644
index 000000000000..e3357ba10f1f
--- /dev/null
+++ b/arch/arm/configs/kirkwood_defconfig
@@ -0,0 +1,1426 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.26-rc5
+# Sun Jun 22 15:51:25 2008
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_ZONE_DMA=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+# CONFIG_MARKERS is not set
+CONFIG_OPROFILE=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_KPROBES=y
+CONFIG_KRETPROBES=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+# CONFIG_HAVE_DMA_ATTRS is not set
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+# CONFIG_KMOD is not set
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_CLASSIC_RCU=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+CONFIG_ARCH_KIRKWOOD=y
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM7X00A is not set
+
+#
+# Marvell Kirkwood Implementations
+#
+CONFIG_MACH_DB88F6281_BP=y
+CONFIG_MACH_RD88F6192_NAS=y
+CONFIG_MACH_RD88F6281=y
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+CONFIG_PLAT_ORION=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_FEROCEON=y
+# CONFIG_CPU_FEROCEON_OLD_ID is not set
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5T=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_FEROCEON=y
+CONFIG_CPU_TLB_FEROCEON=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+CONFIG_OUTER_CACHE=y
+CONFIG_CACHE_FEROCEON_L2=y
+
+#
+# Bus support
+#
+CONFIG_PCI=y
+CONFIG_PCI_SYSCALL=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_PCI_LEGACY=y
+# CONFIG_PCI_DEBUG is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE=""
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+CONFIG_NET_PKTGEN=m
+# CONFIG_NET_TCPPROBE is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_EXT=y
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+CONFIG_MTD_CFI_GEOMETRY=y
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_OTP is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_START=0x0
+CONFIG_MTD_PHYSMAP_LEN=0x0
+CONFIG_MTD_PHYSMAP_BANKWIDTH=0
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_IMPA7 is not set
+# CONFIG_MTD_INTEL_VR_NOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_DATAFLASH is not set
+CONFIG_MTD_M25P80=y
+CONFIG_M25PXX_USE_FAST_READ=y
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_VERIFY_WRITE=y
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_CAFE is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+CONFIG_MTD_NAND_ORION=y
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+# CONFIG_BLK_DEV_UB is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_SCSI_PROC_FS is not set
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SR=m
+# CONFIG_BLK_DEV_SR_VENDOR is not set
+CONFIG_CHR_DEV_SG=m
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_3W_9XXX is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_AIC94XX is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_ARCMSR is not set
+# CONFIG_MEGARAID_NEWGEN is not set
+# CONFIG_MEGARAID_LEGACY is not set
+# CONFIG_MEGARAID_SAS is not set
+# CONFIG_SCSI_HPTIOP is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_IPS is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_MVSAS is not set
+# CONFIG_SCSI_STEX is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
+# CONFIG_SCSI_IPR is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLA_FC is not set
+# CONFIG_SCSI_QLA_ISCSI is not set
+# CONFIG_SCSI_LPFC is not set
+# CONFIG_SCSI_DC395x is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_NSP32 is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_SRP is not set
+CONFIG_ATA=y
+# CONFIG_ATA_NONSTANDARD is not set
+CONFIG_SATA_PMP=y
+# CONFIG_SATA_AHCI is not set
+# CONFIG_SATA_SIL24 is not set
+CONFIG_ATA_SFF=y
+# CONFIG_SATA_SVW is not set
+# CONFIG_ATA_PIIX is not set
+CONFIG_SATA_MV=y
+# CONFIG_SATA_NV is not set
+# CONFIG_PDC_ADMA is not set
+# CONFIG_SATA_QSTOR is not set
+# CONFIG_SATA_PROMISE is not set
+# CONFIG_SATA_SX4 is not set
+# CONFIG_SATA_SIL is not set
+# CONFIG_SATA_SIS is not set
+# CONFIG_SATA_ULI is not set
+# CONFIG_SATA_VIA is not set
+# CONFIG_SATA_VITESSE is not set
+# CONFIG_SATA_INIC162X is not set
+# CONFIG_PATA_ALI is not set
+# CONFIG_PATA_AMD is not set
+# CONFIG_PATA_ARTOP is not set
+# CONFIG_PATA_ATIIXP is not set
+# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_CMD64X is not set
+# CONFIG_PATA_CS5520 is not set
+# CONFIG_PATA_CS5530 is not set
+# CONFIG_PATA_CYPRESS is not set
+# CONFIG_PATA_EFAR is not set
+# CONFIG_ATA_GENERIC is not set
+# CONFIG_PATA_HPT366 is not set
+# CONFIG_PATA_HPT37X is not set
+# CONFIG_PATA_HPT3X2N is not set
+# CONFIG_PATA_HPT3X3 is not set
+# CONFIG_PATA_IT821X is not set
+# CONFIG_PATA_IT8213 is not set
+# CONFIG_PATA_JMICRON is not set
+# CONFIG_PATA_TRIFLEX is not set
+# CONFIG_PATA_MARVELL is not set
+# CONFIG_PATA_MPIIX is not set
+# CONFIG_PATA_OLDPIIX is not set
+# CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
+# CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_NS87415 is not set
+# CONFIG_PATA_OPTI is not set
+# CONFIG_PATA_OPTIDMA is not set
+# CONFIG_PATA_PDC_OLD is not set
+# CONFIG_PATA_RADISYS is not set
+# CONFIG_PATA_RZ1000 is not set
+# CONFIG_PATA_SC1200 is not set
+# CONFIG_PATA_SERVERWORKS is not set
+# CONFIG_PATA_PDC2027X is not set
+# CONFIG_PATA_SIL680 is not set
+# CONFIG_PATA_SIS is not set
+# CONFIG_PATA_VIA is not set
+# CONFIG_PATA_WINBOND is not set
+# CONFIG_PATA_PLATFORM is not set
+# CONFIG_PATA_SCH is not set
+# CONFIG_MD is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_IEEE1394 is not set
+# CONFIG_I2O is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_ARCNET is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_ENC28J60 is not set
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_AMD8111_ETH is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_B44 is not set
+# CONFIG_FORCEDETH is not set
+# CONFIG_EEPRO100 is not set
+# CONFIG_E100 is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+# CONFIG_8139CP is not set
+# CONFIG_8139TOO is not set
+# CONFIG_R6040 is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_SC92031 is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+CONFIG_E1000=y
+CONFIG_E1000_NAPI=y
+# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
+# CONFIG_E1000E is not set
+# CONFIG_E1000E_ENABLED is not set
+# CONFIG_IP1000 is not set
+# CONFIG_IGB is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+CONFIG_MV643XX_ETH=y
+# CONFIG_QLA3XXX is not set
+# CONFIG_ATL1 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_TR is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NET_FC is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_DEVKMEM is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_SERIAL_8250_PCI is not set
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=2
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=16
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_I810 is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_PROSAVAGE is not set
+# CONFIG_I2C_SAVAGE4 is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_TINY_USB is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+# CONFIG_I2C_VOODOO3 is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+CONFIG_I2C_MV64XXX=y
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_BITBANG is not set
+CONFIG_SPI_ORION=y
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_AT25 is not set
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_PASIC3 is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_USB_HIDINPUT_POWERBOOK is not set
+# CONFIG_HID_FF is not set
+# CONFIG_USB_HIDDEV is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_EHCI_TT_NEWSCHED=y
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_OHCI_HCD is not set
+# CONFIG_USB_UHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+CONFIG_USB_PRINTER=y
+# CONFIG_USB_WDM is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+CONFIG_USB_STORAGE_DATAFAB=y
+CONFIG_USB_STORAGE_FREECOM=y
+# CONFIG_USB_STORAGE_ISD200 is not set
+CONFIG_USB_STORAGE_DPCM=y
+# CONFIG_USB_STORAGE_USBAT is not set
+CONFIG_USB_STORAGE_SDDR09=y
+CONFIG_USB_STORAGE_SDDR55=y
+CONFIG_USB_STORAGE_JUMPSHOT=y
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_MON is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_GADGET is not set
+# CONFIG_MMC is not set
+CONFIG_NEW_LEDS=y
+# CONFIG_LEDS_CLASS is not set
+
+#
+# LED drivers
+#
+
+#
+# LED Triggers
+#
+# CONFIG_LEDS_TRIGGERS is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+CONFIG_RTC_DRV_MV=y
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_DMADEVICES=y
+
+#
+# DMA Devices
+#
+CONFIG_MV_XOR=y
+CONFIG_DMA_ENGINE=y
+
+#
+# DMA Clients
+#
+# CONFIG_NET_DMA is not set
+# CONFIG_UIO is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+CONFIG_XFS_FS=y
+# CONFIG_XFS_QUOTA is not set
+# CONFIG_XFS_POSIX_ACL is not set
+# CONFIG_XFS_RT is not set
+# CONFIG_XFS_DEBUG is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+# CONFIG_ZISOFS is not set
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+CONFIG_NLS_CODEPAGE_850=y
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=y
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=y
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_KPROBES_SANITY_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_LKDTM is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SAMPLES is not set
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_ASYNC_CORE=y
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=m
+CONFIG_CRYPTO_BLKCIPHER=m
+CONFIG_CRYPTO_MANAGER=m
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=m
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=m
+# CONFIG_CRYPTO_LRW is not set
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_DEV_HIFN_795X is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+# CONFIG_GENERIC_FIND_NEXT_BIT is not set
+CONFIG_CRC_CCITT=y
+CONFIG_CRC16=y
+CONFIG_CRC_ITU_T=m
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+CONFIG_LIBCRC32C=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/ks8695_defconfig b/arch/arm/configs/ks8695_defconfig
index 8ab21a0719e9..6077f2cb88e4 100644
--- a/arch/arm/configs/ks8695_defconfig
+++ b/arch/arm/configs/ks8695_defconfig
@@ -174,7 +174,6 @@ CONFIG_PCCARD_NONSTATIC=y
 # Kernel Features
 #
 # CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
 # CONFIG_AEABI is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/loki_defconfig b/arch/arm/configs/loki_defconfig
new file mode 100644
index 000000000000..17da7c3b3d53
--- /dev/null
+++ b/arch/arm/configs/loki_defconfig
@@ -0,0 +1,1147 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.26-rc5
+# Fri Jun 13 03:07:49 2008
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+# CONFIG_GENERIC_GPIO is not set
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_ZONE_DMA=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+# CONFIG_HAVE_DMA_ATTRS is not set
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+# CONFIG_KMOD is not set
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_CLASSIC_RCU=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+CONFIG_ARCH_LOKI=y
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM7X00A is not set
+
+#
+# Marvell Loki (88RC8480) Implementations
+#
+CONFIG_MACH_LB88RC8480=y
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+CONFIG_PLAT_ORION=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_FEROCEON=y
+# CONFIG_CPU_FEROCEON_OLD_ID is not set
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5T=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_FEROCEON=y
+CONFIG_CPU_TLB_FEROCEON=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE=""
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+# CONFIG_FPE_NWFPE is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+CONFIG_NET_PKTGEN=m
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_EXT=y
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_FTL=y
+CONFIG_NFTL=y
+# CONFIG_NFTL_RW is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+CONFIG_MTD_CFI_GEOMETRY=y
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+CONFIG_MTD_CFI_I4=y
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_OTP is not set
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_START=0x0
+CONFIG_MTD_PHYSMAP_LEN=0x0
+CONFIG_MTD_PHYSMAP_BANKWIDTH=0
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_IMPA7 is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_DATAFLASH is not set
+CONFIG_MTD_M25P80=y
+CONFIG_M25PXX_USE_FAST_READ=y
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_VERIFY_WRITE=y
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+CONFIG_MTD_NAND_ORION=y
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_SCSI_PROC_FS is not set
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SR=m
+# CONFIG_BLK_DEV_SR_VENDOR is not set
+CONFIG_CHR_DEV_SG=m
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_SCSI_DEBUG is not set
+CONFIG_ATA=y
+# CONFIG_ATA_NONSTANDARD is not set
+CONFIG_SATA_PMP=y
+CONFIG_ATA_SFF=y
+CONFIG_SATA_MV=y
+# CONFIG_PATA_PLATFORM is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_ENC28J60 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_E1000E_ENABLED is not set
+CONFIG_MV643XX_ETH=y
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=2
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=16
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=m
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_TINY_USB is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+CONFIG_I2C_MV64XXX=y
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_BITBANG is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_AT25 is not set
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_PASIC3 is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_USB_HIDINPUT_POWERBOOK is not set
+# CONFIG_HID_FF is not set
+# CONFIG_USB_HIDDEV is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+CONFIG_USB_PRINTER=y
+# CONFIG_USB_WDM is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+CONFIG_USB_STORAGE_DATAFAB=y
+CONFIG_USB_STORAGE_FREECOM=y
+# CONFIG_USB_STORAGE_ISD200 is not set
+CONFIG_USB_STORAGE_DPCM=y
+# CONFIG_USB_STORAGE_USBAT is not set
+CONFIG_USB_STORAGE_SDDR09=y
+CONFIG_USB_STORAGE_SDDR55=y
+CONFIG_USB_STORAGE_JUMPSHOT=y
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_MON is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_GADGET is not set
+# CONFIG_MMC is not set
+CONFIG_NEW_LEDS=y
+# CONFIG_LEDS_CLASS is not set
+
+#
+# LED drivers
+#
+
+#
+# LED Triggers
+#
+# CONFIG_LEDS_TRIGGERS is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_UIO is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+CONFIG_XFS_FS=y
+# CONFIG_XFS_QUOTA is not set
+# CONFIG_XFS_POSIX_ACL is not set
+# CONFIG_XFS_RT is not set
+# CONFIG_XFS_DEBUG is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=y
+# CONFIG_JOLIET is not set
+# CONFIG_ZISOFS is not set
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_BSD_DISKLABEL=y
+CONFIG_MINIX_SUBPARTITION=y
+CONFIG_SOLARIS_X86_PARTITION=y
+CONFIG_UNIXWARE_DISKLABEL=y
+CONFIG_LDM_PARTITION=y
+CONFIG_LDM_DEBUG=y
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+CONFIG_SUN_PARTITION=y
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+CONFIG_NLS_CODEPAGE_850=y
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=y
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SAMPLES is not set
+CONFIG_DEBUG_USER=y
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=m
+CONFIG_CRYPTO_BLKCIPHER=m
+CONFIG_CRYPTO_MANAGER=m
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=m
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=m
+# CONFIG_CRYPTO_LRW is not set
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_HW=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+# CONFIG_GENERIC_FIND_NEXT_BIT is not set
+CONFIG_CRC_CCITT=y
+CONFIG_CRC16=y
+CONFIG_CRC_ITU_T=m
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+CONFIG_LIBCRC32C=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/lpd270_defconfig b/arch/arm/configs/lpd270_defconfig
index a3bf5833b87a..1a38d8e3fe66 100644
--- a/arch/arm/configs/lpd270_defconfig
+++ b/arch/arm/configs/lpd270_defconfig
@@ -173,7 +173,6 @@ CONFIG_XSCALE_PMU=y
 # Kernel Features
 #
 # CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
 # CONFIG_AEABI is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/lpd7a404_defconfig b/arch/arm/configs/lpd7a404_defconfig
index 46a0f7fe1fa5..7a2e932da1c6 100644
--- a/arch/arm/configs/lpd7a404_defconfig
+++ b/arch/arm/configs/lpd7a404_defconfig
@@ -148,7 +148,6 @@ CONFIG_ARM_AMBA=y
 # Kernel Features
 #
 CONFIG_PREEMPT=y
-# CONFIG_NO_IDLE_HZ is not set
 # CONFIG_AEABI is not set
 CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
 CONFIG_SELECT_MEMORY_MODEL=y
diff --git a/arch/arm/configs/mv78xx0_defconfig b/arch/arm/configs/mv78xx0_defconfig
new file mode 100644
index 000000000000..d38ebf8721a4
--- /dev/null
+++ b/arch/arm/configs/mv78xx0_defconfig
@@ -0,0 +1,1445 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.26-rc5
+# Fri Jun 13 02:57:32 2008
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+# CONFIG_GENERIC_GPIO is not set
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_ZONE_DMA=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+# CONFIG_GROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+# CONFIG_MARKERS is not set
+CONFIG_OPROFILE=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_KPROBES=y
+CONFIG_KRETPROBES=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+# CONFIG_HAVE_DMA_ATTRS is not set
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+# CONFIG_KMOD is not set
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_CLASSIC_RCU=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_LOKI is not set
+CONFIG_ARCH_MV78XX0=y
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM7X00A is not set
+
+#
+# Marvell MV78xx0 Implementations
+#
+CONFIG_MACH_DB78X00_BP=y
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+CONFIG_PLAT_ORION=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_FEROCEON=y
+CONFIG_CPU_FEROCEON_OLD_ID=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5T=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_FEROCEON=y
+CONFIG_CPU_TLB_FEROCEON=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+CONFIG_OUTER_CACHE=y
+CONFIG_CACHE_FEROCEON_L2=y
+
+#
+# Bus support
+#
+CONFIG_PCI=y
+CONFIG_PCI_SYSCALL=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_PCI_LEGACY=y
+# CONFIG_PCI_DEBUG is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE=""
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+CONFIG_VFP=y
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+CONFIG_NET_PKTGEN=m
+# CONFIG_NET_TCPPROBE is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_EXT=y
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+CONFIG_MTD_CFI_GEOMETRY=y
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_OTP is not set
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_START=0x0
+CONFIG_MTD_PHYSMAP_LEN=0x0
+CONFIG_MTD_PHYSMAP_BANKWIDTH=0
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_IMPA7 is not set
+# CONFIG_MTD_INTEL_VR_NOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_VERIFY_WRITE=y
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_CAFE is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+CONFIG_MTD_NAND_ORION=y
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+# CONFIG_BLK_DEV_UB is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_PHANTOM is not set
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_SGI_IOC4 is not set
+# CONFIG_TIFM_CORE is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_SCSI_PROC_FS is not set
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SR=m
+# CONFIG_BLK_DEV_SR_VENDOR is not set
+CONFIG_CHR_DEV_SG=m
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_3W_9XXX is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_AIC94XX is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_ARCMSR is not set
+# CONFIG_MEGARAID_NEWGEN is not set
+# CONFIG_MEGARAID_LEGACY is not set
+# CONFIG_MEGARAID_SAS is not set
+# CONFIG_SCSI_HPTIOP is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_IPS is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_MVSAS is not set
+# CONFIG_SCSI_STEX is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
+# CONFIG_SCSI_IPR is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLA_FC is not set
+# CONFIG_SCSI_QLA_ISCSI is not set
+# CONFIG_SCSI_LPFC is not set
+# CONFIG_SCSI_DC395x is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_NSP32 is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_SRP is not set
+CONFIG_ATA=y
+# CONFIG_ATA_NONSTANDARD is not set
+CONFIG_SATA_PMP=y
+# CONFIG_SATA_AHCI is not set
+# CONFIG_SATA_SIL24 is not set
+CONFIG_ATA_SFF=y
+# CONFIG_SATA_SVW is not set
+# CONFIG_ATA_PIIX is not set
+CONFIG_SATA_MV=y
+# CONFIG_SATA_NV is not set
+# CONFIG_PDC_ADMA is not set
+# CONFIG_SATA_QSTOR is not set
+# CONFIG_SATA_PROMISE is not set
+# CONFIG_SATA_SX4 is not set
+# CONFIG_SATA_SIL is not set
+# CONFIG_SATA_SIS is not set
+# CONFIG_SATA_ULI is not set
+# CONFIG_SATA_VIA is not set
+# CONFIG_SATA_VITESSE is not set
+# CONFIG_SATA_INIC162X is not set
+# CONFIG_PATA_ALI is not set
+# CONFIG_PATA_AMD is not set
+# CONFIG_PATA_ARTOP is not set
+# CONFIG_PATA_ATIIXP is not set
+# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_CMD64X is not set
+# CONFIG_PATA_CS5520 is not set
+# CONFIG_PATA_CS5530 is not set
+# CONFIG_PATA_CYPRESS is not set
+# CONFIG_PATA_EFAR is not set
+# CONFIG_ATA_GENERIC is not set
+# CONFIG_PATA_HPT366 is not set
+# CONFIG_PATA_HPT37X is not set
+# CONFIG_PATA_HPT3X2N is not set
+# CONFIG_PATA_HPT3X3 is not set
+# CONFIG_PATA_IT821X is not set
+# CONFIG_PATA_IT8213 is not set
+# CONFIG_PATA_JMICRON is not set
+# CONFIG_PATA_TRIFLEX is not set
+# CONFIG_PATA_MARVELL is not set
+# CONFIG_PATA_MPIIX is not set
+# CONFIG_PATA_OLDPIIX is not set
+# CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
+# CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_NS87415 is not set
+# CONFIG_PATA_OPTI is not set
+# CONFIG_PATA_OPTIDMA is not set
+# CONFIG_PATA_PDC_OLD is not set
+# CONFIG_PATA_RADISYS is not set
+# CONFIG_PATA_RZ1000 is not set
+# CONFIG_PATA_SC1200 is not set
+# CONFIG_PATA_SERVERWORKS is not set
+# CONFIG_PATA_PDC2027X is not set
+# CONFIG_PATA_SIL680 is not set
+# CONFIG_PATA_SIS is not set
+# CONFIG_PATA_VIA is not set
+# CONFIG_PATA_WINBOND is not set
+# CONFIG_PATA_PLATFORM is not set
+# CONFIG_PATA_SCH is not set
+# CONFIG_MD is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_IEEE1394 is not set
+# CONFIG_I2O is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_ARCNET is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_AMD8111_ETH is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_B44 is not set
+# CONFIG_FORCEDETH is not set
+# CONFIG_EEPRO100 is not set
+# CONFIG_E100 is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+# CONFIG_8139CP is not set
+# CONFIG_8139TOO is not set
+# CONFIG_R6040 is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_SC92031 is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_E1000E is not set
+# CONFIG_E1000E_ENABLED is not set
+# CONFIG_IP1000 is not set
+# CONFIG_IGB is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+CONFIG_MV643XX_ETH=y
+# CONFIG_QLA3XXX is not set
+# CONFIG_ATL1 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_TR is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NET_FC is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_SERIAL_8250_PCI is not set
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=2
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=16
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_I810 is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_PROSAVAGE is not set
+# CONFIG_I2C_SAVAGE4 is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_TINY_USB is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+# CONFIG_I2C_VOODOO3 is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+CONFIG_I2C_MV64XXX=y
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+# CONFIG_SPI is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_I5K_AMB is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_SIS5595 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_VIA686A is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_VT8231 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_PASIC3 is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_USB_HIDINPUT_POWERBOOK is not set
+# CONFIG_HID_FF is not set
+# CONFIG_USB_HIDDEV is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_EHCI_TT_NEWSCHED=y
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_OHCI_HCD is not set
+# CONFIG_USB_UHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+CONFIG_USB_PRINTER=y
+# CONFIG_USB_WDM is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+CONFIG_USB_STORAGE_DATAFAB=y
+CONFIG_USB_STORAGE_FREECOM=y
+# CONFIG_USB_STORAGE_ISD200 is not set
+CONFIG_USB_STORAGE_DPCM=y
+# CONFIG_USB_STORAGE_USBAT is not set
+CONFIG_USB_STORAGE_SDDR09=y
+CONFIG_USB_STORAGE_SDDR55=y
+CONFIG_USB_STORAGE_JUMPSHOT=y
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_MON is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_GADGET is not set
+# CONFIG_MMC is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+CONFIG_RTC_DRV_DS1307=y
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+CONFIG_RTC_DRV_RS5C372=y
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+CONFIG_RTC_DRV_M41T80=y
+# CONFIG_RTC_DRV_M41T80_WDT is not set
+# CONFIG_RTC_DRV_S35390A is not set
+
+#
+# SPI RTC drivers
+#
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_UIO is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+# CONFIG_ZISOFS is not set
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_BSD_DISKLABEL=y
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+CONFIG_NLS_CODEPAGE_850=y
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=y
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
+CONFIG_SCHEDSTATS=y
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+CONFIG_DEBUG_PREEMPT=y
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_KPROBES_SANITY_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_LKDTM is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SAMPLES is not set
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=m
+CONFIG_CRYPTO_BLKCIPHER=m
+CONFIG_CRYPTO_MANAGER=m
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=m
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=m
+# CONFIG_CRYPTO_LRW is not set
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_DEV_HIFN_795X is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+# CONFIG_GENERIC_FIND_NEXT_BIT is not set
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+CONFIG_CRC_ITU_T=m
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/mx31ads_defconfig b/arch/arm/configs/mx31ads_defconfig
new file mode 100644
index 000000000000..e05271753e15
--- /dev/null
+++ b/arch/arm/configs/mx31ads_defconfig
@@ -0,0 +1,839 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.26-rc6
+# Fri Jun 20 16:21:11 2008
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_ZONE_DMA=y
+CONFIG_ARCH_MTD_XIP=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+# CONFIG_HAVE_DMA_ATTRS is not set
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_CLASSIC_RCU=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+CONFIG_ARCH_MXC=y
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM7X00A is not set
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# Freescale MXC Implementations
+#
+# CONFIG_ARCH_MX2 is not set
+CONFIG_ARCH_MX3=y
+
+#
+# MX3 Options
+#
+CONFIG_MACH_MX31ADS=y
+# CONFIG_MACH_PCM037 is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_V6=y
+# CONFIG_CPU_32v6K is not set
+CONFIG_CPU_32v6=y
+CONFIG_CPU_ABRT_EV6=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_V6=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V6=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="noinitrd console=ttymxc0,115200 root=/dev/mtdblock2 rw ip=off"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_VFP=y
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=m
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_REDBOOT_PARTS=y
+CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
+# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set
+# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+CONFIG_MTD_CFI_GEOMETRY=y
+# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+# CONFIG_MTD_CFI_I2 is not set
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_OTP is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_RAM=y
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_XIP is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+# CONFIG_BLK_DEV is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+# CONFIG_INPUT is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_IMX=y
+CONFIG_SERIAL_IMX_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+CONFIG_HAVE_GPIO_LIB=y
+
+#
+# GPIO Support
+#
+
+#
+# I2C GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_MMC is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_UIO is not set
+
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4DEV_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_DNOTIFY is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+# CONFIG_NFS_V3 is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_NLS is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_PRINTK_TIME=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_SAMPLES is not set
+# CONFIG_DEBUG_USER is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+# CONFIG_CRYPTO_HW is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+# CONFIG_GENERIC_FIND_NEXT_BIT is not set
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/mx31litekit_defconfig b/arch/arm/configs/mx31litekit_defconfig
new file mode 100644
index 000000000000..4f41c4135685
--- /dev/null
+++ b/arch/arm/configs/mx31litekit_defconfig
@@ -0,0 +1,1100 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.26-rc5
+# Fri Jun 13 14:23:39 2008
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+# CONFIG_GENERIC_GPIO is not set
+# CONFIG_GENERIC_TIME is not set
+# CONFIG_GENERIC_CLOCKEVENTS is not set
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_ZONE_DMA=y
+CONFIG_ARCH_MTD_XIP=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+# CONFIG_GROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+# CONFIG_HAVE_DMA_ATTRS is not set
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_CLASSIC_RCU=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+CONFIG_ARCH_MXC=y
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM7X00A is not set
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# Freescale MXC Implementations
+#
+CONFIG_ARCH_MX3=y
+
+#
+# MX3 Options
+#
+# CONFIG_MACH_MX31ADS is not set
+CONFIG_MACH_MX31LITE=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_V6=y
+# CONFIG_CPU_32v6K is not set
+CONFIG_CPU_32v6=y
+CONFIG_CPU_ABRT_EV6=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_V6=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V6=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_PCCARD=m
+# CONFIG_PCMCIA_DEBUG is not set
+# CONFIG_PCMCIA is not set
+
+#
+# PC-card bridges
+#
+
+#
+# Kernel Features
+#
+# CONFIG_TICK_ONESHOT is not set
+CONFIG_PREEMPT=y
+# CONFIG_NO_IDLE_HZ is not set
+CONFIG_HZ=100
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="noinitrd console=ttymxc0,115200 root=/dev/mtdblock2 rw ip=off"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_VFP=y
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+CONFIG_BINFMT_AOUT=y
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+# CONFIG_SUSPEND is not set
+# CONFIG_APM_EMULATION is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=m
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_REDBOOT_PARTS=y
+CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
+# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set
+# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+CONFIG_MTD_CFI_GEOMETRY=y
+# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+# CONFIG_MTD_CFI_I2 is not set
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_OTP is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_RAM=y
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_XIP is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+# CONFIG_BLK_DEV is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_UCB1400 is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_PASIC3 is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+CONFIG_VIDEO_DEV=y
+CONFIG_VIDEO_V4L2_COMMON=y
+CONFIG_VIDEO_ALLOW_V4L1=y
+CONFIG_VIDEO_V4L1_COMPAT=y
+# CONFIG_DVB_CORE is not set
+CONFIG_VIDEO_MEDIA=y
+
+#
+# Multimedia drivers
+#
+# CONFIG_MEDIA_ATTACH is not set
+CONFIG_VIDEO_V4L2=y
+CONFIG_VIDEO_V4L1=y
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
+# CONFIG_VIDEO_VIVI is not set
+# CONFIG_VIDEO_CPIA is not set
+# CONFIG_VIDEO_CPIA2 is not set
+CONFIG_V4L_USB_DRIVERS=y
+# CONFIG_USB_VICAM is not set
+# CONFIG_USB_IBMCAM is not set
+# CONFIG_USB_KONICAWC is not set
+# CONFIG_USB_QUICKCAM_MESSENGER is not set
+# CONFIG_USB_ET61X251 is not set
+# CONFIG_USB_OV511 is not set
+# CONFIG_USB_SE401 is not set
+# CONFIG_USB_SN9C102 is not set
+# CONFIG_USB_STV680 is not set
+# CONFIG_USB_ZC0301 is not set
+# CONFIG_USB_PWC is not set
+# CONFIG_USB_ZR364XX is not set
+# CONFIG_USB_STKWEBCAM is not set
+# CONFIG_SOC_CAMERA is not set
+CONFIG_RADIO_ADAPTERS=y
+# CONFIG_USB_DSBR is not set
+# CONFIG_USB_SI470X is not set
+CONFIG_DAB=y
+# CONFIG_USB_DABUSB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_CFB_FILLRECT is not set
+# CONFIG_FB_CFB_COPYAREA is not set
+# CONFIG_FB_CFB_IMAGEBLIT is not set
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+CONFIG_LOGO_LINUX_CLUT224=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_SUSPEND is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+CONFIG_USB_MON=y
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_GADGET is not set
+# CONFIG_MMC is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_UIO is not set
+
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4DEV_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_DNOTIFY is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+# CONFIG_NFS_V3 is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_NLS is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_PRINTK_TIME=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+CONFIG_DEBUG_PREEMPT=y
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
+# CONFIG_DEBUG_USER is not set
+CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_HW=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+# CONFIG_GENERIC_FIND_NEXT_BIT is not set
+CONFIG_CRC_CCITT=m
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/netx_defconfig b/arch/arm/configs/netx_defconfig
index 57f32f39d0ff..0884f2370c3a 100644
--- a/arch/arm/configs/netx_defconfig
+++ b/arch/arm/configs/netx_defconfig
@@ -154,7 +154,6 @@ CONFIG_ARM_AMBA=y
 # Kernel Features
 #
 CONFIG_PREEMPT=y
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
 # CONFIG_AEABI is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/onearm_defconfig b/arch/arm/configs/onearm_defconfig
index 650a248613e5..418ca2febbe3 100644
--- a/arch/arm/configs/onearm_defconfig
+++ b/arch/arm/configs/onearm_defconfig
@@ -202,7 +202,6 @@ CONFIG_AT91_CF=y
 # Kernel Features
 #
 # CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
 # CONFIG_AEABI is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/orion5x_defconfig b/arch/arm/configs/orion5x_defconfig
index 52cd99bd52fb..9578b5d9f9c7 100644
--- a/arch/arm/configs/orion5x_defconfig
+++ b/arch/arm/configs/orion5x_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.24
-# Thu Feb  7 14:10:30 2008
+# Linux kernel version: 2.6.26-rc4
+# Mon Jun  2 23:54:48 2008
 #
 CONFIG_ARM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
@@ -21,6 +21,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U64 is not set
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
 CONFIG_ZONE_DMA=y
 CONFIG_VECTORS_BASE=0xffff0000
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
@@ -40,24 +41,24 @@ CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
-# CONFIG_USER_NS is not set
-# CONFIG_PID_NS is not set
 # CONFIG_AUDIT is not set
 # CONFIG_IKCONFIG is not set
 CONFIG_LOG_BUF_SHIFT=14
 # CONFIG_CGROUPS is not set
-CONFIG_FAIR_GROUP_SCHED=y
-CONFIG_FAIR_USER_SCHED=y
-# CONFIG_FAIR_CGROUP_SCHED is not set
+# CONFIG_GROUP_SCHED is not set
 CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
 # CONFIG_BLK_DEV_INITRD is not set
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_SYSCTL=y
 CONFIG_EMBEDDED=y
 CONFIG_UID16=y
 CONFIG_SYSCTL_SYSCALL=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
 CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
@@ -73,20 +74,25 @@ CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
 CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_SLAB=y
-# CONFIG_SLUB is not set
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
 # CONFIG_SLOB is not set
-# CONFIG_PROFILING is not set
+CONFIG_PROFILING=y
 # CONFIG_MARKERS is not set
+CONFIG_OPROFILE=y
 CONFIG_HAVE_OPROFILE=y
-# CONFIG_KPROBES is not set
+CONFIG_KPROBES=y
+CONFIG_KRETPROBES=y
 CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+# CONFIG_HAVE_DMA_ATTRS is not set
 CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
@@ -111,7 +117,6 @@ CONFIG_DEFAULT_CFQ=y
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="cfq"
 CONFIG_CLASSIC_RCU=y
-# CONFIG_PREEMPT_RCU is not set
 
 #
 # System Type
@@ -160,6 +165,15 @@ CONFIG_MACH_RD88F5182=y
 CONFIG_MACH_KUROBOX_PRO=y
 CONFIG_MACH_DNS323=y
 CONFIG_MACH_TS209=y
+CONFIG_MACH_LINKSTATION_PRO=y
+CONFIG_MACH_TS409=y
+CONFIG_MACH_WRT350N_V2=y
+CONFIG_MACH_TS78XX=y
+CONFIG_MACH_MV2120=y
+CONFIG_MACH_MSS2=y
+CONFIG_MACH_WNR854T=y
+CONFIG_MACH_RD88F5181L_GE=y
+CONFIG_MACH_RD88F5181L_FXO=y
 
 #
 # Boot options
@@ -168,6 +182,7 @@ CONFIG_MACH_TS209=y
 #
 # Power management
 #
+CONFIG_PLAT_ORION=y
 
 #
 # Processor Type
@@ -177,8 +192,9 @@ CONFIG_CPU_FEROCEON=y
 CONFIG_CPU_FEROCEON_OLD_ID=y
 CONFIG_CPU_32v5=y
 CONFIG_CPU_ABRT_EV5T=y
+CONFIG_CPU_PABRT_NOIFAR=y
 CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_COPY_FEROCEON=y
 CONFIG_CPU_TLB_V4WBI=y
 CONFIG_CPU_CP15=y
 CONFIG_CPU_CP15_MMU=y
@@ -189,7 +205,6 @@ CONFIG_CPU_CP15_MMU=y
 CONFIG_ARM_THUMB=y
 # CONFIG_CPU_ICACHE_DISABLE is not set
 # CONFIG_CPU_DCACHE_DISABLE is not set
-# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
 # CONFIG_OUTER_CACHE is not set
 
 #
@@ -199,6 +214,7 @@ CONFIG_PCI=y
 CONFIG_PCI_SYSCALL=y
 # CONFIG_ARCH_SUPPORTS_MSI is not set
 CONFIG_PCI_LEGACY=y
+# CONFIG_PCI_DEBUG is not set
 # CONFIG_PCCARD is not set
 
 #
@@ -221,6 +237,7 @@ CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
 # CONFIG_SPARSEMEM_STATIC is not set
 # CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4096
 # CONFIG_RESOURCES_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
@@ -238,7 +255,6 @@ CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_CMDLINE=""
 # CONFIG_XIP_KERNEL is not set
 # CONFIG_KEXEC is not set
-# CONFIG_ATAGS_PROC is not set
 
 #
 # Floating point emulation
@@ -311,8 +327,6 @@ CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TCP_MD5SIG is not set
 # CONFIG_IPV6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
 # CONFIG_NETWORK_SECMARK is not set
 # CONFIG_NETFILTER is not set
 # CONFIG_IP_DCCP is not set
@@ -335,6 +349,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # Network testing
 #
 CONFIG_NET_PKTGEN=m
+# CONFIG_NET_TCPPROBE is not set
 # CONFIG_HAMRADIO is not set
 # CONFIG_CAN is not set
 # CONFIG_IRDA is not set
@@ -362,6 +377,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 CONFIG_FW_LOADER=y
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
 # CONFIG_SYS_HYPERVISOR is not set
 # CONFIG_CONNECTOR is not set
 CONFIG_MTD=y
@@ -371,6 +388,7 @@ CONFIG_MTD_PARTITIONS=y
 # CONFIG_MTD_REDBOOT_PARTS is not set
 CONFIG_MTD_CMDLINE_PARTS=y
 # CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
 
 #
 # User Modules And Translation Layers
@@ -378,9 +396,8 @@ CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLKDEVS=y
 CONFIG_MTD_BLOCK=y
-CONFIG_FTL=y
-CONFIG_NFTL=y
-# CONFIG_NFTL_RW is not set
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
 # CONFIG_INFTL is not set
 # CONFIG_RFD_FTL is not set
 # CONFIG_SSFDC is not set
@@ -405,12 +422,12 @@ CONFIG_MTD_MAP_BANK_WIDTH_4=y
 # CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
 CONFIG_MTD_CFI_I1=y
 CONFIG_MTD_CFI_I2=y
-CONFIG_MTD_CFI_I4=y
+# CONFIG_MTD_CFI_I4 is not set
 # CONFIG_MTD_CFI_I8 is not set
 # CONFIG_MTD_OTP is not set
 CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_CFI_STAA=y
+# CONFIG_MTD_CFI_STAA is not set
 CONFIG_MTD_CFI_UTIL=y
 # CONFIG_MTD_RAM is not set
 # CONFIG_MTD_ROM is not set
@@ -481,6 +498,9 @@ CONFIG_MISC_DEVICES=y
 # CONFIG_EEPROM_93CX6 is not set
 # CONFIG_SGI_IOC4 is not set
 # CONFIG_TIFM_CORE is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
 
 #
 # SCSI device support
@@ -542,6 +562,7 @@ CONFIG_SCSI_LOWLEVEL=y
 # CONFIG_SCSI_IPS is not set
 # CONFIG_SCSI_INITIO is not set
 # CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_MVSAS is not set
 # CONFIG_SCSI_STEX is not set
 # CONFIG_SCSI_SYM53C8XX_2 is not set
 # CONFIG_SCSI_IPR is not set
@@ -556,7 +577,10 @@ CONFIG_SCSI_LOWLEVEL=y
 # CONFIG_SCSI_SRP is not set
 CONFIG_ATA=y
 # CONFIG_ATA_NONSTANDARD is not set
+CONFIG_SATA_PMP=y
 # CONFIG_SATA_AHCI is not set
+# CONFIG_SATA_SIL24 is not set
+CONFIG_ATA_SFF=y
 # CONFIG_SATA_SVW is not set
 # CONFIG_ATA_PIIX is not set
 CONFIG_SATA_MV=y
@@ -566,7 +590,6 @@ CONFIG_SATA_MV=y
 # CONFIG_SATA_PROMISE is not set
 # CONFIG_SATA_SX4 is not set
 # CONFIG_SATA_SIL is not set
-# CONFIG_SATA_SIL24 is not set
 # CONFIG_SATA_SIS is not set
 # CONFIG_SATA_ULI is not set
 # CONFIG_SATA_VIA is not set
@@ -611,6 +634,7 @@ CONFIG_SATA_MV=y
 # CONFIG_PATA_VIA is not set
 # CONFIG_PATA_WINBOND is not set
 # CONFIG_PATA_PLATFORM is not set
+# CONFIG_PATA_SCH is not set
 # CONFIG_MD is not set
 # CONFIG_FUSION is not set
 
@@ -652,7 +676,7 @@ CONFIG_NET_PCI=y
 # CONFIG_B44 is not set
 # CONFIG_FORCEDETH is not set
 # CONFIG_EEPRO100 is not set
-CONFIG_E100=y
+# CONFIG_E100 is not set
 # CONFIG_FEALNX is not set
 # CONFIG_NATSEMI is not set
 # CONFIG_NE2K_PCI is not set
@@ -668,9 +692,7 @@ CONFIG_E100=y
 CONFIG_NETDEV_1000=y
 # CONFIG_ACENIC is not set
 # CONFIG_DL2K is not set
-CONFIG_E1000=y
-CONFIG_E1000_NAPI=y
-# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
+# CONFIG_E1000 is not set
 # CONFIG_E1000E is not set
 # CONFIG_E1000E_ENABLED is not set
 # CONFIG_IP1000 is not set
@@ -680,27 +702,15 @@ CONFIG_E1000_NAPI=y
 # CONFIG_YELLOWFIN is not set
 # CONFIG_R8169 is not set
 # CONFIG_SIS190 is not set
-CONFIG_SKGE=y
-CONFIG_SKY2=y
-# CONFIG_SK98LIN is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
 # CONFIG_VIA_VELOCITY is not set
-CONFIG_TIGON3=y
+# CONFIG_TIGON3 is not set
 # CONFIG_BNX2 is not set
 CONFIG_MV643XX_ETH=y
 # CONFIG_QLA3XXX is not set
 # CONFIG_ATL1 is not set
-CONFIG_NETDEV_10000=y
-# CONFIG_CHELSIO_T1 is not set
-# CONFIG_CHELSIO_T3 is not set
-# CONFIG_IXGBE is not set
-# CONFIG_IXGB is not set
-# CONFIG_S2IO is not set
-# CONFIG_MYRI10GE is not set
-# CONFIG_NETXEN_NIC is not set
-# CONFIG_NIU is not set
-# CONFIG_MLX4_CORE is not set
-# CONFIG_TEHUTI is not set
-# CONFIG_BNX2X is not set
+# CONFIG_NETDEV_10000 is not set
 # CONFIG_TR is not set
 
 #
@@ -708,6 +718,7 @@ CONFIG_NETDEV_10000=y
 #
 # CONFIG_WLAN_PRE80211 is not set
 # CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
 
 #
 # USB Network Adapters
@@ -738,12 +749,9 @@ CONFIG_INPUT=y
 #
 # Userland interfaces
 #
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_MOUSEDEV is not set
 # CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_EVDEV is not set
+CONFIG_INPUT_EVDEV=y
 # CONFIG_INPUT_EVBUG is not set
 
 #
@@ -765,10 +773,8 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 #
 # Character devices
 #
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_VT is not set
+CONFIG_DEVKMEM=y
 # CONFIG_SERIAL_NONSTANDARD is not set
 # CONFIG_NOZOMI is not set
 
@@ -777,7 +783,7 @@ CONFIG_HW_CONSOLE=y
 #
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_PCI=y
+# CONFIG_SERIAL_8250_PCI is not set
 CONFIG_SERIAL_8250_NR_UARTS=4
 CONFIG_SERIAL_8250_RUNTIME_UARTS=2
 # CONFIG_SERIAL_8250_EXTENDED is not set
@@ -792,7 +798,7 @@ CONFIG_UNIX98_PTYS=y
 CONFIG_LEGACY_PTYS=y
 CONFIG_LEGACY_PTY_COUNT=16
 # CONFIG_IPMI_HANDLER is not set
-CONFIG_HW_RANDOM=m
+# CONFIG_HW_RANDOM is not set
 # CONFIG_NVRAM is not set
 # CONFIG_R3964 is not set
 # CONFIG_APPLICOM is not set
@@ -804,13 +810,6 @@ CONFIG_I2C_BOARDINFO=y
 CONFIG_I2C_CHARDEV=y
 
 #
-# I2C Algorithms
-#
-# CONFIG_I2C_ALGOBIT is not set
-# CONFIG_I2C_ALGOPCF is not set
-# CONFIG_I2C_ALGOPCA is not set
-
-#
 # I2C Hardware Bus support
 #
 # CONFIG_I2C_ALI1535 is not set
@@ -837,6 +836,7 @@ CONFIG_I2C_CHARDEV=y
 # CONFIG_I2C_VIA is not set
 # CONFIG_I2C_VIAPRO is not set
 # CONFIG_I2C_VOODOO3 is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
 CONFIG_I2C_MV64XXX=y
 
 #
@@ -847,19 +847,13 @@ CONFIG_I2C_MV64XXX=y
 # CONFIG_SENSORS_PCF8574 is not set
 # CONFIG_PCF8575 is not set
 # CONFIG_SENSORS_PCF8591 is not set
-# CONFIG_TPS65010 is not set
 # CONFIG_SENSORS_MAX6875 is not set
 # CONFIG_SENSORS_TSL2550 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
 # CONFIG_I2C_DEBUG_ALGO is not set
 # CONFIG_I2C_DEBUG_BUS is not set
 # CONFIG_I2C_DEBUG_CHIP is not set
-
-#
-# SPI support
-#
 # CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
 # CONFIG_W1 is not set
 # CONFIG_POWER_SUPPLY is not set
 CONFIG_HWMON=y
@@ -872,6 +866,7 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_ADM1031 is not set
 # CONFIG_SENSORS_ADM9240 is not set
 # CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
 # CONFIG_SENSORS_ATXP1 is not set
 # CONFIG_SENSORS_DS1621 is not set
 # CONFIG_SENSORS_I5K_AMB is not set
@@ -901,6 +896,7 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_SMSC47M1 is not set
 # CONFIG_SENSORS_SMSC47M192 is not set
 # CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
 # CONFIG_SENSORS_THMC50 is not set
 # CONFIG_SENSORS_VIA686A is not set
 # CONFIG_SENSORS_VT1211 is not set
@@ -910,6 +906,7 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_W83792D is not set
 # CONFIG_SENSORS_W83793 is not set
 # CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
 # CONFIG_SENSORS_W83627HF is not set
 # CONFIG_SENSORS_W83627EHF is not set
 # CONFIG_HWMON_DEBUG_CHIP is not set
@@ -925,14 +922,24 @@ CONFIG_SSB_POSSIBLE=y
 # Multifunction device drivers
 #
 # CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_PASIC3 is not set
 
 #
 # Multimedia devices
 #
+
+#
+# Multimedia core support
+#
 # CONFIG_VIDEO_DEV is not set
 # CONFIG_DVB_CORE is not set
-CONFIG_DAB=y
-# CONFIG_USB_DABUSB is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
 
 #
 # Graphics support
@@ -949,12 +956,6 @@ CONFIG_DAB=y
 # CONFIG_DISPLAY_SUPPORT is not set
 
 #
-# Console display driver support
-#
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_DUMMY_CONSOLE=y
-
-#
 # Sound
 #
 # CONFIG_SOUND is not set
@@ -985,14 +986,18 @@ CONFIG_USB_DEVICEFS=y
 CONFIG_USB_DEVICE_CLASS=y
 # CONFIG_USB_DYNAMIC_MINORS is not set
 # CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
 
 #
 # USB Host Controller Drivers
 #
+# CONFIG_USB_C67X00_HCD is not set
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_ROOT_HUB_TT=y
 CONFIG_USB_EHCI_TT_NEWSCHED=y
 # CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
 # CONFIG_USB_OHCI_HCD is not set
 # CONFIG_USB_UHCI_HCD is not set
 # CONFIG_USB_SL811_HCD is not set
@@ -1003,6 +1008,7 @@ CONFIG_USB_EHCI_TT_NEWSCHED=y
 #
 # CONFIG_USB_ACM is not set
 CONFIG_USB_PRINTER=y
+# CONFIG_USB_WDM is not set
 
 #
 # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
@@ -1022,7 +1028,9 @@ CONFIG_USB_STORAGE_SDDR09=y
 CONFIG_USB_STORAGE_SDDR55=y
 CONFIG_USB_STORAGE_JUMPSHOT=y
 # CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
 # CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
 # CONFIG_USB_LIBUSUAL is not set
 
 #
@@ -1060,6 +1068,7 @@ CONFIG_USB_STORAGE_JUMPSHOT=y
 # CONFIG_USB_TRANCEVIBRATOR is not set
 # CONFIG_USB_IOWARRIOR is not set
 # CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
 # CONFIG_USB_GADGET is not set
 # CONFIG_MMC is not set
 CONFIG_NEW_LEDS=y
@@ -1068,7 +1077,7 @@ CONFIG_LEDS_CLASS=y
 #
 # LED drivers
 #
-# CONFIG_LEDS_GPIO is not set
+CONFIG_LEDS_GPIO=y
 
 #
 # LED Triggers
@@ -1076,6 +1085,7 @@ CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_TIMER=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
 CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_HCTOSYS=y
@@ -1105,6 +1115,7 @@ CONFIG_RTC_DRV_RS5C372=y
 # CONFIG_RTC_DRV_PCF8583 is not set
 CONFIG_RTC_DRV_M41T80=y
 # CONFIG_RTC_DRV_M41T80_WDT is not set
+# CONFIG_RTC_DRV_S35390A is not set
 
 #
 # SPI RTC drivers
@@ -1125,6 +1136,7 @@ CONFIG_RTC_DRV_M41T80=y
 #
 # on-CPU RTC drivers
 #
+# CONFIG_UIO is not set
 
 #
 # File systems
@@ -1140,14 +1152,11 @@ CONFIG_JBD=y
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
 # CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
+CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
 # CONFIG_QUOTA is not set
-CONFIG_DNOTIFY=y
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
 # CONFIG_FUSE_FS is not set
@@ -1155,8 +1164,8 @@ CONFIG_DNOTIFY=y
 #
 # CD-ROM/DVD Filesystems
 #
-CONFIG_ISO9660_FS=y
-# CONFIG_JOLIET is not set
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
 # CONFIG_ZISOFS is not set
 CONFIG_UDF_FS=m
 CONFIG_UDF_NLS=y
@@ -1205,8 +1214,10 @@ CONFIG_JFFS2_RTIME=y
 # CONFIG_JFFS2_RUBIN is not set
 CONFIG_CRAMFS=y
 # CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
 CONFIG_NETWORK_FILESYSTEMS=y
@@ -1214,7 +1225,6 @@ CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
 # CONFIG_NFS_V3_ACL is not set
 # CONFIG_NFS_V4 is not set
-# CONFIG_NFS_DIRECTIO is not set
 # CONFIG_NFSD is not set
 CONFIG_ROOT_NFS=y
 CONFIG_LOCKD=y
@@ -1241,14 +1251,13 @@ CONFIG_PARTITION_ADVANCED=y
 # CONFIG_MAC_PARTITION is not set
 CONFIG_MSDOS_PARTITION=y
 CONFIG_BSD_DISKLABEL=y
-CONFIG_MINIX_SUBPARTITION=y
-CONFIG_SOLARIS_X86_PARTITION=y
-CONFIG_UNIXWARE_DISKLABEL=y
-CONFIG_LDM_PARTITION=y
-CONFIG_LDM_DEBUG=y
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
 # CONFIG_SGI_PARTITION is not set
 # CONFIG_ULTRIX_PARTITION is not set
-CONFIG_SUN_PARTITION=y
+# CONFIG_SUN_PARTITION is not set
 # CONFIG_KARMA_PARTITION is not set
 # CONFIG_EFI_PARTITION is not set
 # CONFIG_SYSV68_PARTITION is not set
@@ -1300,15 +1309,48 @@ CONFIG_NLS_ISO8859_2=y
 # CONFIG_PRINTK_TIME is not set
 CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
-# CONFIG_MAGIC_SYSRQ is not set
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
 # CONFIG_UNUSED_SYMBOLS is not set
 # CONFIG_DEBUG_FS is not set
 # CONFIG_HEADERS_CHECK is not set
-# CONFIG_DEBUG_KERNEL is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
+CONFIG_SCHEDSTATS=y
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+CONFIG_DEBUG_PREEMPT=y
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
 # CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
 CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_KPROBES_SANITY_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_LKDTM is not set
+# CONFIG_FAULT_INJECTION is not set
 # CONFIG_SAMPLES is not set
 CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
 
 #
 # Security options
@@ -1317,50 +1359,79 @@ CONFIG_DEBUG_USER=y
 # CONFIG_SECURITY is not set
 # CONFIG_SECURITY_FILE_CAPABILITIES is not set
 CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
 CONFIG_CRYPTO_ALGAPI=m
 CONFIG_CRYPTO_BLKCIPHER=m
-# CONFIG_CRYPTO_SEQIV is not set
 CONFIG_CRYPTO_MANAGER=m
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=m
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=m
+# CONFIG_CRYPTO_LRW is not set
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
 # CONFIG_CRYPTO_HMAC is not set
 # CONFIG_CRYPTO_XCBC is not set
-# CONFIG_CRYPTO_NULL is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
 # CONFIG_CRYPTO_MD4 is not set
 # CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
 # CONFIG_CRYPTO_SHA1 is not set
 # CONFIG_CRYPTO_SHA256 is not set
 # CONFIG_CRYPTO_SHA512 is not set
-# CONFIG_CRYPTO_WP512 is not set
 # CONFIG_CRYPTO_TGR192 is not set
-# CONFIG_CRYPTO_GF128MUL is not set
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_CBC=m
-CONFIG_CRYPTO_PCBC=m
-# CONFIG_CRYPTO_LRW is not set
-# CONFIG_CRYPTO_XTS is not set
-# CONFIG_CRYPTO_CTR is not set
-# CONFIG_CRYPTO_GCM is not set
-# CONFIG_CRYPTO_CCM is not set
-# CONFIG_CRYPTO_CRYPTD is not set
-# CONFIG_CRYPTO_DES is not set
-# CONFIG_CRYPTO_FCRYPT is not set
-# CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_TWOFISH is not set
-# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
 # CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
 # CONFIG_CRYPTO_CAST5 is not set
 # CONFIG_CRYPTO_CAST6 is not set
-# CONFIG_CRYPTO_TEA is not set
-# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
 # CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_ANUBIS is not set
-# CONFIG_CRYPTO_SEED is not set
 # CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
 # CONFIG_CRYPTO_DEFLATE is not set
-# CONFIG_CRYPTO_MICHAEL_MIC is not set
-# CONFIG_CRYPTO_CRC32C is not set
-# CONFIG_CRYPTO_CAMELLIA is not set
-# CONFIG_CRYPTO_TEST is not set
-# CONFIG_CRYPTO_AUTHENC is not set
 # CONFIG_CRYPTO_LZO is not set
 CONFIG_CRYPTO_HW=y
 # CONFIG_CRYPTO_DEV_HIFN_795X is not set
@@ -1369,12 +1440,14 @@ CONFIG_CRYPTO_HW=y
 # Library routines
 #
 CONFIG_BITREVERSE=y
-CONFIG_CRC_CCITT=y
-CONFIG_CRC16=y
-# CONFIG_CRC_ITU_T is not set
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+# CONFIG_GENERIC_FIND_NEXT_BIT is not set
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+CONFIG_CRC_ITU_T=m
 CONFIG_CRC32=y
 # CONFIG_CRC7 is not set
-CONFIG_LIBCRC32C=y
+# CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
 CONFIG_ZLIB_DEFLATE=y
 CONFIG_PLIST=y
diff --git a/arch/arm/configs/pcm037_defconfig b/arch/arm/configs/pcm037_defconfig
new file mode 100644
index 000000000000..627474586470
--- /dev/null
+++ b/arch/arm/configs/pcm037_defconfig
@@ -0,0 +1,748 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.26-rc6
+# Wed Jun 25 11:52:42 2008
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_ZONE_DMA=y
+CONFIG_ARCH_MTD_XIP=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+# CONFIG_HAVE_DMA_ATTRS is not set
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_CLASSIC_RCU=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+CONFIG_ARCH_MXC=y
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM7X00A is not set
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# Freescale MXC Implementations
+#
+CONFIG_ARCH_MX3=y
+
+#
+# MX3 Options
+#
+# CONFIG_MACH_MX31ADS is not set
+CONFIG_MACH_PCM037=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_V6=y
+# CONFIG_CPU_32v6K is not set
+CONFIG_CPU_32v6=y
+CONFIG_CPU_ABRT_EV6=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_V6=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V6=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="noinitrd console=ttymxc0,115200 root=/dev/mtdblock2 rw ip=off"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_VFP=y
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=m
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+# CONFIG_MTD_CFI_NOSWAP is not set
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_START=0x0
+CONFIG_MTD_PHYSMAP_LEN=0
+CONFIG_MTD_PHYSMAP_BANKWIDTH=2
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+# CONFIG_BLK_DEV is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+CONFIG_SMC91X=y
+# CONFIG_DM9000 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+# CONFIG_INPUT is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_IMX=y
+CONFIG_SERIAL_IMX_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+CONFIG_HAVE_GPIO_LIB=y
+
+#
+# GPIO Support
+#
+
+#
+# I2C GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_MMC is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_UIO is not set
+
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4DEV_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_DNOTIFY is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+# CONFIG_NFS_V3 is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_NLS is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_SAMPLES is not set
+# CONFIG_DEBUG_USER is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_CRYPTO is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+# CONFIG_GENERIC_FIND_NEXT_BIT is not set
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/pcm038_defconfig b/arch/arm/configs/pcm038_defconfig
new file mode 100644
index 000000000000..6b798c215ca8
--- /dev/null
+++ b/arch/arm/configs/pcm038_defconfig
@@ -0,0 +1,1008 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.26-rc6
+# Fri Jun 20 16:38:36 2008
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_ZONE_DMA=y
+CONFIG_ARCH_MTD_XIP=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_RT_GROUP_SCHED=y
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+CONFIG_MARKERS=y
+CONFIG_OPROFILE=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_KPROBES=y
+CONFIG_KRETPROBES=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+# CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_PROC_PAGE_MONITOR is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+# CONFIG_KMOD is not set
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+CONFIG_DEFAULT_NOOP=y
+CONFIG_DEFAULT_IOSCHED="noop"
+CONFIG_CLASSIC_RCU=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+CONFIG_ARCH_MXC=y
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM7X00A is not set
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# Freescale MXC Implementations
+#
+CONFIG_ARCH_MX2=y
+# CONFIG_ARCH_MX3 is not set
+
+#
+# MX2 family CPU support
+#
+CONFIG_MACH_MX27=y
+
+#
+# MX2 Platforms
+#
+# CONFIG_MACH_MX27ADS is not set
+CONFIG_MACH_PCM038=y
+CONFIG_MACH_PCM970_BASEBOARD=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE=""
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NET_TCPPROBE is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+CONFIG_MTD_CFI_GEOMETRY=y
+# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+# CONFIG_MTD_CFI_I2 is not set
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_OTP is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_XIP is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_START=0x00000000
+CONFIG_MTD_PHYSMAP_LEN=0x0
+CONFIG_MTD_PHYSMAP_BANKWIDTH=2
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+# CONFIG_MII is not set
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_ENC28J60 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+CONFIG_FEC_OLD=y
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_ADS7846 is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_UCB1400 is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_IMX=y
+CONFIG_SERIAL_IMX_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I2C_CHARDEV is not set
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+CONFIG_SPI_BITBANG=y
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_AT25 is not set
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+CONFIG_HAVE_GPIO_LIB=y
+
+#
+# GPIO Support
+#
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+CONFIG_VIDEO_DEV=y
+CONFIG_VIDEO_V4L2_COMMON=y
+CONFIG_VIDEO_ALLOW_V4L1=y
+CONFIG_VIDEO_V4L1_COMPAT=y
+# CONFIG_DVB_CORE is not set
+CONFIG_VIDEO_MEDIA=y
+
+#
+# Multimedia drivers
+#
+# CONFIG_MEDIA_ATTACH is not set
+CONFIG_MEDIA_TUNER=y
+# CONFIG_MEDIA_TUNER_CUSTOMIZE is not set
+CONFIG_MEDIA_TUNER_SIMPLE=y
+CONFIG_MEDIA_TUNER_TDA8290=y
+CONFIG_MEDIA_TUNER_TDA9887=y
+CONFIG_MEDIA_TUNER_TEA5761=y
+CONFIG_MEDIA_TUNER_TEA5767=y
+CONFIG_MEDIA_TUNER_MT20XX=y
+CONFIG_MEDIA_TUNER_XC2028=y
+CONFIG_MEDIA_TUNER_XC5000=y
+CONFIG_VIDEO_V4L2=y
+CONFIG_VIDEO_V4L1=y
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
+# CONFIG_VIDEO_VIVI is not set
+# CONFIG_VIDEO_CPIA is not set
+# CONFIG_VIDEO_SAA5246A is not set
+# CONFIG_VIDEO_SAA5249 is not set
+# CONFIG_TUNER_3036 is not set
+# CONFIG_SOC_CAMERA is not set
+# CONFIG_RADIO_ADAPTERS is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_CFB_FILLRECT is not set
+# CONFIG_FB_CFB_COPYAREA is not set
+# CONFIG_FB_CFB_IMAGEBLIT is not set
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+CONFIG_FONTS=y
+CONFIG_FONT_8x8=y
+# CONFIG_FONT_8x16 is not set
+# CONFIG_FONT_6x11 is not set
+# CONFIG_FONT_7x14 is not set
+# CONFIG_FONT_PEARL_8x8 is not set
+# CONFIG_FONT_ACORN_8x8 is not set
+# CONFIG_FONT_MINI_4x6 is not set
+# CONFIG_FONT_SUN8x16 is not set
+# CONFIG_FONT_SUN12x22 is not set
+# CONFIG_FONT_10x18 is not set
+# CONFIG_LOGO is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_MMC is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+CONFIG_RTC_DRV_PCF8563=y
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_UIO is not set
+
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4DEV_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY is not set
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=m
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+CONFIG_NLS_CODEPAGE_850=m
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+CONFIG_NLS_ISO8859_15=m
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_SAMPLES is not set
+# CONFIG_DEBUG_USER is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_CRYPTO is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+# CONFIG_GENERIC_FIND_NEXT_BIT is not set
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/picotux200_defconfig b/arch/arm/configs/picotux200_defconfig
index 95a22f512805..14826f0dabde 100644
--- a/arch/arm/configs/picotux200_defconfig
+++ b/arch/arm/configs/picotux200_defconfig
@@ -201,7 +201,6 @@ CONFIG_ARM_THUMB=y
 # Kernel Features
 #
 # CONFIG_PREEMPT is not set
-CONFIG_NO_IDLE_HZ=y
 CONFIG_HZ=100
 CONFIG_AEABI=y
 CONFIG_OABI_COMPAT=y
diff --git a/arch/arm/configs/pnx4008_defconfig b/arch/arm/configs/pnx4008_defconfig
index b5e11aa2e290..811b8f60d19d 100644
--- a/arch/arm/configs/pnx4008_defconfig
+++ b/arch/arm/configs/pnx4008_defconfig
@@ -151,7 +151,6 @@ CONFIG_ARM_THUMB=y
 # Kernel Features
 #
 CONFIG_PREEMPT=y
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
 # CONFIG_AEABI is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/qil-a9260_defconfig b/arch/arm/configs/qil-a9260_defconfig
new file mode 100644
index 000000000000..ef903bed061e
--- /dev/null
+++ b/arch/arm/configs/qil-a9260_defconfig
@@ -0,0 +1,1256 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.24
+# Tue Apr 15 12:28:38 2008
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_FAIR_USER_SCHED=y
+# CONFIG_FAIR_CGROUP_SCHED is not set
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_RELAY is not set
+# CONFIG_BLK_DEV_INITRD is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+CONFIG_ARCH_AT91=y
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# Atmel AT91 System-on-Chip
+#
+# CONFIG_ARCH_AT91RM9200 is not set
+CONFIG_ARCH_AT91SAM9260=y
+# CONFIG_ARCH_AT91SAM9261 is not set
+# CONFIG_ARCH_AT91SAM9263 is not set
+# CONFIG_ARCH_AT91SAM9RL is not set
+# CONFIG_ARCH_AT91CAP9 is not set
+# CONFIG_ARCH_AT91X40 is not set
+CONFIG_AT91_PMC_UNIT=y
+
+#
+# AT91SAM9260 Variants
+#
+# CONFIG_ARCH_AT91SAM9260_SAM9XE is not set
+
+#
+# AT91SAM9260 / AT91SAM9XE Board Type
+#
+# CONFIG_MACH_AT91SAM9260EK is not set
+# CONFIG_MACH_CAM60 is not set
+# CONFIG_MACH_SAM9_L9260 is not set
+# CONFIG_MACH_USB_A9260 is not set
+CONFIG_MACH_QIL_A9260=y
+
+#
+# AT91 Board Options
+#
+
+#
+# AT91 Feature Selections
+#
+# CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set
+CONFIG_AT91_SLOW_CLOCK=y
+CONFIG_AT91_TIMER_HZ=100
+# CONFIG_AT91_EARLY_DBGU is not set
+CONFIG_AT91_EARLY_USART0=y
+# CONFIG_AT91_EARLY_USART1 is not set
+# CONFIG_AT91_EARLY_USART2 is not set
+# CONFIG_AT91_EARLY_USART3 is not set
+# CONFIG_AT91_EARLY_USART4 is not set
+# CONFIG_AT91_EARLY_USART5 is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+# CONFIG_ARM_THUMB is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=100
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="mem=64M console=ttyS1,115200"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_LEGACY is not set
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND_UP_POSSIBLE=y
+CONFIG_SUSPEND=y
+# CONFIG_APM_EMULATION is not set
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ASK_IP_FIB_HASH=y
+# CONFIG_IP_FIB_TRIE is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_MULTIPLE_TABLES is not set
+# CONFIG_IP_ROUTE_MULTIPATH is not set
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+CONFIG_IP_MROUTE=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+CONFIG_MTD_DATAFLASH=y
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+CONFIG_MTD_NAND_AT91=y
+CONFIG_MTD_NAND_AT91_ECC_SOFT=y
+# CONFIG_MTD_NAND_AT91_ECC_HW is not set
+# CONFIG_MTD_NAND_AT91_ECC_NONE is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MISC_DEVICES is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_MACB=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+CONFIG_NETDEV_1000=y
+CONFIG_NETDEV_10000=y
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_EVBUG=y
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_ATMEL=y
+CONFIG_SERIAL_ATMEL_CONSOLE=y
+# CONFIG_SERIAL_ATMEL_TTYAT is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+
+#
+# I2C Algorithms
+#
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_TINY_USB is not set
+# CONFIG_I2C_PCA is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_SENSORS_DS1337 is not set
+# CONFIG_SENSORS_DS1374 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+
+#
+# SPI support
+#
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+CONFIG_SPI_ATMEL=y
+# CONFIG_SPI_BITBANG is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_AT25 is not set
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+# CONFIG_AT91SAM9_WATCHDOG is not set
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+# CONFIG_USB_HID is not set
+
+#
+# USB HID Boot Protocol drivers
+#
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_SUSPEND is not set
+# CONFIG_USB_PERSIST is not set
+# CONFIG_USB_OTG is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_ISP116X_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+CONFIG_USB_MON=y
+
+#
+# USB port drivers
+#
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+
+#
+# USB DSL modem support
+#
+
+#
+# USB Gadget Support
+#
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_PXA2XX is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+CONFIG_USB_GADGET_AT91=y
+CONFIG_USB_AT91=y
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+# CONFIG_USB_GADGET_DUALSPEED is not set
+# CONFIG_USB_ZERO is not set
+CONFIG_USB_ETH=y
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FILE_STORAGE is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+
+#
+# MMC/SD Host Controller Drivers
+#
+CONFIG_MMC_AT91=y
+# CONFIG_MMC_SPI is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+CONFIG_LEDS_GPIO=y
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+# CONFIG_LEDS_TRIGGER_TIMER is not set
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+CONFIG_RTC_DRV_M41T94=y
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_RTC_DRV_AT91SAM9 is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4DEV_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=m
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+# CONFIG_MSDOS_FS is not set
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_ACL_SUPPORT=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+# CONFIG_SUNRPC_BIND34 is not set
+CONFIG_RPCSEC_GSS_KRB5=y
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+CONFIG_NLS_CODEPAGE_850=y
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+# CONFIG_INSTRUMENTATION is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+CONFIG_FRAME_POINTER=y
+CONFIG_FORCED_INLINING=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
+CONFIG_DEBUG_USER=y
+# CONFIG_DEBUG_ERRORS is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_MANAGER=y
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_WP512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_ECB is not set
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_XTS is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_TEST is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_HW is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/realview-smp_defconfig b/arch/arm/configs/realview-smp_defconfig
index fc39ba1a89f3..0c09b23167ec 100644
--- a/arch/arm/configs/realview-smp_defconfig
+++ b/arch/arm/configs/realview-smp_defconfig
@@ -177,7 +177,6 @@ CONFIG_NR_CPUS=4
 CONFIG_HOTPLUG_CPU=y
 CONFIG_LOCAL_TIMERS=y
 # CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
 # CONFIG_AEABI is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/realview_defconfig b/arch/arm/configs/realview_defconfig
index accbf529ce5b..907e54344dad 100644
--- a/arch/arm/configs/realview_defconfig
+++ b/arch/arm/configs/realview_defconfig
@@ -126,7 +126,6 @@ CONFIG_ISA_DMA_API=y
 #
 # Kernel Features
 #
-# CONFIG_NO_IDLE_HZ is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
diff --git a/arch/arm/configs/rpc_defconfig b/arch/arm/configs/rpc_defconfig
index 5ddecb9ddf01..f62d1817d2c6 100644
--- a/arch/arm/configs/rpc_defconfig
+++ b/arch/arm/configs/rpc_defconfig
@@ -190,7 +190,6 @@ CONFIG_ISA_DMA_API=y
 #
 # CONFIG_TICK_ONESHOT is not set
 # CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
 # CONFIG_AEABI is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/s3c2410_defconfig b/arch/arm/configs/s3c2410_defconfig
index f8a1645b3d4a..35faaea8623e 100644
--- a/arch/arm/configs/s3c2410_defconfig
+++ b/arch/arm/configs/s3c2410_defconfig
@@ -1,15 +1,18 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.21-rc6
-# Mon Apr  9 10:12:58 2007
+# Linux kernel version: 2.6.26-rc8
+# Mon Jul  7 16:59:23 2008
 #
 CONFIG_ARM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
 CONFIG_GENERIC_GPIO=y
 # CONFIG_GENERIC_TIME is not set
+# CONFIG_GENERIC_CLOCKEVENTS is not set
 CONFIG_MMU=y
 CONFIG_NO_IOPORT=y
 CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
 CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 CONFIG_HARDIRQS_SW_RESEND=y
 CONFIG_GENERIC_IRQ_PROBE=y
@@ -18,34 +21,39 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U64 is not set
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
 CONFIG_ZONE_DMA=y
 CONFIG_VECTORS_BASE=0xffff0000
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 
 #
-# Code maturity level options
+# General setup
 #
 CONFIG_EXPERIMENTAL=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
 CONFIG_LOCALVERSION=""
 CONFIG_LOCALVERSION_AUTO=y
 CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
-# CONFIG_IPC_NS is not set
 CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
-# CONFIG_UTS_NS is not set
 # CONFIG_AUDIT is not set
-# CONFIG_IKCONFIG is not set
+CONFIG_IKCONFIG=m
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=16
+# CONFIG_CGROUPS is not set
+# CONFIG_GROUP_SCHED is not set
 CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_RELAY is not set
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
@@ -53,6 +61,7 @@ CONFIG_SYSCTL=y
 # CONFIG_EMBEDDED is not set
 CONFIG_UID16=y
 CONFIG_SYSCTL_SYSCALL=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_KALLSYMS=y
 # CONFIG_KALLSYMS_ALL is not set
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
@@ -60,34 +69,43 @@ CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
-CONFIG_SLAB=y
 CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+# CONFIG_HAVE_DMA_ATTRS is not set
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
-# CONFIG_SLOB is not set
-
-#
-# Loadable module support
-#
 CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_KMOD=y
-
-#
-# Block layer
-#
 CONFIG_BLOCK=y
 # CONFIG_LBD is not set
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
 
 #
 # IO Schedulers
@@ -101,6 +119,7 @@ CONFIG_DEFAULT_AS=y
 # CONFIG_DEFAULT_CFQ is not set
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_CLASSIC_RCU=y
 
 #
 # System Type
@@ -119,14 +138,17 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
 # CONFIG_ARCH_NETX is not set
 # CONFIG_ARCH_H720X is not set
 # CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
 # CONFIG_ARCH_IOP32X is not set
 # CONFIG_ARCH_IOP33X is not set
-# CONFIG_ARCH_IOP13XX is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_IXP2000 is not set
 # CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
 # CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
 # CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
 # CONFIG_ARCH_PNX4008 is not set
 # CONFIG_ARCH_PXA is not set
 # CONFIG_ARCH_RPC is not set
@@ -134,18 +156,32 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
 CONFIG_ARCH_S3C2410=y
 # CONFIG_ARCH_SHARK is not set
 # CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
 # CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM7X00A is not set
 CONFIG_PLAT_S3C24XX=y
 CONFIG_CPU_S3C244X=y
+# CONFIG_S3C24XX_PWM is not set
 CONFIG_PM_SIMTEC=y
+CONFIG_S3C2410_DMA=y
+# CONFIG_S3C2410_DMA_DEBUG is not set
+CONFIG_MACH_SMDK=y
+CONFIG_PLAT_S3C=y
+CONFIG_CPU_LLSERIAL_S3C2410=y
+CONFIG_CPU_LLSERIAL_S3C2440=y
+
+#
+# Boot options
+#
 # CONFIG_S3C_BOOT_WATCHDOG is not set
 # CONFIG_S3C_BOOT_ERROR_RESET is not set
+
+#
+# Power management
+#
 # CONFIG_S3C2410_PM_DEBUG is not set
 # CONFIG_S3C2410_PM_CHECK is not set
 CONFIG_S3C_LOWLEVEL_UART_PORT=0
-CONFIG_S3C2410_DMA=y
-# CONFIG_S3C2410_DMA_DEBUG is not set
-CONFIG_MACH_SMDK=y
 
 #
 # S3C2400 Machines
@@ -155,6 +191,8 @@ CONFIG_CPU_S3C2410_DMA=y
 CONFIG_S3C2410_PM=y
 CONFIG_S3C2410_GPIO=y
 CONFIG_S3C2410_CLOCK=y
+CONFIG_SIMTEC_NOR=y
+CONFIG_MACH_BAST_IDE=y
 
 #
 # S3C2410 Machines
@@ -167,6 +205,7 @@ CONFIG_ARCH_BAST=y
 CONFIG_MACH_OTOM=y
 CONFIG_MACH_AML_M5900=y
 CONFIG_BAST_PC104_IRQ=y
+# CONFIG_MACH_TCT_HAMMER is not set
 CONFIG_MACH_VR1000=y
 CONFIG_MACH_QT2410=y
 CONFIG_CPU_S3C2412=y
@@ -176,8 +215,10 @@ CONFIG_S3C2412_PM=y
 #
 # S3C2412 Machines
 #
+# CONFIG_MACH_JIVE is not set
 CONFIG_MACH_SMDK2413=y
 CONFIG_MACH_S3C2413=y
+# CONFIG_MACH_SMDK2412 is not set
 CONFIG_MACH_VSTMS=y
 CONFIG_CPU_S3C2440=y
 CONFIG_S3C2440_DMA=y
@@ -191,6 +232,7 @@ CONFIG_MACH_RX3715=y
 CONFIG_ARCH_S3C2440=y
 CONFIG_MACH_NEXCODER_2440=y
 CONFIG_SMDK2440_CPU2440=y
+# CONFIG_MACH_AT2440EVB is not set
 CONFIG_CPU_S3C2442=y
 
 #
@@ -215,6 +257,7 @@ CONFIG_CPU_32v4T=y
 CONFIG_CPU_32v5=y
 CONFIG_CPU_ABRT_EV4T=y
 CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_PABRT_NOIFAR=y
 CONFIG_CPU_CACHE_V4WT=y
 CONFIG_CPU_CACHE_VIVT=y
 CONFIG_CPU_COPY_V4WB=y
@@ -236,17 +279,15 @@ CONFIG_CPU_CP15_MMU=y
 # Bus support
 #
 CONFIG_ISA=y
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
 # CONFIG_PCCARD is not set
 
 #
 # Kernel Features
 #
+# CONFIG_TICK_ONESHOT is not set
 # CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=200
 # CONFIG_AEABI is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
@@ -257,9 +298,13 @@ CONFIG_FLATMEM_MANUAL=y
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
 # CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4096
 # CONFIG_RESOURCES_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
 CONFIG_ALIGNMENT_TRAP=y
 
 #
@@ -279,7 +324,7 @@ CONFIG_CMDLINE="root=/dev/hda1 ro init=/bin/bash console=ttySAC0"
 # At least one emulation must be selected
 #
 CONFIG_FPE_NWFPE=y
-# CONFIG_FPE_NWFPE_XP is not set
+CONFIG_FPE_NWFPE_XP=y
 # CONFIG_FPE_FASTFPE is not set
 # CONFIG_VFP is not set
 
@@ -295,10 +340,12 @@ CONFIG_BINFMT_AOUT=y
 # Power management options
 #
 CONFIG_PM=y
-# CONFIG_PM_LEGACY is not set
 # CONFIG_PM_DEBUG is not set
-# CONFIG_PM_SYSFS_DEPRECATED is not set
-# CONFIG_APM_EMULATION is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_APM_EMULATION=m
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
 
 #
 # Networking
@@ -308,59 +355,67 @@ CONFIG_NET=y
 #
 # Networking options
 #
-# CONFIG_NETDEBUG is not set
-# CONFIG_PACKET is not set
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
 CONFIG_UNIX=y
 CONFIG_XFRM=y
 # CONFIG_XFRM_USER is not set
 # CONFIG_XFRM_SUB_POLICY is not set
 # CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
-# CONFIG_IP_MULTICAST is not set
+CONFIG_IP_MULTICAST=y
 # CONFIG_IP_ADVANCED_ROUTER is not set
 CONFIG_IP_FIB_HASH=y
 CONFIG_IP_PNP=y
-# CONFIG_IP_PNP_DHCP is not set
+CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
 # CONFIG_IP_PNP_RARP is not set
 # CONFIG_NET_IPIP is not set
 # CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
 # CONFIG_ARPD is not set
 # CONFIG_SYN_COOKIES is not set
 # CONFIG_INET_AH is not set
 # CONFIG_INET_ESP is not set
 # CONFIG_INET_IPCOMP is not set
 # CONFIG_INET_XFRM_TUNNEL is not set
-# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_TUNNEL=m
 CONFIG_INET_XFRM_MODE_TRANSPORT=y
 CONFIG_INET_XFRM_MODE_TUNNEL=y
 CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
 CONFIG_INET_DIAG=y
 CONFIG_INET_TCP_DIAG=y
 # CONFIG_TCP_CONG_ADVANCED is not set
 CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TCP_MD5SIG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
+CONFIG_IPV6=m
+CONFIG_IPV6_PRIVACY=y
+CONFIG_IPV6_ROUTER_PREF=y
+# CONFIG_IPV6_ROUTE_INFO is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+CONFIG_INET6_AH=m
+CONFIG_INET6_ESP=m
+CONFIG_INET6_IPCOMP=m
+CONFIG_IPV6_MIP6=m
+CONFIG_INET6_XFRM_TUNNEL=m
+CONFIG_INET6_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
+CONFIG_IPV6_SIT=m
+CONFIG_IPV6_NDISC_NODETYPE=y
+CONFIG_IPV6_TUNNEL=m
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
 # CONFIG_NETWORK_SECMARK is not set
 # CONFIG_NETFILTER is not set
-
-#
-# DCCP Configuration (EXPERIMENTAL)
-#
 # CONFIG_IP_DCCP is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
 # CONFIG_IP_SCTP is not set
-
-#
-# TIPC Configuration (EXPERIMENTAL)
-#
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
@@ -373,20 +428,71 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
 # CONFIG_NET_SCHED is not set
+CONFIG_NET_SCH_FIFO=y
 
 #
 # Network testing
 #
 # CONFIG_NET_PKTGEN is not set
 # CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
 # CONFIG_IRDA is not set
-# CONFIG_BT is not set
+CONFIG_BT=m
+CONFIG_BT_L2CAP=m
+CONFIG_BT_SCO=m
+CONFIG_BT_RFCOMM=m
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=m
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=m
+
+#
+# Bluetooth device drivers
+#
+CONFIG_BT_HCIUSB=m
+CONFIG_BT_HCIUSB_SCO=y
+CONFIG_BT_HCIUART=m
+CONFIG_BT_HCIUART_H4=y
+CONFIG_BT_HCIUART_BCSP=y
+CONFIG_BT_HCIUART_LL=y
+CONFIG_BT_HCIBCM203X=m
+CONFIG_BT_HCIBPA10X=m
+CONFIG_BT_HCIBFUSB=m
+CONFIG_BT_HCIVHCI=m
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+CONFIG_CFG80211=m
+CONFIG_NL80211=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_MAC80211=m
+
+#
+# Rate control algorithm selection
+#
+CONFIG_MAC80211_RC_DEFAULT_PID=y
+# CONFIG_MAC80211_RC_DEFAULT_NONE is not set
+
+#
+# Selecting 'y' for an algorithm will
+#
+
+#
+# build the algorithm into mac80211.
+#
+CONFIG_MAC80211_RC_DEFAULT="pid"
+CONFIG_MAC80211_RC_PID=y
+CONFIG_MAC80211_MESH=y
+CONFIG_MAC80211_LEDS=y
+# CONFIG_MAC80211_DEBUG_PACKET_ALIGNMENT is not set
+# CONFIG_MAC80211_DEBUG is not set
 # CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
 
 #
 # Device Drivers
@@ -395,21 +501,14 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 #
 # Generic Driver Options
 #
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
-# CONFIG_FW_LOADER is not set
+CONFIG_FW_LOADER=m
 # CONFIG_DEBUG_DRIVER is not set
 # CONFIG_DEBUG_DEVRES is not set
 # CONFIG_SYS_HYPERVISOR is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
 # CONFIG_CONNECTOR is not set
-
-#
-# Memory Technology Devices (MTD)
-#
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
 # CONFIG_MTD_CONCAT is not set
@@ -420,6 +519,7 @@ CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
 # CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
 CONFIG_MTD_CMDLINE_PARTS=y
 # CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
 
 #
 # User Modules And Translation Layers
@@ -432,6 +532,7 @@ CONFIG_MTD_BLOCK=y
 # CONFIG_INFTL is not set
 # CONFIG_RFD_FTL is not set
 # CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
 
 #
 # RAM/ROM/Flash chip drivers
@@ -457,7 +558,6 @@ CONFIG_MTD_CFI_UTIL=y
 # CONFIG_MTD_RAM is not set
 CONFIG_MTD_ROM=y
 # CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_OBSOLETE_CHIPS is not set
 
 #
 # Mapping drivers for chip access
@@ -486,13 +586,10 @@ CONFIG_MTD_BAST_MAXSIZE=4
 # CONFIG_MTD_DOC2000 is not set
 # CONFIG_MTD_DOC2001 is not set
 # CONFIG_MTD_DOC2001PLUS is not set
-
-#
-# NAND Flash Device Drivers
-#
 CONFIG_MTD_NAND=y
 # CONFIG_MTD_NAND_VERIFY_WRITE is not set
 # CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
 CONFIG_MTD_NAND_IDS=y
 CONFIG_MTD_NAND_S3C2410=y
 # CONFIG_MTD_NAND_S3C2410_DEBUG is not set
@@ -500,30 +597,25 @@ CONFIG_MTD_NAND_S3C2410=y
 # CONFIG_MTD_NAND_S3C2410_CLKSTOP is not set
 # CONFIG_MTD_NAND_DISKONCHIP is not set
 # CONFIG_MTD_NAND_NANDSIM is not set
-
-#
-# OneNAND Flash Device Drivers
-#
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
 # CONFIG_MTD_ONENAND is not set
 
 #
-# Parallel port support
+# UBI - Unsorted block images
 #
+# CONFIG_MTD_UBI is not set
 CONFIG_PARPORT=y
-# CONFIG_PARPORT_PC is not set
+CONFIG_PARPORT_PC=m
+# CONFIG_PARPORT_PC_FIFO is not set
+# CONFIG_PARPORT_PC_SUPERIO is not set
 # CONFIG_PARPORT_GSC is not set
-# CONFIG_PARPORT_AX88796 is not set
+CONFIG_PARPORT_AX88796=m
 CONFIG_PARPORT_1284=y
-
-#
-# Plug and Play support
-#
+CONFIG_PARPORT_NOT_PC=y
 # CONFIG_PNP is not set
-# CONFIG_PNPACPI is not set
-
-#
-# Block devices
-#
+CONFIG_BLK_DEV=y
+# CONFIG_PARIDE is not set
 # CONFIG_BLK_DEV_COW_COMMON is not set
 CONFIG_BLK_DEV_LOOP=y
 # CONFIG_BLK_DEV_CRYPTOLOOP is not set
@@ -532,34 +624,34 @@ CONFIG_BLK_DEV_NBD=m
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_BLK_DEV_XIP is not set
 # CONFIG_CDROM_PKTCDVD is not set
 CONFIG_ATA_OVER_ETH=m
-
-#
-# ATA/ATAPI/MFM/RLL support
-#
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
 CONFIG_IDE=y
 CONFIG_BLK_DEV_IDE=y
 
 #
-# Please see Documentation/ide.txt for help/info on IDE drives
+# Please see Documentation/ide/ide.txt for help/info on IDE drives
 #
 # CONFIG_BLK_DEV_IDE_SATA is not set
 CONFIG_BLK_DEV_IDEDISK=y
 # CONFIG_IDEDISK_MULTI_MODE is not set
 CONFIG_BLK_DEV_IDECD=y
+CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y
 CONFIG_BLK_DEV_IDETAPE=m
 CONFIG_BLK_DEV_IDEFLOPPY=m
+# CONFIG_BLK_DEV_IDESCSI is not set
 # CONFIG_IDE_TASK_IOCTL is not set
+CONFIG_IDE_PROC_FS=y
 
 #
 # IDE chipset support/bugfixes
 #
-CONFIG_IDE_GENERIC=y
-# CONFIG_IDE_ARM is not set
-CONFIG_BLK_DEV_IDE_BAST=y
-# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_BLK_DEV_PLATFORM is not set
 # CONFIG_BLK_DEV_IDEDMA is not set
 # CONFIG_BLK_DEV_HD is not set
 
@@ -567,101 +659,119 @@ CONFIG_BLK_DEV_IDE_BAST=y
 # SCSI device support
 #
 # CONFIG_RAID_ATTRS is not set
-# CONFIG_SCSI is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+CONFIG_SCSI_TGT=m
 # CONFIG_SCSI_NETLINK is not set
-
-#
-# Serial ATA (prod) and Parallel ATA (experimental) drivers
-#
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_ST=m
+# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SR=m
+CONFIG_BLK_DEV_SR_VENDOR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_CHR_DEV_SCH=m
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_SCSI_CONSTANTS=y
+# CONFIG_SCSI_LOGGING is not set
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_SCSI_AHA152X is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set
+# CONFIG_SCSI_PPA is not set
+# CONFIG_SCSI_IMM is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_DEBUG is not set
 # CONFIG_ATA is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
+CONFIG_HAVE_PATA_PLATFORM=y
 # CONFIG_MD is not set
-
-#
-# Fusion MPT device support
-#
-# CONFIG_FUSION is not set
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# Network device support
-#
 CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
-
-#
-# ARCnet devices
-#
+# CONFIG_VETH is not set
 # CONFIG_ARCNET is not set
-
-#
-# PHY device support
-#
 # CONFIG_PHYLIB is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
 CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
+# CONFIG_AX88796 is not set
 # CONFIG_NET_VENDOR_3COM is not set
 # CONFIG_NET_VENDOR_SMC is not set
 # CONFIG_SMC91X is not set
 CONFIG_DM9000=y
+# CONFIG_ENC28J60 is not set
+CONFIG_DM9000_DEBUGLEVEL=4
 # CONFIG_NET_VENDOR_RACAL is not set
 # CONFIG_AT1700 is not set
 # CONFIG_DEPCA is not set
 # CONFIG_HP100 is not set
 # CONFIG_NET_ISA is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
 # CONFIG_NET_PCI is not set
+# CONFIG_B44 is not set
 # CONFIG_NET_POCKET is not set
-
-#
-# Ethernet (1000 Mbit)
-#
-
-#
-# Ethernet (10000 Mbit)
-#
-
-#
-# Token Ring devices
-#
+CONFIG_NETDEV_1000=y
+# CONFIG_E1000E_ENABLED is not set
+CONFIG_NETDEV_10000=y
 # CONFIG_TR is not set
 
 #
-# Wireless LAN (non-hamradio)
+# Wireless LAN
 #
-# CONFIG_NET_RADIO is not set
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
 
 #
-# Wan interfaces
+# USB Network Adapters
 #
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
 # CONFIG_WAN is not set
 # CONFIG_PLIP is not set
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
-# CONFIG_SHAPER is not set
 # CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
-
-#
-# ISDN subsystem
-#
 # CONFIG_ISDN is not set
 
 #
@@ -669,6 +779,7 @@ CONFIG_DM9000=y
 #
 CONFIG_INPUT=y
 # CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
 
 #
 # Userland interfaces
@@ -678,7 +789,6 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y
 CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 # CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
 # CONFIG_INPUT_EVDEV is not set
 # CONFIG_INPUT_EVBUG is not set
 
@@ -695,12 +805,21 @@ CONFIG_KEYBOARD_ATKBD=y
 # CONFIG_KEYBOARD_GPIO is not set
 CONFIG_INPUT_MOUSE=y
 CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_LIFEBOOK=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
 # CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
 # CONFIG_MOUSE_INPORT is not set
 # CONFIG_MOUSE_LOGIBM is not set
 # CONFIG_MOUSE_PC110PAD is not set
 # CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_GPIO is not set
 # CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
 # CONFIG_INPUT_TOUCHSCREEN is not set
 # CONFIG_INPUT_MISC is not set
 
@@ -721,6 +840,7 @@ CONFIG_VT=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
 # CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
 CONFIG_SERIAL_NONSTANDARD=y
 # CONFIG_COMPUTONE is not set
 # CONFIG_ROCKETPORT is not set
@@ -728,8 +848,6 @@ CONFIG_SERIAL_NONSTANDARD=y
 # CONFIG_DIGIEPCA is not set
 # CONFIG_MOXA_INTELLIO is not set
 # CONFIG_MOXA_SMARTIO is not set
-# CONFIG_MOXA_SMARTIO_NEW is not set
-# CONFIG_SYNCLINKMP is not set
 # CONFIG_N_HDLC is not set
 # CONFIG_RISCOM8 is not set
 # CONFIG_SPECIALIX is not set
@@ -758,8 +876,12 @@ CONFIG_SERIAL_8250_SHARE_IRQ=y
 #
 # Non-8250 serial port support
 #
+CONFIG_SERIAL_SAMSUNG=y
+# CONFIG_SERIAL_SAMSUNG_DEBUG is not set
+CONFIG_SERIAL_SAMSUNG_CONSOLE=y
 CONFIG_SERIAL_S3C2410=y
-CONFIG_SERIAL_S3C2410_CONSOLE=y
+CONFIG_SERIAL_S3C2412=y
+CONFIG_SERIAL_S3C2440=y
 CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
@@ -768,89 +890,50 @@ CONFIG_LEGACY_PTY_COUNT=256
 CONFIG_PRINTER=y
 # CONFIG_LP_CONSOLE is not set
 CONFIG_PPDEV=y
-# CONFIG_TIPAR is not set
-
-#
-# IPMI
-#
 # CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-CONFIG_WATCHDOG=y
-# CONFIG_WATCHDOG_NOWAYOUT is not set
-
-#
-# Watchdog Device Drivers
-#
-# CONFIG_SOFT_WATCHDOG is not set
-CONFIG_S3C2410_WATCHDOG=y
-
-#
-# ISA-based Watchdog Cards
-#
-# CONFIG_PCWATCHDOG is not set
-# CONFIG_MIXCOMWD is not set
-# CONFIG_WDT is not set
-
-#
-# USB-based Watchdog Cards
-#
-# CONFIG_USBPCWATCHDOG is not set
 CONFIG_HW_RANDOM=y
 # CONFIG_NVRAM is not set
 # CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
 # CONFIG_RAW_DRIVER is not set
-
-#
-# TPM devices
-#
 # CONFIG_TCG_TPM is not set
-
-#
-# I2C support
-#
+CONFIG_DEVPORT=y
 CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
 CONFIG_I2C_CHARDEV=m
-
-#
-# I2C Algorithms
-#
-CONFIG_I2C_ALGOBIT=m
-# CONFIG_I2C_ALGOPCF is not set
-# CONFIG_I2C_ALGOPCA is not set
+CONFIG_I2C_ALGOBIT=y
 
 #
 # I2C Hardware Bus support
 #
 # CONFIG_I2C_ELEKTOR is not set
+# CONFIG_I2C_GPIO is not set
 # CONFIG_I2C_OCORES is not set
 # CONFIG_I2C_PARPORT is not set
 # CONFIG_I2C_PARPORT_LIGHT is not set
 CONFIG_I2C_S3C2410=y
+CONFIG_I2C_SIMTEC=y
+# CONFIG_I2C_TAOS_EVM is not set
 # CONFIG_I2C_STUB is not set
+# CONFIG_I2C_TINY_USB is not set
 # CONFIG_I2C_PCA_ISA is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
 
 #
 # Miscellaneous I2C Chip support
 #
-# CONFIG_SENSORS_DS1337 is not set
-# CONFIG_SENSORS_DS1374 is not set
+# CONFIG_DS1682 is not set
 CONFIG_SENSORS_EEPROM=m
 # CONFIG_SENSORS_PCF8574 is not set
-# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_PCF8575 is not set
 # CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_TPS65010 is not set
 # CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
 # CONFIG_I2C_DEBUG_ALGO is not set
 # CONFIG_I2C_DEBUG_BUS is not set
 # CONFIG_I2C_DEBUG_CHIP is not set
-
-#
-# SPI support
-#
 CONFIG_SPI=y
 # CONFIG_SPI_DEBUG is not set
 CONFIG_SPI_MASTER=y
@@ -860,6 +943,7 @@ CONFIG_SPI_MASTER=y
 #
 CONFIG_SPI_BITBANG=m
 # CONFIG_SPI_BUTTERFLY is not set
+# CONFIG_SPI_LM70_LLP is not set
 CONFIG_SPI_S3C24XX=m
 CONFIG_SPI_S3C24XX_GPIO=m
 
@@ -867,30 +951,43 @@ CONFIG_SPI_S3C24XX_GPIO=m
 # SPI Protocol Masters
 #
 # CONFIG_SPI_AT25 is not set
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+CONFIG_HAVE_GPIO_LIB=y
 
 #
-# Dallas's 1-wire bus
+# GPIO Support
 #
-# CONFIG_W1 is not set
+# CONFIG_DEBUG_GPIO is not set
 
 #
-# Hardware Monitoring support
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+
 #
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
 CONFIG_HWMON=y
 CONFIG_HWMON_VID=m
-# CONFIG_SENSORS_ABITUGURU is not set
+# CONFIG_SENSORS_AD7418 is not set
 # CONFIG_SENSORS_ADM1021 is not set
 # CONFIG_SENSORS_ADM1025 is not set
 # CONFIG_SENSORS_ADM1026 is not set
 # CONFIG_SENSORS_ADM1029 is not set
 # CONFIG_SENSORS_ADM1031 is not set
 # CONFIG_SENSORS_ADM9240 is not set
-# CONFIG_SENSORS_ASB100 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
 # CONFIG_SENSORS_ATXP1 is not set
 # CONFIG_SENSORS_DS1621 is not set
 # CONFIG_SENSORS_F71805F is not set
-# CONFIG_SENSORS_FSCHER is not set
-# CONFIG_SENSORS_FSCPOS is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
 # CONFIG_SENSORS_GL518SM is not set
 # CONFIG_SENSORS_GL520SM is not set
 # CONFIG_SENSORS_IT87 is not set
@@ -905,72 +1002,95 @@ CONFIG_SENSORS_LM85=m
 # CONFIG_SENSORS_LM87 is not set
 # CONFIG_SENSORS_LM90 is not set
 # CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
 # CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
 # CONFIG_SENSORS_PC87360 is not set
 # CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_DME1737 is not set
 # CONFIG_SENSORS_SMSC47M1 is not set
 # CONFIG_SENSORS_SMSC47M192 is not set
 # CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_THMC50 is not set
 # CONFIG_SENSORS_VT1211 is not set
 # CONFIG_SENSORS_W83781D is not set
 # CONFIG_SENSORS_W83791D is not set
 # CONFIG_SENSORS_W83792D is not set
 # CONFIG_SENSORS_W83793 is not set
 # CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
 # CONFIG_SENSORS_W83627HF is not set
 # CONFIG_SENSORS_W83627EHF is not set
 # CONFIG_HWMON_DEBUG_CHIP is not set
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
 
 #
-# Misc devices
+# Watchdog Device Drivers
 #
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_S3C2410_WATCHDOG=y
 
 #
-# Multifunction device drivers
+# ISA-based Watchdog Cards
 #
-# CONFIG_MFD_SM501 is not set
+# CONFIG_PCWATCHDOG is not set
+# CONFIG_MIXCOMWD is not set
+# CONFIG_WDT is not set
 
 #
-# LED devices
+# USB-based Watchdog Cards
 #
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=m
+# CONFIG_USBPCWATCHDOG is not set
 
 #
-# LED drivers
+# Sonics Silicon Backplane
 #
-CONFIG_LEDS_S3C24XX=m
-CONFIG_LEDS_H1940=m
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
 
 #
-# LED Triggers
+# Multifunction device drivers
 #
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_TIMER=m
-# CONFIG_LEDS_TRIGGER_IDE_DISK is not set
-CONFIG_LEDS_TRIGGER_HEARTBEAT=m
+CONFIG_MFD_SM501=y
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
 
 #
 # Multimedia devices
 #
+
+#
+# Multimedia core support
+#
 # CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
 
 #
-# Digital Video Broadcasting Devices
+# Multimedia drivers
 #
-# CONFIG_DVB is not set
-# CONFIG_USB_DABUSB is not set
+# CONFIG_DAB is not set
 
 #
 # Graphics support
 #
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
 CONFIG_FB=y
 CONFIG_FIRMWARE_EDID=y
 # CONFIG_FB_DDC is not set
 CONFIG_FB_CFB_FILLRECT=y
 CONFIG_FB_CFB_COPYAREA=y
 CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
 # CONFIG_FB_SVGALIB is not set
 # CONFIG_FB_MACMODES is not set
 # CONFIG_FB_BACKLIGHT is not set
@@ -978,12 +1098,19 @@ CONFIG_FB_MODE_HELPERS=y
 # CONFIG_FB_TILEBLITTING is not set
 
 #
-# Frambuffer hardware drivers
+# Frame buffer hardware drivers
 #
 # CONFIG_FB_S1D13XXX is not set
 CONFIG_FB_S3C2410=y
 # CONFIG_FB_S3C2410_DEBUG is not set
+CONFIG_FB_SM501=y
 # CONFIG_FB_VIRTUAL is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
 
 #
 # Console display driver support
@@ -992,40 +1119,45 @@ CONFIG_FB_S3C2410=y
 # CONFIG_MDA_CONSOLE is not set
 CONFIG_DUMMY_CONSOLE=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
 # CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
 # CONFIG_FONTS is not set
 CONFIG_FONT_8x8=y
 CONFIG_FONT_8x16=y
-
-#
-# Logo configuration
-#
 # CONFIG_LOGO is not set
 
 #
 # Sound
 #
 # CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
 
 #
-# HID Devices
+# USB Input Devices
 #
-CONFIG_HID=y
-# CONFIG_HID_DEBUG is not set
+# CONFIG_USB_HID is not set
 
 #
-# USB support
+# USB HID Boot Protocol drivers
 #
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
 CONFIG_USB_ARCH_HAS_OHCI=y
 # CONFIG_USB_ARCH_HAS_EHCI is not set
 CONFIG_USB=y
 # CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
 
 #
 # Miscellaneous USB options
 #
 CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
 # CONFIG_USB_DYNAMIC_MINORS is not set
 # CONFIG_USB_SUSPEND is not set
 # CONFIG_USB_OTG is not set
@@ -1033,18 +1165,22 @@ CONFIG_USB_DEVICEFS=y
 #
 # USB Host Controller Drivers
 #
+# CONFIG_USB_C67X00_HCD is not set
 # CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
 CONFIG_USB_OHCI_HCD=y
 # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
 # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
 CONFIG_USB_OHCI_LITTLE_ENDIAN=y
 # CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
 
 #
 # USB Device Class drivers
 #
-# CONFIG_USB_ACM is not set
-# CONFIG_USB_PRINTER is not set
+CONFIG_USB_ACM=m
+CONFIG_USB_PRINTER=m
+CONFIG_USB_WDM=m
 
 #
 # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
@@ -1053,57 +1189,78 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y
 #
 # may also be needed; see USB_STORAGE Help for more information
 #
-# CONFIG_USB_LIBUSUAL is not set
-
-#
-# USB Input Devices
-#
-# CONFIG_USB_HID is not set
-
-#
-# USB HID Boot Protocol drivers
-#
-# CONFIG_USB_KBD is not set
-# CONFIG_USB_MOUSE is not set
-# CONFIG_USB_AIPTEK is not set
-# CONFIG_USB_WACOM is not set
-# CONFIG_USB_ACECAD is not set
-# CONFIG_USB_KBTAB is not set
-# CONFIG_USB_POWERMATE is not set
-# CONFIG_USB_TOUCHSCREEN is not set
-# CONFIG_USB_YEALINK is not set
-# CONFIG_USB_XPAD is not set
-# CONFIG_USB_ATI_REMOTE is not set
-# CONFIG_USB_ATI_REMOTE2 is not set
-# CONFIG_USB_KEYSPAN_REMOTE is not set
-# CONFIG_USB_APPLETOUCH is not set
-# CONFIG_USB_GTCO is not set
+CONFIG_USB_STORAGE=m
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+CONFIG_USB_LIBUSUAL=y
 
 #
 # USB Imaging devices
 #
 # CONFIG_USB_MDC800 is not set
-
-#
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET_MII is not set
-# CONFIG_USB_USBNET is not set
+# CONFIG_USB_MICROTEK is not set
 CONFIG_USB_MON=y
 
 #
 # USB port drivers
 #
 # CONFIG_USB_USS720 is not set
-
-#
-# USB Serial Converter support
-#
-# CONFIG_USB_SERIAL is not set
+CONFIG_USB_SERIAL=y
+# CONFIG_USB_SERIAL_CONSOLE is not set
+# CONFIG_USB_EZUSB is not set
+CONFIG_USB_SERIAL_GENERIC=y
+# CONFIG_USB_SERIAL_AIRCABLE is not set
+# CONFIG_USB_SERIAL_AIRPRIME is not set
+# CONFIG_USB_SERIAL_ARK3116 is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_CH341 is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_CP2101 is not set
+# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+CONFIG_USB_SERIAL_FTDI_SIO=y
+# CONFIG_USB_SERIAL_FUNSOFT is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IPAQ is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
+# CONFIG_USB_SERIAL_GARMIN is not set
+# CONFIG_USB_SERIAL_IPW is not set
+# CONFIG_USB_SERIAL_IUU is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KLSI is not set
+# CONFIG_USB_SERIAL_KOBIL_SCT is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_MOS7720 is not set
+# CONFIG_USB_SERIAL_MOS7840 is not set
+# CONFIG_USB_SERIAL_MOTOROLA is not set
+CONFIG_USB_SERIAL_NAVMAN=m
+CONFIG_USB_SERIAL_PL2303=y
+# CONFIG_USB_SERIAL_OTI6858 is not set
+# CONFIG_USB_SERIAL_SPCP8X5 is not set
+# CONFIG_USB_SERIAL_HP4X is not set
+# CONFIG_USB_SERIAL_SAFE is not set
+# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
+# CONFIG_USB_SERIAL_TI is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+CONFIG_USB_SERIAL_OPTION=m
+# CONFIG_USB_SERIAL_OMNINET is not set
+# CONFIG_USB_SERIAL_DEBUG is not set
 
 #
 # USB Miscellaneous drivers
@@ -1116,35 +1273,38 @@ CONFIG_USB_MON=y
 # CONFIG_USB_LEGOTOWER is not set
 # CONFIG_USB_LCD is not set
 # CONFIG_USB_BERRY_CHARGE is not set
-# CONFIG_USB_LED is not set
+CONFIG_USB_LED=m
 # CONFIG_USB_CYPRESS_CY7C63 is not set
 # CONFIG_USB_CYTHERM is not set
 # CONFIG_USB_PHIDGET is not set
 # CONFIG_USB_IDMOUSE is not set
 # CONFIG_USB_FTDI_ELAN is not set
 # CONFIG_USB_APPLEDISPLAY is not set
-# CONFIG_USB_LD is not set
+CONFIG_USB_LD=m
 # CONFIG_USB_TRANCEVIBRATOR is not set
 # CONFIG_USB_IOWARRIOR is not set
 # CONFIG_USB_TEST is not set
-
-#
-# USB DSL modem support
-#
-
-#
-# USB Gadget Support
-#
+# CONFIG_USB_ISIGHTFW is not set
 # CONFIG_USB_GADGET is not set
+# CONFIG_MMC is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=m
 
 #
-# MMC/SD Card support
+# LED drivers
 #
-# CONFIG_MMC is not set
+CONFIG_LEDS_S3C24XX=m
+CONFIG_LEDS_H1940=m
+# CONFIG_LEDS_GPIO is not set
 
 #
-# Real Time Clock
+# LED Triggers
 #
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=m
+# CONFIG_LEDS_TRIGGER_IDE_DISK is not set
+CONFIG_LEDS_TRIGGER_HEARTBEAT=m
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
 CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_HCTOSYS=y
@@ -1158,61 +1318,86 @@ CONFIG_RTC_INTF_SYSFS=y
 CONFIG_RTC_INTF_PROC=y
 CONFIG_RTC_INTF_DEV=y
 # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
 
 #
-# RTC drivers
+# I2C RTC drivers
 #
-# CONFIG_RTC_DRV_CMOS is not set
-# CONFIG_RTC_DRV_X1205 is not set
 # CONFIG_RTC_DRV_DS1307 is not set
-# CONFIG_RTC_DRV_DS1553 is not set
-# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
 # CONFIG_RTC_DRV_DS1672 is not set
-# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
 # CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
 # CONFIG_RTC_DRV_RS5C348 is not set
-# CONFIG_RTC_DRV_RS5C372 is not set
-CONFIG_RTC_DRV_S3C=y
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
 # CONFIG_RTC_DRV_M48T86 is not set
-# CONFIG_RTC_DRV_TEST is not set
-# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
 # CONFIG_RTC_DRV_V3020 is not set
 
 #
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_S3C=y
+# CONFIG_UIO is not set
+
+#
 # File systems
 #
 CONFIG_EXT2_FS=y
-# CONFIG_EXT2_FS_XATTR is not set
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
 # CONFIG_EXT2_FS_XIP is not set
 CONFIG_EXT3_FS=y
 CONFIG_EXT3_FS_XATTR=y
-# CONFIG_EXT3_FS_POSIX_ACL is not set
+CONFIG_EXT3_FS_POSIX_ACL=y
 # CONFIG_EXT3_FS_SECURITY is not set
 # CONFIG_EXT4DEV_FS is not set
 CONFIG_JBD=y
-# CONFIG_JBD_DEBUG is not set
 CONFIG_FS_MBCACHE=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
-# CONFIG_FS_POSIX_ACL is not set
+CONFIG_FS_POSIX_ACL=y
 # CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-CONFIG_ROMFS_FS=y
+CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
 # CONFIG_QUOTA is not set
-CONFIG_DNOTIFY=y
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
 # CONFIG_FUSE_FS is not set
+CONFIG_GENERIC_ACL=y
 
 #
 # CD-ROM/DVD Filesystems
 #
-# CONFIG_ISO9660_FS is not set
-# CONFIG_UDF_FS is not set
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+# CONFIG_ZISOFS is not set
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
 
 #
 # DOS/FAT/NT Filesystems
@@ -1222,7 +1407,9 @@ CONFIG_MSDOS_FS=y
 CONFIG_VFAT_FS=y
 CONFIG_FAT_DEFAULT_CODEPAGE=437
 CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-# CONFIG_NTFS_FS is not set
+CONFIG_NTFS_FS=m
+# CONFIG_NTFS_DEBUG is not set
+# CONFIG_NTFS_RW is not set
 
 #
 # Pseudo filesystems
@@ -1230,10 +1417,10 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 CONFIG_PROC_FS=y
 CONFIG_PROC_SYSCTL=y
 CONFIG_SYSFS=y
-# CONFIG_TMPFS is not set
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
-# CONFIG_CONFIGFS_FS is not set
+CONFIG_CONFIGFS_FS=m
 
 #
 # Miscellaneous filesystems
@@ -1248,31 +1435,32 @@ CONFIG_RAMFS=y
 CONFIG_JFFS2_FS=y
 CONFIG_JFFS2_FS_DEBUG=0
 CONFIG_JFFS2_FS_WRITEBUFFER=y
-# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+CONFIG_JFFS2_SUMMARY=y
 # CONFIG_JFFS2_FS_XATTR is not set
 # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
 CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
 CONFIG_JFFS2_RTIME=y
 # CONFIG_JFFS2_RUBIN is not set
 CONFIG_CRAMFS=y
 # CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
+CONFIG_ROMFS_FS=y
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
+CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=y
 # CONFIG_NFS_V3 is not set
 # CONFIG_NFS_V4 is not set
-# CONFIG_NFS_DIRECTIO is not set
 # CONFIG_NFSD is not set
 CONFIG_ROOT_NFS=y
 CONFIG_LOCKD=y
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 # CONFIG_SMB_FS is not set
@@ -1280,7 +1468,6 @@ CONFIG_SUNRPC=y
 # CONFIG_NCP_FS is not set
 # CONFIG_CODA_FS is not set
 # CONFIG_AFS_FS is not set
-# CONFIG_9P_FS is not set
 
 #
 # Partition Types
@@ -1302,94 +1489,93 @@ CONFIG_SOLARIS_X86_PARTITION=y
 # CONFIG_SUN_PARTITION is not set
 # CONFIG_KARMA_PARTITION is not set
 # CONFIG_EFI_PARTITION is not set
-
-#
-# Native Language Support
-#
+# CONFIG_SYSV68_PARTITION is not set
 CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="iso8859-1"
-# CONFIG_NLS_CODEPAGE_437 is not set
-# CONFIG_NLS_CODEPAGE_737 is not set
-# CONFIG_NLS_CODEPAGE_775 is not set
-# CONFIG_NLS_CODEPAGE_850 is not set
-# CONFIG_NLS_CODEPAGE_852 is not set
-# CONFIG_NLS_CODEPAGE_855 is not set
-# CONFIG_NLS_CODEPAGE_857 is not set
-# CONFIG_NLS_CODEPAGE_860 is not set
-# CONFIG_NLS_CODEPAGE_861 is not set
-# CONFIG_NLS_CODEPAGE_862 is not set
-# CONFIG_NLS_CODEPAGE_863 is not set
-# CONFIG_NLS_CODEPAGE_864 is not set
-# CONFIG_NLS_CODEPAGE_865 is not set
-# CONFIG_NLS_CODEPAGE_866 is not set
-# CONFIG_NLS_CODEPAGE_869 is not set
-# CONFIG_NLS_CODEPAGE_936 is not set
-# CONFIG_NLS_CODEPAGE_950 is not set
-# CONFIG_NLS_CODEPAGE_932 is not set
-# CONFIG_NLS_CODEPAGE_949 is not set
-# CONFIG_NLS_CODEPAGE_874 is not set
-# CONFIG_NLS_ISO8859_8 is not set
-# CONFIG_NLS_CODEPAGE_1250 is not set
-# CONFIG_NLS_CODEPAGE_1251 is not set
-# CONFIG_NLS_ASCII is not set
-# CONFIG_NLS_ISO8859_1 is not set
-# CONFIG_NLS_ISO8859_2 is not set
-# CONFIG_NLS_ISO8859_3 is not set
-# CONFIG_NLS_ISO8859_4 is not set
-# CONFIG_NLS_ISO8859_5 is not set
-# CONFIG_NLS_ISO8859_6 is not set
-# CONFIG_NLS_ISO8859_7 is not set
-# CONFIG_NLS_ISO8859_9 is not set
-# CONFIG_NLS_ISO8859_13 is not set
-# CONFIG_NLS_ISO8859_14 is not set
-# CONFIG_NLS_ISO8859_15 is not set
-# CONFIG_NLS_KOI8_R is not set
-# CONFIG_NLS_KOI8_U is not set
-# CONFIG_NLS_UTF8 is not set
-
-#
-# Distributed Lock Manager
-#
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_737=m
+CONFIG_NLS_CODEPAGE_775=m
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_CODEPAGE_852=m
+CONFIG_NLS_CODEPAGE_855=m
+CONFIG_NLS_CODEPAGE_857=m
+CONFIG_NLS_CODEPAGE_860=m
+CONFIG_NLS_CODEPAGE_861=m
+CONFIG_NLS_CODEPAGE_862=m
+CONFIG_NLS_CODEPAGE_863=m
+CONFIG_NLS_CODEPAGE_864=m
+CONFIG_NLS_CODEPAGE_865=m
+CONFIG_NLS_CODEPAGE_866=m
+CONFIG_NLS_CODEPAGE_869=m
+CONFIG_NLS_CODEPAGE_936=m
+CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_CODEPAGE_932=m
+CONFIG_NLS_CODEPAGE_949=m
+CONFIG_NLS_CODEPAGE_874=m
+CONFIG_NLS_ISO8859_8=m
+CONFIG_NLS_CODEPAGE_1250=m
+CONFIG_NLS_CODEPAGE_1251=m
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=m
+CONFIG_NLS_ISO8859_3=m
+CONFIG_NLS_ISO8859_4=m
+CONFIG_NLS_ISO8859_5=m
+CONFIG_NLS_ISO8859_6=m
+CONFIG_NLS_ISO8859_7=m
+CONFIG_NLS_ISO8859_9=m
+CONFIG_NLS_ISO8859_13=m
+CONFIG_NLS_ISO8859_14=m
+CONFIG_NLS_ISO8859_15=m
+CONFIG_NLS_KOI8_R=m
+CONFIG_NLS_KOI8_U=m
+CONFIG_NLS_UTF8=m
 # CONFIG_DLM is not set
 
 #
-# Profiling support
-#
-# CONFIG_PROFILING is not set
-
-#
 # Kernel hacking
 #
 # CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
 CONFIG_MAGIC_SYSRQ=y
 # CONFIG_UNUSED_SYMBOLS is not set
 # CONFIG_DEBUG_FS is not set
 # CONFIG_HEADERS_CHECK is not set
 CONFIG_DEBUG_KERNEL=y
 # CONFIG_DEBUG_SHIRQ is not set
-CONFIG_LOG_BUF_SHIFT=16
 CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
 # CONFIG_SCHEDSTATS is not set
 # CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
 # CONFIG_DEBUG_SLAB is not set
 # CONFIG_DEBUG_RT_MUTEXES is not set
 # CONFIG_RT_MUTEX_TESTER is not set
 # CONFIG_DEBUG_SPINLOCK is not set
 CONFIG_DEBUG_MUTEXES=y
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
 # CONFIG_DEBUG_SPINLOCK_SLEEP is not set
 # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
 # CONFIG_DEBUG_KOBJECT is not set
 CONFIG_DEBUG_BUGVERBOSE=y
 CONFIG_DEBUG_INFO=y
 # CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
 # CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
 CONFIG_FRAME_POINTER=y
-CONFIG_FORCED_INLINING=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
 # CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
 CONFIG_DEBUG_USER=y
-# CONFIG_DEBUG_ERRORS is not set
+CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_STACK_USAGE is not set
 CONFIG_DEBUG_LL=y
 # CONFIG_DEBUG_ICEDCC is not set
 CONFIG_DEBUG_S3C_PORT=y
@@ -1400,21 +1586,100 @@ CONFIG_DEBUG_S3C_UART=0
 #
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=m
+CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_BLKCIPHER=m
+CONFIG_CRYPTO_HASH=m
+CONFIG_CRYPTO_MANAGER=m
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_AUTHENC=m
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=m
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=m
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=m
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=m
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+CONFIG_CRYPTO_SHA1=m
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=m
+# CONFIG_CRYPTO_ANUBIS is not set
+CONFIG_CRYPTO_ARC4=m
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=m
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
 
 #
-# Cryptographic options
+# Compression
 #
-# CONFIG_CRYPTO is not set
+CONFIG_CRYPTO_DEFLATE=m
+# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_HW=y
 
 #
 # Library routines
 #
 CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+# CONFIG_GENERIC_FIND_NEXT_BIT is not set
 # CONFIG_CRC_CCITT is not set
 # CONFIG_CRC16 is not set
+CONFIG_CRC_ITU_T=m
 CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
 CONFIG_ZLIB_DEFLATE=y
 CONFIG_PLIST=y
 CONFIG_HAS_IOMEM=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/sam9_l9260_defconfig b/arch/arm/configs/sam9_l9260_defconfig
index 484dc9739dfc..8688362bcf7b 100644
--- a/arch/arm/configs/sam9_l9260_defconfig
+++ b/arch/arm/configs/sam9_l9260_defconfig
@@ -211,7 +211,6 @@ CONFIG_ARM_THUMB=y
 #
 # CONFIG_TICK_ONESHOT is not set
 CONFIG_PREEMPT=y
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
 # CONFIG_AEABI is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/spitz_defconfig b/arch/arm/configs/spitz_defconfig
index aa7a01179500..7d59fb1f1cea 100644
--- a/arch/arm/configs/spitz_defconfig
+++ b/arch/arm/configs/spitz_defconfig
@@ -164,7 +164,6 @@ CONFIG_PCMCIA_PXA2XX=y
 # Kernel Features
 #
 CONFIG_PREEMPT=y
-# CONFIG_NO_IDLE_HZ is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
 CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_FLATMEM_MANUAL=y
diff --git a/arch/arm/configs/tct_hammer_defconfig b/arch/arm/configs/tct_hammer_defconfig
index 576b8339f0d6..07dfb98df4f0 100644
--- a/arch/arm/configs/tct_hammer_defconfig
+++ b/arch/arm/configs/tct_hammer_defconfig
@@ -247,7 +247,6 @@ CONFIG_ARM_THUMB=y
 #
 # CONFIG_TICK_ONESHOT is not set
 # CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=200
 # CONFIG_AEABI is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/trizeps4_defconfig b/arch/arm/configs/trizeps4_defconfig
index 6db6392806f9..8b7a431a8bfc 100644
--- a/arch/arm/configs/trizeps4_defconfig
+++ b/arch/arm/configs/trizeps4_defconfig
@@ -195,7 +195,6 @@ CONFIG_PCMCIA_PXA2XX=y
 # Kernel Features
 #
 CONFIG_PREEMPT=y
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
 CONFIG_AEABI=y
 CONFIG_OABI_COMPAT=y
diff --git a/arch/arm/configs/usb-a9260_defconfig b/arch/arm/configs/usb-a9260_defconfig
new file mode 100644
index 000000000000..3680bd2df26d
--- /dev/null
+++ b/arch/arm/configs/usb-a9260_defconfig
@@ -0,0 +1,1142 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.24
+# Tue Apr 15 11:39:35 2008
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_FAIR_USER_SCHED=y
+# CONFIG_FAIR_CGROUP_SCHED is not set
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_RELAY is not set
+# CONFIG_BLK_DEV_INITRD is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+CONFIG_ARCH_AT91=y
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# Atmel AT91 System-on-Chip
+#
+# CONFIG_ARCH_AT91RM9200 is not set
+CONFIG_ARCH_AT91SAM9260=y
+# CONFIG_ARCH_AT91SAM9261 is not set
+# CONFIG_ARCH_AT91SAM9263 is not set
+# CONFIG_ARCH_AT91SAM9RL is not set
+# CONFIG_ARCH_AT91CAP9 is not set
+# CONFIG_ARCH_AT91X40 is not set
+CONFIG_AT91_PMC_UNIT=y
+
+#
+# AT91SAM9260 Variants
+#
+# CONFIG_ARCH_AT91SAM9260_SAM9XE is not set
+
+#
+# AT91SAM9260 / AT91SAM9XE Board Type
+#
+# CONFIG_MACH_AT91SAM9260EK is not set
+# CONFIG_MACH_CAM60 is not set
+# CONFIG_MACH_SAM9_L9260 is not set
+CONFIG_MACH_USB_A9260=y
+# CONFIG_MACH_QIL_A9260 is not set
+
+#
+# AT91 Board Options
+#
+
+#
+# AT91 Feature Selections
+#
+# CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set
+CONFIG_AT91_SLOW_CLOCK=y
+CONFIG_AT91_TIMER_HZ=100
+CONFIG_AT91_EARLY_DBGU=y
+# CONFIG_AT91_EARLY_USART0 is not set
+# CONFIG_AT91_EARLY_USART1 is not set
+# CONFIG_AT91_EARLY_USART2 is not set
+# CONFIG_AT91_EARLY_USART3 is not set
+# CONFIG_AT91_EARLY_USART4 is not set
+# CONFIG_AT91_EARLY_USART5 is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+# CONFIG_ARM_THUMB is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=100
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="mem=64M console=ttyS0,115200"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_LEGACY is not set
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND_UP_POSSIBLE=y
+CONFIG_SUSPEND=y
+# CONFIG_APM_EMULATION is not set
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ASK_IP_FIB_HASH=y
+# CONFIG_IP_FIB_TRIE is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_MULTIPLE_TABLES is not set
+# CONFIG_IP_ROUTE_MULTIPATH is not set
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+CONFIG_IP_MROUTE=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+CONFIG_MTD_DATAFLASH=y
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+CONFIG_MTD_NAND_AT91=y
+CONFIG_MTD_NAND_AT91_ECC_SOFT=y
+# CONFIG_MTD_NAND_AT91_ECC_HW is not set
+# CONFIG_MTD_NAND_AT91_ECC_NONE is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MISC_DEVICES is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_MACB=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+CONFIG_NETDEV_1000=y
+CONFIG_NETDEV_10000=y
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_EVBUG=y
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_ATMEL=y
+CONFIG_SERIAL_ATMEL_CONSOLE=y
+# CONFIG_SERIAL_ATMEL_TTYAT is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+
+#
+# SPI support
+#
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+CONFIG_SPI_ATMEL=y
+# CONFIG_SPI_BITBANG is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_AT25 is not set
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+# CONFIG_USB_HID is not set
+
+#
+# USB HID Boot Protocol drivers
+#
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_SUSPEND is not set
+# CONFIG_USB_PERSIST is not set
+# CONFIG_USB_OTG is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_ISP116X_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+CONFIG_USB_MON=y
+
+#
+# USB port drivers
+#
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+
+#
+# USB DSL modem support
+#
+
+#
+# USB Gadget Support
+#
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_PXA2XX is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+CONFIG_USB_GADGET_AT91=y
+CONFIG_USB_AT91=y
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+# CONFIG_USB_GADGET_DUALSPEED is not set
+# CONFIG_USB_ZERO is not set
+CONFIG_USB_ETH=y
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FILE_STORAGE is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_MMC is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+CONFIG_LEDS_GPIO=y
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+# CONFIG_LEDS_TRIGGER_TIMER is not set
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4DEV_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=m
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+# CONFIG_MSDOS_FS is not set
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_ACL_SUPPORT=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+# CONFIG_SUNRPC_BIND34 is not set
+CONFIG_RPCSEC_GSS_KRB5=y
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+CONFIG_NLS_CODEPAGE_850=y
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+# CONFIG_INSTRUMENTATION is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+CONFIG_FRAME_POINTER=y
+CONFIG_FORCED_INLINING=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
+CONFIG_DEBUG_USER=y
+# CONFIG_DEBUG_ERRORS is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_MANAGER=y
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_WP512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_ECB is not set
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_XTS is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_TEST is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_HW is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/usb-a9263_defconfig b/arch/arm/configs/usb-a9263_defconfig
new file mode 100644
index 000000000000..48d455bc7363
--- /dev/null
+++ b/arch/arm/configs/usb-a9263_defconfig
@@ -0,0 +1,1134 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.24
+# Tue Apr 15 11:15:19 2008
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_FAIR_USER_SCHED=y
+# CONFIG_FAIR_CGROUP_SCHED is not set
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_RELAY is not set
+# CONFIG_BLK_DEV_INITRD is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+CONFIG_ARCH_AT91=y
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# Atmel AT91 System-on-Chip
+#
+# CONFIG_ARCH_AT91RM9200 is not set
+# CONFIG_ARCH_AT91SAM9260 is not set
+# CONFIG_ARCH_AT91SAM9261 is not set
+CONFIG_ARCH_AT91SAM9263=y
+# CONFIG_ARCH_AT91SAM9RL is not set
+# CONFIG_ARCH_AT91CAP9 is not set
+# CONFIG_ARCH_AT91X40 is not set
+CONFIG_AT91_PMC_UNIT=y
+
+#
+# AT91SAM9263 Board Type
+#
+# CONFIG_MACH_AT91SAM9263EK is not set
+CONFIG_MACH_USB_A9263=y
+
+#
+# AT91 Board Options
+#
+
+#
+# AT91 Feature Selections
+#
+# CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set
+CONFIG_AT91_SLOW_CLOCK=y
+CONFIG_AT91_TIMER_HZ=100
+CONFIG_AT91_EARLY_DBGU=y
+# CONFIG_AT91_EARLY_USART0 is not set
+# CONFIG_AT91_EARLY_USART1 is not set
+# CONFIG_AT91_EARLY_USART2 is not set
+# CONFIG_AT91_EARLY_USART3 is not set
+# CONFIG_AT91_EARLY_USART4 is not set
+# CONFIG_AT91_EARLY_USART5 is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+# CONFIG_ARM_THUMB is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=100
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="mem=64M console=ttyS0,115200"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_LEGACY is not set
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND_UP_POSSIBLE=y
+CONFIG_SUSPEND=y
+# CONFIG_APM_EMULATION is not set
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ASK_IP_FIB_HASH=y
+# CONFIG_IP_FIB_TRIE is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_MULTIPLE_TABLES is not set
+# CONFIG_IP_ROUTE_MULTIPATH is not set
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+CONFIG_IP_MROUTE=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+CONFIG_MTD_DATAFLASH=y
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+CONFIG_MTD_NAND_AT91=y
+CONFIG_MTD_NAND_AT91_ECC_SOFT=y
+# CONFIG_MTD_NAND_AT91_ECC_HW is not set
+# CONFIG_MTD_NAND_AT91_ECC_NONE is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MISC_DEVICES is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_MACB=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+CONFIG_NETDEV_1000=y
+CONFIG_NETDEV_10000=y
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_EVBUG=y
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_ATMEL=y
+CONFIG_SERIAL_ATMEL_CONSOLE=y
+# CONFIG_SERIAL_ATMEL_TTYAT is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+
+#
+# SPI support
+#
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+CONFIG_SPI_ATMEL=y
+# CONFIG_SPI_BITBANG is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_AT25 is not set
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+# CONFIG_USB_HID is not set
+
+#
+# USB HID Boot Protocol drivers
+#
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_SUSPEND is not set
+# CONFIG_USB_PERSIST is not set
+# CONFIG_USB_OTG is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_ISP116X_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+CONFIG_USB_MON=y
+
+#
+# USB port drivers
+#
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+
+#
+# USB DSL modem support
+#
+
+#
+# USB Gadget Support
+#
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_PXA2XX is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+CONFIG_USB_GADGET_AT91=y
+CONFIG_USB_AT91=y
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+# CONFIG_USB_GADGET_DUALSPEED is not set
+# CONFIG_USB_ZERO is not set
+CONFIG_USB_ETH=y
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FILE_STORAGE is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_MMC is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+CONFIG_LEDS_GPIO=y
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+# CONFIG_LEDS_TRIGGER_TIMER is not set
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4DEV_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=m
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+# CONFIG_MSDOS_FS is not set
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_ACL_SUPPORT=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+# CONFIG_SUNRPC_BIND34 is not set
+CONFIG_RPCSEC_GSS_KRB5=y
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+CONFIG_NLS_CODEPAGE_850=y
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+# CONFIG_INSTRUMENTATION is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+CONFIG_FRAME_POINTER=y
+CONFIG_FORCED_INLINING=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
+CONFIG_DEBUG_USER=y
+# CONFIG_DEBUG_ERRORS is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_MANAGER=y
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_WP512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_ECB is not set
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_XTS is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_TEST is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_HW is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/versatile_defconfig b/arch/arm/configs/versatile_defconfig
index 48dca69addae..8355f88f7292 100644
--- a/arch/arm/configs/versatile_defconfig
+++ b/arch/arm/configs/versatile_defconfig
@@ -151,7 +151,6 @@ CONFIG_ARM_AMBA=y
 # Kernel Features
 #
 # CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
 # CONFIG_AEABI is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/cm_x270_defconfig b/arch/arm/configs/xm_x270_defconfig
index 5cab08397ae7..aa40d91ce599 100644
--- a/arch/arm/configs/cm_x270_defconfig
+++ b/arch/arm/configs/xm_x270_defconfig
@@ -1,13 +1,13 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.22
-# Wed Jul 18 14:11:48 2007
+# Linux kernel version: 2.6.25
+# Sun May 11 15:12:52 2008
 #
 CONFIG_ARM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
 CONFIG_GENERIC_GPIO=y
 CONFIG_GENERIC_TIME=y
-# CONFIG_GENERIC_CLOCKEVENTS is not set
+CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_MMU=y
 # CONFIG_NO_IOPORT is not set
 CONFIG_GENERIC_HARDIRQS=y
@@ -21,21 +21,18 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U64 is not set
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
 CONFIG_ZONE_DMA=y
 CONFIG_ARCH_MTD_XIP=y
 CONFIG_VECTORS_BASE=0xffff0000
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 
 #
-# Code maturity level options
+# General setup
 #
 CONFIG_EXPERIMENTAL=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
 CONFIG_LOCALVERSION=""
 # CONFIG_LOCALVERSION_AUTO is not set
 CONFIG_SWAP=y
@@ -44,13 +41,20 @@ CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
-# CONFIG_USER_NS is not set
 # CONFIG_AUDIT is not set
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=17
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
 CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
@@ -58,6 +62,7 @@ CONFIG_SYSCTL=y
 CONFIG_EMBEDDED=y
 CONFIG_UID16=y
 CONFIG_SYSCTL_SYSCALL=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_KALLSYMS=y
 # CONFIG_KALLSYMS_ALL is not set
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
@@ -65,24 +70,34 @@ CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 CONFIG_ELF_CORE=y
+# CONFIG_COMPAT_BRK is not set
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_ANON_INODES=y
-# CONFIG_EPOLL is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_SLAB=y
-# CONFIG_SLUB is not set
+# CONFIG_VM_EVENT_COUNTERS is not set
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
 # CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+# CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_PROC_PAGE_MONITOR is not set
 CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_KMOD=y
@@ -99,11 +114,12 @@ CONFIG_IOSCHED_NOOP=y
 CONFIG_IOSCHED_AS=y
 CONFIG_IOSCHED_DEADLINE=y
 CONFIG_IOSCHED_CFQ=y
-CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_AS is not set
 # CONFIG_DEFAULT_DEADLINE is not set
-# CONFIG_DEFAULT_CFQ is not set
+CONFIG_DEFAULT_CFQ=y
 # CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_CLASSIC_RCU=y
 
 #
 # System Type
@@ -131,6 +147,8 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
 # CONFIG_ARCH_L7200 is not set
 # CONFIG_ARCH_KS8695 is not set
 # CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
 # CONFIG_ARCH_PNX4008 is not set
 CONFIG_ARCH_PXA=y
 # CONFIG_ARCH_RPC is not set
@@ -140,19 +158,41 @@ CONFIG_ARCH_PXA=y
 # CONFIG_ARCH_LH7A40X is not set
 # CONFIG_ARCH_DAVINCI is not set
 # CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM7X00A is not set
 CONFIG_DMABOUNCE=y
 
 #
-# Intel PXA2xx Implementations
+# Intel PXA2xx/PXA3xx Implementations
 #
+
+#
+# Select target boards
+#
+# CONFIG_ARCH_GUMSTIX is not set
 # CONFIG_ARCH_LUBBOCK is not set
 # CONFIG_MACH_LOGICPD_PXA270 is not set
 # CONFIG_MACH_MAINSTONE is not set
 # CONFIG_ARCH_PXA_IDP is not set
 # CONFIG_PXA_SHARPSL is not set
+# CONFIG_ARCH_PXA_ESERIES is not set
 # CONFIG_MACH_TRIZEPS4 is not set
+CONFIG_MACH_EM_X270=y
+# CONFIG_MACH_COLIBRI is not set
+# CONFIG_MACH_ZYLONITE is not set
+# CONFIG_MACH_LITTLETON is not set
 CONFIG_MACH_ARMCORE=y
+# CONFIG_MACH_MAGICIAN is not set
+# CONFIG_MACH_PCM027 is not set
 CONFIG_PXA27x=y
+# CONFIG_PXA_PWM is not set
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
 
 #
 # Processor Type
@@ -161,6 +201,7 @@ CONFIG_CPU_32=y
 CONFIG_CPU_XSCALE=y
 CONFIG_CPU_32v5=y
 CONFIG_CPU_ABRT_EV5T=y
+CONFIG_CPU_PABRT_NOIFAR=y
 CONFIG_CPU_CACHE_VIVT=y
 CONFIG_CPU_TLB_V4WBI=y
 CONFIG_CPU_CP15=y
@@ -182,21 +223,40 @@ CONFIG_PCI=y
 CONFIG_PCI_SYSCALL=y
 CONFIG_PCI_HOST_ITE8152=y
 # CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_PCI_LEGACY=y
 # CONFIG_PCI_DEBUG is not set
+CONFIG_PCCARD=m
+# CONFIG_PCMCIA_DEBUG is not set
+CONFIG_PCMCIA=m
+CONFIG_PCMCIA_LOAD_CIS=y
+CONFIG_PCMCIA_IOCTL=y
+CONFIG_CARDBUS=y
 
 #
-# PCCARD (PCMCIA/CardBus) support
+# PC-card bridges
 #
-# CONFIG_PCCARD is not set
+CONFIG_YENTA=m
+# CONFIG_YENTA_O2 is not set
+# CONFIG_YENTA_RICOH is not set
+CONFIG_YENTA_TI=y
+# CONFIG_YENTA_ENE_TUNE is not set
+# CONFIG_YENTA_TOSHIBA is not set
+# CONFIG_PD6729 is not set
+# CONFIG_I82092 is not set
+CONFIG_PCMCIA_PXA2XX=m
+CONFIG_PCCARD_NONSTATIC=m
 
 #
 # Kernel Features
 #
-# CONFIG_TICK_ONESHOT is not set
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
 # CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
-# CONFIG_AEABI is not set
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
 CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_FLATMEM_MANUAL=y
@@ -205,6 +265,8 @@ CONFIG_FLATMEM_MANUAL=y
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
 # CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4096
 # CONFIG_RESOURCES_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
@@ -217,11 +279,16 @@ CONFIG_ALIGNMENT_TRAP=y
 #
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE=""
+CONFIG_CMDLINE="root=1f03 mem=32M"
 # CONFIG_XIP_KERNEL is not set
 # CONFIG_KEXEC is not set
 
 #
+# CPU Frequency scaling
+#
+# CONFIG_CPU_FREQ is not set
+
+#
 # Floating point emulation
 #
 
@@ -238,16 +305,17 @@ CONFIG_FPE_NWFPE=y
 CONFIG_BINFMT_ELF=y
 # CONFIG_BINFMT_AOUT is not set
 # CONFIG_BINFMT_MISC is not set
-# CONFIG_ARTHUR is not set
 
 #
 # Power management options
 #
 CONFIG_PM=y
-# CONFIG_PM_LEGACY is not set
 # CONFIG_PM_DEBUG is not set
-# CONFIG_PM_SYSFS_DEPRECATED is not set
-# CONFIG_APM_EMULATION is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_APM_EMULATION=m
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
 
 #
 # Networking
@@ -258,15 +326,16 @@ CONFIG_NET=y
 # Networking options
 #
 CONFIG_PACKET=y
-# CONFIG_PACKET_MMAP is not set
+CONFIG_PACKET_MMAP=y
 CONFIG_UNIX=y
 CONFIG_XFRM=y
 # CONFIG_XFRM_USER is not set
 # CONFIG_XFRM_SUB_POLICY is not set
 # CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
-# CONFIG_IP_MULTICAST is not set
+CONFIG_IP_MULTICAST=y
 # CONFIG_IP_ADVANCED_ROUTER is not set
 CONFIG_IP_FIB_HASH=y
 CONFIG_IP_PNP=y
@@ -275,6 +344,7 @@ CONFIG_IP_PNP_BOOTP=y
 # CONFIG_IP_PNP_RARP is not set
 # CONFIG_NET_IPIP is not set
 # CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
 # CONFIG_ARPD is not set
 # CONFIG_SYN_COOKIES is not set
 # CONFIG_INET_AH is not set
@@ -285,15 +355,13 @@ CONFIG_IP_PNP_BOOTP=y
 CONFIG_INET_XFRM_MODE_TRANSPORT=y
 CONFIG_INET_XFRM_MODE_TUNNEL=y
 CONFIG_INET_XFRM_MODE_BEET=y
-CONFIG_INET_DIAG=y
-CONFIG_INET_TCP_DIAG=y
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
 # CONFIG_TCP_CONG_ADVANCED is not set
 CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TCP_MD5SIG is not set
 # CONFIG_IPV6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
 # CONFIG_NETWORK_SECMARK is not set
 # CONFIG_NETFILTER is not set
 # CONFIG_IP_DCCP is not set
@@ -310,10 +378,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
 # CONFIG_NET_SCHED is not set
 
 #
@@ -321,8 +385,33 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 #
 # CONFIG_NET_PKTGEN is not set
 # CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
 # CONFIG_IRDA is not set
-# CONFIG_BT is not set
+CONFIG_BT=m
+CONFIG_BT_L2CAP=m
+CONFIG_BT_SCO=m
+CONFIG_BT_RFCOMM=m
+# CONFIG_BT_RFCOMM_TTY is not set
+CONFIG_BT_BNEP=m
+# CONFIG_BT_BNEP_MC_FILTER is not set
+# CONFIG_BT_BNEP_PROTO_FILTER is not set
+CONFIG_BT_HIDP=m
+
+#
+# Bluetooth device drivers
+#
+CONFIG_BT_HCIUSB=m
+CONFIG_BT_HCIUSB_SCO=y
+# CONFIG_BT_HCIBTSDIO is not set
+# CONFIG_BT_HCIUART is not set
+# CONFIG_BT_HCIBCM203X is not set
+# CONFIG_BT_HCIBPA10X is not set
+# CONFIG_BT_HCIBFUSB is not set
+# CONFIG_BT_HCIDTL1 is not set
+# CONFIG_BT_HCIBT3C is not set
+# CONFIG_BT_HCIBLUECARD is not set
+# CONFIG_BT_HCIBTUART is not set
+# CONFIG_BT_HCIVHCI is not set
 # CONFIG_AF_RXRPC is not set
 
 #
@@ -331,12 +420,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_CFG80211 is not set
 CONFIG_WIRELESS_EXT=y
 # CONFIG_MAC80211 is not set
-CONFIG_IEEE80211=m
-# CONFIG_IEEE80211_DEBUG is not set
-CONFIG_IEEE80211_CRYPT_WEP=m
-CONFIG_IEEE80211_CRYPT_CCMP=m
-# CONFIG_IEEE80211_CRYPT_TKIP is not set
-# CONFIG_IEEE80211_SOFTMAC is not set
+# CONFIG_IEEE80211 is not set
 # CONFIG_RFKILL is not set
 # CONFIG_NET_9P is not set
 
@@ -347,38 +431,47 @@ CONFIG_IEEE80211_CRYPT_CCMP=m
 #
 # Generic Driver Options
 #
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=y
+CONFIG_FW_LOADER=m
 # CONFIG_DEBUG_DRIVER is not set
 # CONFIG_DEBUG_DEVRES is not set
 # CONFIG_SYS_HYPERVISOR is not set
 # CONFIG_CONNECTOR is not set
-CONFIG_MTD=m
+CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
 # CONFIG_MTD_CONCAT is not set
 CONFIG_MTD_PARTITIONS=y
 # CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
 # CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
 
 #
 # User Modules And Translation Layers
 #
-CONFIG_MTD_CHAR=m
-CONFIG_MTD_BLKDEVS=m
-CONFIG_MTD_BLOCK=m
-# CONFIG_MTD_BLOCK_RO is not set
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
 # CONFIG_FTL is not set
 # CONFIG_NFTL is not set
 # CONFIG_INFTL is not set
 # CONFIG_RFD_FTL is not set
 # CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
 
 #
 # RAM/ROM/Flash chip drivers
 #
-# CONFIG_MTD_CFI is not set
-# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_GEOMETRY is not set
 CONFIG_MTD_MAP_BANK_WIDTH_1=y
 CONFIG_MTD_MAP_BANK_WIDTH_2=y
 CONFIG_MTD_MAP_BANK_WIDTH_4=y
@@ -389,15 +482,29 @@ CONFIG_MTD_CFI_I1=y
 CONFIG_MTD_CFI_I2=y
 # CONFIG_MTD_CFI_I4 is not set
 # CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_OTP is not set
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_CFI_UTIL=y
 # CONFIG_MTD_RAM is not set
 # CONFIG_MTD_ROM is not set
 # CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_XIP is not set
 
 #
 # Mapping drivers for chip access
 #
 # CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_START=0x0
+CONFIG_MTD_PHYSMAP_LEN=0x400000
+CONFIG_MTD_PHYSMAP_BANKWIDTH=2
+CONFIG_MTD_PXA2XX=y
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_IMPA7 is not set
 # CONFIG_MTD_SHARP_SL is not set
+# CONFIG_MTD_INTEL_VR_NOR is not set
 # CONFIG_MTD_PLATRAM is not set
 
 #
@@ -415,18 +522,19 @@ CONFIG_MTD_CFI_I2=y
 # CONFIG_MTD_DOC2000 is not set
 # CONFIG_MTD_DOC2001 is not set
 # CONFIG_MTD_DOC2001PLUS is not set
-CONFIG_MTD_NAND=m
+CONFIG_MTD_NAND=y
 # CONFIG_MTD_NAND_VERIFY_WRITE is not set
 # CONFIG_MTD_NAND_ECC_SMC is not set
 # CONFIG_MTD_NAND_MUSEUM_IDS is not set
 # CONFIG_MTD_NAND_H1900 is not set
-CONFIG_MTD_NAND_IDS=m
+CONFIG_MTD_NAND_IDS=y
 # CONFIG_MTD_NAND_DISKONCHIP is not set
 # CONFIG_MTD_NAND_SHARPSL is not set
 # CONFIG_MTD_NAND_CAFE is not set
-CONFIG_MTD_NAND_CM_X270=m
+CONFIG_MTD_NAND_CM_X270=y
 # CONFIG_MTD_NAND_NANDSIM is not set
-# CONFIG_MTD_NAND_PLATFORM is not set
+CONFIG_MTD_NAND_PLATFORM=y
+# CONFIG_MTD_ALAUDA is not set
 # CONFIG_MTD_ONENAND is not set
 
 #
@@ -447,36 +555,13 @@ CONFIG_BLK_DEV_LOOP=y
 # CONFIG_BLK_DEV_UB is not set
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=12000
-CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
-CONFIG_IDE=m
-CONFIG_IDE_MAX_HWIFS=4
-CONFIG_BLK_DEV_IDE=m
-
-#
-# Please see Documentation/ide.txt for help/info on IDE drives
-#
-# CONFIG_BLK_DEV_IDE_SATA is not set
-CONFIG_BLK_DEV_IDEDISK=m
-# CONFIG_IDEDISK_MULTI_MODE is not set
-CONFIG_BLK_DEV_IDECD=m
-# CONFIG_BLK_DEV_IDETAPE is not set
-# CONFIG_BLK_DEV_IDEFLOPPY is not set
-# CONFIG_BLK_DEV_IDESCSI is not set
-# CONFIG_IDE_TASK_IOCTL is not set
-CONFIG_IDE_PROC_FS=y
-
-#
-# IDE chipset support/bugfixes
-#
-# CONFIG_IDE_GENERIC is not set
-# CONFIG_BLK_DEV_IDEPCI is not set
-# CONFIG_IDEPCI_PCIBUS_ORDER is not set
-# CONFIG_IDE_ARM is not set
-# CONFIG_BLK_DEV_IDEDMA is not set
-# CONFIG_BLK_DEV_HD is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
 
 #
 # SCSI device support
@@ -486,7 +571,7 @@ CONFIG_SCSI=y
 CONFIG_SCSI_DMA=y
 # CONFIG_SCSI_TGT is not set
 # CONFIG_SCSI_NETLINK is not set
-# CONFIG_SCSI_PROC_FS is not set
+CONFIG_SCSI_PROC_FS=y
 
 #
 # SCSI support type (disk, tape, CD-ROM)
@@ -513,12 +598,9 @@ CONFIG_SCSI_WAIT_SCAN=m
 # CONFIG_SCSI_SPI_ATTRS is not set
 # CONFIG_SCSI_FC_ATTRS is not set
 # CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_ATTRS is not set
 # CONFIG_SCSI_SAS_LIBSAS is not set
-
-#
-# SCSI low-level drivers
-#
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
 # CONFIG_ISCSI_TCP is not set
 # CONFIG_BLK_DEV_3W_XXXX_RAID is not set
 # CONFIG_SCSI_3W_9XXX is not set
@@ -529,6 +611,7 @@ CONFIG_SCSI_WAIT_SCAN=m
 # CONFIG_SCSI_AIC79XX is not set
 # CONFIG_SCSI_AIC94XX is not set
 # CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
 # CONFIG_SCSI_ARCMSR is not set
 # CONFIG_MEGARAID_NEWGEN is not set
 # CONFIG_MEGARAID_LEGACY is not set
@@ -539,8 +622,10 @@ CONFIG_SCSI_WAIT_SCAN=m
 # CONFIG_SCSI_IPS is not set
 # CONFIG_SCSI_INITIO is not set
 # CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_MVSAS is not set
 # CONFIG_SCSI_STEX is not set
 # CONFIG_SCSI_SYM53C8XX_2 is not set
+# CONFIG_SCSI_IPR is not set
 # CONFIG_SCSI_QLOGIC_1280 is not set
 # CONFIG_SCSI_QLA_FC is not set
 # CONFIG_SCSI_QLA_ISCSI is not set
@@ -550,16 +635,69 @@ CONFIG_SCSI_WAIT_SCAN=m
 # CONFIG_SCSI_NSP32 is not set
 # CONFIG_SCSI_DEBUG is not set
 # CONFIG_SCSI_SRP is not set
-# CONFIG_ATA is not set
+# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
+CONFIG_ATA=m
+# CONFIG_ATA_NONSTANDARD is not set
+# CONFIG_SATA_PMP is not set
+# CONFIG_SATA_AHCI is not set
+# CONFIG_SATA_SIL24 is not set
+CONFIG_ATA_SFF=y
+# CONFIG_SATA_SVW is not set
+# CONFIG_ATA_PIIX is not set
+# CONFIG_SATA_MV is not set
+# CONFIG_SATA_NV is not set
+# CONFIG_PDC_ADMA is not set
+# CONFIG_SATA_QSTOR is not set
+# CONFIG_SATA_PROMISE is not set
+# CONFIG_SATA_SX4 is not set
+# CONFIG_SATA_SIL is not set
+# CONFIG_SATA_SIS is not set
+# CONFIG_SATA_ULI is not set
+# CONFIG_SATA_VIA is not set
+# CONFIG_SATA_VITESSE is not set
+# CONFIG_SATA_INIC162X is not set
+# CONFIG_PATA_ALI is not set
+# CONFIG_PATA_AMD is not set
+# CONFIG_PATA_ARTOP is not set
+# CONFIG_PATA_ATIIXP is not set
+# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_CMD64X is not set
+# CONFIG_PATA_CS5520 is not set
+# CONFIG_PATA_CS5530 is not set
+# CONFIG_PATA_CYPRESS is not set
+# CONFIG_PATA_EFAR is not set
+# CONFIG_ATA_GENERIC is not set
+# CONFIG_PATA_HPT366 is not set
+# CONFIG_PATA_HPT37X is not set
+# CONFIG_PATA_HPT3X2N is not set
+# CONFIG_PATA_HPT3X3 is not set
+# CONFIG_PATA_IT821X is not set
+# CONFIG_PATA_IT8213 is not set
+# CONFIG_PATA_JMICRON is not set
+# CONFIG_PATA_TRIFLEX is not set
+# CONFIG_PATA_MARVELL is not set
+# CONFIG_PATA_MPIIX is not set
+# CONFIG_PATA_OLDPIIX is not set
+# CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
+# CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_NS87415 is not set
+# CONFIG_PATA_OPTI is not set
+# CONFIG_PATA_OPTIDMA is not set
+CONFIG_PATA_PCMCIA=m
+# CONFIG_PATA_PDC_OLD is not set
+# CONFIG_PATA_RADISYS is not set
+# CONFIG_PATA_RZ1000 is not set
+# CONFIG_PATA_SC1200 is not set
+# CONFIG_PATA_SERVERWORKS is not set
+# CONFIG_PATA_PDC2027X is not set
+# CONFIG_PATA_SIL680 is not set
+# CONFIG_PATA_SIS is not set
+# CONFIG_PATA_VIA is not set
+# CONFIG_PATA_WINBOND is not set
+# CONFIG_PATA_PLATFORM is not set
 # CONFIG_MD is not set
-
-#
-# Fusion MPT device support
-#
 # CONFIG_FUSION is not set
-# CONFIG_FUSION_SPI is not set
-# CONFIG_FUSION_FC is not set
-# CONFIG_FUSION_SAS is not set
 
 #
 # IEEE 1394 (FireWire) support
@@ -574,6 +712,7 @@ CONFIG_NETDEVICES=y
 # CONFIG_MACVLAN is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
+# CONFIG_VETH is not set
 # CONFIG_ARCNET is not set
 # CONFIG_PHYLIB is not set
 CONFIG_NET_ETHERNET=y
@@ -585,64 +724,65 @@ CONFIG_MII=y
 # CONFIG_NET_VENDOR_3COM is not set
 # CONFIG_SMC91X is not set
 CONFIG_DM9000=y
+CONFIG_DM9000_DEBUGLEVEL=1
 # CONFIG_SMC911X is not set
 # CONFIG_NET_TULIP is not set
 # CONFIG_HP100 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
 CONFIG_NET_PCI=y
 # CONFIG_PCNET32 is not set
 # CONFIG_AMD8111_ETH is not set
 # CONFIG_ADAPTEC_STARFIRE is not set
 # CONFIG_B44 is not set
 # CONFIG_FORCEDETH is not set
-# CONFIG_DGRS is not set
 # CONFIG_EEPRO100 is not set
 # CONFIG_E100 is not set
 # CONFIG_FEALNX is not set
 # CONFIG_NATSEMI is not set
 # CONFIG_NE2K_PCI is not set
 # CONFIG_8139CP is not set
-CONFIG_8139TOO=m
+CONFIG_8139TOO=y
 # CONFIG_8139TOO_PIO is not set
 # CONFIG_8139TOO_TUNE_TWISTER is not set
 # CONFIG_8139TOO_8129 is not set
 # CONFIG_8139_OLD_RX_RESET is not set
+# CONFIG_R6040 is not set
 # CONFIG_SIS900 is not set
 # CONFIG_EPIC100 is not set
 # CONFIG_SUNDANCE is not set
 # CONFIG_TLAN is not set
 # CONFIG_VIA_RHINE is not set
 # CONFIG_SC92031 is not set
-CONFIG_NETDEV_1000=y
-# CONFIG_ACENIC is not set
-# CONFIG_DL2K is not set
-# CONFIG_E1000 is not set
-# CONFIG_NS83820 is not set
-# CONFIG_HAMACHI is not set
-# CONFIG_YELLOWFIN is not set
-# CONFIG_R8169 is not set
-# CONFIG_SIS190 is not set
-# CONFIG_SKGE is not set
-# CONFIG_SKY2 is not set
-# CONFIG_VIA_VELOCITY is not set
-# CONFIG_TIGON3 is not set
-# CONFIG_BNX2 is not set
-# CONFIG_QLA3XXX is not set
-# CONFIG_ATL1 is not set
-CONFIG_NETDEV_10000=y
-# CONFIG_CHELSIO_T1 is not set
-# CONFIG_CHELSIO_T3 is not set
-# CONFIG_IXGB is not set
-# CONFIG_S2IO is not set
-# CONFIG_MYRI10GE is not set
-# CONFIG_NETXEN_NIC is not set
-# CONFIG_MLX4_CORE is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
 # CONFIG_TR is not set
 
 #
 # Wireless LAN
 #
 # CONFIG_WLAN_PRE80211 is not set
-# CONFIG_WLAN_80211 is not set
+CONFIG_WLAN_80211=y
+# CONFIG_PCMCIA_RAYCS is not set
+# CONFIG_IPW2100 is not set
+# CONFIG_IPW2200 is not set
+CONFIG_LIBERTAS=m
+# CONFIG_LIBERTAS_USB is not set
+# CONFIG_LIBERTAS_CS is not set
+CONFIG_LIBERTAS_SDIO=m
+# CONFIG_LIBERTAS_DEBUG is not set
+# CONFIG_HERMES is not set
+# CONFIG_ATMEL is not set
+# CONFIG_AIRO_CS is not set
+# CONFIG_PCMCIA_WL3501 is not set
+# CONFIG_PRISM54 is not set
+# CONFIG_USB_ZD1201 is not set
+# CONFIG_USB_NET_RNDIS_WLAN is not set
+# CONFIG_IWLWIFI is not set
+# CONFIG_IWLWIFI_LEDS is not set
+# CONFIG_HOSTAP is not set
 
 #
 # USB Network Adapters
@@ -651,15 +791,24 @@ CONFIG_NETDEV_10000=y
 # CONFIG_USB_KAWETH is not set
 # CONFIG_USB_PEGASUS is not set
 # CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET_MII is not set
 # CONFIG_USB_USBNET is not set
+# CONFIG_NET_PCMCIA is not set
 # CONFIG_WAN is not set
 # CONFIG_FDDI is not set
 # CONFIG_HIPPI is not set
-# CONFIG_PPP is not set
+CONFIG_PPP=m
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_ASYNC=m
+# CONFIG_PPP_SYNC_TTY is not set
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_BSDCOMP=m
+# CONFIG_PPP_MPPE is not set
+# CONFIG_PPPOE is not set
+# CONFIG_PPPOL2TP is not set
 # CONFIG_SLIP is not set
+CONFIG_SLHC=m
 # CONFIG_NET_FC is not set
-# CONFIG_SHAPER is not set
 # CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
@@ -675,20 +824,32 @@ CONFIG_INPUT=y
 #
 # Userland interfaces
 #
-# CONFIG_INPUT_MOUSEDEV is not set
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 # CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
 CONFIG_INPUT_EVDEV=y
 # CONFIG_INPUT_EVBUG is not set
+# CONFIG_INPUT_APMPOWER is not set
 
 #
 # Input Device Drivers
 #
-# CONFIG_INPUT_KEYBOARD is not set
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_ATKBD=y
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+CONFIG_KEYBOARD_PXA27x=m
+# CONFIG_KEYBOARD_GPIO is not set
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_INPUT_JOYSTICK is not set
 # CONFIG_INPUT_TABLET is not set
 CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
 # CONFIG_TOUCHSCREEN_GUNZE is not set
 # CONFIG_TOUCHSCREEN_ELO is not set
 # CONFIG_TOUCHSCREEN_MTOUCH is not set
@@ -697,13 +858,22 @@ CONFIG_INPUT_TOUCHSCREEN=y
 # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
 # CONFIG_TOUCHSCREEN_TOUCHWIN is not set
 CONFIG_TOUCHSCREEN_UCB1400=m
+CONFIG_TOUCHSCREEN_WM97XX=m
+# CONFIG_TOUCHSCREEN_WM9705 is not set
+CONFIG_TOUCHSCREEN_WM9712=y
+# CONFIG_TOUCHSCREEN_WM9713 is not set
+# CONFIG_TOUCHSCREEN_WM97XX_MAINSTONE is not set
 # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
 # CONFIG_INPUT_MISC is not set
 
 #
 # Hardware I/O ports
 #
-# CONFIG_SERIO is not set
+CONFIG_SERIO=y
+# CONFIG_SERIO_SERPORT is not set
+# CONFIG_SERIO_PCIPS2 is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
 # CONFIG_GAMEPORT is not set
 
 #
@@ -713,7 +883,9 @@ CONFIG_VT=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
 # CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
 # CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
 
 #
 # Serial drivers
@@ -730,83 +902,141 @@ CONFIG_SERIAL_CORE_CONSOLE=y
 # CONFIG_SERIAL_JSM is not set
 CONFIG_UNIX98_PTYS=y
 CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
+CONFIG_LEGACY_PTY_COUNT=16
 # CONFIG_IPMI_HANDLER is not set
-# CONFIG_WATCHDOG is not set
-CONFIG_HW_RANDOM=m
+# CONFIG_HW_RANDOM is not set
 # CONFIG_NVRAM is not set
 # CONFIG_R3964 is not set
 # CONFIG_APPLICOM is not set
-# CONFIG_DRM is not set
+
+#
+# PCMCIA character devices
+#
+# CONFIG_SYNCLINK_CS is not set
+# CONFIG_CARDMAN_4000 is not set
+# CONFIG_CARDMAN_4040 is not set
+# CONFIG_IPWIRELESS is not set
 # CONFIG_RAW_DRIVER is not set
 # CONFIG_TCG_TPM is not set
 CONFIG_DEVPORT=y
-# CONFIG_I2C is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=m
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_I810 is not set
+CONFIG_I2C_PXA=y
+# CONFIG_I2C_PXA_SLAVE is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_PROSAVAGE is not set
+# CONFIG_I2C_SAVAGE4 is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_TINY_USB is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+# CONFIG_I2C_VOODOO3 is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+# CONFIG_SPI is not set
+CONFIG_HAVE_GPIO_LIB=y
 
 #
-# SPI support
+# GPIO Support
 #
-# CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
-# CONFIG_W1 is not set
-# CONFIG_HWMON is not set
-CONFIG_MISC_DEVICES=y
-# CONFIG_PHANTOM is not set
-# CONFIG_EEPROM_93CX6 is not set
-# CONFIG_SGI_IOC4 is not set
-# CONFIG_TIFM_CORE is not set
+# CONFIG_DEBUG_GPIO is not set
 
 #
-# Multifunction device drivers
+# I2C GPIO expanders:
 #
-# CONFIG_MFD_SM501 is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
 
 #
-# LED devices
+# SPI GPIO expanders:
 #
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_WATCHDOG is not set
 
 #
-# LED drivers
+# Sonics Silicon Backplane
 #
-CONFIG_LEDS_CM_X270=y
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
 
 #
-# LED Triggers
+# Multifunction device drivers
 #
-CONFIG_LEDS_TRIGGERS=y
-# CONFIG_LEDS_TRIGGER_TIMER is not set
-# CONFIG_LEDS_TRIGGER_IDE_DISK is not set
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
 
 #
 # Multimedia devices
 #
+
+#
+# Multimedia core support
+#
 # CONFIG_VIDEO_DEV is not set
 # CONFIG_DVB_CORE is not set
-CONFIG_DAB=y
-# CONFIG_USB_DABUSB is not set
 
 #
-# Graphics support
+# Multimedia drivers
 #
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+# CONFIG_DAB is not set
 
 #
-# Display device support
+# Graphics support
 #
-# CONFIG_DISPLAY_SUPPORT is not set
+# CONFIG_DRM is not set
 # CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
 CONFIG_FB=y
 # CONFIG_FIRMWARE_EDID is not set
 # CONFIG_FB_DDC is not set
 CONFIG_FB_CFB_FILLRECT=y
 CONFIG_FB_CFB_COPYAREA=y
 CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
 # CONFIG_FB_SYS_FILLRECT is not set
 # CONFIG_FB_SYS_COPYAREA is not set
 # CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
 # CONFIG_FB_SYS_FOPS is not set
 CONFIG_FB_DEFERRED_IO=y
 # CONFIG_FB_SVGALIB is not set
@@ -842,9 +1072,17 @@ CONFIG_FB_DEFERRED_IO=y
 # CONFIG_FB_ARK is not set
 # CONFIG_FB_PM3 is not set
 CONFIG_FB_PXA=y
-# CONFIG_FB_PXA_PARAMETERS is not set
+# CONFIG_FB_PXA_SMARTPANEL is not set
+CONFIG_FB_PXA_PARAMETERS=y
 CONFIG_FB_MBX=m
+# CONFIG_FB_AM200EPD is not set
 # CONFIG_FB_VIRTUAL is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
 
 #
 # Console display driver support
@@ -904,10 +1142,12 @@ CONFIG_SND_AC97_CODEC=m
 # CONFIG_SND_AU8810 is not set
 # CONFIG_SND_AU8820 is not set
 # CONFIG_SND_AU8830 is not set
+# CONFIG_SND_AW2 is not set
 # CONFIG_SND_AZT3328 is not set
 # CONFIG_SND_BT87X is not set
 # CONFIG_SND_CA0106 is not set
 # CONFIG_SND_CMIPCI is not set
+# CONFIG_SND_OXYGEN is not set
 # CONFIG_SND_CS4281 is not set
 # CONFIG_SND_CS46XX is not set
 # CONFIG_SND_DARLA20 is not set
@@ -932,6 +1172,7 @@ CONFIG_SND_AC97_CODEC=m
 # CONFIG_SND_HDA_INTEL is not set
 # CONFIG_SND_HDSP is not set
 # CONFIG_SND_HDSPM is not set
+# CONFIG_SND_HIFIER is not set
 # CONFIG_SND_ICE1712 is not set
 # CONFIG_SND_ICE1724 is not set
 # CONFIG_SND_INTEL8X0 is not set
@@ -949,6 +1190,7 @@ CONFIG_SND_AC97_CODEC=m
 # CONFIG_SND_TRIDENT is not set
 # CONFIG_SND_VIA82XX is not set
 # CONFIG_SND_VIA82XX_MODEM is not set
+# CONFIG_SND_VIRTUOSO is not set
 # CONFIG_SND_VX222 is not set
 # CONFIG_SND_YMFPCI is not set
 # CONFIG_SND_AC97_POWER_SAVE is not set
@@ -966,18 +1208,33 @@ CONFIG_SND_PXA2XX_AC97=m
 # CONFIG_SND_USB_CAIAQ is not set
 
 #
+# PCMCIA devices
+#
+# CONFIG_SND_VXPOCKET is not set
+# CONFIG_SND_PDAUDIOCF is not set
+
+#
 # System on Chip audio support
 #
 # CONFIG_SND_SOC is not set
 
 #
+# ALSA SoC audio for Freescale SOCs
+#
+
+#
+# SoC Audio for the Texas Instruments OMAP
+#
+
+#
 # Open Sound System
 #
 # CONFIG_SOUND_PRIME is not set
 CONFIG_AC97_BUS=m
 CONFIG_HID_SUPPORT=y
 CONFIG_HID=y
-# CONFIG_HID_DEBUG is not set
+CONFIG_HID_DEBUG=y
+# CONFIG_HIDRAW is not set
 
 #
 # USB Input Devices
@@ -992,6 +1249,7 @@ CONFIG_USB_ARCH_HAS_OHCI=y
 CONFIG_USB_ARCH_HAS_EHCI=y
 CONFIG_USB=y
 # CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
 
 #
 # Miscellaneous USB options
@@ -1000,8 +1258,9 @@ CONFIG_USB_DEVICEFS=y
 # CONFIG_USB_DEVICE_CLASS is not set
 # CONFIG_USB_DYNAMIC_MINORS is not set
 # CONFIG_USB_SUSPEND is not set
-# CONFIG_USB_PERSIST is not set
 # CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
 
 #
 # USB Host Controller Drivers
@@ -1033,13 +1292,16 @@ CONFIG_USB_STORAGE=y
 # CONFIG_USB_STORAGE_DEBUG is not set
 # CONFIG_USB_STORAGE_DATAFAB is not set
 # CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
 # CONFIG_USB_STORAGE_DPCM is not set
 # CONFIG_USB_STORAGE_USBAT is not set
 # CONFIG_USB_STORAGE_SDDR09 is not set
 # CONFIG_USB_STORAGE_SDDR55 is not set
 # CONFIG_USB_STORAGE_JUMPSHOT is not set
 # CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
 # CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
 # CONFIG_USB_LIBUSUAL is not set
 
 #
@@ -1052,10 +1314,6 @@ CONFIG_USB_MON=y
 #
 # USB port drivers
 #
-
-#
-# USB Serial Converter support
-#
 # CONFIG_USB_SERIAL is not set
 
 #
@@ -1080,14 +1338,6 @@ CONFIG_USB_MON=y
 # CONFIG_USB_TRANCEVIBRATOR is not set
 # CONFIG_USB_IOWARRIOR is not set
 # CONFIG_USB_TEST is not set
-
-#
-# USB DSL modem support
-#
-
-#
-# USB Gadget Support
-#
 # CONFIG_USB_GADGET is not set
 CONFIG_MMC=m
 # CONFIG_MMC_DEBUG is not set
@@ -1098,6 +1348,7 @@ CONFIG_MMC=m
 #
 CONFIG_MMC_BLOCK=m
 CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
 
 #
 # MMC/SD Host Controller Drivers
@@ -1105,10 +1356,22 @@ CONFIG_MMC_BLOCK_BOUNCE=y
 CONFIG_MMC_PXA=m
 # CONFIG_MMC_SDHCI is not set
 # CONFIG_MMC_TIFM_SD is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
 
 #
-# Real Time Clock
+# LED drivers
 #
+# CONFIG_LEDS_GPIO is not set
+CONFIG_LEDS_CM_X270=y
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+# CONFIG_LEDS_TRIGGER_TIMER is not set
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
 CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_HCTOSYS=y
@@ -1125,11 +1388,32 @@ CONFIG_RTC_INTF_DEV=y
 # CONFIG_RTC_DRV_TEST is not set
 
 #
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+
+#
+# SPI RTC drivers
+#
+
+#
 # Platform RTC drivers
 #
 # CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1511 is not set
 # CONFIG_RTC_DRV_DS1553 is not set
 # CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
 # CONFIG_RTC_DRV_M48T86 is not set
 # CONFIG_RTC_DRV_M48T59 is not set
 CONFIG_RTC_DRV_V3020=y
@@ -1138,19 +1422,7 @@ CONFIG_RTC_DRV_V3020=y
 # on-CPU RTC drivers
 #
 CONFIG_RTC_DRV_SA1100=y
-
-#
-# DMA Engine support
-#
-# CONFIG_DMA_ENGINE is not set
-
-#
-# DMA Clients
-#
-
-#
-# DMA Devices
-#
+# CONFIG_UIO is not set
 
 #
 # File systems
@@ -1164,20 +1436,16 @@ CONFIG_EXT3_FS_XATTR=y
 # CONFIG_EXT3_FS_SECURITY is not set
 # CONFIG_EXT4DEV_FS is not set
 CONFIG_JBD=y
-# CONFIG_JBD_DEBUG is not set
 CONFIG_FS_MBCACHE=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
 # CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
+CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
 # CONFIG_QUOTA is not set
-CONFIG_DNOTIFY=y
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
 # CONFIG_FUSE_FS is not set
@@ -1191,9 +1459,9 @@ CONFIG_DNOTIFY=y
 #
 # DOS/FAT/NT Filesystems
 #
-CONFIG_FAT_FS=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
+CONFIG_FAT_FS=m
+# CONFIG_MSDOS_FS is not set
+CONFIG_VFAT_FS=m
 CONFIG_FAT_DEFAULT_CODEPAGE=437
 CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 # CONFIG_NTFS_FS is not set
@@ -1207,7 +1475,6 @@ CONFIG_SYSFS=y
 CONFIG_TMPFS=y
 # CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
 # CONFIG_CONFIGFS_FS is not set
 
 #
@@ -1220,22 +1487,30 @@ CONFIG_RAMFS=y
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
-# CONFIG_JFFS2_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+CONFIG_JFFS2_SUMMARY=y
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
 # CONFIG_CRAMFS is not set
 # CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
+CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
 # CONFIG_NFS_V3_ACL is not set
 # CONFIG_NFS_V4 is not set
-# CONFIG_NFS_DIRECTIO is not set
 # CONFIG_NFSD is not set
 CONFIG_ROOT_NFS=y
 CONFIG_LOCKD=y
@@ -1245,9 +1520,13 @@ CONFIG_SUNRPC=y
 # CONFIG_SUNRPC_BIND34 is not set
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
-CONFIG_SMB_FS=y
-# CONFIG_SMB_NLS_DEFAULT is not set
-# CONFIG_CIFS is not set
+# CONFIG_SMB_FS is not set
+CONFIG_CIFS=m
+# CONFIG_CIFS_STATS is not set
+# CONFIG_CIFS_WEAK_PW_HASH is not set
+# CONFIG_CIFS_XATTR is not set
+# CONFIG_CIFS_DEBUG2 is not set
+# CONFIG_CIFS_EXPERIMENTAL is not set
 # CONFIG_NCP_FS is not set
 # CONFIG_CODA_FS is not set
 # CONFIG_AFS_FS is not set
@@ -1255,15 +1534,27 @@ CONFIG_SMB_FS=y
 #
 # Partition Types
 #
-# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
 CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
-CONFIG_NLS=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=m
 CONFIG_NLS_DEFAULT="iso8859-1"
-CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_437=m
 # CONFIG_NLS_CODEPAGE_737 is not set
 # CONFIG_NLS_CODEPAGE_775 is not set
 # CONFIG_NLS_CODEPAGE_850 is not set
@@ -1287,7 +1578,7 @@ CONFIG_NLS_CODEPAGE_437=y
 # CONFIG_NLS_CODEPAGE_1250 is not set
 # CONFIG_NLS_CODEPAGE_1251 is not set
 # CONFIG_NLS_ASCII is not set
-CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_1=m
 # CONFIG_NLS_ISO8859_2 is not set
 # CONFIG_NLS_ISO8859_3 is not set
 # CONFIG_NLS_ISO8859_4 is not set
@@ -1300,53 +1591,52 @@ CONFIG_NLS_ISO8859_1=y
 # CONFIG_NLS_ISO8859_15 is not set
 # CONFIG_NLS_KOI8_R is not set
 # CONFIG_NLS_KOI8_U is not set
-# CONFIG_NLS_UTF8 is not set
-
-#
-# Distributed Lock Manager
-#
+CONFIG_NLS_UTF8=m
 # CONFIG_DLM is not set
 
 #
-# Profiling support
-#
-# CONFIG_PROFILING is not set
-
-#
 # Kernel hacking
 #
 # CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
-CONFIG_MAGIC_SYSRQ=y
+CONFIG_FRAME_WARN=0
+# CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_UNUSED_SYMBOLS is not set
 # CONFIG_DEBUG_FS is not set
 # CONFIG_HEADERS_CHECK is not set
 CONFIG_DEBUG_KERNEL=y
 # CONFIG_DEBUG_SHIRQ is not set
 # CONFIG_DETECT_SOFTLOCKUP is not set
-CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHED_DEBUG is not set
 # CONFIG_SCHEDSTATS is not set
 # CONFIG_TIMER_STATS is not set
-# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_OBJECTS is not set
 # CONFIG_DEBUG_RT_MUTEXES is not set
 # CONFIG_RT_MUTEX_TESTER is not set
 # CONFIG_DEBUG_SPINLOCK is not set
 # CONFIG_DEBUG_MUTEXES is not set
 # CONFIG_DEBUG_LOCK_ALLOC is not set
 # CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
 # CONFIG_DEBUG_SPINLOCK_SLEEP is not set
 # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
 # CONFIG_DEBUG_KOBJECT is not set
 # CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_INFO is not set
 # CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
 # CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
 CONFIG_FRAME_POINTER=y
-CONFIG_FORCED_INLINING=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
 # CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
 CONFIG_DEBUG_USER=y
 CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_STACK_USAGE is not set
 CONFIG_DEBUG_LL=y
 # CONFIG_DEBUG_ICEDCC is not set
 
@@ -1355,55 +1645,96 @@ CONFIG_DEBUG_LL=y
 #
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
 CONFIG_CRYPTO=y
-CONFIG_CRYPTO_ALGAPI=m
-CONFIG_CRYPTO_BLKCIPHER=m
-CONFIG_CRYPTO_MANAGER=m
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
 # CONFIG_CRYPTO_HMAC is not set
 # CONFIG_CRYPTO_XCBC is not set
-# CONFIG_CRYPTO_NULL is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
 # CONFIG_CRYPTO_MD4 is not set
 # CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
 # CONFIG_CRYPTO_SHA1 is not set
 # CONFIG_CRYPTO_SHA256 is not set
 # CONFIG_CRYPTO_SHA512 is not set
-# CONFIG_CRYPTO_WP512 is not set
 # CONFIG_CRYPTO_TGR192 is not set
-# CONFIG_CRYPTO_GF128MUL is not set
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_CBC=m
-CONFIG_CRYPTO_PCBC=m
-# CONFIG_CRYPTO_LRW is not set
-# CONFIG_CRYPTO_CRYPTD is not set
-# CONFIG_CRYPTO_DES is not set
-# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
 # CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_TWOFISH is not set
-# CONFIG_CRYPTO_SERPENT is not set
-CONFIG_CRYPTO_AES=m
+# CONFIG_CRYPTO_CAMELLIA is not set
 # CONFIG_CRYPTO_CAST5 is not set
 # CONFIG_CRYPTO_CAST6 is not set
-# CONFIG_CRYPTO_TEA is not set
-CONFIG_CRYPTO_ARC4=m
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
 # CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
 # CONFIG_CRYPTO_DEFLATE is not set
-# CONFIG_CRYPTO_MICHAEL_MIC is not set
-# CONFIG_CRYPTO_CRC32C is not set
-# CONFIG_CRYPTO_CAMELLIA is not set
-# CONFIG_CRYPTO_TEST is not set
-CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_LZO is not set
+# CONFIG_CRYPTO_HW is not set
 
 #
 # Library routines
 #
 CONFIG_BITREVERSE=y
-# CONFIG_CRC_CCITT is not set
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+# CONFIG_GENERIC_FIND_NEXT_BIT is not set
+CONFIG_CRC_CCITT=m
 # CONFIG_CRC16 is not set
 # CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
 # CONFIG_CRC7 is not set
 # CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
 CONFIG_PLIST=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index ad455ff5aebe..eb9092ca8008 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -4,6 +4,10 @@
 
 AFLAGS_head.o := -DTEXT_OFFSET=$(TEXT_OFFSET)
 
+ifdef CONFIG_DYNAMIC_FTRACE
+CFLAGS_REMOVE_ftrace.o = -pg
+endif
+
 # Object file lists.
 
 obj-y           := compat.o entry-armv.o entry-common.o irq.o \
@@ -18,6 +22,7 @@ obj-$(CONFIG_ARTHUR)		+= arthur.o
 obj-$(CONFIG_ISA_DMA)           += dma-isa.o
 obj-$(CONFIG_PCI)               += bios32.o isa.o
 obj-$(CONFIG_SMP)               += smp.o
+obj-$(CONFIG_DYNAMIC_FTRACE)    += ftrace.o
 obj-$(CONFIG_KEXEC)             += machine_kexec.o relocate_kernel.o
 obj-$(CONFIG_KPROBES)           += kprobes.o kprobes-decode.o
 obj-$(CONFIG_ATAGS_PROC)        += atags.o
diff --git a/arch/arm/kernel/armksyms.c b/arch/arm/kernel/armksyms.c
index 688b7b1ee416..cc7b246e9652 100644
--- a/arch/arm/kernel/armksyms.c
+++ b/arch/arm/kernel/armksyms.c
@@ -18,6 +18,7 @@
 #include <asm/io.h>
 #include <asm/system.h>
 #include <asm/uaccess.h>
+#include <asm/ftrace.h>
 
 /*
  * libgcc functions - functions that are used internally by the
@@ -181,3 +182,7 @@ EXPORT_SYMBOL(_find_next_bit_be);
 #endif
 
 EXPORT_SYMBOL(copy_page);
+
+#ifdef CONFIG_FTRACE
+EXPORT_SYMBOL(mcount);
+#endif
diff --git a/arch/arm/kernel/atags.c b/arch/arm/kernel/atags.c
index 64c420805e6f..42a1a1415fa6 100644
--- a/arch/arm/kernel/atags.c
+++ b/arch/arm/kernel/atags.c
@@ -1,5 +1,4 @@
 #include <linux/slab.h>
-#include <linux/kexec.h>
 #include <linux/proc_fs.h>
 #include <asm/setup.h>
 #include <asm/types.h>
@@ -7,9 +6,8 @@
 
 struct buffer {
         size_t size;
-        char *data;
+        char data[];
 };
-static struct buffer tags_buffer;
 
 static int
 read_buffer(char* page, char** start, off_t off, int count,
@@ -29,58 +27,57 @@ read_buffer(char* page, char** start, off_t off, int count,
         return count;
 }
 
-
-static int
-create_proc_entries(void)
-{
-        struct proc_dir_entry* tags_entry;
-
-        tags_entry = create_proc_read_entry("atags", 0400, NULL, read_buffer, &tags_buffer);
-        if (!tags_entry)
-                return -ENOMEM;
-
-        return 0;
-}
-
-
-static char __initdata atags_copy_buf[KEXEC_BOOT_PARAMS_SIZE];
-static char __initdata *atags_copy;
+#define BOOT_PARAMS_SIZE 1536
+static char __initdata atags_copy[BOOT_PARAMS_SIZE];
 
 void __init save_atags(const struct tag *tags)
 {
-        atags_copy = atags_copy_buf;
-        memcpy(atags_copy, tags, KEXEC_BOOT_PARAMS_SIZE);
+        memcpy(atags_copy, tags, sizeof(atags_copy));
 }
 
-
 static int __init init_atags_procfs(void)
 {
-        struct tag *tag;
-        int error;
+        /*
+         * This cannot go into save_atags() because kmalloc and proc don't work
+         * yet when it is called.
+         */
+        struct proc_dir_entry *tags_entry;
+        struct tag *tag = (struct tag *)atags_copy;
+        struct buffer *b;
+        size_t size;
 
-        if (!atags_copy) {
-                printk(KERN_WARNING "Exporting ATAGs: No saved tags found\n");
-                return -EIO;
+        if (tag->hdr.tag != ATAG_CORE) {
+                printk(KERN_INFO "No ATAGs?");
+                return -EINVAL;
         }
 
-        for (tag = (struct tag *) atags_copy; tag->hdr.size; tag = tag_next(tag))
+        for (; tag->hdr.size; tag = tag_next(tag))
                 ;
 
-        tags_buffer.size = ((char *) tag - atags_copy) + sizeof(tag->hdr);
-        tags_buffer.data = kmalloc(tags_buffer.size, GFP_KERNEL);
-        if (tags_buffer.data == NULL)
-                return -ENOMEM;
-        memcpy(tags_buffer.data, atags_copy, tags_buffer.size);
-
-        error = create_proc_entries();
-        if (error) {
-                printk(KERN_ERR "Exporting ATAGs: not enough memory\n");
-                kfree(tags_buffer.data);
-                tags_buffer.size = 0;
-                tags_buffer.data = NULL;
-        }
+        /* include the terminating ATAG_NONE */
+        size = (char *)tag - atags_copy + sizeof(struct tag_header);
 
-        return error;
-}
+        WARN_ON(tag->hdr.tag != ATAG_NONE);
+
+        b = kmalloc(sizeof(*b) + size, GFP_KERNEL);
+        if (!b)
+                goto nomem;
 
+        b->size = size;
+        memcpy(b->data, atags_copy, size);
+
+        tags_entry = create_proc_read_entry("atags", 0400,
+                        NULL, read_buffer, b);
+
+        if (!tags_entry)
+                goto nomem;
+
+        return 0;
+
+nomem:
+        kfree(b);
+        printk(KERN_ERR "Exporting ATAGs: not enough memory\n");
+
+        return -ENOMEM;
+}
 arch_initcall(init_atags_procfs);
diff --git a/arch/arm/kernel/ecard.c b/arch/arm/kernel/ecard.c
index a53c0aba5c14..8bfd299bfe77 100644
--- a/arch/arm/kernel/ecard.c
+++ b/arch/arm/kernel/ecard.c
@@ -680,7 +680,7 @@ static int __init ecard_probeirqhw(void)
 #define IO_EC_MEMC8_BASE 0
 #endif
 
-unsigned int __ecard_address(ecard_t *ec, card_type_t type, card_speed_t speed)
+static unsigned int __ecard_address(ecard_t *ec, card_type_t type, card_speed_t speed)
 {
         unsigned long address = 0;
         int slot = ec->slot_no;
@@ -1002,7 +1002,7 @@ ecard_probe(int slot, card_type_t type)
         }
 
         rc = -ENODEV;
-        if ((ec->podaddr = ecard_address(ec, type, ECARD_SYNC)) == 0)
+        if ((ec->podaddr = __ecard_address(ec, type, ECARD_SYNC)) == 0)
                 goto nodev;
 
         cid.r_zero = 1;
@@ -1141,10 +1141,10 @@ static int ecard_drv_probe(struct device *dev)
 
         id = ecard_match_device(drv->id_table, ec);
 
-        ecard_claim(ec);
+        ec->claimed = 1;
         ret = drv->probe(ec, id);
         if (ret)
-                ecard_release(ec);
+                ec->claimed = 0;
         return ret;
 }
 
@@ -1154,7 +1154,7 @@ static int ecard_drv_remove(struct device *dev)
         struct ecard_driver *drv = ECARD_DRV(dev->driver);
 
         drv->remove(ec);
-        ecard_release(ec);
+        ec->claimed = 0;
 
         /*
          * Restore the default operations.  We ensure that the
@@ -1182,7 +1182,7 @@ static void ecard_drv_shutdown(struct device *dev)
         if (dev->driver) {
                 if (drv->shutdown)
                         drv->shutdown(ec);
-                ecard_release(ec);
+                ec->claimed = 0;
         }
 
         /*
@@ -1239,7 +1239,6 @@ static int ecard_bus_init(void)
 postcore_initcall(ecard_bus_init);
 
 EXPORT_SYMBOL(ecard_readchunk);
-EXPORT_SYMBOL(__ecard_address);
 EXPORT_SYMBOL(ecard_register_driver);
 EXPORT_SYMBOL(ecard_remove_driver);
 EXPORT_SYMBOL(ecard_bus_type);
diff --git a/arch/arm/kernel/ecard.h b/arch/arm/kernel/ecard.h
index d7c2dacf935d..4642d436be2a 100644
--- a/arch/arm/kernel/ecard.h
+++ b/arch/arm/kernel/ecard.h
@@ -54,3 +54,16 @@ struct ex_chunk_dir {
 #define c_len(x)        ((x)->r_len[0]|((x)->r_len[1]<<8)|((x)->r_len[2]<<16))
 #define c_start(x)      ((x)->r_start)
 };
+
+typedef enum ecard_type {               /* Cards address space          */
+        ECARD_IOC,
+        ECARD_MEMC,
+        ECARD_EASI
+} card_type_t;
+
+typedef enum {                          /* Speed for ECARD_IOC space    */
+        ECARD_SLOW       = 0,
+        ECARD_MEDIUM     = 1,
+        ECARD_FAST       = 2,
+        ECARD_SYNC       = 3
+} card_speed_t;
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index 597ed00a08d8..84694e88b428 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -9,6 +9,7 @@
  */
 
 #include <asm/unistd.h>
+#include <asm/ftrace.h>
 #include <asm/arch/entry-macro.S>
 
 #include "entry-header.S"
@@ -99,6 +100,56 @@ ENTRY(ret_from_fork)
 #undef CALL
 #define CALL(x) .long x
 
+#ifdef CONFIG_FTRACE
+#ifdef CONFIG_DYNAMIC_FTRACE
+ENTRY(mcount)
+        stmdb sp!, {r0-r3, lr}
+        mov r0, lr
+        sub r0, r0, #MCOUNT_INSN_SIZE
+
+        .globl mcount_call
+mcount_call:
+        bl ftrace_stub
+        ldmia sp!, {r0-r3, pc}
+
+ENTRY(ftrace_caller)
+        stmdb sp!, {r0-r3, lr}
+        ldr r1, [fp, #-4]
+        mov r0, lr
+        sub r0, r0, #MCOUNT_INSN_SIZE
+
+        .globl ftrace_call
+ftrace_call:
+        bl ftrace_stub
+        ldmia sp!, {r0-r3, pc}
+
+#else
+
+ENTRY(mcount)
+        stmdb sp!, {r0-r3, lr}
+        ldr r0, =ftrace_trace_function
+        ldr r2, [r0]
+        adr r0, ftrace_stub
+        cmp r0, r2
+        bne trace
+        ldmia sp!, {r0-r3, pc}
+
+trace:
+        ldr r1, [fp, #-4]
+        mov r0, lr
+        sub r0, r0, #MCOUNT_INSN_SIZE
+        mov lr, pc
+        mov pc, r2
+        ldmia sp!, {r0-r3, pc}
+
+#endif /* CONFIG_DYNAMIC_FTRACE */
+
+        .globl ftrace_stub
+ftrace_stub:
+        mov pc, lr
+
+#endif /* CONFIG_FTRACE */
+
 /*=============================================================================
  * SWI handler
  *-----------------------------------------------------------------------------
diff --git a/arch/arm/kernel/ftrace.c b/arch/arm/kernel/ftrace.c
new file mode 100644
index 000000000000..76d50e6091bc
--- /dev/null
+++ b/arch/arm/kernel/ftrace.c
@@ -0,0 +1,116 @@
+/*
+ * Dynamic function tracing support.
+ *
+ * Copyright (C) 2008 Abhishek Sagar <sagar.abhishek@gmail.com>
+ *
+ * For licencing details, see COPYING.
+ *
+ * Defines low-level handling of mcount calls when the kernel
+ * is compiled with the -pg flag. When using dynamic ftrace, the
+ * mcount call-sites get patched lazily with NOP till they are
+ * enabled. All code mutation routines here take effect atomically.
+ */
+
+#include <linux/ftrace.h>
+
+#include <asm/cacheflush.h>
+#include <asm/ftrace.h>
+
+#define PC_OFFSET      8
+#define BL_OPCODE      0xeb000000
+#define BL_OFFSET_MASK 0x00ffffff
+
+static unsigned long bl_insn;
+static const unsigned long NOP = 0xe1a00000; /* mov r0, r0 */
+
+unsigned char *ftrace_nop_replace(void)
+{
+        return (char *)&NOP;
+}
+
+/* construct a branch (BL) instruction to addr */
+unsigned char *ftrace_call_replace(unsigned long pc, unsigned long addr)
+{
+        long offset;
+
+        offset = (long)addr - (long)(pc + PC_OFFSET);
+        if (unlikely(offset < -33554432 || offset > 33554428)) {
+                /* Can't generate branches that far (from ARM ARM). Ftrace
+                 * doesn't generate branches outside of kernel text.
+                 */
+                WARN_ON_ONCE(1);
+                return NULL;
+        }
+        offset = (offset >> 2) & BL_OFFSET_MASK;
+        bl_insn = BL_OPCODE | offset;
+        return (unsigned char *)&bl_insn;
+}
+
+int ftrace_modify_code(unsigned long pc, unsigned char *old_code,
+                       unsigned char *new_code)
+{
+        unsigned long err = 0, replaced = 0, old, new;
+
+        old = *(unsigned long *)old_code;
+        new = *(unsigned long *)new_code;
+
+        __asm__ __volatile__ (
+                "1:  ldr    %1, [%2]  \n"
+                "    cmp    %1, %4    \n"
+                "2:  streq  %3, [%2]  \n"
+                "    cmpne  %1, %3    \n"
+                "    movne  %0, #2    \n"
+                "3:\n"
+
+                ".section .fixup, \"ax\"\n"
+                "4:  mov  %0, #1  \n"
+                "    b    3b      \n"
+                ".previous\n"
+
+                ".section __ex_table, \"a\"\n"
+                "    .long 1b, 4b \n"
+                "    .long 2b, 4b \n"
+                ".previous\n"
+
+                : "=r"(err), "=r"(replaced)
+                : "r"(pc), "r"(new), "r"(old), "0"(err), "1"(replaced)
+                : "memory");
+
+        if (!err && (replaced == old))
+                flush_icache_range(pc, pc + MCOUNT_INSN_SIZE);
+
+        return err;
+}
+
+int ftrace_update_ftrace_func(ftrace_func_t func)
+{
+        int ret;
+        unsigned long pc, old;
+        unsigned char *new;
+
+        pc = (unsigned long)&ftrace_call;
+        memcpy(&old, &ftrace_call, MCOUNT_INSN_SIZE);
+        new = ftrace_call_replace(pc, (unsigned long)func);
+        ret = ftrace_modify_code(pc, (unsigned char *)&old, new);
+        return ret;
+}
+
+int ftrace_mcount_set(unsigned long *data)
+{
+        unsigned long pc, old;
+        unsigned long *addr = data;
+        unsigned char *new;
+
+        pc = (unsigned long)&mcount_call;
+        memcpy(&old, &mcount_call, MCOUNT_INSN_SIZE);
+        new = ftrace_call_replace(pc, *addr);
+        *addr = ftrace_modify_code(pc, (unsigned char *)&old, new);
+        return 0;
+}
+
+/* run from kstop_machine */
+int __init ftrace_dyn_arch_init(void *data)
+{
+        ftrace_mcount_set(data);
+        return 0;
+}
diff --git a/arch/arm/kernel/kprobes.c b/arch/arm/kernel/kprobes.c
index 5593dd207216..5ee39e10c8d1 100644
--- a/arch/arm/kernel/kprobes.c
+++ b/arch/arm/kernel/kprobes.c
@@ -274,7 +274,7 @@ int __kprobes kprobe_exceptions_notify(struct notifier_block *self,
  * for kretprobe handlers which should normally be interested in r0 only
  * anyway.
  */
-static void __attribute__((naked)) __kprobes kretprobe_trampoline(void)
+void __naked __kprobes kretprobe_trampoline(void)
 {
         __asm__ __volatile__ (
                 "stmdb  sp!, {r0 - r11}         \n\t"
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 46bf2ede6128..199b3680118b 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -133,10 +133,8 @@ static void default_idle(void)
                 cpu_relax();
         else {
                 local_irq_disable();
-                if (!need_resched()) {
-                        timer_dyn_reprogram();
+                if (!need_resched())
                         arch_idle();
-                }
                 local_irq_enable();
         }
 }
diff --git a/arch/arm/kernel/stacktrace.c b/arch/arm/kernel/stacktrace.c
index ae31deb2d065..90e0c35ae60d 100644
--- a/arch/arm/kernel/stacktrace.c
+++ b/arch/arm/kernel/stacktrace.c
@@ -36,6 +36,7 @@ EXPORT_SYMBOL(walk_stackframe);
 #ifdef CONFIG_STACKTRACE
 struct stack_trace_data {
         struct stack_trace *trace;
+        unsigned int no_sched_functions;
         unsigned int skip;
 };
 
@@ -43,27 +44,52 @@ static int save_trace(struct stackframe *frame, void *d)
 {
         struct stack_trace_data *data = d;
         struct stack_trace *trace = data->trace;
+        unsigned long addr = frame->lr;
 
+        if (data->no_sched_functions && in_sched_functions(addr))
+                return 0;
         if (data->skip) {
                 data->skip--;
                 return 0;
         }
 
-        trace->entries[trace->nr_entries++] = frame->lr;
+        trace->entries[trace->nr_entries++] = addr;
 
         return trace->nr_entries >= trace->max_entries;
 }
 
-void save_stack_trace(struct stack_trace *trace)
+void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace)
 {
         struct stack_trace_data data;
         unsigned long fp, base;
 
         data.trace = trace;
         data.skip = trace->skip;
-        base = (unsigned long)task_stack_page(current);
-        asm("mov %0, fp" : "=r" (fp));
+        base = (unsigned long)task_stack_page(tsk);
+
+        if (tsk != current) {
+#ifdef CONFIG_SMP
+                /*
+                 * What guarantees do we have here that 'tsk'
+                 * is not running on another CPU?
+                 */
+                BUG();
+#else
+                data.no_sched_functions = 1;
+                fp = thread_saved_fp(tsk);
+#endif
+        } else {
+                data.no_sched_functions = 0;
+                asm("mov %0, fp" : "=r" (fp));
+        }
 
         walk_stackframe(fp, base, base + THREAD_SIZE, save_trace, &data);
+        if (trace->nr_entries < trace->max_entries)
+                trace->entries[trace->nr_entries++] = ULONG_MAX;
+}
+
+void save_stack_trace(struct stack_trace *trace)
+{
+        save_stack_trace_tsk(current, trace);
 }
 #endif
diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c
index b5867eca1d0b..cc5145b28e7f 100644
--- a/arch/arm/kernel/time.c
+++ b/arch/arm/kernel/time.c
@@ -365,108 +365,6 @@ static struct sysdev_class timer_sysclass = {
         .resume         = timer_resume,
 };
 
-#ifdef CONFIG_NO_IDLE_HZ
-static int timer_dyn_tick_enable(void)
-{
-        struct dyn_tick_timer *dyn_tick = system_timer->dyn_tick;
-        unsigned long flags;
-        int ret = -ENODEV;
-
-        if (dyn_tick) {
-                spin_lock_irqsave(&dyn_tick->lock, flags);
-                ret = 0;
-                if (!(dyn_tick->state & DYN_TICK_ENABLED)) {
-                        ret = dyn_tick->enable();
-
-                        if (ret == 0)
-                                dyn_tick->state |= DYN_TICK_ENABLED;
-                }
-                spin_unlock_irqrestore(&dyn_tick->lock, flags);
-        }
-
-        return ret;
-}
-
-static int timer_dyn_tick_disable(void)
-{
-        struct dyn_tick_timer *dyn_tick = system_timer->dyn_tick;
-        unsigned long flags;
-        int ret = -ENODEV;
-
-        if (dyn_tick) {
-                spin_lock_irqsave(&dyn_tick->lock, flags);
-                ret = 0;
-                if (dyn_tick->state & DYN_TICK_ENABLED) {
-                        ret = dyn_tick->disable();
-
-                        if (ret == 0)
-                                dyn_tick->state &= ~DYN_TICK_ENABLED;
-                }
-                spin_unlock_irqrestore(&dyn_tick->lock, flags);
-        }
-
-        return ret;
-}
-
-/*
- * Reprogram the system timer for at least the calculated time interval.
- * This function should be called from the idle thread with IRQs disabled,
- * immediately before sleeping.
- */
-void timer_dyn_reprogram(void)
-{
-        struct dyn_tick_timer *dyn_tick = system_timer->dyn_tick;
-        unsigned long next, seq, flags;
-
-        if (!dyn_tick)
-                return;
-
-        spin_lock_irqsave(&dyn_tick->lock, flags);
-        if (dyn_tick->state & DYN_TICK_ENABLED) {
-                next = next_timer_interrupt();
-                do {
-                        seq = read_seqbegin(&xtime_lock);
-                        dyn_tick->reprogram(next - jiffies);
-                } while (read_seqretry(&xtime_lock, seq));
-        }
-        spin_unlock_irqrestore(&dyn_tick->lock, flags);
-}
-
-static ssize_t timer_show_dyn_tick(struct sys_device *dev, char *buf)
-{
-        return sprintf(buf, "%i\n",
-                       (system_timer->dyn_tick->state & DYN_TICK_ENABLED) >> 1);
-}
-
-static ssize_t timer_set_dyn_tick(struct sys_device *dev, const char *buf,
-                                  size_t count)
-{
-        unsigned int enable = simple_strtoul(buf, NULL, 2);
-
-        if (enable)
-                timer_dyn_tick_enable();
-        else
-                timer_dyn_tick_disable();
-
-        return count;
-}
-static SYSDEV_ATTR(dyn_tick, 0644, timer_show_dyn_tick, timer_set_dyn_tick);
-
-/*
- * dyntick=enable|disable
- */
-static char dyntick_str[4] __initdata = "";
-
-static int __init dyntick_setup(char *str)
-{
-        if (str)
-                strlcpy(dyntick_str, str, sizeof(dyntick_str));
-        return 1;
-}
-
-__setup("dyntick=", dyntick_setup);
-#endif
-
 static int __init timer_init_sysfs(void)
 {
         int ret = sysdev_class_register(&timer_sysclass);
@@ -475,19 +373,6 @@ static int __init timer_init_sysfs(void)
                 ret = sysdev_register(&system_timer->dev);
         }
 
-#ifdef CONFIG_NO_IDLE_HZ
-        if (ret == 0 && system_timer->dyn_tick) {
-                ret = sysdev_create_file(&system_timer->dev, &attr_dyn_tick);
-
-                /*
-                 * Turn on dynamic tick after calibrate delay
-                 * for correct bogomips
-                 */
-                if (ret == 0 && dyntick_str[0] == 'e')
-                        ret = timer_dyn_tick_enable();
-        }
-#endif
-
         return ret;
 }
 
@@ -500,10 +385,5 @@ void __init time_init(void)
                 system_timer->offset = dummy_gettimeoffset;
 #endif
         system_timer->init();
-
-#ifdef CONFIG_NO_IDLE_HZ
-        if (system_timer->dyn_tick)
-                spin_lock_init(&system_timer->dyn_tick->lock);
-#endif
 }
 
diff --git a/arch/arm/lib/copy_template.S b/arch/arm/lib/copy_template.S
index cab355c0c1f7..139cce646055 100644
--- a/arch/arm/lib/copy_template.S
+++ b/arch/arm/lib/copy_template.S
@@ -13,14 +13,6 @@
  */
 
 /*
- * This can be used to enable code to cacheline align the source pointer.
- * Experiments on tested architectures (StrongARM and XScale) didn't show
- * this a worthwhile thing to do.  That might be different in the future.
- */
-//#define CALGN(code...)        code
-#define CALGN(code...)
-
-/*
  * Theory of operation
  * -------------------
  *
@@ -82,7 +74,7 @@
                 stmfd   sp!, {r5 - r8}
                 blt     5f
 
-        CALGN(  ands    ip, r1, #31             )
+        CALGN(  ands    ip, r0, #31             )
         CALGN(  rsb     r3, ip, #32             )
         CALGN(  sbcnes  r4, r3, r2              )  @ C is always set here
         CALGN(  bcs     2f                      )
@@ -168,7 +160,7 @@
                 subs    r2, r2, #28
                 blt     14f
 
-        CALGN(  ands    ip, r1, #31             )
+        CALGN(  ands    ip, r0, #31             )
         CALGN(  rsb     ip, ip, #32             )
         CALGN(  sbcnes  r4, ip, r2              )  @ C is always set here
         CALGN(  subcc   r2, r2, ip              )
diff --git a/arch/arm/lib/memmove.S b/arch/arm/lib/memmove.S
index ef7fddc14ac9..2e301b7bd8f1 100644
--- a/arch/arm/lib/memmove.S
+++ b/arch/arm/lib/memmove.S
@@ -13,14 +13,6 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 
-/*
- * This can be used to enable code to cacheline align the source pointer.
- * Experiments on tested architectures (StrongARM and XScale) didn't show
- * this a worthwhile thing to do.  That might be different in the future.
- */
-//#define CALGN(code...)        code
-#define CALGN(code...)
-
                 .text
 
 /*
@@ -55,11 +47,12 @@ ENTRY(memmove)
                 stmfd   sp!, {r5 - r8}
                 blt     5f
 
-        CALGN(  ands    ip, r1, #31             )
+        CALGN(  ands    ip, r0, #31             )
         CALGN(  sbcnes  r4, ip, r2              )  @ C is always set here
         CALGN(  bcs     2f                      )
         CALGN(  adr     r4, 6f                  )
         CALGN(  subs    r2, r2, ip              )  @ C is set here
+        CALGN(  rsb     ip, ip, #32             )
         CALGN(  add     pc, r4, ip              )
 
         PLD(    pld     [r1, #-4]               )
@@ -138,8 +131,7 @@ ENTRY(memmove)
                 subs    r2, r2, #28
                 blt     14f
 
-        CALGN(  ands    ip, r1, #31             )
-        CALGN(  rsb     ip, ip, #32             )
+        CALGN(  ands    ip, r0, #31             )
         CALGN(  sbcnes  r4, ip, r2              )  @ C is always set here
         CALGN(  subcc   r2, r2, ip              )
         CALGN(  bcc     15f                     )
diff --git a/arch/arm/lib/memset.S b/arch/arm/lib/memset.S
index 95b110b07a89..b477d4ac88ef 100644
--- a/arch/arm/lib/memset.S
+++ b/arch/arm/lib/memset.S
@@ -39,6 +39,9 @@ ENTRY(memset)
         mov     r3, r1
         cmp     r2, #16
         blt     4f
+
+#if ! CALGN(1)+0
+
 /*
  * We need an extra register for this loop - save the return address and
  * use the LR
@@ -64,6 +67,49 @@ ENTRY(memset)
         stmneia r0!, {r1, r3, ip, lr}
         ldr     lr, [sp], #4
 
+#else
+
+/*
+ * This version aligns the destination pointer in order to write
+ * whole cache lines at once.
+ */
+
+        stmfd   sp!, {r4-r7, lr}
+        mov     r4, r1
+        mov     r5, r1
+        mov     r6, r1
+        mov     r7, r1
+        mov     ip, r1
+        mov     lr, r1
+
+        cmp     r2, #96
+        tstgt   r0, #31
+        ble     3f
+
+        and     ip, r0, #31
+        rsb     ip, ip, #32
+        sub     r2, r2, ip
+        movs    ip, ip, lsl #(32 - 4)
+        stmcsia r0!, {r4, r5, r6, r7}
+        stmmiia r0!, {r4, r5}
+        tst     ip, #(1 << 30)
+        mov     ip, r1
+        strne   r1, [r0], #4
+
+3:      subs    r2, r2, #64
+        stmgeia r0!, {r1, r3-r7, ip, lr}
+        stmgeia r0!, {r1, r3-r7, ip, lr}
+        bgt     3b
+        ldmeqfd sp!, {r4-r7, pc}
+
+        tst     r2, #32
+        stmneia r0!, {r1, r3-r7, ip, lr}
+        tst     r2, #16
+        stmneia r0!, {r4-r7}
+        ldmfd   sp!, {r4-r7, lr}
+
+#endif
+
 4:      tst     r2, #8
         stmneia r0!, {r1, r3}
         tst     r2, #4
diff --git a/arch/arm/lib/memzero.S b/arch/arm/lib/memzero.S
index abf2508e8221..b8f79d80ee9b 100644
--- a/arch/arm/lib/memzero.S
+++ b/arch/arm/lib/memzero.S
@@ -39,6 +39,9 @@ ENTRY(__memzero)
  */
         cmp     r1, #16                 @ 1 we can skip this chunk if we
         blt     4f                      @ 1 have < 16 bytes
+
+#if ! CALGN(1)+0
+
 /*
  * We need an extra register for this loop - save the return address and
  * use the LR
@@ -64,6 +67,47 @@ ENTRY(__memzero)
         stmneia r0!, {r2, r3, ip, lr}   @ 4
         ldr     lr, [sp], #4            @ 1
 
+#else
+
+/*
+ * This version aligns the destination pointer in order to write
+ * whole cache lines at once.
+ */
+
+        stmfd   sp!, {r4-r7, lr}
+        mov     r4, r2
+        mov     r5, r2
+        mov     r6, r2
+        mov     r7, r2
+        mov     ip, r2
+        mov     lr, r2
+
+        cmp     r1, #96
+        andgts  ip, r0, #31
+        ble     3f
+
+        rsb     ip, ip, #32
+        sub     r1, r1, ip
+        movs    ip, ip, lsl #(32 - 4)
+        stmcsia r0!, {r4, r5, r6, r7}
+        stmmiia r0!, {r4, r5}
+        movs    ip, ip, lsl #2
+        strcs   r2, [r0], #4
+
+3:      subs    r1, r1, #64
+        stmgeia r0!, {r2-r7, ip, lr}
+        stmgeia r0!, {r2-r7, ip, lr}
+        bgt     3b
+        ldmeqfd sp!, {r4-r7, pc}
+
+        tst     r1, #32
+        stmneia r0!, {r2-r7, ip, lr}
+        tst     r1, #16
+        stmneia r0!, {r4-r7}
+        ldmfd   sp!, {r4-r7, lr}
+
+#endif
+
 4:      tst     r1, #8                  @ 1 8 bytes or more?
         stmneia r0!, {r2, r3}           @ 2
         tst     r1, #4                  @ 1 4 bytes or more?
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 0fc07b6db749..5bad6b9b00d7 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -30,6 +30,11 @@ config ARCH_AT91SAM9RL
         select GENERIC_TIME
         select GENERIC_CLOCKEVENTS
 
+config ARCH_AT91SAM9G20
+        bool "AT91SAM9G20"
+        select GENERIC_TIME
+        select GENERIC_CLOCKEVENTS
+
 config ARCH_AT91CAP9
         bool "AT91CAP9"
         select GENERIC_TIME
@@ -126,6 +131,12 @@ config MACH_ECBAT91
           Select this if you are using emQbit's ECB_AT91 board.
           <http://wiki.emqbit.com/free-ecb-at91>
 
+config MACH_YL9200
+        bool "ucDragon YL-9200"
+        depends on ARCH_AT91RM9200
+        help
+          Select this if you are using the ucDragon YL-9200 board.
+
 endif
 
 # ----------------------------------------------------------
@@ -164,6 +175,20 @@ config MACH_SAM9_L9260
           Select this if you are using Olimex's SAM9-L9260 board based on the Atmel AT91SAM9260.
           <http://www.olimex.com/dev/sam9-L9260.html>
 
+config MACH_USB_A9260
+        bool "CALAO USB-A9260"
+        depends on ARCH_AT91SAM9260
+        help
+          Select this if you are using a Calao Systems USB-A9260.
+          <http://www.calao-systems.com>
+
+config MACH_QIL_A9260
+        bool "CALAO QIL-A9260 board"
+        depends on ARCH_AT91SAM9260
+        help
+          Select this if you are using a Calao Systems QIL-A9260 Board.
+          <http://www.calao-systems.com>
+
 endif
 
 # ----------------------------------------------------------
@@ -194,6 +219,13 @@ config MACH_AT91SAM9263EK
           Select this if you are using Atmel's AT91SAM9263-EK Evaluation Kit.
           <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4057>
 
+config MACH_USB_A9263
+        bool "CALAO USB-A9263"
+        depends on ARCH_AT91SAM9263
+        help
+          Select this if you are using a Calao Systems USB-A9263.
+          <http://www.calao-systems.com>
+
 endif
 
 # ----------------------------------------------------------
@@ -212,6 +244,20 @@ endif
 
 # ----------------------------------------------------------
 
+if ARCH_AT91SAM9G20
+
+comment "AT91SAM9G20 Board Type"
+
+config MACH_AT91SAM9G20EK
+        bool "Atmel AT91SAM9G20-EK Evaluation Kit"
+        depends on ARCH_AT91SAM9G20
+        help
+          Select this if you are using Atmel's AT91SAM9G20-EK Evaluation Kit.
+
+endif
+
+# ----------------------------------------------------------
+
 if ARCH_AT91CAP9
 
 comment "AT91CAP9 Board Type"
@@ -247,13 +293,13 @@ comment "AT91 Board Options"
 
 config MTD_AT91_DATAFLASH_CARD
         bool "Enable DataFlash Card support"
-        depends on (ARCH_AT91RM9200DK || MACH_AT91RM9200EK || MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9263EK || MACH_AT91CAP9ADK || MACH_SAM9_L9260 || MACH_ECBAT91)
+        depends on (ARCH_AT91RM9200DK || MACH_AT91RM9200EK || MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9263EK || MACH_AT91SAM9G20EK || MACH_ECBAT91 || MACH_SAM9_L9260 || MACH_AT91CAP9ADK)
         help
           Enable support for the DataFlash card.
 
 config MTD_NAND_AT91_BUSWIDTH_16
         bool "Enable 16-bit data bus interface to NAND flash"
-        depends on (MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9263EK || MACH_AT91CAP9ADK)
+        depends on (MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9263EK || MACH_AT91SAM9G20EK || MACH_AT91CAP9ADK)
         help
           On AT91SAM926x boards both types of NAND flash can be present
           (8 and 16 bit data bus width).
@@ -302,15 +348,15 @@ config AT91_EARLY_USART2
 
 config AT91_EARLY_USART3
         bool "USART3"
-        depends on (ARCH_AT91RM9200 || ARCH_AT91SAM9RL || ARCH_AT91SAM9260)
+        depends on (ARCH_AT91RM9200 || ARCH_AT91SAM9RL || ARCH_AT91SAM9260 || ARCH_AT91SAM9G20)
 
 config AT91_EARLY_USART4
         bool "USART4"
-        depends on ARCH_AT91SAM9260
+        depends on ARCH_AT91SAM9260 || ARCH_AT91SAM9G20
 
 config AT91_EARLY_USART5
         bool "USART5"
-        depends on ARCH_AT91SAM9260
+        depends on ARCH_AT91SAM9260 || ARCH_AT91SAM9G20
 
 endchoice
 
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 8d9bc0153b18..7d641f97516b 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_ARCH_AT91SAM9260)	+= at91sam9260.o at91sam926x_time.o at91sam9260_d
 obj-$(CONFIG_ARCH_AT91SAM9261)  += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o
 obj-$(CONFIG_ARCH_AT91SAM9263)  += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o
 obj-$(CONFIG_ARCH_AT91SAM9RL)   += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o
+obj-$(CONFIG_ARCH_AT91SAM9G20)  += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o
 obj-$(CONFIG_ARCH_AT91CAP9)     += at91cap9.o at91sam926x_time.o at91cap9_devices.o
 obj-$(CONFIG_ARCH_AT91X40)      += at91x40.o at91x40_time.o
 
@@ -30,21 +31,28 @@ obj-$(CONFIG_MACH_ATEB9200)	+= board-eb9200.o
 obj-$(CONFIG_MACH_KAFA)         += board-kafa.o
 obj-$(CONFIG_MACH_PICOTUX2XX)   += board-picotux200.o
 obj-$(CONFIG_MACH_ECBAT91)      += board-ecbat91.o
+obj-$(CONFIG_MACH_YL9200)       += board-yl-9200.o
 
 # AT91SAM9260 board-specific support
 obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o
 obj-$(CONFIG_MACH_CAM60)        += board-cam60.o
 obj-$(CONFIG_MACH_SAM9_L9260)   += board-sam9-l9260.o
+obj-$(CONFIG_MACH_USB_A9260)    += board-usb-a9260.o
+obj-$(CONFIG_MACH_QIL_A9260)    += board-qil-a9260.o
 
 # AT91SAM9261 board-specific support
 obj-$(CONFIG_MACH_AT91SAM9261EK) += board-sam9261ek.o
 
 # AT91SAM9263 board-specific support
 obj-$(CONFIG_MACH_AT91SAM9263EK) += board-sam9263ek.o
+obj-$(CONFIG_MACH_USB_A9263)    += board-usb-a9263.o
 
 # AT91SAM9RL board-specific support
 obj-$(CONFIG_MACH_AT91SAM9RLEK) += board-sam9rlek.o
 
+# AT91SAM9G20 board-specific support
+obj-$(CONFIG_MACH_AT91SAM9G20EK) += board-sam9g20ek.o
+
 # AT91CAP9 board-specific support
 obj-$(CONFIG_MACH_AT91CAP9ADK)  += board-cap9adk.o
 
diff --git a/arch/arm/mach-at91/at91cap9_devices.c b/arch/arm/mach-at91/at91cap9_devices.c
index be526746e01e..747b9dedab88 100644
--- a/arch/arm/mach-at91/at91cap9_devices.c
+++ b/arch/arm/mach-at91/at91cap9_devices.c
@@ -84,6 +84,105 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
 
 
 /* --------------------------------------------------------------------
+ *  USB HS Device (Gadget)
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_USB_GADGET_ATMEL_USBA) || defined(CONFIG_USB_GADGET_ATMEL_USBA_MODULE)
+
+static struct resource usba_udc_resources[] = {
+        [0] = {
+                .start  = AT91CAP9_UDPHS_FIFO,
+                .end    = AT91CAP9_UDPHS_FIFO + SZ_512K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91CAP9_BASE_UDPHS,
+                .end    = AT91CAP9_BASE_UDPHS + SZ_1K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [2] = {
+                .start  = AT91CAP9_ID_UDPHS,
+                .end    = AT91CAP9_ID_UDPHS,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+#define EP(nam, idx, maxpkt, maxbk, dma, isoc)                  \
+        [idx] = {                                               \
+                .name           = nam,                          \
+                .index          = idx,                          \
+                .fifo_size      = maxpkt,                       \
+                .nr_banks       = maxbk,                        \
+                .can_dma        = dma,                          \
+                .can_isoc       = isoc,                         \
+        }
+
+static struct usba_ep_data usba_udc_ep[] = {
+        EP("ep0", 0,   64, 1, 0, 0),
+        EP("ep1", 1, 1024, 3, 1, 1),
+        EP("ep2", 2, 1024, 3, 1, 1),
+        EP("ep3", 3, 1024, 2, 1, 1),
+        EP("ep4", 4, 1024, 2, 1, 1),
+        EP("ep5", 5, 1024, 2, 1, 0),
+        EP("ep6", 6, 1024, 2, 1, 0),
+        EP("ep7", 7, 1024, 2, 0, 0),
+};
+
+#undef EP
+
+/*
+ * pdata doesn't have room for any endpoints, so we need to
+ * append room for the ones we need right after it.
+ */
+static struct {
+        struct usba_platform_data pdata;
+        struct usba_ep_data ep[8];
+} usba_udc_data;
+
+static struct platform_device at91_usba_udc_device = {
+        .name           = "atmel_usba_udc",
+        .id             = -1,
+        .dev            = {
+                                .platform_data  = &usba_udc_data.pdata,
+        },
+        .resource       = usba_udc_resources,
+        .num_resources  = ARRAY_SIZE(usba_udc_resources),
+};
+
+void __init at91_add_device_usba(struct usba_platform_data *data)
+{
+        at91_sys_write(AT91_MATRIX_UDPHS, AT91_MATRIX_SELECT_UDPHS |
+                                          AT91_MATRIX_UDPHS_BYPASS_LOCK);
+
+        /*
+         * Invalid pins are 0 on AT91, but the usba driver is shared
+         * with AVR32, which use negative values instead. Once/if
+         * gpio_is_valid() is ported to AT91, revisit this code.
+         */
+        usba_udc_data.pdata.vbus_pin = -EINVAL;
+        usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
+        memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));;
+
+        if (data && data->vbus_pin > 0) {
+                at91_set_gpio_input(data->vbus_pin, 0);
+                at91_set_deglitch(data->vbus_pin, 1);
+                usba_udc_data.pdata.vbus_pin = data->vbus_pin;
+        }
+
+        /* Pullup pin is handled internally by USB device peripheral */
+
+        /* Clocks */
+        at91_clock_associate("utmi_clk", &at91_usba_udc_device.dev, "hclk");
+        at91_clock_associate("udphs_clk", &at91_usba_udc_device.dev, "pclk");
+
+        platform_device_register(&at91_usba_udc_device);
+}
+#else
+void __init at91_add_device_usba(struct usba_platform_data *data) {}
+#endif
+
+
+/* --------------------------------------------------------------------
  *  Ethernet
  * -------------------------------------------------------------------- */
 
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index ee26550cdc21..380f12a12200 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -47,6 +47,20 @@ static struct map_desc at91sam9260_sram_desc[] __initdata = {
         }
 };
 
+static struct map_desc at91sam9g20_sram_desc[] __initdata = {
+        {
+                .virtual        = AT91_IO_VIRT_BASE - AT91SAM9G20_SRAM0_SIZE,
+                .pfn            = __phys_to_pfn(AT91SAM9G20_SRAM0_BASE),
+                .length         = AT91SAM9G20_SRAM0_SIZE,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = AT91_IO_VIRT_BASE - AT91SAM9G20_SRAM0_SIZE - AT91SAM9G20_SRAM1_SIZE,
+                .pfn            = __phys_to_pfn(AT91SAM9G20_SRAM1_BASE),
+                .length         = AT91SAM9G20_SRAM1_SIZE,
+                .type           = MT_DEVICE,
+        }
+};
+
 static struct map_desc at91sam9xe_sram_desc[] __initdata = {
         {
                 .pfn            = __phys_to_pfn(AT91SAM9XE_SRAM_BASE),
@@ -307,6 +321,8 @@ void __init at91sam9260_initialize(unsigned long main_clock)
 
         if (cpu_is_at91sam9xe())
                 at91sam9xe_initialize();
+        else if (cpu_is_at91sam9g20())
+                iotable_init(at91sam9g20_sram_desc, ARRAY_SIZE(at91sam9g20_sram_desc));
         else
                 iotable_init(at91sam9260_sram_desc, ARRAY_SIZE(at91sam9260_sram_desc));
 
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index 393a32aefce5..86cba4ac29b1 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -18,6 +18,7 @@
 
 #include <asm/arch/board.h>
 #include <asm/arch/gpio.h>
+#include <asm/arch/cpu.h>
 #include <asm/arch/at91sam9260.h>
 #include <asm/arch/at91sam9260_matrix.h>
 #include <asm/arch/at91sam9_smc.h>
@@ -320,20 +321,41 @@ void __init at91_add_device_nand(struct at91_nand_data *data)
         csa = at91_sys_read(AT91_MATRIX_EBICSA);
         at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
 
-        /* set the bus interface characteristics */
-        at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0)
-                        | AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
+        if (cpu_is_at91sam9260()) {
+                /* Timing for sam9260 */
+                /* set the bus interface characteristics */
+                at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0)
+                                | AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
 
-        at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3)
-                        | AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
+                at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3)
+                                | AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
 
-        at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
+                at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
 
-        if (data->bus_width_16)
-                mode = AT91_SMC_DBW_16;
-        else
-                mode = AT91_SMC_DBW_8;
-        at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(2));
+                if (data->bus_width_16)
+                        mode = AT91_SMC_DBW_16;
+                else
+                        mode = AT91_SMC_DBW_8;
+                at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(2));
+        }
+
+        if (cpu_is_at91sam9g20()) {
+                /* Timing for sam9g20 */
+                /* set the bus interface characteristics */
+                at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0)
+                                | AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0));
+
+                at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(4)
+                                | AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(4));
+
+                at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
+
+                if (data->bus_width_16)
+                        mode = AT91_SMC_DBW_16;
+                else
+                        mode = AT91_SMC_DBW_8;
+                at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(3));
+        }
 
         /* enable pin */
         if (data->enable_pin)
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index 0babb645b83c..ec1891375dfb 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -232,19 +232,19 @@ void __init at91_add_device_nand(struct at91_nand_data *data)
         at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
 
         /* set the bus interface characteristics */
-        at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0)
-                        | AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
+        at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0)
+                        | AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
 
-        at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(2) | AT91_SMC_NCS_WRPULSE_(5)
-                        | AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(5));
+        at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3)
+                        | AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
 
-        at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
+        at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
 
         if (data->bus_width_16)
                 mode = AT91_SMC_DBW_16;
         else
                 mode = AT91_SMC_DBW_8;
-        at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(1));
+        at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(2));
 
         /* enable pin */
         if (data->enable_pin)
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index 719667e25c98..8a81f76f0200 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -391,8 +391,8 @@ void __init at91_add_device_nand(struct at91_nand_data *data)
         at91_sys_write(AT91_MATRIX_EBI0CSA, csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
 
         /* set the bus interface characteristics */
-        at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0)
-                        | AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
+        at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0)
+                        | AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
 
         at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3)
                         | AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c
index 450db304936f..ae28101e7542 100644
--- a/arch/arm/mach-at91/at91sam9rl_devices.c
+++ b/arch/arm/mach-at91/at91sam9rl_devices.c
@@ -26,6 +26,101 @@
 
 
 /* --------------------------------------------------------------------
+ *  USB HS Device (Gadget)
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_USB_GADGET_ATMEL_USBA) || defined(CONFIG_USB_GADGET_ATMEL_USBA_MODULE)
+
+static struct resource usba_udc_resources[] = {
+        [0] = {
+                .start  = AT91SAM9RL_UDPHS_FIFO,
+                .end    = AT91SAM9RL_UDPHS_FIFO + SZ_512K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9RL_BASE_UDPHS,
+                .end    = AT91SAM9RL_BASE_UDPHS + SZ_1K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [2] = {
+                .start  = AT91SAM9RL_ID_UDPHS,
+                .end    = AT91SAM9RL_ID_UDPHS,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+#define EP(nam, idx, maxpkt, maxbk, dma, isoc)                  \
+        [idx] = {                                               \
+                .name           = nam,                          \
+                .index          = idx,                          \
+                .fifo_size      = maxpkt,                       \
+                .nr_banks       = maxbk,                        \
+                .can_dma        = dma,                          \
+                .can_isoc       = isoc,                         \
+        }
+
+static struct usba_ep_data usba_udc_ep[] __initdata = {
+        EP("ep0", 0, 64, 1, 0, 0),
+        EP("ep1", 1, 1024, 2, 1, 1),
+        EP("ep2", 2, 1024, 2, 1, 1),
+        EP("ep3", 3, 1024, 3, 1, 0),
+        EP("ep4", 4, 1024, 3, 1, 0),
+        EP("ep5", 5, 1024, 3, 1, 1),
+        EP("ep6", 6, 1024, 3, 1, 1),
+};
+
+#undef EP
+
+/*
+ * pdata doesn't have room for any endpoints, so we need to
+ * append room for the ones we need right after it.
+ */
+static struct {
+        struct usba_platform_data pdata;
+        struct usba_ep_data ep[7];
+} usba_udc_data;
+
+static struct platform_device at91_usba_udc_device = {
+        .name           = "atmel_usba_udc",
+        .id             = -1,
+        .dev            = {
+                                .platform_data  = &usba_udc_data.pdata,
+        },
+        .resource       = usba_udc_resources,
+        .num_resources  = ARRAY_SIZE(usba_udc_resources),
+};
+
+void __init at91_add_device_usba(struct usba_platform_data *data)
+{
+        /*
+         * Invalid pins are 0 on AT91, but the usba driver is shared
+         * with AVR32, which use negative values instead. Once/if
+         * gpio_is_valid() is ported to AT91, revisit this code.
+         */
+        usba_udc_data.pdata.vbus_pin = -EINVAL;
+        usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
+        memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));;
+
+        if (data && data->vbus_pin > 0) {
+                at91_set_gpio_input(data->vbus_pin, 0);
+                at91_set_deglitch(data->vbus_pin, 1);
+                usba_udc_data.pdata.vbus_pin = data->vbus_pin;
+        }
+
+        /* Pullup pin is handled internally by USB device peripheral */
+
+        /* Clocks */
+        at91_clock_associate("utmi_clk", &at91_usba_udc_device.dev, "hclk");
+        at91_clock_associate("udphs_clk", &at91_usba_udc_device.dev, "pclk");
+
+        platform_device_register(&at91_usba_udc_device);
+}
+#else
+void __init at91_add_device_usba(struct usba_platform_data *data) {}
+#endif
+
+
+/* --------------------------------------------------------------------
  *  MMC / SD
  * -------------------------------------------------------------------- */
 
@@ -138,15 +233,15 @@ void __init at91_add_device_nand(struct at91_nand_data *data)
         at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
 
         /* set the bus interface characteristics */
-        at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0)
-                        | AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
+        at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0)
+                        | AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
 
-        at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(2) | AT91_SMC_NCS_WRPULSE_(5)
-                        | AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(5));
+        at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3)
+                        | AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
 
-        at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
+        at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
 
-        at91_sys_write(AT91_SMC_MODE(3), AT91_SMC_DBW_8 | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(1));
+        at91_sys_write(AT91_SMC_MODE(3), AT91_SMC_DBW_8 | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(2));
 
         /* enable pin */
         if (data->enable_pin)
diff --git a/arch/arm/mach-at91/board-cap9adk.c b/arch/arm/mach-at91/board-cap9adk.c
index e5512d1ff217..8a2a958639db 100644
--- a/arch/arm/mach-at91/board-cap9adk.c
+++ b/arch/arm/mach-at91/board-cap9adk.c
@@ -78,6 +78,12 @@ static struct at91_usbh_data __initdata cap9adk_usbh_data = {
         .ports          = 2,
 };
 
+/*
+ * USB HS Device port
+ */
+static struct usba_platform_data __initdata cap9adk_usba_udc_data = {
+        .vbus_pin       = AT91_PIN_PB31,
+};
 
 /*
  * ADS7846 Touchscreen
@@ -326,6 +332,9 @@ static void __init cap9adk_board_init(void)
         /* USB Host */
         set_irq_type(AT91CAP9_ID_UHP, IRQT_HIGH);
         at91_add_device_usbh(&cap9adk_usbh_data);
+        /* USB HS */
+        set_irq_type(AT91CAP9_ID_UDPHS, IRQT_HIGH);
+        at91_add_device_usba(&cap9adk_usba_udc_data);
         /* SPI */
         at91_add_device_spi(cap9adk_spi_devices, ARRAY_SIZE(cap9adk_spi_devices));
         /* Touchscreen */
diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c
index 0f0878294a67..9854fc3dd1f2 100644
--- a/arch/arm/mach-at91/board-carmeva.c
+++ b/arch/arm/mach-at91/board-carmeva.c
@@ -40,24 +40,21 @@
 #include "generic.h"
 
 
-/*
- * Serial port configuration.
- *    0 .. 3 = USART0 .. USART3
- *    4      = DBGU
- */
-static struct at91_uart_config __initdata carmeva_uart_config = {
-        .console_tty    = 0,                            /* ttyS0 */
-        .nr_tty         = 2,
-        .tty_map        = { 4, 1, -1, -1, -1 }          /* ttyS0, ..., ttyS4 */
-};
-
 static void __init carmeva_map_io(void)
 {
         /* Initialize processor: 20.000 MHz crystal */
         at91rm9200_initialize(20000000, AT91RM9200_BGA);
 
-        /* Setup the serial ports and console */
-        at91_init_serial(&carmeva_uart_config);
+        /* DBGU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+
+        /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
+        at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
+                           | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
+                           | ATMEL_UART_RI);
+
+        /* set serial console to ttyS0 (ie, DBGU) */
+        at91_set_serial_console(0);
 }
 
 static void __init carmeva_init_irq(void)
diff --git a/arch/arm/mach-at91/board-csb637.c b/arch/arm/mach-at91/board-csb637.c
index 419fd19b620b..bb1a5474ddab 100644
--- a/arch/arm/mach-at91/board-csb637.c
+++ b/arch/arm/mach-at91/board-csb637.c
@@ -45,10 +45,10 @@ static void __init csb637_map_io(void)
         /* Initialize processor: 3.6864 MHz crystal */
         at91rm9200_initialize(3686400, AT91RM9200_BGA);
 
-        /* DBGU on ttyS0 */
+        /* DBGU on ttyS0. (Rx & Tx only) */
         at91_register_uart(0, 0, 0);
 
-        /* make console=ttyS0 the default */
+        /* make console=ttyS0 (ie, DBGU) the default */
         at91_set_serial_console(0);
 }
 
diff --git a/arch/arm/mach-at91/board-dk.c b/arch/arm/mach-at91/board-dk.c
index c1a813c7169b..dab958d25926 100644
--- a/arch/arm/mach-at91/board-dk.c
+++ b/arch/arm/mach-at91/board-dk.c
@@ -45,17 +45,6 @@
 #include "generic.h"
 
 
-/*
- * Serial port configuration.
- *    0 .. 3 = USART0 .. USART3
- *    4      = DBGU
- */
-static struct at91_uart_config __initdata dk_uart_config = {
-        .console_tty    = 0,                            /* ttyS0 */
-        .nr_tty         = 2,
-        .tty_map        = { 4, 1, -1, -1, -1 }          /* ttyS0, ..., ttyS4 */
-};
-
 static void __init dk_map_io(void)
 {
         /* Initialize processor: 18.432 MHz crystal */
@@ -64,8 +53,16 @@ static void __init dk_map_io(void)
         /* Setup the LEDs */
         at91_init_leds(AT91_PIN_PB2, AT91_PIN_PB2);
 
-        /* Setup the serial ports and console */
-        at91_init_serial(&dk_uart_config);
+        /* DBGU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+
+        /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
+        at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
+                           | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
+                           | ATMEL_UART_RI);
+
+        /* set serial console to ttyS0 (ie, DBGU) */
+        at91_set_serial_console(0);
 }
 
 static void __init dk_init_irq(void)
@@ -163,7 +160,7 @@ static struct at91_nand_data __initdata dk_nand_data = {
 #define DK_FLASH_SIZE   0x200000
 
 static struct physmap_flash_data dk_flash_data = {
-        .width  = 2,
+        .width          = 2,
 };
 
 static struct resource dk_flash_resource = {
diff --git a/arch/arm/mach-at91/board-eb9200.c b/arch/arm/mach-at91/board-eb9200.c
index af1a1d8ecc30..3fe054e0056b 100644
--- a/arch/arm/mach-at91/board-eb9200.c
+++ b/arch/arm/mach-at91/board-eb9200.c
@@ -40,24 +40,24 @@
 #include "generic.h"
 
 
-/*
- * Serial port configuration.
- *    0 .. 3 = USART0 .. USART3
- *    4      = DBGU
- */
-static struct at91_uart_config __initdata eb9200_uart_config = {
-        .console_tty    = 0,                            /* ttyS0 */
-        .nr_tty         = 2,
-        .tty_map        = { 4, 1, -1, -1, -1 }          /* ttyS0, ..., ttyS4 */
-};
-
 static void __init eb9200_map_io(void)
 {
         /* Initialize processor: 18.432 MHz crystal */
         at91rm9200_initialize(18432000, AT91RM9200_BGA);
 
-        /* Setup the serial ports and console */
-        at91_init_serial(&eb9200_uart_config);
+        /* DBGU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+
+        /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
+        at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
+                        | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
+                        | ATMEL_UART_RI);
+
+        /* USART2 on ttyS2. (Rx, Tx) - IRDA */
+        at91_register_uart(AT91RM9200_ID_US2, 2, 0);
+
+        /* set serial console to ttyS0 (ie, DBGU) */
+        at91_set_serial_console(0);
 }
 
 static void __init eb9200_init_irq(void)
diff --git a/arch/arm/mach-at91/board-ek.c b/arch/arm/mach-at91/board-ek.c
index 0574e50a30dd..74aa4325eab3 100644
--- a/arch/arm/mach-at91/board-ek.c
+++ b/arch/arm/mach-at91/board-ek.c
@@ -45,17 +45,6 @@
 #include "generic.h"
 
 
-/*
- * Serial port configuration.
- *    0 .. 3 = USART0 .. USART3
- *    4      = DBGU
- */
-static struct at91_uart_config __initdata ek_uart_config = {
-        .console_tty    = 0,                            /* ttyS0 */
-        .nr_tty         = 2,
-        .tty_map        = { 4, 1, -1, -1, -1 }          /* ttyS0, ..., ttyS4 */
-};
-
 static void __init ek_map_io(void)
 {
         /* Initialize processor: 18.432 MHz crystal */
@@ -64,8 +53,16 @@ static void __init ek_map_io(void)
         /* Setup the LEDs */
         at91_init_leds(AT91_PIN_PB1, AT91_PIN_PB2);
 
-        /* Setup the serial ports and console */
-        at91_init_serial(&ek_uart_config);
+        /* DBGU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+
+        /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
+        at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
+                           | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
+                           | ATMEL_UART_RI);
+
+        /* set serial console to ttyS0 (ie, DBGU) */
+        at91_set_serial_console(0);
 }
 
 static void __init ek_init_irq(void)
@@ -122,7 +119,7 @@ static struct i2c_board_info __initdata ek_i2c_devices[] = {
 #define EK_FLASH_SIZE   0x200000
 
 static struct physmap_flash_data ek_flash_data = {
-        .width  = 2,
+        .width          = 2,
 };
 
 static struct resource ek_flash_resource = {
diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c
index 4b39b9cda75b..cb065febd95e 100644
--- a/arch/arm/mach-at91/board-kb9202.c
+++ b/arch/arm/mach-at91/board-kb9202.c
@@ -37,19 +37,10 @@
 #include <asm/arch/board.h>
 #include <asm/arch/gpio.h>
 
-#include "generic.h"
+#include <asm/arch/at91rm9200_mc.h>
 
+#include "generic.h"
 
-/*
- * Serial port configuration.
- *    0 .. 3 = USART0 .. USART3
- *    4      = DBGU
- */
-static struct at91_uart_config __initdata kb9202_uart_config = {
-        .console_tty    = 0,                                    /* ttyS0 */
-        .nr_tty         = 3,
-        .tty_map        = { 4, 0, 1, -1, -1 }                   /* ttyS0, ..., ttyS4 */
-};
 
 static void __init kb9202_map_io(void)
 {
@@ -59,8 +50,20 @@ static void __init kb9202_map_io(void)
         /* Set up the LEDs */
         at91_init_leds(AT91_PIN_PC19, AT91_PIN_PC18);
 
-        /* Setup the serial ports and console */
-        at91_init_serial(&kb9202_uart_config);
+        /* DBGU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+
+        /* USART0 on ttyS1 (Rx & Tx only) */
+        at91_register_uart(AT91RM9200_ID_US0, 1, 0);
+
+        /* USART1 on ttyS2 (Rx & Tx only) - IRDA (optional) */
+        at91_register_uart(AT91RM9200_ID_US1, 2, 0);
+
+        /* USART3 on ttyS3 (Rx, Tx, CTS, RTS) - RS485 (optional) */
+        at91_register_uart(AT91RM9200_ID_US3, 3, ATMEL_UART_CTS | ATMEL_UART_RTS);
+
+        /* set serial console to ttyS0 (ie, DBGU) */
+        at91_set_serial_console(0);
 }
 
 static void __init kb9202_init_irq(void)
diff --git a/arch/arm/mach-at91/board-qil-a9260.c b/arch/arm/mach-at91/board-qil-a9260.c
new file mode 100644
index 000000000000..99b4ec3818d6
--- /dev/null
+++ b/arch/arm/mach-at91/board-qil-a9260.c
@@ -0,0 +1,255 @@
+/*
+ * linux/arch/arm/mach-at91/board-qil-a9260.c
+ *
+ *  Copyright (C) 2005 SAN People
+ *  Copyright (C) 2006 Atmel
+ *  Copyright (C) 2007 Calao-systems
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <linux/clk.h>
+
+#include <asm/hardware.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/arch/board.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/at91_shdwc.h>
+
+#include "generic.h"
+
+
+static void __init ek_map_io(void)
+{
+        /* Initialize processor: 12.000 MHz crystal */
+        at91sam9260_initialize(12000000);
+
+        /* DGBU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+
+        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
+        at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
+                           | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
+                           | ATMEL_UART_RI);
+
+        /* USART1 on ttyS2. (Rx, Tx, CTS, RTS) */
+        at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
+
+        /* USART2 on ttyS3. (Rx, Tx, CTS, RTS) */
+        at91_register_uart(AT91SAM9260_ID_US2, 3, ATMEL_UART_CTS | ATMEL_UART_RTS);
+
+        /* set serial console to ttyS1 (ie, USART0) */
+        at91_set_serial_console(1);
+
+}
+
+static void __init ek_init_irq(void)
+{
+        at91sam9260_init_interrupts(NULL);
+}
+
+
+/*
+ * USB Host port
+ */
+static struct at91_usbh_data __initdata ek_usbh_data = {
+        .ports          = 2,
+};
+
+/*
+ * USB Device port
+ */
+static struct at91_udc_data __initdata ek_udc_data = {
+        .vbus_pin       = AT91_PIN_PC5,
+        .pullup_pin     = 0,            /* pull-up driven by UDC */
+};
+
+/*
+ * SPI devices.
+ */
+static struct spi_board_info ek_spi_devices[] = {
+#if defined(CONFIG_RTC_DRV_M41T94)
+        {       /* M41T94 RTC */
+                .modalias       = "m41t94",
+                .chip_select    = 0,
+                .max_speed_hz   = 1 * 1000 * 1000,
+                .bus_num        = 0,
+        }
+#endif
+};
+
+/*
+ * MACB Ethernet device
+ */
+static struct at91_eth_data __initdata ek_macb_data = {
+        .phy_irq_pin    = AT91_PIN_PA31,
+        .is_rmii        = 1,
+};
+
+/*
+ * NAND flash
+ */
+static struct mtd_partition __initdata ek_nand_partition[] = {
+        {
+                .name   = "Uboot & Kernel",
+                .offset = 0x00000000,
+                .size   = 16 * 1024 * 1024,
+        },
+        {
+                .name   = "Root FS",
+                .offset = 0x01000000,
+                .size   = 120 * 1024 * 1024,
+        },
+        {
+                .name   = "FS",
+                .offset = 0x08800000,
+                .size   = 120 * 1024 * 1024,
+        },
+};
+
+static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
+{
+        *num_partitions = ARRAY_SIZE(ek_nand_partition);
+        return ek_nand_partition;
+}
+
+static struct at91_nand_data __initdata ek_nand_data = {
+        .ale            = 21,
+        .cle            = 22,
+//      .det_pin        = ... not connected
+        .rdy_pin        = AT91_PIN_PC13,
+        .enable_pin     = AT91_PIN_PC14,
+        .partition_info = nand_partitions,
+#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
+        .bus_width_16   = 1,
+#else
+        .bus_width_16   = 0,
+#endif
+};
+
+/*
+ * MCI (SD/MMC)
+ */
+static struct at91_mmc_data __initdata ek_mmc_data = {
+        .slot_b         = 0,
+        .wire4          = 1,
+//      .det_pin        = ... not connected
+//      .wp_pin         = ... not connected
+//      .vcc_pin        = ... not connected
+};
+
+/*
+ * GPIO Buttons
+ */
+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+static struct gpio_keys_button ek_buttons[] = {
+        {       /* USER PUSH BUTTON */
+                .code           = KEY_ENTER,
+                .gpio           = AT91_PIN_PB10,
+                .active_low     = 1,
+                .desc           = "user_pb",
+                .wakeup         = 1,
+        }
+};
+
+static struct gpio_keys_platform_data ek_button_data = {
+        .buttons        = ek_buttons,
+        .nbuttons       = ARRAY_SIZE(ek_buttons),
+};
+
+static struct platform_device ek_button_device = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .num_resources  = 0,
+        .dev            = {
+                .platform_data  = &ek_button_data,
+        }
+};
+
+static void __init ek_add_device_buttons(void)
+{
+        at91_set_GPIO_periph(AT91_PIN_PB10, 1); /* user push button, pull up enabled */
+        at91_set_deglitch(AT91_PIN_PB10, 1);
+
+        platform_device_register(&ek_button_device);
+}
+#else
+static void __init ek_add_device_buttons(void) {}
+#endif
+
+/*
+ * LEDs
+ */
+static struct gpio_led ek_leds[] = {
+        {       /* user_led (green) */
+                .name                   = "user_led",
+                .gpio                   = AT91_PIN_PB21,
+                .active_low             = 0,
+                .default_trigger        = "heartbeat",
+        }
+};
+
+static void __init ek_board_init(void)
+{
+        /* Serial */
+        at91_add_device_serial();
+        /* USB Host */
+        at91_add_device_usbh(&ek_usbh_data);
+        /* USB Device */
+        at91_add_device_udc(&ek_udc_data);
+        /* SPI */
+        at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
+        /* NAND */
+        at91_add_device_nand(&ek_nand_data);
+        /* I2C */
+        at91_add_device_i2c(NULL, 0);
+        /* Ethernet */
+        at91_add_device_eth(&ek_macb_data);
+        /* MMC */
+        at91_add_device_mmc(0, &ek_mmc_data);
+        /* Push Buttons */
+        ek_add_device_buttons();
+        /* LEDs */
+        at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
+        /* shutdown controller, wakeup button (5 msec low) */
+        at91_sys_write(AT91_SHDW_MR, AT91_SHDW_CPTWK0_(10) | AT91_SHDW_WKMODE0_LOW
+                                | AT91_SHDW_RTTWKEN);
+}
+
+MACHINE_START(QIL_A9260, "CALAO QIL_A9260")
+        /* Maintainer: calao-systems */
+        .phys_io        = AT91_BASE_SYS,
+        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
+        .boot_params    = AT91_SDRAM_BASE + 0x100,
+        .timer          = &at91sam926x_timer,
+        .map_io         = ek_map_io,
+        .init_irq       = ek_init_irq,
+        .init_machine   = ek_board_init,
+MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c
new file mode 100644
index 000000000000..45617c201240
--- /dev/null
+++ b/arch/arm/mach-at91/board-sam9g20ek.c
@@ -0,0 +1,218 @@
+/*
+ *  Copyright (C) 2005 SAN People
+ *  Copyright (C) 2008 Atmel
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/at73c213.h>
+#include <linux/clk.h>
+
+#include <asm/hardware.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/arch/board.h>
+#include <asm/arch/gpio.h>
+
+#include "generic.h"
+
+
+static void __init ek_map_io(void)
+{
+        /* Initialize processor: 18.432 MHz crystal */
+        at91sam9260_initialize(18432000);
+
+        /* DGBU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+
+        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
+        at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
+                           | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
+                           | ATMEL_UART_RI);
+
+        /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
+        at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
+
+        /* set serial console to ttyS0 (ie, DBGU) */
+        at91_set_serial_console(0);
+}
+
+static void __init ek_init_irq(void)
+{
+        at91sam9260_init_interrupts(NULL);
+}
+
+
+/*
+ * USB Host port
+ */
+static struct at91_usbh_data __initdata ek_usbh_data = {
+        .ports          = 2,
+};
+
+/*
+ * USB Device port
+ */
+static struct at91_udc_data __initdata ek_udc_data = {
+        .vbus_pin       = AT91_PIN_PC5,
+        .pullup_pin     = 0,            /* pull-up driven by UDC */
+};
+
+
+/*
+ * SPI devices.
+ */
+static struct spi_board_info ek_spi_devices[] = {
+#if !defined(CONFIG_MMC_AT91)
+        {       /* DataFlash chip */
+                .modalias       = "mtd_dataflash",
+                .chip_select    = 1,
+                .max_speed_hz   = 15 * 1000 * 1000,
+                .bus_num        = 0,
+        },
+#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
+        {       /* DataFlash card */
+                .modalias       = "mtd_dataflash",
+                .chip_select    = 0,
+                .max_speed_hz   = 15 * 1000 * 1000,
+                .bus_num        = 0,
+        },
+#endif
+#endif
+};
+
+
+/*
+ * MACB Ethernet device
+ */
+static struct at91_eth_data __initdata ek_macb_data = {
+        .phy_irq_pin    = AT91_PIN_PA7,
+        .is_rmii        = 1,
+};
+
+
+/*
+ * NAND flash
+ */
+static struct mtd_partition __initdata ek_nand_partition[] = {
+        {
+                .name   = "Bootstrap",
+                .offset = 0,
+                .size   = 4 * 1024 * 1024,
+        },
+        {
+                .name   = "Partition 1",
+                .offset = 4 * 1024 * 1024,
+                .size   = 60 * 1024 * 1024,
+        },
+        {
+                .name   = "Partition 2",
+                .offset = 64 * 1024 * 1024,
+                .size   = MTDPART_SIZ_FULL,
+        },
+};
+
+static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
+{
+        *num_partitions = ARRAY_SIZE(ek_nand_partition);
+        return ek_nand_partition;
+}
+
+/* det_pin is not connected */
+static struct at91_nand_data __initdata ek_nand_data = {
+        .ale            = 21,
+        .cle            = 22,
+        .rdy_pin        = AT91_PIN_PC13,
+        .enable_pin     = AT91_PIN_PC14,
+        .partition_info = nand_partitions,
+#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
+        .bus_width_16   = 1,
+#else
+        .bus_width_16   = 0,
+#endif
+};
+
+
+/*
+ * MCI (SD/MMC)
+ * det_pin, wp_pin and vcc_pin are not connected
+ */
+static struct at91_mmc_data __initdata ek_mmc_data = {
+        .slot_b         = 1,
+        .wire4          = 1,
+};
+
+
+/*
+ * LEDs
+ */
+static struct gpio_led ek_leds[] = {
+        {       /* "bottom" led, green, userled1 to be defined */
+                .name                   = "ds5",
+                .gpio                   = AT91_PIN_PA6,
+                .active_low             = 1,
+                .default_trigger        = "none",
+        },
+        {       /* "power" led, yellow */
+                .name                   = "ds1",
+                .gpio                   = AT91_PIN_PA9,
+                .default_trigger        = "heartbeat",
+        }
+};
+
+static void __init ek_board_init(void)
+{
+        /* Serial */
+        at91_add_device_serial();
+        /* USB Host */
+        at91_add_device_usbh(&ek_usbh_data);
+        /* USB Device */
+        at91_add_device_udc(&ek_udc_data);
+        /* SPI */
+        at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
+        /* NAND */
+        at91_add_device_nand(&ek_nand_data);
+        /* Ethernet */
+        at91_add_device_eth(&ek_macb_data);
+        /* MMC */
+        at91_add_device_mmc(0, &ek_mmc_data);
+        /* I2C */
+        at91_add_device_i2c(NULL, 0);
+        /* LEDs */
+        at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
+}
+
+MACHINE_START(AT91SAM9G20EK, "Atmel AT91SAM9G20-EK")
+        /* Maintainer: Atmel */
+        .phys_io        = AT91_BASE_SYS,
+        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
+        .boot_params    = AT91_SDRAM_BASE + 0x100,
+        .timer          = &at91sam926x_timer,
+        .map_io         = ek_map_io,
+        .init_irq       = ek_init_irq,
+        .init_machine   = ek_board_init,
+MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c
index ffc0597aee8d..b6a70fc735c3 100644
--- a/arch/arm/mach-at91/board-sam9rlek.c
+++ b/arch/arm/mach-at91/board-sam9rlek.c
@@ -56,6 +56,14 @@ static void __init ek_init_irq(void)
 
 
 /*
+ * USB HS Device port
+ */
+static struct usba_platform_data __initdata ek_usba_udc_data = {
+        .vbus_pin       = AT91_PIN_PA8,
+};
+
+
+/*
  * MCI (SD/MMC)
  */
 static struct at91_mmc_data __initdata ek_mmc_data = {
@@ -175,6 +183,8 @@ static void __init ek_board_init(void)
 {
         /* Serial */
         at91_add_device_serial();
+        /* USB HS */
+        at91_add_device_usba(&ek_usba_udc_data);
         /* I2C */
         at91_add_device_i2c(NULL, 0);
         /* NAND */
diff --git a/arch/arm/mach-at91/board-usb-a9260.c b/arch/arm/mach-at91/board-usb-a9260.c
new file mode 100644
index 000000000000..837aedf8ffeb
--- /dev/null
+++ b/arch/arm/mach-at91/board-usb-a9260.c
@@ -0,0 +1,215 @@
+/*
+ * linux/arch/arm/mach-at91/board-usb-a9260.c
+ *
+ *  Copyright (C) 2005 SAN People
+ *  Copyright (C) 2006 Atmel
+ *  Copyright (C) 2007 Calao-systems
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <linux/clk.h>
+
+#include <asm/hardware.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/arch/board.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/at91_shdwc.h>
+
+#include "generic.h"
+
+
+static void __init ek_map_io(void)
+{
+        /* Initialize processor: 12.000 MHz crystal */
+        at91sam9260_initialize(12000000);
+
+        /* DGBU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+
+        /* set serial console to ttyS0 (ie, DBGU) */
+        at91_set_serial_console(0);
+}
+
+static void __init ek_init_irq(void)
+{
+        at91sam9260_init_interrupts(NULL);
+}
+
+
+/*
+ * USB Host port
+ */
+static struct at91_usbh_data __initdata ek_usbh_data = {
+        .ports          = 2,
+};
+
+/*
+ * USB Device port
+ */
+static struct at91_udc_data __initdata ek_udc_data = {
+        .vbus_pin       = AT91_PIN_PC5,
+        .pullup_pin     = 0,            /* pull-up driven by UDC */
+};
+
+/*
+ * MACB Ethernet device
+ */
+static struct at91_eth_data __initdata ek_macb_data = {
+        .phy_irq_pin    = AT91_PIN_PA31,
+        .is_rmii        = 1,
+};
+
+/*
+ * NAND flash
+ */
+static struct mtd_partition __initdata ek_nand_partition[] = {
+        {
+                .name   = "Uboot & Kernel",
+                .offset = 0x00000000,
+                .size   = 16 * 1024 * 1024,
+        },
+        {
+                .name   = "Root FS",
+                .offset = 0x01000000,
+                .size   = 120 * 1024 * 1024,
+        },
+        {
+                .name   = "FS",
+                .offset = 0x08800000,
+                .size   = 120 * 1024 * 1024,
+        }
+};
+
+static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
+{
+        *num_partitions = ARRAY_SIZE(ek_nand_partition);
+        return ek_nand_partition;
+}
+
+static struct at91_nand_data __initdata ek_nand_data = {
+        .ale            = 21,
+        .cle            = 22,
+//      .det_pin        = ... not connected
+        .rdy_pin        = AT91_PIN_PC13,
+        .enable_pin     = AT91_PIN_PC14,
+        .partition_info = nand_partitions,
+#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
+        .bus_width_16   = 1,
+#else
+        .bus_width_16   = 0,
+#endif
+};
+
+/*
+ * GPIO Buttons
+ */
+
+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+static struct gpio_keys_button ek_buttons[] = {
+        {       /* USER PUSH BUTTON */
+                .code           = KEY_ENTER,
+                .gpio           = AT91_PIN_PB10,
+                .active_low     = 1,
+                .desc           = "user_pb",
+                .wakeup         = 1,
+        }
+};
+
+static struct gpio_keys_platform_data ek_button_data = {
+        .buttons        = ek_buttons,
+        .nbuttons       = ARRAY_SIZE(ek_buttons),
+};
+
+static struct platform_device ek_button_device = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .num_resources  = 0,
+        .dev            = {
+                .platform_data  = &ek_button_data,
+        }
+};
+
+static void __init ek_add_device_buttons(void)
+{
+        at91_set_GPIO_periph(AT91_PIN_PB10, 1); /* user push button, pull up enabled */
+        at91_set_deglitch(AT91_PIN_PB10, 1);
+
+        platform_device_register(&ek_button_device);
+}
+#else
+static void __init ek_add_device_buttons(void) {}
+#endif
+
+/*
+ * LEDs
+ */
+static struct gpio_led ek_leds[] = {
+        {       /* user_led (green) */
+                .name                   = "user_led",
+                .gpio                   = AT91_PIN_PB21,
+                .active_low             = 0,
+                .default_trigger        = "heartbeat",
+        }
+};
+
+static void __init ek_board_init(void)
+{
+        /* Serial */
+        at91_add_device_serial();
+        /* USB Host */
+        at91_add_device_usbh(&ek_usbh_data);
+        /* USB Device */
+        at91_add_device_udc(&ek_udc_data);
+        /* NAND */
+        at91_add_device_nand(&ek_nand_data);
+        /* I2C */
+        at91_add_device_i2c(NULL, 0);
+        /* Ethernet */
+        at91_add_device_eth(&ek_macb_data);
+        /* Push Buttons */
+        ek_add_device_buttons();
+        /* LEDs */
+        at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
+        /* shutdown controller, wakeup button (5 msec low) */
+        at91_sys_write(AT91_SHDW_MR, AT91_SHDW_CPTWK0_(10) | AT91_SHDW_WKMODE0_LOW
+                                | AT91_SHDW_RTTWKEN);
+}
+
+MACHINE_START(USB_A9260, "CALAO USB_A9260")
+        /* Maintainer: calao-systems */
+        .phys_io        = AT91_BASE_SYS,
+        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
+        .boot_params    = AT91_SDRAM_BASE + 0x100,
+        .timer          = &at91sam926x_timer,
+        .map_io         = ek_map_io,
+        .init_irq       = ek_init_irq,
+        .init_machine   = ek_board_init,
+MACHINE_END
diff --git a/arch/arm/mach-at91/board-usb-a9263.c b/arch/arm/mach-at91/board-usb-a9263.c
new file mode 100644
index 000000000000..95800d32bd49
--- /dev/null
+++ b/arch/arm/mach-at91/board-usb-a9263.c
@@ -0,0 +1,230 @@
+/*
+ * linux/arch/arm/mach-at91/board-usb-a9263.c
+ *
+ *  Copyright (C) 2005 SAN People
+ *  Copyright (C) 2007 Atmel Corporation.
+ *  Copyright (C) 2007 Calao-systems
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+
+#include <asm/hardware.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/arch/board.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/at91_shdwc.h>
+
+#include "generic.h"
+
+
+static void __init ek_map_io(void)
+{
+        /* Initialize processor: 12.00 MHz crystal */
+        at91sam9263_initialize(12000000);
+
+        /* DGBU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+
+        /* set serial console to ttyS0 (ie, DBGU) */
+        at91_set_serial_console(0);
+}
+
+static void __init ek_init_irq(void)
+{
+        at91sam9263_init_interrupts(NULL);
+}
+
+
+/*
+ * USB Host port
+ */
+static struct at91_usbh_data __initdata ek_usbh_data = {
+        .ports          = 2,
+};
+
+/*
+ * USB Device port
+ */
+static struct at91_udc_data __initdata ek_udc_data = {
+        .vbus_pin       = AT91_PIN_PB11,
+        .pullup_pin     = 0,            /* pull-up driven by UDC */
+};
+
+/*
+ * SPI devices.
+ */
+static struct spi_board_info ek_spi_devices[] = {
+#if !defined(CONFIG_MMC_AT91)
+        {       /* DataFlash chip */
+                .modalias       = "mtd_dataflash",
+                .chip_select    = 0,
+                .max_speed_hz   = 15 * 1000 * 1000,
+                .bus_num        = 0,
+        }
+#endif
+};
+
+/*
+ * MACB Ethernet device
+ */
+static struct at91_eth_data __initdata ek_macb_data = {
+        .phy_irq_pin    = AT91_PIN_PE31,
+        .is_rmii        = 1,
+};
+
+/*
+ * NAND flash
+ */
+static struct mtd_partition __initdata ek_nand_partition[] = {
+        {
+                .name   = "Linux Kernel",
+                .offset = 0x00000000,
+                .size   = 16 * 1024 * 1024,
+        },
+        {
+                .name   = "Root FS",
+                .offset = 0x01000000,
+                .size   = 120 * 1024 * 1024,
+        },
+        {
+                .name   = "FS",
+                .offset = 0x08800000,
+                .size   = 120 * 1024 * 1024,
+        }
+};
+
+static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
+{
+        *num_partitions = ARRAY_SIZE(ek_nand_partition);
+        return ek_nand_partition;
+}
+
+static struct at91_nand_data __initdata ek_nand_data = {
+        .ale            = 21,
+        .cle            = 22,
+//      .det_pin        = ... not connected
+        .rdy_pin        = AT91_PIN_PA22,
+        .enable_pin     = AT91_PIN_PD15,
+        .partition_info = nand_partitions,
+#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
+        .bus_width_16   = 1,
+#else
+        .bus_width_16   = 0,
+#endif
+};
+
+/*
+ * GPIO Buttons
+ */
+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+static struct gpio_keys_button ek_buttons[] = {
+        {       /* USER PUSH BUTTON */
+                .code           = KEY_ENTER,
+                .gpio           = AT91_PIN_PB10,
+                .active_low     = 1,
+                .desc           = "user_pb",
+                .wakeup         = 1,
+        }
+};
+
+static struct gpio_keys_platform_data ek_button_data = {
+        .buttons        = ek_buttons,
+        .nbuttons       = ARRAY_SIZE(ek_buttons),
+};
+
+static struct platform_device ek_button_device = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .num_resources  = 0,
+        .dev            = {
+                .platform_data  = &ek_button_data,
+        }
+};
+
+static void __init ek_add_device_buttons(void)
+{
+        at91_set_GPIO_periph(AT91_PIN_PB10, 1); /* user push button, pull up enabled */
+        at91_set_deglitch(AT91_PIN_PB10, 1);
+
+        platform_device_register(&ek_button_device);
+}
+#else
+static void __init ek_add_device_buttons(void) {}
+#endif
+
+/*
+ * LEDs
+ */
+static struct gpio_led ek_leds[] = {
+        {       /* user_led (green) */
+                .name                   = "user_led",
+                .gpio                   = AT91_PIN_PB21,
+                .active_low             = 1,
+                .default_trigger        = "heartbeat",
+        }
+};
+
+
+static void __init ek_board_init(void)
+{
+        /* Serial */
+        at91_add_device_serial();
+        /* USB Host */
+        at91_add_device_usbh(&ek_usbh_data);
+        /* USB Device */
+        at91_add_device_udc(&ek_udc_data);
+        /* SPI */
+        at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
+        /* Ethernet */
+        at91_add_device_eth(&ek_macb_data);
+        /* NAND */
+        at91_add_device_nand(&ek_nand_data);
+        /* I2C */
+        at91_add_device_i2c(NULL, 0);
+        /* Push Buttons */
+        ek_add_device_buttons();
+        /* LEDs */
+        at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
+        /* shutdown controller, wakeup button (5 msec low) */
+        at91_sys_write(AT91_SHDW_MR, AT91_SHDW_CPTWK0_(10) | AT91_SHDW_WKMODE0_LOW
+                                | AT91_SHDW_RTTWKEN);
+}
+
+MACHINE_START(USB_A9263, "CALAO USB_A9263")
+        /* Maintainer: calao-systems */
+        .phys_io        = AT91_BASE_SYS,
+        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
+        .boot_params    = AT91_SDRAM_BASE + 0x100,
+        .timer          = &at91sam926x_timer,
+        .map_io         = ek_map_io,
+        .init_irq       = ek_init_irq,
+        .init_machine   = ek_board_init,
+MACHINE_END
diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c
index b5717108991d..7079050ab88d 100755
--- a/arch/arm/mach-at91/board-yl-9200.c
+++ b/arch/arm/mach-at91/board-yl-9200.c
@@ -1,11 +1,10 @@
 /*
  * linux/arch/arm/mach-at91/board-yl-9200.c
  *
- * Adapted from:
- *various board files in
- * /arch/arm/mach-at91
- * modifications  to convert to  YL-9200 platform
- *  Copyright (C) 2007 S.Birtles
+ * Adapted from various board files in arch/arm/mach-at91
+ *
+ * Modifications for YL-9200 platform:
+ *  Copyright (C) 2007 S. Birtles
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -26,13 +25,14 @@
 #include <linux/init.h>
 #include <linux/mm.h>
 #include <linux/module.h>
+#include <linux/dma-mapping.h>
 #include <linux/platform_device.h>
 #include <linux/spi/spi.h>
-/*#include <linux/can_bus/candata.h>*/
 #include <linux/spi/ads7846.h>
 #include <linux/mtd/physmap.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
 
-/*#include <sound/gpio_sounder.h>*/
 #include <asm/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -45,179 +45,108 @@
 #include <asm/arch/board.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/at91rm9200_mc.h>
-#include <linux/gpio_keys.h>
-#include <linux/input.h>
 
 #include "generic.h"
-#include <asm/arch/at91_pio.h>
 
-#define YL_9200_FLASH_BASE      AT91_CHIPSELECT_0
-#define YL_9200_FLASH_SIZE      0x800000
 
-/*
- * Serial port configuration.
- *    0 .. 3 = USART0 .. USART3
- *    4      = DBGU
- *atmel_usart.0: ttyS0 at MMIO 0xfefff200 (irq = 1) is a ATMEL_SERIAL
- *atmel_usart.1: ttyS1 at MMIO 0xfffc0000 (irq = 6) is a ATMEL_SERIAL
- *atmel_usart.2: ttyS2 at MMIO 0xfffc4000 (irq = 7) is a ATMEL_SERIAL
- *atmel_usart.3: ttyS3 at MMIO 0xfffc8000 (irq = 8) is a ATMEL_SERIAL
- *atmel_usart.4: ttyS4 at MMIO 0xfffcc000 (irq = 9) is a ATMEL_SERIAL
- * on the YL-9200 we are sitting at the following
- *ttyS0 at MMIO 0xfefff200 (irq = 1) is a AT91_SERIAL
- *ttyS1 at MMIO 0xfefc4000 (irq = 7) is a AT91_SERIAL
- */
+static void __init yl9200_map_io(void)
+{
+        /* Initialize processor: 18.432 MHz crystal */
+        at91rm9200_initialize(18432000, AT91RM9200_PQFP);
 
-/* extern void __init yl_9200_add_device_sounder(struct gpio_sounder *sounders, int nr);*/
+        /* Setup the LEDs D2=PB17 (timer), D3=PB16 (cpu) */
+        at91_init_leds(AT91_PIN_PB16, AT91_PIN_PB17);
 
-static struct at91_uart_config __initdata yl_9200_uart_config = {
-        .console_tty    = 0,                            /* ttyS0 */
-        .nr_tty         = 3,
-        .tty_map        = { 4, 1, 0, -1, -1 }           /* ttyS0, ..., ttyS4 */
-};
+        /* DBGU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
 
-static void __init yl_9200_map_io(void)
-{
-        /* Initialize processor: 18.432 MHz crystal */
-        /*Also initialises register clocks & gpio*/
-        at91rm9200_initialize(18432000, AT91RM9200_PQFP); /*we have a 3 bank system*/
+        /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
+        at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
+                        | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
+                        | ATMEL_UART_RI);
 
-        /* Setup the serial ports and console */
-        at91_init_serial(&yl_9200_uart_config);
+        /* USART0 on ttyS2. (Rx & Tx only to JP3) */
+        at91_register_uart(AT91RM9200_ID_US0, 2, 0);
 
-        /* Setup the LEDs D2=PB17,D3=PB16 */
-        at91_init_leds(AT91_PIN_PB16,AT91_PIN_PB17); /*cpu-led,timer-led*/
+        /* USART3 on ttyS3. (Rx, Tx, RTS - RS485 interface) */
+        at91_register_uart(AT91RM9200_ID_US3, 3, ATMEL_UART_RTS);
+
+        /* set serial console to ttyS0 (ie, DBGU) */
+        at91_set_serial_console(0);
 }
 
-static void __init yl_9200_init_irq(void)
+static void __init yl9200_init_irq(void)
 {
         at91rm9200_init_interrupts(NULL);
 }
 
-static struct at91_eth_data __initdata yl_9200_eth_data = {
-        .phy_irq_pin    = AT91_PIN_PB28,
-        .is_rmii        = 1,
-};
 
-static struct at91_usbh_data __initdata yl_9200_usbh_data = {
-        .ports          = 1,  /* this should be 1 not 2 for the Yl9200*/
+/*
+ * LEDs
+ */
+static struct gpio_led yl9200_leds[] = {
+        {       /* D2 */
+                .name                   = "led2",
+                .gpio                   = AT91_PIN_PB17,
+                .active_low             = 1,
+                .default_trigger        = "timer",
+        },
+        {       /* D3 */
+                .name                   = "led3",
+                .gpio                   = AT91_PIN_PB16,
+                .active_low             = 1,
+                .default_trigger        = "heartbeat",
+        },
+        {       /* D4 */
+                .name                   = "led4",
+                .gpio                   = AT91_PIN_PB15,
+                .active_low             = 1,
+        },
+        {       /* D5 */
+                .name                   = "led5",
+                .gpio                   = AT91_PIN_PB8,
+                .active_low             = 1,
+        }
 };
 
-static struct at91_udc_data __initdata yl_9200_udc_data = {
-/*on sheet 7 Schemitic rev 1.0*/
-        .pullup_pin     = AT91_PIN_PC4,
-        .vbus_pin=  AT91_PIN_PC5,
-        .pullup_active_low = 1, /*ACTIVE LOW!! due to PNP transistor on page 7*/
-
-};
 /*
-static struct at91_cf_data __initdata yl_9200_cf_data = {
-TODO S.BIRTLES
-        .det_pin        = AT91_PIN_xxx,
-        .rst_pin        = AT91_PIN_xxx,
-        .irq_pin        = ... not connected
-        .vcc_pin        = ... always powered
-
+ * Ethernet
+ */
+static struct at91_eth_data __initdata yl9200_eth_data = {
+        .phy_irq_pin            = AT91_PIN_PB28,
+        .is_rmii                = 1,
 };
-*/
-static struct at91_mmc_data __initdata yl_9200_mmc_data = {
-        .det_pin        = AT91_PIN_PB9, /*THIS LOOKS CORRECT SHEET7*/
-/*      .wp_pin         = ... not connected  SHEET7*/
-        .slot_b         = 0,
-        .wire4          = 1,
 
+/*
+ * USB Host
+ */
+static struct at91_usbh_data __initdata yl9200_usbh_data = {
+        .ports                  = 1,    /* PQFP version of AT91RM9200 */
 };
 
-/* --------------------------------------------------------------------
- *  Touch screen
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
-static int ads7843_pendown_state(void)
-{
-        return !at91_get_gpio_value(AT91_PIN_PB11);     /* Touchscreen PENIRQ */
-}
-
-static void __init at91_init_device_ts(void)
-{
-/*IMPORTANT NOTE THE SPI INTERFACE IS ALREADY CONFIGURED BY XXX_DEVICES.C
-THAT IS TO SAY THAT  MISO,MOSI,SPCK AND CS  are already configured
-we only need to enable the other datapins which are:
-PB10/RK1 BUSY
-*/
-/* Touchscreen BUSY signal ,  pin,use pullup ( TODO not currently used in the ADS7843/6.c driver)*/
-at91_set_gpio_input(AT91_PIN_PB10, 1);
-}
-
-#else
-static void __init at91_init_device_ts(void) {}
-#endif
-
-static struct ads7846_platform_data ads_info = {
-        .model                  = 7843,
-        .x_min                  = 150,
-        .x_max                  = 3830,
-        .y_min                  = 190,
-        .y_max                  = 3830,
-        .vref_delay_usecs       = 100,
-/* for a 8" touch screen*/
-        //.x_plate_ohms         = 603, //= 450, S.Birtles TODO
-        //.y_plate_ohms         = 332, //= 250, S.Birtles TODO
-/*for a 10.4" touch screen*/
-        //.x_plate_ohms         =611,
-        //.y_plate_ohms         =325,
-
-        .x_plate_ohms   = 576,
-        .y_plate_ohms   = 366,
-                //
-        .pressure_max           = 15000, /*generally nonsense on the 7843*/
-         /*number of times to send query to chip in a given run 0 equals one time (do not set to 0!! ,there is a bug in ADS 7846 code)*/
-        .debounce_max           = 1,
-        .debounce_rep           = 0,
-        .debounce_tol           = (~0),
-        .get_pendown_state      = ads7843_pendown_state,
-};
+/*
+ * USB Device
+ */
+static struct at91_udc_data __initdata yl9200_udc_data = {
+        .pullup_pin             = AT91_PIN_PC4,
+        .vbus_pin               = AT91_PIN_PC5,
+        .pullup_active_low      = 1,    /* Active Low due to PNP transistor (pg 7) */
 
-/*static struct canbus_platform_data can_info = {
-        .model                  = 2510,
 };
-*/
-
-static struct spi_board_info yl_9200_spi_devices[] = {
-/*this sticks it at:
- /sys/devices/platform/atmel_spi.0/spi0.0
- /sys/bus/platform/devices/
-Documentation/spi IIRC*/
 
-#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
- /*(this IS correct 04-NOV-2007)*/
-        {
-                .modalias               = "ads7846", /* because the driver is called ads7846*/
-                .chip_select    = 0, /*THIS MUST BE AN INDEX INTO AN ARRAY OF  pins */
-/*this is ONLY TO BE USED if chipselect above is not used, it passes a pin directly for the chip select*/
-                /*.controller_data =AT91_PIN_PA3 ,*/
-                .max_speed_hz   = 5000*26, /*(4700 * 26)-125000 * 26, (max sample rate @ 3V) * (cmd + data + overhead) */
-                .bus_num                = 0,
-                .platform_data  = &ads_info,
-                .irq                    = AT91_PIN_PB11,
-        },
-#endif
-/*we need to put our CAN driver data here!!*/
-/*THIS IS ALL DUMMY DATA*/
-/*      {
-                .modalias               = "mcp2510", //DUMMY for MCP2510 chip
-                .chip_select    = 1,*/ /*THIS MUST BE AN INDEX INTO AN ARRAY OF  pins */
-        /*this is ONLY TO BE USED if chipselect above is not used, it passes a pin directly for the chip select */
-        /*  .controller_data =AT91_PIN_PA4 ,
-                .max_speed_hz   = 25000 * 26,
-                .bus_num                = 0,
-                .platform_data  = &can_info,
-                .irq                    = AT91_PIN_PC0,
-        },
-        */
-        //max SPI chip needs to go here
+/*
+ * MMC
+ */
+static struct at91_mmc_data __initdata yl9200_mmc_data = {
+        .det_pin        = AT91_PIN_PB9,
+        // .wp_pin      = ... not connected
+        .wire4          = 1,
 };
 
-static struct mtd_partition __initdata yl_9200_nand_partition[] = {
+/*
+ * NAND Flash
+ */
+static struct mtd_partition __initdata yl9200_nand_partition[] = {
         {
                 .name   = "AT91 NAND partition 1, boot",
                 .offset = 0,
@@ -242,442 +171,434 @@ static struct mtd_partition __initdata yl_9200_nand_partition[] = {
                 .name   = "AT91 NAND partition 5, ext-fs",
                 .offset = 32 * SZ_1M,
                 .size   = 32 * SZ_1M
-        },
+        }
 };
 
 static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
 {
-        *num_partitions = ARRAY_SIZE(yl_9200_nand_partition);
-        return yl_9200_nand_partition;
+        *num_partitions = ARRAY_SIZE(yl9200_nand_partition);
+        return yl9200_nand_partition;
 }
 
-static struct at91_nand_data __initdata yl_9200_nand_data = {
-        .ale= 6,
-        .cle= 7,
-        /*.det_pin      = AT91_PIN_PCxx,*/   /*we don't have a det pin because NandFlash is fixed to board*/
-        .rdy_pin        = AT91_PIN_PC14,  /*R/!B Sheet10*/
-        .enable_pin     = AT91_PIN_PC15,  /*!CE  Sheet10 */
+static struct at91_nand_data __initdata yl9200_nand_data = {
+        .ale            = 6,
+        .cle            = 7,
+        // .det_pin     = ... not connected
+        .rdy_pin        = AT91_PIN_PC14,        /* R/!B (Sheet10) */
+        .enable_pin     = AT91_PIN_PC15,        /* !CE  (Sheet10) */
         .partition_info = nand_partitions,
 };
 
-
-
 /*
-TODO S.Birtles
-potentially a problem with the size above
-physmap platform flash device: 00800000 at 10000000
-physmap-flash.0: Found 1 x16 devices at 0x0 in 16-bit bank
-NOR chip too large to fit in mapping. Attempting to cope...
- Intel/Sharp Extended Query Table at 0x0031
-Using buffer write method
-cfi_cmdset_0001: Erase suspend on write enabled
-Reducing visibility of 16384KiB chip to 8192KiB
-*/
+ * NOR Flash
+ */
+#define YL9200_FLASH_BASE       AT91_CHIPSELECT_0
+#define YL9200_FLASH_SIZE       0x1000000
 
-static struct mtd_partition yl_9200_flash_partitions[] = {
+static struct mtd_partition yl9200_flash_partitions[] = {
+        {
+                .name           = "Bootloader",
+                .size           = 0x00040000,
+                .offset         = 0,
+                .mask_flags     = MTD_WRITEABLE,        /* force read-only */
+        },
         {
-                .name =         "Bootloader",
-                .size =         0x00040000,
-                .offset =       0,
-                .mask_flags =   MTD_WRITEABLE  /* force read-only */
-        },{
-                .name =         "Kernel",
-                .size =         0x001C0000,
-                .offset =       0x00040000,
-        },{
-                .name =         "Filesystem",
-                .size =         MTDPART_SIZ_FULL,
-                .offset =       0x00200000
+                .name           = "Kernel",
+                .size           = 0x001C0000,
+                .offset         = 0x00040000,
+        },
+        {
+                .name           = "Filesystem",
+                .size           = MTDPART_SIZ_FULL,
+                .offset         = 0x00200000
         }
-
 };
 
-static struct physmap_flash_data yl_9200_flash_data = {
-        .width  = 2,
-        .parts          = yl_9200_flash_partitions,
-        .nr_parts       = ARRAY_SIZE(yl_9200_flash_partitions),
+static struct physmap_flash_data yl9200_flash_data = {
+        .width          = 2,
+        .parts          = yl9200_flash_partitions,
+        .nr_parts       = ARRAY_SIZE(yl9200_flash_partitions),
 };
 
-static struct resource yl_9200_flash_resources[] = {
-{
-        .start          = YL_9200_FLASH_BASE,
-        .end            = YL_9200_FLASH_BASE + YL_9200_FLASH_SIZE - 1,
-        .flags          = IORESOURCE_MEM,
+static struct resource yl9200_flash_resources[] = {
+        {
+                .start  = YL9200_FLASH_BASE,
+                .end    = YL9200_FLASH_BASE + YL9200_FLASH_SIZE - 1,
+                .flags  = IORESOURCE_MEM,
         }
 };
 
-static struct platform_device yl_9200_flash = {
+static struct platform_device yl9200_flash = {
         .name           = "physmap-flash",
         .id             = 0,
         .dev            = {
-                                .platform_data  = &yl_9200_flash_data,
+                                .platform_data  = &yl9200_flash_data,
                         },
-        .resource       = yl_9200_flash_resources,
-        .num_resources  = ARRAY_SIZE(yl_9200_flash_resources),
+        .resource       = yl9200_flash_resources,
+        .num_resources  = ARRAY_SIZE(yl9200_flash_resources),
 };
 
-
-static struct gpio_led yl_9200_leds[] = {
-/*D2 &D3 are passed directly in via at91_init_leds*/
-        {
-                .name                   = "led4",  /*D4*/
-                .gpio                   = AT91_PIN_PB15,
-                .active_low             = 1,
-                .default_trigger        = "heartbeat",
-                /*.default_trigger      = "timer",*/
-        },
-        {
-                .name                   = "led5",  /*D5*/
-                .gpio                   = AT91_PIN_PB8,
-                .active_low             = 1,
-                .default_trigger        = "heartbeat",
-        }
-};
-
-//static struct gpio_sounder yl_9200_sounder[] = {*/
-/*This is a simple speaker attached to a gpo line*/
-
-//      {
-//              .name                   = "Speaker",  /*LS1*/
-//              .gpio                   = AT91_PIN_PA22,
-//              .active_low             = 0,
-//              .default_trigger        = "heartbeat",
-                /*.default_trigger      = "timer",*/
-//      },
-//};
-
-
-
-static struct i2c_board_info __initdata yl_9200_i2c_devices[] = {
-        {
-        /*TODO*/
-                I2C_BOARD_INFO("CS4334", 0x00),
+/*
+ * I2C (TWI)
+ */
+static struct i2c_board_info __initdata yl9200_i2c_devices[] = {
+        {       /* EEPROM */
+                I2C_BOARD_INFO("24c128", 0x50),
         }
 };
 
-
- /*
+/*
  * GPIO Buttons
- */
+*/
 #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
-static struct gpio_keys_button yl_9200_buttons[] = {
+static struct gpio_keys_button yl9200_buttons[] = {
         {
                 .gpio           = AT91_PIN_PA24,
-                .code   = BTN_2,
+                .code           = BTN_2,
                 .desc           = "SW2",
                 .active_low     = 1,
                 .wakeup         = 1,
         },
         {
                 .gpio           = AT91_PIN_PB1,
-                .code   = BTN_3,
+                .code           = BTN_3,
                 .desc           = "SW3",
                 .active_low     = 1,
                 .wakeup         = 1,
         },
         {
                 .gpio           = AT91_PIN_PB2,
-                .code   = BTN_4,
+                .code           = BTN_4,
                 .desc           = "SW4",
                 .active_low     = 1,
                 .wakeup         = 1,
         },
         {
                 .gpio           = AT91_PIN_PB6,
-                .code   = BTN_5,
+                .code           = BTN_5,
                 .desc           = "SW5",
                 .active_low     = 1,
                 .wakeup         = 1,
-        },
-
+        }
 };
 
-static struct gpio_keys_platform_data yl_9200_button_data = {
-        .buttons        = yl_9200_buttons,
-        .nbuttons       = ARRAY_SIZE(yl_9200_buttons),
+static struct gpio_keys_platform_data yl9200_button_data = {
+        .buttons        = yl9200_buttons,
+        .nbuttons       = ARRAY_SIZE(yl9200_buttons),
 };
 
-static struct platform_device yl_9200_button_device = {
+static struct platform_device yl9200_button_device = {
         .name           = "gpio-keys",
         .id             = -1,
         .num_resources  = 0,
         .dev            = {
-        .platform_data  = &yl_9200_button_data,
+                .platform_data  = &yl9200_button_data,
         }
 };
 
-static void __init yl_9200_add_device_buttons(void)
+static void __init yl9200_add_device_buttons(void)
 {
-        //SW2
-        at91_set_gpio_input(AT91_PIN_PA24, 0);
+        at91_set_gpio_input(AT91_PIN_PA24, 1);  /* SW2 */
         at91_set_deglitch(AT91_PIN_PA24, 1);
-
-        //SW3
-        at91_set_gpio_input(AT91_PIN_PB1, 0);
+        at91_set_gpio_input(AT91_PIN_PB1, 1);   /* SW3 */
         at91_set_deglitch(AT91_PIN_PB1, 1);
-        //SW4
-        at91_set_gpio_input(AT91_PIN_PB2, 0);
+        at91_set_gpio_input(AT91_PIN_PB2, 1);   /* SW4 */
         at91_set_deglitch(AT91_PIN_PB2, 1);
-
-        //SW5
-        at91_set_gpio_input(AT91_PIN_PB6, 0);
+        at91_set_gpio_input(AT91_PIN_PB6, 1);   /* SW5 */
         at91_set_deglitch(AT91_PIN_PB6, 1);
 
+        /* Enable buttons (Sheet 5) */
+        at91_set_gpio_output(AT91_PIN_PB7, 1);
+
+        platform_device_register(&yl9200_button_device);
+}
+#else
+static void __init yl9200_add_device_buttons(void) {}
+#endif
+
+/*
+ * Touchscreen
+ */
+#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
+static int ads7843_pendown_state(void)
+{
+        return !at91_get_gpio_value(AT91_PIN_PB11);     /* Touchscreen PENIRQ */
+}
+
+static struct ads7846_platform_data ads_info = {
+        .model                  = 7843,
+        .x_min                  = 150,
+        .x_max                  = 3830,
+        .y_min                  = 190,
+        .y_max                  = 3830,
+        .vref_delay_usecs       = 100,
+
+        /* For a 8" touch-screen */
+        // .x_plate_ohms                = 603,
+        // .y_plate_ohms                = 332,
+
+        /* For a 10.4" touch-screen */
+        // .x_plate_ohms                = 611,
+        // .y_plate_ohms                = 325,
+
+        .x_plate_ohms           = 576,
+        .y_plate_ohms           = 366,
+
+        .pressure_max           = 15000, /* generally nonsense on the 7843 */
+        .debounce_max           = 1,
+        .debounce_rep           = 0,
+        .debounce_tol           = (~0),
+        .get_pendown_state      = ads7843_pendown_state,
+};
 
-        at91_set_gpio_output(AT91_PIN_PB7, 1);  /* #TURN BUTTONS ON, SHEET 5  of schematics */
-        platform_device_register(&yl_9200_button_device);
+static void __init yl9200_add_device_ts(void)
+{
+        at91_set_gpio_input(AT91_PIN_PB11, 1);  /* Touchscreen interrupt pin */
+        at91_set_gpio_input(AT91_PIN_PB10, 1);  /* Touchscreen BUSY signal - not used! */
 }
 #else
-static void __init yl_9200_add_device_buttons(void) {}
+static void __init yl9200_add_device_ts(void) {}
+#endif
+
+/*
+ * SPI devices
+ */
+static struct spi_board_info yl9200_spi_devices[] = {
+#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
+        {       /* Touchscreen */
+                .modalias       = "ads7846",
+                .chip_select    = 0,
+                .max_speed_hz   = 5000 * 26,
+                .platform_data  = &ads_info,
+                .irq            = AT91_PIN_PB11,
+        },
 #endif
+        {       /* CAN */
+                .modalias       = "mcp2510",
+                .chip_select    = 1,
+                .max_speed_hz   = 25000 * 26,
+                .irq            = AT91_PIN_PC0,
+        }
+};
 
+/*
+ * LCD / VGA
+ *
+ * EPSON S1D13806 FB (discontinued chip)
+ * EPSON S1D13506 FB
+ */
 #if defined(CONFIG_FB_S1D135XX) || defined(CONFIG_FB_S1D13XXX_MODULE)
 #include <video/s1d13xxxfb.h>
 
-/* EPSON S1D13806 FB (discontinued chip)*/
-/* EPSON S1D13506 FB */
-
 #define AT91_FB_REG_BASE        0x80000000L
 #define AT91_FB_REG_SIZE        0x200
 #define AT91_FB_VMEM_BASE       0x80200000L
 #define AT91_FB_VMEM_SIZE       0x200000L
 
-/*#define S1D_DISPLAY_WIDTH           640*/
-/*#define S1D_DISPLAY_HEIGHT          480*/
-
-
-static void __init yl_9200_init_video(void)
+static void __init yl9200_init_video(void)
 {
-        at91_sys_write(AT91_PIOC + PIO_ASR,AT91_PIN_PC6);
-        at91_sys_write(AT91_PIOC + PIO_BSR,0);
-        at91_sys_write(AT91_PIOC + PIO_ASR,AT91_PIN_PC6);
-
-        at91_sys_write( AT91_SMC_CSR(2),
-        AT91_SMC_NWS_(0x4) |
-        AT91_SMC_WSEN |
-        AT91_SMC_TDF_(0x100) |
-        AT91_SMC_DBW
-        );
-
-
+        /* NWAIT Signal */
+        at91_set_A_periph(AT91_PIN_PC6, 0);
 
+        /* Initialization of the Static Memory Controller for Chip Select 2 */
+        at91_sys_write(AT91_SMC_CSR(2), AT91_SMC_DBW_16         /* 16 bit */
+                        | AT91_SMC_WSEN | AT91_SMC_NWS_(0x4)    /* wait states */
+                        | AT91_SMC_TDF_(0x100)                  /* float time */
+        );
 }
 
-
-static struct s1d13xxxfb_regval yl_9200_s1dfb_initregs[] =
+static struct s1d13xxxfb_regval yl9200_s1dfb_initregs[] =
 {
-        {S1DREG_MISC,                           0x00},   /* Miscellaneous Register*/
-        {S1DREG_COM_DISP_MODE,          0x01},   /* Display Mode Register, LCD only*/
-        {S1DREG_GPIO_CNF0,                      0x00},   /* General IO Pins Configuration Register*/
-        {S1DREG_GPIO_CTL0,                      0x00},   /* General IO Pins Control Register*/
-        {S1DREG_CLK_CNF,                        0x11},   /* Memory Clock Configuration Register*/
-        {S1DREG_LCD_CLK_CNF,            0x10},   /* LCD Pixel Clock Configuration Register*/
-        {S1DREG_CRT_CLK_CNF,            0x12},   /* CRT/TV Pixel Clock Configuration Register*/
-        {S1DREG_MPLUG_CLK_CNF,          0x01},   /* MediaPlug Clock Configuration Register*/
-        {S1DREG_CPU2MEM_WST_SEL,        0x02},   /* CPU To Memory Wait State Select Register*/
-        {S1DREG_MEM_CNF,                        0x00},   /* Memory Configuration Register*/
-        {S1DREG_SDRAM_REF_RATE,         0x04},   /* DRAM Refresh Rate Register, MCLK source*/
-        {S1DREG_SDRAM_TC0,                      0x12},   /* DRAM Timings Control Register 0*/
-        {S1DREG_SDRAM_TC1,                      0x02},   /* DRAM Timings Control Register 1*/
-        {S1DREG_PANEL_TYPE,                     0x25},   /* Panel Type Register*/
-        {S1DREG_MOD_RATE,                       0x00},   /* MOD Rate Register*/
-        {S1DREG_LCD_DISP_HWIDTH,        0x4F},   /* LCD Horizontal Display Width Register*/
-        {S1DREG_LCD_NDISP_HPER,         0x13},   /* LCD Horizontal Non-Display Period Register*/
-        {S1DREG_TFT_FPLINE_START,       0x01},   /* TFT FPLINE Start Position Register*/
-        {S1DREG_TFT_FPLINE_PWIDTH,      0x0c},   /* TFT FPLINE Pulse Width Register*/
-        {S1DREG_LCD_DISP_VHEIGHT0,      0xDF},   /* LCD Vertical Display Height Register 0*/
-        {S1DREG_LCD_DISP_VHEIGHT1,      0x01},   /* LCD Vertical Display Height Register 1*/
-        {S1DREG_LCD_NDISP_VPER,         0x2c},   /* LCD Vertical Non-Display Period Register*/
-        {S1DREG_TFT_FPFRAME_START,      0x0a},   /* TFT FPFRAME Start Position Register*/
-        {S1DREG_TFT_FPFRAME_PWIDTH,     0x02},   /* TFT FPFRAME Pulse Width Register*/
-        {S1DREG_LCD_DISP_MODE,          0x05},   /* LCD Display Mode Register*/
-        {S1DREG_LCD_MISC,                       0x01},   /* LCD Miscellaneous Register*/
-        {S1DREG_LCD_DISP_START0,        0x00},   /* LCD Display Start Address Register 0*/
-        {S1DREG_LCD_DISP_START1,        0x00},   /* LCD Display Start Address Register 1*/
-        {S1DREG_LCD_DISP_START2,        0x00},   /* LCD Display Start Address Register 2*/
-        {S1DREG_LCD_MEM_OFF0,           0x80},   /* LCD Memory Address Offset Register 0*/
-        {S1DREG_LCD_MEM_OFF1,           0x02},   /* LCD Memory Address Offset Register 1*/
-        {S1DREG_LCD_PIX_PAN,            0x03},   /* LCD Pixel Panning Register*/
-        {S1DREG_LCD_DISP_FIFO_HTC,      0x00},   /* LCD Display FIFO High Threshold Control Register*/
-        {S1DREG_LCD_DISP_FIFO_LTC,      0x00},   /* LCD Display FIFO Low Threshold Control Register*/
-        {S1DREG_CRT_DISP_HWIDTH,        0x4F},   /* CRT/TV Horizontal Display Width Register*/
-        {S1DREG_CRT_NDISP_HPER,         0x13},   /* CRT/TV Horizontal Non-Display Period Register*/
-        {S1DREG_CRT_HRTC_START,         0x01},   /* CRT/TV HRTC Start Position Register*/
-        {S1DREG_CRT_HRTC_PWIDTH,        0x0B},   /* CRT/TV HRTC Pulse Width Register*/
-        {S1DREG_CRT_DISP_VHEIGHT0,      0xDF},   /* CRT/TV Vertical Display Height Register 0*/
-        {S1DREG_CRT_DISP_VHEIGHT1,      0x01},   /* CRT/TV Vertical Display Height Register 1*/
-        {S1DREG_CRT_NDISP_VPER,         0x2B},   /* CRT/TV Vertical Non-Display Period Register*/
-        {S1DREG_CRT_VRTC_START,         0x09},   /* CRT/TV VRTC Start Position Register*/
-        {S1DREG_CRT_VRTC_PWIDTH,        0x01},   /* CRT/TV VRTC Pulse Width Register*/
-        {S1DREG_TV_OUT_CTL,                     0x18},   /* TV Output Control Register */
-        {S1DREG_CRT_DISP_MODE,          0x05},   /* CRT/TV Display Mode Register, 16BPP*/
-        {S1DREG_CRT_DISP_START0,        0x00},   /* CRT/TV Display Start Address Register 0*/
-        {S1DREG_CRT_DISP_START1,        0x00},   /* CRT/TV Display Start Address Register 1*/
-        {S1DREG_CRT_DISP_START2,        0x00},   /* CRT/TV Display Start Address Register 2*/
-        {S1DREG_CRT_MEM_OFF0,           0x80},   /* CRT/TV Memory Address Offset Register 0*/
-        {S1DREG_CRT_MEM_OFF1,           0x02},   /* CRT/TV Memory Address Offset Register 1*/
-        {S1DREG_CRT_PIX_PAN,            0x00},   /* CRT/TV Pixel Panning Register*/
-        {S1DREG_CRT_DISP_FIFO_HTC,      0x00},   /* CRT/TV Display FIFO High Threshold Control Register*/
-        {S1DREG_CRT_DISP_FIFO_LTC,      0x00},   /* CRT/TV Display FIFO Low Threshold Control Register*/
-        {S1DREG_LCD_CUR_CTL,            0x00},   /* LCD Ink/Cursor Control Register*/
-        {S1DREG_LCD_CUR_START,          0x01},   /* LCD Ink/Cursor Start Address Register*/
-        {S1DREG_LCD_CUR_XPOS0,          0x00},   /* LCD Cursor X Position Register 0*/
-        {S1DREG_LCD_CUR_XPOS1,          0x00},   /* LCD Cursor X Position Register 1*/
-        {S1DREG_LCD_CUR_YPOS0,          0x00},   /* LCD Cursor Y Position Register 0*/
-        {S1DREG_LCD_CUR_YPOS1,          0x00},   /* LCD Cursor Y Position Register 1*/
-        {S1DREG_LCD_CUR_BCTL0,          0x00},   /* LCD Ink/Cursor Blue Color 0 Register*/
-        {S1DREG_LCD_CUR_GCTL0,          0x00},   /* LCD Ink/Cursor Green Color 0 Register*/
-        {S1DREG_LCD_CUR_RCTL0,          0x00},   /* LCD Ink/Cursor Red Color 0 Register*/
-        {S1DREG_LCD_CUR_BCTL1,          0x1F},   /* LCD Ink/Cursor Blue Color 1 Register*/
-        {S1DREG_LCD_CUR_GCTL1,          0x3F},   /* LCD Ink/Cursor Green Color 1 Register*/
-        {S1DREG_LCD_CUR_RCTL1,          0x1F},   /* LCD Ink/Cursor Red Color 1 Register*/
-        {S1DREG_LCD_CUR_FIFO_HTC,       0x00},   /* LCD Ink/Cursor FIFO Threshold Register*/
-        {S1DREG_CRT_CUR_CTL,            0x00},   /* CRT/TV Ink/Cursor Control Register*/
-        {S1DREG_CRT_CUR_START,          0x01},   /* CRT/TV Ink/Cursor Start Address Register*/
-        {S1DREG_CRT_CUR_XPOS0,          0x00},   /* CRT/TV Cursor X Position Register 0*/
-        {S1DREG_CRT_CUR_XPOS1,          0x00},   /* CRT/TV Cursor X Position Register 1*/
-        {S1DREG_CRT_CUR_YPOS0,          0x00},   /* CRT/TV Cursor Y Position Register 0*/
-        {S1DREG_CRT_CUR_YPOS1,          0x00},   /* CRT/TV Cursor Y Position Register 1*/
-        {S1DREG_CRT_CUR_BCTL0,          0x00},   /* CRT/TV Ink/Cursor Blue Color 0 Register*/
-        {S1DREG_CRT_CUR_GCTL0,          0x00},   /* CRT/TV Ink/Cursor Green Color 0 Register*/
-        {S1DREG_CRT_CUR_RCTL0,          0x00},   /* CRT/TV Ink/Cursor Red Color 0 Register*/
-        {S1DREG_CRT_CUR_BCTL1,          0x1F},   /* CRT/TV Ink/Cursor Blue Color 1 Register*/
-        {S1DREG_CRT_CUR_GCTL1,          0x3F},   /* CRT/TV Ink/Cursor Green Color 1 Register*/
-        {S1DREG_CRT_CUR_RCTL1,          0x1F},   /* CRT/TV Ink/Cursor Red Color 1 Register*/
-        {S1DREG_CRT_CUR_FIFO_HTC,       0x00},   /* CRT/TV Ink/Cursor FIFO Threshold Register*/
-        {S1DREG_BBLT_CTL0,                      0x00},   /* BitBlt Control Register 0*/
-        {S1DREG_BBLT_CTL1,                      0x01},   /* BitBlt Control Register 1*/
-        {S1DREG_BBLT_CC_EXP,            0x00},   /* BitBlt ROP Code/Color Expansion Register*/
-        {S1DREG_BBLT_OP,                        0x00},   /* BitBlt Operation Register*/
-        {S1DREG_BBLT_SRC_START0,        0x00},   /* BitBlt Source Start Address Register 0*/
-        {S1DREG_BBLT_SRC_START1,        0x00},   /* BitBlt Source Start Address Register 1*/
-        {S1DREG_BBLT_SRC_START2,        0x00},   /* BitBlt Source Start Address Register 2*/
-        {S1DREG_BBLT_DST_START0,        0x00},   /* BitBlt Destination Start Address Register 0*/
-        {S1DREG_BBLT_DST_START1,        0x00},   /* BitBlt Destination Start Address Register 1*/
-        {S1DREG_BBLT_DST_START2,        0x00},   /* BitBlt Destination Start Address Register 2*/
-        {S1DREG_BBLT_MEM_OFF0,          0x00},   /* BitBlt Memory Address Offset Register 0*/
-        {S1DREG_BBLT_MEM_OFF1,          0x00},   /* BitBlt Memory Address Offset Register 1*/
-        {S1DREG_BBLT_WIDTH0,            0x00},   /* BitBlt Width Register 0*/
-        {S1DREG_BBLT_WIDTH1,            0x00},   /* BitBlt Width Register 1*/
-        {S1DREG_BBLT_HEIGHT0,           0x00},   /* BitBlt Height Register 0*/
-        {S1DREG_BBLT_HEIGHT1,           0x00},   /* BitBlt Height Register 1*/
-        {S1DREG_BBLT_BGC0,                      0x00},   /* BitBlt Background Color Register 0*/
-        {S1DREG_BBLT_BGC1,                      0x00},   /* BitBlt Background Color Register 1*/
-        {S1DREG_BBLT_FGC0,                      0x00},   /* BitBlt Foreground Color Register 0*/
-        {S1DREG_BBLT_FGC1,                      0x00},   /* BitBlt Foreground Color Register 1*/
-        {S1DREG_LKUP_MODE,                      0x00},   /* Look-Up Table Mode Register*/
-        {S1DREG_LKUP_ADDR,                      0x00},   /* Look-Up Table Address Register*/
-        {S1DREG_PS_CNF,                         0x00},   /* Power Save Configuration Register*/
-        {S1DREG_PS_STATUS,                      0x00},   /* Power Save Status Register*/
-        {S1DREG_CPU2MEM_WDOGT,          0x00},   /* CPU-to-Memory Access Watchdog Timer Register*/
-        {S1DREG_COM_DISP_MODE,          0x01},   /* Display Mode Register, LCD only*/
+        {S1DREG_MISC,                   0x00},  /* Miscellaneous Register*/
+        {S1DREG_COM_DISP_MODE,          0x01},  /* Display Mode Register, LCD only*/
+        {S1DREG_GPIO_CNF0,              0x00},  /* General IO Pins Configuration Register*/
+        {S1DREG_GPIO_CTL0,              0x00},  /* General IO Pins Control Register*/
+        {S1DREG_CLK_CNF,                0x11},  /* Memory Clock Configuration Register*/
+        {S1DREG_LCD_CLK_CNF,            0x10},  /* LCD Pixel Clock Configuration Register*/
+        {S1DREG_CRT_CLK_CNF,            0x12},  /* CRT/TV Pixel Clock Configuration Register*/
+        {S1DREG_MPLUG_CLK_CNF,          0x01},  /* MediaPlug Clock Configuration Register*/
+        {S1DREG_CPU2MEM_WST_SEL,        0x02},  /* CPU To Memory Wait State Select Register*/
+        {S1DREG_MEM_CNF,                0x00},  /* Memory Configuration Register*/
+        {S1DREG_SDRAM_REF_RATE,         0x04},  /* DRAM Refresh Rate Register, MCLK source*/
+        {S1DREG_SDRAM_TC0,              0x12},  /* DRAM Timings Control Register 0*/
+        {S1DREG_SDRAM_TC1,              0x02},  /* DRAM Timings Control Register 1*/
+        {S1DREG_PANEL_TYPE,             0x25},  /* Panel Type Register*/
+        {S1DREG_MOD_RATE,               0x00},  /* MOD Rate Register*/
+        {S1DREG_LCD_DISP_HWIDTH,        0x4F},  /* LCD Horizontal Display Width Register*/
+        {S1DREG_LCD_NDISP_HPER,         0x13},  /* LCD Horizontal Non-Display Period Register*/
+        {S1DREG_TFT_FPLINE_START,       0x01},  /* TFT FPLINE Start Position Register*/
+        {S1DREG_TFT_FPLINE_PWIDTH,      0x0c},  /* TFT FPLINE Pulse Width Register*/
+        {S1DREG_LCD_DISP_VHEIGHT0,      0xDF},  /* LCD Vertical Display Height Register 0*/
+        {S1DREG_LCD_DISP_VHEIGHT1,      0x01},  /* LCD Vertical Display Height Register 1*/
+        {S1DREG_LCD_NDISP_VPER,         0x2c},  /* LCD Vertical Non-Display Period Register*/
+        {S1DREG_TFT_FPFRAME_START,      0x0a},  /* TFT FPFRAME Start Position Register*/
+        {S1DREG_TFT_FPFRAME_PWIDTH,     0x02},  /* TFT FPFRAME Pulse Width Register*/
+        {S1DREG_LCD_DISP_MODE,          0x05},  /* LCD Display Mode Register*/
+        {S1DREG_LCD_MISC,               0x01},  /* LCD Miscellaneous Register*/
+        {S1DREG_LCD_DISP_START0,        0x00},  /* LCD Display Start Address Register 0*/
+        {S1DREG_LCD_DISP_START1,        0x00},  /* LCD Display Start Address Register 1*/
+        {S1DREG_LCD_DISP_START2,        0x00},  /* LCD Display Start Address Register 2*/
+        {S1DREG_LCD_MEM_OFF0,           0x80},  /* LCD Memory Address Offset Register 0*/
+        {S1DREG_LCD_MEM_OFF1,           0x02},  /* LCD Memory Address Offset Register 1*/
+        {S1DREG_LCD_PIX_PAN,            0x03},  /* LCD Pixel Panning Register*/
+        {S1DREG_LCD_DISP_FIFO_HTC,      0x00},  /* LCD Display FIFO High Threshold Control Register*/
+        {S1DREG_LCD_DISP_FIFO_LTC,      0x00},  /* LCD Display FIFO Low Threshold Control Register*/
+        {S1DREG_CRT_DISP_HWIDTH,        0x4F},  /* CRT/TV Horizontal Display Width Register*/
+        {S1DREG_CRT_NDISP_HPER,         0x13},  /* CRT/TV Horizontal Non-Display Period Register*/
+        {S1DREG_CRT_HRTC_START,         0x01},  /* CRT/TV HRTC Start Position Register*/
+        {S1DREG_CRT_HRTC_PWIDTH,        0x0B},  /* CRT/TV HRTC Pulse Width Register*/
+        {S1DREG_CRT_DISP_VHEIGHT0,      0xDF},  /* CRT/TV Vertical Display Height Register 0*/
+        {S1DREG_CRT_DISP_VHEIGHT1,      0x01},  /* CRT/TV Vertical Display Height Register 1*/
+        {S1DREG_CRT_NDISP_VPER,         0x2B},  /* CRT/TV Vertical Non-Display Period Register*/
+        {S1DREG_CRT_VRTC_START,         0x09},  /* CRT/TV VRTC Start Position Register*/
+        {S1DREG_CRT_VRTC_PWIDTH,        0x01},  /* CRT/TV VRTC Pulse Width Register*/
+        {S1DREG_TV_OUT_CTL,             0x18},  /* TV Output Control Register */
+        {S1DREG_CRT_DISP_MODE,          0x05},  /* CRT/TV Display Mode Register, 16BPP*/
+        {S1DREG_CRT_DISP_START0,        0x00},  /* CRT/TV Display Start Address Register 0*/
+        {S1DREG_CRT_DISP_START1,        0x00},  /* CRT/TV Display Start Address Register 1*/
+        {S1DREG_CRT_DISP_START2,        0x00},  /* CRT/TV Display Start Address Register 2*/
+        {S1DREG_CRT_MEM_OFF0,           0x80},  /* CRT/TV Memory Address Offset Register 0*/
+        {S1DREG_CRT_MEM_OFF1,           0x02},  /* CRT/TV Memory Address Offset Register 1*/
+        {S1DREG_CRT_PIX_PAN,            0x00},  /* CRT/TV Pixel Panning Register*/
+        {S1DREG_CRT_DISP_FIFO_HTC,      0x00},  /* CRT/TV Display FIFO High Threshold Control Register*/
+        {S1DREG_CRT_DISP_FIFO_LTC,      0x00},  /* CRT/TV Display FIFO Low Threshold Control Register*/
+        {S1DREG_LCD_CUR_CTL,            0x00},  /* LCD Ink/Cursor Control Register*/
+        {S1DREG_LCD_CUR_START,          0x01},  /* LCD Ink/Cursor Start Address Register*/
+        {S1DREG_LCD_CUR_XPOS0,          0x00},  /* LCD Cursor X Position Register 0*/
+        {S1DREG_LCD_CUR_XPOS1,          0x00},  /* LCD Cursor X Position Register 1*/
+        {S1DREG_LCD_CUR_YPOS0,          0x00},  /* LCD Cursor Y Position Register 0*/
+        {S1DREG_LCD_CUR_YPOS1,          0x00},  /* LCD Cursor Y Position Register 1*/
+        {S1DREG_LCD_CUR_BCTL0,          0x00},  /* LCD Ink/Cursor Blue Color 0 Register*/
+        {S1DREG_LCD_CUR_GCTL0,          0x00},  /* LCD Ink/Cursor Green Color 0 Register*/
+        {S1DREG_LCD_CUR_RCTL0,          0x00},  /* LCD Ink/Cursor Red Color 0 Register*/
+        {S1DREG_LCD_CUR_BCTL1,          0x1F},  /* LCD Ink/Cursor Blue Color 1 Register*/
+        {S1DREG_LCD_CUR_GCTL1,          0x3F},  /* LCD Ink/Cursor Green Color 1 Register*/
+        {S1DREG_LCD_CUR_RCTL1,          0x1F},  /* LCD Ink/Cursor Red Color 1 Register*/
+        {S1DREG_LCD_CUR_FIFO_HTC,       0x00},  /* LCD Ink/Cursor FIFO Threshold Register*/
+        {S1DREG_CRT_CUR_CTL,            0x00},  /* CRT/TV Ink/Cursor Control Register*/
+        {S1DREG_CRT_CUR_START,          0x01},  /* CRT/TV Ink/Cursor Start Address Register*/
+        {S1DREG_CRT_CUR_XPOS0,          0x00},  /* CRT/TV Cursor X Position Register 0*/
+        {S1DREG_CRT_CUR_XPOS1,          0x00},  /* CRT/TV Cursor X Position Register 1*/
+        {S1DREG_CRT_CUR_YPOS0,          0x00},  /* CRT/TV Cursor Y Position Register 0*/
+        {S1DREG_CRT_CUR_YPOS1,          0x00},  /* CRT/TV Cursor Y Position Register 1*/
+        {S1DREG_CRT_CUR_BCTL0,          0x00},  /* CRT/TV Ink/Cursor Blue Color 0 Register*/
+        {S1DREG_CRT_CUR_GCTL0,          0x00},  /* CRT/TV Ink/Cursor Green Color 0 Register*/
+        {S1DREG_CRT_CUR_RCTL0,          0x00},  /* CRT/TV Ink/Cursor Red Color 0 Register*/
+        {S1DREG_CRT_CUR_BCTL1,          0x1F},  /* CRT/TV Ink/Cursor Blue Color 1 Register*/
+        {S1DREG_CRT_CUR_GCTL1,          0x3F},  /* CRT/TV Ink/Cursor Green Color 1 Register*/
+        {S1DREG_CRT_CUR_RCTL1,          0x1F},  /* CRT/TV Ink/Cursor Red Color 1 Register*/
+        {S1DREG_CRT_CUR_FIFO_HTC,       0x00},  /* CRT/TV Ink/Cursor FIFO Threshold Register*/
+        {S1DREG_BBLT_CTL0,              0x00},  /* BitBlt Control Register 0*/
+        {S1DREG_BBLT_CTL1,              0x01},  /* BitBlt Control Register 1*/
+        {S1DREG_BBLT_CC_EXP,            0x00},  /* BitBlt ROP Code/Color Expansion Register*/
+        {S1DREG_BBLT_OP,                0x00},  /* BitBlt Operation Register*/
+        {S1DREG_BBLT_SRC_START0,        0x00},  /* BitBlt Source Start Address Register 0*/
+        {S1DREG_BBLT_SRC_START1,        0x00},  /* BitBlt Source Start Address Register 1*/
+        {S1DREG_BBLT_SRC_START2,        0x00},  /* BitBlt Source Start Address Register 2*/
+        {S1DREG_BBLT_DST_START0,        0x00},  /* BitBlt Destination Start Address Register 0*/
+        {S1DREG_BBLT_DST_START1,        0x00},  /* BitBlt Destination Start Address Register 1*/
+        {S1DREG_BBLT_DST_START2,        0x00},  /* BitBlt Destination Start Address Register 2*/
+        {S1DREG_BBLT_MEM_OFF0,          0x00},  /* BitBlt Memory Address Offset Register 0*/
+        {S1DREG_BBLT_MEM_OFF1,          0x00},  /* BitBlt Memory Address Offset Register 1*/
+        {S1DREG_BBLT_WIDTH0,            0x00},  /* BitBlt Width Register 0*/
+        {S1DREG_BBLT_WIDTH1,            0x00},  /* BitBlt Width Register 1*/
+        {S1DREG_BBLT_HEIGHT0,           0x00},  /* BitBlt Height Register 0*/
+        {S1DREG_BBLT_HEIGHT1,           0x00},  /* BitBlt Height Register 1*/
+        {S1DREG_BBLT_BGC0,              0x00},  /* BitBlt Background Color Register 0*/
+        {S1DREG_BBLT_BGC1,              0x00},  /* BitBlt Background Color Register 1*/
+        {S1DREG_BBLT_FGC0,              0x00},  /* BitBlt Foreground Color Register 0*/
+        {S1DREG_BBLT_FGC1,              0x00},  /* BitBlt Foreground Color Register 1*/
+        {S1DREG_LKUP_MODE,              0x00},  /* Look-Up Table Mode Register*/
+        {S1DREG_LKUP_ADDR,              0x00},  /* Look-Up Table Address Register*/
+        {S1DREG_PS_CNF,                 0x00},  /* Power Save Configuration Register*/
+        {S1DREG_PS_STATUS,              0x00},  /* Power Save Status Register*/
+        {S1DREG_CPU2MEM_WDOGT,          0x00},  /* CPU-to-Memory Access Watchdog Timer Register*/
+        {S1DREG_COM_DISP_MODE,          0x01},  /* Display Mode Register, LCD only*/
 };
 
-static u64 s1dfb_dmamask = 0xffffffffUL;
+static u64 s1dfb_dmamask = DMA_BIT_MASK(32);
 
-static struct s1d13xxxfb_pdata yl_9200_s1dfb_pdata = {
-                .initregs                               = yl_9200_s1dfb_initregs,
-                .initregssize                   = ARRAY_SIZE(yl_9200_s1dfb_initregs),
-                .platform_init_video    = yl_9200_init_video,
+static struct s1d13xxxfb_pdata yl9200_s1dfb_pdata = {
+        .initregs               = yl9200_s1dfb_initregs,
+        .initregssize           = ARRAY_SIZE(yl9200_s1dfb_initregs),
+        .platform_init_video    = yl9200_init_video,
 };
 
-static struct resource yl_9200_s1dfb_resource[] = {
+static struct resource yl9200_s1dfb_resource[] = {
         [0] = { /* video mem */
-                .name   = "s1d13xxxfb memory",
-        /*      .name   = "s1d13806 memory",*/
-                .start  = AT91_FB_VMEM_BASE,
-                .end    = AT91_FB_VMEM_BASE + AT91_FB_VMEM_SIZE -1,
-                .flags  = IORESOURCE_MEM,
+                .name   = "s1d13xxxfb memory",
+                .start  = AT91_FB_VMEM_BASE,
+                .end    = AT91_FB_VMEM_BASE + AT91_FB_VMEM_SIZE -1,
+                .flags  = IORESOURCE_MEM,
         },
         [1] = { /* video registers */
-                .name   = "s1d13xxxfb registers",
-        /*      .name   = "s1d13806 registers",*/
-                .start  = AT91_FB_REG_BASE,
-                .end    = AT91_FB_REG_BASE + AT91_FB_REG_SIZE -1,
-                .flags  = IORESOURCE_MEM,
+                .name   = "s1d13xxxfb registers",
+                .start  = AT91_FB_REG_BASE,
+                .end    = AT91_FB_REG_BASE + AT91_FB_REG_SIZE -1,
+                .flags  = IORESOURCE_MEM,
         },
 };
 
-static struct platform_device yl_9200_s1dfb_device = {
-        /*TODO S.Birtles , really we need the chip revision in here as well*/
-                .name           = "s1d13806fb",
-        /*  .name               = "s1d13506fb",*/
-                .id                     = -1,
-                .dev            = {
-        /*TODO theres a waring here!!*/
-        /*WARNING: vmlinux.o(.data+0x2dbc): Section mismatch: reference to .init.text: (between 'yl_9200_s1dfb_pdata' and 's1dfb_dmamask')*/
+static struct platform_device yl9200_s1dfb_device = {
+        .name           = "s1d13806fb",
+        .id             = -1,
+        .dev    = {
                 .dma_mask               = &s1dfb_dmamask,
-                .coherent_dma_mask      = 0xffffffff,
-                .platform_data          = &yl_9200_s1dfb_pdata,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                .platform_data          = &yl9200_s1dfb_pdata,
         },
-        .resource       = yl_9200_s1dfb_resource,
-        .num_resources  = ARRAY_SIZE(yl_9200_s1dfb_resource),
+        .resource       = yl9200_s1dfb_resource,
+        .num_resources  = ARRAY_SIZE(yl9200_s1dfb_resource),
 };
 
-void __init yl_9200_add_device_video(void)
+void __init yl9200_add_device_video(void)
 {
-        platform_device_register(&yl_9200_s1dfb_device);
+        platform_device_register(&yl9200_s1dfb_device);
 }
 #else
-        void __init yl_9200_add_device_video(void) {}
+void __init yl9200_add_device_video(void) {}
 #endif
 
-/*this is not called first , yl_9200_map_io is called first*/
-static void __init yl_9200_board_init(void)
+
+static void __init yl9200_board_init(void)
 {
         /* Serial */
         at91_add_device_serial();
         /* Ethernet */
-        at91_add_device_eth(&yl_9200_eth_data);
+        at91_add_device_eth(&yl9200_eth_data);
         /* USB Host */
-        at91_add_device_usbh(&yl_9200_usbh_data);
+        at91_add_device_usbh(&yl9200_usbh_data);
         /* USB Device */
-        at91_add_device_udc(&yl_9200_udc_data);
-        /* pullup_pin it is  actually active low, but this is not needed, driver sets it up */
-        /*at91_set_multi_drive(yl_9200_udc_data.pullup_pin, 0);*/
-
-        /* Compact Flash */
-        /*at91_add_device_cf(&yl_9200_cf_data);*/
-
+        at91_add_device_udc(&yl9200_udc_data);
         /* I2C */
-        at91_add_device_i2c(yl_9200_i2c_devices, ARRAY_SIZE(yl_9200_i2c_devices));
-        /* SPI */
-        /*TODO YL9200 we have 2 spi interfaces touch screen & CAN*/
-        /* AT91_PIN_PA5, AT91_PIN_PA6 , are used on the  max 485 NOT SPI*/
-
-        /*touch screen and CAN*/
-        at91_add_device_spi(yl_9200_spi_devices, ARRAY_SIZE(yl_9200_spi_devices));
-
-        /*Basically the  TS uses  PB11 & PB10 , PB11 is configured by the SPI system BP10 IS NOT USED!!*/
-        /* we need this incase the board is running without a touch screen*/
-        #if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
-        at91_init_device_ts(); /*init the touch screen device*/
-        #endif
-        /* DataFlash card */
-        at91_add_device_mmc(0, &yl_9200_mmc_data);
+        at91_add_device_i2c(yl9200_i2c_devices, ARRAY_SIZE(yl9200_i2c_devices));
+        /* MMC */
+        at91_add_device_mmc(0, &yl9200_mmc_data);
         /* NAND */
-        at91_add_device_nand(&yl_9200_nand_data);
+        at91_add_device_nand(&yl9200_nand_data);
         /* NOR Flash */
-        platform_device_register(&yl_9200_flash);
-        /* LEDs. Note!! this does not include the led's we passed for the processor status */
-        at91_gpio_leds(yl_9200_leds, ARRAY_SIZE(yl_9200_leds));
-        /* VGA  */
-        /*this is self registered by including the s1d13xxx chip in the kernel build*/
-        yl_9200_add_device_video();
+        platform_device_register(&yl9200_flash);
+#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
+        /* SPI */
+        at91_add_device_spi(yl9200_spi_devices, ARRAY_SIZE(yl9200_spi_devices));
+        /* Touchscreen */
+        yl9200_add_device_ts();
+#endif
+        /* LEDs. */
+        at91_gpio_leds(yl9200_leds, ARRAY_SIZE(yl9200_leds));
         /* Push Buttons */
-        yl_9200_add_device_buttons();
-        /*TODO fixup the Sounder */
-//      yl_9200_add_device_sounder(yl_9200_sounder,ARRAY_SIZE(yl_9200_sounder));
-
+        yl9200_add_device_buttons();
+        /* VGA */
+        yl9200_add_device_video();
 }
 
 MACHINE_START(YL9200, "uCdragon YL-9200")
-        /* Maintainer: S.Birtles*/
-        .phys_io                = AT91_BASE_SYS,
+        /* Maintainer: S.Birtles */
+        .phys_io        = AT91_BASE_SYS,
         .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
         .boot_params    = AT91_SDRAM_BASE + 0x100,
-        .timer                  = &at91rm9200_timer,
-        .map_io                 = yl_9200_map_io,
-        .init_irq               = yl_9200_init_irq,
-        .init_machine   = yl_9200_board_init,
+        .timer          = &at91rm9200_timer,
+        .map_io         = yl9200_map_io,
+        .init_irq       = yl9200_init_irq,
+        .init_machine   = yl9200_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index a33dfe450726..464bdbbf74df 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -112,12 +112,34 @@ static void pmc_sys_mode(struct clk *clk, int is_on)
                 at91_sys_write(AT91_PMC_SCDR, clk->pmc_mask);
 }
 
+static void pmc_uckr_mode(struct clk *clk, int is_on)
+{
+        unsigned int uckr = at91_sys_read(AT91_CKGR_UCKR);
+
+        if (is_on) {
+                is_on = AT91_PMC_LOCKU;
+                at91_sys_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
+        } else
+                at91_sys_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask));
+
+        do {
+                cpu_relax();
+        } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on);
+}
+
 /* USB function clocks (PLLB must be 48 MHz) */
 static struct clk udpck = {
         .name           = "udpck",
         .parent         = &pllb,
         .mode           = pmc_sys_mode,
 };
+static struct clk utmi_clk = {
+        .name           = "utmi_clk",
+        .parent         = &main_clk,
+        .pmc_mask       = AT91_PMC_UPLLEN,      /* in CKGR_UCKR */
+        .mode           = pmc_uckr_mode,
+        .type           = CLK_TYPE_PLL,
+};
 static struct clk uhpck = {
         .name           = "uhpck",
         .parent         = &pllb,
@@ -361,7 +383,7 @@ static void __init init_programmable_clock(struct clk *clk)
 
 static int at91_clk_show(struct seq_file *s, void *unused)
 {
-        u32             scsr, pcsr, sr;
+        u32             scsr, pcsr, uckr = 0, sr;
         struct clk      *clk;
 
         seq_printf(s, "SCSR = %8x\n", scsr = at91_sys_read(AT91_PMC_SCSR));
@@ -369,7 +391,10 @@ static int at91_clk_show(struct seq_file *s, void *unused)
         seq_printf(s, "MOR  = %8x\n", at91_sys_read(AT91_CKGR_MOR));
         seq_printf(s, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR));
         seq_printf(s, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR));
-        seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR));
+        if (!cpu_is_at91sam9rl())
+                seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR));
+        if (cpu_is_at91cap9() || cpu_is_at91sam9rl())
+                seq_printf(s, "UCKR = %8x\n", uckr = at91_sys_read(AT91_CKGR_UCKR));
         seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR));
         seq_printf(s, "SR   = %8x\n", sr = at91_sys_read(AT91_PMC_SR));
 
@@ -382,6 +407,8 @@ static int at91_clk_show(struct seq_file *s, void *unused)
                         state = (scsr & clk->pmc_mask) ? "on" : "off";
                 else if (clk->mode == pmc_periph_mode)
                         state = (pcsr & clk->pmc_mask) ? "on" : "off";
+                else if (clk->mode == pmc_uckr_mode)
+                        state = (uckr & clk->pmc_mask) ? "on" : "off";
                 else if (clk->pmc_mask)
                         state = (sr & clk->pmc_mask) ? "on" : "off";
                 else if (clk == &clk32k || clk == &main_clk)
@@ -488,14 +515,19 @@ static unsigned __init at91_pll_calc(unsigned main_freq, unsigned out_freq)
                 /*
                  * PLL input between 1MHz and 32MHz per spec, but lower
                  * frequences seem necessary in some cases so allow 100K.
+                 * Warning: some newer products need 2MHz min.
                  */
                 input = main_freq / i;
+                if (cpu_is_at91sam9g20() && input < 2000000)
+                        continue;
                 if (input < 100000)
                         continue;
                 if (input > 32000000)
                         continue;
 
                 mul1 = out_freq / input;
+                if (cpu_is_at91sam9g20() && mul > 63)
+                        continue;
                 if (mul1 > 2048)
                         continue;
                 if (mul1 < 2)
@@ -555,7 +587,8 @@ int __init at91_clock_init(unsigned long main_clock)
 
         /* report if PLLA is more than mildly overclocked */
         plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
-        if (plla.rate_hz > 209000000)
+        if ((!cpu_is_at91sam9g20() && plla.rate_hz > 209000000)
+           || (cpu_is_at91sam9g20() && plla.rate_hz > 800000000))
                 pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
 
         /*
@@ -570,7 +603,7 @@ int __init at91_clock_init(unsigned long main_clock)
                 uhpck.pmc_mask = AT91RM9200_PMC_UHP;
                 udpck.pmc_mask = AT91RM9200_PMC_UDP;
                 at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
-        } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263()) {
+        } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263() || cpu_is_at91sam9g20()) {
                 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
                 udpck.pmc_mask = AT91SAM926x_PMC_UDP;
         } else if (cpu_is_at91cap9()) {
@@ -582,6 +615,17 @@ int __init at91_clock_init(unsigned long main_clock)
         uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
 
         /*
+         * USB HS clock init
+         */
+        if (cpu_is_at91cap9() || cpu_is_at91sam9rl()) {
+                /*
+                 * multiplier is hard-wired to 40
+                 * (obtain the USB High Speed 480 MHz when input is 12 MHz)
+                 */
+                utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz;
+        }
+
+        /*
          * MCK and CPU derive from one of those primary clocks.
          * For now, assume this parentage won't change.
          */
@@ -591,13 +635,21 @@ int __init at91_clock_init(unsigned long main_clock)
         freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2));                           /* prescale */
         if (cpu_is_at91rm9200())
                 mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8));       /* mdiv */
-        else
-                mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));      /* mdiv */
+        else if (cpu_is_at91sam9g20()) {
+                mck.rate_hz = (mckr & AT91_PMC_MDIV) ?
+                        freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq;    /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
+                if (mckr & AT91_PMC_PDIV)
+                        freq /= 2;              /* processor clock division */
+        } else
+                mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));      /* mdiv */
 
         /* Register the PMC's standard clocks */
         for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
                 list_add_tail(&standard_pmc_clocks[i]->node, &clocks);
 
+        if (cpu_is_at91cap9() || cpu_is_at91sam9rl())
+                list_add_tail(&utmi_clk.node, &clocks);
+
         /* MCK and CPU clock are "always on" */
         clk_enable(&mck);
 
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index aa863c157708..8ab4feb1ec5b 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -202,7 +202,7 @@ static int at91_pm_verify_clocks(void)
                         pr_debug("AT91: PM - Suspend-to-RAM with USB still active\n");
                         return 0;
                 }
-        } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263()) {
+        } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263() || cpu_is_at91sam9g20()) {
                 if ((scsr & (AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP)) != 0) {
                         pr_debug("AT91: PM - Suspend-to-RAM with USB still active\n");
                         return 0;
diff --git a/arch/arm/mach-ep93xx/clock.c b/arch/arm/mach-ep93xx/clock.c
index 9d7515c36bff..f62c35500bb7 100644
--- a/arch/arm/mach-ep93xx/clock.c
+++ b/arch/arm/mach-ep93xx/clock.c
@@ -74,6 +74,7 @@ struct clk *clk_get(struct device *dev, const char *id)
 
         return ERR_PTR(-ENOENT);
 }
+EXPORT_SYMBOL(clk_get);
 
 int clk_enable(struct clk *clk)
 {
@@ -86,6 +87,7 @@ int clk_enable(struct clk *clk)
 
         return 0;
 }
+EXPORT_SYMBOL(clk_enable);
 
 void clk_disable(struct clk *clk)
 {
@@ -96,15 +98,18 @@ void clk_disable(struct clk *clk)
                 __raw_writel(value & ~clk->enable_mask, clk->enable_reg);
         }
 }
+EXPORT_SYMBOL(clk_disable);
 
 unsigned long clk_get_rate(struct clk *clk)
 {
         return clk->rate;
 }
+EXPORT_SYMBOL(clk_get_rate);
 
 void clk_put(struct clk *clk)
 {
 }
+EXPORT_SYMBOL(clk_put);
 
 
 
diff --git a/arch/arm/mach-footbridge/Makefile b/arch/arm/mach-footbridge/Makefile
index 0694ad6b6476..32f8609e4f85 100644
--- a/arch/arm/mach-footbridge/Makefile
+++ b/arch/arm/mach-footbridge/Makefile
@@ -14,12 +14,10 @@ pci-$(CONFIG_ARCH_EBSA285_HOST) += ebsa285-pci.o
 pci-$(CONFIG_ARCH_NETWINDER) += netwinder-pci.o
 pci-$(CONFIG_ARCH_PERSONAL_SERVER) += personal-pci.o
 
-leds-$(CONFIG_ARCH_CO285) += ebsa285-leds.o
 leds-$(CONFIG_ARCH_EBSA285) += ebsa285-leds.o
 leds-$(CONFIG_ARCH_NETWINDER) += netwinder-leds.o
 
 obj-$(CONFIG_ARCH_CATS) += cats-hw.o isa-timer.o
-obj-$(CONFIG_ARCH_CO285) += co285.o dc21285-timer.o
 obj-$(CONFIG_ARCH_EBSA285) += ebsa285.o dc21285-timer.o
 obj-$(CONFIG_ARCH_NETWINDER) += netwinder-hw.o isa-timer.o
 obj-$(CONFIG_ARCH_PERSONAL_SERVER) += personal.o dc21285-timer.o
diff --git a/arch/arm/mach-footbridge/co285.c b/arch/arm/mach-footbridge/co285.c
deleted file mode 100644
index 4545576ad8d9..000000000000
--- a/arch/arm/mach-footbridge/co285.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * linux/arch/arm/mach-footbridge/co285.c
- *
- * CO285 machine fixup
- */
-#include <linux/init.h>
-
-#include <asm/hardware/dec21285.h>
-#include <asm/mach-types.h>
-
-#include <asm/mach/arch.h>
-
-#include "common.h"
-
-static void __init
-fixup_coebsa285(struct machine_desc *desc, struct tag *tags,
-                char **cmdline, struct meminfo *mi)
-{
-        extern unsigned long boot_memory_end;
-        extern char boot_command_line[];
-
-        mi->nr_banks      = 1;
-        mi->bank[0].start = PHYS_OFFSET;
-        mi->bank[0].size  = boot_memory_end;
-        mi->bank[0].node  = 0;
-
-        *cmdline = boot_command_line;
-}
-
-MACHINE_START(CO285, "co-EBSA285")
-        /* Maintainer: Mark van Doesburg */
-        .phys_io        = DC21285_ARMCSR_BASE,
-        .io_pg_offst    = ((0x7cf00000) >> 18) & 0xfffc,
-        .fixup          = fixup_coebsa285,
-        .map_io         = footbridge_map_io,
-        .init_irq       = footbridge_init_irq,
-        .timer          = &footbridge_timer,
-MACHINE_END
-
diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c
index ef29fc34ce65..b08ab507c052 100644
--- a/arch/arm/mach-footbridge/common.c
+++ b/arch/arm/mach-footbridge/common.c
@@ -177,25 +177,6 @@ static struct map_desc ebsa285_host_io_desc[] __initdata = {
 #endif
 };
 
-/*
- * The CO-ebsa285 mapping.
- */
-static struct map_desc co285_io_desc[] __initdata = {
-#ifdef CONFIG_ARCH_CO285
-        {
-                .virtual        = PCIO_BASE,
-                .pfn            = __phys_to_pfn(DC21285_PCI_IO),
-                .length         = PCIO_SIZE,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = PCIMEM_BASE,
-                .pfn            = __phys_to_pfn(DC21285_PCI_MEM),
-                .length         = PCIMEM_SIZE,
-                .type           = MT_DEVICE,
-        },
-#endif
-};
-
 void __init footbridge_map_io(void)
 {
         /*
@@ -208,8 +189,6 @@ void __init footbridge_map_io(void)
          * Now, work out what we've got to map in addition on this
          * platform.
          */
-        if (machine_is_co285())
-                iotable_init(co285_io_desc, ARRAY_SIZE(co285_io_desc));
         if (footbridge_cfn_mode())
                 iotable_init(ebsa285_host_io_desc, ARRAY_SIZE(ebsa285_host_io_desc));
 }
diff --git a/arch/arm/mach-footbridge/ebsa285-leds.c b/arch/arm/mach-footbridge/ebsa285-leds.c
index a64e22226515..09c1fbc51876 100644
--- a/arch/arm/mach-footbridge/ebsa285-leds.c
+++ b/arch/arm/mach-footbridge/ebsa285-leds.c
@@ -128,7 +128,7 @@ static void ebsa285_leds_event(led_event_t evt)
 
 static int __init leds_init(void)
 {
-        if (machine_is_ebsa285() || machine_is_co285())
+        if (machine_is_ebsa285())
                 leds_event = ebsa285_leds_event;
 
         leds_event(led_start);
diff --git a/arch/arm/mach-footbridge/time.c b/arch/arm/mach-footbridge/time.c
index 5d02e95dede3..d5cfcda385d6 100644
--- a/arch/arm/mach-footbridge/time.c
+++ b/arch/arm/mach-footbridge/time.c
@@ -115,8 +115,7 @@ static int set_isa_cmos_time(void)
 
 void __init isa_rtc_init(void)
 {
-        if (machine_is_co285() ||
-            machine_is_personal_server())
+        if (machine_is_personal_server())
                 /*
                  * Add-in 21285s shouldn't access the RTC
                  */
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 88d5e61a2e13..b047c7e795a9 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -4,7 +4,7 @@
 
 # Object file lists.
 
-obj-y                   += irq.o time.o dma.o generic.o
+obj-y                   += irq.o time.o dma.o generic.o clock.o
 
 obj-$(CONFIG_CPU_FREQ_IMX)      += cpufreq.o
 
diff --git a/arch/arm/mach-imx/clock.c b/arch/arm/mach-imx/clock.c
new file mode 100644
index 000000000000..6a90fe5578df
--- /dev/null
+++ b/arch/arm/mach-imx/clock.c
@@ -0,0 +1,205 @@
+/*
+ *  Copyright (C) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/list.h>
+#include <linux/math64.h>
+#include <linux/err.h>
+
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+
+/*
+ * Very simple approach: We can't disable clocks, so we do
+ * not need refcounting
+ */
+
+struct clk {
+        struct list_head node;
+        const char *name;
+        unsigned long (*get_rate)(void);
+};
+
+/*
+ *  get the system pll clock in Hz
+ *
+ *                  mfi + mfn / (mfd +1)
+ *  f = 2 * f_ref * --------------------
+ *                        pd + 1
+ */
+static unsigned long imx_decode_pll(unsigned int pll, u32 f_ref)
+{
+        unsigned long long ll;
+        unsigned long quot;
+
+        u32 mfi = (pll >> 10) & 0xf;
+        u32 mfn = pll & 0x3ff;
+        u32 mfd = (pll >> 16) & 0x3ff;
+        u32 pd =  (pll >> 26) & 0xf;
+
+        mfi = mfi <= 5 ? 5 : mfi;
+
+        ll = 2 * (unsigned long long)f_ref *
+                ((mfi << 16) + (mfn << 16) / (mfd + 1));
+        quot = (pd + 1) * (1 << 16);
+        ll += quot / 2;
+        do_div(ll, quot);
+        return (unsigned long)ll;
+}
+
+static unsigned long imx_get_system_clk(void)
+{
+        u32 f_ref = (CSCR & CSCR_SYSTEM_SEL) ? 16000000 : (CLK32 * 512);
+
+        return imx_decode_pll(SPCTL0, f_ref);
+}
+
+static unsigned long imx_get_mcu_clk(void)
+{
+        return imx_decode_pll(MPCTL0, CLK32 * 512);
+}
+
+/*
+ *  get peripheral clock 1 ( UART[12], Timer[12], PWM )
+ */
+static unsigned long imx_get_perclk1(void)
+{
+        return imx_get_system_clk() / (((PCDR) & 0xf)+1);
+}
+
+/*
+ *  get peripheral clock 2 ( LCD, SD, SPI[12] )
+ */
+static unsigned long imx_get_perclk2(void)
+{
+        return imx_get_system_clk() / (((PCDR>>4) & 0xf)+1);
+}
+
+/*
+ *  get peripheral clock 3 ( SSI )
+ */
+static unsigned long imx_get_perclk3(void)
+{
+        return imx_get_system_clk() / (((PCDR>>16) & 0x7f)+1);
+}
+
+/*
+ *  get hclk ( SDRAM, CSI, Memory Stick, I2C, DMA )
+ */
+static unsigned long imx_get_hclk(void)
+{
+        return imx_get_system_clk() / (((CSCR>>10) & 0xf)+1);
+}
+
+static struct clk clk_system_clk = {
+        .name = "system_clk",
+        .get_rate = imx_get_system_clk,
+};
+
+static struct clk clk_hclk = {
+        .name = "hclk",
+        .get_rate = imx_get_hclk,
+};
+
+static struct clk clk_mcu_clk = {
+        .name = "mcu_clk",
+        .get_rate = imx_get_mcu_clk,
+};
+
+static struct clk clk_perclk1 = {
+        .name = "perclk1",
+        .get_rate = imx_get_perclk1,
+};
+
+static struct clk clk_uart_clk = {
+        .name = "uart_clk",
+        .get_rate = imx_get_perclk1,
+};
+
+static struct clk clk_perclk2 = {
+        .name = "perclk2",
+        .get_rate = imx_get_perclk2,
+};
+
+static struct clk clk_perclk3 = {
+        .name = "perclk3",
+        .get_rate = imx_get_perclk3,
+};
+
+static struct clk *clks[] = {
+        &clk_perclk1,
+        &clk_perclk2,
+        &clk_perclk3,
+        &clk_system_clk,
+        &clk_hclk,
+        &clk_mcu_clk,
+        &clk_uart_clk,
+};
+
+static LIST_HEAD(clocks);
+static DEFINE_MUTEX(clocks_mutex);
+
+struct clk *clk_get(struct device *dev, const char *id)
+{
+        struct clk *p, *clk = ERR_PTR(-ENOENT);
+
+        mutex_lock(&clocks_mutex);
+        list_for_each_entry(p, &clocks, node) {
+                if (!strcmp(p->name, id)) {
+                        clk = p;
+                        goto found;
+                }
+        }
+
+found:
+        mutex_unlock(&clocks_mutex);
+
+        return clk;
+}
+
+void clk_put(struct clk *clk)
+{
+}
+
+int clk_enable(struct clk *clk)
+{
+        return 0;
+}
+
+void clk_disable(struct clk *clk)
+{
+}
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+        return clk->get_rate();
+}
+
+int imx_clocks_init(void)
+{
+        int i;
+
+        mutex_lock(&clocks_mutex);
+        for (i = 0; i < ARRAY_SIZE(clks); i++)
+                list_add(&clks[i]->node, &clocks);
+        mutex_unlock(&clocks_mutex);
+
+        return 0;
+}
+
diff --git a/arch/arm/mach-imx/cpufreq.c b/arch/arm/mach-imx/cpufreq.c
index e548ba74a4d2..be0809b33e08 100644
--- a/arch/arm/mach-imx/cpufreq.c
+++ b/arch/arm/mach-imx/cpufreq.c
@@ -32,6 +32,8 @@
 #include <linux/types.h>
 #include <linux/init.h>
 #include <linux/cpufreq.h>
+#include <linux/clk.h>
+#include <linux/err.h>
 #include <asm/system.h>
 
 #include <asm/hardware.h>
@@ -52,6 +54,8 @@
 static u32 mpctl0_at_boot;
 static u32 bclk_div_at_boot;
 
+static struct clk *system_clk, *mcu_clk;
+
 static void imx_set_async_mode(void)
 {
         adjust_cr(CR_920T_CLOCK_MODE, CR_920T_ASYNC_MODE);
@@ -160,10 +164,10 @@ static unsigned int imx_get_speed(unsigned int cpu)
         cr = get_cr();
 
         if((cr & CR_920T_CLOCK_MODE) == CR_920T_FASTBUS_MODE) {
-                freq = imx_get_system_clk();
+                freq = clk_get_rate(system_clk);
                 freq = (freq + bclk_div/2) / bclk_div;
         } else {
-                freq = imx_get_mcu_clk();
+                freq = clk_get_rate(mcu_clk);
                 if (cscr & CSCR_MPU_PRESC)
                         freq /= 2;
         }
@@ -201,7 +205,7 @@ static int imx_set_target(struct cpufreq_policy *policy,
         pr_debug(KERN_DEBUG "imx: requested frequency %ld Hz, mpctl0 at boot 0x%08x\n",
                         freq, mpctl0_at_boot);
 
-        sysclk = imx_get_system_clk();
+        sysclk = clk_get_rate(system_clk);
 
         if (freq > sysclk / bclk_div_at_boot + 1000000) {
                 freq = imx_compute_mpctl(&mpctl0, mpctl0_at_boot, CLK32 * 512, freq, relation);
@@ -290,6 +294,16 @@ static int __init imx_cpufreq_init(void)
         bclk_div_at_boot = __mfld2val(CSCR_BCLK_DIV, CSCR) + 1;
         mpctl0_at_boot = 0;
 
+        system_clk = clk_get(NULL, "system_clk");
+        if (IS_ERR(system_clk))
+                return PTR_ERR(system_clk);
+
+        mcu_clk = clk_get(NULL, "mcu_clk");
+        if (IS_ERR(mcu_clk)) {
+                clk_put(system_clk);
+                return PTR_ERR(mcu_clk);
+        }
+
         if((CSCR & CSCR_MPEN) &&
            ((get_cr() & CR_920T_CLOCK_MODE) != CR_920T_FASTBUS_MODE))
                 mpctl0_at_boot = MPCTL0;
diff --git a/arch/arm/mach-imx/dma.c b/arch/arm/mach-imx/dma.c
index a59ff2987cb7..ee1c6f06ff64 100644
--- a/arch/arm/mach-imx/dma.c
+++ b/arch/arm/mach-imx/dma.c
@@ -410,7 +410,6 @@ void imx_dma_free(imx_dmach_t dma_ch)
 
 /**
  * imx_dma_request_by_prio - find and request some of free channels best suiting requested priority
- * @dma_ch: i.MX DMA channel number
  * @name: the driver/caller own non-%NULL identification
  * @prio: one of the hardware distinguished priority level:
  *        %DMA_PRIO_HIGH, %DMA_PRIO_MEDIUM, %DMA_PRIO_LOW
@@ -420,11 +419,9 @@ void imx_dma_free(imx_dmach_t dma_ch)
  * in the higher and then even lower priority groups.
  *
  * Return value: If there is no free channel to allocate, -%ENODEV is returned.
- *               Zero value indicates successful channel allocation.
+ *               On successful allocation channel is returned.
  */
-int
-imx_dma_request_by_prio(imx_dmach_t * pdma_ch, const char *name,
-                        imx_dma_prio prio)
+imx_dmach_t imx_dma_request_by_prio(const char *name, imx_dma_prio prio)
 {
         int i;
         int best;
@@ -444,15 +441,13 @@ imx_dma_request_by_prio(imx_dmach_t * pdma_ch, const char *name,
 
         for (i = best; i < IMX_DMA_CHANNELS; i++) {
                 if (!imx_dma_request(i, name)) {
-                        *pdma_ch = i;
-                        return 0;
+                        return i;
                 }
         }
 
         for (i = best - 1; i >= 0; i--) {
                 if (!imx_dma_request(i, name)) {
-                        *pdma_ch = i;
-                        return 0;
+                        return i;
                 }
         }
 
diff --git a/arch/arm/mach-imx/generic.c b/arch/arm/mach-imx/generic.c
index 4cfc9d3af28a..98ddd8a6d05f 100644
--- a/arch/arm/mach-imx/generic.c
+++ b/arch/arm/mach-imx/generic.c
@@ -214,82 +214,6 @@ int imx_irq_to_gpio(unsigned irq)
 
 EXPORT_SYMBOL(imx_irq_to_gpio);
 
-/*
- *  get the system pll clock in Hz
- *
- *                  mfi + mfn / (mfd +1)
- *  f = 2 * f_ref * --------------------
- *                        pd + 1
- */
-static unsigned int imx_decode_pll(unsigned int pll, u32 f_ref)
-{
-        unsigned long long ll;
-        unsigned long quot;
-
-        u32 mfi = (pll >> 10) & 0xf;
-        u32 mfn = pll & 0x3ff;
-        u32 mfd = (pll >> 16) & 0x3ff;
-        u32 pd =  (pll >> 26) & 0xf;
-
-        mfi = mfi <= 5 ? 5 : mfi;
-
-        ll = 2 * (unsigned long long)f_ref * ( (mfi<<16) + (mfn<<16) / (mfd+1) );
-        quot = (pd+1) * (1<<16);
-        ll += quot / 2;
-        do_div(ll, quot);
-        return (unsigned int) ll;
-}
-
-unsigned int imx_get_system_clk(void)
-{
-        u32 f_ref = (CSCR & CSCR_SYSTEM_SEL) ? 16000000 : (CLK32 * 512);
-
-        return imx_decode_pll(SPCTL0, f_ref);
-}
-EXPORT_SYMBOL(imx_get_system_clk);
-
-unsigned int imx_get_mcu_clk(void)
-{
-        return imx_decode_pll(MPCTL0, CLK32 * 512);
-}
-EXPORT_SYMBOL(imx_get_mcu_clk);
-
-/*
- *  get peripheral clock 1 ( UART[12], Timer[12], PWM )
- */
-unsigned int imx_get_perclk1(void)
-{
-        return imx_get_system_clk() / (((PCDR) & 0xf)+1);
-}
-EXPORT_SYMBOL(imx_get_perclk1);
-
-/*
- *  get peripheral clock 2 ( LCD, SD, SPI[12] )
- */
-unsigned int imx_get_perclk2(void)
-{
-        return imx_get_system_clk() / (((PCDR>>4) & 0xf)+1);
-}
-EXPORT_SYMBOL(imx_get_perclk2);
-
-/*
- *  get peripheral clock 3 ( SSI )
- */
-unsigned int imx_get_perclk3(void)
-{
-        return imx_get_system_clk() / (((PCDR>>16) & 0x7f)+1);
-}
-EXPORT_SYMBOL(imx_get_perclk3);
-
-/*
- *  get hclk ( SDRAM, CSI, Memory Stick, I2C, DMA )
- */
-unsigned int imx_get_hclk(void)
-{
-        return imx_get_system_clk() / (((CSCR>>10) & 0xf)+1);
-}
-EXPORT_SYMBOL(imx_get_hclk);
-
 static struct resource imx_mmc_resources[] = {
         [0] = {
                 .start  = 0x00214000,
diff --git a/arch/arm/mach-imx/mx1ads.c b/arch/arm/mach-imx/mx1ads.c
index a9778c1587ab..9635d5812bcd 100644
--- a/arch/arm/mach-imx/mx1ads.c
+++ b/arch/arm/mach-imx/mx1ads.c
@@ -69,6 +69,11 @@ static struct resource imx_uart1_resources[] = {
                 .end    = (UART1_MINT_TX),
                 .flags  = IORESOURCE_IRQ,
         },
+        [3] = {
+                .start  = UART1_MINT_RTS,
+                .end    = UART1_MINT_RTS,
+                .flags  = IORESOURCE_IRQ,
+        },
 };
 
 static struct platform_device imx_uart1_device = {
@@ -97,6 +102,11 @@ static struct resource imx_uart2_resources[] = {
                 .end    = (UART2_MINT_TX),
                 .flags  = IORESOURCE_IRQ,
         },
+        [3] = {
+                .start  = UART2_MINT_RTS,
+                .end    = UART2_MINT_RTS,
+                .flags  = IORESOURCE_IRQ,
+        },
 };
 
 static struct platform_device imx_uart2_device = {
diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c
index d86d124aea22..5a41e96e8586 100644
--- a/arch/arm/mach-imx/time.c
+++ b/arch/arm/mach-imx/time.c
@@ -17,6 +17,7 @@
 #include <linux/time.h>
 #include <linux/clocksource.h>
 #include <linux/clockchips.h>
+#include <linux/clk.h>
 
 #include <asm/hardware.h>
 #include <asm/io.h>
@@ -86,10 +87,10 @@ static struct clocksource clocksource_imx = {
         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
-static int __init imx_clocksource_init(void)
+static int __init imx_clocksource_init(unsigned long rate)
 {
         clocksource_imx.mult =
-                clocksource_hz2mult(imx_get_perclk1(), clocksource_imx.shift);
+                clocksource_hz2mult(rate, clocksource_imx.shift);
         clocksource_register(&clocksource_imx);
 
         return 0;
@@ -174,9 +175,9 @@ static struct clock_event_device clockevent_imx = {
         .rating         = 200,
 };
 
-static int __init imx_clockevent_init(void)
+static int __init imx_clockevent_init(unsigned long rate)
 {
-        clockevent_imx.mult = div_sc(imx_get_perclk1(), NSEC_PER_SEC,
+        clockevent_imx.mult = div_sc(rate, NSEC_PER_SEC,
                                         clockevent_imx.shift);
         clockevent_imx.max_delta_ns =
                 clockevent_delta2ns(0xfffffffe, &clockevent_imx);
@@ -190,13 +191,23 @@ static int __init imx_clockevent_init(void)
         return 0;
 }
 
+extern int imx_clocks_init(void);
 
 static void __init imx_timer_init(void)
 {
+        struct clk *clk;
+        unsigned long rate;
+
+        imx_clocks_init();
+
+        clk = clk_get(NULL, "perclk1");
+        clk_enable(clk);
+        rate = clk_get_rate(clk);
+
         imx_timer_hardware_init();
-        imx_clocksource_init();
+        imx_clocksource_init(rate);
 
-        imx_clockevent_init();
+        imx_clockevent_init(rate);
 
         /*
          * Make irqs happen for the system timer
diff --git a/arch/arm/mach-integrator/Makefile b/arch/arm/mach-integrator/Makefile
index 158daaf9e3b0..6a5ef8d30b10 100644
--- a/arch/arm/mach-integrator/Makefile
+++ b/arch/arm/mach-integrator/Makefile
@@ -4,7 +4,7 @@
 
 # Object file lists.
 
-obj-y                                   := clock.o core.o lm.o time.o
+obj-y                                   := clock.o core.o lm.o
 obj-$(CONFIG_ARCH_INTEGRATOR_AP)        += integrator_ap.o
 obj-$(CONFIG_ARCH_INTEGRATOR_CP)        += integrator_cp.o
 
diff --git a/arch/arm/mach-integrator/time.c b/arch/arm/mach-integrator/time.c
deleted file mode 100644
index 8508a0db3eaf..000000000000
--- a/arch/arm/mach-integrator/time.c
+++ /dev/null
@@ -1,223 +0,0 @@
-/*
- *  linux/arch/arm/mach-integrator/time.c
- *
- *  Copyright (C) 2000-2001 Deep Blue Solutions Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/time.h>
-#include <linux/mc146818rtc.h>
-#include <linux/interrupt.h>
-#include <linux/init.h>
-#include <linux/device.h>
-#include <linux/amba/bus.h>
-
-#include <asm/hardware.h>
-#include <asm/io.h>
-#include <asm/uaccess.h>
-#include <asm/rtc.h>
-
-#include <asm/mach/time.h>
-
-#define RTC_DR          (0)
-#define RTC_MR          (4)
-#define RTC_STAT        (8)
-#define RTC_EOI         (8)
-#define RTC_LR          (12)
-#define RTC_CR          (16)
-#define RTC_CR_MIE      (1 << 0)
-
-extern int (*set_rtc)(void);
-static void __iomem *rtc_base;
-
-static int integrator_set_rtc(void)
-{
-        __raw_writel(xtime.tv_sec, rtc_base + RTC_LR);
-        return 1;
-}
-
-static int integrator_rtc_read_alarm(struct rtc_wkalrm *alrm)
-{
-        rtc_time_to_tm(readl(rtc_base + RTC_MR), &alrm->time);
-        return 0;
-}
-
-static inline int integrator_rtc_set_alarm(struct rtc_wkalrm *alrm)
-{
-        unsigned long time;
-        int ret;
-
-        /*
-         * At the moment, we can only deal with non-wildcarded alarm times.
-         */
-        ret = rtc_valid_tm(&alrm->time);
-        if (ret == 0)
-                ret = rtc_tm_to_time(&alrm->time, &time);
-        if (ret == 0)
-                writel(time, rtc_base + RTC_MR);
-        return ret;
-}
-
-static int integrator_rtc_read_time(struct rtc_time *tm)
-{
-        rtc_time_to_tm(readl(rtc_base + RTC_DR), tm);
-        return 0;
-}
-
-/*
- * Set the RTC time.  Unfortunately, we can't accurately set
- * the point at which the counter updates.
- *
- * Also, since RTC_LR is transferred to RTC_CR on next rising
- * edge of the 1Hz clock, we must write the time one second
- * in advance.
- */
-static inline int integrator_rtc_set_time(struct rtc_time *tm)
-{
-        unsigned long time;
-        int ret;
-
-        ret = rtc_tm_to_time(tm, &time);
-        if (ret == 0)
-                writel(time + 1, rtc_base + RTC_LR);
-
-        return ret;
-}
-
-static struct rtc_ops rtc_ops = {
-        .owner          = THIS_MODULE,
-        .read_time      = integrator_rtc_read_time,
-        .set_time       = integrator_rtc_set_time,
-        .read_alarm     = integrator_rtc_read_alarm,
-        .set_alarm      = integrator_rtc_set_alarm,
-};
-
-static irqreturn_t arm_rtc_interrupt(int irq, void *dev_id)
-{
-        writel(0, rtc_base + RTC_EOI);
-        return IRQ_HANDLED;
-}
-
-static int rtc_probe(struct amba_device *dev, void *id)
-{
-        int ret;
-
-        if (rtc_base)
-                return -EBUSY;
-
-        ret = amba_request_regions(dev, NULL);
-        if (ret)
-                goto out;
-
-        rtc_base = ioremap(dev->res.start, SZ_4K);
-        if (!rtc_base) {
-                ret = -ENOMEM;
-                goto res_out;
-        }
-
-        __raw_writel(0, rtc_base + RTC_CR);
-        __raw_writel(0, rtc_base + RTC_EOI);
-
-        xtime.tv_sec = __raw_readl(rtc_base + RTC_DR);
-
-        /* note that 'dev' is merely used for irq disambiguation;
-         * it is not actually referenced in the irq handler
-         */
-        ret = request_irq(dev->irq[0], arm_rtc_interrupt, IRQF_DISABLED,
-                          "rtc-pl030", dev);
-        if (ret)
-                goto map_out;
-
-        ret = register_rtc(&rtc_ops);
-        if (ret)
-                goto irq_out;
-
-        set_rtc = integrator_set_rtc;
-        return 0;
-
- irq_out:
-        free_irq(dev->irq[0], dev);
- map_out:
-        iounmap(rtc_base);
-        rtc_base = NULL;
- res_out:
-        amba_release_regions(dev);
- out:
-        return ret;
-}
-
-static int rtc_remove(struct amba_device *dev)
-{
-        set_rtc = NULL;
-
-        writel(0, rtc_base + RTC_CR);
-
-        free_irq(dev->irq[0], dev);
-        unregister_rtc(&rtc_ops);
-
-        iounmap(rtc_base);
-        rtc_base = NULL;
-        amba_release_regions(dev);
-
-        return 0;
-}
-
-static struct timespec rtc_delta;
-
-static int rtc_suspend(struct amba_device *dev, pm_message_t state)
-{
-        struct timespec rtc;
-
-        rtc.tv_sec = readl(rtc_base + RTC_DR);
-        rtc.tv_nsec = 0;
-        save_time_delta(&rtc_delta, &rtc);
-
-        return 0;
-}
-
-static int rtc_resume(struct amba_device *dev)
-{
-        struct timespec rtc;
-
-        rtc.tv_sec = readl(rtc_base + RTC_DR);
-        rtc.tv_nsec = 0;
-        restore_time_delta(&rtc_delta, &rtc);
-
-        return 0;
-}
-
-static struct amba_id rtc_ids[] = {
-        {
-                .id     = 0x00041030,
-                .mask   = 0x000fffff,
-        },
-        { 0, 0 },
-};
-
-static struct amba_driver rtc_driver = {
-        .drv            = {
-                .name   = "rtc-pl030",
-        },
-        .probe          = rtc_probe,
-        .remove         = rtc_remove,
-        .suspend        = rtc_suspend,
-        .resume         = rtc_resume,
-        .id_table       = rtc_ids,
-};
-
-static int __init integrator_rtc_init(void)
-{
-        return amba_driver_register(&rtc_driver);
-}
-
-static void __exit integrator_rtc_exit(void)
-{
-        amba_driver_unregister(&rtc_driver);
-}
-
-module_init(integrator_rtc_init);
-module_exit(integrator_rtc_exit);
diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig
index e774447c0592..db8b5fe06c0d 100644
--- a/arch/arm/mach-ixp4xx/Kconfig
+++ b/arch/arm/mach-ixp4xx/Kconfig
@@ -125,6 +125,15 @@ config	ARCH_IXDP4XX
         depends on ARCH_IXDP425 || MACH_IXDP465 || MACH_KIXRP435
         default y
 
+config MACH_FSG
+        bool
+        prompt "Freecom FSG-3"
+        select PCI
+        help
+          Say 'Y' here if you want your kernel to support Freecom's
+          FSG-3 device. For more information on this platform,
+          see http://www.nslu2-linux.org/wiki/FSG3/HomePage
+
 #
 # Certain registers and IRQs are only enabled if supporting IXP465 CPUs
 #
diff --git a/arch/arm/mach-ixp4xx/Makefile b/arch/arm/mach-ixp4xx/Makefile
index c1956882c48b..2e6bbf927a74 100644
--- a/arch/arm/mach-ixp4xx/Makefile
+++ b/arch/arm/mach-ixp4xx/Makefile
@@ -15,6 +15,7 @@ obj-pci-$(CONFIG_MACH_NAS100D)		+= nas100d-pci.o
 obj-pci-$(CONFIG_MACH_DSMG600)          += dsmg600-pci.o
 obj-pci-$(CONFIG_MACH_GATEWAY7001)      += gateway7001-pci.o
 obj-pci-$(CONFIG_MACH_WG302V2)          += wg302v2-pci.o
+obj-pci-$(CONFIG_MACH_FSG)              += fsg-pci.o
 
 obj-y   += common.o
 
@@ -28,6 +29,7 @@ obj-$(CONFIG_MACH_NAS100D)	+= nas100d-setup.o
 obj-$(CONFIG_MACH_DSMG600)      += dsmg600-setup.o
 obj-$(CONFIG_MACH_GATEWAY7001)  += gateway7001-setup.o
 obj-$(CONFIG_MACH_WG302V2)      += wg302v2-setup.o
+obj-$(CONFIG_MACH_FSG)          += fsg-setup.o
 
 obj-$(CONFIG_PCI)               += $(obj-pci-$(CONFIG_PCI)) common-pci.o
 obj-$(CONFIG_IXP4XX_QMGR)       += ixp4xx_qmgr.o
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index f6d66dce6852..3781b3db9f49 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -326,11 +326,11 @@ static struct resource ixp4xx_udc_resources[] = {
 };
 
 /*
- * USB device controller. The IXP4xx uses the same controller as PXA2XX,
+ * USB device controller. The IXP4xx uses the same controller as PXA25X,
  * so we just use the same device.
  */
 static struct platform_device ixp4xx_udc_device = {
-        .name           = "pxa2xx-udc",
+        .name           = "pxa25x-udc",
         .id             = -1,
         .num_resources  = 2,
         .resource       = ixp4xx_udc_resources,
diff --git a/arch/arm/mach-ixp4xx/fsg-pci.c b/arch/arm/mach-ixp4xx/fsg-pci.c
new file mode 100644
index 000000000000..f19f3f6feda1
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/fsg-pci.c
@@ -0,0 +1,71 @@
+/*
+ * arch/arch/mach-ixp4xx/fsg-pci.c
+ *
+ * FSG board-level PCI initialization
+ *
+ * Author: Rod Whitby <rod@whitby.id.au>
+ * Maintainer: http://www.nslu2-linux.org/
+ *
+ * based on ixdp425-pci.c:
+ *      Copyright (C) 2002 Intel Corporation.
+ *      Copyright (C) 2003-2004 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+
+#include <asm/mach/pci.h>
+#include <asm/mach-types.h>
+
+void __init fsg_pci_preinit(void)
+{
+        set_irq_type(IRQ_FSG_PCI_INTA, IRQT_LOW);
+        set_irq_type(IRQ_FSG_PCI_INTB, IRQT_LOW);
+        set_irq_type(IRQ_FSG_PCI_INTC, IRQT_LOW);
+
+        ixp4xx_pci_preinit();
+}
+
+static int __init fsg_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+        static int pci_irq_table[FSG_PCI_IRQ_LINES] = {
+                IRQ_FSG_PCI_INTC,
+                IRQ_FSG_PCI_INTB,
+                IRQ_FSG_PCI_INTA,
+        };
+
+        int irq = -1;
+        slot = slot - 11;
+
+        if (slot >= 1 && slot <= FSG_PCI_MAX_DEV &&
+            pin >= 1 && pin <= FSG_PCI_IRQ_LINES)
+                irq = pci_irq_table[(slot - 1)];
+        printk(KERN_INFO "%s: Mapped slot %d pin %d to IRQ %d\n",
+               __func__, slot, pin, irq);
+
+        return irq;
+}
+
+struct hw_pci fsg_pci __initdata = {
+        .nr_controllers = 1,
+        .preinit =        fsg_pci_preinit,
+        .swizzle =        pci_std_swizzle,
+        .setup =          ixp4xx_setup,
+        .scan =           ixp4xx_scan_bus,
+        .map_irq =        fsg_map_irq,
+};
+
+int __init fsg_pci_init(void)
+{
+        if (machine_is_fsg())
+                pci_common_init(&fsg_pci);
+        return 0;
+}
+
+subsys_initcall(fsg_pci_init);
diff --git a/arch/arm/mach-ixp4xx/fsg-setup.c b/arch/arm/mach-ixp4xx/fsg-setup.c
new file mode 100644
index 000000000000..0db3a909ae61
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/fsg-setup.c
@@ -0,0 +1,276 @@
+/*
+ * arch/arm/mach-ixp4xx/fsg-setup.c
+ *
+ * FSG board-setup
+ *
+ * Copyright (C) 2008 Rod Whitby <rod@whitby.id.au>
+ *
+ * based on ixdp425-setup.c:
+ *      Copyright (C) 2003-2004 MontaVista Software, Inc.
+ * based on nslu2-power.c
+ *      Copyright (C) 2005 Tower Technologies
+ *
+ * Author: Rod Whitby <rod@whitby.id.au>
+ * Maintainers: http://www.nslu2-linux.org/
+ *
+ */
+
+#include <linux/if_ether.h>
+#include <linux/irq.h>
+#include <linux/serial.h>
+#include <linux/serial_8250.h>
+#include <linux/leds.h>
+#include <linux/reboot.h>
+#include <linux/i2c.h>
+#include <linux/i2c-gpio.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/flash.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+
+static struct flash_platform_data fsg_flash_data = {
+        .map_name               = "cfi_probe",
+        .width                  = 2,
+};
+
+static struct resource fsg_flash_resource = {
+        .flags                  = IORESOURCE_MEM,
+};
+
+static struct platform_device fsg_flash = {
+        .name                   = "IXP4XX-Flash",
+        .id                     = 0,
+        .dev = {
+                .platform_data  = &fsg_flash_data,
+        },
+        .num_resources          = 1,
+        .resource               = &fsg_flash_resource,
+};
+
+static struct i2c_gpio_platform_data fsg_i2c_gpio_data = {
+        .sda_pin                = FSG_SDA_PIN,
+        .scl_pin                = FSG_SCL_PIN,
+};
+
+static struct platform_device fsg_i2c_gpio = {
+        .name                   = "i2c-gpio",
+        .id                     = 0,
+        .dev = {
+                .platform_data  = &fsg_i2c_gpio_data,
+        },
+};
+
+static struct i2c_board_info __initdata fsg_i2c_board_info [] = {
+        {
+                I2C_BOARD_INFO("rtc-isl1208", 0x6f),
+        },
+};
+
+static struct resource fsg_uart_resources[] = {
+        {
+                .start          = IXP4XX_UART1_BASE_PHYS,
+                .end            = IXP4XX_UART1_BASE_PHYS + 0x0fff,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = IXP4XX_UART2_BASE_PHYS,
+                .end            = IXP4XX_UART2_BASE_PHYS + 0x0fff,
+                .flags          = IORESOURCE_MEM,
+        }
+};
+
+static struct plat_serial8250_port fsg_uart_data[] = {
+        {
+                .mapbase        = IXP4XX_UART1_BASE_PHYS,
+                .membase        = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
+                .irq            = IRQ_IXP4XX_UART1,
+                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+                .uartclk        = IXP4XX_UART_XTAL,
+        },
+        {
+                .mapbase        = IXP4XX_UART2_BASE_PHYS,
+                .membase        = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
+                .irq            = IRQ_IXP4XX_UART2,
+                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+                .uartclk        = IXP4XX_UART_XTAL,
+        },
+        { }
+};
+
+static struct platform_device fsg_uart = {
+        .name                   = "serial8250",
+        .id                     = PLAT8250_DEV_PLATFORM,
+        .dev = {
+                .platform_data  = fsg_uart_data,
+        },
+        .num_resources          = ARRAY_SIZE(fsg_uart_resources),
+        .resource               = fsg_uart_resources,
+};
+
+static struct platform_device fsg_leds = {
+        .name           = "fsg-led",
+        .id             = -1,
+};
+
+/* Built-in 10/100 Ethernet MAC interfaces */
+static struct eth_plat_info fsg_plat_eth[] = {
+        {
+                .phy            = 5,
+                .rxq            = 3,
+                .txreadyq       = 20,
+        }, {
+                .phy            = 4,
+                .rxq            = 4,
+                .txreadyq       = 21,
+        }
+};
+
+static struct platform_device fsg_eth[] = {
+        {
+                .name                   = "ixp4xx_eth",
+                .id                     = IXP4XX_ETH_NPEB,
+                .dev = {
+                        .platform_data  = fsg_plat_eth,
+                },
+        }, {
+                .name                   = "ixp4xx_eth",
+                .id                     = IXP4XX_ETH_NPEC,
+                .dev = {
+                        .platform_data  = fsg_plat_eth + 1,
+                },
+        }
+};
+
+static struct platform_device *fsg_devices[] __initdata = {
+        &fsg_i2c_gpio,
+        &fsg_flash,
+        &fsg_leds,
+        &fsg_eth[0],
+        &fsg_eth[1],
+};
+
+static irqreturn_t fsg_power_handler(int irq, void *dev_id)
+{
+        /* Signal init to do the ctrlaltdel action, this will bypass init if
+         * it hasn't started and do a kernel_restart.
+         */
+        ctrl_alt_del();
+
+        return IRQ_HANDLED;
+}
+
+static irqreturn_t fsg_reset_handler(int irq, void *dev_id)
+{
+        /* This is the paper-clip reset which does an emergency reboot. */
+        printk(KERN_INFO "Restarting system.\n");
+        machine_restart(NULL);
+
+        /* This should never be reached. */
+        return IRQ_HANDLED;
+}
+
+static void __init fsg_init(void)
+{
+        DECLARE_MAC_BUF(mac_buf);
+        uint8_t __iomem *f;
+        int i;
+
+        ixp4xx_sys_init();
+
+        fsg_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
+        fsg_flash_resource.end =
+                IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
+
+        *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE;
+        *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
+
+        /* Configure CS2 for operation, 8bit and writable */
+        *IXP4XX_EXP_CS2 = 0xbfff0002;
+
+        i2c_register_board_info(0, fsg_i2c_board_info,
+                                ARRAY_SIZE(fsg_i2c_board_info));
+
+        /* This is only useful on a modified machine, but it is valuable
+         * to have it first in order to see debug messages, and so that
+         * it does *not* get removed if platform_add_devices fails!
+         */
+        (void)platform_device_register(&fsg_uart);
+
+        platform_add_devices(fsg_devices, ARRAY_SIZE(fsg_devices));
+
+        if (request_irq(gpio_to_irq(FSG_RB_GPIO), &fsg_reset_handler,
+                        IRQF_DISABLED | IRQF_TRIGGER_LOW,
+                        "FSG reset button", NULL) < 0) {
+
+                printk(KERN_DEBUG "Reset Button IRQ %d not available\n",
+                        gpio_to_irq(FSG_RB_GPIO));
+        }
+
+        if (request_irq(gpio_to_irq(FSG_SB_GPIO), &fsg_power_handler,
+                        IRQF_DISABLED | IRQF_TRIGGER_LOW,
+                        "FSG power button", NULL) < 0) {
+
+                printk(KERN_DEBUG "Power Button IRQ %d not available\n",
+                        gpio_to_irq(FSG_SB_GPIO));
+        }
+
+        /*
+         * Map in a portion of the flash and read the MAC addresses.
+         * Since it is stored in BE in the flash itself, we need to
+         * byteswap it if we're in LE mode.
+         */
+        f = ioremap(IXP4XX_EXP_BUS_BASE(0), 0x400000);
+        if (f) {
+#ifdef __ARMEB__
+                for (i = 0; i < 6; i++) {
+                        fsg_plat_eth[0].hwaddr[i] = readb(f + 0x3C0422 + i);
+                        fsg_plat_eth[1].hwaddr[i] = readb(f + 0x3C043B + i);
+                }
+#else
+
+                /*
+                  Endian-swapped reads from unaligned addresses are
+                  required to extract the two MACs from the big-endian
+                  Redboot config area in flash.
+                */
+
+                fsg_plat_eth[0].hwaddr[0] = readb(f + 0x3C0421);
+                fsg_plat_eth[0].hwaddr[1] = readb(f + 0x3C0420);
+                fsg_plat_eth[0].hwaddr[2] = readb(f + 0x3C0427);
+                fsg_plat_eth[0].hwaddr[3] = readb(f + 0x3C0426);
+                fsg_plat_eth[0].hwaddr[4] = readb(f + 0x3C0425);
+                fsg_plat_eth[0].hwaddr[5] = readb(f + 0x3C0424);
+
+                fsg_plat_eth[1].hwaddr[0] = readb(f + 0x3C0439);
+                fsg_plat_eth[1].hwaddr[1] = readb(f + 0x3C043F);
+                fsg_plat_eth[1].hwaddr[2] = readb(f + 0x3C043E);
+                fsg_plat_eth[1].hwaddr[3] = readb(f + 0x3C043D);
+                fsg_plat_eth[1].hwaddr[4] = readb(f + 0x3C043C);
+                fsg_plat_eth[1].hwaddr[5] = readb(f + 0x3C0443);
+#endif
+                iounmap(f);
+        }
+        printk(KERN_INFO "FSG: Using MAC address %s for port 0\n",
+               print_mac(mac_buf, fsg_plat_eth[0].hwaddr));
+        printk(KERN_INFO "FSG: Using MAC address %s for port 1\n",
+               print_mac(mac_buf, fsg_plat_eth[1].hwaddr));
+
+}
+
+MACHINE_START(FSG, "Freecom FSG-3")
+        /* Maintainer: www.nslu2-linux.org */
+        .phys_io        = IXP4XX_PERIPHERAL_BASE_PHYS,
+        .io_pg_offst    = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
+        .map_io         = ixp4xx_map_io,
+        .init_irq       = ixp4xx_init_irq,
+        .timer          = &ixp4xx_timer,
+        .boot_params    = 0x0100,
+        .init_machine   = fsg_init,
+MACHINE_END
+
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
new file mode 100644
index 000000000000..3600cd9f0519
--- /dev/null
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -0,0 +1,25 @@
+if ARCH_KIRKWOOD
+
+menu "Marvell Kirkwood Implementations"
+
+config MACH_DB88F6281_BP
+        bool "Marvell DB-88F6281-BP Development Board"
+        help
+          Say 'Y' here if you want your kernel to support the
+          Marvell DB-88F6281-BP Development Board.
+
+config MACH_RD88F6192_NAS
+        bool "Marvell RD-88F6192-NAS Reference Board"
+        help
+          Say 'Y' here if you want your kernel to support the
+          Marvell RD-88F6192-NAS Reference Board.
+
+config MACH_RD88F6281
+        bool "Marvell RD-88F6281 Reference Board"
+        help
+          Say 'Y' here if you want your kernel to support the
+          Marvell RD-88F6281 Reference Board.
+
+endmenu
+
+endif
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
new file mode 100644
index 000000000000..e14bf40bfb07
--- /dev/null
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -0,0 +1,5 @@
+obj-y                           += common.o addr-map.o irq.o pcie.o
+
+obj-$(CONFIG_MACH_DB88F6281_BP)         += db88f6281-bp-setup.o
+obj-$(CONFIG_MACH_RD88F6192_NAS)        += rd88f6192-nas-setup.o
+obj-$(CONFIG_MACH_RD88F6192_NAS)        += rd88f6281-setup.o
diff --git a/arch/arm/mach-kirkwood/Makefile.boot b/arch/arm/mach-kirkwood/Makefile.boot
new file mode 100644
index 000000000000..67039c3e0c48
--- /dev/null
+++ b/arch/arm/mach-kirkwood/Makefile.boot
@@ -0,0 +1,3 @@
+   zreladdr-y   := 0x00008000
+params_phys-y   := 0x00000100
+initrd_phys-y   := 0x00800000
diff --git a/arch/arm/mach-kirkwood/addr-map.c b/arch/arm/mach-kirkwood/addr-map.c
new file mode 100644
index 000000000000..a39f0f3c4730
--- /dev/null
+++ b/arch/arm/mach-kirkwood/addr-map.c
@@ -0,0 +1,139 @@
+/*
+ * arch/arm/mach-kirkwood/addr-map.c
+ *
+ * Address map functions for Marvell Kirkwood SoCs
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mbus.h>
+#include <linux/io.h>
+#include <asm/hardware.h>
+#include "common.h"
+
+/*
+ * Generic Address Decode Windows bit settings
+ */
+#define TARGET_DDR              0
+#define TARGET_DEV_BUS          1
+#define TARGET_PCIE             4
+#define ATTR_DEV_SPI_ROM        0x1e
+#define ATTR_DEV_BOOT           0x1d
+#define ATTR_DEV_NAND           0x2f
+#define ATTR_DEV_CS3            0x37
+#define ATTR_DEV_CS2            0x3b
+#define ATTR_DEV_CS1            0x3d
+#define ATTR_DEV_CS0            0x3e
+#define ATTR_PCIE_IO            0xe0
+#define ATTR_PCIE_MEM           0xe8
+
+/*
+ * Helpers to get DDR bank info
+ */
+#define DDR_BASE_CS_OFF(n)      (0x0000 + ((n) << 3))
+#define DDR_SIZE_CS_OFF(n)      (0x0004 + ((n) << 3))
+
+/*
+ * CPU Address Decode Windows registers
+ */
+#define WIN_OFF(n)              (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4))
+#define WIN_CTRL_OFF            0x0000
+#define WIN_BASE_OFF            0x0004
+#define WIN_REMAP_LO_OFF        0x0008
+#define WIN_REMAP_HI_OFF        0x000c
+
+
+struct mbus_dram_target_info kirkwood_mbus_dram_info;
+
+static int __init cpu_win_can_remap(int win)
+{
+        if (win < 4)
+                return 1;
+
+        return 0;
+}
+
+static void __init setup_cpu_win(int win, u32 base, u32 size,
+                                 u8 target, u8 attr, int remap)
+{
+        void __iomem *addr = (void __iomem *)WIN_OFF(win);
+        u32 ctrl;
+
+        base &= 0xffff0000;
+        ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1;
+
+        writel(base, addr + WIN_BASE_OFF);
+        writel(ctrl, addr + WIN_CTRL_OFF);
+        if (cpu_win_can_remap(win)) {
+                if (remap < 0)
+                        remap = base;
+
+                writel(remap & 0xffff0000, addr + WIN_REMAP_LO_OFF);
+                writel(0, addr + WIN_REMAP_HI_OFF);
+        }
+}
+
+void __init kirkwood_setup_cpu_mbus(void)
+{
+        void __iomem *addr;
+        int i;
+        int cs;
+
+        /*
+         * First, disable and clear windows.
+         */
+        for (i = 0; i < 8; i++) {
+                addr = (void __iomem *)WIN_OFF(i);
+
+                writel(0, addr + WIN_BASE_OFF);
+                writel(0, addr + WIN_CTRL_OFF);
+                if (cpu_win_can_remap(i)) {
+                        writel(0, addr + WIN_REMAP_LO_OFF);
+                        writel(0, addr + WIN_REMAP_HI_OFF);
+                }
+        }
+
+        /*
+         * Setup windows for PCIe IO+MEM space.
+         */
+        setup_cpu_win(0, KIRKWOOD_PCIE_IO_PHYS_BASE, KIRKWOOD_PCIE_IO_SIZE,
+                      TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE);
+        setup_cpu_win(1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE,
+                      TARGET_PCIE, ATTR_PCIE_MEM, -1);
+
+        /*
+         * Setup window for NAND controller.
+         */
+        setup_cpu_win(2, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
+                      TARGET_DEV_BUS, ATTR_DEV_NAND, -1);
+
+        /*
+         * Setup MBUS dram target info.
+         */
+        kirkwood_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
+
+        addr = (void __iomem *)DDR_WINDOW_CPU_BASE;
+
+        for (i = 0, cs = 0; i < 4; i++) {
+                u32 base = readl(addr + DDR_BASE_CS_OFF(i));
+                u32 size = readl(addr + DDR_SIZE_CS_OFF(i));
+
+                /*
+                 * Chip select enabled?
+                 */
+                if (size & 1) {
+                        struct mbus_dram_window *w;
+
+                        w = &kirkwood_mbus_dram_info.cs[cs++];
+                        w->cs_index = i;
+                        w->mbus_attr = 0xf & ~(1 << i);
+                        w->base = base & 0xffff0000;
+                        w->size = (size | 0x0000ffff) + 1;
+                }
+        }
+        kirkwood_mbus_dram_info.num_cs = cs;
+}
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
new file mode 100644
index 000000000000..5938a3b33cdc
--- /dev/null
+++ b/arch/arm/mach-kirkwood/common.c
@@ -0,0 +1,331 @@
+/*
+ * arch/arm/mach-kirkwood/common.c
+ *
+ * Core functions for Marvell Kirkwood SoCs
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/serial_8250.h>
+#include <linux/mbus.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/ata_platform.h>
+#include <asm/page.h>
+#include <asm/timex.h>
+#include <asm/mach/map.h>
+#include <asm/mach/time.h>
+#include <asm/arch/kirkwood.h>
+#include <asm/plat-orion/cache-feroceon-l2.h>
+#include <asm/plat-orion/ehci-orion.h>
+#include <asm/plat-orion/orion_nand.h>
+#include <asm/plat-orion/time.h>
+#include "common.h"
+
+/*****************************************************************************
+ * I/O Address Mapping
+ ****************************************************************************/
+static struct map_desc kirkwood_io_desc[] __initdata = {
+        {
+                .virtual        = KIRKWOOD_PCIE_IO_VIRT_BASE,
+                .pfn            = __phys_to_pfn(KIRKWOOD_PCIE_IO_PHYS_BASE),
+                .length         = KIRKWOOD_PCIE_IO_SIZE,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = KIRKWOOD_REGS_VIRT_BASE,
+                .pfn            = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
+                .length         = KIRKWOOD_REGS_SIZE,
+                .type           = MT_DEVICE,
+        },
+};
+
+void __init kirkwood_map_io(void)
+{
+        iotable_init(kirkwood_io_desc, ARRAY_SIZE(kirkwood_io_desc));
+}
+
+
+/*****************************************************************************
+ * EHCI
+ ****************************************************************************/
+static struct orion_ehci_data kirkwood_ehci_data = {
+        .dram           = &kirkwood_mbus_dram_info,
+};
+
+static u64 ehci_dmamask = 0xffffffffUL;
+
+
+/*****************************************************************************
+ * EHCI0
+ ****************************************************************************/
+static struct resource kirkwood_ehci_resources[] = {
+        {
+                .start  = USB_PHYS_BASE,
+                .end    = USB_PHYS_BASE + 0x0fff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = IRQ_KIRKWOOD_USB,
+                .end    = IRQ_KIRKWOOD_USB,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device kirkwood_ehci = {
+        .name           = "orion-ehci",
+        .id             = 0,
+        .dev            = {
+                .dma_mask               = &ehci_dmamask,
+                .coherent_dma_mask      = 0xffffffff,
+                .platform_data          = &kirkwood_ehci_data,
+        },
+        .resource       = kirkwood_ehci_resources,
+        .num_resources  = ARRAY_SIZE(kirkwood_ehci_resources),
+};
+
+void __init kirkwood_ehci_init(void)
+{
+        platform_device_register(&kirkwood_ehci);
+}
+
+
+/*****************************************************************************
+ * GE00
+ ****************************************************************************/
+struct mv643xx_eth_shared_platform_data kirkwood_ge00_shared_data = {
+        .t_clk          = KIRKWOOD_TCLK,
+        .dram           = &kirkwood_mbus_dram_info,
+};
+
+static struct resource kirkwood_ge00_shared_resources[] = {
+        {
+                .name   = "ge00 base",
+                .start  = GE00_PHYS_BASE + 0x2000,
+                .end    = GE00_PHYS_BASE + 0x3fff,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device kirkwood_ge00_shared = {
+        .name           = MV643XX_ETH_SHARED_NAME,
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &kirkwood_ge00_shared_data,
+        },
+        .num_resources  = 1,
+        .resource       = kirkwood_ge00_shared_resources,
+};
+
+static struct resource kirkwood_ge00_resources[] = {
+        {
+                .name   = "ge00 irq",
+                .start  = IRQ_KIRKWOOD_GE00_SUM,
+                .end    = IRQ_KIRKWOOD_GE00_SUM,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device kirkwood_ge00 = {
+        .name           = MV643XX_ETH_NAME,
+        .id             = 0,
+        .num_resources  = 1,
+        .resource       = kirkwood_ge00_resources,
+};
+
+void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data)
+{
+        eth_data->shared = &kirkwood_ge00_shared;
+        kirkwood_ge00.dev.platform_data = eth_data;
+
+        platform_device_register(&kirkwood_ge00_shared);
+        platform_device_register(&kirkwood_ge00);
+}
+
+
+/*****************************************************************************
+ * SoC RTC
+ ****************************************************************************/
+static struct resource kirkwood_rtc_resource = {
+        .start  = RTC_PHYS_BASE,
+        .end    = RTC_PHYS_BASE + SZ_16 - 1,
+        .flags  = IORESOURCE_MEM,
+};
+
+void __init kirkwood_rtc_init(void)
+{
+        platform_device_register_simple("rtc-mv", -1, &kirkwood_rtc_resource, 1);
+}
+
+
+/*****************************************************************************
+ * SATA
+ ****************************************************************************/
+static struct resource kirkwood_sata_resources[] = {
+        {
+                .name   = "sata base",
+                .start  = SATA_PHYS_BASE,
+                .end    = SATA_PHYS_BASE + 0x5000 - 1,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .name   = "sata irq",
+                .start  = IRQ_KIRKWOOD_SATA,
+                .end    = IRQ_KIRKWOOD_SATA,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device kirkwood_sata = {
+        .name           = "sata_mv",
+        .id             = 0,
+        .dev            = {
+                .coherent_dma_mask      = 0xffffffff,
+        },
+        .num_resources  = ARRAY_SIZE(kirkwood_sata_resources),
+        .resource       = kirkwood_sata_resources,
+};
+
+void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data)
+{
+        sata_data->dram = &kirkwood_mbus_dram_info;
+        kirkwood_sata.dev.platform_data = sata_data;
+        platform_device_register(&kirkwood_sata);
+}
+
+
+/*****************************************************************************
+ * UART0
+ ****************************************************************************/
+static struct plat_serial8250_port kirkwood_uart0_data[] = {
+        {
+                .mapbase        = UART0_PHYS_BASE,
+                .membase        = (char *)UART0_VIRT_BASE,
+                .irq            = IRQ_KIRKWOOD_UART_0,
+                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+                .uartclk        = KIRKWOOD_TCLK,
+        }, {
+        },
+};
+
+static struct resource kirkwood_uart0_resources[] = {
+        {
+                .start          = UART0_PHYS_BASE,
+                .end            = UART0_PHYS_BASE + 0xff,
+                .flags          = IORESOURCE_MEM,
+        }, {
+                .start          = IRQ_KIRKWOOD_UART_0,
+                .end            = IRQ_KIRKWOOD_UART_0,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device kirkwood_uart0 = {
+        .name                   = "serial8250",
+        .id                     = 0,
+        .dev                    = {
+                .platform_data  = kirkwood_uart0_data,
+        },
+        .resource               = kirkwood_uart0_resources,
+        .num_resources          = ARRAY_SIZE(kirkwood_uart0_resources),
+};
+
+void __init kirkwood_uart0_init(void)
+{
+        platform_device_register(&kirkwood_uart0);
+}
+
+
+/*****************************************************************************
+ * UART1
+ ****************************************************************************/
+static struct plat_serial8250_port kirkwood_uart1_data[] = {
+        {
+                .mapbase        = UART1_PHYS_BASE,
+                .membase        = (char *)UART1_VIRT_BASE,
+                .irq            = IRQ_KIRKWOOD_UART_1,
+                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+                .uartclk        = KIRKWOOD_TCLK,
+        }, {
+        },
+};
+
+static struct resource kirkwood_uart1_resources[] = {
+        {
+                .start          = UART1_PHYS_BASE,
+                .end            = UART1_PHYS_BASE + 0xff,
+                .flags          = IORESOURCE_MEM,
+        }, {
+                .start          = IRQ_KIRKWOOD_UART_1,
+                .end            = IRQ_KIRKWOOD_UART_1,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device kirkwood_uart1 = {
+        .name                   = "serial8250",
+        .id                     = 1,
+        .dev                    = {
+                .platform_data  = kirkwood_uart1_data,
+        },
+        .resource               = kirkwood_uart1_resources,
+        .num_resources          = ARRAY_SIZE(kirkwood_uart1_resources),
+};
+
+void __init kirkwood_uart1_init(void)
+{
+        platform_device_register(&kirkwood_uart1);
+}
+
+
+/*****************************************************************************
+ * Time handling
+ ****************************************************************************/
+static void kirkwood_timer_init(void)
+{
+        orion_time_init(IRQ_KIRKWOOD_BRIDGE, KIRKWOOD_TCLK);
+}
+
+struct sys_timer kirkwood_timer = {
+        .init = kirkwood_timer_init,
+};
+
+
+/*****************************************************************************
+ * General
+ ****************************************************************************/
+static char * __init kirkwood_id(void)
+{
+        switch (readl(DEVICE_ID) & 0x3) {
+        case 0:
+                return "88F6180";
+        case 1:
+                return "88F6192";
+        case 2:
+                return "88F6281";
+        }
+
+        return "unknown 88F6000 variant";
+}
+
+static int __init is_l2_writethrough(void)
+{
+        return !!(readl(L2_CONFIG_REG) & L2_WRITETHROUGH);
+}
+
+void __init kirkwood_init(void)
+{
+        printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n",
+                kirkwood_id(), KIRKWOOD_TCLK);
+
+        kirkwood_setup_cpu_mbus();
+
+#ifdef CONFIG_CACHE_FEROCEON_L2
+        feroceon_l2_init(is_l2_writethrough());
+#endif
+}
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
new file mode 100644
index 000000000000..5dee2f6b40a5
--- /dev/null
+++ b/arch/arm/mach-kirkwood/common.h
@@ -0,0 +1,42 @@
+/*
+ * arch/arm/mach-kirkwood/common.h
+ *
+ * Core functions for Marvell Kirkwood SoCs
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ARCH_KIRKWOOD_COMMON_H
+#define __ARCH_KIRKWOOD_COMMON_H
+
+struct mv643xx_eth_platform_data;
+struct mv_sata_platform_data;
+
+/*
+ * Basic Kirkwood init functions used early by machine-setup.
+ */
+void kirkwood_map_io(void);
+void kirkwood_init(void);
+void kirkwood_init_irq(void);
+
+extern struct mbus_dram_target_info kirkwood_mbus_dram_info;
+void kirkwood_setup_cpu_mbus(void);
+void kirkwood_setup_pcie_io_win(int window, u32 base, u32 size,
+                                int maj, int min);
+void kirkwood_setup_pcie_mem_win(int window, u32 base, u32 size,
+                                 int maj, int min);
+
+void kirkwood_ehci_init(void);
+void kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data);
+void kirkwood_pcie_init(void);
+void kirkwood_rtc_init(void);
+void kirkwood_sata_init(struct mv_sata_platform_data *sata_data);
+void kirkwood_uart0_init(void);
+void kirkwood_uart1_init(void);
+
+extern struct sys_timer kirkwood_timer;
+
+
+#endif
diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
new file mode 100644
index 000000000000..d5c482c628e3
--- /dev/null
+++ b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
@@ -0,0 +1,68 @@
+/*
+ * arch/arm/mach-kirkwood/db88f6281-bp-setup.c
+ *
+ * Marvell DB-88F6281-BP Development Board Setup
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/pci.h>
+#include <linux/irq.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mtd/nand.h>
+#include <linux/timer.h>
+#include <linux/ata_platform.h>
+#include <linux/mv643xx_eth.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/pci.h>
+#include <asm/arch/kirkwood.h>
+#include "common.h"
+
+static struct mv643xx_eth_platform_data db88f6281_ge00_data = {
+        .phy_addr       = 8,
+};
+
+static struct mv_sata_platform_data db88f6281_sata_data = {
+        .n_ports        = 2,
+};
+
+static void __init db88f6281_init(void)
+{
+        /*
+         * Basic setup. Needs to be called early.
+         */
+        kirkwood_init();
+
+        kirkwood_ehci_init();
+        kirkwood_ge00_init(&db88f6281_ge00_data);
+        kirkwood_rtc_init();
+        kirkwood_sata_init(&db88f6281_sata_data);
+        kirkwood_uart0_init();
+        kirkwood_uart1_init();
+}
+
+static int __init db88f6281_pci_init(void)
+{
+        if (machine_is_db88f6281_bp())
+                kirkwood_pcie_init();
+
+        return 0;
+}
+subsys_initcall(db88f6281_pci_init);
+
+MACHINE_START(DB88F6281_BP, "Marvell DB-88F6281-BP Development Board")
+        /* Maintainer: Saeed Bishara <saeed@marvell.com> */
+        .phys_io        = KIRKWOOD_REGS_PHYS_BASE,
+        .io_pg_offst    = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
+        .boot_params    = 0x00000100,
+        .init_machine   = db88f6281_init,
+        .map_io         = kirkwood_map_io,
+        .init_irq       = kirkwood_init_irq,
+        .timer          = &kirkwood_timer,
+MACHINE_END
diff --git a/arch/arm/mach-kirkwood/irq.c b/arch/arm/mach-kirkwood/irq.c
new file mode 100644
index 000000000000..302bb2cf6669
--- /dev/null
+++ b/arch/arm/mach-kirkwood/irq.c
@@ -0,0 +1,22 @@
+/*
+ * arch/arm/mach-kirkwood/irq.c
+ *
+ * Kirkwood IRQ handling.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <asm/plat-orion/irq.h>
+#include "common.h"
+
+void __init kirkwood_init_irq(void)
+{
+        orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
+        orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
+}
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
new file mode 100644
index 000000000000..8282d0ff84bf
--- /dev/null
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -0,0 +1,180 @@
+/*
+ * arch/arm/mach-kirkwood/pcie.c
+ *
+ * PCIe functions for Marvell Kirkwood SoCs
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/mbus.h>
+#include <asm/mach/pci.h>
+#include <asm/plat-orion/pcie.h>
+#include "common.h"
+
+
+#define PCIE_BASE       ((void __iomem *)PCIE_VIRT_BASE)
+
+static int pcie_valid_config(int bus, int dev)
+{
+        /*
+         * Don't go out when trying to access --
+         * 1. nonexisting device on local bus
+         * 2. where there's no device connected (no link)
+         */
+        if (bus == 0 && dev == 0)
+                return 1;
+
+        if (!orion_pcie_link_up(PCIE_BASE))
+                return 0;
+
+        if (bus == 0 && dev != 1)
+                return 0;
+
+        return 1;
+}
+
+
+/*
+ * PCIe config cycles are done by programming the PCIE_CONF_ADDR register
+ * and then reading the PCIE_CONF_DATA register. Need to make sure these
+ * transactions are atomic.
+ */
+static DEFINE_SPINLOCK(kirkwood_pcie_lock);
+
+static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
+                        int size, u32 *val)
+{
+        unsigned long flags;
+        int ret;
+
+        if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
+                *val = 0xffffffff;
+                return PCIBIOS_DEVICE_NOT_FOUND;
+        }
+
+        spin_lock_irqsave(&kirkwood_pcie_lock, flags);
+        ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val);
+        spin_unlock_irqrestore(&kirkwood_pcie_lock, flags);
+
+        return ret;
+}
+
+static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
+                        int where, int size, u32 val)
+{
+        unsigned long flags;
+        int ret;
+
+        if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
+                return PCIBIOS_DEVICE_NOT_FOUND;
+
+        spin_lock_irqsave(&kirkwood_pcie_lock, flags);
+        ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val);
+        spin_unlock_irqrestore(&kirkwood_pcie_lock, flags);
+
+        return ret;
+}
+
+static struct pci_ops pcie_ops = {
+        .read = pcie_rd_conf,
+        .write = pcie_wr_conf,
+};
+
+
+static int kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
+{
+        struct resource *res;
+
+        /*
+         * Generic PCIe unit setup.
+         */
+        orion_pcie_setup(PCIE_BASE, &kirkwood_mbus_dram_info);
+
+        /*
+         * Request resources.
+         */
+        res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
+        if (!res)
+                panic("pcie_setup unable to alloc resources");
+
+        /*
+         * IORESOURCE_IO
+         */
+        res[0].name = "PCIe I/O Space";
+        res[0].flags = IORESOURCE_IO;
+        res[0].start = KIRKWOOD_PCIE_IO_PHYS_BASE;
+        res[0].end = res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
+        if (request_resource(&ioport_resource, &res[0]))
+                panic("Request PCIe IO resource failed\n");
+        sys->resource[0] = &res[0];
+
+        /*
+         * IORESOURCE_MEM
+         */
+        res[1].name = "PCIe Memory Space";
+        res[1].flags = IORESOURCE_MEM;
+        res[1].start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
+        res[1].end = res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1;
+        if (request_resource(&iomem_resource, &res[1]))
+                panic("Request PCIe Memory resource failed\n");
+        sys->resource[1] = &res[1];
+
+        sys->resource[2] = NULL;
+        sys->io_offset = 0;
+
+        return 1;
+}
+
+static void __devinit rc_pci_fixup(struct pci_dev *dev)
+{
+        /*
+         * Prevent enumeration of root complex.
+         */
+        if (dev->bus->parent == NULL && dev->devfn == 0) {
+                int i;
+
+                for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
+                        dev->resource[i].start = 0;
+                        dev->resource[i].end   = 0;
+                        dev->resource[i].flags = 0;
+                }
+        }
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
+
+static struct pci_bus __init *
+kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
+{
+        struct pci_bus *bus;
+
+        if (nr == 0) {
+                bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
+        } else {
+                bus = NULL;
+                BUG();
+        }
+
+        return bus;
+}
+
+static int __init kirkwood_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+        return IRQ_KIRKWOOD_PCIE;
+}
+
+static struct hw_pci kirkwood_pci __initdata = {
+        .nr_controllers = 1,
+        .swizzle        = pci_std_swizzle,
+        .setup          = kirkwood_pcie_setup,
+        .scan           = kirkwood_pcie_scan_bus,
+        .map_irq        = kirkwood_pcie_map_irq,
+};
+
+void __init kirkwood_pcie_init(void)
+{
+        pci_common_init(&kirkwood_pci);
+}
diff --git a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
new file mode 100644
index 000000000000..6cf642c504d3
--- /dev/null
+++ b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
@@ -0,0 +1,69 @@
+/*
+ * arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
+ *
+ * Marvell RD-88F6192-NAS Reference Board Setup
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/pci.h>
+#include <linux/irq.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mtd/nand.h>
+#include <linux/timer.h>
+#include <linux/ata_platform.h>
+#include <linux/mv643xx_eth.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/pci.h>
+#include <asm/arch/kirkwood.h>
+#include "common.h"
+
+#define RD88F6192_GPIO_USB_VBUS         10
+
+static struct mv643xx_eth_platform_data rd88f6192_ge00_data = {
+        .phy_addr       = 8,
+};
+
+static struct mv_sata_platform_data rd88f6192_sata_data = {
+        .n_ports        = 2,
+};
+
+static void __init rd88f6192_init(void)
+{
+        /*
+         * Basic setup. Needs to be called early.
+         */
+        kirkwood_init();
+
+        kirkwood_ehci_init();
+        kirkwood_ge00_init(&rd88f6192_ge00_data);
+        kirkwood_rtc_init();
+        kirkwood_sata_init(&rd88f6192_sata_data);
+        kirkwood_uart0_init();
+}
+
+static int __init rd88f6192_pci_init(void)
+{
+        if (machine_is_rd88f6192_nas())
+                kirkwood_pcie_init();
+
+        return 0;
+}
+subsys_initcall(rd88f6192_pci_init);
+
+MACHINE_START(RD88F6192_NAS, "Marvell RD-88F6192-NAS Development Board")
+        /* Maintainer: Saeed Bishara <saeed@marvell.com> */
+        .phys_io        = KIRKWOOD_REGS_PHYS_BASE,
+        .io_pg_offst    = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
+        .boot_params    = 0x00000100,
+        .init_machine   = rd88f6192_init,
+        .map_io         = kirkwood_map_io,
+        .init_irq       = kirkwood_init_irq,
+        .timer          = &kirkwood_timer,
+MACHINE_END
diff --git a/arch/arm/mach-kirkwood/rd88f6281-setup.c b/arch/arm/mach-kirkwood/rd88f6281-setup.c
new file mode 100644
index 000000000000..e1f8de2c74a2
--- /dev/null
+++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c
@@ -0,0 +1,113 @@
+/*
+ * arch/arm/mach-kirkwood/rd88f6281-setup.c
+ *
+ * Marvell RD-88F6281 Reference Board Setup
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/pci.h>
+#include <linux/irq.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mtd/nand.h>
+#include <linux/timer.h>
+#include <linux/ata_platform.h>
+#include <linux/mv643xx_eth.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/pci.h>
+#include <asm/arch/kirkwood.h>
+#include <asm/plat-orion/orion_nand.h>
+#include "common.h"
+
+static struct mtd_partition rd88f6281_nand_parts[] = {
+        {
+                .name = "u-boot",
+                .offset = 0,
+                .size = SZ_1M
+        }, {
+                .name = "uImage",
+                .offset = MTDPART_OFS_NXTBLK,
+                .size = SZ_2M
+        }, {
+                .name = "root",
+                .offset = MTDPART_OFS_NXTBLK,
+                .size = MTDPART_SIZ_FULL
+        },
+};
+
+static struct resource rd88f6281_nand_resource = {
+        .flags          = IORESOURCE_MEM,
+        .start          = KIRKWOOD_NAND_MEM_PHYS_BASE,
+        .end            = KIRKWOOD_NAND_MEM_PHYS_BASE +
+                          KIRKWOOD_NAND_MEM_SIZE - 1,
+};
+
+static struct orion_nand_data rd88f6281_nand_data = {
+        .parts          = rd88f6281_nand_parts,
+        .nr_parts       = ARRAY_SIZE(rd88f6281_nand_parts),
+        .cle            = 0,
+        .ale            = 1,
+        .width          = 8,
+        .chip_delay     = 25,
+};
+
+static struct platform_device rd88f6281_nand_flash = {
+        .name           = "orion_nand",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &rd88f6281_nand_data,
+        },
+        .resource       = &rd88f6281_nand_resource,
+        .num_resources  = 1,
+};
+
+static struct mv643xx_eth_platform_data rd88f6281_ge00_data = {
+        .phy_addr       = -1,
+};
+
+static struct mv_sata_platform_data rd88f6281_sata_data = {
+        .n_ports        = 2,
+};
+
+static void __init rd88f6281_init(void)
+{
+        /*
+         * Basic setup. Needs to be called early.
+         */
+        kirkwood_init();
+
+        kirkwood_ehci_init();
+        kirkwood_ge00_init(&rd88f6281_ge00_data);
+        kirkwood_rtc_init();
+        kirkwood_sata_init(&rd88f6281_sata_data);
+        kirkwood_uart0_init();
+        kirkwood_uart1_init();
+
+        platform_device_register(&rd88f6281_nand_flash);
+}
+
+static int __init rd88f6281_pci_init(void)
+{
+        if (machine_is_rd88f6281())
+                kirkwood_pcie_init();
+
+        return 0;
+}
+subsys_initcall(rd88f6281_pci_init);
+
+MACHINE_START(RD88F6281, "Marvell RD-88F6281 Reference Board")
+        /* Maintainer: Saeed Bishara <saeed@marvell.com> */
+        .phys_io        = KIRKWOOD_REGS_PHYS_BASE,
+        .io_pg_offst    = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
+        .boot_params    = 0x00000100,
+        .init_machine   = rd88f6281_init,
+        .map_io         = kirkwood_map_io,
+        .init_irq       = kirkwood_init_irq,
+        .timer          = &kirkwood_timer,
+MACHINE_END
diff --git a/arch/arm/mach-loki/Kconfig b/arch/arm/mach-loki/Kconfig
new file mode 100644
index 000000000000..0045bdd761ca
--- /dev/null
+++ b/arch/arm/mach-loki/Kconfig
@@ -0,0 +1,13 @@
+if ARCH_LOKI
+
+menu "Marvell Loki (88RC8480) Implementations"
+
+config MACH_LB88RC8480
+        bool "Marvell LB88RC8480 Development Board"
+        help
+          Say 'Y' here if you want your kernel to support the
+          Marvell LB88RC8480 Development Board.
+
+endmenu
+
+endif
diff --git a/arch/arm/mach-loki/Makefile b/arch/arm/mach-loki/Makefile
new file mode 100644
index 000000000000..d43233ee590f
--- /dev/null
+++ b/arch/arm/mach-loki/Makefile
@@ -0,0 +1,3 @@
+obj-y                           += common.o addr-map.o irq.o
+
+obj-$(CONFIG_MACH_LB88RC8480)   += lb88rc8480-setup.o
diff --git a/arch/arm/mach-loki/Makefile.boot b/arch/arm/mach-loki/Makefile.boot
new file mode 100644
index 000000000000..67039c3e0c48
--- /dev/null
+++ b/arch/arm/mach-loki/Makefile.boot
@@ -0,0 +1,3 @@
+   zreladdr-y   := 0x00008000
+params_phys-y   := 0x00000100
+initrd_phys-y   := 0x00800000
diff --git a/arch/arm/mach-loki/addr-map.c b/arch/arm/mach-loki/addr-map.c
new file mode 100644
index 000000000000..ba25e56ade58
--- /dev/null
+++ b/arch/arm/mach-loki/addr-map.c
@@ -0,0 +1,121 @@
+/*
+ * arch/arm/mach-loki/addr-map.c
+ *
+ * Address map functions for Marvell Loki (88RC8480) SoCs
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mbus.h>
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include "common.h"
+
+/*
+ * Generic Address Decode Windows bit settings
+ */
+#define TARGET_DDR              0
+#define TARGET_DEV_BUS          1
+#define TARGET_PCIE0            3
+#define TARGET_PCIE1            4
+#define ATTR_DEV_BOOT           0x0f
+#define ATTR_DEV_CS2            0x1b
+#define ATTR_DEV_CS1            0x1d
+#define ATTR_DEV_CS0            0x1e
+#define ATTR_PCIE_IO            0x51
+#define ATTR_PCIE_MEM           0x59
+
+/*
+ * Helpers to get DDR bank info
+ */
+#define DDR_SIZE_CS(n)          DDR_REG(0x1500 + ((n) << 3))
+#define DDR_BASE_CS(n)          DDR_REG(0x1504 + ((n) << 3))
+
+/*
+ * CPU Address Decode Windows registers
+ */
+#define CPU_WIN_CTRL(n)         BRIDGE_REG(0x000 | ((n) << 4))
+#define CPU_WIN_BASE(n)         BRIDGE_REG(0x004 | ((n) << 4))
+#define CPU_WIN_REMAP_LO(n)     BRIDGE_REG(0x008 | ((n) << 4))
+#define CPU_WIN_REMAP_HI(n)     BRIDGE_REG(0x00c | ((n) << 4))
+
+
+struct mbus_dram_target_info loki_mbus_dram_info;
+
+static void __init setup_cpu_win(int win, u32 base, u32 size,
+                                 u8 target, u8 attr, int remap)
+{
+        u32 ctrl;
+
+        base &= 0xffff0000;
+        ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (1 << 5) | target;
+
+        writel(base, CPU_WIN_BASE(win));
+        writel(ctrl, CPU_WIN_CTRL(win));
+        if (win < 2) {
+                if (remap < 0)
+                        remap = base;
+
+                writel(remap & 0xffff0000, CPU_WIN_REMAP_LO(win));
+                writel(0, CPU_WIN_REMAP_HI(win));
+        }
+}
+
+void __init loki_setup_cpu_mbus(void)
+{
+        int i;
+        int cs;
+
+        /*
+         * First, disable and clear windows.
+         */
+        for (i = 0; i < 8; i++) {
+                writel(0, CPU_WIN_BASE(i));
+                writel(0, CPU_WIN_CTRL(i));
+                if (i < 2) {
+                        writel(0, CPU_WIN_REMAP_LO(i));
+                        writel(0, CPU_WIN_REMAP_HI(i));
+                }
+        }
+
+        /*
+         * Setup windows for PCIe IO+MEM space.
+         */
+        setup_cpu_win(2, LOKI_PCIE0_MEM_PHYS_BASE, LOKI_PCIE0_MEM_SIZE,
+                      TARGET_PCIE0, ATTR_PCIE_MEM, -1);
+        setup_cpu_win(3, LOKI_PCIE1_MEM_PHYS_BASE, LOKI_PCIE1_MEM_SIZE,
+                      TARGET_PCIE1, ATTR_PCIE_MEM, -1);
+
+        /*
+         * Setup MBUS dram target info.
+         */
+        loki_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
+
+        for (i = 0, cs = 0; i < 4; i++) {
+                u32 base = readl(DDR_BASE_CS(i));
+                u32 size = readl(DDR_SIZE_CS(i));
+
+                /*
+                 * Chip select enabled?
+                 */
+                if (size & 1) {
+                        struct mbus_dram_window *w;
+
+                        w = &loki_mbus_dram_info.cs[cs++];
+                        w->cs_index = i;
+                        w->mbus_attr = 0xf & ~(1 << i);
+                        w->base = base & 0xffff0000;
+                        w->size = (size | 0x0000ffff) + 1;
+                }
+        }
+        loki_mbus_dram_info.num_cs = cs;
+}
+
+void __init loki_setup_dev_boot_win(u32 base, u32 size)
+{
+        setup_cpu_win(4, base, size, TARGET_DEV_BUS, ATTR_DEV_BOOT, -1);
+}
diff --git a/arch/arm/mach-loki/common.c b/arch/arm/mach-loki/common.c
new file mode 100644
index 000000000000..410f50399dd3
--- /dev/null
+++ b/arch/arm/mach-loki/common.c
@@ -0,0 +1,305 @@
+/*
+ * arch/arm/mach-loki/common.c
+ *
+ * Core functions for Marvell Loki (88RC8480) SoCs
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/serial_8250.h>
+#include <linux/mbus.h>
+#include <linux/mv643xx_eth.h>
+#include <asm/page.h>
+#include <asm/timex.h>
+#include <asm/mach/map.h>
+#include <asm/mach/time.h>
+#include <asm/arch/loki.h>
+#include <asm/plat-orion/orion_nand.h>
+#include <asm/plat-orion/time.h>
+#include "common.h"
+
+/*****************************************************************************
+ * I/O Address Mapping
+ ****************************************************************************/
+static struct map_desc loki_io_desc[] __initdata = {
+        {
+                .virtual        = LOKI_REGS_VIRT_BASE,
+                .pfn            = __phys_to_pfn(LOKI_REGS_PHYS_BASE),
+                .length         = LOKI_REGS_SIZE,
+                .type           = MT_DEVICE,
+        },
+};
+
+void __init loki_map_io(void)
+{
+        iotable_init(loki_io_desc, ARRAY_SIZE(loki_io_desc));
+}
+
+
+/*****************************************************************************
+ * GE0
+ ****************************************************************************/
+struct mv643xx_eth_shared_platform_data loki_ge0_shared_data = {
+        .t_clk          = LOKI_TCLK,
+        .dram           = &loki_mbus_dram_info,
+};
+
+static struct resource loki_ge0_shared_resources[] = {
+        {
+                .name   = "ge0 base",
+                .start  = GE0_PHYS_BASE + 0x2000,
+                .end    = GE0_PHYS_BASE + 0x3fff,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device loki_ge0_shared = {
+        .name           = MV643XX_ETH_SHARED_NAME,
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &loki_ge0_shared_data,
+        },
+        .num_resources  = 1,
+        .resource       = loki_ge0_shared_resources,
+};
+
+static struct resource loki_ge0_resources[] = {
+        {
+                .name   = "ge0 irq",
+                .start  = IRQ_LOKI_GBE_A_INT,
+                .end    = IRQ_LOKI_GBE_A_INT,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device loki_ge0 = {
+        .name           = MV643XX_ETH_NAME,
+        .id             = 0,
+        .num_resources  = 1,
+        .resource       = loki_ge0_resources,
+};
+
+void __init loki_ge0_init(struct mv643xx_eth_platform_data *eth_data)
+{
+        eth_data->shared = &loki_ge0_shared;
+        loki_ge0.dev.platform_data = eth_data;
+
+        writel(0x00079220, GE0_VIRT_BASE + 0x20b0);
+        platform_device_register(&loki_ge0_shared);
+        platform_device_register(&loki_ge0);
+}
+
+
+/*****************************************************************************
+ * GE1
+ ****************************************************************************/
+struct mv643xx_eth_shared_platform_data loki_ge1_shared_data = {
+        .t_clk          = LOKI_TCLK,
+        .dram           = &loki_mbus_dram_info,
+};
+
+static struct resource loki_ge1_shared_resources[] = {
+        {
+                .name   = "ge1 base",
+                .start  = GE1_PHYS_BASE + 0x2000,
+                .end    = GE1_PHYS_BASE + 0x3fff,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device loki_ge1_shared = {
+        .name           = MV643XX_ETH_SHARED_NAME,
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &loki_ge1_shared_data,
+        },
+        .num_resources  = 1,
+        .resource       = loki_ge1_shared_resources,
+};
+
+static struct resource loki_ge1_resources[] = {
+        {
+                .name   = "ge1 irq",
+                .start  = IRQ_LOKI_GBE_B_INT,
+                .end    = IRQ_LOKI_GBE_B_INT,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device loki_ge1 = {
+        .name           = MV643XX_ETH_NAME,
+        .id             = 1,
+        .num_resources  = 1,
+        .resource       = loki_ge1_resources,
+};
+
+void __init loki_ge1_init(struct mv643xx_eth_platform_data *eth_data)
+{
+        eth_data->shared = &loki_ge1_shared;
+        loki_ge1.dev.platform_data = eth_data;
+
+        writel(0x00079220, GE1_VIRT_BASE + 0x20b0);
+        platform_device_register(&loki_ge1_shared);
+        platform_device_register(&loki_ge1);
+}
+
+
+/*****************************************************************************
+ * SAS/SATA
+ ****************************************************************************/
+static struct resource loki_sas_resources[] = {
+        {
+                .name   = "mvsas0 mem",
+                .start  = SAS0_PHYS_BASE,
+                .end    = SAS0_PHYS_BASE + 0x01ff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .name   = "mvsas0 irq",
+                .start  = IRQ_LOKI_SAS_A,
+                .end    = IRQ_LOKI_SAS_A,
+                .flags  = IORESOURCE_IRQ,
+        }, {
+                .name   = "mvsas1 mem",
+                .start  = SAS1_PHYS_BASE,
+                .end    = SAS1_PHYS_BASE + 0x01ff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .name   = "mvsas1 irq",
+                .start  = IRQ_LOKI_SAS_B,
+                .end    = IRQ_LOKI_SAS_B,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device loki_sas = {
+        .name           = "mvsas",
+        .id             = 0,
+        .dev            = {
+                .coherent_dma_mask      = 0xffffffff,
+        },
+        .num_resources  = ARRAY_SIZE(loki_sas_resources),
+        .resource       = loki_sas_resources,
+};
+
+void __init loki_sas_init(void)
+{
+        writel(0x8300f707, DDR_REG(0x1424));
+        platform_device_register(&loki_sas);
+}
+
+
+/*****************************************************************************
+ * UART0
+ ****************************************************************************/
+static struct plat_serial8250_port loki_uart0_data[] = {
+        {
+                .mapbase        = UART0_PHYS_BASE,
+                .membase        = (char *)UART0_VIRT_BASE,
+                .irq            = IRQ_LOKI_UART0,
+                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+                .uartclk        = LOKI_TCLK,
+        }, {
+        },
+};
+
+static struct resource loki_uart0_resources[] = {
+        {
+                .start          = UART0_PHYS_BASE,
+                .end            = UART0_PHYS_BASE + 0xff,
+                .flags          = IORESOURCE_MEM,
+        }, {
+                .start          = IRQ_LOKI_UART0,
+                .end            = IRQ_LOKI_UART0,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device loki_uart0 = {
+        .name                   = "serial8250",
+        .id                     = 0,
+        .dev                    = {
+                .platform_data  = loki_uart0_data,
+        },
+        .resource               = loki_uart0_resources,
+        .num_resources          = ARRAY_SIZE(loki_uart0_resources),
+};
+
+void __init loki_uart0_init(void)
+{
+        platform_device_register(&loki_uart0);
+}
+
+
+/*****************************************************************************
+ * UART1
+ ****************************************************************************/
+static struct plat_serial8250_port loki_uart1_data[] = {
+        {
+                .mapbase        = UART1_PHYS_BASE,
+                .membase        = (char *)UART1_VIRT_BASE,
+                .irq            = IRQ_LOKI_UART1,
+                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+                .uartclk        = LOKI_TCLK,
+        }, {
+        },
+};
+
+static struct resource loki_uart1_resources[] = {
+        {
+                .start          = UART1_PHYS_BASE,
+                .end            = UART1_PHYS_BASE + 0xff,
+                .flags          = IORESOURCE_MEM,
+        }, {
+                .start          = IRQ_LOKI_UART1,
+                .end            = IRQ_LOKI_UART1,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device loki_uart1 = {
+        .name                   = "serial8250",
+        .id                     = 1,
+        .dev                    = {
+                .platform_data  = loki_uart1_data,
+        },
+        .resource               = loki_uart1_resources,
+        .num_resources          = ARRAY_SIZE(loki_uart1_resources),
+};
+
+void __init loki_uart1_init(void)
+{
+        platform_device_register(&loki_uart1);
+}
+
+
+/*****************************************************************************
+ * Time handling
+ ****************************************************************************/
+static void loki_timer_init(void)
+{
+        orion_time_init(IRQ_LOKI_BRIDGE, LOKI_TCLK);
+}
+
+struct sys_timer loki_timer = {
+        .init = loki_timer_init,
+};
+
+
+/*****************************************************************************
+ * General
+ ****************************************************************************/
+void __init loki_init(void)
+{
+        printk(KERN_INFO "Loki ID: 88RC8480. TCLK=%d.\n", LOKI_TCLK);
+
+        loki_setup_cpu_mbus();
+}
diff --git a/arch/arm/mach-loki/common.h b/arch/arm/mach-loki/common.h
new file mode 100644
index 000000000000..26054fd0f05e
--- /dev/null
+++ b/arch/arm/mach-loki/common.h
@@ -0,0 +1,36 @@
+/*
+ * arch/arm/mach-loki/common.h
+ *
+ * Core functions for Marvell Loki (88RC8480) SoCs
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ARCH_LOKI_COMMON_H
+#define __ARCH_LOKI_COMMON_H
+
+struct mv643xx_eth_platform_data;
+
+/*
+ * Basic Loki init functions used early by machine-setup.
+ */
+void loki_map_io(void);
+void loki_init(void);
+void loki_init_irq(void);
+
+extern struct mbus_dram_target_info loki_mbus_dram_info;
+void loki_setup_cpu_mbus(void);
+void loki_setup_dev_boot_win(u32 base, u32 size);
+
+void loki_ge0_init(struct mv643xx_eth_platform_data *eth_data);
+void loki_ge1_init(struct mv643xx_eth_platform_data *eth_data);
+void loki_sas_init(void);
+void loki_uart0_init(void);
+void loki_uart1_init(void);
+
+extern struct sys_timer loki_timer;
+
+
+#endif
diff --git a/arch/arm/mach-loki/irq.c b/arch/arm/mach-loki/irq.c
new file mode 100644
index 000000000000..d839af91fe03
--- /dev/null
+++ b/arch/arm/mach-loki/irq.c
@@ -0,0 +1,21 @@
+/*
+ * arch/arm/mach-loki/irq.c
+ *
+ * Marvell Loki (88RC8480) IRQ handling.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <asm/io.h>
+#include <asm/plat-orion/irq.h>
+#include "common.h"
+
+void __init loki_init_irq(void)
+{
+        orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_OFF));
+}
diff --git a/arch/arm/mach-loki/lb88rc8480-setup.c b/arch/arm/mach-loki/lb88rc8480-setup.c
new file mode 100644
index 000000000000..d1b9e6e6253a
--- /dev/null
+++ b/arch/arm/mach-loki/lb88rc8480-setup.c
@@ -0,0 +1,100 @@
+/*
+ * arch/arm/mach-loki/lb88rc8480-setup.c
+ *
+ * Marvell LB88RC8480 Development Board Setup
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/irq.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mtd/nand.h>
+#include <linux/timer.h>
+#include <linux/ata_platform.h>
+#include <linux/mv643xx_eth.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/arch/loki.h>
+#include "common.h"
+
+#define LB88RC8480_FLASH_BOOT_CS_BASE   0xf8000000
+#define LB88RC8480_FLASH_BOOT_CS_SIZE   SZ_128M
+
+#define LB88RC8480_NOR_BOOT_BASE        0xff000000
+#define LB88RC8480_NOR_BOOT_SIZE        SZ_16M
+
+static struct mtd_partition lb88rc8480_boot_flash_parts[] = {
+        {
+                .name   = "kernel",
+                .offset = 0,
+                .size   = SZ_2M,
+        }, {
+                .name   = "root-fs",
+                .offset = SZ_2M,
+                .size   = (SZ_8M + SZ_4M + SZ_1M),
+        }, {
+                .name   = "u-boot",
+                .offset = (SZ_8M + SZ_4M + SZ_2M + SZ_1M),
+                .size   = SZ_1M,
+        },
+};
+
+static struct physmap_flash_data lb88rc8480_boot_flash_data = {
+        .parts          = lb88rc8480_boot_flash_parts,
+        .nr_parts       = ARRAY_SIZE(lb88rc8480_boot_flash_parts),
+        .width          = 1,    /* 8 bit bus width */
+};
+
+static struct resource lb88rc8480_boot_flash_resource = {
+        .flags  = IORESOURCE_MEM,
+        .start  = LB88RC8480_NOR_BOOT_BASE,
+        .end    = LB88RC8480_NOR_BOOT_BASE + LB88RC8480_NOR_BOOT_SIZE - 1,
+};
+
+static struct platform_device lb88rc8480_boot_flash = {
+        .name   = "physmap-flash",
+        .id     = 0,
+        .dev    = {
+                .platform_data  = &lb88rc8480_boot_flash_data,
+        },
+        .num_resources  = 1,
+        .resource       = &lb88rc8480_boot_flash_resource,
+};
+
+static struct mv643xx_eth_platform_data lb88rc8480_ge0_data = {
+        .phy_addr       = 1,
+        .mac_addr       = { 0x00, 0x50, 0x43, 0x11, 0x22, 0x33 },
+};
+
+static void __init lb88rc8480_init(void)
+{
+        /*
+         * Basic setup. Needs to be called early.
+         */
+        loki_init();
+
+        loki_ge0_init(&lb88rc8480_ge0_data);
+        loki_sas_init();
+        loki_uart0_init();
+        loki_uart1_init();
+
+        loki_setup_dev_boot_win(LB88RC8480_FLASH_BOOT_CS_BASE,
+                                LB88RC8480_FLASH_BOOT_CS_SIZE);
+        platform_device_register(&lb88rc8480_boot_flash);
+}
+
+MACHINE_START(LB88RC8480, "Marvell LB88RC8480 Development Board")
+        /* Maintainer: Ke Wei <kewei@marvell.com> */
+        .phys_io        = LOKI_REGS_PHYS_BASE,
+        .io_pg_offst    = ((LOKI_REGS_VIRT_BASE) >> 18) & 0xfffc,
+        .boot_params    = 0x00000100,
+        .init_machine   = lb88rc8480_init,
+        .map_io         = loki_map_io,
+        .init_irq       = loki_init_irq,
+        .timer          = &loki_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mv78xx0/Kconfig b/arch/arm/mach-mv78xx0/Kconfig
new file mode 100644
index 000000000000..d83cb86837db
--- /dev/null
+++ b/arch/arm/mach-mv78xx0/Kconfig
@@ -0,0 +1,13 @@
+if ARCH_MV78XX0
+
+menu "Marvell MV78xx0 Implementations"
+
+config MACH_DB78X00_BP
+        bool "Marvell DB-78x00-BP Development Board"
+        help
+          Say 'Y' here if you want your kernel to support the
+          Marvell DB-78x00-BP Development Board.
+
+endmenu
+
+endif
diff --git a/arch/arm/mach-mv78xx0/Makefile b/arch/arm/mach-mv78xx0/Makefile
new file mode 100644
index 000000000000..ec16c05c3b1b
--- /dev/null
+++ b/arch/arm/mach-mv78xx0/Makefile
@@ -0,0 +1,2 @@
+obj-y                           += common.o addr-map.o irq.o pcie.o
+obj-$(CONFIG_MACH_DB78X00_BP)   += db78x00-bp-setup.o
diff --git a/arch/arm/mach-mv78xx0/Makefile.boot b/arch/arm/mach-mv78xx0/Makefile.boot
new file mode 100644
index 000000000000..67039c3e0c48
--- /dev/null
+++ b/arch/arm/mach-mv78xx0/Makefile.boot
@@ -0,0 +1,3 @@
+   zreladdr-y   := 0x00008000
+params_phys-y   := 0x00000100
+initrd_phys-y   := 0x00800000
diff --git a/arch/arm/mach-mv78xx0/addr-map.c b/arch/arm/mach-mv78xx0/addr-map.c
new file mode 100644
index 000000000000..4004b672a2eb
--- /dev/null
+++ b/arch/arm/mach-mv78xx0/addr-map.c
@@ -0,0 +1,156 @@
+/*
+ * arch/arm/mach-mv78xx0/addr-map.c
+ *
+ * Address map functions for Marvell MV78xx0 SoCs
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mbus.h>
+#include <asm/io.h>
+#include "common.h"
+
+/*
+ * Generic Address Decode Windows bit settings
+ */
+#define TARGET_DDR              0
+#define TARGET_DEV_BUS          1
+#define TARGET_PCIE0            4
+#define TARGET_PCIE1            8
+#define TARGET_PCIE(i)          ((i) ? TARGET_PCIE1 : TARGET_PCIE0)
+#define ATTR_DEV_SPI_ROM        0x1f
+#define ATTR_DEV_BOOT           0x2f
+#define ATTR_DEV_CS3            0x37
+#define ATTR_DEV_CS2            0x3b
+#define ATTR_DEV_CS1            0x3d
+#define ATTR_DEV_CS0            0x3e
+#define ATTR_PCIE_IO(l)         (0xf0 & ~(0x10 << (l)))
+#define ATTR_PCIE_MEM(l)        (0xf8 & ~(0x10 << (l)))
+
+/*
+ * Helpers to get DDR bank info
+ */
+#define DDR_BASE_CS_OFF(n)      (0x0000 + ((n) << 3))
+#define DDR_SIZE_CS_OFF(n)      (0x0004 + ((n) << 3))
+
+/*
+ * CPU Address Decode Windows registers
+ */
+#define WIN0_OFF(n)             (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4))
+#define WIN8_OFF(n)             (BRIDGE_VIRT_BASE + 0x0900 + (((n) - 8) << 4))
+#define WIN_CTRL_OFF            0x0000
+#define WIN_BASE_OFF            0x0004
+#define WIN_REMAP_LO_OFF        0x0008
+#define WIN_REMAP_HI_OFF        0x000c
+
+
+struct mbus_dram_target_info mv78xx0_mbus_dram_info;
+
+static void __init __iomem *win_cfg_base(int win)
+{
+        /*
+         * Find the control register base address for this window.
+         *
+         * BRIDGE_VIRT_BASE points to the right (CPU0's or CPU1's)
+         * MBUS bridge depending on which CPU core we're running on,
+         * so we don't need to take that into account here.
+         */
+
+        return (void __iomem *)((win < 8) ? WIN0_OFF(win) : WIN8_OFF(win));
+}
+
+static int __init cpu_win_can_remap(int win)
+{
+        if (win < 8)
+                return 1;
+
+        return 0;
+}
+
+static void __init setup_cpu_win(int win, u32 base, u32 size,
+                                 u8 target, u8 attr, int remap)
+{
+        void __iomem *addr = win_cfg_base(win);
+        u32 ctrl;
+
+        base &= 0xffff0000;
+        ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1;
+
+        writel(base, addr + WIN_BASE_OFF);
+        writel(ctrl, addr + WIN_CTRL_OFF);
+        if (cpu_win_can_remap(win)) {
+                if (remap < 0)
+                        remap = base;
+
+                writel(remap & 0xffff0000, addr + WIN_REMAP_LO_OFF);
+                writel(0, addr + WIN_REMAP_HI_OFF);
+        }
+}
+
+void __init mv78xx0_setup_cpu_mbus(void)
+{
+        void __iomem *addr;
+        int i;
+        int cs;
+
+        /*
+         * First, disable and clear windows.
+         */
+        for (i = 0; i < 14; i++) {
+                addr = win_cfg_base(i);
+
+                writel(0, addr + WIN_BASE_OFF);
+                writel(0, addr + WIN_CTRL_OFF);
+                if (cpu_win_can_remap(i)) {
+                        writel(0, addr + WIN_REMAP_LO_OFF);
+                        writel(0, addr + WIN_REMAP_HI_OFF);
+                }
+        }
+
+        /*
+         * Setup MBUS dram target info.
+         */
+        mv78xx0_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
+
+        if (mv78xx0_core_index() == 0)
+                addr = (void __iomem *)DDR_WINDOW_CPU0_BASE;
+        else
+                addr = (void __iomem *)DDR_WINDOW_CPU1_BASE;
+
+        for (i = 0, cs = 0; i < 4; i++) {
+                u32 base = readl(addr + DDR_BASE_CS_OFF(i));
+                u32 size = readl(addr + DDR_SIZE_CS_OFF(i));
+
+                /*
+                 * Chip select enabled?
+                 */
+                if (size & 1) {
+                        struct mbus_dram_window *w;
+
+                        w = &mv78xx0_mbus_dram_info.cs[cs++];
+                        w->cs_index = i;
+                        w->mbus_attr = 0xf & ~(1 << i);
+                        w->base = base & 0xffff0000;
+                        w->size = (size | 0x0000ffff) + 1;
+                }
+        }
+        mv78xx0_mbus_dram_info.num_cs = cs;
+}
+
+void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size,
+                                      int maj, int min)
+{
+        setup_cpu_win(window, base, size, TARGET_PCIE(maj),
+                      ATTR_PCIE_IO(min), -1);
+}
+
+void __init mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size,
+                                       int maj, int min)
+{
+        setup_cpu_win(window, base, size, TARGET_PCIE(maj),
+                      ATTR_PCIE_MEM(min), -1);
+}
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
new file mode 100644
index 000000000000..d27b83b7bf62
--- /dev/null
+++ b/arch/arm/mach-mv78xx0/common.c
@@ -0,0 +1,754 @@
+/*
+ * arch/arm/mach-mv78xx0/common.c
+ *
+ * Core functions for Marvell MV78xx0 SoCs
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/serial_8250.h>
+#include <linux/mbus.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/ata_platform.h>
+#include <asm/mach/map.h>
+#include <asm/mach/time.h>
+#include <asm/arch/mv78xx0.h>
+#include <asm/plat-orion/cache-feroceon-l2.h>
+#include <asm/plat-orion/ehci-orion.h>
+#include <asm/plat-orion/orion_nand.h>
+#include <asm/plat-orion/time.h>
+#include "common.h"
+
+
+/*****************************************************************************
+ * Common bits
+ ****************************************************************************/
+int mv78xx0_core_index(void)
+{
+        u32 extra;
+
+        /*
+         * Read Extra Features register.
+         */
+        __asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (extra));
+
+        return !!(extra & 0x00004000);
+}
+
+static int get_hclk(void)
+{
+        int hclk;
+
+        /*
+         * HCLK tick rate is configured by DEV_D[7:5] pins.
+         */
+        switch ((readl(SAMPLE_AT_RESET_LOW) >> 5) & 7) {
+        case 0:
+                hclk = 166666667;
+                break;
+        case 1:
+                hclk = 200000000;
+                break;
+        case 2:
+                hclk = 266666667;
+                break;
+        case 3:
+                hclk = 333333333;
+                break;
+        case 4:
+                hclk = 400000000;
+                break;
+        default:
+                panic("unknown HCLK PLL setting: %.8x\n",
+                        readl(SAMPLE_AT_RESET_LOW));
+        }
+
+        return hclk;
+}
+
+static void get_pclk_l2clk(int hclk, int core_index, int *pclk, int *l2clk)
+{
+        u32 cfg;
+
+        /*
+         * Core #0 PCLK/L2CLK is configured by bits [13:8], core #1
+         * PCLK/L2CLK by bits [19:14].
+         */
+        if (core_index == 0) {
+                cfg = (readl(SAMPLE_AT_RESET_LOW) >> 8) & 0x3f;
+        } else {
+                cfg = (readl(SAMPLE_AT_RESET_LOW) >> 14) & 0x3f;
+        }
+
+        /*
+         * Bits [11:8] ([17:14] for core #1) configure the PCLK:HCLK
+         * ratio (1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6).
+         */
+        *pclk = ((u64)hclk * (2 + (cfg & 0xf))) >> 1;
+
+        /*
+         * Bits [13:12] ([19:18] for core #1) configure the PCLK:L2CLK
+         * ratio (1, 2, 3).
+         */
+        *l2clk = *pclk / (((cfg >> 4) & 3) + 1);
+}
+
+static int get_tclk(void)
+{
+        int tclk;
+
+        /*
+         * TCLK tick rate is configured by DEV_A[2:0] strap pins.
+         */
+        switch ((readl(SAMPLE_AT_RESET_HIGH) >> 6) & 7) {
+        case 1:
+                tclk = 166666667;
+                break;
+        case 3:
+                tclk = 200000000;
+                break;
+        default:
+                panic("unknown TCLK PLL setting: %.8x\n",
+                        readl(SAMPLE_AT_RESET_HIGH));
+        }
+
+        return tclk;
+}
+
+
+/*****************************************************************************
+ * I/O Address Mapping
+ ****************************************************************************/
+static struct map_desc mv78xx0_io_desc[] __initdata = {
+        {
+                .virtual        = MV78XX0_CORE_REGS_VIRT_BASE,
+                .pfn            = 0,
+                .length         = MV78XX0_CORE_REGS_SIZE,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = MV78XX0_PCIE_IO_VIRT_BASE(0),
+                .pfn            = __phys_to_pfn(MV78XX0_PCIE_IO_PHYS_BASE(0)),
+                .length         = MV78XX0_PCIE_IO_SIZE * 8,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = MV78XX0_REGS_VIRT_BASE,
+                .pfn            = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE),
+                .length         = MV78XX0_REGS_SIZE,
+                .type           = MT_DEVICE,
+        },
+};
+
+void __init mv78xx0_map_io(void)
+{
+        unsigned long phys;
+
+        /*
+         * Map the right set of per-core registers depending on
+         * which core we are running on.
+         */
+        if (mv78xx0_core_index() == 0) {
+                phys = MV78XX0_CORE0_REGS_PHYS_BASE;
+        } else {
+                phys = MV78XX0_CORE1_REGS_PHYS_BASE;
+        }
+        mv78xx0_io_desc[0].pfn = __phys_to_pfn(phys);
+
+        iotable_init(mv78xx0_io_desc, ARRAY_SIZE(mv78xx0_io_desc));
+}
+
+
+/*****************************************************************************
+ * EHCI
+ ****************************************************************************/
+static struct orion_ehci_data mv78xx0_ehci_data = {
+        .dram           = &mv78xx0_mbus_dram_info,
+};
+
+static u64 ehci_dmamask = 0xffffffffUL;
+
+
+/*****************************************************************************
+ * EHCI0
+ ****************************************************************************/
+static struct resource mv78xx0_ehci0_resources[] = {
+        {
+                .start  = USB0_PHYS_BASE,
+                .end    = USB0_PHYS_BASE + 0x0fff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = IRQ_MV78XX0_USB_0,
+                .end    = IRQ_MV78XX0_USB_0,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mv78xx0_ehci0 = {
+        .name           = "orion-ehci",
+        .id             = 0,
+        .dev            = {
+                .dma_mask               = &ehci_dmamask,
+                .coherent_dma_mask      = 0xffffffff,
+                .platform_data          = &mv78xx0_ehci_data,
+        },
+        .resource       = mv78xx0_ehci0_resources,
+        .num_resources  = ARRAY_SIZE(mv78xx0_ehci0_resources),
+};
+
+void __init mv78xx0_ehci0_init(void)
+{
+        platform_device_register(&mv78xx0_ehci0);
+}
+
+
+/*****************************************************************************
+ * EHCI1
+ ****************************************************************************/
+static struct resource mv78xx0_ehci1_resources[] = {
+        {
+                .start  = USB1_PHYS_BASE,
+                .end    = USB1_PHYS_BASE + 0x0fff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = IRQ_MV78XX0_USB_1,
+                .end    = IRQ_MV78XX0_USB_1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mv78xx0_ehci1 = {
+        .name           = "orion-ehci",
+        .id             = 1,
+        .dev            = {
+                .dma_mask               = &ehci_dmamask,
+                .coherent_dma_mask      = 0xffffffff,
+                .platform_data          = &mv78xx0_ehci_data,
+        },
+        .resource       = mv78xx0_ehci1_resources,
+        .num_resources  = ARRAY_SIZE(mv78xx0_ehci1_resources),
+};
+
+void __init mv78xx0_ehci1_init(void)
+{
+        platform_device_register(&mv78xx0_ehci1);
+}
+
+
+/*****************************************************************************
+ * EHCI2
+ ****************************************************************************/
+static struct resource mv78xx0_ehci2_resources[] = {
+        {
+                .start  = USB2_PHYS_BASE,
+                .end    = USB2_PHYS_BASE + 0x0fff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = IRQ_MV78XX0_USB_2,
+                .end    = IRQ_MV78XX0_USB_2,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mv78xx0_ehci2 = {
+        .name           = "orion-ehci",
+        .id             = 2,
+        .dev            = {
+                .dma_mask               = &ehci_dmamask,
+                .coherent_dma_mask      = 0xffffffff,
+                .platform_data          = &mv78xx0_ehci_data,
+        },
+        .resource       = mv78xx0_ehci2_resources,
+        .num_resources  = ARRAY_SIZE(mv78xx0_ehci2_resources),
+};
+
+void __init mv78xx0_ehci2_init(void)
+{
+        platform_device_register(&mv78xx0_ehci2);
+}
+
+
+/*****************************************************************************
+ * GE00
+ ****************************************************************************/
+struct mv643xx_eth_shared_platform_data mv78xx0_ge00_shared_data = {
+        .t_clk          = 0,
+        .dram           = &mv78xx0_mbus_dram_info,
+};
+
+static struct resource mv78xx0_ge00_shared_resources[] = {
+        {
+                .name   = "ge00 base",
+                .start  = GE00_PHYS_BASE + 0x2000,
+                .end    = GE00_PHYS_BASE + 0x3fff,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device mv78xx0_ge00_shared = {
+        .name           = MV643XX_ETH_SHARED_NAME,
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &mv78xx0_ge00_shared_data,
+        },
+        .num_resources  = 1,
+        .resource       = mv78xx0_ge00_shared_resources,
+};
+
+static struct resource mv78xx0_ge00_resources[] = {
+        {
+                .name   = "ge00 irq",
+                .start  = IRQ_MV78XX0_GE00_SUM,
+                .end    = IRQ_MV78XX0_GE00_SUM,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mv78xx0_ge00 = {
+        .name           = MV643XX_ETH_NAME,
+        .id             = 0,
+        .num_resources  = 1,
+        .resource       = mv78xx0_ge00_resources,
+};
+
+void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data)
+{
+        eth_data->shared = &mv78xx0_ge00_shared;
+        mv78xx0_ge00.dev.platform_data = eth_data;
+
+        platform_device_register(&mv78xx0_ge00_shared);
+        platform_device_register(&mv78xx0_ge00);
+}
+
+
+/*****************************************************************************
+ * GE01
+ ****************************************************************************/
+struct mv643xx_eth_shared_platform_data mv78xx0_ge01_shared_data = {
+        .t_clk          = 0,
+        .dram           = &mv78xx0_mbus_dram_info,
+};
+
+static struct resource mv78xx0_ge01_shared_resources[] = {
+        {
+                .name   = "ge01 base",
+                .start  = GE01_PHYS_BASE + 0x2000,
+                .end    = GE01_PHYS_BASE + 0x3fff,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device mv78xx0_ge01_shared = {
+        .name           = MV643XX_ETH_SHARED_NAME,
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &mv78xx0_ge01_shared_data,
+        },
+        .num_resources  = 1,
+        .resource       = mv78xx0_ge01_shared_resources,
+};
+
+static struct resource mv78xx0_ge01_resources[] = {
+        {
+                .name   = "ge01 irq",
+                .start  = IRQ_MV78XX0_GE01_SUM,
+                .end    = IRQ_MV78XX0_GE01_SUM,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mv78xx0_ge01 = {
+        .name           = MV643XX_ETH_NAME,
+        .id             = 1,
+        .num_resources  = 1,
+        .resource       = mv78xx0_ge01_resources,
+};
+
+void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data)
+{
+        eth_data->shared = &mv78xx0_ge01_shared;
+        eth_data->shared_smi = &mv78xx0_ge00_shared;
+        mv78xx0_ge01.dev.platform_data = eth_data;
+
+        platform_device_register(&mv78xx0_ge01_shared);
+        platform_device_register(&mv78xx0_ge01);
+}
+
+
+/*****************************************************************************
+ * GE10
+ ****************************************************************************/
+struct mv643xx_eth_shared_platform_data mv78xx0_ge10_shared_data = {
+        .t_clk          = 0,
+        .dram           = &mv78xx0_mbus_dram_info,
+};
+
+static struct resource mv78xx0_ge10_shared_resources[] = {
+        {
+                .name   = "ge10 base",
+                .start  = GE10_PHYS_BASE + 0x2000,
+                .end    = GE10_PHYS_BASE + 0x3fff,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device mv78xx0_ge10_shared = {
+        .name           = MV643XX_ETH_SHARED_NAME,
+        .id             = 2,
+        .dev            = {
+                .platform_data  = &mv78xx0_ge10_shared_data,
+        },
+        .num_resources  = 1,
+        .resource       = mv78xx0_ge10_shared_resources,
+};
+
+static struct resource mv78xx0_ge10_resources[] = {
+        {
+                .name   = "ge10 irq",
+                .start  = IRQ_MV78XX0_GE10_SUM,
+                .end    = IRQ_MV78XX0_GE10_SUM,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mv78xx0_ge10 = {
+        .name           = MV643XX_ETH_NAME,
+        .id             = 2,
+        .num_resources  = 1,
+        .resource       = mv78xx0_ge10_resources,
+};
+
+void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data)
+{
+        eth_data->shared = &mv78xx0_ge10_shared;
+        eth_data->shared_smi = &mv78xx0_ge00_shared;
+        mv78xx0_ge10.dev.platform_data = eth_data;
+
+        platform_device_register(&mv78xx0_ge10_shared);
+        platform_device_register(&mv78xx0_ge10);
+}
+
+
+/*****************************************************************************
+ * GE11
+ ****************************************************************************/
+struct mv643xx_eth_shared_platform_data mv78xx0_ge11_shared_data = {
+        .t_clk          = 0,
+        .dram           = &mv78xx0_mbus_dram_info,
+};
+
+static struct resource mv78xx0_ge11_shared_resources[] = {
+        {
+                .name   = "ge11 base",
+                .start  = GE11_PHYS_BASE + 0x2000,
+                .end    = GE11_PHYS_BASE + 0x3fff,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device mv78xx0_ge11_shared = {
+        .name           = MV643XX_ETH_SHARED_NAME,
+        .id             = 3,
+        .dev            = {
+                .platform_data  = &mv78xx0_ge11_shared_data,
+        },
+        .num_resources  = 1,
+        .resource       = mv78xx0_ge11_shared_resources,
+};
+
+static struct resource mv78xx0_ge11_resources[] = {
+        {
+                .name   = "ge11 irq",
+                .start  = IRQ_MV78XX0_GE11_SUM,
+                .end    = IRQ_MV78XX0_GE11_SUM,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mv78xx0_ge11 = {
+        .name           = MV643XX_ETH_NAME,
+        .id             = 3,
+        .num_resources  = 1,
+        .resource       = mv78xx0_ge11_resources,
+};
+
+void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data)
+{
+        eth_data->shared = &mv78xx0_ge11_shared;
+        eth_data->shared_smi = &mv78xx0_ge00_shared;
+        mv78xx0_ge11.dev.platform_data = eth_data;
+
+        platform_device_register(&mv78xx0_ge11_shared);
+        platform_device_register(&mv78xx0_ge11);
+}
+
+
+/*****************************************************************************
+ * SATA
+ ****************************************************************************/
+static struct resource mv78xx0_sata_resources[] = {
+        {
+                .name   = "sata base",
+                .start  = SATA_PHYS_BASE,
+                .end    = SATA_PHYS_BASE + 0x5000 - 1,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .name   = "sata irq",
+                .start  = IRQ_MV78XX0_SATA,
+                .end    = IRQ_MV78XX0_SATA,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mv78xx0_sata = {
+        .name           = "sata_mv",
+        .id             = 0,
+        .dev            = {
+                .coherent_dma_mask      = 0xffffffff,
+        },
+        .num_resources  = ARRAY_SIZE(mv78xx0_sata_resources),
+        .resource       = mv78xx0_sata_resources,
+};
+
+void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data)
+{
+        sata_data->dram = &mv78xx0_mbus_dram_info;
+        mv78xx0_sata.dev.platform_data = sata_data;
+        platform_device_register(&mv78xx0_sata);
+}
+
+
+/*****************************************************************************
+ * UART0
+ ****************************************************************************/
+static struct plat_serial8250_port mv78xx0_uart0_data[] = {
+        {
+                .mapbase        = UART0_PHYS_BASE,
+                .membase        = (char *)UART0_VIRT_BASE,
+                .irq            = IRQ_MV78XX0_UART_0,
+                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+                .uartclk        = 0,
+        }, {
+        },
+};
+
+static struct resource mv78xx0_uart0_resources[] = {
+        {
+                .start          = UART0_PHYS_BASE,
+                .end            = UART0_PHYS_BASE + 0xff,
+                .flags          = IORESOURCE_MEM,
+        }, {
+                .start          = IRQ_MV78XX0_UART_0,
+                .end            = IRQ_MV78XX0_UART_0,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mv78xx0_uart0 = {
+        .name                   = "serial8250",
+        .id                     = 0,
+        .dev                    = {
+                .platform_data  = mv78xx0_uart0_data,
+        },
+        .resource               = mv78xx0_uart0_resources,
+        .num_resources          = ARRAY_SIZE(mv78xx0_uart0_resources),
+};
+
+void __init mv78xx0_uart0_init(void)
+{
+        platform_device_register(&mv78xx0_uart0);
+}
+
+
+/*****************************************************************************
+ * UART1
+ ****************************************************************************/
+static struct plat_serial8250_port mv78xx0_uart1_data[] = {
+        {
+                .mapbase        = UART1_PHYS_BASE,
+                .membase        = (char *)UART1_VIRT_BASE,
+                .irq            = IRQ_MV78XX0_UART_1,
+                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+                .uartclk        = 0,
+        }, {
+        },
+};
+
+static struct resource mv78xx0_uart1_resources[] = {
+        {
+                .start          = UART1_PHYS_BASE,
+                .end            = UART1_PHYS_BASE + 0xff,
+                .flags          = IORESOURCE_MEM,
+        }, {
+                .start          = IRQ_MV78XX0_UART_1,
+                .end            = IRQ_MV78XX0_UART_1,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mv78xx0_uart1 = {
+        .name                   = "serial8250",
+        .id                     = 1,
+        .dev                    = {
+                .platform_data  = mv78xx0_uart1_data,
+        },
+        .resource               = mv78xx0_uart1_resources,
+        .num_resources          = ARRAY_SIZE(mv78xx0_uart1_resources),
+};
+
+void __init mv78xx0_uart1_init(void)
+{
+        platform_device_register(&mv78xx0_uart1);
+}
+
+
+/*****************************************************************************
+ * UART2
+ ****************************************************************************/
+static struct plat_serial8250_port mv78xx0_uart2_data[] = {
+        {
+                .mapbase        = UART2_PHYS_BASE,
+                .membase        = (char *)UART2_VIRT_BASE,
+                .irq            = IRQ_MV78XX0_UART_2,
+                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+                .uartclk        = 0,
+        }, {
+        },
+};
+
+static struct resource mv78xx0_uart2_resources[] = {
+        {
+                .start          = UART2_PHYS_BASE,
+                .end            = UART2_PHYS_BASE + 0xff,
+                .flags          = IORESOURCE_MEM,
+        }, {
+                .start          = IRQ_MV78XX0_UART_2,
+                .end            = IRQ_MV78XX0_UART_2,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mv78xx0_uart2 = {
+        .name                   = "serial8250",
+        .id                     = 2,
+        .dev                    = {
+                .platform_data  = mv78xx0_uart2_data,
+        },
+        .resource               = mv78xx0_uart2_resources,
+        .num_resources          = ARRAY_SIZE(mv78xx0_uart2_resources),
+};
+
+void __init mv78xx0_uart2_init(void)
+{
+        platform_device_register(&mv78xx0_uart2);
+}
+
+
+/*****************************************************************************
+ * UART3
+ ****************************************************************************/
+static struct plat_serial8250_port mv78xx0_uart3_data[] = {
+        {
+                .mapbase        = UART3_PHYS_BASE,
+                .membase        = (char *)UART3_VIRT_BASE,
+                .irq            = IRQ_MV78XX0_UART_3,
+                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+                .uartclk        = 0,
+        }, {
+        },
+};
+
+static struct resource mv78xx0_uart3_resources[] = {
+        {
+                .start          = UART3_PHYS_BASE,
+                .end            = UART3_PHYS_BASE + 0xff,
+                .flags          = IORESOURCE_MEM,
+        }, {
+                .start          = IRQ_MV78XX0_UART_3,
+                .end            = IRQ_MV78XX0_UART_3,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mv78xx0_uart3 = {
+        .name                   = "serial8250",
+        .id                     = 3,
+        .dev                    = {
+                .platform_data  = mv78xx0_uart3_data,
+        },
+        .resource               = mv78xx0_uart3_resources,
+        .num_resources          = ARRAY_SIZE(mv78xx0_uart3_resources),
+};
+
+void __init mv78xx0_uart3_init(void)
+{
+        platform_device_register(&mv78xx0_uart3);
+}
+
+
+/*****************************************************************************
+ * Time handling
+ ****************************************************************************/
+static void mv78xx0_timer_init(void)
+{
+        orion_time_init(IRQ_MV78XX0_TIMER_1, get_tclk());
+}
+
+struct sys_timer mv78xx0_timer = {
+        .init = mv78xx0_timer_init,
+};
+
+
+/*****************************************************************************
+ * General
+ ****************************************************************************/
+static int __init is_l2_writethrough(void)
+{
+        return !!(readl(CPU_CONTROL) & L2_WRITETHROUGH);
+}
+
+void __init mv78xx0_init(void)
+{
+        int core_index;
+        int hclk;
+        int pclk;
+        int l2clk;
+        int tclk;
+
+        core_index = mv78xx0_core_index();
+        hclk = get_hclk();
+        get_pclk_l2clk(hclk, core_index, &pclk, &l2clk);
+        tclk = get_tclk();
+
+        printk(KERN_INFO "MV78xx0 core #%d, ", core_index);
+        printk("PCLK = %dMHz, ", (pclk + 499999) / 1000000);
+        printk("L2 = %dMHz, ", (l2clk + 499999) / 1000000);
+        printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000);
+        printk("TCLK = %dMHz\n", (tclk + 499999) / 1000000);
+
+        mv78xx0_setup_cpu_mbus();
+
+#ifdef CONFIG_CACHE_FEROCEON_L2
+        feroceon_l2_init(is_l2_writethrough());
+#endif
+
+        mv78xx0_ge00_shared_data.t_clk = tclk;
+        mv78xx0_ge01_shared_data.t_clk = tclk;
+        mv78xx0_ge10_shared_data.t_clk = tclk;
+        mv78xx0_ge11_shared_data.t_clk = tclk;
+        mv78xx0_uart0_data[0].uartclk = tclk;
+        mv78xx0_uart1_data[0].uartclk = tclk;
+        mv78xx0_uart2_data[0].uartclk = tclk;
+        mv78xx0_uart3_data[0].uartclk = tclk;
+}
diff --git a/arch/arm/mach-mv78xx0/common.h b/arch/arm/mach-mv78xx0/common.h
new file mode 100644
index 000000000000..78af5de319dd
--- /dev/null
+++ b/arch/arm/mach-mv78xx0/common.h
@@ -0,0 +1,49 @@
+/*
+ * arch/arm/mach-mv78xx0/common.h
+ *
+ * Core functions for Marvell MV78xx0 SoCs
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ARCH_MV78XX0_COMMON_H
+#define __ARCH_MV78XX0_COMMON_H
+
+struct mv643xx_eth_platform_data;
+struct mv_sata_platform_data;
+
+/*
+ * Basic MV78xx0 init functions used early by machine-setup.
+ */
+int mv78xx0_core_index(void);
+void mv78xx0_map_io(void);
+void mv78xx0_init(void);
+void mv78xx0_init_irq(void);
+
+extern struct mbus_dram_target_info mv78xx0_mbus_dram_info;
+void mv78xx0_setup_cpu_mbus(void);
+void mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size,
+                               int maj, int min);
+void mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size,
+                                int maj, int min);
+
+void mv78xx0_ehci0_init(void);
+void mv78xx0_ehci1_init(void);
+void mv78xx0_ehci2_init(void);
+void mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data);
+void mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data);
+void mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data);
+void mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data);
+void mv78xx0_pcie_init(int init_port0, int init_port1);
+void mv78xx0_sata_init(struct mv_sata_platform_data *sata_data);
+void mv78xx0_uart0_init(void);
+void mv78xx0_uart1_init(void);
+void mv78xx0_uart2_init(void);
+void mv78xx0_uart3_init(void);
+
+extern struct sys_timer mv78xx0_timer;
+
+
+#endif
diff --git a/arch/arm/mach-mv78xx0/db78x00-bp-setup.c b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c
new file mode 100644
index 000000000000..0c93d19193df
--- /dev/null
+++ b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c
@@ -0,0 +1,94 @@
+/*
+ * arch/arm/mach-mv78xx0/db78x00-bp-setup.c
+ *
+ * Marvell DB-78x00-BP Development Board Setup
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/ata_platform.h>
+#include <linux/mv643xx_eth.h>
+#include <asm/arch/mv78xx0.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include "common.h"
+
+static struct mv643xx_eth_platform_data db78x00_ge00_data = {
+        .phy_addr       = 8,
+};
+
+static struct mv643xx_eth_platform_data db78x00_ge01_data = {
+        .phy_addr       = 9,
+};
+
+static struct mv643xx_eth_platform_data db78x00_ge10_data = {
+        .phy_addr       = -1,
+};
+
+static struct mv643xx_eth_platform_data db78x00_ge11_data = {
+        .phy_addr       = -1,
+};
+
+static struct mv_sata_platform_data db78x00_sata_data = {
+        .n_ports        = 2,
+};
+
+static void __init db78x00_init(void)
+{
+        /*
+         * Basic MV78xx0 setup. Needs to be called early.
+         */
+        mv78xx0_init();
+
+        /*
+         * Partition on-chip peripherals between the two CPU cores.
+         */
+        if (mv78xx0_core_index() == 0) {
+                mv78xx0_ehci0_init();
+                mv78xx0_ehci1_init();
+                mv78xx0_ehci2_init();
+                mv78xx0_ge00_init(&db78x00_ge00_data);
+                mv78xx0_ge01_init(&db78x00_ge01_data);
+                mv78xx0_ge10_init(&db78x00_ge10_data);
+                mv78xx0_ge11_init(&db78x00_ge11_data);
+                mv78xx0_sata_init(&db78x00_sata_data);
+                mv78xx0_uart0_init();
+                mv78xx0_uart2_init();
+        } else {
+                mv78xx0_uart1_init();
+                mv78xx0_uart3_init();
+        }
+}
+
+static int __init db78x00_pci_init(void)
+{
+        if (machine_is_db78x00_bp()) {
+                /*
+                 * Assign the x16 PCIe slot on the board to CPU core
+                 * #0, and let CPU core #1 have the four x1 slots.
+                 */
+                if (mv78xx0_core_index() == 0)
+                        mv78xx0_pcie_init(0, 1);
+                else
+                        mv78xx0_pcie_init(1, 0);
+        }
+
+        return 0;
+}
+subsys_initcall(db78x00_pci_init);
+
+MACHINE_START(DB78X00_BP, "Marvell DB-78x00-BP Development Board")
+        /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
+        .phys_io        = MV78XX0_REGS_PHYS_BASE,
+        .io_pg_offst    = ((MV78XX0_REGS_VIRT_BASE) >> 18) & 0xfffc,
+        .boot_params    = 0x00000100,
+        .init_machine   = db78x00_init,
+        .map_io         = mv78xx0_map_io,
+        .init_irq       = mv78xx0_init_irq,
+        .timer          = &mv78xx0_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mv78xx0/irq.c b/arch/arm/mach-mv78xx0/irq.c
new file mode 100644
index 000000000000..60f4ee4d4532
--- /dev/null
+++ b/arch/arm/mach-mv78xx0/irq.c
@@ -0,0 +1,22 @@
+/*
+ * arch/arm/mach-mv78xx0/irq.c
+ *
+ * MV78xx0 IRQ handling.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <asm/arch/mv78xx0.h>
+#include <asm/plat-orion/irq.h>
+#include "common.h"
+
+void __init mv78xx0_init_irq(void)
+{
+        orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
+        orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
+}
diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c
new file mode 100644
index 000000000000..b78e1443159f
--- /dev/null
+++ b/arch/arm/mach-mv78xx0/pcie.c
@@ -0,0 +1,312 @@
+/*
+ * arch/arm/mach-mv78xx0/pcie.c
+ *
+ * PCIe functions for Marvell MV78xx0 SoCs
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/mbus.h>
+#include <asm/mach/pci.h>
+#include <asm/plat-orion/pcie.h>
+#include "common.h"
+
+struct pcie_port {
+        u8                      maj;
+        u8                      min;
+        u8                      root_bus_nr;
+        void __iomem            *base;
+        spinlock_t              conf_lock;
+        char                    io_space_name[16];
+        char                    mem_space_name[16];
+        struct resource         res[2];
+};
+
+static struct pcie_port pcie_port[8];
+static int num_pcie_ports;
+static struct resource pcie_io_space;
+static struct resource pcie_mem_space;
+
+
+static void __init mv78xx0_pcie_preinit(void)
+{
+        int i;
+        u32 size_each;
+        u32 start;
+        int win;
+
+        pcie_io_space.name = "PCIe I/O Space";
+        pcie_io_space.start = MV78XX0_PCIE_IO_PHYS_BASE(0);
+        pcie_io_space.end =
+                MV78XX0_PCIE_IO_PHYS_BASE(0) + MV78XX0_PCIE_IO_SIZE * 8 - 1;
+        pcie_io_space.flags = IORESOURCE_IO;
+        if (request_resource(&iomem_resource, &pcie_io_space))
+                panic("can't allocate PCIe I/O space");
+
+        pcie_mem_space.name = "PCIe MEM Space";
+        pcie_mem_space.start = MV78XX0_PCIE_MEM_PHYS_BASE;
+        pcie_mem_space.end =
+                MV78XX0_PCIE_MEM_PHYS_BASE + MV78XX0_PCIE_MEM_SIZE - 1;
+        pcie_mem_space.flags = IORESOURCE_MEM;
+        if (request_resource(&iomem_resource, &pcie_mem_space))
+                panic("can't allocate PCIe MEM space");
+
+        for (i = 0; i < num_pcie_ports; i++) {
+                struct pcie_port *pp = pcie_port + i;
+
+                snprintf(pp->io_space_name, sizeof(pp->io_space_name),
+                        "PCIe %d.%d I/O", pp->maj, pp->min);
+                pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0;
+                pp->res[0].name = pp->io_space_name;
+                pp->res[0].start = MV78XX0_PCIE_IO_PHYS_BASE(i);
+                pp->res[0].end = pp->res[0].start + MV78XX0_PCIE_IO_SIZE - 1;
+                pp->res[0].flags = IORESOURCE_IO;
+
+                snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
+                        "PCIe %d.%d MEM", pp->maj, pp->min);
+                pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
+                pp->res[1].name = pp->mem_space_name;
+                pp->res[1].flags = IORESOURCE_MEM;
+        }
+
+        switch (num_pcie_ports) {
+        case 0:
+                size_each = 0;
+                break;
+
+        case 1:
+                size_each = 0x30000000;
+                break;
+
+        case 2 ... 3:
+                size_each = 0x10000000;
+                break;
+
+        case 4 ... 6:
+                size_each = 0x08000000;
+                break;
+
+        case 7:
+                size_each = 0x04000000;
+                break;
+
+        default:
+                panic("invalid number of PCIe ports");
+        }
+
+        start = MV78XX0_PCIE_MEM_PHYS_BASE;
+        for (i = 0; i < num_pcie_ports; i++) {
+                struct pcie_port *pp = pcie_port + i;
+
+                pp->res[1].start = start;
+                pp->res[1].end = start + size_each - 1;
+                start += size_each;
+        }
+
+        for (i = 0; i < num_pcie_ports; i++) {
+                struct pcie_port *pp = pcie_port + i;
+
+                if (request_resource(&pcie_io_space, &pp->res[0]))
+                        panic("can't allocate PCIe I/O sub-space");
+
+                if (request_resource(&pcie_mem_space, &pp->res[1]))
+                        panic("can't allocate PCIe MEM sub-space");
+        }
+
+        win = 0;
+        for (i = 0; i < num_pcie_ports; i++) {
+                struct pcie_port *pp = pcie_port + i;
+
+                mv78xx0_setup_pcie_io_win(win++, pp->res[0].start,
+                        pp->res[0].end - pp->res[0].start + 1,
+                        pp->maj, pp->min);
+
+                mv78xx0_setup_pcie_mem_win(win++, pp->res[1].start,
+                        pp->res[1].end - pp->res[1].start + 1,
+                        pp->maj, pp->min);
+        }
+}
+
+static int __init mv78xx0_pcie_setup(int nr, struct pci_sys_data *sys)
+{
+        struct pcie_port *pp;
+
+        if (nr >= num_pcie_ports)
+                return 0;
+
+        pp = &pcie_port[nr];
+        pp->root_bus_nr = sys->busnr;
+
+        /*
+         * Generic PCIe unit setup.
+         */
+        orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
+        orion_pcie_setup(pp->base, &mv78xx0_mbus_dram_info);
+
+        sys->resource[0] = &pp->res[0];
+        sys->resource[1] = &pp->res[1];
+        sys->resource[2] = NULL;
+
+        return 1;
+}
+
+static struct pcie_port *bus_to_port(int bus)
+{
+        int i;
+
+        for (i = num_pcie_ports - 1; i >= 0; i--) {
+                int rbus = pcie_port[i].root_bus_nr;
+                if (rbus != -1 && rbus <= bus)
+                        break;
+        }
+
+        return i >= 0 ? pcie_port + i : NULL;
+}
+
+static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
+{
+        /*
+         * Don't go out when trying to access nonexisting devices
+         * on the local bus.
+         */
+        if (bus == pp->root_bus_nr && dev > 1)
+                return 0;
+
+        return 1;
+}
+
+static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
+                        int size, u32 *val)
+{
+        struct pcie_port *pp = bus_to_port(bus->number);
+        unsigned long flags;
+        int ret;
+
+        if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
+                *val = 0xffffffff;
+                return PCIBIOS_DEVICE_NOT_FOUND;
+        }
+
+        spin_lock_irqsave(&pp->conf_lock, flags);
+        ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
+        spin_unlock_irqrestore(&pp->conf_lock, flags);
+
+        return ret;
+}
+
+static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
+                        int where, int size, u32 val)
+{
+        struct pcie_port *pp = bus_to_port(bus->number);
+        unsigned long flags;
+        int ret;
+
+        if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
+                return PCIBIOS_DEVICE_NOT_FOUND;
+
+        spin_lock_irqsave(&pp->conf_lock, flags);
+        ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
+        spin_unlock_irqrestore(&pp->conf_lock, flags);
+
+        return ret;
+}
+
+static struct pci_ops pcie_ops = {
+        .read = pcie_rd_conf,
+        .write = pcie_wr_conf,
+};
+
+static void __devinit rc_pci_fixup(struct pci_dev *dev)
+{
+        /*
+         * Prevent enumeration of root complex.
+         */
+        if (dev->bus->parent == NULL && dev->devfn == 0) {
+                int i;
+
+                for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
+                        dev->resource[i].start = 0;
+                        dev->resource[i].end   = 0;
+                        dev->resource[i].flags = 0;
+                }
+        }
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
+
+static struct pci_bus __init *
+mv78xx0_pcie_scan_bus(int nr, struct pci_sys_data *sys)
+{
+        struct pci_bus *bus;
+
+        if (nr < num_pcie_ports) {
+                bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
+        } else {
+                bus = NULL;
+                BUG();
+        }
+
+        return bus;
+}
+
+static int __init mv78xx0_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+        struct pcie_port *pp = bus_to_port(dev->bus->number);
+
+        return IRQ_MV78XX0_PCIE_00 + (pp->maj << 2) + pp->min;
+}
+
+static struct hw_pci mv78xx0_pci __initdata = {
+        .nr_controllers = 8,
+        .preinit        = mv78xx0_pcie_preinit,
+        .swizzle        = pci_std_swizzle,
+        .setup          = mv78xx0_pcie_setup,
+        .scan           = mv78xx0_pcie_scan_bus,
+        .map_irq        = mv78xx0_pcie_map_irq,
+};
+
+static void __init add_pcie_port(int maj, int min, unsigned long base)
+{
+        printk(KERN_INFO "MV78xx0 PCIe port %d.%d: ", maj, min);
+
+        if (orion_pcie_link_up((void __iomem *)base)) {
+                struct pcie_port *pp = &pcie_port[num_pcie_ports++];
+
+                printk("link up\n");
+
+                pp->maj = maj;
+                pp->min = min;
+                pp->root_bus_nr = -1;
+                pp->base = (void __iomem *)base;
+                spin_lock_init(&pp->conf_lock);
+                memset(pp->res, 0, sizeof(pp->res));
+        } else {
+                printk("link down, ignoring\n");
+        }
+}
+
+void __init mv78xx0_pcie_init(int init_port0, int init_port1)
+{
+        if (init_port0) {
+                add_pcie_port(0, 0, PCIE00_VIRT_BASE);
+                if (!orion_pcie_x4_mode((void __iomem *)PCIE00_VIRT_BASE)) {
+                        add_pcie_port(0, 1, PCIE01_VIRT_BASE);
+                        add_pcie_port(0, 2, PCIE02_VIRT_BASE);
+                        add_pcie_port(0, 3, PCIE03_VIRT_BASE);
+                }
+        }
+
+        if (init_port1) {
+                add_pcie_port(1, 0, PCIE10_VIRT_BASE);
+                if (!orion_pcie_x4_mode((void __iomem *)PCIE10_VIRT_BASE)) {
+                        add_pcie_port(1, 1, PCIE11_VIRT_BASE);
+                        add_pcie_port(1, 2, PCIE12_VIRT_BASE);
+                        add_pcie_port(1, 3, PCIE13_VIRT_BASE);
+                }
+        }
+
+        pci_common_init(&mv78xx0_pci);
+}
diff --git a/arch/arm/mach-mx2/Kconfig b/arch/arm/mach-mx2/Kconfig
new file mode 100644
index 000000000000..1eaa97cb716d
--- /dev/null
+++ b/arch/arm/mach-mx2/Kconfig
@@ -0,0 +1,39 @@
+comment "MX2 family CPU support"
+        depends on ARCH_MX2
+
+config MACH_MX27
+        bool "i.MX27 support"
+        depends on ARCH_MX2
+        help
+          This enables support for Freescale's MX2 based i.MX27 processor.
+
+comment "MX2 Platforms"
+        depends on ARCH_MX2
+
+config MACH_MX27ADS
+        bool "MX27ADS platform"
+        depends on MACH_MX27
+        help
+          Include support for MX27ADS platform. This includes specific
+          configurations for the board and its peripherals.
+
+config MACH_PCM038
+        bool "Phytec phyCORE-i.MX27 CPU module (pcm038)"
+        depends on MACH_MX27
+        help
+          Include support for phyCORE-i.MX27 (aka pcm038) platform. This
+          includes specific configurations for the module and its peripherals.
+
+choice
+        prompt "Baseboard"
+        depends on MACH_PCM038
+        default MACH_PCM970_BASEBOARD
+
+config MACH_PCM970_BASEBOARD
+        prompt "PHYTEC PCM970 development board"
+        bool
+        help
+          This adds board specific devices that can be found on Phytec's
+          PCM970 evaluation board.
+
+endchoice
diff --git a/arch/arm/mach-mx2/Makefile b/arch/arm/mach-mx2/Makefile
new file mode 100644
index 000000000000..382d86080e86
--- /dev/null
+++ b/arch/arm/mach-mx2/Makefile
@@ -0,0 +1,14 @@
+#
+# Makefile for the linux kernel.
+#
+
+# Object file lists.
+
+obj-y   :=  system.o generic.o devices.o serial.o
+
+obj-$(CONFIG_MACH_MX27) += cpu_imx27.o
+obj-$(CONFIG_MACH_MX27) += clock_imx27.o
+
+obj-$(CONFIG_MACH_MX27ADS) += mx27ads.o
+obj-$(CONFIG_MACH_PCM038) += pcm038.o
+obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o
diff --git a/arch/arm/mach-mx2/Makefile.boot b/arch/arm/mach-mx2/Makefile.boot
new file mode 100644
index 000000000000..696831dcd485
--- /dev/null
+++ b/arch/arm/mach-mx2/Makefile.boot
@@ -0,0 +1,3 @@
+   zreladdr-y   := 0xA0008000
+params_phys-y   := 0xA0000100
+initrd_phys-y   := 0xA0800000
diff --git a/arch/arm/mach-mx2/clock_imx27.c b/arch/arm/mach-mx2/clock_imx27.c
new file mode 100644
index 000000000000..0a29ef29c73a
--- /dev/null
+++ b/arch/arm/mach-mx2/clock_imx27.c
@@ -0,0 +1,1626 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/spinlock.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/common.h>
+#include <asm/div64.h>
+#include <asm/mach-types.h>
+
+#include "crm_regs.h"
+
+static struct clk ckil_clk;
+static struct clk mpll_clk;
+static struct clk mpll_main_clk[];
+static struct clk spll_clk;
+
+static int _clk_enable(struct clk *clk)
+{
+        unsigned long reg;
+
+        reg = __raw_readl(clk->enable_reg);
+        reg |= 1 << clk->enable_shift;
+        __raw_writel(reg, clk->enable_reg);
+
+        return 0;
+}
+
+static void _clk_disable(struct clk *clk)
+{
+        unsigned long reg;
+
+        reg = __raw_readl(clk->enable_reg);
+        reg &= ~(1 << clk->enable_shift);
+        __raw_writel(reg, clk->enable_reg);
+}
+
+static int _clk_spll_enable(struct clk *clk)
+{
+        unsigned long reg;
+
+        reg = __raw_readl(CCM_CSCR);
+        reg |= CCM_CSCR_SPEN;
+        __raw_writel(reg, CCM_CSCR);
+
+        while ((__raw_readl(CCM_SPCTL1) & CCM_SPCTL1_LF) == 0)
+                ;
+
+        return 0;
+}
+
+static void _clk_spll_disable(struct clk *clk)
+{
+        unsigned long reg;
+
+        reg = __raw_readl(CCM_CSCR);
+        reg &= ~CCM_CSCR_SPEN;
+        __raw_writel(reg, CCM_CSCR);
+}
+
+static void _clk_pccr01_enable(unsigned long mask0, unsigned long mask1)
+{
+        unsigned long reg;
+
+        reg = __raw_readl(CCM_PCCR0);
+        reg |= mask0;
+        __raw_writel(reg, CCM_PCCR0);
+
+        reg = __raw_readl(CCM_PCCR1);
+        reg |= mask1;
+        __raw_writel(reg, CCM_PCCR1);
+
+}
+
+static void _clk_pccr01_disable(unsigned long mask0, unsigned long mask1)
+{
+        unsigned long reg;
+
+        reg = __raw_readl(CCM_PCCR0);
+        reg &= ~mask0;
+        __raw_writel(reg, CCM_PCCR0);
+
+        reg = __raw_readl(CCM_PCCR1);
+        reg &= ~mask1;
+        __raw_writel(reg, CCM_PCCR1);
+}
+
+static void _clk_pccr10_enable(unsigned long mask1, unsigned long mask0)
+{
+        unsigned long reg;
+
+        reg = __raw_readl(CCM_PCCR1);
+        reg |= mask1;
+        __raw_writel(reg, CCM_PCCR1);
+
+        reg = __raw_readl(CCM_PCCR0);
+        reg |= mask0;
+        __raw_writel(reg, CCM_PCCR0);
+}
+
+static void _clk_pccr10_disable(unsigned long mask1, unsigned long mask0)
+{
+        unsigned long reg;
+
+        reg = __raw_readl(CCM_PCCR1);
+        reg &= ~mask1;
+        __raw_writel(reg, CCM_PCCR1);
+
+        reg = __raw_readl(CCM_PCCR0);
+        reg &= ~mask0;
+        __raw_writel(reg, CCM_PCCR0);
+}
+
+static int _clk_dma_enable(struct clk *clk)
+{
+        _clk_pccr01_enable(CCM_PCCR0_DMA_MASK, CCM_PCCR1_HCLK_DMA_MASK);
+
+        return 0;
+}
+
+static void _clk_dma_disable(struct clk *clk)
+{
+        _clk_pccr01_disable(CCM_PCCR0_DMA_MASK, CCM_PCCR1_HCLK_DMA_MASK);
+}
+
+static int _clk_rtic_enable(struct clk *clk)
+{
+        _clk_pccr01_enable(CCM_PCCR0_RTIC_MASK, CCM_PCCR1_HCLK_RTIC_MASK);
+
+        return 0;
+}
+
+static void _clk_rtic_disable(struct clk *clk)
+{
+        _clk_pccr01_disable(CCM_PCCR0_RTIC_MASK, CCM_PCCR1_HCLK_RTIC_MASK);
+}
+
+static int _clk_emma_enable(struct clk *clk)
+{
+        _clk_pccr01_enable(CCM_PCCR0_EMMA_MASK, CCM_PCCR1_HCLK_EMMA_MASK);
+
+        return 0;
+}
+
+static void _clk_emma_disable(struct clk *clk)
+{
+        _clk_pccr01_disable(CCM_PCCR0_EMMA_MASK, CCM_PCCR1_HCLK_EMMA_MASK);
+}
+
+static int _clk_slcdc_enable(struct clk *clk)
+{
+        _clk_pccr01_enable(CCM_PCCR0_SLCDC_MASK, CCM_PCCR1_HCLK_SLCDC_MASK);
+
+        return 0;
+}
+
+static void _clk_slcdc_disable(struct clk *clk)
+{
+        _clk_pccr01_disable(CCM_PCCR0_SLCDC_MASK, CCM_PCCR1_HCLK_SLCDC_MASK);
+}
+
+static int _clk_fec_enable(struct clk *clk)
+{
+        _clk_pccr01_enable(CCM_PCCR0_FEC_MASK, CCM_PCCR1_HCLK_FEC_MASK);
+
+        return 0;
+}
+
+static void _clk_fec_disable(struct clk *clk)
+{
+        _clk_pccr01_disable(CCM_PCCR0_FEC_MASK, CCM_PCCR1_HCLK_FEC_MASK);
+}
+
+static int _clk_vpu_enable(struct clk *clk)
+{
+        unsigned long reg;
+
+        reg = __raw_readl(CCM_PCCR1);
+        reg |= CCM_PCCR1_VPU_BAUD_MASK | CCM_PCCR1_HCLK_VPU_MASK;
+        __raw_writel(reg, CCM_PCCR1);
+
+        return 0;
+}
+
+static void _clk_vpu_disable(struct clk *clk)
+{
+        unsigned long reg;
+
+        reg = __raw_readl(CCM_PCCR1);
+        reg &= ~(CCM_PCCR1_VPU_BAUD_MASK | CCM_PCCR1_HCLK_VPU_MASK);
+        __raw_writel(reg, CCM_PCCR1);
+}
+
+static int _clk_sahara2_enable(struct clk *clk)
+{
+        _clk_pccr01_enable(CCM_PCCR0_SAHARA_MASK, CCM_PCCR1_HCLK_SAHARA_MASK);
+
+        return 0;
+}
+
+static void _clk_sahara2_disable(struct clk *clk)
+{
+        _clk_pccr01_disable(CCM_PCCR0_SAHARA_MASK, CCM_PCCR1_HCLK_SAHARA_MASK);
+}
+
+static int _clk_mstick1_enable(struct clk *clk)
+{
+        _clk_pccr10_enable(CCM_PCCR1_MSHC_BAUD_MASK, CCM_PCCR0_MSHC_MASK);
+
+        return 0;
+}
+
+static void _clk_mstick1_disable(struct clk *clk)
+{
+        _clk_pccr10_disable(CCM_PCCR1_MSHC_BAUD_MASK, CCM_PCCR0_MSHC_MASK);
+}
+
+#define CSCR() (__raw_readl(CCM_CSCR))
+#define PCDR0() (__raw_readl(CCM_PCDR0))
+#define PCDR1() (__raw_readl(CCM_PCDR1))
+
+static int _clk_cpu_set_parent(struct clk *clk, struct clk *parent)
+{
+        int cscr = CSCR();
+
+        if (clk->parent == parent)
+                return 0;
+
+        if (mx27_revision() >= CHIP_REV_2_0) {
+                if (parent == &mpll_main_clk[0]) {
+                        cscr |= CCM_CSCR_ARM_SRC;
+                } else {
+                        if (parent == &mpll_main_clk[1])
+                                cscr &= ~CCM_CSCR_ARM_SRC;
+                        else
+                                return -EINVAL;
+                }
+                __raw_writel(cscr, CCM_CSCR);
+        } else
+                return -ENODEV;
+
+        clk->parent = parent;
+        return 0;
+}
+
+static unsigned long _clk_cpu_round_rate(struct clk *clk, unsigned long rate)
+{
+        int div;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        div = parent_rate / rate;
+        if (parent_rate % rate)
+                div++;
+
+        if (div > 4)
+                div = 4;
+
+        return parent_rate / div;
+}
+
+static int _clk_cpu_set_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned int div;
+        uint32_t reg;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        div = parent_rate / rate;
+
+        if (div > 4 || div < 1 || ((parent_rate / div) != rate))
+                return -EINVAL;
+
+        div--;
+
+        reg = __raw_readl(CCM_CSCR);
+        if (mx27_revision() >= CHIP_REV_2_0) {
+                reg &= ~CCM_CSCR_ARM_MASK;
+                reg |= div << CCM_CSCR_ARM_OFFSET;
+                reg &= ~0x06;
+                __raw_writel(reg | 0x80000000, CCM_CSCR);
+        } else {
+                printk(KERN_ERR "Cant set CPU frequency!\n");
+        }
+
+        return 0;
+}
+
+static unsigned long _clk_perclkx_round_rate(struct clk *clk,
+                                             unsigned long rate)
+{
+        u32 div;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        div = parent_rate / rate;
+        if (parent_rate % rate)
+                div++;
+
+        if (div > 64)
+                div = 64;
+
+        return parent_rate / div;
+}
+
+static int _clk_perclkx_set_rate(struct clk *clk, unsigned long rate)
+{
+        u32 reg;
+        u32 div;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        if (clk->id < 0 || clk->id > 3)
+                return -EINVAL;
+
+        div = parent_rate / rate;
+        if (div > 64 || div < 1 || ((parent_rate / div) != rate))
+                return -EINVAL;
+        div--;
+
+        reg =
+            __raw_readl(CCM_PCDR1) & ~(CCM_PCDR1_PERDIV1_MASK <<
+                                       (clk->id << 3));
+        reg |= div << (clk->id << 3);
+        __raw_writel(reg, CCM_PCDR1);
+
+        return 0;
+}
+
+static unsigned long _clk_usb_recalc(struct clk *clk)
+{
+        unsigned long usb_pdf;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        usb_pdf = (CSCR() & CCM_CSCR_USB_MASK) >> CCM_CSCR_USB_OFFSET;
+
+        return parent_rate / (usb_pdf + 1U);
+}
+
+static unsigned long _clk_ssi1_recalc(struct clk *clk)
+{
+        unsigned long ssi1_pdf;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        ssi1_pdf = (PCDR0() & CCM_PCDR0_SSI1BAUDDIV_MASK) >>
+                                        CCM_PCDR0_SSI1BAUDDIV_OFFSET;
+
+        if (mx27_revision() >= CHIP_REV_2_0)
+                ssi1_pdf += 4;
+        else
+                ssi1_pdf = (ssi1_pdf < 2) ? 124UL : ssi1_pdf;
+
+        return 2UL * parent_rate / ssi1_pdf;
+}
+
+static unsigned long _clk_ssi2_recalc(struct clk *clk)
+{
+        unsigned long ssi2_pdf;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        ssi2_pdf = (PCDR0() & CCM_PCDR0_SSI2BAUDDIV_MASK) >>
+            CCM_PCDR0_SSI2BAUDDIV_OFFSET;
+
+        if (mx27_revision() >= CHIP_REV_2_0)
+                ssi2_pdf += 4;
+        else
+                ssi2_pdf = (ssi2_pdf < 2) ? 124UL : ssi2_pdf;
+
+        return 2UL * parent_rate / ssi2_pdf;
+}
+
+static unsigned long _clk_nfc_recalc(struct clk *clk)
+{
+        unsigned long nfc_pdf;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        if (mx27_revision() >= CHIP_REV_2_0) {
+                nfc_pdf =
+                    (PCDR0() & CCM_PCDR0_NFCDIV2_MASK) >>
+                    CCM_PCDR0_NFCDIV2_OFFSET;
+        } else {
+                nfc_pdf =
+                    (PCDR0() & CCM_PCDR0_NFCDIV_MASK) >>
+                    CCM_PCDR0_NFCDIV_OFFSET;
+        }
+
+        return parent_rate / (nfc_pdf + 1);
+}
+
+static unsigned long _clk_vpu_recalc(struct clk *clk)
+{
+        unsigned long vpu_pdf;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        if (mx27_revision() >= CHIP_REV_2_0) {
+                vpu_pdf =
+                    (PCDR0() & CCM_PCDR0_VPUDIV2_MASK) >>
+                    CCM_PCDR0_VPUDIV2_OFFSET;
+                vpu_pdf += 4;
+        } else {
+                vpu_pdf =
+                    (PCDR0() & CCM_PCDR0_VPUDIV_MASK) >>
+                    CCM_PCDR0_VPUDIV_OFFSET;
+                vpu_pdf = (vpu_pdf < 2) ? 124 : vpu_pdf;
+        }
+        return 2UL * parent_rate / vpu_pdf;
+}
+
+static unsigned long _clk_parent_round_rate(struct clk *clk, unsigned long rate)
+{
+        return clk->parent->round_rate(clk->parent, rate);
+}
+
+static int _clk_parent_set_rate(struct clk *clk, unsigned long rate)
+{
+        return clk->parent->set_rate(clk->parent, rate);
+}
+
+/* in Hz */
+static unsigned long external_high_reference = 26000000;
+
+static unsigned long get_high_reference_clock_rate(struct clk *clk)
+{
+        return external_high_reference;
+}
+
+/*
+ * the high frequency external clock reference
+ * Default case is 26MHz. Could be changed at runtime
+ * with a call to change_external_high_reference()
+ */
+static struct clk ckih_clk = {
+        .name = "ckih",
+        .get_rate = get_high_reference_clock_rate,
+};
+
+/* in Hz */
+static unsigned long external_low_reference = 32768;
+
+static unsigned long get_low_reference_clock_rate(struct clk *clk)
+{
+        return external_low_reference;
+}
+
+/*
+ * the low frequency external clock reference
+ * Default case is 32.768kHz Could be changed at runtime
+ * with a call to change_external_low_reference()
+ */
+static struct clk ckil_clk = {
+        .name = "ckil",
+        .get_rate = get_low_reference_clock_rate,
+};
+
+static unsigned long get_mpll_clk(struct clk *clk)
+{
+        uint32_t reg;
+        unsigned long ref_clk;
+        unsigned long mfi = 0, mfn = 0, mfd = 0, pdf = 0;
+        unsigned long long temp;
+
+        ref_clk = clk_get_rate(clk->parent);
+
+        reg = __raw_readl(CCM_MPCTL0);
+        pdf = (reg & CCM_MPCTL0_PD_MASK) >> CCM_MPCTL0_PD_OFFSET;
+        mfd = (reg & CCM_MPCTL0_MFD_MASK) >> CCM_MPCTL0_MFD_OFFSET;
+        mfi = (reg & CCM_MPCTL0_MFI_MASK) >> CCM_MPCTL0_MFI_OFFSET;
+        mfn = (reg & CCM_MPCTL0_MFN_MASK) >> CCM_MPCTL0_MFN_OFFSET;
+
+        mfi = (mfi <= 5) ? 5 : mfi;
+        temp = 2LL * ref_clk * mfn;
+        do_div(temp, mfd + 1);
+        temp = 2LL * ref_clk * mfi + temp;
+        do_div(temp, pdf + 1);
+
+        return (unsigned long)temp;
+}
+
+static struct clk mpll_clk = {
+        .name = "mpll",
+        .parent = &ckih_clk,
+        .get_rate = get_mpll_clk,
+};
+
+static unsigned long _clk_mpll_main_get_rate(struct clk *clk)
+{
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        /* i.MX27 TO2:
+         * clk->id == 0: arm clock source path 1 which is from 2*MPLL/DIV_2
+         * clk->id == 1: arm clock source path 2 which is from 2*MPLL/DIV_3
+         */
+
+        if (mx27_revision() >= CHIP_REV_2_0 && clk->id == 1)
+                return 2UL * parent_rate / 3UL;
+
+        return parent_rate;
+}
+
+static struct clk mpll_main_clk[] = {
+        {
+                /* For i.MX27 TO2, it is the MPLL path 1 of ARM core
+                 * It provide the clock source whose rate is same as MPLL
+                 */
+                .name = "mpll_main",
+                .id = 0,
+                .parent = &mpll_clk,
+                .get_rate = _clk_mpll_main_get_rate
+        }, {
+                /* For i.MX27 TO2, it is the MPLL path 2 of ARM core
+                 * It provide the clock source whose rate is same MPLL * 2/3
+                 */
+                .name = "mpll_main",
+                .id = 1,
+                .parent = &mpll_clk,
+                .get_rate = _clk_mpll_main_get_rate
+        }
+};
+
+static unsigned long get_spll_clk(struct clk *clk)
+{
+        uint32_t reg;
+        unsigned long ref_clk;
+        unsigned long mfi = 0, mfn = 0, mfd = 0, pdf = 0;
+        unsigned long long temp;
+
+        ref_clk = clk_get_rate(clk->parent);
+
+        reg = __raw_readl(CCM_SPCTL0);
+        /*TODO: This is TO2 Bug */
+        if (mx27_revision() >= CHIP_REV_2_0)
+                __raw_writel(reg, CCM_SPCTL0);
+
+        pdf = (reg & CCM_SPCTL0_PD_MASK) >> CCM_SPCTL0_PD_OFFSET;
+        mfd = (reg & CCM_SPCTL0_MFD_MASK) >> CCM_SPCTL0_MFD_OFFSET;
+        mfi = (reg & CCM_SPCTL0_MFI_MASK) >> CCM_SPCTL0_MFI_OFFSET;
+        mfn = (reg & CCM_SPCTL0_MFN_MASK) >> CCM_SPCTL0_MFN_OFFSET;
+
+        mfi = (mfi <= 5) ? 5 : mfi;
+        temp = 2LL * ref_clk * mfn;
+        do_div(temp, mfd + 1);
+        temp = 2LL * ref_clk * mfi + temp;
+        do_div(temp, pdf + 1);
+
+        return (unsigned long)temp;
+}
+
+static struct clk spll_clk = {
+        .name = "spll",
+        .parent = &ckih_clk,
+        .get_rate = get_spll_clk,
+        .enable = _clk_spll_enable,
+        .disable = _clk_spll_disable,
+};
+
+static unsigned long get_cpu_clk(struct clk *clk)
+{
+        u32 div;
+        unsigned long rate;
+
+        if (mx27_revision() >= CHIP_REV_2_0)
+                div = (CSCR() & CCM_CSCR_ARM_MASK) >> CCM_CSCR_ARM_OFFSET;
+        else
+                div = (CSCR() & CCM_CSCR_PRESC_MASK) >> CCM_CSCR_PRESC_OFFSET;
+
+        rate = clk_get_rate(clk->parent);
+        return rate / (div + 1);
+}
+
+static struct clk cpu_clk = {
+        .name = "cpu_clk",
+        .parent = &mpll_main_clk[1],
+        .set_parent = _clk_cpu_set_parent,
+        .round_rate = _clk_cpu_round_rate,
+        .get_rate = get_cpu_clk,
+        .set_rate = _clk_cpu_set_rate,
+};
+
+static unsigned long get_ahb_clk(struct clk *clk)
+{
+        unsigned long rate;
+        unsigned long bclk_pdf;
+
+        if (mx27_revision() >= CHIP_REV_2_0)
+                bclk_pdf = (CSCR() & CCM_CSCR_AHB_MASK)
+                                        >> CCM_CSCR_AHB_OFFSET;
+        else
+                bclk_pdf = (CSCR() & CCM_CSCR_BCLK_MASK)
+                                        >> CCM_CSCR_BCLK_OFFSET;
+
+        rate = clk_get_rate(clk->parent);
+        return rate / (bclk_pdf + 1);
+}
+
+static struct clk ahb_clk = {
+        .name = "ahb_clk",
+        .parent = &mpll_main_clk[1],
+        .get_rate = get_ahb_clk,
+};
+
+static unsigned long get_ipg_clk(struct clk *clk)
+{
+        unsigned long rate;
+        unsigned long ipg_pdf;
+
+        if (mx27_revision() >= CHIP_REV_2_0)
+                return clk_get_rate(clk->parent);
+        else
+                ipg_pdf = (CSCR() & CCM_CSCR_IPDIV) >> CCM_CSCR_IPDIV_OFFSET;
+
+        rate = clk_get_rate(clk->parent);
+        return rate / (ipg_pdf + 1);
+}
+
+static struct clk ipg_clk = {
+        .name = "ipg_clk",
+        .parent = &ahb_clk,
+        .get_rate = get_ipg_clk,
+};
+
+static unsigned long _clk_perclkx_recalc(struct clk *clk)
+{
+        unsigned long perclk_pdf;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        if (clk->id < 0 || clk->id > 3)
+                return 0;
+
+        perclk_pdf = (PCDR1() >> (clk->id << 3)) & CCM_PCDR1_PERDIV1_MASK;
+
+        return parent_rate / (perclk_pdf + 1);
+}
+
+static struct clk per_clk[] = {
+        {
+                .name = "per_clk",
+                .id = 0,
+                .parent = &mpll_main_clk[1],
+                .get_rate = _clk_perclkx_recalc,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR1,
+                .enable_shift = CCM_PCCR1_PERCLK1_OFFSET,
+                .disable = _clk_disable,
+        }, {
+                .name = "per_clk",
+                .id = 1,
+                .parent = &mpll_main_clk[1],
+                .get_rate = _clk_perclkx_recalc,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR1,
+                .enable_shift = CCM_PCCR1_PERCLK2_OFFSET,
+                .disable = _clk_disable,
+        }, {
+                .name = "per_clk",
+                .id = 2,
+                .parent = &mpll_main_clk[1],
+                .round_rate = _clk_perclkx_round_rate,
+                .set_rate = _clk_perclkx_set_rate,
+                .get_rate = _clk_perclkx_recalc,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR1,
+                .enable_shift = CCM_PCCR1_PERCLK3_OFFSET,
+                .disable = _clk_disable,
+        }, {
+                .name = "per_clk",
+                .id = 3,
+                .parent = &mpll_main_clk[1],
+                .round_rate = _clk_perclkx_round_rate,
+                .set_rate = _clk_perclkx_set_rate,
+                .get_rate = _clk_perclkx_recalc,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR1,
+                .enable_shift = CCM_PCCR1_PERCLK4_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+struct clk uart1_clk[] = {
+        {
+                .name = "uart_clk",
+                .id = 0,
+                .parent = &per_clk[0],
+                .secondary = &uart1_clk[1],
+        }, {
+                .name = "uart_ipg_clk",
+                .id = 0,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR1,
+                .enable_shift = CCM_PCCR1_UART1_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+struct clk uart2_clk[] = {
+        {
+                .name = "uart_clk",
+                .id = 1,
+                .parent = &per_clk[0],
+                .secondary = &uart2_clk[1],
+        }, {
+                .name = "uart_ipg_clk",
+                .id = 1,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR1,
+                .enable_shift = CCM_PCCR1_UART2_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+struct clk uart3_clk[] = {
+        {
+                .name = "uart_clk",
+                .id = 2,
+                .parent = &per_clk[0],
+                .secondary = &uart3_clk[1],
+        }, {
+                .name = "uart_ipg_clk",
+                .id = 2,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR1,
+                .enable_shift = CCM_PCCR1_UART3_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+struct clk uart4_clk[] = {
+        {
+                .name = "uart_clk",
+                .id = 3,
+                .parent = &per_clk[0],
+                .secondary = &uart4_clk[1],
+        }, {
+                .name = "uart_ipg_clk",
+                .id = 3,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR1,
+                .enable_shift = CCM_PCCR1_UART4_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+struct clk uart5_clk[] = {
+        {
+                .name = "uart_clk",
+                .id = 4,
+                .parent = &per_clk[0],
+                .secondary = &uart5_clk[1],
+        }, {
+                .name = "uart_ipg_clk",
+                .id = 4,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR1,
+                .enable_shift = CCM_PCCR1_UART5_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+struct clk uart6_clk[] = {
+        {
+                .name = "uart_clk",
+                .id = 5,
+                .parent = &per_clk[0],
+                .secondary = &uart6_clk[1],
+        }, {
+                .name = "uart_ipg_clk",
+                .id = 5,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR1,
+                .enable_shift = CCM_PCCR1_UART6_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk gpt1_clk[] = {
+        {
+                .name = "gpt_clk",
+                .id = 0,
+                .parent = &per_clk[0],
+                .secondary = &gpt1_clk[1],
+        }, {
+                .name = "gpt_ipg_clk",
+                .id = 0,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR0,
+                .enable_shift = CCM_PCCR0_GPT1_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk gpt2_clk[] = {
+        {
+                .name = "gpt_clk",
+                .id = 1,
+                .parent = &per_clk[0],
+                .secondary = &gpt2_clk[1],
+        }, {
+                .name = "gpt_ipg_clk",
+                .id = 1,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR0,
+                .enable_shift = CCM_PCCR0_GPT2_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk gpt3_clk[] = {
+        {
+                .name = "gpt_clk",
+                .id = 2,
+                .parent = &per_clk[0],
+                .secondary = &gpt3_clk[1],
+        }, {
+                .name = "gpt_ipg_clk",
+                .id = 2,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR0,
+                .enable_shift = CCM_PCCR0_GPT3_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk gpt4_clk[] = {
+        {
+                .name = "gpt_clk",
+                .id = 3,
+                .parent = &per_clk[0],
+                .secondary = &gpt4_clk[1],
+        }, {
+                .name = "gpt_ipg_clk",
+                .id = 3,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR0,
+                .enable_shift = CCM_PCCR0_GPT4_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk gpt5_clk[] = {
+        {
+                .name = "gpt_clk",
+                .id = 4,
+                .parent = &per_clk[0],
+                .secondary = &gpt5_clk[1],
+        }, {
+                .name = "gpt_ipg_clk",
+                .id = 4,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR0,
+                .enable_shift = CCM_PCCR0_GPT5_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk gpt6_clk[] = {
+        {
+                .name = "gpt_clk",
+                .id = 5,
+                .parent = &per_clk[0],
+                .secondary = &gpt6_clk[1],
+        }, {
+                .name = "gpt_ipg_clk",
+                .id = 5,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR0,
+                .enable_shift = CCM_PCCR0_GPT6_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk pwm_clk[] = {
+        {
+                .name = "pwm_clk",
+                .parent = &per_clk[0],
+                .secondary = &pwm_clk[1],
+        }, {
+                .name = "pwm_clk",
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR0,
+                .enable_shift = CCM_PCCR0_PWM_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk sdhc1_clk[] = {
+        {
+                .name = "sdhc_clk",
+                .id = 0,
+                .parent = &per_clk[1],
+                .secondary = &sdhc1_clk[1],
+        }, {
+                .name = "sdhc_ipg_clk",
+                .id = 0,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR0,
+                .enable_shift = CCM_PCCR0_SDHC1_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk sdhc2_clk[] = {
+        {
+                .name = "sdhc_clk",
+                .id = 1,
+                .parent = &per_clk[1],
+                .secondary = &sdhc2_clk[1],
+        }, {
+                .name = "sdhc_ipg_clk",
+                .id = 1,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR0,
+                .enable_shift = CCM_PCCR0_SDHC2_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk sdhc3_clk[] = {
+        {
+                .name = "sdhc_clk",
+                .id = 2,
+                .parent = &per_clk[1],
+                .secondary = &sdhc3_clk[1],
+        }, {
+                .name = "sdhc_ipg_clk",
+                .id = 2,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR0,
+                .enable_shift = CCM_PCCR0_SDHC3_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk cspi1_clk[] = {
+        {
+                .name = "cspi_clk",
+                .id = 0,
+                .parent = &per_clk[1],
+                .secondary = &cspi1_clk[1],
+        }, {
+                .name = "cspi_ipg_clk",
+                .id = 0,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR0,
+                .enable_shift = CCM_PCCR0_CSPI1_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk cspi2_clk[] = {
+        {
+                .name = "cspi_clk",
+                .id = 1,
+                .parent = &per_clk[1],
+                .secondary = &cspi2_clk[1],
+        }, {
+                .name = "cspi_ipg_clk",
+                .id = 1,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR0,
+                .enable_shift = CCM_PCCR0_CSPI2_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk cspi3_clk[] = {
+        {
+                .name = "cspi_clk",
+                .id = 2,
+                .parent = &per_clk[1],
+                .secondary = &cspi3_clk[1],
+        }, {
+                .name = "cspi_ipg_clk",
+                .id = 2,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR0,
+                .enable_shift = CCM_PCCR0_CSPI3_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk lcdc_clk[] = {
+        {
+                .name = "lcdc_clk",
+                .parent = &per_clk[2],
+                .secondary = &lcdc_clk[1],
+                .round_rate = _clk_parent_round_rate,
+                .set_rate = _clk_parent_set_rate,
+        }, {
+                .name = "lcdc_ipg_clk",
+                .parent = &ipg_clk,
+                .secondary = &lcdc_clk[2],
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR0,
+                .enable_shift = CCM_PCCR0_LCDC_OFFSET,
+                .disable = _clk_disable,
+        }, {
+                .name = "lcdc_ahb_clk",
+                .parent = &ahb_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR1,
+                .enable_shift = CCM_PCCR1_HCLK_LCDC_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk csi_clk[] = {
+        {
+                .name = "csi_perclk",
+                .parent = &per_clk[3],
+                .secondary = &csi_clk[1],
+                .round_rate = _clk_parent_round_rate,
+                .set_rate = _clk_parent_set_rate,
+        }, {
+                .name = "csi_ahb_clk",
+                .parent = &ahb_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR1,
+                .enable_shift = CCM_PCCR1_HCLK_CSI_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk usb_clk[] = {
+        {
+                .name = "usb_clk",
+                .parent = &spll_clk,
+                .get_rate = _clk_usb_recalc,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR1,
+                .enable_shift = CCM_PCCR1_USBOTG_OFFSET,
+                .disable = _clk_disable,
+        }, {
+                .name = "usb_ahb_clk",
+                .parent = &ahb_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR1,
+                .enable_shift = CCM_PCCR1_HCLK_USBOTG_OFFSET,
+                .disable = _clk_disable,
+        }
+};
+
+static struct clk ssi1_clk[] = {
+        {
+                .name = "ssi_clk",
+                .id = 0,
+                .parent = &mpll_main_clk[1],
+                .secondary = &ssi1_clk[1],
+                .get_rate = _clk_ssi1_recalc,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR1,
+                .enable_shift = CCM_PCCR1_SSI1_BAUD_OFFSET,
+                .disable = _clk_disable,
+        }, {
+                .name = "ssi_ipg_clk",
+                .id = 0,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR0,
+                .enable_shift = CCM_PCCR0_SSI1_IPG_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk ssi2_clk[] = {
+        {
+                .name = "ssi_clk",
+                .id = 1,
+                .parent = &mpll_main_clk[1],
+                .secondary = &ssi2_clk[1],
+                .get_rate = _clk_ssi2_recalc,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR1,
+                .enable_shift = CCM_PCCR1_SSI2_BAUD_OFFSET,
+                .disable = _clk_disable,
+        }, {
+                .name = "ssi_ipg_clk",
+                .id = 1,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR0,
+                .enable_shift = CCM_PCCR0_SSI2_IPG_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk nfc_clk = {
+        .name = "nfc_clk",
+        .parent = &cpu_clk,
+        .get_rate = _clk_nfc_recalc,
+        .enable = _clk_enable,
+        .enable_reg = CCM_PCCR1,
+        .enable_shift = CCM_PCCR1_NFC_BAUD_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk vpu_clk = {
+        .name = "vpu_clk",
+        .parent = &mpll_main_clk[1],
+        .get_rate = _clk_vpu_recalc,
+        .enable = _clk_vpu_enable,
+        .disable = _clk_vpu_disable,
+};
+
+static struct clk dma_clk = {
+        .name = "dma_clk",
+        .parent = &ahb_clk,
+        .enable = _clk_dma_enable,
+        .disable = _clk_dma_disable,
+};
+
+static struct clk rtic_clk = {
+        .name = "rtic_clk",
+        .parent = &ahb_clk,
+        .enable = _clk_rtic_enable,
+        .disable = _clk_rtic_disable,
+};
+
+static struct clk brom_clk = {
+        .name = "brom_clk",
+        .parent = &ahb_clk,
+        .enable = _clk_enable,
+        .enable_reg = CCM_PCCR1,
+        .enable_shift = CCM_PCCR1_HCLK_BROM_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk emma_clk = {
+        .name = "emma_clk",
+        .parent = &ahb_clk,
+        .enable = _clk_emma_enable,
+        .disable = _clk_emma_disable,
+};
+
+static struct clk slcdc_clk = {
+        .name = "slcdc_clk",
+        .parent = &ahb_clk,
+        .enable = _clk_slcdc_enable,
+        .disable = _clk_slcdc_disable,
+};
+
+static struct clk fec_clk = {
+        .name = "fec_clk",
+        .parent = &ahb_clk,
+        .enable = _clk_fec_enable,
+        .disable = _clk_fec_disable,
+};
+
+static struct clk emi_clk = {
+        .name = "emi_clk",
+        .parent = &ahb_clk,
+        .enable = _clk_enable,
+        .enable_reg = CCM_PCCR1,
+        .enable_shift = CCM_PCCR1_HCLK_EMI_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk sahara2_clk = {
+        .name = "sahara_clk",
+        .parent = &ahb_clk,
+        .enable = _clk_sahara2_enable,
+        .disable = _clk_sahara2_disable,
+};
+
+static struct clk ata_clk = {
+        .name = "ata_clk",
+        .parent = &ahb_clk,
+        .enable = _clk_enable,
+        .enable_reg = CCM_PCCR1,
+        .enable_shift = CCM_PCCR1_HCLK_ATA_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk mstick1_clk = {
+        .name = "mstick1_clk",
+        .parent = &ipg_clk,
+        .enable = _clk_mstick1_enable,
+        .disable = _clk_mstick1_disable,
+};
+
+static struct clk wdog_clk = {
+        .name = "wdog_clk",
+        .parent = &ipg_clk,
+        .enable = _clk_enable,
+        .enable_reg = CCM_PCCR1,
+        .enable_shift = CCM_PCCR1_WDT_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk gpio_clk = {
+        .name = "gpio_clk",
+        .parent = &ipg_clk,
+        .enable = _clk_enable,
+        .enable_reg = CCM_PCCR1,
+        .enable_shift = CCM_PCCR0_GPIO_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk i2c_clk[] = {
+        {
+                .name = "i2c_clk",
+                .id = 0,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR0,
+                .enable_shift = CCM_PCCR0_I2C1_OFFSET,
+                .disable = _clk_disable,
+        }, {
+                .name = "i2c_clk",
+                .id = 1,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR0,
+                .enable_shift = CCM_PCCR0_I2C2_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk iim_clk = {
+        .name = "iim_clk",
+        .parent = &ipg_clk,
+        .enable = _clk_enable,
+        .enable_reg = CCM_PCCR0,
+        .enable_shift = CCM_PCCR0_IIM_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk kpp_clk = {
+        .name = "kpp_clk",
+        .parent = &ipg_clk,
+        .enable = _clk_enable,
+        .enable_reg = CCM_PCCR0,
+        .enable_shift = CCM_PCCR0_KPP_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk owire_clk = {
+        .name = "owire_clk",
+        .parent = &ipg_clk,
+        .enable = _clk_enable,
+        .enable_reg = CCM_PCCR0,
+        .enable_shift = CCM_PCCR0_OWIRE_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk rtc_clk = {
+        .name = "rtc_clk",
+        .parent = &ipg_clk,
+        .enable = _clk_enable,
+        .enable_reg = CCM_PCCR0,
+        .enable_shift = CCM_PCCR0_RTC_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk scc_clk = {
+        .name = "scc_clk",
+        .parent = &ipg_clk,
+        .enable = _clk_enable,
+        .enable_reg = CCM_PCCR0,
+        .enable_shift = CCM_PCCR0_SCC_OFFSET,
+        .disable = _clk_disable,
+};
+
+static unsigned long _clk_clko_round_rate(struct clk *clk, unsigned long rate)
+{
+        u32 div;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+        div = parent_rate / rate;
+        if (parent_rate % rate)
+                div++;
+
+        if (div > 8)
+                div = 8;
+
+        return parent_rate / div;
+}
+
+static int _clk_clko_set_rate(struct clk *clk, unsigned long rate)
+{
+        u32 reg;
+        u32 div;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        div = parent_rate / rate;
+
+        if (div > 8 || div < 1 || ((parent_rate / div) != rate))
+                return -EINVAL;
+        div--;
+
+        reg = __raw_readl(CCM_PCDR0) & ~CCM_PCDR0_CLKODIV_MASK;
+        reg |= div << CCM_PCDR0_CLKODIV_OFFSET;
+        __raw_writel(reg, CCM_PCDR0);
+
+        return 0;
+}
+
+static unsigned long _clk_clko_recalc(struct clk *clk)
+{
+        u32 div;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        div = __raw_readl(CCM_PCDR0) & CCM_PCDR0_CLKODIV_MASK >>
+                CCM_PCDR0_CLKODIV_OFFSET;
+        div++;
+
+        return parent_rate / div;
+}
+
+static int _clk_clko_set_parent(struct clk *clk, struct clk *parent)
+{
+        u32 reg;
+
+        reg = __raw_readl(CCM_CCSR) & ~CCM_CCSR_CLKOSEL_MASK;
+
+        if (parent == &ckil_clk)
+                reg |= 0 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &ckih_clk)
+                reg |= 2 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == mpll_clk.parent)
+                reg |= 3 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == spll_clk.parent)
+                reg |= 4 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &mpll_clk)
+                reg |= 5 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &spll_clk)
+                reg |= 6 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &cpu_clk)
+                reg |= 7 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &ahb_clk)
+                reg |= 8 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &ipg_clk)
+                reg |= 9 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &per_clk[0])
+                reg |= 0xA << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &per_clk[1])
+                reg |= 0xB << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &per_clk[2])
+                reg |= 0xC << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &per_clk[3])
+                reg |= 0xD << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &ssi1_clk[0])
+                reg |= 0xE << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &ssi2_clk[0])
+                reg |= 0xF << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &nfc_clk)
+                reg |= 0x10 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &mstick1_clk)
+                reg |= 0x11 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &vpu_clk)
+                reg |= 0x12 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &usb_clk[0])
+                reg |= 0x15 << CCM_CCSR_CLKOSEL_OFFSET;
+        else
+                return -EINVAL;
+
+        __raw_writel(reg, CCM_CCSR);
+
+        return 0;
+}
+
+static int _clk_clko_enable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(CCM_PCDR0) | CCM_PCDR0_CLKO_EN;
+        __raw_writel(reg, CCM_PCDR0);
+
+        return 0;
+}
+
+static void _clk_clko_disable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(CCM_PCDR0) & ~CCM_PCDR0_CLKO_EN;
+        __raw_writel(reg, CCM_PCDR0);
+}
+
+static struct clk clko_clk = {
+        .name = "clko_clk",
+        .get_rate = _clk_clko_recalc,
+        .set_rate = _clk_clko_set_rate,
+        .round_rate = _clk_clko_round_rate,
+        .set_parent = _clk_clko_set_parent,
+        .enable = _clk_clko_enable,
+        .disable = _clk_clko_disable,
+};
+
+static struct clk *mxc_clks[] = {
+        &ckih_clk,
+        &ckil_clk,
+        &mpll_clk,
+        &mpll_main_clk[0],
+        &mpll_main_clk[1],
+        &spll_clk,
+        &cpu_clk,
+        &ahb_clk,
+        &ipg_clk,
+        &per_clk[0],
+        &per_clk[1],
+        &per_clk[2],
+        &per_clk[3],
+        &clko_clk,
+        &uart1_clk[0],
+        &uart1_clk[1],
+        &uart2_clk[0],
+        &uart2_clk[1],
+        &uart3_clk[0],
+        &uart3_clk[1],
+        &uart4_clk[0],
+        &uart4_clk[1],
+        &uart5_clk[0],
+        &uart5_clk[1],
+        &uart6_clk[0],
+        &uart6_clk[1],
+        &gpt1_clk[0],
+        &gpt1_clk[1],
+        &gpt2_clk[0],
+        &gpt2_clk[1],
+        &gpt3_clk[0],
+        &gpt3_clk[1],
+        &gpt4_clk[0],
+        &gpt4_clk[1],
+        &gpt5_clk[0],
+        &gpt5_clk[1],
+        &gpt6_clk[0],
+        &gpt6_clk[1],
+        &pwm_clk[0],
+        &pwm_clk[1],
+        &sdhc1_clk[0],
+        &sdhc1_clk[1],
+        &sdhc2_clk[0],
+        &sdhc2_clk[1],
+        &sdhc3_clk[0],
+        &sdhc3_clk[1],
+        &cspi1_clk[0],
+        &cspi1_clk[1],
+        &cspi2_clk[0],
+        &cspi2_clk[1],
+        &cspi3_clk[0],
+        &cspi3_clk[1],
+        &lcdc_clk[0],
+        &lcdc_clk[1],
+        &lcdc_clk[2],
+        &csi_clk[0],
+        &csi_clk[1],
+        &usb_clk[0],
+        &usb_clk[1],
+        &ssi1_clk[0],
+        &ssi1_clk[1],
+        &ssi2_clk[0],
+        &ssi2_clk[1],
+        &nfc_clk,
+        &vpu_clk,
+        &dma_clk,
+        &rtic_clk,
+        &brom_clk,
+        &emma_clk,
+        &slcdc_clk,
+        &fec_clk,
+        &emi_clk,
+        &sahara2_clk,
+        &ata_clk,
+        &mstick1_clk,
+        &wdog_clk,
+        &gpio_clk,
+        &i2c_clk[0],
+        &i2c_clk[1],
+        &iim_clk,
+        &kpp_clk,
+        &owire_clk,
+        &rtc_clk,
+        &scc_clk,
+};
+
+void __init change_external_low_reference(unsigned long new_ref)
+{
+        external_low_reference = new_ref;
+}
+
+unsigned long __init clk_early_get_timer_rate(void)
+{
+        return clk_get_rate(&per_clk[0]);
+}
+
+static void __init probe_mxc_clocks(void)
+{
+        int i;
+
+        if (mx27_revision() >= CHIP_REV_2_0) {
+                if (CSCR() & 0x8000)
+                        cpu_clk.parent = &mpll_main_clk[0];
+
+                if (!(CSCR() & 0x00800000))
+                        ssi2_clk[0].parent = &spll_clk;
+
+                if (!(CSCR() & 0x00400000))
+                        ssi1_clk[0].parent = &spll_clk;
+
+                if (!(CSCR() & 0x00200000))
+                        vpu_clk.parent = &spll_clk;
+        } else {
+                cpu_clk.parent = &mpll_clk;
+                cpu_clk.set_parent = NULL;
+                cpu_clk.round_rate = NULL;
+                cpu_clk.set_rate = NULL;
+                ahb_clk.parent = &mpll_clk;
+
+                for (i = 0; i < sizeof(per_clk) / sizeof(per_clk[0]); i++)
+                        per_clk[i].parent = &mpll_clk;
+
+                ssi1_clk[0].parent = &mpll_clk;
+                ssi2_clk[0].parent = &mpll_clk;
+
+                vpu_clk.parent = &mpll_clk;
+        }
+}
+
+/*
+ * must be called very early to get information about the
+ * available clock rate when the timer framework starts
+ */
+int __init mxc_clocks_init(unsigned long fref)
+{
+        u32 cscr;
+        struct clk **clkp;
+
+        external_high_reference = fref;
+
+        /* detect clock reference for both system PLL */
+        cscr = CSCR();
+        if (cscr & CCM_CSCR_MCU)
+                mpll_clk.parent = &ckih_clk;
+        else
+                mpll_clk.parent = &ckil_clk;
+
+        if (cscr & CCM_CSCR_SP)
+                spll_clk.parent = &ckih_clk;
+        else
+                spll_clk.parent = &ckil_clk;
+
+        probe_mxc_clocks();
+
+        per_clk[0].enable(&per_clk[0]);
+        gpt1_clk[1].enable(&gpt1_clk[1]);
+
+        for (clkp = mxc_clks; clkp < mxc_clks + ARRAY_SIZE(mxc_clks); clkp++)
+                clk_register(*clkp);
+
+        /* Turn off all possible clocks */
+        __raw_writel(CCM_PCCR0_GPT1_MASK, CCM_PCCR0);
+        __raw_writel(CCM_PCCR1_PERCLK1_MASK | CCM_PCCR1_HCLK_EMI_MASK,
+                     CCM_PCCR1);
+        spll_clk.disable(&spll_clk);
+
+        /* This will propagate to all children and init all the clock rates */
+
+        clk_enable(&emi_clk);
+        clk_enable(&gpio_clk);
+        clk_enable(&iim_clk);
+        clk_enable(&gpt1_clk[0]);
+#ifdef CONFIG_DEBUG_LL_CONSOLE
+        clk_enable(&uart1_clk[0]);
+#endif
+        return 0;
+}
diff --git a/arch/arm/mach-mx2/cpu_imx27.c b/arch/arm/mach-mx2/cpu_imx27.c
new file mode 100644
index 000000000000..d6b5c2e3377f
--- /dev/null
+++ b/arch/arm/mach-mx2/cpu_imx27.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+/*
+ * i.MX27 specific CPU detection code
+ */
+
+#include <linux/io.h>
+#include <linux/module.h>
+
+#include <asm/hardware.h>
+
+#include "crm_regs.h"
+
+static int cpu_silicon_rev = -1;
+static int cpu_partnumber;
+
+static void query_silicon_parameter(void)
+{
+        u32 val;
+        /*
+         * now we have access to the IO registers. As we need
+         * the silicon revision very early we read it here to
+         * avoid any further hooks
+        */
+        val = __raw_readl(IO_ADDRESS(SYSCTRL_BASE_ADDR) + SYS_CHIP_ID);
+
+        cpu_silicon_rev = (int)(val >> 28);
+        cpu_partnumber = (int)((val >> 12) & 0xFFFF);
+}
+
+/*
+ * Returns:
+ *      the silicon revision of the cpu
+ *      -EINVAL - not a mx27
+ */
+int mx27_revision(void)
+{
+        if (cpu_silicon_rev == -1)
+                query_silicon_parameter();
+
+        if (cpu_partnumber != 0x8821)
+                return -EINVAL;
+
+        return cpu_silicon_rev;
+}
+EXPORT_SYMBOL(mx27_revision);
diff --git a/arch/arm/mach-mx2/crm_regs.h b/arch/arm/mach-mx2/crm_regs.h
new file mode 100644
index 000000000000..a40a9b950ce9
--- /dev/null
+++ b/arch/arm/mach-mx2/crm_regs.h
@@ -0,0 +1,273 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#ifndef __ARCH_ARM_MACH_MX2_CRM_REGS_H__
+#define __ARCH_ARM_MACH_MX2_CRM_REGS_H__
+
+#include <asm/arch/hardware.h>
+
+/* Register offsets */
+#define CCM_CSCR                (IO_ADDRESS(CCM_BASE_ADDR) + 0x0)
+#define CCM_MPCTL0              (IO_ADDRESS(CCM_BASE_ADDR) + 0x4)
+#define CCM_MPCTL1              (IO_ADDRESS(CCM_BASE_ADDR) + 0x8)
+#define CCM_SPCTL0              (IO_ADDRESS(CCM_BASE_ADDR) + 0xC)
+#define CCM_SPCTL1              (IO_ADDRESS(CCM_BASE_ADDR) + 0x10)
+#define CCM_OSC26MCTL           (IO_ADDRESS(CCM_BASE_ADDR) + 0x14)
+#define CCM_PCDR0               (IO_ADDRESS(CCM_BASE_ADDR) + 0x18)
+#define CCM_PCDR1               (IO_ADDRESS(CCM_BASE_ADDR) + 0x1c)
+#define CCM_PCCR0               (IO_ADDRESS(CCM_BASE_ADDR) + 0x20)
+#define CCM_PCCR1               (IO_ADDRESS(CCM_BASE_ADDR) + 0x24)
+#define CCM_CCSR                (IO_ADDRESS(CCM_BASE_ADDR) + 0x28)
+#define CCM_PMCTL               (IO_ADDRESS(CCM_BASE_ADDR) + 0x2c)
+#define CCM_PMCOUNT             (IO_ADDRESS(CCM_BASE_ADDR) + 0x30)
+#define CCM_WKGDCTL             (IO_ADDRESS(CCM_BASE_ADDR) + 0x34)
+
+#define CCM_CSCR_USB_OFFSET     28
+#define CCM_CSCR_USB_MASK       (0x7 << 28)
+#define CCM_CSCR_SD_OFFSET      24
+#define CCM_CSCR_SD_MASK        (0x3 << 24)
+#define CCM_CSCR_SSI2           (1 << 23)
+#define CCM_CSCR_SSI2_OFFSET    23
+#define CCM_CSCR_SSI1           (1 << 22)
+#define CCM_CSCR_SSI1_OFFSET    22
+#define CCM_CSCR_VPU           (1 << 21)
+#define CCM_CSCR_VPU_OFFSET    21
+#define CCM_CSCR_MSHC           (1 << 20)
+#define CCM_CSCR_SPLLRES        (1 << 19)
+#define CCM_CSCR_MPLLRES        (1 << 18)
+#define CCM_CSCR_SP             (1 << 17)
+#define CCM_CSCR_MCU            (1 << 16)
+/* CCM_CSCR_ARM_xxx just be avaliable on i.MX27 TO2*/
+#define CCM_CSCR_ARM_SRC        (1 << 15)
+#define CCM_CSCR_ARM_OFFSET     12
+#define CCM_CSCR_ARM_MASK       (0x3 << 12)
+/* CCM_CSCR_ARM_xxx just be avaliable on i.MX27 TO2*/
+#define CCM_CSCR_PRESC_OFFSET   13
+#define CCM_CSCR_PRESC_MASK     (0x7 << 13)
+#define CCM_CSCR_BCLK_OFFSET    9
+#define CCM_CSCR_BCLK_MASK      (0xf << 9)
+#define CCM_CSCR_IPDIV_OFFSET   8
+#define CCM_CSCR_IPDIV          (1 << 8)
+/* CCM_CSCR_AHB_xxx just be avaliable on i.MX27 TO2*/
+#define CCM_CSCR_AHB_OFFSET     8
+#define CCM_CSCR_AHB_MASK       (0x3 << 8)
+/* CCM_CSCR_AHB_xxx just be avaliable on i.MX27 TO2*/
+#define CCM_CSCR_OSC26MDIV      (1 << 4)
+#define CCM_CSCR_OSC26M         (1 << 3)
+#define CCM_CSCR_FPM            (1 << 2)
+#define CCM_CSCR_SPEN           (1 << 1)
+#define CCM_CSCR_MPEN           1
+
+#define CCM_MPCTL0_CPLM         (1 << 31)
+#define CCM_MPCTL0_PD_OFFSET    26
+#define CCM_MPCTL0_PD_MASK      (0xf << 26)
+#define CCM_MPCTL0_MFD_OFFSET   16
+#define CCM_MPCTL0_MFD_MASK     (0x3ff << 16)
+#define CCM_MPCTL0_MFI_OFFSET   10
+#define CCM_MPCTL0_MFI_MASK     (0xf << 10)
+#define CCM_MPCTL0_MFN_OFFSET   0
+#define CCM_MPCTL0_MFN_MASK     0x3ff
+
+#define CCM_MPCTL1_LF           (1 << 15)
+#define CCM_MPCTL1_BRMO         (1 << 6)
+
+#define CCM_SPCTL0_CPLM         (1 << 31)
+#define CCM_SPCTL0_PD_OFFSET    26
+#define CCM_SPCTL0_PD_MASK      (0xf << 26)
+#define CCM_SPCTL0_MFD_OFFSET   16
+#define CCM_SPCTL0_MFD_MASK     (0x3ff << 16)
+#define CCM_SPCTL0_MFI_OFFSET   10
+#define CCM_SPCTL0_MFI_MASK     (0xf << 10)
+#define CCM_SPCTL0_MFN_OFFSET   0
+#define CCM_SPCTL0_MFN_MASK     0x3ff
+
+#define CCM_SPCTL1_LF           (1 << 15)
+#define CCM_SPCTL1_BRMO         (1 << 6)
+
+#define CCM_OSC26MCTL_PEAK_OFFSET       16
+#define CCM_OSC26MCTL_PEAK_MASK         (0x3 << 16)
+#define CCM_OSC26MCTL_AGC_OFFSET        8
+#define CCM_OSC26MCTL_AGC_MASK          (0x3f << 8)
+#define CCM_OSC26MCTL_ANATEST_OFFSET    0
+#define CCM_OSC26MCTL_ANATEST_MASK      0x3f
+
+#define CCM_PCDR0_SSI2BAUDDIV_OFFSET    26
+#define CCM_PCDR0_SSI2BAUDDIV_MASK      (0x3f << 26)
+#define CCM_PCDR0_CLKO_EN               25
+#define CCM_PCDR0_CLKODIV_OFFSET        22
+#define CCM_PCDR0_CLKODIV_MASK          (0x7 << 22)
+#define CCM_PCDR0_SSI1BAUDDIV_OFFSET    16
+#define CCM_PCDR0_SSI1BAUDDIV_MASK      (0x3f << 16)
+/*The difinition for i.MX27 TO2*/
+#define CCM_PCDR0_VPUDIV2_OFFSET        10
+#define CCM_PCDR0_VPUDIV2_MASK          (0x3f << 10)
+#define CCM_PCDR0_NFCDIV2_OFFSET         6
+#define CCM_PCDR0_NFCDIV2_MASK           (0xf << 6)
+#define CCM_PCDR0_MSHCDIV2_MASK          0x3f
+/*The difinition for i.MX27 TO2*/
+#define CCM_PCDR0_NFCDIV_OFFSET         12
+#define CCM_PCDR0_NFCDIV_MASK           (0xf << 12)
+#define CCM_PCDR0_VPUDIV_OFFSET        8
+#define CCM_PCDR0_VPUDIV_MASK          (0xf << 8)
+#define CCM_PCDR0_MSHCDIV_OFFSET        0
+#define CCM_PCDR0_MSHCDIV_MASK          0x1f
+
+#define CCM_PCDR1_PERDIV4_OFFSET        24
+#define CCM_PCDR1_PERDIV4_MASK          (0x3f << 24)
+#define CCM_PCDR1_PERDIV3_OFFSET        16
+#define CCM_PCDR1_PERDIV3_MASK          (0x3f << 16)
+#define CCM_PCDR1_PERDIV2_OFFSET        8
+#define CCM_PCDR1_PERDIV2_MASK          (0x3f << 8)
+#define CCM_PCDR1_PERDIV1_OFFSET        0
+#define CCM_PCDR1_PERDIV1_MASK          0x3f
+
+#define CCM_PCCR0_CSPI1_OFFSET          31
+#define CCM_PCCR0_CSPI1_MASK            (1 << 31)
+#define CCM_PCCR0_CSPI2_OFFSET          30
+#define CCM_PCCR0_CSPI2_MASK            (1 << 30)
+#define CCM_PCCR0_CSPI3_OFFSET          29
+#define CCM_PCCR0_CSPI3_MASK            (1 << 29)
+#define CCM_PCCR0_DMA_OFFSET            28
+#define CCM_PCCR0_DMA_MASK              (1 << 28)
+#define CCM_PCCR0_EMMA_OFFSET           27
+#define CCM_PCCR0_EMMA_MASK             (1 << 27)
+#define CCM_PCCR0_FEC_OFFSET            26
+#define CCM_PCCR0_FEC_MASK              (1 << 26)
+#define CCM_PCCR0_GPIO_OFFSET           25
+#define CCM_PCCR0_GPIO_MASK             (1 << 25)
+#define CCM_PCCR0_GPT1_OFFSET           24
+#define CCM_PCCR0_GPT1_MASK             (1 << 24)
+#define CCM_PCCR0_GPT2_OFFSET           23
+#define CCM_PCCR0_GPT2_MASK             (1 << 23)
+#define CCM_PCCR0_GPT3_OFFSET           22
+#define CCM_PCCR0_GPT3_MASK             (1 << 22)
+#define CCM_PCCR0_GPT4_OFFSET           21
+#define CCM_PCCR0_GPT4_MASK             (1 << 21)
+#define CCM_PCCR0_GPT5_OFFSET           20
+#define CCM_PCCR0_GPT5_MASK             (1 << 20)
+#define CCM_PCCR0_GPT6_OFFSET           19
+#define CCM_PCCR0_GPT6_MASK             (1 << 19)
+#define CCM_PCCR0_I2C1_OFFSET           18
+#define CCM_PCCR0_I2C1_MASK             (1 << 18)
+#define CCM_PCCR0_I2C2_OFFSET           17
+#define CCM_PCCR0_I2C2_MASK             (1 << 17)
+#define CCM_PCCR0_IIM_OFFSET            16
+#define CCM_PCCR0_IIM_MASK              (1 << 16)
+#define CCM_PCCR0_KPP_OFFSET            15
+#define CCM_PCCR0_KPP_MASK              (1 << 15)
+#define CCM_PCCR0_LCDC_OFFSET           14
+#define CCM_PCCR0_LCDC_MASK             (1 << 14)
+#define CCM_PCCR0_MSHC_OFFSET           13
+#define CCM_PCCR0_MSHC_MASK             (1 << 13)
+#define CCM_PCCR0_OWIRE_OFFSET          12
+#define CCM_PCCR0_OWIRE_MASK            (1 << 12)
+#define CCM_PCCR0_PWM_OFFSET            11
+#define CCM_PCCR0_PWM_MASK              (1 << 11)
+#define CCM_PCCR0_RTC_OFFSET            9
+#define CCM_PCCR0_RTC_MASK              (1 << 9)
+#define CCM_PCCR0_RTIC_OFFSET           8
+#define CCM_PCCR0_RTIC_MASK             (1 << 8)
+#define CCM_PCCR0_SAHARA_OFFSET         7
+#define CCM_PCCR0_SAHARA_MASK           (1 << 7)
+#define CCM_PCCR0_SCC_OFFSET            6
+#define CCM_PCCR0_SCC_MASK              (1 << 6)
+#define CCM_PCCR0_SDHC1_OFFSET          5
+#define CCM_PCCR0_SDHC1_MASK            (1 << 5)
+#define CCM_PCCR0_SDHC2_OFFSET          4
+#define CCM_PCCR0_SDHC2_MASK            (1 << 4)
+#define CCM_PCCR0_SDHC3_OFFSET          3
+#define CCM_PCCR0_SDHC3_MASK            (1 << 3)
+#define CCM_PCCR0_SLCDC_OFFSET          2
+#define CCM_PCCR0_SLCDC_MASK            (1 << 2)
+#define CCM_PCCR0_SSI1_IPG_OFFSET       1
+#define CCM_PCCR0_SSI1_IPG_MASK         (1 << 1)
+#define CCM_PCCR0_SSI2_IPG_OFFSET       0
+#define CCM_PCCR0_SSI2_IPG_MASK         (1 << 0)
+
+#define CCM_PCCR1_UART1_OFFSET          31
+#define CCM_PCCR1_UART1_MASK            (1 << 31)
+#define CCM_PCCR1_UART2_OFFSET          30
+#define CCM_PCCR1_UART2_MASK            (1 << 30)
+#define CCM_PCCR1_UART3_OFFSET          29
+#define CCM_PCCR1_UART3_MASK            (1 << 29)
+#define CCM_PCCR1_UART4_OFFSET          28
+#define CCM_PCCR1_UART4_MASK            (1 << 28)
+#define CCM_PCCR1_UART5_OFFSET          27
+#define CCM_PCCR1_UART5_MASK            (1 << 27)
+#define CCM_PCCR1_UART6_OFFSET          26
+#define CCM_PCCR1_UART6_MASK            (1 << 26)
+#define CCM_PCCR1_USBOTG_OFFSET         25
+#define CCM_PCCR1_USBOTG_MASK           (1 << 25)
+#define CCM_PCCR1_WDT_OFFSET            24
+#define CCM_PCCR1_WDT_MASK              (1 << 24)
+#define CCM_PCCR1_HCLK_ATA_OFFSET       23
+#define CCM_PCCR1_HCLK_ATA_MASK         (1 << 23)
+#define CCM_PCCR1_HCLK_BROM_OFFSET      22
+#define CCM_PCCR1_HCLK_BROM_MASK        (1 << 22)
+#define CCM_PCCR1_HCLK_CSI_OFFSET       21
+#define CCM_PCCR1_HCLK_CSI_MASK         (1 << 21)
+#define CCM_PCCR1_HCLK_DMA_OFFSET       20
+#define CCM_PCCR1_HCLK_DMA_MASK         (1 << 20)
+#define CCM_PCCR1_HCLK_EMI_OFFSET       19
+#define CCM_PCCR1_HCLK_EMI_MASK         (1 << 19)
+#define CCM_PCCR1_HCLK_EMMA_OFFSET      18
+#define CCM_PCCR1_HCLK_EMMA_MASK        (1 << 18)
+#define CCM_PCCR1_HCLK_FEC_OFFSET       17
+#define CCM_PCCR1_HCLK_FEC_MASK         (1 << 17)
+#define CCM_PCCR1_HCLK_VPU_OFFSET       16
+#define CCM_PCCR1_HCLK_VPU_MASK         (1 << 16)
+#define CCM_PCCR1_HCLK_LCDC_OFFSET      15
+#define CCM_PCCR1_HCLK_LCDC_MASK        (1 << 15)
+#define CCM_PCCR1_HCLK_RTIC_OFFSET      14
+#define CCM_PCCR1_HCLK_RTIC_MASK        (1 << 14)
+#define CCM_PCCR1_HCLK_SAHARA_OFFSET    13
+#define CCM_PCCR1_HCLK_SAHARA_MASK      (1 << 13)
+#define CCM_PCCR1_HCLK_SLCDC_OFFSET     12
+#define CCM_PCCR1_HCLK_SLCDC_MASK       (1 << 12)
+#define CCM_PCCR1_HCLK_USBOTG_OFFSET    11
+#define CCM_PCCR1_HCLK_USBOTG_MASK      (1 << 11)
+#define CCM_PCCR1_PERCLK1_OFFSET        10
+#define CCM_PCCR1_PERCLK1_MASK          (1 << 10)
+#define CCM_PCCR1_PERCLK2_OFFSET        9
+#define CCM_PCCR1_PERCLK2_MASK          (1 << 9)
+#define CCM_PCCR1_PERCLK3_OFFSET        8
+#define CCM_PCCR1_PERCLK3_MASK          (1 << 8)
+#define CCM_PCCR1_PERCLK4_OFFSET        7
+#define CCM_PCCR1_PERCLK4_MASK          (1 << 7)
+#define CCM_PCCR1_VPU_BAUD_OFFSET       6
+#define CCM_PCCR1_VPU_BAUD_MASK         (1 << 6)
+#define CCM_PCCR1_SSI1_BAUD_OFFSET      5
+#define CCM_PCCR1_SSI1_BAUD_MASK        (1 << 5)
+#define CCM_PCCR1_SSI2_BAUD_OFFSET      4
+#define CCM_PCCR1_SSI2_BAUD_MASK        (1 << 4)
+#define CCM_PCCR1_NFC_BAUD_OFFSET       3
+#define CCM_PCCR1_NFC_BAUD_MASK         (1 << 3)
+#define CCM_PCCR1_MSHC_BAUD_OFFSET      2
+#define CCM_PCCR1_MSHC_BAUD_MASK        (1 << 2)
+
+#define CCM_CCSR_32KSR          (1 << 15)
+#define CCM_CCSR_CLKMODE1       (1 << 9)
+#define CCM_CCSR_CLKMODE0       (1 << 8)
+#define CCM_CCSR_CLKOSEL_OFFSET 0
+#define CCM_CCSR_CLKOSEL_MASK   0x1f
+
+#define SYS_FMCR                0x14    /*  Functional Muxing Control Reg */
+#define SYS_CHIP_ID             0x00    /* The offset of CHIP ID register */
+
+#endif /* __ARCH_ARM_MACH_MX2_CRM_REGS_H__ */
diff --git a/arch/arm/mach-mx2/devices.c b/arch/arm/mach-mx2/devices.c
new file mode 100644
index 000000000000..a1f44c3c5315
--- /dev/null
+++ b/arch/arm/mach-mx2/devices.c
@@ -0,0 +1,231 @@
+/*
+ * Author: MontaVista Software, Inc.
+ *       <source@mvista.com>
+ *
+ * Based on the OMAP devices.c
+ *
+ * 2005 (c) MontaVista Software, Inc. This file is licensed under the
+ * terms of the GNU General Public License version 2. This program is
+ * licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+
+#include <asm/hardware.h>
+
+/*
+ * Resource definition for the MXC IrDA
+ */
+static struct resource mxc_irda_resources[] = {
+        [0] = {
+                .start   = UART3_BASE_ADDR,
+                .end     = UART3_BASE_ADDR + SZ_4K - 1,
+                .flags   = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start   = MXC_INT_UART3,
+                .end     = MXC_INT_UART3,
+                .flags   = IORESOURCE_IRQ,
+        },
+};
+
+/* Platform Data for MXC IrDA */
+struct platform_device mxc_irda_device = {
+        .name = "mxc_irda",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(mxc_irda_resources),
+        .resource = mxc_irda_resources,
+};
+
+/*
+ * General Purpose Timer
+ * - i.MX1: 2 timer (slighly different register handling)
+ * - i.MX21: 3 timer
+ * - i.MX27: 6 timer
+ */
+
+/* We use gpt0 as system timer, so do not add a device for this one */
+
+static struct resource timer1_resources[] = {
+        [0] = {
+                .start  = GPT2_BASE_ADDR,
+                .end    = GPT2_BASE_ADDR + 0x17,
+                .flags  = IORESOURCE_MEM
+        },
+        [1] = {
+                .start   = MXC_INT_GPT2,
+                .end     = MXC_INT_GPT2,
+                .flags   = IORESOURCE_IRQ,
+        }
+};
+
+struct platform_device mxc_gpt1 = {
+        .name = "imx_gpt",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(timer1_resources),
+        .resource = timer1_resources
+};
+
+static struct resource timer2_resources[] = {
+        [0] = {
+                .start  = GPT3_BASE_ADDR,
+                .end    = GPT3_BASE_ADDR + 0x17,
+                .flags  = IORESOURCE_MEM
+        },
+        [1] = {
+                .start   = MXC_INT_GPT3,
+                .end     = MXC_INT_GPT3,
+                .flags   = IORESOURCE_IRQ,
+        }
+};
+
+struct platform_device mxc_gpt2 = {
+        .name = "imx_gpt",
+        .id = 2,
+        .num_resources = ARRAY_SIZE(timer2_resources),
+        .resource = timer2_resources
+};
+
+#ifdef CONFIG_MACH_MX27
+static struct resource timer3_resources[] = {
+        [0] = {
+                .start  = GPT4_BASE_ADDR,
+                .end    = GPT4_BASE_ADDR + 0x17,
+                .flags  = IORESOURCE_MEM
+        },
+        [1] = {
+                .start   = MXC_INT_GPT4,
+                .end     = MXC_INT_GPT4,
+                .flags   = IORESOURCE_IRQ,
+        }
+};
+
+struct platform_device mxc_gpt3 = {
+        .name = "imx_gpt",
+        .id = 3,
+        .num_resources = ARRAY_SIZE(timer3_resources),
+        .resource = timer3_resources
+};
+
+static struct resource timer4_resources[] = {
+        [0] = {
+                .start  = GPT5_BASE_ADDR,
+                .end    = GPT5_BASE_ADDR + 0x17,
+                .flags  = IORESOURCE_MEM
+        },
+        [1] = {
+                .start   = MXC_INT_GPT5,
+                .end     = MXC_INT_GPT5,
+                .flags   = IORESOURCE_IRQ,
+        }
+};
+
+struct platform_device mxc_gpt4 = {
+        .name = "imx_gpt",
+        .id = 4,
+        .num_resources = ARRAY_SIZE(timer4_resources),
+        .resource = timer4_resources
+};
+
+static struct resource timer5_resources[] = {
+        [0] = {
+                .start  = GPT6_BASE_ADDR,
+                .end    = GPT6_BASE_ADDR + 0x17,
+                .flags  = IORESOURCE_MEM
+        },
+        [1] = {
+                .start   = MXC_INT_GPT6,
+                .end     = MXC_INT_GPT6,
+                .flags   = IORESOURCE_IRQ,
+        }
+};
+
+struct platform_device mxc_gpt5 = {
+        .name = "imx_gpt",
+        .id = 5,
+        .num_resources = ARRAY_SIZE(timer5_resources),
+        .resource = timer5_resources
+};
+#endif
+
+/*
+ * Watchdog:
+ * - i.MX1
+ * - i.MX21
+ * - i.MX27
+ */
+static struct resource mxc_wdt_resources[] = {
+        {
+                .start  = WDOG_BASE_ADDR,
+                .end    = WDOG_BASE_ADDR + 0x30,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+struct platform_device mxc_wdt = {
+        .name = "mxc_wdt",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(mxc_wdt_resources),
+        .resource = mxc_wdt_resources,
+};
+
+/* GPIO port description */
+static struct mxc_gpio_port imx_gpio_ports[] = {
+        [0] = {
+                .chip.label = "gpio-0",
+                .irq = MXC_INT_GPIO,
+                .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 0),
+                .virtual_irq_start = MXC_MAX_INT_LINES,
+        },
+        [1] = {
+                .chip.label = "gpio-1",
+                .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 1),
+                .virtual_irq_start = MXC_MAX_INT_LINES + 32,
+        },
+        [2] = {
+                .chip.label = "gpio-2",
+                .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 2),
+                .virtual_irq_start = MXC_MAX_INT_LINES + 64,
+        },
+        [3] = {
+                .chip.label = "gpio-3",
+                .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 3),
+                .virtual_irq_start = MXC_MAX_INT_LINES + 96,
+        },
+        [4] = {
+                .chip.label = "gpio-4",
+                .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 4),
+                .virtual_irq_start = MXC_MAX_INT_LINES + 128,
+        },
+        [5] = {
+                .chip.label = "gpio-5",
+                .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 5),
+                .virtual_irq_start = MXC_MAX_INT_LINES + 160,
+        }
+};
+
+int __init mxc_register_gpios(void)
+{
+        return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
+}
diff --git a/arch/arm/mach-mx2/generic.c b/arch/arm/mach-mx2/generic.c
new file mode 100644
index 000000000000..07875cf00de9
--- /dev/null
+++ b/arch/arm/mach-mx2/generic.c
@@ -0,0 +1,74 @@
+/*
+ * generic.c
+ *
+ * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/mm.h>
+#include <linux/init.h>
+#include <asm/hardware.h>
+#include <asm/pgtable.h>
+#include <asm/mach/map.h>
+
+/* MX27 memory map definition */
+static struct map_desc mxc_io_desc[] __initdata = {
+        /*
+         * this fixed mapping covers:
+         * - AIPI1
+         * - AIPI2
+         * - AITC
+         * - ROM Patch
+         * - and some reserved space
+         */
+        {
+                .virtual = AIPI_BASE_ADDR_VIRT,
+                .pfn = __phys_to_pfn(AIPI_BASE_ADDR),
+                .length = AIPI_SIZE,
+                .type = MT_DEVICE
+        },
+        /*
+         * this fixed mapping covers:
+         * - CSI
+         * - ATA
+         */
+        {
+                .virtual = SAHB1_BASE_ADDR_VIRT,
+                .pfn = __phys_to_pfn(SAHB1_BASE_ADDR),
+                .length = SAHB1_SIZE,
+                .type = MT_DEVICE
+        },
+        /*
+         * this fixed mapping covers:
+         * - EMI
+         */
+        {
+                .virtual = X_MEMC_BASE_ADDR_VIRT,
+                .pfn = __phys_to_pfn(X_MEMC_BASE_ADDR),
+                .length = X_MEMC_SIZE,
+                .type = MT_DEVICE
+        }
+};
+
+/*
+ * Initialize the memory map. It is called during the
+ * system startup to create static physical to virtual
+ * memory map for the IO modules.
+ */
+void __init mxc_map_io(void)
+{
+        iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
+}
diff --git a/arch/arm/mach-mx2/mx27ads.c b/arch/arm/mach-mx2/mx27ads.c
new file mode 100644
index 000000000000..a9ff01fff137
--- /dev/null
+++ b/arch/arm/mach-mx2/mx27ads.c
@@ -0,0 +1,304 @@
+/*
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ *  Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/map.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
+#include <asm/arch/common.h>
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/imx-uart.h>
+#include <asm/arch/iomux-mx1-mx2.h>
+#include <asm/arch/board-mx27ads.h>
+
+/* ADS's NOR flash */
+static struct physmap_flash_data mx27ads_flash_data = {
+        .width = 2,
+};
+
+static struct resource mx27ads_flash_resource = {
+        .start = 0xc0000000,
+        .end = 0xc0000000 + 0x02000000 - 1,
+        .flags = IORESOURCE_MEM,
+
+};
+
+static struct platform_device mx27ads_nor_mtd_device = {
+        .name = "physmap-flash",
+        .id = 0,
+        .dev = {
+                .platform_data = &mx27ads_flash_data,
+        },
+        .num_resources = 1,
+        .resource = &mx27ads_flash_resource,
+};
+
+static int mxc_uart0_pins[] = {
+        PE12_PF_UART1_TXD,
+        PE13_PF_UART1_RXD,
+        PE14_PF_UART1_CTS,
+        PE15_PF_UART1_RTS
+};
+
+static int uart_mxc_port0_init(struct platform_device *pdev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_uart0_pins,
+                        ARRAY_SIZE(mxc_uart0_pins),
+                        MXC_GPIO_ALLOC_MODE_NORMAL, "UART0");
+}
+
+static int uart_mxc_port0_exit(struct platform_device *pdev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_uart0_pins,
+                        ARRAY_SIZE(mxc_uart0_pins),
+                        MXC_GPIO_ALLOC_MODE_RELEASE, "UART0");
+}
+
+static int mxc_uart1_pins[] = {
+        PE3_PF_UART2_CTS,
+        PE4_PF_UART2_RTS,
+        PE6_PF_UART2_TXD,
+        PE7_PF_UART2_RXD
+};
+
+static int uart_mxc_port1_init(struct platform_device *pdev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_uart1_pins,
+                        ARRAY_SIZE(mxc_uart1_pins),
+                        MXC_GPIO_ALLOC_MODE_NORMAL, "UART1");
+}
+
+static int uart_mxc_port1_exit(struct platform_device *pdev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_uart1_pins,
+                        ARRAY_SIZE(mxc_uart1_pins),
+                        MXC_GPIO_ALLOC_MODE_RELEASE, "UART1");
+}
+
+static int mxc_uart2_pins[] = {
+        PE8_PF_UART3_TXD,
+        PE9_PF_UART3_RXD,
+        PE10_PF_UART3_CTS,
+        PE11_PF_UART3_RTS
+};
+
+static int uart_mxc_port2_init(struct platform_device *pdev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_uart2_pins,
+                        ARRAY_SIZE(mxc_uart2_pins),
+                        MXC_GPIO_ALLOC_MODE_NORMAL, "UART2");
+}
+
+static int uart_mxc_port2_exit(struct platform_device *pdev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_uart2_pins,
+                        ARRAY_SIZE(mxc_uart2_pins),
+                        MXC_GPIO_ALLOC_MODE_RELEASE, "UART2");
+}
+
+static int mxc_uart3_pins[] = {
+        PB26_AF_UART4_RTS,
+        PB28_AF_UART4_TXD,
+        PB29_AF_UART4_CTS,
+        PB31_AF_UART4_RXD
+};
+
+static int uart_mxc_port3_init(struct platform_device *pdev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_uart3_pins,
+                        ARRAY_SIZE(mxc_uart3_pins),
+                        MXC_GPIO_ALLOC_MODE_NORMAL, "UART3");
+}
+
+static int uart_mxc_port3_exit(struct platform_device *pdev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_uart3_pins,
+                        ARRAY_SIZE(mxc_uart3_pins),
+                        MXC_GPIO_ALLOC_MODE_RELEASE, "UART3");
+}
+
+static int mxc_uart4_pins[] = {
+        PB18_AF_UART5_TXD,
+        PB19_AF_UART5_RXD,
+        PB20_AF_UART5_CTS,
+        PB21_AF_UART5_RTS
+};
+
+static int uart_mxc_port4_init(struct platform_device *pdev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_uart4_pins,
+                        ARRAY_SIZE(mxc_uart4_pins),
+                        MXC_GPIO_ALLOC_MODE_NORMAL, "UART4");
+}
+
+static int uart_mxc_port4_exit(struct platform_device *pdev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_uart4_pins,
+                        ARRAY_SIZE(mxc_uart4_pins),
+                        MXC_GPIO_ALLOC_MODE_RELEASE, "UART4");
+}
+
+static int mxc_uart5_pins[] = {
+        PB10_AF_UART6_TXD,
+        PB12_AF_UART6_CTS,
+        PB11_AF_UART6_RXD,
+        PB13_AF_UART6_RTS
+};
+
+static int uart_mxc_port5_init(struct platform_device *pdev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_uart5_pins,
+                        ARRAY_SIZE(mxc_uart5_pins),
+                        MXC_GPIO_ALLOC_MODE_NORMAL, "UART5");
+}
+
+static int uart_mxc_port5_exit(struct platform_device *pdev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_uart5_pins,
+                        ARRAY_SIZE(mxc_uart5_pins),
+                        MXC_GPIO_ALLOC_MODE_RELEASE, "UART5");
+}
+
+static struct platform_device *platform_devices[] __initdata = {
+        &mx27ads_nor_mtd_device,
+};
+
+static int mxc_fec_pins[] = {
+        PD0_AIN_FEC_TXD0,
+        PD1_AIN_FEC_TXD1,
+        PD2_AIN_FEC_TXD2,
+        PD3_AIN_FEC_TXD3,
+        PD4_AOUT_FEC_RX_ER,
+        PD5_AOUT_FEC_RXD1,
+        PD6_AOUT_FEC_RXD2,
+        PD7_AOUT_FEC_RXD3,
+        PD8_AF_FEC_MDIO,
+        PD9_AIN_FEC_MDC,
+        PD10_AOUT_FEC_CRS,
+        PD11_AOUT_FEC_TX_CLK,
+        PD12_AOUT_FEC_RXD0,
+        PD13_AOUT_FEC_RX_DV,
+        PD14_AOUT_FEC_CLR,
+        PD15_AOUT_FEC_COL,
+        PD16_AIN_FEC_TX_ER,
+        PF23_AIN_FEC_TX_EN
+};
+
+static void gpio_fec_active(void)
+{
+        mxc_gpio_setup_multiple_pins(mxc_fec_pins,
+                        ARRAY_SIZE(mxc_fec_pins),
+                        MXC_GPIO_ALLOC_MODE_NORMAL, "FEC");
+}
+
+static void gpio_fec_inactive(void)
+{
+        mxc_gpio_setup_multiple_pins(mxc_fec_pins,
+                        ARRAY_SIZE(mxc_fec_pins),
+                        MXC_GPIO_ALLOC_MODE_RELEASE, "FEC");
+}
+
+static struct imxuart_platform_data uart_pdata[] = {
+        {
+                .init = uart_mxc_port0_init,
+                .exit = uart_mxc_port0_exit,
+                .flags = IMXUART_HAVE_RTSCTS,
+        }, {
+                .init = uart_mxc_port1_init,
+                .exit = uart_mxc_port1_exit,
+                .flags = IMXUART_HAVE_RTSCTS,
+        }, {
+                .init = uart_mxc_port2_init,
+                .exit = uart_mxc_port2_exit,
+                .flags = IMXUART_HAVE_RTSCTS,
+        }, {
+                .init = uart_mxc_port3_init,
+                .exit = uart_mxc_port3_exit,
+                .flags = IMXUART_HAVE_RTSCTS,
+        }, {
+                .init = uart_mxc_port4_init,
+                .exit = uart_mxc_port4_exit,
+                .flags = IMXUART_HAVE_RTSCTS,
+        }, {
+                .init = uart_mxc_port5_init,
+                .exit = uart_mxc_port5_exit,
+                .flags = IMXUART_HAVE_RTSCTS,
+        },
+};
+
+static void __init mx27ads_board_init(void)
+{
+        int i;
+
+        gpio_fec_active();
+
+        for (i = 0; i < 6; i++)
+                imx_init_uart(i, &uart_pdata[i]);
+
+        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+}
+
+static void __init mx27ads_timer_init(void)
+{
+        unsigned long fref = 26000000;
+
+        if ((__raw_readw(PBC_VERSION_REG) & CKIH_27MHZ_BIT_SET) == 0)
+                fref = 27000000;
+
+        mxc_clocks_init(fref);
+        mxc_timer_init("gpt_clk.0");
+}
+
+struct sys_timer mx27ads_timer = {
+        .init   = mx27ads_timer_init,
+};
+
+static struct map_desc mx27ads_io_desc[] __initdata = {
+        {
+                .virtual = PBC_BASE_ADDRESS,
+                .pfn = __phys_to_pfn(CS4_BASE_ADDR),
+                .length = SZ_1M,
+                .type = MT_DEVICE,
+        },
+};
+
+void __init mx27ads_map_io(void)
+{
+        mxc_map_io();
+        iotable_init(mx27ads_io_desc, ARRAY_SIZE(mx27ads_io_desc));
+}
+
+MACHINE_START(MX27ADS, "Freescale i.MX27ADS")
+        /* maintainer: Freescale Semiconductor, Inc. */
+        .phys_io        = AIPI_BASE_ADDR,
+        .io_pg_offst    = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+        .boot_params    = PHYS_OFFSET + 0x100,
+        .map_io         = mx27ads_map_io,
+        .init_irq       = mxc_init_irq,
+        .init_machine   = mx27ads_board_init,
+        .timer          = &mx27ads_timer,
+MACHINE_END
+
diff --git a/arch/arm/mach-mx2/pcm038.c b/arch/arm/mach-mx2/pcm038.c
new file mode 100644
index 000000000000..a9a28f58e714
--- /dev/null
+++ b/arch/arm/mach-mx2/pcm038.c
@@ -0,0 +1,204 @@
+/*
+ * Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
+ * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+#include <asm/arch/common.h>
+#include <asm/hardware.h>
+#include <asm/arch/iomux-mx1-mx2.h>
+#include <asm/mach/time.h>
+#include <asm/arch/imx-uart.h>
+#include <asm/arch/board-pcm038.h>
+
+/*
+ * Phytec's phyCORE-i.MX27 comes with 32MiB flash,
+ * 16 bit width
+ */
+static struct physmap_flash_data pcm038_flash_data = {
+        .width = 2,
+};
+
+static struct resource pcm038_flash_resource = {
+        .start = 0xc0000000,
+        .end   = 0xc1ffffff,
+        .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device pcm038_nor_mtd_device = {
+        .name = "physmap-flash",
+        .id = 0,
+        .dev = {
+                .platform_data = &pcm038_flash_data,
+        },
+        .num_resources = 1,
+        .resource = &pcm038_flash_resource,
+};
+
+static int mxc_uart0_pins[] = {
+        PE12_PF_UART1_TXD,
+        PE13_PF_UART1_RXD,
+        PE14_PF_UART1_CTS,
+        PE15_PF_UART1_RTS
+};
+
+static int uart_mxc_port0_init(struct platform_device *pdev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_uart0_pins,
+                        ARRAY_SIZE(mxc_uart0_pins),
+                        MXC_GPIO_ALLOC_MODE_NORMAL, "UART0");
+}
+
+static int uart_mxc_port0_exit(struct platform_device *pdev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_uart0_pins,
+                        ARRAY_SIZE(mxc_uart0_pins),
+                        MXC_GPIO_ALLOC_MODE_RELEASE, "UART0");
+}
+
+static int mxc_uart1_pins[] = {
+        PE3_PF_UART2_CTS,
+        PE4_PF_UART2_RTS,
+        PE6_PF_UART2_TXD,
+        PE7_PF_UART2_RXD
+};
+
+static int uart_mxc_port1_init(struct platform_device *pdev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_uart1_pins,
+                        ARRAY_SIZE(mxc_uart1_pins),
+                        MXC_GPIO_ALLOC_MODE_NORMAL, "UART1");
+}
+
+static int uart_mxc_port1_exit(struct platform_device *pdev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_uart1_pins,
+                        ARRAY_SIZE(mxc_uart1_pins),
+                        MXC_GPIO_ALLOC_MODE_RELEASE, "UART1");
+}
+
+static int mxc_uart2_pins[] = { PE10_PF_UART3_CTS,
+                                PE9_PF_UART3_RXD,
+                                PE10_PF_UART3_CTS,
+                                PE9_PF_UART3_RXD };
+
+static int uart_mxc_port2_init(struct platform_device *pdev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_uart2_pins,
+                        ARRAY_SIZE(mxc_uart2_pins),
+                        MXC_GPIO_ALLOC_MODE_NORMAL, "UART2");
+}
+
+static int uart_mxc_port2_exit(struct platform_device *pdev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_uart2_pins,
+                        ARRAY_SIZE(mxc_uart2_pins),
+                        MXC_GPIO_ALLOC_MODE_RELEASE, "UART2");
+}
+
+static struct imxuart_platform_data uart_pdata[] = {
+        {
+                .init = uart_mxc_port0_init,
+                .exit = uart_mxc_port0_exit,
+                .flags = IMXUART_HAVE_RTSCTS,
+        }, {
+                .init = uart_mxc_port1_init,
+                .exit = uart_mxc_port1_exit,
+                .flags = IMXUART_HAVE_RTSCTS,
+        }, {
+                .init = uart_mxc_port2_init,
+                .exit = uart_mxc_port2_exit,
+                .flags = IMXUART_HAVE_RTSCTS,
+        },
+};
+
+static int mxc_fec_pins[] = {
+        PD0_AIN_FEC_TXD0,
+        PD1_AIN_FEC_TXD1,
+        PD2_AIN_FEC_TXD2,
+        PD3_AIN_FEC_TXD3,
+        PD4_AOUT_FEC_RX_ER,
+        PD5_AOUT_FEC_RXD1,
+        PD6_AOUT_FEC_RXD2,
+        PD7_AOUT_FEC_RXD3,
+        PD8_AF_FEC_MDIO,
+        PD9_AIN_FEC_MDC,
+        PD10_AOUT_FEC_CRS,
+        PD11_AOUT_FEC_TX_CLK,
+        PD12_AOUT_FEC_RXD0,
+        PD13_AOUT_FEC_RX_DV,
+        PD14_AOUT_FEC_CLR,
+        PD15_AOUT_FEC_COL,
+        PD16_AIN_FEC_TX_ER,
+        PF23_AIN_FEC_TX_EN
+};
+
+static void gpio_fec_active(void)
+{
+        mxc_gpio_setup_multiple_pins(mxc_fec_pins,
+                        ARRAY_SIZE(mxc_fec_pins),
+                        MXC_GPIO_ALLOC_MODE_NORMAL, "FEC");
+}
+
+static void gpio_fec_inactive(void)
+{
+        mxc_gpio_setup_multiple_pins(mxc_fec_pins,
+                        ARRAY_SIZE(mxc_fec_pins),
+                        MXC_GPIO_ALLOC_MODE_RELEASE, "FEC");
+}
+
+static struct platform_device *platform_devices[] __initdata = {
+        &pcm038_nor_mtd_device,
+};
+
+static void __init pcm038_init(void)
+{
+        int i;
+        gpio_fec_active();
+
+        for (i = 0; i < 3; i++)
+                imx_init_uart(i, &uart_pdata[i]);
+
+        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+
+#ifdef CONFIG_MACH_PCM970_BASEBOARD
+        pcm970_baseboard_init();
+#endif
+}
+
+static void __init pcm038_timer_init(void)
+{
+        mxc_clocks_init(26000000);
+        mxc_timer_init("gpt_clk.0");
+}
+
+struct sys_timer pcm038_timer = {
+        .init = pcm038_timer_init,
+};
+
+MACHINE_START(PCM038, "phyCORE-i.MX27")
+        .phys_io        = AIPI_BASE_ADDR,
+        .io_pg_offst    = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+        .boot_params    = PHYS_OFFSET + 0x100,
+        .map_io         = mxc_map_io,
+        .init_irq       = mxc_init_irq,
+        .init_machine   = pcm038_init,
+        .timer          = &pcm038_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mx2/pcm970-baseboard.c b/arch/arm/mach-mx2/pcm970-baseboard.c
new file mode 100644
index 000000000000..028ac4d33684
--- /dev/null
+++ b/arch/arm/mach-mx2/pcm970-baseboard.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/platform_device.h>
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+/*
+ * system init for baseboard usage. Will be called by pcm038 init.
+ *
+ * Add platform devices present on this baseboard and init
+ * them from CPU side as far as required to use them later on
+ */
+void __init pcm970_baseboard_init(void)
+{
+}
diff --git a/arch/arm/mach-mx2/serial.c b/arch/arm/mach-mx2/serial.c
new file mode 100644
index 000000000000..570c02b8e5df
--- /dev/null
+++ b/arch/arm/mach-mx2/serial.c
@@ -0,0 +1,177 @@
+/*
+ * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/serial.h>
+#include <asm/hardware.h>
+#include <asm/arch/imx-uart.h>
+
+static struct resource uart0[] = {
+        {
+                .start = UART1_BASE_ADDR,
+                .end = UART1_BASE_ADDR + 0x0B5,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_UART1,
+                .end = MXC_INT_UART1,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mxc_uart_device0 = {
+        .name = "imx-uart",
+        .id = 0,
+        .resource = uart0,
+        .num_resources = ARRAY_SIZE(uart0),
+};
+
+static struct resource uart1[] = {
+        {
+                .start = UART2_BASE_ADDR,
+                .end = UART2_BASE_ADDR + 0x0B5,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_UART2,
+                .end = MXC_INT_UART2,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mxc_uart_device1 = {
+        .name = "imx-uart",
+        .id = 1,
+        .resource = uart1,
+        .num_resources = ARRAY_SIZE(uart1),
+};
+
+static struct resource uart2[] = {
+        {
+                .start = UART3_BASE_ADDR,
+                .end = UART3_BASE_ADDR + 0x0B5,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_UART3,
+                .end = MXC_INT_UART3,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mxc_uart_device2 = {
+        .name = "imx-uart",
+        .id = 2,
+        .resource = uart2,
+        .num_resources = ARRAY_SIZE(uart2),
+};
+
+static struct resource uart3[] = {
+        {
+                .start = UART4_BASE_ADDR,
+                .end = UART4_BASE_ADDR + 0x0B5,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_UART4,
+                .end = MXC_INT_UART4,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mxc_uart_device3 = {
+        .name = "imx-uart",
+        .id = 3,
+        .resource = uart3,
+        .num_resources = ARRAY_SIZE(uart3),
+};
+
+static struct resource uart4[] = {
+        {
+                .start = UART5_BASE_ADDR,
+                .end = UART5_BASE_ADDR + 0x0B5,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_UART5,
+                .end = MXC_INT_UART5,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mxc_uart_device4 = {
+        .name = "imx-uart",
+        .id = 4,
+        .resource = uart4,
+        .num_resources = ARRAY_SIZE(uart4),
+};
+
+static struct resource uart5[] = {
+        {
+                .start = UART6_BASE_ADDR,
+                .end = UART6_BASE_ADDR + 0x0B5,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_UART6,
+                .end = MXC_INT_UART6,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mxc_uart_device5 = {
+        .name = "imx-uart",
+        .id = 5,
+        .resource = uart5,
+        .num_resources = ARRAY_SIZE(uart5),
+};
+
+/*
+ * Register only those UARTs that physically exists
+ */
+int __init imx_init_uart(int uart_no, struct imxuart_platform_data *pdata)
+{
+        switch (uart_no) {
+        case 0:
+                mxc_uart_device0.dev.platform_data = pdata;
+                platform_device_register(&mxc_uart_device0);
+                break;
+        case 1:
+                mxc_uart_device1.dev.platform_data = pdata;
+                platform_device_register(&mxc_uart_device1);
+                break;
+#ifndef CONFIG_MXC_IRDA
+        case 2:
+                mxc_uart_device2.dev.platform_data = pdata;
+                platform_device_register(&mxc_uart_device2);
+                break;
+#endif
+        case 3:
+                mxc_uart_device3.dev.platform_data = pdata;
+                platform_device_register(&mxc_uart_device3);
+                break;
+        case 4:
+                mxc_uart_device4.dev.platform_data = pdata;
+                platform_device_register(&mxc_uart_device4);
+                break;
+        case 5:
+                mxc_uart_device5.dev.platform_data = pdata;
+                platform_device_register(&mxc_uart_device5);
+                break;
+        default:
+                return -ENODEV;
+        }
+
+        return 0;
+}
diff --git a/arch/arm/mach-mx2/system.c b/arch/arm/mach-mx2/system.c
new file mode 100644
index 000000000000..99304645299d
--- /dev/null
+++ b/arch/arm/mach-mx2/system.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright (C) 1999 ARM Limited
+ * Copyright (C) 2000 Deep Blue Solutions Ltd
+ * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <asm/arch/hardware.h>
+#include <asm/proc-fns.h>
+#include <asm/system.h>
+
+/*
+ * Put the CPU into idle mode. It is called by default_idle()
+ * in process.c file.
+ */
+void arch_idle(void)
+{
+        /*
+         * This should do all the clock switching
+         * and wait for interrupt tricks.
+         */
+        cpu_do_idle();
+}
+
+#define WDOG_WCR_REG                    IO_ADDRESS(WDOG_BASE_ADDR)
+#define WDOG_WCR_SRS                    (1 << 4)
+
+/*
+ * Reset the system. It is called by machine_restart().
+ */
+void arch_reset(char mode)
+{
+        struct clk *clk;
+
+        clk = clk_get(NULL, "wdog_clk");
+        if (!clk) {
+                printk(KERN_ERR"Cannot activate the watchdog. Giving up\n");
+                return;
+        }
+
+        clk_enable(clk);
+
+        /* Assert SRS signal */
+        __raw_writew(__raw_readw(WDOG_WCR_REG) & ~WDOG_WCR_SRS, WDOG_WCR_REG);
+}
diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
index 5fe8606cac08..db9431dee1b4 100644
--- a/arch/arm/mach-mx3/Kconfig
+++ b/arch/arm/mach-mx3/Kconfig
@@ -8,5 +8,18 @@ config MACH_MX31ADS
           Include support for MX31ADS platform. This includes specific
           configurations for the board and its peripherals.
 
+config MACH_PCM037
+        bool "Support Phytec pcm037 platforms"
+        help
+          Include support for Phytec pcm037 platform. This includes
+          specific configurations for the board and its peripherals.
+
+config MACH_MX31LITE
+        bool "Support MX31 LITEKIT (LogicPD)"
+        default n
+        help
+          Include support for MX31 LITEKIT platform. This includes specific
+          configurations for the board and its peripherals.
+
 endmenu
 
diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile
index cbec997f332a..8b21abb71fb0 100644
--- a/arch/arm/mach-mx3/Makefile
+++ b/arch/arm/mach-mx3/Makefile
@@ -4,5 +4,7 @@
 
 # Object file lists.
 
-obj-y                   := mm.o time.o
+obj-y                   := mm.o clock.o devices.o iomux.o
 obj-$(CONFIG_MACH_MX31ADS)      += mx31ads.o
+obj-$(CONFIG_MACH_MX31LITE)     += mx31lite.o
+obj-$(CONFIG_MACH_PCM037)       += pcm037.o
diff --git a/arch/arm/mach-mx3/clock.c b/arch/arm/mach-mx3/clock.c
new file mode 100644
index 000000000000..2f3635943e70
--- /dev/null
+++ b/arch/arm/mach-mx3/clock.c
@@ -0,0 +1,1147 @@
+/*
+ * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/spinlock.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <asm/arch/clock.h>
+#include <asm/div64.h>
+
+#include "crm_regs.h"
+
+#define PRE_DIV_MIN_FREQ    10000000 /* Minimum Frequency after Predivider */
+
+static void __calc_pre_post_dividers(u32 div, u32 *pre, u32 *post)
+{
+        u32 min_pre, temp_pre, old_err, err;
+
+        if (div >= 512) {
+                *pre = 8;
+                *post = 64;
+        } else if (div >= 64) {
+                min_pre = (div - 1) / 64 + 1;
+                old_err = 8;
+                for (temp_pre = 8; temp_pre >= min_pre; temp_pre--) {
+                        err = div % temp_pre;
+                        if (err == 0) {
+                                *pre = temp_pre;
+                                break;
+                        }
+                        err = temp_pre - err;
+                        if (err < old_err) {
+                                old_err = err;
+                                *pre = temp_pre;
+                        }
+                }
+                *post = (div + *pre - 1) / *pre;
+        } else if (div <= 8) {
+                *pre = div;
+                *post = 1;
+        } else {
+                *pre = 1;
+                *post = div;
+        }
+}
+
+static struct clk mcu_pll_clk;
+static struct clk mcu_main_clk;
+static struct clk usb_pll_clk;
+static struct clk serial_pll_clk;
+static struct clk ipg_clk;
+static struct clk ckih_clk;
+static struct clk ahb_clk;
+
+static int _clk_enable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(clk->enable_reg);
+        reg |= 3 << clk->enable_shift;
+        __raw_writel(reg, clk->enable_reg);
+
+        return 0;
+}
+
+static void _clk_disable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(clk->enable_reg);
+        reg &= ~(3 << clk->enable_shift);
+        __raw_writel(reg, clk->enable_reg);
+}
+
+static void _clk_emi_disable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(clk->enable_reg);
+        reg &= ~(3 << clk->enable_shift);
+        reg |= (1 << clk->enable_shift);
+        __raw_writel(reg, clk->enable_reg);
+}
+
+static int _clk_pll_set_rate(struct clk *clk, unsigned long rate)
+{
+        u32 reg;
+        signed long pd = 1;     /* Pre-divider */
+        signed long mfi;        /* Multiplication Factor (Integer part) */
+        signed long mfn;        /* Multiplication Factor (Integer part) */
+        signed long mfd;        /* Multiplication Factor (Denominator Part) */
+        signed long tmp;
+        u32 ref_freq = clk_get_rate(clk->parent);
+
+        while (((ref_freq / pd) * 10) > rate)
+                pd++;
+
+        if ((ref_freq / pd) < PRE_DIV_MIN_FREQ)
+                return -EINVAL;
+
+        /* the ref_freq/2 in the following is to round up */
+        mfi = (((rate / 2) * pd) + (ref_freq / 2)) / ref_freq;
+        if (mfi < 5 || mfi > 15)
+                return -EINVAL;
+
+        /* pick a mfd value that will work
+         * then solve for mfn */
+        mfd = ref_freq / 50000;
+
+        /*
+         *          pll_freq * pd * mfd
+         *   mfn = --------------------  -  (mfi * mfd)
+         *           2 * ref_freq
+         */
+        /* the tmp/2 is for rounding */
+        tmp = ref_freq / 10000;
+        mfn =
+            ((((((rate / 2) + (tmp / 2)) / tmp) * pd) * mfd) / 10000) -
+            (mfi * mfd);
+
+        mfn = mfn & 0x3ff;
+        pd--;
+        mfd--;
+
+        /* Change the Pll value */
+        reg = (mfi << MXC_CCM_PCTL_MFI_OFFSET) |
+            (mfn << MXC_CCM_PCTL_MFN_OFFSET) |
+            (mfd << MXC_CCM_PCTL_MFD_OFFSET) | (pd << MXC_CCM_PCTL_PD_OFFSET);
+
+        if (clk == &mcu_pll_clk)
+                __raw_writel(reg, MXC_CCM_MPCTL);
+        else if (clk == &usb_pll_clk)
+                __raw_writel(reg, MXC_CCM_UPCTL);
+        else if (clk == &serial_pll_clk)
+                __raw_writel(reg, MXC_CCM_SRPCTL);
+
+        return 0;
+}
+
+static unsigned long _clk_pll_get_rate(struct clk *clk)
+{
+        long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;
+        unsigned long reg, ccmr;
+        s64 temp;
+        unsigned int prcs;
+
+        ccmr = __raw_readl(MXC_CCM_CCMR);
+        prcs = (ccmr & MXC_CCM_CCMR_PRCS_MASK) >> MXC_CCM_CCMR_PRCS_OFFSET;
+        if (prcs == 0x1)
+                ref_clk = CKIL_CLK_FREQ * 1024;
+        else
+                ref_clk = clk_get_rate(&ckih_clk);
+
+        if (clk == &mcu_pll_clk) {
+                if ((ccmr & MXC_CCM_CCMR_MPE) == 0)
+                        return ref_clk;
+                if ((ccmr & MXC_CCM_CCMR_MDS) != 0)
+                        return ref_clk;
+                reg = __raw_readl(MXC_CCM_MPCTL);
+        } else if (clk == &usb_pll_clk)
+                reg = __raw_readl(MXC_CCM_UPCTL);
+        else if (clk == &serial_pll_clk)
+                reg = __raw_readl(MXC_CCM_SRPCTL);
+        else {
+                BUG();
+                return 0;
+        }
+
+        pdf = (reg & MXC_CCM_PCTL_PD_MASK) >> MXC_CCM_PCTL_PD_OFFSET;
+        mfd = (reg & MXC_CCM_PCTL_MFD_MASK) >> MXC_CCM_PCTL_MFD_OFFSET;
+        mfi = (reg & MXC_CCM_PCTL_MFI_MASK) >> MXC_CCM_PCTL_MFI_OFFSET;
+        mfi = (mfi <= 5) ? 5 : mfi;
+        mfn = mfn_abs = reg & MXC_CCM_PCTL_MFN_MASK;
+
+        if (mfn >= 0x200) {
+                mfn |= 0xFFFFFE00;
+                mfn_abs = -mfn;
+        }
+
+        ref_clk *= 2;
+        ref_clk /= pdf + 1;
+
+        temp = (u64) ref_clk * mfn_abs;
+        do_div(temp, mfd + 1);
+        if (mfn < 0)
+                temp = -temp;
+        temp = (ref_clk * mfi) + temp;
+
+        return temp;
+}
+
+static int _clk_usb_pll_enable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(MXC_CCM_CCMR);
+        reg |= MXC_CCM_CCMR_UPE;
+        __raw_writel(reg, MXC_CCM_CCMR);
+
+        /* No lock bit on MX31, so using max time from spec */
+        udelay(80);
+
+        return 0;
+}
+
+static void _clk_usb_pll_disable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(MXC_CCM_CCMR);
+        reg &= ~MXC_CCM_CCMR_UPE;
+        __raw_writel(reg, MXC_CCM_CCMR);
+}
+
+static int _clk_serial_pll_enable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(MXC_CCM_CCMR);
+        reg |= MXC_CCM_CCMR_SPE;
+        __raw_writel(reg, MXC_CCM_CCMR);
+
+        /* No lock bit on MX31, so using max time from spec */
+        udelay(80);
+
+        return 0;
+}
+
+static void _clk_serial_pll_disable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(MXC_CCM_CCMR);
+        reg &= ~MXC_CCM_CCMR_SPE;
+        __raw_writel(reg, MXC_CCM_CCMR);
+}
+
+#define PDR0(mask, off) ((__raw_readl(MXC_CCM_PDR0) & mask) >> off)
+#define PDR1(mask, off) ((__raw_readl(MXC_CCM_PDR1) & mask) >> off)
+#define PDR2(mask, off) ((__raw_readl(MXC_CCM_PDR2) & mask) >> off)
+
+static unsigned long _clk_mcu_main_get_rate(struct clk *clk)
+{
+        u32 pmcr0 = __raw_readl(MXC_CCM_PMCR0);
+
+        if ((pmcr0 & MXC_CCM_PMCR0_DFSUP1) == MXC_CCM_PMCR0_DFSUP1_SPLL)
+                return clk_get_rate(&serial_pll_clk);
+        else
+                return clk_get_rate(&mcu_pll_clk);
+}
+
+static unsigned long _clk_hclk_get_rate(struct clk *clk)
+{
+        unsigned long max_pdf;
+
+        max_pdf = PDR0(MXC_CCM_PDR0_MAX_PODF_MASK,
+                       MXC_CCM_PDR0_MAX_PODF_OFFSET);
+        return clk_get_rate(clk->parent) / (max_pdf + 1);
+}
+
+static unsigned long _clk_ipg_get_rate(struct clk *clk)
+{
+        unsigned long ipg_pdf;
+
+        ipg_pdf = PDR0(MXC_CCM_PDR0_IPG_PODF_MASK,
+                       MXC_CCM_PDR0_IPG_PODF_OFFSET);
+        return clk_get_rate(clk->parent) / (ipg_pdf + 1);
+}
+
+static unsigned long _clk_nfc_get_rate(struct clk *clk)
+{
+        unsigned long nfc_pdf;
+
+        nfc_pdf = PDR0(MXC_CCM_PDR0_NFC_PODF_MASK,
+                       MXC_CCM_PDR0_NFC_PODF_OFFSET);
+        return clk_get_rate(clk->parent) / (nfc_pdf + 1);
+}
+
+static unsigned long _clk_hsp_get_rate(struct clk *clk)
+{
+        unsigned long hsp_pdf;
+
+        hsp_pdf = PDR0(MXC_CCM_PDR0_HSP_PODF_MASK,
+                       MXC_CCM_PDR0_HSP_PODF_OFFSET);
+        return clk_get_rate(clk->parent) / (hsp_pdf + 1);
+}
+
+static unsigned long _clk_usb_get_rate(struct clk *clk)
+{
+        unsigned long usb_pdf, usb_prepdf;
+
+        usb_pdf = PDR1(MXC_CCM_PDR1_USB_PODF_MASK,
+                       MXC_CCM_PDR1_USB_PODF_OFFSET);
+        usb_prepdf = PDR1(MXC_CCM_PDR1_USB_PRDF_MASK,
+                          MXC_CCM_PDR1_USB_PRDF_OFFSET);
+        return clk_get_rate(clk->parent) / (usb_prepdf + 1) / (usb_pdf + 1);
+}
+
+static unsigned long _clk_csi_get_rate(struct clk *clk)
+{
+        u32 reg, pre, post;
+
+        reg = __raw_readl(MXC_CCM_PDR0);
+        pre = (reg & MXC_CCM_PDR0_CSI_PRDF_MASK) >>
+            MXC_CCM_PDR0_CSI_PRDF_OFFSET;
+        pre++;
+        post = (reg & MXC_CCM_PDR0_CSI_PODF_MASK) >>
+            MXC_CCM_PDR0_CSI_PODF_OFFSET;
+        post++;
+        return clk_get_rate(clk->parent) / (pre * post);
+}
+
+static unsigned long _clk_csi_round_rate(struct clk *clk, unsigned long rate)
+{
+        u32 pre, post, parent = clk_get_rate(clk->parent);
+        u32 div = parent / rate;
+
+        if (parent % rate)
+                div++;
+
+        __calc_pre_post_dividers(div, &pre, &post);
+
+        return parent / (pre * post);
+}
+
+static int _clk_csi_set_rate(struct clk *clk, unsigned long rate)
+{
+        u32 reg, div, pre, post, parent = clk_get_rate(clk->parent);
+
+        div = parent / rate;
+
+        if ((parent / div) != rate)
+                return -EINVAL;
+
+        __calc_pre_post_dividers(div, &pre, &post);
+
+        /* Set CSI clock divider */
+        reg = __raw_readl(MXC_CCM_PDR0) &
+            ~(MXC_CCM_PDR0_CSI_PODF_MASK | MXC_CCM_PDR0_CSI_PRDF_MASK);
+        reg |= (post - 1) << MXC_CCM_PDR0_CSI_PODF_OFFSET;
+        reg |= (pre - 1) << MXC_CCM_PDR0_CSI_PRDF_OFFSET;
+        __raw_writel(reg, MXC_CCM_PDR0);
+
+        return 0;
+}
+
+static unsigned long _clk_per_get_rate(struct clk *clk)
+{
+        unsigned long per_pdf;
+
+        per_pdf = PDR0(MXC_CCM_PDR0_PER_PODF_MASK,
+                       MXC_CCM_PDR0_PER_PODF_OFFSET);
+        return clk_get_rate(clk->parent) / (per_pdf + 1);
+}
+
+static unsigned long _clk_ssi1_get_rate(struct clk *clk)
+{
+        unsigned long ssi1_pdf, ssi1_prepdf;
+
+        ssi1_pdf = PDR1(MXC_CCM_PDR1_SSI1_PODF_MASK,
+                        MXC_CCM_PDR1_SSI1_PODF_OFFSET);
+        ssi1_prepdf = PDR1(MXC_CCM_PDR1_SSI1_PRE_PODF_MASK,
+                           MXC_CCM_PDR1_SSI1_PRE_PODF_OFFSET);
+        return clk_get_rate(clk->parent) / (ssi1_prepdf + 1) / (ssi1_pdf + 1);
+}
+
+static unsigned long _clk_ssi2_get_rate(struct clk *clk)
+{
+        unsigned long ssi2_pdf, ssi2_prepdf;
+
+        ssi2_pdf = PDR1(MXC_CCM_PDR1_SSI2_PODF_MASK,
+                        MXC_CCM_PDR1_SSI2_PODF_OFFSET);
+        ssi2_prepdf = PDR1(MXC_CCM_PDR1_SSI2_PRE_PODF_MASK,
+                           MXC_CCM_PDR1_SSI2_PRE_PODF_OFFSET);
+        return clk_get_rate(clk->parent) / (ssi2_prepdf + 1) / (ssi2_pdf + 1);
+}
+
+static unsigned long _clk_firi_get_rate(struct clk *clk)
+{
+        unsigned long firi_pdf, firi_prepdf;
+
+        firi_pdf = PDR1(MXC_CCM_PDR1_FIRI_PODF_MASK,
+                        MXC_CCM_PDR1_FIRI_PODF_OFFSET);
+        firi_prepdf = PDR1(MXC_CCM_PDR1_FIRI_PRE_PODF_MASK,
+                           MXC_CCM_PDR1_FIRI_PRE_PODF_OFFSET);
+        return clk_get_rate(clk->parent) / (firi_prepdf + 1) / (firi_pdf + 1);
+}
+
+static unsigned long _clk_firi_round_rate(struct clk *clk, unsigned long rate)
+{
+        u32 pre, post;
+        u32 parent = clk_get_rate(clk->parent);
+        u32 div = parent / rate;
+
+        if (parent % rate)
+                div++;
+
+        __calc_pre_post_dividers(div, &pre, &post);
+
+        return parent / (pre * post);
+
+}
+
+static int _clk_firi_set_rate(struct clk *clk, unsigned long rate)
+{
+        u32 reg, div, pre, post, parent = clk_get_rate(clk->parent);
+
+        div = parent / rate;
+
+        if ((parent / div) != rate)
+                return -EINVAL;
+
+        __calc_pre_post_dividers(div, &pre, &post);
+
+        /* Set FIRI clock divider */
+        reg = __raw_readl(MXC_CCM_PDR1) &
+            ~(MXC_CCM_PDR1_FIRI_PODF_MASK | MXC_CCM_PDR1_FIRI_PRE_PODF_MASK);
+        reg |= (pre - 1) << MXC_CCM_PDR1_FIRI_PRE_PODF_OFFSET;
+        reg |= (post - 1) << MXC_CCM_PDR1_FIRI_PODF_OFFSET;
+        __raw_writel(reg, MXC_CCM_PDR1);
+
+        return 0;
+}
+
+static unsigned long _clk_mbx_get_rate(struct clk *clk)
+{
+        return clk_get_rate(clk->parent) / 2;
+}
+
+static unsigned long _clk_mstick1_get_rate(struct clk *clk)
+{
+        unsigned long msti_pdf;
+
+        msti_pdf = PDR2(MXC_CCM_PDR2_MST1_PDF_MASK,
+                        MXC_CCM_PDR2_MST1_PDF_OFFSET);
+        return clk_get_rate(clk->parent) / (msti_pdf + 1);
+}
+
+static unsigned long _clk_mstick2_get_rate(struct clk *clk)
+{
+        unsigned long msti_pdf;
+
+        msti_pdf = PDR2(MXC_CCM_PDR2_MST2_PDF_MASK,
+                        MXC_CCM_PDR2_MST2_PDF_OFFSET);
+        return clk_get_rate(clk->parent) / (msti_pdf + 1);
+}
+
+static unsigned long ckih_rate;
+
+static unsigned long clk_ckih_get_rate(struct clk *clk)
+{
+        return ckih_rate;
+}
+
+static struct clk ckih_clk = {
+        .name = "ckih",
+        .get_rate = clk_ckih_get_rate,
+};
+
+static unsigned long clk_ckil_get_rate(struct clk *clk)
+{
+        return CKIL_CLK_FREQ;
+}
+
+static struct clk ckil_clk = {
+        .name = "ckil",
+        .get_rate = clk_ckil_get_rate,
+};
+
+static struct clk mcu_pll_clk = {
+        .name = "mcu_pll",
+        .parent = &ckih_clk,
+        .set_rate = _clk_pll_set_rate,
+        .get_rate = _clk_pll_get_rate,
+};
+
+static struct clk mcu_main_clk = {
+        .name = "mcu_main_clk",
+        .parent = &mcu_pll_clk,
+        .get_rate = _clk_mcu_main_get_rate,
+};
+
+static struct clk serial_pll_clk = {
+        .name = "serial_pll",
+        .parent = &ckih_clk,
+        .set_rate = _clk_pll_set_rate,
+        .get_rate = _clk_pll_get_rate,
+        .enable = _clk_serial_pll_enable,
+        .disable = _clk_serial_pll_disable,
+};
+
+static struct clk usb_pll_clk = {
+        .name = "usb_pll",
+        .parent = &ckih_clk,
+        .set_rate = _clk_pll_set_rate,
+        .get_rate = _clk_pll_get_rate,
+        .enable = _clk_usb_pll_enable,
+        .disable = _clk_usb_pll_disable,
+};
+
+static struct clk ahb_clk = {
+        .name = "ahb_clk",
+        .parent = &mcu_main_clk,
+        .get_rate = _clk_hclk_get_rate,
+};
+
+static struct clk per_clk = {
+        .name = "per_clk",
+        .parent = &usb_pll_clk,
+        .get_rate = _clk_per_get_rate,
+};
+
+static struct clk perclk_clk = {
+        .name = "perclk_clk",
+        .parent = &ipg_clk,
+};
+
+static struct clk cspi_clk[] = {
+        {
+         .name = "cspi_clk",
+         .id = 0,
+         .parent = &ipg_clk,
+         .enable = _clk_enable,
+         .enable_reg = MXC_CCM_CGR2,
+         .enable_shift = MXC_CCM_CGR2_CSPI1_OFFSET,
+         .disable = _clk_disable,},
+        {
+         .name = "cspi_clk",
+         .id = 1,
+         .parent = &ipg_clk,
+         .enable = _clk_enable,
+         .enable_reg = MXC_CCM_CGR2,
+         .enable_shift = MXC_CCM_CGR2_CSPI2_OFFSET,
+         .disable = _clk_disable,},
+        {
+         .name = "cspi_clk",
+         .id = 2,
+         .parent = &ipg_clk,
+         .enable = _clk_enable,
+         .enable_reg = MXC_CCM_CGR0,
+         .enable_shift = MXC_CCM_CGR0_CSPI3_OFFSET,
+         .disable = _clk_disable,},
+};
+
+static struct clk ipg_clk = {
+        .name = "ipg_clk",
+        .parent = &ahb_clk,
+        .get_rate = _clk_ipg_get_rate,
+};
+
+static struct clk emi_clk = {
+        .name = "emi_clk",
+        .parent = &ahb_clk,
+        .enable = _clk_enable,
+        .enable_reg = MXC_CCM_CGR2,
+        .enable_shift = MXC_CCM_CGR2_EMI_OFFSET,
+        .disable = _clk_emi_disable,
+};
+
+static struct clk gpt_clk = {
+        .name = "gpt_clk",
+        .parent = &perclk_clk,
+        .enable = _clk_enable,
+        .enable_reg = MXC_CCM_CGR0,
+        .enable_shift = MXC_CCM_CGR0_GPT_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk pwm_clk = {
+        .name = "pwm_clk",
+        .parent = &perclk_clk,
+        .enable = _clk_enable,
+        .enable_reg = MXC_CCM_CGR0,
+        .enable_shift = MXC_CCM_CGR1_PWM_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk epit_clk[] = {
+        {
+         .name = "epit_clk",
+         .id = 0,
+         .parent = &perclk_clk,
+         .enable = _clk_enable,
+         .enable_reg = MXC_CCM_CGR0,
+         .enable_shift = MXC_CCM_CGR0_EPIT1_OFFSET,
+         .disable = _clk_disable,},
+        {
+         .name = "epit_clk",
+         .id = 1,
+         .parent = &perclk_clk,
+         .enable = _clk_enable,
+         .enable_reg = MXC_CCM_CGR0,
+         .enable_shift = MXC_CCM_CGR0_EPIT2_OFFSET,
+         .disable = _clk_disable,},
+};
+
+static struct clk nfc_clk = {
+        .name = "nfc_clk",
+        .parent = &ahb_clk,
+        .get_rate = _clk_nfc_get_rate,
+};
+
+static struct clk scc_clk = {
+        .name = "scc_clk",
+        .parent = &ipg_clk,
+};
+
+static struct clk ipu_clk = {
+        .name = "ipu_clk",
+        .parent = &mcu_main_clk,
+        .get_rate = _clk_hsp_get_rate,
+        .enable = _clk_enable,
+        .enable_reg = MXC_CCM_CGR1,
+        .enable_shift = MXC_CCM_CGR1_IPU_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk kpp_clk = {
+        .name = "kpp_clk",
+        .parent = &ipg_clk,
+        .enable = _clk_enable,
+        .enable_reg = MXC_CCM_CGR1,
+        .enable_shift = MXC_CCM_CGR1_KPP_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk wdog_clk = {
+        .name = "wdog_clk",
+        .parent = &ipg_clk,
+        .enable = _clk_enable,
+        .enable_reg = MXC_CCM_CGR1,
+        .enable_shift = MXC_CCM_CGR1_WDOG_OFFSET,
+        .disable = _clk_disable,
+};
+static struct clk rtc_clk = {
+        .name = "rtc_clk",
+        .parent = &ipg_clk,
+        .enable = _clk_enable,
+        .enable_reg = MXC_CCM_CGR1,
+        .enable_shift = MXC_CCM_CGR1_RTC_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk usb_clk[] = {
+        {
+         .name = "usb_clk",
+         .parent = &usb_pll_clk,
+         .get_rate = _clk_usb_get_rate,},
+        {
+         .name = "usb_ahb_clk",
+         .parent = &ahb_clk,
+         .enable = _clk_enable,
+         .enable_reg = MXC_CCM_CGR1,
+         .enable_shift = MXC_CCM_CGR1_USBOTG_OFFSET,
+         .disable = _clk_disable,},
+};
+
+static struct clk csi_clk = {
+        .name = "csi_clk",
+        .parent = &serial_pll_clk,
+        .get_rate = _clk_csi_get_rate,
+        .round_rate = _clk_csi_round_rate,
+        .set_rate = _clk_csi_set_rate,
+        .enable = _clk_enable,
+        .enable_reg = MXC_CCM_CGR1,
+        .enable_shift = MXC_CCM_CGR1_CSI_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk uart_clk[] = {
+        {
+         .name = "uart_clk",
+         .id = 0,
+         .parent = &perclk_clk,
+         .enable = _clk_enable,
+         .enable_reg = MXC_CCM_CGR0,
+         .enable_shift = MXC_CCM_CGR0_UART1_OFFSET,
+         .disable = _clk_disable,},
+        {
+         .name = "uart_clk",
+         .id = 1,
+         .parent = &perclk_clk,
+         .enable = _clk_enable,
+         .enable_reg = MXC_CCM_CGR0,
+         .enable_shift = MXC_CCM_CGR0_UART2_OFFSET,
+         .disable = _clk_disable,},
+        {
+         .name = "uart_clk",
+         .id = 2,
+         .parent = &perclk_clk,
+         .enable = _clk_enable,
+         .enable_reg = MXC_CCM_CGR1,
+         .enable_shift = MXC_CCM_CGR1_UART3_OFFSET,
+         .disable = _clk_disable,},
+        {
+         .name = "uart_clk",
+         .id = 3,
+         .parent = &perclk_clk,
+         .enable = _clk_enable,
+         .enable_reg = MXC_CCM_CGR1,
+         .enable_shift = MXC_CCM_CGR1_UART4_OFFSET,
+         .disable = _clk_disable,},
+        {
+         .name = "uart_clk",
+         .id = 4,
+         .parent = &perclk_clk,
+         .enable = _clk_enable,
+         .enable_reg = MXC_CCM_CGR1,
+         .enable_shift = MXC_CCM_CGR1_UART5_OFFSET,
+         .disable = _clk_disable,},
+};
+
+static struct clk i2c_clk[] = {
+        {
+         .name = "i2c_clk",
+         .id = 0,
+         .parent = &perclk_clk,
+         .enable = _clk_enable,
+         .enable_reg = MXC_CCM_CGR0,
+         .enable_shift = MXC_CCM_CGR0_I2C1_OFFSET,
+         .disable = _clk_disable,},
+        {
+         .name = "i2c_clk",
+         .id = 1,
+         .parent = &perclk_clk,
+         .enable = _clk_enable,
+         .enable_reg = MXC_CCM_CGR0,
+         .enable_shift = MXC_CCM_CGR0_I2C2_OFFSET,
+         .disable = _clk_disable,},
+        {
+         .name = "i2c_clk",
+         .id = 2,
+         .parent = &perclk_clk,
+         .enable = _clk_enable,
+         .enable_reg = MXC_CCM_CGR0,
+         .enable_shift = MXC_CCM_CGR0_I2C3_OFFSET,
+         .disable = _clk_disable,},
+};
+
+static struct clk owire_clk = {
+        .name = "owire_clk",
+        .parent = &perclk_clk,
+        .enable_reg = MXC_CCM_CGR1,
+        .enable_shift = MXC_CCM_CGR1_OWIRE_OFFSET,
+        .enable = _clk_enable,
+        .disable = _clk_disable,
+};
+
+static struct clk sdhc_clk[] = {
+        {
+         .name = "sdhc_clk",
+         .id = 0,
+         .parent = &perclk_clk,
+         .enable = _clk_enable,
+         .enable_reg = MXC_CCM_CGR0,
+         .enable_shift = MXC_CCM_CGR0_SD_MMC1_OFFSET,
+         .disable = _clk_disable,},
+        {
+         .name = "sdhc_clk",
+         .id = 1,
+         .parent = &perclk_clk,
+         .enable = _clk_enable,
+         .enable_reg = MXC_CCM_CGR0,
+         .enable_shift = MXC_CCM_CGR0_SD_MMC2_OFFSET,
+         .disable = _clk_disable,},
+};
+
+static struct clk ssi_clk[] = {
+        {
+         .name = "ssi_clk",
+         .parent = &serial_pll_clk,
+         .get_rate = _clk_ssi1_get_rate,
+         .enable = _clk_enable,
+         .enable_reg = MXC_CCM_CGR0,
+         .enable_shift = MXC_CCM_CGR0_SSI1_OFFSET,
+         .disable = _clk_disable,},
+        {
+         .name = "ssi_clk",
+         .id = 1,
+         .parent = &serial_pll_clk,
+         .get_rate = _clk_ssi2_get_rate,
+         .enable = _clk_enable,
+         .enable_reg = MXC_CCM_CGR2,
+         .enable_shift = MXC_CCM_CGR2_SSI2_OFFSET,
+         .disable = _clk_disable,},
+};
+
+static struct clk firi_clk = {
+        .name = "firi_clk",
+        .parent = &usb_pll_clk,
+        .round_rate = _clk_firi_round_rate,
+        .set_rate = _clk_firi_set_rate,
+        .get_rate = _clk_firi_get_rate,
+        .enable = _clk_enable,
+        .enable_reg = MXC_CCM_CGR2,
+        .enable_shift = MXC_CCM_CGR2_FIRI_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk ata_clk = {
+        .name = "ata_clk",
+        .parent = &ipg_clk,
+        .enable = _clk_enable,
+        .enable_reg = MXC_CCM_CGR0,
+        .enable_shift = MXC_CCM_CGR0_ATA_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk mbx_clk = {
+        .name = "mbx_clk",
+        .parent = &ahb_clk,
+        .enable = _clk_enable,
+        .enable_reg = MXC_CCM_CGR2,
+        .enable_shift = MXC_CCM_CGR2_GACC_OFFSET,
+        .get_rate = _clk_mbx_get_rate,
+};
+
+static struct clk vpu_clk = {
+        .name = "vpu_clk",
+        .parent = &ahb_clk,
+        .enable = _clk_enable,
+        .enable_reg = MXC_CCM_CGR2,
+        .enable_shift = MXC_CCM_CGR2_GACC_OFFSET,
+        .get_rate = _clk_mbx_get_rate,
+};
+
+static struct clk rtic_clk = {
+        .name = "rtic_clk",
+        .parent = &ahb_clk,
+        .enable = _clk_enable,
+        .enable_reg = MXC_CCM_CGR2,
+        .enable_shift = MXC_CCM_CGR2_RTIC_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk rng_clk = {
+        .name = "rng_clk",
+        .parent = &ipg_clk,
+        .enable = _clk_enable,
+        .enable_reg = MXC_CCM_CGR0,
+        .enable_shift = MXC_CCM_CGR0_RNG_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk sdma_clk[] = {
+        {
+         .name = "sdma_ahb_clk",
+         .parent = &ahb_clk,
+         .enable = _clk_enable,
+         .enable_reg = MXC_CCM_CGR0,
+         .enable_shift = MXC_CCM_CGR0_SDMA_OFFSET,
+         .disable = _clk_disable,},
+        {
+         .name = "sdma_ipg_clk",
+         .parent = &ipg_clk,}
+};
+
+static struct clk mpeg4_clk = {
+        .name = "mpeg4_clk",
+        .parent = &ahb_clk,
+        .enable = _clk_enable,
+        .enable_reg = MXC_CCM_CGR1,
+        .enable_shift = MXC_CCM_CGR1_HANTRO_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk vl2cc_clk = {
+        .name = "vl2cc_clk",
+        .parent = &ahb_clk,
+        .enable = _clk_enable,
+        .enable_reg = MXC_CCM_CGR1,
+        .enable_shift = MXC_CCM_CGR1_HANTRO_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk mstick_clk[] = {
+        {
+         .name = "mstick_clk",
+         .id = 0,
+         .parent = &usb_pll_clk,
+         .get_rate = _clk_mstick1_get_rate,
+         .enable = _clk_enable,
+         .enable_reg = MXC_CCM_CGR1,
+         .enable_shift = MXC_CCM_CGR1_MEMSTICK1_OFFSET,
+         .disable = _clk_disable,},
+        {
+         .name = "mstick_clk",
+         .id = 1,
+         .parent = &usb_pll_clk,
+         .get_rate = _clk_mstick2_get_rate,
+         .enable = _clk_enable,
+         .enable_reg = MXC_CCM_CGR1,
+         .enable_shift = MXC_CCM_CGR1_MEMSTICK2_OFFSET,
+         .disable = _clk_disable,},
+};
+
+static struct clk iim_clk = {
+        .name = "iim_clk",
+        .parent = &ipg_clk,
+        .enable = _clk_enable,
+        .enable_reg = MXC_CCM_CGR0,
+        .enable_shift = MXC_CCM_CGR0_IIM_OFFSET,
+        .disable = _clk_disable,
+};
+
+static unsigned long _clk_cko1_round_rate(struct clk *clk, unsigned long rate)
+{
+        u32 div, parent = clk_get_rate(clk->parent);
+
+        div = parent / rate;
+        if (parent % rate)
+                div++;
+
+        if (div > 8)
+                div = 16;
+        else if (div > 4)
+                div = 8;
+        else if (div > 2)
+                div = 4;
+
+        return parent / div;
+}
+
+static int _clk_cko1_set_rate(struct clk *clk, unsigned long rate)
+{
+        u32 reg, div, parent = clk_get_rate(clk->parent);
+
+        div = parent / rate;
+
+        if (div == 16)
+                div = 4;
+        else if (div == 8)
+                div = 3;
+        else if (div == 4)
+                div = 2;
+        else if (div == 2)
+                div = 1;
+        else if (div == 1)
+                div = 0;
+        else
+                return -EINVAL;
+
+        reg = __raw_readl(MXC_CCM_COSR) & ~MXC_CCM_COSR_CLKOUTDIV_MASK;
+        reg |= div << MXC_CCM_COSR_CLKOUTDIV_OFFSET;
+        __raw_writel(reg, MXC_CCM_COSR);
+
+        return 0;
+}
+
+static unsigned long _clk_cko1_get_rate(struct clk *clk)
+{
+        u32 div;
+
+        div = __raw_readl(MXC_CCM_COSR) & MXC_CCM_COSR_CLKOUTDIV_MASK >>
+            MXC_CCM_COSR_CLKOUTDIV_OFFSET;
+
+        return clk_get_rate(clk->parent) / (1 << div);
+}
+
+static int _clk_cko1_set_parent(struct clk *clk, struct clk *parent)
+{
+        u32 reg;
+
+        reg = __raw_readl(MXC_CCM_COSR) & ~MXC_CCM_COSR_CLKOSEL_MASK;
+
+        if (parent == &mcu_main_clk)
+                reg |= 0 << MXC_CCM_COSR_CLKOSEL_OFFSET;
+        else if (parent == &ipg_clk)
+                reg |= 1 << MXC_CCM_COSR_CLKOSEL_OFFSET;
+        else if (parent == &usb_pll_clk)
+                reg |= 2 << MXC_CCM_COSR_CLKOSEL_OFFSET;
+        else if (parent == mcu_main_clk.parent)
+                reg |= 3 << MXC_CCM_COSR_CLKOSEL_OFFSET;
+        else if (parent == &ahb_clk)
+                reg |= 5 << MXC_CCM_COSR_CLKOSEL_OFFSET;
+        else if (parent == &serial_pll_clk)
+                reg |= 7 << MXC_CCM_COSR_CLKOSEL_OFFSET;
+        else if (parent == &ckih_clk)
+                reg |= 8 << MXC_CCM_COSR_CLKOSEL_OFFSET;
+        else if (parent == &emi_clk)
+                reg |= 9 << MXC_CCM_COSR_CLKOSEL_OFFSET;
+        else if (parent == &ipu_clk)
+                reg |= 0xA << MXC_CCM_COSR_CLKOSEL_OFFSET;
+        else if (parent == &nfc_clk)
+                reg |= 0xB << MXC_CCM_COSR_CLKOSEL_OFFSET;
+        else if (parent == &uart_clk[0])
+                reg |= 0xC << MXC_CCM_COSR_CLKOSEL_OFFSET;
+        else
+                return -EINVAL;
+
+        __raw_writel(reg, MXC_CCM_COSR);
+
+        return 0;
+}
+
+static int _clk_cko1_enable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(MXC_CCM_COSR) | MXC_CCM_COSR_CLKOEN;
+        __raw_writel(reg, MXC_CCM_COSR);
+
+        return 0;
+}
+
+static void _clk_cko1_disable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(MXC_CCM_COSR) & ~MXC_CCM_COSR_CLKOEN;
+        __raw_writel(reg, MXC_CCM_COSR);
+}
+
+static struct clk cko1_clk = {
+        .name = "cko1_clk",
+        .get_rate = _clk_cko1_get_rate,
+        .set_rate = _clk_cko1_set_rate,
+        .round_rate = _clk_cko1_round_rate,
+        .set_parent = _clk_cko1_set_parent,
+        .enable = _clk_cko1_enable,
+        .disable = _clk_cko1_disable,
+};
+
+static struct clk *mxc_clks[] = {
+        &ckih_clk,
+        &ckil_clk,
+        &mcu_pll_clk,
+        &usb_pll_clk,
+        &serial_pll_clk,
+        &mcu_main_clk,
+        &ahb_clk,
+        &per_clk,
+        &perclk_clk,
+        &cko1_clk,
+        &emi_clk,
+        &cspi_clk[0],
+        &cspi_clk[1],
+        &cspi_clk[2],
+        &ipg_clk,
+        &gpt_clk,
+        &pwm_clk,
+        &wdog_clk,
+        &rtc_clk,
+        &epit_clk[0],
+        &epit_clk[1],
+        &nfc_clk,
+        &ipu_clk,
+        &kpp_clk,
+        &usb_clk[0],
+        &usb_clk[1],
+        &csi_clk,
+        &uart_clk[0],
+        &uart_clk[1],
+        &uart_clk[2],
+        &uart_clk[3],
+        &uart_clk[4],
+        &i2c_clk[0],
+        &i2c_clk[1],
+        &i2c_clk[2],
+        &owire_clk,
+        &sdhc_clk[0],
+        &sdhc_clk[1],
+        &ssi_clk[0],
+        &ssi_clk[1],
+        &firi_clk,
+        &ata_clk,
+        &rtic_clk,
+        &rng_clk,
+        &sdma_clk[0],
+        &sdma_clk[1],
+        &mstick_clk[0],
+        &mstick_clk[1],
+        &scc_clk,
+        &iim_clk,
+};
+
+int __init mxc_clocks_init(unsigned long fref)
+{
+        u32 reg;
+        struct clk **clkp;
+
+        ckih_rate = fref;
+
+        for (clkp = mxc_clks; clkp < mxc_clks + ARRAY_SIZE(mxc_clks); clkp++)
+                clk_register(*clkp);
+
+        if (cpu_is_mx31()) {
+                clk_register(&mpeg4_clk);
+                clk_register(&mbx_clk);
+        } else {
+                clk_register(&vpu_clk);
+                clk_register(&vl2cc_clk);
+        }
+
+        /* Turn off all possible clocks */
+        __raw_writel(MXC_CCM_CGR0_GPT_MASK, MXC_CCM_CGR0);
+        __raw_writel(0, MXC_CCM_CGR1);
+
+        __raw_writel(MXC_CCM_CGR2_EMI_MASK |
+                     MXC_CCM_CGR2_IPMUX1_MASK |
+                     MXC_CCM_CGR2_IPMUX2_MASK |
+                     MXC_CCM_CGR2_MXCCLKENSEL_MASK |    /* for MX32 */
+                     MXC_CCM_CGR2_CHIKCAMPEN_MASK |     /* for MX32 */
+                     MXC_CCM_CGR2_OVRVPUBUSY_MASK |     /* for MX32 */
+                     1 << 27 | 1 << 28, /* Bit 27 and 28 are not defined for
+                                           MX32, but still required to be set */
+                     MXC_CCM_CGR2);
+
+        clk_disable(&cko1_clk);
+        clk_disable(&usb_pll_clk);
+
+        pr_info("Clock input source is %ld\n", clk_get_rate(&ckih_clk));
+
+        clk_enable(&gpt_clk);
+        clk_enable(&emi_clk);
+        clk_enable(&iim_clk);
+
+        clk_enable(&serial_pll_clk);
+
+        if (mx31_revision() >= CHIP_REV_2_0) {
+                reg = __raw_readl(MXC_CCM_PMCR1);
+                /* No PLL restart on DVFS switch; enable auto EMI handshake */
+                reg |= MXC_CCM_PMCR1_PLLRDIS | MXC_CCM_PMCR1_EMIRQ_EN;
+                __raw_writel(reg, MXC_CCM_PMCR1);
+        }
+
+        return 0;
+}
+
diff --git a/arch/arm/mach-mx3/crm_regs.h b/arch/arm/mach-mx3/crm_regs.h
new file mode 100644
index 000000000000..4a0e0ede23bb
--- /dev/null
+++ b/arch/arm/mach-mx3/crm_regs.h
@@ -0,0 +1,401 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#ifndef __ARCH_ARM_MACH_MX3_CRM_REGS_H__
+#define __ARCH_ARM_MACH_MX3_CRM_REGS_H__
+
+#define CKIH_CLK_FREQ           26000000
+#define CKIH_CLK_FREQ_27MHZ     27000000
+#define CKIL_CLK_FREQ           32768
+
+#define MXC_CCM_BASE            IO_ADDRESS(CCM_BASE_ADDR)
+
+/* Register addresses */
+#define MXC_CCM_CCMR            (MXC_CCM_BASE + 0x00)
+#define MXC_CCM_PDR0            (MXC_CCM_BASE + 0x04)
+#define MXC_CCM_PDR1            (MXC_CCM_BASE + 0x08)
+#define MXC_CCM_RCSR            (MXC_CCM_BASE + 0x0C)
+#define MXC_CCM_MPCTL           (MXC_CCM_BASE + 0x10)
+#define MXC_CCM_UPCTL           (MXC_CCM_BASE + 0x14)
+#define MXC_CCM_SRPCTL          (MXC_CCM_BASE + 0x18)
+#define MXC_CCM_COSR            (MXC_CCM_BASE + 0x1C)
+#define MXC_CCM_CGR0            (MXC_CCM_BASE + 0x20)
+#define MXC_CCM_CGR1            (MXC_CCM_BASE + 0x24)
+#define MXC_CCM_CGR2            (MXC_CCM_BASE + 0x28)
+#define MXC_CCM_WIMR            (MXC_CCM_BASE + 0x2C)
+#define MXC_CCM_LDC             (MXC_CCM_BASE + 0x30)
+#define MXC_CCM_DCVR0           (MXC_CCM_BASE + 0x34)
+#define MXC_CCM_DCVR1           (MXC_CCM_BASE + 0x38)
+#define MXC_CCM_DCVR2           (MXC_CCM_BASE + 0x3C)
+#define MXC_CCM_DCVR3           (MXC_CCM_BASE + 0x40)
+#define MXC_CCM_LTR0            (MXC_CCM_BASE + 0x44)
+#define MXC_CCM_LTR1            (MXC_CCM_BASE + 0x48)
+#define MXC_CCM_LTR2            (MXC_CCM_BASE + 0x4C)
+#define MXC_CCM_LTR3            (MXC_CCM_BASE + 0x50)
+#define MXC_CCM_LTBR0           (MXC_CCM_BASE + 0x54)
+#define MXC_CCM_LTBR1           (MXC_CCM_BASE + 0x58)
+#define MXC_CCM_PMCR0           (MXC_CCM_BASE + 0x5C)
+#define MXC_CCM_PMCR1           (MXC_CCM_BASE + 0x60)
+#define MXC_CCM_PDR2            (MXC_CCM_BASE + 0x64)
+
+/* Register bit definitions */
+#define MXC_CCM_CCMR_WBEN                       (1 << 27)
+#define MXC_CCM_CCMR_CSCS                       (1 << 25)
+#define MXC_CCM_CCMR_PERCS                      (1 << 24)
+#define MXC_CCM_CCMR_SSI1S_OFFSET               18
+#define MXC_CCM_CCMR_SSI1S_MASK                 (0x3 << 18)
+#define MXC_CCM_CCMR_SSI2S_OFFSET               21
+#define MXC_CCM_CCMR_SSI2S_MASK                 (0x3 << 21)
+#define MXC_CCM_CCMR_LPM_OFFSET                 14
+#define MXC_CCM_CCMR_LPM_MASK                   (0x3 << 14)
+#define MXC_CCM_CCMR_FIRS_OFFSET                11
+#define MXC_CCM_CCMR_FIRS_MASK                  (0x3 << 11)
+#define MXC_CCM_CCMR_UPE                        (1 << 9)
+#define MXC_CCM_CCMR_SPE                        (1 << 8)
+#define MXC_CCM_CCMR_MDS                        (1 << 7)
+#define MXC_CCM_CCMR_SBYCS                      (1 << 4)
+#define MXC_CCM_CCMR_MPE                        (1 << 3)
+#define MXC_CCM_CCMR_PRCS_OFFSET                1
+#define MXC_CCM_CCMR_PRCS_MASK                  (0x3 << 1)
+
+#define MXC_CCM_PDR0_CSI_PODF_OFFSET            26
+#define MXC_CCM_PDR0_CSI_PODF_MASK              (0x3F << 26)
+#define MXC_CCM_PDR0_CSI_PRDF_OFFSET            23
+#define MXC_CCM_PDR0_CSI_PRDF_MASK              (0x7 << 23)
+#define MXC_CCM_PDR0_PER_PODF_OFFSET            16
+#define MXC_CCM_PDR0_PER_PODF_MASK              (0x1F << 16)
+#define MXC_CCM_PDR0_HSP_PODF_OFFSET            11
+#define MXC_CCM_PDR0_HSP_PODF_MASK              (0x7 << 11)
+#define MXC_CCM_PDR0_NFC_PODF_OFFSET            8
+#define MXC_CCM_PDR0_NFC_PODF_MASK              (0x7 << 8)
+#define MXC_CCM_PDR0_IPG_PODF_OFFSET            6
+#define MXC_CCM_PDR0_IPG_PODF_MASK              (0x3 << 6)
+#define MXC_CCM_PDR0_MAX_PODF_OFFSET            3
+#define MXC_CCM_PDR0_MAX_PODF_MASK              (0x7 << 3)
+#define MXC_CCM_PDR0_MCU_PODF_OFFSET            0
+#define MXC_CCM_PDR0_MCU_PODF_MASK              0x7
+
+#define MXC_CCM_PDR0_HSP_DIV_1                  (0x0 << 11)
+#define MXC_CCM_PDR0_HSP_DIV_2                  (0x1 << 11)
+#define MXC_CCM_PDR0_HSP_DIV_3                  (0x2 << 11)
+#define MXC_CCM_PDR0_HSP_DIV_4                  (0x3 << 11)
+#define MXC_CCM_PDR0_HSP_DIV_5                  (0x4 << 11)
+#define MXC_CCM_PDR0_HSP_DIV_6                  (0x5 << 11)
+#define MXC_CCM_PDR0_HSP_DIV_7                  (0x6 << 11)
+#define MXC_CCM_PDR0_HSP_DIV_8                  (0x7 << 11)
+
+#define MXC_CCM_PDR0_IPG_DIV_1                  (0x0 << 6)
+#define MXC_CCM_PDR0_IPG_DIV_2                  (0x1 << 6)
+#define MXC_CCM_PDR0_IPG_DIV_3                  (0x2 << 6)
+#define MXC_CCM_PDR0_IPG_DIV_4                  (0x3 << 6)
+
+#define MXC_CCM_PDR0_MAX_DIV_1                  (0x0 << 3)
+#define MXC_CCM_PDR0_MAX_DIV_2                  (0x1 << 3)
+#define MXC_CCM_PDR0_MAX_DIV_3                  (0x2 << 3)
+#define MXC_CCM_PDR0_MAX_DIV_4                  (0x3 << 3)
+#define MXC_CCM_PDR0_MAX_DIV_5                  (0x4 << 3)
+#define MXC_CCM_PDR0_MAX_DIV_6                  (0x5 << 3)
+#define MXC_CCM_PDR0_MAX_DIV_7                  (0x6 << 3)
+#define MXC_CCM_PDR0_MAX_DIV_8                  (0x7 << 3)
+
+#define MXC_CCM_PDR0_NFC_DIV_1                  (0x0 << 8)
+#define MXC_CCM_PDR0_NFC_DIV_2                  (0x1 << 8)
+#define MXC_CCM_PDR0_NFC_DIV_3                  (0x2 << 8)
+#define MXC_CCM_PDR0_NFC_DIV_4                  (0x3 << 8)
+#define MXC_CCM_PDR0_NFC_DIV_5                  (0x4 << 8)
+#define MXC_CCM_PDR0_NFC_DIV_6                  (0x5 << 8)
+#define MXC_CCM_PDR0_NFC_DIV_7                  (0x6 << 8)
+#define MXC_CCM_PDR0_NFC_DIV_8                  (0x7 << 8)
+
+#define MXC_CCM_PDR0_MCU_DIV_1                  0x0
+#define MXC_CCM_PDR0_MCU_DIV_2                  0x1
+#define MXC_CCM_PDR0_MCU_DIV_3                  0x2
+#define MXC_CCM_PDR0_MCU_DIV_4                  0x3
+#define MXC_CCM_PDR0_MCU_DIV_5                  0x4
+#define MXC_CCM_PDR0_MCU_DIV_6                  0x5
+#define MXC_CCM_PDR0_MCU_DIV_7                  0x6
+#define MXC_CCM_PDR0_MCU_DIV_8                  0x7
+
+#define MXC_CCM_PDR1_USB_PRDF_OFFSET            30
+#define MXC_CCM_PDR1_USB_PRDF_MASK              (0x3 << 30)
+#define MXC_CCM_PDR1_USB_PODF_OFFSET            27
+#define MXC_CCM_PDR1_USB_PODF_MASK              (0x7 << 27)
+#define MXC_CCM_PDR1_FIRI_PRE_PODF_OFFSET       24
+#define MXC_CCM_PDR1_FIRI_PRE_PODF_MASK         (0x7 << 24)
+#define MXC_CCM_PDR1_FIRI_PODF_OFFSET           18
+#define MXC_CCM_PDR1_FIRI_PODF_MASK             (0x3F << 18)
+#define MXC_CCM_PDR1_SSI2_PRE_PODF_OFFSET       15
+#define MXC_CCM_PDR1_SSI2_PRE_PODF_MASK         (0x7 << 15)
+#define MXC_CCM_PDR1_SSI2_PODF_OFFSET           9
+#define MXC_CCM_PDR1_SSI2_PODF_MASK             (0x3F << 9)
+#define MXC_CCM_PDR1_SSI1_PRE_PODF_OFFSET       6
+#define MXC_CCM_PDR1_SSI1_PRE_PODF_MASK         (0x7 << 6)
+#define MXC_CCM_PDR1_SSI1_PODF_OFFSET           0
+#define MXC_CCM_PDR1_SSI1_PODF_MASK             0x3F
+
+/* Bit definitions for RCSR */
+#define MXC_CCM_RCSR_NF16B                      0x80000000
+
+/* Bit definitions for both MCU, USB and SR PLL control registers */
+#define MXC_CCM_PCTL_BRM                        0x80000000
+#define MXC_CCM_PCTL_PD_OFFSET                  26
+#define MXC_CCM_PCTL_PD_MASK                    (0xF << 26)
+#define MXC_CCM_PCTL_MFD_OFFSET                 16
+#define MXC_CCM_PCTL_MFD_MASK                   (0x3FF << 16)
+#define MXC_CCM_PCTL_MFI_OFFSET                 10
+#define MXC_CCM_PCTL_MFI_MASK                   (0xF << 10)
+#define MXC_CCM_PCTL_MFN_OFFSET                 0
+#define MXC_CCM_PCTL_MFN_MASK                   0x3FF
+
+#define MXC_CCM_CGR0_SD_MMC1_OFFSET             0
+#define MXC_CCM_CGR0_SD_MMC1_MASK               (0x3 << 0)
+#define MXC_CCM_CGR0_SD_MMC2_OFFSET             2
+#define MXC_CCM_CGR0_SD_MMC2_MASK               (0x3 << 2)
+#define MXC_CCM_CGR0_GPT_OFFSET                 4
+#define MXC_CCM_CGR0_GPT_MASK                   (0x3 << 4)
+#define MXC_CCM_CGR0_EPIT1_OFFSET               6
+#define MXC_CCM_CGR0_EPIT1_MASK                 (0x3 << 6)
+#define MXC_CCM_CGR0_EPIT2_OFFSET               8
+#define MXC_CCM_CGR0_EPIT2_MASK                 (0x3 << 8)
+#define MXC_CCM_CGR0_IIM_OFFSET                 10
+#define MXC_CCM_CGR0_IIM_MASK                   (0x3 << 10)
+#define MXC_CCM_CGR0_ATA_OFFSET                 12
+#define MXC_CCM_CGR0_ATA_MASK                   (0x3 << 12)
+#define MXC_CCM_CGR0_SDMA_OFFSET                14
+#define MXC_CCM_CGR0_SDMA_MASK                  (0x3 << 14)
+#define MXC_CCM_CGR0_CSPI3_OFFSET               16
+#define MXC_CCM_CGR0_CSPI3_MASK                 (0x3 << 16)
+#define MXC_CCM_CGR0_RNG_OFFSET                 18
+#define MXC_CCM_CGR0_RNG_MASK                   (0x3 << 18)
+#define MXC_CCM_CGR0_UART1_OFFSET               20
+#define MXC_CCM_CGR0_UART1_MASK                 (0x3 << 20)
+#define MXC_CCM_CGR0_UART2_OFFSET               22
+#define MXC_CCM_CGR0_UART2_MASK                 (0x3 << 22)
+#define MXC_CCM_CGR0_SSI1_OFFSET                24
+#define MXC_CCM_CGR0_SSI1_MASK                  (0x3 << 24)
+#define MXC_CCM_CGR0_I2C1_OFFSET                26
+#define MXC_CCM_CGR0_I2C1_MASK                  (0x3 << 26)
+#define MXC_CCM_CGR0_I2C2_OFFSET                28
+#define MXC_CCM_CGR0_I2C2_MASK                  (0x3 << 28)
+#define MXC_CCM_CGR0_I2C3_OFFSET                30
+#define MXC_CCM_CGR0_I2C3_MASK                  (0x3 << 30)
+
+#define MXC_CCM_CGR1_HANTRO_OFFSET              0
+#define MXC_CCM_CGR1_HANTRO_MASK                (0x3 << 0)
+#define MXC_CCM_CGR1_MEMSTICK1_OFFSET           2
+#define MXC_CCM_CGR1_MEMSTICK1_MASK             (0x3 << 2)
+#define MXC_CCM_CGR1_MEMSTICK2_OFFSET           4
+#define MXC_CCM_CGR1_MEMSTICK2_MASK             (0x3 << 4)
+#define MXC_CCM_CGR1_CSI_OFFSET                 6
+#define MXC_CCM_CGR1_CSI_MASK                   (0x3 << 6)
+#define MXC_CCM_CGR1_RTC_OFFSET                 8
+#define MXC_CCM_CGR1_RTC_MASK                   (0x3 << 8)
+#define MXC_CCM_CGR1_WDOG_OFFSET                10
+#define MXC_CCM_CGR1_WDOG_MASK                  (0x3 << 10)
+#define MXC_CCM_CGR1_PWM_OFFSET                 12
+#define MXC_CCM_CGR1_PWM_MASK                   (0x3 << 12)
+#define MXC_CCM_CGR1_SIM_OFFSET                 14
+#define MXC_CCM_CGR1_SIM_MASK                   (0x3 << 14)
+#define MXC_CCM_CGR1_ECT_OFFSET                 16
+#define MXC_CCM_CGR1_ECT_MASK                   (0x3 << 16)
+#define MXC_CCM_CGR1_USBOTG_OFFSET              18
+#define MXC_CCM_CGR1_USBOTG_MASK                (0x3 << 18)
+#define MXC_CCM_CGR1_KPP_OFFSET                 20
+#define MXC_CCM_CGR1_KPP_MASK                   (0x3 << 20)
+#define MXC_CCM_CGR1_IPU_OFFSET                 22
+#define MXC_CCM_CGR1_IPU_MASK                   (0x3 << 22)
+#define MXC_CCM_CGR1_UART3_OFFSET               24
+#define MXC_CCM_CGR1_UART3_MASK                 (0x3 << 24)
+#define MXC_CCM_CGR1_UART4_OFFSET               26
+#define MXC_CCM_CGR1_UART4_MASK                 (0x3 << 26)
+#define MXC_CCM_CGR1_UART5_OFFSET               28
+#define MXC_CCM_CGR1_UART5_MASK                 (0x3 << 28)
+#define MXC_CCM_CGR1_OWIRE_OFFSET               30
+#define MXC_CCM_CGR1_OWIRE_MASK                 (0x3 << 30)
+
+#define MXC_CCM_CGR2_SSI2_OFFSET                0
+#define MXC_CCM_CGR2_SSI2_MASK                  (0x3 << 0)
+#define MXC_CCM_CGR2_CSPI1_OFFSET               2
+#define MXC_CCM_CGR2_CSPI1_MASK                 (0x3 << 2)
+#define MXC_CCM_CGR2_CSPI2_OFFSET               4
+#define MXC_CCM_CGR2_CSPI2_MASK                 (0x3 << 4)
+#define MXC_CCM_CGR2_GACC_OFFSET                6
+#define MXC_CCM_CGR2_GACC_MASK                  (0x3 << 6)
+#define MXC_CCM_CGR2_EMI_OFFSET                 8
+#define MXC_CCM_CGR2_EMI_MASK                   (0x3 << 8)
+#define MXC_CCM_CGR2_RTIC_OFFSET                10
+#define MXC_CCM_CGR2_RTIC_MASK                  (0x3 << 10)
+#define MXC_CCM_CGR2_FIRI_OFFSET                12
+#define MXC_CCM_CGR2_FIRI_MASK                  (0x3 << 12)
+#define MXC_CCM_CGR2_IPMUX1_OFFSET              14
+#define MXC_CCM_CGR2_IPMUX1_MASK                (0x3 << 14)
+#define MXC_CCM_CGR2_IPMUX2_OFFSET              16
+#define MXC_CCM_CGR2_IPMUX2_MASK                (0x3 << 16)
+
+/* These new CGR2 bits are added in MX32 */
+#define MXC_CCM_CGR2_APMSYSCLKSEL_OFFSET        18
+#define MXC_CCM_CGR2_APMSYSCLKSEL_MASK          (0x3 << 18)
+#define MXC_CCM_CGR2_APMSSICLKSEL_OFFSET        20
+#define MXC_CCM_CGR2_APMSSICLKSEL_MASK          (0x3 << 20)
+#define MXC_CCM_CGR2_APMPERCLKSEL_OFFSET        22
+#define MXC_CCM_CGR2_APMPERCLKSEL_MASK          (0x3 << 22)
+#define MXC_CCM_CGR2_MXCCLKENSEL_OFFSET         24
+#define MXC_CCM_CGR2_MXCCLKENSEL_MASK           (0x1 << 24)
+#define MXC_CCM_CGR2_CHIKCAMPEN_OFFSET          25
+#define MXC_CCM_CGR2_CHIKCAMPEN_MASK            (0x1 << 25)
+#define MXC_CCM_CGR2_OVRVPUBUSY_OFFSET          26
+#define MXC_CCM_CGR2_OVRVPUBUSY_MASK            (0x1 << 26)
+#define MXC_CCM_CGR2_APMENA_OFFSET              30
+#define MXC_CCM_CGR2_AOMENA_MASK                (0x1 << 30)
+
+/*
+ * LTR0 register offsets
+ */
+#define MXC_CCM_LTR0_DIV3CK_OFFSET              1
+#define MXC_CCM_LTR0_DIV3CK_MASK                (0x3 << 1)
+#define MXC_CCM_LTR0_DNTHR_OFFSET               16
+#define MXC_CCM_LTR0_DNTHR_MASK                 (0x3F << 16)
+#define MXC_CCM_LTR0_UPTHR_OFFSET               22
+#define MXC_CCM_LTR0_UPTHR_MASK                 (0x3F << 22)
+
+/*
+ * LTR1 register offsets
+ */
+#define MXC_CCM_LTR1_PNCTHR_OFFSET              0
+#define MXC_CCM_LTR1_PNCTHR_MASK                0x3F
+#define MXC_CCM_LTR1_UPCNT_OFFSET               6
+#define MXC_CCM_LTR1_UPCNT_MASK                 (0xFF << 6)
+#define MXC_CCM_LTR1_DNCNT_OFFSET               14
+#define MXC_CCM_LTR1_DNCNT_MASK                 (0xFF << 14)
+#define MXC_CCM_LTR1_LTBRSR_MASK                0x400000
+#define MXC_CCM_LTR1_LTBRSR_OFFSET              22
+#define MXC_CCM_LTR1_LTBRSR                     0x400000
+#define MXC_CCM_LTR1_LTBRSH                     0x800000
+
+/*
+ * LTR2 bit definitions. x ranges from 0 for WSW9 to 6 for WSW15
+ */
+#define MXC_CCM_LTR2_WSW_OFFSET(x)              (11 + (x) * 3)
+#define MXC_CCM_LTR2_WSW_MASK(x)                (0x7 << \
+                                        MXC_CCM_LTR2_WSW_OFFSET((x)))
+#define MXC_CCM_LTR2_EMAC_OFFSET                0
+#define MXC_CCM_LTR2_EMAC_MASK                  0x1FF
+
+/*
+ * LTR3 bit definitions. x ranges from 0 for WSW0 to 8 for WSW8
+ */
+#define MXC_CCM_LTR3_WSW_OFFSET(x)              (5 + (x) * 3)
+#define MXC_CCM_LTR3_WSW_MASK(x)                (0x7 << \
+                                        MXC_CCM_LTR3_WSW_OFFSET((x)))
+
+#define MXC_CCM_PMCR0_DFSUP1                    0x80000000
+#define MXC_CCM_PMCR0_DFSUP1_SPLL               (0 << 31)
+#define MXC_CCM_PMCR0_DFSUP1_MPLL               (1 << 31)
+#define MXC_CCM_PMCR0_DFSUP0                    0x40000000
+#define MXC_CCM_PMCR0_DFSUP0_PLL                (0 << 30)
+#define MXC_CCM_PMCR0_DFSUP0_PDR                (1 << 30)
+#define MXC_CCM_PMCR0_DFSUP_MASK                (0x3 << 30)
+
+#define DVSUP_TURBO                             0
+#define DVSUP_HIGH                              1
+#define DVSUP_MEDIUM                            2
+#define DVSUP_LOW                               3
+#define MXC_CCM_PMCR0_DVSUP_TURBO               (DVSUP_TURBO << 28)
+#define MXC_CCM_PMCR0_DVSUP_HIGH                (DVSUP_HIGH << 28)
+#define MXC_CCM_PMCR0_DVSUP_MEDIUM              (DVSUP_MEDIUM << 28)
+#define MXC_CCM_PMCR0_DVSUP_LOW                 (DVSUP_LOW << 28)
+#define MXC_CCM_PMCR0_DVSUP_OFFSET              28
+#define MXC_CCM_PMCR0_DVSUP_MASK                (0x3 << 28)
+#define MXC_CCM_PMCR0_UDSC                      0x08000000
+#define MXC_CCM_PMCR0_UDSC_MASK                 (1 << 27)
+#define MXC_CCM_PMCR0_UDSC_UP                   (1 << 27)
+#define MXC_CCM_PMCR0_UDSC_DOWN                 (0 << 27)
+
+#define MXC_CCM_PMCR0_VSCNT_1                   (0x0 << 24)
+#define MXC_CCM_PMCR0_VSCNT_2                   (0x1 << 24)
+#define MXC_CCM_PMCR0_VSCNT_3                   (0x2 << 24)
+#define MXC_CCM_PMCR0_VSCNT_4                   (0x3 << 24)
+#define MXC_CCM_PMCR0_VSCNT_5                   (0x4 << 24)
+#define MXC_CCM_PMCR0_VSCNT_6                   (0x5 << 24)
+#define MXC_CCM_PMCR0_VSCNT_7                   (0x6 << 24)
+#define MXC_CCM_PMCR0_VSCNT_8                   (0x7 << 24)
+#define MXC_CCM_PMCR0_VSCNT_OFFSET              24
+#define MXC_CCM_PMCR0_VSCNT_MASK                (0x7 << 24)
+#define MXC_CCM_PMCR0_DVFEV                     0x00800000
+#define MXC_CCM_PMCR0_DVFIS                     0x00400000
+#define MXC_CCM_PMCR0_LBMI                      0x00200000
+#define MXC_CCM_PMCR0_LBFL                      0x00100000
+#define MXC_CCM_PMCR0_LBCF_4                    (0x0 << 18)
+#define MXC_CCM_PMCR0_LBCF_8                    (0x1 << 18)
+#define MXC_CCM_PMCR0_LBCF_12                   (0x2 << 18)
+#define MXC_CCM_PMCR0_LBCF_16                   (0x3 << 18)
+#define MXC_CCM_PMCR0_LBCF_OFFSET               18
+#define MXC_CCM_PMCR0_LBCF_MASK                 (0x3 << 18)
+#define MXC_CCM_PMCR0_PTVIS                     0x00020000
+#define MXC_CCM_PMCR0_UPDTEN                    0x00010000
+#define MXC_CCM_PMCR0_UPDTEN_MASK               (0x1 << 16)
+#define MXC_CCM_PMCR0_FSVAIM                    0x00008000
+#define MXC_CCM_PMCR0_FSVAI_OFFSET              13
+#define MXC_CCM_PMCR0_FSVAI_MASK                (0x3 << 13)
+#define MXC_CCM_PMCR0_DPVCR                     0x00001000
+#define MXC_CCM_PMCR0_DPVV                      0x00000800
+#define MXC_CCM_PMCR0_WFIM                      0x00000400
+#define MXC_CCM_PMCR0_DRCE3                     0x00000200
+#define MXC_CCM_PMCR0_DRCE2                     0x00000100
+#define MXC_CCM_PMCR0_DRCE1                     0x00000080
+#define MXC_CCM_PMCR0_DRCE0                     0x00000040
+#define MXC_CCM_PMCR0_DCR                       0x00000020
+#define MXC_CCM_PMCR0_DVFEN                     0x00000010
+#define MXC_CCM_PMCR0_PTVAIM                    0x00000008
+#define MXC_CCM_PMCR0_PTVAI_OFFSET              1
+#define MXC_CCM_PMCR0_PTVAI_MASK                (0x3 << 1)
+#define MXC_CCM_PMCR0_DPTEN                     0x00000001
+
+#define MXC_CCM_PMCR1_DVGP_OFFSET               0
+#define MXC_CCM_PMCR1_DVGP_MASK                 (0xF)
+
+#define MXC_CCM_PMCR1_PLLRDIS                      (0x1 << 7)
+#define MXC_CCM_PMCR1_EMIRQ_EN                      (0x1 << 8)
+
+#define MXC_CCM_DCVR_ULV_MASK                   (0x3FF << 22)
+#define MXC_CCM_DCVR_ULV_OFFSET                 22
+#define MXC_CCM_DCVR_LLV_MASK                   (0x3FF << 12)
+#define MXC_CCM_DCVR_LLV_OFFSET                 12
+#define MXC_CCM_DCVR_ELV_MASK                   (0x3FF << 2)
+#define MXC_CCM_DCVR_ELV_OFFSET                 2
+
+#define MXC_CCM_PDR2_MST2_PDF_MASK              (0x3F << 7)
+#define MXC_CCM_PDR2_MST2_PDF_OFFSET            7
+#define MXC_CCM_PDR2_MST1_PDF_MASK              0x3F
+#define MXC_CCM_PDR2_MST1_PDF_OFFSET            0
+
+#define MXC_CCM_COSR_CLKOSEL_MASK               0x0F
+#define MXC_CCM_COSR_CLKOSEL_OFFSET             0
+#define MXC_CCM_COSR_CLKOUTDIV_MASK             (0x07 << 6)
+#define MXC_CCM_COSR_CLKOUTDIV_OFFSET           6
+#define MXC_CCM_COSR_CLKOEN                     (1 << 9)
+
+/*
+ * PMCR0 register offsets
+ */
+#define MXC_CCM_PMCR0_LBFL_OFFSET   20
+#define MXC_CCM_PMCR0_DFSUP0_OFFSET 30
+#define MXC_CCM_PMCR0_DFSUP1_OFFSET 31
+
+#endif                          /* __ARCH_ARM_MACH_MX3_CRM_REGS_H__ */
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c
new file mode 100644
index 000000000000..5c0320fce5b6
--- /dev/null
+++ b/arch/arm/mach-mx3/devices.c
@@ -0,0 +1,180 @@
+/*
+ * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ * Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/serial.h>
+#include <linux/gpio.h>
+#include <asm/hardware.h>
+#include <asm/arch/imx-uart.h>
+
+static struct resource uart0[] = {
+        {
+                .start = UART1_BASE_ADDR,
+                .end = UART1_BASE_ADDR + 0x0B5,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_UART1,
+                .end = MXC_INT_UART1,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mxc_uart_device0 = {
+        .name = "imx-uart",
+        .id = 0,
+        .resource = uart0,
+        .num_resources = ARRAY_SIZE(uart0),
+};
+
+static struct resource uart1[] = {
+        {
+                .start = UART2_BASE_ADDR,
+                .end = UART2_BASE_ADDR + 0x0B5,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_UART2,
+                .end = MXC_INT_UART2,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mxc_uart_device1 = {
+        .name = "imx-uart",
+        .id = 1,
+        .resource = uart1,
+        .num_resources = ARRAY_SIZE(uart1),
+};
+
+static struct resource uart2[] = {
+        {
+                .start = UART3_BASE_ADDR,
+                .end = UART3_BASE_ADDR + 0x0B5,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_UART3,
+                .end = MXC_INT_UART3,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mxc_uart_device2 = {
+        .name = "imx-uart",
+        .id = 2,
+        .resource = uart2,
+        .num_resources = ARRAY_SIZE(uart2),
+};
+
+static struct resource uart3[] = {
+        {
+                .start = UART4_BASE_ADDR,
+                .end = UART4_BASE_ADDR + 0x0B5,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_UART4,
+                .end = MXC_INT_UART4,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mxc_uart_device3 = {
+        .name = "imx-uart",
+        .id = 3,
+        .resource = uart3,
+        .num_resources = ARRAY_SIZE(uart3),
+};
+
+static struct resource uart4[] = {
+        {
+                .start = UART5_BASE_ADDR,
+                .end = UART5_BASE_ADDR + 0x0B5,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_UART5,
+                .end = MXC_INT_UART5,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mxc_uart_device4 = {
+        .name = "imx-uart",
+        .id = 4,
+        .resource = uart4,
+        .num_resources = ARRAY_SIZE(uart4),
+};
+
+/*
+ * Register only those UARTs that physically exist
+ */
+int __init imx_init_uart(int uart_no, struct imxuart_platform_data *pdata)
+{
+        switch (uart_no) {
+        case 0:
+                mxc_uart_device0.dev.platform_data = pdata;
+                platform_device_register(&mxc_uart_device0);
+                break;
+        case 1:
+                mxc_uart_device1.dev.platform_data = pdata;
+                platform_device_register(&mxc_uart_device1);
+                break;
+        case 2:
+                mxc_uart_device2.dev.platform_data = pdata;
+                platform_device_register(&mxc_uart_device2);
+                break;
+        case 3:
+                mxc_uart_device3.dev.platform_data = pdata;
+                platform_device_register(&mxc_uart_device3);
+                break;
+        case 4:
+                mxc_uart_device4.dev.platform_data = pdata;
+                platform_device_register(&mxc_uart_device4);
+                break;
+        default:
+                return -ENODEV;
+        }
+
+        return 0;
+}
+
+/* GPIO port description */
+static struct mxc_gpio_port imx_gpio_ports[] = {
+        [0] = {
+                .chip.label = "gpio-0",
+                .base = IO_ADDRESS(GPIO1_BASE_ADDR),
+                .irq = MXC_INT_GPIO1,
+                .virtual_irq_start = MXC_GPIO_INT_BASE
+        },
+        [1] = {
+                .chip.label = "gpio-1",
+                .base = IO_ADDRESS(GPIO2_BASE_ADDR),
+                .irq = MXC_INT_GPIO2,
+                .virtual_irq_start = MXC_GPIO_INT_BASE + GPIO_NUM_PIN
+        },
+        [2] = {
+                .chip.label = "gpio-2",
+                .base = IO_ADDRESS(GPIO3_BASE_ADDR),
+                .irq = MXC_INT_GPIO3,
+                .virtual_irq_start = MXC_GPIO_INT_BASE + GPIO_NUM_PIN * 2
+        }
+};
+
+int __init mxc_register_gpios(void)
+{
+        return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
+}
diff --git a/arch/arm/mach-mx3/iomux.c b/arch/arm/mach-mx3/iomux.c
new file mode 100644
index 000000000000..adc51feefc1d
--- /dev/null
+++ b/arch/arm/mach-mx3/iomux.c
@@ -0,0 +1,111 @@
+/*
+ * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <asm/hardware.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/iomux-mx3.h>
+
+/*
+ * IOMUX register (base) addresses
+ */
+#define IOMUX_BASE      IO_ADDRESS(IOMUXC_BASE_ADDR)
+#define IOMUXINT_OBS1   (IOMUX_BASE + 0x000)
+#define IOMUXINT_OBS2   (IOMUX_BASE + 0x004)
+#define IOMUXGPR        (IOMUX_BASE + 0x008)
+#define IOMUXSW_MUX_CTL (IOMUX_BASE + 0x00C)
+#define IOMUXSW_PAD_CTL (IOMUX_BASE + 0x154)
+
+static DEFINE_SPINLOCK(gpio_mux_lock);
+
+#define IOMUX_REG_MASK (IOMUX_PADNUM_MASK & ~0x3)
+/*
+ * set the mode for a IOMUX pin.
+ */
+int mxc_iomux_mode(unsigned int pin_mode)
+{
+        u32 reg, field, l, mode, ret = 0;
+
+        reg = IOMUXSW_MUX_CTL + (pin_mode & IOMUX_REG_MASK);
+        field = pin_mode & 0x3;
+        mode = (pin_mode & IOMUX_MODE_MASK) >> IOMUX_MODE_SHIFT;
+
+        pr_debug("%s: reg offset = 0x%x field = %d mode = 0x%02x\n",
+                        __func__, (pin_mode & IOMUX_REG_MASK), field, mode);
+
+        spin_lock(&gpio_mux_lock);
+
+        l = __raw_readl(reg);
+        l &= ~(0xff << (field * 8));
+        l |= mode << (field * 8);
+        __raw_writel(l, reg);
+
+        spin_unlock(&gpio_mux_lock);
+
+        return ret;
+}
+EXPORT_SYMBOL(mxc_iomux_mode);
+
+/*
+ * This function configures the pad value for a IOMUX pin.
+ */
+void mxc_iomux_set_pad(enum iomux_pins pin, u32 config)
+{
+        u32 reg, field, l;
+
+        reg = IOMUXSW_PAD_CTL + (pin + 2) / 3;
+        field = (pin + 2) % 3;
+
+        pr_debug("%s: reg offset = 0x%x field = %d\n",
+                        __func__, (pin + 2) / 3, field);
+
+        spin_lock(&gpio_mux_lock);
+
+        l = __raw_readl(reg);
+        l &= ~(0x1ff << (field * 9));
+        l |= config << (field * 9);
+        __raw_writel(l, reg);
+
+        spin_unlock(&gpio_mux_lock);
+}
+EXPORT_SYMBOL(mxc_iomux_set_pad);
+
+/*
+ * This function enables/disables the general purpose function for a particular
+ * signal.
+ */
+void mxc_iomux_set_gpr(enum iomux_gp_func gp, bool en)
+{
+        u32 l;
+
+        spin_lock(&gpio_mux_lock);
+        l = __raw_readl(IOMUXGPR);
+        if (en)
+                l |= gp;
+        else
+                l &= ~gp;
+
+        __raw_writel(l, IOMUXGPR);
+        spin_unlock(&gpio_mux_lock);
+}
+EXPORT_SYMBOL(mxc_iomux_set_gpr);
+
diff --git a/arch/arm/mach-mx3/mx31ads.c b/arch/arm/mach-mx3/mx31ads.c
index 7e89bdc23a9f..eba3e0cd4283 100644
--- a/arch/arm/mach-mx3/mx31ads.c
+++ b/arch/arm/mach-mx3/mx31ads.c
@@ -26,9 +26,11 @@
 #include <asm/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
+#include <asm/mach/time.h>
 #include <asm/memory.h>
 #include <asm/mach/map.h>
 #include <asm/arch/common.h>
+#include <asm/arch/board-mx31ads.h>
 
 /*!
  * @file mx31ads.c
@@ -126,6 +128,16 @@ static void __init mxc_board_init(void)
         mxc_init_extuart();
 }
 
+static void __init mx31ads_timer_init(void)
+{
+        mxc_clocks_init(26000000);
+        mxc_timer_init("ipg_clk.0");
+}
+
+struct sys_timer mx31ads_timer = {
+        .init   = mx31ads_timer_init,
+};
+
 /*
  * The following uses standard kernel macros defined in arch.h in order to
  * initialize __mach_desc_MX31ADS data structure.
@@ -138,5 +150,5 @@ MACHINE_START(MX31ADS, "Freescale MX31ADS")
         .map_io         = mx31ads_map_io,
         .init_irq       = mxc_init_irq,
         .init_machine   = mxc_board_init,
-        .timer          = &mxc_timer,
+        .timer          = &mx31ads_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mx3/mx31lite.c b/arch/arm/mach-mx3/mx31lite.c
new file mode 100644
index 000000000000..1372c1a1fc3f
--- /dev/null
+++ b/arch/arm/mach-mx3/mx31lite.c
@@ -0,0 +1,107 @@
+/*
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ *  Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/memory.h>
+
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+#include <asm/arch/common.h>
+#include <asm/page.h>
+#include <asm/setup.h>
+#include <asm/arch/board-mx31lite.h>
+
+/*
+ * This file contains the board-specific initialization routines.
+ */
+
+/*
+ * This structure defines the MX31 memory map.
+ */
+static struct map_desc mx31lite_io_desc[] __initdata = {
+        {
+                .virtual = AIPS1_BASE_ADDR_VIRT,
+                .pfn = __phys_to_pfn(AIPS1_BASE_ADDR),
+                .length = AIPS1_SIZE,
+                .type = MT_NONSHARED_DEVICE
+        }, {
+                .virtual = SPBA0_BASE_ADDR_VIRT,
+                .pfn = __phys_to_pfn(SPBA0_BASE_ADDR),
+                .length = SPBA0_SIZE,
+                .type = MT_NONSHARED_DEVICE
+        }, {
+                .virtual = AIPS2_BASE_ADDR_VIRT,
+                .pfn = __phys_to_pfn(AIPS2_BASE_ADDR),
+                .length = AIPS2_SIZE,
+                .type = MT_NONSHARED_DEVICE
+        }, {
+                .virtual = CS4_BASE_ADDR_VIRT,
+                .pfn = __phys_to_pfn(CS4_BASE_ADDR),
+                .length = CS4_SIZE,
+                .type = MT_DEVICE
+        }
+};
+
+/*
+ * Set up static virtual mappings.
+ */
+void __init mx31lite_map_io(void)
+{
+        mxc_map_io();
+        iotable_init(mx31lite_io_desc, ARRAY_SIZE(mx31lite_io_desc));
+}
+
+/*
+ * Board specific initialization.
+ */
+static void __init mxc_board_init(void)
+{
+}
+
+static void __init mx31lite_timer_init(void)
+{
+        mxc_clocks_init(26000000);
+        mxc_timer_init("ipg_clk.0");
+}
+
+struct sys_timer mx31lite_timer = {
+        .init   = mx31lite_timer_init,
+};
+
+/*
+ * The following uses standard kernel macros defined in arch.h in order to
+ * initialize __mach_desc_MX31LITE data structure.
+ */
+
+MACHINE_START(MX31LITE, "LogicPD MX31 LITEKIT")
+        /* Maintainer: Freescale Semiconductor, Inc. */
+        .phys_io        = AIPS1_BASE_ADDR,
+        .io_pg_offst    = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+        .boot_params    = PHYS_OFFSET + 0x100,
+        .map_io         = mx31lite_map_io,
+        .init_irq       = mxc_init_irq,
+        .init_machine   = mxc_board_init,
+        .timer          = &mx31lite_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mx3/pcm037.c b/arch/arm/mach-mx3/pcm037.c
new file mode 100644
index 000000000000..a34ae6de266f
--- /dev/null
+++ b/arch/arm/mach-mx3/pcm037.c
@@ -0,0 +1,130 @@
+/*
+ *  Copyright (C) 2008 Sascha Hauer, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <linux/memory.h>
+
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+#include <asm/arch/common.h>
+#include <asm/arch/imx-uart.h>
+#include <asm/arch/iomux-mx3.h>
+#include <asm/arch/board-pcm037.h>
+
+static struct physmap_flash_data pcm037_flash_data = {
+        .width  = 2,
+};
+
+static struct resource pcm037_flash_resource = {
+        .start  = 0xa0000000,
+        .end    = 0xa1ffffff,
+        .flags  = IORESOURCE_MEM,
+};
+
+static struct platform_device pcm037_flash = {
+        .name   = "physmap-flash",
+        .id     = 0,
+        .dev    = {
+                .platform_data  = &pcm037_flash_data,
+        },
+        .resource = &pcm037_flash_resource,
+        .num_resources = 1,
+};
+
+static struct imxuart_platform_data uart_pdata = {
+        .flags = 0,
+};
+
+static struct platform_device *devices[] __initdata = {
+        &pcm037_flash,
+};
+
+/*
+ * Board specific initialization.
+ */
+static void __init mxc_board_init(void)
+{
+        platform_add_devices(devices, ARRAY_SIZE(devices));
+
+        mxc_iomux_mode(MX31_PIN_CTS1__CTS1);
+        mxc_iomux_mode(MX31_PIN_RTS1__RTS1);
+        mxc_iomux_mode(MX31_PIN_TXD1__TXD1);
+        mxc_iomux_mode(MX31_PIN_RXD1__RXD1);
+
+        imx_init_uart(0, &uart_pdata);
+
+        mxc_iomux_mode(MX31_PIN_CSPI3_MOSI__RXD3);
+        mxc_iomux_mode(MX31_PIN_CSPI3_MISO__TXD3);
+
+        imx_init_uart(2, &uart_pdata);
+}
+
+/*
+ * This structure defines static mappings for the pcm037 board.
+ */
+static struct map_desc pcm037_io_desc[] __initdata = {
+        {
+                .virtual        = AIPS1_BASE_ADDR_VIRT,
+                .pfn            = __phys_to_pfn(AIPS1_BASE_ADDR),
+                .length         = AIPS1_SIZE,
+                .type           = MT_DEVICE
+        }, {
+                .virtual        = AIPS2_BASE_ADDR_VIRT,
+                .pfn            = __phys_to_pfn(AIPS2_BASE_ADDR),
+                .length         = AIPS2_SIZE,
+                .type           = MT_DEVICE
+        },
+};
+
+/*
+ * Set up static virtual mappings.
+ */
+void __init pcm037_map_io(void)
+{
+        mxc_map_io();
+        iotable_init(pcm037_io_desc, ARRAY_SIZE(pcm037_io_desc));
+}
+
+static void __init pcm037_timer_init(void)
+{
+        mxc_clocks_init(26000000);
+        mxc_timer_init("ipg_clk.0");
+}
+
+struct sys_timer pcm037_timer = {
+        .init   = pcm037_timer_init,
+};
+
+MACHINE_START(PCM037, "Phytec Phycore pcm037")
+        /* Maintainer: Pengutronix */
+        .phys_io        = AIPS1_BASE_ADDR,
+        .io_pg_offst    = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+        .boot_params    = PHYS_OFFSET + 0x100,
+        .map_io         = pcm037_map_io,
+        .init_irq       = mxc_init_irq,
+        .init_machine   = mxc_board_init,
+        .timer          = &pcm037_timer,
+MACHINE_END
+
diff --git a/arch/arm/mach-mx3/time.c b/arch/arm/mach-mx3/time.c
deleted file mode 100644
index fb565c98dbfb..000000000000
--- a/arch/arm/mach-mx3/time.c
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * System Timer Interrupt reconfigured to run in free-run mode.
- * Author: Vitaly Wool
- * Copyright 2004 MontaVista Software Inc.
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-/*!
- * @file time.c
- * @brief This file contains OS tick and wdog timer implementations.
- *
- * This file contains OS tick and wdog timer implementations.
- *
- * @ingroup Timers
- */
-
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <asm/hardware.h>
-#include <asm/mach/time.h>
-#include <asm/io.h>
-#include <asm/arch/common.h>
-
-/*!
- * This is the timer interrupt service routine to do required tasks.
- * It also services the WDOG timer at the frequency of twice per WDOG
- * timeout value. For example, if the WDOG's timeout value is 4 (2
- * seconds since the WDOG runs at 0.5Hz), it will be serviced once
- * every 2/2=1 second.
- *
- * @param  irq          GPT interrupt source number (not used)
- * @param  dev_id       this parameter is not used
- * @return always returns \b IRQ_HANDLED as defined in
- *         include/linux/interrupt.h.
- */
-static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
-{
-        unsigned int next_match;
-
-        if (__raw_readl(MXC_GPT_GPTSR) & GPTSR_OF1) {
-                do {
-                        timer_tick();
-                        next_match = __raw_readl(MXC_GPT_GPTOCR1) + LATCH;
-                        __raw_writel(GPTSR_OF1, MXC_GPT_GPTSR);
-                        __raw_writel(next_match, MXC_GPT_GPTOCR1);
-                } while ((signed long)(next_match -
-                                       __raw_readl(MXC_GPT_GPTCNT)) <= 0);
-        }
-
-        return IRQ_HANDLED;
-}
-
-/*!
- * This function is used to obtain the number of microseconds since the last
- * timer interrupt. Note that interrupts is disabled by do_gettimeofday().
- *
- * @return the number of microseconds since the last timer interrupt.
- */
-static unsigned long mxc_gettimeoffset(void)
-{
-        unsigned long ticks_to_match, elapsed, usec, tick_usec, i;
-
-        /* Get ticks before next timer match */
-        ticks_to_match =
-            __raw_readl(MXC_GPT_GPTOCR1) - __raw_readl(MXC_GPT_GPTCNT);
-
-        /* We need elapsed ticks since last match */
-        elapsed = LATCH - ticks_to_match;
-
-        /* Now convert them to usec */
-        /* Insure no overflow when calculating the usec below */
-        for (i = 1, tick_usec = tick_nsec / 1000;; i *= 2) {
-                tick_usec /= i;
-                if ((0xFFFFFFFF / tick_usec) > elapsed)
-                        break;
-        }
-        usec = (unsigned long)(elapsed * tick_usec) / (LATCH / i);
-
-        return usec;
-}
-
-/*!
- * The OS tick timer interrupt structure.
- */
-static struct irqaction timer_irq = {
-        .name = "MXC Timer Tick",
-        .flags = IRQF_DISABLED | IRQF_TIMER,
-        .handler = mxc_timer_interrupt
-};
-
-/*!
- * This function is used to initialize the GPT to produce an interrupt
- * based on HZ.  It is called by start_kernel() during system startup.
- */
-void __init mxc_init_time(void)
-{
-        u32 reg, v;
-        reg = __raw_readl(MXC_GPT_GPTCR);
-        reg &= ~GPTCR_ENABLE;
-        __raw_writel(reg, MXC_GPT_GPTCR);
-        reg |= GPTCR_SWR;
-        __raw_writel(reg, MXC_GPT_GPTCR);
-
-        while ((__raw_readl(MXC_GPT_GPTCR) & GPTCR_SWR) != 0)
-                cpu_relax();
-
-        reg = GPTCR_FRR | GPTCR_CLKSRC_HIGHFREQ;
-        __raw_writel(reg, MXC_GPT_GPTCR);
-
-        /* TODO: get timer rate from clk driver */
-        v = 66500000;
-
-        __raw_writel((v / CLOCK_TICK_RATE) - 1, MXC_GPT_GPTPR);
-
-        if ((v % CLOCK_TICK_RATE) != 0) {
-                pr_info("\nWARNING: Can't generate CLOCK_TICK_RATE at %d Hz\n",
-                        CLOCK_TICK_RATE);
-        }
-        pr_info("Actual CLOCK_TICK_RATE is %d Hz\n",
-                v / ((__raw_readl(MXC_GPT_GPTPR) & 0xFFF) + 1));
-
-        reg = __raw_readl(MXC_GPT_GPTCNT);
-        reg += LATCH;
-        __raw_writel(reg, MXC_GPT_GPTOCR1);
-
-        setup_irq(MXC_INT_GPT, &timer_irq);
-
-        reg = __raw_readl(MXC_GPT_GPTCR);
-        reg =
-            GPTCR_FRR | GPTCR_CLKSRC_HIGHFREQ | GPTCR_STOPEN | GPTCR_DOZEN |
-            GPTCR_WAITEN | GPTCR_ENMOD | GPTCR_ENABLE;
-        __raw_writel(reg, MXC_GPT_GPTCR);
-
-        __raw_writel(GPTIR_OF1IE, MXC_GPT_GPTIR);
-}
-
-struct sys_timer mxc_timer = {
-        .init = mxc_init_time,
-        .offset = mxc_gettimeoffset,
-};
diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile
index c06f5254c0f3..1bda8f5d7546 100644
--- a/arch/arm/mach-omap1/Makefile
+++ b/arch/arm/mach-omap1/Makefile
@@ -3,7 +3,9 @@
 #
 
 # Common support
-obj-y := io.o id.o clock.o irq.o mux.o serial.o devices.o
+obj-y := io.o id.o sram.o clock.o irq.o mux.o serial.o devices.o
+
+obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
 
 obj-$(CONFIG_OMAP_MPU_TIMER)    += time.o
 obj-$(CONFIG_OMAP_32K_TIMER)    += timer32k.o
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index bcb984f2300f..3f39e0e79c9f 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -10,6 +10,7 @@
 
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/mutex.h>
 #include <linux/platform_device.h>
 #include <linux/input.h>
 #include <linux/clk.h>
@@ -202,7 +203,7 @@ static struct omap_board_config_kernel nokia770_config[] __initdata = {
 #define AMPLIFIER_CTRL_GPIO     58
 
 static struct clk *dspxor_ck;
-static DECLARE_MUTEX(audio_pwr_sem);
+static DEFINE_MUTEX(audio_pwr_lock);
 /*
  * audio_pwr_state
  * +--+-------------------------+---------------------------------------+
@@ -218,7 +219,7 @@ static DECLARE_MUTEX(audio_pwr_sem);
 static int audio_pwr_state = -1;
 
 /*
- * audio_pwr_up / down should be called under audio_pwr_sem
+ * audio_pwr_up / down should be called under audio_pwr_lock
  */
 static void nokia770_audio_pwr_up(void)
 {
@@ -237,11 +238,11 @@ static void nokia770_audio_pwr_up(void)
 
 static void codec_delayed_power_down(struct work_struct *work)
 {
-        down(&audio_pwr_sem);
+        mutex_lock(&audio_pwr_lock);
         if (audio_pwr_state == -1)
                 aic23_power_down();
         clk_disable(dspxor_ck);
-        up(&audio_pwr_sem);
+        mutex_unlock(&audio_pwr_lock);
 }
 
 static DECLARE_DELAYED_WORK(codec_power_down_work, codec_delayed_power_down);
@@ -258,19 +259,19 @@ static void nokia770_audio_pwr_down(void)
 static int
 nokia770_audio_pwr_up_request(struct dsp_kfunc_device *kdev, int stage)
 {
-        down(&audio_pwr_sem);
+        mutex_lock(&audio_pwr_lock);
         if (audio_pwr_state == -1)
                 nokia770_audio_pwr_up();
         /* force audio_pwr_state = 0, even if it was 1. */
         audio_pwr_state = 0;
-        up(&audio_pwr_sem);
+        mutex_unlock(&audio_pwr_lock);
         return 0;
 }
 
 static int
 nokia770_audio_pwr_down_request(struct dsp_kfunc_device *kdev, int stage)
 {
-        down(&audio_pwr_sem);
+        mutex_lock(&audio_pwr_lock);
         switch (stage) {
         case 1:
                 if (audio_pwr_state == 0)
@@ -283,7 +284,7 @@ nokia770_audio_pwr_down_request(struct dsp_kfunc_device *kdev, int stage)
                 }
                 break;
         }
-        up(&audio_pwr_sem);
+        mutex_unlock(&audio_pwr_lock);
         return 0;
 }
 
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index a66505f58b15..845c66371ca3 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -267,13 +267,17 @@ static struct i2c_board_info __initdata osk_i2c_board_info[] = {
 
 static void __init osk_init_smc91x(void)
 {
+        u32 l;
+
         if ((gpio_request(0, "smc_irq")) < 0) {
                 printk("Error requesting gpio 0 for smc91x irq\n");
                 return;
         }
 
         /* Check EMIFS wait states to fix errors with SMC_GET_PKT_HDR */
-        EMIFS_CCS(1) |= 0x3;
+        l = omap_readl(EMIFS_CCS(1));
+        l |= 0x3;
+        omap_writel(l, EMIFS_CCS(1));
 }
 
 static void __init osk_init_cf(void)
@@ -526,20 +530,26 @@ static void __init osk_mistral_init(void) { }
 
 static void __init osk_init(void)
 {
+        u32 l;
+
         /* Workaround for wrong CS3 (NOR flash) timing
          * There are some U-Boot versions out there which configure
          * wrong CS3 memory timings. This mainly leads to CRC
          * or similar errors if you use NOR flash (e.g. with JFFS2)
          */
-        if (EMIFS_CCS(3) != EMIFS_CS3_VAL)
-                EMIFS_CCS(3) = EMIFS_CS3_VAL;
+        l = omap_readl(EMIFS_CCS(3));
+        if (l != EMIFS_CS3_VAL)
+                omap_writel(EMIFS_CS3_VAL, EMIFS_CCS(3));
 
         osk_flash_resource.end = osk_flash_resource.start = omap_cs3_phys();
         osk_flash_resource.end += SZ_32M - 1;
         platform_add_devices(osk5912_devices, ARRAY_SIZE(osk5912_devices));
         omap_board_config = osk_config;
         omap_board_config_size = ARRAY_SIZE(osk_config);
-        USB_TRANSCEIVER_CTRL_REG |= (3 << 1);
+
+        l = omap_readl(USB_TRANSCEIVER_CTRL);
+        l |= (3 << 1);
+        omap_writel(l, USB_TRANSCEIVER_CTRL);
 
         /* irq for tps65010 chip */
         /* bootloader effectively does:  omap_cfg_reg(U19_1610_MPUIO1); */
diff --git a/arch/arm/mach-omap1/fpga.c b/arch/arm/mach-omap1/fpga.c
index 30e188109046..0cf62ef5ecb7 100644
--- a/arch/arm/mach-omap1/fpga.c
+++ b/arch/arm/mach-omap1/fpga.c
@@ -32,7 +32,7 @@
 
 static void fpga_mask_irq(unsigned int irq)
 {
-        irq -= OMAP1510_IH_FPGA_BASE;
+        irq -= OMAP_FPGA_IRQ_BASE;
 
         if (irq < 8)
                 __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_LO)
@@ -65,7 +65,7 @@ static void fpga_ack_irq(unsigned int irq)
 
 static void fpga_unmask_irq(unsigned int irq)
 {
-        irq -= OMAP1510_IH_FPGA_BASE;
+        irq -= OMAP_FPGA_IRQ_BASE;
 
         if (irq < 8)
                 __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_LO) | (1 << irq)),
@@ -95,8 +95,8 @@ void innovator_fpga_IRQ_demux(unsigned int irq, struct irq_desc *desc)
         if (!stat)
                 return;
 
-        for (fpga_irq = OMAP1510_IH_FPGA_BASE;
-             (fpga_irq < (OMAP1510_IH_FPGA_BASE + NR_FPGA_IRQS)) && stat;
+        for (fpga_irq = OMAP_FPGA_IRQ_BASE;
+             (fpga_irq < OMAP_FPGA_IRQ_END) && stat;
              fpga_irq++, stat >>= 1) {
                 if (stat & 1) {
                         d = irq_desc + fpga_irq;
@@ -151,7 +151,7 @@ void omap1510_fpga_init_irq(void)
         __raw_writeb(0, OMAP1510_FPGA_IMR_HI);
         __raw_writeb(0, INNOVATOR_FPGA_IMR2);
 
-        for (i = OMAP1510_IH_FPGA_BASE; i < (OMAP1510_IH_FPGA_BASE + NR_FPGA_IRQS); i++) {
+        for (i = OMAP_FPGA_IRQ_BASE; i < OMAP_FPGA_IRQ_END; i++) {
 
                 if (i == OMAP1510_INT_FPGA_TS) {
                         /*
diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c
new file mode 100644
index 000000000000..2d2c2522b048
--- /dev/null
+++ b/arch/arm/mach-omap1/mcbsp.c
@@ -0,0 +1,280 @@
+/*
+ * linux/arch/arm/mach-omap1/mcbsp.c
+ *
+ * Copyright (C) 2008 Instituto Nokia de Tecnologia
+ * Contact: Eduardo Valentin <eduardo.valentin@indt.org.br>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Multichannel mode not supported.
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+
+#include <asm/arch/dma.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/mcbsp.h>
+#include <asm/arch/dsp_common.h>
+
+#define DPS_RSTCT2_PER_EN       (1 << 0)
+#define DSP_RSTCT2_WD_PER_EN    (1 << 1)
+
+struct mcbsp_internal_clk {
+        struct clk clk;
+        struct clk **childs;
+        int n_childs;
+};
+
+#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
+static void omap_mcbsp_clk_init(struct mcbsp_internal_clk *mclk)
+{
+        const char *clk_names[] = { "dsp_ck", "api_ck", "dspxor_ck" };
+        int i;
+
+        mclk->n_childs = ARRAY_SIZE(clk_names);
+        mclk->childs = kzalloc(mclk->n_childs * sizeof(struct clk *),
+                                GFP_KERNEL);
+
+        for (i = 0; i < mclk->n_childs; i++) {
+                /* We fake a platform device to get correct device id */
+                struct platform_device pdev;
+
+                pdev.dev.bus = &platform_bus_type;
+                pdev.id = mclk->clk.id;
+                mclk->childs[i] = clk_get(&pdev.dev, clk_names[i]);
+                if (IS_ERR(mclk->childs[i]))
+                        printk(KERN_ERR "Could not get clock %s (%d).\n",
+                                clk_names[i], mclk->clk.id);
+        }
+}
+
+static int omap_mcbsp_clk_enable(struct clk *clk)
+{
+        struct mcbsp_internal_clk *mclk = container_of(clk,
+                                        struct mcbsp_internal_clk, clk);
+        int i;
+
+        for (i = 0; i < mclk->n_childs; i++)
+                clk_enable(mclk->childs[i]);
+        return 0;
+}
+
+static void omap_mcbsp_clk_disable(struct clk *clk)
+{
+        struct mcbsp_internal_clk *mclk = container_of(clk,
+                                        struct mcbsp_internal_clk, clk);
+        int i;
+
+        for (i = 0; i < mclk->n_childs; i++)
+                clk_disable(mclk->childs[i]);
+}
+
+static struct mcbsp_internal_clk omap_mcbsp_clks[] = {
+        {
+                .clk = {
+                        .name           = "mcbsp_clk",
+                        .id             = 1,
+                        .enable         = omap_mcbsp_clk_enable,
+                        .disable        = omap_mcbsp_clk_disable,
+                },
+        },
+        {
+                .clk = {
+                        .name           = "mcbsp_clk",
+                        .id             = 3,
+                        .enable         = omap_mcbsp_clk_enable,
+                        .disable        = omap_mcbsp_clk_disable,
+                },
+        },
+};
+
+#define omap_mcbsp_clks_size    ARRAY_SIZE(omap_mcbsp_clks)
+#else
+#define omap_mcbsp_clks_size    0
+static struct mcbsp_internal_clk __initdata *omap_mcbsp_clks;
+static inline void omap_mcbsp_clk_init(struct mcbsp_internal_clk *mclk)
+{ }
+#endif
+
+static int omap1_mcbsp_check(unsigned int id)
+{
+        /* REVISIT: Check correctly for number of registered McBSPs */
+        if (cpu_is_omap730()) {
+                if (id > OMAP_MAX_MCBSP_COUNT - 2) {
+                       printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n",
+                                id + 1);
+                       return -ENODEV;
+                }
+                return 0;
+        }
+
+        if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
+                if (id > OMAP_MAX_MCBSP_COUNT - 1) {
+                        printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n",
+                                id + 1);
+                        return -ENODEV;
+                }
+                return 0;
+        }
+
+        return -ENODEV;
+}
+
+static void omap1_mcbsp_request(unsigned int id)
+{
+        /*
+         * On 1510, 1610 and 1710, McBSP1 and McBSP3
+         * are DSP public peripherals.
+         */
+        if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3) {
+                omap_dsp_request_mem();
+                /*
+                 * DSP external peripheral reset
+                 * FIXME: This should be moved to dsp code
+                 */
+                __raw_writew(__raw_readw(DSP_RSTCT2) | DPS_RSTCT2_PER_EN |
+                                DSP_RSTCT2_WD_PER_EN, DSP_RSTCT2);
+        }
+}
+
+static void omap1_mcbsp_free(unsigned int id)
+{
+        if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3)
+                omap_dsp_release_mem();
+}
+
+static struct omap_mcbsp_ops omap1_mcbsp_ops = {
+        .check          = omap1_mcbsp_check,
+        .request        = omap1_mcbsp_request,
+        .free           = omap1_mcbsp_free,
+};
+
+#ifdef CONFIG_ARCH_OMAP730
+static struct omap_mcbsp_platform_data omap730_mcbsp_pdata[] = {
+        {
+                .virt_base      = io_p2v(OMAP730_MCBSP1_BASE),
+                .dma_rx_sync    = OMAP_DMA_MCBSP1_RX,
+                .dma_tx_sync    = OMAP_DMA_MCBSP1_TX,
+                .rx_irq         = INT_730_McBSP1RX,
+                .tx_irq         = INT_730_McBSP1TX,
+                .ops            = &omap1_mcbsp_ops,
+        },
+        {
+                .virt_base      = io_p2v(OMAP730_MCBSP2_BASE),
+                .dma_rx_sync    = OMAP_DMA_MCBSP3_RX,
+                .dma_tx_sync    = OMAP_DMA_MCBSP3_TX,
+                .rx_irq         = INT_730_McBSP2RX,
+                .tx_irq         = INT_730_McBSP2TX,
+                .ops            = &omap1_mcbsp_ops,
+        },
+};
+#define OMAP730_MCBSP_PDATA_SZ          ARRAY_SIZE(omap730_mcbsp_pdata)
+#else
+#define omap730_mcbsp_pdata             NULL
+#define OMAP730_MCBSP_PDATA_SZ          0
+#endif
+
+#ifdef CONFIG_ARCH_OMAP15XX
+static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = {
+        {
+                .virt_base      = OMAP1510_MCBSP1_BASE,
+                .dma_rx_sync    = OMAP_DMA_MCBSP1_RX,
+                .dma_tx_sync    = OMAP_DMA_MCBSP1_TX,
+                .rx_irq         = INT_McBSP1RX,
+                .tx_irq         = INT_McBSP1TX,
+                .ops            = &omap1_mcbsp_ops,
+                .clk_name       = "mcbsp_clk",
+                },
+        {
+                .virt_base      = io_p2v(OMAP1510_MCBSP2_BASE),
+                .dma_rx_sync    = OMAP_DMA_MCBSP2_RX,
+                .dma_tx_sync    = OMAP_DMA_MCBSP2_TX,
+                .rx_irq         = INT_1510_SPI_RX,
+                .tx_irq         = INT_1510_SPI_TX,
+                .ops            = &omap1_mcbsp_ops,
+        },
+        {
+                .virt_base      = OMAP1510_MCBSP3_BASE,
+                .dma_rx_sync    = OMAP_DMA_MCBSP3_RX,
+                .dma_tx_sync    = OMAP_DMA_MCBSP3_TX,
+                .rx_irq         = INT_McBSP3RX,
+                .tx_irq         = INT_McBSP3TX,
+                .ops            = &omap1_mcbsp_ops,
+                .clk_name       = "mcbsp_clk",
+        },
+};
+#define OMAP15XX_MCBSP_PDATA_SZ         ARRAY_SIZE(omap15xx_mcbsp_pdata)
+#else
+#define omap15xx_mcbsp_pdata            NULL
+#define OMAP15XX_MCBSP_PDATA_SZ         0
+#endif
+
+#ifdef CONFIG_ARCH_OMAP16XX
+static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = {
+        {
+                .virt_base      = OMAP1610_MCBSP1_BASE,
+                .dma_rx_sync    = OMAP_DMA_MCBSP1_RX,
+                .dma_tx_sync    = OMAP_DMA_MCBSP1_TX,
+                .rx_irq         = INT_McBSP1RX,
+                .tx_irq         = INT_McBSP1TX,
+                .ops            = &omap1_mcbsp_ops,
+                .clk_name       = "mcbsp_clk",
+        },
+        {
+                .virt_base      = io_p2v(OMAP1610_MCBSP2_BASE),
+                .dma_rx_sync    = OMAP_DMA_MCBSP2_RX,
+                .dma_tx_sync    = OMAP_DMA_MCBSP2_TX,
+                .rx_irq         = INT_1610_McBSP2_RX,
+                .tx_irq         = INT_1610_McBSP2_TX,
+                .ops            = &omap1_mcbsp_ops,
+        },
+        {
+                .virt_base      = OMAP1610_MCBSP3_BASE,
+                .dma_rx_sync    = OMAP_DMA_MCBSP3_RX,
+                .dma_tx_sync    = OMAP_DMA_MCBSP3_TX,
+                .rx_irq         = INT_McBSP3RX,
+                .tx_irq         = INT_McBSP3TX,
+                .ops            = &omap1_mcbsp_ops,
+                .clk_name       = "mcbsp_clk",
+        },
+};
+#define OMAP16XX_MCBSP_PDATA_SZ         ARRAY_SIZE(omap16xx_mcbsp_pdata)
+#else
+#define omap16xx_mcbsp_pdata            NULL
+#define OMAP16XX_MCBSP_PDATA_SZ         0
+#endif
+
+int __init omap1_mcbsp_init(void)
+{
+        int i;
+
+        for (i = 0; i < omap_mcbsp_clks_size; i++) {
+                if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
+                        omap_mcbsp_clk_init(&omap_mcbsp_clks[i]);
+                        clk_register(&omap_mcbsp_clks[i].clk);
+                }
+        }
+
+        if (cpu_is_omap730())
+                omap_mcbsp_register_board_cfg(omap730_mcbsp_pdata,
+                                                OMAP730_MCBSP_PDATA_SZ);
+
+        if (cpu_is_omap15xx())
+                omap_mcbsp_register_board_cfg(omap15xx_mcbsp_pdata,
+                                                OMAP15XX_MCBSP_PDATA_SZ);
+
+        if (cpu_is_omap16xx())
+                omap_mcbsp_register_board_cfg(omap16xx_mcbsp_pdata,
+                                                OMAP16XX_MCBSP_PDATA_SZ);
+
+        return omap_mcbsp_init();
+}
+
+arch_initcall(omap1_mcbsp_init);
diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c
index e6c64e10b7ec..742f79e73bd7 100644
--- a/arch/arm/mach-omap1/pm.c
+++ b/arch/arm/mach-omap1/pm.c
@@ -116,13 +116,6 @@ void omap_pm_idle(void)
                 return;
         }
 
-        /*
-         * Since an interrupt may set up a timer, we don't want to
-         * reprogram the hardware timer with interrupts enabled.
-         * Re-enable interrupts only after returning from idle.
-         */
-        timer_dyn_reprogram();
-
 #ifdef CONFIG_OMAP_MPU_TIMER
 #warning Enable 32kHz OS timer in order to allow sleep states in idle
         use_idlect1 = use_idlect1 & ~(1 << 9);
diff --git a/arch/arm/plat-omap/sram-fn.S b/arch/arm/mach-omap1/sram.S
index 9e1813c77e05..126d252062d7 100644
--- a/arch/arm/plat-omap/sram-fn.S
+++ b/arch/arm/mach-omap1/sram.S
@@ -18,7 +18,7 @@
 /*
  * Reprograms ULPD and CKCTL.
  */
-ENTRY(sram_reprogram_clock)
+ENTRY(omap1_sram_reprogram_clock)
         stmfd   sp!, {r0 - r12, lr}             @ save registers on stack
 
         mov     r2, #IO_ADDRESS(DPLL_CTL) & 0xff000000
@@ -53,5 +53,5 @@ lock:	ldrh	r4, [r2], #0			@ read back dpll value
 
 out:
         ldmfd   sp!, {r0 - r12, pc}             @ restore regs and return
-ENTRY(sram_reprogram_clock_sz)
-        .word   . - sram_reprogram_clock
+ENTRY(omap1_sram_reprogram_clock_sz)
+        .word   . - omap1_sram_reprogram_clock
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 2feb6870b735..93ee990618ef 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -3,9 +3,15 @@
 #
 
 # Common support
-obj-y := irq.o id.o io.o sram-fn.o memory.o control.o prcm.o clock.o mux.o \
+obj-y := irq.o id.o io.o memory.o control.o prcm.o clock.o mux.o \
                 devices.o serial.o gpmc.o timer-gp.o
 
+obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
+
+# Functions loaded to SRAM
+obj-$(CONFIG_ARCH_OMAP2420)             += sram242x.o
+obj-$(CONFIG_ARCH_OMAP2430)             += sram243x.o
+
 # Power Management
 obj-$(CONFIG_PM) += pm.o sleep.o
 
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index ab9fc57d25f1..15675bce8012 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -41,6 +41,24 @@
 
 #define MAX_CLOCK_ENABLE_WAIT           100000
 
+/* DPLL rate rounding: minimum DPLL multiplier, divider values */
+#define DPLL_MIN_MULTIPLIER             1
+#define DPLL_MIN_DIVIDER                1
+
+/* Possible error results from _dpll_test_mult */
+#define DPLL_MULT_UNDERFLOW             (1 << 0)
+
+/*
+ * Scale factor to mitigate roundoff errors in DPLL rate rounding.
+ * The higher the scale factor, the greater the risk of arithmetic overflow,
+ * but the closer the rounded rate to the target rate.  DPLL_SCALE_FACTOR
+ * must be a power of DPLL_SCALE_BASE.
+ */
+#define DPLL_SCALE_FACTOR               64
+#define DPLL_SCALE_BASE                 2
+#define DPLL_ROUNDING_VAL               ((DPLL_SCALE_BASE / 2) * \
+                                         (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
+
 u8 cpu_mask;
 
 /*-------------------------------------------------------------------------
@@ -95,7 +113,7 @@ u32 omap2_get_dpll_rate(struct clk *clk)
 {
         long long dpll_clk;
         u32 dpll_mult, dpll_div, dpll;
-        const struct dpll_data *dd;
+        struct dpll_data *dd;
 
         dd = clk->dpll_data;
         /* REVISIT: What do we return on error? */
@@ -603,7 +621,8 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
         clk->rate = clk->parent->rate / new_div;
 
         if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
-                __raw_writel(OMAP24XX_VALID_CONFIG, OMAP24XX_PRCM_CLKCFG_CTRL);
+                prm_write_mod_reg(OMAP24XX_VALID_CONFIG,
+                        OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
                 wmb();
         }
 
@@ -723,6 +742,184 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
         return 0;
 }
 
+/* DPLL rate rounding code */
+
+/**
+ * omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding
+ * @clk: struct clk * of the DPLL
+ * @tolerance: maximum rate error tolerance
+ *
+ * Set the maximum DPLL rate error tolerance for the rate rounding
+ * algorithm.  The rate tolerance is an attempt to balance DPLL power
+ * saving (the least divider value "n") vs. rate fidelity (the least
+ * difference between the desired DPLL target rate and the rounded
+ * rate out of the algorithm).  So, increasing the tolerance is likely
+ * to decrease DPLL power consumption and increase DPLL rate error.
+ * Returns -EINVAL if provided a null clock ptr or a clk that is not a
+ * DPLL; or 0 upon success.
+ */
+int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance)
+{
+        if (!clk || !clk->dpll_data)
+                return -EINVAL;
+
+        clk->dpll_data->rate_tolerance = tolerance;
+
+        return 0;
+}
+
+static unsigned long _dpll_compute_new_rate(unsigned long parent_rate, unsigned int m, unsigned int n)
+{
+        unsigned long long num;
+
+        num = (unsigned long long)parent_rate * m;
+        do_div(num, n);
+        return num;
+}
+
+/*
+ * _dpll_test_mult - test a DPLL multiplier value
+ * @m: pointer to the DPLL m (multiplier) value under test
+ * @n: current DPLL n (divider) value under test
+ * @new_rate: pointer to storage for the resulting rounded rate
+ * @target_rate: the desired DPLL rate
+ * @parent_rate: the DPLL's parent clock rate
+ *
+ * This code tests a DPLL multiplier value, ensuring that the
+ * resulting rate will not be higher than the target_rate, and that
+ * the multiplier value itself is valid for the DPLL.  Initially, the
+ * integer pointed to by the m argument should be prescaled by
+ * multiplying by DPLL_SCALE_FACTOR.  The code will replace this with
+ * a non-scaled m upon return.  This non-scaled m will result in a
+ * new_rate as close as possible to target_rate (but not greater than
+ * target_rate) given the current (parent_rate, n, prescaled m)
+ * triple. Returns DPLL_MULT_UNDERFLOW in the event that the
+ * non-scaled m attempted to underflow, which can allow the calling
+ * function to bail out early; or 0 upon success.
+ */
+static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
+                           unsigned long target_rate,
+                           unsigned long parent_rate)
+{
+        int flags = 0, carry = 0;
+
+        /* Unscale m and round if necessary */
+        if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL)
+                carry = 1;
+        *m = (*m / DPLL_SCALE_FACTOR) + carry;
+
+        /*
+         * The new rate must be <= the target rate to avoid programming
+         * a rate that is impossible for the hardware to handle
+         */
+        *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
+        if (*new_rate > target_rate) {
+                (*m)--;
+                *new_rate = 0;
+        }
+
+        /* Guard against m underflow */
+        if (*m < DPLL_MIN_MULTIPLIER) {
+                *m = DPLL_MIN_MULTIPLIER;
+                *new_rate = 0;
+                flags = DPLL_MULT_UNDERFLOW;
+        }
+
+        if (*new_rate == 0)
+                *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
+
+        return flags;
+}
+
+/**
+ * omap2_dpll_round_rate - round a target rate for an OMAP DPLL
+ * @clk: struct clk * for a DPLL
+ * @target_rate: desired DPLL clock rate
+ *
+ * Given a DPLL, a desired target rate, and a rate tolerance, round
+ * the target rate to a possible, programmable rate for this DPLL.
+ * Rate tolerance is assumed to be set by the caller before this
+ * function is called.  Attempts to select the minimum possible n
+ * within the tolerance to reduce power consumption.  Stores the
+ * computed (m, n) in the DPLL's dpll_data structure so set_rate()
+ * will not need to call this (expensive) function again.  Returns ~0
+ * if the target rate cannot be rounded, either because the rate is
+ * too low or because the rate tolerance is set too tightly; or the
+ * rounded rate upon success.
+ */
+long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
+{
+        int m, n, r, e, scaled_max_m;
+        unsigned long scaled_rt_rp, new_rate;
+        int min_e = -1, min_e_m = -1, min_e_n = -1;
+
+        if (!clk || !clk->dpll_data)
+                return ~0;
+
+        pr_debug("clock: starting DPLL round_rate for clock %s, target rate "
+                 "%ld\n", clk->name, target_rate);
+
+        scaled_rt_rp = target_rate / (clk->parent->rate / DPLL_SCALE_FACTOR);
+        scaled_max_m = clk->dpll_data->max_multiplier * DPLL_SCALE_FACTOR;
+
+        clk->dpll_data->last_rounded_rate = 0;
+
+        for (n = clk->dpll_data->max_divider; n >= DPLL_MIN_DIVIDER; n--) {
+
+                /* Compute the scaled DPLL multiplier, based on the divider */
+                m = scaled_rt_rp * n;
+
+                /*
+                 * Since we're counting n down, a m overflow means we can
+                 * can immediately skip to the next n
+                 */
+                if (m > scaled_max_m)
+                        continue;
+
+                r = _dpll_test_mult(&m, n, &new_rate, target_rate,
+                                    clk->parent->rate);
+
+                e = target_rate - new_rate;
+                pr_debug("clock: n = %d: m = %d: rate error is %d "
+                         "(new_rate = %ld)\n", n, m, e, new_rate);
+
+                if (min_e == -1 ||
+                    min_e >= (int)(abs(e) - clk->dpll_data->rate_tolerance)) {
+                        min_e = e;
+                        min_e_m = m;
+                        min_e_n = n;
+
+                        pr_debug("clock: found new least error %d\n", min_e);
+                }
+
+                /*
+                 * Since we're counting n down, a m underflow means we
+                 * can bail out completely (since as n decreases in
+                 * the next iteration, there's no way that m can
+                 * increase beyond the current m)
+                 */
+                if (r & DPLL_MULT_UNDERFLOW)
+                        break;
+        }
+
+        if (min_e < 0) {
+                pr_debug("clock: error: target rate or tolerance too low\n");
+                return ~0;
+        }
+
+        clk->dpll_data->last_rounded_m = min_e_m;
+        clk->dpll_data->last_rounded_n = min_e_n;
+        clk->dpll_data->last_rounded_rate =
+                _dpll_compute_new_rate(clk->parent->rate, min_e_m,  min_e_n);
+
+        pr_debug("clock: final least error: e = %d, m = %d, n = %d\n",
+                 min_e, min_e_m, min_e_n);
+        pr_debug("clock: final rate: %ld  (target rate: %ld)\n",
+                 clk->dpll_data->last_rounded_rate, target_rate);
+
+        return clk->dpll_data->last_rounded_rate;
+}
+
 /*-------------------------------------------------------------------------
  * Omap2 clock reset and init functions
  *-------------------------------------------------------------------------*/
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index d5980a9e09a4..3cd37cb57c5a 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -18,11 +18,16 @@
 
 #include <asm/arch/clock.h>
 
+/* The maximum error between a target DPLL rate and the rounded rate in Hz */
+#define DEFAULT_DPLL_RATE_TOLERANCE     50000
+
 int omap2_clk_enable(struct clk *clk);
 void omap2_clk_disable(struct clk *clk);
 long omap2_clk_round_rate(struct clk *clk, unsigned long rate);
 int omap2_clk_set_rate(struct clk *clk, unsigned long rate);
 int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent);
+int omap2_dpll_rate_tolerance_set(struct clk *clk, unsigned int tolerance);
+long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate);
 
 #ifdef CONFIG_OMAP_RESET_CLOCKS
 void omap2_clk_disable_unused(struct clk *clk);
@@ -42,6 +47,7 @@ long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
 int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
 u32 omap2_get_dpll_rate(struct clk *clk);
 int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name);
+void omap2_clk_prepare_for_reboot(void);
 
 extern u8 cpu_mask;
 
diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c
index ece32d8acba4..aa567876651d 100644
--- a/arch/arm/mach-omap2/clock24xx.c
+++ b/arch/arm/mach-omap2/clock24xx.c
@@ -154,7 +154,7 @@ static void omap2_clk_fixed_disable(struct clk *clk)
  * Uses the current prcm set to tell if a rate is valid.
  * You can go slower, but not faster within a given rate set.
  */
-static u32 omap2_dpll_round_rate(unsigned long target_rate)
+long omap2_dpllcore_round_rate(unsigned long target_rate)
 {
         u32 high, low, core_clk_src;
 
@@ -183,14 +183,14 @@ static u32 omap2_dpll_round_rate(unsigned long target_rate)
 
 }
 
-static void omap2_dpll_recalc(struct clk *clk)
+static void omap2_dpllcore_recalc(struct clk *clk)
 {
         clk->rate = omap2_get_dpll_rate_24xx(clk);
 
         propagate_rate(clk);
 }
 
-static int omap2_reprogram_dpll(struct clk *clk, unsigned long rate)
+static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
 {
         u32 cur_rate, low, mult, div, valid_rate, done_rate;
         u32 bypass = 0;
@@ -209,7 +209,7 @@ static int omap2_reprogram_dpll(struct clk *clk, unsigned long rate)
         } else if ((rate == (cur_rate * 2)) && (mult == 1)) {
                 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
         } else if (rate != cur_rate) {
-                valid_rate = omap2_dpll_round_rate(rate);
+                valid_rate = omap2_dpllcore_round_rate(rate);
                 if (valid_rate != rate)
                         goto dpll_exit;
 
@@ -256,7 +256,7 @@ static int omap2_reprogram_dpll(struct clk *clk, unsigned long rate)
                 omap2_init_memory_params(omap2_dll_force_needed());
                 omap2_reprogram_sdrc(done_rate, 0);
         }
-        omap2_dpll_recalc(&dpll_ck);
+        omap2_dpllcore_recalc(&dpll_ck);
         ret = 0;
 
 dpll_exit:
@@ -383,7 +383,7 @@ static int omap2_select_table_rate(struct clk *clk, unsigned long rate)
 
                 local_irq_restore(flags);
         }
-        omap2_dpll_recalc(&dpll_ck);
+        omap2_dpllcore_recalc(&dpll_ck);
 
         return 0;
 }
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h
index 88081ed13f96..be4e25554e05 100644
--- a/arch/arm/mach-omap2/clock24xx.h
+++ b/arch/arm/mach-omap2/clock24xx.h
@@ -30,12 +30,12 @@ static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
 static void omap2_sys_clk_recalc(struct clk *clk);
 static void omap2_osc_clk_recalc(struct clk *clk);
 static void omap2_sys_clk_recalc(struct clk *clk);
-static void omap2_dpll_recalc(struct clk *clk);
+static void omap2_dpllcore_recalc(struct clk *clk);
 static int omap2_clk_fixed_enable(struct clk *clk);
 static void omap2_clk_fixed_disable(struct clk *clk);
 static int omap2_enable_osc_ck(struct clk *clk);
 static void omap2_disable_osc_ck(struct clk *clk);
-static int omap2_reprogram_dpll(struct clk *clk, unsigned long rate);
+static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate);
 
 /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
@@ -665,20 +665,27 @@ static struct clk alt_ck = {		/* Typical 54M or 48M, may not exist */
  * deal with this
  */
 
-static const struct dpll_data dpll_dd = {
+static struct dpll_data dpll_dd = {
         .mult_div1_reg          = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
         .mult_mask              = OMAP24XX_DPLL_MULT_MASK,
         .div1_mask              = OMAP24XX_DPLL_DIV_MASK,
+        .max_multiplier         = 1024,
+        .max_divider            = 16,
+        .rate_tolerance         = DEFAULT_DPLL_RATE_TOLERANCE
 };
 
+/*
+ * XXX Cannot add round_rate here yet, as this is still a composite clock,
+ * not just a DPLL
+ */
 static struct clk dpll_ck = {
         .name           = "dpll_ck",
         .parent         = &sys_ck,              /* Can be func_32k also */
         .dpll_data      = &dpll_dd,
         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
                                 RATE_PROPAGATES | ALWAYS_ENABLED,
-        .recalc         = &omap2_dpll_recalc,
-        .set_rate       = &omap2_reprogram_dpll,
+        .recalc         = &omap2_dpllcore_recalc,
+        .set_rate       = &omap2_reprogram_dpllcore,
 };
 
 static struct clk apll96_ck = {
@@ -1747,7 +1754,8 @@ static struct clk gpt12_fck = {
 };
 
 static struct clk mcbsp1_ick = {
-        .name           = "mcbsp1_ick",
+        .name           = "mcbsp_ick",
+        .id             = 1,
         .parent         = &l4_ck,
         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1756,7 +1764,8 @@ static struct clk mcbsp1_ick = {
 };
 
 static struct clk mcbsp1_fck = {
-        .name           = "mcbsp1_fck",
+        .name           = "mcbsp_fck",
+        .id             = 1,
         .parent         = &func_96m_ck,
         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
@@ -1765,7 +1774,8 @@ static struct clk mcbsp1_fck = {
 };
 
 static struct clk mcbsp2_ick = {
-        .name           = "mcbsp2_ick",
+        .name           = "mcbsp_ick",
+        .id             = 2,
         .parent         = &l4_ck,
         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1774,7 +1784,8 @@ static struct clk mcbsp2_ick = {
 };
 
 static struct clk mcbsp2_fck = {
-        .name           = "mcbsp2_fck",
+        .name           = "mcbsp_fck",
+        .id             = 2,
         .parent         = &func_96m_ck,
         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
@@ -1783,7 +1794,8 @@ static struct clk mcbsp2_fck = {
 };
 
 static struct clk mcbsp3_ick = {
-        .name           = "mcbsp3_ick",
+        .name           = "mcbsp_ick",
+        .id             = 3,
         .parent         = &l4_ck,
         .flags          = CLOCK_IN_OMAP243X,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1792,7 +1804,8 @@ static struct clk mcbsp3_ick = {
 };
 
 static struct clk mcbsp3_fck = {
-        .name           = "mcbsp3_fck",
+        .name           = "mcbsp_fck",
+        .id             = 3,
         .parent         = &func_96m_ck,
         .flags          = CLOCK_IN_OMAP243X,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
@@ -1801,7 +1814,8 @@ static struct clk mcbsp3_fck = {
 };
 
 static struct clk mcbsp4_ick = {
-        .name           = "mcbsp4_ick",
+        .name           = "mcbsp_ick",
+        .id             = 4,
         .parent         = &l4_ck,
         .flags          = CLOCK_IN_OMAP243X,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1810,7 +1824,8 @@ static struct clk mcbsp4_ick = {
 };
 
 static struct clk mcbsp4_fck = {
-        .name           = "mcbsp4_fck",
+        .name           = "mcbsp_fck",
+        .id             = 4,
         .parent         = &func_96m_ck,
         .flags          = CLOCK_IN_OMAP243X,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
@@ -1819,7 +1834,8 @@ static struct clk mcbsp4_fck = {
 };
 
 static struct clk mcbsp5_ick = {
-        .name           = "mcbsp5_ick",
+        .name           = "mcbsp_ick",
+        .id             = 5,
         .parent         = &l4_ck,
         .flags          = CLOCK_IN_OMAP243X,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1828,7 +1844,8 @@ static struct clk mcbsp5_ick = {
 };
 
 static struct clk mcbsp5_fck = {
-        .name           = "mcbsp5_fck",
+        .name           = "mcbsp_fck",
+        .id             = 5,
         .parent         = &func_96m_ck,
         .flags          = CLOCK_IN_OMAP243X,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index b42bdd6079a5..4263099b1ad3 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -1,10 +1,11 @@
 /*
  * OMAP3-specific clock framework functions
  *
- * Copyright (C) 2007 Texas Instruments, Inc.
- * Copyright (C) 2007 Nokia Corporation
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008 Nokia Corporation
  *
  * Written by Paul Walmsley
+ * Testing and integration fixes by Jouni Högander
  *
  * Parts of this code are based on code written by
  * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
@@ -23,6 +24,7 @@
 #include <linux/delay.h>
 #include <linux/clk.h>
 #include <linux/io.h>
+#include <linux/limits.h>
 
 #include <asm/arch/clock.h>
 #include <asm/arch/sram.h>
@@ -37,8 +39,11 @@
 #include "cm.h"
 #include "cm-regbits-34xx.h"
 
-/* CM_CLKEN_PLL*.EN* bit values */
-#define DPLL_LOCKED             0x7
+/* CM_AUTOIDLE_PLL*.AUTO_* bit values */
+#define DPLL_AUTOIDLE_DISABLE                   0x0
+#define DPLL_AUTOIDLE_LOW_POWER_STOP            0x1
+
+#define MAX_DPLL_WAIT_TRIES             1000000
 
 /**
  * omap3_dpll_recalc - recalculate DPLL rate
@@ -53,6 +58,290 @@ static void omap3_dpll_recalc(struct clk *clk)
         propagate_rate(clk);
 }
 
+/* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
+static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
+{
+        const struct dpll_data *dd;
+
+        dd = clk->dpll_data;
+
+        cm_rmw_reg_bits(dd->enable_mask, clken_bits << __ffs(dd->enable_mask),
+                        dd->control_reg);
+}
+
+/* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
+static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
+{
+        const struct dpll_data *dd;
+        int i = 0;
+        int ret = -EINVAL;
+        u32 idlest_mask;
+
+        dd = clk->dpll_data;
+
+        state <<= dd->idlest_bit;
+        idlest_mask = 1 << dd->idlest_bit;
+
+        while (((cm_read_reg(dd->idlest_reg) & idlest_mask) != state) &&
+               i < MAX_DPLL_WAIT_TRIES) {
+                i++;
+                udelay(1);
+        }
+
+        if (i == MAX_DPLL_WAIT_TRIES) {
+                printk(KERN_ERR "clock: %s failed transition to '%s'\n",
+                       clk->name, (state) ? "locked" : "bypassed");
+        } else {
+                pr_debug("clock: %s transition to '%s' in %d loops\n",
+                         clk->name, (state) ? "locked" : "bypassed", i);
+
+                ret = 0;
+        }
+
+        return ret;
+}
+
+/* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
+
+/*
+ * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
+ * @clk: pointer to a DPLL struct clk
+ *
+ * Instructs a non-CORE DPLL to lock.  Waits for the DPLL to report
+ * readiness before returning.  Will save and restore the DPLL's
+ * autoidle state across the enable, per the CDP code.  If the DPLL
+ * locked successfully, return 0; if the DPLL did not lock in the time
+ * allotted, or DPLL3 was passed in, return -EINVAL.
+ */
+static int _omap3_noncore_dpll_lock(struct clk *clk)
+{
+        u8 ai;
+        int r;
+
+        if (clk == &dpll3_ck)
+                return -EINVAL;
+
+        pr_debug("clock: locking DPLL %s\n", clk->name);
+
+        ai = omap3_dpll_autoidle_read(clk);
+
+        _omap3_dpll_write_clken(clk, DPLL_LOCKED);
+
+        if (ai) {
+                /*
+                 * If no downstream clocks are enabled, CM_IDLEST bit
+                 * may never become active, so don't wait for DPLL to lock.
+                 */
+                r = 0;
+                omap3_dpll_allow_idle(clk);
+        } else {
+                r = _omap3_wait_dpll_status(clk, 1);
+                omap3_dpll_deny_idle(clk);
+        };
+
+        return r;
+}
+
+/*
+ * omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
+ * @clk: pointer to a DPLL struct clk
+ *
+ * Instructs a non-CORE DPLL to enter low-power bypass mode.  In
+ * bypass mode, the DPLL's rate is set equal to its parent clock's
+ * rate.  Waits for the DPLL to report readiness before returning.
+ * Will save and restore the DPLL's autoidle state across the enable,
+ * per the CDP code.  If the DPLL entered bypass mode successfully,
+ * return 0; if the DPLL did not enter bypass in the time allotted, or
+ * DPLL3 was passed in, or the DPLL does not support low-power bypass,
+ * return -EINVAL.
+ */
+static int _omap3_noncore_dpll_bypass(struct clk *clk)
+{
+        int r;
+        u8 ai;
+
+        if (clk == &dpll3_ck)
+                return -EINVAL;
+
+        if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS)))
+                return -EINVAL;
+
+        pr_debug("clock: configuring DPLL %s for low-power bypass\n",
+                 clk->name);
+
+        ai = omap3_dpll_autoidle_read(clk);
+
+        _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS);
+
+        r = _omap3_wait_dpll_status(clk, 0);
+
+        if (ai)
+                omap3_dpll_allow_idle(clk);
+        else
+                omap3_dpll_deny_idle(clk);
+
+        return r;
+}
+
+/*
+ * _omap3_noncore_dpll_stop - instruct a DPLL to stop
+ * @clk: pointer to a DPLL struct clk
+ *
+ * Instructs a non-CORE DPLL to enter low-power stop. Will save and
+ * restore the DPLL's autoidle state across the stop, per the CDP
+ * code.  If DPLL3 was passed in, or the DPLL does not support
+ * low-power stop, return -EINVAL; otherwise, return 0.
+ */
+static int _omap3_noncore_dpll_stop(struct clk *clk)
+{
+        u8 ai;
+
+        if (clk == &dpll3_ck)
+                return -EINVAL;
+
+        if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
+                return -EINVAL;
+
+        pr_debug("clock: stopping DPLL %s\n", clk->name);
+
+        ai = omap3_dpll_autoidle_read(clk);
+
+        _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP);
+
+        if (ai)
+                omap3_dpll_allow_idle(clk);
+        else
+                omap3_dpll_deny_idle(clk);
+
+        return 0;
+}
+
+/**
+ * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
+ * @clk: pointer to a DPLL struct clk
+ *
+ * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
+ * The choice of modes depends on the DPLL's programmed rate: if it is
+ * the same as the DPLL's parent clock, it will enter bypass;
+ * otherwise, it will enter lock.  This code will wait for the DPLL to
+ * indicate readiness before returning, unless the DPLL takes too long
+ * to enter the target state.  Intended to be used as the struct clk's
+ * enable function.  If DPLL3 was passed in, or the DPLL does not
+ * support low-power stop, or if the DPLL took too long to enter
+ * bypass or lock, return -EINVAL; otherwise, return 0.
+ */
+static int omap3_noncore_dpll_enable(struct clk *clk)
+{
+        int r;
+
+        if (clk == &dpll3_ck)
+                return -EINVAL;
+
+        if (clk->parent->rate == clk_get_rate(clk))
+                r = _omap3_noncore_dpll_bypass(clk);
+        else
+                r = _omap3_noncore_dpll_lock(clk);
+
+        return r;
+}
+
+/**
+ * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
+ * @clk: pointer to a DPLL struct clk
+ *
+ * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
+ * The choice of modes depends on the DPLL's programmed rate: if it is
+ * the same as the DPLL's parent clock, it will enter bypass;
+ * otherwise, it will enter lock.  This code will wait for the DPLL to
+ * indicate readiness before returning, unless the DPLL takes too long
+ * to enter the target state.  Intended to be used as the struct clk's
+ * enable function.  If DPLL3 was passed in, or the DPLL does not
+ * support low-power stop, or if the DPLL took too long to enter
+ * bypass or lock, return -EINVAL; otherwise, return 0.
+ */
+static void omap3_noncore_dpll_disable(struct clk *clk)
+{
+        if (clk == &dpll3_ck)
+                return;
+
+        _omap3_noncore_dpll_stop(clk);
+}
+
+/**
+ * omap3_dpll_autoidle_read - read a DPLL's autoidle bits
+ * @clk: struct clk * of the DPLL to read
+ *
+ * Return the DPLL's autoidle bits, shifted down to bit 0.  Returns
+ * -EINVAL if passed a null pointer or if the struct clk does not
+ * appear to refer to a DPLL.
+ */
+static u32 omap3_dpll_autoidle_read(struct clk *clk)
+{
+        const struct dpll_data *dd;
+        u32 v;
+
+        if (!clk || !clk->dpll_data)
+                return -EINVAL;
+
+        dd = clk->dpll_data;
+
+        v = cm_read_reg(dd->autoidle_reg);
+        v &= dd->autoidle_mask;
+        v >>= __ffs(dd->autoidle_mask);
+
+        return v;
+}
+
+/**
+ * omap3_dpll_allow_idle - enable DPLL autoidle bits
+ * @clk: struct clk * of the DPLL to operate on
+ *
+ * Enable DPLL automatic idle control.  This automatic idle mode
+ * switching takes effect only when the DPLL is locked, at least on
+ * OMAP3430.  The DPLL will enter low-power stop when its downstream
+ * clocks are gated.  No return value.
+ */
+static void omap3_dpll_allow_idle(struct clk *clk)
+{
+        const struct dpll_data *dd;
+
+        if (!clk || !clk->dpll_data)
+                return;
+
+        dd = clk->dpll_data;
+
+        /*
+         * REVISIT: CORE DPLL can optionally enter low-power bypass
+         * by writing 0x5 instead of 0x1.  Add some mechanism to
+         * optionally enter this mode.
+         */
+        cm_rmw_reg_bits(dd->autoidle_mask,
+                        DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask),
+                        dd->autoidle_reg);
+}
+
+/**
+ * omap3_dpll_deny_idle - prevent DPLL from automatically idling
+ * @clk: struct clk * of the DPLL to operate on
+ *
+ * Disable DPLL automatic idle control.  No return value.
+ */
+static void omap3_dpll_deny_idle(struct clk *clk)
+{
+        const struct dpll_data *dd;
+
+        if (!clk || !clk->dpll_data)
+                return;
+
+        dd = clk->dpll_data;
+
+        cm_rmw_reg_bits(dd->autoidle_mask,
+                        DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask),
+                        dd->autoidle_reg);
+}
+
+/* Clock control for DPLL outputs */
+
 /**
  * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
  * @clk: DPLL output struct clk
@@ -89,6 +378,8 @@ static void omap3_clkoutx2_recalc(struct clk *clk)
                 propagate_rate(clk);
 }
 
+/* Common clock code */
+
 /*
  * As it is structured now, this will prevent an OMAP2/3 multiboot
  * kernel from compiling.  This will need further attention.
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index c9c5972a2e25..05757eb032bc 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -1,14 +1,19 @@
 /*
  * OMAP3 clock framework
  *
- * Virtual clocks are introduced as a convenient tools.
- * They are sources for other clocks and not supposed
- * to be requested from drivers directly.
- *
  * Copyright (C) 2007-2008 Texas Instruments, Inc.
  * Copyright (C) 2007-2008 Nokia Corporation
  *
  * Written by Paul Walmsley
+ * With many device clock fixes by Kevin Hilman and Jouni Högander
+ * DPLL bypass clock support added by Roman Tereshonkov
+ *
+ */
+
+/*
+ * Virtual clocks are introduced as convenient tools.
+ * They are sources for other clocks and not supposed
+ * to be requested from drivers directly.
  */
 
 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
@@ -24,6 +29,15 @@
 
 static void omap3_dpll_recalc(struct clk *clk);
 static void omap3_clkoutx2_recalc(struct clk *clk);
+static void omap3_dpll_allow_idle(struct clk *clk);
+static void omap3_dpll_deny_idle(struct clk *clk);
+static u32 omap3_dpll_autoidle_read(struct clk *clk);
+static int omap3_noncore_dpll_enable(struct clk *clk);
+static void omap3_noncore_dpll_disable(struct clk *clk);
+
+/* Maximum DPLL multiplier, divider values for OMAP3 */
+#define OMAP3_MAX_DPLL_MULT             2048
+#define OMAP3_MAX_DPLL_DIV              128
 
 /*
  * DPLL1 supplies clock to the MPU.
@@ -33,6 +47,11 @@ static void omap3_clkoutx2_recalc(struct clk *clk);
  * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
  */
 
+/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
+#define DPLL_LOW_POWER_STOP             0x1
+#define DPLL_LOW_POWER_BYPASS           0x5
+#define DPLL_LOCKED                     0x7
+
 /* PRM CLOCKS */
 
 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
@@ -240,15 +259,23 @@ static const struct clksel_rate div16_dpll_rates[] = {
 /* DPLL1 */
 /* MPU clock source */
 /* Type: DPLL */
-static const struct dpll_data dpll1_dd = {
+static struct dpll_data dpll1_dd = {
         .mult_div1_reg  = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
         .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
         .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
         .control_reg    = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
         .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
+        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
         .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
         .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
         .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
+        .autoidle_reg   = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
+        .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
+        .idlest_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
+        .idlest_bit     = OMAP3430_ST_MPU_CLK_SHIFT,
+        .max_multiplier = OMAP3_MAX_DPLL_MULT,
+        .max_divider    = OMAP3_MAX_DPLL_DIV,
+        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 };
 
 static struct clk dpll1_ck = {
@@ -256,6 +283,7 @@ static struct clk dpll1_ck = {
         .parent         = &sys_ck,
         .dpll_data      = &dpll1_dd,
         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+        .round_rate     = &omap2_dpll_round_rate,
         .recalc         = &omap3_dpll_recalc,
 };
 
@@ -297,22 +325,34 @@ static struct clk dpll1_x2m2_ck = {
 /* IVA2 clock source */
 /* Type: DPLL */
 
-static const struct dpll_data dpll2_dd = {
+static struct dpll_data dpll2_dd = {
         .mult_div1_reg  = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
         .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
         .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
         .control_reg    = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
         .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
+        .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
+                                (1 << DPLL_LOW_POWER_BYPASS),
         .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
         .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
         .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
+        .autoidle_reg   = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
+        .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
+        .idlest_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
+        .idlest_bit     = OMAP3430_ST_IVA2_CLK_SHIFT,
+        .max_multiplier = OMAP3_MAX_DPLL_MULT,
+        .max_divider    = OMAP3_MAX_DPLL_DIV,
+        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 };
 
 static struct clk dpll2_ck = {
         .name           = "dpll2_ck",
         .parent         = &sys_ck,
         .dpll_data      = &dpll2_dd,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+        .enable         = &omap3_noncore_dpll_enable,
+        .disable        = &omap3_noncore_dpll_disable,
+        .round_rate     = &omap2_dpll_round_rate,
         .recalc         = &omap3_dpll_recalc,
 };
 
@@ -338,10 +378,12 @@ static struct clk dpll2_m2_ck = {
         .recalc         = &omap2_clksel_recalc,
 };
 
-/* DPLL3 */
-/* Source clock for all interfaces and for some device fclks */
-/* Type: DPLL */
-static const struct dpll_data dpll3_dd = {
+/*
+ * DPLL3
+ * Source clock for all interfaces and for some device fclks
+ * REVISIT: Also supports fast relock bypass - not included below
+ */
+static struct dpll_data dpll3_dd = {
         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
         .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
         .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
@@ -350,6 +392,11 @@ static const struct dpll_data dpll3_dd = {
         .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
         .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
         .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
+        .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
+        .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
+        .max_multiplier = OMAP3_MAX_DPLL_MULT,
+        .max_divider    = OMAP3_MAX_DPLL_DIV,
+        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 };
 
 static struct clk dpll3_ck = {
@@ -357,6 +404,7 @@ static struct clk dpll3_ck = {
         .parent         = &sys_ck,
         .dpll_data      = &dpll3_dd,
         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+        .round_rate     = &omap2_dpll_round_rate,
         .recalc         = &omap3_dpll_recalc,
 };
 
@@ -439,7 +487,7 @@ static struct clk core_ck = {
         .name           = "core_ck",
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
-        .clksel_mask    = OMAP3430_ST_CORE_CLK,
+        .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
         .clksel         = core_ck_clksel,
         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
                                 PARENT_CONTROLS_CLOCK,
@@ -456,7 +504,7 @@ static struct clk dpll3_m2x2_ck = {
         .name           = "dpll3_m2x2_ck",
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
-        .clksel_mask    = OMAP3430_ST_CORE_CLK,
+        .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
         .clksel         = dpll3_m2x2_ck_clksel,
         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
                                 PARENT_CONTROLS_CLOCK,
@@ -503,7 +551,7 @@ static struct clk emu_core_alwon_ck = {
         .parent         = &dpll3_m3x2_ck,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
-        .clksel_mask    = OMAP3430_ST_CORE_CLK,
+        .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
         .clksel         = emu_core_alwon_ck_clksel,
         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
                                 PARENT_CONTROLS_CLOCK,
@@ -513,22 +561,33 @@ static struct clk emu_core_alwon_ck = {
 /* DPLL4 */
 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 /* Type: DPLL */
-static const struct dpll_data dpll4_dd = {
+static struct dpll_data dpll4_dd = {
         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
         .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
+        .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
+        .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
+        .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
+        .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
+        .idlest_bit     = OMAP3430_ST_PERIPH_CLK_SHIFT,
+        .max_multiplier = OMAP3_MAX_DPLL_MULT,
+        .max_divider    = OMAP3_MAX_DPLL_DIV,
+        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 };
 
 static struct clk dpll4_ck = {
         .name           = "dpll4_ck",
         .parent         = &sys_ck,
         .dpll_data      = &dpll4_dd,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+        .enable         = &omap3_noncore_dpll_enable,
+        .disable        = &omap3_noncore_dpll_disable,
+        .round_rate     = &omap2_dpll_round_rate,
         .recalc         = &omap3_dpll_recalc,
 };
 
@@ -584,7 +643,7 @@ static struct clk omap_96m_alwon_fck = {
         .parent         = &dpll4_m2x2_ck,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
-        .clksel_mask    = OMAP3430_ST_PERIPH_CLK,
+        .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
         .clksel         = omap_96m_alwon_fck_clksel,
         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
                                  PARENT_CONTROLS_CLOCK,
@@ -610,7 +669,7 @@ static struct clk cm_96m_fck = {
         .parent         = &dpll4_m2x2_ck,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
-        .clksel_mask    = OMAP3430_ST_PERIPH_CLK,
+        .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
         .clksel         = cm_96m_fck_clksel,
         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
                                 PARENT_CONTROLS_CLOCK,
@@ -652,7 +711,7 @@ static struct clk virt_omap_54m_fck = {
         .parent         = &dpll4_m3x2_ck,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
-        .clksel_mask    = OMAP3430_ST_PERIPH_CLK,
+        .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
         .clksel         = virt_omap_54m_fck_clksel,
         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
                                 PARENT_CONTROLS_CLOCK,
@@ -804,23 +863,33 @@ static struct clk emu_per_alwon_ck = {
 /* Supplies 120MHz clock, USIM source clock */
 /* Type: DPLL */
 /* 3430ES2 only */
-static const struct dpll_data dpll5_dd = {
+static struct dpll_data dpll5_dd = {
         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
         .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
         .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
         .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
+        .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
         .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
         .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
         .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
+        .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
+        .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
+        .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
+        .idlest_bit     = OMAP3430ES2_ST_PERIPH2_CLK_SHIFT,
+        .max_multiplier = OMAP3_MAX_DPLL_MULT,
+        .max_divider    = OMAP3_MAX_DPLL_DIV,
+        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 };
 
 static struct clk dpll5_ck = {
         .name           = "dpll5_ck",
         .parent         = &sys_ck,
         .dpll_data      = &dpll5_dd,
-        .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
-                                ALWAYS_ENABLED,
+        .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
+        .enable         = &omap3_noncore_dpll_enable,
+        .disable        = &omap3_noncore_dpll_disable,
+        .round_rate     = &omap2_dpll_round_rate,
         .recalc         = &omap3_dpll_recalc,
 };
 
@@ -1365,7 +1434,8 @@ static const struct clksel mcbsp_15_clksel[] = {
 };
 
 static struct clk mcbsp5_fck = {
-        .name           = "mcbsp5_fck",
+        .name           = "mcbsp_fck",
+        .id             = 5,
         .init           = &omap2_init_clksel_parent,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
@@ -1377,7 +1447,8 @@ static struct clk mcbsp5_fck = {
 };
 
 static struct clk mcbsp1_fck = {
-        .name           = "mcbsp1_fck",
+        .name           = "mcbsp_fck",
+        .id             = 1,
         .init           = &omap2_init_clksel_parent,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
@@ -1789,7 +1860,8 @@ static struct clk gpt10_ick = {
 };
 
 static struct clk mcbsp5_ick = {
-        .name           = "mcbsp5_ick",
+        .name           = "mcbsp_ick",
+        .id             = 5,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
@@ -1798,7 +1870,8 @@ static struct clk mcbsp5_ick = {
 };
 
 static struct clk mcbsp1_ick = {
-        .name           = "mcbsp1_ick",
+        .name           = "mcbsp_ick",
+        .id             = 1,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
@@ -1935,7 +2008,7 @@ static struct clk dss1_alwon_fck = {
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
-        .clksel_mask    = OMAP3430_ST_PERIPH_CLK,
+        .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
         .clksel         = dss1_alwon_fck_clksel,
         .flags          = CLOCK_IN_OMAP343X,
         .recalc         = &omap2_clksel_recalc,
@@ -1991,7 +2064,7 @@ static struct clk cam_mclk = {
         .parent         = &dpll4_m5x2_ck,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
-        .clksel_mask    = OMAP3430_ST_PERIPH_CLK,
+        .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
         .clksel         = cam_mclk_clksel,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
@@ -2541,7 +2614,8 @@ static struct clk gpt2_ick = {
 };
 
 static struct clk mcbsp2_ick = {
-        .name           = "mcbsp2_ick",
+        .name           = "mcbsp_ick",
+        .id             = 2,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
@@ -2550,7 +2624,8 @@ static struct clk mcbsp2_ick = {
 };
 
 static struct clk mcbsp3_ick = {
-        .name           = "mcbsp3_ick",
+        .name           = "mcbsp_ick",
+        .id             = 3,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
@@ -2559,7 +2634,8 @@ static struct clk mcbsp3_ick = {
 };
 
 static struct clk mcbsp4_ick = {
-        .name           = "mcbsp4_ick",
+        .name           = "mcbsp_ick",
+        .id             = 4,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
@@ -2574,7 +2650,8 @@ static const struct clksel mcbsp_234_clksel[] = {
 };
 
 static struct clk mcbsp2_fck = {
-        .name           = "mcbsp2_fck",
+        .name           = "mcbsp_fck",
+        .id             = 2,
         .init           = &omap2_init_clksel_parent,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
@@ -2586,7 +2663,8 @@ static struct clk mcbsp2_fck = {
 };
 
 static struct clk mcbsp3_fck = {
-        .name           = "mcbsp3_fck",
+        .name           = "mcbsp_fck",
+        .id             = 3,
         .init           = &omap2_init_clksel_parent,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
@@ -2598,7 +2676,8 @@ static struct clk mcbsp3_fck = {
 };
 
 static struct clk mcbsp4_fck = {
-        .name           = "mcbsp4_fck",
+        .name           = "mcbsp_fck",
+        .id             = 4,
         .init           = &omap2_init_clksel_parent,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index 3c38395f6442..ee4c0ca1a708 100644
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -72,7 +72,8 @@
 #define OMAP3430_ST_IVA2                                (1 << 0)
 
 /* CM_IDLEST_PLL_IVA2 */
-#define OMAP3430_ST_IVA2_CLK                            (1 << 0)
+#define OMAP3430_ST_IVA2_CLK_SHIFT                      0
+#define OMAP3430_ST_IVA2_CLK_MASK                       (1 << 0)
 
 /* CM_AUTOIDLE_PLL_IVA2 */
 #define OMAP3430_AUTO_IVA2_DPLL_SHIFT                   0
@@ -115,10 +116,7 @@
 #define OMAP3430_ST_MPU                                 (1 << 0)
 
 /* CM_IDLEST_PLL_MPU */
-#define OMAP3430_ST_MPU_CLK                             (1 << 0)
-#define OMAP3430_ST_IVA2_CLK_MASK                       (1 << 0)
-
-/* CM_IDLEST_PLL_MPU */
+#define OMAP3430_ST_MPU_CLK_SHIFT                       0
 #define OMAP3430_ST_MPU_CLK_MASK                        (1 << 0)
 
 /* CM_AUTOIDLE_PLL_MPU */
@@ -408,8 +406,10 @@
 #define OMAP3430_ST_12M_CLK                             (1 << 4)
 #define OMAP3430_ST_48M_CLK                             (1 << 3)
 #define OMAP3430_ST_96M_CLK                             (1 << 2)
-#define OMAP3430_ST_PERIPH_CLK                          (1 << 1)
-#define OMAP3430_ST_CORE_CLK                            (1 << 0)
+#define OMAP3430_ST_PERIPH_CLK_SHIFT                    1
+#define OMAP3430_ST_PERIPH_CLK_MASK                     (1 << 1)
+#define OMAP3430_ST_CORE_CLK_SHIFT                      0
+#define OMAP3430_ST_CORE_CLK_MASK                       (1 << 0)
 
 /* CM_IDLEST2_CKGEN */
 #define OMAP3430ES2_ST_120M_CLK_SHIFT                   1
@@ -423,6 +423,10 @@
 #define OMAP3430_AUTO_CORE_DPLL_SHIFT                   0
 #define OMAP3430_AUTO_CORE_DPLL_MASK                    (0x7 << 0)
 
+/* CM_AUTOIDLE2_PLL */
+#define OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT             0
+#define OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK              (0x7 << 0)
+
 /* CM_CLKSEL1_PLL */
 /* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */
 #define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT             27
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h
index 8489f3029fed..87a44c715aa4 100644
--- a/arch/arm/mach-omap2/cm.h
+++ b/arch/arm/mach-omap2/cm.h
@@ -81,6 +81,7 @@
 #define OMAP3430ES2_CM_FCLKEN3                          0x0008
 #define OMAP3430_CM_IDLEST_PLL                          CM_IDLEST2
 #define OMAP3430_CM_AUTOIDLE_PLL                        CM_AUTOIDLE2
+#define OMAP3430ES2_CM_AUTOIDLE2_PLL                    CM_AUTOIDLE2
 #define OMAP3430_CM_CLKSEL1                             CM_CLKSEL
 #define OMAP3430_CM_CLKSEL1_PLL                         CM_CLKSEL
 #define OMAP3430_CM_CLKSEL2_PLL                         CM_CLKSEL2
@@ -96,15 +97,21 @@
 /* Clock management domain register get/set */
 
 #ifndef __ASSEMBLER__
-static inline void cm_write_mod_reg(u32 val, s16 module, s16 idx)
+
+extern u32 cm_read_mod_reg(s16 module, u16 idx);
+extern void cm_write_mod_reg(u32 val, s16 module, u16 idx);
+extern u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
+
+static inline u32 cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
 {
-        __raw_writel(val, OMAP_CM_REGADDR(module, idx));
+        return cm_rmw_mod_reg_bits(bits, bits, module, idx);
 }
 
-static inline u32 cm_read_mod_reg(s16 module, s16 idx)
+static inline u32 cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
 {
-        return __raw_readl(OMAP_CM_REGADDR(module, idx));
+        return cm_rmw_mod_reg_bits(bits, 0x0, module, idx);
 }
+
 #endif
 
 /* CM register bits shared between 24XX and 3430 */
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index a5d86a49c213..51f70300996f 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -13,22 +13,21 @@
 #undef DEBUG
 
 #include <linux/kernel.h>
+#include <linux/io.h>
 
-#include <asm/io.h>
-
+#include <asm/arch/common.h>
 #include <asm/arch/control.h>
 
-static u32 omap2_ctrl_base;
+static void __iomem *omap2_ctrl_base;
 
-#define OMAP_CTRL_REGADDR(reg)  (void __iomem *)IO_ADDRESS(omap2_ctrl_base \
-                                                                + (reg))
+#define OMAP_CTRL_REGADDR(reg)          (omap2_ctrl_base + (reg))
 
-void omap_ctrl_base_set(u32 base)
+void __init omap2_set_globals_control(struct omap_globals *omap2_globals)
 {
-        omap2_ctrl_base = base;
+        omap2_ctrl_base = omap2_globals->ctrl;
 }
 
-u32 omap_ctrl_base_get(void)
+void __iomem *omap_ctrl_base_get(void)
 {
         return omap2_ctrl_base;
 }
@@ -50,25 +49,16 @@ u32 omap_ctrl_readl(u16 offset)
 
 void omap_ctrl_writeb(u8 val, u16 offset)
 {
-        pr_debug("omap_ctrl_writeb: writing 0x%0x to 0x%0x\n", val,
-                 (u32)OMAP_CTRL_REGADDR(offset));
-
         __raw_writeb(val, OMAP_CTRL_REGADDR(offset));
 }
 
 void omap_ctrl_writew(u16 val, u16 offset)
 {
-        pr_debug("omap_ctrl_writew: writing 0x%0x to 0x%0x\n", val,
-                 (u32)OMAP_CTRL_REGADDR(offset));
-
         __raw_writew(val, OMAP_CTRL_REGADDR(offset));
 }
 
 void omap_ctrl_writel(u32 val, u16 offset)
 {
-        pr_debug("omap_ctrl_writel: writing 0x%0x to 0x%0x\n", val,
-                 (u32)OMAP_CTRL_REGADDR(offset));
-
         __raw_writel(val, OMAP_CTRL_REGADDR(offset));
 }
 
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 4dfd878d7968..dff4b16cead6 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -17,16 +17,23 @@
 
 #include <asm/io.h>
 
-#if defined(CONFIG_ARCH_OMAP2420)
-#define OMAP24XX_TAP_BASE       io_p2v(0x48014000)
-#endif
+#include <asm/arch/control.h>
+#include <asm/arch/cpu.h>
 
-#if defined(CONFIG_ARCH_OMAP2430)
-#define OMAP24XX_TAP_BASE       io_p2v(0x4900A000)
+#if defined(CONFIG_ARCH_OMAP2420)
+#define TAP_BASE        io_p2v(0x48014000)
+#elif defined(CONFIG_ARCH_OMAP2430)
+#define TAP_BASE        io_p2v(0x4900A000)
+#elif defined(CONFIG_ARCH_OMAP34XX)
+#define TAP_BASE        io_p2v(0x4830A000)
 #endif
 
 #define OMAP_TAP_IDCODE         0x0204
+#if defined(CONFIG_ARCH_OMAP34XX)
+#define OMAP_TAP_PROD_ID        0x0210
+#else
 #define OMAP_TAP_PROD_ID        0x0208
+#endif
 
 #define OMAP_TAP_DIE_ID_0       0x0218
 #define OMAP_TAP_DIE_ID_1       0x021C
@@ -56,9 +63,134 @@ static struct omap_id omap_ids[] __initdata = {
         { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300000 },
 };
 
+static struct omap_chip_id omap_chip;
+
+/**
+ * omap_chip_is - test whether currently running OMAP matches a chip type
+ * @oc: omap_chip_t to test against
+ *
+ * Test whether the currently-running OMAP chip matches the supplied
+ * chip type 'oc'.  Returns 1 upon a match; 0 upon failure.
+ */
+int omap_chip_is(struct omap_chip_id oci)
+{
+        return (oci.oc & omap_chip.oc) ? 1 : 0;
+}
+EXPORT_SYMBOL(omap_chip_is);
+
 static u32 __init read_tap_reg(int reg)
 {
-        return __raw_readl(OMAP24XX_TAP_BASE + reg);
+        unsigned int regval = 0;
+        u32 cpuid;
+
+        /* Reading the IDCODE register on 3430 ES1 results in a
+         * data abort as the register is not exposed on the OCP
+         * Hence reading the Cortex Rev
+         */
+        cpuid = read_cpuid(CPUID_ID);
+
+        /* If the processor type is Cortex-A8 and the revision is 0x0
+         * it means its Cortex r0p0 which is 3430 ES1
+         */
+        if ((((cpuid >> 4) & 0xFFF) == 0xC08) && ((cpuid & 0xF) == 0x0)) {
+                switch (reg) {
+                case OMAP_TAP_IDCODE  : regval = 0x0B7AE02F; break;
+                /* Making DevType as 0xF in ES1 to differ from ES2 */
+                case OMAP_TAP_PROD_ID : regval = 0x000F00F0; break;
+                case OMAP_TAP_DIE_ID_0: regval = 0x01000000; break;
+                case OMAP_TAP_DIE_ID_1: regval = 0x1012d687; break;
+                case OMAP_TAP_DIE_ID_2: regval = 0x00000000; break;
+                case OMAP_TAP_DIE_ID_3: regval = 0x2d2c0000; break;
+                }
+        } else
+                regval = __raw_readl(TAP_BASE + reg);
+
+        return regval;
+
+}
+
+/*
+ * _set_system_rev - set the system_rev global based on current OMAP chip type
+ *
+ * Set the system_rev global.  This is primarily used by the cpu_is_omapxxxx()
+ * macros.
+ */
+static void __init _set_system_rev(u32 type, u8 rev)
+{
+        u32 i, ctrl_status;
+
+        /*
+         * system_rev encoding is as follows
+         * system_rev & 0xff000000 -> Omap Class (24xx/34xx)
+         * system_rev & 0xfff00000 -> Omap Sub Class (242x/343x)
+         * system_rev & 0xffff0000 -> Omap type (2420/2422/2423/2430/3430)
+         * system_rev & 0x0000f000 -> Silicon revision (ES1, ES2 )
+         * system_rev & 0x00000700 -> Device Type ( EMU/HS/GP/BAD )
+         * system_rev & 0x000000c0 -> IDCODE revision[6:7]
+         * system_rev & 0x0000003f -> sys_boot[0:5]
+         */
+        /* Embedding the ES revision info in type field */
+        system_rev = type;
+        /* Also add IDCODE revision info only two lower bits */
+        system_rev |= ((rev & 0x3) << 6);
+
+        /* Add in the device type and sys_boot fields (see above) */
+        if (cpu_is_omap24xx()) {
+                i = OMAP24XX_CONTROL_STATUS;
+        } else if (cpu_is_omap343x()) {
+                i = OMAP343X_CONTROL_STATUS;
+        } else {
+                printk(KERN_ERR "id: unknown CPU type\n");
+                BUG();
+        }
+        ctrl_status = omap_ctrl_readl(i);
+        system_rev |= (ctrl_status & (OMAP2_SYSBOOT_5_MASK |
+                                      OMAP2_SYSBOOT_4_MASK |
+                                      OMAP2_SYSBOOT_3_MASK |
+                                      OMAP2_SYSBOOT_2_MASK |
+                                      OMAP2_SYSBOOT_1_MASK |
+                                      OMAP2_SYSBOOT_0_MASK));
+        system_rev |= (ctrl_status & OMAP2_DEVICETYPE_MASK);
+}
+
+
+/*
+ * _set_omap_chip - set the omap_chip global based on OMAP chip type
+ *
+ * Build the omap_chip bits.  This variable is used by powerdomain and
+ * clockdomain code to indicate whether structures are applicable for
+ * the current OMAP chip type by ANDing it against a 'platform' bitfield
+ * in the structure.
+ */
+static void __init _set_omap_chip(void)
+{
+        if (cpu_is_omap343x()) {
+
+                omap_chip.oc = CHIP_IS_OMAP3430;
+                if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0))
+                        omap_chip.oc |= CHIP_IS_OMAP3430ES1;
+                else if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0))
+                        omap_chip.oc |= CHIP_IS_OMAP3430ES2;
+
+        } else if (cpu_is_omap243x()) {
+
+                /* Currently only supports 2430ES2.1 and 2430-all */
+                omap_chip.oc |= CHIP_IS_OMAP2430;
+
+        } else if (cpu_is_omap242x()) {
+
+                /* Currently only supports 2420ES2.1.1 and 2420-all */
+                omap_chip.oc |= CHIP_IS_OMAP2420;
+
+        } else {
+
+                /* Current CPU not supported by this code. */
+                printk(KERN_WARNING "OMAP chip type code does not yet support "
+                       "this CPU type.\n");
+                WARN_ON(1);
+
+        }
+
 }
 
 void __init omap2_check_revision(void)
@@ -76,21 +208,31 @@ void __init omap2_check_revision(void)
         rev = (idcode >> 28) & 0x0f;
         dev_type = (prod_id >> 16) & 0x0f;
 
-#ifdef DEBUG
-        printk(KERN_DEBUG "OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
-                idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
-        printk(KERN_DEBUG "OMAP_TAP_DIE_ID_0: 0x%08x\n",
-                read_tap_reg(OMAP_TAP_DIE_ID_0));
-        printk(KERN_DEBUG "OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
-                read_tap_reg(OMAP_TAP_DIE_ID_1),
-               (read_tap_reg(OMAP_TAP_DIE_ID_1) >> 28) & 0xf);
-        printk(KERN_DEBUG "OMAP_TAP_DIE_ID_2: 0x%08x\n",
-                read_tap_reg(OMAP_TAP_DIE_ID_2));
-        printk(KERN_DEBUG "OMAP_TAP_DIE_ID_3: 0x%08x\n",
-                read_tap_reg(OMAP_TAP_DIE_ID_3));
-        printk(KERN_DEBUG "OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
-                prod_id, dev_type);
-#endif
+        pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
+                 idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
+        pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n",
+                 read_tap_reg(OMAP_TAP_DIE_ID_0));
+        pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
+                 read_tap_reg(OMAP_TAP_DIE_ID_1),
+                 (read_tap_reg(OMAP_TAP_DIE_ID_1) >> 28) & 0xf);
+        pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n",
+                 read_tap_reg(OMAP_TAP_DIE_ID_2));
+        pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n",
+                 read_tap_reg(OMAP_TAP_DIE_ID_3));
+        pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
+                 prod_id, dev_type);
+
+        /*
+         * Detection for 34xx ES2.0 and above can be done with just
+         * hawkeye and rev. See TRM 1.5.2 Device Identification.
+         * Note that rev cannot be used directly as ES1.0 uses value 0.
+         */
+        if (hawkeye == 0xb7ae) {
+                system_rev = 0x34300000 | ((1 + rev) << 12);
+                pr_info("OMAP%04x ES2.%i\n", system_rev >> 16, rev);
+                _set_omap_chip();
+                return;
+        }
 
         /* Check hawkeye ids */
         for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
@@ -114,16 +256,15 @@ void __init omap2_check_revision(void)
                                 omap_ids[i].type >> 16);
                 j = i;
         }
-        system_rev = omap_ids[j].type;
 
-        system_rev |= rev << 8;
+        _set_system_rev(omap_ids[j].type, rev);
 
-        /* Add the cpu class info (24xx) */
-        system_rev |= 0x24;
+        _set_omap_chip();
 
         pr_info("OMAP%04x", system_rev >> 16);
         if ((system_rev >> 8) & 0x0f)
-                printk("%x", (system_rev >> 8) & 0x0f);
-        printk("\n");
+                pr_info("ES%x", (system_rev >> 12) & 0xf);
+        pr_info("\n");
+
 }
 
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
new file mode 100644
index 000000000000..17cf199d1130
--- /dev/null
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -0,0 +1,208 @@
+/*
+ * linux/arch/arm/mach-omap2/mcbsp.c
+ *
+ * Copyright (C) 2008 Instituto Nokia de Tecnologia
+ * Contact: Eduardo Valentin <eduardo.valentin@indt.org.br>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Multichannel mode not supported.
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+
+#include <asm/arch/dma.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/mcbsp.h>
+
+struct mcbsp_internal_clk {
+        struct clk clk;
+        struct clk **childs;
+        int n_childs;
+};
+
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+static void omap_mcbsp_clk_init(struct mcbsp_internal_clk *mclk)
+{
+        const char *clk_names[] = { "mcbsp_ick", "mcbsp_fck" };
+        int i;
+
+        mclk->n_childs = ARRAY_SIZE(clk_names);
+        mclk->childs = kzalloc(mclk->n_childs * sizeof(struct clk *),
+                                GFP_KERNEL);
+
+        for (i = 0; i < mclk->n_childs; i++) {
+                /* We fake a platform device to get correct device id */
+                struct platform_device pdev;
+
+                pdev.dev.bus = &platform_bus_type;
+                pdev.id = mclk->clk.id;
+                mclk->childs[i] = clk_get(&pdev.dev, clk_names[i]);
+                if (IS_ERR(mclk->childs[i]))
+                        printk(KERN_ERR "Could not get clock %s (%d).\n",
+                                clk_names[i], mclk->clk.id);
+        }
+}
+
+static int omap_mcbsp_clk_enable(struct clk *clk)
+{
+        struct mcbsp_internal_clk *mclk = container_of(clk,
+                                        struct mcbsp_internal_clk, clk);
+        int i;
+
+        for (i = 0; i < mclk->n_childs; i++)
+                clk_enable(mclk->childs[i]);
+        return 0;
+}
+
+static void omap_mcbsp_clk_disable(struct clk *clk)
+{
+        struct mcbsp_internal_clk *mclk = container_of(clk,
+                                        struct mcbsp_internal_clk, clk);
+        int i;
+
+        for (i = 0; i < mclk->n_childs; i++)
+                clk_disable(mclk->childs[i]);
+}
+
+static struct mcbsp_internal_clk omap_mcbsp_clks[] = {
+        {
+                .clk = {
+                        .name           = "mcbsp_clk",
+                        .id             = 1,
+                        .enable         = omap_mcbsp_clk_enable,
+                        .disable        = omap_mcbsp_clk_disable,
+                },
+        },
+        {
+                .clk = {
+                        .name           = "mcbsp_clk",
+                        .id             = 2,
+                        .enable         = omap_mcbsp_clk_enable,
+                        .disable        = omap_mcbsp_clk_disable,
+                },
+        },
+};
+
+#define omap_mcbsp_clks_size    ARRAY_SIZE(omap_mcbsp_clks)
+#else
+#define omap_mcbsp_clks_size    0
+static struct mcbsp_internal_clk __initdata *omap_mcbsp_clks;
+static inline void omap_mcbsp_clk_init(struct clk *clk)
+{ }
+#endif
+
+static void omap2_mcbsp2_mux_setup(void)
+{
+        omap_cfg_reg(Y15_24XX_MCBSP2_CLKX);
+        omap_cfg_reg(R14_24XX_MCBSP2_FSX);
+        omap_cfg_reg(W15_24XX_MCBSP2_DR);
+        omap_cfg_reg(V15_24XX_MCBSP2_DX);
+        omap_cfg_reg(V14_24XX_GPIO117);
+        /*
+         * TODO: Need to add MUX settings for OMAP 2430 SDP
+         */
+}
+
+static void omap2_mcbsp_request(unsigned int id)
+{
+        if (cpu_is_omap2420() && (id == OMAP_MCBSP2))
+                omap2_mcbsp2_mux_setup();
+}
+
+static int omap2_mcbsp_check(unsigned int id)
+{
+        if (id > OMAP_MAX_MCBSP_COUNT - 1) {
+                printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n", id + 1);
+                return -ENODEV;
+        }
+        return 0;
+}
+
+static struct omap_mcbsp_ops omap2_mcbsp_ops = {
+        .request        = omap2_mcbsp_request,
+        .check          = omap2_mcbsp_check,
+};
+
+#ifdef CONFIG_ARCH_OMAP24XX
+static struct omap_mcbsp_platform_data omap24xx_mcbsp_pdata[] = {
+        {
+                .virt_base      = IO_ADDRESS(OMAP24XX_MCBSP1_BASE),
+                .dma_rx_sync    = OMAP24XX_DMA_MCBSP1_RX,
+                .dma_tx_sync    = OMAP24XX_DMA_MCBSP1_TX,
+                .rx_irq         = INT_24XX_MCBSP1_IRQ_RX,
+                .tx_irq         = INT_24XX_MCBSP1_IRQ_TX,
+                .ops            = &omap2_mcbsp_ops,
+                .clk_name       = "mcbsp_clk",
+        },
+        {
+                .virt_base      = IO_ADDRESS(OMAP24XX_MCBSP2_BASE),
+                .dma_rx_sync    = OMAP24XX_DMA_MCBSP2_RX,
+                .dma_tx_sync    = OMAP24XX_DMA_MCBSP2_TX,
+                .rx_irq         = INT_24XX_MCBSP2_IRQ_RX,
+                .tx_irq         = INT_24XX_MCBSP2_IRQ_TX,
+                .ops            = &omap2_mcbsp_ops,
+                .clk_name       = "mcbsp_clk",
+        },
+};
+#define OMAP24XX_MCBSP_PDATA_SZ         ARRAY_SIZE(omap24xx_mcbsp_pdata)
+#else
+#define omap24xx_mcbsp_pdata            NULL
+#define OMAP24XX_MCBSP_PDATA_SZ         0
+#endif
+
+#ifdef CONFIG_ARCH_OMAP34XX
+static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
+        {
+                .virt_base      = IO_ADDRESS(OMAP34XX_MCBSP1_BASE),
+                .dma_rx_sync    = OMAP24XX_DMA_MCBSP1_RX,
+                .dma_tx_sync    = OMAP24XX_DMA_MCBSP1_TX,
+                .rx_irq         = INT_24XX_MCBSP1_IRQ_RX,
+                .tx_irq         = INT_24XX_MCBSP1_IRQ_TX,
+                .ops            = &omap2_mcbsp_ops,
+                .clk_name       = "mcbsp_clk",
+        },
+        {
+                .virt_base      = IO_ADDRESS(OMAP34XX_MCBSP2_BASE),
+                .dma_rx_sync    = OMAP24XX_DMA_MCBSP2_RX,
+                .dma_tx_sync    = OMAP24XX_DMA_MCBSP2_TX,
+                .rx_irq         = INT_24XX_MCBSP2_IRQ_RX,
+                .tx_irq         = INT_24XX_MCBSP2_IRQ_TX,
+                .ops            = &omap2_mcbsp_ops,
+                .clk_name       = "mcbsp_clk",
+        },
+};
+#define OMAP34XX_MCBSP_PDATA_SZ         ARRAY_SIZE(omap34xx_mcbsp_pdata)
+#else
+#define omap34xx_mcbsp_pdata            NULL
+#define OMAP34XX_MCBSP_PDATA_SZ         0
+#endif
+
+int __init omap2_mcbsp_init(void)
+{
+        int i;
+
+        for (i = 0; i < omap_mcbsp_clks_size; i++) {
+                /* Once we call clk_get inside init, we do not register it */
+                omap_mcbsp_clk_init(&omap_mcbsp_clks[i]);
+                clk_register(&omap_mcbsp_clks[i].clk);
+        }
+
+        if (cpu_is_omap24xx())
+                omap_mcbsp_register_board_cfg(omap24xx_mcbsp_pdata,
+                                                OMAP24XX_MCBSP_PDATA_SZ);
+
+        if (cpu_is_omap34xx())
+                omap_mcbsp_register_board_cfg(omap34xx_mcbsp_pdata,
+                                                OMAP34XX_MCBSP_PDATA_SZ);
+
+        return omap_mcbsp_init();
+}
+arch_initcall(omap2_mcbsp_init);
diff --git a/arch/arm/mach-omap2/memory.c b/arch/arm/mach-omap2/memory.c
index 12479081881a..73cadb2c75cf 100644
--- a/arch/arm/mach-omap2/memory.c
+++ b/arch/arm/mach-omap2/memory.c
@@ -24,6 +24,7 @@
 
 #include <asm/io.h>
 
+#include <asm/arch/common.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/sram.h>
 
@@ -32,8 +33,8 @@
 #include "memory.h"
 #include "sdrc.h"
 
-unsigned long omap2_sdrc_base;
-unsigned long omap2_sms_base;
+void __iomem *omap2_sdrc_base;
+void __iomem *omap2_sms_base;
 
 static struct memory_timings mem_timings;
 static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2;
@@ -154,6 +155,12 @@ void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
         mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8));
 }
 
+void __init omap2_set_globals_memory(struct omap_globals *omap2_globals)
+{
+        omap2_sdrc_base = omap2_globals->sdrc;
+        omap2_sms_base = omap2_globals->sms;
+}
+
 /* turn on smart idle modes for SDRAM scheduler and controller */
 void __init omap2_init_memory(void)
 {
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 930770012a75..8f98b20f30a1 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -236,7 +236,7 @@ void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u8 reg)
         warn = (orig != reg);
         if (debug || warn)
                 printk(KERN_WARNING
-                        "MUX: setup %s (0x%08x): 0x%02x -> 0x%02x\n",
+                        "MUX: setup %s (0x%p): 0x%04x -> 0x%04x\n",
                         cfg->name, omap_ctrl_base_get() + cfg->mux_reg,
                         orig, reg);
 }
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index aad781dcf1b1..d6c9de82ca0c 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -57,13 +57,6 @@ void omap2_pm_idle(void)
                 return;
         }
 
-        /*
-         * Since an interrupt may set up a timer, we don't want to
-         * reprogram the hardware timer with interrupts enabled.
-         * Re-enable interrupts only after returning from idle.
-         */
-        timer_dyn_reprogram();
-
         omap2_sram_idle();
         local_fiq_enable();
         local_irq_enable();
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index cacb34086e35..54c32f482131 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -32,6 +32,7 @@
 
 
 /* Chip-specific module offsets */
+#define OMAP24XX_GR_MOD                                 OCP_MOD
 #define OMAP24XX_DSP_MOD                                0x800
 
 #define OMAP2430_MDM_MOD                                0xc00
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index b12f423b8595..fd92a80f38f2 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -16,16 +16,21 @@
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/clk.h>
+#include <linux/io.h>
 
-#include <asm/io.h>
+#include <asm/arch/common.h>
+#include <asm/arch/prcm.h>
 
+#include "clock.h"
 #include "prm.h"
 #include "prm-regbits-24xx.h"
 
-extern void omap2_clk_prepare_for_reboot(void);
+static void __iomem *prm_base;
+static void __iomem *cm_base;
 
 u32 omap_prcm_get_reset_sources(void)
 {
+        /* XXX This presumably needs modification for 34XX */
         return prm_read_mod_reg(WKUP_MOD, RM_RSTST) & 0x7f;
 }
 EXPORT_SYMBOL(omap_prcm_get_reset_sources);
@@ -33,11 +38,90 @@ EXPORT_SYMBOL(omap_prcm_get_reset_sources);
 /* Resets clock rates and reboots the system. Only called from system.h */
 void omap_prcm_arch_reset(char mode)
 {
-        u32 wkup;
+        s16 prcm_offs;
         omap2_clk_prepare_for_reboot();
 
-        if (cpu_is_omap24xx()) {
-                wkup = prm_read_mod_reg(WKUP_MOD, RM_RSTCTRL) | OMAP_RST_DPLL3;
-                prm_write_mod_reg(wkup, WKUP_MOD, RM_RSTCTRL);
-        }
+        if (cpu_is_omap24xx())
+                prcm_offs = WKUP_MOD;
+        else if (cpu_is_omap34xx())
+                prcm_offs = OMAP3430_GR_MOD;
+        else
+                WARN_ON(1);
+
+        prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs, RM_RSTCTRL);
+}
+
+static inline u32 __omap_prcm_read(void __iomem *base, s16 module, u16 reg)
+{
+        BUG_ON(!base);
+        return __raw_readl(base + module + reg);
+}
+
+static inline void __omap_prcm_write(u32 value, void __iomem *base,
+                                                s16 module, u16 reg)
+{
+        BUG_ON(!base);
+        __raw_writel(value, base + module + reg);
+}
+
+/* Read a register in a PRM module */
+u32 prm_read_mod_reg(s16 module, u16 idx)
+{
+        return __omap_prcm_read(prm_base, module, idx);
+}
+EXPORT_SYMBOL(prm_read_mod_reg);
+
+/* Write into a register in a PRM module */
+void prm_write_mod_reg(u32 val, s16 module, u16 idx)
+{
+        __omap_prcm_write(val, prm_base, module, idx);
+}
+EXPORT_SYMBOL(prm_write_mod_reg);
+
+/* Read-modify-write a register in a PRM module. Caller must lock */
+u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
+{
+        u32 v;
+
+        v = prm_read_mod_reg(module, idx);
+        v &= ~mask;
+        v |= bits;
+        prm_write_mod_reg(v, module, idx);
+
+        return v;
+}
+EXPORT_SYMBOL(prm_rmw_mod_reg_bits);
+
+/* Read a register in a CM module */
+u32 cm_read_mod_reg(s16 module, u16 idx)
+{
+        return __omap_prcm_read(cm_base, module, idx);
+}
+EXPORT_SYMBOL(cm_read_mod_reg);
+
+/* Write into a register in a CM module */
+void cm_write_mod_reg(u32 val, s16 module, u16 idx)
+{
+        __omap_prcm_write(val, cm_base, module, idx);
+}
+EXPORT_SYMBOL(cm_write_mod_reg);
+
+/* Read-modify-write a register in a CM module. Caller must lock */
+u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
+{
+        u32 v;
+
+        v = cm_read_mod_reg(module, idx);
+        v &= ~mask;
+        v |= bits;
+        cm_write_mod_reg(v, module, idx);
+
+        return v;
+}
+EXPORT_SYMBOL(cm_rmw_mod_reg_bits);
+
+void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
+{
+        prm_base = omap2_globals->prm;
+        cm_base = omap2_globals->cm;
 }
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index 618f8111658a..bbf41fc8e9a9 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -38,13 +38,29 @@
  *
  */
 
+/* Global 24xx registers in GR_MOD (Same as OCP_MOD for 24xx) */
+#define OMAP24XX_PRCM_VOLTCTRL_OFFSET           0x0050
+#define OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET        0x0080
+
+/* 242x GR_MOD registers, use these only for assembly code */
+#define OMAP242X_PRCM_VOLTCTRL          OMAP2420_PRM_REGADDR(OMAP24XX_GR_MOD,   \
+                                                OMAP24XX_PRCM_VOLTCTRL_OFFSET)
+#define OMAP242X_PRCM_CLKCFG_CTRL       OMAP2420_PRM_REGADDR(OMAP24XX_GR_MOD,   \
+                                                OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET)
+
+/* 243x GR_MOD registers, use these only for assembly code */
+#define OMAP243X_PRCM_VOLTCTRL          OMAP2430_PRM_REGADDR(OMAP24XX_GR_MOD,   \
+                                                OMAP24XX_PRCM_VOLTCTRL_OFFSET)
+#define OMAP243X_PRCM_CLKCFG_CTRL       OMAP2430_PRM_REGADDR(OMAP24XX_GR_MOD,   \
+                                                OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET)
+
+/* These will disappear */
 #define OMAP24XX_PRCM_REVISION          OMAP_PRM_REGADDR(OCP_MOD, 0x0000)
 #define OMAP24XX_PRCM_SYSCONFIG         OMAP_PRM_REGADDR(OCP_MOD, 0x0010)
 
 #define OMAP24XX_PRCM_IRQSTATUS_MPU     OMAP_PRM_REGADDR(OCP_MOD, 0x0018)
 #define OMAP24XX_PRCM_IRQENABLE_MPU     OMAP_PRM_REGADDR(OCP_MOD, 0x001c)
 
-#define OMAP24XX_PRCM_VOLTCTRL          OMAP_PRM_REGADDR(OCP_MOD, 0x0050)
 #define OMAP24XX_PRCM_VOLTST            OMAP_PRM_REGADDR(OCP_MOD, 0x0054)
 #define OMAP24XX_PRCM_CLKSRC_CTRL       OMAP_PRM_REGADDR(OCP_MOD, 0x0060)
 #define OMAP24XX_PRCM_CLKOUT_CTRL       OMAP_PRM_REGADDR(OCP_MOD, 0x0070)
@@ -150,15 +166,19 @@
 #ifndef __ASSEMBLER__
 
 /* Power/reset management domain register get/set */
+extern u32 prm_read_mod_reg(s16 module, u16 idx);
+extern void prm_write_mod_reg(u32 val, s16 module, u16 idx);
+extern u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
 
-static inline void prm_write_mod_reg(u32 val, s16 module, s16 idx)
+/* Read-modify-write bits in a PRM register (by domain) */
+static inline u32 prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
 {
-        __raw_writel(val, OMAP_PRM_REGADDR(module, idx));
+        return prm_rmw_mod_reg_bits(bits, bits, module, idx);
 }
 
-static inline u32 prm_read_mod_reg(s16 module, s16 idx)
+static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
 {
-        return __raw_readl(OMAP_PRM_REGADDR(module, idx));
+        return prm_rmw_mod_reg_bits(bits, 0x0, module, idx);
 }
 
 #endif
diff --git a/arch/arm/mach-omap2/sdrc.h b/arch/arm/mach-omap2/sdrc.h
index d7f23bc9550a..1b1fe4f6e030 100644
--- a/arch/arm/mach-omap2/sdrc.h
+++ b/arch/arm/mach-omap2/sdrc.h
@@ -18,13 +18,11 @@
 #include <asm/arch/sdrc.h>
 
 #ifndef __ASSEMBLER__
-extern unsigned long omap2_sdrc_base;
-extern unsigned long omap2_sms_base;
+extern void __iomem *omap2_sdrc_base;
+extern void __iomem *omap2_sms_base;
 
-#define OMAP_SDRC_REGADDR(reg)                                          \
-                (void __iomem *)IO_ADDRESS(omap2_sdrc_base + (reg))
-#define OMAP_SMS_REGADDR(reg)                                           \
-                (void __iomem *)IO_ADDRESS(omap2_sms_base + (reg))
+#define OMAP_SDRC_REGADDR(reg)                  (omap2_sdrc_base + (reg))
+#define OMAP_SMS_REGADDR(reg)                   (omap2_sms_base + (reg))
 
 /* SDRC global register get/set */
 
diff --git a/arch/arm/mach-omap2/sram-fn.S b/arch/arm/mach-omap2/sram242x.S
index 4a9e49140716..4c274510f3e9 100644
--- a/arch/arm/mach-omap2/sram-fn.S
+++ b/arch/arm/mach-omap2/sram242x.S
@@ -1,5 +1,5 @@
 /*
- * linux/arch/arm/mach-omap2/sram-fn.S
+ * linux/arch/arm/mach-omap2/sram242x.S
  *
  * Omap2 specific functions that need to be run in internal SRAM
  *
@@ -27,22 +27,20 @@
 #include <asm/arch/io.h>
 #include <asm/hardware.h>
 
-#include "sdrc.h"
 #include "prm.h"
 #include "cm.h"
-
-#define TIMER_32KSYNCT_CR_V     IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010)
+#include "sdrc.h"
 
         .text
 
-ENTRY(sram_ddr_init)
+ENTRY(omap242x_sram_ddr_init)
         stmfd   sp!, {r0 - r12, lr}     @ save registers on stack
 
         mov     r12, r2                 @ capture CS1 vs CS0
         mov     r8, r3                  @ capture force parameter
 
         /* frequency shift down */
-        ldr     r2, cm_clksel2_pll      @ get address of dpllout reg
+        ldr     r2, omap242x_sdi_cm_clksel2_pll @ get address of dpllout reg
         mov     r3, #0x1                @ value for 1x operation
         str     r3, [r2]                @ go to L1-freq operation
 
@@ -51,7 +49,7 @@ ENTRY(sram_ddr_init)
         bl voltage_shift                @ go drop voltage
 
         /* dll lock mode */
-        ldr     r11, sdrc_dlla_ctrl     @ addr of dlla ctrl
+        ldr     r11, omap242x_sdi_sdrc_dlla_ctrl        @ addr of dlla ctrl
         ldr     r10, [r11]              @ get current val
         cmp     r12, #0x1               @ cs1 base (2422 es2.05/1)
         addeq   r11, r11, #0x8          @ if cs1 base, move to DLLB
@@ -102,7 +100,7 @@ i_dll_delay:
          * wait for it to finish, use 32k sync counter, 1tick=31uS.
          */
 voltage_shift:
-        ldr     r4, prcm_voltctrl       @ get addr of volt ctrl.
+        ldr     r4, omap242x_sdi_prcm_voltctrl  @ get addr of volt ctrl.
         ldr     r5, [r4]                @ get value.
         ldr     r6, prcm_mask_val       @ get value of mask
         and     r5, r5, r6              @ apply mask to clear bits
@@ -112,7 +110,7 @@ voltage_shift:
         orr     r5, r5, r3              @ build value for force
         str     r5, [r4]                @ Force transition to L1
 
-        ldr     r3, timer_32ksynct_cr   @ get addr of counter
+        ldr     r3, omap242x_sdi_timer_32ksynct_cr      @ get addr of counter
         ldr     r5, [r3]                @ get value
         add     r5, r5, #0x3            @ give it at most 93uS
 volt_delay:
@@ -121,32 +119,31 @@ volt_delay:
         bhi     volt_delay              @ not yet->branch
         mov     pc, lr                  @ back to caller.
 
-/* relative load constants */
-cm_clksel2_pll:
+omap242x_sdi_cm_clksel2_pll:
         .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
-sdrc_dlla_ctrl:
+omap242x_sdi_sdrc_dlla_ctrl:
         .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
-prcm_voltctrl:
-        .word OMAP2420_PRM_REGADDR(OCP_MOD, 0x50)
+omap242x_sdi_prcm_voltctrl:
+        .word OMAP242X_PRCM_VOLTCTRL
 prcm_mask_val:
         .word 0xFFFF3FFC
-timer_32ksynct_cr:
-        .word TIMER_32KSYNCT_CR_V
-ENTRY(sram_ddr_init_sz)
-        .word   . - sram_ddr_init
+omap242x_sdi_timer_32ksynct_cr:
+        .word IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010)
+ENTRY(omap242x_sram_ddr_init_sz)
+        .word   . - omap242x_sram_ddr_init
 
 /*
  * Reprograms memory timings.
  * r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR | SDR]
  * PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0
  */
-ENTRY(sram_reprogram_sdrc)
+ENTRY(omap242x_sram_reprogram_sdrc)
         stmfd   sp!, {r0 - r10, lr}     @ save registers on stack
         mov     r3, #0x0                @ clear for mrc call
         mcr     p15, 0, r3, c7, c10, 4  @ memory barrier, finish ARM SDR/DDR
         nop
         nop
-        ldr     r6, ddr_sdrc_rfr_ctrl   @ get addr of refresh reg
+        ldr     r6, omap242x_srs_sdrc_rfr_ctrl  @ get addr of refresh reg
         ldr     r5, [r6]                @ get value
         mov     r5, r5, lsr #8          @ isolate rfr field and drop burst
 
@@ -160,7 +157,7 @@ ENTRY(sram_reprogram_sdrc)
         movne   r5, r5, lsl #1          @ mult by 2 if to full
         mov     r5, r5, lsl #8          @ put rfr field back into place
         add     r5, r5, #0x1            @ turn on burst of 1
-        ldr     r4, ddr_cm_clksel2_pll  @ get address of out reg
+        ldr     r4, omap242x_srs_cm_clksel2_pll @ get address of out reg
         ldr     r3, [r4]                @ get curr value
         orr     r3, r3, #0x3
         bic     r3, r3, #0x3            @ clear lower bits
@@ -181,7 +178,7 @@ ENTRY(sram_reprogram_sdrc)
         bne     freq_out                @ leave if SDR, no DLL function
 
         /* With DDR, we need to take care of the DLL for the frequency change */
-        ldr     r2, ddr_sdrc_dlla_ctrl  @ addr of dlla ctrl
+        ldr     r2, omap242x_srs_sdrc_dlla_ctrl @ addr of dlla ctrl
         str     r1, [r2]                @ write out new SDRC_DLLA_CTRL
         add     r2, r2, #0x8            @ addr to SDRC_DLLB_CTRL
         str     r1, [r2]                @ commit to SDRC_DLLB_CTRL
@@ -197,7 +194,7 @@ freq_out:
      *  wait for it to finish, use 32k sync counter, 1tick=31uS.
      */
 voltage_shift_c:
-        ldr     r10, ddr_prcm_voltctrl  @ get addr of volt ctrl
+        ldr     r10, omap242x_srs_prcm_voltctrl @ get addr of volt ctrl
         ldr     r8, [r10]               @ get value
         ldr     r7, ddr_prcm_mask_val   @ get value of mask
         and     r8, r8, r7              @ apply mask to clear bits
@@ -207,7 +204,7 @@ voltage_shift_c:
         orr     r8, r8, r7              @ build value for force
         str     r8, [r10]               @ Force transition to L1
 
-        ldr     r10, ddr_timer_32ksynct @ get addr of counter
+        ldr     r10, omap242x_srs_timer_32ksynct        @ get addr of counter
         ldr     r8, [r10]               @ get value
         add     r8, r8, #0x2            @ give it at most 62uS (min 31+)
 volt_delay_c:
@@ -216,39 +213,39 @@ volt_delay_c:
         bhi     volt_delay_c            @ not yet->branch
         mov     pc, lr                  @ back to caller
 
-ddr_cm_clksel2_pll:
+omap242x_srs_cm_clksel2_pll:
         .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
-ddr_sdrc_dlla_ctrl:
+omap242x_srs_sdrc_dlla_ctrl:
         .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
-ddr_sdrc_rfr_ctrl:
+omap242x_srs_sdrc_rfr_ctrl:
         .word OMAP242X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
-ddr_prcm_voltctrl:
-        .word OMAP2420_PRM_REGADDR(OCP_MOD, 0x50)
+omap242x_srs_prcm_voltctrl:
+        .word OMAP242X_PRCM_VOLTCTRL
 ddr_prcm_mask_val:
         .word 0xFFFF3FFC
-ddr_timer_32ksynct:
-        .word TIMER_32KSYNCT_CR_V
+omap242x_srs_timer_32ksynct:
+        .word IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010)
 
-ENTRY(sram_reprogram_sdrc_sz)
-        .word   . - sram_reprogram_sdrc
+ENTRY(omap242x_sram_reprogram_sdrc_sz)
+        .word   . - omap242x_sram_reprogram_sdrc
 
 /*
  * Set dividers and pll. Also recalculate DLL value for DDR and unlock mode.
  */
-ENTRY(sram_set_prcm)
+ENTRY(omap242x_sram_set_prcm)
         stmfd   sp!, {r0-r12, lr}       @ regs to stack
         adr     r4, pbegin              @ addr of preload start
         adr     r8, pend                @ addr of preload end
         mcrr    p15, 1, r8, r4, c12     @ preload into icache
 pbegin:
         /* move into fast relock bypass */
-        ldr     r8, pll_ctl             @ get addr
+        ldr     r8, omap242x_ssp_pll_ctl        @ get addr
         ldr     r5, [r8]                @ get val
         mvn     r6, #0x3                @ clear mask
         and     r5, r5, r6              @ clear field
         orr     r7, r5, #0x2            @ fast relock val
         str     r7, [r8]                @ go to fast relock
-        ldr     r4, pll_stat            @ addr of stat
+        ldr     r4, omap242x_ssp_pll_stat       @ addr of stat
 block:
         /* wait for bypass */
         ldr     r8, [r4]                @ stat value
@@ -257,10 +254,10 @@ block:
         bne     block                   @ loop if not
 
         /* set new dpll dividers _after_ in bypass */
-        ldr     r4, pll_div             @ get addr
+        ldr     r4, omap242x_ssp_pll_div        @ get addr
         str     r0, [r4]                @ set dpll ctrl val
 
-        ldr     r4, set_config          @ get addr
+        ldr     r4, omap242x_ssp_set_config     @ get addr
         mov     r8, #1                  @ valid cfg msk
         str     r8, [r4]                @ make dividers take
 
@@ -274,8 +271,8 @@ wait_a_bit:
         beq     pend                    @ jump over dpll relock
 
         /* relock DPLL with new vals */
-        ldr     r5, pll_stat            @ get addr
-        ldr     r4, pll_ctl             @ get addr
+        ldr     r5, omap242x_ssp_pll_stat       @ get addr
+        ldr     r4, omap242x_ssp_pll_ctl        @ get addr
         orr     r8, r7, #0x3            @ val for lock dpll
         str     r8, [r4]                @ set val
         mov     r0, #1000               @ dead spin a bit
@@ -289,9 +286,9 @@ wait_lock:
         bne     wait_lock               @ wait if not
 pend:
         /* update memory timings & briefly lock dll */
-        ldr     r4, sdrc_rfr            @ get addr
+        ldr     r4, omap242x_ssp_sdrc_rfr       @ get addr
         str     r1, [r4]                @ update refresh timing
-        ldr     r11, dlla_ctrl          @ get addr of DLLA ctrl
+        ldr     r11, omap242x_ssp_dlla_ctrl     @ get addr of DLLA ctrl
         ldr     r10, [r11]              @ get current val
         mvn     r9, #0x4                @ mask to get clear bit2
         and     r10, r10, r9            @ clear bit2 for lock mode
@@ -307,18 +304,18 @@ wait_dll_lock:
         nop
         ldmfd   sp!, {r0-r12, pc}       @ restore regs and return
 
-set_config:
-        .word OMAP2420_PRM_REGADDR(OCP_MOD, 0x80)
-pll_ctl:
-        .word OMAP2420_CM_REGADDR(PLL_MOD, CM_FCLKEN1)
-pll_stat:
-        .word OMAP2420_CM_REGADDR(PLL_MOD, CM_IDLEST1)
-pll_div:
-        .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL)
-sdrc_rfr:
+omap242x_ssp_set_config:
+        .word OMAP242X_PRCM_CLKCFG_CTRL
+omap242x_ssp_pll_ctl:
+        .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKEN)
+omap242x_ssp_pll_stat:
+        .word OMAP2420_CM_REGADDR(PLL_MOD, CM_IDLEST)
+omap242x_ssp_pll_div:
+        .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
+omap242x_ssp_sdrc_rfr:
         .word OMAP242X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
-dlla_ctrl:
+omap242x_ssp_dlla_ctrl:
         .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
 
-ENTRY(sram_set_prcm_sz)
-        .word   . - sram_set_prcm
+ENTRY(omap242x_sram_set_prcm_sz)
+        .word   . - omap242x_sram_set_prcm
diff --git a/arch/arm/mach-omap2/sram243x.S b/arch/arm/mach-omap2/sram243x.S
new file mode 100644
index 000000000000..a3fa48dc08cd
--- /dev/null
+++ b/arch/arm/mach-omap2/sram243x.S
@@ -0,0 +1,321 @@
+/*
+ * linux/arch/arm/mach-omap2/sram243x.S
+ *
+ * Omap2 specific functions that need to be run in internal SRAM
+ *
+ * (C) Copyright 2004
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <asm/arch/io.h>
+#include <asm/hardware.h>
+
+#include "prm.h"
+#include "cm.h"
+#include "sdrc.h"
+
+        .text
+
+ENTRY(omap243x_sram_ddr_init)
+        stmfd   sp!, {r0 - r12, lr}     @ save registers on stack
+
+        mov     r12, r2                 @ capture CS1 vs CS0
+        mov     r8, r3                  @ capture force parameter
+
+        /* frequency shift down */
+        ldr     r2, omap243x_sdi_cm_clksel2_pll @ get address of dpllout reg
+        mov     r3, #0x1                @ value for 1x operation
+        str     r3, [r2]                @ go to L1-freq operation
+
+        /* voltage shift down */
+        mov r9, #0x1                    @ set up for L1 voltage call
+        bl voltage_shift                @ go drop voltage
+
+        /* dll lock mode */
+        ldr     r11, omap243x_sdi_sdrc_dlla_ctrl        @ addr of dlla ctrl
+        ldr     r10, [r11]              @ get current val
+        cmp     r12, #0x1               @ cs1 base (2422 es2.05/1)
+        addeq   r11, r11, #0x8          @ if cs1 base, move to DLLB
+        mvn     r9, #0x4                @ mask to get clear bit2
+        and     r10, r10, r9            @ clear bit2 for lock mode.
+        orr     r10, r10, #0x8          @ make sure DLL on (es2 bit pos)
+        orr     r10, r10, #0x2          @ 90 degree phase for all below 133Mhz
+        str     r10, [r11]              @ commit to DLLA_CTRL
+        bl      i_dll_wait              @ wait for dll to lock
+
+        /* get dll value */
+        add     r11, r11, #0x4          @ get addr of status reg
+        ldr     r10, [r11]              @ get locked value
+
+        /* voltage shift up */
+        mov r9, #0x0                    @ shift back to L0-voltage
+        bl voltage_shift                @ go raise voltage
+
+        /* frequency shift up */
+        mov     r3, #0x2                @ value for 2x operation
+        str     r3, [r2]                @ go to L0-freq operation
+
+        /* reset entry mode for dllctrl */
+        sub     r11, r11, #0x4          @ move from status to ctrl
+        cmp     r12, #0x1               @ normalize if cs1 based
+        subeq   r11, r11, #0x8          @ possibly back to DLLA
+        cmp     r8, #0x1                @ if forced unlock exit
+        orreq   r1, r1, #0x4            @ make sure exit with unlocked value
+        str     r1, [r11]               @ restore DLLA_CTRL high value
+        add     r11, r11, #0x8          @ move to DLLB_CTRL addr
+        str     r1, [r11]               @ set value DLLB_CTRL
+        bl      i_dll_wait              @ wait for possible lock
+
+        /* set up for return, DDR should be good */
+        str r10, [r0]                   @ write dll_status and return counter
+        ldmfd   sp!, {r0 - r12, pc}     @ restore regs and return
+
+        /* ensure the DLL has relocked */
+i_dll_wait:
+        mov     r4, #0x800              @ delay DLL relock, min 0x400 L3 clocks
+i_dll_delay:
+        subs    r4, r4, #0x1
+        bne     i_dll_delay
+        mov     pc, lr
+
+        /*
+         * shift up or down voltage, use R9 as input to tell level.
+         * wait for it to finish, use 32k sync counter, 1tick=31uS.
+         */
+voltage_shift:
+        ldr     r4, omap243x_sdi_prcm_voltctrl  @ get addr of volt ctrl.
+        ldr     r5, [r4]                @ get value.
+        ldr     r6, prcm_mask_val       @ get value of mask
+        and     r5, r5, r6              @ apply mask to clear bits
+        orr     r5, r5, r9              @ bulld value for L0/L1-volt operation.
+        str     r5, [r4]                @ set up for change.
+        mov     r3, #0x4000             @ get val for force
+        orr     r5, r5, r3              @ build value for force
+        str     r5, [r4]                @ Force transition to L1
+
+        ldr     r3, omap243x_sdi_timer_32ksynct_cr      @ get addr of counter
+        ldr     r5, [r3]                @ get value
+        add     r5, r5, #0x3            @ give it at most 93uS
+volt_delay:
+        ldr     r7, [r3]                @ get timer value
+        cmp     r5, r7                  @ time up?
+        bhi     volt_delay              @ not yet->branch
+        mov     pc, lr                  @ back to caller.
+
+omap243x_sdi_cm_clksel2_pll:
+        .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
+omap243x_sdi_sdrc_dlla_ctrl:
+        .word OMAP243X_SDRC_REGADDR(SDRC_DLLA_CTRL)
+omap243x_sdi_prcm_voltctrl:
+        .word OMAP243X_PRCM_VOLTCTRL
+prcm_mask_val:
+        .word 0xFFFF3FFC
+omap243x_sdi_timer_32ksynct_cr:
+        .word IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010)
+ENTRY(omap243x_sram_ddr_init_sz)
+        .word   . - omap243x_sram_ddr_init
+
+/*
+ * Reprograms memory timings.
+ * r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR | SDR]
+ * PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0
+ */
+ENTRY(omap243x_sram_reprogram_sdrc)
+        stmfd   sp!, {r0 - r10, lr}     @ save registers on stack
+        mov     r3, #0x0                @ clear for mrc call
+        mcr     p15, 0, r3, c7, c10, 4  @ memory barrier, finish ARM SDR/DDR
+        nop
+        nop
+        ldr     r6, omap243x_srs_sdrc_rfr_ctrl  @ get addr of refresh reg
+        ldr     r5, [r6]                @ get value
+        mov     r5, r5, lsr #8          @ isolate rfr field and drop burst
+
+        cmp     r0, #0x1                @ going to half speed?
+        movne   r9, #0x0                @ if up set flag up for pre up, hi volt
+
+        blne    voltage_shift_c         @ adjust voltage
+
+        cmp     r0, #0x1                @ going to half speed (post branch link)
+        moveq   r5, r5, lsr #1          @ divide by 2 if to half
+        movne   r5, r5, lsl #1          @ mult by 2 if to full
+        mov     r5, r5, lsl #8          @ put rfr field back into place
+        add     r5, r5, #0x1            @ turn on burst of 1
+        ldr     r4, omap243x_srs_cm_clksel2_pll @ get address of out reg
+        ldr     r3, [r4]                @ get curr value
+        orr     r3, r3, #0x3
+        bic     r3, r3, #0x3            @ clear lower bits
+        orr     r3, r3, r0              @ new state value
+        str     r3, [r4]                @ set new state (pll/x, x=1 or 2)
+        nop
+        nop
+
+        moveq   r9, #0x1                @ if speed down, post down, drop volt
+        bleq    voltage_shift_c
+
+        mcr     p15, 0, r3, c7, c10, 4  @ memory barrier
+        str     r5, [r6]                @ set new RFR_1 value
+        add     r6, r6, #0x30           @ get RFR_2 addr
+        str     r5, [r6]                @ set RFR_2
+        nop
+        cmp     r2, #0x1                @ (SDR or DDR) do we need to adjust DLL
+        bne     freq_out                @ leave if SDR, no DLL function
+
+        /* With DDR, we need to take care of the DLL for the frequency change */
+        ldr     r2, omap243x_srs_sdrc_dlla_ctrl @ addr of dlla ctrl
+        str     r1, [r2]                @ write out new SDRC_DLLA_CTRL
+        add     r2, r2, #0x8            @ addr to SDRC_DLLB_CTRL
+        str     r1, [r2]                @ commit to SDRC_DLLB_CTRL
+        mov     r1, #0x2000             @ wait DLL relock, min 0x400 L3 clocks
+dll_wait:
+        subs    r1, r1, #0x1
+        bne     dll_wait
+freq_out:
+        ldmfd   sp!, {r0 - r10, pc}     @ restore regs and return
+
+    /*
+     * shift up or down voltage, use R9 as input to tell level.
+     *  wait for it to finish, use 32k sync counter, 1tick=31uS.
+     */
+voltage_shift_c:
+        ldr     r10, omap243x_srs_prcm_voltctrl @ get addr of volt ctrl
+        ldr     r8, [r10]               @ get value
+        ldr     r7, ddr_prcm_mask_val   @ get value of mask
+        and     r8, r8, r7              @ apply mask to clear bits
+        orr     r8, r8, r9              @ bulld value for L0/L1-volt operation.
+        str     r8, [r10]               @ set up for change.
+        mov     r7, #0x4000             @ get val for force
+        orr     r8, r8, r7              @ build value for force
+        str     r8, [r10]               @ Force transition to L1
+
+        ldr     r10, omap243x_srs_timer_32ksynct        @ get addr of counter
+        ldr     r8, [r10]               @ get value
+        add     r8, r8, #0x2            @ give it at most 62uS (min 31+)
+volt_delay_c:
+        ldr     r7, [r10]               @ get timer value
+        cmp     r8, r7                  @ time up?
+        bhi     volt_delay_c            @ not yet->branch
+        mov     pc, lr                  @ back to caller
+
+omap243x_srs_cm_clksel2_pll:
+        .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
+omap243x_srs_sdrc_dlla_ctrl:
+        .word OMAP243X_SDRC_REGADDR(SDRC_DLLA_CTRL)
+omap243x_srs_sdrc_rfr_ctrl:
+        .word OMAP243X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
+omap243x_srs_prcm_voltctrl:
+        .word OMAP243X_PRCM_VOLTCTRL
+ddr_prcm_mask_val:
+        .word 0xFFFF3FFC
+omap243x_srs_timer_32ksynct:
+        .word IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010)
+
+ENTRY(omap243x_sram_reprogram_sdrc_sz)
+        .word   . - omap243x_sram_reprogram_sdrc
+
+/*
+ * Set dividers and pll. Also recalculate DLL value for DDR and unlock mode.
+ */
+ENTRY(omap243x_sram_set_prcm)
+        stmfd   sp!, {r0-r12, lr}       @ regs to stack
+        adr     r4, pbegin              @ addr of preload start
+        adr     r8, pend                @ addr of preload end
+        mcrr    p15, 1, r8, r4, c12     @ preload into icache
+pbegin:
+        /* move into fast relock bypass */
+        ldr     r8, omap243x_ssp_pll_ctl        @ get addr
+        ldr     r5, [r8]                @ get val
+        mvn     r6, #0x3                @ clear mask
+        and     r5, r5, r6              @ clear field
+        orr     r7, r5, #0x2            @ fast relock val
+        str     r7, [r8]                @ go to fast relock
+        ldr     r4, omap243x_ssp_pll_stat       @ addr of stat
+block:
+        /* wait for bypass */
+        ldr     r8, [r4]                @ stat value
+        and     r8, r8, #0x3            @ mask for stat
+        cmp     r8, #0x1                @ there yet
+        bne     block                   @ loop if not
+
+        /* set new dpll dividers _after_ in bypass */
+        ldr     r4, omap243x_ssp_pll_div        @ get addr
+        str     r0, [r4]                @ set dpll ctrl val
+
+        ldr     r4, omap243x_ssp_set_config     @ get addr
+        mov     r8, #1                  @ valid cfg msk
+        str     r8, [r4]                @ make dividers take
+
+        mov     r4, #100                @ dead spin a bit
+wait_a_bit:
+        subs    r4, r4, #1              @ dec loop
+        bne     wait_a_bit              @ delay done?
+
+        /* check if staying in bypass */
+        cmp     r2, #0x1                @ stay in bypass?
+        beq     pend                    @ jump over dpll relock
+
+        /* relock DPLL with new vals */
+        ldr     r5, omap243x_ssp_pll_stat       @ get addr
+        ldr     r4, omap243x_ssp_pll_ctl        @ get addr
+        orr     r8, r7, #0x3            @ val for lock dpll
+        str     r8, [r4]                @ set val
+        mov     r0, #1000               @ dead spin a bit
+wait_more:
+        subs    r0, r0, #1              @ dec loop
+        bne     wait_more               @ delay done?
+wait_lock:
+        ldr     r8, [r5]                @ get lock val
+        and     r8, r8, #3              @ isolate field
+        cmp     r8, #2                  @ locked?
+        bne     wait_lock               @ wait if not
+pend:
+        /* update memory timings & briefly lock dll */
+        ldr     r4, omap243x_ssp_sdrc_rfr       @ get addr
+        str     r1, [r4]                @ update refresh timing
+        ldr     r11, omap243x_ssp_dlla_ctrl     @ get addr of DLLA ctrl
+        ldr     r10, [r11]              @ get current val
+        mvn     r9, #0x4                @ mask to get clear bit2
+        and     r10, r10, r9            @ clear bit2 for lock mode
+        orr     r10, r10, #0x8          @ make sure DLL on (es2 bit pos)
+        str     r10, [r11]              @ commit to DLLA_CTRL
+        add     r11, r11, #0x8          @ move to dllb
+        str     r10, [r11]              @ hit DLLB also
+
+        mov     r4, #0x800              @ relock time (min 0x400 L3 clocks)
+wait_dll_lock:
+        subs    r4, r4, #0x1
+        bne     wait_dll_lock
+        nop
+        ldmfd   sp!, {r0-r12, pc}       @ restore regs and return
+
+omap243x_ssp_set_config:
+        .word OMAP243X_PRCM_CLKCFG_CTRL
+omap243x_ssp_pll_ctl:
+        .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKEN)
+omap243x_ssp_pll_stat:
+        .word OMAP2430_CM_REGADDR(PLL_MOD, CM_IDLEST)
+omap243x_ssp_pll_div:
+        .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
+omap243x_ssp_sdrc_rfr:
+        .word OMAP243X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
+omap243x_ssp_dlla_ctrl:
+        .word OMAP243X_SDRC_REGADDR(SDRC_DLLA_CTRL)
+
+ENTRY(omap243x_sram_set_prcm_sz)
+        .word   . - omap243x_sram_set_prcm
diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
index 78d05f203fff..557603f99313 100644
--- a/arch/arm/mach-omap2/timer-gp.c
+++ b/arch/arm/mach-omap2/timer-gp.c
@@ -59,8 +59,7 @@ static struct irqaction omap2_gp_timer_irq = {
 static int omap2_gp_timer_set_next_event(unsigned long cycles,
                                          struct clock_event_device *evt)
 {
-        omap_dm_timer_set_load(gptimer, 0, 0xffffffff - cycles);
-        omap_dm_timer_start(gptimer);
+        omap_dm_timer_set_load_start(gptimer, 0, 0xffffffff - cycles);
 
         return 0;
 }
@@ -77,8 +76,7 @@ static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
                 period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / HZ;
                 period -= 1;
 
-                omap_dm_timer_set_load(gptimer, 1, 0xffffffff - period);
-                omap_dm_timer_start(gptimer);
+                omap_dm_timer_set_load_start(gptimer, 1, 0xffffffff - period);
                 break;
         case CLOCK_EVT_MODE_ONESHOT:
                 break;
@@ -172,8 +170,7 @@ static void __init omap2_gp_clocksource_init(void)
         tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gpt));
         tick_period = (tick_rate / HZ) - 1;
 
-        omap_dm_timer_set_load(gpt, 1, 0);
-        omap_dm_timer_start(gpt);
+        omap_dm_timer_set_load_start(gpt, 1, 0);
 
         clocksource_gpt.mult =
                 clocksource_khz2mult(tick_rate/1000, clocksource_gpt.shift);
diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
index 93debf336155..ddcd41b15d17 100644
--- a/arch/arm/mach-orion5x/Kconfig
+++ b/arch/arm/mach-orion5x/Kconfig
@@ -44,6 +44,54 @@ config MACH_LINKSTATION_PRO
           Buffalo Linkstation Pro/Live platform. Both v1 and
           v2 devices are supported.
 
+config MACH_TS409
+        bool "QNAP TS-409"
+        help
+          Say 'Y' here if you want your kernel to support the
+          QNAP TS-409 platform.
+
+config MACH_WRT350N_V2
+        bool "Linksys WRT350N v2"
+        help
+          Say 'Y' here if you want your kernel to support the
+          Linksys WRT350N v2 platform.
+
+config MACH_TS78XX
+        bool "Technologic Systems TS-78xx"
+        help
+          Say 'Y' here if you want your kernel to support the
+          Technologic Systems TS-78xx platform.
+
+config MACH_MV2120
+        bool "HP Media Vault mv2120"
+        help
+          Say 'Y' here if you want your kernel to support the
+          HP Media Vault mv2120 or mv5100.
+
+config MACH_MSS2
+        bool "Maxtor Shared Storage II"
+        help
+          Say 'Y' here if you want your kernel to support the
+          Maxtor Shared Storage II platform.
+
+config MACH_WNR854T
+        bool "Netgear WNR854T"
+        help
+          Say 'Y' here if you want your kernel to support the
+          Netgear WNR854T platform.
+
+config MACH_RD88F5181L_GE
+        bool "Marvell Orion-VoIP GE Reference Design"
+        help
+          Say 'Y' here if you want your kernel to support the
+          Marvell Orion-VoIP GE (88F5181L) RD.
+
+config MACH_RD88F5181L_FXO
+        bool "Marvell Orion-VoIP FXO Reference Design"
+        help
+          Say 'Y' here if you want your kernel to support the
+          Marvell Orion-VoIP FXO (88F5181L) RD.
+
 endmenu
 
 endif
diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile
index 9301bf55910b..fcc48a8864f3 100644
--- a/arch/arm/mach-orion5x/Makefile
+++ b/arch/arm/mach-orion5x/Makefile
@@ -1,7 +1,15 @@
-obj-y                           += common.o addr-map.o pci.o gpio.o irq.o
+obj-y                           += common.o addr-map.o pci.o gpio.o irq.o mpp.o
 obj-$(CONFIG_MACH_DB88F5281)    += db88f5281-setup.o
 obj-$(CONFIG_MACH_RD88F5182)    += rd88f5182-setup.o
 obj-$(CONFIG_MACH_KUROBOX_PRO)  += kurobox_pro-setup.o
 obj-$(CONFIG_MACH_LINKSTATION_PRO) += kurobox_pro-setup.o
 obj-$(CONFIG_MACH_DNS323)       += dns323-setup.o
-obj-$(CONFIG_MACH_TS209)        += ts209-setup.o
+obj-$(CONFIG_MACH_TS209)        += ts209-setup.o tsx09-common.o
+obj-$(CONFIG_MACH_TS409)        += ts409-setup.o tsx09-common.o
+obj-$(CONFIG_MACH_WRT350N_V2)   += wrt350n-v2-setup.o
+obj-$(CONFIG_MACH_TS78XX)       += ts78xx-setup.o
+obj-$(CONFIG_MACH_MV2120)       += mv2120-setup.o
+obj-$(CONFIG_MACH_MSS2)         += mss2-setup.o
+obj-$(CONFIG_MACH_WNR854T)      += wnr854t-setup.o
+obj-$(CONFIG_MACH_RD88F5181L_GE)        += rd88f5181l-ge-setup.o
+obj-$(CONFIG_MACH_RD88F5181L_FXO)       += rd88f5181l-fxo-setup.o
diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c
index e63fb05dc893..6f0dbda6c44c 100644
--- a/arch/arm/mach-orion5x/addr-map.c
+++ b/arch/arm/mach-orion5x/addr-map.c
@@ -70,6 +70,7 @@
 
 
 struct mbus_dram_target_info orion5x_mbus_dram_info;
+static int __initdata win_alloc_count;
 
 static int __init orion5x_cpu_win_can_remap(int win)
 {
@@ -87,16 +88,22 @@ static int __init orion5x_cpu_win_can_remap(int win)
 static void __init setup_cpu_win(int win, u32 base, u32 size,
                                  u8 target, u8 attr, int remap)
 {
-        orion5x_write(CPU_WIN_BASE(win), base & 0xffff0000);
-        orion5x_write(CPU_WIN_CTRL(win),
-                ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1);
+        if (win >= 8) {
+                printk(KERN_ERR "setup_cpu_win: trying to allocate "
+                                "window %d\n", win);
+                return;
+        }
+
+        writel(base & 0xffff0000, CPU_WIN_BASE(win));
+        writel(((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1,
+                CPU_WIN_CTRL(win));
 
         if (orion5x_cpu_win_can_remap(win)) {
                 if (remap < 0)
                         remap = base;
 
-                orion5x_write(CPU_WIN_REMAP_LO(win), remap & 0xffff0000);
-                orion5x_write(CPU_WIN_REMAP_HI(win), 0);
+                writel(remap & 0xffff0000, CPU_WIN_REMAP_LO(win));
+                writel(0, CPU_WIN_REMAP_HI(win));
         }
 }
 
@@ -109,11 +116,11 @@ void __init orion5x_setup_cpu_mbus_bridge(void)
          * First, disable and clear windows.
          */
         for (i = 0; i < 8; i++) {
-                orion5x_write(CPU_WIN_BASE(i), 0);
-                orion5x_write(CPU_WIN_CTRL(i), 0);
+                writel(0, CPU_WIN_BASE(i));
+                writel(0, CPU_WIN_CTRL(i));
                 if (orion5x_cpu_win_can_remap(i)) {
-                        orion5x_write(CPU_WIN_REMAP_LO(i), 0);
-                        orion5x_write(CPU_WIN_REMAP_HI(i), 0);
+                        writel(0, CPU_WIN_REMAP_LO(i));
+                        writel(0, CPU_WIN_REMAP_HI(i));
                 }
         }
 
@@ -128,6 +135,7 @@ void __init orion5x_setup_cpu_mbus_bridge(void)
                 TARGET_PCIE, ATTR_PCIE_MEM, -1);
         setup_cpu_win(3, ORION5X_PCI_MEM_PHYS_BASE, ORION5X_PCI_MEM_SIZE,
                 TARGET_PCI, ATTR_PCI_MEM, -1);
+        win_alloc_count = 4;
 
         /*
          * Setup MBUS dram target info.
@@ -147,8 +155,8 @@ void __init orion5x_setup_cpu_mbus_bridge(void)
                         w = &orion5x_mbus_dram_info.cs[cs++];
                         w->cs_index = i;
                         w->mbus_attr = 0xf & ~(1 << i);
-                        w->base = base & 0xff000000;
-                        w->size = (size | 0x00ffffff) + 1;
+                        w->base = base & 0xffff0000;
+                        w->size = (size | 0x0000ffff) + 1;
                 }
         }
         orion5x_mbus_dram_info.num_cs = cs;
@@ -156,25 +164,30 @@ void __init orion5x_setup_cpu_mbus_bridge(void)
 
 void __init orion5x_setup_dev_boot_win(u32 base, u32 size)
 {
-        setup_cpu_win(4, base, size, TARGET_DEV_BUS, ATTR_DEV_BOOT, -1);
+        setup_cpu_win(win_alloc_count++, base, size,
+                      TARGET_DEV_BUS, ATTR_DEV_BOOT, -1);
 }
 
 void __init orion5x_setup_dev0_win(u32 base, u32 size)
 {
-        setup_cpu_win(5, base, size, TARGET_DEV_BUS, ATTR_DEV_CS0, -1);
+        setup_cpu_win(win_alloc_count++, base, size,
+                      TARGET_DEV_BUS, ATTR_DEV_CS0, -1);
 }
 
 void __init orion5x_setup_dev1_win(u32 base, u32 size)
 {
-        setup_cpu_win(6, base, size, TARGET_DEV_BUS, ATTR_DEV_CS1, -1);
+        setup_cpu_win(win_alloc_count++, base, size,
+                      TARGET_DEV_BUS, ATTR_DEV_CS1, -1);
 }
 
 void __init orion5x_setup_dev2_win(u32 base, u32 size)
 {
-        setup_cpu_win(7, base, size, TARGET_DEV_BUS, ATTR_DEV_CS2, -1);
+        setup_cpu_win(win_alloc_count++, base, size,
+                      TARGET_DEV_BUS, ATTR_DEV_CS2, -1);
 }
 
 void __init orion5x_setup_pcie_wa_win(u32 base, u32 size)
 {
-        setup_cpu_win(7, base, size, TARGET_PCIE, ATTR_PCIE_WA, -1);
+        setup_cpu_win(win_alloc_count++, base, size,
+                      TARGET_PCIE, ATTR_PCIE_WA, -1);
 }
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index 4f13fd037f04..faf4e3211918 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -39,25 +39,22 @@ static struct map_desc orion5x_io_desc[] __initdata = {
                 .virtual        = ORION5X_REGS_VIRT_BASE,
                 .pfn            = __phys_to_pfn(ORION5X_REGS_PHYS_BASE),
                 .length         = ORION5X_REGS_SIZE,
-                .type           = MT_DEVICE
-        },
-        {
+                .type           = MT_DEVICE,
+        }, {
                 .virtual        = ORION5X_PCIE_IO_VIRT_BASE,
                 .pfn            = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE),
                 .length         = ORION5X_PCIE_IO_SIZE,
-                .type           = MT_DEVICE
-        },
-        {
+                .type           = MT_DEVICE,
+        }, {
                 .virtual        = ORION5X_PCI_IO_VIRT_BASE,
                 .pfn            = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE),
                 .length         = ORION5X_PCI_IO_SIZE,
-                .type           = MT_DEVICE
-        },
-        {
+                .type           = MT_DEVICE,
+        }, {
                 .virtual        = ORION5X_PCIE_WA_VIRT_BASE,
                 .pfn            = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),
                 .length         = ORION5X_PCIE_WA_SIZE,
-                .type           = MT_DEVICE
+                .type           = MT_DEVICE,
         },
 };
 
@@ -66,101 +63,32 @@ void __init orion5x_map_io(void)
         iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc));
 }
 
+
 /*****************************************************************************
- * UART
+ * EHCI
  ****************************************************************************/
-
-static struct resource orion5x_uart_resources[] = {
-        {
-                .start          = UART0_PHYS_BASE,
-                .end            = UART0_PHYS_BASE + 0xff,
-                .flags          = IORESOURCE_MEM,
-        },
-        {
-                .start          = IRQ_ORION5X_UART0,
-                .end            = IRQ_ORION5X_UART0,
-                .flags          = IORESOURCE_IRQ,
-        },
-        {
-                .start          = UART1_PHYS_BASE,
-                .end            = UART1_PHYS_BASE + 0xff,
-                .flags          = IORESOURCE_MEM,
-        },
-        {
-                .start          = IRQ_ORION5X_UART1,
-                .end            = IRQ_ORION5X_UART1,
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-
-static struct plat_serial8250_port orion5x_uart_data[] = {
-        {
-                .mapbase        = UART0_PHYS_BASE,
-                .membase        = (char *)UART0_VIRT_BASE,
-                .irq            = IRQ_ORION5X_UART0,
-                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-                .uartclk        = ORION5X_TCLK,
-        },
-        {
-                .mapbase        = UART1_PHYS_BASE,
-                .membase        = (char *)UART1_VIRT_BASE,
-                .irq            = IRQ_ORION5X_UART1,
-                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-                .uartclk        = ORION5X_TCLK,
-        },
-        { },
+static struct orion_ehci_data orion5x_ehci_data = {
+        .dram           = &orion5x_mbus_dram_info,
 };
 
-static struct platform_device orion5x_uart = {
-        .name                   = "serial8250",
-        .id                     = PLAT8250_DEV_PLATFORM,
-        .dev                    = {
-                .platform_data  = orion5x_uart_data,
-        },
-        .resource               = orion5x_uart_resources,
-        .num_resources          = ARRAY_SIZE(orion5x_uart_resources),
-};
+static u64 ehci_dmamask = 0xffffffffUL;
 
-/*******************************************************************************
- * USB Controller - 2 interfaces
- ******************************************************************************/
 
+/*****************************************************************************
+ * EHCI0
+ ****************************************************************************/
 static struct resource orion5x_ehci0_resources[] = {
         {
                 .start  = ORION5X_USB0_PHYS_BASE,
                 .end    = ORION5X_USB0_PHYS_BASE + SZ_4K - 1,
                 .flags  = IORESOURCE_MEM,
-        },
-        {
+        }, {
                 .start  = IRQ_ORION5X_USB0_CTRL,
                 .end    = IRQ_ORION5X_USB0_CTRL,
                 .flags  = IORESOURCE_IRQ,
         },
 };
 
-static struct resource orion5x_ehci1_resources[] = {
-        {
-                .start  = ORION5X_USB1_PHYS_BASE,
-                .end    = ORION5X_USB1_PHYS_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = IRQ_ORION5X_USB1_CTRL,
-                .end    = IRQ_ORION5X_USB1_CTRL,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct orion_ehci_data orion5x_ehci_data = {
-        .dram           = &orion5x_mbus_dram_info,
-};
-
-static u64 ehci_dmamask = 0xffffffffUL;
-
 static struct platform_device orion5x_ehci0 = {
         .name           = "orion-ehci",
         .id             = 0,
@@ -173,6 +101,27 @@ static struct platform_device orion5x_ehci0 = {
         .num_resources  = ARRAY_SIZE(orion5x_ehci0_resources),
 };
 
+void __init orion5x_ehci0_init(void)
+{
+        platform_device_register(&orion5x_ehci0);
+}
+
+
+/*****************************************************************************
+ * EHCI1
+ ****************************************************************************/
+static struct resource orion5x_ehci1_resources[] = {
+        {
+                .start  = ORION5X_USB1_PHYS_BASE,
+                .end    = ORION5X_USB1_PHYS_BASE + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = IRQ_ORION5X_USB1_CTRL,
+                .end    = IRQ_ORION5X_USB1_CTRL,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
 static struct platform_device orion5x_ehci1 = {
         .name           = "orion-ehci",
         .id             = 1,
@@ -185,11 +134,15 @@ static struct platform_device orion5x_ehci1 = {
         .num_resources  = ARRAY_SIZE(orion5x_ehci1_resources),
 };
 
+void __init orion5x_ehci1_init(void)
+{
+        platform_device_register(&orion5x_ehci1);
+}
+
+
 /*****************************************************************************
- * Gigabit Ethernet port
- * (The Orion and Discovery (MV643xx) families use the same Ethernet driver)
+ * GigE
  ****************************************************************************/
-
 struct mv643xx_eth_shared_platform_data orion5x_eth_shared_data = {
         .dram           = &orion5x_mbus_dram_info,
         .t_clk          = ORION5X_TCLK,
@@ -219,7 +172,7 @@ static struct resource orion5x_eth_resources[] = {
                 .start  = IRQ_ORION5X_ETH_SUM,
                 .end    = IRQ_ORION5X_ETH_SUM,
                 .flags  = IORESOURCE_IRQ,
-        }
+        },
 };
 
 static struct platform_device orion5x_eth = {
@@ -238,11 +191,10 @@ void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
         platform_device_register(&orion5x_eth);
 }
 
+
 /*****************************************************************************
- * I2C controller
- * (The Orion and Discovery (MV643xx) families share the same I2C controller)
+ * I2C
  ****************************************************************************/
-
 static struct mv64xxx_i2c_pdata orion5x_i2c_pdata = {
         .freq_m         = 8, /* assumes 166 MHz TCLK */
         .freq_n         = 3,
@@ -251,16 +203,15 @@ static struct mv64xxx_i2c_pdata orion5x_i2c_pdata = {
 
 static struct resource orion5x_i2c_resources[] = {
         {
-                .name   = "i2c base",
-                .start  = I2C_PHYS_BASE,
-                .end    = I2C_PHYS_BASE + 0x20 -1,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .name   = "i2c irq",
-                .start  = IRQ_ORION5X_I2C,
-                .end    = IRQ_ORION5X_I2C,
-                .flags  = IORESOURCE_IRQ,
+                .name   = "i2c base",
+                .start  = I2C_PHYS_BASE,
+                .end    = I2C_PHYS_BASE + 0x1f,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .name   = "i2c irq",
+                .start  = IRQ_ORION5X_I2C,
+                .end    = IRQ_ORION5X_I2C,
+                .flags  = IORESOURCE_IRQ,
         },
 };
 
@@ -270,36 +221,41 @@ static struct platform_device orion5x_i2c = {
         .num_resources  = ARRAY_SIZE(orion5x_i2c_resources),
         .resource       = orion5x_i2c_resources,
         .dev            = {
-                .platform_data = &orion5x_i2c_pdata,
+                .platform_data  = &orion5x_i2c_pdata,
         },
 };
 
+void __init orion5x_i2c_init(void)
+{
+        platform_device_register(&orion5x_i2c);
+}
+
+
 /*****************************************************************************
- * Sata port
+ * SATA
  ****************************************************************************/
 static struct resource orion5x_sata_resources[] = {
-        {
-                .name   = "sata base",
-                .start  = ORION5X_SATA_PHYS_BASE,
-                .end    = ORION5X_SATA_PHYS_BASE + 0x5000 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
         {
-                .name   = "sata irq",
-                .start  = IRQ_ORION5X_SATA,
-                .end    = IRQ_ORION5X_SATA,
-                .flags  = IORESOURCE_IRQ,
-        },
+                .name   = "sata base",
+                .start  = ORION5X_SATA_PHYS_BASE,
+                .end    = ORION5X_SATA_PHYS_BASE + 0x5000 - 1,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .name   = "sata irq",
+                .start  = IRQ_ORION5X_SATA,
+                .end    = IRQ_ORION5X_SATA,
+                .flags  = IORESOURCE_IRQ,
+        },
 };
 
 static struct platform_device orion5x_sata = {
-        .name           = "sata_mv",
-        .id             = 0,
+        .name           = "sata_mv",
+        .id             = 0,
         .dev            = {
                 .coherent_dma_mask      = 0xffffffff,
         },
-        .num_resources  = ARRAY_SIZE(orion5x_sata_resources),
-        .resource       = orion5x_sata_resources,
+        .num_resources  = ARRAY_SIZE(orion5x_sata_resources),
+        .resource       = orion5x_sata_resources,
 };
 
 void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
@@ -309,23 +265,111 @@ void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
         platform_device_register(&orion5x_sata);
 }
 
+
 /*****************************************************************************
- * Time handling
+ * UART0
+ ****************************************************************************/
+static struct plat_serial8250_port orion5x_uart0_data[] = {
+        {
+                .mapbase        = UART0_PHYS_BASE,
+                .membase        = (char *)UART0_VIRT_BASE,
+                .irq            = IRQ_ORION5X_UART0,
+                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+                .uartclk        = ORION5X_TCLK,
+        }, {
+        },
+};
+
+static struct resource orion5x_uart0_resources[] = {
+        {
+                .start          = UART0_PHYS_BASE,
+                .end            = UART0_PHYS_BASE + 0xff,
+                .flags          = IORESOURCE_MEM,
+        }, {
+                .start          = IRQ_ORION5X_UART0,
+                .end            = IRQ_ORION5X_UART0,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device orion5x_uart0 = {
+        .name                   = "serial8250",
+        .id                     = PLAT8250_DEV_PLATFORM,
+        .dev                    = {
+                .platform_data  = orion5x_uart0_data,
+        },
+        .resource               = orion5x_uart0_resources,
+        .num_resources          = ARRAY_SIZE(orion5x_uart0_resources),
+};
+
+void __init orion5x_uart0_init(void)
+{
+        platform_device_register(&orion5x_uart0);
+}
+
+
+/*****************************************************************************
+ * UART1
  ****************************************************************************/
+static struct plat_serial8250_port orion5x_uart1_data[] = {
+        {
+                .mapbase        = UART1_PHYS_BASE,
+                .membase        = (char *)UART1_VIRT_BASE,
+                .irq            = IRQ_ORION5X_UART1,
+                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+                .uartclk        = ORION5X_TCLK,
+        }, {
+        },
+};
+
+static struct resource orion5x_uart1_resources[] = {
+        {
+                .start          = UART1_PHYS_BASE,
+                .end            = UART1_PHYS_BASE + 0xff,
+                .flags          = IORESOURCE_MEM,
+        }, {
+                .start          = IRQ_ORION5X_UART1,
+                .end            = IRQ_ORION5X_UART1,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device orion5x_uart1 = {
+        .name                   = "serial8250",
+        .id                     = PLAT8250_DEV_PLATFORM1,
+        .dev                    = {
+                .platform_data  = orion5x_uart1_data,
+        },
+        .resource               = orion5x_uart1_resources,
+        .num_resources          = ARRAY_SIZE(orion5x_uart1_resources),
+};
+
+void __init orion5x_uart1_init(void)
+{
+        platform_device_register(&orion5x_uart1);
+}
+
 
+/*****************************************************************************
+ * Time handling
+ ****************************************************************************/
 static void orion5x_timer_init(void)
 {
         orion_time_init(IRQ_ORION5X_BRIDGE, ORION5X_TCLK);
 }
 
 struct sys_timer orion5x_timer = {
-        .init = orion5x_timer_init,
+        .init = orion5x_timer_init,
 };
 
+
 /*****************************************************************************
  * General
  ****************************************************************************/
-
 /*
  * Identify device ID and rev from PCIe configuration header space '0'.
  */
@@ -350,8 +394,10 @@ static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name)
         } else if (*dev == MV88F5181_DEV_ID) {
                 if (*rev == MV88F5181_REV_B1) {
                         *dev_name = "MV88F5181-Rev-B1";
+                } else if (*rev == MV88F5181L_REV_A1) {
+                        *dev_name = "MV88F5181L-Rev-A1";
                 } else {
-                        *dev_name = "MV88F5181-Rev-Unsupported";
+                        *dev_name = "MV88F5181(L)-Rev-Unsupported";
                 }
         } else {
                 *dev_name = "Device-Unknown";
@@ -370,15 +416,6 @@ void __init orion5x_init(void)
          * Setup Orion address map
          */
         orion5x_setup_cpu_mbus_bridge();
-
-        /*
-         * Register devices.
-         */
-        platform_device_register(&orion5x_uart);
-        platform_device_register(&orion5x_ehci0);
-        if (dev == MV88F5182_DEV_ID)
-                platform_device_register(&orion5x_ehci1);
-        platform_device_register(&orion5x_i2c);
 }
 
 /*
diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h
index bd0f05de6e18..f72cf0e77544 100644
--- a/arch/arm/mach-orion5x/common.h
+++ b/arch/arm/mach-orion5x/common.h
@@ -1,10 +1,12 @@
 #ifndef __ARCH_ORION5X_COMMON_H
 #define __ARCH_ORION5X_COMMON_H
 
+struct mv643xx_eth_platform_data;
+struct mv_sata_platform_data;
+
 /*
  * Basic Orion init functions used early by machine-setup.
  */
-
 void orion5x_map_io(void);
 void orion5x_init_irq(void);
 void orion5x_init(void);
@@ -23,15 +25,22 @@ void orion5x_setup_dev1_win(u32 base, u32 size);
 void orion5x_setup_dev2_win(u32 base, u32 size);
 void orion5x_setup_pcie_wa_win(u32 base, u32 size);
 
+void orion5x_ehci0_init(void);
+void orion5x_ehci1_init(void);
+void orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data);
+void orion5x_i2c_init(void);
+void orion5x_sata_init(struct mv_sata_platform_data *sata_data);
+void orion5x_uart0_init(void);
+void orion5x_uart1_init(void);
+
 /*
- * Shared code used internally by other Orion core functions.
- * (/mach-orion/pci.c)
+ * PCIe/PCI functions.
  */
-
-struct pci_sys_data;
 struct pci_bus;
+struct pci_sys_data;
 
 void orion5x_pcie_id(u32 *dev, u32 *rev);
+void orion5x_pci_set_cardbus_mode(void);
 int orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys);
 struct pci_bus *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys);
 int orion5x_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin);
@@ -40,26 +49,9 @@ int orion5x_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin);
  * Valid GPIO pins according to MPP setup, used by machine-setup.
  * (/mach-orion/gpio.c).
  */
-
-void orion5x_gpio_set_valid_pins(u32 pins);
+void orion5x_gpio_set_valid(unsigned pin, int valid);
 void gpio_display(void);        /* debug */
 
-/*
- * Pull in Orion Ethernet platform_data, used by machine-setup
- */
-
-struct mv643xx_eth_platform_data;
-
-void orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data);
-
-/*
- * Orion Sata platform_data, used by machine-setup
- */
-
-struct mv_sata_platform_data;
-
-void orion5x_sata_init(struct mv_sata_platform_data *sata_data);
-
 struct machine_desc;
 struct meminfo;
 struct tag;
diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c
index 44c64342dacb..88405e74e5e3 100644
--- a/arch/arm/mach-orion5x/db88f5281-setup.c
+++ b/arch/arm/mach-orion5x/db88f5281-setup.c
@@ -27,6 +27,7 @@
 #include <asm/arch/orion5x.h>
 #include <asm/plat-orion/orion_nand.h>
 #include "common.h"
+#include "mpp.h"
 
 /*****************************************************************************
  * DB-88F5281 on board devices
@@ -86,7 +87,7 @@ static struct platform_device db88f5281_boot_flash = {
         .name           = "physmap-flash",
         .id             = 0,
         .dev            = {
-                .platform_data = &db88f5281_boot_flash_data,
+                .platform_data  = &db88f5281_boot_flash_data,
         },
         .num_resources  = 1,
         .resource       = &db88f5281_boot_flash_resource,
@@ -110,7 +111,7 @@ static struct platform_device db88f5281_nor_flash = {
         .name           = "physmap-flash",
         .id             = 1,
         .dev            = {
-                .platform_data = &db88f5281_nor_flash_data,
+                .platform_data  = &db88f5281_nor_flash_data,
         },
         .num_resources  = 1,
         .resource       = &db88f5281_nor_flash_resource,
@@ -125,18 +126,15 @@ static struct mtd_partition db88f5281_nand_parts[] = {
                 .name = "kernel",
                 .offset = 0,
                 .size = SZ_2M,
-        },
-        {
+        }, {
                 .name = "root",
                 .offset = SZ_2M,
                 .size = (SZ_16M - SZ_2M),
-        },
-        {
+        }, {
                 .name = "user",
                 .offset = SZ_16M,
                 .size = SZ_8M,
-        },
-        {
+        }, {
                 .name = "recovery",
                 .offset = (SZ_16M + SZ_8M),
                 .size = SZ_8M,
@@ -288,7 +286,6 @@ subsys_initcall(db88f5281_pci_init);
  ****************************************************************************/
 static struct mv643xx_eth_platform_data db88f5281_eth_data = {
         .phy_addr       = 8,
-        .force_phy_addr = 1,
 };
 
 /*****************************************************************************
@@ -301,11 +298,28 @@ static struct i2c_board_info __initdata db88f5281_i2c_rtc = {
 /*****************************************************************************
  * General Setup
  ****************************************************************************/
-
-static struct platform_device *db88f5281_devs[] __initdata = {
-        &db88f5281_boot_flash,
-        &db88f5281_nor_flash,
-        &db88f5281_nand_flash,
+static struct orion5x_mpp_mode db88f5281_mpp_modes[] __initdata = {
+        {  0, MPP_GPIO },               /* USB Over Current */
+        {  1, MPP_GPIO },               /* USB Vbat input */
+        {  2, MPP_PCI_ARB },            /* PCI_REQn[2] */
+        {  3, MPP_PCI_ARB },            /* PCI_GNTn[2] */
+        {  4, MPP_PCI_ARB },            /* PCI_REQn[3] */
+        {  5, MPP_PCI_ARB },            /* PCI_GNTn[3] */
+        {  6, MPP_GPIO },               /* JP0, CON17.2 */
+        {  7, MPP_GPIO },               /* JP1, CON17.1 */
+        {  8, MPP_GPIO },               /* JP2, CON11.2 */
+        {  9, MPP_GPIO },               /* JP3, CON11.3 */
+        { 10, MPP_GPIO },               /* RTC int */
+        { 11, MPP_GPIO },               /* Baud Rate Generator */
+        { 12, MPP_GPIO },               /* PCI int 1 */
+        { 13, MPP_GPIO },               /* PCI int 2 */
+        { 14, MPP_NAND },               /* NAND_REn[2] */
+        { 15, MPP_NAND },               /* NAND_WEn[2] */
+        { 16, MPP_UART },               /* UART1_RX */
+        { 17, MPP_UART },               /* UART1_TX */
+        { 18, MPP_UART },               /* UART1_CTSn */
+        { 19, MPP_UART },               /* UART1_RTSn */
+        { -1 },
 };
 
 static void __init db88f5281_init(void)
@@ -315,39 +329,31 @@ static void __init db88f5281_init(void)
          */
         orion5x_init();
 
+        orion5x_mpp_conf(db88f5281_mpp_modes);
+        writel(0, MPP_DEV_CTRL);                /* DEV_D[31:16] */
+
         /*
-         * Setup the CPU address decode windows for our on-board devices
+         * Configure peripherals.
          */
+        orion5x_ehci0_init();
+        orion5x_eth_init(&db88f5281_eth_data);
+        orion5x_i2c_init();
+        orion5x_uart0_init();
+        orion5x_uart1_init();
+
         orion5x_setup_dev_boot_win(DB88F5281_NOR_BOOT_BASE,
                                 DB88F5281_NOR_BOOT_SIZE);
+        platform_device_register(&db88f5281_boot_flash);
+
         orion5x_setup_dev0_win(DB88F5281_7SEG_BASE, DB88F5281_7SEG_SIZE);
-        orion5x_setup_dev1_win(DB88F5281_NOR_BASE, DB88F5281_NOR_SIZE);
-        orion5x_setup_dev2_win(DB88F5281_NAND_BASE, DB88F5281_NAND_SIZE);
 
-        /*
-         * Setup Multiplexing Pins:
-         * MPP0: GPIO (USB Over Current)        MPP1: GPIO (USB Vbat input)
-         * MPP2: PCI_REQn[2]                    MPP3: PCI_GNTn[2]
-         * MPP4: PCI_REQn[3]                    MPP5: PCI_GNTn[3]
-         * MPP6: GPIO (JP0, CON17.2)            MPP7: GPIO (JP1, CON17.1)
-         * MPP8: GPIO (JP2, CON11.2)            MPP9: GPIO (JP3, CON11.3)
-         * MPP10: GPIO (RTC int)                MPP11: GPIO (Baud Rate Generator)
-         * MPP12: GPIO (PCI int 1)              MPP13: GPIO (PCI int 2)
-         * MPP14: NAND_REn[2]                   MPP15: NAND_WEn[2]
-         * MPP16: UART1_RX                      MPP17: UART1_TX
-         * MPP18: UART1_CTS                     MPP19: UART1_RTS
-         * MPP-DEV: DEV_D[16:31]
-         */
-        orion5x_write(MPP_0_7_CTRL, 0x00222203);
-        orion5x_write(MPP_8_15_CTRL, 0x44000000);
-        orion5x_write(MPP_16_19_CTRL, 0);
-        orion5x_write(MPP_DEV_CTRL, 0);
+        orion5x_setup_dev1_win(DB88F5281_NOR_BASE, DB88F5281_NOR_SIZE);
+        platform_device_register(&db88f5281_nor_flash);
 
-        orion5x_gpio_set_valid_pins(0x00003fc3);
+        orion5x_setup_dev2_win(DB88F5281_NAND_BASE, DB88F5281_NAND_SIZE);
+        platform_device_register(&db88f5281_nand_flash);
 
-        platform_add_devices(db88f5281_devs, ARRAY_SIZE(db88f5281_devs));
         i2c_register_board_info(0, &db88f5281_i2c_rtc, 1);
-        orion5x_eth_init(&db88f5281_eth_data);
 }
 
 MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board")
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index 27ce967ab9e5..3791ca6f001a 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -27,6 +27,7 @@
 #include <asm/mach/pci.h>
 #include <asm/arch/orion5x.h>
 #include "common.h"
+#include "mpp.h"
 
 #define DNS323_GPIO_LED_RIGHT_AMBER     1
 #define DNS323_GPIO_LED_LEFT_AMBER      2
@@ -52,8 +53,6 @@ static int __init dns323_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
         if (irq != -1)
                 return irq;
 
-        pr_err("%s: requested mapping for unknown device\n", __func__);
-
         return -1;
 }
 
@@ -81,7 +80,6 @@ subsys_initcall(dns323_pci_init);
 
 static struct mv643xx_eth_platform_data dns323_eth_data = {
         .phy_addr = 8,
-        .force_phy_addr = 1,
 };
 
 /****************************************************************************
@@ -119,7 +117,7 @@ static struct mtd_partition dns323_partitions[] = {
                 .name   = "u-boot",
                 .size   = 0x00030000,
                 .offset = 0x007d0000,
-        }
+        },
 };
 
 static struct physmap_flash_data dns323_nor_flash_data = {
@@ -137,7 +135,9 @@ static struct resource dns323_nor_flash_resource = {
 static struct platform_device dns323_nor_flash = {
         .name           = "physmap-flash",
         .id             = 0,
-        .dev            = { .platform_data = &dns323_nor_flash_data, },
+        .dev            = {
+                .platform_data  = &dns323_nor_flash_data,
+        },
         .resource       = &dns323_nor_flash_resource,
         .num_resources  = 1,
 };
@@ -170,7 +170,9 @@ static struct gpio_led_platform_data dns323_led_data = {
 static struct platform_device dns323_gpio_leds = {
         .name           = "leds-gpio",
         .id             = -1,
-        .dev            = { .platform_data = &dns323_led_data, },
+        .dev            = {
+                .platform_data  = &dns323_led_data,
+        },
 };
 
 /****************************************************************************
@@ -183,35 +185,53 @@ static struct gpio_keys_button dns323_buttons[] = {
                 .gpio           = DNS323_GPIO_KEY_RESET,
                 .desc           = "Reset Button",
                 .active_low     = 1,
-        },
-        {
+        }, {
                 .code           = KEY_POWER,
                 .gpio           = DNS323_GPIO_KEY_POWER,
                 .desc           = "Power Button",
                 .active_low     = 1,
-        }
+        },
 };
 
 static struct gpio_keys_platform_data dns323_button_data = {
         .buttons        = dns323_buttons,
-        .nbuttons       = ARRAY_SIZE(dns323_buttons),
+        .nbuttons       = ARRAY_SIZE(dns323_buttons),
 };
 
 static struct platform_device dns323_button_device = {
         .name           = "gpio-keys",
         .id             = -1,
         .num_resources  = 0,
-        .dev            = { .platform_data  = &dns323_button_data, },
+        .dev            = {
+                .platform_data  = &dns323_button_data,
+        },
 };
 
 /****************************************************************************
  * General Setup
  */
-
-static struct platform_device *dns323_plat_devices[] __initdata = {
-        &dns323_nor_flash,
-        &dns323_gpio_leds,
-        &dns323_button_device,
+static struct orion5x_mpp_mode dns323_mpp_modes[] __initdata = {
+        {  0, MPP_PCIE_RST_OUTn },
+        {  1, MPP_GPIO },               /* right amber LED (sata ch0) */
+        {  2, MPP_GPIO },               /* left amber LED (sata ch1) */
+        {  3, MPP_UNUSED },
+        {  4, MPP_GPIO },               /* power button LED */
+        {  5, MPP_GPIO },               /* power button LED */
+        {  6, MPP_GPIO },               /* GMT G751-2f overtemp */
+        {  7, MPP_GPIO },               /* M41T80 nIRQ/OUT/SQW */
+        {  8, MPP_GPIO },               /* triggers power off */
+        {  9, MPP_GPIO },               /* power button switch */
+        { 10, MPP_GPIO },               /* reset button switch */
+        { 11, MPP_UNUSED },
+        { 12, MPP_UNUSED },
+        { 13, MPP_UNUSED },
+        { 14, MPP_UNUSED },
+        { 15, MPP_UNUSED },
+        { 16, MPP_UNUSED },
+        { 17, MPP_UNUSED },
+        { 18, MPP_UNUSED },
+        { 19, MPP_UNUSED },
+        { -1 },
 };
 
 /*
@@ -225,17 +245,15 @@ static struct platform_device *dns323_plat_devices[] __initdata = {
 static struct i2c_board_info __initdata dns323_i2c_devices[] = {
         {
                 I2C_BOARD_INFO("g760a", 0x3e),
-        },
 #if 0
         /* this entry requires the new-style driver model lm75 driver,
          * for the meantime "insmod lm75.ko force_lm75=0,0x48" is needed */
-        {
+        }, {
                 I2C_BOARD_INFO("g751", 0x48),
-        },
 #endif
-        {
+        }, {
                 I2C_BOARD_INFO("m41t80", 0x68),
-        }
+        },
 };
 
 /* DNS-323 specific power off method */
@@ -250,62 +268,35 @@ static void __init dns323_init(void)
         /* Setup basic Orion functions. Need to be called early. */
         orion5x_init();
 
+        orion5x_mpp_conf(dns323_mpp_modes);
+        writel(0, MPP_DEV_CTRL);                /* DEV_D[31:16] */
+
+        /*
+         * Configure peripherals.
+         */
+        orion5x_ehci0_init();
+        orion5x_eth_init(&dns323_eth_data);
+        orion5x_i2c_init();
+        orion5x_uart0_init();
+
         /* setup flash mapping
          * CS3 holds a 8 MB Spansion S29GL064M90TFIR4
          */
         orion5x_setup_dev_boot_win(DNS323_NOR_BOOT_BASE, DNS323_NOR_BOOT_SIZE);
+        platform_device_register(&dns323_nor_flash);
 
-        /* DNS-323 has a Marvell 88X7042 SATA controller attached via PCIe
-         *
-         * Open a special address decode windows for the PCIe WA.
-         */
-        orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE,
-                                ORION5X_PCIE_WA_SIZE);
-
-        /* set MPP to 0 as D-Link's 2.6.12.6 kernel did */
-        orion5x_write(MPP_0_7_CTRL, 0);
-        orion5x_write(MPP_8_15_CTRL, 0);
-        orion5x_write(MPP_16_19_CTRL, 0);
-        orion5x_write(MPP_DEV_CTRL, 0);
-
-        /* Define used GPIO pins
-
-          GPIO Map:
-
-          |  0 |     | PEX_RST_OUT (not controlled by GPIO)
-          |  1 | Out | right amber LED (= sata ch0 LED)  (low-active)
-          |  2 | Out | left  amber LED (= sata ch1 LED)  (low-active)
-          |  3 | Out | //unknown//
-          |  4 | Out | power button LED (low-active, together with pin #5)
-          |  5 | Out | power button LED (low-active, together with pin #4)
-          |  6 | In  | GMT G751-2f overtemp. shutdown signal (low-active)
-          |  7 | In  | M41T80 nIRQ/OUT/SQW signal
-          |  8 | Out | triggers power off (high-active)
-          |  9 | In  | power button switch (low-active)
-          | 10 | In  | reset button switch (low-active)
-          | 11 | Out | //unknown//
-          | 12 | Out | //unknown//
-          | 13 | Out | //unknown//
-          | 14 | Out | //unknown//
-          | 15 | Out | //unknown//
-        */
-        orion5x_gpio_set_valid_pins(0x07f6);
-
-        /* register dns323 specific power-off method */
-        if ((gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0)
-            || (gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0))
-                pr_err("DNS323: failed to setup power-off GPIO\n");
-
-        pm_power_off = dns323_power_off;
+        platform_device_register(&dns323_gpio_leds);
 
-        /* register flash and other platform devices */
-        platform_add_devices(dns323_plat_devices,
-                             ARRAY_SIZE(dns323_plat_devices));
+        platform_device_register(&dns323_button_device);
 
         i2c_register_board_info(0, dns323_i2c_devices,
                                 ARRAY_SIZE(dns323_i2c_devices));
 
-        orion5x_eth_init(&dns323_eth_data);
+        /* register dns323 specific power-off method */
+        if (gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0 ||
+            gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0)
+                pr_err("DNS323: failed to setup power-off GPIO\n");
+        pm_power_off = dns323_power_off;
 }
 
 /* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */
diff --git a/arch/arm/mach-orion5x/gpio.c b/arch/arm/mach-orion5x/gpio.c
index 8108c316c426..d09797990f41 100644
--- a/arch/arm/mach-orion5x/gpio.c
+++ b/arch/arm/mach-orion5x/gpio.c
@@ -24,9 +24,12 @@ static DEFINE_SPINLOCK(gpio_lock);
 static unsigned long gpio_valid[BITS_TO_LONGS(GPIO_MAX)];
 static const char *gpio_label[GPIO_MAX];  /* non null for allocated GPIOs */
 
-void __init orion5x_gpio_set_valid_pins(u32 pins)
+void __init orion5x_gpio_set_valid(unsigned pin, int valid)
 {
-        gpio_valid[0] = pins;
+        if (valid)
+                __set_bit(pin, gpio_valid);
+        else
+                __clear_bit(pin, gpio_valid);
 }
 
 /*
@@ -93,10 +96,10 @@ int gpio_get_value(unsigned pin)
 {
         int val, mask = 1 << pin;
 
-        if (orion5x_read(GPIO_IO_CONF) & mask)
-                val = orion5x_read(GPIO_DATA_IN) ^ orion5x_read(GPIO_IN_POL);
+        if (readl(GPIO_IO_CONF) & mask)
+                val = readl(GPIO_DATA_IN) ^ readl(GPIO_IN_POL);
         else
-                val = orion5x_read(GPIO_OUT);
+                val = readl(GPIO_OUT);
 
         return val & mask;
 }
@@ -188,39 +191,39 @@ void gpio_display(void)
                         printk("GPIO, free\n");
                 } else {
                         printk("GPIO, used by %s, ", gpio_label[i]);
-                        if (orion5x_read(GPIO_IO_CONF) & (1 << i)) {
+                        if (readl(GPIO_IO_CONF) & (1 << i)) {
                                 printk("input, active %s, level %s, edge %s\n",
-                                ((orion5x_read(GPIO_IN_POL) >> i) & 1) ? "low" : "high",
-                                ((orion5x_read(GPIO_LEVEL_MASK) >> i) & 1) ? "enabled" : "masked",
-                                ((orion5x_read(GPIO_EDGE_MASK) >> i) & 1) ? "enabled" : "masked");
+                                ((readl(GPIO_IN_POL) >> i) & 1) ? "low" : "high",
+                                ((readl(GPIO_LEVEL_MASK) >> i) & 1) ? "enabled" : "masked",
+                                ((readl(GPIO_EDGE_MASK) >> i) & 1) ? "enabled" : "masked");
                         } else {
-                                printk("output, val=%d\n", (orion5x_read(GPIO_OUT) >> i) & 1);
+                                printk("output, val=%d\n", (readl(GPIO_OUT) >> i) & 1);
                         }
                 }
         }
 
         printk(KERN_DEBUG "MPP_0_7_CTRL (0x%08x) = 0x%08x\n",
-                                MPP_0_7_CTRL, orion5x_read(MPP_0_7_CTRL));
+                                MPP_0_7_CTRL, readl(MPP_0_7_CTRL));
         printk(KERN_DEBUG "MPP_8_15_CTRL (0x%08x) = 0x%08x\n",
-                                MPP_8_15_CTRL, orion5x_read(MPP_8_15_CTRL));
+                                MPP_8_15_CTRL, readl(MPP_8_15_CTRL));
         printk(KERN_DEBUG "MPP_16_19_CTRL (0x%08x) = 0x%08x\n",
-                                MPP_16_19_CTRL, orion5x_read(MPP_16_19_CTRL));
+                                MPP_16_19_CTRL, readl(MPP_16_19_CTRL));
         printk(KERN_DEBUG "MPP_DEV_CTRL (0x%08x) = 0x%08x\n",
-                                MPP_DEV_CTRL, orion5x_read(MPP_DEV_CTRL));
+                                MPP_DEV_CTRL, readl(MPP_DEV_CTRL));
         printk(KERN_DEBUG "GPIO_OUT (0x%08x) = 0x%08x\n",
-                                GPIO_OUT, orion5x_read(GPIO_OUT));
+                                GPIO_OUT, readl(GPIO_OUT));
         printk(KERN_DEBUG "GPIO_IO_CONF (0x%08x) = 0x%08x\n",
-                                GPIO_IO_CONF, orion5x_read(GPIO_IO_CONF));
+                                GPIO_IO_CONF, readl(GPIO_IO_CONF));
         printk(KERN_DEBUG "GPIO_BLINK_EN (0x%08x) = 0x%08x\n",
-                                GPIO_BLINK_EN, orion5x_read(GPIO_BLINK_EN));
+                                GPIO_BLINK_EN, readl(GPIO_BLINK_EN));
         printk(KERN_DEBUG "GPIO_IN_POL (0x%08x) = 0x%08x\n",
-                                GPIO_IN_POL, orion5x_read(GPIO_IN_POL));
+                                GPIO_IN_POL, readl(GPIO_IN_POL));
         printk(KERN_DEBUG "GPIO_DATA_IN (0x%08x) = 0x%08x\n",
-                                GPIO_DATA_IN, orion5x_read(GPIO_DATA_IN));
+                                GPIO_DATA_IN, readl(GPIO_DATA_IN));
         printk(KERN_DEBUG "GPIO_LEVEL_MASK (0x%08x) = 0x%08x\n",
-                                GPIO_LEVEL_MASK, orion5x_read(GPIO_LEVEL_MASK));
+                                GPIO_LEVEL_MASK, readl(GPIO_LEVEL_MASK));
         printk(KERN_DEBUG "GPIO_EDGE_CAUSE (0x%08x) = 0x%08x\n",
-                                GPIO_EDGE_CAUSE, orion5x_read(GPIO_EDGE_CAUSE));
+                                GPIO_EDGE_CAUSE, readl(GPIO_EDGE_CAUSE));
         printk(KERN_DEBUG "GPIO_EDGE_MASK (0x%08x) = 0x%08x\n",
-                                GPIO_EDGE_MASK, orion5x_read(GPIO_EDGE_MASK));
+                                GPIO_EDGE_MASK, readl(GPIO_EDGE_MASK));
 }
diff --git a/arch/arm/mach-orion5x/irq.c b/arch/arm/mach-orion5x/irq.c
index dd21f38c5d37..e2a0084ab4a3 100644
--- a/arch/arm/mach-orion5x/irq.c
+++ b/arch/arm/mach-orion5x/irq.c
@@ -82,7 +82,7 @@ static int orion5x_gpio_set_irq_type(u32 irq, u32 type)
         int pin = irq_to_gpio(irq);
         struct irq_desc *desc;
 
-        if ((orion5x_read(GPIO_IO_CONF) & (1 << pin)) == 0) {
+        if ((readl(GPIO_IO_CONF) & (1 << pin)) == 0) {
                 printk(KERN_ERR "orion5x_gpio_set_irq_type failed "
                                 "(irq %d, pin %d).\n", irq, pin);
                 return -EINVAL;
@@ -117,7 +117,7 @@ static int orion5x_gpio_set_irq_type(u32 irq, u32 type)
                 /*
                  * set initial polarity based on current input level
                  */
-                if ((orion5x_read(GPIO_IN_POL) ^ orion5x_read(GPIO_DATA_IN))
+                if ((readl(GPIO_IN_POL) ^ readl(GPIO_DATA_IN))
                     & (1 << pin))
                         orion5x_setbits(GPIO_IN_POL, (1 << pin)); /* falling */
                 else
@@ -149,8 +149,8 @@ static void orion5x_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 
         BUG_ON(irq < IRQ_ORION5X_GPIO_0_7 || irq > IRQ_ORION5X_GPIO_24_31);
         offs = (irq - IRQ_ORION5X_GPIO_0_7) * 8;
-        cause = (orion5x_read(GPIO_DATA_IN) & orion5x_read(GPIO_LEVEL_MASK)) |
-                (orion5x_read(GPIO_EDGE_CAUSE) & orion5x_read(GPIO_EDGE_MASK));
+        cause = (readl(GPIO_DATA_IN) & readl(GPIO_LEVEL_MASK)) |
+                (readl(GPIO_EDGE_CAUSE) & readl(GPIO_EDGE_MASK));
 
         for (pin = offs; pin < offs + 8; pin++) {
                 if (cause & (1 << pin)) {
@@ -158,9 +158,9 @@ static void orion5x_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
                         desc = irq_desc + irq;
                         if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE) {
                                 /* Swap polarity (race with GPIO line) */
-                                u32 polarity = orion5x_read(GPIO_IN_POL);
+                                u32 polarity = readl(GPIO_IN_POL);
                                 polarity ^= 1 << pin;
-                                orion5x_write(GPIO_IN_POL, polarity);
+                                writel(polarity, GPIO_IN_POL);
                         }
                         desc_handle_irq(irq, desc);
                 }
@@ -175,9 +175,9 @@ static void __init orion5x_init_gpio_irq(void)
         /*
          * Mask and clear GPIO IRQ interrupts
          */
-        orion5x_write(GPIO_LEVEL_MASK, 0x0);
-        orion5x_write(GPIO_EDGE_MASK, 0x0);
-        orion5x_write(GPIO_EDGE_CAUSE, 0x0);
+        writel(0x0, GPIO_LEVEL_MASK);
+        writel(0x0, GPIO_EDGE_MASK);
+        writel(0x0, GPIO_EDGE_CAUSE);
 
         /*
          * Register chained level handlers for GPIO IRQs by default.
diff --git a/arch/arm/mach-orion5x/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c
index f5074b877b7f..84feac4a1fe2 100644
--- a/arch/arm/mach-orion5x/kurobox_pro-setup.c
+++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c
@@ -13,10 +13,12 @@
 #include <linux/platform_device.h>
 #include <linux/pci.h>
 #include <linux/irq.h>
+#include <linux/delay.h>
 #include <linux/mtd/physmap.h>
 #include <linux/mtd/nand.h>
 #include <linux/mv643xx_eth.h>
 #include <linux/i2c.h>
+#include <linux/serial_reg.h>
 #include <linux/ata_platform.h>
 #include <asm/mach-types.h>
 #include <asm/gpio.h>
@@ -25,6 +27,7 @@
 #include <asm/arch/orion5x.h>
 #include <asm/plat-orion/orion_nand.h>
 #include "common.h"
+#include "mpp.h"
 
 /*****************************************************************************
  * KUROBOX-PRO Info
@@ -53,13 +56,11 @@ static struct mtd_partition kurobox_pro_nand_parts[] = {
                 .name   = "uImage",
                 .offset = 0,
                 .size   = SZ_4M,
-        },
-        {
+        }, {
                 .name   = "rootfs",
                 .offset = SZ_4M,
                 .size   = SZ_64M,
-        },
-        {
+        }, {
                 .name   = "extra",
                 .offset = SZ_4M + SZ_64M,
                 .size   = SZ_256M - (SZ_4M + SZ_64M),
@@ -132,8 +133,6 @@ static int __init kurobox_pro_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
         /*
          * PCI isn't used on the Kuro
          */
-        printk(KERN_ERR "kurobox_pro_pci_map_irq failed, unknown bus\n");
-
         return -1;
 }
 
@@ -161,7 +160,6 @@ subsys_initcall(kurobox_pro_pci_init);
 
 static struct mv643xx_eth_platform_data kurobox_pro_eth_data = {
         .phy_addr       = 8,
-        .force_phy_addr = 1,
 };
 
 /*****************************************************************************
@@ -175,12 +173,169 @@ static struct i2c_board_info __initdata kurobox_pro_i2c_rtc = {
  * SATA
  ****************************************************************************/
 static struct mv_sata_platform_data kurobox_pro_sata_data = {
-        .n_ports        = 2,
+        .n_ports        = 2,
 };
 
 /*****************************************************************************
+ * Kurobox Pro specific power off method via UART1-attached microcontroller
+ ****************************************************************************/
+
+#define UART1_REG(x)    (UART1_VIRT_BASE + ((UART_##x) << 2))
+
+static int kurobox_pro_miconread(unsigned char *buf, int count)
+{
+        int i;
+        int timeout;
+
+        for (i = 0; i < count; i++) {
+                timeout = 10;
+
+                while (!(readl(UART1_REG(LSR)) & UART_LSR_DR)) {
+                        if (--timeout == 0)
+                                break;
+                        udelay(1000);
+                }
+
+                if (timeout == 0)
+                        break;
+                buf[i] = readl(UART1_REG(RX));
+        }
+
+        /* return read bytes */
+        return i;
+}
+
+static int kurobox_pro_miconwrite(const unsigned char *buf, int count)
+{
+        int i = 0;
+
+        while (count--) {
+                while (!(readl(UART1_REG(LSR)) & UART_LSR_THRE))
+                        barrier();
+                writel(buf[i++], UART1_REG(TX));
+        }
+
+        return 0;
+}
+
+static int kurobox_pro_miconsend(const unsigned char *data, int count)
+{
+        int i;
+        unsigned char checksum = 0;
+        unsigned char recv_buf[40];
+        unsigned char send_buf[40];
+        unsigned char correct_ack[3];
+        int retry = 2;
+
+        /* Generate checksum */
+        for (i = 0; i < count; i++)
+                checksum -=  data[i];
+
+        do {
+                /* Send data */
+                kurobox_pro_miconwrite(data, count);
+
+                /* send checksum */
+                kurobox_pro_miconwrite(&checksum, 1);
+
+                if (kurobox_pro_miconread(recv_buf, sizeof(recv_buf)) <= 3) {
+                        printk(KERN_ERR ">%s: receive failed.\n", __func__);
+
+                        /* send preamble to clear the receive buffer */
+                        memset(&send_buf, 0xff, sizeof(send_buf));
+                        kurobox_pro_miconwrite(send_buf, sizeof(send_buf));
+
+                        /* make dummy reads */
+                        mdelay(100);
+                        kurobox_pro_miconread(recv_buf, sizeof(recv_buf));
+                } else {
+                        /* Generate expected ack */
+                        correct_ack[0] = 0x01;
+                        correct_ack[1] = data[1];
+                        correct_ack[2] = 0x00;
+
+                        /* checksum Check */
+                        if ((recv_buf[0] + recv_buf[1] + recv_buf[2] +
+                             recv_buf[3]) & 0xFF) {
+                                printk(KERN_ERR ">%s: Checksum Error : "
+                                        "Received data[%02x, %02x, %02x, %02x]"
+                                        "\n", __func__, recv_buf[0],
+                                        recv_buf[1], recv_buf[2], recv_buf[3]);
+                        } else {
+                                /* Check Received Data */
+                                if (correct_ack[0] == recv_buf[0] &&
+                                    correct_ack[1] == recv_buf[1] &&
+                                    correct_ack[2] == recv_buf[2]) {
+                                        /* Interval for next command */
+                                        mdelay(10);
+
+                                        /* Receive ACK */
+                                        return 0;
+                                }
+                        }
+                        /* Received NAK or illegal Data */
+                        printk(KERN_ERR ">%s: Error : NAK or Illegal Data "
+                                        "Received\n", __func__);
+                }
+        } while (retry--);
+
+        /* Interval for next command */
+        mdelay(10);
+
+        return -1;
+}
+
+static void kurobox_pro_power_off(void)
+{
+        const unsigned char watchdogkill[]      = {0x01, 0x35, 0x00};
+        const unsigned char shutdownwait[]      = {0x00, 0x0c};
+        const unsigned char poweroff[]          = {0x00, 0x06};
+        /* 38400 baud divisor */
+        const unsigned divisor = ((ORION5X_TCLK + (8 * 38400)) / (16 * 38400));
+
+        pr_info("%s: triggering power-off...\n", __func__);
+
+        /* hijack uart1 and reset into sane state (38400,8n1,even parity) */
+        writel(0x83, UART1_REG(LCR));
+        writel(divisor & 0xff, UART1_REG(DLL));
+        writel((divisor >> 8) & 0xff, UART1_REG(DLM));
+        writel(0x1b, UART1_REG(LCR));
+        writel(0x00, UART1_REG(IER));
+        writel(0x07, UART1_REG(FCR));
+        writel(0x00, UART1_REG(MCR));
+
+        /* Send the commands to shutdown the Kurobox Pro */
+        kurobox_pro_miconsend(watchdogkill, sizeof(watchdogkill)) ;
+        kurobox_pro_miconsend(shutdownwait, sizeof(shutdownwait)) ;
+        kurobox_pro_miconsend(poweroff, sizeof(poweroff));
+}
+
+/*****************************************************************************
  * General Setup
  ****************************************************************************/
+static struct orion5x_mpp_mode kurobox_pro_mpp_modes[] __initdata = {
+        {  0, MPP_UNUSED },
+        {  1, MPP_UNUSED },
+        {  2, MPP_GPIO },               /* GPIO Micon */
+        {  3, MPP_GPIO },               /* GPIO Rtc */
+        {  4, MPP_UNUSED },
+        {  5, MPP_UNUSED },
+        {  6, MPP_NAND },               /* NAND Flash REn */
+        {  7, MPP_NAND },               /* NAND Flash WEn */
+        {  8, MPP_UNUSED },
+        {  9, MPP_UNUSED },
+        { 10, MPP_UNUSED },
+        { 11, MPP_UNUSED },
+        { 12, MPP_SATA_LED },           /* SATA 0 presence */
+        { 13, MPP_SATA_LED },           /* SATA 1 presence */
+        { 14, MPP_SATA_LED },           /* SATA 0 active */
+        { 15, MPP_SATA_LED },           /* SATA 1 active */
+        { 16, MPP_UART },               /* UART1 RXD */
+        { 17, MPP_UART },               /* UART1 TXD */
+        { 18, MPP_UART },               /* UART1 CTSn */
+        { 19, MPP_UART },               /* UART1 RTSn */
+        { -1 },
+};
 
 static void __init kurobox_pro_init(void)
 {
@@ -189,46 +344,33 @@ static void __init kurobox_pro_init(void)
          */
         orion5x_init();
 
-        /*
-         * Setup the CPU address decode windows for our devices
-         */
-        orion5x_setup_dev_boot_win(KUROBOX_PRO_NOR_BOOT_BASE,
-                                KUROBOX_PRO_NOR_BOOT_SIZE);
-        orion5x_setup_dev0_win(KUROBOX_PRO_NAND_BASE, KUROBOX_PRO_NAND_SIZE);
+        orion5x_mpp_conf(kurobox_pro_mpp_modes);
 
         /*
-         * Open a special address decode windows for the PCIe WA.
+         * Configure peripherals.
          */
-        orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE,
-                                ORION5X_PCIE_WA_SIZE);
-
-        /*
-         * Setup Multiplexing Pins --
-         * MPP[0-1] Not used
-         * MPP[2] GPIO Micon
-         * MPP[3] GPIO RTC
-         * MPP[4-5] Not used
-         * MPP[6] Nand Flash REn
-         * MPP[7] Nand Flash WEn
-         * MPP[8-11] Not used
-         * MPP[12] SATA 0 presence Indication
-         * MPP[13] SATA 1 presence Indication
-         * MPP[14] SATA 0 active Indication
-         * MPP[15] SATA 1 active indication
-         * MPP[16-19] Not used
-         */
-        orion5x_write(MPP_0_7_CTRL, 0x44220003);
-        orion5x_write(MPP_8_15_CTRL, 0x55550000);
-        orion5x_write(MPP_16_19_CTRL, 0x0);
-
-        orion5x_gpio_set_valid_pins(0x0000000c);
+        orion5x_ehci0_init();
+        orion5x_ehci1_init();
+        orion5x_eth_init(&kurobox_pro_eth_data);
+        orion5x_i2c_init();
+        orion5x_sata_init(&kurobox_pro_sata_data);
+        orion5x_uart0_init();
+        orion5x_uart1_init();
 
+        orion5x_setup_dev_boot_win(KUROBOX_PRO_NOR_BOOT_BASE,
+                                   KUROBOX_PRO_NOR_BOOT_SIZE);
         platform_device_register(&kurobox_pro_nor_flash);
-        if (machine_is_kurobox_pro())
+
+        if (machine_is_kurobox_pro()) {
+                orion5x_setup_dev0_win(KUROBOX_PRO_NAND_BASE,
+                                       KUROBOX_PRO_NAND_SIZE);
                 platform_device_register(&kurobox_pro_nand_flash);
+        }
+
         i2c_register_board_info(0, &kurobox_pro_i2c_rtc, 1);
-        orion5x_eth_init(&kurobox_pro_eth_data);
-        orion5x_sata_init(&kurobox_pro_sata_data);
+
+        /* register Kurobox Pro specific power-off method */
+        pm_power_off = kurobox_pro_power_off;
 }
 
 #ifdef CONFIG_MACH_KUROBOX_PRO
diff --git a/arch/arm/mach-orion5x/mpp.c b/arch/arm/mach-orion5x/mpp.c
new file mode 100644
index 000000000000..a48cadb01590
--- /dev/null
+++ b/arch/arm/mach-orion5x/mpp.c
@@ -0,0 +1,163 @@
+/*
+ * arch/arm/mach-orion5x/mpp.c
+ *
+ * MPP functions for Marvell Orion 5x SoCs
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mbus.h>
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include "common.h"
+#include "mpp.h"
+
+static int is_5181l(void)
+{
+        u32 dev;
+        u32 rev;
+
+        orion5x_pcie_id(&dev, &rev);
+
+        return !!(dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0);
+}
+
+static int is_5182(void)
+{
+        u32 dev;
+        u32 rev;
+
+        orion5x_pcie_id(&dev, &rev);
+
+        return !!(dev == MV88F5182_DEV_ID);
+}
+
+static int is_5281(void)
+{
+        u32 dev;
+        u32 rev;
+
+        orion5x_pcie_id(&dev, &rev);
+
+        return !!(dev == MV88F5281_DEV_ID);
+}
+
+static int __init determine_type_encoding(int mpp, enum orion5x_mpp_type type)
+{
+        switch (type) {
+        case MPP_UNUSED:
+        case MPP_GPIO:
+                if (mpp == 0)
+                        return 3;
+                if (mpp >= 1 && mpp <= 15)
+                        return 0;
+                if (mpp >= 16 && mpp <= 19) {
+                        if (is_5182())
+                                return 5;
+                        if (type == MPP_UNUSED)
+                                return 0;
+                }
+                return -1;
+
+        case MPP_PCIE_RST_OUTn:
+                if (mpp == 0)
+                        return 0;
+                return -1;
+
+        case MPP_PCI_ARB:
+                if (mpp >= 0 && mpp <= 7)
+                        return 2;
+                return -1;
+
+        case MPP_PCI_PMEn:
+                if (mpp == 2)
+                        return 3;
+                return -1;
+
+        case MPP_GIGE:
+                if (mpp >= 8 && mpp <= 19)
+                        return 1;
+                return -1;
+
+        case MPP_NAND:
+                if (is_5182() || is_5281()) {
+                        if (mpp >= 4 && mpp <= 7)
+                                return 4;
+                        if (mpp >= 12 && mpp <= 17)
+                                return 4;
+                }
+                return -1;
+
+        case MPP_PCI_CLK:
+                if (is_5181l() && mpp >= 6 && mpp <= 7)
+                        return 5;
+                return -1;
+
+        case MPP_SATA_LED:
+                if (is_5182()) {
+                        if (mpp >= 4 && mpp <= 7)
+                                return 5;
+                        if (mpp >= 12 && mpp <= 15)
+                                return 5;
+                }
+                return -1;
+
+        case MPP_UART:
+                if (mpp >= 16 && mpp <= 19)
+                        return 0;
+                return -1;
+        }
+
+        printk(KERN_INFO "unknown MPP type %d\n", type);
+
+        return -1;
+}
+
+void __init orion5x_mpp_conf(struct orion5x_mpp_mode *mode)
+{
+        u32 mpp_0_7_ctrl = readl(MPP_0_7_CTRL);
+        u32 mpp_8_15_ctrl = readl(MPP_8_15_CTRL);
+        u32 mpp_16_19_ctrl = readl(MPP_16_19_CTRL);
+
+        while (mode->mpp >= 0) {
+                u32 *reg;
+                int num_type;
+                int shift;
+
+                if (mode->mpp >= 0 && mode->mpp <= 7)
+                        reg = &mpp_0_7_ctrl;
+                else if (mode->mpp >= 8 && mode->mpp <= 15)
+                        reg = &mpp_8_15_ctrl;
+                else if (mode->mpp >= 16 && mode->mpp <= 19)
+                        reg = &mpp_16_19_ctrl;
+                else {
+                        printk(KERN_ERR "orion5x_mpp_conf: invalid MPP "
+                                        "(%d)\n", mode->mpp);
+                        continue;
+                }
+
+                num_type = determine_type_encoding(mode->mpp, mode->type);
+                if (num_type < 0) {
+                        printk(KERN_ERR "orion5x_mpp_conf: invalid MPP "
+                                        "combination (%d, %d)\n", mode->mpp,
+                                        mode->type);
+                        continue;
+                }
+
+                shift = (mode->mpp & 7) << 2;
+                *reg &= ~(0xf << shift);
+                *reg |= (num_type & 0xf) << shift;
+
+                orion5x_gpio_set_valid(mode->mpp, !!(mode->type == MPP_GPIO));
+
+                mode++;
+        }
+
+        writel(mpp_0_7_ctrl, MPP_0_7_CTRL);
+        writel(mpp_8_15_ctrl, MPP_8_15_CTRL);
+        writel(mpp_16_19_ctrl, MPP_16_19_CTRL);
+}
diff --git a/arch/arm/mach-orion5x/mpp.h b/arch/arm/mach-orion5x/mpp.h
new file mode 100644
index 000000000000..290e610dc012
--- /dev/null
+++ b/arch/arm/mach-orion5x/mpp.h
@@ -0,0 +1,74 @@
+#ifndef __ARCH_ORION5X_MPP_H
+#define __ARCH_ORION5X_MPP_H
+
+enum orion5x_mpp_type {
+        /*
+         * This MPP is unused.
+         */
+        MPP_UNUSED,
+
+        /*
+         * This MPP pin is used as a generic GPIO pin.  Valid for
+         * MPPs 0-15 and device bus data pins 16-31.  On 5182, also
+         * valid for MPPs 16-19.
+         */
+        MPP_GPIO,
+
+        /*
+         * This MPP is used as PCIe_RST_OUTn pin.  Valid for
+         * MPP 0 only.
+         */
+        MPP_PCIE_RST_OUTn,
+
+        /*
+         * This MPP is used as PCI arbiter pin (REQn/GNTn).
+         * Valid for MPPs 0-7 only.
+         */
+        MPP_PCI_ARB,
+
+        /*
+         * This MPP is used as PCI_PMEn pin.  Valid for MPP 2 only.
+         */
+        MPP_PCI_PMEn,
+
+        /*
+         * This MPP is used as GigE half-duplex (COL, CRS) or GMII
+         * (RXERR, CRS, TXERR, TXD[7:4], RXD[7:4]) pin.  Valid for
+         * MPPs 8-19 only.
+         */
+        MPP_GIGE,
+
+        /*
+         * This MPP is used as NAND REn/WEn pin.  Valid for MPPs
+         * 4-7 and 12-17 only, and only on the 5181l/5182/5281.
+         */
+        MPP_NAND,
+
+        /*
+         * This MPP is used as a PCI clock output pin.  Valid for
+         * MPPs 6-7 only, and only on the 5181l.
+         */
+        MPP_PCI_CLK,
+
+        /*
+         * This MPP is used as a SATA presence/activity LED.
+         * Valid for MPPs 4-7 and 12-15 only, and only on the 5182.
+         */
+        MPP_SATA_LED,
+
+        /*
+         * This MPP is used as UART1 RXD/TXD/CTSn/RTSn pin.
+         * Valid for MPPs 16-19 only.
+         */
+        MPP_UART,
+};
+
+struct orion5x_mpp_mode {
+        int                     mpp;
+        enum orion5x_mpp_type   type;
+};
+
+void orion5x_mpp_conf(struct orion5x_mpp_mode *mode);
+
+
+#endif
diff --git a/arch/arm/mach-orion5x/mss2-setup.c b/arch/arm/mach-orion5x/mss2-setup.c
new file mode 100644
index 000000000000..7ce9e407d9d1
--- /dev/null
+++ b/arch/arm/mach-orion5x/mss2-setup.c
@@ -0,0 +1,270 @@
+/*
+ * Maxtor Shared Storage II Board Setup
+ *
+ * Maintainer: Sylver Bruneau <sylver.bruneau@googlemail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/pci.h>
+#include <linux/irq.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/leds.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <linux/i2c.h>
+#include <linux/ata_platform.h>
+#include <linux/gpio.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/pci.h>
+#include <asm/arch/orion5x.h>
+#include "common.h"
+#include "mpp.h"
+
+#define MSS2_NOR_BOOT_BASE      0xff800000
+#define MSS2_NOR_BOOT_SIZE      SZ_256K
+
+/*****************************************************************************
+ * Maxtor Shared Storage II Info
+ ****************************************************************************/
+
+/*
+ * Maxtor Shared Storage II hardware :
+ * - Marvell 88F5182-A2 C500
+ * - Marvell 88E1111 Gigabit Ethernet PHY
+ * - RTC M41T81 (@0x68) on I2C bus
+ * - 256KB NOR flash
+ * - 64MB of RAM
+ */
+
+/*****************************************************************************
+ * 256KB NOR Flash on BOOT Device
+ ****************************************************************************/
+
+static struct physmap_flash_data mss2_nor_flash_data = {
+        .width          = 1,
+};
+
+static struct resource mss2_nor_flash_resource = {
+        .flags          = IORESOURCE_MEM,
+        .start          = MSS2_NOR_BOOT_BASE,
+        .end            = MSS2_NOR_BOOT_BASE + MSS2_NOR_BOOT_SIZE - 1,
+};
+
+static struct platform_device mss2_nor_flash = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &mss2_nor_flash_data,
+        },
+        .resource       = &mss2_nor_flash_resource,
+        .num_resources  = 1,
+};
+
+/****************************************************************************
+ * PCI setup
+ ****************************************************************************/
+static int __init mss2_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+        int irq;
+
+        /*
+         * Check for devices with hard-wired IRQs.
+         */
+        irq = orion5x_pci_map_irq(dev, slot, pin);
+        if (irq != -1)
+                return irq;
+
+        return -1;
+}
+
+static struct hw_pci mss2_pci __initdata = {
+        .nr_controllers = 2,
+        .swizzle        = pci_std_swizzle,
+        .setup          = orion5x_pci_sys_setup,
+        .scan           = orion5x_pci_sys_scan_bus,
+        .map_irq        = mss2_pci_map_irq,
+};
+
+static int __init mss2_pci_init(void)
+{
+        if (machine_is_mss2())
+                pci_common_init(&mss2_pci);
+
+        return 0;
+}
+subsys_initcall(mss2_pci_init);
+
+
+/*****************************************************************************
+ * Ethernet
+ ****************************************************************************/
+
+static struct mv643xx_eth_platform_data mss2_eth_data = {
+        .phy_addr       = 8,
+};
+
+/*****************************************************************************
+ * SATA
+ ****************************************************************************/
+
+static struct mv_sata_platform_data mss2_sata_data = {
+        .n_ports        = 2,
+};
+
+/*****************************************************************************
+ * GPIO buttons
+ ****************************************************************************/
+
+#define MSS2_GPIO_KEY_RESET     12
+#define MSS2_GPIO_KEY_POWER     11
+
+static struct gpio_keys_button mss2_buttons[] = {
+        {
+                .code           = KEY_POWER,
+                .gpio           = MSS2_GPIO_KEY_POWER,
+                .desc           = "Power",
+                .active_low     = 1,
+        }, {
+                .code           = KEY_RESTART,
+                .gpio           = MSS2_GPIO_KEY_RESET,
+                .desc           = "Reset",
+                .active_low     = 1,
+        },
+};
+
+static struct gpio_keys_platform_data mss2_button_data = {
+        .buttons        = mss2_buttons,
+        .nbuttons       = ARRAY_SIZE(mss2_buttons),
+};
+
+static struct platform_device mss2_button_device = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &mss2_button_data,
+        },
+};
+
+/*****************************************************************************
+ * RTC m41t81 on I2C bus
+ ****************************************************************************/
+
+#define MSS2_GPIO_RTC_IRQ       3
+
+static struct i2c_board_info __initdata mss2_i2c_rtc = {
+        I2C_BOARD_INFO("m41t81", 0x68),
+};
+
+/*****************************************************************************
+ * MSS2 power off method
+ ****************************************************************************/
+/*
+ * On the Maxtor Shared Storage II, the shutdown process is the following :
+ * - Userland modifies U-boot env to tell U-boot to go idle at next boot
+ * - The board reboots
+ * - U-boot starts and go into an idle mode until the user press "power"
+ */
+static void mss2_power_off(void)
+{
+        u32 reg;
+
+        /*
+         * Enable and issue soft reset
+         */
+        reg = readl(CPU_RESET_MASK);
+        reg |= 1 << 2;
+        writel(reg, CPU_RESET_MASK);
+
+        reg = readl(CPU_SOFT_RESET);
+        reg |= 1;
+        writel(reg, CPU_SOFT_RESET);
+}
+
+/****************************************************************************
+ * General Setup
+ ****************************************************************************/
+static struct orion5x_mpp_mode mss2_mpp_modes[] __initdata = {
+        {  0, MPP_GPIO },               /* Power LED */
+        {  1, MPP_GPIO },               /* Error LED */
+        {  2, MPP_UNUSED },
+        {  3, MPP_GPIO },               /* RTC interrupt */
+        {  4, MPP_GPIO },               /* HDD ind. (Single/Dual)*/
+        {  5, MPP_GPIO },               /* HD0 5V control */
+        {  6, MPP_GPIO },               /* HD0 12V control */
+        {  7, MPP_GPIO },               /* HD1 5V control */
+        {  8, MPP_GPIO },               /* HD1 12V control */
+        {  9, MPP_UNUSED },
+        { 10, MPP_GPIO },               /* Fan control */
+        { 11, MPP_GPIO },               /* Power button */
+        { 12, MPP_GPIO },               /* Reset button */
+        { 13, MPP_UNUSED },
+        { 14, MPP_SATA_LED },           /* SATA 0 active */
+        { 15, MPP_SATA_LED },           /* SATA 1 active */
+        { 16, MPP_UNUSED },
+        { 17, MPP_UNUSED },
+        { 18, MPP_UNUSED },
+        { 19, MPP_UNUSED },
+        { -1 },
+};
+
+static void __init mss2_init(void)
+{
+        /* Setup basic Orion functions. Need to be called early. */
+        orion5x_init();
+
+        orion5x_mpp_conf(mss2_mpp_modes);
+
+        /*
+         * MPP[20] Unused
+         * MPP[21] PCI clock
+         * MPP[22] USB 0 over current
+         * MPP[23] USB 1 over current
+         */
+
+        /*
+         * Configure peripherals.
+         */
+        orion5x_ehci0_init();
+        orion5x_ehci1_init();
+        orion5x_eth_init(&mss2_eth_data);
+        orion5x_i2c_init();
+        orion5x_sata_init(&mss2_sata_data);
+        orion5x_uart0_init();
+
+        orion5x_setup_dev_boot_win(MSS2_NOR_BOOT_BASE, MSS2_NOR_BOOT_SIZE);
+        platform_device_register(&mss2_nor_flash);
+
+        platform_device_register(&mss2_button_device);
+
+        if (gpio_request(MSS2_GPIO_RTC_IRQ, "rtc") == 0) {
+                if (gpio_direction_input(MSS2_GPIO_RTC_IRQ) == 0)
+                        mss2_i2c_rtc.irq = gpio_to_irq(MSS2_GPIO_RTC_IRQ);
+                else
+                        gpio_free(MSS2_GPIO_RTC_IRQ);
+        }
+        i2c_register_board_info(0, &mss2_i2c_rtc, 1);
+
+        /* register mss2 specific power-off method */
+        pm_power_off = mss2_power_off;
+}
+
+MACHINE_START(MSS2, "Maxtor Shared Storage II")
+        /* Maintainer: Sylver Bruneau <sylver.bruneau@googlemail.com> */
+        .phys_io        = ORION5X_REGS_PHYS_BASE,
+        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
+        .boot_params    = 0x00000100,
+        .init_machine   = mss2_init,
+        .map_io         = orion5x_map_io,
+        .init_irq       = orion5x_init_irq,
+        .timer          = &orion5x_timer,
+        .fixup          = tag_fixup_mem32
+MACHINE_END
diff --git a/arch/arm/mach-orion5x/mv2120-setup.c b/arch/arm/mach-orion5x/mv2120-setup.c
new file mode 100644
index 000000000000..55f3b0fdef8b
--- /dev/null
+++ b/arch/arm/mach-orion5x/mv2120-setup.c
@@ -0,0 +1,239 @@
+/*
+ * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org>
+ * Copyright (C) 2008 Martin Michlmayr <tbm@cyrius.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/irq.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/leds.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <linux/i2c.h>
+#include <linux/ata_platform.h>
+#include <asm/mach-types.h>
+#include <asm/gpio.h>
+#include <asm/mach/arch.h>
+#include <asm/arch/orion5x.h>
+#include "common.h"
+#include "mpp.h"
+
+#define MV2120_NOR_BOOT_BASE    0xf4000000
+#define MV2120_NOR_BOOT_SIZE    SZ_512K
+
+#define MV2120_GPIO_RTC_IRQ     3
+#define MV2120_GPIO_KEY_RESET   17
+#define MV2120_GPIO_KEY_POWER   18
+#define MV2120_GPIO_POWER_OFF   19
+
+
+/*****************************************************************************
+ * Ethernet
+ ****************************************************************************/
+static struct mv643xx_eth_platform_data mv2120_eth_data = {
+        .phy_addr       = 8,
+};
+
+static struct mv_sata_platform_data mv2120_sata_data = {
+        .n_ports        = 2,
+};
+
+static struct mtd_partition mv2120_partitions[] = {
+        {
+                .name   = "firmware",
+                .size   = 0x00080000,
+                .offset = 0,
+        },
+};
+
+static struct physmap_flash_data mv2120_nor_flash_data = {
+        .width          = 1,
+        .parts          = mv2120_partitions,
+        .nr_parts       = ARRAY_SIZE(mv2120_partitions)
+};
+
+static struct resource mv2120_nor_flash_resource = {
+        .flags          = IORESOURCE_MEM,
+        .start          = MV2120_NOR_BOOT_BASE,
+        .end            = MV2120_NOR_BOOT_BASE + MV2120_NOR_BOOT_SIZE - 1,
+};
+
+static struct platform_device mv2120_nor_flash = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &mv2120_nor_flash_data,
+        },
+        .resource       = &mv2120_nor_flash_resource,
+        .num_resources  = 1,
+};
+
+static struct gpio_keys_button mv2120_buttons[] = {
+        {
+                .code           = KEY_RESTART,
+                .gpio           = MV2120_GPIO_KEY_RESET,
+                .desc           = "reset",
+                .active_low     = 1,
+        }, {
+                .code           = KEY_POWER,
+                .gpio           = MV2120_GPIO_KEY_POWER,
+                .desc           = "power",
+                .active_low     = 1,
+        },
+};
+
+static struct gpio_keys_platform_data mv2120_button_data = {
+        .buttons        = mv2120_buttons,
+        .nbuttons       = ARRAY_SIZE(mv2120_buttons),
+};
+
+static struct platform_device mv2120_button_device = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .num_resources  = 0,
+        .dev            = {
+                .platform_data  = &mv2120_button_data,
+        },
+};
+
+
+/****************************************************************************
+ * General Setup
+ ****************************************************************************/
+static struct orion5x_mpp_mode mv2120_mpp_modes[] __initdata = {
+        {  0, MPP_GPIO },               /* Sys status LED */
+        {  1, MPP_GPIO },               /* Sys error LED */
+        {  2, MPP_GPIO },               /* OverTemp interrupt */
+        {  3, MPP_GPIO },               /* RTC interrupt */
+        {  4, MPP_GPIO },               /* V_LED 5V */
+        {  5, MPP_GPIO },               /* V_LED 3.3V */
+        {  6, MPP_UNUSED },
+        {  7, MPP_UNUSED },
+        {  8, MPP_GPIO },               /* SATA 0 fail LED */
+        {  9, MPP_GPIO },               /* SATA 1 fail LED */
+        { 10, MPP_UNUSED },
+        { 11, MPP_UNUSED },
+        { 12, MPP_SATA_LED },           /* SATA 0 presence */
+        { 13, MPP_SATA_LED },           /* SATA 1 presence */
+        { 14, MPP_SATA_LED },           /* SATA 0 active */
+        { 15, MPP_SATA_LED },           /* SATA 1 active */
+        { 16, MPP_UNUSED },
+        { 17, MPP_GPIO },               /* Reset button */
+        { 18, MPP_GPIO },               /* Power button */
+        { 19, MPP_GPIO },               /* Power off */
+        { -1 },
+};
+
+static struct i2c_board_info __initdata mv2120_i2c_rtc = {
+        I2C_BOARD_INFO("pcf8563", 0x51),
+        .irq    = 0,
+};
+
+static struct gpio_led mv2120_led_pins[] = {
+        {
+                .name                   = "mv2120:blue:health",
+                .gpio                   = 0,
+        },
+        {
+                .name                   = "mv2120:red:health",
+                .gpio                   = 1,
+        },
+        {
+                .name                   = "mv2120:led:bright",
+                .gpio                   = 4,
+                .default_trigger        = "default-on",
+        },
+        {
+                .name                   = "mv2120:led:dimmed",
+                .gpio                   = 5,
+        },
+        {
+                .name                   = "mv2120:red:sata0",
+                .gpio                   = 8,
+                .active_low             = 1,
+        },
+        {
+                .name                   = "mv2120:red:sata1",
+                .gpio                   = 9,
+                .active_low             = 1,
+        },
+
+};
+
+static struct gpio_led_platform_data mv2120_led_data = {
+        .leds           = mv2120_led_pins,
+        .num_leds       = ARRAY_SIZE(mv2120_led_pins),
+};
+
+static struct platform_device mv2120_leds = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &mv2120_led_data,
+        }
+};
+
+static void mv2120_power_off(void)
+{
+        pr_info("%s: triggering power-off...\n", __func__);
+        gpio_set_value(MV2120_GPIO_POWER_OFF, 0);
+}
+
+static void __init mv2120_init(void)
+{
+        /* Setup basic Orion functions. Need to be called early. */
+        orion5x_init();
+
+        orion5x_mpp_conf(mv2120_mpp_modes);
+
+        /*
+         * Configure peripherals.
+         */
+        orion5x_ehci0_init();
+        orion5x_ehci1_init();
+        orion5x_eth_init(&mv2120_eth_data);
+        orion5x_i2c_init();
+        orion5x_sata_init(&mv2120_sata_data);
+        orion5x_uart0_init();
+
+        orion5x_setup_dev_boot_win(MV2120_NOR_BOOT_BASE, MV2120_NOR_BOOT_SIZE);
+        platform_device_register(&mv2120_nor_flash);
+
+        platform_device_register(&mv2120_button_device);
+
+        if (gpio_request(MV2120_GPIO_RTC_IRQ, "rtc") == 0) {
+                if (gpio_direction_input(MV2120_GPIO_RTC_IRQ) == 0)
+                        mv2120_i2c_rtc.irq = gpio_to_irq(MV2120_GPIO_RTC_IRQ);
+                else
+                        gpio_free(MV2120_GPIO_RTC_IRQ);
+        }
+        i2c_register_board_info(0, &mv2120_i2c_rtc, 1);
+        platform_device_register(&mv2120_leds);
+
+        /* register mv2120 specific power-off method */
+        if (gpio_request(MV2120_GPIO_POWER_OFF, "POWEROFF") != 0 ||
+            gpio_direction_output(MV2120_GPIO_POWER_OFF, 1) != 0)
+                pr_err("mv2120: failed to setup power-off GPIO\n");
+        pm_power_off = mv2120_power_off;
+}
+
+/* Warning: HP uses a wrong mach-type (=526) in their bootloader */
+MACHINE_START(MV2120, "HP Media Vault mv2120")
+        /* Maintainer: Martin Michlmayr <tbm@cyrius.com> */
+        .phys_io        = ORION5X_REGS_PHYS_BASE,
+        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
+        .boot_params    = 0x00000100,
+        .init_machine   = mv2120_init,
+        .map_io         = orion5x_map_io,
+        .init_irq       = orion5x_init_irq,
+        .timer          = &orion5x_timer,
+        .fixup          = tag_fixup_mem32
+MACHINE_END
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
index 9d5d39fa19c3..256a4f680935 100644
--- a/arch/arm/mach-orion5x/pci.c
+++ b/arch/arm/mach-orion5x/pci.c
@@ -152,6 +152,8 @@ static int __init pcie_setup(struct pci_sys_data *sys)
         if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) {
                 printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config "
                                    "read transaction workaround\n");
+                orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE,
+                                          ORION5X_PCIE_WA_SIZE);
                 pcie_ops.read = pcie_rd_conf_wa;
         }
 
@@ -240,13 +242,13 @@ static int __init pcie_setup(struct pci_sys_data *sys)
  * PCI Address Decode Windows registers
  */
 #define PCI_BAR_SIZE_DDR_CS(n)  (((n) == 0) ? ORION5X_PCI_REG(0xc08) : \
-                                ((n) == 1) ? ORION5X_PCI_REG(0xd08) :  \
-                                ((n) == 2) ? ORION5X_PCI_REG(0xc0c) :  \
-                                ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0)
-#define PCI_BAR_REMAP_DDR_CS(n) (((n) ==0) ? ORION5X_PCI_REG(0xc48) :  \
-                                ((n) == 1) ? ORION5X_PCI_REG(0xd48) :  \
-                                ((n) == 2) ? ORION5X_PCI_REG(0xc4c) :  \
-                                ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0)
+                                 ((n) == 1) ? ORION5X_PCI_REG(0xd08) : \
+                                 ((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \
+                                 ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0)
+#define PCI_BAR_REMAP_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc48) : \
+                                 ((n) == 1) ? ORION5X_PCI_REG(0xd48) : \
+                                 ((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \
+                                 ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0)
 #define PCI_BAR_ENABLE          ORION5X_PCI_REG(0xc3c)
 #define PCI_ADDR_DECODE_CTRL    ORION5X_PCI_REG(0xd3c)
 
@@ -264,9 +266,11 @@ static int __init pcie_setup(struct pci_sys_data *sys)
  */
 static DEFINE_SPINLOCK(orion5x_pci_lock);
 
+static int orion5x_pci_cardbus_mode;
+
 static int orion5x_pci_local_bus_nr(void)
 {
-        u32 conf = orion5x_read(PCI_P2P_CONF);
+        u32 conf = readl(PCI_P2P_CONF);
         return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS);
 }
 
@@ -276,11 +280,11 @@ static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func,
         unsigned long flags;
         spin_lock_irqsave(&orion5x_pci_lock, flags);
 
-        orion5x_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) |
-                        PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
-                        PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN);
+        writel(PCI_CONF_BUS(bus) |
+                PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
+                PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR);
 
-        *val = orion5x_read(PCI_CONF_DATA);
+        *val = readl(PCI_CONF_DATA);
 
         if (size == 1)
                 *val = (*val >> (8*(where & 0x3))) & 0xff;
@@ -300,9 +304,9 @@ static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func,
 
         spin_lock_irqsave(&orion5x_pci_lock, flags);
 
-        orion5x_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) |
-                        PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
-                        PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN);
+        writel(PCI_CONF_BUS(bus) |
+                PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
+                PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR);
 
         if (size == 4) {
                 __raw_writel(val, PCI_CONF_DATA);
@@ -319,14 +323,30 @@ static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func,
         return ret;
 }
 
+static int orion5x_pci_valid_config(int bus, u32 devfn)
+{
+        if (bus == orion5x_pci_local_bus_nr()) {
+                /*
+                 * Don't go out for local device
+                 */
+                if (PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0)
+                        return 0;
+
+                /*
+                 * When the PCI signals are directly connected to a
+                 * Cardbus slot, ignore all but device IDs 0 and 1.
+                 */
+                if (orion5x_pci_cardbus_mode && PCI_SLOT(devfn) > 1)
+                        return 0;
+        }
+
+        return 1;
+}
+
 static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn,
                                 int where, int size, u32 *val)
 {
-        /*
-         * Don't go out for local device
-         */
-        if (bus->number == orion5x_pci_local_bus_nr() &&
-            PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0) {
+        if (!orion5x_pci_valid_config(bus->number, devfn)) {
                 *val = 0xffffffff;
                 return PCIBIOS_DEVICE_NOT_FOUND;
         }
@@ -338,8 +358,7 @@ static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn,
 static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn,
                                 int where, int size, u32 val)
 {
-        if (bus->number == orion5x_pci_local_bus_nr() &&
-            PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0)
+        if (!orion5x_pci_valid_config(bus->number, devfn))
                 return PCIBIOS_DEVICE_NOT_FOUND;
 
         return orion5x_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn),
@@ -353,9 +372,9 @@ static struct pci_ops pci_ops = {
 
 static void __init orion5x_pci_set_bus_nr(int nr)
 {
-        u32 p2p = orion5x_read(PCI_P2P_CONF);
+        u32 p2p = readl(PCI_P2P_CONF);
 
-        if (orion5x_read(PCI_MODE) & PCI_MODE_PCIX) {
+        if (readl(PCI_MODE) & PCI_MODE_PCIX) {
                 /*
                  * PCI-X mode
                  */
@@ -372,7 +391,7 @@ static void __init orion5x_pci_set_bus_nr(int nr)
                  */
                 p2p &= ~PCI_P2P_BUS_MASK;
                 p2p |= (nr << PCI_P2P_BUS_OFFS);
-                orion5x_write(PCI_P2P_CONF, p2p);
+                writel(p2p, PCI_P2P_CONF);
         }
 }
 
@@ -399,7 +418,7 @@ static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram)
          * First, disable windows.
          */
         win_enable = 0xffffffff;
-        orion5x_write(PCI_BAR_ENABLE, win_enable);
+        writel(win_enable, PCI_BAR_ENABLE);
 
         /*
          * Setup windows for DDR banks.
@@ -425,10 +444,10 @@ static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram)
                  */
                 reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index);
                 orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0);
-                orion5x_write(PCI_BAR_SIZE_DDR_CS(cs->cs_index),
-                                (cs->size - 1) & 0xfffff000);
-                orion5x_write(PCI_BAR_REMAP_DDR_CS(cs->cs_index),
-                                cs->base & 0xfffff000);
+                writel((cs->size - 1) & 0xfffff000,
+                        PCI_BAR_SIZE_DDR_CS(cs->cs_index));
+                writel(cs->base & 0xfffff000,
+                        PCI_BAR_REMAP_DDR_CS(cs->cs_index));
 
                 /*
                  * Enable decode window for this chip select.
@@ -439,7 +458,7 @@ static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram)
         /*
          * Re-enable decode windows.
          */
-        orion5x_write(PCI_BAR_ENABLE, win_enable);
+        writel(win_enable, PCI_BAR_ENABLE);
 
         /*
          * Disable automatic update of address remaping when writing to BARs.
@@ -522,6 +541,11 @@ static void __devinit rc_pci_fixup(struct pci_dev *dev)
 }
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
 
+void __init orion5x_pci_set_cardbus_mode(void)
+{
+        orion5x_pci_cardbus_mode = 1;
+}
+
 int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys)
 {
         int ret = 0;
diff --git a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
new file mode 100644
index 000000000000..d50e3650a09e
--- /dev/null
+++ b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
@@ -0,0 +1,161 @@
+/*
+ * arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
+ *
+ * Marvell Orion-VoIP FXO Reference Design Setup
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/pci.h>
+#include <linux/irq.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mv643xx_eth.h>
+#include <asm/mach-types.h>
+#include <asm/gpio.h>
+#include <asm/leds.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/pci.h>
+#include <asm/arch/orion5x.h>
+#include "common.h"
+#include "mpp.h"
+
+/*****************************************************************************
+ * RD-88F5181L FXO Info
+ ****************************************************************************/
+/*
+ * 8M NOR flash Device bus boot chip select
+ */
+#define RD88F5181L_FXO_NOR_BOOT_BASE            0xff800000
+#define RD88F5181L_FXO_NOR_BOOT_SIZE            SZ_8M
+
+
+/*****************************************************************************
+ * 8M NOR Flash on Device bus Boot chip select
+ ****************************************************************************/
+static struct physmap_flash_data rd88f5181l_fxo_nor_boot_flash_data = {
+        .width          = 1,
+};
+
+static struct resource rd88f5181l_fxo_nor_boot_flash_resource = {
+        .flags          = IORESOURCE_MEM,
+        .start          = RD88F5181L_FXO_NOR_BOOT_BASE,
+        .end            = RD88F5181L_FXO_NOR_BOOT_BASE +
+                          RD88F5181L_FXO_NOR_BOOT_SIZE - 1,
+};
+
+static struct platform_device rd88f5181l_fxo_nor_boot_flash = {
+        .name                   = "physmap-flash",
+        .id                     = 0,
+        .dev            = {
+                .platform_data  = &rd88f5181l_fxo_nor_boot_flash_data,
+        },
+        .num_resources          = 1,
+        .resource               = &rd88f5181l_fxo_nor_boot_flash_resource,
+};
+
+
+/*****************************************************************************
+ * General Setup
+ ****************************************************************************/
+static struct orion5x_mpp_mode rd88f5181l_fxo_mpp_modes[] __initdata = {
+        {  0, MPP_GPIO },               /* LED1 CardBus LED (front panel) */
+        {  1, MPP_GPIO },               /* PCI_intA */
+        {  2, MPP_GPIO },               /* Hard Reset / Factory Init*/
+        {  3, MPP_GPIO },               /* FXS or DAA select */
+        {  4, MPP_GPIO },               /* LED6 - phone LED (front panel) */
+        {  5, MPP_GPIO },               /* LED5 - phone LED (front panel) */
+        {  6, MPP_PCI_CLK },            /* CPU PCI refclk */
+        {  7, MPP_PCI_CLK },            /* PCI/PCIe refclk */
+        {  8, MPP_GPIO },               /* CardBus reset */
+        {  9, MPP_GPIO },               /* GE_RXERR */
+        { 10, MPP_GPIO },               /* LED2 MiniPCI LED (front panel) */
+        { 11, MPP_GPIO },               /* Lifeline control */
+        { 12, MPP_GIGE },               /* GE_TXD[4] */
+        { 13, MPP_GIGE },               /* GE_TXD[5] */
+        { 14, MPP_GIGE },               /* GE_TXD[6] */
+        { 15, MPP_GIGE },               /* GE_TXD[7] */
+        { 16, MPP_GIGE },               /* GE_RXD[4] */
+        { 17, MPP_GIGE },               /* GE_RXD[5] */
+        { 18, MPP_GIGE },               /* GE_RXD[6] */
+        { 19, MPP_GIGE },               /* GE_RXD[7] */
+        { -1 },
+};
+
+static struct mv643xx_eth_platform_data rd88f5181l_fxo_eth_data = {
+        .phy_addr       = -1,
+};
+
+static void __init rd88f5181l_fxo_init(void)
+{
+        /*
+         * Setup basic Orion functions. Need to be called early.
+         */
+        orion5x_init();
+
+        orion5x_mpp_conf(rd88f5181l_fxo_mpp_modes);
+
+        /*
+         * Configure peripherals.
+         */
+        orion5x_ehci0_init();
+        orion5x_eth_init(&rd88f5181l_fxo_eth_data);
+        orion5x_uart0_init();
+
+        orion5x_setup_dev_boot_win(RD88F5181L_FXO_NOR_BOOT_BASE,
+                                   RD88F5181L_FXO_NOR_BOOT_SIZE);
+        platform_device_register(&rd88f5181l_fxo_nor_boot_flash);
+}
+
+static int __init
+rd88f5181l_fxo_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+        int irq;
+
+        /*
+         * Check for devices with hard-wired IRQs.
+         */
+        irq = orion5x_pci_map_irq(dev, slot, pin);
+        if (irq != -1)
+                return irq;
+
+        /*
+         * Mini-PCI / Cardbus slot.
+         */
+        return gpio_to_irq(1);
+}
+
+static struct hw_pci rd88f5181l_fxo_pci __initdata = {
+        .nr_controllers = 2,
+        .swizzle        = pci_std_swizzle,
+        .setup          = orion5x_pci_sys_setup,
+        .scan           = orion5x_pci_sys_scan_bus,
+        .map_irq        = rd88f5181l_fxo_pci_map_irq,
+};
+
+static int __init rd88f5181l_fxo_pci_init(void)
+{
+        if (machine_is_rd88f5181l_fxo()) {
+                orion5x_pci_set_cardbus_mode();
+                pci_common_init(&rd88f5181l_fxo_pci);
+        }
+
+        return 0;
+}
+subsys_initcall(rd88f5181l_fxo_pci_init);
+
+MACHINE_START(RD88F5181L_FXO, "Marvell Orion-VoIP FXO Reference Design")
+        /* Maintainer: Nicolas Pitre <nico@marvell.com> */
+        .phys_io        = ORION5X_REGS_PHYS_BASE,
+        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
+        .boot_params    = 0x00000100,
+        .init_machine   = rd88f5181l_fxo_init,
+        .map_io         = orion5x_map_io,
+        .init_irq       = orion5x_init_irq,
+        .timer          = &orion5x_timer,
+        .fixup          = tag_fixup_mem32,
+MACHINE_END
diff --git a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
new file mode 100644
index 000000000000..b56447d32e17
--- /dev/null
+++ b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
@@ -0,0 +1,172 @@
+/*
+ * arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
+ *
+ * Marvell Orion-VoIP GE Reference Design Setup
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/pci.h>
+#include <linux/irq.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/i2c.h>
+#include <asm/mach-types.h>
+#include <asm/gpio.h>
+#include <asm/leds.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/pci.h>
+#include <asm/arch/orion5x.h>
+#include "common.h"
+#include "mpp.h"
+
+/*****************************************************************************
+ * RD-88F5181L GE Info
+ ****************************************************************************/
+/*
+ * 16M NOR flash Device bus boot chip select
+ */
+#define RD88F5181L_GE_NOR_BOOT_BASE             0xff000000
+#define RD88F5181L_GE_NOR_BOOT_SIZE             SZ_16M
+
+
+/*****************************************************************************
+ * 16M NOR Flash on Device bus Boot chip select
+ ****************************************************************************/
+static struct physmap_flash_data rd88f5181l_ge_nor_boot_flash_data = {
+        .width          = 1,
+};
+
+static struct resource rd88f5181l_ge_nor_boot_flash_resource = {
+        .flags          = IORESOURCE_MEM,
+        .start          = RD88F5181L_GE_NOR_BOOT_BASE,
+        .end            = RD88F5181L_GE_NOR_BOOT_BASE +
+                          RD88F5181L_GE_NOR_BOOT_SIZE - 1,
+};
+
+static struct platform_device rd88f5181l_ge_nor_boot_flash = {
+        .name                   = "physmap-flash",
+        .id                     = 0,
+        .dev            = {
+                .platform_data  = &rd88f5181l_ge_nor_boot_flash_data,
+        },
+        .num_resources          = 1,
+        .resource               = &rd88f5181l_ge_nor_boot_flash_resource,
+};
+
+
+/*****************************************************************************
+ * General Setup
+ ****************************************************************************/
+static struct orion5x_mpp_mode rd88f5181l_ge_mpp_modes[] __initdata = {
+        {  0, MPP_GPIO },               /* LED1 */
+        {  1, MPP_GPIO },               /* LED5 */
+        {  2, MPP_GPIO },               /* LED4 */
+        {  3, MPP_GPIO },               /* LED3 */
+        {  4, MPP_GPIO },               /* PCI_intA */
+        {  5, MPP_GPIO },               /* RTC interrupt */
+        {  6, MPP_PCI_CLK },            /* CPU PCI refclk */
+        {  7, MPP_PCI_CLK },            /* PCI/PCIe refclk */
+        {  8, MPP_GPIO },               /* 88e6131 interrupt */
+        {  9, MPP_GPIO },               /* GE_RXERR */
+        { 10, MPP_GPIO },               /* PCI_intB */
+        { 11, MPP_GPIO },               /* LED2 */
+        { 12, MPP_GIGE },               /* GE_TXD[4] */
+        { 13, MPP_GIGE },               /* GE_TXD[5] */
+        { 14, MPP_GIGE },               /* GE_TXD[6] */
+        { 15, MPP_GIGE },               /* GE_TXD[7] */
+        { 16, MPP_GIGE },               /* GE_RXD[4] */
+        { 17, MPP_GIGE },               /* GE_RXD[5] */
+        { 18, MPP_GIGE },               /* GE_RXD[6] */
+        { 19, MPP_GIGE },               /* GE_RXD[7] */
+        { -1 },
+};
+
+static struct mv643xx_eth_platform_data rd88f5181l_ge_eth_data = {
+        .phy_addr       = -1,
+};
+
+static struct i2c_board_info __initdata rd88f5181l_ge_i2c_rtc = {
+        I2C_BOARD_INFO("ds1338", 0x68),
+};
+
+static void __init rd88f5181l_ge_init(void)
+{
+        /*
+         * Setup basic Orion functions. Need to be called early.
+         */
+        orion5x_init();
+
+        orion5x_mpp_conf(rd88f5181l_ge_mpp_modes);
+
+        /*
+         * Configure peripherals.
+         */
+        orion5x_ehci0_init();
+        orion5x_eth_init(&rd88f5181l_ge_eth_data);
+        orion5x_i2c_init();
+        orion5x_uart0_init();
+
+        orion5x_setup_dev_boot_win(RD88F5181L_GE_NOR_BOOT_BASE,
+                                   RD88F5181L_GE_NOR_BOOT_SIZE);
+        platform_device_register(&rd88f5181l_ge_nor_boot_flash);
+
+        i2c_register_board_info(0, &rd88f5181l_ge_i2c_rtc, 1);
+}
+
+static int __init
+rd88f5181l_ge_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+        int irq;
+
+        /*
+         * Check for devices with hard-wired IRQs.
+         */
+        irq = orion5x_pci_map_irq(dev, slot, pin);
+        if (irq != -1)
+                return irq;
+
+        /*
+         * Cardbus slot.
+         */
+        if (pin == 1)
+                return gpio_to_irq(4);
+        else
+                return gpio_to_irq(10);
+}
+
+static struct hw_pci rd88f5181l_ge_pci __initdata = {
+        .nr_controllers = 2,
+        .swizzle        = pci_std_swizzle,
+        .setup          = orion5x_pci_sys_setup,
+        .scan           = orion5x_pci_sys_scan_bus,
+        .map_irq        = rd88f5181l_ge_pci_map_irq,
+};
+
+static int __init rd88f5181l_ge_pci_init(void)
+{
+        if (machine_is_rd88f5181l_ge()) {
+                orion5x_pci_set_cardbus_mode();
+                pci_common_init(&rd88f5181l_ge_pci);
+        }
+
+        return 0;
+}
+subsys_initcall(rd88f5181l_ge_pci_init);
+
+MACHINE_START(RD88F5181L_GE, "Marvell Orion-VoIP GE Reference Design")
+        /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
+        .phys_io        = ORION5X_REGS_PHYS_BASE,
+        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
+        .boot_params    = 0x00000100,
+        .init_machine   = rd88f5181l_ge_init,
+        .map_io         = orion5x_map_io,
+        .init_irq       = orion5x_init_irq,
+        .timer          = &orion5x_timer,
+        .fixup          = tag_fixup_mem32,
+MACHINE_END
diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c
index 81abc1003aae..10ae62864269 100644
--- a/arch/arm/mach-orion5x/rd88f5182-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5182-setup.c
@@ -26,6 +26,7 @@
 #include <asm/mach/pci.h>
 #include <asm/arch/orion5x.h>
 #include "common.h"
+#include "mpp.h"
 
 /*****************************************************************************
  * RD-88F5182 Info
@@ -125,6 +126,7 @@ static int __init rd88f5182_dbgled_init(void)
 
                 leds_event = rd88f5182_dbgled_event;
         }
+
         return 0;
 }
 
@@ -220,7 +222,6 @@ subsys_initcall(rd88f5182_pci_init);
 
 static struct mv643xx_eth_platform_data rd88f5182_eth_data = {
         .phy_addr       = 8,
-        .force_phy_addr = 1,
 };
 
 /*****************************************************************************
@@ -234,15 +235,34 @@ static struct i2c_board_info __initdata rd88f5182_i2c_rtc = {
  * Sata
  ****************************************************************************/
 static struct mv_sata_platform_data rd88f5182_sata_data = {
-        .n_ports        = 2,
+        .n_ports        = 2,
 };
 
 /*****************************************************************************
  * General Setup
  ****************************************************************************/
-
-static struct platform_device *rd88f5182_devices[] __initdata = {
-        &rd88f5182_nor_flash,
+static struct orion5x_mpp_mode rd88f5182_mpp_modes[] __initdata = {
+        {  0, MPP_GPIO },               /* Debug Led */
+        {  1, MPP_GPIO },               /* Reset Switch */
+        {  2, MPP_UNUSED },
+        {  3, MPP_GPIO },               /* RTC Int */
+        {  4, MPP_GPIO },
+        {  5, MPP_GPIO },
+        {  6, MPP_GPIO },               /* PCI_intA */
+        {  7, MPP_GPIO },               /* PCI_intB */
+        {  8, MPP_UNUSED },
+        {  9, MPP_UNUSED },
+        { 10, MPP_UNUSED },
+        { 11, MPP_UNUSED },
+        { 12, MPP_SATA_LED },           /* SATA 0 presence */
+        { 13, MPP_SATA_LED },           /* SATA 1 presence */
+        { 14, MPP_SATA_LED },           /* SATA 0 active */
+        { 15, MPP_SATA_LED },           /* SATA 1 active */
+        { 16, MPP_UNUSED },
+        { 17, MPP_UNUSED },
+        { 18, MPP_UNUSED },
+        { 19, MPP_UNUSED },
+        { -1 },
 };
 
 static void __init rd88f5182_init(void)
@@ -252,35 +272,9 @@ static void __init rd88f5182_init(void)
          */
         orion5x_init();
 
-        /*
-         * Setup the CPU address decode windows for our devices
-         */
-        orion5x_setup_dev_boot_win(RD88F5182_NOR_BOOT_BASE,
-                                RD88F5182_NOR_BOOT_SIZE);
-        orion5x_setup_dev1_win(RD88F5182_NOR_BASE, RD88F5182_NOR_SIZE);
-
-        /*
-         * Open a special address decode windows for the PCIe WA.
-         */
-        orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE,
-                                ORION5X_PCIE_WA_SIZE);
+        orion5x_mpp_conf(rd88f5182_mpp_modes);
 
         /*
-         * Setup Multiplexing Pins --
-         * MPP[0] Debug Led (GPIO - Out)
-         * MPP[1] Debug Led (GPIO - Out)
-         * MPP[2] N/A
-         * MPP[3] RTC_Int (GPIO - In)
-         * MPP[4] GPIO
-         * MPP[5] GPIO
-         * MPP[6] PCI_intA (GPIO - In)
-         * MPP[7] PCI_intB (GPIO - In)
-         * MPP[8-11] N/A
-         * MPP[12] SATA 0 presence Indication
-         * MPP[13] SATA 1 presence Indication
-         * MPP[14] SATA 0 active Indication
-         * MPP[15] SATA 1 active indication
-         * MPP[16-19] Not used
          * MPP[20] PCI Clock to MV88F5182
          * MPP[21] PCI Clock to mini PCI CON11
          * MPP[22] USB 0 over current indication
@@ -289,16 +283,23 @@ static void __init rd88f5182_init(void)
          * MPP[25] USB 0 over current enable
          */
 
-        orion5x_write(MPP_0_7_CTRL, 0x00000003);
-        orion5x_write(MPP_8_15_CTRL, 0x55550000);
-        orion5x_write(MPP_16_19_CTRL, 0x5555);
+        /*
+         * Configure peripherals.
+         */
+        orion5x_ehci0_init();
+        orion5x_ehci1_init();
+        orion5x_eth_init(&rd88f5182_eth_data);
+        orion5x_i2c_init();
+        orion5x_sata_init(&rd88f5182_sata_data);
+        orion5x_uart0_init();
 
-        orion5x_gpio_set_valid_pins(0x000000fb);
+        orion5x_setup_dev_boot_win(RD88F5182_NOR_BOOT_BASE,
+                                   RD88F5182_NOR_BOOT_SIZE);
+
+        orion5x_setup_dev1_win(RD88F5182_NOR_BASE, RD88F5182_NOR_SIZE);
+        platform_device_register(&rd88f5182_nor_flash);
 
-        platform_add_devices(rd88f5182_devices, ARRAY_SIZE(rd88f5182_devices));
         i2c_register_board_info(0, &rd88f5182_i2c_rtc, 1);
-        orion5x_eth_init(&rd88f5182_eth_data);
-        orion5x_sata_init(&rd88f5182_sata_data);
 }
 
 MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design")
diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c
index 9afb41ee6e07..a9cef9703d5b 100644
--- a/arch/arm/mach-orion5x/ts209-setup.c
+++ b/arch/arm/mach-orion5x/ts209-setup.c
@@ -28,6 +28,8 @@
 #include <asm/mach/pci.h>
 #include <asm/arch/orion5x.h>
 #include "common.h"
+#include "mpp.h"
+#include "tsx09-common.h"
 
 #define QNAP_TS209_NOR_BOOT_BASE 0xf4000000
 #define QNAP_TS209_NOR_BOOT_SIZE SZ_8M
@@ -47,52 +49,54 @@
  ***************************************************************************/
 static struct mtd_partition qnap_ts209_partitions[] = {
         {
-                .name       = "U-Boot",
-                .size       = 0x00080000,
-                .offset     = 0x00780000,
-                .mask_flags = MTD_WRITEABLE,
+                .name           = "U-Boot",
+                .size           = 0x00080000,
+                .offset         = 0x00780000,
+                .mask_flags     = MTD_WRITEABLE,
         }, {
-                .name   = "Kernel",
-                .size   = 0x00200000,
-                .offset = 0,
+                .name           = "Kernel",
+                .size           = 0x00200000,
+                .offset         = 0,
         }, {
-                .name   = "RootFS1",
-                .size   = 0x00400000,
-                .offset = 0x00200000,
+                .name           = "RootFS1",
+                .size           = 0x00400000,
+                .offset         = 0x00200000,
         }, {
-                .name   = "RootFS2",
-                .size   = 0x00100000,
-                .offset = 0x00600000,
+                .name           = "RootFS2",
+                .size           = 0x00100000,
+                .offset         = 0x00600000,
         }, {
-                .name   = "U-Boot Config",
-                .size   = 0x00020000,
-                .offset = 0x00760000,
+                .name           = "U-Boot Config",
+                .size           = 0x00020000,
+                .offset         = 0x00760000,
         }, {
-                .name       = "NAS Config",
-                .size       = 0x00060000,
-                .offset     = 0x00700000,
-                .mask_flags = MTD_WRITEABLE,
-        }
+                .name           = "NAS Config",
+                .size           = 0x00060000,
+                .offset         = 0x00700000,
+                .mask_flags     = MTD_WRITEABLE,
+        },
 };
 
 static struct physmap_flash_data qnap_ts209_nor_flash_data = {
-        .width    = 1,
-        .parts    = qnap_ts209_partitions,
-        .nr_parts = ARRAY_SIZE(qnap_ts209_partitions)
+        .width          = 1,
+        .parts          = qnap_ts209_partitions,
+        .nr_parts       = ARRAY_SIZE(qnap_ts209_partitions)
 };
 
 static struct resource qnap_ts209_nor_flash_resource = {
-        .flags = IORESOURCE_MEM,
-        .start = QNAP_TS209_NOR_BOOT_BASE,
-        .end   = QNAP_TS209_NOR_BOOT_BASE + QNAP_TS209_NOR_BOOT_SIZE - 1,
+        .flags  = IORESOURCE_MEM,
+        .start  = QNAP_TS209_NOR_BOOT_BASE,
+        .end    = QNAP_TS209_NOR_BOOT_BASE + QNAP_TS209_NOR_BOOT_SIZE - 1,
 };
 
 static struct platform_device qnap_ts209_nor_flash = {
-        .name          = "physmap-flash",
-        .id            = 0,
-        .dev           = { .platform_data = &qnap_ts209_nor_flash_data, },
-        .resource      = &qnap_ts209_nor_flash_resource,
-        .num_resources = 1,
+        .name           = "physmap-flash",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &qnap_ts209_nor_flash_data,
+        },
+        .resource       = &qnap_ts209_nor_flash_resource,
+        .num_resources  = 1,
 };
 
 /*****************************************************************************
@@ -164,12 +168,12 @@ static int __init qnap_ts209_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 }
 
 static struct hw_pci qnap_ts209_pci __initdata = {
-        .nr_controllers = 2,
-        .preinit        = qnap_ts209_pci_preinit,
-        .swizzle        = pci_std_swizzle,
-        .setup          = orion5x_pci_sys_setup,
-        .scan           = orion5x_pci_sys_scan_bus,
-        .map_irq        = qnap_ts209_pci_map_irq,
+        .nr_controllers = 2,
+        .preinit        = qnap_ts209_pci_preinit,
+        .swizzle        = pci_std_swizzle,
+        .setup          = orion5x_pci_sys_setup,
+        .scan           = orion5x_pci_sys_scan_bus,
+        .map_irq        = qnap_ts209_pci_map_irq,
 };
 
 static int __init qnap_ts209_pci_init(void)
@@ -183,96 +187,6 @@ static int __init qnap_ts209_pci_init(void)
 subsys_initcall(qnap_ts209_pci_init);
 
 /*****************************************************************************
- * Ethernet
- ****************************************************************************/
-
-static struct mv643xx_eth_platform_data qnap_ts209_eth_data = {
-        .phy_addr       = 8,
-        .force_phy_addr = 1,
-};
-
-static int __init parse_hex_nibble(char n)
-{
-        if (n >= '0' && n <= '9')
-                return n - '0';
-
-        if (n >= 'A' && n <= 'F')
-                return n - 'A' + 10;
-
-        if (n >= 'a' && n <= 'f')
-                return n - 'a' + 10;
-
-        return -1;
-}
-
-static int __init parse_hex_byte(const char *b)
-{
-        int hi;
-        int lo;
-
-        hi = parse_hex_nibble(b[0]);
-        lo = parse_hex_nibble(b[1]);
-
-        if (hi < 0 || lo < 0)
-                return -1;
-
-        return (hi << 4) | lo;
-}
-
-static int __init check_mac_addr(const char *addr_str)
-{
-        u_int8_t addr[6];
-        int i;
-
-        for (i = 0; i < 6; i++) {
-                int byte;
-
-                /*
-                 * Enforce "xx:xx:xx:xx:xx:xx\n" format.
-                 */
-                if (addr_str[(i * 3) + 2] != ((i < 5) ? ':' : '\n'))
-                        return -1;
-
-                byte = parse_hex_byte(addr_str + (i * 3));
-                if (byte < 0)
-                        return -1;
-                addr[i] = byte;
-        }
-
-        printk(KERN_INFO "ts209: found ethernet mac address ");
-        for (i = 0; i < 6; i++)
-                printk("%.2x%s", addr[i], (i < 5) ? ":" : ".\n");
-
-        memcpy(qnap_ts209_eth_data.mac_addr, addr, 6);
-
-        return 0;
-}
-
-/*
- * The 'NAS Config' flash partition has an ext2 filesystem which
- * contains a file that has the ethernet MAC address in plain text
- * (format "xx:xx:xx:xx:xx:xx\n".)
- */
-static void __init ts209_find_mac_addr(void)
-{
-        unsigned long addr;
-
-        for (addr = 0x00700000; addr < 0x00760000; addr += 1024) {
-                char *nor_page;
-                int ret = 0;
-
-                nor_page = ioremap(QNAP_TS209_NOR_BOOT_BASE + addr, 1024);
-                if (nor_page != NULL) {
-                        ret = check_mac_addr(nor_page);
-                        iounmap(nor_page);
-                }
-
-                if (ret == 0)
-                        break;
-        }
-}
-
-/*****************************************************************************
  * RTC S35390A on I2C bus
  ****************************************************************************/
 
@@ -280,7 +194,7 @@ static void __init ts209_find_mac_addr(void)
 
 static struct i2c_board_info __initdata qnap_ts209_i2c_rtc = {
         I2C_BOARD_INFO("s35390a", 0x30),
-       .irq         = 0,
+        .irq    = 0,
 };
 
 /****************************************************************************
@@ -297,70 +211,63 @@ static struct gpio_keys_button qnap_ts209_buttons[] = {
                 .gpio           = QNAP_TS209_GPIO_KEY_MEDIA,
                 .desc           = "USB Copy Button",
                 .active_low     = 1,
-        },
-        {
+        }, {
                 .code           = KEY_POWER,
                 .gpio           = QNAP_TS209_GPIO_KEY_RESET,
                 .desc           = "Reset Button",
                 .active_low     = 1,
-        }
+        },
 };
 
 static struct gpio_keys_platform_data qnap_ts209_button_data = {
         .buttons        = qnap_ts209_buttons,
-        .nbuttons       = ARRAY_SIZE(qnap_ts209_buttons),
+        .nbuttons       = ARRAY_SIZE(qnap_ts209_buttons),
 };
 
 static struct platform_device qnap_ts209_button_device = {
         .name           = "gpio-keys",
         .id             = -1,
         .num_resources  = 0,
-        .dev            = { .platform_data  = &qnap_ts209_button_data, },
+        .dev            = {
+                .platform_data  = &qnap_ts209_button_data,
+        },
 };
 
 /*****************************************************************************
  * SATA
  ****************************************************************************/
 static struct mv_sata_platform_data qnap_ts209_sata_data = {
-        .n_ports        = 2,
+        .n_ports        = 2,
 };
 
 /*****************************************************************************
 
  * General Setup
  ****************************************************************************/
-
-static struct platform_device *qnap_ts209_devices[] __initdata = {
-        &qnap_ts209_nor_flash,
-        &qnap_ts209_button_device,
+static struct orion5x_mpp_mode ts209_mpp_modes[] __initdata = {
+        {  0, MPP_UNUSED },
+        {  1, MPP_GPIO },               /* USB copy button */
+        {  2, MPP_GPIO },               /* Load defaults button */
+        {  3, MPP_GPIO },               /* GPIO RTC */
+        {  4, MPP_UNUSED },
+        {  5, MPP_UNUSED },
+        {  6, MPP_GPIO },               /* PCI Int A */
+        {  7, MPP_GPIO },               /* PCI Int B */
+        {  8, MPP_UNUSED },
+        {  9, MPP_UNUSED },
+        { 10, MPP_UNUSED },
+        { 11, MPP_UNUSED },
+        { 12, MPP_SATA_LED },           /* SATA 0 presence */
+        { 13, MPP_SATA_LED },           /* SATA 1 presence */
+        { 14, MPP_SATA_LED },           /* SATA 0 active */
+        { 15, MPP_SATA_LED },           /* SATA 1 active */
+        { 16, MPP_UART },               /* UART1 RXD */
+        { 17, MPP_UART },               /* UART1 TXD */
+        { 18, MPP_GPIO },               /* SW_RST */
+        { 19, MPP_UNUSED },
+        { -1 },
 };
 
-/*
- * QNAP TS-[12]09 specific power off method via UART1-attached PIC
- */
-
-#define UART1_REG(x)  (UART1_VIRT_BASE + ((UART_##x) << 2))
-
-static void qnap_ts209_power_off(void)
-{
-        /* 19200 baud divisor */
-        const unsigned divisor = ((ORION5X_TCLK + (8 * 19200)) / (16 * 19200));
-
-        pr_info("%s: triggering power-off...\n", __func__);
-
-        /* hijack uart1 and reset into sane state (19200,8n1) */
-        orion5x_write(UART1_REG(LCR), 0x83);
-        orion5x_write(UART1_REG(DLL), divisor & 0xff);
-        orion5x_write(UART1_REG(DLM), (divisor >> 8) & 0xff);
-        orion5x_write(UART1_REG(LCR), 0x03);
-        orion5x_write(UART1_REG(IER), 0x00);
-        orion5x_write(UART1_REG(FCR), 0x00);
-        orion5x_write(UART1_REG(MCR), 0x00);
-
-        /* send the power-off command 'A' to PIC */
-        orion5x_write(UART1_REG(TX), 'A');
-}
-
 static void __init qnap_ts209_init(void)
 {
         /*
@@ -368,51 +275,33 @@ static void __init qnap_ts209_init(void)
          */
         orion5x_init();
 
-        /*
-         * Setup flash mapping
-         */
-        orion5x_setup_dev_boot_win(QNAP_TS209_NOR_BOOT_BASE,
-                            QNAP_TS209_NOR_BOOT_SIZE);
-
-        /*
-         * Open a special address decode windows for the PCIe WA.
-         */
-        orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE,
-                                ORION5X_PCIE_WA_SIZE);
+        orion5x_mpp_conf(ts209_mpp_modes);
 
         /*
-         * Setup Multiplexing Pins --
-         * MPP[0] Reserved
-         * MPP[1] USB copy button (0 active)
-         * MPP[2] Load defaults button (0 active)
-         * MPP[3] GPIO RTC
-         * MPP[4-5] Reserved
-         * MPP[6] PCI Int A
-         * MPP[7] PCI Int B
-         * MPP[8-11] Reserved
-         * MPP[12] SATA 0 presence
-         * MPP[13] SATA 1 presence
-         * MPP[14] SATA 0 active
-         * MPP[15] SATA 1 active
-         * MPP[16] UART1 RXD
-         * MPP[17] UART1 TXD
-         * MPP[18] SW_RST (0 active)
-         * MPP[19] Reserved
          * MPP[20] PCI clock 0
          * MPP[21] PCI clock 1
          * MPP[22] USB 0 over current
          * MPP[23-25] Reserved
          */
-        orion5x_write(MPP_0_7_CTRL, 0x3);
-        orion5x_write(MPP_8_15_CTRL, 0x55550000);
-        orion5x_write(MPP_16_19_CTRL, 0x5500);
-        orion5x_gpio_set_valid_pins(0x3cc0fff);
 
-        /* register ts209 specific power-off method */
-        pm_power_off = qnap_ts209_power_off;
+        /*
+         * Configure peripherals.
+         */
+        orion5x_ehci0_init();
+        orion5x_ehci1_init();
+        qnap_tsx09_find_mac_addr(QNAP_TS209_NOR_BOOT_BASE +
+                                 qnap_ts209_partitions[5].offset,
+                                 qnap_ts209_partitions[5].size);
+        orion5x_eth_init(&qnap_tsx09_eth_data);
+        orion5x_i2c_init();
+        orion5x_sata_init(&qnap_ts209_sata_data);
+        orion5x_uart0_init();
+
+        orion5x_setup_dev_boot_win(QNAP_TS209_NOR_BOOT_BASE,
+                                   QNAP_TS209_NOR_BOOT_SIZE);
+        platform_device_register(&qnap_ts209_nor_flash);
 
-        platform_add_devices(qnap_ts209_devices,
-                                ARRAY_SIZE(qnap_ts209_devices));
+        platform_device_register(&qnap_ts209_button_device);
 
         /* Get RTC IRQ and register the chip */
         if (gpio_request(TS209_RTC_GPIO, "rtc") == 0) {
@@ -425,14 +314,12 @@ static void __init qnap_ts209_init(void)
                 pr_warning("qnap_ts209_init: failed to get RTC IRQ\n");
         i2c_register_board_info(0, &qnap_ts209_i2c_rtc, 1);
 
-        ts209_find_mac_addr();
-        orion5x_eth_init(&qnap_ts209_eth_data);
-
-        orion5x_sata_init(&qnap_ts209_sata_data);
+        /* register tsx09 specific power-off method */
+        pm_power_off = qnap_tsx09_power_off;
 }
 
 MACHINE_START(TS209, "QNAP TS-109/TS-209")
-        /* Maintainer:  Byron Bradley <byron.bbradley@gmail.com> */
+        /* Maintainer: Byron Bradley <byron.bbradley@gmail.com> */
         .phys_io        = ORION5X_REGS_PHYS_BASE,
         .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
         .boot_params    = 0x00000100,
diff --git a/arch/arm/mach-orion5x/ts409-setup.c b/arch/arm/mach-orion5x/ts409-setup.c
new file mode 100644
index 000000000000..32f0ff073b7e
--- /dev/null
+++ b/arch/arm/mach-orion5x/ts409-setup.c
@@ -0,0 +1,273 @@
+/*
+ * QNAP TS-409 Board Setup
+ *
+ * Maintainer: Sylver Bruneau <sylver.bruneau@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/pci.h>
+#include <linux/irq.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <linux/i2c.h>
+#include <linux/serial_reg.h>
+#include <asm/mach-types.h>
+#include <asm/gpio.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/pci.h>
+#include <asm/arch/orion5x.h>
+#include "common.h"
+#include "mpp.h"
+#include "tsx09-common.h"
+
+/*****************************************************************************
+ * QNAP TS-409 Info
+ ****************************************************************************/
+
+/*
+ * QNAP TS-409 hardware :
+ * - Marvell 88F5281-D0
+ * - Marvell 88SX7042 SATA controller (PCIe)
+ * - Marvell 88E1118 Gigabit Ethernet PHY
+ * - RTC S35390A (@0x30) on I2C bus
+ * - 8MB NOR flash
+ * - 256MB of DDR-2 RAM
+ */
+
+/*
+ * 8MB NOR flash Device bus boot chip select
+ */
+
+#define QNAP_TS409_NOR_BOOT_BASE 0xff800000
+#define QNAP_TS409_NOR_BOOT_SIZE SZ_8M
+
+/****************************************************************************
+ * 8MiB NOR flash. The struct mtd_partition is not in the same order as the
+ *     partitions on the device because we want to keep compatability with
+ *     existing QNAP firmware.
+ *
+ * Layout as used by QNAP:
+ *  [2] 0x00000000-0x00200000 : "Kernel"
+ *  [3] 0x00200000-0x00600000 : "RootFS1"
+ *  [4] 0x00600000-0x00700000 : "RootFS2"
+ *  [6] 0x00700000-0x00760000 : "NAS Config" (read-only)
+ *  [5] 0x00760000-0x00780000 : "U-Boot Config"
+ *  [1] 0x00780000-0x00800000 : "U-Boot" (read-only)
+ ***************************************************************************/
+static struct mtd_partition qnap_ts409_partitions[] = {
+        {
+                .name           = "U-Boot",
+                .size           = 0x00080000,
+                .offset         = 0x00780000,
+                .mask_flags     = MTD_WRITEABLE,
+        }, {
+                .name           = "Kernel",
+                .size           = 0x00200000,
+                .offset         = 0,
+        }, {
+                .name           = "RootFS1",
+                .size           = 0x00400000,
+                .offset         = 0x00200000,
+        }, {
+                .name           = "RootFS2",
+                .size           = 0x00100000,
+                .offset         = 0x00600000,
+        }, {
+                .name           = "U-Boot Config",
+                .size           = 0x00020000,
+                .offset         = 0x00760000,
+        }, {
+                .name           = "NAS Config",
+                .size           = 0x00060000,
+                .offset         = 0x00700000,
+                .mask_flags     = MTD_WRITEABLE,
+        },
+};
+
+static struct physmap_flash_data qnap_ts409_nor_flash_data = {
+        .width          = 1,
+        .parts          = qnap_ts409_partitions,
+        .nr_parts       = ARRAY_SIZE(qnap_ts409_partitions)
+};
+
+static struct resource qnap_ts409_nor_flash_resource = {
+        .flags  = IORESOURCE_MEM,
+        .start  = QNAP_TS409_NOR_BOOT_BASE,
+        .end    = QNAP_TS409_NOR_BOOT_BASE + QNAP_TS409_NOR_BOOT_SIZE - 1,
+};
+
+static struct platform_device qnap_ts409_nor_flash = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .dev            = { .platform_data = &qnap_ts409_nor_flash_data, },
+        .num_resources  = 1,
+        .resource       = &qnap_ts409_nor_flash_resource,
+};
+
+/*****************************************************************************
+ * PCI
+ ****************************************************************************/
+
+static int __init qnap_ts409_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+        int irq;
+
+        /*
+         * Check for devices with hard-wired IRQs.
+         */
+        irq = orion5x_pci_map_irq(dev, slot, pin);
+        if (irq != -1)
+                return irq;
+
+        /*
+         * PCI isn't used on the TS-409
+         */
+        return -1;
+}
+
+static struct hw_pci qnap_ts409_pci __initdata = {
+        .nr_controllers = 2,
+        .swizzle        = pci_std_swizzle,
+        .setup          = orion5x_pci_sys_setup,
+        .scan           = orion5x_pci_sys_scan_bus,
+        .map_irq        = qnap_ts409_pci_map_irq,
+};
+
+static int __init qnap_ts409_pci_init(void)
+{
+        if (machine_is_ts409())
+                pci_common_init(&qnap_ts409_pci);
+
+        return 0;
+}
+
+subsys_initcall(qnap_ts409_pci_init);
+
+/*****************************************************************************
+ * RTC S35390A on I2C bus
+ ****************************************************************************/
+
+#define TS409_RTC_GPIO  10
+
+static struct i2c_board_info __initdata qnap_ts409_i2c_rtc = {
+        I2C_BOARD_INFO("s35390a", 0x30),
+};
+
+/****************************************************************************
+ * GPIO Attached Keys
+ *     Power button is attached to the PIC microcontroller
+ ****************************************************************************/
+
+#define QNAP_TS409_GPIO_KEY_MEDIA       15
+
+static struct gpio_keys_button qnap_ts409_buttons[] = {
+        {
+                .code           = KEY_RESTART,
+                .gpio           = QNAP_TS409_GPIO_KEY_MEDIA,
+                .desc           = "USB Copy Button",
+                .active_low     = 1,
+        },
+};
+
+static struct gpio_keys_platform_data qnap_ts409_button_data = {
+        .buttons        = qnap_ts409_buttons,
+        .nbuttons       = ARRAY_SIZE(qnap_ts409_buttons),
+};
+
+static struct platform_device qnap_ts409_button_device = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .num_resources  = 0,
+        .dev            = {
+                .platform_data  = &qnap_ts409_button_data,
+        },
+};
+
+/*****************************************************************************
+ * General Setup
+ ****************************************************************************/
+static struct orion5x_mpp_mode ts409_mpp_modes[] __initdata = {
+        {  0, MPP_UNUSED },
+        {  1, MPP_UNUSED },
+        {  2, MPP_UNUSED },
+        {  3, MPP_UNUSED },
+        {  4, MPP_GPIO },               /* HDD 1 status */
+        {  5, MPP_GPIO },               /* HDD 2 status */
+        {  6, MPP_GPIO },               /* HDD 3 status */
+        {  7, MPP_GPIO },               /* HDD 4 status */
+        {  8, MPP_UNUSED },
+        {  9, MPP_UNUSED },
+        { 10, MPP_GPIO },               /* RTC int */
+        { 11, MPP_UNUSED },
+        { 12, MPP_UNUSED },
+        { 13, MPP_UNUSED },
+        { 14, MPP_GPIO },               /* SW_RST */
+        { 15, MPP_GPIO },               /* USB copy button */
+        { 16, MPP_UART },               /* UART1 RXD */
+        { 17, MPP_UART },               /* UART1 TXD */
+        { 18, MPP_UNUSED },
+        { 19, MPP_UNUSED },
+        { -1 },
+};
+
+static void __init qnap_ts409_init(void)
+{
+        /*
+         * Setup basic Orion functions. Need to be called early.
+         */
+        orion5x_init();
+
+        orion5x_mpp_conf(ts409_mpp_modes);
+
+        /*
+         * Configure peripherals.
+         */
+        orion5x_ehci0_init();
+        qnap_tsx09_find_mac_addr(QNAP_TS409_NOR_BOOT_BASE +
+                                 qnap_ts409_partitions[5].offset,
+                                 qnap_ts409_partitions[5].size);
+        orion5x_eth_init(&qnap_tsx09_eth_data);
+        orion5x_i2c_init();
+        orion5x_uart0_init();
+
+        orion5x_setup_dev_boot_win(QNAP_TS409_NOR_BOOT_BASE,
+                                   QNAP_TS409_NOR_BOOT_SIZE);
+        platform_device_register(&qnap_ts409_nor_flash);
+
+        platform_device_register(&qnap_ts409_button_device);
+
+        /* Get RTC IRQ and register the chip */
+        if (gpio_request(TS409_RTC_GPIO, "rtc") == 0) {
+                if (gpio_direction_input(TS409_RTC_GPIO) == 0)
+                        qnap_ts409_i2c_rtc.irq = gpio_to_irq(TS409_RTC_GPIO);
+                else
+                        gpio_free(TS409_RTC_GPIO);
+        }
+        if (qnap_ts409_i2c_rtc.irq == 0)
+                pr_warning("qnap_ts409_init: failed to get RTC IRQ\n");
+        i2c_register_board_info(0, &qnap_ts409_i2c_rtc, 1);
+
+        /* register tsx09 specific power-off method */
+        pm_power_off = qnap_tsx09_power_off;
+}
+
+MACHINE_START(TS409, "QNAP TS-409")
+        /* Maintainer:  Sylver Bruneau <sylver.bruneau@gmail.com> */
+        .phys_io        = ORION5X_REGS_PHYS_BASE,
+        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
+        .boot_params    = 0x00000100,
+        .init_machine   = qnap_ts409_init,
+        .map_io         = orion5x_map_io,
+        .init_irq       = orion5x_init_irq,
+        .timer          = &orion5x_timer,
+        .fixup          = tag_fixup_mem32,
+MACHINE_END
diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c
new file mode 100644
index 000000000000..77e9f351f07a
--- /dev/null
+++ b/arch/arm/mach-orion5x/ts78xx-setup.c
@@ -0,0 +1,277 @@
+/*
+ * arch/arm/mach-orion5x/ts78xx-setup.c
+ *
+ * Maintainer: Alexander Clouter <alex@digriz.org.uk>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/ata_platform.h>
+#include <linux/m48t86.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/arch/orion5x.h>
+#include "common.h"
+#include "mpp.h"
+
+/*****************************************************************************
+ * TS-78xx Info
+ ****************************************************************************/
+
+/*
+ * FPGA - lives where the PCI bus would be at ORION5X_PCI_MEM_PHYS_BASE
+ */
+#define TS78XX_FPGA_REGS_PHYS_BASE      0xe8000000
+#define TS78XX_FPGA_REGS_VIRT_BASE      0xff900000
+#define TS78XX_FPGA_REGS_SIZE           SZ_1M
+
+#define TS78XX_FPGA_REGS_SYSCON_ID      (TS78XX_FPGA_REGS_VIRT_BASE | 0x000)
+#define TS78XX_FPGA_REGS_SYSCON_LCDI    (TS78XX_FPGA_REGS_VIRT_BASE | 0x004)
+#define TS78XX_FPGA_REGS_SYSCON_LCDO    (TS78XX_FPGA_REGS_VIRT_BASE | 0x008)
+
+#define TS78XX_FPGA_REGS_RTC_CTRL       (TS78XX_FPGA_REGS_VIRT_BASE | 0x808)
+#define TS78XX_FPGA_REGS_RTC_DATA       (TS78XX_FPGA_REGS_VIRT_BASE | 0x80c)
+
+/*
+ * 512kB NOR flash Device
+ */
+#define TS78XX_NOR_BOOT_BASE            0xff800000
+#define TS78XX_NOR_BOOT_SIZE            SZ_512K
+
+/*****************************************************************************
+ * I/O Address Mapping
+ ****************************************************************************/
+static struct map_desc ts78xx_io_desc[] __initdata = {
+        {
+                .virtual        = TS78XX_FPGA_REGS_VIRT_BASE,
+                .pfn            = __phys_to_pfn(TS78XX_FPGA_REGS_PHYS_BASE),
+                .length         = TS78XX_FPGA_REGS_SIZE,
+                .type           = MT_DEVICE,
+        },
+};
+
+void __init ts78xx_map_io(void)
+{
+        orion5x_map_io();
+        iotable_init(ts78xx_io_desc, ARRAY_SIZE(ts78xx_io_desc));
+}
+
+/*****************************************************************************
+ * 512kB NOR Boot Flash - the chip is a M25P40
+ ****************************************************************************/
+static struct mtd_partition ts78xx_nor_boot_flash_resources[] = {
+        {
+                .name           = "ts-bootrom",
+                .offset         = 0,
+                /* only the first 256kB is used */
+                .size           = SZ_256K,
+                .mask_flags     = MTD_WRITEABLE,
+        },
+};
+
+static struct physmap_flash_data ts78xx_nor_boot_flash_data = {
+        .width          = 1,
+        .parts          = ts78xx_nor_boot_flash_resources,
+        .nr_parts       = ARRAY_SIZE(ts78xx_nor_boot_flash_resources),
+};
+
+static struct resource ts78xx_nor_boot_flash_resource = {
+        .flags          = IORESOURCE_MEM,
+        .start          = TS78XX_NOR_BOOT_BASE,
+        .end            = TS78XX_NOR_BOOT_BASE + TS78XX_NOR_BOOT_SIZE - 1,
+};
+
+static struct platform_device ts78xx_nor_boot_flash = {
+        .name           = "physmap-flash",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &ts78xx_nor_boot_flash_data,
+        },
+        .num_resources  = 1,
+        .resource       = &ts78xx_nor_boot_flash_resource,
+};
+
+/*****************************************************************************
+ * Ethernet
+ ****************************************************************************/
+static struct mv643xx_eth_platform_data ts78xx_eth_data = {
+        .phy_addr       = 0,
+        .force_phy_addr = 1,
+};
+
+/*****************************************************************************
+ * RTC M48T86 - nicked^Wborrowed from arch/arm/mach-ep93xx/ts72xx.c
+ ****************************************************************************/
+#ifdef CONFIG_RTC_DRV_M48T86
+static unsigned char ts78xx_rtc_readbyte(unsigned long addr)
+{
+        writeb(addr, TS78XX_FPGA_REGS_RTC_CTRL);
+        return readb(TS78XX_FPGA_REGS_RTC_DATA);
+}
+
+static void ts78xx_rtc_writebyte(unsigned char value, unsigned long addr)
+{
+        writeb(addr, TS78XX_FPGA_REGS_RTC_CTRL);
+        writeb(value, TS78XX_FPGA_REGS_RTC_DATA);
+}
+
+static struct m48t86_ops ts78xx_rtc_ops = {
+        .readbyte       = ts78xx_rtc_readbyte,
+        .writebyte      = ts78xx_rtc_writebyte,
+};
+
+static struct platform_device ts78xx_rtc_device = {
+        .name           = "rtc-m48t86",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &ts78xx_rtc_ops,
+        },
+        .num_resources  = 0,
+};
+
+/*
+ * TS uses some of the user storage space on the RTC chip so see if it is
+ * present; as it's an optional feature at purchase time and not all boards
+ * will have it present
+ *
+ * I've used the method TS use in their rtc7800.c example for the detection
+ *
+ * TODO: track down a guinea pig without an RTC to see if we can work out a
+ *              better RTC detection routine
+ */
+static int __init ts78xx_rtc_init(void)
+{
+        unsigned char tmp_rtc0, tmp_rtc1;
+
+        tmp_rtc0 = ts78xx_rtc_readbyte(126);
+        tmp_rtc1 = ts78xx_rtc_readbyte(127);
+
+        ts78xx_rtc_writebyte(0x00, 126);
+        ts78xx_rtc_writebyte(0x55, 127);
+        if (ts78xx_rtc_readbyte(127) == 0x55) {
+                ts78xx_rtc_writebyte(0xaa, 127);
+                if (ts78xx_rtc_readbyte(127) == 0xaa
+                                && ts78xx_rtc_readbyte(126) == 0x00) {
+                        ts78xx_rtc_writebyte(tmp_rtc0, 126);
+                        ts78xx_rtc_writebyte(tmp_rtc1, 127);
+                        platform_device_register(&ts78xx_rtc_device);
+                        return 1;
+                }
+        }
+
+        return 0;
+};
+#else
+static int __init ts78xx_rtc_init(void)
+{
+        return 0;
+}
+#endif
+
+/*****************************************************************************
+ * SATA
+ ****************************************************************************/
+static struct mv_sata_platform_data ts78xx_sata_data = {
+        .n_ports        = 2,
+};
+
+/*****************************************************************************
+ * print some information regarding the board
+ ****************************************************************************/
+static void __init ts78xx_print_board_id(void)
+{
+        unsigned int board_info;
+
+        board_info = readl(TS78XX_FPGA_REGS_SYSCON_ID);
+        printk(KERN_INFO "TS-78xx Info: FPGA rev=%.2x, Board Magic=%.6x, ",
+                                board_info & 0xff,
+                                (board_info >> 8) & 0xffffff);
+        board_info = readl(TS78XX_FPGA_REGS_SYSCON_LCDI);
+        printk("JP1=%d, JP2=%d\n",
+                                (board_info >> 30) & 0x1,
+                                (board_info >> 31) & 0x1);
+};
+
+/*****************************************************************************
+ * General Setup
+ ****************************************************************************/
+static struct orion5x_mpp_mode ts78xx_mpp_modes[] __initdata = {
+        {  0, MPP_UNUSED },
+        {  1, MPP_GPIO },               /* JTAG Clock */
+        {  2, MPP_GPIO },               /* JTAG Data In */
+        {  3, MPP_GPIO },               /* Lat ECP2 256 FPGA - PB2B */
+        {  4, MPP_GPIO },               /* JTAG Data Out */
+        {  5, MPP_GPIO },               /* JTAG TMS */
+        {  6, MPP_GPIO },               /* Lat ECP2 256 FPGA - PB31A_CLK4+ */
+        {  7, MPP_GPIO },               /* Lat ECP2 256 FPGA - PB22B */
+        {  8, MPP_UNUSED },
+        {  9, MPP_UNUSED },
+        { 10, MPP_UNUSED },
+        { 11, MPP_UNUSED },
+        { 12, MPP_UNUSED },
+        { 13, MPP_UNUSED },
+        { 14, MPP_UNUSED },
+        { 15, MPP_UNUSED },
+        { 16, MPP_UART },
+        { 17, MPP_UART },
+        { 18, MPP_UART },
+        { 19, MPP_UART },
+        { -1 },
+};
+
+static void __init ts78xx_init(void)
+{
+        /*
+         * Setup basic Orion functions. Need to be called early.
+         */
+        orion5x_init();
+
+        ts78xx_print_board_id();
+
+        orion5x_mpp_conf(ts78xx_mpp_modes);
+
+        /*
+         * MPP[20] PCI Clock Out 1
+         * MPP[21] PCI Clock Out 0
+         * MPP[22] Unused
+         * MPP[23] Unused
+         * MPP[24] Unused
+         * MPP[25] Unused
+         */
+
+        /*
+         * Configure peripherals.
+         */
+        orion5x_ehci0_init();
+        orion5x_ehci1_init();
+        orion5x_eth_init(&ts78xx_eth_data);
+        orion5x_sata_init(&ts78xx_sata_data);
+        orion5x_uart0_init();
+        orion5x_uart1_init();
+
+        orion5x_setup_dev_boot_win(TS78XX_NOR_BOOT_BASE,
+                                   TS78XX_NOR_BOOT_SIZE);
+        platform_device_register(&ts78xx_nor_boot_flash);
+
+        if (!ts78xx_rtc_init())
+                printk(KERN_INFO "TS-78xx RTC not detected or enabled\n");
+}
+
+MACHINE_START(TS78XX, "Technologic Systems TS-78xx SBC")
+        /* Maintainer: Alexander Clouter <alex@digriz.org.uk> */
+        .phys_io        = ORION5X_REGS_PHYS_BASE,
+        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
+        .boot_params    = 0x00000100,
+        .init_machine   = ts78xx_init,
+        .map_io         = ts78xx_map_io,
+        .init_irq       = orion5x_init_irq,
+        .timer          = &orion5x_timer,
+MACHINE_END
diff --git a/arch/arm/mach-orion5x/tsx09-common.c b/arch/arm/mach-orion5x/tsx09-common.c
new file mode 100644
index 000000000000..83feac3147a6
--- /dev/null
+++ b/arch/arm/mach-orion5x/tsx09-common.c
@@ -0,0 +1,133 @@
+/*
+ * QNAP TS-x09 Boards common functions
+ *
+ * Maintainers: Lennert Buytenhek <buytenh@marvell.com>
+ *              Byron Bradley <byron.bbradley@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/timex.h>
+#include <linux/serial_reg.h>
+#include "tsx09-common.h"
+
+/*****************************************************************************
+ * QNAP TS-x09 specific power off method via UART1-attached PIC
+ ****************************************************************************/
+
+#define UART1_REG(x)    (UART1_VIRT_BASE + ((UART_##x) << 2))
+
+void qnap_tsx09_power_off(void)
+{
+        /* 19200 baud divisor */
+        const unsigned divisor = ((ORION5X_TCLK + (8 * 19200)) / (16 * 19200));
+
+        pr_info("%s: triggering power-off...\n", __func__);
+
+        /* hijack uart1 and reset into sane state (19200,8n1) */
+        writel(0x83, UART1_REG(LCR));
+        writel(divisor & 0xff, UART1_REG(DLL));
+        writel((divisor >> 8) & 0xff, UART1_REG(DLM));
+        writel(0x03, UART1_REG(LCR));
+        writel(0x00, UART1_REG(IER));
+        writel(0x00, UART1_REG(FCR));
+        writel(0x00, UART1_REG(MCR));
+
+        /* send the power-off command 'A' to PIC */
+        writel('A', UART1_REG(TX));
+}
+
+/*****************************************************************************
+ * Ethernet
+ ****************************************************************************/
+
+struct mv643xx_eth_platform_data qnap_tsx09_eth_data = {
+        .phy_addr       = 8,
+};
+
+static int __init qnap_tsx09_parse_hex_nibble(char n)
+{
+        if (n >= '0' && n <= '9')
+                return n - '0';
+
+        if (n >= 'A' && n <= 'F')
+                return n - 'A' + 10;
+
+        if (n >= 'a' && n <= 'f')
+                return n - 'a' + 10;
+
+        return -1;
+}
+
+static int __init qnap_tsx09_parse_hex_byte(const char *b)
+{
+        int hi;
+        int lo;
+
+        hi = qnap_tsx09_parse_hex_nibble(b[0]);
+        lo = qnap_tsx09_parse_hex_nibble(b[1]);
+
+        if (hi < 0 || lo < 0)
+                return -1;
+
+        return (hi << 4) | lo;
+}
+
+static int __init qnap_tsx09_check_mac_addr(const char *addr_str)
+{
+        u_int8_t addr[6];
+        int i;
+
+        for (i = 0; i < 6; i++) {
+                int byte;
+
+                /*
+                 * Enforce "xx:xx:xx:xx:xx:xx\n" format.
+                 */
+                if (addr_str[(i * 3) + 2] != ((i < 5) ? ':' : '\n'))
+                        return -1;
+
+                byte = qnap_tsx09_parse_hex_byte(addr_str + (i * 3));
+                if (byte < 0)
+                        return -1;
+                addr[i] = byte;
+        }
+
+        printk(KERN_INFO "tsx09: found ethernet mac address ");
+        for (i = 0; i < 6; i++)
+                printk("%.2x%s", addr[i], (i < 5) ? ":" : ".\n");
+
+        memcpy(qnap_tsx09_eth_data.mac_addr, addr, 6);
+
+        return 0;
+}
+
+/*
+ * The 'NAS Config' flash partition has an ext2 filesystem which
+ * contains a file that has the ethernet MAC address in plain text
+ * (format "xx:xx:xx:xx:xx:xx\n").
+ */
+void __init qnap_tsx09_find_mac_addr(u32 mem_base, u32 size)
+{
+        unsigned long addr;
+
+        for (addr = mem_base; addr < (mem_base + size); addr += 1024) {
+                char *nor_page;
+                int ret = 0;
+
+                nor_page = ioremap(addr, 1024);
+                if (nor_page != NULL) {
+                        ret = qnap_tsx09_check_mac_addr(nor_page);
+                        iounmap(nor_page);
+                }
+
+                if (ret == 0)
+                        break;
+        }
+}
diff --git a/arch/arm/mach-orion5x/tsx09-common.h b/arch/arm/mach-orion5x/tsx09-common.h
new file mode 100644
index 000000000000..0984264616f0
--- /dev/null
+++ b/arch/arm/mach-orion5x/tsx09-common.h
@@ -0,0 +1,20 @@
+#ifndef __ARCH_ORION5X_TSX09_COMMON_H
+#define __ARCH_ORION5X_TSX09_COMMON_H
+
+/*
+ * QNAP TS-x09 Boards power-off function
+ */
+extern void qnap_tsx09_power_off(void);
+
+/*
+ * QNAP TS-x09 Boards function to find Ethernet MAC address in flash memory
+ */
+extern void __init qnap_tsx09_find_mac_addr(u32 mem_base, u32 size);
+
+/*
+ * QNAP TS-x09 Boards ethernet declaration
+ */
+extern struct mv643xx_eth_platform_data qnap_tsx09_eth_data;
+
+
+#endif
diff --git a/arch/arm/mach-orion5x/wnr854t-setup.c b/arch/arm/mach-orion5x/wnr854t-setup.c
new file mode 100644
index 000000000000..1af093ff8cf3
--- /dev/null
+++ b/arch/arm/mach-orion5x/wnr854t-setup.c
@@ -0,0 +1,164 @@
+/*
+ * arch/arm/mach-orion5x/wnr854t-setup.c
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/pci.h>
+#include <linux/irq.h>
+#include <linux/delay.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mv643xx_eth.h>
+#include <asm/mach-types.h>
+#include <asm/gpio.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/pci.h>
+#include <asm/arch/orion5x.h>
+#include "common.h"
+#include "mpp.h"
+
+static struct orion5x_mpp_mode wnr854t_mpp_modes[] __initdata = {
+        {  0, MPP_GPIO },               /* Power LED green (0=on) */
+        {  1, MPP_GPIO },               /* Reset Button (0=off) */
+        {  2, MPP_GPIO },               /* Power LED blink (0=off) */
+        {  3, MPP_GPIO },               /* WAN Status LED amber (0=off) */
+        {  4, MPP_GPIO },               /* PCI int */
+        {  5, MPP_GPIO },               /* ??? */
+        {  6, MPP_GPIO },               /* ??? */
+        {  7, MPP_GPIO },               /* ??? */
+        {  8, MPP_UNUSED },             /* ??? */
+        {  9, MPP_GIGE },               /* GE_RXERR */
+        { 10, MPP_UNUSED },             /* ??? */
+        { 11, MPP_UNUSED },             /* ??? */
+        { 12, MPP_GIGE },               /* GE_TXD[4] */
+        { 13, MPP_GIGE },               /* GE_TXD[5] */
+        { 14, MPP_GIGE },               /* GE_TXD[6] */
+        { 15, MPP_GIGE },               /* GE_TXD[7] */
+        { 16, MPP_GIGE },               /* GE_RXD[4] */
+        { 17, MPP_GIGE },               /* GE_RXD[5] */
+        { 18, MPP_GIGE },               /* GE_RXD[6] */
+        { 19, MPP_GIGE },               /* GE_RXD[7] */
+        { -1 },
+};
+
+/*
+ * 8M NOR flash Device bus boot chip select
+ */
+#define WNR854T_NOR_BOOT_BASE   0xf4000000
+#define WNR854T_NOR_BOOT_SIZE   SZ_8M
+
+static struct mtd_partition wnr854t_nor_flash_partitions[] = {
+        {
+                .name           = "kernel",
+                .offset         = 0x00000000,
+                .size           = 0x00100000,
+        }, {
+                .name           = "rootfs",
+                .offset         = 0x00100000,
+                .size           = 0x00660000,
+        }, {
+                .name           = "uboot",
+                .offset         = 0x00760000,
+                .size           = 0x00040000,
+        },
+};
+
+static struct physmap_flash_data wnr854t_nor_flash_data = {
+        .width          = 2,
+        .parts          = wnr854t_nor_flash_partitions,
+        .nr_parts       = ARRAY_SIZE(wnr854t_nor_flash_partitions),
+};
+
+static struct resource wnr854t_nor_flash_resource = {
+        .flags          = IORESOURCE_MEM,
+        .start          = WNR854T_NOR_BOOT_BASE,
+        .end            = WNR854T_NOR_BOOT_BASE + WNR854T_NOR_BOOT_SIZE - 1,
+};
+
+static struct platform_device wnr854t_nor_flash = {
+        .name                   = "physmap-flash",
+        .id                     = 0,
+        .dev            = {
+                .platform_data  = &wnr854t_nor_flash_data,
+        },
+        .num_resources          = 1,
+        .resource               = &wnr854t_nor_flash_resource,
+};
+
+static struct mv643xx_eth_platform_data wnr854t_eth_data = {
+        .phy_addr       = -1,
+};
+
+static void __init wnr854t_init(void)
+{
+        /*
+         * Setup basic Orion functions. Need to be called early.
+         */
+        orion5x_init();
+
+        orion5x_mpp_conf(wnr854t_mpp_modes);
+
+        /*
+         * Configure peripherals.
+         */
+        orion5x_eth_init(&wnr854t_eth_data);
+        orion5x_uart0_init();
+
+        orion5x_setup_dev_boot_win(WNR854T_NOR_BOOT_BASE,
+                                   WNR854T_NOR_BOOT_SIZE);
+        platform_device_register(&wnr854t_nor_flash);
+}
+
+static int __init wnr854t_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+        int irq;
+
+        /*
+         * Check for devices with hard-wired IRQs.
+         */
+        irq = orion5x_pci_map_irq(dev, slot, pin);
+        if (irq != -1)
+                return irq;
+
+        /*
+         * Mini-PCI slot.
+         */
+        if (slot == 7)
+                return gpio_to_irq(4);
+
+        return -1;
+}
+
+static struct hw_pci wnr854t_pci __initdata = {
+        .nr_controllers = 2,
+        .swizzle        = pci_std_swizzle,
+        .setup          = orion5x_pci_sys_setup,
+        .scan           = orion5x_pci_sys_scan_bus,
+        .map_irq        = wnr854t_pci_map_irq,
+};
+
+static int __init wnr854t_pci_init(void)
+{
+        if (machine_is_wnr854t())
+                pci_common_init(&wnr854t_pci);
+
+        return 0;
+}
+subsys_initcall(wnr854t_pci_init);
+
+MACHINE_START(WNR854T, "Netgear WNR854T")
+        /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
+        .phys_io        = ORION5X_REGS_PHYS_BASE,
+        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
+        .boot_params    = 0x00000100,
+        .init_machine   = wnr854t_init,
+        .map_io         = orion5x_map_io,
+        .init_irq       = orion5x_init_irq,
+        .timer          = &orion5x_timer,
+        .fixup          = tag_fixup_mem32,
+MACHINE_END
diff --git a/arch/arm/mach-orion5x/wrt350n-v2-setup.c b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
new file mode 100644
index 000000000000..aeab55c6a82d
--- /dev/null
+++ b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
@@ -0,0 +1,173 @@
+/*
+ * arch/arm/mach-orion5x/wrt350n-v2-setup.c
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/pci.h>
+#include <linux/irq.h>
+#include <linux/delay.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mv643xx_eth.h>
+#include <asm/mach-types.h>
+#include <asm/gpio.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/pci.h>
+#include <asm/arch/orion5x.h>
+#include "common.h"
+#include "mpp.h"
+
+static struct orion5x_mpp_mode wrt350n_v2_mpp_modes[] __initdata = {
+        {  0, MPP_GPIO },               /* Power LED green (0=on) */
+        {  1, MPP_GPIO },               /* Security LED (0=on) */
+        {  2, MPP_GPIO },               /* Internal Button (0=on) */
+        {  3, MPP_GPIO },               /* Reset Button (0=on) */
+        {  4, MPP_GPIO },               /* PCI int */
+        {  5, MPP_GPIO },               /* Power LED orange (0=on) */
+        {  6, MPP_GPIO },               /* USB LED (0=on) */
+        {  7, MPP_GPIO },               /* Wireless LED (0=on) */
+        {  8, MPP_UNUSED },             /* ??? */
+        {  9, MPP_GIGE },               /* GE_RXERR */
+        { 10, MPP_UNUSED },             /* ??? */
+        { 11, MPP_UNUSED },             /* ??? */
+        { 12, MPP_GIGE },               /* GE_TXD[4] */
+        { 13, MPP_GIGE },               /* GE_TXD[5] */
+        { 14, MPP_GIGE },               /* GE_TXD[6] */
+        { 15, MPP_GIGE },               /* GE_TXD[7] */
+        { 16, MPP_GIGE },               /* GE_RXD[4] */
+        { 17, MPP_GIGE },               /* GE_RXD[5] */
+        { 18, MPP_GIGE },               /* GE_RXD[6] */
+        { 19, MPP_GIGE },               /* GE_RXD[7] */
+        { -1 },
+};
+
+/*
+ * 8M NOR flash Device bus boot chip select
+ */
+#define WRT350N_V2_NOR_BOOT_BASE        0xf4000000
+#define WRT350N_V2_NOR_BOOT_SIZE        SZ_8M
+
+static struct mtd_partition wrt350n_v2_nor_flash_partitions[] = {
+        {
+                .name           = "kernel",
+                .offset         = 0x00000000,
+                .size           = 0x00760000,
+        }, {
+                .name           = "rootfs",
+                .offset         = 0x001a0000,
+                .size           = 0x005c0000,
+        }, {
+                .name           = "lang",
+                .offset         = 0x00760000,
+                .size           = 0x00040000,
+        }, {
+                .name           = "nvram",
+                .offset         = 0x007a0000,
+                .size           = 0x00020000,
+        }, {
+                .name           = "u-boot",
+                .offset         = 0x007c0000,
+                .size           = 0x00040000,
+        },
+};
+
+static struct physmap_flash_data wrt350n_v2_nor_flash_data = {
+        .width          = 1,
+        .parts          = wrt350n_v2_nor_flash_partitions,
+        .nr_parts       = ARRAY_SIZE(wrt350n_v2_nor_flash_partitions),
+};
+
+static struct resource wrt350n_v2_nor_flash_resource = {
+        .flags          = IORESOURCE_MEM,
+        .start          = WRT350N_V2_NOR_BOOT_BASE,
+        .end            = WRT350N_V2_NOR_BOOT_BASE + WRT350N_V2_NOR_BOOT_SIZE - 1,
+};
+
+static struct platform_device wrt350n_v2_nor_flash = {
+        .name                   = "physmap-flash",
+        .id                     = 0,
+        .dev            = {
+                .platform_data  = &wrt350n_v2_nor_flash_data,
+        },
+        .num_resources          = 1,
+        .resource               = &wrt350n_v2_nor_flash_resource,
+};
+
+static struct mv643xx_eth_platform_data wrt350n_v2_eth_data = {
+        .phy_addr       = -1,
+};
+
+static void __init wrt350n_v2_init(void)
+{
+        /*
+         * Setup basic Orion functions. Need to be called early.
+         */
+        orion5x_init();
+
+        orion5x_mpp_conf(wrt350n_v2_mpp_modes);
+
+        /*
+         * Configure peripherals.
+         */
+        orion5x_ehci0_init();
+        orion5x_eth_init(&wrt350n_v2_eth_data);
+        orion5x_uart0_init();
+
+        orion5x_setup_dev_boot_win(WRT350N_V2_NOR_BOOT_BASE,
+                                   WRT350N_V2_NOR_BOOT_SIZE);
+        platform_device_register(&wrt350n_v2_nor_flash);
+}
+
+static int __init wrt350n_v2_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+        int irq;
+
+        /*
+         * Check for devices with hard-wired IRQs.
+         */
+        irq = orion5x_pci_map_irq(dev, slot, pin);
+        if (irq != -1)
+                return irq;
+
+        /*
+         * Mini-PCI slot.
+         */
+        if (slot == 7)
+                return gpio_to_irq(4);
+
+        return -1;
+}
+
+static struct hw_pci wrt350n_v2_pci __initdata = {
+        .nr_controllers = 2,
+        .swizzle        = pci_std_swizzle,
+        .setup          = orion5x_pci_sys_setup,
+        .scan           = orion5x_pci_sys_scan_bus,
+        .map_irq        = wrt350n_v2_pci_map_irq,
+};
+
+static int __init wrt350n_v2_pci_init(void)
+{
+        if (machine_is_wrt350n_v2())
+                pci_common_init(&wrt350n_v2_pci);
+
+        return 0;
+}
+subsys_initcall(wrt350n_v2_pci_init);
+
+MACHINE_START(WRT350N_V2, "Linksys WRT350N v2")
+        /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
+        .phys_io        = ORION5X_REGS_PHYS_BASE,
+        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
+        .boot_params    = 0x00000100,
+        .init_machine   = wrt350n_v2_init,
+        .map_io         = orion5x_map_io,
+        .init_irq       = orion5x_init_irq,
+        .timer          = &orion5x_timer,
+        .fixup          = tag_fixup_mem32,
+MACHINE_END
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index 5da7a6820492..914bb33dab92 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -20,8 +20,7 @@ endmenu
 
 endif
 
-choice
-        prompt "Select target board"
+menu "Select target boards"
 
 config ARCH_GUMSTIX
         bool "Gumstix XScale boards"
@@ -37,10 +36,12 @@ config ARCH_LUBBOCK
 config MACH_LOGICPD_PXA270
         bool "LogicPD PXA270 Card Engine Development Platform"
         select PXA27x
+        select HAVE_PWM
 
 config MACH_MAINSTONE
         bool "Intel HCDDBBVA0 Development Platform"
         select PXA27x
+        select HAVE_PWM
 
 config ARCH_PXA_IDP
         bool "Accelent Xscale IDP"
@@ -116,6 +117,7 @@ config MACH_COLIBRI
 config MACH_ZYLONITE
         bool "PXA3xx Development Platform"
         select PXA3xx
+        select HAVE_PWM
 
 config MACH_LITTLETON
         bool "PXA3xx Form Factor Platform (aka Littleton)"
@@ -138,7 +140,7 @@ config MACH_PCM027
         select PXA27x
         select IWMMXT
 
-endchoice
+endmenu
 
 choice
         prompt "Used baseboard"
@@ -146,25 +148,24 @@ choice
 
 config MACH_PCM990_BASEBOARD
         bool "PHYTEC PCM-990 development board"
+        select HAVE_PWM
 
 endchoice
 
-if PXA_SHARPSL
-
 choice
-        prompt "Select target Sharp Zaurus device range"
+        prompt "display on pcm990"
+        depends on MACH_PCM990_BASEBOARD
 
-config PXA_SHARPSL_25x
-        bool "Sharp PXA25x models (SL-5600, SL-C7xx and SL-C6000x)"
-        select PXA25x
+config PCM990_DISPLAY_SHARP
+        bool "sharp lq084v1dg21 stn display"
 
-config PXA_SHARPSL_27x
-        bool "Sharp PXA270 models (SL-Cxx00)"
-        select PXA27x
+config PCM990_DISPLAY_NEC
+        bool "nec nl6448bc20_18d tft display"
 
-endchoice
+config PCM990_DISPLAY_NONE
+        bool "no display"
 
-endif
+endchoice
 
 if ARCH_GUMSTIX
 
@@ -199,28 +200,33 @@ endmenu
 
 config MACH_POODLE
         bool "Enable Sharp SL-5600 (Poodle) Support"
-        depends on PXA_SHARPSL_25x
+        depends on PXA_SHARPSL
+        select PXA25x
         select SHARP_LOCOMO
         select PXA_SSP
 
 config MACH_CORGI
         bool "Enable Sharp SL-C700 (Corgi) Support"
-        depends on PXA_SHARPSL_25x
+        depends on PXA_SHARPSL
+        select PXA25x
         select PXA_SHARP_C7xx
 
 config MACH_SHEPHERD
         bool "Enable Sharp SL-C750 (Shepherd) Support"
-        depends on PXA_SHARPSL_25x
+        depends on PXA_SHARPSL
+        select PXA25x
         select PXA_SHARP_C7xx
 
 config MACH_HUSKY
         bool "Enable Sharp SL-C760 (Husky) Support"
-        depends on PXA_SHARPSL_25x
+        depends on PXA_SHARPSL
+        select PXA25x
         select PXA_SHARP_C7xx
 
 config MACH_AKITA
         bool "Enable Sharp SL-1000 (Akita) Support"
-        depends on PXA_SHARPSL_27x
+        depends on PXA_SHARPSL
+        select PXA27x
         select PXA_SHARP_Cxx00
         select MACH_SPITZ
         select I2C
@@ -228,17 +234,20 @@ config MACH_AKITA
 
 config MACH_SPITZ
         bool "Enable Sharp Zaurus SL-3000 (Spitz) Support"
-        depends on PXA_SHARPSL_27x
+        depends on PXA_SHARPSL
+        select PXA27x
         select PXA_SHARP_Cxx00
 
 config MACH_BORZOI
         bool "Enable Sharp Zaurus SL-3100 (Borzoi) Support"
-        depends on PXA_SHARPSL_27x
+        depends on PXA_SHARPSL
+        select PXA27x
         select PXA_SHARP_Cxx00
 
 config MACH_TOSA
         bool "Enable Sharp SL-6000x (Tosa) Support"
-        depends on PXA_SHARPSL_25x
+        depends on PXA_SHARPSL
+        select PXA25x
 
 config PXA25x
         bool
@@ -273,4 +282,10 @@ config PXA_SSP
         tristate
         help
           Enable support for PXA2xx SSP ports
+
+config PXA_PWM
+        tristate
+        default BACKLIGHT_PWM
+        help
+          Enable support for PXA2xx/PXA3xx PWM controllers
 endif
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index 0e6d05bb81aa..c4dfbe87fc4e 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -10,10 +10,11 @@ obj-$(CONFIG_CPU_FREQ)		+= cpu-pxa.o
 
 # Generic drivers that other drivers may depend upon
 obj-$(CONFIG_PXA_SSP)           += ssp.o
+obj-$(CONFIG_PXA_PWM)           += pwm.o
 
 # SoC-specific code
-obj-$(CONFIG_PXA25x)            += mfp-pxa2xx.o pxa25x.o
-obj-$(CONFIG_PXA27x)            += mfp-pxa2xx.o pxa27x.o
+obj-$(CONFIG_PXA25x)            += mfp-pxa2xx.o pxa2xx.o pxa25x.o
+obj-$(CONFIG_PXA27x)            += mfp-pxa2xx.o pxa2xx.o pxa27x.o
 obj-$(CONFIG_PXA3xx)            += mfp-pxa3xx.o pxa3xx.o smemc.o
 obj-$(CONFIG_CPU_PXA300)        += pxa300.o
 obj-$(CONFIG_CPU_PXA320)        += pxa320.o
diff --git a/arch/arm/mach-pxa/clock.c b/arch/arm/mach-pxa/clock.c
index e97dc59813c8..b4d04955dcb0 100644
--- a/arch/arm/mach-pxa/clock.c
+++ b/arch/arm/mach-pxa/clock.c
@@ -12,7 +12,7 @@
 #include <linux/platform_device.h>
 #include <linux/delay.h>
 
-#include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-regs.h>
 #include <asm/arch/pxa2xx-gpio.h>
 #include <asm/hardware.h>
 
@@ -47,6 +47,9 @@ struct clk *clk_get(struct device *dev, const char *id)
                 clk = p;
         mutex_unlock(&clocks_mutex);
 
+        if (!IS_ERR(clk) && clk->ops == NULL)
+                clk = clk->other;
+
         return clk;
 }
 EXPORT_SYMBOL(clk_get);
diff --git a/arch/arm/mach-pxa/clock.h b/arch/arm/mach-pxa/clock.h
index bc6b77e1592e..83cbfaba485d 100644
--- a/arch/arm/mach-pxa/clock.h
+++ b/arch/arm/mach-pxa/clock.h
@@ -15,6 +15,7 @@ struct clk {
         unsigned int            cken;
         unsigned int            delay;
         unsigned int            enabled;
+        struct clk              *other;
 };
 
 #define INIT_CKEN(_name, _cken, _rate, _delay, _dev)    \
@@ -35,6 +36,17 @@ struct clk {
                 .cken   = CKEN_##_cken,                 \
         }
 
+/*
+ * This is a placeholder to alias one clock device+name pair
+ * to another struct clk.
+ */
+#define INIT_CKOTHER(_name, _other, _dev)               \
+        {                                               \
+                .name   = _name,                        \
+                .dev    = _dev,                         \
+                .other  = _other,                       \
+        }
+
 extern const struct clkops clk_cken_ops;
 
 void clk_cken_enable(struct clk *clk);
diff --git a/arch/arm/mach-pxa/cm-x270-pci.c b/arch/arm/mach-pxa/cm-x270-pci.c
index ac7f05f9f3eb..319c9ff3ab9a 100644
--- a/arch/arm/mach-pxa/cm-x270-pci.c
+++ b/arch/arm/mach-pxa/cm-x270-pci.c
@@ -41,18 +41,20 @@ void __init cmx270_pci_adjust_zones(int node, unsigned long *zone_size,
 {
         unsigned int sz = SZ_64M >> PAGE_SHIFT;
 
-        pr_info("Adjusting zones for CM-x270\n");
-
-        /*
-         * Only adjust if > 64M on current system
-         */
-        if (node || (zone_size[0] <= sz))
-                return;
-
-        zone_size[1] = zone_size[0] - sz;
-        zone_size[0] = sz;
-        zhole_size[1] = zhole_size[0];
-        zhole_size[0] = 0;
+        if (machine_is_armcore()) {
+                pr_info("Adjusting zones for CM-x270\n");
+
+                /*
+                 * Only adjust if > 64M on current system
+                 */
+                if (node || (zone_size[0] <= sz))
+                        return;
+
+                zone_size[1] = zone_size[0] - sz;
+                zone_size[0] = sz;
+                zhole_size[1] = zhole_size[0];
+                zhole_size[0] = 0;
+        }
 }
 
 static void cmx270_it8152_irq_demux(unsigned int irq, struct irq_desc *desc)
diff --git a/arch/arm/mach-pxa/cm-x270.c b/arch/arm/mach-pxa/cm-x270.c
index f5851d1adc25..01b9964acec1 100644
--- a/arch/arm/mach-pxa/cm-x270.c
+++ b/arch/arm/mach-pxa/cm-x270.c
@@ -31,6 +31,7 @@
 #include <asm/arch/pxa-regs.h>
 #include <asm/arch/pxa2xx-regs.h>
 #include <asm/arch/pxa2xx-gpio.h>
+#include <asm/arch/audio.h>
 #include <asm/arch/pxafb.h>
 #include <asm/arch/ohci.h>
 #include <asm/arch/mmc.h>
@@ -81,12 +82,6 @@ static struct platform_device cmx270_device_dm9k = {
         }
 };
 
-/* audio device */
-static struct platform_device cmx270_audio_device = {
-        .name           = "pxa2xx-ac97",
-        .id             = -1,
-};
-
 /* touchscreen controller */
 static struct platform_device cmx270_ts_device = {
         .name           = "ucb1400_ts",
@@ -219,7 +214,6 @@ static struct platform_device cmx270_ata = {
 /* platform devices */
 static struct platform_device *platform_devices[] __initdata = {
         &cmx270_device_dm9k,
-        &cmx270_audio_device,
         &cmx270_rtc_device,
         &cmx270_2700G,
         &cmx270_led_device,
@@ -594,6 +588,7 @@ static void __init cmx270_init(void)
 
         /* register CM-X270 platform devices */
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+        pxa_set_ac97_info(NULL);
 
         /* set MCI and OHCI platform parameters */
         pxa_set_mci_info(&cmx270_mci_platform_data);
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index b757dd756655..b37671b71886 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -36,6 +36,7 @@
 #include <asm/mach/irq.h>
 
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-regs.h>
 #include <asm/arch/pxa2xx-gpio.h>
 #include <asm/arch/irda.h>
 #include <asm/arch/mmc.h>
diff --git a/arch/arm/mach-pxa/corgi_pm.c b/arch/arm/mach-pxa/corgi_pm.c
index 0a85f706e887..e91c0f26c412 100644
--- a/arch/arm/mach-pxa/corgi_pm.c
+++ b/arch/arm/mach-pxa/corgi_pm.c
@@ -26,6 +26,7 @@
 #include <asm/arch/sharpsl.h>
 #include <asm/arch/corgi.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-regs.h>
 #include <asm/arch/pxa2xx-gpio.h>
 #include "sharpsl.h"
 
@@ -204,7 +205,9 @@ static struct sharpsl_charger_machinfo corgi_pm_machinfo = {
         .read_devdata    = corgipm_read_devdata,
         .charger_wakeup  = corgi_charger_wakeup,
         .should_wakeup   = corgi_should_wakeup,
+#ifdef CONFIG_BACKLIGHT_CORGI
         .backlight_limit = corgibl_limit_intensity,
+#endif
         .charge_on_volt   = SHARPSL_CHARGE_ON_VOLT,
         .charge_on_temp   = SHARPSL_CHARGE_ON_TEMP,
         .charge_acin_high = SHARPSL_CHARGE_ON_ACIN_HIGH,
@@ -226,6 +229,10 @@ static int __devinit corgipm_init(void)
 {
         int ret;
 
+        if (!machine_is_corgi() && !machine_is_shepherd()
+                        && !machine_is_husky())
+                return -ENODEV;
+
         corgipm_device = platform_device_alloc("sharpsl-pm", -1);
         if (!corgipm_device)
                 return -ENOMEM;
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c
index d6c05b6eab35..a6f2390ce662 100644
--- a/arch/arm/mach-pxa/devices.c
+++ b/arch/arm/mach-pxa/devices.c
@@ -10,11 +10,14 @@
 #include <asm/arch/mmc.h>
 #include <asm/arch/irda.h>
 #include <asm/arch/i2c.h>
+#include <asm/arch/mfp-pxa27x.h>
 #include <asm/arch/ohci.h>
 #include <asm/arch/pxa27x_keypad.h>
 #include <asm/arch/camera.h>
+#include <asm/arch/audio.h>
 
 #include "devices.h"
+#include "generic.h"
 
 void __init pxa_register_device(struct platform_device *dev, void *data)
 {
@@ -91,8 +94,19 @@ static struct resource pxa2xx_udc_resources[] = {
 
 static u64 udc_dma_mask = ~(u32)0;
 
-struct platform_device pxa_device_udc = {
-        .name           = "pxa2xx-udc",
+struct platform_device pxa25x_device_udc = {
+        .name           = "pxa25x-udc",
+        .id             = -1,
+        .resource       = pxa2xx_udc_resources,
+        .num_resources  = ARRAY_SIZE(pxa2xx_udc_resources),
+        .dev            =  {
+                .platform_data  = &pxa_udc_info,
+                .dma_mask       = &udc_dma_mask,
+        }
+};
+
+struct platform_device pxa27x_device_udc = {
+        .name           = "pxa27x-udc",
         .id             = -1,
         .resource       = pxa2xx_udc_resources,
         .num_resources  = ARRAY_SIZE(pxa2xx_udc_resources),
@@ -233,8 +247,15 @@ struct platform_device pxa_device_i2c = {
         .num_resources  = ARRAY_SIZE(pxai2c_resources),
 };
 
+static unsigned long pxa27x_i2c_mfp_cfg[] = {
+        GPIO117_I2C_SCL,
+        GPIO118_I2C_SDA,
+};
+
 void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
 {
+        if (cpu_is_pxa27x())
+                pxa2xx_mfp_config(ARRAY_AND_SIZE(pxa27x_i2c_mfp_cfg));
         pxa_register_device(&pxa_device_i2c, info);
 }
 
@@ -278,8 +299,69 @@ struct platform_device pxa_device_rtc = {
         .id             = -1,
 };
 
+static struct resource pxa_ac97_resources[] = {
+        [0] = {
+                .start  = 0x40500000,
+                .end    = 0x40500000 + 0xfff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_AC97,
+                .end    = IRQ_AC97,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static u64 pxa_ac97_dmamask = 0xffffffffUL;
+
+struct platform_device pxa_device_ac97 = {
+        .name           = "pxa2xx-ac97",
+        .id             = -1,
+        .dev            = {
+                .dma_mask = &pxa_ac97_dmamask,
+                .coherent_dma_mask = 0xffffffff,
+        },
+        .num_resources  = ARRAY_SIZE(pxa_ac97_resources),
+        .resource       = pxa_ac97_resources,
+};
+
+void __init pxa_set_ac97_info(pxa2xx_audio_ops_t *ops)
+{
+        pxa_register_device(&pxa_device_ac97, ops);
+}
+
 #ifdef CONFIG_PXA25x
 
+static struct resource pxa25x_resource_pwm0[] = {
+        [0] = {
+                .start  = 0x40b00000,
+                .end    = 0x40b0000f,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+struct platform_device pxa25x_device_pwm0 = {
+        .name           = "pxa25x-pwm",
+        .id             = 0,
+        .resource       = pxa25x_resource_pwm0,
+        .num_resources  = ARRAY_SIZE(pxa25x_resource_pwm0),
+};
+
+static struct resource pxa25x_resource_pwm1[] = {
+        [0] = {
+                .start  = 0x40c00000,
+                .end    = 0x40c0000f,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+struct platform_device pxa25x_device_pwm1 = {
+        .name           = "pxa25x-pwm",
+        .id             = 1,
+        .resource       = pxa25x_resource_pwm1,
+        .num_resources  = ARRAY_SIZE(pxa25x_resource_pwm1),
+};
+
 static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);
 
 static struct resource pxa25x_resource_ssp[] = {
@@ -568,6 +650,36 @@ struct platform_device pxa27x_device_ssp3 = {
         .num_resources  = ARRAY_SIZE(pxa27x_resource_ssp3),
 };
 
+static struct resource pxa27x_resource_pwm0[] = {
+        [0] = {
+                .start  = 0x40b00000,
+                .end    = 0x40b0001f,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+struct platform_device pxa27x_device_pwm0 = {
+        .name           = "pxa27x-pwm",
+        .id             = 0,
+        .resource       = pxa27x_resource_pwm0,
+        .num_resources  = ARRAY_SIZE(pxa27x_resource_pwm0),
+};
+
+static struct resource pxa27x_resource_pwm1[] = {
+        [0] = {
+                .start  = 0x40c00000,
+                .end    = 0x40c0001f,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+struct platform_device pxa27x_device_pwm1 = {
+        .name           = "pxa27x-pwm",
+        .id             = 1,
+        .resource       = pxa27x_resource_pwm1,
+        .num_resources  = ARRAY_SIZE(pxa27x_resource_pwm1),
+};
+
 static struct resource pxa27x_resource_camera[] = {
         [0] = {
                 .start  = 0x50000000,
diff --git a/arch/arm/mach-pxa/devices.h b/arch/arm/mach-pxa/devices.h
index fcab017f27ee..b852eb18daa5 100644
--- a/arch/arm/mach-pxa/devices.h
+++ b/arch/arm/mach-pxa/devices.h
@@ -1,7 +1,8 @@
 extern struct platform_device pxa_device_mci;
 extern struct platform_device pxa3xx_device_mci2;
 extern struct platform_device pxa3xx_device_mci3;
-extern struct platform_device pxa_device_udc;
+extern struct platform_device pxa25x_device_udc;
+extern struct platform_device pxa27x_device_udc;
 extern struct platform_device pxa_device_fb;
 extern struct platform_device pxa_device_ffuart;
 extern struct platform_device pxa_device_btuart;
@@ -11,6 +12,7 @@ extern struct platform_device pxa_device_i2c;
 extern struct platform_device pxa_device_i2s;
 extern struct platform_device pxa_device_ficp;
 extern struct platform_device pxa_device_rtc;
+extern struct platform_device pxa_device_ac97;
 
 extern struct platform_device pxa27x_device_i2c_power;
 extern struct platform_device pxa27x_device_ohci;
@@ -24,4 +26,9 @@ extern struct platform_device pxa27x_device_ssp2;
 extern struct platform_device pxa27x_device_ssp3;
 extern struct platform_device pxa3xx_device_ssp4;
 
+extern struct platform_device pxa25x_device_pwm0;
+extern struct platform_device pxa25x_device_pwm1;
+extern struct platform_device pxa27x_device_pwm0;
+extern struct platform_device pxa27x_device_pwm1;
+
 void __init pxa_register_device(struct platform_device *dev, void *data);
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
index 9c57700ee5c2..1bf680749928 100644
--- a/arch/arm/mach-pxa/em-x270.c
+++ b/arch/arm/mach-pxa/em-x270.c
@@ -24,6 +24,8 @@
 
 #include <asm/arch/pxa-regs.h>
 #include <asm/arch/pxa2xx-gpio.h>
+#include <asm/arch/pxa27x-udc.h>
+#include <asm/arch/audio.h>
 #include <asm/arch/pxafb.h>
 #include <asm/arch/ohci.h>
 #include <asm/arch/mmc.h>
@@ -72,12 +74,6 @@ static struct platform_device em_x270_dm9k = {
         }
 };
 
-/* audio device */
-static struct platform_device em_x270_audio = {
-        .name           = "pxa2xx-ac97",
-        .id             = -1,
-};
-
 /* WM9712 touchscreen controller. Hopefully the driver will make it to
  * the mainstream sometime */
 static struct platform_device em_x270_ts = {
@@ -217,7 +213,6 @@ static struct platform_device em_x270_nand = {
 /* platform devices */
 static struct platform_device *platform_devices[] __initdata = {
         &em_x270_dm9k,
-        &em_x270_audio,
         &em_x270_ts,
         &em_x270_rtc,
         &em_x270_nand,
@@ -325,6 +320,7 @@ static void __init em_x270_init(void)
 
         /* register EM-X270 platform devices */
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+        pxa_set_ac97_info(NULL);
 
         /* set MCI and OHCI platform parameters */
         pxa_set_mci_info(&em_x270_mci_platform_data);
diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c
index 44617938f3f1..ca053226fba0 100644
--- a/arch/arm/mach-pxa/generic.c
+++ b/arch/arm/mach-pxa/generic.c
@@ -60,23 +60,6 @@ unsigned int get_memclk_frequency_10khz(void)
 EXPORT_SYMBOL(get_memclk_frequency_10khz);
 
 /*
- * Routine to safely enable or disable a clock in the CKEN
- */
-void __pxa_set_cken(int clock, int enable)
-{
-        unsigned long flags;
-        local_irq_save(flags);
-
-        if (enable)
-                CKEN |= (1 << clock);
-        else
-                CKEN &= ~(1 << clock);
-
-        local_irq_restore(flags);
-}
-EXPORT_SYMBOL(__pxa_set_cken);
-
-/*
  * Intel PXA2xx internal register mapping.
  *
  * Note 1: not all PXA2xx variants implement all those addresses.
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c
index a9a0c3fab159..fbff557bb225 100644
--- a/arch/arm/mach-pxa/irq.c
+++ b/arch/arm/mach-pxa/irq.c
@@ -21,7 +21,6 @@
 #include <asm/irq.h>
 #include <asm/mach/irq.h>
 #include <asm/arch/pxa-regs.h>
-#include <asm/arch/pxa2xx-gpio.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c
index a20e4b1649d6..cc1c4fa06145 100644
--- a/arch/arm/mach-pxa/lpd270.c
+++ b/arch/arm/mach-pxa/lpd270.c
@@ -23,6 +23,7 @@
 #include <linux/ioport.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
+#include <linux/pwm_backlight.h>
 
 #include <asm/types.h>
 #include <asm/setup.h>
@@ -134,9 +135,12 @@ static struct sys_device lpd270_irq_device = {
 
 static int __init lpd270_irq_device_init(void)
 {
-        int ret = sysdev_class_register(&lpd270_irq_sysclass);
-        if (ret == 0)
-                ret = sysdev_register(&lpd270_irq_device);
+        int ret = -ENODEV;
+        if (machine_is_logicpd_pxa270()) {
+                ret = sysdev_class_register(&lpd270_irq_sysclass);
+                if (ret == 0)
+                        ret = sysdev_register(&lpd270_irq_device);
+        }
         return ret;
 }
 
@@ -164,11 +168,6 @@ static struct platform_device smc91x_device = {
         .resource       = smc91x_resources,
 };
 
-static struct platform_device lpd270_audio_device = {
-        .name           = "pxa2xx-ac97",
-        .id             = -1,
-};
-
 static struct resource lpd270_flash_resources[] = {
         [0] = {
                 .start  = PXA_CS0_PHYS,
@@ -233,21 +232,20 @@ static struct platform_device lpd270_flash_device[2] = {
         },
 };
 
-static void lpd270_backlight_power(int on)
-{
-        if (on) {
-                pxa_gpio_mode(GPIO16_PWM0_MD);
-                pxa_set_cken(CKEN_PWM0, 1);
-                PWM_CTRL0 = 0;
-                PWM_PWDUTY0 = 0x3ff;
-                PWM_PERVAL0 = 0x3ff;
-        } else {
-                PWM_CTRL0 = 0;
-                PWM_PWDUTY0 = 0x0;
-                PWM_PERVAL0 = 0x3FF;
-                pxa_set_cken(CKEN_PWM0, 0);
-        }
-}
+static struct platform_pwm_backlight_data lpd270_backlight_data = {
+        .pwm_id         = 0,
+        .max_brightness = 1,
+        .dft_brightness = 1,
+        .pwm_period_ns  = 78770,
+};
+
+static struct platform_device lpd270_backlight_device = {
+        .name           = "pwm-backlight",
+        .dev            = {
+                .parent = &pxa27x_device_pwm0.dev,
+                .platform_data = &lpd270_backlight_data,
+        },
+};
 
 /* 5.7" TFT QVGA (LoLo display number 1) */
 static struct pxafb_mode_info sharp_lq057q3dc02_mode = {
@@ -269,7 +267,6 @@ static struct pxafb_mach_info sharp_lq057q3dc02 = {
         .num_modes              = 1,
         .lccr0                  = 0x07800080,
         .lccr3                  = 0x00400000,
-        .pxafb_backlight_power  = lpd270_backlight_power,
 };
 
 /* 12.1" TFT SVGA (LoLo display number 2) */
@@ -292,7 +289,6 @@ static struct pxafb_mach_info sharp_lq121s1dg31 = {
         .num_modes              = 1,
         .lccr0                  = 0x07800080,
         .lccr3                  = 0x00400000,
-        .pxafb_backlight_power  = lpd270_backlight_power,
 };
 
 /* 3.6" TFT QVGA (LoLo display number 3) */
@@ -315,7 +311,6 @@ static struct pxafb_mach_info sharp_lq036q1da01 = {
         .num_modes              = 1,
         .lccr0                  = 0x07800080,
         .lccr3                  = 0x00400000,
-        .pxafb_backlight_power  = lpd270_backlight_power,
 };
 
 /* 6.4" TFT VGA (LoLo display number 5) */
@@ -338,7 +333,6 @@ static struct pxafb_mach_info sharp_lq64d343 = {
         .num_modes              = 1,
         .lccr0                  = 0x07800080,
         .lccr3                  = 0x00400000,
-        .pxafb_backlight_power  = lpd270_backlight_power,
 };
 
 /* 10.4" TFT VGA (LoLo display number 7) */
@@ -361,7 +355,6 @@ static struct pxafb_mach_info sharp_lq10d368 = {
         .num_modes              = 1,
         .lccr0                  = 0x07800080,
         .lccr3                  = 0x00400000,
-        .pxafb_backlight_power  = lpd270_backlight_power,
 };
 
 /* 3.5" TFT QVGA (LoLo display number 8) */
@@ -384,7 +377,6 @@ static struct pxafb_mach_info sharp_lq035q7db02_20 = {
         .num_modes              = 1,
         .lccr0                  = 0x07800080,
         .lccr3                  = 0x00400000,
-        .pxafb_backlight_power  = lpd270_backlight_power,
 };
 
 static struct pxafb_mach_info *lpd270_lcd_to_use;
@@ -414,7 +406,7 @@ __setup("lcd=", lpd270_set_lcd);
 
 static struct platform_device *platform_devices[] __initdata = {
         &smc91x_device,
-        &lpd270_audio_device,
+        &lpd270_backlight_device,
         &lpd270_flash_device[0],
         &lpd270_flash_device[1],
 };
@@ -454,9 +446,12 @@ static void __init lpd270_init(void)
          * On LogicPD PXA270, we route AC97_SYSCLK via GPIO45.
          */
         pxa_gpio_mode(GPIO45_SYSCLK_AC97_MD);
+        pxa_gpio_mode(GPIO16_PWM0_MD);
 
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 
+        pxa_set_ac97_info(NULL);
+
         if (lpd270_lcd_to_use != NULL)
                 set_pxa_fb_info(lpd270_lcd_to_use);
 
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c
index 7b9bdd0c6665..a3fae4139203 100644
--- a/arch/arm/mach-pxa/lubbock.c
+++ b/arch/arm/mach-pxa/lubbock.c
@@ -43,6 +43,7 @@
 #include <asm/arch/pxa-regs.h>
 #include <asm/arch/pxa2xx-regs.h>
 #include <asm/arch/mfp-pxa25x.h>
+#include <asm/arch/audio.h>
 #include <asm/arch/lubbock.h>
 #include <asm/arch/udc.h>
 #include <asm/arch/irda.h>
@@ -196,11 +197,6 @@ static struct pxa2xx_udc_mach_info udc_info __initdata = {
         // no D+ pullup; lubbock can't connect/disconnect in software
 };
 
-static struct platform_device lub_audio_device = {
-        .name           = "pxa2xx-ac97",
-        .id             = -1,
-};
-
 static struct resource sa1111_resources[] = {
         [0] = {
                 .start  = 0x10000000,
@@ -368,7 +364,6 @@ static struct platform_device lubbock_flash_device[2] = {
 
 static struct platform_device *devices[] __initdata = {
         &sa1111_device,
-        &lub_audio_device,
         &smc91x_device,
         &lubbock_flash_device[0],
         &lubbock_flash_device[1],
@@ -494,6 +489,7 @@ static void __init lubbock_init(void)
         set_pxa_fb_info(&sharp_lm8v31);
         pxa_set_mci_info(&lubbock_mci_platform_data);
         pxa_set_ficp_info(&lubbock_ficp_platform_data);
+        pxa_set_ac97_info(NULL);
 
         lubbock_flash_data[0].width = lubbock_flash_data[1].width =
                 (BOOT_DEF & 1) ? 2 : 4;
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c
index badba064dc04..01b2fa790217 100644
--- a/arch/arm/mach-pxa/magician.c
+++ b/arch/arm/mach-pxa/magician.c
@@ -25,6 +25,7 @@
 #include <linux/mtd/map.h>
 #include <linux/mtd/physmap.h>
 #include <linux/pda_power.h>
+#include <linux/pwm_backlight.h>
 
 #include <asm/gpio.h>
 #include <asm/hardware.h>
@@ -33,12 +34,14 @@
 #include <asm/arch/magician.h>
 #include <asm/arch/mfp-pxa27x.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-regs.h>
 #include <asm/arch/pxafb.h>
 #include <asm/arch/i2c.h>
 #include <asm/arch/mmc.h>
 #include <asm/arch/irda.h>
 #include <asm/arch/ohci.h>
 
+#include "devices.h"
 #include "generic.h"
 
 static unsigned long magician_pin_config[] = {
@@ -348,40 +351,58 @@ static struct pxafb_mach_info samsung_info = {
  * Backlight
  */
 
-static void magician_set_bl_intensity(int intensity)
+static int magician_backlight_init(struct device *dev)
 {
-        if (intensity) {
-                PWM_CTRL0 = 1;
-                PWM_PERVAL0 = 0xc8;
-                if (intensity > 0xc7) {
-                        PWM_PWDUTY0 = intensity - 0x48;
-                        gpio_set_value(EGPIO_MAGICIAN_BL_POWER2, 1);
-                } else {
-                        PWM_PWDUTY0 = intensity;
-                        gpio_set_value(EGPIO_MAGICIAN_BL_POWER2, 0);
-                }
-                gpio_set_value(EGPIO_MAGICIAN_BL_POWER, 1);
-                pxa_set_cken(CKEN_PWM0, 1);
+        int ret;
+
+        ret = gpio_request(EGPIO_MAGICIAN_BL_POWER, "BL_POWER");
+        if (ret)
+                goto err;
+        ret = gpio_request(EGPIO_MAGICIAN_BL_POWER2, "BL_POWER2");
+        if (ret)
+                goto err2;
+        return 0;
+
+err2:
+        gpio_free(EGPIO_MAGICIAN_BL_POWER);
+err:
+        return ret;
+}
+
+static int magician_backlight_notify(int brightness)
+{
+        gpio_set_value(EGPIO_MAGICIAN_BL_POWER, brightness);
+        if (brightness >= 200) {
+                gpio_set_value(EGPIO_MAGICIAN_BL_POWER2, 1);
+                return brightness - 72;
         } else {
-                /* PWM_PWDUTY0 = intensity; */
-                gpio_set_value(EGPIO_MAGICIAN_BL_POWER, 0);
-                pxa_set_cken(CKEN_PWM0, 0);
+                gpio_set_value(EGPIO_MAGICIAN_BL_POWER2, 0);
+                return brightness;
         }
 }
 
-static struct generic_bl_info backlight_info = {
-        .default_intensity = 0x64,
-        .limit_mask        = 0x0b,
-        .max_intensity     = 0xc7+0x48,
-        .set_bl_intensity  = magician_set_bl_intensity,
+static void magician_backlight_exit(struct device *dev)
+{
+        gpio_free(EGPIO_MAGICIAN_BL_POWER);
+        gpio_free(EGPIO_MAGICIAN_BL_POWER2);
+}
+
+static struct platform_pwm_backlight_data backlight_data = {
+        .pwm_id         = 0,
+        .max_brightness = 272,
+        .dft_brightness = 100,
+        .pwm_period_ns  = 30923,
+        .init           = magician_backlight_init,
+        .notify         = magician_backlight_notify,
+        .exit           = magician_backlight_exit,
 };
 
 static struct platform_device backlight = {
-        .name = "generic-bl",
+        .name = "pwm-backlight",
         .dev  = {
-                .platform_data = &backlight_info,
+                .parent        = &pxa27x_device_pwm0.dev,
+                .platform_data = &backlight_data,
         },
-        .id   = -1,
 };
 
 /*
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index 7399fb34da4e..f2e9e7c4da8e 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -23,9 +23,9 @@
 #include <linux/ioport.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
-#include <linux/backlight.h>
 #include <linux/input.h>
 #include <linux/gpio_keys.h>
+#include <linux/pwm_backlight.h>
 
 #include <asm/types.h>
 #include <asm/setup.h>
@@ -280,12 +280,6 @@ static pxa2xx_audio_ops_t mst_audio_ops = {
         .resume         = mst_audio_resume,
 };
 
-static struct platform_device mst_audio_device = {
-        .name           = "pxa2xx-ac97",
-        .id             = -1,
-        .dev            = { .platform_data = &mst_audio_ops },
-};
-
 static struct resource flash_resources[] = {
         [0] = {
                 .start  = PXA_CS0_PHYS,
@@ -349,56 +343,27 @@ static struct platform_device mst_flash_device[2] = {
         },
 };
 
-#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
-static int mainstone_backlight_update_status(struct backlight_device *bl)
-{
-        int brightness = bl->props.brightness;
-
-        if (bl->props.power != FB_BLANK_UNBLANK ||
-            bl->props.fb_blank != FB_BLANK_UNBLANK)
-                brightness = 0;
-
-        if (brightness != 0)
-                pxa_set_cken(CKEN_PWM0, 1);
-
-        PWM_CTRL0 = 0;
-        PWM_PWDUTY0 = brightness;
-        PWM_PERVAL0 = bl->props.max_brightness;
-
-        if (brightness == 0)
-                pxa_set_cken(CKEN_PWM0, 0);
-        return 0; /* pointless return value */
-}
-
-static int mainstone_backlight_get_brightness(struct backlight_device *bl)
-{
-        return PWM_PWDUTY0;
-}
+#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
+static struct platform_pwm_backlight_data mainstone_backlight_data = {
+        .pwm_id         = 0,
+        .max_brightness = 1023,
+        .dft_brightness = 1023,
+        .pwm_period_ns  = 78770,
+};
 
-static /*const*/ struct backlight_ops mainstone_backlight_ops = {
-        .update_status  = mainstone_backlight_update_status,
-        .get_brightness = mainstone_backlight_get_brightness,
+static struct platform_device mainstone_backlight_device = {
+        .name           = "pwm-backlight",
+        .dev            = {
+                .parent = &pxa27x_device_pwm0.dev,
+                .platform_data = &mainstone_backlight_data,
+        },
 };
 
 static void __init mainstone_backlight_register(void)
 {
-        struct backlight_device *bl;
-
-        bl = backlight_device_register("mainstone-bl", &pxa_device_fb.dev,
-                                       NULL, &mainstone_backlight_ops);
-        if (IS_ERR(bl)) {
-                printk(KERN_ERR "mainstone: unable to register backlight: %ld\n",
-                       PTR_ERR(bl));
-                return;
-        }
-
-        /*
-         * broken design - register-then-setup interfaces are
-         * utterly broken by definition.
-         */
-        bl->props.max_brightness = 1023;
-        bl->props.brightness = 1023;
-        backlight_update_status(bl);
+        int ret = platform_device_register(&mainstone_backlight_device);
+        if (ret)
+                printk(KERN_ERR "mainstone: failed to register backlight device: %d\n", ret);
 }
 #else
 #define mainstone_backlight_register()  do { } while (0)
@@ -528,7 +493,6 @@ static struct platform_device mst_gpio_keys_device = {
 
 static struct platform_device *platform_devices[] __initdata = {
         &smc91x_device,
-        &mst_audio_device,
         &mst_flash_device[0],
         &mst_flash_device[1],
         &mst_gpio_keys_device,
@@ -638,6 +602,7 @@ static void __init mainstone_init(void)
         pxa_set_ficp_info(&mainstone_ficp_platform_data);
         pxa_set_ohci_info(&mainstone_ohci_platform_data);
         pxa_set_i2c_info(NULL);
+        pxa_set_ac97_info(&mst_audio_ops);
 
         mainstone_init_keypad();
 }
diff --git a/arch/arm/mach-pxa/mfp-pxa2xx.c b/arch/arm/mach-pxa/mfp-pxa2xx.c
index 22097a1707cc..d1cdb4ecb0b8 100644
--- a/arch/arm/mach-pxa/mfp-pxa2xx.c
+++ b/arch/arm/mach-pxa/mfp-pxa2xx.c
@@ -20,6 +20,7 @@
 
 #include <asm/arch/hardware.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-regs.h>
 #include <asm/arch/mfp-pxa2xx.h>
 
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c
index 49d951db0f3d..5d87c7c866e4 100644
--- a/arch/arm/mach-pxa/pcm990-baseboard.c
+++ b/arch/arm/mach-pxa/pcm990-baseboard.c
@@ -24,6 +24,7 @@
 #include <linux/platform_device.h>
 #include <linux/ide.h>
 #include <linux/i2c.h>
+#include <linux/pwm_backlight.h>
 
 #include <media/soc_camera.h>
 
@@ -33,12 +34,103 @@
 #include <asm/mach/map.h>
 #include <asm/arch/pxa-regs.h>
 #include <asm/arch/pxa2xx-gpio.h>
+#include <asm/arch/audio.h>
 #include <asm/arch/mmc.h>
 #include <asm/arch/ohci.h>
 #include <asm/arch/pcm990_baseboard.h>
+#include <asm/arch/pxafb.h>
+
+#include "devices.h"
 
 /*
- * The PCM-990 development baseboard uses PCM-027's hardeware in the
+ * pcm990_lcd_power - control power supply to the LCD
+ * @on: 0 = switch off, 1 = switch on
+ *
+ * Called by the pxafb driver
+ */
+#ifndef CONFIG_PCM990_DISPLAY_NONE
+static void pcm990_lcd_power(int on, struct fb_var_screeninfo *var)
+{
+        if (on) {
+                /* enable LCD-Latches
+                 * power on LCD
+                 */
+                __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG3) =
+                        PCM990_CTRL_LCDPWR + PCM990_CTRL_LCDON;
+        } else {
+                /* disable LCD-Latches
+                 * power off LCD
+                 */
+                __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG3) = 0x00;
+        }
+}
+#endif
+
+#if defined(CONFIG_PCM990_DISPLAY_SHARP)
+static struct pxafb_mode_info fb_info_sharp_lq084v1dg21 = {
+        .pixclock               = 28000,
+        .xres                   = 640,
+        .yres                   = 480,
+        .bpp                    = 16,
+        .hsync_len              = 20,
+        .left_margin            = 103,
+        .right_margin           = 47,
+        .vsync_len              = 6,
+        .upper_margin           = 28,
+        .lower_margin           = 5,
+        .sync                   = 0,
+        .cmap_greyscale         = 0,
+};
+
+static struct pxafb_mach_info pcm990_fbinfo __initdata = {
+        .modes                  = &fb_info_sharp_lq084v1dg21,
+        .num_modes              = 1,
+        .lccr0                  = LCCR0_PAS,
+        .lccr3                  = LCCR3_PCP,
+        .pxafb_lcd_power        = pcm990_lcd_power,
+};
+#elif defined(CONFIG_PCM990_DISPLAY_NEC)
+struct pxafb_mode_info fb_info_nec_nl6448bc20_18d = {
+        .pixclock               = 39720,
+        .xres                   = 640,
+        .yres                   = 480,
+        .bpp                    = 16,
+        .hsync_len              = 32,
+        .left_margin            = 16,
+        .right_margin           = 48,
+        .vsync_len              = 2,
+        .upper_margin           = 12,
+        .lower_margin           = 17,
+        .sync                   = 0,
+        .cmap_greyscale         = 0,
+};
+
+static struct pxafb_mach_info pcm990_fbinfo __initdata = {
+        .modes                  = &fb_info_nec_nl6448bc20_18d,
+        .num_modes              = 1,
+        .lccr0                  = LCCR0_Act,
+        .lccr3                  = LCCR3_PixFlEdg,
+        .pxafb_lcd_power        = pcm990_lcd_power,
+};
+#endif
+
+static struct platform_pwm_backlight_data pcm990_backlight_data = {
+        .pwm_id         = 0,
+        .max_brightness = 1023,
+        .dft_brightness = 1023,
+        .pwm_period_ns  = 78770,
+};
+
+static struct platform_device pcm990_backlight_device = {
+        .name           = "pwm-backlight",
+        .dev            = {
+                .parent = &pxa27x_device_pwm0.dev,
+                .platform_data = &pcm990_backlight_data,
+        },
+};
+
+/*
+ * The PCM-990 development baseboard uses PCM-027's hardware in the
  * following way:
  *
  * - LCD support is in use
@@ -333,36 +425,6 @@ static struct i2c_board_info __initdata pcm990_i2c_devices[] = {
 #endif /* CONFIG_VIDEO_PXA27x ||CONFIG_VIDEO_PXA27x_MODULE */
 
 /*
- * AC97 support
- * Note: The connected AC97 mixer also reports interrupts at PCM990_AC97_IRQ
- */
-static struct resource pxa27x_ac97_resources[] = {
-        [0] = {
-                .start  = 0x40500000,
-                .end    = 0x40500000 + 0xfff,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_AC97,
-                .end    = IRQ_AC97,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static u64 pxa_ac97_dmamask = 0xffffffffUL;
-
-static struct platform_device pxa27x_device_ac97 = {
-        .name           = "pxa2xx-ac97",
-        .id             = -1,
-        .dev            = {
-                .dma_mask = &pxa_ac97_dmamask,
-                .coherent_dma_mask = 0xffffffff,
-        },
-        .num_resources  = ARRAY_SIZE(pxa27x_ac97_resources),
-        .resource       = pxa27x_ac97_resources,
-};
-
-/*
  * enable generic access to the base board control CPLDs U6 and U7
  */
 static struct map_desc pcm990_io_desc[] __initdata = {
@@ -393,7 +455,11 @@ void __init pcm990_baseboard_init(void)
         /* register CPLD's IRQ controller */
         pcm990_init_irq();
 
-        platform_device_register(&pxa27x_device_ac97);
+#ifndef CONFIG_PCM990_DISPLAY_NONE
+        set_pxa_fb_info(&pcm990_fbinfo);
+#endif
+        pxa_gpio_mode(GPIO16_PWM0_MD);
+        platform_device_register(&pcm990_backlight_device);
 
         /* MMC */
         pxa_set_mci_info(&pcm990_mci_platform_data);
@@ -402,6 +468,7 @@ void __init pcm990_baseboard_init(void)
         pxa_set_ohci_info(&pcm990_ohci_platform_data);
 
         pxa_set_i2c_info(NULL);
+        pxa_set_ac97_info(NULL);
 
 #if defined(CONFIG_VIDEO_PXA27x) || defined(CONFIG_VIDEO_PXA27x_MODULE)
         pxa_set_camera_info(&pcm990_pxacamera_platform_data);
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index 0b30f25cff3c..f81c10cafd48 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -32,6 +32,7 @@
 #include <asm/mach/irq.h>
 
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-regs.h>
 #include <asm/arch/pxa2xx-gpio.h>
 #include <asm/arch/mmc.h>
 #include <asm/arch/udc.h>
diff --git a/arch/arm/mach-pxa/pwm.c b/arch/arm/mach-pxa/pwm.c
new file mode 100644
index 000000000000..ce28cd9fed16
--- /dev/null
+++ b/arch/arm/mach-pxa/pwm.c
@@ -0,0 +1,319 @@
+/*
+ * linux/arch/arm/mach-pxa/pwm.c
+ *
+ * simple driver for PWM (Pulse Width Modulator) controller
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * 2008-02-13   initial version
+ *              eric miao <eric.miao@marvell.com>
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/pwm.h>
+
+#include <asm/div64.h>
+#include <asm/arch/pxa-regs.h>
+
+/* PWM registers and bits definitions */
+#define PWMCR           (0x00)
+#define PWMDCR          (0x04)
+#define PWMPCR          (0x08)
+
+#define PWMCR_SD        (1 << 6)
+#define PWMDCR_FD       (1 << 10)
+
+struct pwm_device {
+        struct list_head        node;
+        struct platform_device *pdev;
+
+        const char      *label;
+        struct clk      *clk;
+        int             clk_enabled;
+        void __iomem    *mmio_base;
+
+        unsigned int    use_count;
+        unsigned int    pwm_id;
+};
+
+/*
+ * period_ns = 10^9 * (PRESCALE + 1) * (PV + 1) / PWM_CLK_RATE
+ * duty_ns   = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE
+ */
+int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
+{
+        unsigned long long c;
+        unsigned long period_cycles, prescale, pv, dc;
+
+        if (pwm == NULL || period_ns == 0 || duty_ns > period_ns)
+                return -EINVAL;
+
+        c = clk_get_rate(pwm->clk);
+        c = c * period_ns;
+        do_div(c, 1000000000);
+        period_cycles = c;
+
+        if (period_cycles < 0)
+                period_cycles = 1;
+        prescale = (period_cycles - 1) / 1024;
+        pv = period_cycles / (prescale + 1) - 1;
+
+        if (prescale > 63)
+                return -EINVAL;
+
+        if (duty_ns == period_ns)
+                dc = PWMDCR_FD;
+        else
+                dc = (pv + 1) * duty_ns / period_ns;
+
+        /* NOTE: the clock to PWM has to be enabled first
+         * before writing to the registers
+         */
+        clk_enable(pwm->clk);
+        __raw_writel(prescale, pwm->mmio_base + PWMCR);
+        __raw_writel(dc, pwm->mmio_base + PWMDCR);
+        __raw_writel(pv, pwm->mmio_base + PWMPCR);
+        clk_disable(pwm->clk);
+
+        return 0;
+}
+EXPORT_SYMBOL(pwm_config);
+
+int pwm_enable(struct pwm_device *pwm)
+{
+        int rc = 0;
+
+        if (!pwm->clk_enabled) {
+                rc = clk_enable(pwm->clk);
+                if (!rc)
+                        pwm->clk_enabled = 1;
+        }
+        return rc;
+}
+EXPORT_SYMBOL(pwm_enable);
+
+void pwm_disable(struct pwm_device *pwm)
+{
+        if (pwm->clk_enabled) {
+                clk_disable(pwm->clk);
+                pwm->clk_enabled = 0;
+        }
+}
+EXPORT_SYMBOL(pwm_disable);
+
+static DEFINE_MUTEX(pwm_lock);
+static LIST_HEAD(pwm_list);
+
+struct pwm_device *pwm_request(int pwm_id, const char *label)
+{
+        struct pwm_device *pwm;
+        int found = 0;
+
+        mutex_lock(&pwm_lock);
+
+        list_for_each_entry(pwm, &pwm_list, node) {
+                if (pwm->pwm_id == pwm_id) {
+                        found = 1;
+                        break;
+                }
+        }
+
+        if (found) {
+                if (pwm->use_count == 0) {
+                        pwm->use_count++;
+                        pwm->label = label;
+                } else
+                        pwm = ERR_PTR(-EBUSY);
+        } else
+                pwm = ERR_PTR(-ENOENT);
+
+        mutex_unlock(&pwm_lock);
+        return pwm;
+}
+EXPORT_SYMBOL(pwm_request);
+
+void pwm_free(struct pwm_device *pwm)
+{
+        mutex_lock(&pwm_lock);
+
+        if (pwm->use_count) {
+                pwm->use_count--;
+                pwm->label = NULL;
+        } else
+                pr_warning("PWM device already freed\n");
+
+        mutex_unlock(&pwm_lock);
+}
+EXPORT_SYMBOL(pwm_free);
+
+static inline void __add_pwm(struct pwm_device *pwm)
+{
+        mutex_lock(&pwm_lock);
+        list_add_tail(&pwm->node, &pwm_list);
+        mutex_unlock(&pwm_lock);
+}
+
+static struct pwm_device *pwm_probe(struct platform_device *pdev,
+                unsigned int pwm_id, struct pwm_device *parent_pwm)
+{
+        struct pwm_device *pwm;
+        struct resource *r;
+        int ret = 0;
+
+        pwm = kzalloc(sizeof(struct pwm_device), GFP_KERNEL);
+        if (pwm == NULL) {
+                dev_err(&pdev->dev, "failed to allocate memory\n");
+                return ERR_PTR(-ENOMEM);
+        }
+
+        pwm->clk = clk_get(&pdev->dev, "PWMCLK");
+        if (IS_ERR(pwm->clk)) {
+                ret = PTR_ERR(pwm->clk);
+                goto err_free;
+        }
+        pwm->clk_enabled = 0;
+
+        pwm->use_count = 0;
+        pwm->pwm_id = pwm_id;
+        pwm->pdev = pdev;
+
+        if (parent_pwm != NULL) {
+                /* registers for the second PWM has offset of 0x10 */
+                pwm->mmio_base = parent_pwm->mmio_base + 0x10;
+                __add_pwm(pwm);
+                return pwm;
+        }
+
+        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (r == NULL) {
+                dev_err(&pdev->dev, "no memory resource defined\n");
+                ret = -ENODEV;
+                goto err_free_clk;
+        }
+
+        r = request_mem_region(r->start, r->end - r->start + 1, pdev->name);
+        if (r == NULL) {
+                dev_err(&pdev->dev, "failed to request memory resource\n");
+                ret = -EBUSY;
+                goto err_free_clk;
+        }
+
+        pwm->mmio_base = ioremap(r->start, r->end - r->start + 1);
+        if (pwm->mmio_base == NULL) {
+                dev_err(&pdev->dev, "failed to ioremap() registers\n");
+                ret = -ENODEV;
+                goto err_free_mem;
+        }
+
+        __add_pwm(pwm);
+        platform_set_drvdata(pdev, pwm);
+        return pwm;
+
+err_free_mem:
+        release_mem_region(r->start, r->end - r->start + 1);
+err_free_clk:
+        clk_put(pwm->clk);
+err_free:
+        kfree(pwm);
+        return ERR_PTR(ret);
+}
+
+static int __devinit pxa25x_pwm_probe(struct platform_device *pdev)
+{
+        struct pwm_device *pwm = pwm_probe(pdev, pdev->id, NULL);
+
+        if (IS_ERR(pwm))
+                return PTR_ERR(pwm);
+
+        return 0;
+}
+
+static int __devinit pxa27x_pwm_probe(struct platform_device *pdev)
+{
+        struct pwm_device *pwm;
+
+        pwm = pwm_probe(pdev, pdev->id, NULL);
+        if (IS_ERR(pwm))
+                return PTR_ERR(pwm);
+
+        pwm = pwm_probe(pdev, pdev->id + 2, pwm);
+        if (IS_ERR(pwm))
+                return PTR_ERR(pwm);
+
+        return 0;
+}
+
+static int __devexit pwm_remove(struct platform_device *pdev)
+{
+        struct pwm_device *pwm;
+        struct resource *r;
+
+        pwm = platform_get_drvdata(pdev);
+        if (pwm == NULL)
+                return -ENODEV;
+
+        mutex_lock(&pwm_lock);
+        list_del(&pwm->node);
+        mutex_unlock(&pwm_lock);
+
+        iounmap(pwm->mmio_base);
+
+        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        release_mem_region(r->start, r->end - r->start + 1);
+
+        clk_put(pwm->clk);
+        kfree(pwm);
+        return 0;
+}
+
+static struct platform_driver pxa25x_pwm_driver = {
+        .driver         = {
+                .name   = "pxa25x-pwm",
+        },
+        .probe          = pxa25x_pwm_probe,
+        .remove         = __devexit_p(pwm_remove),
+};
+
+static struct platform_driver pxa27x_pwm_driver = {
+        .driver         = {
+                .name   = "pxa27x-pwm",
+        },
+        .probe          = pxa27x_pwm_probe,
+        .remove         = __devexit_p(pwm_remove),
+};
+
+static int __init pwm_init(void)
+{
+        int ret = 0;
+
+        ret = platform_driver_register(&pxa25x_pwm_driver);
+        if (ret) {
+                printk(KERN_ERR "failed to register pxa25x_pwm_driver\n");
+                return ret;
+        }
+
+        ret = platform_driver_register(&pxa27x_pwm_driver);
+        if (ret) {
+                printk(KERN_ERR "failed to register pxa27x_pwm_driver\n");
+                return ret;
+        }
+
+        return ret;
+}
+arch_initcall(pwm_init);
+
+static void __exit pwm_exit(void)
+{
+        platform_driver_unregister(&pxa25x_pwm_driver);
+        platform_driver_unregister(&pxa27x_pwm_driver);
+}
+module_exit(pwm_exit);
+
+MODULE_LICENSE("GPL v2");
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index e5b417d14bb0..4cd50e3005e9 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -26,6 +26,7 @@
 #include <asm/hardware.h>
 #include <asm/arch/irqs.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-regs.h>
 #include <asm/arch/mfp-pxa25x.h>
 #include <asm/arch/pm.h>
 #include <asm/arch/dma.h>
@@ -117,29 +118,35 @@ static struct clk pxa25x_hwuart_clk =
         INIT_CKEN("UARTCLK", HWUART, 14745600, 1, &pxa_device_hwuart.dev)
 ;
 
+/*
+ * PXA 2xx clock declarations. Order is important (see aliases below)
+ * Please be careful not to disrupt the ordering.
+ */
 static struct clk pxa25x_clks[] = {
         INIT_CK("LCDCLK", LCD, &clk_pxa25x_lcd_ops, &pxa_device_fb.dev),
         INIT_CKEN("UARTCLK", FFUART, 14745600, 1, &pxa_device_ffuart.dev),
         INIT_CKEN("UARTCLK", BTUART, 14745600, 1, &pxa_device_btuart.dev),
         INIT_CKEN("UARTCLK", STUART, 14745600, 1, NULL),
-        INIT_CKEN("UDCCLK", USB, 47923000, 5, &pxa_device_udc.dev),
+        INIT_CKEN("UDCCLK", USB, 47923000, 5, &pxa25x_device_udc.dev),
         INIT_CKEN("MMCCLK", MMC, 19169000, 0, &pxa_device_mci.dev),
         INIT_CKEN("I2CCLK", I2C, 31949000, 0, &pxa_device_i2c.dev),
 
         INIT_CKEN("SSPCLK",  SSP, 3686400, 0, &pxa25x_device_ssp.dev),
         INIT_CKEN("SSPCLK", NSSP, 3686400, 0, &pxa25x_device_nssp.dev),
         INIT_CKEN("SSPCLK", ASSP, 3686400, 0, &pxa25x_device_assp.dev),
+        INIT_CKEN("PWMCLK", PWM0, 3686400, 0, &pxa25x_device_pwm0.dev),
+        INIT_CKEN("PWMCLK", PWM1, 3686400, 0, &pxa25x_device_pwm1.dev),
 
         INIT_CKEN("AC97CLK",     AC97,     24576000, 0, NULL),
 
         /*
-        INIT_CKEN("PWMCLK",  PWM0, 3686400,  0, NULL),
-        INIT_CKEN("PWMCLK",  PWM0, 3686400,  0, NULL),
         INIT_CKEN("I2SCLK",  I2S,  14745600, 0, NULL),
         */
         INIT_CKEN("FICPCLK", FICP, 47923000, 0, NULL),
 };
 
+static struct clk gpio7_clk = INIT_CKOTHER("GPIO7_CK", &pxa25x_clks[4], NULL);
+
 #ifdef CONFIG_PM
 
 #define SAVE(x)         sleep_save[SLEEP_SAVE_##x] = x
@@ -260,7 +267,7 @@ void __init pxa25x_init_irq(void)
 }
 
 static struct platform_device *pxa25x_devices[] __initdata = {
-        &pxa_device_udc,
+        &pxa25x_device_udc,
         &pxa_device_ffuart,
         &pxa_device_btuart,
         &pxa_device_stuart,
@@ -269,6 +276,8 @@ static struct platform_device *pxa25x_devices[] __initdata = {
         &pxa25x_device_ssp,
         &pxa25x_device_nssp,
         &pxa25x_device_assp,
+        &pxa25x_device_pwm0,
+        &pxa25x_device_pwm1,
 };
 
 static struct sys_device pxa25x_sysdev[] = {
@@ -311,6 +320,8 @@ static int __init pxa25x_init(void)
         if (cpu_is_pxa25x())
                 ret = platform_device_register(&pxa_device_hwuart);
 
+        clks_register(&gpio7_clk, 1);
+
         return ret;
 }
 
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index 7e945836e129..d5d14ea33f27 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -146,7 +146,7 @@ static struct clk pxa27x_clks[] = {
 
         INIT_CKEN("I2SCLK",  I2S,  14682000, 0, &pxa_device_i2s.dev),
         INIT_CKEN("I2CCLK",  I2C,  32842000, 0, &pxa_device_i2c.dev),
-        INIT_CKEN("UDCCLK",  USB,  48000000, 5, &pxa_device_udc.dev),
+        INIT_CKEN("UDCCLK",  USB,  48000000, 5, &pxa27x_device_udc.dev),
         INIT_CKEN("MMCCLK",  MMC,  19500000, 0, &pxa_device_mci.dev),
         INIT_CKEN("FICPCLK", FICP, 48000000, 0, &pxa_device_ficp.dev),
 
@@ -157,12 +157,13 @@ static struct clk pxa27x_clks[] = {
         INIT_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev),
         INIT_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev),
         INIT_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev),
+        INIT_CKEN("PWMCLK", PWM0, 13000000, 0, &pxa27x_device_pwm0.dev),
+        INIT_CKEN("PWMCLK", PWM1, 13000000, 0, &pxa27x_device_pwm1.dev),
 
         INIT_CKEN("AC97CLK",     AC97,     24576000, 0, NULL),
         INIT_CKEN("AC97CONFCLK", AC97CONF, 24576000, 0, NULL),
 
         /*
-        INIT_CKEN("PWMCLK",  PWM0, 13000000, 0, NULL),
         INIT_CKEN("MSLCLK",  MSL,  48000000, 0, NULL),
         INIT_CKEN("USIMCLK", USIM, 48000000, 0, NULL),
         INIT_CKEN("MSTKCLK", MEMSTK, 19500000, 0, NULL),
@@ -349,11 +350,14 @@ struct platform_device pxa27x_device_i2c_power = {
 
 void __init pxa_set_i2c_power_info(struct i2c_pxa_platform_data *info)
 {
+        local_irq_disable();
+        PCFR |= PCFR_PI2CEN;
+        local_irq_enable();
         pxa27x_device_i2c_power.dev.platform_data = info;
 }
 
 static struct platform_device *devices[] __initdata = {
-        &pxa_device_udc,
+        &pxa27x_device_udc,
         &pxa_device_ffuart,
         &pxa_device_btuart,
         &pxa_device_stuart,
@@ -363,6 +367,8 @@ static struct platform_device *devices[] __initdata = {
         &pxa27x_device_ssp1,
         &pxa27x_device_ssp2,
         &pxa27x_device_ssp3,
+        &pxa27x_device_pwm0,
+        &pxa27x_device_pwm1,
 };
 
 static struct sys_device pxa27x_sysdev[] = {
diff --git a/arch/arm/mach-pxa/pxa2xx.c b/arch/arm/mach-pxa/pxa2xx.c
new file mode 100644
index 000000000000..d4f6415e8413
--- /dev/null
+++ b/arch/arm/mach-pxa/pxa2xx.c
@@ -0,0 +1,46 @@
+/*
+ * linux/arch/arm/mach-pxa/pxa2xx.c
+ *
+ * code specific to pxa2xx
+ *
+ * Copyright (C) 2008 Dmitry Baryshkov
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+
+#include <asm/arch/mfp-pxa2xx.h>
+#include <asm/arch/mfp-pxa25x.h>
+#include <asm/arch/irda.h>
+
+static unsigned long pxa2xx_mfp_fir[] = {
+        GPIO46_FICP_RXD,
+        GPIO47_FICP_TXD,
+};
+
+static unsigned long pxa2xx_mfp_sir[] = {
+        GPIO46_STUART_RXD,
+        GPIO47_STUART_TXD,
+};
+
+static unsigned long pxa2xx_mfp_off[] = {
+        GPIO46_GPIO | MFP_LPM_DRIVE_LOW,
+        GPIO47_GPIO | MFP_LPM_DRIVE_LOW,
+};
+
+void pxa2xx_transceiver_mode(struct device *dev, int mode)
+{
+        if (mode & IR_OFF) {
+                pxa2xx_mfp_config(pxa2xx_mfp_off, ARRAY_SIZE(pxa2xx_mfp_off));
+        } else if (mode & IR_SIRMODE) {
+                pxa2xx_mfp_config(pxa2xx_mfp_sir, ARRAY_SIZE(pxa2xx_mfp_sir));
+        } else if (mode & IR_FIRMODE) {
+                pxa2xx_mfp_config(pxa2xx_mfp_fir, ARRAY_SIZE(pxa2xx_mfp_fir));
+        } else
+                BUG();
+}
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index 644550bfa330..15685d2b8f8c 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -231,7 +231,7 @@ static struct clk pxa3xx_clks[] = {
         PXA3xx_CKEN("UARTCLK", STUART, 14857000, 1, NULL),
 
         PXA3xx_CKEN("I2CCLK", I2C,  32842000, 0, &pxa_device_i2c.dev),
-        PXA3xx_CKEN("UDCCLK", UDC,  48000000, 5, &pxa_device_udc.dev),
+        PXA3xx_CKEN("UDCCLK", UDC,  48000000, 5, &pxa27x_device_udc.dev),
         PXA3xx_CKEN("USBCLK", USBH, 48000000, 0, &pxa27x_device_ohci.dev),
         PXA3xx_CKEN("KBDCLK", KEYPAD,  32768, 0, &pxa27x_device_keypad.dev),
 
@@ -239,6 +239,8 @@ static struct clk pxa3xx_clks[] = {
         PXA3xx_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev),
         PXA3xx_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev),
         PXA3xx_CKEN("SSPCLK", SSP4, 13000000, 0, &pxa3xx_device_ssp4.dev),
+        PXA3xx_CKEN("PWMCLK", PWM0, 13000000, 0, &pxa27x_device_pwm0.dev),
+        PXA3xx_CKEN("PWMCLK", PWM1, 13000000, 0, &pxa27x_device_pwm1.dev),
 
         PXA3xx_CKEN("MMCCLK", MMC1, 19500000, 0, &pxa_device_mci.dev),
         PXA3xx_CKEN("MMCCLK", MMC2, 19500000, 0, &pxa3xx_device_mci2.dev),
@@ -520,7 +522,7 @@ void __init pxa3xx_init_irq(void)
  */
 
 static struct platform_device *devices[] __initdata = {
-        &pxa_device_udc,
+/*      &pxa_device_udc,        The UDC driver is PXA25x only */
         &pxa_device_ffuart,
         &pxa_device_btuart,
         &pxa_device_stuart,
@@ -530,6 +532,8 @@ static struct platform_device *devices[] __initdata = {
         &pxa27x_device_ssp2,
         &pxa27x_device_ssp3,
         &pxa3xx_device_ssp4,
+        &pxa27x_device_pwm0,
+        &pxa27x_device_pwm1,
 };
 
 static struct sys_device pxa3xx_sysdev[] = {
diff --git a/arch/arm/mach-pxa/spitz_pm.c b/arch/arm/mach-pxa/spitz_pm.c
index 23f050feb208..360354084ae4 100644
--- a/arch/arm/mach-pxa/spitz_pm.c
+++ b/arch/arm/mach-pxa/spitz_pm.c
@@ -26,6 +26,7 @@
 #include <asm/arch/sharpsl.h>
 #include <asm/arch/spitz.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-regs.h>
 #include <asm/arch/pxa2xx-gpio.h>
 #include "sharpsl.h"
 
@@ -207,7 +208,9 @@ struct sharpsl_charger_machinfo spitz_pm_machinfo = {
         .read_devdata     = spitzpm_read_devdata,
         .charger_wakeup   = spitz_charger_wakeup,
         .should_wakeup    = spitz_should_wakeup,
+#ifdef CONFIG_BACKLIGHT_CORGI
         .backlight_limit  = corgibl_limit_intensity,
+#endif
         .charge_on_volt   = SHARPSL_CHARGE_ON_VOLT,
         .charge_on_temp   = SHARPSL_CHARGE_ON_TEMP,
         .charge_acin_high = SHARPSL_CHARGE_ON_ACIN_HIGH,
@@ -229,6 +232,10 @@ static int __devinit spitzpm_init(void)
 {
         int ret;
 
+        if (!machine_is_spitz() && !machine_is_akita()
+                        && !machine_is_borzoi())
+                return -ENODEV;
+
         spitzpm_device = platform_device_alloc("sharpsl-pm", -1);
         if (!spitzpm_device)
                 return -ENOMEM;
diff --git a/arch/arm/mach-pxa/standby.S b/arch/arm/mach-pxa/standby.S
index 167412e6bec8..40bb70eff3fe 100644
--- a/arch/arm/mach-pxa/standby.S
+++ b/arch/arm/mach-pxa/standby.S
@@ -14,6 +14,7 @@
 #include <asm/hardware.h>
 
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-regs.h>
 
                 .text
 
@@ -35,20 +36,20 @@ ENTRY(pxa_cpu_standby)
 
 #ifdef CONFIG_PXA3xx
 
-#define MDCNFG          0x0000
-#define MDCNFG_DMCEN    (1 << 30)
-#define DDR_HCAL        0x0060
-#define DDR_HCAL_HCRNG  0x1f
-#define DDR_HCAL_HCPROG (1 << 28)
-#define DDR_HCAL_HCEN   (1 << 31)
-#define DMCIER          0x0070
-#define DMCIER_EDLP     (1 << 29)
-#define DMCISR          0x0078
-#define RCOMP           0x0100
-#define RCOMP_SWEVAL    (1 << 31)
+#define PXA3_MDCNFG             0x0000
+#define PXA3_MDCNFG_DMCEN       (1 << 30)
+#define PXA3_DDR_HCAL           0x0060
+#define PXA3_DDR_HCAL_HCRNG     0x1f
+#define PXA3_DDR_HCAL_HCPROG    (1 << 28)
+#define PXA3_DDR_HCAL_HCEN      (1 << 31)
+#define PXA3_DMCIER             0x0070
+#define PXA3_DMCIER_EDLP        (1 << 29)
+#define PXA3_DMCISR             0x0078
+#define PXA3_RCOMP              0x0100
+#define PXA3_RCOMP_SWEVAL       (1 << 31)
 
 ENTRY(pm_enter_standby_start)
-        mov     r1, #0xf6000000         @ DMEMC_REG_BASE (MDCNFG)
+        mov     r1, #0xf6000000                 @ DMEMC_REG_BASE (PXA3_MDCNFG)
         add     r1, r1, #0x00100000
 
         /*
@@ -59,54 +60,54 @@ ENTRY(pm_enter_standby_start)
          * This also means that only the dynamic memory controller
          * can be reliably accessed in the code following standby.
          */
-        ldr     r2, [r1]                @ Dummy read MDCNFG
+        ldr     r2, [r1]                        @ Dummy read PXA3_MDCNFG
 
         mcr     p14, 0, r0, c7, c0, 0
         .rept   8
         nop
         .endr
 
-        ldr     r0, [r1, #DDR_HCAL]     @ Clear (and wait for) HCEN
-        bic     r0, r0, #DDR_HCAL_HCEN
-        str     r0, [r1, #DDR_HCAL]
-1:      ldr     r0, [r1, #DDR_HCAL]
-        tst     r0, #DDR_HCAL_HCEN
+        ldr     r0, [r1, #PXA3_DDR_HCAL]        @ Clear (and wait for) HCEN
+        bic     r0, r0, #PXA3_DDR_HCAL_HCEN
+        str     r0, [r1, #PXA3_DDR_HCAL]
+1:      ldr     r0, [r1, #PXA3_DDR_HCAL]
+        tst     r0, #PXA3_DDR_HCAL_HCEN
         bne     1b
 
-        ldr     r0, [r1, #RCOMP]        @ Initiate RCOMP
-        orr     r0, r0, #RCOMP_SWEVAL
-        str     r0, [r1, #RCOMP]
+        ldr     r0, [r1, #PXA3_RCOMP]           @ Initiate RCOMP
+        orr     r0, r0, #PXA3_RCOMP_SWEVAL
+        str     r0, [r1, #PXA3_RCOMP]
 
-        mov     r0, #~0                 @ Clear interrupts
-        str     r0, [r1, #DMCISR]
+        mov     r0, #~0                         @ Clear interrupts
+        str     r0, [r1, #PXA3_DMCISR]
 
-        ldr     r0, [r1, #DMCIER]       @ set DMIER[EDLP]
-        orr     r0, r0, #DMCIER_EDLP
-        str     r0, [r1, #DMCIER]
+        ldr     r0, [r1, #PXA3_DMCIER]          @ set DMIER[EDLP]
+        orr     r0, r0, #PXA3_DMCIER_EDLP
+        str     r0, [r1, #PXA3_DMCIER]
 
-        ldr     r0, [r1, #DDR_HCAL]     @ clear HCRNG, set HCPROG, HCEN
-        bic     r0, r0, #DDR_HCAL_HCRNG
-        orr     r0, r0, #DDR_HCAL_HCEN | DDR_HCAL_HCPROG
-        str     r0, [r1, #DDR_HCAL]
+        ldr     r0, [r1, #PXA3_DDR_HCAL]        @ clear HCRNG, set HCPROG, HCEN
+        bic     r0, r0, #PXA3_DDR_HCAL_HCRNG
+        orr     r0, r0, #PXA3_DDR_HCAL_HCEN | PXA3_DDR_HCAL_HCPROG
+        str     r0, [r1, #PXA3_DDR_HCAL]
 
-1:      ldr     r0, [r1, #DMCISR]
-        tst     r0, #DMCIER_EDLP
+1:      ldr     r0, [r1, #PXA3_DMCISR]
+        tst     r0, #PXA3_DMCIER_EDLP
         beq     1b
 
-        ldr     r0, [r1, #MDCNFG]       @ set MDCNFG[DMCEN]
-        orr     r0, r0, #MDCNFG_DMCEN
-        str     r0, [r1, #MDCNFG]
-1:      ldr     r0, [r1, #MDCNFG]
-        tst     r0, #MDCNFG_DMCEN
+        ldr     r0, [r1, #PXA3_MDCNFG]          @ set PXA3_MDCNFG[DMCEN]
+        orr     r0, r0, #PXA3_MDCNFG_DMCEN
+        str     r0, [r1, #PXA3_MDCNFG]
+1:      ldr     r0, [r1, #PXA3_MDCNFG]
+        tst     r0, #PXA3_MDCNFG_DMCEN
         beq     1b
 
-        ldr     r0, [r1, #DDR_HCAL]     @ set DDR_HCAL[HCRNG]
+        ldr     r0, [r1, #PXA3_DDR_HCAL]        @ set PXA3_DDR_HCAL[HCRNG]
         orr     r0, r0, #2 @ HCRNG
-        str     r0, [r1, #DDR_HCAL]
+        str     r0, [r1, #PXA3_DDR_HCAL]
 
-        ldr     r0, [r1, #DMCIER]       @ Clear the interrupt
+        ldr     r0, [r1, #PXA3_DMCIER]          @ Clear the interrupt
         bic     r0, r0, #0x20000000
-        str     r0, [r1, #DMCIER]
+        str     r0, [r1, #PXA3_DMCIER]
 
         mov     pc, lr
 ENTRY(pm_enter_standby_end)
diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c
index 931885d86b91..61e244023089 100644
--- a/arch/arm/mach-pxa/trizeps4.c
+++ b/arch/arm/mach-pxa/trizeps4.c
@@ -41,6 +41,7 @@
 #include <asm/mach/flash.h>
 
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-regs.h>
 #include <asm/arch/pxa2xx-gpio.h>
 #include <asm/arch/trizeps4.h>
 #include <asm/arch/audio.h>
@@ -175,19 +176,10 @@ static struct platform_device uart_devices = {
         .resource       = NULL,
 };
 
-/********************************************************************************************
- * PXA270 ac97 sound codec
- ********************************************************************************************/
-static struct platform_device ac97_audio_device = {
-        .name           = "pxa2xx-ac97",
-        .id             = -1,
-};
-
 static struct platform_device * trizeps4_devices[] __initdata = {
         &flash_device,
         &uart_devices,
         &dm9000_device,
-        &ac97_audio_device,
 };
 
 #ifdef CONFIG_MACH_TRIZEPS4_CONXS
@@ -438,6 +430,7 @@ static void __init trizeps4_init(void)
         pxa_set_mci_info(&trizeps4_mci_platform_data);
         pxa_set_ficp_info(&trizeps4_ficp_platform_data);
         pxa_set_ohci_info(&trizeps4_ohci_platform_data);
+        pxa_set_ac97_info(NULL);
 }
 
 static void __init trizeps4_map_io(void)
@@ -487,6 +480,7 @@ static void __init trizeps4_map_io(void)
         ConXS_BCR = trizeps_conxs_bcr;
 #endif
 
+#warning FIXME - accessing PM registers directly is deprecated
         PWER  = 0x00000002;
         PFER  = 0x00000000;
         PRER  = 0x00000002;
diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c
index 4a0028087ea6..66b446ca273d 100644
--- a/arch/arm/mach-pxa/zylonite.c
+++ b/arch/arm/mach-pxa/zylonite.c
@@ -18,22 +18,24 @@
 #include <linux/interrupt.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
+#include <linux/pwm_backlight.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/hardware.h>
+#include <asm/arch/audio.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/pxafb.h>
 #include <asm/arch/zylonite.h>
 #include <asm/arch/mmc.h>
 #include <asm/arch/pxa27x_keypad.h>
 
+#include "devices.h"
 #include "generic.h"
 
 #define MAX_SLOTS       3
 struct platform_mmc_slot zylonite_mmc_slot[MAX_SLOTS];
 
-int gpio_backlight;
 int gpio_eth_irq;
 
 int wm9713_irq;
@@ -62,10 +64,20 @@ static struct platform_device smc91x_device = {
 };
 
 #if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
-static void zylonite_backlight_power(int on)
-{
-        gpio_set_value(gpio_backlight, on);
-}
+static struct platform_pwm_backlight_data zylonite_backlight_data = {
+        .pwm_id         = 3,
+        .max_brightness = 100,
+        .dft_brightness = 100,
+        .pwm_period_ns  = 10000,
+};
+
+static struct platform_device zylonite_backlight_device = {
+        .name           = "pwm-backlight",
+        .dev            = {
+                .parent = &pxa27x_device_pwm1.dev,
+                .platform_data  = &zylonite_backlight_data,
+        },
+};
 
 static struct pxafb_mode_info toshiba_ltm035a776c_mode = {
         .pixclock               = 110000,
@@ -98,7 +110,6 @@ static struct pxafb_mode_info toshiba_ltm04c380k_mode = {
 static struct pxafb_mach_info zylonite_toshiba_lcd_info = {
         .num_modes              = 1,
         .lcd_conn               = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
-        .pxafb_backlight_power  = zylonite_backlight_power,
 };
 
 static struct pxafb_mode_info sharp_ls037_modes[] = {
@@ -134,13 +145,11 @@ static struct pxafb_mach_info zylonite_sharp_lcd_info = {
         .modes                  = sharp_ls037_modes,
         .num_modes              = 2,
         .lcd_conn               = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
-        .pxafb_backlight_power  = zylonite_backlight_power,
 };
 
 static void __init zylonite_init_lcd(void)
 {
-        /* backlight GPIO: output, default on */
-        gpio_direction_output(gpio_backlight, 1);
+        platform_device_register(&zylonite_backlight_device);
 
         if (lcd_id & 0x20) {
                 set_pxa_fb_info(&zylonite_sharp_lcd_info);
@@ -329,6 +338,7 @@ static void __init zylonite_init(void)
         smc91x_resources[1].end   = gpio_to_irq(gpio_eth_irq);
         platform_device_register(&smc91x_device);
 
+        pxa_set_ac97_info(NULL);
         zylonite_init_lcd();
         zylonite_init_mmc();
         zylonite_init_keypad();
diff --git a/arch/arm/mach-pxa/zylonite_pxa300.c b/arch/arm/mach-pxa/zylonite_pxa300.c
index 324fb9daae28..6f7ae972b8db 100644
--- a/arch/arm/mach-pxa/zylonite_pxa300.c
+++ b/arch/arm/mach-pxa/zylonite_pxa300.c
@@ -50,6 +50,7 @@ static mfp_cfg_t common_mfp_cfg[] __initdata = {
         GPIO75_LCD_BIAS,
         GPIO76_LCD_VSYNC,
         GPIO127_LCD_CS_N,
+        GPIO20_PWM3_OUT,        /* backlight */
 
         /* BTUART */
         GPIO111_UART2_RTS,
@@ -200,9 +201,6 @@ void __init zylonite_pxa300_init(void)
                 /* detect LCD panel */
                 zylonite_detect_lcd_panel();
 
-                /* GPIO pin assignment */
-                gpio_backlight = mfp_to_gpio(MFP_PIN_GPIO20);
-
                 /* MMC card detect & write protect for controller 0 */
                 zylonite_mmc_slot[0].gpio_cd  = EXT_GPIO(0);
                 zylonite_mmc_slot[0].gpio_wp  = EXT_GPIO(2);
diff --git a/arch/arm/mach-pxa/zylonite_pxa320.c b/arch/arm/mach-pxa/zylonite_pxa320.c
index 193d07903b06..2b4fc34919ac 100644
--- a/arch/arm/mach-pxa/zylonite_pxa320.c
+++ b/arch/arm/mach-pxa/zylonite_pxa320.c
@@ -49,6 +49,7 @@ static mfp_cfg_t mfp_cfg[] __initdata = {
         GPIO15_2_LCD_LCLK,
         GPIO16_2_LCD_PCLK,
         GPIO17_2_LCD_BIAS,
+        GPIO14_PWM3_OUT,        /* backlight */
 
         /* FFUART */
         GPIO41_UART1_RXD | MFP_LPM_EDGE_FALL,
@@ -187,7 +188,6 @@ void __init zylonite_pxa320_init(void)
                 zylonite_detect_lcd_panel();
 
                 /* GPIO pin assignment */
-                gpio_backlight  = mfp_to_gpio(MFP_PIN_GPIO14);
                 gpio_eth_irq    = mfp_to_gpio(MFP_PIN_GPIO9);
 
                 /* MMC card detect & write protect for controller 0 */
diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig
index cd3dc0834b3b..99fdc736698c 100644
--- a/arch/arm/mach-s3c2410/Kconfig
+++ b/arch/arm/mach-s3c2410/Kconfig
@@ -37,6 +37,17 @@ config S3C2410_CLOCK
         help
           Clock code for the S3C2410, and similar processors
 
+config SIMTEC_NOR
+        bool
+        help
+          Internal node to specify machine has simtec NOR mapping
+
+config MACH_BAST_IDE
+        bool
+        select HAVE_PATA_PLATFORM
+        help
+          Internal node for machines with an BAST style IDE
+          interface
 
 menu "S3C2410 Machines"
 
@@ -61,15 +72,18 @@ config PM_H1940
           Internal node for H1940 and related PM
 
 config MACH_N30
-        bool "Acer N30"
+        bool "Acer N30 family"
         select CPU_S3C2410
         help
-          Say Y here if you are using the Acer N30
+          Say Y here if you want suppt for the Acer N30, Acer N35,
+          Navman PiN570, Yakumo AlphaX or Airis NC05 PDAs.
 
 config ARCH_BAST
         bool "Simtec Electronics BAST (EB2410ITX)"
         select CPU_S3C2410
         select PM_SIMTEC if PM
+        select SIMTEC_NOR
+        select MACH_BAST_IDE
         select ISA
         help
           Say Y here if you are using the Simtec Electronics EB2410ITX
@@ -107,6 +121,8 @@ config MACH_TCT_HAMMER
 config MACH_VR1000
         bool "Thorcom VR1000"
         select PM_SIMTEC if PM
+        select SIMTEC_NOR
+        select MACH_BAST_IDE
         select CPU_S3C2410
         help
           Say Y here if you are using the Thorcom VR1000 board.
@@ -118,4 +134,3 @@ config MACH_QT2410
            Say Y here if you are using the Armzone QT2410
 
 endmenu
-
diff --git a/arch/arm/mach-s3c2410/Makefile b/arch/arm/mach-s3c2410/Makefile
index cabc13ce09e4..00f31f8c4e78 100644
--- a/arch/arm/mach-s3c2410/Makefile
+++ b/arch/arm/mach-s3c2410/Makefile
@@ -30,3 +30,11 @@ obj-$(CONFIG_BAST_PC104_IRQ)	+= bast-irq.o
 obj-$(CONFIG_MACH_TCT_HAMMER)   += mach-tct_hammer.o
 obj-$(CONFIG_MACH_VR1000)       += mach-vr1000.o usb-simtec.o
 obj-$(CONFIG_MACH_QT2410)       += mach-qt2410.o
+
+# Common bits of machine support
+
+obj-$(CONFIG_SIMTEC_NOR)        += nor-simtec.o
+
+# machine additions
+
+obj-$(CONFIG_MACH_BAST_IDE)     += bast-ide.o
diff --git a/arch/arm/mach-s3c2410/bast-ide.c b/arch/arm/mach-s3c2410/bast-ide.c
new file mode 100644
index 000000000000..df95fe37cdc8
--- /dev/null
+++ b/arch/arm/mach-s3c2410/bast-ide.c
@@ -0,0 +1,112 @@
+/* linux/arch/arm/mach-s3c2410/bast-ide.c
+ *
+ * Copyright 2007 Simtec Electronics
+ *      http://www.simtec.co.uk/products/EB2410ITX/
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+
+#include <linux/platform_device.h>
+#include <linux/ata_platform.h>
+
+#include <asm/mach-types.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/arch/map.h>
+#include <asm/arch/bast-map.h>
+#include <asm/arch/bast-irq.h>
+
+/* IDE ports */
+
+static struct pata_platform_info bast_ide_platdata = {
+        .ioport_shift   = 5,
+};
+
+#define IDE_CS  S3C2410_CS5
+
+static struct resource bast_ide0_resource[] = {
+        [0]     = {
+                .start  = IDE_CS + BAST_PA_IDEPRI,
+                .end    = IDE_CS + BAST_PA_IDEPRI + (8 * 0x20) - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1]     = {
+                .start  = IDE_CS + BAST_PA_IDEPRIAUX + (6 * 0x20) ,
+                .end    = IDE_CS + BAST_PA_IDEPRIAUX + (7 * 0x20) - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [2]     = {
+                .start  = IRQ_IDE0,
+                .end    = IRQ_IDE0,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device bast_device_ide0 = {
+        .name           = "pata_platform",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(bast_ide0_resource),
+        .resource       = bast_ide0_resource,
+        .dev            = {
+                .platform_data = &bast_ide_platdata,
+                .coherent_dma_mask = ~0,
+        }
+
+};
+
+static struct resource bast_ide1_resource[] = {
+        [0]     = {
+                .start  = IDE_CS + BAST_PA_IDESEC,
+                .end    = IDE_CS + BAST_PA_IDESEC + (8 * 0x20) - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1]     = {
+                .start  = IDE_CS + BAST_PA_IDESECAUX + (6 * 0x20),
+                .end    = IDE_CS + BAST_PA_IDESECAUX + (7 * 0x20) - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [2]     = {
+                .start  = IRQ_IDE1,
+                .end    = IRQ_IDE1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device bast_device_ide1 = {
+        .name           = "pata_platform",
+        .id             = 1,
+        .num_resources  = ARRAY_SIZE(bast_ide1_resource),
+        .resource       = bast_ide1_resource,
+        .dev            = {
+                .platform_data = &bast_ide_platdata,
+                .coherent_dma_mask = ~0,
+        }
+};
+
+static struct platform_device *bast_ide_devices[] __initdata = {
+        &bast_device_ide0,
+        &bast_device_ide1,
+};
+
+static __init int bast_ide_init(void)
+{
+        if (machine_is_bast() || machine_is_vr1000())
+                return platform_add_devices(bast_ide_devices,
+                                            ARRAY_SIZE(bast_ide_devices));
+
+        return 0;
+}
+
+fs_initcall(bast_ide_init);
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c
index 27f63d5d3a7b..965f27129707 100644
--- a/arch/arm/mach-s3c2410/mach-bast.c
+++ b/arch/arm/mach-s3c2410/mach-bast.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/mach-s3c2410/mach-bast.c
  *
- * Copyright (c) 2003-2005 Simtec Electronics
+ * Copyright (c) 2003-2005,2008 Simtec Electronics
  *   Ben Dooks <ben@simtec.co.uk>
  *
  * http://www.simtec.co.uk/products/EB2410ITX/
@@ -20,6 +20,8 @@
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
 #include <linux/dm9000.h>
+#include <linux/ata_platform.h>
+#include <linux/i2c.h>
 
 #include <net/ax88796.h>
 
@@ -56,7 +58,9 @@
 #include <asm/plat-s3c24xx/clock.h>
 #include <asm/plat-s3c24xx/devs.h>
 #include <asm/plat-s3c24xx/cpu.h>
+
 #include "usb-simtec.h"
+#include "nor-simtec.h"
 
 #define COPYRIGHT ", (c) 2004-2005 Simtec Electronics"
 
@@ -134,37 +138,21 @@ static struct map_desc bast_iodesc[] __initdata = {
   { VA_C2(BAST_VA_ISAIO),   PA_CS2(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
   { VA_C2(BAST_VA_ISAMEM),  PA_CS2(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
   { VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
-  { VA_C2(BAST_VA_IDEPRI),  PA_CS3(BAST_PA_IDEPRI),   SZ_1M,  MT_DEVICE },
-  { VA_C2(BAST_VA_IDESEC),  PA_CS3(BAST_PA_IDESEC),   SZ_1M,  MT_DEVICE },
-  { VA_C2(BAST_VA_IDEPRIAUX), PA_CS3(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
-  { VA_C2(BAST_VA_IDESECAUX), PA_CS3(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
 
   /* slow, word */
   { VA_C3(BAST_VA_ISAIO),   PA_CS3(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
   { VA_C3(BAST_VA_ISAMEM),  PA_CS3(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
   { VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
-  { VA_C3(BAST_VA_IDEPRI),  PA_CS3(BAST_PA_IDEPRI),   SZ_1M,  MT_DEVICE },
-  { VA_C3(BAST_VA_IDESEC),  PA_CS3(BAST_PA_IDESEC),   SZ_1M,  MT_DEVICE },
-  { VA_C3(BAST_VA_IDEPRIAUX), PA_CS3(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
-  { VA_C3(BAST_VA_IDESECAUX), PA_CS3(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
 
   /* fast, byte */
   { VA_C4(BAST_VA_ISAIO),   PA_CS4(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
   { VA_C4(BAST_VA_ISAMEM),  PA_CS4(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
   { VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
-  { VA_C4(BAST_VA_IDEPRI),  PA_CS5(BAST_PA_IDEPRI),   SZ_1M,  MT_DEVICE },
-  { VA_C4(BAST_VA_IDESEC),  PA_CS5(BAST_PA_IDESEC),   SZ_1M,  MT_DEVICE },
-  { VA_C4(BAST_VA_IDEPRIAUX), PA_CS5(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
-  { VA_C4(BAST_VA_IDESECAUX), PA_CS5(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
 
   /* fast, word */
   { VA_C5(BAST_VA_ISAIO),   PA_CS5(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
   { VA_C5(BAST_VA_ISAMEM),  PA_CS5(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
   { VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
-  { VA_C5(BAST_VA_IDEPRI),  PA_CS5(BAST_PA_IDEPRI),   SZ_1M,  MT_DEVICE },
-  { VA_C5(BAST_VA_IDESEC),  PA_CS5(BAST_PA_IDESEC),   SZ_1M,  MT_DEVICE },
-  { VA_C5(BAST_VA_IDEPRIAUX), PA_CS5(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
-  { VA_C5(BAST_VA_IDESECAUX), PA_CS5(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
 };
 
 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
@@ -218,23 +206,6 @@ static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
         }
 };
 
-/* NOR Flash on BAST board */
-
-static struct resource bast_nor_resource[] = {
-        [0] = {
-                .start = S3C2410_CS1 + 0x4000000,
-                .end   = S3C2410_CS1 + 0x4000000 + (32*1024*1024) - 1,
-                .flags = IORESOURCE_MEM,
-        }
-};
-
-static struct platform_device bast_device_nor = {
-        .name           = "bast-nor",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(bast_nor_resource),
-        .resource       = bast_nor_resource,
-};
-
 /* NAND Flash on BAST board */
 
 #ifdef CONFIG_PM
@@ -374,7 +345,7 @@ static struct resource bast_dm9k_resource[] = {
         [2] = {
                 .start = IRQ_DM9000,
                 .end   = IRQ_DM9000,
-                .flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH,
+                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
         }
 
 };
@@ -564,6 +535,18 @@ static struct s3c2410fb_mach_info __initdata bast_fb_info = {
         .default_display = 1,
 };
 
+/* I2C devices fitted. */
+
+static struct i2c_board_info bast_i2c_devs[] __initdata = {
+        {
+                I2C_BOARD_INFO("tlv320aic23", 0x1a),
+        }, {
+                I2C_BOARD_INFO("simtec-pmu", 0x6b),
+        }, {
+                I2C_BOARD_INFO("ch7013", 0x75),
+        },
+};
+
 /* Standard BAST devices */
 
 static struct platform_device *bast_devices[] __initdata = {
@@ -573,7 +556,6 @@ static struct platform_device *bast_devices[] __initdata = {
         &s3c_device_i2c,
         &s3c_device_rtc,
         &s3c_device_nand,
-        &bast_device_nor,
         &bast_device_dm9k,
         &bast_device_asix,
         &bast_device_axpp,
@@ -622,6 +604,11 @@ static void __init bast_init(void)
 
         s3c24xx_fb_set_platdata(&bast_fb_info);
         platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices));
+
+        i2c_register_board_info(0, bast_i2c_devs,
+                                ARRAY_SIZE(bast_i2c_devs));
+
+        nor_simtec_init();
 }
 
 MACHINE_START(BAST, "Simtec-BAST")
diff --git a/arch/arm/mach-s3c2410/mach-n30.c b/arch/arm/mach-s3c2410/mach-n30.c
index 621f548da610..43c2e915c5bf 100644
--- a/arch/arm/mach-s3c2410/mach-n30.c
+++ b/arch/arm/mach-s3c2410/mach-n30.c
@@ -1,9 +1,10 @@
-/* linux/arch/arm/mach-s3c2410/mach-n30.c
+/* Machine specific code for the Acer n30, Acer N35, Navman PiN 570,
+ * Yakumo AlphaX and Airis NC05 PDAs.
  *
  * Copyright (c) 2003-2005 Simtec Electronics
  *      Ben Dooks <ben@simtec.co.uk>
  *
- * Copyright (c) 2005 Christer Weinigel <christer@weinigel.se>
+ * Copyright (c) 2005-2008 Christer Weinigel <christer@weinigel.se>
  *
  * There is a wiki with more information about the n30 port at
  * http://handhelds.org/moin/moin.cgi/AcerN30Documentation .
@@ -11,36 +12,42 @@
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
-*/
+ */
 
 #include <linux/kernel.h>
 #include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/timer.h>
-#include <linux/init.h>
+
 #include <linux/delay.h>
-#include <linux/serial_core.h>
+#include <linux/gpio_keys.h>
+#include <linux/init.h>
+#include <linux/input.h>
+#include <linux/interrupt.h>
 #include <linux/platform_device.h>
-#include <linux/kthread.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
+#include <linux/serial_core.h>
+#include <linux/timer.h>
 
 #include <asm/hardware.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
-#include <asm/plat-s3c/regs-serial.h>
+#include <asm/arch/fb.h>
+#include <asm/arch/leds-gpio.h>
 #include <asm/arch/regs-gpio.h>
+#include <asm/arch/regs-lcd.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/irq.h>
+#include <asm/mach/map.h>
+
 #include <asm/plat-s3c/iic.h>
+#include <asm/plat-s3c/regs-serial.h>
 
-#include <asm/plat-s3c24xx/s3c2410.h>
 #include <asm/plat-s3c24xx/clock.h>
-#include <asm/plat-s3c24xx/devs.h>
 #include <asm/plat-s3c24xx/cpu.h>
+#include <asm/plat-s3c24xx/devs.h>
+#include <asm/plat-s3c24xx/s3c2410.h>
+#include <asm/plat-s3c24xx/udc.h>
 
 static struct map_desc n30_iodesc[] __initdata = {
         /* nothing here yet */
@@ -64,7 +71,8 @@ static struct s3c2410_uartcfg n30_uartcfgs[] = {
                 .ulcon       = 0x43,
                 .ufcon       = 0x51,
         },
-        /* The BlueTooth controller is connected to port 2 */
+        /* On the N30 the bluetooth controller is connected here.
+         * On the N35 and variants the GPS receiver is connected here. */
         [2] = {
                 .hwport      = 2,
                 .flags       = 0,
@@ -74,13 +82,260 @@ static struct s3c2410_uartcfg n30_uartcfgs[] = {
         },
 };
 
+static void n30_udc_pullup(enum s3c2410_udc_cmd_e cmd)
+{
+        switch (cmd) {
+        case S3C2410_UDC_P_ENABLE :
+                s3c2410_gpio_setpin(S3C2410_GPB3, 1);
+                break;
+        case S3C2410_UDC_P_DISABLE :
+                s3c2410_gpio_setpin(S3C2410_GPB3, 0);
+                break;
+        case S3C2410_UDC_P_RESET :
+                break;
+        default:
+                break;
+        }
+}
+
+static struct s3c2410_udc_mach_info n30_udc_cfg __initdata = {
+        .udc_command            = n30_udc_pullup,
+        .vbus_pin               = S3C2410_GPG1,
+        .vbus_pin_inverted      = 0,
+};
+
+static struct gpio_keys_button n30_buttons[] = {
+        {
+                .gpio           = S3C2410_GPF0,
+                .code           = KEY_POWER,
+                .desc           = "Power",
+                .active_low     = 0,
+        },
+        {
+                .gpio           = S3C2410_GPG9,
+                .code           = KEY_UP,
+                .desc           = "Thumbwheel Up",
+                .active_low     = 0,
+        },
+        {
+                .gpio           = S3C2410_GPG8,
+                .code           = KEY_DOWN,
+                .desc           = "Thumbwheel Down",
+                .active_low     = 0,
+        },
+        {
+                .gpio           = S3C2410_GPG7,
+                .code           = KEY_ENTER,
+                .desc           = "Thumbwheel Press",
+                .active_low     = 0,
+        },
+        {
+                .gpio           = S3C2410_GPF7,
+                .code           = KEY_HOMEPAGE,
+                .desc           = "Home",
+                .active_low     = 0,
+        },
+        {
+                .gpio           = S3C2410_GPF6,
+                .code           = KEY_CALENDAR,
+                .desc           = "Calendar",
+                .active_low     = 0,
+        },
+        {
+                .gpio           = S3C2410_GPF5,
+                .code           = KEY_ADDRESSBOOK,
+                .desc           = "Contacts",
+                .active_low     = 0,
+        },
+        {
+                .gpio           = S3C2410_GPF4,
+                .code           = KEY_MAIL,
+                .desc           = "Mail",
+                .active_low     = 0,
+        },
+};
+
+static struct gpio_keys_platform_data n30_button_data = {
+        .buttons        = n30_buttons,
+        .nbuttons       = ARRAY_SIZE(n30_buttons),
+};
+
+static struct platform_device n30_button_device = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &n30_button_data,
+        }
+};
+
+static struct gpio_keys_button n35_buttons[] = {
+        {
+                .gpio           = S3C2410_GPF0,
+                .code           = KEY_POWER,
+                .desc           = "Power",
+                .active_low     = 0,
+        },
+        {
+                .gpio           = S3C2410_GPG9,
+                .code           = KEY_UP,
+                .desc           = "Joystick Up",
+                .active_low     = 0,
+        },
+        {
+                .gpio           = S3C2410_GPG8,
+                .code           = KEY_DOWN,
+                .desc           = "Joystick Down",
+                .active_low     = 0,
+        },
+        {
+                .gpio           = S3C2410_GPG6,
+                .code           = KEY_DOWN,
+                .desc           = "Joystick Left",
+                .active_low     = 0,
+        },
+        {
+                .gpio           = S3C2410_GPG5,
+                .code           = KEY_DOWN,
+                .desc           = "Joystick Right",
+                .active_low     = 0,
+        },
+        {
+                .gpio           = S3C2410_GPG7,
+                .code           = KEY_ENTER,
+                .desc           = "Joystick Press",
+                .active_low     = 0,
+        },
+        {
+                .gpio           = S3C2410_GPF7,
+                .code           = KEY_HOMEPAGE,
+                .desc           = "Home",
+                .active_low     = 0,
+        },
+        {
+                .gpio           = S3C2410_GPF6,
+                .code           = KEY_CALENDAR,
+                .desc           = "Calendar",
+                .active_low     = 0,
+        },
+        {
+                .gpio           = S3C2410_GPF5,
+                .code           = KEY_ADDRESSBOOK,
+                .desc           = "Contacts",
+                .active_low     = 0,
+        },
+        {
+                .gpio           = S3C2410_GPF4,
+                .code           = KEY_MAIL,
+                .desc           = "Mail",
+                .active_low     = 0,
+        },
+        {
+                .gpio           = S3C2410_GPF3,
+                .code           = SW_RADIO,
+                .desc           = "GPS Antenna",
+                .active_low     = 0,
+        },
+        {
+                .gpio           = S3C2410_GPG2,
+                .code           = SW_HEADPHONE_INSERT,
+                .desc           = "Headphone",
+                .active_low     = 0,
+        },
+};
+
+static struct gpio_keys_platform_data n35_button_data = {
+        .buttons        = n35_buttons,
+        .nbuttons       = ARRAY_SIZE(n35_buttons),
+};
+
+static struct platform_device n35_button_device = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .num_resources  = 0,
+        .dev            = {
+                .platform_data  = &n35_button_data,
+        }
+};
+
+/* This is the bluetooth LED on the device. */
+static struct s3c24xx_led_platdata n30_blue_led_pdata = {
+        .name           = "blue_led",
+        .gpio           = S3C2410_GPG6,
+        .def_trigger    = "",
+};
+
+/* This LED is driven by the battery microcontroller, and is blinking
+ * red, blinking green or solid green when the battery is low,
+ * charging or full respectively.  By driving GPD9 low, it's possible
+ * to force the LED to blink red, so call that warning LED.  */
+static struct s3c24xx_led_platdata n30_warning_led_pdata = {
+        .name           = "warning_led",
+        .flags          = S3C24XX_LEDF_ACTLOW,
+        .gpio           = S3C2410_GPD9,
+        .def_trigger    = "",
+};
+
+static struct platform_device n30_blue_led = {
+        .name           = "s3c24xx_led",
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &n30_blue_led_pdata,
+        },
+};
+
+static struct platform_device n30_warning_led = {
+        .name           = "s3c24xx_led",
+        .id             = 2,
+        .dev            = {
+                .platform_data  = &n30_warning_led_pdata,
+        },
+};
+
+static struct s3c2410fb_display n30_display __initdata = {
+        .type           = S3C2410_LCDCON1_TFT,
+        .width          = 240,
+        .height         = 320,
+        .pixclock       = 170000,
+
+        .xres           = 240,
+        .yres           = 320,
+        .bpp            = 16,
+        .left_margin    = 3,
+        .right_margin   = 40,
+        .hsync_len      = 40,
+        .upper_margin   = 2,
+        .lower_margin   = 3,
+        .vsync_len      = 2,
+
+        .lcdcon5 = S3C2410_LCDCON5_INVVLINE | S3C2410_LCDCON5_INVVFRAME,
+};
+
+static struct s3c2410fb_mach_info n30_fb_info __initdata = {
+        .displays       = &n30_display,
+        .num_displays   = 1,
+        .default_display = 0,
+        .lpcsel         = 0x06,
+};
+
 static struct platform_device *n30_devices[] __initdata = {
+        &s3c_device_lcd,
+        &s3c_device_wdt,
+        &s3c_device_i2c,
+        &s3c_device_iis,
         &s3c_device_usb,
+        &s3c_device_usbgadget,
+        &n30_button_device,
+        &n30_blue_led,
+        &n30_warning_led,
+};
+
+static struct platform_device *n35_devices[] __initdata = {
         &s3c_device_lcd,
         &s3c_device_wdt,
         &s3c_device_i2c,
         &s3c_device_iis,
         &s3c_device_usbgadget,
+        &n35_button_device,
 };
 
 static struct s3c2410_platform_i2c n30_i2ccfg = {
@@ -90,9 +345,148 @@ static struct s3c2410_platform_i2c n30_i2ccfg = {
         .max_freq       = 10*1000,
 };
 
+/* Lots of hardcoded stuff, but it sets up the hardware in a useful
+ * state so that we can boot Linux directly from flash. */
+static void __init n30_hwinit(void)
+{
+        /* GPA0-11 special functions -- unknown what they do
+         * GPA12 N30 special function -- unknown what it does
+         *       N35/PiN output -- unknown what it does
+         *
+         * A12 is nGCS1 on the N30 and an output on the N35/PiN.  I
+         * don't think it does anything useful on the N30, so I ought
+         * to make it an output there too since it always driven to 0
+         * as far as I can tell. */
+        if (machine_is_n30())
+                __raw_writel(0x007fffff, S3C2410_GPACON);
+        if (machine_is_n35())
+                __raw_writel(0x007fefff, S3C2410_GPACON);
+        __raw_writel(0x00000000, S3C2410_GPADAT);
+
+        /* GPB0 TOUT0 backlight level
+         * GPB1 output 1=backlight on
+         * GPB2 output IrDA enable 0=transceiver enabled, 1=disabled
+         * GPB3 output USB D+ pull up 0=disabled, 1=enabled
+         * GPB4 N30 output -- unknown function
+         *      N30/PiN GPS control 0=GPS enabled, 1=GPS disabled
+         * GPB5 output -- unknown function
+         * GPB6 input -- unknown function
+         * GPB7 output -- unknown function
+         * GPB8 output -- probably LCD driver enable
+         * GPB9 output -- probably LCD VSYNC driver enable
+         * GPB10 output -- probably LCD HSYNC driver enable
+         */
+        __raw_writel(0x00154556, S3C2410_GPBCON);
+        __raw_writel(0x00000750, S3C2410_GPBDAT);
+        __raw_writel(0x00000073, S3C2410_GPBUP);
+
+        /* GPC0 input RS232 DCD/DSR/RI
+         * GPC1 LCD
+         * GPC2 output RS232 DTR?
+         * GPC3 input RS232 DCD/DSR/RI
+         * GPC4 LCD
+         * GPC5 output 0=NAND write enabled, 1=NAND write protect
+         * GPC6 input -- unknown function
+         * GPC7 input charger status 0=charger connected
+         *      this input can be triggered by power on the USB device
+         *      port too, but will go back to disconnected soon after.
+         * GPC8 N30/N35 output -- unknown function, always driven to 1
+         *      PiN input -- unknown function, always read as 1
+         *      Make it an input with a pull up for all models.
+         * GPC9-15 LCD
+         */
+        __raw_writel(0xaaa80618, S3C2410_GPCCON);
+        __raw_writel(0x0000014c, S3C2410_GPCDAT);
+        __raw_writel(0x0000fef2, S3C2410_GPCUP);
+
+        /* GPD0 input -- unknown function
+         * GPD1-D7 LCD
+         * GPD8 N30 output -- unknown function
+         *      N35/PiN output 1=GPS LED on
+         * GPD9 output 0=power led blinks red, 1=normal power led function
+         * GPD10 output -- unknown function
+         * GPD11-15 LCD drivers
+         */
+        __raw_writel(0xaa95aaa4, S3C2410_GPDCON);
+        __raw_writel(0x00000601, S3C2410_GPDDAT);
+        __raw_writel(0x0000fbfe, S3C2410_GPDUP);
+
+        /* GPE0-4 I2S audio bus
+         * GPE5-10 SD/MMC bus
+         * E11-13 outputs -- unknown function, probably power management
+         * E14-15 I2C bus connected to the battery controller
+         */
+        __raw_writel(0xa56aaaaa, S3C2410_GPECON);
+        __raw_writel(0x0000efc5, S3C2410_GPEDAT);
+        __raw_writel(0x0000f81f, S3C2410_GPEUP);
+
+        /* GPF0  input 0=power button pressed
+         * GPF1  input SD/MMC switch 0=card present
+         * GPF2  N30 1=reset button pressed (inverted compared to the rest)
+         *       N35/PiN 0=reset button pressed
+         * GPF3  N30/PiN input -- unknown function
+         *       N35 input GPS antenna position, 0=antenna closed, 1=open
+         * GPF4  input 0=button 4 pressed
+         * GPF5  input 0=button 3 pressed
+         * GPF6  input 0=button 2 pressed
+         * GPF7  input 0=button 1 pressed
+         */
+        __raw_writel(0x0000aaaa, S3C2410_GPFCON);
+        __raw_writel(0x00000000, S3C2410_GPFDAT);
+        __raw_writel(0x000000ff, S3C2410_GPFUP);
+
+        /* GPG0  input RS232 DCD/DSR/RI
+         * GPG1  input 1=USB gadget port has power from a host
+         * GPG2  N30 input -- unknown function
+         *       N35/PiN input 0=headphones plugged in, 1=not plugged in
+         * GPG3  N30 output -- unknown function
+         *       N35/PiN input with unknown function
+         * GPG4  N30 output 0=MMC enabled, 1=MMC disabled
+         * GPG5  N30 output 0=BlueTooth chip disabled, 1=enabled
+         *       N35/PiN input joystick right
+         * GPG6  N30 output 0=blue led on, 1=off
+         *       N35/PiN input joystick left
+         * GPG7  input 0=thumbwheel pressed
+         * GPG8  input 0=thumbwheel down
+         * GPG9  input 0=thumbwheel up
+         * GPG10 input SD/MMC write protect switch
+         * GPG11 N30 input -- unknown function
+         *       N35 output 0=GPS antenna powered, 1=not powered
+         *       PiN output -- unknown function
+         * GPG12-15 touch screen functions
+         *
+         * The pullups differ between the models, so enable all
+         * pullups that are enabled on any of the models.
+         */
+        if (machine_is_n30())
+                __raw_writel(0xff0a956a, S3C2410_GPGCON);
+        if (machine_is_n35())
+                __raw_writel(0xff4aa92a, S3C2410_GPGCON);
+        __raw_writel(0x0000e800, S3C2410_GPGDAT);
+        __raw_writel(0x0000f86f, S3C2410_GPGUP);
+
+        /* GPH0/1/2/3 RS232 serial port
+         * GPH4/5 IrDA serial port
+         * GPH6/7  N30 BlueTooth serial port
+         *         N35/PiN GPS receiver
+         * GPH8 input -- unknown function
+         * GPH9 CLKOUT0 HCLK -- unknown use
+         * GPH10 CLKOUT1 FCLK -- unknown use
+         *
+         * The pull ups for H6/H7 are enabled on N30 but not on the
+         * N35/PiN.  I suppose is useful for a budget model of the N30
+         * with no bluetooh.  It doesn't hurt to have the pull ups
+         * enabled on the N35, so leave them enabled for all models.
+         */
+        __raw_writel(0x0028aaaa, S3C2410_GPHCON);
+        __raw_writel(0x000005ef, S3C2410_GPHDAT);
+        __raw_writel(0x0000063f, S3C2410_GPHUP);
+}
+
 static void __init n30_map_io(void)
 {
         s3c24xx_init_io(n30_iodesc, ARRAY_SIZE(n30_iodesc));
+        n30_hwinit();
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(n30_uartcfgs, ARRAY_SIZE(n30_uartcfgs));
 }
@@ -106,7 +500,9 @@ static void __init n30_init_irq(void)
 
 static void __init n30_init(void)
 {
+        s3c24xx_fb_set_platdata(&n30_fb_info);
         s3c_device_i2c.dev.platform_data = &n30_i2ccfg;
+        s3c24xx_udc_set_platdata(&n30_udc_cfg);
 
         /* Turn off suspend on both USB ports, and switch the
          * selectable USB port to USB device mode. */
@@ -115,7 +511,32 @@ static void __init n30_init(void)
                               S3C2410_MISCCR_USBSUSPND0 |
                               S3C2410_MISCCR_USBSUSPND1, 0x0);
 
-        platform_add_devices(n30_devices, ARRAY_SIZE(n30_devices));
+        if (machine_is_n30()) {
+                /* Turn off suspend on both USB ports, and switch the
+                 * selectable USB port to USB device mode. */
+                s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST |
+                                      S3C2410_MISCCR_USBSUSPND0 |
+                                      S3C2410_MISCCR_USBSUSPND1, 0x0);
+
+                platform_add_devices(n30_devices, ARRAY_SIZE(n30_devices));
+        }
+
+        if (machine_is_n35()) {
+                /* Turn off suspend and switch the selectable USB port
+                 * to USB device mode.  Turn on suspend for the host
+                 * port since it is not connected on the N35.
+                 *
+                 * Actually, the host port is available at some pads
+                 * on the back of the device, so it would actually be
+                 * possible to add a USB device inside the N35 if you
+                 * are willing to do some hardware modifications. */
+                s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST |
+                                      S3C2410_MISCCR_USBSUSPND0 |
+                                      S3C2410_MISCCR_USBSUSPND1,
+                                      S3C2410_MISCCR_USBSUSPND1);
+
+                platform_add_devices(n35_devices, ARRAY_SIZE(n35_devices));
+        }
 }
 
 MACHINE_START(N30, "Acer-N30")
@@ -131,9 +552,14 @@ MACHINE_START(N30, "Acer-N30")
         .map_io         = n30_map_io,
 MACHINE_END
 
-/*
-    Local variables:
-        compile-command: "make ARCH=arm CROSS_COMPILE=/usr/local/arm/3.3.2/bin/arm-linux- -k -C ../../.."
-        c-basic-offset: 8
-    End:
-*/
+MACHINE_START(N35, "Acer-N35")
+        /* Maintainer: Christer Weinigel <christer@weinigel.se>
+        */
+        .phys_io        = S3C2410_PA_UART,
+        .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
+        .boot_params    = S3C2410_SDRAM_PA + 0x100,
+        .timer          = &s3c24xx_timer,
+        .init_machine   = n30_init,
+        .init_irq       = n30_init_irq,
+        .map_io         = n30_map_io,
+MACHINE_END
diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c
index 4c4b5c4207c4..9a0965ac5e11 100644
--- a/arch/arm/mach-s3c2410/mach-vr1000.c
+++ b/arch/arm/mach-s3c2410/mach-vr1000.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/mach-s3c2410/mach-vr1000.c
  *
- * Copyright (c) 2003-2005 Simtec Electronics
+ * Copyright (c) 2003-2005,2008 Simtec Electronics
  *   Ben Dooks <ben@simtec.co.uk>
  *
  * Machine support for Thorcom VR1000 board. Designed for Thorcom by
@@ -19,6 +19,7 @@
 #include <linux/timer.h>
 #include <linux/init.h>
 #include <linux/dm9000.h>
+#include <linux/i2c.h>
 
 #include <linux/serial.h>
 #include <linux/tty.h>
@@ -46,7 +47,9 @@
 #include <asm/plat-s3c24xx/clock.h>
 #include <asm/plat-s3c24xx/devs.h>
 #include <asm/plat-s3c24xx/cpu.h>
+
 #include "usb-simtec.h"
+#include "nor-simtec.h"
 
 /* macros for virtual address mods for the io space entries */
 #define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
@@ -97,34 +100,6 @@ static struct map_desc vr1000_iodesc[] __initdata = {
           .length       = SZ_1M,
           .type         = MT_DEVICE,
   },
-
-  /* peripheral space... one for each of fast/slow/byte/16bit */
-  /* note, ide is only decoded in word space, even though some registers
-   * are only 8bit */
-
-  /* slow, byte */
-  { VA_C2(VR1000_VA_IDEPRI),  PA_CS3(VR1000_PA_IDEPRI),   SZ_1M,  MT_DEVICE },
-  { VA_C2(VR1000_VA_IDESEC),  PA_CS3(VR1000_PA_IDESEC),   SZ_1M,  MT_DEVICE },
-  { VA_C2(VR1000_VA_IDEPRIAUX), PA_CS3(VR1000_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
-  { VA_C2(VR1000_VA_IDESECAUX), PA_CS3(VR1000_PA_IDESECAUX), SZ_1M, MT_DEVICE },
-
-  /* slow, word */
-  { VA_C3(VR1000_VA_IDEPRI),  PA_CS3(VR1000_PA_IDEPRI),   SZ_1M,  MT_DEVICE },
-  { VA_C3(VR1000_VA_IDESEC),  PA_CS3(VR1000_PA_IDESEC),   SZ_1M,  MT_DEVICE },
-  { VA_C3(VR1000_VA_IDEPRIAUX), PA_CS3(VR1000_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
-  { VA_C3(VR1000_VA_IDESECAUX), PA_CS3(VR1000_PA_IDESECAUX), SZ_1M, MT_DEVICE },
-
-  /* fast, byte */
-  { VA_C4(VR1000_VA_IDEPRI),  PA_CS5(VR1000_PA_IDEPRI),   SZ_1M,  MT_DEVICE },
-  { VA_C4(VR1000_VA_IDESEC),  PA_CS5(VR1000_PA_IDESEC),   SZ_1M,  MT_DEVICE },
-  { VA_C4(VR1000_VA_IDEPRIAUX), PA_CS5(VR1000_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
-  { VA_C4(VR1000_VA_IDESECAUX), PA_CS5(VR1000_PA_IDESECAUX), SZ_1M, MT_DEVICE },
-
-  /* fast, word */
-  { VA_C5(VR1000_VA_IDEPRI),  PA_CS5(VR1000_PA_IDEPRI),   SZ_1M,  MT_DEVICE },
-  { VA_C5(VR1000_VA_IDESEC),  PA_CS5(VR1000_PA_IDESEC),   SZ_1M,  MT_DEVICE },
-  { VA_C5(VR1000_VA_IDEPRIAUX), PA_CS5(VR1000_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
-  { VA_C5(VR1000_VA_IDESECAUX), PA_CS5(VR1000_PA_IDESECAUX), SZ_1M, MT_DEVICE },
 };
 
 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
@@ -230,23 +205,6 @@ static struct platform_device serial_device = {
         },
 };
 
-/* MTD NOR Flash */
-
-static struct resource vr1000_nor_resource[] = {
-        [0] = {
-                .start  = S3C2410_CS1 + 0x4000000,
-                .end    = S3C2410_CS1 + 0x4000000 + SZ_16M - 1,
-                .flags  = IORESOURCE_MEM,
-        }
-};
-
-static struct platform_device vr1000_nor = {
-        .name           = "bast-nor",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(vr1000_nor_resource),
-        .resource       = vr1000_nor_resource,
-};
-
 /* DM9000 ethernet devices */
 
 static struct resource vr1000_dm9k0_resource[] = {
@@ -263,7 +221,7 @@ static struct resource vr1000_dm9k0_resource[] = {
         [2] = {
                 .start = IRQ_VR1000_DM9000A,
                 .end   = IRQ_VR1000_DM9000A,
-                .flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH,
+                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
         }
 
 };
@@ -282,7 +240,7 @@ static struct resource vr1000_dm9k1_resource[] = {
         [2] = {
                 .start = IRQ_VR1000_DM9000N,
                 .end   = IRQ_VR1000_DM9000N,
-                .flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH,
+                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
         }
 };
 
@@ -358,6 +316,18 @@ static struct platform_device vr1000_led3 = {
         },
 };
 
+/* I2C devices. */
+
+static struct i2c_board_info vr1000_i2c_devs[] __initdata = {
+        {
+                I2C_BOARD_INFO("tlv320aic23", 0x1a),
+        }, {
+                I2C_BOARD_INFO("tmp101", 0x48),
+        }, {
+                I2C_BOARD_INFO("m41st87", 0x68),
+        },
+};
+
 /* devices for this board */
 
 static struct platform_device *vr1000_devices[] __initdata = {
@@ -367,7 +337,6 @@ static struct platform_device *vr1000_devices[] __initdata = {
         &s3c_device_i2c,
         &s3c_device_adc,
         &serial_device,
-        &vr1000_nor,
         &vr1000_dm9k0,
         &vr1000_dm9k1,
         &vr1000_led1,
@@ -416,6 +385,11 @@ static void __init vr1000_map_io(void)
 static void __init vr1000_init(void)
 {
         platform_add_devices(vr1000_devices, ARRAY_SIZE(vr1000_devices));
+
+        i2c_register_board_info(0, vr1000_i2c_devs,
+                                ARRAY_SIZE(vr1000_i2c_devs));
+
+        nor_simtec_init();
 }
 
 MACHINE_START(VR1000, "Thorcom-VR1000")
diff --git a/arch/arm/mach-s3c2410/nor-simtec.c b/arch/arm/mach-s3c2410/nor-simtec.c
new file mode 100644
index 000000000000..f44e21b9c3ba
--- /dev/null
+++ b/arch/arm/mach-s3c2410/nor-simtec.c
@@ -0,0 +1,86 @@
+/* linux/arch/arm/mach-s3c2410/nor-simtec.c
+ *
+ * Copyright (c) 2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * Simtec NOR mapping
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/map.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/arch/map.h>
+#include <asm/arch/bast-map.h>
+#include <asm/arch/bast-cpld.h>
+
+
+static void simtec_nor_vpp(struct map_info *map, int vpp)
+{
+        unsigned int val;
+        unsigned long flags;
+
+        local_irq_save(flags);
+        val = __raw_readb(BAST_VA_CTRL3);
+
+        printk(KERN_DEBUG "%s(%d)\n", __func__, vpp);
+
+        if (vpp)
+                val |= BAST_CPLD_CTRL3_ROMWEN;
+        else
+                val &= ~BAST_CPLD_CTRL3_ROMWEN;
+
+        __raw_writeb(val, BAST_VA_CTRL3);
+        local_irq_restore(flags);
+}
+
+struct physmap_flash_data simtec_nor_pdata = {
+        .width          = 2,
+        .set_vpp        = simtec_nor_vpp,
+        .nr_parts       = 0,
+};
+
+static struct resource simtec_nor_resource[] = {
+        [0] = {
+                .start = S3C2410_CS1 + 0x4000000,
+                .end   = S3C2410_CS1 + 0x4000000 + SZ_8M - 1,
+                .flags = IORESOURCE_MEM,
+        }
+};
+
+static struct platform_device simtec_device_nor = {
+        .name           = "physmap-flash",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(simtec_nor_resource),
+        .resource       = simtec_nor_resource,
+        .dev            = {
+                .platform_data = &simtec_nor_pdata,
+        },
+};
+
+void __init nor_simtec_init(void)
+{
+        int ret;
+
+        ret = platform_device_register(&simtec_device_nor);
+        if (ret < 0)
+                printk(KERN_ERR "failed to register physmap-flash device\n");
+        else
+                simtec_nor_vpp(NULL, 1);
+}
diff --git a/arch/arm/mach-s3c2410/nor-simtec.h b/arch/arm/mach-s3c2410/nor-simtec.h
new file mode 100644
index 000000000000..f619c1e0d0c8
--- /dev/null
+++ b/arch/arm/mach-s3c2410/nor-simtec.h
@@ -0,0 +1,14 @@
+/* linux/arch/arm/mach-s3c2410/nor-simtec.h
+ *
+ * Copyright (c) 2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * Simtec NOR mapping
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+extern void nor_simtec_init(void);
diff --git a/arch/arm/mach-s3c2412/Kconfig b/arch/arm/mach-s3c2412/Kconfig
index 0b43431d4b75..c59a9d2ee9a6 100644
--- a/arch/arm/mach-s3c2412/Kconfig
+++ b/arch/arm/mach-s3c2412/Kconfig
@@ -34,6 +34,16 @@ config S3C2412_PM
 
 menu "S3C2412 Machines"
 
+config MACH_JIVE
+        bool "Logitech Jive"
+        select CPU_S3C2412
+        help
+          Say Y here if you are using the Logitech Jive.
+
+config MACH_JIVE_SHOW_BOOTLOADER
+        bool "Allow access to bootloader partitions in MTD"
+        depends on MACH_JIVE && EXPERIMENTAL
+
 config MACH_SMDK2413
         bool "SMDK2413"
         select CPU_S3C2412
diff --git a/arch/arm/mach-s3c2412/Makefile b/arch/arm/mach-s3c2412/Makefile
index 267f3348301e..20918d5dc6a9 100644
--- a/arch/arm/mach-s3c2412/Makefile
+++ b/arch/arm/mach-s3c2412/Makefile
@@ -18,5 +18,6 @@ obj-$(CONFIG_S3C2412_PM)	+= pm.o sleep.o
 
 # Machine support
 
+obj-$(CONFIG_MACH_JIVE)         += mach-jive.o
 obj-$(CONFIG_MACH_SMDK2413)     += mach-smdk2413.o
 obj-$(CONFIG_MACH_VSTMS)        += mach-vstms.o
diff --git a/arch/arm/mach-s3c2412/clock.c b/arch/arm/mach-s3c2412/clock.c
index 2697a65ba727..1157b5a16263 100644
--- a/arch/arm/mach-s3c2412/clock.c
+++ b/arch/arm/mach-s3c2412/clock.c
@@ -631,6 +631,17 @@ static struct clk_init clks_src[] __initdata = {
                 .bit    = S3C2412_CLKSRC_USBCLK_HCLK,
                 .src_0  = &clk_usysclk,
                 .src_1  = &clk_h,
+        /* here we assume  OM[4] select xtal */
+        }, {
+                .clk    = &clk_erefclk,
+                .bit    = S3C2412_CLKSRC_EREFCLK_EXTCLK,
+                .src_0  = &clk_xtal,
+                .src_1  = &clk_ext,
+        }, {
+                .clk    = &clk_urefclk,
+                .bit    = S3C2412_CLKSRC_UREFCLK_EXTCLK,
+                .src_0  = &clk_xtal,
+                .src_1  = &clk_ext,
         },
 };
 
@@ -666,8 +677,6 @@ static void __init s3c2412_clk_initparents(void)
 static struct clk *clks[] __initdata = {
         &clk_ext,
         &clk_usb_bus,
-        &clk_erefclk,
-        &clk_urefclk,
         &clk_mrefclk,
         &clk_armclk,
 };
diff --git a/arch/arm/mach-s3c2412/mach-jive.c b/arch/arm/mach-s3c2412/mach-jive.c
new file mode 100644
index 000000000000..7f5924713485
--- /dev/null
+++ b/arch/arm/mach-s3c2412/mach-jive.c
@@ -0,0 +1,687 @@
+/* linux/arch/arm/mach-s3c2410/mach-jive.c
+ *
+ * Copyright 2007 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/sysdev.h>
+#include <linux/delay.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+#include <linux/i2c.h>
+
+#include <video/ili9320.h>
+
+#include <linux/spi/spi.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/plat-s3c/regs-serial.h>
+#include <asm/plat-s3c/nand.h>
+#include <asm/plat-s3c/iic.h>
+
+#include <asm/arch/regs-power.h>
+#include <asm/arch/regs-gpio.h>
+#include <asm/arch/regs-mem.h>
+#include <asm/arch/regs-lcd.h>
+#include <asm/arch/spi-gpio.h>
+#include <asm/arch/fb.h>
+
+#include <asm/mach-types.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_ecc.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/plat-s3c24xx/clock.h>
+#include <asm/plat-s3c24xx/devs.h>
+#include <asm/plat-s3c24xx/cpu.h>
+#include <asm/plat-s3c24xx/pm.h>
+#include <asm/plat-s3c24xx/udc.h>
+
+static struct map_desc jive_iodesc[] __initdata = {
+};
+
+#define UCON S3C2410_UCON_DEFAULT
+#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE
+#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
+
+static struct s3c2410_uartcfg jive_uartcfgs[] = {
+        [0] = {
+                .hwport      = 0,
+                .flags       = 0,
+                .ucon        = UCON,
+                .ulcon       = ULCON,
+                .ufcon       = UFCON,
+        },
+        [1] = {
+                .hwport      = 1,
+                .flags       = 0,
+                .ucon        = UCON,
+                .ulcon       = ULCON,
+                .ufcon       = UFCON,
+        },
+        [2] = {
+                .hwport      = 2,
+                .flags       = 0,
+                .ucon        = UCON,
+                .ulcon       = ULCON,
+                .ufcon       = UFCON,
+        }
+};
+
+/* Jive flash assignment
+ *
+ * 0x00000000-0x00028000 : uboot
+ * 0x00028000-0x0002c000 : uboot env
+ * 0x0002c000-0x00030000 : spare
+ * 0x00030000-0x00200000 : zimage A
+ * 0x00200000-0x01600000 : cramfs A
+ * 0x01600000-0x017d0000 : zimage B
+ * 0x017d0000-0x02bd0000 : cramfs B
+ * 0x02bd0000-0x03fd0000 : yaffs
+ */
+static struct mtd_partition jive_imageA_nand_part[] = {
+
+#ifdef CONFIG_MACH_JIVE_SHOW_BOOTLOADER
+        /* Don't allow access to the bootloader from linux */
+        {
+                .name           = "uboot",
+                .offset         = 0,
+                .size           = (160 * SZ_1K),
+                .mask_flags     = MTD_WRITEABLE, /* force read-only */
+        },
+
+        /* spare */
+        {
+                .name           = "spare",
+                .offset         = (176 * SZ_1K),
+                .size           = (16 * SZ_1K),
+        },
+#endif
+
+        /* booted images */
+        {
+                .name           = "kernel (ro)",
+                .offset         = (192 * SZ_1K),
+                .size           = (SZ_2M) - (192 * SZ_1K),
+                .mask_flags     = MTD_WRITEABLE, /* force read-only */
+        }, {
+                .name           = "root (ro)",
+                .offset         = (SZ_2M),
+                .size           = (20 * SZ_1M),
+                .mask_flags     = MTD_WRITEABLE, /* force read-only */
+        },
+
+        /* yaffs */
+        {
+                .name           = "yaffs",
+                .offset         = (44 * SZ_1M),
+                .size           = (20 * SZ_1M),
+        },
+
+        /* bootloader environment */
+        {
+                .name           = "env",
+                .offset         = (160 * SZ_1K),
+                .size           = (16 * SZ_1K),
+        },
+
+        /* upgrade images */
+        {
+                .name           = "zimage",
+                .offset         = (22 * SZ_1M),
+                .size           = (2 * SZ_1M) - (192 * SZ_1K),
+        }, {
+                .name           = "cramfs",
+                .offset         = (24 * SZ_1M) - (192*SZ_1K),
+                .size           = (20 * SZ_1M),
+        },
+};
+
+static struct mtd_partition jive_imageB_nand_part[] = {
+
+#ifdef CONFIG_MACH_JIVE_SHOW_BOOTLOADER
+        /* Don't allow access to the bootloader from linux */
+        {
+                .name           = "uboot",
+                .offset         = 0,
+                .size           = (160 * SZ_1K),
+                .mask_flags     = MTD_WRITEABLE, /* force read-only */
+        },
+
+        /* spare */
+        {
+                .name           = "spare",
+                .offset         = (176 * SZ_1K),
+                .size           = (16 * SZ_1K),
+        },
+#endif
+
+        /* booted images */
+        {
+                .name           = "kernel (ro)",
+                .offset         = (22 * SZ_1M),
+                .size           = (2 * SZ_1M) - (192 * SZ_1K),
+                .mask_flags     = MTD_WRITEABLE, /* force read-only */
+        },
+        {
+                .name           = "root (ro)",
+                .offset         = (24 * SZ_1M) - (192 * SZ_1K),
+                .size           = (20 * SZ_1M),
+                .mask_flags     = MTD_WRITEABLE, /* force read-only */
+        },
+
+        /* yaffs */
+        {
+                .name           = "yaffs",
+                .offset         = (44 * SZ_1M),
+                .size           = (20 * SZ_1M),
+        },
+
+        /* bootloader environment */
+        {
+                .name           = "env",
+                .offset         = (160 * SZ_1K),
+                .size           = (16 * SZ_1K),
+        },
+
+        /* upgrade images */
+        {
+                .name           = "zimage",
+                .offset         = (192 * SZ_1K),
+                .size           = (2 * SZ_1M) - (192 * SZ_1K),
+        }, {
+                .name           = "cramfs",
+                .offset         = (2 * SZ_1M),
+                .size           = (20 * SZ_1M),
+        },
+};
+
+static struct s3c2410_nand_set jive_nand_sets[] = {
+        [0] = {
+                .name           = "flash",
+                .nr_chips       = 1,
+                .nr_partitions  = ARRAY_SIZE(jive_imageA_nand_part),
+                .partitions     = jive_imageA_nand_part,
+        },
+};
+
+static struct s3c2410_platform_nand jive_nand_info = {
+        /* set taken from osiris nand timings, possibly still conservative */
+        .tacls          = 30,
+        .twrph0         = 55,
+        .twrph1         = 40,
+        .sets           = jive_nand_sets,
+        .nr_sets        = ARRAY_SIZE(jive_nand_sets),
+};
+
+static int __init jive_mtdset(char *options)
+{
+        struct s3c2410_nand_set *nand = &jive_nand_sets[0];
+        unsigned long set;
+
+        if (options == NULL || options[0] == '\0')
+                return 0;
+
+        if (strict_strtoul(options, 10, &set)) {
+                printk(KERN_ERR "failed to parse mtdset=%s\n", options);
+                return 0;
+        }
+
+        switch (set) {
+        case 1:
+                nand->nr_partitions = ARRAY_SIZE(jive_imageB_nand_part);
+                nand->partitions = jive_imageB_nand_part;
+        case 0:
+                /* this is already setup in the nand info */
+                break;
+        default:
+                printk(KERN_ERR "Unknown mtd set %ld specified,"
+                       "using default.", set);
+        }
+
+        return 0;
+}
+
+/* parse the mtdset= option given to the kernel command line */
+__setup("mtdset=", jive_mtdset);
+
+/* LCD timing and setup */
+
+#define LCD_XRES         (240)
+#define LCD_YRES         (320)
+#define LCD_LEFT_MARGIN  (12)
+#define LCD_RIGHT_MARGIN (12)
+#define LCD_LOWER_MARGIN (12)
+#define LCD_UPPER_MARGIN (12)
+#define LCD_VSYNC        (2)
+#define LCD_HSYNC        (2)
+
+#define LCD_REFRESH      (60)
+
+#define LCD_HTOT (LCD_HSYNC + LCD_LEFT_MARGIN + LCD_XRES + LCD_RIGHT_MARGIN)
+#define LCD_VTOT (LCD_VSYNC + LCD_LOWER_MARGIN + LCD_YRES + LCD_UPPER_MARGIN)
+
+struct s3c2410fb_display jive_vgg2432a4_display[] = {
+        [0] = {
+                .width          = LCD_XRES,
+                .height         = LCD_YRES,
+                .xres           = LCD_XRES,
+                .yres           = LCD_YRES,
+                .left_margin    = LCD_LEFT_MARGIN,
+                .right_margin   = LCD_RIGHT_MARGIN,
+                .upper_margin   = LCD_UPPER_MARGIN,
+                .lower_margin   = LCD_LOWER_MARGIN,
+                .hsync_len      = LCD_HSYNC,
+                .vsync_len      = LCD_VSYNC,
+
+                .pixclock       = (1000000000000LL /
+                                   (LCD_REFRESH * LCD_HTOT * LCD_VTOT)),
+
+                .bpp            = 16,
+                .type           = (S3C2410_LCDCON1_TFT16BPP |
+                                   S3C2410_LCDCON1_TFT),
+
+                .lcdcon5        = (S3C2410_LCDCON5_FRM565 |
+                                   S3C2410_LCDCON5_INVVLINE |
+                                   S3C2410_LCDCON5_INVVFRAME |
+                                   S3C2410_LCDCON5_INVVDEN |
+                                   S3C2410_LCDCON5_PWREN),
+        },
+};
+
+/* todo - put into gpio header */
+
+#define S3C2410_GPCCON_MASK(x)  (3 << ((x) * 2))
+#define S3C2410_GPDCON_MASK(x)  (3 << ((x) * 2))
+
+struct s3c2410fb_mach_info jive_lcd_config = {
+        .displays        = jive_vgg2432a4_display,
+        .num_displays    = ARRAY_SIZE(jive_vgg2432a4_display),
+        .default_display = 0,
+
+        /* Enable VD[2..7], VD[10..15], VD[18..23] and VCLK, syncs, VDEN
+         * and disable the pull down resistors on pins we are using for LCD
+         * data. */
+
+        .gpcup          = (0xf << 1) | (0x3f << 10),
+
+        .gpccon         = (S3C2410_GPC1_VCLK   | S3C2410_GPC2_VLINE |
+                           S3C2410_GPC3_VFRAME | S3C2410_GPC4_VM |
+                           S3C2410_GPC10_VD2   | S3C2410_GPC11_VD3 |
+                           S3C2410_GPC12_VD4   | S3C2410_GPC13_VD5 |
+                           S3C2410_GPC14_VD6   | S3C2410_GPC15_VD7),
+
+        .gpccon_mask    = (S3C2410_GPCCON_MASK(1)  | S3C2410_GPCCON_MASK(2)  |
+                           S3C2410_GPCCON_MASK(3)  | S3C2410_GPCCON_MASK(4)  |
+                           S3C2410_GPCCON_MASK(10) | S3C2410_GPCCON_MASK(11) |
+                           S3C2410_GPCCON_MASK(12) | S3C2410_GPCCON_MASK(13) |
+                           S3C2410_GPCCON_MASK(14) | S3C2410_GPCCON_MASK(15)),
+
+        .gpdup          = (0x3f << 2) | (0x3f << 10),
+
+        .gpdcon         = (S3C2410_GPD2_VD10  | S3C2410_GPD3_VD11 |
+                           S3C2410_GPD4_VD12  | S3C2410_GPD5_VD13 |
+                           S3C2410_GPD6_VD14  | S3C2410_GPD7_VD15 |
+                           S3C2410_GPD10_VD18 | S3C2410_GPD11_VD19 |
+                           S3C2410_GPD12_VD20 | S3C2410_GPD13_VD21 |
+                           S3C2410_GPD14_VD22 | S3C2410_GPD15_VD23),
+
+        .gpdcon_mask    = (S3C2410_GPDCON_MASK(2)  | S3C2410_GPDCON_MASK(3) |
+                           S3C2410_GPDCON_MASK(4)  | S3C2410_GPDCON_MASK(5) |
+                           S3C2410_GPDCON_MASK(6)  | S3C2410_GPDCON_MASK(7) |
+                           S3C2410_GPDCON_MASK(10) | S3C2410_GPDCON_MASK(11)|
+                           S3C2410_GPDCON_MASK(12) | S3C2410_GPDCON_MASK(13)|
+                           S3C2410_GPDCON_MASK(14) | S3C2410_GPDCON_MASK(15)),
+};
+
+/* ILI9320 support. */
+
+static void jive_lcm_reset(unsigned int set)
+{
+        printk(KERN_DEBUG "%s(%d)\n", __func__, set);
+
+        s3c2410_gpio_setpin(S3C2410_GPG13, set);
+        s3c2410_gpio_cfgpin(S3C2410_GPG13, S3C2410_GPIO_OUTPUT);
+}
+
+#undef LCD_UPPER_MARGIN
+#define LCD_UPPER_MARGIN 2
+
+static struct ili9320_platdata jive_lcm_config = {
+        .hsize          = LCD_XRES,
+        .vsize          = LCD_YRES,
+
+        .reset          = jive_lcm_reset,
+        .suspend        = ILI9320_SUSPEND_DEEP,
+
+        .entry_mode     = ILI9320_ENTRYMODE_ID(3) | ILI9320_ENTRYMODE_BGR,
+        .display2       = (ILI9320_DISPLAY2_FP(LCD_UPPER_MARGIN) |
+                           ILI9320_DISPLAY2_BP(LCD_LOWER_MARGIN)),
+        .display3       = 0x0,
+        .display4       = 0x0,
+        .rgb_if1        = (ILI9320_RGBIF1_RIM_RGB18 |
+                           ILI9320_RGBIF1_RM | ILI9320_RGBIF1_CLK_RGBIF),
+        .rgb_if2        = ILI9320_RGBIF2_DPL,
+        .interface2     = 0x0,
+        .interface3     = 0x3,
+        .interface4     = (ILI9320_INTERFACE4_RTNE(16) |
+                           ILI9320_INTERFACE4_DIVE(1)),
+        .interface5     = 0x0,
+        .interface6     = 0x0,
+};
+
+/* LCD SPI support */
+
+static void jive_lcd_spi_chipselect(struct s3c2410_spigpio_info *spi, int cs)
+{
+        s3c2410_gpio_setpin(S3C2410_GPB7, cs ? 0 : 1);
+}
+
+static struct s3c2410_spigpio_info jive_lcd_spi = {
+        .bus_num        = 0,
+        .pin_clk        = S3C2410_GPG8,
+        .pin_mosi       = S3C2410_GPB8,
+        .chip_select    = jive_lcd_spi_chipselect,
+};
+
+static struct platform_device jive_device_lcdspi = {
+        .name           = "s3c24xx-spi-gpio",
+        .id             = 1,
+        .num_resources  = 0,
+        .dev.platform_data = &jive_lcd_spi,
+};
+
+/* WM8750 audio code SPI definition */
+
+static void jive_wm8750_chipselect(struct s3c2410_spigpio_info *spi, int cs)
+{
+        s3c2410_gpio_setpin(S3C2410_GPH10, cs ? 0 : 1);
+}
+
+static struct s3c2410_spigpio_info jive_wm8750_spi = {
+        .bus_num        = 2,
+        .pin_clk        = S3C2410_GPB4,
+        .pin_mosi       = S3C2410_GPB9,
+        .chip_select    = jive_wm8750_chipselect,
+};
+
+static struct platform_device jive_device_wm8750 = {
+        .name           = "s3c24xx-spi-gpio",
+        .id             = 2,
+        .num_resources  = 0,
+        .dev.platform_data = &jive_wm8750_spi,
+};
+
+/* JIVE SPI devices. */
+
+static struct spi_board_info __initdata jive_spi_devs[] = {
+        [0] = {
+                .modalias       = "VGG2432A4",
+                .bus_num        = 1,
+                .chip_select    = 0,
+                .mode           = SPI_MODE_3,   /* CPOL=1, CPHA=1 */
+                .max_speed_hz   = 100000,
+                .platform_data  = &jive_lcm_config,
+        }, {
+                .modalias       = "WM8750",
+                .bus_num        = 2,
+                .chip_select    = 0,
+                .mode           = SPI_MODE_0,   /* CPOL=0, CPHA=0 */
+                .max_speed_hz   = 100000,
+        },
+};
+
+/* I2C bus and device configuration. */
+
+static struct s3c2410_platform_i2c jive_i2c_cfg = {
+        .max_freq       = 80 * 1000,
+        .bus_freq       = 50 * 1000,
+        .flags          = S3C_IICFLG_FILTER,
+        .sda_delay      = 2,
+};
+
+static struct i2c_board_info jive_i2c_devs[] = {
+        [0] = {
+                I2C_BOARD_INFO("lis302dl", 0x1c),
+                .irq    = IRQ_EINT14,
+        },
+};
+
+/* The platform devices being used. */
+
+static struct platform_device *jive_devices[] __initdata = {
+        &s3c_device_usb,
+        &s3c_device_rtc,
+        &s3c_device_wdt,
+        &s3c_device_i2c,
+        &s3c_device_lcd,
+        &jive_device_lcdspi,
+        &jive_device_wm8750,
+        &s3c_device_nand,
+        &s3c_device_usbgadget,
+};
+
+static struct s3c2410_udc_mach_info jive_udc_cfg __initdata = {
+        .vbus_pin       = S3C2410_GPG1,         /* detect is on GPG1 */
+};
+
+/* Jive power management device */
+
+#ifdef CONFIG_PM
+static int jive_pm_suspend(struct sys_device *sd, pm_message_t state)
+{
+        /* Write the magic value u-boot uses to check for resume into
+         * the INFORM0 register, and ensure INFORM1 is set to the
+         * correct address to resume from. */
+
+        __raw_writel(0x2BED, S3C2412_INFORM0);
+        __raw_writel(virt_to_phys(s3c2410_cpu_resume), S3C2412_INFORM1);
+
+        return 0;
+}
+
+static int jive_pm_resume(struct sys_device *sd)
+{
+        __raw_writel(0x0, S3C2412_INFORM0);
+        return 0;
+}
+
+#else
+#define jive_pm_suspend NULL
+#define jive_pm_resume NULL
+#endif
+
+static struct sysdev_class jive_pm_sysclass = {
+        .name           = "jive-pm",
+        .suspend        = jive_pm_suspend,
+        .resume         = jive_pm_resume,
+};
+
+static struct sys_device jive_pm_sysdev = {
+        .cls            = &jive_pm_sysclass,
+};
+
+static void __init jive_map_io(void)
+{
+        s3c24xx_init_io(jive_iodesc, ARRAY_SIZE(jive_iodesc));
+        s3c24xx_init_clocks(12000000);
+        s3c24xx_init_uarts(jive_uartcfgs, ARRAY_SIZE(jive_uartcfgs));
+}
+
+static void jive_power_off(void)
+{
+        printk(KERN_INFO "powering system down...\n");
+
+        s3c2410_gpio_setpin(S3C2410_GPC5, 1);
+        s3c2410_gpio_cfgpin(S3C2410_GPC5, S3C2410_GPIO_OUTPUT);
+}
+
+static void __init jive_machine_init(void)
+{
+        /* register system devices for managing low level suspend */
+
+        sysdev_class_register(&jive_pm_sysclass);
+        sysdev_register(&jive_pm_sysdev);
+
+        /* write our sleep configurations for the IO. Pull down all unused
+         * IO, ensure that we have turned off all peripherals we do not
+         * need, and configure the ones we do need. */
+
+        /* Port B sleep */
+
+        __raw_writel(S3C2412_SLPCON_IN(0)   |
+                     S3C2412_SLPCON_PULL(1) |
+                     S3C2412_SLPCON_HIGH(2) |
+                     S3C2412_SLPCON_PULL(3) |
+                     S3C2412_SLPCON_PULL(4) |
+                     S3C2412_SLPCON_PULL(5) |
+                     S3C2412_SLPCON_PULL(6) |
+                     S3C2412_SLPCON_HIGH(7) |
+                     S3C2412_SLPCON_PULL(8) |
+                     S3C2412_SLPCON_PULL(9) |
+                     S3C2412_SLPCON_PULL(10), S3C2412_GPBSLPCON);
+
+        /* Port C sleep */
+
+        __raw_writel(S3C2412_SLPCON_PULL(0) |
+                     S3C2412_SLPCON_PULL(1) |
+                     S3C2412_SLPCON_PULL(2) |
+                     S3C2412_SLPCON_PULL(3) |
+                     S3C2412_SLPCON_PULL(4) |
+                     S3C2412_SLPCON_PULL(5) |
+                     S3C2412_SLPCON_LOW(6)  |
+                     S3C2412_SLPCON_PULL(6) |
+                     S3C2412_SLPCON_PULL(7) |
+                     S3C2412_SLPCON_PULL(8) |
+                     S3C2412_SLPCON_PULL(9) |
+                     S3C2412_SLPCON_PULL(10) |
+                     S3C2412_SLPCON_PULL(11) |
+                     S3C2412_SLPCON_PULL(12) |
+                     S3C2412_SLPCON_PULL(13) |
+                     S3C2412_SLPCON_PULL(14) |
+                     S3C2412_SLPCON_PULL(15), S3C2412_GPCSLPCON);
+
+        /* Port D sleep */
+
+        __raw_writel(S3C2412_SLPCON_ALL_PULL, S3C2412_GPDSLPCON);
+
+        /* Port F sleep */
+
+        __raw_writel(S3C2412_SLPCON_LOW(0)  |
+                     S3C2412_SLPCON_LOW(1)  |
+                     S3C2412_SLPCON_LOW(2)  |
+                     S3C2412_SLPCON_EINT(3) |
+                     S3C2412_SLPCON_EINT(4) |
+                     S3C2412_SLPCON_EINT(5) |
+                     S3C2412_SLPCON_EINT(6) |
+                     S3C2412_SLPCON_EINT(7), S3C2412_GPFSLPCON);
+
+        /* Port G sleep */
+
+        __raw_writel(S3C2412_SLPCON_IN(0)    |
+                     S3C2412_SLPCON_IN(1)    |
+                     S3C2412_SLPCON_IN(2)    |
+                     S3C2412_SLPCON_IN(3)    |
+                     S3C2412_SLPCON_IN(4)    |
+                     S3C2412_SLPCON_IN(5)    |
+                     S3C2412_SLPCON_IN(6)    |
+                     S3C2412_SLPCON_IN(7)    |
+                     S3C2412_SLPCON_PULL(8)  |
+                     S3C2412_SLPCON_PULL(9)  |
+                     S3C2412_SLPCON_IN(10)   |
+                     S3C2412_SLPCON_PULL(11) |
+                     S3C2412_SLPCON_PULL(12) |
+                     S3C2412_SLPCON_PULL(13) |
+                     S3C2412_SLPCON_IN(14)   |
+                     S3C2412_SLPCON_PULL(15), S3C2412_GPGSLPCON);
+
+        /* Port H sleep */
+
+        __raw_writel(S3C2412_SLPCON_PULL(0) |
+                     S3C2412_SLPCON_PULL(1) |
+                     S3C2412_SLPCON_PULL(2) |
+                     S3C2412_SLPCON_PULL(3) |
+                     S3C2412_SLPCON_PULL(4) |
+                     S3C2412_SLPCON_PULL(5) |
+                     S3C2412_SLPCON_PULL(6) |
+                     S3C2412_SLPCON_IN(7)   |
+                     S3C2412_SLPCON_IN(8)   |
+                     S3C2412_SLPCON_PULL(9) |
+                     S3C2412_SLPCON_IN(10), S3C2412_GPHSLPCON);
+
+        /* initialise the power management now we've setup everything. */
+
+        s3c2410_pm_init();
+
+        s3c_device_nand.dev.platform_data = &jive_nand_info;
+
+        /* initialise the spi */
+
+        s3c2410_gpio_setpin(S3C2410_GPG13, 0);
+        s3c2410_gpio_cfgpin(S3C2410_GPG13, S3C2410_GPIO_OUTPUT);
+
+        s3c2410_gpio_setpin(S3C2410_GPB7, 1);
+        s3c2410_gpio_cfgpin(S3C2410_GPB7, S3C2410_GPIO_OUTPUT);
+
+        s3c2410_gpio_setpin(S3C2410_GPB6, 0);
+        s3c2410_gpio_cfgpin(S3C2410_GPB6, S3C2410_GPIO_OUTPUT);
+
+        s3c2410_gpio_setpin(S3C2410_GPG8, 1);
+        s3c2410_gpio_cfgpin(S3C2410_GPG8, S3C2410_GPIO_OUTPUT);
+
+        /* initialise the WM8750 spi */
+
+        s3c2410_gpio_setpin(S3C2410_GPH10, 1);
+        s3c2410_gpio_cfgpin(S3C2410_GPH10, S3C2410_GPIO_OUTPUT);
+
+        /* Turn off suspend on both USB ports, and switch the
+         * selectable USB port to USB device mode. */
+
+        s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST |
+                              S3C2410_MISCCR_USBSUSPND0 |
+                              S3C2410_MISCCR_USBSUSPND1, 0x0);
+
+        s3c24xx_udc_set_platdata(&jive_udc_cfg);
+        s3c24xx_fb_set_platdata(&jive_lcd_config);
+
+        spi_register_board_info(jive_spi_devs, ARRAY_SIZE(jive_spi_devs));
+
+        s3c_device_i2c.dev.platform_data = &jive_i2c_cfg;
+        i2c_register_board_info(0, jive_i2c_devs, ARRAY_SIZE(jive_i2c_devs));
+
+        pm_power_off = jive_power_off;
+
+        platform_add_devices(jive_devices, ARRAY_SIZE(jive_devices));
+}
+
+MACHINE_START(JIVE, "JIVE")
+        /* Maintainer: Ben Dooks <ben@fluff.org> */
+        .phys_io        = S3C2410_PA_UART,
+        .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
+        .boot_params    = S3C2410_SDRAM_PA + 0x100,
+
+        .init_irq       = s3c24xx_init_irq,
+        .map_io         = jive_map_io,
+        .init_machine   = jive_machine_init,
+        .timer          = &s3c24xx_timer,
+MACHINE_END
diff --git a/arch/arm/mach-s3c2440/Kconfig b/arch/arm/mach-s3c2440/Kconfig
index f1915bd61d15..25de042ab996 100644
--- a/arch/arm/mach-s3c2440/Kconfig
+++ b/arch/arm/mach-s3c2440/Kconfig
@@ -29,6 +29,7 @@ config MACH_ANUBIS
         bool "Simtec Electronics ANUBIS"
         select CPU_S3C2440
         select PM_SIMTEC if PM
+        select HAVE_PATA_PLATFORM
         help
           Say Y here if you are using the Simtec Electronics ANUBIS
           development system
@@ -67,6 +68,11 @@ config SMDK2440_CPU2440
         default y if ARCH_S3C2440
         select CPU_S3C2440
 
+config MACH_AT2440EVB
+        bool "Avantech AT2440EVB development board"
+        select CPU_S3C2440
+        help
+          Say Y here if you are using the AT2440EVB development board
 
 endmenu
 
diff --git a/arch/arm/mach-s3c2440/Makefile b/arch/arm/mach-s3c2440/Makefile
index c81ed6248dcb..0b4440e79b90 100644
--- a/arch/arm/mach-s3c2440/Makefile
+++ b/arch/arm/mach-s3c2440/Makefile
@@ -21,3 +21,4 @@ obj-$(CONFIG_MACH_OSIRIS)	+= mach-osiris.o
 obj-$(CONFIG_MACH_RX3715)       += mach-rx3715.o
 obj-$(CONFIG_ARCH_S3C2440)      += mach-smdk2440.o
 obj-$(CONFIG_MACH_NEXCODER_2440) += mach-nexcoder.o
+obj-$(CONFIG_MACH_AT2440EVB) += mach-at2440evb.o
diff --git a/arch/arm/mach-s3c2440/mach-anubis.c b/arch/arm/mach-s3c2440/mach-anubis.c
index 47258915a2f9..09af8b23500b 100644
--- a/arch/arm/mach-s3c2440/mach-anubis.c
+++ b/arch/arm/mach-s3c2440/mach-anubis.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/mach-s3c2440/mach-anubis.c
  *
- * Copyright (c) 2003-2005 Simtec Electronics
+ * Copyright (c) 2003-2005,2008 Simtec Electronics
  *      http://armlinux.simtec.co.uk/
  *      Ben Dooks <ben@simtec.co.uk>
  *
@@ -17,6 +17,8 @@
 #include <linux/init.h>
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
+#include <linux/ata_platform.h>
+#include <linux/i2c.h>
 
 #include <linux/sm501.h>
 #include <linux/sm501-regs.h>
@@ -241,14 +243,18 @@ static struct s3c2410_platform_nand anubis_nand_info = {
 
 /* IDE channels */
 
+struct pata_platform_info anubis_ide_platdata = {
+        .ioport_shift   = 5,
+};
+
 static struct resource anubis_ide0_resource[] = {
         {
                 .start  = S3C2410_CS3,
                 .end    = S3C2410_CS3 + (8*32) - 1,
                 .flags  = IORESOURCE_MEM,
         }, {
-                .start  = S3C2410_CS3 + (1<<26),
-                .end    = S3C2410_CS3 + (1<<26) + (8*32) - 1,
+                .start  = S3C2410_CS3 + (1<<26) + (6*32),
+                .end    = S3C2410_CS3 + (1<<26) + (7*32) - 1,
                 .flags  = IORESOURCE_MEM,
         }, {
                 .start  = IRQ_IDE0,
@@ -258,10 +264,14 @@ static struct resource anubis_ide0_resource[] = {
 };
 
 static struct platform_device anubis_device_ide0 = {
-        .name           = "simtec-ide",
+        .name           = "pata_platform",
         .id             = 0,
         .num_resources  = ARRAY_SIZE(anubis_ide0_resource),
         .resource       = anubis_ide0_resource,
+        .dev    = {
+                .platform_data = &anubis_ide_platdata,
+                .coherent_dma_mask = ~0,
+        },
 };
 
 static struct resource anubis_ide1_resource[] = {
@@ -270,8 +280,8 @@ static struct resource anubis_ide1_resource[] = {
                 .end    = S3C2410_CS4 + (8*32) - 1,
                 .flags  = IORESOURCE_MEM,
         }, {
-                .start  = S3C2410_CS4 + (1<<26),
-                .end    = S3C2410_CS4 + (1<<26) + (8*32) - 1,
+                .start  = S3C2410_CS4 + (1<<26) + (6*32),
+                .end    = S3C2410_CS4 + (1<<26) + (7*32) - 1,
                 .flags  = IORESOURCE_MEM,
         }, {
                 .start  = IRQ_IDE0,
@@ -280,12 +290,15 @@ static struct resource anubis_ide1_resource[] = {
         },
 };
 
-
 static struct platform_device anubis_device_ide1 = {
-        .name           = "simtec-ide",
+        .name           = "pata_platform",
         .id             = 1,
         .num_resources  = ARRAY_SIZE(anubis_ide1_resource),
         .resource       = anubis_ide1_resource,
+        .dev    = {
+                .platform_data = &anubis_ide_platdata,
+                .coherent_dma_mask = ~0,
+        },
 };
 
 /* Asix AX88796 10/100 ethernet controller */
@@ -409,6 +422,15 @@ static struct clk *anubis_clocks[] = {
         &s3c24xx_uclk,
 };
 
+/* I2C devices. */
+
+static struct i2c_board_info anubis_i2c_devs[] __initdata = {
+        {
+                I2C_BOARD_INFO("tps65011", 0x48),
+                .irq    = IRQ_EINT20,
+        }
+};
+
 static void __init anubis_map_io(void)
 {
         /* initialise the clocks */
@@ -448,6 +470,9 @@ static void __init anubis_map_io(void)
 static void __init anubis_init(void)
 {
         platform_add_devices(anubis_devices, ARRAY_SIZE(anubis_devices));
+
+        i2c_register_board_info(0, anubis_i2c_devs,
+                                ARRAY_SIZE(anubis_i2c_devs));
 }
 
 
diff --git a/arch/arm/mach-s3c2440/mach-at2440evb.c b/arch/arm/mach-s3c2440/mach-at2440evb.c
new file mode 100644
index 000000000000..f5e3c7f27639
--- /dev/null
+++ b/arch/arm/mach-s3c2440/mach-at2440evb.c
@@ -0,0 +1,198 @@
+/* linux/arch/arm/mach-s3c2440/mach-at2440evb.c
+ *
+ * Copyright (c) 2008 Ramax Lo <ramaxlo@gmail.com>
+ *      Based on mach-anubis.c by Ben Dooks <ben@simtec.co.uk>
+ *      and modifications by SBZ <sbz@spgui.org> and
+ *      Weibing <http://weibing.blogbus.com>
+ *
+ * For product information, visit http://www.arm9e.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/serial_core.h>
+#include <linux/dm9000.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/hardware.h>
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+
+#include <asm/plat-s3c/regs-serial.h>
+#include <asm/arch/regs-gpio.h>
+#include <asm/arch/regs-mem.h>
+#include <asm/arch/regs-lcd.h>
+#include <asm/plat-s3c/nand.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_ecc.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/plat-s3c24xx/clock.h>
+#include <asm/plat-s3c24xx/devs.h>
+#include <asm/plat-s3c24xx/cpu.h>
+
+static struct map_desc at2440evb_iodesc[] __initdata = {
+        /* Nothing here */
+};
+
+#define UCON S3C2410_UCON_DEFAULT
+#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE)
+#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
+
+static struct s3c24xx_uart_clksrc at2440evb_serial_clocks[] = {
+        [0] = {
+                .name           = "uclk",
+                .divisor        = 1,
+                .min_baud       = 0,
+                .max_baud       = 0,
+        },
+        [1] = {
+                .name           = "pclk",
+                .divisor        = 1,
+                .min_baud       = 0,
+                .max_baud       = 0,
+        }
+};
+
+
+static struct s3c2410_uartcfg at2440evb_uartcfgs[] __initdata = {
+        [0] = {
+                .hwport      = 0,
+                .flags       = 0,
+                .ucon        = UCON,
+                .ulcon       = ULCON,
+                .ufcon       = UFCON,
+                .clocks      = at2440evb_serial_clocks,
+                .clocks_size = ARRAY_SIZE(at2440evb_serial_clocks),
+        },
+        [1] = {
+                .hwport      = 1,
+                .flags       = 0,
+                .ucon        = UCON,
+                .ulcon       = ULCON,
+                .ufcon       = UFCON,
+                .clocks      = at2440evb_serial_clocks,
+                .clocks_size = ARRAY_SIZE(at2440evb_serial_clocks),
+        },
+};
+
+/* NAND Flash on AT2440EVB board */
+
+static struct mtd_partition at2440evb_default_nand_part[] = {
+        [0] = {
+                .name   = "Boot Agent",
+                .size   = SZ_256K,
+                .offset = 0,
+        },
+        [1] = {
+                .name   = "Kernel",
+                .size   = SZ_2M,
+                .offset = SZ_256K,
+        },
+        [2] = {
+                .name   = "Root",
+                .offset = SZ_256K + SZ_2M,
+                .size   = MTDPART_SIZ_FULL,
+        },
+};
+
+static struct s3c2410_nand_set at2440evb_nand_sets[] = {
+        [0] = {
+                .name           = "nand",
+                .nr_chips       = 1,
+                .nr_partitions  = ARRAY_SIZE(at2440evb_default_nand_part),
+                .partitions     = at2440evb_default_nand_part,
+        },
+};
+
+static struct s3c2410_platform_nand at2440evb_nand_info = {
+        .tacls          = 25,
+        .twrph0         = 55,
+        .twrph1         = 40,
+        .nr_sets        = ARRAY_SIZE(at2440evb_nand_sets),
+        .sets           = at2440evb_nand_sets,
+};
+
+/* DM9000AEP 10/100 ethernet controller */
+
+static struct resource at2440evb_dm9k_resource[] = {
+        [0] = {
+                .start = S3C2410_CS3,
+                .end   = S3C2410_CS3 + 3,
+                .flags = IORESOURCE_MEM
+        },
+        [1] = {
+                .start = S3C2410_CS3 + 4,
+                .end   = S3C2410_CS3 + 7,
+                .flags = IORESOURCE_MEM
+        },
+        [2] = {
+                .start = IRQ_EINT7,
+                .end   = IRQ_EINT7,
+                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
+        }
+};
+
+static struct dm9000_plat_data at2440evb_dm9k_pdata = {
+        .flags          = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
+};
+
+static struct platform_device at2440evb_device_eth = {
+        .name           = "dm9000",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(at2440evb_dm9k_resource),
+        .resource       = at2440evb_dm9k_resource,
+        .dev            = {
+                .platform_data  = &at2440evb_dm9k_pdata,
+        },
+};
+
+static struct platform_device *at2440evb_devices[] __initdata = {
+        &s3c_device_usb,
+        &s3c_device_wdt,
+        &s3c_device_adc,
+        &s3c_device_i2c,
+        &s3c_device_rtc,
+        &s3c_device_nand,
+        &at2440evb_device_eth,
+};
+
+static void __init at2440evb_map_io(void)
+{
+        s3c_device_nand.dev.platform_data = &at2440evb_nand_info;
+
+        s3c24xx_init_io(at2440evb_iodesc, ARRAY_SIZE(at2440evb_iodesc));
+        s3c24xx_init_clocks(16934400);
+        s3c24xx_init_uarts(at2440evb_uartcfgs, ARRAY_SIZE(at2440evb_uartcfgs));
+}
+
+static void __init at2440evb_init(void)
+{
+        platform_add_devices(at2440evb_devices, ARRAY_SIZE(at2440evb_devices));
+}
+
+
+MACHINE_START(AT2440EVB, "AT2440EVB")
+        .phys_io        = S3C2410_PA_UART,
+        .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
+        .boot_params    = S3C2410_SDRAM_PA + 0x100,
+        .map_io         = at2440evb_map_io,
+        .init_machine   = at2440evb_init,
+        .init_irq       = s3c24xx_init_irq,
+        .timer          = &s3c24xx_timer,
+MACHINE_END
diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c
index 8a8acdbd072d..af996b0e91e8 100644
--- a/arch/arm/mach-s3c2440/mach-osiris.c
+++ b/arch/arm/mach-s3c2440/mach-osiris.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/mach-s3c2440/mach-osiris.c
  *
- * Copyright (c) 2005 Simtec Electronics
+ * Copyright (c) 2005,2008 Simtec Electronics
  *      http://armlinux.simtec.co.uk/
  *      Ben Dooks <ben@simtec.co.uk>
  *
@@ -19,6 +19,7 @@
 #include <linux/sysdev.h>
 #include <linux/serial_core.h>
 #include <linux/clk.h>
+#include <linux/i2c.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -322,6 +323,15 @@ static struct sys_device osiris_pm_sysdev = {
         .cls            = &osiris_pm_sysclass,
 };
 
+/* I2C devices fitted. */
+
+static struct i2c_board_info osiris_i2c_devs[] __initdata = {
+        {
+                I2C_BOARD_INFO("tps65011", 0x48),
+                .irq    = IRQ_EINT20,
+        },
+};
+
 /* Standard Osiris devices */
 
 static struct platform_device *osiris_devices[] __initdata = {
@@ -388,6 +398,9 @@ static void __init osiris_init(void)
         sysdev_class_register(&osiris_pm_sysclass);
         sysdev_register(&osiris_pm_sysdev);
 
+        i2c_register_board_info(0, osiris_i2c_devs,
+                                ARRAY_SIZE(osiris_i2c_devs));
+
         platform_add_devices(osiris_devices, ARRAY_SIZE(osiris_devices));
 };
 
diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c
index b42f956738d0..17f064fabdaf 100644
--- a/arch/arm/mach-s3c2443/clock.c
+++ b/arch/arm/mach-s3c2443/clock.c
@@ -81,7 +81,7 @@ static int s3c2443_clkcon_enable_p(struct clk *clk, int enable)
         else
                 clkcon &= ~clocks;
 
-        __raw_writel(clkcon, S3C2443_HCLKCON);
+        __raw_writel(clkcon, S3C2443_PCLKCON);
 
         return 0;
 }
@@ -221,7 +221,6 @@ static struct clk clk_mdivclk = {
         .get_rate       = s3c2443_getrate_mdivclk,
 };
 
-
 static int s3c2443_setparent_msysclk(struct clk *clk, struct clk *parent)
 {
         unsigned long clksrc = __raw_readl(S3C2443_CLKSRC);
@@ -249,6 +248,46 @@ static struct clk clk_msysclk = {
         .set_parent     = s3c2443_setparent_msysclk,
 };
 
+/* armdiv
+ *
+ * this clock is sourced from msysclk and can have a number of
+ * divider values applied to it to then be fed into armclk.
+*/
+
+static struct clk clk_armdiv = {
+        .name           = "armdiv",
+        .id             = -1,
+        .parent         = &clk_msysclk,
+};
+
+/* armclk
+ *
+ * this is the clock fed into the ARM core itself, either from
+ * armdiv or from hclk.
+ */
+
+static int s3c2443_setparent_armclk(struct clk *clk, struct clk *parent)
+{
+        unsigned long clkdiv0;
+
+        clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
+
+        if (parent == &clk_armdiv)
+                clkdiv0 &= ~S3C2443_CLKDIV0_DVS;
+        else if (parent == &clk_h)
+                clkdiv0 |= S3C2443_CLKDIV0_DVS;
+        else
+                return -EINVAL;
+
+        __raw_writel(clkdiv0, S3C2443_CLKDIV0);
+        return 0;
+}
+
+static struct clk clk_arm = {
+        .name           = "armclk",
+        .id             = -1,
+        .set_parent     = s3c2443_setparent_armclk,
+};
 
 /* esysclk
  *
@@ -639,6 +678,29 @@ static struct clk clk_display = {
         .round_rate     = s3c2443_roundrate_clksrc256,
 };
 
+/* prediv
+ *
+ * this divides the msysclk down to pass to h/p/etc.
+ */
+
+static unsigned long s3c2443_prediv_getrate(struct clk *clk)
+{
+        unsigned long rate = clk_get_rate(clk->parent);
+        unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
+
+        clkdiv0 &= S3C2443_CLKDIV0_PREDIV_MASK;
+        clkdiv0 >>= S3C2443_CLKDIV0_PREDIV_SHIFT;
+
+        return rate / (clkdiv0 + 1);
+}
+
+static struct clk clk_prediv = {
+        .name           = "prediv",
+        .id             = -1,
+        .parent         = &clk_msysclk,
+        .get_rate       = s3c2443_prediv_getrate,
+};
+
 /* standard clock definitions */
 
 static struct clk init_clocks_disable[] = {
@@ -887,6 +949,15 @@ static void __init s3c2443_clk_initparents(void)
         }
 
         clk_init_set_parent(&clk_msysclk, parent);
+
+        /* arm */
+
+        if (__raw_readl(S3C2443_CLKDIV0) & S3C2443_CLKDIV0_DVS)
+                parent = &clk_h;
+        else
+                parent = &clk_armdiv;
+
+        clk_init_set_parent(&clk_arm, parent);
 }
 
 /* armdiv divisor table */
@@ -909,10 +980,9 @@ static inline unsigned int s3c2443_fclk_div(unsigned long clkcon0)
         return armdiv[clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT];
 }
 
-static inline unsigned long s3c2443_get_prediv(unsigned long clkcon0)
+static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0)
 {
-        clkcon0 &= S3C2443_CLKDIV0_PREDIV_MASK;
-        clkcon0 >>= S3C2443_CLKDIV0_PREDIV_SHIFT;
+        clkcon0 &= S3C2443_CLKDIV0_HCLKDIV_MASK;
 
         return clkcon0 + 1;
 }
@@ -936,6 +1006,9 @@ static struct clk *clks[] __initdata = {
         &clk_hsspi,
         &clk_hsmmc_div,
         &clk_hsmmc,
+        &clk_armdiv,
+        &clk_arm,
+        &clk_prediv,
 };
 
 void __init s3c2443_init_clocks(int xtal)
@@ -951,10 +1024,16 @@ void __init s3c2443_init_clocks(int xtal)
         int ret;
         int ptr;
 
+        /* s3c2443 parents h and p clocks from prediv */
+        clk_h.parent = &clk_prediv;
+        clk_p.parent = &clk_prediv;
+
         pll = s3c2443_get_mpll(mpllcon, xtal);
+        clk_msysclk.rate = pll;
 
         fclk = pll / s3c2443_fclk_div(clkdiv0);
-        hclk = fclk / s3c2443_get_prediv(clkdiv0);
+        hclk = s3c2443_prediv_getrate(&clk_prediv);
+        hclk = hclk / s3c2443_get_hdiv(clkdiv0);
         hclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_HCLK) ? 2 : 1);
         pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1);
 
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 33ed048502a3..3a6c8ec34cd9 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -180,8 +180,21 @@ config CPU_ARM925T
 # ARM926T
 config CPU_ARM926T
         bool "Support ARM926T processor"
-        depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91CAP9 || ARCH_NS9XXX || ARCH_DAVINCI
-        default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91CAP9 || ARCH_NS9XXX || ARCH_DAVINCI
+        depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || \
+                MACH_VERSATILE_AB || ARCH_OMAP730 || \
+                ARCH_OMAP16XX || MACH_REALVIEW_EB || \
+                ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || \
+                ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || \
+                ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || \
+                ARCH_AT91SAM9G20 || ARCH_AT91CAP9 || \
+                ARCH_NS9XXX || ARCH_DAVINCI
+        default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || \
+                ARCH_OMAP730 || ARCH_OMAP16XX || \
+                ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || \
+                ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || \
+                ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || \
+                ARCH_AT91SAM9G20 || ARCH_AT91CAP9 || \
+                ARCH_NS9XXX || ARCH_DAVINCI || ARCH_MX2
         select CPU_32v5
         select CPU_ABRT_EV5TJ
         select CPU_PABRT_NOIFAR
@@ -365,7 +378,7 @@ config CPU_XSC3
 # Feroceon
 config CPU_FEROCEON
         bool
-        depends on ARCH_ORION5X
+        depends on ARCH_ORION5X || ARCH_LOKI || ARCH_KIRKWOOD || ARCH_MV78XX0
         default y
         select CPU_32v5
         select CPU_ABRT_EV5T
@@ -373,7 +386,7 @@ config CPU_FEROCEON
         select CPU_CACHE_VIVT
         select CPU_CP15_MMU
         select CPU_COPY_FEROCEON if MMU
-        select CPU_TLB_V4WBI if MMU
+        select CPU_TLB_FEROCEON if MMU
 
 config CPU_FEROCEON_OLD_ID
         bool "Accept early Feroceon cores with an ARM926 ID"
@@ -551,6 +564,11 @@ config CPU_TLB_V4WBI
           ARM Architecture Version 4 TLB with writeback cache and invalidate
           instruction cache entry.
 
+config CPU_TLB_FEROCEON
+        bool
+        help
+          Feroceon TLB (v4wbi with non-outer-cachable page table walks).
+
 config CPU_TLB_V6
         bool
 
@@ -709,6 +727,14 @@ config OUTER_CACHE
         bool
         default n
 
+config CACHE_FEROCEON_L2
+        bool "Enable the Feroceon L2 cache controller"
+        depends on ARCH_KIRKWOOD || ARCH_MV78XX0
+        default y
+        select OUTER_CACHE
+        help
+          This option enables the Feroceon L2 cache controller.
+
 config CACHE_L2X0
         bool "Enable the L2x0 outer cache controller"
         depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index 32b2d2d213a6..f64b92557b11 100644
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_CPU_TLB_V3)	+= tlb-v3.o
 obj-$(CONFIG_CPU_TLB_V4WT)      += tlb-v4.o
 obj-$(CONFIG_CPU_TLB_V4WB)      += tlb-v4wb.o
 obj-$(CONFIG_CPU_TLB_V4WBI)     += tlb-v4wbi.o
+obj-$(CONFIG_CPU_TLB_FEROCEON)  += tlb-v4wbi.o  # reuse v4wbi TLB functions
 obj-$(CONFIG_CPU_TLB_V6)        += tlb-v6.o
 obj-$(CONFIG_CPU_TLB_V7)        += tlb-v7.o
 
@@ -73,4 +74,5 @@ obj-$(CONFIG_CPU_FEROCEON)	+= proc-feroceon.o
 obj-$(CONFIG_CPU_V6)            += proc-v6.o
 obj-$(CONFIG_CPU_V7)            += proc-v7.o
 
+obj-$(CONFIG_CACHE_FEROCEON_L2) += cache-feroceon-l2.o
 obj-$(CONFIG_CACHE_L2X0)        += cache-l2x0.o
diff --git a/arch/arm/mm/cache-feroceon-l2.c b/arch/arm/mm/cache-feroceon-l2.c
new file mode 100644
index 000000000000..20eec4ba173f
--- /dev/null
+++ b/arch/arm/mm/cache-feroceon-l2.c
@@ -0,0 +1,318 @@
+/*
+ * arch/arm/mm/cache-feroceon-l2.c - Feroceon L2 cache controller support
+ *
+ * Copyright (C) 2008 Marvell Semiconductor
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * References:
+ * - Unified Layer 2 Cache for Feroceon CPU Cores,
+ *   Document ID MV-S104858-00, Rev. A, October 23 2007.
+ */
+
+#include <linux/init.h>
+#include <asm/cacheflush.h>
+#include <asm/plat-orion/cache-feroceon-l2.h>
+
+
+/*
+ * Low-level cache maintenance operations.
+ *
+ * As well as the regular 'clean/invalidate/flush L2 cache line by
+ * MVA' instructions, the Feroceon L2 cache controller also features
+ * 'clean/invalidate L2 range by MVA' operations.
+ *
+ * Cache range operations are initiated by writing the start and
+ * end addresses to successive cp15 registers, and process every
+ * cache line whose first byte address lies in the inclusive range
+ * [start:end].
+ *
+ * The cache range operations stall the CPU pipeline until completion.
+ *
+ * The range operations require two successive cp15 writes, in
+ * between which we don't want to be preempted.
+ */
+static inline void l2_clean_pa(unsigned long addr)
+{
+        __asm__("mcr p15, 1, %0, c15, c9, 3" : : "r" (addr));
+}
+
+static inline void l2_clean_mva_range(unsigned long start, unsigned long end)
+{
+        unsigned long flags;
+
+        /*
+         * Make sure 'start' and 'end' reference the same page, as
+         * L2 is PIPT and range operations only do a TLB lookup on
+         * the start address.
+         */
+        BUG_ON((start ^ end) & ~(PAGE_SIZE - 1));
+
+        raw_local_irq_save(flags);
+        __asm__("mcr p15, 1, %0, c15, c9, 4" : : "r" (start));
+        __asm__("mcr p15, 1, %0, c15, c9, 5" : : "r" (end));
+        raw_local_irq_restore(flags);
+}
+
+static inline void l2_clean_pa_range(unsigned long start, unsigned long end)
+{
+        l2_clean_mva_range(__phys_to_virt(start), __phys_to_virt(end));
+}
+
+static inline void l2_clean_inv_pa(unsigned long addr)
+{
+        __asm__("mcr p15, 1, %0, c15, c10, 3" : : "r" (addr));
+}
+
+static inline void l2_inv_pa(unsigned long addr)
+{
+        __asm__("mcr p15, 1, %0, c15, c11, 3" : : "r" (addr));
+}
+
+static inline void l2_inv_mva_range(unsigned long start, unsigned long end)
+{
+        unsigned long flags;
+
+        /*
+         * Make sure 'start' and 'end' reference the same page, as
+         * L2 is PIPT and range operations only do a TLB lookup on
+         * the start address.
+         */
+        BUG_ON((start ^ end) & ~(PAGE_SIZE - 1));
+
+        raw_local_irq_save(flags);
+        __asm__("mcr p15, 1, %0, c15, c11, 4" : : "r" (start));
+        __asm__("mcr p15, 1, %0, c15, c11, 5" : : "r" (end));
+        raw_local_irq_restore(flags);
+}
+
+static inline void l2_inv_pa_range(unsigned long start, unsigned long end)
+{
+        l2_inv_mva_range(__phys_to_virt(start), __phys_to_virt(end));
+}
+
+
+/*
+ * Linux primitives.
+ *
+ * Note that the end addresses passed to Linux primitives are
+ * noninclusive, while the hardware cache range operations use
+ * inclusive start and end addresses.
+ */
+#define CACHE_LINE_SIZE         32
+#define MAX_RANGE_SIZE          1024
+
+static int l2_wt_override;
+
+static unsigned long calc_range_end(unsigned long start, unsigned long end)
+{
+        unsigned long range_end;
+
+        BUG_ON(start & (CACHE_LINE_SIZE - 1));
+        BUG_ON(end & (CACHE_LINE_SIZE - 1));
+
+        /*
+         * Try to process all cache lines between 'start' and 'end'.
+         */
+        range_end = end;
+
+        /*
+         * Limit the number of cache lines processed at once,
+         * since cache range operations stall the CPU pipeline
+         * until completion.
+         */
+        if (range_end > start + MAX_RANGE_SIZE)
+                range_end = start + MAX_RANGE_SIZE;
+
+        /*
+         * Cache range operations can't straddle a page boundary.
+         */
+        if (range_end > (start | (PAGE_SIZE - 1)) + 1)
+                range_end = (start | (PAGE_SIZE - 1)) + 1;
+
+        return range_end;
+}
+
+static void feroceon_l2_inv_range(unsigned long start, unsigned long end)
+{
+        /*
+         * Clean and invalidate partial first cache line.
+         */
+        if (start & (CACHE_LINE_SIZE - 1)) {
+                l2_clean_inv_pa(start & ~(CACHE_LINE_SIZE - 1));
+                start = (start | (CACHE_LINE_SIZE - 1)) + 1;
+        }
+
+        /*
+         * Clean and invalidate partial last cache line.
+         */
+        if (end & (CACHE_LINE_SIZE - 1)) {
+                l2_clean_inv_pa(end & ~(CACHE_LINE_SIZE - 1));
+                end &= ~(CACHE_LINE_SIZE - 1);
+        }
+
+        /*
+         * Invalidate all full cache lines between 'start' and 'end'.
+         */
+        while (start != end) {
+                unsigned long range_end = calc_range_end(start, end);
+                l2_inv_pa_range(start, range_end - CACHE_LINE_SIZE);
+                start = range_end;
+        }
+
+        dsb();
+}
+
+static void feroceon_l2_clean_range(unsigned long start, unsigned long end)
+{
+        /*
+         * If L2 is forced to WT, the L2 will always be clean and we
+         * don't need to do anything here.
+         */
+        if (!l2_wt_override) {
+                start &= ~(CACHE_LINE_SIZE - 1);
+                end = (end + CACHE_LINE_SIZE - 1) & ~(CACHE_LINE_SIZE - 1);
+                while (start != end) {
+                        unsigned long range_end = calc_range_end(start, end);
+                        l2_clean_pa_range(start, range_end - CACHE_LINE_SIZE);
+                        start = range_end;
+                }
+        }
+
+        dsb();
+}
+
+static void feroceon_l2_flush_range(unsigned long start, unsigned long end)
+{
+        start &= ~(CACHE_LINE_SIZE - 1);
+        end = (end + CACHE_LINE_SIZE - 1) & ~(CACHE_LINE_SIZE - 1);
+        while (start != end) {
+                unsigned long range_end = calc_range_end(start, end);
+                if (!l2_wt_override)
+                        l2_clean_pa_range(start, range_end - CACHE_LINE_SIZE);
+                l2_inv_pa_range(start, range_end - CACHE_LINE_SIZE);
+                start = range_end;
+        }
+
+        dsb();
+}
+
+
+/*
+ * Routines to disable and re-enable the D-cache and I-cache at run
+ * time.  These are necessary because the L2 cache can only be enabled
+ * or disabled while the L1 Dcache and Icache are both disabled.
+ */
+static void __init invalidate_and_disable_dcache(void)
+{
+        u32 cr;
+
+        cr = get_cr();
+        if (cr & CR_C) {
+                unsigned long flags;
+
+                raw_local_irq_save(flags);
+                flush_cache_all();
+                set_cr(cr & ~CR_C);
+                raw_local_irq_restore(flags);
+        }
+}
+
+static void __init enable_dcache(void)
+{
+        u32 cr;
+
+        cr = get_cr();
+        if (!(cr & CR_C))
+                set_cr(cr | CR_C);
+}
+
+static void __init __invalidate_icache(void)
+{
+        int dummy;
+
+        __asm__ __volatile__("mcr p15, 0, %0, c7, c5, 0\n" : "=r" (dummy));
+}
+
+static void __init invalidate_and_disable_icache(void)
+{
+        u32 cr;
+
+        cr = get_cr();
+        if (cr & CR_I) {
+                set_cr(cr & ~CR_I);
+                __invalidate_icache();
+        }
+}
+
+static void __init enable_icache(void)
+{
+        u32 cr;
+
+        cr = get_cr();
+        if (!(cr & CR_I))
+                set_cr(cr | CR_I);
+}
+
+static inline u32 read_extra_features(void)
+{
+        u32 u;
+
+        __asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (u));
+
+        return u;
+}
+
+static inline void write_extra_features(u32 u)
+{
+        __asm__("mcr p15, 1, %0, c15, c1, 0" : : "r" (u));
+}
+
+static void __init disable_l2_prefetch(void)
+{
+        u32 u;
+
+        /*
+         * Read the CPU Extra Features register and verify that the
+         * Disable L2 Prefetch bit is set.
+         */
+        u = read_extra_features();
+        if (!(u & 0x01000000)) {
+                printk(KERN_INFO "Feroceon L2: Disabling L2 prefetch.\n");
+                write_extra_features(u | 0x01000000);
+        }
+}
+
+static void __init enable_l2(void)
+{
+        u32 u;
+
+        u = read_extra_features();
+        if (!(u & 0x00400000)) {
+                printk(KERN_INFO "Feroceon L2: Enabling L2\n");
+
+                invalidate_and_disable_dcache();
+                invalidate_and_disable_icache();
+                write_extra_features(u | 0x00400000);
+                enable_icache();
+                enable_dcache();
+        }
+}
+
+void __init feroceon_l2_init(int __l2_wt_override)
+{
+        l2_wt_override = __l2_wt_override;
+
+        disable_l2_prefetch();
+
+        outer_cache.inv_range = feroceon_l2_inv_range;
+        outer_cache.clean_range = feroceon_l2_clean_range;
+        outer_cache.flush_range = feroceon_l2_flush_range;
+
+        enable_l2();
+
+        printk(KERN_INFO "Feroceon L2: Cache support initialised%s.\n",
+                         l2_wt_override ? ", in WT override mode" : "");
+}
diff --git a/arch/arm/mm/fault-armv.c b/arch/arm/mm/fault-armv.c
index 44558d5f9313..fbfa26058442 100644
--- a/arch/arm/mm/fault-armv.c
+++ b/arch/arm/mm/fault-armv.c
@@ -144,13 +144,17 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
         page = pfn_to_page(pfn);
         mapping = page_mapping(page);
         if (mapping) {
+#ifndef CONFIG_SMP
                 int dirty = test_and_clear_bit(PG_dcache_dirty, &page->flags);
 
                 if (dirty)
                         __flush_dcache_page(mapping, page);
+#endif
 
                 if (cache_is_vivt())
                         make_coherent(mapping, vma, addr, pfn);
+                else if (vma->vm_flags & VM_EXEC)
+                        __flush_icache_all();
         }
 }
 
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index 9df507d36e0b..029ee65fda2b 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -199,6 +199,8 @@ void flush_dcache_page(struct page *page)
                 __flush_dcache_page(mapping, page);
                 if (mapping && cache_is_vivt())
                         __flush_dcache_aliases(mapping, page);
+                else if (mapping)
+                        __flush_icache_all();
         }
 }
 EXPORT_SYMBOL(flush_dcache_page);
diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S
index a02c1712b52d..f2e5884c513a 100644
--- a/arch/arm/mm/proc-feroceon.S
+++ b/arch/arm/mm/proc-feroceon.S
@@ -44,11 +44,31 @@
  */
 #define CACHE_DLINESIZE 32
 
+        .bss
+        .align 3
+__cache_params_loc:
+        .space  8
+
         .text
+__cache_params:
+        .word   __cache_params_loc
+
 /*
  * cpu_feroceon_proc_init()
  */
 ENTRY(cpu_feroceon_proc_init)
+        mrc     p15, 0, r0, c0, c0, 1           @ read cache type register
+        ldr     r1, __cache_params
+        mov     r2, #(16 << 5)
+        tst     r0, #(1 << 16)                  @ get way
+        mov     r0, r0, lsr #18                 @ get cache size order
+        movne   r3, #((4 - 1) << 30)            @ 4-way
+        and     r0, r0, #0xf
+        moveq   r3, #0                          @ 1-way
+        mov     r2, r2, lsl r0                  @ actual cache size
+        movne   r2, r2, lsr #2                  @ turned into # of sets
+        sub     r2, r2, #(1 << 5)
+        stmia   r1, {r2, r3}
         mov     pc, lr
 
 /*
@@ -59,6 +79,13 @@ ENTRY(cpu_feroceon_proc_fin)
         mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
         msr     cpsr_c, ip
         bl      feroceon_flush_kern_cache_all
+
+#if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH)
+        mov     r0, #0
+        mcr     p15, 1, r0, c15, c9, 0          @ clean L2
+        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
+#endif
+
         mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
         bic     r0, r0, #0x1000                 @ ...i............
         bic     r0, r0, #0x000e                 @ ............wca.
@@ -117,11 +144,19 @@ ENTRY(feroceon_flush_user_cache_all)
  */
 ENTRY(feroceon_flush_kern_cache_all)
         mov     r2, #VM_EXEC
-        mov     ip, #0
+
 __flush_whole_cache:
-1:      mrc     p15, 0, r15, c7, c14, 3         @ test,clean,invalidate
-        bne     1b
+        ldr     r1, __cache_params
+        ldmia   r1, {r1, r3}
+1:      orr     ip, r1, r3
+2:      mcr     p15, 0, ip, c7, c14, 2          @ clean + invalidate D set/way
+        subs    ip, ip, #(1 << 30)              @ next way
+        bcs     2b
+        subs    r1, r1, #(1 << 5)               @ next set
+        bcs     1b
+
         tst     r2, #VM_EXEC
+        mov     ip, #0
         mcrne   p15, 0, ip, c7, c5, 0           @ invalidate I cache
         mcrne   p15, 0, ip, c7, c10, 4          @ drain WB
         mov     pc, lr
@@ -138,7 +173,6 @@ __flush_whole_cache:
  */
         .align  5
 ENTRY(feroceon_flush_user_cache_range)
-        mov     ip, #0
         sub     r3, r1, r0                      @ calculate total size
         cmp     r3, #CACHE_DLIMIT
         bgt     __flush_whole_cache
@@ -152,6 +186,7 @@ ENTRY(feroceon_flush_user_cache_range)
         cmp     r0, r1
         blo     1b
         tst     r2, #VM_EXEC
+        mov     ip, #0
         mcrne   p15, 0, ip, c7, c10, 4          @ drain WB
         mov     pc, lr
 
@@ -209,6 +244,20 @@ ENTRY(feroceon_flush_kern_dcache_page)
         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
         mov     pc, lr
 
+        .align  5
+ENTRY(feroceon_range_flush_kern_dcache_page)
+        mrs     r2, cpsr
+        add     r1, r0, #PAGE_SZ - CACHE_DLINESIZE      @ top addr is inclusive
+        orr     r3, r2, #PSR_I_BIT
+        msr     cpsr_c, r3                      @ disable interrupts
+        mcr     p15, 5, r0, c15, c15, 0         @ D clean/inv range start
+        mcr     p15, 5, r1, c15, c15, 1         @ D clean/inv range top
+        msr     cpsr_c, r2                      @ restore interrupts
+        mov     r0, #0
+        mcr     p15, 0, r0, c7, c5, 0           @ invalidate I cache
+        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
+        mov     pc, lr
+
 /*
  *      dma_inv_range(start, end)
  *
@@ -225,10 +274,10 @@ ENTRY(feroceon_flush_kern_dcache_page)
         .align  5
 ENTRY(feroceon_dma_inv_range)
         tst     r0, #CACHE_DLINESIZE - 1
+        bic     r0, r0, #CACHE_DLINESIZE - 1
         mcrne   p15, 0, r0, c7, c10, 1          @ clean D entry
         tst     r1, #CACHE_DLINESIZE - 1
         mcrne   p15, 0, r1, c7, c10, 1          @ clean D entry
-        bic     r0, r0, #CACHE_DLINESIZE - 1
 1:      mcr     p15, 0, r0, c7, c6, 1           @ invalidate D entry
         add     r0, r0, #CACHE_DLINESIZE
         cmp     r0, r1
@@ -236,6 +285,22 @@ ENTRY(feroceon_dma_inv_range)
         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
         mov     pc, lr
 
+        .align  5
+ENTRY(feroceon_range_dma_inv_range)
+        mrs     r2, cpsr
+        tst     r0, #CACHE_DLINESIZE - 1
+        mcrne   p15, 0, r0, c7, c10, 1          @ clean D entry
+        tst     r1, #CACHE_DLINESIZE - 1
+        mcrne   p15, 0, r1, c7, c10, 1          @ clean D entry
+        cmp     r1, r0
+        subne   r1, r1, #1                      @ top address is inclusive
+        orr     r3, r2, #PSR_I_BIT
+        msr     cpsr_c, r3                      @ disable interrupts
+        mcr     p15, 5, r0, c15, c14, 0         @ D inv range start
+        mcr     p15, 5, r1, c15, c14, 1         @ D inv range top
+        msr     cpsr_c, r2                      @ restore interrupts
+        mov     pc, lr
+
 /*
  *      dma_clean_range(start, end)
  *
@@ -256,6 +321,19 @@ ENTRY(feroceon_dma_clean_range)
         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
         mov     pc, lr
 
+        .align  5
+ENTRY(feroceon_range_dma_clean_range)
+        mrs     r2, cpsr
+        cmp     r1, r0
+        subne   r1, r1, #1                      @ top address is inclusive
+        orr     r3, r2, #PSR_I_BIT
+        msr     cpsr_c, r3                      @ disable interrupts
+        mcr     p15, 5, r0, c15, c13, 0         @ D clean range start
+        mcr     p15, 5, r1, c15, c13, 1         @ D clean range top
+        msr     cpsr_c, r2                      @ restore interrupts
+        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
+        mov     pc, lr
+
 /*
  *      dma_flush_range(start, end)
  *
@@ -274,6 +352,19 @@ ENTRY(feroceon_dma_flush_range)
         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
         mov     pc, lr
 
+        .align  5
+ENTRY(feroceon_range_dma_flush_range)
+        mrs     r2, cpsr
+        cmp     r1, r0
+        subne   r1, r1, #1                      @ top address is inclusive
+        orr     r3, r2, #PSR_I_BIT
+        msr     cpsr_c, r3                      @ disable interrupts
+        mcr     p15, 5, r0, c15, c15, 0         @ D clean/inv range start
+        mcr     p15, 5, r1, c15, c15, 1         @ D clean/inv range top
+        msr     cpsr_c, r2                      @ restore interrupts
+        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
+        mov     pc, lr
+
 ENTRY(feroceon_cache_fns)
         .long   feroceon_flush_kern_cache_all
         .long   feroceon_flush_user_cache_all
@@ -285,12 +376,33 @@ ENTRY(feroceon_cache_fns)
         .long   feroceon_dma_clean_range
         .long   feroceon_dma_flush_range
 
+ENTRY(feroceon_range_cache_fns)
+        .long   feroceon_flush_kern_cache_all
+        .long   feroceon_flush_user_cache_all
+        .long   feroceon_flush_user_cache_range
+        .long   feroceon_coherent_kern_range
+        .long   feroceon_coherent_user_range
+        .long   feroceon_range_flush_kern_dcache_page
+        .long   feroceon_range_dma_inv_range
+        .long   feroceon_range_dma_clean_range
+        .long   feroceon_range_dma_flush_range
+
         .align  5
 ENTRY(cpu_feroceon_dcache_clean_area)
+#if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH)
+        mov     r2, r0
+        mov     r3, r1
+#endif
 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
         add     r0, r0, #CACHE_DLINESIZE
         subs    r1, r1, #CACHE_DLINESIZE
         bhi     1b
+#if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH)
+1:      mcr     p15, 1, r2, c15, c9, 1          @ clean L2 entry
+        add     r2, r2, #CACHE_DLINESIZE
+        subs    r3, r3, #CACHE_DLINESIZE
+        bhi     1b
+#endif
         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
         mov     pc, lr
 
@@ -306,16 +418,25 @@ ENTRY(cpu_feroceon_dcache_clean_area)
         .align  5
 ENTRY(cpu_feroceon_switch_mm)
 #ifdef CONFIG_MMU
-        mov     ip, #0
-@ && 'Clean & Invalidate whole DCache'
-1:      mrc     p15, 0, r15, c7, c14, 3         @ test,clean,invalidate
-        bne     1b
-        mcr     p15, 0, ip, c7, c5, 0           @ invalidate I cache
-        mcr     p15, 0, ip, c7, c10, 4          @ drain WB
+        /*
+         * Note: we wish to call __flush_whole_cache but we need to preserve
+         * lr to do so.  The only way without touching main memory is to
+         * use r2 which is normally used to test the VM_EXEC flag, and
+         * compensate locally for the skipped ops if it is not set.
+         */
+        mov     r2, lr                          @ abuse r2 to preserve lr
+        bl      __flush_whole_cache
+        @ if r2 contains the VM_EXEC bit then the next 2 ops are done already
+        tst     r2, #VM_EXEC
+        mcreq   p15, 0, ip, c7, c5, 0           @ invalidate I cache
+        mcreq   p15, 0, ip, c7, c10, 4          @ drain WB
+
         mcr     p15, 0, r0, c2, c0, 0           @ load page table pointer
         mcr     p15, 0, ip, c8, c7, 0           @ invalidate I & D TLBs
-#endif
+        mov     pc, r2
+#else
         mov     pc, lr
+#endif
 
 /*
  * cpu_feroceon_set_pte_ext(ptep, pte, ext)
@@ -345,6 +466,9 @@ ENTRY(cpu_feroceon_set_pte_ext)
         str     r2, [r0]                        @ hardware version
         mov     r0, r0
         mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
+#if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH)
+        mcr     p15, 1, r0, c15, c9, 1          @ clean L2 entry
+#endif
         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
 #endif
         mov     pc, lr
@@ -369,14 +493,15 @@ __feroceon_setup:
         .size   __feroceon_setup, . - __feroceon_setup
 
         /*
-         *  R
-         * .RVI ZFRS BLDP WCAM
-         * .011 0001 ..11 0101
+         *      B
+         *  R   P
+         * .RVI UFRS BLDP WCAM
+         * .011 .001 ..11 0101
          *
          */
         .type   feroceon_crval, #object
 feroceon_crval:
-        crval   clear=0x00007f3f, mmuset=0x00003135, ucset=0x00001134
+        crval   clear=0x0000773f, mmuset=0x00003135, ucset=0x00001134
 
         __INITDATA
 
@@ -414,6 +539,21 @@ cpu_feroceon_name:
         .asciz  "Feroceon"
         .size   cpu_feroceon_name, . - cpu_feroceon_name
 
+        .type   cpu_88fr531_name, #object
+cpu_88fr531_name:
+        .asciz  "Feroceon 88FR531-vd"
+        .size   cpu_88fr531_name, . - cpu_88fr531_name
+
+        .type   cpu_88fr571_name, #object
+cpu_88fr571_name:
+        .asciz  "Feroceon 88FR571-vd"
+        .size   cpu_88fr571_name, . - cpu_88fr571_name
+
+        .type   cpu_88fr131_name, #object
+cpu_88fr131_name:
+        .asciz  "Feroceon 88FR131"
+        .size   cpu_88fr131_name, . - cpu_88fr131_name
+
         .align
 
         .section ".proc.info.init", #alloc, #execinstr
@@ -421,15 +561,15 @@ cpu_feroceon_name:
 #ifdef CONFIG_CPU_FEROCEON_OLD_ID
         .type   __feroceon_old_id_proc_info,#object
 __feroceon_old_id_proc_info:
-        .long   0x41069260
-        .long   0xfffffff0
-        .long   PMD_TYPE_SECT | \
+        .long   0x41009260
+        .long   0xff00fff0
+        .long   PMD_TYPE_SECT | \
                 PMD_SECT_BUFFERABLE | \
                 PMD_SECT_CACHEABLE | \
                 PMD_BIT4 | \
                 PMD_SECT_AP_WRITE | \
                 PMD_SECT_AP_READ
-        .long   PMD_TYPE_SECT | \
+        .long   PMD_TYPE_SECT | \
                 PMD_BIT4 | \
                 PMD_SECT_AP_WRITE | \
                 PMD_SECT_AP_READ
@@ -445,17 +585,17 @@ __feroceon_old_id_proc_info:
         .size   __feroceon_old_id_proc_info, . - __feroceon_old_id_proc_info
 #endif
 
-        .type   __feroceon_proc_info,#object
-__feroceon_proc_info:
+        .type   __88fr531_proc_info,#object
+__88fr531_proc_info:
         .long   0x56055310
         .long   0xfffffff0
-        .long   PMD_TYPE_SECT | \
+        .long   PMD_TYPE_SECT | \
                 PMD_SECT_BUFFERABLE | \
                 PMD_SECT_CACHEABLE | \
                 PMD_BIT4 | \
                 PMD_SECT_AP_WRITE | \
                 PMD_SECT_AP_READ
-        .long   PMD_TYPE_SECT | \
+        .long   PMD_TYPE_SECT | \
                 PMD_BIT4 | \
                 PMD_SECT_AP_WRITE | \
                 PMD_SECT_AP_READ
@@ -463,9 +603,59 @@ __feroceon_proc_info:
         .long   cpu_arch_name
         .long   cpu_elf_name
         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
-        .long   cpu_feroceon_name
+        .long   cpu_88fr531_name
         .long   feroceon_processor_functions
         .long   v4wbi_tlb_fns
         .long   feroceon_user_fns
         .long   feroceon_cache_fns
-        .size   __feroceon_proc_info, . - __feroceon_proc_info
+        .size   __88fr531_proc_info, . - __88fr531_proc_info
+
+        .type   __88fr571_proc_info,#object
+__88fr571_proc_info:
+        .long   0x56155710
+        .long   0xfffffff0
+        .long   PMD_TYPE_SECT | \
+                PMD_SECT_BUFFERABLE | \
+                PMD_SECT_CACHEABLE | \
+                PMD_BIT4 | \
+                PMD_SECT_AP_WRITE | \
+                PMD_SECT_AP_READ
+        .long   PMD_TYPE_SECT | \
+                PMD_BIT4 | \
+                PMD_SECT_AP_WRITE | \
+                PMD_SECT_AP_READ
+        b       __feroceon_setup
+        .long   cpu_arch_name
+        .long   cpu_elf_name
+        .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
+        .long   cpu_88fr571_name
+        .long   feroceon_processor_functions
+        .long   v4wbi_tlb_fns
+        .long   feroceon_user_fns
+        .long   feroceon_range_cache_fns
+        .size   __88fr571_proc_info, . - __88fr571_proc_info
+
+        .type   __88fr131_proc_info,#object
+__88fr131_proc_info:
+        .long   0x56251310
+        .long   0xfffffff0
+        .long   PMD_TYPE_SECT | \
+                PMD_SECT_BUFFERABLE | \
+                PMD_SECT_CACHEABLE | \
+                PMD_BIT4 | \
+                PMD_SECT_AP_WRITE | \
+                PMD_SECT_AP_READ
+        .long   PMD_TYPE_SECT | \
+                PMD_BIT4 | \
+                PMD_SECT_AP_WRITE | \
+                PMD_SECT_AP_READ
+        b       __feroceon_setup
+        .long   cpu_arch_name
+        .long   cpu_elf_name
+        .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
+        .long   cpu_88fr131_name
+        .long   feroceon_processor_functions
+        .long   v4wbi_tlb_fns
+        .long   feroceon_user_fns
+        .long   feroceon_range_cache_fns
+        .size   __88fr131_proc_info, . - __88fr131_proc_info
diff --git a/arch/arm/plat-iop/gpio.c b/arch/arm/plat-iop/gpio.c
index eda436083417..640e498c12ef 100644
--- a/arch/arm/plat-iop/gpio.c
+++ b/arch/arm/plat-iop/gpio.c
@@ -11,6 +11,10 @@
  */
 
 #include <linux/device.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/gpio.h>
 #include <asm/hardware/iop3xx.h>
 
 void gpio_line_config(int line, int direction)
@@ -46,3 +50,42 @@ void gpio_line_set(int line, int value)
         local_irq_restore(flags);
 }
 EXPORT_SYMBOL(gpio_line_set);
+
+static int iop3xx_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
+{
+        gpio_line_config(gpio, GPIO_IN);
+        return 0;
+}
+
+static int iop3xx_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int level)
+{
+        gpio_line_set(gpio, level);
+        gpio_line_config(gpio, GPIO_OUT);
+        return 0;
+}
+
+static int iop3xx_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
+{
+        return gpio_line_get(gpio);
+}
+
+static void iop3xx_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
+{
+        gpio_line_set(gpio, value);
+}
+
+static struct gpio_chip iop3xx_chip = {
+        .label                  = "iop3xx",
+        .direction_input        = iop3xx_gpio_direction_input,
+        .get                    = iop3xx_gpio_get_value,
+        .direction_output       = iop3xx_gpio_direction_output,
+        .set                    = iop3xx_gpio_set_value,
+        .base                   = 0,
+        .ngpio                  = IOP3XX_N_GPIOS,
+};
+
+static int __init iop3xx_gpio_setup(void)
+{
+        return gpiochip_add(&iop3xx_chip);
+}
+arch_initcall(iop3xx_gpio_setup);
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index bb6e12738fb3..e14eaad11dd5 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -3,9 +3,14 @@ if ARCH_MXC
 menu "Freescale MXC Implementations"
 
 choice
-        prompt "MXC/iMX System Type"
+        prompt "MXC/iMX Base Type"
         default ARCH_MX3
 
+config ARCH_MX2
+        bool "MX2-based"
+        help
+          This enables support for systems based on the Freescale i.MX2 family
+
 config ARCH_MX3
         bool "MX3-based"
         help
@@ -13,6 +18,7 @@ config ARCH_MX3
 
 endchoice
 
+source "arch/arm/mach-mx2/Kconfig"
 source "arch/arm/mach-mx3/Kconfig"
 
 endmenu
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index f96dc0362068..db66e9ae8414 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -3,4 +3,6 @@
 #
 
 # Common support
-obj-y := irq.o
+obj-y := irq.o clock.o gpio.o time.o
+
+obj-$(CONFIG_ARCH_MX2) += iomux-mx1-mx2.o
diff --git a/arch/arm/plat-mxc/clock.c b/arch/arm/plat-mxc/clock.c
new file mode 100644
index 000000000000..1aa86fd60d71
--- /dev/null
+++ b/arch/arm/plat-mxc/clock.c
@@ -0,0 +1,331 @@
+/*
+ * Based on arch/arm/plat-omap/clock.c
+ *
+ * Copyright (C) 2004 - 2005 Nokia corporation
+ * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
+ * Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
+ * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
+ */
+
+/* #define DEBUG */
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/platform_device.h>
+#include <linux/proc_fs.h>
+#include <linux/semaphore.h>
+#include <linux/string.h>
+#include <linux/version.h>
+
+#include <asm/arch/clock.h>
+
+static LIST_HEAD(clocks);
+static DEFINE_MUTEX(clocks_mutex);
+
+/*-------------------------------------------------------------------------
+ * Standard clock functions defined in include/linux/clk.h
+ *-------------------------------------------------------------------------*/
+
+/*
+ * Retrieve a clock by name.
+ *
+ * Note that we first try to use device id on the bus
+ * and clock name. If this fails, we try to use "<name>.<id>". If this fails,
+ * we try to use clock name only.
+ * The reference count to the clock's module owner ref count is incremented.
+ */
+struct clk *clk_get(struct device *dev, const char *id)
+{
+        struct clk *p, *clk = ERR_PTR(-ENOENT);
+        int idno;
+        const char *str;
+
+        if (id == NULL)
+                return clk;
+
+        if (dev == NULL || dev->bus != &platform_bus_type)
+                idno = -1;
+        else
+                idno = to_platform_device(dev)->id;
+
+        mutex_lock(&clocks_mutex);
+
+        list_for_each_entry(p, &clocks, node) {
+                if (p->id == idno &&
+                    strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
+                        clk = p;
+                        goto found;
+                }
+        }
+
+        str = strrchr(id, '.');
+        if (str) {
+                int cnt = str - id;
+                str++;
+                idno = simple_strtol(str, NULL, 10);
+                list_for_each_entry(p, &clocks, node) {
+                        if (p->id == idno &&
+                            strlen(p->name) == cnt &&
+                            strncmp(id, p->name, cnt) == 0 &&
+                            try_module_get(p->owner)) {
+                                clk = p;
+                                goto found;
+                        }
+                }
+        }
+
+        list_for_each_entry(p, &clocks, node) {
+                if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
+                        clk = p;
+                        goto found;
+                }
+        }
+
+        printk(KERN_WARNING "clk: Unable to get requested clock: %s\n", id);
+
+found:
+        mutex_unlock(&clocks_mutex);
+
+        return clk;
+}
+EXPORT_SYMBOL(clk_get);
+
+static void __clk_disable(struct clk *clk)
+{
+        if (clk == NULL || IS_ERR(clk))
+                return;
+
+        __clk_disable(clk->parent);
+        __clk_disable(clk->secondary);
+
+        if (!(--clk->usecount) && clk->disable)
+                clk->disable(clk);
+}
+
+static int __clk_enable(struct clk *clk)
+{
+        if (clk == NULL || IS_ERR(clk))
+                return -EINVAL;
+
+        __clk_enable(clk->parent);
+        __clk_enable(clk->secondary);
+
+        if (clk->usecount++ == 0 && clk->enable)
+                clk->enable(clk);
+
+        return 0;
+}
+
+/* This function increments the reference count on the clock and enables the
+ * clock if not already enabled. The parent clock tree is recursively enabled
+ */
+int clk_enable(struct clk *clk)
+{
+        int ret = 0;
+
+        if (clk == NULL || IS_ERR(clk))
+                return -EINVAL;
+
+        mutex_lock(&clocks_mutex);
+        ret = __clk_enable(clk);
+        mutex_unlock(&clocks_mutex);
+
+        return ret;
+}
+EXPORT_SYMBOL(clk_enable);
+
+/* This function decrements the reference count on the clock and disables
+ * the clock when reference count is 0. The parent clock tree is
+ * recursively disabled
+ */
+void clk_disable(struct clk *clk)
+{
+        if (clk == NULL || IS_ERR(clk))
+                return;
+
+        mutex_lock(&clocks_mutex);
+        __clk_disable(clk);
+        mutex_unlock(&clocks_mutex);
+}
+EXPORT_SYMBOL(clk_disable);
+
+/* Retrieve the *current* clock rate. If the clock itself
+ * does not provide a special calculation routine, ask
+ * its parent and so on, until one is able to return
+ * a valid clock rate
+ */
+unsigned long clk_get_rate(struct clk *clk)
+{
+        if (clk == NULL || IS_ERR(clk))
+                return 0UL;
+
+        if (clk->get_rate)
+                return clk->get_rate(clk);
+
+        return clk_get_rate(clk->parent);
+}
+EXPORT_SYMBOL(clk_get_rate);
+
+/* Decrement the clock's module reference count */
+void clk_put(struct clk *clk)
+{
+        if (clk && !IS_ERR(clk))
+                module_put(clk->owner);
+}
+EXPORT_SYMBOL(clk_put);
+
+/* Round the requested clock rate to the nearest supported
+ * rate that is less than or equal to the requested rate.
+ * This is dependent on the clock's current parent.
+ */
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+        if (clk == NULL || IS_ERR(clk) || !clk->round_rate)
+                return 0;
+
+        return clk->round_rate(clk, rate);
+}
+EXPORT_SYMBOL(clk_round_rate);
+
+/* Set the clock to the requested clock rate. The rate must
+ * match a supported rate exactly based on what clk_round_rate returns
+ */
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+        int ret = -EINVAL;
+
+        if (clk == NULL || IS_ERR(clk) || clk->set_rate == NULL || rate == 0)
+                return ret;
+
+        mutex_lock(&clocks_mutex);
+        ret = clk->set_rate(clk, rate);
+        mutex_unlock(&clocks_mutex);
+
+        return ret;
+}
+EXPORT_SYMBOL(clk_set_rate);
+
+/* Set the clock's parent to another clock source */
+int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+        int ret = -EINVAL;
+
+        if (clk == NULL || IS_ERR(clk) || parent == NULL ||
+            IS_ERR(parent) || clk->set_parent == NULL)
+                return ret;
+
+        mutex_lock(&clocks_mutex);
+        ret = clk->set_parent(clk, parent);
+        if (ret == 0)
+                clk->parent = parent;
+        mutex_unlock(&clocks_mutex);
+
+        return ret;
+}
+EXPORT_SYMBOL(clk_set_parent);
+
+/* Retrieve the clock's parent clock source */
+struct clk *clk_get_parent(struct clk *clk)
+{
+        struct clk *ret = NULL;
+
+        if (clk == NULL || IS_ERR(clk))
+                return ret;
+
+        return clk->parent;
+}
+EXPORT_SYMBOL(clk_get_parent);
+
+/*
+ * Add a new clock to the clock tree.
+ */
+int clk_register(struct clk *clk)
+{
+        if (clk == NULL || IS_ERR(clk))
+                return -EINVAL;
+
+        mutex_lock(&clocks_mutex);
+        list_add(&clk->node, &clocks);
+        mutex_unlock(&clocks_mutex);
+
+        return 0;
+}
+EXPORT_SYMBOL(clk_register);
+
+/* Remove a clock from the clock tree */
+void clk_unregister(struct clk *clk)
+{
+        if (clk == NULL || IS_ERR(clk))
+                return;
+
+        mutex_lock(&clocks_mutex);
+        list_del(&clk->node);
+        mutex_unlock(&clocks_mutex);
+}
+EXPORT_SYMBOL(clk_unregister);
+
+#ifdef CONFIG_PROC_FS
+static int mxc_clock_read_proc(char *page, char **start, off_t off,
+                                int count, int *eof, void *data)
+{
+        struct clk *clkp;
+        char *p = page;
+        int len;
+
+        list_for_each_entry(clkp, &clocks, node) {
+                p += sprintf(p, "%s-%d:\t\t%lu, %d", clkp->name, clkp->id,
+                                clk_get_rate(clkp), clkp->usecount);
+                if (clkp->parent)
+                        p += sprintf(p, ", %s-%d\n", clkp->parent->name,
+                                     clkp->parent->id);
+                else
+                        p += sprintf(p, "\n");
+        }
+
+        len = (p - page) - off;
+        if (len < 0)
+                len = 0;
+
+        *eof = (len <= count) ? 1 : 0;
+        *start = page + off;
+
+        return len;
+}
+
+static int __init mxc_setup_proc_entry(void)
+{
+        struct proc_dir_entry *res;
+
+        res = create_proc_read_entry("cpu/clocks", 0, NULL,
+                                     mxc_clock_read_proc, NULL);
+        if (!res) {
+                printk(KERN_ERR "Failed to create proc/cpu/clocks\n");
+                return -ENOMEM;
+        }
+        return 0;
+}
+
+late_initcall(mxc_setup_proc_entry);
+#endif
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
new file mode 100644
index 000000000000..4a7736717d86
--- /dev/null
+++ b/arch/arm/plat-mxc/gpio.c
@@ -0,0 +1,253 @@
+/*
+ * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * Based on code from Freescale,
+ * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+#include <asm/hardware.h>
+#include <asm-generic/bug.h>
+
+static struct mxc_gpio_port *mxc_gpio_ports;
+static int gpio_table_size;
+
+/* Note: This driver assumes 32 GPIOs are handled in one register */
+
+static void _clear_gpio_irqstatus(struct mxc_gpio_port *port, u32 index)
+{
+        __raw_writel(1 << index, port->base + GPIO_ISR);
+}
+
+static void _set_gpio_irqenable(struct mxc_gpio_port *port, u32 index,
+                                int enable)
+{
+        u32 l;
+
+        l = __raw_readl(port->base + GPIO_IMR);
+        l = (l & (~(1 << index))) | (!!enable << index);
+        __raw_writel(l, port->base + GPIO_IMR);
+}
+
+static void gpio_ack_irq(u32 irq)
+{
+        u32 gpio = irq_to_gpio(irq);
+        _clear_gpio_irqstatus(&mxc_gpio_ports[gpio / 32], gpio & 0x1f);
+}
+
+static void gpio_mask_irq(u32 irq)
+{
+        u32 gpio = irq_to_gpio(irq);
+        _set_gpio_irqenable(&mxc_gpio_ports[gpio / 32], gpio & 0x1f, 0);
+}
+
+static void gpio_unmask_irq(u32 irq)
+{
+        u32 gpio = irq_to_gpio(irq);
+        _set_gpio_irqenable(&mxc_gpio_ports[gpio / 32], gpio & 0x1f, 1);
+}
+
+static int gpio_set_irq_type(u32 irq, u32 type)
+{
+        u32 gpio = irq_to_gpio(irq);
+        struct mxc_gpio_port *port = &mxc_gpio_ports[gpio / 32];
+        u32 bit, val;
+        int edge;
+        void __iomem *reg = port->base;
+
+        switch (type) {
+        case IRQT_RISING:
+                edge = GPIO_INT_RISE_EDGE;
+                break;
+        case IRQT_FALLING:
+                edge = GPIO_INT_FALL_EDGE;
+                break;
+        case IRQT_LOW:
+                edge = GPIO_INT_LOW_LEV;
+                break;
+        case IRQT_HIGH:
+                edge = GPIO_INT_HIGH_LEV;
+                break;
+        default:        /* this includes IRQT_BOTHEDGE */
+                return -EINVAL;
+        }
+
+        reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
+        bit = gpio & 0xf;
+        val = __raw_readl(reg) & ~(0x3 << (bit << 1));
+        __raw_writel(val | (edge << (bit << 1)), reg);
+        _clear_gpio_irqstatus(port, gpio & 0x1f);
+
+        return 0;
+}
+
+/* handle n interrupts in one status register */
+static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
+{
+        u32 gpio_irq_no;
+
+        gpio_irq_no = port->virtual_irq_start;
+        for (; irq_stat != 0; irq_stat >>= 1, gpio_irq_no++) {
+
+                if ((irq_stat & 1) == 0)
+                        continue;
+
+                BUG_ON(!(irq_desc[gpio_irq_no].handle_irq));
+                irq_desc[gpio_irq_no].handle_irq(gpio_irq_no,
+                                &irq_desc[gpio_irq_no]);
+        }
+}
+
+#ifdef CONFIG_ARCH_MX3
+/* MX3 has one interrupt *per* gpio port */
+static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
+{
+        u32 irq_stat;
+        struct mxc_gpio_port *port = (struct mxc_gpio_port *)get_irq_data(irq);
+
+        irq_stat = __raw_readl(port->base + GPIO_ISR) &
+                        __raw_readl(port->base + GPIO_IMR);
+        BUG_ON(!irq_stat);
+        mxc_gpio_irq_handler(port, irq_stat);
+}
+#endif
+
+#ifdef CONFIG_ARCH_MX2
+/* MX2 has one interrupt *for all* gpio ports */
+static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
+{
+        int i;
+        u32 irq_msk, irq_stat;
+        struct mxc_gpio_port *port = (struct mxc_gpio_port *)get_irq_data(irq);
+
+        /* walk through all interrupt status registers */
+        for (i = 0; i < gpio_table_size; i++) {
+                irq_msk = __raw_readl(port[i].base + GPIO_IMR);
+                if (!irq_msk)
+                        continue;
+
+                irq_stat = __raw_readl(port[i].base + GPIO_ISR) & irq_msk;
+                if (irq_stat)
+                        mxc_gpio_irq_handler(&port[i], irq_stat);
+        }
+}
+#endif
+
+static struct irq_chip gpio_irq_chip = {
+        .ack = gpio_ack_irq,
+        .mask = gpio_mask_irq,
+        .unmask = gpio_unmask_irq,
+        .set_type = gpio_set_irq_type,
+};
+
+static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset,
+                                int dir)
+{
+        struct mxc_gpio_port *port =
+                container_of(chip, struct mxc_gpio_port, chip);
+        u32 l;
+
+        l = __raw_readl(port->base + GPIO_GDIR);
+        if (dir)
+                l |= 1 << offset;
+        else
+                l &= ~(1 << offset);
+        __raw_writel(l, port->base + GPIO_GDIR);
+}
+
+static void mxc_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+        struct mxc_gpio_port *port =
+                container_of(chip, struct mxc_gpio_port, chip);
+        void __iomem *reg = port->base + GPIO_DR;
+        u32 l;
+
+        l = (__raw_readl(reg) & (~(1 << offset))) | (value << offset);
+        __raw_writel(l, reg);
+}
+
+static int mxc_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+        struct mxc_gpio_port *port =
+                container_of(chip, struct mxc_gpio_port, chip);
+
+        return (__raw_readl(port->base + GPIO_DR) >> offset) & 1;
+}
+
+static int mxc_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+        _set_gpio_direction(chip, offset, 0);
+        return 0;
+}
+
+static int mxc_gpio_direction_output(struct gpio_chip *chip,
+                                     unsigned offset, int value)
+{
+        _set_gpio_direction(chip, offset, 1);
+        mxc_gpio_set(chip, offset, value);
+        return 0;
+}
+
+int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
+{
+        int i, j;
+
+        /* save for local usage */
+        mxc_gpio_ports = port;
+        gpio_table_size = cnt;
+
+        printk(KERN_INFO "MXC GPIO hardware\n");
+
+        for (i = 0; i < cnt; i++) {
+                /* disable the interrupt and clear the status */
+                __raw_writel(0, port[i].base + GPIO_IMR);
+                __raw_writel(~0, port[i].base + GPIO_ISR);
+                for (j = port[i].virtual_irq_start;
+                        j < port[i].virtual_irq_start + 32; j++) {
+                        set_irq_chip(j, &gpio_irq_chip);
+                        set_irq_handler(j, handle_edge_irq);
+                        set_irq_flags(j, IRQF_VALID);
+                }
+
+                /* register gpio chip */
+                port[i].chip.direction_input = mxc_gpio_direction_input;
+                port[i].chip.direction_output = mxc_gpio_direction_output;
+                port[i].chip.get = mxc_gpio_get;
+                port[i].chip.set = mxc_gpio_set;
+                port[i].chip.base = i * 32;
+                port[i].chip.ngpio = 32;
+
+                /* its a serious configuration bug when it fails */
+                BUG_ON( gpiochip_add(&port[i].chip) < 0 );
+
+#ifdef CONFIG_ARCH_MX3
+                /* setup one handler for each entry */
+                set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler);
+                set_irq_data(port[i].irq, &port[i]);
+#endif
+        }
+
+#ifdef CONFIG_ARCH_MX2
+        /* setup one handler for all GPIO interrupts */
+        set_irq_chained_handler(port[0].irq, mx2_gpio_irq_handler);
+        set_irq_data(port[0].irq, port);
+#endif
+        return 0;
+}
diff --git a/arch/arm/plat-mxc/iomux-mx1-mx2.c b/arch/arm/plat-mxc/iomux-mx1-mx2.c
new file mode 100644
index 000000000000..1985571eb40c
--- /dev/null
+++ b/arch/arm/plat-mxc/iomux-mx1-mx2.c
@@ -0,0 +1,156 @@
+/*
+ *  arch/arm/mach-mxc/generic.c
+ *
+ *  author: Sascha Hauer
+ *  Created: april 20th, 2004
+ *  Copyright: Synertronixx GmbH
+ *
+ *  Common code for i.MX machines
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/string.h>
+#include <linux/gpio.h>
+
+#include <asm/hardware.h>
+#include <asm/mach/map.h>
+#include <asm/arch/iomux-mx1-mx2.h>
+
+void mxc_gpio_mode(int gpio_mode)
+{
+        unsigned int pin = gpio_mode & GPIO_PIN_MASK;
+        unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
+        unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT;
+        unsigned int tmp;
+
+        /* Pullup enable */
+        tmp = __raw_readl(VA_GPIO_BASE + MXC_PUEN(port));
+        if (gpio_mode & GPIO_PUEN)
+                tmp |= (1 << pin);
+        else
+                tmp &= ~(1 << pin);
+        __raw_writel(tmp, VA_GPIO_BASE + MXC_PUEN(port));
+
+        /* Data direction */
+        tmp = __raw_readl(VA_GPIO_BASE + MXC_DDIR(port));
+        if (gpio_mode & GPIO_OUT)
+                tmp |= 1 << pin;
+        else
+                tmp &= ~(1 << pin);
+        __raw_writel(tmp, VA_GPIO_BASE + MXC_DDIR(port));
+
+        /* Primary / alternate function */
+        tmp = __raw_readl(VA_GPIO_BASE + MXC_GPR(port));
+        if (gpio_mode & GPIO_AF)
+                tmp |= (1 << pin);
+        else
+                tmp &= ~(1 << pin);
+        __raw_writel(tmp, VA_GPIO_BASE + MXC_GPR(port));
+
+        /* use as gpio? */
+        tmp = __raw_readl(VA_GPIO_BASE + MXC_GIUS(port));
+        if (gpio_mode & (GPIO_PF | GPIO_AF))
+                tmp &= ~(1 << pin);
+        else
+                tmp |= (1 << pin);
+        __raw_writel(tmp, VA_GPIO_BASE + MXC_GIUS(port));
+
+        if (pin < 16) {
+                tmp = __raw_readl(VA_GPIO_BASE + MXC_OCR1(port));
+                tmp &= ~(3 << (pin * 2));
+                tmp |= (ocr << (pin * 2));
+                __raw_writel(tmp, VA_GPIO_BASE + MXC_OCR1(port));
+
+                tmp = __raw_readl(VA_GPIO_BASE + MXC_ICONFA1(port));
+                tmp &= ~(3 << (pin * 2));
+                tmp |= ((gpio_mode >> GPIO_AOUT_SHIFT) & 3) << (pin * 2);
+                __raw_writel(tmp, VA_GPIO_BASE + MXC_ICONFA1(port));
+
+                tmp = __raw_readl(VA_GPIO_BASE + MXC_ICONFB1(port));
+                tmp &= ~(3 << (pin * 2));
+                tmp |= ((gpio_mode >> GPIO_BOUT_SHIFT) & 3) << (pin * 2);
+                __raw_writel(tmp, VA_GPIO_BASE + MXC_ICONFB1(port));
+        } else {
+                pin -= 16;
+
+                tmp = __raw_readl(VA_GPIO_BASE + MXC_OCR2(port));
+                tmp &= ~(3 << (pin * 2));
+                tmp |= (ocr << (pin * 2));
+                __raw_writel(tmp, VA_GPIO_BASE + MXC_OCR2(port));
+
+                tmp = __raw_readl(VA_GPIO_BASE + MXC_ICONFA2(port));
+                tmp &= ~(3 << (pin * 2));
+                tmp |= ((gpio_mode >> GPIO_AOUT_SHIFT) & 3) << (pin * 2);
+                __raw_writel(tmp, VA_GPIO_BASE + MXC_ICONFA2(port));
+
+                tmp = __raw_readl(VA_GPIO_BASE + MXC_ICONFB2(port));
+                tmp &= ~(3 << (pin * 2));
+                tmp |= ((gpio_mode >> GPIO_BOUT_SHIFT) & 3) << (pin * 2);
+                __raw_writel(tmp, VA_GPIO_BASE + MXC_ICONFB2(port));
+        }
+}
+EXPORT_SYMBOL(mxc_gpio_mode);
+
+int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
+                                int alloc_mode, const char *label)
+{
+        const int *p = pin_list;
+        int i;
+        unsigned gpio;
+        unsigned mode;
+
+        for (i = 0; i < count; i++) {
+                gpio = *p & (GPIO_PIN_MASK | GPIO_PORT_MASK);
+                mode = *p & ~(GPIO_PIN_MASK | GPIO_PORT_MASK);
+
+                if (gpio >= (GPIO_PORT_MAX + 1) * 32)
+                        goto setup_error;
+
+                if (alloc_mode & MXC_GPIO_ALLOC_MODE_RELEASE)
+                        gpio_free(gpio);
+                else if (!(alloc_mode & MXC_GPIO_ALLOC_MODE_NO_ALLOC))
+                        if (gpio_request(gpio, label)
+                           && !(alloc_mode & MXC_GPIO_ALLOC_MODE_TRY_ALLOC))
+                                goto setup_error;
+
+                if (!(alloc_mode & (MXC_GPIO_ALLOC_MODE_ALLOC_ONLY |
+                                    MXC_GPIO_ALLOC_MODE_RELEASE)))
+                        mxc_gpio_mode(gpio | mode);
+
+                p++;
+        }
+        return 0;
+
+setup_error:
+        if (alloc_mode & (MXC_GPIO_ALLOC_MODE_NO_ALLOC |
+            MXC_GPIO_ALLOC_MODE_TRY_ALLOC))
+                return -EINVAL;
+
+        while (p != pin_list) {
+                p--;
+                gpio = *p & (GPIO_PIN_MASK | GPIO_PORT_MASK);
+                gpio_free(gpio);
+        }
+
+        return -EINVAL;
+}
+EXPORT_SYMBOL(mxc_gpio_setup_multiple_pins);
+
diff --git a/arch/arm/plat-mxc/irq.c b/arch/arm/plat-mxc/irq.c
index 2ad5a6917b3f..1fbe01da6925 100644
--- a/arch/arm/plat-mxc/irq.c
+++ b/arch/arm/plat-mxc/irq.c
@@ -1,24 +1,59 @@
 /*
- *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
  */
 
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/module.h>
-#include <linux/moduleparam.h>
-#include <linux/init.h>
-#include <linux/device.h>
-#include <linux/errno.h>
-#include <asm/hardware.h>
+#include <linux/irq.h>
 #include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/mach/irq.h>
 #include <asm/arch/common.h>
 
+#define AVIC_BASE               IO_ADDRESS(AVIC_BASE_ADDR)
+#define AVIC_INTCNTL            (AVIC_BASE + 0x00)      /* int control reg */
+#define AVIC_NIMASK             (AVIC_BASE + 0x04)      /* int mask reg */
+#define AVIC_INTENNUM           (AVIC_BASE + 0x08)      /* int enable number reg */
+#define AVIC_INTDISNUM          (AVIC_BASE + 0x0C)      /* int disable number reg */
+#define AVIC_INTENABLEH         (AVIC_BASE + 0x10)      /* int enable reg high */
+#define AVIC_INTENABLEL         (AVIC_BASE + 0x14)      /* int enable reg low */
+#define AVIC_INTTYPEH           (AVIC_BASE + 0x18)      /* int type reg high */
+#define AVIC_INTTYPEL           (AVIC_BASE + 0x1C)      /* int type reg low */
+#define AVIC_NIPRIORITY7        (AVIC_BASE + 0x20)      /* norm int priority lvl7 */
+#define AVIC_NIPRIORITY6        (AVIC_BASE + 0x24)      /* norm int priority lvl6 */
+#define AVIC_NIPRIORITY5        (AVIC_BASE + 0x28)      /* norm int priority lvl5 */
+#define AVIC_NIPRIORITY4        (AVIC_BASE + 0x2C)      /* norm int priority lvl4 */
+#define AVIC_NIPRIORITY3        (AVIC_BASE + 0x30)      /* norm int priority lvl3 */
+#define AVIC_NIPRIORITY2        (AVIC_BASE + 0x34)      /* norm int priority lvl2 */
+#define AVIC_NIPRIORITY1        (AVIC_BASE + 0x38)      /* norm int priority lvl1 */
+#define AVIC_NIPRIORITY0        (AVIC_BASE + 0x3C)      /* norm int priority lvl0 */
+#define AVIC_NIVECSR            (AVIC_BASE + 0x40)      /* norm int vector/status */
+#define AVIC_FIVECSR            (AVIC_BASE + 0x44)      /* fast int vector/status */
+#define AVIC_INTSRCH            (AVIC_BASE + 0x48)      /* int source reg high */
+#define AVIC_INTSRCL            (AVIC_BASE + 0x4C)      /* int source reg low */
+#define AVIC_INTFRCH            (AVIC_BASE + 0x50)      /* int force reg high */
+#define AVIC_INTFRCL            (AVIC_BASE + 0x54)      /* int force reg low */
+#define AVIC_NIPNDH             (AVIC_BASE + 0x58)      /* norm int pending high */
+#define AVIC_NIPNDL             (AVIC_BASE + 0x5C)      /* norm int pending low */
+#define AVIC_FIPNDH             (AVIC_BASE + 0x60)      /* fast int pending high */
+#define AVIC_FIPNDL             (AVIC_BASE + 0x64)      /* fast int pending low */
+
+#define SYSTEM_PREV_REG         IO_ADDRESS(IIM_BASE_ADDR + 0x20)
+#define SYSTEM_SREV_REG         IO_ADDRESS(IIM_BASE_ADDR + 0x24)
+#define IIM_PROD_REV_SH         3
+#define IIM_PROD_REV_LEN        5
+
 /* Disable interrupt number "irq" in the AVIC */
 static void mxc_mask_irq(unsigned int irq)
 {
@@ -32,7 +67,7 @@ static void mxc_unmask_irq(unsigned int irq)
 }
 
 static struct irq_chip mxc_avic_chip = {
-        .mask_ack = mxc_mask_irq,
+        .ack = mxc_mask_irq,
         .mask = mxc_mask_irq,
         .unmask = mxc_unmask_irq,
 };
@@ -71,5 +106,8 @@ void __init mxc_init_irq(void)
         reg |= (0xF << 28);
         __raw_writel(reg, AVIC_NIPRIORITY6);
 
+        /* init architectures chained interrupt handler */
+        mxc_register_gpios();
+
         printk(KERN_INFO "MXC IRQ initialized\n");
 }
diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c
new file mode 100644
index 000000000000..3bf86343fdf4
--- /dev/null
+++ b/arch/arm/plat-mxc/time.c
@@ -0,0 +1,228 @@
+/*
+ *  linux/arch/arm/plat-mxc/time.c
+ *
+ *  Copyright (C) 2000-2001 Deep Blue Solutions
+ *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ *  Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
+ *  Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/clockchips.h>
+#include <linux/clk.h>
+
+#include <asm/hardware.h>
+#include <asm/mach/time.h>
+#include <asm/arch/common.h>
+#include <asm/arch/mxc_timer.h>
+
+static struct clock_event_device clockevent_mxc;
+static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;
+
+/* clock source for the timer */
+static struct clk *timer_clk;
+
+/* clock source */
+
+static cycle_t mxc_get_cycles(void)
+{
+        return __raw_readl(TIMER_BASE + MXC_TCN);
+}
+
+static struct clocksource clocksource_mxc = {
+        .name           = "mxc_timer1",
+        .rating         = 200,
+        .read           = mxc_get_cycles,
+        .mask           = CLOCKSOURCE_MASK(32),
+        .shift          = 20,
+        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+static int __init mxc_clocksource_init(void)
+{
+        unsigned int clock;
+
+        clock = clk_get_rate(timer_clk);
+
+        clocksource_mxc.mult = clocksource_hz2mult(clock,
+                                        clocksource_mxc.shift);
+        clocksource_register(&clocksource_mxc);
+
+        return 0;
+}
+
+/* clock event */
+
+static int mxc_set_next_event(unsigned long evt,
+                              struct clock_event_device *unused)
+{
+        unsigned long tcmp;
+
+        tcmp = __raw_readl(TIMER_BASE + MXC_TCN) + evt;
+        __raw_writel(tcmp, TIMER_BASE + MXC_TCMP);
+
+        return (int)(tcmp - __raw_readl(TIMER_BASE + MXC_TCN)) < 0 ?
+                                -ETIME : 0;
+}
+
+#ifdef DEBUG
+static const char *clock_event_mode_label[] = {
+        [CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC",
+        [CLOCK_EVT_MODE_ONESHOT]  = "CLOCK_EVT_MODE_ONESHOT",
+        [CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN",
+        [CLOCK_EVT_MODE_UNUSED]   = "CLOCK_EVT_MODE_UNUSED"
+};
+#endif /* DEBUG */
+
+static void mxc_set_mode(enum clock_event_mode mode,
+                                struct clock_event_device *evt)
+{
+        unsigned long flags;
+
+        /*
+         * The timer interrupt generation is disabled at least
+         * for enough time to call mxc_set_next_event()
+         */
+        local_irq_save(flags);
+
+        /* Disable interrupt in GPT module */
+        gpt_irq_disable();
+
+        if (mode != clockevent_mode) {
+                /* Set event time into far-far future */
+                __raw_writel(__raw_readl(TIMER_BASE + MXC_TCN) - 3,
+                                TIMER_BASE + MXC_TCMP);
+                /* Clear pending interrupt */
+                gpt_irq_acknowledge();
+        }
+
+#ifdef DEBUG
+        printk(KERN_INFO "mxc_set_mode: changing mode from %s to %s\n",
+                clock_event_mode_label[clockevent_mode],
+                clock_event_mode_label[mode]);
+#endif /* DEBUG */
+
+        /* Remember timer mode */
+        clockevent_mode = mode;
+        local_irq_restore(flags);
+
+        switch (mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+                printk(KERN_ERR"mxc_set_mode: Periodic mode is not "
+                                "supported for i.MX\n");
+                break;
+        case CLOCK_EVT_MODE_ONESHOT:
+        /*
+         * Do not put overhead of interrupt enable/disable into
+         * mxc_set_next_event(), the core has about 4 minutes
+         * to call mxc_set_next_event() or shutdown clock after
+         * mode switching
+         */
+                local_irq_save(flags);
+                gpt_irq_enable();
+                local_irq_restore(flags);
+                break;
+        case CLOCK_EVT_MODE_SHUTDOWN:
+        case CLOCK_EVT_MODE_UNUSED:
+        case CLOCK_EVT_MODE_RESUME:
+                /* Left event sources disabled, no more interrupts appear */
+                break;
+        }
+}
+
+/*
+ * IRQ handler for the timer
+ */
+static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
+{
+        struct clock_event_device *evt = &clockevent_mxc;
+        uint32_t tstat;
+
+        tstat = __raw_readl(TIMER_BASE + MXC_TSTAT);
+
+        gpt_irq_acknowledge();
+
+        evt->event_handler(evt);
+
+        return IRQ_HANDLED;
+}
+
+static struct irqaction mxc_timer_irq = {
+        .name           = "i.MX Timer Tick",
+        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+        .handler        = mxc_timer_interrupt,
+};
+
+static struct clock_event_device clockevent_mxc = {
+        .name           = "mxc_timer1",
+        .features       = CLOCK_EVT_FEAT_ONESHOT,
+        .shift          = 32,
+        .set_mode       = mxc_set_mode,
+        .set_next_event = mxc_set_next_event,
+        .rating         = 200,
+};
+
+static int __init mxc_clockevent_init(void)
+{
+        unsigned int clock;
+
+        clock = clk_get_rate(timer_clk);
+
+        clockevent_mxc.mult = div_sc(clock, NSEC_PER_SEC,
+                                        clockevent_mxc.shift);
+        clockevent_mxc.max_delta_ns =
+                        clockevent_delta2ns(0xfffffffe, &clockevent_mxc);
+        clockevent_mxc.min_delta_ns =
+                        clockevent_delta2ns(0xff, &clockevent_mxc);
+
+        clockevent_mxc.cpumask = cpumask_of_cpu(0);
+
+        clockevents_register_device(&clockevent_mxc);
+
+        return 0;
+}
+
+void __init mxc_timer_init(const char *clk_timer)
+{
+        timer_clk = clk_get(NULL, clk_timer);
+        if (!timer_clk) {
+                printk(KERN_ERR"Cannot determine timer clock. Giving up.\n");
+                return;
+        }
+
+        clk_enable(timer_clk);
+
+        /*
+         * Initialise to a known state (all timers off, and timing reset)
+         */
+        __raw_writel(0, TIMER_BASE + MXC_TCTL);
+        __raw_writel(0, TIMER_BASE + MXC_TPRER); /* see datasheet note */
+
+        __raw_writel(TCTL_FRR | /* free running */
+                     TCTL_VAL | /* set clocksource and arch specific bits */
+                     TCTL_TEN,  /* start the timer */
+                     TIMER_BASE + MXC_TCTL);
+
+        /* init and register the timer to the framework */
+        mxc_clocksource_init();
+        mxc_clockevent_init();
+
+        /* Make irqs happen */
+        setup_irq(TIMER_INTERRUPT, &mxc_timer_irq);
+}
+
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index bc639a30d6d1..2c4051cc79a1 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -3,7 +3,7 @@
 #
 
 # Common support
-obj-y := common.o sram.o sram-fn.o clock.o devices.o dma.o mux.o gpio.o \
+obj-y := common.o sram.o clock.o devices.o dma.o mux.o gpio.o \
          usb.o fb.o
 obj-m :=
 obj-n :=
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index 2db5580048d8..c2e741de0203 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -1,7 +1,7 @@
 /*
  *  linux/arch/arm/plat-omap/clock.c
  *
- *  Copyright (C) 2004 - 2005 Nokia corporation
+ *  Copyright (C) 2004 - 2008 Nokia corporation
  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
  *
  *  Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
@@ -22,6 +22,7 @@
 #include <linux/mutex.h>
 #include <linux/platform_device.h>
 #include <linux/cpufreq.h>
+#include <linux/debugfs.h>
 
 #include <asm/io.h>
 
@@ -33,41 +34,6 @@ static DEFINE_SPINLOCK(clockfw_lock);
 
 static struct clk_functions *arch_clock;
 
-#ifdef CONFIG_PM_DEBUG
-
-static void print_parents(struct clk *clk)
-{
-        struct clk *p;
-        int printed = 0;
-
-        list_for_each_entry(p, &clocks, node) {
-                if (p->parent == clk && p->usecount) {
-                        if (!clk->usecount && !printed) {
-                                printk("MISMATCH: %s\n", clk->name);
-                                printed = 1;
-                        }
-                        printk("\t%-15s\n", p->name);
-                }
-        }
-}
-
-void clk_print_usecounts(void)
-{
-        unsigned long flags;
-        struct clk *p;
-
-        spin_lock_irqsave(&clockfw_lock, flags);
-        list_for_each_entry(p, &clocks, node) {
-                if (p->usecount)
-                        printk("%-15s: %d\n", p->name, p->usecount);
-                print_parents(p);
-
-        }
-        spin_unlock_irqrestore(&clockfw_lock, flags);
-}
-
-#endif
-
 /*-------------------------------------------------------------------------
  * Standard clock functions defined in include/linux/clk.h
  *-------------------------------------------------------------------------*/
@@ -446,3 +412,93 @@ int __init clk_init(struct clk_functions * custom_clocks)
         return 0;
 }
 
+#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
+/*
+ *      debugfs support to trace clock tree hierarchy and attributes
+ */
+static struct dentry *clk_debugfs_root;
+
+static int clk_debugfs_register_one(struct clk *c)
+{
+        int err;
+        struct dentry *d, *child;
+        struct clk *pa = c->parent;
+        char s[255];
+        char *p = s;
+
+        p += sprintf(p, "%s", c->name);
+        if (c->id != 0)
+                sprintf(p, ":%d", c->id);
+        d = debugfs_create_dir(s, pa ? pa->dent : clk_debugfs_root);
+        if (IS_ERR(d))
+                return PTR_ERR(d);
+        c->dent = d;
+
+        d = debugfs_create_u8("usecount", S_IRUGO, c->dent, (u8 *)&c->usecount);
+        if (IS_ERR(d)) {
+                err = PTR_ERR(d);
+                goto err_out;
+        }
+        d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate);
+        if (IS_ERR(d)) {
+                err = PTR_ERR(d);
+                goto err_out;
+        }
+        d = debugfs_create_x32("flags", S_IRUGO, c->dent, (u32 *)&c->flags);
+        if (IS_ERR(d)) {
+                err = PTR_ERR(d);
+                goto err_out;
+        }
+        return 0;
+
+err_out:
+        d = c->dent;
+        list_for_each_entry(child, &d->d_subdirs, d_u.d_child)
+                debugfs_remove(child);
+        debugfs_remove(c->dent);
+        return err;
+}
+
+static int clk_debugfs_register(struct clk *c)
+{
+        int err;
+        struct clk *pa = c->parent;
+
+        if (pa && !pa->dent) {
+                err = clk_debugfs_register(pa);
+                if (err)
+                        return err;
+        }
+
+        if (!c->dent) {
+                err = clk_debugfs_register_one(c);
+                if (err)
+                        return err;
+        }
+        return 0;
+}
+
+static int __init clk_debugfs_init(void)
+{
+        struct clk *c;
+        struct dentry *d;
+        int err;
+
+        d = debugfs_create_dir("clock", NULL);
+        if (IS_ERR(d))
+                return PTR_ERR(d);
+        clk_debugfs_root = d;
+
+        list_for_each_entry(c, &clocks, node) {
+                err = clk_debugfs_register(c);
+                if (err)
+                        goto err_out;
+        }
+        return 0;
+err_out:
+        debugfs_remove(clk_debugfs_root); /* REVISIT: Cleanup correctly */
+        return err;
+}
+late_initcall(clk_debugfs_init);
+
+#endif /* defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) */
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index bd1cef2c3c14..8d04929a3c75 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -26,6 +26,7 @@
 #include <asm/io.h>
 #include <asm/setup.h>
 
+#include <asm/arch/common.h>
 #include <asm/arch/board.h>
 #include <asm/arch/control.h>
 #include <asm/arch/mux.h>
@@ -241,30 +242,70 @@ arch_initcall(omap_init_clocksource_32k);
 
 /* Global address base setup code */
 
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+
+static struct omap_globals *omap2_globals;
+
+static void __init __omap2_set_globals(void)
+{
+        omap2_set_globals_memory(omap2_globals);
+        omap2_set_globals_control(omap2_globals);
+        omap2_set_globals_prcm(omap2_globals);
+}
+
+#endif
+
 #if defined(CONFIG_ARCH_OMAP2420)
+
+static struct omap_globals omap242x_globals = {
+        .tap    = (__force void __iomem *)OMAP2_IO_ADDRESS(0x48014000),
+        .sdrc   = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_SDRC_BASE),
+        .sms    = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_SMS_BASE),
+        .ctrl   = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_CTRL_BASE),
+        .prm    = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_PRM_BASE),
+        .cm     = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_CM_BASE),
+};
+
 void __init omap2_set_globals_242x(void)
 {
-        omap2_sdrc_base = OMAP2420_SDRC_BASE;
-        omap2_sms_base = OMAP2420_SMS_BASE;
-        omap_ctrl_base_set(OMAP2420_CTRL_BASE);
+        omap2_globals = &omap242x_globals;
+        __omap2_set_globals();
 }
 #endif
 
 #if defined(CONFIG_ARCH_OMAP2430)
+
+static struct omap_globals omap243x_globals = {
+        .tap    = (__force void __iomem *)OMAP2_IO_ADDRESS(0x4900a000),
+        .sdrc   = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP243X_SDRC_BASE),
+        .sms    = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP243X_SMS_BASE),
+        .ctrl   = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP243X_CTRL_BASE),
+        .prm    = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2430_PRM_BASE),
+        .cm     = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2430_CM_BASE),
+};
+
 void __init omap2_set_globals_243x(void)
 {
-        omap2_sdrc_base = OMAP243X_SDRC_BASE;
-        omap2_sms_base = OMAP243X_SMS_BASE;
-        omap_ctrl_base_set(OMAP243X_CTRL_BASE);
+        omap2_globals = &omap243x_globals;
+        __omap2_set_globals();
 }
 #endif
 
 #if defined(CONFIG_ARCH_OMAP3430)
+
+static struct omap_globals omap343x_globals = {
+        .tap    = (__force void __iomem *)OMAP2_IO_ADDRESS(0x4830A000),
+        .sdrc   = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP343X_SDRC_BASE),
+        .sms    = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP343X_SMS_BASE),
+        .ctrl   = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP343X_CTRL_BASE),
+        .prm    = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP3430_PRM_BASE),
+        .cm     = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP3430_CM_BASE),
+};
+
 void __init omap2_set_globals_343x(void)
 {
-        omap2_sdrc_base = OMAP343X_SDRC_BASE;
-        omap2_sms_base = OMAP343X_SMS_BASE;
-        omap_ctrl_base_set(OMAP343X_CTRL_BASE);
+        omap2_globals = &omap343x_globals;
+        __omap2_set_globals();
 }
 #endif
 
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
index 4a53f9ba6c43..81002b722da1 100644
--- a/arch/arm/plat-omap/devices.c
+++ b/arch/arm/plat-omap/devices.c
@@ -24,6 +24,7 @@
 #include <asm/arch/mux.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/menelaus.h>
+#include <asm/arch/mcbsp.h>
 
 #if     defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE)
 
@@ -145,6 +146,53 @@ static inline void omap_init_kp(void) {}
 #endif
 
 /*-------------------------------------------------------------------------*/
+#if defined(CONFIG_OMAP_MCBSP) || defined(CONFIG_OMAP_MCBSP_MODULE)
+
+static struct platform_device **omap_mcbsp_devices;
+
+void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
+                                        int size)
+{
+        int i;
+
+        if (size > OMAP_MAX_MCBSP_COUNT) {
+                printk(KERN_WARNING "Registered too many McBSPs platform_data."
+                        " Using maximum (%d) available.\n",
+                        OMAP_MAX_MCBSP_COUNT);
+                size = OMAP_MAX_MCBSP_COUNT;
+        }
+
+        omap_mcbsp_devices = kzalloc(size * sizeof(struct platform_device *),
+                                     GFP_KERNEL);
+        if (!omap_mcbsp_devices) {
+                printk(KERN_ERR "Could not register McBSP devices\n");
+                return;
+        }
+
+        for (i = 0; i < size; i++) {
+                struct platform_device *new_mcbsp;
+                int ret;
+
+                new_mcbsp = platform_device_alloc("omap-mcbsp", i + 1);
+                if (!new_mcbsp)
+                        continue;
+                new_mcbsp->dev.platform_data = &config[i];
+                ret = platform_device_add(new_mcbsp);
+                if (ret) {
+                        platform_device_put(new_mcbsp);
+                        continue;
+                }
+                omap_mcbsp_devices[i] = new_mcbsp;
+        }
+}
+
+#else
+void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
+                                        int size)
+{  }
+#endif
+
+/*-------------------------------------------------------------------------*/
 
 #if     defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
 
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 39c637b0ffea..fac8e994f588 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -1,7 +1,7 @@
 /*
  * linux/arch/arm/plat-omap/dma.c
  *
- * Copyright (C) 2003 Nokia Corporation
+ * Copyright (C) 2003 - 2008 Nokia Corporation
  * Author: Juha Yrjölä <juha.yrjola@nokia.com>
  * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
  * Graphics DMA and LCD DMA graphics tranformations
@@ -25,11 +25,11 @@
 #include <linux/errno.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <linux/io.h>
 
 #include <asm/system.h>
 #include <asm/hardware.h>
 #include <asm/dma.h>
-#include <asm/io.h>
 
 #include <asm/arch/tc.h>
 
@@ -43,13 +43,13 @@ enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
 enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
 #endif
 
-#define OMAP_DMA_ACTIVE         0x01
-#define OMAP_DMA_CCR_EN         (1 << 7)
+#define OMAP_DMA_ACTIVE                 0x01
+#define OMAP_DMA_CCR_EN                 (1 << 7)
 #define OMAP2_DMA_CSR_CLEAR_MASK        0xffe
 
-#define OMAP_FUNC_MUX_ARM_BASE  (0xfffe1000 + 0xec)
+#define OMAP_FUNC_MUX_ARM_BASE          (0xfffe1000 + 0xec)
 
-static int enable_1510_mode = 0;
+static int enable_1510_mode;
 
 struct omap_dma_lch {
         int next_lch;
@@ -57,7 +57,7 @@ struct omap_dma_lch {
         u16 saved_csr;
         u16 enabled_irqs;
         const char *dev_name;
-        void (* callback)(int lch, u16 ch_status, void *data);
+        void (*callback)(int lch, u16 ch_status, void *data);
         void *data;
 
 #ifndef CONFIG_ARCH_OMAP1
@@ -72,7 +72,6 @@ struct omap_dma_lch {
         long flags;
 };
 
-#ifndef CONFIG_ARCH_OMAP1
 struct dma_link_info {
         int *linked_dmach_q;
         int no_of_lchs_linked;
@@ -86,7 +85,9 @@ struct dma_link_info {
 
 };
 
-static struct dma_link_info dma_linked_lch[OMAP_LOGICAL_DMA_CH_COUNT];
+static struct dma_link_info *dma_linked_lch;
+
+#ifndef CONFIG_ARCH_OMAP1
 
 /* Chain handling macros */
 #define OMAP_DMA_CHAIN_QINIT(chain_id)                                  \
@@ -119,12 +120,15 @@ static struct dma_link_info dma_linked_lch[OMAP_LOGICAL_DMA_CH_COUNT];
                 dma_linked_lch[chain_id].q_count++; \
         } while (0)
 #endif
+
+static int dma_lch_count;
 static int dma_chan_count;
 
 static spinlock_t dma_chan_lock;
-static struct omap_dma_lch dma_chan[OMAP_LOGICAL_DMA_CH_COUNT];
+static struct omap_dma_lch *dma_chan;
+static void __iomem *omap_dma_base;
 
-static const u8 omap1_dma_irq[OMAP_LOGICAL_DMA_CH_COUNT] = {
+static const u8 omap1_dma_irq[OMAP1_LOGICAL_DMA_CH_COUNT] = {
         INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
         INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
         INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
@@ -139,6 +143,24 @@ static inline void omap_enable_channel_irq(int lch);
 #define REVISIT_24XX()          printk(KERN_ERR "FIXME: no %s on 24xx\n", \
                                                 __func__);
 
+#define dma_read(reg)                                                   \
+({                                                                      \
+        u32 __val;                                                      \
+        if (cpu_class_is_omap1())                                       \
+                __val = __raw_readw(omap_dma_base + OMAP1_DMA_##reg);   \
+        else                                                            \
+                __val = __raw_readl(omap_dma_base + OMAP_DMA4_##reg);   \
+        __val;                                                          \
+})
+
+#define dma_write(val, reg)                                             \
+({                                                                      \
+        if (cpu_class_is_omap1())                                       \
+                __raw_writew((u16)(val), omap_dma_base + OMAP1_DMA_##reg); \
+        else                                                            \
+                __raw_writel((val), omap_dma_base + OMAP_DMA4_##reg);   \
+})
+
 #ifdef CONFIG_ARCH_OMAP15XX
 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
 int omap_dma_in_1510_mode(void)
@@ -173,13 +195,14 @@ static inline void set_gdma_dev(int req, int dev)
 #define set_gdma_dev(req, dev)  do {} while (0)
 #endif
 
+/* Omap1 only */
 static void clear_lch_regs(int lch)
 {
         int i;
-        u32 lch_base = OMAP_DMA_BASE + lch * 0x40;
+        void __iomem *lch_base = omap_dma_base + OMAP1_DMA_CH_BASE(lch);
 
         for (i = 0; i < 0x2c; i += 2)
-                omap_writew(0, lch_base + i);
+                __raw_writew(0, lch_base + i);
 }
 
 void omap_set_dma_priority(int lch, int dst_port, int priority)
@@ -212,33 +235,49 @@ void omap_set_dma_priority(int lch, int dst_port, int priority)
         }
 
         if (cpu_class_is_omap2()) {
+                u32 ccr;
+
+                ccr = dma_read(CCR(lch));
                 if (priority)
-                        OMAP_DMA_CCR_REG(lch) |= (1 << 6);
+                        ccr |= (1 << 6);
                 else
-                        OMAP_DMA_CCR_REG(lch) &= ~(1 << 6);
+                        ccr &= ~(1 << 6);
+                dma_write(ccr, CCR(lch));
         }
 }
+EXPORT_SYMBOL(omap_set_dma_priority);
 
 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
                                   int frame_count, int sync_mode,
                                   int dma_trigger, int src_or_dst_synch)
 {
-        OMAP_DMA_CSDP_REG(lch) &= ~0x03;
-        OMAP_DMA_CSDP_REG(lch) |= data_type;
+        u32 l;
+
+        l = dma_read(CSDP(lch));
+        l &= ~0x03;
+        l |= data_type;
+        dma_write(l, CSDP(lch));
 
         if (cpu_class_is_omap1()) {
-                OMAP_DMA_CCR_REG(lch) &= ~(1 << 5);
+                u16 ccr;
+
+                ccr = dma_read(CCR(lch));
+                ccr &= ~(1 << 5);
                 if (sync_mode == OMAP_DMA_SYNC_FRAME)
-                        OMAP_DMA_CCR_REG(lch) |= 1 << 5;
+                        ccr |= 1 << 5;
+                dma_write(ccr, CCR(lch));
 
-                OMAP1_DMA_CCR2_REG(lch) &= ~(1 << 2);
+                ccr = dma_read(CCR2(lch));
+                ccr &= ~(1 << 2);
                 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
-                        OMAP1_DMA_CCR2_REG(lch) |= 1 << 2;
+                        ccr |= 1 << 2;
+                dma_write(ccr, CCR2(lch));
         }
 
         if (cpu_class_is_omap2() && dma_trigger) {
-                u32 val = OMAP_DMA_CCR_REG(lch);
+                u32 val;
 
+                val = dma_read(CCR(lch));
                 val &= ~(3 << 19);
                 if (dma_trigger > 63)
                         val |= 1 << 20;
@@ -263,12 +302,13 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
                 else
                         val &= ~(1 << 24);      /* dest synch */
 
-                OMAP_DMA_CCR_REG(lch) = val;
+                dma_write(val, CCR(lch));
         }
 
-        OMAP_DMA_CEN_REG(lch) = elem_count;
-        OMAP_DMA_CFN_REG(lch) = frame_count;
+        dma_write(elem_count, CEN(lch));
+        dma_write(frame_count, CFN(lch));
 }
+EXPORT_SYMBOL(omap_set_dma_transfer_params);
 
 void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
 {
@@ -281,7 +321,9 @@ void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
                 return;
         }
 
-        w = OMAP1_DMA_CCR2_REG(lch) & ~0x03;
+        w = dma_read(CCR2(lch));
+        w &= ~0x03;
+
         switch (mode) {
         case OMAP_DMA_CONSTANT_FILL:
                 w |= 0x01;
@@ -294,52 +336,81 @@ void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
         default:
                 BUG();
         }
-        OMAP1_DMA_CCR2_REG(lch) = w;
+        dma_write(w, CCR2(lch));
 
-        w = OMAP1_DMA_LCH_CTRL_REG(lch) & ~0x0f;
+        w = dma_read(LCH_CTRL(lch));
+        w &= ~0x0f;
         /* Default is channel type 2D */
         if (mode) {
-                OMAP1_DMA_COLOR_L_REG(lch) = (u16)color;
-                OMAP1_DMA_COLOR_U_REG(lch) = (u16)(color >> 16);
+                dma_write((u16)color, COLOR_L(lch));
+                dma_write((u16)(color >> 16), COLOR_U(lch));
                 w |= 1;         /* Channel type G */
         }
-        OMAP1_DMA_LCH_CTRL_REG(lch) = w;
+        dma_write(w, LCH_CTRL(lch));
 }
+EXPORT_SYMBOL(omap_set_dma_color_mode);
 
 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
 {
         if (cpu_class_is_omap2()) {
-                OMAP_DMA_CSDP_REG(lch) &= ~(0x3 << 16);
-                OMAP_DMA_CSDP_REG(lch) |= (mode << 16);
+                u32 csdp;
+
+                csdp = dma_read(CSDP(lch));
+                csdp &= ~(0x3 << 16);
+                csdp |= (mode << 16);
+                dma_write(csdp, CSDP(lch));
+        }
+}
+EXPORT_SYMBOL(omap_set_dma_write_mode);
+
+void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
+{
+        if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
+                u32 l;
+
+                l = dma_read(LCH_CTRL(lch));
+                l &= ~0x7;
+                l |= mode;
+                dma_write(l, LCH_CTRL(lch));
         }
 }
+EXPORT_SYMBOL(omap_set_dma_channel_mode);
 
 /* Note that src_port is only for omap1 */
 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
                              unsigned long src_start,
                              int src_ei, int src_fi)
 {
+        u32 l;
+
         if (cpu_class_is_omap1()) {
-                OMAP_DMA_CSDP_REG(lch) &= ~(0x1f << 2);
-                OMAP_DMA_CSDP_REG(lch) |= src_port << 2;
+                u16 w;
+
+                w = dma_read(CSDP(lch));
+                w &= ~(0x1f << 2);
+                w |= src_port << 2;
+                dma_write(w, CSDP(lch));
         }
 
-        OMAP_DMA_CCR_REG(lch) &= ~(0x03 << 12);
-        OMAP_DMA_CCR_REG(lch) |= src_amode << 12;
+        l = dma_read(CCR(lch));
+        l &= ~(0x03 << 12);
+        l |= src_amode << 12;
+        dma_write(l, CCR(lch));
 
         if (cpu_class_is_omap1()) {
-                OMAP1_DMA_CSSA_U_REG(lch) = src_start >> 16;
-                OMAP1_DMA_CSSA_L_REG(lch) = src_start;
+                dma_write(src_start >> 16, CSSA_U(lch));
+                dma_write((u16)src_start, CSSA_L(lch));
         }
 
         if (cpu_class_is_omap2())
-                OMAP2_DMA_CSSA_REG(lch) = src_start;
+                dma_write(src_start, CSSA(lch));
 
-        OMAP_DMA_CSEI_REG(lch) = src_ei;
-        OMAP_DMA_CSFI_REG(lch) = src_fi;
+        dma_write(src_ei, CSEI(lch));
+        dma_write(src_fi, CSFI(lch));
 }
+EXPORT_SYMBOL(omap_set_dma_src_params);
 
-void omap_set_dma_params(int lch, struct omap_dma_channel_params * params)
+void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
 {
         omap_set_dma_transfer_params(lch, params->data_type,
                                      params->elem_count, params->frame_count,
@@ -356,28 +427,37 @@ void omap_set_dma_params(int lch, struct omap_dma_channel_params * params)
                 omap_dma_set_prio_lch(lch, params->read_prio,
                                       params->write_prio);
 }
+EXPORT_SYMBOL(omap_set_dma_params);
 
 void omap_set_dma_src_index(int lch, int eidx, int fidx)
 {
-        if (cpu_class_is_omap2()) {
-                REVISIT_24XX();
+        if (cpu_class_is_omap2())
                 return;
-        }
-        OMAP_DMA_CSEI_REG(lch) = eidx;
-        OMAP_DMA_CSFI_REG(lch) = fidx;
+
+        dma_write(eidx, CSEI(lch));
+        dma_write(fidx, CSFI(lch));
 }
+EXPORT_SYMBOL(omap_set_dma_src_index);
 
 void omap_set_dma_src_data_pack(int lch, int enable)
 {
-        OMAP_DMA_CSDP_REG(lch) &= ~(1 << 6);
+        u32 l;
+
+        l = dma_read(CSDP(lch));
+        l &= ~(1 << 6);
         if (enable)
-                OMAP_DMA_CSDP_REG(lch) |= (1 << 6);
+                l |= (1 << 6);
+        dma_write(l, CSDP(lch));
 }
+EXPORT_SYMBOL(omap_set_dma_src_data_pack);
 
 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
 {
         unsigned int burst = 0;
-        OMAP_DMA_CSDP_REG(lch) &= ~(0x03 << 7);
+        u32 l;
+
+        l = dma_read(CSDP(lch));
+        l &= ~(0x03 << 7);
 
         switch (burst_mode) {
         case OMAP_DMA_DATA_BURST_DIS:
@@ -408,55 +488,73 @@ void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
         default:
                 BUG();
         }
-        OMAP_DMA_CSDP_REG(lch) |= (burst << 7);
+
+        l |= (burst << 7);
+        dma_write(l, CSDP(lch));
 }
+EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
 
 /* Note that dest_port is only for OMAP1 */
 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
                               unsigned long dest_start,
                               int dst_ei, int dst_fi)
 {
+        u32 l;
+
         if (cpu_class_is_omap1()) {
-                OMAP_DMA_CSDP_REG(lch) &= ~(0x1f << 9);
-                OMAP_DMA_CSDP_REG(lch) |= dest_port << 9;
+                l = dma_read(CSDP(lch));
+                l &= ~(0x1f << 9);
+                l |= dest_port << 9;
+                dma_write(l, CSDP(lch));
         }
 
-        OMAP_DMA_CCR_REG(lch) &= ~(0x03 << 14);
-        OMAP_DMA_CCR_REG(lch) |= dest_amode << 14;
+        l = dma_read(CCR(lch));
+        l &= ~(0x03 << 14);
+        l |= dest_amode << 14;
+        dma_write(l, CCR(lch));
 
         if (cpu_class_is_omap1()) {
-                OMAP1_DMA_CDSA_U_REG(lch) = dest_start >> 16;
-                OMAP1_DMA_CDSA_L_REG(lch) = dest_start;
+                dma_write(dest_start >> 16, CDSA_U(lch));
+                dma_write(dest_start, CDSA_L(lch));
         }
 
         if (cpu_class_is_omap2())
-                OMAP2_DMA_CDSA_REG(lch) = dest_start;
+                dma_write(dest_start, CDSA(lch));
 
-        OMAP_DMA_CDEI_REG(lch) = dst_ei;
-        OMAP_DMA_CDFI_REG(lch) = dst_fi;
+        dma_write(dst_ei, CDEI(lch));
+        dma_write(dst_fi, CDFI(lch));
 }
+EXPORT_SYMBOL(omap_set_dma_dest_params);
 
 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
 {
-        if (cpu_class_is_omap2()) {
-                REVISIT_24XX();
+        if (cpu_class_is_omap2())
                 return;
-        }
-        OMAP_DMA_CDEI_REG(lch) = eidx;
-        OMAP_DMA_CDFI_REG(lch) = fidx;
+
+        dma_write(eidx, CDEI(lch));
+        dma_write(fidx, CDFI(lch));
 }
+EXPORT_SYMBOL(omap_set_dma_dest_index);
 
 void omap_set_dma_dest_data_pack(int lch, int enable)
 {
-        OMAP_DMA_CSDP_REG(lch) &= ~(1 << 13);
+        u32 l;
+
+        l = dma_read(CSDP(lch));
+        l &= ~(1 << 13);
         if (enable)
-                OMAP_DMA_CSDP_REG(lch) |= 1 << 13;
+                l |= 1 << 13;
+        dma_write(l, CSDP(lch));
 }
+EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
 
 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
 {
         unsigned int burst = 0;
-        OMAP_DMA_CSDP_REG(lch) &= ~(0x03 << 14);
+        u32 l;
+
+        l = dma_read(CSDP(lch));
+        l &= ~(0x03 << 14);
 
         switch (burst_mode) {
         case OMAP_DMA_DATA_BURST_DIS:
@@ -486,8 +584,10 @@ void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
                 BUG();
                 return;
         }
-        OMAP_DMA_CSDP_REG(lch) |= (burst << 14);
+        l |= (burst << 14);
+        dma_write(l, CSDP(lch));
 }
+EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
 
 static inline void omap_enable_channel_irq(int lch)
 {
@@ -495,62 +595,74 @@ static inline void omap_enable_channel_irq(int lch)
 
         /* Clear CSR */
         if (cpu_class_is_omap1())
-                status = OMAP_DMA_CSR_REG(lch);
+                status = dma_read(CSR(lch));
         else if (cpu_class_is_omap2())
-                OMAP_DMA_CSR_REG(lch) = OMAP2_DMA_CSR_CLEAR_MASK;
+                dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
 
         /* Enable some nice interrupts. */
-        OMAP_DMA_CICR_REG(lch) = dma_chan[lch].enabled_irqs;
+        dma_write(dma_chan[lch].enabled_irqs, CICR(lch));
 }
 
 static void omap_disable_channel_irq(int lch)
 {
         if (cpu_class_is_omap2())
-                OMAP_DMA_CICR_REG(lch) = 0;
+                dma_write(0, CICR(lch));
 }
 
 void omap_enable_dma_irq(int lch, u16 bits)
 {
         dma_chan[lch].enabled_irqs |= bits;
 }
+EXPORT_SYMBOL(omap_enable_dma_irq);
 
 void omap_disable_dma_irq(int lch, u16 bits)
 {
         dma_chan[lch].enabled_irqs &= ~bits;
 }
+EXPORT_SYMBOL(omap_disable_dma_irq);
 
 static inline void enable_lnk(int lch)
 {
+        u32 l;
+
+        l = dma_read(CLNK_CTRL(lch));
+
         if (cpu_class_is_omap1())
-                OMAP_DMA_CLNK_CTRL_REG(lch) &= ~(1 << 14);
+                l &= ~(1 << 14);
 
         /* Set the ENABLE_LNK bits */
         if (dma_chan[lch].next_lch != -1)
-                OMAP_DMA_CLNK_CTRL_REG(lch) =
-                        dma_chan[lch].next_lch | (1 << 15);
+                l = dma_chan[lch].next_lch | (1 << 15);
 
 #ifndef CONFIG_ARCH_OMAP1
-        if (dma_chan[lch].next_linked_ch != -1)
-                OMAP_DMA_CLNK_CTRL_REG(lch) =
-                        dma_chan[lch].next_linked_ch | (1 << 15);
+        if (cpu_class_is_omap2())
+                if (dma_chan[lch].next_linked_ch != -1)
+                        l = dma_chan[lch].next_linked_ch | (1 << 15);
 #endif
+
+        dma_write(l, CLNK_CTRL(lch));
 }
 
 static inline void disable_lnk(int lch)
 {
+        u32 l;
+
+        l = dma_read(CLNK_CTRL(lch));
+
         /* Disable interrupts */
         if (cpu_class_is_omap1()) {
-                OMAP_DMA_CICR_REG(lch) = 0;
+                dma_write(0, CICR(lch));
                 /* Set the STOP_LNK bit */
-                OMAP_DMA_CLNK_CTRL_REG(lch) |= 1 << 14;
+                l |= 1 << 14;
         }
 
         if (cpu_class_is_omap2()) {
                 omap_disable_channel_irq(lch);
                 /* Clear the ENABLE_LNK bit */
-                OMAP_DMA_CLNK_CTRL_REG(lch) &= ~(1 << 15);
+                l &= ~(1 << 15);
         }
 
+        dma_write(l, CLNK_CTRL(lch));
         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
 }
 
@@ -561,13 +673,13 @@ static inline void omap2_enable_irq_lch(int lch)
         if (!cpu_class_is_omap2())
                 return;
 
-        val = omap_readl(OMAP_DMA4_IRQENABLE_L0);
+        val = dma_read(IRQENABLE_L0);
         val |= 1 << lch;
-        omap_writel(val, OMAP_DMA4_IRQENABLE_L0);
+        dma_write(val, IRQENABLE_L0);
 }
 
 int omap_request_dma(int dev_id, const char *dev_name,
-                     void (* callback)(int lch, u16 ch_status, void *data),
+                     void (*callback)(int lch, u16 ch_status, void *data),
                      void *data, int *dma_ch_out)
 {
         int ch, free_ch = -1;
@@ -600,10 +712,14 @@ int omap_request_dma(int dev_id, const char *dev_name,
         chan->dev_name = dev_name;
         chan->callback = callback;
         chan->data = data;
+
 #ifndef CONFIG_ARCH_OMAP1
-        chan->chain_id = -1;
-        chan->next_linked_ch = -1;
+        if (cpu_class_is_omap2()) {
+                chan->chain_id = -1;
+                chan->next_linked_ch = -1;
+        }
 #endif
+
         chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
 
         if (cpu_class_is_omap1())
@@ -618,26 +734,28 @@ int omap_request_dma(int dev_id, const char *dev_name,
                         set_gdma_dev(free_ch + 1, dev_id);
                         dev_id = free_ch + 1;
                 }
-                /* Disable the 1510 compatibility mode and set the sync device
-                 * id. */
-                OMAP_DMA_CCR_REG(free_ch) = dev_id | (1 << 10);
+                /*
+                 * Disable the 1510 compatibility mode and set the sync device
+                 * id.
+                 */
+                dma_write(dev_id | (1 << 10), CCR(free_ch));
         } else if (cpu_is_omap730() || cpu_is_omap15xx()) {
-                OMAP_DMA_CCR_REG(free_ch) = dev_id;
+                dma_write(dev_id, CCR(free_ch));
         }
 
         if (cpu_class_is_omap2()) {
                 omap2_enable_irq_lch(free_ch);
-
                 omap_enable_channel_irq(free_ch);
                 /* Clear the CSR register and IRQ status register */
-                OMAP_DMA_CSR_REG(free_ch) = OMAP2_DMA_CSR_CLEAR_MASK;
-                omap_writel(1 << free_ch, OMAP_DMA4_IRQSTATUS_L0);
+                dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(free_ch));
+                dma_write(1 << free_ch, IRQSTATUS_L0);
         }
 
         *dma_ch_out = free_ch;
 
         return 0;
 }
+EXPORT_SYMBOL(omap_request_dma);
 
 void omap_free_dma(int lch)
 {
@@ -645,11 +763,12 @@ void omap_free_dma(int lch)
 
         spin_lock_irqsave(&dma_chan_lock, flags);
         if (dma_chan[lch].dev_id == -1) {
-                printk("omap_dma: trying to free nonallocated DMA channel %d\n",
+                pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
                        lch);
                 spin_unlock_irqrestore(&dma_chan_lock, flags);
                 return;
         }
+
         dma_chan[lch].dev_id = -1;
         dma_chan[lch].next_lch = -1;
         dma_chan[lch].callback = NULL;
@@ -657,30 +776,31 @@ void omap_free_dma(int lch)
 
         if (cpu_class_is_omap1()) {
                 /* Disable all DMA interrupts for the channel. */
-                OMAP_DMA_CICR_REG(lch) = 0;
+                dma_write(0, CICR(lch));
                 /* Make sure the DMA transfer is stopped. */
-                OMAP_DMA_CCR_REG(lch) = 0;
+                dma_write(0, CCR(lch));
         }
 
         if (cpu_class_is_omap2()) {
                 u32 val;
                 /* Disable interrupts */
-                val = omap_readl(OMAP_DMA4_IRQENABLE_L0);
+                val = dma_read(IRQENABLE_L0);
                 val &= ~(1 << lch);
-                omap_writel(val, OMAP_DMA4_IRQENABLE_L0);
+                dma_write(val, IRQENABLE_L0);
 
                 /* Clear the CSR register and IRQ status register */
-                OMAP_DMA_CSR_REG(lch) = OMAP2_DMA_CSR_CLEAR_MASK;
-                omap_writel(1 << lch, OMAP_DMA4_IRQSTATUS_L0);
+                dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
+                dma_write(1 << lch, IRQSTATUS_L0);
 
                 /* Disable all DMA interrupts for the channel. */
-                OMAP_DMA_CICR_REG(lch) = 0;
+                dma_write(0, CICR(lch));
 
                 /* Make sure the DMA transfer is stopped. */
-                OMAP_DMA_CCR_REG(lch) = 0;
+                dma_write(0, CCR(lch));
                 omap_clear_dma(lch);
         }
 }
+EXPORT_SYMBOL(omap_free_dma);
 
 /**
  * @brief omap_dma_set_global_params : Set global priority settings for dma
@@ -708,7 +828,7 @@ omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
         reg = (arb_rate & 0xff) << 16;
         reg |= (0xff & max_fifo_depth);
 
-        omap_writel(reg, OMAP_DMA4_GCR_REG);
+        dma_write(reg, GCR);
 }
 EXPORT_SYMBOL(omap_dma_set_global_params);
 
@@ -725,20 +845,21 @@ int
 omap_dma_set_prio_lch(int lch, unsigned char read_prio,
                       unsigned char write_prio)
 {
-        u32 w;
+        u32 l;
 
-        if (unlikely((lch < 0 || lch >= OMAP_LOGICAL_DMA_CH_COUNT))) {
+        if (unlikely((lch < 0 || lch >= dma_lch_count))) {
                 printk(KERN_ERR "Invalid channel id\n");
                 return -EINVAL;
         }
-        w = OMAP_DMA_CCR_REG(lch);
-        w &= ~((1 << 6) | (1 << 26));
+        l = dma_read(CCR(lch));
+        l &= ~((1 << 6) | (1 << 26));
         if (cpu_is_omap2430() || cpu_is_omap34xx())
-                w |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
+                l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
         else
-                w |= ((read_prio & 0x1) << 6);
+                l |= ((read_prio & 0x1) << 6);
+
+        dma_write(l, CCR(lch));
 
-        OMAP_DMA_CCR_REG(lch) = w;
         return 0;
 }
 EXPORT_SYMBOL(omap_dma_set_prio_lch);
@@ -754,28 +875,34 @@ void omap_clear_dma(int lch)
         local_irq_save(flags);
 
         if (cpu_class_is_omap1()) {
-                int status;
-                OMAP_DMA_CCR_REG(lch) &= ~OMAP_DMA_CCR_EN;
+                u32 l;
+
+                l = dma_read(CCR(lch));
+                l &= ~OMAP_DMA_CCR_EN;
+                dma_write(l, CCR(lch));
 
                 /* Clear pending interrupts */
-                status = OMAP_DMA_CSR_REG(lch);
+                l = dma_read(CSR(lch));
         }
 
         if (cpu_class_is_omap2()) {
                 int i;
-                u32 lch_base = OMAP_DMA4_BASE + lch * 0x60 + 0x80;
+                void __iomem *lch_base = omap_dma_base + OMAP_DMA4_CH_BASE(lch);
                 for (i = 0; i < 0x44; i += 4)
-                        omap_writel(0, lch_base + i);
+                        __raw_writel(0, lch_base + i);
         }
 
         local_irq_restore(flags);
 }
+EXPORT_SYMBOL(omap_clear_dma);
 
 void omap_start_dma(int lch)
 {
+        u32 l;
+
         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
                 int next_lch, cur_lch;
-                char dma_chan_link_map[OMAP_LOGICAL_DMA_CH_COUNT];
+                char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
 
                 dma_chan_link_map[lch] = 1;
                 /* Set the link register of the first channel */
@@ -799,27 +926,34 @@ void omap_start_dma(int lch)
                 } while (next_lch != -1);
         } else if (cpu_class_is_omap2()) {
                 /* Errata: Need to write lch even if not using chaining */
-                OMAP_DMA_CLNK_CTRL_REG(lch) = lch;
+                dma_write(lch, CLNK_CTRL(lch));
         }
 
         omap_enable_channel_irq(lch);
 
-        /* Errata: On ES2.0 BUFFERING disable must be set.
-         * This will always fail on ES1.0 */
-        if (cpu_is_omap24xx()) {
-                OMAP_DMA_CCR_REG(lch) |= OMAP_DMA_CCR_EN;
-        }
+        l = dma_read(CCR(lch));
+
+        /*
+         * Errata: On ES2.0 BUFFERING disable must be set.
+         * This will always fail on ES1.0
+         */
+        if (cpu_is_omap24xx())
+                l |= OMAP_DMA_CCR_EN;
 
-        OMAP_DMA_CCR_REG(lch) |= OMAP_DMA_CCR_EN;
+        l |= OMAP_DMA_CCR_EN;
+        dma_write(l, CCR(lch));
 
         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
 }
+EXPORT_SYMBOL(omap_start_dma);
 
 void omap_stop_dma(int lch)
 {
+        u32 l;
+
         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
                 int next_lch, cur_lch = lch;
-                char dma_chan_link_map[OMAP_LOGICAL_DMA_CH_COUNT];
+                char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
 
                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
                 do {
@@ -840,18 +974,22 @@ void omap_stop_dma(int lch)
 
         /* Disable all interrupts on the channel */
         if (cpu_class_is_omap1())
-                OMAP_DMA_CICR_REG(lch) = 0;
+                dma_write(0, CICR(lch));
+
+        l = dma_read(CCR(lch));
+        l &= ~OMAP_DMA_CCR_EN;
+        dma_write(l, CCR(lch));
 
-        OMAP_DMA_CCR_REG(lch) &= ~OMAP_DMA_CCR_EN;
         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
 }
+EXPORT_SYMBOL(omap_stop_dma);
 
 /*
  * Allows changing the DMA callback function or data. This may be needed if
  * the driver shares a single DMA channel for multiple dma triggers.
  */
 int omap_set_dma_callback(int lch,
-                          void (* callback)(int lch, u16 ch_status, void *data),
+                          void (*callback)(int lch, u16 ch_status, void *data),
                           void *data)
 {
         unsigned long flags;
@@ -871,6 +1009,7 @@ int omap_set_dma_callback(int lch,
 
         return 0;
 }
+EXPORT_SYMBOL(omap_set_dma_callback);
 
 /*
  * Returns current physical source address for the given DMA channel.
@@ -884,15 +1023,24 @@ dma_addr_t omap_get_dma_src_pos(int lch)
 {
         dma_addr_t offset = 0;
 
-        if (cpu_class_is_omap1())
-                offset = (dma_addr_t) (OMAP1_DMA_CSSA_L_REG(lch) |
-                                       (OMAP1_DMA_CSSA_U_REG(lch) << 16));
+        if (cpu_is_omap15xx())
+                offset = dma_read(CPC(lch));
+        else
+                offset = dma_read(CSAC(lch));
 
-        if (cpu_class_is_omap2())
-                offset = OMAP_DMA_CSAC_REG(lch);
+        /*
+         * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
+         * read before the DMA controller finished disabling the channel.
+         */
+        if (!cpu_is_omap15xx() && offset == 0)
+                offset = dma_read(CSAC(lch));
+
+        if (cpu_class_is_omap1())
+                offset |= (dma_read(CSSA_U(lch)) << 16);
 
         return offset;
 }
+EXPORT_SYMBOL(omap_get_dma_src_pos);
 
 /*
  * Returns current physical destination address for the given DMA channel.
@@ -906,25 +1054,30 @@ dma_addr_t omap_get_dma_dst_pos(int lch)
 {
         dma_addr_t offset = 0;
 
-        if (cpu_class_is_omap1())
-                offset = (dma_addr_t) (OMAP1_DMA_CDSA_L_REG(lch) |
-                                       (OMAP1_DMA_CDSA_U_REG(lch) << 16));
+        if (cpu_is_omap15xx())
+                offset = dma_read(CPC(lch));
+        else
+                offset = dma_read(CDAC(lch));
 
-        if (cpu_class_is_omap2())
-                offset = OMAP_DMA_CDAC_REG(lch);
+        /*
+         * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
+         * read before the DMA controller finished disabling the channel.
+         */
+        if (!cpu_is_omap15xx() && offset == 0)
+                offset = dma_read(CDAC(lch));
+
+        if (cpu_class_is_omap1())
+                offset |= (dma_read(CDSA_U(lch)) << 16);
 
         return offset;
 }
+EXPORT_SYMBOL(omap_get_dma_dst_pos);
 
-/*
- * Returns current source transfer counting for the given DMA channel.
- * Can be used to monitor the progress of a transfer inside a block.
- * It must be called with disabled interrupts.
- */
-int omap_get_dma_src_addr_counter(int lch)
+int omap_get_dma_active_status(int lch)
 {
-        return (dma_addr_t) OMAP_DMA_CSAC_REG(lch);
+        return (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN) != 0;
 }
+EXPORT_SYMBOL(omap_get_dma_active_status);
 
 int omap_dma_running(void)
 {
@@ -936,7 +1089,7 @@ int omap_dma_running(void)
                         return 1;
 
         for (lch = 0; lch < dma_chan_count; lch++)
-                if (OMAP_DMA_CCR_REG(lch) & OMAP_DMA_CCR_EN)
+                if (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN)
                         return 1;
 
         return 0;
@@ -947,7 +1100,7 @@ int omap_dma_running(void)
  * For this DMA link to start, you still need to start (see omap_start_dma)
  * the first one. That will fire up the entire queue.
  */
-void omap_dma_link_lch (int lch_head, int lch_queue)
+void omap_dma_link_lch(int lch_head, int lch_queue)
 {
         if (omap_dma_in_1510_mode()) {
                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
@@ -964,11 +1117,12 @@ void omap_dma_link_lch (int lch_head, int lch_queue)
 
         dma_chan[lch_head].next_lch = lch_queue;
 }
+EXPORT_SYMBOL(omap_dma_link_lch);
 
 /*
  * Once the DMA queue is stopped, we can destroy it.
  */
-void omap_dma_unlink_lch (int lch_head, int lch_queue)
+void omap_dma_unlink_lch(int lch_head, int lch_queue)
 {
         if (omap_dma_in_1510_mode()) {
                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
@@ -983,7 +1137,6 @@ void omap_dma_unlink_lch (int lch_head, int lch_queue)
                 dump_stack();
         }
 
-
         if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
             (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) {
                 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
@@ -993,12 +1146,15 @@ void omap_dma_unlink_lch (int lch_head, int lch_queue)
 
         dma_chan[lch_head].next_lch = -1;
 }
+EXPORT_SYMBOL(omap_dma_unlink_lch);
+
+/*----------------------------------------------------------------------------*/
 
 #ifndef CONFIG_ARCH_OMAP1
 /* Create chain of DMA channesls */
 static void create_dma_lch_chain(int lch_head, int lch_queue)
 {
-        u32 w;
+        u32 l;
 
         /* Check if this is the first link in chain */
         if (dma_chan[lch_head].next_linked_ch == -1) {
@@ -1018,15 +1174,15 @@ static void create_dma_lch_chain(int lch_head, int lch_queue)
                                         lch_queue;
         }
 
-        w = OMAP_DMA_CLNK_CTRL_REG(lch_head);
-        w &= ~(0x1f);
-        w |= lch_queue;
-        OMAP_DMA_CLNK_CTRL_REG(lch_head) = w;
+        l = dma_read(CLNK_CTRL(lch_head));
+        l &= ~(0x1f);
+        l |= lch_queue;
+        dma_write(l, CLNK_CTRL(lch_head));
 
-        w = OMAP_DMA_CLNK_CTRL_REG(lch_queue);
-        w &= ~(0x1f);
-        w |= (dma_chan[lch_queue].next_linked_ch);
-        OMAP_DMA_CLNK_CTRL_REG(lch_queue) = w;
+        l = dma_read(CLNK_CTRL(lch_queue));
+        l &= ~(0x1f);
+        l |= (dma_chan[lch_queue].next_linked_ch);
+        dma_write(l, CLNK_CTRL(lch_queue));
 }
 
 /**
@@ -1061,7 +1217,7 @@ int omap_request_dma_chain(int dev_id, const char *dev_name,
         }
 
         if (unlikely((no_of_chans < 1
-                        || no_of_chans > OMAP_LOGICAL_DMA_CH_COUNT))) {
+                        || no_of_chans > dma_lch_count))) {
                 printk(KERN_ERR "Invalid Number of channels requested\n");
                 return -EINVAL;
         }
@@ -1116,6 +1272,7 @@ int omap_request_dma_chain(int dev_id, const char *dev_name,
                 for (i = 0; i < (no_of_chans - 1); i++)
                         create_dma_lch_chain(channels[i], channels[i + 1]);
         }
+
         return 0;
 }
 EXPORT_SYMBOL(omap_request_dma_chain);
@@ -1138,7 +1295,7 @@ int omap_modify_dma_chain_params(int chain_id,
 
         /* Check for input params */
         if (unlikely((chain_id < 0
-                        || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
+                        || chain_id >= dma_lch_count))) {
                 printk(KERN_ERR "Invalid chain id\n");
                 return -EINVAL;
         }
@@ -1158,6 +1315,7 @@ int omap_modify_dma_chain_params(int chain_id,
                  */
                 omap_set_dma_params(channels[i], &params);
         }
+
         return 0;
 }
 EXPORT_SYMBOL(omap_modify_dma_chain_params);
@@ -1176,7 +1334,7 @@ int omap_free_dma_chain(int chain_id)
         u32 i;
 
         /* Check for input params */
-        if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
+        if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
                 printk(KERN_ERR "Invalid chain id\n");
                 return -EINVAL;
         }
@@ -1201,6 +1359,7 @@ int omap_free_dma_chain(int chain_id)
         dma_linked_lch[chain_id].linked_dmach_q = NULL;
         dma_linked_lch[chain_id].chain_mode = -1;
         dma_linked_lch[chain_id].chain_state = -1;
+
         return (0);
 }
 EXPORT_SYMBOL(omap_free_dma_chain);
@@ -1216,7 +1375,7 @@ EXPORT_SYMBOL(omap_free_dma_chain);
 int omap_dma_chain_status(int chain_id)
 {
         /* Check for input params */
-        if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
+        if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
                 printk(KERN_ERR "Invalid chain id\n");
                 return -EINVAL;
         }
@@ -1231,6 +1390,7 @@ int omap_dma_chain_status(int chain_id)
 
         if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
                 return OMAP_DMA_CHAIN_INACTIVE;
+
         return OMAP_DMA_CHAIN_ACTIVE;
 }
 EXPORT_SYMBOL(omap_dma_chain_status);
@@ -1253,11 +1413,13 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
                         int elem_count, int frame_count, void *callbk_data)
 {
         int *channels;
-        u32 w, lch;
+        u32 l, lch;
         int start_dma = 0;
 
-        /* if buffer size is less than 1 then there is
-         * no use of starting the chain */
+        /*
+         * if buffer size is less than 1 then there is
+         * no use of starting the chain
+         */
         if (elem_count < 1) {
                 printk(KERN_ERR "Invalid buffer size\n");
                 return -EINVAL;
@@ -1265,7 +1427,7 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
 
         /* Check for input params */
         if (unlikely((chain_id < 0
-                        || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
+                        || chain_id >= dma_lch_count))) {
                 printk(KERN_ERR "Invalid chain id\n");
                 return -EINVAL;
         }
@@ -1294,20 +1456,24 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
 
         /* Set the params to the free channel */
         if (src_start != 0)
-                OMAP2_DMA_CSSA_REG(lch) = src_start;
+                dma_write(src_start, CSSA(lch));
         if (dest_start != 0)
-                OMAP2_DMA_CDSA_REG(lch) = dest_start;
+                dma_write(dest_start, CDSA(lch));
 
         /* Write the buffer size */
-        OMAP_DMA_CEN_REG(lch) = elem_count;
-        OMAP_DMA_CFN_REG(lch) = frame_count;
+        dma_write(elem_count, CEN(lch));
+        dma_write(frame_count, CFN(lch));
 
-        /* If the chain is dynamically linked,
-         * then we may have to start the chain if its not active */
+        /*
+         * If the chain is dynamically linked,
+         * then we may have to start the chain if its not active
+         */
         if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
 
-                /* In Dynamic chain, if the chain is not started,
-                 * queue the channel */
+                /*
+                 * In Dynamic chain, if the chain is not started,
+                 * queue the channel
+                 */
                 if (dma_linked_lch[chain_id].chain_state ==
                                                 DMA_CHAIN_NOTSTARTED) {
                         /* Enable the link in previous channel */
@@ -1317,8 +1483,10 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
                         dma_chan[lch].state = DMA_CH_QUEUED;
                 }
 
-                /* Chain is already started, make sure its active,
-                 * if not then start the chain */
+                /*
+                 * Chain is already started, make sure its active,
+                 * if not then start the chain
+                 */
                 else {
                         start_dma = 1;
 
@@ -1327,8 +1495,8 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
                                 enable_lnk(dma_chan[lch].prev_linked_ch);
                                 dma_chan[lch].state = DMA_CH_QUEUED;
                                 start_dma = 0;
-                                if (0 == ((1 << 7) & (OMAP_DMA_CCR_REG
-                                        (dma_chan[lch].prev_linked_ch)))) {
+                                if (0 == ((1 << 7) & dma_read(
+                                        CCR(dma_chan[lch].prev_linked_ch)))) {
                                         disable_lnk(dma_chan[lch].
                                                     prev_linked_ch);
                                         pr_debug("\n prev ch is stopped\n");
@@ -1344,27 +1512,28 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
                         }
                         omap_enable_channel_irq(lch);
 
-                        w = OMAP_DMA_CCR_REG(lch);
+                        l = dma_read(CCR(lch));
 
-                        if ((0 == (w & (1 << 24))))
-                                w &= ~(1 << 25);
+                        if ((0 == (l & (1 << 24))))
+                                l &= ~(1 << 25);
                         else
-                                w |= (1 << 25);
+                                l |= (1 << 25);
                         if (start_dma == 1) {
-                                if (0 == (w & (1 << 7))) {
-                                        w |= (1 << 7);
+                                if (0 == (l & (1 << 7))) {
+                                        l |= (1 << 7);
                                         dma_chan[lch].state = DMA_CH_STARTED;
                                         pr_debug("starting %d\n", lch);
-                                        OMAP_DMA_CCR_REG(lch) = w;
+                                        dma_write(l, CCR(lch));
                                 } else
                                         start_dma = 0;
                         } else {
-                                if (0 == (w & (1 << 7)))
-                                        OMAP_DMA_CCR_REG(lch) = w;
+                                if (0 == (l & (1 << 7)))
+                                        dma_write(l, CCR(lch));
                         }
                         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
                 }
         }
+
         return 0;
 }
 EXPORT_SYMBOL(omap_dma_chain_a_transfer);
@@ -1380,9 +1549,9 @@ EXPORT_SYMBOL(omap_dma_chain_a_transfer);
 int omap_start_dma_chain_transfers(int chain_id)
 {
         int *channels;
-        u32 w, i;
+        u32 l, i;
 
-        if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
+        if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
                 printk(KERN_ERR "Invalid chain id\n");
                 return -EINVAL;
         }
@@ -1404,18 +1573,19 @@ int omap_start_dma_chain_transfers(int chain_id)
                 omap_enable_channel_irq(channels[0]);
         }
 
-        w = OMAP_DMA_CCR_REG(channels[0]);
-        w |= (1 << 7);
+        l = dma_read(CCR(channels[0]));
+        l |= (1 << 7);
         dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
         dma_chan[channels[0]].state = DMA_CH_STARTED;
 
-        if ((0 == (w & (1 << 24))))
-                w &= ~(1 << 25);
+        if ((0 == (l & (1 << 24))))
+                l &= ~(1 << 25);
         else
-                w |= (1 << 25);
-        OMAP_DMA_CCR_REG(channels[0]) = w;
+                l |= (1 << 25);
+        dma_write(l, CCR(channels[0]));
 
         dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
+
         return 0;
 }
 EXPORT_SYMBOL(omap_start_dma_chain_transfers);
@@ -1431,11 +1601,11 @@ EXPORT_SYMBOL(omap_start_dma_chain_transfers);
 int omap_stop_dma_chain_transfers(int chain_id)
 {
         int *channels;
-        u32 w, i;
+        u32 l, i;
         u32 sys_cf;
 
         /* Check for input params */
-        if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
+        if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
                 printk(KERN_ERR "Invalid chain id\n");
                 return -EINVAL;
         }
@@ -1447,21 +1617,22 @@ int omap_stop_dma_chain_transfers(int chain_id)
         }
         channels = dma_linked_lch[chain_id].linked_dmach_q;
 
-        /* DMA Errata:
+        /*
+         * DMA Errata:
          * Special programming model needed to disable DMA before end of block
          */
-        sys_cf = omap_readl(OMAP_DMA4_OCP_SYSCONFIG);
-        w = sys_cf;
+        sys_cf = dma_read(OCP_SYSCONFIG);
+        l = sys_cf;
         /* Middle mode reg set no Standby */
-        w &= ~((1 << 12)|(1 << 13));
-        omap_writel(w, OMAP_DMA4_OCP_SYSCONFIG);
+        l &= ~((1 << 12)|(1 << 13));
+        dma_write(l, OCP_SYSCONFIG);
 
         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
 
                 /* Stop the Channel transmission */
-                w = OMAP_DMA_CCR_REG(channels[i]);
-                w &= ~(1 << 7);
-                OMAP_DMA_CCR_REG(channels[i]) = w;
+                l = dma_read(CCR(channels[i]));
+                l &= ~(1 << 7);
+                dma_write(l, CCR(channels[i]));
 
                 /* Disable the link in all the channels */
                 disable_lnk(channels[i]);
@@ -1474,7 +1645,8 @@ int omap_stop_dma_chain_transfers(int chain_id)
         OMAP_DMA_CHAIN_QINIT(chain_id);
 
         /* Errata - put in the old value */
-        omap_writel(sys_cf, OMAP_DMA4_OCP_SYSCONFIG);
+        dma_write(sys_cf, OCP_SYSCONFIG);
+
         return 0;
 }
 EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
@@ -1497,7 +1669,7 @@ int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
         int *channels;
 
         /* Check for input params */
-        if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
+        if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
                 printk(KERN_ERR "Invalid chain id\n");
                 return -EINVAL;
         }
@@ -1515,8 +1687,8 @@ int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
         /* Get the current channel */
         lch = channels[dma_linked_lch[chain_id].q_head];
 
-        *ei = OMAP2_DMA_CCEN_REG(lch);
-        *fi = OMAP2_DMA_CCFN_REG(lch);
+        *ei = dma_read(CCEN(lch));
+        *fi = dma_read(CCFN(lch));
 
         return 0;
 }
@@ -1537,7 +1709,7 @@ int omap_get_dma_chain_dst_pos(int chain_id)
         int *channels;
 
         /* Check for input params */
-        if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
+        if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
                 printk(KERN_ERR "Invalid chain id\n");
                 return -EINVAL;
         }
@@ -1553,7 +1725,7 @@ int omap_get_dma_chain_dst_pos(int chain_id)
         /* Get the current channel */
         lch = channels[dma_linked_lch[chain_id].q_head];
 
-        return (OMAP_DMA_CDAC_REG(lch));
+        return dma_read(CDAC(lch));
 }
 EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
 
@@ -1571,7 +1743,7 @@ int omap_get_dma_chain_src_pos(int chain_id)
         int *channels;
 
         /* Check for input params */
-        if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
+        if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
                 printk(KERN_ERR "Invalid chain id\n");
                 return -EINVAL;
         }
@@ -1587,10 +1759,10 @@ int omap_get_dma_chain_src_pos(int chain_id)
         /* Get the current channel */
         lch = channels[dma_linked_lch[chain_id].q_head];
 
-        return (OMAP_DMA_CSAC_REG(lch));
+        return dma_read(CSAC(lch));
 }
 EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
-#endif
+#endif  /* ifndef CONFIG_ARCH_OMAP1 */
 
 /*----------------------------------------------------------------------------*/
 
@@ -1598,13 +1770,13 @@ EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
 
 static int omap1_dma_handle_ch(int ch)
 {
-        u16 csr;
+        u32 csr;
 
         if (enable_1510_mode && ch >= 6) {
                 csr = dma_chan[ch].saved_csr;
                 dma_chan[ch].saved_csr = 0;
         } else
-                csr = OMAP_DMA_CSR_REG(ch);
+                csr = dma_read(CSR(ch));
         if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
                 dma_chan[ch + 6].saved_csr = csr >> 7;
                 csr &= 0x7f;
@@ -1626,6 +1798,7 @@ static int omap1_dma_handle_ch(int ch)
                 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
         if (likely(dma_chan[ch].callback != NULL))
                 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
+
         return 1;
 }
 
@@ -1656,12 +1829,13 @@ static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
 
 static int omap2_dma_handle_ch(int ch)
 {
-        u32 status = OMAP_DMA_CSR_REG(ch);
+        u32 status = dma_read(CSR(ch));
 
         if (!status) {
                 if (printk_ratelimit())
-                        printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n", ch);
-                omap_writel(1 << ch, OMAP_DMA4_IRQSTATUS_L0);
+                        printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
+                                ch);
+                dma_write(1 << ch, IRQSTATUS_L0);
                 return 0;
         }
         if (unlikely(dma_chan[ch].dev_id == -1)) {
@@ -1684,14 +1858,14 @@ static int omap2_dma_handle_ch(int ch)
                 printk(KERN_INFO "DMA misaligned error with device %d\n",
                        dma_chan[ch].dev_id);
 
-        OMAP_DMA_CSR_REG(ch) = OMAP2_DMA_CSR_CLEAR_MASK;
-        omap_writel(1 << ch, OMAP_DMA4_IRQSTATUS_L0);
+        dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(ch));
+        dma_write(1 << ch, IRQSTATUS_L0);
 
         /* If the ch is not chained then chain_id will be -1 */
         if (dma_chan[ch].chain_id != -1) {
                 int chain_id = dma_chan[ch].chain_id;
                 dma_chan[ch].state = DMA_CH_NOTSTARTED;
-                if (OMAP_DMA_CLNK_CTRL_REG(ch) & (1 << 15))
+                if (dma_read(CLNK_CTRL(ch)) & (1 << 15))
                         dma_chan[dma_chan[ch].next_linked_ch].state =
                                                         DMA_CH_STARTED;
                 if (dma_linked_lch[chain_id].chain_mode ==
@@ -1701,13 +1875,13 @@ static int omap2_dma_handle_ch(int ch)
                 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
                         OMAP_DMA_CHAIN_INCQHEAD(chain_id);
 
-                status = OMAP_DMA_CSR_REG(ch);
+                status = dma_read(CSR(ch));
         }
 
         if (likely(dma_chan[ch].callback != NULL))
                 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
 
-        OMAP_DMA_CSR_REG(ch) = status;
+        dma_write(status, CSR(ch));
 
         return 0;
 }
@@ -1718,13 +1892,13 @@ static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
         u32 val;
         int i;
 
-        val = omap_readl(OMAP_DMA4_IRQSTATUS_L0);
+        val = dma_read(IRQSTATUS_L0);
         if (val == 0) {
                 if (printk_ratelimit())
                         printk(KERN_WARNING "Spurious DMA IRQ\n");
                 return IRQ_HANDLED;
         }
-        for (i = 0; i < OMAP_LOGICAL_DMA_CH_COUNT && val != 0; i++) {
+        for (i = 0; i < dma_lch_count && val != 0; i++) {
                 if (val & 1)
                         omap2_dma_handle_ch(i);
                 val >>= 1;
@@ -1748,7 +1922,7 @@ static struct irqaction omap24xx_dma_irq;
 static struct lcd_dma_info {
         spinlock_t lock;
         int reserved;
-        void (* callback)(u16 status, void *data);
+        void (*callback)(u16 status, void *data);
         void *cb_data;
 
         int active;
@@ -1770,6 +1944,7 @@ void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
         lcd_dma.xres = fb_xres;
         lcd_dma.yres = fb_yres;
 }
+EXPORT_SYMBOL(omap_set_lcd_dma_b1);
 
 void omap_set_lcd_dma_src_port(int port)
 {
@@ -1780,12 +1955,13 @@ void omap_set_lcd_dma_ext_controller(int external)
 {
         lcd_dma.ext_ctrl = external;
 }
+EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
 
 void omap_set_lcd_dma_single_transfer(int single)
 {
         lcd_dma.single_transfer = single;
 }
-
+EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
 
 void omap_set_lcd_dma_b1_rotation(int rotate)
 {
@@ -1796,6 +1972,7 @@ void omap_set_lcd_dma_b1_rotation(int rotate)
         }
         lcd_dma.rotate = rotate;
 }
+EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
 
 void omap_set_lcd_dma_b1_mirror(int mirror)
 {
@@ -1805,6 +1982,7 @@ void omap_set_lcd_dma_b1_mirror(int mirror)
         }
         lcd_dma.mirror = mirror;
 }
+EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
 
 void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
 {
@@ -1815,6 +1993,7 @@ void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
         }
         lcd_dma.vxres = vxres;
 }
+EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
 
 void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
 {
@@ -1825,6 +2004,7 @@ void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
         lcd_dma.xscale = xscale;
         lcd_dma.yscale = yscale;
 }
+EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
 
 static void set_b1_regs(void)
 {
@@ -1855,8 +2035,11 @@ static void set_b1_regs(void)
         xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
         yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
         BUG_ON(vxres < lcd_dma.xres);
-#define PIXADDR(x,y) (lcd_dma.addr + ((y) * vxres * yscale + (x) * xscale) * es)
+
+#define PIXADDR(x, y) (lcd_dma.addr +                                   \
+                ((y) * vxres * yscale + (x) * xscale) * es)
 #define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
+
         switch (lcd_dma.rotate) {
         case 0:
                 if (!lcd_dma.mirror) {
@@ -1865,8 +2048,8 @@ static void set_b1_regs(void)
                         /* 1510 DMA requires the bottom address to be 2 more
                          * than the actual last memory access location. */
                         if (omap_dma_in_1510_mode() &&
-                            lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
-                                bottom += 2;
+                                lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
+                                        bottom += 2;
                         ei = PIXSTEP(0, 0, 1, 0);
                         fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
                 } else {
@@ -1993,7 +2176,7 @@ static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id)
         return IRQ_HANDLED;
 }
 
-int omap_request_lcd_dma(void (* callback)(u16 status, void *data),
+int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
                          void *data)
 {
         spin_lock_irq(&lcd_dma.lock);
@@ -2019,6 +2202,7 @@ int omap_request_lcd_dma(void (* callback)(u16 status, void *data),
 
         return 0;
 }
+EXPORT_SYMBOL(omap_request_lcd_dma);
 
 void omap_free_lcd_dma(void)
 {
@@ -2035,12 +2219,14 @@ void omap_free_lcd_dma(void)
         lcd_dma.reserved = 0;
         spin_unlock(&lcd_dma.lock);
 }
+EXPORT_SYMBOL(omap_free_lcd_dma);
 
 void omap_enable_lcd_dma(void)
 {
         u16 w;
 
-        /* Set the Enable bit only if an external controller is
+        /*
+         * Set the Enable bit only if an external controller is
          * connected. Otherwise the OMAP internal controller will
          * start the transfer when it gets enabled.
          */
@@ -2057,6 +2243,7 @@ void omap_enable_lcd_dma(void)
         w |= 1 << 7;
         omap_writew(w, OMAP1610_DMA_LCD_CCR);
 }
+EXPORT_SYMBOL(omap_enable_lcd_dma);
 
 void omap_setup_lcd_dma(void)
 {
@@ -2072,16 +2259,18 @@ void omap_setup_lcd_dma(void)
                 u16 w;
 
                 w = omap_readw(OMAP1610_DMA_LCD_CCR);
-                /* If DMA was already active set the end_prog bit to have
+                /*
+                 * If DMA was already active set the end_prog bit to have
                  * the programmed register set loaded into the active
                  * register set.
                  */
                 w |= 1 << 11;           /* End_prog */
                 if (!lcd_dma.single_transfer)
-                        w |= (3 << 8);  /* Auto_init, repeat */
+                        w |= (3 << 8);  /* Auto_init, repeat */
                 omap_writew(w, OMAP1610_DMA_LCD_CCR);
         }
 }
+EXPORT_SYMBOL(omap_setup_lcd_dma);
 
 void omap_stop_lcd_dma(void)
 {
@@ -2099,6 +2288,7 @@ void omap_stop_lcd_dma(void)
         w &= ~(1 << 8);
         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
 }
+EXPORT_SYMBOL(omap_stop_lcd_dma);
 
 /*----------------------------------------------------------------------------*/
 
@@ -2106,27 +2296,55 @@ static int __init omap_init_dma(void)
 {
         int ch, r;
 
+        if (cpu_class_is_omap1()) {
+                omap_dma_base = (void __iomem *)IO_ADDRESS(OMAP1_DMA_BASE);
+                dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
+        } else if (cpu_is_omap24xx()) {
+                omap_dma_base = (void __iomem *)IO_ADDRESS(OMAP24XX_DMA4_BASE);
+                dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
+        } else if (cpu_is_omap34xx()) {
+                omap_dma_base = (void __iomem *)IO_ADDRESS(OMAP34XX_DMA4_BASE);
+                dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
+        } else {
+                pr_err("DMA init failed for unsupported omap\n");
+                return -ENODEV;
+        }
+
+        dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count,
+                                GFP_KERNEL);
+        if (!dma_chan)
+                return -ENOMEM;
+
+        if (cpu_class_is_omap2()) {
+                dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
+                                                dma_lch_count, GFP_KERNEL);
+                if (!dma_linked_lch) {
+                        kfree(dma_chan);
+                        return -ENOMEM;
+                }
+        }
+
         if (cpu_is_omap15xx()) {
                 printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
                 dma_chan_count = 9;
                 enable_1510_mode = 1;
         } else if (cpu_is_omap16xx() || cpu_is_omap730()) {
                 printk(KERN_INFO "OMAP DMA hardware version %d\n",
-                       omap_readw(OMAP_DMA_HW_ID));
+                       dma_read(HW_ID));
                 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
-                       (omap_readw(OMAP_DMA_CAPS_0_U) << 16) |
-                       omap_readw(OMAP_DMA_CAPS_0_L),
-                       (omap_readw(OMAP_DMA_CAPS_1_U) << 16) |
-                       omap_readw(OMAP_DMA_CAPS_1_L),
-                       omap_readw(OMAP_DMA_CAPS_2), omap_readw(OMAP_DMA_CAPS_3),
-                       omap_readw(OMAP_DMA_CAPS_4));
+                       (dma_read(CAPS_0_U) << 16) |
+                       dma_read(CAPS_0_L),
+                       (dma_read(CAPS_1_U) << 16) |
+                       dma_read(CAPS_1_L),
+                       dma_read(CAPS_2), dma_read(CAPS_3),
+                       dma_read(CAPS_4));
                 if (!enable_1510_mode) {
                         u16 w;
 
                         /* Disable OMAP 3.0/3.1 compatibility mode. */
-                        w = omap_readw(OMAP_DMA_GSCR);
+                        w = dma_read(GSCR);
                         w |= 1 << 3;
-                        omap_writew(w, OMAP_DMA_GSCR);
+                        dma_write(w, GSCR);
                         dma_chan_count = 16;
                 } else
                         dma_chan_count = 9;
@@ -2139,19 +2357,17 @@ static int __init omap_init_dma(void)
                         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
                 }
         } else if (cpu_class_is_omap2()) {
-                u8 revision = omap_readb(OMAP_DMA4_REVISION);
+                u8 revision = dma_read(REVISION) & 0xff;
                 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
                        revision >> 4, revision & 0xf);
-                dma_chan_count = OMAP_LOGICAL_DMA_CH_COUNT;
+                dma_chan_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
         } else {
                 dma_chan_count = 0;
                 return 0;
         }
 
-        memset(&lcd_dma, 0, sizeof(lcd_dma));
         spin_lock_init(&lcd_dma.lock);
         spin_lock_init(&dma_chan_lock);
-        memset(&dma_chan, 0, sizeof(dma_chan));
 
         for (ch = 0; ch < dma_chan_count; ch++) {
                 omap_clear_dma(ch);
@@ -2162,8 +2378,10 @@ static int __init omap_init_dma(void)
                         continue;
 
                 if (cpu_class_is_omap1()) {
-                        /* request_irq() doesn't like dev_id (ie. ch) being
-                         * zero, so we have to kludge around this. */
+                        /*
+                         * request_irq() doesn't like dev_id (ie. ch) being
+                         * zero, so we have to kludge around this.
+                         */
                         r = request_irq(omap1_dma_irq[ch],
                                         omap1_dma_irq_handler, 0, "DMA",
                                         (void *) (ch + 1));
@@ -2208,48 +2426,4 @@ static int __init omap_init_dma(void)
 
 arch_initcall(omap_init_dma);
 
-EXPORT_SYMBOL(omap_get_dma_src_pos);
-EXPORT_SYMBOL(omap_get_dma_dst_pos);
-EXPORT_SYMBOL(omap_get_dma_src_addr_counter);
-EXPORT_SYMBOL(omap_clear_dma);
-EXPORT_SYMBOL(omap_set_dma_priority);
-EXPORT_SYMBOL(omap_request_dma);
-EXPORT_SYMBOL(omap_free_dma);
-EXPORT_SYMBOL(omap_start_dma);
-EXPORT_SYMBOL(omap_stop_dma);
-EXPORT_SYMBOL(omap_set_dma_callback);
-EXPORT_SYMBOL(omap_enable_dma_irq);
-EXPORT_SYMBOL(omap_disable_dma_irq);
-
-EXPORT_SYMBOL(omap_set_dma_transfer_params);
-EXPORT_SYMBOL(omap_set_dma_color_mode);
-EXPORT_SYMBOL(omap_set_dma_write_mode);
-
-EXPORT_SYMBOL(omap_set_dma_src_params);
-EXPORT_SYMBOL(omap_set_dma_src_index);
-EXPORT_SYMBOL(omap_set_dma_src_data_pack);
-EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
-
-EXPORT_SYMBOL(omap_set_dma_dest_params);
-EXPORT_SYMBOL(omap_set_dma_dest_index);
-EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
-EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
-
-EXPORT_SYMBOL(omap_set_dma_params);
-
-EXPORT_SYMBOL(omap_dma_link_lch);
-EXPORT_SYMBOL(omap_dma_unlink_lch);
-
-EXPORT_SYMBOL(omap_request_lcd_dma);
-EXPORT_SYMBOL(omap_free_lcd_dma);
-EXPORT_SYMBOL(omap_enable_lcd_dma);
-EXPORT_SYMBOL(omap_setup_lcd_dma);
-EXPORT_SYMBOL(omap_stop_lcd_dma);
-EXPORT_SYMBOL(omap_set_lcd_dma_b1);
-EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
-EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
-EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
-EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
-EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
-EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
 
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 302ad8dff2cb..f22506af0e67 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -38,34 +38,113 @@
 #include <asm/arch/irqs.h>
 
 /* register offsets */
-#define OMAP_TIMER_ID_REG               0x00
-#define OMAP_TIMER_OCP_CFG_REG          0x10
-#define OMAP_TIMER_SYS_STAT_REG         0x14
-#define OMAP_TIMER_STAT_REG             0x18
-#define OMAP_TIMER_INT_EN_REG           0x1c
-#define OMAP_TIMER_WAKEUP_EN_REG        0x20
-#define OMAP_TIMER_CTRL_REG             0x24
-#define OMAP_TIMER_COUNTER_REG          0x28
-#define OMAP_TIMER_LOAD_REG             0x2c
-#define OMAP_TIMER_TRIGGER_REG          0x30
-#define OMAP_TIMER_WRITE_PEND_REG       0x34
-#define OMAP_TIMER_MATCH_REG            0x38
-#define OMAP_TIMER_CAPTURE_REG          0x3c
-#define OMAP_TIMER_IF_CTRL_REG          0x40
-
-/* timer control reg bits */
-#define OMAP_TIMER_CTRL_GPOCFG          (1 << 14)
-#define OMAP_TIMER_CTRL_CAPTMODE        (1 << 13)
-#define OMAP_TIMER_CTRL_PT              (1 << 12)
-#define OMAP_TIMER_CTRL_TCM_LOWTOHIGH   (0x1 << 8)
-#define OMAP_TIMER_CTRL_TCM_HIGHTOLOW   (0x2 << 8)
-#define OMAP_TIMER_CTRL_TCM_BOTHEDGES   (0x3 << 8)
-#define OMAP_TIMER_CTRL_SCPWM           (1 << 7)
-#define OMAP_TIMER_CTRL_CE              (1 << 6)        /* compare enable */
-#define OMAP_TIMER_CTRL_PRE             (1 << 5)        /* prescaler enable */
-#define OMAP_TIMER_CTRL_PTV_SHIFT       2               /* how much to shift the prescaler value */
-#define OMAP_TIMER_CTRL_AR              (1 << 1)        /* auto-reload enable */
-#define OMAP_TIMER_CTRL_ST              (1 << 0)        /* start timer */
+#define _OMAP_TIMER_ID_OFFSET           0x00
+#define _OMAP_TIMER_OCP_CFG_OFFSET      0x10
+#define _OMAP_TIMER_SYS_STAT_OFFSET     0x14
+#define _OMAP_TIMER_STAT_OFFSET         0x18
+#define _OMAP_TIMER_INT_EN_OFFSET       0x1c
+#define _OMAP_TIMER_WAKEUP_EN_OFFSET    0x20
+#define _OMAP_TIMER_CTRL_OFFSET         0x24
+#define         OMAP_TIMER_CTRL_GPOCFG          (1 << 14)
+#define         OMAP_TIMER_CTRL_CAPTMODE        (1 << 13)
+#define         OMAP_TIMER_CTRL_PT              (1 << 12)
+#define         OMAP_TIMER_CTRL_TCM_LOWTOHIGH   (0x1 << 8)
+#define         OMAP_TIMER_CTRL_TCM_HIGHTOLOW   (0x2 << 8)
+#define         OMAP_TIMER_CTRL_TCM_BOTHEDGES   (0x3 << 8)
+#define         OMAP_TIMER_CTRL_SCPWM           (1 << 7)
+#define         OMAP_TIMER_CTRL_CE              (1 << 6) /* compare enable */
+#define         OMAP_TIMER_CTRL_PRE             (1 << 5) /* prescaler enable */
+#define         OMAP_TIMER_CTRL_PTV_SHIFT       2 /* prescaler value shift */
+#define         OMAP_TIMER_CTRL_POSTED          (1 << 2)
+#define         OMAP_TIMER_CTRL_AR              (1 << 1) /* auto-reload enable */
+#define         OMAP_TIMER_CTRL_ST              (1 << 0) /* start timer */
+#define _OMAP_TIMER_COUNTER_OFFSET      0x28
+#define _OMAP_TIMER_LOAD_OFFSET         0x2c
+#define _OMAP_TIMER_TRIGGER_OFFSET      0x30
+#define _OMAP_TIMER_WRITE_PEND_OFFSET   0x34
+#define         WP_NONE                 0       /* no write pending bit */
+#define         WP_TCLR                 (1 << 0)
+#define         WP_TCRR                 (1 << 1)
+#define         WP_TLDR                 (1 << 2)
+#define         WP_TTGR                 (1 << 3)
+#define         WP_TMAR                 (1 << 4)
+#define         WP_TPIR                 (1 << 5)
+#define         WP_TNIR                 (1 << 6)
+#define         WP_TCVR                 (1 << 7)
+#define         WP_TOCR                 (1 << 8)
+#define         WP_TOWR                 (1 << 9)
+#define _OMAP_TIMER_MATCH_OFFSET        0x38
+#define _OMAP_TIMER_CAPTURE_OFFSET      0x3c
+#define _OMAP_TIMER_IF_CTRL_OFFSET      0x40
+#define _OMAP_TIMER_CAPTURE2_OFFSET             0x44    /* TCAR2, 34xx only */
+#define _OMAP_TIMER_TICK_POS_OFFSET             0x48    /* TPIR, 34xx only */
+#define _OMAP_TIMER_TICK_NEG_OFFSET             0x4c    /* TNIR, 34xx only */
+#define _OMAP_TIMER_TICK_COUNT_OFFSET           0x50    /* TCVR, 34xx only */
+#define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET    0x54    /* TOCR, 34xx only */
+#define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET  0x58    /* TOWR, 34xx only */
+
+/* register offsets with the write pending bit encoded */
+#define WPSHIFT                                 16
+
+#define OMAP_TIMER_ID_REG                       (_OMAP_TIMER_ID_OFFSET \
+                                                        | (WP_NONE << WPSHIFT))
+
+#define OMAP_TIMER_OCP_CFG_REG                  (_OMAP_TIMER_OCP_CFG_OFFSET \
+                                                        | (WP_NONE << WPSHIFT))
+
+#define OMAP_TIMER_SYS_STAT_REG                 (_OMAP_TIMER_SYS_STAT_OFFSET \
+                                                        | (WP_NONE << WPSHIFT))
+
+#define OMAP_TIMER_STAT_REG                     (_OMAP_TIMER_STAT_OFFSET \
+                                                        | (WP_NONE << WPSHIFT))
+
+#define OMAP_TIMER_INT_EN_REG                   (_OMAP_TIMER_INT_EN_OFFSET \
+                                                        | (WP_NONE << WPSHIFT))
+
+#define OMAP_TIMER_WAKEUP_EN_REG                (_OMAP_TIMER_WAKEUP_EN_OFFSET \
+                                                        | (WP_NONE << WPSHIFT))
+
+#define OMAP_TIMER_CTRL_REG                     (_OMAP_TIMER_CTRL_OFFSET \
+                                                        | (WP_TCLR << WPSHIFT))
+
+#define OMAP_TIMER_COUNTER_REG                  (_OMAP_TIMER_COUNTER_OFFSET \
+                                                        | (WP_TCRR << WPSHIFT))
+
+#define OMAP_TIMER_LOAD_REG                     (_OMAP_TIMER_LOAD_OFFSET \
+                                                        | (WP_TLDR << WPSHIFT))
+
+#define OMAP_TIMER_TRIGGER_REG                  (_OMAP_TIMER_TRIGGER_OFFSET \
+                                                        | (WP_TTGR << WPSHIFT))
+
+#define OMAP_TIMER_WRITE_PEND_REG               (_OMAP_TIMER_WRITE_PEND_OFFSET \
+                                                        | (WP_NONE << WPSHIFT))
+
+#define OMAP_TIMER_MATCH_REG                    (_OMAP_TIMER_MATCH_OFFSET \
+                                                        | (WP_TMAR << WPSHIFT))
+
+#define OMAP_TIMER_CAPTURE_REG                  (_OMAP_TIMER_CAPTURE_OFFSET \
+                                                        | (WP_NONE << WPSHIFT))
+
+#define OMAP_TIMER_IF_CTRL_REG                  (_OMAP_TIMER_IF_CTRL_OFFSET \
+                                                        | (WP_NONE << WPSHIFT))
+
+#define OMAP_TIMER_CAPTURE2_REG                 (_OMAP_TIMER_CAPTURE2_OFFSET \
+                                                        | (WP_NONE << WPSHIFT))
+
+#define OMAP_TIMER_TICK_POS_REG                 (_OMAP_TIMER_TICK_POS_OFFSET \
+                                                        | (WP_TPIR << WPSHIFT))
+
+#define OMAP_TIMER_TICK_NEG_REG                 (_OMAP_TIMER_TICK_NEG_OFFSET \
+                                                        | (WP_TNIR << WPSHIFT))
+
+#define OMAP_TIMER_TICK_COUNT_REG               (_OMAP_TIMER_TICK_COUNT_OFFSET \
+                                                        | (WP_TCVR << WPSHIFT))
+
+#define OMAP_TIMER_TICK_INT_MASK_SET_REG                                \
+                (_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT))
+
+#define OMAP_TIMER_TICK_INT_MASK_COUNT_REG                              \
+                (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
 
 struct omap_dm_timer {
         unsigned long phys_base;
@@ -76,6 +155,7 @@ struct omap_dm_timer {
         void __iomem *io_base;
         unsigned reserved:1;
         unsigned enabled:1;
+        unsigned posted:1;
 };
 
 #ifdef CONFIG_ARCH_OMAP1
@@ -181,16 +261,34 @@ static struct clk **dm_source_clocks;
 
 static spinlock_t dm_timer_lock;
 
-static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, int reg)
+/*
+ * Reads timer registers in posted and non-posted mode. The posted mode bit
+ * is encoded in reg. Note that in posted mode write pending bit must be
+ * checked. Otherwise a read of a non completed write will produce an error.
+ */
+static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg)
 {
-        return readl(timer->io_base + reg);
+        if (timer->posted)
+                while (readl(timer->io_base + (OMAP_TIMER_WRITE_PEND_REG & 0xff))
+                                & (reg >> WPSHIFT))
+                        cpu_relax();
+        return readl(timer->io_base + (reg & 0xff));
 }
 
-static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, int reg, u32 value)
+/*
+ * Writes timer registers in posted and non-posted mode. The posted mode bit
+ * is encoded in reg. Note that in posted mode the write pending bit must be
+ * checked. Otherwise a write on a register which has a pending write will be
+ * lost.
+ */
+static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg,
+                                                u32 value)
 {
-        writel(value, timer->io_base + reg);
-        while (omap_dm_timer_read_reg(timer, OMAP_TIMER_WRITE_PEND_REG))
-                ;
+        if (timer->posted)
+                while (readl(timer->io_base + (OMAP_TIMER_WRITE_PEND_REG & 0xff))
+                                & (reg >> WPSHIFT))
+                        cpu_relax();
+        writel(value, timer->io_base + (reg & 0xff));
 }
 
 static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer)
@@ -217,17 +315,23 @@ static void omap_dm_timer_reset(struct omap_dm_timer *timer)
         }
         omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
 
-        /* Set to smart-idle mode */
         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_OCP_CFG_REG);
-        l |= 0x02 << 3;
-
-        if (cpu_class_is_omap2() && timer == &dm_timers[0]) {
-                /* Enable wake-up only for GPT1 on OMAP2 CPUs*/
+        l |= 0x02 << 3;  /* Set to smart-idle mode */
+        l |= 0x2 << 8;   /* Set clock activity to perserve f-clock on idle */
+
+        /*
+         * Enable wake-up only for GPT1 on OMAP2 CPUs.
+         * FIXME: All timers should have wake-up enabled and clear
+         * PRCM status.
+         */
+        if (cpu_class_is_omap2() && (timer == &dm_timers[0]))
                 l |= 1 << 2;
-                /* Non-posted mode */
-                omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0);
-        }
         omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_REG, l);
+
+        /* Match hardware reset default of posted mode */
+        omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG,
+                        OMAP_TIMER_CTRL_POSTED);
+        timer->posted = 1;
 }
 
 static void omap_dm_timer_prepare(struct omap_dm_timer *timer)
@@ -434,9 +538,32 @@ void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
                 l &= ~OMAP_TIMER_CTRL_AR;
         omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
         omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
+
+        /* REVISIT: hw feature, ttgr overtaking tldr? */
+        while (readl(timer->io_base + (OMAP_TIMER_WRITE_PEND_REG & 0xff)))
+                cpu_relax();
+
         omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
 }
 
+/* Optimized set_load which removes costly spin wait in timer_start */
+void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload,
+                            unsigned int load)
+{
+        u32 l;
+
+        l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
+        if (autoreload)
+                l |= OMAP_TIMER_CTRL_AR;
+        else
+                l &= ~OMAP_TIMER_CTRL_AR;
+        l |= OMAP_TIMER_CTRL_ST;
+
+        omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, load);
+        omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
+        omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
+}
+
 void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
                              unsigned int match)
 {
@@ -451,7 +578,6 @@ void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
         omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match);
 }
 
-
 void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
                            int toggle, int trigger)
 {
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index 9cf83c4da9fa..c7f74064696c 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -15,95 +15,66 @@
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/device.h>
+#include <linux/platform_device.h>
 #include <linux/wait.h>
 #include <linux/completion.h>
 #include <linux/interrupt.h>
 #include <linux/err.h>
 #include <linux/clk.h>
 #include <linux/delay.h>
-
-#include <asm/io.h>
-#include <asm/irq.h>
+#include <linux/io.h>
 
 #include <asm/arch/dma.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/irqs.h>
-#include <asm/arch/dsp_common.h>
 #include <asm/arch/mcbsp.h>
 
-#ifdef CONFIG_MCBSP_DEBUG
-#define DBG(x...)       printk(x)
-#else
-#define DBG(x...)                       do { } while (0)
-#endif
-
-struct omap_mcbsp {
-        u32                          io_base;
-        u8                           id;
-        u8                           free;
-        omap_mcbsp_word_length       rx_word_length;
-        omap_mcbsp_word_length       tx_word_length;
-
-        omap_mcbsp_io_type_t         io_type; /* IRQ or poll */
-        /* IRQ based TX/RX */
-        int                          rx_irq;
-        int                          tx_irq;
-
-        /* DMA stuff */
-        u8                           dma_rx_sync;
-        short                        dma_rx_lch;
-        u8                           dma_tx_sync;
-        short                        dma_tx_lch;
-
-        /* Completion queues */
-        struct completion            tx_irq_completion;
-        struct completion            rx_irq_completion;
-        struct completion            tx_dma_completion;
-        struct completion            rx_dma_completion;
-
-        spinlock_t                   lock;
-};
-
 static struct omap_mcbsp mcbsp[OMAP_MAX_MCBSP_COUNT];
-#ifdef CONFIG_ARCH_OMAP1
-static struct clk *mcbsp_dsp_ck = 0;
-static struct clk *mcbsp_api_ck = 0;
-static struct clk *mcbsp_dspxor_ck = 0;
-#endif
-#ifdef CONFIG_ARCH_OMAP2
-static struct clk *mcbsp1_ick = 0;
-static struct clk *mcbsp1_fck = 0;
-static struct clk *mcbsp2_ick = 0;
-static struct clk *mcbsp2_fck = 0;
-#endif
+
+#define omap_mcbsp_check_valid_id(id)   (mcbsp[id].pdata && \
+                                        mcbsp[id].pdata->ops && \
+                                        mcbsp[id].pdata->ops->check && \
+                                        (mcbsp[id].pdata->ops->check(id) == 0))
 
 static void omap_mcbsp_dump_reg(u8 id)
 {
-        DBG("**** MCBSP%d regs ****\n", mcbsp[id].id);
-        DBG("DRR2:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DRR2));
-        DBG("DRR1:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DRR1));
-        DBG("DXR2:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DXR2));
-        DBG("DXR1:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DXR1));
-        DBG("SPCR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR2));
-        DBG("SPCR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR1));
-        DBG("RCR2:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, RCR2));
-        DBG("RCR1:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, RCR1));
-        DBG("XCR2:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, XCR2));
-        DBG("XCR1:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, XCR1));
-        DBG("SRGR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR2));
-        DBG("SRGR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR1));
-        DBG("PCR0:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, PCR0));
-        DBG("***********************\n");
+        dev_dbg(mcbsp[id].dev, "**** McBSP%d regs ****\n", mcbsp[id].id);
+        dev_dbg(mcbsp[id].dev, "DRR2:  0x%04x\n",
+                        OMAP_MCBSP_READ(mcbsp[id].io_base, DRR2));
+        dev_dbg(mcbsp[id].dev, "DRR1:  0x%04x\n",
+                        OMAP_MCBSP_READ(mcbsp[id].io_base, DRR1));
+        dev_dbg(mcbsp[id].dev, "DXR2:  0x%04x\n",
+                        OMAP_MCBSP_READ(mcbsp[id].io_base, DXR2));
+        dev_dbg(mcbsp[id].dev, "DXR1:  0x%04x\n",
+                        OMAP_MCBSP_READ(mcbsp[id].io_base, DXR1));
+        dev_dbg(mcbsp[id].dev, "SPCR2: 0x%04x\n",
+                        OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR2));
+        dev_dbg(mcbsp[id].dev, "SPCR1: 0x%04x\n",
+                        OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR1));
+        dev_dbg(mcbsp[id].dev, "RCR2:  0x%04x\n",
+                        OMAP_MCBSP_READ(mcbsp[id].io_base, RCR2));
+        dev_dbg(mcbsp[id].dev, "RCR1:  0x%04x\n",
+                        OMAP_MCBSP_READ(mcbsp[id].io_base, RCR1));
+        dev_dbg(mcbsp[id].dev, "XCR2:  0x%04x\n",
+                        OMAP_MCBSP_READ(mcbsp[id].io_base, XCR2));
+        dev_dbg(mcbsp[id].dev, "XCR1:  0x%04x\n",
+                        OMAP_MCBSP_READ(mcbsp[id].io_base, XCR1));
+        dev_dbg(mcbsp[id].dev, "SRGR2: 0x%04x\n",
+                        OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR2));
+        dev_dbg(mcbsp[id].dev, "SRGR1: 0x%04x\n",
+                        OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR1));
+        dev_dbg(mcbsp[id].dev, "PCR0:  0x%04x\n",
+                        OMAP_MCBSP_READ(mcbsp[id].io_base, PCR0));
+        dev_dbg(mcbsp[id].dev, "***********************\n");
 }
 
 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
 {
         struct omap_mcbsp *mcbsp_tx = dev_id;
 
-        DBG("TX IRQ callback : 0x%x\n",
-            OMAP_MCBSP_READ(mcbsp_tx->io_base, SPCR2));
+        dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n",
+                OMAP_MCBSP_READ(mcbsp_tx->io_base, SPCR2));
 
         complete(&mcbsp_tx->tx_irq_completion);
+
         return IRQ_HANDLED;
 }
 
@@ -111,10 +82,11 @@ static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
 {
         struct omap_mcbsp *mcbsp_rx = dev_id;
 
-        DBG("RX IRQ callback : 0x%x\n",
-            OMAP_MCBSP_READ(mcbsp_rx->io_base, SPCR2));
+        dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n",
+                OMAP_MCBSP_READ(mcbsp_rx->io_base, SPCR2));
 
         complete(&mcbsp_rx->rx_irq_completion);
+
         return IRQ_HANDLED;
 }
 
@@ -122,8 +94,8 @@ static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
 {
         struct omap_mcbsp *mcbsp_dma_tx = data;
 
-        DBG("TX DMA callback : 0x%x\n",
-            OMAP_MCBSP_READ(mcbsp_dma_tx->io_base, SPCR2));
+        dev_dbg(mcbsp_dma_tx->dev, "TX DMA callback : 0x%x\n",
+                OMAP_MCBSP_READ(mcbsp_dma_tx->io_base, SPCR2));
 
         /* We can free the channels */
         omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
@@ -136,8 +108,8 @@ static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
 {
         struct omap_mcbsp *mcbsp_dma_rx = data;
 
-        DBG("RX DMA callback : 0x%x\n",
-            OMAP_MCBSP_READ(mcbsp_dma_rx->io_base, SPCR2));
+        dev_dbg(mcbsp_dma_rx->dev, "RX DMA callback : 0x%x\n",
+                OMAP_MCBSP_READ(mcbsp_dma_rx->io_base, SPCR2));
 
         /* We can free the channels */
         omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
@@ -146,19 +118,24 @@ static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
         complete(&mcbsp_dma_rx->rx_dma_completion);
 }
 
-
 /*
  * omap_mcbsp_config simply write a config to the
  * appropriate McBSP.
  * You either call this function or set the McBSP registers
  * by yourself before calling omap_mcbsp_start().
  */
-
-void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config)
+void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
 {
-        u32 io_base = mcbsp[id].io_base;
+        u32 io_base;
+
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+                return;
+        }
 
-        DBG("OMAP-McBSP: McBSP%d  io_base: 0x%8x\n", id+1, io_base);
+        io_base = mcbsp[id].io_base;
+        dev_dbg(mcbsp[id].dev, "Configuring McBSP%d  io_base: 0x%8x\n",
+                        mcbsp[id].id, io_base);
 
         /* We write the given config */
         OMAP_MCBSP_WRITE(io_base, SPCR2, config->spcr2);
@@ -173,83 +150,7 @@ void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config
         OMAP_MCBSP_WRITE(io_base, MCR1, config->mcr1);
         OMAP_MCBSP_WRITE(io_base, PCR0, config->pcr0);
 }
-
-
-
-static int omap_mcbsp_check(unsigned int id)
-{
-        if (cpu_is_omap730()) {
-                if (id > OMAP_MAX_MCBSP_COUNT - 1) {
-                       printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n", id + 1);
-                       return -1;
-                }
-                return 0;
-        }
-
-        if (cpu_is_omap15xx() || cpu_is_omap16xx() || cpu_is_omap24xx()) {
-                if (id > OMAP_MAX_MCBSP_COUNT) {
-                        printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n", id + 1);
-                        return -1;
-                }
-                return 0;
-        }
-
-        return -1;
-}
-
-#ifdef CONFIG_ARCH_OMAP1
-static void omap_mcbsp_dsp_request(void)
-{
-        if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
-                int ret;
-
-                ret = omap_dsp_request_mem();
-                if (ret < 0) {
-                        printk(KERN_ERR "Could not get dsp memory: %i\n", ret);
-                        return;
-                }
-
-                clk_enable(mcbsp_dsp_ck);
-                clk_enable(mcbsp_api_ck);
-
-                /* enable 12MHz clock to mcbsp 1 & 3 */
-                clk_enable(mcbsp_dspxor_ck);
-
-                /*
-                 * DSP external peripheral reset
-                 * FIXME: This should be moved to dsp code
-                 */
-                __raw_writew(__raw_readw(DSP_RSTCT2) | 1 | 1 << 1,
-                             DSP_RSTCT2);
-        }
-}
-
-static void omap_mcbsp_dsp_free(void)
-{
-        if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
-                omap_dsp_release_mem();
-                clk_disable(mcbsp_dspxor_ck);
-                clk_disable(mcbsp_dsp_ck);
-                clk_disable(mcbsp_api_ck);
-        }
-}
-#endif
-
-#ifdef CONFIG_ARCH_OMAP2
-static void omap2_mcbsp2_mux_setup(void)
-{
-        if (cpu_is_omap2420()) {
-                omap_cfg_reg(Y15_24XX_MCBSP2_CLKX);
-                omap_cfg_reg(R14_24XX_MCBSP2_FSX);
-                omap_cfg_reg(W15_24XX_MCBSP2_DR);
-                omap_cfg_reg(V15_24XX_MCBSP2_DX);
-                omap_cfg_reg(V14_24XX_GPIO117);
-        }
-        /*
-         * Need to add MUX settings for OMAP 2430 SDP
-         */
-}
-#endif
+EXPORT_SYMBOL(omap_mcbsp_config);
 
 /*
  * We can choose between IRQ based or polled IO.
@@ -257,13 +158,16 @@ static void omap2_mcbsp2_mux_setup(void)
  */
 int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
 {
-        if (omap_mcbsp_check(id) < 0)
-                return -EINVAL;
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+                return -ENODEV;
+        }
 
         spin_lock(&mcbsp[id].lock);
 
         if (!mcbsp[id].free) {
-                printk (KERN_ERR "OMAP-McBSP: McBSP%d is currently in use\n", id + 1);
+                dev_err(mcbsp[id].dev, "McBSP%d is currently in use\n",
+                        mcbsp[id].id);
                 spin_unlock(&mcbsp[id].lock);
                 return -EINVAL;
         }
@@ -274,38 +178,26 @@ int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
 
         return 0;
 }
+EXPORT_SYMBOL(omap_mcbsp_set_io_type);
 
 int omap_mcbsp_request(unsigned int id)
 {
         int err;
 
-        if (omap_mcbsp_check(id) < 0)
-                return -EINVAL;
-
-#ifdef CONFIG_ARCH_OMAP1
-        /*
-         * On 1510, 1610 and 1710, McBSP1 and McBSP3
-         * are DSP public peripherals.
-         */
-        if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3)
-                omap_mcbsp_dsp_request();
-#endif
-
-#ifdef CONFIG_ARCH_OMAP2
-        if (cpu_is_omap24xx()) {
-                if (id == OMAP_MCBSP1) {
-                        clk_enable(mcbsp1_ick);
-                        clk_enable(mcbsp1_fck);
-                } else {
-                        clk_enable(mcbsp2_ick);
-                        clk_enable(mcbsp2_fck);
-                }
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+                return -ENODEV;
         }
-#endif
+
+        if (mcbsp[id].pdata->ops->request)
+                mcbsp[id].pdata->ops->request(id);
+
+        clk_enable(mcbsp[id].clk);
 
         spin_lock(&mcbsp[id].lock);
         if (!mcbsp[id].free) {
-                printk (KERN_ERR "OMAP-McBSP: McBSP%d is currently in use\n", id + 1);
+                dev_err(mcbsp[id].dev, "McBSP%d is currently in use\n",
+                        mcbsp[id].id);
                 spin_unlock(&mcbsp[id].lock);
                 return -1;
         }
@@ -315,24 +207,23 @@ int omap_mcbsp_request(unsigned int id)
 
         if (mcbsp[id].io_type == OMAP_MCBSP_IRQ_IO) {
                 /* We need to get IRQs here */
-                err = request_irq(mcbsp[id].tx_irq, omap_mcbsp_tx_irq_handler, 0,
-                                  "McBSP",
-                                  (void *) (&mcbsp[id]));
+                err = request_irq(mcbsp[id].tx_irq, omap_mcbsp_tx_irq_handler,
+                                        0, "McBSP", (void *) (&mcbsp[id]));
                 if (err != 0) {
-                        printk(KERN_ERR "OMAP-McBSP: Unable to request TX IRQ %d for McBSP%d\n",
-                               mcbsp[id].tx_irq, mcbsp[id].id);
+                        dev_err(mcbsp[id].dev, "Unable to request TX IRQ %d "
+                                        "for McBSP%d\n", mcbsp[id].tx_irq,
+                                        mcbsp[id].id);
                         return err;
                 }
 
                 init_completion(&(mcbsp[id].tx_irq_completion));
 
-
-                err = request_irq(mcbsp[id].rx_irq, omap_mcbsp_rx_irq_handler, 0,
-                                  "McBSP",
-                                  (void *) (&mcbsp[id]));
+                err = request_irq(mcbsp[id].rx_irq, omap_mcbsp_rx_irq_handler,
+                                        0, "McBSP", (void *) (&mcbsp[id]));
                 if (err != 0) {
-                        printk(KERN_ERR "OMAP-McBSP: Unable to request RX IRQ %d for McBSP%d\n",
-                               mcbsp[id].rx_irq, mcbsp[id].id);
+                        dev_err(mcbsp[id].dev, "Unable to request RX IRQ %d "
+                                        "for McBSP%d\n", mcbsp[id].rx_irq,
+                                        mcbsp[id].id);
                         free_irq(mcbsp[id].tx_irq, (void *) (&mcbsp[id]));
                         return err;
                 }
@@ -341,36 +232,25 @@ int omap_mcbsp_request(unsigned int id)
         }
 
         return 0;
-
 }
+EXPORT_SYMBOL(omap_mcbsp_request);
 
 void omap_mcbsp_free(unsigned int id)
 {
-        if (omap_mcbsp_check(id) < 0)
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
                 return;
-
-#ifdef CONFIG_ARCH_OMAP1
-        if (cpu_class_is_omap1()) {
-                if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3)
-                        omap_mcbsp_dsp_free();
         }
-#endif
-
-#ifdef CONFIG_ARCH_OMAP2
-        if (cpu_is_omap24xx()) {
-                if (id == OMAP_MCBSP1) {
-                        clk_disable(mcbsp1_ick);
-                        clk_disable(mcbsp1_fck);
-                } else {
-                        clk_disable(mcbsp2_ick);
-                        clk_disable(mcbsp2_fck);
-                }
-        }
-#endif
+
+        if (mcbsp[id].pdata->ops->free)
+                mcbsp[id].pdata->ops->free(id);
+
+        clk_disable(mcbsp[id].clk);
 
         spin_lock(&mcbsp[id].lock);
         if (mcbsp[id].free) {
-                printk (KERN_ERR "OMAP-McBSP: McBSP%d was not reserved\n", id + 1);
+                dev_err(mcbsp[id].dev, "McBSP%d was not reserved\n",
+                        mcbsp[id].id);
                 spin_unlock(&mcbsp[id].lock);
                 return;
         }
@@ -384,6 +264,7 @@ void omap_mcbsp_free(unsigned int id)
                 free_irq(mcbsp[id].tx_irq, (void *) (&mcbsp[id]));
         }
 }
+EXPORT_SYMBOL(omap_mcbsp_free);
 
 /*
  * Here we start the McBSP, by enabling the sample
@@ -395,13 +276,15 @@ void omap_mcbsp_start(unsigned int id)
         u32 io_base;
         u16 w;
 
-        if (omap_mcbsp_check(id) < 0)
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
                 return;
+        }
 
         io_base = mcbsp[id].io_base;
 
-        mcbsp[id].rx_word_length = ((OMAP_MCBSP_READ(io_base, RCR1) >> 5) & 0x7);
-        mcbsp[id].tx_word_length = ((OMAP_MCBSP_READ(io_base, XCR1) >> 5) & 0x7);
+        mcbsp[id].rx_word_length = (OMAP_MCBSP_READ(io_base, RCR1) >> 5) & 0x7;
+        mcbsp[id].tx_word_length = (OMAP_MCBSP_READ(io_base, XCR1) >> 5) & 0x7;
 
         /* Start the sample generator */
         w = OMAP_MCBSP_READ(io_base, SPCR2);
@@ -422,20 +305,22 @@ void omap_mcbsp_start(unsigned int id)
 
         /* Dump McBSP Regs */
         omap_mcbsp_dump_reg(id);
-
 }
+EXPORT_SYMBOL(omap_mcbsp_start);
 
 void omap_mcbsp_stop(unsigned int id)
 {
         u32 io_base;
         u16 w;
 
-        if (omap_mcbsp_check(id) < 0)
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
                 return;
+        }
 
         io_base = mcbsp[id].io_base;
 
-        /* Reset transmitter */
+        /* Reset transmitter */
         w = OMAP_MCBSP_READ(io_base, SPCR2);
         OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1));
 
@@ -447,12 +332,19 @@ void omap_mcbsp_stop(unsigned int id)
         w = OMAP_MCBSP_READ(io_base, SPCR2);
         OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1 << 6));
 }
-
+EXPORT_SYMBOL(omap_mcbsp_stop);
 
 /* polled mcbsp i/o operations */
 int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
 {
-        u32 base = mcbsp[id].io_base;
+        u32 base;
+
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+                return -ENODEV;
+        }
+
+        base = mcbsp[id].io_base;
         writew(buf, base + OMAP_MCBSP_REG_DXR1);
         /* if frame sync error - clear the error */
         if (readw(base + OMAP_MCBSP_REG_SPCR2) & XSYNC_ERR) {
@@ -474,18 +366,27 @@ int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
                                        (XRST),
                                        base + OMAP_MCBSP_REG_SPCR2);
                                 udelay(10);
-                                printk(KERN_ERR
-                                       " Could not write to McBSP Register\n");
+                                dev_err(mcbsp[id].dev, "Could not write to"
+                                        " McBSP%d Register\n", mcbsp[id].id);
                                 return -2;
                         }
                 }
         }
+
         return 0;
 }
+EXPORT_SYMBOL(omap_mcbsp_pollwrite);
 
-int omap_mcbsp_pollread(unsigned int id, u16 * buf)
+int omap_mcbsp_pollread(unsigned int id, u16 *buf)
 {
-        u32 base = mcbsp[id].io_base;
+        u32 base;
+
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+                return -ENODEV;
+        }
+
+        base = mcbsp[id].io_base;
         /* if frame sync error - clear the error */
         if (readw(base + OMAP_MCBSP_REG_SPCR1) & RSYNC_ERR) {
                 /* clear error */
@@ -506,15 +407,17 @@ int omap_mcbsp_pollread(unsigned int id, u16 * buf)
                                        (RRST),
                                        base + OMAP_MCBSP_REG_SPCR1);
                                 udelay(10);
-                                printk(KERN_ERR
-                                       " Could not read from McBSP Register\n");
+                                dev_err(mcbsp[id].dev, "Could not read from"
+                                        " McBSP%d Register\n", mcbsp[id].id);
                                 return -2;
                         }
                 }
         }
         *buf = readw(base + OMAP_MCBSP_REG_DRR1);
+
         return 0;
 }
+EXPORT_SYMBOL(omap_mcbsp_pollread);
 
 /*
  * IRQ based word transmission.
@@ -522,12 +425,15 @@ int omap_mcbsp_pollread(unsigned int id, u16 * buf)
 void omap_mcbsp_xmit_word(unsigned int id, u32 word)
 {
         u32 io_base;
-        omap_mcbsp_word_length word_length = mcbsp[id].tx_word_length;
+        omap_mcbsp_word_length word_length;
 
-        if (omap_mcbsp_check(id) < 0)
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
                 return;
+        }
 
         io_base = mcbsp[id].io_base;
+        word_length = mcbsp[id].tx_word_length;
 
         wait_for_completion(&(mcbsp[id].tx_irq_completion));
 
@@ -535,16 +441,20 @@ void omap_mcbsp_xmit_word(unsigned int id, u32 word)
                 OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
         OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
 }
+EXPORT_SYMBOL(omap_mcbsp_xmit_word);
 
 u32 omap_mcbsp_recv_word(unsigned int id)
 {
         u32 io_base;
         u16 word_lsb, word_msb = 0;
-        omap_mcbsp_word_length word_length = mcbsp[id].rx_word_length;
+        omap_mcbsp_word_length word_length;
 
-        if (omap_mcbsp_check(id) < 0)
-                return -EINVAL;
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+                return -ENODEV;
+        }
 
+        word_length = mcbsp[id].rx_word_length;
         io_base = mcbsp[id].io_base;
 
         wait_for_completion(&(mcbsp[id].rx_irq_completion));
@@ -555,15 +465,24 @@ u32 omap_mcbsp_recv_word(unsigned int id)
 
         return (word_lsb | (word_msb << 16));
 }
-
+EXPORT_SYMBOL(omap_mcbsp_recv_word);
 
 int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
 {
-        u32 io_base = mcbsp[id].io_base;
-        omap_mcbsp_word_length tx_word_length = mcbsp[id].tx_word_length;
-        omap_mcbsp_word_length rx_word_length = mcbsp[id].rx_word_length;
+        u32 io_base;
+        omap_mcbsp_word_length tx_word_length;
+        omap_mcbsp_word_length rx_word_length;
         u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
 
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+                return -ENODEV;
+        }
+
+        io_base = mcbsp[id].io_base;
+        tx_word_length = mcbsp[id].tx_word_length;
+        rx_word_length = mcbsp[id].rx_word_length;
+
         if (tx_word_length != rx_word_length)
                 return -EINVAL;
 
@@ -577,7 +496,8 @@ int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
                         udelay(10);
                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
                         udelay(10);
-                        printk("McBSP transmitter not ready\n");
+                        dev_err(mcbsp[id].dev, "McBSP%d transmitter not "
+                                "ready\n", mcbsp[id].id);
                         return -EAGAIN;
                 }
         }
@@ -597,7 +517,8 @@ int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
                         udelay(10);
                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
                         udelay(10);
-                        printk("McBSP receiver not ready\n");
+                        dev_err(mcbsp[id].dev, "McBSP%d receiver not "
+                                "ready\n", mcbsp[id].id);
                         return -EAGAIN;
                 }
         }
@@ -609,14 +530,24 @@ int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
 
         return 0;
 }
+EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
 
-int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word)
+int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
 {
-        u32 io_base = mcbsp[id].io_base, clock_word = 0;
-        omap_mcbsp_word_length tx_word_length = mcbsp[id].tx_word_length;
-        omap_mcbsp_word_length rx_word_length = mcbsp[id].rx_word_length;
+        u32 io_base, clock_word = 0;
+        omap_mcbsp_word_length tx_word_length;
+        omap_mcbsp_word_length rx_word_length;
         u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
 
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+                return -ENODEV;
+        }
+
+        io_base = mcbsp[id].io_base;
+        tx_word_length = mcbsp[id].tx_word_length;
+        rx_word_length = mcbsp[id].rx_word_length;
+
         if (tx_word_length != rx_word_length)
                 return -EINVAL;
 
@@ -630,7 +561,8 @@ int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word)
                         udelay(10);
                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
                         udelay(10);
-                        printk("McBSP transmitter not ready\n");
+                        dev_err(mcbsp[id].dev, "McBSP%d transmitter not "
+                                "ready\n", mcbsp[id].id);
                         return -EAGAIN;
                 }
         }
@@ -650,7 +582,8 @@ int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word)
                         udelay(10);
                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
                         udelay(10);
-                        printk("McBSP receiver not ready\n");
+                        dev_err(mcbsp[id].dev, "McBSP%d receiver not "
+                                "ready\n", mcbsp[id].id);
                         return -EAGAIN;
                 }
         }
@@ -664,7 +597,7 @@ int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word)
 
         return 0;
 }
-
+EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);
 
 /*
  * Simple DMA based buffer rx/tx routines.
@@ -673,25 +606,32 @@ int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word)
  * For anything fancier, you should use your own customized DMA
  * routines and callbacks.
  */
-int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length)
+int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer,
+                                unsigned int length)
 {
         int dma_tx_ch;
         int src_port = 0;
         int dest_port = 0;
         int sync_dev = 0;
 
-        if (omap_mcbsp_check(id) < 0)
-                return -EINVAL;
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+                return -ENODEV;
+        }
 
-        if (omap_request_dma(mcbsp[id].dma_tx_sync, "McBSP TX", omap_mcbsp_tx_dma_callback,
-                             &mcbsp[id],
-                             &dma_tx_ch)) {
-                printk("OMAP-McBSP: Unable to request DMA channel for McBSP%d TX. Trying IRQ based TX\n", id+1);
+        if (omap_request_dma(mcbsp[id].dma_tx_sync, "McBSP TX",
+                                omap_mcbsp_tx_dma_callback,
+                                &mcbsp[id],
+                                &dma_tx_ch)) {
+                dev_err(mcbsp[id].dev, " Unable to request DMA channel for "
+                                "McBSP%d TX. Trying IRQ based TX\n",
+                                mcbsp[id].id);
                 return -EAGAIN;
         }
         mcbsp[id].dma_tx_lch = dma_tx_ch;
 
-        DBG("TX DMA on channel %d\n", dma_tx_ch);
+        dev_err(mcbsp[id].dev, "McBSP%d TX DMA on channel %d\n", mcbsp[id].id,
+                dma_tx_ch);
 
         init_completion(&(mcbsp[id].tx_dma_completion));
 
@@ -699,7 +639,7 @@ int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int leng
                 src_port = OMAP_DMA_PORT_TIPB;
                 dest_port = OMAP_DMA_PORT_EMIFF;
         }
-        if (cpu_is_omap24xx())
+        if (cpu_class_is_omap2())
                 sync_dev = mcbsp[id].dma_tx_sync;
 
         omap_set_dma_transfer_params(mcbsp[id].dma_tx_lch,
@@ -722,29 +662,37 @@ int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int leng
 
         omap_start_dma(mcbsp[id].dma_tx_lch);
         wait_for_completion(&(mcbsp[id].tx_dma_completion));
+
         return 0;
 }
+EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
 
-
-int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length)
+int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer,
+                                unsigned int length)
 {
         int dma_rx_ch;
         int src_port = 0;
         int dest_port = 0;
         int sync_dev = 0;
 
-        if (omap_mcbsp_check(id) < 0)
-                return -EINVAL;
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+                return -ENODEV;
+        }
 
-        if (omap_request_dma(mcbsp[id].dma_rx_sync, "McBSP RX", omap_mcbsp_rx_dma_callback,
-                             &mcbsp[id],
-                             &dma_rx_ch)) {
-                printk("Unable to request DMA channel for McBSP%d RX. Trying IRQ based RX\n", id+1);
+        if (omap_request_dma(mcbsp[id].dma_rx_sync, "McBSP RX",
+                                omap_mcbsp_rx_dma_callback,
+                                &mcbsp[id],
+                                &dma_rx_ch)) {
+                dev_err(mcbsp[id].dev, "Unable to request DMA channel for "
+                                "McBSP%d RX. Trying IRQ based RX\n",
+                                mcbsp[id].id);
                 return -EAGAIN;
         }
         mcbsp[id].dma_rx_lch = dma_rx_ch;
 
-        DBG("RX DMA on channel %d\n", dma_rx_ch);
+        dev_err(mcbsp[id].dev, "McBSP%d RX DMA on channel %d\n", mcbsp[id].id,
+                dma_rx_ch);
 
         init_completion(&(mcbsp[id].rx_dma_completion));
 
@@ -752,14 +700,14 @@ int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int leng
                 src_port = OMAP_DMA_PORT_TIPB;
                 dest_port = OMAP_DMA_PORT_EMIFF;
         }
-        if (cpu_is_omap24xx())
+        if (cpu_class_is_omap2())
                 sync_dev = mcbsp[id].dma_rx_sync;
 
         omap_set_dma_transfer_params(mcbsp[id].dma_rx_lch,
-                                     OMAP_DMA_DATA_TYPE_S16,
-                                     length >> 1, 1,
-                                     OMAP_DMA_SYNC_ELEMENT,
-         sync_dev, 0);
+                                        OMAP_DMA_DATA_TYPE_S16,
+                                        length >> 1, 1,
+                                        OMAP_DMA_SYNC_ELEMENT,
+                                        sync_dev, 0);
 
         omap_set_dma_src_params(mcbsp[id].dma_rx_lch,
                                 src_port,
@@ -768,16 +716,17 @@ int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int leng
                                 0, 0);
 
         omap_set_dma_dest_params(mcbsp[id].dma_rx_lch,
-                                 dest_port,
-                                 OMAP_DMA_AMODE_POST_INC,
-                                 buffer,
-                                 0, 0);
+                                        dest_port,
+                                        OMAP_DMA_AMODE_POST_INC,
+                                        buffer,
+                                        0, 0);
 
         omap_start_dma(mcbsp[id].dma_rx_lch);
         wait_for_completion(&(mcbsp[id].rx_dma_completion));
+
         return 0;
 }
-
+EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
 
 /*
  * SPI wrapper.
@@ -785,12 +734,15 @@ int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int leng
  * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
  * Once this is done, you can call omap_mcbsp_start().
  */
-void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg)
+void omap_mcbsp_set_spi_mode(unsigned int id,
+                                const struct omap_mcbsp_spi_cfg *spi_cfg)
 {
         struct omap_mcbsp_reg_cfg mcbsp_cfg;
 
-        if (omap_mcbsp_check(id) < 0)
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
                 return;
+        }
 
         memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
 
@@ -798,7 +750,7 @@ void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg *
         mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0));
         mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0));
 
-        /* Clock stop mode */
+        /* Clock stop mode */
         if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY)
                 mcbsp_cfg.spcr1 |= (1 << 12);
         else
@@ -827,13 +779,12 @@ void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg *
 
         if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) {
                 mcbsp_cfg.pcr0 |= CLKXM;
-                mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div -1);
+                mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div - 1);
                 mcbsp_cfg.pcr0 |= FSXM;
                 mcbsp_cfg.srgr2 &= ~FSGM;
                 mcbsp_cfg.xcr2 |= XDATDLY(1);
                 mcbsp_cfg.rcr2 |= RDATDLY(1);
-        }
-        else {
+        } else {
                 mcbsp_cfg.pcr0 &= ~CLKXM;
                 mcbsp_cfg.srgr1 |= CLKGDV(1);
                 mcbsp_cfg.pcr0 &= ~FSXM;
@@ -846,199 +797,99 @@ void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg *
 
         omap_mcbsp_config(id, &mcbsp_cfg);
 }
-
+EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
 
 /*
  * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
  * 730 has only 2 McBSP, and both of them are MPU peripherals.
  */
-struct omap_mcbsp_info {
-        u32 virt_base;
-        u8 dma_rx_sync, dma_tx_sync;
-        u16 rx_irq, tx_irq;
-};
+static int __init omap_mcbsp_probe(struct platform_device *pdev)
+{
+        struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
+        int id = pdev->id - 1;
+        int ret = 0;
 
-#ifdef CONFIG_ARCH_OMAP730
-static const struct omap_mcbsp_info mcbsp_730[] = {
-        [0] = { .virt_base = io_p2v(OMAP730_MCBSP1_BASE),
-                .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
-                .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
-                .rx_irq = INT_730_McBSP1RX,
-                .tx_irq = INT_730_McBSP1TX },
-        [1] = { .virt_base = io_p2v(OMAP730_MCBSP2_BASE),
-                .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
-                .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
-                .rx_irq = INT_730_McBSP2RX,
-                .tx_irq = INT_730_McBSP2TX },
-};
-#endif
-
-#ifdef CONFIG_ARCH_OMAP15XX
-static const struct omap_mcbsp_info mcbsp_1510[] = {
-        [0] = { .virt_base = OMAP1510_MCBSP1_BASE,
-                .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
-                .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
-                .rx_irq = INT_McBSP1RX,
-                .tx_irq = INT_McBSP1TX },
-        [1] = { .virt_base = io_p2v(OMAP1510_MCBSP2_BASE),
-                .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
-                .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
-                .rx_irq = INT_1510_SPI_RX,
-                .tx_irq = INT_1510_SPI_TX },
-        [2] = { .virt_base = OMAP1510_MCBSP3_BASE,
-                .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
-                .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
-                .rx_irq = INT_McBSP3RX,
-                .tx_irq = INT_McBSP3TX },
-};
-#endif
-
-#if defined(CONFIG_ARCH_OMAP16XX)
-static const struct omap_mcbsp_info mcbsp_1610[] = {
-        [0] = { .virt_base = OMAP1610_MCBSP1_BASE,
-                .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
-                .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
-                .rx_irq = INT_McBSP1RX,
-                .tx_irq = INT_McBSP1TX },
-        [1] = { .virt_base = io_p2v(OMAP1610_MCBSP2_BASE),
-                .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
-                .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
-                .rx_irq = INT_1610_McBSP2_RX,
-                .tx_irq = INT_1610_McBSP2_TX },
-        [2] = { .virt_base = OMAP1610_MCBSP3_BASE,
-                .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
-                .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
-                .rx_irq = INT_McBSP3RX,
-                .tx_irq = INT_McBSP3TX },
-};
-#endif
-
-#if defined(CONFIG_ARCH_OMAP24XX)
-static const struct omap_mcbsp_info mcbsp_24xx[] = {
-        [0] = { .virt_base = IO_ADDRESS(OMAP24XX_MCBSP1_BASE),
-                .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
-                .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
-                .rx_irq = INT_24XX_MCBSP1_IRQ_RX,
-                .tx_irq = INT_24XX_MCBSP1_IRQ_TX,
-                },
-        [1] = { .virt_base = IO_ADDRESS(OMAP24XX_MCBSP2_BASE),
-                .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
-                .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
-                .rx_irq = INT_24XX_MCBSP2_IRQ_RX,
-                .tx_irq = INT_24XX_MCBSP2_IRQ_TX,
-                },
-};
-#endif
+        if (!pdata) {
+                dev_err(&pdev->dev, "McBSP device initialized without"
+                                "platform data\n");
+                ret = -EINVAL;
+                goto exit;
+        }
+
+        dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id);
+
+        if (id >= OMAP_MAX_MCBSP_COUNT) {
+                dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id);
+                ret = -EINVAL;
+                goto exit;
+        }
+
+        spin_lock_init(&mcbsp[id].lock);
+        mcbsp[id].id = id + 1;
+        mcbsp[id].free = 1;
+        mcbsp[id].dma_tx_lch = -1;
+        mcbsp[id].dma_rx_lch = -1;
+
+        mcbsp[id].io_base = pdata->virt_base;
+        /* Default I/O is IRQ based */
+        mcbsp[id].io_type = OMAP_MCBSP_IRQ_IO;
+        mcbsp[id].tx_irq = pdata->tx_irq;
+        mcbsp[id].rx_irq = pdata->rx_irq;
+        mcbsp[id].dma_rx_sync = pdata->dma_rx_sync;
+        mcbsp[id].dma_tx_sync = pdata->dma_tx_sync;
+
+        if (pdata->clk_name)
+                mcbsp[id].clk = clk_get(&pdev->dev, pdata->clk_name);
+        if (IS_ERR(mcbsp[id].clk)) {
+                mcbsp[id].free = 0;
+                dev_err(&pdev->dev,
+                        "Invalid clock configuration for McBSP%d.\n",
+                        mcbsp[id].id);
+                ret = -EINVAL;
+                goto exit;
+        }
+
+        mcbsp[id].pdata = pdata;
+        mcbsp[id].dev = &pdev->dev;
+        platform_set_drvdata(pdev, &mcbsp[id]);
+
+exit:
+        return ret;
+}
 
-static int __init omap_mcbsp_init(void)
+static int omap_mcbsp_remove(struct platform_device *pdev)
 {
-        int mcbsp_count = 0, i;
-        static const struct omap_mcbsp_info *mcbsp_info;
+        struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
 
-        printk("Initializing OMAP McBSP system\n");
+        platform_set_drvdata(pdev, NULL);
+        if (mcbsp) {
 
-#ifdef CONFIG_ARCH_OMAP1
-        mcbsp_dsp_ck = clk_get(0, "dsp_ck");
-        if (IS_ERR(mcbsp_dsp_ck)) {
-                printk(KERN_ERR "mcbsp: could not acquire dsp_ck handle.\n");
-                return PTR_ERR(mcbsp_dsp_ck);
-        }
-        mcbsp_api_ck = clk_get(0, "api_ck");
-        if (IS_ERR(mcbsp_api_ck)) {
-                printk(KERN_ERR "mcbsp: could not acquire api_ck handle.\n");
-                return PTR_ERR(mcbsp_api_ck);
-        }
-        mcbsp_dspxor_ck = clk_get(0, "dspxor_ck");
-        if (IS_ERR(mcbsp_dspxor_ck)) {
-                printk(KERN_ERR "mcbsp: could not acquire dspxor_ck handle.\n");
-                return PTR_ERR(mcbsp_dspxor_ck);
-        }
-#endif
-#ifdef CONFIG_ARCH_OMAP2
-        mcbsp1_ick = clk_get(0, "mcbsp1_ick");
-        if (IS_ERR(mcbsp1_ick)) {
-                printk(KERN_ERR "mcbsp: could not acquire mcbsp1_ick handle.\n");
-                return PTR_ERR(mcbsp1_ick);
-        }
-        mcbsp1_fck = clk_get(0, "mcbsp1_fck");
-        if (IS_ERR(mcbsp1_fck)) {
-                printk(KERN_ERR "mcbsp: could not acquire mcbsp1_fck handle.\n");
-                return PTR_ERR(mcbsp1_fck);
-        }
-        mcbsp2_ick = clk_get(0, "mcbsp2_ick");
-        if (IS_ERR(mcbsp2_ick)) {
-                printk(KERN_ERR "mcbsp: could not acquire mcbsp2_ick handle.\n");
-                return PTR_ERR(mcbsp2_ick);
-        }
-        mcbsp2_fck = clk_get(0, "mcbsp2_fck");
-        if (IS_ERR(mcbsp2_fck)) {
-                printk(KERN_ERR "mcbsp: could not acquire mcbsp2_fck handle.\n");
-                return PTR_ERR(mcbsp2_fck);
-        }
-#endif
+                if (mcbsp->pdata && mcbsp->pdata->ops &&
+                                mcbsp->pdata->ops->free)
+                        mcbsp->pdata->ops->free(mcbsp->id);
 
-#ifdef CONFIG_ARCH_OMAP730
-        if (cpu_is_omap730()) {
-                mcbsp_info = mcbsp_730;
-                mcbsp_count = ARRAY_SIZE(mcbsp_730);
-        }
-#endif
-#ifdef CONFIG_ARCH_OMAP15XX
-        if (cpu_is_omap15xx()) {
-                mcbsp_info = mcbsp_1510;
-                mcbsp_count = ARRAY_SIZE(mcbsp_1510);
-        }
-#endif
-#if defined(CONFIG_ARCH_OMAP16XX)
-        if (cpu_is_omap16xx()) {
-                mcbsp_info = mcbsp_1610;
-                mcbsp_count = ARRAY_SIZE(mcbsp_1610);
-        }
-#endif
-#if defined(CONFIG_ARCH_OMAP24XX)
-        if (cpu_is_omap24xx()) {
-                mcbsp_info = mcbsp_24xx;
-                mcbsp_count = ARRAY_SIZE(mcbsp_24xx);
-                omap2_mcbsp2_mux_setup();
-        }
-#endif
-        for (i = 0; i < OMAP_MAX_MCBSP_COUNT ; i++) {
-                if (i >= mcbsp_count) {
-                        mcbsp[i].io_base = 0;
-                        mcbsp[i].free = 0;
-                        continue;
-                }
-                mcbsp[i].id = i + 1;
-                mcbsp[i].free = 1;
-                mcbsp[i].dma_tx_lch = -1;
-                mcbsp[i].dma_rx_lch = -1;
-
-                mcbsp[i].io_base = mcbsp_info[i].virt_base;
-                mcbsp[i].io_type = OMAP_MCBSP_IRQ_IO; /* Default I/O is IRQ based */
-                mcbsp[i].tx_irq = mcbsp_info[i].tx_irq;
-                mcbsp[i].rx_irq = mcbsp_info[i].rx_irq;
-                mcbsp[i].dma_rx_sync = mcbsp_info[i].dma_rx_sync;
-                mcbsp[i].dma_tx_sync = mcbsp_info[i].dma_tx_sync;
-                spin_lock_init(&mcbsp[i].lock);
+                clk_disable(mcbsp->clk);
+                clk_put(mcbsp->clk);
+
+                mcbsp->clk = NULL;
+                mcbsp->free = 0;
+                mcbsp->dev = NULL;
         }
 
         return 0;
 }
 
-arch_initcall(omap_mcbsp_init);
+static struct platform_driver omap_mcbsp_driver = {
+        .probe          = omap_mcbsp_probe,
+        .remove         = omap_mcbsp_remove,
+        .driver         = {
+                .name   = "omap-mcbsp",
+        },
+};
+
+int __init omap_mcbsp_init(void)
+{
+        /* Register the McBSP driver */
+        return platform_driver_register(&omap_mcbsp_driver);
+}
 
-EXPORT_SYMBOL(omap_mcbsp_config);
-EXPORT_SYMBOL(omap_mcbsp_request);
-EXPORT_SYMBOL(omap_mcbsp_set_io_type);
-EXPORT_SYMBOL(omap_mcbsp_free);
-EXPORT_SYMBOL(omap_mcbsp_start);
-EXPORT_SYMBOL(omap_mcbsp_stop);
-EXPORT_SYMBOL(omap_mcbsp_pollread);
-EXPORT_SYMBOL(omap_mcbsp_pollwrite);
-EXPORT_SYMBOL(omap_mcbsp_xmit_word);
-EXPORT_SYMBOL(omap_mcbsp_recv_word);
-EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
-EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
-EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
-EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);
-EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 1f23f0459e5f..554ee58e1294 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -10,6 +10,7 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
+#undef DEBUG
 
 #include <linux/module.h>
 #include <linux/kernel.h>
@@ -24,25 +25,43 @@
 #include <asm/arch/sram.h>
 #include <asm/arch/board.h>
 
+#include <asm/arch/control.h>
+
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+# include "../mach-omap2/prm.h"
+# include "../mach-omap2/cm.h"
+# include "../mach-omap2/sdrc.h"
+#endif
+
 #define OMAP1_SRAM_PA           0x20000000
-#define OMAP1_SRAM_VA           0xd0000000
+#define OMAP1_SRAM_VA           VMALLOC_END
 #define OMAP2_SRAM_PA           0x40200000
 #define OMAP2_SRAM_PUB_PA       0x4020f800
-#define OMAP2_SRAM_VA           0xd0000000
-#define OMAP2_SRAM_PUB_VA       0xd0000800
-
-#if defined(CONFIG_ARCH_OMAP24XX)
+#define OMAP2_SRAM_VA           VMALLOC_END
+#define OMAP2_SRAM_PUB_VA       (VMALLOC_END + 0x800)
+#define OMAP3_SRAM_PA           0x40200000
+#define OMAP3_SRAM_VA           0xd7000000
+#define OMAP3_SRAM_PUB_PA       0x40208000
+#define OMAP3_SRAM_PUB_VA       0xd7008000
+
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
 #define SRAM_BOOTLOADER_SZ      0x00
 #else
 #define SRAM_BOOTLOADER_SZ      0x80
 #endif
 
-#define VA_REQINFOPERM0         IO_ADDRESS(0x68005048)
-#define VA_READPERM0            IO_ADDRESS(0x68005050)
-#define VA_WRITEPERM0           IO_ADDRESS(0x68005058)
-#define VA_CONTROL_STAT         IO_ADDRESS(0x480002F8)
+#define OMAP24XX_VA_REQINFOPERM0        IO_ADDRESS(0x68005048)
+#define OMAP24XX_VA_READPERM0           IO_ADDRESS(0x68005050)
+#define OMAP24XX_VA_WRITEPERM0          IO_ADDRESS(0x68005058)
+
+#define OMAP34XX_VA_REQINFOPERM0        IO_ADDRESS(0x68012848)
+#define OMAP34XX_VA_READPERM0           IO_ADDRESS(0x68012850)
+#define OMAP34XX_VA_WRITEPERM0          IO_ADDRESS(0x68012858)
+#define OMAP34XX_VA_ADDR_MATCH2         IO_ADDRESS(0x68012880)
+#define OMAP34XX_VA_SMS_RG_ATT0         IO_ADDRESS(0x6C000048)
+#define OMAP34XX_VA_CONTROL_STAT        IO_ADDRESS(0x480022F0)
+
 #define GP_DEVICE               0x300
-#define TYPE_MASK               0x700
 
 #define ROUND_DOWN(value,boundary)      ((value) & (~((boundary)-1)))
 
@@ -68,14 +87,21 @@ static int is_sram_locked(void)
         int type = 0;
 
         if (cpu_is_omap242x())
-                type = __raw_readl(VA_CONTROL_STAT) & TYPE_MASK;
+                type = system_rev & OMAP2_DEVICETYPE_MASK;
 
         if (type == GP_DEVICE) {
                 /* RAMFW: R/W access to all initiators for all qualifier sets */
                 if (cpu_is_omap242x()) {
-                        __raw_writel(0xFF, VA_REQINFOPERM0); /* all q-vects */
-                        __raw_writel(0xCFDE, VA_READPERM0);  /* all i-read */
-                        __raw_writel(0xCFDE, VA_WRITEPERM0); /* all i-write */
+                        __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
+                        __raw_writel(0xCFDE, OMAP24XX_VA_READPERM0);  /* all i-read */
+                        __raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
+                }
+                if (cpu_is_omap34xx()) {
+                        __raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
+                        __raw_writel(0xFFFF, OMAP34XX_VA_READPERM0);  /* all i-read */
+                        __raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
+                        __raw_writel(0x0, OMAP34XX_VA_ADDR_MATCH2);
+                        __raw_writel(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
                 }
                 return 0;
         } else
@@ -92,18 +118,30 @@ void __init omap_detect_sram(void)
 {
         unsigned long reserved;
 
-        if (cpu_is_omap24xx()) {
+        if (cpu_class_is_omap2()) {
                 if (is_sram_locked()) {
-                        omap_sram_base = OMAP2_SRAM_PUB_VA;
-                        omap_sram_start = OMAP2_SRAM_PUB_PA;
-                        omap_sram_size = 0x800; /* 2K */
+                        if (cpu_is_omap34xx()) {
+                                omap_sram_base = OMAP3_SRAM_PUB_VA;
+                                omap_sram_start = OMAP3_SRAM_PUB_PA;
+                                omap_sram_size = 0x8000; /* 32K */
+                        } else {
+                                omap_sram_base = OMAP2_SRAM_PUB_VA;
+                                omap_sram_start = OMAP2_SRAM_PUB_PA;
+                                omap_sram_size = 0x800; /* 2K */
+                        }
                 } else {
-                        omap_sram_base = OMAP2_SRAM_VA;
-                        omap_sram_start = OMAP2_SRAM_PA;
-                        if (cpu_is_omap242x())
-                                omap_sram_size = 0xa0000; /* 640K */
-                        else if (cpu_is_omap243x())
+                        if (cpu_is_omap34xx()) {
+                                omap_sram_base = OMAP3_SRAM_VA;
+                                omap_sram_start = OMAP3_SRAM_PA;
                                 omap_sram_size = 0x10000; /* 64K */
+                        } else {
+                                omap_sram_base = OMAP2_SRAM_VA;
+                                omap_sram_start = OMAP2_SRAM_PA;
+                                if (cpu_is_omap242x())
+                                        omap_sram_size = 0xa0000; /* 640K */
+                                else if (cpu_is_omap243x())
+                                        omap_sram_size = 0x10000; /* 64K */
+                        }
                 }
         } else {
                 omap_sram_base = OMAP1_SRAM_VA;
@@ -157,6 +195,13 @@ void __init omap_map_sram(void)
                 omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
         }
 
+        if (cpu_is_omap34xx()) {
+                omap_sram_io_desc[0].virtual = OMAP3_SRAM_VA;
+                base = OMAP3_SRAM_PA;
+                base = ROUND_DOWN(base, PAGE_SIZE);
+                omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
+        }
+
         omap_sram_io_desc[0].length = 1024 * 1024;      /* Use section desc */
         iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc));
 
@@ -191,6 +236,7 @@ void * omap_sram_push(void * start, unsigned long size)
         omap_sram_ceil -= size;
         omap_sram_ceil = ROUND_DOWN(omap_sram_ceil, sizeof(void *));
         memcpy((void *)omap_sram_ceil, start, size);
+        flush_icache_range((unsigned long)start, (unsigned long)(start + size));
 
         return (void *)omap_sram_ceil;
 }
@@ -214,8 +260,9 @@ void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
 
 int __init omap1_sram_init(void)
 {
-        _omap_sram_reprogram_clock = omap_sram_push(sram_reprogram_clock,
-                                                    sram_reprogram_clock_sz);
+        _omap_sram_reprogram_clock =
+                        omap_sram_push(omap1_sram_reprogram_clock,
+                                        omap1_sram_reprogram_clock_sz);
 
         return 0;
 }
@@ -224,7 +271,7 @@ int __init omap1_sram_init(void)
 #define omap1_sram_init()       do {} while (0)
 #endif
 
-#ifdef CONFIG_ARCH_OMAP2
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
 
 static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
                               u32 base_cs, u32 force_unlock);
@@ -259,19 +306,109 @@ u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
 
         return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
 }
+#endif
+
+#ifdef CONFIG_ARCH_OMAP2420
+int __init omap242x_sram_init(void)
+{
+        _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
+                                        omap242x_sram_ddr_init_sz);
+
+        _omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc,
+                                            omap242x_sram_reprogram_sdrc_sz);
+
+        _omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm,
+                                         omap242x_sram_set_prcm_sz);
+
+        return 0;
+}
+#else
+static inline int omap242x_sram_init(void)
+{
+        return 0;
+}
+#endif
+
+#ifdef CONFIG_ARCH_OMAP2430
+int __init omap243x_sram_init(void)
+{
+        _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
+                                        omap243x_sram_ddr_init_sz);
+
+        _omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc,
+                                            omap243x_sram_reprogram_sdrc_sz);
+
+        _omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm,
+                                         omap243x_sram_set_prcm_sz);
+
+        return 0;
+}
+#else
+static inline int omap243x_sram_init(void)
+{
+        return 0;
+}
+#endif
+
+#ifdef CONFIG_ARCH_OMAP3
+
+static u32 (*_omap2_sram_reprogram_gpmc)(u32 perf_level);
+u32 omap2_sram_reprogram_gpmc(u32 perf_level)
+{
+        if (!_omap2_sram_reprogram_gpmc)
+                omap_sram_error();
+
+        return _omap2_sram_reprogram_gpmc(perf_level);
+}
+
+static u32 (*_omap2_sram_configure_core_dpll)(u32 m, u32 n,
+                                                u32 freqsel, u32 m2);
+u32 omap2_sram_configure_core_dpll(u32 m, u32 n, u32 freqsel, u32 m2)
+{
+        if (!_omap2_sram_configure_core_dpll)
+                omap_sram_error();
+
+        return _omap2_sram_configure_core_dpll(m, n, freqsel, m2);
+}
 
-int __init omap2_sram_init(void)
+/* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */
+void restore_sram_functions(void)
 {
-        _omap2_sram_ddr_init = omap_sram_push(sram_ddr_init, sram_ddr_init_sz);
+        omap_sram_ceil = omap_sram_base + omap_sram_size;
 
-        _omap2_sram_reprogram_sdrc = omap_sram_push(sram_reprogram_sdrc,
-                                                    sram_reprogram_sdrc_sz);
-        _omap2_set_prcm = omap_sram_push(sram_set_prcm, sram_set_prcm_sz);
+        _omap2_sram_reprogram_gpmc = omap_sram_push(omap34xx_sram_reprogram_gpmc,
+                omap34xx_sram_reprogram_gpmc_sz);
+
+        _omap2_sram_configure_core_dpll =
+                        omap_sram_push(omap34xx_sram_configure_core_dpll,
+                                        omap34xx_sram_configure_core_dpll_sz);
+}
+
+int __init omap34xx_sram_init(void)
+{
+        _omap2_sram_ddr_init = omap_sram_push(omap34xx_sram_ddr_init,
+                                        omap34xx_sram_ddr_init_sz);
+
+        _omap2_sram_reprogram_sdrc = omap_sram_push(omap34xx_sram_reprogram_sdrc,
+                                        omap34xx_sram_reprogram_sdrc_sz);
+
+        _omap2_set_prcm = omap_sram_push(omap34xx_sram_set_prcm,
+                                        omap34xx_sram_set_prcm_sz);
+
+        _omap2_sram_reprogram_gpmc = omap_sram_push(omap34xx_sram_reprogram_gpmc,
+                                        omap34xx_sram_reprogram_gpmc_sz);
+
+        _omap2_sram_configure_core_dpll =
+                                omap_sram_push(omap34xx_sram_configure_core_dpll,
+                                        omap34xx_sram_configure_core_dpll_sz);
 
         return 0;
 }
 #else
-#define omap2_sram_init()       do {} while (0)
+static inline int omap34xx_sram_init(void)
+{
+        return 0;
+}
 #endif
 
 int __init omap_sram_init(void)
@@ -279,10 +416,14 @@ int __init omap_sram_init(void)
         omap_detect_sram();
         omap_map_sram();
 
-        if (!cpu_is_omap24xx())
+        if (!(cpu_class_is_omap2()))
                 omap1_sram_init();
-        else
-                omap2_sram_init();
+        else if (cpu_is_omap242x())
+                omap242x_sram_init();
+        else if (cpu_is_omap2430())
+                omap243x_sram_init();
+        else if (cpu_is_omap34xx())
+                omap34xx_sram_init();
 
         return 0;
 }
diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c
index a619475c4b76..2699c16d4da0 100644
--- a/arch/arm/plat-omap/usb.c
+++ b/arch/arm/plat-omap/usb.c
@@ -1,4 +1,4 @@
-/*
+ /*
  * arch/arm/plat-omap/usb.c -- platform level USB initialization
  *
  * Copyright (C) 2004 Texas Instruments, Inc.
@@ -156,8 +156,12 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
 
         if (nwires == 0) {
                 if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
+                        u32 l;
+
                         /* pulldown D+/D- */
-                        USB_TRANSCEIVER_CTRL_REG &= ~(3 << 1);
+                        l = omap_readl(USB_TRANSCEIVER_CTRL);
+                        l &= ~(3 << 1);
+                        omap_writel(l, USB_TRANSCEIVER_CTRL);
                 }
                 return 0;
         }
@@ -171,6 +175,8 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
 
         /* internal transceiver (unavailable on 17xx, 24xx) */
         if (!cpu_class_is_omap2() && nwires == 2) {
+                u32 l;
+
                 // omap_cfg_reg(P9_USB_DP);
                 // omap_cfg_reg(R8_USB_DM);
 
@@ -185,9 +191,11 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
                  *  - OTG support on this port not yet written
                  */
 
-                USB_TRANSCEIVER_CTRL_REG &= ~(7 << 4);
+                l = omap_readl(USB_TRANSCEIVER_CTRL);
+                l &= ~(7 << 4);
                 if (!is_device)
-                        USB_TRANSCEIVER_CTRL_REG |= (3 << 1);
+                        l |= (3 << 1);
+                omap_writel(l, USB_TRANSCEIVER_CTRL);
 
                 return 3 << 16;
         }
@@ -217,8 +225,13 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
          * with VBUS switching and overcurrent detection.
          */
 
-        if (cpu_class_is_omap1() && nwires != 6)
-                USB_TRANSCEIVER_CTRL_REG &= ~CONF_USB2_UNI_R;
+        if (cpu_class_is_omap1() && nwires != 6) {
+                u32 l;
+
+                l = omap_readl(USB_TRANSCEIVER_CTRL);
+                l &= ~CONF_USB2_UNI_R;
+                omap_writel(l, USB_TRANSCEIVER_CTRL);
+        }
 
         switch (nwires) {
         case 3:
@@ -238,9 +251,13 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
                         omap_cfg_reg(K20_24XX_USB0_VM);
                         omap2_usb_devconf_set(0, USB_UNIDIR);
                 } else {
+                        u32 l;
+
                         omap_cfg_reg(AA9_USB0_VP);
                         omap_cfg_reg(R9_USB0_VM);
-                        USB_TRANSCEIVER_CTRL_REG |= CONF_USB2_UNI_R;
+                        l = omap_readl(USB_TRANSCEIVER_CTRL);
+                        l |= CONF_USB2_UNI_R;
+                        omap_writel(l, USB_TRANSCEIVER_CTRL);
                 }
                 break;
         default:
@@ -254,8 +271,13 @@ static u32 __init omap_usb1_init(unsigned nwires)
 {
         u32     syscon1 = 0;
 
-        if (cpu_class_is_omap1() && !cpu_is_omap15xx() && nwires != 6)
-                USB_TRANSCEIVER_CTRL_REG &= ~CONF_USB1_UNI_R;
+        if (cpu_class_is_omap1() && !cpu_is_omap15xx() && nwires != 6) {
+                u32 l;
+
+                l = omap_readl(USB_TRANSCEIVER_CTRL);
+                l &= ~CONF_USB1_UNI_R;
+                omap_writel(l, USB_TRANSCEIVER_CTRL);
+        }
         if (cpu_is_omap24xx())
                 omap2_usb_devconf_clear(1, USB_BIDIR_TLL);
 
@@ -316,8 +338,13 @@ static u32 __init omap_usb1_init(unsigned nwires)
                 syscon1 = 3;
                 omap_cfg_reg(USB1_VP);
                 omap_cfg_reg(USB1_VM);
-                if (!cpu_is_omap15xx())
-                        USB_TRANSCEIVER_CTRL_REG |= CONF_USB1_UNI_R;
+                if (!cpu_is_omap15xx()) {
+                        u32 l;
+
+                        l = omap_readl(USB_TRANSCEIVER_CTRL);
+                        l |= CONF_USB1_UNI_R;
+                        omap_writel(l, USB_TRANSCEIVER_CTRL);
+                }
                 break;
         default:
 bad:
@@ -340,8 +367,13 @@ static u32 __init omap_usb2_init(unsigned nwires, unsigned alt_pingroup)
         if (alt_pingroup || nwires == 0)
                 return 0;
 
-        if (cpu_class_is_omap1() && !cpu_is_omap15xx() && nwires != 6)
-                USB_TRANSCEIVER_CTRL_REG &= ~CONF_USB2_UNI_R;
+        if (cpu_class_is_omap1() && !cpu_is_omap15xx() && nwires != 6) {
+                u32 l;
+
+                l = omap_readl(USB_TRANSCEIVER_CTRL);
+                l &= ~CONF_USB2_UNI_R;
+                omap_writel(l, USB_TRANSCEIVER_CTRL);
+        }
 
         /* external transceiver */
         if (cpu_is_omap15xx()) {
@@ -410,9 +442,13 @@ static u32 __init omap_usb2_init(unsigned nwires, unsigned alt_pingroup)
                         omap_cfg_reg(USB2_VP);
                         omap_cfg_reg(USB2_VM);
                 } else {
+                        u32 l;
+
                         omap_cfg_reg(AA9_USB2_VP);
                         omap_cfg_reg(R9_USB2_VM);
-                        USB_TRANSCEIVER_CTRL_REG |= CONF_USB2_UNI_R;
+                        l = omap_readl(USB_TRANSCEIVER_CTRL);
+                        l |= CONF_USB2_UNI_R;
+                        omap_writel(l, USB_TRANSCEIVER_CTRL);
                 }
                 break;
         default:
@@ -531,10 +567,6 @@ static struct platform_device otg_device = {
 
 /*-------------------------------------------------------------------------*/
 
-#define ULPD_CLOCK_CTRL_REG     __REG16(ULPD_CLOCK_CTRL)
-#define ULPD_SOFT_REQ_REG       __REG16(ULPD_SOFT_REQ)
-
-
 // FIXME correct answer depends on hmc_mode,
 // as does (on omap1) any nonzero value for config->otg port number
 #ifdef  CONFIG_USB_GADGET_OMAP
@@ -550,17 +582,17 @@ static struct platform_device otg_device = {
 void __init
 omap_otg_init(struct omap_usb_config *config)
 {
-        u32             syscon = OTG_SYSCON_1_REG & 0xffff;
+        u32             syscon;
         int             status;
         int             alt_pingroup = 0;
 
         /* NOTE:  no bus or clock setup (yet?) */
 
-        syscon = OTG_SYSCON_1_REG & 0xffff;
+        syscon = omap_readl(OTG_SYSCON_1) & 0xffff;
         if (!(syscon & OTG_RESET_DONE))
                 pr_debug("USB resets not complete?\n");
 
-        // OTG_IRQ_EN_REG = 0;
+        //omap_writew(0, OTG_IRQ_EN);
 
         /* pin muxing and transceiver pinouts */
         if (config->pins[0] > 2)        /* alt pingroup 2 */
@@ -568,8 +600,8 @@ omap_otg_init(struct omap_usb_config *config)
         syscon |= omap_usb0_init(config->pins[0], is_usb0_device(config));
         syscon |= omap_usb1_init(config->pins[1]);
         syscon |= omap_usb2_init(config->pins[2], alt_pingroup);
-        pr_debug("OTG_SYSCON_1_REG = %08x\n", syscon);
-        OTG_SYSCON_1_REG = syscon;
+        pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1));
+        omap_writel(syscon, OTG_SYSCON_1);
 
         syscon = config->hmc_mode;
         syscon |= USBX_SYNCHRO | (4 << 16) /* B_ASE0_BRST */;
@@ -578,9 +610,10 @@ omap_otg_init(struct omap_usb_config *config)
                 syscon |= OTG_EN;
 #endif
         if (cpu_class_is_omap1())
-                pr_debug("USB_TRANSCEIVER_CTRL_REG = %03x\n", USB_TRANSCEIVER_CTRL_REG);
-        pr_debug("OTG_SYSCON_2_REG = %08x\n", syscon);
-        OTG_SYSCON_2_REG = syscon;
+                pr_debug("USB_TRANSCEIVER_CTRL = %03x\n",
+                         omap_readl(USB_TRANSCEIVER_CTRL));
+        pr_debug("OTG_SYSCON_2 = %08x\n", omap_readl(OTG_SYSCON_2));
+        omap_writel(syscon, OTG_SYSCON_2);
 
         printk("USB: hmc %d", config->hmc_mode);
         if (!alt_pingroup)
@@ -597,12 +630,19 @@ omap_otg_init(struct omap_usb_config *config)
         printk("\n");
 
         if (cpu_class_is_omap1()) {
+                u16 w;
+
                 /* leave USB clocks/controllers off until needed */
-                ULPD_SOFT_REQ_REG &= ~SOFT_USB_CLK_REQ;
-                ULPD_CLOCK_CTRL_REG &= ~USB_MCLK_EN;
-                ULPD_CLOCK_CTRL_REG |= DIS_USB_PVCI_CLK;
+                w = omap_readw(ULPD_SOFT_REQ);
+                w &= ~SOFT_USB_CLK_REQ;
+                omap_writew(w, ULPD_SOFT_REQ);
+
+                w = omap_readw(ULPD_CLOCK_CTRL);
+                w &= ~USB_MCLK_EN;
+                w |= DIS_USB_PVCI_CLK;
+                omap_writew(w, ULPD_CLOCK_CTRL);
         }
-        syscon = OTG_SYSCON_1_REG;
+        syscon = omap_readl(OTG_SYSCON_1);
         syscon |= HST_IDLE_EN|DEV_IDLE_EN|OTG_IDLE_EN;
 
 #ifdef  CONFIG_USB_GADGET_OMAP
@@ -639,8 +679,8 @@ omap_otg_init(struct omap_usb_config *config)
                         pr_debug("can't register OTG device, %d\n", status);
         }
 #endif
-        pr_debug("OTG_SYSCON_1_REG = %08x\n", syscon);
-        OTG_SYSCON_1_REG = syscon;
+        pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1));
+        omap_writel(syscon, OTG_SYSCON_1);
 
         status = 0;
 }
@@ -653,18 +693,19 @@ static inline void omap_otg_init(struct omap_usb_config *config) {}
 
 #ifdef  CONFIG_ARCH_OMAP15XX
 
-#define ULPD_DPLL_CTRL_REG      __REG16(ULPD_DPLL_CTRL)
+/* ULPD_DPLL_CTRL */
 #define DPLL_IOB                (1 << 13)
 #define DPLL_PLL_ENABLE         (1 << 4)
 #define DPLL_LOCK               (1 << 0)
 
-#define ULPD_APLL_CTRL_REG      __REG16(ULPD_APLL_CTRL)
+/* ULPD_APLL_CTRL */
 #define APLL_NDPLL_SWITCH       (1 << 0)
 
 
 static void __init omap_1510_usb_init(struct omap_usb_config *config)
 {
         unsigned int val;
+        u16 w;
 
         omap_usb0_init(config->pins[0], is_usb0_device(config));
         omap_usb1_init(config->pins[1]);
@@ -685,12 +726,22 @@ static void __init omap_1510_usb_init(struct omap_usb_config *config)
         printk("\n");
 
         /* use DPLL for 48 MHz function clock */
-        pr_debug("APLL %04x DPLL %04x REQ %04x\n", ULPD_APLL_CTRL_REG,
-                        ULPD_DPLL_CTRL_REG, ULPD_SOFT_REQ_REG);
-        ULPD_APLL_CTRL_REG &= ~APLL_NDPLL_SWITCH;
-        ULPD_DPLL_CTRL_REG |= DPLL_IOB | DPLL_PLL_ENABLE;
-        ULPD_SOFT_REQ_REG |= SOFT_UDC_REQ | SOFT_DPLL_REQ;
-        while (!(ULPD_DPLL_CTRL_REG & DPLL_LOCK))
+        pr_debug("APLL %04x DPLL %04x REQ %04x\n", omap_readw(ULPD_APLL_CTRL),
+                        omap_readw(ULPD_DPLL_CTRL), omap_readw(ULPD_SOFT_REQ));
+
+        w = omap_readw(ULPD_APLL_CTRL);
+        w &= ~APLL_NDPLL_SWITCH;
+        omap_writew(w, ULPD_APLL_CTRL);
+
+        w = omap_readw(ULPD_DPLL_CTRL);
+        w |= DPLL_IOB | DPLL_PLL_ENABLE;
+        omap_writew(w, ULPD_DPLL_CTRL);
+
+        w = omap_readw(ULPD_SOFT_REQ);
+        w |= SOFT_UDC_REQ | SOFT_DPLL_REQ;
+        omap_writew(w, ULPD_SOFT_REQ);
+
+        while (!(omap_readw(ULPD_DPLL_CTRL) & DPLL_LOCK))
                 cpu_relax();
 
 #ifdef  CONFIG_USB_GADGET_OMAP
diff --git a/arch/arm/plat-orion/irq.c b/arch/arm/plat-orion/irq.c
index c5b669d234bc..fe66a1835169 100644
--- a/arch/arm/plat-orion/irq.c
+++ b/arch/arm/plat-orion/irq.c
@@ -36,8 +36,8 @@ static void orion_irq_unmask(u32 irq)
 
 static struct irq_chip orion_irq_chip = {
         .name           = "orion_irq",
-        .ack            = orion_irq_mask,
         .mask           = orion_irq_mask,
+        .mask_ack       = orion_irq_mask,
         .unmask         = orion_irq_unmask,
 };
 
@@ -59,6 +59,7 @@ void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)
                 set_irq_chip(irq, &orion_irq_chip);
                 set_irq_chip_data(irq, maskaddr);
                 set_irq_handler(irq, handle_level_irq);
+                irq_desc[irq].status |= IRQ_LEVEL;
                 set_irq_flags(irq, IRQF_VALID);
         }
 }
diff --git a/arch/arm/plat-orion/pcie.c b/arch/arm/plat-orion/pcie.c
index abfda53f1800..ca32c60e14d7 100644
--- a/arch/arm/plat-orion/pcie.c
+++ b/arch/arm/plat-orion/pcie.c
@@ -39,6 +39,7 @@
 #define PCIE_CONF_DATA_OFF      0x18fc
 #define PCIE_MASK_OFF           0x1910
 #define PCIE_CTRL_OFF           0x1a00
+#define  PCIE_CTRL_X1_MODE              0x0001
 #define PCIE_STAT_OFF           0x1a04
 #define  PCIE_STAT_DEV_OFFS             20
 #define  PCIE_STAT_DEV_MASK             0x1f
@@ -62,6 +63,11 @@ int orion_pcie_link_up(void __iomem *base)
         return !(readl(base + PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
 }
 
+int __init orion_pcie_x4_mode(void __iomem *base)
+{
+        return !(readl(base + PCIE_CTRL_OFF) & PCIE_CTRL_X1_MODE);
+}
+
 int orion_pcie_get_local_bus_nr(void __iomem *base)
 {
         u32 stat = readl(base + PCIE_STAT_OFF);
diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c
index 28b5285446e8..93c4ef9f0067 100644
--- a/arch/arm/plat-orion/time.c
+++ b/arch/arm/plat-orion/time.c
@@ -74,7 +74,7 @@ orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev)
         /*
          * Clear and enable clockevent timer interrupt.
          */
-        writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE);
+        writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE);
 
         u = readl(BRIDGE_MASK);
         u |= BRIDGE_INT_TIMER1;
@@ -138,7 +138,7 @@ orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
                 /*
                  * ACK pending timer interrupt.
                  */
-                writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE);
+                writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE);
 
         }
         local_irq_restore(flags);
@@ -159,7 +159,7 @@ static irqreturn_t orion_timer_interrupt(int irq, void *dev_id)
         /*
          * ACK timer interrupt and call event handler.
          */
-        writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE);
+        writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE);
         orion_clkevt.event_handler(&orion_clkevt);
 
         return IRQ_HANDLED;
diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig
index b66fb3c4e228..5e28c217b8c2 100644
--- a/arch/arm/plat-s3c24xx/Kconfig
+++ b/arch/arm/plat-s3c24xx/Kconfig
@@ -9,6 +9,7 @@ config PLAT_S3C24XX
         depends on ARCH_S3C2410
         default y if ARCH_S3C2410
         select NO_IOPORT
+        select HAVE_GPIO_LIB
         help
           Base platform code for any Samsung S3C24XX device
 
@@ -20,6 +21,13 @@ config CPU_S3C244X
         help
           Support for S3C2440 and S3C2442 Samsung Mobile CPU based systems.
 
+config S3C24XX_PWM
+        bool "PWM device support"
+        select HAVE_PWM
+        help
+          Support for exporting the PWM timer blocks via the pwm device
+          system.
+
 config PM_SIMTEC
         bool
         help
diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile
index 131d20237dd7..d82767b2b833 100644
--- a/arch/arm/plat-s3c24xx/Makefile
+++ b/arch/arm/plat-s3c24xx/Makefile
@@ -16,8 +16,10 @@ obj-y				+= cpu.o
 obj-y                           += irq.o
 obj-y                           += devs.o
 obj-y                           += gpio.o
+obj-y                           += gpiolib.o
 obj-y                           += time.o
 obj-y                           += clock.o
+obj-y                           += pwm-clock.o
 
 # Architecture dependant builds
 
@@ -27,5 +29,6 @@ obj-$(CONFIG_CPU_S3C244X)	+= s3c244x-clock.o
 obj-$(CONFIG_PM_SIMTEC)         += pm-simtec.o
 obj-$(CONFIG_PM)                += pm.o
 obj-$(CONFIG_PM)                += sleep.o
+obj-$(CONFIG_HAVE_PWM)          += pwm.o
 obj-$(CONFIG_S3C2410_DMA)       += dma.o
 obj-$(CONFIG_MACH_SMDK)         += common-smdk.o
diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c
index e546e933b3f7..eea3b32ff798 100644
--- a/arch/arm/plat-s3c24xx/devs.c
+++ b/arch/arm/plat-s3c24xx/devs.c
@@ -495,106 +495,6 @@ struct platform_device s3c_device_spi1 = {
 
 EXPORT_SYMBOL(s3c_device_spi1);
 
-/* pwm timer blocks */
-
-static struct resource s3c_timer0_resource[] = {
-        [0] = {
-                .start = S3C24XX_PA_TIMER + 0x0C,
-                .end   = S3C24XX_PA_TIMER + 0x0C + 0xB,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = IRQ_TIMER0,
-                .end   = IRQ_TIMER0,
-                .flags = IORESOURCE_IRQ,
-        }
-
-};
-
-struct platform_device s3c_device_timer0 = {
-        .name             = "s3c2410-timer",
-        .id               = 0,
-        .num_resources    = ARRAY_SIZE(s3c_timer0_resource),
-        .resource         = s3c_timer0_resource,
-};
-
-EXPORT_SYMBOL(s3c_device_timer0);
-
-/* timer 1 */
-
-static struct resource s3c_timer1_resource[] = {
-        [0] = {
-                .start = S3C24XX_PA_TIMER + 0x18,
-                .end   = S3C24XX_PA_TIMER + 0x23,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = IRQ_TIMER1,
-                .end   = IRQ_TIMER1,
-                .flags = IORESOURCE_IRQ,
-        }
-
-};
-
-struct platform_device s3c_device_timer1 = {
-        .name             = "s3c2410-timer",
-        .id               = 1,
-        .num_resources    = ARRAY_SIZE(s3c_timer1_resource),
-        .resource         = s3c_timer1_resource,
-};
-
-EXPORT_SYMBOL(s3c_device_timer1);
-
-/* timer 2 */
-
-static struct resource s3c_timer2_resource[] = {
-        [0] = {
-                .start = S3C24XX_PA_TIMER + 0x24,
-                .end   = S3C24XX_PA_TIMER + 0x2F,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = IRQ_TIMER2,
-                .end   = IRQ_TIMER2,
-                .flags = IORESOURCE_IRQ,
-        }
-
-};
-
-struct platform_device s3c_device_timer2 = {
-        .name             = "s3c2410-timer",
-        .id               = 2,
-        .num_resources    = ARRAY_SIZE(s3c_timer2_resource),
-        .resource         = s3c_timer2_resource,
-};
-
-EXPORT_SYMBOL(s3c_device_timer2);
-
-/* timer 3 */
-
-static struct resource s3c_timer3_resource[] = {
-        [0] = {
-                .start = S3C24XX_PA_TIMER + 0x30,
-                .end   = S3C24XX_PA_TIMER + 0x3B,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = IRQ_TIMER3,
-                .end   = IRQ_TIMER3,
-                .flags = IORESOURCE_IRQ,
-        }
-
-};
-
-struct platform_device s3c_device_timer3 = {
-        .name             = "s3c2410-timer",
-        .id               = 3,
-        .num_resources    = ARRAY_SIZE(s3c_timer3_resource),
-        .resource         = s3c_timer3_resource,
-};
-
-EXPORT_SYMBOL(s3c_device_timer3);
-
 #ifdef CONFIG_CPU_S3C2440
 
 /* Camif Controller */
diff --git a/arch/arm/plat-s3c24xx/gpiolib.c b/arch/arm/plat-s3c24xx/gpiolib.c
new file mode 100644
index 000000000000..825d8d0c5ca2
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/gpiolib.c
@@ -0,0 +1,259 @@
+/* linux/arch/arm/plat-s3c24xx/gpiolib.c
+ *
+ * Copyright (c) 2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C24XX GPIOlib support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+*/
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+
+#include <asm/hardware.h>
+#include <asm/irq.h>
+
+#include <asm/arch/regs-gpio.h>
+
+struct s3c24xx_gpio_chip {
+        struct gpio_chip        chip;
+        void __iomem            *base;
+};
+
+static inline struct s3c24xx_gpio_chip *to_s3c_chip(struct gpio_chip *gpc)
+{
+        return container_of(gpc, struct s3c24xx_gpio_chip, chip);
+}
+
+/* these routines are exported for use by other parts of the platform
+ * and system support, but are not intended to be used directly by the
+ * drivers themsevles.
+ */
+
+int s3c24xx_gpiolib_input(struct gpio_chip *chip, unsigned offset)
+{
+        struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip);
+        void __iomem *base = ourchip->base;
+        unsigned long flags;
+        unsigned long con;
+
+        local_irq_save(flags);
+
+        con = __raw_readl(base + 0x00);
+        con &= ~(3 << (offset * 2));
+        con |= (S3C2410_GPIO_OUTPUT & 0xf) << (offset * 2);
+
+        __raw_writel(con, base + 0x00);
+
+        local_irq_restore(flags);
+        return 0;
+}
+
+int s3c24xx_gpiolib_output(struct gpio_chip *chip,
+                                  unsigned offset, int value)
+{
+        struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip);
+        void __iomem *base = ourchip->base;
+        unsigned long flags;
+        unsigned long dat;
+        unsigned long con;
+
+        local_irq_save(flags);
+
+        dat = __raw_readl(base + 0x04);
+        dat &= ~(1 << offset);
+        if (value)
+                dat |= 1 << offset;
+        __raw_writel(dat, base + 0x04);
+
+        con = __raw_readl(base + 0x00);
+        con &= ~(3 << (offset * 2));
+        con |= (S3C2410_GPIO_OUTPUT & 0xf) << (offset * 2);
+
+        __raw_writel(con, base + 0x00);
+        __raw_writel(dat, base + 0x04);
+
+        local_irq_restore(flags);
+        return 0;
+}
+
+void s3c24xx_gpiolib_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+        struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip);
+        void __iomem *base = ourchip->base;
+        unsigned long flags;
+        unsigned long dat;
+
+        local_irq_save(flags);
+
+        dat = __raw_readl(base + 0x04);
+        dat &= ~(1 << offset);
+        if (value)
+                dat |= 1 << offset;
+        __raw_writel(dat, base + 0x04);
+
+        local_irq_restore(flags);
+}
+
+int s3c24xx_gpiolib_get(struct gpio_chip *chip, unsigned offset)
+{
+        struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip);
+        unsigned long val;
+
+        val = __raw_readl(ourchip->base + 0x04);
+        val >>= offset;
+        val &= 1;
+
+        return val;
+}
+
+static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset)
+{
+        return -EINVAL;
+}
+
+static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
+                                        unsigned offset, int value)
+{
+        struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip);
+        void __iomem *base = ourchip->base;
+        unsigned long flags;
+        unsigned long dat;
+        unsigned long con;
+
+        local_irq_save(flags);
+
+        con = __raw_readl(base + 0x00);
+        dat = __raw_readl(base + 0x04);
+
+        dat &= ~(1 << offset);
+        if (value)
+                dat |= 1 << offset;
+
+        __raw_writel(dat, base + 0x04);
+
+        con &= ~(1 << offset);
+
+        __raw_writel(con, base + 0x00);
+        __raw_writel(dat, base + 0x04);
+
+        local_irq_restore(flags);
+        return 0;
+}
+
+
+struct s3c24xx_gpio_chip gpios[] = {
+        [0] = {
+                .base   = S3C24XX_GPIO_BASE(S3C2410_GPA0),
+                .chip   = {
+                        .base                   = S3C2410_GPA0,
+                        .owner                  = THIS_MODULE,
+                        .label                  = "GPIOA",
+                        .ngpio                  = 24,
+                        .direction_input        = s3c24xx_gpiolib_banka_input,
+                        .direction_output       = s3c24xx_gpiolib_banka_output,
+                        .set                    = s3c24xx_gpiolib_set,
+                        .get                    = s3c24xx_gpiolib_get,
+                },
+        },
+        [1] = {
+                .base   = S3C24XX_GPIO_BASE(S3C2410_GPB0),
+                .chip   = {
+                        .base                   = S3C2410_GPB0,
+                        .owner                  = THIS_MODULE,
+                        .label                  = "GPIOB",
+                        .ngpio                  = 16,
+                        .direction_input        = s3c24xx_gpiolib_input,
+                        .direction_output       = s3c24xx_gpiolib_output,
+                        .set                    = s3c24xx_gpiolib_set,
+                        .get                    = s3c24xx_gpiolib_get,
+                },
+        },
+        [2] = {
+                .base   = S3C24XX_GPIO_BASE(S3C2410_GPC0),
+                .chip   = {
+                        .base                   = S3C2410_GPC0,
+                        .owner                  = THIS_MODULE,
+                        .label                  = "GPIOC",
+                        .ngpio                  = 16,
+                        .direction_input        = s3c24xx_gpiolib_input,
+                        .direction_output       = s3c24xx_gpiolib_output,
+                        .set                    = s3c24xx_gpiolib_set,
+                        .get                    = s3c24xx_gpiolib_get,
+                },
+        },
+        [3] = {
+                .base   = S3C24XX_GPIO_BASE(S3C2410_GPD0),
+                .chip   = {
+                        .base                   = S3C2410_GPD0,
+                        .owner                  = THIS_MODULE,
+                        .label                  = "GPIOD",
+                        .ngpio                  = 16,
+                        .direction_input        = s3c24xx_gpiolib_input,
+                        .direction_output       = s3c24xx_gpiolib_output,
+                        .set                    = s3c24xx_gpiolib_set,
+                        .get                    = s3c24xx_gpiolib_get,
+                },
+        },
+        [4] = {
+                .base   = S3C24XX_GPIO_BASE(S3C2410_GPE0),
+                .chip   = {
+                        .base                   = S3C2410_GPE0,
+                        .label                  = "GPIOE",
+                        .owner                  = THIS_MODULE,
+                        .ngpio                  = 16,
+                        .direction_input        = s3c24xx_gpiolib_input,
+                        .direction_output       = s3c24xx_gpiolib_output,
+                        .set                    = s3c24xx_gpiolib_set,
+                        .get                    = s3c24xx_gpiolib_get,
+                },
+        },
+        [5] = {
+                .base   = S3C24XX_GPIO_BASE(S3C2410_GPF0),
+                .chip   = {
+                        .base                   = S3C2410_GPF0,
+                        .owner                  = THIS_MODULE,
+                        .label                  = "GPIOF",
+                        .ngpio                  = 8,
+                        .direction_input        = s3c24xx_gpiolib_input,
+                        .direction_output       = s3c24xx_gpiolib_output,
+                        .set                    = s3c24xx_gpiolib_set,
+                        .get                    = s3c24xx_gpiolib_get,
+                },
+        },
+        [6] = {
+                .base   = S3C24XX_GPIO_BASE(S3C2410_GPG0),
+                .chip   = {
+                        .base                   = S3C2410_GPG0,
+                        .owner                  = THIS_MODULE,
+                        .label                  = "GPIOG",
+                        .ngpio                  = 10,
+                        .direction_input        = s3c24xx_gpiolib_input,
+                        .direction_output       = s3c24xx_gpiolib_output,
+                        .set                    = s3c24xx_gpiolib_set,
+                        .get                    = s3c24xx_gpiolib_get,
+                },
+        },
+};
+
+static __init int s3c24xx_gpiolib_init(void)
+{
+        struct s3c24xx_gpio_chip *chip = gpios;
+        int gpn;
+
+        for (gpn = 0; gpn < ARRAY_SIZE(gpios); gpn++, chip++)
+                gpiochip_add(&chip->chip);
+
+        return 0;
+}
+
+arch_initcall(s3c24xx_gpiolib_init);
diff --git a/arch/arm/plat-s3c24xx/pwm-clock.c b/arch/arm/plat-s3c24xx/pwm-clock.c
new file mode 100644
index 000000000000..2cda3e3c6786
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/pwm-clock.c
@@ -0,0 +1,437 @@
+/* linux/arch/arm/plat-s3c24xx/pwm-clock.c
+ *
+ * Copyright (c) 2007 Simtec Electronics
+ * Copyright (c) 2007, 2008 Ben Dooks
+ *      Ben Dooks <ben-linux@fluff.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+#include <asm/hardware.h>
+#include <asm/irq.h>
+
+#include <asm/arch/regs-clock.h>
+#include <asm/arch/regs-gpio.h>
+
+#include <asm/plat-s3c24xx/clock.h>
+#include <asm/plat-s3c24xx/cpu.h>
+
+#include <asm/plat-s3c/regs-timer.h>
+
+/* Each of the timers 0 through 5 go through the following
+ * clock tree, with the inputs depending on the timers.
+ *
+ * pclk ---- [ prescaler 0 ] -+---> timer 0
+ *                            +---> timer 1
+ *
+ * pclk ---- [ prescaler 1 ] -+---> timer 2
+ *                            +---> timer 3
+ *                            \---> timer 4
+ *
+ * Which are fed into the timers as so:
+ *
+ * prescaled 0 ---- [ div 2,4,8,16 ] ---\
+ *                                     [mux] -> timer 0
+ * tclk 0 ------------------------------/
+ *
+ * prescaled 0 ---- [ div 2,4,8,16 ] ---\
+ *                                     [mux] -> timer 1
+ * tclk 0 ------------------------------/
+ *
+ *
+ * prescaled 1 ---- [ div 2,4,8,16 ] ---\
+ *                                     [mux] -> timer 2
+ * tclk 1 ------------------------------/
+ *
+ * prescaled 1 ---- [ div 2,4,8,16 ] ---\
+ *                                     [mux] -> timer 3
+ * tclk 1 ------------------------------/
+ *
+ * prescaled 1 ---- [ div 2,4,8, 16 ] --\
+ *                                     [mux] -> timer 4
+ * tclk 1 ------------------------------/
+ *
+ * Since the mux and the divider are tied together in the
+ * same register space, it is impossible to set the parent
+ * and the rate at the same time. To avoid this, we add an
+ * intermediate 'prescaled-and-divided' clock to select
+ * as the parent for the timer input clock called tdiv.
+ *
+ * prescaled clk --> pwm-tdiv ---\
+ *                             [ mux ] --> timer X
+ * tclk -------------------------/
+*/
+
+static unsigned long clk_pwm_scaler_getrate(struct clk *clk)
+{
+        unsigned long tcfg0 = __raw_readl(S3C2410_TCFG0);
+
+        if (clk->id == 1) {
+                tcfg0 &= S3C2410_TCFG_PRESCALER1_MASK;
+                tcfg0 >>= S3C2410_TCFG_PRESCALER1_SHIFT;
+        } else {
+                tcfg0 &= S3C2410_TCFG_PRESCALER0_MASK;
+        }
+
+        return clk_get_rate(clk->parent) / (tcfg0 + 1);
+}
+
+/* TODO - add set rate calls. */
+
+struct clk clk_timer_scaler[] = {
+        [0]     = {
+                .name           = "pwm-scaler0",
+                .id             = -1,
+                .get_rate       = clk_pwm_scaler_getrate,
+        },
+        [1]     = {
+                .name           = "pwm-scaler1",
+                .id             = -1,
+                .get_rate       = clk_pwm_scaler_getrate,
+        },
+};
+
+struct clk clk_timer_tclk[] = {
+        [0]     = {
+                .name           = "pwm-tclk0",
+                .id             = -1,
+        },
+        [1]     = {
+                .name           = "pwm-tclk1",
+                .id             = -1,
+        },
+};
+
+struct pwm_tdiv_clk {
+        struct clk      clk;
+        unsigned int    divisor;
+};
+
+static inline struct pwm_tdiv_clk *to_tdiv(struct clk *clk)
+{
+        return container_of(clk, struct pwm_tdiv_clk, clk);
+}
+
+static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
+{
+        return 1 << (1 + tcfg1);
+}
+
+static unsigned long clk_pwm_tdiv_get_rate(struct clk *clk)
+{
+        unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
+        unsigned int divisor;
+
+        tcfg1 >>= S3C2410_TCFG1_SHIFT(clk->id);
+        tcfg1 &= S3C2410_TCFG1_MUX_MASK;
+
+        if (tcfg1 == S3C2410_TCFG1_MUX_TCLK)
+                divisor = to_tdiv(clk)->divisor;
+        else
+                divisor = tcfg_to_divisor(tcfg1);
+
+        return clk_get_rate(clk->parent) / divisor;
+}
+
+static unsigned long clk_pwm_tdiv_round_rate(struct clk *clk,
+                                             unsigned long rate)
+{
+        unsigned long parent_rate;
+        unsigned long divisor;
+
+        parent_rate = clk_get_rate(clk->parent);
+        divisor = parent_rate / rate;
+
+        if (divisor <= 2)
+                divisor = 2;
+        else if (divisor <= 4)
+                divisor = 4;
+        else if (divisor <= 8)
+                divisor = 8;
+        else
+                divisor = 16;
+
+        return parent_rate / divisor;
+}
+
+static unsigned long clk_pwm_tdiv_bits(struct pwm_tdiv_clk *divclk)
+{
+        unsigned long bits;
+
+        switch (divclk->divisor) {
+        case 2:
+                bits = S3C2410_TCFG1_MUX_DIV2;
+                break;
+        case 4:
+                bits = S3C2410_TCFG1_MUX_DIV4;
+                break;
+        case 8:
+                bits = S3C2410_TCFG1_MUX_DIV8;
+                break;
+        case 16:
+        default:
+                bits = S3C2410_TCFG1_MUX_DIV16;
+                break;
+        }
+
+        return bits;
+}
+
+static void clk_pwm_tdiv_update(struct pwm_tdiv_clk *divclk)
+{
+        unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
+        unsigned long bits = clk_pwm_tdiv_bits(divclk);
+        unsigned long flags;
+        unsigned long shift =  S3C2410_TCFG1_SHIFT(divclk->clk.id);
+
+        local_irq_save(flags);
+
+        tcfg1 = __raw_readl(S3C2410_TCFG1);
+        tcfg1 &= ~(S3C2410_TCFG1_MUX_MASK << shift);
+        tcfg1 |= bits << shift;
+        __raw_writel(tcfg1, S3C2410_TCFG1);
+
+        local_irq_restore(flags);
+}
+
+static int clk_pwm_tdiv_set_rate(struct clk *clk, unsigned long rate)
+{
+        struct pwm_tdiv_clk *divclk = to_tdiv(clk);
+        unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
+        unsigned long parent_rate = clk_get_rate(clk->parent);
+        unsigned long divisor;
+
+        tcfg1 >>= S3C2410_TCFG1_SHIFT(clk->id);
+        tcfg1 &= S3C2410_TCFG1_MUX_MASK;
+
+        rate = clk_round_rate(clk, rate);
+        divisor = parent_rate / rate;
+
+        if (divisor > 16)
+                return -EINVAL;
+
+        divclk->divisor = divisor;
+
+        /* Update the current MUX settings if we are currently
+         * selected as the clock source for this clock. */
+
+        if (tcfg1 != S3C2410_TCFG1_MUX_TCLK)
+                clk_pwm_tdiv_update(divclk);
+
+        return 0;
+}
+
+struct pwm_tdiv_clk clk_timer_tdiv[] = {
+        [0]     = {
+                .clk    = {
+                        .name           = "pwm-tdiv",
+                        .parent         = &clk_timer_scaler[0],
+                        .get_rate       = clk_pwm_tdiv_get_rate,
+                        .set_rate       = clk_pwm_tdiv_set_rate,
+                        .round_rate     = clk_pwm_tdiv_round_rate,
+                },
+        },
+        [1]     = {
+                .clk    = {
+                        .name           = "pwm-tdiv",
+                        .parent         = &clk_timer_scaler[0],
+                        .get_rate       = clk_pwm_tdiv_get_rate,
+                        .set_rate       = clk_pwm_tdiv_set_rate,
+                        .round_rate     = clk_pwm_tdiv_round_rate,
+                }
+        },
+        [2]     = {
+                .clk    = {
+                        .name           = "pwm-tdiv",
+                        .parent         = &clk_timer_scaler[1],
+                        .get_rate       = clk_pwm_tdiv_get_rate,
+                        .set_rate       = clk_pwm_tdiv_set_rate,
+                        .round_rate     = clk_pwm_tdiv_round_rate,
+                },
+        },
+        [3]     = {
+                .clk    = {
+                        .name           = "pwm-tdiv",
+                        .parent         = &clk_timer_scaler[1],
+                        .get_rate       = clk_pwm_tdiv_get_rate,
+                        .set_rate       = clk_pwm_tdiv_set_rate,
+                        .round_rate     = clk_pwm_tdiv_round_rate,
+                },
+        },
+        [4]     = {
+                .clk    = {
+                        .name           = "pwm-tdiv",
+                        .parent         = &clk_timer_scaler[1],
+                        .get_rate       = clk_pwm_tdiv_get_rate,
+                        .set_rate       = clk_pwm_tdiv_set_rate,
+                        .round_rate     = clk_pwm_tdiv_round_rate,
+                },
+        },
+};
+
+static int __init clk_pwm_tdiv_register(unsigned int id)
+{
+        struct pwm_tdiv_clk *divclk = &clk_timer_tdiv[id];
+        unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
+
+        tcfg1 >>= S3C2410_TCFG1_SHIFT(id);
+        tcfg1 &= S3C2410_TCFG1_MUX_MASK;
+
+        divclk->clk.id = id;
+        divclk->divisor = tcfg_to_divisor(tcfg1);
+
+        return s3c24xx_register_clock(&divclk->clk);
+}
+
+static inline struct clk *s3c24xx_pwmclk_tclk(unsigned int id)
+{
+        return (id >= 2) ? &clk_timer_tclk[1] : &clk_timer_tclk[0];
+}
+
+static inline struct clk *s3c24xx_pwmclk_tdiv(unsigned int id)
+{
+        return &clk_timer_tdiv[id].clk;
+}
+
+static int clk_pwm_tin_set_parent(struct clk *clk, struct clk *parent)
+{
+        unsigned int id = clk->id;
+        unsigned long tcfg1;
+        unsigned long flags;
+        unsigned long bits;
+        unsigned long shift = S3C2410_TCFG1_SHIFT(id);
+
+        if (parent == s3c24xx_pwmclk_tclk(id))
+                bits = S3C2410_TCFG1_MUX_TCLK << shift;
+        else if (parent == s3c24xx_pwmclk_tdiv(id))
+                bits = clk_pwm_tdiv_bits(to_tdiv(clk)) << shift;
+        else
+                return -EINVAL;
+
+        clk->parent = parent;
+
+        local_irq_save(flags);
+
+        tcfg1 = __raw_readl(S3C2410_TCFG1);
+        tcfg1 &= ~(S3C2410_TCFG1_MUX_MASK << shift);
+        __raw_writel(tcfg1 | bits, S3C2410_TCFG1);
+
+        local_irq_restore(flags);
+
+        return 0;
+}
+
+static struct clk clk_tin[] = {
+        [0]     = {
+                .name           = "pwm-tin",
+                .id             = 0,
+                .set_parent     = clk_pwm_tin_set_parent,
+        },
+        [1]     = {
+                .name           = "pwm-tin",
+                .id             = 1,
+                .set_parent     = clk_pwm_tin_set_parent,
+        },
+        [2]     = {
+                .name           = "pwm-tin",
+                .id             = 2,
+                .set_parent     = clk_pwm_tin_set_parent,
+        },
+        [3]     = {
+                .name           = "pwm-tin",
+                .id             = 3,
+                .set_parent     = clk_pwm_tin_set_parent,
+        },
+        [4]     = {
+                .name           = "pwm-tin",
+                .id             = 4,
+                .set_parent     = clk_pwm_tin_set_parent,
+        },
+};
+
+static __init int clk_pwm_tin_register(struct clk *pwm)
+{
+        unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
+        unsigned int id = pwm->id;
+
+        struct clk *parent;
+        int ret;
+
+        ret = s3c24xx_register_clock(pwm);
+        if (ret < 0)
+                return ret;
+
+        tcfg1 >>= S3C2410_TCFG1_SHIFT(id);
+        tcfg1 &= S3C2410_TCFG1_MUX_MASK;
+
+        if (tcfg1 == S3C2410_TCFG1_MUX_TCLK)
+                parent = s3c24xx_pwmclk_tclk(id);
+        else
+                parent = s3c24xx_pwmclk_tdiv(id);
+
+        return clk_set_parent(pwm, parent);
+}
+
+static __init int s3c24xx_pwmclk_init(void)
+{
+        struct clk *clk_timers;
+        unsigned int clk;
+        int ret;
+
+        clk_timers = clk_get(NULL, "timers");
+        if (IS_ERR(clk_timers)) {
+                printk(KERN_ERR "%s: no parent clock\n", __func__);
+                return -EINVAL;
+        }
+
+        for (clk = 0; clk < ARRAY_SIZE(clk_timer_scaler); clk++) {
+                clk_timer_scaler[clk].parent = clk_timers;
+                ret = s3c24xx_register_clock(&clk_timer_scaler[clk]);
+                if (ret < 0) {
+                        printk(KERN_ERR "error adding pwm scaler%d clock\n", clk);
+                        goto err;
+                }
+        }
+
+        for (clk = 0; clk < ARRAY_SIZE(clk_timer_tclk); clk++) {
+                ret = s3c24xx_register_clock(&clk_timer_tclk[clk]);
+                if (ret < 0) {
+                        printk(KERN_ERR "error adding pww tclk%d\n", clk);
+                        goto err;
+                }
+        }
+
+        for (clk = 0; clk < ARRAY_SIZE(clk_timer_tdiv); clk++) {
+                ret = clk_pwm_tdiv_register(clk);
+                if (ret < 0) {
+                        printk(KERN_ERR "error adding pwm%d tdiv clock\n", clk);
+                        goto err;
+                }
+        }
+
+        for (clk = 0; clk < ARRAY_SIZE(clk_tin); clk++) {
+                ret = clk_pwm_tin_register(&clk_tin[clk]);
+                if (ret < 0) {
+                        printk(KERN_ERR "error adding pwm%d tin clock\n", clk);
+                        goto err;
+                }
+        }
+
+        return 0;
+
+ err:
+        return ret;
+}
+
+arch_initcall(s3c24xx_pwmclk_init);
diff --git a/arch/arm/plat-s3c24xx/pwm.c b/arch/arm/plat-s3c24xx/pwm.c
new file mode 100644
index 000000000000..18c4bdc49a05
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/pwm.c
@@ -0,0 +1,402 @@
+/* arch/arm/plat-s3c24xx/pwm.c
+ *
+ * Copyright (c) 2007 Ben Dooks
+ * Copyright (c) 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org>
+ *
+ * S3C24XX PWM device core
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+*/
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/pwm.h>
+
+#include <asm/plat-s3c/regs-timer.h>
+
+struct pwm_device {
+        struct list_head         list;
+        struct platform_device  *pdev;
+
+        struct clk              *clk_div;
+        struct clk              *clk;
+        const char              *label;
+
+        unsigned int             period_ns;
+        unsigned int             duty_ns;
+
+        unsigned char            tcon_base;
+        unsigned char            running;
+        unsigned char            use_count;
+        unsigned char            pwm_id;
+};
+
+#define pwm_dbg(_pwm, msg...) dev_info(&(_pwm)->pdev->dev, msg)
+
+static struct clk *clk_scaler[2];
+
+/* Standard setup for a timer block. */
+
+#define TIMER_RESOURCE_SIZE (1)
+
+#define TIMER_RESOURCE(_tmr, _irq)                      \
+        (struct resource [TIMER_RESOURCE_SIZE]) {       \
+                [0] = {                                 \
+                        .start  = _irq,                 \
+                        .end    = _irq,                 \
+                        .flags  = IORESOURCE_IRQ        \
+                }                                       \
+        }
+
+#define DEFINE_TIMER(_tmr_no, _irq)                     \
+        .name           = "s3c24xx-pwm",                \
+        .id             = _tmr_no,                      \
+        .num_resources  = TIMER_RESOURCE_SIZE,          \
+        .resource       = TIMER_RESOURCE(_tmr_no, _irq),        \
+
+/* since we already have an static mapping for the timer, we do not
+ * bother setting any IO resource for the base.
+ */
+
+struct platform_device s3c_device_timer[] = {
+        [0] = { DEFINE_TIMER(0, IRQ_TIMER0) },
+        [1] = { DEFINE_TIMER(1, IRQ_TIMER1) },
+        [2] = { DEFINE_TIMER(2, IRQ_TIMER2) },
+        [3] = { DEFINE_TIMER(3, IRQ_TIMER3) },
+        [4] = { DEFINE_TIMER(4, IRQ_TIMER4) },
+};
+
+static inline int pwm_is_tdiv(struct pwm_device *pwm)
+{
+        return clk_get_parent(pwm->clk) == pwm->clk_div;
+}
+
+static DEFINE_MUTEX(pwm_lock);
+static LIST_HEAD(pwm_list);
+
+struct pwm_device *pwm_request(int pwm_id, const char *label)
+{
+        struct pwm_device *pwm;
+        int found = 0;
+
+        mutex_lock(&pwm_lock);
+
+        list_for_each_entry(pwm, &pwm_list, list) {
+                if (pwm->pwm_id == pwm_id) {
+                        found = 1;
+                        break;
+                }
+        }
+
+        if (found) {
+                if (pwm->use_count == 0) {
+                        pwm->use_count = 1;
+                        pwm->label = label;
+                } else
+                        pwm = ERR_PTR(-EBUSY);
+        } else
+                pwm = ERR_PTR(-ENOENT);
+
+        mutex_unlock(&pwm_lock);
+        return pwm;
+}
+
+EXPORT_SYMBOL(pwm_request);
+
+
+void pwm_free(struct pwm_device *pwm)
+{
+        mutex_lock(&pwm_lock);
+
+        if (pwm->use_count) {
+                pwm->use_count--;
+                pwm->label = NULL;
+        } else
+                printk(KERN_ERR "PWM%d device already freed\n", pwm->pwm_id);
+
+        mutex_unlock(&pwm_lock);
+}
+
+EXPORT_SYMBOL(pwm_free);
+
+#define pwm_tcon_start(pwm) (1 << (pwm->tcon_base + 0))
+#define pwm_tcon_invert(pwm) (1 << (pwm->tcon_base + 2))
+#define pwm_tcon_autoreload(pwm) (1 << (pwm->tcon_base + 3))
+#define pwm_tcon_manulupdate(pwm) (1 << (pwm->tcon_base + 1))
+
+int pwm_enable(struct pwm_device *pwm)
+{
+        unsigned long flags;
+        unsigned long tcon;
+
+        local_irq_save(flags);
+
+        tcon = __raw_readl(S3C2410_TCON);
+        tcon |= pwm_tcon_start(pwm);
+        __raw_writel(tcon, S3C2410_TCON);
+
+        local_irq_restore(flags);
+
+        pwm->running = 1;
+        return 0;
+}
+
+EXPORT_SYMBOL(pwm_enable);
+
+void pwm_disable(struct pwm_device *pwm)
+{
+        unsigned long flags;
+        unsigned long tcon;
+
+        local_irq_save(flags);
+
+        tcon = __raw_readl(S3C2410_TCON);
+        tcon &= ~pwm_tcon_start(pwm);
+        __raw_writel(tcon, S3C2410_TCON);
+
+        local_irq_restore(flags);
+
+        pwm->running = 0;
+}
+
+EXPORT_SYMBOL(pwm_disable);
+
+unsigned long pwm_calc_tin(struct pwm_device *pwm, unsigned long freq)
+{
+        unsigned long tin_parent_rate;
+        unsigned int div;
+
+        tin_parent_rate = clk_get_rate(clk_get_parent(pwm->clk_div));
+        pwm_dbg(pwm, "tin parent at %lu\n", tin_parent_rate);
+
+        for (div = 2; div <= 16; div *= 2) {
+                if ((tin_parent_rate / (div << 16)) < freq)
+                        return tin_parent_rate / div;
+        }
+
+        return tin_parent_rate / 16;
+}
+
+#define NS_IN_HZ (1000000000UL)
+
+int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
+{
+        unsigned long tin_rate;
+        unsigned long tin_ns;
+        unsigned long period;
+        unsigned long flags;
+        unsigned long tcon;
+        unsigned long tcnt;
+        long tcmp;
+
+        /* We currently avoid using 64bit arithmetic by using the
+         * fact that anything faster than 1Hz is easily representable
+         * by 32bits. */
+
+        if (period_ns > NS_IN_HZ || duty_ns > NS_IN_HZ)
+                return -ERANGE;
+
+        if (duty_ns > period_ns)
+                return -EINVAL;
+
+        if (period_ns == pwm->period_ns &&
+            duty_ns == pwm->duty_ns)
+                return 0;
+
+        /* The TCMP and TCNT can be read without a lock, they're not
+         * shared between the timers. */
+
+        tcmp = __raw_readl(S3C2410_TCMPB(pwm->pwm_id));
+        tcnt = __raw_readl(S3C2410_TCNTB(pwm->pwm_id));
+
+        period = NS_IN_HZ / period_ns;
+
+        pwm_dbg(pwm, "duty_ns=%d, period_ns=%d (%lu)\n",
+                duty_ns, period_ns, period);
+
+        /* Check to see if we are changing the clock rate of the PWM */
+
+        if (pwm->period_ns != period_ns) {
+                if (pwm_is_tdiv(pwm)) {
+                        tin_rate = pwm_calc_tin(pwm, period);
+                        clk_set_rate(pwm->clk_div, tin_rate);
+                } else
+                        tin_rate = clk_get_rate(pwm->clk);
+
+                pwm->period_ns = period_ns;
+
+                pwm_dbg(pwm, "tin_rate=%lu\n", tin_rate);
+
+                tin_ns = NS_IN_HZ / tin_rate;
+                tcnt = period_ns / tin_ns;
+        } else
+                tin_ns = NS_IN_HZ / clk_get_rate(pwm->clk);
+
+        /* Note, counters count down */
+
+        tcmp = duty_ns / tin_ns;
+        tcmp = tcnt - tcmp;
+
+        pwm_dbg(pwm, "tin_ns=%lu, tcmp=%ld/%lu\n", tin_ns, tcmp, tcnt);
+
+        if (tcmp < 0)
+                tcmp = 0;
+
+        /* Update the PWM register block. */
+
+        local_irq_save(flags);
+
+        __raw_writel(tcmp, S3C2410_TCMPB(pwm->pwm_id));
+        __raw_writel(tcnt, S3C2410_TCNTB(pwm->pwm_id));
+
+        tcon = __raw_readl(S3C2410_TCON);
+        tcon |= pwm_tcon_manulupdate(pwm);
+        tcon |= pwm_tcon_autoreload(pwm);
+        __raw_writel(tcon, S3C2410_TCON);
+
+        tcon &= ~pwm_tcon_manulupdate(pwm);
+        __raw_writel(tcon, S3C2410_TCON);
+
+        local_irq_restore(flags);
+
+        return 0;
+}
+
+EXPORT_SYMBOL(pwm_config);
+
+static int pwm_register(struct pwm_device *pwm)
+{
+        pwm->duty_ns = -1;
+        pwm->period_ns = -1;
+
+        mutex_lock(&pwm_lock);
+        list_add_tail(&pwm->list, &pwm_list);
+        mutex_unlock(&pwm_lock);
+
+        return 0;
+}
+
+static int s3c_pwm_probe(struct platform_device *pdev)
+{
+        struct device *dev = &pdev->dev;
+        struct pwm_device *pwm;
+        unsigned long flags;
+        unsigned long tcon;
+        unsigned int id = pdev->id;
+        int ret;
+
+        if (id == 4) {
+                dev_err(dev, "TIMER4 is currently not supported\n");
+                return -ENXIO;
+        }
+
+        pwm = kzalloc(sizeof(struct pwm_device), GFP_KERNEL);
+        if (pwm == NULL) {
+                dev_err(dev, "failed to allocate pwm_device\n");
+                return -ENOMEM;
+        }
+
+        pwm->pdev = pdev;
+        pwm->pwm_id = id;
+
+        /* calculate base of control bits in TCON */
+        pwm->tcon_base = id == 0 ? 0 : (id * 4) + 4;
+
+        pwm->clk = clk_get(dev, "pwm-tin");
+        if (IS_ERR(pwm->clk)) {
+                dev_err(dev, "failed to get pwm tin clk\n");
+                ret = PTR_ERR(pwm->clk);
+                goto err_alloc;
+        }
+
+        pwm->clk_div = clk_get(dev, "pwm-tdiv");
+        if (IS_ERR(pwm->clk_div)) {
+                dev_err(dev, "failed to get pwm tdiv clk\n");
+                ret = PTR_ERR(pwm->clk_div);
+                goto err_clk_tin;
+        }
+
+        local_irq_save(flags);
+
+        tcon = __raw_readl(S3C2410_TCON);
+        tcon |= pwm_tcon_invert(pwm);
+        __raw_writel(tcon, S3C2410_TCON);
+
+        local_irq_restore(flags);
+
+
+        ret = pwm_register(pwm);
+        if (ret) {
+                dev_err(dev, "failed to register pwm\n");
+                goto err_clk_tdiv;
+        }
+
+        pwm_dbg(pwm, "config bits %02x\n",
+                (__raw_readl(S3C2410_TCON) >> pwm->tcon_base) & 0x0f);
+
+        dev_info(dev, "tin at %lu, tdiv at %lu, tin=%sclk, base %d\n",
+                 clk_get_rate(pwm->clk),
+                 clk_get_rate(pwm->clk_div),
+                 pwm_is_tdiv(pwm) ? "div" : "ext", pwm->tcon_base);
+
+        platform_set_drvdata(pdev, pwm);
+        return 0;
+
+ err_clk_tdiv:
+        clk_put(pwm->clk_div);
+
+ err_clk_tin:
+        clk_put(pwm->clk);
+
+ err_alloc:
+        kfree(pwm);
+        return ret;
+}
+
+static int s3c_pwm_remove(struct platform_device *pdev)
+{
+        struct pwm_device *pwm = platform_get_drvdata(pdev);
+
+        clk_put(pwm->clk_div);
+        clk_put(pwm->clk);
+        kfree(pwm);
+
+        return 0;
+}
+
+static struct platform_driver s3c_pwm_driver = {
+        .driver         = {
+                .name   = "s3c24xx-pwm",
+                .owner  = THIS_MODULE,
+        },
+        .probe          = s3c_pwm_probe,
+        .remove         = __devexit_p(s3c_pwm_remove),
+};
+
+static int __init pwm_init(void)
+{
+        int ret;
+
+        clk_scaler[0] = clk_get(NULL, "pwm-scaler0");
+        clk_scaler[1] = clk_get(NULL, "pwm-scaler1");
+
+        if (IS_ERR(clk_scaler[0]) || IS_ERR(clk_scaler[1])) {
+                printk(KERN_ERR "%s: failed to get scaler clocks\n", __func__);
+                return -EINVAL;
+        }
+
+        ret = platform_driver_register(&s3c_pwm_driver);
+        if (ret)
+                printk(KERN_ERR "%s: failed to add pwm driver\n", __func__);
+
+        return ret;
+}
+
+arch_initcall(pwm_init);
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index 207a8b5a0c4a..0be5630ff568 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -12,7 +12,7 @@
 #
 #   http://www.arm.linux.org.uk/developer/machines/?action=new
 #
-# Last update: Sat Apr 19 11:23:38 2008
+# Last update: Mon Jul 7 16:25:39 2008
 #
 # machine_is_xxx        CONFIG_xxxx             MACH_TYPE_xxx           number
 #
@@ -560,7 +560,6 @@ husky			MACH_HUSKY		HUSKY			543
 boxer                   MACH_BOXER              BOXER                   544
 shepherd                MACH_SHEPHERD           SHEPHERD                545
 aml42800aa              MACH_AML42800AA         AML42800AA              546
-ml674001                MACH_MACH_TYPE_ML674001 MACH_TYPE_ML674001      547
 lpc2294                 MACH_LPC2294            LPC2294                 548
 switchgrass             MACH_SWITCHGRASS        SWITCHGRASS             549
 ens_cmu                 MACH_ENS_CMU            ENS_CMU                 550
@@ -748,7 +747,6 @@ anubis			MACH_ANUBIS		ANUBIS			734
 ite8152                 MACH_ITE8152            ITE8152                 735
 lpc3xxx                 MACH_LPC3XXX            LPC3XXX                 736
 puppeteer               MACH_PUPPETEER          PUPPETEER               737
-vt001                   MACH_MACH_VADATECH      MACH_VADATECH           738
 e570                    MACH_E570               E570                    739
 x50                     MACH_X50                X50                     740
 recon                   MACH_RECON              RECON                   741
@@ -839,7 +837,7 @@ ccxp270			MACH_CCXP		CCXP			825
 omap_gsample            MACH_OMAP_GSAMPLE       OMAP_GSAMPLE            826
 realview_eb             MACH_REALVIEW_EB        REALVIEW_EB             827
 samoa                   MACH_SAMOA              SAMOA                   828
-t3xscale                MACH_T3XSCALE           T3XSCALE                829
+palmt3                  MACH_PALMT3             PALMT3                  829
 i878                    MACH_I878               I878                    830
 borzoi                  MACH_BORZOI             BORZOI                  831
 gecko                   MACH_GECKO              GECKO                   832
@@ -895,7 +893,7 @@ mio8390			MACH_MIO8390		MIO8390			881
 omi_board               MACH_OMI_BOARD          OMI_BOARD               882
 mx21civ                 MACH_MX21CIV            MX21CIV                 883
 mahi_cdac               MACH_MAHI_CDAC          MAHI_CDAC               884
-xscale_palmtx           MACH_XSCALE_PALMTX      XSCALE_PALMTX           885
+palmtx                  MACH_PALMTX             PALMTX                  885
 s3c2413                 MACH_S3C2413            S3C2413                 887
 samsys_ep0              MACH_SAMSYS_EP0         SAMSYS_EP0              888
 wg302v1                 MACH_WG302V1            WG302V1                 889
@@ -918,7 +916,7 @@ nxdb500			MACH_NXDB500		NXDB500			905
 apf9328                 MACH_APF9328            APF9328                 906
 omap_wipoq              MACH_OMAP_WIPOQ         OMAP_WIPOQ              907
 omap_twip               MACH_OMAP_TWIP          OMAP_TWIP               908
-xscale_treo650          MACH_XSCALE_PALMTREO650 XSCALE_PALMTREO650      909
+palmtreo650             MACH_PALMTREO650        PALMTREO650             909
 acumen                  MACH_ACUMEN             ACUMEN                  910
 xp100                   MACH_XP100              XP100                   911
 fs2410                  MACH_FS2410             FS2410                  912
@@ -926,8 +924,8 @@ pxa270_cerf		MACH_PXA270_CERF	PXA270_CERF		913
 sq2ftlpalm              MACH_SQ2FTLPALM         SQ2FTLPALM              914
 bsemserver              MACH_BSEMSERVER         BSEMSERVER              915
 netclient               MACH_NETCLIENT          NETCLIENT               916
-xscale_palmtt5          MACH_XSCALE_PALMTT5     XSCALE_PALMTT5          917
-xscale_palmtc           MACH_OMAP_PALMTC        OMAP_PALMTC             918
+palmt5                  MACH_PALMT5             PALMT5                  917
+palmtc                  MACH_PALMTC             PALMTC                  918
 omap_apollon            MACH_OMAP_APOLLON       OMAP_APOLLON            919
 mxc30030evb             MACH_MXC30030EVB        MXC30030EVB             920
 rea_2d                  MACH_REA_2D             REA_2D                  921
@@ -1220,7 +1218,6 @@ empca400		MACH_EMPCA400		EMPCA400		1211
 em7210                  MACH_EM7210             EM7210                  1212
 htchermes               MACH_HTCHERMES          HTCHERMES               1213
 eti_c1                  MACH_ETI_C1             ETI_C1                  1214
-mach_dep2410            MACH_MACH_DEP2410       MACH_DEP2410            1215
 ac100                   MACH_AC100              AC100                   1216
 sneetch                 MACH_SNEETCH            SNEETCH                 1217
 studentmate             MACH_STUDENTMATE        STUDENTMATE             1218
@@ -1421,10 +1418,10 @@ looxc550		MACH_LOOXC550		LOOXC550		1417
 cnty_titan              MACH_CNTY_TITAN         CNTY_TITAN              1418
 app3xx                  MACH_APP3XX             APP3XX                  1419
 sideoatsgrama           MACH_SIDEOATSGRAMA      SIDEOATSGRAMA           1420
-xscale_palmt700p        MACH_XSCALE_PALMT700P   XSCALE_PALMT700P        1421
-xscale_palmt700w        MACH_XSCALE_PALMT700W   XSCALE_PALMT700W        1422
-xscale_palmt750         MACH_XSCALE_PALMT750    XSCALE_PALMT750         1423
-xscale_palmt755p        MACH_XSCALE_PALMT755P   XSCALE_PALMT755P        1424
+palmtreo700p            MACH_PALMTREO700P       PALMTREO700P            1421
+palmtreo700w            MACH_PALMTREO700W       PALMTREO700W            1422
+palmtreo750             MACH_PALMTREO750        PALMTREO750             1423
+palmtreo755p            MACH_PALMTREO755P       PALMTREO755P            1424
 ezreganut9200           MACH_EZREGANUT9200      EZREGANUT9200           1425
 sarge                   MACH_SARGE              SARGE                   1426
 a696                    MACH_A696               A696                    1427
@@ -1463,7 +1460,7 @@ artemis			MACH_ARTEMIS		ARTEMIS			1462
 htctitan                MACH_HTCTITAN           HTCTITAN                1463
 qranium                 MACH_QRANIUM            QRANIUM                 1464
 adx_wsc2                MACH_ADX_WSC2           ADX_WSC2                1465
-adx_medcom              MACH_ADX_MEDINET        ADX_MEDINET             1466
+adx_medcom              MACH_ADX_MEDCOM         ADX_MEDCOM              1466
 bboard                  MACH_BBOARD             BBOARD                  1467
 cambria                 MACH_CAMBRIA            CAMBRIA                 1468
 mt7xxx                  MACH_MT7XXX             MT7XXX                  1469
@@ -1519,7 +1516,7 @@ wp188			MACH_WP188		WP188			1518
 corsica                 MACH_CORSICA            CORSICA                 1519
 bigeye                  MACH_BIGEYE             BIGEYE                  1520
 tll5000                 MACH_TLL5000            TLL5000                 1522
-hni270                  MACH_HNI_X270           HNI_X270                1523
+bebot                   MACH_BEBOT              BEBOT                   1523
 qong                    MACH_QONG               QONG                    1524
 tcompact                MACH_TCOMPACT           TCOMPACT                1525
 puma5                   MACH_PUMA5              PUMA5                   1526
@@ -1636,7 +1633,6 @@ awlug4lcu		MACH_AWLUG4LCU		AWLUG4LCU		1637
 palermoc                MACH_PALERMOC           PALERMOC                1638
 omap_ldp                MACH_OMAP_LDP           OMAP_LDP                1639
 ip500                   MACH_IP500              IP500                   1640
-mx35ads                 MACH_MACH_MX35ADS       MACH_MX35ADS            1641
 ase2                    MACH_ASE2               ASE2                    1642
 mx35evb                 MACH_MX35EVB            MX35EVB                 1643
 aml_m8050               MACH_AML_M8050          AML_M8050               1644
@@ -1647,7 +1643,7 @@ badger			MACH_BADGER		BADGER			1648
 trizeps4wl              MACH_TRIZEPS4WL         TRIZEPS4WL              1649
 trizeps5                MACH_TRIZEPS5           TRIZEPS5                1650
 marlin                  MACH_MARLIN             MARLIN                  1651
-ts7800                  MACH_TS7800             TS7800                  1652
+ts78xx                  MACH_TS78XX             TS78XX                  1652
 hpipaq214               MACH_HPIPAQ214          HPIPAQ214               1653
 at572d940dcm            MACH_AT572D940DCM       AT572D940DCM            1654
 ne1board                MACH_NE1BOARD           NE1BOARD                1655
@@ -1720,3 +1716,99 @@ htc_kaiser		MACH_HTC_KAISER		HTC_KAISER		1724
 lg_ks20                 MACH_LG_KS20            LG_KS20                 1725
 hhgps                   MACH_HHGPS              HHGPS                   1726
 nokia_n810_wimax        MACH_NOKIA_N810_WIMAX   NOKIA_N810_WIMAX        1727
+insight                 MACH_INSIGHT            INSIGHT                 1728
+sapphire                MACH_SAPPHIRE           SAPPHIRE                1729
+csb637xo                MACH_CSB637XO           CSB637XO                1730
+evisiong                MACH_EVISIONG           EVISIONG                1731
+stmp37xx                MACH_STMP37XX           STMP37XX                1732
+stmp378x                MACH_STMP38XX           STMP38XX                1733
+tnt                     MACH_TNT                TNT                     1734
+tbxt                    MACH_TBXT               TBXT                    1735
+playmate                MACH_PLAYMATE           PLAYMATE                1736
+pns10                   MACH_PNS10              PNS10                   1737
+eznavi                  MACH_EZNAVI             EZNAVI                  1738
+ps4000                  MACH_PS4000             PS4000                  1739
+ezx_a780                MACH_EZX_A780           EZX_A780                1740
+ezx_e680                MACH_EZX_E680           EZX_E680                1741
+ezx_a1200               MACH_EZX_A1200          EZX_A1200               1742
+ezx_e6                  MACH_EZX_E6             EZX_E6                  1743
+ezx_e2                  MACH_EZX_E2             EZX_E2                  1744
+ezx_a910                MACH_EZX_A910           EZX_A910                1745
+cwmx31                  MACH_CWMX31             CWMX31                  1746
+sl2312                  MACH_SL2312             SL2312                  1747
+blenny                  MACH_BLENNY             BLENNY                  1748
+ds107                   MACH_DS107              DS107                   1749
+dsx07                   MACH_DSX07              DSX07                   1750
+picocom1                MACH_PICOCOM1           PICOCOM1                1751
+lynx_wolverine          MACH_LYNX_WOLVERINE     LYNX_WOLVERINE          1752
+ubisys_p9_sc19          MACH_UBISYS_P9_SC19     UBISYS_P9_SC19          1753
+kratos_low              MACH_KRATOS_LOW         KRATOS_LOW              1754
+m700                    MACH_M700               M700                    1755
+edmini_v2               MACH_EDMINI_V2          EDMINI_V2               1756
+zipit2                  MACH_ZIPIT2             ZIPIT2                  1757
+hslfemtocell            MACH_HSLFEMTOCELL       HSLFEMTOCELL            1758
+daintree_at91           MACH_DAINTREE_AT91      DAINTREE_AT91           1759
+sg560usb                MACH_SG560USB           SG560USB                1760
+omap3_pandora           MACH_OMAP3_PANDORA      OMAP3_PANDORA           1761
+usr8200                 MACH_USR8200            USR8200                 1762
+s1s65k                  MACH_S1S65K             S1S65K                  1763
+s2s65a                  MACH_S2S65A             S2S65A                  1764
+icore                   MACH_ICORE              ICORE                   1765
+mss2                    MACH_MSS2               MSS2                    1766
+belmont                 MACH_BELMONT            BELMONT                 1767
+asusp525                MACH_ASUSP525           ASUSP525                1768
+lb88rc8480              MACH_LB88RC8480         LB88RC8480              1769
+hipxa                   MACH_HIPXA              HIPXA                   1770
+mx25_3ds                MACH_MX25_3DS           MX25_3DS                1771
+m800                    MACH_M800               M800                    1772
+omap3530_lv_som         MACH_OMAP3530_LV_SOM    OMAP3530_LV_SOM         1773
+prima_evb               MACH_PRIMA_EVB          PRIMA_EVB               1774
+mx31bt1                 MACH_MX31BT1            MX31BT1                 1775
+atlas4_evb              MACH_ATLAS4_EVB         ATLAS4_EVB              1776
+mx31cicada              MACH_MX31CICADA         MX31CICADA              1777
+mi424wr                 MACH_MI424WR            MI424WR                 1778
+axs_ultrax              MACH_AXS_ULTRAX         AXS_ULTRAX              1779
+at572d940deb            MACH_AT572D940DEB       AT572D940DEB            1780
+davinci_da8xx_evm       MACH_DAVINCI_DA8XX_EVM  DAVINCI_DA8XX_EVM       1781
+ep9302                  MACH_EP9302             EP9302                  1782
+at572d940hfeb           MACH_AT572D940HFEB      AT572D940HFEB           1783
+cybook3                 MACH_CYBOOK3            CYBOOK3                 1784
+wdg002                  MACH_WDG002             WDG002                  1785
+sg560adsl               MACH_SG560ADSL          SG560ADSL               1786
+nextio_n2800_ica        MACH_NEXTIO_N2800_ICA   NEXTIO_N2800_ICA        1787
+marvell_newdb           MACH_MARVELL_NEWDB      MARVELL_NEWDB           1789
+vandihud                MACH_VANDIHUD           VANDIHUD                1790
+magx_e8                 MACH_MAGX_E8            MAGX_E8                 1791
+magx_z6                 MACH_MAGX_Z6            MAGX_Z6                 1792
+magx_v8                 MACH_MAGX_V8            MAGX_V8                 1793
+magx_u9                 MACH_MAGX_U9            MAGX_U9                 1794
+toughcf08               MACH_TOUGHCF08          TOUGHCF08               1795
+zw4400                  MACH_ZW4400             ZW4400                  1796
+marat91                 MACH_MARAT91            MARAT91                 1797
+overo                   MACH_OVERO              OVERO                   1798
+at2440evb               MACH_AT2440EVB          AT2440EVB               1799
+neocore926              MACH_NEOCORE926         NEOCORE926              1800
+wnr854t                 MACH_WNR854T            WNR854T                 1801
+imx27                   MACH_IMX27              IMX27                   1802
+moose_db                MACH_MOOSE_DB           MOOSE_DB                1803
+fab4                    MACH_FAB4               FAB4                    1804
+htcdiamond              MACH_HTCDIAMOND         HTCDIAMOND              1805
+fiona                   MACH_FIONA              FIONA                   1806
+mxc30030_x              MACH_MXC30030_X         MXC30030_X              1807
+bmp1000                 MACH_BMP1000            BMP1000                 1808
+logi9200                MACH_LOGI9200           LOGI9200                1809
+tqma31                  MACH_TQMA31             TQMA31                  1810
+ccw9p9215js             MACH_CCW9P9215JS        CCW9P9215JS             1811
+rd88f5181l_ge           MACH_RD88F5181L_GE      RD88F5181L_GE           1812
+sifmain                 MACH_SIFMAIN            SIFMAIN                 1813
+sam9_l9261              MACH_SAM9_L9261         SAM9_L9261              1814
+cc9m2443js              MACH_CC9M2443JS         CC9M2443JS              1815
+xaria300                MACH_XARIA300           XARIA300                1816
+it9200                  MACH_IT9200             IT9200                  1817
+rd88f5181l_fxo          MACH_RD88F5181L_FXO     RD88F5181L_FXO          1818
+kriss_sensor            MACH_KRISS_SENSOR       KRISS_SENSOR            1819
+pilz_pmi5               MACH_PILZ_PMI5          PILZ_PMI5               1820
+jade                    MACH_JADE               JADE                    1821
+ks8695_softplc          MACH_KS8695_SOFTPLC     KS8695_SOFTPLC          1822
+gprisc4                 MACH_GPRISC4            GPRISC4                 1823
+stamp9260               MACH_STAMP9260          STAMP9260               1824
diff --git a/arch/avr32/Kconfig b/arch/avr32/Kconfig
index 09ad7995080c..45d63c986015 100644
--- a/arch/avr32/Kconfig
+++ b/arch/avr32/Kconfig
@@ -88,6 +88,7 @@ config PLATFORM_AT32AP
         select MMU
         select PERFORMANCE_COUNTERS
         select HAVE_GPIO_LIB
+        select GENERIC_ALLOCATOR
 
 #
 # CPU types
@@ -147,6 +148,9 @@ config PHYS_OFFSET
 
 source "kernel/Kconfig.preempt"
 
+config QUICKLIST
+        def_bool y
+
 config HAVE_ARCH_BOOTMEM_NODE
         def_bool n
 
@@ -201,6 +205,11 @@ endmenu
 
 menu "Power management options"
 
+source "kernel/power/Kconfig"
+
+config ARCH_SUSPEND_POSSIBLE
+        def_bool y
+
 menu "CPU Frequency scaling"
 
 source "drivers/cpufreq/Kconfig"
diff --git a/arch/avr32/boards/atngw100/setup.c b/arch/avr32/boards/atngw100/setup.c
index a398be284966..a51bb9fb3c89 100644
--- a/arch/avr32/boards/atngw100/setup.c
+++ b/arch/avr32/boards/atngw100/setup.c
@@ -9,6 +9,8 @@
  */
 #include <linux/clk.h>
 #include <linux/etherdevice.h>
+#include <linux/irq.h>
+#include <linux/i2c.h>
 #include <linux/i2c-gpio.h>
 #include <linux/init.h>
 #include <linux/linkage.h>
@@ -25,6 +27,13 @@
 #include <asm/arch/init.h>
 #include <asm/arch/portmux.h>
 
+/* Oscillator frequencies. These are board-specific */
+unsigned long at32_board_osc_rates[3] = {
+        [0] = 32768,    /* 32.768 kHz on RTC osc */
+        [1] = 20000000, /* 20 MHz on osc0 */
+        [2] = 12000000, /* 12 MHz on osc1 */
+};
+
 /* Initialized by bootloader-specific startup code. */
 struct tag *bootloader_tags __initdata;
 
@@ -140,6 +149,10 @@ static struct platform_device i2c_gpio_device = {
         },
 };
 
+static struct i2c_board_info __initdata i2c_info[] = {
+        /* NOTE:  original ATtiny24 firmware is at address 0x0b */
+};
+
 static int __init atngw100_init(void)
 {
         unsigned        i;
@@ -165,12 +178,28 @@ static int __init atngw100_init(void)
         }
         platform_device_register(&ngw_gpio_leds);
 
+        /* all these i2c/smbus pins should have external pullups for
+         * open-drain sharing among all I2C devices.  SDA and SCL do;
+         * PB28/EXTINT3 doesn't; it should be SMBALERT# (for PMBus),
+         * but it's not available off-board.
+         */
+        at32_select_periph(GPIO_PIN_PB(28), 0, AT32_GPIOF_PULLUP);
         at32_select_gpio(i2c_gpio_data.sda_pin,
                 AT32_GPIOF_MULTIDRV | AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
         at32_select_gpio(i2c_gpio_data.scl_pin,
                 AT32_GPIOF_MULTIDRV | AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
         platform_device_register(&i2c_gpio_device);
+        i2c_register_board_info(0, i2c_info, ARRAY_SIZE(i2c_info));
 
         return 0;
 }
 postcore_initcall(atngw100_init);
+
+static int __init atngw100_arch_init(void)
+{
+        /* set_irq_type() after the arch_initcall for EIC has run, and
+         * before the I2C subsystem could try using this IRQ.
+         */
+        return set_irq_type(AT32_EXTINT(3), IRQ_TYPE_EDGE_FALLING);
+}
+arch_initcall(atngw100_arch_init);
diff --git a/arch/avr32/boards/atstk1000/atstk1002.c b/arch/avr32/boards/atstk1000/atstk1002.c
index 000eb4220a12..86b363c1c25b 100644
--- a/arch/avr32/boards/atstk1000/atstk1002.c
+++ b/arch/avr32/boards/atstk1000/atstk1002.c
@@ -28,6 +28,12 @@
 
 #include "atstk1000.h"
 
+/* Oscillator frequencies. These are board specific */
+unsigned long at32_board_osc_rates[3] = {
+        [0] = 32768,    /* 32.768 kHz on RTC osc */
+        [1] = 20000000, /* 20 MHz on osc0 */
+        [2] = 12000000, /* 12 MHz on osc1 */
+};
 
 struct eth_addr {
         u8 addr[6];
@@ -232,7 +238,7 @@ static int __init atstk1002_init(void)
         set_hw_addr(at32_add_device_eth(1, &eth_data[1]));
 #else
         at32_add_device_lcdc(0, &atstk1000_lcdc_data,
-                             fbmem_start, fbmem_size);
+                             fbmem_start, fbmem_size, 0);
 #endif
         at32_add_device_usba(0, NULL);
 #ifndef CONFIG_BOARD_ATSTK100X_SW3_CUSTOM
diff --git a/arch/avr32/boards/atstk1000/atstk1003.c b/arch/avr32/boards/atstk1000/atstk1003.c
index a0b223df35a2..ea109f435a83 100644
--- a/arch/avr32/boards/atstk1000/atstk1003.c
+++ b/arch/avr32/boards/atstk1000/atstk1003.c
@@ -27,6 +27,13 @@
 
 #include "atstk1000.h"
 
+/* Oscillator frequencies. These are board specific */
+unsigned long at32_board_osc_rates[3] = {
+        [0] = 32768,    /* 32.768 kHz on RTC osc */
+        [1] = 20000000, /* 20 MHz on osc0 */
+        [2] = 12000000, /* 12 MHz on osc1 */
+};
+
 #ifdef CONFIG_BOARD_ATSTK1000_EXTDAC
 static struct at73c213_board_info at73c213_data = {
         .ssc_id         = 0,
diff --git a/arch/avr32/boards/atstk1000/atstk1004.c b/arch/avr32/boards/atstk1000/atstk1004.c
index e765a8652b3e..c7236df74d74 100644
--- a/arch/avr32/boards/atstk1000/atstk1004.c
+++ b/arch/avr32/boards/atstk1000/atstk1004.c
@@ -29,6 +29,13 @@
 
 #include "atstk1000.h"
 
+/* Oscillator frequencies. These are board specific */
+unsigned long at32_board_osc_rates[3] = {
+        [0] = 32768,    /* 32.768 kHz on RTC osc */
+        [1] = 20000000, /* 20 MHz on osc0 */
+        [2] = 12000000, /* 12 MHz on osc1 */
+};
+
 #ifdef CONFIG_BOARD_ATSTK1000_EXTDAC
 static struct at73c213_board_info at73c213_data = {
         .ssc_id         = 0,
@@ -133,7 +140,7 @@ static int __init atstk1004_init(void)
         at32_add_device_mci(0);
 #endif
         at32_add_device_lcdc(0, &atstk1000_lcdc_data,
-                             fbmem_start, fbmem_size);
+                             fbmem_start, fbmem_size, 0);
         at32_add_device_usba(0, NULL);
 #ifndef CONFIG_BOARD_ATSTK100X_SW3_CUSTOM
         at32_add_device_ssc(0, ATMEL_SSC_TX);
diff --git a/arch/avr32/kernel/entry-avr32b.S b/arch/avr32/kernel/entry-avr32b.S
index 5f31702d6b1c..2b398cae110c 100644
--- a/arch/avr32/kernel/entry-avr32b.S
+++ b/arch/avr32/kernel/entry-avr32b.S
@@ -74,50 +74,41 @@ exception_vectors:
         .align  2
         bral    do_dtlb_modified
 
-        /*
-         * r0 : PGD/PT/PTE
-         * r1 : Offending address
-         * r2 : Scratch register
-         * r3 : Cause (5, 12 or 13)
-         */
 #define tlbmiss_save    pushm   r0-r3
 #define tlbmiss_restore popm    r0-r3
 
-        .section .tlbx.ex.text,"ax",@progbits
+        .org    0x50
         .global itlb_miss
 itlb_miss:
         tlbmiss_save
         rjmp    tlb_miss_common
 
-        .section .tlbr.ex.text,"ax",@progbits
+        .org    0x60
 dtlb_miss_read:
         tlbmiss_save
         rjmp    tlb_miss_common
 
-        .section .tlbw.ex.text,"ax",@progbits
+        .org    0x70
 dtlb_miss_write:
         tlbmiss_save
 
         .global tlb_miss_common
+        .align  2
 tlb_miss_common:
         mfsr    r0, SYSREG_TLBEAR
         mfsr    r1, SYSREG_PTBR
 
-        /* Is it the vmalloc space? */
-        bld     r0, 31
-        brcs    handle_vmalloc_miss
-
-        /* First level lookup */
+        /*
+         * First level lookup: The PGD contains virtual pointers to
+         * the second-level page tables, but they may be NULL if not
+         * present.
+         */
 pgtbl_lookup:
         lsr     r2, r0, PGDIR_SHIFT
         ld.w    r3, r1[r2 << 2]
         bfextu  r1, r0, PAGE_SHIFT, PGDIR_SHIFT - PAGE_SHIFT
-        bld     r3, _PAGE_BIT_PRESENT
-        brcc    page_table_not_present
-
-        /* Translate to virtual address in P1. */
-        andl    r3, 0xf000
-        sbr     r3, 31
+        cp.w    r3, 0
+        breq    page_table_not_present
 
         /* Second level lookup */
         ld.w    r2, r3[r1 << 2]
@@ -148,16 +139,55 @@ pgtbl_lookup:
         tlbmiss_restore
         rete
 
-handle_vmalloc_miss:
-        /* Simply do the lookup in init's page table */
+        /* The slow path of the TLB miss handler */
+        .align  2
+page_table_not_present:
+        /* Do we need to synchronize with swapper_pg_dir? */
+        bld     r0, 31
+        brcs    sync_with_swapper_pg_dir
+
+page_not_present:
+        tlbmiss_restore
+        sub     sp, 4
+        stmts   --sp, r0-lr
+        rcall   save_full_context_ex
+        mfsr    r12, SYSREG_ECR
+        mov     r11, sp
+        rcall   do_page_fault
+        rjmp    ret_from_exception
+
+        .align  2
+sync_with_swapper_pg_dir:
+        /*
+         * If swapper_pg_dir contains a non-NULL second-level page
+         * table pointer, copy it into the current PGD. If not, we
+         * must handle it as a full-blown page fault.
+         *
+         * Jumping back to pgtbl_lookup causes an unnecessary lookup,
+         * but it is guaranteed to be a cache hit, it won't happen
+         * very often, and we absolutely do not want to sacrifice any
+         * performance in the fast path in order to improve this.
+         */
         mov     r1, lo(swapper_pg_dir)
         orh     r1, hi(swapper_pg_dir)
+        ld.w    r3, r1[r2 << 2]
+        cp.w    r3, 0
+        breq    page_not_present
+        mfsr    r1, SYSREG_PTBR
+        st.w    r1[r2 << 2], r3
         rjmp    pgtbl_lookup
 
+        /*
+         * We currently have two bytes left at this point until we
+         * crash into the system call handler...
+         *
+         * Don't worry, the assembler will let us know.
+         */
+
 
         /* ---                    System Call                    --- */
 
-        .section .scall.text,"ax",@progbits
+        .org    0x100
 system_call:
 #ifdef CONFIG_PREEMPT
         mask_interrupts
@@ -266,18 +296,6 @@ syscall_exit_work:
         brcc    syscall_exit_cont
         rjmp    enter_monitor_mode
 
-        /* The slow path of the TLB miss handler */
-page_table_not_present:
-page_not_present:
-        tlbmiss_restore
-        sub     sp, 4
-        stmts   --sp, r0-lr
-        rcall   save_full_context_ex
-        mfsr    r12, SYSREG_ECR
-        mov     r11, sp
-        rcall   do_page_fault
-        rjmp    ret_from_exception
-
         /* This function expects to find offending PC in SYSREG_RAR_EX */
         .type   save_full_context_ex, @function
         .align  2
diff --git a/arch/avr32/kernel/signal.c b/arch/avr32/kernel/signal.c
index 5616a00c10ba..c5b11f9067f1 100644
--- a/arch/avr32/kernel/signal.c
+++ b/arch/avr32/kernel/signal.c
@@ -93,6 +93,9 @@ asmlinkage int sys_rt_sigreturn(struct pt_regs *regs)
         if (restore_sigcontext(regs, &frame->uc.uc_mcontext))
                 goto badframe;
 
+        if (do_sigaltstack(&frame->uc.uc_stack, NULL, regs->sp) == -EFAULT)
+                goto badframe;
+
         pr_debug("Context restored: pc = %08lx, lr = %08lx, sp = %08lx\n",
                  regs->pc, regs->lr, regs->sp);
 
diff --git a/arch/avr32/kernel/time.c b/arch/avr32/kernel/time.c
index 00a9862380ff..abd954fb7ba0 100644
--- a/arch/avr32/kernel/time.c
+++ b/arch/avr32/kernel/time.c
@@ -7,21 +7,13 @@
  */
 #include <linux/clk.h>
 #include <linux/clockchips.h>
-#include <linux/time.h>
-#include <linux/module.h>
+#include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
-#include <linux/kernel_stat.h>
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <linux/profile.h>
-#include <linux/sysdev.h>
-#include <linux/err.h>
+#include <linux/kernel.h>
+#include <linux/time.h>
 
-#include <asm/div64.h>
 #include <asm/sysreg.h>
-#include <asm/io.h>
-#include <asm/sections.h>
 
 #include <asm/arch/pm.h>
 
diff --git a/arch/avr32/kernel/vmlinux.lds.S b/arch/avr32/kernel/vmlinux.lds.S
index 481cfd40c053..7910d41eb886 100644
--- a/arch/avr32/kernel/vmlinux.lds.S
+++ b/arch/avr32/kernel/vmlinux.lds.S
@@ -68,14 +68,6 @@ SECTIONS
                 _evba = .;
                 _text = .;
                 *(.ex.text)
-                . = 0x50;
-                *(.tlbx.ex.text)
-                . = 0x60;
-                *(.tlbr.ex.text)
-                . = 0x70;
-                *(.tlbw.ex.text)
-                . = 0x100;
-                *(.scall.text)
                 *(.irq.text)
                 KPROBES_TEXT
                 TEXT_TEXT
@@ -93,8 +85,6 @@ SECTIONS
                 __stop___ex_table = .;
         }
 
-        BUG_TABLE
-
         RODATA
 
         . = ALIGN(THREAD_SIZE);
@@ -107,6 +97,10 @@ SECTIONS
                  */
                 *(.data.init_task)
 
+                /* Then, the page-aligned data */
+                . = ALIGN(PAGE_SIZE);
+                *(.data.page_aligned)
+
                 /* Then, the cacheline aligned data */
                 . = ALIGN(L1_CACHE_BYTES);
                 *(.data.cacheline_aligned)
diff --git a/arch/avr32/lib/io-readsb.S b/arch/avr32/lib/io-readsb.S
index 2be5da7ed26b..cb2d86945559 100644
--- a/arch/avr32/lib/io-readsb.S
+++ b/arch/avr32/lib/io-readsb.S
@@ -41,7 +41,7 @@ __raw_readsb:
 2:      sub     r10, -4
         reteq   r12
 
-3:      ld.uh   r8, r12[0]
+3:      ld.ub   r8, r12[0]
         sub     r10, 1
         st.b    r11++, r8
         brne    3b
diff --git a/arch/avr32/mach-at32ap/Makefile b/arch/avr32/mach-at32ap/Makefile
index e89009439e4a..d5018e2eed25 100644
--- a/arch/avr32/mach-at32ap/Makefile
+++ b/arch/avr32/mach-at32ap/Makefile
@@ -1,3 +1,8 @@
-obj-y                           += at32ap.o clock.o intc.o extint.o pio.o hsmc.o
+obj-y                           += pdc.o clock.o intc.o extint.o pio.o hsmc.o
 obj-$(CONFIG_CPU_AT32AP700X)    += at32ap700x.o pm-at32ap700x.o
 obj-$(CONFIG_CPU_FREQ_AT32AP)   += cpufreq.o
+obj-$(CONFIG_PM)                += pm.o
+
+ifeq ($(CONFIG_PM_DEBUG),y)
+CFLAGS_pm.o     += -DDEBUG
+endif
diff --git a/arch/avr32/mach-at32ap/at32ap700x.c b/arch/avr32/mach-at32ap/at32ap700x.c
index 0f24b4f85c17..07b21b121eef 100644
--- a/arch/avr32/mach-at32ap/at32ap700x.c
+++ b/arch/avr32/mach-at32ap/at32ap700x.c
@@ -20,6 +20,7 @@
 #include <asm/arch/at32ap700x.h>
 #include <asm/arch/board.h>
 #include <asm/arch/portmux.h>
+#include <asm/arch/sram.h>
 
 #include <video/atmel_lcdc.h>
 
@@ -93,19 +94,12 @@ static struct clk devname##_##_name = {				\
 
 static DEFINE_SPINLOCK(pm_lock);
 
-unsigned long at32ap7000_osc_rates[3] = {
-        [0] = 32768,
-        /* FIXME: these are ATSTK1002-specific */
-        [1] = 20000000,
-        [2] = 12000000,
-};
-
 static struct clk osc0;
 static struct clk osc1;
 
 static unsigned long osc_get_rate(struct clk *clk)
 {
-        return at32ap7000_osc_rates[clk->index];
+        return at32_board_osc_rates[clk->index];
 }
 
 static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
@@ -682,6 +676,14 @@ static struct clk hramc_clk = {
         .users          = 1,
         .index          = 3,
 };
+static struct clk sdramc_clk = {
+        .name           = "sdramc_clk",
+        .parent         = &pbb_clk,
+        .mode           = pbb_clk_mode,
+        .get_rate       = pbb_clk_get_rate,
+        .users          = 1,
+        .index          = 14,
+};
 
 static struct resource smc0_resource[] = {
         PBMEM(0xfff03400),
@@ -841,6 +843,81 @@ void __init at32_add_system_devices(void)
 }
 
 /* --------------------------------------------------------------------
+ *  PSIF
+ * -------------------------------------------------------------------- */
+static struct resource atmel_psif0_resource[] __initdata = {
+        {
+                .start  = 0xffe03c00,
+                .end    = 0xffe03cff,
+                .flags  = IORESOURCE_MEM,
+        },
+        IRQ(18),
+};
+static struct clk atmel_psif0_pclk = {
+        .name           = "pclk",
+        .parent         = &pba_clk,
+        .mode           = pba_clk_mode,
+        .get_rate       = pba_clk_get_rate,
+        .index          = 15,
+};
+
+static struct resource atmel_psif1_resource[] __initdata = {
+        {
+                .start  = 0xffe03d00,
+                .end    = 0xffe03dff,
+                .flags  = IORESOURCE_MEM,
+        },
+        IRQ(18),
+};
+static struct clk atmel_psif1_pclk = {
+        .name           = "pclk",
+        .parent         = &pba_clk,
+        .mode           = pba_clk_mode,
+        .get_rate       = pba_clk_get_rate,
+        .index          = 15,
+};
+
+struct platform_device *__init at32_add_device_psif(unsigned int id)
+{
+        struct platform_device *pdev;
+
+        if (!(id == 0 || id == 1))
+                return NULL;
+
+        pdev = platform_device_alloc("atmel_psif", id);
+        if (!pdev)
+                return NULL;
+
+        switch (id) {
+        case 0:
+                if (platform_device_add_resources(pdev, atmel_psif0_resource,
+                                        ARRAY_SIZE(atmel_psif0_resource)))
+                        goto err_add_resources;
+                atmel_psif0_pclk.dev = &pdev->dev;
+                select_peripheral(PA(8), PERIPH_A, 0); /* CLOCK */
+                select_peripheral(PA(9), PERIPH_A, 0); /* DATA  */
+                break;
+        case 1:
+                if (platform_device_add_resources(pdev, atmel_psif1_resource,
+                                        ARRAY_SIZE(atmel_psif1_resource)))
+                        goto err_add_resources;
+                atmel_psif1_pclk.dev = &pdev->dev;
+                select_peripheral(PB(11), PERIPH_A, 0); /* CLOCK */
+                select_peripheral(PB(12), PERIPH_A, 0); /* DATA  */
+                break;
+        default:
+                return NULL;
+        }
+
+        platform_device_add(pdev);
+        return pdev;
+
+err_add_resources:
+        platform_device_put(pdev);
+        return NULL;
+}
+
+/* --------------------------------------------------------------------
  *  USART
  * -------------------------------------------------------------------- */
 
@@ -1113,7 +1190,8 @@ at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
         switch (id) {
         case 0:
                 pdev = &atmel_spi0_device;
-                select_peripheral(PA(0),  PERIPH_A, 0); /* MISO  */
+                /* pullup MISO so a level is always defined */
+                select_peripheral(PA(0),  PERIPH_A, AT32_GPIOF_PULLUP);
                 select_peripheral(PA(1),  PERIPH_A, 0); /* MOSI  */
                 select_peripheral(PA(2),  PERIPH_A, 0); /* SCK   */
                 at32_spi_setup_slaves(0, b, n, spi0_pins);
@@ -1121,7 +1199,8 @@ at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
 
         case 1:
                 pdev = &atmel_spi1_device;
-                select_peripheral(PB(0),  PERIPH_B, 0); /* MISO  */
+                /* pullup MISO so a level is always defined */
+                select_peripheral(PB(0),  PERIPH_B, AT32_GPIOF_PULLUP);
                 select_peripheral(PB(1),  PERIPH_B, 0); /* MOSI  */
                 select_peripheral(PB(5),  PERIPH_B, 0); /* SCK   */
                 at32_spi_setup_slaves(1, b, n, spi1_pins);
@@ -1264,7 +1343,8 @@ static struct clk atmel_lcdfb0_pixclk = {
 
 struct platform_device *__init
 at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
-                     unsigned long fbmem_start, unsigned long fbmem_len)
+                     unsigned long fbmem_start, unsigned long fbmem_len,
+                     unsigned int pin_config)
 {
         struct platform_device *pdev;
         struct atmel_lcdfb_info *info;
@@ -1291,37 +1371,77 @@ at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
         switch (id) {
         case 0:
                 pdev = &atmel_lcdfb0_device;
-                select_peripheral(PC(19), PERIPH_A, 0); /* CC     */
-                select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC  */
-                select_peripheral(PC(21), PERIPH_A, 0); /* PCLK   */
-                select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC  */
-                select_peripheral(PC(23), PERIPH_A, 0); /* DVAL   */
-                select_peripheral(PC(24), PERIPH_A, 0); /* MODE   */
-                select_peripheral(PC(25), PERIPH_A, 0); /* PWR    */
-                select_peripheral(PC(26), PERIPH_A, 0); /* DATA0  */
-                select_peripheral(PC(27), PERIPH_A, 0); /* DATA1  */
-                select_peripheral(PC(28), PERIPH_A, 0); /* DATA2  */
-                select_peripheral(PC(29), PERIPH_A, 0); /* DATA3  */
-                select_peripheral(PC(30), PERIPH_A, 0); /* DATA4  */
-                select_peripheral(PC(31), PERIPH_A, 0); /* DATA5  */
-                select_peripheral(PD(0),  PERIPH_A, 0); /* DATA6  */
-                select_peripheral(PD(1),  PERIPH_A, 0); /* DATA7  */
-                select_peripheral(PD(2),  PERIPH_A, 0); /* DATA8  */
-                select_peripheral(PD(3),  PERIPH_A, 0); /* DATA9  */
-                select_peripheral(PD(4),  PERIPH_A, 0); /* DATA10 */
-                select_peripheral(PD(5),  PERIPH_A, 0); /* DATA11 */
-                select_peripheral(PD(6),  PERIPH_A, 0); /* DATA12 */
-                select_peripheral(PD(7),  PERIPH_A, 0); /* DATA13 */
-                select_peripheral(PD(8),  PERIPH_A, 0); /* DATA14 */
-                select_peripheral(PD(9),  PERIPH_A, 0); /* DATA15 */
-                select_peripheral(PD(10), PERIPH_A, 0); /* DATA16 */
-                select_peripheral(PD(11), PERIPH_A, 0); /* DATA17 */
-                select_peripheral(PD(12), PERIPH_A, 0); /* DATA18 */
-                select_peripheral(PD(13), PERIPH_A, 0); /* DATA19 */
-                select_peripheral(PD(14), PERIPH_A, 0); /* DATA20 */
-                select_peripheral(PD(15), PERIPH_A, 0); /* DATA21 */
-                select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
-                select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
+
+                switch (pin_config) {
+                case 0:
+                        select_peripheral(PC(19), PERIPH_A, 0); /* CC     */
+                        select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC  */
+                        select_peripheral(PC(21), PERIPH_A, 0); /* PCLK   */
+                        select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC  */
+                        select_peripheral(PC(23), PERIPH_A, 0); /* DVAL   */
+                        select_peripheral(PC(24), PERIPH_A, 0); /* MODE   */
+                        select_peripheral(PC(25), PERIPH_A, 0); /* PWR    */
+                        select_peripheral(PC(26), PERIPH_A, 0); /* DATA0  */
+                        select_peripheral(PC(27), PERIPH_A, 0); /* DATA1  */
+                        select_peripheral(PC(28), PERIPH_A, 0); /* DATA2  */
+                        select_peripheral(PC(29), PERIPH_A, 0); /* DATA3  */
+                        select_peripheral(PC(30), PERIPH_A, 0); /* DATA4  */
+                        select_peripheral(PC(31), PERIPH_A, 0); /* DATA5  */
+                        select_peripheral(PD(0),  PERIPH_A, 0); /* DATA6  */
+                        select_peripheral(PD(1),  PERIPH_A, 0); /* DATA7  */
+                        select_peripheral(PD(2),  PERIPH_A, 0); /* DATA8  */
+                        select_peripheral(PD(3),  PERIPH_A, 0); /* DATA9  */
+                        select_peripheral(PD(4),  PERIPH_A, 0); /* DATA10 */
+                        select_peripheral(PD(5),  PERIPH_A, 0); /* DATA11 */
+                        select_peripheral(PD(6),  PERIPH_A, 0); /* DATA12 */
+                        select_peripheral(PD(7),  PERIPH_A, 0); /* DATA13 */
+                        select_peripheral(PD(8),  PERIPH_A, 0); /* DATA14 */
+                        select_peripheral(PD(9),  PERIPH_A, 0); /* DATA15 */
+                        select_peripheral(PD(10), PERIPH_A, 0); /* DATA16 */
+                        select_peripheral(PD(11), PERIPH_A, 0); /* DATA17 */
+                        select_peripheral(PD(12), PERIPH_A, 0); /* DATA18 */
+                        select_peripheral(PD(13), PERIPH_A, 0); /* DATA19 */
+                        select_peripheral(PD(14), PERIPH_A, 0); /* DATA20 */
+                        select_peripheral(PD(15), PERIPH_A, 0); /* DATA21 */
+                        select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
+                        select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
+                        break;
+                case 1:
+                        select_peripheral(PE(0),  PERIPH_B, 0); /* CC     */
+                        select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC  */
+                        select_peripheral(PC(21), PERIPH_A, 0); /* PCLK   */
+                        select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC  */
+                        select_peripheral(PE(1),  PERIPH_B, 0); /* DVAL   */
+                        select_peripheral(PE(2),  PERIPH_B, 0); /* MODE   */
+                        select_peripheral(PC(25), PERIPH_A, 0); /* PWR    */
+                        select_peripheral(PE(3),  PERIPH_B, 0); /* DATA0  */
+                        select_peripheral(PE(4),  PERIPH_B, 0); /* DATA1  */
+                        select_peripheral(PE(5),  PERIPH_B, 0); /* DATA2  */
+                        select_peripheral(PE(6),  PERIPH_B, 0); /* DATA3  */
+                        select_peripheral(PE(7),  PERIPH_B, 0); /* DATA4  */
+                        select_peripheral(PC(31), PERIPH_A, 0); /* DATA5  */
+                        select_peripheral(PD(0),  PERIPH_A, 0); /* DATA6  */
+                        select_peripheral(PD(1),  PERIPH_A, 0); /* DATA7  */
+                        select_peripheral(PE(8),  PERIPH_B, 0); /* DATA8  */
+                        select_peripheral(PE(9),  PERIPH_B, 0); /* DATA9  */
+                        select_peripheral(PE(10), PERIPH_B, 0); /* DATA10 */
+                        select_peripheral(PE(11), PERIPH_B, 0); /* DATA11 */
+                        select_peripheral(PE(12), PERIPH_B, 0); /* DATA12 */
+                        select_peripheral(PD(7),  PERIPH_A, 0); /* DATA13 */
+                        select_peripheral(PD(8),  PERIPH_A, 0); /* DATA14 */
+                        select_peripheral(PD(9),  PERIPH_A, 0); /* DATA15 */
+                        select_peripheral(PE(13), PERIPH_B, 0); /* DATA16 */
+                        select_peripheral(PE(14), PERIPH_B, 0); /* DATA17 */
+                        select_peripheral(PE(15), PERIPH_B, 0); /* DATA18 */
+                        select_peripheral(PE(16), PERIPH_B, 0); /* DATA19 */
+                        select_peripheral(PE(17), PERIPH_B, 0); /* DATA20 */
+                        select_peripheral(PE(18), PERIPH_B, 0); /* DATA21 */
+                        select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
+                        select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
+                        break;
+                default:
+                        goto err_invalid_id;
+                }
 
                 clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
                 clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
@@ -1360,7 +1480,7 @@ static struct resource atmel_pwm0_resource[] __initdata = {
         IRQ(24),
 };
 static struct clk atmel_pwm0_mck = {
-        .name           = "mck",
+        .name           = "pwm_clk",
         .parent         = &pbb_clk,
         .mode           = pbb_clk_mode,
         .get_rate       = pbb_clk_get_rate,
@@ -1887,6 +2007,7 @@ struct clk *at32_clock_list[] = {
         &hmatrix_clk,
         &ebi_clk,
         &hramc_clk,
+        &sdramc_clk,
         &smc0_pclk,
         &smc0_mck,
         &pdc_hclk,
@@ -1900,6 +2021,8 @@ struct clk *at32_clock_list[] = {
         &pio4_mck,
         &at32_tcb0_t0_clk,
         &at32_tcb1_t0_clk,
+        &atmel_psif0_pclk,
+        &atmel_psif1_pclk,
         &atmel_usart0_usart,
         &atmel_usart1_usart,
         &atmel_usart2_usart,
@@ -1935,16 +2058,7 @@ struct clk *at32_clock_list[] = {
 };
 unsigned int at32_nr_clocks = ARRAY_SIZE(at32_clock_list);
 
-void __init at32_portmux_init(void)
-{
-        at32_init_pio(&pio0_device);
-        at32_init_pio(&pio1_device);
-        at32_init_pio(&pio2_device);
-        at32_init_pio(&pio3_device);
-        at32_init_pio(&pio4_device);
-}
-
-void __init at32_clock_init(void)
+void __init setup_platform(void)
 {
         u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
         int i;
@@ -1999,4 +2113,36 @@ void __init at32_clock_init(void)
         pm_writel(HSB_MASK, hsb_mask);
         pm_writel(PBA_MASK, pba_mask);
         pm_writel(PBB_MASK, pbb_mask);
+
+        /* Initialize the port muxes */
+        at32_init_pio(&pio0_device);
+        at32_init_pio(&pio1_device);
+        at32_init_pio(&pio2_device);
+        at32_init_pio(&pio3_device);
+        at32_init_pio(&pio4_device);
+}
+
+struct gen_pool *sram_pool;
+
+static int __init sram_init(void)
+{
+        struct gen_pool *pool;
+
+        /* 1KiB granularity */
+        pool = gen_pool_create(10, -1);
+        if (!pool)
+                goto fail;
+
+        if (gen_pool_add(pool, 0x24000000, 0x8000, -1))
+                goto err_pool_add;
+
+        sram_pool = pool;
+        return 0;
+
+err_pool_add:
+        gen_pool_destroy(pool);
+fail:
+        pr_err("Failed to create SRAM pool\n");
+        return -ENOMEM;
 }
+core_initcall(sram_init);
diff --git a/arch/avr32/mach-at32ap/intc.c b/arch/avr32/mach-at32ap/intc.c
index 097cf4e84052..994c4545e2b7 100644
--- a/arch/avr32/mach-at32ap/intc.c
+++ b/arch/avr32/mach-at32ap/intc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2006 Atmel Corporation
+ * Copyright (C) 2006, 2008 Atmel Corporation
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -12,14 +12,20 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/platform_device.h>
+#include <linux/sysdev.h>
 
 #include <asm/io.h>
 
 #include "intc.h"
 
 struct intc {
-        void __iomem    *regs;
-        struct irq_chip chip;
+        void __iomem            *regs;
+        struct irq_chip         chip;
+        struct sys_device       sysdev;
+#ifdef CONFIG_PM
+        unsigned long           suspend_ipr;
+        unsigned long           saved_ipr[64];
+#endif
 };
 
 extern struct platform_device at32_intc0_device;
@@ -136,6 +142,74 @@ fail:
         panic("Interrupt controller initialization failed!\n");
 }
 
+#ifdef CONFIG_PM
+void intc_set_suspend_handler(unsigned long offset)
+{
+        intc0.suspend_ipr = offset;
+}
+
+static int intc_suspend(struct sys_device *sdev, pm_message_t state)
+{
+        struct intc *intc = container_of(sdev, struct intc, sysdev);
+        int i;
+
+        if (unlikely(!irqs_disabled())) {
+                pr_err("intc_suspend: called with interrupts enabled\n");
+                return -EINVAL;
+        }
+
+        if (unlikely(!intc->suspend_ipr)) {
+                pr_err("intc_suspend: suspend_ipr not initialized\n");
+                return -EINVAL;
+        }
+
+        for (i = 0; i < 64; i++) {
+                intc->saved_ipr[i] = intc_readl(intc, INTPR0 + 4 * i);
+                intc_writel(intc, INTPR0 + 4 * i, intc->suspend_ipr);
+        }
+
+        return 0;
+}
+
+static int intc_resume(struct sys_device *sdev)
+{
+        struct intc *intc = container_of(sdev, struct intc, sysdev);
+        int i;
+
+        WARN_ON(!irqs_disabled());
+
+        for (i = 0; i < 64; i++)
+                intc_writel(intc, INTPR0 + 4 * i, intc->saved_ipr[i]);
+
+        return 0;
+}
+#else
+#define intc_suspend    NULL
+#define intc_resume     NULL
+#endif
+
+static struct sysdev_class intc_class = {
+        .name           = "intc",
+        .suspend        = intc_suspend,
+        .resume         = intc_resume,
+};
+
+static int __init intc_init_sysdev(void)
+{
+        int ret;
+
+        ret = sysdev_class_register(&intc_class);
+        if (ret)
+                return ret;
+
+        intc0.sysdev.id = 0;
+        intc0.sysdev.cls = &intc_class;
+        ret = sysdev_register(&intc0.sysdev);
+
+        return ret;
+}
+device_initcall(intc_init_sysdev);
+
 unsigned long intc_get_pending(unsigned int group)
 {
         return intc_readl(&intc0, INTREQ0 + 4 * group);
diff --git a/arch/avr32/mach-at32ap/at32ap.c b/arch/avr32/mach-at32ap/pdc.c
index 7c4987f3287a..1040bda4fda7 100644
--- a/arch/avr32/mach-at32ap/at32ap.c
+++ b/arch/avr32/mach-at32ap/pdc.c
@@ -11,14 +11,6 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 
-#include <asm/arch/init.h>
-
-void __init setup_platform(void)
-{
-        at32_clock_init();
-        at32_portmux_init();
-}
-
 static int __init pdc_probe(struct platform_device *pdev)
 {
         struct clk *pclk, *hclk;
diff --git a/arch/avr32/mach-at32ap/pio.c b/arch/avr32/mach-at32ap/pio.c
index 38a8fa31c0b5..60da03ba7117 100644
--- a/arch/avr32/mach-at32ap/pio.c
+++ b/arch/avr32/mach-at32ap/pio.c
@@ -318,6 +318,8 @@ static void pio_bank_show(struct seq_file *s, struct gpio_chip *chip)
                 const char *label;
 
                 label = gpiochip_is_requested(chip, i);
+                if (!label && (imr & mask))
+                        label = "[irq]";
                 if (!label)
                         continue;
 
diff --git a/arch/avr32/mach-at32ap/pio.h b/arch/avr32/mach-at32ap/pio.h
index 7795116a483a..9484dfcc08f2 100644
--- a/arch/avr32/mach-at32ap/pio.h
+++ b/arch/avr32/mach-at32ap/pio.h
@@ -57,7 +57,7 @@
 
 /* Bitfields in IFDR */
 
-/* Bitfields in ISFR */
+/* Bitfields in IFSR */
 
 /* Bitfields in SODR */
 
diff --git a/arch/avr32/mach-at32ap/pm-at32ap700x.S b/arch/avr32/mach-at32ap/pm-at32ap700x.S
index 949e2485e278..0a53ad314ff4 100644
--- a/arch/avr32/mach-at32ap/pm-at32ap700x.S
+++ b/arch/avr32/mach-at32ap/pm-at32ap700x.S
@@ -12,6 +12,12 @@
 #include <asm/thread_info.h>
 #include <asm/arch/pm.h>
 
+#include "pm.h"
+#include "sdramc.h"
+
+/* Same as 0xfff00000 but fits in a 21 bit signed immediate */
+#define PM_BASE -0x100000
+
         .section .bss, "wa", @nobits
         .global disable_idle_sleep
         .type   disable_idle_sleep, @object
@@ -64,3 +70,105 @@ cpu_idle_skip_sleep:
         unmask_interrupts
         retal   r12
         .size   cpu_idle_skip_sleep, . - cpu_idle_skip_sleep
+
+#ifdef CONFIG_PM
+        .section .init.text, "ax", @progbits
+
+        .global pm_exception
+        .type   pm_exception, @function
+pm_exception:
+        /*
+         * Exceptions are masked when we switch to this handler, so
+         * we'll only get "unrecoverable" exceptions (offset 0.)
+         */
+        sub     r12, pc, . - .Lpanic_msg
+        lddpc   pc, .Lpanic_addr
+
+        .align  2
+.Lpanic_addr:
+        .long   panic
+.Lpanic_msg:
+        .asciz  "Unrecoverable exception during suspend\n"
+        .size   pm_exception, . - pm_exception
+
+        .global pm_irq0
+        .type   pm_irq0, @function
+pm_irq0:
+        /* Disable interrupts and return after the sleep instruction */
+        mfsr    r9, SYSREG_RSR_INT0
+        mtsr    SYSREG_RAR_INT0, r8
+        sbr     r9, SYSREG_GM_OFFSET
+        mtsr    SYSREG_RSR_INT0, r9
+        rete
+
+        /*
+         * void cpu_enter_standby(unsigned long sdramc_base)
+         *
+         * Enter PM_SUSPEND_STANDBY mode. At this point, all drivers
+         * are suspended and interrupts are disabled. Interrupts
+         * marked as 'wakeup' event sources may still come along and
+         * get us out of here.
+         *
+         * The SDRAM will be put into self-refresh mode (which does
+         * not require a clock from the CPU), and the CPU will be put
+         * into "frozen" mode (HSB bus stopped). The SDRAM controller
+         * will automatically bring the SDRAM into normal mode on the
+         * first access, and the power manager will automatically
+         * start the HSB and CPU clocks upon a wakeup event.
+         *
+         * This code uses the same "skip sleep" technique as above.
+         * It is very important that we jump directly to
+         * cpu_after_sleep after the sleep instruction since that's
+         * where we'll end up if the interrupt handler decides that we
+         * need to skip the sleep instruction.
+         */
+        .global pm_standby
+        .type   pm_standby, @function
+pm_standby:
+        /*
+         * interrupts are already masked at this point, and EVBA
+         * points to pm_exception above.
+         */
+        ld.w    r10, r12[SDRAMC_LPR]
+        sub     r8, pc, . - 1f          /* return address for irq handler */
+        mov     r11, SDRAMC_LPR_LPCB_SELF_RFR
+        bfins   r10, r11, 0, 2          /* LPCB <- self Refresh */
+        sync    0                       /* flush write buffer */
+        st.w    r12[SDRAMC_LPR], r11    /* put SDRAM in self-refresh mode */
+        ld.w    r11, r12[SDRAMC_LPR]
+        unmask_interrupts
+        sleep   CPU_SLEEP_FROZEN
+1:      mask_interrupts
+        retal   r12
+        .size   pm_standby, . - pm_standby
+
+        .global pm_suspend_to_ram
+        .type   pm_suspend_to_ram, @function
+pm_suspend_to_ram:
+        /*
+         * interrupts are already masked at this point, and EVBA
+         * points to pm_exception above.
+         */
+        mov     r11, 0
+        cache   r11[2], 8               /* clean all dcache lines */
+        sync    0                       /* flush write buffer */
+        ld.w    r10, r12[SDRAMC_LPR]
+        sub     r8, pc, . - 1f          /* return address for irq handler */
+        mov     r11, SDRAMC_LPR_LPCB_SELF_RFR
+        bfins   r10, r11, 0, 2          /* LPCB <- self refresh */
+        st.w    r12[SDRAMC_LPR], r10    /* put SDRAM in self-refresh mode */
+        ld.w    r11, r12[SDRAMC_LPR]
+
+        unmask_interrupts
+        sleep   CPU_SLEEP_STOP
+1:      mask_interrupts
+
+        retal   r12
+        .size   pm_suspend_to_ram, . - pm_suspend_to_ram
+
+        .global pm_sram_end
+        .type   pm_sram_end, @function
+pm_sram_end:
+        .size   pm_sram_end, 0
+
+#endif /* CONFIG_PM */
diff --git a/arch/avr32/mach-at32ap/pm.c b/arch/avr32/mach-at32ap/pm.c
new file mode 100644
index 000000000000..0b764320135d
--- /dev/null
+++ b/arch/avr32/mach-at32ap/pm.c
@@ -0,0 +1,245 @@
+/*
+ * AVR32 AP Power Management
+ *
+ * Copyright (C) 2008 Atmel Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ */
+#include <linux/io.h>
+#include <linux/suspend.h>
+#include <linux/vmalloc.h>
+
+#include <asm/cacheflush.h>
+#include <asm/sysreg.h>
+
+#include <asm/arch/pm.h>
+#include <asm/arch/sram.h>
+
+/* FIXME: This is only valid for AP7000 */
+#define SDRAMC_BASE     0xfff03800
+
+#include "sdramc.h"
+
+#define SRAM_PAGE_FLAGS (SYSREG_BIT(TLBELO_D) | SYSREG_BF(SZ, 1)        \
+                                | SYSREG_BF(AP, 3) | SYSREG_BIT(G))
+
+
+static unsigned long    pm_sram_start;
+static size_t           pm_sram_size;
+static struct vm_struct *pm_sram_area;
+
+static void (*avr32_pm_enter_standby)(unsigned long sdramc_base);
+static void (*avr32_pm_enter_str)(unsigned long sdramc_base);
+
+/*
+ * Must be called with interrupts disabled. Exceptions will be masked
+ * on return (i.e. all exceptions will be "unrecoverable".)
+ */
+static void *avr32_pm_map_sram(void)
+{
+        unsigned long   vaddr;
+        unsigned long   page_addr;
+        u32             tlbehi;
+        u32             mmucr;
+
+        vaddr = (unsigned long)pm_sram_area->addr;
+        page_addr = pm_sram_start & PAGE_MASK;
+
+        /*
+         * Mask exceptions and grab the first TLB entry. We won't be
+         * needing it while sleeping.
+         */
+        asm volatile("ssrf      %0" : : "i"(SYSREG_EM_OFFSET) : "memory");
+
+        mmucr = sysreg_read(MMUCR);
+        tlbehi = sysreg_read(TLBEHI);
+        sysreg_write(MMUCR, SYSREG_BFINS(DRP, 0, mmucr));
+
+        tlbehi = SYSREG_BF(ASID, SYSREG_BFEXT(ASID, tlbehi));
+        tlbehi |= vaddr & PAGE_MASK;
+        tlbehi |= SYSREG_BIT(TLBEHI_V);
+
+        sysreg_write(TLBELO, page_addr | SRAM_PAGE_FLAGS);
+        sysreg_write(TLBEHI, tlbehi);
+        __builtin_tlbw();
+
+        return (void *)(vaddr + pm_sram_start - page_addr);
+}
+
+/*
+ * Must be called with interrupts disabled. Exceptions will be
+ * unmasked on return.
+ */
+static void avr32_pm_unmap_sram(void)
+{
+        u32     mmucr;
+        u32     tlbehi;
+        u32     tlbarlo;
+
+        /* Going to update TLB entry at index 0 */
+        mmucr = sysreg_read(MMUCR);
+        tlbehi = sysreg_read(TLBEHI);
+        sysreg_write(MMUCR, SYSREG_BFINS(DRP, 0, mmucr));
+
+        /* Clear the "valid" bit */
+        tlbehi = SYSREG_BF(ASID, SYSREG_BFEXT(ASID, tlbehi));
+        sysreg_write(TLBEHI, tlbehi);
+
+        /* Mark it as "not accessed" */
+        tlbarlo = sysreg_read(TLBARLO);
+        sysreg_write(TLBARLO, tlbarlo | 0x80000000U);
+
+        /* Update the TLB */
+        __builtin_tlbw();
+
+        /* Unmask exceptions */
+        asm volatile("csrf      %0" : : "i"(SYSREG_EM_OFFSET) : "memory");
+}
+
+static int avr32_pm_valid_state(suspend_state_t state)
+{
+        switch (state) {
+        case PM_SUSPEND_ON:
+        case PM_SUSPEND_STANDBY:
+        case PM_SUSPEND_MEM:
+                return 1;
+
+        default:
+                return 0;
+        }
+}
+
+static int avr32_pm_enter(suspend_state_t state)
+{
+        u32             lpr_saved;
+        u32             evba_saved;
+        void            *sram;
+
+        switch (state) {
+        case PM_SUSPEND_STANDBY:
+                sram = avr32_pm_map_sram();
+
+                /* Switch to in-sram exception handlers */
+                evba_saved = sysreg_read(EVBA);
+                sysreg_write(EVBA, (unsigned long)sram);
+
+                /*
+                 * Save the LPR register so that we can re-enable
+                 * SDRAM Low Power mode on resume.
+                 */
+                lpr_saved = sdramc_readl(LPR);
+                pr_debug("%s: Entering standby...\n", __func__);
+                avr32_pm_enter_standby(SDRAMC_BASE);
+                sdramc_writel(LPR, lpr_saved);
+
+                /* Switch back to regular exception handlers */
+                sysreg_write(EVBA, evba_saved);
+
+                avr32_pm_unmap_sram();
+                break;
+
+        case PM_SUSPEND_MEM:
+                sram = avr32_pm_map_sram();
+
+                /* Switch to in-sram exception handlers */
+                evba_saved = sysreg_read(EVBA);
+                sysreg_write(EVBA, (unsigned long)sram);
+
+                /*
+                 * Save the LPR register so that we can re-enable
+                 * SDRAM Low Power mode on resume.
+                 */
+                lpr_saved = sdramc_readl(LPR);
+                pr_debug("%s: Entering suspend-to-ram...\n", __func__);
+                avr32_pm_enter_str(SDRAMC_BASE);
+                sdramc_writel(LPR, lpr_saved);
+
+                /* Switch back to regular exception handlers */
+                sysreg_write(EVBA, evba_saved);
+
+                avr32_pm_unmap_sram();
+                break;
+
+        case PM_SUSPEND_ON:
+                pr_debug("%s: Entering idle...\n", __func__);
+                cpu_enter_idle();
+                break;
+
+        default:
+                pr_debug("%s: Invalid suspend state %d\n", __func__, state);
+                goto out;
+        }
+
+        pr_debug("%s: wakeup\n", __func__);
+
+out:
+        return 0;
+}
+
+static struct platform_suspend_ops avr32_pm_ops = {
+        .valid  = avr32_pm_valid_state,
+        .enter  = avr32_pm_enter,
+};
+
+static unsigned long avr32_pm_offset(void *symbol)
+{
+        extern u8 pm_exception[];
+
+        return (unsigned long)symbol - (unsigned long)pm_exception;
+}
+
+static int __init avr32_pm_init(void)
+{
+        extern u8 pm_exception[];
+        extern u8 pm_irq0[];
+        extern u8 pm_standby[];
+        extern u8 pm_suspend_to_ram[];
+        extern u8 pm_sram_end[];
+        void *dst;
+
+        /*
+         * To keep things simple, we depend on not needing more than a
+         * single page.
+         */
+        pm_sram_size = avr32_pm_offset(pm_sram_end);
+        if (pm_sram_size > PAGE_SIZE)
+                goto err;
+
+        pm_sram_start = sram_alloc(pm_sram_size);
+        if (!pm_sram_start)
+                goto err_alloc_sram;
+
+        /* Grab a virtual area we can use later on. */
+        pm_sram_area = get_vm_area(pm_sram_size, VM_IOREMAP);
+        if (!pm_sram_area)
+                goto err_vm_area;
+        pm_sram_area->phys_addr = pm_sram_start;
+
+        local_irq_disable();
+        dst = avr32_pm_map_sram();
+        memcpy(dst, pm_exception, pm_sram_size);
+        flush_dcache_region(dst, pm_sram_size);
+        invalidate_icache_region(dst, pm_sram_size);
+        avr32_pm_unmap_sram();
+        local_irq_enable();
+
+        avr32_pm_enter_standby = dst + avr32_pm_offset(pm_standby);
+        avr32_pm_enter_str = dst + avr32_pm_offset(pm_suspend_to_ram);
+        intc_set_suspend_handler(avr32_pm_offset(pm_irq0));
+
+        suspend_set_ops(&avr32_pm_ops);
+
+        printk("AVR32 AP Power Management enabled\n");
+
+        return 0;
+
+err_vm_area:
+        sram_free(pm_sram_start, pm_sram_size);
+err_alloc_sram:
+err:
+        pr_err("AVR32 Power Management initialization failed\n");
+        return -ENOMEM;
+}
+arch_initcall(avr32_pm_init);
diff --git a/arch/avr32/mach-at32ap/sdramc.h b/arch/avr32/mach-at32ap/sdramc.h
new file mode 100644
index 000000000000..66eeaed49073
--- /dev/null
+++ b/arch/avr32/mach-at32ap/sdramc.h
@@ -0,0 +1,76 @@
+/*
+ * Register definitions for the AT32AP SDRAM Controller
+ *
+ * Copyright (C) 2008 Atmel Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ */
+
+/* Register offsets */
+#define SDRAMC_MR                       0x0000
+#define SDRAMC_TR                       0x0004
+#define SDRAMC_CR                       0x0008
+#define SDRAMC_HSR                      0x000c
+#define SDRAMC_LPR                      0x0010
+#define SDRAMC_IER                      0x0014
+#define SDRAMC_IDR                      0x0018
+#define SDRAMC_IMR                      0x001c
+#define SDRAMC_ISR                      0x0020
+#define SDRAMC_MDR                      0x0024
+
+/* MR - Mode Register */
+#define SDRAMC_MR_MODE_NORMAL           (  0 <<  0)
+#define SDRAMC_MR_MODE_NOP              (  1 <<  0)
+#define SDRAMC_MR_MODE_BANKS_PRECHARGE  (  2 <<  0)
+#define SDRAMC_MR_MODE_LOAD_MODE        (  3 <<  0)
+#define SDRAMC_MR_MODE_AUTO_REFRESH     (  4 <<  0)
+#define SDRAMC_MR_MODE_EXT_LOAD_MODE    (  5 <<  0)
+#define SDRAMC_MR_MODE_POWER_DOWN       (  6 <<  0)
+
+/* CR - Configuration Register */
+#define SDRAMC_CR_NC_8_BITS             (  0 <<  0)
+#define SDRAMC_CR_NC_9_BITS             (  1 <<  0)
+#define SDRAMC_CR_NC_10_BITS            (  2 <<  0)
+#define SDRAMC_CR_NC_11_BITS            (  3 <<  0)
+#define SDRAMC_CR_NR_11_BITS            (  0 <<  2)
+#define SDRAMC_CR_NR_12_BITS            (  1 <<  2)
+#define SDRAMC_CR_NR_13_BITS            (  2 <<  2)
+#define SDRAMC_CR_NB_2_BANKS            (  0 <<  4)
+#define SDRAMC_CR_NB_4_BANKS            (  1 <<  4)
+#define SDRAMC_CR_CAS(x)                ((x) <<  5)
+#define SDRAMC_CR_DBW_32_BITS           (  0 <<  7)
+#define SDRAMC_CR_DBW_16_BITS           (  1 <<  7)
+#define SDRAMC_CR_TWR(x)                ((x) <<  8)
+#define SDRAMC_CR_TRC(x)                ((x) << 12)
+#define SDRAMC_CR_TRP(x)                ((x) << 16)
+#define SDRAMC_CR_TRCD(x)               ((x) << 20)
+#define SDRAMC_CR_TRAS(x)               ((x) << 24)
+#define SDRAMC_CR_TXSR(x)               ((x) << 28)
+
+/* HSR - High Speed Register */
+#define SDRAMC_HSR_DA                   (  1 <<  0)
+
+/* LPR - Low Power Register */
+#define SDRAMC_LPR_LPCB_INHIBIT         (  0 <<  0)
+#define SDRAMC_LPR_LPCB_SELF_RFR        (  1 <<  0)
+#define SDRAMC_LPR_LPCB_PDOWN           (  2 <<  0)
+#define SDRAMC_LPR_LPCB_DEEP_PDOWN      (  3 <<  0)
+#define SDRAMC_LPR_PASR(x)              ((x) <<  4)
+#define SDRAMC_LPR_TCSR(x)              ((x) <<  8)
+#define SDRAMC_LPR_DS(x)                ((x) << 10)
+#define SDRAMC_LPR_TIMEOUT(x)           ((x) << 12)
+
+/* IER/IDR/IMR/ISR - Interrupt Enable/Disable/Mask/Status Register */
+#define SDRAMC_ISR_RES                  (  1 <<  0)
+
+/* MDR - Memory Device Register */
+#define SDRAMC_MDR_MD_SDRAM             (  0 <<  0)
+#define SDRAMC_MDR_MD_LOW_PWR_SDRAM     (  1 <<  0)
+
+/* Register access macros */
+#define sdramc_readl(reg) \
+        __raw_readl((void __iomem __force *)SDRAMC_BASE + SDRAMC_##reg)
+#define sdramc_writel(reg, value) \
+        __raw_writel(value, (void __iomem __force *)SDRAMC_BASE + SDRAMC_##reg)
diff --git a/arch/avr32/mm/init.c b/arch/avr32/mm/init.c
index 0e64ddc45e37..3f90a87527bb 100644
--- a/arch/avr32/mm/init.c
+++ b/arch/avr32/mm/init.c
@@ -11,6 +11,7 @@
 #include <linux/swap.h>
 #include <linux/init.h>
 #include <linux/mmzone.h>
+#include <linux/module.h>
 #include <linux/bootmem.h>
 #include <linux/pagemap.h>
 #include <linux/nodemask.h>
@@ -23,11 +24,14 @@
 #include <asm/setup.h>
 #include <asm/sections.h>
 
+#define __page_aligned  __attribute__((section(".data.page_aligned")))
+
 DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
 
-pgd_t swapper_pg_dir[PTRS_PER_PGD];
+pgd_t swapper_pg_dir[PTRS_PER_PGD] __page_aligned;
 
 struct page *empty_zero_page;
+EXPORT_SYMBOL(empty_zero_page);
 
 /*
  * Cache of MMU context last used.
@@ -106,19 +110,9 @@ void __init paging_init(void)
         zero_page = alloc_bootmem_low_pages_node(NODE_DATA(0),
                                                  PAGE_SIZE);
 
-        {
-                pgd_t *pg_dir;
-                int i;
-
-                pg_dir = swapper_pg_dir;
-                sysreg_write(PTBR, (unsigned long)pg_dir);
-
-                for (i = 0; i < PTRS_PER_PGD; i++)
-                        pgd_val(pg_dir[i]) = 0;
-
-                enable_mmu();
-                printk ("CPU: Paging enabled\n");
-        }
+        sysreg_write(PTBR, (unsigned long)swapper_pg_dir);
+        enable_mmu();
+        printk ("CPU: Paging enabled\n");
 
         for_each_online_node(nid) {
                 pg_data_t *pgdat = NODE_DATA(nid);
diff --git a/arch/avr32/mm/tlb.c b/arch/avr32/mm/tlb.c
index cd12edbea9f2..06677be98ffb 100644
--- a/arch/avr32/mm/tlb.c
+++ b/arch/avr32/mm/tlb.c
@@ -11,21 +11,21 @@
 
 #include <asm/mmu_context.h>
 
-#define _TLBEHI_I       0x100
+/* TODO: Get the correct number from the CONFIG1 system register */
+#define NR_TLB_ENTRIES 32
 
-void show_dtlb_entry(unsigned int index)
+static void show_dtlb_entry(unsigned int index)
 {
-        unsigned int tlbehi, tlbehi_save, tlbelo, mmucr, mmucr_save;
+        u32 tlbehi, tlbehi_save, tlbelo, mmucr, mmucr_save;
         unsigned long flags;
 
         local_irq_save(flags);
         mmucr_save = sysreg_read(MMUCR);
         tlbehi_save = sysreg_read(TLBEHI);
-        mmucr = mmucr_save & 0x13;
-        mmucr |= index << 14;
+        mmucr = SYSREG_BFINS(DRP, index, mmucr_save);
         sysreg_write(MMUCR, mmucr);
 
-        asm volatile("tlbr" : : : "memory");
+        __builtin_tlbr();
         cpu_sync_pipeline();
 
         tlbehi = sysreg_read(TLBEHI);
@@ -33,15 +33,17 @@ void show_dtlb_entry(unsigned int index)
 
         printk("%2u: %c %c %02x   %05x %05x %o  %o  %c %c %c %c\n",
                index,
-               (tlbehi & 0x200)?'1':'0',
-               (tlbelo & 0x100)?'1':'0',
-               (tlbehi & 0xff),
-               (tlbehi >> 12), (tlbelo >> 12),
-               (tlbelo >> 4) & 7, (tlbelo >> 2) & 3,
-               (tlbelo & 0x200)?'1':'0',
-               (tlbelo & 0x080)?'1':'0',
-               (tlbelo & 0x001)?'1':'0',
-               (tlbelo & 0x002)?'1':'0');
+               SYSREG_BFEXT(TLBEHI_V, tlbehi) ? '1' : '0',
+               SYSREG_BFEXT(G, tlbelo) ? '1' : '0',
+               SYSREG_BFEXT(ASID, tlbehi),
+               SYSREG_BFEXT(VPN, tlbehi) >> 2,
+               SYSREG_BFEXT(PFN, tlbelo) >> 2,
+               SYSREG_BFEXT(AP, tlbelo),
+               SYSREG_BFEXT(SZ, tlbelo),
+               SYSREG_BFEXT(TLBELO_C, tlbelo) ? 'C' : ' ',
+               SYSREG_BFEXT(B, tlbelo) ? 'B' : ' ',
+               SYSREG_BFEXT(W, tlbelo) ? 'W' : ' ',
+               SYSREG_BFEXT(TLBELO_D, tlbelo) ? 'D' : ' ');
 
         sysreg_write(MMUCR, mmucr_save);
         sysreg_write(TLBEHI, tlbehi_save);
@@ -54,29 +56,33 @@ void dump_dtlb(void)
         unsigned int i;
 
         printk("ID  V G ASID VPN   PFN   AP SZ C B W D\n");
-        for (i = 0; i < 32; i++)
+        for (i = 0; i < NR_TLB_ENTRIES; i++)
                 show_dtlb_entry(i);
 }
 
-static unsigned long last_mmucr;
-
-static inline void set_replacement_pointer(unsigned shift)
+static void update_dtlb(unsigned long address, pte_t pte)
 {
-        unsigned long mmucr, mmucr_save;
+        u32 tlbehi;
+        u32 mmucr;
 
-        mmucr = mmucr_save = sysreg_read(MMUCR);
+        /*
+         * We're not changing the ASID here, so no need to flush the
+         * pipeline.
+         */
+        tlbehi = sysreg_read(TLBEHI);
+        tlbehi = SYSREG_BF(ASID, SYSREG_BFEXT(ASID, tlbehi));
+        tlbehi |= address & MMU_VPN_MASK;
+        tlbehi |= SYSREG_BIT(TLBEHI_V);
+        sysreg_write(TLBEHI, tlbehi);
 
         /* Does this mapping already exist? */
-        __asm__ __volatile__(
-                "       tlbs\n"
-                "       mfsr %0, %1"
-                : "=r"(mmucr)
-                : "i"(SYSREG_MMUCR));
+        __builtin_tlbs();
+        mmucr = sysreg_read(MMUCR);
 
         if (mmucr & SYSREG_BIT(MMUCR_N)) {
                 /* Not found -- pick a not-recently-accessed entry */
-                unsigned long rp;
-                unsigned long tlbar = sysreg_read(TLBARLO);
+                unsigned int rp;
+                u32 tlbar = sysreg_read(TLBARLO);
 
                 rp = 32 - fls(tlbar);
                 if (rp == 32) {
@@ -84,30 +90,14 @@ static inline void set_replacement_pointer(unsigned shift)
                         sysreg_write(TLBARLO, -1L);
                 }
 
-                mmucr &= 0x13;
-                mmucr |= (rp << shift);
-
+                mmucr = SYSREG_BFINS(DRP, rp, mmucr);
                 sysreg_write(MMUCR, mmucr);
         }
 
-        last_mmucr = mmucr;
-}
-
-static void update_dtlb(unsigned long address, pte_t pte, unsigned long asid)
-{
-        unsigned long vpn;
-
-        vpn = (address & MMU_VPN_MASK) | _TLBEHI_VALID | asid;
-        sysreg_write(TLBEHI, vpn);
-        cpu_sync_pipeline();
-
-        set_replacement_pointer(14);
-
         sysreg_write(TLBELO, pte_val(pte) & _PAGE_FLAGS_HARDWARE_MASK);
 
         /* Let's go */
-        asm volatile("nop\n\ttlbw" : : : "memory");
-        cpu_sync_pipeline();
+        __builtin_tlbw();
 }
 
 void update_mmu_cache(struct vm_area_struct *vma,
@@ -120,39 +110,40 @@ void update_mmu_cache(struct vm_area_struct *vma,
                 return;
 
         local_irq_save(flags);
-        update_dtlb(address, pte, get_asid());
+        update_dtlb(address, pte);
         local_irq_restore(flags);
 }
 
-void __flush_tlb_page(unsigned long asid, unsigned long page)
+static void __flush_tlb_page(unsigned long asid, unsigned long page)
 {
-        unsigned long mmucr, tlbehi;
+        u32 mmucr, tlbehi;
 
-        page |= asid;
-        sysreg_write(TLBEHI, page);
-        cpu_sync_pipeline();
-        asm volatile("tlbs");
+        /*
+         * Caller is responsible for masking out non-PFN bits in page
+         * and changing the current ASID if necessary. This means that
+         * we don't need to flush the pipeline after writing TLBEHI.
+         */
+        tlbehi = page | asid;
+        sysreg_write(TLBEHI, tlbehi);
+
+        __builtin_tlbs();
         mmucr = sysreg_read(MMUCR);
 
         if (!(mmucr & SYSREG_BIT(MMUCR_N))) {
-                unsigned long tlbarlo;
-                unsigned long entry;
+                unsigned int entry;
+                u32 tlbarlo;
 
                 /* Clear the "valid" bit */
-                tlbehi = sysreg_read(TLBEHI);
-                tlbehi &= ~_TLBEHI_VALID;
                 sysreg_write(TLBEHI, tlbehi);
-                cpu_sync_pipeline();
 
                 /* mark the entry as "not accessed" */
-                entry = (mmucr >> 14) & 0x3f;
+                entry = SYSREG_BFEXT(DRP, mmucr);
                 tlbarlo = sysreg_read(TLBARLO);
-                tlbarlo |= (0x80000000 >> entry);
+                tlbarlo |= (0x80000000UL >> entry);
                 sysreg_write(TLBARLO, tlbarlo);
 
                 /* update the entry with valid bit clear */
-                asm volatile("tlbw");
-                cpu_sync_pipeline();
+                __builtin_tlbw();
         }
 }
 
@@ -190,17 +181,22 @@ void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
 
                 local_irq_save(flags);
                 size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
+
                 if (size > (MMU_DTLB_ENTRIES / 4)) { /* Too many entries to flush */
                         mm->context = NO_CONTEXT;
                         if (mm == current->mm)
                                 activate_context(mm);
                 } else {
-                        unsigned long asid = mm->context & MMU_CONTEXT_ASID_MASK;
-                        unsigned long saved_asid = MMU_NO_ASID;
+                        unsigned long asid;
+                        unsigned long saved_asid;
+
+                        asid = mm->context & MMU_CONTEXT_ASID_MASK;
+                        saved_asid = MMU_NO_ASID;
 
                         start &= PAGE_MASK;
                         end += (PAGE_SIZE - 1);
                         end &= PAGE_MASK;
+
                         if (mm != current->mm) {
                                 saved_asid = get_asid();
                                 set_asid(asid);
@@ -218,33 +214,34 @@ void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
 }
 
 /*
- * TODO: If this is only called for addresses > TASK_SIZE, we can probably
- * skip the ASID stuff and just use the Global bit...
+ * This function depends on the pages to be flushed having the G
+ * (global) bit set in their pte. This is true for all
+ * PAGE_KERNEL(_RO) pages.
  */
 void flush_tlb_kernel_range(unsigned long start, unsigned long end)
 {
         unsigned long flags;
         int size;
 
-        local_irq_save(flags);
         size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
         if (size > (MMU_DTLB_ENTRIES / 4)) { /* Too many entries to flush */
                 flush_tlb_all();
         } else {
-                unsigned long asid = init_mm.context & MMU_CONTEXT_ASID_MASK;
-                unsigned long saved_asid = get_asid();
+                unsigned long asid;
+
+                local_irq_save(flags);
+                asid = get_asid();
 
                 start &= PAGE_MASK;
                 end += (PAGE_SIZE - 1);
                 end &= PAGE_MASK;
-                set_asid(asid);
+
                 while (start < end) {
                         __flush_tlb_page(asid, start);
                         start += PAGE_SIZE;
                 }
-                set_asid(saved_asid);
+                local_irq_restore(flags);
         }
-        local_irq_restore(flags);
 }
 
 void flush_tlb_mm(struct mm_struct *mm)
@@ -280,7 +277,7 @@ static void *tlb_start(struct seq_file *tlb, loff_t *pos)
 {
         static unsigned long tlb_index;
 
-        if (*pos >= 32)
+        if (*pos >= NR_TLB_ENTRIES)
                 return NULL;
 
         tlb_index = 0;
@@ -291,7 +288,7 @@ static void *tlb_next(struct seq_file *tlb, void *v, loff_t *pos)
 {
         unsigned long *index = v;
 
-        if (*index >= 31)
+        if (*index >= NR_TLB_ENTRIES - 1)
                 return NULL;
 
         ++*pos;
@@ -313,16 +310,16 @@ static int tlb_show(struct seq_file *tlb, void *v)
         if (*index == 0)
                 seq_puts(tlb, "ID  V G ASID VPN   PFN   AP SZ C B W D\n");
 
-        BUG_ON(*index >= 32);
+        BUG_ON(*index >= NR_TLB_ENTRIES);
 
         local_irq_save(flags);
         mmucr_save = sysreg_read(MMUCR);
         tlbehi_save = sysreg_read(TLBEHI);
-        mmucr = mmucr_save & 0x13;
-        mmucr |= *index << 14;
+        mmucr = SYSREG_BFINS(DRP, *index, mmucr_save);
         sysreg_write(MMUCR, mmucr);
 
-        asm volatile("tlbr" : : : "memory");
+        /* TLBR might change the ASID */
+        __builtin_tlbr();
         cpu_sync_pipeline();
 
         tlbehi = sysreg_read(TLBEHI);
@@ -334,16 +331,18 @@ static int tlb_show(struct seq_file *tlb, void *v)
         local_irq_restore(flags);
 
         seq_printf(tlb, "%2lu: %c %c %02x   %05x %05x %o  %o  %c %c %c %c\n",
-               *index,
-               (tlbehi & 0x200)?'1':'0',
-               (tlbelo & 0x100)?'1':'0',
-               (tlbehi & 0xff),
-               (tlbehi >> 12), (tlbelo >> 12),
-               (tlbelo >> 4) & 7, (tlbelo >> 2) & 3,
-               (tlbelo & 0x200)?'1':'0',
-               (tlbelo & 0x080)?'1':'0',
-               (tlbelo & 0x001)?'1':'0',
-               (tlbelo & 0x002)?'1':'0');
+                   *index,
+                   SYSREG_BFEXT(TLBEHI_V, tlbehi) ? '1' : '0',
+                   SYSREG_BFEXT(G, tlbelo) ? '1' : '0',
+                   SYSREG_BFEXT(ASID, tlbehi),
+                   SYSREG_BFEXT(VPN, tlbehi) >> 2,
+                   SYSREG_BFEXT(PFN, tlbelo) >> 2,
+                   SYSREG_BFEXT(AP, tlbelo),
+                   SYSREG_BFEXT(SZ, tlbelo),
+                   SYSREG_BFEXT(TLBELO_C, tlbelo) ? '1' : '0',
+                   SYSREG_BFEXT(B, tlbelo) ? '1' : '0',
+                   SYSREG_BFEXT(W, tlbelo) ? '1' : '0',
+                   SYSREG_BFEXT(TLBELO_D, tlbelo) ? '1' : '0');
 
         return 0;
 }
diff --git a/arch/blackfin/mach-bf561/coreb.c b/arch/blackfin/mach-bf561/coreb.c
index 1b44e9e6dc3b..8598098c0840 100644
--- a/arch/blackfin/mach-bf561/coreb.c
+++ b/arch/blackfin/mach-bf561/coreb.c
@@ -194,6 +194,7 @@ static loff_t coreb_lseek(struct file *file, loff_t offset, int origin)
         return ret;
 }
 
+/* No BKL needed here */
 static int coreb_open(struct inode *inode, struct file *file)
 {
         spin_lock_irq(&coreb_lock);
diff --git a/arch/cris/arch-v10/drivers/eeprom.c b/arch/cris/arch-v10/drivers/eeprom.c
index f1cac9dc75b8..1f2ae909d3e6 100644
--- a/arch/cris/arch-v10/drivers/eeprom.c
+++ b/arch/cris/arch-v10/drivers/eeprom.c
@@ -28,6 +28,7 @@
 #include <linux/init.h>
 #include <linux/delay.h>
 #include <linux/interrupt.h>
+#include <linux/smp_lock.h>
 #include <linux/wait.h>
 #include <asm/uaccess.h>
 #include "i2c.h"
@@ -375,10 +376,9 @@ int __init eeprom_init(void)
 }
 
 /* Opens the device. */
-
 static int eeprom_open(struct inode * inode, struct file * file)
 {
-
+  cycle_kernel_lock();
   if(iminor(inode) != EEPROM_MINOR_NR)
      return -ENXIO;
   if(imajor(inode) != EEPROM_MAJOR_NR)
diff --git a/arch/cris/arch-v10/drivers/gpio.c b/arch/cris/arch-v10/drivers/gpio.c
index 68a998bd1069..86048e697eb5 100644
--- a/arch/cris/arch-v10/drivers/gpio.c
+++ b/arch/cris/arch-v10/drivers/gpio.c
@@ -16,6 +16,7 @@
 #include <linux/errno.h>
 #include <linux/kernel.h>
 #include <linux/fs.h>
+#include <linux/smp_lock.h>
 #include <linux/string.h>
 #include <linux/poll.h>
 #include <linux/init.h>
@@ -323,6 +324,7 @@ gpio_open(struct inode *inode, struct file *filp)
         if (!priv)
                 return -ENOMEM;
 
+        lock_kernel();
         priv->minor = p;
 
         /* initialize the io/alarm struct */
@@ -357,6 +359,7 @@ gpio_open(struct inode *inode, struct file *filp)
         alarmlist = priv;
         spin_unlock_irqrestore(&gpio_lock, flags);
 
+        unlock_kernel();
         return 0;
 }
 
diff --git a/arch/cris/arch-v10/drivers/i2c.c b/arch/cris/arch-v10/drivers/i2c.c
index d6d22067d0c8..2797e67ce4f4 100644
--- a/arch/cris/arch-v10/drivers/i2c.c
+++ b/arch/cris/arch-v10/drivers/i2c.c
@@ -15,6 +15,7 @@
 #include <linux/module.h>
 #include <linux/sched.h>
 #include <linux/slab.h>
+#include <linux/smp_lock.h>
 #include <linux/errno.h>
 #include <linux/kernel.h>
 #include <linux/fs.h>
@@ -566,6 +567,7 @@ i2c_readreg(unsigned char theSlave, unsigned char theReg)
 static int
 i2c_open(struct inode *inode, struct file *filp)
 {
+        cycle_kernel_lock();
         return 0;
 }
 
diff --git a/arch/cris/arch-v10/drivers/sync_serial.c b/arch/cris/arch-v10/drivers/sync_serial.c
index 069546e342c5..91fea623c7c9 100644
--- a/arch/cris/arch-v10/drivers/sync_serial.c
+++ b/arch/cris/arch-v10/drivers/sync_serial.c
@@ -21,6 +21,7 @@
 #include <linux/interrupt.h>
 #include <linux/poll.h>
 #include <linux/init.h>
+#include <linux/smp_lock.h>
 #include <linux/timer.h>
 #include <asm/irq.h>
 #include <asm/dma.h>
@@ -443,18 +444,21 @@ static int sync_serial_open(struct inode *inode, struct file *file)
         int dev = MINOR(inode->i_rdev);
         struct sync_port *port;
         int mode;
+        int err = -EBUSY;
 
+        lock_kernel();
         DEBUG(printk(KERN_DEBUG "Open sync serial port %d\n", dev));
 
         if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) {
                 DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev));
-                return -ENODEV;
+                err = -ENODEV;
+                goto out;
         }
         port = &ports[dev];
         /* Allow open this device twice (assuming one reader and one writer) */
         if (port->busy == 2) {
                 DEBUG(printk(KERN_DEBUG "Device is busy.. \n"));
-                return -EBUSY;
+                goto out;
         }
         if (port->init_irqs) {
                 if (port->use_dma) {
@@ -465,14 +469,14 @@ static int sync_serial_open(struct inode *inode, struct file *file)
                                                 &ports[0])) {
                                         printk(KERN_CRIT "Can't alloc "
                                                 "sync serial port 1 IRQ");
-                                        return -EBUSY;
+                                        goto out;
                                 } else if (request_irq(25, rx_interrupt, 0,
                                                 "synchronous serial 1 dma rx",
                                                 &ports[0])) {
                                         free_irq(24, &port[0]);
                                         printk(KERN_CRIT "Can't alloc "
                                                 "sync serial port 1 IRQ");
-                                        return -EBUSY;
+                                        goto out;
                                 } else if (cris_request_dma(8,
                                                 "synchronous serial 1 dma tr",
                                                 DMA_VERBOSE_ON_ERROR,
@@ -482,7 +486,7 @@ static int sync_serial_open(struct inode *inode, struct file *file)
                                         printk(KERN_CRIT "Can't alloc "
                                                 "sync serial port 1 "
                                                 "TX DMA channel");
-                                        return -EBUSY;
+                                        goto out;
                                 } else if (cris_request_dma(9,
                                                 "synchronous serial 1 dma rec",
                                                 DMA_VERBOSE_ON_ERROR,
@@ -493,7 +497,7 @@ static int sync_serial_open(struct inode *inode, struct file *file)
                                         printk(KERN_CRIT "Can't alloc "
                                                 "sync serial port 1 "
                                                 "RX DMA channel");
-                                        return -EBUSY;
+                                        goto out;
                                 }
 #endif
                                 RESET_DMA(8); WAIT_DMA(8);
@@ -520,14 +524,14 @@ static int sync_serial_open(struct inode *inode, struct file *file)
                                                 &ports[1])) {
                                         printk(KERN_CRIT "Can't alloc "
                                                 "sync serial port 3 IRQ");
-                                        return -EBUSY;
+                                        goto out;
                                 } else if (request_irq(21, rx_interrupt, 0,
                                                 "synchronous serial 3 dma rx",
                                                 &ports[1])) {
                                         free_irq(20, &ports[1]);
                                         printk(KERN_CRIT "Can't alloc "
                                                 "sync serial port 3 IRQ");
-                                        return -EBUSY;
+                                        goto out;
                                 } else if (cris_request_dma(4,
                                                 "synchronous serial 3 dma tr",
                                                 DMA_VERBOSE_ON_ERROR,
@@ -537,7 +541,7 @@ static int sync_serial_open(struct inode *inode, struct file *file)
                                         printk(KERN_CRIT "Can't alloc "
                                                 "sync serial port 3 "
                                                 "TX DMA channel");
-                                        return -EBUSY;
+                                        goto out;
                                 } else if (cris_request_dma(5,
                                                 "synchronous serial 3 dma rec",
                                                 DMA_VERBOSE_ON_ERROR,
@@ -548,7 +552,7 @@ static int sync_serial_open(struct inode *inode, struct file *file)
                                         printk(KERN_CRIT "Can't alloc "
                                                 "sync serial port 3 "
                                                 "RX DMA channel");
-                                        return -EBUSY;
+                                        goto out;
                                 }
 #endif
                                 RESET_DMA(4); WAIT_DMA(4);
@@ -581,7 +585,7 @@ static int sync_serial_open(struct inode *inode, struct file *file)
                                                 &ports[0])) {
                                         printk(KERN_CRIT "Can't alloc "
                                                 "sync serial manual irq");
-                                        return -EBUSY;
+                                        goto out;
                                 }
                         } else if (port == &ports[1]) {
                                 if (request_irq(8,
@@ -591,7 +595,7 @@ static int sync_serial_open(struct inode *inode, struct file *file)
                                                 &ports[1])) {
                                         printk(KERN_CRIT "Can't alloc "
                                                 "sync serial manual irq");
-                                        return -EBUSY;
+                                        goto out;
                                 }
                         }
                         port->init_irqs = 0;
@@ -620,7 +624,11 @@ static int sync_serial_open(struct inode *inode, struct file *file)
                         *R_IRQ_MASK1_SET = 1 << port->data_avail_bit;
                 DEBUG(printk(KERN_DEBUG "sser%d rec started\n", dev));
         }
-        return 0;
+        ret = 0;
+        
+out:
+        unlock_kernel();
+        return ret;
 }
 
 static int sync_serial_release(struct inode *inode, struct file *file)
diff --git a/arch/cris/arch-v32/drivers/cryptocop.c b/arch/cris/arch-v32/drivers/cryptocop.c
index 9fb58202be99..67c61ea86813 100644
--- a/arch/cris/arch-v32/drivers/cryptocop.c
+++ b/arch/cris/arch-v32/drivers/cryptocop.c
@@ -11,6 +11,7 @@
 #include <linux/string.h>
 #include <linux/fs.h>
 #include <linux/mm.h>
+#include <linux/smp_lock.h>
 #include <linux/spinlock.h>
 #include <linux/stddef.h>
 
@@ -2302,11 +2303,11 @@ static int cryptocop_job_setup(struct cryptocop_prio_job **pj, struct cryptocop_
         return 0;
 }
 
-
 static int cryptocop_open(struct inode *inode, struct file *filp)
 {
         int p = iminor(inode);
 
+        cycle_kernel_lock();
         if (p != CRYPTOCOP_MINOR) return -EINVAL;
 
         filp->private_data = NULL;
diff --git a/arch/cris/arch-v32/drivers/i2c.c b/arch/cris/arch-v32/drivers/i2c.c
index c2fb7a5c1396..179e7b804331 100644
--- a/arch/cris/arch-v32/drivers/i2c.c
+++ b/arch/cris/arch-v32/drivers/i2c.c
@@ -33,6 +33,7 @@
 #include <linux/fs.h>
 #include <linux/string.h>
 #include <linux/init.h>
+#include <linux/smp_lock.h>
 
 #include <asm/etraxi2c.h>
 
@@ -636,6 +637,7 @@ i2c_readreg(unsigned char theSlave, unsigned char theReg)
 static int
 i2c_open(struct inode *inode, struct file *filp)
 {
+        cycle_kernel_lock();
         return 0;
 }
 
diff --git a/arch/cris/arch-v32/drivers/mach-a3/gpio.c b/arch/cris/arch-v32/drivers/mach-a3/gpio.c
index de107dad9f4f..ef98608e5067 100644
--- a/arch/cris/arch-v32/drivers/mach-a3/gpio.c
+++ b/arch/cris/arch-v32/drivers/mach-a3/gpio.c
@@ -23,6 +23,7 @@
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/spinlock.h>
+#include <linux/smp_lock.h>
 
 #include <asm/etraxgpio.h>
 #include <hwregs/reg_map.h>
@@ -390,6 +391,8 @@ static int gpio_open(struct inode *inode, struct file *filp)
 
         if (!priv)
                 return -ENOMEM;
+
+        lock_kernel();
         memset(priv, 0, sizeof(*priv));
 
         priv->minor = p;
@@ -412,6 +415,7 @@ static int gpio_open(struct inode *inode, struct file *filp)
                 spin_unlock_irq(&gpio_lock);
         }
 
+        unlock_kernel();
         return 0;
 }
 
diff --git a/arch/cris/arch-v32/drivers/mach-fs/gpio.c b/arch/cris/arch-v32/drivers/mach-fs/gpio.c
index 7863fd4efc2b..fe1fde893887 100644
--- a/arch/cris/arch-v32/drivers/mach-fs/gpio.c
+++ b/arch/cris/arch-v32/drivers/mach-fs/gpio.c
@@ -22,6 +22,7 @@
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/spinlock.h>
+#include <linux/smp_lock.h>
 
 #include <asm/etraxgpio.h>
 #include <hwregs/reg_map.h>
@@ -426,9 +427,10 @@ gpio_open(struct inode *inode, struct file *filp)
                 return -EINVAL;
 
         priv = kmalloc(sizeof(struct gpio_private), GFP_KERNEL);
-
         if (!priv)
                 return -ENOMEM;
+
+        lock_kernel();
         memset(priv, 0, sizeof(*priv));
 
         priv->minor = p;
@@ -449,6 +451,7 @@ gpio_open(struct inode *inode, struct file *filp)
         alarmlist = priv;
         spin_unlock_irq(&alarm_lock);
 
+        unlock_kernel();
         return 0;
 }
 
diff --git a/arch/cris/arch-v32/drivers/sync_serial.c b/arch/cris/arch-v32/drivers/sync_serial.c
index 47c377df6fb3..d2a0fbf5341f 100644
--- a/arch/cris/arch-v32/drivers/sync_serial.c
+++ b/arch/cris/arch-v32/drivers/sync_serial.c
@@ -14,6 +14,7 @@
 #include <linux/major.h>
 #include <linux/sched.h>
 #include <linux/slab.h>
+#include <linux/smp_lock.h>
 #include <linux/interrupt.h>
 #include <linux/poll.h>
 #include <linux/init.h>
@@ -429,23 +430,26 @@ static inline int sync_data_avail_to_end(struct sync_port *port)
 static int sync_serial_open(struct inode *inode, struct file *file)
 {
         int dev = iminor(inode);
+        int ret = -EBUSY;
         sync_port *port;
         reg_dma_rw_cfg cfg = {.en = regk_dma_yes};
         reg_dma_rw_intr_mask intr_mask = {.data = regk_dma_yes};
 
+        lock_kernel();
         DEBUG(printk(KERN_DEBUG "Open sync serial port %d\n", dev));
 
         if (dev < 0 || dev >= NBR_PORTS || !ports[dev].enabled)
         {
                 DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev));
-                return -ENODEV;
+                ret = -ENODEV;
+                goto out;
         }
         port = &ports[dev];
         /* Allow open this device twice (assuming one reader and one writer) */
         if (port->busy == 2)
         {
                 DEBUG(printk(KERN_DEBUG "Device is busy.. \n"));
-                return -EBUSY;
+                goto out;
         }
 
 
@@ -459,7 +463,7 @@ static int sync_serial_open(struct inode *inode, struct file *file)
                                                 "synchronous serial 0 dma tr",
                                                 &ports[0])) {
                                         printk(KERN_CRIT "Can't allocate sync serial port 0 IRQ");
-                                        return -EBUSY;
+                                        goto out;
                                 } else if (request_irq(DMA_IN_INTR_VECT,
                                                 rx_interrupt,
                                                 0,
@@ -467,7 +471,7 @@ static int sync_serial_open(struct inode *inode, struct file *file)
                                                 &ports[0])) {
                                         free_irq(DMA_OUT_INTR_VECT, &port[0]);
                                         printk(KERN_CRIT "Can't allocate sync serial port 0 IRQ");
-                                        return -EBUSY;
+                                        goto out;
                                 } else if (crisv32_request_dma(OUT_DMA_NBR,
                                                 "synchronous serial 0 dma tr",
                                                 DMA_VERBOSE_ON_ERROR,
@@ -476,7 +480,7 @@ static int sync_serial_open(struct inode *inode, struct file *file)
                                         free_irq(DMA_OUT_INTR_VECT, &port[0]);
                                         free_irq(DMA_IN_INTR_VECT, &port[0]);
                                         printk(KERN_CRIT "Can't allocate sync serial port 0 TX DMA channel");
-                                        return -EBUSY;
+                                        goto out;
                                 } else if (crisv32_request_dma(IN_DMA_NBR,
                                                 "synchronous serial 0 dma rec",
                                                 DMA_VERBOSE_ON_ERROR,
@@ -486,7 +490,7 @@ static int sync_serial_open(struct inode *inode, struct file *file)
                                         free_irq(DMA_OUT_INTR_VECT, &port[0]);
                                         free_irq(DMA_IN_INTR_VECT, &port[0]);
                                         printk(KERN_CRIT "Can't allocate sync serial port 1 RX DMA channel");
-                                        return -EBUSY;
+                                        goto out;
                                 }
 #endif
                         }
@@ -499,7 +503,7 @@ static int sync_serial_open(struct inode *inode, struct file *file)
                                                 "synchronous serial 1 dma tr",
                                                 &ports[1])) {
                                         printk(KERN_CRIT "Can't allocate sync serial port 1 IRQ");
-                                        return -EBUSY;
+                                        goto out;
                                 } else if (request_irq(DMA7_INTR_VECT,
                                                        rx_interrupt,
                                                        0,
@@ -507,7 +511,7 @@ static int sync_serial_open(struct inode *inode, struct file *file)
                                                        &ports[1])) {
                                         free_irq(DMA6_INTR_VECT, &ports[1]);
                                         printk(KERN_CRIT "Can't allocate sync serial port 3 IRQ");
-                                        return -EBUSY;
+                                        goto out;
                                 } else if (crisv32_request_dma(
                                                 SYNC_SER1_TX_DMA_NBR,
                                                 "synchronous serial 1 dma tr",
@@ -517,7 +521,7 @@ static int sync_serial_open(struct inode *inode, struct file *file)
                                         free_irq(DMA6_INTR_VECT, &ports[1]);
                                         free_irq(DMA7_INTR_VECT, &ports[1]);
                                         printk(KERN_CRIT "Can't allocate sync serial port 3 TX DMA channel");
-                                        return -EBUSY;
+                                        goto out;
                                 } else if (crisv32_request_dma(
                                                 SYNC_SER1_RX_DMA_NBR,
                                                 "synchronous serial 3 dma rec",
@@ -528,7 +532,7 @@ static int sync_serial_open(struct inode *inode, struct file *file)
                                         free_irq(DMA6_INTR_VECT, &ports[1]);
                                         free_irq(DMA7_INTR_VECT, &ports[1]);
                                         printk(KERN_CRIT "Can't allocate sync serial port 3 RX DMA channel");
-                                        return -EBUSY;
+                                        goto out;
                                 }
 #endif
                         }
@@ -554,7 +558,7 @@ static int sync_serial_open(struct inode *inode, struct file *file)
                                                 "synchronous serial manual irq",
                                                 &ports[0])) {
                                         printk("Can't allocate sync serial manual irq");
-                                        return -EBUSY;
+                                        goto out;
                                 }
                         }
 #ifdef CONFIG_ETRAXFS
@@ -565,7 +569,7 @@ static int sync_serial_open(struct inode *inode, struct file *file)
                                                 "synchronous serial manual irq",
                                                 &ports[1])) {
                                         printk(KERN_CRIT "Can't allocate sync serial manual irq");
-                                        return -EBUSY;
+                                        goto out;
                                 }
                         }
 #endif
@@ -578,7 +582,10 @@ static int sync_serial_open(struct inode *inode, struct file *file)
         } /* port->init_irqs */
 
         port->busy++;
-        return 0;
+        ret = 0;
+out:
+        unlock_kernel();
+        return ret;
 }
 
 static int sync_serial_release(struct inode *inode, struct file *file)
diff --git a/arch/m68k/bvme6000/rtc.c b/arch/m68k/bvme6000/rtc.c
index a812d03879f8..e8ac3f7d72df 100644
--- a/arch/m68k/bvme6000/rtc.c
+++ b/arch/m68k/bvme6000/rtc.c
@@ -10,6 +10,7 @@
 #include <linux/errno.h>
 #include <linux/miscdevice.h>
 #include <linux/slab.h>
+#include <linux/smp_lock.h>
 #include <linux/ioport.h>
 #include <linux/capability.h>
 #include <linux/fcntl.h>
@@ -140,10 +141,14 @@ static int rtc_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
 
 static int rtc_open(struct inode *inode, struct file *file)
 {
-        if(rtc_status)
+        lock_kernel();
+        if(rtc_status) {
+                unlock_kernel();
                 return -EBUSY;
+        }
 
         rtc_status = 1;
+        unlock_kernel();
         return 0;
 }
 
diff --git a/arch/m68k/mvme16x/rtc.c b/arch/m68k/mvme16x/rtc.c
index e341387787ab..432a9f13b2ed 100644
--- a/arch/m68k/mvme16x/rtc.c
+++ b/arch/m68k/mvme16x/rtc.c
@@ -10,6 +10,7 @@
 #include <linux/errno.h>
 #include <linux/miscdevice.h>
 #include <linux/slab.h>
+#include <linux/smp_lock.h>
 #include <linux/ioport.h>
 #include <linux/capability.h>
 #include <linux/fcntl.h>
@@ -127,11 +128,14 @@ static int rtc_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
 
 static int rtc_open(struct inode *inode, struct file *file)
 {
+        lock_kernel();
         if( !atomic_dec_and_test(&rtc_ready) )
         {
                 atomic_inc( &rtc_ready );
+                unlock_kernel();
                 return -EBUSY;
         }
+        unlock_kernel();
 
         return 0;
 }
diff --git a/arch/mips/basler/excite/excite_iodev.c b/arch/mips/basler/excite/excite_iodev.c
index 476d20e08d0e..a1e3526b4a94 100644
--- a/arch/mips/basler/excite/excite_iodev.c
+++ b/arch/mips/basler/excite/excite_iodev.c
@@ -26,6 +26,7 @@
 #include <linux/interrupt.h>
 #include <linux/platform_device.h>
 #include <linux/miscdevice.h>
+#include <linux/smp_lock.h>
 
 #include "excite_iodev.h"
 
@@ -110,8 +111,14 @@ static int __exit iodev_remove(struct device *dev)
 
 static int iodev_open(struct inode *i, struct file *f)
 {
-        return request_irq(iodev_irq, iodev_irqhdl, IRQF_DISABLED,
+        int ret;
+
+        lock_kernel();
+        ret = request_irq(iodev_irq, iodev_irqhdl, IRQF_DISABLED,
                            iodev_name, &miscdev);
+        unlock_kernel();
+
+        return ret;
 }
 
 static int iodev_release(struct inode *i, struct file *f)
diff --git a/arch/mips/kernel/rtlx.c b/arch/mips/kernel/rtlx.c
index b88f1c18ff4d..b55641961232 100644
--- a/arch/mips/kernel/rtlx.c
+++ b/arch/mips/kernel/rtlx.c
@@ -28,6 +28,7 @@
 #include <linux/vmalloc.h>
 #include <linux/elf.h>
 #include <linux/seq_file.h>
+#include <linux/smp_lock.h>
 #include <linux/syscalls.h>
 #include <linux/moduleloader.h>
 #include <linux/interrupt.h>
@@ -392,8 +393,12 @@ out:
 static int file_open(struct inode *inode, struct file *filp)
 {
         int minor = iminor(inode);
+        int err;
 
-        return rtlx_open(minor, (filp->f_flags & O_NONBLOCK) ? 0 : 1);
+        lock_kernel();
+        err = rtlx_open(minor, (filp->f_flags & O_NONBLOCK) ? 0 : 1);
+        unlock_kernel();
+        return err;
 }
 
 static int file_release(struct inode *inode, struct file *filp)
diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c
index 2794501ff302..972b2d2b8401 100644
--- a/arch/mips/kernel/vpe.c
+++ b/arch/mips/kernel/vpe.c
@@ -38,6 +38,7 @@
 #include <linux/vmalloc.h>
 #include <linux/elf.h>
 #include <linux/seq_file.h>
+#include <linux/smp_lock.h>
 #include <linux/syscalls.h>
 #include <linux/moduleloader.h>
 #include <linux/interrupt.h>
@@ -1050,17 +1051,20 @@ static int vpe_open(struct inode *inode, struct file *filp)
         enum vpe_state state;
         struct vpe_notifications *not;
         struct vpe *v;
-        int ret;
+        int ret, err = 0;
 
+        lock_kernel();
         if (minor != iminor(inode)) {
                 /* assume only 1 device at the moment. */
                 printk(KERN_WARNING "VPE loader: only vpe1 is supported\n");
-                return -ENODEV;
+                err = -ENODEV;
+                goto out;
         }
 
         if ((v = get_vpe(tclimit)) == NULL) {
                 printk(KERN_WARNING "VPE loader: unable to get vpe\n");
-                return -ENODEV;
+                err = -ENODEV;
+                goto out;
         }
 
         state = xchg(&v->state, VPE_STATE_INUSE);
@@ -1100,6 +1104,8 @@ static int vpe_open(struct inode *inode, struct file *filp)
         v->shared_ptr = NULL;
         v->__start = 0;
 
+out:
+        unlock_kernel();
         return 0;
 }
 
diff --git a/arch/mips/sibyte/common/sb_tbprof.c b/arch/mips/sibyte/common/sb_tbprof.c
index 63b444eaf01e..28b012ab8dcb 100644
--- a/arch/mips/sibyte/common/sb_tbprof.c
+++ b/arch/mips/sibyte/common/sb_tbprof.c
@@ -28,6 +28,7 @@
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/slab.h>
+#include <linux/smp_lock.h>
 #include <linux/vmalloc.h>
 #include <linux/fs.h>
 #include <linux/errno.h>
@@ -402,18 +403,26 @@ static int sbprof_zbprof_stop(void)
 static int sbprof_tb_open(struct inode *inode, struct file *filp)
 {
         int minor;
+        int err = 0;
 
+        lock_kernel();
         minor = iminor(inode);
-        if (minor != 0)
-                return -ENODEV;
+        if (minor != 0) {
+                err = -ENODEV;
+                goto out;
+        }
 
-        if (xchg(&sbp.open, SB_OPENING) != SB_CLOSED)
-                return -EBUSY;
+        if (xchg(&sbp.open, SB_OPENING) != SB_CLOSED) {
+                err = -EBUSY;
+                goto out;
+        }
 
         memset(&sbp, 0, sizeof(struct sbprof_tb));
         sbp.sbprof_tbbuf = vmalloc(MAX_TBSAMPLE_BYTES);
-        if (!sbp.sbprof_tbbuf)
-                return -ENOMEM;
+        if (!sbp.sbprof_tbbuf) {
+                err = -ENOMEM;
+                goto out;
+        }
         memset(sbp.sbprof_tbbuf, 0, MAX_TBSAMPLE_BYTES);
         init_waitqueue_head(&sbp.tb_sync);
         init_waitqueue_head(&sbp.tb_read);
@@ -421,7 +430,9 @@ static int sbprof_tb_open(struct inode *inode, struct file *filp)
 
         sbp.open = SB_OPEN;
 
-        return 0;
+  out:
+        unlock_kernel();
+        return err;
 }
 
 static int sbprof_tb_release(struct inode *inode, struct file *filp)
diff --git a/arch/parisc/kernel/perf.c b/arch/parisc/kernel/perf.c
index 89d6d5ad44b5..f696f57faa15 100644
--- a/arch/parisc/kernel/perf.c
+++ b/arch/parisc/kernel/perf.c
@@ -46,6 +46,7 @@
 #include <linux/init.h>
 #include <linux/proc_fs.h>
 #include <linux/miscdevice.h>
+#include <linux/smp_lock.h>
 #include <linux/spinlock.h>
 
 #include <asm/uaccess.h>
@@ -260,13 +261,16 @@ printk("Preparing to start counters\n");
  */
 static int perf_open(struct inode *inode, struct file *file)
 {
+        lock_kernel();
         spin_lock(&perf_lock);
         if (perf_enabled) {
                 spin_unlock(&perf_lock);
+                unlock_kernel();
                 return -EBUSY;
         }
         perf_enabled = 1;
         spin_unlock(&perf_lock);
+        unlock_kernel();
 
         return 0;
 }
diff --git a/arch/parisc/kernel/vmlinux.lds.S b/arch/parisc/kernel/vmlinux.lds.S
index 2e516b871752..1a3b6ccd3620 100644
--- a/arch/parisc/kernel/vmlinux.lds.S
+++ b/arch/parisc/kernel/vmlinux.lds.S
@@ -67,7 +67,6 @@ SECTIONS
         _etext = .;
 
         RODATA
-        BUG_TABLE
 
         /* writeable */
         /* Make sure this is page aligned so
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 06b72771ae22..1530a41fc56d 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -108,12 +108,14 @@ config ARCH_NO_VIRT_TO_BUS
 config PPC
         bool
         default y
+        select HAVE_DYNAMIC_FTRACE
+        select HAVE_FTRACE
         select HAVE_IDE
-        select HAVE_OPROFILE
         select HAVE_KPROBES
         select HAVE_KRETPROBES
         select HAVE_LMB
         select HAVE_DMA_ATTRS if PPC64
+        select HAVE_OPROFILE
 
 config EARLY_PRINTK
         bool
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index 9ebeb2406b5b..bf0b1fd0ec34 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -12,6 +12,18 @@ CFLAGS_prom_init.o      += -fPIC
 CFLAGS_btext.o          += -fPIC
 endif
 
+ifdef CONFIG_FTRACE
+# Do not trace early boot code
+CFLAGS_REMOVE_cputable.o = -pg
+CFLAGS_REMOVE_prom_init.o = -pg
+
+ifdef CONFIG_DYNAMIC_FTRACE
+# dynamic ftrace setup.
+CFLAGS_REMOVE_ftrace.o = -pg
+endif
+
+endif
+
 obj-y                           := cputable.o ptrace.o syscalls.o \
                                    irq.o align.o signal_32.o pmc.o vdso.o \
                                    init_task.o process.o systbl.o idle.o \
@@ -79,6 +91,8 @@ obj-$(CONFIG_KEXEC)		+= machine_kexec.o crash.o \
 obj-$(CONFIG_AUDIT)             += audit.o
 obj64-$(CONFIG_AUDIT)           += compat_audit.o
 
+obj-$(CONFIG_DYNAMIC_FTRACE)    += ftrace.o
+
 obj-$(CONFIG_8XX_MINIMAL_FPEMU) += softemu8xx.o
 
 ifneq ($(CONFIG_PPC_INDIRECT_IO),y)
diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S
index ab2d62f70b14..da52269aec1e 100644
--- a/arch/powerpc/kernel/entry_32.S
+++ b/arch/powerpc/kernel/entry_32.S
@@ -30,6 +30,7 @@
 #include <asm/ppc_asm.h>
 #include <asm/asm-offsets.h>
 #include <asm/unistd.h>
+#include <asm/ftrace.h>
 
 #undef SHOW_SYSCALLS
 #undef SHOW_SYSCALLS_TASK
@@ -1151,3 +1152,129 @@ machine_check_in_rtas:
         /* XXX load up BATs and panic */
 
 #endif /* CONFIG_PPC_RTAS */
+
+#ifdef CONFIG_FTRACE
+#ifdef CONFIG_DYNAMIC_FTRACE
+_GLOBAL(mcount)
+_GLOBAL(_mcount)
+        stwu    r1,-48(r1)
+        stw     r3, 12(r1)
+        stw     r4, 16(r1)
+        stw     r5, 20(r1)
+        stw     r6, 24(r1)
+        mflr    r3
+        stw     r7, 28(r1)
+        mfcr    r5
+        stw     r8, 32(r1)
+        stw     r9, 36(r1)
+        stw     r10,40(r1)
+        stw     r3, 44(r1)
+        stw     r5, 8(r1)
+        subi    r3, r3, MCOUNT_INSN_SIZE
+        .globl mcount_call
+mcount_call:
+        bl      ftrace_stub
+        nop
+        lwz     r6, 8(r1)
+        lwz     r0, 44(r1)
+        lwz     r3, 12(r1)
+        mtctr   r0
+        lwz     r4, 16(r1)
+        mtcr    r6
+        lwz     r5, 20(r1)
+        lwz     r6, 24(r1)
+        lwz     r0, 52(r1)
+        lwz     r7, 28(r1)
+        lwz     r8, 32(r1)
+        mtlr    r0
+        lwz     r9, 36(r1)
+        lwz     r10,40(r1)
+        addi    r1, r1, 48
+        bctr
+
+_GLOBAL(ftrace_caller)
+        /* Based off of objdump optput from glibc */
+        stwu    r1,-48(r1)
+        stw     r3, 12(r1)
+        stw     r4, 16(r1)
+        stw     r5, 20(r1)
+        stw     r6, 24(r1)
+        mflr    r3
+        lwz     r4, 52(r1)
+        mfcr    r5
+        stw     r7, 28(r1)
+        stw     r8, 32(r1)
+        stw     r9, 36(r1)
+        stw     r10,40(r1)
+        stw     r3, 44(r1)
+        stw     r5, 8(r1)
+        subi    r3, r3, MCOUNT_INSN_SIZE
+.globl ftrace_call
+ftrace_call:
+        bl      ftrace_stub
+        nop
+        lwz     r6, 8(r1)
+        lwz     r0, 44(r1)
+        lwz     r3, 12(r1)
+        mtctr   r0
+        lwz     r4, 16(r1)
+        mtcr    r6
+        lwz     r5, 20(r1)
+        lwz     r6, 24(r1)
+        lwz     r0, 52(r1)
+        lwz     r7, 28(r1)
+        lwz     r8, 32(r1)
+        mtlr    r0
+        lwz     r9, 36(r1)
+        lwz     r10,40(r1)
+        addi    r1, r1, 48
+        bctr
+#else
+_GLOBAL(mcount)
+_GLOBAL(_mcount)
+        stwu    r1,-48(r1)
+        stw     r3, 12(r1)
+        stw     r4, 16(r1)
+        stw     r5, 20(r1)
+        stw     r6, 24(r1)
+        mflr    r3
+        lwz     r4, 52(r1)
+        mfcr    r5
+        stw     r7, 28(r1)
+        stw     r8, 32(r1)
+        stw     r9, 36(r1)
+        stw     r10,40(r1)
+        stw     r3, 44(r1)
+        stw     r5, 8(r1)
+
+        subi    r3, r3, MCOUNT_INSN_SIZE
+        LOAD_REG_ADDR(r5, ftrace_trace_function)
+        lwz     r5,0(r5)
+
+        mtctr   r5
+        bctrl
+
+        nop
+
+        lwz     r6, 8(r1)
+        lwz     r0, 44(r1)
+        lwz     r3, 12(r1)
+        mtctr   r0
+        lwz     r4, 16(r1)
+        mtcr    r6
+        lwz     r5, 20(r1)
+        lwz     r6, 24(r1)
+        lwz     r0, 52(r1)
+        lwz     r7, 28(r1)
+        lwz     r8, 32(r1)
+        mtlr    r0
+        lwz     r9, 36(r1)
+        lwz     r10,40(r1)
+        addi    r1, r1, 48
+        bctr
+#endif
+
+_GLOBAL(ftrace_stub)
+        blr
+
+#endif /* CONFIG_MCOUNT */
diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
index 12eb95a80ce9..d7369243ae44 100644
--- a/arch/powerpc/kernel/entry_64.S
+++ b/arch/powerpc/kernel/entry_64.S
@@ -31,6 +31,7 @@
 #include <asm/bug.h>
 #include <asm/ptrace.h>
 #include <asm/irqflags.h>
+#include <asm/ftrace.h>
 
 /*
  * System calls.
@@ -875,3 +876,67 @@ _GLOBAL(enter_prom)
         ld      r0,16(r1)
         mtlr    r0
         blr
+
+#ifdef CONFIG_FTRACE
+#ifdef CONFIG_DYNAMIC_FTRACE
+_GLOBAL(mcount)
+_GLOBAL(_mcount)
+        /* Taken from output of objdump from lib64/glibc */
+        mflr    r3
+        stdu    r1, -112(r1)
+        std     r3, 128(r1)
+        subi    r3, r3, MCOUNT_INSN_SIZE
+        .globl mcount_call
+mcount_call:
+        bl      ftrace_stub
+        nop
+        ld      r0, 128(r1)
+        mtlr    r0
+        addi    r1, r1, 112
+        blr
+
+_GLOBAL(ftrace_caller)
+        /* Taken from output of objdump from lib64/glibc */
+        mflr    r3
+        ld      r11, 0(r1)
+        stdu    r1, -112(r1)
+        std     r3, 128(r1)
+        ld      r4, 16(r11)
+        subi    r3, r3, MCOUNT_INSN_SIZE
+.globl ftrace_call
+ftrace_call:
+        bl      ftrace_stub
+        nop
+        ld      r0, 128(r1)
+        mtlr    r0
+        addi    r1, r1, 112
+_GLOBAL(ftrace_stub)
+        blr
+#else
+_GLOBAL(mcount)
+        blr
+
+_GLOBAL(_mcount)
+        /* Taken from output of objdump from lib64/glibc */
+        mflr    r3
+        ld      r11, 0(r1)
+        stdu    r1, -112(r1)
+        std     r3, 128(r1)
+        ld      r4, 16(r11)
+
+        subi    r3, r3, MCOUNT_INSN_SIZE
+        LOAD_REG_ADDR(r5,ftrace_trace_function)
+        ld      r5,0(r5)
+        ld      r5,0(r5)
+        mtctr   r5
+        bctrl
+
+        nop
+        ld      r0, 128(r1)
+        mtlr    r0
+        addi    r1, r1, 112
+_GLOBAL(ftrace_stub)
+        blr
+
+#endif
+#endif
diff --git a/arch/powerpc/kernel/ftrace.c b/arch/powerpc/kernel/ftrace.c
new file mode 100644
index 000000000000..3855ceb937b0
--- /dev/null
+++ b/arch/powerpc/kernel/ftrace.c
@@ -0,0 +1,154 @@
+/*
+ * Code for replacing ftrace calls with jumps.
+ *
+ * Copyright (C) 2007-2008 Steven Rostedt <srostedt@redhat.com>
+ *
+ * Thanks goes out to P.A. Semi, Inc for supplying me with a PPC64 box.
+ *
+ */
+
+#include <linux/spinlock.h>
+#include <linux/hardirq.h>
+#include <linux/ftrace.h>
+#include <linux/percpu.h>
+#include <linux/init.h>
+#include <linux/list.h>
+
+#include <asm/cacheflush.h>
+#include <asm/ftrace.h>
+
+
+static unsigned int ftrace_nop = 0x60000000;
+
+#ifdef CONFIG_PPC32
+# define GET_ADDR(addr) addr
+#else
+/* PowerPC64's functions are data that points to the functions */
+# define GET_ADDR(addr) *(unsigned long *)addr
+#endif
+
+
+static unsigned int notrace ftrace_calc_offset(long ip, long addr)
+{
+        return (int)(addr - ip);
+}
+
+notrace unsigned char *ftrace_nop_replace(void)
+{
+        return (char *)&ftrace_nop;
+}
+
+notrace unsigned char *ftrace_call_replace(unsigned long ip, unsigned long addr)
+{
+        static unsigned int op;
+
+        /*
+         * It would be nice to just use create_function_call, but that will
+         * update the code itself. Here we need to just return the
+         * instruction that is going to be modified, without modifying the
+         * code.
+         */
+        addr = GET_ADDR(addr);
+
+        /* Set to "bl addr" */
+        op = 0x48000001 | (ftrace_calc_offset(ip, addr) & 0x03fffffc);
+
+        /*
+         * No locking needed, this must be called via kstop_machine
+         * which in essence is like running on a uniprocessor machine.
+         */
+        return (unsigned char *)&op;
+}
+
+#ifdef CONFIG_PPC64
+# define _ASM_ALIGN     " .align 3 "
+# define _ASM_PTR       " .llong "
+#else
+# define _ASM_ALIGN     " .align 2 "
+# define _ASM_PTR       " .long "
+#endif
+
+notrace int
+ftrace_modify_code(unsigned long ip, unsigned char *old_code,
+                   unsigned char *new_code)
+{
+        unsigned replaced;
+        unsigned old = *(unsigned *)old_code;
+        unsigned new = *(unsigned *)new_code;
+        int faulted = 0;
+
+        /*
+         * Note: Due to modules and __init, code can
+         *  disappear and change, we need to protect against faulting
+         *  as well as code changing.
+         *
+         * No real locking needed, this code is run through
+         * kstop_machine.
+         */
+        asm volatile (
+                "1: lwz         %1, 0(%2)\n"
+                "   cmpw        %1, %5\n"
+                "   bne         2f\n"
+                "   stwu        %3, 0(%2)\n"
+                "2:\n"
+                ".section .fixup, \"ax\"\n"
+                "3:     li %0, 1\n"
+                "       b 2b\n"
+                ".previous\n"
+                ".section __ex_table,\"a\"\n"
+                _ASM_ALIGN "\n"
+                _ASM_PTR "1b, 3b\n"
+                ".previous"
+                : "=r"(faulted), "=r"(replaced)
+                : "r"(ip), "r"(new),
+                  "0"(faulted), "r"(old)
+                : "memory");
+
+        if (replaced != old && replaced != new)
+                faulted = 2;
+
+        if (!faulted)
+                flush_icache_range(ip, ip + 8);
+
+        return faulted;
+}
+
+notrace int ftrace_update_ftrace_func(ftrace_func_t func)
+{
+        unsigned long ip = (unsigned long)(&ftrace_call);
+        unsigned char old[MCOUNT_INSN_SIZE], *new;
+        int ret;
+
+        memcpy(old, &ftrace_call, MCOUNT_INSN_SIZE);
+        new = ftrace_call_replace(ip, (unsigned long)func);
+        ret = ftrace_modify_code(ip, old, new);
+
+        return ret;
+}
+
+notrace int ftrace_mcount_set(unsigned long *data)
+{
+        unsigned long ip = (long)(&mcount_call);
+        unsigned long *addr = data;
+        unsigned char old[MCOUNT_INSN_SIZE], *new;
+
+        /*
+         * Replace the mcount stub with a pointer to the
+         * ip recorder function.
+         */
+        memcpy(old, &mcount_call, MCOUNT_INSN_SIZE);
+        new = ftrace_call_replace(ip, *addr);
+        *addr = ftrace_modify_code(ip, old, new);
+
+        return 0;
+}
+
+int __init ftrace_dyn_arch_init(void *data)
+{
+        /* This is running in kstop_machine */
+
+        ftrace_mcount_set(data);
+
+        return 0;
+}
+
diff --git a/arch/powerpc/kernel/io.c b/arch/powerpc/kernel/io.c
index e31aca9208eb..1882bf419fa6 100644
--- a/arch/powerpc/kernel/io.c
+++ b/arch/powerpc/kernel/io.c
@@ -120,7 +120,8 @@ EXPORT_SYMBOL(_outsl_ns);
 
 #define IO_CHECK_ALIGN(v,a) ((((unsigned long)(v)) & ((a) - 1)) == 0)
 
-void _memset_io(volatile void __iomem *addr, int c, unsigned long n)
+notrace void
+_memset_io(volatile void __iomem *addr, int c, unsigned long n)
 {
         void *p = (void __force *)addr;
         u32 lc = c;
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c
index d6df018bb584..6ac8612da3c3 100644
--- a/arch/powerpc/kernel/irq.c
+++ b/arch/powerpc/kernel/irq.c
@@ -98,7 +98,7 @@ EXPORT_SYMBOL(irq_desc);
 
 int distribute_irqs = 1;
 
-static inline unsigned long get_hard_enabled(void)
+static inline notrace unsigned long get_hard_enabled(void)
 {
         unsigned long enabled;
 
@@ -108,13 +108,13 @@ static inline unsigned long get_hard_enabled(void)
         return enabled;
 }
 
-static inline void set_soft_enabled(unsigned long enable)
+static inline notrace void set_soft_enabled(unsigned long enable)
 {
         __asm__ __volatile__("stb %0,%1(13)"
         : : "r" (enable), "i" (offsetof(struct paca_struct, soft_enabled)));
 }
 
-void raw_local_irq_restore(unsigned long en)
+notrace void raw_local_irq_restore(unsigned long en)
 {
         /*
          * get_paca()->soft_enabled = en;
diff --git a/arch/powerpc/kernel/ppc_ksyms.c b/arch/powerpc/kernel/ppc_ksyms.c
index 958ecb9ae7dc..e1ea4fe5cfbd 100644
--- a/arch/powerpc/kernel/ppc_ksyms.c
+++ b/arch/powerpc/kernel/ppc_ksyms.c
@@ -42,6 +42,7 @@
 #include <asm/div64.h>
 #include <asm/signal.h>
 #include <asm/dcr.h>
+#include <asm/ftrace.h>
 
 #ifdef CONFIG_PPC32
 extern void transfer_to_handler(void);
@@ -67,6 +68,10 @@ EXPORT_SYMBOL(single_step_exception);
 EXPORT_SYMBOL(sys_sigreturn);
 #endif
 
+#ifdef CONFIG_FTRACE
+EXPORT_SYMBOL(_mcount);
+#endif
+
 EXPORT_SYMBOL(strcpy);
 EXPORT_SYMBOL(strncpy);
 EXPORT_SYMBOL(strcat);
diff --git a/arch/powerpc/kernel/setup_32.c b/arch/powerpc/kernel/setup_32.c
index 0109e7f0ccf9..4efebe88e64a 100644
--- a/arch/powerpc/kernel/setup_32.c
+++ b/arch/powerpc/kernel/setup_32.c
@@ -81,7 +81,7 @@ int ucache_bsize;
  * from the address that it was linked at, so we must use RELOC/PTRRELOC
  * to access static data (including strings).  -- paulus
  */
-unsigned long __init early_init(unsigned long dt_ptr)
+notrace unsigned long __init early_init(unsigned long dt_ptr)
 {
         unsigned long offset = reloc_offset();
         struct cpu_spec *spec;
@@ -115,7 +115,7 @@ unsigned long __init early_init(unsigned long dt_ptr)
  * This is called very early on the boot process, after a minimal
  * MMU environment has been set up but before MMU_init is called.
  */
-void __init machine_init(unsigned long dt_ptr, unsigned long phys)
+notrace void __init machine_init(unsigned long dt_ptr, unsigned long phys)
 {
         /* Enable early debugging if any specified (see udbg.h) */
         udbg_early_init();
@@ -142,7 +142,7 @@ void __init machine_init(unsigned long dt_ptr, unsigned long phys)
 
 #ifdef CONFIG_BOOKE_WDT
 /* Checks wdt=x and wdt_period=xx command-line option */
-int __init early_parse_wdt(char *p)
+notrace int __init early_parse_wdt(char *p)
 {
         if (p && strncmp(p, "0", 1) != 0)
                booke_wdt_enabled = 1;
diff --git a/arch/powerpc/kernel/vmlinux.lds.S b/arch/powerpc/kernel/vmlinux.lds.S
index 6856f6c15727..87a72c66ce27 100644
--- a/arch/powerpc/kernel/vmlinux.lds.S
+++ b/arch/powerpc/kernel/vmlinux.lds.S
@@ -64,8 +64,6 @@ SECTIONS
 
         NOTES
 
-        BUG_TABLE
-
 /*
  * Init sections discarded at runtime
  */
diff --git a/arch/powerpc/platforms/powermac/Makefile b/arch/powerpc/platforms/powermac/Makefile
index 4d72c8f72159..89774177b209 100644
--- a/arch/powerpc/platforms/powermac/Makefile
+++ b/arch/powerpc/platforms/powermac/Makefile
@@ -1,5 +1,10 @@
 CFLAGS_bootx_init.o             += -fPIC
 
+ifdef CONFIG_FTRACE
+# Do not trace early boot code
+CFLAGS_REMOVE_bootx_init.o = -pg
+endif
+
 obj-y                           += pic.o setup.o time.o feature.o pci.o \
                                    sleep.o low_i2c.o cache.o pfunc_core.o \
                                    pfunc_base.o
diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig
index 107e492cb47e..5dc8f8028d52 100644
--- a/arch/s390/Kconfig
+++ b/arch/s390/Kconfig
@@ -146,6 +146,7 @@ config MATHEMU
 config COMPAT
         bool "Kernel support for 31 bit emulation"
         depends on 64BIT
+        select COMPAT_BINFMT_ELF
         help
           Select this option if you want to enable your system kernel to
           handle system-calls from ELF binaries for 31 bit ESA.  This option
@@ -312,6 +313,10 @@ config ARCH_SPARSEMEM_DEFAULT
 config ARCH_SELECT_MEMORY_MODEL
        def_bool y
 
+config ARCH_ENABLE_MEMORY_HOTPLUG
+        def_bool y
+        depends on SPARSEMEM
+
 source "mm/Kconfig"
 
 comment "I/O subsystem configuration"
@@ -344,6 +349,22 @@ config QDIO_DEBUG
 
           If unsure, say N.
 
+config CHSC_SCH
+        tristate "Support for CHSC subchannels"
+        help
+          This driver allows usage of CHSC subchannels. A CHSC subchannel
+          is usually present on LPAR only.
+          The driver creates a device /dev/chsc, which may be used to
+          obtain I/O configuration information about the machine and
+          to issue asynchronous chsc commands (DANGEROUS).
+          You will usually only want to use this interface on a special
+          LPAR designated for system management.
+
+          To compile this driver as a module, choose M here: the
+          module will be called chsc_sch.
+
+          If unsure, say N.
+
 comment "Misc"
 
 config IPL
diff --git a/arch/s390/appldata/appldata.h b/arch/s390/appldata/appldata.h
index db3ae8505103..17a2636fec0a 100644
--- a/arch/s390/appldata/appldata.h
+++ b/arch/s390/appldata/appldata.h
@@ -3,13 +3,11 @@
  *
  * Definitions and interface for Linux - z/VM Monitor Stream.
  *
- * Copyright (C) 2003,2006 IBM Corporation, IBM Deutschland Entwicklung GmbH.
+ * Copyright IBM Corp. 2003, 2008
  *
  * Author: Gerald Schaefer <gerald.schaefer@de.ibm.com>
  */
 
-//#define APPLDATA_DEBUG                        /* Debug messages on/off */
-
 #define APPLDATA_MAX_REC_SIZE     4024  /* Maximum size of the */
                                         /* data buffer */
 #define APPLDATA_MAX_PROCS 100
@@ -32,12 +30,6 @@
 #define P_ERROR(x...)   printk(KERN_ERR MY_PRINT_NAME " error: " x)
 #define P_WARNING(x...) printk(KERN_WARNING MY_PRINT_NAME " status: " x)
 
-#ifdef APPLDATA_DEBUG
-#define P_DEBUG(x...)   printk(KERN_DEBUG MY_PRINT_NAME " debug: " x)
-#else
-#define P_DEBUG(x...)   do {} while (0)
-#endif
-
 struct appldata_ops {
         struct list_head list;
         struct ctl_table_header *sysctl_header;
diff --git a/arch/s390/appldata/appldata_base.c b/arch/s390/appldata/appldata_base.c
index ad40729bec3d..9cb3d92447a3 100644
--- a/arch/s390/appldata/appldata_base.c
+++ b/arch/s390/appldata/appldata_base.c
@@ -5,7 +5,7 @@
  * Exports appldata_register_ops() and appldata_unregister_ops() for the
  * data gathering modules.
  *
- * Copyright (C) 2003,2006 IBM Corporation, IBM Deutschland Entwicklung GmbH.
+ * Copyright IBM Corp. 2003, 2008
  *
  * Author: Gerald Schaefer <gerald.schaefer@de.ibm.com>
  */
@@ -108,9 +108,6 @@ static LIST_HEAD(appldata_ops_list);
  */
 static void appldata_timer_function(unsigned long data)
 {
-        P_DEBUG("   -= Timer =-\n");
-        P_DEBUG("CPU: %i, expire_count: %i\n", smp_processor_id(),
-                atomic_read(&appldata_expire_count));
         if (atomic_dec_and_test(&appldata_expire_count)) {
                 atomic_set(&appldata_expire_count, num_online_cpus());
                 queue_work(appldata_wq, (struct work_struct *) data);
@@ -128,14 +125,11 @@ static void appldata_work_fn(struct work_struct *work)
         struct appldata_ops *ops;
         int i;
 
-        P_DEBUG("  -= Work Queue =-\n");
         i = 0;
         get_online_cpus();
         spin_lock(&appldata_ops_lock);
         list_for_each(lh, &appldata_ops_list) {
                 ops = list_entry(lh, struct appldata_ops, list);
-                P_DEBUG("list_for_each loop: %i) active = %u, name = %s\n",
-                        ++i, ops->active, ops->name);
                 if (ops->active == 1) {
                         ops->callback(ops->data);
                 }
@@ -212,7 +206,6 @@ __appldata_vtimer_setup(int cmd)
                                                  0, 1);
                 }
                 appldata_timer_active = 1;
-                P_INFO("Monitoring timer started.\n");
                 break;
         case APPLDATA_DEL_TIMER:
                 for_each_online_cpu(i)
@@ -221,7 +214,6 @@ __appldata_vtimer_setup(int cmd)
                         break;
                 appldata_timer_active = 0;
                 atomic_set(&appldata_expire_count, num_online_cpus());
-                P_INFO("Monitoring timer stopped.\n");
                 break;
         case APPLDATA_MOD_TIMER:
                 per_cpu_interval = (u64) (appldata_interval*1000 /
@@ -313,10 +305,8 @@ appldata_interval_handler(ctl_table *ctl, int write, struct file *filp,
         }
         interval = 0;
         sscanf(buf, "%i", &interval);
-        if (interval <= 0) {
-                P_ERROR("Timer CPU interval has to be > 0!\n");
+        if (interval <= 0)
                 return -EINVAL;
-        }
 
         get_online_cpus();
         spin_lock(&appldata_timer_lock);
@@ -324,9 +314,6 @@ appldata_interval_handler(ctl_table *ctl, int write, struct file *filp,
         __appldata_vtimer_setup(APPLDATA_MOD_TIMER);
         spin_unlock(&appldata_timer_lock);
         put_online_cpus();
-
-        P_INFO("Monitoring CPU interval set to %u milliseconds.\n",
-                 interval);
 out:
         *lenp = len;
         *ppos += len;
@@ -406,23 +393,16 @@ appldata_generic_handler(ctl_table *ctl, int write, struct file *filp,
                         P_ERROR("START DIAG 0xDC for %s failed, "
                                 "return code: %d\n", ops->name, rc);
                         module_put(ops->owner);
-                } else {
-                        P_INFO("Monitoring %s data enabled, "
-                                "DIAG 0xDC started.\n", ops->name);
+                } else
                         ops->active = 1;
-                }
         } else if ((buf[0] == '0') && (ops->active == 1)) {
                 ops->active = 0;
                 rc = appldata_diag(ops->record_nr, APPLDATA_STOP_REC,
                                 (unsigned long) ops->data, ops->size,
                                 ops->mod_lvl);
-                if (rc != 0) {
+                if (rc != 0)
                         P_ERROR("STOP DIAG 0xDC for %s failed, "
                                 "return code: %d\n", ops->name, rc);
-                } else {
-                        P_INFO("Monitoring %s data disabled, "
-                                "DIAG 0xDC stopped.\n", ops->name);
-                }
                 module_put(ops->owner);
         }
         spin_unlock(&appldata_ops_lock);
@@ -468,7 +448,6 @@ int appldata_register_ops(struct appldata_ops *ops)
         ops->sysctl_header = register_sysctl_table(ops->ctl_table);
         if (!ops->sysctl_header)
                 goto out;
-        P_INFO("%s-ops registered!\n", ops->name);
         return 0;
 out:
         spin_lock(&appldata_ops_lock);
@@ -490,7 +469,6 @@ void appldata_unregister_ops(struct appldata_ops *ops)
         spin_unlock(&appldata_ops_lock);
         unregister_sysctl_table(ops->sysctl_header);
         kfree(ops->ctl_table);
-        P_INFO("%s-ops unregistered!\n", ops->name);
 }
 /********************** module-ops management <END> **************************/
 
@@ -553,14 +531,9 @@ static int __init appldata_init(void)
 {
         int i;
 
-        P_DEBUG("sizeof(parameter_list) = %lu\n",
-                sizeof(struct appldata_parameter_list));
-
         appldata_wq = create_singlethread_workqueue("appldata");
-        if (!appldata_wq) {
-                P_ERROR("Could not create work queue\n");
+        if (!appldata_wq)
                 return -ENOMEM;
-        }
 
         get_online_cpus();
         for_each_online_cpu(i)
@@ -571,8 +544,6 @@ static int __init appldata_init(void)
         register_hotcpu_notifier(&appldata_nb);
 
         appldata_sysctl_header = register_sysctl_table(appldata_dir_table);
-
-        P_DEBUG("Base interface initialized.\n");
         return 0;
 }
 
@@ -584,7 +555,9 @@ EXPORT_SYMBOL_GPL(appldata_register_ops);
 EXPORT_SYMBOL_GPL(appldata_unregister_ops);
 EXPORT_SYMBOL_GPL(appldata_diag);
 
+#ifdef CONFIG_SWAP
 EXPORT_SYMBOL_GPL(si_swapinfo);
+#endif
 EXPORT_SYMBOL_GPL(nr_threads);
 EXPORT_SYMBOL_GPL(nr_running);
 EXPORT_SYMBOL_GPL(nr_iowait);
diff --git a/arch/s390/appldata/appldata_mem.c b/arch/s390/appldata/appldata_mem.c
index 51181ccdb87b..3ed56b7d1b2f 100644
--- a/arch/s390/appldata/appldata_mem.c
+++ b/arch/s390/appldata/appldata_mem.c
@@ -14,14 +14,13 @@
 #include <linux/slab.h>
 #include <linux/errno.h>
 #include <linux/kernel_stat.h>
-#include <asm/io.h>
 #include <linux/pagemap.h>
 #include <linux/swap.h>
+#include <asm/io.h>
 
 #include "appldata.h"
 
 
-#define MY_PRINT_NAME "appldata_mem"            /* for debug messages, etc. */
 #define P2K(x) ((x) << (PAGE_SHIFT - 10))       /* Converts #Pages to KB */
 
 /*
@@ -70,30 +69,6 @@ static struct appldata_mem_data {
 } __attribute__((packed)) appldata_mem_data;
 
 
-static inline void appldata_debug_print(struct appldata_mem_data *mem_data)
-{
-        P_DEBUG("--- MEM - RECORD ---\n");
-        P_DEBUG("pgpgin     = %8lu KB\n", mem_data->pgpgin);
-        P_DEBUG("pgpgout    = %8lu KB\n", mem_data->pgpgout);
-        P_DEBUG("pswpin     = %8lu Pages\n", mem_data->pswpin);
-        P_DEBUG("pswpout    = %8lu Pages\n", mem_data->pswpout);
-        P_DEBUG("pgalloc    = %8lu \n", mem_data->pgalloc);
-        P_DEBUG("pgfault    = %8lu \n", mem_data->pgfault);
-        P_DEBUG("pgmajfault = %8lu \n", mem_data->pgmajfault);
-        P_DEBUG("sharedram  = %8lu KB\n", mem_data->sharedram);
-        P_DEBUG("totalram   = %8lu KB\n", mem_data->totalram);
-        P_DEBUG("freeram    = %8lu KB\n", mem_data->freeram);
-        P_DEBUG("totalhigh  = %8lu KB\n", mem_data->totalhigh);
-        P_DEBUG("freehigh   = %8lu KB\n", mem_data->freehigh);
-        P_DEBUG("bufferram  = %8lu KB\n", mem_data->bufferram);
-        P_DEBUG("cached     = %8lu KB\n", mem_data->cached);
-        P_DEBUG("totalswap  = %8lu KB\n", mem_data->totalswap);
-        P_DEBUG("freeswap   = %8lu KB\n", mem_data->freeswap);
-        P_DEBUG("sync_count_1 = %u\n", mem_data->sync_count_1);
-        P_DEBUG("sync_count_2 = %u\n", mem_data->sync_count_2);
-        P_DEBUG("timestamp    = %lX\n", mem_data->timestamp);
-}
-
 /*
  * appldata_get_mem_data()
  *
@@ -140,9 +115,6 @@ static void appldata_get_mem_data(void *data)
 
         mem_data->timestamp = get_clock();
         mem_data->sync_count_2++;
-#ifdef APPLDATA_DEBUG
-        appldata_debug_print(mem_data);
-#endif
 }
 
 
@@ -164,17 +136,7 @@ static struct appldata_ops ops = {
  */
 static int __init appldata_mem_init(void)
 {
-        int rc;
-
-        P_DEBUG("sizeof(mem) = %lu\n", sizeof(struct appldata_mem_data));
-
-        rc = appldata_register_ops(&ops);
-        if (rc != 0) {
-                P_ERROR("Error registering ops, rc = %i\n", rc);
-        } else {
-                P_DEBUG("%s-ops registered!\n", ops.name);
-        }
-        return rc;
+        return appldata_register_ops(&ops);
 }
 
 /*
@@ -185,7 +147,6 @@ static int __init appldata_mem_init(void)
 static void __exit appldata_mem_exit(void)
 {
         appldata_unregister_ops(&ops);
-        P_DEBUG("%s-ops unregistered!\n", ops.name);
 }
 
 
diff --git a/arch/s390/appldata/appldata_net_sum.c b/arch/s390/appldata/appldata_net_sum.c
index 4d8344336001..3b746556e1a3 100644
--- a/arch/s390/appldata/appldata_net_sum.c
+++ b/arch/s390/appldata/appldata_net_sum.c
@@ -21,9 +21,6 @@
 #include "appldata.h"
 
 
-#define MY_PRINT_NAME   "appldata_net_sum"      /* for debug messages, etc. */
-
-
 /*
  * Network data
  *
@@ -60,26 +57,6 @@ static struct appldata_net_sum_data {
 } __attribute__((packed)) appldata_net_sum_data;
 
 
-static inline void appldata_print_debug(struct appldata_net_sum_data *net_data)
-{
-        P_DEBUG("--- NET - RECORD ---\n");
-
-        P_DEBUG("nr_interfaces = %u\n", net_data->nr_interfaces);
-        P_DEBUG("rx_packets    = %8lu\n", net_data->rx_packets);
-        P_DEBUG("tx_packets    = %8lu\n", net_data->tx_packets);
-        P_DEBUG("rx_bytes      = %8lu\n", net_data->rx_bytes);
-        P_DEBUG("tx_bytes      = %8lu\n", net_data->tx_bytes);
-        P_DEBUG("rx_errors     = %8lu\n", net_data->rx_errors);
-        P_DEBUG("tx_errors     = %8lu\n", net_data->tx_errors);
-        P_DEBUG("rx_dropped    = %8lu\n", net_data->rx_dropped);
-        P_DEBUG("tx_dropped    = %8lu\n", net_data->tx_dropped);
-        P_DEBUG("collisions    = %8lu\n", net_data->collisions);
-
-        P_DEBUG("sync_count_1 = %u\n", net_data->sync_count_1);
-        P_DEBUG("sync_count_2 = %u\n", net_data->sync_count_2);
-        P_DEBUG("timestamp    = %lX\n", net_data->timestamp);
-}
-
 /*
  * appldata_get_net_sum_data()
  *
@@ -135,9 +112,6 @@ static void appldata_get_net_sum_data(void *data)
 
         net_data->timestamp = get_clock();
         net_data->sync_count_2++;
-#ifdef APPLDATA_DEBUG
-        appldata_print_debug(net_data);
-#endif
 }
 
 
@@ -159,17 +133,7 @@ static struct appldata_ops ops = {
  */
 static int __init appldata_net_init(void)
 {
-        int rc;
-
-        P_DEBUG("sizeof(net) = %lu\n", sizeof(struct appldata_net_sum_data));
-
-        rc = appldata_register_ops(&ops);
-        if (rc != 0) {
-                P_ERROR("Error registering ops, rc = %i\n", rc);
-        } else {
-                P_DEBUG("%s-ops registered!\n", ops.name);
-        }
-        return rc;
+        return appldata_register_ops(&ops);
 }
 
 /*
@@ -180,7 +144,6 @@ static int __init appldata_net_init(void)
 static void __exit appldata_net_exit(void)
 {
         appldata_unregister_ops(&ops);
-        P_DEBUG("%s-ops unregistered!\n", ops.name);
 }
 
 
diff --git a/arch/s390/appldata/appldata_os.c b/arch/s390/appldata/appldata_os.c
index 6b3eafe10453..eb44f9f8ab91 100644
--- a/arch/s390/appldata/appldata_os.c
+++ b/arch/s390/appldata/appldata_os.c
@@ -89,44 +89,6 @@ static struct appldata_ops ops = {
 };
 
 
-static inline void appldata_print_debug(struct appldata_os_data *os_data)
-{
-        int a0, a1, a2, i;
-
-        P_DEBUG("--- OS - RECORD ---\n");
-        P_DEBUG("nr_threads   = %u\n", os_data->nr_threads);
-        P_DEBUG("nr_running   = %u\n", os_data->nr_running);
-        P_DEBUG("nr_iowait    = %u\n", os_data->nr_iowait);
-        P_DEBUG("avenrun(int) = %8x / %8x / %8x\n", os_data->avenrun[0],
-                os_data->avenrun[1], os_data->avenrun[2]);
-        a0 = os_data->avenrun[0];
-        a1 = os_data->avenrun[1];
-        a2 = os_data->avenrun[2];
-        P_DEBUG("avenrun(float) = %d.%02d / %d.%02d / %d.%02d\n",
-                LOAD_INT(a0), LOAD_FRAC(a0), LOAD_INT(a1), LOAD_FRAC(a1),
-                LOAD_INT(a2), LOAD_FRAC(a2));
-
-        P_DEBUG("nr_cpus = %u\n", os_data->nr_cpus);
-        for (i = 0; i < os_data->nr_cpus; i++) {
-                P_DEBUG("cpu%u : user = %u, nice = %u, system = %u, "
-                        "idle = %u, irq = %u, softirq = %u, iowait = %u, "
-                        "steal = %u\n",
-                                os_data->os_cpu[i].cpu_id,
-                                os_data->os_cpu[i].per_cpu_user,
-                                os_data->os_cpu[i].per_cpu_nice,
-                                os_data->os_cpu[i].per_cpu_system,
-                                os_data->os_cpu[i].per_cpu_idle,
-                                os_data->os_cpu[i].per_cpu_irq,
-                                os_data->os_cpu[i].per_cpu_softirq,
-                                os_data->os_cpu[i].per_cpu_iowait,
-                                os_data->os_cpu[i].per_cpu_steal);
-        }
-
-        P_DEBUG("sync_count_1 = %u\n", os_data->sync_count_1);
-        P_DEBUG("sync_count_2 = %u\n", os_data->sync_count_2);
-        P_DEBUG("timestamp    = %lX\n", os_data->timestamp);
-}
-
 /*
  * appldata_get_os_data()
  *
@@ -180,13 +142,10 @@ static void appldata_get_os_data(void *data)
                                            APPLDATA_START_INTERVAL_REC,
                                            (unsigned long) ops.data, new_size,
                                            ops.mod_lvl);
-                        if (rc != 0) {
+                        if (rc != 0)
                                 P_ERROR("os: START NEW DIAG 0xDC failed, "
                                         "return code: %d, new size = %i\n", rc,
                                         new_size);
-                                P_INFO("os: stopping old record now\n");
-                        } else
-                                P_INFO("os: new record size = %i\n", new_size);
 
                         rc = appldata_diag(APPLDATA_RECORD_OS_ID,
                                            APPLDATA_STOP_REC,
@@ -204,9 +163,6 @@ static void appldata_get_os_data(void *data)
         }
         os_data->timestamp = get_clock();
         os_data->sync_count_2++;
-#ifdef APPLDATA_DEBUG
-        appldata_print_debug(os_data);
-#endif
 }
 
 
@@ -227,12 +183,9 @@ static int __init appldata_os_init(void)
                 rc = -ENOMEM;
                 goto out;
         }
-        P_DEBUG("max. sizeof(os) = %i, sizeof(os_cpu) = %lu\n", max_size,
-                sizeof(struct appldata_os_per_cpu));
 
         appldata_os_data = kzalloc(max_size, GFP_DMA);
         if (appldata_os_data == NULL) {
-                P_ERROR("No memory for %s!\n", ops.name);
                 rc = -ENOMEM;
                 goto out;
         }
@@ -240,17 +193,12 @@ static int __init appldata_os_init(void)
         appldata_os_data->per_cpu_size = sizeof(struct appldata_os_per_cpu);
         appldata_os_data->cpu_offset   = offsetof(struct appldata_os_data,
                                                         os_cpu);
-        P_DEBUG("cpu offset = %u\n", appldata_os_data->cpu_offset);
 
         ops.data = appldata_os_data;
         ops.callback  = &appldata_get_os_data;
         rc = appldata_register_ops(&ops);
-        if (rc != 0) {
-                P_ERROR("Error registering ops, rc = %i\n", rc);
+        if (rc != 0)
                 kfree(appldata_os_data);
-        } else {
-                P_DEBUG("%s-ops registered!\n", ops.name);
-        }
 out:
         return rc;
 }
@@ -264,7 +212,6 @@ static void __exit appldata_os_exit(void)
 {
         appldata_unregister_ops(&ops);
         kfree(appldata_os_data);
-        P_DEBUG("%s-ops unregistered!\n", ops.name);
 }
 
 
diff --git a/arch/s390/crypto/crypt_s390.h b/arch/s390/crypto/crypt_s390.h
index 9992f95ef992..0ef9829f2ad6 100644
--- a/arch/s390/crypto/crypt_s390.h
+++ b/arch/s390/crypto/crypt_s390.h
@@ -296,6 +296,10 @@ static inline int crypt_s390_func_available(int func)
         unsigned char status[16];
         int ret;
 
+        /* check if CPACF facility (bit 17) is available */
+        if (!(stfl() & 1ULL << (31 - 17)))
+                return 0;
+
         switch (func & CRYPT_S390_OP_MASK) {
         case CRYPT_S390_KM:
                 ret = crypt_s390_km(KM_QUERY, &status, NULL, NULL, 0);
diff --git a/arch/s390/crypto/prng.c b/arch/s390/crypto/prng.c
index 0cfefddd8375..eca724d229ec 100644
--- a/arch/s390/crypto/prng.c
+++ b/arch/s390/crypto/prng.c
@@ -6,6 +6,7 @@
 #include <linux/fs.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
+#include <linux/smp_lock.h>
 #include <linux/miscdevice.h>
 #include <linux/module.h>
 #include <linux/moduleparam.h>
@@ -48,6 +49,7 @@ static unsigned char parm_block[32] = {
 
 static int prng_open(struct inode *inode, struct file *file)
 {
+        cycle_kernel_lock();
         return nonseekable_open(inode, file);
 }
 
@@ -185,11 +187,8 @@ static int __init prng_init(void)
         prng_seed(16);
 
         ret = misc_register(&prng_dev);
-        if (ret) {
-                printk(KERN_WARNING
-                       "Could not register misc device for PRNG.\n");
+        if (ret)
                 goto out_buf;
-        }
         return 0;
 
 out_buf:
diff --git a/arch/s390/hypfs/inode.c b/arch/s390/hypfs/inode.c
index 4b010ff814c9..7383781f3e6a 100644
--- a/arch/s390/hypfs/inode.c
+++ b/arch/s390/hypfs/inode.c
@@ -150,33 +150,24 @@ static ssize_t hypfs_aio_read(struct kiocb *iocb, const struct iovec *iov,
                               unsigned long nr_segs, loff_t offset)
 {
         char *data;
-        size_t len;
+        ssize_t ret;
         struct file *filp = iocb->ki_filp;
         /* XXX: temporary */
         char __user *buf = iov[0].iov_base;
         size_t count = iov[0].iov_len;
 
-        if (nr_segs != 1) {
-                count = -EINVAL;
-                goto out;
-        }
+        if (nr_segs != 1)
+                return -EINVAL;
 
         data = filp->private_data;
-        len = strlen(data);
-        if (offset > len) {
-                count = 0;
-                goto out;
-        }
-        if (count > len - offset)
-                count = len - offset;
-        if (copy_to_user(buf, data + offset, count)) {
-                count = -EFAULT;
-                goto out;
-        }
-        iocb->ki_pos += count;
+        ret = simple_read_from_buffer(buf, count, &offset, data, strlen(data));
+        if (ret <= 0)
+                return ret;
+
+        iocb->ki_pos += ret;
         file_accessed(filp);
-out:
-        return count;
+
+        return ret;
 }
 static ssize_t hypfs_aio_write(struct kiocb *iocb, const struct iovec *iov,
                               unsigned long nr_segs, loff_t offset)
diff --git a/arch/s390/kernel/Makefile b/arch/s390/kernel/Makefile
index 6302f5082588..50f657e77344 100644
--- a/arch/s390/kernel/Makefile
+++ b/arch/s390/kernel/Makefile
@@ -7,9 +7,14 @@
 #
 CFLAGS_smp.o    := -Wno-nonnull
 
+#
+# Pass UTS_MACHINE for user_regset definition
+#
+CFLAGS_ptrace.o         += -DUTS_MACHINE='"$(UTS_MACHINE)"'
+
 obj-y   :=  bitmap.o traps.o time.o process.o base.o early.o \
             setup.o sys_s390.o ptrace.o signal.o cpcmd.o ebcdic.o \
-            s390_ext.o debug.o irq.o ipl.o dis.o diag.o
+            s390_ext.o debug.o irq.o ipl.o dis.o diag.o mem_detect.o
 
 obj-y   += $(if $(CONFIG_64BIT),entry64.o,entry.o)
 obj-y   += $(if $(CONFIG_64BIT),reipl64.o,reipl.o)
@@ -23,7 +28,7 @@ obj-$(CONFIG_AUDIT)		+= audit.o
 compat-obj-$(CONFIG_AUDIT)      += compat_audit.o
 obj-$(CONFIG_COMPAT)            += compat_linux.o compat_signal.o \
                                         compat_wrapper.o compat_exec_domain.o \
-                                        binfmt_elf32.o $(compat-obj-y)
+                                        $(compat-obj-y)
 
 obj-$(CONFIG_VIRT_TIMER)        += vtime.o
 obj-$(CONFIG_STACKTRACE)        += stacktrace.o
diff --git a/arch/s390/kernel/binfmt_elf32.c b/arch/s390/kernel/binfmt_elf32.c
deleted file mode 100644
index 3e1c315b736d..000000000000
--- a/arch/s390/kernel/binfmt_elf32.c
+++ /dev/null
@@ -1,214 +0,0 @@
-/*
- * Support for 32-bit Linux for S390 ELF binaries.
- *
- * Copyright (C) 2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
- * Author(s): Gerhard Tonn (ton@de.ibm.com)
- *
- * Heavily inspired by the 32-bit Sparc compat code which is
- * Copyright (C) 1995, 1996, 1997, 1998 David S. Miller (davem@redhat.com)
- * Copyright (C) 1995, 1996, 1997, 1998 Jakub Jelinek   (jj@ultra.linux.cz)
- */
-
-#define __ASMS390_ELF_H
-
-#include <linux/time.h>
-
-/*
- * These are used to set parameters in the core dumps.
- */
-#define ELF_CLASS       ELFCLASS32
-#define ELF_DATA        ELFDATA2MSB
-#define ELF_ARCH        EM_S390
-
-/*
- * This is used to ensure we don't load something for the wrong architecture.
- */
-#define elf_check_arch(x) \
-        (((x)->e_machine == EM_S390 || (x)->e_machine == EM_S390_OLD) \
-         && (x)->e_ident[EI_CLASS] == ELF_CLASS)
-
-/* ELF register definitions */
-#define NUM_GPRS      16
-#define NUM_FPRS      16
-#define NUM_ACRS      16    
-
-/* For SVR4/S390 the function pointer to be registered with `atexit` is
-   passed in R14. */
-#define ELF_PLAT_INIT(_r, load_addr) \
-        do { \
-                _r->gprs[14] = 0; \
-        } while(0)
-
-#define USE_ELF_CORE_DUMP
-#define ELF_EXEC_PAGESIZE       4096
-
-/* This is the location that an ET_DYN program is loaded if exec'ed.  Typical
-   use of this is to invoke "./ld.so someprog" to test out a new version of
-   the loader.  We need to make sure that it is out of the way of the program
-   that it will "exec", and that there is sufficient room for the brk.  */
-
-#define ELF_ET_DYN_BASE         (TASK_SIZE / 3 * 2)
-
-/* Wow, the "main" arch needs arch dependent functions too.. :) */
-
-/* regs is struct pt_regs, pr_reg is elf_gregset_t (which is
-   now struct_user_regs, they are different) */
-
-#define ELF_CORE_COPY_REGS(pr_reg, regs) dump_regs32(regs, &pr_reg);
-
-#define ELF_CORE_COPY_TASK_REGS(tsk, regs) dump_task_regs32(tsk, regs)
-
-#define ELF_CORE_COPY_FPREGS(tsk, fpregs) dump_task_fpu(tsk, fpregs)
-
-/* This yields a mask that user programs can use to figure out what
-   instruction set this CPU supports. */
-
-#define ELF_HWCAP (0)
-
-/* This yields a string that ld.so will use to load implementation
-   specific libraries for optimization.  This is more specific in
-   intent than poking at uname or /proc/cpuinfo.
-
-   For the moment, we have only optimizations for the Intel generations,
-   but that could change... */
-
-#define ELF_PLATFORM (NULL)
-
-#define SET_PERSONALITY(ex, ibcs2)                      \
-do {                                                    \
-        if (ibcs2)                                      \
-                set_personality(PER_SVR4);              \
-        else if (current->personality != PER_LINUX32)   \
-                set_personality(PER_LINUX);             \
-        set_thread_flag(TIF_31BIT);                     \
-} while (0)
-
-#include "compat_linux.h"
-
-typedef _s390_fp_regs32 elf_fpregset_t;
-
-typedef struct
-{
-        
-        _psw_t32        psw;
-        __u32           gprs[__NUM_GPRS]; 
-        __u32           acrs[__NUM_ACRS]; 
-        __u32           orig_gpr2;
-} s390_regs32;
-typedef s390_regs32 elf_gregset_t;
-
-static inline int dump_regs32(struct pt_regs *ptregs, elf_gregset_t *regs)
-{
-        int i;
-
-        memcpy(&regs->psw.mask, &ptregs->psw.mask, 4);
-        memcpy(&regs->psw.addr, (char *)&ptregs->psw.addr + 4, 4);
-        for (i = 0; i < NUM_GPRS; i++)
-                regs->gprs[i] = ptregs->gprs[i];
-        save_access_regs(regs->acrs);
-        regs->orig_gpr2 = ptregs->orig_gpr2;
-        return 1;
-}
-
-static inline int dump_task_regs32(struct task_struct *tsk, elf_gregset_t *regs)
-{
-        struct pt_regs *ptregs = task_pt_regs(tsk);
-        int i;
-
-        memcpy(&regs->psw.mask, &ptregs->psw.mask, 4);
-        memcpy(&regs->psw.addr, (char *)&ptregs->psw.addr + 4, 4);
-        for (i = 0; i < NUM_GPRS; i++)
-                regs->gprs[i] = ptregs->gprs[i];
-        memcpy(regs->acrs, tsk->thread.acrs, sizeof(regs->acrs));
-        regs->orig_gpr2 = ptregs->orig_gpr2;
-        return 1;
-}
-
-static inline int dump_task_fpu(struct task_struct *tsk, elf_fpregset_t *fpregs)
-{
-        if (tsk == current)
-                save_fp_regs((s390_fp_regs *) fpregs);
-        else
-                memcpy(fpregs, &tsk->thread.fp_regs, sizeof(elf_fpregset_t));
-        return 1;
-}
-
-#include <asm/processor.h>
-#include <asm/pgalloc.h>
-#include <linux/module.h>
-#include <linux/elfcore.h>
-#include <linux/binfmts.h>
-#include <linux/compat.h>
-
-#define elf_prstatus elf_prstatus32
-struct elf_prstatus32
-{
-        struct elf_siginfo pr_info;     /* Info associated with signal */
-        short   pr_cursig;              /* Current signal */
-        u32     pr_sigpend;     /* Set of pending signals */
-        u32     pr_sighold;     /* Set of held signals */
-        pid_t   pr_pid;
-        pid_t   pr_ppid;
-        pid_t   pr_pgrp;
-        pid_t   pr_sid;
-        struct compat_timeval pr_utime; /* User time */
-        struct compat_timeval pr_stime; /* System time */
-        struct compat_timeval pr_cutime;        /* Cumulative user time */
-        struct compat_timeval pr_cstime;        /* Cumulative system time */
-        elf_gregset_t pr_reg;   /* GP registers */
-        int pr_fpvalid;         /* True if math co-processor being used.  */
-};
-
-#define elf_prpsinfo elf_prpsinfo32
-struct elf_prpsinfo32
-{
-        char    pr_state;       /* numeric process state */
-        char    pr_sname;       /* char for pr_state */
-        char    pr_zomb;        /* zombie */
-        char    pr_nice;        /* nice val */
-        u32     pr_flag;        /* flags */
-        u16     pr_uid;
-        u16     pr_gid;
-        pid_t   pr_pid, pr_ppid, pr_pgrp, pr_sid;
-        /* Lots missing */
-        char    pr_fname[16];   /* filename of executable */
-        char    pr_psargs[ELF_PRARGSZ]; /* initial part of arg list */
-};
-
-#include <linux/highuid.h>
-
-/*
-#define init_elf_binfmt init_elf32_binfmt
-*/
-
-#undef start_thread
-#define start_thread                    start_thread31 
-
-static inline void start_thread31(struct pt_regs *regs, unsigned long new_psw,
-                                  unsigned long new_stackp)
-{
-        set_fs(USER_DS);
-        regs->psw.mask  = psw_user32_bits;
-        regs->psw.addr  = new_psw;
-        regs->gprs[15]  = new_stackp;
-        crst_table_downgrade(current->mm, 1UL << 31);
-}
-
-MODULE_DESCRIPTION("Binary format loader for compatibility with 32bit Linux for S390 binaries,"
-                   " Copyright 2000 IBM Corporation"); 
-MODULE_AUTHOR("Gerhard Tonn <ton@de.ibm.com>");
-
-#undef MODULE_DESCRIPTION
-#undef MODULE_AUTHOR
-
-#undef cputime_to_timeval
-#define cputime_to_timeval cputime_to_compat_timeval
-static inline void
-cputime_to_compat_timeval(const cputime_t cputime, struct compat_timeval *value)
-{
-        value->tv_usec = cputime % 1000000;
-        value->tv_sec = cputime / 1000000;
-}
-
-#include "../../../fs/binfmt_elf.c"
-
diff --git a/arch/s390/kernel/compat_ptrace.h b/arch/s390/kernel/compat_ptrace.h
index 419aef913ee1..cde81fa64f89 100644
--- a/arch/s390/kernel/compat_ptrace.h
+++ b/arch/s390/kernel/compat_ptrace.h
@@ -1,7 +1,7 @@
 #ifndef _PTRACE32_H
 #define _PTRACE32_H
 
-#include "compat_linux.h"  /* needed for _psw_t32 */
+#include "compat_linux.h"  /* needed for psw_compat_t */
 
 typedef struct {
         __u32 cr[3];
@@ -38,7 +38,7 @@ typedef struct {
 
 struct user_regs_struct32
 {
-        _psw_t32 psw;
+        psw_compat_t psw;
         u32 gprs[NUM_GPRS];
         u32 acrs[NUM_ACRS];
         u32 orig_gpr2;
diff --git a/arch/s390/kernel/debug.c b/arch/s390/kernel/debug.c
index c93d1296cc0a..d80fcd4a7fe1 100644
--- a/arch/s390/kernel/debug.c
+++ b/arch/s390/kernel/debug.c
@@ -1079,7 +1079,6 @@ __init debug_init(void)
         s390dbf_sysctl_header = register_sysctl_table(s390dbf_dir_table);
         mutex_lock(&debug_mutex);
         debug_debugfs_root_entry = debugfs_create_dir(DEBUG_DIR_ROOT,NULL);
-        printk(KERN_INFO "debug: Initialization complete\n");
         initialized = 1;
         mutex_unlock(&debug_mutex);
 
@@ -1193,7 +1192,6 @@ debug_get_uint(char *buf)
         for(; isspace(*buf); buf++);
         rc = simple_strtoul(buf, &buf, 10);
         if(*buf){
-                printk("debug: no integer specified!\n");
                 rc = -EINVAL;
         }
         return rc;
@@ -1340,19 +1338,12 @@ static void debug_flush(debug_info_t* id, int area)
                                 memset(id->areas[i][j], 0, PAGE_SIZE);
                         }
                 }
-                printk(KERN_INFO "debug: %s: all areas flushed\n",id->name);
         } else if(area >= 0 && area < id->nr_areas) {
                 id->active_entries[area] = 0;
                 id->active_pages[area] = 0;
                 for(i = 0; i < id->pages_per_area; i++) {
                         memset(id->areas[area][i],0,PAGE_SIZE);
                 }
-                printk(KERN_INFO "debug: %s: area %i has been flushed\n",
-                        id->name, area);
-        } else {
-                printk(KERN_INFO
-                      "debug: %s: area %i cannot be flushed (range: %i - %i)\n",
-                        id->name, area, 0, id->nr_areas-1);
         }
         spin_unlock_irqrestore(&id->lock,flags);
 }
diff --git a/arch/s390/kernel/early.c b/arch/s390/kernel/early.c
index d0e09684b9ce..2a2ca268b1dd 100644
--- a/arch/s390/kernel/early.c
+++ b/arch/s390/kernel/early.c
@@ -14,6 +14,7 @@
 #include <linux/module.h>
 #include <linux/pfn.h>
 #include <linux/uaccess.h>
+#include <asm/ebcdic.h>
 #include <asm/ipl.h>
 #include <asm/lowcore.h>
 #include <asm/processor.h>
@@ -26,12 +27,40 @@
 /*
  * Create a Kernel NSS if the SAVESYS= parameter is defined
  */
-#define DEFSYS_CMD_SIZE         96
+#define DEFSYS_CMD_SIZE         128
 #define SAVESYS_CMD_SIZE        32
 
 char kernel_nss_name[NSS_NAME_SIZE + 1];
 
+static void __init setup_boot_command_line(void);
+
+
 #ifdef CONFIG_SHARED_KERNEL
+int __init savesys_ipl_nss(char *cmd, const int cmdlen);
+
+asm(
+        "       .section .init.text,\"ax\",@progbits\n"
+        "       .align  4\n"
+        "       .type   savesys_ipl_nss, @function\n"
+        "savesys_ipl_nss:\n"
+#ifdef CONFIG_64BIT
+        "       stmg    6,15,48(15)\n"
+        "       lgr     14,3\n"
+        "       sam31\n"
+        "       diag    2,14,0x8\n"
+        "       sam64\n"
+        "       lgr     2,14\n"
+        "       lmg     6,15,48(15)\n"
+#else
+        "       stm     6,15,24(15)\n"
+        "       lr      14,3\n"
+        "       diag    2,14,0x8\n"
+        "       lr      2,14\n"
+        "       lm      6,15,24(15)\n"
+#endif
+        "       br      14\n"
+        "       .size   savesys_ipl_nss, .-savesys_ipl_nss\n");
+
 static noinline __init void create_kernel_nss(void)
 {
         unsigned int i, stext_pfn, eshared_pfn, end_pfn, min_size;
@@ -39,6 +68,7 @@ static noinline __init void create_kernel_nss(void)
         unsigned int sinitrd_pfn, einitrd_pfn;
 #endif
         int response;
+        size_t len;
         char *savesys_ptr;
         char upper_command_line[COMMAND_LINE_SIZE];
         char defsys_cmd[DEFSYS_CMD_SIZE];
@@ -49,8 +79,8 @@ static noinline __init void create_kernel_nss(void)
                 return;
 
         /* Convert COMMAND_LINE to upper case */
-        for (i = 0; i < strlen(COMMAND_LINE); i++)
-                upper_command_line[i] = toupper(COMMAND_LINE[i]);
+        for (i = 0; i < strlen(boot_command_line); i++)
+                upper_command_line[i] = toupper(boot_command_line[i]);
 
         savesys_ptr = strstr(upper_command_line, "SAVESYS=");
 
@@ -83,7 +113,8 @@ static noinline __init void create_kernel_nss(void)
         }
 #endif
 
-        sprintf(defsys_cmd, "%s EW MINSIZE=%.7iK", defsys_cmd, min_size);
+        sprintf(defsys_cmd, "%s EW MINSIZE=%.7iK PARMREGS=0-13",
+                defsys_cmd, min_size);
         sprintf(savesys_cmd, "SAVESYS %s \n IPL %s",
                 kernel_nss_name, kernel_nss_name);
 
@@ -94,13 +125,24 @@ static noinline __init void create_kernel_nss(void)
                 return;
         }
 
-        __cpcmd(savesys_cmd, NULL, 0, &response);
+        len = strlen(savesys_cmd);
+        ASCEBC(savesys_cmd, len);
+        response = savesys_ipl_nss(savesys_cmd, len);
 
-        if (response != strlen(savesys_cmd)) {
+        /* On success: response is equal to the command size,
+         *             max SAVESYS_CMD_SIZE
+         * On error: response contains the numeric portion of cp error message.
+         *           for SAVESYS it will be >= 263
+         */
+        if (response > SAVESYS_CMD_SIZE) {
                 kernel_nss_name[0] = '\0';
                 return;
         }
 
+        /* re-setup boot command line with new ipl vm parms */
+        ipl_update_parameters();
+        setup_boot_command_line();
+
         ipl_flags = IPL_NSS_VALID;
 }
 
@@ -141,109 +183,11 @@ static noinline __init void detect_machine_type(void)
         if (cpuinfo->cpu_id.version == 0xff)
                 machine_flags |= MACHINE_FLAG_VM;
 
-        /* Running on a P/390 ? */
-        if (cpuinfo->cpu_id.machine == 0x7490)
-                machine_flags |= MACHINE_FLAG_P390;
-
         /* Running under KVM ? */
         if (cpuinfo->cpu_id.version == 0xfe)
                 machine_flags |= MACHINE_FLAG_KVM;
 }
 
-#ifdef CONFIG_64BIT
-static noinline __init int memory_fast_detect(void)
-{
-        unsigned long val0 = 0;
-        unsigned long val1 = 0xc;
-        int ret = -ENOSYS;
-
-        if (ipl_flags & IPL_NSS_VALID)
-                return -ENOSYS;
-
-        asm volatile(
-                "       diag    %1,%2,0x260\n"
-                "0:     lhi     %0,0\n"
-                "1:\n"
-                EX_TABLE(0b,1b)
-                : "+d" (ret), "+d" (val0), "+d" (val1) : : "cc");
-
-        if (ret || val0 != val1)
-                return -ENOSYS;
-
-        memory_chunk[0].size = val0 + 1;
-        return 0;
-}
-#else
-static inline int memory_fast_detect(void)
-{
-        return -ENOSYS;
-}
-#endif
-
-static inline __init unsigned long __tprot(unsigned long addr)
-{
-        int cc = -1;
-
-        asm volatile(
-                "       tprot   0(%1),0\n"
-                "0:     ipm     %0\n"
-                "       srl     %0,28\n"
-                "1:\n"
-                EX_TABLE(0b,1b)
-                : "+d" (cc) : "a" (addr) : "cc");
-        return (unsigned long)cc;
-}
-
-/* Checking memory in 128KB increments. */
-#define CHUNK_INCR      (1UL << 17)
-#define ADDR2G          (1UL << 31)
-
-static noinline __init void find_memory_chunks(unsigned long memsize)
-{
-        unsigned long addr = 0, old_addr = 0;
-        unsigned long old_cc = CHUNK_READ_WRITE;
-        unsigned long cc;
-        int chunk = 0;
-
-        while (chunk < MEMORY_CHUNKS) {
-                cc = __tprot(addr);
-                while (cc == old_cc) {
-                        addr += CHUNK_INCR;
-                        if (memsize && addr >= memsize)
-                                break;
-#ifndef CONFIG_64BIT
-                        if (addr == ADDR2G)
-                                break;
-#endif
-                        cc = __tprot(addr);
-                }
-
-                if (old_addr != addr &&
-                    (old_cc == CHUNK_READ_WRITE || old_cc == CHUNK_READ_ONLY)) {
-                        memory_chunk[chunk].addr = old_addr;
-                        memory_chunk[chunk].size = addr - old_addr;
-                        memory_chunk[chunk].type = old_cc;
-                        chunk++;
-                }
-
-                old_addr = addr;
-                old_cc = cc;
-
-#ifndef CONFIG_64BIT
-                if (addr == ADDR2G)
-                        break;
-#endif
-                /*
-                 * Finish memory detection at the first hole
-                 * if storage size is unknown.
-                 */
-                if (cc == -1UL && !memsize)
-                        break;
-                if (memsize && addr >= memsize)
-                        break;
-        }
-}
-
 static __init void early_pgm_check_handler(void)
 {
         unsigned long addr;
@@ -380,23 +324,61 @@ static __init void detect_machine_facilities(void)
 #endif
 }
 
+static __init void rescue_initrd(void)
+{
+#ifdef CONFIG_BLK_DEV_INITRD
+        /*
+         * Move the initrd right behind the bss section in case it starts
+         * within the bss section. So we don't overwrite it when the bss
+         * section gets cleared.
+         */
+        if (!INITRD_START || !INITRD_SIZE)
+                return;
+        if (INITRD_START >= (unsigned long) __bss_stop)
+                return;
+        memmove(__bss_stop, (void *) INITRD_START, INITRD_SIZE);
+        INITRD_START = (unsigned long) __bss_stop;
+#endif
+}
+
+/* Set up boot command line */
+static void __init setup_boot_command_line(void)
+{
+        char *parm = NULL;
+
+        /* copy arch command line */
+        strlcpy(boot_command_line, COMMAND_LINE, ARCH_COMMAND_LINE_SIZE);
+        boot_command_line[ARCH_COMMAND_LINE_SIZE - 1] = 0;
+
+        /* append IPL PARM data to the boot command line */
+        if (MACHINE_IS_VM) {
+                parm = boot_command_line + strlen(boot_command_line);
+                *parm++ = ' ';
+                get_ipl_vmparm(parm);
+                if (parm[0] == '=')
+                        memmove(boot_command_line, parm + 1, strlen(parm));
+        }
+}
+
+
 /*
  * Save ipl parameters, clear bss memory, initialize storage keys
  * and create a kernel NSS at startup if the SAVESYS= parm is defined
  */
 void __init startup_init(void)
 {
-        unsigned long long memsize;
-
         ipl_save_parameters();
+        rescue_initrd();
         clear_bss_section();
         init_kernel_storage_key();
         lockdep_init();
         lockdep_off();
-        detect_machine_type();
-        create_kernel_nss();
         sort_main_extable();
         setup_lowcore_early();
+        detect_machine_type();
+        ipl_update_parameters();
+        setup_boot_command_line();
+        create_kernel_nss();
         detect_mvpg();
         detect_ieee();
         detect_csp();
@@ -404,18 +386,7 @@ void __init startup_init(void)
         detect_diag44();
         detect_machine_facilities();
         setup_hpage();
-        sclp_read_info_early();
         sclp_facilities_detect();
-        memsize = sclp_memory_detect();
-#ifndef CONFIG_64BIT
-        /*
-         * Can't deal with more than 2G in 31 bit addressing mode, so
-         * limit the value in order to avoid strange side effects.
-         */
-        if (memsize > ADDR2G)
-                memsize = ADDR2G;
-#endif
-        if (memory_fast_detect() < 0)
-                find_memory_chunks((unsigned long) memsize);
+        detect_memory_layout(memory_chunk);
         lockdep_on();
 }
diff --git a/arch/s390/kernel/ipl.c b/arch/s390/kernel/ipl.c
index 532542447d66..54b2779b5e2f 100644
--- a/arch/s390/kernel/ipl.c
+++ b/arch/s390/kernel/ipl.c
@@ -14,6 +14,7 @@
 #include <linux/delay.h>
 #include <linux/reboot.h>
 #include <linux/ctype.h>
+#include <linux/fs.h>
 #include <asm/ipl.h>
 #include <asm/smp.h>
 #include <asm/setup.h>
@@ -22,6 +23,7 @@
 #include <asm/ebcdic.h>
 #include <asm/reset.h>
 #include <asm/sclp.h>
+#include <asm/setup.h>
 
 #define IPL_PARM_BLOCK_VERSION 0
 
@@ -121,6 +123,7 @@ enum ipl_method {
         REIPL_METHOD_FCP_RO_VM,
         REIPL_METHOD_FCP_DUMP,
         REIPL_METHOD_NSS,
+        REIPL_METHOD_NSS_DIAG,
         REIPL_METHOD_DEFAULT,
 };
 
@@ -134,14 +137,15 @@ enum dump_method {
 
 static int diag308_set_works = 0;
 
+static struct ipl_parameter_block ipl_block;
+
 static int reipl_capabilities = IPL_TYPE_UNKNOWN;
 
 static enum ipl_type reipl_type = IPL_TYPE_UNKNOWN;
 static enum ipl_method reipl_method = REIPL_METHOD_DEFAULT;
 static struct ipl_parameter_block *reipl_block_fcp;
 static struct ipl_parameter_block *reipl_block_ccw;
-
-static char reipl_nss_name[NSS_NAME_SIZE + 1];
+static struct ipl_parameter_block *reipl_block_nss;
 
 static int dump_capabilities = DUMP_TYPE_NONE;
 static enum dump_type dump_type = DUMP_TYPE_NONE;
@@ -263,6 +267,56 @@ static ssize_t ipl_type_show(struct kobject *kobj, struct kobj_attribute *attr,
 
 static struct kobj_attribute sys_ipl_type_attr = __ATTR_RO(ipl_type);
 
+/* VM IPL PARM routines */
+static void reipl_get_ascii_vmparm(char *dest,
+                                   const struct ipl_parameter_block *ipb)
+{
+        int i;
+        int len = 0;
+        char has_lowercase = 0;
+
+        if ((ipb->ipl_info.ccw.vm_flags & DIAG308_VM_FLAGS_VP_VALID) &&
+            (ipb->ipl_info.ccw.vm_parm_len > 0)) {
+
+                len = ipb->ipl_info.ccw.vm_parm_len;
+                memcpy(dest, ipb->ipl_info.ccw.vm_parm, len);
+                /* If at least one character is lowercase, we assume mixed
+                 * case; otherwise we convert everything to lowercase.
+                 */
+                for (i = 0; i < len; i++)
+                        if ((dest[i] > 0x80 && dest[i] < 0x8a) || /* a-i */
+                            (dest[i] > 0x90 && dest[i] < 0x9a) || /* j-r */
+                            (dest[i] > 0xa1 && dest[i] < 0xaa)) { /* s-z */
+                                has_lowercase = 1;
+                                break;
+                        }
+                if (!has_lowercase)
+                        EBC_TOLOWER(dest, len);
+                EBCASC(dest, len);
+        }
+        dest[len] = 0;
+}
+
+void get_ipl_vmparm(char *dest)
+{
+        if (diag308_set_works && (ipl_block.hdr.pbt == DIAG308_IPL_TYPE_CCW))
+                reipl_get_ascii_vmparm(dest, &ipl_block);
+        else
+                dest[0] = 0;
+}
+
+static ssize_t ipl_vm_parm_show(struct kobject *kobj,
+                                struct kobj_attribute *attr, char *page)
+{
+        char parm[DIAG308_VMPARM_SIZE + 1] = {};
+
+        get_ipl_vmparm(parm);
+        return sprintf(page, "%s\n", parm);
+}
+
+static struct kobj_attribute sys_ipl_vm_parm_attr =
+        __ATTR(parm, S_IRUGO, ipl_vm_parm_show, NULL);
+
 static ssize_t sys_ipl_device_show(struct kobject *kobj,
                                    struct kobj_attribute *attr, char *page)
 {
@@ -285,14 +339,8 @@ static struct kobj_attribute sys_ipl_device_attr =
 static ssize_t ipl_parameter_read(struct kobject *kobj, struct bin_attribute *attr,
                                   char *buf, loff_t off, size_t count)
 {
-        unsigned int size = IPL_PARMBLOCK_SIZE;
-
-        if (off > size)
-                return 0;
-        if (off + count > size)
-                count = size - off;
-        memcpy(buf, (void *)IPL_PARMBLOCK_START + off, count);
-        return count;
+        return memory_read_from_buffer(buf, count, &off, IPL_PARMBLOCK_START,
+                                        IPL_PARMBLOCK_SIZE);
 }
 
 static struct bin_attribute ipl_parameter_attr = {
@@ -310,12 +358,7 @@ static ssize_t ipl_scp_data_read(struct kobject *kobj, struct bin_attribute *att
         unsigned int size = IPL_PARMBLOCK_START->ipl_info.fcp.scp_data_len;
         void *scp_data = &IPL_PARMBLOCK_START->ipl_info.fcp.scp_data;
 
-        if (off > size)
-                return 0;
-        if (off + count > size)
-                count = size - off;
-        memcpy(buf, scp_data + off, count);
-        return count;
+        return memory_read_from_buffer(buf, count, &off, scp_data, size);
 }
 
 static struct bin_attribute ipl_scp_data_attr = {
@@ -370,15 +413,27 @@ static ssize_t ipl_ccw_loadparm_show(struct kobject *kobj,
 static struct kobj_attribute sys_ipl_ccw_loadparm_attr =
         __ATTR(loadparm, 0444, ipl_ccw_loadparm_show, NULL);
 
-static struct attribute *ipl_ccw_attrs[] = {
+static struct attribute *ipl_ccw_attrs_vm[] = {
         &sys_ipl_type_attr.attr,
         &sys_ipl_device_attr.attr,
         &sys_ipl_ccw_loadparm_attr.attr,
+        &sys_ipl_vm_parm_attr.attr,
         NULL,
 };
 
-static struct attribute_group ipl_ccw_attr_group = {
-        .attrs = ipl_ccw_attrs,
+static struct attribute *ipl_ccw_attrs_lpar[] = {
+        &sys_ipl_type_attr.attr,
+        &sys_ipl_device_attr.attr,
+        &sys_ipl_ccw_loadparm_attr.attr,
+        NULL,
+};
+
+static struct attribute_group ipl_ccw_attr_group_vm = {
+        .attrs = ipl_ccw_attrs_vm,
+};
+
+static struct attribute_group ipl_ccw_attr_group_lpar = {
+        .attrs = ipl_ccw_attrs_lpar
 };
 
 /* NSS ipl device attributes */
@@ -388,6 +443,8 @@ DEFINE_IPL_ATTR_RO(ipl_nss, name, "%s\n", kernel_nss_name);
 static struct attribute *ipl_nss_attrs[] = {
         &sys_ipl_type_attr.attr,
         &sys_ipl_nss_name_attr.attr,
+        &sys_ipl_ccw_loadparm_attr.attr,
+        &sys_ipl_vm_parm_attr.attr,
         NULL,
 };
 
@@ -450,7 +507,12 @@ static int __init ipl_init(void)
         }
         switch (ipl_info.type) {
         case IPL_TYPE_CCW:
-                rc = sysfs_create_group(&ipl_kset->kobj, &ipl_ccw_attr_group);
+                if (MACHINE_IS_VM)
+                        rc = sysfs_create_group(&ipl_kset->kobj,
+                                                &ipl_ccw_attr_group_vm);
+                else
+                        rc = sysfs_create_group(&ipl_kset->kobj,
+                                                &ipl_ccw_attr_group_lpar);
                 break;
         case IPL_TYPE_FCP:
         case IPL_TYPE_FCP_DUMP:
@@ -481,6 +543,83 @@ static struct shutdown_action __refdata ipl_action = {
  * reipl shutdown action: Reboot Linux on shutdown.
  */
 
+/* VM IPL PARM attributes */
+static ssize_t reipl_generic_vmparm_show(struct ipl_parameter_block *ipb,
+                                          char *page)
+{
+        char vmparm[DIAG308_VMPARM_SIZE + 1] = {};
+
+        reipl_get_ascii_vmparm(vmparm, ipb);
+        return sprintf(page, "%s\n", vmparm);
+}
+
+static ssize_t reipl_generic_vmparm_store(struct ipl_parameter_block *ipb,
+                                          size_t vmparm_max,
+                                          const char *buf, size_t len)
+{
+        int i, ip_len;
+
+        /* ignore trailing newline */
+        ip_len = len;
+        if ((len > 0) && (buf[len - 1] == '\n'))
+                ip_len--;
+
+        if (ip_len > vmparm_max)
+                return -EINVAL;
+
+        /* parm is used to store kernel options, check for common chars */
+        for (i = 0; i < ip_len; i++)
+                if (!(isalnum(buf[i]) || isascii(buf[i]) || isprint(buf[i])))
+                        return -EINVAL;
+
+        memset(ipb->ipl_info.ccw.vm_parm, 0, DIAG308_VMPARM_SIZE);
+        ipb->ipl_info.ccw.vm_parm_len = ip_len;
+        if (ip_len > 0) {
+                ipb->ipl_info.ccw.vm_flags |= DIAG308_VM_FLAGS_VP_VALID;
+                memcpy(ipb->ipl_info.ccw.vm_parm, buf, ip_len);
+                ASCEBC(ipb->ipl_info.ccw.vm_parm, ip_len);
+        } else {
+                ipb->ipl_info.ccw.vm_flags &= ~DIAG308_VM_FLAGS_VP_VALID;
+        }
+
+        return len;
+}
+
+/* NSS wrapper */
+static ssize_t reipl_nss_vmparm_show(struct kobject *kobj,
+                                     struct kobj_attribute *attr, char *page)
+{
+        return reipl_generic_vmparm_show(reipl_block_nss, page);
+}
+
+static ssize_t reipl_nss_vmparm_store(struct kobject *kobj,
+                                      struct kobj_attribute *attr,
+                                      const char *buf, size_t len)
+{
+        return reipl_generic_vmparm_store(reipl_block_nss, 56, buf, len);
+}
+
+/* CCW wrapper */
+static ssize_t reipl_ccw_vmparm_show(struct kobject *kobj,
+                                     struct kobj_attribute *attr, char *page)
+{
+        return reipl_generic_vmparm_show(reipl_block_ccw, page);
+}
+
+static ssize_t reipl_ccw_vmparm_store(struct kobject *kobj,
+                                      struct kobj_attribute *attr,
+                                      const char *buf, size_t len)
+{
+        return reipl_generic_vmparm_store(reipl_block_ccw, 64, buf, len);
+}
+
+static struct kobj_attribute sys_reipl_nss_vmparm_attr =
+        __ATTR(parm, S_IRUGO | S_IWUSR, reipl_nss_vmparm_show,
+                                        reipl_nss_vmparm_store);
+static struct kobj_attribute sys_reipl_ccw_vmparm_attr =
+        __ATTR(parm, S_IRUGO | S_IWUSR, reipl_ccw_vmparm_show,
+                                        reipl_ccw_vmparm_store);
+
 /* FCP reipl device attributes */
 
 DEFINE_IPL_ATTR_RW(reipl_fcp, wwpn, "0x%016llx\n", "%016llx\n",
@@ -513,27 +652,26 @@ static struct attribute_group reipl_fcp_attr_group = {
 DEFINE_IPL_ATTR_RW(reipl_ccw, device, "0.0.%04llx\n", "0.0.%llx\n",
         reipl_block_ccw->ipl_info.ccw.devno);
 
-static void reipl_get_ascii_loadparm(char *loadparm)
+static void reipl_get_ascii_loadparm(char *loadparm,
+                                     struct ipl_parameter_block *ibp)
 {
-        memcpy(loadparm, &reipl_block_ccw->ipl_info.ccw.load_param,
-               LOADPARM_LEN);
+        memcpy(loadparm, ibp->ipl_info.ccw.load_parm, LOADPARM_LEN);
         EBCASC(loadparm, LOADPARM_LEN);
         loadparm[LOADPARM_LEN] = 0;
         strstrip(loadparm);
 }
 
-static ssize_t reipl_ccw_loadparm_show(struct kobject *kobj,
-                                       struct kobj_attribute *attr, char *page)
+static ssize_t reipl_generic_loadparm_show(struct ipl_parameter_block *ipb,
+                                           char *page)
 {
         char buf[LOADPARM_LEN + 1];
 
-        reipl_get_ascii_loadparm(buf);
+        reipl_get_ascii_loadparm(buf, ipb);
         return sprintf(page, "%s\n", buf);
 }
 
-static ssize_t reipl_ccw_loadparm_store(struct kobject *kobj,
-                                        struct kobj_attribute *attr,
-                                        const char *buf, size_t len)
+static ssize_t reipl_generic_loadparm_store(struct ipl_parameter_block *ipb,
+                                            const char *buf, size_t len)
 {
         int i, lp_len;
 
@@ -552,35 +690,128 @@ static ssize_t reipl_ccw_loadparm_store(struct kobject *kobj,
                 return -EINVAL;
         }
         /* initialize loadparm with blanks */
-        memset(&reipl_block_ccw->ipl_info.ccw.load_param, ' ', LOADPARM_LEN);
+        memset(ipb->ipl_info.ccw.load_parm, ' ', LOADPARM_LEN);
         /* copy and convert to ebcdic */
-        memcpy(&reipl_block_ccw->ipl_info.ccw.load_param, buf, lp_len);
-        ASCEBC(reipl_block_ccw->ipl_info.ccw.load_param, LOADPARM_LEN);
+        memcpy(ipb->ipl_info.ccw.load_parm, buf, lp_len);
+        ASCEBC(ipb->ipl_info.ccw.load_parm, LOADPARM_LEN);
         return len;
 }
 
+/* NSS wrapper */
+static ssize_t reipl_nss_loadparm_show(struct kobject *kobj,
+                                       struct kobj_attribute *attr, char *page)
+{
+        return reipl_generic_loadparm_show(reipl_block_nss, page);
+}
+
+static ssize_t reipl_nss_loadparm_store(struct kobject *kobj,
+                                        struct kobj_attribute *attr,
+                                        const char *buf, size_t len)
+{
+        return reipl_generic_loadparm_store(reipl_block_nss, buf, len);
+}
+
+/* CCW wrapper */
+static ssize_t reipl_ccw_loadparm_show(struct kobject *kobj,
+                                       struct kobj_attribute *attr, char *page)
+{
+        return reipl_generic_loadparm_show(reipl_block_ccw, page);
+}
+
+static ssize_t reipl_ccw_loadparm_store(struct kobject *kobj,
+                                        struct kobj_attribute *attr,
+                                        const char *buf, size_t len)
+{
+        return reipl_generic_loadparm_store(reipl_block_ccw, buf, len);
+}
+
 static struct kobj_attribute sys_reipl_ccw_loadparm_attr =
-        __ATTR(loadparm, 0644, reipl_ccw_loadparm_show,
-               reipl_ccw_loadparm_store);
+        __ATTR(loadparm, S_IRUGO | S_IWUSR, reipl_ccw_loadparm_show,
+                                            reipl_ccw_loadparm_store);
 
-static struct attribute *reipl_ccw_attrs[] = {
+static struct attribute *reipl_ccw_attrs_vm[] = {
         &sys_reipl_ccw_device_attr.attr,
         &sys_reipl_ccw_loadparm_attr.attr,
+        &sys_reipl_ccw_vmparm_attr.attr,
         NULL,
 };
 
-static struct attribute_group reipl_ccw_attr_group = {
+static struct attribute *reipl_ccw_attrs_lpar[] = {
+        &sys_reipl_ccw_device_attr.attr,
+        &sys_reipl_ccw_loadparm_attr.attr,
+        NULL,
+};
+
+static struct attribute_group reipl_ccw_attr_group_vm = {
+        .name  = IPL_CCW_STR,
+        .attrs = reipl_ccw_attrs_vm,
+};
+
+static struct attribute_group reipl_ccw_attr_group_lpar = {
         .name  = IPL_CCW_STR,
-        .attrs = reipl_ccw_attrs,
+        .attrs = reipl_ccw_attrs_lpar,
 };
 
 
 /* NSS reipl device attributes */
+static void reipl_get_ascii_nss_name(char *dst,
+                                     struct ipl_parameter_block *ipb)
+{
+        memcpy(dst, ipb->ipl_info.ccw.nss_name, NSS_NAME_SIZE);
+        EBCASC(dst, NSS_NAME_SIZE);
+        dst[NSS_NAME_SIZE] = 0;
+}
+
+static ssize_t reipl_nss_name_show(struct kobject *kobj,
+                                   struct kobj_attribute *attr, char *page)
+{
+        char nss_name[NSS_NAME_SIZE + 1] = {};
 
-DEFINE_IPL_ATTR_STR_RW(reipl_nss, name, "%s\n", "%s\n", reipl_nss_name);
+        reipl_get_ascii_nss_name(nss_name, reipl_block_nss);
+        return sprintf(page, "%s\n", nss_name);
+}
+
+static ssize_t reipl_nss_name_store(struct kobject *kobj,
+                                    struct kobj_attribute *attr,
+                                    const char *buf, size_t len)
+{
+        int nss_len;
+
+        /* ignore trailing newline */
+        nss_len = len;
+        if ((len > 0) && (buf[len - 1] == '\n'))
+                nss_len--;
+
+        if (nss_len > NSS_NAME_SIZE)
+                return -EINVAL;
+
+        memset(reipl_block_nss->ipl_info.ccw.nss_name, 0x40, NSS_NAME_SIZE);
+        if (nss_len > 0) {
+                reipl_block_nss->ipl_info.ccw.vm_flags |=
+                        DIAG308_VM_FLAGS_NSS_VALID;
+                memcpy(reipl_block_nss->ipl_info.ccw.nss_name, buf, nss_len);
+                ASCEBC(reipl_block_nss->ipl_info.ccw.nss_name, nss_len);
+                EBC_TOUPPER(reipl_block_nss->ipl_info.ccw.nss_name, nss_len);
+        } else {
+                reipl_block_nss->ipl_info.ccw.vm_flags &=
+                        ~DIAG308_VM_FLAGS_NSS_VALID;
+        }
+
+        return len;
+}
+
+static struct kobj_attribute sys_reipl_nss_name_attr =
+        __ATTR(name, S_IRUGO | S_IWUSR, reipl_nss_name_show,
+                                        reipl_nss_name_store);
+
+static struct kobj_attribute sys_reipl_nss_loadparm_attr =
+        __ATTR(loadparm, S_IRUGO | S_IWUSR, reipl_nss_loadparm_show,
+                                            reipl_nss_loadparm_store);
 
 static struct attribute *reipl_nss_attrs[] = {
         &sys_reipl_nss_name_attr.attr,
+        &sys_reipl_nss_loadparm_attr.attr,
+        &sys_reipl_nss_vmparm_attr.attr,
         NULL,
 };
 
@@ -617,7 +848,10 @@ static int reipl_set_type(enum ipl_type type)
                 reipl_method = REIPL_METHOD_FCP_DUMP;
                 break;
         case IPL_TYPE_NSS:
-                reipl_method = REIPL_METHOD_NSS;
+                if (diag308_set_works)
+                        reipl_method = REIPL_METHOD_NSS_DIAG;
+                else
+                        reipl_method = REIPL_METHOD_NSS;
                 break;
         case IPL_TYPE_UNKNOWN:
                 reipl_method = REIPL_METHOD_DEFAULT;
@@ -655,11 +889,38 @@ static struct kobj_attribute reipl_type_attr =
 
 static struct kset *reipl_kset;
 
+static void get_ipl_string(char *dst, struct ipl_parameter_block *ipb,
+                           const enum ipl_method m)
+{
+        char loadparm[LOADPARM_LEN + 1] = {};
+        char vmparm[DIAG308_VMPARM_SIZE + 1] = {};
+        char nss_name[NSS_NAME_SIZE + 1] = {};
+        size_t pos = 0;
+
+        reipl_get_ascii_loadparm(loadparm, ipb);
+        reipl_get_ascii_nss_name(nss_name, ipb);
+        reipl_get_ascii_vmparm(vmparm, ipb);
+
+        switch (m) {
+        case REIPL_METHOD_CCW_VM:
+                pos = sprintf(dst, "IPL %X CLEAR", ipb->ipl_info.ccw.devno);
+                break;
+        case REIPL_METHOD_NSS:
+                pos = sprintf(dst, "IPL %s", nss_name);
+                break;
+        default:
+                break;
+        }
+        if (strlen(loadparm) > 0)
+                pos += sprintf(dst + pos, " LOADPARM '%s'", loadparm);
+        if (strlen(vmparm) > 0)
+                sprintf(dst + pos, " PARM %s", vmparm);
+}
+
 static void reipl_run(struct shutdown_trigger *trigger)
 {
         struct ccw_dev_id devid;
-        static char buf[100];
-        char loadparm[LOADPARM_LEN + 1];
+        static char buf[128];
 
         switch (reipl_method) {
         case REIPL_METHOD_CCW_CIO:
@@ -668,13 +929,7 @@ static void reipl_run(struct shutdown_trigger *trigger)
                 reipl_ccw_dev(&devid);
                 break;
         case REIPL_METHOD_CCW_VM:
-                reipl_get_ascii_loadparm(loadparm);
-                if (strlen(loadparm) == 0)
-                        sprintf(buf, "IPL %X CLEAR",
-                                reipl_block_ccw->ipl_info.ccw.devno);
-                else
-                        sprintf(buf, "IPL %X CLEAR LOADPARM '%s'",
-                                reipl_block_ccw->ipl_info.ccw.devno, loadparm);
+                get_ipl_string(buf, reipl_block_ccw, REIPL_METHOD_CCW_VM);
                 __cpcmd(buf, NULL, 0, NULL);
                 break;
         case REIPL_METHOD_CCW_DIAG:
@@ -691,8 +946,12 @@ static void reipl_run(struct shutdown_trigger *trigger)
         case REIPL_METHOD_FCP_RO_VM:
                 __cpcmd("IPL", NULL, 0, NULL);
                 break;
+        case REIPL_METHOD_NSS_DIAG:
+                diag308(DIAG308_SET, reipl_block_nss);
+                diag308(DIAG308_IPL, NULL);
+                break;
         case REIPL_METHOD_NSS:
-                sprintf(buf, "IPL %s", reipl_nss_name);
+                get_ipl_string(buf, reipl_block_nss, REIPL_METHOD_NSS);
                 __cpcmd(buf, NULL, 0, NULL);
                 break;
         case REIPL_METHOD_DEFAULT:
@@ -707,16 +966,36 @@ static void reipl_run(struct shutdown_trigger *trigger)
         disabled_wait((unsigned long) __builtin_return_address(0));
 }
 
-static void __init reipl_probe(void)
+static void reipl_block_ccw_init(struct ipl_parameter_block *ipb)
 {
-        void *buffer;
+        ipb->hdr.len = IPL_PARM_BLK_CCW_LEN;
+        ipb->hdr.version = IPL_PARM_BLOCK_VERSION;
+        ipb->hdr.blk0_len = IPL_PARM_BLK0_CCW_LEN;
+        ipb->hdr.pbt = DIAG308_IPL_TYPE_CCW;
+}
 
-        buffer = (void *) get_zeroed_page(GFP_KERNEL);
-        if (!buffer)
-                return;
-        if (diag308(DIAG308_STORE, buffer) == DIAG308_RC_OK)
-                diag308_set_works = 1;
-        free_page((unsigned long)buffer);
+static void reipl_block_ccw_fill_parms(struct ipl_parameter_block *ipb)
+{
+        /* LOADPARM */
+        /* check if read scp info worked and set loadparm */
+        if (sclp_ipl_info.is_valid)
+                memcpy(ipb->ipl_info.ccw.load_parm,
+                                &sclp_ipl_info.loadparm, LOADPARM_LEN);
+        else
+                /* read scp info failed: set empty loadparm (EBCDIC blanks) */
+                memset(ipb->ipl_info.ccw.load_parm, 0x40, LOADPARM_LEN);
+        ipb->hdr.flags = DIAG308_FLAGS_LP_VALID;
+
+        /* VM PARM */
+        if (MACHINE_IS_VM && diag308_set_works &&
+            (ipl_block.ipl_info.ccw.vm_flags & DIAG308_VM_FLAGS_VP_VALID)) {
+
+                ipb->ipl_info.ccw.vm_flags |= DIAG308_VM_FLAGS_VP_VALID;
+                ipb->ipl_info.ccw.vm_parm_len =
+                                        ipl_block.ipl_info.ccw.vm_parm_len;
+                memcpy(ipb->ipl_info.ccw.vm_parm,
+                       ipl_block.ipl_info.ccw.vm_parm, DIAG308_VMPARM_SIZE);
+        }
 }
 
 static int __init reipl_nss_init(void)
@@ -725,10 +1004,31 @@ static int __init reipl_nss_init(void)
 
         if (!MACHINE_IS_VM)
                 return 0;
+
+        reipl_block_nss = (void *) get_zeroed_page(GFP_KERNEL);
+        if (!reipl_block_nss)
+                return -ENOMEM;
+
+        if (!diag308_set_works)
+                sys_reipl_nss_vmparm_attr.attr.mode = S_IRUGO;
+
         rc = sysfs_create_group(&reipl_kset->kobj, &reipl_nss_attr_group);
         if (rc)
                 return rc;
-        strncpy(reipl_nss_name, kernel_nss_name, NSS_NAME_SIZE + 1);
+
+        reipl_block_ccw_init(reipl_block_nss);
+        if (ipl_info.type == IPL_TYPE_NSS) {
+                memset(reipl_block_nss->ipl_info.ccw.nss_name,
+                        ' ', NSS_NAME_SIZE);
+                memcpy(reipl_block_nss->ipl_info.ccw.nss_name,
+                        kernel_nss_name, strlen(kernel_nss_name));
+                ASCEBC(reipl_block_nss->ipl_info.ccw.nss_name, NSS_NAME_SIZE);
+                reipl_block_nss->ipl_info.ccw.vm_flags |=
+                        DIAG308_VM_FLAGS_NSS_VALID;
+
+                reipl_block_ccw_fill_parms(reipl_block_nss);
+        }
+
         reipl_capabilities |= IPL_TYPE_NSS;
         return 0;
 }
@@ -740,28 +1040,27 @@ static int __init reipl_ccw_init(void)
         reipl_block_ccw = (void *) get_zeroed_page(GFP_KERNEL);
         if (!reipl_block_ccw)
                 return -ENOMEM;
-        rc = sysfs_create_group(&reipl_kset->kobj, &reipl_ccw_attr_group);
-        if (rc) {
-                free_page((unsigned long)reipl_block_ccw);
-                return rc;
+
+        if (MACHINE_IS_VM) {
+                if (!diag308_set_works)
+                        sys_reipl_ccw_vmparm_attr.attr.mode = S_IRUGO;
+                rc = sysfs_create_group(&reipl_kset->kobj,
+                                        &reipl_ccw_attr_group_vm);
+        } else {
+                if(!diag308_set_works)
+                        sys_reipl_ccw_loadparm_attr.attr.mode = S_IRUGO;
+                rc = sysfs_create_group(&reipl_kset->kobj,
+                                        &reipl_ccw_attr_group_lpar);
         }
-        reipl_block_ccw->hdr.len = IPL_PARM_BLK_CCW_LEN;
-        reipl_block_ccw->hdr.version = IPL_PARM_BLOCK_VERSION;
-        reipl_block_ccw->hdr.blk0_len = IPL_PARM_BLK0_CCW_LEN;
-        reipl_block_ccw->hdr.pbt = DIAG308_IPL_TYPE_CCW;
-        reipl_block_ccw->hdr.flags = DIAG308_FLAGS_LP_VALID;
-        /* check if read scp info worked and set loadparm */
-        if (sclp_ipl_info.is_valid)
-                memcpy(reipl_block_ccw->ipl_info.ccw.load_param,
-                       &sclp_ipl_info.loadparm, LOADPARM_LEN);
-        else
-                /* read scp info failed: set empty loadparm (EBCDIC blanks) */
-                memset(reipl_block_ccw->ipl_info.ccw.load_param, 0x40,
-                       LOADPARM_LEN);
-        if (!MACHINE_IS_VM && !diag308_set_works)
-                sys_reipl_ccw_loadparm_attr.attr.mode = S_IRUGO;
-        if (ipl_info.type == IPL_TYPE_CCW)
+        if (rc)
+                return rc;
+
+        reipl_block_ccw_init(reipl_block_ccw);
+        if (ipl_info.type == IPL_TYPE_CCW) {
                 reipl_block_ccw->ipl_info.ccw.devno = ipl_devno;
+                reipl_block_ccw_fill_parms(reipl_block_ccw);
+        }
+
         reipl_capabilities |= IPL_TYPE_CCW;
         return 0;
 }
@@ -1298,7 +1597,6 @@ static void __init shutdown_actions_init(void)
 
 static int __init s390_ipl_init(void)
 {
-        reipl_probe();
         sclp_get_ipl_info(&sclp_ipl_info);
         shutdown_actions_init();
         shutdown_triggers_init();
@@ -1405,6 +1703,12 @@ void __init setup_ipl(void)
         atomic_notifier_chain_register(&panic_notifier_list, &on_panic_nb);
 }
 
+void __init ipl_update_parameters(void)
+{
+        if (diag308(DIAG308_STORE, &ipl_block) == DIAG308_RC_OK)
+                diag308_set_works = 1;
+}
+
 void __init ipl_save_parameters(void)
 {
         struct cio_iplinfo iplinfo;
diff --git a/arch/s390/kernel/kprobes.c b/arch/s390/kernel/kprobes.c
index ed04d1372d5d..288ad490a6dd 100644
--- a/arch/s390/kernel/kprobes.c
+++ b/arch/s390/kernel/kprobes.c
@@ -41,10 +41,8 @@ int __kprobes arch_prepare_kprobe(struct kprobe *p)
         if (is_prohibited_opcode((kprobe_opcode_t *) p->addr))
                 return -EINVAL;
 
-        if ((unsigned long)p->addr & 0x01) {
-                printk("Attempt to register kprobe at an unaligned address\n");
+        if ((unsigned long)p->addr & 0x01)
                 return -EINVAL;
-                }
 
         /* Use the get_insn_slot() facility for correctness */
         if (!(p->ainsn.insn = get_insn_slot()))
diff --git a/arch/s390/kernel/machine_kexec.c b/arch/s390/kernel/machine_kexec.c
index 3c77dd36994c..131d7ee8b416 100644
--- a/arch/s390/kernel/machine_kexec.c
+++ b/arch/s390/kernel/machine_kexec.c
@@ -52,7 +52,6 @@ void machine_kexec_cleanup(struct kimage *image)
 
 void machine_shutdown(void)
 {
-        printk(KERN_INFO "kexec: machine_shutdown called\n");
 }
 
 void machine_kexec(struct kimage *image)
diff --git a/arch/s390/kernel/mem_detect.c b/arch/s390/kernel/mem_detect.c
new file mode 100644
index 000000000000..18ed7abe16c5
--- /dev/null
+++ b/arch/s390/kernel/mem_detect.c
@@ -0,0 +1,100 @@
+/*
+ *    Copyright IBM Corp. 2008
+ *    Author(s): Heiko Carstens <heiko.carstens@de.ibm.com>
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <asm/ipl.h>
+#include <asm/sclp.h>
+#include <asm/setup.h>
+
+static int memory_fast_detect(struct mem_chunk *chunk)
+{
+        unsigned long val0 = 0;
+        unsigned long val1 = 0xc;
+        int rc = -EOPNOTSUPP;
+
+        if (ipl_flags & IPL_NSS_VALID)
+                return -EOPNOTSUPP;
+        asm volatile(
+                "       diag    %1,%2,0x260\n"
+                "0:     lhi     %0,0\n"
+                "1:\n"
+                EX_TABLE(0b,1b)
+                : "+d" (rc), "+d" (val0), "+d" (val1) : : "cc");
+
+        if (rc || val0 != val1)
+                return -EOPNOTSUPP;
+        chunk->size = val0 + 1;
+        return 0;
+}
+
+static inline int tprot(unsigned long addr)
+{
+        int rc = -EFAULT;
+
+        asm volatile(
+                "       tprot   0(%1),0\n"
+                "0:     ipm     %0\n"
+                "       srl     %0,28\n"
+                "1:\n"
+                EX_TABLE(0b,1b)
+                : "+d" (rc) : "a" (addr) : "cc");
+        return rc;
+}
+
+#define ADDR2G (1ULL << 31)
+
+static void find_memory_chunks(struct mem_chunk chunk[])
+{
+        unsigned long long memsize, rnmax, rzm;
+        unsigned long addr = 0, size;
+        int i = 0, type;
+
+        rzm = sclp_get_rzm();
+        rnmax = sclp_get_rnmax();
+        memsize = rzm * rnmax;
+        if (!rzm)
+                rzm = 1ULL << 17;
+        if (sizeof(long) == 4) {
+                rzm = min(ADDR2G, rzm);
+                memsize = memsize ? min(ADDR2G, memsize) : ADDR2G;
+        }
+        do {
+                size = 0;
+                type = tprot(addr);
+                do {
+                        size += rzm;
+                        if (memsize && addr + size >= memsize)
+                                break;
+                } while (type == tprot(addr + size));
+                if (type == CHUNK_READ_WRITE || type == CHUNK_READ_ONLY) {
+                        chunk[i].addr = addr;
+                        chunk[i].size = size;
+                        chunk[i].type = type;
+                        i++;
+                }
+                addr += size;
+        } while (addr < memsize && i < MEMORY_CHUNKS);
+}
+
+void detect_memory_layout(struct mem_chunk chunk[])
+{
+        unsigned long flags, cr0;
+
+        memset(chunk, 0, MEMORY_CHUNKS * sizeof(struct mem_chunk));
+        if (memory_fast_detect(&chunk[0]) == 0)
+                return;
+        /* Disable IRQs, DAT and low address protection so tprot does the
+         * right thing and we don't get scheduled away with low address
+         * protection disabled.
+         */
+        flags = __raw_local_irq_stnsm(0xf8);
+        __ctl_store(cr0, 0, 0);
+        __ctl_clear_bit(0, 28);
+        find_memory_chunks(chunk);
+        __ctl_load(cr0, 0, 0);
+        __raw_local_irq_ssm(flags);
+}
+EXPORT_SYMBOL(detect_memory_layout);
diff --git a/arch/s390/kernel/process.c b/arch/s390/kernel/process.c
index 7920861109d2..85defd01d293 100644
--- a/arch/s390/kernel/process.c
+++ b/arch/s390/kernel/process.c
@@ -75,46 +75,19 @@ unsigned long thread_saved_pc(struct task_struct *tsk)
         return sf->gprs[8];
 }
 
-/*
- * Need to know about CPUs going idle?
- */
-static ATOMIC_NOTIFIER_HEAD(idle_chain);
 DEFINE_PER_CPU(struct s390_idle_data, s390_idle);
 
-int register_idle_notifier(struct notifier_block *nb)
-{
-        return atomic_notifier_chain_register(&idle_chain, nb);
-}
-EXPORT_SYMBOL(register_idle_notifier);
-
-int unregister_idle_notifier(struct notifier_block *nb)
-{
-        return atomic_notifier_chain_unregister(&idle_chain, nb);
-}
-EXPORT_SYMBOL(unregister_idle_notifier);
-
 static int s390_idle_enter(void)
 {
         struct s390_idle_data *idle;
-        int nr_calls = 0;
-        void *hcpu;
-        int rc;
 
-        hcpu = (void *)(long)smp_processor_id();
-        rc = __atomic_notifier_call_chain(&idle_chain, S390_CPU_IDLE, hcpu, -1,
-                                          &nr_calls);
-        if (rc == NOTIFY_BAD) {
-                nr_calls--;
-                __atomic_notifier_call_chain(&idle_chain, S390_CPU_NOT_IDLE,
-                                             hcpu, nr_calls, NULL);
-                return rc;
-        }
         idle = &__get_cpu_var(s390_idle);
         spin_lock(&idle->lock);
         idle->idle_count++;
         idle->in_idle = 1;
         idle->idle_enter = get_clock();
         spin_unlock(&idle->lock);
+        vtime_stop_cpu_timer();
         return NOTIFY_OK;
 }
 
@@ -122,13 +95,12 @@ void s390_idle_leave(void)
 {
         struct s390_idle_data *idle;
 
+        vtime_start_cpu_timer();
         idle = &__get_cpu_var(s390_idle);
         spin_lock(&idle->lock);
         idle->idle_time += get_clock() - idle->idle_enter;
         idle->in_idle = 0;
         spin_unlock(&idle->lock);
-        atomic_notifier_call_chain(&idle_chain, S390_CPU_NOT_IDLE,
-                                   (void *)(long) smp_processor_id());
 }
 
 extern void s390_handle_mcck(void);
diff --git a/arch/s390/kernel/ptrace.c b/arch/s390/kernel/ptrace.c
index 35827b9bd4d1..2815bfe348a6 100644
--- a/arch/s390/kernel/ptrace.c
+++ b/arch/s390/kernel/ptrace.c
@@ -33,6 +33,8 @@
 #include <linux/security.h>
 #include <linux/audit.h>
 #include <linux/signal.h>
+#include <linux/elf.h>
+#include <linux/regset.h>
 
 #include <asm/segment.h>
 #include <asm/page.h>
@@ -47,6 +49,11 @@
 #include "compat_ptrace.h"
 #endif
 
+enum s390_regset {
+        REGSET_GENERAL,
+        REGSET_FP,
+};
+
 static void
 FixPerRegisters(struct task_struct *task)
 {
@@ -126,24 +133,10 @@ ptrace_disable(struct task_struct *child)
  * struct user contain pad bytes that should be read as zeroes.
  * Lovely...
  */
-static int
-peek_user(struct task_struct *child, addr_t addr, addr_t data)
+static unsigned long __peek_user(struct task_struct *child, addr_t addr)
 {
         struct user *dummy = NULL;
-        addr_t offset, tmp, mask;
-
-        /*
-         * Stupid gdb peeks/pokes the access registers in 64 bit with
-         * an alignment of 4. Programmers from hell...
-         */
-        mask = __ADDR_MASK;
-#ifdef CONFIG_64BIT
-        if (addr >= (addr_t) &dummy->regs.acrs &&
-            addr < (addr_t) &dummy->regs.orig_gpr2)
-                mask = 3;
-#endif
-        if ((addr & mask) || addr > sizeof(struct user) - __ADDR_MASK)
-                return -EIO;
+        addr_t offset, tmp;
 
         if (addr < (addr_t) &dummy->regs.acrs) {
                 /*
@@ -197,24 +190,18 @@ peek_user(struct task_struct *child, addr_t addr, addr_t data)
         } else
                 tmp = 0;
 
-        return put_user(tmp, (addr_t __user *) data);
+        return tmp;
 }
 
-/*
- * Write a word to the user area of a process at location addr. This
- * operation does have an additional problem compared to peek_user.
- * Stores to the program status word and on the floating point
- * control register needs to get checked for validity.
- */
 static int
-poke_user(struct task_struct *child, addr_t addr, addr_t data)
+peek_user(struct task_struct *child, addr_t addr, addr_t data)
 {
         struct user *dummy = NULL;
-        addr_t offset, mask;
+        addr_t tmp, mask;
 
         /*
          * Stupid gdb peeks/pokes the access registers in 64 bit with
-         * an alignment of 4. Programmers from hell indeed...
+         * an alignment of 4. Programmers from hell...
          */
         mask = __ADDR_MASK;
 #ifdef CONFIG_64BIT
@@ -225,6 +212,21 @@ poke_user(struct task_struct *child, addr_t addr, addr_t data)
         if ((addr & mask) || addr > sizeof(struct user) - __ADDR_MASK)
                 return -EIO;
 
+        tmp = __peek_user(child, addr);
+        return put_user(tmp, (addr_t __user *) data);
+}
+
+/*
+ * Write a word to the user area of a process at location addr. This
+ * operation does have an additional problem compared to peek_user.
+ * Stores to the program status word and on the floating point
+ * control register needs to get checked for validity.
+ */
+static int __poke_user(struct task_struct *child, addr_t addr, addr_t data)
+{
+        struct user *dummy = NULL;
+        addr_t offset;
+
         if (addr < (addr_t) &dummy->regs.acrs) {
                 /*
                  * psw and gprs are stored on the stack
@@ -292,6 +294,28 @@ poke_user(struct task_struct *child, addr_t addr, addr_t data)
         return 0;
 }
 
+static int
+poke_user(struct task_struct *child, addr_t addr, addr_t data)
+{
+        struct user *dummy = NULL;
+        addr_t mask;
+
+        /*
+         * Stupid gdb peeks/pokes the access registers in 64 bit with
+         * an alignment of 4. Programmers from hell indeed...
+         */
+        mask = __ADDR_MASK;
+#ifdef CONFIG_64BIT
+        if (addr >= (addr_t) &dummy->regs.acrs &&
+            addr < (addr_t) &dummy->regs.orig_gpr2)
+                mask = 3;
+#endif
+        if ((addr & mask) || addr > sizeof(struct user) - __ADDR_MASK)
+                return -EIO;
+
+        return __poke_user(child, addr, data);
+}
+
 long arch_ptrace(struct task_struct *child, long request, long addr, long data)
 {
         ptrace_area parea; 
@@ -367,18 +391,13 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
 /*
  * Same as peek_user but for a 31 bit program.
  */
-static int
-peek_user_emu31(struct task_struct *child, addr_t addr, addr_t data)
+static u32 __peek_user_compat(struct task_struct *child, addr_t addr)
 {
         struct user32 *dummy32 = NULL;
         per_struct32 *dummy_per32 = NULL;
         addr_t offset;
         __u32 tmp;
 
-        if (!test_thread_flag(TIF_31BIT) ||
-            (addr & 3) || addr > sizeof(struct user) - 3)
-                return -EIO;
-
         if (addr < (addr_t) &dummy32->regs.acrs) {
                 /*
                  * psw and gprs are stored on the stack
@@ -435,25 +454,32 @@ peek_user_emu31(struct task_struct *child, addr_t addr, addr_t data)
         } else
                 tmp = 0;
 
+        return tmp;
+}
+
+static int peek_user_compat(struct task_struct *child,
+                            addr_t addr, addr_t data)
+{
+        __u32 tmp;
+
+        if (!test_thread_flag(TIF_31BIT) ||
+            (addr & 3) || addr > sizeof(struct user) - 3)
+                return -EIO;
+
+        tmp = __peek_user_compat(child, addr);
         return put_user(tmp, (__u32 __user *) data);
 }
 
 /*
  * Same as poke_user but for a 31 bit program.
  */
-static int
-poke_user_emu31(struct task_struct *child, addr_t addr, addr_t data)
+static int __poke_user_compat(struct task_struct *child,
+                              addr_t addr, addr_t data)
 {
         struct user32 *dummy32 = NULL;
         per_struct32 *dummy_per32 = NULL;
+        __u32 tmp = (__u32) data;
         addr_t offset;
-        __u32 tmp;
-
-        if (!test_thread_flag(TIF_31BIT) ||
-            (addr & 3) || addr > sizeof(struct user32) - 3)
-                return -EIO;
-
-        tmp = (__u32) data;
 
         if (addr < (addr_t) &dummy32->regs.acrs) {
                 /*
@@ -528,6 +554,16 @@ poke_user_emu31(struct task_struct *child, addr_t addr, addr_t data)
         return 0;
 }
 
+static int poke_user_compat(struct task_struct *child,
+                            addr_t addr, addr_t data)
+{
+        if (!test_thread_flag(TIF_31BIT) ||
+            (addr & 3) || addr > sizeof(struct user32) - 3)
+                return -EIO;
+
+        return __poke_user_compat(child, addr, data);
+}
+
 long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
                         compat_ulong_t caddr, compat_ulong_t cdata)
 {
@@ -539,11 +575,11 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
         switch (request) {
         case PTRACE_PEEKUSR:
                 /* read the word at location addr in the USER area. */
-                return peek_user_emu31(child, addr, data);
+                return peek_user_compat(child, addr, data);
 
         case PTRACE_POKEUSR:
                 /* write the word at location addr in the USER area */
-                return poke_user_emu31(child, addr, data);
+                return poke_user_compat(child, addr, data);
 
         case PTRACE_PEEKUSR_AREA:
         case PTRACE_POKEUSR_AREA:
@@ -555,13 +591,13 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
                 copied = 0;
                 while (copied < parea.len) {
                         if (request == PTRACE_PEEKUSR_AREA)
-                                ret = peek_user_emu31(child, addr, data);
+                                ret = peek_user_compat(child, addr, data);
                         else {
                                 __u32 utmp;
                                 if (get_user(utmp,
                                              (__u32 __force __user *) data))
                                         return -EFAULT;
-                                ret = poke_user_emu31(child, addr, utmp);
+                                ret = poke_user_compat(child, addr, utmp);
                         }
                         if (ret)
                                 return ret;
@@ -610,3 +646,240 @@ syscall_trace(struct pt_regs *regs, int entryexit)
                                     regs->gprs[2], regs->orig_gpr2, regs->gprs[3],
                                     regs->gprs[4], regs->gprs[5]);
 }
+
+/*
+ * user_regset definitions.
+ */
+
+static int s390_regs_get(struct task_struct *target,
+                         const struct user_regset *regset,
+                         unsigned int pos, unsigned int count,
+                         void *kbuf, void __user *ubuf)
+{
+        if (target == current)
+                save_access_regs(target->thread.acrs);
+
+        if (kbuf) {
+                unsigned long *k = kbuf;
+                while (count > 0) {
+                        *k++ = __peek_user(target, pos);
+                        count -= sizeof(*k);
+                        pos += sizeof(*k);
+                }
+        } else {
+                unsigned long __user *u = ubuf;
+                while (count > 0) {
+                        if (__put_user(__peek_user(target, pos), u++))
+                                return -EFAULT;
+                        count -= sizeof(*u);
+                        pos += sizeof(*u);
+                }
+        }
+        return 0;
+}
+
+static int s390_regs_set(struct task_struct *target,
+                         const struct user_regset *regset,
+                         unsigned int pos, unsigned int count,
+                         const void *kbuf, const void __user *ubuf)
+{
+        int rc = 0;
+
+        if (target == current)
+                save_access_regs(target->thread.acrs);
+
+        if (kbuf) {
+                const unsigned long *k = kbuf;
+                while (count > 0 && !rc) {
+                        rc = __poke_user(target, pos, *k++);
+                        count -= sizeof(*k);
+                        pos += sizeof(*k);
+                }
+        } else {
+                const unsigned long  __user *u = ubuf;
+                while (count > 0 && !rc) {
+                        unsigned long word;
+                        rc = __get_user(word, u++);
+                        if (rc)
+                                break;
+                        rc = __poke_user(target, pos, word);
+                        count -= sizeof(*u);
+                        pos += sizeof(*u);
+                }
+        }
+
+        if (rc == 0 && target == current)
+                restore_access_regs(target->thread.acrs);
+
+        return rc;
+}
+
+static int s390_fpregs_get(struct task_struct *target,
+                           const struct user_regset *regset, unsigned int pos,
+                           unsigned int count, void *kbuf, void __user *ubuf)
+{
+        if (target == current)
+                save_fp_regs(&target->thread.fp_regs);
+
+        return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
+                                   &target->thread.fp_regs, 0, -1);
+}
+
+static int s390_fpregs_set(struct task_struct *target,
+                           const struct user_regset *regset, unsigned int pos,
+                           unsigned int count, const void *kbuf,
+                           const void __user *ubuf)
+{
+        int rc = 0;
+
+        if (target == current)
+                save_fp_regs(&target->thread.fp_regs);
+
+        /* If setting FPC, must validate it first. */
+        if (count > 0 && pos < offsetof(s390_fp_regs, fprs)) {
+                u32 fpc[2] = { target->thread.fp_regs.fpc, 0 };
+                rc = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &fpc,
+                                        0, offsetof(s390_fp_regs, fprs));
+                if (rc)
+                        return rc;
+                if ((fpc[0] & ~FPC_VALID_MASK) != 0 || fpc[1] != 0)
+                        return -EINVAL;
+                target->thread.fp_regs.fpc = fpc[0];
+        }
+
+        if (rc == 0 && count > 0)
+                rc = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
+                                        target->thread.fp_regs.fprs,
+                                        offsetof(s390_fp_regs, fprs), -1);
+
+        if (rc == 0 && target == current)
+                restore_fp_regs(&target->thread.fp_regs);
+
+        return rc;
+}
+
+static const struct user_regset s390_regsets[] = {
+        [REGSET_GENERAL] = {
+                .core_note_type = NT_PRSTATUS,
+                .n = sizeof(s390_regs) / sizeof(long),
+                .size = sizeof(long),
+                .align = sizeof(long),
+                .get = s390_regs_get,
+                .set = s390_regs_set,
+        },
+        [REGSET_FP] = {
+                .core_note_type = NT_PRFPREG,
+                .n = sizeof(s390_fp_regs) / sizeof(long),
+                .size = sizeof(long),
+                .align = sizeof(long),
+                .get = s390_fpregs_get,
+                .set = s390_fpregs_set,
+        },
+};
+
+static const struct user_regset_view user_s390_view = {
+        .name = UTS_MACHINE,
+        .e_machine = EM_S390,
+        .regsets = s390_regsets,
+        .n = ARRAY_SIZE(s390_regsets)
+};
+
+#ifdef CONFIG_COMPAT
+static int s390_compat_regs_get(struct task_struct *target,
+                                const struct user_regset *regset,
+                                unsigned int pos, unsigned int count,
+                                void *kbuf, void __user *ubuf)
+{
+        if (target == current)
+                save_access_regs(target->thread.acrs);
+
+        if (kbuf) {
+                compat_ulong_t *k = kbuf;
+                while (count > 0) {
+                        *k++ = __peek_user_compat(target, pos);
+                        count -= sizeof(*k);
+                        pos += sizeof(*k);
+                }
+        } else {
+                compat_ulong_t __user *u = ubuf;
+                while (count > 0) {
+                        if (__put_user(__peek_user_compat(target, pos), u++))
+                                return -EFAULT;
+                        count -= sizeof(*u);
+                        pos += sizeof(*u);
+                }
+        }
+        return 0;
+}
+
+static int s390_compat_regs_set(struct task_struct *target,
+                                const struct user_regset *regset,
+                                unsigned int pos, unsigned int count,
+                                const void *kbuf, const void __user *ubuf)
+{
+        int rc = 0;
+
+        if (target == current)
+                save_access_regs(target->thread.acrs);
+
+        if (kbuf) {
+                const compat_ulong_t *k = kbuf;
+                while (count > 0 && !rc) {
+                        rc = __poke_user_compat(target, pos, *k++);
+                        count -= sizeof(*k);
+                        pos += sizeof(*k);
+                }
+        } else {
+                const compat_ulong_t  __user *u = ubuf;
+                while (count > 0 && !rc) {
+                        compat_ulong_t word;
+                        rc = __get_user(word, u++);
+                        if (rc)
+                                break;
+                        rc = __poke_user_compat(target, pos, word);
+                        count -= sizeof(*u);
+                        pos += sizeof(*u);
+                }
+        }
+
+        if (rc == 0 && target == current)
+                restore_access_regs(target->thread.acrs);
+
+        return rc;
+}
+
+static const struct user_regset s390_compat_regsets[] = {
+        [REGSET_GENERAL] = {
+                .core_note_type = NT_PRSTATUS,
+                .n = sizeof(s390_compat_regs) / sizeof(compat_long_t),
+                .size = sizeof(compat_long_t),
+                .align = sizeof(compat_long_t),
+                .get = s390_compat_regs_get,
+                .set = s390_compat_regs_set,
+        },
+        [REGSET_FP] = {
+                .core_note_type = NT_PRFPREG,
+                .n = sizeof(s390_fp_regs) / sizeof(compat_long_t),
+                .size = sizeof(compat_long_t),
+                .align = sizeof(compat_long_t),
+                .get = s390_fpregs_get,
+                .set = s390_fpregs_set,
+        },
+};
+
+static const struct user_regset_view user_s390_compat_view = {
+        .name = "s390",
+        .e_machine = EM_S390,
+        .regsets = s390_compat_regsets,
+        .n = ARRAY_SIZE(s390_compat_regsets)
+};
+#endif
+
+const struct user_regset_view *task_user_regset_view(struct task_struct *task)
+{
+#ifdef CONFIG_COMPAT
+        if (test_tsk_thread_flag(task, TIF_31BIT))
+                return &user_s390_compat_view;
+#endif
+        return &user_s390_view;
+}
diff --git a/arch/s390/kernel/setup.c b/arch/s390/kernel/setup.c
index 2bc70b6e876a..b358e18273b0 100644
--- a/arch/s390/kernel/setup.c
+++ b/arch/s390/kernel/setup.c
@@ -77,7 +77,7 @@ unsigned long machine_flags;
 unsigned long elf_hwcap = 0;
 char elf_platform[ELF_PLATFORM_SIZE];
 
-struct mem_chunk __meminitdata memory_chunk[MEMORY_CHUNKS];
+struct mem_chunk __initdata memory_chunk[MEMORY_CHUNKS];
 volatile int __cpu_logical_map[NR_CPUS]; /* logical cpu to cpu address */
 static unsigned long __initdata memory_end;
 
@@ -205,12 +205,6 @@ static void __init conmode_default(void)
                         SET_CONSOLE_SCLP;
 #endif
                 }
-        } else if (MACHINE_IS_P390) {
-#if defined(CONFIG_TN3215_CONSOLE)
-                SET_CONSOLE_3215;
-#elif defined(CONFIG_TN3270_CONSOLE)
-                SET_CONSOLE_3270;
-#endif
         } else {
 #if defined(CONFIG_SCLP_CONSOLE) || defined(CONFIG_SCLP_VT220_CONSOLE)
                 SET_CONSOLE_SCLP;
@@ -221,18 +215,17 @@ static void __init conmode_default(void)
 #if defined(CONFIG_ZFCPDUMP) || defined(CONFIG_ZFCPDUMP_MODULE)
 static void __init setup_zfcpdump(unsigned int console_devno)
 {
-        static char str[64];
+        static char str[41];
 
         if (ipl_info.type != IPL_TYPE_FCP_DUMP)
                 return;
         if (console_devno != -1)
-                sprintf(str, "cio_ignore=all,!0.0.%04x,!0.0.%04x",
+                sprintf(str, " cio_ignore=all,!0.0.%04x,!0.0.%04x",
                         ipl_info.data.fcp.dev_id.devno, console_devno);
         else
-                sprintf(str, "cio_ignore=all,!0.0.%04x",
+                sprintf(str, " cio_ignore=all,!0.0.%04x",
                         ipl_info.data.fcp.dev_id.devno);
-        strcat(COMMAND_LINE, " ");
-        strcat(COMMAND_LINE, str);
+        strcat(boot_command_line, str);
         console_loglevel = 2;
 }
 #else
@@ -289,32 +282,6 @@ static int __init early_parse_mem(char *p)
 }
 early_param("mem", early_parse_mem);
 
-/*
- * "ipldelay=XXX[sm]" sets ipl delay in seconds or minutes
- */
-static int __init early_parse_ipldelay(char *p)
-{
-        unsigned long delay = 0;
-
-        delay = simple_strtoul(p, &p, 0);
-
-        switch (*p) {
-        case 's':
-        case 'S':
-                delay *= 1000000;
-                break;
-        case 'm':
-        case 'M':
-                delay *= 60 * 1000000;
-        }
-
-        /* now wait for the requested amount of time */
-        udelay(delay);
-
-        return 0;
-}
-early_param("ipldelay", early_parse_ipldelay);
-
 #ifdef CONFIG_S390_SWITCH_AMODE
 #ifdef CONFIG_PGSTE
 unsigned int switch_amode = 1;
@@ -804,11 +771,9 @@ setup_arch(char **cmdline_p)
                 printk("We are running native (64 bit mode)\n");
 #endif /* CONFIG_64BIT */
 
-        /* Save unparsed command line copy for /proc/cmdline */
-        strlcpy(boot_command_line, COMMAND_LINE, COMMAND_LINE_SIZE);
-
-        *cmdline_p = COMMAND_LINE;
-        *(*cmdline_p + COMMAND_LINE_SIZE - 1) = '\0';
+        /* Have one command line that is parsed and saved in /proc/cmdline */
+        /* boot_command_line has been already set up in early.c */
+        *cmdline_p = boot_command_line;
 
         ROOT_DEV = Root_RAM0;
 
diff --git a/arch/s390/kernel/time.c b/arch/s390/kernel/time.c
index 7aec676fefd5..7418bebb547f 100644
--- a/arch/s390/kernel/time.c
+++ b/arch/s390/kernel/time.c
@@ -3,7 +3,7 @@
  *    Time of day based timer functions.
  *
  *  S390 version
- *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Copyright IBM Corp. 1999, 2008
  *    Author(s): Hartmut Penner (hp@de.ibm.com),
  *               Martin Schwidefsky (schwidefsky@de.ibm.com),
  *               Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com)
@@ -31,6 +31,7 @@
 #include <linux/notifier.h>
 #include <linux/clocksource.h>
 #include <linux/clockchips.h>
+#include <linux/bootmem.h>
 #include <asm/uaccess.h>
 #include <asm/delay.h>
 #include <asm/s390_ext.h>
@@ -162,7 +163,7 @@ void init_cpu_timer(void)
         /* Enable clock comparator timer interrupt. */
         __ctl_set_bit(0,11);
 
-        /* Always allow ETR external interrupts, even without an ETR. */
+        /* Always allow the timing alert external interrupt. */
         __ctl_set_bit(0, 4);
 }
 
@@ -170,8 +171,21 @@ static void clock_comparator_interrupt(__u16 code)
 {
 }
 
+static void etr_timing_alert(struct etr_irq_parm *);
+static void stp_timing_alert(struct stp_irq_parm *);
+
+static void timing_alert_interrupt(__u16 code)
+{
+        if (S390_lowcore.ext_params & 0x00c40000)
+                etr_timing_alert((struct etr_irq_parm *)
+                                 &S390_lowcore.ext_params);
+        if (S390_lowcore.ext_params & 0x00038000)
+                stp_timing_alert((struct stp_irq_parm *)
+                                 &S390_lowcore.ext_params);
+}
+
 static void etr_reset(void);
-static void etr_ext_handler(__u16);
+static void stp_reset(void);
 
 /*
  * Get the TOD clock running.
@@ -181,6 +195,7 @@ static u64 __init reset_tod_clock(void)
         u64 time;
 
         etr_reset();
+        stp_reset();
         if (store_clock(&time) == 0)
                 return time;
         /* TOD clock not running. Set the clock to Unix Epoch. */
@@ -231,8 +246,9 @@ void __init time_init(void)
         if (clocksource_register(&clocksource_tod) != 0)
                 panic("Could not register TOD clock source");
 
-        /* request the etr external interrupt */
-        if (register_early_external_interrupt(0x1406, etr_ext_handler,
+        /* request the timing alert external interrupt */
+        if (register_early_external_interrupt(0x1406,
+                                              timing_alert_interrupt,
                                               &ext_int_etr_cc) != 0)
                 panic("Couldn't request external interrupt 0x1406");
 
@@ -245,10 +261,112 @@ void __init time_init(void)
 }
 
 /*
+ * The time is "clock". old is what we think the time is.
+ * Adjust the value by a multiple of jiffies and add the delta to ntp.
+ * "delay" is an approximation how long the synchronization took. If
+ * the time correction is positive, then "delay" is subtracted from
+ * the time difference and only the remaining part is passed to ntp.
+ */
+static unsigned long long adjust_time(unsigned long long old,
+                                      unsigned long long clock,
+                                      unsigned long long delay)
+{
+        unsigned long long delta, ticks;
+        struct timex adjust;
+
+        if (clock > old) {
+                /* It is later than we thought. */
+                delta = ticks = clock - old;
+                delta = ticks = (delta < delay) ? 0 : delta - delay;
+                delta -= do_div(ticks, CLK_TICKS_PER_JIFFY);
+                adjust.offset = ticks * (1000000 / HZ);
+        } else {
+                /* It is earlier than we thought. */
+                delta = ticks = old - clock;
+                delta -= do_div(ticks, CLK_TICKS_PER_JIFFY);
+                delta = -delta;
+                adjust.offset = -ticks * (1000000 / HZ);
+        }
+        jiffies_timer_cc += delta;
+        if (adjust.offset != 0) {
+                printk(KERN_NOTICE "etr: time adjusted by %li micro-seconds\n",
+                       adjust.offset);
+                adjust.modes = ADJ_OFFSET_SINGLESHOT;
+                do_adjtimex(&adjust);
+        }
+        return delta;
+}
+
+static DEFINE_PER_CPU(atomic_t, clock_sync_word);
+static unsigned long clock_sync_flags;
+
+#define CLOCK_SYNC_HAS_ETR      0
+#define CLOCK_SYNC_HAS_STP      1
+#define CLOCK_SYNC_ETR          2
+#define CLOCK_SYNC_STP          3
+
+/*
+ * The synchronous get_clock function. It will write the current clock
+ * value to the clock pointer and return 0 if the clock is in sync with
+ * the external time source. If the clock mode is local it will return
+ * -ENOSYS and -EAGAIN if the clock is not in sync with the external
+ * reference.
+ */
+int get_sync_clock(unsigned long long *clock)
+{
+        atomic_t *sw_ptr;
+        unsigned int sw0, sw1;
+
+        sw_ptr = &get_cpu_var(clock_sync_word);
+        sw0 = atomic_read(sw_ptr);
+        *clock = get_clock();
+        sw1 = atomic_read(sw_ptr);
+        put_cpu_var(clock_sync_sync);
+        if (sw0 == sw1 && (sw0 & 0x80000000U))
+                /* Success: time is in sync. */
+                return 0;
+        if (!test_bit(CLOCK_SYNC_HAS_ETR, &clock_sync_flags) &&
+            !test_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags))
+                return -ENOSYS;
+        if (!test_bit(CLOCK_SYNC_ETR, &clock_sync_flags) &&
+            !test_bit(CLOCK_SYNC_STP, &clock_sync_flags))
+                return -EACCES;
+        return -EAGAIN;
+}
+EXPORT_SYMBOL(get_sync_clock);
+
+/*
+ * Make get_sync_clock return -EAGAIN.
+ */
+static void disable_sync_clock(void *dummy)
+{
+        atomic_t *sw_ptr = &__get_cpu_var(clock_sync_word);
+        /*
+         * Clear the in-sync bit 2^31. All get_sync_clock calls will
+         * fail until the sync bit is turned back on. In addition
+         * increase the "sequence" counter to avoid the race of an
+         * etr event and the complete recovery against get_sync_clock.
+         */
+        atomic_clear_mask(0x80000000, sw_ptr);
+        atomic_inc(sw_ptr);
+}
+
+/*
+ * Make get_sync_clock return 0 again.
+ * Needs to be called from a context disabled for preemption.
+ */
+static void enable_sync_clock(void)
+{
+        atomic_t *sw_ptr = &__get_cpu_var(clock_sync_word);
+        atomic_set_mask(0x80000000, sw_ptr);
+}
+
+/*
  * External Time Reference (ETR) code.
  */
 static int etr_port0_online;
 static int etr_port1_online;
+static int etr_steai_available;
 
 static int __init early_parse_etr(char *p)
 {
@@ -273,12 +391,6 @@ enum etr_event {
         ETR_EVENT_UPDATE,
 };
 
-enum etr_flags {
-        ETR_FLAG_ENOSYS,
-        ETR_FLAG_EACCES,
-        ETR_FLAG_STEAI,
-};
-
 /*
  * Valid bit combinations of the eacr register are (x = don't care):
  * e0 e1 dp p0 p1 ea es sl
@@ -305,74 +417,18 @@ enum etr_flags {
  */
 static struct etr_eacr etr_eacr;
 static u64 etr_tolec;                   /* time of last eacr update */
-static unsigned long etr_flags;
 static struct etr_aib etr_port0;
 static int etr_port0_uptodate;
 static struct etr_aib etr_port1;
 static int etr_port1_uptodate;
 static unsigned long etr_events;
 static struct timer_list etr_timer;
-static DEFINE_PER_CPU(atomic_t, etr_sync_word);
 
 static void etr_timeout(unsigned long dummy);
 static void etr_work_fn(struct work_struct *work);
 static DECLARE_WORK(etr_work, etr_work_fn);
 
 /*
- * The etr get_clock function. It will write the current clock value
- * to the clock pointer and return 0 if the clock is in sync with the
- * external time source. If the clock mode is local it will return
- * -ENOSYS and -EAGAIN if the clock is not in sync with the external
- * reference. This function is what ETR is all about..
- */
-int get_sync_clock(unsigned long long *clock)
-{
-        atomic_t *sw_ptr;
-        unsigned int sw0, sw1;
-
-        sw_ptr = &get_cpu_var(etr_sync_word);
-        sw0 = atomic_read(sw_ptr);
-        *clock = get_clock();
-        sw1 = atomic_read(sw_ptr);
-        put_cpu_var(etr_sync_sync);
-        if (sw0 == sw1 && (sw0 & 0x80000000U))
-                /* Success: time is in sync. */
-                return 0;
-        if (test_bit(ETR_FLAG_ENOSYS, &etr_flags))
-                return -ENOSYS;
-        if (test_bit(ETR_FLAG_EACCES, &etr_flags))
-                return -EACCES;
-        return -EAGAIN;
-}
-EXPORT_SYMBOL(get_sync_clock);
-
-/*
- * Make get_sync_clock return -EAGAIN.
- */
-static void etr_disable_sync_clock(void *dummy)
-{
-        atomic_t *sw_ptr = &__get_cpu_var(etr_sync_word);
-        /*
-         * Clear the in-sync bit 2^31. All get_sync_clock calls will
-         * fail until the sync bit is turned back on. In addition
-         * increase the "sequence" counter to avoid the race of an
-         * etr event and the complete recovery against get_sync_clock.
-         */
-        atomic_clear_mask(0x80000000, sw_ptr);
-        atomic_inc(sw_ptr);
-}
-
-/*
- * Make get_sync_clock return 0 again.
- * Needs to be called from a context disabled for preemption.
- */
-static void etr_enable_sync_clock(void)
-{
-        atomic_t *sw_ptr = &__get_cpu_var(etr_sync_word);
-        atomic_set_mask(0x80000000, sw_ptr);
-}
-
-/*
  * Reset ETR attachment.
  */
 static void etr_reset(void)
@@ -381,15 +437,13 @@ static void etr_reset(void)
                 .e0 = 0, .e1 = 0, ._pad0 = 4, .dp = 0,
                 .p0 = 0, .p1 = 0, ._pad1 = 0, .ea = 0,
                 .es = 0, .sl = 0 };
-        if (etr_setr(&etr_eacr) == 0)
+        if (etr_setr(&etr_eacr) == 0) {
                 etr_tolec = get_clock();
-        else {
-                set_bit(ETR_FLAG_ENOSYS, &etr_flags);
-                if (etr_port0_online || etr_port1_online) {
-                        printk(KERN_WARNING "Running on non ETR capable "
-                               "machine, only local mode available.\n");
-                        etr_port0_online = etr_port1_online = 0;
-                }
+                set_bit(CLOCK_SYNC_HAS_ETR, &clock_sync_flags);
+        } else if (etr_port0_online || etr_port1_online) {
+                printk(KERN_WARNING "Running on non ETR capable "
+                       "machine, only local mode available.\n");
+                etr_port0_online = etr_port1_online = 0;
         }
 }
 
@@ -397,14 +451,12 @@ static int __init etr_init(void)
 {
         struct etr_aib aib;
 
-        if (test_bit(ETR_FLAG_ENOSYS, &etr_flags))
+        if (!test_bit(CLOCK_SYNC_HAS_ETR, &clock_sync_flags))
                 return 0;
         /* Check if this machine has the steai instruction. */
         if (etr_steai(&aib, ETR_STEAI_STEPPING_PORT) == 0)
-                set_bit(ETR_FLAG_STEAI, &etr_flags);
+                etr_steai_available = 1;
         setup_timer(&etr_timer, etr_timeout, 0UL);
-        if (!etr_port0_online && !etr_port1_online)
-                set_bit(ETR_FLAG_EACCES, &etr_flags);
         if (etr_port0_online) {
                 set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events);
                 schedule_work(&etr_work);
@@ -435,7 +487,8 @@ void etr_switch_to_local(void)
 {
         if (!etr_eacr.sl)
                 return;
-        etr_disable_sync_clock(NULL);
+        if (test_bit(CLOCK_SYNC_ETR, &clock_sync_flags))
+                disable_sync_clock(NULL);
         set_bit(ETR_EVENT_SWITCH_LOCAL, &etr_events);
         schedule_work(&etr_work);
 }
@@ -450,23 +503,21 @@ void etr_sync_check(void)
 {
         if (!etr_eacr.es)
                 return;
-        etr_disable_sync_clock(NULL);
+        if (test_bit(CLOCK_SYNC_ETR, &clock_sync_flags))
+                disable_sync_clock(NULL);
         set_bit(ETR_EVENT_SYNC_CHECK, &etr_events);
         schedule_work(&etr_work);
 }
 
 /*
- * ETR external interrupt. There are two causes:
+ * ETR timing alert. There are two causes:
  * 1) port state change, check the usability of the port
  * 2) port alert, one of the ETR-data-validity bits (v1-v2 bits of the
  *    sldr-status word) or ETR-data word 1 (edf1) or ETR-data word 3 (edf3)
  *    or ETR-data word 4 (edf4) has changed.
  */
-static void etr_ext_handler(__u16 code)
+static void etr_timing_alert(struct etr_irq_parm *intparm)
 {
-        struct etr_interruption_parameter *intparm =
-                (struct etr_interruption_parameter *) &S390_lowcore.ext_params;
-
         if (intparm->pc0)
                 /* ETR port 0 state change. */
                 set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events);
@@ -591,58 +642,23 @@ static int etr_aib_follows(struct etr_aib *a1, struct etr_aib *a2, int p)
         return 1;
 }
 
-/*
- * The time is "clock". old is what we think the time is.
- * Adjust the value by a multiple of jiffies and add the delta to ntp.
- * "delay" is an approximation how long the synchronization took. If
- * the time correction is positive, then "delay" is subtracted from
- * the time difference and only the remaining part is passed to ntp.
- */
-static unsigned long long etr_adjust_time(unsigned long long old,
-                                          unsigned long long clock,
-                                          unsigned long long delay)
-{
-        unsigned long long delta, ticks;
-        struct timex adjust;
-
-        if (clock > old) {
-                /* It is later than we thought. */
-                delta = ticks = clock - old;
-                delta = ticks = (delta < delay) ? 0 : delta - delay;
-                delta -= do_div(ticks, CLK_TICKS_PER_JIFFY);
-                adjust.offset = ticks * (1000000 / HZ);
-        } else {
-                /* It is earlier than we thought. */
-                delta = ticks = old - clock;
-                delta -= do_div(ticks, CLK_TICKS_PER_JIFFY);
-                delta = -delta;
-                adjust.offset = -ticks * (1000000 / HZ);
-        }
-        jiffies_timer_cc += delta;
-        if (adjust.offset != 0) {
-                printk(KERN_NOTICE "etr: time adjusted by %li micro-seconds\n",
-                       adjust.offset);
-                adjust.modes = ADJ_OFFSET_SINGLESHOT;
-                do_adjtimex(&adjust);
-        }
-        return delta;
-}
-
-static struct {
+struct clock_sync_data {
         int in_sync;
         unsigned long long fixup_cc;
-} etr_sync;
+};
 
-static void etr_sync_cpu_start(void *dummy)
+static void clock_sync_cpu_start(void *dummy)
 {
-        etr_enable_sync_clock();
+        struct clock_sync_data *sync = dummy;
+
+        enable_sync_clock();
         /*
          * This looks like a busy wait loop but it isn't. etr_sync_cpus
          * is called on all other cpus while the TOD clocks is stopped.
          * __udelay will stop the cpu on an enabled wait psw until the
          * TOD is running again.
          */
-        while (etr_sync.in_sync == 0) {
+        while (sync->in_sync == 0) {
                 __udelay(1);
                 /*
                  * A different cpu changes *in_sync. Therefore use
@@ -650,17 +666,17 @@ static void etr_sync_cpu_start(void *dummy)
                  */
                 barrier();
         }
-        if (etr_sync.in_sync != 1)
+        if (sync->in_sync != 1)
                 /* Didn't work. Clear per-cpu in sync bit again. */
-                etr_disable_sync_clock(NULL);
+                disable_sync_clock(NULL);
         /*
          * This round of TOD syncing is done. Set the clock comparator
          * to the next tick and let the processor continue.
          */
-        fixup_clock_comparator(etr_sync.fixup_cc);
+        fixup_clock_comparator(sync->fixup_cc);
 }
 
-static void etr_sync_cpu_end(void *dummy)
+static void clock_sync_cpu_end(void *dummy)
 {
 }
 
@@ -672,6 +688,7 @@ static void etr_sync_cpu_end(void *dummy)
 static int etr_sync_clock(struct etr_aib *aib, int port)
 {
         struct etr_aib *sync_port;
+        struct clock_sync_data etr_sync;
         unsigned long long clock, old_clock, delay, delta;
         int follows;
         int rc;
@@ -690,9 +707,9 @@ static int etr_sync_clock(struct etr_aib *aib, int port)
          */
         memset(&etr_sync, 0, sizeof(etr_sync));
         preempt_disable();
-        smp_call_function(etr_sync_cpu_start, NULL, 0, 0);
+        smp_call_function(clock_sync_cpu_start, &etr_sync, 0, 0);
         local_irq_disable();
-        etr_enable_sync_clock();
+        enable_sync_clock();
 
         /* Set clock to next OTE. */
         __ctl_set_bit(14, 21);
@@ -707,13 +724,13 @@ static int etr_sync_clock(struct etr_aib *aib, int port)
                 /* Adjust Linux timing variables. */
                 delay = (unsigned long long)
                         (aib->edf2.etv - sync_port->edf2.etv) << 32;
-                delta = etr_adjust_time(old_clock, clock, delay);
+                delta = adjust_time(old_clock, clock, delay);
                 etr_sync.fixup_cc = delta;
                 fixup_clock_comparator(delta);
                 /* Verify that the clock is properly set. */
                 if (!etr_aib_follows(sync_port, aib, port)) {
                         /* Didn't work. */
-                        etr_disable_sync_clock(NULL);
+                        disable_sync_clock(NULL);
                         etr_sync.in_sync = -EAGAIN;
                         rc = -EAGAIN;
                 } else {
@@ -724,12 +741,12 @@ static int etr_sync_clock(struct etr_aib *aib, int port)
                 /* Could not set the clock ?!? */
                 __ctl_clear_bit(0, 29);
                 __ctl_clear_bit(14, 21);
-                etr_disable_sync_clock(NULL);
+                disable_sync_clock(NULL);
                 etr_sync.in_sync = -EAGAIN;
                 rc = -EAGAIN;
         }
         local_irq_enable();
-        smp_call_function(etr_sync_cpu_end,NULL,0,0);
+        smp_call_function(clock_sync_cpu_end, NULL, 0, 0);
         preempt_enable();
         return rc;
 }
@@ -832,7 +849,7 @@ static struct etr_eacr etr_handle_update(struct etr_aib *aib,
          * Do not try to get the alternate port aib if the clock
          * is not in sync yet.
          */
-        if (!eacr.es)
+        if (!test_bit(CLOCK_SYNC_STP, &clock_sync_flags) && !eacr.es)
                 return eacr;
 
         /*
@@ -840,7 +857,7 @@ static struct etr_eacr etr_handle_update(struct etr_aib *aib,
          * the other port immediately. If only stetr is available the
          * data-port bit toggle has to be used.
          */
-        if (test_bit(ETR_FLAG_STEAI, &etr_flags)) {
+        if (etr_steai_available) {
                 if (eacr.p0 && !etr_port0_uptodate) {
                         etr_steai_cv(&etr_port0, ETR_STEAI_PORT_0);
                         etr_port0_uptodate = 1;
@@ -909,10 +926,10 @@ static void etr_work_fn(struct work_struct *work)
         if (!eacr.ea) {
                 /* Both ports offline. Reset everything. */
                 eacr.dp = eacr.es = eacr.sl = 0;
-                on_each_cpu(etr_disable_sync_clock, NULL, 0, 1);
+                on_each_cpu(disable_sync_clock, NULL, 0, 1);
                 del_timer_sync(&etr_timer);
                 etr_update_eacr(eacr);
-                set_bit(ETR_FLAG_EACCES, &etr_flags);
+                clear_bit(CLOCK_SYNC_ETR, &clock_sync_flags);
                 return;
         }
 
@@ -953,7 +970,6 @@ static void etr_work_fn(struct work_struct *work)
                         eacr.e1 = 1;
                 sync_port = (etr_port0_uptodate &&
                              etr_port_valid(&etr_port0, 0)) ? 0 : -1;
-                clear_bit(ETR_FLAG_EACCES, &etr_flags);
         } else if (eacr.p1 && aib.esw.psc1 == etr_lpsc_pps_mode) {
                 eacr.sl = 0;
                 eacr.e0 = 0;
@@ -962,7 +978,6 @@ static void etr_work_fn(struct work_struct *work)
                         eacr.es = 0;
                 sync_port = (etr_port1_uptodate &&
                              etr_port_valid(&etr_port1, 1)) ? 1 : -1;
-                clear_bit(ETR_FLAG_EACCES, &etr_flags);
         } else if (eacr.p0 && aib.esw.psc0 == etr_lpsc_operational_step) {
                 eacr.sl = 1;
                 eacr.e0 = 1;
@@ -976,7 +991,6 @@ static void etr_work_fn(struct work_struct *work)
                         eacr.e1 = 1;
                 sync_port = (etr_port0_uptodate &&
                              etr_port_valid(&etr_port0, 0)) ? 0 : -1;
-                clear_bit(ETR_FLAG_EACCES, &etr_flags);
         } else if (eacr.p1 && aib.esw.psc1 == etr_lpsc_operational_step) {
                 eacr.sl = 1;
                 eacr.e0 = 0;
@@ -985,19 +999,22 @@ static void etr_work_fn(struct work_struct *work)
                         eacr.es = 0;
                 sync_port = (etr_port1_uptodate &&
                              etr_port_valid(&etr_port1, 1)) ? 1 : -1;
-                clear_bit(ETR_FLAG_EACCES, &etr_flags);
         } else {
                 /* Both ports not usable. */
                 eacr.es = eacr.sl = 0;
                 sync_port = -1;
-                set_bit(ETR_FLAG_EACCES, &etr_flags);
+                clear_bit(CLOCK_SYNC_ETR, &clock_sync_flags);
         }
 
+        if (!test_bit(CLOCK_SYNC_ETR, &clock_sync_flags))
+                eacr.es = 0;
+
         /*
          * If the clock is in sync just update the eacr and return.
          * If there is no valid sync port wait for a port update.
          */
-        if (eacr.es || sync_port < 0) {
+        if (test_bit(CLOCK_SYNC_STP, &clock_sync_flags) ||
+            eacr.es || sync_port < 0) {
                 etr_update_eacr(eacr);
                 etr_set_tolec_timeout(now);
                 return;
@@ -1018,11 +1035,13 @@ static void etr_work_fn(struct work_struct *work)
          * and set up a timer to try again after 0.5 seconds
          */
         etr_update_eacr(eacr);
+        set_bit(CLOCK_SYNC_ETR, &clock_sync_flags);
         if (now < etr_tolec + (1600000 << 12) ||
             etr_sync_clock(&aib, sync_port) != 0) {
                 /* Sync failed. Try again in 1/2 second. */
                 eacr.es = 0;
                 etr_update_eacr(eacr);
+                clear_bit(CLOCK_SYNC_ETR, &clock_sync_flags);
                 etr_set_sync_timeout();
         } else
                 etr_set_tolec_timeout(now);
@@ -1097,8 +1116,8 @@ static ssize_t etr_online_store(struct sys_device *dev,
         value = simple_strtoul(buf, NULL, 0);
         if (value != 0 && value != 1)
                 return -EINVAL;
-        if (test_bit(ETR_FLAG_ENOSYS, &etr_flags))
-                return -ENOSYS;
+        if (!test_bit(CLOCK_SYNC_HAS_ETR, &clock_sync_flags))
+                return -EOPNOTSUPP;
         if (dev == &etr_port0_dev) {
                 if (etr_port0_online == value)
                         return count;   /* Nothing to do. */
@@ -1292,3 +1311,318 @@ out:
 }
 
 device_initcall(etr_init_sysfs);
+
+/*
+ * Server Time Protocol (STP) code.
+ */
+static int stp_online;
+static struct stp_sstpi stp_info;
+static void *stp_page;
+
+static void stp_work_fn(struct work_struct *work);
+static DECLARE_WORK(stp_work, stp_work_fn);
+
+static int __init early_parse_stp(char *p)
+{
+        if (strncmp(p, "off", 3) == 0)
+                stp_online = 0;
+        else if (strncmp(p, "on", 2) == 0)
+                stp_online = 1;
+        return 0;
+}
+early_param("stp", early_parse_stp);
+
+/*
+ * Reset STP attachment.
+ */
+static void stp_reset(void)
+{
+        int rc;
+
+        stp_page = alloc_bootmem_pages(PAGE_SIZE);
+        rc = chsc_sstpc(stp_page, STP_OP_CTRL, 0x0000);
+        if (rc == 1)
+                set_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags);
+        else if (stp_online) {
+                printk(KERN_WARNING "Running on non STP capable machine.\n");
+                free_bootmem((unsigned long) stp_page, PAGE_SIZE);
+                stp_page = NULL;
+                stp_online = 0;
+        }
+}
+
+static int __init stp_init(void)
+{
+        if (test_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags) && stp_online)
+                schedule_work(&stp_work);
+        return 0;
+}
+
+arch_initcall(stp_init);
+
+/*
+ * STP timing alert. There are three causes:
+ * 1) timing status change
+ * 2) link availability change
+ * 3) time control parameter change
+ * In all three cases we are only interested in the clock source state.
+ * If a STP clock source is now available use it.
+ */
+static void stp_timing_alert(struct stp_irq_parm *intparm)
+{
+        if (intparm->tsc || intparm->lac || intparm->tcpc)
+                schedule_work(&stp_work);
+}
+
+/*
+ * STP sync check machine check. This is called when the timing state
+ * changes from the synchronized state to the unsynchronized state.
+ * After a STP sync check the clock is not in sync. The machine check
+ * is broadcasted to all cpus at the same time.
+ */
+void stp_sync_check(void)
+{
+        if (!test_bit(CLOCK_SYNC_STP, &clock_sync_flags))
+                return;
+        disable_sync_clock(NULL);
+        schedule_work(&stp_work);
+}
+
+/*
+ * STP island condition machine check. This is called when an attached
+ * server  attempts to communicate over an STP link and the servers
+ * have matching CTN ids and have a valid stratum-1 configuration
+ * but the configurations do not match.
+ */
+void stp_island_check(void)
+{
+        if (!test_bit(CLOCK_SYNC_STP, &clock_sync_flags))
+                return;
+        disable_sync_clock(NULL);
+        schedule_work(&stp_work);
+}
+
+/*
+ * STP tasklet. Check for the STP state and take over the clock
+ * synchronization if the STP clock source is usable.
+ */
+static void stp_work_fn(struct work_struct *work)
+{
+        struct clock_sync_data stp_sync;
+        unsigned long long old_clock, delta;
+        int rc;
+
+        if (!stp_online) {
+                chsc_sstpc(stp_page, STP_OP_CTRL, 0x0000);
+                return;
+        }
+
+        rc = chsc_sstpc(stp_page, STP_OP_CTRL, 0xb0e0);
+        if (rc)
+                return;
+
+        rc = chsc_sstpi(stp_page, &stp_info, sizeof(struct stp_sstpi));
+        if (rc || stp_info.c == 0)
+                return;
+
+        /*
+         * Catch all other cpus and make them wait until we have
+         * successfully synced the clock. smp_call_function will
+         * return after all other cpus are in clock_sync_cpu_start.
+         */
+        memset(&stp_sync, 0, sizeof(stp_sync));
+        preempt_disable();
+        smp_call_function(clock_sync_cpu_start, &stp_sync, 0, 0);
+        local_irq_disable();
+        enable_sync_clock();
+
+        set_bit(CLOCK_SYNC_STP, &clock_sync_flags);
+        if (test_and_clear_bit(CLOCK_SYNC_ETR, &clock_sync_flags))
+                schedule_work(&etr_work);
+
+        rc = 0;
+        if (stp_info.todoff[0] || stp_info.todoff[1] ||
+            stp_info.todoff[2] || stp_info.todoff[3] ||
+            stp_info.tmd != 2) {
+                old_clock = get_clock();
+                rc = chsc_sstpc(stp_page, STP_OP_SYNC, 0);
+                if (rc == 0) {
+                        delta = adjust_time(old_clock, get_clock(), 0);
+                        fixup_clock_comparator(delta);
+                        rc = chsc_sstpi(stp_page, &stp_info,
+                                        sizeof(struct stp_sstpi));
+                        if (rc == 0 && stp_info.tmd != 2)
+                                rc = -EAGAIN;
+                }
+        }
+        if (rc) {
+                disable_sync_clock(NULL);
+                stp_sync.in_sync = -EAGAIN;
+                clear_bit(CLOCK_SYNC_STP, &clock_sync_flags);
+                if (etr_port0_online || etr_port1_online)
+                        schedule_work(&etr_work);
+        } else
+                stp_sync.in_sync = 1;
+
+        local_irq_enable();
+        smp_call_function(clock_sync_cpu_end, NULL, 0, 0);
+        preempt_enable();
+}
+
+/*
+ * STP class sysfs interface functions
+ */
+static struct sysdev_class stp_sysclass = {
+        .name   = "stp",
+};
+
+static ssize_t stp_ctn_id_show(struct sysdev_class *class, char *buf)
+{
+        if (!stp_online)
+                return -ENODATA;
+        return sprintf(buf, "%016llx\n",
+                       *(unsigned long long *) stp_info.ctnid);
+}
+
+static SYSDEV_CLASS_ATTR(ctn_id, 0400, stp_ctn_id_show, NULL);
+
+static ssize_t stp_ctn_type_show(struct sysdev_class *class, char *buf)
+{
+        if (!stp_online)
+                return -ENODATA;
+        return sprintf(buf, "%i\n", stp_info.ctn);
+}
+
+static SYSDEV_CLASS_ATTR(ctn_type, 0400, stp_ctn_type_show, NULL);
+
+static ssize_t stp_dst_offset_show(struct sysdev_class *class, char *buf)
+{
+        if (!stp_online || !(stp_info.vbits & 0x2000))
+                return -ENODATA;
+        return sprintf(buf, "%i\n", (int)(s16) stp_info.dsto);
+}
+
+static SYSDEV_CLASS_ATTR(dst_offset, 0400, stp_dst_offset_show, NULL);
+
+static ssize_t stp_leap_seconds_show(struct sysdev_class *class, char *buf)
+{
+        if (!stp_online || !(stp_info.vbits & 0x8000))
+                return -ENODATA;
+        return sprintf(buf, "%i\n", (int)(s16) stp_info.leaps);
+}
+
+static SYSDEV_CLASS_ATTR(leap_seconds, 0400, stp_leap_seconds_show, NULL);
+
+static ssize_t stp_stratum_show(struct sysdev_class *class, char *buf)
+{
+        if (!stp_online)
+                return -ENODATA;
+        return sprintf(buf, "%i\n", (int)(s16) stp_info.stratum);
+}
+
+static SYSDEV_CLASS_ATTR(stratum, 0400, stp_stratum_show, NULL);
+
+static ssize_t stp_time_offset_show(struct sysdev_class *class, char *buf)
+{
+        if (!stp_online || !(stp_info.vbits & 0x0800))
+                return -ENODATA;
+        return sprintf(buf, "%i\n", (int) stp_info.tto);
+}
+
+static SYSDEV_CLASS_ATTR(time_offset, 0400, stp_time_offset_show, NULL);
+
+static ssize_t stp_time_zone_offset_show(struct sysdev_class *class, char *buf)
+{
+        if (!stp_online || !(stp_info.vbits & 0x4000))
+                return -ENODATA;
+        return sprintf(buf, "%i\n", (int)(s16) stp_info.tzo);
+}
+
+static SYSDEV_CLASS_ATTR(time_zone_offset, 0400,
+                         stp_time_zone_offset_show, NULL);
+
+static ssize_t stp_timing_mode_show(struct sysdev_class *class, char *buf)
+{
+        if (!stp_online)
+                return -ENODATA;
+        return sprintf(buf, "%i\n", stp_info.tmd);
+}
+
+static SYSDEV_CLASS_ATTR(timing_mode, 0400, stp_timing_mode_show, NULL);
+
+static ssize_t stp_timing_state_show(struct sysdev_class *class, char *buf)
+{
+        if (!stp_online)
+                return -ENODATA;
+        return sprintf(buf, "%i\n", stp_info.tst);
+}
+
+static SYSDEV_CLASS_ATTR(timing_state, 0400, stp_timing_state_show, NULL);
+
+static ssize_t stp_online_show(struct sysdev_class *class, char *buf)
+{
+        return sprintf(buf, "%i\n", stp_online);
+}
+
+static ssize_t stp_online_store(struct sysdev_class *class,
+                                const char *buf, size_t count)
+{
+        unsigned int value;
+
+        value = simple_strtoul(buf, NULL, 0);
+        if (value != 0 && value != 1)
+                return -EINVAL;
+        if (!test_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags))
+                return -EOPNOTSUPP;
+        stp_online = value;
+        schedule_work(&stp_work);
+        return count;
+}
+
+/*
+ * Can't use SYSDEV_CLASS_ATTR because the attribute should be named
+ * stp/online but attr_online already exists in this file ..
+ */
+static struct sysdev_class_attribute attr_stp_online = {
+        .attr = { .name = "online", .mode = 0600 },
+        .show   = stp_online_show,
+        .store  = stp_online_store,
+};
+
+static struct sysdev_class_attribute *stp_attributes[] = {
+        &attr_ctn_id,
+        &attr_ctn_type,
+        &attr_dst_offset,
+        &attr_leap_seconds,
+        &attr_stp_online,
+        &attr_stratum,
+        &attr_time_offset,
+        &attr_time_zone_offset,
+        &attr_timing_mode,
+        &attr_timing_state,
+        NULL
+};
+
+static int __init stp_init_sysfs(void)
+{
+        struct sysdev_class_attribute **attr;
+        int rc;
+
+        rc = sysdev_class_register(&stp_sysclass);
+        if (rc)
+                goto out;
+        for (attr = stp_attributes; *attr; attr++) {
+                rc = sysdev_class_create_file(&stp_sysclass, *attr);
+                if (rc)
+                        goto out_unreg;
+        }
+        return 0;
+out_unreg:
+        for (; attr >= stp_attributes; attr--)
+                sysdev_class_remove_file(&stp_sysclass, *attr);
+        sysdev_class_unregister(&stp_sysclass);
+out:
+        return rc;
+}
+
+device_initcall(stp_init_sysfs);
diff --git a/arch/s390/kernel/topology.c b/arch/s390/kernel/topology.c
index 661a07217057..212d618b0095 100644
--- a/arch/s390/kernel/topology.c
+++ b/arch/s390/kernel/topology.c
@@ -313,8 +313,6 @@ void __init s390_init_cpu_topology(void)
                 machine_has_topology_irq = 1;
 
         tl_info = alloc_bootmem_pages(PAGE_SIZE);
-        if (!tl_info)
-                goto error;
         info = tl_info;
         stsi(info, 15, 1, 2);
 
diff --git a/arch/s390/kernel/vmlinux.lds.S b/arch/s390/kernel/vmlinux.lds.S
index b4607155e8d0..76c1e60c92f3 100644
--- a/arch/s390/kernel/vmlinux.lds.S
+++ b/arch/s390/kernel/vmlinux.lds.S
@@ -40,7 +40,6 @@ SECTIONS
         _etext = .;             /* End of text section */
 
         NOTES :text :note
-        BUG_TABLE :text
 
         RODATA
 
diff --git a/arch/s390/kernel/vtime.c b/arch/s390/kernel/vtime.c
index ca90ee3f930e..0fa5dc5d68e1 100644
--- a/arch/s390/kernel/vtime.c
+++ b/arch/s390/kernel/vtime.c
@@ -136,7 +136,7 @@ static inline void set_vtimer(__u64 expires)
 }
 #endif
 
-static void start_cpu_timer(void)
+void vtime_start_cpu_timer(void)
 {
         struct vtimer_queue *vt_list;
 
@@ -150,7 +150,7 @@ static void start_cpu_timer(void)
                 set_vtimer(vt_list->idle);
 }
 
-static void stop_cpu_timer(void)
+void vtime_stop_cpu_timer(void)
 {
         struct vtimer_queue *vt_list;
 
@@ -318,8 +318,7 @@ static void internal_add_vtimer(struct vtimer_list *timer)
         vt_list = &per_cpu(virt_cpu_timer, timer->cpu);
         spin_lock_irqsave(&vt_list->lock, flags);
 
-        if (timer->cpu != smp_processor_id())
-                printk("internal_add_vtimer: BUG, running on wrong CPU");
+        BUG_ON(timer->cpu != smp_processor_id());
 
         /* if list is empty we only have to set the timer */
         if (list_empty(&vt_list->list)) {
@@ -353,25 +352,12 @@ static void internal_add_vtimer(struct vtimer_list *timer)
         put_cpu();
 }
 
-static inline int prepare_vtimer(struct vtimer_list *timer)
+static inline void prepare_vtimer(struct vtimer_list *timer)
 {
-        if (!timer->function) {
-                printk("add_virt_timer: uninitialized timer\n");
-                return -EINVAL;
-        }
-
-        if (!timer->expires || timer->expires > VTIMER_MAX_SLICE) {
-                printk("add_virt_timer: invalid timer expire value!\n");
-                return -EINVAL;
-        }
-
-        if (vtimer_pending(timer)) {
-                printk("add_virt_timer: timer pending\n");
-                return -EBUSY;
-        }
-
+        BUG_ON(!timer->function);
+        BUG_ON(!timer->expires || timer->expires > VTIMER_MAX_SLICE);
+        BUG_ON(vtimer_pending(timer));
         timer->cpu = get_cpu();
-        return 0;
 }
 
 /*
@@ -382,10 +368,7 @@ void add_virt_timer(void *new)
         struct vtimer_list *timer;
 
         timer = (struct vtimer_list *)new;
-
-        if (prepare_vtimer(timer) < 0)
-                return;
-
+        prepare_vtimer(timer);
         timer->interval = 0;
         internal_add_vtimer(timer);
 }
@@ -399,10 +382,7 @@ void add_virt_timer_periodic(void *new)
         struct vtimer_list *timer;
 
         timer = (struct vtimer_list *)new;
-
-        if (prepare_vtimer(timer) < 0)
-                return;
-
+        prepare_vtimer(timer);
         timer->interval = timer->expires;
         internal_add_vtimer(timer);
 }
@@ -423,15 +403,8 @@ int mod_virt_timer(struct vtimer_list *timer, __u64 expires)
         unsigned long flags;
         int cpu;
 
-        if (!timer->function) {
-                printk("mod_virt_timer: uninitialized timer\n");
-                return  -EINVAL;
-        }
-
-        if (!expires || expires > VTIMER_MAX_SLICE) {
-                printk("mod_virt_timer: invalid expire range\n");
-                return -EINVAL;
-        }
+        BUG_ON(!timer->function);
+        BUG_ON(!expires || expires > VTIMER_MAX_SLICE);
 
         /*
          * This is a common optimization triggered by the
@@ -444,6 +417,9 @@ int mod_virt_timer(struct vtimer_list *timer, __u64 expires)
         cpu = get_cpu();
         vt_list = &per_cpu(virt_cpu_timer, cpu);
 
+        /* check if we run on the right CPU */
+        BUG_ON(timer->cpu != cpu);
+
         /* disable interrupts before test if timer is pending */
         spin_lock_irqsave(&vt_list->lock, flags);
 
@@ -458,14 +434,6 @@ int mod_virt_timer(struct vtimer_list *timer, __u64 expires)
                 return 0;
         }
 
-        /* check if we run on the right CPU */
-        if (timer->cpu != cpu) {
-                printk("mod_virt_timer: running on wrong CPU, check your code\n");
-                spin_unlock_irqrestore(&vt_list->lock, flags);
-                put_cpu();
-                return -EINVAL;
-        }
-
         list_del_init(&timer->entry);
         timer->expires = expires;
 
@@ -536,24 +504,6 @@ void init_cpu_vtimer(void)
 
 }
 
-static int vtimer_idle_notify(struct notifier_block *self,
-                              unsigned long action, void *hcpu)
-{
-        switch (action) {
-        case S390_CPU_IDLE:
-                stop_cpu_timer();
-                break;
-        case S390_CPU_NOT_IDLE:
-                start_cpu_timer();
-                break;
-        }
-        return NOTIFY_OK;
-}
-
-static struct notifier_block vtimer_idle_nb = {
-        .notifier_call = vtimer_idle_notify,
-};
-
 void __init vtime_init(void)
 {
         /* request the cpu timer external interrupt */
@@ -561,9 +511,6 @@ void __init vtime_init(void)
                                               &ext_int_info_timer) != 0)
                 panic("Couldn't request external interrupt 0x1005");
 
-        if (register_idle_notifier(&vtimer_idle_nb))
-                panic("Couldn't register idle notifier");
-
         /* Enable cpu timer interrupts on the boot cpu. */
         init_cpu_vtimer();
 }
diff --git a/arch/s390/mm/init.c b/arch/s390/mm/init.c
index 05598649b326..388cc7420055 100644
--- a/arch/s390/mm/init.c
+++ b/arch/s390/mm/init.c
@@ -202,3 +202,22 @@ void free_initrd_mem(unsigned long start, unsigned long end)
         }
 }
 #endif
+
+#ifdef CONFIG_MEMORY_HOTPLUG
+int arch_add_memory(int nid, u64 start, u64 size)
+{
+        struct pglist_data *pgdat;
+        struct zone *zone;
+        int rc;
+
+        pgdat = NODE_DATA(nid);
+        zone = pgdat->node_zones + ZONE_NORMAL;
+        rc = vmem_add_mapping(start, size);
+        if (rc)
+                return rc;
+        rc = __add_pages(zone, PFN_DOWN(start), PFN_DOWN(size));
+        if (rc)
+                vmem_remove_mapping(start, size);
+        return rc;
+}
+#endif /* CONFIG_MEMORY_HOTPLUG */
diff --git a/arch/sh/boards/landisk/gio.c b/arch/sh/boards/landisk/gio.c
index 17025080db35..0c15b0a50b99 100644
--- a/arch/sh/boards/landisk/gio.c
+++ b/arch/sh/boards/landisk/gio.c
@@ -14,6 +14,7 @@
  */
 #include <linux/module.h>
 #include <linux/init.h>
+#include <linux/smp_lock.h>
 #include <linux/kdev_t.h>
 #include <linux/cdev.h>
 #include <linux/fs.h>
@@ -32,17 +33,20 @@ static int openCnt;
 static int gio_open(struct inode *inode, struct file *filp)
 {
         int minor;
+        int ret = -ENOENT;
 
+        lock_kernel();
         minor = MINOR(inode->i_rdev);
         if (minor < DEVCOUNT) {
                 if (openCnt > 0) {
-                        return -EALREADY;
+                        ret = -EALREADY;
                 } else {
                         openCnt++;
-                        return 0;
+                        ret = 0;
                 }
         }
-        return -ENOENT;
+        unlock_kernel();
+        return ret;
 }
 
 static int gio_close(struct inode *inode, struct file *filp)
diff --git a/arch/sh/configs/landisk_defconfig b/arch/sh/configs/landisk_defconfig
index f52db125432f..38f934ab50c7 100644
--- a/arch/sh/configs/landisk_defconfig
+++ b/arch/sh/configs/landisk_defconfig
@@ -226,7 +226,6 @@ CONFIG_CPU_HAS_PTEA=y
 #
 CONFIG_SH_TMU=y
 CONFIG_SH_TIMER_IRQ=16
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_SH_PCLK_FREQ=33333333
 
 #
diff --git a/arch/sh/configs/lboxre2_defconfig b/arch/sh/configs/lboxre2_defconfig
index 9fa66d92a4e7..b68b6cdbb78f 100644
--- a/arch/sh/configs/lboxre2_defconfig
+++ b/arch/sh/configs/lboxre2_defconfig
@@ -231,7 +231,6 @@ CONFIG_CPU_HAS_PTEA=y
 #
 CONFIG_SH_TMU=y
 CONFIG_SH_TIMER_IRQ=16
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_SH_PCLK_FREQ=40000000
 
 #
diff --git a/arch/sh/configs/se7705_defconfig b/arch/sh/configs/se7705_defconfig
index 84717d854867..490dcbc2ce33 100644
--- a/arch/sh/configs/se7705_defconfig
+++ b/arch/sh/configs/se7705_defconfig
@@ -239,7 +239,6 @@ CONFIG_CPU_HAS_SR_RB=y
 #
 CONFIG_SH_TMU=y
 CONFIG_SH_TIMER_IRQ=16
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_SH_PCLK_FREQ=33333333
 
 #
diff --git a/arch/sh/configs/se7712_defconfig b/arch/sh/configs/se7712_defconfig
index 240a1cef69aa..2dd83af988f0 100644
--- a/arch/sh/configs/se7712_defconfig
+++ b/arch/sh/configs/se7712_defconfig
@@ -236,7 +236,6 @@ CONFIG_CPU_HAS_SR_RB=y
 #
 CONFIG_SH_TMU=y
 CONFIG_SH_TIMER_IRQ=16
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_SH_PCLK_FREQ=66666666
 
 #
diff --git a/arch/sh/configs/se7750_defconfig b/arch/sh/configs/se7750_defconfig
index c60b6fd4fc42..167786f9a9bd 100644
--- a/arch/sh/configs/se7750_defconfig
+++ b/arch/sh/configs/se7750_defconfig
@@ -235,7 +235,6 @@ CONFIG_CPU_HAS_PTEA=y
 #
 CONFIG_SH_TMU=y
 CONFIG_SH_TIMER_IRQ=16
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_SH_PCLK_FREQ=33333333
 
 #
diff --git a/arch/sh/kernel/vmlinux_32.lds.S b/arch/sh/kernel/vmlinux_32.lds.S
index c7113786ecd4..7b4b82bd1156 100644
--- a/arch/sh/kernel/vmlinux_32.lds.S
+++ b/arch/sh/kernel/vmlinux_32.lds.S
@@ -44,7 +44,6 @@ SECTIONS
 
         _etext = .;                     /* End of text section */
 
-        BUG_TABLE
         NOTES
         RO_DATA(PAGE_SIZE)
 
diff --git a/arch/sh/kernel/vmlinux_64.lds.S b/arch/sh/kernel/vmlinux_64.lds.S
index d1e177009a41..33fa46451406 100644
--- a/arch/sh/kernel/vmlinux_64.lds.S
+++ b/arch/sh/kernel/vmlinux_64.lds.S
@@ -65,7 +65,6 @@ SECTIONS
 
         _etext = .;                     /* End of text section */
 
-        BUG_TABLE
         NOTES 
         RO_DATA(PAGE_SIZE)
 
diff --git a/arch/sparc/kernel/apc.c b/arch/sparc/kernel/apc.c
index d06a405ca718..6707422c9847 100644
--- a/arch/sparc/kernel/apc.c
+++ b/arch/sparc/kernel/apc.c
@@ -10,6 +10,7 @@
 #include <linux/errno.h>
 #include <linux/init.h>
 #include <linux/miscdevice.h>
+#include <linux/smp_lock.h>
 #include <linux/pm.h>
 
 #include <asm/io.h>
@@ -75,6 +76,7 @@ static inline void apc_free(void)
 
 static int apc_open(struct inode *inode, struct file *f)
 {
+        cycle_kernel_lock();
         return 0;
 }
 
diff --git a/arch/sparc64/Kconfig b/arch/sparc64/Kconfig
index eb36f3b746b8..fca9246470b1 100644
--- a/arch/sparc64/Kconfig
+++ b/arch/sparc64/Kconfig
@@ -11,6 +11,8 @@ config SPARC
 config SPARC64
         bool
         default y
+        select HAVE_DYNAMIC_FTRACE
+        select HAVE_FTRACE
         select HAVE_IDE
         select HAVE_LMB
         select HAVE_ARCH_KGDB
diff --git a/arch/sparc64/Kconfig.debug b/arch/sparc64/Kconfig.debug
index 6a4d28a4076d..d6d32d178fc8 100644
--- a/arch/sparc64/Kconfig.debug
+++ b/arch/sparc64/Kconfig.debug
@@ -33,7 +33,7 @@ config DEBUG_PAGEALLOC
 
 config MCOUNT
         bool
-        depends on STACK_DEBUG
+        depends on STACK_DEBUG || FTRACE
         default y
 
 config FRAME_POINTER
diff --git a/arch/sparc64/kernel/Makefile b/arch/sparc64/kernel/Makefile
index ec4f5ebb1ca6..418b5782096e 100644
--- a/arch/sparc64/kernel/Makefile
+++ b/arch/sparc64/kernel/Makefile
@@ -14,6 +14,7 @@ obj-y		:= process.o setup.o cpu.o idprom.o \
                    power.o sbus.o sparc64_ksyms.o chmc.o \
                    visemul.o prom.o of_device.o hvapi.o sstate.o mdesc.o
 
+obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o
 obj-$(CONFIG_STACKTRACE) += stacktrace.o
 obj-$(CONFIG_PCI)        += ebus.o pci_common.o \
                             pci_psycho.o pci_sabre.o pci_schizo.o \
diff --git a/arch/sparc64/kernel/ftrace.c b/arch/sparc64/kernel/ftrace.c
new file mode 100644
index 000000000000..4298d0aee713
--- /dev/null
+++ b/arch/sparc64/kernel/ftrace.c
@@ -0,0 +1,94 @@
+#include <linux/spinlock.h>
+#include <linux/hardirq.h>
+#include <linux/ftrace.h>
+#include <linux/percpu.h>
+#include <linux/init.h>
+#include <linux/list.h>
+
+#include <asm/ftrace.h>
+
+static const u32 ftrace_nop = 0x01000000;
+
+notrace unsigned char *ftrace_nop_replace(void)
+{
+        return (char *)&ftrace_nop;
+}
+
+notrace unsigned char *ftrace_call_replace(unsigned long ip, unsigned long addr)
+{
+        static u32 call;
+        s32 off;
+
+        off = ((s32)addr - (s32)ip);
+        call = 0x40000000 | ((u32)off >> 2);
+
+        return (unsigned char *) &call;
+}
+
+notrace int
+ftrace_modify_code(unsigned long ip, unsigned char *old_code,
+                   unsigned char *new_code)
+{
+        u32 old = *(u32 *)old_code;
+        u32 new = *(u32 *)new_code;
+        u32 replaced;
+        int faulted;
+
+        __asm__ __volatile__(
+        "1:     cas     [%[ip]], %[old], %[new]\n"
+        "       flush   %[ip]\n"
+        "       mov     0, %[faulted]\n"
+        "2:\n"
+        "       .section .fixup,#alloc,#execinstr\n"
+        "       .align  4\n"
+        "3:     sethi   %%hi(2b), %[faulted]\n"
+        "       jmpl    %[faulted] + %%lo(2b), %%g0\n"
+        "        mov    1, %[faulted]\n"
+        "       .previous\n"
+        "       .section __ex_table,\"a\"\n"
+        "       .align  4\n"
+        "       .word   1b, 3b\n"
+        "       .previous\n"
+        : "=r" (replaced), [faulted] "=r" (faulted)
+        : [new] "0" (new), [old] "r" (old), [ip] "r" (ip)
+        : "memory");
+
+        if (replaced != old && replaced != new)
+                faulted = 2;
+
+        return faulted;
+}
+
+notrace int ftrace_update_ftrace_func(ftrace_func_t func)
+{
+        unsigned long ip = (unsigned long)(&ftrace_call);
+        unsigned char old[MCOUNT_INSN_SIZE], *new;
+
+        memcpy(old, &ftrace_call, MCOUNT_INSN_SIZE);
+        new = ftrace_call_replace(ip, (unsigned long)func);
+        return ftrace_modify_code(ip, old, new);
+}
+
+notrace int ftrace_mcount_set(unsigned long *data)
+{
+        unsigned long ip = (long)(&mcount_call);
+        unsigned long *addr = data;
+        unsigned char old[MCOUNT_INSN_SIZE], *new;
+
+        /*
+         * Replace the mcount stub with a pointer to the
+         * ip recorder function.
+         */
+        memcpy(old, &mcount_call, MCOUNT_INSN_SIZE);
+        new = ftrace_call_replace(ip, *addr);
+        *addr = ftrace_modify_code(ip, old, new);
+
+        return 0;
+}
+
+
+int __init ftrace_dyn_arch_init(void *data)
+{
+        ftrace_mcount_set(data);
+        return 0;
+}
diff --git a/arch/sparc64/kernel/sparc64_ksyms.c b/arch/sparc64/kernel/sparc64_ksyms.c
index 8ac0b99f2c55..49d3ea50c247 100644
--- a/arch/sparc64/kernel/sparc64_ksyms.c
+++ b/arch/sparc64/kernel/sparc64_ksyms.c
@@ -53,6 +53,7 @@
 #include <asm/ns87303.h>
 #include <asm/timer.h>
 #include <asm/cpudata.h>
+#include <asm/ftrace.h>
 
 struct poll {
         int fd;
@@ -111,8 +112,7 @@ EXPORT_SYMBOL(__write_trylock);
 EXPORT_SYMBOL(smp_call_function);
 #endif /* CONFIG_SMP */
 
-#if defined(CONFIG_MCOUNT)
-extern void _mcount(void);
+#ifdef CONFIG_MCOUNT
 EXPORT_SYMBOL(_mcount);
 #endif
 
diff --git a/arch/sparc64/kernel/time.c b/arch/sparc64/kernel/time.c
index e5d238970c7e..bedc4c159b1c 100644
--- a/arch/sparc64/kernel/time.c
+++ b/arch/sparc64/kernel/time.c
@@ -11,6 +11,7 @@
 #include <linux/errno.h>
 #include <linux/module.h>
 #include <linux/sched.h>
+#include <linux/smp_lock.h>
 #include <linux/kernel.h>
 #include <linux/param.h>
 #include <linux/string.h>
@@ -1659,10 +1660,14 @@ static int mini_rtc_ioctl(struct inode *inode, struct file *file,
 
 static int mini_rtc_open(struct inode *inode, struct file *file)
 {
-        if (mini_rtc_status & RTC_IS_OPEN)
+        lock_kernel();
+        if (mini_rtc_status & RTC_IS_OPEN) {
+                unlock_kernel();
                 return -EBUSY;
+        }
 
         mini_rtc_status |= RTC_IS_OPEN;
+        unlock_kernel();
 
         return 0;
 }
diff --git a/arch/sparc64/lib/mcount.S b/arch/sparc64/lib/mcount.S
index 9e4534b485c7..7735a7a60533 100644
--- a/arch/sparc64/lib/mcount.S
+++ b/arch/sparc64/lib/mcount.S
@@ -28,10 +28,13 @@ ovstack:
         .skip           OVSTACKSIZE
 #endif
         .text
-        .align 32
-        .globl mcount, _mcount
-mcount:
+        .align          32
+        .globl          _mcount
+        .type           _mcount,#function
+        .globl          mcount
+        .type           mcount,#function
 _mcount:
+mcount:
 #ifdef CONFIG_STACK_DEBUG
         /*
          * Check whether %sp is dangerously low.
@@ -55,6 +58,53 @@ _mcount:
          or             %g3, %lo(panicstring), %o0
         call            prom_halt
          nop
+1:
+#endif
+#ifdef CONFIG_FTRACE
+#ifdef CONFIG_DYNAMIC_FTRACE
+        mov             %o7, %o0
+        .globl          mcount_call
+mcount_call:
+        call            ftrace_stub
+         mov            %o0, %o7
+#else
+        sethi           %hi(ftrace_trace_function), %g1
+        sethi           %hi(ftrace_stub), %g2
+        ldx             [%g1 + %lo(ftrace_trace_function)], %g1
+        or              %g2, %lo(ftrace_stub), %g2
+        cmp             %g1, %g2
+        be,pn           %icc, 1f
+         mov            %i7, %o1
+        jmpl            %g1, %g0
+         mov            %o7, %o0
+        /* not reached */
+1:
 #endif
-1:      retl
+#endif
+        retl
          nop
+        .size           _mcount,.-_mcount
+        .size           mcount,.-mcount
+
+#ifdef CONFIG_FTRACE
+        .globl          ftrace_stub
+        .type           ftrace_stub,#function
+ftrace_stub:
+        retl
+         nop
+        .size           ftrace_stub,.-ftrace_stub
+#ifdef CONFIG_DYNAMIC_FTRACE
+        .globl          ftrace_caller
+        .type           ftrace_caller,#function
+ftrace_caller:
+        mov             %i7, %o1
+        mov             %o7, %o0
+        .globl          ftrace_call
+ftrace_call:
+        call            ftrace_stub
+         mov            %o0, %o7
+        retl
+         nop
+        .size           ftrace_caller,.-ftrace_caller
+#endif
+#endif
diff --git a/arch/um/drivers/harddog_kern.c b/arch/um/drivers/harddog_kern.c
index a9ad4bd6d953..d332503fa1be 100644
--- a/arch/um/drivers/harddog_kern.c
+++ b/arch/um/drivers/harddog_kern.c
@@ -66,6 +66,7 @@ static int harddog_open(struct inode *inode, struct file *file)
         int err = -EBUSY;
         char *sock = NULL;
 
+        lock_kernel();
         spin_lock(&lock);
         if(timer_alive)
                 goto err;
@@ -82,9 +83,11 @@ static int harddog_open(struct inode *inode, struct file *file)
 
         timer_alive = 1;
         spin_unlock(&lock);
+        unlock_kernel();
         return nonseekable_open(inode, file);
 err:
         spin_unlock(&lock);
+        unlock_kernel();
         return err;
 }
 
diff --git a/arch/um/drivers/mmapper_kern.c b/arch/um/drivers/mmapper_kern.c
index 67b2f55a602f..eb240323c40a 100644
--- a/arch/um/drivers/mmapper_kern.c
+++ b/arch/um/drivers/mmapper_kern.c
@@ -16,6 +16,7 @@
 #include <linux/miscdevice.h>
 #include <linux/module.h>
 #include <linux/mm.h>
+#include <linux/smp_lock.h>
 #include <asm/uaccess.h>
 #include "mem_user.h"
 
@@ -77,6 +78,7 @@ out:
 
 static int mmapper_open(struct inode *inode, struct file *file)
 {
+        cycle_kernel_lock();
         return 0;
 }
 
diff --git a/arch/um/drivers/random.c b/arch/um/drivers/random.c
index 4949044773ba..6eabb7022a2d 100644
--- a/arch/um/drivers/random.c
+++ b/arch/um/drivers/random.c
@@ -7,6 +7,7 @@
  * of the GNU General Public License, incorporated herein by reference.
  */
 #include <linux/sched.h>
+#include <linux/smp_lock.h>
 #include <linux/module.h>
 #include <linux/fs.h>
 #include <linux/interrupt.h>
@@ -33,6 +34,8 @@ static DECLARE_WAIT_QUEUE_HEAD(host_read_wait);
 
 static int rng_dev_open (struct inode *inode, struct file *filp)
 {
+        cycle_kernel_lock();
+
         /* enforce read-only access to this chrdev */
         if ((filp->f_mode & FMODE_READ) == 0)
                 return -EINVAL;
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index bf07b6f50fa1..6958d6bcaf70 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -23,6 +23,8 @@ config X86
         select HAVE_OPROFILE
         select HAVE_KPROBES
         select HAVE_KRETPROBES
+        select HAVE_DYNAMIC_FTRACE
+        select HAVE_FTRACE
         select HAVE_KVM if ((X86_32 && !X86_VOYAGER && !X86_VISWS && !X86_NUMAQ) || X86_64)
         select HAVE_ARCH_KGDB if !X86_VOYAGER
 
@@ -121,7 +123,7 @@ config ARCH_HAS_CACHE_LINE_SIZE
         def_bool y
 
 config HAVE_SETUP_PER_CPU_AREA
-        def_bool X86_64 || (X86_SMP && !X86_VOYAGER)
+        def_bool X86_64_SMP || (X86_SMP && !X86_VOYAGER)
 
 config HAVE_CPUMASK_OF_CPU_MAP
         def_bool X86_64_SMP
@@ -181,12 +183,12 @@ config X86_64_SMP
 config X86_HT
         bool
         depends on SMP
-        depends on (X86_32 && !(X86_VISWS || X86_VOYAGER)) || X86_64
+        depends on (X86_32 && !X86_VOYAGER) || X86_64
         default y
 
 config X86_BIOS_REBOOT
         bool
-        depends on !X86_VISWS && !X86_VOYAGER
+        depends on !X86_VOYAGER
         default y
 
 config X86_TRAMPOLINE
@@ -230,6 +232,26 @@ config SMP
 
           If you don't know what to do here, say N.
 
+config X86_FIND_SMP_CONFIG
+        def_bool y
+        depends on X86_MPPARSE || X86_VOYAGER
+
+if ACPI
+config X86_MPPARSE
+        def_bool y
+        bool "Enable MPS table"
+        depends on X86_LOCAL_APIC
+        help
+          For old smp systems that do not have proper acpi support. Newer systems
+          (esp with 64bit cpus) with acpi support, MADT and DSDT will override it
+endif
+
+if !ACPI
+config X86_MPPARSE
+        def_bool y
+        depends on X86_LOCAL_APIC
+endif
+
 choice
         prompt "Subarchitecture Type"
         default X86_PC
@@ -251,7 +273,7 @@ config X86_ELAN
 
 config X86_VOYAGER
         bool "Voyager (NCR)"
-        depends on X86_32 && (SMP || BROKEN)
+        depends on X86_32 && (SMP || BROKEN) && !PCI
         help
           Voyager is an MCA-based 32-way capable SMP architecture proprietary
           to NCR Corp.  Machine classes 345x/35xx/4100/51xx are Voyager-based.
@@ -261,16 +283,27 @@ config X86_VOYAGER
           If you do not specifically know you have a Voyager based machine,
           say N here, otherwise the kernel you build will not be bootable.
 
+config X86_GENERICARCH
+       bool "Generic architecture"
+        depends on X86_32
+       help
+          This option compiles in the NUMAQ, Summit, bigsmp, ES7000, default
+          subarchitectures.  It is intended for a generic binary kernel.
+          if you select them all, kernel will probe it one by one. and will
+          fallback to default.
+
+if X86_GENERICARCH
+
 config X86_NUMAQ
         bool "NUMAQ (IBM/Sequent)"
-        depends on SMP && X86_32
+        depends on SMP && X86_32 && PCI && X86_MPPARSE
         select NUMA
         help
-          This option is used for getting Linux to run on a (IBM/Sequent) NUMA
-          multiquad box. This changes the way that processors are bootstrapped,
-          and uses Clustered Logical APIC addressing mode instead of Flat Logical.
-          You will need a new lynxer.elf file to flash your firmware with - send
-          email to <Martin.Bligh@us.ibm.com>.
+          This option is used for getting Linux to run on a NUMAQ (IBM/Sequent)
+          NUMA multiquad box. This changes the way that processors are
+          bootstrapped, and uses Clustered Logical APIC addressing mode instead
+          of Flat Logical.  You will need a new lynxer.elf file to flash your
+          firmware with - send email to <Martin.Bligh@us.ibm.com>.
 
 config X86_SUMMIT
         bool "Summit/EXA (IBM x440)"
@@ -279,46 +312,21 @@ config X86_SUMMIT
           This option is needed for IBM systems that use the Summit/EXA chipset.
           In particular, it is needed for the x440.
 
-          If you don't have one of these computers, you should say N here.
-          If you want to build a NUMA kernel, you must select ACPI.
+config X86_ES7000
+        bool "Support for Unisys ES7000 IA32 series"
+        depends on X86_32 && SMP
+        help
+          Support for Unisys ES7000 systems.  Say 'Y' here if this kernel is
+          supposed to run on an IA32-based Unisys ES7000 system.
 
 config X86_BIGSMP
-        bool "Support for other sub-arch SMP systems with more than 8 CPUs"
+        bool "Support for big SMP systems with more than 8 CPUs"
         depends on X86_32 && SMP
         help
           This option is needed for the systems that have more than 8 CPUs
           and if the system is not of any sub-arch type above.
 
-          If you don't have such a system, you should say N here.
-
-config X86_VISWS
-        bool "SGI 320/540 (Visual Workstation)"
-        depends on X86_32
-        help
-          The SGI Visual Workstation series is an IA32-based workstation
-          based on SGI systems chips with some legacy PC hardware attached.
-
-          Say Y here to create a kernel to run on the SGI 320 or 540.
-
-          A kernel compiled for the Visual Workstation will not run on PCs
-          and vice versa. See <file:Documentation/sgi-visws.txt> for details.
-
-config X86_GENERICARCH
-       bool "Generic architecture (Summit, bigsmp, ES7000, default)"
-        depends on X86_32
-       help
-          This option compiles in the Summit, bigsmp, ES7000, default subarchitectures.
-          It is intended for a generic binary kernel.
-          If you want a NUMA kernel, select ACPI.   We need SRAT for NUMA.
-
-config X86_ES7000
-        bool "Support for Unisys ES7000 IA32 series"
-        depends on X86_32 && SMP
-        help
-          Support for Unisys ES7000 systems.  Say 'Y' here if this kernel is
-          supposed to run on an IA32-based Unisys ES7000 system.
-          Only choose this option if you have such a system, otherwise you
-          should say N here.
+endif
 
 config X86_RDC321X
         bool "RDC R-321x SoC"
@@ -337,7 +345,7 @@ config X86_RDC321X
 config X86_VSMP
         bool "Support for ScaleMP vSMP"
         select PARAVIRT
-        depends on X86_64
+        depends on X86_64 && PCI
         help
           Support for ScaleMP vSMP systems.  Say 'Y' here if this kernel is
           supposed to run on these EM64T-based machines.  Only choose this option
@@ -345,6 +353,18 @@ config X86_VSMP
 
 endchoice
 
+config X86_VISWS
+        bool "SGI 320/540 (Visual Workstation)"
+        depends on X86_32 && PCI && !X86_VOYAGER && X86_MPPARSE && PCI_GODIRECT
+        help
+          The SGI Visual Workstation series is an IA32-based workstation
+          based on SGI systems chips with some legacy PC hardware attached.
+
+          Say Y here to create a kernel to run on the SGI 320 or 540.
+
+          A kernel compiled for the Visual Workstation will run on general
+          PCs as well. See <file:Documentation/sgi-visws.txt> for details.
+
 config SCHED_NO_NO_OMIT_FRAME_POINTER
         def_bool y
         prompt "Single-depth WCHAN output"
@@ -373,7 +393,7 @@ config VMI
         bool "VMI Guest support"
         select PARAVIRT
         depends on X86_32
-        depends on !(X86_VISWS || X86_VOYAGER)
+        depends on !X86_VOYAGER
         help
           VMI provides a paravirtualized interface to the VMware ESX server
           (it could be used by other hypervisors in theory too, but is not
@@ -384,7 +404,7 @@ config KVM_CLOCK
         bool "KVM paravirtualized clock"
         select PARAVIRT
         select PARAVIRT_CLOCK
-        depends on !(X86_VISWS || X86_VOYAGER)
+        depends on !X86_VOYAGER
         help
           Turning on this option will allow you to run a paravirtualized clock
           when running over the KVM hypervisor. Instead of relying on a PIT
@@ -395,7 +415,7 @@ config KVM_CLOCK
 config KVM_GUEST
         bool "KVM Guest support"
         select PARAVIRT
-        depends on !(X86_VISWS || X86_VOYAGER)
+        depends on !X86_VOYAGER
         help
          This option enables various optimizations for running under the KVM
          hypervisor.
@@ -404,7 +424,7 @@ source "arch/x86/lguest/Kconfig"
 
 config PARAVIRT
         bool "Enable paravirtualization code"
-        depends on !(X86_VISWS || X86_VOYAGER)
+        depends on !X86_VOYAGER
         help
           This changes the kernel so it can modify itself when it is run
           under a hypervisor, potentially improving performance significantly
@@ -417,51 +437,33 @@ config PARAVIRT_CLOCK
 
 endif
 
-config MEMTEST_BOOTPARAM
-        bool "Memtest boot parameter"
+config PARAVIRT_DEBUG
+       bool "paravirt-ops debugging"
+       depends on PARAVIRT && DEBUG_KERNEL
+       help
+         Enable to debug paravirt_ops internals.  Specifically, BUG if
+         a paravirt_op is missing when it is called.
+
+config MEMTEST
+        bool "Memtest"
         depends on X86_64
         default y
         help
           This option adds a kernel parameter 'memtest', which allows memtest
-          to be disabled at boot.  If this option is selected, memtest
-          functionality can be disabled with memtest=0 on the kernel
-          command line.  The purpose of this option is to allow a single
-          kernel image to be distributed with memtest built in, but not
-          necessarily enabled.
-
+          to be set.
+                memtest=0, mean disabled; -- default
+                memtest=1, mean do 1 test pattern;
+                ...
+                memtest=4, mean do 4 test patterns.
           If you are unsure how to answer this question, answer Y.
 
-config MEMTEST_BOOTPARAM_VALUE
-        int "Memtest boot parameter default value (0-4)"
-        depends on MEMTEST_BOOTPARAM
-        range 0 4
-        default 0
-        help
-          This option sets the default value for the kernel parameter
-          'memtest', which allows memtest to be disabled at boot.  If this
-          option is set to 0 (zero), the memtest kernel parameter will
-          default to 0, disabling memtest at bootup.  If this option is
-          set to 4, the memtest kernel parameter will default to 4,
-          enabling memtest at bootup, and use that as pattern number.
-
-          If you are unsure how to answer this question, answer 0.
-
-config ACPI_SRAT
-        def_bool y
-        depends on X86_32 && ACPI && NUMA && (X86_SUMMIT || X86_GENERICARCH)
-        select ACPI_NUMA
-
-config HAVE_ARCH_PARSE_SRAT
-        def_bool y
-        depends on ACPI_SRAT
-
 config X86_SUMMIT_NUMA
         def_bool y
-        depends on X86_32 && NUMA && (X86_SUMMIT || X86_GENERICARCH)
+        depends on X86_32 && NUMA && X86_GENERICARCH
 
 config X86_CYCLONE_TIMER
         def_bool y
-        depends on X86_32 && X86_SUMMIT || X86_GENERICARCH
+        depends on X86_GENERICARCH
 
 config ES7000_CLUSTERED_APIC
         def_bool y
@@ -549,6 +551,21 @@ config CALGARY_IOMMU_ENABLED_BY_DEFAULT
           Calgary anyway, pass 'iommu=calgary' on the kernel command line.
           If unsure, say Y.
 
+config AMD_IOMMU
+        bool "AMD IOMMU support"
+        select SWIOTLB
+        depends on X86_64 && PCI && ACPI
+        help
+          With this option you can enable support for AMD IOMMU hardware in
+          your system. An IOMMU is a hardware component which provides
+          remapping of DMA memory accesses from devices. With an AMD IOMMU you
+          can isolate the the DMA memory of different devices and protect the
+          system from misbehaving device drivers or hardware.
+
+          You can find out if your system has an AMD IOMMU if you look into
+          your BIOS for an option to enable it or if you have an IVRS ACPI
+          table.
+
 # need this always selected by IOMMU for the VIA workaround
 config SWIOTLB
         bool
@@ -560,21 +577,36 @@ config SWIOTLB
           3 GB of memory. If unsure, say Y.
 
 config IOMMU_HELPER
-        def_bool (CALGARY_IOMMU || GART_IOMMU || SWIOTLB)
+        def_bool (CALGARY_IOMMU || GART_IOMMU || SWIOTLB || AMD_IOMMU)
+config MAXSMP
+        bool "Configure Maximum number of SMP Processors and NUMA Nodes"
+        depends on X86_64 && SMP
+        default n
+        help
+          Configure maximum number of CPUS and NUMA Nodes for this architecture.
+          If unsure, say N.
 
+if MAXSMP
 config NR_CPUS
-        int "Maximum number of CPUs (2-255)"
-        range 2 255
+        int
+        default "4096"
+endif
+
+if !MAXSMP
+config NR_CPUS
+        int "Maximum number of CPUs (2-4096)"
+        range 2 4096
         depends on SMP
         default "32" if X86_NUMAQ || X86_SUMMIT || X86_BIGSMP || X86_ES7000
         default "8"
         help
           This allows you to specify the maximum number of CPUs which this
-          kernel will support.  The maximum supported value is 255 and the
+          kernel will support.  The maximum supported value is 4096 and the
           minimum value which makes sense is 2.
 
           This is purely to save memory - each supported CPU adds
           approximately eight kilobytes to the kernel image.
+endif
 
 config SCHED_SMT
         bool "SMT (Hyperthreading) scheduler support"
@@ -598,7 +630,7 @@ source "kernel/Kconfig.preempt"
 
 config X86_UP_APIC
         bool "Local APIC support on uniprocessors"
-        depends on X86_32 && !SMP && !(X86_VISWS || X86_VOYAGER || X86_GENERICARCH)
+        depends on X86_32 && !SMP && !(X86_VOYAGER || X86_GENERICARCH)
         help
           A local APIC (Advanced Programmable Interrupt Controller) is an
           integrated interrupt controller in the CPU. If you have a single-CPU
@@ -623,11 +655,11 @@ config X86_UP_IOAPIC
 
 config X86_LOCAL_APIC
         def_bool y
-        depends on X86_64 || (X86_32 && (X86_UP_APIC || ((X86_VISWS || SMP) && !X86_VOYAGER) || X86_GENERICARCH))
+        depends on X86_64 || (X86_32 && (X86_UP_APIC || (SMP && !X86_VOYAGER) || X86_GENERICARCH))
 
 config X86_IO_APIC
         def_bool y
-        depends on X86_64 || (X86_32 && (X86_UP_IOAPIC || (SMP && !(X86_VISWS || X86_VOYAGER)) || X86_GENERICARCH))
+        depends on X86_64 || (X86_32 && (X86_UP_IOAPIC || (SMP && !X86_VOYAGER) || X86_GENERICARCH))
 
 config X86_VISWS_APIC
         def_bool y
@@ -681,7 +713,7 @@ config X86_MCE_NONFATAL
 
 config X86_MCE_P4THERMAL
         bool "check for P4 thermal throttling interrupt."
-        depends on X86_32 && X86_MCE && (X86_UP_APIC || SMP) && !X86_VISWS
+        depends on X86_32 && X86_MCE && (X86_UP_APIC || SMP)
         help
           Enabling this feature will cause a message to be printed when the P4
           enters thermal throttling.
@@ -911,9 +943,9 @@ config X86_PAE
 config NUMA
         bool "Numa Memory Allocation and Scheduler Support (EXPERIMENTAL)"
         depends on SMP
-        depends on X86_64 || (X86_32 && HIGHMEM64G && (X86_NUMAQ || (X86_SUMMIT || X86_GENERICARCH) && ACPI) && EXPERIMENTAL)
+        depends on X86_64 || (X86_32 && HIGHMEM64G && (X86_NUMAQ || X86_BIGSMP || X86_SUMMIT && ACPI) && EXPERIMENTAL)
         default n if X86_PC
-        default y if (X86_NUMAQ || X86_SUMMIT)
+        default y if (X86_NUMAQ || X86_SUMMIT || X86_BIGSMP)
         help
           Enable NUMA (Non Uniform Memory Access) support.
           The kernel will try to allocate memory used by a CPU on the
@@ -965,13 +997,25 @@ config NUMA_EMU
           into virtual nodes when booted with "numa=fake=N", where N is the
           number of nodes. This is only useful for debugging.
 
+if MAXSMP
+
+config NODES_SHIFT
+        int
+        default "9"
+endif
+
+if !MAXSMP
 config NODES_SHIFT
-        int "Max num nodes shift(1-9)"
-        range 1 9  if X86_64
+        int "Maximum NUMA Nodes (as a power of 2)"
+        range 1 9   if X86_64
         default "6" if X86_64
         default "4" if X86_NUMAQ
         default "3"
         depends on NEED_MULTIPLE_NODES
+        help
+          Specify the maximum number of NUMA Nodes available on the target
+          system.  Increases memory reserved to accomodate various tables.
+endif
 
 config HAVE_ARCH_BOOTMEM_NODE
         def_bool y
@@ -1090,6 +1134,40 @@ config MTRR
 
           See <file:Documentation/mtrr.txt> for more information.
 
+config MTRR_SANITIZER
+        def_bool y
+        prompt "MTRR cleanup support"
+        depends on MTRR
+        help
+          Convert MTRR layout from continuous to discrete, so some X driver
+          could add WB entries.
+
+          Say N here if you see bootup problems (boot crash, boot hang,
+          spontaneous reboots).
+
+          Could be disabled with disable_mtrr_cleanup. Also mtrr_chunk_size
+          could be used to send largest mtrr entry size for continuous block
+          to hold holes (aka. UC entries)
+
+          If unsure, say Y.
+
+config MTRR_SANITIZER_ENABLE_DEFAULT
+        int "MTRR cleanup enable value (0-1)"
+        range 0 1
+        default "0"
+        depends on MTRR_SANITIZER
+        help
+          Enable mtrr cleanup default value
+
+config MTRR_SANITIZER_SPARE_REG_NR_DEFAULT
+        int "MTRR cleanup spare reg num (0-7)"
+        range 0 7
+        default "1"
+        depends on MTRR_SANITIZER
+        help
+          mtrr cleanup spare entries default, it can be changed via
+          mtrr_spare_reg_nr=
+
 config X86_PAT
         bool
         prompt "x86 PAT support"
@@ -1190,7 +1268,6 @@ config KEXEC
 
 config CRASH_DUMP
         bool "kernel crash dumps (EXPERIMENTAL)"
-        depends on EXPERIMENTAL
         depends on X86_64 || (X86_32 && HIGHMEM)
         help
           Generate crash dump after being started by kexec.
@@ -1339,7 +1416,7 @@ config X86_APM_BOOT
 
 menuconfig APM
         tristate "APM (Advanced Power Management) BIOS support"
-        depends on X86_32 && PM_SLEEP && !X86_VISWS
+        depends on X86_32 && PM_SLEEP
         ---help---
           APM is a BIOS specification for saving power using several different
           techniques. This is mostly useful for battery powered laptops with
@@ -1475,8 +1552,7 @@ endmenu
 menu "Bus options (PCI etc.)"
 
 config PCI
-        bool "PCI support" if !X86_VISWS && !X86_VSMP
-        depends on !X86_VOYAGER
+        bool "PCI support"
         default y
         select ARCH_SUPPORTS_MSI if (X86_LOCAL_APIC && X86_IO_APIC)
         help
@@ -1487,7 +1563,7 @@ config PCI
 
 choice
         prompt "PCI access mode"
-        depends on X86_32 && PCI && !X86_VISWS
+        depends on X86_32 && PCI
         default PCI_GOANY
         ---help---
           On PCI systems, the BIOS can be used to detect the PCI devices and
@@ -1524,12 +1600,12 @@ endchoice
 
 config PCI_BIOS
         def_bool y
-        depends on X86_32 && !X86_VISWS && PCI && (PCI_GOBIOS || PCI_GOANY)
+        depends on X86_32 && PCI && (PCI_GOBIOS || PCI_GOANY)
 
 # x86-64 doesn't support PCI BIOS access from long mode so always go direct.
 config PCI_DIRECT
         def_bool y
-        depends on PCI && (X86_64 || (PCI_GODIRECT || PCI_GOANY || PCI_GOOLPC) || X86_VISWS)
+        depends on PCI && (X86_64 || (PCI_GODIRECT || PCI_GOANY || PCI_GOOLPC))
 
 config PCI_MMCONFIG
         def_bool y
@@ -1589,7 +1665,7 @@ if X86_32
 
 config ISA
         bool "ISA support"
-        depends on !(X86_VOYAGER || X86_VISWS)
+        depends on !X86_VOYAGER
         help
           Find out whether you have ISA slots on your motherboard.  ISA is the
           name of a bus system, i.e. the way the CPU talks to the other stuff
@@ -1616,7 +1692,7 @@ config EISA
 source "drivers/eisa/Kconfig"
 
 config MCA
-        bool "MCA support" if !(X86_VISWS || X86_VOYAGER)
+        bool "MCA support" if !X86_VOYAGER
         default y if X86_VOYAGER
         help
           MicroChannel Architecture is found in some IBM PS/2 machines and
diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu
index 2ad6301849a1..abff1b84ed5b 100644
--- a/arch/x86/Kconfig.cpu
+++ b/arch/x86/Kconfig.cpu
@@ -344,7 +344,7 @@ config X86_F00F_BUG
 
 config X86_WP_WORKS_OK
         def_bool y
-        depends on X86_32 && !M386
+        depends on !M386
 
 config X86_INVLPG
         def_bool y
@@ -399,6 +399,10 @@ config X86_TSC
         def_bool y
         depends on ((MWINCHIP3D || MWINCHIP2 || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2) && !X86_NUMAQ) || X86_64
 
+config X86_CMPXCHG64
+        def_bool y
+        depends on X86_PAE || X86_64
+
 # this should be set for all -march=.. options where the compiler
 # generates cmov.
 config X86_CMOV
diff --git a/arch/x86/Kconfig.debug b/arch/x86/Kconfig.debug
index 18363374d51a..ae36bfa814e5 100644
--- a/arch/x86/Kconfig.debug
+++ b/arch/x86/Kconfig.debug
@@ -20,6 +20,14 @@ config NONPROMISC_DEVMEM
 
           If in doubt, say Y.
 
+config X86_VERBOSE_BOOTUP
+        bool "Enable verbose x86 bootup info messages"
+        default y
+        help
+          Enables the informational output from the decompression stage
+          (e.g. bzImage) of the boot. If you disable this you will still
+          see errors. Disable this if you want silent bootup.
+
 config EARLY_PRINTK
         bool "Early printk" if EMBEDDED
         default y
@@ -60,7 +68,7 @@ config DEBUG_PAGEALLOC
 config DEBUG_PER_CPU_MAPS
         bool "Debug access to per_cpu maps"
         depends on DEBUG_KERNEL
-        depends on X86_64_SMP
+        depends on X86_SMP
         default n
         help
           Say Y to verify that the per_cpu map being accessed has
@@ -129,15 +137,6 @@ config 4KSTACKS
           on the VM subsystem for higher order allocations. This option
           will also use IRQ stacks to compensate for the reduced stackspace.
 
-config X86_FIND_SMP_CONFIG
-        def_bool y
-        depends on X86_LOCAL_APIC || X86_VOYAGER
-        depends on X86_32
-
-config X86_MPPARSE
-        def_bool y
-        depends on (X86_32 && (X86_LOCAL_APIC && !X86_VISWS)) || X86_64
-
 config DOUBLEFAULT
         default y
         bool "Enable doublefault exception handler" if EMBEDDED
@@ -172,6 +171,33 @@ config IOMMU_LEAK
           Add a simple leak tracer to the IOMMU code. This is useful when you
           are debugging a buggy device driver that leaks IOMMU mappings.
 
+config MMIOTRACE_HOOKS
+        bool
+
+config MMIOTRACE
+        bool "Memory mapped IO tracing"
+        depends on DEBUG_KERNEL && PCI
+        select TRACING
+        select MMIOTRACE_HOOKS
+        help
+          Mmiotrace traces Memory Mapped I/O access and is meant for
+          debugging and reverse engineering. It is called from the ioremap
+          implementation and works via page faults. Tracing is disabled by
+          default and can be enabled at run-time.
+
+          See Documentation/tracers/mmiotrace.txt.
+          If you are not helping to develop drivers, say N.
+
+config MMIOTRACE_TEST
+        tristate "Test module for mmiotrace"
+        depends on MMIOTRACE && m
+        help
+          This is a dumb module for testing mmiotrace. It is very dangerous
+          as it will write garbage to IO memory starting at a given address.
+          However, it should be safe to use on e.g. unused portion of VRAM.
+
+          Say N, unless you absolutely know what you are doing.
+
 #
 # IO delay types:
 #
diff --git a/arch/x86/Makefile b/arch/x86/Makefile
index 3cff3c894cf3..919ce21ea654 100644
--- a/arch/x86/Makefile
+++ b/arch/x86/Makefile
@@ -113,33 +113,11 @@ mcore-y  := arch/x86/mach-default/
 mflags-$(CONFIG_X86_VOYAGER)    := -Iinclude/asm-x86/mach-voyager
 mcore-$(CONFIG_X86_VOYAGER)     := arch/x86/mach-voyager/
 
-# VISWS subarch support
-mflags-$(CONFIG_X86_VISWS)      := -Iinclude/asm-x86/mach-visws
-mcore-$(CONFIG_X86_VISWS)       := arch/x86/mach-visws/
-
-# NUMAQ subarch support
-mflags-$(CONFIG_X86_NUMAQ)      := -Iinclude/asm-x86/mach-numaq
-mcore-$(CONFIG_X86_NUMAQ)       := arch/x86/mach-default/
-
-# BIGSMP subarch support
-mflags-$(CONFIG_X86_BIGSMP)     := -Iinclude/asm-x86/mach-bigsmp
-mcore-$(CONFIG_X86_BIGSMP)      := arch/x86/mach-default/
-
-#Summit subarch support
-mflags-$(CONFIG_X86_SUMMIT)     := -Iinclude/asm-x86/mach-summit
-mcore-$(CONFIG_X86_SUMMIT)      := arch/x86/mach-default/
-
 # generic subarchitecture
 mflags-$(CONFIG_X86_GENERICARCH):= -Iinclude/asm-x86/mach-generic
 fcore-$(CONFIG_X86_GENERICARCH) += arch/x86/mach-generic/
 mcore-$(CONFIG_X86_GENERICARCH) := arch/x86/mach-default/
 
-
-# ES7000 subarch support
-mflags-$(CONFIG_X86_ES7000)     := -Iinclude/asm-x86/mach-es7000
-fcore-$(CONFIG_X86_ES7000)      := arch/x86/mach-es7000/
-mcore-$(CONFIG_X86_ES7000)      := arch/x86/mach-default/
-
 # RDC R-321x subarch support
 mflags-$(CONFIG_X86_RDC321X)    := -Iinclude/asm-x86/mach-rdc321x
 mcore-$(CONFIG_X86_RDC321X)     := arch/x86/mach-default/
@@ -160,6 +138,7 @@ KBUILD_AFLAGS += $(mflags-y)
 
 head-y := arch/x86/kernel/head_$(BITS).o
 head-y += arch/x86/kernel/head$(BITS).o
+head-y += arch/x86/kernel/head.o
 head-y += arch/x86/kernel/init_task.o
 
 libs-y  += arch/x86/lib/
@@ -210,12 +189,12 @@ all: bzImage
 
 # KBUILD_IMAGE specify target image being built
                     KBUILD_IMAGE := $(boot)/bzImage
-zImage zlilo zdisk: KBUILD_IMAGE := arch/x86/boot/zImage
+zImage zlilo zdisk: KBUILD_IMAGE := $(boot)/zImage
 
 zImage bzImage: vmlinux
         $(Q)$(MAKE) $(build)=$(boot) $(KBUILD_IMAGE)
         $(Q)mkdir -p $(objtree)/arch/$(UTS_MACHINE)/boot
-        $(Q)ln -fsn ../../x86/boot/bzImage $(objtree)/arch/$(UTS_MACHINE)/boot/bzImage
+        $(Q)ln -fsn ../../x86/boot/bzImage $(objtree)/arch/$(UTS_MACHINE)/boot/$@
 
 compressed: zImage
 
diff --git a/arch/x86/boot/a20.c b/arch/x86/boot/a20.c
index e01aafd03bde..4063d630deff 100644
--- a/arch/x86/boot/a20.c
+++ b/arch/x86/boot/a20.c
@@ -1,7 +1,7 @@
 /* -*- linux-c -*- ------------------------------------------------------- *
  *
  *   Copyright (C) 1991, 1992 Linus Torvalds
- *   Copyright 2007 rPath, Inc. - All Rights Reserved
+ *   Copyright 2007-2008 rPath, Inc. - All Rights Reserved
  *
  *   This file is part of the Linux kernel, and is made available under
  *   the terms of the GNU General Public License version 2.
@@ -95,6 +95,9 @@ static void enable_a20_kbc(void)
 
         outb(0xdf, 0x60);       /* A20 on */
         empty_8042();
+
+        outb(0xff, 0x64);       /* Null command, but UHCI wants it */
+        empty_8042();
 }
 
 static void enable_a20_fast(void)
diff --git a/arch/x86/boot/compressed/head_64.S b/arch/x86/boot/compressed/head_64.S
index d8819efac81d..1d5dff4123e1 100644
--- a/arch/x86/boot/compressed/head_64.S
+++ b/arch/x86/boot/compressed/head_64.S
@@ -30,6 +30,7 @@
 #include <asm/page.h>
 #include <asm/boot.h>
 #include <asm/msr.h>
+#include <asm/processor-flags.h>
 #include <asm/asm-offsets.h>
 
 .section ".text.head"
@@ -109,7 +110,7 @@ startup_32:
 
         /* Enable PAE mode */
         xorl    %eax, %eax
-        orl     $(1 << 5), %eax
+        orl     $(X86_CR4_PAE), %eax
         movl    %eax, %cr4
 
  /*
@@ -170,7 +171,7 @@ startup_32:
         pushl   %eax
 
         /* Enter paged protected Mode, activating Long Mode */
-        movl    $0x80000001, %eax /* Enable Paging and Protected mode */
+        movl    $(X86_CR0_PG | X86_CR0_PE), %eax /* Enable Paging and Protected mode */
         movl    %eax, %cr0
 
         /* Jump from 32bit compatibility mode into 64bit mode. */
diff --git a/arch/x86/boot/compressed/misc.c b/arch/x86/boot/compressed/misc.c
index 90456cee47c3..bc5553b496f7 100644
--- a/arch/x86/boot/compressed/misc.c
+++ b/arch/x86/boot/compressed/misc.c
@@ -30,6 +30,7 @@
 #include <asm/io.h>
 #include <asm/page.h>
 #include <asm/boot.h>
+#include <asm/bootparam.h>
 
 /* WARNING!!
  * This code is compiled with -fPIC and it is relocated dynamically
@@ -187,13 +188,8 @@ static void gzip_release(void **);
 /*
  * This is set up by the setup-routine at boot-time
  */
-static unsigned char *real_mode; /* Pointer to real-mode data */
-
-#define RM_EXT_MEM_K   (*(unsigned short *)(real_mode + 0x2))
-#ifndef STANDARD_MEMORY_BIOS_CALL
-#define RM_ALT_MEM_K   (*(unsigned long *)(real_mode + 0x1e0))
-#endif
-#define RM_SCREEN_INFO (*(struct screen_info *)(real_mode+0))
+static struct boot_params *real_mode;           /* Pointer to real-mode data */
+static int quiet;
 
 extern unsigned char input_data[];
 extern int input_len;
@@ -206,7 +202,8 @@ static void free(void *where);
 static void *memset(void *s, int c, unsigned n);
 static void *memcpy(void *dest, const void *src, unsigned n);
 
-static void putstr(const char *);
+static void __putstr(int, const char *);
+#define putstr(__x)  __putstr(0, __x)
 
 #ifdef CONFIG_X86_64
 #define memptr long
@@ -221,10 +218,6 @@ static char *vidmem;
 static int vidport;
 static int lines, cols;
 
-#ifdef CONFIG_X86_NUMAQ
-void *xquad_portio;
-#endif
-
 #include "../../../../lib/inflate.c"
 
 static void *malloc(int size)
@@ -270,18 +263,24 @@ static void scroll(void)
                 vidmem[i] = ' ';
 }
 
-static void putstr(const char *s)
+static void __putstr(int error, const char *s)
 {
         int x, y, pos;
         char c;
 
+#ifndef CONFIG_X86_VERBOSE_BOOTUP
+        if (!error)
+                return;
+#endif
+
 #ifdef CONFIG_X86_32
-        if (RM_SCREEN_INFO.orig_video_mode == 0 && lines == 0 && cols == 0)
+        if (real_mode->screen_info.orig_video_mode == 0 &&
+            lines == 0 && cols == 0)
                 return;
 #endif
 
-        x = RM_SCREEN_INFO.orig_x;
-        y = RM_SCREEN_INFO.orig_y;
+        x = real_mode->screen_info.orig_x;
+        y = real_mode->screen_info.orig_y;
 
         while ((c = *s++) != '\0') {
                 if (c == '\n') {
@@ -302,8 +301,8 @@ static void putstr(const char *s)
                 }
         }
 
-        RM_SCREEN_INFO.orig_x = x;
-        RM_SCREEN_INFO.orig_y = y;
+        real_mode->screen_info.orig_x = x;
+        real_mode->screen_info.orig_y = y;
 
         pos = (x + cols * y) * 2;       /* Update cursor position */
         outb(14, vidport);
@@ -366,9 +365,9 @@ static void flush_window(void)
 
 static void error(char *x)
 {
-        putstr("\n\n");
-        putstr(x);
-        putstr("\n\n -- System halted");
+        __putstr(1, "\n\n");
+        __putstr(1, x);
+        __putstr(1, "\n\n -- System halted");
 
         while (1)
                 asm("hlt");
@@ -395,7 +394,8 @@ static void parse_elf(void *output)
                 return;
         }
 
-        putstr("Parsing ELF... ");
+        if (!quiet)
+                putstr("Parsing ELF... ");
 
         phdrs = malloc(sizeof(*phdrs) * ehdr.e_phnum);
         if (!phdrs)
@@ -430,7 +430,10 @@ asmlinkage void decompress_kernel(void *rmode, memptr heap,
 {
         real_mode = rmode;
 
-        if (RM_SCREEN_INFO.orig_video_mode == 7) {
+        if (real_mode->hdr.loadflags & QUIET_FLAG)
+                quiet = 1;
+
+        if (real_mode->screen_info.orig_video_mode == 7) {
                 vidmem = (char *) 0xb0000;
                 vidport = 0x3b4;
         } else {
@@ -438,8 +441,8 @@ asmlinkage void decompress_kernel(void *rmode, memptr heap,
                 vidport = 0x3d4;
         }
 
-        lines = RM_SCREEN_INFO.orig_video_lines;
-        cols = RM_SCREEN_INFO.orig_video_cols;
+        lines = real_mode->screen_info.orig_video_lines;
+        cols = real_mode->screen_info.orig_video_cols;
 
         window = output;                /* Output buffer (Normally at 1M) */
         free_mem_ptr     = heap;        /* Heap */
@@ -465,9 +468,11 @@ asmlinkage void decompress_kernel(void *rmode, memptr heap,
 #endif
 
         makecrc();
-        putstr("\nDecompressing Linux... ");
+        if (!quiet)
+                putstr("\nDecompressing Linux... ");
         gunzip();
         parse_elf(output);
-        putstr("done.\nBooting the kernel.\n");
+        if (!quiet)
+                putstr("done.\nBooting the kernel.\n");
         return;
 }
diff --git a/arch/x86/boot/compressed/relocs.c b/arch/x86/boot/compressed/relocs.c
index edaadea90aaf..a1310c52fc0c 100644
--- a/arch/x86/boot/compressed/relocs.c
+++ b/arch/x86/boot/compressed/relocs.c
@@ -10,16 +10,20 @@
 #define USE_BSD
 #include <endian.h>
 
-#define MAX_SHDRS 100
 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
 static Elf32_Ehdr ehdr;
-static Elf32_Shdr shdr[MAX_SHDRS];
-static Elf32_Sym  *symtab[MAX_SHDRS];
-static Elf32_Rel  *reltab[MAX_SHDRS];
-static char *strtab[MAX_SHDRS];
 static unsigned long reloc_count, reloc_idx;
 static unsigned long *relocs;
 
+struct section {
+        Elf32_Shdr     shdr;
+        struct section *link;
+        Elf32_Sym      *symtab;
+        Elf32_Rel      *reltab;
+        char           *strtab;
+};
+static struct section *secs;
+
 /*
  * Following symbols have been audited. There values are constant and do
  * not change if bzImage is loaded at a different physical address than
@@ -35,7 +39,7 @@ static int is_safe_abs_reloc(const char* sym_name)
 {
         int i;
 
-        for(i = 0; i < ARRAY_SIZE(safe_abs_relocs); i++) {
+        for (i = 0; i < ARRAY_SIZE(safe_abs_relocs); i++) {
                 if (!strcmp(sym_name, safe_abs_relocs[i]))
                         /* Match found */
                         return 1;
@@ -137,10 +141,10 @@ static const char *sec_name(unsigned shndx)
 {
         const char *sec_strtab;
         const char *name;
-        sec_strtab = strtab[ehdr.e_shstrndx];
+        sec_strtab = secs[ehdr.e_shstrndx].strtab;
         name = "<noname>";
         if (shndx < ehdr.e_shnum) {
-                name = sec_strtab + shdr[shndx].sh_name;
+                name = sec_strtab + secs[shndx].shdr.sh_name;
         }
         else if (shndx == SHN_ABS) {
                 name = "ABSOLUTE";
@@ -159,7 +163,7 @@ static const char *sym_name(const char *sym_strtab, Elf32_Sym *sym)
                 name = sym_strtab + sym->st_name;
         }
         else {
-                name = sec_name(shdr[sym->st_shndx].sh_name);
+                name = sec_name(secs[sym->st_shndx].shdr.sh_name);
         }
         return name;
 }
@@ -244,29 +248,34 @@ static void read_ehdr(FILE *fp)
 static void read_shdrs(FILE *fp)
 {
         int i;
-        if (ehdr.e_shnum > MAX_SHDRS) {
-                die("%d section headers supported: %d\n",
-                        ehdr.e_shnum, MAX_SHDRS);
+        Elf32_Shdr shdr;
+
+        secs = calloc(ehdr.e_shnum, sizeof(struct section));
+        if (!secs) {
+                die("Unable to allocate %d section headers\n",
+                    ehdr.e_shnum);
         }
         if (fseek(fp, ehdr.e_shoff, SEEK_SET) < 0) {
                 die("Seek to %d failed: %s\n",
                         ehdr.e_shoff, strerror(errno));
         }
-        if (fread(&shdr, sizeof(shdr[0]), ehdr.e_shnum, fp) != ehdr.e_shnum) {
-                die("Cannot read ELF section headers: %s\n",
-                        strerror(errno));
-        }
-        for(i = 0; i < ehdr.e_shnum; i++) {
-                shdr[i].sh_name      = elf32_to_cpu(shdr[i].sh_name);
-                shdr[i].sh_type      = elf32_to_cpu(shdr[i].sh_type);
-                shdr[i].sh_flags     = elf32_to_cpu(shdr[i].sh_flags);
-                shdr[i].sh_addr      = elf32_to_cpu(shdr[i].sh_addr);
-                shdr[i].sh_offset    = elf32_to_cpu(shdr[i].sh_offset);
-                shdr[i].sh_size      = elf32_to_cpu(shdr[i].sh_size);
-                shdr[i].sh_link      = elf32_to_cpu(shdr[i].sh_link);
-                shdr[i].sh_info      = elf32_to_cpu(shdr[i].sh_info);
-                shdr[i].sh_addralign = elf32_to_cpu(shdr[i].sh_addralign);
-                shdr[i].sh_entsize   = elf32_to_cpu(shdr[i].sh_entsize);
+        for (i = 0; i < ehdr.e_shnum; i++) {
+                struct section *sec = &secs[i];
+                if (fread(&shdr, sizeof shdr, 1, fp) != 1)
+                        die("Cannot read ELF section headers %d/%d: %s\n",
+                            i, ehdr.e_shnum, strerror(errno));
+                sec->shdr.sh_name      = elf32_to_cpu(shdr.sh_name);
+                sec->shdr.sh_type      = elf32_to_cpu(shdr.sh_type);
+                sec->shdr.sh_flags     = elf32_to_cpu(shdr.sh_flags);
+                sec->shdr.sh_addr      = elf32_to_cpu(shdr.sh_addr);
+                sec->shdr.sh_offset    = elf32_to_cpu(shdr.sh_offset);
+                sec->shdr.sh_size      = elf32_to_cpu(shdr.sh_size);
+                sec->shdr.sh_link      = elf32_to_cpu(shdr.sh_link);
+                sec->shdr.sh_info      = elf32_to_cpu(shdr.sh_info);
+                sec->shdr.sh_addralign = elf32_to_cpu(shdr.sh_addralign);
+                sec->shdr.sh_entsize   = elf32_to_cpu(shdr.sh_entsize);
+                if (sec->shdr.sh_link < ehdr.e_shnum)
+                        sec->link = &secs[sec->shdr.sh_link];
         }
 
 }
@@ -274,20 +283,22 @@ static void read_shdrs(FILE *fp)
 static void read_strtabs(FILE *fp)
 {
         int i;
-        for(i = 0; i < ehdr.e_shnum; i++) {
-                if (shdr[i].sh_type != SHT_STRTAB) {
+        for (i = 0; i < ehdr.e_shnum; i++) {
+                struct section *sec = &secs[i];
+                if (sec->shdr.sh_type != SHT_STRTAB) {
                         continue;
                 }
-                strtab[i] = malloc(shdr[i].sh_size);
-                if (!strtab[i]) {
+                sec->strtab = malloc(sec->shdr.sh_size);
+                if (!sec->strtab) {
                         die("malloc of %d bytes for strtab failed\n",
-                                shdr[i].sh_size);
+                                sec->shdr.sh_size);
                 }
-                if (fseek(fp, shdr[i].sh_offset, SEEK_SET) < 0) {
+                if (fseek(fp, sec->shdr.sh_offset, SEEK_SET) < 0) {
                         die("Seek to %d failed: %s\n",
-                                shdr[i].sh_offset, strerror(errno));
+                                sec->shdr.sh_offset, strerror(errno));
                 }
-                if (fread(strtab[i], 1, shdr[i].sh_size, fp) != shdr[i].sh_size) {
+                if (fread(sec->strtab, 1, sec->shdr.sh_size, fp)
+                    != sec->shdr.sh_size) {
                         die("Cannot read symbol table: %s\n",
                                 strerror(errno));
                 }
@@ -297,28 +308,31 @@ static void read_strtabs(FILE *fp)
 static void read_symtabs(FILE *fp)
 {
         int i,j;
-        for(i = 0; i < ehdr.e_shnum; i++) {
-                if (shdr[i].sh_type != SHT_SYMTAB) {
+        for (i = 0; i < ehdr.e_shnum; i++) {
+                struct section *sec = &secs[i];
+                if (sec->shdr.sh_type != SHT_SYMTAB) {
                         continue;
                 }
-                symtab[i] = malloc(shdr[i].sh_size);
-                if (!symtab[i]) {
+                sec->symtab = malloc(sec->shdr.sh_size);
+                if (!sec->symtab) {
                         die("malloc of %d bytes for symtab failed\n",
-                                shdr[i].sh_size);
+                                sec->shdr.sh_size);
                 }
-                if (fseek(fp, shdr[i].sh_offset, SEEK_SET) < 0) {
+                if (fseek(fp, sec->shdr.sh_offset, SEEK_SET) < 0) {
                         die("Seek to %d failed: %s\n",
-                                shdr[i].sh_offset, strerror(errno));
+                                sec->shdr.sh_offset, strerror(errno));
                 }
-                if (fread(symtab[i], 1, shdr[i].sh_size, fp) != shdr[i].sh_size) {
+                if (fread(sec->symtab, 1, sec->shdr.sh_size, fp)
+                    != sec->shdr.sh_size) {
                         die("Cannot read symbol table: %s\n",
                                 strerror(errno));
                 }
-                for(j = 0; j < shdr[i].sh_size/sizeof(symtab[i][0]); j++) {
-                        symtab[i][j].st_name  = elf32_to_cpu(symtab[i][j].st_name);
-                        symtab[i][j].st_value = elf32_to_cpu(symtab[i][j].st_value);
-                        symtab[i][j].st_size  = elf32_to_cpu(symtab[i][j].st_size);
-                        symtab[i][j].st_shndx = elf16_to_cpu(symtab[i][j].st_shndx);
+                for (j = 0; j < sec->shdr.sh_size/sizeof(Elf32_Sym); j++) {
+                        Elf32_Sym *sym = &sec->symtab[j];
+                        sym->st_name  = elf32_to_cpu(sym->st_name);
+                        sym->st_value = elf32_to_cpu(sym->st_value);
+                        sym->st_size  = elf32_to_cpu(sym->st_size);
+                        sym->st_shndx = elf16_to_cpu(sym->st_shndx);
                 }
         }
 }
@@ -327,26 +341,29 @@ static void read_symtabs(FILE *fp)
 static void read_relocs(FILE *fp)
 {
         int i,j;
-        for(i = 0; i < ehdr.e_shnum; i++) {
-                if (shdr[i].sh_type != SHT_REL) {
+        for (i = 0; i < ehdr.e_shnum; i++) {
+                struct section *sec = &secs[i];
+                if (sec->shdr.sh_type != SHT_REL) {
                         continue;
                 }
-                reltab[i] = malloc(shdr[i].sh_size);
-                if (!reltab[i]) {
+                sec->reltab = malloc(sec->shdr.sh_size);
+                if (!sec->reltab) {
                         die("malloc of %d bytes for relocs failed\n",
-                                shdr[i].sh_size);
+                                sec->shdr.sh_size);
                 }
-                if (fseek(fp, shdr[i].sh_offset, SEEK_SET) < 0) {
+                if (fseek(fp, sec->shdr.sh_offset, SEEK_SET) < 0) {
                         die("Seek to %d failed: %s\n",
-                                shdr[i].sh_offset, strerror(errno));
+                                sec->shdr.sh_offset, strerror(errno));
                 }
-                if (fread(reltab[i], 1, shdr[i].sh_size, fp) != shdr[i].sh_size) {
+                if (fread(sec->reltab, 1, sec->shdr.sh_size, fp)
+                    != sec->shdr.sh_size) {
                         die("Cannot read symbol table: %s\n",
                                 strerror(errno));
                 }
-                for(j = 0; j < shdr[i].sh_size/sizeof(reltab[0][0]); j++) {
-                        reltab[i][j].r_offset = elf32_to_cpu(reltab[i][j].r_offset);
-                        reltab[i][j].r_info   = elf32_to_cpu(reltab[i][j].r_info);
+                for (j = 0; j < sec->shdr.sh_size/sizeof(Elf32_Rel); j++) {
+                        Elf32_Rel *rel = &sec->reltab[j];
+                        rel->r_offset = elf32_to_cpu(rel->r_offset);
+                        rel->r_info   = elf32_to_cpu(rel->r_info);
                 }
         }
 }
@@ -357,19 +374,21 @@ static void print_absolute_symbols(void)
         int i;
         printf("Absolute symbols\n");
         printf(" Num:    Value Size  Type       Bind        Visibility  Name\n");
-        for(i = 0; i < ehdr.e_shnum; i++) {
+        for (i = 0; i < ehdr.e_shnum; i++) {
+                struct section *sec = &secs[i];
                 char *sym_strtab;
                 Elf32_Sym *sh_symtab;
                 int j;
-                if (shdr[i].sh_type != SHT_SYMTAB) {
+
+                if (sec->shdr.sh_type != SHT_SYMTAB) {
                         continue;
                 }
-                sh_symtab = symtab[i];
-                sym_strtab = strtab[shdr[i].sh_link];
-                for(j = 0; j < shdr[i].sh_size/sizeof(symtab[0][0]); j++) {
+                sh_symtab = sec->symtab;
+                sym_strtab = sec->link->strtab;
+                for (j = 0; j < sec->shdr.sh_size/sizeof(Elf32_Sym); j++) {
                         Elf32_Sym *sym;
                         const char *name;
-                        sym = &symtab[i][j];
+                        sym = &sec->symtab[j];
                         name = sym_name(sym_strtab, sym);
                         if (sym->st_shndx != SHN_ABS) {
                                 continue;
@@ -389,26 +408,27 @@ static void print_absolute_relocs(void)
 {
         int i, printed = 0;
 
-        for(i = 0; i < ehdr.e_shnum; i++) {
+        for (i = 0; i < ehdr.e_shnum; i++) {
+                struct section *sec = &secs[i];
+                struct section *sec_applies, *sec_symtab;
                 char *sym_strtab;
                 Elf32_Sym *sh_symtab;
-                unsigned sec_applies, sec_symtab;
                 int j;
-                if (shdr[i].sh_type != SHT_REL) {
+                if (sec->shdr.sh_type != SHT_REL) {
                         continue;
                 }
-                sec_symtab  = shdr[i].sh_link;
-                sec_applies = shdr[i].sh_info;
-                if (!(shdr[sec_applies].sh_flags & SHF_ALLOC)) {
+                sec_symtab  = sec->link;
+                sec_applies = &secs[sec->shdr.sh_info];
+                if (!(sec_applies->shdr.sh_flags & SHF_ALLOC)) {
                         continue;
                 }
-                sh_symtab = symtab[sec_symtab];
-                sym_strtab = strtab[shdr[sec_symtab].sh_link];
-                for(j = 0; j < shdr[i].sh_size/sizeof(reltab[0][0]); j++) {
+                sh_symtab  = sec_symtab->symtab;
+                sym_strtab = sec_symtab->link->strtab;
+                for (j = 0; j < sec->shdr.sh_size/sizeof(Elf32_Rel); j++) {
                         Elf32_Rel *rel;
                         Elf32_Sym *sym;
                         const char *name;
-                        rel = &reltab[i][j];
+                        rel = &sec->reltab[j];
                         sym = &sh_symtab[ELF32_R_SYM(rel->r_info)];
                         name = sym_name(sym_strtab, sym);
                         if (sym->st_shndx != SHN_ABS) {
@@ -456,26 +476,28 @@ static void walk_relocs(void (*visit)(Elf32_Rel *rel, Elf32_Sym *sym))
 {
         int i;
         /* Walk through the relocations */
-        for(i = 0; i < ehdr.e_shnum; i++) {
+        for (i = 0; i < ehdr.e_shnum; i++) {
                 char *sym_strtab;
                 Elf32_Sym *sh_symtab;
-                unsigned sec_applies, sec_symtab;
+                struct section *sec_applies, *sec_symtab;
                 int j;
-                if (shdr[i].sh_type != SHT_REL) {
+                struct section *sec = &secs[i];
+
+                if (sec->shdr.sh_type != SHT_REL) {
                         continue;
                 }
-                sec_symtab  = shdr[i].sh_link;
-                sec_applies = shdr[i].sh_info;
-                if (!(shdr[sec_applies].sh_flags & SHF_ALLOC)) {
+                sec_symtab  = sec->link;
+                sec_applies = &secs[sec->shdr.sh_info];
+                if (!(sec_applies->shdr.sh_flags & SHF_ALLOC)) {
                         continue;
                 }
-                sh_symtab = symtab[sec_symtab];
-                sym_strtab = strtab[shdr[sec_symtab].sh_link];
-                for(j = 0; j < shdr[i].sh_size/sizeof(reltab[0][0]); j++) {
+                sh_symtab = sec_symtab->symtab;
+                sym_strtab = sec->link->strtab;
+                for (j = 0; j < sec->shdr.sh_size/sizeof(Elf32_Rel); j++) {
                         Elf32_Rel *rel;
                         Elf32_Sym *sym;
                         unsigned r_type;
-                        rel = &reltab[i][j];
+                        rel = &sec->reltab[j];
                         sym = &sh_symtab[ELF32_R_SYM(rel->r_info)];
                         r_type = ELF32_R_TYPE(rel->r_info);
                         /* Don't visit relocations to absolute symbols */
@@ -539,7 +561,7 @@ static void emit_relocs(int as_text)
                  */
                 printf(".section \".data.reloc\",\"a\"\n");
                 printf(".balign 4\n");
-                for(i = 0; i < reloc_count; i++) {
+                for (i = 0; i < reloc_count; i++) {
                         printf("\t .long 0x%08lx\n", relocs[i]);
                 }
                 printf("\n");
@@ -550,7 +572,7 @@ static void emit_relocs(int as_text)
                 /* Print a stop */
                 printf("%c%c%c%c", buf[0], buf[1], buf[2], buf[3]);
                 /* Now print each relocation */
-                for(i = 0; i < reloc_count; i++) {
+                for (i = 0; i < reloc_count; i++) {
                         buf[0] = (relocs[i] >>  0) & 0xff;
                         buf[1] = (relocs[i] >>  8) & 0xff;
                         buf[2] = (relocs[i] >> 16) & 0xff;
@@ -577,7 +599,7 @@ int main(int argc, char **argv)
         show_absolute_relocs = 0;
         as_text = 0;
         fname = NULL;
-        for(i = 1; i < argc; i++) {
+        for (i = 1; i < argc; i++) {
                 char *arg = argv[i];
                 if (*arg == '-') {
                         if (strcmp(argv[1], "--abs-syms") == 0) {
diff --git a/arch/x86/boot/cpu.c b/arch/x86/boot/cpu.c
index 00e19edd852c..92d6fd73dc7d 100644
--- a/arch/x86/boot/cpu.c
+++ b/arch/x86/boot/cpu.c
@@ -28,6 +28,8 @@ static char *cpu_name(int level)
         if (level == 64) {
                 return "x86-64";
         } else {
+                if (level == 15)
+                        level = 6;
                 sprintf(buf, "i%d86", level);
                 return buf;
         }
diff --git a/arch/x86/boot/main.c b/arch/x86/boot/main.c
index 77569a4a3be1..2296164b54d2 100644
--- a/arch/x86/boot/main.c
+++ b/arch/x86/boot/main.c
@@ -165,6 +165,10 @@ void main(void)
         /* Set the video mode */
         set_video();
 
+        /* Parse command line for 'quiet' and pass it to decompressor. */
+        if (cmdline_find_option_bool("quiet"))
+                boot_params.hdr.loadflags |= QUIET_FLAG;
+
         /* Do the last things and invoke protected mode */
         go_to_protected_mode();
 }
diff --git a/arch/x86/boot/memory.c b/arch/x86/boot/memory.c
index acad32eb4290..53165c97336b 100644
--- a/arch/x86/boot/memory.c
+++ b/arch/x86/boot/memory.c
@@ -13,6 +13,7 @@
  */
 
 #include "boot.h"
+#include <linux/kernel.h>
 
 #define SMAP    0x534d4150      /* ASCII "SMAP" */
 
@@ -53,7 +54,7 @@ static int detect_memory_e820(void)
 
                 count++;
                 desc++;
-        } while (next && count < E820MAX);
+        } while (next && count < ARRAY_SIZE(boot_params.e820_map));
 
         return boot_params.e820_entries = count;
 }
diff --git a/arch/x86/boot/pmjump.S b/arch/x86/boot/pmjump.S
index ab049d40a884..141b6e20ed31 100644
--- a/arch/x86/boot/pmjump.S
+++ b/arch/x86/boot/pmjump.S
@@ -33,6 +33,8 @@ protected_mode_jump:
         movw    %cs, %bx
         shll    $4, %ebx
         addl    %ebx, 2f
+        jmp     1f                      # Short jump to serialize on 386/486
+1:
 
         movw    $__BOOT_DS, %cx
         movw    $__BOOT_TSS, %di
@@ -40,8 +42,6 @@ protected_mode_jump:
         movl    %cr0, %edx
         orb     $X86_CR0_PE, %dl        # Protected mode
         movl    %edx, %cr0
-        jmp     1f                      # Short jump to serialize on 386/486
-1:
 
         # Transition to 32-bit mode
         .byte   0x66, 0xea              # ljmpl opcode
diff --git a/arch/x86/boot/video-vga.c b/arch/x86/boot/video-vga.c
index 40ecb8d7688c..b939cb476dec 100644
--- a/arch/x86/boot/video-vga.c
+++ b/arch/x86/boot/video-vga.c
@@ -259,8 +259,7 @@ static int vga_probe(void)
         return mode_count[adapter];
 }
 
-__videocard video_vga =
-{
+__videocard video_vga = {
         .card_name      = "VGA",
         .probe          = vga_probe,
         .set_mode       = vga_set_mode,
diff --git a/arch/x86/configs/i386_defconfig b/arch/x86/configs/i386_defconfig
index ad7ddaaff588..9bc34e2033ec 100644
--- a/arch/x86/configs/i386_defconfig
+++ b/arch/x86/configs/i386_defconfig
@@ -1,54 +1,103 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.22-git14
-# Fri Jul 20 09:53:15 2007
+# Linux kernel version: 2.6.26-rc1
+# Sun May  4 19:59:02 2008
 #
+# CONFIG_64BIT is not set
 CONFIG_X86_32=y
+# CONFIG_X86_64 is not set
+CONFIG_X86=y
+CONFIG_DEFCONFIG_LIST="arch/x86/configs/i386_defconfig"
+# CONFIG_GENERIC_LOCKBREAK is not set
 CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CMOS_UPDATE=y
 CONFIG_CLOCKSOURCE_WATCHDOG=y
 CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
 CONFIG_LOCKDEP_SUPPORT=y
 CONFIG_STACKTRACE_SUPPORT=y
-CONFIG_SEMAPHORE_SLEEPERS=y
-CONFIG_X86=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_FAST_CMPXCHG_LOCAL=y
 CONFIG_MMU=y
 CONFIG_ZONE_DMA=y
-CONFIG_QUICKLIST=y
 CONFIG_GENERIC_ISA_DMA=y
 CONFIG_GENERIC_IOMAP=y
 CONFIG_GENERIC_BUG=y
 CONFIG_GENERIC_HWEIGHT=y
+# CONFIG_GENERIC_GPIO is not set
 CONFIG_ARCH_MAY_HAVE_PC_FDC=y
-CONFIG_DMI=y
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+# CONFIG_RWSEM_GENERIC_SPINLOCK is not set
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+# CONFIG_GENERIC_TIME_VSYSCALL is not set
+CONFIG_ARCH_HAS_CPU_RELAX=y
+CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
+CONFIG_HAVE_SETUP_PER_CPU_AREA=y
+# CONFIG_HAVE_CPUMASK_OF_CPU_MAP is not set
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# CONFIG_ZONE_DMA32 is not set
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+# CONFIG_AUDIT_ARCH is not set
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_PENDING_IRQ=y
+CONFIG_X86_SMP=y
+CONFIG_X86_32_SMP=y
+CONFIG_X86_HT=y
+CONFIG_X86_BIOS_REBOOT=y
+CONFIG_X86_TRAMPOLINE=y
+CONFIG_KTIME_SCALAR=y
 
 #
-# Code maturity level options
+# General setup
 #
 CONFIG_EXPERIMENTAL=y
 CONFIG_LOCK_KERNEL=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
 CONFIG_LOCALVERSION=""
-CONFIG_LOCALVERSION_AUTO=y
+# CONFIG_LOCALVERSION_AUTO is not set
 CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
 CONFIG_SYSVIPC_SYSCTL=y
 CONFIG_POSIX_MQUEUE=y
-# CONFIG_BSD_PROCESS_ACCT is not set
-# CONFIG_TASKSTATS is not set
-# CONFIG_USER_NS is not set
-# CONFIG_AUDIT is not set
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=18
-# CONFIG_CPUSETS is not set
-CONFIG_SYSFS_DEPRECATED=y
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_AUDIT=y
+CONFIG_AUDITSYSCALL=y
+CONFIG_AUDIT_TREE=y
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_CGROUP_NS=y
+# CONFIG_CGROUP_DEVICE is not set
+CONFIG_CPUSETS=y
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+# CONFIG_USER_SCHED is not set
+CONFIG_CGROUP_SCHED=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+# CONFIG_CGROUP_MEM_RES_CTLR is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+CONFIG_PROC_PID_CPUSET=y
 CONFIG_RELAY=y
+CONFIG_NAMESPACES=y
+CONFIG_UTS_NS=y
+CONFIG_IPC_NS=y
+CONFIG_USER_NS=y
+CONFIG_PID_NS=y
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
@@ -56,13 +105,15 @@ CONFIG_SYSCTL=y
 # CONFIG_EMBEDDED is not set
 CONFIG_UID16=y
 CONFIG_SYSCTL_SYSCALL=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_KALLSYMS=y
 CONFIG_KALLSYMS_ALL=y
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_KALLSYMS_EXTRA_PASS=y
 CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 CONFIG_ELF_CORE=y
+# CONFIG_COMPAT_BRK is not set
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_ANON_INODES=y
@@ -76,6 +127,17 @@ CONFIG_SLUB_DEBUG=y
 # CONFIG_SLAB is not set
 CONFIG_SLUB=y
 # CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+CONFIG_MARKERS=y
+# CONFIG_OPROFILE is not set
+CONFIG_HAVE_OPROFILE=y
+CONFIG_KPROBES=y
+CONFIG_KRETPROBES=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+# CONFIG_HAVE_DMA_ATTRS is not set
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
@@ -87,10 +149,10 @@ CONFIG_MODULE_FORCE_UNLOAD=y
 # CONFIG_KMOD is not set
 CONFIG_STOP_MACHINE=y
 CONFIG_BLOCK=y
-CONFIG_LBD=y
-# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LBD is not set
+CONFIG_BLK_DEV_IO_TRACE=y
 # CONFIG_LSF is not set
-# CONFIG_BLK_DEV_BSG is not set
+CONFIG_BLK_DEV_BSG=y
 
 #
 # IO Schedulers
@@ -103,7 +165,8 @@ CONFIG_IOSCHED_CFQ=y
 # CONFIG_DEFAULT_DEADLINE is not set
 CONFIG_DEFAULT_CFQ=y
 # CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_CLASSIC_RCU=y
 
 #
 # Processor type and features
@@ -111,18 +174,21 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
 CONFIG_TICK_ONESHOT=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
 CONFIG_SMP=y
-# CONFIG_X86_PC is not set
+CONFIG_X86_PC=y
 # CONFIG_X86_ELAN is not set
 # CONFIG_X86_VOYAGER is not set
 # CONFIG_X86_NUMAQ is not set
 # CONFIG_X86_SUMMIT is not set
 # CONFIG_X86_BIGSMP is not set
 # CONFIG_X86_VISWS is not set
-CONFIG_X86_GENERICARCH=y
+# CONFIG_X86_GENERICARCH is not set
 # CONFIG_X86_ES7000 is not set
-# CONFIG_PARAVIRT is not set
-CONFIG_X86_CYCLONE_TIMER=y
+# CONFIG_X86_RDC321X is not set
+# CONFIG_X86_VSMP is not set
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+# CONFIG_PARAVIRT_GUEST is not set
 # CONFIG_M386 is not set
 # CONFIG_M486 is not set
 # CONFIG_M586 is not set
@@ -130,9 +196,8 @@ CONFIG_X86_CYCLONE_TIMER=y
 # CONFIG_M586MMX is not set
 # CONFIG_M686 is not set
 # CONFIG_MPENTIUMII is not set
-CONFIG_MPENTIUMIII=y
+# CONFIG_MPENTIUMIII is not set
 # CONFIG_MPENTIUMM is not set
-# CONFIG_MCORE2 is not set
 # CONFIG_MPENTIUM4 is not set
 # CONFIG_MK6 is not set
 # CONFIG_MK7 is not set
@@ -147,14 +212,14 @@ CONFIG_MPENTIUMIII=y
 # CONFIG_MCYRIXIII is not set
 # CONFIG_MVIAC3_2 is not set
 # CONFIG_MVIAC7 is not set
-CONFIG_X86_GENERIC=y
+# CONFIG_MPSC is not set
+CONFIG_MCORE2=y
+# CONFIG_GENERIC_CPU is not set
+# CONFIG_X86_GENERIC is not set
+CONFIG_X86_CPU=y
 CONFIG_X86_CMPXCHG=y
-CONFIG_X86_L1_CACHE_SHIFT=7
+CONFIG_X86_L1_CACHE_SHIFT=6
 CONFIG_X86_XADD=y
-CONFIG_RWSEM_XCHGADD_ALGORITHM=y
-# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-CONFIG_GENERIC_CALIBRATE_DELAY=y
 CONFIG_X86_WP_WORKS_OK=y
 CONFIG_X86_INVLPG=y
 CONFIG_X86_BSWAP=y
@@ -162,106 +227,120 @@ CONFIG_X86_POPAD_OK=y
 CONFIG_X86_GOOD_APIC=y
 CONFIG_X86_INTEL_USERCOPY=y
 CONFIG_X86_USE_PPRO_CHECKSUM=y
+CONFIG_X86_P6_NOP=y
 CONFIG_X86_TSC=y
-CONFIG_X86_CMOV=y
-CONFIG_X86_MINIMUM_CPU_FAMILY=4
+CONFIG_X86_MINIMUM_CPU_FAMILY=6
+CONFIG_X86_DEBUGCTLMSR=y
 CONFIG_HPET_TIMER=y
 CONFIG_HPET_EMULATE_RTC=y
-CONFIG_NR_CPUS=32
-CONFIG_SCHED_SMT=y
+CONFIG_DMI=y
+# CONFIG_IOMMU_HELPER is not set
+CONFIG_NR_CPUS=4
+# CONFIG_SCHED_SMT is not set
 CONFIG_SCHED_MC=y
 # CONFIG_PREEMPT_NONE is not set
 CONFIG_PREEMPT_VOLUNTARY=y
 # CONFIG_PREEMPT is not set
-CONFIG_PREEMPT_BKL=y
 CONFIG_X86_LOCAL_APIC=y
 CONFIG_X86_IO_APIC=y
-CONFIG_X86_MCE=y
-CONFIG_X86_MCE_NONFATAL=y
-CONFIG_X86_MCE_P4THERMAL=y
+# CONFIG_X86_MCE is not set
 CONFIG_VM86=y
 # CONFIG_TOSHIBA is not set
 # CONFIG_I8K is not set
 # CONFIG_X86_REBOOTFIXUPS is not set
-CONFIG_MICROCODE=y
-CONFIG_MICROCODE_OLD_INTERFACE=y
+# CONFIG_MICROCODE is not set
 CONFIG_X86_MSR=y
 CONFIG_X86_CPUID=y
-
-#
-# Firmware Drivers
-#
-# CONFIG_EDD is not set
-# CONFIG_DELL_RBU is not set
-# CONFIG_DCDBAS is not set
-CONFIG_DMIID=y
 # CONFIG_NOHIGHMEM is not set
 CONFIG_HIGHMEM4G=y
 # CONFIG_HIGHMEM64G is not set
 CONFIG_PAGE_OFFSET=0xC0000000
 CONFIG_HIGHMEM=y
-CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_NEED_NODE_MEMMAP_SIZE=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
 CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_FLATMEM_MANUAL=y
+# CONFIG_FLATMEM_MANUAL is not set
 # CONFIG_DISCONTIGMEM_MANUAL is not set
-# CONFIG_SPARSEMEM_MANUAL is not set
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_SPARSEMEM=y
+CONFIG_HAVE_MEMORY_PRESENT=y
+CONFIG_SPARSEMEM_STATIC=y
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+
+#
+# Memory hotplug is currently incompatible with Software Suspend
+#
+CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
 CONFIG_RESOURCES_64BIT=y
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_BOUNCE=y
-CONFIG_NR_QUICK=1
 CONFIG_VIRT_TO_BUS=y
 # CONFIG_HIGHPTE is not set
 # CONFIG_MATH_EMULATION is not set
 CONFIG_MTRR=y
-# CONFIG_EFI is not set
+# CONFIG_X86_PAT is not set
+CONFIG_EFI=y
 # CONFIG_IRQBALANCE is not set
 CONFIG_SECCOMP=y
 # CONFIG_HZ_100 is not set
-CONFIG_HZ_250=y
+# CONFIG_HZ_250 is not set
 # CONFIG_HZ_300 is not set
-# CONFIG_HZ_1000 is not set
-CONFIG_HZ=250
-# CONFIG_KEXEC is not set
-# CONFIG_CRASH_DUMP is not set
-CONFIG_PHYSICAL_START=0x100000
-# CONFIG_RELOCATABLE is not set
-CONFIG_PHYSICAL_ALIGN=0x100000
-# CONFIG_HOTPLUG_CPU is not set
-CONFIG_COMPAT_VDSO=y
+CONFIG_HZ_1000=y
+CONFIG_HZ=1000
+CONFIG_SCHED_HRTICK=y
+CONFIG_KEXEC=y
+CONFIG_CRASH_DUMP=y
+CONFIG_PHYSICAL_START=0x1000000
+CONFIG_RELOCATABLE=y
+CONFIG_PHYSICAL_ALIGN=0x200000
+CONFIG_HOTPLUG_CPU=y
+# CONFIG_COMPAT_VDSO is not set
 CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
 
 #
-# Power management options (ACPI, APM)
+# Power management options
 #
 CONFIG_PM=y
-CONFIG_PM_LEGACY=y
-# CONFIG_PM_DEBUG is not set
-
-#
-# ACPI (Advanced Configuration and Power Interface) Support
-#
+CONFIG_PM_DEBUG=y
+# CONFIG_PM_VERBOSE is not set
+CONFIG_CAN_PM_TRACE=y
+CONFIG_PM_TRACE=y
+CONFIG_PM_TRACE_RTC=y
+CONFIG_PM_SLEEP_SMP=y
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_HIBERNATION=y
+CONFIG_PM_STD_PARTITION=""
 CONFIG_ACPI=y
+CONFIG_ACPI_SLEEP=y
 CONFIG_ACPI_PROCFS=y
+CONFIG_ACPI_PROCFS_POWER=y
+CONFIG_ACPI_SYSFS_POWER=y
+CONFIG_ACPI_PROC_EVENT=y
 CONFIG_ACPI_AC=y
 CONFIG_ACPI_BATTERY=y
 CONFIG_ACPI_BUTTON=y
 CONFIG_ACPI_FAN=y
-# CONFIG_ACPI_DOCK is not set
+CONFIG_ACPI_DOCK=y
+# CONFIG_ACPI_BAY is not set
 CONFIG_ACPI_PROCESSOR=y
+CONFIG_ACPI_HOTPLUG_CPU=y
 CONFIG_ACPI_THERMAL=y
+# CONFIG_ACPI_WMI is not set
 # CONFIG_ACPI_ASUS is not set
 # CONFIG_ACPI_TOSHIBA is not set
-CONFIG_ACPI_BLACKLIST_YEAR=2001
-CONFIG_ACPI_DEBUG=y
+# CONFIG_ACPI_CUSTOM_DSDT is not set
+CONFIG_ACPI_BLACKLIST_YEAR=0
+# CONFIG_ACPI_DEBUG is not set
 CONFIG_ACPI_EC=y
 CONFIG_ACPI_POWER=y
 CONFIG_ACPI_SYSTEM=y
 CONFIG_X86_PM_TIMER=y
-# CONFIG_ACPI_CONTAINER is not set
+CONFIG_ACPI_CONTAINER=y
 # CONFIG_ACPI_SBS is not set
 # CONFIG_APM is not set
 
@@ -271,15 +350,17 @@ CONFIG_X86_PM_TIMER=y
 CONFIG_CPU_FREQ=y
 CONFIG_CPU_FREQ_TABLE=y
 CONFIG_CPU_FREQ_DEBUG=y
-CONFIG_CPU_FREQ_STAT=y
-# CONFIG_CPU_FREQ_STAT_DETAILS is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_STAT is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
 CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
 # CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
 CONFIG_CPU_FREQ_GOV_USERSPACE=y
 CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
 
 #
 # CPUFreq processor drivers
@@ -287,8 +368,7 @@ CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
 CONFIG_X86_ACPI_CPUFREQ=y
 # CONFIG_X86_POWERNOW_K6 is not set
 # CONFIG_X86_POWERNOW_K7 is not set
-CONFIG_X86_POWERNOW_K8=y
-CONFIG_X86_POWERNOW_K8_ACPI=y
+# CONFIG_X86_POWERNOW_K8 is not set
 # CONFIG_X86_GX_SUSPMOD is not set
 # CONFIG_X86_SPEEDSTEP_CENTRINO is not set
 # CONFIG_X86_SPEEDSTEP_ICH is not set
@@ -302,43 +382,72 @@ CONFIG_X86_POWERNOW_K8_ACPI=y
 #
 # shared options
 #
-CONFIG_X86_ACPI_CPUFREQ_PROC_INTF=y
+# CONFIG_X86_ACPI_CPUFREQ_PROC_INTF is not set
 # CONFIG_X86_SPEEDSTEP_LIB is not set
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_IDLE_GOV_MENU=y
 
 #
-# Bus options (PCI, PCMCIA, EISA, MCA, ISA)
+# Bus options (PCI etc.)
 #
 CONFIG_PCI=y
 # CONFIG_PCI_GOBIOS is not set
 # CONFIG_PCI_GOMMCONFIG is not set
 # CONFIG_PCI_GODIRECT is not set
 CONFIG_PCI_GOANY=y
+# CONFIG_PCI_GOOLPC is not set
 CONFIG_PCI_BIOS=y
 CONFIG_PCI_DIRECT=y
 CONFIG_PCI_MMCONFIG=y
-# CONFIG_PCIEPORTBUS is not set
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCIEPORTBUS=y
+# CONFIG_HOTPLUG_PCI_PCIE is not set
+CONFIG_PCIEAER=y
+# CONFIG_PCIEASPM is not set
 CONFIG_ARCH_SUPPORTS_MSI=y
 CONFIG_PCI_MSI=y
+# CONFIG_PCI_LEGACY is not set
 # CONFIG_PCI_DEBUG is not set
-# CONFIG_HT_IRQ is not set
+CONFIG_HT_IRQ=y
 CONFIG_ISA_DMA_API=y
 # CONFIG_ISA is not set
 # CONFIG_MCA is not set
 # CONFIG_SCx200 is not set
+# CONFIG_OLPC is not set
 CONFIG_K8_NB=y
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
-# CONFIG_PCCARD is not set
-# CONFIG_HOTPLUG_PCI is not set
-
-#
-# Executable file formats
+CONFIG_PCCARD=y
+# CONFIG_PCMCIA_DEBUG is not set
+CONFIG_PCMCIA=y
+CONFIG_PCMCIA_LOAD_CIS=y
+CONFIG_PCMCIA_IOCTL=y
+CONFIG_CARDBUS=y
+
+#
+# PC-card bridges
+#
+CONFIG_YENTA=y
+CONFIG_YENTA_O2=y
+CONFIG_YENTA_RICOH=y
+CONFIG_YENTA_TI=y
+CONFIG_YENTA_ENE_TUNE=y
+CONFIG_YENTA_TOSHIBA=y
+# CONFIG_PD6729 is not set
+# CONFIG_I82092 is not set
+CONFIG_PCCARD_NONSTATIC=y
+CONFIG_HOTPLUG_PCI=y
+# CONFIG_HOTPLUG_PCI_FAKE is not set
+# CONFIG_HOTPLUG_PCI_IBM is not set
+# CONFIG_HOTPLUG_PCI_ACPI is not set
+# CONFIG_HOTPLUG_PCI_CPCI is not set
+# CONFIG_HOTPLUG_PCI_SHPC is not set
+
+#
+# Executable file formats / Emulations
 #
 CONFIG_BINFMT_ELF=y
 # CONFIG_BINFMT_AOUT is not set
-# CONFIG_BINFMT_MISC is not set
+CONFIG_BINFMT_MISC=y
 
 #
 # Networking
@@ -349,59 +458,142 @@ CONFIG_NET=y
 # Networking options
 #
 CONFIG_PACKET=y
-# CONFIG_PACKET_MMAP is not set
+CONFIG_PACKET_MMAP=y
 CONFIG_UNIX=y
 CONFIG_XFRM=y
-# CONFIG_XFRM_USER is not set
+CONFIG_XFRM_USER=y
 # CONFIG_XFRM_SUB_POLICY is not set
 # CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
 CONFIG_IP_MULTICAST=y
-# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ASK_IP_FIB_HASH=y
+# CONFIG_IP_FIB_TRIE is not set
 CONFIG_IP_FIB_HASH=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_IP_PNP_BOOTP is not set
-# CONFIG_IP_PNP_RARP is not set
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+# CONFIG_IP_PNP is not set
 # CONFIG_NET_IPIP is not set
 # CONFIG_NET_IPGRE is not set
-# CONFIG_IP_MROUTE is not set
+CONFIG_IP_MROUTE=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
 # CONFIG_ARPD is not set
-# CONFIG_SYN_COOKIES is not set
+CONFIG_SYN_COOKIES=y
 # CONFIG_INET_AH is not set
 # CONFIG_INET_ESP is not set
 # CONFIG_INET_IPCOMP is not set
 # CONFIG_INET_XFRM_TUNNEL is not set
 CONFIG_INET_TUNNEL=y
-CONFIG_INET_XFRM_MODE_TRANSPORT=y
-CONFIG_INET_XFRM_MODE_TUNNEL=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
 # CONFIG_INET_XFRM_MODE_BEET is not set
-CONFIG_INET_DIAG=y
-CONFIG_INET_TCP_DIAG=y
-# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_INET_LRO=y
+# CONFIG_INET_DIAG is not set
+CONFIG_TCP_CONG_ADVANCED=y
+# CONFIG_TCP_CONG_BIC is not set
 CONFIG_TCP_CONG_CUBIC=y
+# CONFIG_TCP_CONG_WESTWOOD is not set
+# CONFIG_TCP_CONG_HTCP is not set
+# CONFIG_TCP_CONG_HSTCP is not set
+# CONFIG_TCP_CONG_HYBLA is not set
+# CONFIG_TCP_CONG_VEGAS is not set
+# CONFIG_TCP_CONG_SCALABLE is not set
+# CONFIG_TCP_CONG_LP is not set
+# CONFIG_TCP_CONG_VENO is not set
+# CONFIG_TCP_CONG_YEAH is not set
+# CONFIG_TCP_CONG_ILLINOIS is not set
+# CONFIG_DEFAULT_BIC is not set
+CONFIG_DEFAULT_CUBIC=y
+# CONFIG_DEFAULT_HTCP is not set
+# CONFIG_DEFAULT_VEGAS is not set
+# CONFIG_DEFAULT_WESTWOOD is not set
+# CONFIG_DEFAULT_RENO is not set
 CONFIG_DEFAULT_TCP_CONG="cubic"
-# CONFIG_TCP_MD5SIG is not set
+CONFIG_TCP_MD5SIG=y
+# CONFIG_IP_VS is not set
 CONFIG_IPV6=y
 # CONFIG_IPV6_PRIVACY is not set
 # CONFIG_IPV6_ROUTER_PREF is not set
 # CONFIG_IPV6_OPTIMISTIC_DAD is not set
-# CONFIG_INET6_AH is not set
-# CONFIG_INET6_ESP is not set
+CONFIG_INET6_AH=y
+CONFIG_INET6_ESP=y
 # CONFIG_INET6_IPCOMP is not set
 # CONFIG_IPV6_MIP6 is not set
 # CONFIG_INET6_XFRM_TUNNEL is not set
 # CONFIG_INET6_TUNNEL is not set
 CONFIG_INET6_XFRM_MODE_TRANSPORT=y
 CONFIG_INET6_XFRM_MODE_TUNNEL=y
-# CONFIG_INET6_XFRM_MODE_BEET is not set
+CONFIG_INET6_XFRM_MODE_BEET=y
 # CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
 CONFIG_IPV6_SIT=y
+CONFIG_IPV6_NDISC_NODETYPE=y
 # CONFIG_IPV6_TUNNEL is not set
 # CONFIG_IPV6_MULTIPLE_TABLES is not set
-# CONFIG_NETWORK_SECMARK is not set
-# CONFIG_NETFILTER is not set
+# CONFIG_IPV6_MROUTE is not set
+CONFIG_NETLABEL=y
+CONFIG_NETWORK_SECMARK=y
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+# CONFIG_NETFILTER_ADVANCED is not set
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=y
+CONFIG_NETFILTER_NETLINK_LOG=y
+CONFIG_NF_CONNTRACK=y
+CONFIG_NF_CONNTRACK_SECMARK=y
+CONFIG_NF_CONNTRACK_FTP=y
+CONFIG_NF_CONNTRACK_IRC=y
+CONFIG_NF_CONNTRACK_SIP=y
+CONFIG_NF_CT_NETLINK=y
+CONFIG_NETFILTER_XTABLES=y
+CONFIG_NETFILTER_XT_TARGET_MARK=y
+CONFIG_NETFILTER_XT_TARGET_NFLOG=y
+CONFIG_NETFILTER_XT_TARGET_SECMARK=y
+CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=y
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=y
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
+CONFIG_NETFILTER_XT_MATCH_MARK=y
+CONFIG_NETFILTER_XT_MATCH_POLICY=y
+CONFIG_NETFILTER_XT_MATCH_STATE=y
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_CONNTRACK_IPV4=y
+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_IP_NF_TARGET_LOG=y
+CONFIG_IP_NF_TARGET_ULOG=y
+CONFIG_NF_NAT=y
+CONFIG_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+CONFIG_NF_NAT_FTP=y
+CONFIG_NF_NAT_IRC=y
+# CONFIG_NF_NAT_TFTP is not set
+# CONFIG_NF_NAT_AMANDA is not set
+# CONFIG_NF_NAT_PPTP is not set
+# CONFIG_NF_NAT_H323 is not set
+CONFIG_NF_NAT_SIP=y
+CONFIG_IP_NF_MANGLE=y
+
+#
+# IPv6: Netfilter Configuration
+#
+CONFIG_NF_CONNTRACK_IPV6=y
+CONFIG_IP6_NF_IPTABLES=y
+CONFIG_IP6_NF_MATCH_IPV6HEADER=y
+CONFIG_IP6_NF_FILTER=y
+CONFIG_IP6_NF_TARGET_LOG=y
+CONFIG_IP6_NF_TARGET_REJECT=y
+CONFIG_IP6_NF_MANGLE=y
 # CONFIG_IP_DCCP is not set
 # CONFIG_IP_SCTP is not set
 # CONFIG_TIPC is not set
@@ -409,6 +601,7 @@ CONFIG_IPV6_SIT=y
 # CONFIG_BRIDGE is not set
 # CONFIG_VLAN_8021Q is not set
 # CONFIG_DECNET is not set
+CONFIG_LLC=y
 # CONFIG_LLC2 is not set
 # CONFIG_IPX is not set
 # CONFIG_ATALK is not set
@@ -416,28 +609,99 @@ CONFIG_IPV6_SIT=y
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
-# CONFIG_NET_SCHED is not set
+CONFIG_NET_SCHED=y
+
+#
+# Queueing/Scheduling
+#
+# CONFIG_NET_SCH_CBQ is not set
+# CONFIG_NET_SCH_HTB is not set
+# CONFIG_NET_SCH_HFSC is not set
+# CONFIG_NET_SCH_PRIO is not set
+# CONFIG_NET_SCH_RR is not set
+# CONFIG_NET_SCH_RED is not set
+# CONFIG_NET_SCH_SFQ is not set
+# CONFIG_NET_SCH_TEQL is not set
+# CONFIG_NET_SCH_TBF is not set
+# CONFIG_NET_SCH_GRED is not set
+# CONFIG_NET_SCH_DSMARK is not set
+# CONFIG_NET_SCH_NETEM is not set
+# CONFIG_NET_SCH_INGRESS is not set
+
+#
+# Classification
+#
+CONFIG_NET_CLS=y
+# CONFIG_NET_CLS_BASIC is not set
+# CONFIG_NET_CLS_TCINDEX is not set
+# CONFIG_NET_CLS_ROUTE4 is not set
+# CONFIG_NET_CLS_FW is not set
+# CONFIG_NET_CLS_U32 is not set
+# CONFIG_NET_CLS_RSVP is not set
+# CONFIG_NET_CLS_RSVP6 is not set
+# CONFIG_NET_CLS_FLOW is not set
+CONFIG_NET_EMATCH=y
+CONFIG_NET_EMATCH_STACK=32
+# CONFIG_NET_EMATCH_CMP is not set
+# CONFIG_NET_EMATCH_NBYTE is not set
+# CONFIG_NET_EMATCH_U32 is not set
+# CONFIG_NET_EMATCH_META is not set
+# CONFIG_NET_EMATCH_TEXT is not set
+CONFIG_NET_CLS_ACT=y
+# CONFIG_NET_ACT_POLICE is not set
+# CONFIG_NET_ACT_GACT is not set
+# CONFIG_NET_ACT_MIRRED is not set
+# CONFIG_NET_ACT_IPT is not set
+# CONFIG_NET_ACT_NAT is not set
+# CONFIG_NET_ACT_PEDIT is not set
+# CONFIG_NET_ACT_SIMP is not set
+CONFIG_NET_SCH_FIFO=y
 
 #
 # Network testing
 #
 # CONFIG_NET_PKTGEN is not set
 # CONFIG_NET_TCPPROBE is not set
-# CONFIG_HAMRADIO is not set
+CONFIG_HAMRADIO=y
+
+#
+# Packet Radio protocols
+#
+# CONFIG_AX25 is not set
+# CONFIG_CAN is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
 # CONFIG_AF_RXRPC is not set
+CONFIG_FIB_RULES=y
 
 #
 # Wireless
 #
-# CONFIG_CFG80211 is not set
-# CONFIG_WIRELESS_EXT is not set
-# CONFIG_MAC80211 is not set
+CONFIG_CFG80211=y
+CONFIG_NL80211=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_MAC80211=y
+
+#
+# Rate control algorithm selection
+#
+CONFIG_MAC80211_RC_DEFAULT_PID=y
+# CONFIG_MAC80211_RC_DEFAULT_NONE is not set
+
+#
+# Selecting 'y' for an algorithm will
+#
+
+#
+# build the algorithm into mac80211.
+#
+CONFIG_MAC80211_RC_DEFAULT="pid"
+CONFIG_MAC80211_RC_PID=y
+# CONFIG_MAC80211_MESH is not set
+CONFIG_MAC80211_LEDS=y
+# CONFIG_MAC80211_DEBUGFS is not set
+# CONFIG_MAC80211_DEBUG_PACKET_ALIGNMENT is not set
+# CONFIG_MAC80211_DEBUG is not set
 # CONFIG_IEEE80211 is not set
 # CONFIG_RFKILL is not set
 # CONFIG_NET_9P is not set
@@ -449,13 +713,15 @@ CONFIG_IPV6_SIT=y
 #
 # Generic Driver Options
 #
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 CONFIG_FW_LOADER=y
 # CONFIG_DEBUG_DRIVER is not set
-# CONFIG_DEBUG_DEVRES is not set
+CONFIG_DEBUG_DEVRES=y
 # CONFIG_SYS_HYPERVISOR is not set
-# CONFIG_CONNECTOR is not set
+CONFIG_CONNECTOR=y
+CONFIG_PROC_EVENTS=y
 # CONFIG_MTD is not set
 # CONFIG_PARPORT is not set
 CONFIG_PNP=y
@@ -466,7 +732,7 @@ CONFIG_PNP=y
 #
 CONFIG_PNPACPI=y
 CONFIG_BLK_DEV=y
-CONFIG_BLK_DEV_FD=y
+# CONFIG_BLK_DEV_FD is not set
 # CONFIG_BLK_CPQ_DA is not set
 # CONFIG_BLK_CPQ_CISS_DA is not set
 # CONFIG_BLK_DEV_DAC960 is not set
@@ -479,8 +745,8 @@ CONFIG_BLK_DEV_LOOP=y
 # CONFIG_BLK_DEV_UB is not set
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+CONFIG_BLK_DEV_RAM_SIZE=16384
+# CONFIG_BLK_DEV_XIP is not set
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
 CONFIG_MISC_DEVICES=y
@@ -489,73 +755,17 @@ CONFIG_MISC_DEVICES=y
 # CONFIG_EEPROM_93CX6 is not set
 # CONFIG_SGI_IOC4 is not set
 # CONFIG_TIFM_CORE is not set
+# CONFIG_ACER_WMI is not set
+# CONFIG_ASUS_LAPTOP is not set
+# CONFIG_FUJITSU_LAPTOP is not set
+# CONFIG_TC1100_WMI is not set
+# CONFIG_MSI_LAPTOP is not set
 # CONFIG_SONY_LAPTOP is not set
 # CONFIG_THINKPAD_ACPI is not set
-CONFIG_IDE=y
-CONFIG_BLK_DEV_IDE=y
-
-#
-# Please see Documentation/ide.txt for help/info on IDE drives
-#
-# CONFIG_BLK_DEV_IDE_SATA is not set
-# CONFIG_BLK_DEV_HD_IDE is not set
-CONFIG_BLK_DEV_IDEDISK=y
-CONFIG_IDEDISK_MULTI_MODE=y
-CONFIG_BLK_DEV_IDECD=y
-# CONFIG_BLK_DEV_IDETAPE is not set
-# CONFIG_BLK_DEV_IDEFLOPPY is not set
-# CONFIG_BLK_DEV_IDESCSI is not set
-CONFIG_BLK_DEV_IDEACPI=y
-# CONFIG_IDE_TASK_IOCTL is not set
-CONFIG_IDE_PROC_FS=y
-
-#
-# IDE chipset support/bugfixes
-#
-CONFIG_IDE_GENERIC=y
-# CONFIG_BLK_DEV_CMD640 is not set
-# CONFIG_BLK_DEV_IDEPNP is not set
-CONFIG_BLK_DEV_IDEPCI=y
-# CONFIG_IDEPCI_SHARE_IRQ is not set
-CONFIG_IDEPCI_PCIBUS_ORDER=y
-# CONFIG_BLK_DEV_OFFBOARD is not set
-# CONFIG_BLK_DEV_GENERIC is not set
-# CONFIG_BLK_DEV_OPTI621 is not set
-# CONFIG_BLK_DEV_RZ1000 is not set
-CONFIG_BLK_DEV_IDEDMA_PCI=y
-# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
-# CONFIG_IDEDMA_ONLYDISK is not set
-# CONFIG_BLK_DEV_AEC62XX is not set
-# CONFIG_BLK_DEV_ALI15X3 is not set
-CONFIG_BLK_DEV_AMD74XX=y
-# CONFIG_BLK_DEV_ATIIXP is not set
-# CONFIG_BLK_DEV_CMD64X is not set
-# CONFIG_BLK_DEV_TRIFLEX is not set
-# CONFIG_BLK_DEV_CY82C693 is not set
-# CONFIG_BLK_DEV_CS5520 is not set
-# CONFIG_BLK_DEV_CS5530 is not set
-# CONFIG_BLK_DEV_CS5535 is not set
-# CONFIG_BLK_DEV_HPT34X is not set
-# CONFIG_BLK_DEV_HPT366 is not set
-# CONFIG_BLK_DEV_JMICRON is not set
-# CONFIG_BLK_DEV_SC1200 is not set
-CONFIG_BLK_DEV_PIIX=y
-# CONFIG_BLK_DEV_IT8213 is not set
-# CONFIG_BLK_DEV_IT821X is not set
-# CONFIG_BLK_DEV_NS87415 is not set
-# CONFIG_BLK_DEV_PDC202XX_OLD is not set
-# CONFIG_BLK_DEV_PDC202XX_NEW is not set
-# CONFIG_BLK_DEV_SVWKS is not set
-# CONFIG_BLK_DEV_SIIMAGE is not set
-# CONFIG_BLK_DEV_SIS5513 is not set
-# CONFIG_BLK_DEV_SLC90E66 is not set
-# CONFIG_BLK_DEV_TRM290 is not set
-# CONFIG_BLK_DEV_VIA82CXXX is not set
-# CONFIG_BLK_DEV_TC86C001 is not set
-# CONFIG_IDE_ARM is not set
-CONFIG_BLK_DEV_IDEDMA=y
-# CONFIG_IDEDMA_IVB is not set
-# CONFIG_BLK_DEV_HD is not set
+# CONFIG_INTEL_MENLOW is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
 
 #
 # SCSI device support
@@ -564,8 +774,8 @@ CONFIG_BLK_DEV_IDEDMA=y
 CONFIG_SCSI=y
 CONFIG_SCSI_DMA=y
 # CONFIG_SCSI_TGT is not set
-CONFIG_SCSI_NETLINK=y
-# CONFIG_SCSI_PROC_FS is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
 
 #
 # SCSI support type (disk, tape, CD-ROM)
@@ -574,7 +784,7 @@ CONFIG_BLK_DEV_SD=y
 # CONFIG_CHR_DEV_ST is not set
 # CONFIG_CHR_DEV_OSST is not set
 CONFIG_BLK_DEV_SR=y
-# CONFIG_BLK_DEV_SR_VENDOR is not set
+CONFIG_BLK_DEV_SR_VENDOR=y
 CONFIG_CHR_DEV_SG=y
 # CONFIG_CHR_DEV_SCH is not set
 
@@ -582,7 +792,7 @@ CONFIG_CHR_DEV_SG=y
 # Some SCSI devices (e.g. CD jukebox) support multiple LUNs
 #
 # CONFIG_SCSI_MULTI_LUN is not set
-# CONFIG_SCSI_CONSTANTS is not set
+CONFIG_SCSI_CONSTANTS=y
 # CONFIG_SCSI_LOGGING is not set
 # CONFIG_SCSI_SCAN_ASYNC is not set
 CONFIG_SCSI_WAIT_SCAN=m
@@ -591,81 +801,37 @@ CONFIG_SCSI_WAIT_SCAN=m
 # SCSI Transports
 #
 CONFIG_SCSI_SPI_ATTRS=y
-CONFIG_SCSI_FC_ATTRS=y
+# CONFIG_SCSI_FC_ATTRS is not set
 # CONFIG_SCSI_ISCSI_ATTRS is not set
 # CONFIG_SCSI_SAS_ATTRS is not set
 # CONFIG_SCSI_SAS_LIBSAS is not set
-
-#
-# SCSI low-level drivers
-#
-# CONFIG_ISCSI_TCP is not set
-CONFIG_BLK_DEV_3W_XXXX_RAID=y
-# CONFIG_SCSI_3W_9XXX is not set
-# CONFIG_SCSI_ACARD is not set
-# CONFIG_SCSI_AACRAID is not set
-CONFIG_SCSI_AIC7XXX=y
-CONFIG_AIC7XXX_CMDS_PER_DEVICE=32
-CONFIG_AIC7XXX_RESET_DELAY_MS=5000
-CONFIG_AIC7XXX_DEBUG_ENABLE=y
-CONFIG_AIC7XXX_DEBUG_MASK=0
-CONFIG_AIC7XXX_REG_PRETTY_PRINT=y
-# CONFIG_SCSI_AIC7XXX_OLD is not set
-CONFIG_SCSI_AIC79XX=y
-CONFIG_AIC79XX_CMDS_PER_DEVICE=32
-CONFIG_AIC79XX_RESET_DELAY_MS=4000
-# CONFIG_AIC79XX_DEBUG_ENABLE is not set
-CONFIG_AIC79XX_DEBUG_MASK=0
-# CONFIG_AIC79XX_REG_PRETTY_PRINT is not set
-# CONFIG_SCSI_AIC94XX is not set
-# CONFIG_SCSI_DPT_I2O is not set
-# CONFIG_SCSI_ADVANSYS is not set
-# CONFIG_SCSI_ARCMSR is not set
-# CONFIG_MEGARAID_NEWGEN is not set
-# CONFIG_MEGARAID_LEGACY is not set
-# CONFIG_MEGARAID_SAS is not set
-# CONFIG_SCSI_HPTIOP is not set
-# CONFIG_SCSI_BUSLOGIC is not set
-# CONFIG_SCSI_DMX3191D is not set
-# CONFIG_SCSI_EATA is not set
-# CONFIG_SCSI_FUTURE_DOMAIN is not set
-# CONFIG_SCSI_GDTH is not set
-# CONFIG_SCSI_IPS is not set
-# CONFIG_SCSI_INITIO is not set
-# CONFIG_SCSI_INIA100 is not set
-# CONFIG_SCSI_STEX is not set
-# CONFIG_SCSI_SYM53C8XX_2 is not set
-# CONFIG_SCSI_IPR is not set
-# CONFIG_SCSI_QLOGIC_1280 is not set
-# CONFIG_SCSI_QLA_FC is not set
-# CONFIG_SCSI_QLA_ISCSI is not set
-# CONFIG_SCSI_LPFC is not set
-# CONFIG_SCSI_DC395x is not set
-# CONFIG_SCSI_DC390T is not set
-# CONFIG_SCSI_NSP32 is not set
-# CONFIG_SCSI_DEBUG is not set
-# CONFIG_SCSI_SRP is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
 CONFIG_ATA=y
 # CONFIG_ATA_NONSTANDARD is not set
 CONFIG_ATA_ACPI=y
+CONFIG_SATA_PMP=y
 CONFIG_SATA_AHCI=y
-CONFIG_SATA_SVW=y
+# CONFIG_SATA_SIL24 is not set
+CONFIG_ATA_SFF=y
+# CONFIG_SATA_SVW is not set
 CONFIG_ATA_PIIX=y
 # CONFIG_SATA_MV is not set
-CONFIG_SATA_NV=y
+# CONFIG_SATA_NV is not set
 # CONFIG_PDC_ADMA is not set
 # CONFIG_SATA_QSTOR is not set
 # CONFIG_SATA_PROMISE is not set
 # CONFIG_SATA_SX4 is not set
-CONFIG_SATA_SIL=y
-# CONFIG_SATA_SIL24 is not set
+# CONFIG_SATA_SIL is not set
 # CONFIG_SATA_SIS is not set
 # CONFIG_SATA_ULI is not set
-CONFIG_SATA_VIA=y
+# CONFIG_SATA_VIA is not set
 # CONFIG_SATA_VITESSE is not set
 # CONFIG_SATA_INIC162X is not set
+# CONFIG_PATA_ACPI is not set
 # CONFIG_PATA_ALI is not set
-# CONFIG_PATA_AMD is not set
+CONFIG_PATA_AMD=y
 # CONFIG_PATA_ARTOP is not set
 # CONFIG_PATA_ATIIXP is not set
 # CONFIG_PATA_CMD640_PCI is not set
@@ -673,6 +839,7 @@ CONFIG_SATA_VIA=y
 # CONFIG_PATA_CS5520 is not set
 # CONFIG_PATA_CS5530 is not set
 # CONFIG_PATA_CS5535 is not set
+# CONFIG_PATA_CS5536 is not set
 # CONFIG_PATA_CYPRESS is not set
 # CONFIG_PATA_EFAR is not set
 # CONFIG_ATA_GENERIC is not set
@@ -686,11 +853,14 @@ CONFIG_SATA_VIA=y
 # CONFIG_PATA_TRIFLEX is not set
 # CONFIG_PATA_MARVELL is not set
 # CONFIG_PATA_MPIIX is not set
-# CONFIG_PATA_OLDPIIX is not set
+CONFIG_PATA_OLDPIIX=y
 # CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
 # CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_NS87415 is not set
 # CONFIG_PATA_OPTI is not set
 # CONFIG_PATA_OPTIDMA is not set
+# CONFIG_PATA_PCMCIA is not set
 # CONFIG_PATA_PDC_OLD is not set
 # CONFIG_PATA_RADISYS is not set
 # CONFIG_PATA_RZ1000 is not set
@@ -702,65 +872,42 @@ CONFIG_SATA_VIA=y
 # CONFIG_PATA_VIA is not set
 # CONFIG_PATA_WINBOND is not set
 CONFIG_MD=y
-# CONFIG_BLK_DEV_MD is not set
+CONFIG_BLK_DEV_MD=y
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID10 is not set
+# CONFIG_MD_RAID456 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_MD_FAULTY is not set
 CONFIG_BLK_DEV_DM=y
 # CONFIG_DM_DEBUG is not set
 # CONFIG_DM_CRYPT is not set
 # CONFIG_DM_SNAPSHOT is not set
-# CONFIG_DM_MIRROR is not set
-# CONFIG_DM_ZERO is not set
+CONFIG_DM_MIRROR=y
+CONFIG_DM_ZERO=y
 # CONFIG_DM_MULTIPATH is not set
 # CONFIG_DM_DELAY is not set
-
-#
-# Fusion MPT device support
-#
-CONFIG_FUSION=y
-CONFIG_FUSION_SPI=y
-# CONFIG_FUSION_FC is not set
-# CONFIG_FUSION_SAS is not set
-CONFIG_FUSION_MAX_SGE=128
-# CONFIG_FUSION_CTL is not set
+# CONFIG_DM_UEVENT is not set
+# CONFIG_FUSION is not set
 
 #
 # IEEE 1394 (FireWire) support
 #
 # CONFIG_FIREWIRE is not set
-CONFIG_IEEE1394=y
-
-#
-# Subsystem Options
-#
-# CONFIG_IEEE1394_VERBOSEDEBUG is not set
-
-#
-# Controllers
-#
-
-#
-# Texas Instruments PCILynx requires I2C
-#
-CONFIG_IEEE1394_OHCI1394=y
-
-#
-# Protocols
-#
-# CONFIG_IEEE1394_VIDEO1394 is not set
-# CONFIG_IEEE1394_SBP2 is not set
-# CONFIG_IEEE1394_ETH1394_ROM_ENTRY is not set
-# CONFIG_IEEE1394_ETH1394 is not set
-# CONFIG_IEEE1394_DV1394 is not set
-CONFIG_IEEE1394_RAWIO=y
+# CONFIG_IEEE1394 is not set
 # CONFIG_I2O is not set
 CONFIG_MACINTOSH_DRIVERS=y
-# CONFIG_MAC_EMUMOUSEBTN is not set
+CONFIG_MAC_EMUMOUSEBTN=y
 CONFIG_NETDEVICES=y
-CONFIG_NETDEVICES_MULTIQUEUE=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_IFB is not set
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
+# CONFIG_VETH is not set
 # CONFIG_NET_SB1000 is not set
 # CONFIG_ARCNET is not set
 # CONFIG_PHYLIB is not set
@@ -770,38 +917,40 @@ CONFIG_MII=y
 # CONFIG_SUNGEM is not set
 # CONFIG_CASSINI is not set
 CONFIG_NET_VENDOR_3COM=y
-CONFIG_VORTEX=y
+# CONFIG_VORTEX is not set
 # CONFIG_TYPHOON is not set
 CONFIG_NET_TULIP=y
 # CONFIG_DE2104X is not set
-CONFIG_TULIP=y
-# CONFIG_TULIP_MWI is not set
-# CONFIG_TULIP_MMIO is not set
-# CONFIG_TULIP_NAPI is not set
+# CONFIG_TULIP is not set
 # CONFIG_DE4X5 is not set
 # CONFIG_WINBOND_840 is not set
 # CONFIG_DM9102 is not set
 # CONFIG_ULI526X is not set
+# CONFIG_PCMCIA_XIRCOM is not set
 # CONFIG_HP100 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
 CONFIG_NET_PCI=y
 # CONFIG_PCNET32 is not set
 # CONFIG_AMD8111_ETH is not set
 # CONFIG_ADAPTEC_STARFIRE is not set
-CONFIG_B44=y
+# CONFIG_B44 is not set
 CONFIG_FORCEDETH=y
 # CONFIG_FORCEDETH_NAPI is not set
-# CONFIG_DGRS is not set
 # CONFIG_EEPRO100 is not set
 CONFIG_E100=y
 # CONFIG_FEALNX is not set
 # CONFIG_NATSEMI is not set
 # CONFIG_NE2K_PCI is not set
-CONFIG_8139CP=y
+# CONFIG_8139CP is not set
 CONFIG_8139TOO=y
-# CONFIG_8139TOO_PIO is not set
+CONFIG_8139TOO_PIO=y
 # CONFIG_8139TOO_TUNE_TWISTER is not set
 # CONFIG_8139TOO_8129 is not set
 # CONFIG_8139_OLD_RX_RESET is not set
+# CONFIG_R6040 is not set
 # CONFIG_SIS900 is not set
 # CONFIG_EPIC100 is not set
 # CONFIG_SUNDANCE is not set
@@ -814,34 +963,75 @@ CONFIG_NETDEV_1000=y
 CONFIG_E1000=y
 # CONFIG_E1000_NAPI is not set
 # CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
+# CONFIG_E1000E is not set
+# CONFIG_E1000E_ENABLED is not set
+# CONFIG_IP1000 is not set
+# CONFIG_IGB is not set
 # CONFIG_NS83820 is not set
 # CONFIG_HAMACHI is not set
 # CONFIG_YELLOWFIN is not set
-CONFIG_R8169=y
-# CONFIG_R8169_NAPI is not set
+# CONFIG_R8169 is not set
 # CONFIG_SIS190 is not set
 # CONFIG_SKGE is not set
 CONFIG_SKY2=y
+# CONFIG_SKY2_DEBUG is not set
 # CONFIG_VIA_VELOCITY is not set
 CONFIG_TIGON3=y
-CONFIG_BNX2=y
+# CONFIG_BNX2 is not set
 # CONFIG_QLA3XXX is not set
 # CONFIG_ATL1 is not set
 CONFIG_NETDEV_10000=y
 # CONFIG_CHELSIO_T1 is not set
 # CONFIG_CHELSIO_T3 is not set
+# CONFIG_IXGBE is not set
 # CONFIG_IXGB is not set
 # CONFIG_S2IO is not set
 # CONFIG_MYRI10GE is not set
 # CONFIG_NETXEN_NIC is not set
+# CONFIG_NIU is not set
 # CONFIG_MLX4_CORE is not set
-# CONFIG_TR is not set
+# CONFIG_TEHUTI is not set
+# CONFIG_BNX2X is not set
+# CONFIG_SFC is not set
+CONFIG_TR=y
+# CONFIG_IBMOL is not set
+# CONFIG_IBMLS is not set
+# CONFIG_3C359 is not set
+# CONFIG_TMS380TR is not set
 
 #
 # Wireless LAN
 #
 # CONFIG_WLAN_PRE80211 is not set
-# CONFIG_WLAN_80211 is not set
+CONFIG_WLAN_80211=y
+# CONFIG_PCMCIA_RAYCS is not set
+# CONFIG_IPW2100 is not set
+# CONFIG_IPW2200 is not set
+# CONFIG_LIBERTAS is not set
+# CONFIG_AIRO is not set
+# CONFIG_HERMES is not set
+# CONFIG_ATMEL is not set
+# CONFIG_AIRO_CS is not set
+# CONFIG_PCMCIA_WL3501 is not set
+# CONFIG_PRISM54 is not set
+# CONFIG_USB_ZD1201 is not set
+# CONFIG_USB_NET_RNDIS_WLAN is not set
+# CONFIG_RTL8180 is not set
+# CONFIG_RTL8187 is not set
+# CONFIG_ADM8211 is not set
+# CONFIG_P54_COMMON is not set
+CONFIG_ATH5K=y
+# CONFIG_ATH5K_DEBUG is not set
+# CONFIG_IWLWIFI is not set
+# CONFIG_IWLCORE is not set
+# CONFIG_IWLWIFI_LEDS is not set
+# CONFIG_IWL4965 is not set
+# CONFIG_IWL3945 is not set
+# CONFIG_HOSTAP is not set
+# CONFIG_B43 is not set
+# CONFIG_B43LEGACY is not set
+# CONFIG_ZD1211RW is not set
+# CONFIG_RT2X00 is not set
 
 #
 # USB Network Adapters
@@ -850,16 +1040,27 @@ CONFIG_NETDEV_10000=y
 # CONFIG_USB_KAWETH is not set
 # CONFIG_USB_PEGASUS is not set
 # CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET_MII is not set
 # CONFIG_USB_USBNET is not set
+CONFIG_NET_PCMCIA=y
+# CONFIG_PCMCIA_3C589 is not set
+# CONFIG_PCMCIA_3C574 is not set
+# CONFIG_PCMCIA_FMVJ18X is not set
+# CONFIG_PCMCIA_PCNET is not set
+# CONFIG_PCMCIA_NMCLAN is not set
+# CONFIG_PCMCIA_SMC91C92 is not set
+# CONFIG_PCMCIA_XIRC2PS is not set
+# CONFIG_PCMCIA_AXNET is not set
+# CONFIG_PCMCIA_IBMTR is not set
 # CONFIG_WAN is not set
-# CONFIG_FDDI is not set
+CONFIG_FDDI=y
+# CONFIG_DEFXX is not set
+# CONFIG_SKFP is not set
 # CONFIG_HIPPI is not set
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
 # CONFIG_NET_FC is not set
-# CONFIG_SHAPER is not set
 CONFIG_NETCONSOLE=y
+# CONFIG_NETCONSOLE_DYNAMIC is not set
 CONFIG_NETPOLL=y
 # CONFIG_NETPOLL_TRAP is not set
 CONFIG_NET_POLL_CONTROLLER=y
@@ -870,18 +1071,17 @@ CONFIG_NET_POLL_CONTROLLER=y
 # Input device support
 #
 CONFIG_INPUT=y
-# CONFIG_INPUT_FF_MEMLESS is not set
-# CONFIG_INPUT_POLLDEV is not set
+CONFIG_INPUT_FF_MEMLESS=y
+CONFIG_INPUT_POLLDEV=y
 
 #
 # Userland interfaces
 #
 CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
 CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 # CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
 CONFIG_INPUT_EVDEV=y
 # CONFIG_INPUT_EVBUG is not set
 
@@ -906,17 +1106,63 @@ CONFIG_MOUSE_PS2_TRACKPOINT=y
 # CONFIG_MOUSE_SERIAL is not set
 # CONFIG_MOUSE_APPLETOUCH is not set
 # CONFIG_MOUSE_VSXXXAA is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TABLET is not set
-# CONFIG_INPUT_TOUCHSCREEN is not set
-# CONFIG_INPUT_MISC is not set
+CONFIG_INPUT_JOYSTICK=y
+# CONFIG_JOYSTICK_ANALOG is not set
+# CONFIG_JOYSTICK_A3D is not set
+# CONFIG_JOYSTICK_ADI is not set
+# CONFIG_JOYSTICK_COBRA is not set
+# CONFIG_JOYSTICK_GF2K is not set
+# CONFIG_JOYSTICK_GRIP is not set
+# CONFIG_JOYSTICK_GRIP_MP is not set
+# CONFIG_JOYSTICK_GUILLEMOT is not set
+# CONFIG_JOYSTICK_INTERACT is not set
+# CONFIG_JOYSTICK_SIDEWINDER is not set
+# CONFIG_JOYSTICK_TMDC is not set
+# CONFIG_JOYSTICK_IFORCE is not set
+# CONFIG_JOYSTICK_WARRIOR is not set
+# CONFIG_JOYSTICK_MAGELLAN is not set
+# CONFIG_JOYSTICK_SPACEORB is not set
+# CONFIG_JOYSTICK_SPACEBALL is not set
+# CONFIG_JOYSTICK_STINGER is not set
+# CONFIG_JOYSTICK_TWIDJOY is not set
+# CONFIG_JOYSTICK_ZHENHUA is not set
+# CONFIG_JOYSTICK_JOYDUMP is not set
+# CONFIG_JOYSTICK_XPAD is not set
+CONFIG_INPUT_TABLET=y
+# CONFIG_TABLET_USB_ACECAD is not set
+# CONFIG_TABLET_USB_AIPTEK is not set
+# CONFIG_TABLET_USB_GTCO is not set
+# CONFIG_TABLET_USB_KBTAB is not set
+# CONFIG_TABLET_USB_WACOM is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_UCB1400 is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_PCSPKR is not set
+# CONFIG_INPUT_APANEL is not set
+# CONFIG_INPUT_WISTRON_BTNS is not set
+# CONFIG_INPUT_ATLAS_BTNS is not set
+# CONFIG_INPUT_ATI_REMOTE is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_YEALINK is not set
+# CONFIG_INPUT_UINPUT is not set
 
 #
 # Hardware I/O ports
 #
 CONFIG_SERIO=y
 CONFIG_SERIO_I8042=y
-# CONFIG_SERIO_SERPORT is not set
+CONFIG_SERIO_SERPORT=y
 # CONFIG_SERIO_CT82C710 is not set
 # CONFIG_SERIO_PCIPS2 is not set
 CONFIG_SERIO_LIBPS2=y
@@ -929,8 +1175,26 @@ CONFIG_SERIO_LIBPS2=y
 CONFIG_VT=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVKMEM=y
+CONFIG_SERIAL_NONSTANDARD=y
+# CONFIG_COMPUTONE is not set
+# CONFIG_ROCKETPORT is not set
+# CONFIG_CYCLADES is not set
+# CONFIG_DIGIEPCA is not set
+# CONFIG_MOXA_INTELLIO is not set
+# CONFIG_MOXA_SMARTIO is not set
+# CONFIG_ISI is not set
+# CONFIG_SYNCLINK is not set
+# CONFIG_SYNCLINKMP is not set
+# CONFIG_SYNCLINK_GT is not set
+# CONFIG_N_HDLC is not set
+# CONFIG_RISCOM8 is not set
+# CONFIG_SPECIALIX is not set
+# CONFIG_SX is not set
+# CONFIG_RIO is not set
+# CONFIG_STALDRV is not set
+# CONFIG_NOZOMI is not set
 
 #
 # Serial drivers
@@ -940,9 +1204,14 @@ CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_FIX_EARLYCON_MEM=y
 CONFIG_SERIAL_8250_PCI=y
 CONFIG_SERIAL_8250_PNP=y
-CONFIG_SERIAL_8250_NR_UARTS=4
+# CONFIG_SERIAL_8250_CS is not set
+CONFIG_SERIAL_8250_NR_UARTS=32
 CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-# CONFIG_SERIAL_8250_EXTENDED is not set
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250_DETECT_IRQ=y
+CONFIG_SERIAL_8250_RSA=y
 
 #
 # Non-8250 serial port support
@@ -951,89 +1220,275 @@ CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 # CONFIG_SERIAL_JSM is not set
 CONFIG_UNIX98_PTYS=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_LEGACY_PTYS is not set
 # CONFIG_IPMI_HANDLER is not set
-# CONFIG_WATCHDOG is not set
 CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_INTEL=y
-CONFIG_HW_RANDOM_AMD=y
+# CONFIG_HW_RANDOM_INTEL is not set
+# CONFIG_HW_RANDOM_AMD is not set
 CONFIG_HW_RANDOM_GEODE=y
 CONFIG_HW_RANDOM_VIA=y
-# CONFIG_NVRAM is not set
-CONFIG_RTC=y
+CONFIG_NVRAM=y
 # CONFIG_R3964 is not set
 # CONFIG_APPLICOM is not set
 # CONFIG_SONYPI is not set
-CONFIG_AGP=y
-# CONFIG_AGP_ALI is not set
-# CONFIG_AGP_ATI is not set
-# CONFIG_AGP_AMD is not set
-CONFIG_AGP_AMD64=y
-CONFIG_AGP_INTEL=y
-# CONFIG_AGP_NVIDIA is not set
-# CONFIG_AGP_SIS is not set
-# CONFIG_AGP_SWORKS is not set
-# CONFIG_AGP_VIA is not set
-# CONFIG_AGP_EFFICEON is not set
-# CONFIG_DRM is not set
+
+#
+# PCMCIA character devices
+#
+# CONFIG_SYNCLINK_CS is not set
+# CONFIG_CARDMAN_4000 is not set
+# CONFIG_CARDMAN_4040 is not set
+# CONFIG_IPWIRELESS is not set
 # CONFIG_MWAVE is not set
 # CONFIG_PC8736x_GPIO is not set
 # CONFIG_NSC_GPIO is not set
 # CONFIG_CS5535_GPIO is not set
-CONFIG_RAW_DRIVER=y
-CONFIG_MAX_RAW_DEVS=256
+# CONFIG_RAW_DRIVER is not set
 CONFIG_HPET=y
 # CONFIG_HPET_RTC_IRQ is not set
-CONFIG_HPET_MMAP=y
+# CONFIG_HPET_MMAP is not set
 # CONFIG_HANGCHECK_TIMER is not set
 # CONFIG_TCG_TPM is not set
 # CONFIG_TELCLOCK is not set
 CONFIG_DEVPORT=y
-# CONFIG_I2C is not set
-
-#
-# SPI support
-#
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I2C_CHARDEV is not set
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+CONFIG_I2C_I801=y
+# CONFIG_I2C_I810 is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_PROSAVAGE is not set
+# CONFIG_I2C_SAVAGE4 is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_SCx200_ACB is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_TINY_USB is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+# CONFIG_I2C_VOODOO3 is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
 # CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
 # CONFIG_W1 is not set
-# CONFIG_POWER_SUPPLY is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_BATTERY_DS2760 is not set
 # CONFIG_HWMON is not set
+CONFIG_THERMAL=y
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+# CONFIG_ACQUIRE_WDT is not set
+# CONFIG_ADVANTECH_WDT is not set
+# CONFIG_ALIM1535_WDT is not set
+# CONFIG_ALIM7101_WDT is not set
+# CONFIG_SC520_WDT is not set
+# CONFIG_EUROTECH_WDT is not set
+# CONFIG_IB700_WDT is not set
+# CONFIG_IBMASR is not set
+# CONFIG_WAFER_WDT is not set
+# CONFIG_I6300ESB_WDT is not set
+# CONFIG_ITCO_WDT is not set
+# CONFIG_IT8712F_WDT is not set
+# CONFIG_HP_WATCHDOG is not set
+# CONFIG_SC1200_WDT is not set
+# CONFIG_PC87413_WDT is not set
+# CONFIG_60XX_WDT is not set
+# CONFIG_SBC8360_WDT is not set
+# CONFIG_SBC7240_WDT is not set
+# CONFIG_CPU5_WDT is not set
+# CONFIG_SMSC37B787_WDT is not set
+# CONFIG_W83627HF_WDT is not set
+# CONFIG_W83697HF_WDT is not set
+# CONFIG_W83877F_WDT is not set
+# CONFIG_W83977F_WDT is not set
+# CONFIG_MACHZ_WDT is not set
+# CONFIG_SBC_EPX_C3_WATCHDOG is not set
+
+#
+# PCI-based Watchdog Cards
+#
+# CONFIG_PCIPCWATCHDOG is not set
+# CONFIG_WDTPCI is not set
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
 
 #
 # Multifunction device drivers
 #
 # CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
 
 #
 # Multimedia devices
 #
+
+#
+# Multimedia core support
+#
 # CONFIG_VIDEO_DEV is not set
 # CONFIG_DVB_CORE is not set
+
+#
+# Multimedia drivers
+#
 CONFIG_DAB=y
 # CONFIG_USB_DABUSB is not set
 
 #
 # Graphics support
 #
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+CONFIG_AGP=y
+# CONFIG_AGP_ALI is not set
+# CONFIG_AGP_ATI is not set
+# CONFIG_AGP_AMD is not set
+CONFIG_AGP_AMD64=y
+CONFIG_AGP_INTEL=y
+# CONFIG_AGP_NVIDIA is not set
+# CONFIG_AGP_SIS is not set
+# CONFIG_AGP_SWORKS is not set
+# CONFIG_AGP_VIA is not set
+# CONFIG_AGP_EFFICEON is not set
+CONFIG_DRM=y
+# CONFIG_DRM_TDFX is not set
+# CONFIG_DRM_R128 is not set
+# CONFIG_DRM_RADEON is not set
+# CONFIG_DRM_I810 is not set
+# CONFIG_DRM_I830 is not set
+CONFIG_DRM_I915=y
+# CONFIG_DRM_MGA is not set
+# CONFIG_DRM_SIS is not set
+# CONFIG_DRM_VIA is not set
+# CONFIG_DRM_SAVAGE is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_TILEBLITTING=y
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_CIRRUS is not set
+# CONFIG_FB_PM2 is not set
+# CONFIG_FB_CYBER2000 is not set
+# CONFIG_FB_ARC is not set
+# CONFIG_FB_ASILIANT is not set
+# CONFIG_FB_IMSTT is not set
+# CONFIG_FB_VGA16 is not set
+# CONFIG_FB_UVESA is not set
+# CONFIG_FB_VESA is not set
+CONFIG_FB_EFI=y
+# CONFIG_FB_IMAC is not set
+# CONFIG_FB_N411 is not set
+# CONFIG_FB_HGA is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_NVIDIA is not set
+# CONFIG_FB_RIVA is not set
+# CONFIG_FB_I810 is not set
+# CONFIG_FB_LE80578 is not set
+# CONFIG_FB_INTEL is not set
+# CONFIG_FB_MATROX is not set
+# CONFIG_FB_RADEON is not set
+# CONFIG_FB_ATY128 is not set
+# CONFIG_FB_ATY is not set
+# CONFIG_FB_S3 is not set
+# CONFIG_FB_SAVAGE is not set
+# CONFIG_FB_SIS is not set
+# CONFIG_FB_NEOMAGIC is not set
+# CONFIG_FB_KYRO is not set
+# CONFIG_FB_3DFX is not set
+# CONFIG_FB_VOODOO1 is not set
+# CONFIG_FB_VT8623 is not set
+# CONFIG_FB_CYBLA is not set
+# CONFIG_FB_TRIDENT is not set
+# CONFIG_FB_ARK is not set
+# CONFIG_FB_PM3 is not set
+# CONFIG_FB_GEODE is not set
+# CONFIG_FB_VIRTUAL is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_CORGI is not set
+# CONFIG_BACKLIGHT_PROGEAR is not set
 
 #
 # Display device support
 #
 # CONFIG_DISPLAY_SUPPORT is not set
-# CONFIG_VGASTATE is not set
-# CONFIG_FB is not set
 
 #
 # Console display driver support
 #
 CONFIG_VGA_CONSOLE=y
 CONFIG_VGACON_SOFT_SCROLLBACK=y
-CONFIG_VGACON_SOFT_SCROLLBACK_SIZE=128
+CONFIG_VGACON_SOFT_SCROLLBACK_SIZE=64
 CONFIG_VIDEO_SELECT=y
 CONFIG_DUMMY_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE is not set
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+CONFIG_LOGO_LINUX_CLUT224=y
 
 #
 # Sound
@@ -1043,33 +1498,167 @@ CONFIG_SOUND=y
 #
 # Advanced Linux Sound Architecture
 #
-# CONFIG_SND is not set
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_HWDEP=y
+CONFIG_SND_SEQUENCER=y
+CONFIG_SND_SEQ_DUMMY=y
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=y
+CONFIG_SND_PCM_OSS=y
+CONFIG_SND_PCM_OSS_PLUGINS=y
+CONFIG_SND_SEQUENCER_OSS=y
+CONFIG_SND_DYNAMIC_MINORS=y
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_VMASTER=y
+
+#
+# Generic devices
+#
+# CONFIG_SND_PCSP is not set
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_VIRMIDI is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+
+#
+# PCI devices
+#
+# CONFIG_SND_AD1889 is not set
+# CONFIG_SND_ALS300 is not set
+# CONFIG_SND_ALS4000 is not set
+# CONFIG_SND_ALI5451 is not set
+# CONFIG_SND_ATIIXP is not set
+# CONFIG_SND_ATIIXP_MODEM is not set
+# CONFIG_SND_AU8810 is not set
+# CONFIG_SND_AU8820 is not set
+# CONFIG_SND_AU8830 is not set
+# CONFIG_SND_AW2 is not set
+# CONFIG_SND_AZT3328 is not set
+# CONFIG_SND_BT87X is not set
+# CONFIG_SND_CA0106 is not set
+# CONFIG_SND_CMIPCI is not set
+# CONFIG_SND_OXYGEN is not set
+# CONFIG_SND_CS4281 is not set
+# CONFIG_SND_CS46XX is not set
+# CONFIG_SND_CS5530 is not set
+# CONFIG_SND_CS5535AUDIO is not set
+# CONFIG_SND_DARLA20 is not set
+# CONFIG_SND_GINA20 is not set
+# CONFIG_SND_LAYLA20 is not set
+# CONFIG_SND_DARLA24 is not set
+# CONFIG_SND_GINA24 is not set
+# CONFIG_SND_LAYLA24 is not set
+# CONFIG_SND_MONA is not set
+# CONFIG_SND_MIA is not set
+# CONFIG_SND_ECHO3G is not set
+# CONFIG_SND_INDIGO is not set
+# CONFIG_SND_INDIGOIO is not set
+# CONFIG_SND_INDIGODJ is not set
+# CONFIG_SND_EMU10K1 is not set
+# CONFIG_SND_EMU10K1X is not set
+# CONFIG_SND_ENS1370 is not set
+# CONFIG_SND_ENS1371 is not set
+# CONFIG_SND_ES1938 is not set
+# CONFIG_SND_ES1968 is not set
+# CONFIG_SND_FM801 is not set
+CONFIG_SND_HDA_INTEL=y
+CONFIG_SND_HDA_HWDEP=y
+CONFIG_SND_HDA_CODEC_REALTEK=y
+CONFIG_SND_HDA_CODEC_ANALOG=y
+CONFIG_SND_HDA_CODEC_SIGMATEL=y
+CONFIG_SND_HDA_CODEC_VIA=y
+CONFIG_SND_HDA_CODEC_ATIHDMI=y
+CONFIG_SND_HDA_CODEC_CONEXANT=y
+CONFIG_SND_HDA_CODEC_CMEDIA=y
+CONFIG_SND_HDA_CODEC_SI3054=y
+CONFIG_SND_HDA_GENERIC=y
+# CONFIG_SND_HDA_POWER_SAVE is not set
+# CONFIG_SND_HDSP is not set
+# CONFIG_SND_HDSPM is not set
+# CONFIG_SND_HIFIER is not set
+# CONFIG_SND_ICE1712 is not set
+# CONFIG_SND_ICE1724 is not set
+# CONFIG_SND_INTEL8X0 is not set
+# CONFIG_SND_INTEL8X0M is not set
+# CONFIG_SND_KORG1212 is not set
+# CONFIG_SND_MAESTRO3 is not set
+# CONFIG_SND_MIXART is not set
+# CONFIG_SND_NM256 is not set
+# CONFIG_SND_PCXHR is not set
+# CONFIG_SND_RIPTIDE is not set
+# CONFIG_SND_RME32 is not set
+# CONFIG_SND_RME96 is not set
+# CONFIG_SND_RME9652 is not set
+# CONFIG_SND_SIS7019 is not set
+# CONFIG_SND_SONICVIBES is not set
+# CONFIG_SND_TRIDENT is not set
+# CONFIG_SND_VIA82XX is not set
+# CONFIG_SND_VIA82XX_MODEM is not set
+# CONFIG_SND_VIRTUOSO is not set
+# CONFIG_SND_VX222 is not set
+# CONFIG_SND_YMFPCI is not set
+
+#
+# USB devices
+#
+# CONFIG_SND_USB_AUDIO is not set
+# CONFIG_SND_USB_USX2Y is not set
+# CONFIG_SND_USB_CAIAQ is not set
+
+#
+# PCMCIA devices
+#
+# CONFIG_SND_VXPOCKET is not set
+# CONFIG_SND_PDAUDIOCF is not set
+
+#
+# System on Chip audio support
+#
+# CONFIG_SND_SOC is not set
+
+#
+# ALSA SoC audio for Freescale SOCs
+#
+
+#
+# SoC Audio for the Texas Instruments OMAP
+#
 
 #
 # Open Sound System
 #
-CONFIG_SOUND_PRIME=y
-# CONFIG_SOUND_TRIDENT is not set
-# CONFIG_SOUND_MSNDCLAS is not set
-# CONFIG_SOUND_MSNDPIN is not set
-# CONFIG_SOUND_OSS is not set
+# CONFIG_SOUND_PRIME is not set
 CONFIG_HID_SUPPORT=y
 CONFIG_HID=y
-# CONFIG_HID_DEBUG is not set
+CONFIG_HID_DEBUG=y
+CONFIG_HIDRAW=y
 
 #
 # USB Input Devices
 #
 CONFIG_USB_HID=y
-# CONFIG_USB_HIDINPUT_POWERBOOK is not set
-# CONFIG_HID_FF is not set
-# CONFIG_USB_HIDDEV is not set
+CONFIG_USB_HIDINPUT_POWERBOOK=y
+CONFIG_HID_FF=y
+CONFIG_HID_PID=y
+CONFIG_LOGITECH_FF=y
+# CONFIG_LOGIRUMBLEPAD2_FF is not set
+CONFIG_PANTHERLORD_FF=y
+CONFIG_THRUSTMASTER_FF=y
+CONFIG_ZEROPLUS_FF=y
+CONFIG_USB_HIDDEV=y
 CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
 CONFIG_USB_ARCH_HAS_OHCI=y
 CONFIG_USB_ARCH_HAS_EHCI=y
 CONFIG_USB=y
-# CONFIG_USB_DEBUG is not set
+CONFIG_USB_DEBUG=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
 
 #
 # Miscellaneous USB options
@@ -1077,18 +1666,18 @@ CONFIG_USB=y
 CONFIG_USB_DEVICEFS=y
 # CONFIG_USB_DEVICE_CLASS is not set
 # CONFIG_USB_DYNAMIC_MINORS is not set
-# CONFIG_USB_SUSPEND is not set
-# CONFIG_USB_PERSIST is not set
+CONFIG_USB_SUSPEND=y
 # CONFIG_USB_OTG is not set
 
 #
 # USB Host Controller Drivers
 #
+# CONFIG_USB_C67X00_HCD is not set
 CONFIG_USB_EHCI_HCD=y
-# CONFIG_USB_EHCI_SPLIT_ISO is not set
 # CONFIG_USB_EHCI_ROOT_HUB_TT is not set
 # CONFIG_USB_EHCI_TT_NEWSCHED is not set
 # CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
 CONFIG_USB_OHCI_HCD=y
 # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
 # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
@@ -1121,8 +1710,10 @@ CONFIG_USB_STORAGE=y
 # CONFIG_USB_STORAGE_SDDR55 is not set
 # CONFIG_USB_STORAGE_JUMPSHOT is not set
 # CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
 # CONFIG_USB_STORAGE_KARMA is not set
-# CONFIG_USB_LIBUSUAL is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+CONFIG_USB_LIBUSUAL=y
 
 #
 # USB Imaging devices
@@ -1134,10 +1725,6 @@ CONFIG_USB_MON=y
 #
 # USB port drivers
 #
-
-#
-# USB Serial Converter support
-#
 # CONFIG_USB_SERIAL is not set
 
 #
@@ -1163,90 +1750,125 @@ CONFIG_USB_MON=y
 # CONFIG_USB_TRANCEVIBRATOR is not set
 # CONFIG_USB_IOWARRIOR is not set
 # CONFIG_USB_TEST is not set
+# CONFIG_USB_GADGET is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
 
 #
-# USB DSL modem support
+# LED drivers
 #
+# CONFIG_LEDS_CLEVO_MAIL is not set
 
 #
-# USB Gadget Support
+# LED Triggers
 #
-# CONFIG_USB_GADGET is not set
-# CONFIG_MMC is not set
+CONFIG_LEDS_TRIGGERS=y
+# CONFIG_LEDS_TRIGGER_TIMER is not set
+# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+CONFIG_EDAC=y
 
 #
-# LED devices
+# Reporting subsystems
 #
-# CONFIG_NEW_LEDS is not set
+# CONFIG_EDAC_DEBUG is not set
+# CONFIG_EDAC_MM_EDAC is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_HCTOSYS is not set
+# CONFIG_RTC_DEBUG is not set
 
 #
-# LED drivers
+# RTC interfaces
 #
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
 
 #
-# LED Triggers
+# I2C RTC drivers
 #
-# CONFIG_INFINIBAND is not set
-# CONFIG_EDAC is not set
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
 
 #
-# Real Time Clock
+# SPI RTC drivers
 #
-# CONFIG_RTC_CLASS is not set
 
 #
-# DMA Engine support
+# Platform RTC drivers
 #
-# CONFIG_DMA_ENGINE is not set
+CONFIG_RTC_DRV_CMOS=y
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_V3020 is not set
 
 #
-# DMA Clients
+# on-CPU RTC drivers
 #
+CONFIG_DMADEVICES=y
 
 #
 # DMA Devices
 #
-CONFIG_VIRTUALIZATION=y
-# CONFIG_KVM is not set
+# CONFIG_INTEL_IOATDMA is not set
+# CONFIG_UIO is not set
 
 #
-# Userspace I/O
+# Firmware Drivers
 #
-# CONFIG_UIO is not set
+# CONFIG_EDD is not set
+CONFIG_EFI_VARS=y
+# CONFIG_DELL_RBU is not set
+# CONFIG_DCDBAS is not set
+CONFIG_DMIID=y
+# CONFIG_ISCSI_IBFT_FIND is not set
 
 #
 # File systems
 #
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_POSIX_ACL=y
-# CONFIG_EXT2_FS_SECURITY is not set
-# CONFIG_EXT2_FS_XIP is not set
+# CONFIG_EXT2_FS is not set
 CONFIG_EXT3_FS=y
 CONFIG_EXT3_FS_XATTR=y
 CONFIG_EXT3_FS_POSIX_ACL=y
-# CONFIG_EXT3_FS_SECURITY is not set
+CONFIG_EXT3_FS_SECURITY=y
 # CONFIG_EXT4DEV_FS is not set
 CONFIG_JBD=y
 # CONFIG_JBD_DEBUG is not set
 CONFIG_FS_MBCACHE=y
-CONFIG_REISERFS_FS=y
-# CONFIG_REISERFS_CHECK is not set
-# CONFIG_REISERFS_PROC_INFO is not set
-CONFIG_REISERFS_FS_XATTR=y
-CONFIG_REISERFS_FS_POSIX_ACL=y
-# CONFIG_REISERFS_FS_SECURITY is not set
+# CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 CONFIG_FS_POSIX_ACL=y
 # CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
+CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
-# CONFIG_QUOTA is not set
-CONFIG_DNOTIFY=y
+CONFIG_QUOTA=y
+CONFIG_QUOTA_NETLINK_INTERFACE=y
+# CONFIG_PRINT_QUOTA_WARNING is not set
+# CONFIG_QFMT_V1 is not set
+CONFIG_QFMT_V2=y
+CONFIG_QUOTACTL=y
 # CONFIG_AUTOFS_FS is not set
 CONFIG_AUTOFS4_FS=y
 # CONFIG_FUSE_FS is not set
@@ -1256,8 +1878,8 @@ CONFIG_GENERIC_ACL=y
 # CD-ROM/DVD Filesystems
 #
 CONFIG_ISO9660_FS=y
-# CONFIG_JOLIET is not set
-# CONFIG_ZISOFS is not set
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
 # CONFIG_UDF_FS is not set
 
 #
@@ -1275,13 +1897,13 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 #
 CONFIG_PROC_FS=y
 CONFIG_PROC_KCORE=y
+CONFIG_PROC_VMCORE=y
 CONFIG_PROC_SYSCTL=y
 CONFIG_SYSFS=y
 CONFIG_TMPFS=y
 CONFIG_TMPFS_POSIX_ACL=y
 CONFIG_HUGETLBFS=y
 CONFIG_HUGETLB_PAGE=y
-CONFIG_RAMFS=y
 # CONFIG_CONFIGFS_FS is not set
 
 #
@@ -1289,6 +1911,7 @@ CONFIG_RAMFS=y
 #
 # CONFIG_ADFS_FS is not set
 # CONFIG_AFFS_FS is not set
+# CONFIG_ECRYPT_FS is not set
 # CONFIG_HFS_FS is not set
 # CONFIG_HFSPLUS_FS is not set
 # CONFIG_BEFS_FS is not set
@@ -1296,33 +1919,15 @@ CONFIG_RAMFS=y
 # CONFIG_EFS_FS is not set
 # CONFIG_CRAMFS is not set
 # CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-# CONFIG_NFS_V3_ACL is not set
-# CONFIG_NFS_V4 is not set
-# CONFIG_NFS_DIRECTIO is not set
-CONFIG_NFSD=y
-CONFIG_NFSD_V3=y
-# CONFIG_NFSD_V3_ACL is not set
-# CONFIG_NFSD_V4 is not set
-CONFIG_NFSD_TCP=y
-CONFIG_ROOT_NFS=y
-CONFIG_LOCKD=y
-CONFIG_LOCKD_V4=y
-CONFIG_EXPORTFS=y
-CONFIG_NFS_COMMON=y
-CONFIG_SUNRPC=y
-# CONFIG_SUNRPC_BIND34 is not set
-# CONFIG_RPCSEC_GSS_KRB5 is not set
-# CONFIG_RPCSEC_GSS_SPKM3 is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+# CONFIG_NFS_FS is not set
+# CONFIG_NFSD is not set
 # CONFIG_SMB_FS is not set
 # CONFIG_CIFS is not set
 # CONFIG_NCP_FS is not set
@@ -1332,14 +1937,26 @@ CONFIG_SUNRPC=y
 #
 # Partition Types
 #
-# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+CONFIG_OSF_PARTITION=y
+CONFIG_AMIGA_PARTITION=y
+# CONFIG_ATARI_PARTITION is not set
+CONFIG_MAC_PARTITION=y
 CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
+CONFIG_BSD_DISKLABEL=y
+CONFIG_MINIX_SUBPARTITION=y
+CONFIG_SOLARIS_X86_PARTITION=y
+CONFIG_UNIXWARE_DISKLABEL=y
+# CONFIG_LDM_PARTITION is not set
+CONFIG_SGI_PARTITION=y
+# CONFIG_ULTRIX_PARTITION is not set
+CONFIG_SUN_PARTITION=y
+CONFIG_KARMA_PARTITION=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_SYSV68_PARTITION is not set
 CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_DEFAULT="utf8"
 CONFIG_NLS_CODEPAGE_437=y
 # CONFIG_NLS_CODEPAGE_737 is not set
 # CONFIG_NLS_CODEPAGE_775 is not set
@@ -1374,37 +1991,33 @@ CONFIG_NLS_ISO8859_1=y
 # CONFIG_NLS_ISO8859_9 is not set
 # CONFIG_NLS_ISO8859_13 is not set
 # CONFIG_NLS_ISO8859_14 is not set
-CONFIG_NLS_ISO8859_15=y
+# CONFIG_NLS_ISO8859_15 is not set
 # CONFIG_NLS_KOI8_R is not set
 # CONFIG_NLS_KOI8_U is not set
 CONFIG_NLS_UTF8=y
-
-#
-# Distributed Lock Manager
-#
 # CONFIG_DLM is not set
-CONFIG_INSTRUMENTATION=y
-CONFIG_PROFILING=y
-CONFIG_OPROFILE=y
-CONFIG_KPROBES=y
 
 #
 # Kernel hacking
 #
 CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 # CONFIG_PRINTK_TIME is not set
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
 # CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=2048
 CONFIG_MAGIC_SYSRQ=y
-CONFIG_UNUSED_SYMBOLS=y
-# CONFIG_DEBUG_FS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_CHECK is not set
 CONFIG_DEBUG_KERNEL=y
 # CONFIG_DEBUG_SHIRQ is not set
-CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_DETECT_SOFTLOCKUP is not set
 # CONFIG_SCHED_DEBUG is not set
-# CONFIG_SCHEDSTATS is not set
+CONFIG_SCHEDSTATS=y
 CONFIG_TIMER_STATS=y
+# CONFIG_DEBUG_OBJECTS is not set
 # CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
 # CONFIG_DEBUG_RT_MUTEXES is not set
 # CONFIG_RT_MUTEX_TESTER is not set
 # CONFIG_DEBUG_SPINLOCK is not set
@@ -1419,48 +2032,174 @@ CONFIG_TIMER_STATS=y
 CONFIG_DEBUG_BUGVERBOSE=y
 # CONFIG_DEBUG_INFO is not set
 # CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
 # CONFIG_DEBUG_LIST is not set
-# CONFIG_FRAME_POINTER is not set
-CONFIG_OPTIMIZE_INLINING=y
+# CONFIG_DEBUG_SG is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_KPROBES_SANITY_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
 # CONFIG_LKDTM is not set
 # CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+CONFIG_PROVIDE_OHCI1394_DMA_INIT=y
+# CONFIG_SAMPLES is not set
+# CONFIG_KGDB is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_NONPROMISC_DEVMEM is not set
 CONFIG_EARLY_PRINTK=y
 CONFIG_DEBUG_STACKOVERFLOW=y
-# CONFIG_DEBUG_STACK_USAGE is not set
-# CONFIG_DEBUG_RODATA is not set
+CONFIG_DEBUG_STACK_USAGE=y
+# CONFIG_DEBUG_PAGEALLOC is not set
+# CONFIG_X86_PTDUMP is not set
+CONFIG_DEBUG_RODATA=y
+# CONFIG_DEBUG_RODATA_TEST is not set
+CONFIG_DEBUG_NX_TEST=m
 # CONFIG_4KSTACKS is not set
 CONFIG_X86_FIND_SMP_CONFIG=y
 CONFIG_X86_MPPARSE=y
 CONFIG_DOUBLEFAULT=y
+CONFIG_IO_DELAY_TYPE_0X80=0
+CONFIG_IO_DELAY_TYPE_0XED=1
+CONFIG_IO_DELAY_TYPE_UDELAY=2
+CONFIG_IO_DELAY_TYPE_NONE=3
+CONFIG_IO_DELAY_0X80=y
+# CONFIG_IO_DELAY_0XED is not set
+# CONFIG_IO_DELAY_UDELAY is not set
+# CONFIG_IO_DELAY_NONE is not set
+CONFIG_DEFAULT_IO_DELAY_TYPE=0
+CONFIG_DEBUG_BOOT_PARAMS=y
+# CONFIG_CPA_DEBUG is not set
 
 #
 # Security options
 #
-# CONFIG_KEYS is not set
-# CONFIG_SECURITY is not set
-# CONFIG_CRYPTO is not set
+CONFIG_KEYS=y
+CONFIG_KEYS_DEBUG_PROC_KEYS=y
+CONFIG_SECURITY=y
+CONFIG_SECURITY_NETWORK=y
+# CONFIG_SECURITY_NETWORK_XFRM is not set
+CONFIG_SECURITY_CAPABILITIES=y
+CONFIG_SECURITY_FILE_CAPABILITIES=y
+# CONFIG_SECURITY_ROOTPLUG is not set
+CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=65536
+CONFIG_SECURITY_SELINUX=y
+CONFIG_SECURITY_SELINUX_BOOTPARAM=y
+CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=1
+CONFIG_SECURITY_SELINUX_DISABLE=y
+CONFIG_SECURITY_SELINUX_DEVELOP=y
+CONFIG_SECURITY_SELINUX_AVC_STATS=y
+CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1
+# CONFIG_SECURITY_SELINUX_ENABLE_SECMARK_DEFAULT is not set
+# CONFIG_SECURITY_SELINUX_POLICYDB_VERSION_MAX is not set
+# CONFIG_SECURITY_SMACK is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_MANAGER=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_AUTHENC=y
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=y
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=y
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+CONFIG_CRYPTO_SHA1=y
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_AES_586 is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+CONFIG_CRYPTO_ARC4=y
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SALSA20_586 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# CONFIG_CRYPTO_TWOFISH_586 is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_DEV_PADLOCK is not set
+# CONFIG_CRYPTO_DEV_GEODE is not set
+# CONFIG_CRYPTO_DEV_HIFN_795X is not set
+CONFIG_HAVE_KVM=y
+CONFIG_VIRTUALIZATION=y
+# CONFIG_KVM is not set
+# CONFIG_LGUEST is not set
+# CONFIG_VIRTIO_PCI is not set
+# CONFIG_VIRTIO_BALLOON is not set
 
 #
 # Library routines
 #
 CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_FIRST_BIT=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
 # CONFIG_CRC_CCITT is not set
 # CONFIG_CRC16 is not set
 # CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
 # CONFIG_CRC7 is not set
 # CONFIG_LIBCRC32C is not set
+CONFIG_AUDIT_GENERIC=y
 CONFIG_ZLIB_INFLATE=y
 CONFIG_PLIST=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_GENERIC_PENDING_IRQ=y
-CONFIG_X86_SMP=y
-CONFIG_X86_HT=y
-CONFIG_X86_BIOS_REBOOT=y
-CONFIG_X86_TRAMPOLINE=y
-CONFIG_KTIME_SCALAR=y
diff --git a/arch/x86/configs/x86_64_defconfig b/arch/x86/configs/x86_64_defconfig
index 2d6f5b2809d2..ae5124e064d4 100644
--- a/arch/x86/configs/x86_64_defconfig
+++ b/arch/x86/configs/x86_64_defconfig
@@ -1,64 +1,103 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.22-git14
-# Fri Jul 20 09:53:15 2007
+# Linux kernel version: 2.6.26-rc1
+# Sun May  4 19:59:57 2008
 #
-CONFIG_X86_64=y
 CONFIG_64BIT=y
+# CONFIG_X86_32 is not set
+CONFIG_X86_64=y
 CONFIG_X86=y
+CONFIG_DEFCONFIG_LIST="arch/x86/configs/x86_64_defconfig"
+# CONFIG_GENERIC_LOCKBREAK is not set
 CONFIG_GENERIC_TIME=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
 CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_ZONE_DMA32=y
+CONFIG_CLOCKSOURCE_WATCHDOG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
 CONFIG_LOCKDEP_SUPPORT=y
 CONFIG_STACKTRACE_SUPPORT=y
-CONFIG_SEMAPHORE_SLEEPERS=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_FAST_CMPXCHG_LOCAL=y
 CONFIG_MMU=y
 CONFIG_ZONE_DMA=y
-CONFIG_QUICKLIST=y
-CONFIG_NR_QUICK=2
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-CONFIG_GENERIC_HWEIGHT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_X86_CMPXCHG=y
-CONFIG_EARLY_PRINTK=y
 CONFIG_GENERIC_ISA_DMA=y
 CONFIG_GENERIC_IOMAP=y
-CONFIG_ARCH_MAY_HAVE_PC_FDC=y
-CONFIG_ARCH_POPULATES_NODE_MAP=y
-CONFIG_DMI=y
-CONFIG_AUDIT_ARCH=y
 CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_HWEIGHT=y
+# CONFIG_GENERIC_GPIO is not set
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
 # CONFIG_ARCH_HAS_ILOG2_U64 is not set
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_ARCH_HAS_CPU_RELAX=y
+CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
+CONFIG_HAVE_SETUP_PER_CPU_AREA=y
+CONFIG_HAVE_CPUMASK_OF_CPU_MAP=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ZONE_DMA32=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_AUDIT_ARCH=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_PENDING_IRQ=y
+CONFIG_X86_SMP=y
+CONFIG_X86_64_SMP=y
+CONFIG_X86_HT=y
+CONFIG_X86_BIOS_REBOOT=y
+CONFIG_X86_TRAMPOLINE=y
+# CONFIG_KTIME_SCALAR is not set
 
 #
-# Code maturity level options
+# General setup
 #
 CONFIG_EXPERIMENTAL=y
 CONFIG_LOCK_KERNEL=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
 CONFIG_LOCALVERSION=""
-CONFIG_LOCALVERSION_AUTO=y
+# CONFIG_LOCALVERSION_AUTO is not set
 CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
 CONFIG_SYSVIPC_SYSCTL=y
 CONFIG_POSIX_MQUEUE=y
-# CONFIG_BSD_PROCESS_ACCT is not set
-# CONFIG_TASKSTATS is not set
-# CONFIG_USER_NS is not set
-# CONFIG_AUDIT is not set
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=18
-# CONFIG_CPUSETS is not set
-CONFIG_SYSFS_DEPRECATED=y
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_AUDIT=y
+CONFIG_AUDITSYSCALL=y
+CONFIG_AUDIT_TREE=y
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_CGROUP_NS=y
+# CONFIG_CGROUP_DEVICE is not set
+CONFIG_CPUSETS=y
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+# CONFIG_USER_SCHED is not set
+CONFIG_CGROUP_SCHED=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+# CONFIG_CGROUP_MEM_RES_CTLR is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+CONFIG_PROC_PID_CPUSET=y
 CONFIG_RELAY=y
+CONFIG_NAMESPACES=y
+CONFIG_UTS_NS=y
+CONFIG_IPC_NS=y
+CONFIG_USER_NS=y
+CONFIG_PID_NS=y
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
@@ -66,13 +105,15 @@ CONFIG_SYSCTL=y
 # CONFIG_EMBEDDED is not set
 CONFIG_UID16=y
 CONFIG_SYSCTL_SYSCALL=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_KALLSYMS=y
 CONFIG_KALLSYMS_ALL=y
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_KALLSYMS_EXTRA_PASS=y
 CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 CONFIG_ELF_CORE=y
+# CONFIG_COMPAT_BRK is not set
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_ANON_INODES=y
@@ -82,9 +123,21 @@ CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
 CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_SLAB=y
-# CONFIG_SLUB is not set
+CONFIG_SLUB_DEBUG=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
 # CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+CONFIG_MARKERS=y
+# CONFIG_OPROFILE is not set
+CONFIG_HAVE_OPROFILE=y
+CONFIG_KPROBES=y
+CONFIG_KRETPROBES=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+# CONFIG_HAVE_DMA_ATTRS is not set
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
@@ -96,14 +149,15 @@ CONFIG_MODULE_FORCE_UNLOAD=y
 # CONFIG_KMOD is not set
 CONFIG_STOP_MACHINE=y
 CONFIG_BLOCK=y
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_BLK_DEV_BSG is not set
+CONFIG_BLK_DEV_IO_TRACE=y
+CONFIG_BLK_DEV_BSG=y
+CONFIG_BLOCK_COMPAT=y
 
 #
 # IO Schedulers
 #
 CONFIG_IOSCHED_NOOP=y
-# CONFIG_IOSCHED_AS is not set
+CONFIG_IOSCHED_AS=y
 CONFIG_IOSCHED_DEADLINE=y
 CONFIG_IOSCHED_CFQ=y
 # CONFIG_DEFAULT_AS is not set
@@ -111,107 +165,177 @@ CONFIG_IOSCHED_CFQ=y
 CONFIG_DEFAULT_CFQ=y
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_CLASSIC_RCU=y
 
 #
 # Processor type and features
 #
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_SMP=y
 CONFIG_X86_PC=y
+# CONFIG_X86_ELAN is not set
+# CONFIG_X86_VOYAGER is not set
+# CONFIG_X86_NUMAQ is not set
+# CONFIG_X86_SUMMIT is not set
+# CONFIG_X86_BIGSMP is not set
+# CONFIG_X86_VISWS is not set
+# CONFIG_X86_GENERICARCH is not set
+# CONFIG_X86_ES7000 is not set
+# CONFIG_X86_RDC321X is not set
 # CONFIG_X86_VSMP is not set
+# CONFIG_PARAVIRT_GUEST is not set
+CONFIG_MEMTEST_BOOTPARAM=y
+CONFIG_MEMTEST_BOOTPARAM_VALUE=0
+# CONFIG_M386 is not set
+# CONFIG_M486 is not set
+# CONFIG_M586 is not set
+# CONFIG_M586TSC is not set
+# CONFIG_M586MMX is not set
+# CONFIG_M686 is not set
+# CONFIG_MPENTIUMII is not set
+# CONFIG_MPENTIUMIII is not set
+# CONFIG_MPENTIUMM is not set
+# CONFIG_MPENTIUM4 is not set
+# CONFIG_MK6 is not set
+# CONFIG_MK7 is not set
 # CONFIG_MK8 is not set
+# CONFIG_MCRUSOE is not set
+# CONFIG_MEFFICEON is not set
+# CONFIG_MWINCHIPC6 is not set
+# CONFIG_MWINCHIP2 is not set
+# CONFIG_MWINCHIP3D is not set
+# CONFIG_MGEODEGX1 is not set
+# CONFIG_MGEODE_LX is not set
+# CONFIG_MCYRIXIII is not set
+# CONFIG_MVIAC3_2 is not set
+# CONFIG_MVIAC7 is not set
 # CONFIG_MPSC is not set
-# CONFIG_MCORE2 is not set
-CONFIG_GENERIC_CPU=y
-CONFIG_X86_L1_CACHE_BYTES=128
-CONFIG_X86_L1_CACHE_SHIFT=7
-CONFIG_X86_INTERNODE_CACHE_BYTES=128
-CONFIG_X86_TSC=y
+CONFIG_MCORE2=y
+# CONFIG_GENERIC_CPU is not set
+CONFIG_X86_CPU=y
+CONFIG_X86_L1_CACHE_BYTES=64
+CONFIG_X86_INTERNODE_CACHE_BYTES=64
+CONFIG_X86_CMPXCHG=y
+CONFIG_X86_L1_CACHE_SHIFT=6
 CONFIG_X86_GOOD_APIC=y
-# CONFIG_MICROCODE is not set
-CONFIG_X86_MSR=y
-CONFIG_X86_CPUID=y
-CONFIG_X86_HT=y
-CONFIG_X86_IO_APIC=y
-CONFIG_X86_LOCAL_APIC=y
-CONFIG_MTRR=y
-CONFIG_SMP=y
-CONFIG_SCHED_SMT=y
+CONFIG_X86_INTEL_USERCOPY=y
+CONFIG_X86_USE_PPRO_CHECKSUM=y
+CONFIG_X86_P6_NOP=y
+CONFIG_X86_TSC=y
+CONFIG_X86_CMOV=y
+CONFIG_X86_MINIMUM_CPU_FAMILY=64
+CONFIG_X86_DEBUGCTLMSR=y
+CONFIG_HPET_TIMER=y
+CONFIG_HPET_EMULATE_RTC=y
+CONFIG_DMI=y
+CONFIG_GART_IOMMU=y
+CONFIG_CALGARY_IOMMU=y
+CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT=y
+CONFIG_SWIOTLB=y
+CONFIG_IOMMU_HELPER=y
+CONFIG_NR_CPUS=4
+# CONFIG_SCHED_SMT is not set
 CONFIG_SCHED_MC=y
 # CONFIG_PREEMPT_NONE is not set
 CONFIG_PREEMPT_VOLUNTARY=y
 # CONFIG_PREEMPT is not set
-CONFIG_PREEMPT_BKL=y
+CONFIG_X86_LOCAL_APIC=y
+CONFIG_X86_IO_APIC=y
+# CONFIG_X86_MCE is not set
+# CONFIG_I8K is not set
+# CONFIG_MICROCODE is not set
+CONFIG_X86_MSR=y
+CONFIG_X86_CPUID=y
 CONFIG_NUMA=y
 CONFIG_K8_NUMA=y
-CONFIG_NODES_SHIFT=6
 CONFIG_X86_64_ACPI_NUMA=y
-CONFIG_NUMA_EMU=y
+CONFIG_NODES_SPAN_OTHER_NODES=y
+# CONFIG_NUMA_EMU is not set
+CONFIG_NODES_SHIFT=6
+CONFIG_ARCH_SPARSEMEM_DEFAULT=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_SELECT_MEMORY_MODEL=y
+# CONFIG_FLATMEM_MANUAL is not set
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_SPARSEMEM=y
 CONFIG_NEED_MULTIPLE_NODES=y
+CONFIG_HAVE_MEMORY_PRESENT=y
 # CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_SPARSEMEM_EXTREME=y
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_SPARSEMEM_VMEMMAP=y
+
+#
+# Memory hotplug is currently incompatible with Software Suspend
+#
+CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
 CONFIG_MIGRATION=y
 CONFIG_RESOURCES_64BIT=y
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_BOUNCE=y
 CONFIG_VIRT_TO_BUS=y
-CONFIG_HAVE_ARCH_EARLY_PFN_TO_NID=y
-CONFIG_OUT_OF_LINE_PFN_TO_PAGE=y
-CONFIG_NR_CPUS=32
-CONFIG_PHYSICAL_ALIGN=0x200000
-CONFIG_HOTPLUG_CPU=y
-CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
-CONFIG_HPET_TIMER=y
-CONFIG_HPET_EMULATE_RTC=y
-CONFIG_GART_IOMMU=y
-# CONFIG_CALGARY_IOMMU is not set
-CONFIG_SWIOTLB=y
-CONFIG_X86_MCE=y
-CONFIG_X86_MCE_INTEL=y
-CONFIG_X86_MCE_AMD=y
-# CONFIG_KEXEC is not set
-# CONFIG_CRASH_DUMP is not set
-# CONFIG_RELOCATABLE is not set
-CONFIG_PHYSICAL_START=0x200000
+CONFIG_MTRR=y
+# CONFIG_X86_PAT is not set
+CONFIG_EFI=y
 CONFIG_SECCOMP=y
-# CONFIG_CC_STACKPROTECTOR is not set
 # CONFIG_HZ_100 is not set
-CONFIG_HZ_250=y
+# CONFIG_HZ_250 is not set
 # CONFIG_HZ_300 is not set
-# CONFIG_HZ_1000 is not set
-CONFIG_HZ=250
-CONFIG_K8_NB=y
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_ISA_DMA_API=y
-CONFIG_GENERIC_PENDING_IRQ=y
+CONFIG_HZ_1000=y
+CONFIG_HZ=1000
+CONFIG_SCHED_HRTICK=y
+CONFIG_KEXEC=y
+CONFIG_CRASH_DUMP=y
+CONFIG_PHYSICAL_START=0x1000000
+CONFIG_RELOCATABLE=y
+CONFIG_PHYSICAL_ALIGN=0x200000
+CONFIG_HOTPLUG_CPU=y
+# CONFIG_COMPAT_VDSO is not set
+CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
+CONFIG_HAVE_ARCH_EARLY_PFN_TO_NID=y
 
 #
 # Power management options
 #
+CONFIG_ARCH_HIBERNATION_HEADER=y
 CONFIG_PM=y
-# CONFIG_PM_LEGACY is not set
-# CONFIG_PM_DEBUG is not set
+CONFIG_PM_DEBUG=y
+# CONFIG_PM_VERBOSE is not set
+CONFIG_CAN_PM_TRACE=y
+CONFIG_PM_TRACE=y
+CONFIG_PM_TRACE_RTC=y
+CONFIG_PM_SLEEP_SMP=y
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
 CONFIG_HIBERNATION=y
 CONFIG_PM_STD_PARTITION=""
-
-#
-# ACPI (Advanced Configuration and Power Interface) Support
-#
 CONFIG_ACPI=y
 CONFIG_ACPI_SLEEP=y
-CONFIG_ACPI_SLEEP_PROC_FS=y
-CONFIG_ACPI_SLEEP_PROC_SLEEP=y
 CONFIG_ACPI_PROCFS=y
+CONFIG_ACPI_PROCFS_POWER=y
+CONFIG_ACPI_SYSFS_POWER=y
+CONFIG_ACPI_PROC_EVENT=y
 CONFIG_ACPI_AC=y
 CONFIG_ACPI_BATTERY=y
 CONFIG_ACPI_BUTTON=y
 CONFIG_ACPI_FAN=y
-# CONFIG_ACPI_DOCK is not set
+CONFIG_ACPI_DOCK=y
+# CONFIG_ACPI_BAY is not set
 CONFIG_ACPI_PROCESSOR=y
 CONFIG_ACPI_HOTPLUG_CPU=y
 CONFIG_ACPI_THERMAL=y
 CONFIG_ACPI_NUMA=y
+# CONFIG_ACPI_WMI is not set
 # CONFIG_ACPI_ASUS is not set
 # CONFIG_ACPI_TOSHIBA is not set
+# CONFIG_ACPI_CUSTOM_DSDT is not set
 CONFIG_ACPI_BLACKLIST_YEAR=0
 # CONFIG_ACPI_DEBUG is not set
 CONFIG_ACPI_EC=y
@@ -227,29 +351,34 @@ CONFIG_ACPI_CONTAINER=y
 CONFIG_CPU_FREQ=y
 CONFIG_CPU_FREQ_TABLE=y
 CONFIG_CPU_FREQ_DEBUG=y
-CONFIG_CPU_FREQ_STAT=y
-# CONFIG_CPU_FREQ_STAT_DETAILS is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_STAT is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
 CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
 # CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
 CONFIG_CPU_FREQ_GOV_USERSPACE=y
 CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
 
 #
 # CPUFreq processor drivers
 #
-CONFIG_X86_POWERNOW_K8=y
-CONFIG_X86_POWERNOW_K8_ACPI=y
-# CONFIG_X86_SPEEDSTEP_CENTRINO is not set
 CONFIG_X86_ACPI_CPUFREQ=y
+# CONFIG_X86_POWERNOW_K8 is not set
+# CONFIG_X86_SPEEDSTEP_CENTRINO is not set
+# CONFIG_X86_P4_CLOCKMOD is not set
 
 #
 # shared options
 #
-CONFIG_X86_ACPI_CPUFREQ_PROC_INTF=y
+# CONFIG_X86_ACPI_CPUFREQ_PROC_INTF is not set
 # CONFIG_X86_SPEEDSTEP_LIB is not set
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_IDLE_GOV_MENU=y
 
 #
 # Bus options (PCI etc.)
@@ -257,27 +386,56 @@ CONFIG_X86_ACPI_CPUFREQ_PROC_INTF=y
 CONFIG_PCI=y
 CONFIG_PCI_DIRECT=y
 CONFIG_PCI_MMCONFIG=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_DMAR=y
+CONFIG_DMAR_GFX_WA=y
+CONFIG_DMAR_FLOPPY_WA=y
 CONFIG_PCIEPORTBUS=y
+# CONFIG_HOTPLUG_PCI_PCIE is not set
 CONFIG_PCIEAER=y
+# CONFIG_PCIEASPM is not set
 CONFIG_ARCH_SUPPORTS_MSI=y
 CONFIG_PCI_MSI=y
+# CONFIG_PCI_LEGACY is not set
 # CONFIG_PCI_DEBUG is not set
-# CONFIG_HT_IRQ is not set
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
-# CONFIG_PCCARD is not set
-# CONFIG_HOTPLUG_PCI is not set
+CONFIG_HT_IRQ=y
+CONFIG_ISA_DMA_API=y
+CONFIG_K8_NB=y
+CONFIG_PCCARD=y
+# CONFIG_PCMCIA_DEBUG is not set
+CONFIG_PCMCIA=y
+CONFIG_PCMCIA_LOAD_CIS=y
+CONFIG_PCMCIA_IOCTL=y
+CONFIG_CARDBUS=y
+
+#
+# PC-card bridges
+#
+CONFIG_YENTA=y
+CONFIG_YENTA_O2=y
+CONFIG_YENTA_RICOH=y
+CONFIG_YENTA_TI=y
+CONFIG_YENTA_ENE_TUNE=y
+CONFIG_YENTA_TOSHIBA=y
+# CONFIG_PD6729 is not set
+# CONFIG_I82092 is not set
+CONFIG_PCCARD_NONSTATIC=y
+CONFIG_HOTPLUG_PCI=y
+# CONFIG_HOTPLUG_PCI_FAKE is not set
+# CONFIG_HOTPLUG_PCI_ACPI is not set
+# CONFIG_HOTPLUG_PCI_CPCI is not set
+# CONFIG_HOTPLUG_PCI_SHPC is not set
 
 #
 # Executable file formats / Emulations
 #
 CONFIG_BINFMT_ELF=y
-# CONFIG_BINFMT_MISC is not set
+CONFIG_COMPAT_BINFMT_ELF=y
+CONFIG_BINFMT_MISC=y
 CONFIG_IA32_EMULATION=y
-CONFIG_IA32_AOUT=y
+# CONFIG_IA32_AOUT is not set
 CONFIG_COMPAT=y
+CONFIG_COMPAT_FOR_U64_ALIGNMENT=y
 CONFIG_SYSVIPC_COMPAT=y
 
 #
@@ -289,22 +447,31 @@ CONFIG_NET=y
 # Networking options
 #
 CONFIG_PACKET=y
-# CONFIG_PACKET_MMAP is not set
+CONFIG_PACKET_MMAP=y
 CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=y
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
 CONFIG_IP_MULTICAST=y
-# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ASK_IP_FIB_HASH=y
+# CONFIG_IP_FIB_TRIE is not set
 CONFIG_IP_FIB_HASH=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_IP_PNP_BOOTP is not set
-# CONFIG_IP_PNP_RARP is not set
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+# CONFIG_IP_PNP is not set
 # CONFIG_NET_IPIP is not set
 # CONFIG_NET_IPGRE is not set
-# CONFIG_IP_MROUTE is not set
+CONFIG_IP_MROUTE=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
 # CONFIG_ARPD is not set
-# CONFIG_SYN_COOKIES is not set
+CONFIG_SYN_COOKIES=y
 # CONFIG_INET_AH is not set
 # CONFIG_INET_ESP is not set
 # CONFIG_INET_IPCOMP is not set
@@ -313,31 +480,109 @@ CONFIG_INET_TUNNEL=y
 # CONFIG_INET_XFRM_MODE_TRANSPORT is not set
 # CONFIG_INET_XFRM_MODE_TUNNEL is not set
 # CONFIG_INET_XFRM_MODE_BEET is not set
-CONFIG_INET_DIAG=y
-CONFIG_INET_TCP_DIAG=y
-# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_INET_LRO=y
+# CONFIG_INET_DIAG is not set
+CONFIG_TCP_CONG_ADVANCED=y
+# CONFIG_TCP_CONG_BIC is not set
 CONFIG_TCP_CONG_CUBIC=y
+# CONFIG_TCP_CONG_WESTWOOD is not set
+# CONFIG_TCP_CONG_HTCP is not set
+# CONFIG_TCP_CONG_HSTCP is not set
+# CONFIG_TCP_CONG_HYBLA is not set
+# CONFIG_TCP_CONG_VEGAS is not set
+# CONFIG_TCP_CONG_SCALABLE is not set
+# CONFIG_TCP_CONG_LP is not set
+# CONFIG_TCP_CONG_VENO is not set
+# CONFIG_TCP_CONG_YEAH is not set
+# CONFIG_TCP_CONG_ILLINOIS is not set
+# CONFIG_DEFAULT_BIC is not set
+CONFIG_DEFAULT_CUBIC=y
+# CONFIG_DEFAULT_HTCP is not set
+# CONFIG_DEFAULT_VEGAS is not set
+# CONFIG_DEFAULT_WESTWOOD is not set
+# CONFIG_DEFAULT_RENO is not set
 CONFIG_DEFAULT_TCP_CONG="cubic"
-# CONFIG_TCP_MD5SIG is not set
+CONFIG_TCP_MD5SIG=y
+# CONFIG_IP_VS is not set
 CONFIG_IPV6=y
 # CONFIG_IPV6_PRIVACY is not set
 # CONFIG_IPV6_ROUTER_PREF is not set
 # CONFIG_IPV6_OPTIMISTIC_DAD is not set
-# CONFIG_INET6_AH is not set
-# CONFIG_INET6_ESP is not set
+CONFIG_INET6_AH=y
+CONFIG_INET6_ESP=y
 # CONFIG_INET6_IPCOMP is not set
 # CONFIG_IPV6_MIP6 is not set
 # CONFIG_INET6_XFRM_TUNNEL is not set
 # CONFIG_INET6_TUNNEL is not set
-# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET6_XFRM_MODE_BEET is not set
+CONFIG_INET6_XFRM_MODE_TRANSPORT=y
+CONFIG_INET6_XFRM_MODE_TUNNEL=y
+CONFIG_INET6_XFRM_MODE_BEET=y
 # CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
 CONFIG_IPV6_SIT=y
+CONFIG_IPV6_NDISC_NODETYPE=y
 # CONFIG_IPV6_TUNNEL is not set
 # CONFIG_IPV6_MULTIPLE_TABLES is not set
-# CONFIG_NETWORK_SECMARK is not set
-# CONFIG_NETFILTER is not set
+# CONFIG_IPV6_MROUTE is not set
+CONFIG_NETLABEL=y
+CONFIG_NETWORK_SECMARK=y
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+# CONFIG_NETFILTER_ADVANCED is not set
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=y
+CONFIG_NETFILTER_NETLINK_LOG=y
+CONFIG_NF_CONNTRACK=y
+CONFIG_NF_CONNTRACK_SECMARK=y
+CONFIG_NF_CONNTRACK_FTP=y
+CONFIG_NF_CONNTRACK_IRC=y
+CONFIG_NF_CONNTRACK_SIP=y
+CONFIG_NF_CT_NETLINK=y
+CONFIG_NETFILTER_XTABLES=y
+CONFIG_NETFILTER_XT_TARGET_MARK=y
+CONFIG_NETFILTER_XT_TARGET_NFLOG=y
+CONFIG_NETFILTER_XT_TARGET_SECMARK=y
+CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=y
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=y
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
+CONFIG_NETFILTER_XT_MATCH_MARK=y
+CONFIG_NETFILTER_XT_MATCH_POLICY=y
+CONFIG_NETFILTER_XT_MATCH_STATE=y
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_CONNTRACK_IPV4=y
+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_IP_NF_TARGET_LOG=y
+CONFIG_IP_NF_TARGET_ULOG=y
+CONFIG_NF_NAT=y
+CONFIG_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+CONFIG_NF_NAT_FTP=y
+CONFIG_NF_NAT_IRC=y
+# CONFIG_NF_NAT_TFTP is not set
+# CONFIG_NF_NAT_AMANDA is not set
+# CONFIG_NF_NAT_PPTP is not set
+# CONFIG_NF_NAT_H323 is not set
+CONFIG_NF_NAT_SIP=y
+CONFIG_IP_NF_MANGLE=y
+
+#
+# IPv6: Netfilter Configuration
+#
+CONFIG_NF_CONNTRACK_IPV6=y
+CONFIG_IP6_NF_IPTABLES=y
+CONFIG_IP6_NF_MATCH_IPV6HEADER=y
+CONFIG_IP6_NF_FILTER=y
+CONFIG_IP6_NF_TARGET_LOG=y
+CONFIG_IP6_NF_TARGET_REJECT=y
+CONFIG_IP6_NF_MANGLE=y
 # CONFIG_IP_DCCP is not set
 # CONFIG_IP_SCTP is not set
 # CONFIG_TIPC is not set
@@ -345,6 +590,7 @@ CONFIG_IPV6_SIT=y
 # CONFIG_BRIDGE is not set
 # CONFIG_VLAN_8021Q is not set
 # CONFIG_DECNET is not set
+CONFIG_LLC=y
 # CONFIG_LLC2 is not set
 # CONFIG_IPX is not set
 # CONFIG_ATALK is not set
@@ -352,28 +598,99 @@ CONFIG_IPV6_SIT=y
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
-# CONFIG_NET_SCHED is not set
+CONFIG_NET_SCHED=y
+
+#
+# Queueing/Scheduling
+#
+# CONFIG_NET_SCH_CBQ is not set
+# CONFIG_NET_SCH_HTB is not set
+# CONFIG_NET_SCH_HFSC is not set
+# CONFIG_NET_SCH_PRIO is not set
+# CONFIG_NET_SCH_RR is not set
+# CONFIG_NET_SCH_RED is not set
+# CONFIG_NET_SCH_SFQ is not set
+# CONFIG_NET_SCH_TEQL is not set
+# CONFIG_NET_SCH_TBF is not set
+# CONFIG_NET_SCH_GRED is not set
+# CONFIG_NET_SCH_DSMARK is not set
+# CONFIG_NET_SCH_NETEM is not set
+# CONFIG_NET_SCH_INGRESS is not set
+
+#
+# Classification
+#
+CONFIG_NET_CLS=y
+# CONFIG_NET_CLS_BASIC is not set
+# CONFIG_NET_CLS_TCINDEX is not set
+# CONFIG_NET_CLS_ROUTE4 is not set
+# CONFIG_NET_CLS_FW is not set
+# CONFIG_NET_CLS_U32 is not set
+# CONFIG_NET_CLS_RSVP is not set
+# CONFIG_NET_CLS_RSVP6 is not set
+# CONFIG_NET_CLS_FLOW is not set
+CONFIG_NET_EMATCH=y
+CONFIG_NET_EMATCH_STACK=32
+# CONFIG_NET_EMATCH_CMP is not set
+# CONFIG_NET_EMATCH_NBYTE is not set
+# CONFIG_NET_EMATCH_U32 is not set
+# CONFIG_NET_EMATCH_META is not set
+# CONFIG_NET_EMATCH_TEXT is not set
+CONFIG_NET_CLS_ACT=y
+# CONFIG_NET_ACT_POLICE is not set
+# CONFIG_NET_ACT_GACT is not set
+# CONFIG_NET_ACT_MIRRED is not set
+# CONFIG_NET_ACT_IPT is not set
+# CONFIG_NET_ACT_NAT is not set
+# CONFIG_NET_ACT_PEDIT is not set
+# CONFIG_NET_ACT_SIMP is not set
+CONFIG_NET_SCH_FIFO=y
 
 #
 # Network testing
 #
 # CONFIG_NET_PKTGEN is not set
 # CONFIG_NET_TCPPROBE is not set
-# CONFIG_HAMRADIO is not set
+CONFIG_HAMRADIO=y
+
+#
+# Packet Radio protocols
+#
+# CONFIG_AX25 is not set
+# CONFIG_CAN is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
 # CONFIG_AF_RXRPC is not set
+CONFIG_FIB_RULES=y
 
 #
 # Wireless
 #
-# CONFIG_CFG80211 is not set
-# CONFIG_WIRELESS_EXT is not set
-# CONFIG_MAC80211 is not set
+CONFIG_CFG80211=y
+CONFIG_NL80211=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_MAC80211=y
+
+#
+# Rate control algorithm selection
+#
+CONFIG_MAC80211_RC_DEFAULT_PID=y
+# CONFIG_MAC80211_RC_DEFAULT_NONE is not set
+
+#
+# Selecting 'y' for an algorithm will
+#
+
+#
+# build the algorithm into mac80211.
+#
+CONFIG_MAC80211_RC_DEFAULT="pid"
+CONFIG_MAC80211_RC_PID=y
+# CONFIG_MAC80211_MESH is not set
+CONFIG_MAC80211_LEDS=y
+# CONFIG_MAC80211_DEBUGFS is not set
+# CONFIG_MAC80211_DEBUG_PACKET_ALIGNMENT is not set
+# CONFIG_MAC80211_DEBUG is not set
 # CONFIG_IEEE80211 is not set
 # CONFIG_RFKILL is not set
 # CONFIG_NET_9P is not set
@@ -385,13 +702,15 @@ CONFIG_IPV6_SIT=y
 #
 # Generic Driver Options
 #
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 CONFIG_FW_LOADER=y
 # CONFIG_DEBUG_DRIVER is not set
-# CONFIG_DEBUG_DEVRES is not set
+CONFIG_DEBUG_DEVRES=y
 # CONFIG_SYS_HYPERVISOR is not set
-# CONFIG_CONNECTOR is not set
+CONFIG_CONNECTOR=y
+CONFIG_PROC_EVENTS=y
 # CONFIG_MTD is not set
 # CONFIG_PARPORT is not set
 CONFIG_PNP=y
@@ -402,7 +721,7 @@ CONFIG_PNP=y
 #
 CONFIG_PNPACPI=y
 CONFIG_BLK_DEV=y
-CONFIG_BLK_DEV_FD=y
+# CONFIG_BLK_DEV_FD is not set
 # CONFIG_BLK_CPQ_DA is not set
 # CONFIG_BLK_CPQ_CISS_DA is not set
 # CONFIG_BLK_DEV_DAC960 is not set
@@ -415,8 +734,8 @@ CONFIG_BLK_DEV_LOOP=y
 # CONFIG_BLK_DEV_UB is not set
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+CONFIG_BLK_DEV_RAM_SIZE=16384
+# CONFIG_BLK_DEV_XIP is not set
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
 CONFIG_MISC_DEVICES=y
@@ -425,72 +744,16 @@ CONFIG_MISC_DEVICES=y
 # CONFIG_EEPROM_93CX6 is not set
 # CONFIG_SGI_IOC4 is not set
 # CONFIG_TIFM_CORE is not set
+# CONFIG_ACER_WMI is not set
+# CONFIG_ASUS_LAPTOP is not set
+# CONFIG_FUJITSU_LAPTOP is not set
+# CONFIG_MSI_LAPTOP is not set
 # CONFIG_SONY_LAPTOP is not set
 # CONFIG_THINKPAD_ACPI is not set
-CONFIG_IDE=y
-CONFIG_BLK_DEV_IDE=y
-
-#
-# Please see Documentation/ide.txt for help/info on IDE drives
-#
-# CONFIG_BLK_DEV_IDE_SATA is not set
-# CONFIG_BLK_DEV_HD_IDE is not set
-CONFIG_BLK_DEV_IDEDISK=y
-CONFIG_IDEDISK_MULTI_MODE=y
-CONFIG_BLK_DEV_IDECD=y
-# CONFIG_BLK_DEV_IDETAPE is not set
-# CONFIG_BLK_DEV_IDEFLOPPY is not set
-# CONFIG_BLK_DEV_IDESCSI is not set
-CONFIG_BLK_DEV_IDEACPI=y
-# CONFIG_IDE_TASK_IOCTL is not set
-CONFIG_IDE_PROC_FS=y
-
-#
-# IDE chipset support/bugfixes
-#
-CONFIG_IDE_GENERIC=y
-# CONFIG_BLK_DEV_CMD640 is not set
-# CONFIG_BLK_DEV_IDEPNP is not set
-CONFIG_BLK_DEV_IDEPCI=y
-# CONFIG_IDEPCI_SHARE_IRQ is not set
-CONFIG_IDEPCI_PCIBUS_ORDER=y
-# CONFIG_BLK_DEV_OFFBOARD is not set
-# CONFIG_BLK_DEV_GENERIC is not set
-# CONFIG_BLK_DEV_OPTI621 is not set
-# CONFIG_BLK_DEV_RZ1000 is not set
-CONFIG_BLK_DEV_IDEDMA_PCI=y
-# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
-# CONFIG_IDEDMA_ONLYDISK is not set
-# CONFIG_BLK_DEV_AEC62XX is not set
-# CONFIG_BLK_DEV_ALI15X3 is not set
-CONFIG_BLK_DEV_AMD74XX=y
-CONFIG_BLK_DEV_ATIIXP=y
-# CONFIG_BLK_DEV_CMD64X is not set
-# CONFIG_BLK_DEV_TRIFLEX is not set
-# CONFIG_BLK_DEV_CY82C693 is not set
-# CONFIG_BLK_DEV_CS5520 is not set
-# CONFIG_BLK_DEV_CS5530 is not set
-# CONFIG_BLK_DEV_HPT34X is not set
-# CONFIG_BLK_DEV_HPT366 is not set
-# CONFIG_BLK_DEV_JMICRON is not set
-# CONFIG_BLK_DEV_SC1200 is not set
-CONFIG_BLK_DEV_PIIX=y
-# CONFIG_BLK_DEV_IT8213 is not set
-# CONFIG_BLK_DEV_IT821X is not set
-# CONFIG_BLK_DEV_NS87415 is not set
-# CONFIG_BLK_DEV_PDC202XX_OLD is not set
-CONFIG_BLK_DEV_PDC202XX_NEW=y
-# CONFIG_BLK_DEV_SVWKS is not set
-# CONFIG_BLK_DEV_SIIMAGE is not set
-# CONFIG_BLK_DEV_SIS5513 is not set
-# CONFIG_BLK_DEV_SLC90E66 is not set
-# CONFIG_BLK_DEV_TRM290 is not set
-# CONFIG_BLK_DEV_VIA82CXXX is not set
-# CONFIG_BLK_DEV_TC86C001 is not set
-# CONFIG_IDE_ARM is not set
-CONFIG_BLK_DEV_IDEDMA=y
-# CONFIG_IDEDMA_IVB is not set
-# CONFIG_BLK_DEV_HD is not set
+# CONFIG_INTEL_MENLOW is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
 
 #
 # SCSI device support
@@ -499,8 +762,8 @@ CONFIG_BLK_DEV_IDEDMA=y
 CONFIG_SCSI=y
 CONFIG_SCSI_DMA=y
 # CONFIG_SCSI_TGT is not set
-CONFIG_SCSI_NETLINK=y
-# CONFIG_SCSI_PROC_FS is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
 
 #
 # SCSI support type (disk, tape, CD-ROM)
@@ -509,7 +772,7 @@ CONFIG_BLK_DEV_SD=y
 # CONFIG_CHR_DEV_ST is not set
 # CONFIG_CHR_DEV_OSST is not set
 CONFIG_BLK_DEV_SR=y
-# CONFIG_BLK_DEV_SR_VENDOR is not set
+CONFIG_BLK_DEV_SR_VENDOR=y
 CONFIG_CHR_DEV_SG=y
 # CONFIG_CHR_DEV_SCH is not set
 
@@ -526,73 +789,37 @@ CONFIG_SCSI_WAIT_SCAN=m
 # SCSI Transports
 #
 CONFIG_SCSI_SPI_ATTRS=y
-CONFIG_SCSI_FC_ATTRS=y
+# CONFIG_SCSI_FC_ATTRS is not set
 # CONFIG_SCSI_ISCSI_ATTRS is not set
-CONFIG_SCSI_SAS_ATTRS=y
+# CONFIG_SCSI_SAS_ATTRS is not set
 # CONFIG_SCSI_SAS_LIBSAS is not set
-
-#
-# SCSI low-level drivers
-#
-# CONFIG_ISCSI_TCP is not set
-# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
-# CONFIG_SCSI_3W_9XXX is not set
-# CONFIG_SCSI_ACARD is not set
-# CONFIG_SCSI_AACRAID is not set
-# CONFIG_SCSI_AIC7XXX is not set
-# CONFIG_SCSI_AIC7XXX_OLD is not set
-CONFIG_SCSI_AIC79XX=y
-CONFIG_AIC79XX_CMDS_PER_DEVICE=32
-CONFIG_AIC79XX_RESET_DELAY_MS=4000
-# CONFIG_AIC79XX_DEBUG_ENABLE is not set
-CONFIG_AIC79XX_DEBUG_MASK=0
-# CONFIG_AIC79XX_REG_PRETTY_PRINT is not set
-# CONFIG_SCSI_AIC94XX is not set
-# CONFIG_SCSI_ARCMSR is not set
-# CONFIG_MEGARAID_NEWGEN is not set
-# CONFIG_MEGARAID_LEGACY is not set
-# CONFIG_MEGARAID_SAS is not set
-# CONFIG_SCSI_HPTIOP is not set
-# CONFIG_SCSI_BUSLOGIC is not set
-# CONFIG_SCSI_DMX3191D is not set
-# CONFIG_SCSI_EATA is not set
-# CONFIG_SCSI_FUTURE_DOMAIN is not set
-# CONFIG_SCSI_GDTH is not set
-# CONFIG_SCSI_IPS is not set
-# CONFIG_SCSI_INITIO is not set
-# CONFIG_SCSI_INIA100 is not set
-# CONFIG_SCSI_STEX is not set
-# CONFIG_SCSI_SYM53C8XX_2 is not set
-# CONFIG_SCSI_IPR is not set
-# CONFIG_SCSI_QLOGIC_1280 is not set
-# CONFIG_SCSI_QLA_FC is not set
-# CONFIG_SCSI_QLA_ISCSI is not set
-# CONFIG_SCSI_LPFC is not set
-# CONFIG_SCSI_DC395x is not set
-# CONFIG_SCSI_DC390T is not set
-# CONFIG_SCSI_DEBUG is not set
-# CONFIG_SCSI_SRP is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
 CONFIG_ATA=y
 # CONFIG_ATA_NONSTANDARD is not set
 CONFIG_ATA_ACPI=y
+CONFIG_SATA_PMP=y
 CONFIG_SATA_AHCI=y
-CONFIG_SATA_SVW=y
+# CONFIG_SATA_SIL24 is not set
+CONFIG_ATA_SFF=y
+# CONFIG_SATA_SVW is not set
 CONFIG_ATA_PIIX=y
 # CONFIG_SATA_MV is not set
-CONFIG_SATA_NV=y
+# CONFIG_SATA_NV is not set
 # CONFIG_PDC_ADMA is not set
 # CONFIG_SATA_QSTOR is not set
 # CONFIG_SATA_PROMISE is not set
 # CONFIG_SATA_SX4 is not set
-CONFIG_SATA_SIL=y
-# CONFIG_SATA_SIL24 is not set
+# CONFIG_SATA_SIL is not set
 # CONFIG_SATA_SIS is not set
 # CONFIG_SATA_ULI is not set
-CONFIG_SATA_VIA=y
+# CONFIG_SATA_VIA is not set
 # CONFIG_SATA_VITESSE is not set
 # CONFIG_SATA_INIC162X is not set
+# CONFIG_PATA_ACPI is not set
 # CONFIG_PATA_ALI is not set
-# CONFIG_PATA_AMD is not set
+CONFIG_PATA_AMD=y
 # CONFIG_PATA_ARTOP is not set
 # CONFIG_PATA_ATIIXP is not set
 # CONFIG_PATA_CMD640_PCI is not set
@@ -612,11 +839,14 @@ CONFIG_SATA_VIA=y
 # CONFIG_PATA_TRIFLEX is not set
 # CONFIG_PATA_MARVELL is not set
 # CONFIG_PATA_MPIIX is not set
-# CONFIG_PATA_OLDPIIX is not set
+CONFIG_PATA_OLDPIIX=y
 # CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
 # CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_NS87415 is not set
 # CONFIG_PATA_OPTI is not set
 # CONFIG_PATA_OPTIDMA is not set
+# CONFIG_PATA_PCMCIA is not set
 # CONFIG_PATA_PDC_OLD is not set
 # CONFIG_PATA_RADISYS is not set
 # CONFIG_PATA_RZ1000 is not set
@@ -628,65 +858,42 @@ CONFIG_SATA_VIA=y
 # CONFIG_PATA_VIA is not set
 # CONFIG_PATA_WINBOND is not set
 CONFIG_MD=y
-# CONFIG_BLK_DEV_MD is not set
+CONFIG_BLK_DEV_MD=y
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID10 is not set
+# CONFIG_MD_RAID456 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_MD_FAULTY is not set
 CONFIG_BLK_DEV_DM=y
 # CONFIG_DM_DEBUG is not set
 # CONFIG_DM_CRYPT is not set
 # CONFIG_DM_SNAPSHOT is not set
-# CONFIG_DM_MIRROR is not set
-# CONFIG_DM_ZERO is not set
+CONFIG_DM_MIRROR=y
+CONFIG_DM_ZERO=y
 # CONFIG_DM_MULTIPATH is not set
 # CONFIG_DM_DELAY is not set
-
-#
-# Fusion MPT device support
-#
-CONFIG_FUSION=y
-CONFIG_FUSION_SPI=y
-# CONFIG_FUSION_FC is not set
-# CONFIG_FUSION_SAS is not set
-CONFIG_FUSION_MAX_SGE=128
-# CONFIG_FUSION_CTL is not set
+# CONFIG_DM_UEVENT is not set
+# CONFIG_FUSION is not set
 
 #
 # IEEE 1394 (FireWire) support
 #
 # CONFIG_FIREWIRE is not set
-CONFIG_IEEE1394=y
-
-#
-# Subsystem Options
-#
-# CONFIG_IEEE1394_VERBOSEDEBUG is not set
-
-#
-# Controllers
-#
-
-#
-# Texas Instruments PCILynx requires I2C
-#
-CONFIG_IEEE1394_OHCI1394=y
-
-#
-# Protocols
-#
-# CONFIG_IEEE1394_VIDEO1394 is not set
-# CONFIG_IEEE1394_SBP2 is not set
-# CONFIG_IEEE1394_ETH1394_ROM_ENTRY is not set
-# CONFIG_IEEE1394_ETH1394 is not set
-# CONFIG_IEEE1394_DV1394 is not set
-CONFIG_IEEE1394_RAWIO=y
+# CONFIG_IEEE1394 is not set
 # CONFIG_I2O is not set
 CONFIG_MACINTOSH_DRIVERS=y
-# CONFIG_MAC_EMUMOUSEBTN is not set
+CONFIG_MAC_EMUMOUSEBTN=y
 CONFIG_NETDEVICES=y
-CONFIG_NETDEVICES_MULTIQUEUE=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_IFB is not set
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
 # CONFIG_EQUALIZER is not set
-CONFIG_TUN=y
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
 # CONFIG_NET_SB1000 is not set
 # CONFIG_ARCNET is not set
 # CONFIG_PHYLIB is not set
@@ -696,39 +903,40 @@ CONFIG_MII=y
 # CONFIG_SUNGEM is not set
 # CONFIG_CASSINI is not set
 CONFIG_NET_VENDOR_3COM=y
-CONFIG_VORTEX=y
+# CONFIG_VORTEX is not set
 # CONFIG_TYPHOON is not set
 CONFIG_NET_TULIP=y
 # CONFIG_DE2104X is not set
-CONFIG_TULIP=y
-# CONFIG_TULIP_MWI is not set
-# CONFIG_TULIP_MMIO is not set
-# CONFIG_TULIP_NAPI is not set
+# CONFIG_TULIP is not set
 # CONFIG_DE4X5 is not set
 # CONFIG_WINBOND_840 is not set
 # CONFIG_DM9102 is not set
 # CONFIG_ULI526X is not set
+# CONFIG_PCMCIA_XIRCOM is not set
 # CONFIG_HP100 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
 CONFIG_NET_PCI=y
 # CONFIG_PCNET32 is not set
-CONFIG_AMD8111_ETH=y
-# CONFIG_AMD8111E_NAPI is not set
+# CONFIG_AMD8111_ETH is not set
 # CONFIG_ADAPTEC_STARFIRE is not set
-CONFIG_B44=y
+# CONFIG_B44 is not set
 CONFIG_FORCEDETH=y
 # CONFIG_FORCEDETH_NAPI is not set
-# CONFIG_DGRS is not set
 # CONFIG_EEPRO100 is not set
 CONFIG_E100=y
 # CONFIG_FEALNX is not set
 # CONFIG_NATSEMI is not set
 # CONFIG_NE2K_PCI is not set
-CONFIG_8139CP=y
+# CONFIG_8139CP is not set
 CONFIG_8139TOO=y
-# CONFIG_8139TOO_PIO is not set
+CONFIG_8139TOO_PIO=y
 # CONFIG_8139TOO_TUNE_TWISTER is not set
 # CONFIG_8139TOO_8129 is not set
 # CONFIG_8139_OLD_RX_RESET is not set
+# CONFIG_R6040 is not set
 # CONFIG_SIS900 is not set
 # CONFIG_EPIC100 is not set
 # CONFIG_SUNDANCE is not set
@@ -740,34 +948,74 @@ CONFIG_NETDEV_1000=y
 CONFIG_E1000=y
 # CONFIG_E1000_NAPI is not set
 # CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
+# CONFIG_E1000E is not set
+# CONFIG_E1000E_ENABLED is not set
+# CONFIG_IP1000 is not set
+# CONFIG_IGB is not set
 # CONFIG_NS83820 is not set
 # CONFIG_HAMACHI is not set
 # CONFIG_YELLOWFIN is not set
 # CONFIG_R8169 is not set
 # CONFIG_SIS190 is not set
 # CONFIG_SKGE is not set
-# CONFIG_SKY2 is not set
+CONFIG_SKY2=y
+# CONFIG_SKY2_DEBUG is not set
 # CONFIG_VIA_VELOCITY is not set
 CONFIG_TIGON3=y
-CONFIG_BNX2=y
+# CONFIG_BNX2 is not set
 # CONFIG_QLA3XXX is not set
 # CONFIG_ATL1 is not set
 CONFIG_NETDEV_10000=y
 # CONFIG_CHELSIO_T1 is not set
 # CONFIG_CHELSIO_T3 is not set
+# CONFIG_IXGBE is not set
 # CONFIG_IXGB is not set
-CONFIG_S2IO=m
-# CONFIG_S2IO_NAPI is not set
+# CONFIG_S2IO is not set
 # CONFIG_MYRI10GE is not set
 # CONFIG_NETXEN_NIC is not set
+# CONFIG_NIU is not set
 # CONFIG_MLX4_CORE is not set
-# CONFIG_TR is not set
+# CONFIG_TEHUTI is not set
+# CONFIG_BNX2X is not set
+# CONFIG_SFC is not set
+CONFIG_TR=y
+# CONFIG_IBMOL is not set
+# CONFIG_3C359 is not set
+# CONFIG_TMS380TR is not set
 
 #
 # Wireless LAN
 #
 # CONFIG_WLAN_PRE80211 is not set
-# CONFIG_WLAN_80211 is not set
+CONFIG_WLAN_80211=y
+# CONFIG_PCMCIA_RAYCS is not set
+# CONFIG_IPW2100 is not set
+# CONFIG_IPW2200 is not set
+# CONFIG_LIBERTAS is not set
+# CONFIG_AIRO is not set
+# CONFIG_HERMES is not set
+# CONFIG_ATMEL is not set
+# CONFIG_AIRO_CS is not set
+# CONFIG_PCMCIA_WL3501 is not set
+# CONFIG_PRISM54 is not set
+# CONFIG_USB_ZD1201 is not set
+# CONFIG_USB_NET_RNDIS_WLAN is not set
+# CONFIG_RTL8180 is not set
+# CONFIG_RTL8187 is not set
+# CONFIG_ADM8211 is not set
+# CONFIG_P54_COMMON is not set
+CONFIG_ATH5K=y
+# CONFIG_ATH5K_DEBUG is not set
+# CONFIG_IWLWIFI is not set
+# CONFIG_IWLCORE is not set
+# CONFIG_IWLWIFI_LEDS is not set
+# CONFIG_IWL4965 is not set
+# CONFIG_IWL3945 is not set
+# CONFIG_HOSTAP is not set
+# CONFIG_B43 is not set
+# CONFIG_B43LEGACY is not set
+# CONFIG_ZD1211RW is not set
+# CONFIG_RT2X00 is not set
 
 #
 # USB Network Adapters
@@ -776,16 +1024,26 @@ CONFIG_S2IO=m
 # CONFIG_USB_KAWETH is not set
 # CONFIG_USB_PEGASUS is not set
 # CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET_MII is not set
 # CONFIG_USB_USBNET is not set
+CONFIG_NET_PCMCIA=y
+# CONFIG_PCMCIA_3C589 is not set
+# CONFIG_PCMCIA_3C574 is not set
+# CONFIG_PCMCIA_FMVJ18X is not set
+# CONFIG_PCMCIA_PCNET is not set
+# CONFIG_PCMCIA_NMCLAN is not set
+# CONFIG_PCMCIA_SMC91C92 is not set
+# CONFIG_PCMCIA_XIRC2PS is not set
+# CONFIG_PCMCIA_AXNET is not set
 # CONFIG_WAN is not set
-# CONFIG_FDDI is not set
+CONFIG_FDDI=y
+# CONFIG_DEFXX is not set
+# CONFIG_SKFP is not set
 # CONFIG_HIPPI is not set
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
 # CONFIG_NET_FC is not set
-# CONFIG_SHAPER is not set
 CONFIG_NETCONSOLE=y
+# CONFIG_NETCONSOLE_DYNAMIC is not set
 CONFIG_NETPOLL=y
 # CONFIG_NETPOLL_TRAP is not set
 CONFIG_NET_POLL_CONTROLLER=y
@@ -796,18 +1054,17 @@ CONFIG_NET_POLL_CONTROLLER=y
 # Input device support
 #
 CONFIG_INPUT=y
-# CONFIG_INPUT_FF_MEMLESS is not set
-# CONFIG_INPUT_POLLDEV is not set
+CONFIG_INPUT_FF_MEMLESS=y
+CONFIG_INPUT_POLLDEV=y
 
 #
 # Userland interfaces
 #
 CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
 CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 # CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
 CONFIG_INPUT_EVDEV=y
 # CONFIG_INPUT_EVBUG is not set
 
@@ -832,17 +1089,62 @@ CONFIG_MOUSE_PS2_TRACKPOINT=y
 # CONFIG_MOUSE_SERIAL is not set
 # CONFIG_MOUSE_APPLETOUCH is not set
 # CONFIG_MOUSE_VSXXXAA is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TABLET is not set
-# CONFIG_INPUT_TOUCHSCREEN is not set
-# CONFIG_INPUT_MISC is not set
+CONFIG_INPUT_JOYSTICK=y
+# CONFIG_JOYSTICK_ANALOG is not set
+# CONFIG_JOYSTICK_A3D is not set
+# CONFIG_JOYSTICK_ADI is not set
+# CONFIG_JOYSTICK_COBRA is not set
+# CONFIG_JOYSTICK_GF2K is not set
+# CONFIG_JOYSTICK_GRIP is not set
+# CONFIG_JOYSTICK_GRIP_MP is not set
+# CONFIG_JOYSTICK_GUILLEMOT is not set
+# CONFIG_JOYSTICK_INTERACT is not set
+# CONFIG_JOYSTICK_SIDEWINDER is not set
+# CONFIG_JOYSTICK_TMDC is not set
+# CONFIG_JOYSTICK_IFORCE is not set
+# CONFIG_JOYSTICK_WARRIOR is not set
+# CONFIG_JOYSTICK_MAGELLAN is not set
+# CONFIG_JOYSTICK_SPACEORB is not set
+# CONFIG_JOYSTICK_SPACEBALL is not set
+# CONFIG_JOYSTICK_STINGER is not set
+# CONFIG_JOYSTICK_TWIDJOY is not set
+# CONFIG_JOYSTICK_ZHENHUA is not set
+# CONFIG_JOYSTICK_JOYDUMP is not set
+# CONFIG_JOYSTICK_XPAD is not set
+CONFIG_INPUT_TABLET=y
+# CONFIG_TABLET_USB_ACECAD is not set
+# CONFIG_TABLET_USB_AIPTEK is not set
+# CONFIG_TABLET_USB_GTCO is not set
+# CONFIG_TABLET_USB_KBTAB is not set
+# CONFIG_TABLET_USB_WACOM is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_UCB1400 is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_PCSPKR is not set
+# CONFIG_INPUT_APANEL is not set
+# CONFIG_INPUT_ATLAS_BTNS is not set
+# CONFIG_INPUT_ATI_REMOTE is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_YEALINK is not set
+# CONFIG_INPUT_UINPUT is not set
 
 #
 # Hardware I/O ports
 #
 CONFIG_SERIO=y
 CONFIG_SERIO_I8042=y
-# CONFIG_SERIO_SERPORT is not set
+CONFIG_SERIO_SERPORT=y
 # CONFIG_SERIO_CT82C710 is not set
 # CONFIG_SERIO_PCIPS2 is not set
 CONFIG_SERIO_LIBPS2=y
@@ -855,8 +1157,26 @@ CONFIG_SERIO_LIBPS2=y
 CONFIG_VT=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVKMEM=y
+CONFIG_SERIAL_NONSTANDARD=y
+# CONFIG_COMPUTONE is not set
+# CONFIG_ROCKETPORT is not set
+# CONFIG_CYCLADES is not set
+# CONFIG_DIGIEPCA is not set
+# CONFIG_MOXA_INTELLIO is not set
+# CONFIG_MOXA_SMARTIO is not set
+# CONFIG_ISI is not set
+# CONFIG_SYNCLINK is not set
+# CONFIG_SYNCLINKMP is not set
+# CONFIG_SYNCLINK_GT is not set
+# CONFIG_N_HDLC is not set
+# CONFIG_RISCOM8 is not set
+# CONFIG_SPECIALIX is not set
+# CONFIG_SX is not set
+# CONFIG_RIO is not set
+# CONFIG_STALDRV is not set
+# CONFIG_NOZOMI is not set
 
 #
 # Serial drivers
@@ -866,9 +1186,14 @@ CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_FIX_EARLYCON_MEM=y
 CONFIG_SERIAL_8250_PCI=y
 CONFIG_SERIAL_8250_PNP=y
-CONFIG_SERIAL_8250_NR_UARTS=4
+# CONFIG_SERIAL_8250_CS is not set
+CONFIG_SERIAL_8250_NR_UARTS=32
 CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-# CONFIG_SERIAL_8250_EXTENDED is not set
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250_DETECT_IRQ=y
+CONFIG_SERIAL_8250_RSA=y
 
 #
 # Non-8250 serial port support
@@ -877,78 +1202,260 @@ CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 # CONFIG_SERIAL_JSM is not set
 CONFIG_UNIX98_PTYS=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_LEGACY_PTYS is not set
 # CONFIG_IPMI_HANDLER is not set
-# CONFIG_WATCHDOG is not set
 CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_INTEL=y
-CONFIG_HW_RANDOM_AMD=y
-# CONFIG_NVRAM is not set
-CONFIG_RTC=y
+# CONFIG_HW_RANDOM_INTEL is not set
+# CONFIG_HW_RANDOM_AMD is not set
+CONFIG_NVRAM=y
 # CONFIG_R3964 is not set
 # CONFIG_APPLICOM is not set
-CONFIG_AGP=y
-CONFIG_AGP_AMD64=y
-CONFIG_AGP_INTEL=y
-# CONFIG_AGP_SIS is not set
-# CONFIG_AGP_VIA is not set
-# CONFIG_DRM is not set
+
+#
+# PCMCIA character devices
+#
+# CONFIG_SYNCLINK_CS is not set
+# CONFIG_CARDMAN_4000 is not set
+# CONFIG_CARDMAN_4040 is not set
+# CONFIG_IPWIRELESS is not set
 # CONFIG_MWAVE is not set
 # CONFIG_PC8736x_GPIO is not set
-CONFIG_RAW_DRIVER=y
-CONFIG_MAX_RAW_DEVS=256
+# CONFIG_RAW_DRIVER is not set
 CONFIG_HPET=y
 # CONFIG_HPET_RTC_IRQ is not set
-CONFIG_HPET_MMAP=y
+# CONFIG_HPET_MMAP is not set
 # CONFIG_HANGCHECK_TIMER is not set
 # CONFIG_TCG_TPM is not set
 # CONFIG_TELCLOCK is not set
 CONFIG_DEVPORT=y
-# CONFIG_I2C is not set
-
-#
-# SPI support
-#
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I2C_CHARDEV is not set
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+CONFIG_I2C_I801=y
+# CONFIG_I2C_I810 is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_PROSAVAGE is not set
+# CONFIG_I2C_SAVAGE4 is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_TINY_USB is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+# CONFIG_I2C_VOODOO3 is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
 # CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
 # CONFIG_W1 is not set
-# CONFIG_POWER_SUPPLY is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_BATTERY_DS2760 is not set
 # CONFIG_HWMON is not set
+CONFIG_THERMAL=y
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+# CONFIG_ACQUIRE_WDT is not set
+# CONFIG_ADVANTECH_WDT is not set
+# CONFIG_ALIM1535_WDT is not set
+# CONFIG_ALIM7101_WDT is not set
+# CONFIG_SC520_WDT is not set
+# CONFIG_EUROTECH_WDT is not set
+# CONFIG_IB700_WDT is not set
+# CONFIG_IBMASR is not set
+# CONFIG_WAFER_WDT is not set
+# CONFIG_I6300ESB_WDT is not set
+# CONFIG_ITCO_WDT is not set
+# CONFIG_IT8712F_WDT is not set
+# CONFIG_HP_WATCHDOG is not set
+# CONFIG_SC1200_WDT is not set
+# CONFIG_PC87413_WDT is not set
+# CONFIG_60XX_WDT is not set
+# CONFIG_SBC8360_WDT is not set
+# CONFIG_CPU5_WDT is not set
+# CONFIG_SMSC37B787_WDT is not set
+# CONFIG_W83627HF_WDT is not set
+# CONFIG_W83697HF_WDT is not set
+# CONFIG_W83877F_WDT is not set
+# CONFIG_W83977F_WDT is not set
+# CONFIG_MACHZ_WDT is not set
+# CONFIG_SBC_EPX_C3_WATCHDOG is not set
+
+#
+# PCI-based Watchdog Cards
+#
+# CONFIG_PCIPCWATCHDOG is not set
+# CONFIG_WDTPCI is not set
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
 
 #
 # Multifunction device drivers
 #
 # CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
 
 #
 # Multimedia devices
 #
+
+#
+# Multimedia core support
+#
 # CONFIG_VIDEO_DEV is not set
 # CONFIG_DVB_CORE is not set
+
+#
+# Multimedia drivers
+#
 CONFIG_DAB=y
 # CONFIG_USB_DABUSB is not set
 
 #
 # Graphics support
 #
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+CONFIG_AGP=y
+CONFIG_AGP_AMD64=y
+CONFIG_AGP_INTEL=y
+# CONFIG_AGP_SIS is not set
+# CONFIG_AGP_VIA is not set
+CONFIG_DRM=y
+# CONFIG_DRM_TDFX is not set
+# CONFIG_DRM_R128 is not set
+# CONFIG_DRM_RADEON is not set
+# CONFIG_DRM_I810 is not set
+# CONFIG_DRM_I830 is not set
+CONFIG_DRM_I915=y
+# CONFIG_DRM_MGA is not set
+# CONFIG_DRM_SIS is not set
+# CONFIG_DRM_VIA is not set
+# CONFIG_DRM_SAVAGE is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_TILEBLITTING=y
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_CIRRUS is not set
+# CONFIG_FB_PM2 is not set
+# CONFIG_FB_CYBER2000 is not set
+# CONFIG_FB_ARC is not set
+# CONFIG_FB_ASILIANT is not set
+# CONFIG_FB_IMSTT is not set
+# CONFIG_FB_VGA16 is not set
+# CONFIG_FB_UVESA is not set
+# CONFIG_FB_VESA is not set
+CONFIG_FB_EFI=y
+# CONFIG_FB_IMAC is not set
+# CONFIG_FB_N411 is not set
+# CONFIG_FB_HGA is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_NVIDIA is not set
+# CONFIG_FB_RIVA is not set
+# CONFIG_FB_LE80578 is not set
+# CONFIG_FB_INTEL is not set
+# CONFIG_FB_MATROX is not set
+# CONFIG_FB_RADEON is not set
+# CONFIG_FB_ATY128 is not set
+# CONFIG_FB_ATY is not set
+# CONFIG_FB_S3 is not set
+# CONFIG_FB_SAVAGE is not set
+# CONFIG_FB_SIS is not set
+# CONFIG_FB_NEOMAGIC is not set
+# CONFIG_FB_KYRO is not set
+# CONFIG_FB_3DFX is not set
+# CONFIG_FB_VOODOO1 is not set
+# CONFIG_FB_VT8623 is not set
+# CONFIG_FB_TRIDENT is not set
+# CONFIG_FB_ARK is not set
+# CONFIG_FB_PM3 is not set
+# CONFIG_FB_GEODE is not set
+# CONFIG_FB_VIRTUAL is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_CORGI is not set
+# CONFIG_BACKLIGHT_PROGEAR is not set
 
 #
 # Display device support
 #
 # CONFIG_DISPLAY_SUPPORT is not set
-# CONFIG_VGASTATE is not set
-# CONFIG_FB is not set
 
 #
 # Console display driver support
 #
 CONFIG_VGA_CONSOLE=y
 CONFIG_VGACON_SOFT_SCROLLBACK=y
-CONFIG_VGACON_SOFT_SCROLLBACK_SIZE=256
+CONFIG_VGACON_SOFT_SCROLLBACK_SIZE=64
 CONFIG_VIDEO_SELECT=y
 CONFIG_DUMMY_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE is not set
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+CONFIG_LOGO_LINUX_CLUT224=y
 
 #
 # Sound
@@ -958,33 +1465,165 @@ CONFIG_SOUND=y
 #
 # Advanced Linux Sound Architecture
 #
-# CONFIG_SND is not set
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_HWDEP=y
+CONFIG_SND_SEQUENCER=y
+CONFIG_SND_SEQ_DUMMY=y
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=y
+CONFIG_SND_PCM_OSS=y
+CONFIG_SND_PCM_OSS_PLUGINS=y
+CONFIG_SND_SEQUENCER_OSS=y
+CONFIG_SND_DYNAMIC_MINORS=y
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_VMASTER=y
+
+#
+# Generic devices
+#
+# CONFIG_SND_PCSP is not set
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_VIRMIDI is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+
+#
+# PCI devices
+#
+# CONFIG_SND_AD1889 is not set
+# CONFIG_SND_ALS300 is not set
+# CONFIG_SND_ALS4000 is not set
+# CONFIG_SND_ALI5451 is not set
+# CONFIG_SND_ATIIXP is not set
+# CONFIG_SND_ATIIXP_MODEM is not set
+# CONFIG_SND_AU8810 is not set
+# CONFIG_SND_AU8820 is not set
+# CONFIG_SND_AU8830 is not set
+# CONFIG_SND_AW2 is not set
+# CONFIG_SND_AZT3328 is not set
+# CONFIG_SND_BT87X is not set
+# CONFIG_SND_CA0106 is not set
+# CONFIG_SND_CMIPCI is not set
+# CONFIG_SND_OXYGEN is not set
+# CONFIG_SND_CS4281 is not set
+# CONFIG_SND_CS46XX is not set
+# CONFIG_SND_CS5530 is not set
+# CONFIG_SND_DARLA20 is not set
+# CONFIG_SND_GINA20 is not set
+# CONFIG_SND_LAYLA20 is not set
+# CONFIG_SND_DARLA24 is not set
+# CONFIG_SND_GINA24 is not set
+# CONFIG_SND_LAYLA24 is not set
+# CONFIG_SND_MONA is not set
+# CONFIG_SND_MIA is not set
+# CONFIG_SND_ECHO3G is not set
+# CONFIG_SND_INDIGO is not set
+# CONFIG_SND_INDIGOIO is not set
+# CONFIG_SND_INDIGODJ is not set
+# CONFIG_SND_EMU10K1 is not set
+# CONFIG_SND_EMU10K1X is not set
+# CONFIG_SND_ENS1370 is not set
+# CONFIG_SND_ENS1371 is not set
+# CONFIG_SND_ES1938 is not set
+# CONFIG_SND_ES1968 is not set
+# CONFIG_SND_FM801 is not set
+CONFIG_SND_HDA_INTEL=y
+CONFIG_SND_HDA_HWDEP=y
+CONFIG_SND_HDA_CODEC_REALTEK=y
+CONFIG_SND_HDA_CODEC_ANALOG=y
+CONFIG_SND_HDA_CODEC_SIGMATEL=y
+CONFIG_SND_HDA_CODEC_VIA=y
+CONFIG_SND_HDA_CODEC_ATIHDMI=y
+CONFIG_SND_HDA_CODEC_CONEXANT=y
+CONFIG_SND_HDA_CODEC_CMEDIA=y
+CONFIG_SND_HDA_CODEC_SI3054=y
+CONFIG_SND_HDA_GENERIC=y
+# CONFIG_SND_HDA_POWER_SAVE is not set
+# CONFIG_SND_HDSP is not set
+# CONFIG_SND_HDSPM is not set
+# CONFIG_SND_HIFIER is not set
+# CONFIG_SND_ICE1712 is not set
+# CONFIG_SND_ICE1724 is not set
+# CONFIG_SND_INTEL8X0 is not set
+# CONFIG_SND_INTEL8X0M is not set
+# CONFIG_SND_KORG1212 is not set
+# CONFIG_SND_MAESTRO3 is not set
+# CONFIG_SND_MIXART is not set
+# CONFIG_SND_NM256 is not set
+# CONFIG_SND_PCXHR is not set
+# CONFIG_SND_RIPTIDE is not set
+# CONFIG_SND_RME32 is not set
+# CONFIG_SND_RME96 is not set
+# CONFIG_SND_RME9652 is not set
+# CONFIG_SND_SONICVIBES is not set
+# CONFIG_SND_TRIDENT is not set
+# CONFIG_SND_VIA82XX is not set
+# CONFIG_SND_VIA82XX_MODEM is not set
+# CONFIG_SND_VIRTUOSO is not set
+# CONFIG_SND_VX222 is not set
+# CONFIG_SND_YMFPCI is not set
+
+#
+# USB devices
+#
+# CONFIG_SND_USB_AUDIO is not set
+# CONFIG_SND_USB_USX2Y is not set
+# CONFIG_SND_USB_CAIAQ is not set
+
+#
+# PCMCIA devices
+#
+# CONFIG_SND_VXPOCKET is not set
+# CONFIG_SND_PDAUDIOCF is not set
+
+#
+# System on Chip audio support
+#
+# CONFIG_SND_SOC is not set
+
+#
+# ALSA SoC audio for Freescale SOCs
+#
+
+#
+# SoC Audio for the Texas Instruments OMAP
+#
 
 #
 # Open Sound System
 #
-CONFIG_SOUND_PRIME=y
-# CONFIG_SOUND_TRIDENT is not set
-# CONFIG_SOUND_MSNDCLAS is not set
-# CONFIG_SOUND_MSNDPIN is not set
-# CONFIG_SOUND_OSS is not set
+# CONFIG_SOUND_PRIME is not set
 CONFIG_HID_SUPPORT=y
 CONFIG_HID=y
-# CONFIG_HID_DEBUG is not set
+CONFIG_HID_DEBUG=y
+CONFIG_HIDRAW=y
 
 #
 # USB Input Devices
 #
 CONFIG_USB_HID=y
-# CONFIG_USB_HIDINPUT_POWERBOOK is not set
-# CONFIG_HID_FF is not set
-# CONFIG_USB_HIDDEV is not set
+CONFIG_USB_HIDINPUT_POWERBOOK=y
+CONFIG_HID_FF=y
+CONFIG_HID_PID=y
+CONFIG_LOGITECH_FF=y
+# CONFIG_LOGIRUMBLEPAD2_FF is not set
+CONFIG_PANTHERLORD_FF=y
+CONFIG_THRUSTMASTER_FF=y
+CONFIG_ZEROPLUS_FF=y
+CONFIG_USB_HIDDEV=y
 CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
 CONFIG_USB_ARCH_HAS_OHCI=y
 CONFIG_USB_ARCH_HAS_EHCI=y
 CONFIG_USB=y
-# CONFIG_USB_DEBUG is not set
+CONFIG_USB_DEBUG=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
 
 #
 # Miscellaneous USB options
@@ -992,18 +1631,18 @@ CONFIG_USB=y
 CONFIG_USB_DEVICEFS=y
 # CONFIG_USB_DEVICE_CLASS is not set
 # CONFIG_USB_DYNAMIC_MINORS is not set
-# CONFIG_USB_SUSPEND is not set
-# CONFIG_USB_PERSIST is not set
+CONFIG_USB_SUSPEND=y
 # CONFIG_USB_OTG is not set
 
 #
 # USB Host Controller Drivers
 #
+# CONFIG_USB_C67X00_HCD is not set
 CONFIG_USB_EHCI_HCD=y
-# CONFIG_USB_EHCI_SPLIT_ISO is not set
 # CONFIG_USB_EHCI_ROOT_HUB_TT is not set
 # CONFIG_USB_EHCI_TT_NEWSCHED is not set
 # CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
 CONFIG_USB_OHCI_HCD=y
 # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
 # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
@@ -1036,8 +1675,10 @@ CONFIG_USB_STORAGE=y
 # CONFIG_USB_STORAGE_SDDR55 is not set
 # CONFIG_USB_STORAGE_JUMPSHOT is not set
 # CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
 # CONFIG_USB_STORAGE_KARMA is not set
-# CONFIG_USB_LIBUSUAL is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+CONFIG_USB_LIBUSUAL=y
 
 #
 # USB Imaging devices
@@ -1049,10 +1690,6 @@ CONFIG_USB_MON=y
 #
 # USB port drivers
 #
-
-#
-# USB Serial Converter support
-#
 # CONFIG_USB_SERIAL is not set
 
 #
@@ -1078,98 +1715,126 @@ CONFIG_USB_MON=y
 # CONFIG_USB_TRANCEVIBRATOR is not set
 # CONFIG_USB_IOWARRIOR is not set
 # CONFIG_USB_TEST is not set
+# CONFIG_USB_GADGET is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
 
 #
-# USB DSL modem support
+# LED drivers
 #
+# CONFIG_LEDS_CLEVO_MAIL is not set
 
 #
-# USB Gadget Support
+# LED Triggers
 #
-# CONFIG_USB_GADGET is not set
-# CONFIG_MMC is not set
+CONFIG_LEDS_TRIGGERS=y
+# CONFIG_LEDS_TRIGGER_TIMER is not set
+# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+CONFIG_EDAC=y
 
 #
-# LED devices
+# Reporting subsystems
 #
-# CONFIG_NEW_LEDS is not set
+# CONFIG_EDAC_DEBUG is not set
+# CONFIG_EDAC_MM_EDAC is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_HCTOSYS is not set
+# CONFIG_RTC_DEBUG is not set
 
 #
-# LED drivers
+# RTC interfaces
 #
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
 
 #
-# LED Triggers
+# I2C RTC drivers
 #
-# CONFIG_INFINIBAND is not set
-# CONFIG_EDAC is not set
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
 
 #
-# Real Time Clock
+# SPI RTC drivers
 #
-# CONFIG_RTC_CLASS is not set
 
 #
-# DMA Engine support
+# Platform RTC drivers
 #
-# CONFIG_DMA_ENGINE is not set
+CONFIG_RTC_DRV_CMOS=y
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_V3020 is not set
 
 #
-# DMA Clients
+# on-CPU RTC drivers
 #
+CONFIG_DMADEVICES=y
 
 #
 # DMA Devices
 #
-CONFIG_VIRTUALIZATION=y
-# CONFIG_KVM is not set
-
-#
-# Userspace I/O
-#
+# CONFIG_INTEL_IOATDMA is not set
 # CONFIG_UIO is not set
 
 #
 # Firmware Drivers
 #
 # CONFIG_EDD is not set
+CONFIG_EFI_VARS=y
 # CONFIG_DELL_RBU is not set
 # CONFIG_DCDBAS is not set
 CONFIG_DMIID=y
+# CONFIG_ISCSI_IBFT_FIND is not set
 
 #
 # File systems
 #
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_POSIX_ACL=y
-# CONFIG_EXT2_FS_SECURITY is not set
-# CONFIG_EXT2_FS_XIP is not set
+# CONFIG_EXT2_FS is not set
 CONFIG_EXT3_FS=y
 CONFIG_EXT3_FS_XATTR=y
 CONFIG_EXT3_FS_POSIX_ACL=y
-# CONFIG_EXT3_FS_SECURITY is not set
+CONFIG_EXT3_FS_SECURITY=y
 # CONFIG_EXT4DEV_FS is not set
 CONFIG_JBD=y
 # CONFIG_JBD_DEBUG is not set
 CONFIG_FS_MBCACHE=y
-CONFIG_REISERFS_FS=y
-# CONFIG_REISERFS_CHECK is not set
-# CONFIG_REISERFS_PROC_INFO is not set
-CONFIG_REISERFS_FS_XATTR=y
-CONFIG_REISERFS_FS_POSIX_ACL=y
-# CONFIG_REISERFS_FS_SECURITY is not set
+# CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 CONFIG_FS_POSIX_ACL=y
 # CONFIG_XFS_FS is not set
 # CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
+CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
-# CONFIG_QUOTA is not set
-CONFIG_DNOTIFY=y
+CONFIG_QUOTA=y
+CONFIG_QUOTA_NETLINK_INTERFACE=y
+# CONFIG_PRINT_QUOTA_WARNING is not set
+# CONFIG_QFMT_V1 is not set
+CONFIG_QFMT_V2=y
+CONFIG_QUOTACTL=y
 # CONFIG_AUTOFS_FS is not set
 CONFIG_AUTOFS4_FS=y
 # CONFIG_FUSE_FS is not set
@@ -1180,7 +1845,7 @@ CONFIG_GENERIC_ACL=y
 #
 CONFIG_ISO9660_FS=y
 CONFIG_JOLIET=y
-# CONFIG_ZISOFS is not set
+CONFIG_ZISOFS=y
 # CONFIG_UDF_FS is not set
 
 #
@@ -1198,13 +1863,13 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 #
 CONFIG_PROC_FS=y
 CONFIG_PROC_KCORE=y
+CONFIG_PROC_VMCORE=y
 CONFIG_PROC_SYSCTL=y
 CONFIG_SYSFS=y
 CONFIG_TMPFS=y
 CONFIG_TMPFS_POSIX_ACL=y
 CONFIG_HUGETLBFS=y
 CONFIG_HUGETLB_PAGE=y
-CONFIG_RAMFS=y
 # CONFIG_CONFIGFS_FS is not set
 
 #
@@ -1212,6 +1877,7 @@ CONFIG_RAMFS=y
 #
 # CONFIG_ADFS_FS is not set
 # CONFIG_AFFS_FS is not set
+# CONFIG_ECRYPT_FS is not set
 # CONFIG_HFS_FS is not set
 # CONFIG_HFSPLUS_FS is not set
 # CONFIG_BEFS_FS is not set
@@ -1219,33 +1885,15 @@ CONFIG_RAMFS=y
 # CONFIG_EFS_FS is not set
 # CONFIG_CRAMFS is not set
 # CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-# CONFIG_NFS_V3_ACL is not set
-# CONFIG_NFS_V4 is not set
-# CONFIG_NFS_DIRECTIO is not set
-CONFIG_NFSD=y
-CONFIG_NFSD_V3=y
-# CONFIG_NFSD_V3_ACL is not set
-# CONFIG_NFSD_V4 is not set
-CONFIG_NFSD_TCP=y
-CONFIG_ROOT_NFS=y
-CONFIG_LOCKD=y
-CONFIG_LOCKD_V4=y
-CONFIG_EXPORTFS=y
-CONFIG_NFS_COMMON=y
-CONFIG_SUNRPC=y
-# CONFIG_SUNRPC_BIND34 is not set
-# CONFIG_RPCSEC_GSS_KRB5 is not set
-# CONFIG_RPCSEC_GSS_SPKM3 is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+# CONFIG_NFS_FS is not set
+# CONFIG_NFSD is not set
 # CONFIG_SMB_FS is not set
 # CONFIG_CIFS is not set
 # CONFIG_NCP_FS is not set
@@ -1255,14 +1903,26 @@ CONFIG_SUNRPC=y
 #
 # Partition Types
 #
-# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+CONFIG_OSF_PARTITION=y
+CONFIG_AMIGA_PARTITION=y
+# CONFIG_ATARI_PARTITION is not set
+CONFIG_MAC_PARTITION=y
 CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
+CONFIG_BSD_DISKLABEL=y
+CONFIG_MINIX_SUBPARTITION=y
+CONFIG_SOLARIS_X86_PARTITION=y
+CONFIG_UNIXWARE_DISKLABEL=y
+# CONFIG_LDM_PARTITION is not set
+CONFIG_SGI_PARTITION=y
+# CONFIG_ULTRIX_PARTITION is not set
+CONFIG_SUN_PARTITION=y
+CONFIG_KARMA_PARTITION=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_SYSV68_PARTITION is not set
 CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_DEFAULT="utf8"
 CONFIG_NLS_CODEPAGE_437=y
 # CONFIG_NLS_CODEPAGE_737 is not set
 # CONFIG_NLS_CODEPAGE_775 is not set
@@ -1297,40 +1957,33 @@ CONFIG_NLS_ISO8859_1=y
 # CONFIG_NLS_ISO8859_9 is not set
 # CONFIG_NLS_ISO8859_13 is not set
 # CONFIG_NLS_ISO8859_14 is not set
-CONFIG_NLS_ISO8859_15=y
+# CONFIG_NLS_ISO8859_15 is not set
 # CONFIG_NLS_KOI8_R is not set
 # CONFIG_NLS_KOI8_U is not set
 CONFIG_NLS_UTF8=y
-
-#
-# Distributed Lock Manager
-#
 # CONFIG_DLM is not set
 
 #
-# Instrumentation Support
-#
-CONFIG_PROFILING=y
-CONFIG_OPROFILE=y
-CONFIG_KPROBES=y
-
-#
 # Kernel hacking
 #
 CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 # CONFIG_PRINTK_TIME is not set
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
 # CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=2048
 CONFIG_MAGIC_SYSRQ=y
-CONFIG_UNUSED_SYMBOLS=y
+# CONFIG_UNUSED_SYMBOLS is not set
 CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_CHECK is not set
 CONFIG_DEBUG_KERNEL=y
 # CONFIG_DEBUG_SHIRQ is not set
-CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_DETECT_SOFTLOCKUP is not set
 # CONFIG_SCHED_DEBUG is not set
-# CONFIG_SCHEDSTATS is not set
+CONFIG_SCHEDSTATS=y
 CONFIG_TIMER_STATS=y
-# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
 # CONFIG_DEBUG_RT_MUTEXES is not set
 # CONFIG_RT_MUTEX_TESTER is not set
 # CONFIG_DEBUG_SPINLOCK is not set
@@ -1344,28 +1997,162 @@ CONFIG_TIMER_STATS=y
 CONFIG_DEBUG_BUGVERBOSE=y
 # CONFIG_DEBUG_INFO is not set
 # CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
 # CONFIG_DEBUG_LIST is not set
-# CONFIG_FRAME_POINTER is not set
-CONFIG_OPTIMIZE_INLINING=y
+# CONFIG_DEBUG_SG is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_KPROBES_SANITY_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
 # CONFIG_LKDTM is not set
 # CONFIG_FAULT_INJECTION is not set
-# CONFIG_DEBUG_RODATA is not set
-# CONFIG_IOMMU_DEBUG is not set
+# CONFIG_LATENCYTOP is not set
+CONFIG_PROVIDE_OHCI1394_DMA_INIT=y
+# CONFIG_SAMPLES is not set
+# CONFIG_KGDB is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_NONPROMISC_DEVMEM is not set
+CONFIG_EARLY_PRINTK=y
 CONFIG_DEBUG_STACKOVERFLOW=y
-# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_STACK_USAGE=y
+# CONFIG_DEBUG_PAGEALLOC is not set
+# CONFIG_DEBUG_PER_CPU_MAPS is not set
+# CONFIG_X86_PTDUMP is not set
+CONFIG_DEBUG_RODATA=y
+# CONFIG_DIRECT_GBPAGES is not set
+# CONFIG_DEBUG_RODATA_TEST is not set
+CONFIG_DEBUG_NX_TEST=m
+CONFIG_X86_MPPARSE=y
+# CONFIG_IOMMU_DEBUG is not set
+CONFIG_IO_DELAY_TYPE_0X80=0
+CONFIG_IO_DELAY_TYPE_0XED=1
+CONFIG_IO_DELAY_TYPE_UDELAY=2
+CONFIG_IO_DELAY_TYPE_NONE=3
+CONFIG_IO_DELAY_0X80=y
+# CONFIG_IO_DELAY_0XED is not set
+# CONFIG_IO_DELAY_UDELAY is not set
+# CONFIG_IO_DELAY_NONE is not set
+CONFIG_DEFAULT_IO_DELAY_TYPE=0
+CONFIG_DEBUG_BOOT_PARAMS=y
+# CONFIG_CPA_DEBUG is not set
 
 #
 # Security options
 #
-# CONFIG_KEYS is not set
-# CONFIG_SECURITY is not set
-# CONFIG_CRYPTO is not set
+CONFIG_KEYS=y
+CONFIG_KEYS_DEBUG_PROC_KEYS=y
+CONFIG_SECURITY=y
+CONFIG_SECURITY_NETWORK=y
+# CONFIG_SECURITY_NETWORK_XFRM is not set
+CONFIG_SECURITY_CAPABILITIES=y
+CONFIG_SECURITY_FILE_CAPABILITIES=y
+# CONFIG_SECURITY_ROOTPLUG is not set
+CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=65536
+CONFIG_SECURITY_SELINUX=y
+CONFIG_SECURITY_SELINUX_BOOTPARAM=y
+CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=1
+CONFIG_SECURITY_SELINUX_DISABLE=y
+CONFIG_SECURITY_SELINUX_DEVELOP=y
+CONFIG_SECURITY_SELINUX_AVC_STATS=y
+CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1
+# CONFIG_SECURITY_SELINUX_ENABLE_SECMARK_DEFAULT is not set
+# CONFIG_SECURITY_SELINUX_POLICYDB_VERSION_MAX is not set
+# CONFIG_SECURITY_SMACK is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_MANAGER=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_AUTHENC=y
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=y
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=y
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+CONFIG_CRYPTO_SHA1=y
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_AES_X86_64 is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+CONFIG_CRYPTO_ARC4=y
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SALSA20_X86_64 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# CONFIG_CRYPTO_TWOFISH_X86_64 is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_DEV_HIFN_795X is not set
+CONFIG_HAVE_KVM=y
+CONFIG_VIRTUALIZATION=y
+# CONFIG_KVM is not set
+# CONFIG_VIRTIO_PCI is not set
+# CONFIG_VIRTIO_BALLOON is not set
 
 #
 # Library routines
 #
 CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_FIRST_BIT=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
 # CONFIG_CRC_CCITT is not set
 # CONFIG_CRC16 is not set
 # CONFIG_CRC_ITU_T is not set
diff --git a/arch/x86/ia32/ia32entry.S b/arch/x86/ia32/ia32entry.S
index b5e329da166c..20371d0635e4 100644
--- a/arch/x86/ia32/ia32entry.S
+++ b/arch/x86/ia32/ia32entry.S
@@ -61,6 +61,19 @@
         CFI_UNDEFINED   r15
         .endm
 
+#ifdef CONFIG_PARAVIRT
+ENTRY(native_usergs_sysret32)
+        swapgs
+        sysretl
+ENDPROC(native_usergs_sysret32)
+
+ENTRY(native_irq_enable_sysexit)
+        swapgs
+        sti
+        sysexit
+ENDPROC(native_irq_enable_sysexit)
+#endif
+
 /*
  * 32bit SYSENTER instruction entry.
  *
@@ -85,14 +98,14 @@ ENTRY(ia32_sysenter_target)
         CFI_SIGNAL_FRAME
         CFI_DEF_CFA     rsp,0
         CFI_REGISTER    rsp,rbp
-        swapgs
+        SWAPGS_UNSAFE_STACK
         movq    %gs:pda_kernelstack, %rsp
         addq    $(PDA_STACKOFFSET),%rsp 
         /*
          * No need to follow this irqs on/off section: the syscall
          * disabled irqs, here we enable it straight after entry:
          */
-        sti     
+        ENABLE_INTERRUPTS(CLBR_NONE)
         movl    %ebp,%ebp               /* zero extension */
         pushq   $__USER32_DS
         CFI_ADJUST_CFA_OFFSET 8
@@ -103,7 +116,7 @@ ENTRY(ia32_sysenter_target)
         pushfq
         CFI_ADJUST_CFA_OFFSET 8
         /*CFI_REL_OFFSET rflags,0*/
-        movl    8*3-THREAD_SIZE+threadinfo_sysenter_return(%rsp), %r10d
+        movl    8*3-THREAD_SIZE+TI_sysenter_return(%rsp), %r10d
         CFI_REGISTER rip,r10
         pushq   $__USER32_CS
         CFI_ADJUST_CFA_OFFSET 8
@@ -123,8 +136,9 @@ ENTRY(ia32_sysenter_target)
         .quad 1b,ia32_badarg
         .previous       
         GET_THREAD_INFO(%r10)
-        orl    $TS_COMPAT,threadinfo_status(%r10)
-        testl  $(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT|_TIF_SECCOMP),threadinfo_flags(%r10)
+        orl    $TS_COMPAT,TI_status(%r10)
+        testl  $(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT|_TIF_SECCOMP), \
+                 TI_flags(%r10)
         CFI_REMEMBER_STATE
         jnz  sysenter_tracesys
 sysenter_do_call:       
@@ -134,11 +148,11 @@ sysenter_do_call:
         call    *ia32_sys_call_table(,%rax,8)
         movq    %rax,RAX-ARGOFFSET(%rsp)
         GET_THREAD_INFO(%r10)
-        cli
+        DISABLE_INTERRUPTS(CLBR_NONE)
         TRACE_IRQS_OFF
-        testl   $_TIF_ALLWORK_MASK,threadinfo_flags(%r10)
+        testl   $_TIF_ALLWORK_MASK,TI_flags(%r10)
         jnz     int_ret_from_sys_call
-        andl    $~TS_COMPAT,threadinfo_status(%r10)
+        andl    $~TS_COMPAT,TI_status(%r10)
         /* clear IF, that popfq doesn't enable interrupts early */
         andl  $~0x200,EFLAGS-R11(%rsp) 
         movl    RIP-R11(%rsp),%edx              /* User %eip */
@@ -151,10 +165,7 @@ sysenter_do_call:
         CFI_ADJUST_CFA_OFFSET -8
         CFI_REGISTER rsp,rcx
         TRACE_IRQS_ON
-        swapgs
-        sti             /* sti only takes effect after the next instruction */
-        /* sysexit */
-        .byte   0xf, 0x35
+        ENABLE_INTERRUPTS_SYSEXIT32
 
 sysenter_tracesys:
         CFI_RESTORE_STATE
@@ -200,7 +211,7 @@ ENTRY(ia32_cstar_target)
         CFI_DEF_CFA     rsp,PDA_STACKOFFSET
         CFI_REGISTER    rip,rcx
         /*CFI_REGISTER  rflags,r11*/
-        swapgs
+        SWAPGS_UNSAFE_STACK
         movl    %esp,%r8d
         CFI_REGISTER    rsp,r8
         movq    %gs:pda_kernelstack,%rsp
@@ -208,7 +219,7 @@ ENTRY(ia32_cstar_target)
          * No need to follow this irqs on/off section: the syscall
          * disabled irqs and here we enable it straight after entry:
          */
-        sti
+        ENABLE_INTERRUPTS(CLBR_NONE)
         SAVE_ARGS 8,1,1
         movl    %eax,%eax       /* zero extension */
         movq    %rax,ORIG_RAX-ARGOFFSET(%rsp)
@@ -230,8 +241,9 @@ ENTRY(ia32_cstar_target)
         .quad 1b,ia32_badarg
         .previous       
         GET_THREAD_INFO(%r10)
-        orl   $TS_COMPAT,threadinfo_status(%r10)
-        testl $(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT|_TIF_SECCOMP),threadinfo_flags(%r10)
+        orl   $TS_COMPAT,TI_status(%r10)
+        testl $(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT|_TIF_SECCOMP), \
+                TI_flags(%r10)
         CFI_REMEMBER_STATE
         jnz   cstar_tracesys
 cstar_do_call:  
@@ -241,11 +253,11 @@ cstar_do_call:
         call *ia32_sys_call_table(,%rax,8)
         movq %rax,RAX-ARGOFFSET(%rsp)
         GET_THREAD_INFO(%r10)
-        cli
+        DISABLE_INTERRUPTS(CLBR_NONE)
         TRACE_IRQS_OFF
-        testl $_TIF_ALLWORK_MASK,threadinfo_flags(%r10)
+        testl $_TIF_ALLWORK_MASK,TI_flags(%r10)
         jnz  int_ret_from_sys_call
-        andl $~TS_COMPAT,threadinfo_status(%r10)
+        andl $~TS_COMPAT,TI_status(%r10)
         RESTORE_ARGS 1,-ARG_SKIP,1,1,1
         movl RIP-ARGOFFSET(%rsp),%ecx
         CFI_REGISTER rip,rcx
@@ -254,8 +266,7 @@ cstar_do_call:
         TRACE_IRQS_ON
         movl RSP-ARGOFFSET(%rsp),%esp
         CFI_RESTORE rsp
-        swapgs
-        sysretl
+        USERGS_SYSRET32
         
 cstar_tracesys: 
         CFI_RESTORE_STATE
@@ -310,12 +321,12 @@ ENTRY(ia32_syscall)
         /*CFI_REL_OFFSET        rflags,EFLAGS-RIP*/
         /*CFI_REL_OFFSET        cs,CS-RIP*/
         CFI_REL_OFFSET  rip,RIP-RIP
-        swapgs
+        SWAPGS
         /*
          * No need to follow this irqs on/off section: the syscall
          * disabled irqs and here we enable it straight after entry:
          */
-        sti
+        ENABLE_INTERRUPTS(CLBR_NONE)
         movl %eax,%eax
         pushq %rax
         CFI_ADJUST_CFA_OFFSET 8
@@ -324,8 +335,9 @@ ENTRY(ia32_syscall)
            this could be a problem. */
         SAVE_ARGS 0,0,1
         GET_THREAD_INFO(%r10)
-        orl   $TS_COMPAT,threadinfo_status(%r10)
-        testl $(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT|_TIF_SECCOMP),threadinfo_flags(%r10)
+        orl   $TS_COMPAT,TI_status(%r10)
+        testl $(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT|_TIF_SECCOMP), \
+                TI_flags(%r10)
         jnz ia32_tracesys
 ia32_do_syscall:        
         cmpl $(IA32_NR_syscalls-1),%eax
@@ -370,13 +382,11 @@ quiet_ni_syscall:
         PTREGSCALL stub32_rt_sigreturn, sys32_rt_sigreturn, %rdi
         PTREGSCALL stub32_sigreturn, sys32_sigreturn, %rdi
         PTREGSCALL stub32_sigaltstack, sys32_sigaltstack, %rdx
-        PTREGSCALL stub32_sigsuspend, sys32_sigsuspend, %rcx
         PTREGSCALL stub32_execve, sys32_execve, %rcx
         PTREGSCALL stub32_fork, sys_fork, %rdi
         PTREGSCALL stub32_clone, sys32_clone, %rdx
         PTREGSCALL stub32_vfork, sys_vfork, %rdi
         PTREGSCALL stub32_iopl, sys_iopl, %rsi
-        PTREGSCALL stub32_rt_sigsuspend, sys_rt_sigsuspend, %rdx
 
 ENTRY(ia32_ptregs_common)
         popq %r11
@@ -476,7 +486,7 @@ ia32_sys_call_table:
         .quad sys_ssetmask
         .quad sys_setreuid16    /* 70 */
         .quad sys_setregid16
-        .quad stub32_sigsuspend
+        .quad sys32_sigsuspend
         .quad compat_sys_sigpending
         .quad sys_sethostname
         .quad compat_sys_setrlimit      /* 75 */
@@ -583,7 +593,7 @@ ia32_sys_call_table:
         .quad sys32_rt_sigpending
         .quad compat_sys_rt_sigtimedwait
         .quad sys32_rt_sigqueueinfo
-        .quad stub32_rt_sigsuspend
+        .quad sys_rt_sigsuspend
         .quad sys32_pread               /* 180 */
         .quad sys32_pwrite
         .quad sys_chown16
diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile
index 77807d4769c9..5112c84f5421 100644
--- a/arch/x86/kernel/Makefile
+++ b/arch/x86/kernel/Makefile
@@ -2,10 +2,17 @@
 # Makefile for the linux kernel.
 #
 
-extra-y                := head_$(BITS).o head$(BITS).o init_task.o vmlinux.lds
+extra-y                := head_$(BITS).o head$(BITS).o head.o init_task.o vmlinux.lds
 
 CPPFLAGS_vmlinux.lds += -U$(UTS_MACHINE)
 
+ifdef CONFIG_FTRACE
+# Do not profile debug utilities
+CFLAGS_REMOVE_tsc_64.o = -pg
+CFLAGS_REMOVE_tsc_32.o = -pg
+CFLAGS_REMOVE_rtc.o = -pg
+endif
+
 #
 # vsyscalls (which work on the user stack) should have
 # no stack-protector checks:
@@ -13,20 +20,21 @@ CPPFLAGS_vmlinux.lds += -U$(UTS_MACHINE)
 nostackp := $(call cc-option, -fno-stack-protector)
 CFLAGS_vsyscall_64.o    := $(PROFILING) -g0 $(nostackp)
 CFLAGS_hpet.o           := $(nostackp)
-CFLAGS_tsc_64.o         := $(nostackp)
+CFLAGS_tsc.o            := $(nostackp)
 
 obj-y                   := process_$(BITS).o signal_$(BITS).o entry_$(BITS).o
 obj-y                   += traps_$(BITS).o irq_$(BITS).o
 obj-y                   += time_$(BITS).o ioport.o ldt.o
-obj-y                   += setup_$(BITS).o i8259_$(BITS).o setup.o
+obj-y                   += setup.o i8259.o irqinit_$(BITS).o setup_percpu.o
+obj-$(CONFIG_X86_VISWS) += visws_quirks.o
+obj-$(CONFIG_X86_32)    += probe_roms_32.o
 obj-$(CONFIG_X86_32)    += sys_i386_32.o i386_ksyms_32.o
 obj-$(CONFIG_X86_64)    += sys_x86_64.o x8664_ksyms_64.o
-obj-$(CONFIG_X86_64)    += syscall_64.o vsyscall_64.o setup64.o
-obj-y                   += bootflag.o e820_$(BITS).o
+obj-$(CONFIG_X86_64)    += syscall_64.o vsyscall_64.o
+obj-y                   += bootflag.o e820.o
 obj-y                   += pci-dma.o quirks.o i8237.o topology.o kdebugfs.o
 obj-y                   += alternative.o i8253.o pci-nommu.o
-obj-$(CONFIG_X86_64)    += bugs_64.o
-obj-y                   += tsc_$(BITS).o io_delay.o rtc.o
+obj-y                   += tsc.o io_delay.o rtc.o
 
 obj-$(CONFIG_X86_TRAMPOLINE)    += trampoline.o
 obj-y                           += process.o
@@ -53,9 +61,10 @@ obj-$(CONFIG_X86_32_SMP)	+= smpcommon.o
 obj-$(CONFIG_X86_64_SMP)        += tsc_sync.o smpcommon.o
 obj-$(CONFIG_X86_TRAMPOLINE)    += trampoline_$(BITS).o
 obj-$(CONFIG_X86_MPPARSE)       += mpparse.o
-obj-$(CONFIG_X86_LOCAL_APIC)    += apic_$(BITS).o nmi_$(BITS).o
+obj-$(CONFIG_X86_LOCAL_APIC)    += apic_$(BITS).o nmi.o
 obj-$(CONFIG_X86_IO_APIC)       += io_apic_$(BITS).o
 obj-$(CONFIG_X86_REBOOTFIXUPS)  += reboot_fixups_32.o
+obj-$(CONFIG_DYNAMIC_FTRACE)    += ftrace.o
 obj-$(CONFIG_KEXEC)             += machine_kexec_$(BITS).o
 obj-$(CONFIG_KEXEC)             += relocate_kernel_$(BITS).o crash.o
 obj-$(CONFIG_CRASH_DUMP)        += crash_dump_$(BITS).o
@@ -64,7 +73,6 @@ obj-$(CONFIG_X86_SUMMIT_NUMA)	+= summit_32.o
 obj-y                           += vsmp_64.o
 obj-$(CONFIG_KPROBES)           += kprobes.o
 obj-$(CONFIG_MODULES)           += module_$(BITS).o
-obj-$(CONFIG_ACPI_SRAT)         += srat_32.o
 obj-$(CONFIG_EFI)               += efi.o efi_$(BITS).o efi_stub_$(BITS).o
 obj-$(CONFIG_DOUBLEFAULT)       += doublefault_32.o
 obj-$(CONFIG_KGDB)              += kgdb.o
@@ -94,12 +102,13 @@ obj-$(CONFIG_OLPC)		+= olpc.o
 ###
 # 64 bit specific files
 ifeq ($(CONFIG_X86_64),y)
-        obj-y                           += genapic_64.o genapic_flat_64.o genx2apic_uv_x.o
+        obj-y                           += genapic_64.o genapic_flat_64.o genx2apic_uv_x.o tlb_uv.o
         obj-$(CONFIG_X86_PM_TIMER)      += pmtimer_64.o
         obj-$(CONFIG_AUDIT)             += audit_64.o
 
         obj-$(CONFIG_GART_IOMMU)        += pci-gart_64.o aperture_64.o
         obj-$(CONFIG_CALGARY_IOMMU)     += pci-calgary_64.o tce_64.o
+        obj-$(CONFIG_AMD_IOMMU)         += amd_iommu_init.o amd_iommu.o
         obj-$(CONFIG_SWIOTLB)           += pci-swiotlb_64.o
 
         obj-$(CONFIG_PCI_MMCONFIG)      += mmconf-fam10h_64.o
diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c
index 33c5216fd3e1..f489d7a9be92 100644
--- a/arch/x86/kernel/acpi/boot.c
+++ b/arch/x86/kernel/acpi/boot.c
@@ -37,6 +37,7 @@
 #include <asm/pgtable.h>
 #include <asm/io_apic.h>
 #include <asm/apic.h>
+#include <asm/genapic.h>
 #include <asm/io.h>
 #include <asm/mpspec.h>
 #include <asm/smp.h>
@@ -106,21 +107,6 @@ static u64 acpi_lapic_addr __initdata = APIC_DEFAULT_PHYS_BASE;
  */
 enum acpi_irq_model_id acpi_irq_model = ACPI_IRQ_MODEL_PIC;
 
-#ifdef  CONFIG_X86_64
-
-/* rely on all ACPI tables being in the direct mapping */
-char *__init __acpi_map_table(unsigned long phys_addr, unsigned long size)
-{
-        if (!phys_addr || !size)
-                return NULL;
-
-        if (phys_addr+size <= (max_pfn_mapped << PAGE_SHIFT) + PAGE_SIZE)
-                return __va(phys_addr);
-
-        return NULL;
-}
-
-#else
 
 /*
  * Temporarily use the virtual area starting from FIX_IO_APIC_BASE_END,
@@ -139,11 +125,15 @@ char *__init __acpi_map_table(unsigned long phys, unsigned long size)
         unsigned long base, offset, mapped_size;
         int idx;
 
-        if (phys + size < 8 * 1024 * 1024)
+        if (!phys || !size)
+                return NULL;
+
+        if (phys+size <= (max_low_pfn_mapped << PAGE_SHIFT))
                 return __va(phys);
 
         offset = phys & (PAGE_SIZE - 1);
         mapped_size = PAGE_SIZE - offset;
+        clear_fixmap(FIX_ACPI_END);
         set_fixmap(FIX_ACPI_END, phys);
         base = fix_to_virt(FIX_ACPI_END);
 
@@ -155,13 +145,13 @@ char *__init __acpi_map_table(unsigned long phys, unsigned long size)
                 if (--idx < FIX_ACPI_BEGIN)
                         return NULL;    /* cannot handle this */
                 phys += PAGE_SIZE;
+                clear_fixmap(idx);
                 set_fixmap(idx, phys);
                 mapped_size += PAGE_SIZE;
         }
 
         return ((unsigned char *)base + offset);
 }
-#endif
 
 #ifdef CONFIG_PCI_MMCONFIG
 /* The physical address of the MMCONFIG aperture.  Set from ACPI tables. */
@@ -338,8 +328,6 @@ acpi_parse_lapic_nmi(struct acpi_subtable_header * header, const unsigned long e
 
 #ifdef CONFIG_X86_IO_APIC
 
-struct mp_ioapic_routing mp_ioapic_routing[MAX_IO_APICS];
-
 static int __init
 acpi_parse_ioapic(struct acpi_subtable_header * header, const unsigned long end)
 {
@@ -514,8 +502,6 @@ int acpi_register_gsi(u32 gsi, int triggering, int polarity)
          * Make sure all (legacy) PCI IRQs are set as level-triggered.
          */
         if (acpi_irq_model == ACPI_IRQ_MODEL_PIC) {
-                extern void eisa_set_level_irq(unsigned int irq);
-
                 if (triggering == ACPI_LEVEL_SENSITIVE)
                         eisa_set_level_irq(gsi);
         }
@@ -860,6 +846,364 @@ static int __init acpi_parse_madt_lapic_entries(void)
 #endif                          /* CONFIG_X86_LOCAL_APIC */
 
 #ifdef  CONFIG_X86_IO_APIC
+#define MP_ISA_BUS              0
+
+#ifdef CONFIG_X86_ES7000
+extern int es7000_plat;
+#endif
+
+static struct {
+        int apic_id;
+        int gsi_base;
+        int gsi_end;
+        DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
+} mp_ioapic_routing[MAX_IO_APICS];
+
+static int mp_find_ioapic(int gsi)
+{
+        int i = 0;
+
+        /* Find the IOAPIC that manages this GSI. */
+        for (i = 0; i < nr_ioapics; i++) {
+                if ((gsi >= mp_ioapic_routing[i].gsi_base)
+                    && (gsi <= mp_ioapic_routing[i].gsi_end))
+                        return i;
+        }
+
+        printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
+        return -1;
+}
+
+static u8 __init uniq_ioapic_id(u8 id)
+{
+#ifdef CONFIG_X86_32
+        if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
+            !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
+                return io_apic_get_unique_id(nr_ioapics, id);
+        else
+                return id;
+#else
+        int i;
+        DECLARE_BITMAP(used, 256);
+        bitmap_zero(used, 256);
+        for (i = 0; i < nr_ioapics; i++) {
+                struct mp_config_ioapic *ia = &mp_ioapics[i];
+                __set_bit(ia->mp_apicid, used);
+        }
+        if (!test_bit(id, used))
+                return id;
+        return find_first_zero_bit(used, 256);
+#endif
+}
+
+static int bad_ioapic(unsigned long address)
+{
+        if (nr_ioapics >= MAX_IO_APICS) {
+                printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
+                       "(found %d)\n", MAX_IO_APICS, nr_ioapics);
+                panic("Recompile kernel with bigger MAX_IO_APICS!\n");
+        }
+        if (!address) {
+                printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
+                       " found in table, skipping!\n");
+                return 1;
+        }
+        return 0;
+}
+
+void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
+{
+        int idx = 0;
+
+        if (bad_ioapic(address))
+                return;
+
+        idx = nr_ioapics;
+
+        mp_ioapics[idx].mp_type = MP_IOAPIC;
+        mp_ioapics[idx].mp_flags = MPC_APIC_USABLE;
+        mp_ioapics[idx].mp_apicaddr = address;
+
+        set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
+        mp_ioapics[idx].mp_apicid = uniq_ioapic_id(id);
+#ifdef CONFIG_X86_32
+        mp_ioapics[idx].mp_apicver = io_apic_get_version(idx);
+#else
+        mp_ioapics[idx].mp_apicver = 0;
+#endif
+        /*
+         * Build basic GSI lookup table to facilitate gsi->io_apic lookups
+         * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
+         */
+        mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mp_apicid;
+        mp_ioapic_routing[idx].gsi_base = gsi_base;
+        mp_ioapic_routing[idx].gsi_end = gsi_base +
+            io_apic_get_redir_entries(idx);
+
+        printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%lx, "
+               "GSI %d-%d\n", idx, mp_ioapics[idx].mp_apicid,
+               mp_ioapics[idx].mp_apicver, mp_ioapics[idx].mp_apicaddr,
+               mp_ioapic_routing[idx].gsi_base, mp_ioapic_routing[idx].gsi_end);
+
+        nr_ioapics++;
+}
+
+static void assign_to_mp_irq(struct mp_config_intsrc *m,
+                                    struct mp_config_intsrc *mp_irq)
+{
+        memcpy(mp_irq, m, sizeof(struct mp_config_intsrc));
+}
+
+static int mp_irq_cmp(struct mp_config_intsrc *mp_irq,
+                                struct mp_config_intsrc *m)
+{
+        return memcmp(mp_irq, m, sizeof(struct mp_config_intsrc));
+}
+
+static void save_mp_irq(struct mp_config_intsrc *m)
+{
+        int i;
+
+        for (i = 0; i < mp_irq_entries; i++) {
+                if (!mp_irq_cmp(&mp_irqs[i], m))
+                        return;
+        }
+
+        assign_to_mp_irq(m, &mp_irqs[mp_irq_entries]);
+        if (++mp_irq_entries == MAX_IRQ_SOURCES)
+                panic("Max # of irq sources exceeded!!\n");
+}
+
+void __init mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi)
+{
+        int ioapic;
+        int pin;
+        struct mp_config_intsrc mp_irq;
+
+        /*
+         * Convert 'gsi' to 'ioapic.pin'.
+         */
+        ioapic = mp_find_ioapic(gsi);
+        if (ioapic < 0)
+                return;
+        pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
+
+        /*
+         * TBD: This check is for faulty timer entries, where the override
+         *      erroneously sets the trigger to level, resulting in a HUGE
+         *      increase of timer interrupts!
+         */
+        if ((bus_irq == 0) && (trigger == 3))
+                trigger = 1;
+
+        mp_irq.mp_type = MP_INTSRC;
+        mp_irq.mp_irqtype = mp_INT;
+        mp_irq.mp_irqflag = (trigger << 2) | polarity;
+        mp_irq.mp_srcbus = MP_ISA_BUS;
+        mp_irq.mp_srcbusirq = bus_irq;  /* IRQ */
+        mp_irq.mp_dstapic = mp_ioapics[ioapic].mp_apicid; /* APIC ID */
+        mp_irq.mp_dstirq = pin; /* INTIN# */
+
+        save_mp_irq(&mp_irq);
+}
+
+void __init mp_config_acpi_legacy_irqs(void)
+{
+        int i;
+        int ioapic;
+        unsigned int dstapic;
+        struct mp_config_intsrc mp_irq;
+
+#if defined (CONFIG_MCA) || defined (CONFIG_EISA)
+        /*
+         * Fabricate the legacy ISA bus (bus #31).
+         */
+        mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA;
+#endif
+        set_bit(MP_ISA_BUS, mp_bus_not_pci);
+        Dprintk("Bus #%d is ISA\n", MP_ISA_BUS);
+
+#ifdef CONFIG_X86_ES7000
+        /*
+         * Older generations of ES7000 have no legacy identity mappings
+         */
+        if (es7000_plat == 1)
+                return;
+#endif
+
+        /*
+         * Locate the IOAPIC that manages the ISA IRQs (0-15).
+         */
+        ioapic = mp_find_ioapic(0);
+        if (ioapic < 0)
+                return;
+        dstapic = mp_ioapics[ioapic].mp_apicid;
+
+        /*
+         * Use the default configuration for the IRQs 0-15.  Unless
+         * overridden by (MADT) interrupt source override entries.
+         */
+        for (i = 0; i < 16; i++) {
+                int idx;
+
+                for (idx = 0; idx < mp_irq_entries; idx++) {
+                        struct mp_config_intsrc *irq = mp_irqs + idx;
+
+                        /* Do we already have a mapping for this ISA IRQ? */
+                        if (irq->mp_srcbus == MP_ISA_BUS
+                            && irq->mp_srcbusirq == i)
+                                break;
+
+                        /* Do we already have a mapping for this IOAPIC pin */
+                        if (irq->mp_dstapic == dstapic &&
+                            irq->mp_dstirq == i)
+                                break;
+                }
+
+                if (idx != mp_irq_entries) {
+                        printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
+                        continue;       /* IRQ already used */
+                }
+
+                mp_irq.mp_type = MP_INTSRC;
+                mp_irq.mp_irqflag = 0;  /* Conforming */
+                mp_irq.mp_srcbus = MP_ISA_BUS;
+                mp_irq.mp_dstapic = dstapic;
+                mp_irq.mp_irqtype = mp_INT;
+                mp_irq.mp_srcbusirq = i; /* Identity mapped */
+                mp_irq.mp_dstirq = i;
+
+                save_mp_irq(&mp_irq);
+        }
+}
+
+int mp_register_gsi(u32 gsi, int triggering, int polarity)
+{
+        int ioapic;
+        int ioapic_pin;
+#ifdef CONFIG_X86_32
+#define MAX_GSI_NUM     4096
+#define IRQ_COMPRESSION_START   64
+
+        static int pci_irq = IRQ_COMPRESSION_START;
+        /*
+         * Mapping between Global System Interrupts, which
+         * represent all possible interrupts, and IRQs
+         * assigned to actual devices.
+         */
+        static int gsi_to_irq[MAX_GSI_NUM];
+#else
+
+        if (acpi_irq_model != ACPI_IRQ_MODEL_IOAPIC)
+                return gsi;
+#endif
+
+        /* Don't set up the ACPI SCI because it's already set up */
+        if (acpi_gbl_FADT.sci_interrupt == gsi)
+                return gsi;
+
+        ioapic = mp_find_ioapic(gsi);
+        if (ioapic < 0) {
+                printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
+                return gsi;
+        }
+
+        ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
+
+#ifdef CONFIG_X86_32
+        if (ioapic_renumber_irq)
+                gsi = ioapic_renumber_irq(ioapic, gsi);
+#endif
+
+        /*
+         * Avoid pin reprogramming.  PRTs typically include entries
+         * with redundant pin->gsi mappings (but unique PCI devices);
+         * we only program the IOAPIC on the first.
+         */
+        if (ioapic_pin > MP_MAX_IOAPIC_PIN) {
+                printk(KERN_ERR "Invalid reference to IOAPIC pin "
+                       "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
+                       ioapic_pin);
+                return gsi;
+        }
+        if (test_bit(ioapic_pin, mp_ioapic_routing[ioapic].pin_programmed)) {
+                Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
+                        mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
+#ifdef CONFIG_X86_32
+                return (gsi < IRQ_COMPRESSION_START ? gsi : gsi_to_irq[gsi]);
+#else
+                return gsi;
+#endif
+        }
+
+        set_bit(ioapic_pin, mp_ioapic_routing[ioapic].pin_programmed);
+#ifdef CONFIG_X86_32
+        /*
+         * For GSI >= 64, use IRQ compression
+         */
+        if ((gsi >= IRQ_COMPRESSION_START)
+            && (triggering == ACPI_LEVEL_SENSITIVE)) {
+                /*
+                 * For PCI devices assign IRQs in order, avoiding gaps
+                 * due to unused I/O APIC pins.
+                 */
+                int irq = gsi;
+                if (gsi < MAX_GSI_NUM) {
+                        /*
+                         * Retain the VIA chipset work-around (gsi > 15), but
+                         * avoid a problem where the 8254 timer (IRQ0) is setup
+                         * via an override (so it's not on pin 0 of the ioapic),
+                         * and at the same time, the pin 0 interrupt is a PCI
+                         * type.  The gsi > 15 test could cause these two pins
+                         * to be shared as IRQ0, and they are not shareable.
+                         * So test for this condition, and if necessary, avoid
+                         * the pin collision.
+                         */
+                        gsi = pci_irq++;
+                        /*
+                         * Don't assign IRQ used by ACPI SCI
+                         */
+                        if (gsi == acpi_gbl_FADT.sci_interrupt)
+                                gsi = pci_irq++;
+                        gsi_to_irq[irq] = gsi;
+                } else {
+                        printk(KERN_ERR "GSI %u is too high\n", gsi);
+                        return gsi;
+                }
+        }
+#endif
+        io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
+                                triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
+                                polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
+        return gsi;
+}
+
+int mp_config_acpi_gsi(unsigned char number, unsigned int devfn, u8 pin,
+                        u32 gsi, int triggering, int polarity)
+{
+#ifdef CONFIG_X86_MPPARSE
+        struct mp_config_intsrc mp_irq;
+        int ioapic;
+
+        if (!acpi_ioapic)
+                return 0;
+
+        /* print the entry should happen on mptable identically */
+        mp_irq.mp_type = MP_INTSRC;
+        mp_irq.mp_irqtype = mp_INT;
+        mp_irq.mp_irqflag = (triggering == ACPI_EDGE_SENSITIVE ? 4 : 0x0c) |
+                                (polarity == ACPI_ACTIVE_HIGH ? 1 : 3);
+        mp_irq.mp_srcbus = number;
+        mp_irq.mp_srcbusirq = (((devfn >> 3) & 0x1f) << 2) | ((pin - 1) & 3);
+        ioapic = mp_find_ioapic(gsi);
+        mp_irq.mp_dstapic = mp_ioapic_routing[ioapic].apic_id;
+        mp_irq.mp_dstirq = gsi - mp_ioapic_routing[ioapic].gsi_base;
+
+        save_mp_irq(&mp_irq);
+#endif
+        return 0;
+}
+
 /*
  * Parse IOAPIC related entries in MADT
  * returns 0 on success, < 0 on error
@@ -1009,8 +1353,6 @@ static void __init acpi_process_madt(void)
         return;
 }
 
-#ifdef __i386__
-
 static int __init disable_acpi_irq(const struct dmi_system_id *d)
 {
         if (!acpi_force) {
@@ -1061,6 +1403,16 @@ static int __init force_acpi_ht(const struct dmi_system_id *d)
 }
 
 /*
+ * Force ignoring BIOS IRQ0 pin2 override
+ */
+static int __init dmi_ignore_irq0_timer_override(const struct dmi_system_id *d)
+{
+        pr_notice("%s detected: Ignoring BIOS IRQ0 pin2 override\n", d->ident);
+        acpi_skip_timer_override = 1;
+        return 0;
+}
+
+/*
  * If your system is blacklisted here, but you find that acpi=force
  * works for you, please contact acpi-devel@sourceforge.net
  */
@@ -1227,11 +1579,35 @@ static struct dmi_system_id __initdata acpi_dmi_table[] = {
                      DMI_MATCH(DMI_PRODUCT_NAME, "TravelMate 360"),
                      },
          },
+        /*
+         * HP laptops which use a DSDT reporting as HP/SB400/10000,
+         * which includes some code which overrides all temperature
+         * trip points to 16C if the INTIN2 input of the I/O APIC
+         * is enabled.  This input is incorrectly designated the
+         * ISA IRQ 0 via an interrupt source override even though
+         * it is wired to the output of the master 8259A and INTIN0
+         * is not connected at all.  Force ignoring BIOS IRQ0 pin2
+         * override in that cases.
+         */
+        {
+         .callback = dmi_ignore_irq0_timer_override,
+         .ident = "HP NX6125 laptop",
+         .matches = {
+                     DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
+                     DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6125"),
+                     },
+         },
+        {
+         .callback = dmi_ignore_irq0_timer_override,
+         .ident = "HP NX6325 laptop",
+         .matches = {
+                     DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
+                     DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6325"),
+                     },
+         },
         {}
 };
 
-#endif                          /* __i386__ */
-
 /*
  * acpi_boot_table_init() and acpi_boot_init()
  *  called from setup_arch(), always.
@@ -1259,9 +1635,7 @@ int __init acpi_boot_table_init(void)
 {
         int error;
 
-#ifdef __i386__
         dmi_check_system(acpi_dmi_table);
-#endif
 
         /*
          * If acpi_disabled, bail out
@@ -1386,6 +1760,20 @@ static int __init parse_pci(char *arg)
 }
 early_param("pci", parse_pci);
 
+int __init acpi_mps_check(void)
+{
+#if defined(CONFIG_X86_LOCAL_APIC) && !defined(CONFIG_X86_MPPARSE)
+/* mptable code is not built-in*/
+        if (acpi_disabled || acpi_noirq) {
+                printk(KERN_WARNING "MPS support code is not built-in.\n"
+                       "Using acpi=off or acpi=noirq or pci=noacpi "
+                       "may have problem\n");
+                return 1;
+        }
+#endif
+        return 0;
+}
+
 #ifdef CONFIG_X86_IO_APIC
 static int __init parse_acpi_skip_timer_override(char *arg)
 {
diff --git a/arch/x86/kernel/acpi/sleep.c b/arch/x86/kernel/acpi/sleep.c
index 36af01f029ed..e6a4b564ccaa 100644
--- a/arch/x86/kernel/acpi/sleep.c
+++ b/arch/x86/kernel/acpi/sleep.c
@@ -86,7 +86,9 @@ int acpi_save_state_mem(void)
         saved_magic = 0x12345678;
 #else /* CONFIG_64BIT */
         header->trampoline_segment = setup_trampoline() >> 4;
-        init_rsp = (unsigned long)temp_stack + 4096;
+#ifdef CONFIG_SMP
+        stack_start.sp = temp_stack + 4096;
+#endif
         initial_code = (unsigned long)wakeup_long64;
         saved_magic = 0x123456789abcdef0;
 #endif /* CONFIG_64BIT */
diff --git a/arch/x86/kernel/alternative.c b/arch/x86/kernel/alternative.c
index 65c7857a90dd..2763cb37b553 100644
--- a/arch/x86/kernel/alternative.c
+++ b/arch/x86/kernel/alternative.c
@@ -1,6 +1,6 @@
 #include <linux/module.h>
 #include <linux/sched.h>
-#include <linux/spinlock.h>
+#include <linux/mutex.h>
 #include <linux/list.h>
 #include <linux/kprobes.h>
 #include <linux/mm.h>
@@ -143,7 +143,7 @@ static const unsigned char *const p6_nops[ASM_NOP_MAX+1] = {
 #ifdef CONFIG_X86_64
 
 extern char __vsyscall_0;
-static inline const unsigned char*const * find_nop_table(void)
+const unsigned char *const *find_nop_table(void)
 {
         return boot_cpu_data.x86_vendor != X86_VENDOR_INTEL ||
                boot_cpu_data.x86 < 6 ? k8_nops : p6_nops;
@@ -162,7 +162,7 @@ static const struct nop {
         { -1, NULL }
 };
 
-static const unsigned char*const * find_nop_table(void)
+const unsigned char *const *find_nop_table(void)
 {
         const unsigned char *const *noptable = intel_nops;
         int i;
@@ -279,7 +279,7 @@ struct smp_alt_module {
         struct list_head next;
 };
 static LIST_HEAD(smp_alt_modules);
-static DEFINE_SPINLOCK(smp_alt);
+static DEFINE_MUTEX(smp_alt);
 static int smp_mode = 1;        /* protected by smp_alt */
 
 void alternatives_smp_module_add(struct module *mod, char *name,
@@ -312,12 +312,12 @@ void alternatives_smp_module_add(struct module *mod, char *name,
                 __func__, smp->locks, smp->locks_end,
                 smp->text, smp->text_end, smp->name);
 
-        spin_lock(&smp_alt);
+        mutex_lock(&smp_alt);
         list_add_tail(&smp->next, &smp_alt_modules);
         if (boot_cpu_has(X86_FEATURE_UP))
                 alternatives_smp_unlock(smp->locks, smp->locks_end,
                                         smp->text, smp->text_end);
-        spin_unlock(&smp_alt);
+        mutex_unlock(&smp_alt);
 }
 
 void alternatives_smp_module_del(struct module *mod)
@@ -327,17 +327,17 @@ void alternatives_smp_module_del(struct module *mod)
         if (smp_alt_once || noreplace_smp)
                 return;
 
-        spin_lock(&smp_alt);
+        mutex_lock(&smp_alt);
         list_for_each_entry(item, &smp_alt_modules, next) {
                 if (mod != item->mod)
                         continue;
                 list_del(&item->next);
-                spin_unlock(&smp_alt);
+                mutex_unlock(&smp_alt);
                 DPRINTK("%s: %s\n", __func__, item->name);
                 kfree(item);
                 return;
         }
-        spin_unlock(&smp_alt);
+        mutex_unlock(&smp_alt);
 }
 
 void alternatives_smp_switch(int smp)
@@ -359,7 +359,7 @@ void alternatives_smp_switch(int smp)
                 return;
         BUG_ON(!smp && (num_online_cpus() > 1));
 
-        spin_lock(&smp_alt);
+        mutex_lock(&smp_alt);
 
         /*
          * Avoid unnecessary switches because it forces JIT based VMs to
@@ -383,7 +383,7 @@ void alternatives_smp_switch(int smp)
                                                 mod->text, mod->text_end);
         }
         smp_mode = smp;
-        spin_unlock(&smp_alt);
+        mutex_unlock(&smp_alt);
 }
 
 #endif
diff --git a/arch/x86/kernel/amd_iommu.c b/arch/x86/kernel/amd_iommu.c
new file mode 100644
index 000000000000..f2766d84c7a0
--- /dev/null
+++ b/arch/x86/kernel/amd_iommu.c
@@ -0,0 +1,962 @@
+/*
+ * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
+ * Author: Joerg Roedel <joerg.roedel@amd.com>
+ *         Leo Duran <leo.duran@amd.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+
+#include <linux/pci.h>
+#include <linux/gfp.h>
+#include <linux/bitops.h>
+#include <linux/scatterlist.h>
+#include <linux/iommu-helper.h>
+#include <asm/proto.h>
+#include <asm/gart.h>
+#include <asm/amd_iommu_types.h>
+#include <asm/amd_iommu.h>
+
+#define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
+
+#define to_pages(addr, size) \
+         (round_up(((addr) & ~PAGE_MASK) + (size), PAGE_SIZE) >> PAGE_SHIFT)
+
+static DEFINE_RWLOCK(amd_iommu_devtable_lock);
+
+struct command {
+        u32 data[4];
+};
+
+static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
+                             struct unity_map_entry *e);
+
+static int iommu_has_npcache(struct amd_iommu *iommu)
+{
+        return iommu->cap & IOMMU_CAP_NPCACHE;
+}
+
+static int __iommu_queue_command(struct amd_iommu *iommu, struct command *cmd)
+{
+        u32 tail, head;
+        u8 *target;
+
+        tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
+        target = (iommu->cmd_buf + tail);
+        memcpy_toio(target, cmd, sizeof(*cmd));
+        tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
+        head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
+        if (tail == head)
+                return -ENOMEM;
+        writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
+
+        return 0;
+}
+
+static int iommu_queue_command(struct amd_iommu *iommu, struct command *cmd)
+{
+        unsigned long flags;
+        int ret;
+
+        spin_lock_irqsave(&iommu->lock, flags);
+        ret = __iommu_queue_command(iommu, cmd);
+        spin_unlock_irqrestore(&iommu->lock, flags);
+
+        return ret;
+}
+
+static int iommu_completion_wait(struct amd_iommu *iommu)
+{
+        int ret;
+        struct command cmd;
+        volatile u64 ready = 0;
+        unsigned long ready_phys = virt_to_phys(&ready);
+
+        memset(&cmd, 0, sizeof(cmd));
+        cmd.data[0] = LOW_U32(ready_phys) | CMD_COMPL_WAIT_STORE_MASK;
+        cmd.data[1] = HIGH_U32(ready_phys);
+        cmd.data[2] = 1; /* value written to 'ready' */
+        CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT);
+
+        iommu->need_sync = 0;
+
+        ret = iommu_queue_command(iommu, &cmd);
+
+        if (ret)
+                return ret;
+
+        while (!ready)
+                cpu_relax();
+
+        return 0;
+}
+
+static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid)
+{
+        struct command cmd;
+
+        BUG_ON(iommu == NULL);
+
+        memset(&cmd, 0, sizeof(cmd));
+        CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY);
+        cmd.data[0] = devid;
+
+        iommu->need_sync = 1;
+
+        return iommu_queue_command(iommu, &cmd);
+}
+
+static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu,
+                u64 address, u16 domid, int pde, int s)
+{
+        struct command cmd;
+
+        memset(&cmd, 0, sizeof(cmd));
+        address &= PAGE_MASK;
+        CMD_SET_TYPE(&cmd, CMD_INV_IOMMU_PAGES);
+        cmd.data[1] |= domid;
+        cmd.data[2] = LOW_U32(address);
+        cmd.data[3] = HIGH_U32(address);
+        if (s)
+                cmd.data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
+        if (pde)
+                cmd.data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
+
+        iommu->need_sync = 1;
+
+        return iommu_queue_command(iommu, &cmd);
+}
+
+static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid,
+                u64 address, size_t size)
+{
+        int s = 0;
+        unsigned pages = to_pages(address, size);
+
+        address &= PAGE_MASK;
+
+        if (pages > 1) {
+                /*
+                 * If we have to flush more than one page, flush all
+                 * TLB entries for this domain
+                 */
+                address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
+                s = 1;
+        }
+
+        iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s);
+
+        return 0;
+}
+
+static int iommu_map(struct protection_domain *dom,
+                     unsigned long bus_addr,
+                     unsigned long phys_addr,
+                     int prot)
+{
+        u64 __pte, *pte, *page;
+
+        bus_addr  = PAGE_ALIGN(bus_addr);
+        phys_addr = PAGE_ALIGN(bus_addr);
+
+        /* only support 512GB address spaces for now */
+        if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK))
+                return -EINVAL;
+
+        pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)];
+
+        if (!IOMMU_PTE_PRESENT(*pte)) {
+                page = (u64 *)get_zeroed_page(GFP_KERNEL);
+                if (!page)
+                        return -ENOMEM;
+                *pte = IOMMU_L2_PDE(virt_to_phys(page));
+        }
+
+        pte = IOMMU_PTE_PAGE(*pte);
+        pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
+
+        if (!IOMMU_PTE_PRESENT(*pte)) {
+                page = (u64 *)get_zeroed_page(GFP_KERNEL);
+                if (!page)
+                        return -ENOMEM;
+                *pte = IOMMU_L1_PDE(virt_to_phys(page));
+        }
+
+        pte = IOMMU_PTE_PAGE(*pte);
+        pte = &pte[IOMMU_PTE_L0_INDEX(bus_addr)];
+
+        if (IOMMU_PTE_PRESENT(*pte))
+                return -EBUSY;
+
+        __pte = phys_addr | IOMMU_PTE_P;
+        if (prot & IOMMU_PROT_IR)
+                __pte |= IOMMU_PTE_IR;
+        if (prot & IOMMU_PROT_IW)
+                __pte |= IOMMU_PTE_IW;
+
+        *pte = __pte;
+
+        return 0;
+}
+
+static int iommu_for_unity_map(struct amd_iommu *iommu,
+                               struct unity_map_entry *entry)
+{
+        u16 bdf, i;
+
+        for (i = entry->devid_start; i <= entry->devid_end; ++i) {
+                bdf = amd_iommu_alias_table[i];
+                if (amd_iommu_rlookup_table[bdf] == iommu)
+                        return 1;
+        }
+
+        return 0;
+}
+
+static int iommu_init_unity_mappings(struct amd_iommu *iommu)
+{
+        struct unity_map_entry *entry;
+        int ret;
+
+        list_for_each_entry(entry, &amd_iommu_unity_map, list) {
+                if (!iommu_for_unity_map(iommu, entry))
+                        continue;
+                ret = dma_ops_unity_map(iommu->default_dom, entry);
+                if (ret)
+                        return ret;
+        }
+
+        return 0;
+}
+
+static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
+                             struct unity_map_entry *e)
+{
+        u64 addr;
+        int ret;
+
+        for (addr = e->address_start; addr < e->address_end;
+             addr += PAGE_SIZE) {
+                ret = iommu_map(&dma_dom->domain, addr, addr, e->prot);
+                if (ret)
+                        return ret;
+                /*
+                 * if unity mapping is in aperture range mark the page
+                 * as allocated in the aperture
+                 */
+                if (addr < dma_dom->aperture_size)
+                        __set_bit(addr >> PAGE_SHIFT, dma_dom->bitmap);
+        }
+
+        return 0;
+}
+
+static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
+                                          u16 devid)
+{
+        struct unity_map_entry *e;
+        int ret;
+
+        list_for_each_entry(e, &amd_iommu_unity_map, list) {
+                if (!(devid >= e->devid_start && devid <= e->devid_end))
+                        continue;
+                ret = dma_ops_unity_map(dma_dom, e);
+                if (ret)
+                        return ret;
+        }
+
+        return 0;
+}
+
+static unsigned long dma_mask_to_pages(unsigned long mask)
+{
+        return (mask >> PAGE_SHIFT) +
+                (PAGE_ALIGN(mask & ~PAGE_MASK) >> PAGE_SHIFT);
+}
+
+static unsigned long dma_ops_alloc_addresses(struct device *dev,
+                                             struct dma_ops_domain *dom,
+                                             unsigned int pages)
+{
+        unsigned long limit = dma_mask_to_pages(*dev->dma_mask);
+        unsigned long address;
+        unsigned long size = dom->aperture_size >> PAGE_SHIFT;
+        unsigned long boundary_size;
+
+        boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
+                        PAGE_SIZE) >> PAGE_SHIFT;
+        limit = limit < size ? limit : size;
+
+        if (dom->next_bit >= limit)
+                dom->next_bit = 0;
+
+        address = iommu_area_alloc(dom->bitmap, limit, dom->next_bit, pages,
+                        0 , boundary_size, 0);
+        if (address == -1)
+                address = iommu_area_alloc(dom->bitmap, limit, 0, pages,
+                                0, boundary_size, 0);
+
+        if (likely(address != -1)) {
+                dom->next_bit = address + pages;
+                address <<= PAGE_SHIFT;
+        } else
+                address = bad_dma_address;
+
+        WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
+
+        return address;
+}
+
+static void dma_ops_free_addresses(struct dma_ops_domain *dom,
+                                   unsigned long address,
+                                   unsigned int pages)
+{
+        address >>= PAGE_SHIFT;
+        iommu_area_free(dom->bitmap, address, pages);
+}
+
+static u16 domain_id_alloc(void)
+{
+        unsigned long flags;
+        int id;
+
+        write_lock_irqsave(&amd_iommu_devtable_lock, flags);
+        id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
+        BUG_ON(id == 0);
+        if (id > 0 && id < MAX_DOMAIN_ID)
+                __set_bit(id, amd_iommu_pd_alloc_bitmap);
+        else
+                id = 0;
+        write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
+
+        return id;
+}
+
+static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
+                                      unsigned long start_page,
+                                      unsigned int pages)
+{
+        unsigned int last_page = dom->aperture_size >> PAGE_SHIFT;
+
+        if (start_page + pages > last_page)
+                pages = last_page - start_page;
+
+        set_bit_string(dom->bitmap, start_page, pages);
+}
+
+static void dma_ops_free_pagetable(struct dma_ops_domain *dma_dom)
+{
+        int i, j;
+        u64 *p1, *p2, *p3;
+
+        p1 = dma_dom->domain.pt_root;
+
+        if (!p1)
+                return;
+
+        for (i = 0; i < 512; ++i) {
+                if (!IOMMU_PTE_PRESENT(p1[i]))
+                        continue;
+
+                p2 = IOMMU_PTE_PAGE(p1[i]);
+                for (j = 0; j < 512; ++i) {
+                        if (!IOMMU_PTE_PRESENT(p2[j]))
+                                continue;
+                        p3 = IOMMU_PTE_PAGE(p2[j]);
+                        free_page((unsigned long)p3);
+                }
+
+                free_page((unsigned long)p2);
+        }
+
+        free_page((unsigned long)p1);
+}
+
+static void dma_ops_domain_free(struct dma_ops_domain *dom)
+{
+        if (!dom)
+                return;
+
+        dma_ops_free_pagetable(dom);
+
+        kfree(dom->pte_pages);
+
+        kfree(dom->bitmap);
+
+        kfree(dom);
+}
+
+static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu,
+                                                   unsigned order)
+{
+        struct dma_ops_domain *dma_dom;
+        unsigned i, num_pte_pages;
+        u64 *l2_pde;
+        u64 address;
+
+        /*
+         * Currently the DMA aperture must be between 32 MB and 1GB in size
+         */
+        if ((order < 25) || (order > 30))
+                return NULL;
+
+        dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
+        if (!dma_dom)
+                return NULL;
+
+        spin_lock_init(&dma_dom->domain.lock);
+
+        dma_dom->domain.id = domain_id_alloc();
+        if (dma_dom->domain.id == 0)
+                goto free_dma_dom;
+        dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
+        dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
+        dma_dom->domain.priv = dma_dom;
+        if (!dma_dom->domain.pt_root)
+                goto free_dma_dom;
+        dma_dom->aperture_size = (1ULL << order);
+        dma_dom->bitmap = kzalloc(dma_dom->aperture_size / (PAGE_SIZE * 8),
+                                  GFP_KERNEL);
+        if (!dma_dom->bitmap)
+                goto free_dma_dom;
+        /*
+         * mark the first page as allocated so we never return 0 as
+         * a valid dma-address. So we can use 0 as error value
+         */
+        dma_dom->bitmap[0] = 1;
+        dma_dom->next_bit = 0;
+
+        if (iommu->exclusion_start &&
+            iommu->exclusion_start < dma_dom->aperture_size) {
+                unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT;
+                int pages = to_pages(iommu->exclusion_start,
+                                iommu->exclusion_length);
+                dma_ops_reserve_addresses(dma_dom, startpage, pages);
+        }
+
+        num_pte_pages = dma_dom->aperture_size / (PAGE_SIZE * 512);
+        dma_dom->pte_pages = kzalloc(num_pte_pages * sizeof(void *),
+                        GFP_KERNEL);
+        if (!dma_dom->pte_pages)
+                goto free_dma_dom;
+
+        l2_pde = (u64 *)get_zeroed_page(GFP_KERNEL);
+        if (l2_pde == NULL)
+                goto free_dma_dom;
+
+        dma_dom->domain.pt_root[0] = IOMMU_L2_PDE(virt_to_phys(l2_pde));
+
+        for (i = 0; i < num_pte_pages; ++i) {
+                dma_dom->pte_pages[i] = (u64 *)get_zeroed_page(GFP_KERNEL);
+                if (!dma_dom->pte_pages[i])
+                        goto free_dma_dom;
+                address = virt_to_phys(dma_dom->pte_pages[i]);
+                l2_pde[i] = IOMMU_L1_PDE(address);
+        }
+
+        return dma_dom;
+
+free_dma_dom:
+        dma_ops_domain_free(dma_dom);
+
+        return NULL;
+}
+
+static struct protection_domain *domain_for_device(u16 devid)
+{
+        struct protection_domain *dom;
+        unsigned long flags;
+
+        read_lock_irqsave(&amd_iommu_devtable_lock, flags);
+        dom = amd_iommu_pd_table[devid];
+        read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
+
+        return dom;
+}
+
+static void set_device_domain(struct amd_iommu *iommu,
+                              struct protection_domain *domain,
+                              u16 devid)
+{
+        unsigned long flags;
+
+        u64 pte_root = virt_to_phys(domain->pt_root);
+
+        pte_root |= (domain->mode & 0x07) << 9;
+        pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | 2;
+
+        write_lock_irqsave(&amd_iommu_devtable_lock, flags);
+        amd_iommu_dev_table[devid].data[0] = pte_root;
+        amd_iommu_dev_table[devid].data[1] = pte_root >> 32;
+        amd_iommu_dev_table[devid].data[2] = domain->id;
+
+        amd_iommu_pd_table[devid] = domain;
+        write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
+
+        iommu_queue_inv_dev_entry(iommu, devid);
+
+        iommu->need_sync = 1;
+}
+
+static int get_device_resources(struct device *dev,
+                                struct amd_iommu **iommu,
+                                struct protection_domain **domain,
+                                u16 *bdf)
+{
+        struct dma_ops_domain *dma_dom;
+        struct pci_dev *pcidev;
+        u16 _bdf;
+
+        BUG_ON(!dev || dev->bus != &pci_bus_type || !dev->dma_mask);
+
+        pcidev = to_pci_dev(dev);
+        _bdf = (pcidev->bus->number << 8) | pcidev->devfn;
+
+        if (_bdf >= amd_iommu_last_bdf) {
+                *iommu = NULL;
+                *domain = NULL;
+                *bdf = 0xffff;
+                return 0;
+        }
+
+        *bdf = amd_iommu_alias_table[_bdf];
+
+        *iommu = amd_iommu_rlookup_table[*bdf];
+        if (*iommu == NULL)
+                return 0;
+        dma_dom = (*iommu)->default_dom;
+        *domain = domain_for_device(*bdf);
+        if (*domain == NULL) {
+                *domain = &dma_dom->domain;
+                set_device_domain(*iommu, *domain, *bdf);
+                printk(KERN_INFO "AMD IOMMU: Using protection domain %d for "
+                                "device ", (*domain)->id);
+                print_devid(_bdf, 1);
+        }
+
+        return 1;
+}
+
+static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu,
+                                     struct dma_ops_domain *dom,
+                                     unsigned long address,
+                                     phys_addr_t paddr,
+                                     int direction)
+{
+        u64 *pte, __pte;
+
+        WARN_ON(address > dom->aperture_size);
+
+        paddr &= PAGE_MASK;
+
+        pte  = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)];
+        pte += IOMMU_PTE_L0_INDEX(address);
+
+        __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
+
+        if (direction == DMA_TO_DEVICE)
+                __pte |= IOMMU_PTE_IR;
+        else if (direction == DMA_FROM_DEVICE)
+                __pte |= IOMMU_PTE_IW;
+        else if (direction == DMA_BIDIRECTIONAL)
+                __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
+
+        WARN_ON(*pte);
+
+        *pte = __pte;
+
+        return (dma_addr_t)address;
+}
+
+static void dma_ops_domain_unmap(struct amd_iommu *iommu,
+                                 struct dma_ops_domain *dom,
+                                 unsigned long address)
+{
+        u64 *pte;
+
+        if (address >= dom->aperture_size)
+                return;
+
+        WARN_ON(address & 0xfffULL || address > dom->aperture_size);
+
+        pte  = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)];
+        pte += IOMMU_PTE_L0_INDEX(address);
+
+        WARN_ON(!*pte);
+
+        *pte = 0ULL;
+}
+
+static dma_addr_t __map_single(struct device *dev,
+                               struct amd_iommu *iommu,
+                               struct dma_ops_domain *dma_dom,
+                               phys_addr_t paddr,
+                               size_t size,
+                               int dir)
+{
+        dma_addr_t offset = paddr & ~PAGE_MASK;
+        dma_addr_t address, start;
+        unsigned int pages;
+        int i;
+
+        pages = to_pages(paddr, size);
+        paddr &= PAGE_MASK;
+
+        address = dma_ops_alloc_addresses(dev, dma_dom, pages);
+        if (unlikely(address == bad_dma_address))
+                goto out;
+
+        start = address;
+        for (i = 0; i < pages; ++i) {
+                dma_ops_domain_map(iommu, dma_dom, start, paddr, dir);
+                paddr += PAGE_SIZE;
+                start += PAGE_SIZE;
+        }
+        address += offset;
+
+out:
+        return address;
+}
+
+static void __unmap_single(struct amd_iommu *iommu,
+                           struct dma_ops_domain *dma_dom,
+                           dma_addr_t dma_addr,
+                           size_t size,
+                           int dir)
+{
+        dma_addr_t i, start;
+        unsigned int pages;
+
+        if ((dma_addr == 0) || (dma_addr + size > dma_dom->aperture_size))
+                return;
+
+        pages = to_pages(dma_addr, size);
+        dma_addr &= PAGE_MASK;
+        start = dma_addr;
+
+        for (i = 0; i < pages; ++i) {
+                dma_ops_domain_unmap(iommu, dma_dom, start);
+                start += PAGE_SIZE;
+        }
+
+        dma_ops_free_addresses(dma_dom, dma_addr, pages);
+}
+
+static dma_addr_t map_single(struct device *dev, phys_addr_t paddr,
+                             size_t size, int dir)
+{
+        unsigned long flags;
+        struct amd_iommu *iommu;
+        struct protection_domain *domain;
+        u16 devid;
+        dma_addr_t addr;
+
+        get_device_resources(dev, &iommu, &domain, &devid);
+
+        if (iommu == NULL || domain == NULL)
+                return (dma_addr_t)paddr;
+
+        spin_lock_irqsave(&domain->lock, flags);
+        addr = __map_single(dev, iommu, domain->priv, paddr, size, dir);
+        if (addr == bad_dma_address)
+                goto out;
+
+        if (iommu_has_npcache(iommu))
+                iommu_flush_pages(iommu, domain->id, addr, size);
+
+        if (iommu->need_sync)
+                iommu_completion_wait(iommu);
+
+out:
+        spin_unlock_irqrestore(&domain->lock, flags);
+
+        return addr;
+}
+
+static void unmap_single(struct device *dev, dma_addr_t dma_addr,
+                         size_t size, int dir)
+{
+        unsigned long flags;
+        struct amd_iommu *iommu;
+        struct protection_domain *domain;
+        u16 devid;
+
+        if (!get_device_resources(dev, &iommu, &domain, &devid))
+                return;
+
+        spin_lock_irqsave(&domain->lock, flags);
+
+        __unmap_single(iommu, domain->priv, dma_addr, size, dir);
+
+        iommu_flush_pages(iommu, domain->id, dma_addr, size);
+
+        if (iommu->need_sync)
+                iommu_completion_wait(iommu);
+
+        spin_unlock_irqrestore(&domain->lock, flags);
+}
+
+static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
+                           int nelems, int dir)
+{
+        struct scatterlist *s;
+        int i;
+
+        for_each_sg(sglist, s, nelems, i) {
+                s->dma_address = (dma_addr_t)sg_phys(s);
+                s->dma_length  = s->length;
+        }
+
+        return nelems;
+}
+
+static int map_sg(struct device *dev, struct scatterlist *sglist,
+                  int nelems, int dir)
+{
+        unsigned long flags;
+        struct amd_iommu *iommu;
+        struct protection_domain *domain;
+        u16 devid;
+        int i;
+        struct scatterlist *s;
+        phys_addr_t paddr;
+        int mapped_elems = 0;
+
+        get_device_resources(dev, &iommu, &domain, &devid);
+
+        if (!iommu || !domain)
+                return map_sg_no_iommu(dev, sglist, nelems, dir);
+
+        spin_lock_irqsave(&domain->lock, flags);
+
+        for_each_sg(sglist, s, nelems, i) {
+                paddr = sg_phys(s);
+
+                s->dma_address = __map_single(dev, iommu, domain->priv,
+                                              paddr, s->length, dir);
+
+                if (s->dma_address) {
+                        s->dma_length = s->length;
+                        mapped_elems++;
+                } else
+                        goto unmap;
+                if (iommu_has_npcache(iommu))
+                        iommu_flush_pages(iommu, domain->id, s->dma_address,
+                                          s->dma_length);
+        }
+
+        if (iommu->need_sync)
+                iommu_completion_wait(iommu);
+
+out:
+        spin_unlock_irqrestore(&domain->lock, flags);
+
+        return mapped_elems;
+unmap:
+        for_each_sg(sglist, s, mapped_elems, i) {
+                if (s->dma_address)
+                        __unmap_single(iommu, domain->priv, s->dma_address,
+                                       s->dma_length, dir);
+                s->dma_address = s->dma_length = 0;
+        }
+
+        mapped_elems = 0;
+
+        goto out;
+}
+
+static void unmap_sg(struct device *dev, struct scatterlist *sglist,
+                     int nelems, int dir)
+{
+        unsigned long flags;
+        struct amd_iommu *iommu;
+        struct protection_domain *domain;
+        struct scatterlist *s;
+        u16 devid;
+        int i;
+
+        if (!get_device_resources(dev, &iommu, &domain, &devid))
+                return;
+
+        spin_lock_irqsave(&domain->lock, flags);
+
+        for_each_sg(sglist, s, nelems, i) {
+                __unmap_single(iommu, domain->priv, s->dma_address,
+                               s->dma_length, dir);
+                iommu_flush_pages(iommu, domain->id, s->dma_address,
+                                  s->dma_length);
+                s->dma_address = s->dma_length = 0;
+        }
+
+        if (iommu->need_sync)
+                iommu_completion_wait(iommu);
+
+        spin_unlock_irqrestore(&domain->lock, flags);
+}
+
+static void *alloc_coherent(struct device *dev, size_t size,
+                            dma_addr_t *dma_addr, gfp_t flag)
+{
+        unsigned long flags;
+        void *virt_addr;
+        struct amd_iommu *iommu;
+        struct protection_domain *domain;
+        u16 devid;
+        phys_addr_t paddr;
+
+        virt_addr = (void *)__get_free_pages(flag, get_order(size));
+        if (!virt_addr)
+                return 0;
+
+        memset(virt_addr, 0, size);
+        paddr = virt_to_phys(virt_addr);
+
+        get_device_resources(dev, &iommu, &domain, &devid);
+
+        if (!iommu || !domain) {
+                *dma_addr = (dma_addr_t)paddr;
+                return virt_addr;
+        }
+
+        spin_lock_irqsave(&domain->lock, flags);
+
+        *dma_addr = __map_single(dev, iommu, domain->priv, paddr,
+                                 size, DMA_BIDIRECTIONAL);
+
+        if (*dma_addr == bad_dma_address) {
+                free_pages((unsigned long)virt_addr, get_order(size));
+                virt_addr = NULL;
+                goto out;
+        }
+
+        if (iommu_has_npcache(iommu))
+                iommu_flush_pages(iommu, domain->id, *dma_addr, size);
+
+        if (iommu->need_sync)
+                iommu_completion_wait(iommu);
+
+out:
+        spin_unlock_irqrestore(&domain->lock, flags);
+
+        return virt_addr;
+}
+
+static void free_coherent(struct device *dev, size_t size,
+                          void *virt_addr, dma_addr_t dma_addr)
+{
+        unsigned long flags;
+        struct amd_iommu *iommu;
+        struct protection_domain *domain;
+        u16 devid;
+
+        get_device_resources(dev, &iommu, &domain, &devid);
+
+        if (!iommu || !domain)
+                goto free_mem;
+
+        spin_lock_irqsave(&domain->lock, flags);
+
+        __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
+        iommu_flush_pages(iommu, domain->id, dma_addr, size);
+
+        if (iommu->need_sync)
+                iommu_completion_wait(iommu);
+
+        spin_unlock_irqrestore(&domain->lock, flags);
+
+free_mem:
+        free_pages((unsigned long)virt_addr, get_order(size));
+}
+
+/*
+ * If the driver core informs the DMA layer if a driver grabs a device
+ * we don't need to preallocate the protection domains anymore.
+ * For now we have to.
+ */
+void prealloc_protection_domains(void)
+{
+        struct pci_dev *dev = NULL;
+        struct dma_ops_domain *dma_dom;
+        struct amd_iommu *iommu;
+        int order = amd_iommu_aperture_order;
+        u16 devid;
+
+        while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
+                devid = (dev->bus->number << 8) | dev->devfn;
+                if (devid >= amd_iommu_last_bdf)
+                        continue;
+                devid = amd_iommu_alias_table[devid];
+                if (domain_for_device(devid))
+                        continue;
+                iommu = amd_iommu_rlookup_table[devid];
+                if (!iommu)
+                        continue;
+                dma_dom = dma_ops_domain_alloc(iommu, order);
+                if (!dma_dom)
+                        continue;
+                init_unity_mappings_for_device(dma_dom, devid);
+                set_device_domain(iommu, &dma_dom->domain, devid);
+                printk(KERN_INFO "AMD IOMMU: Allocated domain %d for device ",
+                       dma_dom->domain.id);
+                print_devid(devid, 1);
+        }
+}
+
+static struct dma_mapping_ops amd_iommu_dma_ops = {
+        .alloc_coherent = alloc_coherent,
+        .free_coherent = free_coherent,
+        .map_single = map_single,
+        .unmap_single = unmap_single,
+        .map_sg = map_sg,
+        .unmap_sg = unmap_sg,
+};
+
+int __init amd_iommu_init_dma_ops(void)
+{
+        struct amd_iommu *iommu;
+        int order = amd_iommu_aperture_order;
+        int ret;
+
+        list_for_each_entry(iommu, &amd_iommu_list, list) {
+                iommu->default_dom = dma_ops_domain_alloc(iommu, order);
+                if (iommu->default_dom == NULL)
+                        return -ENOMEM;
+                ret = iommu_init_unity_mappings(iommu);
+                if (ret)
+                        goto free_domains;
+        }
+
+        if (amd_iommu_isolate)
+                prealloc_protection_domains();
+
+        iommu_detected = 1;
+        force_iommu = 1;
+        bad_dma_address = 0;
+#ifdef CONFIG_GART_IOMMU
+        gart_iommu_aperture_disabled = 1;
+        gart_iommu_aperture = 0;
+#endif
+
+        dma_ops = &amd_iommu_dma_ops;
+
+        return 0;
+
+free_domains:
+
+        list_for_each_entry(iommu, &amd_iommu_list, list) {
+                if (iommu->default_dom)
+                        dma_ops_domain_free(iommu->default_dom);
+        }
+
+        return ret;
+}
diff --git a/arch/x86/kernel/amd_iommu_init.c b/arch/x86/kernel/amd_iommu_init.c
new file mode 100644
index 000000000000..2a13e430437d
--- /dev/null
+++ b/arch/x86/kernel/amd_iommu_init.c
@@ -0,0 +1,875 @@
+/*
+ * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
+ * Author: Joerg Roedel <joerg.roedel@amd.com>
+ *         Leo Duran <leo.duran@amd.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+
+#include <linux/pci.h>
+#include <linux/acpi.h>
+#include <linux/gfp.h>
+#include <linux/list.h>
+#include <linux/sysdev.h>
+#include <asm/pci-direct.h>
+#include <asm/amd_iommu_types.h>
+#include <asm/amd_iommu.h>
+#include <asm/gart.h>
+
+/*
+ * definitions for the ACPI scanning code
+ */
+#define UPDATE_LAST_BDF(x) do {\
+        if ((x) > amd_iommu_last_bdf) \
+                amd_iommu_last_bdf = (x); \
+        } while (0);
+
+#define DEVID(bus, devfn) (((bus) << 8) | (devfn))
+#define PCI_BUS(x) (((x) >> 8) & 0xff)
+#define IVRS_HEADER_LENGTH 48
+#define TBL_SIZE(x) (1 << (PAGE_SHIFT + get_order(amd_iommu_last_bdf * (x))))
+
+#define ACPI_IVHD_TYPE                  0x10
+#define ACPI_IVMD_TYPE_ALL              0x20
+#define ACPI_IVMD_TYPE                  0x21
+#define ACPI_IVMD_TYPE_RANGE            0x22
+
+#define IVHD_DEV_ALL                    0x01
+#define IVHD_DEV_SELECT                 0x02
+#define IVHD_DEV_SELECT_RANGE_START     0x03
+#define IVHD_DEV_RANGE_END              0x04
+#define IVHD_DEV_ALIAS                  0x42
+#define IVHD_DEV_ALIAS_RANGE            0x43
+#define IVHD_DEV_EXT_SELECT             0x46
+#define IVHD_DEV_EXT_SELECT_RANGE       0x47
+
+#define IVHD_FLAG_HT_TUN_EN             0x00
+#define IVHD_FLAG_PASSPW_EN             0x01
+#define IVHD_FLAG_RESPASSPW_EN          0x02
+#define IVHD_FLAG_ISOC_EN               0x03
+
+#define IVMD_FLAG_EXCL_RANGE            0x08
+#define IVMD_FLAG_UNITY_MAP             0x01
+
+#define ACPI_DEVFLAG_INITPASS           0x01
+#define ACPI_DEVFLAG_EXTINT             0x02
+#define ACPI_DEVFLAG_NMI                0x04
+#define ACPI_DEVFLAG_SYSMGT1            0x10
+#define ACPI_DEVFLAG_SYSMGT2            0x20
+#define ACPI_DEVFLAG_LINT0              0x40
+#define ACPI_DEVFLAG_LINT1              0x80
+#define ACPI_DEVFLAG_ATSDIS             0x10000000
+
+struct ivhd_header {
+        u8 type;
+        u8 flags;
+        u16 length;
+        u16 devid;
+        u16 cap_ptr;
+        u64 mmio_phys;
+        u16 pci_seg;
+        u16 info;
+        u32 reserved;
+} __attribute__((packed));
+
+struct ivhd_entry {
+        u8 type;
+        u16 devid;
+        u8 flags;
+        u32 ext;
+} __attribute__((packed));
+
+struct ivmd_header {
+        u8 type;
+        u8 flags;
+        u16 length;
+        u16 devid;
+        u16 aux;
+        u64 resv;
+        u64 range_start;
+        u64 range_length;
+} __attribute__((packed));
+
+static int __initdata amd_iommu_detected;
+
+u16 amd_iommu_last_bdf;
+struct list_head amd_iommu_unity_map;
+unsigned amd_iommu_aperture_order = 26;
+int amd_iommu_isolate;
+
+struct list_head amd_iommu_list;
+struct dev_table_entry *amd_iommu_dev_table;
+u16 *amd_iommu_alias_table;
+struct amd_iommu **amd_iommu_rlookup_table;
+struct protection_domain **amd_iommu_pd_table;
+unsigned long *amd_iommu_pd_alloc_bitmap;
+
+static u32 dev_table_size;
+static u32 alias_table_size;
+static u32 rlookup_table_size;
+
+static void __init iommu_set_exclusion_range(struct amd_iommu *iommu)
+{
+        u64 start = iommu->exclusion_start & PAGE_MASK;
+        u64 limit = (start + iommu->exclusion_length) & PAGE_MASK;
+        u64 entry;
+
+        if (!iommu->exclusion_start)
+                return;
+
+        entry = start | MMIO_EXCL_ENABLE_MASK;
+        memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
+                        &entry, sizeof(entry));
+
+        entry = limit;
+        memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
+                        &entry, sizeof(entry));
+}
+
+static void __init iommu_set_device_table(struct amd_iommu *iommu)
+{
+        u32 entry;
+
+        BUG_ON(iommu->mmio_base == NULL);
+
+        entry = virt_to_phys(amd_iommu_dev_table);
+        entry |= (dev_table_size >> 12) - 1;
+        memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
+                        &entry, sizeof(entry));
+}
+
+static void __init iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
+{
+        u32 ctrl;
+
+        ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
+        ctrl |= (1 << bit);
+        writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
+}
+
+static void __init iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
+{
+        u32 ctrl;
+
+        ctrl = (u64)readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
+        ctrl &= ~(1 << bit);
+        writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
+}
+
+void __init iommu_enable(struct amd_iommu *iommu)
+{
+        printk(KERN_INFO "AMD IOMMU: Enabling IOMMU at ");
+        print_devid(iommu->devid, 0);
+        printk(" cap 0x%hx\n", iommu->cap_ptr);
+
+        iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
+}
+
+static u8 * __init iommu_map_mmio_space(u64 address)
+{
+        u8 *ret;
+
+        if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu"))
+                return NULL;
+
+        ret = ioremap_nocache(address, MMIO_REGION_LENGTH);
+        if (ret != NULL)
+                return ret;
+
+        release_mem_region(address, MMIO_REGION_LENGTH);
+
+        return NULL;
+}
+
+static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
+{
+        if (iommu->mmio_base)
+                iounmap(iommu->mmio_base);
+        release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH);
+}
+
+static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr)
+{
+        u32 cap;
+
+        cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET);
+        UPDATE_LAST_BDF(DEVID(MMIO_GET_BUS(cap), MMIO_GET_LD(cap)));
+
+        return 0;
+}
+
+static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
+{
+        u8 *p = (void *)h, *end = (void *)h;
+        struct ivhd_entry *dev;
+
+        p += sizeof(*h);
+        end += h->length;
+
+        find_last_devid_on_pci(PCI_BUS(h->devid),
+                        PCI_SLOT(h->devid),
+                        PCI_FUNC(h->devid),
+                        h->cap_ptr);
+
+        while (p < end) {
+                dev = (struct ivhd_entry *)p;
+                switch (dev->type) {
+                case IVHD_DEV_SELECT:
+                case IVHD_DEV_RANGE_END:
+                case IVHD_DEV_ALIAS:
+                case IVHD_DEV_EXT_SELECT:
+                        UPDATE_LAST_BDF(dev->devid);
+                        break;
+                default:
+                        break;
+                }
+                p += 0x04 << (*p >> 6);
+        }
+
+        WARN_ON(p != end);
+
+        return 0;
+}
+
+static int __init find_last_devid_acpi(struct acpi_table_header *table)
+{
+        int i;
+        u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table;
+        struct ivhd_header *h;
+
+        /*
+         * Validate checksum here so we don't need to do it when
+         * we actually parse the table
+         */
+        for (i = 0; i < table->length; ++i)
+                checksum += p[i];
+        if (checksum != 0)
+                /* ACPI table corrupt */
+                return -ENODEV;
+
+        p += IVRS_HEADER_LENGTH;
+
+        end += table->length;
+        while (p < end) {
+                h = (struct ivhd_header *)p;
+                switch (h->type) {
+                case ACPI_IVHD_TYPE:
+                        find_last_devid_from_ivhd(h);
+                        break;
+                default:
+                        break;
+                }
+                p += h->length;
+        }
+        WARN_ON(p != end);
+
+        return 0;
+}
+
+static u8 * __init alloc_command_buffer(struct amd_iommu *iommu)
+{
+        u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL,
+                        get_order(CMD_BUFFER_SIZE));
+        u64 entry = 0;
+
+        if (cmd_buf == NULL)
+                return NULL;
+
+        iommu->cmd_buf_size = CMD_BUFFER_SIZE;
+
+        memset(cmd_buf, 0, CMD_BUFFER_SIZE);
+
+        entry = (u64)virt_to_phys(cmd_buf);
+        entry |= MMIO_CMD_SIZE_512;
+        memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
+                        &entry, sizeof(entry));
+
+        iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
+
+        return cmd_buf;
+}
+
+static void __init free_command_buffer(struct amd_iommu *iommu)
+{
+        if (iommu->cmd_buf)
+                free_pages((unsigned long)iommu->cmd_buf,
+                                get_order(CMD_BUFFER_SIZE));
+}
+
+static void set_dev_entry_bit(u16 devid, u8 bit)
+{
+        int i = (bit >> 5) & 0x07;
+        int _bit = bit & 0x1f;
+
+        amd_iommu_dev_table[devid].data[i] |= (1 << _bit);
+}
+
+static void __init set_dev_entry_from_acpi(u16 devid, u32 flags, u32 ext_flags)
+{
+        if (flags & ACPI_DEVFLAG_INITPASS)
+                set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
+        if (flags & ACPI_DEVFLAG_EXTINT)
+                set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
+        if (flags & ACPI_DEVFLAG_NMI)
+                set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
+        if (flags & ACPI_DEVFLAG_SYSMGT1)
+                set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
+        if (flags & ACPI_DEVFLAG_SYSMGT2)
+                set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
+        if (flags & ACPI_DEVFLAG_LINT0)
+                set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
+        if (flags & ACPI_DEVFLAG_LINT1)
+                set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
+}
+
+static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
+{
+        amd_iommu_rlookup_table[devid] = iommu;
+}
+
+static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
+{
+        struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
+
+        if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
+                return;
+
+        if (iommu) {
+                set_dev_entry_bit(m->devid, DEV_ENTRY_EX);
+                iommu->exclusion_start = m->range_start;
+                iommu->exclusion_length = m->range_length;
+        }
+}
+
+static void __init init_iommu_from_pci(struct amd_iommu *iommu)
+{
+        int bus = PCI_BUS(iommu->devid);
+        int dev = PCI_SLOT(iommu->devid);
+        int fn  = PCI_FUNC(iommu->devid);
+        int cap_ptr = iommu->cap_ptr;
+        u32 range;
+
+        iommu->cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_CAP_HDR_OFFSET);
+
+        range = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET);
+        iommu->first_device = DEVID(MMIO_GET_BUS(range), MMIO_GET_FD(range));
+        iommu->last_device = DEVID(MMIO_GET_BUS(range), MMIO_GET_LD(range));
+}
+
+static void __init init_iommu_from_acpi(struct amd_iommu *iommu,
+                                        struct ivhd_header *h)
+{
+        u8 *p = (u8 *)h;
+        u8 *end = p, flags = 0;
+        u16 dev_i, devid = 0, devid_start = 0, devid_to = 0;
+        u32 ext_flags = 0;
+        bool alias = 0;
+        struct ivhd_entry *e;
+
+        /*
+         * First set the recommended feature enable bits from ACPI
+         * into the IOMMU control registers
+         */
+        h->flags & IVHD_FLAG_HT_TUN_EN ?
+                iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
+                iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
+
+        h->flags & IVHD_FLAG_PASSPW_EN ?
+                iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
+                iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
+
+        h->flags & IVHD_FLAG_RESPASSPW_EN ?
+                iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
+                iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
+
+        h->flags & IVHD_FLAG_ISOC_EN ?
+                iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
+                iommu_feature_disable(iommu, CONTROL_ISOC_EN);
+
+        /*
+         * make IOMMU memory accesses cache coherent
+         */
+        iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
+
+        /*
+         * Done. Now parse the device entries
+         */
+        p += sizeof(struct ivhd_header);
+        end += h->length;
+
+        while (p < end) {
+                e = (struct ivhd_entry *)p;
+                switch (e->type) {
+                case IVHD_DEV_ALL:
+                        for (dev_i = iommu->first_device;
+                                        dev_i <= iommu->last_device; ++dev_i)
+                                set_dev_entry_from_acpi(dev_i, e->flags, 0);
+                        break;
+                case IVHD_DEV_SELECT:
+                        devid = e->devid;
+                        set_dev_entry_from_acpi(devid, e->flags, 0);
+                        break;
+                case IVHD_DEV_SELECT_RANGE_START:
+                        devid_start = e->devid;
+                        flags = e->flags;
+                        ext_flags = 0;
+                        alias = 0;
+                        break;
+                case IVHD_DEV_ALIAS:
+                        devid = e->devid;
+                        devid_to = e->ext >> 8;
+                        set_dev_entry_from_acpi(devid, e->flags, 0);
+                        amd_iommu_alias_table[devid] = devid_to;
+                        break;
+                case IVHD_DEV_ALIAS_RANGE:
+                        devid_start = e->devid;
+                        flags = e->flags;
+                        devid_to = e->ext >> 8;
+                        ext_flags = 0;
+                        alias = 1;
+                        break;
+                case IVHD_DEV_EXT_SELECT:
+                        devid = e->devid;
+                        set_dev_entry_from_acpi(devid, e->flags, e->ext);
+                        break;
+                case IVHD_DEV_EXT_SELECT_RANGE:
+                        devid_start = e->devid;
+                        flags = e->flags;
+                        ext_flags = e->ext;
+                        alias = 0;
+                        break;
+                case IVHD_DEV_RANGE_END:
+                        devid = e->devid;
+                        for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
+                                if (alias)
+                                        amd_iommu_alias_table[dev_i] = devid_to;
+                                set_dev_entry_from_acpi(
+                                                amd_iommu_alias_table[dev_i],
+                                                flags, ext_flags);
+                        }
+                        break;
+                default:
+                        break;
+                }
+
+                p += 0x04 << (e->type >> 6);
+        }
+}
+
+static int __init init_iommu_devices(struct amd_iommu *iommu)
+{
+        u16 i;
+
+        for (i = iommu->first_device; i <= iommu->last_device; ++i)
+                set_iommu_for_device(iommu, i);
+
+        return 0;
+}
+
+static void __init free_iommu_one(struct amd_iommu *iommu)
+{
+        free_command_buffer(iommu);
+        iommu_unmap_mmio_space(iommu);
+}
+
+static void __init free_iommu_all(void)
+{
+        struct amd_iommu *iommu, *next;
+
+        list_for_each_entry_safe(iommu, next, &amd_iommu_list, list) {
+                list_del(&iommu->list);
+                free_iommu_one(iommu);
+                kfree(iommu);
+        }
+}
+
+static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
+{
+        spin_lock_init(&iommu->lock);
+        list_add_tail(&iommu->list, &amd_iommu_list);
+
+        /*
+         * Copy data from ACPI table entry to the iommu struct
+         */
+        iommu->devid = h->devid;
+        iommu->cap_ptr = h->cap_ptr;
+        iommu->mmio_phys = h->mmio_phys;
+        iommu->mmio_base = iommu_map_mmio_space(h->mmio_phys);
+        if (!iommu->mmio_base)
+                return -ENOMEM;
+
+        iommu_set_device_table(iommu);
+        iommu->cmd_buf = alloc_command_buffer(iommu);
+        if (!iommu->cmd_buf)
+                return -ENOMEM;
+
+        init_iommu_from_pci(iommu);
+        init_iommu_from_acpi(iommu, h);
+        init_iommu_devices(iommu);
+
+        return 0;
+}
+
+static int __init init_iommu_all(struct acpi_table_header *table)
+{
+        u8 *p = (u8 *)table, *end = (u8 *)table;
+        struct ivhd_header *h;
+        struct amd_iommu *iommu;
+        int ret;
+
+        INIT_LIST_HEAD(&amd_iommu_list);
+
+        end += table->length;
+        p += IVRS_HEADER_LENGTH;
+
+        while (p < end) {
+                h = (struct ivhd_header *)p;
+                switch (*p) {
+                case ACPI_IVHD_TYPE:
+                        iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
+                        if (iommu == NULL)
+                                return -ENOMEM;
+                        ret = init_iommu_one(iommu, h);
+                        if (ret)
+                                return ret;
+                        break;
+                default:
+                        break;
+                }
+                p += h->length;
+
+        }
+        WARN_ON(p != end);
+
+        return 0;
+}
+
+static void __init free_unity_maps(void)
+{
+        struct unity_map_entry *entry, *next;
+
+        list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
+                list_del(&entry->list);
+                kfree(entry);
+        }
+}
+
+static int __init init_exclusion_range(struct ivmd_header *m)
+{
+        int i;
+
+        switch (m->type) {
+        case ACPI_IVMD_TYPE:
+                set_device_exclusion_range(m->devid, m);
+                break;
+        case ACPI_IVMD_TYPE_ALL:
+                for (i = 0; i < amd_iommu_last_bdf; ++i)
+                        set_device_exclusion_range(i, m);
+                break;
+        case ACPI_IVMD_TYPE_RANGE:
+                for (i = m->devid; i <= m->aux; ++i)
+                        set_device_exclusion_range(i, m);
+                break;
+        default:
+                break;
+        }
+
+        return 0;
+}
+
+static int __init init_unity_map_range(struct ivmd_header *m)
+{
+        struct unity_map_entry *e = 0;
+
+        e = kzalloc(sizeof(*e), GFP_KERNEL);
+        if (e == NULL)
+                return -ENOMEM;
+
+        switch (m->type) {
+        default:
+        case ACPI_IVMD_TYPE:
+                e->devid_start = e->devid_end = m->devid;
+                break;
+        case ACPI_IVMD_TYPE_ALL:
+                e->devid_start = 0;
+                e->devid_end = amd_iommu_last_bdf;
+                break;
+        case ACPI_IVMD_TYPE_RANGE:
+                e->devid_start = m->devid;
+                e->devid_end = m->aux;
+                break;
+        }
+        e->address_start = PAGE_ALIGN(m->range_start);
+        e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
+        e->prot = m->flags >> 1;
+
+        list_add_tail(&e->list, &amd_iommu_unity_map);
+
+        return 0;
+}
+
+static int __init init_memory_definitions(struct acpi_table_header *table)
+{
+        u8 *p = (u8 *)table, *end = (u8 *)table;
+        struct ivmd_header *m;
+
+        INIT_LIST_HEAD(&amd_iommu_unity_map);
+
+        end += table->length;
+        p += IVRS_HEADER_LENGTH;
+
+        while (p < end) {
+                m = (struct ivmd_header *)p;
+                if (m->flags & IVMD_FLAG_EXCL_RANGE)
+                        init_exclusion_range(m);
+                else if (m->flags & IVMD_FLAG_UNITY_MAP)
+                        init_unity_map_range(m);
+
+                p += m->length;
+        }
+
+        return 0;
+}
+
+static void __init enable_iommus(void)
+{
+        struct amd_iommu *iommu;
+
+        list_for_each_entry(iommu, &amd_iommu_list, list) {
+                iommu_set_exclusion_range(iommu);
+                iommu_enable(iommu);
+        }
+}
+
+/*
+ * Suspend/Resume support
+ * disable suspend until real resume implemented
+ */
+
+static int amd_iommu_resume(struct sys_device *dev)
+{
+        return 0;
+}
+
+static int amd_iommu_suspend(struct sys_device *dev, pm_message_t state)
+{
+        return -EINVAL;
+}
+
+static struct sysdev_class amd_iommu_sysdev_class = {
+        .name = "amd_iommu",
+        .suspend = amd_iommu_suspend,
+        .resume = amd_iommu_resume,
+};
+
+static struct sys_device device_amd_iommu = {
+        .id = 0,
+        .cls = &amd_iommu_sysdev_class,
+};
+
+int __init amd_iommu_init(void)
+{
+        int i, ret = 0;
+
+
+        if (no_iommu) {
+                printk(KERN_INFO "AMD IOMMU disabled by kernel command line\n");
+                return 0;
+        }
+
+        if (!amd_iommu_detected)
+                return -ENODEV;
+
+        /*
+         * First parse ACPI tables to find the largest Bus/Dev/Func
+         * we need to handle. Upon this information the shared data
+         * structures for the IOMMUs in the system will be allocated
+         */
+        if (acpi_table_parse("IVRS", find_last_devid_acpi) != 0)
+                return -ENODEV;
+
+        dev_table_size     = TBL_SIZE(DEV_TABLE_ENTRY_SIZE);
+        alias_table_size   = TBL_SIZE(ALIAS_TABLE_ENTRY_SIZE);
+        rlookup_table_size = TBL_SIZE(RLOOKUP_TABLE_ENTRY_SIZE);
+
+        ret = -ENOMEM;
+
+        /* Device table - directly used by all IOMMUs */
+        amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL,
+                                      get_order(dev_table_size));
+        if (amd_iommu_dev_table == NULL)
+                goto out;
+
+        /*
+         * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
+         * IOMMU see for that device
+         */
+        amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
+                        get_order(alias_table_size));
+        if (amd_iommu_alias_table == NULL)
+                goto free;
+
+        /* IOMMU rlookup table - find the IOMMU for a specific device */
+        amd_iommu_rlookup_table = (void *)__get_free_pages(GFP_KERNEL,
+                        get_order(rlookup_table_size));
+        if (amd_iommu_rlookup_table == NULL)
+                goto free;
+
+        /*
+         * Protection Domain table - maps devices to protection domains
+         * This table has the same size as the rlookup_table
+         */
+        amd_iommu_pd_table = (void *)__get_free_pages(GFP_KERNEL,
+                                     get_order(rlookup_table_size));
+        if (amd_iommu_pd_table == NULL)
+                goto free;
+
+        amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(GFP_KERNEL,
+                                            get_order(MAX_DOMAIN_ID/8));
+        if (amd_iommu_pd_alloc_bitmap == NULL)
+                goto free;
+
+        /*
+         * memory is allocated now; initialize the device table with all zeroes
+         * and let all alias entries point to itself
+         */
+        memset(amd_iommu_dev_table, 0, dev_table_size);
+        for (i = 0; i < amd_iommu_last_bdf; ++i)
+                amd_iommu_alias_table[i] = i;
+
+        memset(amd_iommu_pd_table, 0, rlookup_table_size);
+        memset(amd_iommu_pd_alloc_bitmap, 0, MAX_DOMAIN_ID / 8);
+
+        /*
+         * never allocate domain 0 because its used as the non-allocated and
+         * error value placeholder
+         */
+        amd_iommu_pd_alloc_bitmap[0] = 1;
+
+        /*
+         * now the data structures are allocated and basically initialized
+         * start the real acpi table scan
+         */
+        ret = -ENODEV;
+        if (acpi_table_parse("IVRS", init_iommu_all) != 0)
+                goto free;
+
+        if (acpi_table_parse("IVRS", init_memory_definitions) != 0)
+                goto free;
+
+        ret = amd_iommu_init_dma_ops();
+        if (ret)
+                goto free;
+
+        ret = sysdev_class_register(&amd_iommu_sysdev_class);
+        if (ret)
+                goto free;
+
+        ret = sysdev_register(&device_amd_iommu);
+        if (ret)
+                goto free;
+
+        enable_iommus();
+
+        printk(KERN_INFO "AMD IOMMU: aperture size is %d MB\n",
+                        (1 << (amd_iommu_aperture_order-20)));
+
+        printk(KERN_INFO "AMD IOMMU: device isolation ");
+        if (amd_iommu_isolate)
+                printk("enabled\n");
+        else
+                printk("disabled\n");
+
+out:
+        return ret;
+
+free:
+        if (amd_iommu_pd_alloc_bitmap)
+                free_pages((unsigned long)amd_iommu_pd_alloc_bitmap, 1);
+
+        if (amd_iommu_pd_table)
+                free_pages((unsigned long)amd_iommu_pd_table,
+                                get_order(rlookup_table_size));
+
+        if (amd_iommu_rlookup_table)
+                free_pages((unsigned long)amd_iommu_rlookup_table,
+                                get_order(rlookup_table_size));
+
+        if (amd_iommu_alias_table)
+                free_pages((unsigned long)amd_iommu_alias_table,
+                                get_order(alias_table_size));
+
+        if (amd_iommu_dev_table)
+                free_pages((unsigned long)amd_iommu_dev_table,
+                                get_order(dev_table_size));
+
+        free_iommu_all();
+
+        free_unity_maps();
+
+        goto out;
+}
+
+static int __init early_amd_iommu_detect(struct acpi_table_header *table)
+{
+        return 0;
+}
+
+void __init amd_iommu_detect(void)
+{
+        if (swiotlb || no_iommu || iommu_detected)
+                return;
+
+        if (acpi_table_parse("IVRS", early_amd_iommu_detect) == 0) {
+                iommu_detected = 1;
+                amd_iommu_detected = 1;
+#ifdef CONFIG_GART_IOMMU
+                gart_iommu_aperture_disabled = 1;
+                gart_iommu_aperture = 0;
+#endif
+        }
+}
+
+static int __init parse_amd_iommu_options(char *str)
+{
+        for (; *str; ++str) {
+                if (strcmp(str, "isolate") == 0)
+                        amd_iommu_isolate = 1;
+        }
+
+        return 1;
+}
+
+static int __init parse_amd_iommu_size_options(char *str)
+{
+        for (; *str; ++str) {
+                if (strcmp(str, "32M") == 0)
+                        amd_iommu_aperture_order = 25;
+                if (strcmp(str, "64M") == 0)
+                        amd_iommu_aperture_order = 26;
+                if (strcmp(str, "128M") == 0)
+                        amd_iommu_aperture_order = 27;
+                if (strcmp(str, "256M") == 0)
+                        amd_iommu_aperture_order = 28;
+                if (strcmp(str, "512M") == 0)
+                        amd_iommu_aperture_order = 29;
+                if (strcmp(str, "1G") == 0)
+                        amd_iommu_aperture_order = 30;
+        }
+
+        return 1;
+}
+
+__setup("amd_iommu=", parse_amd_iommu_options);
+__setup("amd_iommu_size=", parse_amd_iommu_size_options);
diff --git a/arch/x86/kernel/aperture_64.c b/arch/x86/kernel/aperture_64.c
index 479926d9e004..9f907806c1a5 100644
--- a/arch/x86/kernel/aperture_64.c
+++ b/arch/x86/kernel/aperture_64.c
@@ -35,6 +35,18 @@ int fallback_aper_force __initdata;
 
 int fix_aperture __initdata = 1;
 
+struct bus_dev_range {
+        int bus;
+        int dev_base;
+        int dev_limit;
+};
+
+static struct bus_dev_range bus_dev_ranges[] __initdata = {
+        { 0x00, 0x18, 0x20},
+        { 0xff, 0x00, 0x20},
+        { 0xfe, 0x00, 0x20}
+};
+
 static struct resource gart_resource = {
         .name   = "GART",
         .flags  = IORESOURCE_MEM,
@@ -55,8 +67,9 @@ static u32 __init allocate_aperture(void)
         u32 aper_size;
         void *p;
 
-        if (fallback_aper_order > 7)
-                fallback_aper_order = 7;
+        /* aper_size should <= 1G */
+        if (fallback_aper_order > 5)
+                fallback_aper_order = 5;
         aper_size = (32 * 1024 * 1024) << fallback_aper_order;
 
         /*
@@ -65,7 +78,20 @@ static u32 __init allocate_aperture(void)
          * memory. Unfortunately we cannot move it up because that would
          * make the IOMMU useless.
          */
-        p = __alloc_bootmem_nopanic(aper_size, aper_size, 0);
+        /*
+         * using 512M as goal, in case kexec will load kernel_big
+         * that will do the on position decompress, and  could overlap with
+         * that positon with gart that is used.
+         * sequende:
+         * kernel_small
+         * ==> kexec (with kdump trigger path or previous doesn't shutdown gart)
+         * ==> kernel_small(gart area become e820_reserved)
+         * ==> kexec (with kdump trigger path or previous doesn't shutdown gart)
+         * ==> kerne_big (uncompressed size will be big than 64M or 128M)
+         * so don't use 512M below as gart iommu, leave the space for kernel
+         * code for safe
+         */
+        p = __alloc_bootmem_nopanic(aper_size, aper_size, 512ULL<<20);
         if (!p || __pa(p)+aper_size > 0xffffffff) {
                 printk(KERN_ERR
                         "Cannot allocate aperture memory hole (%p,%uK)\n",
@@ -83,69 +109,53 @@ static u32 __init allocate_aperture(void)
         return (u32)__pa(p);
 }
 
-static int __init aperture_valid(u64 aper_base, u32 aper_size)
-{
-        if (!aper_base)
-                return 0;
-
-        if (aper_base + aper_size > 0x100000000UL) {
-                printk(KERN_ERR "Aperture beyond 4GB. Ignoring.\n");
-                return 0;
-        }
-        if (e820_any_mapped(aper_base, aper_base + aper_size, E820_RAM)) {
-                printk(KERN_ERR "Aperture pointing to e820 RAM. Ignoring.\n");
-                return 0;
-        }
-        if (aper_size < 64*1024*1024) {
-                printk(KERN_ERR "Aperture too small (%d MB)\n", aper_size>>20);
-                return 0;
-        }
-
-        return 1;
-}
 
 /* Find a PCI capability */
-static __u32 __init find_cap(int num, int slot, int func, int cap)
+static u32 __init find_cap(int bus, int slot, int func, int cap)
 {
         int bytes;
         u8 pos;
 
-        if (!(read_pci_config_16(num, slot, func, PCI_STATUS) &
+        if (!(read_pci_config_16(bus, slot, func, PCI_STATUS) &
                                                 PCI_STATUS_CAP_LIST))
                 return 0;
 
-        pos = read_pci_config_byte(num, slot, func, PCI_CAPABILITY_LIST);
+        pos = read_pci_config_byte(bus, slot, func, PCI_CAPABILITY_LIST);
         for (bytes = 0; bytes < 48 && pos >= 0x40; bytes++) {
                 u8 id;
 
                 pos &= ~3;
-                id = read_pci_config_byte(num, slot, func, pos+PCI_CAP_LIST_ID);
+                id = read_pci_config_byte(bus, slot, func, pos+PCI_CAP_LIST_ID);
                 if (id == 0xff)
                         break;
                 if (id == cap)
                         return pos;
-                pos = read_pci_config_byte(num, slot, func,
+                pos = read_pci_config_byte(bus, slot, func,
                                                 pos+PCI_CAP_LIST_NEXT);
         }
         return 0;
 }
 
 /* Read a standard AGPv3 bridge header */
-static __u32 __init read_agp(int num, int slot, int func, int cap, u32 *order)
+static u32 __init read_agp(int bus, int slot, int func, int cap, u32 *order)
 {
         u32 apsize;
         u32 apsizereg;
         int nbits;
         u32 aper_low, aper_hi;
         u64 aper;
+        u32 old_order;
 
-        printk(KERN_INFO "AGP bridge at %02x:%02x:%02x\n", num, slot, func);
-        apsizereg = read_pci_config_16(num, slot, func, cap + 0x14);
+        printk(KERN_INFO "AGP bridge at %02x:%02x:%02x\n", bus, slot, func);
+        apsizereg = read_pci_config_16(bus, slot, func, cap + 0x14);
         if (apsizereg == 0xffffffff) {
                 printk(KERN_ERR "APSIZE in AGP bridge unreadable\n");
                 return 0;
         }
 
+        /* old_order could be the value from NB gart setting */
+        old_order = *order;
+
         apsize = apsizereg & 0xfff;
         /* Some BIOS use weird encodings not in the AGPv3 table. */
         if (apsize & 0xff)
@@ -155,14 +165,26 @@ static __u32 __init read_agp(int num, int slot, int func, int cap, u32 *order)
         if ((int)*order < 0) /* < 32MB */
                 *order = 0;
 
-        aper_low = read_pci_config(num, slot, func, 0x10);
-        aper_hi = read_pci_config(num, slot, func, 0x14);
+        aper_low = read_pci_config(bus, slot, func, 0x10);
+        aper_hi = read_pci_config(bus, slot, func, 0x14);
         aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32);
 
+        /*
+         * On some sick chips, APSIZE is 0. It means it wants 4G
+         * so let double check that order, and lets trust AMD NB settings:
+         */
+        printk(KERN_INFO "Aperture from AGP @ %Lx old size %u MB\n",
+                        aper, 32 << old_order);
+        if (aper + (32ULL<<(20 + *order)) > 0x100000000ULL) {
+                printk(KERN_INFO "Aperture size %u MB (APSIZE %x) is not right, using settings from NB\n",
+                                32 << *order, apsizereg);
+                *order = old_order;
+        }
+
         printk(KERN_INFO "Aperture from AGP @ %Lx size %u MB (APSIZE %x)\n",
                         aper, 32 << *order, apsizereg);
 
-        if (!aperture_valid(aper, (32*1024*1024) << *order))
+        if (!aperture_valid(aper, (32*1024*1024) << *order, 32<<20))
                 return 0;
         return (u32)aper;
 }
@@ -180,17 +202,17 @@ static __u32 __init read_agp(int num, int slot, int func, int cap, u32 *order)
  * the AGP bridges should be always an own bus on the HT hierarchy,
  * but do it here for future safety.
  */
-static __u32 __init search_agp_bridge(u32 *order, int *valid_agp)
+static u32 __init search_agp_bridge(u32 *order, int *valid_agp)
 {
-        int num, slot, func;
+        int bus, slot, func;
 
         /* Poor man's PCI discovery */
-        for (num = 0; num < 256; num++) {
+        for (bus = 0; bus < 256; bus++) {
                 for (slot = 0; slot < 32; slot++) {
                         for (func = 0; func < 8; func++) {
                                 u32 class, cap;
                                 u8 type;
-                                class = read_pci_config(num, slot, func,
+                                class = read_pci_config(bus, slot, func,
                                                         PCI_CLASS_REVISION);
                                 if (class == 0xffffffff)
                                         break;
@@ -199,17 +221,17 @@ static __u32 __init search_agp_bridge(u32 *order, int *valid_agp)
                                 case PCI_CLASS_BRIDGE_HOST:
                                 case PCI_CLASS_BRIDGE_OTHER: /* needed? */
                                         /* AGP bridge? */
-                                        cap = find_cap(num, slot, func,
+                                        cap = find_cap(bus, slot, func,
                                                         PCI_CAP_ID_AGP);
                                         if (!cap)
                                                 break;
                                         *valid_agp = 1;
-                                        return read_agp(num, slot, func, cap,
+                                        return read_agp(bus, slot, func, cap,
                                                         order);
                                 }
 
                                 /* No multi-function device? */
-                                type = read_pci_config_byte(num, slot, func,
+                                type = read_pci_config_byte(bus, slot, func,
                                                                PCI_HEADER_TYPE);
                                 if (!(type & 0x80))
                                         break;
@@ -249,36 +271,50 @@ void __init early_gart_iommu_check(void)
          * or BIOS forget to put that in reserved.
          * try to update e820 to make that region as reserved.
          */
-        int fix, num;
+        int i, fix, slot;
         u32 ctl;
         u32 aper_size = 0, aper_order = 0, last_aper_order = 0;
         u64 aper_base = 0, last_aper_base = 0;
-        int aper_enabled = 0, last_aper_enabled = 0;
+        int aper_enabled = 0, last_aper_enabled = 0, last_valid = 0;
 
         if (!early_pci_allowed())
                 return;
 
+        /* This is mostly duplicate of iommu_hole_init */
         fix = 0;
-        for (num = 24; num < 32; num++) {
-                if (!early_is_k8_nb(read_pci_config(0, num, 3, 0x00)))
-                        continue;
-
-                ctl = read_pci_config(0, num, 3, 0x90);
-                aper_enabled = ctl & 1;
-                aper_order = (ctl >> 1) & 7;
-                aper_size = (32 * 1024 * 1024) << aper_order;
-                aper_base = read_pci_config(0, num, 3, 0x94) & 0x7fff;
-                aper_base <<= 25;
-
-                if ((last_aper_order && aper_order != last_aper_order) ||
-                    (last_aper_base && aper_base != last_aper_base) ||
-                    (last_aper_enabled && aper_enabled != last_aper_enabled)) {
-                        fix = 1;
-                        break;
+        for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) {
+                int bus;
+                int dev_base, dev_limit;
+
+                bus = bus_dev_ranges[i].bus;
+                dev_base = bus_dev_ranges[i].dev_base;
+                dev_limit = bus_dev_ranges[i].dev_limit;
+
+                for (slot = dev_base; slot < dev_limit; slot++) {
+                        if (!early_is_k8_nb(read_pci_config(bus, slot, 3, 0x00)))
+                                continue;
+
+                        ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL);
+                        aper_enabled = ctl & AMD64_GARTEN;
+                        aper_order = (ctl >> 1) & 7;
+                        aper_size = (32 * 1024 * 1024) << aper_order;
+                        aper_base = read_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE) & 0x7fff;
+                        aper_base <<= 25;
+
+                        if (last_valid) {
+                                if ((aper_order != last_aper_order) ||
+                                    (aper_base != last_aper_base) ||
+                                    (aper_enabled != last_aper_enabled)) {
+                                        fix = 1;
+                                        break;
+                                }
+                        }
+
+                        last_aper_order = aper_order;
+                        last_aper_base = aper_base;
+                        last_aper_enabled = aper_enabled;
+                        last_valid = 1;
                 }
-                last_aper_order = aper_order;
-                last_aper_base = aper_base;
-                last_aper_enabled = aper_enabled;
         }
 
         if (!fix && !aper_enabled)
@@ -290,32 +326,46 @@ void __init early_gart_iommu_check(void)
         if (gart_fix_e820 && !fix && aper_enabled) {
                 if (e820_any_mapped(aper_base, aper_base + aper_size,
                                     E820_RAM)) {
-                        /* reserved it, so we can resuse it in second kernel */
+                        /* reserve it, so we can reuse it in second kernel */
                         printk(KERN_INFO "update e820 for GART\n");
-                        add_memory_region(aper_base, aper_size, E820_RESERVED);
+                        e820_add_region(aper_base, aper_size, E820_RESERVED);
                         update_e820();
                 }
-                return;
         }
 
+        if (!fix)
+                return;
+
         /* different nodes have different setting, disable them all at first*/
-        for (num = 24; num < 32; num++) {
-                if (!early_is_k8_nb(read_pci_config(0, num, 3, 0x00)))
-                        continue;
+        for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) {
+                int bus;
+                int dev_base, dev_limit;
+
+                bus = bus_dev_ranges[i].bus;
+                dev_base = bus_dev_ranges[i].dev_base;
+                dev_limit = bus_dev_ranges[i].dev_limit;
+
+                for (slot = dev_base; slot < dev_limit; slot++) {
+                        if (!early_is_k8_nb(read_pci_config(bus, slot, 3, 0x00)))
+                                continue;
 
-                ctl = read_pci_config(0, num, 3, 0x90);
-                ctl &= ~1;
-                write_pci_config(0, num, 3, 0x90, ctl);
+                        ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL);
+                        ctl &= ~AMD64_GARTEN;
+                        write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl);
+                }
         }
 
 }
 
+static int __initdata printed_gart_size_msg;
+
 void __init gart_iommu_hole_init(void)
 {
+        u32 agp_aper_base = 0, agp_aper_order = 0;
         u32 aper_size, aper_alloc = 0, aper_order = 0, last_aper_order = 0;
         u64 aper_base, last_aper_base = 0;
-        int fix, num, valid_agp = 0;
-        int node;
+        int fix, slot, valid_agp = 0;
+        int i, node;
 
         if (gart_iommu_aperture_disabled || !fix_aperture ||
             !early_pci_allowed())
@@ -323,38 +373,65 @@ void __init gart_iommu_hole_init(void)
 
         printk(KERN_INFO  "Checking aperture...\n");
 
+        if (!fallback_aper_force)
+                agp_aper_base = search_agp_bridge(&agp_aper_order, &valid_agp);
+
         fix = 0;
         node = 0;
-        for (num = 24; num < 32; num++) {
-                if (!early_is_k8_nb(read_pci_config(0, num, 3, 0x00)))
-                        continue;
-
-                iommu_detected = 1;
-                gart_iommu_aperture = 1;
-
-                aper_order = (read_pci_config(0, num, 3, 0x90) >> 1) & 7;
-                aper_size = (32 * 1024 * 1024) << aper_order;
-                aper_base = read_pci_config(0, num, 3, 0x94) & 0x7fff;
-                aper_base <<= 25;
-
-                printk(KERN_INFO "Node %d: aperture @ %Lx size %u MB\n",
-                                node, aper_base, aper_size >> 20);
-                node++;
-
-                if (!aperture_valid(aper_base, aper_size)) {
-                        fix = 1;
-                        break;
-                }
+        for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) {
+                int bus;
+                int dev_base, dev_limit;
+
+                bus = bus_dev_ranges[i].bus;
+                dev_base = bus_dev_ranges[i].dev_base;
+                dev_limit = bus_dev_ranges[i].dev_limit;
+
+                for (slot = dev_base; slot < dev_limit; slot++) {
+                        if (!early_is_k8_nb(read_pci_config(bus, slot, 3, 0x00)))
+                                continue;
+
+                        iommu_detected = 1;
+                        gart_iommu_aperture = 1;
+
+                        aper_order = (read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL) >> 1) & 7;
+                        aper_size = (32 * 1024 * 1024) << aper_order;
+                        aper_base = read_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE) & 0x7fff;
+                        aper_base <<= 25;
+
+                        printk(KERN_INFO "Node %d: aperture @ %Lx size %u MB\n",
+                                        node, aper_base, aper_size >> 20);
+                        node++;
+
+                        if (!aperture_valid(aper_base, aper_size, 64<<20)) {
+                                if (valid_agp && agp_aper_base &&
+                                    agp_aper_base == aper_base &&
+                                    agp_aper_order == aper_order) {
+                                        /* the same between two setting from NB and agp */
+                                        if (!no_iommu &&
+                                            max_pfn > MAX_DMA32_PFN &&
+                                            !printed_gart_size_msg) {
+                                                printk(KERN_ERR "you are using iommu with agp, but GART size is less than 64M\n");
+                                                printk(KERN_ERR "please increase GART size in your BIOS setup\n");
+                                                printk(KERN_ERR "if BIOS doesn't have that option, contact your HW vendor!\n");
+                                                printed_gart_size_msg = 1;
+                                        }
+                                } else {
+                                        fix = 1;
+                                        goto out;
+                                }
+                        }
 
-                if ((last_aper_order && aper_order != last_aper_order) ||
-                    (last_aper_base && aper_base != last_aper_base)) {
-                        fix = 1;
-                        break;
+                        if ((last_aper_order && aper_order != last_aper_order) ||
+                            (last_aper_base && aper_base != last_aper_base)) {
+                                fix = 1;
+                                goto out;
+                        }
+                        last_aper_order = aper_order;
+                        last_aper_base = aper_base;
                 }
-                last_aper_order = aper_order;
-                last_aper_base = aper_base;
         }
 
+out:
         if (!fix && !fallback_aper_force) {
                 if (last_aper_base) {
                         unsigned long n = (32 * 1024 * 1024) << last_aper_order;
@@ -364,14 +441,16 @@ void __init gart_iommu_hole_init(void)
                 return;
         }
 
-        if (!fallback_aper_force)
-                aper_alloc = search_agp_bridge(&aper_order, &valid_agp);
+        if (!fallback_aper_force) {
+                aper_alloc = agp_aper_base;
+                aper_order = agp_aper_order;
+        }
 
         if (aper_alloc) {
                 /* Got the aperture from the AGP bridge */
         } else if (swiotlb && !valid_agp) {
                 /* Do nothing */
-        } else if ((!no_iommu && end_pfn > MAX_DMA32_PFN) ||
+        } else if ((!no_iommu && max_pfn > MAX_DMA32_PFN) ||
                    force_iommu ||
                    valid_agp ||
                    fallback_aper_force) {
@@ -401,16 +480,24 @@ void __init gart_iommu_hole_init(void)
         }
 
         /* Fix up the north bridges */
-        for (num = 24; num < 32; num++) {
-                if (!early_is_k8_nb(read_pci_config(0, num, 3, 0x00)))
-                        continue;
-
-                /*
-                 * Don't enable translation yet. That is done later.
-                 * Assume this BIOS didn't initialise the GART so
-                 * just overwrite all previous bits
-                 */
-                write_pci_config(0, num, 3, 0x90, aper_order<<1);
-                write_pci_config(0, num, 3, 0x94, aper_alloc>>25);
+        for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) {
+                int bus;
+                int dev_base, dev_limit;
+
+                bus = bus_dev_ranges[i].bus;
+                dev_base = bus_dev_ranges[i].dev_base;
+                dev_limit = bus_dev_ranges[i].dev_limit;
+                for (slot = dev_base; slot < dev_limit; slot++) {
+                        if (!early_is_k8_nb(read_pci_config(bus, slot, 3, 0x00)))
+                                continue;
+
+                        /* Don't enable translation yet. That is done later.
+                           Assume this BIOS didn't initialise the GART so
+                           just overwrite all previous bits */
+                        write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, aper_order << 1);
+                        write_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE, aper_alloc >> 25);
+                }
         }
+
+        set_up_gart_resume(aper_order, aper_alloc);
 }
diff --git a/arch/x86/kernel/apic_32.c b/arch/x86/kernel/apic_32.c
index 4b99b1bdeb6c..3e58b676d23b 100644
--- a/arch/x86/kernel/apic_32.c
+++ b/arch/x86/kernel/apic_32.c
@@ -52,30 +52,41 @@
 
 unsigned long mp_lapic_addr;
 
-DEFINE_PER_CPU(u16, x86_bios_cpu_apicid) = BAD_APICID;
-EXPORT_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
-
 /*
  * Knob to control our willingness to enable the local APIC.
  *
- * -1=force-disable, +1=force-enable
+ * +1=force-enable
  */
-static int enable_local_apic __initdata;
+static int force_enable_local_apic;
+int disable_apic;
 
 /* Local APIC timer verification ok */
 static int local_apic_timer_verify_ok;
-/* Disable local APIC timer from the kernel commandline or via dmi quirk
-   or using CPU MSR check */
-int local_apic_timer_disabled;
+/* Disable local APIC timer from the kernel commandline or via dmi quirk */
+static int local_apic_timer_disabled;
 /* Local APIC timer works in C2 */
 int local_apic_timer_c2_ok;
 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
 
+int first_system_vector = 0xfe;
+
+char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE};
+
 /*
  * Debug level, exported for io_apic.c
  */
 int apic_verbosity;
 
+int pic_mode;
+
+/* Have we found an MP table */
+int smp_found_config;
+
+static struct resource lapic_resource = {
+        .name = "Local APIC",
+        .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
+};
+
 static unsigned int calibration_result;
 
 static int lapic_next_event(unsigned long delta,
@@ -545,7 +556,7 @@ void __init setup_boot_APIC_clock(void)
                         lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
                 else
                         printk(KERN_WARNING "APIC timer registered as dummy,"
-                               " due to nmi_watchdog=1!\n");
+                                " due to nmi_watchdog=%d!\n", nmi_watchdog);
         }
 
         /* Setup the lapic or request the broadcast */
@@ -963,7 +974,7 @@ void __cpuinit setup_local_APIC(void)
          * Double-check whether this APIC is really registered.
          */
         if (!apic_id_registered())
-                BUG();
+                WARN_ON_ONCE(1);
 
         /*
          * Intel recommends to set DFR, LDR and TPR before enabling
@@ -1094,7 +1105,7 @@ static int __init detect_init_APIC(void)
         u32 h, l, features;
 
         /* Disabled by kernel option? */
-        if (enable_local_apic < 0)
+        if (disable_apic)
                 return -1;
 
         switch (boot_cpu_data.x86_vendor) {
@@ -1117,7 +1128,7 @@ static int __init detect_init_APIC(void)
                  * Over-ride BIOS and try to enable the local APIC only if
                  * "lapic" specified.
                  */
-                if (enable_local_apic <= 0) {
+                if (!force_enable_local_apic) {
                         printk(KERN_INFO "Local APIC disabled by BIOS -- "
                                "you can enable it with \"lapic\"\n");
                         return -1;
@@ -1154,9 +1165,6 @@ static int __init detect_init_APIC(void)
         if (l & MSR_IA32_APICBASE_ENABLE)
                 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
 
-        if (nmi_watchdog != NMI_NONE && nmi_watchdog != NMI_DISABLED)
-                nmi_watchdog = NMI_LOCAL_APIC;
-
         printk(KERN_INFO "Found and enabled local APIC!\n");
 
         apic_pm_activate();
@@ -1195,36 +1203,6 @@ void __init init_apic_mappings(void)
         if (boot_cpu_physical_apicid == -1U)
                 boot_cpu_physical_apicid = GET_APIC_ID(read_apic_id());
 
-#ifdef CONFIG_X86_IO_APIC
-        {
-                unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
-                int i;
-
-                for (i = 0; i < nr_ioapics; i++) {
-                        if (smp_found_config) {
-                                ioapic_phys = mp_ioapics[i].mpc_apicaddr;
-                                if (!ioapic_phys) {
-                                        printk(KERN_ERR
-                                               "WARNING: bogus zero IO-APIC "
-                                               "address found in MPTABLE, "
-                                               "disabling IO/APIC support!\n");
-                                        smp_found_config = 0;
-                                        skip_ioapic_setup = 1;
-                                        goto fake_ioapic_page;
-                                }
-                        } else {
-fake_ioapic_page:
-                                ioapic_phys = (unsigned long)
-                                              alloc_bootmem_pages(PAGE_SIZE);
-                                ioapic_phys = __pa(ioapic_phys);
-                        }
-                        set_fixmap_nocache(idx, ioapic_phys);
-                        printk(KERN_DEBUG "mapped IOAPIC to %08lx (%08lx)\n",
-                               __fix_to_virt(idx), ioapic_phys);
-                        idx++;
-                }
-        }
-#endif
 }
 
 /*
@@ -1236,7 +1214,7 @@ int apic_version[MAX_APICS];
 
 int __init APIC_init_uniprocessor(void)
 {
-        if (enable_local_apic < 0)
+        if (disable_apic)
                 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
 
         if (!smp_found_config && !cpu_has_apic)
@@ -1265,10 +1243,14 @@ int __init APIC_init_uniprocessor(void)
 #ifdef CONFIG_CRASH_DUMP
         boot_cpu_physical_apicid = GET_APIC_ID(read_apic_id());
 #endif
-        phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid);
+        physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
 
         setup_local_APIC();
 
+#ifdef CONFIG_X86_IO_APIC
+        if (!smp_found_config || skip_ioapic_setup || !nr_ioapics)
+#endif
+                localise_nmi_watchdog();
         end_local_APIC_setup();
 #ifdef CONFIG_X86_IO_APIC
         if (smp_found_config)
@@ -1351,13 +1333,13 @@ void __init smp_intr_init(void)
          * The reschedule interrupt is a CPU-to-CPU reschedule-helper
          * IPI, driven by wakeup.
          */
-        set_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
+        alloc_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
 
         /* IPI for invalidation */
-        set_intr_gate(INVALIDATE_TLB_VECTOR, invalidate_interrupt);
+        alloc_intr_gate(INVALIDATE_TLB_VECTOR, invalidate_interrupt);
 
         /* IPI for generic function call */
-        set_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
+        alloc_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
 }
 #endif
 
@@ -1370,15 +1352,15 @@ void __init apic_intr_init(void)
         smp_intr_init();
 #endif
         /* self generated IPI for local APIC timer */
-        set_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
+        alloc_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
 
         /* IPI vectors for APIC spurious and error interrupts */
-        set_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
-        set_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
+        alloc_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
+        alloc_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
 
         /* thermal monitor LVT interrupt */
 #ifdef CONFIG_X86_MCE_P4THERMAL
-        set_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
+        alloc_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
 #endif
 }
 
@@ -1513,6 +1495,9 @@ void __cpuinit generic_processor_info(int apicid, int version)
                  */
                 cpu = 0;
 
+        if (apicid > max_physical_apicid)
+                max_physical_apicid = apicid;
+
         /*
          * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
          * but we need to work other dependencies like SMP_SUSPEND etc
@@ -1520,7 +1505,7 @@ void __cpuinit generic_processor_info(int apicid, int version)
          * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
          *       - Ashok Raj <ashok.raj@intel.com>
          */
-        if (num_processors > 8) {
+        if (max_physical_apicid >= 8) {
                 switch (boot_cpu_data.x86_vendor) {
                 case X86_VENDOR_INTEL:
                         if (!APIC_XAPIC(version)) {
@@ -1534,9 +1519,9 @@ void __cpuinit generic_processor_info(int apicid, int version)
         }
 #ifdef CONFIG_SMP
         /* are we being called early in kernel startup? */
-        if (x86_cpu_to_apicid_early_ptr) {
-                u16 *cpu_to_apicid = x86_cpu_to_apicid_early_ptr;
-                u16 *bios_cpu_apicid = x86_bios_cpu_apicid_early_ptr;
+        if (early_per_cpu_ptr(x86_cpu_to_apicid)) {
+                u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid);
+                u16 *bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
 
                 cpu_to_apicid[cpu] = apicid;
                 bios_cpu_apicid[cpu] = apicid;
@@ -1703,14 +1688,14 @@ static void apic_pm_activate(void) { }
  */
 static int __init parse_lapic(char *arg)
 {
-        enable_local_apic = 1;
+        force_enable_local_apic = 1;
         return 0;
 }
 early_param("lapic", parse_lapic);
 
 static int __init parse_nolapic(char *arg)
 {
-        enable_local_apic = -1;
+        disable_apic = 1;
         clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
         return 0;
 }
@@ -1740,3 +1725,21 @@ static int __init apic_set_verbosity(char *str)
 }
 __setup("apic=", apic_set_verbosity);
 
+static int __init lapic_insert_resource(void)
+{
+        if (!apic_phys)
+                return -1;
+
+        /* Put local APIC into the resource map. */
+        lapic_resource.start = apic_phys;
+        lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
+        insert_resource(&iomem_resource, &lapic_resource);
+
+        return 0;
+}
+
+/*
+ * need call insert after e820_reserve_resources()
+ * that is using request_resource
+ */
+late_initcall(lapic_insert_resource);
diff --git a/arch/x86/kernel/apic_64.c b/arch/x86/kernel/apic_64.c
index 0633cfd0dc29..1e3d32e27c14 100644
--- a/arch/x86/kernel/apic_64.c
+++ b/arch/x86/kernel/apic_64.c
@@ -43,7 +43,7 @@
 #include <mach_ipi.h>
 #include <mach_apic.h>
 
-int disable_apic_timer __cpuinitdata;
+static int disable_apic_timer __cpuinitdata;
 static int apic_calibrate_pmtmr __initdata;
 int disable_apic;
 
@@ -56,6 +56,9 @@ EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
  */
 int apic_verbosity;
 
+/* Have we found an MP table */
+int smp_found_config;
+
 static struct resource lapic_resource = {
         .name = "Local APIC",
         .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
@@ -87,9 +90,6 @@ static unsigned long apic_phys;
 
 unsigned long mp_lapic_addr;
 
-DEFINE_PER_CPU(u16, x86_bios_cpu_apicid) = BAD_APICID;
-EXPORT_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
-
 unsigned int __cpuinitdata maxcpus = NR_CPUS;
 /*
  * Get the LAPIC version
@@ -417,37 +417,13 @@ void __init setup_boot_APIC_clock(void)
                 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
         else
                 printk(KERN_WARNING "APIC timer registered as dummy,"
-                       " due to nmi_watchdog=1!\n");
+                        " due to nmi_watchdog=%d!\n", nmi_watchdog);
 
         setup_APIC_timer();
 }
 
-/*
- * AMD C1E enabled CPUs have a real nasty problem: Some BIOSes set the
- * C1E flag only in the secondary CPU, so when we detect the wreckage
- * we already have enabled the boot CPU local apic timer. Check, if
- * disable_apic_timer is set and the DUMMY flag is cleared. If yes,
- * set the DUMMY flag again and force the broadcast mode in the
- * clockevents layer.
- */
-static void __cpuinit check_boot_apic_timer_broadcast(void)
-{
-        if (!disable_apic_timer ||
-            (lapic_clockevent.features & CLOCK_EVT_FEAT_DUMMY))
-                return;
-
-        printk(KERN_INFO "AMD C1E detected late. Force timer broadcast.\n");
-        lapic_clockevent.features |= CLOCK_EVT_FEAT_DUMMY;
-
-        local_irq_enable();
-        clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
-                           &boot_cpu_physical_apicid);
-        local_irq_disable();
-}
-
 void __cpuinit setup_secondary_APIC_clock(void)
 {
-        check_boot_apic_timer_broadcast();
         setup_APIC_timer();
 }
 
@@ -850,7 +826,6 @@ static void __cpuinit lapic_setup_esr(void)
 void __cpuinit end_local_APIC_setup(void)
 {
         lapic_setup_esr();
-        nmi_watchdog_default();
         setup_apic_nmi_watchdog(NULL);
         apic_pm_activate();
 }
@@ -875,7 +850,7 @@ static int __init detect_init_APIC(void)
 
 void __init early_init_lapic_mapping(void)
 {
-        unsigned long apic_phys;
+        unsigned long phys_addr;
 
         /*
          * If no local APIC can be found then go out
@@ -884,11 +859,11 @@ void __init early_init_lapic_mapping(void)
         if (!smp_found_config)
                 return;
 
-        apic_phys = mp_lapic_addr;
+        phys_addr = mp_lapic_addr;
 
-        set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
+        set_fixmap_nocache(FIX_APIC_BASE, phys_addr);
         apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
-                                 APIC_BASE, apic_phys);
+                    APIC_BASE, phys_addr);
 
         /*
          * Fetch the APIC ID of the BSP in case we have a
@@ -942,7 +917,9 @@ int __init APIC_init_uniprocessor(void)
 
         verify_local_APIC();
 
-        phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid);
+        connect_bsp_APIC();
+
+        physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
         apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
 
         setup_local_APIC();
@@ -954,6 +931,8 @@ int __init APIC_init_uniprocessor(void)
         if (!skip_ioapic_setup && nr_ioapics)
                 enable_IO_APIC();
 
+        if (!smp_found_config || skip_ioapic_setup || !nr_ioapics)
+                localise_nmi_watchdog();
         end_local_APIC_setup();
 
         if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
@@ -1021,6 +1000,14 @@ asmlinkage void smp_error_interrupt(void)
         irq_exit();
 }
 
+/**
+ *  * connect_bsp_APIC - attach the APIC to the interrupt system
+ *   */
+void __init connect_bsp_APIC(void)
+{
+        enable_apic_mode();
+}
+
 void disconnect_bsp_APIC(int virt_wire_setup)
 {
         /* Go back to Virtual Wire compatibility mode */
@@ -1090,10 +1077,13 @@ void __cpuinit generic_processor_info(int apicid, int version)
                  */
                 cpu = 0;
         }
+        if (apicid > max_physical_apicid)
+                max_physical_apicid = apicid;
+
         /* are we being called early in kernel startup? */
-        if (x86_cpu_to_apicid_early_ptr) {
-                u16 *cpu_to_apicid = x86_cpu_to_apicid_early_ptr;
-                u16 *bios_cpu_apicid = x86_bios_cpu_apicid_early_ptr;
+        if (early_per_cpu_ptr(x86_cpu_to_apicid)) {
+                u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid);
+                u16 *bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
 
                 cpu_to_apicid[cpu] = apicid;
                 bios_cpu_apicid[cpu] = apicid;
@@ -1269,7 +1259,7 @@ __cpuinit int apic_is_clustered_box(void)
         if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box())
                 return 0;
 
-        bios_cpu_apicid = x86_bios_cpu_apicid_early_ptr;
+        bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
         bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
 
         for (i = 0; i < NR_CPUS; i++) {
diff --git a/arch/x86/kernel/apm_32.c b/arch/x86/kernel/apm_32.c
index bf9290e29013..75cb5da4ea0a 100644
--- a/arch/x86/kernel/apm_32.c
+++ b/arch/x86/kernel/apm_32.c
@@ -204,6 +204,7 @@
 #include <linux/module.h>
 
 #include <linux/poll.h>
+#include <linux/smp_lock.h>
 #include <linux/types.h>
 #include <linux/stddef.h>
 #include <linux/timer.h>
@@ -228,6 +229,7 @@
 #include <linux/suspend.h>
 #include <linux/kthread.h>
 #include <linux/jiffies.h>
+#include <linux/smp_lock.h>
 
 #include <asm/system.h>
 #include <asm/uaccess.h>
@@ -1149,7 +1151,7 @@ static void queue_event(apm_event_t event, struct apm_user *sender)
                                 as->event_tail = 0;
                 }
                 as->events[as->event_head] = event;
-                if ((!as->suser) || (!as->writer))
+                if (!as->suser || !as->writer)
                         continue;
                 switch (event) {
                 case APM_SYS_SUSPEND:
@@ -1396,7 +1398,7 @@ static void apm_mainloop(void)
 
 static int check_apm_user(struct apm_user *as, const char *func)
 {
-        if ((as == NULL) || (as->magic != APM_BIOS_MAGIC)) {
+        if (as == NULL || as->magic != APM_BIOS_MAGIC) {
                 printk(KERN_ERR "apm: %s passed bad filp\n", func);
                 return 1;
         }
@@ -1459,18 +1461,19 @@ static unsigned int do_poll(struct file *fp, poll_table *wait)
         return 0;
 }
 
-static int do_ioctl(struct inode *inode, struct file *filp,
-                    u_int cmd, u_long arg)
+static long do_ioctl(struct file *filp, u_int cmd, u_long arg)
 {
         struct apm_user *as;
+        int ret;
 
         as = filp->private_data;
         if (check_apm_user(as, "ioctl"))
                 return -EIO;
-        if ((!as->suser) || (!as->writer))
+        if (!as->suser || !as->writer)
                 return -EPERM;
         switch (cmd) {
         case APM_IOC_STANDBY:
+                lock_kernel();
                 if (as->standbys_read > 0) {
                         as->standbys_read--;
                         as->standbys_pending--;
@@ -1479,8 +1482,10 @@ static int do_ioctl(struct inode *inode, struct file *filp,
                         queue_event(APM_USER_STANDBY, as);
                 if (standbys_pending <= 0)
                         standby();
+                unlock_kernel();
                 break;
         case APM_IOC_SUSPEND:
+                lock_kernel();
                 if (as->suspends_read > 0) {
                         as->suspends_read--;
                         as->suspends_pending--;
@@ -1488,16 +1493,17 @@ static int do_ioctl(struct inode *inode, struct file *filp,
                 } else
                         queue_event(APM_USER_SUSPEND, as);
                 if (suspends_pending <= 0) {
-                        return suspend(1);
+                        ret = suspend(1);
                 } else {
                         as->suspend_wait = 1;
                         wait_event_interruptible(apm_suspend_waitqueue,
                                         as->suspend_wait == 0);
-                        return as->suspend_result;
+                        ret = as->suspend_result;
                 }
-                break;
+                unlock_kernel();
+                return ret;
         default:
-                return -EINVAL;
+                return -ENOTTY;
         }
         return 0;
 }
@@ -1544,10 +1550,12 @@ static int do_open(struct inode *inode, struct file *filp)
 {
         struct apm_user *as;
 
+        lock_kernel();
         as = kmalloc(sizeof(*as), GFP_KERNEL);
         if (as == NULL) {
                 printk(KERN_ERR "apm: cannot allocate struct of size %d bytes\n",
                        sizeof(*as));
+                       unlock_kernel();
                 return -ENOMEM;
         }
         as->magic = APM_BIOS_MAGIC;
@@ -1569,6 +1577,7 @@ static int do_open(struct inode *inode, struct file *filp)
         user_list = as;
         spin_unlock(&user_list_lock);
         filp->private_data = as;
+        unlock_kernel();
         return 0;
 }
 
@@ -1860,7 +1869,7 @@ static const struct file_operations apm_bios_fops = {
         .owner          = THIS_MODULE,
         .read           = do_read,
         .poll           = do_poll,
-        .ioctl          = do_ioctl,
+        .unlocked_ioctl = do_ioctl,
         .open           = do_open,
         .release        = do_release,
 };
diff --git a/arch/x86/kernel/asm-offsets_32.c b/arch/x86/kernel/asm-offsets_32.c
index 92588083950f..6649d09ad88f 100644
--- a/arch/x86/kernel/asm-offsets_32.c
+++ b/arch/x86/kernel/asm-offsets_32.c
@@ -111,7 +111,7 @@ void foo(void)
         OFFSET(PV_IRQ_irq_disable, pv_irq_ops, irq_disable);
         OFFSET(PV_IRQ_irq_enable, pv_irq_ops, irq_enable);
         OFFSET(PV_CPU_iret, pv_cpu_ops, iret);
-        OFFSET(PV_CPU_irq_enable_syscall_ret, pv_cpu_ops, irq_enable_syscall_ret);
+        OFFSET(PV_CPU_irq_enable_sysexit, pv_cpu_ops, irq_enable_sysexit);
         OFFSET(PV_CPU_read_cr0, pv_cpu_ops, read_cr0);
 #endif
 
diff --git a/arch/x86/kernel/asm-offsets_64.c b/arch/x86/kernel/asm-offsets_64.c
index f126c05d6170..bacf5deeec2d 100644
--- a/arch/x86/kernel/asm-offsets_64.c
+++ b/arch/x86/kernel/asm-offsets_64.c
@@ -34,7 +34,7 @@ int main(void)
         ENTRY(pid);
         BLANK();
 #undef ENTRY
-#define ENTRY(entry) DEFINE(threadinfo_ ## entry, offsetof(struct thread_info, entry))
+#define ENTRY(entry) DEFINE(TI_ ## entry, offsetof(struct thread_info, entry))
         ENTRY(flags);
         ENTRY(addr_limit);
         ENTRY(preempt_count);
@@ -61,8 +61,11 @@ int main(void)
         OFFSET(PARAVIRT_PATCH_pv_irq_ops, paravirt_patch_template, pv_irq_ops);
         OFFSET(PV_IRQ_irq_disable, pv_irq_ops, irq_disable);
         OFFSET(PV_IRQ_irq_enable, pv_irq_ops, irq_enable);
+        OFFSET(PV_IRQ_adjust_exception_frame, pv_irq_ops, adjust_exception_frame);
         OFFSET(PV_CPU_iret, pv_cpu_ops, iret);
-        OFFSET(PV_CPU_irq_enable_syscall_ret, pv_cpu_ops, irq_enable_syscall_ret);
+        OFFSET(PV_CPU_usergs_sysret32, pv_cpu_ops, usergs_sysret32);
+        OFFSET(PV_CPU_usergs_sysret64, pv_cpu_ops, usergs_sysret64);
+        OFFSET(PV_CPU_irq_enable_sysexit, pv_cpu_ops, irq_enable_sysexit);
         OFFSET(PV_CPU_swapgs, pv_cpu_ops, swapgs);
         OFFSET(PV_MMU_read_cr2, pv_mmu_ops, read_cr2);
 #endif
diff --git a/arch/x86/kernel/cpu/Makefile b/arch/x86/kernel/cpu/Makefile
index a0c6f8190887..ee76eaad3001 100644
--- a/arch/x86/kernel/cpu/Makefile
+++ b/arch/x86/kernel/cpu/Makefile
@@ -6,11 +6,15 @@ obj-y			:= intel_cacheinfo.o addon_cpuid_features.o
 obj-y                   += proc.o feature_names.o
 
 obj-$(CONFIG_X86_32)    += common.o bugs.o
+obj-$(CONFIG_X86_64)    += common_64.o bugs_64.o
 obj-$(CONFIG_X86_32)    += amd.o
+obj-$(CONFIG_X86_64)    += amd_64.o
 obj-$(CONFIG_X86_32)    += cyrix.o
 obj-$(CONFIG_X86_32)    += centaur.o
+obj-$(CONFIG_X86_64)    += centaur_64.o
 obj-$(CONFIG_X86_32)    += transmeta.o
 obj-$(CONFIG_X86_32)    += intel.o
+obj-$(CONFIG_X86_64)    += intel_64.o
 obj-$(CONFIG_X86_32)    += umc.o
 
 obj-$(CONFIG_X86_MCE)   += mcheck/
diff --git a/arch/x86/kernel/cpu/addon_cpuid_features.c b/arch/x86/kernel/cpu/addon_cpuid_features.c
index c2e1ce33c7cb..84a8220a6072 100644
--- a/arch/x86/kernel/cpu/addon_cpuid_features.c
+++ b/arch/x86/kernel/cpu/addon_cpuid_features.c
@@ -1,9 +1,7 @@
-
 /*
  *      Routines to indentify additional cpu features that are scattered in
  *      cpuid space.
  */
-
 #include <linux/cpu.h>
 
 #include <asm/pat.h>
@@ -53,19 +51,20 @@ void __cpuinit init_scattered_cpuid_features(struct cpuinfo_x86 *c)
 #ifdef CONFIG_X86_PAT
 void __cpuinit validate_pat_support(struct cpuinfo_x86 *c)
 {
+        if (!cpu_has_pat)
+                pat_disable("PAT not supported by CPU.");
+
         switch (c->x86_vendor) {
-        case X86_VENDOR_AMD:
-                if (c->x86 >= 0xf && c->x86 <= 0x11)
-                        return;
-                break;
         case X86_VENDOR_INTEL:
                 if (c->x86 == 0xF || (c->x86 == 6 && c->x86_model >= 15))
                         return;
                 break;
+        case X86_VENDOR_AMD:
+        case X86_VENDOR_CENTAUR:
+        case X86_VENDOR_TRANSMETA:
+                return;
         }
 
-        pat_disable(cpu_has_pat ?
-                    "PAT disabled. Not yet verified on this CPU type." :
-                    "PAT not supported by CPU.");
+        pat_disable("PAT disabled. Not yet verified on this CPU type.");
 }
 #endif
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 245866828294..81a07ca65d44 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -24,43 +24,6 @@
 extern void vide(void);
 __asm__(".align 4\nvide: ret");
 
-#ifdef CONFIG_X86_LOCAL_APIC
-#define ENABLE_C1E_MASK         0x18000000
-#define CPUID_PROCESSOR_SIGNATURE       1
-#define CPUID_XFAM              0x0ff00000
-#define CPUID_XFAM_K8           0x00000000
-#define CPUID_XFAM_10H          0x00100000
-#define CPUID_XFAM_11H          0x00200000
-#define CPUID_XMOD              0x000f0000
-#define CPUID_XMOD_REV_F        0x00040000
-
-/* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
-static __cpuinit int amd_apic_timer_broken(void)
-{
-        u32 lo, hi;
-        u32 eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
-        switch (eax & CPUID_XFAM) {
-        case CPUID_XFAM_K8:
-                if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)
-                        break;
-        case CPUID_XFAM_10H:
-        case CPUID_XFAM_11H:
-                rdmsr(MSR_K8_ENABLE_C1E, lo, hi);
-                if (lo & ENABLE_C1E_MASK) {
-                        if (smp_processor_id() != boot_cpu_physical_apicid)
-                                printk(KERN_INFO "AMD C1E detected late. "
-                                       "        Force timer broadcast.\n");
-                        return 1;
-                }
-                break;
-        default:
-                /* err on the side of caution */
-                return 1;
-        }
-        return 0;
-}
-#endif
-
 int force_mwait __cpuinitdata;
 
 static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
@@ -297,11 +260,6 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
                         num_cache_leaves = 3;
         }
 
-#ifdef CONFIG_X86_LOCAL_APIC
-        if (amd_apic_timer_broken())
-                local_apic_timer_disabled = 1;
-#endif
-
         /* K6s reports MCEs but don't actually have all the MSRs */
         if (c->x86 < 6)
                 clear_cpu_cap(c, X86_FEATURE_MCE);
diff --git a/arch/x86/kernel/cpu/amd_64.c b/arch/x86/kernel/cpu/amd_64.c
new file mode 100644
index 000000000000..7c36fb8a28d4
--- /dev/null
+++ b/arch/x86/kernel/cpu/amd_64.c
@@ -0,0 +1,222 @@
+#include <linux/init.h>
+#include <linux/mm.h>
+
+#include <asm/numa_64.h>
+#include <asm/mmconfig.h>
+#include <asm/cacheflush.h>
+
+#include <mach_apic.h>
+
+#include "cpu.h"
+
+int force_mwait __cpuinitdata;
+
+#ifdef CONFIG_NUMA
+static int __cpuinit nearby_node(int apicid)
+{
+        int i, node;
+
+        for (i = apicid - 1; i >= 0; i--) {
+                node = apicid_to_node[i];
+                if (node != NUMA_NO_NODE && node_online(node))
+                        return node;
+        }
+        for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
+                node = apicid_to_node[i];
+                if (node != NUMA_NO_NODE && node_online(node))
+                        return node;
+        }
+        return first_node(node_online_map); /* Shouldn't happen */
+}
+#endif
+
+/*
+ * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
+ * Assumes number of cores is a power of two.
+ */
+static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c)
+{
+#ifdef CONFIG_SMP
+        unsigned bits;
+#ifdef CONFIG_NUMA
+        int cpu = smp_processor_id();
+        int node = 0;
+        unsigned apicid = hard_smp_processor_id();
+#endif
+        bits = c->x86_coreid_bits;
+
+        /* Low order bits define the core id (index of core in socket) */
+        c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
+        /* Convert the initial APIC ID into the socket ID */
+        c->phys_proc_id = c->initial_apicid >> bits;
+
+#ifdef CONFIG_NUMA
+        node = c->phys_proc_id;
+        if (apicid_to_node[apicid] != NUMA_NO_NODE)
+                node = apicid_to_node[apicid];
+        if (!node_online(node)) {
+                /* Two possibilities here:
+                   - The CPU is missing memory and no node was created.
+                   In that case try picking one from a nearby CPU
+                   - The APIC IDs differ from the HyperTransport node IDs
+                   which the K8 northbridge parsing fills in.
+                   Assume they are all increased by a constant offset,
+                   but in the same order as the HT nodeids.
+                   If that doesn't result in a usable node fall back to the
+                   path for the previous case.  */
+
+                int ht_nodeid = c->initial_apicid;
+
+                if (ht_nodeid >= 0 &&
+                    apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
+                        node = apicid_to_node[ht_nodeid];
+                /* Pick a nearby node */
+                if (!node_online(node))
+                        node = nearby_node(apicid);
+        }
+        numa_set_node(cpu, node);
+
+        printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
+#endif
+#endif
+}
+
+static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c)
+{
+#ifdef CONFIG_SMP
+        unsigned bits, ecx;
+
+        /* Multi core CPU? */
+        if (c->extended_cpuid_level < 0x80000008)
+                return;
+
+        ecx = cpuid_ecx(0x80000008);
+
+        c->x86_max_cores = (ecx & 0xff) + 1;
+
+        /* CPU telling us the core id bits shift? */
+        bits = (ecx >> 12) & 0xF;
+
+        /* Otherwise recompute */
+        if (bits == 0) {
+                while ((1 << bits) < c->x86_max_cores)
+                        bits++;
+        }
+
+        c->x86_coreid_bits = bits;
+
+#endif
+}
+
+static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
+{
+        early_init_amd_mc(c);
+
+        /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
+        if (c->x86_power & (1<<8))
+                set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
+}
+
+static void __cpuinit init_amd(struct cpuinfo_x86 *c)
+{
+        unsigned level;
+
+#ifdef CONFIG_SMP
+        unsigned long value;
+
+        /*
+         * Disable TLB flush filter by setting HWCR.FFDIS on K8
+         * bit 6 of msr C001_0015
+         *
+         * Errata 63 for SH-B3 steppings
+         * Errata 122 for all steppings (F+ have it disabled by default)
+         */
+        if (c->x86 == 0xf) {
+                rdmsrl(MSR_K8_HWCR, value);
+                value |= 1 << 6;
+                wrmsrl(MSR_K8_HWCR, value);
+        }
+#endif
+
+        /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
+           3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
+        clear_cpu_cap(c, 0*32+31);
+
+        /* On C+ stepping K8 rep microcode works well for copy/memset */
+        if (c->x86 == 0xf) {
+                level = cpuid_eax(1);
+                if((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58)
+                        set_cpu_cap(c, X86_FEATURE_REP_GOOD);
+        }
+        if (c->x86 == 0x10 || c->x86 == 0x11)
+                set_cpu_cap(c, X86_FEATURE_REP_GOOD);
+
+        /* Enable workaround for FXSAVE leak */
+        if (c->x86 >= 6)
+                set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);
+
+        level = get_model_name(c);
+        if (!level) {
+                switch (c->x86) {
+                case 0xf:
+                        /* Should distinguish Models here, but this is only
+                           a fallback anyways. */
+                        strcpy(c->x86_model_id, "Hammer");
+                        break;
+                }
+        }
+        display_cacheinfo(c);
+
+        /* Multi core CPU? */
+        if (c->extended_cpuid_level >= 0x80000008)
+                amd_detect_cmp(c);
+
+        if (c->extended_cpuid_level >= 0x80000006 &&
+                (cpuid_edx(0x80000006) & 0xf000))
+                num_cache_leaves = 4;
+        else
+                num_cache_leaves = 3;
+
+        if (c->x86 >= 0xf && c->x86 <= 0x11)
+                set_cpu_cap(c, X86_FEATURE_K8);
+
+        /* MFENCE stops RDTSC speculation */
+        set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
+
+        if (c->x86 == 0x10) {
+                /* do this for boot cpu */
+                if (c == &boot_cpu_data)
+                        check_enable_amd_mmconf_dmi();
+
+                fam10h_check_enable_mmcfg();
+        }
+
+        if (c == &boot_cpu_data && c->x86 >= 0xf && c->x86 <= 0x11) {
+                unsigned long long tseg;
+
+                /*
+                 * Split up direct mapping around the TSEG SMM area.
+                 * Don't do it for gbpages because there seems very little
+                 * benefit in doing so.
+                 */
+                if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) {
+                    printk(KERN_DEBUG "tseg: %010llx\n", tseg);
+                    if ((tseg>>PMD_SHIFT) <
+                                (max_low_pfn_mapped>>(PMD_SHIFT-PAGE_SHIFT)) ||
+                        ((tseg>>PMD_SHIFT) <
+                                (max_pfn_mapped>>(PMD_SHIFT-PAGE_SHIFT)) &&
+                         (tseg>>PMD_SHIFT) >= (1ULL<<(32 - PMD_SHIFT))))
+                        set_memory_4k((unsigned long)__va(tseg), 1);
+                }
+        }
+}
+
+static struct cpu_dev amd_cpu_dev __cpuinitdata = {
+        .c_vendor       = "AMD",
+        .c_ident        = { "AuthenticAMD" },
+        .c_early_init   = early_init_amd,
+        .c_init         = init_amd,
+};
+
+cpu_vendor_dev_register(X86_VENDOR_AMD, &amd_cpu_dev);
+
diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
index 170d2f5523b2..1b1c56bb338f 100644
--- a/arch/x86/kernel/cpu/bugs.c
+++ b/arch/x86/kernel/cpu/bugs.c
@@ -59,8 +59,12 @@ static void __init check_fpu(void)
                 return;
         }
 
-/* trap_init() enabled FXSR and company _before_ testing for FP problems here. */
-        /* Test for the divl bug.. */
+        /*
+         * trap_init() enabled FXSR and company _before_ testing for FP
+         * problems here.
+         *
+         * Test for the divl bug..
+         */
         __asm__("fninit\n\t"
                 "fldl %1\n\t"
                 "fdivl %2\n\t"
@@ -108,10 +112,15 @@ static void __init check_popad(void)
           "movl $12345678,%%eax; movl $0,%%edi; pusha; popa; movl (%%edx,%%edi),%%ecx "
           : "=&a" (res)
           : "d" (inp)
-          : "ecx", "edi" );
-        /* If this fails, it means that any user program may lock the CPU hard. Too bad. */
-        if (res != 12345678) printk( "Buggy.\n" );
-                        else printk( "OK.\n" );
+          : "ecx", "edi");
+        /*
+         * If this fails, it means that any user program may lock the
+         * CPU hard. Too bad.
+         */
+        if (res != 12345678)
+                printk("Buggy.\n");
+        else
+                printk("OK.\n");
 #endif
 }
 
@@ -137,7 +146,8 @@ static void __init check_config(void)
  * i486+ only features! (WP works in supervisor mode and the
  * new "invlpg" and "bswap" instructions)
  */
-#if defined(CONFIG_X86_WP_WORKS_OK) || defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_BSWAP)
+#if defined(CONFIG_X86_WP_WORKS_OK) || defined(CONFIG_X86_INVLPG) || \
+        defined(CONFIG_X86_BSWAP)
         if (boot_cpu_data.x86 == 3)
                 panic("Kernel requires i486+ for 'invlpg' and other features");
 #endif
@@ -170,6 +180,7 @@ void __init check_bugs(void)
         check_fpu();
         check_hlt();
         check_popad();
-        init_utsname()->machine[1] = '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86);
+        init_utsname()->machine[1] =
+                '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86);
         alternative_instructions();
 }
diff --git a/arch/x86/kernel/bugs_64.c b/arch/x86/kernel/cpu/bugs_64.c
index 9a3ed0649d4e..9a3ed0649d4e 100644
--- a/arch/x86/kernel/bugs_64.c
+++ b/arch/x86/kernel/cpu/bugs_64.c
diff --git a/arch/x86/kernel/cpu/centaur_64.c b/arch/x86/kernel/cpu/centaur_64.c
new file mode 100644
index 000000000000..1d181c40e2e1
--- /dev/null
+++ b/arch/x86/kernel/cpu/centaur_64.c
@@ -0,0 +1,35 @@
+#include <linux/init.h>
+#include <linux/smp.h>
+
+#include <asm/cpufeature.h>
+#include <asm/processor.h>
+
+#include "cpu.h"
+
+static void __cpuinit early_init_centaur(struct cpuinfo_x86 *c)
+{
+        if (c->x86 == 0x6 && c->x86_model >= 0xf)
+                set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
+
+        set_cpu_cap(c, X86_FEATURE_SYSENTER32);
+}
+
+static void __cpuinit init_centaur(struct cpuinfo_x86 *c)
+{
+        if (c->x86 == 0x6 && c->x86_model >= 0xf) {
+                c->x86_cache_alignment = c->x86_clflush_size * 2;
+                set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
+                set_cpu_cap(c, X86_FEATURE_REP_GOOD);
+        }
+        set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
+}
+
+static struct cpu_dev centaur_cpu_dev __cpuinitdata = {
+        .c_vendor       = "Centaur",
+        .c_ident        = { "CentaurHauls" },
+        .c_early_init   = early_init_centaur,
+        .c_init         = init_centaur,
+};
+
+cpu_vendor_dev_register(X86_VENDOR_CENTAUR, &centaur_cpu_dev);
+
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index d0463a946247..80ab20d4fa39 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -427,7 +427,7 @@ __setup("serialnumber", x86_serial_nr_setup);
 /*
  * This does the hard work of actually picking apart the CPU stuff...
  */
-void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
+static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
 {
         int i;
 
diff --git a/arch/x86/kernel/cpu/common_64.c b/arch/x86/kernel/cpu/common_64.c
new file mode 100644
index 000000000000..7b8cc72feb40
--- /dev/null
+++ b/arch/x86/kernel/cpu/common_64.c
@@ -0,0 +1,681 @@
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/string.h>
+#include <linux/bootmem.h>
+#include <linux/bitops.h>
+#include <linux/module.h>
+#include <linux/kgdb.h>
+#include <linux/topology.h>
+#include <linux/string.h>
+#include <linux/delay.h>
+#include <linux/smp.h>
+#include <linux/module.h>
+#include <linux/percpu.h>
+#include <asm/processor.h>
+#include <asm/i387.h>
+#include <asm/msr.h>
+#include <asm/io.h>
+#include <asm/mmu_context.h>
+#include <asm/mtrr.h>
+#include <asm/mce.h>
+#include <asm/pat.h>
+#include <asm/numa.h>
+#ifdef CONFIG_X86_LOCAL_APIC
+#include <asm/mpspec.h>
+#include <asm/apic.h>
+#include <mach_apic.h>
+#endif
+#include <asm/pda.h>
+#include <asm/pgtable.h>
+#include <asm/processor.h>
+#include <asm/desc.h>
+#include <asm/atomic.h>
+#include <asm/proto.h>
+#include <asm/sections.h>
+#include <asm/setup.h>
+#include <asm/genapic.h>
+
+#include "cpu.h"
+
+/* We need valid kernel segments for data and code in long mode too
+ * IRET will check the segment types  kkeil 2000/10/28
+ * Also sysret mandates a special GDT layout
+ */
+/* The TLS descriptors are currently at a different place compared to i386.
+   Hopefully nobody expects them at a fixed place (Wine?) */
+DEFINE_PER_CPU(struct gdt_page, gdt_page) = { .gdt = {
+        [GDT_ENTRY_KERNEL32_CS] = { { { 0x0000ffff, 0x00cf9b00 } } },
+        [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00af9b00 } } },
+        [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9300 } } },
+        [GDT_ENTRY_DEFAULT_USER32_CS] = { { { 0x0000ffff, 0x00cffb00 } } },
+        [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff300 } } },
+        [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00affb00 } } },
+} };
+EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
+
+__u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;
+
+/* Current gdt points %fs at the "master" per-cpu area: after this,
+ * it's on the real one. */
+void switch_to_new_gdt(void)
+{
+        struct desc_ptr gdt_descr;
+
+        gdt_descr.address = (long)get_cpu_gdt_table(smp_processor_id());
+        gdt_descr.size = GDT_SIZE - 1;
+        load_gdt(&gdt_descr);
+}
+
+struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
+
+static void __cpuinit default_init(struct cpuinfo_x86 *c)
+{
+        display_cacheinfo(c);
+}
+
+static struct cpu_dev __cpuinitdata default_cpu = {
+        .c_init = default_init,
+        .c_vendor = "Unknown",
+};
+static struct cpu_dev *this_cpu __cpuinitdata = &default_cpu;
+
+int __cpuinit get_model_name(struct cpuinfo_x86 *c)
+{
+        unsigned int *v;
+
+        if (c->extended_cpuid_level < 0x80000004)
+                return 0;
+
+        v = (unsigned int *) c->x86_model_id;
+        cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
+        cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
+        cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
+        c->x86_model_id[48] = 0;
+        return 1;
+}
+
+
+void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
+{
+        unsigned int n, dummy, ebx, ecx, edx;
+
+        n = c->extended_cpuid_level;
+
+        if (n >= 0x80000005) {
+                cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
+                printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), "
+                       "D cache %dK (%d bytes/line)\n",
+                       edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
+                c->x86_cache_size = (ecx>>24) + (edx>>24);
+                /* On K8 L1 TLB is inclusive, so don't count it */
+                c->x86_tlbsize = 0;
+        }
+
+        if (n >= 0x80000006) {
+                cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
+                ecx = cpuid_ecx(0x80000006);
+                c->x86_cache_size = ecx >> 16;
+                c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
+
+                printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
+                c->x86_cache_size, ecx & 0xFF);
+        }
+}
+
+void __cpuinit detect_ht(struct cpuinfo_x86 *c)
+{
+#ifdef CONFIG_SMP
+        u32 eax, ebx, ecx, edx;
+        int index_msb, core_bits;
+
+        cpuid(1, &eax, &ebx, &ecx, &edx);
+
+
+        if (!cpu_has(c, X86_FEATURE_HT))
+                return;
+        if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
+                goto out;
+
+        smp_num_siblings = (ebx & 0xff0000) >> 16;
+
+        if (smp_num_siblings == 1) {
+                printk(KERN_INFO  "CPU: Hyper-Threading is disabled\n");
+        } else if (smp_num_siblings > 1) {
+
+                if (smp_num_siblings > NR_CPUS) {
+                        printk(KERN_WARNING "CPU: Unsupported number of "
+                               "siblings %d", smp_num_siblings);
+                        smp_num_siblings = 1;
+                        return;
+                }
+
+                index_msb = get_count_order(smp_num_siblings);
+                c->phys_proc_id = phys_pkg_id(index_msb);
+
+                smp_num_siblings = smp_num_siblings / c->x86_max_cores;
+
+                index_msb = get_count_order(smp_num_siblings);
+
+                core_bits = get_count_order(c->x86_max_cores);
+
+                c->cpu_core_id = phys_pkg_id(index_msb) &
+                                               ((1 << core_bits) - 1);
+        }
+out:
+        if ((c->x86_max_cores * smp_num_siblings) > 1) {
+                printk(KERN_INFO  "CPU: Physical Processor ID: %d\n",
+                       c->phys_proc_id);
+                printk(KERN_INFO  "CPU: Processor Core ID: %d\n",
+                       c->cpu_core_id);
+        }
+
+#endif
+}
+
+static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
+{
+        char *v = c->x86_vendor_id;
+        int i;
+        static int printed;
+
+        for (i = 0; i < X86_VENDOR_NUM; i++) {
+                if (cpu_devs[i]) {
+                        if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
+                            (cpu_devs[i]->c_ident[1] &&
+                            !strcmp(v, cpu_devs[i]->c_ident[1]))) {
+                                c->x86_vendor = i;
+                                this_cpu = cpu_devs[i];
+                                return;
+                        }
+                }
+        }
+        if (!printed) {
+                printed++;
+                printk(KERN_ERR "CPU: Vendor unknown, using generic init.\n");
+                printk(KERN_ERR "CPU: Your system may be unstable.\n");
+        }
+        c->x86_vendor = X86_VENDOR_UNKNOWN;
+}
+
+static void __init early_cpu_support_print(void)
+{
+        int i,j;
+        struct cpu_dev *cpu_devx;
+
+        printk("KERNEL supported cpus:\n");
+        for (i = 0; i < X86_VENDOR_NUM; i++) {
+                cpu_devx = cpu_devs[i];
+                if (!cpu_devx)
+                        continue;
+                for (j = 0; j < 2; j++) {
+                        if (!cpu_devx->c_ident[j])
+                                continue;
+                        printk("  %s %s\n", cpu_devx->c_vendor,
+                                cpu_devx->c_ident[j]);
+                }
+        }
+}
+
+static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c);
+
+void __init early_cpu_init(void)
+{
+        struct cpu_vendor_dev *cvdev;
+
+        for (cvdev = __x86cpuvendor_start ;
+             cvdev < __x86cpuvendor_end   ;
+             cvdev++)
+                cpu_devs[cvdev->vendor] = cvdev->cpu_dev;
+        early_cpu_support_print();
+        early_identify_cpu(&boot_cpu_data);
+}
+
+/* Do some early cpuid on the boot CPU to get some parameter that are
+   needed before check_bugs. Everything advanced is in identify_cpu
+   below. */
+static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
+{
+        u32 tfms, xlvl;
+
+        c->loops_per_jiffy = loops_per_jiffy;
+        c->x86_cache_size = -1;
+        c->x86_vendor = X86_VENDOR_UNKNOWN;
+        c->x86_model = c->x86_mask = 0; /* So far unknown... */
+        c->x86_vendor_id[0] = '\0'; /* Unset */
+        c->x86_model_id[0] = '\0';  /* Unset */
+        c->x86_clflush_size = 64;
+        c->x86_cache_alignment = c->x86_clflush_size;
+        c->x86_max_cores = 1;
+        c->x86_coreid_bits = 0;
+        c->extended_cpuid_level = 0;
+        memset(&c->x86_capability, 0, sizeof c->x86_capability);
+
+        /* Get vendor name */
+        cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
+              (unsigned int *)&c->x86_vendor_id[0],
+              (unsigned int *)&c->x86_vendor_id[8],
+              (unsigned int *)&c->x86_vendor_id[4]);
+
+        get_cpu_vendor(c);
+
+        /* Initialize the standard set of capabilities */
+        /* Note that the vendor-specific code below might override */
+
+        /* Intel-defined flags: level 0x00000001 */
+        if (c->cpuid_level >= 0x00000001) {
+                __u32 misc;
+                cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4],
+                      &c->x86_capability[0]);
+                c->x86 = (tfms >> 8) & 0xf;
+                c->x86_model = (tfms >> 4) & 0xf;
+                c->x86_mask = tfms & 0xf;
+                if (c->x86 == 0xf)
+                        c->x86 += (tfms >> 20) & 0xff;
+                if (c->x86 >= 0x6)
+                        c->x86_model += ((tfms >> 16) & 0xF) << 4;
+                if (test_cpu_cap(c, X86_FEATURE_CLFLSH))
+                        c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
+        } else {
+                /* Have CPUID level 0 only - unheard of */
+                c->x86 = 4;
+        }
+
+        c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xff;
+#ifdef CONFIG_SMP
+        c->phys_proc_id = c->initial_apicid;
+#endif
+        /* AMD-defined flags: level 0x80000001 */
+        xlvl = cpuid_eax(0x80000000);
+        c->extended_cpuid_level = xlvl;
+        if ((xlvl & 0xffff0000) == 0x80000000) {
+                if (xlvl >= 0x80000001) {
+                        c->x86_capability[1] = cpuid_edx(0x80000001);
+                        c->x86_capability[6] = cpuid_ecx(0x80000001);
+                }
+                if (xlvl >= 0x80000004)
+                        get_model_name(c); /* Default name */
+        }
+
+        /* Transmeta-defined flags: level 0x80860001 */
+        xlvl = cpuid_eax(0x80860000);
+        if ((xlvl & 0xffff0000) == 0x80860000) {
+                /* Don't set x86_cpuid_level here for now to not confuse. */
+                if (xlvl >= 0x80860001)
+                        c->x86_capability[2] = cpuid_edx(0x80860001);
+        }
+
+        c->extended_cpuid_level = cpuid_eax(0x80000000);
+        if (c->extended_cpuid_level >= 0x80000007)
+                c->x86_power = cpuid_edx(0x80000007);
+
+        if (c->extended_cpuid_level >= 0x80000008) {
+                u32 eax = cpuid_eax(0x80000008);
+
+                c->x86_virt_bits = (eax >> 8) & 0xff;
+                c->x86_phys_bits = eax & 0xff;
+        }
+
+        /* Assume all 64-bit CPUs support 32-bit syscall */
+        set_cpu_cap(c, X86_FEATURE_SYSCALL32);
+
+        if (c->x86_vendor != X86_VENDOR_UNKNOWN &&
+            cpu_devs[c->x86_vendor]->c_early_init)
+                cpu_devs[c->x86_vendor]->c_early_init(c);
+
+        validate_pat_support(c);
+
+        /* early_param could clear that, but recall get it set again */
+        if (disable_apic)
+                clear_cpu_cap(c, X86_FEATURE_APIC);
+}
+
+/*
+ * This does the hard work of actually picking apart the CPU stuff...
+ */
+static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
+{
+        int i;
+
+        early_identify_cpu(c);
+
+        init_scattered_cpuid_features(c);
+
+        c->apicid = phys_pkg_id(0);
+
+        /*
+         * Vendor-specific initialization.  In this section we
+         * canonicalize the feature flags, meaning if there are
+         * features a certain CPU supports which CPUID doesn't
+         * tell us, CPUID claiming incorrect flags, or other bugs,
+         * we handle them here.
+         *
+         * At the end of this section, c->x86_capability better
+         * indicate the features this CPU genuinely supports!
+         */
+        if (this_cpu->c_init)
+                this_cpu->c_init(c);
+
+        detect_ht(c);
+
+        /*
+         * On SMP, boot_cpu_data holds the common feature set between
+         * all CPUs; so make sure that we indicate which features are
+         * common between the CPUs.  The first time this routine gets
+         * executed, c == &boot_cpu_data.
+         */
+        if (c != &boot_cpu_data) {
+                /* AND the already accumulated flags with these */
+                for (i = 0; i < NCAPINTS; i++)
+                        boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
+        }
+
+        /* Clear all flags overriden by options */
+        for (i = 0; i < NCAPINTS; i++)
+                c->x86_capability[i] &= ~cleared_cpu_caps[i];
+
+#ifdef CONFIG_X86_MCE
+        mcheck_init(c);
+#endif
+        select_idle_routine(c);
+
+#ifdef CONFIG_NUMA
+        numa_add_cpu(smp_processor_id());
+#endif
+
+}
+
+void __cpuinit identify_boot_cpu(void)
+{
+        identify_cpu(&boot_cpu_data);
+}
+
+void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
+{
+        BUG_ON(c == &boot_cpu_data);
+        identify_cpu(c);
+        mtrr_ap_init();
+}
+
+static __init int setup_noclflush(char *arg)
+{
+        setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
+        return 1;
+}
+__setup("noclflush", setup_noclflush);
+
+void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
+{
+        if (c->x86_model_id[0])
+                printk(KERN_CONT "%s", c->x86_model_id);
+
+        if (c->x86_mask || c->cpuid_level >= 0)
+                printk(KERN_CONT " stepping %02x\n", c->x86_mask);
+        else
+                printk(KERN_CONT "\n");
+}
+
+static __init int setup_disablecpuid(char *arg)
+{
+        int bit;
+        if (get_option(&arg, &bit) && bit < NCAPINTS*32)
+                setup_clear_cpu_cap(bit);
+        else
+                return 0;
+        return 1;
+}
+__setup("clearcpuid=", setup_disablecpuid);
+
+cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE;
+
+struct x8664_pda **_cpu_pda __read_mostly;
+EXPORT_SYMBOL(_cpu_pda);
+
+struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table };
+
+char boot_cpu_stack[IRQSTACKSIZE] __page_aligned_bss;
+
+unsigned long __supported_pte_mask __read_mostly = ~0UL;
+EXPORT_SYMBOL_GPL(__supported_pte_mask);
+
+static int do_not_nx __cpuinitdata;
+
+/* noexec=on|off
+Control non executable mappings for 64bit processes.
+
+on      Enable(default)
+off     Disable
+*/
+static int __init nonx_setup(char *str)
+{
+        if (!str)
+                return -EINVAL;
+        if (!strncmp(str, "on", 2)) {
+                __supported_pte_mask |= _PAGE_NX;
+                do_not_nx = 0;
+        } else if (!strncmp(str, "off", 3)) {
+                do_not_nx = 1;
+                __supported_pte_mask &= ~_PAGE_NX;
+        }
+        return 0;
+}
+early_param("noexec", nonx_setup);
+
+int force_personality32;
+
+/* noexec32=on|off
+Control non executable heap for 32bit processes.
+To control the stack too use noexec=off
+
+on      PROT_READ does not imply PROT_EXEC for 32bit processes (default)
+off     PROT_READ implies PROT_EXEC
+*/
+static int __init nonx32_setup(char *str)
+{
+        if (!strcmp(str, "on"))
+                force_personality32 &= ~READ_IMPLIES_EXEC;
+        else if (!strcmp(str, "off"))
+                force_personality32 |= READ_IMPLIES_EXEC;
+        return 1;
+}
+__setup("noexec32=", nonx32_setup);
+
+void pda_init(int cpu)
+{
+        struct x8664_pda *pda = cpu_pda(cpu);
+
+        /* Setup up data that may be needed in __get_free_pages early */
+        loadsegment(fs, 0);
+        loadsegment(gs, 0);
+        /* Memory clobbers used to order PDA accessed */
+        mb();
+        wrmsrl(MSR_GS_BASE, pda);
+        mb();
+
+        pda->cpunumber = cpu;
+        pda->irqcount = -1;
+        pda->kernelstack = (unsigned long)stack_thread_info() -
+                                 PDA_STACKOFFSET + THREAD_SIZE;
+        pda->active_mm = &init_mm;
+        pda->mmu_state = 0;
+
+        if (cpu == 0) {
+                /* others are initialized in smpboot.c */
+                pda->pcurrent = &init_task;
+                pda->irqstackptr = boot_cpu_stack;
+        } else {
+                pda->irqstackptr = (char *)
+                        __get_free_pages(GFP_ATOMIC, IRQSTACK_ORDER);
+                if (!pda->irqstackptr)
+                        panic("cannot allocate irqstack for cpu %d", cpu);
+
+                if (pda->nodenumber == 0 && cpu_to_node(cpu) != NUMA_NO_NODE)
+                        pda->nodenumber = cpu_to_node(cpu);
+        }
+
+        pda->irqstackptr += IRQSTACKSIZE-64;
+}
+
+char boot_exception_stacks[(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ +
+                           DEBUG_STKSZ]
+__attribute__((section(".bss.page_aligned")));
+
+extern asmlinkage void ignore_sysret(void);
+
+/* May not be marked __init: used by software suspend */
+void syscall_init(void)
+{
+        /*
+         * LSTAR and STAR live in a bit strange symbiosis.
+         * They both write to the same internal register. STAR allows to
+         * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
+         */
+        wrmsrl(MSR_STAR,  ((u64)__USER32_CS)<<48  | ((u64)__KERNEL_CS)<<32);
+        wrmsrl(MSR_LSTAR, system_call);
+        wrmsrl(MSR_CSTAR, ignore_sysret);
+
+#ifdef CONFIG_IA32_EMULATION
+        syscall32_cpu_init();
+#endif
+
+        /* Flags to clear on syscall */
+        wrmsrl(MSR_SYSCALL_MASK,
+               X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL);
+}
+
+void __cpuinit check_efer(void)
+{
+        unsigned long efer;
+
+        rdmsrl(MSR_EFER, efer);
+        if (!(efer & EFER_NX) || do_not_nx)
+                __supported_pte_mask &= ~_PAGE_NX;
+}
+
+unsigned long kernel_eflags;
+
+/*
+ * Copies of the original ist values from the tss are only accessed during
+ * debugging, no special alignment required.
+ */
+DEFINE_PER_CPU(struct orig_ist, orig_ist);
+
+/*
+ * cpu_init() initializes state that is per-CPU. Some data is already
+ * initialized (naturally) in the bootstrap process, such as the GDT
+ * and IDT. We reload them nevertheless, this function acts as a
+ * 'CPU state barrier', nothing should get across.
+ * A lot of state is already set up in PDA init.
+ */
+void __cpuinit cpu_init(void)
+{
+        int cpu = stack_smp_processor_id();
+        struct tss_struct *t = &per_cpu(init_tss, cpu);
+        struct orig_ist *orig_ist = &per_cpu(orig_ist, cpu);
+        unsigned long v;
+        char *estacks = NULL;
+        struct task_struct *me;
+        int i;
+
+        /* CPU 0 is initialised in head64.c */
+        if (cpu != 0)
+                pda_init(cpu);
+        else
+                estacks = boot_exception_stacks;
+
+        me = current;
+
+        if (cpu_test_and_set(cpu, cpu_initialized))
+                panic("CPU#%d already initialized!\n", cpu);
+
+        printk(KERN_INFO "Initializing CPU#%d\n", cpu);
+
+        clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
+
+        /*
+         * Initialize the per-CPU GDT with the boot GDT,
+         * and set up the GDT descriptor:
+         */
+
+        switch_to_new_gdt();
+        load_idt((const struct desc_ptr *)&idt_descr);
+
+        memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
+        syscall_init();
+
+        wrmsrl(MSR_FS_BASE, 0);
+        wrmsrl(MSR_KERNEL_GS_BASE, 0);
+        barrier();
+
+        check_efer();
+
+        /*
+         * set up and load the per-CPU TSS
+         */
+        for (v = 0; v < N_EXCEPTION_STACKS; v++) {
+                static const unsigned int order[N_EXCEPTION_STACKS] = {
+                        [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STACK_ORDER,
+                        [DEBUG_STACK - 1] = DEBUG_STACK_ORDER
+                };
+                if (cpu) {
+                        estacks = (char *)__get_free_pages(GFP_ATOMIC, order[v]);
+                        if (!estacks)
+                                panic("Cannot allocate exception stack %ld %d\n",
+                                      v, cpu);
+                }
+                estacks += PAGE_SIZE << order[v];
+                orig_ist->ist[v] = t->x86_tss.ist[v] = (unsigned long)estacks;
+        }
+
+        t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
+        /*
+         * <= is required because the CPU will access up to
+         * 8 bits beyond the end of the IO permission bitmap.
+         */
+        for (i = 0; i <= IO_BITMAP_LONGS; i++)
+                t->io_bitmap[i] = ~0UL;
+
+        atomic_inc(&init_mm.mm_count);
+        me->active_mm = &init_mm;
+        if (me->mm)
+                BUG();
+        enter_lazy_tlb(&init_mm, me);
+
+        load_sp0(t, &current->thread);
+        set_tss_desc(cpu, t);
+        load_TR_desc();
+        load_LDT(&init_mm.context);
+
+#ifdef CONFIG_KGDB
+        /*
+         * If the kgdb is connected no debug regs should be altered.  This
+         * is only applicable when KGDB and a KGDB I/O module are built
+         * into the kernel and you are using early debugging with
+         * kgdbwait. KGDB will control the kernel HW breakpoint registers.
+         */
+        if (kgdb_connected && arch_kgdb_ops.correct_hw_break)
+                arch_kgdb_ops.correct_hw_break();
+        else {
+#endif
+        /*
+         * Clear all 6 debug registers:
+         */
+
+        set_debugreg(0UL, 0);
+        set_debugreg(0UL, 1);
+        set_debugreg(0UL, 2);
+        set_debugreg(0UL, 3);
+        set_debugreg(0UL, 6);
+        set_debugreg(0UL, 7);
+#ifdef CONFIG_KGDB
+        /* If the kgdb is connected no debug regs should be altered. */
+        }
+#endif
+
+        fpu_init();
+
+        raw_local_save_flags(kernel_eflags);
+
+        if (is_uv_system())
+                uv_cpu_init();
+}
diff --git a/arch/x86/kernel/cpu/cpu.h b/arch/x86/kernel/cpu/cpu.h
index 783691b2a738..4d894e8565fe 100644
--- a/arch/x86/kernel/cpu/cpu.h
+++ b/arch/x86/kernel/cpu/cpu.h
@@ -1,3 +1,6 @@
+#ifndef ARCH_X86_CPU_H
+
+#define ARCH_X86_CPU_H
 
 struct cpu_model_info {
         int vendor;
@@ -36,3 +39,5 @@ extern struct cpu_vendor_dev __x86cpuvendor_start[], __x86cpuvendor_end[];
 
 extern int get_model_name(struct cpuinfo_x86 *c);
 extern void display_cacheinfo(struct cpuinfo_x86 *c);
+
+#endif
diff --git a/arch/x86/kernel/cpu/cpufreq/cpufreq-nforce2.c b/arch/x86/kernel/cpu/cpufreq/cpufreq-nforce2.c
index f03e9153618e..965ea52767ac 100644
--- a/arch/x86/kernel/cpu/cpufreq/cpufreq-nforce2.c
+++ b/arch/x86/kernel/cpu/cpufreq/cpufreq-nforce2.c
@@ -26,9 +26,10 @@
 #define NFORCE2_SAFE_DISTANCE 50
 
 /* Delay in ms between FSB changes */
-//#define NFORCE2_DELAY 10
+/* #define NFORCE2_DELAY 10 */
 
-/* nforce2_chipset:
+/*
+ * nforce2_chipset:
  * FSB is changed using the chipset
  */
 static struct pci_dev *nforce2_chipset_dev;
@@ -36,13 +37,13 @@ static struct pci_dev *nforce2_chipset_dev;
 /* fid:
  * multiplier * 10
  */
-static int fid = 0;
+static int fid;
 
 /* min_fsb, max_fsb:
  * minimum and maximum FSB (= FSB at boot time)
  */
-static int min_fsb = 0;
-static int max_fsb = 0;
+static int min_fsb;
+static int max_fsb;
 
 MODULE_AUTHOR("Sebastian Witt <se.witt@gmx.net>");
 MODULE_DESCRIPTION("nForce2 FSB changing cpufreq driver");
@@ -53,7 +54,7 @@ module_param(min_fsb, int, 0444);
 
 MODULE_PARM_DESC(fid, "CPU multiplier to use (11.5 = 115)");
 MODULE_PARM_DESC(min_fsb,
-                 "Minimum FSB to use, if not defined: current FSB - 50");
+                "Minimum FSB to use, if not defined: current FSB - 50");
 
 #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "cpufreq-nforce2", msg)
 
@@ -139,7 +140,7 @@ static unsigned int nforce2_fsb_read(int bootfsb)
 
         /* Get chipset boot FSB from subdevice 5 (FSB at boot-time) */
         nforce2_sub5 = pci_get_subsys(PCI_VENDOR_ID_NVIDIA,
-                                                0x01EF,PCI_ANY_ID,PCI_ANY_ID,NULL);
+                                                0x01EF, PCI_ANY_ID, PCI_ANY_ID, NULL);
         if (!nforce2_sub5)
                 return 0;
 
@@ -147,13 +148,13 @@ static unsigned int nforce2_fsb_read(int bootfsb)
         fsb /= 1000000;
 
         /* Check if PLL register is already set */
-        pci_read_config_byte(nforce2_chipset_dev,NFORCE2_PLLENABLE, (u8 *)&temp);
+        pci_read_config_byte(nforce2_chipset_dev, NFORCE2_PLLENABLE, (u8 *)&temp);
 
-        if(bootfsb || !temp)
+        if (bootfsb || !temp)
                 return fsb;
-                
+
         /* Use PLL register FSB value */
-        pci_read_config_dword(nforce2_chipset_dev,NFORCE2_PLLREG, &temp);
+        pci_read_config_dword(nforce2_chipset_dev, NFORCE2_PLLREG, &temp);
         fsb = nforce2_calc_fsb(temp);
 
         return fsb;
@@ -184,7 +185,7 @@ static int nforce2_set_fsb(unsigned int fsb)
         }
 
         /* First write? Then set actual value */
-        pci_read_config_byte(nforce2_chipset_dev,NFORCE2_PLLENABLE, (u8 *)&temp);
+        pci_read_config_byte(nforce2_chipset_dev, NFORCE2_PLLENABLE, (u8 *)&temp);
         if (!temp) {
                 pll = nforce2_calc_pll(tfsb);
 
@@ -210,7 +211,8 @@ static int nforce2_set_fsb(unsigned int fsb)
                         tfsb--;
 
                 /* Calculate the PLL reg. value */
-                if ((pll = nforce2_calc_pll(tfsb)) == -1)
+                pll = nforce2_calc_pll(tfsb);
+                if (pll == -1)
                         return -EINVAL;
 
                 nforce2_write_pll(pll);
@@ -249,7 +251,7 @@ static unsigned int nforce2_get(unsigned int cpu)
 static int nforce2_target(struct cpufreq_policy *policy,
                           unsigned int target_freq, unsigned int relation)
 {
-//        unsigned long         flags;
+/*        unsigned long         flags; */
         struct cpufreq_freqs freqs;
         unsigned int target_fsb;
 
@@ -271,17 +273,17 @@ static int nforce2_target(struct cpufreq_policy *policy,
         cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
 
         /* Disable IRQs */
-        //local_irq_save(flags);
+        /* local_irq_save(flags); */
 
         if (nforce2_set_fsb(target_fsb) < 0)
                 printk(KERN_ERR "cpufreq: Changing FSB to %d failed\n",
-                       target_fsb);
+                        target_fsb);
         else
                 dprintk("Changed FSB successfully to %d\n",
-                       target_fsb);
+                        target_fsb);
 
         /* Enable IRQs */
-        //local_irq_restore(flags);
+        /* local_irq_restore(flags); */
 
         cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
 
@@ -302,8 +304,8 @@ static int nforce2_verify(struct cpufreq_policy *policy)
                 policy->max = (fsb_pol_max + 1) * fid * 100;
 
         cpufreq_verify_within_limits(policy,
-                                     policy->cpuinfo.min_freq,
-                                     policy->cpuinfo.max_freq);
+                                     policy->cpuinfo.min_freq,
+                                     policy->cpuinfo.max_freq);
         return 0;
 }
 
@@ -347,7 +349,7 @@ static int nforce2_cpu_init(struct cpufreq_policy *policy)
         /* Set maximum FSB to FSB at boot time */
         max_fsb = nforce2_fsb_read(1);
 
-        if(!max_fsb)
+        if (!max_fsb)
                 return -EIO;
 
         if (!min_fsb)
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index fe9224c51d37..70609efdf1da 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -226,6 +226,10 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
 
         if (cpu_has_bts)
                 ds_init_intel(c);
+
+#ifdef CONFIG_X86_NUMAQ
+        numaq_tsc_disable();
+#endif
 }
 
 static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
diff --git a/arch/x86/kernel/cpu/intel_64.c b/arch/x86/kernel/cpu/intel_64.c
new file mode 100644
index 000000000000..1019c58d39f0
--- /dev/null
+++ b/arch/x86/kernel/cpu/intel_64.c
@@ -0,0 +1,95 @@
+#include <linux/init.h>
+#include <linux/smp.h>
+#include <asm/processor.h>
+#include <asm/ptrace.h>
+#include <asm/topology.h>
+#include <asm/numa_64.h>
+
+#include "cpu.h"
+
+static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
+{
+        if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
+            (c->x86 == 0x6 && c->x86_model >= 0x0e))
+                set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
+
+        set_cpu_cap(c, X86_FEATURE_SYSENTER32);
+}
+
+/*
+ * find out the number of processor cores on the die
+ */
+static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
+{
+        unsigned int eax, t;
+
+        if (c->cpuid_level < 4)
+                return 1;
+
+        cpuid_count(4, 0, &eax, &t, &t, &t);
+
+        if (eax & 0x1f)
+                return ((eax >> 26) + 1);
+        else
+                return 1;
+}
+
+static void __cpuinit srat_detect_node(void)
+{
+#ifdef CONFIG_NUMA
+        unsigned node;
+        int cpu = smp_processor_id();
+        int apicid = hard_smp_processor_id();
+
+        /* Don't do the funky fallback heuristics the AMD version employs
+           for now. */
+        node = apicid_to_node[apicid];
+        if (node == NUMA_NO_NODE || !node_online(node))
+                node = first_node(node_online_map);
+        numa_set_node(cpu, node);
+
+        printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
+#endif
+}
+
+static void __cpuinit init_intel(struct cpuinfo_x86 *c)
+{
+        init_intel_cacheinfo(c);
+        if (c->cpuid_level > 9) {
+                unsigned eax = cpuid_eax(10);
+                /* Check for version and the number of counters */
+                if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
+                        set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
+        }
+
+        if (cpu_has_ds) {
+                unsigned int l1, l2;
+                rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
+                if (!(l1 & (1<<11)))
+                        set_cpu_cap(c, X86_FEATURE_BTS);
+                if (!(l1 & (1<<12)))
+                        set_cpu_cap(c, X86_FEATURE_PEBS);
+        }
+
+
+        if (cpu_has_bts)
+                ds_init_intel(c);
+
+        if (c->x86 == 15)
+                c->x86_cache_alignment = c->x86_clflush_size * 2;
+        if (c->x86 == 6)
+                set_cpu_cap(c, X86_FEATURE_REP_GOOD);
+        set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
+        c->x86_max_cores = intel_num_cpu_cores(c);
+
+        srat_detect_node();
+}
+
+static struct cpu_dev intel_cpu_dev __cpuinitdata = {
+        .c_vendor       = "Intel",
+        .c_ident        = { "GenuineIntel" },
+        .c_early_init   = early_init_intel,
+        .c_init         = init_intel,
+};
+cpu_vendor_dev_register(X86_VENDOR_INTEL, &intel_cpu_dev);
+
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 26d615dcb149..2c8afafa18e8 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -62,6 +62,7 @@ static struct _cache_table cache_table[] __cpuinitdata =
         { 0x4b, LVL_3,      8192 },     /* 16-way set assoc, 64 byte line size */
         { 0x4c, LVL_3,     12288 },     /* 12-way set assoc, 64 byte line size */
         { 0x4d, LVL_3,     16384 },     /* 16-way set assoc, 64 byte line size */
+        { 0x4e, LVL_2,      6144 },     /* 24-way set assoc, 64 byte line size */
         { 0x60, LVL_1_DATA, 16 },       /* 8-way set assoc, sectored cache, 64 byte line size */
         { 0x66, LVL_1_DATA, 8 },        /* 4-way set assoc, sectored cache, 64 byte line size */
         { 0x67, LVL_1_DATA, 16 },       /* 4-way set assoc, sectored cache, 64 byte line size */
diff --git a/arch/x86/kernel/cpu/mcheck/k7.c b/arch/x86/kernel/cpu/mcheck/k7.c
index e633c9c2b764..f390c9f66351 100644
--- a/arch/x86/kernel/cpu/mcheck/k7.c
+++ b/arch/x86/kernel/cpu/mcheck/k7.c
@@ -9,23 +9,23 @@
 #include <linux/interrupt.h>
 #include <linux/smp.h>
 
-#include <asm/processor.h> 
+#include <asm/processor.h>
 #include <asm/system.h>
 #include <asm/msr.h>
 
 #include "mce.h"
 
 /* Machine Check Handler For AMD Athlon/Duron */
-static void k7_machine_check(struct pt_regs * regs, long error_code)
+static void k7_machine_check(struct pt_regs *regs, long error_code)
 {
-        int recover=1;
+        int recover = 1;
         u32 alow, ahigh, high, low;
         u32 mcgstl, mcgsth;
         int i;
 
-        rdmsr (MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
+        rdmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
         if (mcgstl & (1<<0))    /* Recoverable ? */
-                recover=0;
+                recover = 0;
 
         printk(KERN_EMERG "CPU %d: Machine Check Exception: %08x%08x\n",
                 smp_processor_id(), mcgsth, mcgstl);
@@ -60,12 +60,12 @@ static void k7_machine_check(struct pt_regs * regs, long error_code)
         }
 
         if (recover&2)
-                panic ("CPU context corrupt");
+                panic("CPU context corrupt");
         if (recover&1)
-                panic ("Unable to continue");
-        printk (KERN_EMERG "Attempting to continue.\n");
+                panic("Unable to continue");
+        printk(KERN_EMERG "Attempting to continue.\n");
         mcgstl &= ~(1<<2);
-        wrmsr (MSR_IA32_MCG_STATUS,mcgstl, mcgsth);
+        wrmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
 }
 
 
@@ -81,25 +81,25 @@ void amd_mcheck_init(struct cpuinfo_x86 *c)
         machine_check_vector = k7_machine_check;
         wmb();
 
-        printk (KERN_INFO "Intel machine check architecture supported.\n");
-        rdmsr (MSR_IA32_MCG_CAP, l, h);
+        printk(KERN_INFO "Intel machine check architecture supported.\n");
+        rdmsr(MSR_IA32_MCG_CAP, l, h);
         if (l & (1<<8)) /* Control register present ? */
-                wrmsr (MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
+                wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
         nr_mce_banks = l & 0xff;
 
         /* Clear status for MC index 0 separately, we don't touch CTL,
          * as some K7 Athlons cause spurious MCEs when its enabled. */
         if (boot_cpu_data.x86 == 6) {
-                wrmsr (MSR_IA32_MC0_STATUS, 0x0, 0x0);
+                wrmsr(MSR_IA32_MC0_STATUS, 0x0, 0x0);
                 i = 1;
         } else
                 i = 0;
-        for (; i<nr_mce_banks; i++) {
-                wrmsr (MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff);
-                wrmsr (MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0);
+        for (; i < nr_mce_banks; i++) {
+                wrmsr(MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff);
+                wrmsr(MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0);
         }
 
-        set_in_cr4 (X86_CR4_MCE);
-        printk (KERN_INFO "Intel machine check reporting enabled on CPU#%d.\n",
+        set_in_cr4(X86_CR4_MCE);
+        printk(KERN_INFO "Intel machine check reporting enabled on CPU#%d.\n",
                 smp_processor_id());
 }
diff --git a/arch/x86/kernel/cpu/mcheck/mce_64.c b/arch/x86/kernel/cpu/mcheck/mce_64.c
index e07e8c068ae0..987410745182 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_64.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_64.c
@@ -9,6 +9,7 @@
 #include <linux/types.h>
 #include <linux/kernel.h>
 #include <linux/sched.h>
+#include <linux/smp_lock.h>
 #include <linux/string.h>
 #include <linux/rcupdate.h>
 #include <linux/kallsyms.h>
@@ -31,7 +32,7 @@
 #include <asm/idle.h>
 
 #define MISC_MCELOG_MINOR 227
-#define NR_BANKS 6
+#define NR_SYSFS_BANKS 6
 
 atomic_t mce_entry;
 
@@ -46,7 +47,7 @@ static int mce_dont_init;
  */
 static int tolerant = 1;
 static int banks;
-static unsigned long bank[NR_BANKS] = { [0 ... NR_BANKS-1] = ~0UL };
+static unsigned long bank[NR_SYSFS_BANKS] = { [0 ... NR_SYSFS_BANKS-1] = ~0UL };
 static unsigned long notify_user;
 static int rip_msr;
 static int mce_bootlog = -1;
@@ -209,7 +210,7 @@ void do_machine_check(struct pt_regs * regs, long error_code)
         barrier();
 
         for (i = 0; i < banks; i++) {
-                if (!bank[i])
+                if (i < NR_SYSFS_BANKS && !bank[i])
                         continue;
 
                 m.misc = 0;
@@ -444,9 +445,10 @@ static void mce_init(void *dummy)
 
         rdmsrl(MSR_IA32_MCG_CAP, cap);
         banks = cap & 0xff;
-        if (banks > NR_BANKS) {
-                printk(KERN_INFO "MCE: warning: using only %d banks\n", banks);
-                banks = NR_BANKS;
+        if (banks > MCE_EXTENDED_BANK) {
+                banks = MCE_EXTENDED_BANK;
+                printk(KERN_INFO "MCE: warning: using only %d banks\n",
+                       MCE_EXTENDED_BANK);
         }
         /* Use accurate RIP reporting if available. */
         if ((cap & (1<<9)) && ((cap >> 16) & 0xff) >= 9)
@@ -462,7 +464,11 @@ static void mce_init(void *dummy)
                 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
 
         for (i = 0; i < banks; i++) {
-                wrmsrl(MSR_IA32_MC0_CTL+4*i, bank[i]);
+                if (i < NR_SYSFS_BANKS)
+                        wrmsrl(MSR_IA32_MC0_CTL+4*i, bank[i]);
+                else
+                        wrmsrl(MSR_IA32_MC0_CTL+4*i, ~0UL);
+
                 wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0);
         }
 }
@@ -527,10 +533,12 @@ static int open_exclu;	/* already open exclusive? */
 
 static int mce_open(struct inode *inode, struct file *file)
 {
+        lock_kernel();
         spin_lock(&mce_state_lock);
 
         if (open_exclu || (open_count && (file->f_flags & O_EXCL))) {
                 spin_unlock(&mce_state_lock);
+                unlock_kernel();
                 return -EBUSY;
         }
 
@@ -539,6 +547,7 @@ static int mce_open(struct inode *inode, struct file *file)
         open_count++;
 
         spin_unlock(&mce_state_lock);
+        unlock_kernel();
 
         return nonseekable_open(inode, file);
 }
@@ -766,7 +775,10 @@ DEFINE_PER_CPU(struct sys_device, device_mce);
         }                                                               \
         static SYSDEV_ATTR(name, 0644, show_ ## name, set_ ## name);
 
-/* TBD should generate these dynamically based on number of available banks */
+/*
+ * TBD should generate these dynamically based on number of available banks.
+ * Have only 6 contol banks in /sysfs until then.
+ */
 ACCESSOR(bank0ctl,bank[0],mce_restart())
 ACCESSOR(bank1ctl,bank[1],mce_restart())
 ACCESSOR(bank2ctl,bank[2],mce_restart())
diff --git a/arch/x86/kernel/cpu/mcheck/p4.c b/arch/x86/kernel/cpu/mcheck/p4.c
index cb03345554a5..eef001ad3bde 100644
--- a/arch/x86/kernel/cpu/mcheck/p4.c
+++ b/arch/x86/kernel/cpu/mcheck/p4.c
@@ -8,7 +8,7 @@
 #include <linux/interrupt.h>
 #include <linux/smp.h>
 
-#include <asm/processor.h> 
+#include <asm/processor.h>
 #include <asm/system.h>
 #include <asm/msr.h>
 #include <asm/apic.h>
@@ -32,12 +32,12 @@ struct intel_mce_extended_msrs {
         /* u32 *reserved[]; */
 };
 
-static int mce_num_extended_msrs = 0;
+static int mce_num_extended_msrs;
 
 
 #ifdef CONFIG_X86_MCE_P4THERMAL
 static void unexpected_thermal_interrupt(struct pt_regs *regs)
-{       
+{
         printk(KERN_ERR "CPU%d: Unexpected LVT TMR interrupt!\n",
                         smp_processor_id());
         add_taint(TAINT_MACHINE_CHECK);
@@ -83,7 +83,7 @@ static void intel_init_thermal(struct cpuinfo_x86 *c)
          * be some SMM goo which handles it, so we can't even put a handler
          * since it might be delivered via SMI already -zwanem.
          */
-        rdmsr (MSR_IA32_MISC_ENABLE, l, h);
+        rdmsr(MSR_IA32_MISC_ENABLE, l, h);
         h = apic_read(APIC_LVTTHMR);
         if ((l & (1<<3)) && (h & APIC_DM_SMI)) {
                 printk(KERN_DEBUG "CPU%d: Thermal monitoring handled by SMI\n",
@@ -91,7 +91,7 @@ static void intel_init_thermal(struct cpuinfo_x86 *c)
                 return; /* -EBUSY */
         }
 
-        /* check whether a vector already exists, temporarily masked? */        
+        /* check whether a vector already exists, temporarily masked? */
         if (h & APIC_VECTOR_MASK) {
                 printk(KERN_DEBUG "CPU%d: Thermal LVT vector (%#x) already "
                                 "installed\n",
@@ -104,18 +104,18 @@ static void intel_init_thermal(struct cpuinfo_x86 *c)
         h |= (APIC_DM_FIXED | APIC_LVT_MASKED); /* we'll mask till we're ready */
         apic_write_around(APIC_LVTTHMR, h);
 
-        rdmsr (MSR_IA32_THERM_INTERRUPT, l, h);
-        wrmsr (MSR_IA32_THERM_INTERRUPT, l | 0x03 , h);
+        rdmsr(MSR_IA32_THERM_INTERRUPT, l, h);
+        wrmsr(MSR_IA32_THERM_INTERRUPT, l | 0x03 , h);
 
         /* ok we're good to go... */
         vendor_thermal_interrupt = intel_thermal_interrupt;
-        
-        rdmsr (MSR_IA32_MISC_ENABLE, l, h);
-        wrmsr (MSR_IA32_MISC_ENABLE, l | (1<<3), h);
 
-        l = apic_read (APIC_LVTTHMR);
-        apic_write_around (APIC_LVTTHMR, l & ~APIC_LVT_MASKED);
-        printk (KERN_INFO "CPU%d: Thermal monitoring enabled\n", cpu);
+        rdmsr(MSR_IA32_MISC_ENABLE, l, h);
+        wrmsr(MSR_IA32_MISC_ENABLE, l | (1<<3), h);
+
+        l = apic_read(APIC_LVTTHMR);
+        apic_write_around(APIC_LVTTHMR, l & ~APIC_LVT_MASKED);
+        printk(KERN_INFO "CPU%d: Thermal monitoring enabled\n", cpu);
 
         /* enable thermal throttle processing */
         atomic_set(&therm_throt_en, 1);
@@ -129,28 +129,28 @@ static inline void intel_get_extended_msrs(struct intel_mce_extended_msrs *r)
 {
         u32 h;
 
-        rdmsr (MSR_IA32_MCG_EAX, r->eax, h);
-        rdmsr (MSR_IA32_MCG_EBX, r->ebx, h);
-        rdmsr (MSR_IA32_MCG_ECX, r->ecx, h);
-        rdmsr (MSR_IA32_MCG_EDX, r->edx, h);
-        rdmsr (MSR_IA32_MCG_ESI, r->esi, h);
-        rdmsr (MSR_IA32_MCG_EDI, r->edi, h);
-        rdmsr (MSR_IA32_MCG_EBP, r->ebp, h);
-        rdmsr (MSR_IA32_MCG_ESP, r->esp, h);
-        rdmsr (MSR_IA32_MCG_EFLAGS, r->eflags, h);
-        rdmsr (MSR_IA32_MCG_EIP, r->eip, h);
+        rdmsr(MSR_IA32_MCG_EAX, r->eax, h);
+        rdmsr(MSR_IA32_MCG_EBX, r->ebx, h);
+        rdmsr(MSR_IA32_MCG_ECX, r->ecx, h);
+        rdmsr(MSR_IA32_MCG_EDX, r->edx, h);
+        rdmsr(MSR_IA32_MCG_ESI, r->esi, h);
+        rdmsr(MSR_IA32_MCG_EDI, r->edi, h);
+        rdmsr(MSR_IA32_MCG_EBP, r->ebp, h);
+        rdmsr(MSR_IA32_MCG_ESP, r->esp, h);
+        rdmsr(MSR_IA32_MCG_EFLAGS, r->eflags, h);
+        rdmsr(MSR_IA32_MCG_EIP, r->eip, h);
 }
 
-static void intel_machine_check(struct pt_regs * regs, long error_code)
+static void intel_machine_check(struct pt_regs *regs, long error_code)
 {
-        int recover=1;
+        int recover = 1;
         u32 alow, ahigh, high, low;
         u32 mcgstl, mcgsth;
         int i;
 
-        rdmsr (MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
+        rdmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
         if (mcgstl & (1<<0))    /* Recoverable ? */
-                recover=0;
+                recover = 0;
 
         printk(KERN_EMERG "CPU %d: Machine Check Exception: %08x%08x\n",
                 smp_processor_id(), mcgsth, mcgstl);
@@ -191,20 +191,20 @@ static void intel_machine_check(struct pt_regs * regs, long error_code)
         }
 
         if (recover & 2)
-                panic ("CPU context corrupt");
+                panic("CPU context corrupt");
         if (recover & 1)
-                panic ("Unable to continue");
+                panic("Unable to continue");
 
         printk(KERN_EMERG "Attempting to continue.\n");
-        /* 
-         * Do not clear the MSR_IA32_MCi_STATUS if the error is not 
+        /*
+         * Do not clear the MSR_IA32_MCi_STATUS if the error is not
          * recoverable/continuable.This will allow BIOS to look at the MSRs
          * for errors if the OS could not log the error.
          */
-        for (i=0; i<nr_mce_banks; i++) {
+        for (i = 0; i < nr_mce_banks; i++) {
                 u32 msr;
                 msr = MSR_IA32_MC0_STATUS+i*4;
-                rdmsr (msr, low, high);
+                rdmsr(msr, low, high);
                 if (high&(1<<31)) {
                         /* Clear it */
                         wrmsr(msr, 0UL, 0UL);
@@ -214,7 +214,7 @@ static void intel_machine_check(struct pt_regs * regs, long error_code)
                 }
         }
         mcgstl &= ~(1<<2);
-        wrmsr (MSR_IA32_MCG_STATUS,mcgstl, mcgsth);
+        wrmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
 }
 
 
@@ -222,30 +222,30 @@ void intel_p4_mcheck_init(struct cpuinfo_x86 *c)
 {
         u32 l, h;
         int i;
-        
+
         machine_check_vector = intel_machine_check;
         wmb();
 
-        printk (KERN_INFO "Intel machine check architecture supported.\n");
-        rdmsr (MSR_IA32_MCG_CAP, l, h);
+        printk(KERN_INFO "Intel machine check architecture supported.\n");
+        rdmsr(MSR_IA32_MCG_CAP, l, h);
         if (l & (1<<8)) /* Control register present ? */
-                wrmsr (MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
+                wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
         nr_mce_banks = l & 0xff;
 
-        for (i=0; i<nr_mce_banks; i++) {
-                wrmsr (MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff);
-                wrmsr (MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0);
+        for (i = 0; i < nr_mce_banks; i++) {
+                wrmsr(MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff);
+                wrmsr(MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0);
         }
 
-        set_in_cr4 (X86_CR4_MCE);
-        printk (KERN_INFO "Intel machine check reporting enabled on CPU#%d.\n",
+        set_in_cr4(X86_CR4_MCE);
+        printk(KERN_INFO "Intel machine check reporting enabled on CPU#%d.\n",
                 smp_processor_id());
 
         /* Check for P4/Xeon extended MCE MSRs */
-        rdmsr (MSR_IA32_MCG_CAP, l, h);
+        rdmsr(MSR_IA32_MCG_CAP, l, h);
         if (l & (1<<9)) {/* MCG_EXT_P */
                 mce_num_extended_msrs = (l >> 16) & 0xff;
-                printk (KERN_INFO "CPU%d: Intel P4/Xeon Extended MCE MSRs (%d)"
+                printk(KERN_INFO "CPU%d: Intel P4/Xeon Extended MCE MSRs (%d)"
                                 " available\n",
                         smp_processor_id(), mce_num_extended_msrs);
 
diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/generic.c
index 5d241ce94a44..509bd3d9eacd 100644
--- a/arch/x86/kernel/cpu/mtrr/generic.c
+++ b/arch/x86/kernel/cpu/mtrr/generic.c
@@ -37,7 +37,7 @@ static struct fixed_range_block fixed_range_blocks[] = {
 static unsigned long smp_changes_mask;
 static struct mtrr_state mtrr_state = {};
 static int mtrr_state_set;
-static u64 tom2;
+u64 mtrr_tom2;
 
 #undef MODULE_PARAM_PREFIX
 #define MODULE_PARAM_PREFIX "mtrr."
@@ -139,8 +139,8 @@ u8 mtrr_type_lookup(u64 start, u64 end)
                 }
         }
 
-        if (tom2) {
-                if (start >= (1ULL<<32) && (end < tom2))
+        if (mtrr_tom2) {
+                if (start >= (1ULL<<32) && (end < mtrr_tom2))
                         return MTRR_TYPE_WRBACK;
         }
 
@@ -158,6 +158,20 @@ get_mtrr_var_range(unsigned int index, struct mtrr_var_range *vr)
         rdmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr->mask_hi);
 }
 
+/*  fill the MSR pair relating to a var range  */
+void fill_mtrr_var_range(unsigned int index,
+                u32 base_lo, u32 base_hi, u32 mask_lo, u32 mask_hi)
+{
+        struct mtrr_var_range *vr;
+
+        vr = mtrr_state.var_ranges;
+
+        vr[index].base_lo = base_lo;
+        vr[index].base_hi = base_hi;
+        vr[index].mask_lo = mask_lo;
+        vr[index].mask_hi = mask_hi;
+}
+
 static void
 get_fixed_ranges(mtrr_type * frs)
 {
@@ -213,13 +227,13 @@ void __init get_mtrr_state(void)
         mtrr_state.enabled = (lo & 0xc00) >> 10;
 
         if (amd_special_default_mtrr()) {
-                unsigned lo, hi;
+                unsigned low, high;
                 /* TOP_MEM2 */
-                rdmsr(MSR_K8_TOP_MEM2, lo, hi);
-                tom2 = hi;
-                tom2 <<= 32;
-                tom2 |= lo;
-                tom2 &= 0xffffff8000000ULL;
+                rdmsr(MSR_K8_TOP_MEM2, low, high);
+                mtrr_tom2 = high;
+                mtrr_tom2 <<= 32;
+                mtrr_tom2 |= low;
+                mtrr_tom2 &= 0xffffff800000ULL;
         }
         if (mtrr_show) {
                 int high_width;
@@ -251,9 +265,9 @@ void __init get_mtrr_state(void)
                         else
                                 printk(KERN_INFO "MTRR %u disabled\n", i);
                 }
-                if (tom2) {
+                if (mtrr_tom2) {
                         printk(KERN_INFO "TOM2: %016llx aka %lldM\n",
-                                          tom2, tom2>>20);
+                                          mtrr_tom2, mtrr_tom2>>20);
                 }
         }
         mtrr_state_set = 1;
@@ -328,7 +342,7 @@ static void set_fixed_range(int msr, bool *changed, unsigned int *msrwords)
 
         if (lo != msrwords[0] || hi != msrwords[1]) {
                 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
-                    boot_cpu_data.x86 == 15 &&
+                    (boot_cpu_data.x86 >= 0x0f && boot_cpu_data.x86 <= 0x11) &&
                     ((msrwords[0] | msrwords[1]) & K8_MTRR_RDMEM_WRMEM_MASK))
                         k8_enable_fixed_iorrs();
                 mtrr_wrmsr(msr, msrwords[0], msrwords[1]);
diff --git a/arch/x86/kernel/cpu/mtrr/main.c b/arch/x86/kernel/cpu/mtrr/main.c
index 6a1e278d9323..105afe12beb0 100644
--- a/arch/x86/kernel/cpu/mtrr/main.c
+++ b/arch/x86/kernel/cpu/mtrr/main.c
@@ -37,6 +37,7 @@
 #include <linux/smp.h>
 #include <linux/cpu.h>
 #include <linux/mutex.h>
+#include <linux/sort.h>
 
 #include <asm/e820.h>
 #include <asm/mtrr.h>
@@ -609,6 +610,787 @@ static struct sysdev_driver mtrr_sysdev_driver = {
         .resume         = mtrr_restore,
 };
 
+/* should be related to MTRR_VAR_RANGES nums */
+#define RANGE_NUM 256
+
+struct res_range {
+        unsigned long start;
+        unsigned long end;
+};
+
+static int __init
+add_range(struct res_range *range, int nr_range, unsigned long start,
+                              unsigned long end)
+{
+        /* out of slots */
+        if (nr_range >= RANGE_NUM)
+                return nr_range;
+
+        range[nr_range].start = start;
+        range[nr_range].end = end;
+
+        nr_range++;
+
+        return nr_range;
+}
+
+static int __init
+add_range_with_merge(struct res_range *range, int nr_range, unsigned long start,
+                              unsigned long end)
+{
+        int i;
+
+        /* try to merge it with old one */
+        for (i = 0; i < nr_range; i++) {
+                unsigned long final_start, final_end;
+                unsigned long common_start, common_end;
+
+                if (!range[i].end)
+                        continue;
+
+                common_start = max(range[i].start, start);
+                common_end = min(range[i].end, end);
+                if (common_start > common_end + 1)
+                        continue;
+
+                final_start = min(range[i].start, start);
+                final_end = max(range[i].end, end);
+
+                range[i].start = final_start;
+                range[i].end =  final_end;
+                return nr_range;
+        }
+
+        /* need to add that */
+        return add_range(range, nr_range, start, end);
+}
+
+static void __init
+subtract_range(struct res_range *range, unsigned long start, unsigned long end)
+{
+        int i, j;
+
+        for (j = 0; j < RANGE_NUM; j++) {
+                if (!range[j].end)
+                        continue;
+
+                if (start <= range[j].start && end >= range[j].end) {
+                        range[j].start = 0;
+                        range[j].end = 0;
+                        continue;
+                }
+
+                if (start <= range[j].start && end < range[j].end &&
+                    range[j].start < end + 1) {
+                        range[j].start = end + 1;
+                        continue;
+                }
+
+
+                if (start > range[j].start && end >= range[j].end &&
+                    range[j].end > start - 1) {
+                        range[j].end = start - 1;
+                        continue;
+                }
+
+                if (start > range[j].start && end < range[j].end) {
+                        /* find the new spare */
+                        for (i = 0; i < RANGE_NUM; i++) {
+                                if (range[i].end == 0)
+                                        break;
+                        }
+                        if (i < RANGE_NUM) {
+                                range[i].end = range[j].end;
+                                range[i].start = end + 1;
+                        } else {
+                                printk(KERN_ERR "run of slot in ranges\n");
+                        }
+                        range[j].end = start - 1;
+                        continue;
+                }
+        }
+}
+
+static int __init cmp_range(const void *x1, const void *x2)
+{
+        const struct res_range *r1 = x1;
+        const struct res_range *r2 = x2;
+        long start1, start2;
+
+        start1 = r1->start;
+        start2 = r2->start;
+
+        return start1 - start2;
+}
+
+struct var_mtrr_range_state {
+        unsigned long base_pfn;
+        unsigned long size_pfn;
+        mtrr_type type;
+};
+
+struct var_mtrr_range_state __initdata range_state[RANGE_NUM];
+static int __initdata debug_print;
+
+static int __init
+x86_get_mtrr_mem_range(struct res_range *range, int nr_range,
+                       unsigned long extra_remove_base,
+                       unsigned long extra_remove_size)
+{
+        unsigned long i, base, size;
+        mtrr_type type;
+
+        for (i = 0; i < num_var_ranges; i++) {
+                type = range_state[i].type;
+                if (type != MTRR_TYPE_WRBACK)
+                        continue;
+                base = range_state[i].base_pfn;
+                size = range_state[i].size_pfn;
+                nr_range = add_range_with_merge(range, nr_range, base,
+                                                base + size - 1);
+        }
+        if (debug_print) {
+                printk(KERN_DEBUG "After WB checking\n");
+                for (i = 0; i < nr_range; i++)
+                        printk(KERN_DEBUG "MTRR MAP PFN: %016lx - %016lx\n",
+                                 range[i].start, range[i].end + 1);
+        }
+
+        /* take out UC ranges */
+        for (i = 0; i < num_var_ranges; i++) {
+                type = range_state[i].type;
+                if (type != MTRR_TYPE_UNCACHABLE)
+                        continue;
+                size = range_state[i].size_pfn;
+                if (!size)
+                        continue;
+                base = range_state[i].base_pfn;
+                subtract_range(range, base, base + size - 1);
+        }
+        if (extra_remove_size)
+                subtract_range(range, extra_remove_base,
+                                 extra_remove_base + extra_remove_size  - 1);
+
+        /* get new range num */
+        nr_range = 0;
+        for (i = 0; i < RANGE_NUM; i++) {
+                if (!range[i].end)
+                        continue;
+                nr_range++;
+        }
+        if  (debug_print) {
+                printk(KERN_DEBUG "After UC checking\n");
+                for (i = 0; i < nr_range; i++)
+                        printk(KERN_DEBUG "MTRR MAP PFN: %016lx - %016lx\n",
+                                 range[i].start, range[i].end + 1);
+        }
+
+        /* sort the ranges */
+        sort(range, nr_range, sizeof(struct res_range), cmp_range, NULL);
+        if  (debug_print) {
+                printk(KERN_DEBUG "After sorting\n");
+                for (i = 0; i < nr_range; i++)
+                        printk(KERN_DEBUG "MTRR MAP PFN: %016lx - %016lx\n",
+                                 range[i].start, range[i].end + 1);
+        }
+
+        /* clear those is not used */
+        for (i = nr_range; i < RANGE_NUM; i++)
+                memset(&range[i], 0, sizeof(range[i]));
+
+        return nr_range;
+}
+
+static struct res_range __initdata range[RANGE_NUM];
+
+#ifdef CONFIG_MTRR_SANITIZER
+
+static unsigned long __init sum_ranges(struct res_range *range, int nr_range)
+{
+        unsigned long sum;
+        int i;
+
+        sum = 0;
+        for (i = 0; i < nr_range; i++)
+                sum += range[i].end + 1 - range[i].start;
+
+        return sum;
+}
+
+static int enable_mtrr_cleanup __initdata =
+        CONFIG_MTRR_SANITIZER_ENABLE_DEFAULT;
+
+static int __init disable_mtrr_cleanup_setup(char *str)
+{
+        if (enable_mtrr_cleanup != -1)
+                enable_mtrr_cleanup = 0;
+        return 0;
+}
+early_param("disable_mtrr_cleanup", disable_mtrr_cleanup_setup);
+
+static int __init enable_mtrr_cleanup_setup(char *str)
+{
+        if (enable_mtrr_cleanup != -1)
+                enable_mtrr_cleanup = 1;
+        return 0;
+}
+early_param("enble_mtrr_cleanup", enable_mtrr_cleanup_setup);
+
+struct var_mtrr_state {
+        unsigned long   range_startk;
+        unsigned long   range_sizek;
+        unsigned long   chunk_sizek;
+        unsigned long   gran_sizek;
+        unsigned int    reg;
+};
+
+static void __init
+set_var_mtrr(unsigned int reg, unsigned long basek, unsigned long sizek,
+                unsigned char type, unsigned int address_bits)
+{
+        u32 base_lo, base_hi, mask_lo, mask_hi;
+        u64 base, mask;
+
+        if (!sizek) {
+                fill_mtrr_var_range(reg, 0, 0, 0, 0);
+                return;
+        }
+
+        mask = (1ULL << address_bits) - 1;
+        mask &= ~((((u64)sizek) << 10) - 1);
+
+        base  = ((u64)basek) << 10;
+
+        base |= type;
+        mask |= 0x800;
+
+        base_lo = base & ((1ULL<<32) - 1);
+        base_hi = base >> 32;
+
+        mask_lo = mask & ((1ULL<<32) - 1);
+        mask_hi = mask >> 32;
+
+        fill_mtrr_var_range(reg, base_lo, base_hi, mask_lo, mask_hi);
+}
+
+static void __init
+save_var_mtrr(unsigned int reg, unsigned long basek, unsigned long sizek,
+                unsigned char type)
+{
+        range_state[reg].base_pfn = basek >> (PAGE_SHIFT - 10);
+        range_state[reg].size_pfn = sizek >> (PAGE_SHIFT - 10);
+        range_state[reg].type = type;
+}
+
+static void __init
+set_var_mtrr_all(unsigned int address_bits)
+{
+        unsigned long basek, sizek;
+        unsigned char type;
+        unsigned int reg;
+
+        for (reg = 0; reg < num_var_ranges; reg++) {
+                basek = range_state[reg].base_pfn << (PAGE_SHIFT - 10);
+                sizek = range_state[reg].size_pfn << (PAGE_SHIFT - 10);
+                type = range_state[reg].type;
+
+                set_var_mtrr(reg, basek, sizek, type, address_bits);
+        }
+}
+
+static unsigned int __init
+range_to_mtrr(unsigned int reg, unsigned long range_startk,
+              unsigned long range_sizek, unsigned char type)
+{
+        if (!range_sizek || (reg >= num_var_ranges))
+                return reg;
+
+        while (range_sizek) {
+                unsigned long max_align, align;
+                unsigned long sizek;
+
+                /* Compute the maximum size I can make a range */
+                if (range_startk)
+                        max_align = ffs(range_startk) - 1;
+                else
+                        max_align = 32;
+                align = fls(range_sizek) - 1;
+                if (align > max_align)
+                        align = max_align;
+
+                sizek = 1 << align;
+                if (debug_print)
+                        printk(KERN_DEBUG "Setting variable MTRR %d, "
+                                "base: %ldMB, range: %ldMB, type %s\n",
+                                reg, range_startk >> 10, sizek >> 10,
+                                (type == MTRR_TYPE_UNCACHABLE)?"UC":
+                                    ((type == MTRR_TYPE_WRBACK)?"WB":"Other")
+                                );
+                save_var_mtrr(reg++, range_startk, sizek, type);
+                range_startk += sizek;
+                range_sizek -= sizek;
+                if (reg >= num_var_ranges)
+                        break;
+        }
+        return reg;
+}
+
+static unsigned __init
+range_to_mtrr_with_hole(struct var_mtrr_state *state, unsigned long basek,
+                        unsigned long sizek)
+{
+        unsigned long hole_basek, hole_sizek;
+        unsigned long second_basek, second_sizek;
+        unsigned long range0_basek, range0_sizek;
+        unsigned long range_basek, range_sizek;
+        unsigned long chunk_sizek;
+        unsigned long gran_sizek;
+
+        hole_basek = 0;
+        hole_sizek = 0;
+        second_basek = 0;
+        second_sizek = 0;
+        chunk_sizek = state->chunk_sizek;
+        gran_sizek = state->gran_sizek;
+
+        /* align with gran size, prevent small block used up MTRRs */
+        range_basek = ALIGN(state->range_startk, gran_sizek);
+        if ((range_basek > basek) && basek)
+                return second_sizek;
+        state->range_sizek -= (range_basek - state->range_startk);
+        range_sizek = ALIGN(state->range_sizek, gran_sizek);
+
+        while (range_sizek > state->range_sizek) {
+                range_sizek -= gran_sizek;
+                if (!range_sizek)
+                        return 0;
+        }
+        state->range_sizek = range_sizek;
+
+        /* try to append some small hole */
+        range0_basek = state->range_startk;
+        range0_sizek = ALIGN(state->range_sizek, chunk_sizek);
+        if (range0_sizek == state->range_sizek) {
+                if (debug_print)
+                        printk(KERN_DEBUG "rangeX: %016lx - %016lx\n",
+                                range0_basek<<10,
+                                (range0_basek + state->range_sizek)<<10);
+                state->reg = range_to_mtrr(state->reg, range0_basek,
+                                state->range_sizek, MTRR_TYPE_WRBACK);
+                return 0;
+        }
+
+        range0_sizek -= chunk_sizek;
+        if (range0_sizek && sizek) {
+            while (range0_basek + range0_sizek > (basek + sizek)) {
+                range0_sizek -= chunk_sizek;
+                if (!range0_sizek)
+                        break;
+            }
+        }
+
+        if (range0_sizek) {
+                if (debug_print)
+                        printk(KERN_DEBUG "range0: %016lx - %016lx\n",
+                                range0_basek<<10,
+                                (range0_basek + range0_sizek)<<10);
+                state->reg = range_to_mtrr(state->reg, range0_basek,
+                                range0_sizek, MTRR_TYPE_WRBACK);
+
+        }
+
+        range_basek = range0_basek + range0_sizek;
+        range_sizek = chunk_sizek;
+
+        if (range_basek + range_sizek > basek &&
+            range_basek + range_sizek <= (basek + sizek)) {
+                /* one hole */
+                second_basek = basek;
+                second_sizek = range_basek + range_sizek - basek;
+        }
+
+        /* if last piece, only could one hole near end */
+        if ((second_basek || !basek) &&
+            range_sizek - (state->range_sizek - range0_sizek) - second_sizek <
+            (chunk_sizek >> 1)) {
+                /*
+                 * one hole in middle (second_sizek is 0) or at end
+                 * (second_sizek is 0 )
+                 */
+                hole_sizek = range_sizek - (state->range_sizek - range0_sizek)
+                                 - second_sizek;
+                hole_basek = range_basek + range_sizek - hole_sizek
+                                 - second_sizek;
+        } else {
+                /* fallback for big hole, or several holes */
+                range_sizek = state->range_sizek - range0_sizek;
+                second_basek = 0;
+                second_sizek = 0;
+        }
+
+        if (debug_print)
+                printk(KERN_DEBUG "range: %016lx - %016lx\n", range_basek<<10,
+                         (range_basek + range_sizek)<<10);
+        state->reg = range_to_mtrr(state->reg, range_basek, range_sizek,
+                                         MTRR_TYPE_WRBACK);
+        if (hole_sizek) {
+                if (debug_print)
+                        printk(KERN_DEBUG "hole: %016lx - %016lx\n",
+                                 hole_basek<<10, (hole_basek + hole_sizek)<<10);
+                state->reg = range_to_mtrr(state->reg, hole_basek, hole_sizek,
+                                                 MTRR_TYPE_UNCACHABLE);
+
+        }
+
+        return second_sizek;
+}
+
+static void __init
+set_var_mtrr_range(struct var_mtrr_state *state, unsigned long base_pfn,
+                   unsigned long size_pfn)
+{
+        unsigned long basek, sizek;
+        unsigned long second_sizek = 0;
+
+        if (state->reg >= num_var_ranges)
+                return;
+
+        basek = base_pfn << (PAGE_SHIFT - 10);
+        sizek = size_pfn << (PAGE_SHIFT - 10);
+
+        /* See if I can merge with the last range */
+        if ((basek <= 1024) ||
+            (state->range_startk + state->range_sizek == basek)) {
+                unsigned long endk = basek + sizek;
+                state->range_sizek = endk - state->range_startk;
+                return;
+        }
+        /* Write the range mtrrs */
+        if (state->range_sizek != 0)
+                second_sizek = range_to_mtrr_with_hole(state, basek, sizek);
+
+        /* Allocate an msr */
+        state->range_startk = basek + second_sizek;
+        state->range_sizek  = sizek - second_sizek;
+}
+
+/* mininum size of mtrr block that can take hole */
+static u64 mtrr_chunk_size __initdata = (256ULL<<20);
+
+static int __init parse_mtrr_chunk_size_opt(char *p)
+{
+        if (!p)
+                return -EINVAL;
+        mtrr_chunk_size = memparse(p, &p);
+        return 0;
+}
+early_param("mtrr_chunk_size", parse_mtrr_chunk_size_opt);
+
+/* granity of mtrr of block */
+static u64 mtrr_gran_size __initdata;
+
+static int __init parse_mtrr_gran_size_opt(char *p)
+{
+        if (!p)
+                return -EINVAL;
+        mtrr_gran_size = memparse(p, &p);
+        return 0;
+}
+early_param("mtrr_gran_size", parse_mtrr_gran_size_opt);
+
+static int nr_mtrr_spare_reg __initdata =
+                                 CONFIG_MTRR_SANITIZER_SPARE_REG_NR_DEFAULT;
+
+static int __init parse_mtrr_spare_reg(char *arg)
+{
+        if (arg)
+                nr_mtrr_spare_reg = simple_strtoul(arg, NULL, 0);
+        return 0;
+}
+
+early_param("mtrr_spare_reg_nr", parse_mtrr_spare_reg);
+
+static int __init
+x86_setup_var_mtrrs(struct res_range *range, int nr_range,
+                    u64 chunk_size, u64 gran_size)
+{
+        struct var_mtrr_state var_state;
+        int i;
+        int num_reg;
+
+        var_state.range_startk  = 0;
+        var_state.range_sizek   = 0;
+        var_state.reg           = 0;
+        var_state.chunk_sizek   = chunk_size >> 10;
+        var_state.gran_sizek    = gran_size >> 10;
+
+        memset(range_state, 0, sizeof(range_state));
+
+        /* Write the range etc */
+        for (i = 0; i < nr_range; i++)
+                set_var_mtrr_range(&var_state, range[i].start,
+                                   range[i].end - range[i].start + 1);
+
+        /* Write the last range */
+        if (var_state.range_sizek != 0)
+                range_to_mtrr_with_hole(&var_state, 0, 0);
+
+        num_reg = var_state.reg;
+        /* Clear out the extra MTRR's */
+        while (var_state.reg < num_var_ranges) {
+                save_var_mtrr(var_state.reg, 0, 0, 0);
+                var_state.reg++;
+        }
+
+        return num_reg;
+}
+
+struct mtrr_cleanup_result {
+        unsigned long gran_sizek;
+        unsigned long chunk_sizek;
+        unsigned long lose_cover_sizek;
+        unsigned int num_reg;
+        int bad;
+};
+
+/*
+ * gran_size: 1M, 2M, ..., 2G
+ * chunk size: gran_size, ..., 4G
+ * so we need (2+13)*6
+ */
+#define NUM_RESULT      90
+#define PSHIFT          (PAGE_SHIFT - 10)
+
+static struct mtrr_cleanup_result __initdata result[NUM_RESULT];
+static struct res_range __initdata range_new[RANGE_NUM];
+static unsigned long __initdata min_loss_pfn[RANGE_NUM];
+
+static int __init mtrr_cleanup(unsigned address_bits)
+{
+        unsigned long extra_remove_base, extra_remove_size;
+        unsigned long i, base, size, def, dummy;
+        mtrr_type type;
+        int nr_range, nr_range_new;
+        u64 chunk_size, gran_size;
+        unsigned long range_sums, range_sums_new;
+        int index_good;
+        int num_reg_good;
+
+        /* extra one for all 0 */
+        int num[MTRR_NUM_TYPES + 1];
+
+        if (!is_cpu(INTEL) || enable_mtrr_cleanup < 1)
+                return 0;
+        rdmsr(MTRRdefType_MSR, def, dummy);
+        def &= 0xff;
+        if (def != MTRR_TYPE_UNCACHABLE)
+                return 0;
+
+        /* get it and store it aside */
+        memset(range_state, 0, sizeof(range_state));
+        for (i = 0; i < num_var_ranges; i++) {
+                mtrr_if->get(i, &base, &size, &type);
+                range_state[i].base_pfn = base;
+                range_state[i].size_pfn = size;
+                range_state[i].type = type;
+        }
+
+        /* check entries number */
+        memset(num, 0, sizeof(num));
+        for (i = 0; i < num_var_ranges; i++) {
+                type = range_state[i].type;
+                size = range_state[i].size_pfn;
+                if (type >= MTRR_NUM_TYPES)
+                        continue;
+                if (!size)
+                        type = MTRR_NUM_TYPES;
+                num[type]++;
+        }
+
+        /* check if we got UC entries */
+        if (!num[MTRR_TYPE_UNCACHABLE])
+                return 0;
+
+        /* check if we only had WB and UC */
+        if (num[MTRR_TYPE_WRBACK] + num[MTRR_TYPE_UNCACHABLE] !=
+                num_var_ranges - num[MTRR_NUM_TYPES])
+                return 0;
+
+        memset(range, 0, sizeof(range));
+        extra_remove_size = 0;
+        if (mtrr_tom2) {
+                extra_remove_base = 1 << (32 - PAGE_SHIFT);
+                extra_remove_size =
+                        (mtrr_tom2 >> PAGE_SHIFT) - extra_remove_base;
+        }
+        nr_range = x86_get_mtrr_mem_range(range, 0, extra_remove_base,
+                                          extra_remove_size);
+        range_sums = sum_ranges(range, nr_range);
+        printk(KERN_INFO "total RAM coverred: %ldM\n",
+               range_sums >> (20 - PAGE_SHIFT));
+
+        if (mtrr_chunk_size && mtrr_gran_size) {
+                int num_reg;
+
+                debug_print = 1;
+                /* convert ranges to var ranges state */
+                num_reg = x86_setup_var_mtrrs(range, nr_range, mtrr_chunk_size,
+                                              mtrr_gran_size);
+
+                /* we got new setting in range_state, check it */
+                memset(range_new, 0, sizeof(range_new));
+                nr_range_new = x86_get_mtrr_mem_range(range_new, 0,
+                                                      extra_remove_base,
+                                                      extra_remove_size);
+                range_sums_new = sum_ranges(range_new, nr_range_new);
+
+                i = 0;
+                result[i].chunk_sizek = mtrr_chunk_size >> 10;
+                result[i].gran_sizek = mtrr_gran_size >> 10;
+                result[i].num_reg = num_reg;
+                if (range_sums < range_sums_new) {
+                        result[i].lose_cover_sizek =
+                                (range_sums_new - range_sums) << PSHIFT;
+                        result[i].bad = 1;
+                } else
+                        result[i].lose_cover_sizek =
+                                (range_sums - range_sums_new) << PSHIFT;
+
+                printk(KERN_INFO "%sgran_size: %ldM \tchunk_size: %ldM \t",
+                         result[i].bad?"*BAD*":" ", result[i].gran_sizek >> 10,
+                         result[i].chunk_sizek >> 10);
+                printk(KERN_CONT "num_reg: %d  \tlose cover RAM: %s%ldM \n",
+                         result[i].num_reg, result[i].bad?"-":"",
+                         result[i].lose_cover_sizek >> 10);
+                if (!result[i].bad) {
+                        set_var_mtrr_all(address_bits);
+                        return 1;
+                }
+                printk(KERN_INFO "invalid mtrr_gran_size or mtrr_chunk_size, "
+                       "will find optimal one\n");
+                debug_print = 0;
+                memset(result, 0, sizeof(result[0]));
+        }
+
+        i = 0;
+        memset(min_loss_pfn, 0xff, sizeof(min_loss_pfn));
+        memset(result, 0, sizeof(result));
+        for (gran_size = (1ULL<<20); gran_size < (1ULL<<32); gran_size <<= 1) {
+                for (chunk_size = gran_size; chunk_size < (1ULL<<33);
+                     chunk_size <<= 1) {
+                        int num_reg;
+
+                        if (debug_print)
+                                printk(KERN_INFO
+                               "\ngran_size: %lldM   chunk_size_size: %lldM\n",
+                                       gran_size >> 20, chunk_size >> 20);
+                        if (i >= NUM_RESULT)
+                                continue;
+
+                        /* convert ranges to var ranges state */
+                        num_reg = x86_setup_var_mtrrs(range, nr_range,
+                                                         chunk_size, gran_size);
+
+                        /* we got new setting in range_state, check it */
+                        memset(range_new, 0, sizeof(range_new));
+                        nr_range_new = x86_get_mtrr_mem_range(range_new, 0,
+                                         extra_remove_base, extra_remove_size);
+                        range_sums_new = sum_ranges(range_new, nr_range_new);
+
+                        result[i].chunk_sizek = chunk_size >> 10;
+                        result[i].gran_sizek = gran_size >> 10;
+                        result[i].num_reg = num_reg;
+                        if (range_sums < range_sums_new) {
+                                result[i].lose_cover_sizek =
+                                        (range_sums_new - range_sums) << PSHIFT;
+                                result[i].bad = 1;
+                        } else
+                                result[i].lose_cover_sizek =
+                                        (range_sums - range_sums_new) << PSHIFT;
+
+                        /* double check it */
+                        if (!result[i].bad && !result[i].lose_cover_sizek) {
+                                if (nr_range_new != nr_range ||
+                                        memcmp(range, range_new, sizeof(range)))
+                                                result[i].bad = 1;
+                        }
+
+                        if (!result[i].bad && (range_sums - range_sums_new <
+                                               min_loss_pfn[num_reg])) {
+                                min_loss_pfn[num_reg] =
+                                        range_sums - range_sums_new;
+                        }
+                        i++;
+                }
+        }
+
+        /* print out all */
+        for (i = 0; i < NUM_RESULT; i++) {
+                printk(KERN_INFO "%sgran_size: %ldM \tchunk_size: %ldM \t",
+                       result[i].bad?"*BAD* ":" ", result[i].gran_sizek >> 10,
+                       result[i].chunk_sizek >> 10);
+                printk(KERN_CONT "num_reg: %d \tlose RAM: %s%ldM\n",
+                       result[i].num_reg, result[i].bad?"-":"",
+                       result[i].lose_cover_sizek >> 10);
+        }
+
+        /* try to find the optimal index */
+        if (nr_mtrr_spare_reg >= num_var_ranges)
+                nr_mtrr_spare_reg = num_var_ranges - 1;
+        num_reg_good = -1;
+        for (i = num_var_ranges - nr_mtrr_spare_reg; i > 0; i--) {
+                if (!min_loss_pfn[i]) {
+                        num_reg_good = i;
+                        break;
+                }
+        }
+
+        index_good = -1;
+        if (num_reg_good != -1) {
+                for (i = 0; i < NUM_RESULT; i++) {
+                        if (!result[i].bad &&
+                            result[i].num_reg == num_reg_good &&
+                            !result[i].lose_cover_sizek) {
+                                index_good = i;
+                                break;
+                        }
+                }
+        }
+
+        if (index_good != -1) {
+                printk(KERN_INFO "Found optimal setting for mtrr clean up\n");
+                i = index_good;
+                printk(KERN_INFO "gran_size: %ldM \tchunk_size: %ldM \t",
+                                result[i].gran_sizek >> 10,
+                                result[i].chunk_sizek >> 10);
+                printk(KERN_CONT "num_reg: %d \tlose RAM: %ldM\n",
+                                result[i].num_reg,
+                                result[i].lose_cover_sizek >> 10);
+                /* convert ranges to var ranges state */
+                chunk_size = result[i].chunk_sizek;
+                chunk_size <<= 10;
+                gran_size = result[i].gran_sizek;
+                gran_size <<= 10;
+                debug_print = 1;
+                x86_setup_var_mtrrs(range, nr_range, chunk_size, gran_size);
+                set_var_mtrr_all(address_bits);
+                return 1;
+        }
+
+        printk(KERN_INFO "mtrr_cleanup: can not find optimal value\n");
+        printk(KERN_INFO "please specify mtrr_gran_size/mtrr_chunk_size\n");
+
+        return 0;
+}
+#else
+static int __init mtrr_cleanup(unsigned address_bits)
+{
+        return 0;
+}
+#endif
+
+static int __initdata changed_by_mtrr_cleanup;
+
 static int disable_mtrr_trim;
 
 static int __init disable_mtrr_trim_setup(char *str)
@@ -648,6 +1430,19 @@ int __init amd_special_default_mtrr(void)
         return 0;
 }
 
+static u64 __init real_trim_memory(unsigned long start_pfn,
+                                   unsigned long limit_pfn)
+{
+        u64 trim_start, trim_size;
+        trim_start = start_pfn;
+        trim_start <<= PAGE_SHIFT;
+        trim_size = limit_pfn;
+        trim_size <<= PAGE_SHIFT;
+        trim_size -= trim_start;
+
+        return e820_update_range(trim_start, trim_size, E820_RAM,
+                                E820_RESERVED);
+}
 /**
  * mtrr_trim_uncached_memory - trim RAM not covered by MTRRs
  * @end_pfn: ending page frame number
@@ -663,8 +1458,11 @@ int __init mtrr_trim_uncached_memory(unsigned long end_pfn)
 {
         unsigned long i, base, size, highest_pfn = 0, def, dummy;
         mtrr_type type;
-        u64 trim_start, trim_size;
+        int nr_range;
+        u64 total_trim_size;
 
+        /* extra one for all 0 */
+        int num[MTRR_NUM_TYPES + 1];
         /*
          * Make sure we only trim uncachable memory on machines that
          * support the Intel MTRR architecture:
@@ -676,14 +1474,22 @@ int __init mtrr_trim_uncached_memory(unsigned long end_pfn)
         if (def != MTRR_TYPE_UNCACHABLE)
                 return 0;
 
-        if (amd_special_default_mtrr())
-                return 0;
+        /* get it and store it aside */
+        memset(range_state, 0, sizeof(range_state));
+        for (i = 0; i < num_var_ranges; i++) {
+                mtrr_if->get(i, &base, &size, &type);
+                range_state[i].base_pfn = base;
+                range_state[i].size_pfn = size;
+                range_state[i].type = type;
+        }
 
         /* Find highest cached pfn */
         for (i = 0; i < num_var_ranges; i++) {
-                mtrr_if->get(i, &base, &size, &type);
+                type = range_state[i].type;
                 if (type != MTRR_TYPE_WRBACK)
                         continue;
+                base = range_state[i].base_pfn;
+                size = range_state[i].size_pfn;
                 if (highest_pfn < base + size)
                         highest_pfn = base + size;
         }
@@ -698,22 +1504,65 @@ int __init mtrr_trim_uncached_memory(unsigned long end_pfn)
                 return 0;
         }
 
-        if (highest_pfn < end_pfn) {
+        /* check entries number */
+        memset(num, 0, sizeof(num));
+        for (i = 0; i < num_var_ranges; i++) {
+                type = range_state[i].type;
+                if (type >= MTRR_NUM_TYPES)
+                        continue;
+                size = range_state[i].size_pfn;
+                if (!size)
+                        type = MTRR_NUM_TYPES;
+                num[type]++;
+        }
+
+        /* no entry for WB? */
+        if (!num[MTRR_TYPE_WRBACK])
+                return 0;
+
+        /* check if we only had WB and UC */
+        if (num[MTRR_TYPE_WRBACK] + num[MTRR_TYPE_UNCACHABLE] !=
+                num_var_ranges - num[MTRR_NUM_TYPES])
+                return 0;
+
+        memset(range, 0, sizeof(range));
+        nr_range = 0;
+        if (mtrr_tom2) {
+                range[nr_range].start = (1ULL<<(32 - PAGE_SHIFT));
+                range[nr_range].end = (mtrr_tom2 >> PAGE_SHIFT) - 1;
+                if (highest_pfn < range[nr_range].end + 1)
+                        highest_pfn = range[nr_range].end + 1;
+                nr_range++;
+        }
+        nr_range = x86_get_mtrr_mem_range(range, nr_range, 0, 0);
+
+        total_trim_size = 0;
+        /* check the head */
+        if (range[0].start)
+                total_trim_size += real_trim_memory(0, range[0].start);
+        /* check the holes */
+        for (i = 0; i < nr_range - 1; i++) {
+                if (range[i].end + 1 < range[i+1].start)
+                        total_trim_size += real_trim_memory(range[i].end + 1,
+                                                            range[i+1].start);
+        }
+        /* check the top */
+        i = nr_range - 1;
+        if (range[i].end + 1 < end_pfn)
+                total_trim_size += real_trim_memory(range[i].end + 1,
+                                                         end_pfn);
+
+        if (total_trim_size) {
                 printk(KERN_WARNING "WARNING: BIOS bug: CPU MTRRs don't cover"
-                        " all of memory, losing %luMB of RAM.\n",
-                        (end_pfn - highest_pfn) >> (20 - PAGE_SHIFT));
+                        " all of memory, losing %lluMB of RAM.\n",
+                        total_trim_size >> 20);
 
-                WARN_ON(1);
+                if (!changed_by_mtrr_cleanup)
+                        WARN_ON(1);
 
                 printk(KERN_INFO "update e820 for mtrr\n");
-                trim_start = highest_pfn;
-                trim_start <<= PAGE_SHIFT;
-                trim_size = end_pfn;
-                trim_size <<= PAGE_SHIFT;
-                trim_size -= trim_start;
-                update_memory_range(trim_start, trim_size, E820_RAM,
-                                        E820_RESERVED);
                 update_e820();
+
                 return 1;
         }
 
@@ -729,18 +1578,21 @@ int __init mtrr_trim_uncached_memory(unsigned long end_pfn)
  */
 void __init mtrr_bp_init(void)
 {
+        u32 phys_addr;
         init_ifs();
 
+        phys_addr = 32;
+
         if (cpu_has_mtrr) {
                 mtrr_if = &generic_mtrr_ops;
                 size_or_mask = 0xff000000;      /* 36 bits */
                 size_and_mask = 0x00f00000;
+                phys_addr = 36;
 
                 /* This is an AMD specific MSR, but we assume(hope?) that
                    Intel will implement it to when they extend the address
                    bus of the Xeon. */
                 if (cpuid_eax(0x80000000) >= 0x80000008) {
-                        u32 phys_addr;
                         phys_addr = cpuid_eax(0x80000008) & 0xff;
                         /* CPUID workaround for Intel 0F33/0F34 CPU */
                         if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
@@ -758,6 +1610,7 @@ void __init mtrr_bp_init(void)
                            don't support PAE */
                         size_or_mask = 0xfff00000;      /* 32 bits */
                         size_and_mask = 0;
+                        phys_addr = 32;
                 }
         } else {
                 switch (boot_cpu_data.x86_vendor) {
@@ -791,8 +1644,15 @@ void __init mtrr_bp_init(void)
         if (mtrr_if) {
                 set_num_var_ranges();
                 init_table();
-                if (use_intel())
+                if (use_intel()) {
                         get_mtrr_state();
+
+                        if (mtrr_cleanup(phys_addr)) {
+                                changed_by_mtrr_cleanup = 1;
+                                mtrr_if->set_all();
+                        }
+
+                }
         }
 }
 
@@ -829,9 +1689,10 @@ static int __init mtrr_init_finialize(void)
 {
         if (!mtrr_if)
                 return 0;
-        if (use_intel())
-                mtrr_state_warn();
-        else {
+        if (use_intel()) {
+                if (!changed_by_mtrr_cleanup)
+                        mtrr_state_warn();
+        } else {
                 /* The CPUs haven't MTRR and seem to not support SMP. They have
                  * specific drivers, we use a tricky method to support
                  * suspend/resume for them.
diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.h b/arch/x86/kernel/cpu/mtrr/mtrr.h
index 2cc77eb6fea3..2dc4ec656b23 100644
--- a/arch/x86/kernel/cpu/mtrr/mtrr.h
+++ b/arch/x86/kernel/cpu/mtrr/mtrr.h
@@ -81,6 +81,8 @@ void set_mtrr_done(struct set_mtrr_context *ctxt);
 void set_mtrr_cache_disable(struct set_mtrr_context *ctxt);
 void set_mtrr_prepare_save(struct set_mtrr_context *ctxt);
 
+void fill_mtrr_var_range(unsigned int index,
+                u32 base_lo, u32 base_hi, u32 mask_lo, u32 mask_hi);
 void get_mtrr_state(void);
 
 extern void set_mtrr_ops(struct mtrr_ops * ops);
@@ -92,6 +94,7 @@ extern struct mtrr_ops * mtrr_if;
 #define use_intel()     (mtrr_if && mtrr_if->use_intel_if == 1)
 
 extern unsigned int num_var_ranges;
+extern u64 mtrr_tom2;
 
 void mtrr_state_warn(void);
 const char *mtrr_attrib_to_str(int x);
diff --git a/arch/x86/kernel/cpu/perfctr-watchdog.c b/arch/x86/kernel/cpu/perfctr-watchdog.c
index f9ae93adffe5..2e9bef6e3aa3 100644
--- a/arch/x86/kernel/cpu/perfctr-watchdog.c
+++ b/arch/x86/kernel/cpu/perfctr-watchdog.c
@@ -1,11 +1,15 @@
-/* local apic based NMI watchdog for various CPUs.
-   This file also handles reservation of performance counters for coordination
-   with other users (like oprofile).
-
-   Note that these events normally don't tick when the CPU idles. This means
-   the frequency varies with CPU load.
-
-   Original code for K7/P6 written by Keith Owens */
+/*
+ * local apic based NMI watchdog for various CPUs.
+ *
+ * This file also handles reservation of performance counters for coordination
+ * with other users (like oprofile).
+ *
+ * Note that these events normally don't tick when the CPU idles. This means
+ * the frequency varies with CPU load.
+ *
+ * Original code for K7/P6 written by Keith Owens
+ *
+ */
 
 #include <linux/percpu.h>
 #include <linux/module.h>
@@ -36,12 +40,16 @@ struct wd_ops {
 
 static const struct wd_ops *wd_ops;
 
-/* this number is calculated from Intel's MSR_P4_CRU_ESCR5 register and it's
- * offset from MSR_P4_BSU_ESCR0.  It will be the max for all platforms (for now)
+/*
+ * this number is calculated from Intel's MSR_P4_CRU_ESCR5 register and it's
+ * offset from MSR_P4_BSU_ESCR0.
+ *
+ * It will be the max for all platforms (for now)
  */
 #define NMI_MAX_COUNTER_BITS 66
 
-/* perfctr_nmi_owner tracks the ownership of the perfctr registers:
+/*
+ * perfctr_nmi_owner tracks the ownership of the perfctr registers:
  * evtsel_nmi_owner tracks the ownership of the event selection
  * - different performance counters/ event selection may be reserved for
  *   different subsystems this reservation system just tries to coordinate
@@ -73,8 +81,10 @@ static inline unsigned int nmi_perfctr_msr_to_bit(unsigned int msr)
         return 0;
 }
 
-/* converts an msr to an appropriate reservation bit */
-/* returns the bit offset of the event selection register */
+/*
+ * converts an msr to an appropriate reservation bit
+ * returns the bit offset of the event selection register
+ */
 static inline unsigned int nmi_evntsel_msr_to_bit(unsigned int msr)
 {
         /* returns the bit offset of the event selection register */
@@ -114,6 +124,7 @@ int avail_to_resrv_perfctr_nmi(unsigned int msr)
 
         return (!test_bit(counter, perfctr_nmi_owner));
 }
+EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi_bit);
 
 int reserve_perfctr_nmi(unsigned int msr)
 {
@@ -128,6 +139,7 @@ int reserve_perfctr_nmi(unsigned int msr)
                 return 1;
         return 0;
 }
+EXPORT_SYMBOL(reserve_perfctr_nmi);
 
 void release_perfctr_nmi(unsigned int msr)
 {
@@ -140,6 +152,7 @@ void release_perfctr_nmi(unsigned int msr)
 
         clear_bit(counter, perfctr_nmi_owner);
 }
+EXPORT_SYMBOL(release_perfctr_nmi);
 
 int reserve_evntsel_nmi(unsigned int msr)
 {
@@ -154,6 +167,7 @@ int reserve_evntsel_nmi(unsigned int msr)
                 return 1;
         return 0;
 }
+EXPORT_SYMBOL(reserve_evntsel_nmi);
 
 void release_evntsel_nmi(unsigned int msr)
 {
@@ -166,11 +180,6 @@ void release_evntsel_nmi(unsigned int msr)
 
         clear_bit(counter, evntsel_nmi_owner);
 }
-
-EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi_bit);
-EXPORT_SYMBOL(reserve_perfctr_nmi);
-EXPORT_SYMBOL(release_perfctr_nmi);
-EXPORT_SYMBOL(reserve_evntsel_nmi);
 EXPORT_SYMBOL(release_evntsel_nmi);
 
 void disable_lapic_nmi_watchdog(void)
@@ -181,7 +190,9 @@ void disable_lapic_nmi_watchdog(void)
                 return;
 
         on_each_cpu(stop_apic_nmi_watchdog, NULL, 0, 1);
-        wd_ops->unreserve();
+
+        if (wd_ops)
+                wd_ops->unreserve();
 
         BUG_ON(atomic_read(&nmi_active) != 0);
 }
@@ -232,8 +243,8 @@ static unsigned int adjust_for_32bit_ctr(unsigned int hz)
         return retval;
 }
 
-static void
-write_watchdog_counter(unsigned int perfctr_msr, const char *descr, unsigned nmi_hz)
+static void write_watchdog_counter(unsigned int perfctr_msr,
+                                const char *descr, unsigned nmi_hz)
 {
         u64 count = (u64)cpu_khz * 1000;
 
@@ -244,7 +255,7 @@ write_watchdog_counter(unsigned int perfctr_msr, const char *descr, unsigned nmi
 }
 
 static void write_watchdog_counter32(unsigned int perfctr_msr,
-                const char *descr, unsigned nmi_hz)
+                                const char *descr, unsigned nmi_hz)
 {
         u64 count = (u64)cpu_khz * 1000;
 
@@ -254,9 +265,10 @@ static void write_watchdog_counter32(unsigned int perfctr_msr,
         wrmsr(perfctr_msr, (u32)(-count), 0);
 }
 
-/* AMD K7/K8/Family10h/Family11h support. AMD keeps this interface
-   nicely stable so there is not much variety */
-
+/*
+ * AMD K7/K8/Family10h/Family11h support.
+ * AMD keeps this interface nicely stable so there is not much variety
+ */
 #define K7_EVNTSEL_ENABLE       (1 << 22)
 #define K7_EVNTSEL_INT          (1 << 20)
 #define K7_EVNTSEL_OS           (1 << 17)
@@ -289,7 +301,7 @@ static int setup_k7_watchdog(unsigned nmi_hz)
 
         wd->perfctr_msr = perfctr_msr;
         wd->evntsel_msr = evntsel_msr;
-        wd->cccr_msr = 0;  //unused
+        wd->cccr_msr = 0;  /* unused */
         return 1;
 }
 
@@ -325,18 +337,19 @@ static void single_msr_rearm(struct nmi_watchdog_ctlblk *wd, unsigned nmi_hz)
 }
 
 static const struct wd_ops k7_wd_ops = {
-        .reserve = single_msr_reserve,
-        .unreserve = single_msr_unreserve,
-        .setup = setup_k7_watchdog,
-        .rearm = single_msr_rearm,
-        .stop = single_msr_stop_watchdog,
-        .perfctr = MSR_K7_PERFCTR0,
-        .evntsel = MSR_K7_EVNTSEL0,
-        .checkbit = 1ULL<<47,
+        .reserve        = single_msr_reserve,
+        .unreserve      = single_msr_unreserve,
+        .setup          = setup_k7_watchdog,
+        .rearm          = single_msr_rearm,
+        .stop           = single_msr_stop_watchdog,
+        .perfctr        = MSR_K7_PERFCTR0,
+        .evntsel        = MSR_K7_EVNTSEL0,
+        .checkbit       = 1ULL << 47,
 };
 
-/* Intel Model 6 (PPro+,P2,P3,P-M,Core1) */
-
+/*
+ * Intel Model 6 (PPro+,P2,P3,P-M,Core1)
+ */
 #define P6_EVNTSEL0_ENABLE      (1 << 22)
 #define P6_EVNTSEL_INT          (1 << 20)
 #define P6_EVNTSEL_OS           (1 << 17)
@@ -372,52 +385,58 @@ static int setup_p6_watchdog(unsigned nmi_hz)
 
         wd->perfctr_msr = perfctr_msr;
         wd->evntsel_msr = evntsel_msr;
-        wd->cccr_msr = 0;  //unused
+        wd->cccr_msr = 0;  /* unused */
         return 1;
 }
 
 static void p6_rearm(struct nmi_watchdog_ctlblk *wd, unsigned nmi_hz)
 {
-        /* P6 based Pentium M need to re-unmask
+        /*
+         * P6 based Pentium M need to re-unmask
          * the apic vector but it doesn't hurt
          * other P6 variant.
-         * ArchPerfom/Core Duo also needs this */
+         * ArchPerfom/Core Duo also needs this
+         */
         apic_write(APIC_LVTPC, APIC_DM_NMI);
+
         /* P6/ARCH_PERFMON has 32 bit counter write */
         write_watchdog_counter32(wd->perfctr_msr, NULL,nmi_hz);
 }
 
 static const struct wd_ops p6_wd_ops = {
-        .reserve = single_msr_reserve,
-        .unreserve = single_msr_unreserve,
-        .setup = setup_p6_watchdog,
-        .rearm = p6_rearm,
-        .stop = single_msr_stop_watchdog,
-        .perfctr = MSR_P6_PERFCTR0,
-        .evntsel = MSR_P6_EVNTSEL0,
-        .checkbit = 1ULL<<39,
+        .reserve        = single_msr_reserve,
+        .unreserve      = single_msr_unreserve,
+        .setup          = setup_p6_watchdog,
+        .rearm          = p6_rearm,
+        .stop           = single_msr_stop_watchdog,
+        .perfctr        = MSR_P6_PERFCTR0,
+        .evntsel        = MSR_P6_EVNTSEL0,
+        .checkbit       = 1ULL << 39,
 };
 
-/* Intel P4 performance counters. By far the most complicated of all. */
-
-#define MSR_P4_MISC_ENABLE_PERF_AVAIL   (1<<7)
-#define P4_ESCR_EVENT_SELECT(N) ((N)<<25)
-#define P4_ESCR_OS              (1<<3)
-#define P4_ESCR_USR             (1<<2)
-#define P4_CCCR_OVF_PMI0        (1<<26)
-#define P4_CCCR_OVF_PMI1        (1<<27)
-#define P4_CCCR_THRESHOLD(N)    ((N)<<20)
-#define P4_CCCR_COMPLEMENT      (1<<19)
-#define P4_CCCR_COMPARE         (1<<18)
-#define P4_CCCR_REQUIRED        (3<<16)
-#define P4_CCCR_ESCR_SELECT(N)  ((N)<<13)
-#define P4_CCCR_ENABLE          (1<<12)
-#define P4_CCCR_OVF             (1<<31)
-
-/* Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter
-   CRU_ESCR0 (with any non-null event selector) through a complemented
-   max threshold. [IA32-Vol3, Section 14.9.9] */
+/*
+ * Intel P4 performance counters.
+ * By far the most complicated of all.
+ */
+#define MSR_P4_MISC_ENABLE_PERF_AVAIL   (1 << 7)
+#define P4_ESCR_EVENT_SELECT(N) ((N) << 25)
+#define P4_ESCR_OS              (1 << 3)
+#define P4_ESCR_USR             (1 << 2)
+#define P4_CCCR_OVF_PMI0        (1 << 26)
+#define P4_CCCR_OVF_PMI1        (1 << 27)
+#define P4_CCCR_THRESHOLD(N)    ((N) << 20)
+#define P4_CCCR_COMPLEMENT      (1 << 19)
+#define P4_CCCR_COMPARE         (1 << 18)
+#define P4_CCCR_REQUIRED        (3 << 16)
+#define P4_CCCR_ESCR_SELECT(N)  ((N) << 13)
+#define P4_CCCR_ENABLE          (1 << 12)
+#define P4_CCCR_OVF             (1 << 31)
 
+/*
+ * Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter
+ * CRU_ESCR0 (with any non-null event selector) through a complemented
+ * max threshold. [IA32-Vol3, Section 14.9.9]
+ */
 static int setup_p4_watchdog(unsigned nmi_hz)
 {
         unsigned int perfctr_msr, evntsel_msr, cccr_msr;
@@ -442,7 +461,8 @@ static int setup_p4_watchdog(unsigned nmi_hz)
 #endif
                 ht_num = 0;
 
-        /* performance counters are shared resources
+        /*
+         * performance counters are shared resources
          * assign each hyperthread its own set
          * (re-use the ESCR0 register, seems safe
          * and keeps the cccr_val the same)
@@ -540,20 +560,21 @@ static void p4_rearm(struct nmi_watchdog_ctlblk *wd, unsigned nmi_hz)
 }
 
 static const struct wd_ops p4_wd_ops = {
-        .reserve = p4_reserve,
-        .unreserve = p4_unreserve,
-        .setup = setup_p4_watchdog,
-        .rearm = p4_rearm,
-        .stop = stop_p4_watchdog,
+        .reserve        = p4_reserve,
+        .unreserve      = p4_unreserve,
+        .setup          = setup_p4_watchdog,
+        .rearm          = p4_rearm,
+        .stop           = stop_p4_watchdog,
         /* RED-PEN this is wrong for the other sibling */
-        .perfctr = MSR_P4_BPU_PERFCTR0,
-        .evntsel = MSR_P4_BSU_ESCR0,
-        .checkbit = 1ULL<<39,
+        .perfctr        = MSR_P4_BPU_PERFCTR0,
+        .evntsel        = MSR_P4_BSU_ESCR0,
+        .checkbit       = 1ULL << 39,
 };
 
-/* Watchdog using the Intel architected PerfMon. Used for Core2 and hopefully
-   all future Intel CPUs. */
-
+/*
+ * Watchdog using the Intel architected PerfMon.
+ * Used for Core2 and hopefully all future Intel CPUs.
+ */
 #define ARCH_PERFMON_NMI_EVENT_SEL      ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL
 #define ARCH_PERFMON_NMI_EVENT_UMASK    ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK
 
@@ -599,19 +620,19 @@ static int setup_intel_arch_watchdog(unsigned nmi_hz)
 
         wd->perfctr_msr = perfctr_msr;
         wd->evntsel_msr = evntsel_msr;
-        wd->cccr_msr = 0;  //unused
+        wd->cccr_msr = 0;  /* unused */
         intel_arch_wd_ops.checkbit = 1ULL << (eax.split.bit_width - 1);
         return 1;
 }
 
 static struct wd_ops intel_arch_wd_ops __read_mostly = {
-        .reserve = single_msr_reserve,
-        .unreserve = single_msr_unreserve,
-        .setup = setup_intel_arch_watchdog,
-        .rearm = p6_rearm,
-        .stop = single_msr_stop_watchdog,
-        .perfctr = MSR_ARCH_PERFMON_PERFCTR1,
-        .evntsel = MSR_ARCH_PERFMON_EVENTSEL1,
+        .reserve        = single_msr_reserve,
+        .unreserve      = single_msr_unreserve,
+        .setup          = setup_intel_arch_watchdog,
+        .rearm          = p6_rearm,
+        .stop           = single_msr_stop_watchdog,
+        .perfctr        = MSR_ARCH_PERFMON_PERFCTR1,
+        .evntsel        = MSR_ARCH_PERFMON_EVENTSEL1,
 };
 
 static void probe_nmi_watchdog(void)
@@ -624,8 +645,10 @@ static void probe_nmi_watchdog(void)
                 wd_ops = &k7_wd_ops;
                 break;
         case X86_VENDOR_INTEL:
-                /* Work around Core Duo (Yonah) errata AE49 where perfctr1
-                   doesn't have a working enable bit. */
+                /*
+                 * Work around Core Duo (Yonah) errata AE49 where perfctr1
+                 * doesn't have a working enable bit.
+                 */
                 if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 14) {
                         intel_arch_wd_ops.perfctr = MSR_ARCH_PERFMON_PERFCTR0;
                         intel_arch_wd_ops.evntsel = MSR_ARCH_PERFMON_EVENTSEL0;
@@ -636,7 +659,7 @@ static void probe_nmi_watchdog(void)
                 }
                 switch (boot_cpu_data.x86) {
                 case 6:
-                        if (boot_cpu_data.x86_model > 0xd)
+                        if (boot_cpu_data.x86_model > 13)
                                 return;
 
                         wd_ops = &p6_wd_ops;
@@ -697,10 +720,11 @@ int lapic_wd_event(unsigned nmi_hz)
 {
         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
         u64 ctr;
+
         rdmsrl(wd->perfctr_msr, ctr);
-        if (ctr & wd_ops->checkbit) { /* perfctr still running? */
+        if (ctr & wd_ops->checkbit) /* perfctr still running? */
                 return 0;
-        }
+
         wd_ops->rearm(wd, nmi_hz);
         return 1;
 }
diff --git a/arch/x86/kernel/cpuid.c b/arch/x86/kernel/cpuid.c
index daff52a62248..71f1c2654bec 100644
--- a/arch/x86/kernel/cpuid.c
+++ b/arch/x86/kernel/cpuid.c
@@ -33,6 +33,7 @@
 #include <linux/init.h>
 #include <linux/poll.h>
 #include <linux/smp.h>
+#include <linux/smp_lock.h>
 #include <linux/major.h>
 #include <linux/fs.h>
 #include <linux/smp_lock.h>
@@ -107,15 +108,23 @@ static ssize_t cpuid_read(struct file *file, char __user *buf,
 
 static int cpuid_open(struct inode *inode, struct file *file)
 {
-        unsigned int cpu = iminor(file->f_path.dentry->d_inode);
-        struct cpuinfo_x86 *c = &cpu_data(cpu);
-
-        if (cpu >= NR_CPUS || !cpu_online(cpu))
-                return -ENXIO;  /* No such CPU */
+        unsigned int cpu;
+        struct cpuinfo_x86 *c;
+        int ret = 0;
+        
+        lock_kernel();
+
+        cpu = iminor(file->f_path.dentry->d_inode);
+        if (cpu >= NR_CPUS || !cpu_online(cpu)) {
+                ret = -ENXIO;   /* No such CPU */
+                goto out;
+        }
+        c = &cpu_data(cpu);
         if (c->cpuid_level < 0)
-                return -EIO;    /* CPUID not supported */
-
-        return 0;
+                ret = -EIO;     /* CPUID not supported */
+out:
+        unlock_kernel();
+        return ret;
 }
 
 /*
diff --git a/arch/x86/kernel/e820.c b/arch/x86/kernel/e820.c
new file mode 100644
index 000000000000..28c29180b380
--- /dev/null
+++ b/arch/x86/kernel/e820.c
@@ -0,0 +1,1390 @@
+/*
+ * Handle the memory map.
+ * The functions here do the job until bootmem takes over.
+ *
+ *  Getting sanitize_e820_map() in sync with i386 version by applying change:
+ *  -  Provisions for empty E820 memory regions (reported by certain BIOSes).
+ *     Alex Achenbach <xela@slit.de>, December 2002.
+ *  Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/bootmem.h>
+#include <linux/ioport.h>
+#include <linux/string.h>
+#include <linux/kexec.h>
+#include <linux/module.h>
+#include <linux/mm.h>
+#include <linux/pfn.h>
+#include <linux/suspend.h>
+#include <linux/firmware-map.h>
+
+#include <asm/pgtable.h>
+#include <asm/page.h>
+#include <asm/e820.h>
+#include <asm/proto.h>
+#include <asm/setup.h>
+#include <asm/trampoline.h>
+
+/*
+ * The e820 map is the map that gets modified e.g. with command line parameters
+ * and that is also registered with modifications in the kernel resource tree
+ * with the iomem_resource as parent.
+ *
+ * The e820_saved is directly saved after the BIOS-provided memory map is
+ * copied. It doesn't get modified afterwards. It's registered for the
+ * /sys/firmware/memmap interface.
+ *
+ * That memory map is not modified and is used as base for kexec. The kexec'd
+ * kernel should get the same memory map as the firmware provides. Then the
+ * user can e.g. boot the original kernel with mem=1G while still booting the
+ * next kernel with full memory.
+ */
+struct e820map e820;
+struct e820map e820_saved;
+
+/* For PCI or other memory-mapped resources */
+unsigned long pci_mem_start = 0xaeedbabe;
+#ifdef CONFIG_PCI
+EXPORT_SYMBOL(pci_mem_start);
+#endif
+
+/*
+ * This function checks if any part of the range <start,end> is mapped
+ * with type.
+ */
+int
+e820_any_mapped(u64 start, u64 end, unsigned type)
+{
+        int i;
+
+        for (i = 0; i < e820.nr_map; i++) {
+                struct e820entry *ei = &e820.map[i];
+
+                if (type && ei->type != type)
+                        continue;
+                if (ei->addr >= end || ei->addr + ei->size <= start)
+                        continue;
+                return 1;
+        }
+        return 0;
+}
+EXPORT_SYMBOL_GPL(e820_any_mapped);
+
+/*
+ * This function checks if the entire range <start,end> is mapped with type.
+ *
+ * Note: this function only works correct if the e820 table is sorted and
+ * not-overlapping, which is the case
+ */
+int __init e820_all_mapped(u64 start, u64 end, unsigned type)
+{
+        int i;
+
+        for (i = 0; i < e820.nr_map; i++) {
+                struct e820entry *ei = &e820.map[i];
+
+                if (type && ei->type != type)
+                        continue;
+                /* is the region (part) in overlap with the current region ?*/
+                if (ei->addr >= end || ei->addr + ei->size <= start)
+                        continue;
+
+                /* if the region is at the beginning of <start,end> we move
+                 * start to the end of the region since it's ok until there
+                 */
+                if (ei->addr <= start)
+                        start = ei->addr + ei->size;
+                /*
+                 * if start is now at or beyond end, we're done, full
+                 * coverage
+                 */
+                if (start >= end)
+                        return 1;
+        }
+        return 0;
+}
+
+/*
+ * Add a memory region to the kernel e820 map.
+ */
+void __init e820_add_region(u64 start, u64 size, int type)
+{
+        int x = e820.nr_map;
+
+        if (x == ARRAY_SIZE(e820.map)) {
+                printk(KERN_ERR "Ooops! Too many entries in the memory map!\n");
+                return;
+        }
+
+        e820.map[x].addr = start;
+        e820.map[x].size = size;
+        e820.map[x].type = type;
+        e820.nr_map++;
+}
+
+void __init e820_print_map(char *who)
+{
+        int i;
+
+        for (i = 0; i < e820.nr_map; i++) {
+                printk(KERN_INFO " %s: %016Lx - %016Lx ", who,
+                       (unsigned long long) e820.map[i].addr,
+                       (unsigned long long)
+                       (e820.map[i].addr + e820.map[i].size));
+                switch (e820.map[i].type) {
+                case E820_RAM:
+                case E820_RESERVED_KERN:
+                        printk(KERN_CONT "(usable)\n");
+                        break;
+                case E820_RESERVED:
+                        printk(KERN_CONT "(reserved)\n");
+                        break;
+                case E820_ACPI:
+                        printk(KERN_CONT "(ACPI data)\n");
+                        break;
+                case E820_NVS:
+                        printk(KERN_CONT "(ACPI NVS)\n");
+                        break;
+                default:
+                        printk(KERN_CONT "type %u\n", e820.map[i].type);
+                        break;
+                }
+        }
+}
+
+/*
+ * Sanitize the BIOS e820 map.
+ *
+ * Some e820 responses include overlapping entries. The following
+ * replaces the original e820 map with a new one, removing overlaps,
+ * and resolving conflicting memory types in favor of highest
+ * numbered type.
+ *
+ * The input parameter biosmap points to an array of 'struct
+ * e820entry' which on entry has elements in the range [0, *pnr_map)
+ * valid, and which has space for up to max_nr_map entries.
+ * On return, the resulting sanitized e820 map entries will be in
+ * overwritten in the same location, starting at biosmap.
+ *
+ * The integer pointed to by pnr_map must be valid on entry (the
+ * current number of valid entries located at biosmap) and will
+ * be updated on return, with the new number of valid entries
+ * (something no more than max_nr_map.)
+ *
+ * The return value from sanitize_e820_map() is zero if it
+ * successfully 'sanitized' the map entries passed in, and is -1
+ * if it did nothing, which can happen if either of (1) it was
+ * only passed one map entry, or (2) any of the input map entries
+ * were invalid (start + size < start, meaning that the size was
+ * so big the described memory range wrapped around through zero.)
+ *
+ *      Visually we're performing the following
+ *      (1,2,3,4 = memory types)...
+ *
+ *      Sample memory map (w/overlaps):
+ *         ____22__________________
+ *         ______________________4_
+ *         ____1111________________
+ *         _44_____________________
+ *         11111111________________
+ *         ____________________33__
+ *         ___________44___________
+ *         __________33333_________
+ *         ______________22________
+ *         ___________________2222_
+ *         _________111111111______
+ *         _____________________11_
+ *         _________________4______
+ *
+ *      Sanitized equivalent (no overlap):
+ *         1_______________________
+ *         _44_____________________
+ *         ___1____________________
+ *         ____22__________________
+ *         ______11________________
+ *         _________1______________
+ *         __________3_____________
+ *         ___________44___________
+ *         _____________33_________
+ *         _______________2________
+ *         ________________1_______
+ *         _________________4______
+ *         ___________________2____
+ *         ____________________33__
+ *         ______________________4_
+ */
+
+int __init sanitize_e820_map(struct e820entry *biosmap, int max_nr_map,
+                                int *pnr_map)
+{
+        struct change_member {
+                struct e820entry *pbios; /* pointer to original bios entry */
+                unsigned long long addr; /* address for this change point */
+        };
+        static struct change_member change_point_list[2*E820_X_MAX] __initdata;
+        static struct change_member *change_point[2*E820_X_MAX] __initdata;
+        static struct e820entry *overlap_list[E820_X_MAX] __initdata;
+        static struct e820entry new_bios[E820_X_MAX] __initdata;
+        struct change_member *change_tmp;
+        unsigned long current_type, last_type;
+        unsigned long long last_addr;
+        int chgidx, still_changing;
+        int overlap_entries;
+        int new_bios_entry;
+        int old_nr, new_nr, chg_nr;
+        int i;
+
+        /* if there's only one memory region, don't bother */
+        if (*pnr_map < 2)
+                return -1;
+
+        old_nr = *pnr_map;
+        BUG_ON(old_nr > max_nr_map);
+
+        /* bail out if we find any unreasonable addresses in bios map */
+        for (i = 0; i < old_nr; i++)
+                if (biosmap[i].addr + biosmap[i].size < biosmap[i].addr)
+                        return -1;
+
+        /* create pointers for initial change-point information (for sorting) */
+        for (i = 0; i < 2 * old_nr; i++)
+                change_point[i] = &change_point_list[i];
+
+        /* record all known change-points (starting and ending addresses),
+           omitting those that are for empty memory regions */
+        chgidx = 0;
+        for (i = 0; i < old_nr; i++)    {
+                if (biosmap[i].size != 0) {
+                        change_point[chgidx]->addr = biosmap[i].addr;
+                        change_point[chgidx++]->pbios = &biosmap[i];
+                        change_point[chgidx]->addr = biosmap[i].addr +
+                                biosmap[i].size;
+                        change_point[chgidx++]->pbios = &biosmap[i];
+                }
+        }
+        chg_nr = chgidx;
+
+        /* sort change-point list by memory addresses (low -> high) */
+        still_changing = 1;
+        while (still_changing)  {
+                still_changing = 0;
+                for (i = 1; i < chg_nr; i++)  {
+                        unsigned long long curaddr, lastaddr;
+                        unsigned long long curpbaddr, lastpbaddr;
+
+                        curaddr = change_point[i]->addr;
+                        lastaddr = change_point[i - 1]->addr;
+                        curpbaddr = change_point[i]->pbios->addr;
+                        lastpbaddr = change_point[i - 1]->pbios->addr;
+
+                        /*
+                         * swap entries, when:
+                         *
+                         * curaddr > lastaddr or
+                         * curaddr == lastaddr and curaddr == curpbaddr and
+                         * lastaddr != lastpbaddr
+                         */
+                        if (curaddr < lastaddr ||
+                            (curaddr == lastaddr && curaddr == curpbaddr &&
+                             lastaddr != lastpbaddr)) {
+                                change_tmp = change_point[i];
+                                change_point[i] = change_point[i-1];
+                                change_point[i-1] = change_tmp;
+                                still_changing = 1;
+                        }
+                }
+        }
+
+        /* create a new bios memory map, removing overlaps */
+        overlap_entries = 0;     /* number of entries in the overlap table */
+        new_bios_entry = 0;      /* index for creating new bios map entries */
+        last_type = 0;           /* start with undefined memory type */
+        last_addr = 0;           /* start with 0 as last starting address */
+
+        /* loop through change-points, determining affect on the new bios map */
+        for (chgidx = 0; chgidx < chg_nr; chgidx++) {
+                /* keep track of all overlapping bios entries */
+                if (change_point[chgidx]->addr ==
+                    change_point[chgidx]->pbios->addr) {
+                        /*
+                         * add map entry to overlap list (> 1 entry
+                         * implies an overlap)
+                         */
+                        overlap_list[overlap_entries++] =
+                                change_point[chgidx]->pbios;
+                } else {
+                        /*
+                         * remove entry from list (order independent,
+                         * so swap with last)
+                         */
+                        for (i = 0; i < overlap_entries; i++) {
+                                if (overlap_list[i] ==
+                                    change_point[chgidx]->pbios)
+                                        overlap_list[i] =
+                                                overlap_list[overlap_entries-1];
+                        }
+                        overlap_entries--;
+                }
+                /*
+                 * if there are overlapping entries, decide which
+                 * "type" to use (larger value takes precedence --
+                 * 1=usable, 2,3,4,4+=unusable)
+                 */
+                current_type = 0;
+                for (i = 0; i < overlap_entries; i++)
+                        if (overlap_list[i]->type > current_type)
+                                current_type = overlap_list[i]->type;
+                /*
+                 * continue building up new bios map based on this
+                 * information
+                 */
+                if (current_type != last_type)  {
+                        if (last_type != 0)      {
+                                new_bios[new_bios_entry].size =
+                                        change_point[chgidx]->addr - last_addr;
+                                /*
+                                 * move forward only if the new size
+                                 * was non-zero
+                                 */
+                                if (new_bios[new_bios_entry].size != 0)
+                                        /*
+                                         * no more space left for new
+                                         * bios entries ?
+                                         */
+                                        if (++new_bios_entry >= max_nr_map)
+                                                break;
+                        }
+                        if (current_type != 0)  {
+                                new_bios[new_bios_entry].addr =
+                                        change_point[chgidx]->addr;
+                                new_bios[new_bios_entry].type = current_type;
+                                last_addr = change_point[chgidx]->addr;
+                        }
+                        last_type = current_type;
+                }
+        }
+        /* retain count for new bios entries */
+        new_nr = new_bios_entry;
+
+        /* copy new bios mapping into original location */
+        memcpy(biosmap, new_bios, new_nr * sizeof(struct e820entry));
+        *pnr_map = new_nr;
+
+        return 0;
+}
+
+static int __init __append_e820_map(struct e820entry *biosmap, int nr_map)
+{
+        while (nr_map) {
+                u64 start = biosmap->addr;
+                u64 size = biosmap->size;
+                u64 end = start + size;
+                u32 type = biosmap->type;
+
+                /* Overflow in 64 bits? Ignore the memory map. */
+                if (start > end)
+                        return -1;
+
+                e820_add_region(start, size, type);
+
+                biosmap++;
+                nr_map--;
+        }
+        return 0;
+}
+
+/*
+ * Copy the BIOS e820 map into a safe place.
+ *
+ * Sanity-check it while we're at it..
+ *
+ * If we're lucky and live on a modern system, the setup code
+ * will have given us a memory map that we can use to properly
+ * set up memory.  If we aren't, we'll fake a memory map.
+ */
+static int __init append_e820_map(struct e820entry *biosmap, int nr_map)
+{
+        /* Only one memory region (or negative)? Ignore it */
+        if (nr_map < 2)
+                return -1;
+
+        return __append_e820_map(biosmap, nr_map);
+}
+
+static u64 __init e820_update_range_map(struct e820map *e820x, u64 start,
+                                        u64 size, unsigned old_type,
+                                        unsigned new_type)
+{
+        int i;
+        u64 real_updated_size = 0;
+
+        BUG_ON(old_type == new_type);
+
+        if (size > (ULLONG_MAX - start))
+                size = ULLONG_MAX - start;
+
+        for (i = 0; i < e820.nr_map; i++) {
+                struct e820entry *ei = &e820x->map[i];
+                u64 final_start, final_end;
+                if (ei->type != old_type)
+                        continue;
+                /* totally covered? */
+                if (ei->addr >= start &&
+                    (ei->addr + ei->size) <= (start + size)) {
+                        ei->type = new_type;
+                        real_updated_size += ei->size;
+                        continue;
+                }
+                /* partially covered */
+                final_start = max(start, ei->addr);
+                final_end = min(start + size, ei->addr + ei->size);
+                if (final_start >= final_end)
+                        continue;
+                e820_add_region(final_start, final_end - final_start,
+                                         new_type);
+                real_updated_size += final_end - final_start;
+
+                ei->size -= final_end - final_start;
+                if (ei->addr < final_start)
+                        continue;
+                ei->addr = final_end;
+        }
+        return real_updated_size;
+}
+
+u64 __init e820_update_range(u64 start, u64 size, unsigned old_type,
+                             unsigned new_type)
+{
+        return e820_update_range_map(&e820, start, size, old_type, new_type);
+}
+
+static u64 __init e820_update_range_saved(u64 start, u64 size,
+                                          unsigned old_type, unsigned new_type)
+{
+        return e820_update_range_map(&e820_saved, start, size, old_type,
+                                     new_type);
+}
+
+/* make e820 not cover the range */
+u64 __init e820_remove_range(u64 start, u64 size, unsigned old_type,
+                             int checktype)
+{
+        int i;
+        u64 real_removed_size = 0;
+
+        if (size > (ULLONG_MAX - start))
+                size = ULLONG_MAX - start;
+
+        for (i = 0; i < e820.nr_map; i++) {
+                struct e820entry *ei = &e820.map[i];
+                u64 final_start, final_end;
+
+                if (checktype && ei->type != old_type)
+                        continue;
+                /* totally covered? */
+                if (ei->addr >= start &&
+                    (ei->addr + ei->size) <= (start + size)) {
+                        real_removed_size += ei->size;
+                        memset(ei, 0, sizeof(struct e820entry));
+                        continue;
+                }
+                /* partially covered */
+                final_start = max(start, ei->addr);
+                final_end = min(start + size, ei->addr + ei->size);
+                if (final_start >= final_end)
+                        continue;
+                real_removed_size += final_end - final_start;
+
+                ei->size -= final_end - final_start;
+                if (ei->addr < final_start)
+                        continue;
+                ei->addr = final_end;
+        }
+        return real_removed_size;
+}
+
+void __init update_e820(void)
+{
+        int nr_map;
+
+        nr_map = e820.nr_map;
+        if (sanitize_e820_map(e820.map, ARRAY_SIZE(e820.map), &nr_map))
+                return;
+        e820.nr_map = nr_map;
+        printk(KERN_INFO "modified physical RAM map:\n");
+        e820_print_map("modified");
+}
+static void __init update_e820_saved(void)
+{
+        int nr_map;
+
+        nr_map = e820_saved.nr_map;
+        if (sanitize_e820_map(e820_saved.map, ARRAY_SIZE(e820_saved.map), &nr_map))
+                return;
+        e820_saved.nr_map = nr_map;
+}
+#define MAX_GAP_END 0x100000000ull
+/*
+ * Search for a gap in the e820 memory space from start_addr to end_addr.
+ */
+__init int e820_search_gap(unsigned long *gapstart, unsigned long *gapsize,
+                unsigned long start_addr, unsigned long long end_addr)
+{
+        unsigned long long last;
+        int i = e820.nr_map;
+        int found = 0;
+
+        last = (end_addr && end_addr < MAX_GAP_END) ? end_addr : MAX_GAP_END;
+
+        while (--i >= 0) {
+                unsigned long long start = e820.map[i].addr;
+                unsigned long long end = start + e820.map[i].size;
+
+                if (end < start_addr)
+                        continue;
+
+                /*
+                 * Since "last" is at most 4GB, we know we'll
+                 * fit in 32 bits if this condition is true
+                 */
+                if (last > end) {
+                        unsigned long gap = last - end;
+
+                        if (gap >= *gapsize) {
+                                *gapsize = gap;
+                                *gapstart = end;
+                                found = 1;
+                        }
+                }
+                if (start < last)
+                        last = start;
+        }
+        return found;
+}
+
+/*
+ * Search for the biggest gap in the low 32 bits of the e820
+ * memory space.  We pass this space to PCI to assign MMIO resources
+ * for hotplug or unconfigured devices in.
+ * Hopefully the BIOS let enough space left.
+ */
+__init void e820_setup_gap(void)
+{
+        unsigned long gapstart, gapsize, round;
+        int found;
+
+        gapstart = 0x10000000;
+        gapsize = 0x400000;
+        found  = e820_search_gap(&gapstart, &gapsize, 0, MAX_GAP_END);
+
+#ifdef CONFIG_X86_64
+        if (!found) {
+                gapstart = (max_pfn << PAGE_SHIFT) + 1024*1024;
+                printk(KERN_ERR "PCI: Warning: Cannot find a gap in the 32bit "
+                       "address range\n"
+                       KERN_ERR "PCI: Unassigned devices with 32bit resource "
+                       "registers may break!\n");
+        }
+#endif
+
+        /*
+         * See how much we want to round up: start off with
+         * rounding to the next 1MB area.
+         */
+        round = 0x100000;
+        while ((gapsize >> 4) > round)
+                round += round;
+        /* Fun with two's complement */
+        pci_mem_start = (gapstart + round) & -round;
+
+        printk(KERN_INFO
+               "Allocating PCI resources starting at %lx (gap: %lx:%lx)\n",
+               pci_mem_start, gapstart, gapsize);
+}
+
+/**
+ * Because of the size limitation of struct boot_params, only first
+ * 128 E820 memory entries are passed to kernel via
+ * boot_params.e820_map, others are passed via SETUP_E820_EXT node of
+ * linked list of struct setup_data, which is parsed here.
+ */
+void __init parse_e820_ext(struct setup_data *sdata, unsigned long pa_data)
+{
+        u32 map_len;
+        int entries;
+        struct e820entry *extmap;
+
+        entries = sdata->len / sizeof(struct e820entry);
+        map_len = sdata->len + sizeof(struct setup_data);
+        if (map_len > PAGE_SIZE)
+                sdata = early_ioremap(pa_data, map_len);
+        extmap = (struct e820entry *)(sdata->data);
+        __append_e820_map(extmap, entries);
+        sanitize_e820_map(e820.map, ARRAY_SIZE(e820.map), &e820.nr_map);
+        if (map_len > PAGE_SIZE)
+                early_iounmap(sdata, map_len);
+        printk(KERN_INFO "extended physical RAM map:\n");
+        e820_print_map("extended");
+}
+
+#if defined(CONFIG_X86_64) || \
+        (defined(CONFIG_X86_32) && defined(CONFIG_HIBERNATION))
+/**
+ * Find the ranges of physical addresses that do not correspond to
+ * e820 RAM areas and mark the corresponding pages as nosave for
+ * hibernation (32 bit) or software suspend and suspend to RAM (64 bit).
+ *
+ * This function requires the e820 map to be sorted and without any
+ * overlapping entries and assumes the first e820 area to be RAM.
+ */
+void __init e820_mark_nosave_regions(unsigned long limit_pfn)
+{
+        int i;
+        unsigned long pfn;
+
+        pfn = PFN_DOWN(e820.map[0].addr + e820.map[0].size);
+        for (i = 1; i < e820.nr_map; i++) {
+                struct e820entry *ei = &e820.map[i];
+
+                if (pfn < PFN_UP(ei->addr))
+                        register_nosave_region(pfn, PFN_UP(ei->addr));
+
+                pfn = PFN_DOWN(ei->addr + ei->size);
+                if (ei->type != E820_RAM && ei->type != E820_RESERVED_KERN)
+                        register_nosave_region(PFN_UP(ei->addr), pfn);
+
+                if (pfn >= limit_pfn)
+                        break;
+        }
+}
+#endif
+
+/*
+ * Early reserved memory areas.
+ */
+#define MAX_EARLY_RES 20
+
+struct early_res {
+        u64 start, end;
+        char name[16];
+        char overlap_ok;
+};
+static struct early_res early_res[MAX_EARLY_RES] __initdata = {
+        { 0, PAGE_SIZE, "BIOS data page" },     /* BIOS data page */
+#if defined(CONFIG_X86_64) && defined(CONFIG_X86_TRAMPOLINE)
+        { TRAMPOLINE_BASE, TRAMPOLINE_BASE + 2 * PAGE_SIZE, "TRAMPOLINE" },
+#endif
+#if defined(CONFIG_X86_32) && defined(CONFIG_SMP)
+        /*
+         * But first pinch a few for the stack/trampoline stuff
+         * FIXME: Don't need the extra page at 4K, but need to fix
+         * trampoline before removing it. (see the GDT stuff)
+         */
+        { PAGE_SIZE, PAGE_SIZE + PAGE_SIZE, "EX TRAMPOLINE" },
+        /*
+         * Has to be in very low memory so we can execute
+         * real-mode AP code.
+         */
+        { TRAMPOLINE_BASE, TRAMPOLINE_BASE + PAGE_SIZE, "TRAMPOLINE" },
+#endif
+        {}
+};
+
+static int __init find_overlapped_early(u64 start, u64 end)
+{
+        int i;
+        struct early_res *r;
+
+        for (i = 0; i < MAX_EARLY_RES && early_res[i].end; i++) {
+                r = &early_res[i];
+                if (end > r->start && start < r->end)
+                        break;
+        }
+
+        return i;
+}
+
+/*
+ * Drop the i-th range from the early reservation map,
+ * by copying any higher ranges down one over it, and
+ * clearing what had been the last slot.
+ */
+static void __init drop_range(int i)
+{
+        int j;
+
+        for (j = i + 1; j < MAX_EARLY_RES && early_res[j].end; j++)
+                ;
+
+        memmove(&early_res[i], &early_res[i + 1],
+               (j - 1 - i) * sizeof(struct early_res));
+
+        early_res[j - 1].end = 0;
+}
+
+/*
+ * Split any existing ranges that:
+ *  1) are marked 'overlap_ok', and
+ *  2) overlap with the stated range [start, end)
+ * into whatever portion (if any) of the existing range is entirely
+ * below or entirely above the stated range.  Drop the portion
+ * of the existing range that overlaps with the stated range,
+ * which will allow the caller of this routine to then add that
+ * stated range without conflicting with any existing range.
+ */
+static void __init drop_overlaps_that_are_ok(u64 start, u64 end)
+{
+        int i;
+        struct early_res *r;
+        u64 lower_start, lower_end;
+        u64 upper_start, upper_end;
+        char name[16];
+
+        for (i = 0; i < MAX_EARLY_RES && early_res[i].end; i++) {
+                r = &early_res[i];
+
+                /* Continue past non-overlapping ranges */
+                if (end <= r->start || start >= r->end)
+                        continue;
+
+                /*
+                 * Leave non-ok overlaps as is; let caller
+                 * panic "Overlapping early reservations"
+                 * when it hits this overlap.
+                 */
+                if (!r->overlap_ok)
+                        return;
+
+                /*
+                 * We have an ok overlap.  We will drop it from the early
+                 * reservation map, and add back in any non-overlapping
+                 * portions (lower or upper) as separate, overlap_ok,
+                 * non-overlapping ranges.
+                 */
+
+                /* 1. Note any non-overlapping (lower or upper) ranges. */
+                strncpy(name, r->name, sizeof(name) - 1);
+
+                lower_start = lower_end = 0;
+                upper_start = upper_end = 0;
+                if (r->start < start) {
+                        lower_start = r->start;
+                        lower_end = start;
+                }
+                if (r->end > end) {
+                        upper_start = end;
+                        upper_end = r->end;
+                }
+
+                /* 2. Drop the original ok overlapping range */
+                drop_range(i);
+
+                i--;            /* resume for-loop on copied down entry */
+
+                /* 3. Add back in any non-overlapping ranges. */
+                if (lower_end)
+                        reserve_early_overlap_ok(lower_start, lower_end, name);
+                if (upper_end)
+                        reserve_early_overlap_ok(upper_start, upper_end, name);
+        }
+}
+
+static void __init __reserve_early(u64 start, u64 end, char *name,
+                                                int overlap_ok)
+{
+        int i;
+        struct early_res *r;
+
+        i = find_overlapped_early(start, end);
+        if (i >= MAX_EARLY_RES)
+                panic("Too many early reservations");
+        r = &early_res[i];
+        if (r->end)
+                panic("Overlapping early reservations "
+                      "%llx-%llx %s to %llx-%llx %s\n",
+                      start, end - 1, name?name:"", r->start,
+                      r->end - 1, r->name);
+        r->start = start;
+        r->end = end;
+        r->overlap_ok = overlap_ok;
+        if (name)
+                strncpy(r->name, name, sizeof(r->name) - 1);
+}
+
+/*
+ * A few early reservtations come here.
+ *
+ * The 'overlap_ok' in the name of this routine does -not- mean it
+ * is ok for these reservations to overlap an earlier reservation.
+ * Rather it means that it is ok for subsequent reservations to
+ * overlap this one.
+ *
+ * Use this entry point to reserve early ranges when you are doing
+ * so out of "Paranoia", reserving perhaps more memory than you need,
+ * just in case, and don't mind a subsequent overlapping reservation
+ * that is known to be needed.
+ *
+ * The drop_overlaps_that_are_ok() call here isn't really needed.
+ * It would be needed if we had two colliding 'overlap_ok'
+ * reservations, so that the second such would not panic on the
+ * overlap with the first.  We don't have any such as of this
+ * writing, but might as well tolerate such if it happens in
+ * the future.
+ */
+void __init reserve_early_overlap_ok(u64 start, u64 end, char *name)
+{
+        drop_overlaps_that_are_ok(start, end);
+        __reserve_early(start, end, name, 1);
+}
+
+/*
+ * Most early reservations come here.
+ *
+ * We first have drop_overlaps_that_are_ok() drop any pre-existing
+ * 'overlap_ok' ranges, so that we can then reserve this memory
+ * range without risk of panic'ing on an overlapping overlap_ok
+ * early reservation.
+ */
+void __init reserve_early(u64 start, u64 end, char *name)
+{
+        drop_overlaps_that_are_ok(start, end);
+        __reserve_early(start, end, name, 0);
+}
+
+void __init free_early(u64 start, u64 end)
+{
+        struct early_res *r;
+        int i;
+
+        i = find_overlapped_early(start, end);
+        r = &early_res[i];
+        if (i >= MAX_EARLY_RES || r->end != end || r->start != start)
+                panic("free_early on not reserved area: %llx-%llx!",
+                         start, end - 1);
+
+        drop_range(i);
+}
+
+void __init early_res_to_bootmem(u64 start, u64 end)
+{
+        int i, count;
+        u64 final_start, final_end;
+
+        count  = 0;
+        for (i = 0; i < MAX_EARLY_RES && early_res[i].end; i++)
+                count++;
+
+        printk(KERN_INFO "(%d early reservations) ==> bootmem\n", count);
+        for (i = 0; i < count; i++) {
+                struct early_res *r = &early_res[i];
+                printk(KERN_INFO "  #%d [%010llx - %010llx] %16s", i,
+                        r->start, r->end, r->name);
+                final_start = max(start, r->start);
+                final_end = min(end, r->end);
+                if (final_start >= final_end) {
+                        printk(KERN_CONT "\n");
+                        continue;
+                }
+                printk(KERN_CONT " ==> [%010llx - %010llx]\n",
+                        final_start, final_end);
+                reserve_bootmem_generic(final_start, final_end - final_start,
+                                BOOTMEM_DEFAULT);
+        }
+}
+
+/* Check for already reserved areas */
+static inline int __init bad_addr(u64 *addrp, u64 size, u64 align)
+{
+        int i;
+        u64 addr = *addrp;
+        int changed = 0;
+        struct early_res *r;
+again:
+        i = find_overlapped_early(addr, addr + size);
+        r = &early_res[i];
+        if (i < MAX_EARLY_RES && r->end) {
+                *addrp = addr = round_up(r->end, align);
+                changed = 1;
+                goto again;
+        }
+        return changed;
+}
+
+/* Check for already reserved areas */
+static inline int __init bad_addr_size(u64 *addrp, u64 *sizep, u64 align)
+{
+        int i;
+        u64 addr = *addrp, last;
+        u64 size = *sizep;
+        int changed = 0;
+again:
+        last = addr + size;
+        for (i = 0; i < MAX_EARLY_RES && early_res[i].end; i++) {
+                struct early_res *r = &early_res[i];
+                if (last > r->start && addr < r->start) {
+                        size = r->start - addr;
+                        changed = 1;
+                        goto again;
+                }
+                if (last > r->end && addr < r->end) {
+                        addr = round_up(r->end, align);
+                        size = last - addr;
+                        changed = 1;
+                        goto again;
+                }
+                if (last <= r->end && addr >= r->start) {
+                        (*sizep)++;
+                        return 0;
+                }
+        }
+        if (changed) {
+                *addrp = addr;
+                *sizep = size;
+        }
+        return changed;
+}
+
+/*
+ * Find a free area with specified alignment in a specific range.
+ */
+u64 __init find_e820_area(u64 start, u64 end, u64 size, u64 align)
+{
+        int i;
+
+        for (i = 0; i < e820.nr_map; i++) {
+                struct e820entry *ei = &e820.map[i];
+                u64 addr, last;
+                u64 ei_last;
+
+                if (ei->type != E820_RAM)
+                        continue;
+                addr = round_up(ei->addr, align);
+                ei_last = ei->addr + ei->size;
+                if (addr < start)
+                        addr = round_up(start, align);
+                if (addr >= ei_last)
+                        continue;
+                while (bad_addr(&addr, size, align) && addr+size <= ei_last)
+                        ;
+                last = addr + size;
+                if (last > ei_last)
+                        continue;
+                if (last > end)
+                        continue;
+                return addr;
+        }
+        return -1ULL;
+}
+
+/*
+ * Find next free range after *start
+ */
+u64 __init find_e820_area_size(u64 start, u64 *sizep, u64 align)
+{
+        int i;
+
+        for (i = 0; i < e820.nr_map; i++) {
+                struct e820entry *ei = &e820.map[i];
+                u64 addr, last;
+                u64 ei_last;
+
+                if (ei->type != E820_RAM)
+                        continue;
+                addr = round_up(ei->addr, align);
+                ei_last = ei->addr + ei->size;
+                if (addr < start)
+                        addr = round_up(start, align);
+                if (addr >= ei_last)
+                        continue;
+                *sizep = ei_last - addr;
+                while (bad_addr_size(&addr, sizep, align) &&
+                        addr + *sizep <= ei_last)
+                        ;
+                last = addr + *sizep;
+                if (last > ei_last)
+                        continue;
+                return addr;
+        }
+        return -1UL;
+
+}
+
+/*
+ * pre allocated 4k and reserved it in e820
+ */
+u64 __init early_reserve_e820(u64 startt, u64 sizet, u64 align)
+{
+        u64 size = 0;
+        u64 addr;
+        u64 start;
+
+        start = startt;
+        while (size < sizet)
+                start = find_e820_area_size(start, &size, align);
+
+        if (size < sizet)
+                return 0;
+
+        addr = round_down(start + size - sizet, align);
+        e820_update_range(addr, sizet, E820_RAM, E820_RESERVED);
+        e820_update_range_saved(addr, sizet, E820_RAM, E820_RESERVED);
+        printk(KERN_INFO "update e820 for early_reserve_e820\n");
+        update_e820();
+        update_e820_saved();
+
+        return addr;
+}
+
+#ifdef CONFIG_X86_32
+# ifdef CONFIG_X86_PAE
+#  define MAX_ARCH_PFN          (1ULL<<(36-PAGE_SHIFT))
+# else
+#  define MAX_ARCH_PFN          (1ULL<<(32-PAGE_SHIFT))
+# endif
+#else /* CONFIG_X86_32 */
+# define MAX_ARCH_PFN MAXMEM>>PAGE_SHIFT
+#endif
+
+/*
+ * Find the highest page frame number we have available
+ */
+static unsigned long __init e820_end_pfn(unsigned long limit_pfn, unsigned type)
+{
+        int i;
+        unsigned long last_pfn = 0;
+        unsigned long max_arch_pfn = MAX_ARCH_PFN;
+
+        for (i = 0; i < e820.nr_map; i++) {
+                struct e820entry *ei = &e820.map[i];
+                unsigned long start_pfn;
+                unsigned long end_pfn;
+
+                if (ei->type != type)
+                        continue;
+
+                start_pfn = ei->addr >> PAGE_SHIFT;
+                end_pfn = (ei->addr + ei->size) >> PAGE_SHIFT;
+
+                if (start_pfn >= limit_pfn)
+                        continue;
+                if (end_pfn > limit_pfn) {
+                        last_pfn = limit_pfn;
+                        break;
+                }
+                if (end_pfn > last_pfn)
+                        last_pfn = end_pfn;
+        }
+
+        if (last_pfn > max_arch_pfn)
+                last_pfn = max_arch_pfn;
+
+        printk(KERN_INFO "last_pfn = %#lx max_arch_pfn = %#lx\n",
+                         last_pfn, max_arch_pfn);
+        return last_pfn;
+}
+unsigned long __init e820_end_of_ram_pfn(void)
+{
+        return e820_end_pfn(MAX_ARCH_PFN, E820_RAM);
+}
+
+unsigned long __init e820_end_of_low_ram_pfn(void)
+{
+        return e820_end_pfn(1UL<<(32 - PAGE_SHIFT), E820_RAM);
+}
+/*
+ * Finds an active region in the address range from start_pfn to last_pfn and
+ * returns its range in ei_startpfn and ei_endpfn for the e820 entry.
+ */
+int __init e820_find_active_region(const struct e820entry *ei,
+                                  unsigned long start_pfn,
+                                  unsigned long last_pfn,
+                                  unsigned long *ei_startpfn,
+                                  unsigned long *ei_endpfn)
+{
+        u64 align = PAGE_SIZE;
+
+        *ei_startpfn = round_up(ei->addr, align) >> PAGE_SHIFT;
+        *ei_endpfn = round_down(ei->addr + ei->size, align) >> PAGE_SHIFT;
+
+        /* Skip map entries smaller than a page */
+        if (*ei_startpfn >= *ei_endpfn)
+                return 0;
+
+        /* Skip if map is outside the node */
+        if (ei->type != E820_RAM || *ei_endpfn <= start_pfn ||
+                                    *ei_startpfn >= last_pfn)
+                return 0;
+
+        /* Check for overlaps */
+        if (*ei_startpfn < start_pfn)
+                *ei_startpfn = start_pfn;
+        if (*ei_endpfn > last_pfn)
+                *ei_endpfn = last_pfn;
+
+        return 1;
+}
+
+/* Walk the e820 map and register active regions within a node */
+void __init e820_register_active_regions(int nid, unsigned long start_pfn,
+                                         unsigned long last_pfn)
+{
+        unsigned long ei_startpfn;
+        unsigned long ei_endpfn;
+        int i;
+
+        for (i = 0; i < e820.nr_map; i++)
+                if (e820_find_active_region(&e820.map[i],
+                                            start_pfn, last_pfn,
+                                            &ei_startpfn, &ei_endpfn))
+                        add_active_range(nid, ei_startpfn, ei_endpfn);
+}
+
+/*
+ * Find the hole size (in bytes) in the memory range.
+ * @start: starting address of the memory range to scan
+ * @end: ending address of the memory range to scan
+ */
+u64 __init e820_hole_size(u64 start, u64 end)
+{
+        unsigned long start_pfn = start >> PAGE_SHIFT;
+        unsigned long last_pfn = end >> PAGE_SHIFT;
+        unsigned long ei_startpfn, ei_endpfn, ram = 0;
+        int i;
+
+        for (i = 0; i < e820.nr_map; i++) {
+                if (e820_find_active_region(&e820.map[i],
+                                            start_pfn, last_pfn,
+                                            &ei_startpfn, &ei_endpfn))
+                        ram += ei_endpfn - ei_startpfn;
+        }
+        return end - start - ((u64)ram << PAGE_SHIFT);
+}
+
+static void early_panic(char *msg)
+{
+        early_printk(msg);
+        panic(msg);
+}
+
+static int userdef __initdata;
+
+/* "mem=nopentium" disables the 4MB page tables. */
+static int __init parse_memopt(char *p)
+{
+        u64 mem_size;
+
+        if (!p)
+                return -EINVAL;
+
+#ifdef CONFIG_X86_32
+        if (!strcmp(p, "nopentium")) {
+                setup_clear_cpu_cap(X86_FEATURE_PSE);
+                return 0;
+        }
+#endif
+
+        userdef = 1;
+        mem_size = memparse(p, &p);
+        e820_remove_range(mem_size, ULLONG_MAX - mem_size, E820_RAM, 1);
+
+        return 0;
+}
+early_param("mem", parse_memopt);
+
+static int __init parse_memmap_opt(char *p)
+{
+        char *oldp;
+        u64 start_at, mem_size;
+
+        if (!p)
+                return -EINVAL;
+
+        if (!strcmp(p, "exactmap")) {
+#ifdef CONFIG_CRASH_DUMP
+                /*
+                 * If we are doing a crash dump, we still need to know
+                 * the real mem size before original memory map is
+                 * reset.
+                 */
+                saved_max_pfn = e820_end_of_ram_pfn();
+#endif
+                e820.nr_map = 0;
+                userdef = 1;
+                return 0;
+        }
+
+        oldp = p;
+        mem_size = memparse(p, &p);
+        if (p == oldp)
+                return -EINVAL;
+
+        userdef = 1;
+        if (*p == '@') {
+                start_at = memparse(p+1, &p);
+                e820_add_region(start_at, mem_size, E820_RAM);
+        } else if (*p == '#') {
+                start_at = memparse(p+1, &p);
+                e820_add_region(start_at, mem_size, E820_ACPI);
+        } else if (*p == '$') {
+                start_at = memparse(p+1, &p);
+                e820_add_region(start_at, mem_size, E820_RESERVED);
+        } else
+                e820_remove_range(mem_size, ULLONG_MAX - mem_size, E820_RAM, 1);
+
+        return *p == '\0' ? 0 : -EINVAL;
+}
+early_param("memmap", parse_memmap_opt);
+
+void __init finish_e820_parsing(void)
+{
+        if (userdef) {
+                int nr = e820.nr_map;
+
+                if (sanitize_e820_map(e820.map, ARRAY_SIZE(e820.map), &nr) < 0)
+                        early_panic("Invalid user supplied memory map");
+                e820.nr_map = nr;
+
+                printk(KERN_INFO "user-defined physical RAM map:\n");
+                e820_print_map("user");
+        }
+}
+
+static inline const char *e820_type_to_string(int e820_type)
+{
+        switch (e820_type) {
+        case E820_RESERVED_KERN:
+        case E820_RAM:  return "System RAM";
+        case E820_ACPI: return "ACPI Tables";
+        case E820_NVS:  return "ACPI Non-volatile Storage";
+        default:        return "reserved";
+        }
+}
+
+/*
+ * Mark e820 reserved areas as busy for the resource manager.
+ */
+void __init e820_reserve_resources(void)
+{
+        int i;
+        struct resource *res;
+        u64 end;
+
+        res = alloc_bootmem_low(sizeof(struct resource) * e820.nr_map);
+        for (i = 0; i < e820.nr_map; i++) {
+                end = e820.map[i].addr + e820.map[i].size - 1;
+#ifndef CONFIG_RESOURCES_64BIT
+                if (end > 0x100000000ULL) {
+                        res++;
+                        continue;
+                }
+#endif
+                res->name = e820_type_to_string(e820.map[i].type);
+                res->start = e820.map[i].addr;
+                res->end = end;
+
+                res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
+                insert_resource(&iomem_resource, res);
+                res++;
+        }
+
+        for (i = 0; i < e820_saved.nr_map; i++) {
+                struct e820entry *entry = &e820_saved.map[i];
+                firmware_map_add_early(entry->addr,
+                        entry->addr + entry->size - 1,
+                        e820_type_to_string(entry->type));
+        }
+}
+
+/*
+ * Non-standard memory setup can be specified via this quirk:
+ */
+char * (*arch_memory_setup_quirk)(void);
+
+char *__init default_machine_specific_memory_setup(void)
+{
+        char *who = "BIOS-e820";
+        int new_nr;
+        /*
+         * Try to copy the BIOS-supplied E820-map.
+         *
+         * Otherwise fake a memory map; one section from 0k->640k,
+         * the next section from 1mb->appropriate_mem_k
+         */
+        new_nr = boot_params.e820_entries;
+        sanitize_e820_map(boot_params.e820_map,
+                        ARRAY_SIZE(boot_params.e820_map),
+                        &new_nr);
+        boot_params.e820_entries = new_nr;
+        if (append_e820_map(boot_params.e820_map, boot_params.e820_entries)
+          < 0) {
+                u64 mem_size;
+
+                /* compare results from other methods and take the greater */
+                if (boot_params.alt_mem_k
+                    < boot_params.screen_info.ext_mem_k) {
+                        mem_size = boot_params.screen_info.ext_mem_k;
+                        who = "BIOS-88";
+                } else {
+                        mem_size = boot_params.alt_mem_k;
+                        who = "BIOS-e801";
+                }
+
+                e820.nr_map = 0;
+                e820_add_region(0, LOWMEMSIZE(), E820_RAM);
+                e820_add_region(HIGH_MEMORY, mem_size << 10, E820_RAM);
+        }
+
+        /* In case someone cares... */
+        return who;
+}
+
+char *__init __attribute__((weak)) machine_specific_memory_setup(void)
+{
+        if (arch_memory_setup_quirk) {
+                char *who = arch_memory_setup_quirk();
+
+                if (who)
+                        return who;
+        }
+        return default_machine_specific_memory_setup();
+}
+
+/* Overridden in paravirt.c if CONFIG_PARAVIRT */
+char * __init __attribute__((weak)) memory_setup(void)
+{
+        return machine_specific_memory_setup();
+}
+
+void __init setup_memory_map(void)
+{
+        char *who;
+
+        who = memory_setup();
+        memcpy(&e820_saved, &e820, sizeof(struct e820map));
+        printk(KERN_INFO "BIOS-provided physical RAM map:\n");
+        e820_print_map(who);
+}
+
+#ifdef CONFIG_X86_64
+int __init arch_get_ram_range(int slot, u64 *addr, u64 *size)
+{
+        int i;
+
+        if (slot < 0 || slot >= e820.nr_map)
+                return -1;
+        for (i = slot; i < e820.nr_map; i++) {
+                if (e820.map[i].type != E820_RAM)
+                        continue;
+                break;
+        }
+        if (i == e820.nr_map || e820.map[i].addr > (max_pfn << PAGE_SHIFT))
+                return -1;
+        *addr = e820.map[i].addr;
+        *size = min_t(u64, e820.map[i].size + e820.map[i].addr,
+                max_pfn << PAGE_SHIFT) - *addr;
+        return i + 1;
+}
+#endif
diff --git a/arch/x86/kernel/e820_32.c b/arch/x86/kernel/e820_32.c
deleted file mode 100644
index ed733e7cf4e6..000000000000
--- a/arch/x86/kernel/e820_32.c
+++ /dev/null
@@ -1,775 +0,0 @@
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/bootmem.h>
-#include <linux/ioport.h>
-#include <linux/string.h>
-#include <linux/kexec.h>
-#include <linux/module.h>
-#include <linux/mm.h>
-#include <linux/pfn.h>
-#include <linux/uaccess.h>
-#include <linux/suspend.h>
-
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <asm/e820.h>
-#include <asm/setup.h>
-
-struct e820map e820;
-struct change_member {
-        struct e820entry *pbios; /* pointer to original bios entry */
-        unsigned long long addr; /* address for this change point */
-};
-static struct change_member change_point_list[2*E820MAX] __initdata;
-static struct change_member *change_point[2*E820MAX] __initdata;
-static struct e820entry *overlap_list[E820MAX] __initdata;
-static struct e820entry new_bios[E820MAX] __initdata;
-/* For PCI or other memory-mapped resources */
-unsigned long pci_mem_start = 0x10000000;
-#ifdef CONFIG_PCI
-EXPORT_SYMBOL(pci_mem_start);
-#endif
-extern int user_defined_memmap;
-
-static struct resource system_rom_resource = {
-        .name   = "System ROM",
-        .start  = 0xf0000,
-        .end    = 0xfffff,
-        .flags  = IORESOURCE_BUSY | IORESOURCE_READONLY | IORESOURCE_MEM
-};
-
-static struct resource extension_rom_resource = {
-        .name   = "Extension ROM",
-        .start  = 0xe0000,
-        .end    = 0xeffff,
-        .flags  = IORESOURCE_BUSY | IORESOURCE_READONLY | IORESOURCE_MEM
-};
-
-static struct resource adapter_rom_resources[] = { {
-        .name   = "Adapter ROM",
-        .start  = 0xc8000,
-        .end    = 0,
-        .flags  = IORESOURCE_BUSY | IORESOURCE_READONLY | IORESOURCE_MEM
-}, {
-        .name   = "Adapter ROM",
-        .start  = 0,
-        .end    = 0,
-        .flags  = IORESOURCE_BUSY | IORESOURCE_READONLY | IORESOURCE_MEM
-}, {
-        .name   = "Adapter ROM",
-        .start  = 0,
-        .end    = 0,
-        .flags  = IORESOURCE_BUSY | IORESOURCE_READONLY | IORESOURCE_MEM
-}, {
-        .name   = "Adapter ROM",
-        .start  = 0,
-        .end    = 0,
-        .flags  = IORESOURCE_BUSY | IORESOURCE_READONLY | IORESOURCE_MEM
-}, {
-        .name   = "Adapter ROM",
-        .start  = 0,
-        .end    = 0,
-        .flags  = IORESOURCE_BUSY | IORESOURCE_READONLY | IORESOURCE_MEM
-}, {
-        .name   = "Adapter ROM",
-        .start  = 0,
-        .end    = 0,
-        .flags  = IORESOURCE_BUSY | IORESOURCE_READONLY | IORESOURCE_MEM
-} };
-
-static struct resource video_rom_resource = {
-        .name   = "Video ROM",
-        .start  = 0xc0000,
-        .end    = 0xc7fff,
-        .flags  = IORESOURCE_BUSY | IORESOURCE_READONLY | IORESOURCE_MEM
-};
-
-#define ROMSIGNATURE 0xaa55
-
-static int __init romsignature(const unsigned char *rom)
-{
-        const unsigned short * const ptr = (const unsigned short *)rom;
-        unsigned short sig;
-
-        return probe_kernel_address(ptr, sig) == 0 && sig == ROMSIGNATURE;
-}
-
-static int __init romchecksum(const unsigned char *rom, unsigned long length)
-{
-        unsigned char sum, c;
-
-        for (sum = 0; length && probe_kernel_address(rom++, c) == 0; length--)
-                sum += c;
-        return !length && !sum;
-}
-
-static void __init probe_roms(void)
-{
-        const unsigned char *rom;
-        unsigned long start, length, upper;
-        unsigned char c;
-        int i;
-
-        /* video rom */
-        upper = adapter_rom_resources[0].start;
-        for (start = video_rom_resource.start; start < upper; start += 2048) {
-                rom = isa_bus_to_virt(start);
-                if (!romsignature(rom))
-                        continue;
-
-                video_rom_resource.start = start;
-
-                if (probe_kernel_address(rom + 2, c) != 0)
-                        continue;
-
-                /* 0 < length <= 0x7f * 512, historically */
-                length = c * 512;
-
-                /* if checksum okay, trust length byte */
-                if (length && romchecksum(rom, length))
-                        video_rom_resource.end = start + length - 1;
-
-                request_resource(&iomem_resource, &video_rom_resource);
-                break;
-        }
-
-        start = (video_rom_resource.end + 1 + 2047) & ~2047UL;
-        if (start < upper)
-                start = upper;
-
-        /* system rom */
-        request_resource(&iomem_resource, &system_rom_resource);
-        upper = system_rom_resource.start;
-
-        /* check for extension rom (ignore length byte!) */
-        rom = isa_bus_to_virt(extension_rom_resource.start);
-        if (romsignature(rom)) {
-                length = extension_rom_resource.end - extension_rom_resource.start + 1;
-                if (romchecksum(rom, length)) {
-                        request_resource(&iomem_resource, &extension_rom_resource);
-                        upper = extension_rom_resource.start;
-                }
-        }
-
-        /* check for adapter roms on 2k boundaries */
-        for (i = 0; i < ARRAY_SIZE(adapter_rom_resources) && start < upper; start += 2048) {
-                rom = isa_bus_to_virt(start);
-                if (!romsignature(rom))
-                        continue;
-
-                if (probe_kernel_address(rom + 2, c) != 0)
-                        continue;
-
-                /* 0 < length <= 0x7f * 512, historically */
-                length = c * 512;
-
-                /* but accept any length that fits if checksum okay */
-                if (!length || start + length > upper || !romchecksum(rom, length))
-                        continue;
-
-                adapter_rom_resources[i].start = start;
-                adapter_rom_resources[i].end = start + length - 1;
-                request_resource(&iomem_resource, &adapter_rom_resources[i]);
-
-                start = adapter_rom_resources[i++].end & ~2047UL;
-        }
-}
-
-/*
- * Request address space for all standard RAM and ROM resources
- * and also for regions reported as reserved by the e820.
- */
-void __init init_iomem_resources(struct resource *code_resource,
-                struct resource *data_resource,
-                struct resource *bss_resource)
-{
-        int i;
-
-        probe_roms();
-        for (i = 0; i < e820.nr_map; i++) {
-                struct resource *res;
-#ifndef CONFIG_RESOURCES_64BIT
-                if (e820.map[i].addr + e820.map[i].size > 0x100000000ULL)
-                        continue;
-#endif
-                res = kzalloc(sizeof(struct resource), GFP_ATOMIC);
-                switch (e820.map[i].type) {
-                case E820_RAM:  res->name = "System RAM"; break;
-                case E820_ACPI: res->name = "ACPI Tables"; break;
-                case E820_NVS:  res->name = "ACPI Non-volatile Storage"; break;
-                default:        res->name = "reserved";
-                }
-                res->start = e820.map[i].addr;
-                res->end = res->start + e820.map[i].size - 1;
-                res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
-                if (request_resource(&iomem_resource, res)) {
-                        kfree(res);
-                        continue;
-                }
-                if (e820.map[i].type == E820_RAM) {
-                        /*
-                         *  We don't know which RAM region contains kernel data,
-                         *  so we try it repeatedly and let the resource manager
-                         *  test it.
-                         */
-                        request_resource(res, code_resource);
-                        request_resource(res, data_resource);
-                        request_resource(res, bss_resource);
-#ifdef CONFIG_KEXEC
-                        if (crashk_res.start != crashk_res.end)
-                                request_resource(res, &crashk_res);
-#endif
-                }
-        }
-}
-
-#if defined(CONFIG_PM) && defined(CONFIG_HIBERNATION)
-/**
- * e820_mark_nosave_regions - Find the ranges of physical addresses that do not
- * correspond to e820 RAM areas and mark the corresponding pages as nosave for
- * hibernation.
- *
- * This function requires the e820 map to be sorted and without any
- * overlapping entries and assumes the first e820 area to be RAM.
- */
-void __init e820_mark_nosave_regions(void)
-{
-        int i;
-        unsigned long pfn;
-
-        pfn = PFN_DOWN(e820.map[0].addr + e820.map[0].size);
-        for (i = 1; i < e820.nr_map; i++) {
-                struct e820entry *ei = &e820.map[i];
-
-                if (pfn < PFN_UP(ei->addr))
-                        register_nosave_region(pfn, PFN_UP(ei->addr));
-
-                pfn = PFN_DOWN(ei->addr + ei->size);
-                if (ei->type != E820_RAM)
-                        register_nosave_region(PFN_UP(ei->addr), pfn);
-
-                if (pfn >= max_low_pfn)
-                        break;
-        }
-}
-#endif
-
-void __init add_memory_region(unsigned long long start,
-                              unsigned long long size, int type)
-{
-        int x;
-
-        x = e820.nr_map;
-
-        if (x == E820MAX) {
-                printk(KERN_ERR "Ooops! Too many entries in the memory map!\n");
-                return;
-        }
-
-        e820.map[x].addr = start;
-        e820.map[x].size = size;
-        e820.map[x].type = type;
-        e820.nr_map++;
-} /* add_memory_region */
-
-/*
- * Sanitize the BIOS e820 map.
- *
- * Some e820 responses include overlapping entries.  The following
- * replaces the original e820 map with a new one, removing overlaps.
- *
- */
-int __init sanitize_e820_map(struct e820entry * biosmap, char * pnr_map)
-{
-        struct change_member *change_tmp;
-        unsigned long current_type, last_type;
-        unsigned long long last_addr;
-        int chgidx, still_changing;
-        int overlap_entries;
-        int new_bios_entry;
-        int old_nr, new_nr, chg_nr;
-        int i;
-
-        /*
-                Visually we're performing the following (1,2,3,4 = memory types)...
-
-                Sample memory map (w/overlaps):
-                   ____22__________________
-                   ______________________4_
-                   ____1111________________
-                   _44_____________________
-                   11111111________________
-                   ____________________33__
-                   ___________44___________
-                   __________33333_________
-                   ______________22________
-                   ___________________2222_
-                   _________111111111______
-                   _____________________11_
-                   _________________4______
-
-                Sanitized equivalent (no overlap):
-                   1_______________________
-                   _44_____________________
-                   ___1____________________
-                   ____22__________________
-                   ______11________________
-                   _________1______________
-                   __________3_____________
-                   ___________44___________
-                   _____________33_________
-                   _______________2________
-                   ________________1_______
-                   _________________4______
-                   ___________________2____
-                   ____________________33__
-                   ______________________4_
-        */
-        /* if there's only one memory region, don't bother */
-        if (*pnr_map < 2) {
-                return -1;
-        }
-
-        old_nr = *pnr_map;
-
-        /* bail out if we find any unreasonable addresses in bios map */
-        for (i=0; i<old_nr; i++)
-                if (biosmap[i].addr + biosmap[i].size < biosmap[i].addr) {
-                        return -1;
-                }
-
-        /* create pointers for initial change-point information (for sorting) */
-        for (i=0; i < 2*old_nr; i++)
-                change_point[i] = &change_point_list[i];
-
-        /* record all known change-points (starting and ending addresses),
-           omitting those that are for empty memory regions */
-        chgidx = 0;
-        for (i=0; i < old_nr; i++)      {
-                if (biosmap[i].size != 0) {
-                        change_point[chgidx]->addr = biosmap[i].addr;
-                        change_point[chgidx++]->pbios = &biosmap[i];
-                        change_point[chgidx]->addr = biosmap[i].addr + biosmap[i].size;
-                        change_point[chgidx++]->pbios = &biosmap[i];
-                }
-        }
-        chg_nr = chgidx;        /* true number of change-points */
-
-        /* sort change-point list by memory addresses (low -> high) */
-        still_changing = 1;
-        while (still_changing)  {
-                still_changing = 0;
-                for (i=1; i < chg_nr; i++)  {
-                        /* if <current_addr> > <last_addr>, swap */
-                        /* or, if current=<start_addr> & last=<end_addr>, swap */
-                        if ((change_point[i]->addr < change_point[i-1]->addr) ||
-                                ((change_point[i]->addr == change_point[i-1]->addr) &&
-                                 (change_point[i]->addr == change_point[i]->pbios->addr) &&
-                                 (change_point[i-1]->addr != change_point[i-1]->pbios->addr))
-                           )
-                        {
-                                change_tmp = change_point[i];
-                                change_point[i] = change_point[i-1];
-                                change_point[i-1] = change_tmp;
-                                still_changing=1;
-                        }
-                }
-        }
-
-        /* create a new bios memory map, removing overlaps */
-        overlap_entries=0;       /* number of entries in the overlap table */
-        new_bios_entry=0;        /* index for creating new bios map entries */
-        last_type = 0;           /* start with undefined memory type */
-        last_addr = 0;           /* start with 0 as last starting address */
-        /* loop through change-points, determining affect on the new bios map */
-        for (chgidx=0; chgidx < chg_nr; chgidx++)
-        {
-                /* keep track of all overlapping bios entries */
-                if (change_point[chgidx]->addr == change_point[chgidx]->pbios->addr)
-                {
-                        /* add map entry to overlap list (> 1 entry implies an overlap) */
-                        overlap_list[overlap_entries++]=change_point[chgidx]->pbios;
-                }
-                else
-                {
-                        /* remove entry from list (order independent, so swap with last) */
-                        for (i=0; i<overlap_entries; i++)
-                        {
-                                if (overlap_list[i] == change_point[chgidx]->pbios)
-                                        overlap_list[i] = overlap_list[overlap_entries-1];
-                        }
-                        overlap_entries--;
-                }
-                /* if there are overlapping entries, decide which "type" to use */
-                /* (larger value takes precedence -- 1=usable, 2,3,4,4+=unusable) */
-                current_type = 0;
-                for (i=0; i<overlap_entries; i++)
-                        if (overlap_list[i]->type > current_type)
-                                current_type = overlap_list[i]->type;
-                /* continue building up new bios map based on this information */
-                if (current_type != last_type)  {
-                        if (last_type != 0)      {
-                                new_bios[new_bios_entry].size =
-                                        change_point[chgidx]->addr - last_addr;
-                                /* move forward only if the new size was non-zero */
-                                if (new_bios[new_bios_entry].size != 0)
-                                        if (++new_bios_entry >= E820MAX)
-                                                break;  /* no more space left for new bios entries */
-                        }
-                        if (current_type != 0)  {
-                                new_bios[new_bios_entry].addr = change_point[chgidx]->addr;
-                                new_bios[new_bios_entry].type = current_type;
-                                last_addr=change_point[chgidx]->addr;
-                        }
-                        last_type = current_type;
-                }
-        }
-        new_nr = new_bios_entry;   /* retain count for new bios entries */
-
-        /* copy new bios mapping into original location */
-        memcpy(biosmap, new_bios, new_nr*sizeof(struct e820entry));
-        *pnr_map = new_nr;
-
-        return 0;
-}
-
-/*
- * Copy the BIOS e820 map into a safe place.
- *
- * Sanity-check it while we're at it..
- *
- * If we're lucky and live on a modern system, the setup code
- * will have given us a memory map that we can use to properly
- * set up memory.  If we aren't, we'll fake a memory map.
- *
- * We check to see that the memory map contains at least 2 elements
- * before we'll use it, because the detection code in setup.S may
- * not be perfect and most every PC known to man has two memory
- * regions: one from 0 to 640k, and one from 1mb up.  (The IBM
- * thinkpad 560x, for example, does not cooperate with the memory
- * detection code.)
- */
-int __init copy_e820_map(struct e820entry *biosmap, int nr_map)
-{
-        /* Only one memory region (or negative)? Ignore it */
-        if (nr_map < 2)
-                return -1;
-
-        do {
-                u64 start = biosmap->addr;
-                u64 size = biosmap->size;
-                u64 end = start + size;
-                u32 type = biosmap->type;
-
-                /* Overflow in 64 bits? Ignore the memory map. */
-                if (start > end)
-                        return -1;
-
-                add_memory_region(start, size, type);
-        } while (biosmap++, --nr_map);
-
-        return 0;
-}
-
-/*
- * Find the highest page frame number we have available
- */
-void __init propagate_e820_map(void)
-{
-        int i;
-
-        max_pfn = 0;
-
-        for (i = 0; i < e820.nr_map; i++) {
-                unsigned long start, end;
-                /* RAM? */
-                if (e820.map[i].type != E820_RAM)
-                        continue;
-                start = PFN_UP(e820.map[i].addr);
-                end = PFN_DOWN(e820.map[i].addr + e820.map[i].size);
-                if (start >= end)
-                        continue;
-                if (end > max_pfn)
-                        max_pfn = end;
-                memory_present(0, start, end);
-        }
-}
-
-/*
- * Register fully available low RAM pages with the bootmem allocator.
- */
-void __init register_bootmem_low_pages(unsigned long max_low_pfn)
-{
-        int i;
-
-        for (i = 0; i < e820.nr_map; i++) {
-                unsigned long curr_pfn, last_pfn, size;
-                /*
-                 * Reserve usable low memory
-                 */
-                if (e820.map[i].type != E820_RAM)
-                        continue;
-                /*
-                 * We are rounding up the start address of usable memory:
-                 */
-                curr_pfn = PFN_UP(e820.map[i].addr);
-                if (curr_pfn >= max_low_pfn)
-                        continue;
-                /*
-                 * ... and at the end of the usable range downwards:
-                 */
-                last_pfn = PFN_DOWN(e820.map[i].addr + e820.map[i].size);
-
-                if (last_pfn > max_low_pfn)
-                        last_pfn = max_low_pfn;
-
-                /*
-                 * .. finally, did all the rounding and playing
-                 * around just make the area go away?
-                 */
-                if (last_pfn <= curr_pfn)
-                        continue;
-
-                size = last_pfn - curr_pfn;
-                free_bootmem(PFN_PHYS(curr_pfn), PFN_PHYS(size));
-        }
-}
-
-void __init e820_register_memory(void)
-{
-        unsigned long gapstart, gapsize, round;
-        unsigned long long last;
-        int i;
-
-        /*
-         * Search for the biggest gap in the low 32 bits of the e820
-         * memory space.
-         */
-        last = 0x100000000ull;
-        gapstart = 0x10000000;
-        gapsize = 0x400000;
-        i = e820.nr_map;
-        while (--i >= 0) {
-                unsigned long long start = e820.map[i].addr;
-                unsigned long long end = start + e820.map[i].size;
-
-                /*
-                 * Since "last" is at most 4GB, we know we'll
-                 * fit in 32 bits if this condition is true
-                 */
-                if (last > end) {
-                        unsigned long gap = last - end;
-
-                        if (gap > gapsize) {
-                                gapsize = gap;
-                                gapstart = end;
-                        }
-                }
-                if (start < last)
-                        last = start;
-        }
-
-        /*
-         * See how much we want to round up: start off with
-         * rounding to the next 1MB area.
-         */
-        round = 0x100000;
-        while ((gapsize >> 4) > round)
-                round += round;
-        /* Fun with two's complement */
-        pci_mem_start = (gapstart + round) & -round;
-
-        printk("Allocating PCI resources starting at %08lx (gap: %08lx:%08lx)\n",
-                pci_mem_start, gapstart, gapsize);
-}
-
-void __init print_memory_map(char *who)
-{
-        int i;
-
-        for (i = 0; i < e820.nr_map; i++) {
-                printk(" %s: %016Lx - %016Lx ", who,
-                        e820.map[i].addr,
-                        e820.map[i].addr + e820.map[i].size);
-                switch (e820.map[i].type) {
-                case E820_RAM:  printk("(usable)\n");
-                                break;
-                case E820_RESERVED:
-                                printk("(reserved)\n");
-                                break;
-                case E820_ACPI:
-                                printk("(ACPI data)\n");
-                                break;
-                case E820_NVS:
-                                printk("(ACPI NVS)\n");
-                                break;
-                default:        printk("type %u\n", e820.map[i].type);
-                                break;
-                }
-        }
-}
-
-void __init limit_regions(unsigned long long size)
-{
-        unsigned long long current_addr;
-        int i;
-
-        print_memory_map("limit_regions start");
-        for (i = 0; i < e820.nr_map; i++) {
-                current_addr = e820.map[i].addr + e820.map[i].size;
-                if (current_addr < size)
-                        continue;
-
-                if (e820.map[i].type != E820_RAM)
-                        continue;
-
-                if (e820.map[i].addr >= size) {
-                        /*
-                         * This region starts past the end of the
-                         * requested size, skip it completely.
-                         */
-                        e820.nr_map = i;
-                } else {
-                        e820.nr_map = i + 1;
-                        e820.map[i].size -= current_addr - size;
-                }
-                print_memory_map("limit_regions endfor");
-                return;
-        }
-        print_memory_map("limit_regions endfunc");
-}
-
-/*
- * This function checks if any part of the range <start,end> is mapped
- * with type.
- */
-int
-e820_any_mapped(u64 start, u64 end, unsigned type)
-{
-        int i;
-        for (i = 0; i < e820.nr_map; i++) {
-                const struct e820entry *ei = &e820.map[i];
-                if (type && ei->type != type)
-                        continue;
-                if (ei->addr >= end || ei->addr + ei->size <= start)
-                        continue;
-                return 1;
-        }
-        return 0;
-}
-EXPORT_SYMBOL_GPL(e820_any_mapped);
-
- /*
-  * This function checks if the entire range <start,end> is mapped with type.
-  *
-  * Note: this function only works correct if the e820 table is sorted and
-  * not-overlapping, which is the case
-  */
-int __init
-e820_all_mapped(unsigned long s, unsigned long e, unsigned type)
-{
-        u64 start = s;
-        u64 end = e;
-        int i;
-        for (i = 0; i < e820.nr_map; i++) {
-                struct e820entry *ei = &e820.map[i];
-                if (type && ei->type != type)
-                        continue;
-                /* is the region (part) in overlap with the current region ?*/
-                if (ei->addr >= end || ei->addr + ei->size <= start)
-                        continue;
-                /* if the region is at the beginning of <start,end> we move
-                 * start to the end of the region since it's ok until there
-                 */
-                if (ei->addr <= start)
-                        start = ei->addr + ei->size;
-                /* if start is now at or beyond end, we're done, full
-                 * coverage */
-                if (start >= end)
-                        return 1; /* we're done */
-        }
-        return 0;
-}
-
-static int __init parse_memmap(char *arg)
-{
-        if (!arg)
-                return -EINVAL;
-
-        if (strcmp(arg, "exactmap") == 0) {
-#ifdef CONFIG_CRASH_DUMP
-                /* If we are doing a crash dump, we
-                 * still need to know the real mem
-                 * size before original memory map is
-                 * reset.
-                 */
-                propagate_e820_map();
-                saved_max_pfn = max_pfn;
-#endif
-                e820.nr_map = 0;
-                user_defined_memmap = 1;
-        } else {
-                /* If the user specifies memory size, we
-                 * limit the BIOS-provided memory map to
-                 * that size. exactmap can be used to specify
-                 * the exact map. mem=number can be used to
-                 * trim the existing memory map.
-                 */
-                unsigned long long start_at, mem_size;
-
-                mem_size = memparse(arg, &arg);
-                if (*arg == '@') {
-                        start_at = memparse(arg+1, &arg);
-                        add_memory_region(start_at, mem_size, E820_RAM);
-                } else if (*arg == '#') {
-                        start_at = memparse(arg+1, &arg);
-                        add_memory_region(start_at, mem_size, E820_ACPI);
-                } else if (*arg == '$') {
-                        start_at = memparse(arg+1, &arg);
-                        add_memory_region(start_at, mem_size, E820_RESERVED);
-                } else {
-                        limit_regions(mem_size);
-                        user_defined_memmap = 1;
-                }
-        }
-        return 0;
-}
-early_param("memmap", parse_memmap);
-void __init update_memory_range(u64 start, u64 size, unsigned old_type,
-                                unsigned new_type)
-{
-        int i;
-
-        BUG_ON(old_type == new_type);
-
-        for (i = 0; i < e820.nr_map; i++) {
-                struct e820entry *ei = &e820.map[i];
-                u64 final_start, final_end;
-                if (ei->type != old_type)
-                        continue;
-                /* totally covered? */
-                if (ei->addr >= start && ei->size <= size) {
-                        ei->type = new_type;
-                        continue;
-                }
-                /* partially covered */
-                final_start = max(start, ei->addr);
-                final_end = min(start + size, ei->addr + ei->size);
-                if (final_start >= final_end)
-                        continue;
-                add_memory_region(final_start, final_end - final_start,
-                                         new_type);
-        }
-}
-void __init update_e820(void)
-{
-        u8 nr_map;
-
-        nr_map = e820.nr_map;
-        if (sanitize_e820_map(e820.map, &nr_map))
-                return;
-        e820.nr_map = nr_map;
-        printk(KERN_INFO "modified physical RAM map:\n");
-        print_memory_map("modified");
-}
diff --git a/arch/x86/kernel/e820_64.c b/arch/x86/kernel/e820_64.c
deleted file mode 100644
index 124480c0008d..000000000000
--- a/arch/x86/kernel/e820_64.c
+++ /dev/null
@@ -1,952 +0,0 @@
-/*
- * Handle the memory map.
- * The functions here do the job until bootmem takes over.
- *
- *  Getting sanitize_e820_map() in sync with i386 version by applying change:
- *  -  Provisions for empty E820 memory regions (reported by certain BIOSes).
- *     Alex Achenbach <xela@slit.de>, December 2002.
- *  Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
- *
- */
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/bootmem.h>
-#include <linux/ioport.h>
-#include <linux/string.h>
-#include <linux/kexec.h>
-#include <linux/module.h>
-#include <linux/mm.h>
-#include <linux/suspend.h>
-#include <linux/pfn.h>
-
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <asm/e820.h>
-#include <asm/proto.h>
-#include <asm/setup.h>
-#include <asm/sections.h>
-#include <asm/kdebug.h>
-#include <asm/trampoline.h>
-
-struct e820map e820;
-
-/*
- * PFN of last memory page.
- */
-unsigned long end_pfn;
-
-/*
- * end_pfn only includes RAM, while max_pfn_mapped includes all e820 entries.
- * The direct mapping extends to max_pfn_mapped, so that we can directly access
- * apertures, ACPI and other tables without having to play with fixmaps.
- */
-unsigned long max_pfn_mapped;
-
-/*
- * Last pfn which the user wants to use.
- */
-static unsigned long __initdata end_user_pfn = MAXMEM>>PAGE_SHIFT;
-
-/*
- * Early reserved memory areas.
- */
-#define MAX_EARLY_RES 20
-
-struct early_res {
-        unsigned long start, end;
-        char name[16];
-};
-static struct early_res early_res[MAX_EARLY_RES] __initdata = {
-        { 0, PAGE_SIZE, "BIOS data page" },                     /* BIOS data page */
-#ifdef CONFIG_X86_TRAMPOLINE
-        { TRAMPOLINE_BASE, TRAMPOLINE_BASE + 2 * PAGE_SIZE, "TRAMPOLINE" },
-#endif
-        {}
-};
-
-void __init reserve_early(unsigned long start, unsigned long end, char *name)
-{
-        int i;
-        struct early_res *r;
-        for (i = 0; i < MAX_EARLY_RES && early_res[i].end; i++) {
-                r = &early_res[i];
-                if (end > r->start && start < r->end)
-                        panic("Overlapping early reservations %lx-%lx %s to %lx-%lx %s\n",
-                              start, end - 1, name?name:"", r->start, r->end - 1, r->name);
-        }
-        if (i >= MAX_EARLY_RES)
-                panic("Too many early reservations");
-        r = &early_res[i];
-        r->start = start;
-        r->end = end;
-        if (name)
-                strncpy(r->name, name, sizeof(r->name) - 1);
-}
-
-void __init free_early(unsigned long start, unsigned long end)
-{
-        struct early_res *r;
-        int i, j;
-
-        for (i = 0; i < MAX_EARLY_RES && early_res[i].end; i++) {
-                r = &early_res[i];
-                if (start == r->start && end == r->end)
-                        break;
-        }
-        if (i >= MAX_EARLY_RES || !early_res[i].end)
-                panic("free_early on not reserved area: %lx-%lx!", start, end);
-
-        for (j = i + 1; j < MAX_EARLY_RES && early_res[j].end; j++)
-                ;
-
-        memmove(&early_res[i], &early_res[i + 1],
-               (j - 1 - i) * sizeof(struct early_res));
-
-        early_res[j - 1].end = 0;
-}
-
-void __init early_res_to_bootmem(unsigned long start, unsigned long end)
-{
-        int i;
-        unsigned long final_start, final_end;
-        for (i = 0; i < MAX_EARLY_RES && early_res[i].end; i++) {
-                struct early_res *r = &early_res[i];
-                final_start = max(start, r->start);
-                final_end = min(end, r->end);
-                if (final_start >= final_end)
-                        continue;
-                printk(KERN_INFO "  early res: %d [%lx-%lx] %s\n", i,
-                        final_start, final_end - 1, r->name);
-                reserve_bootmem_generic(final_start, final_end - final_start);
-        }
-}
-
-/* Check for already reserved areas */
-static inline int __init
-bad_addr(unsigned long *addrp, unsigned long size, unsigned long align)
-{
-        int i;
-        unsigned long addr = *addrp, last;
-        int changed = 0;
-again:
-        last = addr + size;
-        for (i = 0; i < MAX_EARLY_RES && early_res[i].end; i++) {
-                struct early_res *r = &early_res[i];
-                if (last >= r->start && addr < r->end) {
-                        *addrp = addr = round_up(r->end, align);
-                        changed = 1;
-                        goto again;
-                }
-        }
-        return changed;
-}
-
-/* Check for already reserved areas */
-static inline int __init
-bad_addr_size(unsigned long *addrp, unsigned long *sizep, unsigned long align)
-{
-        int i;
-        unsigned long addr = *addrp, last;
-        unsigned long size = *sizep;
-        int changed = 0;
-again:
-        last = addr + size;
-        for (i = 0; i < MAX_EARLY_RES && early_res[i].end; i++) {
-                struct early_res *r = &early_res[i];
-                if (last > r->start && addr < r->start) {
-                        size = r->start - addr;
-                        changed = 1;
-                        goto again;
-                }
-                if (last > r->end && addr < r->end) {
-                        addr = round_up(r->end, align);
-                        size = last - addr;
-                        changed = 1;
-                        goto again;
-                }
-                if (last <= r->end && addr >= r->start) {
-                        (*sizep)++;
-                        return 0;
-                }
-        }
-        if (changed) {
-                *addrp = addr;
-                *sizep = size;
-        }
-        return changed;
-}
-/*
- * This function checks if any part of the range <start,end> is mapped
- * with type.
- */
-int
-e820_any_mapped(unsigned long start, unsigned long end, unsigned type)
-{
-        int i;
-
-        for (i = 0; i < e820.nr_map; i++) {
-                struct e820entry *ei = &e820.map[i];
-
-                if (type && ei->type != type)
-                        continue;
-                if (ei->addr >= end || ei->addr + ei->size <= start)
-                        continue;
-                return 1;
-        }
-        return 0;
-}
-EXPORT_SYMBOL_GPL(e820_any_mapped);
-
-/*
- * This function checks if the entire range <start,end> is mapped with type.
- *
- * Note: this function only works correct if the e820 table is sorted and
- * not-overlapping, which is the case
- */
-int __init e820_all_mapped(unsigned long start, unsigned long end,
-                           unsigned type)
-{
-        int i;
-
-        for (i = 0; i < e820.nr_map; i++) {
-                struct e820entry *ei = &e820.map[i];
-
-                if (type && ei->type != type)
-                        continue;
-                /* is the region (part) in overlap with the current region ?*/
-                if (ei->addr >= end || ei->addr + ei->size <= start)
-                        continue;
-
-                /* if the region is at the beginning of <start,end> we move
-                 * start to the end of the region since it's ok until there
-                 */
-                if (ei->addr <= start)
-                        start = ei->addr + ei->size;
-                /*
-                 * if start is now at or beyond end, we're done, full
-                 * coverage
-                 */
-                if (start >= end)
-                        return 1;
-        }
-        return 0;
-}
-
-/*
- * Find a free area with specified alignment in a specific range.
- */
-unsigned long __init find_e820_area(unsigned long start, unsigned long end,
-                                    unsigned long size, unsigned long align)
-{
-        int i;
-
-        for (i = 0; i < e820.nr_map; i++) {
-                struct e820entry *ei = &e820.map[i];
-                unsigned long addr, last;
-                unsigned long ei_last;
-
-                if (ei->type != E820_RAM)
-                        continue;
-                addr = round_up(ei->addr, align);
-                ei_last = ei->addr + ei->size;
-                if (addr < start)
-                        addr = round_up(start, align);
-                if (addr >= ei_last)
-                        continue;
-                while (bad_addr(&addr, size, align) && addr+size <= ei_last)
-                        ;
-                last = addr + size;
-                if (last > ei_last)
-                        continue;
-                if (last > end)
-                        continue;
-                return addr;
-        }
-        return -1UL;
-}
-
-/*
- * Find next free range after *start
- */
-unsigned long __init find_e820_area_size(unsigned long start,
-                                         unsigned long *sizep,
-                                         unsigned long align)
-{
-        int i;
-
-        for (i = 0; i < e820.nr_map; i++) {
-                struct e820entry *ei = &e820.map[i];
-                unsigned long addr, last;
-                unsigned long ei_last;
-
-                if (ei->type != E820_RAM)
-                        continue;
-                addr = round_up(ei->addr, align);
-                ei_last = ei->addr + ei->size;
-                if (addr < start)
-                        addr = round_up(start, align);
-                if (addr >= ei_last)
-                        continue;
-                *sizep = ei_last - addr;
-                while (bad_addr_size(&addr, sizep, align) &&
-                        addr + *sizep <= ei_last)
-                        ;
-                last = addr + *sizep;
-                if (last > ei_last)
-                        continue;
-                return addr;
-        }
-        return -1UL;
-
-}
-/*
- * Find the highest page frame number we have available
- */
-unsigned long __init e820_end_of_ram(void)
-{
-        unsigned long end_pfn;
-
-        end_pfn = find_max_pfn_with_active_regions();
-
-        if (end_pfn > max_pfn_mapped)
-                max_pfn_mapped = end_pfn;
-        if (max_pfn_mapped > MAXMEM>>PAGE_SHIFT)
-                max_pfn_mapped = MAXMEM>>PAGE_SHIFT;
-        if (end_pfn > end_user_pfn)
-                end_pfn = end_user_pfn;
-        if (end_pfn > max_pfn_mapped)
-                end_pfn = max_pfn_mapped;
-
-        printk(KERN_INFO "max_pfn_mapped = %lu\n", max_pfn_mapped);
-        return end_pfn;
-}
-
-/*
- * Mark e820 reserved areas as busy for the resource manager.
- */
-void __init e820_reserve_resources(void)
-{
-        int i;
-        struct resource *res;
-
-        res = alloc_bootmem_low(sizeof(struct resource) * e820.nr_map);
-        for (i = 0; i < e820.nr_map; i++) {
-                switch (e820.map[i].type) {
-                case E820_RAM:  res->name = "System RAM"; break;
-                case E820_ACPI: res->name = "ACPI Tables"; break;
-                case E820_NVS:  res->name = "ACPI Non-volatile Storage"; break;
-                default:        res->name = "reserved";
-                }
-                res->start = e820.map[i].addr;
-                res->end = res->start + e820.map[i].size - 1;
-                res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
-                insert_resource(&iomem_resource, res);
-                res++;
-        }
-}
-
-/*
- * Find the ranges of physical addresses that do not correspond to
- * e820 RAM areas and mark the corresponding pages as nosave for software
- * suspend and suspend to RAM.
- *
- * This function requires the e820 map to be sorted and without any
- * overlapping entries and assumes the first e820 area to be RAM.
- */
-void __init e820_mark_nosave_regions(void)
-{
-        int i;
-        unsigned long paddr;
-
-        paddr = round_down(e820.map[0].addr + e820.map[0].size, PAGE_SIZE);
-        for (i = 1; i < e820.nr_map; i++) {
-                struct e820entry *ei = &e820.map[i];
-
-                if (paddr < ei->addr)
-                        register_nosave_region(PFN_DOWN(paddr),
-                                                PFN_UP(ei->addr));
-
-                paddr = round_down(ei->addr + ei->size, PAGE_SIZE);
-                if (ei->type != E820_RAM)
-                        register_nosave_region(PFN_UP(ei->addr),
-                                                PFN_DOWN(paddr));
-
-                if (paddr >= (end_pfn << PAGE_SHIFT))
-                        break;
-        }
-}
-
-/*
- * Finds an active region in the address range from start_pfn to end_pfn and
- * returns its range in ei_startpfn and ei_endpfn for the e820 entry.
- */
-static int __init e820_find_active_region(const struct e820entry *ei,
-                                          unsigned long start_pfn,
-                                          unsigned long end_pfn,
-                                          unsigned long *ei_startpfn,
-                                          unsigned long *ei_endpfn)
-{
-        *ei_startpfn = round_up(ei->addr, PAGE_SIZE) >> PAGE_SHIFT;
-        *ei_endpfn = round_down(ei->addr + ei->size, PAGE_SIZE) >> PAGE_SHIFT;
-
-        /* Skip map entries smaller than a page */
-        if (*ei_startpfn >= *ei_endpfn)
-                return 0;
-
-        /* Check if max_pfn_mapped should be updated */
-        if (ei->type != E820_RAM && *ei_endpfn > max_pfn_mapped)
-                max_pfn_mapped = *ei_endpfn;
-
-        /* Skip if map is outside the node */
-        if (ei->type != E820_RAM || *ei_endpfn <= start_pfn ||
-                                    *ei_startpfn >= end_pfn)
-                return 0;
-
-        /* Check for overlaps */
-        if (*ei_startpfn < start_pfn)
-                *ei_startpfn = start_pfn;
-        if (*ei_endpfn > end_pfn)
-                *ei_endpfn = end_pfn;
-
-        /* Obey end_user_pfn to save on memmap */
-        if (*ei_startpfn >= end_user_pfn)
-                return 0;
-        if (*ei_endpfn > end_user_pfn)
-                *ei_endpfn = end_user_pfn;
-
-        return 1;
-}
-
-/* Walk the e820 map and register active regions within a node */
-void __init
-e820_register_active_regions(int nid, unsigned long start_pfn,
-                                                        unsigned long end_pfn)
-{
-        unsigned long ei_startpfn;
-        unsigned long ei_endpfn;
-        int i;
-
-        for (i = 0; i < e820.nr_map; i++)
-                if (e820_find_active_region(&e820.map[i],
-                                            start_pfn, end_pfn,
-                                            &ei_startpfn, &ei_endpfn))
-                        add_active_range(nid, ei_startpfn, ei_endpfn);
-}
-
-/*
- * Add a memory region to the kernel e820 map.
- */
-void __init add_memory_region(unsigned long start, unsigned long size, int type)
-{
-        int x = e820.nr_map;
-
-        if (x == E820MAX) {
-                printk(KERN_ERR "Ooops! Too many entries in the memory map!\n");
-                return;
-        }
-
-        e820.map[x].addr = start;
-        e820.map[x].size = size;
-        e820.map[x].type = type;
-        e820.nr_map++;
-}
-
-/*
- * Find the hole size (in bytes) in the memory range.
- * @start: starting address of the memory range to scan
- * @end: ending address of the memory range to scan
- */
-unsigned long __init e820_hole_size(unsigned long start, unsigned long end)
-{
-        unsigned long start_pfn = start >> PAGE_SHIFT;
-        unsigned long end_pfn = end >> PAGE_SHIFT;
-        unsigned long ei_startpfn, ei_endpfn, ram = 0;
-        int i;
-
-        for (i = 0; i < e820.nr_map; i++) {
-                if (e820_find_active_region(&e820.map[i],
-                                            start_pfn, end_pfn,
-                                            &ei_startpfn, &ei_endpfn))
-                        ram += ei_endpfn - ei_startpfn;
-        }
-        return end - start - (ram << PAGE_SHIFT);
-}
-
-static void __init e820_print_map(char *who)
-{
-        int i;
-
-        for (i = 0; i < e820.nr_map; i++) {
-                printk(KERN_INFO " %s: %016Lx - %016Lx ", who,
-                       (unsigned long long) e820.map[i].addr,
-                       (unsigned long long)
-                       (e820.map[i].addr + e820.map[i].size));
-                switch (e820.map[i].type) {
-                case E820_RAM:
-                        printk(KERN_CONT "(usable)\n");
-                        break;
-                case E820_RESERVED:
-                        printk(KERN_CONT "(reserved)\n");
-                        break;
-                case E820_ACPI:
-                        printk(KERN_CONT "(ACPI data)\n");
-                        break;
-                case E820_NVS:
-                        printk(KERN_CONT "(ACPI NVS)\n");
-                        break;
-                default:
-                        printk(KERN_CONT "type %u\n", e820.map[i].type);
-                        break;
-                }
-        }
-}
-
-/*
- * Sanitize the BIOS e820 map.
- *
- * Some e820 responses include overlapping entries. The following
- * replaces the original e820 map with a new one, removing overlaps.
- *
- */
-static int __init sanitize_e820_map(struct e820entry *biosmap, char *pnr_map)
-{
-        struct change_member {
-                struct e820entry *pbios; /* pointer to original bios entry */
-                unsigned long long addr; /* address for this change point */
-        };
-        static struct change_member change_point_list[2*E820MAX] __initdata;
-        static struct change_member *change_point[2*E820MAX] __initdata;
-        static struct e820entry *overlap_list[E820MAX] __initdata;
-        static struct e820entry new_bios[E820MAX] __initdata;
-        struct change_member *change_tmp;
-        unsigned long current_type, last_type;
-        unsigned long long last_addr;
-        int chgidx, still_changing;
-        int overlap_entries;
-        int new_bios_entry;
-        int old_nr, new_nr, chg_nr;
-        int i;
-
-        /*
-                Visually we're performing the following
-                (1,2,3,4 = memory types)...
-
-                Sample memory map (w/overlaps):
-                   ____22__________________
-                   ______________________4_
-                   ____1111________________
-                   _44_____________________
-                   11111111________________
-                   ____________________33__
-                   ___________44___________
-                   __________33333_________
-                   ______________22________
-                   ___________________2222_
-                   _________111111111______
-                   _____________________11_
-                   _________________4______
-
-                Sanitized equivalent (no overlap):
-                   1_______________________
-                   _44_____________________
-                   ___1____________________
-                   ____22__________________
-                   ______11________________
-                   _________1______________
-                   __________3_____________
-                   ___________44___________
-                   _____________33_________
-                   _______________2________
-                   ________________1_______
-                   _________________4______
-                   ___________________2____
-                   ____________________33__
-                   ______________________4_
-        */
-
-        /* if there's only one memory region, don't bother */
-        if (*pnr_map < 2)
-                return -1;
-
-        old_nr = *pnr_map;
-
-        /* bail out if we find any unreasonable addresses in bios map */
-        for (i = 0; i < old_nr; i++)
-                if (biosmap[i].addr + biosmap[i].size < biosmap[i].addr)
-                        return -1;
-
-        /* create pointers for initial change-point information (for sorting) */
-        for (i = 0; i < 2 * old_nr; i++)
-                change_point[i] = &change_point_list[i];
-
-        /* record all known change-points (starting and ending addresses),
-           omitting those that are for empty memory regions */
-        chgidx = 0;
-        for (i = 0; i < old_nr; i++)    {
-                if (biosmap[i].size != 0) {
-                        change_point[chgidx]->addr = biosmap[i].addr;
-                        change_point[chgidx++]->pbios = &biosmap[i];
-                        change_point[chgidx]->addr = biosmap[i].addr +
-                                biosmap[i].size;
-                        change_point[chgidx++]->pbios = &biosmap[i];
-                }
-        }
-        chg_nr = chgidx;
-
-        /* sort change-point list by memory addresses (low -> high) */
-        still_changing = 1;
-        while (still_changing)  {
-                still_changing = 0;
-                for (i = 1; i < chg_nr; i++)  {
-                        unsigned long long curaddr, lastaddr;
-                        unsigned long long curpbaddr, lastpbaddr;
-
-                        curaddr = change_point[i]->addr;
-                        lastaddr = change_point[i - 1]->addr;
-                        curpbaddr = change_point[i]->pbios->addr;
-                        lastpbaddr = change_point[i - 1]->pbios->addr;
-
-                        /*
-                         * swap entries, when:
-                         *
-                         * curaddr > lastaddr or
-                         * curaddr == lastaddr and curaddr == curpbaddr and
-                         * lastaddr != lastpbaddr
-                         */
-                        if (curaddr < lastaddr ||
-                            (curaddr == lastaddr && curaddr == curpbaddr &&
-                             lastaddr != lastpbaddr)) {
-                                change_tmp = change_point[i];
-                                change_point[i] = change_point[i-1];
-                                change_point[i-1] = change_tmp;
-                                still_changing = 1;
-                        }
-                }
-        }
-
-        /* create a new bios memory map, removing overlaps */
-        overlap_entries = 0;     /* number of entries in the overlap table */
-        new_bios_entry = 0;      /* index for creating new bios map entries */
-        last_type = 0;           /* start with undefined memory type */
-        last_addr = 0;           /* start with 0 as last starting address */
-
-        /* loop through change-points, determining affect on the new bios map */
-        for (chgidx = 0; chgidx < chg_nr; chgidx++) {
-                /* keep track of all overlapping bios entries */
-                if (change_point[chgidx]->addr ==
-                    change_point[chgidx]->pbios->addr) {
-                        /*
-                         * add map entry to overlap list (> 1 entry
-                         * implies an overlap)
-                         */
-                        overlap_list[overlap_entries++] =
-                                change_point[chgidx]->pbios;
-                } else {
-                        /*
-                         * remove entry from list (order independent,
-                         * so swap with last)
-                         */
-                        for (i = 0; i < overlap_entries; i++) {
-                                if (overlap_list[i] ==
-                                    change_point[chgidx]->pbios)
-                                        overlap_list[i] =
-                                                overlap_list[overlap_entries-1];
-                        }
-                        overlap_entries--;
-                }
-                /*
-                 * if there are overlapping entries, decide which
-                 * "type" to use (larger value takes precedence --
-                 * 1=usable, 2,3,4,4+=unusable)
-                 */
-                current_type = 0;
-                for (i = 0; i < overlap_entries; i++)
-                        if (overlap_list[i]->type > current_type)
-                                current_type = overlap_list[i]->type;
-                /*
-                 * continue building up new bios map based on this
-                 * information
-                 */
-                if (current_type != last_type)  {
-                        if (last_type != 0)      {
-                                new_bios[new_bios_entry].size =
-                                        change_point[chgidx]->addr - last_addr;
-                                /*
-                                 * move forward only if the new size
-                                 * was non-zero
-                                 */
-                                if (new_bios[new_bios_entry].size != 0)
-                                        /*
-                                         * no more space left for new
-                                         * bios entries ?
-                                         */
-                                        if (++new_bios_entry >= E820MAX)
-                                                break;
-                        }
-                        if (current_type != 0)  {
-                                new_bios[new_bios_entry].addr =
-                                        change_point[chgidx]->addr;
-                                new_bios[new_bios_entry].type = current_type;
-                                last_addr = change_point[chgidx]->addr;
-                        }
-                        last_type = current_type;
-                }
-        }
-        /* retain count for new bios entries */
-        new_nr = new_bios_entry;
-
-        /* copy new bios mapping into original location */
-        memcpy(biosmap, new_bios, new_nr * sizeof(struct e820entry));
-        *pnr_map = new_nr;
-
-        return 0;
-}
-
-/*
- * Copy the BIOS e820 map into a safe place.
- *
- * Sanity-check it while we're at it..
- *
- * If we're lucky and live on a modern system, the setup code
- * will have given us a memory map that we can use to properly
- * set up memory.  If we aren't, we'll fake a memory map.
- */
-static int __init copy_e820_map(struct e820entry *biosmap, int nr_map)
-{
-        /* Only one memory region (or negative)? Ignore it */
-        if (nr_map < 2)
-                return -1;
-
-        do {
-                u64 start = biosmap->addr;
-                u64 size = biosmap->size;
-                u64 end = start + size;
-                u32 type = biosmap->type;
-
-                /* Overflow in 64 bits? Ignore the memory map. */
-                if (start > end)
-                        return -1;
-
-                add_memory_region(start, size, type);
-        } while (biosmap++, --nr_map);
-        return 0;
-}
-
-static void early_panic(char *msg)
-{
-        early_printk(msg);
-        panic(msg);
-}
-
-/* We're not void only for x86 32-bit compat */
-char * __init machine_specific_memory_setup(void)
-{
-        char *who = "BIOS-e820";
-        /*
-         * Try to copy the BIOS-supplied E820-map.
-         *
-         * Otherwise fake a memory map; one section from 0k->640k,
-         * the next section from 1mb->appropriate_mem_k
-         */
-        sanitize_e820_map(boot_params.e820_map, &boot_params.e820_entries);
-        if (copy_e820_map(boot_params.e820_map, boot_params.e820_entries) < 0)
-                early_panic("Cannot find a valid memory map");
-        printk(KERN_INFO "BIOS-provided physical RAM map:\n");
-        e820_print_map(who);
-
-        /* In case someone cares... */
-        return who;
-}
-
-static int __init parse_memopt(char *p)
-{
-        if (!p)
-                return -EINVAL;
-        end_user_pfn = memparse(p, &p);
-        end_user_pfn >>= PAGE_SHIFT;
-        return 0;
-}
-early_param("mem", parse_memopt);
-
-static int userdef __initdata;
-
-static int __init parse_memmap_opt(char *p)
-{
-        char *oldp;
-        unsigned long long start_at, mem_size;
-
-        if (!strcmp(p, "exactmap")) {
-#ifdef CONFIG_CRASH_DUMP
-                /*
-                 * If we are doing a crash dump, we still need to know
-                 * the real mem size before original memory map is
-                 * reset.
-                 */
-                e820_register_active_regions(0, 0, -1UL);
-                saved_max_pfn = e820_end_of_ram();
-                remove_all_active_ranges();
-#endif
-                max_pfn_mapped = 0;
-                e820.nr_map = 0;
-                userdef = 1;
-                return 0;
-        }
-
-        oldp = p;
-        mem_size = memparse(p, &p);
-        if (p == oldp)
-                return -EINVAL;
-
-        userdef = 1;
-        if (*p == '@') {
-                start_at = memparse(p+1, &p);
-                add_memory_region(start_at, mem_size, E820_RAM);
-        } else if (*p == '#') {
-                start_at = memparse(p+1, &p);
-                add_memory_region(start_at, mem_size, E820_ACPI);
-        } else if (*p == '$') {
-                start_at = memparse(p+1, &p);
-                add_memory_region(start_at, mem_size, E820_RESERVED);
-        } else {
-                end_user_pfn = (mem_size >> PAGE_SHIFT);
-        }
-        return *p == '\0' ? 0 : -EINVAL;
-}
-early_param("memmap", parse_memmap_opt);
-
-void __init finish_e820_parsing(void)
-{
-        if (userdef) {
-                char nr = e820.nr_map;
-
-                if (sanitize_e820_map(e820.map, &nr) < 0)
-                        early_panic("Invalid user supplied memory map");
-                e820.nr_map = nr;
-
-                printk(KERN_INFO "user-defined physical RAM map:\n");
-                e820_print_map("user");
-        }
-}
-
-void __init update_memory_range(u64 start, u64 size, unsigned old_type,
-                                unsigned new_type)
-{
-        int i;
-
-        BUG_ON(old_type == new_type);
-
-        for (i = 0; i < e820.nr_map; i++) {
-                struct e820entry *ei = &e820.map[i];
-                u64 final_start, final_end;
-                if (ei->type != old_type)
-                        continue;
-                /* totally covered? */
-                if (ei->addr >= start && ei->size <= size) {
-                        ei->type = new_type;
-                        continue;
-                }
-                /* partially covered */
-                final_start = max(start, ei->addr);
-                final_end = min(start + size, ei->addr + ei->size);
-                if (final_start >= final_end)
-                        continue;
-                add_memory_region(final_start, final_end - final_start,
-                                         new_type);
-        }
-}
-
-void __init update_e820(void)
-{
-        u8 nr_map;
-
-        nr_map = e820.nr_map;
-        if (sanitize_e820_map(e820.map, &nr_map))
-                return;
-        e820.nr_map = nr_map;
-        printk(KERN_INFO "modified physical RAM map:\n");
-        e820_print_map("modified");
-}
-
-unsigned long pci_mem_start = 0xaeedbabe;
-EXPORT_SYMBOL(pci_mem_start);
-
-/*
- * Search for the biggest gap in the low 32 bits of the e820
- * memory space.  We pass this space to PCI to assign MMIO resources
- * for hotplug or unconfigured devices in.
- * Hopefully the BIOS let enough space left.
- */
-__init void e820_setup_gap(void)
-{
-        unsigned long gapstart, gapsize, round;
-        unsigned long last;
-        int i;
-        int found = 0;
-
-        last = 0x100000000ull;
-        gapstart = 0x10000000;
-        gapsize = 0x400000;
-        i = e820.nr_map;
-        while (--i >= 0) {
-                unsigned long long start = e820.map[i].addr;
-                unsigned long long end = start + e820.map[i].size;
-
-                /*
-                 * Since "last" is at most 4GB, we know we'll
-                 * fit in 32 bits if this condition is true
-                 */
-                if (last > end) {
-                        unsigned long gap = last - end;
-
-                        if (gap > gapsize) {
-                                gapsize = gap;
-                                gapstart = end;
-                                found = 1;
-                        }
-                }
-                if (start < last)
-                        last = start;
-        }
-
-        if (!found) {
-                gapstart = (end_pfn << PAGE_SHIFT) + 1024*1024;
-                printk(KERN_ERR "PCI: Warning: Cannot find a gap in the 32bit "
-                       "address range\n"
-                       KERN_ERR "PCI: Unassigned devices with 32bit resource "
-                       "registers may break!\n");
-        }
-
-        /*
-         * See how much we want to round up: start off with
-         * rounding to the next 1MB area.
-         */
-        round = 0x100000;
-        while ((gapsize >> 4) > round)
-                round += round;
-        /* Fun with two's complement */
-        pci_mem_start = (gapstart + round) & -round;
-
-        printk(KERN_INFO
-               "Allocating PCI resources starting at %lx (gap: %lx:%lx)\n",
-               pci_mem_start, gapstart, gapsize);
-}
-
-int __init arch_get_ram_range(int slot, u64 *addr, u64 *size)
-{
-        int i;
-
-        if (slot < 0 || slot >= e820.nr_map)
-                return -1;
-        for (i = slot; i < e820.nr_map; i++) {
-                if (e820.map[i].type != E820_RAM)
-                        continue;
-                break;
-        }
-        if (i == e820.nr_map || e820.map[i].addr > (max_pfn << PAGE_SHIFT))
-                return -1;
-        *addr = e820.map[i].addr;
-        *size = min_t(u64, e820.map[i].size + e820.map[i].addr,
-                max_pfn << PAGE_SHIFT) - *addr;
-        return i + 1;
-}
diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index 9f51e1ea9e82..a4665f37cfc5 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -50,7 +50,7 @@ static void __init fix_hypertransport_config(int num, int slot, int func)
 static void __init via_bugs(int  num, int slot, int func)
 {
 #ifdef CONFIG_GART_IOMMU
-        if ((end_pfn > MAX_DMA32_PFN ||  force_iommu) &&
+        if ((max_pfn > MAX_DMA32_PFN ||  force_iommu) &&
             !gart_iommu_aperture_allowed) {
                 printk(KERN_INFO
                        "Looks like a VIA chipset. Disabling IOMMU."
@@ -98,17 +98,6 @@ static void __init nvidia_bugs(int num, int slot, int func)
 
 }
 
-static void __init ati_bugs(int num, int slot, int func)
-{
-#ifdef CONFIG_X86_IO_APIC
-        if (timer_over_8254 == 1) {
-                timer_over_8254 = 0;
-                printk(KERN_INFO
-                "ATI board detected. Disabling timer routing over 8254.\n");
-        }
-#endif
-}
-
 #define QFLAG_APPLY_ONCE        0x1
 #define QFLAG_APPLIED           0x2
 #define QFLAG_DONE              (QFLAG_APPLY_ONCE|QFLAG_APPLIED)
@@ -126,8 +115,6 @@ static struct chipset early_qrk[] __initdata = {
           PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, nvidia_bugs },
         { PCI_VENDOR_ID_VIA, PCI_ANY_ID,
           PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, via_bugs },
-        { PCI_VENDOR_ID_ATI, PCI_ANY_ID,
-          PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, ati_bugs },
         { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB,
           PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, fix_hypertransport_config },
         {}
diff --git a/arch/x86/kernel/early_printk.c b/arch/x86/kernel/early_printk.c
index 643fd861b724..ff9e7350da54 100644
--- a/arch/x86/kernel/early_printk.c
+++ b/arch/x86/kernel/early_printk.c
@@ -196,7 +196,7 @@ static struct console simnow_console = {
 static struct console *early_console = &early_vga_console;
 static int early_console_initialized;
 
-void early_printk(const char *fmt, ...)
+asmlinkage void early_printk(const char *fmt, ...)
 {
         char buf[512];
         int n;
diff --git a/arch/x86/kernel/efi.c b/arch/x86/kernel/efi.c
index 77d424cf68b3..06cc8d4254b1 100644
--- a/arch/x86/kernel/efi.c
+++ b/arch/x86/kernel/efi.c
@@ -64,6 +64,17 @@ static int __init setup_noefi(char *arg)
 }
 early_param("noefi", setup_noefi);
 
+int add_efi_memmap;
+EXPORT_SYMBOL(add_efi_memmap);
+
+static int __init setup_add_efi_memmap(char *arg)
+{
+        add_efi_memmap = 1;
+        return 0;
+}
+early_param("add_efi_memmap", setup_add_efi_memmap);
+
+
 static efi_status_t virt_efi_get_time(efi_time_t *tm, efi_time_cap_t *tc)
 {
         return efi_call_virt2(get_time, tm, tc);
@@ -213,6 +224,50 @@ unsigned long efi_get_time(void)
                       eft.minute, eft.second);
 }
 
+/*
+ * Tell the kernel about the EFI memory map.  This might include
+ * more than the max 128 entries that can fit in the e820 legacy
+ * (zeropage) memory map.
+ */
+
+static void __init do_add_efi_memmap(void)
+{
+        void *p;
+
+        for (p = memmap.map; p < memmap.map_end; p += memmap.desc_size) {
+                efi_memory_desc_t *md = p;
+                unsigned long long start = md->phys_addr;
+                unsigned long long size = md->num_pages << EFI_PAGE_SHIFT;
+                int e820_type;
+
+                if (md->attribute & EFI_MEMORY_WB)
+                        e820_type = E820_RAM;
+                else
+                        e820_type = E820_RESERVED;
+                e820_add_region(start, size, e820_type);
+        }
+        sanitize_e820_map(e820.map, ARRAY_SIZE(e820.map), &e820.nr_map);
+}
+
+void __init efi_reserve_early(void)
+{
+        unsigned long pmap;
+
+#ifdef CONFIG_X86_32
+        pmap = boot_params.efi_info.efi_memmap;
+#else
+        pmap = (boot_params.efi_info.efi_memmap |
+                ((__u64)boot_params.efi_info.efi_memmap_hi<<32));
+#endif
+        memmap.phys_map = (void *)pmap;
+        memmap.nr_map = boot_params.efi_info.efi_memmap_size /
+                boot_params.efi_info.efi_memdesc_size;
+        memmap.desc_version = boot_params.efi_info.efi_memdesc_version;
+        memmap.desc_size = boot_params.efi_info.efi_memdesc_size;
+        reserve_early(pmap, pmap + memmap.nr_map * memmap.desc_size,
+                      "EFI memmap");
+}
+
 #if EFI_DEBUG
 static void __init print_efi_memmap(void)
 {
@@ -244,19 +299,11 @@ void __init efi_init(void)
 
 #ifdef CONFIG_X86_32
         efi_phys.systab = (efi_system_table_t *)boot_params.efi_info.efi_systab;
-        memmap.phys_map = (void *)boot_params.efi_info.efi_memmap;
 #else
         efi_phys.systab = (efi_system_table_t *)
                 (boot_params.efi_info.efi_systab |
                  ((__u64)boot_params.efi_info.efi_systab_hi<<32));
-        memmap.phys_map = (void *)
-                (boot_params.efi_info.efi_memmap |
-                 ((__u64)boot_params.efi_info.efi_memmap_hi<<32));
 #endif
-        memmap.nr_map = boot_params.efi_info.efi_memmap_size /
-                boot_params.efi_info.efi_memdesc_size;
-        memmap.desc_version = boot_params.efi_info.efi_memdesc_version;
-        memmap.desc_size = boot_params.efi_info.efi_memdesc_size;
 
         efi.systab = early_ioremap((unsigned long)efi_phys.systab,
                                    sizeof(efi_system_table_t));
@@ -370,6 +417,8 @@ void __init efi_init(void)
         if (memmap.desc_size != sizeof(efi_memory_desc_t))
                 printk(KERN_WARNING "Kernel-defined memdesc"
                        "doesn't match the one from EFI!\n");
+        if (add_efi_memmap)
+                do_add_efi_memmap();
 
         /* Setup for EFI runtime service */
         reboot_type = BOOT_EFI;
@@ -424,7 +473,7 @@ void __init efi_enter_virtual_mode(void)
                 size = md->num_pages << EFI_PAGE_SHIFT;
                 end = md->phys_addr + size;
 
-                if (PFN_UP(end) <= max_pfn_mapped)
+                if (PFN_UP(end) <= max_low_pfn_mapped)
                         va = __va(md->phys_addr);
                 else
                         va = efi_ioremap(md->phys_addr, size);
diff --git a/arch/x86/kernel/efi_64.c b/arch/x86/kernel/efi_64.c
index d0060fdcccac..652c5287215f 100644
--- a/arch/x86/kernel/efi_64.c
+++ b/arch/x86/kernel/efi_64.c
@@ -97,13 +97,7 @@ void __init efi_call_phys_epilog(void)
         early_runtime_code_mapping_set_exec(0);
 }
 
-void __init efi_reserve_bootmem(void)
-{
-        reserve_bootmem_generic((unsigned long)memmap.phys_map,
-                                memmap.nr_map * memmap.desc_size);
-}
-
-void __iomem * __init efi_ioremap(unsigned long phys_addr, unsigned long size)
+void __iomem *__init efi_ioremap(unsigned long phys_addr, unsigned long size)
 {
         static unsigned pages_mapped __initdata;
         unsigned i, pages;
diff --git a/arch/x86/kernel/entry_32.S b/arch/x86/kernel/entry_32.S
index c778e4fa55a2..6bc07f0f1202 100644
--- a/arch/x86/kernel/entry_32.S
+++ b/arch/x86/kernel/entry_32.S
@@ -51,14 +51,15 @@
 #include <asm/percpu.h>
 #include <asm/dwarf2.h>
 #include <asm/processor-flags.h>
-#include "irq_vectors.h"
+#include <asm/ftrace.h>
+#include <asm/irq_vectors.h>
 
 /*
  * We use macros for low-level operations which need to be overridden
  * for paravirtualization.  The following will never clobber any registers:
  *   INTERRUPT_RETURN (aka. "iret")
  *   GET_CR0_INTO_EAX (aka. "movl %cr0, %eax")
- *   ENABLE_INTERRUPTS_SYSCALL_RET (aka "sti; sysexit").
+ *   ENABLE_INTERRUPTS_SYSEXIT (aka "sti; sysexit").
  *
  * For DISABLE_INTERRUPTS/ENABLE_INTERRUPTS (aka "cli"/"sti"), you must
  * specify what registers can be overwritten (CLBR_NONE, CLBR_EAX/EDX/ECX/ANY).
@@ -349,7 +350,7 @@ sysenter_past_esp:
         xorl %ebp,%ebp
         TRACE_IRQS_ON
 1:      mov  PT_FS(%esp), %fs
-        ENABLE_INTERRUPTS_SYSCALL_RET
+        ENABLE_INTERRUPTS_SYSEXIT
         CFI_ENDPROC
 .pushsection .fixup,"ax"
 2:      movl $0,PT_FS(%esp)
@@ -874,10 +875,10 @@ ENTRY(native_iret)
 .previous
 END(native_iret)
 
-ENTRY(native_irq_enable_syscall_ret)
+ENTRY(native_irq_enable_sysexit)
         sti
         sysexit
-END(native_irq_enable_syscall_ret)
+END(native_irq_enable_sysexit)
 #endif
 
 KPROBE_ENTRY(int3)
@@ -1024,6 +1025,7 @@ ENTRY(xen_sysenter_target)
         RING0_INT_FRAME
         addl $5*4, %esp         /* remove xen-provided frame */
         jmp sysenter_past_esp
+        CFI_ENDPROC
 
 ENTRY(xen_hypervisor_callback)
         CFI_STARTPROC
@@ -1110,6 +1112,77 @@ ENDPROC(xen_failsafe_callback)
 
 #endif  /* CONFIG_XEN */
 
+#ifdef CONFIG_FTRACE
+#ifdef CONFIG_DYNAMIC_FTRACE
+
+ENTRY(mcount)
+        pushl %eax
+        pushl %ecx
+        pushl %edx
+        movl 0xc(%esp), %eax
+        subl $MCOUNT_INSN_SIZE, %eax
+
+.globl mcount_call
+mcount_call:
+        call ftrace_stub
+
+        popl %edx
+        popl %ecx
+        popl %eax
+
+        ret
+END(mcount)
+
+ENTRY(ftrace_caller)
+        pushl %eax
+        pushl %ecx
+        pushl %edx
+        movl 0xc(%esp), %eax
+        movl 0x4(%ebp), %edx
+        subl $MCOUNT_INSN_SIZE, %eax
+
+.globl ftrace_call
+ftrace_call:
+        call ftrace_stub
+
+        popl %edx
+        popl %ecx
+        popl %eax
+
+.globl ftrace_stub
+ftrace_stub:
+        ret
+END(ftrace_caller)
+
+#else /* ! CONFIG_DYNAMIC_FTRACE */
+
+ENTRY(mcount)
+        cmpl $ftrace_stub, ftrace_trace_function
+        jnz trace
+.globl ftrace_stub
+ftrace_stub:
+        ret
+
+        /* taken from glibc */
+trace:
+        pushl %eax
+        pushl %ecx
+        pushl %edx
+        movl 0xc(%esp), %eax
+        movl 0x4(%ebp), %edx
+        subl $MCOUNT_INSN_SIZE, %eax
+
+        call *ftrace_trace_function
+
+        popl %edx
+        popl %ecx
+        popl %eax
+
+        jmp ftrace_stub
+END(mcount)
+#endif /* CONFIG_DYNAMIC_FTRACE */
+#endif /* CONFIG_FTRACE */
+
 .section .rodata,"a"
 #include "syscall_table_32.S"
 
diff --git a/arch/x86/kernel/entry_64.S b/arch/x86/kernel/entry_64.S
index 556a8df522a7..ba41bf42748d 100644
--- a/arch/x86/kernel/entry_64.S
+++ b/arch/x86/kernel/entry_64.S
@@ -51,16 +51,121 @@
 #include <asm/page.h>
 #include <asm/irqflags.h>
 #include <asm/paravirt.h>
+#include <asm/ftrace.h>
 
         .code64
 
+#ifdef CONFIG_FTRACE
+#ifdef CONFIG_DYNAMIC_FTRACE
+ENTRY(mcount)
+
+        subq $0x38, %rsp
+        movq %rax, (%rsp)
+        movq %rcx, 8(%rsp)
+        movq %rdx, 16(%rsp)
+        movq %rsi, 24(%rsp)
+        movq %rdi, 32(%rsp)
+        movq %r8, 40(%rsp)
+        movq %r9, 48(%rsp)
+
+        movq 0x38(%rsp), %rdi
+        subq $MCOUNT_INSN_SIZE, %rdi
+
+.globl mcount_call
+mcount_call:
+        call ftrace_stub
+
+        movq 48(%rsp), %r9
+        movq 40(%rsp), %r8
+        movq 32(%rsp), %rdi
+        movq 24(%rsp), %rsi
+        movq 16(%rsp), %rdx
+        movq 8(%rsp), %rcx
+        movq (%rsp), %rax
+        addq $0x38, %rsp
+
+        retq
+END(mcount)
+
+ENTRY(ftrace_caller)
+
+        /* taken from glibc */
+        subq $0x38, %rsp
+        movq %rax, (%rsp)
+        movq %rcx, 8(%rsp)
+        movq %rdx, 16(%rsp)
+        movq %rsi, 24(%rsp)
+        movq %rdi, 32(%rsp)
+        movq %r8, 40(%rsp)
+        movq %r9, 48(%rsp)
+
+        movq 0x38(%rsp), %rdi
+        movq 8(%rbp), %rsi
+        subq $MCOUNT_INSN_SIZE, %rdi
+
+.globl ftrace_call
+ftrace_call:
+        call ftrace_stub
+
+        movq 48(%rsp), %r9
+        movq 40(%rsp), %r8
+        movq 32(%rsp), %rdi
+        movq 24(%rsp), %rsi
+        movq 16(%rsp), %rdx
+        movq 8(%rsp), %rcx
+        movq (%rsp), %rax
+        addq $0x38, %rsp
+
+.globl ftrace_stub
+ftrace_stub:
+        retq
+END(ftrace_caller)
+
+#else /* ! CONFIG_DYNAMIC_FTRACE */
+ENTRY(mcount)
+        cmpq $ftrace_stub, ftrace_trace_function
+        jnz trace
+.globl ftrace_stub
+ftrace_stub:
+        retq
+
+trace:
+        /* taken from glibc */
+        subq $0x38, %rsp
+        movq %rax, (%rsp)
+        movq %rcx, 8(%rsp)
+        movq %rdx, 16(%rsp)
+        movq %rsi, 24(%rsp)
+        movq %rdi, 32(%rsp)
+        movq %r8, 40(%rsp)
+        movq %r9, 48(%rsp)
+
+        movq 0x38(%rsp), %rdi
+        movq 8(%rbp), %rsi
+        subq $MCOUNT_INSN_SIZE, %rdi
+
+        call   *ftrace_trace_function
+
+        movq 48(%rsp), %r9
+        movq 40(%rsp), %r8
+        movq 32(%rsp), %rdi
+        movq 24(%rsp), %rsi
+        movq 16(%rsp), %rdx
+        movq 8(%rsp), %rcx
+        movq (%rsp), %rax
+        addq $0x38, %rsp
+
+        jmp ftrace_stub
+END(mcount)
+#endif /* CONFIG_DYNAMIC_FTRACE */
+#endif /* CONFIG_FTRACE */
+
 #ifndef CONFIG_PREEMPT
 #define retint_kernel retint_restore_args
 #endif  
 
 #ifdef CONFIG_PARAVIRT
-ENTRY(native_irq_enable_syscall_ret)
-        movq    %gs:pda_oldrsp,%rsp
+ENTRY(native_usergs_sysret64)
         swapgs
         sysretq
 #endif /* CONFIG_PARAVIRT */
@@ -104,7 +209,7 @@ ENTRY(native_irq_enable_syscall_ret)
         .macro FAKE_STACK_FRAME child_rip
         /* push in order ss, rsp, eflags, cs, rip */
         xorl %eax, %eax
-        pushq %rax /* ss */
+        pushq $__KERNEL_DS /* ss */
         CFI_ADJUST_CFA_OFFSET   8
         /*CFI_REL_OFFSET        ss,0*/
         pushq %rax /* rsp */
@@ -169,13 +274,13 @@ ENTRY(ret_from_fork)
         CFI_ADJUST_CFA_OFFSET -4
         call schedule_tail
         GET_THREAD_INFO(%rcx)
-        testl $(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT),threadinfo_flags(%rcx)
+        testl $(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT),TI_flags(%rcx)
         jnz rff_trace
 rff_action:     
         RESTORE_REST
         testl $3,CS-ARGOFFSET(%rsp)     # from kernel_thread?
         je   int_ret_from_sys_call
-        testl $_TIF_IA32,threadinfo_flags(%rcx)
+        testl $_TIF_IA32,TI_flags(%rcx)
         jnz  int_ret_from_sys_call
         RESTORE_TOP_OF_STACK %rdi,ARGOFFSET
         jmp ret_from_sys_call
@@ -244,7 +349,8 @@ ENTRY(system_call_after_swapgs)
         movq  %rcx,RIP-ARGOFFSET(%rsp)
         CFI_REL_OFFSET rip,RIP-ARGOFFSET
         GET_THREAD_INFO(%rcx)
-        testl $(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT|_TIF_SECCOMP),threadinfo_flags(%rcx)
+        testl $(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT|_TIF_SECCOMP), \
+                TI_flags(%rcx)
         jnz tracesys
         cmpq $__NR_syscall_max,%rax
         ja badsys
@@ -263,7 +369,7 @@ sysret_check:
         GET_THREAD_INFO(%rcx)
         DISABLE_INTERRUPTS(CLBR_NONE)
         TRACE_IRQS_OFF
-        movl threadinfo_flags(%rcx),%edx
+        movl TI_flags(%rcx),%edx
         andl %edi,%edx
         jnz  sysret_careful 
         CFI_REMEMBER_STATE
@@ -275,7 +381,8 @@ sysret_check:
         CFI_REGISTER    rip,rcx
         RESTORE_ARGS 0,-ARG_SKIP,1
         /*CFI_REGISTER  rflags,r11*/
-        ENABLE_INTERRUPTS_SYSCALL_RET
+        movq    %gs:pda_oldrsp, %rsp
+        USERGS_SYSRET64
 
         CFI_RESTORE_STATE
         /* Handle reschedules */
@@ -305,7 +412,7 @@ sysret_signal:
         leaq -ARGOFFSET(%rsp),%rdi # &pt_regs -> arg1
         xorl %esi,%esi # oldset -> arg2
         call ptregscall_common
-1:      movl $_TIF_NEED_RESCHED,%edi
+1:      movl $_TIF_WORK_MASK,%edi
         /* Use IRET because user could have changed frame. This
            works because ptregscall_common has called FIXUP_TOP_OF_STACK. */
         DISABLE_INTERRUPTS(CLBR_NONE)
@@ -347,10 +454,10 @@ int_ret_from_sys_call:
 int_with_check:
         LOCKDEP_SYS_EXIT_IRQ
         GET_THREAD_INFO(%rcx)
-        movl threadinfo_flags(%rcx),%edx
+        movl TI_flags(%rcx),%edx
         andl %edi,%edx
         jnz   int_careful
-        andl    $~TS_COMPAT,threadinfo_status(%rcx)
+        andl    $~TS_COMPAT,TI_status(%rcx)
         jmp   retint_swapgs
 
         /* Either reschedule or signal or syscall exit tracking needed. */
@@ -393,7 +500,7 @@ int_signal:
         movq %rsp,%rdi          # &ptregs -> arg1
         xorl %esi,%esi          # oldset -> arg2
         call do_notify_resume
-1:      movl $_TIF_NEED_RESCHED,%edi    
+1:      movl $_TIF_WORK_MASK,%edi
 int_restore_rest:
         RESTORE_REST
         DISABLE_INTERRUPTS(CLBR_NONE)
@@ -420,7 +527,6 @@ END(\label)
         PTREGSCALL stub_clone, sys_clone, %r8
         PTREGSCALL stub_fork, sys_fork, %rdi
         PTREGSCALL stub_vfork, sys_vfork, %rdi
-        PTREGSCALL stub_rt_sigsuspend, sys_rt_sigsuspend, %rdx
         PTREGSCALL stub_sigaltstack, sys_sigaltstack, %rdx
         PTREGSCALL stub_iopl, sys_iopl, %rsi
 
@@ -559,7 +665,7 @@ retint_with_reschedule:
         movl $_TIF_WORK_MASK,%edi
 retint_check:
         LOCKDEP_SYS_EXIT_IRQ
-        movl threadinfo_flags(%rcx),%edx
+        movl TI_flags(%rcx),%edx
         andl %edi,%edx
         CFI_REMEMBER_STATE
         jnz  retint_careful
@@ -647,17 +753,16 @@ retint_signal:
         RESTORE_REST
         DISABLE_INTERRUPTS(CLBR_NONE)
         TRACE_IRQS_OFF
-        movl $_TIF_NEED_RESCHED,%edi
         GET_THREAD_INFO(%rcx)
-        jmp retint_check
+        jmp retint_with_reschedule
 
 #ifdef CONFIG_PREEMPT
         /* Returning to kernel space. Check if we need preemption */
         /* rcx:  threadinfo. interrupts off. */
 ENTRY(retint_kernel)
-        cmpl $0,threadinfo_preempt_count(%rcx)
+        cmpl $0,TI_preempt_count(%rcx)
         jnz  retint_restore_args
-        bt  $TIF_NEED_RESCHED,threadinfo_flags(%rcx)
+        bt  $TIF_NEED_RESCHED,TI_flags(%rcx)
         jnc  retint_restore_args
         bt   $9,EFLAGS-ARGOFFSET(%rsp)  /* interrupts off? */
         jnc  retint_restore_args
@@ -720,6 +825,10 @@ ENTRY(apic_timer_interrupt)
         apicinterrupt LOCAL_TIMER_VECTOR,smp_apic_timer_interrupt
 END(apic_timer_interrupt)
 
+ENTRY(uv_bau_message_intr1)
+        apicinterrupt 220,uv_bau_message_interrupt
+END(uv_bau_message_intr1)
+
 ENTRY(error_interrupt)
         apicinterrupt ERROR_APIC_VECTOR,smp_error_interrupt
 END(error_interrupt)
@@ -733,6 +842,7 @@ END(spurious_interrupt)
  */             
         .macro zeroentry sym
         INTR_FRAME
+        PARAVIRT_ADJUST_EXCEPTION_FRAME
         pushq $0        /* push error code/oldrax */ 
         CFI_ADJUST_CFA_OFFSET 8
         pushq %rax      /* push real oldrax to the rdi slot */ 
@@ -745,6 +855,7 @@ END(spurious_interrupt)
 
         .macro errorentry sym
         XCPT_FRAME
+        PARAVIRT_ADJUST_EXCEPTION_FRAME
         pushq %rax
         CFI_ADJUST_CFA_OFFSET 8
         CFI_REL_OFFSET rax,0
@@ -814,7 +925,7 @@ paranoid_restore\trace:
         jmp irq_return
 paranoid_userspace\trace:
         GET_THREAD_INFO(%rcx)
-        movl threadinfo_flags(%rcx),%ebx
+        movl TI_flags(%rcx),%ebx
         andl $_TIF_WORK_MASK,%ebx
         jz paranoid_swapgs\trace
         movq %rsp,%rdi                  /* &pt_regs */
@@ -912,7 +1023,7 @@ error_exit:
         testl %eax,%eax
         jne  retint_kernel
         LOCKDEP_SYS_EXIT_IRQ
-        movl  threadinfo_flags(%rcx),%edx
+        movl  TI_flags(%rcx),%edx
         movl  $_TIF_WORK_MASK,%edi
         andl  %edi,%edx
         jnz  retint_careful
@@ -926,11 +1037,11 @@ error_kernelspace:
            iret run with kernel gs again, so don't set the user space flag.
            B stepping K8s sometimes report an truncated RIP for IRET 
            exceptions returning to compat mode. Check for these here too. */
-        leaq irq_return(%rip),%rbp
-        cmpq %rbp,RIP(%rsp) 
+        leaq irq_return(%rip),%rcx
+        cmpq %rcx,RIP(%rsp)
         je   error_swapgs
-        movl %ebp,%ebp  /* zero extend */
-        cmpq %rbp,RIP(%rsp) 
+        movl %ecx,%ecx  /* zero extend */
+        cmpq %rcx,RIP(%rsp)
         je   error_swapgs
         cmpq $gs_change,RIP(%rsp)
         je   error_swapgs
@@ -939,7 +1050,7 @@ KPROBE_END(error_entry)
         
        /* Reload gs selector with exception handling */
        /* edi:  new selector */ 
-ENTRY(load_gs_index)
+ENTRY(native_load_gs_index)
         CFI_STARTPROC
         pushf
         CFI_ADJUST_CFA_OFFSET 8
@@ -953,7 +1064,7 @@ gs_change:
         CFI_ADJUST_CFA_OFFSET -8
         ret
         CFI_ENDPROC
-ENDPROC(load_gs_index)
+ENDPROC(native_load_gs_index)
        
         .section __ex_table,"a"
         .align 8
@@ -1120,10 +1231,6 @@ ENTRY(coprocessor_segment_overrun)
         zeroentry do_coprocessor_segment_overrun
 END(coprocessor_segment_overrun)
 
-ENTRY(reserved)
-        zeroentry do_reserved
-END(reserved)
-
         /* runs on exception stack */
 ENTRY(double_fault)
         XCPT_FRAME
diff --git a/arch/x86/kernel/ftrace.c b/arch/x86/kernel/ftrace.c
new file mode 100644
index 000000000000..ab115cd15fdf
--- /dev/null
+++ b/arch/x86/kernel/ftrace.c
@@ -0,0 +1,141 @@
+/*
+ * Code for replacing ftrace calls with jumps.
+ *
+ * Copyright (C) 2007-2008 Steven Rostedt <srostedt@redhat.com>
+ *
+ * Thanks goes to Ingo Molnar, for suggesting the idea.
+ * Mathieu Desnoyers, for suggesting postponing the modifications.
+ * Arjan van de Ven, for keeping me straight, and explaining to me
+ * the dangers of modifying code on the run.
+ */
+
+#include <linux/spinlock.h>
+#include <linux/hardirq.h>
+#include <linux/ftrace.h>
+#include <linux/percpu.h>
+#include <linux/init.h>
+#include <linux/list.h>
+
+#include <asm/alternative.h>
+#include <asm/ftrace.h>
+
+
+/* Long is fine, even if it is only 4 bytes ;-) */
+static long *ftrace_nop;
+
+union ftrace_code_union {
+        char code[MCOUNT_INSN_SIZE];
+        struct {
+                char e8;
+                int offset;
+        } __attribute__((packed));
+};
+
+
+static int notrace ftrace_calc_offset(long ip, long addr)
+{
+        return (int)(addr - ip);
+}
+
+notrace unsigned char *ftrace_nop_replace(void)
+{
+        return (char *)ftrace_nop;
+}
+
+notrace unsigned char *ftrace_call_replace(unsigned long ip, unsigned long addr)
+{
+        static union ftrace_code_union calc;
+
+        calc.e8         = 0xe8;
+        calc.offset     = ftrace_calc_offset(ip + MCOUNT_INSN_SIZE, addr);
+
+        /*
+         * No locking needed, this must be called via kstop_machine
+         * which in essence is like running on a uniprocessor machine.
+         */
+        return calc.code;
+}
+
+notrace int
+ftrace_modify_code(unsigned long ip, unsigned char *old_code,
+                   unsigned char *new_code)
+{
+        unsigned replaced;
+        unsigned old = *(unsigned *)old_code; /* 4 bytes */
+        unsigned new = *(unsigned *)new_code; /* 4 bytes */
+        unsigned char newch = new_code[4];
+        int faulted = 0;
+
+        /*
+         * Note: Due to modules and __init, code can
+         *  disappear and change, we need to protect against faulting
+         *  as well as code changing.
+         *
+         * No real locking needed, this code is run through
+         * kstop_machine.
+         */
+        asm volatile (
+                "1: lock\n"
+                "   cmpxchg %3, (%2)\n"
+                "   jnz 2f\n"
+                "   movb %b4, 4(%2)\n"
+                "2:\n"
+                ".section .fixup, \"ax\"\n"
+                "3:     movl $1, %0\n"
+                "       jmp 2b\n"
+                ".previous\n"
+                _ASM_EXTABLE(1b, 3b)
+                : "=r"(faulted), "=a"(replaced)
+                : "r"(ip), "r"(new), "c"(newch),
+                  "0"(faulted), "a"(old)
+                : "memory");
+        sync_core();
+
+        if (replaced != old && replaced != new)
+                faulted = 2;
+
+        return faulted;
+}
+
+notrace int ftrace_update_ftrace_func(ftrace_func_t func)
+{
+        unsigned long ip = (unsigned long)(&ftrace_call);
+        unsigned char old[MCOUNT_INSN_SIZE], *new;
+        int ret;
+
+        memcpy(old, &ftrace_call, MCOUNT_INSN_SIZE);
+        new = ftrace_call_replace(ip, (unsigned long)func);
+        ret = ftrace_modify_code(ip, old, new);
+
+        return ret;
+}
+
+notrace int ftrace_mcount_set(unsigned long *data)
+{
+        unsigned long ip = (long)(&mcount_call);
+        unsigned long *addr = data;
+        unsigned char old[MCOUNT_INSN_SIZE], *new;
+
+        /*
+         * Replace the mcount stub with a pointer to the
+         * ip recorder function.
+         */
+        memcpy(old, &mcount_call, MCOUNT_INSN_SIZE);
+        new = ftrace_call_replace(ip, *addr);
+        *addr = ftrace_modify_code(ip, old, new);
+
+        return 0;
+}
+
+int __init ftrace_dyn_arch_init(void *data)
+{
+        const unsigned char *const *noptable = find_nop_table();
+
+        /* This is running in kstop_machine */
+
+        ftrace_mcount_set(data);
+
+        ftrace_nop = (unsigned long *)noptable[MCOUNT_INSN_SIZE];
+
+        return 0;
+}
diff --git a/arch/x86/kernel/genapic_64.c b/arch/x86/kernel/genapic_64.c
index cbaaf69bedb2..1fa8be5bd217 100644
--- a/arch/x86/kernel/genapic_64.c
+++ b/arch/x86/kernel/genapic_64.c
@@ -51,7 +51,7 @@ void __init setup_apic_routing(void)
         else
 #endif
 
-        if (num_possible_cpus() <= 8)
+        if (max_physical_apicid < 8)
                 genapic = &apic_flat;
         else
                 genapic = &apic_physflat;
diff --git a/arch/x86/kernel/genx2apic_uv_x.c b/arch/x86/kernel/genx2apic_uv_x.c
index ebf13908a743..711f11c30b06 100644
--- a/arch/x86/kernel/genx2apic_uv_x.c
+++ b/arch/x86/kernel/genx2apic_uv_x.c
@@ -5,9 +5,10 @@
  *
  * SGI UV APIC functions (note: not an Intel compatible APIC)
  *
- * Copyright (C) 2007 Silicon Graphics, Inc. All rights reserved.
+ * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
  */
 
+#include <linux/kernel.h>
 #include <linux/threads.h>
 #include <linux/cpumask.h>
 #include <linux/string.h>
@@ -20,6 +21,7 @@
 #include <asm/smp.h>
 #include <asm/ipi.h>
 #include <asm/genapic.h>
+#include <asm/pgtable.h>
 #include <asm/uv/uv_mmrs.h>
 #include <asm/uv/uv_hub.h>
 
@@ -55,37 +57,37 @@ static cpumask_t uv_vector_allocation_domain(int cpu)
 int uv_wakeup_secondary(int phys_apicid, unsigned int start_rip)
 {
         unsigned long val;
-        int nasid;
+        int pnode;
 
-        nasid = uv_apicid_to_nasid(phys_apicid);
+        pnode = uv_apicid_to_pnode(phys_apicid);
         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
             (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
             APIC_DM_INIT;
-        uv_write_global_mmr64(nasid, UVH_IPI_INT, val);
+        uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
         mdelay(10);
 
         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
             (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
             APIC_DM_STARTUP;
-        uv_write_global_mmr64(nasid, UVH_IPI_INT, val);
+        uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
         return 0;
 }
 
 static void uv_send_IPI_one(int cpu, int vector)
 {
         unsigned long val, apicid, lapicid;
-        int nasid;
+        int pnode;
 
         apicid = per_cpu(x86_cpu_to_apicid, cpu); /* ZZZ - cache node-local ? */
         lapicid = apicid & 0x3f;                /* ZZZ macro needed */
-        nasid = uv_apicid_to_nasid(apicid);
+        pnode = uv_apicid_to_pnode(apicid);
         val =
             (1UL << UVH_IPI_INT_SEND_SHFT) | (lapicid <<
                                               UVH_IPI_INT_APIC_ID_SHFT) |
             (vector << UVH_IPI_INT_VECTOR_SHFT);
-        uv_write_global_mmr64(nasid, UVH_IPI_INT, val);
+        uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 }
 
 static void uv_send_IPI_mask(cpumask_t mask, int vector)
@@ -159,39 +161,146 @@ struct genapic apic_x2apic_uv_x = {
         .phys_pkg_id = phys_pkg_id,     /* Fixme ZZZ */
 };
 
-static __cpuinit void set_x2apic_extra_bits(int nasid)
+static __cpuinit void set_x2apic_extra_bits(int pnode)
 {
-        __get_cpu_var(x2apic_extra_bits) = ((nasid >> 1) << 6);
+        __get_cpu_var(x2apic_extra_bits) = (pnode << 6);
 }
 
 /*
  * Called on boot cpu.
  */
+static __init int boot_pnode_to_blade(int pnode)
+{
+        int blade;
+
+        for (blade = 0; blade < uv_num_possible_blades(); blade++)
+                if (pnode == uv_blade_info[blade].pnode)
+                        return blade;
+        BUG();
+}
+
+struct redir_addr {
+        unsigned long redirect;
+        unsigned long alias;
+};
+
+#define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
+
+static __initdata struct redir_addr redir_addrs[] = {
+        {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_SI_ALIAS0_OVERLAY_CONFIG},
+        {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_SI_ALIAS1_OVERLAY_CONFIG},
+        {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_SI_ALIAS2_OVERLAY_CONFIG},
+};
+
+static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
+{
+        union uvh_si_alias0_overlay_config_u alias;
+        union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
+                alias.v = uv_read_local_mmr(redir_addrs[i].alias);
+                if (alias.s.base == 0) {
+                        *size = (1UL << alias.s.m_alias);
+                        redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
+                        *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
+                        return;
+                }
+        }
+        BUG();
+}
+
+static __init void map_low_mmrs(void)
+{
+        init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
+        init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
+}
+
+enum map_type {map_wb, map_uc};
+
+static void map_high(char *id, unsigned long base, int shift, enum map_type map_type)
+{
+        unsigned long bytes, paddr;
+
+        paddr = base << shift;
+        bytes = (1UL << shift);
+        printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr,
+                                                paddr + bytes);
+        if (map_type == map_uc)
+                init_extra_mapping_uc(paddr, bytes);
+        else
+                init_extra_mapping_wb(paddr, bytes);
+
+}
+static __init void map_gru_high(int max_pnode)
+{
+        union uvh_rh_gam_gru_overlay_config_mmr_u gru;
+        int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
+
+        gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
+        if (gru.s.enable)
+                map_high("GRU", gru.s.base, shift, map_wb);
+}
+
+static __init void map_config_high(int max_pnode)
+{
+        union uvh_rh_gam_cfg_overlay_config_mmr_u cfg;
+        int shift = UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_SHFT;
+
+        cfg.v = uv_read_local_mmr(UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR);
+        if (cfg.s.enable)
+                map_high("CONFIG", cfg.s.base, shift, map_uc);
+}
+
+static __init void map_mmr_high(int max_pnode)
+{
+        union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
+        int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
+
+        mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
+        if (mmr.s.enable)
+                map_high("MMR", mmr.s.base, shift, map_uc);
+}
+
+static __init void map_mmioh_high(int max_pnode)
+{
+        union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
+        int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
+
+        mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
+        if (mmioh.s.enable)
+                map_high("MMIOH", mmioh.s.base, shift, map_uc);
+}
+
 static __init void uv_system_init(void)
 {
         union uvh_si_addr_map_config_u m_n_config;
-        int bytes, nid, cpu, lcpu, nasid, last_nasid, blade;
-        unsigned long mmr_base;
+        union uvh_node_id_u node_id;
+        unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
+        int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
+        int max_pnode = 0;
+        unsigned long mmr_base, present;
+
+        map_low_mmrs();
 
         m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG);
+        m_val = m_n_config.s.m_skt;
+        n_val = m_n_config.s.n_skt;
         mmr_base =
             uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
             ~UV_MMR_ENABLE;
         printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
 
-        last_nasid = -1;
-        for_each_possible_cpu(cpu) {
-                nid = cpu_to_node(cpu);
-                nasid = uv_apicid_to_nasid(per_cpu(x86_cpu_to_apicid, cpu));
-                if (nasid != last_nasid)
-                        uv_possible_blades++;
-                last_nasid = nasid;
-        }
+        for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
+                uv_possible_blades +=
+                  hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
         printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());
 
         bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
         uv_blade_info = alloc_bootmem_pages(bytes);
 
+        get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
+
         bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
         uv_node_to_blade = alloc_bootmem_pages(bytes);
         memset(uv_node_to_blade, 255, bytes);
@@ -200,43 +309,62 @@ static __init void uv_system_init(void)
         uv_cpu_to_blade = alloc_bootmem_pages(bytes);
         memset(uv_cpu_to_blade, 255, bytes);
 
-        last_nasid = -1;
-        blade = -1;
-        lcpu = -1;
-        for_each_possible_cpu(cpu) {
-                nid = cpu_to_node(cpu);
-                nasid = uv_apicid_to_nasid(per_cpu(x86_cpu_to_apicid, cpu));
-                if (nasid != last_nasid) {
-                        blade++;
-                        lcpu = -1;
-                        uv_blade_info[blade].nr_posible_cpus = 0;
+        blade = 0;
+        for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
+                present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
+                for (j = 0; j < 64; j++) {
+                        if (!test_bit(j, &present))
+                                continue;
+                        uv_blade_info[blade].pnode = (i * 64 + j);
+                        uv_blade_info[blade].nr_possible_cpus = 0;
                         uv_blade_info[blade].nr_online_cpus = 0;
+                        blade++;
                 }
-                last_nasid = nasid;
-                lcpu++;
+        }
 
-                uv_cpu_hub_info(cpu)->m_val = m_n_config.s.m_skt;
-                uv_cpu_hub_info(cpu)->n_val = m_n_config.s.n_skt;
+        node_id.v = uv_read_local_mmr(UVH_NODE_ID);
+        gnode_upper = (((unsigned long)node_id.s.node_id) &
+                       ~((1 << n_val) - 1)) << m_val;
+
+        for_each_present_cpu(cpu) {
+                nid = cpu_to_node(cpu);
+                pnode = uv_apicid_to_pnode(per_cpu(x86_cpu_to_apicid, cpu));
+                blade = boot_pnode_to_blade(pnode);
+                lcpu = uv_blade_info[blade].nr_possible_cpus;
+                uv_blade_info[blade].nr_possible_cpus++;
+
+                uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
+                uv_cpu_hub_info(cpu)->lowmem_remap_top =
+                                        lowmem_redir_base + lowmem_redir_size;
+                uv_cpu_hub_info(cpu)->m_val = m_val;
+                uv_cpu_hub_info(cpu)->n_val = m_val;
                 uv_cpu_hub_info(cpu)->numa_blade_id = blade;
                 uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
-                uv_cpu_hub_info(cpu)->local_nasid = nasid;
-                uv_cpu_hub_info(cpu)->gnode_upper =
-                    nasid & ~((1 << uv_hub_info->n_val) - 1);
+                uv_cpu_hub_info(cpu)->pnode = pnode;
+                uv_cpu_hub_info(cpu)->pnode_mask = (1 << n_val) - 1;
+                uv_cpu_hub_info(cpu)->gpa_mask = (1 << (m_val + n_val)) - 1;
+                uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
                 uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
                 uv_cpu_hub_info(cpu)->coherency_domain_number = 0;/* ZZZ */
-                uv_blade_info[blade].nasid = nasid;
-                uv_blade_info[blade].nr_posible_cpus++;
                 uv_node_to_blade[nid] = blade;
                 uv_cpu_to_blade[cpu] = blade;
+                max_pnode = max(pnode, max_pnode);
 
-                printk(KERN_DEBUG "UV cpu %d, apicid 0x%x, nasid %d, nid %d\n",
-                       cpu, per_cpu(x86_cpu_to_apicid, cpu), nasid, nid);
-                printk(KERN_DEBUG "UV   lcpu %d, blade %d\n", lcpu, blade);
+                printk(KERN_DEBUG "UV: cpu %d, apicid 0x%x, pnode %d, nid %d, "
+                        "lcpu %d, blade %d\n",
+                        cpu, per_cpu(x86_cpu_to_apicid, cpu), pnode, nid,
+                        lcpu, blade);
         }
+
+        map_gru_high(max_pnode);
+        map_mmr_high(max_pnode);
+        map_config_high(max_pnode);
+        map_mmioh_high(max_pnode);
 }
 
 /*
  * Called on each cpu to initialize the per_cpu UV data area.
+ *      ZZZ hotplug not supported yet
  */
 void __cpuinit uv_cpu_init(void)
 {
@@ -246,5 +374,5 @@ void __cpuinit uv_cpu_init(void)
         uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
 
         if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
-                set_x2apic_extra_bits(uv_hub_info->local_nasid);
+                set_x2apic_extra_bits(uv_hub_info->pnode);
 }
diff --git a/arch/x86/kernel/head.c b/arch/x86/kernel/head.c
new file mode 100644
index 000000000000..3e66bd364a9d
--- /dev/null
+++ b/arch/x86/kernel/head.c
@@ -0,0 +1,55 @@
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/setup.h>
+#include <asm/bios_ebda.h>
+
+#define BIOS_LOWMEM_KILOBYTES 0x413
+
+/*
+ * The BIOS places the EBDA/XBDA at the top of conventional
+ * memory, and usually decreases the reported amount of
+ * conventional memory (int 0x12) too. This also contains a
+ * workaround for Dell systems that neglect to reserve EBDA.
+ * The same workaround also avoids a problem with the AMD768MPX
+ * chipset: reserve a page before VGA to prevent PCI prefetch
+ * into it (errata #56). Usually the page is reserved anyways,
+ * unless you have no PS/2 mouse plugged in.
+ */
+void __init reserve_ebda_region(void)
+{
+        unsigned int lowmem, ebda_addr;
+
+        /* To determine the position of the EBDA and the */
+        /* end of conventional memory, we need to look at */
+        /* the BIOS data area. In a paravirtual environment */
+        /* that area is absent. We'll just have to assume */
+        /* that the paravirt case can handle memory setup */
+        /* correctly, without our help. */
+        if (paravirt_enabled())
+                return;
+
+        /* end of low (conventional) memory */
+        lowmem = *(unsigned short *)__va(BIOS_LOWMEM_KILOBYTES);
+        lowmem <<= 10;
+
+        /* start of EBDA area */
+        ebda_addr = get_bios_ebda();
+
+        /* Fixup: bios puts an EBDA in the top 64K segment */
+        /* of conventional memory, but does not adjust lowmem. */
+        if ((lowmem - ebda_addr) <= 0x10000)
+                lowmem = ebda_addr;
+
+        /* Fixup: bios does not report an EBDA at all. */
+        /* Some old Dells seem to need 4k anyhow (bugzilla 2990) */
+        if ((ebda_addr == 0) && (lowmem >= 0x9f000))
+                lowmem = 0x9f000;
+
+        /* Paranoia: should never happen, but... */
+        if ((lowmem == 0) || (lowmem >= 0x100000))
+                lowmem = 0x9f000;
+
+        /* reserve all memory between lowmem and the 1MB mark */
+        reserve_early_overlap_ok(lowmem, 0x100000, "BIOS reserved");
+}
diff --git a/arch/x86/kernel/head32.c b/arch/x86/kernel/head32.c
index 3db059058927..fa1d25dd83e3 100644
--- a/arch/x86/kernel/head32.c
+++ b/arch/x86/kernel/head32.c
@@ -8,7 +8,34 @@
 #include <linux/init.h>
 #include <linux/start_kernel.h>
 
+#include <asm/setup.h>
+#include <asm/sections.h>
+#include <asm/e820.h>
+#include <asm/bios_ebda.h>
+
 void __init i386_start_kernel(void)
 {
+        reserve_early(__pa_symbol(&_text), __pa_symbol(&_end), "TEXT DATA BSS");
+
+#ifdef CONFIG_BLK_DEV_INITRD
+        /* Reserve INITRD */
+        if (boot_params.hdr.type_of_loader && boot_params.hdr.ramdisk_image) {
+                u64 ramdisk_image = boot_params.hdr.ramdisk_image;
+                u64 ramdisk_size  = boot_params.hdr.ramdisk_size;
+                u64 ramdisk_end   = ramdisk_image + ramdisk_size;
+                reserve_early(ramdisk_image, ramdisk_end, "RAMDISK");
+        }
+#endif
+        reserve_early(init_pg_tables_start, init_pg_tables_end,
+                        "INIT_PG_TABLE");
+
+        reserve_ebda_region();
+
+        /*
+         * At this point everything still needed from the boot loader
+         * or BIOS or kernel text should be early reserved or marked not
+         * RAM in e820. All other memory is free game.
+         */
+
         start_kernel();
 }
diff --git a/arch/x86/kernel/head64.c b/arch/x86/kernel/head64.c
index e25c57b8aa84..c97819829146 100644
--- a/arch/x86/kernel/head64.c
+++ b/arch/x86/kernel/head64.c
@@ -25,6 +25,20 @@
 #include <asm/e820.h>
 #include <asm/bios_ebda.h>
 
+/* boot cpu pda */
+static struct x8664_pda _boot_cpu_pda __read_mostly;
+
+#ifdef CONFIG_SMP
+/*
+ * We install an empty cpu_pda pointer table to indicate to early users
+ * (numa_set_node) that the cpu_pda pointer table for cpus other than
+ * the boot cpu is not yet setup.
+ */
+static struct x8664_pda *__cpu_pda[NR_CPUS] __initdata;
+#else
+static struct x8664_pda *__cpu_pda[NR_CPUS] __read_mostly;
+#endif
+
 static void __init zap_identity_mappings(void)
 {
         pgd_t *pgd = pgd_offset_k(0UL);
@@ -51,74 +65,6 @@ static void __init copy_bootdata(char *real_mode_data)
         }
 }
 
-#define BIOS_LOWMEM_KILOBYTES 0x413
-
-/*
- * The BIOS places the EBDA/XBDA at the top of conventional
- * memory, and usually decreases the reported amount of
- * conventional memory (int 0x12) too. This also contains a
- * workaround for Dell systems that neglect to reserve EBDA.
- * The same workaround also avoids a problem with the AMD768MPX
- * chipset: reserve a page before VGA to prevent PCI prefetch
- * into it (errata #56). Usually the page is reserved anyways,
- * unless you have no PS/2 mouse plugged in.
- */
-static void __init reserve_ebda_region(void)
-{
-        unsigned int lowmem, ebda_addr;
-
-        /* To determine the position of the EBDA and the */
-        /* end of conventional memory, we need to look at */
-        /* the BIOS data area. In a paravirtual environment */
-        /* that area is absent. We'll just have to assume */
-        /* that the paravirt case can handle memory setup */
-        /* correctly, without our help. */
-        if (paravirt_enabled())
-                return;
-
-        /* end of low (conventional) memory */
-        lowmem = *(unsigned short *)__va(BIOS_LOWMEM_KILOBYTES);
-        lowmem <<= 10;
-
-        /* start of EBDA area */
-        ebda_addr = get_bios_ebda();
-
-        /* Fixup: bios puts an EBDA in the top 64K segment */
-        /* of conventional memory, but does not adjust lowmem. */
-        if ((lowmem - ebda_addr) <= 0x10000)
-                lowmem = ebda_addr;
-
-        /* Fixup: bios does not report an EBDA at all. */
-        /* Some old Dells seem to need 4k anyhow (bugzilla 2990) */
-        if ((ebda_addr == 0) && (lowmem >= 0x9f000))
-                lowmem = 0x9f000;
-
-        /* Paranoia: should never happen, but... */
-        if ((lowmem == 0) || (lowmem >= 0x100000))
-                lowmem = 0x9f000;
-
-        /* reserve all memory between lowmem and the 1MB mark */
-        reserve_early(lowmem, 0x100000, "BIOS reserved");
-}
-
-static void __init reserve_setup_data(void)
-{
-        struct setup_data *data;
-        unsigned long pa_data;
-        char buf[32];
-
-        if (boot_params.hdr.version < 0x0209)
-                return;
-        pa_data = boot_params.hdr.setup_data;
-        while (pa_data) {
-                data = early_ioremap(pa_data, sizeof(*data));
-                sprintf(buf, "setup data %x", data->type);
-                reserve_early(pa_data, pa_data+sizeof(*data)+data->len, buf);
-                pa_data = data->next;
-                early_iounmap(data, sizeof(*data));
-        }
-}
-
 void __init x86_64_start_kernel(char * real_mode_data)
 {
         int i;
@@ -156,10 +102,17 @@ void __init x86_64_start_kernel(char * real_mode_data)
 
         early_printk("Kernel alive\n");
 
-        for (i = 0; i < NR_CPUS; i++)
-                cpu_pda(i) = &boot_cpu_pda[i];
-
+        _cpu_pda = __cpu_pda;
+        cpu_pda(0) = &_boot_cpu_pda;
         pda_init(0);
+
+        early_printk("Kernel really alive\n");
+
+        x86_64_start_reservations(real_mode_data);
+}
+
+void __init x86_64_start_reservations(char *real_mode_data)
+{
         copy_bootdata(__va(real_mode_data));
 
         reserve_early(__pa_symbol(&_text), __pa_symbol(&_end), "TEXT DATA BSS");
@@ -175,7 +128,6 @@ void __init x86_64_start_kernel(char * real_mode_data)
 #endif
 
         reserve_ebda_region();
-        reserve_setup_data();
 
         /*
          * At this point everything still needed from the boot loader
diff --git a/arch/x86/kernel/head_32.S b/arch/x86/kernel/head_32.S
index f7357cc0162c..f67e93441caf 100644
--- a/arch/x86/kernel/head_32.S
+++ b/arch/x86/kernel/head_32.S
@@ -194,6 +194,7 @@ default_entry:
         xorl %ebx,%ebx                          /* %ebx is kept at zero */
 
         movl $pa(pg0), %edi
+        movl %edi, pa(init_pg_tables_start)
         movl $pa(swapper_pg_pmd), %edx
         movl $PTE_ATTR, %eax
 10:
@@ -219,6 +220,8 @@ default_entry:
         jb 10b
 1:
         movl %edi,pa(init_pg_tables_end)
+        shrl $12, %eax
+        movl %eax, pa(max_pfn_mapped)
 
         /* Do early initialization of the fixmap area */
         movl $pa(swapper_pg_fixmap)+PDE_ATTR,%eax
@@ -228,6 +231,7 @@ default_entry:
 page_pde_offset = (__PAGE_OFFSET >> 20);
 
         movl $pa(pg0), %edi
+        movl %edi, pa(init_pg_tables_start)
         movl $pa(swapper_pg_dir), %edx
         movl $PTE_ATTR, %eax
 10:
@@ -249,6 +253,8 @@ page_pde_offset = (__PAGE_OFFSET >> 20);
         cmpl %ebp,%eax
         jb 10b
         movl %edi,pa(init_pg_tables_end)
+        shrl $12, %eax
+        movl %eax, pa(max_pfn_mapped)
 
         /* Do early initialization of the fixmap area */
         movl $pa(swapper_pg_fixmap)+PDE_ATTR,%eax
@@ -446,10 +452,13 @@ is386:	movl $2,%ecx		# set MP
         je   1f
         movl $(__KERNEL_PERCPU), %eax
         movl %eax,%fs           # set this cpu's percpu
-        jmp initialize_secondary # all other CPUs call initialize_secondary
+        movl (stack_start), %esp
 1:
 #endif /* CONFIG_SMP */
-        jmp i386_start_kernel
+        jmp *(initial_code)
+.align 4
+ENTRY(initial_code)
+        .long i386_start_kernel
 
 /*
  * We depend on ET to be correct. This checks for 287/387.
diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S
index b817974ef942..b07ac7b217cb 100644
--- a/arch/x86/kernel/head_64.S
+++ b/arch/x86/kernel/head_64.S
@@ -18,6 +18,7 @@
 #include <asm/page.h>
 #include <asm/msr.h>
 #include <asm/cache.h>
+#include <asm/processor-flags.h>
 
 #ifdef CONFIG_PARAVIRT
 #include <asm/asm-offsets.h>
@@ -31,6 +32,13 @@
  *
  */
 
+#define pud_index(x)    (((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
+
+L4_PAGE_OFFSET = pgd_index(__PAGE_OFFSET)
+L3_PAGE_OFFSET = pud_index(__PAGE_OFFSET)
+L4_START_KERNEL = pgd_index(__START_KERNEL_map)
+L3_START_KERNEL = pud_index(__START_KERNEL_map)
+
         .text
         .section .text.head
         .code64
@@ -76,8 +84,8 @@ startup_64:
         /* Fixup the physical addresses in the page table
          */
         addq    %rbp, init_level4_pgt + 0(%rip)
-        addq    %rbp, init_level4_pgt + (258*8)(%rip)
-        addq    %rbp, init_level4_pgt + (511*8)(%rip)
+        addq    %rbp, init_level4_pgt + (L4_PAGE_OFFSET*8)(%rip)
+        addq    %rbp, init_level4_pgt + (L4_START_KERNEL*8)(%rip)
 
         addq    %rbp, level3_ident_pgt + 0(%rip)
 
@@ -154,9 +162,7 @@ ENTRY(secondary_startup_64)
          */
 
         /* Enable PAE mode and PGE */
-        xorq    %rax, %rax
-        btsq    $5, %rax
-        btsq    $7, %rax
+        movl    $(X86_CR4_PAE | X86_CR4_PGE), %eax
         movq    %rax, %cr4
 
         /* Setup early boot stage 4 level pagetables. */
@@ -184,19 +190,15 @@ ENTRY(secondary_startup_64)
 1:      wrmsr                           /* Make changes effective */
 
         /* Setup cr0 */
-#define CR0_PM                          1               /* protected mode */
-#define CR0_MP                          (1<<1)
-#define CR0_ET                          (1<<4)
-#define CR0_NE                          (1<<5)
-#define CR0_WP                          (1<<16)
-#define CR0_AM                          (1<<18)
-#define CR0_PAGING                      (1<<31)
-        movl $CR0_PM|CR0_MP|CR0_ET|CR0_NE|CR0_WP|CR0_AM|CR0_PAGING,%eax
+#define CR0_STATE       (X86_CR0_PE | X86_CR0_MP | X86_CR0_ET | \
+                         X86_CR0_NE | X86_CR0_WP | X86_CR0_AM | \
+                         X86_CR0_PG)
+        movl    $CR0_STATE, %eax
         /* Make changes effective */
         movq    %rax, %cr0
 
         /* Setup a boot time stack */
-        movq init_rsp(%rip),%rsp
+        movq stack_start(%rip),%rsp
 
         /* zero EFLAGS after setting rsp */
         pushq $0
@@ -208,7 +210,7 @@ ENTRY(secondary_startup_64)
          * addresses where we're currently running on. We have to do that here
          * because in 32bit we couldn't load a 64bit linear address.
          */
-        lgdt    cpu_gdt_descr(%rip)
+        lgdt    early_gdt_descr(%rip)
 
         /* set up data segments. actually 0 would do too */
         movl $__KERNEL_DS,%eax
@@ -257,8 +259,9 @@ ENTRY(secondary_startup_64)
         .quad   x86_64_start_kernel
         __FINITDATA
 
-        ENTRY(init_rsp)
+        ENTRY(stack_start)
         .quad  init_thread_union+THREAD_SIZE-8
+        .word  0
 
 bad_address:
         jmp bad_address
@@ -327,11 +330,11 @@ early_idt_ripmsg:
 ENTRY(name)
 
 /* Automate the creation of 1 to 1 mapping pmd entries */
-#define PMDS(START, PERM, COUNT)                \
-        i = 0 ;                                 \
-        .rept (COUNT) ;                         \
-        .quad   (START) + (i << 21) + (PERM) ;  \
-        i = i + 1 ;                             \
+#define PMDS(START, PERM, COUNT)                        \
+        i = 0 ;                                         \
+        .rept (COUNT) ;                                 \
+        .quad   (START) + (i << PMD_SHIFT) + (PERM) ;   \
+        i = i + 1 ;                                     \
         .endr
 
         /*
@@ -342,9 +345,9 @@ ENTRY(name)
          */
 NEXT_PAGE(init_level4_pgt)
         .quad   level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
-        .fill   257,8,0
+        .org    init_level4_pgt + L4_PAGE_OFFSET*8, 0
         .quad   level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
-        .fill   252,8,0
+        .org    init_level4_pgt + L4_START_KERNEL*8, 0
         /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */
         .quad   level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE
 
@@ -353,7 +356,7 @@ NEXT_PAGE(level3_ident_pgt)
         .fill   511,8,0
 
 NEXT_PAGE(level3_kernel_pgt)
-        .fill   510,8,0
+        .fill   L3_START_KERNEL,8,0
         /* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */
         .quad   level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE
         .quad   level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE
@@ -384,7 +387,7 @@ NEXT_PAGE(level2_kernel_pgt)
          *  If you want to increase this then increase MODULES_VADDR
          *  too.)
          */
-        PMDS(0, __PAGE_KERNEL_LARGE_EXEC|_PAGE_GLOBAL,
+        PMDS(0, __PAGE_KERNEL_LARGE_EXEC,
                 KERNEL_IMAGE_SIZE/PMD_SIZE)
 
 NEXT_PAGE(level2_spare_pgt)
@@ -395,54 +398,16 @@ NEXT_PAGE(level2_spare_pgt)
 
         .data
         .align 16
-        .globl cpu_gdt_descr
-cpu_gdt_descr:
-        .word   gdt_end-cpu_gdt_table-1
-gdt:
-        .quad   cpu_gdt_table
-#ifdef CONFIG_SMP
-        .rept   NR_CPUS-1
-        .word   0
-        .quad   0
-        .endr
-#endif
+        .globl early_gdt_descr
+early_gdt_descr:
+        .word   GDT_ENTRIES*8-1
+        .quad   per_cpu__gdt_page
 
 ENTRY(phys_base)
         /* This must match the first entry in level2_kernel_pgt */
         .quad   0x0000000000000000
 
-/* We need valid kernel segments for data and code in long mode too
- * IRET will check the segment types  kkeil 2000/10/28
- * Also sysret mandates a special GDT layout 
- */
-                                
-        .section .data.page_aligned, "aw"
-        .align PAGE_SIZE
-
-/* The TLS descriptors are currently at a different place compared to i386.
-   Hopefully nobody expects them at a fixed place (Wine?) */
         
-ENTRY(cpu_gdt_table)
-        .quad   0x0000000000000000      /* NULL descriptor */
-        .quad   0x00cf9b000000ffff      /* __KERNEL32_CS */
-        .quad   0x00af9b000000ffff      /* __KERNEL_CS */
-        .quad   0x00cf93000000ffff      /* __KERNEL_DS */
-        .quad   0x00cffb000000ffff      /* __USER32_CS */
-        .quad   0x00cff3000000ffff      /* __USER_DS, __USER32_DS  */
-        .quad   0x00affb000000ffff      /* __USER_CS */
-        .quad   0x0                     /* unused */
-        .quad   0,0                     /* TSS */
-        .quad   0,0                     /* LDT */
-        .quad   0,0,0                   /* three TLS descriptors */ 
-        .quad   0x0000f40000000000      /* node/CPU stored in limit */
-gdt_end:        
-        /* asm/segment.h:GDT_ENTRIES must match this */ 
-        /* This should be a multiple of the cache line size */
-        /* GDTs of other CPUs are now dynamically allocated */
-
-        /* zero the remaining page */
-        .fill PAGE_SIZE / 8 - GDT_ENTRIES,8,0
-
         .section .bss, "aw", @nobits
         .align L1_CACHE_BYTES
 ENTRY(idt_table)
diff --git a/arch/x86/kernel/hpet.c b/arch/x86/kernel/hpet.c
index 9b5cfcdfc426..0ea6a19bfdfe 100644
--- a/arch/x86/kernel/hpet.c
+++ b/arch/x86/kernel/hpet.c
@@ -17,7 +17,7 @@
 
 /* FSEC = 10^-15
    NSEC = 10^-9 */
-#define FSEC_PER_NSEC   1000000
+#define FSEC_PER_NSEC   1000000L
 
 /*
  * HPET address is set in acpi/boot.c, when an ACPI entry exists
@@ -36,26 +36,15 @@ static inline void hpet_writel(unsigned long d, unsigned long a)
 }
 
 #ifdef CONFIG_X86_64
-
 #include <asm/pgtable.h>
-
-static inline void hpet_set_mapping(void)
-{
-        set_fixmap_nocache(FIX_HPET_BASE, hpet_address);
-        __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VSYSCALL_NOCACHE);
-        hpet_virt_address = (void __iomem *)fix_to_virt(FIX_HPET_BASE);
-}
-
-static inline void hpet_clear_mapping(void)
-{
-        hpet_virt_address = NULL;
-}
-
-#else
+#endif
 
 static inline void hpet_set_mapping(void)
 {
         hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
+#ifdef CONFIG_X86_64
+        __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VSYSCALL_NOCACHE);
+#endif
 }
 
 static inline void hpet_clear_mapping(void)
@@ -63,7 +52,6 @@ static inline void hpet_clear_mapping(void)
         iounmap(hpet_virt_address);
         hpet_virt_address = NULL;
 }
-#endif
 
 /*
  * HPET command line enable / disable
@@ -206,20 +194,19 @@ static void hpet_enable_legacy_int(void)
 
 static void hpet_legacy_clockevent_register(void)
 {
-        uint64_t hpet_freq;
-
         /* Start HPET legacy interrupts */
         hpet_enable_legacy_int();
 
         /*
-         * The period is a femto seconds value. We need to calculate the
-         * scaled math multiplication factor for nanosecond to hpet tick
-         * conversion.
+         * The mult factor is defined as (include/linux/clockchips.h)
+         *  mult/2^shift = cyc/ns (in contrast to ns/cyc in clocksource.h)
+         * hpet_period is in units of femtoseconds (per cycle), so
+         *  mult/2^shift = cyc/ns = 10^6/hpet_period
+         *  mult = (10^6 * 2^shift)/hpet_period
+         *  mult = (FSEC_PER_NSEC << hpet_clockevent.shift)/hpet_period
          */
-        hpet_freq = 1000000000000000ULL;
-        do_div(hpet_freq, hpet_period);
-        hpet_clockevent.mult = div_sc((unsigned long) hpet_freq,
-                                      NSEC_PER_SEC, hpet_clockevent.shift);
+        hpet_clockevent.mult = div_sc((unsigned long) FSEC_PER_NSEC,
+                                      hpet_period, hpet_clockevent.shift);
         /* Calculate the min / max delta */
         hpet_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF,
                                                            &hpet_clockevent);
@@ -324,7 +311,7 @@ static struct clocksource clocksource_hpet = {
 
 static int hpet_clocksource_register(void)
 {
-        u64 tmp, start, now;
+        u64 start, now;
         cycle_t t1;
 
         /* Start the counter */
@@ -351,21 +338,15 @@ static int hpet_clocksource_register(void)
                 return -ENODEV;
         }
 
-        /* Initialize and register HPET clocksource
-         *
-         * hpet period is in femto seconds per cycle
-         * so we need to convert this to ns/cyc units
-         * approximated by mult/2^shift
-         *
-         *  fsec/cyc * 1nsec/1000000fsec = nsec/cyc = mult/2^shift
-         *  fsec/cyc * 1ns/1000000fsec * 2^shift = mult
-         *  fsec/cyc * 2^shift * 1nsec/1000000fsec = mult
-         *  (fsec/cyc << shift)/1000000 = mult
-         *  (hpet_period << shift)/FSEC_PER_NSEC = mult
+        /*
+         * The definition of mult is (include/linux/clocksource.h)
+         * mult/2^shift = ns/cyc and hpet_period is in units of fsec/cyc
+         * so we first need to convert hpet_period to ns/cyc units:
+         *  mult/2^shift = ns/cyc = hpet_period/10^6
+         *  mult = (hpet_period * 2^shift)/10^6
+         *  mult = (hpet_period << shift)/FSEC_PER_NSEC
          */
-        tmp = (u64)hpet_period << HPET_SHIFT;
-        do_div(tmp, FSEC_PER_NSEC);
-        clocksource_hpet.mult = (u32)tmp;
+        clocksource_hpet.mult = div_sc(hpet_period, FSEC_PER_NSEC, HPET_SHIFT);
 
         clocksource_register(&clocksource_hpet);
 
diff --git a/arch/x86/kernel/i386_ksyms_32.c b/arch/x86/kernel/i386_ksyms_32.c
index deb43785e923..dd7ebee446af 100644
--- a/arch/x86/kernel/i386_ksyms_32.c
+++ b/arch/x86/kernel/i386_ksyms_32.c
@@ -1,7 +1,14 @@
 #include <linux/module.h>
+
 #include <asm/checksum.h>
-#include <asm/desc.h>
 #include <asm/pgtable.h>
+#include <asm/desc.h>
+#include <asm/ftrace.h>
+
+#ifdef CONFIG_FTRACE
+/* mcount is defined in assembly */
+EXPORT_SYMBOL(mcount);
+#endif
 
 /* Networking helper routines. */
 EXPORT_SYMBOL(csum_partial_copy_generic);
diff --git a/arch/x86/kernel/i387.c b/arch/x86/kernel/i387.c
index 95e80e5033c3..eb9ddd8efb82 100644
--- a/arch/x86/kernel/i387.c
+++ b/arch/x86/kernel/i387.c
@@ -162,7 +162,7 @@ int xfpregs_get(struct task_struct *target, const struct user_regset *regset,
         int ret;
 
         if (!cpu_has_fxsr)
-                return -EIO;
+                return -ENODEV;
 
         ret = init_fpu(target);
         if (ret)
@@ -179,7 +179,7 @@ int xfpregs_set(struct task_struct *target, const struct user_regset *regset,
         int ret;
 
         if (!cpu_has_fxsr)
-                return -EIO;
+                return -ENODEV;
 
         ret = init_fpu(target);
         if (ret)
diff --git a/arch/x86/kernel/i8259_32.c b/arch/x86/kernel/i8259.c
index fe631967d625..dc92b49d9204 100644
--- a/arch/x86/kernel/i8259_32.c
+++ b/arch/x86/kernel/i8259.c
@@ -1,8 +1,10 @@
+#include <linux/linkage.h>
 #include <linux/errno.h>
 #include <linux/signal.h>
 #include <linux/sched.h>
 #include <linux/ioport.h>
 #include <linux/interrupt.h>
+#include <linux/timex.h>
 #include <linux/slab.h>
 #include <linux/random.h>
 #include <linux/init.h>
@@ -10,10 +12,12 @@
 #include <linux/sysdev.h>
 #include <linux/bitops.h>
 
+#include <asm/acpi.h>
 #include <asm/atomic.h>
 #include <asm/system.h>
 #include <asm/io.h>
 #include <asm/timer.h>
+#include <asm/hw_irq.h>
 #include <asm/pgtable.h>
 #include <asm/delay.h>
 #include <asm/desc.h>
@@ -32,7 +36,7 @@ static int i8259A_auto_eoi;
 DEFINE_SPINLOCK(i8259A_lock);
 static void mask_and_ack_8259A(unsigned int);
 
-static struct irq_chip i8259A_chip = {
+struct irq_chip i8259A_chip = {
         .name           = "XT-PIC",
         .mask           = disable_8259A_irq,
         .disable        = disable_8259A_irq,
@@ -125,14 +129,14 @@ static inline int i8259A_irq_real(unsigned int irq)
         int irqmask = 1<<irq;
 
         if (irq < 8) {
-                outb(0x0B,PIC_MASTER_CMD);      /* ISR register */
+                outb(0x0B, PIC_MASTER_CMD);     /* ISR register */
                 value = inb(PIC_MASTER_CMD) & irqmask;
-                outb(0x0A,PIC_MASTER_CMD);      /* back to the IRR register */
+                outb(0x0A, PIC_MASTER_CMD);     /* back to the IRR register */
                 return value;
         }
-        outb(0x0B,PIC_SLAVE_CMD);       /* ISR register */
+        outb(0x0B, PIC_SLAVE_CMD);      /* ISR register */
         value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
-        outb(0x0A,PIC_SLAVE_CMD);       /* back to the IRR register */
+        outb(0x0A, PIC_SLAVE_CMD);      /* back to the IRR register */
         return value;
 }
 
@@ -171,12 +175,14 @@ handle_real_irq:
         if (irq & 8) {
                 inb(PIC_SLAVE_IMR);     /* DUMMY - (do we need this?) */
                 outb(cached_slave_mask, PIC_SLAVE_IMR);
-                outb(0x60+(irq&7),PIC_SLAVE_CMD);/* 'Specific EOI' to slave */
-                outb(0x60+PIC_CASCADE_IR,PIC_MASTER_CMD); /* 'Specific EOI' to master-IRQ2 */
+                /* 'Specific EOI' to slave */
+                outb(0x60+(irq&7), PIC_SLAVE_CMD);
+                 /* 'Specific EOI' to master-IRQ2 */
+                outb(0x60+PIC_CASCADE_IR, PIC_MASTER_CMD);
         } else {
                 inb(PIC_MASTER_IMR);    /* DUMMY - (do we need this?) */
                 outb(cached_master_mask, PIC_MASTER_IMR);
-                outb(0x60+irq,PIC_MASTER_CMD);  /* 'Specific EOI to master */
+                outb(0x60+irq, PIC_MASTER_CMD); /* 'Specific EOI to master */
         }
         spin_unlock_irqrestore(&i8259A_lock, flags);
         return;
@@ -199,7 +205,8 @@ spurious_8259A_irq:
                  * lets ACK and report it. [once per IRQ]
                  */
                 if (!(spurious_irq_mask & irqmask)) {
-                        printk(KERN_DEBUG "spurious 8259A interrupt: IRQ%d.\n", irq);
+                        printk(KERN_DEBUG
+                               "spurious 8259A interrupt: IRQ%d.\n", irq);
                         spurious_irq_mask |= irqmask;
                 }
                 atomic_inc(&irq_err_count);
@@ -290,17 +297,28 @@ void init_8259A(int auto_eoi)
          * outb_pic - this has to work on a wide range of PC hardware.
          */
         outb_pic(0x11, PIC_MASTER_CMD); /* ICW1: select 8259A-1 init */
-        outb_pic(0x20 + 0, PIC_MASTER_IMR);     /* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */
-        outb_pic(1U << PIC_CASCADE_IR, PIC_MASTER_IMR); /* 8259A-1 (the master) has a slave on IR2 */
+
+        /* ICW2: 8259A-1 IR0-7 mapped to 0x30-0x37 on x86-64,
+                               to 0x20-0x27 on i386 */
+        outb_pic(IRQ0_VECTOR, PIC_MASTER_IMR);
+
+        /* 8259A-1 (the master) has a slave on IR2 */
+        outb_pic(1U << PIC_CASCADE_IR, PIC_MASTER_IMR);
+
         if (auto_eoi)   /* master does Auto EOI */
                 outb_pic(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR);
         else            /* master expects normal EOI */
                 outb_pic(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);
 
         outb_pic(0x11, PIC_SLAVE_CMD);  /* ICW1: select 8259A-2 init */
-        outb_pic(0x20 + 8, PIC_SLAVE_IMR);      /* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */
-        outb_pic(PIC_CASCADE_IR, PIC_SLAVE_IMR);        /* 8259A-2 is a slave on master's IR2 */
-        outb_pic(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR); /* (slave's support for AEOI in flat mode is to be investigated) */
+
+        /* ICW2: 8259A-2 IR0-7 mapped to IRQ8_VECTOR */
+        outb_pic(IRQ8_VECTOR, PIC_SLAVE_IMR);
+        /* 8259A-2 is a slave on master's IR2 */
+        outb_pic(PIC_CASCADE_IR, PIC_SLAVE_IMR);
+        /* (slave's support for AEOI in flat mode is to be investigated) */
+        outb_pic(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR);
+
         if (auto_eoi)
                 /*
                  * In AEOI mode we just have to mask the interrupt
@@ -317,93 +335,3 @@ void init_8259A(int auto_eoi)
 
         spin_unlock_irqrestore(&i8259A_lock, flags);
 }
-
-/*
- * Note that on a 486, we don't want to do a SIGFPE on an irq13
- * as the irq is unreliable, and exception 16 works correctly
- * (ie as explained in the intel literature). On a 386, you
- * can't use exception 16 due to bad IBM design, so we have to
- * rely on the less exact irq13.
- *
- * Careful.. Not only is IRQ13 unreliable, but it is also
- * leads to races. IBM designers who came up with it should
- * be shot.
- */
- 
-
-static irqreturn_t math_error_irq(int cpl, void *dev_id)
-{
-        extern void math_error(void __user *);
-        outb(0,0xF0);
-        if (ignore_fpu_irq || !boot_cpu_data.hard_math)
-                return IRQ_NONE;
-        math_error((void __user *)get_irq_regs()->ip);
-        return IRQ_HANDLED;
-}
-
-/*
- * New motherboards sometimes make IRQ 13 be a PCI interrupt,
- * so allow interrupt sharing.
- */
-static struct irqaction fpu_irq = {
-        .handler = math_error_irq,
-        .mask = CPU_MASK_NONE,
-        .name = "fpu",
-};
-
-void __init init_ISA_irqs (void)
-{
-        int i;
-
-#ifdef CONFIG_X86_LOCAL_APIC
-        init_bsp_APIC();
-#endif
-        init_8259A(0);
-
-        /*
-         * 16 old-style INTA-cycle interrupts:
-         */
-        for (i = 0; i < 16; i++) {
-                set_irq_chip_and_handler_name(i, &i8259A_chip,
-                                              handle_level_irq, "XT");
-        }
-}
-
-/* Overridden in paravirt.c */
-void init_IRQ(void) __attribute__((weak, alias("native_init_IRQ")));
-
-void __init native_init_IRQ(void)
-{
-        int i;
-
-        /* all the set up before the call gates are initialised */
-        pre_intr_init_hook();
-
-        /*
-         * Cover the whole vector space, no vector can escape
-         * us. (some of these will be overridden and become
-         * 'special' SMP interrupts)
-         */
-        for (i = 0; i < (NR_VECTORS - FIRST_EXTERNAL_VECTOR); i++) {
-                int vector = FIRST_EXTERNAL_VECTOR + i;
-                if (i >= NR_IRQS)
-                        break;
-                /* SYSCALL_VECTOR was reserved in trap_init. */
-                if (!test_bit(vector, used_vectors))
-                        set_intr_gate(vector, interrupt[i]);
-        }
-
-        /* setup after call gates are initialised (usually add in
-         * the architecture specific gates)
-         */
-        intr_init_hook();
-
-        /*
-         * External FPU? Set up irq13 if so, for
-         * original braindamaged IBM FERR coupling.
-         */
-        if (boot_cpu_data.hard_math && !cpu_has_fpu)
-                setup_irq(FPU_IRQ, &fpu_irq);
-
-        irq_ctx_init(smp_processor_id());
-}
diff --git a/arch/x86/kernel/i8259_64.c b/arch/x86/kernel/i8259_64.c
deleted file mode 100644
index fa57a1568508..000000000000
--- a/arch/x86/kernel/i8259_64.c
+++ /dev/null
@@ -1,512 +0,0 @@
-#include <linux/linkage.h>
-#include <linux/errno.h>
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/ioport.h>
-#include <linux/interrupt.h>
-#include <linux/timex.h>
-#include <linux/slab.h>
-#include <linux/random.h>
-#include <linux/init.h>
-#include <linux/kernel_stat.h>
-#include <linux/sysdev.h>
-#include <linux/bitops.h>
-
-#include <asm/acpi.h>
-#include <asm/atomic.h>
-#include <asm/system.h>
-#include <asm/io.h>
-#include <asm/hw_irq.h>
-#include <asm/pgtable.h>
-#include <asm/delay.h>
-#include <asm/desc.h>
-#include <asm/apic.h>
-#include <asm/i8259.h>
-
-/*
- * Common place to define all x86 IRQ vectors
- *
- * This builds up the IRQ handler stubs using some ugly macros in irq.h
- *
- * These macros create the low-level assembly IRQ routines that save
- * register context and call do_IRQ(). do_IRQ() then does all the
- * operations that are needed to keep the AT (or SMP IOAPIC)
- * interrupt-controller happy.
- */
-
-#define BI(x,y) \
-        BUILD_IRQ(x##y)
-
-#define BUILD_16_IRQS(x) \
-        BI(x,0) BI(x,1) BI(x,2) BI(x,3) \
-        BI(x,4) BI(x,5) BI(x,6) BI(x,7) \
-        BI(x,8) BI(x,9) BI(x,a) BI(x,b) \
-        BI(x,c) BI(x,d) BI(x,e) BI(x,f)
-
-/*
- * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts:
- * (these are usually mapped to vectors 0x30-0x3f)
- */
-
-/*
- * The IO-APIC gives us many more interrupt sources. Most of these
- * are unused but an SMP system is supposed to have enough memory ...
- * sometimes (mostly wrt. hw bugs) we get corrupted vectors all
- * across the spectrum, so we really want to be prepared to get all
- * of these. Plus, more powerful systems might have more than 64
- * IO-APIC registers.
- *
- * (these are usually mapped into the 0x30-0xff vector range)
- */
-                                      BUILD_16_IRQS(0x2) BUILD_16_IRQS(0x3)
-BUILD_16_IRQS(0x4) BUILD_16_IRQS(0x5) BUILD_16_IRQS(0x6) BUILD_16_IRQS(0x7)
-BUILD_16_IRQS(0x8) BUILD_16_IRQS(0x9) BUILD_16_IRQS(0xa) BUILD_16_IRQS(0xb)
-BUILD_16_IRQS(0xc) BUILD_16_IRQS(0xd) BUILD_16_IRQS(0xe) BUILD_16_IRQS(0xf)
-
-#undef BUILD_16_IRQS
-#undef BI
-
-
-#define IRQ(x,y) \
-        IRQ##x##y##_interrupt
-
-#define IRQLIST_16(x) \
-        IRQ(x,0), IRQ(x,1), IRQ(x,2), IRQ(x,3), \
-        IRQ(x,4), IRQ(x,5), IRQ(x,6), IRQ(x,7), \
-        IRQ(x,8), IRQ(x,9), IRQ(x,a), IRQ(x,b), \
-        IRQ(x,c), IRQ(x,d), IRQ(x,e), IRQ(x,f)
-
-/* for the irq vectors */
-static void (*__initdata interrupt[NR_VECTORS - FIRST_EXTERNAL_VECTOR])(void) = {
-                                          IRQLIST_16(0x2), IRQLIST_16(0x3),
-        IRQLIST_16(0x4), IRQLIST_16(0x5), IRQLIST_16(0x6), IRQLIST_16(0x7),
-        IRQLIST_16(0x8), IRQLIST_16(0x9), IRQLIST_16(0xa), IRQLIST_16(0xb),
-        IRQLIST_16(0xc), IRQLIST_16(0xd), IRQLIST_16(0xe), IRQLIST_16(0xf)
-};
-
-#undef IRQ
-#undef IRQLIST_16
-
-/*
- * This is the 'legacy' 8259A Programmable Interrupt Controller,
- * present in the majority of PC/AT boxes.
- * plus some generic x86 specific things if generic specifics makes
- * any sense at all.
- * this file should become arch/i386/kernel/irq.c when the old irq.c
- * moves to arch independent land
- */
-
-static int i8259A_auto_eoi;
-DEFINE_SPINLOCK(i8259A_lock);
-static void mask_and_ack_8259A(unsigned int);
-
-static struct irq_chip i8259A_chip = {
-        .name           = "XT-PIC",
-        .mask           = disable_8259A_irq,
-        .disable        = disable_8259A_irq,
-        .unmask         = enable_8259A_irq,
-        .mask_ack       = mask_and_ack_8259A,
-};
-
-/*
- * 8259A PIC functions to handle ISA devices:
- */
-
-/*
- * This contains the irq mask for both 8259A irq controllers,
- */
-unsigned int cached_irq_mask = 0xffff;
-
-/*
- * Not all IRQs can be routed through the IO-APIC, eg. on certain (older)
- * boards the timer interrupt is not really connected to any IO-APIC pin,
- * it's fed to the master 8259A's IR0 line only.
- *
- * Any '1' bit in this mask means the IRQ is routed through the IO-APIC.
- * this 'mixed mode' IRQ handling costs nothing because it's only used
- * at IRQ setup time.
- */
-unsigned long io_apic_irqs;
-
-void disable_8259A_irq(unsigned int irq)
-{
-        unsigned int mask = 1 << irq;
-        unsigned long flags;
-
-        spin_lock_irqsave(&i8259A_lock, flags);
-        cached_irq_mask |= mask;
-        if (irq & 8)
-                outb(cached_slave_mask, PIC_SLAVE_IMR);
-        else
-                outb(cached_master_mask, PIC_MASTER_IMR);
-        spin_unlock_irqrestore(&i8259A_lock, flags);
-}
-
-void enable_8259A_irq(unsigned int irq)
-{
-        unsigned int mask = ~(1 << irq);
-        unsigned long flags;
-
-        spin_lock_irqsave(&i8259A_lock, flags);
-        cached_irq_mask &= mask;
-        if (irq & 8)
-                outb(cached_slave_mask, PIC_SLAVE_IMR);
-        else
-                outb(cached_master_mask, PIC_MASTER_IMR);
-        spin_unlock_irqrestore(&i8259A_lock, flags);
-}
-
-int i8259A_irq_pending(unsigned int irq)
-{
-        unsigned int mask = 1<<irq;
-        unsigned long flags;
-        int ret;
-
-        spin_lock_irqsave(&i8259A_lock, flags);
-        if (irq < 8)
-                ret = inb(PIC_MASTER_CMD) & mask;
-        else
-                ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
-        spin_unlock_irqrestore(&i8259A_lock, flags);
-
-        return ret;
-}
-
-void make_8259A_irq(unsigned int irq)
-{
-        disable_irq_nosync(irq);
-        io_apic_irqs &= ~(1<<irq);
-        set_irq_chip_and_handler_name(irq, &i8259A_chip, handle_level_irq,
-                                      "XT");
-        enable_irq(irq);
-}
-
-/*
- * This function assumes to be called rarely. Switching between
- * 8259A registers is slow.
- * This has to be protected by the irq controller spinlock
- * before being called.
- */
-static inline int i8259A_irq_real(unsigned int irq)
-{
-        int value;
-        int irqmask = 1<<irq;
-
-        if (irq < 8) {
-                outb(0x0B,PIC_MASTER_CMD);      /* ISR register */
-                value = inb(PIC_MASTER_CMD) & irqmask;
-                outb(0x0A,PIC_MASTER_CMD);      /* back to the IRR register */
-                return value;
-        }
-        outb(0x0B,PIC_SLAVE_CMD);       /* ISR register */
-        value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
-        outb(0x0A,PIC_SLAVE_CMD);       /* back to the IRR register */
-        return value;
-}
-
-/*
- * Careful! The 8259A is a fragile beast, it pretty
- * much _has_ to be done exactly like this (mask it
- * first, _then_ send the EOI, and the order of EOI
- * to the two 8259s is important!
- */
-static void mask_and_ack_8259A(unsigned int irq)
-{
-        unsigned int irqmask = 1 << irq;
-        unsigned long flags;
-
-        spin_lock_irqsave(&i8259A_lock, flags);
-        /*
-         * Lightweight spurious IRQ detection. We do not want
-         * to overdo spurious IRQ handling - it's usually a sign
-         * of hardware problems, so we only do the checks we can
-         * do without slowing down good hardware unnecessarily.
-         *
-         * Note that IRQ7 and IRQ15 (the two spurious IRQs
-         * usually resulting from the 8259A-1|2 PICs) occur
-         * even if the IRQ is masked in the 8259A. Thus we
-         * can check spurious 8259A IRQs without doing the
-         * quite slow i8259A_irq_real() call for every IRQ.
-         * This does not cover 100% of spurious interrupts,
-         * but should be enough to warn the user that there
-         * is something bad going on ...
-         */
-        if (cached_irq_mask & irqmask)
-                goto spurious_8259A_irq;
-        cached_irq_mask |= irqmask;
-
-handle_real_irq:
-        if (irq & 8) {
-                inb(PIC_SLAVE_IMR);     /* DUMMY - (do we need this?) */
-                outb(cached_slave_mask, PIC_SLAVE_IMR);
-                /* 'Specific EOI' to slave */
-                outb(0x60+(irq&7),PIC_SLAVE_CMD);
-                 /* 'Specific EOI' to master-IRQ2 */
-                outb(0x60+PIC_CASCADE_IR,PIC_MASTER_CMD);
-        } else {
-                inb(PIC_MASTER_IMR);    /* DUMMY - (do we need this?) */
-                outb(cached_master_mask, PIC_MASTER_IMR);
-                /* 'Specific EOI' to master */
-                outb(0x60+irq,PIC_MASTER_CMD);
-        }
-        spin_unlock_irqrestore(&i8259A_lock, flags);
-        return;
-
-spurious_8259A_irq:
-        /*
-         * this is the slow path - should happen rarely.
-         */
-        if (i8259A_irq_real(irq))
-                /*
-                 * oops, the IRQ _is_ in service according to the
-                 * 8259A - not spurious, go handle it.
-                 */
-                goto handle_real_irq;
-
-        {
-                static int spurious_irq_mask;
-                /*
-                 * At this point we can be sure the IRQ is spurious,
-                 * lets ACK and report it. [once per IRQ]
-                 */
-                if (!(spurious_irq_mask & irqmask)) {
-                        printk(KERN_DEBUG
-                               "spurious 8259A interrupt: IRQ%d.\n", irq);
-                        spurious_irq_mask |= irqmask;
-                }
-                atomic_inc(&irq_err_count);
-                /*
-                 * Theoretically we do not have to handle this IRQ,
-                 * but in Linux this does not cause problems and is
-                 * simpler for us.
-                 */
-                goto handle_real_irq;
-        }
-}
-
-static char irq_trigger[2];
-/**
- * ELCR registers (0x4d0, 0x4d1) control edge/level of IRQ
- */
-static void restore_ELCR(char *trigger)
-{
-        outb(trigger[0], 0x4d0);
-        outb(trigger[1], 0x4d1);
-}
-
-static void save_ELCR(char *trigger)
-{
-        /* IRQ 0,1,2,8,13 are marked as reserved */
-        trigger[0] = inb(0x4d0) & 0xF8;
-        trigger[1] = inb(0x4d1) & 0xDE;
-}
-
-static int i8259A_resume(struct sys_device *dev)
-{
-        init_8259A(i8259A_auto_eoi);
-        restore_ELCR(irq_trigger);
-        return 0;
-}
-
-static int i8259A_suspend(struct sys_device *dev, pm_message_t state)
-{
-        save_ELCR(irq_trigger);
-        return 0;
-}
-
-static int i8259A_shutdown(struct sys_device *dev)
-{
-        /* Put the i8259A into a quiescent state that
-         * the kernel initialization code can get it
-         * out of.
-         */
-        outb(0xff, PIC_MASTER_IMR);     /* mask all of 8259A-1 */
-        outb(0xff, PIC_SLAVE_IMR);      /* mask all of 8259A-1 */
-        return 0;
-}
-
-static struct sysdev_class i8259_sysdev_class = {
-        .name = "i8259",
-        .suspend = i8259A_suspend,
-        .resume = i8259A_resume,
-        .shutdown = i8259A_shutdown,
-};
-
-static struct sys_device device_i8259A = {
-        .id     = 0,
-        .cls    = &i8259_sysdev_class,
-};
-
-static int __init i8259A_init_sysfs(void)
-{
-        int error = sysdev_class_register(&i8259_sysdev_class);
-        if (!error)
-                error = sysdev_register(&device_i8259A);
-        return error;
-}
-
-device_initcall(i8259A_init_sysfs);
-
-void init_8259A(int auto_eoi)
-{
-        unsigned long flags;
-
-        i8259A_auto_eoi = auto_eoi;
-
-        spin_lock_irqsave(&i8259A_lock, flags);
-
-        outb(0xff, PIC_MASTER_IMR);     /* mask all of 8259A-1 */
-        outb(0xff, PIC_SLAVE_IMR);      /* mask all of 8259A-2 */
-
-        /*
-         * outb_pic - this has to work on a wide range of PC hardware.
-         */
-        outb_pic(0x11, PIC_MASTER_CMD); /* ICW1: select 8259A-1 init */
-        /* ICW2: 8259A-1 IR0-7 mapped to 0x30-0x37 */
-        outb_pic(IRQ0_VECTOR, PIC_MASTER_IMR);
-        /* 8259A-1 (the master) has a slave on IR2 */
-        outb_pic(0x04, PIC_MASTER_IMR);
-        if (auto_eoi)   /* master does Auto EOI */
-                outb_pic(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR);
-        else            /* master expects normal EOI */
-                outb_pic(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);
-
-        outb_pic(0x11, PIC_SLAVE_CMD);  /* ICW1: select 8259A-2 init */
-        /* ICW2: 8259A-2 IR0-7 mapped to 0x38-0x3f */
-        outb_pic(IRQ8_VECTOR, PIC_SLAVE_IMR);
-        /* 8259A-2 is a slave on master's IR2 */
-        outb_pic(PIC_CASCADE_IR, PIC_SLAVE_IMR);
-        /* (slave's support for AEOI in flat mode is to be investigated) */
-        outb_pic(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR);
-
-        if (auto_eoi)
-                /*
-                 * In AEOI mode we just have to mask the interrupt
-                 * when acking.
-                 */
-                i8259A_chip.mask_ack = disable_8259A_irq;
-        else
-                i8259A_chip.mask_ack = mask_and_ack_8259A;
-
-        udelay(100);            /* wait for 8259A to initialize */
-
-        outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
-        outb(cached_slave_mask, PIC_SLAVE_IMR);   /* restore slave IRQ mask */
-
-        spin_unlock_irqrestore(&i8259A_lock, flags);
-}
-
-
-
-
-/*
- * IRQ2 is cascade interrupt to second interrupt controller
- */
-
-static struct irqaction irq2 = {
-        .handler = no_action,
-        .mask = CPU_MASK_NONE,
-        .name = "cascade",
-};
-DEFINE_PER_CPU(vector_irq_t, vector_irq) = {
-        [0 ... IRQ0_VECTOR - 1] = -1,
-        [IRQ0_VECTOR] = 0,
-        [IRQ1_VECTOR] = 1,
-        [IRQ2_VECTOR] = 2,
-        [IRQ3_VECTOR] = 3,
-        [IRQ4_VECTOR] = 4,
-        [IRQ5_VECTOR] = 5,
-        [IRQ6_VECTOR] = 6,
-        [IRQ7_VECTOR] = 7,
-        [IRQ8_VECTOR] = 8,
-        [IRQ9_VECTOR] = 9,
-        [IRQ10_VECTOR] = 10,
-        [IRQ11_VECTOR] = 11,
-        [IRQ12_VECTOR] = 12,
-        [IRQ13_VECTOR] = 13,
-        [IRQ14_VECTOR] = 14,
-        [IRQ15_VECTOR] = 15,
-        [IRQ15_VECTOR + 1 ... NR_VECTORS - 1] = -1
-};
-
-void __init init_ISA_irqs (void)
-{
-        int i;
-
-        init_bsp_APIC();
-        init_8259A(0);
-
-        for (i = 0; i < NR_IRQS; i++) {
-                irq_desc[i].status = IRQ_DISABLED;
-                irq_desc[i].action = NULL;
-                irq_desc[i].depth = 1;
-
-                if (i < 16) {
-                        /*
-                         * 16 old-style INTA-cycle interrupts:
-                         */
-                        set_irq_chip_and_handler_name(i, &i8259A_chip,
-                                                      handle_level_irq, "XT");
-                } else {
-                        /*
-                         * 'high' PCI IRQs filled in on demand
-                         */
-                        irq_desc[i].chip = &no_irq_chip;
-                }
-        }
-}
-
-void init_IRQ(void) __attribute__((weak, alias("native_init_IRQ")));
-
-void __init native_init_IRQ(void)
-{
-        int i;
-
-        init_ISA_irqs();
-        /*
-         * Cover the whole vector space, no vector can escape
-         * us. (some of these will be overridden and become
-         * 'special' SMP interrupts)
-         */
-        for (i = 0; i < (NR_VECTORS - FIRST_EXTERNAL_VECTOR); i++) {
-                int vector = FIRST_EXTERNAL_VECTOR + i;
-                if (vector != IA32_SYSCALL_VECTOR)
-                        set_intr_gate(vector, interrupt[i]);
-        }
-
-#ifdef CONFIG_SMP
-        /*
-         * The reschedule interrupt is a CPU-to-CPU reschedule-helper
-         * IPI, driven by wakeup.
-         */
-        set_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
-
-        /* IPIs for invalidation */
-        set_intr_gate(INVALIDATE_TLB_VECTOR_START+0, invalidate_interrupt0);
-        set_intr_gate(INVALIDATE_TLB_VECTOR_START+1, invalidate_interrupt1);
-        set_intr_gate(INVALIDATE_TLB_VECTOR_START+2, invalidate_interrupt2);
-        set_intr_gate(INVALIDATE_TLB_VECTOR_START+3, invalidate_interrupt3);
-        set_intr_gate(INVALIDATE_TLB_VECTOR_START+4, invalidate_interrupt4);
-        set_intr_gate(INVALIDATE_TLB_VECTOR_START+5, invalidate_interrupt5);
-        set_intr_gate(INVALIDATE_TLB_VECTOR_START+6, invalidate_interrupt6);
-        set_intr_gate(INVALIDATE_TLB_VECTOR_START+7, invalidate_interrupt7);
-
-        /* IPI for generic function call */
-        set_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
-
-        /* Low priority IPI to cleanup after moving an irq */
-        set_intr_gate(IRQ_MOVE_CLEANUP_VECTOR, irq_move_cleanup_interrupt);
-#endif
-        set_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
-        set_intr_gate(THRESHOLD_APIC_VECTOR, threshold_interrupt);
-
-        /* self generated IPI for local APIC timer */
-        set_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
-
-        /* IPI vectors for APIC spurious and error interrupts */
-        set_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
-        set_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
-
-        if (!acpi_ioapic)
-                setup_irq(2, &irq2);
-}
diff --git a/arch/x86/kernel/io_apic_32.c b/arch/x86/kernel/io_apic_32.c
index 4dc8600d9d20..603261a5885c 100644
--- a/arch/x86/kernel/io_apic_32.c
+++ b/arch/x86/kernel/io_apic_32.c
@@ -25,6 +25,7 @@
 #include <linux/init.h>
 #include <linux/delay.h>
 #include <linux/sched.h>
+#include <linux/bootmem.h>
 #include <linux/mc146818rtc.h>
 #include <linux/compiler.h>
 #include <linux/acpi.h>
@@ -58,7 +59,7 @@ static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
 static DEFINE_SPINLOCK(ioapic_lock);
 static DEFINE_SPINLOCK(vector_lock);
 
-int timer_over_8254 __initdata = 1;
+int timer_through_8259 __initdata;
 
 /*
  *      Is the SiS APIC rmw bug present ?
@@ -72,15 +73,21 @@ int sis_apic_bug = -1;
 int nr_ioapic_registers[MAX_IO_APICS];
 
 /* I/O APIC entries */
-struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
+struct mp_config_ioapic mp_ioapics[MAX_IO_APICS];
 int nr_ioapics;
 
 /* MP IRQ source entries */
-struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
+struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
 
 /* # of MP IRQ source entries */
 int mp_irq_entries;
 
+#if defined (CONFIG_MCA) || defined (CONFIG_EISA)
+int mp_bus_id_to_type[MAX_MP_BUSSES];
+#endif
+
+DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
+
 static int disable_timer_pin_1 __initdata;
 
 /*
@@ -110,7 +117,7 @@ struct io_apic {
 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
 {
         return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
-                + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
+                + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK);
 }
 
 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
@@ -239,7 +246,7 @@ static void __init replace_pin_at_irq(unsigned int irq,
         }
 }
 
-static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
+static void __modify_IO_APIC_irq(unsigned int irq, unsigned long enable, unsigned long disable)
 {
         struct irq_pin_list *entry = irq_2_pin + irq;
         unsigned int pin, reg;
@@ -259,30 +266,32 @@ static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsign
 }
 
 /* mask = 1 */
-static void __mask_IO_APIC_irq (unsigned int irq)
+static void __mask_IO_APIC_irq(unsigned int irq)
 {
-        __modify_IO_APIC_irq(irq, 0x00010000, 0);
+        __modify_IO_APIC_irq(irq, IO_APIC_REDIR_MASKED, 0);
 }
 
 /* mask = 0 */
-static void __unmask_IO_APIC_irq (unsigned int irq)
+static void __unmask_IO_APIC_irq(unsigned int irq)
 {
-        __modify_IO_APIC_irq(irq, 0, 0x00010000);
+        __modify_IO_APIC_irq(irq, 0, IO_APIC_REDIR_MASKED);
 }
 
 /* mask = 1, trigger = 0 */
-static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
+static void __mask_and_edge_IO_APIC_irq(unsigned int irq)
 {
-        __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
+        __modify_IO_APIC_irq(irq, IO_APIC_REDIR_MASKED,
+                                IO_APIC_REDIR_LEVEL_TRIGGER);
 }
 
 /* mask = 0, trigger = 1 */
-static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
+static void __unmask_and_level_IO_APIC_irq(unsigned int irq)
 {
-        __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
+        __modify_IO_APIC_irq(irq, IO_APIC_REDIR_LEVEL_TRIGGER,
+                                IO_APIC_REDIR_MASKED);
 }
 
-static void mask_IO_APIC_irq (unsigned int irq)
+static void mask_IO_APIC_irq(unsigned int irq)
 {
         unsigned long flags;
 
@@ -291,7 +300,7 @@ static void mask_IO_APIC_irq (unsigned int irq)
         spin_unlock_irqrestore(&ioapic_lock, flags);
 }
 
-static void unmask_IO_APIC_irq (unsigned int irq)
+static void unmask_IO_APIC_irq(unsigned int irq)
 {
         unsigned long flags;
 
@@ -303,7 +312,7 @@ static void unmask_IO_APIC_irq (unsigned int irq)
 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 {
         struct IO_APIC_route_entry entry;
-        
+
         /* Check delivery_mode to be sure we're not clearing an SMI pin */
         entry = ioapic_read_entry(apic, pin);
         if (entry.delivery_mode == dest_SMI)
@@ -315,7 +324,7 @@ static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
         ioapic_mask_entry(apic, pin);
 }
 
-static void clear_IO_APIC (void)
+static void clear_IO_APIC(void)
 {
         int apic, pin;
 
@@ -332,7 +341,7 @@ static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
         struct irq_pin_list *entry = irq_2_pin + irq;
         unsigned int apicid_value;
         cpumask_t tmp;
-        
+
         cpus_and(tmp, cpumask, cpu_online_map);
         if (cpus_empty(tmp))
                 tmp = TARGET_CPUS;
@@ -361,7 +370,7 @@ static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
 # include <linux/kernel_stat.h> /* kstat */
 # include <linux/slab.h>                /* kmalloc() */
 # include <linux/timer.h>
- 
+
 #define IRQBALANCE_CHECK_ARCH -999
 #define MAX_BALANCED_IRQ_INTERVAL       (5*HZ)
 #define MIN_BALANCED_IRQ_INTERVAL       (HZ/2)
@@ -373,14 +382,14 @@ static int physical_balance __read_mostly;
 static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL;
 
 static struct irq_cpu_info {
-        unsigned long * last_irq;
-        unsigned long * irq_delta;
+        unsigned long *last_irq;
+        unsigned long *irq_delta;
         unsigned long irq;
 } irq_cpu_data[NR_CPUS];
 
 #define CPU_IRQ(cpu)            (irq_cpu_data[cpu].irq)
-#define LAST_CPU_IRQ(cpu,irq)   (irq_cpu_data[cpu].last_irq[irq])
-#define IRQ_DELTA(cpu,irq)      (irq_cpu_data[cpu].irq_delta[irq])
+#define LAST_CPU_IRQ(cpu, irq)   (irq_cpu_data[cpu].last_irq[irq])
+#define IRQ_DELTA(cpu, irq)     (irq_cpu_data[cpu].irq_delta[irq])
 
 #define IDLE_ENOUGH(cpu,now) \
         (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
@@ -419,8 +428,8 @@ inside:
                         if (cpu == -1)
                                 cpu = NR_CPUS-1;
                 }
-        } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
-                        (search_idle && !IDLE_ENOUGH(cpu,now)));
+        } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu, allowed_mask) ||
+                        (search_idle && !IDLE_ENOUGH(cpu, now)));
 
         return cpu;
 }
@@ -430,15 +439,14 @@ static inline void balance_irq(int cpu, int irq)
         unsigned long now = jiffies;
         cpumask_t allowed_mask;
         unsigned int new_cpu;
-                
+
         if (irqbalance_disabled)
-                return; 
+                return;
 
         cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]);
         new_cpu = move(cpu, allowed_mask, now, 1);
-        if (cpu != new_cpu) {
+        if (cpu != new_cpu)
                 set_pending_irq(irq, cpumask_of_cpu(new_cpu));
-        }
 }
 
 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
@@ -450,14 +458,14 @@ static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
                         if (!irq_desc[j].action)
                                 continue;
                         /* Is it a significant load ?  */
-                        if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
+                        if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i), j) <
                                                 useful_load_threshold)
                                 continue;
                         balance_irq(i, j);
                 }
         }
         balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
-                balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);       
+                balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
         return;
 }
 
@@ -486,22 +494,22 @@ static void do_irq_balance(void)
                         /* Is this an active IRQ or balancing disabled ? */
                         if (!irq_desc[j].action || irq_balancing_disabled(j))
                                 continue;
-                        if ( package_index == i )
-                                IRQ_DELTA(package_index,j) = 0;
+                        if (package_index == i)
+                                IRQ_DELTA(package_index, j) = 0;
                         /* Determine the total count per processor per IRQ */
                         value_now = (unsigned long) kstat_cpu(i).irqs[j];
 
                         /* Determine the activity per processor per IRQ */
-                        delta = value_now - LAST_CPU_IRQ(i,j);
+                        delta = value_now - LAST_CPU_IRQ(i, j);
 
                         /* Update last_cpu_irq[][] for the next time */
-                        LAST_CPU_IRQ(i,j) = value_now;
+                        LAST_CPU_IRQ(i, j) = value_now;
 
                         /* Ignore IRQs whose rate is less than the clock */
                         if (delta < useful_load_threshold)
                                 continue;
                         /* update the load for the processor or package total */
-                        IRQ_DELTA(package_index,j) += delta;
+                        IRQ_DELTA(package_index, j) += delta;
 
                         /* Keep track of the higher numbered sibling as well */
                         if (i != package_index)
@@ -527,7 +535,8 @@ static void do_irq_balance(void)
         max_cpu_irq = ULONG_MAX;
 
 tryanothercpu:
-        /* Look for heaviest loaded processor.
+        /*
+         * Look for heaviest loaded processor.
          * We may come back to get the next heaviest loaded processor.
          * Skip processors with trivial loads.
          */
@@ -536,7 +545,7 @@ tryanothercpu:
         for_each_online_cpu(i) {
                 if (i != CPU_TO_PACKAGEINDEX(i))
                         continue;
-                if (max_cpu_irq <= CPU_IRQ(i)) 
+                if (max_cpu_irq <= CPU_IRQ(i))
                         continue;
                 if (tmp_cpu_irq < CPU_IRQ(i)) {
                         tmp_cpu_irq = CPU_IRQ(i);
@@ -545,8 +554,9 @@ tryanothercpu:
         }
 
         if (tmp_loaded == -1) {
-         /* In the case of small number of heavy interrupt sources, 
-          * loading some of the cpus too much. We use Ingo's original 
+         /*
+          * In the case of small number of heavy interrupt sources,
+          * loading some of the cpus too much. We use Ingo's original
           * approach to rotate them around.
           */
                 if (!first_attempt && imbalance >= useful_load_threshold) {
@@ -555,13 +565,14 @@ tryanothercpu:
                 }
                 goto not_worth_the_effort;
         }
-        
+
         first_attempt = 0;              /* heaviest search */
         max_cpu_irq = tmp_cpu_irq;      /* load */
         max_loaded = tmp_loaded;        /* processor */
         imbalance = (max_cpu_irq - min_cpu_irq) / 2;
-        
-        /* if imbalance is less than approx 10% of max load, then
+
+        /*
+         * if imbalance is less than approx 10% of max load, then
          * observe diminishing returns action. - quit
          */
         if (imbalance < (max_cpu_irq >> 3))
@@ -577,26 +588,25 @@ tryanotherirq:
                 /* Is this an active IRQ? */
                 if (!irq_desc[j].action)
                         continue;
-                if (imbalance <= IRQ_DELTA(max_loaded,j))
+                if (imbalance <= IRQ_DELTA(max_loaded, j))
                         continue;
                 /* Try to find the IRQ that is closest to the imbalance
                  * without going over.
                  */
-                if (move_this_load < IRQ_DELTA(max_loaded,j)) {
-                        move_this_load = IRQ_DELTA(max_loaded,j);
+                if (move_this_load < IRQ_DELTA(max_loaded, j)) {
+                        move_this_load = IRQ_DELTA(max_loaded, j);
                         selected_irq = j;
                 }
         }
-        if (selected_irq == -1) {
+        if (selected_irq == -1)
                 goto tryanothercpu;
-        }
 
         imbalance = move_this_load;
-        
+
         /* For physical_balance case, we accumulated both load
          * values in the one of the siblings cpu_irq[],
          * to use the same code for physical and logical processors
-         * as much as possible. 
+         * as much as possible.
          *
          * NOTE: the cpu_irq[] array holds the sum of the load for
          * sibling A and sibling B in the slot for the lowest numbered
@@ -625,11 +635,11 @@ tryanotherirq:
                 /* mark for change destination */
                 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
 
-                /* Since we made a change, come back sooner to 
+                /* Since we made a change, come back sooner to
                  * check for more variation.
                  */
                 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
-                        balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);       
+                        balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
                 return;
         }
         goto tryanotherirq;
@@ -640,7 +650,7 @@ not_worth_the_effort:
          * upward
          */
         balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
-                balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);       
+                balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
         return;
 }
 
@@ -679,13 +689,13 @@ static int __init balanced_irq_init(void)
         cpumask_t tmp;
 
         cpus_shift_right(tmp, cpu_online_map, 2);
-        c = &boot_cpu_data;
+        c = &boot_cpu_data;
         /* When not overwritten by the command line ask subarchitecture. */
         if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
                 irqbalance_disabled = NO_BALANCE_IRQ;
         if (irqbalance_disabled)
                 return 0;
-        
+
          /* disable irqbalance completely if there is only one processor online */
         if (num_online_cpus() < 2) {
                 irqbalance_disabled = 1;
@@ -699,16 +709,14 @@ static int __init balanced_irq_init(void)
                 physical_balance = 1;
 
         for_each_online_cpu(i) {
-                irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
-                irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
+                irq_cpu_data[i].irq_delta = kzalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
+                irq_cpu_data[i].last_irq = kzalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
                 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
                         printk(KERN_ERR "balanced_irq_init: out of memory");
                         goto failed;
                 }
-                memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
-                memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
         }
-        
+
         printk(KERN_INFO "Starting balanced_irq\n");
         if (!IS_ERR(kthread_run(balanced_irq, NULL, "kirqd")))
                 return 0;
@@ -801,10 +809,10 @@ static int find_irq_entry(int apic, int pin, int type)
         int i;
 
         for (i = 0; i < mp_irq_entries; i++)
-                if (mp_irqs[i].mpc_irqtype == type &&
-                    (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
-                     mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
-                    mp_irqs[i].mpc_dstirq == pin)
+                if (mp_irqs[i].mp_irqtype == type &&
+                    (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid ||
+                     mp_irqs[i].mp_dstapic == MP_APIC_ALL) &&
+                    mp_irqs[i].mp_dstirq == pin)
                         return i;
 
         return -1;
@@ -818,13 +826,13 @@ static int __init find_isa_irq_pin(int irq, int type)
         int i;
 
         for (i = 0; i < mp_irq_entries; i++) {
-                int lbus = mp_irqs[i].mpc_srcbus;
+                int lbus = mp_irqs[i].mp_srcbus;
 
                 if (test_bit(lbus, mp_bus_not_pci) &&
-                    (mp_irqs[i].mpc_irqtype == type) &&
-                    (mp_irqs[i].mpc_srcbusirq == irq))
+                    (mp_irqs[i].mp_irqtype == type) &&
+                    (mp_irqs[i].mp_srcbusirq == irq))
 
-                        return mp_irqs[i].mpc_dstirq;
+                        return mp_irqs[i].mp_dstirq;
         }
         return -1;
 }
@@ -834,17 +842,17 @@ static int __init find_isa_irq_apic(int irq, int type)
         int i;
 
         for (i = 0; i < mp_irq_entries; i++) {
-                int lbus = mp_irqs[i].mpc_srcbus;
+                int lbus = mp_irqs[i].mp_srcbus;
 
                 if (test_bit(lbus, mp_bus_not_pci) &&
-                    (mp_irqs[i].mpc_irqtype == type) &&
-                    (mp_irqs[i].mpc_srcbusirq == irq))
+                    (mp_irqs[i].mp_irqtype == type) &&
+                    (mp_irqs[i].mp_srcbusirq == irq))
                         break;
         }
         if (i < mp_irq_entries) {
                 int apic;
-                for(apic = 0; apic < nr_ioapics; apic++) {
-                        if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
+                for (apic = 0; apic < nr_ioapics; apic++) {
+                        if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic)
                                 return apic;
                 }
         }
@@ -864,28 +872,28 @@ int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 
         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
                 "slot:%d, pin:%d.\n", bus, slot, pin);
-        if (mp_bus_id_to_pci_bus[bus] == -1) {
+        if (test_bit(bus, mp_bus_not_pci)) {
                 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
                 return -1;
         }
         for (i = 0; i < mp_irq_entries; i++) {
-                int lbus = mp_irqs[i].mpc_srcbus;
+                int lbus = mp_irqs[i].mp_srcbus;
 
                 for (apic = 0; apic < nr_ioapics; apic++)
-                        if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
-                            mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
+                        if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic ||
+                            mp_irqs[i].mp_dstapic == MP_APIC_ALL)
                                 break;
 
                 if (!test_bit(lbus, mp_bus_not_pci) &&
-                    !mp_irqs[i].mpc_irqtype &&
+                    !mp_irqs[i].mp_irqtype &&
                     (bus == lbus) &&
-                    (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
-                        int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
+                    (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) {
+                        int irq = pin_2_irq(i, apic, mp_irqs[i].mp_dstirq);
 
                         if (!(apic || IO_APIC_IRQ(irq)))
                                 continue;
 
-                        if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
+                        if (pin == (mp_irqs[i].mp_srcbusirq & 3))
                                 return irq;
                         /*
                          * Use the first all-but-pin matching entry as a
@@ -900,7 +908,7 @@ int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
 
 /*
- * This function currently is only a helper for the i386 smp boot process where 
+ * This function currently is only a helper for the i386 smp boot process where
  * we need to reprogram the ioredtbls to cater for the cpus which have come online
  * so mask in all cases should simply be TARGET_CPUS
  */
@@ -952,7 +960,7 @@ static int EISA_ELCR(unsigned int irq)
  * EISA conforming in the MP table, that means its trigger type must
  * be read in from the ELCR */
 
-#define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
+#define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mp_srcbusirq))
 #define default_EISA_polarity(idx)      default_ISA_polarity(idx)
 
 /* PCI interrupts are always polarity one level triggered,
@@ -969,118 +977,115 @@ static int EISA_ELCR(unsigned int irq)
 
 static int MPBIOS_polarity(int idx)
 {
-        int bus = mp_irqs[idx].mpc_srcbus;
+        int bus = mp_irqs[idx].mp_srcbus;
         int polarity;
 
         /*
          * Determine IRQ line polarity (high active or low active):
          */
-        switch (mp_irqs[idx].mpc_irqflag & 3)
+        switch (mp_irqs[idx].mp_irqflag & 3) {
+        case 0: /* conforms, ie. bus-type dependent polarity */
         {
-                case 0: /* conforms, ie. bus-type dependent polarity */
-                {
-                        polarity = test_bit(bus, mp_bus_not_pci)?
-                                default_ISA_polarity(idx):
-                                default_PCI_polarity(idx);
-                        break;
-                }
-                case 1: /* high active */
-                {
-                        polarity = 0;
-                        break;
-                }
-                case 2: /* reserved */
-                {
-                        printk(KERN_WARNING "broken BIOS!!\n");
-                        polarity = 1;
-                        break;
-                }
-                case 3: /* low active */
-                {
-                        polarity = 1;
-                        break;
-                }
-                default: /* invalid */
-                {
-                        printk(KERN_WARNING "broken BIOS!!\n");
-                        polarity = 1;
-                        break;
-                }
+                polarity = test_bit(bus, mp_bus_not_pci)?
+                        default_ISA_polarity(idx):
+                        default_PCI_polarity(idx);
+                break;
+        }
+        case 1: /* high active */
+        {
+                polarity = 0;
+                break;
+        }
+        case 2: /* reserved */
+        {
+                printk(KERN_WARNING "broken BIOS!!\n");
+                polarity = 1;
+                break;
+        }
+        case 3: /* low active */
+        {
+                polarity = 1;
+                break;
+        }
+        default: /* invalid */
+        {
+                printk(KERN_WARNING "broken BIOS!!\n");
+                polarity = 1;
+                break;
+        }
         }
         return polarity;
 }
 
 static int MPBIOS_trigger(int idx)
 {
-        int bus = mp_irqs[idx].mpc_srcbus;
+        int bus = mp_irqs[idx].mp_srcbus;
         int trigger;
 
         /*
          * Determine IRQ trigger mode (edge or level sensitive):
          */
-        switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
+        switch ((mp_irqs[idx].mp_irqflag>>2) & 3) {
+        case 0: /* conforms, ie. bus-type dependent */
         {
-                case 0: /* conforms, ie. bus-type dependent */
-                {
-                        trigger = test_bit(bus, mp_bus_not_pci)?
-                                        default_ISA_trigger(idx):
-                                        default_PCI_trigger(idx);
+                trigger = test_bit(bus, mp_bus_not_pci)?
+                                default_ISA_trigger(idx):
+                                default_PCI_trigger(idx);
 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
-                        switch (mp_bus_id_to_type[bus])
-                        {
-                                case MP_BUS_ISA: /* ISA pin */
-                                {
-                                        /* set before the switch */
-                                        break;
-                                }
-                                case MP_BUS_EISA: /* EISA pin */
-                                {
-                                        trigger = default_EISA_trigger(idx);
-                                        break;
-                                }
-                                case MP_BUS_PCI: /* PCI pin */
-                                {
-                                        /* set before the switch */
-                                        break;
-                                }
-                                case MP_BUS_MCA: /* MCA pin */
-                                {
-                                        trigger = default_MCA_trigger(idx);
-                                        break;
-                                }
-                                default:
-                                {
-                                        printk(KERN_WARNING "broken BIOS!!\n");
-                                        trigger = 1;
-                                        break;
-                                }
-                        }
-#endif
+                switch (mp_bus_id_to_type[bus]) {
+                case MP_BUS_ISA: /* ISA pin */
+                {
+                        /* set before the switch */
                         break;
                 }
-                case 1: /* edge */
+                case MP_BUS_EISA: /* EISA pin */
                 {
-                        trigger = 0;
+                        trigger = default_EISA_trigger(idx);
                         break;
                 }
-                case 2: /* reserved */
+                case MP_BUS_PCI: /* PCI pin */
                 {
-                        printk(KERN_WARNING "broken BIOS!!\n");
-                        trigger = 1;
+                        /* set before the switch */
                         break;
                 }
-                case 3: /* level */
+                case MP_BUS_MCA: /* MCA pin */
                 {
-                        trigger = 1;
+                        trigger = default_MCA_trigger(idx);
                         break;
                 }
-                default: /* invalid */
+                default:
                 {
                         printk(KERN_WARNING "broken BIOS!!\n");
-                        trigger = 0;
+                        trigger = 1;
                         break;
                 }
         }
+#endif
+                break;
+        }
+        case 1: /* edge */
+        {
+                trigger = 0;
+                break;
+        }
+        case 2: /* reserved */
+        {
+                printk(KERN_WARNING "broken BIOS!!\n");
+                trigger = 1;
+                break;
+        }
+        case 3: /* level */
+        {
+                trigger = 1;
+                break;
+        }
+        default: /* invalid */
+        {
+                printk(KERN_WARNING "broken BIOS!!\n");
+                trigger = 0;
+                break;
+        }
+        }
         return trigger;
 }
 
@@ -1097,16 +1102,16 @@ static inline int irq_trigger(int idx)
 static int pin_2_irq(int idx, int apic, int pin)
 {
         int irq, i;
-        int bus = mp_irqs[idx].mpc_srcbus;
+        int bus = mp_irqs[idx].mp_srcbus;
 
         /*
          * Debugging check, we are in big trouble if this message pops up!
          */
-        if (mp_irqs[idx].mpc_dstirq != pin)
+        if (mp_irqs[idx].mp_dstirq != pin)
                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
 
         if (test_bit(bus, mp_bus_not_pci))
-                irq = mp_irqs[idx].mpc_srcbusirq;
+                irq = mp_irqs[idx].mp_srcbusirq;
         else {
                 /*
                  * PCI IRQs are mapped in order
@@ -1148,8 +1153,8 @@ static inline int IO_APIC_irq_trigger(int irq)
 
         for (apic = 0; apic < nr_ioapics; apic++) {
                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
-                        idx = find_irq_entry(apic,pin,mp_INT);
-                        if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
+                        idx = find_irq_entry(apic, pin, mp_INT);
+                        if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
                                 return irq_trigger(idx);
                 }
         }
@@ -1164,7 +1169,7 @@ static u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 }
 
 static int __assign_irq_vector(int irq)
 {
-        static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
+        static int current_vector = FIRST_DEVICE_VECTOR, current_offset;
         int vector, offset;
 
         BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
@@ -1176,7 +1181,7 @@ static int __assign_irq_vector(int irq)
         offset = current_offset;
 next:
         vector += 8;
-        if (vector >= FIRST_SYSTEM_VECTOR) {
+        if (vector >= first_system_vector) {
                 offset = (offset + 1) % 8;
                 vector = FIRST_DEVICE_VECTOR + offset;
         }
@@ -1203,6 +1208,11 @@ static int assign_irq_vector(int irq)
 
         return vector;
 }
+
+void setup_vector_irq(int cpu)
+{
+}
+
 static struct irq_chip ioapic_chip;
 
 #define IOAPIC_AUTO     -1
@@ -1237,25 +1247,25 @@ static void __init setup_IO_APIC_irqs(void)
                 /*
                  * add it to the IO-APIC irq-routing table:
                  */
-                memset(&entry,0,sizeof(entry));
+                memset(&entry, 0, sizeof(entry));
 
                 entry.delivery_mode = INT_DELIVERY_MODE;
                 entry.dest_mode = INT_DEST_MODE;
                 entry.mask = 0;                         /* enable IRQ */
-                entry.dest.logical.logical_dest = 
+                entry.dest.logical.logical_dest =
                                         cpu_mask_to_apicid(TARGET_CPUS);
 
-                idx = find_irq_entry(apic,pin,mp_INT);
+                idx = find_irq_entry(apic, pin, mp_INT);
                 if (idx == -1) {
                         if (first_notcon) {
                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
                                                 " IO-APIC (apicid-pin) %d-%d",
-                                                mp_ioapics[apic].mpc_apicid,
+                                                mp_ioapics[apic].mp_apicid,
                                                 pin);
                                 first_notcon = 0;
                         } else
                                 apic_printk(APIC_VERBOSE, ", %d-%d",
-                                        mp_ioapics[apic].mpc_apicid, pin);
+                                        mp_ioapics[apic].mp_apicid, pin);
                         continue;
                 }
 
@@ -1289,7 +1299,7 @@ static void __init setup_IO_APIC_irqs(void)
                         vector = assign_irq_vector(irq);
                         entry.vector = vector;
                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
-                
+
                         if (!apic && (irq < 16))
                                 disable_8259A_irq(irq);
                 }
@@ -1302,25 +1312,21 @@ static void __init setup_IO_APIC_irqs(void)
 }
 
 /*
- * Set up the 8259A-master output pin:
+ * Set up the timer pin, possibly with the 8259A-master behind.
  */
-static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
+static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
+                                        int vector)
 {
         struct IO_APIC_route_entry entry;
 
-        memset(&entry,0,sizeof(entry));
-
-        disable_8259A_irq(0);
-
-        /* mask LVT0 */
-        apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
+        memset(&entry, 0, sizeof(entry));
 
         /*
          * We use logical delivery to get the timer IRQ
          * to the first CPU.
          */
         entry.dest_mode = INT_DEST_MODE;
-        entry.mask = 0;                                 /* unmask IRQ now */
+        entry.mask = 1;                                 /* mask IRQ now */
         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
         entry.delivery_mode = INT_DELIVERY_MODE;
         entry.polarity = 0;
@@ -1329,17 +1335,14 @@ static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, in
 
         /*
          * The timer IRQ doesn't have to know that behind the
-         * scene we have a 8259A-master in AEOI mode ...
+         * scene we may have a 8259A-master in AEOI mode ...
          */
-        irq_desc[0].chip = &ioapic_chip;
-        set_irq_handler(0, handle_edge_irq);
+        ioapic_register_intr(0, vector, IOAPIC_EDGE);
 
         /*
          * Add it to the IO-APIC irq-routing table:
          */
         ioapic_write_entry(apic, pin, entry);
-
-        enable_8259A_irq(0);
 }
 
 void __init print_IO_APIC(void)
@@ -1354,10 +1357,10 @@ void __init print_IO_APIC(void)
         if (apic_verbosity == APIC_QUIET)
                 return;
 
-        printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
+        printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
         for (i = 0; i < nr_ioapics; i++)
                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
-                       mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
+                       mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]);
 
         /*
          * We are a bit conservative about what we expect.  We have to
@@ -1376,7 +1379,7 @@ void __init print_IO_APIC(void)
                 reg_03.raw = io_apic_read(apic, 3);
         spin_unlock_irqrestore(&ioapic_lock, flags);
 
-        printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
+        printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid);
         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
         printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
@@ -1459,7 +1462,7 @@ void __init print_IO_APIC(void)
 
 #if 0
 
-static void print_APIC_bitfield (int base)
+static void print_APIC_bitfield(int base)
 {
         unsigned int v;
         int i, j;
@@ -1480,7 +1483,7 @@ static void print_APIC_bitfield (int base)
         }
 }
 
-void /*__init*/ print_local_APIC(void * dummy)
+void /*__init*/ print_local_APIC(void *dummy)
 {
         unsigned int v, ver, maxlvt;
 
@@ -1489,6 +1492,7 @@ void /*__init*/ print_local_APIC(void * dummy)
 
         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
                 smp_processor_id(), hard_smp_processor_id());
+        v = apic_read(APIC_ID);
         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v,
                         GET_APIC_ID(read_apic_id()));
         v = apic_read(APIC_LVR);
@@ -1563,7 +1567,7 @@ void /*__init*/ print_local_APIC(void * dummy)
         printk("\n");
 }
 
-void print_all_local_APICs (void)
+void print_all_local_APICs(void)
 {
         on_each_cpu(print_local_APIC, NULL, 1, 1);
 }
@@ -1586,11 +1590,11 @@ void /*__init*/ print_PIC(void)
         v = inb(0xa0) << 8 | inb(0x20);
         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
 
-        outb(0x0b,0xa0);
-        outb(0x0b,0x20);
+        outb(0x0b, 0xa0);
+        outb(0x0b, 0x20);
         v = inb(0xa0) << 8 | inb(0x20);
-        outb(0x0a,0xa0);
-        outb(0x0a,0x20);
+        outb(0x0a, 0xa0);
+        outb(0x0a, 0x20);
 
         spin_unlock_irqrestore(&i8259A_lock, flags);
 
@@ -1626,7 +1630,7 @@ static void __init enable_IO_APIC(void)
                 spin_unlock_irqrestore(&ioapic_lock, flags);
                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
         }
-        for(apic = 0; apic < nr_ioapics; apic++) {
+        for (apic = 0; apic < nr_ioapics; apic++) {
                 int pin;
                 /* See if any of the pins is in ExtINT mode */
                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
@@ -1716,7 +1720,6 @@ void disable_IO_APIC(void)
  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
  */
 
-#ifndef CONFIG_X86_NUMAQ
 static void __init setup_ioapic_ids_from_mpc(void)
 {
         union IO_APIC_reg_00 reg_00;
@@ -1726,6 +1729,11 @@ static void __init setup_ioapic_ids_from_mpc(void)
         unsigned char old_id;
         unsigned long flags;
 
+#ifdef CONFIG_X86_NUMAQ
+        if (found_numaq)
+                return;
+#endif
+
         /*
          * Don't check I/O APIC IDs for xAPIC systems.  They have
          * no meaning without the serial APIC bus.
@@ -1748,15 +1756,15 @@ static void __init setup_ioapic_ids_from_mpc(void)
                 spin_lock_irqsave(&ioapic_lock, flags);
                 reg_00.raw = io_apic_read(apic, 0);
                 spin_unlock_irqrestore(&ioapic_lock, flags);
-                
-                old_id = mp_ioapics[apic].mpc_apicid;
 
-                if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
+                old_id = mp_ioapics[apic].mp_apicid;
+
+                if (mp_ioapics[apic].mp_apicid >= get_physical_broadcast()) {
                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
-                                apic, mp_ioapics[apic].mpc_apicid);
+                                apic, mp_ioapics[apic].mp_apicid);
                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
                                 reg_00.bits.ID);
-                        mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
+                        mp_ioapics[apic].mp_apicid = reg_00.bits.ID;
                 }
 
                 /*
@@ -1765,9 +1773,9 @@ static void __init setup_ioapic_ids_from_mpc(void)
                  * 'stuck on smp_invalidate_needed IPI wait' messages.
                  */
                 if (check_apicid_used(phys_id_present_map,
-                                        mp_ioapics[apic].mpc_apicid)) {
+                                        mp_ioapics[apic].mp_apicid)) {
                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
-                                apic, mp_ioapics[apic].mpc_apicid);
+                                apic, mp_ioapics[apic].mp_apicid);
                         for (i = 0; i < get_physical_broadcast(); i++)
                                 if (!physid_isset(i, phys_id_present_map))
                                         break;
@@ -1776,13 +1784,13 @@ static void __init setup_ioapic_ids_from_mpc(void)
                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
                                 i);
                         physid_set(i, phys_id_present_map);
-                        mp_ioapics[apic].mpc_apicid = i;
+                        mp_ioapics[apic].mp_apicid = i;
                 } else {
                         physid_mask_t tmp;
-                        tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
+                        tmp = apicid_to_cpu_present(mp_ioapics[apic].mp_apicid);
                         apic_printk(APIC_VERBOSE, "Setting %d in the "
                                         "phys_id_present_map\n",
-                                        mp_ioapics[apic].mpc_apicid);
+                                        mp_ioapics[apic].mp_apicid);
                         physids_or(phys_id_present_map, phys_id_present_map, tmp);
                 }
 
@@ -1791,21 +1799,21 @@ static void __init setup_ioapic_ids_from_mpc(void)
                  * We need to adjust the IRQ routing table
                  * if the ID changed.
                  */
-                if (old_id != mp_ioapics[apic].mpc_apicid)
+                if (old_id != mp_ioapics[apic].mp_apicid)
                         for (i = 0; i < mp_irq_entries; i++)
-                                if (mp_irqs[i].mpc_dstapic == old_id)
-                                        mp_irqs[i].mpc_dstapic
-                                                = mp_ioapics[apic].mpc_apicid;
+                                if (mp_irqs[i].mp_dstapic == old_id)
+                                        mp_irqs[i].mp_dstapic
+                                                = mp_ioapics[apic].mp_apicid;
 
                 /*
                  * Read the right value from the MPC table and
                  * write it into the ID register.
-                 */
+                 */
                 apic_printk(APIC_VERBOSE, KERN_INFO
                         "...changing IO-APIC physical APIC ID to %d ...",
-                        mp_ioapics[apic].mpc_apicid);
+                        mp_ioapics[apic].mp_apicid);
 
-                reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
+                reg_00.bits.ID = mp_ioapics[apic].mp_apicid;
                 spin_lock_irqsave(&ioapic_lock, flags);
                 io_apic_write(apic, 0, reg_00.raw);
                 spin_unlock_irqrestore(&ioapic_lock, flags);
@@ -1816,15 +1824,12 @@ static void __init setup_ioapic_ids_from_mpc(void)
                 spin_lock_irqsave(&ioapic_lock, flags);
                 reg_00.raw = io_apic_read(apic, 0);
                 spin_unlock_irqrestore(&ioapic_lock, flags);
-                if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
+                if (reg_00.bits.ID != mp_ioapics[apic].mp_apicid)
                         printk("could not set ID!\n");
                 else
                         apic_printk(APIC_VERBOSE, " ok.\n");
         }
 }
-#else
-static void __init setup_ioapic_ids_from_mpc(void) { }
-#endif
 
 int no_timer_check __initdata;
 
@@ -2015,12 +2020,12 @@ static inline void init_IO_APIC_traps(void)
  * The local APIC irq-chip implementation:
  */
 
-static void ack_apic(unsigned int irq)
+static void ack_lapic_irq(unsigned int irq)
 {
         ack_APIC_irq();
 }
 
-static void mask_lapic_irq (unsigned int irq)
+static void mask_lapic_irq(unsigned int irq)
 {
         unsigned long v;
 
@@ -2028,7 +2033,7 @@ static void mask_lapic_irq (unsigned int irq)
         apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
 }
 
-static void unmask_lapic_irq (unsigned int irq)
+static void unmask_lapic_irq(unsigned int irq)
 {
         unsigned long v;
 
@@ -2037,23 +2042,31 @@ static void unmask_lapic_irq (unsigned int irq)
 }
 
 static struct irq_chip lapic_chip __read_mostly = {
-        .name           = "local-APIC-edge",
+        .name           = "local-APIC",
         .mask           = mask_lapic_irq,
         .unmask         = unmask_lapic_irq,
-        .eoi            = ack_apic,
+        .ack            = ack_lapic_irq,
 };
 
+static void lapic_register_intr(int irq, int vector)
+{
+        irq_desc[irq].status &= ~IRQ_LEVEL;
+        set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
+                                      "edge");
+        set_intr_gate(vector, interrupt[irq]);
+}
+
 static void __init setup_nmi(void)
 {
         /*
-         * Dirty trick to enable the NMI watchdog ...
+         * Dirty trick to enable the NMI watchdog ...
          * We put the 8259A master into AEOI mode and
          * unmask on all local APICs LVT0 as NMI.
          *
          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
          * is from Maciej W. Rozycki - so we do not have to EOI from
          * the NMI handler or the timer interrupt.
-         */ 
+         */
         apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
 
         enable_NMI_through_LVT0();
@@ -2129,11 +2142,16 @@ static inline void __init unlock_ExtINT_logic(void)
 static inline void __init check_timer(void)
 {
         int apic1, pin1, apic2, pin2;
+        int no_pin1 = 0;
         int vector;
+        unsigned int ver;
         unsigned long flags;
 
         local_irq_save(flags);
 
+        ver = apic_read(APIC_LVR);
+        ver = GET_APIC_VERSION(ver);
+
         /*
          * get/set the timer IRQ vector:
          */
@@ -2142,17 +2160,17 @@ static inline void __init check_timer(void)
         set_intr_gate(vector, interrupt[0]);
 
         /*
-         * Subtle, code in do_timer_interrupt() expects an AEOI
-         * mode for the 8259A whenever interrupts are routed
-         * through I/O APICs.  Also IRQ0 has to be enabled in
-         * the 8259A which implies the virtual wire has to be
-         * disabled in the local APIC.
+         * As IRQ0 is to be enabled in the 8259A, the virtual
+         * wire has to be disabled in the local APIC.  Also
+         * timer interrupts need to be acknowledged manually in
+         * the 8259A for the i82489DX when using the NMI
+         * watchdog as that APIC treats NMIs as level-triggered.
+         * The AEOI mode will finish them in the 8259A
+         * automatically.
          */
         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
         init_8259A(1);
-        timer_ack = 1;
-        if (timer_over_8254 > 0)
-                enable_8259A_irq(0);
+        timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
 
         pin1  = find_isa_irq_pin(0, mp_INT);
         apic1 = find_isa_irq_apic(0, mp_INT);
@@ -2162,14 +2180,33 @@ static inline void __init check_timer(void)
         printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
                 vector, apic1, pin1, apic2, pin2);
 
+        /*
+         * Some BIOS writers are clueless and report the ExtINTA
+         * I/O APIC input from the cascaded 8259A as the timer
+         * interrupt input.  So just in case, if only one pin
+         * was found above, try it both directly and through the
+         * 8259A.
+         */
+        if (pin1 == -1) {
+                pin1 = pin2;
+                apic1 = apic2;
+                no_pin1 = 1;
+        } else if (pin2 == -1) {
+                pin2 = pin1;
+                apic2 = apic1;
+        }
+
         if (pin1 != -1) {
                 /*
                  * Ok, does IRQ0 through the IOAPIC work?
                  */
+                if (no_pin1) {
+                        add_pin_to_irq(0, apic1, pin1);
+                        setup_timer_IRQ0_pin(apic1, pin1, vector);
+                }
                 unmask_IO_APIC_irq(0);
                 if (timer_irq_works()) {
                         if (nmi_watchdog == NMI_IO_APIC) {
-                                disable_8259A_irq(0);
                                 setup_nmi();
                                 enable_8259A_irq(0);
                         }
@@ -2178,45 +2215,47 @@ static inline void __init check_timer(void)
                         goto out;
                 }
                 clear_IO_APIC_pin(apic1, pin1);
-                printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to "
-                                "IO-APIC\n");
-        }
+                if (!no_pin1)
+                        printk(KERN_ERR "..MP-BIOS bug: "
+                               "8254 timer not connected to IO-APIC\n");
 
-        printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
-        if (pin2 != -1) {
+                printk(KERN_INFO "...trying to set up timer (IRQ0) "
+                       "through the 8259A ... ");
                 printk("\n..... (found pin %d) ...", pin2);
                 /*
                  * legacy devices should be connected to IO APIC #0
                  */
-                setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
+                replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
+                setup_timer_IRQ0_pin(apic2, pin2, vector);
+                unmask_IO_APIC_irq(0);
+                enable_8259A_irq(0);
                 if (timer_irq_works()) {
                         printk("works.\n");
-                        if (pin1 != -1)
-                                replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
-                        else
-                                add_pin_to_irq(0, apic2, pin2);
+                        timer_through_8259 = 1;
                         if (nmi_watchdog == NMI_IO_APIC) {
+                                disable_8259A_irq(0);
                                 setup_nmi();
+                                enable_8259A_irq(0);
                         }
                         goto out;
                 }
                 /*
                  * Cleanup, just in case ...
                  */
+                disable_8259A_irq(0);
                 clear_IO_APIC_pin(apic2, pin2);
+                printk(" failed.\n");
         }
-        printk(" failed.\n");
 
         if (nmi_watchdog == NMI_IO_APIC) {
                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
-                nmi_watchdog = 0;
+                nmi_watchdog = NMI_NONE;
         }
+        timer_ack = 0;
 
         printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
 
-        disable_8259A_irq(0);
-        set_irq_chip_and_handler_name(0, &lapic_chip, handle_fasteoi_irq,
-                                      "fasteoi");
+        lapic_register_intr(0, vector);
         apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector);   /* Fixed mode */
         enable_8259A_irq(0);
 
@@ -2224,12 +2263,12 @@ static inline void __init check_timer(void)
                 printk(" works.\n");
                 goto out;
         }
+        disable_8259A_irq(0);
         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
         printk(" failed.\n");
 
         printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
 
-        timer_ack = 0;
         init_8259A(0);
         make_8259A_irq(0);
         apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
@@ -2248,11 +2287,21 @@ out:
 }
 
 /*
- *
- * IRQ's that are handled by the PIC in the MPS IOAPIC case.
- * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
- *   Linux doesn't really care, as it's not actually used
- *   for any interrupt handling anyway.
+ * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
+ * to devices.  However there may be an I/O APIC pin available for
+ * this interrupt regardless.  The pin may be left unconnected, but
+ * typically it will be reused as an ExtINT cascade interrupt for
+ * the master 8259A.  In the MPS case such a pin will normally be
+ * reported as an ExtINT interrupt in the MP table.  With ACPI
+ * there is no provision for ExtINT interrupts, and in the absence
+ * of an override it would be treated as an ordinary ISA I/O APIC
+ * interrupt, that is edge-triggered and unmasked by default.  We
+ * used to do this, but it caused problems on some systems because
+ * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
+ * the same ExtINT cascade interrupt to drive the local APIC of the
+ * bootstrap processor.  Therefore we refrain from routing IRQ2 to
+ * the I/O APIC in all cases now.  No actual device should request
+ * it anyway.  --macro
  */
 #define PIC_IRQS        (1 << PIC_CASCADE_IR)
 
@@ -2261,15 +2310,12 @@ void __init setup_IO_APIC(void)
         int i;
 
         /* Reserve all the system vectors. */
-        for (i = FIRST_SYSTEM_VECTOR; i < NR_VECTORS; i++)
+        for (i = first_system_vector; i < NR_VECTORS; i++)
                 set_bit(i, used_vectors);
 
         enable_IO_APIC();
 
-        if (acpi_ioapic)
-                io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
-        else
-                io_apic_irqs = ~PIC_IRQS;
+        io_apic_irqs = ~PIC_IRQS;
 
         printk("ENABLING IO-APIC IRQs\n");
 
@@ -2286,28 +2332,14 @@ void __init setup_IO_APIC(void)
                 print_IO_APIC();
 }
 
-static int __init setup_disable_8254_timer(char *s)
-{
-        timer_over_8254 = -1;
-        return 1;
-}
-static int __init setup_enable_8254_timer(char *s)
-{
-        timer_over_8254 = 2;
-        return 1;
-}
-
-__setup("disable_8254_timer", setup_disable_8254_timer);
-__setup("enable_8254_timer", setup_enable_8254_timer);
-
 /*
  *      Called after all the initialization is done. If we didnt find any
  *      APIC bugs then we can allow the modify fast path
  */
- 
+
 static int __init io_apic_bug_finalize(void)
 {
-        if(sis_apic_bug == -1)
+        if (sis_apic_bug == -1)
                 sis_apic_bug = 0;
         return 0;
 }
@@ -2318,17 +2350,17 @@ struct sysfs_ioapic_data {
         struct sys_device dev;
         struct IO_APIC_route_entry entry[0];
 };
-static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
+static struct sysfs_ioapic_data *mp_ioapic_data[MAX_IO_APICS];
 
 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
 {
         struct IO_APIC_route_entry *entry;
         struct sysfs_ioapic_data *data;
         int i;
-        
+
         data = container_of(dev, struct sysfs_ioapic_data, dev);
         entry = data->entry;
-        for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
+        for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
                 entry[i] = ioapic_read_entry(dev->id, i);
 
         return 0;
@@ -2341,18 +2373,18 @@ static int ioapic_resume(struct sys_device *dev)
         unsigned long flags;
         union IO_APIC_reg_00 reg_00;
         int i;
-        
+
         data = container_of(dev, struct sysfs_ioapic_data, dev);
         entry = data->entry;
 
         spin_lock_irqsave(&ioapic_lock, flags);
         reg_00.raw = io_apic_read(dev->id, 0);
-        if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
-                reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
+        if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) {
+                reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid;
                 io_apic_write(dev->id, 0, reg_00.raw);
         }
         spin_unlock_irqrestore(&ioapic_lock, flags);
-        for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
+        for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
                 ioapic_write_entry(dev->id, i, entry[i]);
 
         return 0;
@@ -2366,24 +2398,23 @@ static struct sysdev_class ioapic_sysdev_class = {
 
 static int __init ioapic_init_sysfs(void)
 {
-        struct sys_device * dev;
+        struct sys_device *dev;
         int i, size, error = 0;
 
         error = sysdev_class_register(&ioapic_sysdev_class);
         if (error)
                 return error;
 
-        for (i = 0; i < nr_ioapics; i++ ) {
-                size = sizeof(struct sys_device) + nr_ioapic_registers[i] 
+        for (i = 0; i < nr_ioapics; i++) {
+                size = sizeof(struct sys_device) + nr_ioapic_registers[i]
                         * sizeof(struct IO_APIC_route_entry);
-                mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
+                mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
                 if (!mp_ioapic_data[i]) {
                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
                         continue;
                 }
-                memset(mp_ioapic_data[i], 0, size);
                 dev = &mp_ioapic_data[i]->dev;
-                dev->id = i; 
+                dev->id = i;
                 dev->cls = &ioapic_sysdev_class;
                 error = sysdev_register(dev);
                 if (error) {
@@ -2458,7 +2489,7 @@ static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_ms
                 msg->address_lo =
                         MSI_ADDR_BASE_LO |
                         ((INT_DEST_MODE == 0) ?
-                                MSI_ADDR_DEST_MODE_PHYSICAL:
+MSI_ADDR_DEST_MODE_PHYSICAL:
                                 MSI_ADDR_DEST_MODE_LOGICAL) |
                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
                                 MSI_ADDR_REDIRECTION_CPU:
@@ -2469,7 +2500,7 @@ static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_ms
                         MSI_DATA_TRIGGER_EDGE |
                         MSI_DATA_LEVEL_ASSERT |
                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
-                                MSI_DATA_DELIVERY_FIXED:
+MSI_DATA_DELIVERY_FIXED:
                                 MSI_DATA_DELIVERY_LOWPRI) |
                         MSI_DATA_VECTOR(vector);
         }
@@ -2640,12 +2671,12 @@ int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
 #endif /* CONFIG_HT_IRQ */
 
 /* --------------------------------------------------------------------------
-                          ACPI-based IOAPIC Configuration
+                        ACPI-based IOAPIC Configuration
    -------------------------------------------------------------------------- */
 
 #ifdef CONFIG_ACPI
 
-int __init io_apic_get_unique_id (int ioapic, int apic_id)
+int __init io_apic_get_unique_id(int ioapic, int apic_id)
 {
         union IO_APIC_reg_00 reg_00;
         static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
@@ -2654,10 +2685,10 @@ int __init io_apic_get_unique_id (int ioapic, int apic_id)
         int i = 0;
 
         /*
-         * The P4 platform supports up to 256 APIC IDs on two separate APIC 
-         * buses (one for LAPICs, one for IOAPICs), where predecessors only 
+         * The P4 platform supports up to 256 APIC IDs on two separate APIC
+         * buses (one for LAPICs, one for IOAPICs), where predecessors only
          * supports up to 16 on one shared APIC bus.
-         * 
+         *
          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
          *      advantage of new APIC bus architecture.
          */
@@ -2676,7 +2707,7 @@ int __init io_apic_get_unique_id (int ioapic, int apic_id)
         }
 
         /*
-         * Every APIC in a system must have a unique ID or we get lots of nice 
+         * Every APIC in a system must have a unique ID or we get lots of nice
          * 'stuck on smp_invalidate_needed IPI wait' messages.
          */
         if (check_apicid_used(apic_id_map, apic_id)) {
@@ -2693,7 +2724,7 @@ int __init io_apic_get_unique_id (int ioapic, int apic_id)
                         "trying %d\n", ioapic, apic_id, i);
 
                 apic_id = i;
-        } 
+        }
 
         tmp = apicid_to_cpu_present(apic_id);
         physids_or(apic_id_map, apic_id_map, tmp);
@@ -2720,7 +2751,7 @@ int __init io_apic_get_unique_id (int ioapic, int apic_id)
 }
 
 
-int __init io_apic_get_version (int ioapic)
+int __init io_apic_get_version(int ioapic)
 {
         union IO_APIC_reg_01    reg_01;
         unsigned long flags;
@@ -2733,7 +2764,7 @@ int __init io_apic_get_version (int ioapic)
 }
 
 
-int __init io_apic_get_redir_entries (int ioapic)
+int __init io_apic_get_redir_entries(int ioapic)
 {
         union IO_APIC_reg_01    reg_01;
         unsigned long flags;
@@ -2746,7 +2777,7 @@ int __init io_apic_get_redir_entries (int ioapic)
 }
 
 
-int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
+int io_apic_set_pci_routing(int ioapic, int pin, int irq, int edge_level, int active_high_low)
 {
         struct IO_APIC_route_entry entry;
 
@@ -2762,7 +2793,7 @@ int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int a
          * corresponding device driver registers for this IRQ.
          */
 
-        memset(&entry,0,sizeof(entry));
+        memset(&entry, 0, sizeof(entry));
 
         entry.delivery_mode = INT_DELIVERY_MODE;
         entry.dest_mode = INT_DEST_MODE;
@@ -2781,7 +2812,7 @@ int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int a
 
         apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
                 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
-                mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
+                mp_ioapics[ioapic].mp_apicid, pin, entry.vector, irq,
                 edge_level, active_high_low);
 
         ioapic_register_intr(irq, entry.vector, edge_level);
@@ -2802,8 +2833,8 @@ int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
                 return -1;
 
         for (i = 0; i < mp_irq_entries; i++)
-                if (mp_irqs[i].mpc_irqtype == mp_INT &&
-                    mp_irqs[i].mpc_srcbusirq == bus_irq)
+                if (mp_irqs[i].mp_irqtype == mp_INT &&
+                    mp_irqs[i].mp_srcbusirq == bus_irq)
                         break;
         if (i >= mp_irq_entries)
                 return -1;
@@ -2836,3 +2867,34 @@ static int __init parse_noapic(char *arg)
         return 0;
 }
 early_param("noapic", parse_noapic);
+
+void __init ioapic_init_mappings(void)
+{
+        unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
+        int i;
+
+        for (i = 0; i < nr_ioapics; i++) {
+                if (smp_found_config) {
+                        ioapic_phys = mp_ioapics[i].mp_apicaddr;
+                        if (!ioapic_phys) {
+                                printk(KERN_ERR
+                                       "WARNING: bogus zero IO-APIC "
+                                       "address found in MPTABLE, "
+                                       "disabling IO/APIC support!\n");
+                                smp_found_config = 0;
+                                skip_ioapic_setup = 1;
+                                goto fake_ioapic_page;
+                        }
+                } else {
+fake_ioapic_page:
+                        ioapic_phys = (unsigned long)
+                                      alloc_bootmem_pages(PAGE_SIZE);
+                        ioapic_phys = __pa(ioapic_phys);
+                }
+                set_fixmap_nocache(idx, ioapic_phys);
+                printk(KERN_DEBUG "mapped IOAPIC to %08lx (%08lx)\n",
+                       __fix_to_virt(idx), ioapic_phys);
+                idx++;
+        }
+}
+
diff --git a/arch/x86/kernel/io_apic_64.c b/arch/x86/kernel/io_apic_64.c
index ef1a8dfcc529..b16ef029cf88 100644
--- a/arch/x86/kernel/io_apic_64.c
+++ b/arch/x86/kernel/io_apic_64.c
@@ -61,7 +61,7 @@ struct irq_cfg {
 };
 
 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
-struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
+static struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
         [0]  = { .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR,  },
         [1]  = { .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR,  },
         [2]  = { .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR,  },
@@ -82,6 +82,10 @@ struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
 
 static int assign_irq_vector(int irq, cpumask_t mask);
 
+int first_system_vector = 0xfe;
+
+char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE};
+
 #define __apicdebuginit  __init
 
 int sis_apic_bug; /* not actually supported, dummy for compile */
@@ -90,7 +94,7 @@ static int no_timer_check;
 
 static int disable_timer_pin_1 __initdata;
 
-int timer_over_8254 __initdata = 1;
+int timer_through_8259 __initdata;
 
 /* Where if anywhere is the i8259 connect in external int mode */
 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
@@ -104,15 +108,17 @@ DEFINE_SPINLOCK(vector_lock);
 int nr_ioapic_registers[MAX_IO_APICS];
 
 /* I/O APIC entries */
-struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
+struct mp_config_ioapic mp_ioapics[MAX_IO_APICS];
 int nr_ioapics;
 
 /* MP IRQ source entries */
-struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
+struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
 
 /* # of MP IRQ source entries */
 int mp_irq_entries;
 
+DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
+
 /*
  * Rough estimation of how many shared IRQs there are, can
  * be changed anytime.
@@ -140,7 +146,7 @@ struct io_apic {
 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
 {
         return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
-                + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
+                + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK);
 }
 
 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
@@ -183,7 +189,7 @@ static bool io_apic_level_ack_pending(unsigned int irq)
                         break;
                 reg = io_apic_read(entry->apic, 0x10 + pin*2);
                 /* Is the remote IRR bit set? */
-                if ((reg >> 14) & 1) {
+                if (reg & IO_APIC_REDIR_REMOTE_IRR) {
                         spin_unlock_irqrestore(&ioapic_lock, flags);
                         return true;
                 }
@@ -298,7 +304,7 @@ static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
                         break;
                 io_apic_write(apic, 0x11 + pin*2, dest);
                 reg = io_apic_read(apic, 0x10 + pin*2);
-                reg &= ~0x000000ff;
+                reg &= ~IO_APIC_REDIR_VECTOR_MASK;
                 reg |= vector;
                 io_apic_modify(apic, reg);
                 if (!entry->next)
@@ -360,16 +366,37 @@ static void add_pin_to_irq(unsigned int irq, int apic, int pin)
         entry->pin = pin;
 }
 
+/*
+ * Reroute an IRQ to a different pin.
+ */
+static void __init replace_pin_at_irq(unsigned int irq,
+                                      int oldapic, int oldpin,
+                                      int newapic, int newpin)
+{
+        struct irq_pin_list *entry = irq_2_pin + irq;
+
+        while (1) {
+                if (entry->apic == oldapic && entry->pin == oldpin) {
+                        entry->apic = newapic;
+                        entry->pin = newpin;
+                }
+                if (!entry->next)
+                        break;
+                entry = irq_2_pin + entry->next;
+        }
+}
+
 
 #define DO_ACTION(name,R,ACTION, FINAL)                                 \
                                                                         \
         static void name##_IO_APIC_irq (unsigned int irq)               \
         __DO_ACTION(R, ACTION, FINAL)
 
-DO_ACTION( __mask,             0, |= 0x00010000, io_apic_sync(entry->apic) )
-                                                /* mask = 1 */
-DO_ACTION( __unmask,           0, &= 0xfffeffff, )
-                                                /* mask = 0 */
+/* mask = 1 */
+DO_ACTION(__mask,       0, |= IO_APIC_REDIR_MASKED, io_apic_sync(entry->apic))
+
+/* mask = 0 */
+DO_ACTION(__unmask,     0, &= ~IO_APIC_REDIR_MASKED, )
 
 static void mask_IO_APIC_irq (unsigned int irq)
 {
@@ -430,20 +457,6 @@ static int __init disable_timer_pin_setup(char *arg)
 }
 __setup("disable_timer_pin_1", disable_timer_pin_setup);
 
-static int __init setup_disable_8254_timer(char *s)
-{
-        timer_over_8254 = -1;
-        return 1;
-}
-static int __init setup_enable_8254_timer(char *s)
-{
-        timer_over_8254 = 2;
-        return 1;
-}
-
-__setup("disable_8254_timer", setup_disable_8254_timer);
-__setup("enable_8254_timer", setup_enable_8254_timer);
-
 
 /*
  * Find the IRQ entry number of a certain pin.
@@ -453,10 +466,10 @@ static int find_irq_entry(int apic, int pin, int type)
         int i;
 
         for (i = 0; i < mp_irq_entries; i++)
-                if (mp_irqs[i].mpc_irqtype == type &&
-                    (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
-                     mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
-                    mp_irqs[i].mpc_dstirq == pin)
+                if (mp_irqs[i].mp_irqtype == type &&
+                    (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid ||
+                     mp_irqs[i].mp_dstapic == MP_APIC_ALL) &&
+                    mp_irqs[i].mp_dstirq == pin)
                         return i;
 
         return -1;
@@ -470,13 +483,13 @@ static int __init find_isa_irq_pin(int irq, int type)
         int i;
 
         for (i = 0; i < mp_irq_entries; i++) {
-                int lbus = mp_irqs[i].mpc_srcbus;
+                int lbus = mp_irqs[i].mp_srcbus;
 
                 if (test_bit(lbus, mp_bus_not_pci) &&
-                    (mp_irqs[i].mpc_irqtype == type) &&
-                    (mp_irqs[i].mpc_srcbusirq == irq))
+                    (mp_irqs[i].mp_irqtype == type) &&
+                    (mp_irqs[i].mp_srcbusirq == irq))
 
-                        return mp_irqs[i].mpc_dstirq;
+                        return mp_irqs[i].mp_dstirq;
         }
         return -1;
 }
@@ -486,17 +499,17 @@ static int __init find_isa_irq_apic(int irq, int type)
         int i;
 
         for (i = 0; i < mp_irq_entries; i++) {
-                int lbus = mp_irqs[i].mpc_srcbus;
+                int lbus = mp_irqs[i].mp_srcbus;
 
                 if (test_bit(lbus, mp_bus_not_pci) &&
-                    (mp_irqs[i].mpc_irqtype == type) &&
-                    (mp_irqs[i].mpc_srcbusirq == irq))
+                    (mp_irqs[i].mp_irqtype == type) &&
+                    (mp_irqs[i].mp_srcbusirq == irq))
                         break;
         }
         if (i < mp_irq_entries) {
                 int apic;
                 for(apic = 0; apic < nr_ioapics; apic++) {
-                        if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
+                        if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic)
                                 return apic;
                 }
         }
@@ -516,28 +529,28 @@ int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 
         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
                 bus, slot, pin);
-        if (mp_bus_id_to_pci_bus[bus] == -1) {
+        if (test_bit(bus, mp_bus_not_pci)) {
                 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
                 return -1;
         }
         for (i = 0; i < mp_irq_entries; i++) {
-                int lbus = mp_irqs[i].mpc_srcbus;
+                int lbus = mp_irqs[i].mp_srcbus;
 
                 for (apic = 0; apic < nr_ioapics; apic++)
-                        if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
-                            mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
+                        if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic ||
+                            mp_irqs[i].mp_dstapic == MP_APIC_ALL)
                                 break;
 
                 if (!test_bit(lbus, mp_bus_not_pci) &&
-                    !mp_irqs[i].mpc_irqtype &&
+                    !mp_irqs[i].mp_irqtype &&
                     (bus == lbus) &&
-                    (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
-                        int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
+                    (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) {
+                        int irq = pin_2_irq(i,apic,mp_irqs[i].mp_dstirq);
 
                         if (!(apic || IO_APIC_IRQ(irq)))
                                 continue;
 
-                        if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
+                        if (pin == (mp_irqs[i].mp_srcbusirq & 3))
                                 return irq;
                         /*
                          * Use the first all-but-pin matching entry as a
@@ -565,13 +578,13 @@ int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 
 static int MPBIOS_polarity(int idx)
 {
-        int bus = mp_irqs[idx].mpc_srcbus;
+        int bus = mp_irqs[idx].mp_srcbus;
         int polarity;
 
         /*
          * Determine IRQ line polarity (high active or low active):
          */
-        switch (mp_irqs[idx].mpc_irqflag & 3)
+        switch (mp_irqs[idx].mp_irqflag & 3)
         {
                 case 0: /* conforms, ie. bus-type dependent polarity */
                         if (test_bit(bus, mp_bus_not_pci))
@@ -607,13 +620,13 @@ static int MPBIOS_polarity(int idx)
 
 static int MPBIOS_trigger(int idx)
 {
-        int bus = mp_irqs[idx].mpc_srcbus;
+        int bus = mp_irqs[idx].mp_srcbus;
         int trigger;
 
         /*
          * Determine IRQ trigger mode (edge or level sensitive):
          */
-        switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
+        switch ((mp_irqs[idx].mp_irqflag>>2) & 3)
         {
                 case 0: /* conforms, ie. bus-type dependent */
                         if (test_bit(bus, mp_bus_not_pci))
@@ -660,16 +673,16 @@ static inline int irq_trigger(int idx)
 static int pin_2_irq(int idx, int apic, int pin)
 {
         int irq, i;
-        int bus = mp_irqs[idx].mpc_srcbus;
+        int bus = mp_irqs[idx].mp_srcbus;
 
         /*
          * Debugging check, we are in big trouble if this message pops up!
          */
-        if (mp_irqs[idx].mpc_dstirq != pin)
+        if (mp_irqs[idx].mp_dstirq != pin)
                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
 
         if (test_bit(bus, mp_bus_not_pci)) {
-                irq = mp_irqs[idx].mpc_srcbusirq;
+                irq = mp_irqs[idx].mp_srcbusirq;
         } else {
                 /*
                  * PCI IRQs are mapped in order
@@ -730,7 +743,7 @@ static int __assign_irq_vector(int irq, cpumask_t mask)
                 offset = current_offset;
 next:
                 vector += 8;
-                if (vector >= FIRST_SYSTEM_VECTOR) {
+                if (vector >= first_system_vector) {
                         /* If we run out of vectors on large boxen, must share them. */
                         offset = (offset + 1) % 8;
                         vector = FIRST_DEVICE_VECTOR + offset;
@@ -788,7 +801,7 @@ static void __clear_irq_vector(int irq)
         cpus_clear(cfg->domain);
 }
 
-void __setup_vector_irq(int cpu)
+static void __setup_vector_irq(int cpu)
 {
         /* Initialize vector_irq on a new cpu */
         /* This function must be called with vector_lock held */
@@ -811,6 +824,13 @@ void __setup_vector_irq(int cpu)
         }
 }
 
+void setup_vector_irq(int cpu)
+{
+        spin_lock(&vector_lock);
+        __setup_vector_irq(smp_processor_id());
+        spin_unlock(&vector_lock);
+}
+
 
 static struct irq_chip ioapic_chip;
 
@@ -846,7 +866,7 @@ static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
         apic_printk(APIC_VERBOSE,KERN_DEBUG
                     "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
                     "IRQ %d Mode:%i Active:%i)\n",
-                    apic, mp_ioapics[apic].mpc_apicid, pin, cfg->vector,
+                    apic, mp_ioapics[apic].mp_apicid, pin, cfg->vector,
                     irq, trigger, polarity);
 
         /*
@@ -887,10 +907,10 @@ static void __init setup_IO_APIC_irqs(void)
                 idx = find_irq_entry(apic,pin,mp_INT);
                 if (idx == -1) {
                         if (first_notcon) {
-                                apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
+                                apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mp_apicid, pin);
                                 first_notcon = 0;
                         } else
-                                apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
+                                apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mp_apicid, pin);
                         continue;
                 }
                 if (!first_notcon) {
@@ -911,26 +931,21 @@ static void __init setup_IO_APIC_irqs(void)
 }
 
 /*
- * Set up the 8259A-master output pin as broadcast to all
- * CPUs.
+ * Set up the timer pin, possibly with the 8259A-master behind.
  */
-static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
+static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
+                                        int vector)
 {
         struct IO_APIC_route_entry entry;
 
         memset(&entry, 0, sizeof(entry));
 
-        disable_8259A_irq(0);
-
-        /* mask LVT0 */
-        apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
-
         /*
          * We use logical delivery to get the timer IRQ
          * to the first CPU.
          */
         entry.dest_mode = INT_DEST_MODE;
-        entry.mask = 0;                                 /* unmask IRQ now */
+        entry.mask = 1;                                 /* mask IRQ now */
         entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
         entry.delivery_mode = INT_DELIVERY_MODE;
         entry.polarity = 0;
@@ -939,7 +954,7 @@ static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, in
 
         /*
          * The timer IRQ doesn't have to know that behind the
-         * scene we have a 8259A-master in AEOI mode ...
+         * scene we may have a 8259A-master in AEOI mode ...
          */
         set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
 
@@ -947,8 +962,6 @@ static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, in
          * Add it to the IO-APIC irq-routing table:
          */
         ioapic_write_entry(apic, pin, entry);
-
-        enable_8259A_irq(0);
 }
 
 void __apicdebuginit print_IO_APIC(void)
@@ -965,7 +978,7 @@ void __apicdebuginit print_IO_APIC(void)
         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
         for (i = 0; i < nr_ioapics; i++)
                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
-                       mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
+                       mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]);
 
         /*
          * We are a bit conservative about what we expect.  We have to
@@ -983,7 +996,7 @@ void __apicdebuginit print_IO_APIC(void)
         spin_unlock_irqrestore(&ioapic_lock, flags);
 
         printk("\n");
-        printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
+        printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid);
         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
 
@@ -1077,6 +1090,7 @@ void __apicdebuginit print_local_APIC(void * dummy)
 
         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
                 smp_processor_id(), hard_smp_processor_id());
+        v = apic_read(APIC_ID);
         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(read_apic_id()));
         v = apic_read(APIC_LVR);
         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
@@ -1540,7 +1554,7 @@ static inline void init_IO_APIC_traps(void)
         }
 }
 
-static void enable_lapic_irq (unsigned int irq)
+static void unmask_lapic_irq(unsigned int irq)
 {
         unsigned long v;
 
@@ -1548,7 +1562,7 @@ static void enable_lapic_irq (unsigned int irq)
         apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
 }
 
-static void disable_lapic_irq (unsigned int irq)
+static void mask_lapic_irq(unsigned int irq)
 {
         unsigned long v;
 
@@ -1561,19 +1575,20 @@ static void ack_lapic_irq (unsigned int irq)
         ack_APIC_irq();
 }
 
-static void end_lapic_irq (unsigned int i) { /* nothing */ }
-
-static struct hw_interrupt_type lapic_irq_type __read_mostly = {
-        .name = "local-APIC",
-        .typename = "local-APIC-edge",
-        .startup = NULL, /* startup_irq() not used for IRQ0 */
-        .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
-        .enable = enable_lapic_irq,
-        .disable = disable_lapic_irq,
-        .ack = ack_lapic_irq,
-        .end = end_lapic_irq,
+static struct irq_chip lapic_chip __read_mostly = {
+        .name           = "local-APIC",
+        .mask           = mask_lapic_irq,
+        .unmask         = unmask_lapic_irq,
+        .ack            = ack_lapic_irq,
 };
 
+static void lapic_register_intr(int irq)
+{
+        irq_desc[irq].status &= ~IRQ_LEVEL;
+        set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
+                                      "edge");
+}
+
 static void __init setup_nmi(void)
 {
         /*
@@ -1659,6 +1674,7 @@ static inline void __init check_timer(void)
         struct irq_cfg *cfg = irq_cfg + 0;
         int apic1, pin1, apic2, pin2;
         unsigned long flags;
+        int no_pin1 = 0;
 
         local_irq_save(flags);
 
@@ -1669,16 +1685,11 @@ static inline void __init check_timer(void)
         assign_irq_vector(0, TARGET_CPUS);
 
         /*
-         * Subtle, code in do_timer_interrupt() expects an AEOI
-         * mode for the 8259A whenever interrupts are routed
-         * through I/O APICs.  Also IRQ0 has to be enabled in
-         * the 8259A which implies the virtual wire has to be
-         * disabled in the local APIC.
+         * As IRQ0 is to be enabled in the 8259A, the virtual
+         * wire has to be disabled in the local APIC.
          */
         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
         init_8259A(1);
-        if (timer_over_8254 > 0)
-                enable_8259A_irq(0);
 
         pin1  = find_isa_irq_pin(0, mp_INT);
         apic1 = find_isa_irq_apic(0, mp_INT);
@@ -1688,15 +1699,33 @@ static inline void __init check_timer(void)
         apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
                 cfg->vector, apic1, pin1, apic2, pin2);
 
+        /*
+         * Some BIOS writers are clueless and report the ExtINTA
+         * I/O APIC input from the cascaded 8259A as the timer
+         * interrupt input.  So just in case, if only one pin
+         * was found above, try it both directly and through the
+         * 8259A.
+         */
+        if (pin1 == -1) {
+                pin1 = pin2;
+                apic1 = apic2;
+                no_pin1 = 1;
+        } else if (pin2 == -1) {
+                pin2 = pin1;
+                apic2 = apic1;
+        }
+
         if (pin1 != -1) {
                 /*
                  * Ok, does IRQ0 through the IOAPIC work?
                  */
+                if (no_pin1) {
+                        add_pin_to_irq(0, apic1, pin1);
+                        setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
+                }
                 unmask_IO_APIC_irq(0);
                 if (!no_timer_check && timer_irq_works()) {
-                        nmi_watchdog_default();
                         if (nmi_watchdog == NMI_IO_APIC) {
-                                disable_8259A_irq(0);
                                 setup_nmi();
                                 enable_8259A_irq(0);
                         }
@@ -1705,43 +1734,48 @@ static inline void __init check_timer(void)
                         goto out;
                 }
                 clear_IO_APIC_pin(apic1, pin1);
-                apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
-                                "connected to IO-APIC\n");
-        }
+                if (!no_pin1)
+                        apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: "
+                                    "8254 timer not connected to IO-APIC\n");
 
-        apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
-                                "through the 8259A ... ");
-        if (pin2 != -1) {
+                apic_printk(APIC_VERBOSE,KERN_INFO
+                        "...trying to set up timer (IRQ0) "
+                        "through the 8259A ... ");
                 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
                         apic2, pin2);
                 /*
                  * legacy devices should be connected to IO APIC #0
                  */
-                setup_ExtINT_IRQ0_pin(apic2, pin2, cfg->vector);
+                replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
+                setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
+                unmask_IO_APIC_irq(0);
+                enable_8259A_irq(0);
                 if (timer_irq_works()) {
                         apic_printk(APIC_VERBOSE," works.\n");
-                        nmi_watchdog_default();
+                        timer_through_8259 = 1;
                         if (nmi_watchdog == NMI_IO_APIC) {
+                                disable_8259A_irq(0);
                                 setup_nmi();
+                                enable_8259A_irq(0);
                         }
                         goto out;
                 }
                 /*
                  * Cleanup, just in case ...
                  */
+                disable_8259A_irq(0);
                 clear_IO_APIC_pin(apic2, pin2);
+                apic_printk(APIC_VERBOSE," failed.\n");
         }
-        apic_printk(APIC_VERBOSE," failed.\n");
 
         if (nmi_watchdog == NMI_IO_APIC) {
                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
-                nmi_watchdog = 0;
+                nmi_watchdog = NMI_NONE;
         }
 
         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
 
-        disable_8259A_irq(0);
-        irq_desc[0].chip = &lapic_irq_type;
+        lapic_register_intr(0);
         apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector);     /* Fixed mode */
         enable_8259A_irq(0);
 
@@ -1749,6 +1783,7 @@ static inline void __init check_timer(void)
                 apic_printk(APIC_VERBOSE," works.\n");
                 goto out;
         }
+        disable_8259A_irq(0);
         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
         apic_printk(APIC_VERBOSE," failed.\n");
 
@@ -1778,11 +1813,21 @@ static int __init notimercheck(char *s)
 __setup("no_timer_check", notimercheck);
 
 /*
- *
- * IRQs that are handled by the PIC in the MPS IOAPIC case.
- * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
- *   Linux doesn't really care, as it's not actually used
- *   for any interrupt handling anyway.
+ * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
+ * to devices.  However there may be an I/O APIC pin available for
+ * this interrupt regardless.  The pin may be left unconnected, but
+ * typically it will be reused as an ExtINT cascade interrupt for
+ * the master 8259A.  In the MPS case such a pin will normally be
+ * reported as an ExtINT interrupt in the MP table.  With ACPI
+ * there is no provision for ExtINT interrupts, and in the absence
+ * of an override it would be treated as an ordinary ISA I/O APIC
+ * interrupt, that is edge-triggered and unmasked by default.  We
+ * used to do this, but it caused problems on some systems because
+ * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
+ * the same ExtINT cascade interrupt to drive the local APIC of the
+ * bootstrap processor.  Therefore we refrain from routing IRQ2 to
+ * the I/O APIC in all cases now.  No actual device should request
+ * it anyway.  --macro
  */
 #define PIC_IRQS        (1<<2)
 
@@ -1793,10 +1838,7 @@ void __init setup_IO_APIC(void)
          * calling enable_IO_APIC() is moved to setup_local_APIC for BP
          */
 
-        if (acpi_ioapic)
-                io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
-        else
-                io_apic_irqs = ~PIC_IRQS;
+        io_apic_irqs = ~PIC_IRQS;
 
         apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
 
@@ -1841,8 +1883,8 @@ static int ioapic_resume(struct sys_device *dev)
 
         spin_lock_irqsave(&ioapic_lock, flags);
         reg_00.raw = io_apic_read(dev->id, 0);
-        if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
-                reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
+        if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) {
+                reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid;
                 io_apic_write(dev->id, 0, reg_00.raw);
         }
         spin_unlock_irqrestore(&ioapic_lock, flags);
@@ -2242,8 +2284,8 @@ int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
                 return -1;
 
         for (i = 0; i < mp_irq_entries; i++)
-                if (mp_irqs[i].mpc_irqtype == mp_INT &&
-                    mp_irqs[i].mpc_srcbusirq == bus_irq)
+                if (mp_irqs[i].mp_irqtype == mp_INT &&
+                    mp_irqs[i].mp_srcbusirq == bus_irq)
                         break;
         if (i >= mp_irq_entries)
                 return -1;
@@ -2336,7 +2378,7 @@ void __init ioapic_init_mappings(void)
         ioapic_res = ioapic_setup_resources();
         for (i = 0; i < nr_ioapics; i++) {
                 if (smp_found_config) {
-                        ioapic_phys = mp_ioapics[i].mpc_apicaddr;
+                        ioapic_phys = mp_ioapics[i].mp_apicaddr;
                 } else {
                         ioapic_phys = (unsigned long)
                                 alloc_bootmem_pages(PAGE_SIZE);
diff --git a/arch/x86/kernel/ipi.c b/arch/x86/kernel/ipi.c
index c0df7b89ca23..9d98cda39ad9 100644
--- a/arch/x86/kernel/ipi.c
+++ b/arch/x86/kernel/ipi.c
@@ -8,7 +8,6 @@
 #include <linux/kernel_stat.h>
 #include <linux/mc146818rtc.h>
 #include <linux/cache.h>
-#include <linux/interrupt.h>
 #include <linux/cpu.h>
 #include <linux/module.h>
 
diff --git a/arch/x86/kernel/irq_32.c b/arch/x86/kernel/irq_32.c
index 147352df28b9..47a6f6f12478 100644
--- a/arch/x86/kernel/irq_32.c
+++ b/arch/x86/kernel/irq_32.c
@@ -48,6 +48,29 @@ void ack_bad_irq(unsigned int irq)
 #endif
 }
 
+#ifdef CONFIG_DEBUG_STACKOVERFLOW
+/* Debugging check for stack overflow: is there less than 1KB free? */
+static int check_stack_overflow(void)
+{
+        long sp;
+
+        __asm__ __volatile__("andl %%esp,%0" :
+                             "=r" (sp) : "0" (THREAD_SIZE - 1));
+
+        return sp < (sizeof(struct thread_info) + STACK_WARN);
+}
+
+static void print_stack_overflow(void)
+{
+        printk(KERN_WARNING "low stack detected by irq handler\n");
+        dump_stack();
+}
+
+#else
+static inline int check_stack_overflow(void) { return 0; }
+static inline void print_stack_overflow(void) { }
+#endif
+
 #ifdef CONFIG_4KSTACKS
 /*
  * per-CPU IRQ handling contexts (thread information and stack)
@@ -59,48 +82,29 @@ union irq_ctx {
 
 static union irq_ctx *hardirq_ctx[NR_CPUS] __read_mostly;
 static union irq_ctx *softirq_ctx[NR_CPUS] __read_mostly;
-#endif
 
-/*
- * do_IRQ handles all normal device IRQ's (the special
- * SMP cross-CPU interrupts have their own specific
- * handlers).
- */
-unsigned int do_IRQ(struct pt_regs *regs)
-{       
-        struct pt_regs *old_regs;
-        /* high bit used in ret_from_ code */
-        int irq = ~regs->orig_ax;
-        struct irq_desc *desc = irq_desc + irq;
-#ifdef CONFIG_4KSTACKS
-        union irq_ctx *curctx, *irqctx;
-        u32 *isp;
-#endif
+static char softirq_stack[NR_CPUS * THREAD_SIZE]
+                __attribute__((__section__(".bss.page_aligned")));
 
-        if (unlikely((unsigned)irq >= NR_IRQS)) {
-                printk(KERN_EMERG "%s: cannot handle IRQ %d\n",
-                                        __func__, irq);
-                BUG();
-        }
+static char hardirq_stack[NR_CPUS * THREAD_SIZE]
+                __attribute__((__section__(".bss.page_aligned")));
 
-        old_regs = set_irq_regs(regs);
-        irq_enter();
-#ifdef CONFIG_DEBUG_STACKOVERFLOW
-        /* Debugging check for stack overflow: is there less than 1KB free? */
-        {
-                long sp;
-
-                __asm__ __volatile__("andl %%esp,%0" :
-                                        "=r" (sp) : "0" (THREAD_SIZE - 1));
-                if (unlikely(sp < (sizeof(struct thread_info) + STACK_WARN))) {
-                        printk("do_IRQ: stack overflow: %ld\n",
-                                sp - sizeof(struct thread_info));
-                        dump_stack();
-                }
-        }
-#endif
+static void call_on_stack(void *func, void *stack)
+{
+        asm volatile("xchgl     %%ebx,%%esp     \n"
+                     "call      *%%edi          \n"
+                     "movl      %%ebx,%%esp     \n"
+                     : "=b" (stack)
+                     : "0" (stack),
+                       "D"(func)
+                     : "memory", "cc", "edx", "ecx", "eax");
+}
 
-#ifdef CONFIG_4KSTACKS
+static inline int
+execute_on_irq_stack(int overflow, struct irq_desc *desc, int irq)
+{
+        union irq_ctx *curctx, *irqctx;
+        u32 *isp, arg1, arg2;
 
         curctx = (union irq_ctx *) current_thread_info();
         irqctx = hardirq_ctx[smp_processor_id()];
@@ -111,52 +115,39 @@ unsigned int do_IRQ(struct pt_regs *regs)
          * handler) we can't do that and just have to keep using the
          * current stack (which is the irq stack already after all)
          */
-        if (curctx != irqctx) {
-                int arg1, arg2, bx;
-
-                /* build the stack frame on the IRQ stack */
-                isp = (u32*) ((char*)irqctx + sizeof(*irqctx));
-                irqctx->tinfo.task = curctx->tinfo.task;
-                irqctx->tinfo.previous_esp = current_stack_pointer;
+        if (unlikely(curctx == irqctx))
+                return 0;
 
-                /*
-                 * Copy the softirq bits in preempt_count so that the
-                 * softirq checks work in the hardirq context.
-                 */
-                irqctx->tinfo.preempt_count =
-                        (irqctx->tinfo.preempt_count & ~SOFTIRQ_MASK) |
-                        (curctx->tinfo.preempt_count & SOFTIRQ_MASK);
-
-                asm volatile(
-                        "       xchgl  %%ebx,%%esp    \n"
-                        "       call   *%%edi         \n"
-                        "       movl   %%ebx,%%esp    \n"
-                        : "=a" (arg1), "=d" (arg2), "=b" (bx)
-                        :  "0" (irq),   "1" (desc),  "2" (isp),
-                           "D" (desc->handle_irq)
-                        : "memory", "cc", "ecx"
-                );
-        } else
-#endif
-                desc->handle_irq(irq, desc);
+        /* build the stack frame on the IRQ stack */
+        isp = (u32 *) ((char*)irqctx + sizeof(*irqctx));
+        irqctx->tinfo.task = curctx->tinfo.task;
+        irqctx->tinfo.previous_esp = current_stack_pointer;
 
-        irq_exit();
-        set_irq_regs(old_regs);
+        /*
+         * Copy the softirq bits in preempt_count so that the
+         * softirq checks work in the hardirq context.
+         */
+        irqctx->tinfo.preempt_count =
+                (irqctx->tinfo.preempt_count & ~SOFTIRQ_MASK) |
+                (curctx->tinfo.preempt_count & SOFTIRQ_MASK);
+
+        if (unlikely(overflow))
+                call_on_stack(print_stack_overflow, isp);
+
+        asm volatile("xchgl     %%ebx,%%esp     \n"
+                     "call      *%%edi          \n"
+                     "movl      %%ebx,%%esp     \n"
+                     : "=a" (arg1), "=d" (arg2), "=b" (isp)
+                     :  "0" (irq),   "1" (desc),  "2" (isp),
+                        "D" (desc->handle_irq)
+                     : "memory", "cc", "ecx");
         return 1;
 }
 
-#ifdef CONFIG_4KSTACKS
-
-static char softirq_stack[NR_CPUS * THREAD_SIZE]
-                __attribute__((__section__(".bss.page_aligned")));
-
-static char hardirq_stack[NR_CPUS * THREAD_SIZE]
-                __attribute__((__section__(".bss.page_aligned")));
-
 /*
  * allocate per-cpu stacks for hardirq and for softirq processing
  */
-void irq_ctx_init(int cpu)
+void __cpuinit irq_ctx_init(int cpu)
 {
         union irq_ctx *irqctx;
 
@@ -164,25 +155,25 @@ void irq_ctx_init(int cpu)
                 return;
 
         irqctx = (union irq_ctx*) &hardirq_stack[cpu*THREAD_SIZE];
-        irqctx->tinfo.task              = NULL;
-        irqctx->tinfo.exec_domain       = NULL;
-        irqctx->tinfo.cpu               = cpu;
-        irqctx->tinfo.preempt_count     = HARDIRQ_OFFSET;
-        irqctx->tinfo.addr_limit        = MAKE_MM_SEG(0);
+        irqctx->tinfo.task              = NULL;
+        irqctx->tinfo.exec_domain       = NULL;
+        irqctx->tinfo.cpu               = cpu;
+        irqctx->tinfo.preempt_count     = HARDIRQ_OFFSET;
+        irqctx->tinfo.addr_limit        = MAKE_MM_SEG(0);
 
         hardirq_ctx[cpu] = irqctx;
 
         irqctx = (union irq_ctx*) &softirq_stack[cpu*THREAD_SIZE];
-        irqctx->tinfo.task              = NULL;
-        irqctx->tinfo.exec_domain       = NULL;
-        irqctx->tinfo.cpu               = cpu;
-        irqctx->tinfo.preempt_count     = 0;
-        irqctx->tinfo.addr_limit        = MAKE_MM_SEG(0);
+        irqctx->tinfo.task              = NULL;
+        irqctx->tinfo.exec_domain       = NULL;
+        irqctx->tinfo.cpu               = cpu;
+        irqctx->tinfo.preempt_count     = 0;
+        irqctx->tinfo.addr_limit        = MAKE_MM_SEG(0);
 
         softirq_ctx[cpu] = irqctx;
 
-        printk("CPU %u irqstacks, hard=%p soft=%p\n",
-                cpu,hardirq_ctx[cpu],softirq_ctx[cpu]);
+        printk(KERN_DEBUG "CPU %u irqstacks, hard=%p soft=%p\n",
+               cpu,hardirq_ctx[cpu],softirq_ctx[cpu]);
 }
 
 void irq_ctx_exit(int cpu)
@@ -211,25 +202,56 @@ asmlinkage void do_softirq(void)
                 /* build the stack frame on the softirq stack */
                 isp = (u32*) ((char*)irqctx + sizeof(*irqctx));
 
-                asm volatile(
-                        "       xchgl   %%ebx,%%esp     \n"
-                        "       call    __do_softirq    \n"
-                        "       movl    %%ebx,%%esp     \n"
-                        : "=b"(isp)
-                        : "0"(isp)
-                        : "memory", "cc", "edx", "ecx", "eax"
-                );
+                call_on_stack(__do_softirq, isp);
                 /*
                  * Shouldnt happen, we returned above if in_interrupt():
-                 */
+                 */
                 WARN_ON_ONCE(softirq_count());
         }
 
         local_irq_restore(flags);
 }
+
+#else
+static inline int
+execute_on_irq_stack(int overflow, struct irq_desc *desc, int irq) { return 0; }
 #endif
 
 /*
+ * do_IRQ handles all normal device IRQ's (the special
+ * SMP cross-CPU interrupts have their own specific
+ * handlers).
+ */
+unsigned int do_IRQ(struct pt_regs *regs)
+{
+        struct pt_regs *old_regs;
+        /* high bit used in ret_from_ code */
+        int overflow, irq = ~regs->orig_ax;
+        struct irq_desc *desc = irq_desc + irq;
+
+        if (unlikely((unsigned)irq >= NR_IRQS)) {
+                printk(KERN_EMERG "%s: cannot handle IRQ %d\n",
+                                        __func__, irq);
+                BUG();
+        }
+
+        old_regs = set_irq_regs(regs);
+        irq_enter();
+
+        overflow = check_stack_overflow();
+
+        if (!execute_on_irq_stack(overflow, desc, irq)) {
+                if (unlikely(overflow))
+                        print_stack_overflow();
+                desc->handle_irq(irq, desc);
+        }
+
+        irq_exit();
+        set_irq_regs(old_regs);
+        return 1;
+}
+
+/*
  * Interrupt statistics:
  */
 
@@ -313,16 +335,20 @@ skip:
                                 per_cpu(irq_stat,j).irq_tlb_count);
                 seq_printf(p, "  TLB shootdowns\n");
 #endif
+#ifdef CONFIG_X86_MCE
                 seq_printf(p, "TRM: ");
                 for_each_online_cpu(j)
                         seq_printf(p, "%10u ",
                                 per_cpu(irq_stat,j).irq_thermal_count);
                 seq_printf(p, "  Thermal event interrupts\n");
+#endif
+#ifdef CONFIG_X86_LOCAL_APIC
                 seq_printf(p, "SPU: ");
                 for_each_online_cpu(j)
                         seq_printf(p, "%10u ",
                                 per_cpu(irq_stat,j).irq_spurious_count);
                 seq_printf(p, "  Spurious interrupts\n");
+#endif
                 seq_printf(p, "ERR: %10u\n", atomic_read(&irq_err_count));
 #if defined(CONFIG_X86_IO_APIC)
                 seq_printf(p, "MIS: %10u\n", atomic_read(&irq_mis_count));
@@ -331,6 +357,40 @@ skip:
         return 0;
 }
 
+/*
+ * /proc/stat helpers
+ */
+u64 arch_irq_stat_cpu(unsigned int cpu)
+{
+        u64 sum = nmi_count(cpu);
+
+#ifdef CONFIG_X86_LOCAL_APIC
+        sum += per_cpu(irq_stat, cpu).apic_timer_irqs;
+#endif
+#ifdef CONFIG_SMP
+        sum += per_cpu(irq_stat, cpu).irq_resched_count;
+        sum += per_cpu(irq_stat, cpu).irq_call_count;
+        sum += per_cpu(irq_stat, cpu).irq_tlb_count;
+#endif
+#ifdef CONFIG_X86_MCE
+        sum += per_cpu(irq_stat, cpu).irq_thermal_count;
+#endif
+#ifdef CONFIG_X86_LOCAL_APIC
+        sum += per_cpu(irq_stat, cpu).irq_spurious_count;
+#endif
+        return sum;
+}
+
+u64 arch_irq_stat(void)
+{
+        u64 sum = atomic_read(&irq_err_count);
+
+#ifdef CONFIG_X86_IO_APIC
+        sum += atomic_read(&irq_mis_count);
+#endif
+        return sum;
+}
+
 #ifdef CONFIG_HOTPLUG_CPU
 #include <mach_apic.h>
 
diff --git a/arch/x86/kernel/irq_64.c b/arch/x86/kernel/irq_64.c
index 3aac15466a91..1f78b238d8d2 100644
--- a/arch/x86/kernel/irq_64.c
+++ b/arch/x86/kernel/irq_64.c
@@ -135,6 +135,7 @@ skip:
                         seq_printf(p, "%10u ", cpu_pda(j)->irq_tlb_count);
                 seq_printf(p, "  TLB shootdowns\n");
 #endif
+#ifdef CONFIG_X86_MCE
                 seq_printf(p, "TRM: ");
                 for_each_online_cpu(j)
                         seq_printf(p, "%10u ", cpu_pda(j)->irq_thermal_count);
@@ -143,6 +144,7 @@ skip:
                 for_each_online_cpu(j)
                         seq_printf(p, "%10u ", cpu_pda(j)->irq_threshold_count);
                 seq_printf(p, "  Threshold APIC interrupts\n");
+#endif
                 seq_printf(p, "SPU: ");
                 for_each_online_cpu(j)
                         seq_printf(p, "%10u ", cpu_pda(j)->irq_spurious_count);
@@ -153,6 +155,32 @@ skip:
 }
 
 /*
+ * /proc/stat helpers
+ */
+u64 arch_irq_stat_cpu(unsigned int cpu)
+{
+        u64 sum = cpu_pda(cpu)->__nmi_count;
+
+        sum += cpu_pda(cpu)->apic_timer_irqs;
+#ifdef CONFIG_SMP
+        sum += cpu_pda(cpu)->irq_resched_count;
+        sum += cpu_pda(cpu)->irq_call_count;
+        sum += cpu_pda(cpu)->irq_tlb_count;
+#endif
+#ifdef CONFIG_X86_MCE
+        sum += cpu_pda(cpu)->irq_thermal_count;
+        sum += cpu_pda(cpu)->irq_threshold_count;
+#endif
+        sum += cpu_pda(cpu)->irq_spurious_count;
+        return sum;
+}
+
+u64 arch_irq_stat(void)
+{
+        return atomic_read(&irq_err_count);
+}
+
+/*
  * do_IRQ handles all normal device IRQ's (the special
  * SMP cross-CPU interrupts have their own specific
  * handlers).
diff --git a/arch/x86/kernel/irqinit_32.c b/arch/x86/kernel/irqinit_32.c
new file mode 100644
index 000000000000..d66914287ee1
--- /dev/null
+++ b/arch/x86/kernel/irqinit_32.c
@@ -0,0 +1,114 @@
+#include <linux/errno.h>
+#include <linux/signal.h>
+#include <linux/sched.h>
+#include <linux/ioport.h>
+#include <linux/interrupt.h>
+#include <linux/slab.h>
+#include <linux/random.h>
+#include <linux/init.h>
+#include <linux/kernel_stat.h>
+#include <linux/sysdev.h>
+#include <linux/bitops.h>
+
+#include <asm/atomic.h>
+#include <asm/system.h>
+#include <asm/io.h>
+#include <asm/timer.h>
+#include <asm/pgtable.h>
+#include <asm/delay.h>
+#include <asm/desc.h>
+#include <asm/apic.h>
+#include <asm/arch_hooks.h>
+#include <asm/i8259.h>
+
+
+
+/*
+ * Note that on a 486, we don't want to do a SIGFPE on an irq13
+ * as the irq is unreliable, and exception 16 works correctly
+ * (ie as explained in the intel literature). On a 386, you
+ * can't use exception 16 due to bad IBM design, so we have to
+ * rely on the less exact irq13.
+ *
+ * Careful.. Not only is IRQ13 unreliable, but it is also
+ * leads to races. IBM designers who came up with it should
+ * be shot.
+ */
+ 
+
+static irqreturn_t math_error_irq(int cpl, void *dev_id)
+{
+        extern void math_error(void __user *);
+        outb(0,0xF0);
+        if (ignore_fpu_irq || !boot_cpu_data.hard_math)
+                return IRQ_NONE;
+        math_error((void __user *)get_irq_regs()->ip);
+        return IRQ_HANDLED;
+}
+
+/*
+ * New motherboards sometimes make IRQ 13 be a PCI interrupt,
+ * so allow interrupt sharing.
+ */
+static struct irqaction fpu_irq = {
+        .handler = math_error_irq,
+        .mask = CPU_MASK_NONE,
+        .name = "fpu",
+};
+
+void __init init_ISA_irqs (void)
+{
+        int i;
+
+#ifdef CONFIG_X86_LOCAL_APIC
+        init_bsp_APIC();
+#endif
+        init_8259A(0);
+
+        /*
+         * 16 old-style INTA-cycle interrupts:
+         */
+        for (i = 0; i < 16; i++) {
+                set_irq_chip_and_handler_name(i, &i8259A_chip,
+                                              handle_level_irq, "XT");
+        }
+}
+
+/* Overridden in paravirt.c */
+void init_IRQ(void) __attribute__((weak, alias("native_init_IRQ")));
+
+void __init native_init_IRQ(void)
+{
+        int i;
+
+        /* all the set up before the call gates are initialised */
+        pre_intr_init_hook();
+
+        /*
+         * Cover the whole vector space, no vector can escape
+         * us. (some of these will be overridden and become
+         * 'special' SMP interrupts)
+         */
+        for (i = 0; i < (NR_VECTORS - FIRST_EXTERNAL_VECTOR); i++) {
+                int vector = FIRST_EXTERNAL_VECTOR + i;
+                if (i >= NR_IRQS)
+                        break;
+                /* SYSCALL_VECTOR was reserved in trap_init. */
+                if (!test_bit(vector, used_vectors))
+                        set_intr_gate(vector, interrupt[i]);
+        }
+
+        /* setup after call gates are initialised (usually add in
+         * the architecture specific gates)
+         */
+        intr_init_hook();
+
+        /*
+         * External FPU? Set up irq13 if so, for
+         * original braindamaged IBM FERR coupling.
+         */
+        if (boot_cpu_data.hard_math && !cpu_has_fpu)
+                setup_irq(FPU_IRQ, &fpu_irq);
+
+        irq_ctx_init(smp_processor_id());
+}
diff --git a/arch/x86/kernel/irqinit_64.c b/arch/x86/kernel/irqinit_64.c
new file mode 100644
index 000000000000..31f49e8f46a7
--- /dev/null
+++ b/arch/x86/kernel/irqinit_64.c
@@ -0,0 +1,217 @@
+#include <linux/linkage.h>
+#include <linux/errno.h>
+#include <linux/signal.h>
+#include <linux/sched.h>
+#include <linux/ioport.h>
+#include <linux/interrupt.h>
+#include <linux/timex.h>
+#include <linux/slab.h>
+#include <linux/random.h>
+#include <linux/init.h>
+#include <linux/kernel_stat.h>
+#include <linux/sysdev.h>
+#include <linux/bitops.h>
+
+#include <asm/acpi.h>
+#include <asm/atomic.h>
+#include <asm/system.h>
+#include <asm/io.h>
+#include <asm/hw_irq.h>
+#include <asm/pgtable.h>
+#include <asm/delay.h>
+#include <asm/desc.h>
+#include <asm/apic.h>
+#include <asm/i8259.h>
+
+/*
+ * Common place to define all x86 IRQ vectors
+ *
+ * This builds up the IRQ handler stubs using some ugly macros in irq.h
+ *
+ * These macros create the low-level assembly IRQ routines that save
+ * register context and call do_IRQ(). do_IRQ() then does all the
+ * operations that are needed to keep the AT (or SMP IOAPIC)
+ * interrupt-controller happy.
+ */
+
+#define IRQ_NAME2(nr) nr##_interrupt(void)
+#define IRQ_NAME(nr) IRQ_NAME2(IRQ##nr)
+
+/*
+ *      SMP has a few special interrupts for IPI messages
+ */
+
+#define BUILD_IRQ(nr)                           \
+        asmlinkage void IRQ_NAME(nr);           \
+        asm("\n.p2align\n"                      \
+            "IRQ" #nr "_interrupt:\n\t"         \
+            "push $~(" #nr ") ; "               \
+            "jmp common_interrupt");
+
+#define BI(x,y) \
+        BUILD_IRQ(x##y)
+
+#define BUILD_16_IRQS(x) \
+        BI(x,0) BI(x,1) BI(x,2) BI(x,3) \
+        BI(x,4) BI(x,5) BI(x,6) BI(x,7) \
+        BI(x,8) BI(x,9) BI(x,a) BI(x,b) \
+        BI(x,c) BI(x,d) BI(x,e) BI(x,f)
+
+/*
+ * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts:
+ * (these are usually mapped to vectors 0x30-0x3f)
+ */
+
+/*
+ * The IO-APIC gives us many more interrupt sources. Most of these
+ * are unused but an SMP system is supposed to have enough memory ...
+ * sometimes (mostly wrt. hw bugs) we get corrupted vectors all
+ * across the spectrum, so we really want to be prepared to get all
+ * of these. Plus, more powerful systems might have more than 64
+ * IO-APIC registers.
+ *
+ * (these are usually mapped into the 0x30-0xff vector range)
+ */
+                                      BUILD_16_IRQS(0x2) BUILD_16_IRQS(0x3)
+BUILD_16_IRQS(0x4) BUILD_16_IRQS(0x5) BUILD_16_IRQS(0x6) BUILD_16_IRQS(0x7)
+BUILD_16_IRQS(0x8) BUILD_16_IRQS(0x9) BUILD_16_IRQS(0xa) BUILD_16_IRQS(0xb)
+BUILD_16_IRQS(0xc) BUILD_16_IRQS(0xd) BUILD_16_IRQS(0xe) BUILD_16_IRQS(0xf)
+
+#undef BUILD_16_IRQS
+#undef BI
+
+
+#define IRQ(x,y) \
+        IRQ##x##y##_interrupt
+
+#define IRQLIST_16(x) \
+        IRQ(x,0), IRQ(x,1), IRQ(x,2), IRQ(x,3), \
+        IRQ(x,4), IRQ(x,5), IRQ(x,6), IRQ(x,7), \
+        IRQ(x,8), IRQ(x,9), IRQ(x,a), IRQ(x,b), \
+        IRQ(x,c), IRQ(x,d), IRQ(x,e), IRQ(x,f)
+
+/* for the irq vectors */
+static void (*__initdata interrupt[NR_VECTORS - FIRST_EXTERNAL_VECTOR])(void) = {
+                                          IRQLIST_16(0x2), IRQLIST_16(0x3),
+        IRQLIST_16(0x4), IRQLIST_16(0x5), IRQLIST_16(0x6), IRQLIST_16(0x7),
+        IRQLIST_16(0x8), IRQLIST_16(0x9), IRQLIST_16(0xa), IRQLIST_16(0xb),
+        IRQLIST_16(0xc), IRQLIST_16(0xd), IRQLIST_16(0xe), IRQLIST_16(0xf)
+};
+
+#undef IRQ
+#undef IRQLIST_16
+
+
+
+
+/*
+ * IRQ2 is cascade interrupt to second interrupt controller
+ */
+
+static struct irqaction irq2 = {
+        .handler = no_action,
+        .mask = CPU_MASK_NONE,
+        .name = "cascade",
+};
+DEFINE_PER_CPU(vector_irq_t, vector_irq) = {
+        [0 ... IRQ0_VECTOR - 1] = -1,
+        [IRQ0_VECTOR] = 0,
+        [IRQ1_VECTOR] = 1,
+        [IRQ2_VECTOR] = 2,
+        [IRQ3_VECTOR] = 3,
+        [IRQ4_VECTOR] = 4,
+        [IRQ5_VECTOR] = 5,
+        [IRQ6_VECTOR] = 6,
+        [IRQ7_VECTOR] = 7,
+        [IRQ8_VECTOR] = 8,
+        [IRQ9_VECTOR] = 9,
+        [IRQ10_VECTOR] = 10,
+        [IRQ11_VECTOR] = 11,
+        [IRQ12_VECTOR] = 12,
+        [IRQ13_VECTOR] = 13,
+        [IRQ14_VECTOR] = 14,
+        [IRQ15_VECTOR] = 15,
+        [IRQ15_VECTOR + 1 ... NR_VECTORS - 1] = -1
+};
+
+static void __init init_ISA_irqs (void)
+{
+        int i;
+
+        init_bsp_APIC();
+        init_8259A(0);
+
+        for (i = 0; i < NR_IRQS; i++) {
+                irq_desc[i].status = IRQ_DISABLED;
+                irq_desc[i].action = NULL;
+                irq_desc[i].depth = 1;
+
+                if (i < 16) {
+                        /*
+                         * 16 old-style INTA-cycle interrupts:
+                         */
+                        set_irq_chip_and_handler_name(i, &i8259A_chip,
+                                                      handle_level_irq, "XT");
+                } else {
+                        /*
+                         * 'high' PCI IRQs filled in on demand
+                         */
+                        irq_desc[i].chip = &no_irq_chip;
+                }
+        }
+}
+
+void init_IRQ(void) __attribute__((weak, alias("native_init_IRQ")));
+
+void __init native_init_IRQ(void)
+{
+        int i;
+
+        init_ISA_irqs();
+        /*
+         * Cover the whole vector space, no vector can escape
+         * us. (some of these will be overridden and become
+         * 'special' SMP interrupts)
+         */
+        for (i = 0; i < (NR_VECTORS - FIRST_EXTERNAL_VECTOR); i++) {
+                int vector = FIRST_EXTERNAL_VECTOR + i;
+                if (vector != IA32_SYSCALL_VECTOR)
+                        set_intr_gate(vector, interrupt[i]);
+        }
+
+#ifdef CONFIG_SMP
+        /*
+         * The reschedule interrupt is a CPU-to-CPU reschedule-helper
+         * IPI, driven by wakeup.
+         */
+        alloc_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
+
+        /* IPIs for invalidation */
+        alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+0, invalidate_interrupt0);
+        alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+1, invalidate_interrupt1);
+        alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+2, invalidate_interrupt2);
+        alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+3, invalidate_interrupt3);
+        alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+4, invalidate_interrupt4);
+        alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+5, invalidate_interrupt5);
+        alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+6, invalidate_interrupt6);
+        alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+7, invalidate_interrupt7);
+
+        /* IPI for generic function call */
+        alloc_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
+
+        /* Low priority IPI to cleanup after moving an irq */
+        set_intr_gate(IRQ_MOVE_CLEANUP_VECTOR, irq_move_cleanup_interrupt);
+#endif
+        alloc_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
+        alloc_intr_gate(THRESHOLD_APIC_VECTOR, threshold_interrupt);
+
+        /* self generated IPI for local APIC timer */
+        alloc_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
+
+        /* IPI vectors for APIC spurious and error interrupts */
+        alloc_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
+        alloc_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
+
+        if (!acpi_ioapic)
+                setup_irq(2, &irq2);
+}
diff --git a/arch/x86/kernel/ldt.c b/arch/x86/kernel/ldt.c
index 0224c3637c73..21f2bae98c15 100644
--- a/arch/x86/kernel/ldt.c
+++ b/arch/x86/kernel/ldt.c
@@ -20,9 +20,9 @@
 #include <asm/mmu_context.h>
 
 #ifdef CONFIG_SMP
-static void flush_ldt(void *null)
+static void flush_ldt(void *current_mm)
 {
-        if (current->active_mm)
+        if (current->active_mm == current_mm)
                 load_LDT(&current->active_mm->context);
 }
 #endif
@@ -68,7 +68,7 @@ static int alloc_ldt(mm_context_t *pc, int mincount, int reload)
                 load_LDT(pc);
                 mask = cpumask_of_cpu(smp_processor_id());
                 if (!cpus_equal(current->mm->cpu_vm_mask, mask))
-                        smp_call_function(flush_ldt, NULL, 1, 1);
+                        smp_call_function(flush_ldt, current->mm, 1, 1);
                 preempt_enable();
 #else
                 load_LDT(pc);
diff --git a/arch/x86/kernel/machine_kexec_32.c b/arch/x86/kernel/machine_kexec_32.c
index d0b234c9fc31..8864230d55af 100644
--- a/arch/x86/kernel/machine_kexec_32.c
+++ b/arch/x86/kernel/machine_kexec_32.c
@@ -11,6 +11,8 @@
 #include <linux/delay.h>
 #include <linux/init.h>
 #include <linux/numa.h>
+#include <linux/ftrace.h>
+
 #include <asm/pgtable.h>
 #include <asm/pgalloc.h>
 #include <asm/tlbflush.h>
@@ -39,7 +41,7 @@ static void set_idt(void *newidt, __u16 limit)
         curidt.address = (unsigned long)newidt;
 
         load_idt(&curidt);
-};
+}
 
 
 static void set_gdt(void *newgdt, __u16 limit)
@@ -51,7 +53,7 @@ static void set_gdt(void *newgdt, __u16 limit)
         curgdt.address = (unsigned long)newgdt;
 
         load_gdt(&curgdt);
-};
+}
 
 static void load_segments(void)
 {
@@ -107,6 +109,8 @@ NORET_TYPE void machine_kexec(struct kimage *image)
         unsigned long page_list[PAGES_NR];
         void *control_page;
 
+        tracer_disable();
+
         /* Interrupts aren't acceptable while we reboot */
         local_irq_disable();
 
diff --git a/arch/x86/kernel/machine_kexec_64.c b/arch/x86/kernel/machine_kexec_64.c
index 576a03db4511..9dd9262693a3 100644
--- a/arch/x86/kernel/machine_kexec_64.c
+++ b/arch/x86/kernel/machine_kexec_64.c
@@ -11,6 +11,8 @@
 #include <linux/string.h>
 #include <linux/reboot.h>
 #include <linux/numa.h>
+#include <linux/ftrace.h>
+
 #include <asm/pgtable.h>
 #include <asm/tlbflush.h>
 #include <asm/mmu_context.h>
@@ -110,7 +112,7 @@ static int init_pgtable(struct kimage *image, unsigned long start_pgtable)
 {
         pgd_t *level4p;
         level4p = (pgd_t *)__va(start_pgtable);
-        return init_level4_page(image, level4p, 0, end_pfn << PAGE_SHIFT);
+        return init_level4_page(image, level4p, 0, max_pfn << PAGE_SHIFT);
 }
 
 static void set_idt(void *newidt, u16 limit)
@@ -184,6 +186,8 @@ NORET_TYPE void machine_kexec(struct kimage *image)
         unsigned long page_list[PAGES_NR];
         void *control_page;
 
+        tracer_disable();
+
         /* Interrupts aren't acceptable while we reboot */
         local_irq_disable();
 
diff --git a/arch/x86/kernel/microcode.c b/arch/x86/kernel/microcode.c
index 69729e38b78a..f47ba8156f3e 100644
--- a/arch/x86/kernel/microcode.c
+++ b/arch/x86/kernel/microcode.c
@@ -5,13 +5,14 @@
  *                    2006      Shaohua Li <shaohua.li@intel.com>
  *
  *      This driver allows to upgrade microcode on Intel processors
- *      belonging to IA-32 family - PentiumPro, Pentium II, 
+ *      belonging to IA-32 family - PentiumPro, Pentium II,
  *      Pentium III, Xeon, Pentium 4, etc.
  *
- *      Reference: Section 8.10 of Volume III, Intel Pentium 4 Manual, 
- *      Order Number 245472 or free download from:
- *              
- *      http://developer.intel.com/design/pentium4/manuals/245472.htm
+ *      Reference: Section 8.11 of Volume 3a, IA-32 Intel? Architecture
+ *      Software Developer's Manual
+ *      Order Number 253668 or free download from:
+ *
+ *      http://developer.intel.com/design/pentium4/manuals/253668.htm
  *
  *      For more information, go to http://www.urbanmyth.org/microcode
  *
@@ -58,12 +59,12 @@
  *              nature of implementation.
  *      1.11    22 Mar 2002 Tigran Aivazian <tigran@veritas.com>
  *              Fix the panic when writing zero-length microcode chunk.
- *      1.12    29 Sep 2003 Nitin Kamble <nitin.a.kamble@intel.com>, 
+ *      1.12    29 Sep 2003 Nitin Kamble <nitin.a.kamble@intel.com>,
  *              Jun Nakajima <jun.nakajima@intel.com>
  *              Support for the microcode updates in the new format.
  *      1.13    10 Oct 2003 Tigran Aivazian <tigran@veritas.com>
  *              Removed ->read() method and obsoleted MICROCODE_IOCFREE ioctl
- *              because we no longer hold a copy of applied microcode 
+ *              because we no longer hold a copy of applied microcode
  *              in kernel memory.
  *      1.14    25 Jun 2004 Tigran Aivazian <tigran@veritas.com>
  *              Fix sigmatch() macro to handle old CPUs with pf == 0.
@@ -75,6 +76,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/sched.h>
+#include <linux/smp_lock.h>
 #include <linux/cpumask.h>
 #include <linux/module.h>
 #include <linux/slab.h>
@@ -320,11 +322,11 @@ static void apply_microcode(int cpu)
                 return;
 
         /* serialize access to the physical write to MSR 0x79 */
-        spin_lock_irqsave(&microcode_update_lock, flags);          
+        spin_lock_irqsave(&microcode_update_lock, flags);
 
         /* write microcode via MSR 0x79 */
         wrmsr(MSR_IA32_UCODE_WRITE,
-                (unsigned long) uci->mc->bits, 
+                (unsigned long) uci->mc->bits,
                 (unsigned long) uci->mc->bits >> 16 >> 16);
         wrmsr(MSR_IA32_UCODE_REV, 0, 0);
 
@@ -341,7 +343,7 @@ static void apply_microcode(int cpu)
                 return;
         }
         printk(KERN_INFO "microcode: CPU%d updated from revision "
-               "0x%x to 0x%x, date = %08x \n", 
+               "0x%x to 0x%x, date = %08x \n",
                cpu_num, uci->rev, val[1], uci->mc->hdr.date);
         uci->rev = val[1];
 }
@@ -422,6 +424,7 @@ out:
 
 static int microcode_open (struct inode *unused1, struct file *unused2)
 {
+        cycle_kernel_lock();
         return capable(CAP_SYS_RAWIO) ? 0 : -EPERM;
 }
 
@@ -534,7 +537,7 @@ static int cpu_request_microcode(int cpu)
                 c->x86, c->x86_model, c->x86_mask);
         error = request_firmware(&firmware, name, &microcode_pdev->dev);
         if (error) {
-                pr_debug("microcode: ucode data file %s load failed\n", name);
+                pr_debug("microcode: data file %s load failed\n", name);
                 return error;
         }
         buf = firmware->data;
@@ -805,6 +808,9 @@ static int __init microcode_init (void)
 {
         int error;
 
+        printk(KERN_INFO
+                "IA-32 Microcode Update Driver: v" MICROCODE_VERSION " <tigran@aivazian.fsnet.co.uk>\n");
+
         error = microcode_dev_init();
         if (error)
                 return error;
@@ -825,9 +831,6 @@ static int __init microcode_init (void)
         }
 
         register_hotcpu_notifier(&mc_cpu_notifier);
-
-        printk(KERN_INFO 
-                "IA-32 Microcode Update Driver: v" MICROCODE_VERSION " <tigran@aivazian.fsnet.co.uk>\n");
         return 0;
 }
 
diff --git a/arch/x86/kernel/mmconf-fam10h_64.c b/arch/x86/kernel/mmconf-fam10h_64.c
index edc5fbfe85c0..fdfdc550b366 100644
--- a/arch/x86/kernel/mmconf-fam10h_64.c
+++ b/arch/x86/kernel/mmconf-fam10h_64.c
@@ -12,6 +12,7 @@
 #include <asm/io.h>
 #include <asm/msr.h>
 #include <asm/acpi.h>
+#include <asm/mmconfig.h>
 
 #include "../pci/pci.h"
 
diff --git a/arch/x86/kernel/mpparse.c b/arch/x86/kernel/mpparse.c
index 404683b94e79..3b25e49380c6 100644
--- a/arch/x86/kernel/mpparse.c
+++ b/arch/x86/kernel/mpparse.c
@@ -25,6 +25,8 @@
 #include <asm/proto.h>
 #include <asm/acpi.h>
 #include <asm/bios_ebda.h>
+#include <asm/e820.h>
+#include <asm/trampoline.h>
 
 #include <mach_apic.h>
 #ifdef CONFIG_X86_32
@@ -32,28 +34,6 @@
 #include <mach_mpparse.h>
 #endif
 
-/* Have we found an MP table */
-int smp_found_config;
-
-/*
- * Various Linux-internal data structures created from the
- * MP-table.
- */
-#if defined (CONFIG_MCA) || defined (CONFIG_EISA)
-int mp_bus_id_to_type[MAX_MP_BUSSES];
-#endif
-
-DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
-int mp_bus_id_to_pci_bus[MAX_MP_BUSSES] = {[0 ... MAX_MP_BUSSES - 1] = -1 };
-
-static int mp_current_pci_id;
-
-int pic_mode;
-
-/*
- * Intel MP BIOS table parsing routines:
- */
-
 /*
  * Checksum an MP configuration block.
  */
@@ -69,15 +49,73 @@ static int __init mpf_checksum(unsigned char *mp, int len)
 }
 
 #ifdef CONFIG_X86_NUMAQ
+int found_numaq;
 /*
  * Have to match translation table entries to main table entries by counter
  * hence the mpc_record variable .... can't see a less disgusting way of
  * doing this ....
  */
+struct mpc_config_translation {
+        unsigned char mpc_type;
+        unsigned char trans_len;
+        unsigned char trans_type;
+        unsigned char trans_quad;
+        unsigned char trans_global;
+        unsigned char trans_local;
+        unsigned short trans_reserved;
+};
+
 
 static int mpc_record;
 static struct mpc_config_translation *translation_table[MAX_MPC_ENTRY]
     __cpuinitdata;
+
+static inline int generate_logical_apicid(int quad, int phys_apicid)
+{
+        return (quad << 4) + (phys_apicid ? phys_apicid << 1 : 1);
+}
+
+
+static inline int mpc_apic_id(struct mpc_config_processor *m,
+                        struct mpc_config_translation *translation_record)
+{
+        int quad = translation_record->trans_quad;
+        int logical_apicid = generate_logical_apicid(quad, m->mpc_apicid);
+
+        printk(KERN_DEBUG "Processor #%d %u:%u APIC version %d (quad %d, apic %d)\n",
+               m->mpc_apicid,
+               (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8,
+               (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4,
+               m->mpc_apicver, quad, logical_apicid);
+        return logical_apicid;
+}
+
+int mp_bus_id_to_node[MAX_MP_BUSSES];
+
+int mp_bus_id_to_local[MAX_MP_BUSSES];
+
+static void mpc_oem_bus_info(struct mpc_config_bus *m, char *name,
+        struct mpc_config_translation *translation)
+{
+        int quad = translation->trans_quad;
+        int local = translation->trans_local;
+
+        mp_bus_id_to_node[m->mpc_busid] = quad;
+        mp_bus_id_to_local[m->mpc_busid] = local;
+        printk(KERN_INFO "Bus #%d is %s (node %d)\n",
+               m->mpc_busid, name, quad);
+}
+
+int quad_local_to_mp_bus_id [NR_CPUS/4][4];
+static void mpc_oem_pci_bus(struct mpc_config_bus *m,
+        struct mpc_config_translation *translation)
+{
+        int quad = translation->trans_quad;
+        int local = translation->trans_local;
+
+        quad_local_to_mp_bus_id[quad][local] = m->mpc_busid;
+}
+
 #endif
 
 static void __cpuinit MP_processor_info(struct mpc_config_processor *m)
@@ -90,7 +128,10 @@ static void __cpuinit MP_processor_info(struct mpc_config_processor *m)
                 return;
         }
 #ifdef CONFIG_X86_NUMAQ
-        apicid = mpc_apic_id(m, translation_table[mpc_record]);
+        if (found_numaq)
+                apicid = mpc_apic_id(m, translation_table[mpc_record]);
+        else
+                apicid = m->mpc_apicid;
 #else
         apicid = m->mpc_apicid;
 #endif
@@ -103,17 +144,18 @@ static void __cpuinit MP_processor_info(struct mpc_config_processor *m)
         generic_processor_info(apicid, m->mpc_apicver);
 }
 
+#ifdef CONFIG_X86_IO_APIC
 static void __init MP_bus_info(struct mpc_config_bus *m)
 {
         char str[7];
-
         memcpy(str, m->mpc_bustype, 6);
         str[6] = 0;
 
 #ifdef CONFIG_X86_NUMAQ
-        mpc_oem_bus_info(m, str, translation_table[mpc_record]);
+        if (found_numaq)
+                mpc_oem_bus_info(m, str, translation_table[mpc_record]);
 #else
-        Dprintk("Bus #%d is %s\n", m->mpc_busid, str);
+        printk(KERN_INFO "Bus #%d is %s\n", m->mpc_busid, str);
 #endif
 
 #if MAX_MP_BUSSES < 256
@@ -132,11 +174,10 @@ static void __init MP_bus_info(struct mpc_config_bus *m)
 #endif
         } else if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI) - 1) == 0) {
 #ifdef CONFIG_X86_NUMAQ
-                mpc_oem_pci_bus(m, translation_table[mpc_record]);
+                if (found_numaq)
+                        mpc_oem_pci_bus(m, translation_table[mpc_record]);
 #endif
                 clear_bit(m->mpc_busid, mp_bus_not_pci);
-                mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
-                mp_current_pci_id++;
 #if defined(CONFIG_EISA) || defined (CONFIG_MCA)
                 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI;
         } else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA) - 1) == 0) {
@@ -147,6 +188,7 @@ static void __init MP_bus_info(struct mpc_config_bus *m)
         } else
                 printk(KERN_WARNING "Unknown bustype %s - ignoring\n", str);
 }
+#endif
 
 #ifdef CONFIG_X86_IO_APIC
 
@@ -176,18 +218,89 @@ static void __init MP_ioapic_info(struct mpc_config_ioapic *m)
         if (bad_ioapic(m->mpc_apicaddr))
                 return;
 
-        mp_ioapics[nr_ioapics] = *m;
+        mp_ioapics[nr_ioapics].mp_apicaddr = m->mpc_apicaddr;
+        mp_ioapics[nr_ioapics].mp_apicid = m->mpc_apicid;
+        mp_ioapics[nr_ioapics].mp_type = m->mpc_type;
+        mp_ioapics[nr_ioapics].mp_apicver = m->mpc_apicver;
+        mp_ioapics[nr_ioapics].mp_flags = m->mpc_flags;
         nr_ioapics++;
 }
 
-static void __init MP_intsrc_info(struct mpc_config_intsrc *m)
+static void print_MP_intsrc_info(struct mpc_config_intsrc *m)
 {
-        mp_irqs[mp_irq_entries] = *m;
-        Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
+        printk(KERN_CONT "Int: type %d, pol %d, trig %d, bus %02x,"
                 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
                 m->mpc_irqtype, m->mpc_irqflag & 3,
                 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
                 m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
+}
+
+static void __init print_mp_irq_info(struct mp_config_intsrc *mp_irq)
+{
+        printk(KERN_CONT "Int: type %d, pol %d, trig %d, bus %02x,"
+                " IRQ %02x, APIC ID %x, APIC INT %02x\n",
+                mp_irq->mp_irqtype, mp_irq->mp_irqflag & 3,
+                (mp_irq->mp_irqflag >> 2) & 3, mp_irq->mp_srcbus,
+                mp_irq->mp_srcbusirq, mp_irq->mp_dstapic, mp_irq->mp_dstirq);
+}
+
+static void __init assign_to_mp_irq(struct mpc_config_intsrc *m,
+                                    struct mp_config_intsrc *mp_irq)
+{
+        mp_irq->mp_dstapic = m->mpc_dstapic;
+        mp_irq->mp_type = m->mpc_type;
+        mp_irq->mp_irqtype = m->mpc_irqtype;
+        mp_irq->mp_irqflag = m->mpc_irqflag;
+        mp_irq->mp_srcbus = m->mpc_srcbus;
+        mp_irq->mp_srcbusirq = m->mpc_srcbusirq;
+        mp_irq->mp_dstirq = m->mpc_dstirq;
+}
+
+static void __init assign_to_mpc_intsrc(struct mp_config_intsrc *mp_irq,
+                                        struct mpc_config_intsrc *m)
+{
+        m->mpc_dstapic = mp_irq->mp_dstapic;
+        m->mpc_type = mp_irq->mp_type;
+        m->mpc_irqtype = mp_irq->mp_irqtype;
+        m->mpc_irqflag = mp_irq->mp_irqflag;
+        m->mpc_srcbus = mp_irq->mp_srcbus;
+        m->mpc_srcbusirq = mp_irq->mp_srcbusirq;
+        m->mpc_dstirq = mp_irq->mp_dstirq;
+}
+
+static int __init mp_irq_mpc_intsrc_cmp(struct mp_config_intsrc *mp_irq,
+                                        struct mpc_config_intsrc *m)
+{
+        if (mp_irq->mp_dstapic != m->mpc_dstapic)
+                return 1;
+        if (mp_irq->mp_type != m->mpc_type)
+                return 2;
+        if (mp_irq->mp_irqtype != m->mpc_irqtype)
+                return 3;
+        if (mp_irq->mp_irqflag != m->mpc_irqflag)
+                return 4;
+        if (mp_irq->mp_srcbus != m->mpc_srcbus)
+                return 5;
+        if (mp_irq->mp_srcbusirq != m->mpc_srcbusirq)
+                return 6;
+        if (mp_irq->mp_dstirq != m->mpc_dstirq)
+                return 7;
+
+        return 0;
+}
+
+static void __init MP_intsrc_info(struct mpc_config_intsrc *m)
+{
+        int i;
+
+        print_MP_intsrc_info(m);
+
+        for (i = 0; i < mp_irq_entries; i++) {
+                if (!mp_irq_mpc_intsrc_cmp(&mp_irqs[i], m))
+                        return;
+        }
+
+        assign_to_mp_irq(m, &mp_irqs[mp_irq_entries]);
         if (++mp_irq_entries == MAX_IRQ_SOURCES)
                 panic("Max # of irq sources exceeded!!\n");
 }
@@ -196,7 +309,7 @@ static void __init MP_intsrc_info(struct mpc_config_intsrc *m)
 
 static void __init MP_lintsrc_info(struct mpc_config_lintsrc *m)
 {
-        Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
+        printk(KERN_INFO "Lint: type %d, pol %d, trig %d, bus %02x,"
                 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
                 m->mpc_irqtype, m->mpc_irqflag & 3,
                 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbusid,
@@ -266,11 +379,14 @@ static void __init smp_read_mpc_oem(struct mp_config_oemtable *oemtable,
         }
 }
 
-static inline void mps_oem_check(struct mp_config_table *mpc, char *oem,
+void numaq_mps_oem_check(struct mp_config_table *mpc, char *oem,
                                  char *productid)
 {
         if (strncmp(oem, "IBM NUMA", 8))
-                printk("Warning!  May not be a NUMA-Q system!\n");
+                printk("Warning!  Not a NUMA-Q system!\n");
+        else
+                found_numaq = 1;
+
         if (mpc->mpc_oemptr)
                 smp_read_mpc_oem((struct mp_config_oemtable *)mpc->mpc_oemptr,
                                  mpc->mpc_oemsize);
@@ -281,12 +397,9 @@ static inline void mps_oem_check(struct mp_config_table *mpc, char *oem,
  * Read/parse the MPC
  */
 
-static int __init smp_read_mpc(struct mp_config_table *mpc, unsigned early)
+static int __init smp_check_mpc(struct mp_config_table *mpc, char *oem,
+                                char *str)
 {
-        char str[16];
-        char oem[10];
-        int count = sizeof(*mpc);
-        unsigned char *mpt = ((unsigned char *)mpc) + count;
 
         if (memcmp(mpc->mpc_signature, MPC_SIGNATURE, 4)) {
                 printk(KERN_ERR "MPTABLE: bad signature [%c%c%c%c]!\n",
@@ -309,19 +422,42 @@ static int __init smp_read_mpc(struct mp_config_table *mpc, unsigned early)
         }
         memcpy(oem, mpc->mpc_oem, 8);
         oem[8] = 0;
-        printk(KERN_INFO "MPTABLE: OEM ID: %s ", oem);
+        printk(KERN_INFO "MPTABLE: OEM ID: %s\n", oem);
 
         memcpy(str, mpc->mpc_productid, 12);
         str[12] = 0;
-        printk("Product ID: %s ", str);
 
-#ifdef CONFIG_X86_32
-        mps_oem_check(mpc, oem, str);
-#endif
-        printk(KERN_INFO "MPTABLE: Product ID: %s ", str);
+        printk(KERN_INFO "MPTABLE: Product ID: %s\n", str);
 
         printk(KERN_INFO "MPTABLE: APIC at: 0x%X\n", mpc->mpc_lapic);
 
+        return 1;
+}
+
+static int __init smp_read_mpc(struct mp_config_table *mpc, unsigned early)
+{
+        char str[16];
+        char oem[10];
+
+        int count = sizeof(*mpc);
+        unsigned char *mpt = ((unsigned char *)mpc) + count;
+
+        if (!smp_check_mpc(mpc, oem, str))
+                return 0;
+
+#ifdef CONFIG_X86_32
+        /*
+         * need to make sure summit and es7000's mps_oem_check is safe to be
+         * called early via genericarch 's mps_oem_check
+         */
+        if (early) {
+#ifdef CONFIG_X86_NUMAQ
+                numaq_mps_oem_check(mpc, oem, str);
+#endif
+        } else
+                mps_oem_check(mpc, oem, str);
+#endif
+
         /* save the local APIC address, it might be non-default */
         if (!acpi_lapic)
                 mp_lapic_addr = mpc->mpc_lapic;
@@ -352,7 +488,9 @@ static int __init smp_read_mpc(struct mp_config_table *mpc, unsigned early)
                         {
                                 struct mpc_config_bus *m =
                                     (struct mpc_config_bus *)mpt;
+#ifdef CONFIG_X86_IO_APIC
                                 MP_bus_info(m);
+#endif
                                 mpt += sizeof(*m);
                                 count += sizeof(*m);
                                 break;
@@ -402,6 +540,11 @@ static int __init smp_read_mpc(struct mp_config_table *mpc, unsigned early)
                 ++mpc_record;
 #endif
         }
+
+#ifdef CONFIG_X86_GENERICARCH
+       generic_bigsmp_probe();
+#endif
+
         setup_apic_routing();
         if (!num_processors)
                 printk(KERN_ERR "MPTABLE: no processors registered!\n");
@@ -427,7 +570,7 @@ static void __init construct_default_ioirq_mptable(int mpc_default_type)
         intsrc.mpc_type = MP_INTSRC;
         intsrc.mpc_irqflag = 0; /* conforming */
         intsrc.mpc_srcbus = 0;
-        intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
+        intsrc.mpc_dstapic = mp_ioapics[0].mp_apicid;
 
         intsrc.mpc_irqtype = mp_INT;
 
@@ -488,40 +631,11 @@ static void __init construct_default_ioirq_mptable(int mpc_default_type)
         MP_intsrc_info(&intsrc);
 }
 
-#endif
 
-static inline void __init construct_default_ISA_mptable(int mpc_default_type)
+static void construct_ioapic_table(int mpc_default_type)
 {
-        struct mpc_config_processor processor;
-        struct mpc_config_bus bus;
-#ifdef CONFIG_X86_IO_APIC
         struct mpc_config_ioapic ioapic;
-#endif
-        struct mpc_config_lintsrc lintsrc;
-        int linttypes[2] = { mp_ExtINT, mp_NMI };
-        int i;
-
-        /*
-         * local APIC has default address
-         */
-        mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
-
-        /*
-         * 2 CPUs, numbered 0 & 1.
-         */
-        processor.mpc_type = MP_PROCESSOR;
-        /* Either an integrated APIC or a discrete 82489DX. */
-        processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
-        processor.mpc_cpuflag = CPU_ENABLED;
-        processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
-            (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
-        processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
-        processor.mpc_reserved[0] = 0;
-        processor.mpc_reserved[1] = 0;
-        for (i = 0; i < 2; i++) {
-                processor.mpc_apicid = i;
-                MP_processor_info(&processor);
-        }
+        struct mpc_config_bus bus;
 
         bus.mpc_type = MP_BUS;
         bus.mpc_busid = 0;
@@ -550,7 +664,6 @@ static inline void __init construct_default_ISA_mptable(int mpc_default_type)
                 MP_bus_info(&bus);
         }
 
-#ifdef CONFIG_X86_IO_APIC
         ioapic.mpc_type = MP_IOAPIC;
         ioapic.mpc_apicid = 2;
         ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
@@ -562,7 +675,42 @@ static inline void __init construct_default_ISA_mptable(int mpc_default_type)
          * We set up most of the low 16 IO-APIC pins according to MPS rules.
          */
         construct_default_ioirq_mptable(mpc_default_type);
+}
+#else
+static inline void construct_ioapic_table(int mpc_default_type) { }
 #endif
+
+static inline void __init construct_default_ISA_mptable(int mpc_default_type)
+{
+        struct mpc_config_processor processor;
+        struct mpc_config_lintsrc lintsrc;
+        int linttypes[2] = { mp_ExtINT, mp_NMI };
+        int i;
+
+        /*
+         * local APIC has default address
+         */
+        mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
+
+        /*
+         * 2 CPUs, numbered 0 & 1.
+         */
+        processor.mpc_type = MP_PROCESSOR;
+        /* Either an integrated APIC or a discrete 82489DX. */
+        processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
+        processor.mpc_cpuflag = CPU_ENABLED;
+        processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
+            (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
+        processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
+        processor.mpc_reserved[0] = 0;
+        processor.mpc_reserved[1] = 0;
+        for (i = 0; i < 2; i++) {
+                processor.mpc_apicid = i;
+                MP_processor_info(&processor);
+        }
+
+        construct_ioapic_table(mpc_default_type);
+
         lintsrc.mpc_type = MP_LINTSRC;
         lintsrc.mpc_irqflag = 0;        /* conforming */
         lintsrc.mpc_srcbusid = 0;
@@ -578,12 +726,22 @@ static inline void __init construct_default_ISA_mptable(int mpc_default_type)
 static struct intel_mp_floating *mpf_found;
 
 /*
+ * Machine specific quirk for finding the SMP config before other setup
+ * activities destroy the table:
+ */
+int (*mach_get_smp_config_quirk)(unsigned int early);
+
+/*
  * Scan the memory blocks for an SMP configuration block.
  */
-static void __init __get_smp_config(unsigned early)
+static void __init __get_smp_config(unsigned int early)
 {
         struct intel_mp_floating *mpf = mpf_found;
 
+        if (mach_get_smp_config_quirk) {
+                if (mach_get_smp_config_quirk(early))
+                        return;
+        }
         if (acpi_lapic && early)
                 return;
         /*
@@ -600,7 +758,7 @@ static void __init __get_smp_config(unsigned early)
 
         printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n",
                mpf->mpf_specification);
-#ifdef CONFIG_X86_32
+#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
         if (mpf->mpf_feature2 & (1 << 7)) {
                 printk(KERN_INFO "    IMCR and PIC compatibility mode.\n");
                 pic_mode = 1;
@@ -632,7 +790,9 @@ static void __init __get_smp_config(unsigned early)
                  * override the defaults.
                  */
                 if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr), early)) {
+#ifdef CONFIG_X86_LOCAL_APIC
                         smp_found_config = 0;
+#endif
                         printk(KERN_ERR
                                "BIOS bug, MP table errors detected!...\n");
                         printk(KERN_ERR "... disabling SMP support. "
@@ -689,7 +849,7 @@ static int __init smp_scan_config(unsigned long base, unsigned long length,
         unsigned int *bp = phys_to_virt(base);
         struct intel_mp_floating *mpf;
 
-        Dprintk("Scan SMP from %p for %ld bytes.\n", bp, length);
+        printk(KERN_DEBUG "Scan SMP from %p for %ld bytes.\n", bp, length);
         BUILD_BUG_ON(sizeof(*mpf) != 16);
 
         while (length > 0) {
@@ -699,15 +859,21 @@ static int __init smp_scan_config(unsigned long base, unsigned long length,
                     !mpf_checksum((unsigned char *)bp, 16) &&
                     ((mpf->mpf_specification == 1)
                      || (mpf->mpf_specification == 4))) {
-
+#ifdef CONFIG_X86_LOCAL_APIC
                         smp_found_config = 1;
+#endif
                         mpf_found = mpf;
-#ifdef CONFIG_X86_32
+
                         printk(KERN_INFO "found SMP MP-table at [%p] %08lx\n",
                                mpf, virt_to_phys(mpf));
-                        reserve_bootmem(virt_to_phys(mpf), PAGE_SIZE,
+
+                        if (!reserve)
+                                return 1;
+                        reserve_bootmem_generic(virt_to_phys(mpf), PAGE_SIZE,
                                         BOOTMEM_DEFAULT);
                         if (mpf->mpf_physptr) {
+                                unsigned long size = PAGE_SIZE;
+#ifdef CONFIG_X86_32
                                 /*
                                  * We cannot access to MPC table to compute
                                  * table size yet, as only few megabytes from
@@ -717,24 +883,15 @@ static int __init smp_scan_config(unsigned long base, unsigned long length,
                                  * PAGE_SIZE from mpg->mpf_physptr yields BUG()
                                  * in reserve_bootmem.
                                  */
-                                unsigned long size = PAGE_SIZE;
                                 unsigned long end = max_low_pfn * PAGE_SIZE;
                                 if (mpf->mpf_physptr + size > end)
                                         size = end - mpf->mpf_physptr;
-                                reserve_bootmem(mpf->mpf_physptr, size,
+#endif
+                                reserve_bootmem_generic(mpf->mpf_physptr, size,
                                                 BOOTMEM_DEFAULT);
                         }
 
-#else
-                        if (!reserve)
-                                return 1;
-
-                        reserve_bootmem_generic(virt_to_phys(mpf), PAGE_SIZE);
-                        if (mpf->mpf_physptr)
-                                reserve_bootmem_generic(mpf->mpf_physptr,
-                                                        PAGE_SIZE);
-#endif
-                return 1;
+                        return 1;
                 }
                 bp += 4;
                 length -= 16;
@@ -742,10 +899,16 @@ static int __init smp_scan_config(unsigned long base, unsigned long length,
         return 0;
 }
 
-static void __init __find_smp_config(unsigned reserve)
+int (*mach_find_smp_config_quirk)(unsigned int reserve);
+
+static void __init __find_smp_config(unsigned int reserve)
 {
         unsigned int address;
 
+        if (mach_find_smp_config_quirk) {
+                if (mach_find_smp_config_quirk(reserve))
+                        return;
+        }
         /*
          * FIXME: Linux assumes you have 640K of base ram..
          * this continues the error...
@@ -790,298 +953,294 @@ void __init find_smp_config(void)
         __find_smp_config(1);
 }
 
-/* --------------------------------------------------------------------------
-                            ACPI-based MP Configuration
-   -------------------------------------------------------------------------- */
+#ifdef CONFIG_X86_IO_APIC
+static u8 __initdata irq_used[MAX_IRQ_SOURCES];
 
-/*
- * Keep this outside and initialized to 0, for !CONFIG_ACPI builds:
- */
-int es7000_plat;
+static int  __init get_MP_intsrc_index(struct mpc_config_intsrc *m)
+{
+        int i;
 
-#ifdef CONFIG_ACPI
+        if (m->mpc_irqtype != mp_INT)
+                return 0;
 
-#ifdef  CONFIG_X86_IO_APIC
+        if (m->mpc_irqflag != 0x0f)
+                return 0;
 
-#define MP_ISA_BUS              0
+        /* not legacy */
 
-extern struct mp_ioapic_routing mp_ioapic_routing[MAX_IO_APICS];
+        for (i = 0; i < mp_irq_entries; i++) {
+                if (mp_irqs[i].mp_irqtype != mp_INT)
+                        continue;
 
-static int mp_find_ioapic(int gsi)
-{
-        int i = 0;
+                if (mp_irqs[i].mp_irqflag != 0x0f)
+                        continue;
 
-        /* Find the IOAPIC that manages this GSI. */
-        for (i = 0; i < nr_ioapics; i++) {
-                if ((gsi >= mp_ioapic_routing[i].gsi_base)
-                    && (gsi <= mp_ioapic_routing[i].gsi_end))
-                        return i;
+                if (mp_irqs[i].mp_srcbus != m->mpc_srcbus)
+                        continue;
+                if (mp_irqs[i].mp_srcbusirq != m->mpc_srcbusirq)
+                        continue;
+                if (irq_used[i]) {
+                        /* already claimed */
+                        return -2;
+                }
+                irq_used[i] = 1;
+                return i;
         }
 
-        printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
+        /* not found */
         return -1;
 }
 
-static u8 __init uniq_ioapic_id(u8 id)
-{
-#ifdef CONFIG_X86_32
-        if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
-            !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
-                return io_apic_get_unique_id(nr_ioapics, id);
-        else
-                return id;
-#else
-        int i;
-        DECLARE_BITMAP(used, 256);
-        bitmap_zero(used, 256);
-        for (i = 0; i < nr_ioapics; i++) {
-                struct mpc_config_ioapic *ia = &mp_ioapics[i];
-                __set_bit(ia->mpc_apicid, used);
-        }
-        if (!test_bit(id, used))
-                return id;
-        return find_first_zero_bit(used, 256);
+#define SPARE_SLOT_NUM 20
+
+static struct mpc_config_intsrc __initdata *m_spare[SPARE_SLOT_NUM];
 #endif
-}
 
-void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
+static int  __init replace_intsrc_all(struct mp_config_table *mpc,
+                                        unsigned long mpc_new_phys,
+                                        unsigned long mpc_new_length)
 {
-        int idx = 0;
-
-        if (bad_ioapic(address))
-                return;
+#ifdef CONFIG_X86_IO_APIC
+        int i;
+        int nr_m_spare = 0;
+#endif
 
-        idx = nr_ioapics;
+        int count = sizeof(*mpc);
+        unsigned char *mpt = ((unsigned char *)mpc) + count;
 
-        mp_ioapics[idx].mpc_type = MP_IOAPIC;
-        mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
-        mp_ioapics[idx].mpc_apicaddr = address;
+        printk(KERN_INFO "mpc_length %x\n", mpc->mpc_length);
+        while (count < mpc->mpc_length) {
+                switch (*mpt) {
+                case MP_PROCESSOR:
+                        {
+                                struct mpc_config_processor *m =
+                                    (struct mpc_config_processor *)mpt;
+                                mpt += sizeof(*m);
+                                count += sizeof(*m);
+                                break;
+                        }
+                case MP_BUS:
+                        {
+                                struct mpc_config_bus *m =
+                                    (struct mpc_config_bus *)mpt;
+                                mpt += sizeof(*m);
+                                count += sizeof(*m);
+                                break;
+                        }
+                case MP_IOAPIC:
+                        {
+                                mpt += sizeof(struct mpc_config_ioapic);
+                                count += sizeof(struct mpc_config_ioapic);
+                                break;
+                        }
+                case MP_INTSRC:
+                        {
+#ifdef CONFIG_X86_IO_APIC
+                                struct mpc_config_intsrc *m =
+                                    (struct mpc_config_intsrc *)mpt;
 
-        set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
-        mp_ioapics[idx].mpc_apicid = uniq_ioapic_id(id);
-#ifdef CONFIG_X86_32
-        mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
-#else
-        mp_ioapics[idx].mpc_apicver = 0;
+                                printk(KERN_INFO "OLD ");
+                                print_MP_intsrc_info(m);
+                                i = get_MP_intsrc_index(m);
+                                if (i > 0) {
+                                        assign_to_mpc_intsrc(&mp_irqs[i], m);
+                                        printk(KERN_INFO "NEW ");
+                                        print_mp_irq_info(&mp_irqs[i]);
+                                } else if (!i) {
+                                        /* legacy, do nothing */
+                                } else if (nr_m_spare < SPARE_SLOT_NUM) {
+                                        /*
+                                         * not found (-1), or duplicated (-2)
+                                         * are invalid entries,
+                                         * we need to use the slot  later
+                                         */
+                                        m_spare[nr_m_spare] = m;
+                                        nr_m_spare++;
+                                }
 #endif
-        /*
-         * Build basic GSI lookup table to facilitate gsi->io_apic lookups
-         * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
-         */
-        mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
-        mp_ioapic_routing[idx].gsi_base = gsi_base;
-        mp_ioapic_routing[idx].gsi_end = gsi_base +
-            io_apic_get_redir_entries(idx);
-
-        printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
-               "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
-               mp_ioapics[idx].mpc_apicver, mp_ioapics[idx].mpc_apicaddr,
-               mp_ioapic_routing[idx].gsi_base, mp_ioapic_routing[idx].gsi_end);
-
-        nr_ioapics++;
-}
+                                mpt += sizeof(struct mpc_config_intsrc);
+                                count += sizeof(struct mpc_config_intsrc);
+                                break;
+                        }
+                case MP_LINTSRC:
+                        {
+                                struct mpc_config_lintsrc *m =
+                                    (struct mpc_config_lintsrc *)mpt;
+                                mpt += sizeof(*m);
+                                count += sizeof(*m);
+                                break;
+                        }
+                default:
+                        /* wrong mptable */
+                        printk(KERN_ERR "Your mptable is wrong, contact your HW vendor!\n");
+                        printk(KERN_ERR "type %x\n", *mpt);
+                        print_hex_dump(KERN_ERR, "  ", DUMP_PREFIX_ADDRESS, 16,
+                                        1, mpc, mpc->mpc_length, 1);
+                        goto out;
+                }
+        }
 
-void __init mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi)
-{
-        struct mpc_config_intsrc intsrc;
-        int ioapic = -1;
-        int pin = -1;
+#ifdef CONFIG_X86_IO_APIC
+        for (i = 0; i < mp_irq_entries; i++) {
+                if (irq_used[i])
+                        continue;
 
-        /*
-         * Convert 'gsi' to 'ioapic.pin'.
-         */
-        ioapic = mp_find_ioapic(gsi);
-        if (ioapic < 0)
-                return;
-        pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
+                if (mp_irqs[i].mp_irqtype != mp_INT)
+                        continue;
 
-        /*
-         * TBD: This check is for faulty timer entries, where the override
-         *      erroneously sets the trigger to level, resulting in a HUGE
-         *      increase of timer interrupts!
-         */
-        if ((bus_irq == 0) && (trigger == 3))
-                trigger = 1;
+                if (mp_irqs[i].mp_irqflag != 0x0f)
+                        continue;
 
-        intsrc.mpc_type = MP_INTSRC;
-        intsrc.mpc_irqtype = mp_INT;
-        intsrc.mpc_irqflag = (trigger << 2) | polarity;
-        intsrc.mpc_srcbus = MP_ISA_BUS;
-        intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
-        intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;     /* APIC ID */
-        intsrc.mpc_dstirq = pin;        /* INTIN# */
+                if (nr_m_spare > 0) {
+                        printk(KERN_INFO "*NEW* found ");
+                        nr_m_spare--;
+                        assign_to_mpc_intsrc(&mp_irqs[i], m_spare[nr_m_spare]);
+                        m_spare[nr_m_spare] = NULL;
+                } else {
+                        struct mpc_config_intsrc *m =
+                            (struct mpc_config_intsrc *)mpt;
+                        count += sizeof(struct mpc_config_intsrc);
+                        if (!mpc_new_phys) {
+                                printk(KERN_INFO "No spare slots, try to append...take your risk, new mpc_length %x\n", count);
+                        } else {
+                                if (count <= mpc_new_length)
+                                        printk(KERN_INFO "No spare slots, try to append..., new mpc_length %x\n", count);
+                                else {
+                                        printk(KERN_ERR "mpc_new_length %lx is too small\n", mpc_new_length);
+                                        goto out;
+                                }
+                        }
+                        assign_to_mpc_intsrc(&mp_irqs[i], m);
+                        mpc->mpc_length = count;
+                        mpt += sizeof(struct mpc_config_intsrc);
+                }
+                print_mp_irq_info(&mp_irqs[i]);
+        }
+#endif
+out:
+        /* update checksum */
+        mpc->mpc_checksum = 0;
+        mpc->mpc_checksum -= mpf_checksum((unsigned char *)mpc,
+                                           mpc->mpc_length);
 
-        MP_intsrc_info(&intsrc);
+        return 0;
 }
 
-void __init mp_config_acpi_legacy_irqs(void)
-{
-        struct mpc_config_intsrc intsrc;
-        int i = 0;
-        int ioapic = -1;
+static int __initdata enable_update_mptable;
 
-#if defined (CONFIG_MCA) || defined (CONFIG_EISA)
-        /*
-         * Fabricate the legacy ISA bus (bus #31).
-         */
-        mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA;
-#endif
-        set_bit(MP_ISA_BUS, mp_bus_not_pci);
-        Dprintk("Bus #%d is ISA\n", MP_ISA_BUS);
+static int __init update_mptable_setup(char *str)
+{
+        enable_update_mptable = 1;
+        return 0;
+}
+early_param("update_mptable", update_mptable_setup);
 
-        /*
-         * Older generations of ES7000 have no legacy identity mappings
-         */
-        if (es7000_plat == 1)
-                return;
+static unsigned long __initdata mpc_new_phys;
+static unsigned long mpc_new_length __initdata = 4096;
 
-        /*
-         * Locate the IOAPIC that manages the ISA IRQs (0-15).
-         */
-        ioapic = mp_find_ioapic(0);
-        if (ioapic < 0)
-                return;
+/* alloc_mptable or alloc_mptable=4k */
+static int __initdata alloc_mptable;
+static int __init parse_alloc_mptable_opt(char *p)
+{
+        enable_update_mptable = 1;
+        alloc_mptable = 1;
+        if (!p)
+                return 0;
+        mpc_new_length = memparse(p, &p);
+        return 0;
+}
+early_param("alloc_mptable", parse_alloc_mptable_opt);
 
-        intsrc.mpc_type = MP_INTSRC;
-        intsrc.mpc_irqflag = 0; /* Conforming */
-        intsrc.mpc_srcbus = MP_ISA_BUS;
-#ifdef CONFIG_X86_IO_APIC
-        intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
+void __init early_reserve_e820_mpc_new(void)
+{
+        if (enable_update_mptable && alloc_mptable) {
+                u64 startt = 0;
+#ifdef CONFIG_X86_TRAMPOLINE
+                startt = TRAMPOLINE_BASE;
 #endif
-        /*
-         * Use the default configuration for the IRQs 0-15.  Unless
-         * overridden by (MADT) interrupt source override entries.
-         */
-        for (i = 0; i < 16; i++) {
-                int idx;
-
-                for (idx = 0; idx < mp_irq_entries; idx++) {
-                        struct mpc_config_intsrc *irq = mp_irqs + idx;
-
-                        /* Do we already have a mapping for this ISA IRQ? */
-                        if (irq->mpc_srcbus == MP_ISA_BUS
-                            && irq->mpc_srcbusirq == i)
-                                break;
-
-                        /* Do we already have a mapping for this IOAPIC pin */
-                        if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
-                            (irq->mpc_dstirq == i))
-                                break;
-                }
-
-                if (idx != mp_irq_entries) {
-                        printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
-                        continue;       /* IRQ already used */
-                }
-
-                intsrc.mpc_irqtype = mp_INT;
-                intsrc.mpc_srcbusirq = i;       /* Identity mapped */
-                intsrc.mpc_dstirq = i;
-
-                MP_intsrc_info(&intsrc);
+                mpc_new_phys = early_reserve_e820(startt, mpc_new_length, 4);
         }
 }
 
-int mp_register_gsi(u32 gsi, int triggering, int polarity)
+static int __init update_mp_table(void)
 {
-        int ioapic;
-        int ioapic_pin;
-#ifdef CONFIG_X86_32
-#define MAX_GSI_NUM     4096
-#define IRQ_COMPRESSION_START   64
+        char str[16];
+        char oem[10];
+        struct intel_mp_floating *mpf;
+        struct mp_config_table *mpc;
+        struct mp_config_table *mpc_new;
+
+        if (!enable_update_mptable)
+                return 0;
+
+        mpf = mpf_found;
+        if (!mpf)
+                return 0;
 
-        static int pci_irq = IRQ_COMPRESSION_START;
         /*
-         * Mapping between Global System Interrupts, which
-         * represent all possible interrupts, and IRQs
-         * assigned to actual devices.
+         * Now see if we need to go further.
          */
-        static int gsi_to_irq[MAX_GSI_NUM];
-#else
-
-        if (acpi_irq_model != ACPI_IRQ_MODEL_IOAPIC)
-                return gsi;
-#endif
+        if (mpf->mpf_feature1 != 0)
+                return 0;
 
-        /* Don't set up the ACPI SCI because it's already set up */
-        if (acpi_gbl_FADT.sci_interrupt == gsi)
-                return gsi;
+        if (!mpf->mpf_physptr)
+                return 0;
 
-        ioapic = mp_find_ioapic(gsi);
-        if (ioapic < 0) {
-                printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
-                return gsi;
-        }
+        mpc = phys_to_virt(mpf->mpf_physptr);
 
-        ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
+        if (!smp_check_mpc(mpc, oem, str))
+                return 0;
 
-#ifdef CONFIG_X86_32
-        if (ioapic_renumber_irq)
-                gsi = ioapic_renumber_irq(ioapic, gsi);
-#endif
+        printk(KERN_INFO "mpf: %lx\n", virt_to_phys(mpf));
+        printk(KERN_INFO "mpf_physptr: %x\n", mpf->mpf_physptr);
 
-        /*
-         * Avoid pin reprogramming.  PRTs typically include entries
-         * with redundant pin->gsi mappings (but unique PCI devices);
-         * we only program the IOAPIC on the first.
-         */
-        if (ioapic_pin > MP_MAX_IOAPIC_PIN) {
-                printk(KERN_ERR "Invalid reference to IOAPIC pin "
-                       "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
-                       ioapic_pin);
-                return gsi;
+        if (mpc_new_phys && mpc->mpc_length > mpc_new_length) {
+                mpc_new_phys = 0;
+                printk(KERN_INFO "mpc_new_length is %ld, please use alloc_mptable=8k\n",
+                         mpc_new_length);
         }
-        if (test_bit(ioapic_pin, mp_ioapic_routing[ioapic].pin_programmed)) {
-                Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
-                        mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
-#ifdef CONFIG_X86_32
-                return (gsi < IRQ_COMPRESSION_START ? gsi : gsi_to_irq[gsi]);
-#else
-                return gsi;
-#endif
+
+        if (!mpc_new_phys) {
+                unsigned char old, new;
+                /* check if we can change the postion */
+                mpc->mpc_checksum = 0;
+                old = mpf_checksum((unsigned char *)mpc, mpc->mpc_length);
+                mpc->mpc_checksum = 0xff;
+                new = mpf_checksum((unsigned char *)mpc, mpc->mpc_length);
+                if (old == new) {
+                        printk(KERN_INFO "mpc is readonly, please try alloc_mptable instead\n");
+                        return 0;
+                }
+                printk(KERN_INFO "use in-positon replacing\n");
+        } else {
+                mpf->mpf_physptr = mpc_new_phys;
+                mpc_new = phys_to_virt(mpc_new_phys);
+                memcpy(mpc_new, mpc, mpc->mpc_length);
+                mpc = mpc_new;
+                /* check if we can modify that */
+                if (mpc_new_phys - mpf->mpf_physptr) {
+                        struct intel_mp_floating *mpf_new;
+                        /* steal 16 bytes from [0, 1k) */
+                        printk(KERN_INFO "mpf new: %x\n", 0x400 - 16);
+                        mpf_new = phys_to_virt(0x400 - 16);
+                        memcpy(mpf_new, mpf, 16);
+                        mpf = mpf_new;
+                        mpf->mpf_physptr = mpc_new_phys;
+                }
+                mpf->mpf_checksum = 0;
+                mpf->mpf_checksum -= mpf_checksum((unsigned char *)mpf, 16);
+                printk(KERN_INFO "mpf_physptr new: %x\n", mpf->mpf_physptr);
         }
 
-        set_bit(ioapic_pin, mp_ioapic_routing[ioapic].pin_programmed);
-#ifdef CONFIG_X86_32
         /*
-         * For GSI >= 64, use IRQ compression
+         * only replace the one with mp_INT and
+         *       MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
+         * already in mp_irqs , stored by ... and mp_config_acpi_gsi,
+         * may need pci=routeirq for all coverage
          */
-        if ((gsi >= IRQ_COMPRESSION_START)
-            && (triggering == ACPI_LEVEL_SENSITIVE)) {
-                /*
-                 * For PCI devices assign IRQs in order, avoiding gaps
-                 * due to unused I/O APIC pins.
-                 */
-                int irq = gsi;
-                if (gsi < MAX_GSI_NUM) {
-                        /*
-                         * Retain the VIA chipset work-around (gsi > 15), but
-                         * avoid a problem where the 8254 timer (IRQ0) is setup
-                         * via an override (so it's not on pin 0 of the ioapic),
-                         * and at the same time, the pin 0 interrupt is a PCI
-                         * type.  The gsi > 15 test could cause these two pins
-                         * to be shared as IRQ0, and they are not shareable.
-                         * So test for this condition, and if necessary, avoid
-                         * the pin collision.
-                         */
-                        gsi = pci_irq++;
-                        /*
-                         * Don't assign IRQ used by ACPI SCI
-                         */
-                        if (gsi == acpi_gbl_FADT.sci_interrupt)
-                                gsi = pci_irq++;
-                        gsi_to_irq[irq] = gsi;
-                } else {
-                        printk(KERN_ERR "GSI %u is too high\n", gsi);
-                        return gsi;
-                }
-        }
-#endif
-        io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
-                                triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
-                                polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
-        return gsi;
+        replace_intsrc_all(mpc, mpc_new_phys, mpc_new_length);
+
+        return 0;
 }
 
-#endif /* CONFIG_X86_IO_APIC */
-#endif /* CONFIG_ACPI */
+late_initcall(update_mp_table);
diff --git a/arch/x86/kernel/msr.c b/arch/x86/kernel/msr.c
index 1f3abe048e93..a153b3905f60 100644
--- a/arch/x86/kernel/msr.c
+++ b/arch/x86/kernel/msr.c
@@ -117,12 +117,20 @@ static int msr_open(struct inode *inode, struct file *file)
 {
         unsigned int cpu = iminor(file->f_path.dentry->d_inode);
         struct cpuinfo_x86 *c = &cpu_data(cpu);
+        int ret = 0;
 
-        if (cpu >= NR_CPUS || !cpu_online(cpu))
-                return -ENXIO;  /* No such CPU */
-        if (!cpu_has(c, X86_FEATURE_MSR))
-                return -EIO;    /* MSR not supported */
+        lock_kernel();
+        cpu = iminor(file->f_path.dentry->d_inode);
 
+        if (cpu >= NR_CPUS || !cpu_online(cpu)) {
+                ret = -ENXIO;   /* No such CPU */
+                goto out;
+        }
+        c = &cpu_data(cpu);
+        if (!cpu_has(c, X86_FEATURE_MSR))
+                ret = -EIO;     /* MSR not supported */
+out:
+        unlock_kernel();
         return 0;
 }
 
diff --git a/arch/x86/kernel/nmi_32.c b/arch/x86/kernel/nmi.c
index 84160f74eeb0..716b89284be0 100644
--- a/arch/x86/kernel/nmi_32.c
+++ b/arch/x86/kernel/nmi.c
@@ -11,10 +11,13 @@
  *  Mikael Pettersson   : PM converted to driver model. Disable/enable API.
  */
 
+#include <asm/apic.h>
+
+#include <linux/nmi.h>
+#include <linux/mm.h>
 #include <linux/delay.h>
 #include <linux/interrupt.h>
 #include <linux/module.h>
-#include <linux/nmi.h>
 #include <linux/sysdev.h>
 #include <linux/sysctl.h>
 #include <linux/percpu.h>
@@ -22,12 +25,18 @@
 #include <linux/cpumask.h>
 #include <linux/kernel_stat.h>
 #include <linux/kdebug.h>
-#include <linux/slab.h>
+#include <linux/smp.h>
 
+#include <asm/i8259.h>
+#include <asm/io_apic.h>
 #include <asm/smp.h>
 #include <asm/nmi.h>
+#include <asm/proto.h>
+#include <asm/timer.h>
 
-#include "mach_traps.h"
+#include <asm/mce.h>
+
+#include <mach_traps.h>
 
 int unknown_nmi_panic;
 int nmi_watchdog_enabled;
@@ -41,28 +50,65 @@ static cpumask_t backtrace_mask = CPU_MASK_NONE;
  *  0: the lapic NMI watchdog is disabled, but can be enabled
  */
 atomic_t nmi_active = ATOMIC_INIT(0);           /* oprofile uses this */
+EXPORT_SYMBOL(nmi_active);
 
-unsigned int nmi_watchdog = NMI_DEFAULT;
-static unsigned int nmi_hz = HZ;
+unsigned int nmi_watchdog = NMI_NONE;
+EXPORT_SYMBOL(nmi_watchdog);
 
+static int panic_on_timeout;
+
+static unsigned int nmi_hz = HZ;
 static DEFINE_PER_CPU(short, wd_enabled);
+static int endflag __initdata;
 
-static int endflag __initdata = 0;
+static inline unsigned int get_nmi_count(int cpu)
+{
+#ifdef CONFIG_X86_64
+        return cpu_pda(cpu)->__nmi_count;
+#else
+        return nmi_count(cpu);
+#endif
+}
+
+static inline int mce_in_progress(void)
+{
+#if defined(CONFIG_X86_64) && defined(CONFIG_X86_MCE)
+        return atomic_read(&mce_entry) > 0;
+#endif
+        return 0;
+}
+
+/*
+ * Take the local apic timer and PIT/HPET into account. We don't
+ * know which one is active, when we have highres/dyntick on
+ */
+static inline unsigned int get_timer_irqs(int cpu)
+{
+#ifdef CONFIG_X86_64
+        return read_pda(apic_timer_irqs) + read_pda(irq0_irqs);
+#else
+        return per_cpu(irq_stat, cpu).apic_timer_irqs +
+                per_cpu(irq_stat, cpu).irq0_irqs;
+#endif
+}
 
 #ifdef CONFIG_SMP
-/* The performance counters used by NMI_LOCAL_APIC don't trigger when
+/*
+ * The performance counters used by NMI_LOCAL_APIC don't trigger when
  * the CPU is idle. To make sure the NMI watchdog really ticks on all
  * CPUs during the test make them busy.
  */
 static __init void nmi_cpu_busy(void *data)
 {
         local_irq_enable_in_hardirq();
-        /* Intentionally don't use cpu_relax here. This is
-           to make sure that the performance counter really ticks,
-           even if there is a simulator or similar that catches the
-           pause instruction. On a real HT machine this is fine because
-           all other CPUs are busy with "useless" delay loops and don't
-           care if they get somewhat less cycles. */
+        /*
+         * Intentionally don't use cpu_relax here. This is
+         * to make sure that the performance counter really ticks,
+         * even if there is a simulator or similar that catches the
+         * pause instruction. On a real HT machine this is fine because
+         * all other CPUs are busy with "useless" delay loops and don't
+         * care if they get somewhat less cycles.
+         */
         while (endflag == 0)
                 mb();
 }
@@ -73,15 +119,12 @@ int __init check_nmi_watchdog(void)
         unsigned int *prev_nmi_count;
         int cpu;
 
-        if ((nmi_watchdog == NMI_NONE) || (nmi_watchdog == NMI_DISABLED))
-                return 0;
-
-        if (!atomic_read(&nmi_active))
+        if (!nmi_watchdog_active() || !atomic_read(&nmi_active))
                 return 0;
 
-        prev_nmi_count = kmalloc(NR_CPUS * sizeof(int), GFP_KERNEL);
+        prev_nmi_count = kmalloc(nr_cpu_ids * sizeof(int), GFP_KERNEL);
         if (!prev_nmi_count)
-                return -1;
+                goto error;
 
         printk(KERN_INFO "Testing NMI watchdog ... ");
 
@@ -91,25 +134,19 @@ int __init check_nmi_watchdog(void)
 #endif
 
         for_each_possible_cpu(cpu)
-                prev_nmi_count[cpu] = nmi_count(cpu);
+                prev_nmi_count[cpu] = get_nmi_count(cpu);
         local_irq_enable();
-        mdelay((20*1000)/nmi_hz); // wait 20 ticks
+        mdelay((20 * 1000) / nmi_hz); /* wait 20 ticks */
 
-        for_each_possible_cpu(cpu) {
-#ifdef CONFIG_SMP
-                /* Check cpu_callin_map here because that is set
-                   after the timer is started. */
-                if (!cpu_isset(cpu, cpu_callin_map))
-                        continue;
-#endif
+        for_each_online_cpu(cpu) {
                 if (!per_cpu(wd_enabled, cpu))
                         continue;
-                if (nmi_count(cpu) - prev_nmi_count[cpu] <= 5) {
+                if (get_nmi_count(cpu) - prev_nmi_count[cpu] <= 5) {
                         printk(KERN_WARNING "WARNING: CPU#%d: NMI "
                                 "appears to be stuck (%d->%d)!\n",
                                 cpu,
                                 prev_nmi_count[cpu],
-                                nmi_count(cpu));
+                                get_nmi_count(cpu));
                         per_cpu(wd_enabled, cpu) = 0;
                         atomic_dec(&nmi_active);
                 }
@@ -118,37 +155,53 @@ int __init check_nmi_watchdog(void)
         if (!atomic_read(&nmi_active)) {
                 kfree(prev_nmi_count);
                 atomic_set(&nmi_active, -1);
-                return -1;
+                goto error;
         }
         printk("OK.\n");
 
-        /* now that we know it works we can reduce NMI frequency to
-           something more reasonable; makes a difference in some configs */
+        /*
+         * now that we know it works we can reduce NMI frequency to
+         * something more reasonable; makes a difference in some configs
+         */
         if (nmi_watchdog == NMI_LOCAL_APIC)
                 nmi_hz = lapic_adjust_nmi_hz(1);
 
         kfree(prev_nmi_count);
         return 0;
+error:
+        if (nmi_watchdog == NMI_IO_APIC && !timer_through_8259)
+                disable_8259A_irq(0);
+#ifdef CONFIG_X86_32
+        timer_ack = 0;
+#endif
+        return -1;
 }
 
 static int __init setup_nmi_watchdog(char *str)
 {
-        int nmi;
+        unsigned int nmi;
+
+        if (!strncmp(str, "panic", 5)) {
+                panic_on_timeout = 1;
+                str = strchr(str, ',');
+                if (!str)
+                        return 1;
+                ++str;
+        }
 
         get_option(&str, &nmi);
 
-        if ((nmi >= NMI_INVALID) || (nmi < NMI_NONE))
+        if (nmi >= NMI_INVALID)
                 return 0;
 
         nmi_watchdog = nmi;
         return 1;
 }
-
 __setup("nmi_watchdog=", setup_nmi_watchdog);
 
-
-/* Suspend/resume support */
-
+/*
+ * Suspend/resume support
+ */
 #ifdef CONFIG_PM
 
 static int nmi_pm_active; /* nmi_active before suspend */
@@ -172,7 +225,6 @@ static int lapic_nmi_resume(struct sys_device *dev)
         return 0;
 }
 
-
 static struct sysdev_class nmi_sysclass = {
         .name           = "lapic_nmi",
         .resume         = lapic_nmi_resume,
@@ -188,7 +240,8 @@ static int __init init_lapic_nmi_sysfs(void)
 {
         int error;
 
-        /* should really be a BUG_ON but b/c this is an
+        /*
+         * should really be a BUG_ON but b/c this is an
          * init call, it just doesn't work.  -dcz
          */
         if (nmi_watchdog != NMI_LOCAL_APIC)
@@ -202,6 +255,7 @@ static int __init init_lapic_nmi_sysfs(void)
                 error = sysdev_register(&device_lapic_nmi);
         return error;
 }
+
 /* must come after the local APIC's device_initcall() */
 late_initcall(init_lapic_nmi_sysfs);
 
@@ -223,7 +277,7 @@ void acpi_nmi_enable(void)
 
 static void __acpi_nmi_disable(void *__unused)
 {
-        apic_write(APIC_LVT0, APIC_DM_NMI | APIC_LVT_MASKED);
+        apic_write_around(APIC_LVT0, APIC_DM_NMI | APIC_LVT_MASKED);
 }
 
 /*
@@ -242,12 +296,13 @@ void setup_apic_nmi_watchdog(void *unused)
 
         /* cheap hack to support suspend/resume */
         /* if cpu0 is not active neither should the other cpus */
-        if ((smp_processor_id() != 0) && (atomic_read(&nmi_active) <= 0))
+        if (smp_processor_id() != 0 && atomic_read(&nmi_active) <= 0)
                 return;
 
         switch (nmi_watchdog) {
         case NMI_LOCAL_APIC:
-                __get_cpu_var(wd_enabled) = 1; /* enable it before to avoid race with handler */
+                 /* enable it before to avoid race with handler */
+                __get_cpu_var(wd_enabled) = 1;
                 if (lapic_watchdog_init(nmi_hz) < 0) {
                         __get_cpu_var(wd_enabled) = 0;
                         return;
@@ -262,9 +317,8 @@ void setup_apic_nmi_watchdog(void *unused)
 void stop_apic_nmi_watchdog(void *unused)
 {
         /* only support LOCAL and IO APICs for now */
-        if ((nmi_watchdog != NMI_LOCAL_APIC) &&
-            (nmi_watchdog != NMI_IO_APIC))
-                return;
+        if (!nmi_watchdog_active())
+                return;
         if (__get_cpu_var(wd_enabled) == 0)
                 return;
         if (nmi_watchdog == NMI_LOCAL_APIC)
@@ -284,26 +338,26 @@ void stop_apic_nmi_watchdog(void *unused)
  * since NMIs don't listen to _any_ locks, we have to be extremely
  * careful not to rely on unsafe variables. The printk might lock
  * up though, so we have to break up any console locks first ...
- * [when there will be more tty-related locks, break them up
- *  here too!]
+ * [when there will be more tty-related locks, break them up here too!]
  */
 
-static unsigned int
-        last_irq_sums [NR_CPUS],
-        alert_counter [NR_CPUS];
+static DEFINE_PER_CPU(unsigned, last_irq_sum);
+static DEFINE_PER_CPU(local_t, alert_counter);
+static DEFINE_PER_CPU(int, nmi_touch);
 
 void touch_nmi_watchdog(void)
 {
-        if (nmi_watchdog > 0) {
+        if (nmi_watchdog_active()) {
                 unsigned cpu;
 
                 /*
-                 * Just reset the alert counters, (other CPUs might be
-                 * spinning on locks we hold):
+                 * Tell other CPUs to reset their alert counters. We cannot
+                 * do it ourselves because the alert count increase is not
+                 * atomic.
                  */
                 for_each_present_cpu(cpu) {
-                        if (alert_counter[cpu])
-                                alert_counter[cpu] = 0;
+                        if (per_cpu(nmi_touch, cpu) != 1)
+                                per_cpu(nmi_touch, cpu) = 1;
                 }
         }
 
@@ -314,12 +368,9 @@ void touch_nmi_watchdog(void)
 }
 EXPORT_SYMBOL(touch_nmi_watchdog);
 
-extern void die_nmi(struct pt_regs *, const char *msg);
-
 notrace __kprobes int
 nmi_watchdog_tick(struct pt_regs *regs, unsigned reason)
 {
-
         /*
          * Since current_thread_info()-> is always on the stack, and we
          * always switch the stack NMI-atomically, it's safe to use
@@ -337,39 +388,45 @@ nmi_watchdog_tick(struct pt_regs *regs, unsigned reason)
                 touched = 1;
         }
 
+        sum = get_timer_irqs(cpu);
+
+        if (__get_cpu_var(nmi_touch)) {
+                __get_cpu_var(nmi_touch) = 0;
+                touched = 1;
+        }
+
         if (cpu_isset(cpu, backtrace_mask)) {
                 static DEFINE_SPINLOCK(lock);   /* Serialise the printks */
 
                 spin_lock(&lock);
-                printk("NMI backtrace for cpu %d\n", cpu);
+                printk(KERN_WARNING "NMI backtrace for cpu %d\n", cpu);
                 dump_stack();
                 spin_unlock(&lock);
                 cpu_clear(cpu, backtrace_mask);
         }
 
-        /*
-         * Take the local apic timer and PIT/HPET into account. We don't
-         * know which one is active, when we have highres/dyntick on
-         */
-        sum = per_cpu(irq_stat, cpu).apic_timer_irqs +
-                per_cpu(irq_stat, cpu).irq0_irqs;
+        /* Could check oops_in_progress here too, but it's safer not to */
+        if (mce_in_progress())
+                touched = 1;
 
         /* if the none of the timers isn't firing, this cpu isn't doing much */
-        if (!touched && last_irq_sums[cpu] == sum) {
+        if (!touched && __get_cpu_var(last_irq_sum) == sum) {
                 /*
                  * Ayiee, looks like this CPU is stuck ...
                  * wait a few IRQs (5 seconds) before doing the oops ...
                  */
-                alert_counter[cpu]++;
-                if (alert_counter[cpu] == 5*nmi_hz)
+                local_inc(&__get_cpu_var(alert_counter));
+                if (local_read(&__get_cpu_var(alert_counter)) == 5 * nmi_hz)
                         /*
                          * die_nmi will return ONLY if NOTIFY_STOP happens..
                          */
-                        die_nmi(regs, "BUG: NMI Watchdog detected LOCKUP");
+                        die_nmi("BUG: NMI Watchdog detected LOCKUP",
+                                regs, panic_on_timeout);
         } else {
-                last_irq_sums[cpu] = sum;
-                alert_counter[cpu] = 0;
+                __get_cpu_var(last_irq_sum) = sum;
+                local_set(&__get_cpu_var(alert_counter), 0);
         }
+
         /* see if the nmi watchdog went off */
         if (!__get_cpu_var(wd_enabled))
                 return rc;
@@ -378,7 +435,8 @@ nmi_watchdog_tick(struct pt_regs *regs, unsigned reason)
                 rc |= lapic_wd_event(nmi_hz);
                 break;
         case NMI_IO_APIC:
-                /* don't know how to accurately check for this.
+                /*
+                 * don't know how to accurately check for this.
                  * just assume it was a watchdog timer interrupt
                  * This matches the old behaviour.
                  */
@@ -396,7 +454,7 @@ static int unknown_nmi_panic_callback(struct pt_regs *regs, int cpu)
         char buf[64];
 
         sprintf(buf, "NMI received for unknown reason %02x\n", reason);
-        die_nmi(regs, buf);
+        die_nmi(buf, regs, 1); /* Always panic here */
         return 0;
 }
 
@@ -414,32 +472,26 @@ int proc_nmi_enabled(struct ctl_table *table, int write, struct file *file,
         if (!!old_state == !!nmi_watchdog_enabled)
                 return 0;
 
-        if (atomic_read(&nmi_active) < 0 || nmi_watchdog == NMI_DISABLED) {
-                printk( KERN_WARNING "NMI watchdog is permanently disabled\n");
+        if (atomic_read(&nmi_active) < 0 || !nmi_watchdog_active()) {
+                printk(KERN_WARNING
+                        "NMI watchdog is permanently disabled\n");
                 return -EIO;
         }
 
-        if (nmi_watchdog == NMI_DEFAULT) {
-                if (lapic_watchdog_ok())
-                        nmi_watchdog = NMI_LOCAL_APIC;
-                else
-                        nmi_watchdog = NMI_IO_APIC;
-        }
-
         if (nmi_watchdog == NMI_LOCAL_APIC) {
                 if (nmi_watchdog_enabled)
                         enable_lapic_nmi_watchdog();
                 else
                         disable_lapic_nmi_watchdog();
         } else {
-                printk( KERN_WARNING
+                printk(KERN_WARNING
                         "NMI watchdog doesn't know what hardware to touch\n");
                 return -EIO;
         }
         return 0;
 }
 
-#endif
+#endif /* CONFIG_SYSCTL */
 
 int do_nmi_callback(struct pt_regs *regs, int cpu)
 {
@@ -462,6 +514,3 @@ void __trigger_all_cpu_backtrace(void)
                 mdelay(1);
         }
 }
-
-EXPORT_SYMBOL(nmi_active);
-EXPORT_SYMBOL(nmi_watchdog);
diff --git a/arch/x86/kernel/nmi_64.c b/arch/x86/kernel/nmi_64.c
deleted file mode 100644
index 5a29ded994fa..000000000000
--- a/arch/x86/kernel/nmi_64.c
+++ /dev/null
@@ -1,482 +0,0 @@
-/*
- *  NMI watchdog support on APIC systems
- *
- *  Started by Ingo Molnar <mingo@redhat.com>
- *
- *  Fixes:
- *  Mikael Pettersson   : AMD K7 support for local APIC NMI watchdog.
- *  Mikael Pettersson   : Power Management for local APIC NMI watchdog.
- *  Pavel Machek and
- *  Mikael Pettersson   : PM converted to driver model. Disable/enable API.
- */
-
-#include <linux/nmi.h>
-#include <linux/mm.h>
-#include <linux/delay.h>
-#include <linux/interrupt.h>
-#include <linux/module.h>
-#include <linux/sysdev.h>
-#include <linux/sysctl.h>
-#include <linux/kprobes.h>
-#include <linux/cpumask.h>
-#include <linux/kdebug.h>
-
-#include <asm/smp.h>
-#include <asm/nmi.h>
-#include <asm/proto.h>
-#include <asm/mce.h>
-
-#include <mach_traps.h>
-
-int unknown_nmi_panic;
-int nmi_watchdog_enabled;
-int panic_on_unrecovered_nmi;
-
-static cpumask_t backtrace_mask = CPU_MASK_NONE;
-
-/* nmi_active:
- * >0: the lapic NMI watchdog is active, but can be disabled
- * <0: the lapic NMI watchdog has not been set up, and cannot
- *     be enabled
- *  0: the lapic NMI watchdog is disabled, but can be enabled
- */
-atomic_t nmi_active = ATOMIC_INIT(0);           /* oprofile uses this */
-static int panic_on_timeout;
-
-unsigned int nmi_watchdog = NMI_DEFAULT;
-static unsigned int nmi_hz = HZ;
-
-static DEFINE_PER_CPU(short, wd_enabled);
-
-/* Run after command line and cpu_init init, but before all other checks */
-void nmi_watchdog_default(void)
-{
-        if (nmi_watchdog != NMI_DEFAULT)
-                return;
-        nmi_watchdog = NMI_NONE;
-}
-
-static int endflag __initdata = 0;
-
-#ifdef CONFIG_SMP
-/* The performance counters used by NMI_LOCAL_APIC don't trigger when
- * the CPU is idle. To make sure the NMI watchdog really ticks on all
- * CPUs during the test make them busy.
- */
-static __init void nmi_cpu_busy(void *data)
-{
-        local_irq_enable_in_hardirq();
-        /* Intentionally don't use cpu_relax here. This is
-           to make sure that the performance counter really ticks,
-           even if there is a simulator or similar that catches the
-           pause instruction. On a real HT machine this is fine because
-           all other CPUs are busy with "useless" delay loops and don't
-           care if they get somewhat less cycles. */
-        while (endflag == 0)
-                mb();
-}
-#endif
-
-int __init check_nmi_watchdog(void)
-{
-        int *prev_nmi_count;
-        int cpu;
-
-        if ((nmi_watchdog == NMI_NONE) || (nmi_watchdog == NMI_DISABLED))
-                return 0;
-
-        if (!atomic_read(&nmi_active))
-                return 0;
-
-        prev_nmi_count = kmalloc(NR_CPUS * sizeof(int), GFP_KERNEL);
-        if (!prev_nmi_count)
-                return -1;
-
-        printk(KERN_INFO "Testing NMI watchdog ... ");
-
-#ifdef CONFIG_SMP
-        if (nmi_watchdog == NMI_LOCAL_APIC)
-                smp_call_function(nmi_cpu_busy, (void *)&endflag, 0, 0);
-#endif
-
-        for (cpu = 0; cpu < NR_CPUS; cpu++)
-                prev_nmi_count[cpu] = cpu_pda(cpu)->__nmi_count;
-        local_irq_enable();
-        mdelay((20*1000)/nmi_hz); // wait 20 ticks
-
-        for_each_online_cpu(cpu) {
-                if (!per_cpu(wd_enabled, cpu))
-                        continue;
-                if (cpu_pda(cpu)->__nmi_count - prev_nmi_count[cpu] <= 5) {
-                        printk(KERN_WARNING "WARNING: CPU#%d: NMI "
-                               "appears to be stuck (%d->%d)!\n",
-                                cpu,
-                                prev_nmi_count[cpu],
-                                cpu_pda(cpu)->__nmi_count);
-                        per_cpu(wd_enabled, cpu) = 0;
-                        atomic_dec(&nmi_active);
-                }
-        }
-        endflag = 1;
-        if (!atomic_read(&nmi_active)) {
-                kfree(prev_nmi_count);
-                atomic_set(&nmi_active, -1);
-                return -1;
-        }
-        printk("OK.\n");
-
-        /* now that we know it works we can reduce NMI frequency to
-           something more reasonable; makes a difference in some configs */
-        if (nmi_watchdog == NMI_LOCAL_APIC)
-                nmi_hz = lapic_adjust_nmi_hz(1);
-
-        kfree(prev_nmi_count);
-        return 0;
-}
-
-static int __init setup_nmi_watchdog(char *str)
-{
-        int nmi;
-
-        if (!strncmp(str,"panic",5)) {
-                panic_on_timeout = 1;
-                str = strchr(str, ',');
-                if (!str)
-                        return 1;
-                ++str;
-        }
-
-        get_option(&str, &nmi);
-
-        if ((nmi >= NMI_INVALID) || (nmi < NMI_NONE))
-                return 0;
-
-        nmi_watchdog = nmi;
-        return 1;
-}
-
-__setup("nmi_watchdog=", setup_nmi_watchdog);
-
-#ifdef CONFIG_PM
-
-static int nmi_pm_active; /* nmi_active before suspend */
-
-static int lapic_nmi_suspend(struct sys_device *dev, pm_message_t state)
-{
-        /* only CPU0 goes here, other CPUs should be offline */
-        nmi_pm_active = atomic_read(&nmi_active);
-        stop_apic_nmi_watchdog(NULL);
-        BUG_ON(atomic_read(&nmi_active) != 0);
-        return 0;
-}
-
-static int lapic_nmi_resume(struct sys_device *dev)
-{
-        /* only CPU0 goes here, other CPUs should be offline */
-        if (nmi_pm_active > 0) {
-                setup_apic_nmi_watchdog(NULL);
-                touch_nmi_watchdog();
-        }
-        return 0;
-}
-
-static struct sysdev_class nmi_sysclass = {
-        .name           = "lapic_nmi",
-        .resume         = lapic_nmi_resume,
-        .suspend        = lapic_nmi_suspend,
-};
-
-static struct sys_device device_lapic_nmi = {
-        .id     = 0,
-        .cls    = &nmi_sysclass,
-};
-
-static int __init init_lapic_nmi_sysfs(void)
-{
-        int error;
-
-        /* should really be a BUG_ON but b/c this is an
-         * init call, it just doesn't work.  -dcz
-         */
-        if (nmi_watchdog != NMI_LOCAL_APIC)
-                return 0;
-
-        if (atomic_read(&nmi_active) < 0)
-                return 0;
-
-        error = sysdev_class_register(&nmi_sysclass);
-        if (!error)
-                error = sysdev_register(&device_lapic_nmi);
-        return error;
-}
-/* must come after the local APIC's device_initcall() */
-late_initcall(init_lapic_nmi_sysfs);
-
-#endif  /* CONFIG_PM */
-
-static void __acpi_nmi_enable(void *__unused)
-{
-        apic_write(APIC_LVT0, APIC_DM_NMI);
-}
-
-/*
- * Enable timer based NMIs on all CPUs:
- */
-void acpi_nmi_enable(void)
-{
-        if (atomic_read(&nmi_active) && nmi_watchdog == NMI_IO_APIC)
-                on_each_cpu(__acpi_nmi_enable, NULL, 0, 1);
-}
-
-static void __acpi_nmi_disable(void *__unused)
-{
-        apic_write(APIC_LVT0, APIC_DM_NMI | APIC_LVT_MASKED);
-}
-
-/*
- * Disable timer based NMIs on all CPUs:
- */
-void acpi_nmi_disable(void)
-{
-        if (atomic_read(&nmi_active) && nmi_watchdog == NMI_IO_APIC)
-                on_each_cpu(__acpi_nmi_disable, NULL, 0, 1);
-}
-
-void setup_apic_nmi_watchdog(void *unused)
-{
-        if (__get_cpu_var(wd_enabled))
-                return;
-
-        /* cheap hack to support suspend/resume */
-        /* if cpu0 is not active neither should the other cpus */
-        if ((smp_processor_id() != 0) && (atomic_read(&nmi_active) <= 0))
-                return;
-
-        switch (nmi_watchdog) {
-        case NMI_LOCAL_APIC:
-                __get_cpu_var(wd_enabled) = 1;
-                if (lapic_watchdog_init(nmi_hz) < 0) {
-                        __get_cpu_var(wd_enabled) = 0;
-                        return;
-                }
-                /* FALL THROUGH */
-        case NMI_IO_APIC:
-                __get_cpu_var(wd_enabled) = 1;
-                atomic_inc(&nmi_active);
-        }
-}
-
-void stop_apic_nmi_watchdog(void *unused)
-{
-        /* only support LOCAL and IO APICs for now */
-        if ((nmi_watchdog != NMI_LOCAL_APIC) &&
-            (nmi_watchdog != NMI_IO_APIC))
-                return;
-        if (__get_cpu_var(wd_enabled) == 0)
-                return;
-        if (nmi_watchdog == NMI_LOCAL_APIC)
-                lapic_watchdog_stop();
-        __get_cpu_var(wd_enabled) = 0;
-        atomic_dec(&nmi_active);
-}
-
-/*
- * the best way to detect whether a CPU has a 'hard lockup' problem
- * is to check it's local APIC timer IRQ counts. If they are not
- * changing then that CPU has some problem.
- *
- * as these watchdog NMI IRQs are generated on every CPU, we only
- * have to check the current processor.
- */
-
-static DEFINE_PER_CPU(unsigned, last_irq_sum);
-static DEFINE_PER_CPU(local_t, alert_counter);
-static DEFINE_PER_CPU(int, nmi_touch);
-
-void touch_nmi_watchdog(void)
-{
-        if (nmi_watchdog > 0) {
-                unsigned cpu;
-
-                /*
-                 * Tell other CPUs to reset their alert counters. We cannot
-                 * do it ourselves because the alert count increase is not
-                 * atomic.
-                 */
-                for_each_present_cpu(cpu) {
-                        if (per_cpu(nmi_touch, cpu) != 1)
-                                per_cpu(nmi_touch, cpu) = 1;
-                }
-        }
-
-        touch_softlockup_watchdog();
-}
-EXPORT_SYMBOL(touch_nmi_watchdog);
-
-notrace __kprobes int
-nmi_watchdog_tick(struct pt_regs *regs, unsigned reason)
-{
-        int sum;
-        int touched = 0;
-        int cpu = smp_processor_id();
-        int rc = 0;
-
-        /* check for other users first */
-        if (notify_die(DIE_NMI, "nmi", regs, reason, 2, SIGINT)
-                        == NOTIFY_STOP) {
-                rc = 1;
-                touched = 1;
-        }
-
-        sum = read_pda(apic_timer_irqs) + read_pda(irq0_irqs);
-        if (__get_cpu_var(nmi_touch)) {
-                __get_cpu_var(nmi_touch) = 0;
-                touched = 1;
-        }
-
-        if (cpu_isset(cpu, backtrace_mask)) {
-                static DEFINE_SPINLOCK(lock);   /* Serialise the printks */
-
-                spin_lock(&lock);
-                printk("NMI backtrace for cpu %d\n", cpu);
-                dump_stack();
-                spin_unlock(&lock);
-                cpu_clear(cpu, backtrace_mask);
-        }
-
-#ifdef CONFIG_X86_MCE
-        /* Could check oops_in_progress here too, but it's safer
-           not too */
-        if (atomic_read(&mce_entry) > 0)
-                touched = 1;
-#endif
-        /* if the apic timer isn't firing, this cpu isn't doing much */
-        if (!touched && __get_cpu_var(last_irq_sum) == sum) {
-                /*
-                 * Ayiee, looks like this CPU is stuck ...
-                 * wait a few IRQs (5 seconds) before doing the oops ...
-                 */
-                local_inc(&__get_cpu_var(alert_counter));
-                if (local_read(&__get_cpu_var(alert_counter)) == 5*nmi_hz)
-                        die_nmi("NMI Watchdog detected LOCKUP on CPU %d\n", regs,
-                                panic_on_timeout);
-        } else {
-                __get_cpu_var(last_irq_sum) = sum;
-                local_set(&__get_cpu_var(alert_counter), 0);
-        }
-
-        /* see if the nmi watchdog went off */
-        if (!__get_cpu_var(wd_enabled))
-                return rc;
-        switch (nmi_watchdog) {
-        case NMI_LOCAL_APIC:
-                rc |= lapic_wd_event(nmi_hz);
-                break;
-        case NMI_IO_APIC:
-                /* don't know how to accurately check for this.
-                 * just assume it was a watchdog timer interrupt
-                 * This matches the old behaviour.
-                 */
-                rc = 1;
-                break;
-        }
-        return rc;
-}
-
-static unsigned ignore_nmis;
-
-asmlinkage notrace __kprobes void
-do_nmi(struct pt_regs *regs, long error_code)
-{
-        nmi_enter();
-        add_pda(__nmi_count,1);
-        if (!ignore_nmis)
-                default_do_nmi(regs);
-        nmi_exit();
-}
-
-void stop_nmi(void)
-{
-        acpi_nmi_disable();
-        ignore_nmis++;
-}
-
-void restart_nmi(void)
-{
-        ignore_nmis--;
-        acpi_nmi_enable();
-}
-
-#ifdef CONFIG_SYSCTL
-
-static int unknown_nmi_panic_callback(struct pt_regs *regs, int cpu)
-{
-        unsigned char reason = get_nmi_reason();
-        char buf[64];
-
-        sprintf(buf, "NMI received for unknown reason %02x\n", reason);
-        die_nmi(buf, regs, 1);  /* Always panic here */
-        return 0;
-}
-
-/*
- * proc handler for /proc/sys/kernel/nmi
- */
-int proc_nmi_enabled(struct ctl_table *table, int write, struct file *file,
-                        void __user *buffer, size_t *length, loff_t *ppos)
-{
-        int old_state;
-
-        nmi_watchdog_enabled = (atomic_read(&nmi_active) > 0) ? 1 : 0;
-        old_state = nmi_watchdog_enabled;
-        proc_dointvec(table, write, file, buffer, length, ppos);
-        if (!!old_state == !!nmi_watchdog_enabled)
-                return 0;
-
-        if (atomic_read(&nmi_active) < 0 || nmi_watchdog == NMI_DISABLED) {
-                printk( KERN_WARNING "NMI watchdog is permanently disabled\n");
-                return -EIO;
-        }
-
-        /* if nmi_watchdog is not set yet, then set it */
-        nmi_watchdog_default();
-
-        if (nmi_watchdog == NMI_LOCAL_APIC) {
-                if (nmi_watchdog_enabled)
-                        enable_lapic_nmi_watchdog();
-                else
-                        disable_lapic_nmi_watchdog();
-        } else {
-                printk( KERN_WARNING
-                        "NMI watchdog doesn't know what hardware to touch\n");
-                return -EIO;
-        }
-        return 0;
-}
-
-#endif
-
-int do_nmi_callback(struct pt_regs *regs, int cpu)
-{
-#ifdef CONFIG_SYSCTL
-        if (unknown_nmi_panic)
-                return unknown_nmi_panic_callback(regs, cpu);
-#endif
-        return 0;
-}
-
-void __trigger_all_cpu_backtrace(void)
-{
-        int i;
-
-        backtrace_mask = cpu_online_map;
-        /* Wait for up to 10 seconds for all CPUs to do the backtrace */
-        for (i = 0; i < 10 * 1000; i++) {
-                if (cpus_empty(backtrace_mask))
-                        break;
-                mdelay(1);
-        }
-}
-
-EXPORT_SYMBOL(nmi_active);
-EXPORT_SYMBOL(nmi_watchdog);
diff --git a/arch/x86/kernel/numaq_32.c b/arch/x86/kernel/numaq_32.c
index e65281b1634b..5b20a5e7ac28 100644
--- a/arch/x86/kernel/numaq_32.c
+++ b/arch/x86/kernel/numaq_32.c
@@ -31,6 +31,8 @@
 #include <asm/numaq.h>
 #include <asm/topology.h>
 #include <asm/processor.h>
+#include <asm/mpspec.h>
+#include <asm/e820.h>
 
 #define MB_TO_PAGES(addr) ((addr) << (20 - PAGE_SHIFT))
 
@@ -58,6 +60,8 @@ static void __init smp_dump_qct(void)
                         node_end_pfn[node] = MB_TO_PAGES(
                                 eq->hi_shrd_mem_start + eq->hi_shrd_mem_size);
 
+                        e820_register_active_regions(node, node_start_pfn[node],
+                                                        node_end_pfn[node]);
                         memory_present(node,
                                 node_start_pfn[node], node_end_pfn[node]);
                         node_remap_size[node] = node_memmap_size_bytes(node,
@@ -67,23 +71,35 @@ static void __init smp_dump_qct(void)
         }
 }
 
-/*
- * Unlike Summit, we don't really care to let the NUMA-Q
- * fall back to flat mode.  Don't compile for NUMA-Q
- * unless you really need it!
- */
+static __init void early_check_numaq(void)
+{
+        /*
+         * Find possible boot-time SMP configuration:
+         */
+        early_find_smp_config();
+        /*
+         * get boot-time SMP configuration:
+         */
+        if (smp_found_config)
+                early_get_smp_config();
+}
+
 int __init get_memcfg_numaq(void)
 {
+        early_check_numaq();
+        if (!found_numaq)
+                return 0;
         smp_dump_qct();
         return 1;
 }
 
-static int __init numaq_tsc_disable(void)
+void __init numaq_tsc_disable(void)
 {
+        if (!found_numaq)
+                return -1;
+
         if (num_online_nodes() > 1) {
                 printk(KERN_DEBUG "NUMAQ: disabling TSC\n");
                 setup_clear_cpu_cap(X86_FEATURE_TSC);
         }
-        return 0;
 }
-arch_initcall(numaq_tsc_disable);
diff --git a/arch/x86/kernel/paravirt.c b/arch/x86/kernel/paravirt.c
index 74f0c5ea2a03..e0f571d58c19 100644
--- a/arch/x86/kernel/paravirt.c
+++ b/arch/x86/kernel/paravirt.c
@@ -30,6 +30,7 @@
 #include <asm/setup.h>
 #include <asm/arch_hooks.h>
 #include <asm/time.h>
+#include <asm/pgalloc.h>
 #include <asm/irq.h>
 #include <asm/delay.h>
 #include <asm/fixmap.h>
@@ -139,7 +140,9 @@ unsigned paravirt_patch_default(u8 type, u16 clobbers, void *insnbuf,
                 /* If the operation is a nop, then nop the callsite */
                 ret = paravirt_patch_nop();
         else if (type == PARAVIRT_PATCH(pv_cpu_ops.iret) ||
-                 type == PARAVIRT_PATCH(pv_cpu_ops.irq_enable_syscall_ret))
+                 type == PARAVIRT_PATCH(pv_cpu_ops.irq_enable_sysexit) ||
+                 type == PARAVIRT_PATCH(pv_cpu_ops.usergs_sysret32) ||
+                 type == PARAVIRT_PATCH(pv_cpu_ops.usergs_sysret64))
                 /* If operation requires a jmp, then jmp */
                 ret = paravirt_patch_jmp(insnbuf, opfunc, addr, len);
         else
@@ -190,7 +193,9 @@ static void native_flush_tlb_single(unsigned long addr)
 
 /* These are in entry.S */
 extern void native_iret(void);
-extern void native_irq_enable_syscall_ret(void);
+extern void native_irq_enable_sysexit(void);
+extern void native_usergs_sysret32(void);
+extern void native_usergs_sysret64(void);
 
 static int __init print_banner(void)
 {
@@ -280,7 +285,7 @@ struct pv_time_ops pv_time_ops = {
         .get_wallclock = native_get_wallclock,
         .set_wallclock = native_set_wallclock,
         .sched_clock = native_sched_clock,
-        .get_cpu_khz = native_calculate_cpu_khz,
+        .get_tsc_khz = native_calibrate_tsc,
 };
 
 struct pv_irq_ops pv_irq_ops = {
@@ -291,6 +296,9 @@ struct pv_irq_ops pv_irq_ops = {
         .irq_enable = native_irq_enable,
         .safe_halt = native_safe_halt,
         .halt = native_halt,
+#ifdef CONFIG_X86_64
+        .adjust_exception_frame = paravirt_nop,
+#endif
 };
 
 struct pv_cpu_ops pv_cpu_ops = {
@@ -321,12 +329,23 @@ struct pv_cpu_ops pv_cpu_ops = {
         .store_idt = native_store_idt,
         .store_tr = native_store_tr,
         .load_tls = native_load_tls,
+#ifdef CONFIG_X86_64
+        .load_gs_index = native_load_gs_index,
+#endif
         .write_ldt_entry = native_write_ldt_entry,
         .write_gdt_entry = native_write_gdt_entry,
         .write_idt_entry = native_write_idt_entry,
         .load_sp0 = native_load_sp0,
 
-        .irq_enable_syscall_ret = native_irq_enable_syscall_ret,
+#if defined(CONFIG_X86_32) || defined(CONFIG_IA32_EMULATION)
+        .irq_enable_sysexit = native_irq_enable_sysexit,
+#endif
+#ifdef CONFIG_X86_64
+#ifdef CONFIG_IA32_EMULATION
+        .usergs_sysret32 = native_usergs_sysret32,
+#endif
+        .usergs_sysret64 = native_usergs_sysret64,
+#endif
         .iret = native_iret,
         .swapgs = native_swapgs,
 
@@ -366,6 +385,9 @@ struct pv_mmu_ops pv_mmu_ops = {
         .flush_tlb_single = native_flush_tlb_single,
         .flush_tlb_others = native_flush_tlb_others,
 
+        .pgd_alloc = __paravirt_pgd_alloc,
+        .pgd_free = paravirt_nop,
+
         .alloc_pte = paravirt_nop,
         .alloc_pmd = paravirt_nop,
         .alloc_pmd_clone = paravirt_nop,
@@ -380,6 +402,9 @@ struct pv_mmu_ops pv_mmu_ops = {
         .pte_update = paravirt_nop,
         .pte_update_defer = paravirt_nop,
 
+        .ptep_modify_prot_start = __ptep_modify_prot_start,
+        .ptep_modify_prot_commit = __ptep_modify_prot_commit,
+
 #ifdef CONFIG_HIGHPTE
         .kmap_atomic_pte = kmap_atomic,
 #endif
@@ -403,6 +428,7 @@ struct pv_mmu_ops pv_mmu_ops = {
 #endif /* PAGETABLE_LEVELS >= 3 */
 
         .pte_val = native_pte_val,
+        .pte_flags = native_pte_val,
         .pgd_val = native_pgd_val,
 
         .make_pte = native_make_pte,
@@ -416,6 +442,8 @@ struct pv_mmu_ops pv_mmu_ops = {
                 .enter = paravirt_nop,
                 .leave = paravirt_nop,
         },
+
+        .set_fixmap = native_set_fixmap,
 };
 
 EXPORT_SYMBOL_GPL(pv_time_ops);
diff --git a/arch/x86/kernel/paravirt_patch_32.c b/arch/x86/kernel/paravirt_patch_32.c
index 82fc5fcab4f4..58262218781b 100644
--- a/arch/x86/kernel/paravirt_patch_32.c
+++ b/arch/x86/kernel/paravirt_patch_32.c
@@ -5,7 +5,7 @@ DEF_NATIVE(pv_irq_ops, irq_enable, "sti");
 DEF_NATIVE(pv_irq_ops, restore_fl, "push %eax; popf");
 DEF_NATIVE(pv_irq_ops, save_fl, "pushf; pop %eax");
 DEF_NATIVE(pv_cpu_ops, iret, "iret");
-DEF_NATIVE(pv_cpu_ops, irq_enable_syscall_ret, "sti; sysexit");
+DEF_NATIVE(pv_cpu_ops, irq_enable_sysexit, "sti; sysexit");
 DEF_NATIVE(pv_mmu_ops, read_cr2, "mov %cr2, %eax");
 DEF_NATIVE(pv_mmu_ops, write_cr3, "mov %eax, %cr3");
 DEF_NATIVE(pv_mmu_ops, read_cr3, "mov %cr3, %eax");
@@ -29,7 +29,7 @@ unsigned native_patch(u8 type, u16 clobbers, void *ibuf,
                 PATCH_SITE(pv_irq_ops, restore_fl);
                 PATCH_SITE(pv_irq_ops, save_fl);
                 PATCH_SITE(pv_cpu_ops, iret);
-                PATCH_SITE(pv_cpu_ops, irq_enable_syscall_ret);
+                PATCH_SITE(pv_cpu_ops, irq_enable_sysexit);
                 PATCH_SITE(pv_mmu_ops, read_cr2);
                 PATCH_SITE(pv_mmu_ops, read_cr3);
                 PATCH_SITE(pv_mmu_ops, write_cr3);
diff --git a/arch/x86/kernel/paravirt_patch_64.c b/arch/x86/kernel/paravirt_patch_64.c
index 7d904e138d7e..061d01df9ae6 100644
--- a/arch/x86/kernel/paravirt_patch_64.c
+++ b/arch/x86/kernel/paravirt_patch_64.c
@@ -14,8 +14,9 @@ DEF_NATIVE(pv_mmu_ops, flush_tlb_single, "invlpg (%rdi)");
 DEF_NATIVE(pv_cpu_ops, clts, "clts");
 DEF_NATIVE(pv_cpu_ops, wbinvd, "wbinvd");
 
-/* the three commands give us more control to how to return from a syscall */
-DEF_NATIVE(pv_cpu_ops, irq_enable_syscall_ret, "movq %gs:" __stringify(pda_oldrsp) ", %rsp; swapgs; sysretq;");
+DEF_NATIVE(pv_cpu_ops, irq_enable_sysexit, "swapgs; sti; sysexit");
+DEF_NATIVE(pv_cpu_ops, usergs_sysret64, "swapgs; sysretq");
+DEF_NATIVE(pv_cpu_ops, usergs_sysret32, "swapgs; sysretl");
 DEF_NATIVE(pv_cpu_ops, swapgs, "swapgs");
 
 unsigned native_patch(u8 type, u16 clobbers, void *ibuf,
@@ -35,7 +36,9 @@ unsigned native_patch(u8 type, u16 clobbers, void *ibuf,
                 PATCH_SITE(pv_irq_ops, irq_enable);
                 PATCH_SITE(pv_irq_ops, irq_disable);
                 PATCH_SITE(pv_cpu_ops, iret);
-                PATCH_SITE(pv_cpu_ops, irq_enable_syscall_ret);
+                PATCH_SITE(pv_cpu_ops, irq_enable_sysexit);
+                PATCH_SITE(pv_cpu_ops, usergs_sysret32);
+                PATCH_SITE(pv_cpu_ops, usergs_sysret64);
                 PATCH_SITE(pv_cpu_ops, swapgs);
                 PATCH_SITE(pv_mmu_ops, read_cr2);
                 PATCH_SITE(pv_mmu_ops, read_cr3);
diff --git a/arch/x86/kernel/pci-calgary_64.c b/arch/x86/kernel/pci-calgary_64.c
index e28ec497e142..6959b5c45df4 100644
--- a/arch/x86/kernel/pci-calgary_64.c
+++ b/arch/x86/kernel/pci-calgary_64.c
@@ -1394,7 +1394,7 @@ void __init detect_calgary(void)
                 return;
         }
 
-        specified_table_size = determine_tce_table_size(end_pfn * PAGE_SIZE);
+        specified_table_size = determine_tce_table_size(max_pfn * PAGE_SIZE);
 
         for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
                 struct calgary_bus_info *info = &bus_info[bus];
@@ -1459,7 +1459,7 @@ int __init calgary_iommu_init(void)
         if (ret) {
                 printk(KERN_ERR "PCI-DMA: Calgary init failed %d, "
                        "falling back to no_iommu\n", ret);
-                if (end_pfn > MAX_DMA32_PFN)
+                if (max_pfn > MAX_DMA32_PFN)
                         printk(KERN_ERR "WARNING more than 4GB of memory, "
                                         "32bit PCI may malfunction.\n");
                 return ret;
diff --git a/arch/x86/kernel/pci-dma.c b/arch/x86/kernel/pci-dma.c
index dc00a1331ace..8467ec2320f1 100644
--- a/arch/x86/kernel/pci-dma.c
+++ b/arch/x86/kernel/pci-dma.c
@@ -7,6 +7,7 @@
 #include <asm/dma.h>
 #include <asm/gart.h>
 #include <asm/calgary.h>
+#include <asm/amd_iommu.h>
 
 int forbid_dac __read_mostly;
 EXPORT_SYMBOL(forbid_dac);
@@ -74,13 +75,17 @@ early_param("dma32_size", parse_dma32_size_opt);
 void __init dma32_reserve_bootmem(void)
 {
         unsigned long size, align;
-        if (end_pfn <= MAX_DMA32_PFN)
+        if (max_pfn <= MAX_DMA32_PFN)
                 return;
 
+        /*
+         * check aperture_64.c allocate_aperture() for reason about
+         * using 512M as goal
+         */
         align = 64ULL<<20;
         size = round_up(dma32_bootmem_size, align);
         dma32_bootmem_ptr = __alloc_bootmem_nopanic(size, align,
-                                 __pa(MAX_DMA_ADDRESS));
+                                 512ULL<<20);
         if (dma32_bootmem_ptr)
                 dma32_bootmem_size = size;
         else
@@ -88,17 +93,14 @@ void __init dma32_reserve_bootmem(void)
 }
 static void __init dma32_free_bootmem(void)
 {
-        int node;
 
-        if (end_pfn <= MAX_DMA32_PFN)
+        if (max_pfn <= MAX_DMA32_PFN)
                 return;
 
         if (!dma32_bootmem_ptr)
                 return;
 
-        for_each_online_node(node)
-                free_bootmem_node(NODE_DATA(node), __pa(dma32_bootmem_ptr),
-                                  dma32_bootmem_size);
+        free_bootmem(__pa(dma32_bootmem_ptr), dma32_bootmem_size);
 
         dma32_bootmem_ptr = NULL;
         dma32_bootmem_size = 0;
@@ -122,6 +124,8 @@ void __init pci_iommu_alloc(void)
 
         detect_intel_iommu();
 
+        amd_iommu_detect();
+
 #ifdef CONFIG_SWIOTLB
         pci_swiotlb_init();
 #endif
@@ -357,7 +361,7 @@ int dma_supported(struct device *dev, u64 mask)
 EXPORT_SYMBOL(dma_supported);
 
 /* Allocate DMA memory on node near device */
-noinline struct page *
+static noinline struct page *
 dma_alloc_pages(struct device *dev, gfp_t gfp, unsigned order)
 {
         int node;
@@ -502,6 +506,8 @@ static int __init pci_iommu_init(void)
 
         intel_iommu_init();
 
+        amd_iommu_init();
+
 #ifdef CONFIG_GART_IOMMU
         gart_iommu_init();
 #endif
diff --git a/arch/x86/kernel/pci-gart_64.c b/arch/x86/kernel/pci-gart_64.c
index aa8ec928caa8..c3fe78406d18 100644
--- a/arch/x86/kernel/pci-gart_64.c
+++ b/arch/x86/kernel/pci-gart_64.c
@@ -104,7 +104,6 @@ static unsigned long alloc_iommu(struct device *dev, int size)
                                           size, base_index, boundary_size, 0);
         }
         if (offset != -1) {
-                set_bit_string(iommu_gart_bitmap, offset, size);
                 next_bit = offset+size;
                 if (next_bit >= iommu_pages) {
                         next_bit = 0;
@@ -534,8 +533,8 @@ static __init unsigned read_aperture(struct pci_dev *dev, u32 *size)
         unsigned aper_size = 0, aper_base_32, aper_order;
         u64 aper_base;
 
-        pci_read_config_dword(dev, 0x94, &aper_base_32);
-        pci_read_config_dword(dev, 0x90, &aper_order);
+        pci_read_config_dword(dev, AMD64_GARTAPERTUREBASE, &aper_base_32);
+        pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &aper_order);
         aper_order = (aper_order >> 1) & 7;
 
         aper_base = aper_base_32 & 0x7fff;
@@ -549,14 +548,63 @@ static __init unsigned read_aperture(struct pci_dev *dev, u32 *size)
         return aper_base;
 }
 
+static void enable_gart_translations(void)
+{
+        int i;
+
+        for (i = 0; i < num_k8_northbridges; i++) {
+                struct pci_dev *dev = k8_northbridges[i];
+
+                enable_gart_translation(dev, __pa(agp_gatt_table));
+        }
+}
+
+/*
+ * If fix_up_north_bridges is set, the north bridges have to be fixed up on
+ * resume in the same way as they are handled in gart_iommu_hole_init().
+ */
+static bool fix_up_north_bridges;
+static u32 aperture_order;
+static u32 aperture_alloc;
+
+void set_up_gart_resume(u32 aper_order, u32 aper_alloc)
+{
+        fix_up_north_bridges = true;
+        aperture_order = aper_order;
+        aperture_alloc = aper_alloc;
+}
+
 static int gart_resume(struct sys_device *dev)
 {
+        printk(KERN_INFO "PCI-DMA: Resuming GART IOMMU\n");
+
+        if (fix_up_north_bridges) {
+                int i;
+
+                printk(KERN_INFO "PCI-DMA: Restoring GART aperture settings\n");
+
+                for (i = 0; i < num_k8_northbridges; i++) {
+                        struct pci_dev *dev = k8_northbridges[i];
+
+                        /*
+                         * Don't enable translations just yet.  That is the next
+                         * step.  Restore the pre-suspend aperture settings.
+                         */
+                        pci_write_config_dword(dev, AMD64_GARTAPERTURECTL,
+                                                aperture_order << 1);
+                        pci_write_config_dword(dev, AMD64_GARTAPERTUREBASE,
+                                                aperture_alloc >> 25);
+                }
+        }
+
+        enable_gart_translations();
+
         return 0;
 }
 
 static int gart_suspend(struct sys_device *dev, pm_message_t state)
 {
-        return -EINVAL;
+        return 0;
 }
 
 static struct sysdev_class gart_sysdev_class = {
@@ -582,6 +630,7 @@ static __init int init_k8_gatt(struct agp_kern_info *info)
         struct pci_dev *dev;
         void *gatt;
         int i, error;
+        unsigned long start_pfn, end_pfn;
 
         printk(KERN_INFO "PCI-DMA: Disabling AGP.\n");
         aper_size = aper_base = info->aper_size = 0;
@@ -614,31 +663,25 @@ static __init int init_k8_gatt(struct agp_kern_info *info)
         memset(gatt, 0, gatt_size);
         agp_gatt_table = gatt;
 
-        for (i = 0; i < num_k8_northbridges; i++) {
-                u32 gatt_reg;
-                u32 ctl;
-
-                dev = k8_northbridges[i];
-                gatt_reg = __pa(gatt) >> 12;
-                gatt_reg <<= 4;
-                pci_write_config_dword(dev, 0x98, gatt_reg);
-                pci_read_config_dword(dev, 0x90, &ctl);
-
-                ctl |= 1;
-                ctl &= ~((1<<4) | (1<<5));
-
-                pci_write_config_dword(dev, 0x90, ctl);
-        }
+        enable_gart_translations();
 
         error = sysdev_class_register(&gart_sysdev_class);
         if (!error)
                 error = sysdev_register(&device_gart);
         if (error)
                 panic("Could not register gart_sysdev -- would corrupt data on next suspend");
+
         flush_gart();
 
         printk(KERN_INFO "PCI-DMA: aperture base @ %x size %u KB\n",
                aper_base, aper_size>>10);
+
+        /* need to map that range */
+        end_pfn = (aper_base>>PAGE_SHIFT) + (aper_size>>PAGE_SHIFT);
+        if (end_pfn > max_low_pfn_mapped) {
+                start_pfn = (aper_base>>PAGE_SHIFT);
+                init_memory_mapping(start_pfn<<PAGE_SHIFT, end_pfn<<PAGE_SHIFT);
+        }
         return 0;
 
  nommu:
@@ -677,11 +720,11 @@ void gart_iommu_shutdown(void)
                 u32 ctl;
 
                 dev = k8_northbridges[i];
-                pci_read_config_dword(dev, 0x90, &ctl);
+                pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl);
 
-                ctl &= ~1;
+                ctl &= ~GARTEN;
 
-                pci_write_config_dword(dev, 0x90, ctl);
+                pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);
         }
 }
 
@@ -716,10 +759,10 @@ void __init gart_iommu_init(void)
                 return;
 
         if (no_iommu ||
-            (!force_iommu && end_pfn <= MAX_DMA32_PFN) ||
+            (!force_iommu && max_pfn <= MAX_DMA32_PFN) ||
             !gart_iommu_aperture ||
             (no_agp && init_k8_gatt(&info) < 0)) {
-                if (end_pfn > MAX_DMA32_PFN) {
+                if (max_pfn > MAX_DMA32_PFN) {
                         printk(KERN_WARNING "More than 4GB of memory "
                                           "but GART IOMMU not available.\n"
                                KERN_WARNING "falling back to iommu=soft.\n");
@@ -788,10 +831,10 @@ void __init gart_iommu_init(void)
         wbinvd();
 
         /*
-         * Try to workaround a bug (thanks to BenH)
+         * Try to workaround a bug (thanks to BenH):
          * Set unmapped entries to a scratch page instead of 0.
          * Any prefetches that hit unmapped entries won't get an bus abort
-         * then.
+         * then. (P2P bridge may be prefetching on DMA reads).
          */
         scratch = get_zeroed_page(GFP_KERNEL);
         if (!scratch)
diff --git a/arch/x86/kernel/pci-swiotlb_64.c b/arch/x86/kernel/pci-swiotlb_64.c
index 490da7f4b8d0..82299cd1d04d 100644
--- a/arch/x86/kernel/pci-swiotlb_64.c
+++ b/arch/x86/kernel/pci-swiotlb_64.c
@@ -38,7 +38,7 @@ const struct dma_mapping_ops swiotlb_dma_ops = {
 void __init pci_swiotlb_init(void)
 {
         /* don't initialize swiotlb if iommu=off (no_iommu=1) */
-        if (!iommu_detected && !no_iommu && end_pfn > MAX_DMA32_PFN)
+        if (!iommu_detected && !no_iommu && max_pfn > MAX_DMA32_PFN)
                swiotlb = 1;
         if (swiotlb_force)
                 swiotlb = 1;
diff --git a/arch/x86/kernel/probe_roms_32.c b/arch/x86/kernel/probe_roms_32.c
new file mode 100644
index 000000000000..675a48c404a5
--- /dev/null
+++ b/arch/x86/kernel/probe_roms_32.c
@@ -0,0 +1,166 @@
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/uaccess.h>
+#include <linux/mmzone.h>
+#include <linux/ioport.h>
+#include <linux/seq_file.h>
+#include <linux/console.h>
+#include <linux/init.h>
+#include <linux/edd.h>
+#include <linux/dmi.h>
+#include <linux/pfn.h>
+#include <linux/pci.h>
+#include <asm/pci-direct.h>
+
+
+#include <asm/e820.h>
+#include <asm/mmzone.h>
+#include <asm/setup.h>
+#include <asm/sections.h>
+#include <asm/io.h>
+#include <setup_arch.h>
+
+static struct resource system_rom_resource = {
+        .name   = "System ROM",
+        .start  = 0xf0000,
+        .end    = 0xfffff,
+        .flags  = IORESOURCE_BUSY | IORESOURCE_READONLY | IORESOURCE_MEM
+};
+
+static struct resource extension_rom_resource = {
+        .name   = "Extension ROM",
+        .start  = 0xe0000,
+        .end    = 0xeffff,
+        .flags  = IORESOURCE_BUSY | IORESOURCE_READONLY | IORESOURCE_MEM
+};
+
+static struct resource adapter_rom_resources[] = { {
+        .name   = "Adapter ROM",
+        .start  = 0xc8000,
+        .end    = 0,
+        .flags  = IORESOURCE_BUSY | IORESOURCE_READONLY | IORESOURCE_MEM
+}, {
+        .name   = "Adapter ROM",
+        .start  = 0,
+        .end    = 0,
+        .flags  = IORESOURCE_BUSY | IORESOURCE_READONLY | IORESOURCE_MEM
+}, {
+        .name   = "Adapter ROM",
+        .start  = 0,
+        .end    = 0,
+        .flags  = IORESOURCE_BUSY | IORESOURCE_READONLY | IORESOURCE_MEM
+}, {
+        .name   = "Adapter ROM",
+        .start  = 0,
+        .end    = 0,
+        .flags  = IORESOURCE_BUSY | IORESOURCE_READONLY | IORESOURCE_MEM
+}, {
+        .name   = "Adapter ROM",
+        .start  = 0,
+        .end    = 0,
+        .flags  = IORESOURCE_BUSY | IORESOURCE_READONLY | IORESOURCE_MEM
+}, {
+        .name   = "Adapter ROM",
+        .start  = 0,
+        .end    = 0,
+        .flags  = IORESOURCE_BUSY | IORESOURCE_READONLY | IORESOURCE_MEM
+} };
+
+static struct resource video_rom_resource = {
+        .name   = "Video ROM",
+        .start  = 0xc0000,
+        .end    = 0xc7fff,
+        .flags  = IORESOURCE_BUSY | IORESOURCE_READONLY | IORESOURCE_MEM
+};
+
+#define ROMSIGNATURE 0xaa55
+
+static int __init romsignature(const unsigned char *rom)
+{
+        const unsigned short * const ptr = (const unsigned short *)rom;
+        unsigned short sig;
+
+        return probe_kernel_address(ptr, sig) == 0 && sig == ROMSIGNATURE;
+}
+
+static int __init romchecksum(const unsigned char *rom, unsigned long length)
+{
+        unsigned char sum, c;
+
+        for (sum = 0; length && probe_kernel_address(rom++, c) == 0; length--)
+                sum += c;
+        return !length && !sum;
+}
+
+void __init probe_roms(void)
+{
+        const unsigned char *rom;
+        unsigned long start, length, upper;
+        unsigned char c;
+        int i;
+
+        /* video rom */
+        upper = adapter_rom_resources[0].start;
+        for (start = video_rom_resource.start; start < upper; start += 2048) {
+                rom = isa_bus_to_virt(start);
+                if (!romsignature(rom))
+                        continue;
+
+                video_rom_resource.start = start;
+
+                if (probe_kernel_address(rom + 2, c) != 0)
+                        continue;
+
+                /* 0 < length <= 0x7f * 512, historically */
+                length = c * 512;
+
+                /* if checksum okay, trust length byte */
+                if (length && romchecksum(rom, length))
+                        video_rom_resource.end = start + length - 1;
+
+                request_resource(&iomem_resource, &video_rom_resource);
+                break;
+        }
+
+        start = (video_rom_resource.end + 1 + 2047) & ~2047UL;
+        if (start < upper)
+                start = upper;
+
+        /* system rom */
+        request_resource(&iomem_resource, &system_rom_resource);
+        upper = system_rom_resource.start;
+
+        /* check for extension rom (ignore length byte!) */
+        rom = isa_bus_to_virt(extension_rom_resource.start);
+        if (romsignature(rom)) {
+                length = extension_rom_resource.end - extension_rom_resource.start + 1;
+                if (romchecksum(rom, length)) {
+                        request_resource(&iomem_resource, &extension_rom_resource);
+                        upper = extension_rom_resource.start;
+                }
+        }
+
+        /* check for adapter roms on 2k boundaries */
+        for (i = 0; i < ARRAY_SIZE(adapter_rom_resources) && start < upper; start += 2048) {
+                rom = isa_bus_to_virt(start);
+                if (!romsignature(rom))
+                        continue;
+
+                if (probe_kernel_address(rom + 2, c) != 0)
+                        continue;
+
+                /* 0 < length <= 0x7f * 512, historically */
+                length = c * 512;
+
+                /* but accept any length that fits if checksum okay */
+                if (!length || start + length > upper || !romchecksum(rom, length))
+                        continue;
+
+                adapter_rom_resources[i].start = start;
+                adapter_rom_resources[i].end = start + length - 1;
+                request_resource(&iomem_resource, &adapter_rom_resources[i]);
+
+                start = adapter_rom_resources[i++].end & ~2047UL;
+        }
+}
+
diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
index ba370dc8685b..4061d63aabe7 100644
--- a/arch/x86/kernel/process.c
+++ b/arch/x86/kernel/process.c
@@ -6,6 +6,7 @@
 #include <linux/sched.h>
 #include <linux/module.h>
 #include <linux/pm.h>
+#include <linux/clockchips.h>
 
 struct kmem_cache *task_xstate_cachep;
 
@@ -45,6 +46,76 @@ void arch_task_cache_init(void)
                                   SLAB_PANIC, NULL);
 }
 
+/*
+ * Idle related variables and functions
+ */
+unsigned long boot_option_idle_override = 0;
+EXPORT_SYMBOL(boot_option_idle_override);
+
+/*
+ * Powermanagement idle function, if any..
+ */
+void (*pm_idle)(void);
+EXPORT_SYMBOL(pm_idle);
+
+#ifdef CONFIG_X86_32
+/*
+ * This halt magic was a workaround for ancient floppy DMA
+ * wreckage. It should be safe to remove.
+ */
+static int hlt_counter;
+void disable_hlt(void)
+{
+        hlt_counter++;
+}
+EXPORT_SYMBOL(disable_hlt);
+
+void enable_hlt(void)
+{
+        hlt_counter--;
+}
+EXPORT_SYMBOL(enable_hlt);
+
+static inline int hlt_use_halt(void)
+{
+        return (!hlt_counter && boot_cpu_data.hlt_works_ok);
+}
+#else
+static inline int hlt_use_halt(void)
+{
+        return 1;
+}
+#endif
+
+/*
+ * We use this if we don't have any better
+ * idle routine..
+ */
+void default_idle(void)
+{
+        if (hlt_use_halt()) {
+                current_thread_info()->status &= ~TS_POLLING;
+                /*
+                 * TS_POLLING-cleared state must be visible before we
+                 * test NEED_RESCHED:
+                 */
+                smp_mb();
+
+                if (!need_resched())
+                        safe_halt();    /* enables interrupts racelessly */
+                else
+                        local_irq_enable();
+                current_thread_info()->status |= TS_POLLING;
+        } else {
+                local_irq_enable();
+                /* loop is done by the caller */
+                cpu_relax();
+        }
+}
+#ifdef CONFIG_APM_MODULE
+EXPORT_SYMBOL(default_idle);
+#endif
+
 static void do_nothing(void *unused)
 {
 }
@@ -122,44 +193,129 @@ static void poll_idle(void)
  *
  * idle=mwait overrides this decision and forces the usage of mwait.
  */
+
+#define MWAIT_INFO                      0x05
+#define MWAIT_ECX_EXTENDED_INFO         0x01
+#define MWAIT_EDX_C1                    0xf0
+
 static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c)
 {
+        u32 eax, ebx, ecx, edx;
+
         if (force_mwait)
                 return 1;
 
-        if (c->x86_vendor == X86_VENDOR_AMD) {
-                switch(c->x86) {
-                case 0x10:
-                case 0x11:
-                        return 0;
-                }
-        }
+        if (c->cpuid_level < MWAIT_INFO)
+                return 0;
+
+        cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx);
+        /* Check, whether EDX has extended info about MWAIT */
+        if (!(ecx & MWAIT_ECX_EXTENDED_INFO))
+                return 1;
+
+        /*
+         * edx enumeratios MONITOR/MWAIT extensions. Check, whether
+         * C1  supports MWAIT
+         */
+        return (edx & MWAIT_EDX_C1);
+}
+
+/*
+ * Check for AMD CPUs, which have potentially C1E support
+ */
+static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c)
+{
+        if (c->x86_vendor != X86_VENDOR_AMD)
+                return 0;
+
+        if (c->x86 < 0x0F)
+                return 0;
+
+        /* Family 0x0f models < rev F do not have C1E */
+        if (c->x86 == 0x0f && c->x86_model < 0x40)
+                return 0;
+
         return 1;
 }
 
-void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
+/*
+ * C1E aware idle routine. We check for C1E active in the interrupt
+ * pending message MSR. If we detect C1E, then we handle it the same
+ * way as C3 power states (local apic timer and TSC stop)
+ */
+static void c1e_idle(void)
 {
-        static int selected;
+        static cpumask_t c1e_mask = CPU_MASK_NONE;
+        static int c1e_detected;
 
-        if (selected)
+        if (need_resched())
                 return;
+
+        if (!c1e_detected) {
+                u32 lo, hi;
+
+                rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
+                if (lo & K8_INTP_C1E_ACTIVE_MASK) {
+                        c1e_detected = 1;
+                        mark_tsc_unstable("TSC halt in C1E");
+                        printk(KERN_INFO "System has C1E enabled\n");
+                }
+        }
+
+        if (c1e_detected) {
+                int cpu = smp_processor_id();
+
+                if (!cpu_isset(cpu, c1e_mask)) {
+                        cpu_set(cpu, c1e_mask);
+                        /*
+                         * Force broadcast so ACPI can not interfere. Needs
+                         * to run with interrupts enabled as it uses
+                         * smp_function_call.
+                         */
+                        local_irq_enable();
+                        clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
+                                           &cpu);
+                        printk(KERN_INFO "Switch to broadcast mode on CPU%d\n",
+                               cpu);
+                        local_irq_disable();
+                }
+                clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
+
+                default_idle();
+
+                /*
+                 * The switch back from broadcast mode needs to be
+                 * called with interrupts disabled.
+                 */
+                 local_irq_disable();
+                 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
+                 local_irq_enable();
+        } else
+                default_idle();
+}
+
+void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
+{
 #ifdef CONFIG_X86_SMP
         if (pm_idle == poll_idle && smp_num_siblings > 1) {
                 printk(KERN_WARNING "WARNING: polling idle and HT enabled,"
                         " performance may degrade.\n");
         }
 #endif
+        if (pm_idle)
+                return;
+
         if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) {
                 /*
-                 * Skip, if setup has overridden idle.
                  * One CPU supports mwait => All CPUs supports mwait
                  */
-                if (!pm_idle) {
-                        printk(KERN_INFO "using mwait in idle threads.\n");
-                        pm_idle = mwait_idle;
-                }
-        }
-        selected = 1;
+                printk(KERN_INFO "using mwait in idle threads.\n");
+                pm_idle = mwait_idle;
+        } else if (check_c1e_idle(c)) {
+                printk(KERN_INFO "using C1E aware idle routine\n");
+                pm_idle = c1e_idle;
+        } else
+                pm_idle = default_idle;
 }
 
 static int __init idle_setup(char *str)
diff --git a/arch/x86/kernel/process_32.c b/arch/x86/kernel/process_32.c
index e2db9ac5c61c..0c3927accb00 100644
--- a/arch/x86/kernel/process_32.c
+++ b/arch/x86/kernel/process_32.c
@@ -58,11 +58,6 @@
 
 asmlinkage void ret_from_fork(void) __asm__("ret_from_fork");
 
-static int hlt_counter;
-
-unsigned long boot_option_idle_override = 0;
-EXPORT_SYMBOL(boot_option_idle_override);
-
 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
 EXPORT_PER_CPU_SYMBOL(current_task);
 
@@ -77,57 +72,24 @@ unsigned long thread_saved_pc(struct task_struct *tsk)
         return ((unsigned long *)tsk->thread.sp)[3];
 }
 
-/*
- * Powermanagement idle function, if any..
- */
-void (*pm_idle)(void);
-EXPORT_SYMBOL(pm_idle);
+#ifdef CONFIG_HOTPLUG_CPU
+#include <asm/nmi.h>
 
-void disable_hlt(void)
+static void cpu_exit_clear(void)
 {
-        hlt_counter++;
-}
+        int cpu = raw_smp_processor_id();
 
-EXPORT_SYMBOL(disable_hlt);
+        idle_task_exit();
 
-void enable_hlt(void)
-{
-        hlt_counter--;
-}
+        cpu_uninit();
+        irq_ctx_exit(cpu);
 
-EXPORT_SYMBOL(enable_hlt);
-
-/*
- * We use this if we don't have any better
- * idle routine..
- */
-void default_idle(void)
-{
-        if (!hlt_counter && boot_cpu_data.hlt_works_ok) {
-                current_thread_info()->status &= ~TS_POLLING;
-                /*
-                 * TS_POLLING-cleared state must be visible before we
-                 * test NEED_RESCHED:
-                 */
-                smp_mb();
+        cpu_clear(cpu, cpu_callout_map);
+        cpu_clear(cpu, cpu_callin_map);
 
-                if (!need_resched())
-                        safe_halt();    /* enables interrupts racelessly */
-                else
-                        local_irq_enable();
-                current_thread_info()->status |= TS_POLLING;
-        } else {
-                local_irq_enable();
-                /* loop is done by the caller */
-                cpu_relax();
-        }
+        numa_remove_cpu(cpu);
 }
-#ifdef CONFIG_APM_MODULE
-EXPORT_SYMBOL(default_idle);
-#endif
 
-#ifdef CONFIG_HOTPLUG_CPU
-#include <asm/nmi.h>
 /* We don't actually take CPU down, just spin without interrupts. */
 static inline void play_dead(void)
 {
@@ -168,24 +130,22 @@ void cpu_idle(void)
         while (1) {
                 tick_nohz_stop_sched_tick();
                 while (!need_resched()) {
-                        void (*idle)(void);
 
                         check_pgt_cache();
                         rmb();
-                        idle = pm_idle;
 
                         if (rcu_pending(cpu))
                                 rcu_check_callbacks(cpu, 0);
 
-                        if (!idle)
-                                idle = default_idle;
-
                         if (cpu_is_offline(cpu))
                                 play_dead();
 
                         local_irq_disable();
                         __get_cpu_var(irq_stat).idle_timestamp = jiffies;
-                        idle();
+                        /* Don't trace irqs off for idle */
+                        stop_critical_timings();
+                        pm_idle();
+                        start_critical_timings();
                 }
                 tick_nohz_restart_sched_tick();
                 preempt_enable_no_resched();
diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c
index c6eb5c91e5f6..a8e53626ac9a 100644
--- a/arch/x86/kernel/process_64.c
+++ b/arch/x86/kernel/process_64.c
@@ -56,15 +56,6 @@ asmlinkage extern void ret_from_fork(void);
 
 unsigned long kernel_thread_flags = CLONE_VM | CLONE_UNTRACED;
 
-unsigned long boot_option_idle_override = 0;
-EXPORT_SYMBOL(boot_option_idle_override);
-
-/*
- * Powermanagement idle function, if any..
- */
-void (*pm_idle)(void);
-EXPORT_SYMBOL(pm_idle);
-
 static ATOMIC_NOTIFIER_HEAD(idle_notifier);
 
 void idle_notifier_register(struct notifier_block *n)
@@ -94,25 +85,6 @@ void exit_idle(void)
         __exit_idle();
 }
 
-/*
- * We use this if we don't have any better
- * idle routine..
- */
-void default_idle(void)
-{
-        current_thread_info()->status &= ~TS_POLLING;
-        /*
-         * TS_POLLING-cleared state must be visible before we
-         * test NEED_RESCHED:
-         */
-        smp_mb();
-        if (!need_resched())
-                safe_halt();    /* enables interrupts racelessly */
-        else
-                local_irq_enable();
-        current_thread_info()->status |= TS_POLLING;
-}
-
 #ifdef CONFIG_HOTPLUG_CPU
 DECLARE_PER_CPU(int, cpu_state);
 
@@ -150,12 +122,9 @@ void cpu_idle(void)
         while (1) {
                 tick_nohz_stop_sched_tick();
                 while (!need_resched()) {
-                        void (*idle)(void);
 
                         rmb();
-                        idle = pm_idle;
-                        if (!idle)
-                                idle = default_idle;
+
                         if (cpu_is_offline(smp_processor_id()))
                                 play_dead();
                         /*
@@ -165,7 +134,10 @@ void cpu_idle(void)
                          */
                         local_irq_disable();
                         enter_idle();
-                        idle();
+                        /* Don't trace irqs off for idle */
+                        stop_critical_timings();
+                        pm_idle();
+                        start_critical_timings();
                         /* In many cases the interrupt that ended idle
                            has already called exit_idle. But some idle
                            loops can be woken up without interrupt. */
@@ -366,10 +338,10 @@ int copy_thread(int nr, unsigned long clone_flags, unsigned long sp,
         p->thread.fs = me->thread.fs;
         p->thread.gs = me->thread.gs;
 
-        asm("mov %%gs,%0" : "=m" (p->thread.gsindex));
-        asm("mov %%fs,%0" : "=m" (p->thread.fsindex));
-        asm("mov %%es,%0" : "=m" (p->thread.es));
-        asm("mov %%ds,%0" : "=m" (p->thread.ds));
+        savesegment(gs, p->thread.gsindex);
+        savesegment(fs, p->thread.fsindex);
+        savesegment(es, p->thread.es);
+        savesegment(ds, p->thread.ds);
 
         if (unlikely(test_tsk_thread_flag(me, TIF_IO_BITMAP))) {
                 p->thread.io_bitmap_ptr = kmalloc(IO_BITMAP_BYTES, GFP_KERNEL);
@@ -408,7 +380,9 @@ out:
 void
 start_thread(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp)
 {
-        asm volatile("movl %0, %%fs; movl %0, %%es; movl %0, %%ds" :: "r"(0));
+        loadsegment(fs, 0);
+        loadsegment(es, 0);
+        loadsegment(ds, 0);
         load_gs_index(0);
         regs->ip                = new_ip;
         regs->sp                = new_sp;
@@ -567,6 +541,7 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p)
                                  *next = &next_p->thread;
         int cpu = smp_processor_id();
         struct tss_struct *tss = &per_cpu(init_tss, cpu);
+        unsigned fsindex, gsindex;
 
         /* we're going to use this soon, after a few expensive things */
         if (next_p->fpu_counter>5)
@@ -581,22 +556,38 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p)
          * Switch DS and ES.
          * This won't pick up thread selector changes, but I guess that is ok.
          */
-        asm volatile("mov %%es,%0" : "=m" (prev->es));
+        savesegment(es, prev->es);
         if (unlikely(next->es | prev->es))
                 loadsegment(es, next->es); 
-        
-        asm volatile ("mov %%ds,%0" : "=m" (prev->ds));
+
+        savesegment(ds, prev->ds);
         if (unlikely(next->ds | prev->ds))
                 loadsegment(ds, next->ds);
 
+
+        /* We must save %fs and %gs before load_TLS() because
+         * %fs and %gs may be cleared by load_TLS().
+         *
+         * (e.g. xen_load_tls())
+         */
+        savesegment(fs, fsindex);
+        savesegment(gs, gsindex);
+
         load_TLS(next, cpu);
 
+        /*
+         * Leave lazy mode, flushing any hypercalls made here.
+         * This must be done before restoring TLS segments so
+         * the GDT and LDT are properly updated, and must be
+         * done before math_state_restore, so the TS bit is up
+         * to date.
+         */
+        arch_leave_lazy_cpu_mode();
+
         /* 
          * Switch FS and GS.
          */
         { 
-                unsigned fsindex;
-                asm volatile("movl %%fs,%0" : "=r" (fsindex)); 
                 /* segment register != 0 always requires a reload. 
                    also reload when it has changed. 
                    when prev process used 64bit base always reload
@@ -614,10 +605,7 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p)
                 if (next->fs) 
                         wrmsrl(MSR_FS_BASE, next->fs); 
                 prev->fsindex = fsindex;
-        }
-        { 
-                unsigned gsindex;
-                asm volatile("movl %%gs,%0" : "=r" (gsindex)); 
+
                 if (unlikely(gsindex | next->gsindex | prev->gs)) {
                         load_gs_index(next->gsindex);
                         if (gsindex)
@@ -798,7 +786,7 @@ long do_arch_prctl(struct task_struct *task, int code, unsigned long addr)
                         set_32bit_tls(task, FS_TLS, addr);
                         if (doit) {
                                 load_TLS(&task->thread, cpu);
-                                asm volatile("movl %0,%%fs" :: "r"(FS_TLS_SEL));
+                                loadsegment(fs, FS_TLS_SEL);
                         }
                         task->thread.fsindex = FS_TLS_SEL;
                         task->thread.fs = 0;
@@ -808,7 +796,7 @@ long do_arch_prctl(struct task_struct *task, int code, unsigned long addr)
                         if (doit) {
                                 /* set the selector to 0 to not confuse
                                    __switch_to */
-                                asm volatile("movl %0,%%fs" :: "r" (0));
+                                loadsegment(fs, 0);
                                 ret = checking_wrmsrl(MSR_FS_BASE, addr);
                         }
                 }
@@ -831,7 +819,7 @@ long do_arch_prctl(struct task_struct *task, int code, unsigned long addr)
                 if (task->thread.gsindex == GS_TLS_SEL)
                         base = read_32bit_tls(task, GS_TLS);
                 else if (doit) {
-                        asm("movl %%gs,%0" : "=r" (gsindex));
+                        savesegment(gs, gsindex);
                         if (gsindex)
                                 rdmsrl(MSR_KERNEL_GS_BASE, base);
                         else
diff --git a/arch/x86/kernel/ptrace.c b/arch/x86/kernel/ptrace.c
index a7835f282936..77040b6070e1 100644
--- a/arch/x86/kernel/ptrace.c
+++ b/arch/x86/kernel/ptrace.c
@@ -943,13 +943,13 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
                 return copy_regset_to_user(child, &user_x86_32_view,
                                            REGSET_XFP,
                                            0, sizeof(struct user_fxsr_struct),
-                                           datap);
+                                           datap) ? -EIO : 0;
 
         case PTRACE_SETFPXREGS: /* Set the child extended FPU state. */
                 return copy_regset_from_user(child, &user_x86_32_view,
                                              REGSET_XFP,
                                              0, sizeof(struct user_fxsr_struct),
-                                             datap);
+                                             datap) ? -EIO : 0;
 #endif
 
 #if defined CONFIG_X86_32 || defined CONFIG_IA32_EMULATION
diff --git a/arch/x86/kernel/quirks.c b/arch/x86/kernel/quirks.c
index d89a648fe710..79bdcd11c66e 100644
--- a/arch/x86/kernel/quirks.c
+++ b/arch/x86/kernel/quirks.c
@@ -65,6 +65,7 @@ static enum {
         ICH_FORCE_HPET_RESUME,
         VT8237_FORCE_HPET_RESUME,
         NVIDIA_FORCE_HPET_RESUME,
+        ATI_FORCE_HPET_RESUME,
 } force_hpet_resume_type;
 
 static void __iomem *rcba_base;
@@ -158,6 +159,8 @@ static void ich_force_enable_hpet(struct pci_dev *dev)
 
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0,
                          ich_force_enable_hpet);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0,
+                         ich_force_enable_hpet);
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1,
                          ich_force_enable_hpet);
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0,
@@ -174,6 +177,12 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7,
 
 static struct pci_dev *cached_dev;
 
+static void hpet_print_force_info(void)
+{
+        printk(KERN_INFO "HPET not enabled in BIOS. "
+               "You might try hpet=force boot option\n");
+}
+
 static void old_ich_force_hpet_resume(void)
 {
         u32 val;
@@ -253,6 +262,8 @@ static void old_ich_force_enable_hpet_user(struct pci_dev *dev)
 {
         if (hpet_force_user)
                 old_ich_force_enable_hpet(dev);
+        else
+                hpet_print_force_info();
 }
 
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0,
@@ -290,8 +301,13 @@ static void vt8237_force_enable_hpet(struct pci_dev *dev)
 {
         u32 uninitialized_var(val);
 
-        if (!hpet_force_user || hpet_address || force_hpet_address)
+        if (hpet_address || force_hpet_address)
+                return;
+
+        if (!hpet_force_user) {
+                hpet_print_force_info();
                 return;
+        }
 
         pci_read_config_dword(dev, 0x68, &val);
         /*
@@ -330,6 +346,36 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235,
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237,
                          vt8237_force_enable_hpet);
 
+static void ati_force_hpet_resume(void)
+{
+        pci_write_config_dword(cached_dev, 0x14, 0xfed00000);
+        printk(KERN_DEBUG "Force enabled HPET at resume\n");
+}
+
+static void ati_force_enable_hpet(struct pci_dev *dev)
+{
+        u32 uninitialized_var(val);
+
+        if (hpet_address || force_hpet_address)
+                return;
+
+        if (!hpet_force_user) {
+                hpet_print_force_info();
+                return;
+        }
+
+        pci_write_config_dword(dev, 0x14, 0xfed00000);
+        pci_read_config_dword(dev, 0x14, &val);
+        force_hpet_address = val;
+        force_hpet_resume_type = ATI_FORCE_HPET_RESUME;
+        dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at 0x%lx\n",
+                   force_hpet_address);
+        cached_dev = dev;
+        return;
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS,
+                         ati_force_enable_hpet);
+
 /*
  * Undocumented chipset feature taken from LinuxBIOS.
  */
@@ -343,8 +389,13 @@ static void nvidia_force_enable_hpet(struct pci_dev *dev)
 {
         u32 uninitialized_var(val);
 
-        if (!hpet_force_user || hpet_address || force_hpet_address)
+        if (hpet_address || force_hpet_address)
+                return;
+
+        if (!hpet_force_user) {
+                hpet_print_force_info();
                 return;
+        }
 
         pci_write_config_dword(dev, 0x44, 0xfed00001);
         pci_read_config_dword(dev, 0x44, &val);
@@ -397,6 +448,9 @@ void force_hpet_resume(void)
         case NVIDIA_FORCE_HPET_RESUME:
                 nvidia_force_hpet_resume();
                 return;
+        case ATI_FORCE_HPET_RESUME:
+                ati_force_hpet_resume();
+                return;
         default:
                 break;
         }
diff --git a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c
index f6be7d5f82f8..f8a62160e151 100644
--- a/arch/x86/kernel/reboot.c
+++ b/arch/x86/kernel/reboot.c
@@ -27,7 +27,7 @@
 void (*pm_power_off)(void);
 EXPORT_SYMBOL(pm_power_off);
 
-static long no_idt[3];
+static const struct desc_ptr no_idt = {};
 static int reboot_mode;
 enum reboot_type reboot_type = BOOT_KBD;
 int reboot_force;
@@ -201,15 +201,15 @@ core_initcall(reboot_init);
    controller to pulse the CPU reset line, which is more thorough, but
    doesn't work with at least one type of 486 motherboard.  It is easy
    to stop this code working; hence the copious comments. */
-static unsigned long long
+static const unsigned long long
 real_mode_gdt_entries [3] =
 {
         0x0000000000000000ULL,  /* Null descriptor */
-        0x00009a000000ffffULL,  /* 16-bit real-mode 64k code at 0x00000000 */
-        0x000092000100ffffULL   /* 16-bit real-mode 64k data at 0x00000100 */
+        0x00009b000000ffffULL,  /* 16-bit real-mode 64k code at 0x00000000 */
+        0x000093000100ffffULL   /* 16-bit real-mode 64k data at 0x00000100 */
 };
 
-static struct desc_ptr
+static const struct desc_ptr
 real_mode_gdt = { sizeof (real_mode_gdt_entries) - 1, (long)real_mode_gdt_entries },
 real_mode_idt = { 0x3ff, 0 };
 
@@ -231,7 +231,7 @@ real_mode_idt = { 0x3ff, 0 };
 
    More could be done here to set up the registers as if a CPU reset had
    occurred; hopefully real BIOSs don't assume much. */
-static unsigned char real_mode_switch [] =
+static const unsigned char real_mode_switch [] =
 {
         0x66, 0x0f, 0x20, 0xc0,                 /*    movl  %cr0,%eax        */
         0x66, 0x83, 0xe0, 0x11,                 /*    andl  $0x00000011,%eax */
@@ -245,7 +245,7 @@ static unsigned char real_mode_switch [] =
         0x24, 0x10,                             /* f: andb  $0x10,al         */
         0x66, 0x0f, 0x22, 0xc0                  /*    movl  %eax,%cr0        */
 };
-static unsigned char jump_to_bios [] =
+static const unsigned char jump_to_bios [] =
 {
         0xea, 0x00, 0x00, 0xff, 0xff            /*    ljmp  $0xffff,$0x0000  */
 };
@@ -255,7 +255,7 @@ static unsigned char jump_to_bios [] =
  * specified by the code and length parameters.
  * We assume that length will aways be less that 100!
  */
-void machine_real_restart(unsigned char *code, int length)
+void machine_real_restart(const unsigned char *code, int length)
 {
         local_irq_disable();
 
@@ -368,7 +368,7 @@ static void native_machine_emergency_restart(void)
                         }
 
                 case BOOT_TRIPLE:
-                        load_idt((const struct desc_ptr *)&no_idt);
+                        load_idt(&no_idt);
                         __asm__ __volatile__("int3");
 
                         reboot_type = BOOT_KBD;
diff --git a/arch/x86/kernel/reboot_fixups_32.c b/arch/x86/kernel/reboot_fixups_32.c
index dec0b5ec25c2..61a837743fe5 100644
--- a/arch/x86/kernel/reboot_fixups_32.c
+++ b/arch/x86/kernel/reboot_fixups_32.c
@@ -49,7 +49,7 @@ struct device_fixup {
         void (*reboot_fixup)(struct pci_dev *);
 };
 
-static struct device_fixup fixups_table[] = {
+static const struct device_fixup fixups_table[] = {
 { PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY, cs5530a_warm_reset },
 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, cs5536_warm_reset },
 { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SC1100_BRIDGE, cs5530a_warm_reset },
@@ -64,7 +64,7 @@ static struct device_fixup fixups_table[] = {
  */
 void mach_reboot_fixups(void)
 {
-        struct device_fixup *cur;
+        const struct device_fixup *cur;
         struct pci_dev *dev;
         int i;
 
diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c
index 6f80b852a196..36c540d4ac4b 100644
--- a/arch/x86/kernel/setup.c
+++ b/arch/x86/kernel/setup.c
@@ -1,139 +1,889 @@
-#include <linux/kernel.h>
+/*
+ *  Copyright (C) 1995  Linus Torvalds
+ *
+ *  Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999
+ *
+ *  Memory region support
+ *      David Parsons <orc@pell.chi.il.us>, July-August 1999
+ *
+ *  Added E820 sanitization routine (removes overlapping memory regions);
+ *  Brian Moyle <bmoyle@mvista.com>, February 2001
+ *
+ * Moved CPU detection code to cpu/${cpu}.c
+ *    Patrick Mochel <mochel@osdl.org>, March 2002
+ *
+ *  Provisions for empty E820 memory regions (reported by certain BIOSes).
+ *  Alex Achenbach <xela@slit.de>, December 2002.
+ *
+ */
+
+/*
+ * This file handles the architecture-dependent parts of initialization
+ */
+
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/mmzone.h>
+#include <linux/screen_info.h>
+#include <linux/ioport.h>
+#include <linux/acpi.h>
+#include <linux/apm_bios.h>
+#include <linux/initrd.h>
+#include <linux/bootmem.h>
+#include <linux/seq_file.h>
+#include <linux/console.h>
+#include <linux/mca.h>
+#include <linux/root_dev.h>
+#include <linux/highmem.h>
 #include <linux/module.h>
+#include <linux/efi.h>
 #include <linux/init.h>
-#include <linux/bootmem.h>
+#include <linux/edd.h>
+#include <linux/iscsi_ibft.h>
+#include <linux/nodemask.h>
+#include <linux/kexec.h>
+#include <linux/dmi.h>
+#include <linux/pfn.h>
+#include <linux/pci.h>
+#include <asm/pci-direct.h>
+#include <linux/init_ohci1394_dma.h>
+#include <linux/kvm_para.h>
+
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/stddef.h>
+#include <linux/unistd.h>
+#include <linux/ptrace.h>
+#include <linux/slab.h>
+#include <linux/user.h>
+#include <linux/delay.h>
+#include <linux/highmem.h>
+
+#include <linux/kallsyms.h>
+#include <linux/edd.h>
+#include <linux/iscsi_ibft.h>
+#include <linux/kexec.h>
+#include <linux/cpufreq.h>
+#include <linux/dma-mapping.h>
+#include <linux/ctype.h>
+#include <linux/uaccess.h>
+
 #include <linux/percpu.h>
+#include <linux/crash_dump.h>
+
+#include <video/edid.h>
+
+#include <asm/mtrr.h>
+#include <asm/apic.h>
+#include <asm/e820.h>
+#include <asm/mpspec.h>
+#include <asm/setup.h>
+#include <asm/arch_hooks.h>
+#include <asm/efi.h>
+#include <asm/sections.h>
+#include <asm/dmi.h>
+#include <asm/io_apic.h>
+#include <asm/ist.h>
+#include <asm/vmi.h>
+#include <setup_arch.h>
+#include <asm/bios_ebda.h>
+#include <asm/cacheflush.h>
+#include <asm/processor.h>
+#include <asm/bugs.h>
+
+#include <asm/system.h>
+#include <asm/vsyscall.h>
 #include <asm/smp.h>
+#include <asm/desc.h>
+#include <asm/dma.h>
+#include <asm/gart.h>
+#include <asm/mmu_context.h>
+#include <asm/proto.h>
+
+#include <mach_apic.h>
+#include <asm/paravirt.h>
+
 #include <asm/percpu.h>
 #include <asm/sections.h>
-#include <asm/processor.h>
-#include <asm/setup.h>
 #include <asm/topology.h>
-#include <asm/mpspec.h>
 #include <asm/apicdef.h>
+#ifdef CONFIG_X86_64
+#include <asm/numa_64.h>
+#endif
 
-#ifdef CONFIG_X86_LOCAL_APIC
-unsigned int num_processors;
-unsigned disabled_cpus __cpuinitdata;
-/* Processor that is doing the boot up */
-unsigned int boot_cpu_physical_apicid = -1U;
-EXPORT_SYMBOL(boot_cpu_physical_apicid);
+#ifndef ARCH_SETUP
+#define ARCH_SETUP
+#endif
+
+#ifndef CONFIG_DEBUG_BOOT_PARAMS
+struct boot_params __initdata boot_params;
+#else
+struct boot_params boot_params;
+#endif
+
+/*
+ * Machine setup..
+ */
+static struct resource data_resource = {
+        .name   = "Kernel data",
+        .start  = 0,
+        .end    = 0,
+        .flags  = IORESOURCE_BUSY | IORESOURCE_MEM
+};
+
+static struct resource code_resource = {
+        .name   = "Kernel code",
+        .start  = 0,
+        .end    = 0,
+        .flags  = IORESOURCE_BUSY | IORESOURCE_MEM
+};
+
+static struct resource bss_resource = {
+        .name   = "Kernel bss",
+        .start  = 0,
+        .end    = 0,
+        .flags  = IORESOURCE_BUSY | IORESOURCE_MEM
+};
+
+
+#ifdef CONFIG_X86_32
+/* This value is set up by the early boot code to point to the value
+   immediately after the boot time page tables.  It contains a *physical*
+   address, and must not be in the .bss segment! */
+unsigned long init_pg_tables_start __initdata = ~0UL;
+unsigned long init_pg_tables_end __initdata = ~0UL;
+
+static struct resource video_ram_resource = {
+        .name   = "Video RAM area",
+        .start  = 0xa0000,
+        .end    = 0xbffff,
+        .flags  = IORESOURCE_BUSY | IORESOURCE_MEM
+};
+
+/* cpu data as detected by the assembly code in head.S */
+struct cpuinfo_x86 new_cpu_data __cpuinitdata = {0, 0, 0, 0, -1, 1, 0, 0, -1};
+/* common cpu data for all cpus */
+struct cpuinfo_x86 boot_cpu_data __read_mostly = {0, 0, 0, 0, -1, 1, 0, 0, -1};
+EXPORT_SYMBOL(boot_cpu_data);
+static void set_mca_bus(int x)
+{
+#ifdef CONFIG_MCA
+        MCA_bus = x;
+#endif
+}
+
+unsigned int def_to_bigsmp;
+
+/* for MCA, but anyone else can use it if they want */
+unsigned int machine_id;
+unsigned int machine_submodel_id;
+unsigned int BIOS_revision;
+
+struct apm_info apm_info;
+EXPORT_SYMBOL(apm_info);
+
+#if defined(CONFIG_X86_SPEEDSTEP_SMI) || \
+        defined(CONFIG_X86_SPEEDSTEP_SMI_MODULE)
+struct ist_info ist_info;
+EXPORT_SYMBOL(ist_info);
+#else
+struct ist_info ist_info;
+#endif
+
+#else
+struct cpuinfo_x86 boot_cpu_data __read_mostly;
+EXPORT_SYMBOL(boot_cpu_data);
+#endif
 
-DEFINE_PER_CPU(u16, x86_cpu_to_apicid) = BAD_APICID;
-EXPORT_PER_CPU_SYMBOL(x86_cpu_to_apicid);
 
-/* Bitmask of physically existing CPUs */
-physid_mask_t phys_cpu_present_map;
+#if !defined(CONFIG_X86_PAE) || defined(CONFIG_X86_64)
+unsigned long mmu_cr4_features;
+#else
+unsigned long mmu_cr4_features = X86_CR4_PAE;
 #endif
 
-#if defined(CONFIG_HAVE_SETUP_PER_CPU_AREA) && defined(CONFIG_X86_SMP)
+/* Boot loader ID as an integer, for the benefit of proc_dointvec */
+int bootloader_type;
+
 /*
- * Copy data used in early init routines from the initial arrays to the
- * per cpu data areas.  These arrays then become expendable and the
- * *_early_ptr's are zeroed indicating that the static arrays are gone.
+ * Early DMI memory
  */
-static void __init setup_per_cpu_maps(void)
+int dmi_alloc_index;
+char dmi_alloc_data[DMI_MAX_DATA];
+
+/*
+ * Setup options
+ */
+struct screen_info screen_info;
+EXPORT_SYMBOL(screen_info);
+struct edid_info edid_info;
+EXPORT_SYMBOL_GPL(edid_info);
+
+extern int root_mountflags;
+
+unsigned long saved_video_mode;
+
+#define RAMDISK_IMAGE_START_MASK        0x07FF
+#define RAMDISK_PROMPT_FLAG             0x8000
+#define RAMDISK_LOAD_FLAG               0x4000
+
+static char __initdata command_line[COMMAND_LINE_SIZE];
+
+#if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
+struct edd edd;
+#ifdef CONFIG_EDD_MODULE
+EXPORT_SYMBOL(edd);
+#endif
+/**
+ * copy_edd() - Copy the BIOS EDD information
+ *              from boot_params into a safe place.
+ *
+ */
+static inline void copy_edd(void)
+{
+     memcpy(edd.mbr_signature, boot_params.edd_mbr_sig_buffer,
+            sizeof(edd.mbr_signature));
+     memcpy(edd.edd_info, boot_params.eddbuf, sizeof(edd.edd_info));
+     edd.mbr_signature_nr = boot_params.edd_mbr_sig_buf_entries;
+     edd.edd_info_nr = boot_params.eddbuf_entries;
+}
+#else
+static inline void copy_edd(void)
+{
+}
+#endif
+
+#ifdef CONFIG_BLK_DEV_INITRD
+
+#ifdef CONFIG_X86_32
+
+#define MAX_MAP_CHUNK   (NR_FIX_BTMAPS << PAGE_SHIFT)
+static void __init relocate_initrd(void)
 {
-        int cpu;
 
-        for_each_possible_cpu(cpu) {
-                per_cpu(x86_cpu_to_apicid, cpu) = x86_cpu_to_apicid_init[cpu];
-                per_cpu(x86_bios_cpu_apicid, cpu) =
-                                                x86_bios_cpu_apicid_init[cpu];
-#ifdef CONFIG_NUMA
-                per_cpu(x86_cpu_to_node_map, cpu) =
-                                                x86_cpu_to_node_map_init[cpu];
+        u64 ramdisk_image = boot_params.hdr.ramdisk_image;
+        u64 ramdisk_size  = boot_params.hdr.ramdisk_size;
+        u64 end_of_lowmem = max_low_pfn << PAGE_SHIFT;
+        u64 ramdisk_here;
+        unsigned long slop, clen, mapaddr;
+        char *p, *q;
+
+        /* We need to move the initrd down into lowmem */
+        ramdisk_here = find_e820_area(0, end_of_lowmem, ramdisk_size,
+                                         PAGE_SIZE);
+
+        if (ramdisk_here == -1ULL)
+                panic("Cannot find place for new RAMDISK of size %lld\n",
+                         ramdisk_size);
+
+        /* Note: this includes all the lowmem currently occupied by
+           the initrd, we rely on that fact to keep the data intact. */
+        reserve_early(ramdisk_here, ramdisk_here + ramdisk_size,
+                         "NEW RAMDISK");
+        initrd_start = ramdisk_here + PAGE_OFFSET;
+        initrd_end   = initrd_start + ramdisk_size;
+        printk(KERN_INFO "Allocated new RAMDISK: %08llx - %08llx\n",
+                         ramdisk_here, ramdisk_here + ramdisk_size);
+
+        q = (char *)initrd_start;
+
+        /* Copy any lowmem portion of the initrd */
+        if (ramdisk_image < end_of_lowmem) {
+                clen = end_of_lowmem - ramdisk_image;
+                p = (char *)__va(ramdisk_image);
+                memcpy(q, p, clen);
+                q += clen;
+                ramdisk_image += clen;
+                ramdisk_size  -= clen;
+        }
+
+        /* Copy the highmem portion of the initrd */
+        while (ramdisk_size) {
+                slop = ramdisk_image & ~PAGE_MASK;
+                clen = ramdisk_size;
+                if (clen > MAX_MAP_CHUNK-slop)
+                        clen = MAX_MAP_CHUNK-slop;
+                mapaddr = ramdisk_image & PAGE_MASK;
+                p = early_ioremap(mapaddr, clen+slop);
+                memcpy(q, p+slop, clen);
+                early_iounmap(p, clen+slop);
+                q += clen;
+                ramdisk_image += clen;
+                ramdisk_size  -= clen;
+        }
+        /* high pages is not converted by early_res_to_bootmem */
+        ramdisk_image = boot_params.hdr.ramdisk_image;
+        ramdisk_size  = boot_params.hdr.ramdisk_size;
+        printk(KERN_INFO "Move RAMDISK from %016llx - %016llx to"
+                " %08llx - %08llx\n",
+                ramdisk_image, ramdisk_image + ramdisk_size - 1,
+                ramdisk_here, ramdisk_here + ramdisk_size - 1);
+}
 #endif
+
+static void __init reserve_initrd(void)
+{
+        u64 ramdisk_image = boot_params.hdr.ramdisk_image;
+        u64 ramdisk_size  = boot_params.hdr.ramdisk_size;
+        u64 ramdisk_end   = ramdisk_image + ramdisk_size;
+        u64 end_of_lowmem = max_low_pfn << PAGE_SHIFT;
+
+        if (!boot_params.hdr.type_of_loader ||
+            !ramdisk_image || !ramdisk_size)
+                return;         /* No initrd provided by bootloader */
+
+        initrd_start = 0;
+
+        if (ramdisk_size >= (end_of_lowmem>>1)) {
+                free_early(ramdisk_image, ramdisk_end);
+                printk(KERN_ERR "initrd too large to handle, "
+                       "disabling initrd\n");
+                return;
+        }
+
+        printk(KERN_INFO "RAMDISK: %08llx - %08llx\n", ramdisk_image,
+                        ramdisk_end);
+
+
+        if (ramdisk_end <= end_of_lowmem) {
+                /* All in lowmem, easy case */
+                /*
+                 * don't need to reserve again, already reserved early
+                 * in i386_start_kernel
+                 */
+                initrd_start = ramdisk_image + PAGE_OFFSET;
+                initrd_end = initrd_start + ramdisk_size;
+                return;
         }
 
-        /* indicate the early static arrays will soon be gone */
-        x86_cpu_to_apicid_early_ptr = NULL;
-        x86_bios_cpu_apicid_early_ptr = NULL;
-#ifdef CONFIG_NUMA
-        x86_cpu_to_node_map_early_ptr = NULL;
+#ifdef CONFIG_X86_32
+        relocate_initrd();
+#else
+        printk(KERN_ERR "initrd extends beyond end of memory "
+               "(0x%08llx > 0x%08llx)\ndisabling initrd\n",
+               ramdisk_end, end_of_lowmem);
+        initrd_start = 0;
 #endif
+        free_early(ramdisk_image, ramdisk_end);
 }
+#else
+static void __init reserve_initrd(void)
+{
+}
+#endif /* CONFIG_BLK_DEV_INITRD */
+
+static void __init parse_setup_data(void)
+{
+        struct setup_data *data;
+        u64 pa_data;
+
+        if (boot_params.hdr.version < 0x0209)
+                return;
+        pa_data = boot_params.hdr.setup_data;
+        while (pa_data) {
+                data = early_ioremap(pa_data, PAGE_SIZE);
+                switch (data->type) {
+                case SETUP_E820_EXT:
+                        parse_e820_ext(data, pa_data);
+                        break;
+                default:
+                        break;
+                }
+                pa_data = data->next;
+                early_iounmap(data, PAGE_SIZE);
+        }
+}
+
+static void __init e820_reserve_setup_data(void)
+{
+        struct setup_data *data;
+        u64 pa_data;
+        int found = 0;
+
+        if (boot_params.hdr.version < 0x0209)
+                return;
+        pa_data = boot_params.hdr.setup_data;
+        while (pa_data) {
+                data = early_ioremap(pa_data, sizeof(*data));
+                e820_update_range(pa_data, sizeof(*data)+data->len,
+                         E820_RAM, E820_RESERVED_KERN);
+                found = 1;
+                pa_data = data->next;
+                early_iounmap(data, sizeof(*data));
+        }
+        if (!found)
+                return;
 
-#ifdef CONFIG_HAVE_CPUMASK_OF_CPU_MAP
-cpumask_t *cpumask_of_cpu_map __read_mostly;
-EXPORT_SYMBOL(cpumask_of_cpu_map);
+        sanitize_e820_map(e820.map, ARRAY_SIZE(e820.map), &e820.nr_map);
+        memcpy(&e820_saved, &e820, sizeof(struct e820map));
+        printk(KERN_INFO "extended physical RAM map:\n");
+        e820_print_map("reserve setup_data");
+}
 
-/* requires nr_cpu_ids to be initialized */
-static void __init setup_cpumask_of_cpu(void)
+static void __init reserve_early_setup_data(void)
 {
-        int i;
+        struct setup_data *data;
+        u64 pa_data;
+        char buf[32];
+
+        if (boot_params.hdr.version < 0x0209)
+                return;
+        pa_data = boot_params.hdr.setup_data;
+        while (pa_data) {
+                data = early_ioremap(pa_data, sizeof(*data));
+                sprintf(buf, "setup data %x", data->type);
+                reserve_early(pa_data, pa_data+sizeof(*data)+data->len, buf);
+                pa_data = data->next;
+                early_iounmap(data, sizeof(*data));
+        }
+}
+
+/*
+ * --------- Crashkernel reservation ------------------------------
+ */
+
+#ifdef CONFIG_KEXEC
+
+/**
+ * Reserve @size bytes of crashkernel memory at any suitable offset.
+ *
+ * @size: Size of the crashkernel memory to reserve.
+ * Returns the base address on success, and -1ULL on failure.
+ */
+unsigned long long find_and_reserve_crashkernel(unsigned long long size)
+{
+        const unsigned long long alignment = 16<<20;    /* 16M */
+        unsigned long long start = 0LL;
+
+        while (1) {
+                int ret;
+
+                start = find_e820_area(start, ULONG_MAX, size, alignment);
+                if (start == -1ULL)
+                        return start;
+
+                /* try to reserve it */
+                ret = reserve_bootmem_generic(start, size, BOOTMEM_EXCLUSIVE);
+                if (ret >= 0)
+                        return start;
+
+                start += alignment;
+        }
+}
 
-        /* alloc_bootmem zeroes memory */
-        cpumask_of_cpu_map = alloc_bootmem_low(sizeof(cpumask_t) * nr_cpu_ids);
-        for (i = 0; i < nr_cpu_ids; i++)
-                cpu_set(i, cpumask_of_cpu_map[i]);
+static inline unsigned long long get_total_mem(void)
+{
+        unsigned long long total;
+
+        total = max_low_pfn - min_low_pfn;
+#ifdef CONFIG_HIGHMEM
+        total += highend_pfn - highstart_pfn;
+#endif
+
+        return total << PAGE_SHIFT;
+}
+
+static void __init reserve_crashkernel(void)
+{
+        unsigned long long total_mem;
+        unsigned long long crash_size, crash_base;
+        int ret;
+
+        total_mem = get_total_mem();
+
+        ret = parse_crashkernel(boot_command_line, total_mem,
+                        &crash_size, &crash_base);
+        if (ret != 0 || crash_size <= 0)
+                return;
+
+        /* 0 means: find the address automatically */
+        if (crash_base <= 0) {
+                crash_base = find_and_reserve_crashkernel(crash_size);
+                if (crash_base == -1ULL) {
+                        pr_info("crashkernel reservation failed. "
+                                "No suitable area found.\n");
+                        return;
+                }
+        } else {
+                ret = reserve_bootmem_generic(crash_base, crash_size,
+                                        BOOTMEM_EXCLUSIVE);
+                if (ret < 0) {
+                        pr_info("crashkernel reservation failed - "
+                                "memory is in use\n");
+                        return;
+                }
+        }
+
+        printk(KERN_INFO "Reserving %ldMB of memory at %ldMB "
+                        "for crashkernel (System RAM: %ldMB)\n",
+                        (unsigned long)(crash_size >> 20),
+                        (unsigned long)(crash_base >> 20),
+                        (unsigned long)(total_mem >> 20));
+
+        crashk_res.start = crash_base;
+        crashk_res.end   = crash_base + crash_size - 1;
+        insert_resource(&iomem_resource, &crashk_res);
 }
 #else
-static inline void setup_cpumask_of_cpu(void) { }
+static void __init reserve_crashkernel(void)
+{
+}
 #endif
 
-#ifdef CONFIG_X86_32
-/*
- * Great future not-so-futuristic plan: make i386 and x86_64 do it
- * the same way
+static struct resource standard_io_resources[] = {
+        { .name = "dma1", .start = 0x00, .end = 0x1f,
+                .flags = IORESOURCE_BUSY | IORESOURCE_IO },
+        { .name = "pic1", .start = 0x20, .end = 0x21,
+                .flags = IORESOURCE_BUSY | IORESOURCE_IO },
+        { .name = "timer0", .start = 0x40, .end = 0x43,
+                .flags = IORESOURCE_BUSY | IORESOURCE_IO },
+        { .name = "timer1", .start = 0x50, .end = 0x53,
+                .flags = IORESOURCE_BUSY | IORESOURCE_IO },
+        { .name = "keyboard", .start = 0x60, .end = 0x60,
+                .flags = IORESOURCE_BUSY | IORESOURCE_IO },
+        { .name = "keyboard", .start = 0x64, .end = 0x64,
+                .flags = IORESOURCE_BUSY | IORESOURCE_IO },
+        { .name = "dma page reg", .start = 0x80, .end = 0x8f,
+                .flags = IORESOURCE_BUSY | IORESOURCE_IO },
+        { .name = "pic2", .start = 0xa0, .end = 0xa1,
+                .flags = IORESOURCE_BUSY | IORESOURCE_IO },
+        { .name = "dma2", .start = 0xc0, .end = 0xdf,
+                .flags = IORESOURCE_BUSY | IORESOURCE_IO },
+        { .name = "fpu", .start = 0xf0, .end = 0xff,
+                .flags = IORESOURCE_BUSY | IORESOURCE_IO }
+};
+
+static void __init reserve_standard_io_resources(void)
+{
+        int i;
+
+        /* request I/O space for devices used on all i[345]86 PCs */
+        for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
+                request_resource(&ioport_resource, &standard_io_resources[i]);
+
+}
+
+#ifdef CONFIG_PROC_VMCORE
+/* elfcorehdr= specifies the location of elf core header
+ * stored by the crashed kernel. This option will be passed
+ * by kexec loader to the capture kernel.
  */
-unsigned long __per_cpu_offset[NR_CPUS] __read_mostly;
-EXPORT_SYMBOL(__per_cpu_offset);
+static int __init setup_elfcorehdr(char *arg)
+{
+        char *end;
+        if (!arg)
+                return -EINVAL;
+        elfcorehdr_addr = memparse(arg, &end);
+        return end > arg ? 0 : -EINVAL;
+}
+early_param("elfcorehdr", setup_elfcorehdr);
 #endif
 
 /*
- * Great future plan:
- * Declare PDA itself and support (irqstack,tss,pgd) as per cpu data.
- * Always point %gs to its beginning
+ * Determine if we were loaded by an EFI loader.  If so, then we have also been
+ * passed the efi memmap, systab, etc., so we should use these data structures
+ * for initialization.  Note, the efi init code path is determined by the
+ * global efi_enabled. This allows the same kernel image to be used on existing
+ * systems (with a traditional BIOS) as well as on EFI systems.
  */
-void __init setup_per_cpu_areas(void)
+/*
+ * setup_arch - architecture-specific boot-time initializations
+ *
+ * Note: On x86_64, fixmaps are ready for use even before this is called.
+ */
+
+void __init setup_arch(char **cmdline_p)
 {
-        int i, highest_cpu = 0;
-        unsigned long size;
+#ifdef CONFIG_X86_32
+        memcpy(&boot_cpu_data, &new_cpu_data, sizeof(new_cpu_data));
+        visws_early_detect();
+        pre_setup_arch_hook();
+        early_cpu_init();
+#else
+        printk(KERN_INFO "Command line: %s\n", boot_command_line);
+#endif
 
-#ifdef CONFIG_HOTPLUG_CPU
-        prefill_possible_map();
+        early_ioremap_init();
+
+        ROOT_DEV = old_decode_dev(boot_params.hdr.root_dev);
+        screen_info = boot_params.screen_info;
+        edid_info = boot_params.edid_info;
+#ifdef CONFIG_X86_32
+        apm_info.bios = boot_params.apm_bios_info;
+        ist_info = boot_params.ist_info;
+        if (boot_params.sys_desc_table.length != 0) {
+                set_mca_bus(boot_params.sys_desc_table.table[3] & 0x2);
+                machine_id = boot_params.sys_desc_table.table[0];
+                machine_submodel_id = boot_params.sys_desc_table.table[1];
+                BIOS_revision = boot_params.sys_desc_table.table[2];
+        }
+#endif
+        saved_video_mode = boot_params.hdr.vid_mode;
+        bootloader_type = boot_params.hdr.type_of_loader;
+
+#ifdef CONFIG_BLK_DEV_RAM
+        rd_image_start = boot_params.hdr.ram_size & RAMDISK_IMAGE_START_MASK;
+        rd_prompt = ((boot_params.hdr.ram_size & RAMDISK_PROMPT_FLAG) != 0);
+        rd_doload = ((boot_params.hdr.ram_size & RAMDISK_LOAD_FLAG) != 0);
 #endif
+#ifdef CONFIG_EFI
+        if (!strncmp((char *)&boot_params.efi_info.efi_loader_signature,
+#ifdef CONFIG_X86_32
+                     "EL32",
+#else
+                     "EL64",
+#endif
+         4)) {
+                efi_enabled = 1;
+                efi_reserve_early();
+        }
+#endif
+
+        ARCH_SETUP
 
-        /* Copy section for each CPU (we discard the original) */
-        size = PERCPU_ENOUGH_ROOM;
-        printk(KERN_INFO "PERCPU: Allocating %lu bytes of per cpu data\n",
-                          size);
+        setup_memory_map();
+        parse_setup_data();
+        /* update the e820_saved too */
+        e820_reserve_setup_data();
 
-        for_each_possible_cpu(i) {
-                char *ptr;
-#ifndef CONFIG_NEED_MULTIPLE_NODES
-                ptr = alloc_bootmem_pages(size);
+        copy_edd();
+
+        if (!boot_params.hdr.root_flags)
+                root_mountflags &= ~MS_RDONLY;
+        init_mm.start_code = (unsigned long) _text;
+        init_mm.end_code = (unsigned long) _etext;
+        init_mm.end_data = (unsigned long) _edata;
+#ifdef CONFIG_X86_32
+        init_mm.brk = init_pg_tables_end + PAGE_OFFSET;
 #else
-                int node = early_cpu_to_node(i);
-                if (!node_online(node) || !NODE_DATA(node)) {
-                        ptr = alloc_bootmem_pages(size);
-                        printk(KERN_INFO
-                               "cpu %d has no node or node-local memory\n", i);
-                }
-                else
-                        ptr = alloc_bootmem_pages_node(NODE_DATA(node), size);
+        init_mm.brk = (unsigned long) &_end;
 #endif
-                if (!ptr)
-                        panic("Cannot allocate cpu data for CPU %d\n", i);
+
+        code_resource.start = virt_to_phys(_text);
+        code_resource.end = virt_to_phys(_etext)-1;
+        data_resource.start = virt_to_phys(_etext);
+        data_resource.end = virt_to_phys(_edata)-1;
+        bss_resource.start = virt_to_phys(&__bss_start);
+        bss_resource.end = virt_to_phys(&__bss_stop)-1;
+
 #ifdef CONFIG_X86_64
-                cpu_pda(i)->data_offset = ptr - __per_cpu_start;
+        early_cpu_init();
+#endif
+        strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
+        *cmdline_p = command_line;
+
+        parse_early_param();
+
+        /* after early param, so could get panic from serial */
+        reserve_early_setup_data();
+
+        if (acpi_mps_check()) {
+#ifdef CONFIG_X86_LOCAL_APIC
+                disable_apic = 1;
+#endif
+                clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
+        }
+
+        finish_e820_parsing();
+
+#ifdef CONFIG_X86_32
+        probe_roms();
+#endif
+
+        /* after parse_early_param, so could debug it */
+        insert_resource(&iomem_resource, &code_resource);
+        insert_resource(&iomem_resource, &data_resource);
+        insert_resource(&iomem_resource, &bss_resource);
+
+        if (efi_enabled)
+                efi_init();
+
+#ifdef CONFIG_X86_32
+        if (ppro_with_ram_bug()) {
+                e820_update_range(0x70000000ULL, 0x40000ULL, E820_RAM,
+                                  E820_RESERVED);
+                sanitize_e820_map(e820.map, ARRAY_SIZE(e820.map), &e820.nr_map);
+                printk(KERN_INFO "fixed physical RAM map:\n");
+                e820_print_map("bad_ppro");
+        }
+#else
+        early_gart_iommu_check();
+#endif
+
+        /*
+         * partially used pages are not usable - thus
+         * we are rounding upwards:
+         */
+        max_pfn = e820_end_of_ram_pfn();
+
+        /* preallocate 4k for mptable mpc */
+        early_reserve_e820_mpc_new();
+        /* update e820 for memory not covered by WB MTRRs */
+        mtrr_bp_init();
+        if (mtrr_trim_uncached_memory(max_pfn))
+                max_pfn = e820_end_of_ram_pfn();
+
+#ifdef CONFIG_X86_32
+        /* max_low_pfn get updated here */
+        find_low_pfn_range();
 #else
-                __per_cpu_offset[i] = ptr - __per_cpu_start;
+        num_physpages = max_pfn;
+
+        check_efer();
+
+        /* How many end-of-memory variables you have, grandma! */
+        /* need this before calling reserve_initrd */
+        if (max_pfn > (1UL<<(32 - PAGE_SHIFT)))
+                max_low_pfn = e820_end_of_low_ram_pfn();
+        else
+                max_low_pfn = max_pfn;
+
+        high_memory = (void *)__va(max_pfn * PAGE_SIZE - 1) + 1;
 #endif
-                memcpy(ptr, __per_cpu_start, __per_cpu_end - __per_cpu_start);
 
-                highest_cpu = i;
+        /* max_pfn_mapped is updated here */
+        max_low_pfn_mapped = init_memory_mapping(0, max_low_pfn<<PAGE_SHIFT);
+        max_pfn_mapped = max_low_pfn_mapped;
+
+#ifdef CONFIG_X86_64
+        if (max_pfn > max_low_pfn) {
+                max_pfn_mapped = init_memory_mapping(1UL<<32,
+                                                     max_pfn<<PAGE_SHIFT);
+                /* can we preseve max_low_pfn ?*/
+                max_low_pfn = max_pfn;
         }
+#endif
+
+        /*
+         * NOTE: On x86-32, only from this point on, fixmaps are ready for use.
+         */
 
-        nr_cpu_ids = highest_cpu + 1;
-        printk(KERN_DEBUG "NR_CPUS: %d, nr_cpu_ids: %d\n", NR_CPUS, nr_cpu_ids);
+#ifdef CONFIG_PROVIDE_OHCI1394_DMA_INIT
+        if (init_ohci1394_dma_early)
+                init_ohci1394_dma_on_all_controllers();
+#endif
 
-        /* Setup percpu data maps */
-        setup_per_cpu_maps();
+        reserve_initrd();
 
-        /* Setup cpumask_of_cpu map */
-        setup_cpumask_of_cpu();
-}
+#ifdef CONFIG_X86_64
+        vsmp_init();
+#endif
+
+        dmi_scan_machine();
+
+        io_delay_init();
+
+        /*
+         * Parse the ACPI tables for possible boot-time SMP configuration.
+         */
+        acpi_boot_table_init();
+
+#ifdef CONFIG_ACPI_NUMA
+        /*
+         * Parse SRAT to discover nodes.
+         */
+        acpi_numa_init();
+#endif
+
+        initmem_init(0, max_pfn);
+
+#ifdef CONFIG_X86_64
+        dma32_reserve_bootmem();
+#endif
 
+#ifdef CONFIG_ACPI_SLEEP
+        /*
+         * Reserve low memory region for sleep support.
+         */
+        acpi_reserve_bootmem();
+#endif
+#ifdef CONFIG_X86_FIND_SMP_CONFIG
+        /*
+         * Find and reserve possible boot-time SMP configuration:
+         */
+        find_smp_config();
 #endif
+        reserve_crashkernel();
+
+        reserve_ibft_region();
+
+#ifdef CONFIG_KVM_CLOCK
+        kvmclock_init();
+#endif
+
+#if defined(CONFIG_VMI) && defined(CONFIG_X86_32)
+        /*
+         * Must be after max_low_pfn is determined, and before kernel
+         * pagetables are setup.
+         */
+        vmi_init();
+#endif
+
+        paging_init();
+
+#ifdef CONFIG_X86_64
+        map_vsyscall();
+#endif
+
+#ifdef CONFIG_X86_GENERICARCH
+        generic_apic_probe();
+#endif
+
+        early_quirks();
+
+        /*
+         * Read APIC and some other early information from ACPI tables.
+         */
+        acpi_boot_init();
+
+#if defined(CONFIG_X86_MPPARSE) || defined(CONFIG_X86_VISWS)
+        /*
+         * get boot-time SMP configuration:
+         */
+        if (smp_found_config)
+                get_smp_config();
+#endif
+
+        prefill_possible_map();
+#ifdef CONFIG_X86_64
+        init_cpu_to_node();
+#endif
+
+#ifdef CONFIG_X86_NUMAQ
+        /*
+         * need to check online nodes num, call it
+         * here before time_init/tsc_init
+         */
+        numaq_tsc_disable();
+#endif
+
+        init_apic_mappings();
+        ioapic_init_mappings();
+
+#if defined(CONFIG_SMP) && defined(CONFIG_X86_PC) && defined(CONFIG_X86_32)
+        if (def_to_bigsmp)
+                printk(KERN_WARNING "More than 8 CPUs detected and "
+                        "CONFIG_X86_PC cannot handle it.\nUse "
+                        "CONFIG_X86_GENERICARCH or CONFIG_X86_BIGSMP.\n");
+#endif
+        kvm_guest_init();
+
+        e820_reserve_resources();
+        e820_mark_nosave_regions(max_low_pfn);
+
+#ifdef CONFIG_X86_32
+        request_resource(&iomem_resource, &video_ram_resource);
+#endif
+        reserve_standard_io_resources();
+
+        e820_setup_gap();
+
+#ifdef CONFIG_VT
+#if defined(CONFIG_VGA_CONSOLE)
+        if (!efi_enabled || (efi_mem_type(0xa0000) != EFI_CONVENTIONAL_MEMORY))
+                conswitchp = &vga_con;
+#elif defined(CONFIG_DUMMY_CONSOLE)
+        conswitchp = &dummy_con;
+#endif
+#endif
+}
diff --git a/arch/x86/kernel/setup64.c b/arch/x86/kernel/setup64.c
deleted file mode 100644
index aee0e8200777..000000000000
--- a/arch/x86/kernel/setup64.c
+++ /dev/null
@@ -1,287 +0,0 @@
-/* 
- * X86-64 specific CPU setup.
- * Copyright (C) 1995  Linus Torvalds
- * Copyright 2001, 2002, 2003 SuSE Labs / Andi Kleen.
- * See setup.c for older changelog.
- */ 
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/string.h>
-#include <linux/bootmem.h>
-#include <linux/bitops.h>
-#include <linux/module.h>
-#include <linux/kgdb.h>
-#include <asm/pda.h>
-#include <asm/pgtable.h>
-#include <asm/processor.h>
-#include <asm/desc.h>
-#include <asm/atomic.h>
-#include <asm/mmu_context.h>
-#include <asm/smp.h>
-#include <asm/i387.h>
-#include <asm/percpu.h>
-#include <asm/proto.h>
-#include <asm/sections.h>
-#include <asm/setup.h>
-#include <asm/genapic.h>
-
-#ifndef CONFIG_DEBUG_BOOT_PARAMS
-struct boot_params __initdata boot_params;
-#else
-struct boot_params boot_params;
-#endif
-
-cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE;
-
-struct x8664_pda *_cpu_pda[NR_CPUS] __read_mostly;
-EXPORT_SYMBOL(_cpu_pda);
-struct x8664_pda boot_cpu_pda[NR_CPUS] __cacheline_aligned;
-
-struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table };
-
-char boot_cpu_stack[IRQSTACKSIZE] __attribute__((section(".bss.page_aligned")));
-
-unsigned long __supported_pte_mask __read_mostly = ~0UL;
-EXPORT_SYMBOL_GPL(__supported_pte_mask);
-
-static int do_not_nx __cpuinitdata = 0;
-
-/* noexec=on|off
-Control non executable mappings for 64bit processes.
-
-on      Enable(default)
-off     Disable
-*/ 
-static int __init nonx_setup(char *str)
-{
-        if (!str)
-                return -EINVAL;
-        if (!strncmp(str, "on", 2)) {
-                __supported_pte_mask |= _PAGE_NX; 
-                do_not_nx = 0; 
-        } else if (!strncmp(str, "off", 3)) {
-                do_not_nx = 1;
-                __supported_pte_mask &= ~_PAGE_NX;
-        }
-        return 0;
-} 
-early_param("noexec", nonx_setup);
-
-int force_personality32 = 0; 
-
-/* noexec32=on|off
-Control non executable heap for 32bit processes.
-To control the stack too use noexec=off
-
-on      PROT_READ does not imply PROT_EXEC for 32bit processes (default)
-off     PROT_READ implies PROT_EXEC
-*/
-static int __init nonx32_setup(char *str)
-{
-        if (!strcmp(str, "on"))
-                force_personality32 &= ~READ_IMPLIES_EXEC;
-        else if (!strcmp(str, "off"))
-                force_personality32 |= READ_IMPLIES_EXEC;
-        return 1;
-}
-__setup("noexec32=", nonx32_setup);
-
-void pda_init(int cpu)
-{ 
-        struct x8664_pda *pda = cpu_pda(cpu);
-
-        /* Setup up data that may be needed in __get_free_pages early */
-        asm volatile("movl %0,%%fs ; movl %0,%%gs" :: "r" (0)); 
-        /* Memory clobbers used to order PDA accessed */
-        mb();
-        wrmsrl(MSR_GS_BASE, pda);
-        mb();
-
-        pda->cpunumber = cpu; 
-        pda->irqcount = -1;
-        pda->kernelstack = 
-                (unsigned long)stack_thread_info() - PDA_STACKOFFSET + THREAD_SIZE; 
-        pda->active_mm = &init_mm;
-        pda->mmu_state = 0;
-
-        if (cpu == 0) {
-                /* others are initialized in smpboot.c */
-                pda->pcurrent = &init_task;
-                pda->irqstackptr = boot_cpu_stack; 
-        } else {
-                pda->irqstackptr = (char *)
-                        __get_free_pages(GFP_ATOMIC, IRQSTACK_ORDER);
-                if (!pda->irqstackptr)
-                        panic("cannot allocate irqstack for cpu %d", cpu); 
-        }
-
-
-        pda->irqstackptr += IRQSTACKSIZE-64;
-} 
-
-char boot_exception_stacks[(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]
-__attribute__((section(".bss.page_aligned")));
-
-extern asmlinkage void ignore_sysret(void);
-
-/* May not be marked __init: used by software suspend */
-void syscall_init(void)
-{
-        /* 
-         * LSTAR and STAR live in a bit strange symbiosis.
-         * They both write to the same internal register. STAR allows to set CS/DS
-         * but only a 32bit target. LSTAR sets the 64bit rip.    
-         */ 
-        wrmsrl(MSR_STAR,  ((u64)__USER32_CS)<<48  | ((u64)__KERNEL_CS)<<32); 
-        wrmsrl(MSR_LSTAR, system_call); 
-        wrmsrl(MSR_CSTAR, ignore_sysret);
-
-#ifdef CONFIG_IA32_EMULATION            
-        syscall32_cpu_init ();
-#endif
-
-        /* Flags to clear on syscall */
-        wrmsrl(MSR_SYSCALL_MASK,
-               X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL);
-}
-
-void __cpuinit check_efer(void)
-{
-        unsigned long efer;
-
-        rdmsrl(MSR_EFER, efer); 
-        if (!(efer & EFER_NX) || do_not_nx) { 
-                __supported_pte_mask &= ~_PAGE_NX; 
-        }       
-}
-
-unsigned long kernel_eflags;
-
-/*
- * Copies of the original ist values from the tss are only accessed during
- * debugging, no special alignment required.
- */
-DEFINE_PER_CPU(struct orig_ist, orig_ist);
-
-/*
- * cpu_init() initializes state that is per-CPU. Some data is already
- * initialized (naturally) in the bootstrap process, such as the GDT
- * and IDT. We reload them nevertheless, this function acts as a
- * 'CPU state barrier', nothing should get across.
- * A lot of state is already set up in PDA init.
- */
-void __cpuinit cpu_init (void)
-{
-        int cpu = stack_smp_processor_id();
-        struct tss_struct *t = &per_cpu(init_tss, cpu);
-        struct orig_ist *orig_ist = &per_cpu(orig_ist, cpu);
-        unsigned long v; 
-        char *estacks = NULL; 
-        struct task_struct *me;
-        int i;
-
-        /* CPU 0 is initialised in head64.c */
-        if (cpu != 0) {
-                pda_init(cpu);
-        } else 
-                estacks = boot_exception_stacks; 
-
-        me = current;
-
-        if (cpu_test_and_set(cpu, cpu_initialized))
-                panic("CPU#%d already initialized!\n", cpu);
-
-        printk("Initializing CPU#%d\n", cpu);
-
-        clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
-
-        /*
-         * Initialize the per-CPU GDT with the boot GDT,
-         * and set up the GDT descriptor:
-         */
-        if (cpu)
-                memcpy(get_cpu_gdt_table(cpu), cpu_gdt_table, GDT_SIZE);
-
-        cpu_gdt_descr[cpu].size = GDT_SIZE;
-        load_gdt((const struct desc_ptr *)&cpu_gdt_descr[cpu]);
-        load_idt((const struct desc_ptr *)&idt_descr);
-
-        memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
-        syscall_init();
-
-        wrmsrl(MSR_FS_BASE, 0);
-        wrmsrl(MSR_KERNEL_GS_BASE, 0);
-        barrier(); 
-
-        check_efer();
-
-        /*
-         * set up and load the per-CPU TSS
-         */
-        for (v = 0; v < N_EXCEPTION_STACKS; v++) {
-                static const unsigned int order[N_EXCEPTION_STACKS] = {
-                        [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STACK_ORDER,
-                        [DEBUG_STACK - 1] = DEBUG_STACK_ORDER
-                };
-                if (cpu) {
-                        estacks = (char *)__get_free_pages(GFP_ATOMIC, order[v]);
-                        if (!estacks)
-                                panic("Cannot allocate exception stack %ld %d\n",
-                                      v, cpu); 
-                }
-                estacks += PAGE_SIZE << order[v];
-                orig_ist->ist[v] = t->x86_tss.ist[v] = (unsigned long)estacks;
-        }
-
-        t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
-        /*
-         * <= is required because the CPU will access up to
-         * 8 bits beyond the end of the IO permission bitmap.
-         */
-        for (i = 0; i <= IO_BITMAP_LONGS; i++)
-                t->io_bitmap[i] = ~0UL;
-
-        atomic_inc(&init_mm.mm_count);
-        me->active_mm = &init_mm;
-        if (me->mm)
-                BUG();
-        enter_lazy_tlb(&init_mm, me);
-
-        set_tss_desc(cpu, t);
-        load_TR_desc();
-        load_LDT(&init_mm.context);
-
-#ifdef CONFIG_KGDB
-        /*
-         * If the kgdb is connected no debug regs should be altered.  This
-         * is only applicable when KGDB and a KGDB I/O module are built
-         * into the kernel and you are using early debugging with
-         * kgdbwait. KGDB will control the kernel HW breakpoint registers.
-         */
-        if (kgdb_connected && arch_kgdb_ops.correct_hw_break)
-                arch_kgdb_ops.correct_hw_break();
-        else {
-#endif
-        /*
-         * Clear all 6 debug registers:
-         */
-
-        set_debugreg(0UL, 0);
-        set_debugreg(0UL, 1);
-        set_debugreg(0UL, 2);
-        set_debugreg(0UL, 3);
-        set_debugreg(0UL, 6);
-        set_debugreg(0UL, 7);
-#ifdef CONFIG_KGDB
-        /* If the kgdb is connected no debug regs should be altered. */
-        }
-#endif
-
-        fpu_init(); 
-
-        raw_local_save_flags(kernel_eflags);
-
-        if (is_uv_system())
-                uv_cpu_init();
-}
diff --git a/arch/x86/kernel/setup_32.c b/arch/x86/kernel/setup_32.c
deleted file mode 100644
index 5a2f8e063887..000000000000
--- a/arch/x86/kernel/setup_32.c
+++ /dev/null
@@ -1,964 +0,0 @@
-/*
- *  Copyright (C) 1995  Linus Torvalds
- *
- *  Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999
- *
- *  Memory region support
- *      David Parsons <orc@pell.chi.il.us>, July-August 1999
- *
- *  Added E820 sanitization routine (removes overlapping memory regions);
- *  Brian Moyle <bmoyle@mvista.com>, February 2001
- *
- * Moved CPU detection code to cpu/${cpu}.c
- *    Patrick Mochel <mochel@osdl.org>, March 2002
- *
- *  Provisions for empty E820 memory regions (reported by certain BIOSes).
- *  Alex Achenbach <xela@slit.de>, December 2002.
- *
- */
-
-/*
- * This file handles the architecture-dependent parts of initialization
- */
-
-#include <linux/sched.h>
-#include <linux/mm.h>
-#include <linux/mmzone.h>
-#include <linux/screen_info.h>
-#include <linux/ioport.h>
-#include <linux/acpi.h>
-#include <linux/apm_bios.h>
-#include <linux/initrd.h>
-#include <linux/bootmem.h>
-#include <linux/seq_file.h>
-#include <linux/console.h>
-#include <linux/mca.h>
-#include <linux/root_dev.h>
-#include <linux/highmem.h>
-#include <linux/module.h>
-#include <linux/efi.h>
-#include <linux/init.h>
-#include <linux/edd.h>
-#include <linux/iscsi_ibft.h>
-#include <linux/nodemask.h>
-#include <linux/kexec.h>
-#include <linux/crash_dump.h>
-#include <linux/dmi.h>
-#include <linux/pfn.h>
-#include <linux/pci.h>
-#include <linux/init_ohci1394_dma.h>
-#include <linux/kvm_para.h>
-
-#include <video/edid.h>
-
-#include <asm/mtrr.h>
-#include <asm/apic.h>
-#include <asm/e820.h>
-#include <asm/mpspec.h>
-#include <asm/mmzone.h>
-#include <asm/setup.h>
-#include <asm/arch_hooks.h>
-#include <asm/sections.h>
-#include <asm/io_apic.h>
-#include <asm/ist.h>
-#include <asm/io.h>
-#include <asm/vmi.h>
-#include <setup_arch.h>
-#include <asm/bios_ebda.h>
-#include <asm/cacheflush.h>
-#include <asm/processor.h>
-
-/* This value is set up by the early boot code to point to the value
-   immediately after the boot time page tables.  It contains a *physical*
-   address, and must not be in the .bss segment! */
-unsigned long init_pg_tables_end __initdata = ~0UL;
-
-/*
- * Machine setup..
- */
-static struct resource data_resource = {
-        .name   = "Kernel data",
-        .start  = 0,
-        .end    = 0,
-        .flags  = IORESOURCE_BUSY | IORESOURCE_MEM
-};
-
-static struct resource code_resource = {
-        .name   = "Kernel code",
-        .start  = 0,
-        .end    = 0,
-        .flags  = IORESOURCE_BUSY | IORESOURCE_MEM
-};
-
-static struct resource bss_resource = {
-        .name   = "Kernel bss",
-        .start  = 0,
-        .end    = 0,
-        .flags  = IORESOURCE_BUSY | IORESOURCE_MEM
-};
-
-static struct resource video_ram_resource = {
-        .name   = "Video RAM area",
-        .start  = 0xa0000,
-        .end    = 0xbffff,
-        .flags  = IORESOURCE_BUSY | IORESOURCE_MEM
-};
-
-static struct resource standard_io_resources[] = { {
-        .name   = "dma1",
-        .start  = 0x0000,
-        .end    = 0x001f,
-        .flags  = IORESOURCE_BUSY | IORESOURCE_IO
-}, {
-        .name   = "pic1",
-        .start  = 0x0020,
-        .end    = 0x0021,
-        .flags  = IORESOURCE_BUSY | IORESOURCE_IO
-}, {
-        .name   = "timer0",
-        .start  = 0x0040,
-        .end    = 0x0043,
-        .flags  = IORESOURCE_BUSY | IORESOURCE_IO
-}, {
-        .name   = "timer1",
-        .start  = 0x0050,
-        .end    = 0x0053,
-        .flags  = IORESOURCE_BUSY | IORESOURCE_IO
-}, {
-        .name   = "keyboard",
-        .start  = 0x0060,
-        .end    = 0x0060,
-        .flags  = IORESOURCE_BUSY | IORESOURCE_IO
-}, {
-        .name   = "keyboard",
-        .start  = 0x0064,
-        .end    = 0x0064,
-        .flags  = IORESOURCE_BUSY | IORESOURCE_IO
-}, {
-        .name   = "dma page reg",
-        .start  = 0x0080,
-        .end    = 0x008f,
-        .flags  = IORESOURCE_BUSY | IORESOURCE_IO
-}, {
-        .name   = "pic2",
-        .start  = 0x00a0,
-        .end    = 0x00a1,
-        .flags  = IORESOURCE_BUSY | IORESOURCE_IO
-}, {
-        .name   = "dma2",
-        .start  = 0x00c0,
-        .end    = 0x00df,
-        .flags  = IORESOURCE_BUSY | IORESOURCE_IO
-}, {
-        .name   = "fpu",
-        .start  = 0x00f0,
-        .end    = 0x00ff,
-        .flags  = IORESOURCE_BUSY | IORESOURCE_IO
-} };
-
-/* cpu data as detected by the assembly code in head.S */
-struct cpuinfo_x86 new_cpu_data __cpuinitdata = { 0, 0, 0, 0, -1, 1, 0, 0, -1 };
-/* common cpu data for all cpus */
-struct cpuinfo_x86 boot_cpu_data __read_mostly = { 0, 0, 0, 0, -1, 1, 0, 0, -1 };
-EXPORT_SYMBOL(boot_cpu_data);
-
-unsigned int def_to_bigsmp;
-
-#ifndef CONFIG_X86_PAE
-unsigned long mmu_cr4_features;
-#else
-unsigned long mmu_cr4_features = X86_CR4_PAE;
-#endif
-
-/* for MCA, but anyone else can use it if they want */
-unsigned int machine_id;
-unsigned int machine_submodel_id;
-unsigned int BIOS_revision;
-
-/* Boot loader ID as an integer, for the benefit of proc_dointvec */
-int bootloader_type;
-
-/* user-defined highmem size */
-static unsigned int highmem_pages = -1;
-
-/*
- * Setup options
- */
-struct screen_info screen_info;
-EXPORT_SYMBOL(screen_info);
-struct apm_info apm_info;
-EXPORT_SYMBOL(apm_info);
-struct edid_info edid_info;
-EXPORT_SYMBOL_GPL(edid_info);
-struct ist_info ist_info;
-#if defined(CONFIG_X86_SPEEDSTEP_SMI) || \
-        defined(CONFIG_X86_SPEEDSTEP_SMI_MODULE)
-EXPORT_SYMBOL(ist_info);
-#endif
-
-extern void early_cpu_init(void);
-extern int root_mountflags;
-
-unsigned long saved_video_mode;
-
-#define RAMDISK_IMAGE_START_MASK        0x07FF
-#define RAMDISK_PROMPT_FLAG             0x8000
-#define RAMDISK_LOAD_FLAG               0x4000
-
-static char __initdata command_line[COMMAND_LINE_SIZE];
-
-#ifndef CONFIG_DEBUG_BOOT_PARAMS
-struct boot_params __initdata boot_params;
-#else
-struct boot_params boot_params;
-#endif
-
-#if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
-struct edd edd;
-#ifdef CONFIG_EDD_MODULE
-EXPORT_SYMBOL(edd);
-#endif
-/**
- * copy_edd() - Copy the BIOS EDD information
- *              from boot_params into a safe place.
- *
- */
-static inline void copy_edd(void)
-{
-     memcpy(edd.mbr_signature, boot_params.edd_mbr_sig_buffer,
-            sizeof(edd.mbr_signature));
-     memcpy(edd.edd_info, boot_params.eddbuf, sizeof(edd.edd_info));
-     edd.mbr_signature_nr = boot_params.edd_mbr_sig_buf_entries;
-     edd.edd_info_nr = boot_params.eddbuf_entries;
-}
-#else
-static inline void copy_edd(void)
-{
-}
-#endif
-
-int __initdata user_defined_memmap;
-
-/*
- * "mem=nopentium" disables the 4MB page tables.
- * "mem=XXX[kKmM]" defines a memory region from HIGH_MEM
- * to <mem>, overriding the bios size.
- * "memmap=XXX[KkmM]@XXX[KkmM]" defines a memory region from
- * <start> to <start>+<mem>, overriding the bios size.
- *
- * HPA tells me bootloaders need to parse mem=, so no new
- * option should be mem=  [also see Documentation/i386/boot.txt]
- */
-static int __init parse_mem(char *arg)
-{
-        if (!arg)
-                return -EINVAL;
-
-        if (strcmp(arg, "nopentium") == 0) {
-                setup_clear_cpu_cap(X86_FEATURE_PSE);
-        } else {
-                /* If the user specifies memory size, we
-                 * limit the BIOS-provided memory map to
-                 * that size. exactmap can be used to specify
-                 * the exact map. mem=number can be used to
-                 * trim the existing memory map.
-                 */
-                unsigned long long mem_size;
-
-                mem_size = memparse(arg, &arg);
-                limit_regions(mem_size);
-                user_defined_memmap = 1;
-        }
-        return 0;
-}
-early_param("mem", parse_mem);
-
-#ifdef CONFIG_PROC_VMCORE
-/* elfcorehdr= specifies the location of elf core header
- * stored by the crashed kernel.
- */
-static int __init parse_elfcorehdr(char *arg)
-{
-        if (!arg)
-                return -EINVAL;
-
-        elfcorehdr_addr = memparse(arg, &arg);
-        return 0;
-}
-early_param("elfcorehdr", parse_elfcorehdr);
-#endif /* CONFIG_PROC_VMCORE */
-
-/*
- * highmem=size forces highmem to be exactly 'size' bytes.
- * This works even on boxes that have no highmem otherwise.
- * This also works to reduce highmem size on bigger boxes.
- */
-static int __init parse_highmem(char *arg)
-{
-        if (!arg)
-                return -EINVAL;
-
-        highmem_pages = memparse(arg, &arg) >> PAGE_SHIFT;
-        return 0;
-}
-early_param("highmem", parse_highmem);
-
-/*
- * vmalloc=size forces the vmalloc area to be exactly 'size'
- * bytes. This can be used to increase (or decrease) the
- * vmalloc area - the default is 128m.
- */
-static int __init parse_vmalloc(char *arg)
-{
-        if (!arg)
-                return -EINVAL;
-
-        __VMALLOC_RESERVE = memparse(arg, &arg);
-        return 0;
-}
-early_param("vmalloc", parse_vmalloc);
-
-/*
- * reservetop=size reserves a hole at the top of the kernel address space which
- * a hypervisor can load into later.  Needed for dynamically loaded hypervisors,
- * so relocating the fixmap can be done before paging initialization.
- */
-static int __init parse_reservetop(char *arg)
-{
-        unsigned long address;
-
-        if (!arg)
-                return -EINVAL;
-
-        address = memparse(arg, &arg);
-        reserve_top_address(address);
-        return 0;
-}
-early_param("reservetop", parse_reservetop);
-
-/*
- * Determine low and high memory ranges:
- */
-unsigned long __init find_max_low_pfn(void)
-{
-        unsigned long max_low_pfn;
-
-        max_low_pfn = max_pfn;
-        if (max_low_pfn > MAXMEM_PFN) {
-                if (highmem_pages == -1)
-                        highmem_pages = max_pfn - MAXMEM_PFN;
-                if (highmem_pages + MAXMEM_PFN < max_pfn)
-                        max_pfn = MAXMEM_PFN + highmem_pages;
-                if (highmem_pages + MAXMEM_PFN > max_pfn) {
-                        printk("only %luMB highmem pages available, ignoring highmem size of %uMB.\n", pages_to_mb(max_pfn - MAXMEM_PFN), pages_to_mb(highmem_pages));
-                        highmem_pages = 0;
-                }
-                max_low_pfn = MAXMEM_PFN;
-#ifndef CONFIG_HIGHMEM
-                /* Maximum memory usable is what is directly addressable */
-                printk(KERN_WARNING "Warning only %ldMB will be used.\n",
-                                        MAXMEM>>20);
-                if (max_pfn > MAX_NONPAE_PFN)
-                        printk(KERN_WARNING "Use a HIGHMEM64G enabled kernel.\n");
-                else
-                        printk(KERN_WARNING "Use a HIGHMEM enabled kernel.\n");
-                max_pfn = MAXMEM_PFN;
-#else /* !CONFIG_HIGHMEM */
-#ifndef CONFIG_HIGHMEM64G
-                if (max_pfn > MAX_NONPAE_PFN) {
-                        max_pfn = MAX_NONPAE_PFN;
-                        printk(KERN_WARNING "Warning only 4GB will be used.\n");
-                        printk(KERN_WARNING "Use a HIGHMEM64G enabled kernel.\n");
-                }
-#endif /* !CONFIG_HIGHMEM64G */
-#endif /* !CONFIG_HIGHMEM */
-        } else {
-                if (highmem_pages == -1)
-                        highmem_pages = 0;
-#ifdef CONFIG_HIGHMEM
-                if (highmem_pages >= max_pfn) {
-                        printk(KERN_ERR "highmem size specified (%uMB) is bigger than pages available (%luMB)!.\n", pages_to_mb(highmem_pages), pages_to_mb(max_pfn));
-                        highmem_pages = 0;
-                }
-                if (highmem_pages) {
-                        if (max_low_pfn-highmem_pages < 64*1024*1024/PAGE_SIZE){
-                                printk(KERN_ERR "highmem size %uMB results in smaller than 64MB lowmem, ignoring it.\n", pages_to_mb(highmem_pages));
-                                highmem_pages = 0;
-                        }
-                        max_low_pfn -= highmem_pages;
-                }
-#else
-                if (highmem_pages)
-                        printk(KERN_ERR "ignoring highmem size on non-highmem kernel!\n");
-#endif
-        }
-        return max_low_pfn;
-}
-
-#define BIOS_LOWMEM_KILOBYTES 0x413
-
-/*
- * The BIOS places the EBDA/XBDA at the top of conventional
- * memory, and usually decreases the reported amount of
- * conventional memory (int 0x12) too. This also contains a
- * workaround for Dell systems that neglect to reserve EBDA.
- * The same workaround also avoids a problem with the AMD768MPX
- * chipset: reserve a page before VGA to prevent PCI prefetch
- * into it (errata #56). Usually the page is reserved anyways,
- * unless you have no PS/2 mouse plugged in.
- */
-static void __init reserve_ebda_region(void)
-{
-        unsigned int lowmem, ebda_addr;
-
-        /* To determine the position of the EBDA and the */
-        /* end of conventional memory, we need to look at */
-        /* the BIOS data area. In a paravirtual environment */
-        /* that area is absent. We'll just have to assume */
-        /* that the paravirt case can handle memory setup */
-        /* correctly, without our help. */
-        if (paravirt_enabled())
-                return;
-
-        /* end of low (conventional) memory */
-        lowmem = *(unsigned short *)__va(BIOS_LOWMEM_KILOBYTES);
-        lowmem <<= 10;
-
-        /* start of EBDA area */
-        ebda_addr = get_bios_ebda();
-
-        /* Fixup: bios puts an EBDA in the top 64K segment */
-        /* of conventional memory, but does not adjust lowmem. */
-        if ((lowmem - ebda_addr) <= 0x10000)
-                lowmem = ebda_addr;
-
-        /* Fixup: bios does not report an EBDA at all. */
-        /* Some old Dells seem to need 4k anyhow (bugzilla 2990) */
-        if ((ebda_addr == 0) && (lowmem >= 0x9f000))
-                lowmem = 0x9f000;
-
-        /* Paranoia: should never happen, but... */
-        if ((lowmem == 0) || (lowmem >= 0x100000))
-                lowmem = 0x9f000;
-
-        /* reserve all memory between lowmem and the 1MB mark */
-        reserve_bootmem(lowmem, 0x100000 - lowmem, BOOTMEM_DEFAULT);
-}
-
-#ifndef CONFIG_NEED_MULTIPLE_NODES
-static void __init setup_bootmem_allocator(void);
-static unsigned long __init setup_memory(void)
-{
-        /*
-         * partially used pages are not usable - thus
-         * we are rounding upwards:
-         */
-        min_low_pfn = PFN_UP(init_pg_tables_end);
-
-        max_low_pfn = find_max_low_pfn();
-
-#ifdef CONFIG_HIGHMEM
-        highstart_pfn = highend_pfn = max_pfn;
-        if (max_pfn > max_low_pfn) {
-                highstart_pfn = max_low_pfn;
-        }
-        printk(KERN_NOTICE "%ldMB HIGHMEM available.\n",
-                pages_to_mb(highend_pfn - highstart_pfn));
-        num_physpages = highend_pfn;
-        high_memory = (void *) __va(highstart_pfn * PAGE_SIZE - 1) + 1;
-#else
-        num_physpages = max_low_pfn;
-        high_memory = (void *) __va(max_low_pfn * PAGE_SIZE - 1) + 1;
-#endif
-#ifdef CONFIG_FLATMEM
-        max_mapnr = num_physpages;
-#endif
-        printk(KERN_NOTICE "%ldMB LOWMEM available.\n",
-                        pages_to_mb(max_low_pfn));
-
-        setup_bootmem_allocator();
-
-        return max_low_pfn;
-}
-
-static void __init zone_sizes_init(void)
-{
-        unsigned long max_zone_pfns[MAX_NR_ZONES];
-        memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
-        max_zone_pfns[ZONE_DMA] =
-                virt_to_phys((char *)MAX_DMA_ADDRESS) >> PAGE_SHIFT;
-        max_zone_pfns[ZONE_NORMAL] = max_low_pfn;
-#ifdef CONFIG_HIGHMEM
-        max_zone_pfns[ZONE_HIGHMEM] = highend_pfn;
-        add_active_range(0, 0, highend_pfn);
-#else
-        add_active_range(0, 0, max_low_pfn);
-#endif
-
-        free_area_init_nodes(max_zone_pfns);
-}
-#else
-extern unsigned long __init setup_memory(void);
-extern void zone_sizes_init(void);
-#endif /* !CONFIG_NEED_MULTIPLE_NODES */
-
-static inline unsigned long long get_total_mem(void)
-{
-        unsigned long long total;
-
-        total = max_low_pfn - min_low_pfn;
-#ifdef CONFIG_HIGHMEM
-        total += highend_pfn - highstart_pfn;
-#endif
-
-        return total << PAGE_SHIFT;
-}
-
-#ifdef CONFIG_KEXEC
-static void __init reserve_crashkernel(void)
-{
-        unsigned long long total_mem;
-        unsigned long long crash_size, crash_base;
-        int ret;
-
-        total_mem = get_total_mem();
-
-        ret = parse_crashkernel(boot_command_line, total_mem,
-                        &crash_size, &crash_base);
-        if (ret == 0 && crash_size > 0) {
-                if (crash_base > 0) {
-                        printk(KERN_INFO "Reserving %ldMB of memory at %ldMB "
-                                        "for crashkernel (System RAM: %ldMB)\n",
-                                        (unsigned long)(crash_size >> 20),
-                                        (unsigned long)(crash_base >> 20),
-                                        (unsigned long)(total_mem >> 20));
-
-                        if (reserve_bootmem(crash_base, crash_size,
-                                        BOOTMEM_EXCLUSIVE) < 0) {
-                                printk(KERN_INFO "crashkernel reservation "
-                                        "failed - memory is in use\n");
-                                return;
-                        }
-
-                        crashk_res.start = crash_base;
-                        crashk_res.end   = crash_base + crash_size - 1;
-                } else
-                        printk(KERN_INFO "crashkernel reservation failed - "
-                                        "you have to specify a base address\n");
-        }
-}
-#else
-static inline void __init reserve_crashkernel(void)
-{}
-#endif
-
-#ifdef CONFIG_BLK_DEV_INITRD
-
-static bool do_relocate_initrd = false;
-
-static void __init reserve_initrd(void)
-{
-        unsigned long ramdisk_image = boot_params.hdr.ramdisk_image;
-        unsigned long ramdisk_size  = boot_params.hdr.ramdisk_size;
-        unsigned long ramdisk_end   = ramdisk_image + ramdisk_size;
-        unsigned long end_of_lowmem = max_low_pfn << PAGE_SHIFT;
-        unsigned long ramdisk_here;
-
-        initrd_start = 0;
-
-        if (!boot_params.hdr.type_of_loader ||
-            !ramdisk_image || !ramdisk_size)
-                return;         /* No initrd provided by bootloader */
-
-        if (ramdisk_end < ramdisk_image) {
-                printk(KERN_ERR "initrd wraps around end of memory, "
-                       "disabling initrd\n");
-                return;
-        }
-        if (ramdisk_size >= end_of_lowmem/2) {
-                printk(KERN_ERR "initrd too large to handle, "
-                       "disabling initrd\n");
-                return;
-        }
-        if (ramdisk_end <= end_of_lowmem) {
-                /* All in lowmem, easy case */
-                reserve_bootmem(ramdisk_image, ramdisk_size, BOOTMEM_DEFAULT);
-                initrd_start = ramdisk_image + PAGE_OFFSET;
-                initrd_end = initrd_start+ramdisk_size;
-                return;
-        }
-
-        /* We need to move the initrd down into lowmem */
-        ramdisk_here = (end_of_lowmem - ramdisk_size) & PAGE_MASK;
-
-        /* Note: this includes all the lowmem currently occupied by
-           the initrd, we rely on that fact to keep the data intact. */
-        reserve_bootmem(ramdisk_here, ramdisk_size, BOOTMEM_DEFAULT);
-        initrd_start = ramdisk_here + PAGE_OFFSET;
-        initrd_end   = initrd_start + ramdisk_size;
-
-        do_relocate_initrd = true;
-}
-
-#define MAX_MAP_CHUNK   (NR_FIX_BTMAPS << PAGE_SHIFT)
-
-static void __init relocate_initrd(void)
-{
-        unsigned long ramdisk_image = boot_params.hdr.ramdisk_image;
-        unsigned long ramdisk_size  = boot_params.hdr.ramdisk_size;
-        unsigned long end_of_lowmem = max_low_pfn << PAGE_SHIFT;
-        unsigned long ramdisk_here;
-        unsigned long slop, clen, mapaddr;
-        char *p, *q;
-
-        if (!do_relocate_initrd)
-                return;
-
-        ramdisk_here = initrd_start - PAGE_OFFSET;
-
-        q = (char *)initrd_start;
-
-        /* Copy any lowmem portion of the initrd */
-        if (ramdisk_image < end_of_lowmem) {
-                clen = end_of_lowmem - ramdisk_image;
-                p = (char *)__va(ramdisk_image);
-                memcpy(q, p, clen);
-                q += clen;
-                ramdisk_image += clen;
-                ramdisk_size  -= clen;
-        }
-
-        /* Copy the highmem portion of the initrd */
-        while (ramdisk_size) {
-                slop = ramdisk_image & ~PAGE_MASK;
-                clen = ramdisk_size;
-                if (clen > MAX_MAP_CHUNK-slop)
-                        clen = MAX_MAP_CHUNK-slop;
-                mapaddr = ramdisk_image & PAGE_MASK;
-                p = early_ioremap(mapaddr, clen+slop);
-                memcpy(q, p+slop, clen);
-                early_iounmap(p, clen+slop);
-                q += clen;
-                ramdisk_image += clen;
-                ramdisk_size  -= clen;
-        }
-}
-
-#endif /* CONFIG_BLK_DEV_INITRD */
-
-void __init setup_bootmem_allocator(void)
-{
-        unsigned long bootmap_size;
-        /*
-         * Initialize the boot-time allocator (with low memory only):
-         */
-        bootmap_size = init_bootmem(min_low_pfn, max_low_pfn);
-
-        register_bootmem_low_pages(max_low_pfn);
-
-        /*
-         * Reserve the bootmem bitmap itself as well. We do this in two
-         * steps (first step was init_bootmem()) because this catches
-         * the (very unlikely) case of us accidentally initializing the
-         * bootmem allocator with an invalid RAM area.
-         */
-        reserve_bootmem(__pa_symbol(_text), (PFN_PHYS(min_low_pfn) +
-                         bootmap_size + PAGE_SIZE-1) - __pa_symbol(_text),
-                         BOOTMEM_DEFAULT);
-
-        /*
-         * reserve physical page 0 - it's a special BIOS page on many boxes,
-         * enabling clean reboots, SMP operation, laptop functions.
-         */
-        reserve_bootmem(0, PAGE_SIZE, BOOTMEM_DEFAULT);
-
-        /* reserve EBDA region */
-        reserve_ebda_region();
-
-#ifdef CONFIG_SMP
-        /*
-         * But first pinch a few for the stack/trampoline stuff
-         * FIXME: Don't need the extra page at 4K, but need to fix
-         * trampoline before removing it. (see the GDT stuff)
-         */
-        reserve_bootmem(PAGE_SIZE, PAGE_SIZE, BOOTMEM_DEFAULT);
-#endif
-#ifdef CONFIG_ACPI_SLEEP
-        /*
-         * Reserve low memory region for sleep support.
-         */
-        acpi_reserve_bootmem();
-#endif
-#ifdef CONFIG_X86_FIND_SMP_CONFIG
-        /*
-         * Find and reserve possible boot-time SMP configuration:
-         */
-        find_smp_config();
-#endif
-#ifdef CONFIG_BLK_DEV_INITRD
-        reserve_initrd();
-#endif
-        numa_kva_reserve();
-        reserve_crashkernel();
-
-        reserve_ibft_region();
-}
-
-/*
- * The node 0 pgdat is initialized before all of these because
- * it's needed for bootmem.  node>0 pgdats have their virtual
- * space allocated before the pagetables are in place to access
- * them, so they can't be cleared then.
- *
- * This should all compile down to nothing when NUMA is off.
- */
-static void __init remapped_pgdat_init(void)
-{
-        int nid;
-
-        for_each_online_node(nid) {
-                if (nid != 0)
-                        memset(NODE_DATA(nid), 0, sizeof(struct pglist_data));
-        }
-}
-
-#ifdef CONFIG_MCA
-static void set_mca_bus(int x)
-{
-        MCA_bus = x;
-}
-#else
-static void set_mca_bus(int x) { }
-#endif
-
-/* Overridden in paravirt.c if CONFIG_PARAVIRT */
-char * __init __attribute__((weak)) memory_setup(void)
-{
-        return machine_specific_memory_setup();
-}
-
-#ifdef CONFIG_NUMA
-/*
- * In the golden day, when everything among i386 and x86_64 will be
- * integrated, this will not live here
- */
-void *x86_cpu_to_node_map_early_ptr;
-int x86_cpu_to_node_map_init[NR_CPUS] = {
-        [0 ... NR_CPUS-1] = NUMA_NO_NODE
-};
-DEFINE_PER_CPU(int, x86_cpu_to_node_map) = NUMA_NO_NODE;
-#endif
-
-/*
- * Determine if we were loaded by an EFI loader.  If so, then we have also been
- * passed the efi memmap, systab, etc., so we should use these data structures
- * for initialization.  Note, the efi init code path is determined by the
- * global efi_enabled. This allows the same kernel image to be used on existing
- * systems (with a traditional BIOS) as well as on EFI systems.
- */
-void __init setup_arch(char **cmdline_p)
-{
-        unsigned long max_low_pfn;
-
-        memcpy(&boot_cpu_data, &new_cpu_data, sizeof(new_cpu_data));
-        pre_setup_arch_hook();
-        early_cpu_init();
-        early_ioremap_init();
-
-#ifdef CONFIG_EFI
-        if (!strncmp((char *)&boot_params.efi_info.efi_loader_signature,
-                     "EL32", 4))
-                efi_enabled = 1;
-#endif
-
-        ROOT_DEV = old_decode_dev(boot_params.hdr.root_dev);
-        screen_info = boot_params.screen_info;
-        edid_info = boot_params.edid_info;
-        apm_info.bios = boot_params.apm_bios_info;
-        ist_info = boot_params.ist_info;
-        saved_video_mode = boot_params.hdr.vid_mode;
-        if( boot_params.sys_desc_table.length != 0 ) {
-                set_mca_bus(boot_params.sys_desc_table.table[3] & 0x2);
-                machine_id = boot_params.sys_desc_table.table[0];
-                machine_submodel_id = boot_params.sys_desc_table.table[1];
-                BIOS_revision = boot_params.sys_desc_table.table[2];
-        }
-        bootloader_type = boot_params.hdr.type_of_loader;
-
-#ifdef CONFIG_BLK_DEV_RAM
-        rd_image_start = boot_params.hdr.ram_size & RAMDISK_IMAGE_START_MASK;
-        rd_prompt = ((boot_params.hdr.ram_size & RAMDISK_PROMPT_FLAG) != 0);
-        rd_doload = ((boot_params.hdr.ram_size & RAMDISK_LOAD_FLAG) != 0);
-#endif
-        ARCH_SETUP
-
-        printk(KERN_INFO "BIOS-provided physical RAM map:\n");
-        print_memory_map(memory_setup());
-
-        copy_edd();
-
-        if (!boot_params.hdr.root_flags)
-                root_mountflags &= ~MS_RDONLY;
-        init_mm.start_code = (unsigned long) _text;
-        init_mm.end_code = (unsigned long) _etext;
-        init_mm.end_data = (unsigned long) _edata;
-        init_mm.brk = init_pg_tables_end + PAGE_OFFSET;
-
-        code_resource.start = virt_to_phys(_text);
-        code_resource.end = virt_to_phys(_etext)-1;
-        data_resource.start = virt_to_phys(_etext);
-        data_resource.end = virt_to_phys(_edata)-1;
-        bss_resource.start = virt_to_phys(&__bss_start);
-        bss_resource.end = virt_to_phys(&__bss_stop)-1;
-
-        parse_early_param();
-
-        if (user_defined_memmap) {
-                printk(KERN_INFO "user-defined physical RAM map:\n");
-                print_memory_map("user");
-        }
-
-        strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
-        *cmdline_p = command_line;
-
-        if (efi_enabled)
-                efi_init();
-
-        /* update e820 for memory not covered by WB MTRRs */
-        propagate_e820_map();
-        mtrr_bp_init();
-        if (mtrr_trim_uncached_memory(max_pfn))
-                propagate_e820_map();
-
-        max_low_pfn = setup_memory();
-
-#ifdef CONFIG_KVM_CLOCK
-        kvmclock_init();
-#endif
-
-#ifdef CONFIG_VMI
-        /*
-         * Must be after max_low_pfn is determined, and before kernel
-         * pagetables are setup.
-         */
-        vmi_init();
-#endif
-        kvm_guest_init();
-
-        /*
-         * NOTE: before this point _nobody_ is allowed to allocate
-         * any memory using the bootmem allocator.  Although the
-         * allocator is now initialised only the first 8Mb of the kernel
-         * virtual address space has been mapped.  All allocations before
-         * paging_init() has completed must use the alloc_bootmem_low_pages()
-         * variant (which allocates DMA'able memory) and care must be taken
-         * not to exceed the 8Mb limit.
-         */
-
-#ifdef CONFIG_SMP
-        smp_alloc_memory(); /* AP processor realmode stacks in low memory*/
-#endif
-        paging_init();
-
-        /*
-         * NOTE: On x86-32, only from this point on, fixmaps are ready for use.
-         */
-
-#ifdef CONFIG_PROVIDE_OHCI1394_DMA_INIT
-        if (init_ohci1394_dma_early)
-                init_ohci1394_dma_on_all_controllers();
-#endif
-
-        remapped_pgdat_init();
-        sparse_init();
-        zone_sizes_init();
-
-        /*
-         * NOTE: at this point the bootmem allocator is fully available.
-         */
-
-#ifdef CONFIG_BLK_DEV_INITRD
-        relocate_initrd();
-#endif
-
-        paravirt_post_allocator_init();
-
-        dmi_scan_machine();
-
-        io_delay_init();
-
-#ifdef CONFIG_X86_SMP
-        /*
-         * setup to use the early static init tables during kernel startup
-         * X86_SMP will exclude sub-arches that don't deal well with it.
-         */
-        x86_cpu_to_apicid_early_ptr = (void *)x86_cpu_to_apicid_init;
-        x86_bios_cpu_apicid_early_ptr = (void *)x86_bios_cpu_apicid_init;
-#ifdef CONFIG_NUMA
-        x86_cpu_to_node_map_early_ptr = (void *)x86_cpu_to_node_map_init;
-#endif
-#endif
-
-#ifdef CONFIG_X86_GENERICARCH
-        generic_apic_probe();
-#endif
-
-#ifdef CONFIG_ACPI
-        /*
-         * Parse the ACPI tables for possible boot-time SMP configuration.
-         */
-        acpi_boot_table_init();
-#endif
-
-        early_quirks();
-
-#ifdef CONFIG_ACPI
-        acpi_boot_init();
-
-#if defined(CONFIG_SMP) && defined(CONFIG_X86_PC)
-        if (def_to_bigsmp)
-                printk(KERN_WARNING "More than 8 CPUs detected and "
-                        "CONFIG_X86_PC cannot handle it.\nUse "
-                        "CONFIG_X86_GENERICARCH or CONFIG_X86_BIGSMP.\n");
-#endif
-#endif
-#ifdef CONFIG_X86_LOCAL_APIC
-        if (smp_found_config)
-                get_smp_config();
-#endif
-
-        e820_register_memory();
-        e820_mark_nosave_regions();
-
-#ifdef CONFIG_VT
-#if defined(CONFIG_VGA_CONSOLE)
-        if (!efi_enabled || (efi_mem_type(0xa0000) != EFI_CONVENTIONAL_MEMORY))
-                conswitchp = &vga_con;
-#elif defined(CONFIG_DUMMY_CONSOLE)
-        conswitchp = &dummy_con;
-#endif
-#endif
-}
-
-/*
- * Request address space for all standard resources
- *
- * This is called just before pcibios_init(), which is also a
- * subsys_initcall, but is linked in later (in arch/i386/pci/common.c).
- */
-static int __init request_standard_resources(void)
-{
-        int i;
-
-        printk(KERN_INFO "Setting up standard PCI resources\n");
-        init_iomem_resources(&code_resource, &data_resource, &bss_resource);
-
-        request_resource(&iomem_resource, &video_ram_resource);
-
-        /* request I/O space for devices used on all i[345]86 PCs */
-        for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
-                request_resource(&ioport_resource, &standard_io_resources[i]);
-        return 0;
-}
-
-subsys_initcall(request_standard_resources);
diff --git a/arch/x86/kernel/setup_64.c b/arch/x86/kernel/setup_64.c
deleted file mode 100644
index 6dff1286ad8a..000000000000
--- a/arch/x86/kernel/setup_64.c
+++ /dev/null
@@ -1,1194 +0,0 @@
-/*
- *  Copyright (C) 1995  Linus Torvalds
- */
-
-/*
- * This file handles the architecture-dependent parts of initialization
- */
-
-#include <linux/errno.h>
-#include <linux/sched.h>
-#include <linux/kernel.h>
-#include <linux/mm.h>
-#include <linux/stddef.h>
-#include <linux/unistd.h>
-#include <linux/ptrace.h>
-#include <linux/slab.h>
-#include <linux/user.h>
-#include <linux/screen_info.h>
-#include <linux/ioport.h>
-#include <linux/delay.h>
-#include <linux/init.h>
-#include <linux/initrd.h>
-#include <linux/highmem.h>
-#include <linux/bootmem.h>
-#include <linux/module.h>
-#include <asm/processor.h>
-#include <linux/console.h>
-#include <linux/seq_file.h>
-#include <linux/crash_dump.h>
-#include <linux/root_dev.h>
-#include <linux/pci.h>
-#include <asm/pci-direct.h>
-#include <linux/efi.h>
-#include <linux/acpi.h>
-#include <linux/kallsyms.h>
-#include <linux/edd.h>
-#include <linux/iscsi_ibft.h>
-#include <linux/mmzone.h>
-#include <linux/kexec.h>
-#include <linux/cpufreq.h>
-#include <linux/dmi.h>
-#include <linux/dma-mapping.h>
-#include <linux/ctype.h>
-#include <linux/sort.h>
-#include <linux/uaccess.h>
-#include <linux/init_ohci1394_dma.h>
-#include <linux/kvm_para.h>
-
-#include <asm/mtrr.h>
-#include <asm/uaccess.h>
-#include <asm/system.h>
-#include <asm/vsyscall.h>
-#include <asm/io.h>
-#include <asm/smp.h>
-#include <asm/msr.h>
-#include <asm/desc.h>
-#include <video/edid.h>
-#include <asm/e820.h>
-#include <asm/dma.h>
-#include <asm/gart.h>
-#include <asm/mpspec.h>
-#include <asm/mmu_context.h>
-#include <asm/proto.h>
-#include <asm/setup.h>
-#include <asm/numa.h>
-#include <asm/sections.h>
-#include <asm/dmi.h>
-#include <asm/cacheflush.h>
-#include <asm/mce.h>
-#include <asm/ds.h>
-#include <asm/topology.h>
-#include <asm/trampoline.h>
-#include <asm/pat.h>
-
-#include <mach_apic.h>
-#ifdef CONFIG_PARAVIRT
-#include <asm/paravirt.h>
-#else
-#define ARCH_SETUP
-#endif
-
-/*
- * Machine setup..
- */
-
-struct cpuinfo_x86 boot_cpu_data __read_mostly;
-EXPORT_SYMBOL(boot_cpu_data);
-
-__u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;
-
-unsigned long mmu_cr4_features;
-
-/* Boot loader ID as an integer, for the benefit of proc_dointvec */
-int bootloader_type;
-
-unsigned long saved_video_mode;
-
-int force_mwait __cpuinitdata;
-
-/*
- * Early DMI memory
- */
-int dmi_alloc_index;
-char dmi_alloc_data[DMI_MAX_DATA];
-
-/*
- * Setup options
- */
-struct screen_info screen_info;
-EXPORT_SYMBOL(screen_info);
-struct sys_desc_table_struct {
-        unsigned short length;
-        unsigned char table[0];
-};
-
-struct edid_info edid_info;
-EXPORT_SYMBOL_GPL(edid_info);
-
-extern int root_mountflags;
-
-char __initdata command_line[COMMAND_LINE_SIZE];
-
-static struct resource standard_io_resources[] = {
-        { .name = "dma1", .start = 0x00, .end = 0x1f,
-                .flags = IORESOURCE_BUSY | IORESOURCE_IO },
-        { .name = "pic1", .start = 0x20, .end = 0x21,
-                .flags = IORESOURCE_BUSY | IORESOURCE_IO },
-        { .name = "timer0", .start = 0x40, .end = 0x43,
-                .flags = IORESOURCE_BUSY | IORESOURCE_IO },
-        { .name = "timer1", .start = 0x50, .end = 0x53,
-                .flags = IORESOURCE_BUSY | IORESOURCE_IO },
-        { .name = "keyboard", .start = 0x60, .end = 0x60,
-                .flags = IORESOURCE_BUSY | IORESOURCE_IO },
-        { .name = "keyboard", .start = 0x64, .end = 0x64,
-                .flags = IORESOURCE_BUSY | IORESOURCE_IO },
-        { .name = "dma page reg", .start = 0x80, .end = 0x8f,
-                .flags = IORESOURCE_BUSY | IORESOURCE_IO },
-        { .name = "pic2", .start = 0xa0, .end = 0xa1,
-                .flags = IORESOURCE_BUSY | IORESOURCE_IO },
-        { .name = "dma2", .start = 0xc0, .end = 0xdf,
-                .flags = IORESOURCE_BUSY | IORESOURCE_IO },
-        { .name = "fpu", .start = 0xf0, .end = 0xff,
-                .flags = IORESOURCE_BUSY | IORESOURCE_IO }
-};
-
-#define IORESOURCE_RAM (IORESOURCE_BUSY | IORESOURCE_MEM)
-
-static struct resource data_resource = {
-        .name = "Kernel data",
-        .start = 0,
-        .end = 0,
-        .flags = IORESOURCE_RAM,
-};
-static struct resource code_resource = {
-        .name = "Kernel code",
-        .start = 0,
-        .end = 0,
-        .flags = IORESOURCE_RAM,
-};
-static struct resource bss_resource = {
-        .name = "Kernel bss",
-        .start = 0,
-        .end = 0,
-        .flags = IORESOURCE_RAM,
-};
-
-static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c);
-
-#ifdef CONFIG_PROC_VMCORE
-/* elfcorehdr= specifies the location of elf core header
- * stored by the crashed kernel. This option will be passed
- * by kexec loader to the capture kernel.
- */
-static int __init setup_elfcorehdr(char *arg)
-{
-        char *end;
-        if (!arg)
-                return -EINVAL;
-        elfcorehdr_addr = memparse(arg, &end);
-        return end > arg ? 0 : -EINVAL;
-}
-early_param("elfcorehdr", setup_elfcorehdr);
-#endif
-
-#ifndef CONFIG_NUMA
-static void __init
-contig_initmem_init(unsigned long start_pfn, unsigned long end_pfn)
-{
-        unsigned long bootmap_size, bootmap;
-
-        bootmap_size = bootmem_bootmap_pages(end_pfn)<<PAGE_SHIFT;
-        bootmap = find_e820_area(0, end_pfn<<PAGE_SHIFT, bootmap_size,
-                                 PAGE_SIZE);
-        if (bootmap == -1L)
-                panic("Cannot find bootmem map of size %ld\n", bootmap_size);
-        bootmap_size = init_bootmem(bootmap >> PAGE_SHIFT, end_pfn);
-        e820_register_active_regions(0, start_pfn, end_pfn);
-        free_bootmem_with_active_regions(0, end_pfn);
-        early_res_to_bootmem(0, end_pfn<<PAGE_SHIFT);
-        reserve_bootmem(bootmap, bootmap_size, BOOTMEM_DEFAULT);
-}
-#endif
-
-#if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
-struct edd edd;
-#ifdef CONFIG_EDD_MODULE
-EXPORT_SYMBOL(edd);
-#endif
-/**
- * copy_edd() - Copy the BIOS EDD information
- *              from boot_params into a safe place.
- *
- */
-static inline void copy_edd(void)
-{
-     memcpy(edd.mbr_signature, boot_params.edd_mbr_sig_buffer,
-            sizeof(edd.mbr_signature));
-     memcpy(edd.edd_info, boot_params.eddbuf, sizeof(edd.edd_info));
-     edd.mbr_signature_nr = boot_params.edd_mbr_sig_buf_entries;
-     edd.edd_info_nr = boot_params.eddbuf_entries;
-}
-#else
-static inline void copy_edd(void)
-{
-}
-#endif
-
-#ifdef CONFIG_KEXEC
-static void __init reserve_crashkernel(void)
-{
-        unsigned long long total_mem;
-        unsigned long long crash_size, crash_base;
-        int ret;
-
-        total_mem = ((unsigned long long)max_low_pfn - min_low_pfn) << PAGE_SHIFT;
-
-        ret = parse_crashkernel(boot_command_line, total_mem,
-                        &crash_size, &crash_base);
-        if (ret == 0 && crash_size) {
-                if (crash_base <= 0) {
-                        printk(KERN_INFO "crashkernel reservation failed - "
-                                        "you have to specify a base address\n");
-                        return;
-                }
-
-                if (reserve_bootmem(crash_base, crash_size,
-                                        BOOTMEM_EXCLUSIVE) < 0) {
-                        printk(KERN_INFO "crashkernel reservation failed - "
-                                        "memory is in use\n");
-                        return;
-                }
-
-                printk(KERN_INFO "Reserving %ldMB of memory at %ldMB "
-                                "for crashkernel (System RAM: %ldMB)\n",
-                                (unsigned long)(crash_size >> 20),
-                                (unsigned long)(crash_base >> 20),
-                                (unsigned long)(total_mem >> 20));
-                crashk_res.start = crash_base;
-                crashk_res.end   = crash_base + crash_size - 1;
-                insert_resource(&iomem_resource, &crashk_res);
-        }
-}
-#else
-static inline void __init reserve_crashkernel(void)
-{}
-#endif
-
-/* Overridden in paravirt.c if CONFIG_PARAVIRT */
-void __attribute__((weak)) __init memory_setup(void)
-{
-       machine_specific_memory_setup();
-}
-
-static void __init parse_setup_data(void)
-{
-        struct setup_data *data;
-        unsigned long pa_data;
-
-        if (boot_params.hdr.version < 0x0209)
-                return;
-        pa_data = boot_params.hdr.setup_data;
-        while (pa_data) {
-                data = early_ioremap(pa_data, PAGE_SIZE);
-                switch (data->type) {
-                default:
-                        break;
-                }
-#ifndef CONFIG_DEBUG_BOOT_PARAMS
-                free_early(pa_data, pa_data+sizeof(*data)+data->len);
-#endif
-                pa_data = data->next;
-                early_iounmap(data, PAGE_SIZE);
-        }
-}
-
-#ifdef CONFIG_PCI_MMCONFIG
-extern void __cpuinit fam10h_check_enable_mmcfg(void);
-extern void __init check_enable_amd_mmconf_dmi(void);
-#else
-void __cpuinit fam10h_check_enable_mmcfg(void)
-{
-}
-void __init check_enable_amd_mmconf_dmi(void)
-{
-}
-#endif
-
-/*
- * setup_arch - architecture-specific boot-time initializations
- *
- * Note: On x86_64, fixmaps are ready for use even before this is called.
- */
-void __init setup_arch(char **cmdline_p)
-{
-        unsigned i;
-
-        printk(KERN_INFO "Command line: %s\n", boot_command_line);
-
-        ROOT_DEV = old_decode_dev(boot_params.hdr.root_dev);
-        screen_info = boot_params.screen_info;
-        edid_info = boot_params.edid_info;
-        saved_video_mode = boot_params.hdr.vid_mode;
-        bootloader_type = boot_params.hdr.type_of_loader;
-
-#ifdef CONFIG_BLK_DEV_RAM
-        rd_image_start = boot_params.hdr.ram_size & RAMDISK_IMAGE_START_MASK;
-        rd_prompt = ((boot_params.hdr.ram_size & RAMDISK_PROMPT_FLAG) != 0);
-        rd_doload = ((boot_params.hdr.ram_size & RAMDISK_LOAD_FLAG) != 0);
-#endif
-#ifdef CONFIG_EFI
-        if (!strncmp((char *)&boot_params.efi_info.efi_loader_signature,
-                     "EL64", 4))
-                efi_enabled = 1;
-#endif
-
-        ARCH_SETUP
-
-        memory_setup();
-        copy_edd();
-
-        if (!boot_params.hdr.root_flags)
-                root_mountflags &= ~MS_RDONLY;
-        init_mm.start_code = (unsigned long) &_text;
-        init_mm.end_code = (unsigned long) &_etext;
-        init_mm.end_data = (unsigned long) &_edata;
-        init_mm.brk = (unsigned long) &_end;
-
-        code_resource.start = virt_to_phys(&_text);
-        code_resource.end = virt_to_phys(&_etext)-1;
-        data_resource.start = virt_to_phys(&_etext);
-        data_resource.end = virt_to_phys(&_edata)-1;
-        bss_resource.start = virt_to_phys(&__bss_start);
-        bss_resource.end = virt_to_phys(&__bss_stop)-1;
-
-        early_identify_cpu(&boot_cpu_data);
-
-        strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
-        *cmdline_p = command_line;
-
-        parse_setup_data();
-
-        parse_early_param();
-
-#ifdef CONFIG_PROVIDE_OHCI1394_DMA_INIT
-        if (init_ohci1394_dma_early)
-                init_ohci1394_dma_on_all_controllers();
-#endif
-
-        finish_e820_parsing();
-
-        /* after parse_early_param, so could debug it */
-        insert_resource(&iomem_resource, &code_resource);
-        insert_resource(&iomem_resource, &data_resource);
-        insert_resource(&iomem_resource, &bss_resource);
-
-        early_gart_iommu_check();
-
-        e820_register_active_regions(0, 0, -1UL);
-        /*
-         * partially used pages are not usable - thus
-         * we are rounding upwards:
-         */
-        end_pfn = e820_end_of_ram();
-        /* update e820 for memory not covered by WB MTRRs */
-        mtrr_bp_init();
-        if (mtrr_trim_uncached_memory(end_pfn)) {
-                e820_register_active_regions(0, 0, -1UL);
-                end_pfn = e820_end_of_ram();
-        }
-
-        num_physpages = end_pfn;
-
-        check_efer();
-
-        max_pfn_mapped = init_memory_mapping(0, (max_pfn_mapped << PAGE_SHIFT));
-        if (efi_enabled)
-                efi_init();
-
-        vsmp_init();
-
-        dmi_scan_machine();
-
-        io_delay_init();
-
-#ifdef CONFIG_KVM_CLOCK
-        kvmclock_init();
-#endif
-
-#ifdef CONFIG_SMP
-        /* setup to use the early static init tables during kernel startup */
-        x86_cpu_to_apicid_early_ptr = (void *)x86_cpu_to_apicid_init;
-        x86_bios_cpu_apicid_early_ptr = (void *)x86_bios_cpu_apicid_init;
-#ifdef CONFIG_NUMA
-        x86_cpu_to_node_map_early_ptr = (void *)x86_cpu_to_node_map_init;
-#endif
-#endif
-
-#ifdef CONFIG_ACPI
-        /*
-         * Initialize the ACPI boot-time table parser (gets the RSDP and SDT).
-         * Call this early for SRAT node setup.
-         */
-        acpi_boot_table_init();
-#endif
-
-        /* How many end-of-memory variables you have, grandma! */
-        max_low_pfn = end_pfn;
-        max_pfn = end_pfn;
-        high_memory = (void *)__va(end_pfn * PAGE_SIZE - 1) + 1;
-
-        /* Remove active ranges so rediscovery with NUMA-awareness happens */
-        remove_all_active_ranges();
-
-#ifdef CONFIG_ACPI_NUMA
-        /*
-         * Parse SRAT to discover nodes.
-         */
-        acpi_numa_init();
-#endif
-
-#ifdef CONFIG_NUMA
-        numa_initmem_init(0, end_pfn);
-#else
-        contig_initmem_init(0, end_pfn);
-#endif
-
-        dma32_reserve_bootmem();
-
-#ifdef CONFIG_ACPI_SLEEP
-        /*
-         * Reserve low memory region for sleep support.
-         */
-       acpi_reserve_bootmem();
-#endif
-
-        if (efi_enabled)
-                efi_reserve_bootmem();
-
-       /*
-        * Find and reserve possible boot-time SMP configuration:
-        */
-        find_smp_config();
-#ifdef CONFIG_BLK_DEV_INITRD
-        if (boot_params.hdr.type_of_loader && boot_params.hdr.ramdisk_image) {
-                unsigned long ramdisk_image = boot_params.hdr.ramdisk_image;
-                unsigned long ramdisk_size  = boot_params.hdr.ramdisk_size;
-                unsigned long ramdisk_end   = ramdisk_image + ramdisk_size;
-                unsigned long end_of_mem    = end_pfn << PAGE_SHIFT;
-
-                if (ramdisk_end <= end_of_mem) {
-                        /*
-                         * don't need to reserve again, already reserved early
-                         * in x86_64_start_kernel, and early_res_to_bootmem
-                         * convert that to reserved in bootmem
-                         */
-                        initrd_start = ramdisk_image + PAGE_OFFSET;
-                        initrd_end = initrd_start+ramdisk_size;
-                } else {
-                        free_bootmem(ramdisk_image, ramdisk_size);
-                        printk(KERN_ERR "initrd extends beyond end of memory "
-                               "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
-                               ramdisk_end, end_of_mem);
-                        initrd_start = 0;
-                }
-        }
-#endif
-        reserve_crashkernel();
-
-        reserve_ibft_region();
-
-        paging_init();
-        map_vsyscall();
-
-        early_quirks();
-
-#ifdef CONFIG_ACPI
-        /*
-         * Read APIC and some other early information from ACPI tables.
-         */
-        acpi_boot_init();
-#endif
-
-        init_cpu_to_node();
-
-        /*
-         * get boot-time SMP configuration:
-         */
-        if (smp_found_config)
-                get_smp_config();
-        init_apic_mappings();
-        ioapic_init_mappings();
-
-        kvm_guest_init();
-
-        /*
-         * We trust e820 completely. No explicit ROM probing in memory.
-         */
-        e820_reserve_resources();
-        e820_mark_nosave_regions();
-
-        /* request I/O space for devices used on all i[345]86 PCs */
-        for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
-                request_resource(&ioport_resource, &standard_io_resources[i]);
-
-        e820_setup_gap();
-
-#ifdef CONFIG_VT
-#if defined(CONFIG_VGA_CONSOLE)
-        if (!efi_enabled || (efi_mem_type(0xa0000) != EFI_CONVENTIONAL_MEMORY))
-                conswitchp = &vga_con;
-#elif defined(CONFIG_DUMMY_CONSOLE)
-        conswitchp = &dummy_con;
-#endif
-#endif
-
-        /* do this before identify_cpu for boot cpu */
-        check_enable_amd_mmconf_dmi();
-}
-
-static int __cpuinit get_model_name(struct cpuinfo_x86 *c)
-{
-        unsigned int *v;
-
-        if (c->extended_cpuid_level < 0x80000004)
-                return 0;
-
-        v = (unsigned int *) c->x86_model_id;
-        cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
-        cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
-        cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
-        c->x86_model_id[48] = 0;
-        return 1;
-}
-
-
-static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
-{
-        unsigned int n, dummy, eax, ebx, ecx, edx;
-
-        n = c->extended_cpuid_level;
-
-        if (n >= 0x80000005) {
-                cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
-                printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), "
-                       "D cache %dK (%d bytes/line)\n",
-                       edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
-                c->x86_cache_size = (ecx>>24) + (edx>>24);
-                /* On K8 L1 TLB is inclusive, so don't count it */
-                c->x86_tlbsize = 0;
-        }
-
-        if (n >= 0x80000006) {
-                cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
-                ecx = cpuid_ecx(0x80000006);
-                c->x86_cache_size = ecx >> 16;
-                c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
-
-                printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
-                c->x86_cache_size, ecx & 0xFF);
-        }
-        if (n >= 0x80000008) {
-                cpuid(0x80000008, &eax, &dummy, &dummy, &dummy);
-                c->x86_virt_bits = (eax >> 8) & 0xff;
-                c->x86_phys_bits = eax & 0xff;
-        }
-}
-
-#ifdef CONFIG_NUMA
-static int __cpuinit nearby_node(int apicid)
-{
-        int i, node;
-
-        for (i = apicid - 1; i >= 0; i--) {
-                node = apicid_to_node[i];
-                if (node != NUMA_NO_NODE && node_online(node))
-                        return node;
-        }
-        for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
-                node = apicid_to_node[i];
-                if (node != NUMA_NO_NODE && node_online(node))
-                        return node;
-        }
-        return first_node(node_online_map); /* Shouldn't happen */
-}
-#endif
-
-/*
- * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
- * Assumes number of cores is a power of two.
- */
-static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c)
-{
-#ifdef CONFIG_SMP
-        unsigned bits;
-#ifdef CONFIG_NUMA
-        int cpu = smp_processor_id();
-        int node = 0;
-        unsigned apicid = hard_smp_processor_id();
-#endif
-        bits = c->x86_coreid_bits;
-
-        /* Low order bits define the core id (index of core in socket) */
-        c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
-        /* Convert the initial APIC ID into the socket ID */
-        c->phys_proc_id = c->initial_apicid >> bits;
-
-#ifdef CONFIG_NUMA
-        node = c->phys_proc_id;
-        if (apicid_to_node[apicid] != NUMA_NO_NODE)
-                node = apicid_to_node[apicid];
-        if (!node_online(node)) {
-                /* Two possibilities here:
-                   - The CPU is missing memory and no node was created.
-                   In that case try picking one from a nearby CPU
-                   - The APIC IDs differ from the HyperTransport node IDs
-                   which the K8 northbridge parsing fills in.
-                   Assume they are all increased by a constant offset,
-                   but in the same order as the HT nodeids.
-                   If that doesn't result in a usable node fall back to the
-                   path for the previous case.  */
-
-                int ht_nodeid = c->initial_apicid;
-
-                if (ht_nodeid >= 0 &&
-                    apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
-                        node = apicid_to_node[ht_nodeid];
-                /* Pick a nearby node */
-                if (!node_online(node))
-                        node = nearby_node(apicid);
-        }
-        numa_set_node(cpu, node);
-
-        printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
-#endif
-#endif
-}
-
-static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c)
-{
-#ifdef CONFIG_SMP
-        unsigned bits, ecx;
-
-        /* Multi core CPU? */
-        if (c->extended_cpuid_level < 0x80000008)
-                return;
-
-        ecx = cpuid_ecx(0x80000008);
-
-        c->x86_max_cores = (ecx & 0xff) + 1;
-
-        /* CPU telling us the core id bits shift? */
-        bits = (ecx >> 12) & 0xF;
-
-        /* Otherwise recompute */
-        if (bits == 0) {
-                while ((1 << bits) < c->x86_max_cores)
-                        bits++;
-        }
-
-        c->x86_coreid_bits = bits;
-
-#endif
-}
-
-#define ENABLE_C1E_MASK         0x18000000
-#define CPUID_PROCESSOR_SIGNATURE       1
-#define CPUID_XFAM              0x0ff00000
-#define CPUID_XFAM_K8           0x00000000
-#define CPUID_XFAM_10H          0x00100000
-#define CPUID_XFAM_11H          0x00200000
-#define CPUID_XMOD              0x000f0000
-#define CPUID_XMOD_REV_F        0x00040000
-
-/* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
-static __cpuinit int amd_apic_timer_broken(void)
-{
-        u32 lo, hi, eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
-
-        switch (eax & CPUID_XFAM) {
-        case CPUID_XFAM_K8:
-                if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)
-                        break;
-        case CPUID_XFAM_10H:
-        case CPUID_XFAM_11H:
-                rdmsr(MSR_K8_ENABLE_C1E, lo, hi);
-                if (lo & ENABLE_C1E_MASK)
-                        return 1;
-                break;
-        default:
-                /* err on the side of caution */
-                return 1;
-        }
-        return 0;
-}
-
-static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
-{
-        early_init_amd_mc(c);
-
-        /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
-        if (c->x86_power & (1<<8))
-                set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
-}
-
-static void __cpuinit init_amd(struct cpuinfo_x86 *c)
-{
-        unsigned level;
-
-#ifdef CONFIG_SMP
-        unsigned long value;
-
-        /*
-         * Disable TLB flush filter by setting HWCR.FFDIS on K8
-         * bit 6 of msr C001_0015
-         *
-         * Errata 63 for SH-B3 steppings
-         * Errata 122 for all steppings (F+ have it disabled by default)
-         */
-        if (c->x86 == 15) {
-                rdmsrl(MSR_K8_HWCR, value);
-                value |= 1 << 6;
-                wrmsrl(MSR_K8_HWCR, value);
-        }
-#endif
-
-        /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
-           3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
-        clear_cpu_cap(c, 0*32+31);
-
-        /* On C+ stepping K8 rep microcode works well for copy/memset */
-        level = cpuid_eax(1);
-        if (c->x86 == 15 && ((level >= 0x0f48 && level < 0x0f50) ||
-                             level >= 0x0f58))
-                set_cpu_cap(c, X86_FEATURE_REP_GOOD);
-        if (c->x86 == 0x10 || c->x86 == 0x11)
-                set_cpu_cap(c, X86_FEATURE_REP_GOOD);
-
-        /* Enable workaround for FXSAVE leak */
-        if (c->x86 >= 6)
-                set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);
-
-        level = get_model_name(c);
-        if (!level) {
-                switch (c->x86) {
-                case 15:
-                        /* Should distinguish Models here, but this is only
-                           a fallback anyways. */
-                        strcpy(c->x86_model_id, "Hammer");
-                        break;
-                }
-        }
-        display_cacheinfo(c);
-
-        /* Multi core CPU? */
-        if (c->extended_cpuid_level >= 0x80000008)
-                amd_detect_cmp(c);
-
-        if (c->extended_cpuid_level >= 0x80000006 &&
-                (cpuid_edx(0x80000006) & 0xf000))
-                num_cache_leaves = 4;
-        else
-                num_cache_leaves = 3;
-
-        if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x11)
-                set_cpu_cap(c, X86_FEATURE_K8);
-
-        /* MFENCE stops RDTSC speculation */
-        set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
-
-        if (c->x86 == 0x10)
-                fam10h_check_enable_mmcfg();
-
-        if (amd_apic_timer_broken())
-                disable_apic_timer = 1;
-
-        if (c == &boot_cpu_data && c->x86 >= 0xf && c->x86 <= 0x11) {
-                unsigned long long tseg;
-
-                /*
-                 * Split up direct mapping around the TSEG SMM area.
-                 * Don't do it for gbpages because there seems very little
-                 * benefit in doing so.
-                 */
-                if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg) &&
-                (tseg >> PMD_SHIFT) < (max_pfn_mapped >> (PMD_SHIFT-PAGE_SHIFT)))
-                        set_memory_4k((unsigned long)__va(tseg), 1);
-        }
-}
-
-void __cpuinit detect_ht(struct cpuinfo_x86 *c)
-{
-#ifdef CONFIG_SMP
-        u32 eax, ebx, ecx, edx;
-        int index_msb, core_bits;
-
-        cpuid(1, &eax, &ebx, &ecx, &edx);
-
-
-        if (!cpu_has(c, X86_FEATURE_HT))
-                return;
-        if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
-                goto out;
-
-        smp_num_siblings = (ebx & 0xff0000) >> 16;
-
-        if (smp_num_siblings == 1) {
-                printk(KERN_INFO  "CPU: Hyper-Threading is disabled\n");
-        } else if (smp_num_siblings > 1) {
-
-                if (smp_num_siblings > NR_CPUS) {
-                        printk(KERN_WARNING "CPU: Unsupported number of "
-                               "siblings %d", smp_num_siblings);
-                        smp_num_siblings = 1;
-                        return;
-                }
-
-                index_msb = get_count_order(smp_num_siblings);
-                c->phys_proc_id = phys_pkg_id(index_msb);
-
-                smp_num_siblings = smp_num_siblings / c->x86_max_cores;
-
-                index_msb = get_count_order(smp_num_siblings);
-
-                core_bits = get_count_order(c->x86_max_cores);
-
-                c->cpu_core_id = phys_pkg_id(index_msb) &
-                                               ((1 << core_bits) - 1);
-        }
-out:
-        if ((c->x86_max_cores * smp_num_siblings) > 1) {
-                printk(KERN_INFO  "CPU: Physical Processor ID: %d\n",
-                       c->phys_proc_id);
-                printk(KERN_INFO  "CPU: Processor Core ID: %d\n",
-                       c->cpu_core_id);
-        }
-
-#endif
-}
-
-/*
- * find out the number of processor cores on the die
- */
-static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
-{
-        unsigned int eax, t;
-
-        if (c->cpuid_level < 4)
-                return 1;
-
-        cpuid_count(4, 0, &eax, &t, &t, &t);
-
-        if (eax & 0x1f)
-                return ((eax >> 26) + 1);
-        else
-                return 1;
-}
-
-static void __cpuinit srat_detect_node(void)
-{
-#ifdef CONFIG_NUMA
-        unsigned node;
-        int cpu = smp_processor_id();
-        int apicid = hard_smp_processor_id();
-
-        /* Don't do the funky fallback heuristics the AMD version employs
-           for now. */
-        node = apicid_to_node[apicid];
-        if (node == NUMA_NO_NODE || !node_online(node))
-                node = first_node(node_online_map);
-        numa_set_node(cpu, node);
-
-        printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
-#endif
-}
-
-static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
-{
-        if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
-            (c->x86 == 0x6 && c->x86_model >= 0x0e))
-                set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
-}
-
-static void __cpuinit init_intel(struct cpuinfo_x86 *c)
-{
-        /* Cache sizes */
-        unsigned n;
-
-        init_intel_cacheinfo(c);
-        if (c->cpuid_level > 9) {
-                unsigned eax = cpuid_eax(10);
-                /* Check for version and the number of counters */
-                if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
-                        set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
-        }
-
-        if (cpu_has_ds) {
-                unsigned int l1, l2;
-                rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
-                if (!(l1 & (1<<11)))
-                        set_cpu_cap(c, X86_FEATURE_BTS);
-                if (!(l1 & (1<<12)))
-                        set_cpu_cap(c, X86_FEATURE_PEBS);
-        }
-
-
-        if (cpu_has_bts)
-                ds_init_intel(c);
-
-        n = c->extended_cpuid_level;
-        if (n >= 0x80000008) {
-                unsigned eax = cpuid_eax(0x80000008);
-                c->x86_virt_bits = (eax >> 8) & 0xff;
-                c->x86_phys_bits = eax & 0xff;
-                /* CPUID workaround for Intel 0F34 CPU */
-                if (c->x86_vendor == X86_VENDOR_INTEL &&
-                    c->x86 == 0xF && c->x86_model == 0x3 &&
-                    c->x86_mask == 0x4)
-                        c->x86_phys_bits = 36;
-        }
-
-        if (c->x86 == 15)
-                c->x86_cache_alignment = c->x86_clflush_size * 2;
-        if (c->x86 == 6)
-                set_cpu_cap(c, X86_FEATURE_REP_GOOD);
-        set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
-        c->x86_max_cores = intel_num_cpu_cores(c);
-
-        srat_detect_node();
-}
-
-static void __cpuinit early_init_centaur(struct cpuinfo_x86 *c)
-{
-        if (c->x86 == 0x6 && c->x86_model >= 0xf)
-                set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
-}
-
-static void __cpuinit init_centaur(struct cpuinfo_x86 *c)
-{
-        /* Cache sizes */
-        unsigned n;
-
-        n = c->extended_cpuid_level;
-        if (n >= 0x80000008) {
-                unsigned eax = cpuid_eax(0x80000008);
-                c->x86_virt_bits = (eax >> 8) & 0xff;
-                c->x86_phys_bits = eax & 0xff;
-        }
-
-        if (c->x86 == 0x6 && c->x86_model >= 0xf) {
-                c->x86_cache_alignment = c->x86_clflush_size * 2;
-                set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
-                set_cpu_cap(c, X86_FEATURE_REP_GOOD);
-        }
-        set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
-}
-
-static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
-{
-        char *v = c->x86_vendor_id;
-
-        if (!strcmp(v, "AuthenticAMD"))
-                c->x86_vendor = X86_VENDOR_AMD;
-        else if (!strcmp(v, "GenuineIntel"))
-                c->x86_vendor = X86_VENDOR_INTEL;
-        else if (!strcmp(v, "CentaurHauls"))
-                c->x86_vendor = X86_VENDOR_CENTAUR;
-        else
-                c->x86_vendor = X86_VENDOR_UNKNOWN;
-}
-
-/* Do some early cpuid on the boot CPU to get some parameter that are
-   needed before check_bugs. Everything advanced is in identify_cpu
-   below. */
-static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
-{
-        u32 tfms, xlvl;
-
-        c->loops_per_jiffy = loops_per_jiffy;
-        c->x86_cache_size = -1;
-        c->x86_vendor = X86_VENDOR_UNKNOWN;
-        c->x86_model = c->x86_mask = 0; /* So far unknown... */
-        c->x86_vendor_id[0] = '\0'; /* Unset */
-        c->x86_model_id[0] = '\0';  /* Unset */
-        c->x86_clflush_size = 64;
-        c->x86_cache_alignment = c->x86_clflush_size;
-        c->x86_max_cores = 1;
-        c->x86_coreid_bits = 0;
-        c->extended_cpuid_level = 0;
-        memset(&c->x86_capability, 0, sizeof c->x86_capability);
-
-        /* Get vendor name */
-        cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
-              (unsigned int *)&c->x86_vendor_id[0],
-              (unsigned int *)&c->x86_vendor_id[8],
-              (unsigned int *)&c->x86_vendor_id[4]);
-
-        get_cpu_vendor(c);
-
-        /* Initialize the standard set of capabilities */
-        /* Note that the vendor-specific code below might override */
-
-        /* Intel-defined flags: level 0x00000001 */
-        if (c->cpuid_level >= 0x00000001) {
-                __u32 misc;
-                cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4],
-                      &c->x86_capability[0]);
-                c->x86 = (tfms >> 8) & 0xf;
-                c->x86_model = (tfms >> 4) & 0xf;
-                c->x86_mask = tfms & 0xf;
-                if (c->x86 == 0xf)
-                        c->x86 += (tfms >> 20) & 0xff;
-                if (c->x86 >= 0x6)
-                        c->x86_model += ((tfms >> 16) & 0xF) << 4;
-                if (test_cpu_cap(c, X86_FEATURE_CLFLSH))
-                        c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
-        } else {
-                /* Have CPUID level 0 only - unheard of */
-                c->x86 = 4;
-        }
-
-        c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xff;
-#ifdef CONFIG_SMP
-        c->phys_proc_id = c->initial_apicid;
-#endif
-        /* AMD-defined flags: level 0x80000001 */
-        xlvl = cpuid_eax(0x80000000);
-        c->extended_cpuid_level = xlvl;
-        if ((xlvl & 0xffff0000) == 0x80000000) {
-                if (xlvl >= 0x80000001) {
-                        c->x86_capability[1] = cpuid_edx(0x80000001);
-                        c->x86_capability[6] = cpuid_ecx(0x80000001);
-                }
-                if (xlvl >= 0x80000004)
-                        get_model_name(c); /* Default name */
-        }
-
-        /* Transmeta-defined flags: level 0x80860001 */
-        xlvl = cpuid_eax(0x80860000);
-        if ((xlvl & 0xffff0000) == 0x80860000) {
-                /* Don't set x86_cpuid_level here for now to not confuse. */
-                if (xlvl >= 0x80860001)
-                        c->x86_capability[2] = cpuid_edx(0x80860001);
-        }
-
-        c->extended_cpuid_level = cpuid_eax(0x80000000);
-        if (c->extended_cpuid_level >= 0x80000007)
-                c->x86_power = cpuid_edx(0x80000007);
-
-        switch (c->x86_vendor) {
-        case X86_VENDOR_AMD:
-                early_init_amd(c);
-                break;
-        case X86_VENDOR_INTEL:
-                early_init_intel(c);
-                break;
-        case X86_VENDOR_CENTAUR:
-                early_init_centaur(c);
-                break;
-        }
-
-        validate_pat_support(c);
-}
-
-/*
- * This does the hard work of actually picking apart the CPU stuff...
- */
-void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
-{
-        int i;
-
-        early_identify_cpu(c);
-
-        init_scattered_cpuid_features(c);
-
-        c->apicid = phys_pkg_id(0);
-
-        /*
-         * Vendor-specific initialization.  In this section we
-         * canonicalize the feature flags, meaning if there are
-         * features a certain CPU supports which CPUID doesn't
-         * tell us, CPUID claiming incorrect flags, or other bugs,
-         * we handle them here.
-         *
-         * At the end of this section, c->x86_capability better
-         * indicate the features this CPU genuinely supports!
-         */
-        switch (c->x86_vendor) {
-        case X86_VENDOR_AMD:
-                init_amd(c);
-                break;
-
-        case X86_VENDOR_INTEL:
-                init_intel(c);
-                break;
-
-        case X86_VENDOR_CENTAUR:
-                init_centaur(c);
-                break;
-
-        case X86_VENDOR_UNKNOWN:
-        default:
-                display_cacheinfo(c);
-                break;
-        }
-
-        detect_ht(c);
-
-        /*
-         * On SMP, boot_cpu_data holds the common feature set between
-         * all CPUs; so make sure that we indicate which features are
-         * common between the CPUs.  The first time this routine gets
-         * executed, c == &boot_cpu_data.
-         */
-        if (c != &boot_cpu_data) {
-                /* AND the already accumulated flags with these */
-                for (i = 0; i < NCAPINTS; i++)
-                        boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
-        }
-
-        /* Clear all flags overriden by options */
-        for (i = 0; i < NCAPINTS; i++)
-                c->x86_capability[i] &= ~cleared_cpu_caps[i];
-
-#ifdef CONFIG_X86_MCE
-        mcheck_init(c);
-#endif
-        select_idle_routine(c);
-
-#ifdef CONFIG_NUMA
-        numa_add_cpu(smp_processor_id());
-#endif
-
-}
-
-void __cpuinit identify_boot_cpu(void)
-{
-        identify_cpu(&boot_cpu_data);
-}
-
-void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
-{
-        BUG_ON(c == &boot_cpu_data);
-        identify_cpu(c);
-        mtrr_ap_init();
-}
-
-static __init int setup_noclflush(char *arg)
-{
-        setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
-        return 1;
-}
-__setup("noclflush", setup_noclflush);
-
-void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
-{
-        if (c->x86_model_id[0])
-                printk(KERN_CONT "%s", c->x86_model_id);
-
-        if (c->x86_mask || c->cpuid_level >= 0)
-                printk(KERN_CONT " stepping %02x\n", c->x86_mask);
-        else
-                printk(KERN_CONT "\n");
-}
-
-static __init int setup_disablecpuid(char *arg)
-{
-        int bit;
-        if (get_option(&arg, &bit) && bit < NCAPINTS*32)
-                setup_clear_cpu_cap(bit);
-        else
-                return 0;
-        return 1;
-}
-__setup("clearcpuid=", setup_disablecpuid);
diff --git a/arch/x86/kernel/setup_percpu.c b/arch/x86/kernel/setup_percpu.c
new file mode 100644
index 000000000000..cac68430d31f
--- /dev/null
+++ b/arch/x86/kernel/setup_percpu.c
@@ -0,0 +1,399 @@
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/bootmem.h>
+#include <linux/percpu.h>
+#include <linux/kexec.h>
+#include <linux/crash_dump.h>
+#include <asm/smp.h>
+#include <asm/percpu.h>
+#include <asm/sections.h>
+#include <asm/processor.h>
+#include <asm/setup.h>
+#include <asm/topology.h>
+#include <asm/mpspec.h>
+#include <asm/apicdef.h>
+#include <asm/highmem.h>
+
+#ifdef CONFIG_X86_LOCAL_APIC
+unsigned int num_processors;
+unsigned disabled_cpus __cpuinitdata;
+/* Processor that is doing the boot up */
+unsigned int boot_cpu_physical_apicid = -1U;
+unsigned int max_physical_apicid;
+EXPORT_SYMBOL(boot_cpu_physical_apicid);
+
+/* Bitmask of physically existing CPUs */
+physid_mask_t phys_cpu_present_map;
+#endif
+
+/* map cpu index to physical APIC ID */
+DEFINE_EARLY_PER_CPU(u16, x86_cpu_to_apicid, BAD_APICID);
+DEFINE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid, BAD_APICID);
+EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
+EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
+
+#if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
+#define X86_64_NUMA     1
+
+/* map cpu index to node index */
+DEFINE_EARLY_PER_CPU(int, x86_cpu_to_node_map, NUMA_NO_NODE);
+EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_node_map);
+
+/* which logical CPUs are on which nodes */
+cpumask_t *node_to_cpumask_map;
+EXPORT_SYMBOL(node_to_cpumask_map);
+
+/* setup node_to_cpumask_map */
+static void __init setup_node_to_cpumask_map(void);
+
+#else
+static inline void setup_node_to_cpumask_map(void) { }
+#endif
+
+#if defined(CONFIG_HAVE_SETUP_PER_CPU_AREA) && defined(CONFIG_X86_SMP)
+/*
+ * Copy data used in early init routines from the initial arrays to the
+ * per cpu data areas.  These arrays then become expendable and the
+ * *_early_ptr's are zeroed indicating that the static arrays are gone.
+ */
+static void __init setup_per_cpu_maps(void)
+{
+        int cpu;
+
+        for_each_possible_cpu(cpu) {
+                per_cpu(x86_cpu_to_apicid, cpu) =
+                                early_per_cpu_map(x86_cpu_to_apicid, cpu);
+                per_cpu(x86_bios_cpu_apicid, cpu) =
+                                early_per_cpu_map(x86_bios_cpu_apicid, cpu);
+#ifdef X86_64_NUMA
+                per_cpu(x86_cpu_to_node_map, cpu) =
+                                early_per_cpu_map(x86_cpu_to_node_map, cpu);
+#endif
+        }
+
+        /* indicate the early static arrays will soon be gone */
+        early_per_cpu_ptr(x86_cpu_to_apicid) = NULL;
+        early_per_cpu_ptr(x86_bios_cpu_apicid) = NULL;
+#ifdef X86_64_NUMA
+        early_per_cpu_ptr(x86_cpu_to_node_map) = NULL;
+#endif
+}
+
+#ifdef CONFIG_HAVE_CPUMASK_OF_CPU_MAP
+cpumask_t *cpumask_of_cpu_map __read_mostly;
+EXPORT_SYMBOL(cpumask_of_cpu_map);
+
+/* requires nr_cpu_ids to be initialized */
+static void __init setup_cpumask_of_cpu(void)
+{
+        int i;
+
+        /* alloc_bootmem zeroes memory */
+        cpumask_of_cpu_map = alloc_bootmem_low(sizeof(cpumask_t) * nr_cpu_ids);
+        for (i = 0; i < nr_cpu_ids; i++)
+                cpu_set(i, cpumask_of_cpu_map[i]);
+}
+#else
+static inline void setup_cpumask_of_cpu(void) { }
+#endif
+
+#ifdef CONFIG_X86_32
+/*
+ * Great future not-so-futuristic plan: make i386 and x86_64 do it
+ * the same way
+ */
+unsigned long __per_cpu_offset[NR_CPUS] __read_mostly;
+EXPORT_SYMBOL(__per_cpu_offset);
+static inline void setup_cpu_pda_map(void) { }
+
+#elif !defined(CONFIG_SMP)
+static inline void setup_cpu_pda_map(void) { }
+
+#else /* CONFIG_SMP && CONFIG_X86_64 */
+
+/*
+ * Allocate cpu_pda pointer table and array via alloc_bootmem.
+ */
+static void __init setup_cpu_pda_map(void)
+{
+        char *pda;
+        struct x8664_pda **new_cpu_pda;
+        unsigned long size;
+        int cpu;
+
+        size = roundup(sizeof(struct x8664_pda), cache_line_size());
+
+        /* allocate cpu_pda array and pointer table */
+        {
+                unsigned long tsize = nr_cpu_ids * sizeof(void *);
+                unsigned long asize = size * (nr_cpu_ids - 1);
+
+                tsize = roundup(tsize, cache_line_size());
+                new_cpu_pda = alloc_bootmem(tsize + asize);
+                pda = (char *)new_cpu_pda + tsize;
+        }
+
+        /* initialize pointer table to static pda's */
+        for_each_possible_cpu(cpu) {
+                if (cpu == 0) {
+                        /* leave boot cpu pda in place */
+                        new_cpu_pda[0] = cpu_pda(0);
+                        continue;
+                }
+                new_cpu_pda[cpu] = (struct x8664_pda *)pda;
+                new_cpu_pda[cpu]->in_bootmem = 1;
+                pda += size;
+        }
+
+        /* point to new pointer table */
+        _cpu_pda = new_cpu_pda;
+}
+#endif
+
+/*
+ * Great future plan:
+ * Declare PDA itself and support (irqstack,tss,pgd) as per cpu data.
+ * Always point %gs to its beginning
+ */
+void __init setup_per_cpu_areas(void)
+{
+        ssize_t size = PERCPU_ENOUGH_ROOM;
+        char *ptr;
+        int cpu;
+
+        /* Setup cpu_pda map */
+        setup_cpu_pda_map();
+
+        /* Copy section for each CPU (we discard the original) */
+        size = PERCPU_ENOUGH_ROOM;
+        printk(KERN_INFO "PERCPU: Allocating %zd bytes of per cpu data\n",
+                          size);
+
+        for_each_possible_cpu(cpu) {
+#ifndef CONFIG_NEED_MULTIPLE_NODES
+                ptr = alloc_bootmem_pages(size);
+#else
+                int node = early_cpu_to_node(cpu);
+                if (!node_online(node) || !NODE_DATA(node)) {
+                        ptr = alloc_bootmem_pages(size);
+                        printk(KERN_INFO
+                               "cpu %d has no node %d or node-local memory\n",
+                                cpu, node);
+                }
+                else
+                        ptr = alloc_bootmem_pages_node(NODE_DATA(node), size);
+#endif
+                per_cpu_offset(cpu) = ptr - __per_cpu_start;
+                memcpy(ptr, __per_cpu_start, __per_cpu_end - __per_cpu_start);
+
+        }
+
+        printk(KERN_DEBUG "NR_CPUS: %d, nr_cpu_ids: %d, nr_node_ids %d\n",
+                NR_CPUS, nr_cpu_ids, nr_node_ids);
+
+        /* Setup percpu data maps */
+        setup_per_cpu_maps();
+
+        /* Setup node to cpumask map */
+        setup_node_to_cpumask_map();
+
+        /* Setup cpumask_of_cpu map */
+        setup_cpumask_of_cpu();
+}
+
+#endif
+
+#ifdef X86_64_NUMA
+
+/*
+ * Allocate node_to_cpumask_map based on number of available nodes
+ * Requires node_possible_map to be valid.
+ *
+ * Note: node_to_cpumask() is not valid until after this is done.
+ */
+static void __init setup_node_to_cpumask_map(void)
+{
+        unsigned int node, num = 0;
+        cpumask_t *map;
+
+        /* setup nr_node_ids if not done yet */
+        if (nr_node_ids == MAX_NUMNODES) {
+                for_each_node_mask(node, node_possible_map)
+                        num = node;
+                nr_node_ids = num + 1;
+        }
+
+        /* allocate the map */
+        map = alloc_bootmem_low(nr_node_ids * sizeof(cpumask_t));
+
+        Dprintk(KERN_DEBUG "Node to cpumask map at %p for %d nodes\n",
+                map, nr_node_ids);
+
+        /* node_to_cpumask() will now work */
+        node_to_cpumask_map = map;
+}
+
+void __cpuinit numa_set_node(int cpu, int node)
+{
+        int *cpu_to_node_map = early_per_cpu_ptr(x86_cpu_to_node_map);
+
+        if (cpu_pda(cpu) && node != NUMA_NO_NODE)
+                cpu_pda(cpu)->nodenumber = node;
+
+        if (cpu_to_node_map)
+                cpu_to_node_map[cpu] = node;
+
+        else if (per_cpu_offset(cpu))
+                per_cpu(x86_cpu_to_node_map, cpu) = node;
+
+        else
+                Dprintk(KERN_INFO "Setting node for non-present cpu %d\n", cpu);
+}
+
+void __cpuinit numa_clear_node(int cpu)
+{
+        numa_set_node(cpu, NUMA_NO_NODE);
+}
+
+#ifndef CONFIG_DEBUG_PER_CPU_MAPS
+
+void __cpuinit numa_add_cpu(int cpu)
+{
+        cpu_set(cpu, node_to_cpumask_map[early_cpu_to_node(cpu)]);
+}
+
+void __cpuinit numa_remove_cpu(int cpu)
+{
+        cpu_clear(cpu, node_to_cpumask_map[cpu_to_node(cpu)]);
+}
+
+#else /* CONFIG_DEBUG_PER_CPU_MAPS */
+
+/*
+ * --------- debug versions of the numa functions ---------
+ */
+static void __cpuinit numa_set_cpumask(int cpu, int enable)
+{
+        int node = cpu_to_node(cpu);
+        cpumask_t *mask;
+        char buf[64];
+
+        if (node_to_cpumask_map == NULL) {
+                printk(KERN_ERR "node_to_cpumask_map NULL\n");
+                dump_stack();
+                return;
+        }
+
+        mask = &node_to_cpumask_map[node];
+        if (enable)
+                cpu_set(cpu, *mask);
+        else
+                cpu_clear(cpu, *mask);
+
+        cpulist_scnprintf(buf, sizeof(buf), *mask);
+        printk(KERN_DEBUG "%s cpu %d node %d: mask now %s\n",
+                enable? "numa_add_cpu":"numa_remove_cpu", cpu, node, buf);
+ }
+
+void __cpuinit numa_add_cpu(int cpu)
+{
+        numa_set_cpumask(cpu, 1);
+}
+
+void __cpuinit numa_remove_cpu(int cpu)
+{
+        numa_set_cpumask(cpu, 0);
+}
+
+int cpu_to_node(int cpu)
+{
+        if (early_per_cpu_ptr(x86_cpu_to_node_map)) {
+                printk(KERN_WARNING
+                        "cpu_to_node(%d): usage too early!\n", cpu);
+                dump_stack();
+                return early_per_cpu_ptr(x86_cpu_to_node_map)[cpu];
+        }
+        return per_cpu(x86_cpu_to_node_map, cpu);
+}
+EXPORT_SYMBOL(cpu_to_node);
+
+/*
+ * Same function as cpu_to_node() but used if called before the
+ * per_cpu areas are setup.
+ */
+int early_cpu_to_node(int cpu)
+{
+        if (early_per_cpu_ptr(x86_cpu_to_node_map))
+                return early_per_cpu_ptr(x86_cpu_to_node_map)[cpu];
+
+        if (!per_cpu_offset(cpu)) {
+                printk(KERN_WARNING
+                        "early_cpu_to_node(%d): no per_cpu area!\n", cpu);
+                dump_stack();
+                return NUMA_NO_NODE;
+        }
+        return per_cpu(x86_cpu_to_node_map, cpu);
+}
+
+
+/* empty cpumask */
+static const cpumask_t cpu_mask_none;
+
+/*
+ * Returns a pointer to the bitmask of CPUs on Node 'node'.
+ */
+const cpumask_t *_node_to_cpumask_ptr(int node)
+{
+        if (node_to_cpumask_map == NULL) {
+                printk(KERN_WARNING
+                        "_node_to_cpumask_ptr(%d): no node_to_cpumask_map!\n",
+                        node);
+                dump_stack();
+                return (const cpumask_t *)&cpu_online_map;
+        }
+        if (node >= nr_node_ids) {
+                printk(KERN_WARNING
+                        "_node_to_cpumask_ptr(%d): node > nr_node_ids(%d)\n",
+                        node, nr_node_ids);
+                dump_stack();
+                return &cpu_mask_none;
+        }
+        return &node_to_cpumask_map[node];
+}
+EXPORT_SYMBOL(_node_to_cpumask_ptr);
+
+/*
+ * Returns a bitmask of CPUs on Node 'node'.
+ *
+ * Side note: this function creates the returned cpumask on the stack
+ * so with a high NR_CPUS count, excessive stack space is used.  The
+ * node_to_cpumask_ptr function should be used whenever possible.
+ */
+cpumask_t node_to_cpumask(int node)
+{
+        if (node_to_cpumask_map == NULL) {
+                printk(KERN_WARNING
+                        "node_to_cpumask(%d): no node_to_cpumask_map!\n", node);
+                dump_stack();
+                return cpu_online_map;
+        }
+        if (node >= nr_node_ids) {
+                printk(KERN_WARNING
+                        "node_to_cpumask(%d): node > nr_node_ids(%d)\n",
+                        node, nr_node_ids);
+                dump_stack();
+                return cpu_mask_none;
+        }
+        return node_to_cpumask_map[node];
+}
+EXPORT_SYMBOL(node_to_cpumask);
+
+/*
+ * --------- end of debug versions of the numa functions ---------
+ */
+
+#endif /* CONFIG_DEBUG_PER_CPU_MAPS */
+
+#endif /* X86_64_NUMA */
+
diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
index 3e1cecedde42..f35c2d8016ac 100644
--- a/arch/x86/kernel/smpboot.c
+++ b/arch/x86/kernel/smpboot.c
@@ -59,7 +59,6 @@
 #include <asm/pgtable.h>
 #include <asm/tlbflush.h>
 #include <asm/mtrr.h>
-#include <asm/nmi.h>
 #include <asm/vmi.h>
 #include <asm/genapic.h>
 #include <linux/mc146818rtc.h>
@@ -68,22 +67,6 @@
 #include <mach_wakecpu.h>
 #include <smpboot_hooks.h>
 
-/*
- * FIXME: For x86_64, those are defined in other files. But moving them here,
- * would make the setup areas dependent on smp, which is a loss. When we
- * integrate apic between arches, we can probably do a better job, but
- * right now, they'll stay here -- glommer
- */
-
-/* which logical CPU number maps to which CPU (physical APIC ID) */
-u16 x86_cpu_to_apicid_init[NR_CPUS] __initdata =
-                        { [0 ... NR_CPUS-1] = BAD_APICID };
-void *x86_cpu_to_apicid_early_ptr;
-
-u16 x86_bios_cpu_apicid_init[NR_CPUS] __initdata
-                                = { [0 ... NR_CPUS-1] = BAD_APICID };
-void *x86_bios_cpu_apicid_early_ptr;
-
 #ifdef CONFIG_X86_32
 u8 apicid_2_node[MAX_APICID];
 static int low_mappings;
@@ -198,13 +181,12 @@ static void map_cpu_to_logical_apicid(void)
         map_cpu_to_node(cpu, node);
 }
 
-static void unmap_cpu_to_logical_apicid(int cpu)
+void numa_remove_cpu(int cpu)
 {
         cpu_2_logical_apicid[cpu] = BAD_APICID;
         unmap_cpu_to_node(cpu);
 }
 #else
-#define unmap_cpu_to_logical_apicid(cpu) do {} while (0)
 #define map_cpu_to_logical_apicid()  do {} while (0)
 #endif
 
@@ -346,15 +328,8 @@ static void __cpuinit start_secondary(void *unused)
          * smp_call_function().
          */
         lock_ipi_call_lock();
-#ifdef CONFIG_X86_64
-        spin_lock(&vector_lock);
-
-        /* Setup the per cpu irq handling data structures */
-        __setup_vector_irq(smp_processor_id());
-        /*
-         * Allow the master to continue.
-         */
-        spin_unlock(&vector_lock);
+#ifdef CONFIG_X86_IO_APIC
+        setup_vector_irq(smp_processor_id());
 #endif
         cpu_set(smp_processor_id(), cpu_online_map);
         unlock_ipi_call_lock();
@@ -366,31 +341,8 @@ static void __cpuinit start_secondary(void *unused)
         cpu_idle();
 }
 
-#ifdef CONFIG_X86_32
-/*
- * Everything has been set up for the secondary
- * CPUs - they just need to reload everything
- * from the task structure
- * This function must not return.
- */
-void __devinit initialize_secondary(void)
-{
-        /*
-         * We don't actually need to load the full TSS,
-         * basically just the stack pointer and the ip.
-         */
-
-        asm volatile(
-                "movl %0,%%esp\n\t"
-                "jmp *%1"
-                :
-                :"m" (current->thread.sp), "m" (current->thread.ip));
-}
-#endif
-
 static void __cpuinit smp_apply_quirks(struct cpuinfo_x86 *c)
 {
-#ifdef CONFIG_X86_32
         /*
          * Mask B, Pentium, but not Pentium MMX
          */
@@ -440,7 +392,6 @@ static void __cpuinit smp_apply_quirks(struct cpuinfo_x86 *c)
 
 valid_k7:
         ;
-#endif
 }
 
 static void __cpuinit smp_checks(void)
@@ -555,23 +506,6 @@ cpumask_t cpu_coregroup_map(int cpu)
                 return c->llc_shared_map;
 }
 
-#ifdef CONFIG_X86_32
-/*
- * We are called very early to get the low memory for the
- * SMP bootup trampoline page.
- */
-void __init smp_alloc_memory(void)
-{
-        trampoline_base = alloc_bootmem_low_pages(PAGE_SIZE);
-        /*
-         * Has to be in very low memory so we can execute
-         * real-mode AP code.
-         */
-        if (__pa(trampoline_base) >= 0x9F000)
-                BUG();
-}
-#endif
-
 static void impress_friends(void)
 {
         int cpu;
@@ -748,11 +682,7 @@ wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip)
          * target processor state.
          */
         startup_ipi_hook(phys_apicid, (unsigned long) start_secondary,
-#ifdef CONFIG_X86_64
-                         (unsigned long)init_rsp);
-#else
                          (unsigned long)stack_start.sp);
-#endif
 
         /*
          * Run STARTUP IPI loop.
@@ -832,6 +762,45 @@ static void __cpuinit do_fork_idle(struct work_struct *work)
         complete(&c_idle->done);
 }
 
+#ifdef CONFIG_X86_64
+/*
+ * Allocate node local memory for the AP pda.
+ *
+ * Must be called after the _cpu_pda pointer table is initialized.
+ */
+static int __cpuinit get_local_pda(int cpu)
+{
+        struct x8664_pda *oldpda, *newpda;
+        unsigned long size = sizeof(struct x8664_pda);
+        int node = cpu_to_node(cpu);
+
+        if (cpu_pda(cpu) && !cpu_pda(cpu)->in_bootmem)
+                return 0;
+
+        oldpda = cpu_pda(cpu);
+        newpda = kmalloc_node(size, GFP_ATOMIC, node);
+        if (!newpda) {
+                printk(KERN_ERR "Could not allocate node local PDA "
+                        "for CPU %d on node %d\n", cpu, node);
+
+                if (oldpda)
+                        return 0;       /* have a usable pda */
+                else
+                        return -1;
+        }
+
+        if (oldpda) {
+                memcpy(newpda, oldpda, size);
+                if (!after_bootmem)
+                        free_bootmem((unsigned long)oldpda, size);
+        }
+
+        newpda->in_bootmem = 0;
+        cpu_pda(cpu) = newpda;
+        return 0;
+}
+#endif /* CONFIG_X86_64 */
+
 static int __cpuinit do_boot_cpu(int apicid, int cpu)
 /*
  * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
@@ -848,28 +817,14 @@ static int __cpuinit do_boot_cpu(int apicid, int cpu)
                 .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done),
         };
         INIT_WORK(&c_idle.work, do_fork_idle);
-#ifdef CONFIG_X86_64
-        /* allocate memory for gdts of secondary cpus. Hotplug is considered */
-        if (!cpu_gdt_descr[cpu].address &&
-                !(cpu_gdt_descr[cpu].address = get_zeroed_page(GFP_KERNEL))) {
-                printk(KERN_ERR "Failed to allocate GDT for CPU %d\n", cpu);
-                return -1;
-        }
 
+#ifdef CONFIG_X86_64
         /* Allocate node local memory for AP pdas */
-        if (cpu_pda(cpu) == &boot_cpu_pda[cpu]) {
-                struct x8664_pda *newpda, *pda;
-                int node = cpu_to_node(cpu);
-                pda = cpu_pda(cpu);
-                newpda = kmalloc_node(sizeof(struct x8664_pda), GFP_ATOMIC,
-                                      node);
-                if (newpda) {
-                        memcpy(newpda, pda, sizeof(struct x8664_pda));
-                        cpu_pda(cpu) = newpda;
-                } else
-                        printk(KERN_ERR
-                "Could not allocate node local PDA for CPU %d on node %d\n",
-                                cpu, node);
+        if (cpu > 0) {
+                boot_error = get_local_pda(cpu);
+                if (boot_error)
+                        goto restore_state;
+                        /* if can't get pda memory, can't start cpu */
         }
 #endif
 
@@ -905,18 +860,15 @@ do_rest:
 #ifdef CONFIG_X86_32
         per_cpu(current_task, cpu) = c_idle.idle;
         init_gdt(cpu);
-        early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
-        c_idle.idle->thread.ip = (unsigned long) start_secondary;
         /* Stack for startup_32 can be just as for start_secondary onwards */
-        stack_start.sp = (void *) c_idle.idle->thread.sp;
         irq_ctx_init(cpu);
 #else
         cpu_pda(cpu)->pcurrent = c_idle.idle;
-        init_rsp = c_idle.idle->thread.sp;
-        load_sp0(&per_cpu(init_tss, cpu), &c_idle.idle->thread);
-        initial_code = (unsigned long)start_secondary;
         clear_tsk_thread_flag(c_idle.idle, TIF_FORK);
 #endif
+        early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
+        initial_code = (unsigned long)start_secondary;
+        stack_start.sp = (void *) c_idle.idle->thread.sp;
 
         /* start_ip had better be page-aligned! */
         start_ip = setup_trampoline();
@@ -987,13 +939,12 @@ do_rest:
                                 inquire_remote_apic(apicid);
                 }
         }
-
-        if (boot_error) {
-                /* Try to put things back the way they were before ... */
-                unmap_cpu_to_logical_apicid(cpu);
 #ifdef CONFIG_X86_64
-                clear_node_cpumask(cpu); /* was set by numa_add_cpu */
+restore_state:
 #endif
+        if (boot_error) {
+                /* Try to put things back the way they were before ... */
+                numa_remove_cpu(cpu); /* was set by numa_add_cpu */
                 cpu_clear(cpu, cpu_callout_map); /* was set by do_boot_cpu() */
                 cpu_clear(cpu, cpu_initialized); /* was set by cpu_init() */
                 cpu_clear(cpu, cpu_present_map);
@@ -1087,14 +1038,12 @@ static __init void disable_smp(void)
 {
         cpu_present_map = cpumask_of_cpu(0);
         cpu_possible_map = cpumask_of_cpu(0);
-#ifdef CONFIG_X86_32
         smpboot_clear_io_apic_irqs();
-#endif
+
         if (smp_found_config)
-                phys_cpu_present_map =
-                                physid_mask_of_physid(boot_cpu_physical_apicid);
+                physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
         else
-                phys_cpu_present_map = physid_mask_of_physid(0);
+                physid_set_mask_of_physid(0, &phys_cpu_present_map);
         map_cpu_to_logical_apicid();
         cpu_set(0, per_cpu(cpu_sibling_map, 0));
         cpu_set(0, per_cpu(cpu_core_map, 0));
@@ -1157,12 +1106,12 @@ static int __init smp_sanity_check(unsigned max_cpus)
          * If SMP should be disabled, then really disable it!
          */
         if (!max_cpus) {
-                printk(KERN_INFO "SMP mode deactivated,"
-                                 "forcing use of dummy APIC emulation.\n");
+                printk(KERN_INFO "SMP mode deactivated.\n");
                 smpboot_clear_io_apic();
-#ifdef CONFIG_X86_32
+
+                localise_nmi_watchdog();
+
                 connect_bsp_APIC();
-#endif
                 setup_local_APIC();
                 end_local_APIC_setup();
                 return -1;
@@ -1190,7 +1139,6 @@ static void __init smp_cpu_index_default(void)
 void __init native_smp_prepare_cpus(unsigned int max_cpus)
 {
         preempt_disable();
-        nmi_watchdog_default();
         smp_cpu_index_default();
         current_cpu_data = boot_cpu_data;
         cpu_callin_map = cpumask_of_cpu(0);
@@ -1217,9 +1165,8 @@ void __init native_smp_prepare_cpus(unsigned int max_cpus)
         }
         preempt_enable();
 
-#ifdef CONFIG_X86_32
         connect_bsp_APIC();
-#endif
+
         /*
          * Switch from PIC to APIC mode.
          */
@@ -1257,8 +1204,8 @@ void __init native_smp_prepare_boot_cpu(void)
         int me = smp_processor_id();
 #ifdef CONFIG_X86_32
         init_gdt(me);
-        switch_to_new_gdt();
 #endif
+        switch_to_new_gdt();
         /* already set me in cpu_online_map in boot_cpu_init() */
         cpu_set(me, cpu_callout_map);
         per_cpu(cpu_state, me) = CPU_ONLINE;
@@ -1278,23 +1225,6 @@ void __init native_smp_cpus_done(unsigned int max_cpus)
 
 #ifdef CONFIG_HOTPLUG_CPU
 
-#  ifdef CONFIG_X86_32
-void cpu_exit_clear(void)
-{
-        int cpu = raw_smp_processor_id();
-
-        idle_task_exit();
-
-        cpu_uninit();
-        irq_ctx_exit(cpu);
-
-        cpu_clear(cpu, cpu_callout_map);
-        cpu_clear(cpu, cpu_callin_map);
-
-        unmap_cpu_to_logical_apicid(cpu);
-}
-#  endif /* CONFIG_X86_32 */
-
 static void remove_siblinginfo(int cpu)
 {
         int sibling;
@@ -1348,12 +1278,20 @@ __init void prefill_possible_map(void)
         int i;
         int possible;
 
+        /* no processor from mptable or madt */
+        if (!num_processors)
+                num_processors = 1;
+
+#ifdef CONFIG_HOTPLUG_CPU
         if (additional_cpus == -1) {
                 if (disabled_cpus > 0)
                         additional_cpus = disabled_cpus;
                 else
                         additional_cpus = 0;
         }
+#else
+        additional_cpus = 0;
+#endif
         possible = num_processors + additional_cpus;
         if (possible > NR_CPUS)
                 possible = NR_CPUS;
@@ -1363,18 +1301,18 @@ __init void prefill_possible_map(void)
 
         for (i = 0; i < possible; i++)
                 cpu_set(i, cpu_possible_map);
+
+        nr_cpu_ids = possible;
 }
 
 static void __ref remove_cpu_from_maps(int cpu)
 {
         cpu_clear(cpu, cpu_online_map);
-#ifdef CONFIG_X86_64
         cpu_clear(cpu, cpu_callout_map);
         cpu_clear(cpu, cpu_callin_map);
         /* was set by cpu_init() */
         clear_bit(cpu, (unsigned long *)&cpu_initialized);
-        clear_node_cpumask(cpu);
-#endif
+        numa_remove_cpu(cpu);
 }
 
 int __cpu_disable(void)
diff --git a/arch/x86/kernel/summit_32.c b/arch/x86/kernel/summit_32.c
index ae751094eba9..d67ce5f044ba 100644
--- a/arch/x86/kernel/summit_32.c
+++ b/arch/x86/kernel/summit_32.c
@@ -36,7 +36,9 @@ static struct rio_table_hdr *rio_table_hdr __initdata;
 static struct scal_detail   *scal_devs[MAX_NUMNODES] __initdata;
 static struct rio_detail    *rio_devs[MAX_NUMNODES*4] __initdata;
 
+#ifndef CONFIG_X86_NUMAQ
 static int mp_bus_id_to_node[MAX_MP_BUSSES] __initdata;
+#endif
 
 static int __init setup_pci_node_map_for_wpeg(int wpeg_num, int last_bus)
 {
diff --git a/arch/x86/kernel/sys_i386_32.c b/arch/x86/kernel/sys_i386_32.c
index d2ab52cc1d6b..7066cb855a60 100644
--- a/arch/x86/kernel/sys_i386_32.c
+++ b/arch/x86/kernel/sys_i386_32.c
@@ -19,8 +19,8 @@
 #include <linux/utsname.h>
 #include <linux/ipc.h>
 
-#include <asm/uaccess.h>
-#include <asm/unistd.h>
+#include <linux/uaccess.h>
+#include <linux/unistd.h>
 
 asmlinkage long sys_mmap2(unsigned long addr, unsigned long len,
                           unsigned long prot, unsigned long flags,
@@ -103,7 +103,7 @@ asmlinkage int old_select(struct sel_arg_struct __user *arg)
  *
  * This is really horribly ugly.
  */
-asmlinkage int sys_ipc (uint call, int first, int second,
+asmlinkage int sys_ipc(uint call, int first, int second,
                         int third, void __user *ptr, long fifth)
 {
         int version, ret;
@@ -113,24 +113,24 @@ asmlinkage int sys_ipc (uint call, int first, int second,
 
         switch (call) {
         case SEMOP:
-                return sys_semtimedop (first, (struct sembuf __user *)ptr, second, NULL);
+                return sys_semtimedop(first, (struct sembuf __user *)ptr, second, NULL);
         case SEMTIMEDOP:
                 return sys_semtimedop(first, (struct sembuf __user *)ptr, second,
                                         (const struct timespec __user *)fifth);
 
         case SEMGET:
-                return sys_semget (first, second, third);
+                return sys_semget(first, second, third);
         case SEMCTL: {
                 union semun fourth;
                 if (!ptr)
                         return -EINVAL;
                 if (get_user(fourth.__pad, (void __user * __user *) ptr))
                         return -EFAULT;
-                return sys_semctl (first, second, third, fourth);
+                return sys_semctl(first, second, third, fourth);
         }
 
         case MSGSND:
-                return sys_msgsnd (first, (struct msgbuf __user *) ptr, 
+                return sys_msgsnd(first, (struct msgbuf __user *) ptr,
                                    second, third);
         case MSGRCV:
                 switch (version) {
@@ -138,45 +138,45 @@ asmlinkage int sys_ipc (uint call, int first, int second,
                         struct ipc_kludge tmp;
                         if (!ptr)
                                 return -EINVAL;
-                        
+
                         if (copy_from_user(&tmp,
-                                           (struct ipc_kludge __user *) ptr, 
-                                           sizeof (tmp)))
+                                           (struct ipc_kludge __user *) ptr,
+                                           sizeof(tmp)))
                                 return -EFAULT;
-                        return sys_msgrcv (first, tmp.msgp, second,
+                        return sys_msgrcv(first, tmp.msgp, second,
                                            tmp.msgtyp, third);
                 }
                 default:
-                        return sys_msgrcv (first,
+                        return sys_msgrcv(first,
                                            (struct msgbuf __user *) ptr,
                                            second, fifth, third);
                 }
         case MSGGET:
-                return sys_msgget ((key_t) first, second);
+                return sys_msgget((key_t) first, second);
         case MSGCTL:
-                return sys_msgctl (first, second, (struct msqid_ds __user *) ptr);
+                return sys_msgctl(first, second, (struct msqid_ds __user *) ptr);
 
         case SHMAT:
                 switch (version) {
                 default: {
                         ulong raddr;
-                        ret = do_shmat (first, (char __user *) ptr, second, &raddr);
+                        ret = do_shmat(first, (char __user *) ptr, second, &raddr);
                         if (ret)
                                 return ret;
-                        return put_user (raddr, (ulong __user *) third);
+                        return put_user(raddr, (ulong __user *) third);
                 }
                 case 1: /* iBCS2 emulator entry point */
                         if (!segment_eq(get_fs(), get_ds()))
                                 return -EINVAL;
                         /* The "(ulong *) third" is valid _only_ because of the kernel segment thing */
-                        return do_shmat (first, (char __user *) ptr, second, (ulong *) third);
+                        return do_shmat(first, (char __user *) ptr, second, (ulong *) third);
                 }
-        case SHMDT: 
-                return sys_shmdt ((char __user *)ptr);
+        case SHMDT:
+                return sys_shmdt((char __user *)ptr);
         case SHMGET:
-                return sys_shmget (first, second, third);
+                return sys_shmget(first, second, third);
         case SHMCTL:
-                return sys_shmctl (first, second,
+                return sys_shmctl(first, second,
                                    (struct shmid_ds __user *) ptr);
         default:
                 return -ENOSYS;
@@ -186,28 +186,28 @@ asmlinkage int sys_ipc (uint call, int first, int second,
 /*
  * Old cruft
  */
-asmlinkage int sys_uname(struct old_utsname __user * name)
+asmlinkage int sys_uname(struct old_utsname __user *name)
 {
         int err;
         if (!name)
                 return -EFAULT;
         down_read(&uts_sem);
-        err = copy_to_user(name, utsname(), sizeof (*name));
+        err = copy_to_user(name, utsname(), sizeof(*name));
         up_read(&uts_sem);
-        return err?-EFAULT:0;
+        return err? -EFAULT:0;
 }
 
-asmlinkage int sys_olduname(struct oldold_utsname __user * name)
+asmlinkage int sys_olduname(struct oldold_utsname __user *name)
 {
         int error;
 
         if (!name)
                 return -EFAULT;
-        if (!access_ok(VERIFY_WRITE,name,sizeof(struct oldold_utsname)))
+        if (!access_ok(VERIFY_WRITE, name, sizeof(struct oldold_utsname)))
                 return -EFAULT;
-  
-        down_read(&uts_sem);
-        
+
+        down_read(&uts_sem);
+
         error = __copy_to_user(&name->sysname, &utsname()->sysname,
                                __OLD_UTS_LEN);
         error |= __put_user(0, name->sysname + __OLD_UTS_LEN);
@@ -223,9 +223,9 @@ asmlinkage int sys_olduname(struct oldold_utsname __user * name)
         error |= __copy_to_user(&name->machine, &utsname()->machine,
                                 __OLD_UTS_LEN);
         error |= __put_user(0, name->machine + __OLD_UTS_LEN);
-        
+
         up_read(&uts_sem);
-        
+
         error = error ? -EFAULT : 0;
 
         return error;
@@ -241,6 +241,6 @@ int kernel_execve(const char *filename, char *const argv[], char *const envp[])
         long __res;
         asm volatile ("push %%ebx ; movl %2,%%ebx ; int $0x80 ; pop %%ebx"
         : "=a" (__res)
-        : "0" (__NR_execve),"ri" (filename),"c" (argv), "d" (envp) : "memory");
+        : "0" (__NR_execve), "ri" (filename), "c" (argv), "d" (envp) : "memory");
         return __res;
 }
diff --git a/arch/x86/kernel/time_32.c b/arch/x86/kernel/time_32.c
index 2ff21f398934..059ca6ee59b4 100644
--- a/arch/x86/kernel/time_32.c
+++ b/arch/x86/kernel/time_32.c
@@ -39,9 +39,6 @@
 
 #include "do_timer.h"
 
-unsigned int cpu_khz;   /* Detected as we calibrate the TSC */
-EXPORT_SYMBOL(cpu_khz);
-
 int timer_ack;
 
 unsigned long profile_pc(struct pt_regs *regs)
@@ -84,8 +81,7 @@ irqreturn_t timer_interrupt(int irq, void *dev_id)
         if (timer_ack) {
                 /*
                  * Subtle, when I/O APICs are used we have to ack timer IRQ
-                 * manually to reset the IRR bit for do_slow_gettimeoffset().
-                 * This will also deassert NMI lines for the watchdog if run
+                 * manually to deassert NMI lines for the watchdog if run
                  * on an 82489DX-based system.
                  */
                 spin_lock(&i8259A_lock);
diff --git a/arch/x86/kernel/time_64.c b/arch/x86/kernel/time_64.c
index c737849e2ef7..e3d49c553af2 100644
--- a/arch/x86/kernel/time_64.c
+++ b/arch/x86/kernel/time_64.c
@@ -56,7 +56,7 @@ static irqreturn_t timer_event_interrupt(int irq, void *dev_id)
 /* calibrate_cpu is used on systems with fixed rate TSCs to determine
  * processor frequency */
 #define TICK_COUNT 100000000
-unsigned long __init native_calculate_cpu_khz(void)
+unsigned long __init calibrate_cpu(void)
 {
         int tsc_start, tsc_now;
         int i, no_ctr_free;
@@ -116,23 +116,11 @@ void __init hpet_time_init(void)
 
 void __init time_init(void)
 {
-        tsc_calibrate();
-
-        cpu_khz = tsc_khz;
-        if (cpu_has(&boot_cpu_data, X86_FEATURE_CONSTANT_TSC) &&
-                (boot_cpu_data.x86_vendor == X86_VENDOR_AMD))
-                cpu_khz = calculate_cpu_khz();
-
-        if (unsynchronized_tsc())
-                mark_tsc_unstable("TSCs unsynchronized");
-
+        tsc_init();
         if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP))
                 vgetcpu_mode = VGETCPU_RDTSCP;
         else
                 vgetcpu_mode = VGETCPU_LSL;
 
-        printk(KERN_INFO "time.c: Detected %d.%03d MHz processor.\n",
-                cpu_khz / 1000, cpu_khz % 1000);
-        init_tsc_clocksource();
         late_time_init = choose_time_init();
 }
diff --git a/arch/x86/kernel/tlb_64.c b/arch/x86/kernel/tlb_64.c
index a1f07d793202..5039d0f097a2 100644
--- a/arch/x86/kernel/tlb_64.c
+++ b/arch/x86/kernel/tlb_64.c
@@ -15,6 +15,8 @@
 #include <asm/proto.h>
 #include <asm/apicdef.h>
 #include <asm/idle.h>
+#include <asm/uv/uv_hub.h>
+#include <asm/uv/uv_bau.h>
 
 #include <mach_ipi.h>
 /*
@@ -162,6 +164,9 @@ void native_flush_tlb_others(const cpumask_t *cpumaskp, struct mm_struct *mm,
         union smp_flush_state *f;
         cpumask_t cpumask = *cpumaskp;
 
+        if (is_uv_system() && uv_flush_tlb_others(&cpumask, mm, va))
+                return;
+
         /* Caller has disabled preemption */
         sender = smp_processor_id() % NUM_INVALIDATE_TLB_VECTORS;
         f = &per_cpu(flush_state, sender);
diff --git a/arch/x86/kernel/tlb_uv.c b/arch/x86/kernel/tlb_uv.c
new file mode 100644
index 000000000000..d0fbb7712ab0
--- /dev/null
+++ b/arch/x86/kernel/tlb_uv.c
@@ -0,0 +1,792 @@
+/*
+ *      SGI UltraViolet TLB flush routines.
+ *
+ *      (c) 2008 Cliff Wickman <cpw@sgi.com>, SGI.
+ *
+ *      This code is released under the GNU General Public License version 2 or
+ *      later.
+ */
+#include <linux/mc146818rtc.h>
+#include <linux/proc_fs.h>
+#include <linux/kernel.h>
+
+#include <asm/mmu_context.h>
+#include <asm/uv/uv_mmrs.h>
+#include <asm/uv/uv_hub.h>
+#include <asm/uv/uv_bau.h>
+#include <asm/genapic.h>
+#include <asm/idle.h>
+#include <asm/tsc.h>
+
+#include <mach_apic.h>
+
+static struct bau_control       **uv_bau_table_bases __read_mostly;
+static int                      uv_bau_retry_limit __read_mostly;
+
+/* position of pnode (which is nasid>>1): */
+static int                      uv_nshift __read_mostly;
+
+static unsigned long            uv_mmask __read_mostly;
+
+static DEFINE_PER_CPU(struct ptc_stats, ptcstats);
+static DEFINE_PER_CPU(struct bau_control, bau_control);
+
+/*
+ * Free a software acknowledge hardware resource by clearing its Pending
+ * bit. This will return a reply to the sender.
+ * If the message has timed out, a reply has already been sent by the
+ * hardware but the resource has not been released. In that case our
+ * clear of the Timeout bit (as well) will free the resource. No reply will
+ * be sent (the hardware will only do one reply per message).
+ */
+static void uv_reply_to_message(int resource,
+                                struct bau_payload_queue_entry *msg,
+                                struct bau_msg_status *msp)
+{
+        unsigned long dw;
+
+        dw = (1 << (resource + UV_SW_ACK_NPENDING)) | (1 << resource);
+        msg->replied_to = 1;
+        msg->sw_ack_vector = 0;
+        if (msp)
+                msp->seen_by.bits = 0;
+        uv_write_local_mmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, dw);
+}
+
+/*
+ * Do all the things a cpu should do for a TLB shootdown message.
+ * Other cpu's may come here at the same time for this message.
+ */
+static void uv_bau_process_message(struct bau_payload_queue_entry *msg,
+                                   int msg_slot, int sw_ack_slot)
+{
+        unsigned long this_cpu_mask;
+        struct bau_msg_status *msp;
+        int cpu;
+
+        msp = __get_cpu_var(bau_control).msg_statuses + msg_slot;
+        cpu = uv_blade_processor_id();
+        msg->number_of_cpus =
+            uv_blade_nr_online_cpus(uv_node_to_blade_id(numa_node_id()));
+        this_cpu_mask = 1UL << cpu;
+        if (msp->seen_by.bits & this_cpu_mask)
+                return;
+        atomic_or_long(&msp->seen_by.bits, this_cpu_mask);
+
+        if (msg->replied_to == 1)
+                return;
+
+        if (msg->address == TLB_FLUSH_ALL) {
+                local_flush_tlb();
+                __get_cpu_var(ptcstats).alltlb++;
+        } else {
+                __flush_tlb_one(msg->address);
+                __get_cpu_var(ptcstats).onetlb++;
+        }
+
+        __get_cpu_var(ptcstats).requestee++;
+
+        atomic_inc_short(&msg->acknowledge_count);
+        if (msg->number_of_cpus == msg->acknowledge_count)
+                uv_reply_to_message(sw_ack_slot, msg, msp);
+}
+
+/*
+ * Examine the payload queue on one distribution node to see
+ * which messages have not been seen, and which cpu(s) have not seen them.
+ *
+ * Returns the number of cpu's that have not responded.
+ */
+static int uv_examine_destination(struct bau_control *bau_tablesp, int sender)
+{
+        struct bau_payload_queue_entry *msg;
+        struct bau_msg_status *msp;
+        int count = 0;
+        int i;
+        int j;
+
+        for (msg = bau_tablesp->va_queue_first, i = 0; i < DEST_Q_SIZE;
+             msg++, i++) {
+                if ((msg->sending_cpu == sender) && (!msg->replied_to)) {
+                        msp = bau_tablesp->msg_statuses + i;
+                        printk(KERN_DEBUG
+                               "blade %d: address:%#lx %d of %d, not cpu(s): ",
+                               i, msg->address, msg->acknowledge_count,
+                               msg->number_of_cpus);
+                        for (j = 0; j < msg->number_of_cpus; j++) {
+                                if (!((1L << j) & msp->seen_by.bits)) {
+                                        count++;
+                                        printk("%d ", j);
+                                }
+                        }
+                        printk("\n");
+                }
+        }
+        return count;
+}
+
+/*
+ * Examine the payload queue on all the distribution nodes to see
+ * which messages have not been seen, and which cpu(s) have not seen them.
+ *
+ * Returns the number of cpu's that have not responded.
+ */
+static int uv_examine_destinations(struct bau_target_nodemask *distribution)
+{
+        int sender;
+        int i;
+        int count = 0;
+
+        sender = smp_processor_id();
+        for (i = 0; i < sizeof(struct bau_target_nodemask) * BITSPERBYTE; i++) {
+                if (!bau_node_isset(i, distribution))
+                        continue;
+                count += uv_examine_destination(uv_bau_table_bases[i], sender);
+        }
+        return count;
+}
+
+/*
+ * wait for completion of a broadcast message
+ *
+ * return COMPLETE, RETRY or GIVEUP
+ */
+static int uv_wait_completion(struct bau_desc *bau_desc,
+                              unsigned long mmr_offset, int right_shift)
+{
+        int exams = 0;
+        long destination_timeouts = 0;
+        long source_timeouts = 0;
+        unsigned long descriptor_status;
+
+        while ((descriptor_status = (((unsigned long)
+                uv_read_local_mmr(mmr_offset) >>
+                        right_shift) & UV_ACT_STATUS_MASK)) !=
+                        DESC_STATUS_IDLE) {
+                if (descriptor_status == DESC_STATUS_SOURCE_TIMEOUT) {
+                        source_timeouts++;
+                        if (source_timeouts > SOURCE_TIMEOUT_LIMIT)
+                                source_timeouts = 0;
+                        __get_cpu_var(ptcstats).s_retry++;
+                        return FLUSH_RETRY;
+                }
+                /*
+                 * spin here looking for progress at the destinations
+                 */
+                if (descriptor_status == DESC_STATUS_DESTINATION_TIMEOUT) {
+                        destination_timeouts++;
+                        if (destination_timeouts > DESTINATION_TIMEOUT_LIMIT) {
+                                /*
+                                 * returns number of cpus not responding
+                                 */
+                                if (uv_examine_destinations
+                                    (&bau_desc->distribution) == 0) {
+                                        __get_cpu_var(ptcstats).d_retry++;
+                                        return FLUSH_RETRY;
+                                }
+                                exams++;
+                                if (exams >= uv_bau_retry_limit) {
+                                        printk(KERN_DEBUG
+                                               "uv_flush_tlb_others");
+                                        printk("giving up on cpu %d\n",
+                                               smp_processor_id());
+                                        return FLUSH_GIVEUP;
+                                }
+                                /*
+                                 * delays can hang the simulator
+                                   udelay(1000);
+                                 */
+                                destination_timeouts = 0;
+                        }
+                }
+        }
+        return FLUSH_COMPLETE;
+}
+
+/**
+ * uv_flush_send_and_wait
+ *
+ * Send a broadcast and wait for a broadcast message to complete.
+ *
+ * The cpumaskp mask contains the cpus the broadcast was sent to.
+ *
+ * Returns 1 if all remote flushing was done. The mask is zeroed.
+ * Returns 0 if some remote flushing remains to be done. The mask is left
+ * unchanged.
+ */
+int uv_flush_send_and_wait(int cpu, int this_blade, struct bau_desc *bau_desc,
+                           cpumask_t *cpumaskp)
+{
+        int completion_status = 0;
+        int right_shift;
+        int tries = 0;
+        int blade;
+        int bit;
+        unsigned long mmr_offset;
+        unsigned long index;
+        cycles_t time1;
+        cycles_t time2;
+
+        if (cpu < UV_CPUS_PER_ACT_STATUS) {
+                mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_0;
+                right_shift = cpu * UV_ACT_STATUS_SIZE;
+        } else {
+                mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_1;
+                right_shift =
+                    ((cpu - UV_CPUS_PER_ACT_STATUS) * UV_ACT_STATUS_SIZE);
+        }
+        time1 = get_cycles();
+        do {
+                tries++;
+                index = (1UL << UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT) |
+                        cpu;
+                uv_write_local_mmr(UVH_LB_BAU_SB_ACTIVATION_CONTROL, index);
+                completion_status = uv_wait_completion(bau_desc, mmr_offset,
+                                        right_shift);
+        } while (completion_status == FLUSH_RETRY);
+        time2 = get_cycles();
+        __get_cpu_var(ptcstats).sflush += (time2 - time1);
+        if (tries > 1)
+                __get_cpu_var(ptcstats).retriesok++;
+
+        if (completion_status == FLUSH_GIVEUP) {
+                /*
+                 * Cause the caller to do an IPI-style TLB shootdown on
+                 * the cpu's, all of which are still in the mask.
+                 */
+                __get_cpu_var(ptcstats).ptc_i++;
+                return 0;
+        }
+
+        /*
+         * Success, so clear the remote cpu's from the mask so we don't
+         * use the IPI method of shootdown on them.
+         */
+        for_each_cpu_mask(bit, *cpumaskp) {
+                blade = uv_cpu_to_blade_id(bit);
+                if (blade == this_blade)
+                        continue;
+                cpu_clear(bit, *cpumaskp);
+        }
+        if (!cpus_empty(*cpumaskp))
+                return 0;
+        return 1;
+}
+
+/**
+ * uv_flush_tlb_others - globally purge translation cache of a virtual
+ * address or all TLB's
+ * @cpumaskp: mask of all cpu's in which the address is to be removed
+ * @mm: mm_struct containing virtual address range
+ * @va: virtual address to be removed (or TLB_FLUSH_ALL for all TLB's on cpu)
+ *
+ * This is the entry point for initiating any UV global TLB shootdown.
+ *
+ * Purges the translation caches of all specified processors of the given
+ * virtual address, or purges all TLB's on specified processors.
+ *
+ * The caller has derived the cpumaskp from the mm_struct and has subtracted
+ * the local cpu from the mask.  This function is called only if there
+ * are bits set in the mask. (e.g. flush_tlb_page())
+ *
+ * The cpumaskp is converted into a nodemask of the nodes containing
+ * the cpus.
+ *
+ * Returns 1 if all remote flushing was done.
+ * Returns 0 if some remote flushing remains to be done.
+ */
+int uv_flush_tlb_others(cpumask_t *cpumaskp, struct mm_struct *mm,
+                        unsigned long va)
+{
+        int i;
+        int bit;
+        int blade;
+        int cpu;
+        int this_blade;
+        int locals = 0;
+        struct bau_desc *bau_desc;
+
+        cpu = uv_blade_processor_id();
+        this_blade = uv_numa_blade_id();
+        bau_desc = __get_cpu_var(bau_control).descriptor_base;
+        bau_desc += UV_ITEMS_PER_DESCRIPTOR * cpu;
+
+        bau_nodes_clear(&bau_desc->distribution, UV_DISTRIBUTION_SIZE);
+
+        i = 0;
+        for_each_cpu_mask(bit, *cpumaskp) {
+                blade = uv_cpu_to_blade_id(bit);
+                BUG_ON(blade > (UV_DISTRIBUTION_SIZE - 1));
+                if (blade == this_blade) {
+                        locals++;
+                        continue;
+                }
+                bau_node_set(blade, &bau_desc->distribution);
+                i++;
+        }
+        if (i == 0) {
+                /*
+                 * no off_node flushing; return status for local node
+                 */
+                if (locals)
+                        return 0;
+                else
+                        return 1;
+        }
+        __get_cpu_var(ptcstats).requestor++;
+        __get_cpu_var(ptcstats).ntargeted += i;
+
+        bau_desc->payload.address = va;
+        bau_desc->payload.sending_cpu = smp_processor_id();
+
+        return uv_flush_send_and_wait(cpu, this_blade, bau_desc, cpumaskp);
+}
+
+/*
+ * The BAU message interrupt comes here. (registered by set_intr_gate)
+ * See entry_64.S
+ *
+ * We received a broadcast assist message.
+ *
+ * Interrupts may have been disabled; this interrupt could represent
+ * the receipt of several messages.
+ *
+ * All cores/threads on this node get this interrupt.
+ * The last one to see it does the s/w ack.
+ * (the resource will not be freed until noninterruptable cpus see this
+ *  interrupt; hardware will timeout the s/w ack and reply ERROR)
+ */
+void uv_bau_message_interrupt(struct pt_regs *regs)
+{
+        struct bau_payload_queue_entry *va_queue_first;
+        struct bau_payload_queue_entry *va_queue_last;
+        struct bau_payload_queue_entry *msg;
+        struct pt_regs *old_regs = set_irq_regs(regs);
+        cycles_t time1;
+        cycles_t time2;
+        int msg_slot;
+        int sw_ack_slot;
+        int fw;
+        int count = 0;
+        unsigned long local_pnode;
+
+        ack_APIC_irq();
+        exit_idle();
+        irq_enter();
+
+        time1 = get_cycles();
+
+        local_pnode = uv_blade_to_pnode(uv_numa_blade_id());
+
+        va_queue_first = __get_cpu_var(bau_control).va_queue_first;
+        va_queue_last = __get_cpu_var(bau_control).va_queue_last;
+
+        msg = __get_cpu_var(bau_control).bau_msg_head;
+        while (msg->sw_ack_vector) {
+                count++;
+                fw = msg->sw_ack_vector;
+                msg_slot = msg - va_queue_first;
+                sw_ack_slot = ffs(fw) - 1;
+
+                uv_bau_process_message(msg, msg_slot, sw_ack_slot);
+
+                msg++;
+                if (msg > va_queue_last)
+                        msg = va_queue_first;
+                __get_cpu_var(bau_control).bau_msg_head = msg;
+        }
+        if (!count)
+                __get_cpu_var(ptcstats).nomsg++;
+        else if (count > 1)
+                __get_cpu_var(ptcstats).multmsg++;
+
+        time2 = get_cycles();
+        __get_cpu_var(ptcstats).dflush += (time2 - time1);
+
+        irq_exit();
+        set_irq_regs(old_regs);
+}
+
+static void uv_enable_timeouts(void)
+{
+        int i;
+        int blade;
+        int last_blade;
+        int pnode;
+        int cur_cpu = 0;
+        unsigned long apicid;
+
+        last_blade = -1;
+        for_each_online_node(i) {
+                blade = uv_node_to_blade_id(i);
+                if (blade == last_blade)
+                        continue;
+                last_blade = blade;
+                apicid = per_cpu(x86_cpu_to_apicid, cur_cpu);
+                pnode = uv_blade_to_pnode(blade);
+                cur_cpu += uv_blade_nr_possible_cpus(i);
+        }
+}
+
+static void *uv_ptc_seq_start(struct seq_file *file, loff_t *offset)
+{
+        if (*offset < num_possible_cpus())
+                return offset;
+        return NULL;
+}
+
+static void *uv_ptc_seq_next(struct seq_file *file, void *data, loff_t *offset)
+{
+        (*offset)++;
+        if (*offset < num_possible_cpus())
+                return offset;
+        return NULL;
+}
+
+static void uv_ptc_seq_stop(struct seq_file *file, void *data)
+{
+}
+
+/*
+ * Display the statistics thru /proc
+ * data points to the cpu number
+ */
+static int uv_ptc_seq_show(struct seq_file *file, void *data)
+{
+        struct ptc_stats *stat;
+        int cpu;
+
+        cpu = *(loff_t *)data;
+
+        if (!cpu) {
+                seq_printf(file,
+                "# cpu requestor requestee one all sretry dretry ptc_i ");
+                seq_printf(file,
+                "sw_ack sflush dflush sok dnomsg dmult starget\n");
+        }
+        if (cpu < num_possible_cpus() && cpu_online(cpu)) {
+                stat = &per_cpu(ptcstats, cpu);
+                seq_printf(file, "cpu %d %ld %ld %ld %ld %ld %ld %ld ",
+                           cpu, stat->requestor,
+                           stat->requestee, stat->onetlb, stat->alltlb,
+                           stat->s_retry, stat->d_retry, stat->ptc_i);
+                seq_printf(file, "%lx %ld %ld %ld %ld %ld %ld\n",
+                           uv_read_global_mmr64(uv_blade_to_pnode
+                                        (uv_cpu_to_blade_id(cpu)),
+                                        UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE),
+                           stat->sflush, stat->dflush,
+                           stat->retriesok, stat->nomsg,
+                           stat->multmsg, stat->ntargeted);
+        }
+
+        return 0;
+}
+
+/*
+ *  0: display meaning of the statistics
+ * >0: retry limit
+ */
+static ssize_t uv_ptc_proc_write(struct file *file, const char __user *user,
+                                 size_t count, loff_t *data)
+{
+        long newmode;
+        char optstr[64];
+
+        if (count == 0 || count > sizeof(optstr))
+                return -EINVAL;
+        if (copy_from_user(optstr, user, count))
+                return -EFAULT;
+        optstr[count - 1] = '\0';
+        if (strict_strtoul(optstr, 10, &newmode) < 0) {
+                printk(KERN_DEBUG "%s is invalid\n", optstr);
+                return -EINVAL;
+        }
+
+        if (newmode == 0) {
+                printk(KERN_DEBUG "# cpu:      cpu number\n");
+                printk(KERN_DEBUG
+                "requestor:  times this cpu was the flush requestor\n");
+                printk(KERN_DEBUG
+                "requestee:  times this cpu was requested to flush its TLBs\n");
+                printk(KERN_DEBUG
+                "one:        times requested to flush a single address\n");
+                printk(KERN_DEBUG
+                "all:        times requested to flush all TLB's\n");
+                printk(KERN_DEBUG
+                "sretry:     number of retries of source-side timeouts\n");
+                printk(KERN_DEBUG
+                "dretry:     number of retries of destination-side timeouts\n");
+                printk(KERN_DEBUG
+                "ptc_i:      times UV fell through to IPI-style flushes\n");
+                printk(KERN_DEBUG
+                "sw_ack:     image of UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE\n");
+                printk(KERN_DEBUG
+                "sflush_us:  cycles spent in uv_flush_tlb_others()\n");
+                printk(KERN_DEBUG
+                "dflush_us:  cycles spent in handling flush requests\n");
+                printk(KERN_DEBUG "sok:        successes on retry\n");
+                printk(KERN_DEBUG "dnomsg:     interrupts with no message\n");
+                printk(KERN_DEBUG
+                "dmult:      interrupts with multiple messages\n");
+                printk(KERN_DEBUG "starget:    nodes targeted\n");
+        } else {
+                uv_bau_retry_limit = newmode;
+                printk(KERN_DEBUG "timeout retry limit:%d\n",
+                       uv_bau_retry_limit);
+        }
+
+        return count;
+}
+
+static const struct seq_operations uv_ptc_seq_ops = {
+        .start          = uv_ptc_seq_start,
+        .next           = uv_ptc_seq_next,
+        .stop           = uv_ptc_seq_stop,
+        .show           = uv_ptc_seq_show
+};
+
+static int uv_ptc_proc_open(struct inode *inode, struct file *file)
+{
+        return seq_open(file, &uv_ptc_seq_ops);
+}
+
+static const struct file_operations proc_uv_ptc_operations = {
+        .open           = uv_ptc_proc_open,
+        .read           = seq_read,
+        .write          = uv_ptc_proc_write,
+        .llseek         = seq_lseek,
+        .release        = seq_release,
+};
+
+static int __init uv_ptc_init(void)
+{
+        struct proc_dir_entry *proc_uv_ptc;
+
+        if (!is_uv_system())
+                return 0;
+
+        if (!proc_mkdir("sgi_uv", NULL))
+                return -EINVAL;
+
+        proc_uv_ptc = create_proc_entry(UV_PTC_BASENAME, 0444, NULL);
+        if (!proc_uv_ptc) {
+                printk(KERN_ERR "unable to create %s proc entry\n",
+                       UV_PTC_BASENAME);
+                remove_proc_entry("sgi_uv", NULL);
+                return -EINVAL;
+        }
+        proc_uv_ptc->proc_fops = &proc_uv_ptc_operations;
+        return 0;
+}
+
+/*
+ * begin the initialization of the per-blade control structures
+ */
+static struct bau_control * __init uv_table_bases_init(int blade, int node)
+{
+        int i;
+        int *ip;
+        struct bau_msg_status *msp;
+        struct bau_control *bau_tabp;
+
+        bau_tabp =
+            kmalloc_node(sizeof(struct bau_control), GFP_KERNEL, node);
+        BUG_ON(!bau_tabp);
+
+        bau_tabp->msg_statuses =
+            kmalloc_node(sizeof(struct bau_msg_status) *
+                         DEST_Q_SIZE, GFP_KERNEL, node);
+        BUG_ON(!bau_tabp->msg_statuses);
+
+        for (i = 0, msp = bau_tabp->msg_statuses; i < DEST_Q_SIZE; i++, msp++)
+                bau_cpubits_clear(&msp->seen_by, (int)
+                                  uv_blade_nr_possible_cpus(blade));
+
+        bau_tabp->watching =
+            kmalloc_node(sizeof(int) * DEST_NUM_RESOURCES, GFP_KERNEL, node);
+        BUG_ON(!bau_tabp->watching);
+
+        for (i = 0, ip = bau_tabp->watching; i < DEST_Q_SIZE; i++, ip++)
+                *ip = 0;
+
+        uv_bau_table_bases[blade] = bau_tabp;
+
+        return bau_tabp;
+}
+
+/*
+ * finish the initialization of the per-blade control structures
+ */
+static void __init
+uv_table_bases_finish(int blade, int node, int cur_cpu,
+                      struct bau_control *bau_tablesp,
+                      struct bau_desc *adp)
+{
+        struct bau_control *bcp;
+        int i;
+
+        for (i = cur_cpu; i < cur_cpu + uv_blade_nr_possible_cpus(blade); i++) {
+                bcp = (struct bau_control *)&per_cpu(bau_control, i);
+
+                bcp->bau_msg_head       = bau_tablesp->va_queue_first;
+                bcp->va_queue_first     = bau_tablesp->va_queue_first;
+                bcp->va_queue_last      = bau_tablesp->va_queue_last;
+                bcp->watching           = bau_tablesp->watching;
+                bcp->msg_statuses       = bau_tablesp->msg_statuses;
+                bcp->descriptor_base    = adp;
+        }
+}
+
+/*
+ * initialize the sending side's sending buffers
+ */
+static struct bau_desc * __init
+uv_activation_descriptor_init(int node, int pnode)
+{
+        int i;
+        unsigned long pa;
+        unsigned long m;
+        unsigned long n;
+        unsigned long mmr_image;
+        struct bau_desc *adp;
+        struct bau_desc *ad2;
+
+        adp = (struct bau_desc *)
+            kmalloc_node(16384, GFP_KERNEL, node);
+        BUG_ON(!adp);
+
+        pa = __pa((unsigned long)adp);
+        n = pa >> uv_nshift;
+        m = pa & uv_mmask;
+
+        mmr_image = uv_read_global_mmr64(pnode, UVH_LB_BAU_SB_DESCRIPTOR_BASE);
+        if (mmr_image) {
+                uv_write_global_mmr64(pnode, (unsigned long)
+                                      UVH_LB_BAU_SB_DESCRIPTOR_BASE,
+                                      (n << UV_DESC_BASE_PNODE_SHIFT | m));
+        }
+
+        for (i = 0, ad2 = adp; i < UV_ACTIVATION_DESCRIPTOR_SIZE; i++, ad2++) {
+                memset(ad2, 0, sizeof(struct bau_desc));
+                ad2->header.sw_ack_flag = 1;
+                ad2->header.base_dest_nodeid =
+                    uv_blade_to_pnode(uv_cpu_to_blade_id(0));
+                ad2->header.command = UV_NET_ENDPOINT_INTD;
+                ad2->header.int_both = 1;
+                /*
+                 * all others need to be set to zero:
+                 *   fairness chaining multilevel count replied_to
+                 */
+        }
+        return adp;
+}
+
+/*
+ * initialize the destination side's receiving buffers
+ */
+static struct bau_payload_queue_entry * __init
+uv_payload_queue_init(int node, int pnode, struct bau_control *bau_tablesp)
+{
+        struct bau_payload_queue_entry *pqp;
+        char *cp;
+
+        pqp = (struct bau_payload_queue_entry *) kmalloc_node(
+                (DEST_Q_SIZE + 1) * sizeof(struct bau_payload_queue_entry),
+                GFP_KERNEL, node);
+        BUG_ON(!pqp);
+
+        cp = (char *)pqp + 31;
+        pqp = (struct bau_payload_queue_entry *)(((unsigned long)cp >> 5) << 5);
+        bau_tablesp->va_queue_first = pqp;
+        uv_write_global_mmr64(pnode,
+                              UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST,
+                              ((unsigned long)pnode <<
+                               UV_PAYLOADQ_PNODE_SHIFT) |
+                              uv_physnodeaddr(pqp));
+        uv_write_global_mmr64(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL,
+                              uv_physnodeaddr(pqp));
+        bau_tablesp->va_queue_last = pqp + (DEST_Q_SIZE - 1);
+        uv_write_global_mmr64(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST,
+                              (unsigned long)
+                              uv_physnodeaddr(bau_tablesp->va_queue_last));
+        memset(pqp, 0, sizeof(struct bau_payload_queue_entry) * DEST_Q_SIZE);
+
+        return pqp;
+}
+
+/*
+ * Initialization of each UV blade's structures
+ */
+static int __init uv_init_blade(int blade, int node, int cur_cpu)
+{
+        int pnode;
+        unsigned long pa;
+        unsigned long apicid;
+        struct bau_desc *adp;
+        struct bau_payload_queue_entry *pqp;
+        struct bau_control *bau_tablesp;
+
+        bau_tablesp = uv_table_bases_init(blade, node);
+        pnode = uv_blade_to_pnode(blade);
+        adp = uv_activation_descriptor_init(node, pnode);
+        pqp = uv_payload_queue_init(node, pnode, bau_tablesp);
+        uv_table_bases_finish(blade, node, cur_cpu, bau_tablesp, adp);
+        /*
+         * the below initialization can't be in firmware because the
+         * messaging IRQ will be determined by the OS
+         */
+        apicid = per_cpu(x86_cpu_to_apicid, cur_cpu);
+        pa = uv_read_global_mmr64(pnode, UVH_BAU_DATA_CONFIG);
+        if ((pa & 0xff) != UV_BAU_MESSAGE) {
+                uv_write_global_mmr64(pnode, UVH_BAU_DATA_CONFIG,
+                                      ((apicid << 32) | UV_BAU_MESSAGE));
+        }
+        return 0;
+}
+
+/*
+ * Initialization of BAU-related structures
+ */
+static int __init uv_bau_init(void)
+{
+        int blade;
+        int node;
+        int nblades;
+        int last_blade;
+        int cur_cpu = 0;
+
+        if (!is_uv_system())
+                return 0;
+
+        uv_bau_retry_limit = 1;
+        uv_nshift = uv_hub_info->n_val;
+        uv_mmask = (1UL << uv_hub_info->n_val) - 1;
+        nblades = 0;
+        last_blade = -1;
+        for_each_online_node(node) {
+                blade = uv_node_to_blade_id(node);
+                if (blade == last_blade)
+                        continue;
+                last_blade = blade;
+                nblades++;
+        }
+        uv_bau_table_bases = (struct bau_control **)
+            kmalloc(nblades * sizeof(struct bau_control *), GFP_KERNEL);
+        BUG_ON(!uv_bau_table_bases);
+
+        last_blade = -1;
+        for_each_online_node(node) {
+                blade = uv_node_to_blade_id(node);
+                if (blade == last_blade)
+                        continue;
+                last_blade = blade;
+                uv_init_blade(blade, node, cur_cpu);
+                cur_cpu += uv_blade_nr_possible_cpus(blade);
+        }
+        set_intr_gate(UV_BAU_MESSAGE, uv_bau_message_intr1);
+        uv_enable_timeouts();
+
+        return 0;
+}
+__initcall(uv_bau_init);
+__initcall(uv_ptc_init);
diff --git a/arch/x86/kernel/trampoline.c b/arch/x86/kernel/trampoline.c
index abbf199adebb..1106fac6024d 100644
--- a/arch/x86/kernel/trampoline.c
+++ b/arch/x86/kernel/trampoline.c
@@ -2,7 +2,7 @@
 
 #include <asm/trampoline.h>
 
-/* ready for x86_64, no harm for x86, since it will overwrite after alloc */
+/* ready for x86_64 and x86 */
 unsigned char *trampoline_base = __va(TRAMPOLINE_BASE);
 
 /*
diff --git a/arch/x86/kernel/traps_32.c b/arch/x86/kernel/traps_32.c
index 08d752de4eee..8a768973c4f0 100644
--- a/arch/x86/kernel/traps_32.c
+++ b/arch/x86/kernel/traps_32.c
@@ -1,5 +1,6 @@
 /*
  *  Copyright (C) 1991, 1992  Linus Torvalds
+ *  Copyright (C) 2000, 2001, 2002 Andi Kleen, SuSE Labs
  *
  *  Pentium III FXSR, SSE support
  *      Gareth Hughes <gareth@valinux.com>, May 2000
@@ -60,8 +61,6 @@
 
 #include "mach_traps.h"
 
-int panic_on_unrecovered_nmi;
-
 DECLARE_BITMAP(used_vectors, NR_VECTORS);
 EXPORT_SYMBOL_GPL(used_vectors);
 
@@ -98,19 +97,22 @@ asmlinkage void alignment_check(void);
 asmlinkage void spurious_interrupt_bug(void);
 asmlinkage void machine_check(void);
 
+int panic_on_unrecovered_nmi;
 int kstack_depth_to_print = 24;
 static unsigned int code_bytes = 64;
+static int ignore_nmis;
+static int die_counter;
 
 void printk_address(unsigned long address, int reliable)
 {
 #ifdef CONFIG_KALLSYMS
-        char namebuf[KSYM_NAME_LEN];
         unsigned long offset = 0;
         unsigned long symsize;
         const char *symname;
-        char reliab[4] = "";
-        char *delim = ":";
         char *modname;
+        char *delim = ":";
+        char namebuf[KSYM_NAME_LEN];
+        char reliab[4] = "";
 
         symname = kallsyms_lookup(address, &symsize, &offset,
                                         &modname, namebuf);
@@ -130,22 +132,23 @@ void printk_address(unsigned long address, int reliable)
 #endif
 }
 
-static inline int valid_stack_ptr(struct thread_info *tinfo, void *p, unsigned size)
+static inline int valid_stack_ptr(struct thread_info *tinfo,
+                        void *p, unsigned int size)
 {
-        return  p > (void *)tinfo &&
-                p <= (void *)tinfo + THREAD_SIZE - size;
+        void *t = tinfo;
+        return  p > t && p <= t + THREAD_SIZE - size;
 }
 
 /* The form of the top of the frame on the stack */
 struct stack_frame {
-        struct stack_frame      *next_frame;
-        unsigned long           return_address;
+        struct stack_frame *next_frame;
+        unsigned long return_address;
 };
 
 static inline unsigned long
 print_context_stack(struct thread_info *tinfo,
-                    unsigned long *stack, unsigned long bp,
-                    const struct stacktrace_ops *ops, void *data)
+                unsigned long *stack, unsigned long bp,
+                const struct stacktrace_ops *ops, void *data)
 {
         struct stack_frame *frame = (struct stack_frame *)bp;
 
@@ -167,8 +170,6 @@ print_context_stack(struct thread_info *tinfo,
         return bp;
 }
 
-#define MSG(msg)                ops->warning(data, msg)
-
 void dump_trace(struct task_struct *task, struct pt_regs *regs,
                 unsigned long *stack, unsigned long bp,
                 const struct stacktrace_ops *ops, void *data)
@@ -178,7 +179,6 @@ void dump_trace(struct task_struct *task, struct pt_regs *regs,
 
         if (!stack) {
                 unsigned long dummy;
-
                 stack = &dummy;
                 if (task != current)
                         stack = (unsigned long *)task->thread.sp;
@@ -196,7 +196,7 @@ void dump_trace(struct task_struct *task, struct pt_regs *regs,
         }
 #endif
 
-        while (1) {
+        for (;;) {
                 struct thread_info *context;
 
                 context = (struct thread_info *)
@@ -248,10 +248,10 @@ static void print_trace_address(void *data, unsigned long addr, int reliable)
 }
 
 static const struct stacktrace_ops print_trace_ops = {
-        .warning                = print_trace_warning,
-        .warning_symbol         = print_trace_warning_symbol,
-        .stack                  = print_trace_stack,
-        .address                = print_trace_address,
+        .warning = print_trace_warning,
+        .warning_symbol = print_trace_warning_symbol,
+        .stack = print_trace_stack,
+        .address = print_trace_address,
 };
 
 static void
@@ -351,15 +351,14 @@ void show_registers(struct pt_regs *regs)
                 printk(KERN_EMERG "Code: ");
 
                 ip = (u8 *)regs->ip - code_prologue;
-                if (ip < (u8 *)PAGE_OFFSET ||
-                        probe_kernel_address(ip, c)) {
+                if (ip < (u8 *)PAGE_OFFSET || probe_kernel_address(ip, c)) {
                         /* try starting at EIP */
                         ip = (u8 *)regs->ip;
                         code_len = code_len - code_prologue + 1;
                 }
                 for (i = 0; i < code_len; i++, ip++) {
                         if (ip < (u8 *)PAGE_OFFSET ||
-                                probe_kernel_address(ip, c)) {
+                                        probe_kernel_address(ip, c)) {
                                 printk(" Bad EIP value.");
                                 break;
                         }
@@ -384,8 +383,6 @@ int is_valid_bugaddr(unsigned long ip)
         return ud2 == 0x0b0f;
 }
 
-static int die_counter;
-
 int __kprobes __die(const char *str, struct pt_regs *regs, long err)
 {
         unsigned short ss;
@@ -402,26 +399,22 @@ int __kprobes __die(const char *str, struct pt_regs *regs, long err)
         printk("DEBUG_PAGEALLOC");
 #endif
         printk("\n");
-
         if (notify_die(DIE_OOPS, str, regs, err,
-                        current->thread.trap_no, SIGSEGV) != NOTIFY_STOP) {
-
-                show_registers(regs);
-                /* Executive summary in case the oops scrolled away */
-                sp = (unsigned long) (&regs->sp);
-                savesegment(ss, ss);
-                if (user_mode(regs)) {
-                        sp = regs->sp;
-                        ss = regs->ss & 0xffff;
-                }
-                printk(KERN_EMERG "EIP: [<%08lx>] ", regs->ip);
-                print_symbol("%s", regs->ip);
-                printk(" SS:ESP %04x:%08lx\n", ss, sp);
+                        current->thread.trap_no, SIGSEGV) == NOTIFY_STOP)
+                return 1;
 
-                return 0;
+        show_registers(regs);
+        /* Executive summary in case the oops scrolled away */
+        sp = (unsigned long) (&regs->sp);
+        savesegment(ss, ss);
+        if (user_mode(regs)) {
+                sp = regs->sp;
+                ss = regs->ss & 0xffff;
         }
-
-        return 1;
+        printk(KERN_EMERG "EIP: [<%08lx>] ", regs->ip);
+        print_symbol("%s", regs->ip);
+        printk(" SS:ESP %04x:%08lx\n", ss, sp);
+        return 0;
 }
 
 /*
@@ -546,7 +539,7 @@ void do_##name(struct pt_regs *regs, long error_code)			\
 {                                                                       \
         trace_hardirqs_fixup();                                         \
         if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, signr)  \
-                                                == NOTIFY_STOP)         \
+                                                        == NOTIFY_STOP) \
                 return;                                                 \
         do_trap(trapnr, signr, str, 0, regs, error_code, NULL);         \
 }
@@ -562,7 +555,7 @@ void do_##name(struct pt_regs *regs, long error_code)			\
         info.si_code = sicode;                                          \
         info.si_addr = (void __user *)siaddr;                           \
         if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, signr)  \
-                                                == NOTIFY_STOP)         \
+                                                        == NOTIFY_STOP) \
                 return;                                                 \
         do_trap(trapnr, signr, str, 0, regs, error_code, &info);        \
 }
@@ -571,7 +564,7 @@ void do_##name(struct pt_regs *regs, long error_code)			\
 void do_##name(struct pt_regs *regs, long error_code)                   \
 {                                                                       \
         if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, signr)  \
-                                                == NOTIFY_STOP)         \
+                                                        == NOTIFY_STOP) \
                 return;                                                 \
         do_trap(trapnr, signr, str, 1, regs, error_code, NULL);         \
 }
@@ -586,27 +579,29 @@ void do_##name(struct pt_regs *regs, long error_code)			\
         info.si_addr = (void __user *)siaddr;                           \
         trace_hardirqs_fixup();                                         \
         if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, signr)  \
-                                                == NOTIFY_STOP)         \
+                                                        == NOTIFY_STOP) \
                 return;                                                 \
         do_trap(trapnr, signr, str, 1, regs, error_code, &info);        \
 }
 
-DO_VM86_ERROR_INFO(0, SIGFPE,  "divide error", divide_error, FPE_INTDIV, regs->ip)
+DO_VM86_ERROR_INFO(0, SIGFPE, "divide error", divide_error, FPE_INTDIV, regs->ip)
 #ifndef CONFIG_KPROBES
 DO_VM86_ERROR(3, SIGTRAP, "int3", int3)
 #endif
 DO_VM86_ERROR(4, SIGSEGV, "overflow", overflow)
 DO_VM86_ERROR(5, SIGSEGV, "bounds", bounds)
-DO_ERROR_INFO(6, SIGILL,  "invalid opcode", invalid_op, ILL_ILLOPN, regs->ip, 0)
-DO_ERROR(9, SIGFPE,  "coprocessor segment overrun", coprocessor_segment_overrun)
+DO_ERROR_INFO(6, SIGILL, "invalid opcode", invalid_op, ILL_ILLOPN, regs->ip, 0)
+DO_ERROR(9, SIGFPE, "coprocessor segment overrun", coprocessor_segment_overrun)
 DO_ERROR(10, SIGSEGV, "invalid TSS", invalid_TSS)
-DO_ERROR(11, SIGBUS,  "segment not present", segment_not_present)
-DO_ERROR(12, SIGBUS,  "stack segment", stack_segment)
+DO_ERROR(11, SIGBUS, "segment not present", segment_not_present)
+DO_ERROR(12, SIGBUS, "stack segment", stack_segment)
 DO_ERROR_INFO(17, SIGBUS, "alignment check", alignment_check, BUS_ADRALN, 0, 0)
 DO_ERROR_INFO(32, SIGILL, "iret exception", iret_error, ILL_BADSTK, 0, 1)
 
-void __kprobes do_general_protection(struct pt_regs *regs, long error_code)
+void __kprobes
+do_general_protection(struct pt_regs *regs, long error_code)
 {
+        struct task_struct *tsk;
         struct thread_struct *thread;
         struct tss_struct *tss;
         int cpu;
@@ -647,23 +642,24 @@ void __kprobes do_general_protection(struct pt_regs *regs, long error_code)
         if (regs->flags & X86_VM_MASK)
                 goto gp_in_vm86;
 
+        tsk = current;
         if (!user_mode(regs))
                 goto gp_in_kernel;
 
-        current->thread.error_code = error_code;
-        current->thread.trap_no = 13;
+        tsk->thread.error_code = error_code;
+        tsk->thread.trap_no = 13;
 
-        if (show_unhandled_signals && unhandled_signal(current, SIGSEGV) &&
-            printk_ratelimit()) {
+        if (show_unhandled_signals && unhandled_signal(tsk, SIGSEGV) &&
+                        printk_ratelimit()) {
                 printk(KERN_INFO
-                    "%s[%d] general protection ip:%lx sp:%lx error:%lx",
-                    current->comm, task_pid_nr(current),
-                    regs->ip, regs->sp, error_code);
+                        "%s[%d] general protection ip:%lx sp:%lx error:%lx",
+                        tsk->comm, task_pid_nr(tsk),
+                        regs->ip, regs->sp, error_code);
                 print_vma_addr(" in ", regs->ip);
                 printk("\n");
         }
 
-        force_sig(SIGSEGV, current);
+        force_sig(SIGSEGV, tsk);
         return;
 
 gp_in_vm86:
@@ -672,14 +668,15 @@ gp_in_vm86:
         return;
 
 gp_in_kernel:
-        if (!fixup_exception(regs)) {
-                current->thread.error_code = error_code;
-                current->thread.trap_no = 13;
-                if (notify_die(DIE_GPF, "general protection fault", regs,
+        if (fixup_exception(regs))
+                return;
+
+        tsk->thread.error_code = error_code;
+        tsk->thread.trap_no = 13;
+        if (notify_die(DIE_GPF, "general protection fault", regs,
                                 error_code, 13, SIGSEGV) == NOTIFY_STOP)
-                        return;
-                die("general protection fault", regs, error_code);
-        }
+                return;
+        die("general protection fault", regs, error_code);
 }
 
 static notrace __kprobes void
@@ -756,9 +753,9 @@ unknown_nmi_error(unsigned char reason, struct pt_regs *regs)
 
 static DEFINE_SPINLOCK(nmi_print_lock);
 
-void notrace __kprobes die_nmi(struct pt_regs *regs, const char *msg)
+void notrace __kprobes die_nmi(char *str, struct pt_regs *regs, int do_panic)
 {
-        if (notify_die(DIE_NMIWATCHDOG, msg, regs, 0, 2, SIGINT) == NOTIFY_STOP)
+        if (notify_die(DIE_NMIWATCHDOG, str, regs, 0, 2, SIGINT) == NOTIFY_STOP)
                 return;
 
         spin_lock(&nmi_print_lock);
@@ -767,10 +764,12 @@ void notrace __kprobes die_nmi(struct pt_regs *regs, const char *msg)
         * to get a message out:
         */
         bust_spinlocks(1);
-        printk(KERN_EMERG "%s", msg);
+        printk(KERN_EMERG "%s", str);
         printk(" on CPU%d, ip %08lx, registers:\n",
                 smp_processor_id(), regs->ip);
         show_registers(regs);
+        if (do_panic)
+                panic("Non maskable interrupt");
         console_silent();
         spin_unlock(&nmi_print_lock);
         bust_spinlocks(0);
@@ -790,14 +789,17 @@ void notrace __kprobes die_nmi(struct pt_regs *regs, const char *msg)
 static notrace __kprobes void default_do_nmi(struct pt_regs *regs)
 {
         unsigned char reason = 0;
+        int cpu;
+
+        cpu = smp_processor_id();
 
-        /* Only the BSP gets external NMIs from the system: */
-        if (!smp_processor_id())
+        /* Only the BSP gets external NMIs from the system. */
+        if (!cpu)
                 reason = get_nmi_reason();
 
         if (!(reason & 0xc0)) {
                 if (notify_die(DIE_NMI_IPI, "nmi_ipi", regs, reason, 2, SIGINT)
-                                                        == NOTIFY_STOP)
+                                                                == NOTIFY_STOP)
                         return;
 #ifdef CONFIG_X86_LOCAL_APIC
                 /*
@@ -806,7 +808,7 @@ static notrace __kprobes void default_do_nmi(struct pt_regs *regs)
                  */
                 if (nmi_watchdog_tick(regs, reason))
                         return;
-                if (!do_nmi_callback(regs, smp_processor_id()))
+                if (!do_nmi_callback(regs, cpu))
                         unknown_nmi_error(reason, regs);
 #else
                 unknown_nmi_error(reason, regs);
@@ -816,6 +818,8 @@ static notrace __kprobes void default_do_nmi(struct pt_regs *regs)
         }
         if (notify_die(DIE_NMI, "nmi", regs, reason, 2, SIGINT) == NOTIFY_STOP)
                 return;
+
+        /* AK: following checks seem to be broken on modern chipsets. FIXME */
         if (reason & 0x80)
                 mem_parity_error(reason, regs);
         if (reason & 0x40)
@@ -827,8 +831,6 @@ static notrace __kprobes void default_do_nmi(struct pt_regs *regs)
         reassert_nmi();
 }
 
-static int ignore_nmis;
-
 notrace __kprobes void do_nmi(struct pt_regs *regs, long error_code)
 {
         int cpu;
@@ -913,7 +915,7 @@ void __kprobes do_debug(struct pt_regs *regs, long error_code)
         tsk->thread.debugctlmsr = 0;
 
         if (notify_die(DIE_DEBUG, "debug", regs, condition, error_code,
-                                        SIGTRAP) == NOTIFY_STOP)
+                                                SIGTRAP) == NOTIFY_STOP)
                 return;
         /* It's safe to allow irq's after DR6 has been saved */
         if (regs->flags & X86_EFLAGS_IF)
@@ -974,9 +976,8 @@ clear_TF_reenable:
 void math_error(void __user *ip)
 {
         struct task_struct *task;
-        unsigned short cwd;
-        unsigned short swd;
         siginfo_t info;
+        unsigned short cwd, swd;
 
         /*
          * Save the info for the exception handler and clear the error.
@@ -995,7 +996,7 @@ void math_error(void __user *ip)
          * C1 reg you need in case of a stack fault, 0x040 is the stack
          * fault bit.  We should only be taking one exception at a time,
          * so if this combination doesn't produce any single exception,
-         * then we have a bad program that isn't syncronizing its FPU usage
+         * then we have a bad program that isn't synchronizing its FPU usage
          * and it will suffer the consequences since we won't be able to
          * fully reproduce the context of the exception
          */
@@ -1004,7 +1005,7 @@ void math_error(void __user *ip)
         switch (swd & ~cwd & 0x3f) {
         case 0x000: /* No unmasked exception */
                 return;
-        default:    /* Multiple exceptions */
+        default: /* Multiple exceptions */
                 break;
         case 0x001: /* Invalid Op */
                 /*
@@ -1040,8 +1041,8 @@ void do_coprocessor_error(struct pt_regs *regs, long error_code)
 static void simd_math_error(void __user *ip)
 {
         struct task_struct *task;
-        unsigned short mxcsr;
         siginfo_t info;
+        unsigned short mxcsr;
 
         /*
          * Save the info for the exception handler and clear the error.
@@ -1117,7 +1118,7 @@ void do_spurious_interrupt_bug(struct pt_regs *regs, long error_code)
 
 unsigned long patch_espfix_desc(unsigned long uesp, unsigned long kesp)
 {
-        struct desc_struct *gdt = __get_cpu_var(gdt_page).gdt;
+        struct desc_struct *gdt = get_cpu_gdt_table(smp_processor_id());
         unsigned long base = (kesp - uesp) & -THREAD_SIZE;
         unsigned long new_kesp = kesp - base;
         unsigned long lim_pages = (new_kesp | (THREAD_SIZE - 1)) >> PAGE_SHIFT;
@@ -1196,19 +1197,16 @@ void __init trap_init(void)
         early_iounmap(p, 4);
 #endif
 
-#ifdef CONFIG_X86_LOCAL_APIC
-        init_apic_mappings();
-#endif
-        set_trap_gate(0,  &divide_error);
-        set_intr_gate(1,  &debug);
-        set_intr_gate(2,  &nmi);
-        set_system_intr_gate(3, &int3); /* int3/4 can be called from all */
-        set_system_gate(4, &overflow);
-        set_trap_gate(5,  &bounds);
-        set_trap_gate(6,  &invalid_op);
-        set_trap_gate(7,  &device_not_available);
-        set_task_gate(8,  GDT_ENTRY_DOUBLEFAULT_TSS);
-        set_trap_gate(9,  &coprocessor_segment_overrun);
+        set_trap_gate(0, &divide_error);
+        set_intr_gate(1, &debug);
+        set_intr_gate(2, &nmi);
+        set_system_intr_gate(3, &int3); /* int3 can be called from all */
+        set_system_gate(4, &overflow); /* int4 can be called from all */
+        set_trap_gate(5, &bounds);
+        set_trap_gate(6, &invalid_op);
+        set_trap_gate(7, &device_not_available);
+        set_task_gate(8, GDT_ENTRY_DOUBLEFAULT_TSS);
+        set_trap_gate(9, &coprocessor_segment_overrun);
         set_trap_gate(10, &invalid_TSS);
         set_trap_gate(11, &segment_not_present);
         set_trap_gate(12, &stack_segment);
diff --git a/arch/x86/kernel/traps_64.c b/arch/x86/kernel/traps_64.c
index adff76ea97c4..2696a6837782 100644
--- a/arch/x86/kernel/traps_64.c
+++ b/arch/x86/kernel/traps_64.c
@@ -10,49 +10,49 @@
  * 'Traps.c' handles hardware traps and faults after we have saved some
  * state in 'entry.S'.
  */
-#include <linux/sched.h>
+#include <linux/moduleparam.h>
+#include <linux/interrupt.h>
+#include <linux/kallsyms.h>
+#include <linux/spinlock.h>
+#include <linux/kprobes.h>
+#include <linux/uaccess.h>
+#include <linux/utsname.h>
+#include <linux/kdebug.h>
 #include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/ptrace.h>
 #include <linux/string.h>
+#include <linux/unwind.h>
+#include <linux/delay.h>
 #include <linux/errno.h>
-#include <linux/ptrace.h>
+#include <linux/kexec.h>
+#include <linux/sched.h>
 #include <linux/timer.h>
-#include <linux/mm.h>
 #include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/spinlock.h>
-#include <linux/interrupt.h>
-#include <linux/kallsyms.h>
-#include <linux/module.h>
-#include <linux/moduleparam.h>
-#include <linux/nmi.h>
-#include <linux/kprobes.h>
-#include <linux/kexec.h>
-#include <linux/unwind.h>
-#include <linux/uaccess.h>
 #include <linux/bug.h>
-#include <linux/kdebug.h>
-#include <linux/utsname.h>
-
-#include <mach_traps.h>
+#include <linux/nmi.h>
+#include <linux/mm.h>
 
 #if defined(CONFIG_EDAC)
 #include <linux/edac.h>
 #endif
 
-#include <asm/system.h>
-#include <asm/io.h>
-#include <asm/atomic.h>
+#include <asm/stacktrace.h>
+#include <asm/processor.h>
 #include <asm/debugreg.h>
+#include <asm/atomic.h>
+#include <asm/system.h>
+#include <asm/unwind.h>
 #include <asm/desc.h>
 #include <asm/i387.h>
-#include <asm/processor.h>
-#include <asm/unwind.h>
+#include <asm/nmi.h>
 #include <asm/smp.h>
+#include <asm/io.h>
 #include <asm/pgalloc.h>
-#include <asm/pda.h>
 #include <asm/proto.h>
-#include <asm/nmi.h>
-#include <asm/stacktrace.h>
+#include <asm/pda.h>
+
+#include <mach_traps.h>
 
 asmlinkage void divide_error(void);
 asmlinkage void debug(void);
@@ -71,12 +71,15 @@ asmlinkage void general_protection(void);
 asmlinkage void page_fault(void);
 asmlinkage void coprocessor_error(void);
 asmlinkage void simd_coprocessor_error(void);
-asmlinkage void reserved(void);
 asmlinkage void alignment_check(void);
-asmlinkage void machine_check(void);
 asmlinkage void spurious_interrupt_bug(void);
+asmlinkage void machine_check(void);
 
+int panic_on_unrecovered_nmi;
+int kstack_depth_to_print = 12;
 static unsigned int code_bytes = 64;
+static int ignore_nmis;
+static int die_counter;
 
 static inline void conditional_sti(struct pt_regs *regs)
 {
@@ -100,34 +103,9 @@ static inline void preempt_conditional_cli(struct pt_regs *regs)
         dec_preempt_count();
 }
 
-int kstack_depth_to_print = 12;
-
 void printk_address(unsigned long address, int reliable)
 {
-#ifdef CONFIG_KALLSYMS
-        unsigned long offset = 0, symsize;
-        const char *symname;
-        char *modname;
-        char *delim = ":";
-        char namebuf[KSYM_NAME_LEN];
-        char reliab[4] = "";
-
-        symname = kallsyms_lookup(address, &symsize, &offset,
-                                        &modname, namebuf);
-        if (!symname) {
-                printk(" [<%016lx>]\n", address);
-                return;
-        }
-        if (!reliable)
-                strcpy(reliab, "? ");
-
-        if (!modname)
-                modname = delim = "";
-        printk(" [<%016lx>] %s%s%s%s%s+0x%lx/0x%lx\n",
-                address, reliab, delim, modname, delim, symname, offset, symsize);
-#else
-        printk(" [<%016lx>]\n", address);
-#endif
+        printk(" [<%016lx>] %s%pS\n", address, reliable ? "": "? ", (void *) address);
 }
 
 static unsigned long *in_exception_stack(unsigned cpu, unsigned long stack,
@@ -204,8 +182,6 @@ static unsigned long *in_exception_stack(unsigned cpu, unsigned long stack,
         return NULL;
 }
 
-#define MSG(txt) ops->warning(data, txt)
-
 /*
  * x86-64 can have up to three kernel stacks: 
  * process stack
@@ -232,11 +208,11 @@ struct stack_frame {
         unsigned long return_address;
 };
 
-
-static inline unsigned long print_context_stack(struct thread_info *tinfo,
-                                unsigned long *stack, unsigned long bp,
-                                const struct stacktrace_ops *ops, void *data,
-                                unsigned long *end)
+static inline unsigned long
+print_context_stack(struct thread_info *tinfo,
+                unsigned long *stack, unsigned long bp,
+                const struct stacktrace_ops *ops, void *data,
+                unsigned long *end)
 {
         struct stack_frame *frame = (struct stack_frame *)bp;
 
@@ -258,7 +234,7 @@ static inline unsigned long print_context_stack(struct thread_info *tinfo,
         return bp;
 }
 
-void dump_trace(struct task_struct *tsk, struct pt_regs *regs,
+void dump_trace(struct task_struct *task, struct pt_regs *regs,
                 unsigned long *stack, unsigned long bp,
                 const struct stacktrace_ops *ops, void *data)
 {
@@ -267,36 +243,34 @@ void dump_trace(struct task_struct *tsk, struct pt_regs *regs,
         unsigned used = 0;
         struct thread_info *tinfo;
 
-        if (!tsk)
-                tsk = current;
-        tinfo = task_thread_info(tsk);
+        if (!task)
+                task = current;
 
         if (!stack) {
                 unsigned long dummy;
                 stack = &dummy;
-                if (tsk && tsk != current)
-                        stack = (unsigned long *)tsk->thread.sp;
+                if (task && task != current)
+                        stack = (unsigned long *)task->thread.sp;
         }
 
 #ifdef CONFIG_FRAME_POINTER
         if (!bp) {
-                if (tsk == current) {
+                if (task == current) {
                         /* Grab bp right from our regs */
-                        asm("movq %%rbp, %0" : "=r" (bp):);
+                        asm("movq %%rbp, %0" : "=r" (bp) :);
                 } else {
                         /* bp is the last reg pushed by switch_to */
-                        bp = *(unsigned long *) tsk->thread.sp;
+                        bp = *(unsigned long *) task->thread.sp;
                 }
         }
 #endif
 
-
-
         /*
          * Print function call entries in all stacks, starting at the
          * current stack address. If the stacks consist of nested
          * exceptions
          */
+        tinfo = task_thread_info(task);
         for (;;) {
                 char *id;
                 unsigned long *estack_end;
@@ -381,18 +355,17 @@ static const struct stacktrace_ops print_trace_ops = {
         .address = print_trace_address,
 };
 
-void
-show_trace(struct task_struct *tsk, struct pt_regs *regs, unsigned long *stack,
-                unsigned long bp)
+void show_trace(struct task_struct *task, struct pt_regs *regs,
+                unsigned long *stack, unsigned long bp)
 {
         printk("\nCall Trace:\n");
-        dump_trace(tsk, regs, stack, bp, &print_trace_ops, NULL);
+        dump_trace(task, regs, stack, bp, &print_trace_ops, NULL);
         printk("\n");
 }
 
 static void
-_show_stack(struct task_struct *tsk, struct pt_regs *regs, unsigned long *sp,
-                                                        unsigned long bp)
+_show_stack(struct task_struct *task, struct pt_regs *regs,
+                unsigned long *sp, unsigned long bp)
 {
         unsigned long *stack;
         int i;
@@ -404,14 +377,14 @@ _show_stack(struct task_struct *tsk, struct pt_regs *regs, unsigned long *sp,
         // back trace for this cpu.
 
         if (sp == NULL) {
-                if (tsk)
-                        sp = (unsigned long *)tsk->thread.sp;
+                if (task)
+                        sp = (unsigned long *)task->thread.sp;
                 else
                         sp = (unsigned long *)&sp;
         }
 
         stack = sp;
-        for(i=0; i < kstack_depth_to_print; i++) {
+        for (i = 0; i < kstack_depth_to_print; i++) {
                 if (stack >= irqstack && stack <= irqstack_end) {
                         if (stack == irqstack_end) {
                                 stack = (unsigned long *) (irqstack_end[-1]);
@@ -426,12 +399,12 @@ _show_stack(struct task_struct *tsk, struct pt_regs *regs, unsigned long *sp,
                 printk(" %016lx", *stack++);
                 touch_nmi_watchdog();
         }
-        show_trace(tsk, regs, sp, bp);
+        show_trace(task, regs, sp, bp);
 }
 
-void show_stack(struct task_struct *tsk, unsigned long * sp)
+void show_stack(struct task_struct *task, unsigned long *sp)
 {
-        _show_stack(tsk, NULL, sp, 0);
+        _show_stack(task, NULL, sp, 0);
 }
 
 /*
@@ -439,8 +412,8 @@ void show_stack(struct task_struct *tsk, unsigned long * sp)
  */
 void dump_stack(void)
 {
-        unsigned long dummy;
         unsigned long bp = 0;
+        unsigned long stack;
 
 #ifdef CONFIG_FRAME_POINTER
         if (!bp)
@@ -452,7 +425,7 @@ void dump_stack(void)
                 init_utsname()->release,
                 (int)strcspn(init_utsname()->version, " "),
                 init_utsname()->version);
-        show_trace(NULL, NULL, &dummy, bp);
+        show_trace(NULL, NULL, &stack, bp);
 }
 
 EXPORT_SYMBOL(dump_stack);
@@ -463,12 +436,8 @@ void show_registers(struct pt_regs *regs)
         unsigned long sp;
         const int cpu = smp_processor_id();
         struct task_struct *cur = cpu_pda(cpu)->pcurrent;
-        u8 *ip;
-        unsigned int code_prologue = code_bytes * 43 / 64;
-        unsigned int code_len = code_bytes;
 
         sp = regs->sp;
-        ip = (u8 *) regs->ip - code_prologue;
         printk("CPU %d ", cpu);
         __show_regs(regs);
         printk("Process %s (pid: %d, threadinfo %p, task %p)\n",
@@ -479,15 +448,21 @@ void show_registers(struct pt_regs *regs)
          * time of the fault..
          */
         if (!user_mode(regs)) {
+                unsigned int code_prologue = code_bytes * 43 / 64;
+                unsigned int code_len = code_bytes;
                 unsigned char c;
+                u8 *ip;
+
                 printk("Stack: ");
                 _show_stack(NULL, regs, (unsigned long *)sp, regs->bp);
                 printk("\n");
 
                 printk(KERN_EMERG "Code: ");
+
+                ip = (u8 *)regs->ip - code_prologue;
                 if (ip < (u8 *)PAGE_OFFSET || probe_kernel_address(ip, c)) {
                         /* try starting at RIP */
-                        ip = (u8 *) regs->ip;
+                        ip = (u8 *)regs->ip;
                         code_len = code_len - code_prologue + 1;
                 }
                 for (i = 0; i < code_len; i++, ip++) {
@@ -503,7 +478,7 @@ void show_registers(struct pt_regs *regs)
                 }
         }
         printk("\n");
-}       
+}
 
 int is_valid_bugaddr(unsigned long ip)
 {
@@ -561,10 +536,9 @@ void __kprobes oops_end(unsigned long flags, struct pt_regs *regs, int signr)
         do_exit(signr);
 }
 
-int __kprobes __die(const char * str, struct pt_regs * regs, long err)
+int __kprobes __die(const char *str, struct pt_regs *regs, long err)
 {
-        static int die_counter;
-        printk(KERN_EMERG "%s: %04lx [%u] ", str, err & 0xffff,++die_counter);
+        printk(KERN_EMERG "%s: %04lx [%u] ", str, err & 0xffff, ++die_counter);
 #ifdef CONFIG_PREEMPT
         printk("PREEMPT ");
 #endif
@@ -575,8 +549,10 @@ int __kprobes __die(const char * str, struct pt_regs * regs, long err)
         printk("DEBUG_PAGEALLOC");
 #endif
         printk("\n");
-        if (notify_die(DIE_OOPS, str, regs, err, current->thread.trap_no, SIGSEGV) == NOTIFY_STOP)
+        if (notify_die(DIE_OOPS, str, regs, err,
+                        current->thread.trap_no, SIGSEGV) == NOTIFY_STOP)
                 return 1;
+
         show_registers(regs);
         add_taint(TAINT_DIE);
         /* Executive summary in case the oops scrolled away */
@@ -588,7 +564,7 @@ int __kprobes __die(const char * str, struct pt_regs * regs, long err)
         return 0;
 }
 
-void die(const char * str, struct pt_regs * regs, long err)
+void die(const char *str, struct pt_regs *regs, long err)
 {
         unsigned long flags = oops_begin();
 
@@ -605,8 +581,7 @@ die_nmi(char *str, struct pt_regs *regs, int do_panic)
 {
         unsigned long flags;
 
-        if (notify_die(DIE_NMIWATCHDOG, str, regs, 0, 2, SIGINT) ==
-            NOTIFY_STOP)
+        if (notify_die(DIE_NMIWATCHDOG, str, regs, 0, 2, SIGINT) == NOTIFY_STOP)
                 return;
 
         flags = oops_begin();
@@ -614,7 +589,9 @@ die_nmi(char *str, struct pt_regs *regs, int do_panic)
          * We are in trouble anyway, lets at least try
          * to get a message out.
          */
-        printk(str, smp_processor_id());
+        printk(KERN_EMERG "%s", str);
+        printk(" on CPU%d, ip %08lx, registers:\n",
+                smp_processor_id(), regs->ip);
         show_registers(regs);
         if (kexec_should_crash(current))
                 crash_kexec(regs);
@@ -626,44 +603,44 @@ die_nmi(char *str, struct pt_regs *regs, int do_panic)
         do_exit(SIGBUS);
 }
 
-static void __kprobes do_trap(int trapnr, int signr, char *str,
-                              struct pt_regs * regs, long error_code,
-                              siginfo_t *info)
+static void __kprobes
+do_trap(int trapnr, int signr, char *str, struct pt_regs *regs,
+        long error_code, siginfo_t *info)
 {
         struct task_struct *tsk = current;
 
-        if (user_mode(regs)) {
-                /*
-                 * We want error_code and trap_no set for userspace
-                 * faults and kernelspace faults which result in
-                 * die(), but not kernelspace faults which are fixed
-                 * up.  die() gives the process no chance to handle
-                 * the signal and notice the kernel fault information,
-                 * so that won't result in polluting the information
-                 * about previously queued, but not yet delivered,
-                 * faults.  See also do_general_protection below.
-                 */
-                tsk->thread.error_code = error_code;
-                tsk->thread.trap_no = trapnr;
-
-                if (show_unhandled_signals && unhandled_signal(tsk, signr) &&
-                    printk_ratelimit()) {
-                        printk(KERN_INFO
-                               "%s[%d] trap %s ip:%lx sp:%lx error:%lx",
-                               tsk->comm, tsk->pid, str,
-                               regs->ip, regs->sp, error_code);
-                        print_vma_addr(" in ", regs->ip);
-                        printk("\n");
-                }
+        if (!user_mode(regs))
+                goto kernel_trap;
 
-                if (info)
-                        force_sig_info(signr, info, tsk);
-                else
-                        force_sig(signr, tsk);
-                return;
+        /*
+         * We want error_code and trap_no set for userspace faults and
+         * kernelspace faults which result in die(), but not
+         * kernelspace faults which are fixed up.  die() gives the
+         * process no chance to handle the signal and notice the
+         * kernel fault information, so that won't result in polluting
+         * the information about previously queued, but not yet
+         * delivered, faults.  See also do_general_protection below.
+         */
+        tsk->thread.error_code = error_code;
+        tsk->thread.trap_no = trapnr;
+
+        if (show_unhandled_signals && unhandled_signal(tsk, signr) &&
+            printk_ratelimit()) {
+                printk(KERN_INFO
+                       "%s[%d] trap %s ip:%lx sp:%lx error:%lx",
+                       tsk->comm, tsk->pid, str,
+                       regs->ip, regs->sp, error_code);
+                print_vma_addr(" in ", regs->ip);
+                printk("\n");
         }
 
+        if (info)
+                force_sig_info(signr, info, tsk);
+        else
+                force_sig(signr, tsk);
+        return;
 
+kernel_trap:
         if (!fixup_exception(regs)) {
                 tsk->thread.error_code = error_code;
                 tsk->thread.trap_no = trapnr;
@@ -673,41 +650,39 @@ static void __kprobes do_trap(int trapnr, int signr, char *str,
 }
 
 #define DO_ERROR(trapnr, signr, str, name) \
-asmlinkage void do_##name(struct pt_regs * regs, long error_code) \
-{ \
-        if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, signr) \
-                                                        == NOTIFY_STOP) \
-                return; \
+asmlinkage void do_##name(struct pt_regs * regs, long error_code)       \
+{                                                                       \
+        if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, signr)  \
+                                                        == NOTIFY_STOP) \
+                return;                                                 \
         conditional_sti(regs);                                          \
-        do_trap(trapnr, signr, str, regs, error_code, NULL); \
+        do_trap(trapnr, signr, str, regs, error_code, NULL);            \
 }
 
-#define DO_ERROR_INFO(trapnr, signr, str, name, sicode, siaddr) \
-asmlinkage void do_##name(struct pt_regs * regs, long error_code) \
-{ \
-        siginfo_t info; \
-        info.si_signo = signr; \
-        info.si_errno = 0; \
-        info.si_code = sicode; \
-        info.si_addr = (void __user *)siaddr; \
-        trace_hardirqs_fixup(); \
-        if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, signr) \
-                                                        == NOTIFY_STOP) \
-                return; \
+#define DO_ERROR_INFO(trapnr, signr, str, name, sicode, siaddr)         \
+asmlinkage void do_##name(struct pt_regs * regs, long error_code)       \
+{                                                                       \
+        siginfo_t info;                                                 \
+        info.si_signo = signr;                                          \
+        info.si_errno = 0;                                              \
+        info.si_code = sicode;                                          \
+        info.si_addr = (void __user *)siaddr;                           \
+        trace_hardirqs_fixup();                                         \
+        if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, signr)  \
+                                                        == NOTIFY_STOP) \
+                return;                                                 \
         conditional_sti(regs);                                          \
-        do_trap(trapnr, signr, str, regs, error_code, &info); \
+        do_trap(trapnr, signr, str, regs, error_code, &info);           \
 }
 
-DO_ERROR_INFO( 0, SIGFPE,  "divide error", divide_error, FPE_INTDIV, regs->ip)
-DO_ERROR( 4, SIGSEGV, "overflow", overflow)
-DO_ERROR( 5, SIGSEGV, "bounds", bounds)
-DO_ERROR_INFO( 6, SIGILL,  "invalid opcode", invalid_op, ILL_ILLOPN, regs->ip)
-DO_ERROR( 7, SIGSEGV, "device not available", device_not_available)
-DO_ERROR( 9, SIGFPE,  "coprocessor segment overrun", coprocessor_segment_overrun)
+DO_ERROR_INFO(0, SIGFPE, "divide error", divide_error, FPE_INTDIV, regs->ip)
+DO_ERROR(4, SIGSEGV, "overflow", overflow)
+DO_ERROR(5, SIGSEGV, "bounds", bounds)
+DO_ERROR_INFO(6, SIGILL, "invalid opcode", invalid_op, ILL_ILLOPN, regs->ip)
+DO_ERROR(9, SIGFPE, "coprocessor segment overrun", coprocessor_segment_overrun)
 DO_ERROR(10, SIGSEGV, "invalid TSS", invalid_TSS)
-DO_ERROR(11, SIGBUS,  "segment not present", segment_not_present)
+DO_ERROR(11, SIGBUS, "segment not present", segment_not_present)
 DO_ERROR_INFO(17, SIGBUS, "alignment check", alignment_check, BUS_ADRALN, 0)
-DO_ERROR(18, SIGSEGV, "reserved", reserved)
 
 /* Runs on IST stack */
 asmlinkage void do_stack_segment(struct pt_regs *regs, long error_code)
@@ -737,31 +712,34 @@ asmlinkage void do_double_fault(struct pt_regs * regs, long error_code)
                 die(str, regs, error_code);
 }
 
-asmlinkage void __kprobes do_general_protection(struct pt_regs * regs,
-                                                long error_code)
+asmlinkage void __kprobes
+do_general_protection(struct pt_regs *regs, long error_code)
 {
-        struct task_struct *tsk = current;
+        struct task_struct *tsk;
 
         conditional_sti(regs);
 
-        if (user_mode(regs)) {
-                tsk->thread.error_code = error_code;
-                tsk->thread.trap_no = 13;
-
-                if (show_unhandled_signals && unhandled_signal(tsk, SIGSEGV) &&
-                    printk_ratelimit()) {
-                        printk(KERN_INFO
-                       "%s[%d] general protection ip:%lx sp:%lx error:%lx",
-                               tsk->comm, tsk->pid,
-                               regs->ip, regs->sp, error_code);
-                        print_vma_addr(" in ", regs->ip);
-                        printk("\n");
-                }
+        tsk = current;
+        if (!user_mode(regs))
+                goto gp_in_kernel;
 
-                force_sig(SIGSEGV, tsk);
-                return;
-        } 
+        tsk->thread.error_code = error_code;
+        tsk->thread.trap_no = 13;
+
+        if (show_unhandled_signals && unhandled_signal(tsk, SIGSEGV) &&
+                        printk_ratelimit()) {
+                printk(KERN_INFO
+                        "%s[%d] general protection ip:%lx sp:%lx error:%lx",
+                        tsk->comm, tsk->pid,
+                        regs->ip, regs->sp, error_code);
+                print_vma_addr(" in ", regs->ip);
+                printk("\n");
+        }
 
+        force_sig(SIGSEGV, tsk);
+        return;
+
+gp_in_kernel:
         if (fixup_exception(regs))
                 return;
 
@@ -774,14 +752,14 @@ asmlinkage void __kprobes do_general_protection(struct pt_regs * regs,
 }
 
 static notrace __kprobes void
-mem_parity_error(unsigned char reason, struct pt_regs * regs)
+mem_parity_error(unsigned char reason, struct pt_regs *regs)
 {
         printk(KERN_EMERG "Uhhuh. NMI received for unknown reason %02x.\n",
                 reason);
         printk(KERN_EMERG "You have some hardware problem, likely on the PCI bus.\n");
 
 #if defined(CONFIG_EDAC)
-        if(edac_handler_set()) {
+        if (edac_handler_set()) {
                 edac_atomic_assert_error();
                 return;
         }
@@ -798,7 +776,7 @@ mem_parity_error(unsigned char reason, struct pt_regs * regs)
 }
 
 static notrace __kprobes void
-io_check_error(unsigned char reason, struct pt_regs * regs)
+io_check_error(unsigned char reason, struct pt_regs *regs)
 {
         printk("NMI: IOCK error (debug interrupt?)\n");
         show_registers(regs);
@@ -828,14 +806,14 @@ unknown_nmi_error(unsigned char reason, struct pt_regs * regs)
 
 /* Runs on IST stack. This code must keep interrupts off all the time.
    Nested NMIs are prevented by the CPU. */
-asmlinkage notrace  __kprobes void default_do_nmi(struct pt_regs *regs)
+asmlinkage notrace __kprobes void default_do_nmi(struct pt_regs *regs)
 {
         unsigned char reason = 0;
         int cpu;
 
         cpu = smp_processor_id();
 
-        /* Only the BSP gets external NMIs from the system.  */
+        /* Only the BSP gets external NMIs from the system. */
         if (!cpu)
                 reason = get_nmi_reason();
 
@@ -847,32 +825,57 @@ asmlinkage notrace  __kprobes void default_do_nmi(struct pt_regs *regs)
                  * Ok, so this is none of the documented NMI sources,
                  * so it must be the NMI watchdog.
                  */
-                if (nmi_watchdog_tick(regs,reason))
+                if (nmi_watchdog_tick(regs, reason))
                         return;
-                if (!do_nmi_callback(regs,cpu))
+                if (!do_nmi_callback(regs, cpu))
                         unknown_nmi_error(reason, regs);
 
                 return;
         }
         if (notify_die(DIE_NMI, "nmi", regs, reason, 2, SIGINT) == NOTIFY_STOP)
-                return; 
+                return;
 
         /* AK: following checks seem to be broken on modern chipsets. FIXME */
-
         if (reason & 0x80)
                 mem_parity_error(reason, regs);
         if (reason & 0x40)
                 io_check_error(reason, regs);
 }
 
+asmlinkage notrace __kprobes void
+do_nmi(struct pt_regs *regs, long error_code)
+{
+        nmi_enter();
+
+        add_pda(__nmi_count, 1);
+
+        if (!ignore_nmis)
+                default_do_nmi(regs);
+
+        nmi_exit();
+}
+
+void stop_nmi(void)
+{
+        acpi_nmi_disable();
+        ignore_nmis++;
+}
+
+void restart_nmi(void)
+{
+        ignore_nmis--;
+        acpi_nmi_enable();
+}
+
 /* runs on IST stack. */
-asmlinkage void __kprobes do_int3(struct pt_regs * regs, long error_code)
+asmlinkage void __kprobes do_int3(struct pt_regs *regs, long error_code)
 {
         trace_hardirqs_fixup();
 
-        if (notify_die(DIE_INT3, "int3", regs, error_code, 3, SIGTRAP) == NOTIFY_STOP) {
+        if (notify_die(DIE_INT3, "int3", regs, error_code, 3, SIGTRAP)
+                        == NOTIFY_STOP)
                 return;
-        }
+
         preempt_conditional_sti(regs);
         do_trap(3, SIGTRAP, "int3", regs, error_code, NULL);
         preempt_conditional_cli(regs);
@@ -903,8 +906,8 @@ asmlinkage __kprobes struct pt_regs *sync_regs(struct pt_regs *eregs)
 asmlinkage void __kprobes do_debug(struct pt_regs * regs,
                                    unsigned long error_code)
 {
-        unsigned long condition;
         struct task_struct *tsk = current;
+        unsigned long condition;
         siginfo_t info;
 
         trace_hardirqs_fixup();
@@ -925,21 +928,19 @@ asmlinkage void __kprobes do_debug(struct pt_regs * regs,
 
         /* Mask out spurious debug traps due to lazy DR7 setting */
         if (condition & (DR_TRAP0|DR_TRAP1|DR_TRAP2|DR_TRAP3)) {
-                if (!tsk->thread.debugreg7) { 
+                if (!tsk->thread.debugreg7)
                         goto clear_dr7;
-                }
         }
 
         tsk->thread.debugreg6 = condition;
 
-
         /*
          * Single-stepping through TF: make sure we ignore any events in
          * kernel space (but re-enable TF when returning to user mode).
          */
         if (condition & DR_STEP) {
-                if (!user_mode(regs))
-                       goto clear_TF_reenable;
+                if (!user_mode(regs))
+                        goto clear_TF_reenable;
         }
 
         /* Ok, finally something we can handle */
@@ -952,7 +953,7 @@ asmlinkage void __kprobes do_debug(struct pt_regs * regs,
         force_sig_info(SIGTRAP, &info, tsk);
 
 clear_dr7:
-        set_debugreg(0UL, 7);
+        set_debugreg(0, 7);
         preempt_conditional_cli(regs);
         return;
 
@@ -960,6 +961,7 @@ clear_TF_reenable:
         set_tsk_thread_flag(tsk, TIF_SINGLESTEP);
         regs->flags &= ~X86_EFLAGS_TF;
         preempt_conditional_cli(regs);
+        return;
 }
 
 static int kernel_math_error(struct pt_regs *regs, const char *str, int trapnr)
@@ -982,7 +984,7 @@ static int kernel_math_error(struct pt_regs *regs, const char *str, int trapnr)
 asmlinkage void do_coprocessor_error(struct pt_regs *regs)
 {
         void __user *ip = (void __user *)(regs->ip);
-        struct task_struct * task;
+        struct task_struct *task;
         siginfo_t info;
         unsigned short cwd, swd;
 
@@ -1015,30 +1017,30 @@ asmlinkage void do_coprocessor_error(struct pt_regs *regs)
         cwd = get_fpu_cwd(task);
         swd = get_fpu_swd(task);
         switch (swd & ~cwd & 0x3f) {
-                case 0x000:
-                default:
-                        break;
-                case 0x001: /* Invalid Op */
-                        /*
-                         * swd & 0x240 == 0x040: Stack Underflow
-                         * swd & 0x240 == 0x240: Stack Overflow
-                         * User must clear the SF bit (0x40) if set
-                         */
-                        info.si_code = FPE_FLTINV;
-                        break;
-                case 0x002: /* Denormalize */
-                case 0x010: /* Underflow */
-                        info.si_code = FPE_FLTUND;
-                        break;
-                case 0x004: /* Zero Divide */
-                        info.si_code = FPE_FLTDIV;
-                        break;
-                case 0x008: /* Overflow */
-                        info.si_code = FPE_FLTOVF;
-                        break;
-                case 0x020: /* Precision */
-                        info.si_code = FPE_FLTRES;
-                        break;
+        case 0x000: /* No unmasked exception */
+        default: /* Multiple exceptions */
+                break;
+        case 0x001: /* Invalid Op */
+                /*
+                 * swd & 0x240 == 0x040: Stack Underflow
+                 * swd & 0x240 == 0x240: Stack Overflow
+                 * User must clear the SF bit (0x40) if set
+                 */
+                info.si_code = FPE_FLTINV;
+                break;
+        case 0x002: /* Denormalize */
+        case 0x010: /* Underflow */
+                info.si_code = FPE_FLTUND;
+                break;
+        case 0x004: /* Zero Divide */
+                info.si_code = FPE_FLTDIV;
+                break;
+        case 0x008: /* Overflow */
+                info.si_code = FPE_FLTOVF;
+                break;
+        case 0x020: /* Precision */
+                info.si_code = FPE_FLTRES;
+                break;
         }
         force_sig_info(SIGFPE, &info, task);
 }
@@ -1051,7 +1053,7 @@ asmlinkage void bad_intr(void)
 asmlinkage void do_simd_coprocessor_error(struct pt_regs *regs)
 {
         void __user *ip = (void __user *)(regs->ip);
-        struct task_struct * task;
+        struct task_struct *task;
         siginfo_t info;
         unsigned short mxcsr;
 
@@ -1079,25 +1081,25 @@ asmlinkage void do_simd_coprocessor_error(struct pt_regs *regs)
          */
         mxcsr = get_fpu_mxcsr(task);
         switch (~((mxcsr & 0x1f80) >> 7) & (mxcsr & 0x3f)) {
-                case 0x000:
-                default:
-                        break;
-                case 0x001: /* Invalid Op */
-                        info.si_code = FPE_FLTINV;
-                        break;
-                case 0x002: /* Denormalize */
-                case 0x010: /* Underflow */
-                        info.si_code = FPE_FLTUND;
-                        break;
-                case 0x004: /* Zero Divide */
-                        info.si_code = FPE_FLTDIV;
-                        break;
-                case 0x008: /* Overflow */
-                        info.si_code = FPE_FLTOVF;
-                        break;
-                case 0x020: /* Precision */
-                        info.si_code = FPE_FLTRES;
-                        break;
+        case 0x000:
+        default:
+                break;
+        case 0x001: /* Invalid Op */
+                info.si_code = FPE_FLTINV;
+                break;
+        case 0x002: /* Denormalize */
+        case 0x010: /* Underflow */
+                info.si_code = FPE_FLTUND;
+                break;
+        case 0x004: /* Zero Divide */
+                info.si_code = FPE_FLTDIV;
+                break;
+        case 0x008: /* Overflow */
+                info.si_code = FPE_FLTOVF;
+                break;
+        case 0x020: /* Precision */
+                info.si_code = FPE_FLTRES;
+                break;
         }
         force_sig_info(SIGFPE, &info, task);
 }
@@ -1115,7 +1117,7 @@ asmlinkage void __attribute__((weak)) mce_threshold_interrupt(void)
 }
 
 /*
- *  'math_state_restore()' saves the current math information in the
+ * 'math_state_restore()' saves the current math information in the
  * old math state array, and gets the new ones from the current task
  *
  * Careful.. There are problems with IBM-designed IRQ13 behaviour.
@@ -1140,7 +1142,7 @@ asmlinkage void math_state_restore(void)
                 local_irq_disable();
         }
 
-        clts();                 /* Allow maths ops (or we recurse) */
+        clts();                         /* Allow maths ops (or we recurse) */
         restore_fpu_checking(&me->thread.xstate->fxsave);
         task_thread_info(me)->status |= TS_USEDFPU;
         me->fpu_counter++;
@@ -1149,64 +1151,61 @@ EXPORT_SYMBOL_GPL(math_state_restore);
 
 void __init trap_init(void)
 {
-        set_intr_gate(0,&divide_error);
-        set_intr_gate_ist(1,&debug,DEBUG_STACK);
-        set_intr_gate_ist(2,&nmi,NMI_STACK);
-        set_system_gate_ist(3,&int3,DEBUG_STACK); /* int3 can be called from all */
-        set_system_gate(4,&overflow);   /* int4 can be called from all */
-        set_intr_gate(5,&bounds);
-        set_intr_gate(6,&invalid_op);
-        set_intr_gate(7,&device_not_available);
-        set_intr_gate_ist(8,&double_fault, DOUBLEFAULT_STACK);
-        set_intr_gate(9,&coprocessor_segment_overrun);
-        set_intr_gate(10,&invalid_TSS);
-        set_intr_gate(11,&segment_not_present);
-        set_intr_gate_ist(12,&stack_segment,STACKFAULT_STACK);
-        set_intr_gate(13,&general_protection);
-        set_intr_gate(14,&page_fault);
-        set_intr_gate(15,&spurious_interrupt_bug);
-        set_intr_gate(16,&coprocessor_error);
-        set_intr_gate(17,&alignment_check);
+        set_intr_gate(0, &divide_error);
+        set_intr_gate_ist(1, &debug, DEBUG_STACK);
+        set_intr_gate_ist(2, &nmi, NMI_STACK);
+        set_system_gate_ist(3, &int3, DEBUG_STACK); /* int3 can be called from all */
+        set_system_gate(4, &overflow); /* int4 can be called from all */
+        set_intr_gate(5, &bounds);
+        set_intr_gate(6, &invalid_op);
+        set_intr_gate(7, &device_not_available);
+        set_intr_gate_ist(8, &double_fault, DOUBLEFAULT_STACK);
+        set_intr_gate(9, &coprocessor_segment_overrun);
+        set_intr_gate(10, &invalid_TSS);
+        set_intr_gate(11, &segment_not_present);
+        set_intr_gate_ist(12, &stack_segment, STACKFAULT_STACK);
+        set_intr_gate(13, &general_protection);
+        set_intr_gate(14, &page_fault);
+        set_intr_gate(15, &spurious_interrupt_bug);
+        set_intr_gate(16, &coprocessor_error);
+        set_intr_gate(17, &alignment_check);
 #ifdef CONFIG_X86_MCE
-        set_intr_gate_ist(18,&machine_check, MCE_STACK); 
+        set_intr_gate_ist(18, &machine_check, MCE_STACK);
 #endif
-        set_intr_gate(19,&simd_coprocessor_error);
+        set_intr_gate(19, &simd_coprocessor_error);
 
 #ifdef CONFIG_IA32_EMULATION
         set_system_gate(IA32_SYSCALL_VECTOR, ia32_syscall);
 #endif
-       
         /*
          * initialize the per thread extended state:
          */
-        init_thread_xstate();
+        init_thread_xstate();
         /*
-         * Should be a barrier for any external CPU state.
+         * Should be a barrier for any external CPU state:
          */
         cpu_init();
 }
 
-
 static int __init oops_setup(char *s)
-{ 
+{
         if (!s)
                 return -EINVAL;
         if (!strcmp(s, "panic"))
                 panic_on_oops = 1;
         return 0;
-} 
+}
 early_param("oops", oops_setup);
 
 static int __init kstack_setup(char *s)
 {
         if (!s)
                 return -EINVAL;
-        kstack_depth_to_print = simple_strtoul(s,NULL,0);
+        kstack_depth_to_print = simple_strtoul(s, NULL, 0);
         return 0;
 }
 early_param("kstack", kstack_setup);
 
-
 static int __init code_bytes_setup(char *s)
 {
         code_bytes = simple_strtoul(s, NULL, 0);
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
new file mode 100644
index 000000000000..3c36f92160c9
--- /dev/null
+++ b/arch/x86/kernel/tsc.c
@@ -0,0 +1,533 @@
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/timer.h>
+#include <linux/acpi_pmtmr.h>
+#include <linux/cpufreq.h>
+#include <linux/dmi.h>
+#include <linux/delay.h>
+#include <linux/clocksource.h>
+#include <linux/percpu.h>
+
+#include <asm/hpet.h>
+#include <asm/timer.h>
+#include <asm/vgtod.h>
+#include <asm/time.h>
+#include <asm/delay.h>
+
+unsigned int cpu_khz;           /* TSC clocks / usec, not used here */
+EXPORT_SYMBOL(cpu_khz);
+unsigned int tsc_khz;
+EXPORT_SYMBOL(tsc_khz);
+
+/*
+ * TSC can be unstable due to cpufreq or due to unsynced TSCs
+ */
+static int tsc_unstable;
+
+/* native_sched_clock() is called before tsc_init(), so
+   we must start with the TSC soft disabled to prevent
+   erroneous rdtsc usage on !cpu_has_tsc processors */
+static int tsc_disabled = -1;
+
+/*
+ * Scheduler clock - returns current time in nanosec units.
+ */
+u64 native_sched_clock(void)
+{
+        u64 this_offset;
+
+        /*
+         * Fall back to jiffies if there's no TSC available:
+         * ( But note that we still use it if the TSC is marked
+         *   unstable. We do this because unlike Time Of Day,
+         *   the scheduler clock tolerates small errors and it's
+         *   very important for it to be as fast as the platform
+         *   can achive it. )
+         */
+        if (unlikely(tsc_disabled)) {
+                /* No locking but a rare wrong value is not a big deal: */
+                return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ);
+        }
+
+        /* read the Time Stamp Counter: */
+        rdtscll(this_offset);
+
+        /* return the value in ns */
+        return cycles_2_ns(this_offset);
+}
+
+/* We need to define a real function for sched_clock, to override the
+   weak default version */
+#ifdef CONFIG_PARAVIRT
+unsigned long long sched_clock(void)
+{
+        return paravirt_sched_clock();
+}
+#else
+unsigned long long
+sched_clock(void) __attribute__((alias("native_sched_clock")));
+#endif
+
+int check_tsc_unstable(void)
+{
+        return tsc_unstable;
+}
+EXPORT_SYMBOL_GPL(check_tsc_unstable);
+
+#ifdef CONFIG_X86_TSC
+int __init notsc_setup(char *str)
+{
+        printk(KERN_WARNING "notsc: Kernel compiled with CONFIG_X86_TSC, "
+                        "cannot disable TSC completely.\n");
+        tsc_disabled = 1;
+        return 1;
+}
+#else
+/*
+ * disable flag for tsc. Takes effect by clearing the TSC cpu flag
+ * in cpu/common.c
+ */
+int __init notsc_setup(char *str)
+{
+        setup_clear_cpu_cap(X86_FEATURE_TSC);
+        return 1;
+}
+#endif
+
+__setup("notsc", notsc_setup);
+
+#define MAX_RETRIES     5
+#define SMI_TRESHOLD    50000
+
+/*
+ * Read TSC and the reference counters. Take care of SMI disturbance
+ */
+static u64 __init tsc_read_refs(u64 *pm, u64 *hpet)
+{
+        u64 t1, t2;
+        int i;
+
+        for (i = 0; i < MAX_RETRIES; i++) {
+                t1 = get_cycles();
+                if (hpet)
+                        *hpet = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF;
+                else
+                        *pm = acpi_pm_read_early();
+                t2 = get_cycles();
+                if ((t2 - t1) < SMI_TRESHOLD)
+                        return t2;
+        }
+        return ULLONG_MAX;
+}
+
+/**
+ * native_calibrate_tsc - calibrate the tsc on boot
+ */
+unsigned long native_calibrate_tsc(void)
+{
+        unsigned long flags;
+        u64 tsc1, tsc2, tr1, tr2, delta, pm1, pm2, hpet1, hpet2;
+        int hpet = is_hpet_enabled();
+        unsigned int tsc_khz_val = 0;
+
+        local_irq_save(flags);
+
+        tsc1 = tsc_read_refs(&pm1, hpet ? &hpet1 : NULL);
+
+        outb((inb(0x61) & ~0x02) | 0x01, 0x61);
+
+        outb(0xb0, 0x43);
+        outb((CLOCK_TICK_RATE / (1000 / 50)) & 0xff, 0x42);
+        outb((CLOCK_TICK_RATE / (1000 / 50)) >> 8, 0x42);
+        tr1 = get_cycles();
+        while ((inb(0x61) & 0x20) == 0);
+        tr2 = get_cycles();
+
+        tsc2 = tsc_read_refs(&pm2, hpet ? &hpet2 : NULL);
+
+        local_irq_restore(flags);
+
+        /*
+         * Preset the result with the raw and inaccurate PIT
+         * calibration value
+         */
+        delta = (tr2 - tr1);
+        do_div(delta, 50);
+        tsc_khz_val = delta;
+
+        /* hpet or pmtimer available ? */
+        if (!hpet && !pm1 && !pm2) {
+                printk(KERN_INFO "TSC calibrated against PIT\n");
+                goto out;
+        }
+
+        /* Check, whether the sampling was disturbed by an SMI */
+        if (tsc1 == ULLONG_MAX || tsc2 == ULLONG_MAX) {
+                printk(KERN_WARNING "TSC calibration disturbed by SMI, "
+                                "using PIT calibration result\n");
+                goto out;
+        }
+
+        tsc2 = (tsc2 - tsc1) * 1000000LL;
+
+        if (hpet) {
+                printk(KERN_INFO "TSC calibrated against HPET\n");
+                if (hpet2 < hpet1)
+                        hpet2 += 0x100000000ULL;
+                hpet2 -= hpet1;
+                tsc1 = ((u64)hpet2 * hpet_readl(HPET_PERIOD));
+                do_div(tsc1, 1000000);
+        } else {
+                printk(KERN_INFO "TSC calibrated against PM_TIMER\n");
+                if (pm2 < pm1)
+                        pm2 += (u64)ACPI_PM_OVRRUN;
+                pm2 -= pm1;
+                tsc1 = pm2 * 1000000000LL;
+                do_div(tsc1, PMTMR_TICKS_PER_SEC);
+        }
+
+        do_div(tsc2, tsc1);
+        tsc_khz_val = tsc2;
+
+out:
+        return tsc_khz_val;
+}
+
+
+#ifdef CONFIG_X86_32
+/* Only called from the Powernow K7 cpu freq driver */
+int recalibrate_cpu_khz(void)
+{
+#ifndef CONFIG_SMP
+        unsigned long cpu_khz_old = cpu_khz;
+
+        if (cpu_has_tsc) {
+                tsc_khz = calibrate_tsc();
+                cpu_khz = tsc_khz;
+                cpu_data(0).loops_per_jiffy =
+                        cpufreq_scale(cpu_data(0).loops_per_jiffy,
+                                        cpu_khz_old, cpu_khz);
+                return 0;
+        } else
+                return -ENODEV;
+#else
+        return -ENODEV;
+#endif
+}
+
+EXPORT_SYMBOL(recalibrate_cpu_khz);
+
+#endif /* CONFIG_X86_32 */
+
+/* Accelerators for sched_clock()
+ * convert from cycles(64bits) => nanoseconds (64bits)
+ *  basic equation:
+ *              ns = cycles / (freq / ns_per_sec)
+ *              ns = cycles * (ns_per_sec / freq)
+ *              ns = cycles * (10^9 / (cpu_khz * 10^3))
+ *              ns = cycles * (10^6 / cpu_khz)
+ *
+ *      Then we use scaling math (suggested by george@mvista.com) to get:
+ *              ns = cycles * (10^6 * SC / cpu_khz) / SC
+ *              ns = cycles * cyc2ns_scale / SC
+ *
+ *      And since SC is a constant power of two, we can convert the div
+ *  into a shift.
+ *
+ *  We can use khz divisor instead of mhz to keep a better precision, since
+ *  cyc2ns_scale is limited to 10^6 * 2^10, which fits in 32 bits.
+ *  (mathieu.desnoyers@polymtl.ca)
+ *
+ *                      -johnstul@us.ibm.com "math is hard, lets go shopping!"
+ */
+
+DEFINE_PER_CPU(unsigned long, cyc2ns);
+
+static void set_cyc2ns_scale(unsigned long cpu_khz, int cpu)
+{
+        unsigned long long tsc_now, ns_now;
+        unsigned long flags, *scale;
+
+        local_irq_save(flags);
+        sched_clock_idle_sleep_event();
+
+        scale = &per_cpu(cyc2ns, cpu);
+
+        rdtscll(tsc_now);
+        ns_now = __cycles_2_ns(tsc_now);
+
+        if (cpu_khz)
+                *scale = (NSEC_PER_MSEC << CYC2NS_SCALE_FACTOR)/cpu_khz;
+
+        sched_clock_idle_wakeup_event(0);
+        local_irq_restore(flags);
+}
+
+#ifdef CONFIG_CPU_FREQ
+
+/* Frequency scaling support. Adjust the TSC based timer when the cpu frequency
+ * changes.
+ *
+ * RED-PEN: On SMP we assume all CPUs run with the same frequency.  It's
+ * not that important because current Opteron setups do not support
+ * scaling on SMP anyroads.
+ *
+ * Should fix up last_tsc too. Currently gettimeofday in the
+ * first tick after the change will be slightly wrong.
+ */
+
+static unsigned int  ref_freq;
+static unsigned long loops_per_jiffy_ref;
+static unsigned long tsc_khz_ref;
+
+static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
+                                void *data)
+{
+        struct cpufreq_freqs *freq = data;
+        unsigned long *lpj, dummy;
+
+        if (cpu_has(&cpu_data(freq->cpu), X86_FEATURE_CONSTANT_TSC))
+                return 0;
+
+        lpj = &dummy;
+        if (!(freq->flags & CPUFREQ_CONST_LOOPS))
+#ifdef CONFIG_SMP
+                lpj = &cpu_data(freq->cpu).loops_per_jiffy;
+#else
+        lpj = &boot_cpu_data.loops_per_jiffy;
+#endif
+
+        if (!ref_freq) {
+                ref_freq = freq->old;
+                loops_per_jiffy_ref = *lpj;
+                tsc_khz_ref = tsc_khz;
+        }
+        if ((val == CPUFREQ_PRECHANGE  && freq->old < freq->new) ||
+                        (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) ||
+                        (val == CPUFREQ_RESUMECHANGE)) {
+                *lpj =  cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new);
+
+                tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
+                if (!(freq->flags & CPUFREQ_CONST_LOOPS))
+                        mark_tsc_unstable("cpufreq changes");
+        }
+
+        set_cyc2ns_scale(tsc_khz_ref, freq->cpu);
+
+        return 0;
+}
+
+static struct notifier_block time_cpufreq_notifier_block = {
+        .notifier_call  = time_cpufreq_notifier
+};
+
+static int __init cpufreq_tsc(void)
+{
+        cpufreq_register_notifier(&time_cpufreq_notifier_block,
+                                CPUFREQ_TRANSITION_NOTIFIER);
+        return 0;
+}
+
+core_initcall(cpufreq_tsc);
+
+#endif /* CONFIG_CPU_FREQ */
+
+/* clocksource code */
+
+static struct clocksource clocksource_tsc;
+
+/*
+ * We compare the TSC to the cycle_last value in the clocksource
+ * structure to avoid a nasty time-warp. This can be observed in a
+ * very small window right after one CPU updated cycle_last under
+ * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which
+ * is smaller than the cycle_last reference value due to a TSC which
+ * is slighty behind. This delta is nowhere else observable, but in
+ * that case it results in a forward time jump in the range of hours
+ * due to the unsigned delta calculation of the time keeping core
+ * code, which is necessary to support wrapping clocksources like pm
+ * timer.
+ */
+static cycle_t read_tsc(void)
+{
+        cycle_t ret = (cycle_t)get_cycles();
+
+        return ret >= clocksource_tsc.cycle_last ?
+                ret : clocksource_tsc.cycle_last;
+}
+
+static cycle_t __vsyscall_fn vread_tsc(void)
+{
+        cycle_t ret = (cycle_t)vget_cycles();
+
+        return ret >= __vsyscall_gtod_data.clock.cycle_last ?
+                ret : __vsyscall_gtod_data.clock.cycle_last;
+}
+
+static struct clocksource clocksource_tsc = {
+        .name                   = "tsc",
+        .rating                 = 300,
+        .read                   = read_tsc,
+        .mask                   = CLOCKSOURCE_MASK(64),
+        .shift                  = 22,
+        .flags                  = CLOCK_SOURCE_IS_CONTINUOUS |
+                                  CLOCK_SOURCE_MUST_VERIFY,
+#ifdef CONFIG_X86_64
+        .vread                  = vread_tsc,
+#endif
+};
+
+void mark_tsc_unstable(char *reason)
+{
+        if (!tsc_unstable) {
+                tsc_unstable = 1;
+                printk("Marking TSC unstable due to %s\n", reason);
+                /* Change only the rating, when not registered */
+                if (clocksource_tsc.mult)
+                        clocksource_change_rating(&clocksource_tsc, 0);
+                else
+                        clocksource_tsc.rating = 0;
+        }
+}
+
+EXPORT_SYMBOL_GPL(mark_tsc_unstable);
+
+static int __init dmi_mark_tsc_unstable(const struct dmi_system_id *d)
+{
+        printk(KERN_NOTICE "%s detected: marking TSC unstable.\n",
+                        d->ident);
+        tsc_unstable = 1;
+        return 0;
+}
+
+/* List of systems that have known TSC problems */
+static struct dmi_system_id __initdata bad_tsc_dmi_table[] = {
+        {
+                .callback = dmi_mark_tsc_unstable,
+                .ident = "IBM Thinkpad 380XD",
+                .matches = {
+                        DMI_MATCH(DMI_BOARD_VENDOR, "IBM"),
+                        DMI_MATCH(DMI_BOARD_NAME, "2635FA0"),
+                },
+        },
+        {}
+};
+
+/*
+ * Geode_LX - the OLPC CPU has a possibly a very reliable TSC
+ */
+#ifdef CONFIG_MGEODE_LX
+/* RTSC counts during suspend */
+#define RTSC_SUSP 0x100
+
+static void __init check_geode_tsc_reliable(void)
+{
+        unsigned long res_low, res_high;
+
+        rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high);
+        if (res_low & RTSC_SUSP)
+                clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY;
+}
+#else
+static inline void check_geode_tsc_reliable(void) { }
+#endif
+
+/*
+ * Make an educated guess if the TSC is trustworthy and synchronized
+ * over all CPUs.
+ */
+__cpuinit int unsynchronized_tsc(void)
+{
+        if (!cpu_has_tsc || tsc_unstable)
+                return 1;
+
+#ifdef CONFIG_SMP
+        if (apic_is_clustered_box())
+                return 1;
+#endif
+
+        if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
+                return 0;
+        /*
+         * Intel systems are normally all synchronized.
+         * Exceptions must mark TSC as unstable:
+         */
+        if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
+                /* assume multi socket systems are not synchronized: */
+                if (num_possible_cpus() > 1)
+                        tsc_unstable = 1;
+        }
+
+        return tsc_unstable;
+}
+
+static void __init init_tsc_clocksource(void)
+{
+        clocksource_tsc.mult = clocksource_khz2mult(tsc_khz,
+                        clocksource_tsc.shift);
+        /* lower the rating if we already know its unstable: */
+        if (check_tsc_unstable()) {
+                clocksource_tsc.rating = 0;
+                clocksource_tsc.flags &= ~CLOCK_SOURCE_IS_CONTINUOUS;
+        }
+        clocksource_register(&clocksource_tsc);
+}
+
+void __init tsc_init(void)
+{
+        u64 lpj;
+        int cpu;
+
+        if (!cpu_has_tsc)
+                return;
+
+        tsc_khz = calibrate_tsc();
+        cpu_khz = tsc_khz;
+
+        if (!tsc_khz) {
+                mark_tsc_unstable("could not calculate TSC khz");
+                return;
+        }
+
+#ifdef CONFIG_X86_64
+        if (cpu_has(&boot_cpu_data, X86_FEATURE_CONSTANT_TSC) &&
+                        (boot_cpu_data.x86_vendor == X86_VENDOR_AMD))
+                cpu_khz = calibrate_cpu();
+#endif
+
+        lpj = ((u64)tsc_khz * 1000);
+        do_div(lpj, HZ);
+        lpj_fine = lpj;
+
+        printk("Detected %lu.%03lu MHz processor.\n",
+                        (unsigned long)cpu_khz / 1000,
+                        (unsigned long)cpu_khz % 1000);
+
+        /*
+         * Secondary CPUs do not run through tsc_init(), so set up
+         * all the scale factors for all CPUs, assuming the same
+         * speed as the bootup CPU. (cpufreq notifiers will fix this
+         * up if their speed diverges)
+         */
+        for_each_possible_cpu(cpu)
+                set_cyc2ns_scale(cpu_khz, cpu);
+
+        if (tsc_disabled > 0)
+                return;
+
+        /* now allow native_sched_clock() to use rdtsc */
+        tsc_disabled = 0;
+
+        use_tsc_delay();
+        /* Check and install the TSC clocksource */
+        dmi_check_system(bad_tsc_dmi_table);
+
+        if (unsynchronized_tsc())
+                mark_tsc_unstable("TSCs unsynchronized");
+
+        check_geode_tsc_reliable();
+        init_tsc_clocksource();
+}
+
diff --git a/arch/x86/kernel/tsc_32.c b/arch/x86/kernel/tsc_32.c
deleted file mode 100644
index 65b70637ad97..000000000000
--- a/arch/x86/kernel/tsc_32.c
+++ /dev/null
@@ -1,451 +0,0 @@
-#include <linux/sched.h>
-#include <linux/clocksource.h>
-#include <linux/workqueue.h>
-#include <linux/cpufreq.h>
-#include <linux/jiffies.h>
-#include <linux/init.h>
-#include <linux/dmi.h>
-#include <linux/percpu.h>
-
-#include <asm/delay.h>
-#include <asm/tsc.h>
-#include <asm/io.h>
-#include <asm/timer.h>
-
-#include "mach_timer.h"
-
-/* native_sched_clock() is called before tsc_init(), so
-   we must start with the TSC soft disabled to prevent
-   erroneous rdtsc usage on !cpu_has_tsc processors */
-static int tsc_disabled = -1;
-
-/*
- * On some systems the TSC frequency does not
- * change with the cpu frequency. So we need
- * an extra value to store the TSC freq
- */
-unsigned int tsc_khz;
-EXPORT_SYMBOL_GPL(tsc_khz);
-
-#ifdef CONFIG_X86_TSC
-static int __init tsc_setup(char *str)
-{
-        printk(KERN_WARNING "notsc: Kernel compiled with CONFIG_X86_TSC, "
-               "cannot disable TSC completely.\n");
-        tsc_disabled = 1;
-        return 1;
-}
-#else
-/*
- * disable flag for tsc. Takes effect by clearing the TSC cpu flag
- * in cpu/common.c
- */
-static int __init tsc_setup(char *str)
-{
-        setup_clear_cpu_cap(X86_FEATURE_TSC);
-        return 1;
-}
-#endif
-
-__setup("notsc", tsc_setup);
-
-/*
- * code to mark and check if the TSC is unstable
- * due to cpufreq or due to unsynced TSCs
- */
-static int tsc_unstable;
-
-int check_tsc_unstable(void)
-{
-        return tsc_unstable;
-}
-EXPORT_SYMBOL_GPL(check_tsc_unstable);
-
-/* Accelerators for sched_clock()
- * convert from cycles(64bits) => nanoseconds (64bits)
- *  basic equation:
- *              ns = cycles / (freq / ns_per_sec)
- *              ns = cycles * (ns_per_sec / freq)
- *              ns = cycles * (10^9 / (cpu_khz * 10^3))
- *              ns = cycles * (10^6 / cpu_khz)
- *
- *      Then we use scaling math (suggested by george@mvista.com) to get:
- *              ns = cycles * (10^6 * SC / cpu_khz) / SC
- *              ns = cycles * cyc2ns_scale / SC
- *
- *      And since SC is a constant power of two, we can convert the div
- *  into a shift.
- *
- *  We can use khz divisor instead of mhz to keep a better precision, since
- *  cyc2ns_scale is limited to 10^6 * 2^10, which fits in 32 bits.
- *  (mathieu.desnoyers@polymtl.ca)
- *
- *                      -johnstul@us.ibm.com "math is hard, lets go shopping!"
- */
-
-DEFINE_PER_CPU(unsigned long, cyc2ns);
-
-static void set_cyc2ns_scale(unsigned long cpu_khz, int cpu)
-{
-        unsigned long long tsc_now, ns_now;
-        unsigned long flags, *scale;
-
-        local_irq_save(flags);
-        sched_clock_idle_sleep_event();
-
-        scale = &per_cpu(cyc2ns, cpu);
-
-        rdtscll(tsc_now);
-        ns_now = __cycles_2_ns(tsc_now);
-
-        if (cpu_khz)
-                *scale = (NSEC_PER_MSEC << CYC2NS_SCALE_FACTOR)/cpu_khz;
-
-        /*
-         * Start smoothly with the new frequency:
-         */
-        sched_clock_idle_wakeup_event(0);
-        local_irq_restore(flags);
-}
-
-/*
- * Scheduler clock - returns current time in nanosec units.
- */
-unsigned long long native_sched_clock(void)
-{
-        unsigned long long this_offset;
-
-        /*
-         * Fall back to jiffies if there's no TSC available:
-         * ( But note that we still use it if the TSC is marked
-         *   unstable. We do this because unlike Time Of Day,
-         *   the scheduler clock tolerates small errors and it's
-         *   very important for it to be as fast as the platform
-         *   can achive it. )
-         */
-        if (unlikely(tsc_disabled))
-                /* No locking but a rare wrong value is not a big deal: */
-                return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ);
-
-        /* read the Time Stamp Counter: */
-        rdtscll(this_offset);
-
-        /* return the value in ns */
-        return cycles_2_ns(this_offset);
-}
-
-/* We need to define a real function for sched_clock, to override the
-   weak default version */
-#ifdef CONFIG_PARAVIRT
-unsigned long long sched_clock(void)
-{
-        return paravirt_sched_clock();
-}
-#else
-unsigned long long sched_clock(void)
-        __attribute__((alias("native_sched_clock")));
-#endif
-
-unsigned long native_calculate_cpu_khz(void)
-{
-        unsigned long long start, end;
-        unsigned long count;
-        u64 delta64 = (u64)ULLONG_MAX;
-        int i;
-        unsigned long flags;
-
-        local_irq_save(flags);
-
-        /* run 3 times to ensure the cache is warm and to get an accurate reading */
-        for (i = 0; i < 3; i++) {
-                mach_prepare_counter();
-                rdtscll(start);
-                mach_countup(&count);
-                rdtscll(end);
-
-                /*
-                 * Error: ECTCNEVERSET
-                 * The CTC wasn't reliable: we got a hit on the very first read,
-                 * or the CPU was so fast/slow that the quotient wouldn't fit in
-                 * 32 bits..
-                 */
-                if (count <= 1)
-                        continue;
-
-                /* cpu freq too slow: */
-                if ((end - start) <= CALIBRATE_TIME_MSEC)
-                        continue;
-
-                /*
-                 * We want the minimum time of all runs in case one of them
-                 * is inaccurate due to SMI or other delay
-                 */
-                delta64 = min(delta64, (end - start));
-        }
-
-        /* cpu freq too fast (or every run was bad): */
-        if (delta64 > (1ULL<<32))
-                goto err;
-
-        delta64 += CALIBRATE_TIME_MSEC/2; /* round for do_div */
-        do_div(delta64,CALIBRATE_TIME_MSEC);
-
-        local_irq_restore(flags);
-        return (unsigned long)delta64;
-err:
-        local_irq_restore(flags);
-        return 0;
-}
-
-int recalibrate_cpu_khz(void)
-{
-#ifndef CONFIG_SMP
-        unsigned long cpu_khz_old = cpu_khz;
-
-        if (cpu_has_tsc) {
-                cpu_khz = calculate_cpu_khz();
-                tsc_khz = cpu_khz;
-                cpu_data(0).loops_per_jiffy =
-                        cpufreq_scale(cpu_data(0).loops_per_jiffy,
-                                        cpu_khz_old, cpu_khz);
-                return 0;
-        } else
-                return -ENODEV;
-#else
-        return -ENODEV;
-#endif
-}
-
-EXPORT_SYMBOL(recalibrate_cpu_khz);
-
-#ifdef CONFIG_CPU_FREQ
-
-/*
- * if the CPU frequency is scaled, TSC-based delays will need a different
- * loops_per_jiffy value to function properly.
- */
-static unsigned int ref_freq;
-static unsigned long loops_per_jiffy_ref;
-static unsigned long cpu_khz_ref;
-
-static int
-time_cpufreq_notifier(struct notifier_block *nb, unsigned long val, void *data)
-{
-        struct cpufreq_freqs *freq = data;
-
-        if (!ref_freq) {
-                if (!freq->old){
-                        ref_freq = freq->new;
-                        return 0;
-                }
-                ref_freq = freq->old;
-                loops_per_jiffy_ref = cpu_data(freq->cpu).loops_per_jiffy;
-                cpu_khz_ref = cpu_khz;
-        }
-
-        if ((val == CPUFREQ_PRECHANGE  && freq->old < freq->new) ||
-            (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) ||
-            (val == CPUFREQ_RESUMECHANGE)) {
-                if (!(freq->flags & CPUFREQ_CONST_LOOPS))
-                        cpu_data(freq->cpu).loops_per_jiffy =
-                                cpufreq_scale(loops_per_jiffy_ref,
-                                                ref_freq, freq->new);
-
-                if (cpu_khz) {
-
-                        if (num_online_cpus() == 1)
-                                cpu_khz = cpufreq_scale(cpu_khz_ref,
-                                                ref_freq, freq->new);
-                        if (!(freq->flags & CPUFREQ_CONST_LOOPS)) {
-                                tsc_khz = cpu_khz;
-                                set_cyc2ns_scale(cpu_khz, freq->cpu);
-                                /*
-                                 * TSC based sched_clock turns
-                                 * to junk w/ cpufreq
-                                 */
-                                mark_tsc_unstable("cpufreq changes");
-                        }
-                }
-        }
-
-        return 0;
-}
-
-static struct notifier_block time_cpufreq_notifier_block = {
-        .notifier_call  = time_cpufreq_notifier
-};
-
-static int __init cpufreq_tsc(void)
-{
-        return cpufreq_register_notifier(&time_cpufreq_notifier_block,
-                                         CPUFREQ_TRANSITION_NOTIFIER);
-}
-core_initcall(cpufreq_tsc);
-
-#endif
-
-/* clock source code */
-
-static unsigned long current_tsc_khz;
-static struct clocksource clocksource_tsc;
-
-/*
- * We compare the TSC to the cycle_last value in the clocksource
- * structure to avoid a nasty time-warp issue. This can be observed in
- * a very small window right after one CPU updated cycle_last under
- * xtime lock and the other CPU reads a TSC value which is smaller
- * than the cycle_last reference value due to a TSC which is slighty
- * behind. This delta is nowhere else observable, but in that case it
- * results in a forward time jump in the range of hours due to the
- * unsigned delta calculation of the time keeping core code, which is
- * necessary to support wrapping clocksources like pm timer.
- */
-static cycle_t read_tsc(void)
-{
-        cycle_t ret;
-
-        rdtscll(ret);
-
-        return ret >= clocksource_tsc.cycle_last ?
-                ret : clocksource_tsc.cycle_last;
-}
-
-static struct clocksource clocksource_tsc = {
-        .name                   = "tsc",
-        .rating                 = 300,
-        .read                   = read_tsc,
-        .mask                   = CLOCKSOURCE_MASK(64),
-        .mult                   = 0, /* to be set */
-        .shift                  = 22,
-        .flags                  = CLOCK_SOURCE_IS_CONTINUOUS |
-                                  CLOCK_SOURCE_MUST_VERIFY,
-};
-
-void mark_tsc_unstable(char *reason)
-{
-        if (!tsc_unstable) {
-                tsc_unstable = 1;
-                printk("Marking TSC unstable due to: %s.\n", reason);
-                /* Can be called before registration */
-                if (clocksource_tsc.mult)
-                        clocksource_change_rating(&clocksource_tsc, 0);
-                else
-                        clocksource_tsc.rating = 0;
-        }
-}
-EXPORT_SYMBOL_GPL(mark_tsc_unstable);
-
-static int __init dmi_mark_tsc_unstable(const struct dmi_system_id *d)
-{
-        printk(KERN_NOTICE "%s detected: marking TSC unstable.\n",
-               d->ident);
-        tsc_unstable = 1;
-        return 0;
-}
-
-/* List of systems that have known TSC problems */
-static struct dmi_system_id __initdata bad_tsc_dmi_table[] = {
-        {
-         .callback = dmi_mark_tsc_unstable,
-         .ident = "IBM Thinkpad 380XD",
-         .matches = {
-                     DMI_MATCH(DMI_BOARD_VENDOR, "IBM"),
-                     DMI_MATCH(DMI_BOARD_NAME, "2635FA0"),
-                     },
-         },
-         {}
-};
-
-/*
- * Make an educated guess if the TSC is trustworthy and synchronized
- * over all CPUs.
- */
-__cpuinit int unsynchronized_tsc(void)
-{
-        if (!cpu_has_tsc || tsc_unstable)
-                return 1;
-
-        /* Anything with constant TSC should be synchronized */
-        if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
-                return 0;
-
-        /*
-         * Intel systems are normally all synchronized.
-         * Exceptions must mark TSC as unstable:
-         */
-        if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
-                /* assume multi socket systems are not synchronized: */
-                if (num_possible_cpus() > 1)
-                        tsc_unstable = 1;
-        }
-        return tsc_unstable;
-}
-
-/*
- * Geode_LX - the OLPC CPU has a possibly a very reliable TSC
- */
-#ifdef CONFIG_MGEODE_LX
-/* RTSC counts during suspend */
-#define RTSC_SUSP 0x100
-
-static void __init check_geode_tsc_reliable(void)
-{
-        unsigned long res_low, res_high;
-
-        rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high);
-        if (res_low & RTSC_SUSP)
-                clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY;
-}
-#else
-static inline void check_geode_tsc_reliable(void) { }
-#endif
-
-
-void __init tsc_init(void)
-{
-        int cpu;
-
-        if (!cpu_has_tsc || tsc_disabled > 0)
-                return;
-
-        cpu_khz = calculate_cpu_khz();
-        tsc_khz = cpu_khz;
-
-        if (!cpu_khz) {
-                mark_tsc_unstable("could not calculate TSC khz");
-                return;
-        }
-
-        /* now allow native_sched_clock() to use rdtsc */
-        tsc_disabled = 0;
-
-        printk("Detected %lu.%03lu MHz processor.\n",
-                                (unsigned long)cpu_khz / 1000,
-                                (unsigned long)cpu_khz % 1000);
-
-        /*
-         * Secondary CPUs do not run through tsc_init(), so set up
-         * all the scale factors for all CPUs, assuming the same
-         * speed as the bootup CPU. (cpufreq notifiers will fix this
-         * up if their speed diverges)
-         */
-        for_each_possible_cpu(cpu)
-                set_cyc2ns_scale(cpu_khz, cpu);
-
-        use_tsc_delay();
-
-        /* Check and install the TSC clocksource */
-        dmi_check_system(bad_tsc_dmi_table);
-
-        unsynchronized_tsc();
-        check_geode_tsc_reliable();
-        current_tsc_khz = tsc_khz;
-        clocksource_tsc.mult = clocksource_khz2mult(current_tsc_khz,
-                                                        clocksource_tsc.shift);
-        /* lower the rating if we already know its unstable: */
-        if (check_tsc_unstable()) {
-                clocksource_tsc.rating = 0;
-                clocksource_tsc.flags &= ~CLOCK_SOURCE_IS_CONTINUOUS;
-        }
-        clocksource_register(&clocksource_tsc);
-}
diff --git a/arch/x86/kernel/tsc_64.c b/arch/x86/kernel/tsc_64.c
deleted file mode 100644
index 1784b8077a12..000000000000
--- a/arch/x86/kernel/tsc_64.c
+++ /dev/null
@@ -1,357 +0,0 @@
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/init.h>
-#include <linux/clocksource.h>
-#include <linux/time.h>
-#include <linux/acpi.h>
-#include <linux/cpufreq.h>
-#include <linux/acpi_pmtmr.h>
-
-#include <asm/hpet.h>
-#include <asm/timex.h>
-#include <asm/timer.h>
-#include <asm/vgtod.h>
-
-static int notsc __initdata = 0;
-
-unsigned int cpu_khz;           /* TSC clocks / usec, not used here */
-EXPORT_SYMBOL(cpu_khz);
-unsigned int tsc_khz;
-EXPORT_SYMBOL(tsc_khz);
-
-/* Accelerators for sched_clock()
- * convert from cycles(64bits) => nanoseconds (64bits)
- *  basic equation:
- *              ns = cycles / (freq / ns_per_sec)
- *              ns = cycles * (ns_per_sec / freq)
- *              ns = cycles * (10^9 / (cpu_khz * 10^3))
- *              ns = cycles * (10^6 / cpu_khz)
- *
- *      Then we use scaling math (suggested by george@mvista.com) to get:
- *              ns = cycles * (10^6 * SC / cpu_khz) / SC
- *              ns = cycles * cyc2ns_scale / SC
- *
- *      And since SC is a constant power of two, we can convert the div
- *  into a shift.
- *
- *  We can use khz divisor instead of mhz to keep a better precision, since
- *  cyc2ns_scale is limited to 10^6 * 2^10, which fits in 32 bits.
- *  (mathieu.desnoyers@polymtl.ca)
- *
- *                      -johnstul@us.ibm.com "math is hard, lets go shopping!"
- */
-DEFINE_PER_CPU(unsigned long, cyc2ns);
-
-static void set_cyc2ns_scale(unsigned long cpu_khz, int cpu)
-{
-        unsigned long long tsc_now, ns_now;
-        unsigned long flags, *scale;
-
-        local_irq_save(flags);
-        sched_clock_idle_sleep_event();
-
-        scale = &per_cpu(cyc2ns, cpu);
-
-        rdtscll(tsc_now);
-        ns_now = __cycles_2_ns(tsc_now);
-
-        if (cpu_khz)
-                *scale = (NSEC_PER_MSEC << CYC2NS_SCALE_FACTOR)/cpu_khz;
-
-        sched_clock_idle_wakeup_event(0);
-        local_irq_restore(flags);
-}
-
-unsigned long long native_sched_clock(void)
-{
-        unsigned long a = 0;
-
-        /* Could do CPU core sync here. Opteron can execute rdtsc speculatively,
-         * which means it is not completely exact and may not be monotonous
-         * between CPUs. But the errors should be too small to matter for
-         * scheduling purposes.
-         */
-
-        rdtscll(a);
-        return cycles_2_ns(a);
-}
-
-/* We need to define a real function for sched_clock, to override the
-   weak default version */
-#ifdef CONFIG_PARAVIRT
-unsigned long long sched_clock(void)
-{
-        return paravirt_sched_clock();
-}
-#else
-unsigned long long
-sched_clock(void) __attribute__((alias("native_sched_clock")));
-#endif
-
-
-static int tsc_unstable;
-
-int check_tsc_unstable(void)
-{
-        return tsc_unstable;
-}
-EXPORT_SYMBOL_GPL(check_tsc_unstable);
-
-#ifdef CONFIG_CPU_FREQ
-
-/* Frequency scaling support. Adjust the TSC based timer when the cpu frequency
- * changes.
- *
- * RED-PEN: On SMP we assume all CPUs run with the same frequency.  It's
- * not that important because current Opteron setups do not support
- * scaling on SMP anyroads.
- *
- * Should fix up last_tsc too. Currently gettimeofday in the
- * first tick after the change will be slightly wrong.
- */
-
-static unsigned int  ref_freq;
-static unsigned long loops_per_jiffy_ref;
-static unsigned long tsc_khz_ref;
-
-static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
-                                 void *data)
-{
-        struct cpufreq_freqs *freq = data;
-        unsigned long *lpj, dummy;
-
-        if (cpu_has(&cpu_data(freq->cpu), X86_FEATURE_CONSTANT_TSC))
-                return 0;
-
-        lpj = &dummy;
-        if (!(freq->flags & CPUFREQ_CONST_LOOPS))
-#ifdef CONFIG_SMP
-                lpj = &cpu_data(freq->cpu).loops_per_jiffy;
-#else
-                lpj = &boot_cpu_data.loops_per_jiffy;
-#endif
-
-        if (!ref_freq) {
-                ref_freq = freq->old;
-                loops_per_jiffy_ref = *lpj;
-                tsc_khz_ref = tsc_khz;
-        }
-        if ((val == CPUFREQ_PRECHANGE  && freq->old < freq->new) ||
-                (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) ||
-                (val == CPUFREQ_RESUMECHANGE)) {
-                *lpj =
-                cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new);
-
-                tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
-                if (!(freq->flags & CPUFREQ_CONST_LOOPS))
-                        mark_tsc_unstable("cpufreq changes");
-        }
-
-        set_cyc2ns_scale(tsc_khz_ref, freq->cpu);
-
-        return 0;
-}
-
-static struct notifier_block time_cpufreq_notifier_block = {
-        .notifier_call  = time_cpufreq_notifier
-};
-
-static int __init cpufreq_tsc(void)
-{
-        cpufreq_register_notifier(&time_cpufreq_notifier_block,
-                                  CPUFREQ_TRANSITION_NOTIFIER);
-        return 0;
-}
-
-core_initcall(cpufreq_tsc);
-
-#endif
-
-#define MAX_RETRIES     5
-#define SMI_TRESHOLD    50000
-
-/*
- * Read TSC and the reference counters. Take care of SMI disturbance
- */
-static unsigned long __init tsc_read_refs(unsigned long *pm,
-                                          unsigned long *hpet)
-{
-        unsigned long t1, t2;
-        int i;
-
-        for (i = 0; i < MAX_RETRIES; i++) {
-                t1 = get_cycles();
-                if (hpet)
-                        *hpet = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF;
-                else
-                        *pm = acpi_pm_read_early();
-                t2 = get_cycles();
-                if ((t2 - t1) < SMI_TRESHOLD)
-                        return t2;
-        }
-        return ULONG_MAX;
-}
-
-/**
- * tsc_calibrate - calibrate the tsc on boot
- */
-void __init tsc_calibrate(void)
-{
-        unsigned long flags, tsc1, tsc2, tr1, tr2, pm1, pm2, hpet1, hpet2;
-        int hpet = is_hpet_enabled(), cpu;
-
-        local_irq_save(flags);
-
-        tsc1 = tsc_read_refs(&pm1, hpet ? &hpet1 : NULL);
-
-        outb((inb(0x61) & ~0x02) | 0x01, 0x61);
-
-        outb(0xb0, 0x43);
-        outb((CLOCK_TICK_RATE / (1000 / 50)) & 0xff, 0x42);
-        outb((CLOCK_TICK_RATE / (1000 / 50)) >> 8, 0x42);
-        tr1 = get_cycles();
-        while ((inb(0x61) & 0x20) == 0);
-        tr2 = get_cycles();
-
-        tsc2 = tsc_read_refs(&pm2, hpet ? &hpet2 : NULL);
-
-        local_irq_restore(flags);
-
-        /*
-         * Preset the result with the raw and inaccurate PIT
-         * calibration value
-         */
-        tsc_khz = (tr2 - tr1) / 50;
-
-        /* hpet or pmtimer available ? */
-        if (!hpet && !pm1 && !pm2) {
-                printk(KERN_INFO "TSC calibrated against PIT\n");
-                goto out;
-        }
-
-        /* Check, whether the sampling was disturbed by an SMI */
-        if (tsc1 == ULONG_MAX || tsc2 == ULONG_MAX) {
-                printk(KERN_WARNING "TSC calibration disturbed by SMI, "
-                       "using PIT calibration result\n");
-                goto out;
-        }
-
-        tsc2 = (tsc2 - tsc1) * 1000000L;
-
-        if (hpet) {
-                printk(KERN_INFO "TSC calibrated against HPET\n");
-                if (hpet2 < hpet1)
-                        hpet2 += 0x100000000;
-                hpet2 -= hpet1;
-                tsc1 = (hpet2 * hpet_readl(HPET_PERIOD)) / 1000000;
-        } else {
-                printk(KERN_INFO "TSC calibrated against PM_TIMER\n");
-                if (pm2 < pm1)
-                        pm2 += ACPI_PM_OVRRUN;
-                pm2 -= pm1;
-                tsc1 = (pm2 * 1000000000) / PMTMR_TICKS_PER_SEC;
-        }
-
-        tsc_khz = tsc2 / tsc1;
-
-out:
-        for_each_possible_cpu(cpu)
-                set_cyc2ns_scale(tsc_khz, cpu);
-}
-
-/*
- * Make an educated guess if the TSC is trustworthy and synchronized
- * over all CPUs.
- */
-__cpuinit int unsynchronized_tsc(void)
-{
-        if (tsc_unstable)
-                return 1;
-
-#ifdef CONFIG_SMP
-        if (apic_is_clustered_box())
-                return 1;
-#endif
-
-        if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
-                return 0;
-
-        /* Assume multi socket systems are not synchronized */
-        return num_present_cpus() > 1;
-}
-
-int __init notsc_setup(char *s)
-{
-        notsc = 1;
-        return 1;
-}
-
-__setup("notsc", notsc_setup);
-
-static struct clocksource clocksource_tsc;
-
-/*
- * We compare the TSC to the cycle_last value in the clocksource
- * structure to avoid a nasty time-warp. This can be observed in a
- * very small window right after one CPU updated cycle_last under
- * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which
- * is smaller than the cycle_last reference value due to a TSC which
- * is slighty behind. This delta is nowhere else observable, but in
- * that case it results in a forward time jump in the range of hours
- * due to the unsigned delta calculation of the time keeping core
- * code, which is necessary to support wrapping clocksources like pm
- * timer.
- */
-static cycle_t read_tsc(void)
-{
-        cycle_t ret = (cycle_t)get_cycles();
-
-        return ret >= clocksource_tsc.cycle_last ?
-                ret : clocksource_tsc.cycle_last;
-}
-
-static cycle_t __vsyscall_fn vread_tsc(void)
-{
-        cycle_t ret = (cycle_t)vget_cycles();
-
-        return ret >= __vsyscall_gtod_data.clock.cycle_last ?
-                ret : __vsyscall_gtod_data.clock.cycle_last;
-}
-
-static struct clocksource clocksource_tsc = {
-        .name                   = "tsc",
-        .rating                 = 300,
-        .read                   = read_tsc,
-        .mask                   = CLOCKSOURCE_MASK(64),
-        .shift                  = 22,
-        .flags                  = CLOCK_SOURCE_IS_CONTINUOUS |
-                                  CLOCK_SOURCE_MUST_VERIFY,
-        .vread                  = vread_tsc,
-};
-
-void mark_tsc_unstable(char *reason)
-{
-        if (!tsc_unstable) {
-                tsc_unstable = 1;
-                printk("Marking TSC unstable due to %s\n", reason);
-                /* Change only the rating, when not registered */
-                if (clocksource_tsc.mult)
-                        clocksource_change_rating(&clocksource_tsc, 0);
-                else
-                        clocksource_tsc.rating = 0;
-        }
-}
-EXPORT_SYMBOL_GPL(mark_tsc_unstable);
-
-void __init init_tsc_clocksource(void)
-{
-        if (!notsc) {
-                clocksource_tsc.mult = clocksource_khz2mult(tsc_khz,
-                                                        clocksource_tsc.shift);
-                if (check_tsc_unstable())
-                        clocksource_tsc.rating = 0;
-
-                clocksource_register(&clocksource_tsc);
-        }
-}
diff --git a/arch/x86/kernel/visws_quirks.c b/arch/x86/kernel/visws_quirks.c
new file mode 100644
index 000000000000..e94bdb6add1d
--- /dev/null
+++ b/arch/x86/kernel/visws_quirks.c
@@ -0,0 +1,709 @@
+/*
+ *  SGI Visual Workstation support and quirks, unmaintained.
+ *
+ *  Split out from setup.c by davej@suse.de
+ *
+ *      Copyright (C) 1999 Bent Hagemark, Ingo Molnar
+ *
+ *  SGI Visual Workstation interrupt controller
+ *
+ *  The Cobalt system ASIC in the Visual Workstation contains a "Cobalt" APIC
+ *  which serves as the main interrupt controller in the system.  Non-legacy
+ *  hardware in the system uses this controller directly.  Legacy devices
+ *  are connected to the PIIX4 which in turn has its 8259(s) connected to
+ *  a of the Cobalt APIC entry.
+ *
+ *  09/02/2000 - Updated for 2.4 by jbarnes@sgi.com
+ *
+ *  25/11/2002 - Updated for 2.5 by Andrey Panin <pazke@orbita1.ru>
+ */
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/smp.h>
+
+#include <asm/visws/cobalt.h>
+#include <asm/visws/piix4.h>
+#include <asm/arch_hooks.h>
+#include <asm/fixmap.h>
+#include <asm/reboot.h>
+#include <asm/setup.h>
+#include <asm/e820.h>
+#include <asm/smp.h>
+#include <asm/io.h>
+
+#include <mach_ipi.h>
+
+#include "mach_apic.h"
+
+#include <linux/init.h>
+#include <linux/smp.h>
+
+#include <linux/kernel_stat.h>
+#include <linux/interrupt.h>
+#include <linux/init.h>
+
+#include <asm/io.h>
+#include <asm/apic.h>
+#include <asm/i8259.h>
+#include <asm/irq_vectors.h>
+#include <asm/visws/cobalt.h>
+#include <asm/visws/lithium.h>
+#include <asm/visws/piix4.h>
+
+#include <linux/sched.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/pci_ids.h>
+
+extern int no_broadcast;
+
+#include <asm/io.h>
+#include <asm/apic.h>
+#include <asm/arch_hooks.h>
+#include <asm/visws/cobalt.h>
+#include <asm/visws/lithium.h>
+
+char visws_board_type   = -1;
+char visws_board_rev    = -1;
+
+int is_visws_box(void)
+{
+        return visws_board_type >= 0;
+}
+
+static int __init visws_time_init_quirk(void)
+{
+        printk(KERN_INFO "Starting Cobalt Timer system clock\n");
+
+        /* Set the countdown value */
+        co_cpu_write(CO_CPU_TIMEVAL, CO_TIME_HZ/HZ);
+
+        /* Start the timer */
+        co_cpu_write(CO_CPU_CTRL, co_cpu_read(CO_CPU_CTRL) | CO_CTRL_TIMERUN);
+
+        /* Enable (unmask) the timer interrupt */
+        co_cpu_write(CO_CPU_CTRL, co_cpu_read(CO_CPU_CTRL) & ~CO_CTRL_TIMEMASK);
+
+        /*
+         * Zero return means the generic timer setup code will set up
+         * the standard vector:
+         */
+        return 0;
+}
+
+static int __init visws_pre_intr_init_quirk(void)
+{
+        init_VISWS_APIC_irqs();
+
+        /*
+         * We dont want ISA irqs to be set up by the generic code:
+         */
+        return 1;
+}
+
+/* Quirk for machine specific memory setup. */
+
+#define MB (1024 * 1024)
+
+unsigned long sgivwfb_mem_phys;
+unsigned long sgivwfb_mem_size;
+EXPORT_SYMBOL(sgivwfb_mem_phys);
+EXPORT_SYMBOL(sgivwfb_mem_size);
+
+long long mem_size __initdata = 0;
+
+static char * __init visws_memory_setup_quirk(void)
+{
+        long long gfx_mem_size = 8 * MB;
+
+        mem_size = boot_params.alt_mem_k;
+
+        if (!mem_size) {
+                printk(KERN_WARNING "Bootloader didn't set memory size, upgrade it !\n");
+                mem_size = 128 * MB;
+        }
+
+        /*
+         * this hardcodes the graphics memory to 8 MB
+         * it really should be sized dynamically (or at least
+         * set as a boot param)
+         */
+        if (!sgivwfb_mem_size) {
+                printk(KERN_WARNING "Defaulting to 8 MB framebuffer size\n");
+                sgivwfb_mem_size = 8 * MB;
+        }
+
+        /*
+         * Trim to nearest MB
+         */
+        sgivwfb_mem_size &= ~((1 << 20) - 1);
+        sgivwfb_mem_phys = mem_size - gfx_mem_size;
+
+        e820_add_region(0, LOWMEMSIZE(), E820_RAM);
+        e820_add_region(HIGH_MEMORY, mem_size - sgivwfb_mem_size - HIGH_MEMORY, E820_RAM);
+        e820_add_region(sgivwfb_mem_phys, sgivwfb_mem_size, E820_RESERVED);
+
+        return "PROM";
+}
+
+static void visws_machine_emergency_restart(void)
+{
+        /*
+         * Visual Workstations restart after this
+         * register is poked on the PIIX4
+         */
+        outb(PIIX4_RESET_VAL, PIIX4_RESET_PORT);
+}
+
+static void visws_machine_power_off(void)
+{
+        unsigned short pm_status;
+/*      extern unsigned int pci_bus0; */
+
+        while ((pm_status = inw(PMSTS_PORT)) & 0x100)
+                outw(pm_status, PMSTS_PORT);
+
+        outw(PM_SUSPEND_ENABLE, PMCNTRL_PORT);
+
+        mdelay(10);
+
+#define PCI_CONF1_ADDRESS(bus, devfn, reg) \
+        (0x80000000 | (bus << 16) | (devfn << 8) | (reg & ~3))
+
+/*      outl(PCI_CONF1_ADDRESS(pci_bus0, SPECIAL_DEV, SPECIAL_REG), 0xCF8); */
+        outl(PIIX_SPECIAL_STOP, 0xCFC);
+}
+
+static int __init visws_get_smp_config_quirk(unsigned int early)
+{
+        /*
+         * Prevent MP-table parsing by the generic code:
+         */
+        return 1;
+}
+
+extern unsigned int __cpuinitdata maxcpus;
+
+/*
+ * The Visual Workstation is Intel MP compliant in the hardware
+ * sense, but it doesn't have a BIOS(-configuration table).
+ * No problem for Linux.
+ */
+
+static void __init MP_processor_info (struct mpc_config_processor *m)
+{
+        int ver, logical_apicid;
+        physid_mask_t apic_cpus;
+
+        if (!(m->mpc_cpuflag & CPU_ENABLED))
+                return;
+
+        logical_apicid = m->mpc_apicid;
+        printk(KERN_INFO "%sCPU #%d %u:%u APIC version %d\n",
+               m->mpc_cpuflag & CPU_BOOTPROCESSOR ? "Bootup " : "",
+               m->mpc_apicid,
+               (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8,
+               (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4,
+               m->mpc_apicver);
+
+        if (m->mpc_cpuflag & CPU_BOOTPROCESSOR)
+                boot_cpu_physical_apicid = m->mpc_apicid;
+
+        ver = m->mpc_apicver;
+        if ((ver >= 0x14 && m->mpc_apicid >= 0xff) || m->mpc_apicid >= 0xf) {
+                printk(KERN_ERR "Processor #%d INVALID. (Max ID: %d).\n",
+                        m->mpc_apicid, MAX_APICS);
+                return;
+        }
+
+        apic_cpus = apicid_to_cpu_present(m->mpc_apicid);
+        physids_or(phys_cpu_present_map, phys_cpu_present_map, apic_cpus);
+        /*
+         * Validate version
+         */
+        if (ver == 0x0) {
+                printk(KERN_ERR "BIOS bug, APIC version is 0 for CPU#%d! "
+                        "fixing up to 0x10. (tell your hw vendor)\n",
+                        m->mpc_apicid);
+                ver = 0x10;
+        }
+        apic_version[m->mpc_apicid] = ver;
+}
+
+int __init visws_find_smp_config_quirk(unsigned int reserve)
+{
+        struct mpc_config_processor *mp = phys_to_virt(CO_CPU_TAB_PHYS);
+        unsigned short ncpus = readw(phys_to_virt(CO_CPU_NUM_PHYS));
+
+        if (ncpus > CO_CPU_MAX) {
+                printk(KERN_WARNING "find_visws_smp: got cpu count of %d at %p\n",
+                        ncpus, mp);
+
+                ncpus = CO_CPU_MAX;
+        }
+
+        if (ncpus > maxcpus)
+                ncpus = maxcpus;
+
+#ifdef CONFIG_X86_LOCAL_APIC
+        smp_found_config = 1;
+#endif
+        while (ncpus--)
+                MP_processor_info(mp++);
+
+        mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
+
+        return 1;
+}
+
+extern int visws_trap_init_quirk(void);
+
+void __init visws_early_detect(void)
+{
+        int raw;
+
+        visws_board_type = (char)(inb_p(PIIX_GPI_BD_REG) & PIIX_GPI_BD_REG)
+                                                         >> PIIX_GPI_BD_SHIFT;
+
+        if (visws_board_type < 0)
+                return;
+
+        /*
+         * Install special quirks for timer, interrupt and memory setup:
+         */
+        arch_time_init_quirk            = visws_time_init_quirk;
+        arch_pre_intr_init_quirk        = visws_pre_intr_init_quirk;
+        arch_memory_setup_quirk         = visws_memory_setup_quirk;
+
+        /*
+         * Fall back to generic behavior for traps:
+         */
+        arch_intr_init_quirk            = NULL;
+        arch_trap_init_quirk            = visws_trap_init_quirk;
+
+        /*
+         * Install reboot quirks:
+         */
+        pm_power_off                    = visws_machine_power_off;
+        machine_ops.emergency_restart   = visws_machine_emergency_restart;
+
+        /*
+         * Do not use broadcast IPIs:
+         */
+        no_broadcast = 0;
+
+        /*
+         * Override generic MP-table parsing:
+         */
+        mach_get_smp_config_quirk       = visws_get_smp_config_quirk;
+        mach_find_smp_config_quirk      = visws_find_smp_config_quirk;
+
+#ifdef CONFIG_X86_IO_APIC
+        /*
+         * Turn off IO-APIC detection and initialization:
+         */
+        skip_ioapic_setup               = 1;
+#endif
+
+        /*
+         * Get Board rev.
+         * First, we have to initialize the 307 part to allow us access
+         * to the GPIO registers.  Let's map them at 0x0fc0 which is right
+         * after the PIIX4 PM section.
+         */
+        outb_p(SIO_DEV_SEL, SIO_INDEX);
+        outb_p(SIO_GP_DEV, SIO_DATA);   /* Talk to GPIO regs. */
+
+        outb_p(SIO_DEV_MSB, SIO_INDEX);
+        outb_p(SIO_GP_MSB, SIO_DATA);   /* MSB of GPIO base address */
+
+        outb_p(SIO_DEV_LSB, SIO_INDEX);
+        outb_p(SIO_GP_LSB, SIO_DATA);   /* LSB of GPIO base address */
+
+        outb_p(SIO_DEV_ENB, SIO_INDEX);
+        outb_p(1, SIO_DATA);            /* Enable GPIO registers. */
+
+        /*
+         * Now, we have to map the power management section to write
+         * a bit which enables access to the GPIO registers.
+         * What lunatic came up with this shit?
+         */
+        outb_p(SIO_DEV_SEL, SIO_INDEX);
+        outb_p(SIO_PM_DEV, SIO_DATA);   /* Talk to GPIO regs. */
+
+        outb_p(SIO_DEV_MSB, SIO_INDEX);
+        outb_p(SIO_PM_MSB, SIO_DATA);   /* MSB of PM base address */
+
+        outb_p(SIO_DEV_LSB, SIO_INDEX);
+        outb_p(SIO_PM_LSB, SIO_DATA);   /* LSB of PM base address */
+
+        outb_p(SIO_DEV_ENB, SIO_INDEX);
+        outb_p(1, SIO_DATA);            /* Enable PM registers. */
+
+        /*
+         * Now, write the PM register which enables the GPIO registers.
+         */
+        outb_p(SIO_PM_FER2, SIO_PM_INDEX);
+        outb_p(SIO_PM_GP_EN, SIO_PM_DATA);
+
+        /*
+         * Now, initialize the GPIO registers.
+         * We want them all to be inputs which is the
+         * power on default, so let's leave them alone.
+         * So, let's just read the board rev!
+         */
+        raw = inb_p(SIO_GP_DATA1);
+        raw &= 0x7f;    /* 7 bits of valid board revision ID. */
+
+        if (visws_board_type == VISWS_320) {
+                if (raw < 0x6) {
+                        visws_board_rev = 4;
+                } else if (raw < 0xc) {
+                        visws_board_rev = 5;
+                } else {
+                        visws_board_rev = 6;
+                }
+        } else if (visws_board_type == VISWS_540) {
+                        visws_board_rev = 2;
+                } else {
+                        visws_board_rev = raw;
+                }
+
+        printk(KERN_INFO "Silicon Graphics Visual Workstation %s (rev %d) detected\n",
+               (visws_board_type == VISWS_320 ? "320" :
+               (visws_board_type == VISWS_540 ? "540" :
+                "unknown")), visws_board_rev);
+}
+
+#define A01234 (LI_INTA_0 | LI_INTA_1 | LI_INTA_2 | LI_INTA_3 | LI_INTA_4)
+#define BCD (LI_INTB | LI_INTC | LI_INTD)
+#define ALLDEVS (A01234 | BCD)
+
+static __init void lithium_init(void)
+{
+        set_fixmap(FIX_LI_PCIA, LI_PCI_A_PHYS);
+        set_fixmap(FIX_LI_PCIB, LI_PCI_B_PHYS);
+
+        if ((li_pcia_read16(PCI_VENDOR_ID) != PCI_VENDOR_ID_SGI) ||
+            (li_pcia_read16(PCI_DEVICE_ID) != PCI_DEVICE_ID_SGI_LITHIUM)) {
+                printk(KERN_EMERG "Lithium hostbridge %c not found\n", 'A');
+/*              panic("This machine is not SGI Visual Workstation 320/540"); */
+        }
+
+        if ((li_pcib_read16(PCI_VENDOR_ID) != PCI_VENDOR_ID_SGI) ||
+            (li_pcib_read16(PCI_DEVICE_ID) != PCI_DEVICE_ID_SGI_LITHIUM)) {
+                printk(KERN_EMERG "Lithium hostbridge %c not found\n", 'B');
+/*              panic("This machine is not SGI Visual Workstation 320/540"); */
+        }
+
+        li_pcia_write16(LI_PCI_INTEN, ALLDEVS);
+        li_pcib_write16(LI_PCI_INTEN, ALLDEVS);
+}
+
+static __init void cobalt_init(void)
+{
+        /*
+         * On normal SMP PC this is used only with SMP, but we have to
+         * use it and set it up here to start the Cobalt clock
+         */
+        set_fixmap(FIX_APIC_BASE, APIC_DEFAULT_PHYS_BASE);
+        setup_local_APIC();
+        printk(KERN_INFO "Local APIC Version %#x, ID %#x\n",
+                (unsigned int)apic_read(APIC_LVR),
+                (unsigned int)apic_read(APIC_ID));
+
+        set_fixmap(FIX_CO_CPU, CO_CPU_PHYS);
+        set_fixmap(FIX_CO_APIC, CO_APIC_PHYS);
+        printk(KERN_INFO "Cobalt Revision %#lx, APIC ID %#lx\n",
+                co_cpu_read(CO_CPU_REV), co_apic_read(CO_APIC_ID));
+
+        /* Enable Cobalt APIC being careful to NOT change the ID! */
+        co_apic_write(CO_APIC_ID, co_apic_read(CO_APIC_ID) | CO_APIC_ENABLE);
+
+        printk(KERN_INFO "Cobalt APIC enabled: ID reg %#lx\n",
+                co_apic_read(CO_APIC_ID));
+}
+
+int __init visws_trap_init_quirk(void)
+{
+        lithium_init();
+        cobalt_init();
+
+        return 1;
+}
+
+/*
+ * IRQ controller / APIC support:
+ */
+
+static DEFINE_SPINLOCK(cobalt_lock);
+
+/*
+ * Set the given Cobalt APIC Redirection Table entry to point
+ * to the given IDT vector/index.
+ */
+static inline void co_apic_set(int entry, int irq)
+{
+        co_apic_write(CO_APIC_LO(entry), CO_APIC_LEVEL | (irq + FIRST_EXTERNAL_VECTOR));
+        co_apic_write(CO_APIC_HI(entry), 0);
+}
+
+/*
+ * Cobalt (IO)-APIC functions to handle PCI devices.
+ */
+static inline int co_apic_ide0_hack(void)
+{
+        extern char visws_board_type;
+        extern char visws_board_rev;
+
+        if (visws_board_type == VISWS_320 && visws_board_rev == 5)
+                return 5;
+        return CO_APIC_IDE0;
+}
+
+static int is_co_apic(unsigned int irq)
+{
+        if (IS_CO_APIC(irq))
+                return CO_APIC(irq);
+
+        switch (irq) {
+                case 0: return CO_APIC_CPU;
+                case CO_IRQ_IDE0: return co_apic_ide0_hack();
+                case CO_IRQ_IDE1: return CO_APIC_IDE1;
+                default: return -1;
+        }
+}
+
+
+/*
+ * This is the SGI Cobalt (IO-)APIC:
+ */
+
+static void enable_cobalt_irq(unsigned int irq)
+{
+        co_apic_set(is_co_apic(irq), irq);
+}
+
+static void disable_cobalt_irq(unsigned int irq)
+{
+        int entry = is_co_apic(irq);
+
+        co_apic_write(CO_APIC_LO(entry), CO_APIC_MASK);
+        co_apic_read(CO_APIC_LO(entry));
+}
+
+/*
+ * "irq" really just serves to identify the device.  Here is where we
+ * map this to the Cobalt APIC entry where it's physically wired.
+ * This is called via request_irq -> setup_irq -> irq_desc->startup()
+ */
+static unsigned int startup_cobalt_irq(unsigned int irq)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&cobalt_lock, flags);
+        if ((irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS | IRQ_WAITING)))
+                irq_desc[irq].status &= ~(IRQ_DISABLED | IRQ_INPROGRESS | IRQ_WAITING);
+        enable_cobalt_irq(irq);
+        spin_unlock_irqrestore(&cobalt_lock, flags);
+        return 0;
+}
+
+static void ack_cobalt_irq(unsigned int irq)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&cobalt_lock, flags);
+        disable_cobalt_irq(irq);
+        apic_write(APIC_EOI, APIC_EIO_ACK);
+        spin_unlock_irqrestore(&cobalt_lock, flags);
+}
+
+static void end_cobalt_irq(unsigned int irq)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&cobalt_lock, flags);
+        if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
+                enable_cobalt_irq(irq);
+        spin_unlock_irqrestore(&cobalt_lock, flags);
+}
+
+static struct irq_chip cobalt_irq_type = {
+        .typename =     "Cobalt-APIC",
+        .startup =      startup_cobalt_irq,
+        .shutdown =     disable_cobalt_irq,
+        .enable =       enable_cobalt_irq,
+        .disable =      disable_cobalt_irq,
+        .ack =          ack_cobalt_irq,
+        .end =          end_cobalt_irq,
+};
+
+
+/*
+ * This is the PIIX4-based 8259 that is wired up indirectly to Cobalt
+ * -- not the manner expected by the code in i8259.c.
+ *
+ * there is a 'master' physical interrupt source that gets sent to
+ * the CPU. But in the chipset there are various 'virtual' interrupts
+ * waiting to be handled. We represent this to Linux through a 'master'
+ * interrupt controller type, and through a special virtual interrupt-
+ * controller. Device drivers only see the virtual interrupt sources.
+ */
+static unsigned int startup_piix4_master_irq(unsigned int irq)
+{
+        init_8259A(0);
+
+        return startup_cobalt_irq(irq);
+}
+
+static void end_piix4_master_irq(unsigned int irq)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&cobalt_lock, flags);
+        enable_cobalt_irq(irq);
+        spin_unlock_irqrestore(&cobalt_lock, flags);
+}
+
+static struct irq_chip piix4_master_irq_type = {
+        .typename =     "PIIX4-master",
+        .startup =      startup_piix4_master_irq,
+        .ack =          ack_cobalt_irq,
+        .end =          end_piix4_master_irq,
+};
+
+
+static struct irq_chip piix4_virtual_irq_type = {
+        .typename =     "PIIX4-virtual",
+        .shutdown =     disable_8259A_irq,
+        .enable =       enable_8259A_irq,
+        .disable =      disable_8259A_irq,
+};
+
+
+/*
+ * PIIX4-8259 master/virtual functions to handle interrupt requests
+ * from legacy devices: floppy, parallel, serial, rtc.
+ *
+ * None of these get Cobalt APIC entries, neither do they have IDT
+ * entries. These interrupts are purely virtual and distributed from
+ * the 'master' interrupt source: CO_IRQ_8259.
+ *
+ * When the 8259 interrupts its handler figures out which of these
+ * devices is interrupting and dispatches to its handler.
+ *
+ * CAREFUL: devices see the 'virtual' interrupt only. Thus disable/
+ * enable_irq gets the right irq. This 'master' irq is never directly
+ * manipulated by any driver.
+ */
+static irqreturn_t piix4_master_intr(int irq, void *dev_id)
+{
+        int realirq;
+        irq_desc_t *desc;
+        unsigned long flags;
+
+        spin_lock_irqsave(&i8259A_lock, flags);
+
+        /* Find out what's interrupting in the PIIX4 master 8259 */
+        outb(0x0c, 0x20);               /* OCW3 Poll command */
+        realirq = inb(0x20);
+
+        /*
+         * Bit 7 == 0 means invalid/spurious
+         */
+        if (unlikely(!(realirq & 0x80)))
+                goto out_unlock;
+
+        realirq &= 7;
+
+        if (unlikely(realirq == 2)) {
+                outb(0x0c, 0xa0);
+                realirq = inb(0xa0);
+
+                if (unlikely(!(realirq & 0x80)))
+                        goto out_unlock;
+
+                realirq = (realirq & 7) + 8;
+        }
+
+        /* mask and ack interrupt */
+        cached_irq_mask |= 1 << realirq;
+        if (unlikely(realirq > 7)) {
+                inb(0xa1);
+                outb(cached_slave_mask, 0xa1);
+                outb(0x60 + (realirq & 7), 0xa0);
+                outb(0x60 + 2, 0x20);
+        } else {
+                inb(0x21);
+                outb(cached_master_mask, 0x21);
+                outb(0x60 + realirq, 0x20);
+        }
+
+        spin_unlock_irqrestore(&i8259A_lock, flags);
+
+        desc = irq_desc + realirq;
+
+        /*
+         * handle this 'virtual interrupt' as a Cobalt one now.
+         */
+        kstat_cpu(smp_processor_id()).irqs[realirq]++;
+
+        if (likely(desc->action != NULL))
+                handle_IRQ_event(realirq, desc->action);
+
+        if (!(desc->status & IRQ_DISABLED))
+                enable_8259A_irq(realirq);
+
+        return IRQ_HANDLED;
+
+out_unlock:
+        spin_unlock_irqrestore(&i8259A_lock, flags);
+        return IRQ_NONE;
+}
+
+static struct irqaction master_action = {
+        .handler =      piix4_master_intr,
+        .name =         "PIIX4-8259",
+};
+
+static struct irqaction cascade_action = {
+        .handler =      no_action,
+        .name =         "cascade",
+};
+
+
+void init_VISWS_APIC_irqs(void)
+{
+        int i;
+
+        for (i = 0; i < CO_IRQ_APIC0 + CO_APIC_LAST + 1; i++) {
+                irq_desc[i].status = IRQ_DISABLED;
+                irq_desc[i].action = 0;
+                irq_desc[i].depth = 1;
+
+                if (i == 0) {
+                        irq_desc[i].chip = &cobalt_irq_type;
+                }
+                else if (i == CO_IRQ_IDE0) {
+                        irq_desc[i].chip = &cobalt_irq_type;
+                }
+                else if (i == CO_IRQ_IDE1) {
+                        irq_desc[i].chip = &cobalt_irq_type;
+                }
+                else if (i == CO_IRQ_8259) {
+                        irq_desc[i].chip = &piix4_master_irq_type;
+                }
+                else if (i < CO_IRQ_APIC0) {
+                        irq_desc[i].chip = &piix4_virtual_irq_type;
+                }
+                else if (IS_CO_APIC(i)) {
+                        irq_desc[i].chip = &cobalt_irq_type;
+                }
+        }
+
+        setup_irq(CO_IRQ_8259, &master_action);
+        setup_irq(2, &cascade_action);
+}
diff --git a/arch/x86/kernel/vmi_32.c b/arch/x86/kernel/vmi_32.c
index 956f38927aa7..b15346092b7b 100644
--- a/arch/x86/kernel/vmi_32.c
+++ b/arch/x86/kernel/vmi_32.c
@@ -151,7 +151,7 @@ static unsigned vmi_patch(u8 type, u16 clobbers, void *insns,
                                               insns, ip);
                 case PARAVIRT_PATCH(pv_cpu_ops.iret):
                         return patch_internal(VMI_CALL_IRET, len, insns, ip);
-                case PARAVIRT_PATCH(pv_cpu_ops.irq_enable_syscall_ret):
+                case PARAVIRT_PATCH(pv_cpu_ops.irq_enable_sysexit):
                         return patch_internal(VMI_CALL_SYSEXIT, len, insns, ip);
                 default:
                         break;
@@ -896,7 +896,7 @@ static inline int __init activate_vmi(void)
          * the backend.  They are performance critical anyway, so requiring
          * a patch is not a big problem.
          */
-        pv_cpu_ops.irq_enable_syscall_ret = (void *)0xfeedbab0;
+        pv_cpu_ops.irq_enable_sysexit = (void *)0xfeedbab0;
         pv_cpu_ops.iret = (void *)0xbadbab0;
 
 #ifdef CONFIG_SMP
@@ -932,7 +932,7 @@ static inline int __init activate_vmi(void)
                 pv_apic_ops.setup_secondary_clock = vmi_time_ap_init;
 #endif
                 pv_time_ops.sched_clock = vmi_sched_clock;
-                pv_time_ops.get_cpu_khz = vmi_cpu_khz;
+                pv_time_ops.get_tsc_khz = vmi_tsc_khz;
 
                 /* We have true wallclock functions; disable CMOS clock sync */
                 no_sync_cmos_clock = 1;
diff --git a/arch/x86/kernel/vmiclock_32.c b/arch/x86/kernel/vmiclock_32.c
index a2b030780aa9..6953859fe289 100644
--- a/arch/x86/kernel/vmiclock_32.c
+++ b/arch/x86/kernel/vmiclock_32.c
@@ -33,8 +33,7 @@
 #include <asm/apic.h>
 #include <asm/timer.h>
 #include <asm/i8253.h>
-
-#include <irq_vectors.h>
+#include <asm/irq_vectors.h>
 
 #define VMI_ONESHOT  (VMI_ALARM_IS_ONESHOT  | VMI_CYCLES_REAL | vmi_get_alarm_wiring())
 #define VMI_PERIODIC (VMI_ALARM_IS_PERIODIC | VMI_CYCLES_REAL | vmi_get_alarm_wiring())
@@ -70,8 +69,8 @@ unsigned long long vmi_sched_clock(void)
         return cycles_2_ns(vmi_timer_ops.get_cycle_counter(VMI_CYCLES_AVAILABLE));
 }
 
-/* paravirt_ops.get_cpu_khz = vmi_cpu_khz */
-unsigned long vmi_cpu_khz(void)
+/* paravirt_ops.get_tsc_khz = vmi_tsc_khz */
+unsigned long vmi_tsc_khz(void)
 {
         unsigned long long khz;
         khz = vmi_timer_ops.get_cycle_frequency();
diff --git a/arch/x86/kernel/vmlinux_32.lds.S b/arch/x86/kernel/vmlinux_32.lds.S
index ce5ed083a1e9..cdb2363697d2 100644
--- a/arch/x86/kernel/vmlinux_32.lds.S
+++ b/arch/x86/kernel/vmlinux_32.lds.S
@@ -49,23 +49,14 @@ SECTIONS
         _etext = .;                     /* End of text section */
   } :text = 0x9090
 
+  NOTES :text :note
+
   . = ALIGN(16);                /* Exception table */
   __ex_table : AT(ADDR(__ex_table) - LOAD_OFFSET) {
         __start___ex_table = .;
          *(__ex_table)
         __stop___ex_table = .;
-  }
-
-  NOTES :text :note
-
-  BUG_TABLE :text
-
-  . = ALIGN(4);
-  .tracedata : AT(ADDR(.tracedata) - LOAD_OFFSET) {
-        __tracedata_start = .;
-        *(.tracedata)
-        __tracedata_end = .;
-  }
+  } :text = 0x9090
 
   RODATA
 
diff --git a/arch/x86/kernel/vmlinux_64.lds.S b/arch/x86/kernel/vmlinux_64.lds.S
index fad3674b06a5..63e5c1a22e88 100644
--- a/arch/x86/kernel/vmlinux_64.lds.S
+++ b/arch/x86/kernel/vmlinux_64.lds.S
@@ -19,7 +19,7 @@ PHDRS {
         data PT_LOAD FLAGS(7);  /* RWE */
         user PT_LOAD FLAGS(7);  /* RWE */
         data.init PT_LOAD FLAGS(7);     /* RWE */
-        note PT_NOTE FLAGS(4);  /* R__ */
+        note PT_NOTE FLAGS(0);  /* ___ */
 }
 SECTIONS
 {
@@ -40,26 +40,17 @@ SECTIONS
         _etext = .;             /* End of text section */
   } :text = 0x9090
 
+  NOTES :text :note
+
   . = ALIGN(16);                /* Exception table */
   __ex_table : AT(ADDR(__ex_table) - LOAD_OFFSET) {
         __start___ex_table = .;
          *(__ex_table)
         __stop___ex_table = .;
-  }
-
-  NOTES :text :note
-
-  BUG_TABLE :text
+  } :text = 0x9090
 
   RODATA
 
-  . = ALIGN(4);
-  .tracedata : AT(ADDR(.tracedata) - LOAD_OFFSET) {
-        __tracedata_start = .;
-        *(.tracedata)
-        __tracedata_end = .;
-  }
-
   . = ALIGN(PAGE_SIZE);         /* Align data segment to page size boundary */
                                 /* Data */
   .data : AT(ADDR(.data) - LOAD_OFFSET) {
@@ -177,6 +168,7 @@ SECTIONS
         *(.con_initcall.init)
   }
   __con_initcall_end = .;
+  . = ALIGN(16);
   __x86cpuvendor_start = .;
   .x86cpuvendor.init : AT(ADDR(.x86cpuvendor.init) - LOAD_OFFSET) {
         *(.x86cpuvendor.init)
diff --git a/arch/x86/kernel/vsmp_64.c b/arch/x86/kernel/vsmp_64.c
index ba8c0b75ab0a..0c029e8959c7 100644
--- a/arch/x86/kernel/vsmp_64.c
+++ b/arch/x86/kernel/vsmp_64.c
@@ -15,9 +15,12 @@
 #include <linux/init.h>
 #include <linux/pci_ids.h>
 #include <linux/pci_regs.h>
+
+#include <asm/apic.h>
 #include <asm/pci-direct.h>
 #include <asm/io.h>
 #include <asm/paravirt.h>
+#include <asm/setup.h>
 
 #if defined CONFIG_PCI && defined CONFIG_PARAVIRT
 /*
diff --git a/arch/x86/kernel/vsyscall_64.c b/arch/x86/kernel/vsyscall_64.c
index 61efa2f7d564..e50740d32314 100644
--- a/arch/x86/kernel/vsyscall_64.c
+++ b/arch/x86/kernel/vsyscall_64.c
@@ -42,7 +42,8 @@
 #include <asm/topology.h>
 #include <asm/vgtod.h>
 
-#define __vsyscall(nr) __attribute__ ((unused,__section__(".vsyscall_" #nr)))
+#define __vsyscall(nr) \
+                __attribute__ ((unused, __section__(".vsyscall_" #nr))) notrace
 #define __syscall_clobber "r11","cx","memory"
 
 /*
@@ -249,7 +250,7 @@ static ctl_table kernel_root_table2[] = {
    doesn't violate that. We'll find out if it does. */
 static void __cpuinit vsyscall_set_cpu(int cpu)
 {
-        unsigned long *d;
+        unsigned long d;
         unsigned long node = 0;
 #ifdef CONFIG_NUMA
         node = cpu_to_node(cpu);
@@ -260,11 +261,11 @@ static void __cpuinit vsyscall_set_cpu(int cpu)
         /* Store cpu number in limit so that it can be loaded quickly
            in user space in vgetcpu.
            12 bits for the CPU and 8 bits for the node. */
-        d = (unsigned long *)(get_cpu_gdt_table(cpu) + GDT_ENTRY_PER_CPU);
-        *d = 0x0f40000000000ULL;
-        *d |= cpu;
-        *d |= (node & 0xf) << 12;
-        *d |= (node >> 4) << 48;
+        d = 0x0f40000000000ULL;
+        d |= cpu;
+        d |= (node & 0xf) << 12;
+        d |= (node >> 4) << 48;
+        write_gdt_entry(get_cpu_gdt_table(cpu), GDT_ENTRY_PER_CPU, &d, DESCTYPE_S);
 }
 
 static void __cpuinit cpu_vsyscall_init(void *arg)
diff --git a/arch/x86/kernel/x8664_ksyms_64.c b/arch/x86/kernel/x8664_ksyms_64.c
index f6c05d0410fb..b545f371b5f5 100644
--- a/arch/x86/kernel/x8664_ksyms_64.c
+++ b/arch/x86/kernel/x8664_ksyms_64.c
@@ -2,13 +2,20 @@
    All C exports should go in the respective C files. */
 
 #include <linux/module.h>
-#include <net/checksum.h>
 #include <linux/smp.h>
 
+#include <net/checksum.h>
+
 #include <asm/processor.h>
-#include <asm/uaccess.h>
 #include <asm/pgtable.h>
+#include <asm/uaccess.h>
 #include <asm/desc.h>
+#include <asm/ftrace.h>
+
+#ifdef CONFIG_FTRACE
+/* mcount is defined in assembly */
+EXPORT_SYMBOL(mcount);
+#endif
 
 EXPORT_SYMBOL(kernel_thread);
 
@@ -53,8 +60,3 @@ EXPORT_SYMBOL(init_level4_pgt);
 EXPORT_SYMBOL(load_gs_index);
 
 EXPORT_SYMBOL(_proxy_pda);
-
-#ifdef CONFIG_PARAVIRT
-/* Virtualized guests may want to use it */
-EXPORT_SYMBOL_GPL(cpu_gdt_descr);
-#endif
diff --git a/arch/x86/lguest/Kconfig b/arch/x86/lguest/Kconfig
index 964dfa36d367..c70e12b1a637 100644
--- a/arch/x86/lguest/Kconfig
+++ b/arch/x86/lguest/Kconfig
@@ -3,7 +3,7 @@ config LGUEST_GUEST
         select PARAVIRT
         depends on X86_32
         depends on !X86_PAE
-        depends on !(X86_VISWS || X86_VOYAGER)
+        depends on !X86_VOYAGER
         select VIRTIO
         select VIRTIO_RING
         select VIRTIO_CONSOLE
diff --git a/arch/x86/lguest/boot.c b/arch/x86/lguest/boot.c
index 5c7e2fd52075..50dad44fb542 100644
--- a/arch/x86/lguest/boot.c
+++ b/arch/x86/lguest/boot.c
@@ -607,7 +607,7 @@ static unsigned long lguest_get_wallclock(void)
  * what speed it runs at, or 0 if it's unusable as a reliable clock source.
  * This matches what we want here: if we return 0 from this function, the x86
  * TSC clock will give up and not register itself. */
-static unsigned long lguest_cpu_khz(void)
+static unsigned long lguest_tsc_khz(void)
 {
         return lguest_data.tsc_khz;
 }
@@ -835,7 +835,7 @@ static __init char *lguest_memory_setup(void)
 
         /* The Linux bootloader header contains an "e820" memory map: the
          * Launcher populated the first entry with our memory limit. */
-        add_memory_region(boot_params.e820_map[0].addr,
+        e820_add_region(boot_params.e820_map[0].addr,
                           boot_params.e820_map[0].size,
                           boot_params.e820_map[0].type);
 
@@ -998,7 +998,7 @@ __init void lguest_init(void)
         /* time operations */
         pv_time_ops.get_wallclock = lguest_get_wallclock;
         pv_time_ops.time_init = lguest_time_init;
-        pv_time_ops.get_cpu_khz = lguest_cpu_khz;
+        pv_time_ops.get_tsc_khz = lguest_tsc_khz;
 
         /* Now is a good time to look at the implementations of these functions
          * before returning to the rest of lguest_init(). */
@@ -1012,6 +1012,7 @@ __init void lguest_init(void)
          * clobbered.  The Launcher places our initial pagetables somewhere at
          * the top of our physical memory, so we don't need extra space: set
          * init_pg_tables_end to the end of the kernel. */
+        init_pg_tables_start = __pa(pg0);
         init_pg_tables_end = __pa(pg0);
 
         /* Load the %fs segment register (the per-cpu segment register) with
@@ -1065,9 +1066,9 @@ __init void lguest_init(void)
         pm_power_off = lguest_power_off;
         machine_ops.restart = lguest_restart;
 
-        /* Now we're set up, call start_kernel() in init/main.c and we proceed
+        /* Now we're set up, call i386_start_kernel() in head32.c and we proceed
          * to boot as normal.  It never returns. */
-        start_kernel();
+        i386_start_kernel();
 }
 /*
  * This marks the end of stage II of our journey, The Guest.
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index 76f60f52a885..aa3fa4119424 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -4,8 +4,9 @@
 
 obj-$(CONFIG_SMP) := msr-on-cpu.o
 
-lib-y := delay_$(BITS).o
-lib-y += usercopy_$(BITS).o getuser_$(BITS).o putuser_$(BITS).o
+lib-y := delay.o
+lib-y += thunk_$(BITS).o
+lib-y += usercopy_$(BITS).o getuser.o putuser.o
 lib-y += memcpy_$(BITS).o
 
 ifeq ($(CONFIG_X86_32),y)
diff --git a/arch/x86/lib/copy_user_64.S b/arch/x86/lib/copy_user_64.S
index ee1c3f635157..dfdf428975c0 100644
--- a/arch/x86/lib/copy_user_64.S
+++ b/arch/x86/lib/copy_user_64.S
@@ -1,8 +1,10 @@
-/* Copyright 2002 Andi Kleen, SuSE Labs.
+/*
+ * Copyright 2008 Vitaly Mayatskikh <vmayatsk@redhat.com>
+ * Copyright 2002 Andi Kleen, SuSE Labs.
  * Subject to the GNU Public License v2.
- * 
- * Functions to copy from and to user space.            
- */              
+ *
+ * Functions to copy from and to user space.
+ */
 
 #include <linux/linkage.h>
 #include <asm/dwarf2.h>
@@ -20,60 +22,88 @@
         .long \orig-1f  /* by default jump to orig */
 1:
         .section .altinstr_replacement,"ax"
-2:      .byte 0xe9                   /* near jump with 32bit immediate */
+2:      .byte 0xe9                      /* near jump with 32bit immediate */
         .long \alt-1b /* offset */   /* or alternatively to alt */
         .previous
         .section .altinstructions,"a"
         .align 8
         .quad  0b
         .quad  2b
-        .byte  \feature              /* when feature is set */
+        .byte  \feature                 /* when feature is set */
         .byte  5
         .byte  5
         .previous
         .endm
 
-/* Standard copy_to_user with segment limit checking */         
+        .macro ALIGN_DESTINATION
+#ifdef FIX_ALIGNMENT
+        /* check for bad alignment of destination */
+        movl %edi,%ecx
+        andl $7,%ecx
+        jz 102f                         /* already aligned */
+        subl $8,%ecx
+        negl %ecx
+        subl %ecx,%edx
+100:    movb (%rsi),%al
+101:    movb %al,(%rdi)
+        incq %rsi
+        incq %rdi
+        decl %ecx
+        jnz 100b
+102:
+        .section .fixup,"ax"
+103:    addl %r8d,%edx                  /* ecx is zerorest also */
+        jmp copy_user_handle_tail
+        .previous
+
+        .section __ex_table,"a"
+        .align 8
+        .quad 100b,103b
+        .quad 101b,103b
+        .previous
+#endif
+        .endm
+
+/* Standard copy_to_user with segment limit checking */
 ENTRY(copy_to_user)
         CFI_STARTPROC
         GET_THREAD_INFO(%rax)
         movq %rdi,%rcx
         addq %rdx,%rcx
-        jc  bad_to_user
-        cmpq threadinfo_addr_limit(%rax),%rcx
+        jc bad_to_user
+        cmpq TI_addr_limit(%rax),%rcx
         jae bad_to_user
-        xorl %eax,%eax  /* clear zero flag */
         ALTERNATIVE_JUMP X86_FEATURE_REP_GOOD,copy_user_generic_unrolled,copy_user_generic_string
         CFI_ENDPROC
 
-ENTRY(copy_user_generic)
+/* Standard copy_from_user with segment limit checking */
+ENTRY(copy_from_user)
         CFI_STARTPROC
-        movl $1,%ecx    /* set zero flag */
+        GET_THREAD_INFO(%rax)
+        movq %rsi,%rcx
+        addq %rdx,%rcx
+        jc bad_from_user
+        cmpq TI_addr_limit(%rax),%rcx
+        jae bad_from_user
         ALTERNATIVE_JUMP X86_FEATURE_REP_GOOD,copy_user_generic_unrolled,copy_user_generic_string
         CFI_ENDPROC
+ENDPROC(copy_from_user)
 
-ENTRY(__copy_from_user_inatomic)
+ENTRY(copy_user_generic)
         CFI_STARTPROC
-        xorl %ecx,%ecx  /* clear zero flag */
         ALTERNATIVE_JUMP X86_FEATURE_REP_GOOD,copy_user_generic_unrolled,copy_user_generic_string
         CFI_ENDPROC
+ENDPROC(copy_user_generic)
 
-/* Standard copy_from_user with segment limit checking */       
-ENTRY(copy_from_user)
+ENTRY(__copy_from_user_inatomic)
         CFI_STARTPROC
-        GET_THREAD_INFO(%rax)
-        movq %rsi,%rcx
-        addq %rdx,%rcx
-        jc  bad_from_user
-        cmpq threadinfo_addr_limit(%rax),%rcx
-        jae  bad_from_user
-        movl $1,%ecx    /* set zero flag */
         ALTERNATIVE_JUMP X86_FEATURE_REP_GOOD,copy_user_generic_unrolled,copy_user_generic_string
         CFI_ENDPROC
-ENDPROC(copy_from_user)
-        
+ENDPROC(__copy_from_user_inatomic)
+
         .section .fixup,"ax"
         /* must zero dest */
+ENTRY(bad_from_user)
 bad_from_user:
         CFI_STARTPROC
         movl %edx,%ecx
@@ -81,271 +111,158 @@ bad_from_user:
         rep
         stosb
 bad_to_user:
-        movl    %edx,%eax
+        movl %edx,%eax
         ret
         CFI_ENDPROC
-END(bad_from_user)
+ENDPROC(bad_from_user)
         .previous
-        
-                
+
 /*
  * copy_user_generic_unrolled - memory copy with exception handling.
- * This version is for CPUs like P4 that don't have efficient micro code for rep movsq
- *      
- * Input:       
+ * This version is for CPUs like P4 that don't have efficient micro
+ * code for rep movsq
+ *
+ * Input:
  * rdi destination
  * rsi source
  * rdx count
- * ecx zero flag -- if true zero destination on error
  *
- * Output:              
- * eax uncopied bytes or 0 if successful.
+ * Output:
+ * eax uncopied bytes or 0 if successfull.
  */
 ENTRY(copy_user_generic_unrolled)
         CFI_STARTPROC
-        pushq %rbx
-        CFI_ADJUST_CFA_OFFSET 8
-        CFI_REL_OFFSET rbx, 0
-        pushq %rcx
-        CFI_ADJUST_CFA_OFFSET 8
-        CFI_REL_OFFSET rcx, 0
-        xorl %eax,%eax          /*zero for the exception handler */
-
-#ifdef FIX_ALIGNMENT
-        /* check for bad alignment of destination */
-        movl %edi,%ecx
-        andl $7,%ecx
-        jnz  .Lbad_alignment
-.Lafter_bad_alignment:
-#endif
-
-        movq %rdx,%rcx
-
-        movl $64,%ebx
-        shrq $6,%rdx
-        decq %rdx
-        js   .Lhandle_tail
-
-        .p2align 4
-.Lloop:
-.Ls1:   movq (%rsi),%r11
-.Ls2:   movq 1*8(%rsi),%r8
-.Ls3:   movq 2*8(%rsi),%r9
-.Ls4:   movq 3*8(%rsi),%r10
-.Ld1:   movq %r11,(%rdi)
-.Ld2:   movq %r8,1*8(%rdi)
-.Ld3:   movq %r9,2*8(%rdi)
-.Ld4:   movq %r10,3*8(%rdi)
-
-.Ls5:   movq 4*8(%rsi),%r11
-.Ls6:   movq 5*8(%rsi),%r8
-.Ls7:   movq 6*8(%rsi),%r9
-.Ls8:   movq 7*8(%rsi),%r10
-.Ld5:   movq %r11,4*8(%rdi)
-.Ld6:   movq %r8,5*8(%rdi)
-.Ld7:   movq %r9,6*8(%rdi)
-.Ld8:   movq %r10,7*8(%rdi)
-
-        decq %rdx
-
+        cmpl $8,%edx
+        jb 20f          /* less then 8 bytes, go to byte copy loop */
+        ALIGN_DESTINATION
+        movl %edx,%ecx
+        andl $63,%edx
+        shrl $6,%ecx
+        jz 17f
+1:      movq (%rsi),%r8
+2:      movq 1*8(%rsi),%r9
+3:      movq 2*8(%rsi),%r10
+4:      movq 3*8(%rsi),%r11
+5:      movq %r8,(%rdi)
+6:      movq %r9,1*8(%rdi)
+7:      movq %r10,2*8(%rdi)
+8:      movq %r11,3*8(%rdi)
+9:      movq 4*8(%rsi),%r8
+10:     movq 5*8(%rsi),%r9
+11:     movq 6*8(%rsi),%r10
+12:     movq 7*8(%rsi),%r11
+13:     movq %r8,4*8(%rdi)
+14:     movq %r9,5*8(%rdi)
+15:     movq %r10,6*8(%rdi)
+16:     movq %r11,7*8(%rdi)
         leaq 64(%rsi),%rsi
         leaq 64(%rdi),%rdi
-
-        jns  .Lloop
-
-        .p2align 4
-.Lhandle_tail:
-        movl %ecx,%edx
-        andl $63,%ecx
-        shrl $3,%ecx
-        jz   .Lhandle_7
-        movl $8,%ebx
-        .p2align 4
-.Lloop_8:
-.Ls9:   movq (%rsi),%r8
-.Ld9:   movq %r8,(%rdi)
         decl %ecx
-        leaq 8(%rdi),%rdi
+        jnz 1b
+17:     movl %edx,%ecx
+        andl $7,%edx
+        shrl $3,%ecx
+        jz 20f
+18:     movq (%rsi),%r8
+19:     movq %r8,(%rdi)
         leaq 8(%rsi),%rsi
-        jnz .Lloop_8
-
-.Lhandle_7:
+        leaq 8(%rdi),%rdi
+        decl %ecx
+        jnz 18b
+20:     andl %edx,%edx
+        jz 23f
         movl %edx,%ecx
-        andl $7,%ecx
-        jz   .Lende
-        .p2align 4
-.Lloop_1:
-.Ls10:  movb (%rsi),%bl
-.Ld10:  movb %bl,(%rdi)
-        incq %rdi
+21:     movb (%rsi),%al
+22:     movb %al,(%rdi)
         incq %rsi
+        incq %rdi
         decl %ecx
-        jnz .Lloop_1
-
-        CFI_REMEMBER_STATE
-.Lende:
-        popq %rcx
-        CFI_ADJUST_CFA_OFFSET -8
-        CFI_RESTORE rcx
-        popq %rbx
-        CFI_ADJUST_CFA_OFFSET -8
-        CFI_RESTORE rbx
+        jnz 21b
+23:     xor %eax,%eax
         ret
-        CFI_RESTORE_STATE
 
-#ifdef FIX_ALIGNMENT
-        /* align destination */
-        .p2align 4
-.Lbad_alignment:
-        movl $8,%r9d
-        subl %ecx,%r9d
-        movl %r9d,%ecx
-        cmpq %r9,%rdx
-        jz   .Lhandle_7
-        js   .Lhandle_7
-.Lalign_1:
-.Ls11:  movb (%rsi),%bl
-.Ld11:  movb %bl,(%rdi)
-        incq %rsi
-        incq %rdi
-        decl %ecx
-        jnz .Lalign_1
-        subq %r9,%rdx
-        jmp .Lafter_bad_alignment
-#endif
+        .section .fixup,"ax"
+30:     shll $6,%ecx
+        addl %ecx,%edx
+        jmp 60f
+40:     lea (%rdx,%rcx,8),%rdx
+        jmp 60f
+50:     movl %ecx,%edx
+60:     jmp copy_user_handle_tail /* ecx is zerorest also */
+        .previous
 
-        /* table sorted by exception address */
         .section __ex_table,"a"
         .align 8
-        .quad .Ls1,.Ls1e        /* Ls1-Ls4 have copied zero bytes */
-        .quad .Ls2,.Ls1e
-        .quad .Ls3,.Ls1e
-        .quad .Ls4,.Ls1e
-        .quad .Ld1,.Ls1e        /* Ld1-Ld4 have copied 0-24 bytes */
-        .quad .Ld2,.Ls2e
-        .quad .Ld3,.Ls3e
-        .quad .Ld4,.Ls4e
-        .quad .Ls5,.Ls5e        /* Ls5-Ls8 have copied 32 bytes */
-        .quad .Ls6,.Ls5e
-        .quad .Ls7,.Ls5e
-        .quad .Ls8,.Ls5e
-        .quad .Ld5,.Ls5e        /* Ld5-Ld8 have copied 32-56 bytes */
-        .quad .Ld6,.Ls6e
-        .quad .Ld7,.Ls7e
-        .quad .Ld8,.Ls8e
-        .quad .Ls9,.Le_quad
-        .quad .Ld9,.Le_quad
-        .quad .Ls10,.Le_byte
-        .quad .Ld10,.Le_byte
-#ifdef FIX_ALIGNMENT
-        .quad .Ls11,.Lzero_rest
-        .quad .Ld11,.Lzero_rest
-#endif
-        .quad .Le5,.Le_zero
+        .quad 1b,30b
+        .quad 2b,30b
+        .quad 3b,30b
+        .quad 4b,30b
+        .quad 5b,30b
+        .quad 6b,30b
+        .quad 7b,30b
+        .quad 8b,30b
+        .quad 9b,30b
+        .quad 10b,30b
+        .quad 11b,30b
+        .quad 12b,30b
+        .quad 13b,30b
+        .quad 14b,30b
+        .quad 15b,30b
+        .quad 16b,30b
+        .quad 18b,40b
+        .quad 19b,40b
+        .quad 21b,50b
+        .quad 22b,50b
         .previous
-
-        /* eax: zero, ebx: 64 */
-.Ls1e:  addl $8,%eax            /* eax is bytes left uncopied within the loop (Ls1e: 64 .. Ls8e: 8) */
-.Ls2e:  addl $8,%eax
-.Ls3e:  addl $8,%eax
-.Ls4e:  addl $8,%eax
-.Ls5e:  addl $8,%eax
-.Ls6e:  addl $8,%eax
-.Ls7e:  addl $8,%eax
-.Ls8e:  addl $8,%eax
-        addq %rbx,%rdi  /* +64 */
-        subq %rax,%rdi  /* correct destination with computed offset */
-
-        shlq $6,%rdx    /* loop counter * 64 (stride length) */
-        addq %rax,%rdx  /* add offset to loopcnt */
-        andl $63,%ecx   /* remaining bytes */
-        addq %rcx,%rdx  /* add them */
-        jmp .Lzero_rest
-
-        /* exception on quad word loop in tail handling */
-        /* ecx: loopcnt/8, %edx: length, rdi: correct */
-.Le_quad:
-        shll $3,%ecx
-        andl $7,%edx
-        addl %ecx,%edx
-        /* edx: bytes to zero, rdi: dest, eax:zero */
-.Lzero_rest:
-        cmpl $0,(%rsp)
-        jz   .Le_zero
-        movq %rdx,%rcx
-.Le_byte:
-        xorl %eax,%eax
-.Le5:   rep
-        stosb
-        /* when there is another exception while zeroing the rest just return */
-.Le_zero:
-        movq %rdx,%rax
-        jmp .Lende
         CFI_ENDPROC
-ENDPROC(copy_user_generic)
+ENDPROC(copy_user_generic_unrolled)
 
-
-        /* Some CPUs run faster using the string copy instructions.
-           This is also a lot simpler. Use them when possible.
-           Patch in jmps to this code instead of copying it fully
-           to avoid unwanted aliasing in the exception tables. */
-
- /* rdi destination
-  * rsi source
-  * rdx count
-  * ecx zero flag
-  *
-  * Output:
-  * eax uncopied bytes or 0 if successfull.
-  *
-  * Only 4GB of copy is supported. This shouldn't be a problem
-  * because the kernel normally only writes from/to page sized chunks
-  * even if user space passed a longer buffer.
-  * And more would be dangerous because both Intel and AMD have
-  * errata with rep movsq > 4GB. If someone feels the need to fix
-  * this please consider this.
-  */
+/* Some CPUs run faster using the string copy instructions.
+ * This is also a lot simpler. Use them when possible.
+ *
+ * Only 4GB of copy is supported. This shouldn't be a problem
+ * because the kernel normally only writes from/to page sized chunks
+ * even if user space passed a longer buffer.
+ * And more would be dangerous because both Intel and AMD have
+ * errata with rep movsq > 4GB. If someone feels the need to fix
+ * this please consider this.
+ *
+ * Input:
+ * rdi destination
+ * rsi source
+ * rdx count
+ *
+ * Output:
+ * eax uncopied bytes or 0 if successful.
+ */
 ENTRY(copy_user_generic_string)
         CFI_STARTPROC
-        movl %ecx,%r8d          /* save zero flag */
+        andl %edx,%edx
+        jz 4f
+        cmpl $8,%edx
+        jb 2f           /* less than 8 bytes, go to byte copy loop */
+        ALIGN_DESTINATION
         movl %edx,%ecx
         shrl $3,%ecx
-        andl $7,%edx    
-        jz   10f
-1:      rep 
-        movsq 
-        movl %edx,%ecx
-2:      rep
-        movsb
-9:      movl %ecx,%eax
-        ret
-
-        /* multiple of 8 byte */
-10:     rep
+        andl $7,%edx
+1:      rep
         movsq
-        xor %eax,%eax
+2:      movl %edx,%ecx
+3:      rep
+        movsb
+4:      xorl %eax,%eax
         ret
 
-        /* exception handling */
-3:      lea (%rdx,%rcx,8),%rax  /* exception on quad loop */
-        jmp 6f
-5:      movl %ecx,%eax          /* exception on byte loop */
-        /* eax: left over bytes */
-6:      testl %r8d,%r8d         /* zero flag set? */
-        jz 7f
-        movl %eax,%ecx          /* initialize x86 loop counter */
-        push %rax
-        xorl %eax,%eax
-8:      rep
-        stosb                   /* zero the rest */
-11:     pop %rax
-7:      ret
-        CFI_ENDPROC
-END(copy_user_generic_c)
+        .section .fixup,"ax"
+11:     lea (%rdx,%rcx,8),%rcx
+12:     movl %ecx,%edx          /* ecx is zerorest also */
+        jmp copy_user_handle_tail
+        .previous
 
         .section __ex_table,"a"
-        .quad 1b,3b
-        .quad 2b,5b
-        .quad 8b,11b
-        .quad 10b,3b
+        .align 8
+        .quad 1b,11b
+        .quad 3b,12b
         .previous
+        CFI_ENDPROC
+ENDPROC(copy_user_generic_string)
diff --git a/arch/x86/lib/copy_user_nocache_64.S b/arch/x86/lib/copy_user_nocache_64.S
index 9d3d1ab83763..40e0e309d27e 100644
--- a/arch/x86/lib/copy_user_nocache_64.S
+++ b/arch/x86/lib/copy_user_nocache_64.S
@@ -1,4 +1,6 @@
-/* Copyright 2002 Andi Kleen, SuSE Labs.
+/*
+ * Copyright 2008 Vitaly Mayatskikh <vmayatsk@redhat.com>
+ * Copyright 2002 Andi Kleen, SuSE Labs.
  * Subject to the GNU Public License v2.
  *
  * Functions to copy from and to user space.
@@ -12,204 +14,125 @@
 #include <asm/current.h>
 #include <asm/asm-offsets.h>
 #include <asm/thread_info.h>
-#include <asm/cpufeature.h>
-
-/*
- * copy_user_nocache - Uncached memory copy with exception handling
- * This will force destination/source out of cache for more performance.
- *
- * Input:
- * rdi destination
- * rsi source
- * rdx count
- * rcx zero flag        when 1 zero on exception
- *
- * Output:
- * eax uncopied bytes or 0 if successful.
- */
-ENTRY(__copy_user_nocache)
-        CFI_STARTPROC
-        pushq %rbx
-        CFI_ADJUST_CFA_OFFSET 8
-        CFI_REL_OFFSET rbx, 0
-        pushq %rcx              /* save zero flag */
-        CFI_ADJUST_CFA_OFFSET 8
-        CFI_REL_OFFSET rcx, 0
-
-        xorl %eax,%eax          /* zero for the exception handler */
 
+        .macro ALIGN_DESTINATION
 #ifdef FIX_ALIGNMENT
         /* check for bad alignment of destination */
         movl %edi,%ecx
         andl $7,%ecx
-        jnz  .Lbad_alignment
-.Lafter_bad_alignment:
-#endif
-
-        movq %rdx,%rcx
-
-        movl $64,%ebx
-        shrq $6,%rdx
-        decq %rdx
-        js   .Lhandle_tail
-
-        .p2align 4
-.Lloop:
-.Ls1:   movq (%rsi),%r11
-.Ls2:   movq 1*8(%rsi),%r8
-.Ls3:   movq 2*8(%rsi),%r9
-.Ls4:   movq 3*8(%rsi),%r10
-.Ld1:   movnti %r11,(%rdi)
-.Ld2:   movnti %r8,1*8(%rdi)
-.Ld3:   movnti %r9,2*8(%rdi)
-.Ld4:   movnti %r10,3*8(%rdi)
-
-.Ls5:   movq 4*8(%rsi),%r11
-.Ls6:   movq 5*8(%rsi),%r8
-.Ls7:   movq 6*8(%rsi),%r9
-.Ls8:   movq 7*8(%rsi),%r10
-.Ld5:   movnti %r11,4*8(%rdi)
-.Ld6:   movnti %r8,5*8(%rdi)
-.Ld7:   movnti %r9,6*8(%rdi)
-.Ld8:   movnti %r10,7*8(%rdi)
+        jz 102f                         /* already aligned */
+        subl $8,%ecx
+        negl %ecx
+        subl %ecx,%edx
+100:    movb (%rsi),%al
+101:    movb %al,(%rdi)
+        incq %rsi
+        incq %rdi
+        decl %ecx
+        jnz 100b
+102:
+        .section .fixup,"ax"
+103:    addl %r8d,%edx                  /* ecx is zerorest also */
+        jmp copy_user_handle_tail
+        .previous
 
-        dec  %rdx
+        .section __ex_table,"a"
+        .align 8
+        .quad 100b,103b
+        .quad 101b,103b
+        .previous
+#endif
+        .endm
 
+/*
+ * copy_user_nocache - Uncached memory copy with exception handling
+ * This will force destination/source out of cache for more performance.
+ */
+ENTRY(__copy_user_nocache)
+        CFI_STARTPROC
+        cmpl $8,%edx
+        jb 20f          /* less then 8 bytes, go to byte copy loop */
+        ALIGN_DESTINATION
+        movl %edx,%ecx
+        andl $63,%edx
+        shrl $6,%ecx
+        jz 17f
+1:      movq (%rsi),%r8
+2:      movq 1*8(%rsi),%r9
+3:      movq 2*8(%rsi),%r10
+4:      movq 3*8(%rsi),%r11
+5:      movnti %r8,(%rdi)
+6:      movnti %r9,1*8(%rdi)
+7:      movnti %r10,2*8(%rdi)
+8:      movnti %r11,3*8(%rdi)
+9:      movq 4*8(%rsi),%r8
+10:     movq 5*8(%rsi),%r9
+11:     movq 6*8(%rsi),%r10
+12:     movq 7*8(%rsi),%r11
+13:     movnti %r8,4*8(%rdi)
+14:     movnti %r9,5*8(%rdi)
+15:     movnti %r10,6*8(%rdi)
+16:     movnti %r11,7*8(%rdi)
         leaq 64(%rsi),%rsi
         leaq 64(%rdi),%rdi
-
-        jns  .Lloop
-
-        .p2align 4
-.Lhandle_tail:
-        movl %ecx,%edx
-        andl $63,%ecx
-        shrl $3,%ecx
-        jz   .Lhandle_7
-        movl $8,%ebx
-        .p2align 4
-.Lloop_8:
-.Ls9:   movq (%rsi),%r8
-.Ld9:   movnti %r8,(%rdi)
         decl %ecx
-        leaq 8(%rdi),%rdi
+        jnz 1b
+17:     movl %edx,%ecx
+        andl $7,%edx
+        shrl $3,%ecx
+        jz 20f
+18:     movq (%rsi),%r8
+19:     movnti %r8,(%rdi)
         leaq 8(%rsi),%rsi
-        jnz .Lloop_8
-
-.Lhandle_7:
+        leaq 8(%rdi),%rdi
+        decl %ecx
+        jnz 18b
+20:     andl %edx,%edx
+        jz 23f
         movl %edx,%ecx
-        andl $7,%ecx
-        jz   .Lende
-        .p2align 4
-.Lloop_1:
-.Ls10:  movb (%rsi),%bl
-.Ld10:  movb %bl,(%rdi)
-        incq %rdi
+21:     movb (%rsi),%al
+22:     movb %al,(%rdi)
         incq %rsi
+        incq %rdi
         decl %ecx
-        jnz .Lloop_1
-
-        CFI_REMEMBER_STATE
-.Lende:
-        popq %rcx
-        CFI_ADJUST_CFA_OFFSET -8
-        CFI_RESTORE %rcx
-        popq %rbx
-        CFI_ADJUST_CFA_OFFSET -8
-        CFI_RESTORE rbx
+        jnz 21b
+23:     xorl %eax,%eax
         sfence
         ret
-        CFI_RESTORE_STATE
 
-#ifdef FIX_ALIGNMENT
-        /* align destination */
-        .p2align 4
-.Lbad_alignment:
-        movl $8,%r9d
-        subl %ecx,%r9d
-        movl %r9d,%ecx
-        cmpq %r9,%rdx
-        jz   .Lhandle_7
-        js   .Lhandle_7
-.Lalign_1:
-.Ls11:  movb (%rsi),%bl
-.Ld11:  movb %bl,(%rdi)
-        incq %rsi
-        incq %rdi
-        decl %ecx
-        jnz .Lalign_1
-        subq %r9,%rdx
-        jmp .Lafter_bad_alignment
-#endif
+        .section .fixup,"ax"
+30:     shll $6,%ecx
+        addl %ecx,%edx
+        jmp 60f
+40:     lea (%rdx,%rcx,8),%rdx
+        jmp 60f
+50:     movl %ecx,%edx
+60:     sfence
+        movl %r8d,%ecx
+        jmp copy_user_handle_tail
+        .previous
 
-        /* table sorted by exception address */
         .section __ex_table,"a"
-        .align 8
-        .quad .Ls1,.Ls1e        /* .Ls[1-4] - 0 bytes copied */
-        .quad .Ls2,.Ls1e
-        .quad .Ls3,.Ls1e
-        .quad .Ls4,.Ls1e
-        .quad .Ld1,.Ls1e        /* .Ld[1-4] - 0..24 bytes coped */
-        .quad .Ld2,.Ls2e
-        .quad .Ld3,.Ls3e
-        .quad .Ld4,.Ls4e
-        .quad .Ls5,.Ls5e        /* .Ls[5-8] - 32 bytes copied */
-        .quad .Ls6,.Ls5e
-        .quad .Ls7,.Ls5e
-        .quad .Ls8,.Ls5e
-        .quad .Ld5,.Ls5e        /* .Ld[5-8] - 32..56 bytes copied */
-        .quad .Ld6,.Ls6e
-        .quad .Ld7,.Ls7e
-        .quad .Ld8,.Ls8e
-        .quad .Ls9,.Le_quad
-        .quad .Ld9,.Le_quad
-        .quad .Ls10,.Le_byte
-        .quad .Ld10,.Le_byte
-#ifdef FIX_ALIGNMENT
-        .quad .Ls11,.Lzero_rest
-        .quad .Ld11,.Lzero_rest
-#endif
-        .quad .Le5,.Le_zero
+        .quad 1b,30b
+        .quad 2b,30b
+        .quad 3b,30b
+        .quad 4b,30b
+        .quad 5b,30b
+        .quad 6b,30b
+        .quad 7b,30b
+        .quad 8b,30b
+        .quad 9b,30b
+        .quad 10b,30b
+        .quad 11b,30b
+        .quad 12b,30b
+        .quad 13b,30b
+        .quad 14b,30b
+        .quad 15b,30b
+        .quad 16b,30b
+        .quad 18b,40b
+        .quad 19b,40b
+        .quad 21b,50b
+        .quad 22b,50b
         .previous
-
-        /* eax: zero, ebx: 64 */
-.Ls1e:  addl $8,%eax    /* eax: bytes left uncopied: Ls1e: 64 .. Ls8e: 8 */
-.Ls2e:  addl $8,%eax
-.Ls3e:  addl $8,%eax
-.Ls4e:  addl $8,%eax
-.Ls5e:  addl $8,%eax
-.Ls6e:  addl $8,%eax
-.Ls7e:  addl $8,%eax
-.Ls8e:  addl $8,%eax
-        addq %rbx,%rdi  /* +64 */
-        subq %rax,%rdi  /* correct destination with computed offset */
-
-        shlq $6,%rdx    /* loop counter * 64 (stride length) */
-        addq %rax,%rdx  /* add offset to loopcnt */
-        andl $63,%ecx   /* remaining bytes */
-        addq %rcx,%rdx  /* add them */
-        jmp .Lzero_rest
-
-        /* exception on quad word loop in tail handling */
-        /* ecx: loopcnt/8, %edx: length, rdi: correct */
-.Le_quad:
-        shll $3,%ecx
-        andl $7,%edx
-        addl %ecx,%edx
-        /* edx: bytes to zero, rdi: dest, eax:zero */
-.Lzero_rest:
-        cmpl $0,(%rsp)  /* zero flag set? */
-        jz   .Le_zero
-        movq %rdx,%rcx
-.Le_byte:
-        xorl %eax,%eax
-.Le5:   rep
-        stosb
-        /* when there is another exception while zeroing the rest just return */
-.Le_zero:
-        movq %rdx,%rax
-        jmp .Lende
         CFI_ENDPROC
 ENDPROC(__copy_user_nocache)
-
-
diff --git a/arch/x86/lib/delay_32.c b/arch/x86/lib/delay.c
index d710f2d167bb..f4568605d7d5 100644
--- a/arch/x86/lib/delay_32.c
+++ b/arch/x86/lib/delay.c
@@ -3,6 +3,7 @@
  *
  *      Copyright (C) 1993 Linus Torvalds
  *      Copyright (C) 1997 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
+ *      Copyright (C) 2008 Jiri Hladky <hladky _dot_ jiri _at_ gmail _dot_ com>
  *
  *      The __delay function must _NOT_ be inlined as its execution time
  *      depends wildly on alignment on many x86 processors. The additional
@@ -28,16 +29,22 @@
 /* simple loop based delay: */
 static void delay_loop(unsigned long loops)
 {
-        int d0;
-
-        __asm__ __volatile__(
-                "\tjmp 1f\n"
-                ".align 16\n"
-                "1:\tjmp 2f\n"
-                ".align 16\n"
-                "2:\tdecl %0\n\tjns 2b"
-                :"=&a" (d0)
-                :"0" (loops));
+        asm volatile(
+                "       test %0,%0      \n"
+                "       jz 3f           \n"
+                "       jmp 1f          \n"
+
+                ".align 16              \n"
+                "1:     jmp 2f          \n"
+
+                ".align 16              \n"
+                "2:     dec %0          \n"
+                "       jnz 2b          \n"
+                "3:     dec %0          \n"
+
+                : /* we don't need output */
+                :"a" (loops)
+        );
 }
 
 /* TSC based delay: */
@@ -91,7 +98,7 @@ void use_tsc_delay(void)
 int __devinit read_current_timer(unsigned long *timer_val)
 {
         if (delay_fn == delay_tsc) {
-                rdtscl(*timer_val);
+                rdtscll(*timer_val);
                 return 0;
         }
         return -1;
@@ -101,31 +108,30 @@ void __delay(unsigned long loops)
 {
         delay_fn(loops);
 }
+EXPORT_SYMBOL(__delay);
 
 inline void __const_udelay(unsigned long xloops)
 {
         int d0;
 
         xloops *= 4;
-        __asm__("mull %0"
+        asm("mull %%edx"
                 :"=d" (xloops), "=&a" (d0)
                 :"1" (xloops), "0"
                 (cpu_data(raw_smp_processor_id()).loops_per_jiffy * (HZ/4)));
 
         __delay(++xloops);
 }
+EXPORT_SYMBOL(__const_udelay);
 
 void __udelay(unsigned long usecs)
 {
         __const_udelay(usecs * 0x000010c7); /* 2**32 / 1000000 (rounded up) */
 }
+EXPORT_SYMBOL(__udelay);
 
 void __ndelay(unsigned long nsecs)
 {
         __const_udelay(nsecs * 0x00005); /* 2**32 / 1000000000 (rounded up) */
 }
-
-EXPORT_SYMBOL(__delay);
-EXPORT_SYMBOL(__const_udelay);
-EXPORT_SYMBOL(__udelay);
 EXPORT_SYMBOL(__ndelay);
diff --git a/arch/x86/lib/delay_64.c b/arch/x86/lib/delay_64.c
deleted file mode 100644
index 4c441be92641..000000000000
--- a/arch/x86/lib/delay_64.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- *      Precise Delay Loops for x86-64
- *
- *      Copyright (C) 1993 Linus Torvalds
- *      Copyright (C) 1997 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
- *
- *      The __delay function must _NOT_ be inlined as its execution time
- *      depends wildly on alignment on many x86 processors. 
- */
-
-#include <linux/module.h>
-#include <linux/sched.h>
-#include <linux/timex.h>
-#include <linux/preempt.h>
-#include <linux/delay.h>
-#include <linux/init.h>
-
-#include <asm/delay.h>
-#include <asm/msr.h>
-
-#ifdef CONFIG_SMP
-#include <asm/smp.h>
-#endif
-
-int __devinit read_current_timer(unsigned long *timer_value)
-{
-        rdtscll(*timer_value);
-        return 0;
-}
-
-void __delay(unsigned long loops)
-{
-        unsigned bclock, now;
-        int cpu;
-
-        preempt_disable();
-        cpu = smp_processor_id();
-        rdtscl(bclock);
-        for (;;) {
-                rdtscl(now);
-                if ((now - bclock) >= loops)
-                        break;
-
-                /* Allow RT tasks to run */
-                preempt_enable();
-                rep_nop();
-                preempt_disable();
-
-                /*
-                 * It is possible that we moved to another CPU, and
-                 * since TSC's are per-cpu we need to calculate
-                 * that. The delay must guarantee that we wait "at
-                 * least" the amount of time. Being moved to another
-                 * CPU could make the wait longer but we just need to
-                 * make sure we waited long enough. Rebalance the
-                 * counter for this CPU.
-                 */
-                if (unlikely(cpu != smp_processor_id())) {
-                        loops -= (now - bclock);
-                        cpu = smp_processor_id();
-                        rdtscl(bclock);
-                }
-        }
-        preempt_enable();
-}
-EXPORT_SYMBOL(__delay);
-
-inline void __const_udelay(unsigned long xloops)
-{
-        __delay(((xloops * HZ *
-                cpu_data(raw_smp_processor_id()).loops_per_jiffy) >> 32) + 1);
-}
-EXPORT_SYMBOL(__const_udelay);
-
-void __udelay(unsigned long usecs)
-{
-        __const_udelay(usecs * 0x000010c7);  /* 2**32 / 1000000 (rounded up) */
-}
-EXPORT_SYMBOL(__udelay);
-
-void __ndelay(unsigned long nsecs)
-{
-        __const_udelay(nsecs * 0x00005);  /* 2**32 / 1000000000 (rounded up) */
-}
-EXPORT_SYMBOL(__ndelay);
diff --git a/arch/x86/lib/getuser_64.S b/arch/x86/lib/getuser.S
index 5448876261f8..ad374003742f 100644
--- a/arch/x86/lib/getuser_64.S
+++ b/arch/x86/lib/getuser.S
@@ -3,6 +3,7 @@
  *
  * (C) Copyright 1998 Linus Torvalds
  * (C) Copyright 2005 Andi Kleen
+ * (C) Copyright 2008 Glauber Costa
  *
  * These functions have a non-standard call interface
  * to make them more efficient, especially as they
@@ -13,14 +14,13 @@
 /*
  * __get_user_X
  *
- * Inputs:      %rcx contains the address.
+ * Inputs:      %[r|e]ax contains the address.
  *              The register is modified, but all changes are undone
  *              before returning because the C code doesn't know about it.
  *
- * Outputs:     %rax is error code (0 or -EFAULT)
- *              %rdx contains zero-extended value
- * 
- * %r8 is destroyed.
+ * Outputs:     %[r|e]ax is error code (0 or -EFAULT)
+ *              %[r|e]dx contains zero-extended value
+ *
  *
  * These functions should not modify any other registers,
  * as they get called from within inline assembly.
@@ -32,78 +32,73 @@
 #include <asm/errno.h>
 #include <asm/asm-offsets.h>
 #include <asm/thread_info.h>
+#include <asm/asm.h>
 
         .text
 ENTRY(__get_user_1)
         CFI_STARTPROC
-        GET_THREAD_INFO(%r8)
-        cmpq threadinfo_addr_limit(%r8),%rcx
+        GET_THREAD_INFO(%_ASM_DX)
+        cmp TI_addr_limit(%_ASM_DX),%_ASM_AX
         jae bad_get_user
-1:      movzb (%rcx),%edx
-        xorl %eax,%eax
+1:      movzb (%_ASM_AX),%edx
+        xor %eax,%eax
         ret
         CFI_ENDPROC
 ENDPROC(__get_user_1)
 
 ENTRY(__get_user_2)
         CFI_STARTPROC
-        GET_THREAD_INFO(%r8)
-        addq $1,%rcx
-        jc 20f
-        cmpq threadinfo_addr_limit(%r8),%rcx
-        jae 20f
-        decq   %rcx
-2:      movzwl (%rcx),%edx
-        xorl %eax,%eax
+        add $1,%_ASM_AX
+        jc bad_get_user
+        GET_THREAD_INFO(%_ASM_DX)
+        cmp TI_addr_limit(%_ASM_DX),%_ASM_AX
+        jae bad_get_user
+2:      movzwl -1(%_ASM_AX),%edx
+        xor %eax,%eax
         ret
-20:     decq    %rcx
-        jmp     bad_get_user
         CFI_ENDPROC
 ENDPROC(__get_user_2)
 
 ENTRY(__get_user_4)
         CFI_STARTPROC
-        GET_THREAD_INFO(%r8)
-        addq $3,%rcx
-        jc 30f
-        cmpq threadinfo_addr_limit(%r8),%rcx
-        jae 30f
-        subq $3,%rcx
-3:      movl (%rcx),%edx
-        xorl %eax,%eax
+        add $3,%_ASM_AX
+        jc bad_get_user
+        GET_THREAD_INFO(%_ASM_DX)
+        cmp TI_addr_limit(%_ASM_DX),%_ASM_AX
+        jae bad_get_user
+3:      mov -3(%_ASM_AX),%edx
+        xor %eax,%eax
         ret
-30:     subq $3,%rcx
-        jmp bad_get_user
         CFI_ENDPROC
 ENDPROC(__get_user_4)
 
+#ifdef CONFIG_X86_64
 ENTRY(__get_user_8)
         CFI_STARTPROC
-        GET_THREAD_INFO(%r8)
-        addq $7,%rcx
-        jc 40f
-        cmpq threadinfo_addr_limit(%r8),%rcx
-        jae     40f
-        subq    $7,%rcx
-4:      movq (%rcx),%rdx
-        xorl %eax,%eax
+        add $7,%_ASM_AX
+        jc bad_get_user
+        GET_THREAD_INFO(%_ASM_DX)
+        cmp TI_addr_limit(%_ASM_DX),%_ASM_AX
+        jae     bad_get_user
+4:      movq -7(%_ASM_AX),%_ASM_DX
+        xor %eax,%eax
         ret
-40:     subq $7,%rcx
-        jmp bad_get_user
         CFI_ENDPROC
 ENDPROC(__get_user_8)
+#endif
 
 bad_get_user:
         CFI_STARTPROC
-        xorl %edx,%edx
-        movq $(-EFAULT),%rax
+        xor %edx,%edx
+        mov $(-EFAULT),%_ASM_AX
         ret
         CFI_ENDPROC
 END(bad_get_user)
 
 .section __ex_table,"a"
-        .quad 1b,bad_get_user
-        .quad 2b,bad_get_user
-        .quad 3b,bad_get_user
-        .quad 4b,bad_get_user
-.previous
+        _ASM_PTR 1b,bad_get_user
+        _ASM_PTR 2b,bad_get_user
+        _ASM_PTR 3b,bad_get_user
+#ifdef CONFIG_X86_64
+        _ASM_PTR 4b,bad_get_user
+#endif
diff --git a/arch/x86/lib/getuser_32.S b/arch/x86/lib/getuser_32.S
deleted file mode 100644
index 6d84b53f12a2..000000000000
--- a/arch/x86/lib/getuser_32.S
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * __get_user functions.
- *
- * (C) Copyright 1998 Linus Torvalds
- *
- * These functions have a non-standard call interface
- * to make them more efficient, especially as they
- * return an error value in addition to the "real"
- * return value.
- */
-#include <linux/linkage.h>
-#include <asm/dwarf2.h>
-#include <asm/thread_info.h>
-
-
-/*
- * __get_user_X
- *
- * Inputs:      %eax contains the address
- *
- * Outputs:     %eax is error code (0 or -EFAULT)
- *              %edx contains zero-extended value
- *
- * These functions should not modify any other registers,
- * as they get called from within inline assembly.
- */
-
-.text
-ENTRY(__get_user_1)
-        CFI_STARTPROC
-        GET_THREAD_INFO(%edx)
-        cmpl TI_addr_limit(%edx),%eax
-        jae bad_get_user
-1:      movzbl (%eax),%edx
-        xorl %eax,%eax
-        ret
-        CFI_ENDPROC
-ENDPROC(__get_user_1)
-
-ENTRY(__get_user_2)
-        CFI_STARTPROC
-        addl $1,%eax
-        jc bad_get_user
-        GET_THREAD_INFO(%edx)
-        cmpl TI_addr_limit(%edx),%eax
-        jae bad_get_user
-2:      movzwl -1(%eax),%edx
-        xorl %eax,%eax
-        ret
-        CFI_ENDPROC
-ENDPROC(__get_user_2)
-
-ENTRY(__get_user_4)
-        CFI_STARTPROC
-        addl $3,%eax
-        jc bad_get_user
-        GET_THREAD_INFO(%edx)
-        cmpl TI_addr_limit(%edx),%eax
-        jae bad_get_user
-3:      movl -3(%eax),%edx
-        xorl %eax,%eax
-        ret
-        CFI_ENDPROC
-ENDPROC(__get_user_4)
-
-bad_get_user:
-        CFI_STARTPROC
-        xorl %edx,%edx
-        movl $-14,%eax
-        ret
-        CFI_ENDPROC
-END(bad_get_user)
-
-.section __ex_table,"a"
-        .long 1b,bad_get_user
-        .long 2b,bad_get_user
-        .long 3b,bad_get_user
-.previous
diff --git a/arch/x86/lib/putuser_32.S b/arch/x86/lib/putuser.S
index f58fba109d18..36b0d15ae6e9 100644
--- a/arch/x86/lib/putuser_32.S
+++ b/arch/x86/lib/putuser.S
@@ -2,6 +2,8 @@
  * __put_user functions.
  *
  * (C) Copyright 2005 Linus Torvalds
+ * (C) Copyright 2005 Andi Kleen
+ * (C) Copyright 2008 Glauber Costa
  *
  * These functions have a non-standard call interface
  * to make them more efficient, especially as they
@@ -11,6 +13,8 @@
 #include <linux/linkage.h>
 #include <asm/dwarf2.h>
 #include <asm/thread_info.h>
+#include <asm/errno.h>
+#include <asm/asm.h>
 
 
 /*
@@ -26,73 +30,68 @@
  */
 
 #define ENTER   CFI_STARTPROC ; \
-                pushl %ebx ; \
-                CFI_ADJUST_CFA_OFFSET 4 ; \
-                CFI_REL_OFFSET ebx, 0 ; \
-                GET_THREAD_INFO(%ebx)
-#define EXIT    popl %ebx ; \
-                CFI_ADJUST_CFA_OFFSET -4 ; \
-                CFI_RESTORE ebx ; \
-                ret ; \
+                GET_THREAD_INFO(%_ASM_BX)
+#define EXIT    ret ; \
                 CFI_ENDPROC
 
 .text
 ENTRY(__put_user_1)
         ENTER
-        cmpl TI_addr_limit(%ebx),%ecx
+        cmp TI_addr_limit(%_ASM_BX),%_ASM_CX
         jae bad_put_user
-1:      movb %al,(%ecx)
-        xorl %eax,%eax
+1:      movb %al,(%_ASM_CX)
+        xor %eax,%eax
         EXIT
 ENDPROC(__put_user_1)
 
 ENTRY(__put_user_2)
         ENTER
-        movl TI_addr_limit(%ebx),%ebx
-        subl $1,%ebx
-        cmpl %ebx,%ecx
+        mov TI_addr_limit(%_ASM_BX),%_ASM_BX
+        sub $1,%_ASM_BX
+        cmp %_ASM_BX,%_ASM_CX
         jae bad_put_user
-2:      movw %ax,(%ecx)
-        xorl %eax,%eax
+2:      movw %ax,(%_ASM_CX)
+        xor %eax,%eax
         EXIT
 ENDPROC(__put_user_2)
 
 ENTRY(__put_user_4)
         ENTER
-        movl TI_addr_limit(%ebx),%ebx
-        subl $3,%ebx
-        cmpl %ebx,%ecx
+        mov TI_addr_limit(%_ASM_BX),%_ASM_BX
+        sub $3,%_ASM_BX
+        cmp %_ASM_BX,%_ASM_CX
         jae bad_put_user
-3:      movl %eax,(%ecx)
-        xorl %eax,%eax
+3:      movl %eax,(%_ASM_CX)
+        xor %eax,%eax
         EXIT
 ENDPROC(__put_user_4)
 
 ENTRY(__put_user_8)
         ENTER
-        movl TI_addr_limit(%ebx),%ebx
-        subl $7,%ebx
-        cmpl %ebx,%ecx
+        mov TI_addr_limit(%_ASM_BX),%_ASM_BX
+        sub $7,%_ASM_BX
+        cmp %_ASM_BX,%_ASM_CX
         jae bad_put_user
-4:      movl %eax,(%ecx)
-5:      movl %edx,4(%ecx)
-        xorl %eax,%eax
+4:      mov %_ASM_AX,(%_ASM_CX)
+#ifdef CONFIG_X86_32
+5:      movl %edx,4(%_ASM_CX)
+#endif
+        xor %eax,%eax
         EXIT
 ENDPROC(__put_user_8)
 
 bad_put_user:
-        CFI_STARTPROC simple
-        CFI_DEF_CFA esp, 2*4
-        CFI_OFFSET eip, -1*4
-        CFI_OFFSET ebx, -2*4
-        movl $-14,%eax
+        CFI_STARTPROC
+        movl $-EFAULT,%eax
         EXIT
 END(bad_put_user)
 
 .section __ex_table,"a"
-        .long 1b,bad_put_user
-        .long 2b,bad_put_user
-        .long 3b,bad_put_user
-        .long 4b,bad_put_user
-        .long 5b,bad_put_user
+        _ASM_PTR 1b,bad_put_user
+        _ASM_PTR 2b,bad_put_user
+        _ASM_PTR 3b,bad_put_user
+        _ASM_PTR 4b,bad_put_user
+#ifdef CONFIG_X86_32
+        _ASM_PTR 5b,bad_put_user
+#endif
 .previous
diff --git a/arch/x86/lib/putuser_64.S b/arch/x86/lib/putuser_64.S
deleted file mode 100644
index 4989f5a8fa9b..000000000000
--- a/arch/x86/lib/putuser_64.S
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * __put_user functions.
- *
- * (C) Copyright 1998 Linus Torvalds
- * (C) Copyright 2005 Andi Kleen
- *
- * These functions have a non-standard call interface
- * to make them more efficient, especially as they
- * return an error value in addition to the "real"
- * return value.
- */
-
-/*
- * __put_user_X
- *
- * Inputs:      %rcx contains the address
- *              %rdx contains new value
- *
- * Outputs:     %rax is error code (0 or -EFAULT)
- *
- * %r8 is destroyed.
- *
- * These functions should not modify any other registers,
- * as they get called from within inline assembly.
- */
-
-#include <linux/linkage.h>
-#include <asm/dwarf2.h>
-#include <asm/page.h>
-#include <asm/errno.h>
-#include <asm/asm-offsets.h>
-#include <asm/thread_info.h>
-
-        .text
-ENTRY(__put_user_1)
-        CFI_STARTPROC
-        GET_THREAD_INFO(%r8)
-        cmpq threadinfo_addr_limit(%r8),%rcx
-        jae bad_put_user
-1:      movb %dl,(%rcx)
-        xorl %eax,%eax
-        ret
-        CFI_ENDPROC
-ENDPROC(__put_user_1)
-
-ENTRY(__put_user_2)
-        CFI_STARTPROC
-        GET_THREAD_INFO(%r8)
-        addq $1,%rcx
-        jc 20f
-        cmpq threadinfo_addr_limit(%r8),%rcx
-        jae 20f
-        decq %rcx
-2:      movw %dx,(%rcx)
-        xorl %eax,%eax
-        ret
-20:     decq %rcx
-        jmp bad_put_user
-        CFI_ENDPROC
-ENDPROC(__put_user_2)
-
-ENTRY(__put_user_4)
-        CFI_STARTPROC
-        GET_THREAD_INFO(%r8)
-        addq $3,%rcx
-        jc 30f
-        cmpq threadinfo_addr_limit(%r8),%rcx
-        jae 30f
-        subq $3,%rcx
-3:      movl %edx,(%rcx)
-        xorl %eax,%eax
-        ret
-30:     subq $3,%rcx
-        jmp bad_put_user
-        CFI_ENDPROC
-ENDPROC(__put_user_4)
-
-ENTRY(__put_user_8)
-        CFI_STARTPROC
-        GET_THREAD_INFO(%r8)
-        addq $7,%rcx
-        jc 40f
-        cmpq threadinfo_addr_limit(%r8),%rcx
-        jae 40f
-        subq $7,%rcx
-4:      movq %rdx,(%rcx)
-        xorl %eax,%eax
-        ret
-40:     subq $7,%rcx
-        jmp bad_put_user
-        CFI_ENDPROC
-ENDPROC(__put_user_8)
-
-bad_put_user:
-        CFI_STARTPROC
-        movq $(-EFAULT),%rax
-        ret
-        CFI_ENDPROC
-END(bad_put_user)
-
-.section __ex_table,"a"
-        .quad 1b,bad_put_user
-        .quad 2b,bad_put_user
-        .quad 3b,bad_put_user
-        .quad 4b,bad_put_user
-.previous
diff --git a/arch/x86/lib/thunk_32.S b/arch/x86/lib/thunk_32.S
new file mode 100644
index 000000000000..650b11e00ecc
--- /dev/null
+++ b/arch/x86/lib/thunk_32.S
@@ -0,0 +1,47 @@
+/*
+ * Trampoline to trace irqs off. (otherwise CALLER_ADDR1 might crash)
+ * Copyright 2008 by Steven Rostedt, Red Hat, Inc
+ *  (inspired by Andi Kleen's thunk_64.S)
+ * Subject to the GNU public license, v.2. No warranty of any kind.
+ */
+
+        #include <linux/linkage.h>
+
+#define ARCH_TRACE_IRQS_ON                      \
+        pushl %eax;                             \
+        pushl %ecx;                             \
+        pushl %edx;                             \
+        call trace_hardirqs_on;                 \
+        popl %edx;                              \
+        popl %ecx;                              \
+        popl %eax;
+
+#define ARCH_TRACE_IRQS_OFF                     \
+        pushl %eax;                             \
+        pushl %ecx;                             \
+        pushl %edx;                             \
+        call trace_hardirqs_off;                \
+        popl %edx;                              \
+        popl %ecx;                              \
+        popl %eax;
+
+#ifdef CONFIG_TRACE_IRQFLAGS
+        /* put return address in eax (arg1) */
+        .macro thunk_ra name,func
+        .globl \name
+\name:
+        pushl %eax
+        pushl %ecx
+        pushl %edx
+        /* Place EIP in the arg1 */
+        movl 3*4(%esp), %eax
+        call \func
+        popl %edx
+        popl %ecx
+        popl %eax
+        ret
+        .endm
+
+        thunk_ra trace_hardirqs_on_thunk,trace_hardirqs_on_caller
+        thunk_ra trace_hardirqs_off_thunk,trace_hardirqs_off_caller
+#endif
diff --git a/arch/x86/lib/thunk_64.S b/arch/x86/lib/thunk_64.S
index e009251d4e9f..bf9a7d5a5428 100644
--- a/arch/x86/lib/thunk_64.S
+++ b/arch/x86/lib/thunk_64.S
@@ -2,6 +2,7 @@
  * Save registers before calling assembly functions. This avoids
  * disturbance of register allocation in some inline assembly constructs.
  * Copyright 2001,2002 by Andi Kleen, SuSE Labs.
+ * Added trace_hardirqs callers - Copyright 2007 Steven Rostedt, Red Hat, Inc.
  * Subject to the GNU public license, v.2. No warranty of any kind.
  */
 
@@ -42,8 +43,22 @@
 #endif  
         
 #ifdef CONFIG_TRACE_IRQFLAGS
-        thunk trace_hardirqs_on_thunk,trace_hardirqs_on
-        thunk trace_hardirqs_off_thunk,trace_hardirqs_off
+        /* put return address in rdi (arg1) */
+        .macro thunk_ra name,func
+        .globl \name
+\name:
+        CFI_STARTPROC
+        SAVE_ARGS
+        /* SAVE_ARGS pushs 9 elements */
+        /* the next element would be the rip */
+        movq 9*8(%rsp), %rdi
+        call \func
+        jmp  restore
+        CFI_ENDPROC
+        .endm
+
+        thunk_ra trace_hardirqs_on_thunk,trace_hardirqs_on_caller
+        thunk_ra trace_hardirqs_off_thunk,trace_hardirqs_off_caller
 #endif
 
 #ifdef CONFIG_DEBUG_LOCK_ALLOC
diff --git a/arch/x86/lib/usercopy_64.c b/arch/x86/lib/usercopy_64.c
index 0c89d1bb0287..f4df6e7c718b 100644
--- a/arch/x86/lib/usercopy_64.c
+++ b/arch/x86/lib/usercopy_64.c
@@ -158,3 +158,26 @@ unsigned long copy_in_user(void __user *to, const void __user *from, unsigned le
 }
 EXPORT_SYMBOL(copy_in_user);
 
+/*
+ * Try to copy last bytes and clear the rest if needed.
+ * Since protection fault in copy_from/to_user is not a normal situation,
+ * it is not necessary to optimize tail handling.
+ */
+unsigned long
+copy_user_handle_tail(char *to, char *from, unsigned len, unsigned zerorest)
+{
+        char c;
+        unsigned zero_len;
+
+        for (; len; --len) {
+                if (__get_user_nocheck(c, from++, sizeof(char)))
+                        break;
+                if (__put_user_nocheck(c, to++, sizeof(char)))
+                        break;
+        }
+
+        for (c = 0, zero_len = len; zerorest && zero_len; --zero_len)
+                if (__put_user_nocheck(c, to++, sizeof(char)))
+                        break;
+        return len;
+}
diff --git a/arch/x86/mach-default/setup.c b/arch/x86/mach-default/setup.c
index 0c28a071824c..48278fa7d3de 100644
--- a/arch/x86/mach-default/setup.c
+++ b/arch/x86/mach-default/setup.c
@@ -10,6 +10,14 @@
 #include <asm/e820.h>
 #include <asm/setup.h>
 
+/*
+ * Any quirks to be performed to initialize timers/irqs/etc?
+ */
+int (*arch_time_init_quirk)(void);
+int (*arch_pre_intr_init_quirk)(void);
+int (*arch_intr_init_quirk)(void);
+int (*arch_trap_init_quirk)(void);
+
 #ifdef CONFIG_HOTPLUG_CPU
 #define DEFAULT_SEND_IPI        (1)
 #else
@@ -29,6 +37,10 @@ int no_broadcast=DEFAULT_SEND_IPI;
  **/
 void __init pre_intr_init_hook(void)
 {
+        if (arch_pre_intr_init_quirk) {
+                if (arch_pre_intr_init_quirk())
+                        return;
+        }
         init_ISA_irqs();
 }
 
@@ -52,6 +64,10 @@ static struct irqaction irq2 = {
  **/
 void __init intr_init_hook(void)
 {
+        if (arch_intr_init_quirk) {
+                if (arch_intr_init_quirk())
+                        return;
+        }
 #ifdef CONFIG_X86_LOCAL_APIC
         apic_intr_init();
 #endif
@@ -65,7 +81,7 @@ void __init intr_init_hook(void)
  *
  * Description:
  *      generally used to activate any machine specific identification
- *      routines that may be needed before setup_arch() runs.  On VISWS
+ *      routines that may be needed before setup_arch() runs.  On Voyager
  *      this is used to get the board revision and type.
  **/
 void __init pre_setup_arch_hook(void)
@@ -81,6 +97,10 @@ void __init pre_setup_arch_hook(void)
  **/
 void __init trap_init_hook(void)
 {
+        if (arch_trap_init_quirk) {
+                if (arch_trap_init_quirk())
+                        return;
+        }
 }
 
 static struct irqaction irq0  = {
@@ -99,6 +119,16 @@ static struct irqaction irq0  = {
  **/
 void __init time_init_hook(void)
 {
+        if (arch_time_init_quirk) {
+                /*
+                 * A nonzero return code does not mean failure, it means
+                 * that the architecture quirk does not want any
+                 * generic (timer) setup to be performed after this:
+                 */
+                if (arch_time_init_quirk())
+                        return;
+        }
+
         irq0.mask = cpumask_of_cpu(0);
         setup_irq(0, &irq0);
 }
@@ -142,45 +172,3 @@ static int __init print_ipi_mode(void)
 
 late_initcall(print_ipi_mode);
 
-/**
- * machine_specific_memory_setup - Hook for machine specific memory setup.
- *
- * Description:
- *      This is included late in kernel/setup.c so that it can make
- *      use of all of the static functions.
- **/
-
-char * __init machine_specific_memory_setup(void)
-{
-        char *who;
-
-
-        who = "BIOS-e820";
-
-        /*
-         * Try to copy the BIOS-supplied E820-map.
-         *
-         * Otherwise fake a memory map; one section from 0k->640k,
-         * the next section from 1mb->appropriate_mem_k
-         */
-        sanitize_e820_map(boot_params.e820_map, &boot_params.e820_entries);
-        if (copy_e820_map(boot_params.e820_map, boot_params.e820_entries)
-            < 0) {
-                unsigned long mem_size;
-
-                /* compare results from other methods and take the greater */
-                if (boot_params.alt_mem_k
-                    < boot_params.screen_info.ext_mem_k) {
-                        mem_size = boot_params.screen_info.ext_mem_k;
-                        who = "BIOS-88";
-                } else {
-                        mem_size = boot_params.alt_mem_k;
-                        who = "BIOS-e801";
-                }
-
-                e820.nr_map = 0;
-                add_memory_region(0, LOWMEMSIZE(), E820_RAM);
-                add_memory_region(HIGH_MEMORY, mem_size << 10, E820_RAM);
-        }
-        return who;
-}
diff --git a/arch/x86/mach-es7000/Makefile b/arch/x86/mach-es7000/Makefile
index 69dd4da218dc..3ef8b43b62fc 100644
--- a/arch/x86/mach-es7000/Makefile
+++ b/arch/x86/mach-es7000/Makefile
@@ -3,4 +3,3 @@
 #
 
 obj-$(CONFIG_X86_ES7000)        := es7000plat.o
-obj-$(CONFIG_X86_GENERICARCH)   := es7000plat.o
diff --git a/arch/x86/mach-es7000/es7000plat.c b/arch/x86/mach-es7000/es7000plat.c
index f5d6f7d8b86e..4354ce804889 100644
--- a/arch/x86/mach-es7000/es7000plat.c
+++ b/arch/x86/mach-es7000/es7000plat.c
@@ -52,6 +52,8 @@ static struct mip_reg		*host_reg;
 static int                      mip_port;
 static unsigned long            mip_addr, host_addr;
 
+int es7000_plat;
+
 /*
  * GSI override for ES7000 platforms.
  */
@@ -175,53 +177,6 @@ find_unisys_acpi_oem_table(unsigned long *oem_addr)
 }
 #endif
 
-/*
- * This file also gets compiled if CONFIG_X86_GENERICARCH is set. Generic
- * arch already has got following function definitions (asm-generic/es7000.c)
- * hence no need to define these for that case.
- */
-#ifndef CONFIG_X86_GENERICARCH
-void es7000_sw_apic(void);
-void __init enable_apic_mode(void)
-{
-        es7000_sw_apic();
-        return;
-}
-
-__init int mps_oem_check(struct mp_config_table *mpc, char *oem,
-                char *productid)
-{
-        if (mpc->mpc_oemptr) {
-                struct mp_config_oemtable *oem_table =
-                        (struct mp_config_oemtable *)mpc->mpc_oemptr;
-                if (!strncmp(oem, "UNISYS", 6))
-                        return parse_unisys_oem((char *)oem_table);
-        }
-        return 0;
-}
-#ifdef CONFIG_ACPI
-/* Hook from generic ACPI tables.c */
-int __init acpi_madt_oem_check(char *oem_id, char *oem_table_id)
-{
-        unsigned long oem_addr;
-        if (!find_unisys_acpi_oem_table(&oem_addr)) {
-                if (es7000_check_dsdt())
-                        return parse_unisys_oem((char *)oem_addr);
-                else {
-                        setup_unisys();
-                        return 1;
-                }
-        }
-        return 0;
-}
-#else
-int __init acpi_madt_oem_check(char *oem_id, char *oem_table_id)
-{
-        return 0;
-}
-#endif
-#endif /* COFIG_X86_GENERICARCH */
-
 static void
 es7000_spin(int n)
 {
diff --git a/arch/x86/mach-generic/Makefile b/arch/x86/mach-generic/Makefile
index 19d6d407737b..0dbd7803a1d5 100644
--- a/arch/x86/mach-generic/Makefile
+++ b/arch/x86/mach-generic/Makefile
@@ -2,7 +2,11 @@
 # Makefile for the generic architecture
 #
 
-EXTRA_CFLAGS    := -Iarch/x86/kernel
+EXTRA_CFLAGS                    := -Iarch/x86/kernel
 
-obj-y           := probe.o summit.o bigsmp.o es7000.o default.o 
-obj-y           += ../../x86/mach-es7000/
+obj-y                           := probe.o default.o
+obj-$(CONFIG_X86_NUMAQ)         += numaq.o
+obj-$(CONFIG_X86_SUMMIT)        += summit.o
+obj-$(CONFIG_X86_BIGSMP)        += bigsmp.o
+obj-$(CONFIG_X86_ES7000)        += es7000.o
+obj-$(CONFIG_X86_ES7000)        += ../../x86/mach-es7000/
diff --git a/arch/x86/mach-generic/bigsmp.c b/arch/x86/mach-generic/bigsmp.c
index 95fc463056d0..59d771714559 100644
--- a/arch/x86/mach-generic/bigsmp.c
+++ b/arch/x86/mach-generic/bigsmp.c
@@ -23,10 +23,8 @@ static int dmi_bigsmp; /* can be set by dmi scanners */
 
 static int hp_ht_bigsmp(const struct dmi_system_id *d)
 {
-#ifdef CONFIG_X86_GENERICARCH
         printk(KERN_NOTICE "%s detected: force use of apic=bigsmp\n", d->ident);
         dmi_bigsmp = 1;
-#endif
         return 0;
 }
 
@@ -48,7 +46,7 @@ static const struct dmi_system_id bigsmp_dmi_table[] = {
 static int probe_bigsmp(void)
 {
         if (def_to_bigsmp)
-        dmi_bigsmp = 1;
+                dmi_bigsmp = 1;
         else
                 dmi_check_system(bigsmp_dmi_table);
         return dmi_bigsmp;
diff --git a/arch/x86/mach-generic/numaq.c b/arch/x86/mach-generic/numaq.c
new file mode 100644
index 000000000000..8091e68764c4
--- /dev/null
+++ b/arch/x86/mach-generic/numaq.c
@@ -0,0 +1,41 @@
+/*
+ * APIC driver for the IBM NUMAQ chipset.
+ */
+#define APIC_DEFINITION 1
+#include <linux/threads.h>
+#include <linux/cpumask.h>
+#include <linux/smp.h>
+#include <asm/mpspec.h>
+#include <asm/genapic.h>
+#include <asm/fixmap.h>
+#include <asm/apicdef.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/init.h>
+#include <asm/mach-numaq/mach_apic.h>
+#include <asm/mach-numaq/mach_apicdef.h>
+#include <asm/mach-numaq/mach_ipi.h>
+#include <asm/mach-numaq/mach_mpparse.h>
+#include <asm/mach-numaq/mach_wakecpu.h>
+#include <asm/numaq.h>
+
+static int mps_oem_check(struct mp_config_table *mpc, char *oem,
+                char *productid)
+{
+        numaq_mps_oem_check(mpc, oem, productid);
+        return found_numaq;
+}
+
+static int probe_numaq(void)
+{
+        /* already know from get_memcfg_numaq() */
+        return found_numaq;
+}
+
+/* Hook from generic ACPI tables.c */
+static int acpi_madt_oem_check(char *oem_id, char *oem_table_id)
+{
+        return 0;
+}
+
+struct genapic apic_numaq = APIC_INIT("NUMAQ", probe_numaq);
diff --git a/arch/x86/mach-generic/probe.c b/arch/x86/mach-generic/probe.c
index c5ae751b994a..5a7e4619e1c4 100644
--- a/arch/x86/mach-generic/probe.c
+++ b/arch/x86/mach-generic/probe.c
@@ -16,6 +16,7 @@
 #include <asm/apicdef.h>
 #include <asm/genapic.h>
 
+extern struct genapic apic_numaq;
 extern struct genapic apic_summit;
 extern struct genapic apic_bigsmp;
 extern struct genapic apic_es7000;
@@ -24,9 +25,18 @@ extern struct genapic apic_default;
 struct genapic *genapic = &apic_default;
 
 static struct genapic *apic_probe[] __initdata = {
+#ifdef CONFIG_X86_NUMAQ
+        &apic_numaq,
+#endif
+#ifdef CONFIG_X86_SUMMIT
         &apic_summit,
+#endif
+#ifdef CONFIG_X86_BIGSMP
         &apic_bigsmp,
+#endif
+#ifdef CONFIG_X86_ES7000
         &apic_es7000,
+#endif
         &apic_default,  /* must be last */
         NULL,
 };
@@ -54,6 +64,7 @@ early_param("apic", parse_apic);
 
 void __init generic_bigsmp_probe(void)
 {
+#ifdef CONFIG_X86_BIGSMP
         /*
          * This routine is used to switch to bigsmp mode when
          * - There is no apic= option specified by the user
@@ -67,6 +78,7 @@ void __init generic_bigsmp_probe(void)
                         printk(KERN_INFO "Overriding APIC driver with %s\n",
                                genapic->name);
                 }
+#endif
 }
 
 void __init generic_apic_probe(void)
@@ -88,7 +100,8 @@ void __init generic_apic_probe(void)
 
 /* These functions can switch the APIC even after the initial ->probe() */
 
-int __init mps_oem_check(struct mp_config_table *mpc, char *oem, char *productid)
+int __init mps_oem_check(struct mp_config_table *mpc, char *oem,
+                                 char *productid)
 {
         int i;
         for (i = 0; apic_probe[i]; ++i) {
diff --git a/arch/x86/mach-visws/Makefile b/arch/x86/mach-visws/Makefile
deleted file mode 100644
index 835fd96ad768..000000000000
--- a/arch/x86/mach-visws/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Makefile for the linux kernel.
-#
-
-obj-y                           := setup.o traps.o reboot.o
-
-obj-$(CONFIG_X86_VISWS_APIC)    += visws_apic.o
-obj-$(CONFIG_X86_LOCAL_APIC)    += mpparse.o
diff --git a/arch/x86/mach-visws/mpparse.c b/arch/x86/mach-visws/mpparse.c
deleted file mode 100644
index 57484e91ab90..000000000000
--- a/arch/x86/mach-visws/mpparse.c
+++ /dev/null
@@ -1,88 +0,0 @@
-
-#include <linux/init.h>
-#include <linux/smp.h>
-
-#include <asm/smp.h>
-#include <asm/io.h>
-
-#include "cobalt.h"
-#include "mach_apic.h"
-
-/* Have we found an MP table */
-int smp_found_config;
-
-int pic_mode;
-
-extern unsigned int __cpuinitdata maxcpus;
-
-/*
- * The Visual Workstation is Intel MP compliant in the hardware
- * sense, but it doesn't have a BIOS(-configuration table).
- * No problem for Linux.
- */
-
-static void __init MP_processor_info (struct mpc_config_processor *m)
-{
-        int ver, logical_apicid;
-        physid_mask_t apic_cpus;
-
-        if (!(m->mpc_cpuflag & CPU_ENABLED))
-                return;
-
-        logical_apicid = m->mpc_apicid;
-        printk(KERN_INFO "%sCPU #%d %u:%u APIC version %d\n",
-               m->mpc_cpuflag & CPU_BOOTPROCESSOR ? "Bootup " : "",
-               m->mpc_apicid,
-               (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8,
-               (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4,
-               m->mpc_apicver);
-
-        if (m->mpc_cpuflag & CPU_BOOTPROCESSOR)
-                boot_cpu_physical_apicid = m->mpc_apicid;
-
-        ver = m->mpc_apicver;
-        if ((ver >= 0x14 && m->mpc_apicid >= 0xff) || m->mpc_apicid >= 0xf) {
-                printk(KERN_ERR "Processor #%d INVALID. (Max ID: %d).\n",
-                        m->mpc_apicid, MAX_APICS);
-                return;
-        }
-
-        apic_cpus = apicid_to_cpu_present(m->mpc_apicid);
-        physids_or(phys_cpu_present_map, phys_cpu_present_map, apic_cpus);
-        /*
-         * Validate version
-         */
-        if (ver == 0x0) {
-                printk(KERN_ERR "BIOS bug, APIC version is 0 for CPU#%d! "
-                        "fixing up to 0x10. (tell your hw vendor)\n",
-                        m->mpc_apicid);
-                ver = 0x10;
-        }
-        apic_version[m->mpc_apicid] = ver;
-}
-
-void __init find_smp_config(void)
-{
-        struct mpc_config_processor *mp = phys_to_virt(CO_CPU_TAB_PHYS);
-        unsigned short ncpus = readw(phys_to_virt(CO_CPU_NUM_PHYS));
-
-        if (ncpus > CO_CPU_MAX) {
-                printk(KERN_WARNING "find_visws_smp: got cpu count of %d at %p\n",
-                        ncpus, mp);
-
-                ncpus = CO_CPU_MAX;
-        }
-
-        if (ncpus > maxcpus)
-                ncpus = maxcpus;
-
-        smp_found_config = 1;
-        while (ncpus--)
-                MP_processor_info(mp++);
-
-        mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
-}
-
-void __init get_smp_config (void)
-{
-}
diff --git a/arch/x86/mach-visws/reboot.c b/arch/x86/mach-visws/reboot.c
deleted file mode 100644
index 99332abfad42..000000000000
--- a/arch/x86/mach-visws/reboot.c
+++ /dev/null
@@ -1,55 +0,0 @@
-#include <linux/module.h>
-#include <linux/smp.h>
-#include <linux/delay.h>
-
-#include <asm/io.h>
-#include "piix4.h"
-
-void (*pm_power_off)(void);
-EXPORT_SYMBOL(pm_power_off);
-
-void machine_shutdown(void)
-{
-#ifdef CONFIG_SMP
-        smp_send_stop();
-#endif
-}
-
-void machine_emergency_restart(void)
-{
-        /*
-         * Visual Workstations restart after this
-         * register is poked on the PIIX4
-         */
-        outb(PIIX4_RESET_VAL, PIIX4_RESET_PORT);
-}
-
-void machine_restart(char * __unused)
-{
-        machine_shutdown();
-        machine_emergency_restart();
-}
-
-void machine_power_off(void)
-{
-        unsigned short pm_status;
-        extern unsigned int pci_bus0;
-
-        while ((pm_status = inw(PMSTS_PORT)) & 0x100)
-                outw(pm_status, PMSTS_PORT);
-
-        outw(PM_SUSPEND_ENABLE, PMCNTRL_PORT);
-
-        mdelay(10);
-
-#define PCI_CONF1_ADDRESS(bus, devfn, reg) \
-        (0x80000000 | (bus << 16) | (devfn << 8) | (reg & ~3))
-
-        outl(PCI_CONF1_ADDRESS(pci_bus0, SPECIAL_DEV, SPECIAL_REG), 0xCF8);
-        outl(PIIX_SPECIAL_STOP, 0xCFC);
-}
-
-void machine_halt(void)
-{
-}
-
diff --git a/arch/x86/mach-visws/setup.c b/arch/x86/mach-visws/setup.c
deleted file mode 100644
index de4c9dbd086f..000000000000
--- a/arch/x86/mach-visws/setup.c
+++ /dev/null
@@ -1,183 +0,0 @@
-/*
- *  Unmaintained SGI Visual Workstation support.
- *  Split out from setup.c by davej@suse.de
- */
-
-#include <linux/smp.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/module.h>
-
-#include <asm/fixmap.h>
-#include <asm/arch_hooks.h>
-#include <asm/io.h>
-#include <asm/e820.h>
-#include <asm/setup.h>
-#include "cobalt.h"
-#include "piix4.h"
-
-int no_broadcast;
-
-char visws_board_type = -1;
-char visws_board_rev = -1;
-
-void __init visws_get_board_type_and_rev(void)
-{
-        int raw;
-
-        visws_board_type = (char)(inb_p(PIIX_GPI_BD_REG) & PIIX_GPI_BD_REG)
-                                                         >> PIIX_GPI_BD_SHIFT;
-        /*
-         * Get Board rev.
-         * First, we have to initialize the 307 part to allow us access
-         * to the GPIO registers.  Let's map them at 0x0fc0 which is right
-         * after the PIIX4 PM section.
-         */
-        outb_p(SIO_DEV_SEL, SIO_INDEX);
-        outb_p(SIO_GP_DEV, SIO_DATA);   /* Talk to GPIO regs. */
-
-        outb_p(SIO_DEV_MSB, SIO_INDEX);
-        outb_p(SIO_GP_MSB, SIO_DATA);   /* MSB of GPIO base address */
-
-        outb_p(SIO_DEV_LSB, SIO_INDEX);
-        outb_p(SIO_GP_LSB, SIO_DATA);   /* LSB of GPIO base address */
-
-        outb_p(SIO_DEV_ENB, SIO_INDEX);
-        outb_p(1, SIO_DATA);            /* Enable GPIO registers. */
-
-        /*
-         * Now, we have to map the power management section to write
-         * a bit which enables access to the GPIO registers.
-         * What lunatic came up with this shit?
-         */
-        outb_p(SIO_DEV_SEL, SIO_INDEX);
-        outb_p(SIO_PM_DEV, SIO_DATA);   /* Talk to GPIO regs. */
-
-        outb_p(SIO_DEV_MSB, SIO_INDEX);
-        outb_p(SIO_PM_MSB, SIO_DATA);   /* MSB of PM base address */
-
-        outb_p(SIO_DEV_LSB, SIO_INDEX);
-        outb_p(SIO_PM_LSB, SIO_DATA);   /* LSB of PM base address */
-
-        outb_p(SIO_DEV_ENB, SIO_INDEX);
-        outb_p(1, SIO_DATA);            /* Enable PM registers. */
-
-        /*
-         * Now, write the PM register which enables the GPIO registers.
-         */
-        outb_p(SIO_PM_FER2, SIO_PM_INDEX);
-        outb_p(SIO_PM_GP_EN, SIO_PM_DATA);
-
-        /*
-         * Now, initialize the GPIO registers.
-         * We want them all to be inputs which is the
-         * power on default, so let's leave them alone.
-         * So, let's just read the board rev!
-         */
-        raw = inb_p(SIO_GP_DATA1);
-        raw &= 0x7f;    /* 7 bits of valid board revision ID. */
-
-        if (visws_board_type == VISWS_320) {
-                if (raw < 0x6) {
-                        visws_board_rev = 4;
-                } else if (raw < 0xc) {
-                        visws_board_rev = 5;
-                } else {
-                        visws_board_rev = 6;
-                }
-        } else if (visws_board_type == VISWS_540) {
-                        visws_board_rev = 2;
-                } else {
-                        visws_board_rev = raw;
-                }
-
-        printk(KERN_INFO "Silicon Graphics Visual Workstation %s (rev %d) detected\n",
-               (visws_board_type == VISWS_320 ? "320" :
-               (visws_board_type == VISWS_540 ? "540" :
-                "unknown")), visws_board_rev);
-}
-
-void __init pre_intr_init_hook(void)
-{
-        init_VISWS_APIC_irqs();
-}
-
-void __init intr_init_hook(void)
-{
-#ifdef CONFIG_X86_LOCAL_APIC
-        apic_intr_init();
-#endif
-}
-
-void __init pre_setup_arch_hook()
-{
-        visws_get_board_type_and_rev();
-}
-
-static struct irqaction irq0 = {
-        .handler =      timer_interrupt,
-        .flags =        IRQF_DISABLED | IRQF_IRQPOLL,
-        .name =         "timer",
-};
-
-void __init time_init_hook(void)
-{
-        printk(KERN_INFO "Starting Cobalt Timer system clock\n");
-
-        /* Set the countdown value */
-        co_cpu_write(CO_CPU_TIMEVAL, CO_TIME_HZ/HZ);
-
-        /* Start the timer */
-        co_cpu_write(CO_CPU_CTRL, co_cpu_read(CO_CPU_CTRL) | CO_CTRL_TIMERUN);
-
-        /* Enable (unmask) the timer interrupt */
-        co_cpu_write(CO_CPU_CTRL, co_cpu_read(CO_CPU_CTRL) & ~CO_CTRL_TIMEMASK);
-
-        /* Wire cpu IDT entry to s/w handler (and Cobalt APIC to IDT) */
-        setup_irq(0, &irq0);
-}
-
-/* Hook for machine specific memory setup. */
-
-#define MB (1024 * 1024)
-
-unsigned long sgivwfb_mem_phys;
-unsigned long sgivwfb_mem_size;
-EXPORT_SYMBOL(sgivwfb_mem_phys);
-EXPORT_SYMBOL(sgivwfb_mem_size);
-
-long long mem_size __initdata = 0;
-
-char * __init machine_specific_memory_setup(void)
-{
-        long long gfx_mem_size = 8 * MB;
-
-        mem_size = boot_params.alt_mem_k;
-
-        if (!mem_size) {
-                printk(KERN_WARNING "Bootloader didn't set memory size, upgrade it !\n");
-                mem_size = 128 * MB;
-        }
-
-        /*
-         * this hardcodes the graphics memory to 8 MB
-         * it really should be sized dynamically (or at least
-         * set as a boot param)
-         */
-        if (!sgivwfb_mem_size) {
-                printk(KERN_WARNING "Defaulting to 8 MB framebuffer size\n");
-                sgivwfb_mem_size = 8 * MB;
-        }
-
-        /*
-         * Trim to nearest MB
-         */
-        sgivwfb_mem_size &= ~((1 << 20) - 1);
-        sgivwfb_mem_phys = mem_size - gfx_mem_size;
-
-        add_memory_region(0, LOWMEMSIZE(), E820_RAM);
-        add_memory_region(HIGH_MEMORY, mem_size - sgivwfb_mem_size - HIGH_MEMORY, E820_RAM);
-        add_memory_region(sgivwfb_mem_phys, sgivwfb_mem_size, E820_RESERVED);
-
-        return "PROM";
-}
diff --git a/arch/x86/mach-visws/traps.c b/arch/x86/mach-visws/traps.c
deleted file mode 100644
index bfac6ba10f8a..000000000000
--- a/arch/x86/mach-visws/traps.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/* VISWS traps */
-
-#include <linux/sched.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/pci.h>
-#include <linux/pci_ids.h>
-
-#include <asm/io.h>
-#include <asm/arch_hooks.h>
-#include <asm/apic.h>
-#include "cobalt.h"
-#include "lithium.h"
-
-
-#define A01234 (LI_INTA_0 | LI_INTA_1 | LI_INTA_2 | LI_INTA_3 | LI_INTA_4)
-#define BCD (LI_INTB | LI_INTC | LI_INTD)
-#define ALLDEVS (A01234 | BCD)
-
-static __init void lithium_init(void)
-{
-        set_fixmap(FIX_LI_PCIA, LI_PCI_A_PHYS);
-        set_fixmap(FIX_LI_PCIB, LI_PCI_B_PHYS);
-
-        if ((li_pcia_read16(PCI_VENDOR_ID) != PCI_VENDOR_ID_SGI) ||
-            (li_pcia_read16(PCI_DEVICE_ID) != PCI_DEVICE_ID_SGI_LITHIUM)) {
-                printk(KERN_EMERG "Lithium hostbridge %c not found\n", 'A');
-                panic("This machine is not SGI Visual Workstation 320/540");
-        }
-
-        if ((li_pcib_read16(PCI_VENDOR_ID) != PCI_VENDOR_ID_SGI) ||
-            (li_pcib_read16(PCI_DEVICE_ID) != PCI_DEVICE_ID_SGI_LITHIUM)) {
-                printk(KERN_EMERG "Lithium hostbridge %c not found\n", 'B');
-                panic("This machine is not SGI Visual Workstation 320/540");
-        }
-
-        li_pcia_write16(LI_PCI_INTEN, ALLDEVS);
-        li_pcib_write16(LI_PCI_INTEN, ALLDEVS);
-}
-
-static __init void cobalt_init(void)
-{
-        /*
-         * On normal SMP PC this is used only with SMP, but we have to
-         * use it and set it up here to start the Cobalt clock
-         */
-        set_fixmap(FIX_APIC_BASE, APIC_DEFAULT_PHYS_BASE);
-        setup_local_APIC();
-        printk(KERN_INFO "Local APIC Version %#x, ID %#x\n",
-                (unsigned int)apic_read(APIC_LVR),
-                (unsigned int)apic_read(APIC_ID));
-
-        set_fixmap(FIX_CO_CPU, CO_CPU_PHYS);
-        set_fixmap(FIX_CO_APIC, CO_APIC_PHYS);
-        printk(KERN_INFO "Cobalt Revision %#lx, APIC ID %#lx\n",
-                co_cpu_read(CO_CPU_REV), co_apic_read(CO_APIC_ID));
-
-        /* Enable Cobalt APIC being careful to NOT change the ID! */
-        co_apic_write(CO_APIC_ID, co_apic_read(CO_APIC_ID) | CO_APIC_ENABLE);
-
-        printk(KERN_INFO "Cobalt APIC enabled: ID reg %#lx\n",
-                co_apic_read(CO_APIC_ID));
-}
-
-void __init trap_init_hook(void)
-{
-        lithium_init();
-        cobalt_init();
-}
diff --git a/arch/x86/mach-visws/visws_apic.c b/arch/x86/mach-visws/visws_apic.c
deleted file mode 100644
index cef9cb1d15ac..000000000000
--- a/arch/x86/mach-visws/visws_apic.c
+++ /dev/null
@@ -1,297 +0,0 @@
-/*
- *      Copyright (C) 1999 Bent Hagemark, Ingo Molnar
- *
- *  SGI Visual Workstation interrupt controller
- *
- *  The Cobalt system ASIC in the Visual Workstation contains a "Cobalt" APIC
- *  which serves as the main interrupt controller in the system.  Non-legacy
- *  hardware in the system uses this controller directly.  Legacy devices
- *  are connected to the PIIX4 which in turn has its 8259(s) connected to
- *  a of the Cobalt APIC entry.
- *
- *  09/02/2000 - Updated for 2.4 by jbarnes@sgi.com
- *
- *  25/11/2002 - Updated for 2.5 by Andrey Panin <pazke@orbita1.ru>
- */
-
-#include <linux/kernel_stat.h>
-#include <linux/interrupt.h>
-#include <linux/init.h>
-
-#include <asm/io.h>
-#include <asm/apic.h>
-#include <asm/i8259.h>
-
-#include "cobalt.h"
-#include "irq_vectors.h"
-
-
-static DEFINE_SPINLOCK(cobalt_lock);
-
-/*
- * Set the given Cobalt APIC Redirection Table entry to point
- * to the given IDT vector/index.
- */
-static inline void co_apic_set(int entry, int irq)
-{
-        co_apic_write(CO_APIC_LO(entry), CO_APIC_LEVEL | (irq + FIRST_EXTERNAL_VECTOR));
-        co_apic_write(CO_APIC_HI(entry), 0);
-}
-
-/*
- * Cobalt (IO)-APIC functions to handle PCI devices.
- */
-static inline int co_apic_ide0_hack(void)
-{
-        extern char visws_board_type;
-        extern char visws_board_rev;
-
-        if (visws_board_type == VISWS_320 && visws_board_rev == 5)
-                return 5;
-        return CO_APIC_IDE0;
-}
-
-static int is_co_apic(unsigned int irq)
-{
-        if (IS_CO_APIC(irq))
-                return CO_APIC(irq);
-
-        switch (irq) {
-                case 0: return CO_APIC_CPU;
-                case CO_IRQ_IDE0: return co_apic_ide0_hack();
-                case CO_IRQ_IDE1: return CO_APIC_IDE1;
-                default: return -1;
-        }
-}
-
-
-/*
- * This is the SGI Cobalt (IO-)APIC:
- */
-
-static void enable_cobalt_irq(unsigned int irq)
-{
-        co_apic_set(is_co_apic(irq), irq);
-}
-
-static void disable_cobalt_irq(unsigned int irq)
-{
-        int entry = is_co_apic(irq);
-
-        co_apic_write(CO_APIC_LO(entry), CO_APIC_MASK);
-        co_apic_read(CO_APIC_LO(entry));
-}
-
-/*
- * "irq" really just serves to identify the device.  Here is where we
- * map this to the Cobalt APIC entry where it's physically wired.
- * This is called via request_irq -> setup_irq -> irq_desc->startup()
- */
-static unsigned int startup_cobalt_irq(unsigned int irq)
-{
-        unsigned long flags;
-
-        spin_lock_irqsave(&cobalt_lock, flags);
-        if ((irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS | IRQ_WAITING)))
-                irq_desc[irq].status &= ~(IRQ_DISABLED | IRQ_INPROGRESS | IRQ_WAITING);
-        enable_cobalt_irq(irq);
-        spin_unlock_irqrestore(&cobalt_lock, flags);
-        return 0;
-}
-
-static void ack_cobalt_irq(unsigned int irq)
-{
-        unsigned long flags;
-
-        spin_lock_irqsave(&cobalt_lock, flags);
-        disable_cobalt_irq(irq);
-        apic_write(APIC_EOI, APIC_EIO_ACK);
-        spin_unlock_irqrestore(&cobalt_lock, flags);
-}
-
-static void end_cobalt_irq(unsigned int irq)
-{
-        unsigned long flags;
-
-        spin_lock_irqsave(&cobalt_lock, flags);
-        if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
-                enable_cobalt_irq(irq);
-        spin_unlock_irqrestore(&cobalt_lock, flags);
-}
-
-static struct irq_chip cobalt_irq_type = {
-        .typename =     "Cobalt-APIC",
-        .startup =      startup_cobalt_irq,
-        .shutdown =     disable_cobalt_irq,
-        .enable =       enable_cobalt_irq,
-        .disable =      disable_cobalt_irq,
-        .ack =          ack_cobalt_irq,
-        .end =          end_cobalt_irq,
-};
-
-
-/*
- * This is the PIIX4-based 8259 that is wired up indirectly to Cobalt
- * -- not the manner expected by the code in i8259.c.
- *
- * there is a 'master' physical interrupt source that gets sent to
- * the CPU. But in the chipset there are various 'virtual' interrupts
- * waiting to be handled. We represent this to Linux through a 'master'
- * interrupt controller type, and through a special virtual interrupt-
- * controller. Device drivers only see the virtual interrupt sources.
- */
-static unsigned int startup_piix4_master_irq(unsigned int irq)
-{
-        init_8259A(0);
-
-        return startup_cobalt_irq(irq);
-}
-
-static void end_piix4_master_irq(unsigned int irq)
-{
-        unsigned long flags;
-
-        spin_lock_irqsave(&cobalt_lock, flags);
-        enable_cobalt_irq(irq);
-        spin_unlock_irqrestore(&cobalt_lock, flags);
-}
-
-static struct irq_chip piix4_master_irq_type = {
-        .typename =     "PIIX4-master",
-        .startup =      startup_piix4_master_irq,
-        .ack =          ack_cobalt_irq,
-        .end =          end_piix4_master_irq,
-};
-
-
-static struct irq_chip piix4_virtual_irq_type = {
-        .typename =     "PIIX4-virtual",
-        .shutdown =     disable_8259A_irq,
-        .enable =       enable_8259A_irq,
-        .disable =      disable_8259A_irq,
-};
-
-
-/*
- * PIIX4-8259 master/virtual functions to handle interrupt requests
- * from legacy devices: floppy, parallel, serial, rtc.
- *
- * None of these get Cobalt APIC entries, neither do they have IDT
- * entries. These interrupts are purely virtual and distributed from
- * the 'master' interrupt source: CO_IRQ_8259.
- *
- * When the 8259 interrupts its handler figures out which of these
- * devices is interrupting and dispatches to its handler.
- *
- * CAREFUL: devices see the 'virtual' interrupt only. Thus disable/
- * enable_irq gets the right irq. This 'master' irq is never directly
- * manipulated by any driver.
- */
-static irqreturn_t piix4_master_intr(int irq, void *dev_id)
-{
-        int realirq;
-        irq_desc_t *desc;
-        unsigned long flags;
-
-        spin_lock_irqsave(&i8259A_lock, flags);
-
-        /* Find out what's interrupting in the PIIX4 master 8259 */
-        outb(0x0c, 0x20);               /* OCW3 Poll command */
-        realirq = inb(0x20);
-
-        /*
-         * Bit 7 == 0 means invalid/spurious
-         */
-        if (unlikely(!(realirq & 0x80)))
-                goto out_unlock;
-
-        realirq &= 7;
-
-        if (unlikely(realirq == 2)) {
-                outb(0x0c, 0xa0);
-                realirq = inb(0xa0);
-
-                if (unlikely(!(realirq & 0x80)))
-                        goto out_unlock;
-
-                realirq = (realirq & 7) + 8;
-        }
-
-        /* mask and ack interrupt */
-        cached_irq_mask |= 1 << realirq;
-        if (unlikely(realirq > 7)) {
-                inb(0xa1);
-                outb(cached_slave_mask, 0xa1);
-                outb(0x60 + (realirq & 7), 0xa0);
-                outb(0x60 + 2, 0x20);
-        } else {
-                inb(0x21);
-                outb(cached_master_mask, 0x21);
-                outb(0x60 + realirq, 0x20);
-        }
-
-        spin_unlock_irqrestore(&i8259A_lock, flags);
-
-        desc = irq_desc + realirq;
-
-        /*
-         * handle this 'virtual interrupt' as a Cobalt one now.
-         */
-        kstat_cpu(smp_processor_id()).irqs[realirq]++;
-
-        if (likely(desc->action != NULL))
-                handle_IRQ_event(realirq, desc->action);
-
-        if (!(desc->status & IRQ_DISABLED))
-                enable_8259A_irq(realirq);
-
-        return IRQ_HANDLED;
-
-out_unlock:
-        spin_unlock_irqrestore(&i8259A_lock, flags);
-        return IRQ_NONE;
-}
-
-static struct irqaction master_action = {
-        .handler =      piix4_master_intr,
-        .name =         "PIIX4-8259",
-};
-
-static struct irqaction cascade_action = {
-        .handler =      no_action,
-        .name =         "cascade",
-};
-
-
-void init_VISWS_APIC_irqs(void)
-{
-        int i;
-
-        for (i = 0; i < CO_IRQ_APIC0 + CO_APIC_LAST + 1; i++) {
-                irq_desc[i].status = IRQ_DISABLED;
-                irq_desc[i].action = 0;
-                irq_desc[i].depth = 1;
-
-                if (i == 0) {
-                        irq_desc[i].chip = &cobalt_irq_type;
-                }
-                else if (i == CO_IRQ_IDE0) {
-                        irq_desc[i].chip = &cobalt_irq_type;
-                }
-                else if (i == CO_IRQ_IDE1) {
-                        irq_desc[i].chip = &cobalt_irq_type;
-                }
-                else if (i == CO_IRQ_8259) {
-                        irq_desc[i].chip = &piix4_master_irq_type;
-                }
-                else if (i < CO_IRQ_APIC0) {
-                        irq_desc[i].chip = &piix4_virtual_irq_type;
-                }
-                else if (IS_CO_APIC(i)) {
-                        irq_desc[i].chip = &cobalt_irq_type;
-                }
-        }
-
-        setup_irq(CO_IRQ_8259, &master_action);
-        setup_irq(2, &cascade_action);
-}
diff --git a/arch/x86/mach-voyager/setup.c b/arch/x86/mach-voyager/setup.c
index 5ae5466b9eb9..6bbdd633864c 100644
--- a/arch/x86/mach-voyager/setup.c
+++ b/arch/x86/mach-voyager/setup.c
@@ -62,6 +62,7 @@ void __init time_init_hook(void)
 char *__init machine_specific_memory_setup(void)
 {
         char *who;
+        int new_nr;
 
         who = "NOT VOYAGER";
 
@@ -73,7 +74,7 @@ char *__init machine_specific_memory_setup(void)
 
                 e820.nr_map = 0;
                 for (i = 0; voyager_memory_detect(i, &addr, &length); i++) {
-                        add_memory_region(addr, length, E820_RAM);
+                        e820_add_region(addr, length, E820_RAM);
                 }
                 return who;
         } else if (voyager_level == 4) {
@@ -91,43 +92,17 @@ char *__init machine_specific_memory_setup(void)
                         tom = (boot_params.screen_info.ext_mem_k) << 10;
                 }
                 who = "Voyager-TOM";
-                add_memory_region(0, 0x9f000, E820_RAM);
+                e820_add_region(0, 0x9f000, E820_RAM);
                 /* map from 1M to top of memory */
-                add_memory_region(1 * 1024 * 1024, tom - 1 * 1024 * 1024,
+                e820_add_region(1 * 1024 * 1024, tom - 1 * 1024 * 1024,
                                   E820_RAM);
                 /* FIXME: Should check the ASICs to see if I need to
                  * take out the 8M window.  Just do it at the moment
                  * */
-                add_memory_region(8 * 1024 * 1024, 8 * 1024 * 1024,
+                e820_add_region(8 * 1024 * 1024, 8 * 1024 * 1024,
                                   E820_RESERVED);
                 return who;
         }
 
-        who = "BIOS-e820";
-
-        /*
-         * Try to copy the BIOS-supplied E820-map.
-         *
-         * Otherwise fake a memory map; one section from 0k->640k,
-         * the next section from 1mb->appropriate_mem_k
-         */
-        sanitize_e820_map(boot_params.e820_map, &boot_params.e820_entries);
-        if (copy_e820_map(boot_params.e820_map, boot_params.e820_entries)
-            < 0) {
-                unsigned long mem_size;
-
-                /* compare results from other methods and take the greater */
-                if (boot_params.alt_mem_k < boot_params.screen_info.ext_mem_k) {
-                        mem_size = boot_params.screen_info.ext_mem_k;
-                        who = "BIOS-88";
-                } else {
-                        mem_size = boot_params.alt_mem_k;
-                        who = "BIOS-e801";
-                }
-
-                e820.nr_map = 0;
-                add_memory_region(0, LOWMEMSIZE(), E820_RAM);
-                add_memory_region(HIGH_MEMORY, mem_size << 10, E820_RAM);
-        }
-        return who;
+        return default_machine_specific_memory_setup();
 }
diff --git a/arch/x86/mach-voyager/voyager_smp.c b/arch/x86/mach-voyager/voyager_smp.c
index 8acbf0cdf1a5..8dedd01e909f 100644
--- a/arch/x86/mach-voyager/voyager_smp.c
+++ b/arch/x86/mach-voyager/voyager_smp.c
@@ -59,11 +59,6 @@ __u32 voyager_quad_processors = 0;
  * activity count.  Finally exported by i386_ksyms.c */
 static int voyager_extended_cpus = 1;
 
-/* Have we found an SMP box - used by time.c to do the profiling
-   interrupt for timeslicing; do not set to 1 until the per CPU timer
-   interrupt is active */
-int smp_found_config = 0;
-
 /* Used for the invalidate map that's also checked in the spinlock */
 static volatile unsigned long smp_invalidate_needed;
 
@@ -1137,15 +1132,6 @@ void flush_tlb_all(void)
         on_each_cpu(do_flush_tlb_all, 0, 1, 1);
 }
 
-/* used to set up the trampoline for other CPUs when the memory manager
- * is sorted out */
-void __init smp_alloc_memory(void)
-{
-        trampoline_base = alloc_bootmem_low_pages(PAGE_SIZE);
-        if (__pa(trampoline_base) >= 0x93000)
-                BUG();
-}
-
 /* send a reschedule CPI to one CPU by physical CPU number*/
 static void voyager_smp_send_reschedule(int cpu)
 {
diff --git a/arch/x86/math-emu/reg_constant.c b/arch/x86/math-emu/reg_constant.c
index 04869e64b18e..00548354912f 100644
--- a/arch/x86/math-emu/reg_constant.c
+++ b/arch/x86/math-emu/reg_constant.c
@@ -16,8 +16,8 @@
 #include "reg_constant.h"
 #include "control_w.h"
 
-#define MAKE_REG(s,e,l,h) { l, h, \
-                            ((EXTENDED_Ebias+(e)) | ((SIGN_##s != 0)*0x8000)) }
+#define MAKE_REG(s, e, l, h) { l, h, \
+                ((EXTENDED_Ebias+(e)) | ((SIGN_##s != 0)*0x8000)) }
 
 FPU_REG const CONST_1 = MAKE_REG(POS, 0, 0x00000000, 0x80000000);
 #if 0
@@ -40,7 +40,7 @@ FPU_REG const CONST_PI2extra = MAKE_REG(NEG, -66,
 FPU_REG const CONST_Z = MAKE_REG(POS, EXP_UNDER, 0x0, 0x0);
 
 /* Only the sign and significand (and tag) are used in internal NaNs */
-/* The 80486 never generates one of these 
+/* The 80486 never generates one of these
 FPU_REG const CONST_SNAN = MAKE_REG(POS, EXP_OVER, 0x00000001, 0x80000000);
  */
 /* This is the real indefinite QNaN */
@@ -49,7 +49,7 @@ FPU_REG const CONST_QNaN = MAKE_REG(NEG, EXP_OVER, 0x00000000, 0xC0000000);
 /* Only the sign (and tag) is used in internal infinities */
 FPU_REG const CONST_INF = MAKE_REG(POS, EXP_OVER, 0x00000000, 0x80000000);
 
-static void fld_const(FPU_REG const *c, int adj, u_char tag)
+static void fld_const(FPU_REG const * c, int adj, u_char tag)
 {
         FPU_REG *st_new_ptr;
 
diff --git a/arch/x86/mm/Makefile b/arch/x86/mm/Makefile
index b7b3e4c7cfc9..9873716e9f76 100644
--- a/arch/x86/mm/Makefile
+++ b/arch/x86/mm/Makefile
@@ -8,10 +8,16 @@ obj-$(CONFIG_X86_PTDUMP)	+= dump_pagetables.o
 
 obj-$(CONFIG_HIGHMEM)           += highmem_32.o
 
+obj-$(CONFIG_MMIOTRACE_HOOKS)   += kmmio.o
+obj-$(CONFIG_MMIOTRACE)         += mmiotrace.o
+mmiotrace-y                     := pf_in.o mmio-mod.o
+obj-$(CONFIG_MMIOTRACE_TEST)    += testmmiotrace.o
+
 ifeq ($(CONFIG_X86_32),y)
 obj-$(CONFIG_NUMA)              += discontig_32.o
 else
 obj-$(CONFIG_NUMA)              += numa_64.o
 obj-$(CONFIG_K8_NUMA)           += k8topology_64.o
-obj-$(CONFIG_ACPI_NUMA)         += srat_64.o
 endif
+obj-$(CONFIG_ACPI_NUMA)         += srat_$(BITS).o
+
diff --git a/arch/x86/mm/discontig_32.c b/arch/x86/mm/discontig_32.c
index 914ccf983687..5dfef9fa061a 100644
--- a/arch/x86/mm/discontig_32.c
+++ b/arch/x86/mm/discontig_32.c
@@ -38,6 +38,7 @@
 #include <asm/setup.h>
 #include <asm/mmzone.h>
 #include <asm/bios_ebda.h>
+#include <asm/proto.h>
 
 struct pglist_data *node_data[MAX_NUMNODES] __read_mostly;
 EXPORT_SYMBOL(node_data);
@@ -59,14 +60,14 @@ unsigned long node_end_pfn[MAX_NUMNODES] __read_mostly;
 /*
  * 4) physnode_map     - the mapping between a pfn and owning node
  * physnode_map keeps track of the physical memory layout of a generic
- * numa node on a 256Mb break (each element of the array will
- * represent 256Mb of memory and will be marked by the node id.  so,
+ * numa node on a 64Mb break (each element of the array will
+ * represent 64Mb of memory and will be marked by the node id.  so,
  * if the first gig is on node 0, and the second gig is on node 1
  * physnode_map will contain:
  *
- *     physnode_map[0-3] = 0;
- *     physnode_map[4-7] = 1;
- *     physnode_map[8- ] = -1;
+ *     physnode_map[0-15] = 0;
+ *     physnode_map[16-31] = 1;
+ *     physnode_map[32- ] = -1;
  */
 s8 physnode_map[MAX_ELEMENTS] __read_mostly = { [0 ... (MAX_ELEMENTS - 1)] = -1};
 EXPORT_SYMBOL(physnode_map);
@@ -75,15 +76,15 @@ void memory_present(int nid, unsigned long start, unsigned long end)
 {
         unsigned long pfn;
 
-        printk(KERN_INFO "Node: %d, start_pfn: %ld, end_pfn: %ld\n",
+        printk(KERN_INFO "Node: %d, start_pfn: %lx, end_pfn: %lx\n",
                         nid, start, end);
         printk(KERN_DEBUG "  Setting physnode_map array to node %d for pfns:\n", nid);
         printk(KERN_DEBUG "  ");
         for (pfn = start; pfn < end; pfn += PAGES_PER_ELEMENT) {
                 physnode_map[pfn / PAGES_PER_ELEMENT] = nid;
-                printk("%ld ", pfn);
+                printk(KERN_CONT "%lx ", pfn);
         }
-        printk("\n");
+        printk(KERN_CONT "\n");
 }
 
 unsigned long node_memmap_size_bytes(int nid, unsigned long start_pfn,
@@ -99,7 +100,6 @@ unsigned long node_memmap_size_bytes(int nid, unsigned long start_pfn,
 #endif
 
 extern unsigned long find_max_low_pfn(void);
-extern void add_one_highpage_init(struct page *, int, int);
 extern unsigned long highend_pfn, highstart_pfn;
 
 #define LARGE_PAGE_BYTES (PTRS_PER_PTE * PAGE_SIZE)
@@ -117,13 +117,13 @@ static unsigned long kva_pages;
  */
 int __init get_memcfg_numa_flat(void)
 {
-        printk("NUMA - single node, flat memory mode\n");
+        printk(KERN_DEBUG "NUMA - single node, flat memory mode\n");
 
-        /* Run the memory configuration and find the top of memory. */
-        propagate_e820_map();
         node_start_pfn[0] = 0;
         node_end_pfn[0] = max_pfn;
+        e820_register_active_regions(0, 0, max_pfn);
         memory_present(0, 0, max_pfn);
+        node_remap_size[0] = node_memmap_size_bytes(0, 0, max_pfn);
 
         /* Indicate there is one node available. */
         nodes_clear(node_online_map);
@@ -156,24 +156,32 @@ static void __init propagate_e820_map_node(int nid)
  */
 static void __init allocate_pgdat(int nid)
 {
-        if (nid && node_has_online_mem(nid))
+        char buf[16];
+
+        if (node_has_online_mem(nid) && node_remap_start_vaddr[nid])
                 NODE_DATA(nid) = (pg_data_t *)node_remap_start_vaddr[nid];
         else {
-                NODE_DATA(nid) = (pg_data_t *)(pfn_to_kaddr(min_low_pfn));
-                min_low_pfn += PFN_UP(sizeof(pg_data_t));
+                unsigned long pgdat_phys;
+                pgdat_phys = find_e820_area(min_low_pfn<<PAGE_SHIFT,
+                                 max_pfn_mapped<<PAGE_SHIFT,
+                                 sizeof(pg_data_t),
+                                 PAGE_SIZE);
+                NODE_DATA(nid) = (pg_data_t *)(pfn_to_kaddr(pgdat_phys>>PAGE_SHIFT));
+                memset(buf, 0, sizeof(buf));
+                sprintf(buf, "NODE_DATA %d",  nid);
+                reserve_early(pgdat_phys, pgdat_phys + sizeof(pg_data_t), buf);
         }
+        printk(KERN_DEBUG "allocate_pgdat: node %d NODE_DATA %08lx\n",
+                nid, (unsigned long)NODE_DATA(nid));
 }
 
-#ifdef CONFIG_DISCONTIGMEM
 /*
- * In the discontig memory model, a portion of the kernel virtual area (KVA)
- * is reserved and portions of nodes are mapped using it. This is to allow
- * node-local memory to be allocated for structures that would normally require
- * ZONE_NORMAL. The memory is allocated with alloc_remap() and callers
- * should be prepared to allocate from the bootmem allocator instead. This KVA
- * mechanism is incompatible with SPARSEMEM as it makes assumptions about the
- * layout of memory that are broken if alloc_remap() succeeds for some of the
- * map and fails for others
+ * In the DISCONTIGMEM and SPARSEMEM memory model, a portion of the kernel
+ * virtual address space (KVA) is reserved and portions of nodes are mapped
+ * using it. This is to allow node-local memory to be allocated for
+ * structures that would normally require ZONE_NORMAL. The memory is
+ * allocated with alloc_remap() and callers should be prepared to allocate
+ * from the bootmem allocator instead.
  */
 static unsigned long node_remap_start_pfn[MAX_NUMNODES];
 static void *node_remap_end_vaddr[MAX_NUMNODES];
@@ -195,15 +203,19 @@ void *alloc_remap(int nid, unsigned long size)
         return allocation;
 }
 
-void __init remap_numa_kva(void)
+static void __init remap_numa_kva(void)
 {
         void *vaddr;
         unsigned long pfn;
         int node;
 
         for_each_online_node(node) {
+                printk(KERN_DEBUG "remap_numa_kva: node %d\n", node);
                 for (pfn=0; pfn < node_remap_size[node]; pfn += PTRS_PER_PTE) {
                         vaddr = node_remap_start_vaddr[node]+(pfn<<PAGE_SHIFT);
+                        printk(KERN_DEBUG "remap_numa_kva: %08lx to pfn %08lx\n",
+                                (unsigned long)vaddr,
+                                node_remap_start_pfn[node] + pfn);
                         set_pmd_pfn((ulong) vaddr, 
                                 node_remap_start_pfn[node] + pfn, 
                                 PAGE_KERNEL_LARGE);
@@ -215,17 +227,21 @@ static unsigned long calculate_numa_remap_pages(void)
 {
         int nid;
         unsigned long size, reserve_pages = 0;
-        unsigned long pfn;
 
         for_each_online_node(nid) {
-                unsigned old_end_pfn = node_end_pfn[nid];
+                u64 node_kva_target;
+                u64 node_kva_final;
 
                 /*
                  * The acpi/srat node info can show hot-add memroy zones
                  * where memory could be added but not currently present.
                  */
+                printk(KERN_DEBUG "node %d pfn: [%lx - %lx]\n",
+                        nid, node_start_pfn[nid], node_end_pfn[nid]);
                 if (node_start_pfn[nid] > max_pfn)
                         continue;
+                if (!node_end_pfn[nid])
+                        continue;
                 if (node_end_pfn[nid] > max_pfn)
                         node_end_pfn[nid] = max_pfn;
 
@@ -237,41 +253,48 @@ static unsigned long calculate_numa_remap_pages(void)
                 /* now the roundup is correct, convert to PAGE_SIZE pages */
                 size = size * PTRS_PER_PTE;
 
-                /*
-                 * Validate the region we are allocating only contains valid
-                 * pages.
-                 */
-                for (pfn = node_end_pfn[nid] - size;
-                     pfn < node_end_pfn[nid]; pfn++)
-                        if (!page_is_ram(pfn))
-                                break;
-
-                if (pfn != node_end_pfn[nid])
-                        size = 0;
+                node_kva_target = round_down(node_end_pfn[nid] - size,
+                                                 PTRS_PER_PTE);
+                node_kva_target <<= PAGE_SHIFT;
+                do {
+                        node_kva_final = find_e820_area(node_kva_target,
+                                        ((u64)node_end_pfn[nid])<<PAGE_SHIFT,
+                                                ((u64)size)<<PAGE_SHIFT,
+                                                LARGE_PAGE_BYTES);
+                        node_kva_target -= LARGE_PAGE_BYTES;
+                } while (node_kva_final == -1ULL &&
+                         (node_kva_target>>PAGE_SHIFT) > (node_start_pfn[nid]));
+
+                if (node_kva_final == -1ULL)
+                        panic("Can not get kva ram\n");
 
-                printk("Reserving %ld pages of KVA for lmem_map of node %d\n",
-                                size, nid);
                 node_remap_size[nid] = size;
                 node_remap_offset[nid] = reserve_pages;
                 reserve_pages += size;
-                printk("Shrinking node %d from %ld pages to %ld pages\n",
-                        nid, node_end_pfn[nid], node_end_pfn[nid] - size);
-
-                if (node_end_pfn[nid] & (PTRS_PER_PTE-1)) {
-                        /*
-                         * Align node_end_pfn[] and node_remap_start_pfn[] to
-                         * pmd boundary. remap_numa_kva will barf otherwise.
-                         */
-                        printk("Shrinking node %d further by %ld pages for proper alignment\n",
-                                nid, node_end_pfn[nid] & (PTRS_PER_PTE-1));
-                        size +=  node_end_pfn[nid] & (PTRS_PER_PTE-1);
-                }
+                printk(KERN_DEBUG "Reserving %ld pages of KVA for lmem_map of"
+                                  " node %d at %llx\n",
+                                size, nid, node_kva_final>>PAGE_SHIFT);
+
+                /*
+                 *  prevent kva address below max_low_pfn want it on system
+                 *  with less memory later.
+                 *  layout will be: KVA address , KVA RAM
+                 *
+                 *  we are supposed to only record the one less then max_low_pfn
+                 *  but we could have some hole in high memory, and it will only
+                 *  check page_is_ram(pfn) && !page_is_reserved_early(pfn) to decide
+                 *  to use it as free.
+                 *  So reserve_early here, hope we don't run out of that array
+                 */
+                reserve_early(node_kva_final,
+                              node_kva_final+(((u64)size)<<PAGE_SHIFT),
+                              "KVA RAM");
 
-                node_end_pfn[nid] -= size;
-                node_remap_start_pfn[nid] = node_end_pfn[nid];
-                shrink_active_range(nid, old_end_pfn, node_end_pfn[nid]);
+                node_remap_start_pfn[nid] = node_kva_final>>PAGE_SHIFT;
+                remove_active_range(nid, node_remap_start_pfn[nid],
+                                         node_remap_start_pfn[nid] + size);
         }
-        printk("Reserving total of %ld pages for numa KVA remap\n",
+        printk(KERN_INFO "Reserving total of %lx pages for numa KVA remap\n",
                         reserve_pages);
         return reserve_pages;
 }
@@ -285,37 +308,16 @@ static void init_remap_allocator(int nid)
         node_remap_alloc_vaddr[nid] = node_remap_start_vaddr[nid] +
                 ALIGN(sizeof(pg_data_t), PAGE_SIZE);
 
-        printk ("node %d will remap to vaddr %08lx - %08lx\n", nid,
+        printk(KERN_DEBUG "node %d will remap to vaddr %08lx - %08lx\n", nid,
                 (ulong) node_remap_start_vaddr[nid],
-                (ulong) pfn_to_kaddr(highstart_pfn
-                   + node_remap_offset[nid] + node_remap_size[nid]));
-}
-#else
-void *alloc_remap(int nid, unsigned long size)
-{
-        return NULL;
-}
-
-static unsigned long calculate_numa_remap_pages(void)
-{
-        return 0;
-}
-
-static void init_remap_allocator(int nid)
-{
-}
-
-void __init remap_numa_kva(void)
-{
+                (ulong) node_remap_end_vaddr[nid]);
 }
-#endif /* CONFIG_DISCONTIGMEM */
 
-extern void setup_bootmem_allocator(void);
-unsigned long __init setup_memory(void)
+void __init initmem_init(unsigned long start_pfn,
+                                  unsigned long end_pfn)
 {
         int nid;
-        unsigned long system_start_pfn, system_max_low_pfn;
-        unsigned long wasted_pages;
+        long kva_target_pfn;
 
         /*
          * When mapping a NUMA machine we allocate the node_mem_map arrays
@@ -324,109 +326,77 @@ unsigned long __init setup_memory(void)
          * this space and use it to adjust the boundary between ZONE_NORMAL
          * and ZONE_HIGHMEM.
          */
-        get_memcfg_numa();
 
-        kva_pages = calculate_numa_remap_pages();
+        get_memcfg_numa();
 
-        /* partially used pages are not usable - thus round upwards */
-        system_start_pfn = min_low_pfn = PFN_UP(init_pg_tables_end);
+        kva_pages = round_up(calculate_numa_remap_pages(), PTRS_PER_PTE);
 
-        kva_start_pfn = find_max_low_pfn() - kva_pages;
+        kva_target_pfn = round_down(max_low_pfn - kva_pages, PTRS_PER_PTE);
+        do {
+                kva_start_pfn = find_e820_area(kva_target_pfn<<PAGE_SHIFT,
+                                        max_low_pfn<<PAGE_SHIFT,
+                                        kva_pages<<PAGE_SHIFT,
+                                        PTRS_PER_PTE<<PAGE_SHIFT) >> PAGE_SHIFT;
+                kva_target_pfn -= PTRS_PER_PTE;
+        } while (kva_start_pfn == -1UL && kva_target_pfn > min_low_pfn);
 
-#ifdef CONFIG_BLK_DEV_INITRD
-        /* Numa kva area is below the initrd */
-        if (initrd_start)
-                kva_start_pfn = PFN_DOWN(initrd_start - PAGE_OFFSET)
-                        - kva_pages;
-#endif
+        if (kva_start_pfn == -1UL)
+                panic("Can not get kva space\n");
 
-        /*
-         * We waste pages past at the end of the KVA for no good reason other
-         * than how it is located. This is bad.
-         */
-        wasted_pages = kva_start_pfn & (PTRS_PER_PTE-1);
-        kva_start_pfn -= wasted_pages;
-        kva_pages += wasted_pages;
-
-        system_max_low_pfn = max_low_pfn = find_max_low_pfn();
-        printk("kva_start_pfn ~ %ld find_max_low_pfn() ~ %ld\n",
+        printk(KERN_INFO "kva_start_pfn ~ %lx max_low_pfn ~ %lx\n",
                 kva_start_pfn, max_low_pfn);
-        printk("max_pfn = %ld\n", max_pfn);
+        printk(KERN_INFO "max_pfn = %lx\n", max_pfn);
+
+        /* avoid clash with initrd */
+        reserve_early(kva_start_pfn<<PAGE_SHIFT,
+                      (kva_start_pfn + kva_pages)<<PAGE_SHIFT,
+                     "KVA PG");
 #ifdef CONFIG_HIGHMEM
         highstart_pfn = highend_pfn = max_pfn;
-        if (max_pfn > system_max_low_pfn)
-                highstart_pfn = system_max_low_pfn;
+        if (max_pfn > max_low_pfn)
+                highstart_pfn = max_low_pfn;
         printk(KERN_NOTICE "%ldMB HIGHMEM available.\n",
                pages_to_mb(highend_pfn - highstart_pfn));
         num_physpages = highend_pfn;
         high_memory = (void *) __va(highstart_pfn * PAGE_SIZE - 1) + 1;
 #else
-        num_physpages = system_max_low_pfn;
-        high_memory = (void *) __va(system_max_low_pfn * PAGE_SIZE - 1) + 1;
+        num_physpages = max_low_pfn;
+        high_memory = (void *) __va(max_low_pfn * PAGE_SIZE - 1) + 1;
 #endif
         printk(KERN_NOTICE "%ldMB LOWMEM available.\n",
-                        pages_to_mb(system_max_low_pfn));
-        printk("min_low_pfn = %ld, max_low_pfn = %ld, highstart_pfn = %ld\n", 
-                        min_low_pfn, max_low_pfn, highstart_pfn);
+                        pages_to_mb(max_low_pfn));
+        printk(KERN_DEBUG "max_low_pfn = %lx, highstart_pfn = %lx\n",
+                        max_low_pfn, highstart_pfn);
 
-        printk("Low memory ends at vaddr %08lx\n",
+        printk(KERN_DEBUG "Low memory ends at vaddr %08lx\n",
                         (ulong) pfn_to_kaddr(max_low_pfn));
         for_each_online_node(nid) {
                 init_remap_allocator(nid);
 
                 allocate_pgdat(nid);
         }
-        printk("High memory starts at vaddr %08lx\n",
+        remap_numa_kva();
+
+        printk(KERN_DEBUG "High memory starts at vaddr %08lx\n",
                         (ulong) pfn_to_kaddr(highstart_pfn));
         for_each_online_node(nid)
                 propagate_e820_map_node(nid);
 
-        memset(NODE_DATA(0), 0, sizeof(struct pglist_data));
+        for_each_online_node(nid)
+                memset(NODE_DATA(nid), 0, sizeof(struct pglist_data));
+
         NODE_DATA(0)->bdata = &node0_bdata;
         setup_bootmem_allocator();
-        return max_low_pfn;
-}
-
-void __init numa_kva_reserve(void)
-{
-        if (kva_pages)
-                reserve_bootmem(PFN_PHYS(kva_start_pfn), PFN_PHYS(kva_pages),
-                                BOOTMEM_DEFAULT);
 }
 
-void __init zone_sizes_init(void)
-{
-        int nid;
-        unsigned long max_zone_pfns[MAX_NR_ZONES];
-        memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
-        max_zone_pfns[ZONE_DMA] =
-                virt_to_phys((char *)MAX_DMA_ADDRESS) >> PAGE_SHIFT;
-        max_zone_pfns[ZONE_NORMAL] = max_low_pfn;
-#ifdef CONFIG_HIGHMEM
-        max_zone_pfns[ZONE_HIGHMEM] = highend_pfn;
-#endif
-
-        /* If SRAT has not registered memory, register it now */
-        if (find_max_pfn_with_active_regions() == 0) {
-                for_each_online_node(nid) {
-                        if (node_has_online_mem(nid))
-                                add_active_range(nid, node_start_pfn[nid],
-                                                        node_end_pfn[nid]);
-                }
-        }
-
-        free_area_init_nodes(max_zone_pfns);
-        return;
-}
-
-void __init set_highmem_pages_init(int bad_ppro) 
+void __init set_highmem_pages_init(void)
 {
 #ifdef CONFIG_HIGHMEM
         struct zone *zone;
-        struct page *page;
+        int nid;
 
         for_each_zone(zone) {
-                unsigned long node_pfn, zone_start_pfn, zone_end_pfn;
+                unsigned long zone_start_pfn, zone_end_pfn;
 
                 if (!is_highmem(zone))
                         continue;
@@ -434,16 +404,12 @@ void __init set_highmem_pages_init(int bad_ppro)
                 zone_start_pfn = zone->zone_start_pfn;
                 zone_end_pfn = zone_start_pfn + zone->spanned_pages;
 
-                printk("Initializing %s for node %d (%08lx:%08lx)\n",
-                                zone->name, zone_to_nid(zone),
-                                zone_start_pfn, zone_end_pfn);
+                nid = zone_to_nid(zone);
+                printk(KERN_INFO "Initializing %s for node %d (%08lx:%08lx)\n",
+                                zone->name, nid, zone_start_pfn, zone_end_pfn);
 
-                for (node_pfn = zone_start_pfn; node_pfn < zone_end_pfn; node_pfn++) {
-                        if (!pfn_valid(node_pfn))
-                                continue;
-                        page = pfn_to_page(node_pfn);
-                        add_one_highpage_init(page, node_pfn, bad_ppro);
-                }
+                add_highpages_with_active_regions(nid, zone_start_pfn,
+                                 zone_end_pfn);
         }
         totalram_pages += totalhigh_pages;
 #endif
@@ -476,3 +442,4 @@ int memory_add_physaddr_to_nid(u64 addr)
 
 EXPORT_SYMBOL_GPL(memory_add_physaddr_to_nid);
 #endif
+
diff --git a/arch/x86/mm/dump_pagetables.c b/arch/x86/mm/dump_pagetables.c
index 2c24bea92c66..0bb0caed8971 100644
--- a/arch/x86/mm/dump_pagetables.c
+++ b/arch/x86/mm/dump_pagetables.c
@@ -42,7 +42,7 @@ static struct addr_marker address_markers[] = {
         { 0, "User Space" },
 #ifdef CONFIG_X86_64
         { 0x8000000000000000UL, "Kernel Space" },
-        { 0xffff810000000000UL, "Low Kernel Mapping" },
+        { PAGE_OFFSET,          "Low Kernel Mapping" },
         { VMALLOC_START,        "vmalloc() Area" },
         { VMEMMAP_START,        "Vmemmap" },
         { __START_KERNEL_map,   "High Kernel Mapping" },
diff --git a/arch/x86/mm/fault.c b/arch/x86/mm/fault.c
index 8bcb6f40ccb6..455f3fe67b42 100644
--- a/arch/x86/mm/fault.c
+++ b/arch/x86/mm/fault.c
@@ -10,6 +10,7 @@
 #include <linux/string.h>
 #include <linux/types.h>
 #include <linux/ptrace.h>
+#include <linux/mmiotrace.h>
 #include <linux/mman.h>
 #include <linux/mm.h>
 #include <linux/smp.h>
@@ -49,17 +50,23 @@
 #define PF_RSVD         (1<<3)
 #define PF_INSTR        (1<<4)
 
+static inline int kmmio_fault(struct pt_regs *regs, unsigned long addr)
+{
+#ifdef CONFIG_MMIOTRACE_HOOKS
+        if (unlikely(is_kmmio_active()))
+                if (kmmio_handler(regs, addr) == 1)
+                        return -1;
+#endif
+        return 0;
+}
+
 static inline int notify_page_fault(struct pt_regs *regs)
 {
 #ifdef CONFIG_KPROBES
         int ret = 0;
 
         /* kprobe_running() needs smp_processor_id() */
-#ifdef CONFIG_X86_32
         if (!user_mode_vm(regs)) {
-#else
-        if (!user_mode(regs)) {
-#endif
                 preempt_disable();
                 if (kprobe_running() && kprobe_fault_handler(regs, 14))
                         ret = 1;
@@ -396,11 +403,7 @@ static void show_fault_oops(struct pt_regs *regs, unsigned long error_code,
                 printk(KERN_CONT "NULL pointer dereference");
         else
                 printk(KERN_CONT "paging request");
-#ifdef CONFIG_X86_32
-        printk(KERN_CONT " at %08lx\n", address);
-#else
-        printk(KERN_CONT " at %016lx\n", address);
-#endif
+        printk(KERN_CONT " at %p\n", (void *) address);
         printk(KERN_ALERT "IP:");
         printk_address(regs->ip, 1);
         dump_pagetable(address);
@@ -606,6 +609,8 @@ void __kprobes do_page_fault(struct pt_regs *regs, unsigned long error_code)
 
         if (notify_page_fault(regs))
                 return;
+        if (unlikely(kmmio_fault(regs, address)))
+                return;
 
         /*
          * We fault-in kernel-space virtual memory on-demand. The
@@ -800,14 +805,10 @@ bad_area_nosemaphore:
                 if (show_unhandled_signals && unhandled_signal(tsk, SIGSEGV) &&
                     printk_ratelimit()) {
                         printk(
-#ifdef CONFIG_X86_32
-                        "%s%s[%d]: segfault at %lx ip %08lx sp %08lx error %lx",
-#else
-                        "%s%s[%d]: segfault at %lx ip %lx sp %lx error %lx",
-#endif
+                        "%s%s[%d]: segfault at %lx ip %p sp %p error %lx",
                         task_pid_nr(tsk) > 1 ? KERN_INFO : KERN_EMERG,
-                        tsk->comm, task_pid_nr(tsk), address, regs->ip,
-                        regs->sp, error_code);
+                        tsk->comm, task_pid_nr(tsk), address,
+                        (void *) regs->ip, (void *) regs->sp, error_code);
                         print_vma_addr(" in ", regs->ip);
                         printk("\n");
                 }
@@ -915,14 +916,7 @@ LIST_HEAD(pgd_list);
 void vmalloc_sync_all(void)
 {
 #ifdef CONFIG_X86_32
-        /*
-         * Note that races in the updates of insync and start aren't
-         * problematic: insync can only get set bits added, and updates to
-         * start are only improving performance (without affecting correctness
-         * if undone).
-         */
-        static DECLARE_BITMAP(insync, PTRS_PER_PGD);
-        static unsigned long start = TASK_SIZE;
+        unsigned long start = VMALLOC_START & PGDIR_MASK;
         unsigned long address;
 
         if (SHARED_KERNEL_PMD)
@@ -930,56 +924,38 @@ void vmalloc_sync_all(void)
 
         BUILD_BUG_ON(TASK_SIZE & ~PGDIR_MASK);
         for (address = start; address >= TASK_SIZE; address += PGDIR_SIZE) {
-                if (!test_bit(pgd_index(address), insync)) {
-                        unsigned long flags;
-                        struct page *page;
-
-                        spin_lock_irqsave(&pgd_lock, flags);
-                        list_for_each_entry(page, &pgd_list, lru) {
-                                if (!vmalloc_sync_one(page_address(page),
-                                                      address))
-                                        break;
-                        }
-                        spin_unlock_irqrestore(&pgd_lock, flags);
-                        if (!page)
-                                set_bit(pgd_index(address), insync);
+                unsigned long flags;
+                struct page *page;
+
+                spin_lock_irqsave(&pgd_lock, flags);
+                list_for_each_entry(page, &pgd_list, lru) {
+                        if (!vmalloc_sync_one(page_address(page),
+                                              address))
+                                break;
                 }
-                if (address == start && test_bit(pgd_index(address), insync))
-                        start = address + PGDIR_SIZE;
+                spin_unlock_irqrestore(&pgd_lock, flags);
         }
 #else /* CONFIG_X86_64 */
-        /*
-         * Note that races in the updates of insync and start aren't
-         * problematic: insync can only get set bits added, and updates to
-         * start are only improving performance (without affecting correctness
-         * if undone).
-         */
-        static DECLARE_BITMAP(insync, PTRS_PER_PGD);
-        static unsigned long start = VMALLOC_START & PGDIR_MASK;
+        unsigned long start = VMALLOC_START & PGDIR_MASK;
         unsigned long address;
 
         for (address = start; address <= VMALLOC_END; address += PGDIR_SIZE) {
-                if (!test_bit(pgd_index(address), insync)) {
-                        const pgd_t *pgd_ref = pgd_offset_k(address);
-                        unsigned long flags;
-                        struct page *page;
-
-                        if (pgd_none(*pgd_ref))
-                                continue;
-                        spin_lock_irqsave(&pgd_lock, flags);
-                        list_for_each_entry(page, &pgd_list, lru) {
-                                pgd_t *pgd;
-                                pgd = (pgd_t *)page_address(page) + pgd_index(address);
-                                if (pgd_none(*pgd))
-                                        set_pgd(pgd, *pgd_ref);
-                                else
-                                        BUG_ON(pgd_page_vaddr(*pgd) != pgd_page_vaddr(*pgd_ref));
-                        }
-                        spin_unlock_irqrestore(&pgd_lock, flags);
-                        set_bit(pgd_index(address), insync);
+                const pgd_t *pgd_ref = pgd_offset_k(address);
+                unsigned long flags;
+                struct page *page;
+
+                if (pgd_none(*pgd_ref))
+                        continue;
+                spin_lock_irqsave(&pgd_lock, flags);
+                list_for_each_entry(page, &pgd_list, lru) {
+                        pgd_t *pgd;
+                        pgd = (pgd_t *)page_address(page) + pgd_index(address);
+                        if (pgd_none(*pgd))
+                                set_pgd(pgd, *pgd_ref);
+                        else
+                                BUG_ON(pgd_page_vaddr(*pgd) != pgd_page_vaddr(*pgd_ref));
                 }
-                if (address == start)
-                        start = address + PGDIR_SIZE;
+                spin_unlock_irqrestore(&pgd_lock, flags);
         }
 #endif
 }
diff --git a/arch/x86/mm/init_32.c b/arch/x86/mm/init_32.c
index ec30d10154b6..9689a5138e64 100644
--- a/arch/x86/mm/init_32.c
+++ b/arch/x86/mm/init_32.c
@@ -50,6 +50,7 @@
 
 unsigned int __VMALLOC_RESERVE = 128 << 20;
 
+unsigned long max_low_pfn_mapped;
 unsigned long max_pfn_mapped;
 
 DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
@@ -57,6 +58,27 @@ unsigned long highstart_pfn, highend_pfn;
 
 static noinline int do_test_wp_bit(void);
 
+
+static unsigned long __initdata table_start;
+static unsigned long __meminitdata table_end;
+static unsigned long __meminitdata table_top;
+
+static int __initdata after_init_bootmem;
+
+static __init void *alloc_low_page(unsigned long *phys)
+{
+        unsigned long pfn = table_end++;
+        void *adr;
+
+        if (pfn >= table_top)
+                panic("alloc_low_page: ran out of memory");
+
+        adr = __va(pfn * PAGE_SIZE);
+        memset(adr, 0, PAGE_SIZE);
+        *phys  = pfn * PAGE_SIZE;
+        return adr;
+}
+
 /*
  * Creates a middle page table and puts a pointer to it in the
  * given global directory entry. This only returns the gd entry
@@ -68,9 +90,12 @@ static pmd_t * __init one_md_table_init(pgd_t *pgd)
         pmd_t *pmd_table;
 
 #ifdef CONFIG_X86_PAE
+        unsigned long phys;
         if (!(pgd_val(*pgd) & _PAGE_PRESENT)) {
-                pmd_table = (pmd_t *) alloc_bootmem_low_pages(PAGE_SIZE);
-
+                if (after_init_bootmem)
+                        pmd_table = (pmd_t *)alloc_bootmem_low_pages(PAGE_SIZE);
+                else
+                        pmd_table = (pmd_t *)alloc_low_page(&phys);
                 paravirt_alloc_pmd(&init_mm, __pa(pmd_table) >> PAGE_SHIFT);
                 set_pgd(pgd, __pgd(__pa(pmd_table) | _PAGE_PRESENT));
                 pud = pud_offset(pgd, 0);
@@ -92,12 +117,16 @@ static pte_t * __init one_page_table_init(pmd_t *pmd)
         if (!(pmd_val(*pmd) & _PAGE_PRESENT)) {
                 pte_t *page_table = NULL;
 
+                if (after_init_bootmem) {
 #ifdef CONFIG_DEBUG_PAGEALLOC
-                page_table = (pte_t *) alloc_bootmem_pages(PAGE_SIZE);
+                        page_table = (pte_t *) alloc_bootmem_pages(PAGE_SIZE);
 #endif
-                if (!page_table) {
-                        page_table =
+                        if (!page_table)
+                                page_table =
                                 (pte_t *)alloc_bootmem_low_pages(PAGE_SIZE);
+                } else {
+                        unsigned long phys;
+                        page_table = (pte_t *)alloc_low_page(&phys);
                 }
 
                 paravirt_alloc_pte(&init_mm, __pa(page_table) >> PAGE_SHIFT);
@@ -155,38 +184,44 @@ static inline int is_kernel_text(unsigned long addr)
  * of max_low_pfn pages, by creating page tables starting from address
  * PAGE_OFFSET:
  */
-static void __init kernel_physical_mapping_init(pgd_t *pgd_base)
+static void __init kernel_physical_mapping_init(pgd_t *pgd_base,
+                                                unsigned long start_pfn,
+                                                unsigned long end_pfn,
+                                                int use_pse)
 {
         int pgd_idx, pmd_idx, pte_ofs;
         unsigned long pfn;
         pgd_t *pgd;
         pmd_t *pmd;
         pte_t *pte;
+        unsigned pages_2m = 0, pages_4k = 0;
 
-        pgd_idx = pgd_index(PAGE_OFFSET);
-        pgd = pgd_base + pgd_idx;
-        pfn = 0;
+        if (!cpu_has_pse)
+                use_pse = 0;
 
+        pfn = start_pfn;
+        pgd_idx = pgd_index((pfn<<PAGE_SHIFT) + PAGE_OFFSET);
+        pgd = pgd_base + pgd_idx;
         for (; pgd_idx < PTRS_PER_PGD; pgd++, pgd_idx++) {
                 pmd = one_md_table_init(pgd);
-                if (pfn >= max_low_pfn)
-                        continue;
 
-                for (pmd_idx = 0;
-                     pmd_idx < PTRS_PER_PMD && pfn < max_low_pfn;
+                if (pfn >= end_pfn)
+                        continue;
+#ifdef CONFIG_X86_PAE
+                pmd_idx = pmd_index((pfn<<PAGE_SHIFT) + PAGE_OFFSET);
+                pmd += pmd_idx;
+#else
+                pmd_idx = 0;
+#endif
+                for (; pmd_idx < PTRS_PER_PMD && pfn < end_pfn;
                      pmd++, pmd_idx++) {
                         unsigned int addr = pfn * PAGE_SIZE + PAGE_OFFSET;
 
                         /*
                          * Map with big pages if possible, otherwise
                          * create normal page tables:
-                         *
-                         * Don't use a large page for the first 2/4MB of memory
-                         * because there are often fixed size MTRRs in there
-                         * and overlapping MTRRs into large pages can cause
-                         * slowdowns.
                          */
-                        if (cpu_has_pse && !(pgd_idx == 0 && pmd_idx == 0)) {
+                        if (use_pse) {
                                 unsigned int addr2;
                                 pgprot_t prot = PAGE_KERNEL_LARGE;
 
@@ -197,34 +232,30 @@ static void __init kernel_physical_mapping_init(pgd_t *pgd_base)
                                     is_kernel_text(addr2))
                                         prot = PAGE_KERNEL_LARGE_EXEC;
 
+                                pages_2m++;
                                 set_pmd(pmd, pfn_pmd(pfn, prot));
 
                                 pfn += PTRS_PER_PTE;
-                                max_pfn_mapped = pfn;
                                 continue;
                         }
                         pte = one_page_table_init(pmd);
 
-                        for (pte_ofs = 0;
-                             pte_ofs < PTRS_PER_PTE && pfn < max_low_pfn;
+                        pte_ofs = pte_index((pfn<<PAGE_SHIFT) + PAGE_OFFSET);
+                        pte += pte_ofs;
+                        for (; pte_ofs < PTRS_PER_PTE && pfn < end_pfn;
                              pte++, pfn++, pte_ofs++, addr += PAGE_SIZE) {
                                 pgprot_t prot = PAGE_KERNEL;
 
                                 if (is_kernel_text(addr))
                                         prot = PAGE_KERNEL_EXEC;
 
+                                pages_4k++;
                                 set_pte(pte, pfn_pte(pfn, prot));
                         }
-                        max_pfn_mapped = pfn;
                 }
         }
-}
-
-static inline int page_kills_ppro(unsigned long pagenr)
-{
-        if (pagenr >= 0x70000 && pagenr <= 0x7003F)
-                return 1;
-        return 0;
+        update_page_count(PG_LEVEL_2M, pages_2m);
+        update_page_count(PG_LEVEL_4K, pages_4k);
 }
 
 /*
@@ -287,29 +318,62 @@ static void __init permanent_kmaps_init(pgd_t *pgd_base)
         pkmap_page_table = pte;
 }
 
-void __init add_one_highpage_init(struct page *page, int pfn, int bad_ppro)
+static void __init add_one_highpage_init(struct page *page, int pfn)
 {
-        if (page_is_ram(pfn) && !(bad_ppro && page_kills_ppro(pfn))) {
-                ClearPageReserved(page);
-                init_page_count(page);
-                __free_page(page);
-                totalhigh_pages++;
-        } else
-                SetPageReserved(page);
+        ClearPageReserved(page);
+        init_page_count(page);
+        __free_page(page);
+        totalhigh_pages++;
 }
 
-#ifndef CONFIG_NUMA
-static void __init set_highmem_pages_init(int bad_ppro)
+struct add_highpages_data {
+        unsigned long start_pfn;
+        unsigned long end_pfn;
+};
+
+static int __init add_highpages_work_fn(unsigned long start_pfn,
+                                         unsigned long end_pfn, void *datax)
 {
-        int pfn;
+        int node_pfn;
+        struct page *page;
+        unsigned long final_start_pfn, final_end_pfn;
+        struct add_highpages_data *data;
 
-        for (pfn = highstart_pfn; pfn < highend_pfn; pfn++) {
-                /*
-                 * Holes under sparsemem might not have no mem_map[]:
-                 */
-                if (pfn_valid(pfn))
-                        add_one_highpage_init(pfn_to_page(pfn), pfn, bad_ppro);
+        data = (struct add_highpages_data *)datax;
+
+        final_start_pfn = max(start_pfn, data->start_pfn);
+        final_end_pfn = min(end_pfn, data->end_pfn);
+        if (final_start_pfn >= final_end_pfn)
+                return 0;
+
+        for (node_pfn = final_start_pfn; node_pfn < final_end_pfn;
+             node_pfn++) {
+                if (!pfn_valid(node_pfn))
+                        continue;
+                page = pfn_to_page(node_pfn);
+                add_one_highpage_init(page, node_pfn);
         }
+
+        return 0;
+
+}
+
+void __init add_highpages_with_active_regions(int nid, unsigned long start_pfn,
+                                              unsigned long end_pfn)
+{
+        struct add_highpages_data data;
+
+        data.start_pfn = start_pfn;
+        data.end_pfn = end_pfn;
+
+        work_with_active_regions(nid, add_highpages_work_fn, &data);
+}
+
+#ifndef CONFIG_NUMA
+static void __init set_highmem_pages_init(void)
+{
+        add_highpages_with_active_regions(0, highstart_pfn, highend_pfn);
+
         totalram_pages += totalhigh_pages;
 }
 #endif /* !CONFIG_NUMA */
@@ -317,14 +381,9 @@ static void __init set_highmem_pages_init(int bad_ppro)
 #else
 # define kmap_init()                            do { } while (0)
 # define permanent_kmaps_init(pgd_base)         do { } while (0)
-# define set_highmem_pages_init(bad_ppro)       do { } while (0)
+# define set_highmem_pages_init()       do { } while (0)
 #endif /* CONFIG_HIGHMEM */
 
-pteval_t __PAGE_KERNEL = _PAGE_KERNEL;
-EXPORT_SYMBOL(__PAGE_KERNEL);
-
-pteval_t __PAGE_KERNEL_EXEC = _PAGE_KERNEL_EXEC;
-
 void __init native_pagetable_setup_start(pgd_t *base)
 {
         unsigned long pfn, va;
@@ -380,27 +439,10 @@ void __init native_pagetable_setup_done(pgd_t *base)
  * be partially populated, and so it avoids stomping on any existing
  * mappings.
  */
-static void __init pagetable_init(void)
+static void __init early_ioremap_page_table_range_init(pgd_t *pgd_base)
 {
-        pgd_t *pgd_base = swapper_pg_dir;
         unsigned long vaddr, end;
 
-        paravirt_pagetable_setup_start(pgd_base);
-
-        /* Enable PSE if available */
-        if (cpu_has_pse)
-                set_in_cr4(X86_CR4_PSE);
-
-        /* Enable PGE if available */
-        if (cpu_has_pge) {
-                set_in_cr4(X86_CR4_PGE);
-                __PAGE_KERNEL |= _PAGE_GLOBAL;
-                __PAGE_KERNEL_EXEC |= _PAGE_GLOBAL;
-        }
-
-        kernel_physical_mapping_init(pgd_base);
-        remap_numa_kva();
-
         /*
          * Fixed mappings, only the page table structure has to be
          * created - mappings will be set by set_fixmap():
@@ -410,6 +452,13 @@ static void __init pagetable_init(void)
         end = (FIXADDR_TOP + PMD_SIZE - 1) & PMD_MASK;
         page_table_range_init(vaddr, end, pgd_base);
         early_ioremap_reset();
+}
+
+static void __init pagetable_init(void)
+{
+        pgd_t *pgd_base = swapper_pg_dir;
+
+        paravirt_pagetable_setup_start(pgd_base);
 
         permanent_kmaps_init(pgd_base);
 
@@ -456,7 +505,7 @@ void zap_low_mappings(void)
 
 int nx_enabled;
 
-pteval_t __supported_pte_mask __read_mostly = ~_PAGE_NX;
+pteval_t __supported_pte_mask __read_mostly = ~(_PAGE_NX | _PAGE_GLOBAL);
 EXPORT_SYMBOL_GPL(__supported_pte_mask);
 
 #ifdef CONFIG_X86_PAE
@@ -509,27 +558,318 @@ static void __init set_nx(void)
 }
 #endif
 
+/* user-defined highmem size */
+static unsigned int highmem_pages = -1;
+
 /*
- * paging_init() sets up the page tables - note that the first 8MB are
- * already mapped by head.S.
- *
- * This routines also unmaps the page at virtual kernel address 0, so
- * that we can trap those pesky NULL-reference errors in the kernel.
+ * highmem=size forces highmem to be exactly 'size' bytes.
+ * This works even on boxes that have no highmem otherwise.
+ * This also works to reduce highmem size on bigger boxes.
  */
-void __init paging_init(void)
+static int __init parse_highmem(char *arg)
+{
+        if (!arg)
+                return -EINVAL;
+
+        highmem_pages = memparse(arg, &arg) >> PAGE_SHIFT;
+        return 0;
+}
+early_param("highmem", parse_highmem);
+
+/*
+ * Determine low and high memory ranges:
+ */
+void __init find_low_pfn_range(void)
+{
+        /* it could update max_pfn */
+
+        /* max_low_pfn is 0, we already have early_res support */
+
+        max_low_pfn = max_pfn;
+        if (max_low_pfn > MAXMEM_PFN) {
+                if (highmem_pages == -1)
+                        highmem_pages = max_pfn - MAXMEM_PFN;
+                if (highmem_pages + MAXMEM_PFN < max_pfn)
+                        max_pfn = MAXMEM_PFN + highmem_pages;
+                if (highmem_pages + MAXMEM_PFN > max_pfn) {
+                        printk(KERN_WARNING "only %luMB highmem pages "
+                                "available, ignoring highmem size of %uMB.\n",
+                                pages_to_mb(max_pfn - MAXMEM_PFN),
+                                pages_to_mb(highmem_pages));
+                        highmem_pages = 0;
+                }
+                max_low_pfn = MAXMEM_PFN;
+#ifndef CONFIG_HIGHMEM
+                /* Maximum memory usable is what is directly addressable */
+                printk(KERN_WARNING "Warning only %ldMB will be used.\n",
+                                        MAXMEM>>20);
+                if (max_pfn > MAX_NONPAE_PFN)
+                        printk(KERN_WARNING
+                                 "Use a HIGHMEM64G enabled kernel.\n");
+                else
+                        printk(KERN_WARNING "Use a HIGHMEM enabled kernel.\n");
+                max_pfn = MAXMEM_PFN;
+#else /* !CONFIG_HIGHMEM */
+#ifndef CONFIG_HIGHMEM64G
+                if (max_pfn > MAX_NONPAE_PFN) {
+                        max_pfn = MAX_NONPAE_PFN;
+                        printk(KERN_WARNING "Warning only 4GB will be used."
+                                "Use a HIGHMEM64G enabled kernel.\n");
+                }
+#endif /* !CONFIG_HIGHMEM64G */
+#endif /* !CONFIG_HIGHMEM */
+        } else {
+                if (highmem_pages == -1)
+                        highmem_pages = 0;
+#ifdef CONFIG_HIGHMEM
+                if (highmem_pages >= max_pfn) {
+                        printk(KERN_ERR "highmem size specified (%uMB) is "
+                                "bigger than pages available (%luMB)!.\n",
+                                pages_to_mb(highmem_pages),
+                                pages_to_mb(max_pfn));
+                        highmem_pages = 0;
+                }
+                if (highmem_pages) {
+                        if (max_low_pfn - highmem_pages <
+                            64*1024*1024/PAGE_SIZE){
+                                printk(KERN_ERR "highmem size %uMB results in "
+                                "smaller than 64MB lowmem, ignoring it.\n"
+                                        , pages_to_mb(highmem_pages));
+                                highmem_pages = 0;
+                        }
+                        max_low_pfn -= highmem_pages;
+                }
+#else
+                if (highmem_pages)
+                        printk(KERN_ERR "ignoring highmem size on non-highmem"
+                                        " kernel!\n");
+#endif
+        }
+}
+
+#ifndef CONFIG_NEED_MULTIPLE_NODES
+void __init initmem_init(unsigned long start_pfn,
+                                  unsigned long end_pfn)
 {
+#ifdef CONFIG_HIGHMEM
+        highstart_pfn = highend_pfn = max_pfn;
+        if (max_pfn > max_low_pfn)
+                highstart_pfn = max_low_pfn;
+        memory_present(0, 0, highend_pfn);
+        e820_register_active_regions(0, 0, highend_pfn);
+        printk(KERN_NOTICE "%ldMB HIGHMEM available.\n",
+                pages_to_mb(highend_pfn - highstart_pfn));
+        num_physpages = highend_pfn;
+        high_memory = (void *) __va(highstart_pfn * PAGE_SIZE - 1) + 1;
+#else
+        memory_present(0, 0, max_low_pfn);
+        e820_register_active_regions(0, 0, max_low_pfn);
+        num_physpages = max_low_pfn;
+        high_memory = (void *) __va(max_low_pfn * PAGE_SIZE - 1) + 1;
+#endif
+#ifdef CONFIG_FLATMEM
+        max_mapnr = num_physpages;
+#endif
+        printk(KERN_NOTICE "%ldMB LOWMEM available.\n",
+                        pages_to_mb(max_low_pfn));
+
+        setup_bootmem_allocator();
+}
+#endif /* !CONFIG_NEED_MULTIPLE_NODES */
+
+static void __init zone_sizes_init(void)
+{
+        unsigned long max_zone_pfns[MAX_NR_ZONES];
+        memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
+        max_zone_pfns[ZONE_DMA] =
+                virt_to_phys((char *)MAX_DMA_ADDRESS) >> PAGE_SHIFT;
+        max_zone_pfns[ZONE_NORMAL] = max_low_pfn;
+#ifdef CONFIG_HIGHMEM
+        max_zone_pfns[ZONE_HIGHMEM] = highend_pfn;
+#endif
+
+        free_area_init_nodes(max_zone_pfns);
+}
+
+void __init setup_bootmem_allocator(void)
+{
+        int i;
+        unsigned long bootmap_size, bootmap;
+        /*
+         * Initialize the boot-time allocator (with low memory only):
+         */
+        bootmap_size = bootmem_bootmap_pages(max_low_pfn)<<PAGE_SHIFT;
+        bootmap = find_e820_area(min_low_pfn<<PAGE_SHIFT,
+                                 max_pfn_mapped<<PAGE_SHIFT, bootmap_size,
+                                 PAGE_SIZE);
+        if (bootmap == -1L)
+                panic("Cannot find bootmem map of size %ld\n", bootmap_size);
+        reserve_early(bootmap, bootmap + bootmap_size, "BOOTMAP");
+
+        /* don't touch min_low_pfn */
+        bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap >> PAGE_SHIFT,
+                                         min_low_pfn, max_low_pfn);
+        printk(KERN_INFO "  mapped low ram: 0 - %08lx\n",
+                 max_pfn_mapped<<PAGE_SHIFT);
+        printk(KERN_INFO "  low ram: %08lx - %08lx\n",
+                 min_low_pfn<<PAGE_SHIFT, max_low_pfn<<PAGE_SHIFT);
+        printk(KERN_INFO "  bootmap %08lx - %08lx\n",
+                 bootmap, bootmap + bootmap_size);
+        for_each_online_node(i)
+                free_bootmem_with_active_regions(i, max_low_pfn);
+        early_res_to_bootmem(0, max_low_pfn<<PAGE_SHIFT);
+
+        after_init_bootmem = 1;
+}
+
+static void __init find_early_table_space(unsigned long end)
+{
+        unsigned long puds, pmds, ptes, tables, start;
+
+        puds = (end + PUD_SIZE - 1) >> PUD_SHIFT;
+        tables = PAGE_ALIGN(puds * sizeof(pud_t));
+
+        pmds = (end + PMD_SIZE - 1) >> PMD_SHIFT;
+        tables += PAGE_ALIGN(pmds * sizeof(pmd_t));
+
+        if (cpu_has_pse) {
+                unsigned long extra;
+
+                extra = end - ((end>>PMD_SHIFT) << PMD_SHIFT);
+                extra += PMD_SIZE;
+                ptes = (extra + PAGE_SIZE - 1) >> PAGE_SHIFT;
+        } else
+                ptes = (end + PAGE_SIZE - 1) >> PAGE_SHIFT;
+
+        tables += PAGE_ALIGN(ptes * sizeof(pte_t));
+
+        /* for fixmap */
+        tables += PAGE_SIZE * 2;
+
+        /*
+         * RED-PEN putting page tables only on node 0 could
+         * cause a hotspot and fill up ZONE_DMA. The page tables
+         * need roughly 0.5KB per GB.
+         */
+        start = 0x7000;
+        table_start = find_e820_area(start, max_pfn_mapped<<PAGE_SHIFT,
+                                        tables, PAGE_SIZE);
+        if (table_start == -1UL)
+                panic("Cannot find space for the kernel page tables");
+
+        table_start >>= PAGE_SHIFT;
+        table_end = table_start;
+        table_top = table_start + (tables>>PAGE_SHIFT);
+
+        printk(KERN_DEBUG "kernel direct mapping tables up to %lx @ %lx-%lx\n",
+                end, table_start << PAGE_SHIFT,
+                (table_start << PAGE_SHIFT) + tables);
+}
+
+unsigned long __init_refok init_memory_mapping(unsigned long start,
+                                                unsigned long end)
+{
+        pgd_t *pgd_base = swapper_pg_dir;
+        unsigned long start_pfn, end_pfn;
+        unsigned long big_page_start;
+
+        /*
+         * Find space for the kernel direct mapping tables.
+         */
+        if (!after_init_bootmem)
+                find_early_table_space(end);
+
 #ifdef CONFIG_X86_PAE
         set_nx();
         if (nx_enabled)
                 printk(KERN_INFO "NX (Execute Disable) protection: active\n");
 #endif
-        pagetable_init();
+
+        /* Enable PSE if available */
+        if (cpu_has_pse)
+                set_in_cr4(X86_CR4_PSE);
+
+        /* Enable PGE if available */
+        if (cpu_has_pge) {
+                set_in_cr4(X86_CR4_PGE);
+                __supported_pte_mask |= _PAGE_GLOBAL;
+        }
+
+        /*
+         * Don't use a large page for the first 2/4MB of memory
+         * because there are often fixed size MTRRs in there
+         * and overlapping MTRRs into large pages can cause
+         * slowdowns.
+         */
+        big_page_start = PMD_SIZE;
+
+        if (start < big_page_start) {
+                start_pfn = start >> PAGE_SHIFT;
+                end_pfn = min(big_page_start>>PAGE_SHIFT, end>>PAGE_SHIFT);
+        } else {
+                /* head is not big page alignment ? */
+                start_pfn = start >> PAGE_SHIFT;
+                end_pfn = ((start + (PMD_SIZE - 1))>>PMD_SHIFT)
+                                 << (PMD_SHIFT - PAGE_SHIFT);
+        }
+        if (start_pfn < end_pfn)
+                kernel_physical_mapping_init(pgd_base, start_pfn, end_pfn, 0);
+
+        /* big page range */
+        start_pfn = ((start + (PMD_SIZE - 1))>>PMD_SHIFT)
+                         << (PMD_SHIFT - PAGE_SHIFT);
+        if (start_pfn < (big_page_start >> PAGE_SHIFT))
+                start_pfn =  big_page_start >> PAGE_SHIFT;
+        end_pfn = (end>>PMD_SHIFT) << (PMD_SHIFT - PAGE_SHIFT);
+        if (start_pfn < end_pfn)
+                kernel_physical_mapping_init(pgd_base, start_pfn, end_pfn,
+                                                cpu_has_pse);
+
+        /* tail is not big page alignment ? */
+        start_pfn = end_pfn;
+        if (start_pfn > (big_page_start>>PAGE_SHIFT)) {
+                end_pfn = end >> PAGE_SHIFT;
+                if (start_pfn < end_pfn)
+                        kernel_physical_mapping_init(pgd_base, start_pfn,
+                                                         end_pfn, 0);
+        }
+
+        early_ioremap_page_table_range_init(pgd_base);
 
         load_cr3(swapper_pg_dir);
 
         __flush_tlb_all();
 
+        if (!after_init_bootmem)
+                reserve_early(table_start << PAGE_SHIFT,
+                                 table_end << PAGE_SHIFT, "PGTABLE");
+
+        return end >> PAGE_SHIFT;
+}
+
+
+/*
+ * paging_init() sets up the page tables - note that the first 8MB are
+ * already mapped by head.S.
+ *
+ * This routines also unmaps the page at virtual kernel address 0, so
+ * that we can trap those pesky NULL-reference errors in the kernel.
+ */
+void __init paging_init(void)
+{
+        pagetable_init();
+
+        __flush_tlb_all();
+
         kmap_init();
+
+        /*
+         * NOTE: at this point the bootmem allocator is fully available.
+         */
+        sparse_init();
+        zone_sizes_init();
+
+        paravirt_post_allocator_init();
 }
 
 /*
@@ -564,24 +904,11 @@ static struct kcore_list kcore_mem, kcore_vmalloc;
 void __init mem_init(void)
 {
         int codesize, reservedpages, datasize, initsize;
-        int tmp, bad_ppro;
+        int tmp;
 
 #ifdef CONFIG_FLATMEM
         BUG_ON(!mem_map);
 #endif
-        bad_ppro = ppro_with_ram_bug();
-
-#ifdef CONFIG_HIGHMEM
-        /* check that fixmap and pkmap do not overlap */
-        if (PKMAP_BASE + LAST_PKMAP*PAGE_SIZE >= FIXADDR_START) {
-                printk(KERN_ERR
-                        "fixmap and kmap areas overlap - this will crash\n");
-                printk(KERN_ERR "pkstart: %lxh pkend: %lxh fixstart %lxh\n",
-                                PKMAP_BASE, PKMAP_BASE + LAST_PKMAP*PAGE_SIZE,
-                                FIXADDR_START);
-                BUG();
-        }
-#endif
         /* this will put all low memory onto the freelists */
         totalram_pages += free_all_bootmem();
 
@@ -593,7 +920,7 @@ void __init mem_init(void)
                 if (page_is_ram(tmp) && PageReserved(pfn_to_page(tmp)))
                         reservedpages++;
 
-        set_highmem_pages_init(bad_ppro);
+        set_highmem_pages_init();
 
         codesize =  (unsigned long) &_etext - (unsigned long) &_text;
         datasize =  (unsigned long) &_edata - (unsigned long) &_etext;
@@ -614,7 +941,6 @@ void __init mem_init(void)
                 (unsigned long) (totalhigh_pages << (PAGE_SHIFT-10))
                );
 
-#if 1 /* double-sanity-check paranoia */
         printk(KERN_INFO "virtual kernel memory layout:\n"
                 "    fixmap  : 0x%08lx - 0x%08lx   (%4ld kB)\n"
 #ifdef CONFIG_HIGHMEM
@@ -655,7 +981,6 @@ void __init mem_init(void)
 #endif
         BUG_ON(VMALLOC_START                            > VMALLOC_END);
         BUG_ON((unsigned long)high_memory               > VMALLOC_START);
-#endif /* double-sanity-check paranoia */
 
         if (boot_cpu_data.wp_works_ok < 0)
                 test_wp_bit();
@@ -710,6 +1035,8 @@ void mark_rodata_ro(void)
         unsigned long start = PFN_ALIGN(_text);
         unsigned long size = PFN_ALIGN(_etext) - start;
 
+#ifndef CONFIG_DYNAMIC_FTRACE
+        /* Dynamic tracing modifies the kernel text section */
         set_pages_ro(virt_to_page(start), size >> PAGE_SHIFT);
         printk(KERN_INFO "Write protecting the kernel text: %luk\n",
                 size >> 10);
@@ -722,6 +1049,8 @@ void mark_rodata_ro(void)
         printk(KERN_INFO "Testing CPA: write protecting again\n");
         set_pages_ro(virt_to_page(start), size>>PAGE_SHIFT);
 #endif
+#endif /* CONFIG_DYNAMIC_FTRACE */
+
         start += size;
         size = (unsigned long)__end_rodata - start;
         set_pages_ro(virt_to_page(start), size >> PAGE_SHIFT);
@@ -784,3 +1113,9 @@ void free_initrd_mem(unsigned long start, unsigned long end)
         free_init_pages("initrd memory", start, end);
 }
 #endif
+
+int __init reserve_bootmem_generic(unsigned long phys, unsigned long len,
+                                   int flags)
+{
+        return reserve_bootmem(phys, len, flags);
+}
diff --git a/arch/x86/mm/init_64.c b/arch/x86/mm/init_64.c
index 819dad973b13..27de2435e008 100644
--- a/arch/x86/mm/init_64.c
+++ b/arch/x86/mm/init_64.c
@@ -18,6 +18,7 @@
 #include <linux/swap.h>
 #include <linux/smp.h>
 #include <linux/init.h>
+#include <linux/initrd.h>
 #include <linux/pagemap.h>
 #include <linux/bootmem.h>
 #include <linux/proc_fs.h>
@@ -47,6 +48,14 @@
 #include <asm/numa.h>
 #include <asm/cacheflush.h>
 
+/*
+ * end_pfn only includes RAM, while max_pfn_mapped includes all e820 entries.
+ * The direct mapping extends to max_pfn_mapped, so that we can directly access
+ * apertures, ACPI and other tables without having to play with fixmaps.
+ */
+unsigned long max_low_pfn_mapped;
+unsigned long max_pfn_mapped;
+
 static unsigned long dma_reserve __initdata;
 
 DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
@@ -135,26 +144,17 @@ static __init void *spp_getpage(void)
         return ptr;
 }
 
-static __init void
-set_pte_phys(unsigned long vaddr, unsigned long phys, pgprot_t prot)
+void
+set_pte_vaddr_pud(pud_t *pud_page, unsigned long vaddr, pte_t new_pte)
 {
-        pgd_t *pgd;
         pud_t *pud;
         pmd_t *pmd;
-        pte_t *pte, new_pte;
-
-        pr_debug("set_pte_phys %lx to %lx\n", vaddr, phys);
+        pte_t *pte;
 
-        pgd = pgd_offset_k(vaddr);
-        if (pgd_none(*pgd)) {
-                printk(KERN_ERR
-                        "PGD FIXMAP MISSING, it should be setup in head.S!\n");
-                return;
-        }
-        pud = pud_offset(pgd, vaddr);
+        pud = pud_page + pud_index(vaddr);
         if (pud_none(*pud)) {
                 pmd = (pmd_t *) spp_getpage();
-                set_pud(pud, __pud(__pa(pmd) | _KERNPG_TABLE | _PAGE_USER));
+                pud_populate(&init_mm, pud, pmd);
                 if (pmd != pmd_offset(pud, 0)) {
                         printk(KERN_ERR "PAGETABLE BUG #01! %p <-> %p\n",
                                 pmd, pmd_offset(pud, 0));
@@ -164,13 +164,12 @@ set_pte_phys(unsigned long vaddr, unsigned long phys, pgprot_t prot)
         pmd = pmd_offset(pud, vaddr);
         if (pmd_none(*pmd)) {
                 pte = (pte_t *) spp_getpage();
-                set_pmd(pmd, __pmd(__pa(pte) | _KERNPG_TABLE | _PAGE_USER));
+                pmd_populate_kernel(&init_mm, pmd, pte);
                 if (pte != pte_offset_kernel(pmd, 0)) {
                         printk(KERN_ERR "PAGETABLE BUG #02!\n");
                         return;
                 }
         }
-        new_pte = pfn_pte(phys >> PAGE_SHIFT, prot);
 
         pte = pte_offset_kernel(pmd, vaddr);
         if (!pte_none(*pte) && pte_val(new_pte) &&
@@ -185,6 +184,64 @@ set_pte_phys(unsigned long vaddr, unsigned long phys, pgprot_t prot)
         __flush_tlb_one(vaddr);
 }
 
+void
+set_pte_vaddr(unsigned long vaddr, pte_t pteval)
+{
+        pgd_t *pgd;
+        pud_t *pud_page;
+
+        pr_debug("set_pte_vaddr %lx to %lx\n", vaddr, native_pte_val(pteval));
+
+        pgd = pgd_offset_k(vaddr);
+        if (pgd_none(*pgd)) {
+                printk(KERN_ERR
+                        "PGD FIXMAP MISSING, it should be setup in head.S!\n");
+                return;
+        }
+        pud_page = (pud_t*)pgd_page_vaddr(*pgd);
+        set_pte_vaddr_pud(pud_page, vaddr, pteval);
+}
+
+/*
+ * Create large page table mappings for a range of physical addresses.
+ */
+static void __init __init_extra_mapping(unsigned long phys, unsigned long size,
+                                                pgprot_t prot)
+{
+        pgd_t *pgd;
+        pud_t *pud;
+        pmd_t *pmd;
+
+        BUG_ON((phys & ~PMD_MASK) || (size & ~PMD_MASK));
+        for (; size; phys += PMD_SIZE, size -= PMD_SIZE) {
+                pgd = pgd_offset_k((unsigned long)__va(phys));
+                if (pgd_none(*pgd)) {
+                        pud = (pud_t *) spp_getpage();
+                        set_pgd(pgd, __pgd(__pa(pud) | _KERNPG_TABLE |
+                                                _PAGE_USER));
+                }
+                pud = pud_offset(pgd, (unsigned long)__va(phys));
+                if (pud_none(*pud)) {
+                        pmd = (pmd_t *) spp_getpage();
+                        set_pud(pud, __pud(__pa(pmd) | _KERNPG_TABLE |
+                                                _PAGE_USER));
+                }
+                pmd = pmd_offset(pud, phys);
+                BUG_ON(!pmd_none(*pmd));
+                set_pmd(pmd, __pmd(phys | pgprot_val(prot)));
+        }
+}
+
+void __init init_extra_mapping_wb(unsigned long phys, unsigned long size)
+{
+        __init_extra_mapping(phys, size, PAGE_KERNEL_LARGE);
+}
+
+void __init init_extra_mapping_uc(unsigned long phys, unsigned long size)
+{
+        __init_extra_mapping(phys, size, PAGE_KERNEL_LARGE_NOCACHE);
+}
+
 /*
  * The head.S code sets up the kernel high mapping:
  *
@@ -213,20 +270,9 @@ void __init cleanup_highmap(void)
         }
 }
 
-/* NOTE: this is meant to be run only at boot */
-void __init __set_fixmap(enum fixed_addresses idx, unsigned long phys, pgprot_t prot)
-{
-        unsigned long address = __fix_to_virt(idx);
-
-        if (idx >= __end_of_fixed_addresses) {
-                printk(KERN_ERR "Invalid __set_fixmap\n");
-                return;
-        }
-        set_pte_phys(address, phys, prot);
-}
-
 static unsigned long __initdata table_start;
 static unsigned long __meminitdata table_end;
+static unsigned long __meminitdata table_top;
 
 static __meminit void *alloc_low_page(unsigned long *phys)
 {
@@ -240,7 +286,7 @@ static __meminit void *alloc_low_page(unsigned long *phys)
                 return adr;
         }
 
-        if (pfn >= end_pfn)
+        if (pfn >= table_top)
                 panic("alloc_low_page: ran out of memory");
 
         adr = early_ioremap(pfn * PAGE_SIZE, PAGE_SIZE);
@@ -257,65 +303,61 @@ static __meminit void unmap_low_page(void *adr)
         early_iounmap(adr, PAGE_SIZE);
 }
 
-/* Must run before zap_low_mappings */
-__meminit void *early_ioremap(unsigned long addr, unsigned long size)
+static unsigned long __meminit
+phys_pte_init(pte_t *pte_page, unsigned long addr, unsigned long end)
 {
-        pmd_t *pmd, *last_pmd;
-        unsigned long vaddr;
-        int i, pmds;
+        unsigned pages = 0;
+        unsigned long last_map_addr = end;
+        int i;
+
+        pte_t *pte = pte_page + pte_index(addr);
 
-        pmds = ((addr & ~PMD_MASK) + size + ~PMD_MASK) / PMD_SIZE;
-        vaddr = __START_KERNEL_map;
-        pmd = level2_kernel_pgt;
-        last_pmd = level2_kernel_pgt + PTRS_PER_PMD - 1;
+        for(i = pte_index(addr); i < PTRS_PER_PTE; i++, addr += PAGE_SIZE, pte++) {
 
-        for (; pmd <= last_pmd; pmd++, vaddr += PMD_SIZE) {
-                for (i = 0; i < pmds; i++) {
-                        if (pmd_present(pmd[i]))
-                                goto continue_outer_loop;
+                if (addr >= end) {
+                        if (!after_bootmem) {
+                                for(; i < PTRS_PER_PTE; i++, pte++)
+                                        set_pte(pte, __pte(0));
+                        }
+                        break;
                 }
-                vaddr += addr & ~PMD_MASK;
-                addr &= PMD_MASK;
 
-                for (i = 0; i < pmds; i++, addr += PMD_SIZE)
-                        set_pmd(pmd+i, __pmd(addr | __PAGE_KERNEL_LARGE_EXEC));
-                __flush_tlb_all();
+                if (pte_val(*pte))
+                        continue;
 
-                return (void *)vaddr;
-continue_outer_loop:
-                ;
+                if (0)
+                        printk("   pte=%p addr=%lx pte=%016lx\n",
+                               pte, addr, pfn_pte(addr >> PAGE_SHIFT, PAGE_KERNEL).pte);
+                set_pte(pte, pfn_pte(addr >> PAGE_SHIFT, PAGE_KERNEL));
+                last_map_addr = (addr & PAGE_MASK) + PAGE_SIZE;
+                pages++;
         }
-        printk(KERN_ERR "early_ioremap(0x%lx, %lu) failed\n", addr, size);
+        update_page_count(PG_LEVEL_4K, pages);
 
-        return NULL;
+        return last_map_addr;
 }
 
-/*
- * To avoid virtual aliases later:
- */
-__meminit void early_iounmap(void *addr, unsigned long size)
+static unsigned long __meminit
+phys_pte_update(pmd_t *pmd, unsigned long address, unsigned long end)
 {
-        unsigned long vaddr;
-        pmd_t *pmd;
-        int i, pmds;
-
-        vaddr = (unsigned long)addr;
-        pmds = ((vaddr & ~PMD_MASK) + size + ~PMD_MASK) / PMD_SIZE;
-        pmd = level2_kernel_pgt + pmd_index(vaddr);
-
-        for (i = 0; i < pmds; i++)
-                pmd_clear(pmd + i);
+        pte_t *pte = (pte_t *)pmd_page_vaddr(*pmd);
 
-        __flush_tlb_all();
+        return phys_pte_init(pte, address, end);
 }
 
 static unsigned long __meminit
-phys_pmd_init(pmd_t *pmd_page, unsigned long address, unsigned long end)
+phys_pmd_init(pmd_t *pmd_page, unsigned long address, unsigned long end,
+                         unsigned long page_size_mask)
 {
+        unsigned long pages = 0;
+        unsigned long last_map_addr = end;
+
         int i = pmd_index(address);
 
         for (; i < PTRS_PER_PMD; i++, address += PMD_SIZE) {
+                unsigned long pte_phys;
                 pmd_t *pmd = pmd_page + pmd_index(address);
+                pte_t *pte;
 
                 if (address >= end) {
                         if (!after_bootmem) {
@@ -325,31 +367,50 @@ phys_pmd_init(pmd_t *pmd_page, unsigned long address, unsigned long end)
                         break;
                 }
 
-                if (pmd_val(*pmd))
+                if (pmd_val(*pmd)) {
+                        if (!pmd_large(*pmd))
+                                last_map_addr = phys_pte_update(pmd, address,
+                                                                 end);
+                        continue;
+                }
+
+                if (page_size_mask & (1<<PG_LEVEL_2M)) {
+                        pages++;
+                        set_pte((pte_t *)pmd,
+                                pfn_pte(address >> PAGE_SHIFT, PAGE_KERNEL_LARGE));
+                        last_map_addr = (address & PMD_MASK) + PMD_SIZE;
                         continue;
+                }
+
+                pte = alloc_low_page(&pte_phys);
+                last_map_addr = phys_pte_init(pte, address, end);
+                unmap_low_page(pte);
 
-                set_pte((pte_t *)pmd,
-                        pfn_pte(address >> PAGE_SHIFT, PAGE_KERNEL_LARGE));
+                pmd_populate_kernel(&init_mm, pmd, __va(pte_phys));
         }
-        return address;
+        update_page_count(PG_LEVEL_2M, pages);
+        return last_map_addr;
 }
 
 static unsigned long __meminit
-phys_pmd_update(pud_t *pud, unsigned long address, unsigned long end)
+phys_pmd_update(pud_t *pud, unsigned long address, unsigned long end,
+                         unsigned long page_size_mask)
 {
         pmd_t *pmd = pmd_offset(pud, 0);
         unsigned long last_map_addr;
 
         spin_lock(&init_mm.page_table_lock);
-        last_map_addr = phys_pmd_init(pmd, address, end);
+        last_map_addr = phys_pmd_init(pmd, address, end, page_size_mask);
         spin_unlock(&init_mm.page_table_lock);
         __flush_tlb_all();
         return last_map_addr;
 }
 
 static unsigned long __meminit
-phys_pud_init(pud_t *pud_page, unsigned long addr, unsigned long end)
+phys_pud_init(pud_t *pud_page, unsigned long addr, unsigned long end,
+                         unsigned long page_size_mask)
 {
+        unsigned long pages = 0;
         unsigned long last_map_addr = end;
         int i = pud_index(addr);
 
@@ -369,11 +430,13 @@ phys_pud_init(pud_t *pud_page, unsigned long addr, unsigned long end)
 
                 if (pud_val(*pud)) {
                         if (!pud_large(*pud))
-                                last_map_addr = phys_pmd_update(pud, addr, end);
+                                last_map_addr = phys_pmd_update(pud, addr, end,
+                                                         page_size_mask);
                         continue;
                 }
 
-                if (direct_gbpages) {
+                if (page_size_mask & (1<<PG_LEVEL_1G)) {
+                        pages++;
                         set_pte((pte_t *)pud,
                                 pfn_pte(addr >> PAGE_SHIFT, PAGE_KERNEL_LARGE));
                         last_map_addr = (addr & PUD_MASK) + PUD_SIZE;
@@ -383,27 +446,50 @@ phys_pud_init(pud_t *pud_page, unsigned long addr, unsigned long end)
                 pmd = alloc_low_page(&pmd_phys);
 
                 spin_lock(&init_mm.page_table_lock);
-                set_pud(pud, __pud(pmd_phys | _KERNPG_TABLE));
-                last_map_addr = phys_pmd_init(pmd, addr, end);
+                last_map_addr = phys_pmd_init(pmd, addr, end, page_size_mask);
+                unmap_low_page(pmd);
+                pud_populate(&init_mm, pud, __va(pmd_phys));
                 spin_unlock(&init_mm.page_table_lock);
 
-                unmap_low_page(pmd);
         }
         __flush_tlb_all();
+        update_page_count(PG_LEVEL_1G, pages);
 
-        return last_map_addr >> PAGE_SHIFT;
+        return last_map_addr;
+}
+
+static unsigned long __meminit
+phys_pud_update(pgd_t *pgd, unsigned long addr, unsigned long end,
+                 unsigned long page_size_mask)
+{
+        pud_t *pud;
+
+        pud = (pud_t *)pgd_page_vaddr(*pgd);
+
+        return phys_pud_init(pud, addr, end, page_size_mask);
 }
 
 static void __init find_early_table_space(unsigned long end)
 {
-        unsigned long puds, pmds, tables, start;
+        unsigned long puds, pmds, ptes, tables, start;
 
         puds = (end + PUD_SIZE - 1) >> PUD_SHIFT;
         tables = round_up(puds * sizeof(pud_t), PAGE_SIZE);
-        if (!direct_gbpages) {
+        if (direct_gbpages) {
+                unsigned long extra;
+                extra = end - ((end>>PUD_SHIFT) << PUD_SHIFT);
+                pmds = (extra + PMD_SIZE - 1) >> PMD_SHIFT;
+        } else
                 pmds = (end + PMD_SIZE - 1) >> PMD_SHIFT;
-                tables += round_up(pmds * sizeof(pmd_t), PAGE_SIZE);
-        }
+        tables += round_up(pmds * sizeof(pmd_t), PAGE_SIZE);
+
+        if (cpu_has_pse) {
+                unsigned long extra;
+                extra = end - ((end>>PMD_SHIFT) << PMD_SHIFT);
+                ptes = (extra + PAGE_SIZE - 1) >> PAGE_SHIFT;
+        } else
+                ptes = (end + PAGE_SIZE - 1) >> PAGE_SHIFT;
+        tables += round_up(ptes * sizeof(pte_t), PAGE_SIZE);
 
         /*
          * RED-PEN putting page tables only on node 0 could
@@ -417,10 +503,10 @@ static void __init find_early_table_space(unsigned long end)
 
         table_start >>= PAGE_SHIFT;
         table_end = table_start;
+        table_top = table_start + (tables >> PAGE_SHIFT);
 
-        early_printk("kernel direct mapping tables up to %lx @ %lx-%lx\n",
-                end, table_start << PAGE_SHIFT,
-                (table_start << PAGE_SHIFT) + tables);
+        printk(KERN_DEBUG "kernel direct mapping tables up to %lx @ %lx-%lx\n",
+                end, table_start << PAGE_SHIFT, table_top << PAGE_SHIFT);
 }
 
 static void __init init_gbpages(void)
@@ -431,7 +517,7 @@ static void __init init_gbpages(void)
                 direct_gbpages = 0;
 }
 
-#ifdef CONFIG_MEMTEST_BOOTPARAM
+#ifdef CONFIG_MEMTEST
 
 static void __init memtest(unsigned long start_phys, unsigned long size,
                                  unsigned pattern)
@@ -493,7 +579,8 @@ static void __init memtest(unsigned long start_phys, unsigned long size,
 
 }
 
-static int memtest_pattern __initdata = CONFIG_MEMTEST_BOOTPARAM_VALUE;
+/* default is disabled */
+static int memtest_pattern __initdata;
 
 static int __init parse_memtest(char *arg)
 {
@@ -542,15 +629,85 @@ static void __init early_memtest(unsigned long start, unsigned long end)
 }
 #endif
 
+static unsigned long __init kernel_physical_mapping_init(unsigned long start,
+                                                unsigned long end,
+                                                unsigned long page_size_mask)
+{
+
+        unsigned long next, last_map_addr = end;
+
+        start = (unsigned long)__va(start);
+        end = (unsigned long)__va(end);
+
+        for (; start < end; start = next) {
+                pgd_t *pgd = pgd_offset_k(start);
+                unsigned long pud_phys;
+                pud_t *pud;
+
+                next = start + PGDIR_SIZE;
+                if (next > end)
+                        next = end;
+
+                if (pgd_val(*pgd)) {
+                        last_map_addr = phys_pud_update(pgd, __pa(start),
+                                                 __pa(end), page_size_mask);
+                        continue;
+                }
+
+                if (after_bootmem)
+                        pud = pud_offset(pgd, start & PGDIR_MASK);
+                else
+                        pud = alloc_low_page(&pud_phys);
+
+                last_map_addr = phys_pud_init(pud, __pa(start), __pa(next),
+                                                 page_size_mask);
+                unmap_low_page(pud);
+                pgd_populate(&init_mm, pgd_offset_k(start),
+                             __va(pud_phys));
+        }
+
+        return last_map_addr;
+}
+
+struct map_range {
+        unsigned long start;
+        unsigned long end;
+        unsigned page_size_mask;
+};
+
+#define NR_RANGE_MR 5
+
+static int save_mr(struct map_range *mr, int nr_range,
+                   unsigned long start_pfn, unsigned long end_pfn,
+                   unsigned long page_size_mask)
+{
+
+        if (start_pfn < end_pfn) {
+                if (nr_range >= NR_RANGE_MR)
+                        panic("run out of range for init_memory_mapping\n");
+                mr[nr_range].start = start_pfn<<PAGE_SHIFT;
+                mr[nr_range].end   = end_pfn<<PAGE_SHIFT;
+                mr[nr_range].page_size_mask = page_size_mask;
+                nr_range++;
+        }
+
+        return nr_range;
+}
+
 /*
  * Setup the direct mapping of the physical memory at PAGE_OFFSET.
  * This runs before bootmem is initialized and gets pages directly from
  * the physical memory. To access them they are temporarily mapped.
  */
-unsigned long __init_refok init_memory_mapping(unsigned long start, unsigned long end)
+unsigned long __init_refok init_memory_mapping(unsigned long start,
+                                               unsigned long end)
 {
-        unsigned long next, last_map_addr = end;
-        unsigned long start_phys = start, end_phys = end;
+        unsigned long last_map_addr = 0;
+        unsigned long page_size_mask = 0;
+        unsigned long start_pfn, end_pfn;
+
+        struct map_range mr[NR_RANGE_MR];
+        int nr_range, i;
 
         printk(KERN_INFO "init_memory_mapping\n");
 
@@ -561,48 +718,115 @@ unsigned long __init_refok init_memory_mapping(unsigned long start, unsigned lon
          * memory mapped. Unfortunately this is done currently before the
          * nodes are discovered.
          */
-        if (!after_bootmem) {
+        if (!after_bootmem)
                 init_gbpages();
-                find_early_table_space(end);
-        }
 
-        start = (unsigned long)__va(start);
-        end = (unsigned long)__va(end);
+        if (direct_gbpages)
+                page_size_mask |= 1 << PG_LEVEL_1G;
+        if (cpu_has_pse)
+                page_size_mask |= 1 << PG_LEVEL_2M;
+
+        memset(mr, 0, sizeof(mr));
+        nr_range = 0;
+
+        /* head if not big page alignment ?*/
+        start_pfn = start >> PAGE_SHIFT;
+        end_pfn = ((start + (PMD_SIZE - 1)) >> PMD_SHIFT)
+                        << (PMD_SHIFT - PAGE_SHIFT);
+        nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 0);
+
+        /* big page (2M) range*/
+        start_pfn = ((start + (PMD_SIZE - 1))>>PMD_SHIFT)
+                         << (PMD_SHIFT - PAGE_SHIFT);
+        end_pfn = ((start + (PUD_SIZE - 1))>>PUD_SHIFT)
+                         << (PUD_SHIFT - PAGE_SHIFT);
+        if (end_pfn > ((end>>PUD_SHIFT)<<(PUD_SHIFT - PAGE_SHIFT)))
+                end_pfn = ((end>>PUD_SHIFT)<<(PUD_SHIFT - PAGE_SHIFT));
+        nr_range = save_mr(mr, nr_range, start_pfn, end_pfn,
+                        page_size_mask & (1<<PG_LEVEL_2M));
+
+        /* big page (1G) range */
+        start_pfn = end_pfn;
+        end_pfn = (end>>PUD_SHIFT) << (PUD_SHIFT - PAGE_SHIFT);
+        nr_range = save_mr(mr, nr_range, start_pfn, end_pfn,
+                                page_size_mask &
+                                 ((1<<PG_LEVEL_2M)|(1<<PG_LEVEL_1G)));
+
+        /* tail is not big page (1G) alignment */
+        start_pfn = end_pfn;
+        end_pfn = (end>>PMD_SHIFT) << (PMD_SHIFT - PAGE_SHIFT);
+        nr_range = save_mr(mr, nr_range, start_pfn, end_pfn,
+                        page_size_mask & (1<<PG_LEVEL_2M));
+
+        /* tail is not big page (2M) alignment */
+        start_pfn = end_pfn;
+        end_pfn = end>>PAGE_SHIFT;
+        nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 0);
+
+        /* try to merge same page size and continuous */
+        for (i = 0; nr_range > 1 && i < nr_range - 1; i++) {
+                unsigned long old_start;
+                if (mr[i].end != mr[i+1].start ||
+                    mr[i].page_size_mask != mr[i+1].page_size_mask)
+                        continue;
+                /* move it */
+                old_start = mr[i].start;
+                memmove(&mr[i], &mr[i+1],
+                         (nr_range - 1 - i) * sizeof (struct map_range));
+                mr[i].start = old_start;
+                nr_range--;
+        }
 
-        for (; start < end; start = next) {
-                pgd_t *pgd = pgd_offset_k(start);
-                unsigned long pud_phys;
-                pud_t *pud;
+        for (i = 0; i < nr_range; i++)
+                printk(KERN_DEBUG " %010lx - %010lx page %s\n",
+                                mr[i].start, mr[i].end,
+                        (mr[i].page_size_mask & (1<<PG_LEVEL_1G))?"1G":(
+                         (mr[i].page_size_mask & (1<<PG_LEVEL_2M))?"2M":"4k"));
 
-                if (after_bootmem)
-                        pud = pud_offset(pgd, start & PGDIR_MASK);
-                else
-                        pud = alloc_low_page(&pud_phys);
+        if (!after_bootmem)
+                find_early_table_space(end);
 
-                next = start + PGDIR_SIZE;
-                if (next > end)
-                        next = end;
-                last_map_addr = phys_pud_init(pud, __pa(start), __pa(next));
-                if (!after_bootmem)
-                        set_pgd(pgd_offset_k(start), mk_kernel_pgd(pud_phys));
-                unmap_low_page(pud);
-        }
+        for (i = 0; i < nr_range; i++)
+                last_map_addr = kernel_physical_mapping_init(
+                                        mr[i].start, mr[i].end,
+                                        mr[i].page_size_mask);
 
         if (!after_bootmem)
                 mmu_cr4_features = read_cr4();
         __flush_tlb_all();
 
-        if (!after_bootmem)
+        if (!after_bootmem && table_end > table_start)
                 reserve_early(table_start << PAGE_SHIFT,
                                  table_end << PAGE_SHIFT, "PGTABLE");
 
+        printk(KERN_INFO "last_map_addr: %lx end: %lx\n",
+                         last_map_addr, end);
+
         if (!after_bootmem)
-                early_memtest(start_phys, end_phys);
+                early_memtest(start, end);
 
-        return last_map_addr;
+        return last_map_addr >> PAGE_SHIFT;
 }
 
 #ifndef CONFIG_NUMA
+void __init initmem_init(unsigned long start_pfn, unsigned long end_pfn)
+{
+        unsigned long bootmap_size, bootmap;
+
+        bootmap_size = bootmem_bootmap_pages(end_pfn)<<PAGE_SHIFT;
+        bootmap = find_e820_area(0, end_pfn<<PAGE_SHIFT, bootmap_size,
+                                 PAGE_SIZE);
+        if (bootmap == -1L)
+                panic("Cannot find bootmem map of size %ld\n", bootmap_size);
+        /* don't touch min_low_pfn */
+        bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap >> PAGE_SHIFT,
+                                         0, end_pfn);
+        e820_register_active_regions(0, start_pfn, end_pfn);
+        free_bootmem_with_active_regions(0, end_pfn);
+        early_res_to_bootmem(0, end_pfn<<PAGE_SHIFT);
+        reserve_bootmem(bootmap, bootmap_size, BOOTMEM_DEFAULT);
+}
+
 void __init paging_init(void)
 {
         unsigned long max_zone_pfns[MAX_NR_ZONES];
@@ -610,9 +834,9 @@ void __init paging_init(void)
         memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
         max_zone_pfns[ZONE_DMA] = MAX_DMA_PFN;
         max_zone_pfns[ZONE_DMA32] = MAX_DMA32_PFN;
-        max_zone_pfns[ZONE_NORMAL] = end_pfn;
+        max_zone_pfns[ZONE_NORMAL] = max_pfn;
 
-        memory_present(0, 0, end_pfn);
+        memory_present(0, 0, max_pfn);
         sparse_init();
         free_area_init_nodes(max_zone_pfns);
 }
@@ -694,8 +918,8 @@ void __init mem_init(void)
 #else
         totalram_pages = free_all_bootmem();
 #endif
-        reservedpages = end_pfn - totalram_pages -
-                                        absent_pages_in_range(0, end_pfn);
+        reservedpages = max_pfn - totalram_pages -
+                                        absent_pages_in_range(0, max_pfn);
         after_bootmem = 1;
 
         codesize =  (unsigned long) &_etext - (unsigned long) &_text;
@@ -714,7 +938,7 @@ void __init mem_init(void)
         printk(KERN_INFO "Memory: %luk/%luk available (%ldk kernel code, "
                                 "%ldk reserved, %ldk data, %ldk init)\n",
                 (unsigned long) nr_free_pages() << (PAGE_SHIFT-10),
-                end_pfn << (PAGE_SHIFT-10),
+                max_pfn << (PAGE_SHIFT-10),
                 codesize >> 10,
                 reservedpages << (PAGE_SHIFT-10),
                 datasize >> 10,
@@ -767,6 +991,13 @@ EXPORT_SYMBOL_GPL(rodata_test_data);
 void mark_rodata_ro(void)
 {
         unsigned long start = PFN_ALIGN(_stext), end = PFN_ALIGN(__end_rodata);
+        unsigned long rodata_start =
+                ((unsigned long)__start_rodata + PAGE_SIZE - 1) & PAGE_MASK;
+
+#ifdef CONFIG_DYNAMIC_FTRACE
+        /* Dynamic tracing modifies the kernel text section */
+        start = rodata_start;
+#endif
 
         printk(KERN_INFO "Write protecting the kernel read-only data: %luk\n",
                (end - start) >> 10);
@@ -776,8 +1007,7 @@ void mark_rodata_ro(void)
          * The rodata section (but not the kernel text!) should also be
          * not-executable.
          */
-        start = ((unsigned long)__start_rodata + PAGE_SIZE - 1) & PAGE_MASK;
-        set_memory_nx(start, (end - start) >> PAGE_SHIFT);
+        set_memory_nx(rodata_start, (end - rodata_start) >> PAGE_SHIFT);
 
         rodata_test();
 
@@ -799,24 +1029,26 @@ void free_initrd_mem(unsigned long start, unsigned long end)
 }
 #endif
 
-void __init reserve_bootmem_generic(unsigned long phys, unsigned len)
+int __init reserve_bootmem_generic(unsigned long phys, unsigned long len,
+                                   int flags)
 {
 #ifdef CONFIG_NUMA
         int nid, next_nid;
+        int ret;
 #endif
         unsigned long pfn = phys >> PAGE_SHIFT;
 
-        if (pfn >= end_pfn) {
+        if (pfn >= max_pfn) {
                 /*
                  * This can happen with kdump kernels when accessing
                  * firmware tables:
                  */
                 if (pfn < max_pfn_mapped)
-                        return;
+                        return -EFAULT;
 
-                printk(KERN_ERR "reserve_bootmem: illegal reserve %lx %u\n",
+                printk(KERN_ERR "reserve_bootmem: illegal reserve %lx %lu\n",
                                 phys, len);
-                return;
+                return -EFAULT;
         }
 
         /* Should check here against the e820 map to avoid double free */
@@ -824,9 +1056,13 @@ void __init reserve_bootmem_generic(unsigned long phys, unsigned len)
         nid = phys_to_nid(phys);
         next_nid = phys_to_nid(phys + len - 1);
         if (nid == next_nid)
-                reserve_bootmem_node(NODE_DATA(nid), phys, len, BOOTMEM_DEFAULT);
+                ret = reserve_bootmem_node(NODE_DATA(nid), phys, len, flags);
         else
-                reserve_bootmem(phys, len, BOOTMEM_DEFAULT);
+                ret = reserve_bootmem(phys, len, flags);
+
+        if (ret != 0)
+                return ret;
+
 #else
         reserve_bootmem(phys, len, BOOTMEM_DEFAULT);
 #endif
@@ -835,6 +1071,8 @@ void __init reserve_bootmem_generic(unsigned long phys, unsigned len)
                 dma_reserve += len / PAGE_SIZE;
                 set_dma_reserve(dma_reserve);
         }
+
+        return 0;
 }
 
 int kern_addr_valid(unsigned long addr)
@@ -939,7 +1177,7 @@ vmemmap_populate(struct page *start_page, unsigned long size, int node)
         pmd_t *pmd;
 
         for (; addr < end; addr = next) {
-                next = pmd_addr_end(addr, end);
+                void *p = NULL;
 
                 pgd = vmemmap_pgd_populate(addr, node);
                 if (!pgd)
@@ -949,33 +1187,51 @@ vmemmap_populate(struct page *start_page, unsigned long size, int node)
                 if (!pud)
                         return -ENOMEM;
 
-                pmd = pmd_offset(pud, addr);
-                if (pmd_none(*pmd)) {
-                        pte_t entry;
-                        void *p;
+                if (!cpu_has_pse) {
+                        next = (addr + PAGE_SIZE) & PAGE_MASK;
+                        pmd = vmemmap_pmd_populate(pud, addr, node);
+
+                        if (!pmd)
+                                return -ENOMEM;
+
+                        p = vmemmap_pte_populate(pmd, addr, node);
 
-                        p = vmemmap_alloc_block(PMD_SIZE, node);
                         if (!p)
                                 return -ENOMEM;
 
-                        entry = pfn_pte(__pa(p) >> PAGE_SHIFT,
-                                                        PAGE_KERNEL_LARGE);
-                        set_pmd(pmd, __pmd(pte_val(entry)));
-
-                        /* check to see if we have contiguous blocks */
-                        if (p_end != p || node_start != node) {
-                                if (p_start)
-                                        printk(KERN_DEBUG " [%lx-%lx] PMD -> [%p-%p] on node %d\n",
-                                                addr_start, addr_end-1, p_start, p_end-1, node_start);
-                                addr_start = addr;
-                                node_start = node;
-                                p_start = p;
-                        }
-                        addr_end = addr + PMD_SIZE;
-                        p_end = p + PMD_SIZE;
+                        addr_end = addr + PAGE_SIZE;
+                        p_end = p + PAGE_SIZE;
                 } else {
-                        vmemmap_verify((pte_t *)pmd, node, addr, next);
+                        next = pmd_addr_end(addr, end);
+
+                        pmd = pmd_offset(pud, addr);
+                        if (pmd_none(*pmd)) {
+                                pte_t entry;
+
+                                p = vmemmap_alloc_block(PMD_SIZE, node);
+                                if (!p)
+                                        return -ENOMEM;
+
+                                entry = pfn_pte(__pa(p) >> PAGE_SHIFT,
+                                                PAGE_KERNEL_LARGE);
+                                set_pmd(pmd, __pmd(pte_val(entry)));
+
+                                /* check to see if we have contiguous blocks */
+                                if (p_end != p || node_start != node) {
+                                        if (p_start)
+                                                printk(KERN_DEBUG " [%lx-%lx] PMD -> [%p-%p] on node %d\n",
+                                                       addr_start, addr_end-1, p_start, p_end-1, node_start);
+                                        addr_start = addr;
+                                        node_start = node;
+                                        p_start = p;
+                                }
+
+                                addr_end = addr + PMD_SIZE;
+                                p_end = p + PMD_SIZE;
+                        } else
+                                vmemmap_verify((pte_t *)pmd, node, addr, next);
                 }
+
         }
         return 0;
 }
diff --git a/arch/x86/mm/ioremap.c b/arch/x86/mm/ioremap.c
index d1b867101e5f..24c1d3c30186 100644
--- a/arch/x86/mm/ioremap.c
+++ b/arch/x86/mm/ioremap.c
@@ -12,6 +12,7 @@
 #include <linux/module.h>
 #include <linux/slab.h>
 #include <linux/vmalloc.h>
+#include <linux/mmiotrace.h>
 
 #include <asm/cacheflush.h>
 #include <asm/e820.h>
@@ -122,10 +123,13 @@ static void __iomem *__ioremap_caller(resource_size_t phys_addr,
 {
         unsigned long pfn, offset, vaddr;
         resource_size_t last_addr;
+        const resource_size_t unaligned_phys_addr = phys_addr;
+        const unsigned long unaligned_size = size;
         struct vm_struct *area;
         unsigned long new_prot_val;
         pgprot_t prot;
         int retval;
+        void __iomem *ret_addr;
 
         /* Don't allow wraparound or zero size */
         last_addr = phys_addr + size - 1;
@@ -142,7 +146,7 @@ static void __iomem *__ioremap_caller(resource_size_t phys_addr,
         /*
          * Don't remap the low PCI/ISA area, it's always mapped..
          */
-        if (phys_addr >= ISA_START_ADDRESS && last_addr < ISA_END_ADDRESS)
+        if (is_ISA_range(phys_addr, last_addr))
                 return (__force void __iomem *)phys_to_virt(phys_addr);
 
         /*
@@ -233,7 +237,10 @@ static void __iomem *__ioremap_caller(resource_size_t phys_addr,
                 return NULL;
         }
 
-        return (void __iomem *) (vaddr + offset);
+        ret_addr = (void __iomem *) (vaddr + offset);
+        mmiotrace_ioremap(unaligned_phys_addr, unaligned_size, ret_addr);
+
+        return ret_addr;
 }
 
 /**
@@ -261,7 +268,7 @@ void __iomem *ioremap_nocache(resource_size_t phys_addr, unsigned long size)
 {
         /*
          * Ideally, this should be:
-         *      pat_wc_enabled ? _PAGE_CACHE_UC : _PAGE_CACHE_UC_MINUS;
+         *      pat_enabled ? _PAGE_CACHE_UC : _PAGE_CACHE_UC_MINUS;
          *
          * Till we fix all X drivers to use ioremap_wc(), we will use
          * UC MINUS.
@@ -285,7 +292,7 @@ EXPORT_SYMBOL(ioremap_nocache);
  */
 void __iomem *ioremap_wc(unsigned long phys_addr, unsigned long size)
 {
-        if (pat_wc_enabled)
+        if (pat_enabled)
                 return __ioremap_caller(phys_addr, size, _PAGE_CACHE_WC,
                                         __builtin_return_address(0));
         else
@@ -341,13 +348,15 @@ void iounmap(volatile void __iomem *addr)
          * vm_area and by simply returning an address into the kernel mapping
          * of ISA space.   So handle that here.
          */
-        if (addr >= phys_to_virt(ISA_START_ADDRESS) &&
-            addr < phys_to_virt(ISA_END_ADDRESS))
+        if ((void __force *)addr >= phys_to_virt(ISA_START_ADDRESS) &&
+            (void __force *)addr < phys_to_virt(ISA_END_ADDRESS))
                 return;
 
         addr = (volatile void __iomem *)
                 (PAGE_MASK & (unsigned long __force)addr);
 
+        mmiotrace_iounmap(addr);
+
         /* Use the vm area unlocked, assuming the caller
            ensures there isn't another iounmap for the same address
            in parallel. Reuse of the virtual address is prevented by
@@ -355,7 +364,7 @@ void iounmap(volatile void __iomem *addr)
            cpa takes care of the direct mappings. */
         read_lock(&vmlist_lock);
         for (p = vmlist; p; p = p->next) {
-                if (p->addr == addr)
+                if (p->addr == (void __force *)addr)
                         break;
         }
         read_unlock(&vmlist_lock);
@@ -369,7 +378,7 @@ void iounmap(volatile void __iomem *addr)
         free_memtype(p->phys_addr, p->phys_addr + get_vm_area_size(p));
 
         /* Finally remove it */
-        o = remove_vm_area((void *)addr);
+        o = remove_vm_area((void __force *)addr);
         BUG_ON(p != o || o == NULL);
         kfree(p);
 }
@@ -388,7 +397,7 @@ void *xlate_dev_mem_ptr(unsigned long phys)
         if (page_is_ram(start >> PAGE_SHIFT))
                 return __va(phys);
 
-        addr = (void *)ioremap_default(start, PAGE_SIZE);
+        addr = (void __force *)ioremap_default(start, PAGE_SIZE);
         if (addr)
                 addr = (void *)((unsigned long)addr | (phys & ~PAGE_MASK));
 
@@ -404,8 +413,6 @@ void unxlate_dev_mem_ptr(unsigned long phys, void *addr)
         return;
 }
 
-#ifdef CONFIG_X86_32
-
 int __initdata early_ioremap_debug;
 
 static int __init early_ioremap_debug_setup(char *str)
@@ -417,8 +424,7 @@ static int __init early_ioremap_debug_setup(char *str)
 early_param("early_ioremap_debug", early_ioremap_debug_setup);
 
 static __initdata int after_paging_init;
-static pte_t bm_pte[PAGE_SIZE/sizeof(pte_t)]
-                __section(.bss.page_aligned);
+static pte_t bm_pte[PAGE_SIZE/sizeof(pte_t)] __page_aligned_bss;
 
 static inline pmd_t * __init early_ioremap_pmd(unsigned long addr)
 {
@@ -507,10 +513,11 @@ static void __init __early_set_fixmap(enum fixed_addresses idx,
                 return;
         }
         pte = early_ioremap_pte(addr);
+
         if (pgprot_val(flags))
                 set_pte(pte, pfn_pte(phys >> PAGE_SHIFT, flags));
         else
-                pte_clear(NULL, addr, pte);
+                pte_clear(&init_mm, addr, pte);
         __flush_tlb_one(addr);
 }
 
@@ -648,5 +655,3 @@ void __this_fixmap_does_not_exist(void)
 {
         WARN_ON(1);
 }
-
-#endif /* CONFIG_X86_32 */
diff --git a/arch/x86/mm/k8topology_64.c b/arch/x86/mm/k8topology_64.c
index 1f476e477844..41f1b5c00a1d 100644
--- a/arch/x86/mm/k8topology_64.c
+++ b/arch/x86/mm/k8topology_64.c
@@ -22,6 +22,7 @@
 #include <asm/numa.h>
 #include <asm/mpspec.h>
 #include <asm/apic.h>
+#include <asm/k8.h>
 
 static __init int find_northbridge(void)
 {
@@ -56,34 +57,33 @@ static __init void early_get_boot_cpu_id(void)
         /*
          * Find possible boot-time SMP configuration:
          */
+#ifdef CONFIG_X86_MPPARSE
         early_find_smp_config();
+#endif
 #ifdef CONFIG_ACPI
         /*
          * Read APIC information from ACPI tables.
          */
         early_acpi_boot_init();
 #endif
+#ifdef CONFIG_X86_MPPARSE
         /*
          * get boot-time SMP configuration:
          */
         if (smp_found_config)
                 early_get_smp_config();
+#endif
         early_init_lapic_mapping();
 }
 
 int __init k8_scan_nodes(unsigned long start, unsigned long end)
 {
+        unsigned numnodes, cores, bits, apicid_base;
         unsigned long prevbase;
         struct bootnode nodes[8];
-        int nodeid, i, nb;
         unsigned char nodeids[8];
-        int found = 0;
-        u32 reg;
-        unsigned numnodes;
-        unsigned cores;
-        unsigned bits;
-        int j;
-        unsigned apicid_base;
+        int i, j, nb, found = 0;
+        u32 nodeid, reg;
 
         if (!early_pci_allowed())
                 return -1;
@@ -105,7 +105,6 @@ int __init k8_scan_nodes(unsigned long start, unsigned long end)
         prevbase = 0;
         for (i = 0; i < 8; i++) {
                 unsigned long base, limit;
-                u32 nodeid;
 
                 base = read_pci_config(0, nb, 1, 0x40 + i*8);
                 limit = read_pci_config(0, nb, 1, 0x44 + i*8);
@@ -144,8 +143,8 @@ int __init k8_scan_nodes(unsigned long start, unsigned long end)
                 limit |= (1<<24)-1;
                 limit++;
 
-                if (limit > end_pfn << PAGE_SHIFT)
-                        limit = end_pfn << PAGE_SHIFT;
+                if (limit > max_pfn << PAGE_SHIFT)
+                        limit = max_pfn << PAGE_SHIFT;
                 if (limit <= base)
                         continue;
 
diff --git a/arch/x86/mm/kmmio.c b/arch/x86/mm/kmmio.c
new file mode 100644
index 000000000000..93d82038af4b
--- /dev/null
+++ b/arch/x86/mm/kmmio.c
@@ -0,0 +1,510 @@
+/* Support for MMIO probes.
+ * Benfit many code from kprobes
+ * (C) 2002 Louis Zhuang <louis.zhuang@intel.com>.
+ *     2007 Alexander Eichner
+ *     2008 Pekka Paalanen <pq@iki.fi>
+ */
+
+#include <linux/list.h>
+#include <linux/rculist.h>
+#include <linux/spinlock.h>
+#include <linux/hash.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/uaccess.h>
+#include <linux/ptrace.h>
+#include <linux/preempt.h>
+#include <linux/percpu.h>
+#include <linux/kdebug.h>
+#include <linux/mutex.h>
+#include <linux/io.h>
+#include <asm/cacheflush.h>
+#include <asm/tlbflush.h>
+#include <linux/errno.h>
+#include <asm/debugreg.h>
+#include <linux/mmiotrace.h>
+
+#define KMMIO_PAGE_HASH_BITS 4
+#define KMMIO_PAGE_TABLE_SIZE (1 << KMMIO_PAGE_HASH_BITS)
+
+struct kmmio_fault_page {
+        struct list_head list;
+        struct kmmio_fault_page *release_next;
+        unsigned long page; /* location of the fault page */
+
+        /*
+         * Number of times this page has been registered as a part
+         * of a probe. If zero, page is disarmed and this may be freed.
+         * Used only by writers (RCU).
+         */
+        int count;
+};
+
+struct kmmio_delayed_release {
+        struct rcu_head rcu;
+        struct kmmio_fault_page *release_list;
+};
+
+struct kmmio_context {
+        struct kmmio_fault_page *fpage;
+        struct kmmio_probe *probe;
+        unsigned long saved_flags;
+        unsigned long addr;
+        int active;
+};
+
+static DEFINE_SPINLOCK(kmmio_lock);
+
+/* Protected by kmmio_lock */
+unsigned int kmmio_count;
+
+/* Read-protected by RCU, write-protected by kmmio_lock. */
+static struct list_head kmmio_page_table[KMMIO_PAGE_TABLE_SIZE];
+static LIST_HEAD(kmmio_probes);
+
+static struct list_head *kmmio_page_list(unsigned long page)
+{
+        return &kmmio_page_table[hash_long(page, KMMIO_PAGE_HASH_BITS)];
+}
+
+/* Accessed per-cpu */
+static DEFINE_PER_CPU(struct kmmio_context, kmmio_ctx);
+
+/*
+ * this is basically a dynamic stabbing problem:
+ * Could use the existing prio tree code or
+ * Possible better implementations:
+ * The Interval Skip List: A Data Structure for Finding All Intervals That
+ * Overlap a Point (might be simple)
+ * Space Efficient Dynamic Stabbing with Fast Queries - Mikkel Thorup
+ */
+/* Get the kmmio at this addr (if any). You must be holding RCU read lock. */
+static struct kmmio_probe *get_kmmio_probe(unsigned long addr)
+{
+        struct kmmio_probe *p;
+        list_for_each_entry_rcu(p, &kmmio_probes, list) {
+                if (addr >= p->addr && addr <= (p->addr + p->len))
+                        return p;
+        }
+        return NULL;
+}
+
+/* You must be holding RCU read lock. */
+static struct kmmio_fault_page *get_kmmio_fault_page(unsigned long page)
+{
+        struct list_head *head;
+        struct kmmio_fault_page *p;
+
+        page &= PAGE_MASK;
+        head = kmmio_page_list(page);
+        list_for_each_entry_rcu(p, head, list) {
+                if (p->page == page)
+                        return p;
+        }
+        return NULL;
+}
+
+static void set_page_present(unsigned long addr, bool present,
+                                                        unsigned int *pglevel)
+{
+        pteval_t pteval;
+        pmdval_t pmdval;
+        unsigned int level;
+        pmd_t *pmd;
+        pte_t *pte = lookup_address(addr, &level);
+
+        if (!pte) {
+                pr_err("kmmio: no pte for page 0x%08lx\n", addr);
+                return;
+        }
+
+        if (pglevel)
+                *pglevel = level;
+
+        switch (level) {
+        case PG_LEVEL_2M:
+                pmd = (pmd_t *)pte;
+                pmdval = pmd_val(*pmd) & ~_PAGE_PRESENT;
+                if (present)
+                        pmdval |= _PAGE_PRESENT;
+                set_pmd(pmd, __pmd(pmdval));
+                break;
+
+        case PG_LEVEL_4K:
+                pteval = pte_val(*pte) & ~_PAGE_PRESENT;
+                if (present)
+                        pteval |= _PAGE_PRESENT;
+                set_pte_atomic(pte, __pte(pteval));
+                break;
+
+        default:
+                pr_err("kmmio: unexpected page level 0x%x.\n", level);
+                return;
+        }
+
+        __flush_tlb_one(addr);
+}
+
+/** Mark the given page as not present. Access to it will trigger a fault. */
+static void arm_kmmio_fault_page(unsigned long page, unsigned int *pglevel)
+{
+        set_page_present(page & PAGE_MASK, false, pglevel);
+}
+
+/** Mark the given page as present. */
+static void disarm_kmmio_fault_page(unsigned long page, unsigned int *pglevel)
+{
+        set_page_present(page & PAGE_MASK, true, pglevel);
+}
+
+/*
+ * This is being called from do_page_fault().
+ *
+ * We may be in an interrupt or a critical section. Also prefecthing may
+ * trigger a page fault. We may be in the middle of process switch.
+ * We cannot take any locks, because we could be executing especially
+ * within a kmmio critical section.
+ *
+ * Local interrupts are disabled, so preemption cannot happen.
+ * Do not enable interrupts, do not sleep, and watch out for other CPUs.
+ */
+/*
+ * Interrupts are disabled on entry as trap3 is an interrupt gate
+ * and they remain disabled thorough out this function.
+ */
+int kmmio_handler(struct pt_regs *regs, unsigned long addr)
+{
+        struct kmmio_context *ctx;
+        struct kmmio_fault_page *faultpage;
+        int ret = 0; /* default to fault not handled */
+
+        /*
+         * Preemption is now disabled to prevent process switch during
+         * single stepping. We can only handle one active kmmio trace
+         * per cpu, so ensure that we finish it before something else
+         * gets to run. We also hold the RCU read lock over single
+         * stepping to avoid looking up the probe and kmmio_fault_page
+         * again.
+         */
+        preempt_disable();
+        rcu_read_lock();
+
+        faultpage = get_kmmio_fault_page(addr);
+        if (!faultpage) {
+                /*
+                 * Either this page fault is not caused by kmmio, or
+                 * another CPU just pulled the kmmio probe from under
+                 * our feet. The latter case should not be possible.
+                 */
+                goto no_kmmio;
+        }
+
+        ctx = &get_cpu_var(kmmio_ctx);
+        if (ctx->active) {
+                disarm_kmmio_fault_page(faultpage->page, NULL);
+                if (addr == ctx->addr) {
+                        /*
+                         * On SMP we sometimes get recursive probe hits on the
+                         * same address. Context is already saved, fall out.
+                         */
+                        pr_debug("kmmio: duplicate probe hit on CPU %d, for "
+                                                "address 0x%08lx.\n",
+                                                smp_processor_id(), addr);
+                        ret = 1;
+                        goto no_kmmio_ctx;
+                }
+                /*
+                 * Prevent overwriting already in-flight context.
+                 * This should not happen, let's hope disarming at least
+                 * prevents a panic.
+                 */
+                pr_emerg("kmmio: recursive probe hit on CPU %d, "
+                                        "for address 0x%08lx. Ignoring.\n",
+                                        smp_processor_id(), addr);
+                pr_emerg("kmmio: previous hit was at 0x%08lx.\n",
+                                        ctx->addr);
+                goto no_kmmio_ctx;
+        }
+        ctx->active++;
+
+        ctx->fpage = faultpage;
+        ctx->probe = get_kmmio_probe(addr);
+        ctx->saved_flags = (regs->flags & (X86_EFLAGS_TF | X86_EFLAGS_IF));
+        ctx->addr = addr;
+
+        if (ctx->probe && ctx->probe->pre_handler)
+                ctx->probe->pre_handler(ctx->probe, regs, addr);
+
+        /*
+         * Enable single-stepping and disable interrupts for the faulting
+         * context. Local interrupts must not get enabled during stepping.
+         */
+        regs->flags |= X86_EFLAGS_TF;
+        regs->flags &= ~X86_EFLAGS_IF;
+
+        /* Now we set present bit in PTE and single step. */
+        disarm_kmmio_fault_page(ctx->fpage->page, NULL);
+
+        /*
+         * If another cpu accesses the same page while we are stepping,
+         * the access will not be caught. It will simply succeed and the
+         * only downside is we lose the event. If this becomes a problem,
+         * the user should drop to single cpu before tracing.
+         */
+
+        put_cpu_var(kmmio_ctx);
+        return 1; /* fault handled */
+
+no_kmmio_ctx:
+        put_cpu_var(kmmio_ctx);
+no_kmmio:
+        rcu_read_unlock();
+        preempt_enable_no_resched();
+        return ret;
+}
+
+/*
+ * Interrupts are disabled on entry as trap1 is an interrupt gate
+ * and they remain disabled thorough out this function.
+ * This must always get called as the pair to kmmio_handler().
+ */
+static int post_kmmio_handler(unsigned long condition, struct pt_regs *regs)
+{
+        int ret = 0;
+        struct kmmio_context *ctx = &get_cpu_var(kmmio_ctx);
+
+        if (!ctx->active) {
+                pr_debug("kmmio: spurious debug trap on CPU %d.\n",
+                                                        smp_processor_id());
+                goto out;
+        }
+
+        if (ctx->probe && ctx->probe->post_handler)
+                ctx->probe->post_handler(ctx->probe, condition, regs);
+
+        arm_kmmio_fault_page(ctx->fpage->page, NULL);
+
+        regs->flags &= ~X86_EFLAGS_TF;
+        regs->flags |= ctx->saved_flags;
+
+        /* These were acquired in kmmio_handler(). */
+        ctx->active--;
+        BUG_ON(ctx->active);
+        rcu_read_unlock();
+        preempt_enable_no_resched();
+
+        /*
+         * if somebody else is singlestepping across a probe point, flags
+         * will have TF set, in which case, continue the remaining processing
+         * of do_debug, as if this is not a probe hit.
+         */
+        if (!(regs->flags & X86_EFLAGS_TF))
+                ret = 1;
+out:
+        put_cpu_var(kmmio_ctx);
+        return ret;
+}
+
+/* You must be holding kmmio_lock. */
+static int add_kmmio_fault_page(unsigned long page)
+{
+        struct kmmio_fault_page *f;
+
+        page &= PAGE_MASK;
+        f = get_kmmio_fault_page(page);
+        if (f) {
+                if (!f->count)
+                        arm_kmmio_fault_page(f->page, NULL);
+                f->count++;
+                return 0;
+        }
+
+        f = kmalloc(sizeof(*f), GFP_ATOMIC);
+        if (!f)
+                return -1;
+
+        f->count = 1;
+        f->page = page;
+        list_add_rcu(&f->list, kmmio_page_list(f->page));
+
+        arm_kmmio_fault_page(f->page, NULL);
+
+        return 0;
+}
+
+/* You must be holding kmmio_lock. */
+static void release_kmmio_fault_page(unsigned long page,
+                                struct kmmio_fault_page **release_list)
+{
+        struct kmmio_fault_page *f;
+
+        page &= PAGE_MASK;
+        f = get_kmmio_fault_page(page);
+        if (!f)
+                return;
+
+        f->count--;
+        BUG_ON(f->count < 0);
+        if (!f->count) {
+                disarm_kmmio_fault_page(f->page, NULL);
+                f->release_next = *release_list;
+                *release_list = f;
+        }
+}
+
+/*
+ * With page-unaligned ioremaps, one or two armed pages may contain
+ * addresses from outside the intended mapping. Events for these addresses
+ * are currently silently dropped. The events may result only from programming
+ * mistakes by accessing addresses before the beginning or past the end of a
+ * mapping.
+ */
+int register_kmmio_probe(struct kmmio_probe *p)
+{
+        unsigned long flags;
+        int ret = 0;
+        unsigned long size = 0;
+        const unsigned long size_lim = p->len + (p->addr & ~PAGE_MASK);
+
+        spin_lock_irqsave(&kmmio_lock, flags);
+        if (get_kmmio_probe(p->addr)) {
+                ret = -EEXIST;
+                goto out;
+        }
+        kmmio_count++;
+        list_add_rcu(&p->list, &kmmio_probes);
+        while (size < size_lim) {
+                if (add_kmmio_fault_page(p->addr + size))
+                        pr_err("kmmio: Unable to set page fault.\n");
+                size += PAGE_SIZE;
+        }
+out:
+        spin_unlock_irqrestore(&kmmio_lock, flags);
+        /*
+         * XXX: What should I do here?
+         * Here was a call to global_flush_tlb(), but it does not exist
+         * anymore. It seems it's not needed after all.
+         */
+        return ret;
+}
+EXPORT_SYMBOL(register_kmmio_probe);
+
+static void rcu_free_kmmio_fault_pages(struct rcu_head *head)
+{
+        struct kmmio_delayed_release *dr = container_of(
+                                                head,
+                                                struct kmmio_delayed_release,
+                                                rcu);
+        struct kmmio_fault_page *p = dr->release_list;
+        while (p) {
+                struct kmmio_fault_page *next = p->release_next;
+                BUG_ON(p->count);
+                kfree(p);
+                p = next;
+        }
+        kfree(dr);
+}
+
+static void remove_kmmio_fault_pages(struct rcu_head *head)
+{
+        struct kmmio_delayed_release *dr = container_of(
+                                                head,
+                                                struct kmmio_delayed_release,
+                                                rcu);
+        struct kmmio_fault_page *p = dr->release_list;
+        struct kmmio_fault_page **prevp = &dr->release_list;
+        unsigned long flags;
+        spin_lock_irqsave(&kmmio_lock, flags);
+        while (p) {
+                if (!p->count)
+                        list_del_rcu(&p->list);
+                else
+                        *prevp = p->release_next;
+                prevp = &p->release_next;
+                p = p->release_next;
+        }
+        spin_unlock_irqrestore(&kmmio_lock, flags);
+        /* This is the real RCU destroy call. */
+        call_rcu(&dr->rcu, rcu_free_kmmio_fault_pages);
+}
+
+/*
+ * Remove a kmmio probe. You have to synchronize_rcu() before you can be
+ * sure that the callbacks will not be called anymore. Only after that
+ * you may actually release your struct kmmio_probe.
+ *
+ * Unregistering a kmmio fault page has three steps:
+ * 1. release_kmmio_fault_page()
+ *    Disarm the page, wait a grace period to let all faults finish.
+ * 2. remove_kmmio_fault_pages()
+ *    Remove the pages from kmmio_page_table.
+ * 3. rcu_free_kmmio_fault_pages()
+ *    Actally free the kmmio_fault_page structs as with RCU.
+ */
+void unregister_kmmio_probe(struct kmmio_probe *p)
+{
+        unsigned long flags;
+        unsigned long size = 0;
+        const unsigned long size_lim = p->len + (p->addr & ~PAGE_MASK);
+        struct kmmio_fault_page *release_list = NULL;
+        struct kmmio_delayed_release *drelease;
+
+        spin_lock_irqsave(&kmmio_lock, flags);
+        while (size < size_lim) {
+                release_kmmio_fault_page(p->addr + size, &release_list);
+                size += PAGE_SIZE;
+        }
+        list_del_rcu(&p->list);
+        kmmio_count--;
+        spin_unlock_irqrestore(&kmmio_lock, flags);
+
+        drelease = kmalloc(sizeof(*drelease), GFP_ATOMIC);
+        if (!drelease) {
+                pr_crit("kmmio: leaking kmmio_fault_page objects.\n");
+                return;
+        }
+        drelease->release_list = release_list;
+
+        /*
+         * This is not really RCU here. We have just disarmed a set of
+         * pages so that they cannot trigger page faults anymore. However,
+         * we cannot remove the pages from kmmio_page_table,
+         * because a probe hit might be in flight on another CPU. The
+         * pages are collected into a list, and they will be removed from
+         * kmmio_page_table when it is certain that no probe hit related to
+         * these pages can be in flight. RCU grace period sounds like a
+         * good choice.
+         *
+         * If we removed the pages too early, kmmio page fault handler might
+         * not find the respective kmmio_fault_page and determine it's not
+         * a kmmio fault, when it actually is. This would lead to madness.
+         */
+        call_rcu(&drelease->rcu, remove_kmmio_fault_pages);
+}
+EXPORT_SYMBOL(unregister_kmmio_probe);
+
+static int kmmio_die_notifier(struct notifier_block *nb, unsigned long val,
+                                                                void *args)
+{
+        struct die_args *arg = args;
+
+        if (val == DIE_DEBUG && (arg->err & DR_STEP))
+                if (post_kmmio_handler(arg->err, arg->regs) == 1)
+                        return NOTIFY_STOP;
+
+        return NOTIFY_DONE;
+}
+
+static struct notifier_block nb_die = {
+        .notifier_call = kmmio_die_notifier
+};
+
+static int __init init_kmmio(void)
+{
+        int i;
+        for (i = 0; i < KMMIO_PAGE_TABLE_SIZE; i++)
+                INIT_LIST_HEAD(&kmmio_page_table[i]);
+        return register_die_notifier(&nb_die);
+}
+fs_initcall(init_kmmio); /* should be before device_initcall() */
diff --git a/arch/x86/mm/mmio-mod.c b/arch/x86/mm/mmio-mod.c
new file mode 100644
index 000000000000..e7397e108beb
--- /dev/null
+++ b/arch/x86/mm/mmio-mod.c
@@ -0,0 +1,515 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (C) IBM Corporation, 2005
+ *               Jeff Muizelaar, 2006, 2007
+ *               Pekka Paalanen, 2008 <pq@iki.fi>
+ *
+ * Derived from the read-mod example from relay-examples by Tom Zanussi.
+ */
+#define DEBUG 1
+
+#include <linux/module.h>
+#include <linux/debugfs.h>
+#include <linux/uaccess.h>
+#include <linux/io.h>
+#include <linux/version.h>
+#include <linux/kallsyms.h>
+#include <asm/pgtable.h>
+#include <linux/mmiotrace.h>
+#include <asm/e820.h> /* for ISA_START_ADDRESS */
+#include <asm/atomic.h>
+#include <linux/percpu.h>
+#include <linux/cpu.h>
+
+#include "pf_in.h"
+
+#define NAME "mmiotrace: "
+
+struct trap_reason {
+        unsigned long addr;
+        unsigned long ip;
+        enum reason_type type;
+        int active_traces;
+};
+
+struct remap_trace {
+        struct list_head list;
+        struct kmmio_probe probe;
+        resource_size_t phys;
+        unsigned long id;
+};
+
+/* Accessed per-cpu. */
+static DEFINE_PER_CPU(struct trap_reason, pf_reason);
+static DEFINE_PER_CPU(struct mmiotrace_rw, cpu_trace);
+
+#if 0 /* XXX: no way gather this info anymore */
+/* Access to this is not per-cpu. */
+static DEFINE_PER_CPU(atomic_t, dropped);
+#endif
+
+static struct dentry *marker_file;
+
+static DEFINE_MUTEX(mmiotrace_mutex);
+static DEFINE_SPINLOCK(trace_lock);
+static atomic_t mmiotrace_enabled;
+static LIST_HEAD(trace_list);           /* struct remap_trace */
+
+/*
+ * Locking in this file:
+ * - mmiotrace_mutex enforces enable/disable_mmiotrace() critical sections.
+ * - mmiotrace_enabled may be modified only when holding mmiotrace_mutex
+ *   and trace_lock.
+ * - Routines depending on is_enabled() must take trace_lock.
+ * - trace_list users must hold trace_lock.
+ * - is_enabled() guarantees that mmio_trace_record is allowed.
+ * - pre/post callbacks assume the effect of is_enabled() being true.
+ */
+
+/* module parameters */
+static unsigned long    filter_offset;
+static int              nommiotrace;
+static int              trace_pc;
+
+module_param(filter_offset, ulong, 0);
+module_param(nommiotrace, bool, 0);
+module_param(trace_pc, bool, 0);
+
+MODULE_PARM_DESC(filter_offset, "Start address of traced mappings.");
+MODULE_PARM_DESC(nommiotrace, "Disable actual MMIO tracing.");
+MODULE_PARM_DESC(trace_pc, "Record address of faulting instructions.");
+
+static bool is_enabled(void)
+{
+        return atomic_read(&mmiotrace_enabled);
+}
+
+#if 0 /* XXX: needs rewrite */
+/*
+ * Write callback for the debugfs entry:
+ * Read a marker and write it to the mmio trace log
+ */
+static ssize_t write_marker(struct file *file, const char __user *buffer,
+                                                size_t count, loff_t *ppos)
+{
+        char *event = NULL;
+        struct mm_io_header *headp;
+        ssize_t len = (count > 65535) ? 65535 : count;
+
+        event = kzalloc(sizeof(*headp) + len, GFP_KERNEL);
+        if (!event)
+                return -ENOMEM;
+
+        headp = (struct mm_io_header *)event;
+        headp->type = MMIO_MAGIC | (MMIO_MARKER << MMIO_OPCODE_SHIFT);
+        headp->data_len = len;
+
+        if (copy_from_user(event + sizeof(*headp), buffer, len)) {
+                kfree(event);
+                return -EFAULT;
+        }
+
+        spin_lock_irq(&trace_lock);
+#if 0 /* XXX: convert this to use tracing */
+        if (is_enabled())
+                relay_write(chan, event, sizeof(*headp) + len);
+        else
+#endif
+                len = -EINVAL;
+        spin_unlock_irq(&trace_lock);
+        kfree(event);
+        return len;
+}
+#endif
+
+static void print_pte(unsigned long address)
+{
+        unsigned int level;
+        pte_t *pte = lookup_address(address, &level);
+
+        if (!pte) {
+                pr_err(NAME "Error in %s: no pte for page 0x%08lx\n",
+                                                        __func__, address);
+                return;
+        }
+
+        if (level == PG_LEVEL_2M) {
+                pr_emerg(NAME "4MB pages are not currently supported: "
+                                                        "0x%08lx\n", address);
+                BUG();
+        }
+        pr_info(NAME "pte for 0x%lx: 0x%llx 0x%llx\n", address,
+                (unsigned long long)pte_val(*pte),
+                (unsigned long long)pte_val(*pte) & _PAGE_PRESENT);
+}
+
+/*
+ * For some reason the pre/post pairs have been called in an
+ * unmatched order. Report and die.
+ */
+static void die_kmmio_nesting_error(struct pt_regs *regs, unsigned long addr)
+{
+        const struct trap_reason *my_reason = &get_cpu_var(pf_reason);
+        pr_emerg(NAME "unexpected fault for address: 0x%08lx, "
+                                        "last fault for address: 0x%08lx\n",
+                                        addr, my_reason->addr);
+        print_pte(addr);
+        print_symbol(KERN_EMERG "faulting IP is at %s\n", regs->ip);
+        print_symbol(KERN_EMERG "last faulting IP was at %s\n", my_reason->ip);
+#ifdef __i386__
+        pr_emerg("eax: %08lx   ebx: %08lx   ecx: %08lx   edx: %08lx\n",
+                        regs->ax, regs->bx, regs->cx, regs->dx);
+        pr_emerg("esi: %08lx   edi: %08lx   ebp: %08lx   esp: %08lx\n",
+                        regs->si, regs->di, regs->bp, regs->sp);
+#else
+        pr_emerg("rax: %016lx   rcx: %016lx   rdx: %016lx\n",
+                                        regs->ax, regs->cx, regs->dx);
+        pr_emerg("rsi: %016lx   rdi: %016lx   rbp: %016lx   rsp: %016lx\n",
+                                regs->si, regs->di, regs->bp, regs->sp);
+#endif
+        put_cpu_var(pf_reason);
+        BUG();
+}
+
+static void pre(struct kmmio_probe *p, struct pt_regs *regs,
+                                                unsigned long addr)
+{
+        struct trap_reason *my_reason = &get_cpu_var(pf_reason);
+        struct mmiotrace_rw *my_trace = &get_cpu_var(cpu_trace);
+        const unsigned long instptr = instruction_pointer(regs);
+        const enum reason_type type = get_ins_type(instptr);
+        struct remap_trace *trace = p->private;
+
+        /* it doesn't make sense to have more than one active trace per cpu */
+        if (my_reason->active_traces)
+                die_kmmio_nesting_error(regs, addr);
+        else
+                my_reason->active_traces++;
+
+        my_reason->type = type;
+        my_reason->addr = addr;
+        my_reason->ip = instptr;
+
+        my_trace->phys = addr - trace->probe.addr + trace->phys;
+        my_trace->map_id = trace->id;
+
+        /*
+         * Only record the program counter when requested.
+         * It may taint clean-room reverse engineering.
+         */
+        if (trace_pc)
+                my_trace->pc = instptr;
+        else
+                my_trace->pc = 0;
+
+        /*
+         * XXX: the timestamp recorded will be *after* the tracing has been
+         * done, not at the time we hit the instruction. SMP implications
+         * on event ordering?
+         */
+
+        switch (type) {
+        case REG_READ:
+                my_trace->opcode = MMIO_READ;
+                my_trace->width = get_ins_mem_width(instptr);
+                break;
+        case REG_WRITE:
+                my_trace->opcode = MMIO_WRITE;
+                my_trace->width = get_ins_mem_width(instptr);
+                my_trace->value = get_ins_reg_val(instptr, regs);
+                break;
+        case IMM_WRITE:
+                my_trace->opcode = MMIO_WRITE;
+                my_trace->width = get_ins_mem_width(instptr);
+                my_trace->value = get_ins_imm_val(instptr);
+                break;
+        default:
+                {
+                        unsigned char *ip = (unsigned char *)instptr;
+                        my_trace->opcode = MMIO_UNKNOWN_OP;
+                        my_trace->width = 0;
+                        my_trace->value = (*ip) << 16 | *(ip + 1) << 8 |
+                                                                *(ip + 2);
+                }
+        }
+        put_cpu_var(cpu_trace);
+        put_cpu_var(pf_reason);
+}
+
+static void post(struct kmmio_probe *p, unsigned long condition,
+                                                        struct pt_regs *regs)
+{
+        struct trap_reason *my_reason = &get_cpu_var(pf_reason);
+        struct mmiotrace_rw *my_trace = &get_cpu_var(cpu_trace);
+
+        /* this should always return the active_trace count to 0 */
+        my_reason->active_traces--;
+        if (my_reason->active_traces) {
+                pr_emerg(NAME "unexpected post handler");
+                BUG();
+        }
+
+        switch (my_reason->type) {
+        case REG_READ:
+                my_trace->value = get_ins_reg_val(my_reason->ip, regs);
+                break;
+        default:
+                break;
+        }
+
+        mmio_trace_rw(my_trace);
+        put_cpu_var(cpu_trace);
+        put_cpu_var(pf_reason);
+}
+
+static void ioremap_trace_core(resource_size_t offset, unsigned long size,
+                                                        void __iomem *addr)
+{
+        static atomic_t next_id;
+        struct remap_trace *trace = kmalloc(sizeof(*trace), GFP_KERNEL);
+        /* These are page-unaligned. */
+        struct mmiotrace_map map = {
+                .phys = offset,
+                .virt = (unsigned long)addr,
+                .len = size,
+                .opcode = MMIO_PROBE
+        };
+
+        if (!trace) {
+                pr_err(NAME "kmalloc failed in ioremap\n");
+                return;
+        }
+
+        *trace = (struct remap_trace) {
+                .probe = {
+                        .addr = (unsigned long)addr,
+                        .len = size,
+                        .pre_handler = pre,
+                        .post_handler = post,
+                        .private = trace
+                },
+                .phys = offset,
+                .id = atomic_inc_return(&next_id)
+        };
+        map.map_id = trace->id;
+
+        spin_lock_irq(&trace_lock);
+        if (!is_enabled())
+                goto not_enabled;
+
+        mmio_trace_mapping(&map);
+        list_add_tail(&trace->list, &trace_list);
+        if (!nommiotrace)
+                register_kmmio_probe(&trace->probe);
+
+not_enabled:
+        spin_unlock_irq(&trace_lock);
+}
+
+void mmiotrace_ioremap(resource_size_t offset, unsigned long size,
+                                                void __iomem *addr)
+{
+        if (!is_enabled()) /* recheck and proper locking in *_core() */
+                return;
+
+        pr_debug(NAME "ioremap_*(0x%llx, 0x%lx) = %p\n",
+                                (unsigned long long)offset, size, addr);
+        if ((filter_offset) && (offset != filter_offset))
+                return;
+        ioremap_trace_core(offset, size, addr);
+}
+
+static void iounmap_trace_core(volatile void __iomem *addr)
+{
+        struct mmiotrace_map map = {
+                .phys = 0,
+                .virt = (unsigned long)addr,
+                .len = 0,
+                .opcode = MMIO_UNPROBE
+        };
+        struct remap_trace *trace;
+        struct remap_trace *tmp;
+        struct remap_trace *found_trace = NULL;
+
+        pr_debug(NAME "Unmapping %p.\n", addr);
+
+        spin_lock_irq(&trace_lock);
+        if (!is_enabled())
+                goto not_enabled;
+
+        list_for_each_entry_safe(trace, tmp, &trace_list, list) {
+                if ((unsigned long)addr == trace->probe.addr) {
+                        if (!nommiotrace)
+                                unregister_kmmio_probe(&trace->probe);
+                        list_del(&trace->list);
+                        found_trace = trace;
+                        break;
+                }
+        }
+        map.map_id = (found_trace) ? found_trace->id : -1;
+        mmio_trace_mapping(&map);
+
+not_enabled:
+        spin_unlock_irq(&trace_lock);
+        if (found_trace) {
+                synchronize_rcu(); /* unregister_kmmio_probe() requirement */
+                kfree(found_trace);
+        }
+}
+
+void mmiotrace_iounmap(volatile void __iomem *addr)
+{
+        might_sleep();
+        if (is_enabled()) /* recheck and proper locking in *_core() */
+                iounmap_trace_core(addr);
+}
+
+static void clear_trace_list(void)
+{
+        struct remap_trace *trace;
+        struct remap_trace *tmp;
+
+        /*
+         * No locking required, because the caller ensures we are in a
+         * critical section via mutex, and is_enabled() is false,
+         * i.e. nothing can traverse or modify this list.
+         * Caller also ensures is_enabled() cannot change.
+         */
+        list_for_each_entry(trace, &trace_list, list) {
+                pr_notice(NAME "purging non-iounmapped "
+                                        "trace @0x%08lx, size 0x%lx.\n",
+                                        trace->probe.addr, trace->probe.len);
+                if (!nommiotrace)
+                        unregister_kmmio_probe(&trace->probe);
+        }
+        synchronize_rcu(); /* unregister_kmmio_probe() requirement */
+
+        list_for_each_entry_safe(trace, tmp, &trace_list, list) {
+                list_del(&trace->list);
+                kfree(trace);
+        }
+}
+
+#ifdef CONFIG_HOTPLUG_CPU
+static cpumask_t downed_cpus;
+
+static void enter_uniprocessor(void)
+{
+        int cpu;
+        int err;
+
+        get_online_cpus();
+        downed_cpus = cpu_online_map;
+        cpu_clear(first_cpu(cpu_online_map), downed_cpus);
+        if (num_online_cpus() > 1)
+                pr_notice(NAME "Disabling non-boot CPUs...\n");
+        put_online_cpus();
+
+        for_each_cpu_mask(cpu, downed_cpus) {
+                err = cpu_down(cpu);
+                if (!err)
+                        pr_info(NAME "CPU%d is down.\n", cpu);
+                else
+                        pr_err(NAME "Error taking CPU%d down: %d\n", cpu, err);
+        }
+        if (num_online_cpus() > 1)
+                pr_warning(NAME "multiple CPUs still online, "
+                                                "may miss events.\n");
+}
+
+static void leave_uniprocessor(void)
+{
+        int cpu;
+        int err;
+
+        if (cpus_weight(downed_cpus) == 0)
+                return;
+        pr_notice(NAME "Re-enabling CPUs...\n");
+        for_each_cpu_mask(cpu, downed_cpus) {
+                err = cpu_up(cpu);
+                if (!err)
+                        pr_info(NAME "enabled CPU%d.\n", cpu);
+                else
+                        pr_err(NAME "cannot re-enable CPU%d: %d\n", cpu, err);
+        }
+}
+
+#else /* !CONFIG_HOTPLUG_CPU */
+static void enter_uniprocessor(void)
+{
+        if (num_online_cpus() > 1)
+                pr_warning(NAME "multiple CPUs are online, may miss events. "
+                        "Suggest booting with maxcpus=1 kernel argument.\n");
+}
+
+static void leave_uniprocessor(void)
+{
+}
+#endif
+
+#if 0 /* XXX: out of order */
+static struct file_operations fops_marker = {
+        .owner =        THIS_MODULE,
+        .write =        write_marker
+};
+#endif
+
+void enable_mmiotrace(void)
+{
+        mutex_lock(&mmiotrace_mutex);
+        if (is_enabled())
+                goto out;
+
+#if 0 /* XXX: tracing does not support text entries */
+        marker_file = debugfs_create_file("marker", 0660, dir, NULL,
+                                                                &fops_marker);
+        if (!marker_file)
+                pr_err(NAME "marker file creation failed.\n");
+#endif
+
+        if (nommiotrace)
+                pr_info(NAME "MMIO tracing disabled.\n");
+        enter_uniprocessor();
+        spin_lock_irq(&trace_lock);
+        atomic_inc(&mmiotrace_enabled);
+        spin_unlock_irq(&trace_lock);
+        pr_info(NAME "enabled.\n");
+out:
+        mutex_unlock(&mmiotrace_mutex);
+}
+
+void disable_mmiotrace(void)
+{
+        mutex_lock(&mmiotrace_mutex);
+        if (!is_enabled())
+                goto out;
+
+        spin_lock_irq(&trace_lock);
+        atomic_dec(&mmiotrace_enabled);
+        BUG_ON(is_enabled());
+        spin_unlock_irq(&trace_lock);
+
+        clear_trace_list(); /* guarantees: no more kmmio callbacks */
+        leave_uniprocessor();
+        if (marker_file) {
+                debugfs_remove(marker_file);
+                marker_file = NULL;
+        }
+
+        pr_info(NAME "disabled.\n");
+out:
+        mutex_unlock(&mmiotrace_mutex);
+}
diff --git a/arch/x86/mm/numa_64.c b/arch/x86/mm/numa_64.c
index c5066d519e5d..b432d5781773 100644
--- a/arch/x86/mm/numa_64.c
+++ b/arch/x86/mm/numa_64.c
@@ -27,30 +27,17 @@
 struct pglist_data *node_data[MAX_NUMNODES] __read_mostly;
 EXPORT_SYMBOL(node_data);
 
-bootmem_data_t plat_node_bdata[MAX_NUMNODES];
+static bootmem_data_t plat_node_bdata[MAX_NUMNODES];
 
 struct memnode memnode;
 
-#ifdef CONFIG_SMP
-int x86_cpu_to_node_map_init[NR_CPUS] = {
-        [0 ... NR_CPUS-1] = NUMA_NO_NODE
-};
-void *x86_cpu_to_node_map_early_ptr;
-EXPORT_SYMBOL(x86_cpu_to_node_map_early_ptr);
-#endif
-DEFINE_PER_CPU(int, x86_cpu_to_node_map) = NUMA_NO_NODE;
-EXPORT_PER_CPU_SYMBOL(x86_cpu_to_node_map);
-
 s16 apicid_to_node[MAX_LOCAL_APIC] __cpuinitdata = {
         [0 ... MAX_LOCAL_APIC-1] = NUMA_NO_NODE
 };
 
-cpumask_t node_to_cpumask_map[MAX_NUMNODES] __read_mostly;
-EXPORT_SYMBOL(node_to_cpumask_map);
-
 int numa_off __initdata;
-unsigned long __initdata nodemap_addr;
-unsigned long __initdata nodemap_size;
+static unsigned long __initdata nodemap_addr;
+static unsigned long __initdata nodemap_size;
 
 /*
  * Given a shift value, try to populate memnodemap[]
@@ -99,7 +86,7 @@ static int __init allocate_cachealigned_memnodemap(void)
 
         addr = 0x8000;
         nodemap_size = round_up(sizeof(s16) * memnodemapsize, L1_CACHE_BYTES);
-        nodemap_addr = find_e820_area(addr, end_pfn<<PAGE_SHIFT,
+        nodemap_addr = find_e820_area(addr, max_pfn<<PAGE_SHIFT,
                                       nodemap_size, L1_CACHE_BYTES);
         if (nodemap_addr == -1UL) {
                 printk(KERN_ERR
@@ -192,7 +179,7 @@ static void * __init early_node_mem(int nodeid, unsigned long start,
 void __init setup_node_bootmem(int nodeid, unsigned long start,
                                unsigned long end)
 {
-        unsigned long start_pfn, end_pfn, bootmap_pages, bootmap_size;
+        unsigned long start_pfn, last_pfn, bootmap_pages, bootmap_size;
         unsigned long bootmap_start, nodedata_phys;
         void *bootmap;
         const int pgdat_size = round_up(sizeof(pg_data_t), PAGE_SIZE);
@@ -204,7 +191,7 @@ void __init setup_node_bootmem(int nodeid, unsigned long start,
                start, end);
 
         start_pfn = start >> PAGE_SHIFT;
-        end_pfn = end >> PAGE_SHIFT;
+        last_pfn = end >> PAGE_SHIFT;
 
         node_data[nodeid] = early_node_mem(nodeid, start, end, pgdat_size,
                                            SMP_CACHE_BYTES);
@@ -217,7 +204,7 @@ void __init setup_node_bootmem(int nodeid, unsigned long start,
         memset(NODE_DATA(nodeid), 0, sizeof(pg_data_t));
         NODE_DATA(nodeid)->bdata = &plat_node_bdata[nodeid];
         NODE_DATA(nodeid)->node_start_pfn = start_pfn;
-        NODE_DATA(nodeid)->node_spanned_pages = end_pfn - start_pfn;
+        NODE_DATA(nodeid)->node_spanned_pages = last_pfn - start_pfn;
 
         /*
          * Find a place for the bootmem map
@@ -226,14 +213,14 @@ void __init setup_node_bootmem(int nodeid, unsigned long start,
          * early_node_mem will get that with find_e820_area instead
          * of alloc_bootmem, that could clash with reserved range
          */
-        bootmap_pages = bootmem_bootmap_pages(end_pfn - start_pfn);
+        bootmap_pages = bootmem_bootmap_pages(last_pfn - start_pfn);
         nid = phys_to_nid(nodedata_phys);
         if (nid == nodeid)
                 bootmap_start = round_up(nodedata_phys + pgdat_size, PAGE_SIZE);
         else
                 bootmap_start = round_up(start, PAGE_SIZE);
         /*
-         * SMP_CAHCE_BYTES could be enough, but init_bootmem_node like
+         * SMP_CACHE_BYTES could be enough, but init_bootmem_node like
          * to use that to align to PAGE_SIZE
          */
         bootmap = early_node_mem(nodeid, bootmap_start, end,
@@ -248,7 +235,7 @@ void __init setup_node_bootmem(int nodeid, unsigned long start,
 
         bootmap_size = init_bootmem_node(NODE_DATA(nodeid),
                                          bootmap_start >> PAGE_SHIFT,
-                                         start_pfn, end_pfn);
+                                         start_pfn, last_pfn);
 
         printk(KERN_INFO "  bootmap [%016lx -  %016lx] pages %lx\n",
                  bootmap_start, bootmap_start + bootmap_size - 1,
@@ -309,7 +296,7 @@ void __init numa_init_array(void)
 
 #ifdef CONFIG_NUMA_EMU
 /* Numa emulation */
-char *cmdline __initdata;
+static char *cmdline __initdata;
 
 /*
  * Setups up nid to range from addr to addr + size.  If the end
@@ -413,15 +400,15 @@ static int __init split_nodes_by_size(struct bootnode *nodes, u64 *addr,
 }
 
 /*
- * Sets up the system RAM area from start_pfn to end_pfn according to the
+ * Sets up the system RAM area from start_pfn to last_pfn according to the
  * numa=fake command-line option.
  */
 static struct bootnode nodes[MAX_NUMNODES] __initdata;
 
-static int __init numa_emulation(unsigned long start_pfn, unsigned long end_pfn)
+static int __init numa_emulation(unsigned long start_pfn, unsigned long last_pfn)
 {
         u64 size, addr = start_pfn << PAGE_SHIFT;
-        u64 max_addr = end_pfn << PAGE_SHIFT;
+        u64 max_addr = last_pfn << PAGE_SHIFT;
         int num_nodes = 0, num = 0, coeff_flag, coeff = -1, i;
 
         memset(&nodes, 0, sizeof(nodes));
@@ -527,7 +514,7 @@ out:
 }
 #endif /* CONFIG_NUMA_EMU */
 
-void __init numa_initmem_init(unsigned long start_pfn, unsigned long end_pfn)
+void __init initmem_init(unsigned long start_pfn, unsigned long last_pfn)
 {
         int i;
 
@@ -535,7 +522,7 @@ void __init numa_initmem_init(unsigned long start_pfn, unsigned long end_pfn)
         nodes_clear(node_online_map);
 
 #ifdef CONFIG_NUMA_EMU
-        if (cmdline && !numa_emulation(start_pfn, end_pfn))
+        if (cmdline && !numa_emulation(start_pfn, last_pfn))
                 return;
         nodes_clear(node_possible_map);
         nodes_clear(node_online_map);
@@ -543,7 +530,7 @@ void __init numa_initmem_init(unsigned long start_pfn, unsigned long end_pfn)
 
 #ifdef CONFIG_ACPI_NUMA
         if (!numa_off && !acpi_scan_nodes(start_pfn << PAGE_SHIFT,
-                                          end_pfn << PAGE_SHIFT))
+                                          last_pfn << PAGE_SHIFT))
                 return;
         nodes_clear(node_possible_map);
         nodes_clear(node_online_map);
@@ -551,7 +538,7 @@ void __init numa_initmem_init(unsigned long start_pfn, unsigned long end_pfn)
 
 #ifdef CONFIG_K8_NUMA
         if (!numa_off && !k8_scan_nodes(start_pfn<<PAGE_SHIFT,
-                                        end_pfn<<PAGE_SHIFT))
+                                        last_pfn<<PAGE_SHIFT))
                 return;
         nodes_clear(node_possible_map);
         nodes_clear(node_online_map);
@@ -561,7 +548,7 @@ void __init numa_initmem_init(unsigned long start_pfn, unsigned long end_pfn)
 
         printk(KERN_INFO "Faking a node at %016lx-%016lx\n",
                start_pfn << PAGE_SHIFT,
-               end_pfn << PAGE_SHIFT);
+               last_pfn << PAGE_SHIFT);
         /* setup dummy node covering all memory */
         memnode_shift = 63;
         memnodemap = memnode.embedded_map;
@@ -570,29 +557,8 @@ void __init numa_initmem_init(unsigned long start_pfn, unsigned long end_pfn)
         node_set(0, node_possible_map);
         for (i = 0; i < NR_CPUS; i++)
                 numa_set_node(i, 0);
-        /* cpumask_of_cpu() may not be available during early startup */
-        memset(&node_to_cpumask_map[0], 0, sizeof(node_to_cpumask_map[0]));
-        cpu_set(0, node_to_cpumask_map[0]);
-        e820_register_active_regions(0, start_pfn, end_pfn);
-        setup_node_bootmem(0, start_pfn << PAGE_SHIFT, end_pfn << PAGE_SHIFT);
-}
-
-__cpuinit void numa_add_cpu(int cpu)
-{
-        set_bit(cpu,
-                (unsigned long *)&node_to_cpumask_map[early_cpu_to_node(cpu)]);
-}
-
-void __cpuinit numa_set_node(int cpu, int node)
-{
-        int *cpu_to_node_map = x86_cpu_to_node_map_early_ptr;
-
-        if(cpu_to_node_map)
-                cpu_to_node_map[cpu] = node;
-        else if(per_cpu_offset(cpu))
-                per_cpu(x86_cpu_to_node_map, cpu) = node;
-        else
-                Dprintk(KERN_INFO "Setting node for non-present cpu %d\n", cpu);
+        e820_register_active_regions(0, start_pfn, last_pfn);
+        setup_node_bootmem(0, start_pfn << PAGE_SHIFT, last_pfn << PAGE_SHIFT);
 }
 
 unsigned long __init numa_free_all_bootmem(void)
@@ -613,7 +579,7 @@ void __init paging_init(void)
         memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
         max_zone_pfns[ZONE_DMA] = MAX_DMA_PFN;
         max_zone_pfns[ZONE_DMA32] = MAX_DMA32_PFN;
-        max_zone_pfns[ZONE_NORMAL] = end_pfn;
+        max_zone_pfns[ZONE_NORMAL] = max_pfn;
 
         sparse_memory_present_with_active_regions(MAX_NUMNODES);
         sparse_init();
@@ -641,6 +607,7 @@ static __init int numa_setup(char *opt)
 }
 early_param("numa", numa_setup);
 
+#ifdef CONFIG_NUMA
 /*
  * Setup early cpu_to_node.
  *
@@ -652,14 +619,19 @@ early_param("numa", numa_setup);
  * is already initialized in a round robin manner at numa_init_array,
  * prior to this call, and this initialization is good enough
  * for the fake NUMA cases.
+ *
+ * Called before the per_cpu areas are setup.
  */
 void __init init_cpu_to_node(void)
 {
-        int i;
+        int cpu;
+        u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid);
 
-        for (i = 0; i < NR_CPUS; i++) {
+        BUG_ON(cpu_to_apicid == NULL);
+
+        for_each_possible_cpu(cpu) {
                 int node;
-                u16 apicid = x86_cpu_to_apicid_init[i];
+                u16 apicid = cpu_to_apicid[cpu];
 
                 if (apicid == BAD_APICID)
                         continue;
@@ -668,8 +640,9 @@ void __init init_cpu_to_node(void)
                         continue;
                 if (!node_online(node))
                         continue;
-                numa_set_node(i, node);
+                numa_set_node(cpu, node);
         }
 }
+#endif
 
 
diff --git a/arch/x86/mm/pageattr-test.c b/arch/x86/mm/pageattr-test.c
index 75f1b109aae8..0dcd42eb94e6 100644
--- a/arch/x86/mm/pageattr-test.c
+++ b/arch/x86/mm/pageattr-test.c
@@ -1,8 +1,8 @@
 /*
  * self test for change_page_attr.
  *
- * Clears the global bit on random pages in the direct mapping, then reverts
- * and compares page tables forwards and afterwards.
+ * Clears the a test pte bit on random pages in the direct mapping,
+ * then reverts and compares page tables forwards and afterwards.
  */
 #include <linux/bootmem.h>
 #include <linux/kthread.h>
@@ -32,6 +32,13 @@ enum {
         GPS                     = (1<<30)
 };
 
+#define PAGE_TESTBIT    __pgprot(_PAGE_UNUSED1)
+
+static int pte_testbit(pte_t pte)
+{
+        return pte_flags(pte) & _PAGE_UNUSED1;
+}
+
 struct split_state {
         long lpg, gpg, spg, exec;
         long min_exec, max_exec;
@@ -165,15 +172,14 @@ static int pageattr_test(void)
                         continue;
                 }
 
-                err = change_page_attr_clear(addr[i], len[i],
-                                               __pgprot(_PAGE_GLOBAL));
+                err = change_page_attr_set(addr[i], len[i], PAGE_TESTBIT);
                 if (err < 0) {
                         printk(KERN_ERR "CPA %d failed %d\n", i, err);
                         failed++;
                 }
 
                 pte = lookup_address(addr[i], &level);
-                if (!pte || pte_global(*pte) || pte_huge(*pte)) {
+                if (!pte || !pte_testbit(*pte) || pte_huge(*pte)) {
                         printk(KERN_ERR "CPA %lx: bad pte %Lx\n", addr[i],
                                 pte ? (u64)pte_val(*pte) : 0ULL);
                         failed++;
@@ -198,14 +204,13 @@ static int pageattr_test(void)
                         failed++;
                         continue;
                 }
-                err = change_page_attr_set(addr[i], len[i],
-                                             __pgprot(_PAGE_GLOBAL));
+                err = change_page_attr_clear(addr[i], len[i], PAGE_TESTBIT);
                 if (err < 0) {
                         printk(KERN_ERR "CPA reverting failed: %d\n", err);
                         failed++;
                 }
                 pte = lookup_address(addr[i], &level);
-                if (!pte || !pte_global(*pte)) {
+                if (!pte || pte_testbit(*pte)) {
                         printk(KERN_ERR "CPA %lx: bad pte after revert %Lx\n",
                                 addr[i], pte ? (u64)pte_val(*pte) : 0ULL);
                         failed++;
diff --git a/arch/x86/mm/pageattr.c b/arch/x86/mm/pageattr.c
index 60bcb5b6a37e..47f4e2e4a096 100644
--- a/arch/x86/mm/pageattr.c
+++ b/arch/x86/mm/pageattr.c
@@ -34,6 +34,41 @@ struct cpa_data {
         unsigned        force_split : 1;
 };
 
+#ifdef CONFIG_PROC_FS
+static unsigned long direct_pages_count[PG_LEVEL_NUM];
+
+void update_page_count(int level, unsigned long pages)
+{
+        unsigned long flags;
+
+        /* Protect against CPA */
+        spin_lock_irqsave(&pgd_lock, flags);
+        direct_pages_count[level] += pages;
+        spin_unlock_irqrestore(&pgd_lock, flags);
+}
+
+static void split_page_count(int level)
+{
+        direct_pages_count[level]--;
+        direct_pages_count[level - 1] += PTRS_PER_PTE;
+}
+
+int arch_report_meminfo(char *page)
+{
+        int n = sprintf(page, "DirectMap4k:  %8lu\n"
+                        "DirectMap2M:  %8lu\n",
+                        direct_pages_count[PG_LEVEL_4K],
+                        direct_pages_count[PG_LEVEL_2M]);
+#ifdef CONFIG_X86_64
+        n += sprintf(page + n, "DirectMap1G:  %8lu\n",
+                     direct_pages_count[PG_LEVEL_1G]);
+#endif
+        return n;
+}
+#else
+static inline void split_page_count(int level) { }
+#endif
+
 #ifdef CONFIG_X86_64
 
 static inline unsigned long highmap_start_pfn(void)
@@ -227,6 +262,7 @@ pte_t *lookup_address(unsigned long address, unsigned int *level)
 
         return pte_offset_kernel(pmd, address);
 }
+EXPORT_SYMBOL_GPL(lookup_address);
 
 /*
  * Set the new pmd in all the pgds we know about:
@@ -500,6 +536,16 @@ static int split_large_page(pte_t *kpte, unsigned long address)
         for (i = 0; i < PTRS_PER_PTE; i++, pfn += pfninc)
                 set_pte(&pbase[i], pfn_pte(pfn, ref_prot));
 
+        if (address >= (unsigned long)__va(0) &&
+                address < (unsigned long)__va(max_low_pfn_mapped << PAGE_SHIFT))
+                split_page_count(level);
+
+#ifdef CONFIG_X86_64
+        if (address >= (unsigned long)__va(1UL<<32) &&
+                address < (unsigned long)__va(max_pfn_mapped << PAGE_SHIFT))
+                split_page_count(level);
+#endif
+
         /*
          * Install the new, split up pagetable. Important details here:
          *
@@ -613,15 +659,24 @@ static int cpa_process_alias(struct cpa_data *cpa)
         struct cpa_data alias_cpa;
         int ret = 0;
 
-        if (cpa->pfn > max_pfn_mapped)
+        if (cpa->pfn >= max_pfn_mapped)
                 return 0;
 
+#ifdef CONFIG_X86_64
+        if (cpa->pfn >= max_low_pfn_mapped && cpa->pfn < (1UL<<(32-PAGE_SHIFT)))
+                return 0;
+#endif
         /*
          * No need to redo, when the primary call touched the direct
          * mapping already:
          */
-        if (!within(cpa->vaddr, PAGE_OFFSET,
-                    PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT))) {
+        if (!(within(cpa->vaddr, PAGE_OFFSET,
+                    PAGE_OFFSET + (max_low_pfn_mapped << PAGE_SHIFT))
+#ifdef CONFIG_X86_64
+                || within(cpa->vaddr, PAGE_OFFSET + (1UL<<32),
+                    PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT))
+#endif
+        )) {
 
                 alias_cpa = *cpa;
                 alias_cpa.vaddr = (unsigned long) __va(cpa->pfn << PAGE_SHIFT);
@@ -805,7 +860,7 @@ int _set_memory_wc(unsigned long addr, int numpages)
 
 int set_memory_wc(unsigned long addr, int numpages)
 {
-        if (!pat_wc_enabled)
+        if (!pat_enabled)
                 return set_memory_uc(addr, numpages);
 
         if (reserve_memtype(addr, addr + numpages * PAGE_SIZE,
diff --git a/arch/x86/mm/pat.c b/arch/x86/mm/pat.c
index 06b7a1c90fb8..d4585077977a 100644
--- a/arch/x86/mm/pat.c
+++ b/arch/x86/mm/pat.c
@@ -26,11 +26,11 @@
 #include <asm/io.h>
 
 #ifdef CONFIG_X86_PAT
-int __read_mostly pat_wc_enabled = 1;
+int __read_mostly pat_enabled = 1;
 
 void __cpuinit pat_disable(char *reason)
 {
-        pat_wc_enabled = 0;
+        pat_enabled = 0;
         printk(KERN_INFO "%s\n", reason);
 }
 
@@ -42,6 +42,19 @@ static int __init nopat(char *str)
 early_param("nopat", nopat);
 #endif
 
+
+static int debug_enable;
+static int __init pat_debug_setup(char *str)
+{
+        debug_enable = 1;
+        return 0;
+}
+__setup("debugpat", pat_debug_setup);
+
+#define dprintk(fmt, arg...) \
+        do { if (debug_enable) printk(KERN_INFO fmt, ##arg); } while (0)
+
+
 static u64 __read_mostly boot_pat_state;
 
 enum {
@@ -53,24 +66,25 @@ enum {
         PAT_UC_MINUS = 7,       /* UC, but can be overriden by MTRR */
 };
 
-#define PAT(x,y)        ((u64)PAT_ ## y << ((x)*8))
+#define PAT(x, y)       ((u64)PAT_ ## y << ((x)*8))
 
 void pat_init(void)
 {
         u64 pat;
 
-        if (!pat_wc_enabled)
+        if (!pat_enabled)
                 return;
 
         /* Paranoia check. */
-        if (!cpu_has_pat) {
-                printk(KERN_ERR "PAT enabled, but CPU feature cleared\n");
+        if (!cpu_has_pat && boot_pat_state) {
                 /*
-                 * Panic if this happens on the secondary CPU, and we
+                 * If this happens we are on a secondary CPU, but
                  * switched to PAT on the boot CPU. We have no way to
                  * undo PAT.
-                */
-                BUG_ON(boot_pat_state);
+                 */
+                printk(KERN_ERR "PAT enabled, "
+                       "but not supported by secondary CPU\n");
+                BUG();
         }
 
         /* Set PWT to Write-Combining. All other bits stay the same */
@@ -86,8 +100,8 @@ void pat_init(void)
          *      011 UC          _PAGE_CACHE_UC
          * PAT bit unused
          */
-        pat = PAT(0,WB) | PAT(1,WC) | PAT(2,UC_MINUS) | PAT(3,UC) |
-              PAT(4,WB) | PAT(5,WC) | PAT(6,UC_MINUS) | PAT(7,UC);
+        pat = PAT(0, WB) | PAT(1, WC) | PAT(2, UC_MINUS) | PAT(3, UC) |
+              PAT(4, WB) | PAT(5, WC) | PAT(6, UC_MINUS) | PAT(7, UC);
 
         /* Boot CPU check */
         if (!boot_pat_state)
@@ -103,11 +117,11 @@ void pat_init(void)
 static char *cattr_name(unsigned long flags)
 {
         switch (flags & _PAGE_CACHE_MASK) {
-                case _PAGE_CACHE_UC:            return "uncached";
-                case _PAGE_CACHE_UC_MINUS:      return "uncached-minus";
-                case _PAGE_CACHE_WB:            return "write-back";
-                case _PAGE_CACHE_WC:            return "write-combining";
-                default:                        return "broken";
+        case _PAGE_CACHE_UC:            return "uncached";
+        case _PAGE_CACHE_UC_MINUS:      return "uncached-minus";
+        case _PAGE_CACHE_WB:            return "write-back";
+        case _PAGE_CACHE_WC:            return "write-combining";
+        default:                        return "broken";
         }
 }
 
@@ -145,47 +159,50 @@ static DEFINE_SPINLOCK(memtype_lock); 	/* protects memtype list */
  * The intersection is based on "Effective Memory Type" tables in IA-32
  * SDM vol 3a
  */
-static int pat_x_mtrr_type(u64 start, u64 end, unsigned long prot,
-                                unsigned long *ret_prot)
+static unsigned long pat_x_mtrr_type(u64 start, u64 end, unsigned long req_type)
 {
-        unsigned long pat_type;
-        u8 mtrr_type;
-
-        pat_type = prot & _PAGE_CACHE_MASK;
-        prot &= (~_PAGE_CACHE_MASK);
-
-        /*
-         * We return the PAT request directly for types where PAT takes
-         * precedence with respect to MTRR and for UC_MINUS.
-         * Consistency checks with other PAT requests is done later
-         * while going through memtype list.
-         */
-        if (pat_type == _PAGE_CACHE_WC) {
-                *ret_prot = prot | _PAGE_CACHE_WC;
-                return 0;
-        } else if (pat_type == _PAGE_CACHE_UC_MINUS) {
-                *ret_prot = prot | _PAGE_CACHE_UC_MINUS;
-                return 0;
-        } else if (pat_type == _PAGE_CACHE_UC) {
-                *ret_prot = prot | _PAGE_CACHE_UC;
-                return 0;
-        }
-
         /*
          * Look for MTRR hint to get the effective type in case where PAT
          * request is for WB.
          */
-        mtrr_type = mtrr_type_lookup(start, end);
+        if (req_type == _PAGE_CACHE_WB) {
+                u8 mtrr_type;
+
+                mtrr_type = mtrr_type_lookup(start, end);
+                if (mtrr_type == MTRR_TYPE_UNCACHABLE)
+                        return _PAGE_CACHE_UC;
+                if (mtrr_type == MTRR_TYPE_WRCOMB)
+                        return _PAGE_CACHE_WC;
+        }
 
-        if (mtrr_type == MTRR_TYPE_UNCACHABLE) {
-                *ret_prot = prot | _PAGE_CACHE_UC;
-        } else if (mtrr_type == MTRR_TYPE_WRCOMB) {
-                *ret_prot = prot | _PAGE_CACHE_WC;
-        } else {
-                *ret_prot = prot | _PAGE_CACHE_WB;
+        return req_type;
+}
+
+static int chk_conflict(struct memtype *new, struct memtype *entry,
+                        unsigned long *type)
+{
+        if (new->type != entry->type) {
+                if (type) {
+                        new->type = entry->type;
+                        *type = entry->type;
+                } else
+                        goto conflict;
         }
 
+         /* check overlaps with more than one entry in the list */
+        list_for_each_entry_continue(entry, &memtype_list, nd) {
+                if (new->end <= entry->start)
+                        break;
+                else if (new->type != entry->type)
+                        goto conflict;
+        }
         return 0;
+
+ conflict:
+        printk(KERN_INFO "%s:%d conflicting memory types "
+               "%Lx-%Lx %s<->%s\n", current->comm, current->pid, new->start,
+               new->end, cattr_name(new->type), cattr_name(entry->type));
+        return -EBUSY;
 }
 
 /*
@@ -198,37 +215,36 @@ static int pat_x_mtrr_type(u64 start, u64 end, unsigned long prot,
  * req_type will have a special case value '-1', when requester want to inherit
  * the memory type from mtrr (if WB), existing PAT, defaulting to UC_MINUS.
  *
- * If ret_type is NULL, function will return an error if it cannot reserve the
- * region with req_type. If ret_type is non-null, function will return
- * available type in ret_type in case of no error. In case of any error
+ * If new_type is NULL, function will return an error if it cannot reserve the
+ * region with req_type. If new_type is non-NULL, function will return
+ * available type in new_type in case of no error. In case of any error
  * it will return a negative return value.
  */
 int reserve_memtype(u64 start, u64 end, unsigned long req_type,
-                        unsigned long *ret_type)
+                        unsigned long *new_type)
 {
-        struct memtype *new_entry = NULL;
-        struct memtype *parse;
+        struct memtype *new, *entry;
         unsigned long actual_type;
+        struct list_head *where;
         int err = 0;
 
-        /* Only track when pat_wc_enabled */
-        if (!pat_wc_enabled) {
+        BUG_ON(start >= end); /* end is exclusive */
+
+        if (!pat_enabled) {
                 /* This is identical to page table setting without PAT */
-                if (ret_type) {
-                        if (req_type == -1) {
-                                *ret_type = _PAGE_CACHE_WB;
-                        } else {
-                                *ret_type = req_type;
-                        }
+                if (new_type) {
+                        if (req_type == -1)
+                                *new_type = _PAGE_CACHE_WB;
+                        else
+                                *new_type = req_type & _PAGE_CACHE_MASK;
                 }
                 return 0;
         }
 
         /* Low ISA region is always mapped WB in page table. No need to track */
-        if (start >= ISA_START_ADDRESS && (end - 1) <= ISA_END_ADDRESS) {
-                if (ret_type)
-                        *ret_type = _PAGE_CACHE_WB;
-
+        if (is_ISA_range(start, end - 1)) {
+                if (new_type)
+                        *new_type = _PAGE_CACHE_WB;
                 return 0;
         }
 
@@ -241,206 +257,92 @@ int reserve_memtype(u64 start, u64 end, unsigned long req_type,
                  */
                 u8 mtrr_type = mtrr_type_lookup(start, end);
 
-                if (mtrr_type == MTRR_TYPE_WRBACK) {
-                        req_type = _PAGE_CACHE_WB;
+                if (mtrr_type == MTRR_TYPE_WRBACK)
                         actual_type = _PAGE_CACHE_WB;
-                } else {
-                        req_type = _PAGE_CACHE_UC_MINUS;
+                else
                         actual_type = _PAGE_CACHE_UC_MINUS;
-                }
-        } else {
-                req_type &= _PAGE_CACHE_MASK;
-                err = pat_x_mtrr_type(start, end, req_type, &actual_type);
-        }
-
-        if (err) {
-                if (ret_type)
-                        *ret_type = actual_type;
-
-                return -EINVAL;
-        }
+        } else
+                actual_type = pat_x_mtrr_type(start, end,
+                                              req_type & _PAGE_CACHE_MASK);
 
-        new_entry  = kmalloc(sizeof(struct memtype), GFP_KERNEL);
-        if (!new_entry)
+        new  = kmalloc(sizeof(struct memtype), GFP_KERNEL);
+        if (!new)
                 return -ENOMEM;
 
-        new_entry->start = start;
-        new_entry->end = end;
-        new_entry->type = actual_type;
+        new->start = start;
+        new->end = end;
+        new->type = actual_type;
 
-        if (ret_type)
-                *ret_type = actual_type;
+        if (new_type)
+                *new_type = actual_type;
 
         spin_lock(&memtype_lock);
 
         /* Search for existing mapping that overlaps the current range */
-        list_for_each_entry(parse, &memtype_list, nd) {
-                struct memtype *saved_ptr;
-
-                if (parse->start >= end) {
-                        pr_debug("New Entry\n");
-                        list_add(&new_entry->nd, parse->nd.prev);
-                        new_entry = NULL;
+        where = NULL;
+        list_for_each_entry(entry, &memtype_list, nd) {
+                if (end <= entry->start) {
+                        where = entry->nd.prev;
                         break;
-                }
-
-                if (start <= parse->start && end >= parse->start) {
-                        if (actual_type != parse->type && ret_type) {
-                                actual_type = parse->type;
-                                *ret_type = actual_type;
-                                new_entry->type = actual_type;
-                        }
-
-                        if (actual_type != parse->type) {
-                                printk(
-                KERN_INFO "%s:%d conflicting memory types %Lx-%Lx %s<->%s\n",
-                                        current->comm, current->pid,
-                                        start, end,
-                                        cattr_name(actual_type),
-                                        cattr_name(parse->type));
-                                err = -EBUSY;
-                                break;
+                } else if (start <= entry->start) { /* end > entry->start */
+                        err = chk_conflict(new, entry, new_type);
+                        if (!err) {
+                                dprintk("Overlap at 0x%Lx-0x%Lx\n",
+                                        entry->start, entry->end);
+                                where = entry->nd.prev;
                         }
-
-                        saved_ptr = parse;
-                        /*
-                         * Check to see whether the request overlaps more
-                         * than one entry in the list
-                         */
-                        list_for_each_entry_continue(parse, &memtype_list, nd) {
-                                if (end <= parse->start) {
-                                        break;
-                                }
-
-                                if (actual_type != parse->type) {
-                                        printk(
-                KERN_INFO "%s:%d conflicting memory types %Lx-%Lx %s<->%s\n",
-                                                current->comm, current->pid,
-                                                start, end,
-                                                cattr_name(actual_type),
-                                                cattr_name(parse->type));
-                                        err = -EBUSY;
-                                        break;
-                                }
-                        }
-
-                        if (err) {
-                                break;
-                        }
-
-                        pr_debug("Overlap at 0x%Lx-0x%Lx\n",
-                               saved_ptr->start, saved_ptr->end);
-                        /* No conflict. Go ahead and add this new entry */
-                        list_add(&new_entry->nd, saved_ptr->nd.prev);
-                        new_entry = NULL;
                         break;
-                }
-
-                if (start < parse->end) {
-                        if (actual_type != parse->type && ret_type) {
-                                actual_type = parse->type;
-                                *ret_type = actual_type;
-                                new_entry->type = actual_type;
-                        }
-
-                        if (actual_type != parse->type) {
-                                printk(
-                KERN_INFO "%s:%d conflicting memory types %Lx-%Lx %s<->%s\n",
-                                        current->comm, current->pid,
-                                        start, end,
-                                        cattr_name(actual_type),
-                                        cattr_name(parse->type));
-                                err = -EBUSY;
-                                break;
-                        }
-
-                        saved_ptr = parse;
-                        /*
-                         * Check to see whether the request overlaps more
-                         * than one entry in the list
-                         */
-                        list_for_each_entry_continue(parse, &memtype_list, nd) {
-                                if (end <= parse->start) {
-                                        break;
-                                }
-
-                                if (actual_type != parse->type) {
-                                        printk(
-                KERN_INFO "%s:%d conflicting memory types %Lx-%Lx %s<->%s\n",
-                                                current->comm, current->pid,
-                                                start, end,
-                                                cattr_name(actual_type),
-                                                cattr_name(parse->type));
-                                        err = -EBUSY;
-                                        break;
-                                }
-                        }
-
-                        if (err) {
-                                break;
+                } else if (start < entry->end) { /* start > entry->start */
+                        err = chk_conflict(new, entry, new_type);
+                        if (!err) {
+                                dprintk("Overlap at 0x%Lx-0x%Lx\n",
+                                        entry->start, entry->end);
+                                where = &entry->nd;
                         }
-
-                        pr_debug(KERN_INFO "Overlap at 0x%Lx-0x%Lx\n",
-                                 saved_ptr->start, saved_ptr->end);
-                        /* No conflict. Go ahead and add this new entry */
-                        list_add(&new_entry->nd, &saved_ptr->nd);
-                        new_entry = NULL;
                         break;
                 }
         }
 
         if (err) {
-                printk(KERN_INFO
-        "reserve_memtype failed 0x%Lx-0x%Lx, track %s, req %s\n",
-                        start, end, cattr_name(new_entry->type),
-                        cattr_name(req_type));
-                kfree(new_entry);
+                printk(KERN_INFO "reserve_memtype failed 0x%Lx-0x%Lx, "
+                       "track %s, req %s\n",
+                       start, end, cattr_name(new->type), cattr_name(req_type));
+                kfree(new);
                 spin_unlock(&memtype_lock);
                 return err;
         }
 
-        if (new_entry) {
-                /* No conflict. Not yet added to the list. Add to the tail */
-                list_add_tail(&new_entry->nd, &memtype_list);
-                pr_debug("New Entry\n");
-        }
-
-        if (ret_type) {
-                pr_debug(
-        "reserve_memtype added 0x%Lx-0x%Lx, track %s, req %s, ret %s\n",
-                        start, end, cattr_name(actual_type),
-                        cattr_name(req_type), cattr_name(*ret_type));
-        } else {
-                pr_debug(
-        "reserve_memtype added 0x%Lx-0x%Lx, track %s, req %s\n",
-                        start, end, cattr_name(actual_type),
-                        cattr_name(req_type));
-        }
+        if (where)
+                list_add(&new->nd, where);
+        else
+                list_add_tail(&new->nd, &memtype_list);
 
         spin_unlock(&memtype_lock);
+
+        dprintk("reserve_memtype added 0x%Lx-0x%Lx, track %s, req %s, ret %s\n",
+                start, end, cattr_name(new->type), cattr_name(req_type),
+                new_type ? cattr_name(*new_type) : "-");
+
         return err;
 }
 
 int free_memtype(u64 start, u64 end)
 {
-        struct memtype *ml;
+        struct memtype *entry;
         int err = -EINVAL;
 
-        /* Only track when pat_wc_enabled */
-        if (!pat_wc_enabled) {
+        if (!pat_enabled)
                 return 0;
-        }
 
         /* Low ISA region is always mapped WB. No need to track */
-        if (start >= ISA_START_ADDRESS && end <= ISA_END_ADDRESS) {
+        if (is_ISA_range(start, end - 1))
                 return 0;
-        }
 
         spin_lock(&memtype_lock);
-        list_for_each_entry(ml, &memtype_list, nd) {
-                if (ml->start == start && ml->end == end) {
-                        list_del(&ml->nd);
-                        kfree(ml);
+        list_for_each_entry(entry, &memtype_list, nd) {
+                if (entry->start == start && entry->end == end) {
+                        list_del(&entry->nd);
+                        kfree(entry);
                         err = 0;
                         break;
                 }
@@ -452,7 +354,7 @@ int free_memtype(u64 start, u64 end)
                         current->comm, current->pid, start, end);
         }
 
-        pr_debug("free_memtype request 0x%Lx-0x%Lx\n", start, end);
+        dprintk("free_memtype request 0x%Lx-0x%Lx\n", start, end);
         return err;
 }
 
@@ -521,12 +423,12 @@ int phys_mem_access_prot_allowed(struct file *file, unsigned long pfn,
          * caching for the high addresses through the KEN pin, but
          * we maintain the tradition of paranoia in this code.
          */
-        if (!pat_wc_enabled &&
-            ! ( test_bit(X86_FEATURE_MTRR, boot_cpu_data.x86_capability) ||
-                test_bit(X86_FEATURE_K6_MTRR, boot_cpu_data.x86_capability) ||
-                test_bit(X86_FEATURE_CYRIX_ARR, boot_cpu_data.x86_capability) ||
-                test_bit(X86_FEATURE_CENTAUR_MCR, boot_cpu_data.x86_capability)) &&
-           (pfn << PAGE_SHIFT) >= __pa(high_memory)) {
+        if (!pat_enabled &&
+            !(boot_cpu_has(X86_FEATURE_MTRR) ||
+              boot_cpu_has(X86_FEATURE_K6_MTRR) ||
+              boot_cpu_has(X86_FEATURE_CYRIX_ARR) ||
+              boot_cpu_has(X86_FEATURE_CENTAUR_MCR)) &&
+            (pfn << PAGE_SHIFT) >= __pa(high_memory)) {
                 flags = _PAGE_CACHE_UC;
         }
 #endif
@@ -547,8 +449,9 @@ int phys_mem_access_prot_allowed(struct file *file, unsigned long pfn,
         if (retval < 0)
                 return 0;
 
-        if (pfn <= max_pfn_mapped &&
-            ioremap_change_attr((unsigned long)__va(offset), size, flags) < 0) {
+        if (((pfn < max_low_pfn_mapped) ||
+             (pfn >= (1UL<<(32 - PAGE_SHIFT)) && pfn < max_pfn_mapped)) &&
+            ioremap_change_attr((unsigned long)__va(offset), size, flags) < 0) {
                 free_memtype(offset, offset + size);
                 printk(KERN_INFO
                 "%s:%d /dev/mem ioremap_change_attr failed %s for %Lx-%Lx\n",
@@ -586,4 +489,3 @@ void unmap_devmem(unsigned long pfn, unsigned long size, pgprot_t vma_prot)
 
         free_memtype(addr, addr + size);
 }
-
diff --git a/arch/x86/mm/pf_in.c b/arch/x86/mm/pf_in.c
new file mode 100644
index 000000000000..efa1911e20ca
--- /dev/null
+++ b/arch/x86/mm/pf_in.c
@@ -0,0 +1,489 @@
+/*
+ *  Fault Injection Test harness (FI)
+ *  Copyright (C) Intel Crop.
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  as published by the Free Software Foundation; either version 2
+ *  of the License, or (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307,
+ *  USA.
+ *
+ */
+
+/*  Id: pf_in.c,v 1.1.1.1 2002/11/12 05:56:32 brlock Exp
+ *  Copyright by Intel Crop., 2002
+ *  Louis Zhuang (louis.zhuang@intel.com)
+ *
+ *  Bjorn Steinbrink (B.Steinbrink@gmx.de), 2007
+ */
+
+#include <linux/module.h>
+#include <linux/ptrace.h> /* struct pt_regs */
+#include "pf_in.h"
+
+#ifdef __i386__
+/* IA32 Manual 3, 2-1 */
+static unsigned char prefix_codes[] = {
+        0xF0, 0xF2, 0xF3, 0x2E, 0x36, 0x3E, 0x26, 0x64,
+        0x65, 0x2E, 0x3E, 0x66, 0x67
+};
+/* IA32 Manual 3, 3-432*/
+static unsigned int reg_rop[] = {
+        0x8A, 0x8B, 0xB60F, 0xB70F, 0xBE0F, 0xBF0F
+};
+static unsigned int reg_wop[] = { 0x88, 0x89 };
+static unsigned int imm_wop[] = { 0xC6, 0xC7 };
+/* IA32 Manual 3, 3-432*/
+static unsigned int rw8[] = { 0x88, 0x8A, 0xC6 };
+static unsigned int rw32[] = {
+        0x89, 0x8B, 0xC7, 0xB60F, 0xB70F, 0xBE0F, 0xBF0F
+};
+static unsigned int mw8[] = { 0x88, 0x8A, 0xC6, 0xB60F, 0xBE0F };
+static unsigned int mw16[] = { 0xB70F, 0xBF0F };
+static unsigned int mw32[] = { 0x89, 0x8B, 0xC7 };
+static unsigned int mw64[] = {};
+#else /* not __i386__ */
+static unsigned char prefix_codes[] = {
+        0x66, 0x67, 0x2E, 0x3E, 0x26, 0x64, 0x65, 0x36,
+        0xF0, 0xF3, 0xF2,
+        /* REX Prefixes */
+        0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
+        0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f
+};
+/* AMD64 Manual 3, Appendix A*/
+static unsigned int reg_rop[] = {
+        0x8A, 0x8B, 0xB60F, 0xB70F, 0xBE0F, 0xBF0F
+};
+static unsigned int reg_wop[] = { 0x88, 0x89 };
+static unsigned int imm_wop[] = { 0xC6, 0xC7 };
+static unsigned int rw8[] = { 0xC6, 0x88, 0x8A };
+static unsigned int rw32[] = {
+        0xC7, 0x89, 0x8B, 0xB60F, 0xB70F, 0xBE0F, 0xBF0F
+};
+/* 8 bit only */
+static unsigned int mw8[] = { 0xC6, 0x88, 0x8A, 0xB60F, 0xBE0F };
+/* 16 bit only */
+static unsigned int mw16[] = { 0xB70F, 0xBF0F };
+/* 16 or 32 bit */
+static unsigned int mw32[] = { 0xC7 };
+/* 16, 32 or 64 bit */
+static unsigned int mw64[] = { 0x89, 0x8B };
+#endif /* not __i386__ */
+
+static int skip_prefix(unsigned char *addr, int *shorted, int *enlarged,
+                                                                int *rexr)
+{
+        int i;
+        unsigned char *p = addr;
+        *shorted = 0;
+        *enlarged = 0;
+        *rexr = 0;
+
+restart:
+        for (i = 0; i < ARRAY_SIZE(prefix_codes); i++) {
+                if (*p == prefix_codes[i]) {
+                        if (*p == 0x66)
+                                *shorted = 1;
+#ifdef __amd64__
+                        if ((*p & 0xf8) == 0x48)
+                                *enlarged = 1;
+                        if ((*p & 0xf4) == 0x44)
+                                *rexr = 1;
+#endif
+                        p++;
+                        goto restart;
+                }
+        }
+
+        return (p - addr);
+}
+
+static int get_opcode(unsigned char *addr, unsigned int *opcode)
+{
+        int len;
+
+        if (*addr == 0x0F) {
+                /* 0x0F is extension instruction */
+                *opcode = *(unsigned short *)addr;
+                len = 2;
+        } else {
+                *opcode = *addr;
+                len = 1;
+        }
+
+        return len;
+}
+
+#define CHECK_OP_TYPE(opcode, array, type) \
+        for (i = 0; i < ARRAY_SIZE(array); i++) { \
+                if (array[i] == opcode) { \
+                        rv = type; \
+                        goto exit; \
+                } \
+        }
+
+enum reason_type get_ins_type(unsigned long ins_addr)
+{
+        unsigned int opcode;
+        unsigned char *p;
+        int shorted, enlarged, rexr;
+        int i;
+        enum reason_type rv = OTHERS;
+
+        p = (unsigned char *)ins_addr;
+        p += skip_prefix(p, &shorted, &enlarged, &rexr);
+        p += get_opcode(p, &opcode);
+
+        CHECK_OP_TYPE(opcode, reg_rop, REG_READ);
+        CHECK_OP_TYPE(opcode, reg_wop, REG_WRITE);
+        CHECK_OP_TYPE(opcode, imm_wop, IMM_WRITE);
+
+exit:
+        return rv;
+}
+#undef CHECK_OP_TYPE
+
+static unsigned int get_ins_reg_width(unsigned long ins_addr)
+{
+        unsigned int opcode;
+        unsigned char *p;
+        int i, shorted, enlarged, rexr;
+
+        p = (unsigned char *)ins_addr;
+        p += skip_prefix(p, &shorted, &enlarged, &rexr);
+        p += get_opcode(p, &opcode);
+
+        for (i = 0; i < ARRAY_SIZE(rw8); i++)
+                if (rw8[i] == opcode)
+                        return 1;
+
+        for (i = 0; i < ARRAY_SIZE(rw32); i++)
+                if (rw32[i] == opcode)
+                        return (shorted ? 2 : (enlarged ? 8 : 4));
+
+        printk(KERN_ERR "mmiotrace: Unknown opcode 0x%02x\n", opcode);
+        return 0;
+}
+
+unsigned int get_ins_mem_width(unsigned long ins_addr)
+{
+        unsigned int opcode;
+        unsigned char *p;
+        int i, shorted, enlarged, rexr;
+
+        p = (unsigned char *)ins_addr;
+        p += skip_prefix(p, &shorted, &enlarged, &rexr);
+        p += get_opcode(p, &opcode);
+
+        for (i = 0; i < ARRAY_SIZE(mw8); i++)
+                if (mw8[i] == opcode)
+                        return 1;
+
+        for (i = 0; i < ARRAY_SIZE(mw16); i++)
+                if (mw16[i] == opcode)
+                        return 2;
+
+        for (i = 0; i < ARRAY_SIZE(mw32); i++)
+                if (mw32[i] == opcode)
+                        return shorted ? 2 : 4;
+
+        for (i = 0; i < ARRAY_SIZE(mw64); i++)
+                if (mw64[i] == opcode)
+                        return shorted ? 2 : (enlarged ? 8 : 4);
+
+        printk(KERN_ERR "mmiotrace: Unknown opcode 0x%02x\n", opcode);
+        return 0;
+}
+
+/*
+ * Define register ident in mod/rm byte.
+ * Note: these are NOT the same as in ptrace-abi.h.
+ */
+enum {
+        arg_AL = 0,
+        arg_CL = 1,
+        arg_DL = 2,
+        arg_BL = 3,
+        arg_AH = 4,
+        arg_CH = 5,
+        arg_DH = 6,
+        arg_BH = 7,
+
+        arg_AX = 0,
+        arg_CX = 1,
+        arg_DX = 2,
+        arg_BX = 3,
+        arg_SP = 4,
+        arg_BP = 5,
+        arg_SI = 6,
+        arg_DI = 7,
+#ifdef __amd64__
+        arg_R8  = 8,
+        arg_R9  = 9,
+        arg_R10 = 10,
+        arg_R11 = 11,
+        arg_R12 = 12,
+        arg_R13 = 13,
+        arg_R14 = 14,
+        arg_R15 = 15
+#endif
+};
+
+static unsigned char *get_reg_w8(int no, struct pt_regs *regs)
+{
+        unsigned char *rv = NULL;
+
+        switch (no) {
+        case arg_AL:
+                rv = (unsigned char *)&regs->ax;
+                break;
+        case arg_BL:
+                rv = (unsigned char *)&regs->bx;
+                break;
+        case arg_CL:
+                rv = (unsigned char *)&regs->cx;
+                break;
+        case arg_DL:
+                rv = (unsigned char *)&regs->dx;
+                break;
+        case arg_AH:
+                rv = 1 + (unsigned char *)&regs->ax;
+                break;
+        case arg_BH:
+                rv = 1 + (unsigned char *)&regs->bx;
+                break;
+        case arg_CH:
+                rv = 1 + (unsigned char *)&regs->cx;
+                break;
+        case arg_DH:
+                rv = 1 + (unsigned char *)&regs->dx;
+                break;
+#ifdef __amd64__
+        case arg_R8:
+                rv = (unsigned char *)&regs->r8;
+                break;
+        case arg_R9:
+                rv = (unsigned char *)&regs->r9;
+                break;
+        case arg_R10:
+                rv = (unsigned char *)&regs->r10;
+                break;
+        case arg_R11:
+                rv = (unsigned char *)&regs->r11;
+                break;
+        case arg_R12:
+                rv = (unsigned char *)&regs->r12;
+                break;
+        case arg_R13:
+                rv = (unsigned char *)&regs->r13;
+                break;
+        case arg_R14:
+                rv = (unsigned char *)&regs->r14;
+                break;
+        case arg_R15:
+                rv = (unsigned char *)&regs->r15;
+                break;
+#endif
+        default:
+                printk(KERN_ERR "mmiotrace: Error reg no# %d\n", no);
+                break;
+        }
+        return rv;
+}
+
+static unsigned long *get_reg_w32(int no, struct pt_regs *regs)
+{
+        unsigned long *rv = NULL;
+
+        switch (no) {
+        case arg_AX:
+                rv = &regs->ax;
+                break;
+        case arg_BX:
+                rv = &regs->bx;
+                break;
+        case arg_CX:
+                rv = &regs->cx;
+                break;
+        case arg_DX:
+                rv = &regs->dx;
+                break;
+        case arg_SP:
+                rv = &regs->sp;
+                break;
+        case arg_BP:
+                rv = &regs->bp;
+                break;
+        case arg_SI:
+                rv = &regs->si;
+                break;
+        case arg_DI:
+                rv = &regs->di;
+                break;
+#ifdef __amd64__
+        case arg_R8:
+                rv = &regs->r8;
+                break;
+        case arg_R9:
+                rv = &regs->r9;
+                break;
+        case arg_R10:
+                rv = &regs->r10;
+                break;
+        case arg_R11:
+                rv = &regs->r11;
+                break;
+        case arg_R12:
+                rv = &regs->r12;
+                break;
+        case arg_R13:
+                rv = &regs->r13;
+                break;
+        case arg_R14:
+                rv = &regs->r14;
+                break;
+        case arg_R15:
+                rv = &regs->r15;
+                break;
+#endif
+        default:
+                printk(KERN_ERR "mmiotrace: Error reg no# %d\n", no);
+        }
+
+        return rv;
+}
+
+unsigned long get_ins_reg_val(unsigned long ins_addr, struct pt_regs *regs)
+{
+        unsigned int opcode;
+        unsigned char mod_rm;
+        int reg;
+        unsigned char *p;
+        int i, shorted, enlarged, rexr;
+        unsigned long rv;
+
+        p = (unsigned char *)ins_addr;
+        p += skip_prefix(p, &shorted, &enlarged, &rexr);
+        p += get_opcode(p, &opcode);
+        for (i = 0; i < ARRAY_SIZE(reg_rop); i++)
+                if (reg_rop[i] == opcode) {
+                        rv = REG_READ;
+                        goto do_work;
+                }
+
+        for (i = 0; i < ARRAY_SIZE(reg_wop); i++)
+                if (reg_wop[i] == opcode) {
+                        rv = REG_WRITE;
+                        goto do_work;
+                }
+
+        printk(KERN_ERR "mmiotrace: Not a register instruction, opcode "
+                                                        "0x%02x\n", opcode);
+        goto err;
+
+do_work:
+        mod_rm = *p;
+        reg = ((mod_rm >> 3) & 0x7) | (rexr << 3);
+        switch (get_ins_reg_width(ins_addr)) {
+        case 1:
+                return *get_reg_w8(reg, regs);
+
+        case 2:
+                return *(unsigned short *)get_reg_w32(reg, regs);
+
+        case 4:
+                return *(unsigned int *)get_reg_w32(reg, regs);
+
+#ifdef __amd64__
+        case 8:
+                return *(unsigned long *)get_reg_w32(reg, regs);
+#endif
+
+        default:
+                printk(KERN_ERR "mmiotrace: Error width# %d\n", reg);
+        }
+
+err:
+        return 0;
+}
+
+unsigned long get_ins_imm_val(unsigned long ins_addr)
+{
+        unsigned int opcode;
+        unsigned char mod_rm;
+        unsigned char mod;
+        unsigned char *p;
+        int i, shorted, enlarged, rexr;
+        unsigned long rv;
+
+        p = (unsigned char *)ins_addr;
+        p += skip_prefix(p, &shorted, &enlarged, &rexr);
+        p += get_opcode(p, &opcode);
+        for (i = 0; i < ARRAY_SIZE(imm_wop); i++)
+                if (imm_wop[i] == opcode) {
+                        rv = IMM_WRITE;
+                        goto do_work;
+                }
+
+        printk(KERN_ERR "mmiotrace: Not an immediate instruction, opcode "
+                                                        "0x%02x\n", opcode);
+        goto err;
+
+do_work:
+        mod_rm = *p;
+        mod = mod_rm >> 6;
+        p++;
+        switch (mod) {
+        case 0:
+                /* if r/m is 5 we have a 32 disp (IA32 Manual 3, Table 2-2)  */
+                /* AMD64: XXX Check for address size prefix? */
+                if ((mod_rm & 0x7) == 0x5)
+                        p += 4;
+                break;
+
+        case 1:
+                p += 1;
+                break;
+
+        case 2:
+                p += 4;
+                break;
+
+        case 3:
+        default:
+                printk(KERN_ERR "mmiotrace: not a memory access instruction "
+                                                "at 0x%lx, rm_mod=0x%02x\n",
+                                                ins_addr, mod_rm);
+        }
+
+        switch (get_ins_reg_width(ins_addr)) {
+        case 1:
+                return *(unsigned char *)p;
+
+        case 2:
+                return *(unsigned short *)p;
+
+        case 4:
+                return *(unsigned int *)p;
+
+#ifdef __amd64__
+        case 8:
+                return *(unsigned long *)p;
+#endif
+
+        default:
+                printk(KERN_ERR "mmiotrace: Error: width.\n");
+        }
+
+err:
+        return 0;
+}
diff --git a/arch/x86/mm/pf_in.h b/arch/x86/mm/pf_in.h
new file mode 100644
index 000000000000..e05341a51a27
--- /dev/null
+++ b/arch/x86/mm/pf_in.h
@@ -0,0 +1,39 @@
+/*
+ *  Fault Injection Test harness (FI)
+ *  Copyright (C) Intel Crop.
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  as published by the Free Software Foundation; either version 2
+ *  of the License, or (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307,
+ *  USA.
+ *
+ */
+
+#ifndef __PF_H_
+#define __PF_H_
+
+enum reason_type {
+        NOT_ME, /* page fault is not in regions */
+        NOTHING,        /* access others point in regions */
+        REG_READ,       /* read from addr to reg */
+        REG_WRITE,      /* write from reg to addr */
+        IMM_WRITE,      /* write from imm to addr */
+        OTHERS  /* Other instructions can not intercept */
+};
+
+enum reason_type get_ins_type(unsigned long ins_addr);
+unsigned int get_ins_mem_width(unsigned long ins_addr);
+unsigned long get_ins_reg_val(unsigned long ins_addr, struct pt_regs *regs);
+unsigned long get_ins_imm_val(unsigned long ins_addr);
+
+#endif /* __PF_H_ */
diff --git a/arch/x86/mm/pgtable.c b/arch/x86/mm/pgtable.c
index 50159764f694..557b2abceef8 100644
--- a/arch/x86/mm/pgtable.c
+++ b/arch/x86/mm/pgtable.c
@@ -2,6 +2,7 @@
 #include <asm/pgalloc.h>
 #include <asm/pgtable.h>
 #include <asm/tlb.h>
+#include <asm/fixmap.h>
 
 pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
 {
@@ -65,12 +66,6 @@ static inline void pgd_list_del(pgd_t *pgd)
 static void pgd_ctor(void *p)
 {
         pgd_t *pgd = p;
-        unsigned long flags;
-
-        /* Clear usermode parts of PGD */
-        memset(pgd, 0, KERNEL_PGD_BOUNDARY*sizeof(pgd_t));
-
-        spin_lock_irqsave(&pgd_lock, flags);
 
         /* If the pgd points to a shared pagetable level (either the
            ptes in non-PAE, or shared PMD in PAE), then just copy the
@@ -90,8 +85,6 @@ static void pgd_ctor(void *p)
         /* list required to sync kernel mapping updates */
         if (!SHARED_KERNEL_PMD)
                 pgd_list_add(pgd);
-
-        spin_unlock_irqrestore(&pgd_lock, flags);
 }
 
 static void pgd_dtor(void *pgd)
@@ -119,6 +112,72 @@ static void pgd_dtor(void *pgd)
 
 #ifdef CONFIG_X86_PAE
 /*
+ * In PAE mode, we need to do a cr3 reload (=tlb flush) when
+ * updating the top-level pagetable entries to guarantee the
+ * processor notices the update.  Since this is expensive, and
+ * all 4 top-level entries are used almost immediately in a
+ * new process's life, we just pre-populate them here.
+ *
+ * Also, if we're in a paravirt environment where the kernel pmd is
+ * not shared between pagetables (!SHARED_KERNEL_PMDS), we allocate
+ * and initialize the kernel pmds here.
+ */
+#define PREALLOCATED_PMDS       UNSHARED_PTRS_PER_PGD
+
+void pud_populate(struct mm_struct *mm, pud_t *pudp, pmd_t *pmd)
+{
+        paravirt_alloc_pmd(mm, __pa(pmd) >> PAGE_SHIFT);
+
+        /* Note: almost everything apart from _PAGE_PRESENT is
+           reserved at the pmd (PDPT) level. */
+        set_pud(pudp, __pud(__pa(pmd) | _PAGE_PRESENT));
+
+        /*
+         * According to Intel App note "TLBs, Paging-Structure Caches,
+         * and Their Invalidation", April 2007, document 317080-001,
+         * section 8.1: in PAE mode we explicitly have to flush the
+         * TLB via cr3 if the top-level pgd is changed...
+         */
+        if (mm == current->active_mm)
+                write_cr3(read_cr3());
+}
+#else  /* !CONFIG_X86_PAE */
+
+/* No need to prepopulate any pagetable entries in non-PAE modes. */
+#define PREALLOCATED_PMDS       0
+
+#endif  /* CONFIG_X86_PAE */
+
+static void free_pmds(pmd_t *pmds[])
+{
+        int i;
+
+        for(i = 0; i < PREALLOCATED_PMDS; i++)
+                if (pmds[i])
+                        free_page((unsigned long)pmds[i]);
+}
+
+static int preallocate_pmds(pmd_t *pmds[])
+{
+        int i;
+        bool failed = false;
+
+        for(i = 0; i < PREALLOCATED_PMDS; i++) {
+                pmd_t *pmd = (pmd_t *)get_zeroed_page(GFP_KERNEL|__GFP_REPEAT);
+                if (pmd == NULL)
+                        failed = true;
+                pmds[i] = pmd;
+        }
+
+        if (failed) {
+                free_pmds(pmds);
+                return -ENOMEM;
+        }
+
+        return 0;
+}
+
+/*
  * Mop up any pmd pages which may still be attached to the pgd.
  * Normally they will be freed by munmap/exit_mmap, but any pmd we
  * preallocate which never got a corresponding vma will need to be
@@ -128,7 +187,7 @@ static void pgd_mop_up_pmds(struct mm_struct *mm, pgd_t *pgdp)
 {
         int i;
 
-        for(i = 0; i < UNSHARED_PTRS_PER_PGD; i++) {
+        for(i = 0; i < PREALLOCATED_PMDS; i++) {
                 pgd_t pgd = pgdp[i];
 
                 if (pgd_val(pgd) != 0) {
@@ -142,32 +201,17 @@ static void pgd_mop_up_pmds(struct mm_struct *mm, pgd_t *pgdp)
         }
 }
 
-/*
- * In PAE mode, we need to do a cr3 reload (=tlb flush) when
- * updating the top-level pagetable entries to guarantee the
- * processor notices the update.  Since this is expensive, and
- * all 4 top-level entries are used almost immediately in a
- * new process's life, we just pre-populate them here.
- *
- * Also, if we're in a paravirt environment where the kernel pmd is
- * not shared between pagetables (!SHARED_KERNEL_PMDS), we allocate
- * and initialize the kernel pmds here.
- */
-static int pgd_prepopulate_pmd(struct mm_struct *mm, pgd_t *pgd)
+static void pgd_prepopulate_pmd(struct mm_struct *mm, pgd_t *pgd, pmd_t *pmds[])
 {
         pud_t *pud;
         unsigned long addr;
         int i;
 
         pud = pud_offset(pgd, 0);
-        for (addr = i = 0; i < UNSHARED_PTRS_PER_PGD;
-             i++, pud++, addr += PUD_SIZE) {
-                pmd_t *pmd = pmd_alloc_one(mm, addr);
 
-                if (!pmd) {
-                        pgd_mop_up_pmds(mm, pgd);
-                        return 0;
-                }
+        for (addr = i = 0; i < PREALLOCATED_PMDS;
+             i++, pud++, addr += PUD_SIZE) {
+                pmd_t *pmd = pmds[i];
 
                 if (i >= KERNEL_PGD_BOUNDARY)
                         memcpy(pmd, (pmd_t *)pgd_page_vaddr(swapper_pg_dir[i]),
@@ -175,61 +219,54 @@ static int pgd_prepopulate_pmd(struct mm_struct *mm, pgd_t *pgd)
 
                 pud_populate(mm, pud, pmd);
         }
-
-        return 1;
 }
 
-void pud_populate(struct mm_struct *mm, pud_t *pudp, pmd_t *pmd)
+pgd_t *pgd_alloc(struct mm_struct *mm)
 {
-        paravirt_alloc_pmd(mm, __pa(pmd) >> PAGE_SHIFT);
+        pgd_t *pgd;
+        pmd_t *pmds[PREALLOCATED_PMDS];
+        unsigned long flags;
 
-        /* Note: almost everything apart from _PAGE_PRESENT is
-           reserved at the pmd (PDPT) level. */
-        set_pud(pudp, __pud(__pa(pmd) | _PAGE_PRESENT));
+        pgd = (pgd_t *)__get_free_page(GFP_KERNEL | __GFP_ZERO);
 
-        /*
-         * According to Intel App note "TLBs, Paging-Structure Caches,
-         * and Their Invalidation", April 2007, document 317080-001,
-         * section 8.1: in PAE mode we explicitly have to flush the
-         * TLB via cr3 if the top-level pgd is changed...
-         */
-        if (mm == current->active_mm)
-                write_cr3(read_cr3());
-}
-#else  /* !CONFIG_X86_PAE */
-/* No need to prepopulate any pagetable entries in non-PAE modes. */
-static int pgd_prepopulate_pmd(struct mm_struct *mm, pgd_t *pgd)
-{
-        return 1;
-}
+        if (pgd == NULL)
+                goto out;
 
-static void pgd_mop_up_pmds(struct mm_struct *mm, pgd_t *pgd)
-{
-}
-#endif  /* CONFIG_X86_PAE */
+        mm->pgd = pgd;
 
-pgd_t *pgd_alloc(struct mm_struct *mm)
-{
-        pgd_t *pgd = (pgd_t *)__get_free_page(GFP_KERNEL | __GFP_ZERO);
+        if (preallocate_pmds(pmds) != 0)
+                goto out_free_pgd;
 
-        /* so that alloc_pmd can use it */
-        mm->pgd = pgd;
-        if (pgd)
-                pgd_ctor(pgd);
+        if (paravirt_pgd_alloc(mm) != 0)
+                goto out_free_pmds;
 
-        if (pgd && !pgd_prepopulate_pmd(mm, pgd)) {
-                pgd_dtor(pgd);
-                free_page((unsigned long)pgd);
-                pgd = NULL;
-        }
+        /*
+         * Make sure that pre-populating the pmds is atomic with
+         * respect to anything walking the pgd_list, so that they
+         * never see a partially populated pgd.
+         */
+        spin_lock_irqsave(&pgd_lock, flags);
+
+        pgd_ctor(pgd);
+        pgd_prepopulate_pmd(mm, pgd, pmds);
+
+        spin_unlock_irqrestore(&pgd_lock, flags);
 
         return pgd;
+
+out_free_pmds:
+        free_pmds(pmds);
+out_free_pgd:
+        free_page((unsigned long)pgd);
+out:
+        return NULL;
 }
 
 void pgd_free(struct mm_struct *mm, pgd_t *pgd)
 {
         pgd_mop_up_pmds(mm, pgd);
         pgd_dtor(pgd);
+        paravirt_pgd_free(mm, pgd);
         free_page((unsigned long)pgd);
 }
 
@@ -255,7 +292,7 @@ int ptep_test_and_clear_young(struct vm_area_struct *vma,
 
         if (pte_young(*ptep))
                 ret = test_and_clear_bit(_PAGE_BIT_ACCESSED,
-                                         &ptep->pte);
+                                         (unsigned long *) &ptep->pte);
 
         if (ret)
                 pte_update(vma->vm_mm, addr, ptep);
@@ -274,3 +311,22 @@ int ptep_clear_flush_young(struct vm_area_struct *vma,
 
         return young;
 }
+
+int fixmaps_set;
+
+void __native_set_fixmap(enum fixed_addresses idx, pte_t pte)
+{
+        unsigned long address = __fix_to_virt(idx);
+
+        if (idx >= __end_of_fixed_addresses) {
+                BUG();
+                return;
+        }
+        set_pte_vaddr(address, pte);
+        fixmaps_set++;
+}
+
+void native_set_fixmap(enum fixed_addresses idx, unsigned long phys, pgprot_t flags)
+{
+        __native_set_fixmap(idx, pfn_pte(phys >> PAGE_SHIFT, flags));
+}
diff --git a/arch/x86/mm/pgtable_32.c b/arch/x86/mm/pgtable_32.c
index 369cf065b6a4..b4becbf8c570 100644
--- a/arch/x86/mm/pgtable_32.c
+++ b/arch/x86/mm/pgtable_32.c
@@ -71,7 +71,7 @@ void show_mem(void)
  * Associate a virtual page frame with a given physical page frame 
  * and protection flags for that frame.
  */ 
-static void set_pte_pfn(unsigned long vaddr, unsigned long pfn, pgprot_t flags)
+void set_pte_vaddr(unsigned long vaddr, pte_t pteval)
 {
         pgd_t *pgd;
         pud_t *pud;
@@ -94,8 +94,8 @@ static void set_pte_pfn(unsigned long vaddr, unsigned long pfn, pgprot_t flags)
                 return;
         }
         pte = pte_offset_kernel(pmd, vaddr);
-        if (pgprot_val(flags))
-                set_pte_present(&init_mm, vaddr, pte, pfn_pte(pfn, flags));
+        if (pte_val(pteval))
+                set_pte_present(&init_mm, vaddr, pte, pteval);
         else
                 pte_clear(&init_mm, vaddr, pte);
 
@@ -141,22 +141,9 @@ void set_pmd_pfn(unsigned long vaddr, unsigned long pfn, pgprot_t flags)
         __flush_tlb_one(vaddr);
 }
 
-static int fixmaps;
 unsigned long __FIXADDR_TOP = 0xfffff000;
 EXPORT_SYMBOL(__FIXADDR_TOP);
 
-void __set_fixmap (enum fixed_addresses idx, unsigned long phys, pgprot_t flags)
-{
-        unsigned long address = __fix_to_virt(idx);
-
-        if (idx >= __end_of_fixed_addresses) {
-                BUG();
-                return;
-        }
-        set_pte_pfn(address, phys >> PAGE_SHIFT, flags);
-        fixmaps++;
-}
-
 /**
  * reserve_top_address - reserves a hole in the top of kernel address space
  * @reserve - size of hole to reserve
@@ -164,11 +151,44 @@ void __set_fixmap (enum fixed_addresses idx, unsigned long phys, pgprot_t flags)
  * Can be used to relocate the fixmap area and poke a hole in the top
  * of kernel address space to make room for a hypervisor.
  */
-void reserve_top_address(unsigned long reserve)
+void __init reserve_top_address(unsigned long reserve)
 {
-        BUG_ON(fixmaps > 0);
+        BUG_ON(fixmaps_set > 0);
         printk(KERN_INFO "Reserving virtual address space above 0x%08x\n",
                (int)-reserve);
         __FIXADDR_TOP = -reserve - PAGE_SIZE;
         __VMALLOC_RESERVE += reserve;
 }
+
+/*
+ * vmalloc=size forces the vmalloc area to be exactly 'size'
+ * bytes. This can be used to increase (or decrease) the
+ * vmalloc area - the default is 128m.
+ */
+static int __init parse_vmalloc(char *arg)
+{
+        if (!arg)
+                return -EINVAL;
+
+        __VMALLOC_RESERVE = memparse(arg, &arg);
+        return 0;
+}
+early_param("vmalloc", parse_vmalloc);
+
+/*
+ * reservetop=size reserves a hole at the top of the kernel address space which
+ * a hypervisor can load into later.  Needed for dynamically loaded hypervisors,
+ * so relocating the fixmap can be done before paging initialization.
+ */
+static int __init parse_reservetop(char *arg)
+{
+        unsigned long address;
+
+        if (!arg)
+                return -EINVAL;
+
+        address = memparse(arg, &arg);
+        reserve_top_address(address);
+        return 0;
+}
+early_param("reservetop", parse_reservetop);
diff --git a/arch/x86/kernel/srat_32.c b/arch/x86/mm/srat_32.c
index 70e4a374b4e8..f41d67f8f831 100644
--- a/arch/x86/kernel/srat_32.c
+++ b/arch/x86/mm/srat_32.c
@@ -31,6 +31,7 @@
 #include <asm/srat.h>
 #include <asm/topology.h>
 #include <asm/smp.h>
+#include <asm/e820.h>
 
 /*
  * proximity macros and definitions
@@ -41,7 +42,7 @@
 #define BMAP_TEST(bmap, bit)    ((bmap)[NODE_ARRAY_INDEX(bit)] & (1 << NODE_ARRAY_OFFSET(bit)))
 /* bitmap length; _PXM is at most 255 */
 #define PXM_BITMAP_LEN (MAX_PXM_DOMAINS / 8) 
-static u8 pxm_bitmap[PXM_BITMAP_LEN];   /* bitmap of proximity domains */
+static u8 __initdata pxm_bitmap[PXM_BITMAP_LEN];        /* bitmap of proximity domains */
 
 #define MAX_CHUNKS_PER_NODE     3
 #define MAXCHUNKS               (MAX_CHUNKS_PER_NODE * MAX_NUMNODES)
@@ -52,16 +53,37 @@ struct node_memory_chunk_s {
         u8      nid;            // which cnode contains this chunk?
         u8      bank;           // which mem bank on this node
 };
-static struct node_memory_chunk_s node_memory_chunk[MAXCHUNKS];
+static struct node_memory_chunk_s __initdata node_memory_chunk[MAXCHUNKS];
 
-static int num_memory_chunks;           /* total number of memory chunks */
+static int __initdata num_memory_chunks; /* total number of memory chunks */
 static u8 __initdata apicid_to_pxm[MAX_APICID];
 
+int numa_off __initdata;
+int acpi_numa __initdata;
+
+static __init void bad_srat(void)
+{
+        printk(KERN_ERR "SRAT: SRAT not used.\n");
+        acpi_numa = -1;
+        num_memory_chunks = 0;
+}
+
+static __init inline int srat_disabled(void)
+{
+        return numa_off || acpi_numa < 0;
+}
+
 /* Identify CPU proximity domains */
-static void __init parse_cpu_affinity_structure(char *p)
+void __init
+acpi_numa_processor_affinity_init(struct acpi_srat_cpu_affinity *cpu_affinity)
 {
-        struct acpi_srat_cpu_affinity *cpu_affinity =
-                                (struct acpi_srat_cpu_affinity *) p;
+        if (srat_disabled())
+                return;
+        if (cpu_affinity->header.length !=
+             sizeof(struct acpi_srat_cpu_affinity)) {
+                bad_srat();
+                return;
+        }
 
         if ((cpu_affinity->flags & ACPI_SRAT_CPU_ENABLED) == 0)
                 return;         /* empty entry */
@@ -71,7 +93,7 @@ static void __init parse_cpu_affinity_structure(char *p)
 
         apicid_to_pxm[cpu_affinity->apic_id] = cpu_affinity->proximity_domain_lo;
 
-        printk("CPU 0x%02X in proximity domain 0x%02X\n",
+        printk(KERN_DEBUG "CPU %02x in proximity domain %02x\n",
                 cpu_affinity->apic_id, cpu_affinity->proximity_domain_lo);
 }
 
@@ -79,14 +101,21 @@ static void __init parse_cpu_affinity_structure(char *p)
  * Identify memory proximity domains and hot-remove capabilities.
  * Fill node memory chunk list structure.
  */
-static void __init parse_memory_affinity_structure (char *sratp)
+void __init
+acpi_numa_memory_affinity_init(struct acpi_srat_mem_affinity *memory_affinity)
 {
         unsigned long long paddr, size;
         unsigned long start_pfn, end_pfn;
         u8 pxm;
         struct node_memory_chunk_s *p, *q, *pend;
-        struct acpi_srat_mem_affinity *memory_affinity =
-                        (struct acpi_srat_mem_affinity *) sratp;
+
+        if (srat_disabled())
+                return;
+        if (memory_affinity->header.length !=
+             sizeof(struct acpi_srat_mem_affinity)) {
+                bad_srat();
+                return;
+        }
 
         if ((memory_affinity->flags & ACPI_SRAT_MEM_ENABLED) == 0)
                 return;         /* empty entry */
@@ -105,7 +134,8 @@ static void __init parse_memory_affinity_structure (char *sratp)
 
 
         if (num_memory_chunks >= MAXCHUNKS) {
-                printk("Too many mem chunks in SRAT. Ignoring %lld MBytes at %llx\n",
+                printk(KERN_WARNING "Too many mem chunks in SRAT."
+                        " Ignoring %lld MBytes at %llx\n",
                         size/(1024*1024), paddr);
                 return;
         }
@@ -126,7 +156,8 @@ static void __init parse_memory_affinity_structure (char *sratp)
 
         num_memory_chunks++;
 
-        printk("Memory range 0x%lX to 0x%lX (type 0x%X) in proximity domain 0x%02X %s\n",
+        printk(KERN_DEBUG "Memory range %08lx to %08lx (type %x)"
+                          " in proximity domain %02x %s\n",
                 start_pfn, end_pfn,
                 memory_affinity->memory_type,
                 pxm,
@@ -134,6 +165,14 @@ static void __init parse_memory_affinity_structure (char *sratp)
                  "enabled and removable" : "enabled" ) );
 }
 
+/* Callback for SLIT parsing */
+void __init acpi_numa_slit_init(struct acpi_table_slit *slit)
+{
+}
+
+void acpi_numa_arch_fixup(void)
+{
+}
 /*
  * The SRAT table always lists ascending addresses, so can always
  * assume that the first "start" address that you see is the real
@@ -149,7 +188,7 @@ static __init void node_read_chunk(int nid, struct node_memory_chunk_s *memory_c
          * *possible* memory hotplug areas the same as normal RAM.
          */
         if (memory_chunk->start_pfn >= max_pfn) {
-                printk (KERN_INFO "Ignoring SRAT pfns: 0x%08lx -> %08lx\n",
+                printk(KERN_INFO "Ignoring SRAT pfns: %08lx - %08lx\n",
                         memory_chunk->start_pfn, memory_chunk->end_pfn);
                 return;
         }
@@ -166,42 +205,17 @@ static __init void node_read_chunk(int nid, struct node_memory_chunk_s *memory_c
                 node_end_pfn[nid] = memory_chunk->end_pfn;
 }
 
-/* Parse the ACPI Static Resource Affinity Table */
-static int __init acpi20_parse_srat(struct acpi_table_srat *sratp)
+int __init get_memcfg_from_srat(void)
 {
-        u8 *start, *end, *p;
         int i, j, nid;
 
-        start = (u8 *)(&(sratp->reserved) + 1); /* skip header */
-        p = start;
-        end = (u8 *)sratp + sratp->header.length;
 
-        memset(pxm_bitmap, 0, sizeof(pxm_bitmap));      /* init proximity domain bitmap */
-        memset(node_memory_chunk, 0, sizeof(node_memory_chunk));
-
-        num_memory_chunks = 0;
-        while (p < end) {
-                switch (*p) {
-                case ACPI_SRAT_TYPE_CPU_AFFINITY:
-                        parse_cpu_affinity_structure(p);
-                        break;
-                case ACPI_SRAT_TYPE_MEMORY_AFFINITY:
-                        parse_memory_affinity_structure(p);
-                        break;
-                default:
-                        printk("ACPI 2.0 SRAT: unknown entry skipped: type=0x%02X, len=%d\n", p[0], p[1]);
-                        break;
-                }
-                p += p[1];
-                if (p[1] == 0) {
-                        printk("acpi20_parse_srat: Entry length value is zero;"
-                                " can't parse any further!\n");
-                        break;
-                }
-        }
+        if (srat_disabled())
+                goto out_fail;
 
         if (num_memory_chunks == 0) {
-                printk("could not finy any ACPI SRAT memory areas.\n");
+                printk(KERN_WARNING
+                         "could not finy any ACPI SRAT memory areas.\n");
                 goto out_fail;
         }
 
@@ -228,131 +242,39 @@ static int __init acpi20_parse_srat(struct acpi_table_srat *sratp)
         for (i = 0; i < num_memory_chunks; i++)
                 node_memory_chunk[i].nid = pxm_to_node(node_memory_chunk[i].pxm);
 
-        printk("pxm bitmap: ");
+        printk(KERN_DEBUG "pxm bitmap: ");
         for (i = 0; i < sizeof(pxm_bitmap); i++) {
-                printk("%02X ", pxm_bitmap[i]);
+                printk(KERN_CONT "%02x ", pxm_bitmap[i]);
         }
-        printk("\n");
-        printk("Number of logical nodes in system = %d\n", num_online_nodes());
-        printk("Number of memory chunks in system = %d\n", num_memory_chunks);
+        printk(KERN_CONT "\n");
+        printk(KERN_DEBUG "Number of logical nodes in system = %d\n",
+                         num_online_nodes());
+        printk(KERN_DEBUG "Number of memory chunks in system = %d\n",
+                         num_memory_chunks);
 
         for (i = 0; i < MAX_APICID; i++)
                 apicid_2_node[i] = pxm_to_node(apicid_to_pxm[i]);
 
         for (j = 0; j < num_memory_chunks; j++){
                 struct node_memory_chunk_s * chunk = &node_memory_chunk[j];
-                printk("chunk %d nid %d start_pfn %08lx end_pfn %08lx\n",
+                printk(KERN_DEBUG
+                        "chunk %d nid %d start_pfn %08lx end_pfn %08lx\n",
                        j, chunk->nid, chunk->start_pfn, chunk->end_pfn);
                 node_read_chunk(chunk->nid, chunk);
-                add_active_range(chunk->nid, chunk->start_pfn, chunk->end_pfn);
+                e820_register_active_regions(chunk->nid, chunk->start_pfn,
+                                             min(chunk->end_pfn, max_pfn));
         }
- 
+
         for_each_online_node(nid) {
                 unsigned long start = node_start_pfn[nid];
-                unsigned long end = node_end_pfn[nid];
+                unsigned long end = min(node_end_pfn[nid], max_pfn);
 
                 memory_present(nid, start, end);
                 node_remap_size[nid] = node_memmap_size_bytes(nid, start, end);
         }
         return 1;
 out_fail:
-        return 0;
-}
-
-struct acpi_static_rsdt {
-        struct acpi_table_rsdt table;
-        u32 padding[7]; /* Allow for 7 more table entries */
-};
-
-int __init get_memcfg_from_srat(void)
-{
-        struct acpi_table_header *header = NULL;
-        struct acpi_table_rsdp *rsdp = NULL;
-        struct acpi_table_rsdt *rsdt = NULL;
-        acpi_native_uint rsdp_address = 0;
-        struct acpi_static_rsdt saved_rsdt;
-        int tables = 0;
-        int i = 0;
-
-        rsdp_address = acpi_os_get_root_pointer();
-        if (!rsdp_address) {
-                printk("%s: System description tables not found\n",
-                       __func__);
-                goto out_err;
-        }
-
-        printk("%s: assigning address to rsdp\n", __func__);
-        rsdp = (struct acpi_table_rsdp *)(u32)rsdp_address;
-        if (!rsdp) {
-                printk("%s: Didn't find ACPI root!\n", __func__);
-                goto out_err;
-        }
-
-        printk(KERN_INFO "%.8s v%d [%.6s]\n", rsdp->signature, rsdp->revision,
-                rsdp->oem_id);
-
-        if (strncmp(rsdp->signature, ACPI_SIG_RSDP,strlen(ACPI_SIG_RSDP))) {
-                printk(KERN_WARNING "%s: RSDP table signature incorrect\n", __func__);
-                goto out_err;
-        }
-
-        rsdt = (struct acpi_table_rsdt *)
-            early_ioremap(rsdp->rsdt_physical_address, sizeof(struct acpi_table_rsdt));
-
-        if (!rsdt) {
-                printk(KERN_WARNING
-                       "%s: ACPI: Invalid root system description tables (RSDT)\n",
-                       __func__);
-                goto out_err;
-        }
-
-        header = &rsdt->header;
-
-        if (strncmp(header->signature, ACPI_SIG_RSDT, strlen(ACPI_SIG_RSDT))) {
-                printk(KERN_WARNING "ACPI: RSDT signature incorrect\n");
-                goto out_err;
-        }
-
-        /* 
-         * The number of tables is computed by taking the 
-         * size of all entries (header size minus total 
-         * size of RSDT) divided by the size of each entry
-         * (4-byte table pointers).
-         */
-        tables = (header->length - sizeof(struct acpi_table_header)) / 4;
-
-        if (!tables)
-                goto out_err;
-
-        memcpy(&saved_rsdt, rsdt, sizeof(saved_rsdt));
-
-        if (saved_rsdt.table.header.length > sizeof(saved_rsdt)) {
-                printk(KERN_WARNING "ACPI: Too big length in RSDT: %d\n",
-                       saved_rsdt.table.header.length);
-                goto out_err;
-        }
-
-        printk("Begin SRAT table scan....\n");
-
-        for (i = 0; i < tables; i++) {
-                /* Map in header, then map in full table length. */
-                header = (struct acpi_table_header *)
-                        early_ioremap(saved_rsdt.table.table_offset_entry[i], sizeof(struct acpi_table_header));
-                if (!header)
-                        break;
-                header = (struct acpi_table_header *)
-                        early_ioremap(saved_rsdt.table.table_offset_entry[i], header->length);
-                if (!header)
-                        break;
-
-                if (strncmp((char *) &header->signature, ACPI_SIG_SRAT, 4))
-                        continue;
-
-                /* we've found the srat table. don't need to look at any more tables */
-                return acpi20_parse_srat((struct acpi_table_srat *)header);
-        }
-out_err:
-        remove_all_active_ranges();
-        printk("failed to get NUMA memory information from SRAT table\n");
+        printk(KERN_ERR "failed to get NUMA memory information from SRAT"
+                        " table\n");
         return 0;
 }
diff --git a/arch/x86/mm/srat_64.c b/arch/x86/mm/srat_64.c
index 99649dccad28..1b4763e26ea9 100644
--- a/arch/x86/mm/srat_64.c
+++ b/arch/x86/mm/srat_64.c
@@ -100,7 +100,19 @@ static __init inline int srat_disabled(void)
 /* Callback for SLIT parsing */
 void __init acpi_numa_slit_init(struct acpi_table_slit *slit)
 {
-        acpi_slit = slit;
+        unsigned length;
+        unsigned long phys;
+
+        length = slit->header.length;
+        phys = find_e820_area(0, max_pfn_mapped<<PAGE_SHIFT, length,
+                 PAGE_SIZE);
+
+        if (phys == -1L)
+                panic(" Can not save slit!\n");
+
+        acpi_slit = __va(phys);
+        memcpy(acpi_slit, slit, length);
+        reserve_early(phys, phys + length, "ACPI SLIT");
 }
 
 /* Callback for Proximity Domain -> LAPIC mapping */
@@ -299,7 +311,7 @@ static int __init nodes_cover_memory(const struct bootnode *nodes)
                         pxmram = 0;
         }
 
-        e820ram = end_pfn - absent_pages_in_range(0, end_pfn);
+        e820ram = max_pfn - absent_pages_in_range(0, max_pfn);
         /* We seem to lose 3 pages somewhere. Allow a bit of slack. */
         if ((long)(e820ram - pxmram) >= 1*1024*1024) {
                 printk(KERN_ERR
@@ -376,7 +388,7 @@ int __init acpi_scan_nodes(unsigned long start, unsigned long end)
                 if (node == NUMA_NO_NODE)
                         continue;
                 if (!node_isset(node, node_possible_map))
-                        numa_set_node(i, NUMA_NO_NODE);
+                        numa_clear_node(i);
         }
         numa_init_array();
         return 0;
@@ -495,6 +507,7 @@ int __node_distance(int a, int b)
 
 EXPORT_SYMBOL(__node_distance);
 
+#if defined(CONFIG_MEMORY_HOTPLUG_SPARSE) || defined(CONFIG_ACPI_HOTPLUG_MEMORY)
 int memory_add_physaddr_to_nid(u64 start)
 {
         int i, ret = 0;
@@ -506,4 +519,4 @@ int memory_add_physaddr_to_nid(u64 start)
         return ret;
 }
 EXPORT_SYMBOL_GPL(memory_add_physaddr_to_nid);
-
+#endif
diff --git a/arch/x86/mm/testmmiotrace.c b/arch/x86/mm/testmmiotrace.c
new file mode 100644
index 000000000000..d877c5b423ef
--- /dev/null
+++ b/arch/x86/mm/testmmiotrace.c
@@ -0,0 +1,71 @@
+/*
+ * Written by Pekka Paalanen, 2008 <pq@iki.fi>
+ */
+#include <linux/module.h>
+#include <linux/io.h>
+
+#define MODULE_NAME "testmmiotrace"
+
+static unsigned long mmio_address;
+module_param(mmio_address, ulong, 0);
+MODULE_PARM_DESC(mmio_address, "Start address of the mapping of 16 kB.");
+
+static void do_write_test(void __iomem *p)
+{
+        unsigned int i;
+        for (i = 0; i < 256; i++)
+                iowrite8(i, p + i);
+        for (i = 1024; i < (5 * 1024); i += 2)
+                iowrite16(i * 12 + 7, p + i);
+        for (i = (5 * 1024); i < (16 * 1024); i += 4)
+                iowrite32(i * 212371 + 13, p + i);
+}
+
+static void do_read_test(void __iomem *p)
+{
+        unsigned int i;
+        for (i = 0; i < 256; i++)
+                ioread8(p + i);
+        for (i = 1024; i < (5 * 1024); i += 2)
+                ioread16(p + i);
+        for (i = (5 * 1024); i < (16 * 1024); i += 4)
+                ioread32(p + i);
+}
+
+static void do_test(void)
+{
+        void __iomem *p = ioremap_nocache(mmio_address, 0x4000);
+        if (!p) {
+                pr_err(MODULE_NAME ": could not ioremap, aborting.\n");
+                return;
+        }
+        do_write_test(p);
+        do_read_test(p);
+        iounmap(p);
+}
+
+static int __init init(void)
+{
+        if (mmio_address == 0) {
+                pr_err(MODULE_NAME ": you have to use the module argument "
+                                                        "mmio_address.\n");
+                pr_err(MODULE_NAME ": DO NOT LOAD THIS MODULE UNLESS"
+                                " YOU REALLY KNOW WHAT YOU ARE DOING!\n");
+                return -ENXIO;
+        }
+
+        pr_warning(MODULE_NAME ": WARNING: mapping 16 kB @ 0x%08lx "
+                                        "in PCI address space, and writing "
+                                        "rubbish in there.\n", mmio_address);
+        do_test();
+        return 0;
+}
+
+static void __exit cleanup(void)
+{
+        pr_debug(MODULE_NAME ": unloaded.\n");
+}
+
+module_init(init);
+module_exit(cleanup);
+MODULE_LICENSE("GPL");
diff --git a/arch/x86/oprofile/nmi_int.c b/arch/x86/oprofile/nmi_int.c
index cc48d3fde545..2b6ad5b9f9d5 100644
--- a/arch/x86/oprofile/nmi_int.c
+++ b/arch/x86/oprofile/nmi_int.c
@@ -269,12 +269,13 @@ static void nmi_cpu_shutdown(void *dummy)
 
 static void nmi_shutdown(void)
 {
-        struct op_msrs *msrs = &__get_cpu_var(cpu_msrs);
+        struct op_msrs *msrs = &get_cpu_var(cpu_msrs);
         nmi_enabled = 0;
         on_each_cpu(nmi_cpu_shutdown, NULL, 0, 1);
         unregister_die_notifier(&profile_exceptions_nb);
         model->shutdown(msrs);
         free_msrs();
+        put_cpu_var(cpu_msrs);
 }
 
 static void nmi_cpu_start(void *dummy)
diff --git a/arch/x86/pci/Makefile b/arch/x86/pci/Makefile
index c5c8e485fc44..e515e8db842a 100644
--- a/arch/x86/pci/Makefile
+++ b/arch/x86/pci/Makefile
@@ -1,5 +1,17 @@
-ifeq ($(CONFIG_X86_32),y)
-include ${srctree}/arch/x86/pci/Makefile_32
-else
-include ${srctree}/arch/x86/pci/Makefile_64
-endif
+obj-y                           := i386.o init.o
+
+obj-$(CONFIG_PCI_BIOS)          += pcbios.o
+obj-$(CONFIG_PCI_MMCONFIG)      += mmconfig_$(BITS).o direct.o mmconfig-shared.o
+obj-$(CONFIG_PCI_DIRECT)        += direct.o
+obj-$(CONFIG_PCI_OLPC)          += olpc.o
+
+pci-y                           := fixup.o
+pci-$(CONFIG_ACPI)              += acpi.o
+pci-y                           += legacy.o irq.o
+
+pci-$(CONFIG_X86_VISWS)         += visws.o
+
+pci-$(CONFIG_X86_NUMAQ)         += numa.o
+
+obj-y                           += $(pci-y) common.o early.o
+obj-y                           += amd_bus.o
diff --git a/arch/x86/pci/Makefile_32 b/arch/x86/pci/Makefile_32
deleted file mode 100644
index 89ec35d00efd..000000000000
--- a/arch/x86/pci/Makefile_32
+++ /dev/null
@@ -1,24 +0,0 @@
-obj-y                           := i386.o init.o
-
-obj-$(CONFIG_PCI_BIOS)          += pcbios.o
-obj-$(CONFIG_PCI_MMCONFIG)      += mmconfig_32.o direct.o mmconfig-shared.o
-obj-$(CONFIG_PCI_DIRECT)        += direct.o
-obj-$(CONFIG_PCI_OLPC)          += olpc.o
-
-pci-y                           := fixup.o
-
-# Do not change the ordering here. There is a nasty init function
-# ordering dependency which breaks when you move acpi.o below
-# legacy/irq.o
-pci-$(CONFIG_ACPI)              += acpi.o
-pci-y                           += legacy.o irq.o
-
-# Careful: VISWS and NUMAQ overrule the pci-y above. The colons are
-# therefor correct. This needs a proper fix by distangling the code.
-pci-$(CONFIG_X86_VISWS)         := visws.o fixup.o
-pci-$(CONFIG_X86_NUMAQ)         := numa.o irq.o
-
-# Necessary for NUMAQ as well
-pci-$(CONFIG_NUMA)              += mp_bus_to_node.o
-
-obj-y                           += $(pci-y) common.o early.o
diff --git a/arch/x86/pci/Makefile_64 b/arch/x86/pci/Makefile_64
deleted file mode 100644
index 8fbd19832cf6..000000000000
--- a/arch/x86/pci/Makefile_64
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# Makefile for X86_64 specific PCI routines
-#
-# Reuse the i386 PCI subsystem
-#
-EXTRA_CFLAGS += -Iarch/x86/pci
-
-obj-y           := i386.o
-obj-$(CONFIG_PCI_DIRECT)+= direct.o
-obj-y           += fixup.o init.o
-obj-$(CONFIG_ACPI)      += acpi.o
-obj-y                   += legacy.o irq.o common.o early.o
-# mmconfig has a 64bit special
-obj-$(CONFIG_PCI_MMCONFIG) += mmconfig_64.o direct.o mmconfig-shared.o
-
-obj-y           += k8-bus_64.o
-
diff --git a/arch/x86/pci/acpi.c b/arch/x86/pci/acpi.c
index d95de2f199cd..19af06927fbc 100644
--- a/arch/x86/pci/acpi.c
+++ b/arch/x86/pci/acpi.c
@@ -171,8 +171,11 @@ struct pci_bus * __devinit pci_acpi_scan_root(struct acpi_device *device, int do
         if (node != -1)
                 set_mp_bus_to_node(busnum, node);
         else
-                node = get_mp_bus_to_node(busnum);
 #endif
+                node = get_mp_bus_to_node(busnum);
+
+        if (node != -1 && !node_online(node))
+                node = -1;
 
         /* Allocate per-root-bus (not per bus) arch-specific data.
          * TODO: leak; this memory is never freed.
@@ -204,22 +207,23 @@ struct pci_bus * __devinit pci_acpi_scan_root(struct acpi_device *device, int do
         if (!bus)
                 kfree(sd);
 
+        if (bus && node != -1) {
 #ifdef CONFIG_ACPI_NUMA
-        if (bus) {
-                if (pxm >= 0) {
+                if (pxm >= 0)
                         printk(KERN_DEBUG "bus %02x -> pxm %d -> node %d\n",
-                                busnum, pxm, pxm_to_node(pxm));
-                }
-        }
+                                busnum, pxm, node);
+#else
+                printk(KERN_DEBUG "bus %02x -> node %d\n",
+                        busnum, node);
 #endif
+        }
 
         if (bus && (pci_probe & PCI_USE__CRS))
                 get_current_resources(device, busnum, domain, bus);
         return bus;
 }
 
-extern int pci_routeirq;
-static int __init pci_acpi_init(void)
+int __init pci_acpi_init(void)
 {
         struct pci_dev *dev = NULL;
 
@@ -253,4 +257,3 @@ static int __init pci_acpi_init(void)
 
         return 0;
 }
-subsys_initcall(pci_acpi_init);
diff --git a/arch/x86/pci/k8-bus_64.c b/arch/x86/pci/amd_bus.c
index 5c2799c20e47..a18141ae3f02 100644
--- a/arch/x86/pci/k8-bus_64.c
+++ b/arch/x86/pci/amd_bus.c
@@ -1,40 +1,25 @@
 #include <linux/init.h>
 #include <linux/pci.h>
+#include <linux/topology.h>
+#include "pci.h"
+
+#ifdef CONFIG_X86_64
 #include <asm/pci-direct.h>
 #include <asm/mpspec.h>
 #include <linux/cpumask.h>
-#include <linux/topology.h>
+#endif
 
 /*
  * This discovers the pcibus <-> node mapping on AMD K8.
  * also get peer root bus resource for io,mmio
  */
 
-
-/*
- * sub bus (transparent) will use entres from 3 to store extra from root,
- * so need to make sure have enought slot there, increase PCI_BUS_NUM_RESOURCES?
- */
-#define RES_NUM 16
-struct pci_root_info {
-        char name[12];
-        unsigned int res_num;
-        struct resource res[RES_NUM];
-        int bus_min;
-        int bus_max;
-        int node;
-        int link;
-};
-
-/* 4 at this time, it may become to 32 */
-#define PCI_ROOT_NR 4
-static int pci_root_num;
-static struct pci_root_info pci_root_info[PCI_ROOT_NR];
-
 #ifdef CONFIG_NUMA
 
 #define BUS_NR 256
 
+#ifdef CONFIG_X86_64
+
 static int mp_bus_to_node[BUS_NR];
 
 void set_mp_bus_to_node(int busnum, int node)
@@ -61,7 +46,52 @@ int get_mp_bus_to_node(int busnum)
 
         return node;
 }
-#endif
+
+#else /* CONFIG_X86_32 */
+
+static unsigned char mp_bus_to_node[BUS_NR];
+
+void set_mp_bus_to_node(int busnum, int node)
+{
+        if (busnum >= 0 &&  busnum < BUS_NR)
+        mp_bus_to_node[busnum] = (unsigned char) node;
+}
+
+int get_mp_bus_to_node(int busnum)
+{
+        int node;
+
+        if (busnum < 0 || busnum > (BUS_NR - 1))
+                return 0;
+        node = mp_bus_to_node[busnum];
+        return node;
+}
+
+#endif /* CONFIG_X86_32 */
+
+#endif /* CONFIG_NUMA */
+
+#ifdef CONFIG_X86_64
+
+/*
+ * sub bus (transparent) will use entres from 3 to store extra from root,
+ * so need to make sure have enought slot there, increase PCI_BUS_NUM_RESOURCES?
+ */
+#define RES_NUM 16
+struct pci_root_info {
+        char name[12];
+        unsigned int res_num;
+        struct resource res[RES_NUM];
+        int bus_min;
+        int bus_max;
+        int node;
+        int link;
+};
+
+/* 4 at this time, it may become to 32 */
+#define PCI_ROOT_NR 4
+static int pci_root_num;
+static struct pci_root_info pci_root_info[PCI_ROOT_NR];
 
 void set_pci_bus_resources_arch_default(struct pci_bus *b)
 {
@@ -384,7 +414,7 @@ static int __init early_fill_mp_bus_info(void)
         /* need to take out [0, TOM) for RAM*/
         address = MSR_K8_TOP_MEM1;
         rdmsrl(address, val);
-        end = (val & 0xffffff8000000ULL);
+        end = (val & 0xffffff800000ULL);
         printk(KERN_INFO "TOM: %016lx aka %ldM\n", end, end>>20);
         if (end < (1ULL<<32))
                 update_range(range, 0, end - 1);
@@ -478,7 +508,7 @@ static int __init early_fill_mp_bus_info(void)
                 /* TOP_MEM2 */
                 address = MSR_K8_TOP_MEM2;
                 rdmsrl(address, val);
-                end = (val & 0xffffff8000000ULL);
+                end = (val & 0xffffff800000ULL);
                 printk(KERN_INFO "TOM2: %016lx aka %ldM\n", end, end>>20);
                 update_range(range, 1ULL<<32, end - 1);
         }
@@ -526,3 +556,31 @@ static int __init early_fill_mp_bus_info(void)
 }
 
 postcore_initcall(early_fill_mp_bus_info);
+
+#endif
+
+/* common 32/64 bit code */
+
+#define ENABLE_CF8_EXT_CFG      (1ULL << 46)
+
+static void enable_pci_io_ecs_per_cpu(void *unused)
+{
+        u64 reg;
+        rdmsrl(MSR_AMD64_NB_CFG, reg);
+        if (!(reg & ENABLE_CF8_EXT_CFG)) {
+                reg |= ENABLE_CF8_EXT_CFG;
+                wrmsrl(MSR_AMD64_NB_CFG, reg);
+        }
+}
+
+static int __init enable_pci_io_ecs(void)
+{
+        /* assume all cpus from fam10h have IO ECS */
+        if (boot_cpu_data.x86 < 0x10)
+                return 0;
+        on_each_cpu(enable_pci_io_ecs_per_cpu, NULL, 1, 1);
+        pci_probe |= PCI_HAS_IO_ECS;
+        return 0;
+}
+
+postcore_initcall(enable_pci_io_ecs);
diff --git a/arch/x86/pci/common.c b/arch/x86/pci/common.c
index 6e64aaf00d1d..20b9f59f95df 100644
--- a/arch/x86/pci/common.c
+++ b/arch/x86/pci/common.c
@@ -384,7 +384,7 @@ struct pci_bus * __devinit pcibios_scan_root(int busnum)
 
 extern u8 pci_cache_line_size;
 
-static int __init pcibios_init(void)
+int __init pcibios_init(void)
 {
         struct cpuinfo_x86 *c = &boot_cpu_data;
 
@@ -411,8 +411,6 @@ static int __init pcibios_init(void)
         return 0;
 }
 
-subsys_initcall(pcibios_init);
-
 char * __devinit  pcibios_setup(char *str)
 {
         if (!strcmp(str, "off")) {
diff --git a/arch/x86/pci/direct.c b/arch/x86/pci/direct.c
index 21d1e0e0d535..9915293500fb 100644
--- a/arch/x86/pci/direct.c
+++ b/arch/x86/pci/direct.c
@@ -8,18 +8,21 @@
 #include "pci.h"
 
 /*
- * Functions for accessing PCI configuration space with type 1 accesses
+ * Functions for accessing PCI base (first 256 bytes) and extended
+ * (4096 bytes per PCI function) configuration space with type 1
+ * accesses.
  */
 
 #define PCI_CONF1_ADDRESS(bus, devfn, reg) \
-        (0x80000000 | (bus << 16) | (devfn << 8) | (reg & ~3))
+        (0x80000000 | ((reg & 0xF00) << 16) | (bus << 16) \
+        | (devfn << 8) | (reg & 0xFC))
 
 static int pci_conf1_read(unsigned int seg, unsigned int bus,
                           unsigned int devfn, int reg, int len, u32 *value)
 {
         unsigned long flags;
 
-        if ((bus > 255) || (devfn > 255) || (reg > 255)) {
+        if ((bus > 255) || (devfn > 255) || (reg > 4095)) {
                 *value = -1;
                 return -EINVAL;
         }
@@ -50,7 +53,7 @@ static int pci_conf1_write(unsigned int seg, unsigned int bus,
 {
         unsigned long flags;
 
-        if ((bus > 255) || (devfn > 255) || (reg > 255)) 
+        if ((bus > 255) || (devfn > 255) || (reg > 4095))
                 return -EINVAL;
 
         spin_lock_irqsave(&pci_config_lock, flags);
@@ -260,10 +263,18 @@ void __init pci_direct_init(int type)
                 return;
         printk(KERN_INFO "PCI: Using configuration type %d for base access\n",
                  type);
-        if (type == 1)
+        if (type == 1) {
                 raw_pci_ops = &pci_direct_conf1;
-        else
-                raw_pci_ops = &pci_direct_conf2;
+                if (raw_pci_ext_ops)
+                        return;
+                if (!(pci_probe & PCI_HAS_IO_ECS))
+                        return;
+                printk(KERN_INFO "PCI: Using configuration type 1 "
+                       "for extended access\n");
+                raw_pci_ext_ops = &pci_direct_conf1;
+                return;
+        }
+        raw_pci_ops = &pci_direct_conf2;
 }
 
 int __init pci_direct_probe(void)
diff --git a/arch/x86/pci/i386.c b/arch/x86/pci/i386.c
index 10fb308fded8..2aafb67dc5f1 100644
--- a/arch/x86/pci/i386.c
+++ b/arch/x86/pci/i386.c
@@ -299,9 +299,9 @@ int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
                 return -EINVAL;
 
         prot = pgprot_val(vma->vm_page_prot);
-        if (pat_wc_enabled && write_combine)
+        if (pat_enabled && write_combine)
                 prot |= _PAGE_CACHE_WC;
-        else if (pat_wc_enabled || boot_cpu_data.x86 > 3)
+        else if (pat_enabled || boot_cpu_data.x86 > 3)
                 /*
                  * ioremap() and ioremap_nocache() defaults to UC MINUS for now.
                  * To avoid attribute conflicts, request UC MINUS here
@@ -334,7 +334,9 @@ int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
                 flags = new_flags;
         }
 
-        if (vma->vm_pgoff <= max_pfn_mapped &&
+        if (((vma->vm_pgoff < max_low_pfn_mapped) ||
+             (vma->vm_pgoff >= (1UL<<(32 - PAGE_SHIFT)) &&
+              vma->vm_pgoff < max_pfn_mapped)) &&
             ioremap_change_attr((unsigned long)__va(addr), len, flags)) {
                 free_memtype(addr, addr + len);
                 return -EINVAL;
diff --git a/arch/x86/pci/init.c b/arch/x86/pci/init.c
index b821f4462d99..d6c950f81858 100644
--- a/arch/x86/pci/init.c
+++ b/arch/x86/pci/init.c
@@ -4,7 +4,7 @@
 
 /* arch_initcall has too random ordering, so call the initializers
    in the right sequence from here. */
-static __init int pci_access_init(void)
+static __init int pci_arch_init(void)
 {
 #ifdef CONFIG_PCI_DIRECT
         int type = 0;
@@ -40,4 +40,4 @@ static __init int pci_access_init(void)
 
         return 0;
 }
-arch_initcall(pci_access_init);
+arch_initcall(pci_arch_init);
diff --git a/arch/x86/pci/irq.c b/arch/x86/pci/irq.c
index ca8df9c260bc..dc568c6b83f8 100644
--- a/arch/x86/pci/irq.c
+++ b/arch/x86/pci/irq.c
@@ -11,8 +11,8 @@
 #include <linux/slab.h>
 #include <linux/interrupt.h>
 #include <linux/dmi.h>
-#include <asm/io.h>
-#include <asm/smp.h>
+#include <linux/io.h>
+#include <linux/smp.h>
 #include <asm/io_apic.h>
 #include <linux/irq.h>
 #include <linux/acpi.h>
@@ -61,7 +61,7 @@ void (*pcibios_disable_irq)(struct pci_dev *dev) = NULL;
  *  and perform checksum verification.
  */
 
-static inline struct irq_routing_table * pirq_check_routing_table(u8 *addr)
+static inline struct irq_routing_table *pirq_check_routing_table(u8 *addr)
 {
         struct irq_routing_table *rt;
         int i;
@@ -74,7 +74,7 @@ static inline struct irq_routing_table * pirq_check_routing_table(u8 *addr)
             rt->size < sizeof(struct irq_routing_table))
                 return NULL;
         sum = 0;
-        for (i=0; i < rt->size; i++)
+        for (i = 0; i < rt->size; i++)
                 sum += addr[i];
         if (!sum) {
                 DBG(KERN_DEBUG "PCI: Interrupt Routing Table found at 0x%p\n", rt);
@@ -100,7 +100,7 @@ static struct irq_routing_table * __init pirq_find_routing_table(void)
                         return rt;
                 printk(KERN_WARNING "PCI: PIRQ table NOT found at pirqaddr\n");
         }
-        for(addr = (u8 *) __va(0xf0000); addr < (u8 *) __va(0x100000); addr += 16) {
+        for (addr = (u8 *) __va(0xf0000); addr < (u8 *) __va(0x100000); addr += 16) {
                 rt = pirq_check_routing_table(addr);
                 if (rt)
                         return rt;
@@ -122,20 +122,20 @@ static void __init pirq_peer_trick(void)
         struct irq_info *e;
 
         memset(busmap, 0, sizeof(busmap));
-        for(i=0; i < (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info); i++) {
+        for (i = 0; i < (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info); i++) {
                 e = &rt->slots[i];
 #ifdef DEBUG
                 {
                         int j;
                         DBG(KERN_DEBUG "%02x:%02x slot=%02x", e->bus, e->devfn/8, e->slot);
-                        for(j=0; j<4; j++)
+                        for (j = 0; j < 4; j++)
                                 DBG(" %d:%02x/%04x", j, e->irq[j].link, e->irq[j].bitmap);
                         DBG("\n");
                 }
 #endif
                 busmap[e->bus] = 1;
         }
-        for(i = 1; i < 256; i++) {
+        for (i = 1; i < 256; i++) {
                 int node;
                 if (!busmap[i] || pci_find_bus(0, i))
                         continue;
@@ -285,7 +285,7 @@ static int pirq_ite_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
         static const unsigned char pirqmap[4] = { 1, 0, 2, 3 };
 
         WARN_ON_ONCE(pirq > 4);
-        return read_config_nybble(router,0x43, pirqmap[pirq-1]);
+        return read_config_nybble(router, 0x43, pirqmap[pirq-1]);
 }
 
 static int pirq_ite_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
@@ -314,7 +314,7 @@ static int pirq_opti_set(struct pci_dev *router, struct pci_dev *dev, int pirq,
 
 /*
  * Cyrix: nibble offset 0x5C
- * 0x5C bits 7:4 is INTB bits 3:0 is INTA 
+ * 0x5C bits 7:4 is INTB bits 3:0 is INTA
  * 0x5D bits 7:4 is INTD bits 3:0 is INTC
  */
 static int pirq_cyrix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
@@ -350,7 +350,7 @@ static int pirq_cyrix_set(struct pci_dev *router, struct pci_dev *dev, int pirq,
  *      Apparently there are systems implementing PCI routing table using
  *      link values 0x01-0x04 and others using 0x41-0x44 for PCI INTA..D.
  *      We try our best to handle both link mappings.
- *      
+ *
  *      Currently (2003-05-21) it appears most SiS chipsets follow the
  *      definition of routing registers from the SiS-5595 southbridge.
  *      According to the SiS 5595 datasheets the revision id's of the
@@ -370,7 +370,7 @@ static int pirq_cyrix_set(struct pci_dev *router, struct pci_dev *dev, int pirq,
  *
  *      0x62:   USBIRQ:
  *              bit 6 OHCI function disabled (0), enabled (1)
- *      
+ *
  *      0x6a:   ACPI/SCI IRQ: bits 4-6 reserved
  *
  *      0x7e:   Data Acq. Module IRQ - bits 4-6 reserved
@@ -487,9 +487,7 @@ static int pirq_amd756_get(struct pci_dev *router, struct pci_dev *dev, int pirq
         u8 irq;
         irq = 0;
         if (pirq <= 4)
-        {
                 irq = read_config_nybble(router, 0x56, pirq - 1);
-        }
         printk(KERN_INFO "AMD756: dev %04x:%04x, router pirq : %d get irq : %2d\n",
                 dev->vendor, dev->device, pirq, irq);
         return irq;
@@ -497,12 +495,10 @@ static int pirq_amd756_get(struct pci_dev *router, struct pci_dev *dev, int pirq
 
 static int pirq_amd756_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
 {
-        printk(KERN_INFO "AMD756: dev %04x:%04x, router pirq : %d SET irq : %2d\n", 
+        printk(KERN_INFO "AMD756: dev %04x:%04x, router pirq : %d SET irq : %2d\n",
                 dev->vendor, dev->device, pirq, irq);
         if (pirq <= 4)
-        {
                 write_config_nybble(router, 0x56, pirq - 1, irq);
-        }
         return 1;
 }
 
@@ -549,50 +545,49 @@ static __init int intel_router_probe(struct irq_router *r, struct pci_dev *route
         if (pci_dev_present(pirq_440gx))
                 return 0;
 
-        switch(device)
-        {
-                case PCI_DEVICE_ID_INTEL_82371FB_0:
-                case PCI_DEVICE_ID_INTEL_82371SB_0:
-                case PCI_DEVICE_ID_INTEL_82371AB_0:
-                case PCI_DEVICE_ID_INTEL_82371MX:
-                case PCI_DEVICE_ID_INTEL_82443MX_0:
-                case PCI_DEVICE_ID_INTEL_82801AA_0:
-                case PCI_DEVICE_ID_INTEL_82801AB_0:
-                case PCI_DEVICE_ID_INTEL_82801BA_0:
-                case PCI_DEVICE_ID_INTEL_82801BA_10:
-                case PCI_DEVICE_ID_INTEL_82801CA_0:
-                case PCI_DEVICE_ID_INTEL_82801CA_12:
-                case PCI_DEVICE_ID_INTEL_82801DB_0:
-                case PCI_DEVICE_ID_INTEL_82801E_0:
-                case PCI_DEVICE_ID_INTEL_82801EB_0:
-                case PCI_DEVICE_ID_INTEL_ESB_1:
-                case PCI_DEVICE_ID_INTEL_ICH6_0:
-                case PCI_DEVICE_ID_INTEL_ICH6_1:
-                case PCI_DEVICE_ID_INTEL_ICH7_0:
-                case PCI_DEVICE_ID_INTEL_ICH7_1:
-                case PCI_DEVICE_ID_INTEL_ICH7_30:
-                case PCI_DEVICE_ID_INTEL_ICH7_31:
-                case PCI_DEVICE_ID_INTEL_ESB2_0:
-                case PCI_DEVICE_ID_INTEL_ICH8_0:
-                case PCI_DEVICE_ID_INTEL_ICH8_1:
-                case PCI_DEVICE_ID_INTEL_ICH8_2:
-                case PCI_DEVICE_ID_INTEL_ICH8_3:
-                case PCI_DEVICE_ID_INTEL_ICH8_4:
-                case PCI_DEVICE_ID_INTEL_ICH9_0:
-                case PCI_DEVICE_ID_INTEL_ICH9_1:
-                case PCI_DEVICE_ID_INTEL_ICH9_2:
-                case PCI_DEVICE_ID_INTEL_ICH9_3:
-                case PCI_DEVICE_ID_INTEL_ICH9_4:
-                case PCI_DEVICE_ID_INTEL_ICH9_5:
-                case PCI_DEVICE_ID_INTEL_TOLAPAI_0:
-                case PCI_DEVICE_ID_INTEL_ICH10_0:
-                case PCI_DEVICE_ID_INTEL_ICH10_1:
-                case PCI_DEVICE_ID_INTEL_ICH10_2:
-                case PCI_DEVICE_ID_INTEL_ICH10_3:
-                        r->name = "PIIX/ICH";
-                        r->get = pirq_piix_get;
-                        r->set = pirq_piix_set;
-                        return 1;
+        switch (device) {
+        case PCI_DEVICE_ID_INTEL_82371FB_0:
+        case PCI_DEVICE_ID_INTEL_82371SB_0:
+        case PCI_DEVICE_ID_INTEL_82371AB_0:
+        case PCI_DEVICE_ID_INTEL_82371MX:
+        case PCI_DEVICE_ID_INTEL_82443MX_0:
+        case PCI_DEVICE_ID_INTEL_82801AA_0:
+        case PCI_DEVICE_ID_INTEL_82801AB_0:
+        case PCI_DEVICE_ID_INTEL_82801BA_0:
+        case PCI_DEVICE_ID_INTEL_82801BA_10:
+        case PCI_DEVICE_ID_INTEL_82801CA_0:
+        case PCI_DEVICE_ID_INTEL_82801CA_12:
+        case PCI_DEVICE_ID_INTEL_82801DB_0:
+        case PCI_DEVICE_ID_INTEL_82801E_0:
+        case PCI_DEVICE_ID_INTEL_82801EB_0:
+        case PCI_DEVICE_ID_INTEL_ESB_1:
+        case PCI_DEVICE_ID_INTEL_ICH6_0:
+        case PCI_DEVICE_ID_INTEL_ICH6_1:
+        case PCI_DEVICE_ID_INTEL_ICH7_0:
+        case PCI_DEVICE_ID_INTEL_ICH7_1:
+        case PCI_DEVICE_ID_INTEL_ICH7_30:
+        case PCI_DEVICE_ID_INTEL_ICH7_31:
+        case PCI_DEVICE_ID_INTEL_ESB2_0:
+        case PCI_DEVICE_ID_INTEL_ICH8_0:
+        case PCI_DEVICE_ID_INTEL_ICH8_1:
+        case PCI_DEVICE_ID_INTEL_ICH8_2:
+        case PCI_DEVICE_ID_INTEL_ICH8_3:
+        case PCI_DEVICE_ID_INTEL_ICH8_4:
+        case PCI_DEVICE_ID_INTEL_ICH9_0:
+        case PCI_DEVICE_ID_INTEL_ICH9_1:
+        case PCI_DEVICE_ID_INTEL_ICH9_2:
+        case PCI_DEVICE_ID_INTEL_ICH9_3:
+        case PCI_DEVICE_ID_INTEL_ICH9_4:
+        case PCI_DEVICE_ID_INTEL_ICH9_5:
+        case PCI_DEVICE_ID_INTEL_TOLAPAI_0:
+        case PCI_DEVICE_ID_INTEL_ICH10_0:
+        case PCI_DEVICE_ID_INTEL_ICH10_1:
+        case PCI_DEVICE_ID_INTEL_ICH10_2:
+        case PCI_DEVICE_ID_INTEL_ICH10_3:
+                r->name = "PIIX/ICH";
+                r->get = pirq_piix_get;
+                r->set = pirq_piix_set;
+                return 1;
         }
         return 0;
 }
@@ -606,7 +601,7 @@ static __init int via_router_probe(struct irq_router *r,
          * workarounds for some buggy BIOSes
          */
         if (device == PCI_DEVICE_ID_VIA_82C586_0) {
-                switch(router->device) {
+                switch (router->device) {
                 case PCI_DEVICE_ID_VIA_82C686:
                         /*
                          * Asus k7m bios wrongly reports 82C686A
@@ -631,7 +626,7 @@ static __init int via_router_probe(struct irq_router *r,
                 }
         }
 
-        switch(device) {
+        switch (device) {
         case PCI_DEVICE_ID_VIA_82C586_0:
                 r->name = "VIA";
                 r->get = pirq_via586_get;
@@ -654,13 +649,12 @@ static __init int via_router_probe(struct irq_router *r,
 
 static __init int vlsi_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
 {
-        switch(device)
-        {
-                case PCI_DEVICE_ID_VLSI_82C534:
-                        r->name = "VLSI 82C534";
-                        r->get = pirq_vlsi_get;
-                        r->set = pirq_vlsi_set;
-                        return 1;
+        switch (device) {
+        case PCI_DEVICE_ID_VLSI_82C534:
+                r->name = "VLSI 82C534";
+                r->get = pirq_vlsi_get;
+                r->set = pirq_vlsi_set;
+                return 1;
         }
         return 0;
 }
@@ -668,14 +662,13 @@ static __init int vlsi_router_probe(struct irq_router *r, struct pci_dev *router
 
 static __init int serverworks_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
 {
-        switch(device)
-        {
-                case PCI_DEVICE_ID_SERVERWORKS_OSB4:
-                case PCI_DEVICE_ID_SERVERWORKS_CSB5:
-                        r->name = "ServerWorks";
-                        r->get = pirq_serverworks_get;
-                        r->set = pirq_serverworks_set;
-                        return 1;
+        switch (device) {
+        case PCI_DEVICE_ID_SERVERWORKS_OSB4:
+        case PCI_DEVICE_ID_SERVERWORKS_CSB5:
+                r->name = "ServerWorks";
+                r->get = pirq_serverworks_get;
+                r->set = pirq_serverworks_set;
+                return 1;
         }
         return 0;
 }
@@ -684,7 +677,7 @@ static __init int sis_router_probe(struct irq_router *r, struct pci_dev *router,
 {
         if (device != PCI_DEVICE_ID_SI_503)
                 return 0;
-                
+
         r->name = "SIS";
         r->get = pirq_sis_get;
         r->set = pirq_sis_set;
@@ -693,47 +686,43 @@ static __init int sis_router_probe(struct irq_router *r, struct pci_dev *router,
 
 static __init int cyrix_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
 {
-        switch(device)
-        {
-                case PCI_DEVICE_ID_CYRIX_5520:
-                        r->name = "NatSemi";
-                        r->get = pirq_cyrix_get;
-                        r->set = pirq_cyrix_set;
-                        return 1;
+        switch (device) {
+        case PCI_DEVICE_ID_CYRIX_5520:
+                r->name = "NatSemi";
+                r->get = pirq_cyrix_get;
+                r->set = pirq_cyrix_set;
+                return 1;
         }
         return 0;
 }
 
 static __init int opti_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
 {
-        switch(device)
-        {
-                case PCI_DEVICE_ID_OPTI_82C700:
-                        r->name = "OPTI";
-                        r->get = pirq_opti_get;
-                        r->set = pirq_opti_set;
-                        return 1;
+        switch (device) {
+        case PCI_DEVICE_ID_OPTI_82C700:
+                r->name = "OPTI";
+                r->get = pirq_opti_get;
+                r->set = pirq_opti_set;
+                return 1;
         }
         return 0;
 }
 
 static __init int ite_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
 {
-        switch(device)
-        {
-                case PCI_DEVICE_ID_ITE_IT8330G_0:
-                        r->name = "ITE";
-                        r->get = pirq_ite_get;
-                        r->set = pirq_ite_set;
-                        return 1;
+        switch (device) {
+        case PCI_DEVICE_ID_ITE_IT8330G_0:
+                r->name = "ITE";
+                r->get = pirq_ite_get;
+                r->set = pirq_ite_set;
+                return 1;
         }
         return 0;
 }
 
 static __init int ali_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
 {
-        switch(device)
-        {
+        switch (device) {
         case PCI_DEVICE_ID_AL_M1533:
         case PCI_DEVICE_ID_AL_M1563:
                 printk(KERN_DEBUG "PCI: Using ALI IRQ Router\n");
@@ -747,25 +736,24 @@ static __init int ali_router_probe(struct irq_router *r, struct pci_dev *router,
 
 static __init int amd_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
 {
-        switch(device)
-        {
-                case PCI_DEVICE_ID_AMD_VIPER_740B:
-                        r->name = "AMD756";
-                        break;
-                case PCI_DEVICE_ID_AMD_VIPER_7413:
-                        r->name = "AMD766";
-                        break;
-                case PCI_DEVICE_ID_AMD_VIPER_7443:
-                        r->name = "AMD768";
-                        break;
-                default:
-                        return 0;
+        switch (device) {
+        case PCI_DEVICE_ID_AMD_VIPER_740B:
+                r->name = "AMD756";
+                break;
+        case PCI_DEVICE_ID_AMD_VIPER_7413:
+                r->name = "AMD766";
+                break;
+        case PCI_DEVICE_ID_AMD_VIPER_7443:
+                r->name = "AMD768";
+                break;
+        default:
+                return 0;
         }
         r->get = pirq_amd756_get;
         r->set = pirq_amd756_set;
         return 1;
 }
-                
+
 static __init int pico_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
 {
         switch (device) {
@@ -807,7 +795,7 @@ static struct pci_dev *pirq_router_dev;
  *      FIXME: should we have an option to say "generic for
  *      chipset" ?
  */
- 
+
 static void __init pirq_find_router(struct irq_router *r)
 {
         struct irq_routing_table *rt = pirq_table;
@@ -826,7 +814,7 @@ static void __init pirq_find_router(struct irq_router *r)
         r->name = "default";
         r->get = NULL;
         r->set = NULL;
-        
+
         DBG(KERN_DEBUG "PCI: Attempting to find IRQ router for %04x:%04x\n",
             rt->rtr_vendor, rt->rtr_device);
 
@@ -837,7 +825,7 @@ static void __init pirq_find_router(struct irq_router *r)
                 return;
         }
 
-        for( h = pirq_routers; h->vendor; h++) {
+        for (h = pirq_routers; h->vendor; h++) {
                 /* First look for a router match */
                 if (rt->rtr_vendor == h->vendor && h->probe(r, pirq_router_dev, rt->rtr_device))
                         break;
@@ -889,7 +877,7 @@ static int pcibios_lookup_irq(struct pci_dev *dev, int assign)
 
         if (!pirq_table)
                 return 0;
-        
+
         DBG(KERN_DEBUG "IRQ for %s[%c]", pci_name(dev), 'A' + pin);
         info = pirq_get_info(dev);
         if (!info) {
@@ -928,8 +916,10 @@ static int pcibios_lookup_irq(struct pci_dev *dev, int assign)
          */
         newirq = dev->irq;
         if (newirq && !((1 << newirq) & mask)) {
-                if ( pci_probe & PCI_USE_PIRQ_MASK) newirq = 0;
-                else printk("\n" KERN_WARNING
+                if (pci_probe & PCI_USE_PIRQ_MASK)
+                        newirq = 0;
+                else
+                        printk("\n" KERN_WARNING
                         "PCI: IRQ %i for device %s doesn't match PIRQ mask "
                         "- try pci=usepirqmask\n" KERN_DEBUG, newirq,
                         pci_name(dev));
@@ -949,8 +939,8 @@ static int pcibios_lookup_irq(struct pci_dev *dev, int assign)
                 irq = pirq & 0xf;
                 DBG(" -> hardcoded IRQ %d\n", irq);
                 msg = "Hardcoded";
-        } else if ( r->get && (irq = r->get(pirq_router_dev, dev, pirq)) && \
-        ((!(pci_probe & PCI_USE_PIRQ_MASK)) || ((1 << irq) & mask)) ) {
+        } else if (r->get && (irq = r->get(pirq_router_dev, dev, pirq)) && \
+        ((!(pci_probe & PCI_USE_PIRQ_MASK)) || ((1 << irq) & mask))) {
                 DBG(" -> got IRQ %d\n", irq);
                 msg = "Found";
                 eisa_set_level_irq(irq);
@@ -985,15 +975,15 @@ static int pcibios_lookup_irq(struct pci_dev *dev, int assign)
                         continue;
                 if (info->irq[pin].link == pirq) {
                         /* We refuse to override the dev->irq information. Give a warning! */
-                        if ( dev2->irq && dev2->irq != irq && \
+                        if (dev2->irq && dev2->irq != irq && \
                         (!(pci_probe & PCI_USE_PIRQ_MASK) || \
-                        ((1 << dev2->irq) & mask)) ) {
+                        ((1 << dev2->irq) & mask))) {
 #ifndef CONFIG_PCI_MSI
-                                printk(KERN_INFO "IRQ routing conflict for %s, have irq %d, want irq %d\n",
+                                printk(KERN_INFO "IRQ routing conflict for %s, have irq %d, want irq %d\n",
                                        pci_name(dev2), dev2->irq, irq);
 #endif
-                                continue;
-                        }
+                                continue;
+                        }
                         dev2->irq = irq;
                         pirq_penalty[irq]++;
                         if (dev != dev2)
@@ -1031,8 +1021,7 @@ static void __init pcibios_fixup_irqs(void)
                 /*
                  * Recalculate IRQ numbers if we use the I/O APIC.
                  */
-                if (io_apic_assign_pci_irqs)
-                {
+                if (io_apic_assign_pci_irqs) {
                         int irq;
 
                         if (pin) {
@@ -1045,10 +1034,10 @@ static void __init pcibios_fixup_irqs(void)
          * busses itself so we should get into this branch reliably.
          */
                                 if (irq < 0 && dev->bus->parent) { /* go back to the bridge */
-                                        struct pci_dev * bridge = dev->bus->self;
+                                        struct pci_dev *bridge = dev->bus->self;
 
                                         pin = (pin + PCI_SLOT(dev->devfn)) % 4;
-                                        irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number, 
+                                        irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number,
                                                         PCI_SLOT(bridge->devfn), pin);
                                         if (irq >= 0)
                                                 printk(KERN_WARNING "PCI: using PPB %s[%c] to get irq %d\n",
@@ -1118,7 +1107,7 @@ static struct dmi_system_id __initdata pciirq_dmi_table[] = {
         { }
 };
 
-static int __init pcibios_irq_init(void)
+int __init pcibios_irq_init(void)
 {
         DBG(KERN_DEBUG "PCI: IRQ init\n");
 
@@ -1138,7 +1127,7 @@ static int __init pcibios_irq_init(void)
                 pirq_find_router(&pirq_router);
                 if (pirq_table->exclusive_irqs) {
                         int i;
-                        for (i=0; i<16; i++)
+                        for (i = 0; i < 16; i++)
                                 if (!(pirq_table->exclusive_irqs & (1 << i)))
                                         pirq_penalty[i] += 100;
                 }
@@ -1153,9 +1142,6 @@ static int __init pcibios_irq_init(void)
         return 0;
 }
 
-subsys_initcall(pcibios_irq_init);
-
-
 static void pirq_penalize_isa_irq(int irq, int active)
 {
         /*
@@ -1203,10 +1189,10 @@ static int pirq_enable_irq(struct pci_dev *dev)
                          */
                         temp_dev = dev;
                         while (irq < 0 && dev->bus->parent) { /* go back to the bridge */
-                                struct pci_dev * bridge = dev->bus->self;
+                                struct pci_dev *bridge = dev->bus->self;
 
                                 pin = (pin + PCI_SLOT(dev->devfn)) % 4;
-                                irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number, 
+                                irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number,
                                                 PCI_SLOT(bridge->devfn), pin);
                                 if (irq >= 0)
                                         printk(KERN_WARNING "PCI: using PPB %s[%c] to get irq %d\n",
diff --git a/arch/x86/pci/legacy.c b/arch/x86/pci/legacy.c
index a67921ce60af..132876cc6fca 100644
--- a/arch/x86/pci/legacy.c
+++ b/arch/x86/pci/legacy.c
@@ -55,4 +55,18 @@ static int __init pci_legacy_init(void)
         return 0;
 }
 
-subsys_initcall(pci_legacy_init);
+int __init pci_subsys_init(void)
+{
+#ifdef CONFIG_ACPI
+        pci_acpi_init();
+#endif
+        pci_legacy_init();
+        pcibios_irq_init();
+#ifdef CONFIG_X86_NUMAQ
+        pci_numa_init();
+#endif
+        pcibios_init();
+
+        return 0;
+}
+subsys_initcall(pci_subsys_init);
diff --git a/arch/x86/pci/mmconfig-shared.c b/arch/x86/pci/mmconfig-shared.c
index 0cfebecf2a8f..23faaa890ffc 100644
--- a/arch/x86/pci/mmconfig-shared.c
+++ b/arch/x86/pci/mmconfig-shared.c
@@ -374,7 +374,7 @@ reject:
 
 static int __initdata known_bridge;
 
-void __init __pci_mmcfg_init(int early)
+static void __init __pci_mmcfg_init(int early)
 {
         /* MMCONFIG disabled */
         if ((pci_probe & PCI_PROBE_MMCONF) == 0)
diff --git a/arch/x86/pci/mp_bus_to_node.c b/arch/x86/pci/mp_bus_to_node.c
deleted file mode 100644
index 022943999b84..000000000000
--- a/arch/x86/pci/mp_bus_to_node.c
+++ /dev/null
@@ -1,23 +0,0 @@
-#include <linux/pci.h>
-#include <linux/init.h>
-#include <linux/topology.h>
-
-#define BUS_NR 256
-
-static unsigned char mp_bus_to_node[BUS_NR];
-
-void set_mp_bus_to_node(int busnum, int node)
-{
-        if (busnum >= 0 &&  busnum < BUS_NR)
-        mp_bus_to_node[busnum] = (unsigned char) node;
-}
-
-int get_mp_bus_to_node(int busnum)
-{
-        int node;
-
-        if (busnum < 0 || busnum > (BUS_NR - 1))
-                return 0;
-        node = mp_bus_to_node[busnum];
-        return node;
-}
diff --git a/arch/x86/pci/numa.c b/arch/x86/pci/numa.c
index d9afbae5092b..8b5ca1966731 100644
--- a/arch/x86/pci/numa.c
+++ b/arch/x86/pci/numa.c
@@ -6,45 +6,21 @@
 #include <linux/init.h>
 #include <linux/nodemask.h>
 #include <mach_apic.h>
+#include <asm/mpspec.h>
 #include "pci.h"
 
 #define XQUAD_PORTIO_BASE 0xfe400000
 #define XQUAD_PORTIO_QUAD 0x40000  /* 256k per quad. */
 
-int mp_bus_id_to_node[MAX_MP_BUSSES];
 #define BUS2QUAD(global) (mp_bus_id_to_node[global])
 
-int mp_bus_id_to_local[MAX_MP_BUSSES];
 #define BUS2LOCAL(global) (mp_bus_id_to_local[global])
 
-void mpc_oem_bus_info(struct mpc_config_bus *m, char *name,
-        struct mpc_config_translation *translation)
-{
-        int quad = translation->trans_quad;
-        int local = translation->trans_local;
-
-        mp_bus_id_to_node[m->mpc_busid] = quad;
-        mp_bus_id_to_local[m->mpc_busid] = local;
-        printk(KERN_INFO "Bus #%d is %s (node %d)\n",
-               m->mpc_busid, name, quad);
-}
-
-int quad_local_to_mp_bus_id [NR_CPUS/4][4];
 #define QUADLOCAL2BUS(quad,local) (quad_local_to_mp_bus_id[quad][local])
-void mpc_oem_pci_bus(struct mpc_config_bus *m,
-        struct mpc_config_translation *translation)
-{
-        int quad = translation->trans_quad;
-        int local = translation->trans_local;
-
-        quad_local_to_mp_bus_id[quad][local] = m->mpc_busid;
-}
 
 /* Where the IO area was mapped on multiquad, always 0 otherwise */
 void *xquad_portio;
-#ifdef CONFIG_X86_NUMAQ
 EXPORT_SYMBOL(xquad_portio);
-#endif
 
 #define XQUAD_PORT_ADDR(port, quad) (xquad_portio + (XQUAD_PORTIO_QUAD*quad) + port)
 
@@ -175,10 +151,13 @@ static void __devinit pci_fixup_i450nx(struct pci_dev *d)
 }
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, pci_fixup_i450nx);
 
-static int __init pci_numa_init(void)
+int __init pci_numa_init(void)
 {
         int quad;
 
+        if (!found_numaq)
+                return 0;
+
         raw_pci_ops = &pci_direct_conf1_mq;
 
         if (pcibios_scanned++)
@@ -197,5 +176,3 @@ static int __init pci_numa_init(void)
                 }
         return 0;
 }
-
-subsys_initcall(pci_numa_init);
diff --git a/arch/x86/pci/pci.h b/arch/x86/pci/pci.h
index 720c4c554534..b2270a55b0cf 100644
--- a/arch/x86/pci/pci.h
+++ b/arch/x86/pci/pci.h
@@ -27,6 +27,7 @@
 #define PCI_CAN_SKIP_ISA_ALIGN  0x8000
 #define PCI_USE__CRS            0x10000
 #define PCI_CHECK_ENABLE_AMD_MMCONF     0x20000
+#define PCI_HAS_IO_ECS          0x40000
 
 extern unsigned int pci_probe;
 extern unsigned long pirq_table_addr;
@@ -38,9 +39,6 @@ enum pci_bf_sort_state {
         pci_dmi_bf,
 };
 
-extern void __init dmi_check_pciprobe(void);
-extern void __init dmi_check_skip_isa_align(void);
-
 /* pci-i386.c */
 
 extern unsigned int pcibios_max_latency;
@@ -98,10 +96,19 @@ extern struct pci_raw_ops *raw_pci_ext_ops;
 
 extern struct pci_raw_ops pci_direct_conf1;
 
+/* arch_initcall level */
 extern int pci_direct_probe(void);
 extern void pci_direct_init(int type);
 extern void pci_pcbios_init(void);
 extern int pci_olpc_init(void);
+extern void __init dmi_check_pciprobe(void);
+extern void __init dmi_check_skip_isa_align(void);
+
+/* some common used subsys_initcalls */
+extern int __init pci_acpi_init(void);
+extern int __init pcibios_irq_init(void);
+extern int __init pci_numa_init(void);
+extern int __init pcibios_init(void);
 
 /* pci-mmconfig.c */
 
diff --git a/arch/x86/pci/visws.c b/arch/x86/pci/visws.c
index c2df4e97eed6..1a7bed492bb1 100644
--- a/arch/x86/pci/visws.c
+++ b/arch/x86/pci/visws.c
@@ -8,18 +8,19 @@
 #include <linux/pci.h>
 #include <linux/init.h>
 
-#include "cobalt.h"
-#include "lithium.h"
+#include <asm/setup.h>
+#include <asm/visws/cobalt.h>
+#include <asm/visws/lithium.h>
 
 #include "pci.h"
 
 static int pci_visws_enable_irq(struct pci_dev *dev) { return 0; }
 static void pci_visws_disable_irq(struct pci_dev *dev) { }
 
-int (*pcibios_enable_irq)(struct pci_dev *dev) = &pci_visws_enable_irq;
-void (*pcibios_disable_irq)(struct pci_dev *dev) = &pci_visws_disable_irq;
+/* int (*pcibios_enable_irq)(struct pci_dev *dev) = &pci_visws_enable_irq; */
+/* void (*pcibios_disable_irq)(struct pci_dev *dev) = &pci_visws_disable_irq; */
 
-void __init pcibios_penalize_isa_irq(int irq, int active) {}
+/* void __init pcibios_penalize_isa_irq(int irq, int active) {} */
 
 
 unsigned int pci_bus0, pci_bus1;
@@ -85,7 +86,7 @@ void __init pcibios_update_irq(struct pci_dev *dev, int irq)
         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
 }
 
-static int __init pcibios_init(void)
+static int __init pci_visws_init(void)
 {
         /* The VISWS supports configuration access type 1 only */
         pci_probe = (pci_probe | PCI_PROBE_CONF1) &
@@ -105,4 +106,17 @@ static int __init pcibios_init(void)
         return 0;
 }
 
-subsys_initcall(pcibios_init);
+static __init int pci_subsys_init(void)
+{
+        if (!is_visws_box())
+                return -1;
+
+        pcibios_enable_irq = &pci_visws_enable_irq;
+        pcibios_disable_irq = &pci_visws_disable_irq;
+
+        pci_visws_init();
+        pcibios_init();
+
+        return 0;
+}
+subsys_initcall(pci_subsys_init);
diff --git a/arch/x86/power/hibernate_64.c b/arch/x86/power/hibernate_64.c
index b542355e0e34..6dd000dd7933 100644
--- a/arch/x86/power/hibernate_64.c
+++ b/arch/x86/power/hibernate_64.c
@@ -83,7 +83,7 @@ static int set_up_temporary_mappings(void)
 
         /* Set up the direct mapping from scratch */
         start = (unsigned long)pfn_to_kaddr(0);
-        end = (unsigned long)pfn_to_kaddr(end_pfn);
+        end = (unsigned long)pfn_to_kaddr(max_pfn);
 
         for (; start < end; start = next) {
                 pud_t *pud = (pud_t *)get_safe_page(GFP_ATOMIC);
diff --git a/arch/x86/vdso/vclock_gettime.c b/arch/x86/vdso/vclock_gettime.c
index efa2ba7c6005..1ef0f90813d6 100644
--- a/arch/x86/vdso/vclock_gettime.c
+++ b/arch/x86/vdso/vclock_gettime.c
@@ -23,7 +23,7 @@
 
 #define gtod vdso_vsyscall_gtod_data
 
-static long vdso_fallback_gettime(long clock, struct timespec *ts)
+notrace static long vdso_fallback_gettime(long clock, struct timespec *ts)
 {
         long ret;
         asm("syscall" : "=a" (ret) :
@@ -31,7 +31,7 @@ static long vdso_fallback_gettime(long clock, struct timespec *ts)
         return ret;
 }
 
-static inline long vgetns(void)
+notrace static inline long vgetns(void)
 {
         long v;
         cycles_t (*vread)(void);
@@ -40,7 +40,7 @@ static inline long vgetns(void)
         return (v * gtod->clock.mult) >> gtod->clock.shift;
 }
 
-static noinline int do_realtime(struct timespec *ts)
+notrace static noinline int do_realtime(struct timespec *ts)
 {
         unsigned long seq, ns;
         do {
@@ -54,7 +54,8 @@ static noinline int do_realtime(struct timespec *ts)
 }
 
 /* Copy of the version in kernel/time.c which we cannot directly access */
-static void vset_normalized_timespec(struct timespec *ts, long sec, long nsec)
+notrace static void
+vset_normalized_timespec(struct timespec *ts, long sec, long nsec)
 {
         while (nsec >= NSEC_PER_SEC) {
                 nsec -= NSEC_PER_SEC;
@@ -68,7 +69,7 @@ static void vset_normalized_timespec(struct timespec *ts, long sec, long nsec)
         ts->tv_nsec = nsec;
 }
 
-static noinline int do_monotonic(struct timespec *ts)
+notrace static noinline int do_monotonic(struct timespec *ts)
 {
         unsigned long seq, ns, secs;
         do {
@@ -82,7 +83,7 @@ static noinline int do_monotonic(struct timespec *ts)
         return 0;
 }
 
-int __vdso_clock_gettime(clockid_t clock, struct timespec *ts)
+notrace int __vdso_clock_gettime(clockid_t clock, struct timespec *ts)
 {
         if (likely(gtod->sysctl_enabled && gtod->clock.vread))
                 switch (clock) {
@@ -96,7 +97,7 @@ int __vdso_clock_gettime(clockid_t clock, struct timespec *ts)
 int clock_gettime(clockid_t, struct timespec *)
         __attribute__((weak, alias("__vdso_clock_gettime")));
 
-int __vdso_gettimeofday(struct timeval *tv, struct timezone *tz)
+notrace int __vdso_gettimeofday(struct timeval *tv, struct timezone *tz)
 {
         long ret;
         if (likely(gtod->sysctl_enabled && gtod->clock.vread)) {
diff --git a/arch/x86/vdso/vdso32-setup.c b/arch/x86/vdso/vdso32-setup.c
index cf058fecfcee..0bce5429a515 100644
--- a/arch/x86/vdso/vdso32-setup.c
+++ b/arch/x86/vdso/vdso32-setup.c
@@ -203,20 +203,11 @@ static struct page *vdso32_pages[1];
 
 #ifdef CONFIG_X86_64
 
-static int use_sysenter __read_mostly = -1;
-
-#define vdso32_sysenter()       (use_sysenter > 0)
+#define vdso32_sysenter()       (boot_cpu_has(X86_FEATURE_SYSENTER32))
 
 /* May not be __init: called during resume */
 void syscall32_cpu_init(void)
 {
-        if (use_sysenter < 0) {
-                if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
-                        use_sysenter = 1;
-                if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR)
-                        use_sysenter = 1;
-        }
-
         /* Load these always in case some future AMD CPU supports
            SYSENTER from compat mode too. */
         checking_wrmsrl(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS);
diff --git a/arch/x86/vdso/vgetcpu.c b/arch/x86/vdso/vgetcpu.c
index c8097f17f8a9..9fbc6b20026b 100644
--- a/arch/x86/vdso/vgetcpu.c
+++ b/arch/x86/vdso/vgetcpu.c
@@ -13,7 +13,8 @@
 #include <asm/vgtod.h>
 #include "vextern.h"
 
-long __vdso_getcpu(unsigned *cpu, unsigned *node, struct getcpu_cache *unused)
+notrace long
+__vdso_getcpu(unsigned *cpu, unsigned *node, struct getcpu_cache *unused)
 {
         unsigned int p;
 
diff --git a/arch/x86/vdso/vma.c b/arch/x86/vdso/vma.c
index 3fdd51497a83..19a6cfaf5db9 100644
--- a/arch/x86/vdso/vma.c
+++ b/arch/x86/vdso/vma.c
@@ -16,7 +16,7 @@
 #include "vextern.h"            /* Just for VMAGIC.  */
 #undef VEXTERN
 
-int vdso_enabled = 1;
+unsigned int __read_mostly vdso_enabled = 1;
 
 extern char vdso_start[], vdso_end[];
 extern unsigned short vdso_sync_cpuid;
diff --git a/arch/x86/xen/Kconfig b/arch/x86/xen/Kconfig
index 6c388e593bc8..c2cc99580871 100644
--- a/arch/x86/xen/Kconfig
+++ b/arch/x86/xen/Kconfig
@@ -12,3 +12,13 @@ config XEN
           This is the Linux Xen port.  Enabling this will allow the
           kernel to boot in a paravirtualized environment under the
           Xen hypervisor.
+
+config XEN_MAX_DOMAIN_MEMORY
+       int "Maximum allowed size of a domain in gigabytes"
+       default 8
+       depends on XEN
+       help
+         The pseudo-physical to machine address array is sized
+         according to the maximum possible memory size of a Xen
+         domain.  This array uses 1 page per gigabyte, so there's no
+         need to be too stingy here.
\ No newline at end of file
diff --git a/arch/x86/xen/Makefile b/arch/x86/xen/Makefile
index 3d8df981d5fd..2ba2d1649131 100644
--- a/arch/x86/xen/Makefile
+++ b/arch/x86/xen/Makefile
@@ -1,4 +1,4 @@
 obj-y           := enlighten.o setup.o multicalls.o mmu.o \
-                        time.o manage.o xen-asm.o grant-table.o
+                        time.o xen-asm.o grant-table.o suspend.o
 
 obj-$(CONFIG_SMP)       += smp.o
diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c
index f09c1c69c37a..dcd4e51f2f16 100644
--- a/arch/x86/xen/enlighten.c
+++ b/arch/x86/xen/enlighten.c
@@ -45,6 +45,7 @@
 #include <asm/pgtable.h>
 #include <asm/tlbflush.h>
 #include <asm/reboot.h>
+#include <asm/pgalloc.h>
 
 #include "xen-ops.h"
 #include "mmu.h"
@@ -75,13 +76,13 @@ DEFINE_PER_CPU(unsigned long, xen_current_cr3);	 /* actual vcpu cr3 */
 struct start_info *xen_start_info;
 EXPORT_SYMBOL_GPL(xen_start_info);
 
-static /* __initdata */ struct shared_info dummy_shared_info;
+struct shared_info xen_dummy_shared_info;
 
 /*
  * Point at some empty memory to start with. We map the real shared_info
  * page as soon as fixmap is up and running.
  */
-struct shared_info *HYPERVISOR_shared_info = (void *)&dummy_shared_info;
+struct shared_info *HYPERVISOR_shared_info = (void *)&xen_dummy_shared_info;
 
 /*
  * Flag to determine whether vcpu info placement is available on all
@@ -98,13 +99,13 @@ struct shared_info *HYPERVISOR_shared_info = (void *)&dummy_shared_info;
  */
 static int have_vcpu_info_placement = 1;
 
-static void __init xen_vcpu_setup(int cpu)
+static void xen_vcpu_setup(int cpu)
 {
         struct vcpu_register_vcpu_info info;
         int err;
         struct vcpu_info *vcpup;
 
-        BUG_ON(HYPERVISOR_shared_info == &dummy_shared_info);
+        BUG_ON(HYPERVISOR_shared_info == &xen_dummy_shared_info);
         per_cpu(xen_vcpu, cpu) = &HYPERVISOR_shared_info->vcpu_info[cpu];
 
         if (!have_vcpu_info_placement)
@@ -136,11 +137,41 @@ static void __init xen_vcpu_setup(int cpu)
         }
 }
 
+/*
+ * On restore, set the vcpu placement up again.
+ * If it fails, then we're in a bad state, since
+ * we can't back out from using it...
+ */
+void xen_vcpu_restore(void)
+{
+        if (have_vcpu_info_placement) {
+                int cpu;
+
+                for_each_online_cpu(cpu) {
+                        bool other_cpu = (cpu != smp_processor_id());
+
+                        if (other_cpu &&
+                            HYPERVISOR_vcpu_op(VCPUOP_down, cpu, NULL))
+                                BUG();
+
+                        xen_vcpu_setup(cpu);
+
+                        if (other_cpu &&
+                            HYPERVISOR_vcpu_op(VCPUOP_up, cpu, NULL))
+                                BUG();
+                }
+
+                BUG_ON(!have_vcpu_info_placement);
+        }
+}
+
 static void __init xen_banner(void)
 {
         printk(KERN_INFO "Booting paravirtualized kernel on %s\n",
                pv_info.name);
-        printk(KERN_INFO "Hypervisor signature: %s\n", xen_start_info->magic);
+        printk(KERN_INFO "Hypervisor signature: %s%s\n",
+               xen_start_info->magic,
+               xen_feature(XENFEAT_mmu_pt_update_preserve_ad) ? " (preserve-AD)" : "");
 }
 
 static void xen_cpuid(unsigned int *ax, unsigned int *bx,
@@ -235,13 +266,13 @@ static void xen_irq_enable(void)
 {
         struct vcpu_info *vcpu;
 
-        /* There's a one instruction preempt window here.  We need to
-           make sure we're don't switch CPUs between getting the vcpu
-           pointer and updating the mask. */
-        preempt_disable();
+        /* We don't need to worry about being preempted here, since
+           either a) interrupts are disabled, so no preemption, or b)
+           the caller is confused and is trying to re-enable interrupts
+           on an indeterminate processor. */
+
         vcpu = x86_read_percpu(xen_vcpu);
         vcpu->evtchn_upcall_mask = 0;
-        preempt_enable_no_resched();
 
         /* Doesn't matter if we get preempted here, because any
            pending event will get dealt with anyway. */
@@ -254,7 +285,7 @@ static void xen_irq_enable(void)
 static void xen_safe_halt(void)
 {
         /* Blocking includes an implicit local_irq_enable(). */
-        if (HYPERVISOR_sched_op(SCHEDOP_block, 0) != 0)
+        if (HYPERVISOR_sched_op(SCHEDOP_block, NULL) != 0)
                 BUG();
 }
 
@@ -607,6 +638,30 @@ static void xen_flush_tlb_others(const cpumask_t *cpus, struct mm_struct *mm,
         xen_mc_issue(PARAVIRT_LAZY_MMU);
 }
 
+static void xen_clts(void)
+{
+        struct multicall_space mcs;
+
+        mcs = xen_mc_entry(0);
+
+        MULTI_fpu_taskswitch(mcs.mc, 0);
+
+        xen_mc_issue(PARAVIRT_LAZY_CPU);
+}
+
+static void xen_write_cr0(unsigned long cr0)
+{
+        struct multicall_space mcs;
+
+        /* Only pay attention to cr0.TS; everything else is
+           ignored. */
+        mcs = xen_mc_entry(0);
+
+        MULTI_fpu_taskswitch(mcs.mc, (cr0 & X86_CR0_TS) != 0);
+
+        xen_mc_issue(PARAVIRT_LAZY_CPU);
+}
+
 static void xen_write_cr2(unsigned long cr2)
 {
         x86_read_percpu(xen_vcpu)->arch.cr2 = cr2;
@@ -624,8 +679,10 @@ static unsigned long xen_read_cr2_direct(void)
 
 static void xen_write_cr4(unsigned long cr4)
 {
-        /* Just ignore cr4 changes; Xen doesn't allow us to do
-           anything anyway. */
+        cr4 &= ~X86_CR4_PGE;
+        cr4 &= ~X86_CR4_PSE;
+
+        native_write_cr4(cr4);
 }
 
 static unsigned long xen_read_cr3(void)
@@ -831,7 +888,7 @@ static __init void xen_pagetable_setup_start(pgd_t *base)
                           PFN_DOWN(__pa(xen_start_info->pt_base)));
 }
 
-static __init void setup_shared_info(void)
+void xen_setup_shared_info(void)
 {
         if (!xen_feature(XENFEAT_auto_translated_physmap)) {
                 unsigned long addr = fix_to_virt(FIX_PARAVIRT_BOOTMAP);
@@ -854,6 +911,8 @@ static __init void setup_shared_info(void)
         /* In UP this is as good a place as any to set up shared info */
         xen_setup_vcpu_info_placement();
 #endif
+
+        xen_setup_mfn_list_list();
 }
 
 static __init void xen_pagetable_setup_done(pgd_t *base)
@@ -866,15 +925,23 @@ static __init void xen_pagetable_setup_done(pgd_t *base)
         pv_mmu_ops.release_pmd = xen_release_pmd;
         pv_mmu_ops.set_pte = xen_set_pte;
 
-        setup_shared_info();
+        xen_setup_shared_info();
 
         /* Actually pin the pagetable down, but we can't set PG_pinned
            yet because the page structures don't exist yet. */
         pin_pagetable_pfn(MMUEXT_PIN_L3_TABLE, PFN_DOWN(__pa(base)));
 }
 
+static __init void xen_post_allocator_init(void)
+{
+        pv_mmu_ops.set_pmd = xen_set_pmd;
+        pv_mmu_ops.set_pud = xen_set_pud;
+
+        xen_mark_init_mm_pinned();
+}
+
 /* This is called once we have the cpu_possible_map */
-void __init xen_setup_vcpu_info_placement(void)
+void xen_setup_vcpu_info_placement(void)
 {
         int cpu;
 
@@ -947,6 +1014,33 @@ static unsigned xen_patch(u8 type, u16 clobbers, void *insnbuf,
         return ret;
 }
 
+static void xen_set_fixmap(unsigned idx, unsigned long phys, pgprot_t prot)
+{
+        pte_t pte;
+
+        phys >>= PAGE_SHIFT;
+
+        switch (idx) {
+        case FIX_BTMAP_END ... FIX_BTMAP_BEGIN:
+#ifdef CONFIG_X86_F00F_BUG
+        case FIX_F00F_IDT:
+#endif
+        case FIX_WP_TEST:
+        case FIX_VDSO:
+#ifdef CONFIG_X86_LOCAL_APIC
+        case FIX_APIC_BASE:     /* maps dummy local APIC */
+#endif
+                pte = pfn_pte(phys, prot);
+                break;
+
+        default:
+                pte = mfn_pte(phys, prot);
+                break;
+        }
+
+        __native_set_fixmap(idx, pte);
+}
+
 static const struct pv_info xen_info __initdata = {
         .paravirt_enabled = 1,
         .shared_kernel_pmd = 0,
@@ -960,7 +1054,7 @@ static const struct pv_init_ops xen_init_ops __initdata = {
         .banner = xen_banner,
         .memory_setup = xen_memory_setup,
         .arch_setup = xen_arch_setup,
-        .post_allocator_init = xen_mark_init_mm_pinned,
+        .post_allocator_init = xen_post_allocator_init,
 };
 
 static const struct pv_time_ops xen_time_ops __initdata = {
@@ -968,7 +1062,7 @@ static const struct pv_time_ops xen_time_ops __initdata = {
 
         .set_wallclock = xen_set_wallclock,
         .get_wallclock = xen_get_wallclock,
-        .get_cpu_khz = xen_cpu_khz,
+        .get_tsc_khz = xen_tsc_khz,
         .sched_clock = xen_sched_clock,
 };
 
@@ -978,10 +1072,10 @@ static const struct pv_cpu_ops xen_cpu_ops __initdata = {
         .set_debugreg = xen_set_debugreg,
         .get_debugreg = xen_get_debugreg,
 
-        .clts = native_clts,
+        .clts = xen_clts,
 
         .read_cr0 = native_read_cr0,
-        .write_cr0 = native_write_cr0,
+        .write_cr0 = xen_write_cr0,
 
         .read_cr4 = native_read_cr4,
         .read_cr4_safe = native_read_cr4_safe,
@@ -995,7 +1089,7 @@ static const struct pv_cpu_ops xen_cpu_ops __initdata = {
         .read_pmc = native_read_pmc,
 
         .iret = xen_iret,
-        .irq_enable_syscall_ret = xen_sysexit,
+        .irq_enable_sysexit = xen_sysexit,
 
         .load_tr_desc = paravirt_nop,
         .set_ldt = xen_set_ldt,
@@ -1029,6 +1123,9 @@ static const struct pv_irq_ops xen_irq_ops __initdata = {
         .irq_enable = xen_irq_enable,
         .safe_halt = xen_safe_halt,
         .halt = xen_halt,
+#ifdef CONFIG_X86_64
+        .adjust_exception_frame = paravirt_nop,
+#endif
 };
 
 static const struct pv_apic_ops xen_apic_ops __initdata = {
@@ -1060,6 +1157,9 @@ static const struct pv_mmu_ops xen_mmu_ops __initdata = {
         .pte_update = paravirt_nop,
         .pte_update_defer = paravirt_nop,
 
+        .pgd_alloc = __paravirt_pgd_alloc,
+        .pgd_free = paravirt_nop,
+
         .alloc_pte = xen_alloc_pte_init,
         .release_pte = xen_release_pte_init,
         .alloc_pmd = xen_alloc_pte_init,
@@ -1072,9 +1172,13 @@ static const struct pv_mmu_ops xen_mmu_ops __initdata = {
 
         .set_pte = NULL,        /* see xen_pagetable_setup_* */
         .set_pte_at = xen_set_pte_at,
-        .set_pmd = xen_set_pmd,
+        .set_pmd = xen_set_pmd_hyper,
+
+        .ptep_modify_prot_start = __ptep_modify_prot_start,
+        .ptep_modify_prot_commit = __ptep_modify_prot_commit,
 
         .pte_val = xen_pte_val,
+        .pte_flags = native_pte_val,
         .pgd_val = xen_pgd_val,
 
         .make_pte = xen_make_pte,
@@ -1082,7 +1186,7 @@ static const struct pv_mmu_ops xen_mmu_ops __initdata = {
 
         .set_pte_atomic = xen_set_pte_atomic,
         .set_pte_present = xen_set_pte_at,
-        .set_pud = xen_set_pud,
+        .set_pud = xen_set_pud_hyper,
         .pte_clear = xen_pte_clear,
         .pmd_clear = xen_pmd_clear,
 
@@ -1097,6 +1201,8 @@ static const struct pv_mmu_ops xen_mmu_ops __initdata = {
                 .enter = paravirt_enter_lazy_mmu,
                 .leave = xen_leave_lazy,
         },
+
+        .set_fixmap = xen_set_fixmap,
 };
 
 #ifdef CONFIG_SMP
@@ -1114,11 +1220,13 @@ static const struct smp_ops xen_smp_ops __initdata = {
 
 static void xen_reboot(int reason)
 {
+        struct sched_shutdown r = { .reason = reason };
+
 #ifdef CONFIG_SMP
         smp_send_stop();
 #endif
 
-        if (HYPERVISOR_sched_op(SCHEDOP_shutdown, reason))
+        if (HYPERVISOR_sched_op(SCHEDOP_shutdown, &r))
                 BUG();
 }
 
@@ -1173,6 +1281,8 @@ asmlinkage void __init xen_start_kernel(void)
 
         BUG_ON(memcmp(xen_start_info->magic, "xen-3", 5) != 0);
 
+        xen_setup_features();
+
         /* Install Xen paravirt ops */
         pv_info = xen_info;
         pv_init_ops = xen_init_ops;
@@ -1182,21 +1292,26 @@ asmlinkage void __init xen_start_kernel(void)
         pv_apic_ops = xen_apic_ops;
         pv_mmu_ops = xen_mmu_ops;
 
+        if (xen_feature(XENFEAT_mmu_pt_update_preserve_ad)) {
+                pv_mmu_ops.ptep_modify_prot_start = xen_ptep_modify_prot_start;
+                pv_mmu_ops.ptep_modify_prot_commit = xen_ptep_modify_prot_commit;
+        }
+
         machine_ops = xen_machine_ops;
 
 #ifdef CONFIG_SMP
         smp_ops = xen_smp_ops;
 #endif
 
-        xen_setup_features();
-
         /* Get mfn list */
         if (!xen_feature(XENFEAT_auto_translated_physmap))
-                phys_to_machine_mapping = (unsigned long *)xen_start_info->mfn_list;
+                xen_build_dynamic_phys_to_machine();
 
         pgd = (pgd_t *)xen_start_info->pt_base;
 
+        init_pg_tables_start = __pa(pgd);
         init_pg_tables_end = __pa(pgd) + xen_start_info->nr_pt_frames*PAGE_SIZE;
+        max_pfn_mapped = (init_pg_tables_end + 512*1024) >> PAGE_SHIFT;
 
         init_mm.pgd = pgd; /* use the Xen pagetables to start */
 
@@ -1232,9 +1347,12 @@ asmlinkage void __init xen_start_kernel(void)
                 ? __pa(xen_start_info->mod_start) : 0;
         boot_params.hdr.ramdisk_size = xen_start_info->mod_len;
 
-        if (!is_initial_xendomain())
+        if (!is_initial_xendomain()) {
+                add_preferred_console("xenboot", 0, NULL);
+                add_preferred_console("tty", 0, NULL);
                 add_preferred_console("hvc", 0, NULL);
+        }
 
         /* Start the world */
-        start_kernel();
+        i386_start_kernel();
 }
diff --git a/arch/x86/xen/manage.c b/arch/x86/xen/manage.c
deleted file mode 100644
index aa7af9e6abc0..000000000000
--- a/arch/x86/xen/manage.c
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
- * Handle extern requests for shutdown, reboot and sysrq
- */
-#include <linux/kernel.h>
-#include <linux/err.h>
-#include <linux/reboot.h>
-#include <linux/sysrq.h>
-
-#include <xen/xenbus.h>
-
-#define SHUTDOWN_INVALID  -1
-#define SHUTDOWN_POWEROFF  0
-#define SHUTDOWN_SUSPEND   2
-/* Code 3 is SHUTDOWN_CRASH, which we don't use because the domain can only
- * report a crash, not be instructed to crash!
- * HALT is the same as POWEROFF, as far as we're concerned.  The tools use
- * the distinction when we return the reason code to them.
- */
-#define SHUTDOWN_HALT      4
-
-/* Ignore multiple shutdown requests. */
-static int shutting_down = SHUTDOWN_INVALID;
-
-static void shutdown_handler(struct xenbus_watch *watch,
-                             const char **vec, unsigned int len)
-{
-        char *str;
-        struct xenbus_transaction xbt;
-        int err;
-
-        if (shutting_down != SHUTDOWN_INVALID)
-                return;
-
- again:
-        err = xenbus_transaction_start(&xbt);
-        if (err)
-                return;
-
-        str = (char *)xenbus_read(xbt, "control", "shutdown", NULL);
-        /* Ignore read errors and empty reads. */
-        if (XENBUS_IS_ERR_READ(str)) {
-                xenbus_transaction_end(xbt, 1);
-                return;
-        }
-
-        xenbus_write(xbt, "control", "shutdown", "");
-
-        err = xenbus_transaction_end(xbt, 0);
-        if (err == -EAGAIN) {
-                kfree(str);
-                goto again;
-        }
-
-        if (strcmp(str, "poweroff") == 0 ||
-            strcmp(str, "halt") == 0)
-                orderly_poweroff(false);
-        else if (strcmp(str, "reboot") == 0)
-                ctrl_alt_del();
-        else {
-                printk(KERN_INFO "Ignoring shutdown request: %s\n", str);
-                shutting_down = SHUTDOWN_INVALID;
-        }
-
-        kfree(str);
-}
-
-static void sysrq_handler(struct xenbus_watch *watch, const char **vec,
-                          unsigned int len)
-{
-        char sysrq_key = '\0';
-        struct xenbus_transaction xbt;
-        int err;
-
- again:
-        err = xenbus_transaction_start(&xbt);
-        if (err)
-                return;
-        if (!xenbus_scanf(xbt, "control", "sysrq", "%c", &sysrq_key)) {
-                printk(KERN_ERR "Unable to read sysrq code in "
-                       "control/sysrq\n");
-                xenbus_transaction_end(xbt, 1);
-                return;
-        }
-
-        if (sysrq_key != '\0')
-                xenbus_printf(xbt, "control", "sysrq", "%c", '\0');
-
-        err = xenbus_transaction_end(xbt, 0);
-        if (err == -EAGAIN)
-                goto again;
-
-        if (sysrq_key != '\0')
-                handle_sysrq(sysrq_key, NULL);
-}
-
-static struct xenbus_watch shutdown_watch = {
-        .node = "control/shutdown",
-        .callback = shutdown_handler
-};
-
-static struct xenbus_watch sysrq_watch = {
-        .node = "control/sysrq",
-        .callback = sysrq_handler
-};
-
-static int setup_shutdown_watcher(void)
-{
-        int err;
-
-        err = register_xenbus_watch(&shutdown_watch);
-        if (err) {
-                printk(KERN_ERR "Failed to set shutdown watcher\n");
-                return err;
-        }
-
-        err = register_xenbus_watch(&sysrq_watch);
-        if (err) {
-                printk(KERN_ERR "Failed to set sysrq watcher\n");
-                return err;
-        }
-
-        return 0;
-}
-
-static int shutdown_event(struct notifier_block *notifier,
-                          unsigned long event,
-                          void *data)
-{
-        setup_shutdown_watcher();
-        return NOTIFY_DONE;
-}
-
-static int __init setup_shutdown_event(void)
-{
-        static struct notifier_block xenstore_notifier = {
-                .notifier_call = shutdown_event
-        };
-        register_xenstore_notifier(&xenstore_notifier);
-
-        return 0;
-}
-
-subsys_initcall(setup_shutdown_event);
diff --git a/arch/x86/xen/mmu.c b/arch/x86/xen/mmu.c
index 4e527e7893a8..42b3b9ed641d 100644
--- a/arch/x86/xen/mmu.c
+++ b/arch/x86/xen/mmu.c
@@ -56,6 +56,131 @@
 #include "multicalls.h"
 #include "mmu.h"
 
+#define P2M_ENTRIES_PER_PAGE    (PAGE_SIZE / sizeof(unsigned long))
+#define TOP_ENTRIES             (MAX_DOMAIN_PAGES / P2M_ENTRIES_PER_PAGE)
+
+/* Placeholder for holes in the address space */
+static unsigned long p2m_missing[P2M_ENTRIES_PER_PAGE]
+        __attribute__((section(".data.page_aligned"))) =
+                { [ 0 ... P2M_ENTRIES_PER_PAGE-1 ] = ~0UL };
+
+ /* Array of pointers to pages containing p2m entries */
+static unsigned long *p2m_top[TOP_ENTRIES]
+        __attribute__((section(".data.page_aligned"))) =
+                { [ 0 ... TOP_ENTRIES - 1] = &p2m_missing[0] };
+
+/* Arrays of p2m arrays expressed in mfns used for save/restore */
+static unsigned long p2m_top_mfn[TOP_ENTRIES]
+        __attribute__((section(".bss.page_aligned")));
+
+static unsigned long p2m_top_mfn_list[
+                        PAGE_ALIGN(TOP_ENTRIES / P2M_ENTRIES_PER_PAGE)]
+        __attribute__((section(".bss.page_aligned")));
+
+static inline unsigned p2m_top_index(unsigned long pfn)
+{
+        BUG_ON(pfn >= MAX_DOMAIN_PAGES);
+        return pfn / P2M_ENTRIES_PER_PAGE;
+}
+
+static inline unsigned p2m_index(unsigned long pfn)
+{
+        return pfn % P2M_ENTRIES_PER_PAGE;
+}
+
+/* Build the parallel p2m_top_mfn structures */
+void xen_setup_mfn_list_list(void)
+{
+        unsigned pfn, idx;
+
+        for(pfn = 0; pfn < MAX_DOMAIN_PAGES; pfn += P2M_ENTRIES_PER_PAGE) {
+                unsigned topidx = p2m_top_index(pfn);
+
+                p2m_top_mfn[topidx] = virt_to_mfn(p2m_top[topidx]);
+        }
+
+        for(idx = 0; idx < ARRAY_SIZE(p2m_top_mfn_list); idx++) {
+                unsigned topidx = idx * P2M_ENTRIES_PER_PAGE;
+                p2m_top_mfn_list[idx] = virt_to_mfn(&p2m_top_mfn[topidx]);
+        }
+
+        BUG_ON(HYPERVISOR_shared_info == &xen_dummy_shared_info);
+
+        HYPERVISOR_shared_info->arch.pfn_to_mfn_frame_list_list =
+                virt_to_mfn(p2m_top_mfn_list);
+        HYPERVISOR_shared_info->arch.max_pfn = xen_start_info->nr_pages;
+}
+
+/* Set up p2m_top to point to the domain-builder provided p2m pages */
+void __init xen_build_dynamic_phys_to_machine(void)
+{
+        unsigned long *mfn_list = (unsigned long *)xen_start_info->mfn_list;
+        unsigned long max_pfn = min(MAX_DOMAIN_PAGES, xen_start_info->nr_pages);
+        unsigned pfn;
+
+        for(pfn = 0; pfn < max_pfn; pfn += P2M_ENTRIES_PER_PAGE) {
+                unsigned topidx = p2m_top_index(pfn);
+
+                p2m_top[topidx] = &mfn_list[pfn];
+        }
+}
+
+unsigned long get_phys_to_machine(unsigned long pfn)
+{
+        unsigned topidx, idx;
+
+        if (unlikely(pfn >= MAX_DOMAIN_PAGES))
+                return INVALID_P2M_ENTRY;
+
+        topidx = p2m_top_index(pfn);
+        idx = p2m_index(pfn);
+        return p2m_top[topidx][idx];
+}
+EXPORT_SYMBOL_GPL(get_phys_to_machine);
+
+static void alloc_p2m(unsigned long **pp, unsigned long *mfnp)
+{
+        unsigned long *p;
+        unsigned i;
+
+        p = (void *)__get_free_page(GFP_KERNEL | __GFP_NOFAIL);
+        BUG_ON(p == NULL);
+
+        for(i = 0; i < P2M_ENTRIES_PER_PAGE; i++)
+                p[i] = INVALID_P2M_ENTRY;
+
+        if (cmpxchg(pp, p2m_missing, p) != p2m_missing)
+                free_page((unsigned long)p);
+        else
+                *mfnp = virt_to_mfn(p);
+}
+
+void set_phys_to_machine(unsigned long pfn, unsigned long mfn)
+{
+        unsigned topidx, idx;
+
+        if (unlikely(xen_feature(XENFEAT_auto_translated_physmap))) {
+                BUG_ON(pfn != mfn && mfn != INVALID_P2M_ENTRY);
+                return;
+        }
+
+        if (unlikely(pfn >= MAX_DOMAIN_PAGES)) {
+                BUG_ON(mfn != INVALID_P2M_ENTRY);
+                return;
+        }
+
+        topidx = p2m_top_index(pfn);
+        if (p2m_top[topidx] == p2m_missing) {
+                /* no need to allocate a page to store an invalid entry */
+                if (mfn == INVALID_P2M_ENTRY)
+                        return;
+                alloc_p2m(&p2m_top[topidx], &p2m_top_mfn[topidx]);
+        }
+
+        idx = p2m_index(pfn);
+        p2m_top[topidx][idx] = mfn;
+}
+
 xmaddr_t arbitrary_virt_to_machine(unsigned long address)
 {
         unsigned int level;
@@ -98,24 +223,60 @@ void make_lowmem_page_readwrite(void *vaddr)
 }
 
 
-void xen_set_pmd(pmd_t *ptr, pmd_t val)
+static bool page_pinned(void *ptr)
+{
+        struct page *page = virt_to_page(ptr);
+
+        return PagePinned(page);
+}
+
+static void extend_mmu_update(const struct mmu_update *update)
 {
         struct multicall_space mcs;
         struct mmu_update *u;
 
-        preempt_disable();
+        mcs = xen_mc_extend_args(__HYPERVISOR_mmu_update, sizeof(*u));
+
+        if (mcs.mc != NULL)
+                mcs.mc->args[1]++;
+        else {
+                mcs = __xen_mc_entry(sizeof(*u));
+                MULTI_mmu_update(mcs.mc, mcs.args, 1, NULL, DOMID_SELF);
+        }
 
-        mcs = xen_mc_entry(sizeof(*u));
         u = mcs.args;
-        u->ptr = virt_to_machine(ptr).maddr;
-        u->val = pmd_val_ma(val);
-        MULTI_mmu_update(mcs.mc, u, 1, NULL, DOMID_SELF);
+        *u = *update;
+}
+
+void xen_set_pmd_hyper(pmd_t *ptr, pmd_t val)
+{
+        struct mmu_update u;
+
+        preempt_disable();
+
+        xen_mc_batch();
+
+        u.ptr = virt_to_machine(ptr).maddr;
+        u.val = pmd_val_ma(val);
+        extend_mmu_update(&u);
 
         xen_mc_issue(PARAVIRT_LAZY_MMU);
 
         preempt_enable();
 }
 
+void xen_set_pmd(pmd_t *ptr, pmd_t val)
+{
+        /* If page is not pinned, we can just update the entry
+           directly */
+        if (!page_pinned(ptr)) {
+                *ptr = val;
+                return;
+        }
+
+        xen_set_pmd_hyper(ptr, val);
+}
+
 /*
  * Associate a virtual page frame with a given physical page frame
  * and protection flags for that frame.
@@ -179,6 +340,26 @@ out:
                 preempt_enable();
 }
 
+pte_t xen_ptep_modify_prot_start(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
+{
+        /* Just return the pte as-is.  We preserve the bits on commit */
+        return *ptep;
+}
+
+void xen_ptep_modify_prot_commit(struct mm_struct *mm, unsigned long addr,
+                                 pte_t *ptep, pte_t pte)
+{
+        struct mmu_update u;
+
+        xen_mc_batch();
+
+        u.ptr = virt_to_machine(ptep).maddr | MMU_PT_UPDATE_PRESERVE_AD;
+        u.val = pte_val_ma(pte);
+        extend_mmu_update(&u);
+
+        xen_mc_issue(PARAVIRT_LAZY_MMU);
+}
+
 /* Assume pteval_t is equivalent to all the other *val_t types. */
 static pteval_t pte_mfn_to_pfn(pteval_t val)
 {
@@ -229,24 +410,35 @@ pmdval_t xen_pmd_val(pmd_t pmd)
         return pte_mfn_to_pfn(pmd.pmd);
 }
 
-void xen_set_pud(pud_t *ptr, pud_t val)
+void xen_set_pud_hyper(pud_t *ptr, pud_t val)
 {
-        struct multicall_space mcs;
-        struct mmu_update *u;
+        struct mmu_update u;
 
         preempt_disable();
 
-        mcs = xen_mc_entry(sizeof(*u));
-        u = mcs.args;
-        u->ptr = virt_to_machine(ptr).maddr;
-        u->val = pud_val_ma(val);
-        MULTI_mmu_update(mcs.mc, u, 1, NULL, DOMID_SELF);
+        xen_mc_batch();
+
+        u.ptr = virt_to_machine(ptr).maddr;
+        u.val = pud_val_ma(val);
+        extend_mmu_update(&u);
 
         xen_mc_issue(PARAVIRT_LAZY_MMU);
 
         preempt_enable();
 }
 
+void xen_set_pud(pud_t *ptr, pud_t val)
+{
+        /* If page is not pinned, we can just update the entry
+           directly */
+        if (!page_pinned(ptr)) {
+                *ptr = val;
+                return;
+        }
+
+        xen_set_pud_hyper(ptr, val);
+}
+
 void xen_set_pte(pte_t *ptep, pte_t pte)
 {
         ptep->pte_high = pte.pte_high;
@@ -268,7 +460,7 @@ void xen_pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
 
 void xen_pmd_clear(pmd_t *pmdp)
 {
-        xen_set_pmd(pmdp, __pmd(0));
+        set_pmd(pmdp, __pmd(0));
 }
 
 pmd_t xen_make_pmd(pmdval_t pmd)
@@ -441,6 +633,29 @@ void xen_pgd_pin(pgd_t *pgd)
         xen_mc_issue(0);
 }
 
+/*
+ * On save, we need to pin all pagetables to make sure they get their
+ * mfns turned into pfns.  Search the list for any unpinned pgds and pin
+ * them (unpinned pgds are not currently in use, probably because the
+ * process is under construction or destruction).
+ */
+void xen_mm_pin_all(void)
+{
+        unsigned long flags;
+        struct page *page;
+
+        spin_lock_irqsave(&pgd_lock, flags);
+
+        list_for_each_entry(page, &pgd_list, lru) {
+                if (!PagePinned(page)) {
+                        xen_pgd_pin((pgd_t *)page_address(page));
+                        SetPageSavePinned(page);
+                }
+        }
+
+        spin_unlock_irqrestore(&pgd_lock, flags);
+}
+
 /* The init_mm pagetable is really pinned as soon as its created, but
    that's before we have page structures to store the bits.  So do all
    the book-keeping now. */
@@ -498,6 +713,29 @@ static void xen_pgd_unpin(pgd_t *pgd)
         xen_mc_issue(0);
 }
 
+/*
+ * On resume, undo any pinning done at save, so that the rest of the
+ * kernel doesn't see any unexpected pinned pagetables.
+ */
+void xen_mm_unpin_all(void)
+{
+        unsigned long flags;
+        struct page *page;
+
+        spin_lock_irqsave(&pgd_lock, flags);
+
+        list_for_each_entry(page, &pgd_list, lru) {
+                if (PageSavePinned(page)) {
+                        BUG_ON(!PagePinned(page));
+                        printk("unpinning pinned %p\n", page_address(page));
+                        xen_pgd_unpin((pgd_t *)page_address(page));
+                        ClearPageSavePinned(page);
+                }
+        }
+
+        spin_unlock_irqrestore(&pgd_lock, flags);
+}
+
 void xen_activate_mm(struct mm_struct *prev, struct mm_struct *next)
 {
         spin_lock(&next->page_table_lock);
@@ -591,7 +829,7 @@ void xen_exit_mmap(struct mm_struct *mm)
         spin_lock(&mm->page_table_lock);
 
         /* pgd may not be pinned in the error exit path of execve */
-        if (PagePinned(virt_to_page(mm->pgd)))
+        if (page_pinned(mm->pgd))
                 xen_pgd_unpin(mm->pgd);
 
         spin_unlock(&mm->page_table_lock);
diff --git a/arch/x86/xen/mmu.h b/arch/x86/xen/mmu.h
index 5fe961caffd4..297bf9f5b8bc 100644
--- a/arch/x86/xen/mmu.h
+++ b/arch/x86/xen/mmu.h
@@ -25,10 +25,6 @@ enum pt_level {
 
 void set_pte_mfn(unsigned long vaddr, unsigned long pfn, pgprot_t flags);
 
-void xen_set_pte(pte_t *ptep, pte_t pteval);
-void xen_set_pte_at(struct mm_struct *mm, unsigned long addr,
-                    pte_t *ptep, pte_t pteval);
-void xen_set_pmd(pmd_t *pmdp, pmd_t pmdval);
 
 void xen_activate_mm(struct mm_struct *prev, struct mm_struct *next);
 void xen_dup_mmap(struct mm_struct *oldmm, struct mm_struct *mm);
@@ -45,11 +41,19 @@ pte_t xen_make_pte(pteval_t);
 pmd_t xen_make_pmd(pmdval_t);
 pgd_t xen_make_pgd(pgdval_t);
 
+void xen_set_pte(pte_t *ptep, pte_t pteval);
 void xen_set_pte_at(struct mm_struct *mm, unsigned long addr,
                     pte_t *ptep, pte_t pteval);
 void xen_set_pte_atomic(pte_t *ptep, pte_t pte);
+void xen_set_pmd(pmd_t *pmdp, pmd_t pmdval);
 void xen_set_pud(pud_t *ptr, pud_t val);
+void xen_set_pmd_hyper(pmd_t *pmdp, pmd_t pmdval);
+void xen_set_pud_hyper(pud_t *ptr, pud_t val);
 void xen_pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep);
 void xen_pmd_clear(pmd_t *pmdp);
 
+pte_t xen_ptep_modify_prot_start(struct mm_struct *mm, unsigned long addr, pte_t *ptep);
+void  xen_ptep_modify_prot_commit(struct mm_struct *mm, unsigned long addr,
+                                  pte_t *ptep, pte_t pte);
+
 #endif  /* _XEN_MMU_H */
diff --git a/arch/x86/xen/multicalls.c b/arch/x86/xen/multicalls.c
index 5791eb2e3750..3c63c4da7ed1 100644
--- a/arch/x86/xen/multicalls.c
+++ b/arch/x86/xen/multicalls.c
@@ -29,14 +29,14 @@
 #define MC_DEBUG        1
 
 #define MC_BATCH        32
-#define MC_ARGS         (MC_BATCH * 16 / sizeof(u64))
+#define MC_ARGS         (MC_BATCH * 16)
 
 struct mc_buffer {
         struct multicall_entry entries[MC_BATCH];
 #if MC_DEBUG
         struct multicall_entry debug[MC_BATCH];
 #endif
-        u64 args[MC_ARGS];
+        unsigned char args[MC_ARGS];
         struct callback {
                 void (*fn)(void *);
                 void *data;
@@ -107,20 +107,48 @@ struct multicall_space __xen_mc_entry(size_t args)
 {
         struct mc_buffer *b = &__get_cpu_var(mc_buffer);
         struct multicall_space ret;
-        unsigned argspace = (args + sizeof(u64) - 1) / sizeof(u64);
+        unsigned argidx = roundup(b->argidx, sizeof(u64));
 
         BUG_ON(preemptible());
-        BUG_ON(argspace > MC_ARGS);
+        BUG_ON(b->argidx > MC_ARGS);
 
         if (b->mcidx == MC_BATCH ||
-            (b->argidx + argspace) > MC_ARGS)
+            (argidx + args) > MC_ARGS) {
                 xen_mc_flush();
+                argidx = roundup(b->argidx, sizeof(u64));
+        }
 
         ret.mc = &b->entries[b->mcidx];
         b->mcidx++;
+        ret.args = &b->args[argidx];
+        b->argidx = argidx + args;
+
+        BUG_ON(b->argidx > MC_ARGS);
+        return ret;
+}
+
+struct multicall_space xen_mc_extend_args(unsigned long op, size_t size)
+{
+        struct mc_buffer *b = &__get_cpu_var(mc_buffer);
+        struct multicall_space ret = { NULL, NULL };
+
+        BUG_ON(preemptible());
+        BUG_ON(b->argidx > MC_ARGS);
+
+        if (b->mcidx == 0)
+                return ret;
+
+        if (b->entries[b->mcidx - 1].op != op)
+                return ret;
+
+        if ((b->argidx + size) > MC_ARGS)
+                return ret;
+
+        ret.mc = &b->entries[b->mcidx - 1];
         ret.args = &b->args[b->argidx];
-        b->argidx += argspace;
+        b->argidx += size;
 
+        BUG_ON(b->argidx > MC_ARGS);
         return ret;
 }
 
diff --git a/arch/x86/xen/multicalls.h b/arch/x86/xen/multicalls.h
index 8bae996d99a3..858938241616 100644
--- a/arch/x86/xen/multicalls.h
+++ b/arch/x86/xen/multicalls.h
@@ -45,4 +45,16 @@ static inline void xen_mc_issue(unsigned mode)
 /* Set up a callback to be called when the current batch is flushed */
 void xen_mc_callback(void (*fn)(void *), void *data);
 
+/*
+ * Try to extend the arguments of the previous multicall command.  The
+ * previous command's op must match.  If it does, then it attempts to
+ * extend the argument space allocated to the multicall entry by
+ * arg_size bytes.
+ *
+ * The returned multicall_space will return with mc pointing to the
+ * command on success, or NULL on failure, and args pointing to the
+ * newly allocated space.
+ */
+struct multicall_space xen_mc_extend_args(unsigned long op, size_t arg_size);
+
 #endif /* _XEN_MULTICALLS_H */
diff --git a/arch/x86/xen/setup.c b/arch/x86/xen/setup.c
index 82517e4a752a..e0a39595bde3 100644
--- a/arch/x86/xen/setup.c
+++ b/arch/x86/xen/setup.c
@@ -13,9 +13,11 @@
 #include <asm/vdso.h>
 #include <asm/e820.h>
 #include <asm/setup.h>
+#include <asm/acpi.h>
 #include <asm/xen/hypervisor.h>
 #include <asm/xen/hypercall.h>
 
+#include <xen/page.h>
 #include <xen/interface/callback.h>
 #include <xen/interface/physdev.h>
 #include <xen/features.h>
@@ -27,8 +29,6 @@
 extern const char xen_hypervisor_callback[];
 extern const char xen_failsafe_callback[];
 
-unsigned long *phys_to_machine_mapping;
-EXPORT_SYMBOL(phys_to_machine_mapping);
 
 /**
  * machine_specific_memory_setup - Hook for machine specific memory setup.
@@ -38,9 +38,31 @@ char * __init xen_memory_setup(void)
 {
         unsigned long max_pfn = xen_start_info->nr_pages;
 
+        max_pfn = min(MAX_DOMAIN_PAGES, max_pfn);
+
         e820.nr_map = 0;
-        add_memory_region(0, LOWMEMSIZE(), E820_RAM);
-        add_memory_region(HIGH_MEMORY, PFN_PHYS(max_pfn)-HIGH_MEMORY, E820_RAM);
+
+        e820_add_region(0, PFN_PHYS(max_pfn), E820_RAM);
+
+        /*
+         * Even though this is normal, usable memory under Xen, reserve
+         * ISA memory anyway because too many things think they can poke
+         * about in there.
+         */
+        e820_add_region(ISA_START_ADDRESS, ISA_END_ADDRESS - ISA_START_ADDRESS,
+                        E820_RESERVED);
+
+        /*
+         * Reserve Xen bits:
+         *  - mfn_list
+         *  - xen_start_info
+         * See comment above "struct start_info" in <xen/interface/xen.h>
+         */
+        e820_add_region(__pa(xen_start_info->mfn_list),
+                        xen_start_info->pt_base - xen_start_info->mfn_list,
+                        E820_RESERVED);
+
+        sanitize_e820_map(e820.map, ARRAY_SIZE(e820.map), &e820.nr_map);
 
         return "Xen";
 }
diff --git a/arch/x86/xen/smp.c b/arch/x86/xen/smp.c
index 94e69000f982..d2e3c20127d7 100644
--- a/arch/x86/xen/smp.c
+++ b/arch/x86/xen/smp.c
@@ -35,7 +35,7 @@
 #include "xen-ops.h"
 #include "mmu.h"
 
-static cpumask_t xen_cpu_initialized_map;
+cpumask_t xen_cpu_initialized_map;
 static DEFINE_PER_CPU(int, resched_irq) = -1;
 static DEFINE_PER_CPU(int, callfunc_irq) = -1;
 static DEFINE_PER_CPU(int, debug_irq) = -1;
@@ -65,6 +65,12 @@ static struct call_data_struct *call_data;
  */
 static irqreturn_t xen_reschedule_interrupt(int irq, void *dev_id)
 {
+#ifdef CONFIG_X86_32
+        __get_cpu_var(irq_stat).irq_resched_count++;
+#else
+        add_pda(irq_resched_count, 1);
+#endif
+
         return IRQ_HANDLED;
 }
 
diff --git a/arch/x86/xen/suspend.c b/arch/x86/xen/suspend.c
new file mode 100644
index 000000000000..251669a932d4
--- /dev/null
+++ b/arch/x86/xen/suspend.c
@@ -0,0 +1,45 @@
+#include <linux/types.h>
+
+#include <xen/interface/xen.h>
+#include <xen/grant_table.h>
+#include <xen/events.h>
+
+#include <asm/xen/hypercall.h>
+#include <asm/xen/page.h>
+
+#include "xen-ops.h"
+#include "mmu.h"
+
+void xen_pre_suspend(void)
+{
+        xen_start_info->store_mfn = mfn_to_pfn(xen_start_info->store_mfn);
+        xen_start_info->console.domU.mfn =
+                mfn_to_pfn(xen_start_info->console.domU.mfn);
+
+        BUG_ON(!irqs_disabled());
+
+        HYPERVISOR_shared_info = &xen_dummy_shared_info;
+        if (HYPERVISOR_update_va_mapping(fix_to_virt(FIX_PARAVIRT_BOOTMAP),
+                                         __pte_ma(0), 0))
+                BUG();
+}
+
+void xen_post_suspend(int suspend_cancelled)
+{
+        xen_setup_shared_info();
+
+        if (suspend_cancelled) {
+                xen_start_info->store_mfn =
+                        pfn_to_mfn(xen_start_info->store_mfn);
+                xen_start_info->console.domU.mfn =
+                        pfn_to_mfn(xen_start_info->console.domU.mfn);
+        } else {
+#ifdef CONFIG_SMP
+                xen_cpu_initialized_map = cpu_online_map;
+#endif
+                xen_vcpu_restore();
+                xen_timer_resume();
+        }
+
+}
+
diff --git a/arch/x86/xen/time.c b/arch/x86/xen/time.c
index 41e217503c96..685b77470fc3 100644
--- a/arch/x86/xen/time.c
+++ b/arch/x86/xen/time.c
@@ -197,8 +197,8 @@ unsigned long long xen_sched_clock(void)
 }
 
 
-/* Get the CPU speed from Xen */
-unsigned long xen_cpu_khz(void)
+/* Get the TSC speed from Xen */
+unsigned long xen_tsc_khz(void)
 {
         u64 xen_khz = 1000000ULL << 32;
         const struct pvclock_vcpu_time_info *info =
@@ -459,6 +459,19 @@ void xen_setup_cpu_clockevents(void)
         clockevents_register_device(&__get_cpu_var(xen_clock_events));
 }
 
+void xen_timer_resume(void)
+{
+        int cpu;
+
+        if (xen_clockevent != &xen_vcpuop_clockevent)
+                return;
+
+        for_each_online_cpu(cpu) {
+                if (HYPERVISOR_vcpu_op(VCPUOP_stop_periodic_timer, cpu, NULL))
+                        BUG();
+        }
+}
+
 __init void xen_time_init(void)
 {
         int cpu = smp_processor_id();
diff --git a/arch/x86/xen/xen-head.S b/arch/x86/xen/xen-head.S
index 6ec3b4f7719b..7c0cf6320a0a 100644
--- a/arch/x86/xen/xen-head.S
+++ b/arch/x86/xen/xen-head.S
@@ -7,6 +7,7 @@
 #include <linux/init.h>
 #include <asm/boot.h>
 #include <xen/interface/elfnote.h>
+#include <asm/xen/interface.h>
 
         __INIT
 ENTRY(startup_xen)
@@ -32,5 +33,9 @@ ENTRY(hypercall_page)
         ELFNOTE(Xen, XEN_ELFNOTE_FEATURES,       .asciz "!writable_page_tables|pae_pgdir_above_4gb")
         ELFNOTE(Xen, XEN_ELFNOTE_PAE_MODE,       .asciz "yes")
         ELFNOTE(Xen, XEN_ELFNOTE_LOADER,         .asciz "generic")
+        ELFNOTE(Xen, XEN_ELFNOTE_L1_MFN_VALID,
+                .quad _PAGE_PRESENT; .quad _PAGE_PRESENT)
+        ELFNOTE(Xen, XEN_ELFNOTE_SUSPEND_CANCEL, .long 1)
+        ELFNOTE(Xen, XEN_ELFNOTE_HV_START_LOW,   .long __HYPERVISOR_VIRT_START)
 
 #endif /*CONFIG_XEN */
diff --git a/arch/x86/xen/xen-ops.h b/arch/x86/xen/xen-ops.h
index f1063ae08037..d852ddbb3448 100644
--- a/arch/x86/xen/xen-ops.h
+++ b/arch/x86/xen/xen-ops.h
@@ -9,26 +9,35 @@
 extern const char xen_hypervisor_callback[];
 extern const char xen_failsafe_callback[];
 
+struct trap_info;
 void xen_copy_trap_info(struct trap_info *traps);
 
 DECLARE_PER_CPU(unsigned long, xen_cr3);
 DECLARE_PER_CPU(unsigned long, xen_current_cr3);
 
 extern struct start_info *xen_start_info;
+extern struct shared_info xen_dummy_shared_info;
 extern struct shared_info *HYPERVISOR_shared_info;
 
+void xen_setup_mfn_list_list(void);
+void xen_setup_shared_info(void);
+
 char * __init xen_memory_setup(void);
 void __init xen_arch_setup(void);
 void __init xen_init_IRQ(void);
 void xen_enable_sysenter(void);
+void xen_vcpu_restore(void);
+
+void __init xen_build_dynamic_phys_to_machine(void);
 
 void xen_setup_timer(int cpu);
 void xen_setup_cpu_clockevents(void);
-unsigned long xen_cpu_khz(void);
+unsigned long xen_tsc_khz(void);
 void __init xen_time_init(void);
 unsigned long xen_get_wallclock(void);
 int xen_set_wallclock(unsigned long time);
 unsigned long long xen_sched_clock(void);
+void xen_timer_resume(void);
 
 irqreturn_t xen_debug_interrupt(int irq, void *dev_id);
 
@@ -54,6 +63,8 @@ int xen_smp_call_function_single(int cpu, void (*func) (void *info), void *info,
 int xen_smp_call_function_mask(cpumask_t mask, void (*func)(void *),
                                void *info, int wait);
 
+extern cpumask_t xen_cpu_initialized_map;
+
 
 /* Declare an asm function, along with symbols needed to make it
    inlineable */