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authorJacob Pan <jacob.jun.pan@intel.com>2010-02-12 08:01:12 -0500
committerH. Peter Anvin <hpa@zytor.com>2010-02-24 14:01:33 -0500
commit3746c6b6e26b8ad605f11b43e54acb3481d40980 (patch)
tree7378b6580a6ef9122b9f38ddac578a26b2b1c50e /arch
parentbb24c4716185f6e116c440462c65c1f56649183b (diff)
x86, mrst: Platform clock setup code
Add Moorestown platform clock setup code to the x86_init abstraction. Signed-off-by: Jacob Pan <jacob.jun.pan@intel.com> LKML-Reference: <43F901BD926A4E43B106BF17856F0755A318D2D4@orsmsx508.amr.corp.intel.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/x86/kernel/mrst.c53
1 files changed, 53 insertions, 0 deletions
diff --git a/arch/x86/kernel/mrst.c b/arch/x86/kernel/mrst.c
index b7fa049c826c..0aad8670858e 100644
--- a/arch/x86/kernel/mrst.c
+++ b/arch/x86/kernel/mrst.c
@@ -23,6 +23,7 @@
23#include <asm/mrst.h> 23#include <asm/mrst.h>
24#include <asm/io.h> 24#include <asm/io.h>
25#include <asm/i8259.h> 25#include <asm/i8259.h>
26#include <asm/apb_timer.h>
26 27
27static u32 sfi_mtimer_usage[SFI_MTMR_MAX_NUM]; 28static u32 sfi_mtimer_usage[SFI_MTMR_MAX_NUM];
28static struct sfi_timer_table_entry sfi_mtimer_array[SFI_MTMR_MAX_NUM]; 29static struct sfi_timer_table_entry sfi_mtimer_array[SFI_MTMR_MAX_NUM];
@@ -166,12 +167,56 @@ int __init sfi_parse_mrtc(struct sfi_table_header *table)
166 return 0; 167 return 0;
167} 168}
168 169
170/*
171 * the secondary clock in Moorestown can be APBT or LAPIC clock, default to
172 * APBT but cmdline option can also override it.
173 */
174static void __cpuinit mrst_setup_secondary_clock(void)
175{
176 /* restore default lapic clock if disabled by cmdline */
177 if (disable_apbt_percpu)
178 return setup_secondary_APIC_clock();
179 apbt_setup_secondary_clock();
180}
181
182static unsigned long __init mrst_calibrate_tsc(void)
183{
184 unsigned long flags, fast_calibrate;
185
186 local_irq_save(flags);
187 fast_calibrate = apbt_quick_calibrate();
188 local_irq_restore(flags);
189
190 if (fast_calibrate)
191 return fast_calibrate;
192
193 return 0;
194}
195
196void __init mrst_time_init(void)
197{
198 sfi_table_parse(SFI_SIG_MTMR, NULL, NULL, sfi_parse_mtmr);
199 pre_init_apic_IRQ0();
200 apbt_time_init();
201}
202
169void __init mrst_rtc_init(void) 203void __init mrst_rtc_init(void)
170{ 204{
171 sfi_table_parse(SFI_SIG_MRTC, NULL, NULL, sfi_parse_mrtc); 205 sfi_table_parse(SFI_SIG_MRTC, NULL, NULL, sfi_parse_mrtc);
172} 206}
173 207
174/* 208/*
209 * if we use per cpu apb timer, the bootclock already setup. if we use lapic
210 * timer and one apbt timer for broadcast, we need to set up lapic boot clock.
211 */
212static void __init mrst_setup_boot_clock(void)
213{
214 pr_info("%s: per cpu apbt flag %d \n", __func__, disable_apbt_percpu);
215 if (disable_apbt_percpu)
216 setup_boot_APIC_clock();
217};
218
219/*
175 * Moorestown specific x86_init function overrides and early setup 220 * Moorestown specific x86_init function overrides and early setup
176 * calls. 221 * calls.
177 */ 222 */
@@ -180,6 +225,14 @@ void __init x86_mrst_early_setup(void)
180 x86_init.resources.probe_roms = x86_init_noop; 225 x86_init.resources.probe_roms = x86_init_noop;
181 x86_init.resources.reserve_resources = x86_init_noop; 226 x86_init.resources.reserve_resources = x86_init_noop;
182 227
228 x86_init.timers.timer_init = mrst_time_init;
229 x86_init.timers.setup_percpu_clockev = mrst_setup_boot_clock;
230
231 x86_init.irqs.pre_vector_init = x86_init_noop;
232
233 x86_cpuinit.setup_percpu_clockev = mrst_setup_secondary_clock;
234
235 x86_platform.calibrate_tsc = mrst_calibrate_tsc;
183 x86_init.pci.init = pci_mrst_init; 236 x86_init.pci.init = pci_mrst_init;
184 x86_init.pci.fixup_irqs = x86_init_noop; 237 x86_init.pci.fixup_irqs = x86_init_noop;
185 238