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authorRobert Richter <robert.richter@amd.com>2009-01-08 09:39:49 -0500
committerRobert Richter <robert.richter@amd.com>2009-01-08 09:52:19 -0500
commit25006644e6042aab4bb7cdc4bfc5777cd3141df7 (patch)
tree500d98c1a0467148752249f7577d9d0839023544 /arch
parent883823291d22e06736f1056da6d8303291d6bbf9 (diff)
powerpc/oprofile: fix whitespaces in op_model_cell.c
Signed-off-by: Robert Richter <robert.richter@amd.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/oprofile/op_model_cell.c24
1 files changed, 11 insertions, 13 deletions
diff --git a/arch/powerpc/oprofile/op_model_cell.c b/arch/powerpc/oprofile/op_model_cell.c
index ff96cbfb89bb..ae06c6236d9c 100644
--- a/arch/powerpc/oprofile/op_model_cell.c
+++ b/arch/powerpc/oprofile/op_model_cell.c
@@ -355,13 +355,13 @@ static void set_pm_event(u32 ctr, int event, u32 unit_mask)
355 for (i = 0; i < NUM_DEBUG_BUS_WORDS; i++) { 355 for (i = 0; i < NUM_DEBUG_BUS_WORDS; i++) {
356 if (bus_word & (1 << i)) { 356 if (bus_word & (1 << i)) {
357 pm_regs.debug_bus_control |= 357 pm_regs.debug_bus_control |=
358 (bus_type << (30 - (2 * i))); 358 (bus_type << (30 - (2 * i)));
359 359
360 for (j = 0; j < NUM_INPUT_BUS_WORDS; j++) { 360 for (j = 0; j < NUM_INPUT_BUS_WORDS; j++) {
361 if (input_bus[j] == 0xff) { 361 if (input_bus[j] == 0xff) {
362 input_bus[j] = i; 362 input_bus[j] = i;
363 pm_regs.group_control |= 363 pm_regs.group_control |=
364 (i << (30 - (2 * j))); 364 (i << (30 - (2 * j)));
365 365
366 break; 366 break;
367 } 367 }
@@ -503,7 +503,7 @@ static void cell_virtual_cntr(unsigned long data)
503 cbe_disable_pm_interrupts(cpu); 503 cbe_disable_pm_interrupts(cpu);
504 for (i = 0; i < num_counters; i++) { 504 for (i = 0; i < num_counters; i++) {
505 per_cpu(pmc_values, cpu + prev_hdw_thread)[i] 505 per_cpu(pmc_values, cpu + prev_hdw_thread)[i]
506 = cbe_read_ctr(cpu, i); 506 = cbe_read_ctr(cpu, i);
507 507
508 if (per_cpu(pmc_values, cpu + next_hdw_thread)[i] 508 if (per_cpu(pmc_values, cpu + next_hdw_thread)[i]
509 == 0xFFFFFFFF) 509 == 0xFFFFFFFF)
@@ -639,7 +639,7 @@ static void spu_evnt_swap(unsigned long data)
639 cbe_disable_pm_interrupts(cpu); 639 cbe_disable_pm_interrupts(cpu);
640 640
641 spu_pm_cnt[cur_phys_spu] 641 spu_pm_cnt[cur_phys_spu]
642 = cbe_read_ctr(cpu, 0); 642 = cbe_read_ctr(cpu, 0);
643 643
644 /* restore previous count for the next spu to sample */ 644 /* restore previous count for the next spu to sample */
645 /* NOTE, hardware issue, counter will not start if the 645 /* NOTE, hardware issue, counter will not start if the
@@ -658,9 +658,8 @@ static void spu_evnt_swap(unsigned long data)
658 */ 658 */
659 ret = pm_rtas_activate_signals(cbe_cpu_to_node(cpu), 3); 659 ret = pm_rtas_activate_signals(cbe_cpu_to_node(cpu), 3);
660 if (ret) 660 if (ret)
661 printk(KERN_ERR 661 printk(KERN_ERR "%s: pm_rtas_activate_signals failed, "
662 "%s: pm_rtas_activate_signals failed, SPU event swap\n", 662 "SPU event swap\n", __func__);
663 __func__);
664 663
665 /* clear the trace buffer, don't want to take PC for 664 /* clear the trace buffer, don't want to take PC for
666 * previous SPU*/ 665 * previous SPU*/
@@ -1316,7 +1315,7 @@ static int cell_global_start_spu_cycles(struct op_counter_config *ctr)
1316 1315
1317 /* start profiling */ 1316 /* start profiling */
1318 ret = rtas_call(spu_rtas_token, 3, 1, NULL, subfunc, 1317 ret = rtas_call(spu_rtas_token, 3, 1, NULL, subfunc,
1319 cbe_cpu_to_node(cpu), lfsr_value); 1318 cbe_cpu_to_node(cpu), lfsr_value);
1320 1319
1321 if (unlikely(ret != 0)) { 1320 if (unlikely(ret != 0)) {
1322 printk(KERN_ERR 1321 printk(KERN_ERR
@@ -1397,7 +1396,7 @@ static int cell_global_start_spu_events(struct op_counter_config *ctr)
1397 */ 1396 */
1398 start_spu_event_swap(); 1397 start_spu_event_swap();
1399 start_spu_profiling_events(); 1398 start_spu_profiling_events();
1400 oprofile_running = 1; 1399 oprofile_running = 1;
1401 smp_wmb(); 1400 smp_wmb();
1402 1401
1403 return rtn; 1402 return rtn;
@@ -1422,8 +1421,7 @@ static int cell_global_start_ppu(struct op_counter_config *ctr)
1422 if (ctr_enabled & (1 << i)) { 1421 if (ctr_enabled & (1 << i)) {
1423 cbe_write_ctr(cpu, i, reset_value[i]); 1422 cbe_write_ctr(cpu, i, reset_value[i]);
1424 enable_ctr(cpu, i, pm_regs.pm07_cntrl); 1423 enable_ctr(cpu, i, pm_regs.pm07_cntrl);
1425 interrupt_mask |= 1424 interrupt_mask |= CBE_PM_CTR_OVERFLOW_INTR(i);
1426 CBE_PM_CTR_OVERFLOW_INTR(i);
1427 } else { 1425 } else {
1428 /* Disable counter */ 1426 /* Disable counter */
1429 cbe_write_pm07_control(cpu, i, 0); 1427 cbe_write_pm07_control(cpu, i, 0);
@@ -1517,13 +1515,13 @@ static void cell_handle_interrupt_spu(struct pt_regs *regs,
1517 trace_entry = 0xfedcba; 1515 trace_entry = 0xfedcba;
1518 last_trace_buffer = 0xdeadbeaf; 1516 last_trace_buffer = 0xdeadbeaf;
1519 1517
1520 if ((oprofile_running == 1) && (interrupt_mask != 0)) { 1518 if ((oprofile_running == 1) && (interrupt_mask != 0)) {
1521 /* disable writes to trace buff */ 1519 /* disable writes to trace buff */
1522 cbe_write_pm(cpu, pm_interval, 0); 1520 cbe_write_pm(cpu, pm_interval, 0);
1523 1521
1524 /* only have one perf cntr being used, cntr 0 */ 1522 /* only have one perf cntr being used, cntr 0 */
1525 if ((interrupt_mask & CBE_PM_CTR_OVERFLOW_INTR(0)) 1523 if ((interrupt_mask & CBE_PM_CTR_OVERFLOW_INTR(0))
1526 && ctr[0].enabled) 1524 && ctr[0].enabled)
1527 /* The SPU PC values will be read 1525 /* The SPU PC values will be read
1528 * from the trace buffer, reset counter 1526 * from the trace buffer, reset counter
1529 */ 1527 */